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<title>user/sven/linux.git/include/uapi/linux/kvm.h, branch v3.11.1</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v3.11.1</id>
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<updated>2013-07-03T17:31:38Z</updated>
<entry>
<title>Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64</title>
<updated>2013-07-03T17:31:38Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2013-07-03T17:31:38Z</published>
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<id>urn:sha1:1873e50028ce87dd9014049c86d71a898fa02166</id>
<content type='text'>
Pull ARM64 updates from Catalin Marinas:
 "Main features:
   - KVM and Xen ports to AArch64
   - Hugetlbfs and transparent huge pages support for arm64
   - Applied Micro X-Gene Kconfig entry and dts file
   - Cache flushing improvements

  For arm64 huge pages support, there are x86 changes moving part of
  arch/x86/mm/hugetlbpage.c into mm/hugetlb.c to be re-used by arm64"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: (66 commits)
  arm64: Add initial DTS for APM X-Gene Storm SOC and APM Mustang board
  arm64: Add defines for APM ARMv8 implementation
  arm64: Enable APM X-Gene SOC family in the defconfig
  arm64: Add Kconfig option for APM X-Gene SOC family
  arm64/Makefile: provide vdso_install target
  ARM64: mm: THP support.
  ARM64: mm: Raise MAX_ORDER for 64KB pages and THP.
  ARM64: mm: HugeTLB support.
  ARM64: mm: Move PTE_PROT_NONE bit.
  ARM64: mm: Make PAGE_NONE pages read only and no-execute.
  ARM64: mm: Restore memblock limit when map_mem finished.
  mm: thp: Correct the HPAGE_PMD_ORDER check.
  x86: mm: Remove general hugetlb code from x86.
  mm: hugetlb: Copy general hugetlb code from x86 to mm.
  x86: mm: Remove x86 version of huge_pmd_share.
  mm: hugetlb: Copy huge_pmd_share from x86 to mm.
  arm64: KVM: document kernel object mappings in HYP
  arm64: KVM: MAINTAINERS update
  arm64: KVM: userspace API documentation
  arm64: KVM: enable initialization of a 32bit vcpu
  ...
</content>
</entry>
<entry>
<title>arm64: KVM: enable initialization of a 32bit vcpu</title>
<updated>2013-06-12T15:42:18Z</updated>
<author>
<name>Marc Zyngier</name>
<email>marc.zyngier@arm.com</email>
</author>
<published>2013-02-07T10:46:46Z</published>
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<id>urn:sha1:0d854a60b1d7d39a37b25dd28f63cfa0df637b91</id>
<content type='text'>
Wire the init of a 32bit vcpu by allowing 32bit modes in pstate,
and providing sensible defaults out of reset state.

This feature is of course conditioned by the presence of 32bit
capability on the physical CPU, and is checked by the KVM_CAP_ARM_EL1_32BIT
capability.

Reviewed-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>kvm: Add definition of KVM_REG_MIPS</title>
<updated>2013-06-11T08:06:34Z</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2013-06-10T19:33:47Z</published>
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<id>urn:sha1:2a8fedd0c142d4328ab4667847e05afe17c3295c</id>
<content type='text'>
We use 0x7000000000000000ULL as 0x6000000000000000ULL is reserved for
ARM64.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Signed-off-by: Gleb Natapov &lt;gleb@redhat.com&gt;
</content>
</entry>
<entry>
<title>arm64: KVM: system register handling</title>
<updated>2013-06-07T13:03:36Z</updated>
<author>
<name>Marc Zyngier</name>
<email>marc.zyngier@arm.com</email>
</author>
<published>2012-12-10T16:15:34Z</published>
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<id>urn:sha1:7c8c5e6a9101ea57a1c2c9faff0917e79251a21e</id>
<content type='text'>
Provide 64bit system register handling, modeled after the cp15
handling for ARM.

Reviewed-by: Christopher Covington &lt;cov@codeaurora.org&gt;
Reviewed-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>KVM: PPC: Book3S: Add API for in-kernel XICS emulation</title>
<updated>2013-05-02T13:28:36Z</updated>
<author>
<name>Paul Mackerras</name>
<email>paulus@samba.org</email>
</author>
<published>2013-04-27T00:28:37Z</published>
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<id>urn:sha1:5975a2e0950291a6bfe9fd5880e7952ff87764be</id>
<content type='text'>
This adds the API for userspace to instantiate an XICS device in a VM
and connect VCPUs to it.  The API consists of a new device type for
the KVM_CREATE_DEVICE ioctl, a new capability KVM_CAP_IRQ_XICS, which
functions similarly to KVM_CAP_IRQ_MPIC, and the KVM_IRQ_LINE ioctl,
which is used to assert and deassert interrupt inputs of the XICS.

The XICS device has one attribute group, KVM_DEV_XICS_GRP_SOURCES.
Each attribute within this group corresponds to the state of one
interrupt source.  The attribute number is the same as the interrupt
source number.

This does not support irq routing or irqfd yet.

Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
Acked-by: David Gibson &lt;david@gibson.dropbear.id.au&gt;
Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>kvm: Allow build-time configuration of KVM device assignment</title>
<updated>2013-04-28T09:58:56Z</updated>
<author>
<name>Alex Williamson</name>
<email>alex.williamson@redhat.com</email>
</author>
<published>2013-04-16T19:49:18Z</published>
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<id>urn:sha1:2a5bab1004729f3302c776e53ee7c895b98bb1ce</id>
<content type='text'>
We hope to at some point deprecate KVM legacy device assignment in
favor of VFIO-based assignment.  Towards that end, allow legacy
device assignment to be deconfigured.

Signed-off-by: Alex Williamson &lt;alex.williamson@redhat.com&gt;
Reviewed-by: Alexander Graf &lt;agraf@suse.de&gt;
Acked-by: Michael S. Tsirkin &lt;mst@redhat.com&gt;
Signed-off-by: Gleb Natapov &lt;gleb@redhat.com&gt;
</content>
</entry>
<entry>
<title>KVM: PPC: Book3S: Add infrastructure to implement kernel-side RTAS calls</title>
<updated>2013-04-26T18:27:29Z</updated>
<author>
<name>Michael Ellerman</name>
<email>michael@ellerman.id.au</email>
</author>
<published>2013-04-17T20:30:00Z</published>
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<id>urn:sha1:8e591cb7204739efa8e15967ea334eb367039dde</id>
<content type='text'>
For pseries machine emulation, in order to move the interrupt
controller code to the kernel, we need to intercept some RTAS
calls in the kernel itself.  This adds an infrastructure to allow
in-kernel handlers to be registered for RTAS services by name.
A new ioctl, KVM_PPC_RTAS_DEFINE_TOKEN, then allows userspace to
associate token values with those service names.  Then, when the
guest requests an RTAS service with one of those token values, it
will be handled by the relevant in-kernel handler rather than being
passed up to userspace as at present.

Signed-off-by: Michael Ellerman &lt;michael@ellerman.id.au&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
[agraf: fix warning]
Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>kvm/ppc/mpic: add KVM_CAP_IRQ_MPIC</title>
<updated>2013-04-26T18:27:24Z</updated>
<author>
<name>Scott Wood</name>
<email>scottwood@freescale.com</email>
</author>
<published>2013-04-12T14:08:47Z</published>
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<id>urn:sha1:eb1e4f43e0f47f2655372c7d32c43db9711c278e</id>
<content type='text'>
Enabling this capability connects the vcpu to the designated in-kernel
MPIC.  Using explicit connections between vcpus and irqchips allows
for flexibility, but the main benefit at the moment is that it
simplifies the code -- KVM doesn't need vm-global state to remember
which MPIC object is associated with this vm, and it doesn't need to
care about ordering between irqchip creation and vcpu creation.

Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
[agraf: add stub functions for kvmppc_mpic_{dis,}connect_vcpu]
Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>kvm/ppc/mpic: in-kernel MPIC emulation</title>
<updated>2013-04-26T18:27:23Z</updated>
<author>
<name>Scott Wood</name>
<email>scottwood@freescale.com</email>
</author>
<published>2013-04-12T14:08:46Z</published>
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<id>urn:sha1:5df554ad5b7522ea62b0ff9d5be35183494efc21</id>
<content type='text'>
Hook the MPIC code up to the KVM interfaces, add locking, etc.

Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
[agraf: add stub function for kvmppc_mpic_set_epr, non-booke, 64bit]
Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>kvm: add device control API</title>
<updated>2013-04-26T18:27:20Z</updated>
<author>
<name>Scott Wood</name>
<email>scottwood@freescale.com</email>
</author>
<published>2013-04-12T14:08:42Z</published>
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<id>urn:sha1:852b6d57dc7fa378019786fa84727036e56839ea</id>
<content type='text'>
Currently, devices that are emulated inside KVM are configured in a
hardcoded manner based on an assumption that any given architecture
only has one way to do it.  If there's any need to access device state,
it is done through inflexible one-purpose-only IOCTLs (e.g.
KVM_GET/SET_LAPIC).  Defining new IOCTLs for every little thing is
cumbersome and depletes a limited numberspace.

This API provides a mechanism to instantiate a device of a certain
type, returning an ID that can be used to set/get attributes of the
device.  Attributes may include configuration parameters (e.g.
register base address), device state, operational commands, etc.  It
is similar to the ONE_REG API, except that it acts on devices rather
than vcpus.

Both device types and individual attributes can be tested without having
to create the device or get/set the attribute, without the need for
separately managing enumerated capabilities.

Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
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