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<title>user/sven/linux.git/kernel/irq/Makefile, branch stable/4.7.y</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=stable%2F4.7.y</id>
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<updated>2016-02-25T09:56:56Z</updated>
<entry>
<title>genirq: Add a new generic IPI reservation code to irq core</title>
<updated>2016-02-25T09:56:56Z</updated>
<author>
<name>Qais Yousef</name>
<email>qais.yousef@imgtec.com</email>
</author>
<published>2015-12-08T13:20:19Z</published>
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<id>urn:sha1:d17bf24e695290d3fe7943aca52ab48098a10653</id>
<content type='text'>
Add a generic mechanism to dynamically allocate an IPI. Depending on the
underlying implementation this creates either a single Linux irq or a
consective range of Linux irqs. The Linux irq is used later to send IPIs to
other CPUs.

[ tglx: Massaged the code and removed the 'consecutive mask' restriction for
  	the single IRQ case ]

Signed-off-by: Qais Yousef &lt;qais.yousef@imgtec.com&gt;
Cc: &lt;jason@lakedaemon.net&gt;
Cc: &lt;marc.zyngier@arm.com&gt;
Cc: &lt;jiang.liu@linux.intel.com&gt;
Cc: &lt;ralf@linux-mips.org&gt;
Cc: &lt;linux-mips@linux-mips.org&gt;
Cc: &lt;lisa.parratt@imgtec.com&gt;
Cc: Qais Yousef &lt;qsyousef@gmail.com&gt;
Link: http://lkml.kernel.org/r/1449580830-23652-9-git-send-email-qais.yousef@imgtec.com
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
</entry>
<entry>
<title>genirq: Introduce generic irq migration for cpu hotunplug</title>
<updated>2015-10-01T12:51:15Z</updated>
<author>
<name>Yang Yingliang</name>
<email>yangyingliang@huawei.com</email>
</author>
<published>2015-09-24T09:32:13Z</published>
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<id>urn:sha1:f1e0bb0ad473a32d1b7e6d285ae9f7e47710bb5e</id>
<content type='text'>
ARM and ARM64 have almost identical code for migrating interrupts on
cpu hotunplug. Provide a generic version which can be used by both.

The new code addresses a shortcoming in the ARM[64] variants which
fails to update the affinity change in some cases. The solution for
this is to use the core function irq_do_set_affinity() instead of open
coding it.

[ tglx: Added copyright notice and license boilerplate. Rewrote
  	subject and changelog. ]

Signed-off-by: Yang Yingliang &lt;yangyingliang@huawei.com&gt;
Acked-by: Russell King - ARM Linux &lt;linux@arm.linux.org.uk&gt;
Cc: Jiang Liu &lt;jiang.liu@linux.intel.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: Will Deacon &lt;will.deacon@arm.com&gt;
Cc: Hanjun Guo &lt;hanjun.guo@linaro.org&gt;
Cc: &lt;linux-arm-kernel@lists.infradead.org&gt;
Link: http://lkml.kernel.org/r/1443087135-17044-2-git-send-email-yangyingliang@huawei.com
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
</entry>
<entry>
<title>genirq: Add generic msi irq domain support</title>
<updated>2014-11-23T12:01:47Z</updated>
<author>
<name>Jiang Liu</name>
<email>jiang.liu@linux.intel.com</email>
</author>
<published>2014-11-12T10:39:03Z</published>
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<id>urn:sha1:f3cf8bb0d6c3c11ddedf01f02f856f2ae8c33aa4</id>
<content type='text'>
Implement the basic functions for MSI interrupt support with
hierarchical interrupt domains.

[ tglx: Extracted and combined from several patches ]

Signed-off-by: Jiang Liu &lt;jiang.liu@linux.intel.com&gt;
Cc: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Cc: Grant Likely &lt;grant.likely@linaro.org&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Cc: Yingjoe Chen &lt;yingjoe.chen@mediatek.com&gt;
Cc: Yijing Wang &lt;wangyijing@huawei.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
</entry>
<entry>
<title>irq: add irq_domain translation infrastructure</title>
<updated>2011-07-28T07:32:04Z</updated>
<author>
<name>Grant Likely</name>
<email>grant.likely@secretlab.ca</email>
</author>
<published>2011-07-26T09:19:06Z</published>
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<id>urn:sha1:08a543ad33fc188650801bd36eed4ffe272643e1</id>
<content type='text'>
This patch adds irq_domain infrastructure for translating from
hardware irq numbers to linux irqs.  This is particularly important
for architectures adding device tree support because the current
implementation (excluding PowerPC and SPARC) cannot handle
translation for more than a single interrupt controller.  irq_domain
supports device tree translation for any number of interrupt
controllers.

This patch converts x86, Microblaze, ARM and MIPS to use irq_domain
for device tree irq translation.  x86 is untested beyond compiling it,
irq_domain is enabled for MIPS and Microblaze, but the old behaviour is
preserved until the core code is modified to actually register an
irq_domain yet.  On ARM it works and is required for much of the new
ARM device tree board support.

PowerPC has /not/ been converted to use this new infrastructure.  It
is still missing some features before it can replace the virq
infrastructure already in powerpc (see documentation on
irq_domain_map/unmap for details).  Followup patches will add the
missing pieces and migrate PowerPC to use irq_domain.

SPARC has its own method of managing interrupts from the device tree
and is unaffected by this change.

Acked-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Signed-off-by: Grant Likely &lt;grant.likely@secretlab.ca&gt;
</content>
</entry>
<entry>
<title>genirq: Make generic irq chip depend on CONFIG_GENERIC_IRQ_CHIP</title>
<updated>2011-05-02T16:16:22Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2011-05-02T16:16:22Z</published>
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<id>urn:sha1:c42321c76b0ef472e3bae4bfcb0f46ab19e038ef</id>
<content type='text'>
Only compile it in when there are users.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: linux-arm-kernel@lists.infradead.org
</content>
</entry>
<entry>
<title>genirq: Implement a generic interrupt chip</title>
<updated>2011-04-23T13:56:24Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2011-04-03T09:42:53Z</published>
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<id>urn:sha1:7d8280624797bbe2f5170bd3c85c75a8c9c74242</id>
<content type='text'>
Implement a generic interrupt chip, which is configurable and is able
to handle the most common irq chip implementations.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: linux-arm-kernel@lists.infradead.org
Tested-by: H Hartley Sweeten &lt;hsweeten@visionengravers.com&gt;
Tested-by: Tony Lindgren &lt;tony@atomide.com&gt;
Tested-by; Kevin Hilman &lt;khilman@ti.com&gt;
</content>
</entry>
<entry>
<title>genirq: Remove the now unused sparse irq leftovers</title>
<updated>2010-10-12T14:53:44Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2010-09-29T15:18:47Z</published>
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<id>urn:sha1:78f90d91f395cd0dc1ef3f21e0c5cd6fd50d202c</id>
<content type='text'>
The move_irq_desc() function was only used due to the problem that the
allocator did not free the old descriptors. So the descriptors had to
be moved in create_irq_nr(). That's history.

The code would have never been able to move active interrupt
descriptors on affinity settings. That can be done in a completely
different way w/o all this horror.

Remove all of it.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
<entry>
<title>genirq: Distangle kernel/irq/handle.c</title>
<updated>2010-10-12T14:39:05Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2010-09-22T15:09:43Z</published>
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<id>urn:sha1:3795de236d67a05994a1a12759db9d4dd9ffc42c</id>
<content type='text'>
kernel/irq/handle.c has become a dumpground for random code in random
order. Split out the irq descriptor management and the dummy irq_chip
implementation into separate files. Cleanup the include maze while at
it.

No code change.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
<entry>
<title>x86/irq: use move_irq_desc() in create_irq_nr()</title>
<updated>2009-05-01T17:01:12Z</updated>
<author>
<name>Yinghai Lu</name>
<email>yinghai@kernel.org</email>
</author>
<published>2009-04-30T08:17:50Z</published>
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<id>urn:sha1:15e957d08dd4a841359cfec59ecb74041e0097aa</id>
<content type='text'>
move_irq_desc() will try to move irq_desc to the home node if
the allocated one is not correct, in create_irq_nr().

( This can happen on devices that are on different nodes that
  are using MSI, when drivers are loaded and unloaded randomly. )

v2: fix non-smp build
v3: add NUMA_IRQ_DESC to eliminate #ifdefs

[ Impact: improve irq descriptor locality on NUMA systems ]

Signed-off-by: Yinghai Lu &lt;yinghai@kernel.org&gt;
Cc: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Cc: Suresh Siddha &lt;suresh.b.siddha@intel.com&gt;
Cc: "Eric W. Biederman" &lt;ebiederm@xmission.com&gt;
Cc: Rusty Russell &lt;rusty@rustcorp.com.au&gt;
LKML-Reference: &lt;49F95EAE.2050903@kernel.org&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
<entry>
<title>x86/irq: remove leftover code from NUMA_MIGRATE_IRQ_DESC</title>
<updated>2009-04-28T10:21:15Z</updated>
<author>
<name>Yinghai Lu</name>
<email>yinghai@kernel.org</email>
</author>
<published>2009-04-28T00:58:23Z</published>
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<id>urn:sha1:fcef5911c7ea89b80d5bfc727f402f37c9eefd57</id>
<content type='text'>
The original feature of migrating irq_desc dynamic was too fragile
and was causing problems: it caused crashes on systems with lots of
cards with MSI-X when user-space irq-balancer was enabled.

We now have new patches that create irq_desc according to device
numa node. This patch removes the leftover bits of the dynamic balancer.

[ Impact: remove dead code ]

Signed-off-by: Yinghai Lu &lt;yinghai@kernel.org&gt;
Cc: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Cc: Suresh Siddha &lt;suresh.b.siddha@intel.com&gt;
Cc: "Eric W. Biederman" &lt;ebiederm@xmission.com&gt;
Cc: Rusty Russell &lt;rusty@rustcorp.com.au&gt;
LKML-Reference: &lt;49F654AF.8000808@kernel.org&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
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