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<title>user/sven/linux.git/lib/raid6/test, branch v4.9.191</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2018-11-27T15:09:39Z</updated>
<entry>
<title>lib/raid6: Fix arm64 test build</title>
<updated>2018-11-27T15:09:39Z</updated>
<author>
<name>Jeremy Linton</name>
<email>jeremy.linton@arm.com</email>
</author>
<published>2018-11-06T00:14:41Z</published>
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<id>urn:sha1:d05e26d49ed30201299ca60eec2de3872d43a3d2</id>
<content type='text'>
[ Upstream commit 313a06e636808387822af24c507cba92703568b1 ]

The lib/raid6/test fails to build the neon objects
on arm64 because the correct machine type is 'aarch64'.

Once this is correctly enabled, the neon recovery objects
need to be added to the build.

Reviewed-by: Ard Biesheuvel &lt;ard.biesheuvel@linaro.org&gt;
Signed-off-by: Jeremy Linton &lt;jeremy.linton@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>raid6/test/test.c: bug fix: Specify aligned(alignment) attributes to the char arrays</title>
<updated>2016-09-26T23:18:21Z</updated>
<author>
<name>Gayatri Kammela</name>
<email>gayatri.kammela@intel.com</email>
</author>
<published>2016-09-26T21:37:38Z</published>
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<id>urn:sha1:099b548c429217a8306adbd1552d326615c9b903</id>
<content type='text'>
Specifying the aligned attributes to the char data[NDISKS][PAGE_SIZE],
char recovi[PAGE_SIZE] and char recovi[PAGE_SIZE] arrays, so that all
malloc memory is page boundary aligned.

Without these alignment attributes, the test causes a segfault in
userspace when the NDISKS are changed to 4 from 16.

The RAID stripes will be page aligned anyway, so we want to test what
the kernel actually will execute.

Cc: H. Peter Anvin &lt;hpa@zytor.com&gt;
Cc: Yu-cheng Yu &lt;yu-cheng.yu@intel.com&gt;
Signed-off-by: Gayatri Kammela &lt;gayatri.kammela@intel.com&gt;
Reviewed-by: H. Peter Anvin &lt;hpa@linux.intel.com&gt;
Signed-off-by: Shaohua Li &lt;shli@fb.com&gt;
</content>
</entry>
<entry>
<title>lib/raid6/test/Makefile: Add avx512 gen_syndrome and recovery functions</title>
<updated>2016-09-21T16:09:44Z</updated>
<author>
<name>Gayatri Kammela</name>
<email>gayatri.kammela@intel.com</email>
</author>
<published>2016-08-13T01:03:21Z</published>
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<id>urn:sha1:161db5d165123a72792e2687ecfd8de146dbae1a</id>
<content type='text'>
Adding avx512 gen_syndrome and recovery functions so as to allow code to
be compiled and tested successfully in userspace.

This patch is tested in userspace and improvement in performace is
observed.

Cc: H. Peter Anvin &lt;hpa@zytor.com&gt;
Cc: Jim Kukunas &lt;james.t.kukunas@linux.intel.com&gt;
Cc: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Megha Dey &lt;megha.dey@linux.intel.com&gt;
Signed-off-by: Gayatri Kammela &lt;gayatri.kammela@intel.com&gt;
Reviewed-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Shaohua Li &lt;shli@fb.com&gt;
</content>
</entry>
<entry>
<title>md/raid6 algorithms: improve test program</title>
<updated>2015-04-21T22:00:42Z</updated>
<author>
<name>Markus Stockhausen</name>
<email>stockhausen@collogia.de</email>
</author>
<published>2014-12-15T01:57:04Z</published>
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<id>urn:sha1:7e92e1d7629b00578cef22b1f4c6ada726663701</id>
<content type='text'>
It is always helpful to have a test tool in place if we implement
new data critical algorithms. So add some test routines to the raid6
checker that can prove if the new xor_syndrome() works as expected.

Run through all permutations of start/stop pages per algorithm and
simulate a xor_syndrome() assisted rmw run. After each rmw check if
the recovery algorithm still confirms that the stripe is fine.

Signed-off-by: Markus Stockhausen &lt;stockhausen@collogia.de&gt;
Signed-off-by: NeilBrown &lt;neilb@suse.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'md/3.12' of git://neil.brown.name/md</title>
<updated>2013-09-10T20:03:41Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2013-09-10T20:03:41Z</published>
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<id>urn:sha1:4d7696f1b05f4aeb586c74868fe3da2731daca4b</id>
<content type='text'>
Pull md update from Neil Brown:
 "Headline item is multithreading for RAID5 so that more IO/sec can be
  supported on fast (SSD) devices.  Also TILE-Gx SIMD suppor for RAID6
  calculations and an assortment of bug fixes"

* tag 'md/3.12' of git://neil.brown.name/md:
  raid5: only wakeup necessary threads
  md/raid5: flush out all pending requests before proceeding with reshape.
  md/raid5: use seqcount to protect access to shape in make_request.
  raid5: sysfs entry to control worker thread number
  raid5: offload stripe handle to workqueue
  raid5: fix stripe release order
  raid5: make release_stripe lockless
  md: avoid deadlock when dirty buffers during md_stop.
  md: Don't test all of mddev-&gt;flags at once.
  md: Fix apparent cut-and-paste error in super_90_validate
  raid6/test: replace echo -e with printf
  RAID: add tilegx SIMD implementation of raid6
  md: fix safe_mode buglet.
  md: don't call md_allow_write in get_bitmap_file.
</content>
</entry>
<entry>
<title>raid6/test: replace echo -e with printf</title>
<updated>2013-08-27T06:06:06Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2013-08-22T14:53:06Z</published>
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<id>urn:sha1:c28399b5943a24a214a44e973a3a8002fd36442d</id>
<content type='text'>
-e is a non-standard echo option, echo output is
implementation-dependent when it is used. Replace echo -e with printf as
suggested by POSIX echo manual.

Cc: NeilBrown &lt;neilb@suse.de&gt;
Cc: Jim Kukunas &lt;james.t.kukunas@linux.intel.com&gt;
Cc: "H. Peter Anvin" &lt;hpa@zytor.com&gt;
Cc: Yuanhan Liu &lt;yuanhan.liu@linux.intel.com&gt;
Acked-by: H. Peter Anvin &lt;hpa@zytor.com&gt;
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Signed-off-by: NeilBrown &lt;neilb@suse.de&gt;
</content>
</entry>
<entry>
<title>RAID: add tilegx SIMD implementation of raid6</title>
<updated>2013-08-27T06:05:50Z</updated>
<author>
<name>Ken Steele</name>
<email>ken@tilera.com</email>
</author>
<published>2013-08-07T16:39:56Z</published>
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<id>urn:sha1:ae77cbc1e7b90473a2b0963bce0e1eb163873214</id>
<content type='text'>
This change adds TILE-Gx SIMD instructions to the software raid
(md), modeling the Altivec implementation. This is only for Syndrome
generation; there is more that could be done to improve recovery,
as in the recent Intel SSE3 recovery implementation.

The code unrolls 8 times; this turns out to be the best on tilegx
hardware among the set 1, 2, 4, 8 or 16.  The code reads one
cache-line of data from each disk, stores P and Q then goes to the
next cache-line.

The test code in sys/linux/lib/raid6/test reports 2008 MB/s data
read rate for syndrome generation using 18 disks (16 data and 2
parity). It was 1512 MB/s before this SIMD optimizations. This is
running on 1 core with all the data in cache.

This is based on the paper The Mathematics of RAID-6.
(http://kernel.org/pub/linux/kernel/people/hpa/raid6.pdf).

Signed-off-by: Ken Steele &lt;ken@tilera.com&gt;
Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
Signed-off-by: NeilBrown &lt;neilb@suse.de&gt;
</content>
</entry>
<entry>
<title>lib/raid6: add ARM-NEON accelerated syndrome calculation</title>
<updated>2013-07-08T21:09:18Z</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ard.biesheuvel@linaro.org</email>
</author>
<published>2013-05-16T15:20:32Z</published>
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<id>urn:sha1:7d11965ddb9b9b1e0a5d13c58345ada1ccbc663b</id>
<content type='text'>
Rebased/reworked a patch contributed by Rob Herring that uses
NEON intrinsics to perform the RAID-6 syndrome calculations.
It uses the existing unroll.awk code to generate several
unrolled versions of which the best performing one is selected
at boot time.

Signed-off-by: Ard Biesheuvel &lt;ard.biesheuvel@linaro.org&gt;
Acked-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Cc: hpa@linux.intel.com
</content>
</entry>
<entry>
<title>lib/raid6: build proper files on corresponding arch</title>
<updated>2012-12-13T08:51:04Z</updated>
<author>
<name>Yuanhan Liu</name>
<email>yuanhan.liu@linux.intel.com</email>
</author>
<published>2012-11-30T21:10:40Z</published>
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<id>urn:sha1:4f8c55c5ad491dbc7b52ce08bb702ca39ce944cf</id>
<content type='text'>
sse and avx2 stuff only exist on x86 arch, and we don't need to build
altivec on x86. And we can do that at lib/raid6/Makefile.

Proposed-by: H. Peter Anvin &lt;hpa@zytor.com&gt;
Signed-off-by: Yuanhan Liu &lt;yuanhan.liu@linux.intel.com&gt;
Reviewed-by: H. Peter Anvin &lt;hpa@zytor.com&gt;
Signed-off-by: Jim Kukunas &lt;james.t.kukunas@linux.intel.com&gt;
Signed-off-by: NeilBrown &lt;neilb@suse.de&gt;
</content>
</entry>
<entry>
<title>lib/raid6: Add AVX2 optimized gen_syndrome functions</title>
<updated>2012-12-13T08:51:03Z</updated>
<author>
<name>Yuanhan Liu</name>
<email>yuanhan.liu@linux.intel.com</email>
</author>
<published>2012-11-30T21:10:39Z</published>
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<id>urn:sha1:2c935842bdb46f5f557426feb4d2bdfdad1aa5f9</id>
<content type='text'>
Add AVX2 optimized gen_syndrom functions, which is simply based on
sse2.c written by hpa.

Signed-off-by: Yuanhan Liu &lt;yuanhan.liu@linux.intel.com&gt;
Reviewed-by: H. Peter Anvin &lt;hpa@zytor.com&gt;
Signed-off-by: Jim Kukunas &lt;james.t.kukunas@linux.intel.com&gt;
Signed-off-by: NeilBrown &lt;neilb@suse.de&gt;
</content>
</entry>
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