user/sven/linux.git/scripts/Makefile.build, branch v5.0.16

Merge tag 'kbuild-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild

2018-12-29T20:03:17Z

Pull Kbuild updates from Masahiro Yamada: "Kbuild core: - remove unneeded $(call cc-option,...) switches - consolidate Clang compiler flags into CLANG_FLAGS - announce the deprecation of SUBDIRS - fix single target build for external module - simplify the dependencies of 'prepare' stage targets - allow fixdep to directly write to .*.cmd files - simplify dependency generation for CONFIG_TRIM_UNUSED_KSYMS - change if_changed_rule to accept multi-line recipe - move .SECONDARY special target to scripts/Kbuild.include - remove redundant 'set -e' - improve parallel execution for CONFIG_HEADERS_CHECK - misc cleanups Treewide fixes and cleanups - set Clang flags correctly for PowerPC boot images - fix UML build error with CONFIG_GCC_PLUGINS - remove unneeded patterns from .gitignore files - refactor firmware/Makefile - remove unneeded rules for *offsets.s - avoid unneeded regeneration of intermediate .s files - clean up ./Kbuild Modpost: - remove unused -M, -K options - fix false positive warnings about section mismatch - use simple devtable lookup instead of linker magic - misc cleanups Coccinelle: - relax boolinit.cocci checks for overall consistency - fix warning messages of boolinit.cocci Other tools: - improve -dirty check of scripts/setlocalversion - add a tool to generate compile_commands.json from .*.cmd files" * tag 'kbuild-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild: (51 commits) kbuild: remove unused cmd_gentimeconst kbuild: remove $(obj)/ prefixes in ./Kbuild treewide: add intermediate .s files to targets treewide: remove explicit rules for *offsets.s firmware: refactor firmware/Makefile firmware: remove unnecessary patterns from .gitignore scripts: remove unnecessary ihex2fw and check-lc_ctypes from .gitignore um: remove unused filechk_gen_header in Makefile scripts: add a tool to produce a compile_commands.json file kbuild: add -Werror=implicit-int flag unconditionally kbuild: add -Werror=strict-prototypes flag unconditionally kbuild: add -fno-PIE flag unconditionally scripts: coccinelle: Correct warning message scripts: coccinelle: only suggest true/false in files that already use them kbuild: handle part-of-module correctly for *.ll and *.symtypes kbuild: refactor part-of-module kbuild: refactor quiet_modtag kbuild: remove redundant quiet_modtag for $(obj-m) kbuild: refactor Makefile.asm-generic user/Makefile: Fix typo and capitalization in comment section ...

kbuild: handle part-of-module correctly for .ll and .symtypes

2018-12-16T15:33:43Z

The single targets *.ll and *.symtypes have never been treated as a module. Fix it. Signed-off-by: Masahiro Yamada

kbuild: refactor part-of-module

2018-12-16T15:33:43Z

Use $(foreach ...) to make it shorter. Signed-off-by: Masahiro Yamada

kbuild: refactor quiet_modtag

2018-12-16T15:33:42Z

part-of-module and quiet_modtag are set for the same targets. Define quiet_modtag based on part-of-module. Signed-off-by: Masahiro Yamada

kbuild: remove redundant quiet_modtag for $(obj-m)

2018-12-16T15:33:42Z

All objects in $(obj-m) are contained in $(real-obj-m) as well. It is true composite objects are only contained in $(obj-m), but [M] is hard-coded in quiet_cmd_link_multi-m. This line is redundant. Signed-off-by: Masahiro Yamada

kbuild: move .SECONDARY special target to Kbuild.include

2018-12-02T05:11:49Z

In commit 54a702f70589 ("kbuild: mark $(targets) as .SECONDARY and remove .PRECIOUS markers"), I missed one important feature of the .SECONDARY target: .SECONDARY with no prerequisites causes all targets to be treated as secondary. ... which agrees with the policy of Kbuild. Let's move it to scripts/Kbuild.include, with no prerequisites. Note: If an intermediate file is generated by $(call if_changed,...), you still need to add it to "targets" so its .*.cmd file is included. The arm/arm64 crypto files are generated by $(call cmd,shipped), so they do not need to be added to "targets", but need to be added to "clean-files" so "make clean" can properly clean them away. Signed-off-by: Masahiro Yamada

kbuild: remove redundant 'set -e' from cmd_* defines

2018-12-01T14:13:14Z

These three cmd_* are invoked in the $(call cmd,*) form. Now that 'set -e' moved to the 'cmd' macro, they do not need to explicitly give 'set -e'. Signed-off-by: Masahiro Yamada

kbuild: remove trailing semicolon from cmd_* passed to if_changed_rule

2018-12-01T14:13:14Z

With the change of rule_cc_o_c / rule_as_o_S in the last commit, each command is executed in a separate subshell. Rip off unneeded semicolons. Signed-off-by: Masahiro Yamada

kbuild: change if_changed_rule for multi-line recipe

2018-12-01T14:13:14Z

The 'define' ... 'endef' directive is useful to confine a series of shell commands into a single macro: define foo [action1] [action2] [action3] endif Each action is executed in a separate subshell. However, rule_cc_o_c and rule_as_o_S in scripts/Makefile.build are written as follows (with a trailing semicolon in each cmd_*): define rule_cc_o_c [action1] ; \ [action2] ; \ [action3] ; endef All shell commands are concatenated with '; \' so that it looks like a single command from the Makefile point of view. This does not exploit the benefits of 'define' ... 'endef' form because a single shell command can be more simply written, like this: rule_cc_o_c = \ [action1] ; \ [action2] ; \ [action3] ; I guess the intention for the command concatenation was to let the '@set -e' in if_changed_rule cover all the commands. We can improve the readability by moving '@set -e' to the 'cmd' macro. The combo of $(call echo-cmd,*) $(cmd_*) in rule_cc_o_c and rule_as_o_S have been replaced with $(call cmd,*). The trailing back-slashes have been removed. Here is a note about the performance: the commands in rule_cc_o_c and rule_as_o_S were previously executed all together in a single subshell, but now each line in a separate subshell. This means Make will spawn extra subshells [1]. I measured the build performance for x86_64_defconfig + CONFIG_MODVERSIONS + CONFIG_TRIM_UNUSED_KSYMS and I saw slight performance regression, but I believe code readability and maintainability wins. [1] Precisely, GNU Make may optimize this by executing the command directly instead of forking a subshell, if no shell special characters are found in the command line and omitting the subshell will not change the behavior. Signed-off-by: Masahiro Yamada

kbuild: simplify dependency generation for CONFIG_TRIM_UNUSED_KSYMS

2018-12-01T14:13:14Z

My main motivation of this commit is to clean up scripts/Kbuild.include and scripts/Makefile.build. Currently, CONFIG_TRIM_UNUSED_KSYMS works with a tricky gimmick; possibly exported symbols are detected by letting $(CPP) replace EXPORT_SYMBOL* with a special string '=== __KSYM_*===', which is post-processed by sed, and passed to fixdep. The extra preprocessing is costly, and hacking cmd_and_fixdep is ugly. I came up with a new way to find exported symbols; insert a dummy symbol __ksym_marker_* to each potentially exported symbol. Those dummy symbols are picked up by $(NM), post-processed by sed, then appended to .*.cmd files. I collected the post-process part to a new shell script scripts/gen_ksymdeps.sh for readability. The dummy symbols are put into the .discard.* section so that the linker script rips them off the final vmlinux or modules. A nice side-effect is building with CONFIG_TRIM_UNUSED_KSYMS will be much faster. Signed-off-by: Masahiro Yamada Reviewed-by: Nicolas Pitre