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| author | Olof Johansson <olof@lixom.net> | 2012-09-11 23:22:25 -0700 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2012-09-11 23:22:25 -0700 |
| commit | f46e374c1ea7fafce70a838f09fbd67de3e4d49f (patch) | |
| tree | e191e5316bdb8558bd3e2b0981c715bedd225ca7 /arch/c6x/include/asm/cache.h | |
| parent | a4d3621e0d3ecf191961dc9214e4a378a7186780 (diff) | |
| parent | eb8ca943bae2b84c3fc14dfd7a908cb334465fef (diff) | |
Merge branch 'boards' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards
* 'boards' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: marzen: enable thermal sensor
ARM: shmobile: marzen: fixup regulator id for smsc911x
ARM: shmobile: marzen: add SDHI0 support
+ sync to 3.6-rc4
Diffstat (limited to 'arch/c6x/include/asm/cache.h')
| -rw-r--r-- | arch/c6x/include/asm/cache.h | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h index 6d521d96d941..09c5a0f5f4d1 100644 --- a/arch/c6x/include/asm/cache.h +++ b/arch/c6x/include/asm/cache.h @@ -1,7 +1,7 @@ /* * Port on Texas Instruments TMS320C6x architecture * - * Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated + * Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) * * This program is free software; you can redistribute it and/or modify @@ -16,9 +16,14 @@ /* * Cache line size */ -#define L1D_CACHE_BYTES 64 -#define L1P_CACHE_BYTES 32 -#define L2_CACHE_BYTES 128 +#define L1D_CACHE_SHIFT 6 +#define L1D_CACHE_BYTES (1 << L1D_CACHE_SHIFT) + +#define L1P_CACHE_SHIFT 5 +#define L1P_CACHE_BYTES (1 << L1P_CACHE_SHIFT) + +#define L2_CACHE_SHIFT 7 +#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) /* * L2 used as cache @@ -29,7 +34,8 @@ * For practical reasons the L1_CACHE_BYTES defines should not be smaller than * the L2 line size */ -#define L1_CACHE_BYTES L2_CACHE_BYTES +#define L1_CACHE_SHIFT L2_CACHE_SHIFT +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) #define L2_CACHE_ALIGN_LOW(x) \ (((x) & ~(L2_CACHE_BYTES - 1))) |