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authorLinus Torvalds <torvalds@linux-foundation.org>2026-02-11 19:31:52 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2026-02-11 19:31:52 -0800
commit37a93dd5c49b5fda807fd204edf2547c3493319c (patch)
treece1ef5a642b9ea3d7242156438eb96dc5607a752 /drivers/net/ethernet/dnet.h
parent098b6e44cbaa2d526d06af90c862d13fb414a0ec (diff)
parent83310d613382f74070fc8b402f3f6c2af8439ead (diff)
Merge tag 'net-next-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextipvs/mainipvs/HEADipvs-next/mainipvs-next/HEADdavem/net-next/maindavem/net-next/HEAD
Pull networking updates from Paolo Abeni: "Core & protocols: - A significant effort all around the stack to guide the compiler to make the right choice when inlining code, to avoid unneeded calls for small helper and stack canary overhead in the fast-path. This generates better and faster code with very small or no text size increases, as in many cases the call generated more code than the actual inlined helper. - Extend AccECN implementation so that is now functionally complete, also allow the user-space enabling it on a per network namespace basis. - Add support for memory providers with large (above 4K) rx buffer. Paired with hw-gro, larger rx buffer sizes reduce the number of buffers traversing the stack, dincreasing single stream CPU usage by up to ~30%. - Do not add HBH header to Big TCP GSO packets. This simplifies the RX path, the TX path and the NIC drivers, and is possible because user-space taps can now interpret correctly such packets without the HBH hint. - Allow IPv6 routes to be configured with a gateway address that is resolved out of a different interface than the one specified, aligning IPv6 to IPv4 behavior. - Multi-queue aware sch_cake. This makes it possible to scale the rate shaper of sch_cake across multiple CPUs, while still enforcing a single global rate on the interface. - Add support for the nbcon (new buffer console) infrastructure to netconsole, enabling lock-free, priority-based console operations that are safer in crash scenarios. - Improve the TCP ipv6 output path to cache the flow information, saving cpu cycles, reducing cache line misses and stack use. - Improve netfilter packet tracker to resolve clashes for most protocols, avoiding unneeded drops on rare occasions. - Add IP6IP6 tunneling acceleration to the flowtable infrastructure. - Reduce tcp socket size by one cache line. - Notify neighbour changes atomically, avoiding inconsistencies between the notification sequence and the actual states sequence. - Add vsock namespace support, allowing complete isolation of vsocks across different network namespaces. - Improve xsk generic performances with cache-alignment-oriented optimizations. - Support netconsole automatic target recovery, allowing netconsole to reestablish targets when underlying low-level interface comes back online. Driver API: - Support for switching the working mode (automatic vs manual) of a DPLL device via netlink. - Introduce PHY ports representation to expose multiple front-facing media ports over a single MAC. - Introduce "rx-polarity" and "tx-polarity" device tree properties, to generalize polarity inversion requirements for differential signaling. - Add helper to create, prepare and enable managed clocks. Device drivers: - Add Huawei hinic3 PF etherner driver. - Add DWMAC glue driver for Motorcomm YT6801 PCIe ethernet controller. - Add ethernet driver for MaxLinear MxL862xx switches - Remove parallel-port Ethernet driver. - Convert existing driver timestamp configuration reporting to hwtstamp_get and remove legacy ioctl(). - Convert existing drivers to .get_rx_ring_count(), simplifing the RX ring count retrieval. Also remove the legacy fallback path. - Ethernet high-speed NICs: - Broadcom (bnxt, bng): - bnxt: add FW interface update to support FEC stats histogram and NVRAM defragmentation - bng: add TSO and H/W GRO support - nVidia/Mellanox (mlx5): - improve latency of channel restart operations, reducing the used H/W resources - add TSO support for UDP over GRE over VLAN - add flow counters support for hardware steering (HWS) rules - use a static memory area to store headers for H/W GRO, leading to 12% RX tput improvement - Intel (100G, ice, idpf): - ice: reorganizes layout of Tx and Rx rings for cacheline locality and utilizes __cacheline_group* macros on the new layouts - ice: introduces Synchronous Ethernet (SyncE) support - Meta (fbnic): - adds debugfs for firmware mailbox and tx/rx rings vectors - Ethernet virtual: - geneve: introduce GRO/GSO support for double UDP encapsulation - Ethernet NICs consumer, and embedded: - Synopsys (stmmac): - some code refactoring and cleanups - RealTek (r8169): - add support for RTL8127ATF (10G Fiber SFP) - add dash and LTR support - Airoha: - AN8811HB 2.5 Gbps phy support - Freescale (fec): - add XDP zero-copy support - Thunderbolt: - add get link setting support to allow bonding - Renesas: - add support for RZ/G3L GBETH SoC - Ethernet switches: - Maxlinear: - support R(G)MII slow rate configuration - add support for Intel GSW150 - Motorcomm (yt921x): - add DCB/QoS support - TI: - icssm-prueth: support bridging (STP/RSTP) via the switchdev framework - Ethernet PHYs: - Realtek: - enable SGMII and 2500Base-X in-band auto-negotiation - simplify and reunify C22/C45 drivers - Micrel: convert bindings to DT schema - CAN: - move skb headroom content into skb extensions, making CAN metadata access more robust - CAN drivers: - rcar_canfd: - add support for FD-only mode - add support for the RZ/T2H SoC - sja1000: cleanup the CAN state handling - WiFi: - implement EPPKE/802.1X over auth frames support - split up drop reasons better, removing generic RX_DROP - additional FTM capabilities: 6 GHz support, supported number of spatial streams and supported number of LTF repetitions - better mac80211 iterators to enumerate resources - initial UHR (Wi-Fi 8) support for cfg80211/mac80211 - WiFi drivers: - Qualcomm/Atheros: - ath11k: support for Channel Frequency Response measurement - ath12k: a significant driver refactor to support multi-wiphy devices and and pave the way for future device support in the same driver (rather than splitting to ath13k) - ath12k: support for the QCC2072 chipset - Intel: - iwlwifi: partial Neighbor Awareness Networking (NAN) support - iwlwifi: initial support for U-NII-9 and IEEE 802.11bn - RealTek (rtw89): - preparations for RTL8922DE support - Bluetooth: - implement setsockopt(BT_PHY) to set the connection packet type/PHY - set link_policy on incoming ACL connections - Bluetooth drivers: - btusb: add support for MediaTek7920, Realtek RTL8761BU and 8851BE - btqca: add WCN6855 firmware priority selection feature" * tag 'net-next-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1254 commits) bnge/bng_re: Add a new HSI net: macb: Fix tx/rx malfunction after phy link down and up af_unix: Fix memleak of newsk in unix_stream_connect(). net: ti: icssg-prueth: Add optional dependency on HSR net: dsa: add basic initial driver for MxL862xx switches net: mdio: add unlocked mdiodev C45 bus accessors net: dsa: add tag format for MxL862xx switches dt-bindings: net: dsa: add MaxLinear MxL862xx selftests: drivers: net: hw: Modify toeplitz.c to poll for packets octeontx2-pf: Unregister devlink on probe failure net: renesas: rswitch: fix forwarding offload statemachine ionic: Rate limit unknown xcvr type messages tcp: inet6_csk_xmit() optimization tcp: populate inet->cork.fl.u.ip6 in tcp_v6_syn_recv_sock() tcp: populate inet->cork.fl.u.ip6 in tcp_v6_connect() ipv6: inet6_csk_xmit() and inet6_csk_update_pmtu() use inet->cork.fl.u.ip6 ipv6: use inet->cork.fl.u.ip6 and np->final in ip6_datagram_dst_update() ipv6: use np->final in inet6_sk_rebuild_header() ipv6: add daddr/final storage in struct ipv6_pinfo net: stmmac: qcom-ethqos: fix qcom_ethqos_serdes_powerup() ...
Diffstat (limited to 'drivers/net/ethernet/dnet.h')
-rw-r--r--drivers/net/ethernet/dnet.h220
1 files changed, 0 insertions, 220 deletions
diff --git a/drivers/net/ethernet/dnet.h b/drivers/net/ethernet/dnet.h
deleted file mode 100644
index 030724484b49..000000000000
--- a/drivers/net/ethernet/dnet.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Dave DNET Ethernet Controller driver
- *
- * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
- */
-#ifndef _DNET_H
-#define _DNET_H
-
-#define DRV_NAME "dnet"
-#define PFX DRV_NAME ": "
-
-/* Register access macros */
-#define dnet_writel(port, value, reg) \
- writel((value), (port)->regs + DNET_##reg)
-#define dnet_readl(port, reg) readl((port)->regs + DNET_##reg)
-
-/* ALL DNET FIFO REGISTERS */
-#define DNET_RX_LEN_FIFO 0x000 /* RX_LEN_FIFO */
-#define DNET_RX_DATA_FIFO 0x004 /* RX_DATA_FIFO */
-#define DNET_TX_LEN_FIFO 0x008 /* TX_LEN_FIFO */
-#define DNET_TX_DATA_FIFO 0x00C /* TX_DATA_FIFO */
-
-/* ALL DNET CONTROL/STATUS REGISTERS OFFSETS */
-#define DNET_VERCAPS 0x100 /* VERCAPS */
-#define DNET_INTR_SRC 0x104 /* INTR_SRC */
-#define DNET_INTR_ENB 0x108 /* INTR_ENB */
-#define DNET_RX_STATUS 0x10C /* RX_STATUS */
-#define DNET_TX_STATUS 0x110 /* TX_STATUS */
-#define DNET_RX_FRAMES_CNT 0x114 /* RX_FRAMES_CNT */
-#define DNET_TX_FRAMES_CNT 0x118 /* TX_FRAMES_CNT */
-#define DNET_RX_FIFO_TH 0x11C /* RX_FIFO_TH */
-#define DNET_TX_FIFO_TH 0x120 /* TX_FIFO_TH */
-#define DNET_SYS_CTL 0x124 /* SYS_CTL */
-#define DNET_PAUSE_TMR 0x128 /* PAUSE_TMR */
-#define DNET_RX_FIFO_WCNT 0x12C /* RX_FIFO_WCNT */
-#define DNET_TX_FIFO_WCNT 0x130 /* TX_FIFO_WCNT */
-
-/* ALL DNET MAC REGISTERS */
-#define DNET_MACREG_DATA 0x200 /* Mac-Reg Data */
-#define DNET_MACREG_ADDR 0x204 /* Mac-Reg Addr */
-
-/* ALL DNET RX STATISTICS COUNTERS */
-#define DNET_RX_PKT_IGNR_CNT 0x300
-#define DNET_RX_LEN_CHK_ERR_CNT 0x304
-#define DNET_RX_LNG_FRM_CNT 0x308
-#define DNET_RX_SHRT_FRM_CNT 0x30C
-#define DNET_RX_IPG_VIOL_CNT 0x310
-#define DNET_RX_CRC_ERR_CNT 0x314
-#define DNET_RX_OK_PKT_CNT 0x318
-#define DNET_RX_CTL_FRM_CNT 0x31C
-#define DNET_RX_PAUSE_FRM_CNT 0x320
-#define DNET_RX_MULTICAST_CNT 0x324
-#define DNET_RX_BROADCAST_CNT 0x328
-#define DNET_RX_VLAN_TAG_CNT 0x32C
-#define DNET_RX_PRE_SHRINK_CNT 0x330
-#define DNET_RX_DRIB_NIB_CNT 0x334
-#define DNET_RX_UNSUP_OPCD_CNT 0x338
-#define DNET_RX_BYTE_CNT 0x33C
-
-/* DNET TX STATISTICS COUNTERS */
-#define DNET_TX_UNICAST_CNT 0x400
-#define DNET_TX_PAUSE_FRM_CNT 0x404
-#define DNET_TX_MULTICAST_CNT 0x408
-#define DNET_TX_BRDCAST_CNT 0x40C
-#define DNET_TX_VLAN_TAG_CNT 0x410
-#define DNET_TX_BAD_FCS_CNT 0x414
-#define DNET_TX_JUMBO_CNT 0x418
-#define DNET_TX_BYTE_CNT 0x41C
-
-/* SOME INTERNAL MAC-CORE REGISTER */
-#define DNET_INTERNAL_MODE_REG 0x0
-#define DNET_INTERNAL_RXTX_CONTROL_REG 0x2
-#define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4
-#define DNET_INTERNAL_IGP_REG 0x8
-#define DNET_INTERNAL_MAC_ADDR_0_REG 0xa
-#define DNET_INTERNAL_MAC_ADDR_1_REG 0xc
-#define DNET_INTERNAL_MAC_ADDR_2_REG 0xe
-#define DNET_INTERNAL_TX_RX_STS_REG 0x12
-#define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14
-#define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16
-
-#define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14)
-
-#define DNET_INTERNAL_WRITE (1 << 31)
-
-/* MAC-CORE REGISTER FIELDS */
-
-/* MAC-CORE MODE REGISTER FIELDS */
-#define DNET_INTERNAL_MODE_GBITEN (1 << 0)
-#define DNET_INTERNAL_MODE_FCEN (1 << 1)
-#define DNET_INTERNAL_MODE_RXEN (1 << 2)
-#define DNET_INTERNAL_MODE_TXEN (1 << 3)
-
-/* MAC-CORE RXTX CONTROL REGISTER FIELDS */
-#define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8)
-#define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7)
-#define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4)
-#define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3)
-#define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2)
-#define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1)
-#define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0)
-#define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6)
-#define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5)
-
-/* SYSTEM CONTROL REGISTER FIELDS */
-#define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0)
-#define DNET_SYS_CTL_SENDPAUSE (1 << 2)
-#define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3)
-#define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4)
-
-/* TX STATUS REGISTER FIELDS */
-#define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2)
-#define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1)
-
-/* INTERRUPT SOURCE REGISTER FIELDS */
-#define DNET_INTR_SRC_TX_PKTSENT (1 << 0)
-#define DNET_INTR_SRC_TX_FIFOAF (1 << 1)
-#define DNET_INTR_SRC_TX_FIFOAE (1 << 2)
-#define DNET_INTR_SRC_TX_DISCFRM (1 << 3)
-#define DNET_INTR_SRC_TX_FIFOFULL (1 << 4)
-#define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8)
-#define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9)
-#define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10)
-#define DNET_INTR_SRC_TX_SUMMARY (1 << 16)
-#define DNET_INTR_SRC_RX_SUMMARY (1 << 17)
-#define DNET_INTR_SRC_PHY (1 << 19)
-
-/* INTERRUPT ENABLE REGISTER FIELDS */
-#define DNET_INTR_ENB_TX_PKTSENT (1 << 0)
-#define DNET_INTR_ENB_TX_FIFOAF (1 << 1)
-#define DNET_INTR_ENB_TX_FIFOAE (1 << 2)
-#define DNET_INTR_ENB_TX_DISCFRM (1 << 3)
-#define DNET_INTR_ENB_TX_FIFOFULL (1 << 4)
-#define DNET_INTR_ENB_RX_PKTRDY (1 << 8)
-#define DNET_INTR_ENB_RX_FIFOAF (1 << 9)
-#define DNET_INTR_ENB_RX_FIFOERR (1 << 10)
-#define DNET_INTR_ENB_RX_ERROR (1 << 11)
-#define DNET_INTR_ENB_RX_FIFOFULL (1 << 12)
-#define DNET_INTR_ENB_RX_FIFOAE (1 << 13)
-#define DNET_INTR_ENB_TX_SUMMARY (1 << 16)
-#define DNET_INTR_ENB_RX_SUMMARY (1 << 17)
-#define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18)
-
-/* default values:
- * almost empty = less than one full sized ethernet frame (no jumbo) inside
- * the fifo almost full = can write less than one full sized ethernet frame
- * (no jumbo) inside the fifo
- */
-#define DNET_CFG_TX_FIFO_FULL_THRES 25
-#define DNET_CFG_RX_FIFO_FULL_THRES 20
-
-/*
- * Capabilities. Used by the driver to know the capabilities that the ethernet
- * controller inside the FPGA have.
- */
-
-#define DNET_HAS_MDIO (1 << 0)
-#define DNET_HAS_IRQ (1 << 1)
-#define DNET_HAS_GIGABIT (1 << 2)
-#define DNET_HAS_DMA (1 << 3)
-
-#define DNET_HAS_MII (1 << 4) /* or GMII */
-#define DNET_HAS_RMII (1 << 5) /* or RGMII */
-
-#define DNET_CAPS_MASK 0xFFFF
-
-#define DNET_FIFO_SIZE 1024 /* 1K x 32 bit */
-#define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */
-#define DNET_FIFO_TX_DATA_AE_TH 384
-
-#define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */
-
-/*
- * Hardware-collected statistics.
- */
-struct dnet_stats {
- u32 rx_pkt_ignr;
- u32 rx_len_chk_err;
- u32 rx_lng_frm;
- u32 rx_shrt_frm;
- u32 rx_ipg_viol;
- u32 rx_crc_err;
- u32 rx_ok_pkt;
- u32 rx_ctl_frm;
- u32 rx_pause_frm;
- u32 rx_multicast;
- u32 rx_broadcast;
- u32 rx_vlan_tag;
- u32 rx_pre_shrink;
- u32 rx_drib_nib;
- u32 rx_unsup_opcd;
- u32 rx_byte;
- u32 tx_unicast;
- u32 tx_pause_frm;
- u32 tx_multicast;
- u32 tx_brdcast;
- u32 tx_vlan_tag;
- u32 tx_bad_fcs;
- u32 tx_jumbo;
- u32 tx_byte;
-};
-
-struct dnet {
- void __iomem *regs;
- spinlock_t lock;
- struct platform_device *pdev;
- struct net_device *dev;
- struct dnet_stats hw_stats;
- unsigned int capabilities; /* read from FPGA */
- struct napi_struct napi;
-
- /* PHY stuff */
- struct mii_bus *mii_bus;
- unsigned int link;
- unsigned int speed;
- unsigned int duplex;
-};
-
-#endif /* _DNET_H */