diff options
| author | Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> | 2025-11-19 18:14:28 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2025-11-24 14:10:44 +0000 |
| commit | 1ce3e8adc7d0038e59a7c9f5c9e5f399ba0db5d6 (patch) | |
| tree | 0b43f751db7281ffa5f9865264cfa8242ec40f97 /tools/lib/python/abi/abi_regex.py | |
| parent | 77d931584dd38916b66c65320c80a65cbef4b122 (diff) | |
spi: rzv2h-rspi: add support for using PCLK for transfer clock
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs support
generating the SPI transfer clock from PCLK, with the quirk that SPR 0
is not supported, causing the highest achievable SPI transfer frequency
to be 31.25MHz.
Add support for generating the SPI transfer clock from PCLK.
Renesas RZ/V2H (R9A09G057) also has the BPEN bit used to enable this
option in the datasheet, but it is not explicitly documented and there's
no details about its limitations as there are on RZ/T2H.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Link: https://patch.msgid.link/20251119161434.595677-8-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/lib/python/abi/abi_regex.py')
0 files changed, 0 insertions, 0 deletions