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| author | Junhui Liu <junhui.liu@pigmoral.tech> | 2025-10-21 17:41:43 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2025-11-12 17:06:56 +0000 |
| commit | a94f9be29464f85e97683901162ca236dde40dc7 (patch) | |
| tree | bd9bc9192026e746697de4745cb1aeb0c65d3cce /tools/lib/python/abi/abi_regex.py | |
| parent | ccc3fd3ebeef2686f005733858c0a1b2cb89aaeb (diff) | |
dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
The Anlogic DR1V90 SoC integrates a UART controller compatible with
snps,dw-apb-uart, operating at a 50 MHz clock.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'tools/lib/python/abi/abi_regex.py')
0 files changed, 0 insertions, 0 deletions