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-rw-r--r--drivers/misc/amd-sbi/Kconfig4
-rw-r--r--drivers/misc/amd-sbi/rmi-core.c194
-rw-r--r--drivers/misc/amd-sbi/rmi-i2c.c124
3 files changed, 266 insertions, 56 deletions
diff --git a/drivers/misc/amd-sbi/Kconfig b/drivers/misc/amd-sbi/Kconfig
index ab594908cb4a..be022c71a90c 100644
--- a/drivers/misc/amd-sbi/Kconfig
+++ b/drivers/misc/amd-sbi/Kconfig
@@ -4,8 +4,10 @@ config AMD_SBRMI_I2C
depends on I2C
depends on ARM || ARM64 || COMPILE_TEST
select REGMAP_I2C
+ depends on I3C || !I3C
+ select REGMAP_I3C if I3C
help
- Side band RMI over I2C support for AMD out of band management.
+ Side band RMI over I2C/I3C support for AMD out of band management.
This driver is intended to run on the BMC, not the managed node.
This driver can also be built as a module. If so, the module will
diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c
index 3dec2fc00124..c3a58912d6db 100644
--- a/drivers/misc/amd-sbi/rmi-core.c
+++ b/drivers/misc/amd-sbi/rmi-core.c
@@ -28,13 +28,17 @@
/* CPUID */
#define CPUID_RD_DATA_LEN 0x8
#define CPUID_WR_DATA_LEN 0x8
+#define CPUID_WR_DATA_LEN_EXT 0x9
#define CPUID_RD_REG_LEN 0xa
#define CPUID_WR_REG_LEN 0x9
+#define CPUID_WR_REG_LEN_EXT 0xa
/* MSR */
#define MSR_RD_REG_LEN 0xa
#define MSR_WR_REG_LEN 0x8
+#define MSR_WR_REG_LEN_EXT 0x9
#define MSR_RD_DATA_LEN 0x8
#define MSR_WR_DATA_LEN 0x7
+#define MSR_WR_DATA_LEN_EXT 0x8
/* CPUID MSR Command Ids */
#define CPUID_MCA_CMD 0x73
@@ -59,6 +63,20 @@ struct cpu_msr_indata {
u8 ext; /* extended function */
};
+/* input for bulk write to CPUID protocol for REV 0x21 */
+struct cpu_msr_indata_ext {
+ u8 wr_len; /* const value */
+ u8 rd_len; /* const value */
+ u8 proto_cmd; /* const value */
+ u8 thread_lo; /* thread number low */
+ u8 thread_hi; /* thread number high */
+ union {
+ u8 reg_offset[4]; /* input value */
+ u32 value;
+ } __packed;
+ u8 ext; /* extended function */
+};
+
/* output for bulk read from CPUID protocol */
struct cpu_msr_outdata {
u8 num_bytes; /* number of bytes return */
@@ -81,6 +99,19 @@ static inline void prepare_cpuid_input_message(struct cpu_msr_indata *input,
input->ext = ext_func;
}
+static inline void prepare_cpuid_input_message_ext(struct cpu_msr_indata_ext *input,
+ u16 thread_id, u32 func,
+ u8 ext_func)
+{
+ input->rd_len = CPUID_RD_DATA_LEN;
+ input->wr_len = CPUID_WR_DATA_LEN_EXT;
+ input->proto_cmd = RD_CPUID_CMD;
+ input->thread_lo = (thread_id & 0xFF) << 1;
+ input->thread_hi = thread_id >> 8;
+ input->value = func;
+ input->ext = ext_func;
+}
+
static inline void prepare_mca_msr_input_message(struct cpu_msr_indata *input,
u8 thread_id, u32 data_in)
{
@@ -91,6 +122,17 @@ static inline void prepare_mca_msr_input_message(struct cpu_msr_indata *input,
input->value = data_in;
}
+static inline void prepare_mca_msr_input_message_ext(struct cpu_msr_indata_ext *input,
+ u16 thread_id, u32 data_in)
+{
+ input->rd_len = MSR_RD_DATA_LEN;
+ input->wr_len = MSR_WR_DATA_LEN_EXT;
+ input->proto_cmd = RD_MCA_CMD;
+ input->thread_lo = (thread_id & 0xFF) << 1;
+ input->thread_hi = thread_id >> 8;
+ input->value = data_in;
+}
+
static int sbrmi_get_rev(struct sbrmi_data *data)
{
unsigned int rev;
@@ -105,13 +147,48 @@ static int sbrmi_get_rev(struct sbrmi_data *data)
return 0;
}
+static int rmi_cpuid_input(struct sbrmi_data *data, struct apml_cpuid_msg *msg,
+ u16 thread)
+{
+ struct cpu_msr_indata input = {0};
+ int val = 0, ret;
+
+ /* Thread > 127, Thread128 CS register, 1'b1 needs to be set to 1 */
+ if (thread > 127) {
+ thread -= 128;
+ val = 1;
+ }
+
+ ret = regmap_write(data->regmap, SBRMI_THREAD128CS, val);
+ if (ret < 0)
+ return ret;
+
+ prepare_cpuid_input_message(&input, thread,
+ msg->cpu_in_out & CPUID_MCA_FUNC_MASK,
+ msg->cpu_in_out >> CPUID_EXT_FUNC_INDEX);
+
+ return regmap_bulk_write(data->regmap, CPUID_MCA_CMD,
+ &input, CPUID_WR_REG_LEN);
+}
+
+static int rmi_cpuid_input_ext(struct sbrmi_data *data, struct apml_cpuid_msg *msg,
+ u16 thread)
+{
+ struct cpu_msr_indata_ext input = {0};
+
+ prepare_cpuid_input_message_ext(&input, thread,
+ msg->cpu_in_out & CPUID_MCA_FUNC_MASK,
+ msg->cpu_in_out >> CPUID_EXT_FUNC_INDEX);
+
+ return regmap_bulk_write(data->regmap, CPUID_MCA_CMD,
+ &input, CPUID_WR_REG_LEN_EXT);
+}
+
/* Read CPUID function protocol */
static int rmi_cpuid_read(struct sbrmi_data *data,
struct apml_cpuid_msg *msg)
{
- struct cpu_msr_indata input = {0};
struct cpu_msr_outdata output = {0};
- int val = 0;
int ret, hw_status;
u16 thread;
@@ -122,31 +199,29 @@ static int rmi_cpuid_read(struct sbrmi_data *data,
if (ret < 0)
goto exit_unlock;
}
- /* CPUID protocol for REV 0x10 is not supported*/
- if (data->rev == 0x10) {
- ret = -EOPNOTSUPP;
- goto exit_unlock;
- }
+ /* Extract thread from the input msg structure */
thread = msg->cpu_in_out >> CPUID_MCA_THRD_INDEX;
- /* Thread > 127, Thread128 CS register, 1'b1 needs to be set to 1 */
- if (thread > 127) {
- thread -= 128;
- val = 1;
- }
- ret = regmap_write(data->regmap, SBRMI_THREAD128CS, val);
- if (ret < 0)
+ switch (data->rev) {
+ case 0x10:
+ /* CPUID protocol for REV 0x10 is not supported*/
+ ret = -EOPNOTSUPP;
goto exit_unlock;
-
- prepare_cpuid_input_message(&input, thread,
- msg->cpu_in_out & CPUID_MCA_FUNC_MASK,
- msg->cpu_in_out >> CPUID_EXT_FUNC_INDEX);
-
- ret = regmap_bulk_write(data->regmap, CPUID_MCA_CMD,
- &input, CPUID_WR_REG_LEN);
- if (ret < 0)
+ case 0x20:
+ ret = rmi_cpuid_input(data, msg, thread);
+ if (ret)
+ goto exit_unlock;
+ break;
+ case 0x21:
+ ret = rmi_cpuid_input_ext(data, msg, thread);
+ if (ret)
+ goto exit_unlock;
+ break;
+ default:
+ ret = -EOPNOTSUPP;
goto exit_unlock;
+ }
/*
* For RMI Rev 0x20, new h/w status bit is introduced. which is used
@@ -186,13 +261,47 @@ exit_unlock:
return ret;
}
+static int rmi_mcamsr_input(struct sbrmi_data *data, struct apml_mcamsr_msg *msg,
+ u16 thread)
+{
+ struct cpu_msr_indata input = {0};
+ int val = 0, ret;
+
+ /* Thread > 127, Thread128 CS register, 1'b1 needs to be set to 1 */
+ if (thread > 127) {
+ thread -= 128;
+ val = 1;
+ }
+
+ ret = regmap_write(data->regmap, SBRMI_THREAD128CS, val);
+ if (ret < 0)
+ return ret;
+
+ prepare_mca_msr_input_message(&input, thread,
+ msg->mcamsr_in_out & CPUID_MCA_FUNC_MASK);
+
+ return regmap_bulk_write(data->regmap, CPUID_MCA_CMD,
+ &input, MSR_WR_REG_LEN);
+}
+
+static int rmi_mcamsr_input_ext(struct sbrmi_data *data, struct apml_mcamsr_msg *msg,
+ u16 thread)
+{
+ struct cpu_msr_indata_ext input = {0};
+
+ prepare_mca_msr_input_message_ext(&input, thread,
+ msg->mcamsr_in_out & CPUID_MCA_FUNC_MASK);
+
+ return regmap_bulk_write(data->regmap, CPUID_MCA_CMD,
+ &input, MSR_WR_REG_LEN_EXT);
+}
+
/* MCA MSR protocol */
static int rmi_mca_msr_read(struct sbrmi_data *data,
struct apml_mcamsr_msg *msg)
{
struct cpu_msr_outdata output = {0};
- struct cpu_msr_indata input = {0};
- int ret, val = 0;
+ int ret;
int hw_status;
u16 thread;
@@ -203,30 +312,29 @@ static int rmi_mca_msr_read(struct sbrmi_data *data,
if (ret < 0)
goto exit_unlock;
}
- /* MCA MSR protocol for REV 0x10 is not supported*/
- if (data->rev == 0x10) {
- ret = -EOPNOTSUPP;
- goto exit_unlock;
- }
+ /* Extract thread from the input msg structure */
thread = msg->mcamsr_in_out >> CPUID_MCA_THRD_INDEX;
- /* Thread > 127, Thread128 CS register, 1'b1 needs to be set to 1 */
- if (thread > 127) {
- thread -= 128;
- val = 1;
- }
- ret = regmap_write(data->regmap, SBRMI_THREAD128CS, val);
- if (ret < 0)
+ switch (data->rev) {
+ case 0x10:
+ /* MCAMSR protocol for REV 0x10 is not supported*/
+ ret = -EOPNOTSUPP;
goto exit_unlock;
-
- prepare_mca_msr_input_message(&input, thread,
- msg->mcamsr_in_out & CPUID_MCA_FUNC_MASK);
-
- ret = regmap_bulk_write(data->regmap, CPUID_MCA_CMD,
- &input, MSR_WR_REG_LEN);
- if (ret < 0)
+ case 0x20:
+ ret = rmi_mcamsr_input(data, msg, thread);
+ if (ret)
+ goto exit_unlock;
+ break;
+ case 0x21:
+ ret = rmi_mcamsr_input_ext(data, msg, thread);
+ if (ret)
+ goto exit_unlock;
+ break;
+ default:
+ ret = -EOPNOTSUPP;
goto exit_unlock;
+ }
/*
* For RMI Rev 0x20, new h/w status bit is introduced. which is used
diff --git a/drivers/misc/amd-sbi/rmi-i2c.c b/drivers/misc/amd-sbi/rmi-i2c.c
index f891f5af4bc6..f0cc99000b69 100644
--- a/drivers/misc/amd-sbi/rmi-i2c.c
+++ b/drivers/misc/amd-sbi/rmi-i2c.c
@@ -9,6 +9,8 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/i2c.h>
+#include <linux/i3c/device.h>
+#include <linux/i3c/master.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mutex.h>
@@ -16,6 +18,8 @@
#include <linux/regmap.h>
#include "rmi-core.h"
+#define REV_TWO_BYTE_ADDR 0x21
+
static int sbrmi_enable_alert(struct sbrmi_data *data)
{
int ctrl, ret;
@@ -50,26 +54,18 @@ static int sbrmi_get_max_pwr_limit(struct sbrmi_data *data)
return ret;
}
-static int sbrmi_i2c_probe(struct i2c_client *client)
+static int sbrmi_common_probe(struct device *dev, struct regmap *regmap, uint8_t address)
{
- struct device *dev = &client->dev;
struct sbrmi_data *data;
- struct regmap_config sbrmi_i2c_regmap_config = {
- .reg_bits = 8,
- .val_bits = 8,
- };
int ret;
data = devm_kzalloc(dev, sizeof(struct sbrmi_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
+ data->regmap = regmap;
mutex_init(&data->lock);
- data->regmap = devm_regmap_init_i2c(client, &sbrmi_i2c_regmap_config);
- if (IS_ERR(data->regmap))
- return PTR_ERR(data->regmap);
-
/* Enable alert for SB-RMI sequence */
ret = sbrmi_enable_alert(data);
if (ret < 0)
@@ -80,7 +76,8 @@ static int sbrmi_i2c_probe(struct i2c_client *client)
if (ret < 0)
return ret;
- data->dev_static_addr = client->addr;
+ data->dev_static_addr = address;
+
dev_set_drvdata(dev, data);
ret = create_hwmon_sensor_device(dev, data);
@@ -89,6 +86,48 @@ static int sbrmi_i2c_probe(struct i2c_client *client)
return create_misc_rmi_device(data, dev);
}
+static struct regmap_config sbrmi_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+};
+
+static struct regmap_config sbrmi_regmap_config_ext = {
+ .reg_bits = 16,
+ .val_bits = 8,
+ .reg_format_endian = REGMAP_ENDIAN_LITTLE,
+};
+
+static int sbrmi_i2c_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ struct regmap *regmap;
+ int rev, ret;
+
+ regmap = devm_regmap_init_i2c(client, &sbrmi_regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ ret = regmap_read(regmap, SBRMI_REV, &rev);
+ if (ret)
+ return ret;
+
+ /*
+ * For Turin and newer platforms, revision is 0x21 or later. This is
+ * to identify the two byte register address size. However, one
+ * byte transaction can be successful.
+ * Verify if revision is 0x21 or later, if yes, switch to 2 byte
+ * address size.
+ * Continuously using 1 byte address for revision 0x21 or later can lead
+ * to bus corruption.
+ */
+ if (rev >= REV_TWO_BYTE_ADDR) {
+ regmap = devm_regmap_init_i2c(client, &sbrmi_regmap_config_ext);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+ }
+ return sbrmi_common_probe(dev, regmap, client->addr);
+}
+
static void sbrmi_i2c_remove(struct i2c_client *client)
{
struct sbrmi_data *data = dev_get_drvdata(&client->dev);
@@ -125,7 +164,68 @@ static struct i2c_driver sbrmi_driver = {
.id_table = sbrmi_id,
};
-module_i2c_driver(sbrmi_driver);
+static int sbrmi_i3c_probe(struct i3c_device *i3cdev)
+{
+ struct device *dev = i3cdev_to_dev(i3cdev);
+ struct regmap *regmap;
+ int rev, ret;
+
+ regmap = devm_regmap_init_i3c(i3cdev, &sbrmi_regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ ret = regmap_read(regmap, SBRMI_REV, &rev);
+ if (ret)
+ return ret;
+
+ /*
+ * For Turin and newer platforms, revision is 0x21 or later. This is
+ * to identify the two byte register address size. However, one
+ * byte transaction can be successful.
+ * Verify if revision is 0x21 or later, if yes, switch to 2 byte
+ * address size.
+ * Continuously using 1 byte address for revision 0x21 or later can lead
+ * to bus corruption.
+ */
+ if (rev >= REV_TWO_BYTE_ADDR) {
+ regmap = devm_regmap_init_i3c(i3cdev, &sbrmi_regmap_config_ext);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+ }
+
+ /*
+ * AMD APML I3C devices support static address.
+ * If static address is defined, dynamic address is same as static address.
+ * In case static address is not defined, I3C master controller defined
+ * dynamic address is used.
+ */
+ return sbrmi_common_probe(dev, regmap, i3cdev->desc->info.dyn_addr);
+}
+
+static void sbrmi_i3c_remove(struct i3c_device *i3cdev)
+{
+ struct sbrmi_data *data = dev_get_drvdata(&i3cdev->dev);
+
+ misc_deregister(&data->sbrmi_misc_dev);
+}
+
+static const struct i3c_device_id sbrmi_i3c_id[] = {
+ /* PID for AMD SBRMI device */
+ I3C_DEVICE_EXTRA_INFO(0x112, 0x0, 0x2, NULL),
+ {}
+};
+MODULE_DEVICE_TABLE(i3c, sbrmi_i3c_id);
+
+static struct i3c_driver sbrmi_i3c_driver = {
+ .driver = {
+ .name = "sbrmi-i3c",
+ },
+ .probe = sbrmi_i3c_probe,
+ .remove = sbrmi_i3c_remove,
+ .id_table = sbrmi_i3c_id,
+};
+
+module_i3c_i2c_driver(sbrmi_i3c_driver, &sbrmi_driver);
MODULE_AUTHOR("Akshay Gupta <akshay.gupta@amd.com>");
MODULE_AUTHOR("Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>");
generated by cgit v1.2.3 (git 2.46.0) at 2025-12-07 15:55:50 +0000