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Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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page_to_virt and lowmem_page_address provided equiavlent functionality
so use the more standard lowmem_page_address
This also addresses build issue in ARCH=powerpc since page_to_virt()
has been removed from include/asm-powerpc/page.h
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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This has three main parts: (1) support for the 440GP and 440GX processors,
(2) support for the "Ebony" and "Ocotea" reference boards for those processors,
and (3) support for 64-bit physical addresses. The 440GP and 440GX are "Book E"
processors, and this introduces a CONFIG_BOOKE and some definitions that apply
to all Book E processors.
Having 64-bit physical addresses means that PTEs are now 64 bits. The PTE pages
stay at 4kB, and the pgdir expands to 8kB.
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The tags were slightly useful when the kernel maintainers weren't
using BK, but these days they are more trouble than they are worth.
They tend to cause patch rejects, and often end up getting turned
into the fixed form (rather than the %x% tag form).
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It has been noticed that across a kernel build many calls to
tlb_flush_mmu() do not have anything to flush, apparently because glibc
is mmapping a file over a previously-mapped region which has no
faulted-in ptes.
This patch detects this case and optimises away a little over one third
of the tlb invalidations.
The functions which potentially cause an invalidate are
tlb_remove_tlb_entry(), pte_free_tlb() and pmd_free_tlb(). These have
been front-ended in asm-generic/tlb.h and the per-arch versions now
have leading double-underscores. The generic versions tag the
mmu_gather_t as needing a flush and then call the arch-specific
version.
tlb_flush_mmu() looks at tlb->need_flush and if it sees that no real
activity has happened, the invalidation is avoided.
The success rate is displayed in /proc/meminfo for the while. This
should be removed later.
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now used in generic code.
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This implements ptes-in-highmem for PPC, removes the quicklist
and zero-page stuff. PTEs in highmem on SMP turned out to need
some significant changes to avoid deadlocks on the hash_table_lock
(now renamed to mmu_hash_lock). The PMDs now contain the physical
address of the PTE page rather than the virtual address.
Anything that takes the mmu_hash_lock now operates with the DMMU
off to avoid MMU hash-table misses.
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- Al Viro: fs cleanups
- David Miller: sparc semaphores
- Christoph Hellwig: VxFS update
- Asit Mallick: set machine check bit with set_in_cr4
- Richard Henderson: fix alpha pci_controller_num(), sg_fill, SRM poweroff.
- Johannes Erdfelt: USB updates
- Cort Dougan: bitkeeper Id's on the ppc side
- Matt Chapman: NFS file locking SMP lock fix
- Alan Cox: further merging
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- Johannes Erdfelt: USB updates
- David Howells: more rw-sem stuff
- David Miller: network callback cleanups and fixes
- Jan Harkes: make Coda use the proper VFS layer interfaces, so that it can use
"non-traditional-unix" filesystems without inode numbers for backing store.
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- Kai Germaschewski: Makefile dependency fixes. ISDN update
- Chris Mason: another reiserfs tail writing fix
- unify pte/pmd allocation
- undo some VIA PCI fixups - conflicting behaviour
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- Paul Mackerras: PPC update for thread-safe page table handling
- Ingo Molnar: x86 PAE update for thread-safe page table handling
- Jeff Garzik: network driver updates, i810 rng driver, and
"alloc_etherdev()" network driver insert race condition fix.
- David Miller: UltraSparcIII update, network locking fixes
- Al Viro: fix fs counts on mount failure
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