From ad2a676c64be2bed0bbed32147c4247d46953158 Mon Sep 17 00:00:00 2001 From: Randy Vinson Date: Sat, 11 Jan 2003 13:09:34 +1100 Subject: PPC32: Fix host bridge programming on Adirondack "K2" boards. --- arch/ppc/platforms/k2_pci.c | 7 +++++++ arch/ppc/syslib/cpc710.h | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/arch/ppc/platforms/k2_pci.c b/arch/ppc/platforms/k2_pci.c index f1cd920ec664..e6e70983999d 100644 --- a/arch/ppc/platforms/k2_pci.c +++ b/arch/ppc/platforms/k2_pci.c @@ -156,6 +156,13 @@ void k2_setup_hoses(void) __raw_writel(0x00000080, K2_PCI32_BAR+PSBAR); /* Base@0x80 */ __raw_writel(0x00000000, K2_PCI32_BAR+PPBAR); + __raw_writel(0xc0000000, K2_PCI32_BAR+BPMDLK); + __raw_writel(0xd0000000, K2_PCI32_BAR+TPMDLK); + __raw_writel(0x80000000, K2_PCI32_BAR+BIODLK); + __raw_writel(0x80100000, K2_PCI32_BAR+TIODLK); + __raw_writel(0xe0008000, K2_PCI32_BAR+DLKCTRL); + __raw_writel(0xffffffff, K2_PCI32_BAR+DLKDEV); + /* PCI64 mappings */ __raw_writel(0x00100000, K2_PCI64_BAR+PIBAR); /* PCI I/O base */ __raw_writel(0x10000000, K2_PCI64_BAR+PMBAR); /* PCI Mem base */ diff --git a/arch/ppc/syslib/cpc710.h b/arch/ppc/syslib/cpc710.h index ede184e36b5e..2dfacbb7580a 100644 --- a/arch/ppc/syslib/cpc710.h +++ b/arch/ppc/syslib/cpc710.h @@ -61,6 +61,12 @@ #define BARPP 0x000f8130 #define PSBAR 0x000f8140 #define PPBAR 0x000f8150 +#define BPMDLK 0x000f8200 /* Bottom of Peripheral Memory Space */ +#define TPMDLK 0x000f8210 /* Top of Peripheral Memory Space */ +#define BIODLK 0x000f8220 /* Bottom of Peripheral I/O Space */ +#define TIODLK 0x000f8230 /* Top of Perioheral I/O Space */ +#define DLKCTRL 0x000f8240 /* Deadlock control */ +#define DLKDEV 0x000f8250 /* Deadlock device */ /* System standard configuration registers space */ #define DCR 0xff200000 -- cgit v1.2.3 From 935871e4d6ae17e9d669ff429cbc7f9a8fecb4e3 Mon Sep 17 00:00:00 2001 From: Randy Vinson Date: Sat, 11 Jan 2003 13:29:29 +1100 Subject: PPC32: Explicitly control store-gathering on MPC10x host bridges. This change alters the behavior of the "MCP10x Store Gathering Enable" option. Previously, selecting this option would enable store gathering, while not selecting the option would leave the firmware-provided state. In short, there was no way to disable store gathering if the firmware had left it enabled. This caused problems with the Adaptec 2940U2W when run in 8240 and 8245 Sandpoint systems. The new code will disable store gathering unless the user requests it. --- arch/ppc/syslib/mpc10x_common.c | 24 ++++++++++++++++++++++++ include/asm-ppc/mpc10x.h | 1 + 2 files changed, 25 insertions(+) diff --git a/arch/ppc/syslib/mpc10x_common.c b/arch/ppc/syslib/mpc10x_common.c index facbf56019d7..b972d466672b 100644 --- a/arch/ppc/syslib/mpc10x_common.c +++ b/arch/ppc/syslib/mpc10x_common.c @@ -243,6 +243,8 @@ mpc10x_bridge_init(struct pci_controller *hose, #ifdef CONFIG_MPC10X_STORE_GATHERING mpc10x_enable_store_gathering(hose); +#else + mpc10x_disable_store_gathering(hose); #endif if (ppc_md.progress) ppc_md.progress("mpc10x:exit", 0x100); @@ -376,3 +378,25 @@ mpc10x_enable_store_gathering(struct pci_controller *hose) return 0; } + +int __init +mpc10x_disable_store_gathering(struct pci_controller *hose) +{ + uint picr1; + + early_read_config_dword(hose, + 0, + PCI_DEVFN(0,0), + MPC10X_CFG_PICR1_REG, + &picr1); + + picr1 &= ~MPC10X_CFG_PICR1_ST_GATH_EN; + + early_write_config_dword(hose, + 0, + PCI_DEVFN(0,0), + MPC10X_CFG_PICR1_REG, + picr1); + + return 0; +} diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h index 1d3a64f06d46..d2676d8f8088 100644 --- a/include/asm-ppc/mpc10x.h +++ b/include/asm-ppc/mpc10x.h @@ -164,5 +164,6 @@ int mpc10x_bridge_init(struct pci_controller *hose, uint phys_eumb_base); unsigned long mpc10x_get_mem_size(uint mem_map); int mpc10x_enable_store_gathering(struct pci_controller *hose); +int mpc10x_disable_store_gathering(struct pci_controller *hose); #endif /* __PPC_KERNEL_MPC10X_H */ -- cgit v1.2.3 From d14b8b2307fc6295cd1320fa48d5945082bea5e4 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Sat, 11 Jan 2003 13:50:28 +1100 Subject: PPC32: Use timing workaround for DS1743 RTC chip. --- arch/ppc/syslib/todc_time.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/ppc/syslib/todc_time.c b/arch/ppc/syslib/todc_time.c index 85ee80b4e581..40514058e44e 100644 --- a/arch/ppc/syslib/todc_time.c +++ b/arch/ppc/syslib/todc_time.c @@ -240,6 +240,7 @@ todc_get_rtc_time(void) switch (todc_info->rtc_type) { case TODC_TYPE_DS1557: + case TODC_TYPE_DS1743: case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */ case TODC_TYPE_DS1747: break; @@ -274,6 +275,7 @@ todc_get_rtc_time(void) if (todc_info->rtc_type != TODC_TYPE_MC146818) { switch (todc_info->rtc_type) { case TODC_TYPE_DS1557: + case TODC_TYPE_DS1743: case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */ case TODC_TYPE_DS1747: break; @@ -367,6 +369,7 @@ static unsigned char __init todc_read_timereg(int addr) switch (todc_info->rtc_type) { case TODC_TYPE_DS1557: + case TODC_TYPE_DS1743: case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */ case TODC_TYPE_DS1747: case TODC_TYPE_MC146818: @@ -381,6 +384,7 @@ static unsigned char __init todc_read_timereg(int addr) switch (todc_info->rtc_type) { case TODC_TYPE_DS1557: + case TODC_TYPE_DS1743: case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */ case TODC_TYPE_DS1747: case TODC_TYPE_MC146818: -- cgit v1.2.3 From 8ebe7055cdace09134384090591d80a4d157deca Mon Sep 17 00:00:00 2001 From: Dale Farnsworth Date: Tue, 14 Jan 2003 20:17:16 +1100 Subject: PPC32: Fix copy_from_user to copy as much as possible. copy_from_user is supposed to transfer as much data as is valid and then to return the number of bytes not tranferred. That's how it works on x86. On ppc it can be as much as 15 bytes short. I initially saw the problem with the mount system call. Note that the fifth argument to mount is an address 8 bytes from the end of user data space. There is a null byte at that address, since no mount options are being passed. In the kernel, sys_mount() allocates a page for the options and does copy_from_user(new_page, 0x1005eff8, PAGE_SIZE). copy_from_user should copy 8 bytes and return (PAGE_SIZE-8). Instead, on ppc it reads 8 bytes, faults, writes no bytes, and returns PAGE_SIZE, which causes the EFAULT to be erroneously reported. --- arch/ppc/lib/string.S | 39 +++++++++++++++++++++++++-------------- 1 file changed, 25 insertions(+), 14 deletions(-) diff --git a/arch/ppc/lib/string.S b/arch/ppc/lib/string.S index f182856b2b5b..5557156770dd 100644 --- a/arch/ppc/lib/string.S +++ b/arch/ppc/lib/string.S @@ -507,18 +507,18 @@ _GLOBAL(__copy_tofrom_user) blr /* read fault, initial single-byte copy */ -100: li r4,0 +100: li r9,0 b 90f /* write fault, initial single-byte copy */ -101: li r4,1 +101: li r9,1 90: subf r5,r8,r5 li r3,0 b 99f /* read fault, initial word copy */ -102: li r4,0 +102: li r9,0 b 91f /* write fault, initial word copy */ -103: li r4,1 +103: li r9,1 91: li r3,2 b 99f @@ -542,38 +542,47 @@ _GLOBAL(__copy_tofrom_user) #endif /* read fault in cacheline loop */ -104: li r4,0 +104: li r9,0 b 92f /* fault on dcbz (effectively a write fault) */ /* or write fault in cacheline loop */ -105: li r4,1 +105: li r9,1 92: li r3,LG_CACHELINE_BYTES b 99f /* read fault in final word loop */ -108: li r4,0 +108: li r9,0 b 93f /* write fault in final word loop */ -109: li r4,1 +109: li r9,1 93: andi. r5,r5,3 li r3,2 b 99f /* read fault in final byte loop */ -110: li r4,0 +110: li r9,0 b 94f /* write fault in final byte loop */ -111: li r4,1 +111: li r9,1 94: li r5,0 li r3,0 /* * At this stage the number of bytes not copied is - * r5 + (ctr << r3), and r4 is 0 for read or 1 for write. + * r5 + (ctr << r3), and r9 is 0 for read or 1 for write. */ 99: mfctr r0 slw r3,r0,r3 - add r3,r3,r5 - cmpwi 0,r4,0 + add. r3,r3,r5 + beq 120f /* shouldn't happen */ + cmpwi 0,r9,0 bne 120f -/* for read fault, clear out the destination: r3 bytes starting at 4(r6) */ +/* for a read fault, first try to continue the copy one byte at a time */ + mtctr r3 +130: lbz r0,4(r4) +131: stb r0,4(r6) + addi r4,r4,1 + addi r6,r6,1 + bdnz 130b +/* then clear out the destination: r3 bytes starting at 4(r6) */ +132: mfctr r3 srwi. r0,r3,2 li r9,0 mtctr r0 @@ -594,6 +603,8 @@ _GLOBAL(__copy_tofrom_user) .long 31b,109b .long 40b,110b .long 41b,111b + .long 130b,132b + .long 131b,120b .long 112b,120b .long 114b,120b .text -- cgit v1.2.3 From 9e7f90ddcedbe01fbb63c022ce61ef8c9a10cd8b Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Tue, 14 Jan 2003 20:22:38 +1100 Subject: PPC32: Change struct free_pte_ctx to struct mmu_gather. A couple of occurrences of struct free_pte_ctx in include/asm-ppc/tlb.h got missed in akpm's patch - this fixes them. --- include/asm-ppc/tlb.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/include/asm-ppc/tlb.h b/include/asm-ppc/tlb.h index b4375599b610..2c142c5d8584 100644 --- a/include/asm-ppc/tlb.h +++ b/include/asm-ppc/tlb.h @@ -21,8 +21,8 @@ #ifdef CONFIG_PPC_STD_MMU /* Classic PPC with hash-table based MMU... */ -struct free_pte_ctx; -extern void tlb_flush(struct free_pte_ctx *tlb); +struct mmu_gather; +extern void tlb_flush(struct mmu_gather *tlb); /* Get the generic bits... */ #include @@ -44,10 +44,6 @@ static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, #else /* Embedded PPC with software-loaded TLB, very simple... */ -struct flush_tlb_arch { }; - -#define tlb_init_arch(tlb, full_flush) do { } while (0) -#define tlb_finish_arch(tlb) do { } while (0) #define tlb_start_vma(tlb, vma) do { } while (0) #define tlb_end_vma(tlb, vma) do { } while (0) #define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0) -- cgit v1.2.3