From 897d49be87feb06747a3538e7fbf16cdcd349b75 Mon Sep 17 00:00:00 2001 From: Andrew Morton Date: Wed, 19 May 2004 02:35:27 -0700 Subject: [PATCH] slab: enable runtime cache line size on i386 From: Manfred Spraul the attached patch switches the SLAB_HWCACHE_ALIGN alignment from the compile time L1 cache line size to the runtime detected value for i386. x86-64 already uses the runtime detection. --- include/asm-i386/processor.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h index bab235068f91..9d49ea237f30 100644 --- a/include/asm-i386/processor.h +++ b/include/asm-i386/processor.h @@ -649,6 +649,8 @@ extern inline void prefetchw(const void *x) extern void select_idle_routine(const struct cpuinfo_x86 *c); +#define cache_line_size() (boot_cpu_data.x86_cache_alignment) + #ifdef CONFIG_SCHED_SMT #define ARCH_HAS_SCHED_DOMAIN #define ARCH_HAS_SCHED_WAKE_IDLE -- cgit v1.2.3