From 43a6a29b7eda5b4b5efecf43b30e75dc8faa7af4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 19 Nov 2022 01:32:36 +0200 Subject: dt-bindings: phy: qcom,qmp-pcie: add sm8350 bindings Add bindings for the PCIe QMP PHYs found on SM8350. Reviewed-by: Rob Herring Reviewed-by: Johan Hovold Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20221118233242.2904088-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 80aa8d2507fb..8a85318d9c92 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -19,15 +19,18 @@ properties: - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,sm8350-qmp-gen3x1-pcie-phy reg: minItems: 1 maxItems: 2 clocks: + minItems: 5 maxItems: 6 clock-names: + minItems: 5 items: - const: aux - const: cfg_ahb @@ -104,6 +107,25 @@ allOf: reg: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8350-qmp-gen3x1-pcie-phy + then: + properties: + clocks: + maxItems: 5 + clock-names: + maxItems: 5 + else: + properties: + clocks: + minItems: 6 + clock-names: + minItems: 6 + examples: - | #include -- cgit v1.2.3 From a98f5cc9c0e01186244498a084bf24ae764f86f2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 29 Dec 2022 13:59:31 +0200 Subject: dt-bindings: phy: qcom,pcie2-phy: convert to YAML format Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format from the text description. Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20221229115932.3312318-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/qcom,pcie2-phy.yaml | 86 ++++++++++++++++++++++ .../devicetree/bindings/phy/qcom-pcie2-phy.txt | 42 ----------- 2 files changed, 86 insertions(+), 42 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml new file mode 100644 index 000000000000..dbc4a4c71f05 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCIe2 PHY controller + +maintainers: + - Vinod Koul + +description: + The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm + platforms. + +properties: + compatible: + items: + - const: qcom,qcs404-pcie2-phy + - const: qcom,pcie2-phy + + reg: + items: + - description: PHY register set + + clocks: + items: + - description: a clock-specifier pair for the "pipe" clock + + clock-output-names: + maxItems: 1 + + "#clock-cells": + const: 0 + + "#phy-cells": + const: 0 + + vdda-vp-supply: + description: low voltage regulator + + vdda-vph-supply: + description: high voltage regulator + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: pipe + +required: + - compatible + - reg + - clocks + - clock-output-names + - "#clock-cells" + - "#phy-cells" + - vdda-vp-supply + - vdda-vph-supply + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; +... diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt deleted file mode 100644 index 30064253f290..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt +++ /dev/null @@ -1,42 +0,0 @@ -Qualcomm PCIe2 PHY controller -============================= - -The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm -platforms. - -Required properties: - - compatible: compatible list, should be: - "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy" - - - reg: offset and length of the PHY register set. - - #phy-cells: must be 0. - - - clocks: a clock-specifier pair for the "pipe" clock - - - vdda-vp-supply: phandle to low voltage regulator - - vdda-vph-supply: phandle to high voltage regulator - - - resets: reset-specifier pairs for the "phy" and "pipe" resets - - reset-names: list of resets, should contain: - "phy" and "pipe" - - - clock-output-names: name of the outgoing clock signal from the PHY PLL - - #clock-cells: must be 0 - -Example: - phy@7786000 { - compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; - reg = <0x07786000 0xb8>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc GCC_PCIE_0_PIPE_ARES>; - reset-names = "phy", "pipe"; - - vdda-vp-supply = <&vreg_l3_1p05>; - vdda-vph-supply = <&vreg_l5_1p8>; - - clock-output-names = "pcie_0_pipe_clk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; -- cgit v1.2.3 From 521d431fcace6122ceb12f0985a9632b0049372b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 23 Nov 2022 12:44:40 +0200 Subject: dt-bindings: phy: qcom,*-qmp-ufs-phy: add clock-cells property Add #clock-cells property to the QMP UFS PHYs to describe them as clock providers. The QMP PHY provides rx and tx symbol clocks for the GCC. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20221123104443.3415267-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml | 3 +++ Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 3 +++ 2 files changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml index be41acbd3b6c..80a5348dbfde 100644 --- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml @@ -75,6 +75,9 @@ patternProperties: minItems: 3 maxItems: 6 + "#clock-cells": + const: 1 + "#phy-cells": const: 0 diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index dde86a19f792..32ed1886fbae 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -43,6 +43,9 @@ properties: vdda-pll-supply: true + "#clock-cells": + const: 1 + "#phy-cells": const: 0 -- cgit v1.2.3 From d0aa1608434c25d5803e01018747cc75d1c1ddc1 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 9 Jan 2023 01:22:21 +0000 Subject: dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs, because it has only one OTG USB controller, no host-only OHCI/EHCI controllers. Add a binding document for it. Following the current situation of one YAML file per SoC, this one is based on allwinner,sun8i-v3s-usb-phy.yaml, but with OHCI/EHCI-related bits removed. (The same driver in Linux, phy-sun4i-usb, covers all these binding files now.) Signed-off-by: Icenowy Zheng Reviewed-by: Rob Herring Reviewed-by: Andre Przywara Reviewed-by: Samuel Holland Signed-off-by: Andre Przywara Link: https://lore.kernel.org/r/20230109012223.4079299-2-andre.przywara@arm.com Signed-off-by: Vinod Koul --- .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 ++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml new file mode 100644 index 000000000000..948839499235 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner F1C100s USB PHY + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + "#phy-cells": + const: 1 + + compatible: + const: allwinner,suniv-f1c100s-usb-phy + + reg: + maxItems: 1 + description: PHY Control registers + + reg-names: + const: phy_ctrl + + clocks: + maxItems: 1 + description: USB OTG PHY bus clock + + clock-names: + const: usb0_phy + + resets: + maxItems: 1 + description: USB OTG reset + + reset-names: + const: usb0_reset + + usb0_id_det-gpios: + maxItems: 1 + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + maxItems: 1 + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + phy@1c13400 { + compatible = "allwinner,suniv-f1c100s-usb-phy"; + reg = <0x01c13400 0x10>; + reg-names = "phy_ctrl"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb0_phy"; + resets = <&ccu RST_USB_PHY0>; + reset-names = "usb0_reset"; + #phy-cells = <1>; + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; + }; -- cgit v1.2.3 From 8b3c08aa648e6669c0bcd34a727f819b844fd684 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 6 Jan 2023 16:28:41 +0100 Subject: dt-bindings: phy: mediatek,tphy: add support for mt7986 Add compatible string for mt7986. Signed-off-by: Frank Wunderlich Acked-by: Krzysztof Kozlowski Reviewed-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Link: https://lore.kernel.org/r/20230106152845.88717-2-linux@fw-web.de Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/mediatek,tphy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 5613cc5106e3..230a17f24966 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -79,6 +79,7 @@ properties: - enum: - mediatek,mt2712-tphy - mediatek,mt7629-tphy + - mediatek,mt7986-tphy - mediatek,mt8183-tphy - mediatek,mt8186-tphy - mediatek,mt8192-tphy -- cgit v1.2.3 From e95f49cb06408edbf729492b5a4a63fe15ec6d4c Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 13 Dec 2022 17:58:41 +0530 Subject: dt-bindings: phy: qcom,qmp-usb: Add SM6115 / SM4250 USB3 PHY Add dt-bindings for USB3 PHY found on Qualcomm SM6115 / SM4250 SoC. Signed-off-by: Bhupesh Sharma Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221213122843.454845-2-bhupesh.sharma@linaro.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml index 0c6b3ba7346b..e81a38281f8c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml @@ -30,6 +30,7 @@ properties: - qcom,sdm845-qmp-usb3-uni-phy - qcom,sdx55-qmp-usb3-uni-phy - qcom,sdx65-qmp-usb3-uni-phy + - qcom,sm6115-qmp-usb3-phy - qcom,sm8150-qmp-usb3-phy - qcom,sm8150-qmp-usb3-uni-phy - qcom,sm8250-qmp-usb3-phy @@ -253,6 +254,7 @@ allOf: contains: enum: - qcom,qcm2290-qmp-usb3-phy + - qcom,sm6115-qmp-usb3-phy then: properties: clocks: @@ -321,6 +323,7 @@ allOf: - qcom,sc8180x-qmp-usb3-phy - qcom,sdx55-qmp-usb3-uni-phy - qcom,sdx65-qmp-usb3-uni-phy + - qcom,sm6115-qmp-usb3-phy - qcom,sm8150-qmp-usb3-uni-phy - qcom,sm8250-qmp-usb3-phy then: -- cgit v1.2.3 From 4214f371d546589edc49dc079d5e4044cfa90f28 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 22 Dec 2022 16:58:05 +0100 Subject: dt-bindings: phy: qcom,usb-hsic-phy: convert to DT schema Convert Qualcomm USB HSIC PHY bindings to DT schema. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20221222155805.139284-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/qcom,usb-hsic-phy.txt | 65 --------------------- .../devicetree/bindings/phy/qcom,usb-hsic-phy.yaml | 67 ++++++++++++++++++++++ 2 files changed, 67 insertions(+), 65 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt b/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt deleted file mode 100644 index 3c7cb2be4b12..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt +++ /dev/null @@ -1,65 +0,0 @@ -Qualcomm's USB HSIC PHY - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the - following: - - "qcom,usb-hsic-phy-mdm9615" - "qcom,usb-hsic-phy-msm8974" - -- #phy-cells: - Usage: required - Value type: - Definition: Should contain 0 - -- clocks: - Usage: required - Value type: - Definition: Should contain clock specifier for phy, calibration and - a calibration sleep clock - -- clock-names: - Usage: required - Value type: - Definition: Should contain "phy, "cal" and "cal_sleep" - -- pinctrl-names: - Usage: required - Value type: - Definition: Should contain "init" and "default" in that order - -- pinctrl-0: - Usage: required - Value type: - Definition: List of pinctrl settings to apply to keep HSIC pins in a glitch - free state - -- pinctrl-1: - Usage: required - Value type: - Definition: List of pinctrl settings to apply to mux out the HSIC pins - -EXAMPLE - -usb-controller { - ulpi { - phy { - compatible = "qcom,usb-hsic-phy-msm8974", - "qcom,usb-hsic-phy"; - #phy-cells = <0>; - pinctrl-names = "init", "default"; - pinctrl-0 = <&hsic_sleep>; - pinctrl-1 = <&hsic_default>; - clocks = <&gcc GCC_USB_HSIC_CLK>, - <&gcc GCC_USB_HSIC_IO_CAL_CLK>, - <&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>; - clock-names = "phy", "cal", "cal_sleep"; - assigned-clocks = <&gcc GCC_USB_HSIC_IO_CAL_CLK>; - assigned-clock-rates = <960000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.yaml new file mode 100644 index 000000000000..077e13a94448 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,usb-hsic-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm USB HSIC PHY Controller + +maintainers: + - Bjorn Andersson + - Vinod Koul + +properties: + compatible: + items: + - enum: + - qcom,usb-hsic-phy-mdm9615 + - qcom,usb-hsic-phy-msm8974 + - const: qcom,usb-hsic-phy + + clocks: + maxItems: 3 + + clock-names: + items: + - const: phy + - const: cal + - const: cal_sleep + + "#phy-cells": + const: 0 + + pinctrl-0: true + pinctrl-1: true + + pinctrl-names: + items: + - const: init + - const: default + +required: + - compatible + - clocks + - clock-names + - "#phy-cells" + - pinctrl-0 + - pinctrl-1 + - pinctrl-names + +additionalProperties: false + +examples: + - | + #include + + phy { + compatible = "qcom,usb-hsic-phy-msm8974", + "qcom,usb-hsic-phy"; + clocks = <&gcc GCC_USB_HSIC_CLK>, + <&gcc GCC_USB_HSIC_IO_CAL_CLK>, + <&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>; + clock-names = "phy", "cal", "cal_sleep"; + #phy-cells = <0>; + pinctrl-names = "init", "default"; + pinctrl-0 = <&hsic_sleep>; + pinctrl-1 = <&hsic_default>; + }; -- cgit v1.2.3 From 9160fb7c39a1e7456e309dbe360b5abbafd4b295 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 23 Dec 2022 17:18:32 +0100 Subject: dt-bindings: phy: qcom,usb-snps-femto-v2: use fallback compatibles Document SoC-specific compatibles with generic fallback (e.g. qcom,usb-snps-hs-7nm-phy) already used in DTSI. Add SoC-specific compatibles for PHY on SDX55 and SDX65. This disallows usage of the qcom,usb-snps-hs-5nm-phy and qcom,usb-snps-hs-7nm-phy generic compatibles alone. Do not touch remaining two compatibles - qcom,usb-snps-femto-v2-phy and qcom,sc8180x-usb-hs-phy - because there are no upstream users, so not sure what was the intention for them. This fixes warnings like: sa8295p-adp.dtb: phy@88e5000: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,sc8280xp-usb-hs-phy', 'qcom,usb-snps-hs-5nm-phy'] is too long 'qcom,sc8280xp-usb-hs-phy' is not one of ['qcom,sm8150-usb-hs-phy', 'qcom,sm8250-usb-hs-phy', 'qcom,sm8350-usb-hs-phy', 'qcom,sm8450-usb-hs-phy'] 'qcom,usb-snps-hs-7nm-phy' was expected Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20221223161835.112079-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul --- .../bindings/phy/qcom,usb-snps-femto-v2.yaml | 33 +++++++++++++--------- 1 file changed, 20 insertions(+), 13 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml index 68e70961beb2..85d405e028b9 100644 --- a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml @@ -14,18 +14,25 @@ description: | properties: compatible: - enum: - - qcom,usb-snps-hs-5nm-phy - - qcom,usb-snps-hs-7nm-phy - - qcom,sc7280-usb-hs-phy - - qcom,sc8180x-usb-hs-phy - - qcom,sc8280xp-usb-hs-phy - - qcom,sm6375-usb-hs-phy - - qcom,sm8150-usb-hs-phy - - qcom,sm8250-usb-hs-phy - - qcom,sm8350-usb-hs-phy - - qcom,sm8450-usb-hs-phy - - qcom,usb-snps-femto-v2-phy + oneOf: + - enum: + - qcom,sc8180x-usb-hs-phy + - qcom,usb-snps-femto-v2-phy + - items: + - enum: + - qcom,sc8280xp-usb-hs-phy + - const: qcom,usb-snps-hs-5nm-phy + - items: + - enum: + - qcom,sc7280-usb-hs-phy + - qcom,sdx55-usb-hs-phy + - qcom,sdx65-usb-hs-phy + - qcom,sm6375-usb-hs-phy + - qcom,sm8150-usb-hs-phy + - qcom,sm8250-usb-hs-phy + - qcom,sm8350-usb-hs-phy + - qcom,sm8450-usb-hs-phy + - const: qcom,usb-snps-hs-7nm-phy reg: maxItems: 1 @@ -160,7 +167,7 @@ examples: #include #include phy@88e2000 { - compatible = "qcom,sm8150-usb-hs-phy"; + compatible = "qcom,sm8150-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; reg = <0x088e2000 0x400>; #phy-cells = <0>; -- cgit v1.2.3 From b1e96b50da7b921be4bc6684682b856cebfe8ad0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 24 Dec 2022 16:42:26 +0100 Subject: dt-bindings: phy: qcom,qusb2: do not define properties in "if" block It is more readable to define properties in top-level "properties:" and restrict them (if needed) per compatible in the "if" block. Defining properties in "if" block does not work correctly with additionalProperties:false: sc7180-trogdor-pazquel-lte-ti.dtb: phy@88e3000: 'qcom,bias-ctrl-value', 'qcom,charge-ctrl-value', 'qcom,hsdisc-trim-value', 'qcom,imp-res-offset-value', 'qcom,preemphasis-level', 'qcom,preemphasis-width' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20221224154226.43417-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 160 +++++++++++---------- 1 file changed, 85 insertions(+), 75 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index 636ea430fbff..7f403e77f320 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -82,81 +82,74 @@ properties: Phandle to TCSR syscon register region. $ref: /schemas/types.yaml#/definitions/phandle -if: - properties: - compatible: - contains: - const: qcom,qusb2-v2-phy -then: - properties: - qcom,imp-res-offset-value: - description: - It is a 6 bit value that specifies offset to be - added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY - tuning parameter that may vary for different boards of same SOC. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 63 - default: 0 - - qcom,bias-ctrl-value: - description: - It is a 6 bit value that specifies bias-ctrl-value. It is a PHY - tuning parameter that may vary for different boards of same SOC. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 63 - default: 32 - - qcom,charge-ctrl-value: - description: - It is a 2 bit value that specifies charge-ctrl-value. It is a PHY - tuning parameter that may vary for different boards of same SOC. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 3 - default: 0 - - qcom,hstx-trim-value: - description: - It is a 4 bit value that specifies tuning for HSTX - output current. - Possible range is - 15mA to 24mA (stepsize of 600 uA). - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 15 - default: 3 - - qcom,preemphasis-level: - description: - It is a 2 bit value that specifies pre-emphasis level. - Possible range is 0 to 15% (stepsize of 5%). - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 3 - default: 2 - - qcom,preemphasis-width: - description: - It is a 1 bit value that specifies how long the HSTX - pre-emphasis (specified using qcom,preemphasis-level) must be in - effect. Duration could be half-bit of full-bit. - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 1 - default: 0 - - qcom,hsdisc-trim-value: - description: - It is a 2 bit value tuning parameter that control disconnect - threshold and may vary for different boards of same SOC. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 3 - default: 0 + qcom,imp-res-offset-value: + description: + It is a 6 bit value that specifies offset to be + added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY + tuning parameter that may vary for different boards of same SOC. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 63 + default: 0 + + qcom,bias-ctrl-value: + description: + It is a 6 bit value that specifies bias-ctrl-value. It is a PHY + tuning parameter that may vary for different boards of same SOC. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 63 + default: 32 + + qcom,charge-ctrl-value: + description: + It is a 2 bit value that specifies charge-ctrl-value. It is a PHY + tuning parameter that may vary for different boards of same SOC. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 0 + + qcom,hstx-trim-value: + description: + It is a 4 bit value that specifies tuning for HSTX + output current. + Possible range is - 15mA to 24mA (stepsize of 600 uA). + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + default: 3 + + qcom,preemphasis-level: + description: + It is a 2 bit value that specifies pre-emphasis level. + Possible range is 0 to 15% (stepsize of 5%). + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 2 + + qcom,preemphasis-width: + description: + It is a 1 bit value that specifies how long the HSTX + pre-emphasis (specified using qcom,preemphasis-level) must be in + effect. Duration could be half-bit of full-bit. + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 1 + default: 0 + + qcom,hsdisc-trim-value: + description: + It is a 2 bit value tuning parameter that control disconnect + threshold and may vary for different boards of same SOC. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 0 required: - compatible @@ -169,6 +162,23 @@ required: - vdda-phy-dpdm-supply - resets +allOf: + - if: + not: + properties: + compatible: + contains: + const: qcom,qusb2-v2-phy + then: + properties: + qcom,imp-res-offset-value: false + qcom,bias-ctrl-value: false + qcom,charge-ctrl-value: false + qcom,hstx-trim-value: false + qcom,preemphasis-level: false + qcom,preemphasis-width: false + qcom,hsdisc-trim-value: false + additionalProperties: false examples: -- cgit v1.2.3 From 9fd4dcd9793d9c2ad423bf117ac0da8a8d7c3351 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 25 Dec 2022 12:59:43 +0100 Subject: dt-bindings: phy: qcom,sc7180-qmp-usb3-dp-phy: correct SC7280 compatibles USB3 DP PHY on SC7280 is used with SM8250 fallback: sc7280-herobrine-evoker.dtb: phy-wrapper@88e9000: compatible: ['qcom,sc7280-qmp-usb3-dp-phy', 'qcom,sm8250-qmp-usb3-dp-phy'] is too long Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20221225115944.55425-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul --- .../bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml index d9d0ab90edb1..97d94c685d7b 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml @@ -19,12 +19,17 @@ maintainers: properties: compatible: - enum: - - qcom,sc7180-qmp-usb3-dp-phy - - qcom,sc7280-qmp-usb3-dp-phy - - qcom,sc8180x-qmp-usb3-dp-phy - - qcom,sdm845-qmp-usb3-dp-phy - - qcom,sm8250-qmp-usb3-dp-phy + oneOf: + - enum: + - qcom,sc7180-qmp-usb3-dp-phy + - qcom,sc8180x-qmp-usb3-dp-phy + - qcom,sdm845-qmp-usb3-dp-phy + - qcom,sm8250-qmp-usb3-dp-phy + - items: + - enum: + - qcom,sc7280-qmp-usb3-dp-phy + - const: qcom,sm8250-qmp-usb3-dp-phy + reg: items: - description: Address and length of PHY's USB serdes block. -- cgit v1.2.3 From e43ddd0ec2b8d1f01a9b63a8760ae7b74ad7b0c9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 25 Dec 2022 12:59:44 +0100 Subject: dt-bindings: phy: qcom,sc7180-qmp-usb3-dp-phy: correct clocks per variants Different variants of Qualcomm USB3 DP PHY take different clocks (according to upstream DTS and Linux driver): sc7280-herobrine-crd.dtb: phy-wrapper@88e9000: clocks: [[43, 151], [39, 0], [43, 153]] is too short sc7280-herobrine-crd.dtb: phy-wrapper@88e9000: clock-names:1: 'cfg_ahb' was expected ... sm8250-hdk.dtb: phy@88e9000: clocks: [[46, 185], [44, 0], [46, 187]] is too short sm8250-hdk.dtb: phy@88e9000: clock-names:1: 'cfg_ahb' was expected Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20221225115944.55425-2-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul --- .../bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml | 72 +++++++++++++++++++--- 1 file changed, 62 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml index 97d94c685d7b..2e19a434c669 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml @@ -51,18 +51,12 @@ properties: ranges: true clocks: - items: - - description: Phy aux clock. - - description: Phy config clock. - - description: 19.2 MHz ref clk. - - description: Phy common block aux clock. + minItems: 3 + maxItems: 4 clock-names: - items: - - const: aux - - const: cfg_ahb - - const: ref - - const: com_aux + minItems: 3 + maxItems: 4 power-domains: maxItems: 1 @@ -171,6 +165,64 @@ required: - vdda-phy-supply - vdda-pll-supply +allOf: + - if: + properties: + compatible: + enum: + - qcom,sc7180-qmp-usb3-dp-phy + - qcom,sdm845-qmp-usb3-dp-phy + then: + properties: + clocks: + items: + - description: Phy aux clock + - description: Phy config clock + - description: 19.2 MHz ref clk + - description: Phy common block aux clock + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: com_aux + + - if: + properties: + compatible: + enum: + - qcom,sc8180x-qmp-usb3-dp-phy + then: + properties: + clocks: + items: + - description: Phy aux clock + - description: 19.2 MHz ref clk + - description: Phy common block aux clock + clock-names: + items: + - const: aux + - const: ref + - const: com_aux + + - if: + properties: + compatible: + enum: + - qcom,sm8250-qmp-usb3-dp-phy + then: + properties: + clocks: + items: + - description: Phy aux clock + - description: Board XO source + - description: Phy common block aux clock + clock-names: + items: + - const: aux + - const: ref_clk_src + - const: com_aux + additionalProperties: false examples: -- cgit v1.2.3 From 9083b009b7e226dd32a1c9568d9867000f6dd559 Mon Sep 17 00:00:00 2001 From: Lux Aliaga Date: Sun, 8 Jan 2023 16:53:32 -0300 Subject: dt-bindings: phy: Add QMP UFS PHY compatible for SM6125 Document the QMP UFS PHY compatible for SM6125. Signed-off-by: Lux Aliaga Reviewed-by: Martin Botka Acked-by: Dhruva Gole Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230108195336.388349-3-they@mint.lgbt Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index 32ed1886fbae..760791de0869 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - qcom,sc8280xp-qmp-ufs-phy + - qcom,sm6125-qmp-ufs-phy reg: maxItems: 1 -- cgit v1.2.3 From 43108bb2f34715b40535178ffceba88e5c7d0a0f Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 9 Jan 2023 13:53:32 +0100 Subject: dt-bindings: phy: convert meson-gxl-usb2-phy.txt to dt-schema Convert the Amlogic Meson GXL USB2 PHY bindings to dt-schema. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Martin Blumenstingl Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20221117-b4-amlogic-bindings-convert-v2-8-36ad050bb625@linaro.org Signed-off-by: Vinod Koul --- .../bindings/phy/amlogic,meson-gxl-usb2-phy.yaml | 56 ++++++++++++++++++++++ .../devicetree/bindings/phy/meson-gxl-usb2-phy.txt | 21 -------- 2 files changed, 56 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-gxl-usb2-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-gxl-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-gxl-usb2-phy.yaml new file mode 100644 index 000000000000..c2f5c9d2fce6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-gxl-usb2-phy.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/amlogic,meson-gxl-usb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson GXL USB2 PHY + +maintainers: + - Neil Armstrong + +properties: + compatible: + const: amlogic,meson-gxl-usb2-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: phy + + resets: + maxItems: 1 + + reset-names: + items: + - const: phy + + "#phy-cells": + const: 0 + + phy-supply: true + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@78000 { + compatible = "amlogic,meson-gxl-usb2-phy"; + reg = <0x78000 0x20>; + clocks = <&xtal>; + clock-names = "phy"; + resets = <&phy_reset>; + reset-names = "phy"; + #phy-cells = <0>; + phy-supply = <&usb2_supply>; + }; diff --git a/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt b/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt deleted file mode 100644 index b84a02ebffdf..000000000000 --- a/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Amlogic Meson GXL and GXM USB2 PHY binding - -Required properties: -- compatible: Should be "amlogic,meson-gxl-usb2-phy" -- reg: The base address and length of the registers -- #phys-cells: must be 0 (see phy-bindings.txt in this directory) - -Optional properties: -- clocks: a phandle to the clock of this PHY -- clock-names: must be "phy" -- resets: a phandle to the reset line of this PHY -- reset-names: must be "phy" -- phy-supply: see phy-bindings.txt in this directory - - -Example: - usb2_phy0: phy@78000 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78000 0x0 0x20>; - }; -- cgit v1.2.3 From fb1ff01307ee3133ae609ad11ebd87379ce5bd9b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 13 Jan 2023 16:08:04 +0100 Subject: dt-bindings: phy: tegra-xusb: Convert to json-schema Convert the Tegra XUSB pad controller bindings from free-form text format to json-schema. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20230113150804.1272555-1-thierry.reding@gmail.com Signed-off-by: Vinod Koul --- .../bindings/phy/nvidia,tegra124-xusb-padctl.txt | 779 -------------------- .../bindings/phy/nvidia,tegra124-xusb-padctl.yaml | 654 +++++++++++++++++ .../bindings/phy/nvidia,tegra186-xusb-padctl.yaml | 544 ++++++++++++++ .../bindings/phy/nvidia,tegra194-xusb-padctl.yaml | 630 +++++++++++++++++ .../bindings/phy/nvidia,tegra210-xusb-padctl.yaml | 786 +++++++++++++++++++++ 5 files changed, 2614 insertions(+), 779 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt create mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml create mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra186-xusb-padctl.yaml create mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml create mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra210-xusb-padctl.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt deleted file mode 100644 index b62397d2bb0c..000000000000 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +++ /dev/null @@ -1,779 +0,0 @@ -Device tree binding for NVIDIA Tegra XUSB pad controller -======================================================== - -The Tegra XUSB pad controller manages a set of I/O lanes (with differential -signals) which connect directly to pins/pads on the SoC package. Each lane -is controlled by a HW block referred to as a "pad" in the Tegra hardware -documentation. Each such "pad" may control either one or multiple lanes, -and thus contains any logic common to all its lanes. Each lane can be -separately configured and powered up. - -Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or -super-speed USB. Other lanes are for various types of low-speed, full-speed -or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller -contains a software-configurable mux that sits between the I/O controller -ports (e.g. PCIe) and the lanes. - -In addition to per-lane configuration, USB 3.0 ports may require additional -settings on a per-board basis. - -Pads will be represented as children of the top-level XUSB pad controller -device tree node. Each lane exposed by the pad will be represented by its -own subnode and can be referenced by users of the lane using the standard -PHY bindings, as described by the phy-bindings.txt file in this directory. - -The Tegra hardware documentation refers to the connection between the XUSB -pad controller and the XUSB controller as "ports". This is confusing since -"port" is typically used to denote the physical USB receptacle. The device -tree binding in this document uses the term "port" to refer to the logical -abstraction of the signals that are routed to a USB receptacle (i.e. a PHY -for the USB signal, the VBUS power supply, the USB 2.0 companion port for -USB 3.0 receptacles, ...). - -Required properties: --------------------- -- compatible: Must be: - - Tegra124: "nvidia,tegra124-xusb-padctl" - - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl" - - Tegra210: "nvidia,tegra210-xusb-padctl" - - Tegra186: "nvidia,tegra186-xusb-padctl" - - Tegra194: "nvidia,tegra194-xusb-padctl" -- reg: Physical base address and length of the controller's registers. -- resets: Must contain an entry for each entry in reset-names. -- reset-names: Must include the following entries: - - "padctl" - -For Tegra124: -- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V. -- avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V. -- avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V. -- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V. - -For Tegra210: -- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V. -- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V. -- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V. -- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V. -- nvidia,pmc: phandle and specifier referring to the Tegra210 PMC node. - -For Tegra186: -- avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY - power supply. Must supply 1.8 V. -- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply - 3.3 V. -- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. -- vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V. - -For Tegra194: -- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply - 3.3 V. -- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. - -Pad nodes: -========== - -A required child node named "pads" contains a list of subnodes, one for each -of the pads exposed by the XUSB pad controller. Each pad may need additional -resources that can be referenced in its pad node. - -The "status" property is used to enable or disable the use of a pad. If set -to "disabled", the pad will not be used on the given board. In order to use -the pad and any of its lanes, this property must be set to "okay". - -For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie -and sata. No extra resources are required for operation of these pads. - -For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is -a description of the properties of each pad. - -UTMI pad: ---------- - -Required properties: -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must contain the following entries: - - "trk": phandle and specifier referring to the USB2 tracking clock - -HSIC pad: ---------- - -Required properties: -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must contain the following entries: - - "trk": phandle and specifier referring to the HSIC tracking clock - -PCIe pad: ---------- - -Required properties: -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must contain the following entries: - - "pll": phandle and specifier referring to the PLLE -- resets: Must contain an entry for each entry in reset-names. -- reset-names: Must contain the following entries: - - "phy": reset for the PCIe UPHY block - -SATA pad: ---------- - -Required properties: -- resets: Must contain an entry for each entry in reset-names. -- reset-names: Must contain the following entries: - - "phy": reset for the SATA UPHY block - - -PHY nodes: -========== - -Each pad node has a child named "lanes" that contains one or more children of -its own, each representing one of the lanes controlled by the pad. - -Required properties: --------------------- -- status: Defines the operation status of the PHY. Valid values are: - - "disabled": the PHY is disabled - - "okay": the PHY is enabled -- #phy-cells: Should be 0. Since each lane represents a single PHY, there is - no need for an additional specifier. -- nvidia,function: The output function of the PHY. See below for a list of - valid functions per SoC generation. - -For Tegra124 and Tegra132, the list of valid PHY nodes is given below: -- usb2: usb2-0, usb2-1, usb2-2 - - functions: "snps", "xusb", "uart" -- ulpi: ulpi-0 - - functions: "snps", "xusb" -- hsic: hsic-0, hsic-1 - - functions: "snps", "xusb" -- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4 - - functions: "pcie", "usb3-ss" -- sata: sata-0 - - functions: "usb3-ss", "sata" - -For Tegra210, the list of valid PHY nodes is given below: -- usb2: usb2-0, usb2-1, usb2-2, usb2-3 - - functions: "snps", "xusb", "uart" -- hsic: hsic-0, hsic-1 - - functions: "snps", "xusb" -- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6 - - functions: "pcie-x1", "usb3-ss", "pcie-x4" -- sata: sata-0 - - functions: "usb3-ss", "sata" - -For Tegra194, the list of valid PHY nodes is given below: -- usb2: usb2-0, usb2-1, usb2-2, usb2-3 - - functions: "xusb" -- usb3: usb3-0, usb3-1, usb3-2, usb3-3 - - functions: "xusb" - -Port nodes: -=========== - -A required child node named "ports" contains a list of all the ports exposed -by the XUSB pad controller. Per-port configuration is only required for USB. - -USB2 ports: ------------ - -Required properties: -- status: Defines the operation status of the port. Valid values are: - - "disabled": the port is disabled - - "okay": the port is enabled -- mode: A string that determines the mode in which to run the port. Valid - values are: - - "host": for USB host mode - - "device": for USB device mode - - "otg": for USB OTG mode - -Required properties for OTG/Peripheral capable USB2 ports: -- usb-role-switch: Boolean property to indicate that the port support OTG or - peripheral mode. If present, the port supports switching between USB host - and peripheral roles. Connector should be added as subnode. - See usb/usb-conn-gpio.txt. - -Optional properties: -- nvidia,internal: A boolean property whose presence determines that a port - is internal. In the absence of this property the port is considered to be - external. -- vbus-supply: phandle to a regulator supplying the VBUS voltage. - -ULPI ports: ------------ - -Optional properties: -- status: Defines the operation status of the port. Valid values are: - - "disabled": the port is disabled - - "okay": the port is enabled -- nvidia,internal: A boolean property whose presence determines that a port - is internal. In the absence of this property the port is considered to be - external. -- vbus-supply: phandle to a regulator supplying the VBUS voltage. - -HSIC ports: ------------ - -Required properties: -- status: Defines the operation status of the port. Valid values are: - - "disabled": the port is disabled - - "okay": the port is enabled - -Optional properties: -- vbus-supply: phandle to a regulator supplying the VBUS voltage. - -Super-speed USB ports: ----------------------- - -Required properties: -- status: Defines the operation status of the port. Valid values are: - - "disabled": the port is disabled - - "okay": the port is enabled -- nvidia,usb2-companion: A single cell that specifies the physical port number - to map this super-speed USB port to. The range of valid port numbers varies - with the SoC generation: - - 0-2: for Tegra124 and Tegra132 - - 0-3: for Tegra210 - -Optional properties: -- nvidia,internal: A boolean property whose presence determines that a port - is internal. In the absence of this property the port is considered to be - external. - -- maximum-speed: Only for Tegra194. A string property that specifies maximum - supported speed of a usb3 port. Valid values are: - - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed. - - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only. - -For Tegra124 and Tegra132, the XUSB pad controller exposes the following -ports: -- 3x USB2: usb2-0, usb2-1, usb2-2 -- 1x ULPI: ulpi-0 -- 2x HSIC: hsic-0, hsic-1 -- 2x super-speed USB: usb3-0, usb3-1 - -For Tegra210, the XUSB pad controller exposes the following ports: -- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3 -- 2x HSIC: hsic-0, hsic-1 -- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 - -For Tegra194, the XUSB pad controller exposes the following ports: -- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3 -- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 - -Examples: -========= - -Tegra124 and Tegra132: ----------------------- - -SoC include: - - padctl@7009f000 { - /* for Tegra124 */ - compatible = "nvidia,tegra124-xusb-padctl"; - /* for Tegra132 */ - compatible = "nvidia,tegra132-xusb-padctl", - "nvidia,tegra124-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - pads { - usb2 { - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - ulpi { - status = "disabled"; - - lanes { - ulpi-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - hsic-1 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - pcie { - status = "disabled"; - - lanes { - pcie-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-3 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-4 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - sata { - status = "disabled"; - - lanes { - sata-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - ulpi-0 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - hsic-1 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - }; - }; - -Board file: - - padctl@7009f000 { - status = "okay"; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie"; - status = "okay"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - nvidia,function = "sata"; - status = "okay"; - }; - }; - }; - }; - - ports { - /* Micro A/B */ - usb2-0 { - status = "okay"; - mode = "otg"; - }; - - /* Mini PCIe */ - usb2-1 { - status = "okay"; - mode = "host"; - }; - - /* USB3 */ - usb2-2 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_usb3_vbus>; - }; - - usb3-0 { - nvidia,port = <2>; - status = "okay"; - }; - }; - }; - -Tegra210: ---------- - -SoC include: - - padctl@7009f000 { - compatible = "nvidia,tegra210-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - status = "disabled"; - - pads { - usb2 { - clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-3 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - hsic-1 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - pcie { - clocks = <&tegra_car TEGRA210_CLK_PLL_E>; - clock-names = "pll"; - resets = <&tegra_car 205>; - reset-names = "phy"; - status = "disabled"; - - lanes { - pcie-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-3 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-4 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-5 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-6 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - sata { - clocks = <&tegra_car TEGRA210_CLK_PLL_E>; - clock-names = "pll"; - resets = <&tegra_car 204>; - reset-names = "phy"; - status = "disabled"; - - lanes { - sata-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - usb2-3 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - hsic-1 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - - usb3-2 { - status = "disabled"; - }; - - usb3-3 { - status = "disabled"; - }; - }; - }; - -Board file: - - padctl@7009f000 { - status = "okay"; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-3 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "pcie-x1"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-3 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-5 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-6 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - nvidia,function = "sata"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - mode = "otg"; - }; - - usb2-1 { - status = "okay"; - vbus-supply = <&vdd_5v0_rtl>; - mode = "host"; - }; - - usb2-2 { - status = "okay"; - vbus-supply = <&vdd_usb_vbus>; - mode = "host"; - }; - - usb2-3 { - status = "okay"; - mode = "host"; - }; - - usb3-0 { - status = "okay"; - nvidia,lanes = "pcie-6"; - nvidia,port = <1>; - }; - - usb3-1 { - status = "okay"; - nvidia,lanes = "pcie-5"; - nvidia,port = <2>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml new file mode 100644 index 000000000000..33b41b6b2fd5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.yaml @@ -0,0 +1,654 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra124 XUSB pad controller + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The Tegra XUSB pad controller manages a set of I/O lanes (with differential + signals) which connect directly to pins/pads on the SoC package. Each lane + is controlled by a HW block referred to as a "pad" in the Tegra hardware + documentation. Each such "pad" may control either one or multiple lanes, + and thus contains any logic common to all its lanes. Each lane can be + separately configured and powered up. + + Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or + super-speed USB. Other lanes are for various types of low-speed, full-speed + or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller + contains a software-configurable mux that sits between the I/O controller + ports (e.g. PCIe) and the lanes. + + In addition to per-lane configuration, USB 3.0 ports may require additional + settings on a per-board basis. + + Pads will be represented as children of the top-level XUSB pad controller + device tree node. Each lane exposed by the pad will be represented by its + own subnode and can be referenced by users of the lane using the standard + PHY bindings, as described by the phy-bindings.txt file in this directory. + + The Tegra hardware documentation refers to the connection between the XUSB + pad controller and the XUSB controller as "ports". This is confusing since + "port" is typically used to denote the physical USB receptacle. The device + tree binding in this document uses the term "port" to refer to the logical + abstraction of the signals that are routed to a USB receptacle (i.e. a PHY + for the USB signal, the VBUS power supply, the USB 2.0 companion port for + USB 3.0 receptacles, ...). + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra124-xusb-padctl + + - items: + - const: nvidia,tegra132-xusb-padctl + - const: nvidia,tegra124-xusb-padctl + + reg: + maxItems: 1 + + interrupts: + items: + - description: XUSB pad controller interrupt + + resets: + items: + - description: pad controller reset + + reset-names: + items: + - const: padctl + + avdd-pll-utmip-supply: + description: UTMI PLL power supply. Must supply 1.8 V. + + avdd-pll-erefe-supply: + description: PLLE reference PLL power supply. Must supply 1.05 V. + + avdd-pex-pll-supply: + description: PCIe/USB3 PLL power supply. Must supply 1.05 V. + + hvdd-pex-pll-e-supply: + description: High-voltage PLLE power supply. Must supply 3.3 V. + + pads: + description: A required child node named "pads" contains a list of + subnodes, one for each of the pads exposed by the XUSB pad controller. + Each pad may need additional resources that can be referenced in its + pad node. + + The "status" property is used to enable or disable the use of a pad. + If set to "disabled", the pad will not be used on the given board. In + order to use the pad and any of its lanes, this property must be set + to "okay" or be absent. + type: object + additionalProperties: false + properties: + usb2: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: USB2 tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + usb2-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + usb2-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + ulpi: + type: object + additionalProperties: false + properties: + lanes: + type: object + additionalProperties: false + properties: + ulpi-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb ] + + hsic: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: HSIC tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + hsic-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb ] + + hsic-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb ] + + pcie: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: PLLE clock + + clock-names: + items: + - const: pll + + resets: + items: + - description: reset for the PCIe UPHY block + + reset-names: + items: + - const: phy + + lanes: + type: object + additionalProperties: false + properties: + pcie-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie, usb3-ss ] + + pcie-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie, usb3-ss ] + + pcie-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie, usb3-ss ] + + pcie-3: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie, usb3-ss ] + + pcie-4: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie, usb3-ss ] + + sata: + type: object + additionalProperties: false + properties: + resets: + items: + - description: reset for the SATA UPHY block + + reset-names: + items: + - const: phy + + lanes: + type: object + additionalProperties: false + properties: + sata-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ sata, usb3-ss ] + + ports: + description: A required child node named "ports" contains a list of + subnodes, one for each of the ports exposed by the XUSB pad controller. + Each port may need additional resources that can be referenced in its + port node. + + The "status" property is used to enable or disable the use of a port. + If set to "disabled", the port will not be used on the given board. In + order to use the port, this property must be set to "okay". + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb2-1: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb2-2: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + ulpi-0: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + hsic-0: + type: object + additionalProperties: false + properties: + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + hsic-1: + type: object + additionalProperties: false + properties: + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-0: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-1: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + +additionalProperties: false + +required: + - compatible + - reg + - resets + - reset-names + - avdd-pll-utmip-supply + - avdd-pll-erefe-supply + - avdd-pex-pll-supply + - hvdd-pex-pll-e-supply + +examples: + # Tegra124 and Tegra132 + - | + #include + + padctl@7009f000 { + compatible = "nvidia,tegra124-xusb-padctl"; + reg = <0x7009f000 0x1000>; + interrupts = ; + resets = <&tegra_car 142>; + reset-names = "padctl"; + + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + + pads { + usb2 { + lanes { + usb2-0 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + }; + }; + + ulpi { + lanes { + ulpi-0 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + hsic { + lanes { + hsic-0 { + status = "disabled"; + #phy-cells = <0>; + }; + + hsic-1 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + pcie { + lanes { + pcie-0 { + nvidia,function = "usb3-ss"; + #phy-cells = <0>; + }; + + pcie-1 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-2 { + nvidia,function = "pcie"; + #phy-cells = <0>; + }; + + pcie-3 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-4 { + nvidia,function = "pcie"; + #phy-cells = <0>; + }; + }; + }; + + sata { + lanes { + sata-0 { + nvidia,function = "sata"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + /* Micro A/B */ + usb2-0 { + mode = "otg"; + }; + + /* Mini PCIe */ + usb2-1 { + mode = "host"; + }; + + /* USB3 */ + usb2-2 { + vbus-supply = <&vdd_usb3_vbus>; + mode = "host"; + }; + + ulpi-0 { + status = "disabled"; + }; + + hsic-0 { + status = "disabled"; + }; + + hsic-1 { + status = "disabled"; + }; + + usb3-0 { + nvidia,usb2-companion = <2>; + }; + + usb3-1 { + status = "disabled"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra186-xusb-padctl.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra186-xusb-padctl.yaml new file mode 100644 index 000000000000..8b1d5a8529e3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra186-xusb-padctl.yaml @@ -0,0 +1,544 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 XUSB pad controller + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The Tegra XUSB pad controller manages a set of I/O lanes (with differential + signals) which connect directly to pins/pads on the SoC package. Each lane + is controlled by a HW block referred to as a "pad" in the Tegra hardware + documentation. Each such "pad" may control either one or multiple lanes, + and thus contains any logic common to all its lanes. Each lane can be + separately configured and powered up. + + Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or + super-speed USB. Other lanes are for various types of low-speed, full-speed + or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller + contains a software-configurable mux that sits between the I/O controller + ports (e.g. PCIe) and the lanes. + + In addition to per-lane configuration, USB 3.0 ports may require additional + settings on a per-board basis. + + Pads will be represented as children of the top-level XUSB pad controller + device tree node. Each lane exposed by the pad will be represented by its + own subnode and can be referenced by users of the lane using the standard + PHY bindings, as described by the phy-bindings.txt file in this directory. + + The Tegra hardware documentation refers to the connection between the XUSB + pad controller and the XUSB controller as "ports". This is confusing since + "port" is typically used to denote the physical USB receptacle. The device + tree binding in this document uses the term "port" to refer to the logical + abstraction of the signals that are routed to a USB receptacle (i.e. a PHY + for the USB signal, the VBUS power supply, the USB 2.0 companion port for + USB 3.0 receptacles, ...). + +properties: + compatible: + const: nvidia,tegra186-xusb-padctl + + reg: + items: + - description: pad controller registers + - description: AO registers + + interrupts: + items: + - description: XUSB pad controller interrupt + + reg-names: + items: + - const: padctl + - const: ao + + resets: + items: + - description: pad controller reset + + reset-names: + items: + - const: padctl + + avdd-pll-erefeut-supply: + description: UPHY brick and reference clock as well as UTMI PHY + power supply. Must supply 1.8 V. + + avdd-usb-supply: + description: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must + supply 3.3 V. + + vclamp-usb-supply: + description: Bias rail for USB pad. Must supply 1.8 V. + + vddio-hsic-supply: + description: HSIC PHY power supply. Must supply 1.2 V. + + pads: + description: A required child node named "pads" contains a list of + subnodes, one for each of the pads exposed by the XUSB pad controller. + Each pad may need additional resources that can be referenced in its + pad node. + + The "status" property is used to enable or disable the use of a pad. + If set to "disabled", the pad will not be used on the given board. In + order to use the pad and any of its lanes, this property must be set + to "okay" or be absent. + type: object + additionalProperties: false + properties: + usb2: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: USB2 tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb2-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb2-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + hsic: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: HSIC tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + hsic-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3: + type: object + additionalProperties: false + properties: + lanes: + type: object + additionalProperties: false + properties: + usb3-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + ports: + description: A required child node named "ports" contains a list of + subnodes, one for each of the ports exposed by the XUSB pad controller. + Each port may need additional resources that can be referenced in its + port node. + + The "status" property is used to enable or disable the use of a port. + If set to "disabled", the port will not be used on the given board. In + order to use the port, this property must be set to "okay". + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-1: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-2: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + hsic-0: + type: object + additionalProperties: false + + usb3-0: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-1: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-2: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + +additionalProperties: false + +required: + - compatible + - reg + - resets + - reset-names + - avdd-pll-erefeut-supply + - avdd-usb-supply + - vclamp-usb-supply + - vddio-hsic-supply + +examples: + - | + #include + #include + #include + #include + + padctl@3520000 { + compatible = "nvidia,tegra186-xusb-padctl"; + reg = <0x03520000 0x1000>, + <0x03540000 0x1000>; + reg-names = "padctl", "ao"; + interrupts = ; + + resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; + reset-names = "padctl"; + + avdd-pll-erefeut-supply = <&vdd_1v8_pll>; + avdd-usb-supply = <&vdd_3v3_sys>; + vclamp-usb-supply = <&vdd_1v8>; + vddio-hsic-supply = <&gnd>; + + pads { + usb2 { + clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + }; + }; + + hsic { + clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; + clock-names = "trk"; + status = "disabled"; + + lanes { + hsic-0 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb3-1 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb3-2 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + mode = "otg"; + vbus-supply = <&vdd_usb0>; + usb-role-switch; + + connector { + compatible = "gpio-usb-b-connector", + "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + vbus-gpios = <&gpio TEGRA186_MAIN_GPIO(X, 7) GPIO_ACTIVE_LOW>; + id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + }; + + usb2-1 { + vbus-supply = <&vdd_usb1>; + mode = "host"; + }; + + usb2-2 { + status = "disabled"; + }; + + hsic-0 { + status = "disabled"; + }; + + usb3-0 { + nvidia,usb2-companion = <1>; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml new file mode 100644 index 000000000000..9d4eb7e6fbb7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml @@ -0,0 +1,630 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra194 XUSB pad controller + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The Tegra XUSB pad controller manages a set of I/O lanes (with differential + signals) which connect directly to pins/pads on the SoC package. Each lane + is controlled by a HW block referred to as a "pad" in the Tegra hardware + documentation. Each such "pad" may control either one or multiple lanes, + and thus contains any logic common to all its lanes. Each lane can be + separately configured and powered up. + + Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or + super-speed USB. Other lanes are for various types of low-speed, full-speed + or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller + contains a software-configurable mux that sits between the I/O controller + ports (e.g. PCIe) and the lanes. + + In addition to per-lane configuration, USB 3.0 ports may require additional + settings on a per-board basis. + + Pads will be represented as children of the top-level XUSB pad controller + device tree node. Each lane exposed by the pad will be represented by its + own subnode and can be referenced by users of the lane using the standard + PHY bindings, as described by the phy-bindings.txt file in this directory. + + The Tegra hardware documentation refers to the connection between the XUSB + pad controller and the XUSB controller as "ports". This is confusing since + "port" is typically used to denote the physical USB receptacle. The device + tree binding in this document uses the term "port" to refer to the logical + abstraction of the signals that are routed to a USB receptacle (i.e. a PHY + for the USB signal, the VBUS power supply, the USB 2.0 companion port for + USB 3.0 receptacles, ...). + +properties: + compatible: + const: nvidia,tegra194-xusb-padctl + + reg: + items: + - description: pad controller registers + - description: AO registers + + reg-names: + items: + - const: padctl + - const: ao + + interrupts: + items: + - description: XUSB pad controller interrupt + + resets: + items: + - description: pad controller reset + + reset-names: + items: + - const: padctl + + avdd-usb-supply: + description: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must + supply 3.3 V. + + vclamp-usb-supply: + description: Bias rail for USB pad. Must supply 1.8 V. + + pads: + description: A required child node named "pads" contains a list of + subnodes, one for each of the pads exposed by the XUSB pad controller. + Each pad may need additional resources that can be referenced in its + pad node. + + The "status" property is used to enable or disable the use of a pad. + If set to "disabled", the pad will not be used on the given board. In + order to use the pad and any of its lanes, this property must be set + to "okay" or absent. + type: object + additionalProperties: false + properties: + usb2: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: USB2 tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb2-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb2-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb2-3: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3: + type: object + additionalProperties: false + properties: + lanes: + type: object + additionalProperties: false + properties: + usb3-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + usb3-3: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ xusb ] + + ports: + description: A required child node named "ports" contains a list of + subnodes, one for each of the ports exposed by the XUSB pad controller. + Each port may need additional resources that can be referenced in its + port node. + + The "status" property is used to enable or disable the use of a port. + If set to "disabled", the port will not be used on the given board. In + order to use the port, this property must be set to "okay". + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-1: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-2: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-3: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb3-0: + type: object + additionalProperties: false + properties: + maximum-speed: + description: A string property that specifies the maximum + supported speed of a USB3 port. + $ref: /schemas/types.yaml#/definitions/string + oneOf: + - description: The USB3 port supports USB 3.1 Gen 2 speed. + This is the default. + const: super-speed-plus + - description: The USB3 port supports USB 3.1 Gen 1 speed + only. + const: super-speed + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-1: + type: object + additionalProperties: false + properties: + maximum-speed: + description: A string property that specifies the maximum + supported speed of a USB3 port. + $ref: /schemas/types.yaml#/definitions/string + oneOf: + - description: The USB3 port supports USB 3.1 Gen 2 speed. + This is the default. + const: super-speed-plus + - description: The USB3 port supports USB 3.1 Gen 1 speed + only. + const: super-speed + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-2: + type: object + additionalProperties: false + properties: + maximum-speed: + description: A string property that specifies the maximum + supported speed of a USB3 port. + $ref: /schemas/types.yaml#/definitions/string + oneOf: + - description: The USB3 port supports USB 3.1 Gen 2 speed. + This is the default. + const: super-speed-plus + - description: The USB3 port supports USB 3.1 Gen 1 speed + only. + const: super-speed + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-3: + type: object + additionalProperties: false + properties: + maximum-speed: + description: A string property that specifies the maximum + supported speed of a USB3 port. + $ref: /schemas/types.yaml#/definitions/string + oneOf: + - description: The USB3 port supports USB 3.1 Gen 2 speed. + This is the default. + const: super-speed-plus + - description: The USB3 port supports USB 3.1 Gen 1 speed + only. + const: super-speed + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + +additionalProperties: false + +required: + - compatible + - reg + - resets + - reset-names + - avdd-usb-supply + - vclamp-usb-supply + +examples: + - | + #include + #include + #include + #include + + padctl@3520000 { + compatible = "nvidia,tegra194-xusb-padctl"; + reg = <0x03520000 0x1000>, + <0x03540000 0x1000>; + reg-names = "padctl", "ao"; + interrupts = ; + + resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; + reset-names = "padctl"; + + avdd-usb-supply = <&vdd_usb_3v3>; + vclamp-usb-supply = <&vdd_1v8ao>; + + pads { + usb2 { + clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-3 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-3 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { + vbus-supply = <&vdd_5v0_sys>; + mode = "host"; + }; + + usb2-2 { + status = "disabled"; + }; + + usb2-3 { + vbus-supply = <&vdd_5v_sata>; + mode = "host"; + }; + + usb3-0 { + vbus-supply = <&vdd_5v0_sys>; + nvidia,usb2-companion = <1>; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + maximum-speed = "super-speed"; + vbus-supply = <&vdd_5v0_sys>; + nvidia,usb2-companion = <3>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra210-xusb-padctl.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra210-xusb-padctl.yaml new file mode 100644 index 000000000000..d16bd6e47f90 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra210-xusb-padctl.yaml @@ -0,0 +1,786 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra210 XUSB pad controller + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The Tegra XUSB pad controller manages a set of I/O lanes (with differential + signals) which connect directly to pins/pads on the SoC package. Each lane + is controlled by a HW block referred to as a "pad" in the Tegra hardware + documentation. Each such "pad" may control either one or multiple lanes, + and thus contains any logic common to all its lanes. Each lane can be + separately configured and powered up. + + Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or + super-speed USB. Other lanes are for various types of low-speed, full-speed + or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller + contains a software-configurable mux that sits between the I/O controller + ports (e.g. PCIe) and the lanes. + + In addition to per-lane configuration, USB 3.0 ports may require additional + settings on a per-board basis. + + Pads will be represented as children of the top-level XUSB pad controller + device tree node. Each lane exposed by the pad will be represented by its + own subnode and can be referenced by users of the lane using the standard + PHY bindings, as described by the phy-bindings.txt file in this directory. + + The Tegra hardware documentation refers to the connection between the XUSB + pad controller and the XUSB controller as "ports". This is confusing since + "port" is typically used to denote the physical USB receptacle. The device + tree binding in this document uses the term "port" to refer to the logical + abstraction of the signals that are routed to a USB receptacle (i.e. a PHY + for the USB signal, the VBUS power supply, the USB 2.0 companion port for + USB 3.0 receptacles, ...). + +properties: + compatible: + const: nvidia,tegra210-xusb-padctl + + reg: + maxItems: 1 + + resets: + items: + - description: pad controller reset + + interrupts: + items: + - description: XUSB pad controller interrupt + + reset-names: + items: + - const: padctl + + avdd-pll-utmip-supply: + description: UTMI PLL power supply. Must supply 1.8 V. + + avdd-pll-uerefe-supply: + description: PLLE reference PLL power supply. Must supply 1.05 V. + + dvdd-pex-pll-supply: + description: PCIe/USB3 PLL power supply. Must supply 1.05 V. + + hvdd-pex-pll-e-supply: + description: High-voltage PLLE power supply. Must supply 1.8 V. + + nvidia,pmc: + description: phandle to the Tegra Power Management Controller (PMC) node + $ref: /schemas/types.yaml#/definitions/phandle + + pads: + description: A required child node named "pads" contains a list of + subnodes, one for each of the pads exposed by the XUSB pad controller. + Each pad may need additional resources that can be referenced in its + pad node. + + The "status" property is used to enable or disable the use of a pad. + If set to "disabled", the pad will not be used on the given board. In + order to use the pad and any of its lanes, this property must be set + to "okay" or be absent. + type: object + additionalProperties: false + properties: + usb2: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: USB2 tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + usb2-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + usb2-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + usb2-3: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb, uart ] + + hsic: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: HSIC tracking clock + + clock-names: + items: + - const: trk + + lanes: + type: object + additionalProperties: false + properties: + hsic-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb ] + + hsic-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ snps, xusb ] + + pcie: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: PCIe PLL clock source + + clock-names: + items: + - const: pll + + resets: + items: + - description: PCIe PHY reset + + reset-names: + items: + - const: phy + + lanes: + type: object + additionalProperties: false + properties: + pcie-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + pcie-1: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + pcie-2: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + pcie-3: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + pcie-4: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + pcie-5: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + pcie-6: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ pcie-x1, usb3-ss, pcie-x4 ] + + sata: + type: object + additionalProperties: false + properties: + clocks: + items: + - description: SATA PLL clock source + + clock-names: + items: + - const: pll + + resets: + items: + - description: SATA PHY reset + + reset-names: + items: + - const: phy + + lanes: + type: object + additionalProperties: false + properties: + sata-0: + type: object + additionalProperties: false + properties: + "#phy-cells": + const: 0 + + nvidia,function: + description: Function selection for this lane. + $ref: /schemas/types.yaml#/definitions/string + enum: [ usb3-ss, sata ] + + ports: + description: A required child node named "ports" contains a list of + subnodes, one for each of the ports exposed by the XUSB pad controller. + Each port may need additional resources that can be referenced in its + port node. + + The "status" property is used to enable or disable the use of a port. + If set to "disabled", the port will not be used on the given board. In + order to use the port, this property must be set to "okay". + type: object + additionalProperties: false + properties: + usb2-0: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-1: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-2: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + usb2-3: + type: object + additionalProperties: false + properties: + # no need to further describe this because the connector will + # match on gpio-usb-b-connector or usb-b-connector and cause + # that binding to be selected for the subnode + connector: + type: object + + mode: + description: A string that determines the mode in which to + run the port. + $ref: /schemas/types.yaml#/definitions/string + enum: [ host, peripheral, otg ] + + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + usb-role-switch: + description: | + A boolean property whole presence indicates that the port + supports OTG or peripheral mode. If present, the port + supports switching between USB host and peripheral roles. + A connector must be added as a subnode in that case. + + See ../connector/usb-connector.yaml. + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + dependencies: + usb-role-switch: [ connector ] + + hsic-0: + type: object + additionalProperties: false + properties: + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + hsic-1: + type: object + additionalProperties: false + properties: + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-0: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-1: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-2: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + + usb3-3: + type: object + additionalProperties: false + properties: + nvidia,internal: + description: A boolean property whose presence determines + that a port is internal. In the absence of this property + the port is considered to be external. + $ref: /schemas/types.yaml#/definitions/flag + + nvidia,usb2-companion: + description: A single cell that specifies the physical port + number to map this super-speed USB port to. The range of + valid port numbers varies with the SoC generation. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS + voltage. + +additionalProperties: false + +required: + - avdd-pll-utmip-supply + - avdd-pll-uerefe-supply + - dvdd-pex-pll-supply + - hvdd-pex-pll-e-supply + +examples: + - | + #include + #include + #include + + padctl@7009f000 { + compatible = "nvidia,tegra210-xusb-padctl"; + reg = <0x7009f000 0x1000>; + interrupts = ; + resets = <&tegra_car 142>; + reset-names = "padctl"; + + avdd-pll-utmip-supply = <&vdd_1v8>; + avdd-pll-uerefe-supply = <&vdd_pex_1v05>; + dvdd-pex-pll-supply = <&vdd_pex_1v05>; + hvdd-pex-pll-e-supply = <&vdd_1v8>; + + pads { + usb2 { + clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + + usb2-3 { + nvidia,function = "xusb"; + #phy-cells = <0>; + }; + }; + }; + + hsic { + clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; + clock-names = "trk"; + status = "disabled"; + + lanes { + hsic-0 { + status = "disabled"; + #phy-cells = <0>; + }; + + hsic-1 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + pcie { + clocks = <&tegra_car TEGRA210_CLK_PLL_E>; + clock-names = "pll"; + resets = <&tegra_car 205>; + reset-names = "phy"; + + lanes { + pcie-0 { + nvidia,function = "pcie-x1"; + #phy-cells = <0>; + }; + + pcie-1 { + nvidia,function = "pcie-x4"; + #phy-cells = <0>; + }; + + pcie-2 { + nvidia,function = "pcie-x4"; + #phy-cells = <0>; + }; + + pcie-3 { + nvidia,function = "pcie-x4"; + #phy-cells = <0>; + }; + + pcie-4 { + nvidia,function = "pcie-x4"; + #phy-cells = <0>; + }; + + pcie-5 { + nvidia,function = "usb3-ss"; + #phy-cells = <0>; + }; + + pcie-6 { + nvidia,function = "usb3-ss"; + #phy-cells = <0>; + }; + }; + }; + + sata { + clocks = <&tegra_car TEGRA210_CLK_PLL_E>; + clock-names = "pll"; + resets = <&tegra_car 204>; + reset-names = "phy"; + + lanes { + sata-0 { + nvidia,function = "sata"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + mode = "peripheral"; + usb-role-switch; + + connector { + compatible = "gpio-usb-b-connector", + "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_LOW>; + }; + }; + + usb2-1 { + vbus-supply = <&vdd_5v0_rtl>; + mode = "host"; + }; + + usb2-2 { + vbus-supply = <&vdd_usb_vbus>; + mode = "host"; + }; + + usb2-3 { + mode = "host"; + }; + + hsic-0 { + status = "disabled"; + }; + + hsic-1 { + status = "disabled"; + }; + + usb3-0 { + nvidia,usb2-companion = <1>; + }; + + usb3-1 { + nvidia,usb2-companion = <2>; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + status = "disabled"; + }; + }; + }; -- cgit v1.2.3 From 7f3d995c35da5d6300e019fa6434c0776ba0600a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 18 Jan 2023 11:39:23 +0100 Subject: dt-bindings: phy: ti,tcan104x-can: Document NXP TJR1443 The NXP TJR1443 High-speed CAN transceiver with Sleep mode is a pin-compatible alternative for the TI TCAN1043. Signed-off-by: Geert Uytterhoeven Acked-by: Marc Kleine-Budde Acked-by: Rob Herring Link: https://lore.kernel.org/r/6ee5e2ce00019bd3f77d6a702b38bab1a45f3bb0.1674037830.git.geert+renesas@glider.be Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml b/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml index 02b76f15e717..237295b2b5a8 100644 --- a/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml +++ b/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml @@ -15,6 +15,7 @@ properties: compatible: enum: + - nxp,tjr1443 - ti,tcan1042 - ti,tcan1043 -- cgit v1.2.3 From fdb5a86287c178df3d1ea064b93264dda3a7f697 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 18 Jan 2023 00:41:43 +0200 Subject: dt-bindings: phy: Add QMP UFS PHY comptible for SM8550 Document the QMP UFS PHY compatible for SM8550. Signed-off-by: Abel Vesa Acked-by: Krzysztof Kozlowski Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20230117224148.1914627-2-abel.vesa@linaro.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index 760791de0869..64ed331880f6 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -18,6 +18,7 @@ properties: enum: - qcom,sc8280xp-qmp-ufs-phy - qcom,sm6125-qmp-ufs-phy + - qcom,sm8550-qmp-ufs-phy reg: maxItems: 1 -- cgit v1.2.3 From 5e2714556fa2b4e6ba684e4ebcbdd27c7ea65b22 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 23 Jan 2023 14:29:49 +0100 Subject: dt-bindings: phy: qcom,qmp-usb3-dp: Add sm6350 compatible Add the compatible describing the combo phy found on SM6350. Reviewed-by: Johan Hovold Acked-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20230120-sm6350-usbphy-v4-1-4d700a90ba16@fairphone.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml index 6f31693d9868..0764cd977e76 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - qcom,sc8280xp-qmp-usb43dp-phy + - qcom,sm6350-qmp-usb3-dp-phy reg: maxItems: 1 -- cgit v1.2.3 From 1bd9a7b4afd5e0b938868a90b16d514c19808e6c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 24 Jan 2023 19:37:20 +0100 Subject: phy: Remove unused phy_optional_get() There were never any upstream users of this function since its introduction almost 10 years ago. Besides, the dummy for phy_optional_get() should have returned NULL instead of an error code. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/df61992b1d66bccf4e6e1eafae94a7f7d7629f34.1674584626.git.geert+renesas@glider.be Signed-off-by: Vinod Koul --- Documentation/driver-api/phy/phy.rst | 11 +++++------ drivers/phy/phy-core.c | 21 --------------------- include/linux/phy/phy.h | 7 ------- 3 files changed, 5 insertions(+), 34 deletions(-) (limited to 'Documentation') diff --git a/Documentation/driver-api/phy/phy.rst b/Documentation/driver-api/phy/phy.rst index 8e8b3e8f9523..26467dd4f291 100644 --- a/Documentation/driver-api/phy/phy.rst +++ b/Documentation/driver-api/phy/phy.rst @@ -103,7 +103,6 @@ it. This framework provides the following APIs to get a reference to the PHY. :: struct phy *phy_get(struct device *dev, const char *string); - struct phy *phy_optional_get(struct device *dev, const char *string); struct phy *devm_phy_get(struct device *dev, const char *string); struct phy *devm_phy_optional_get(struct device *dev, const char *string); @@ -111,15 +110,15 @@ it. This framework provides the following APIs to get a reference to the PHY. struct device_node *np, int index); -phy_get, phy_optional_get, devm_phy_get and devm_phy_optional_get can -be used to get the PHY. In the case of dt boot, the string arguments +phy_get, devm_phy_get and devm_phy_optional_get can be used to get the PHY. +In the case of dt boot, the string arguments should contain the phy name as given in the dt data and in the case of non-dt boot, it should contain the label of the PHY. The two devm_phy_get associates the device with the PHY using devres on successful PHY get. On driver detach, release function is invoked on -the devres data and devres data is freed. phy_optional_get and -devm_phy_optional_get should be used when the phy is optional. These -two functions will never return -ENODEV, but instead returns NULL when +the devres data and devres data is freed. +devm_phy_optional_get should be used when the phy is optional. This +function will never return -ENODEV, but instead returns NULL when the phy cannot be found.Some generic drivers, such as ehci, may use multiple phys and for such drivers referencing phy(s) by name(s) does not make sense. In this case, devm_of_phy_get_by_index can be used to get a phy reference based on diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index d93ddf1262c5..672f5c865886 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -766,27 +766,6 @@ struct phy *phy_get(struct device *dev, const char *string) } EXPORT_SYMBOL_GPL(phy_get); -/** - * phy_optional_get() - lookup and obtain a reference to an optional phy. - * @dev: device that requests this phy - * @string: the phy name as given in the dt data or the name of the controller - * port for non-dt case - * - * Returns the phy driver, after getting a refcount to it; or - * NULL if there is no such phy. The caller is responsible for - * calling phy_put() to release that count. - */ -struct phy *phy_optional_get(struct device *dev, const char *string) -{ - struct phy *phy = phy_get(dev, string); - - if (PTR_ERR(phy) == -ENODEV) - phy = NULL; - - return phy; -} -EXPORT_SYMBOL_GPL(phy_optional_get); - /** * devm_phy_get() - lookup and obtain a reference to a phy. * @dev: device that requests this phy diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index b1413757fcc3..1b4f9be21e01 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -250,7 +250,6 @@ static inline void phy_set_bus_width(struct phy *phy, int bus_width) phy->attrs.bus_width = bus_width; } struct phy *phy_get(struct device *dev, const char *string); -struct phy *phy_optional_get(struct device *dev, const char *string); struct phy *devm_phy_get(struct device *dev, const char *string); struct phy *devm_phy_optional_get(struct device *dev, const char *string); struct phy *devm_of_phy_get(struct device *dev, struct device_node *np, @@ -426,12 +425,6 @@ static inline struct phy *phy_get(struct device *dev, const char *string) return ERR_PTR(-ENOSYS); } -static inline struct phy *phy_optional_get(struct device *dev, - const char *string) -{ - return ERR_PTR(-ENOSYS); -} - static inline struct phy *devm_phy_get(struct device *dev, const char *string) { return ERR_PTR(-ENOSYS); -- cgit v1.2.3 From 59c3d3d00d60b6d75ef3faf3b24e6aac037c1085 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 24 Jan 2023 19:37:21 +0100 Subject: doc: phy: Document devm_of_phy_get() Add the missing documentation for devm_of_phy_get(), which was forgotten when the function was introduced. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/768d5845668f081620098a0b4479d1481e212bac.1674584626.git.geert+renesas@glider.be Signed-off-by: Vinod Koul --- Documentation/driver-api/phy/phy.rst | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/driver-api/phy/phy.rst b/Documentation/driver-api/phy/phy.rst index 26467dd4f291..6cadc58f4ce0 100644 --- a/Documentation/driver-api/phy/phy.rst +++ b/Documentation/driver-api/phy/phy.rst @@ -106,6 +106,8 @@ it. This framework provides the following APIs to get a reference to the PHY. struct phy *devm_phy_get(struct device *dev, const char *string); struct phy *devm_phy_optional_get(struct device *dev, const char *string); + struct phy *devm_of_phy_get(struct device *dev, struct device_node *np, + const char *con_id); struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np, int index); @@ -119,10 +121,10 @@ successful PHY get. On driver detach, release function is invoked on the devres data and devres data is freed. devm_phy_optional_get should be used when the phy is optional. This function will never return -ENODEV, but instead returns NULL when -the phy cannot be found.Some generic drivers, such as ehci, may use multiple -phys and for such drivers referencing phy(s) by name(s) does not make sense. In -this case, devm_of_phy_get_by_index can be used to get a phy reference based on -the index. +the phy cannot be found. +Some generic drivers, such as ehci, may use multiple phys. In this case, +devm_of_phy_get or devm_of_phy_get_by_index can be used to get a phy +reference based on name or index. It should be noted that NULL is a valid phy reference. All phy consumer calls on the NULL phy become NOPs. That is the release calls, -- cgit v1.2.3 From d02aa181ee595c81738b6bd7ebad6025fbee035a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 24 Jan 2023 19:37:22 +0100 Subject: phy: Add devm_of_phy_optional_get() helper Add an optional variant of devm_of_phy_get() that also takes care of printing real errors, so drivers no longer have to open-code this operation. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/4cd0069bcff424ffc5c3a102397c02370b91985b.1674584626.git.geert+renesas@glider.be Signed-off-by: Vinod Koul --- Documentation/driver-api/phy/phy.rst | 7 +++++-- drivers/phy/phy-core.c | 30 ++++++++++++++++++++++++++++++ include/linux/phy/phy.h | 9 +++++++++ 3 files changed, 44 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/driver-api/phy/phy.rst b/Documentation/driver-api/phy/phy.rst index 6cadc58f4ce0..81785c084f3e 100644 --- a/Documentation/driver-api/phy/phy.rst +++ b/Documentation/driver-api/phy/phy.rst @@ -108,6 +108,9 @@ it. This framework provides the following APIs to get a reference to the PHY. const char *string); struct phy *devm_of_phy_get(struct device *dev, struct device_node *np, const char *con_id); + struct phy *devm_of_phy_optional_get(struct device *dev, + struct device_node *np, + const char *con_id); struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np, int index); @@ -119,8 +122,8 @@ non-dt boot, it should contain the label of the PHY. The two devm_phy_get associates the device with the PHY using devres on successful PHY get. On driver detach, release function is invoked on the devres data and devres data is freed. -devm_phy_optional_get should be used when the phy is optional. This -function will never return -ENODEV, but instead returns NULL when +The _optional_get variants should be used when the phy is optional. These +functions will never return -ENODEV, but instead return NULL when the phy cannot be found. Some generic drivers, such as ehci, may use multiple phys. In this case, devm_of_phy_get or devm_of_phy_get_by_index can be used to get a phy diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index 672f5c865886..9951efc03eaa 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -858,6 +858,36 @@ struct phy *devm_of_phy_get(struct device *dev, struct device_node *np, } EXPORT_SYMBOL_GPL(devm_of_phy_get); +/** + * devm_of_phy_optional_get() - lookup and obtain a reference to an optional + * phy. + * @dev: device that requests this phy + * @np: node containing the phy + * @con_id: name of the phy from device's point of view + * + * Gets the phy using of_phy_get(), and associates a device with it using + * devres. On driver detach, release function is invoked on the devres data, + * then, devres data is freed. This differs to devm_of_phy_get() in + * that if the phy does not exist, it is not considered an error and + * -ENODEV will not be returned. Instead the NULL phy is returned, + * which can be passed to all other phy consumer calls. + */ +struct phy *devm_of_phy_optional_get(struct device *dev, struct device_node *np, + const char *con_id) +{ + struct phy *phy = devm_of_phy_get(dev, np, con_id); + + if (PTR_ERR(phy) == -ENODEV) + phy = NULL; + + if (IS_ERR(phy)) + dev_err_probe(dev, PTR_ERR(phy), "failed to get PHY %pOF:%s", + np, con_id); + + return phy; +} +EXPORT_SYMBOL_GPL(devm_of_phy_optional_get); + /** * devm_of_phy_get_by_index() - lookup and obtain a reference to a phy by index. * @dev: device that requests this phy diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 1b4f9be21e01..3a570bc59fc7 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -254,6 +254,8 @@ struct phy *devm_phy_get(struct device *dev, const char *string); struct phy *devm_phy_optional_get(struct device *dev, const char *string); struct phy *devm_of_phy_get(struct device *dev, struct device_node *np, const char *con_id); +struct phy *devm_of_phy_optional_get(struct device *dev, struct device_node *np, + const char *con_id); struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np, int index); void of_phy_put(struct phy *phy); @@ -443,6 +445,13 @@ static inline struct phy *devm_of_phy_get(struct device *dev, return ERR_PTR(-ENOSYS); } +static inline struct phy *devm_of_phy_optional_get(struct device *dev, + struct device_node *np, + const char *con_id) +{ + return NULL; +} + static inline struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np, int index) -- cgit v1.2.3 From 052bfe6ec72c8fd3d14968da36816f97772b5a54 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 11 Jan 2023 11:04:46 +0000 Subject: dt-bindings: phy: tegra-xusb: Add support for Tegra234 Add the compatible string for the Tegra234 XUSB PHY. Signed-off-by: Jon Hunter Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230111110450.24617-3-jonathanh@nvidia.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml index 9d4eb7e6fbb7..6e3398399628 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml @@ -42,7 +42,9 @@ description: | properties: compatible: - const: nvidia,tegra194-xusb-padctl + enum: + - nvidia,tegra194-xusb-padctl + - nvidia,tegra234-xusb-padctl reg: items: -- cgit v1.2.3 From d5011cd5608f9252fe4f6da9a60cce4f42b07080 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 6 Feb 2023 10:58:56 +0100 Subject: dt-bindings: phy: qcom,qmp-usb3-dp: document sm8350 & sm8450 compatible Document the USB3/DP Combo PHY compatible found on the SM8350 & SM8450 SoCs. Signed-off-by: Neil Armstrong Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230206-topic-sm8350-upstream-usb-dp-combo-phy-v1-1-ed849ae6b849@linaro.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml index 0764cd977e76..52ab7174df85 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml @@ -18,6 +18,8 @@ properties: enum: - qcom,sc8280xp-qmp-usb43dp-phy - qcom,sm6350-qmp-usb3-dp-phy + - qcom,sm8350-qmp-usb3-dp-phy + - qcom,sm8450-qmp-usb3-dp-phy reg: maxItems: 1 -- cgit v1.2.3 From 496d068e2b881bde0c8b7882a95cbe7d4daa0892 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 8 Feb 2023 20:00:10 +0200 Subject: dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 Document the QMP PCIe PHY compatible for SM8550. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20230208180020.2761766-2-abel.vesa@linaro.org Signed-off-by: Vinod Koul --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 30 +++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 8a85318d9c92..ef49efbd0a20 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -20,6 +20,8 @@ properties: - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8550-qmp-gen3x2-pcie-phy + - qcom,sm8550-qmp-gen4x2-pcie-phy reg: minItems: 1 @@ -43,16 +45,21 @@ properties: maxItems: 1 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 reset-names: + minItems: 1 items: - const: phy + - const: phy_nocsr vdda-phy-supply: true vdda-pll-supply: true + vdda-qref-supply: true + qcom,4ln-config-sel: description: PCIe 4-lane configuration $ref: /schemas/types.yaml#/definitions/phandle-array @@ -113,6 +120,8 @@ allOf: contains: enum: - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8550-qmp-gen3x2-pcie-phy + - qcom,sm8550-qmp-gen4x2-pcie-phy then: properties: clocks: @@ -126,6 +135,25 @@ allOf: clock-names: minItems: 6 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8550-qmp-gen4x2-pcie-phy + then: + properties: + resets: + minItems: 2 + reset-names: + minItems: 2 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 + examples: - | #include -- cgit v1.2.3 From 5ccacdbed44e6816036ced7f84b604629203923f Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 8 Feb 2023 20:34:16 +0200 Subject: dt-bindings: phy: Add qcom,snps-eusb2-phy schema file The SM8550 SoC uses Synopsis eUSB2 PHY. Add a dt-binding schema for the new driver. Signed-off-by: Abel Vesa Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20230208183421.2874423-2-abel.vesa@linaro.org Signed-off-by: Vinod Koul --- .../bindings/phy/qcom,snps-eusb2-phy.yaml | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml new file mode 100644 index 000000000000..de72577e34a4 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SNPS eUSB2 phy controller + +maintainers: + - Abel Vesa + +description: + eUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. + +properties: + compatible: + const: qcom,sm8550-snps-eusb2-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: ref + + clock-names: + items: + - const: ref + + resets: + maxItems: 1 + + vdd-supply: + description: + Phandle to 0.88V regulator supply to PHY digital circuit. + + vdda12-supply: + description: + Phandle to 1.2V regulator supply to PHY refclk pll block. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - vdd-supply + - vdda12-supply + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8550-snps-eusb2-phy"; + reg = <0x88e3000 0x154>; + #phy-cells = <0>; + + clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; -- cgit v1.2.3 From 1c5a654f0d4b698df317013936c26eb8fcf4faef Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 8 Feb 2023 20:34:18 +0200 Subject: dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Document SM8550 compatible Add the SM8550 compatible to the list. Signed-off-by: Abel Vesa Acked-by: Rob Herring Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20230208183421.2874423-4-abel.vesa@linaro.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml index 52ab7174df85..3cd5fc3e8fab 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml @@ -20,6 +20,7 @@ properties: - qcom,sm6350-qmp-usb3-dp-phy - qcom,sm8350-qmp-usb3-dp-phy - qcom,sm8450-qmp-usb3-dp-phy + - qcom,sm8550-qmp-usb3-dp-phy reg: maxItems: 1 -- cgit v1.2.3 From a9b444988026528788c83c995ebb44eda5a54d8c Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 7 Feb 2023 16:03:53 +0100 Subject: dt-bindings: phy: amlogic,g12a-usb3-pcie-phy: add missing optional phy-supply property Add missing optional phy-supply property used to power up PHY regulators. Fixes: 87a55485f2fc ("dt-bindings: phy: meson-g12a-usb3-pcie-phy: convert to yaml") Signed-off-by: Neil Armstrong Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230207-b4-amlogic-amlogic-g12a-usb3-pcie-phy-fix-v1-1-3e437b759549@linaro.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml index 129d26e99776..3314711292d6 100644 --- a/Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml @@ -35,6 +35,11 @@ properties: "#phy-cells": const: 1 + phy-supply: + description: + Phandle to a regulator that provides power to the PHY. This + regulator will be managed during the PHY power on/off sequence. + required: - compatible - reg -- cgit v1.2.3 From f990aae9d6e4388b9b12b447bf7bad0cdf36c853 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 8 Feb 2023 21:01:54 +0200 Subject: dt-bindings: phy: Add qcom,snps-eusb2-repeater schema file The SM8550 SoC uses Synopsis eUSB2 repeater found in PM8550b. Add a dt-binding schema for the new driver. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230208190200.2966723-2-abel.vesa@linaro.org Signed-off-by: Vinod Koul --- .../bindings/phy/qcom,snps-eusb2-repeater.yaml | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml new file mode 100644 index 000000000000..083fda530b48 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-repeater.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Synopsis eUSB2 to USB 2.0 repeater + +maintainers: + - Abel Vesa + +description: + eUSB2 repeater converts between eUSB2 and USB 2.0 signaling levels and + allows a eUSB2 PHY to connect to legacy USB 2.0 products + +properties: + compatible: + const: qcom,pm8550b-eusb2-repeater + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + vdd18-supply: true + + vdd3-supply: true + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + + pmic@7 { + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550b_eusb2_repeater: phy@fd00 { + compatible = "qcom,pm8550b-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +... -- cgit v1.2.3 From 1288b5fef159e7ac57fcc0d82d69a107d3f722f7 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 8 Feb 2023 21:01:56 +0200 Subject: dt-bindings: phy: qcom,snps-eusb2-phy: Add phys property for the repeater The phys property is used for allowing the eusb2 to interface with the repeater, which is modelled as a phy driver. Signed-off-by: Abel Vesa Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230208190200.2966723-4-abel.vesa@linaro.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml index de72577e34a4..c53bab107b6d 100644 --- a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml @@ -33,6 +33,11 @@ properties: resets: maxItems: 1 + phys: + maxItems: 1 + description: + Phandle to eUSB2 to USB 2.0 repeater + vdd-supply: description: Phandle to 0.88V regulator supply to PHY digital circuit. -- cgit v1.2.3