From f7e06786512e730f750138b1221b6342bcf07859 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Mon, 12 Jan 2026 10:22:33 +0000 Subject: drm/amdgpu/mes: Remove idr leftovers v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit cb17fff3a254 ("drm/amdgpu/mes: remove unused functions") removed most of the code using these IDRs but forgot to remove the struct members and init/destroy paths. There is also interrupt handling code in SDMA 5.0 and 5.2 which appears to be using it, but is is unreachable since nothing ever allocates the relevant IDR. We replace those with one time warnings just to avoid any functional difference, but it is also possible they should be removed. v2: also fix up gfx_v12_1.c and sdma_v7_1.c Signed-off-by: Tvrtko Ursulin References: cb17fff3a254 ("drm/amdgpu/mes: remove unused functions") Cc: Alex Deucher Reviewed-by: Christian König Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 9 --------- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 3 --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 25 ++++++++++++------------- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 18 +++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 18 +++--------------- drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 17 +++-------------- 6 files changed, 21 insertions(+), 69 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 6e19836c5ff6..0d4c77c1b4b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -115,9 +115,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev) adev->mes.adev = adev; - idr_init(&adev->mes.pasid_idr); - idr_init(&adev->mes.gang_id_idr); - idr_init(&adev->mes.queue_id_idr); ida_init(&adev->mes.doorbell_ida); spin_lock_init(&adev->mes.queue_id_lock); mutex_init(&adev->mes.mutex_hidden); @@ -252,9 +249,6 @@ error: &adev->mes.hung_queue_db_array_cpu_addr[i]); } - idr_destroy(&adev->mes.pasid_idr); - idr_destroy(&adev->mes.gang_id_idr); - idr_destroy(&adev->mes.queue_id_idr); ida_destroy(&adev->mes.doorbell_ida); mutex_destroy(&adev->mes.mutex_hidden); return r; @@ -283,9 +277,6 @@ void amdgpu_mes_fini(struct amdgpu_device *adev) amdgpu_mes_doorbell_free(adev); - idr_destroy(&adev->mes.pasid_idr); - idr_destroy(&adev->mes.gang_id_idr); - idr_destroy(&adev->mes.queue_id_idr); ida_destroy(&adev->mes.doorbell_ida); mutex_destroy(&adev->mes.mutex_hidden); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 88685c58798e..bcf2a067dc41 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -77,9 +77,6 @@ struct amdgpu_mes { struct mutex mutex_hidden; - struct idr pasid_idr; - struct idr gang_id_idr; - struct idr queue_id_idr; struct ida doorbell_ida; spinlock_t queue_id_lock; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 86cc90a66296..08ae50a6313f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -30,6 +30,7 @@ #include "amdgpu_psp.h" #include "amdgpu_smu.h" #include "amdgpu_atomfirmware.h" +#include "amdgpu_userq_fence.h" #include "imu_v12_1.h" #include "soc_v1_0.h" #include "gfx_v12_1_pkt.h" @@ -3602,25 +3603,23 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - int i, xcc_id; + u32 doorbell_offset = entry->src_data[0]; u8 me_id, pipe_id, queue_id; struct amdgpu_ring *ring; - uint32_t mes_queue_id = entry->src_data[0]; + int i, xcc_id; DRM_DEBUG("IH: CP EOP\n"); - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { - struct amdgpu_mes_queue *queue; + if (adev->enable_mes && doorbell_offset) { + struct amdgpu_userq_fence_driver *fence_drv = NULL; + struct xarray *xa = &adev->userq_xa; + unsigned long flags; - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; - - spin_lock(&adev->mes.queue_id_lock); - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); - if (queue) { - DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); - amdgpu_fence_process(queue->ring); - } - spin_unlock(&adev->mes.queue_id_lock); + xa_lock_irqsave(xa, flags); + fence_drv = xa_load(xa, doorbell_offset); + if (fence_drv) + amdgpu_userq_fence_driver_process(fence_drv); + xa_unlock_irqrestore(xa, flags); } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 7811cbb1f7ba..e77e079fe833 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1704,24 +1704,12 @@ static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - uint32_t mes_queue_id = entry->src_data[0]; - DRM_DEBUG("IH: SDMA trap\n"); - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { - struct amdgpu_mes_queue *queue; - - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; - - spin_lock(&adev->mes.queue_id_lock); - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); - if (queue) { - DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); - amdgpu_fence_process(queue->ring); - } - spin_unlock(&adev->mes.queue_id_lock); + if (drm_WARN_ON_ONCE(&adev->ddev, + adev->enable_mes && + (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG))) return 0; - } switch (entry->client_id) { case SOC15_IH_CLIENTID_SDMA0: diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index dbe5b8f109f6..50b51965c211 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1617,24 +1617,12 @@ static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - uint32_t mes_queue_id = entry->src_data[0]; - DRM_DEBUG("IH: SDMA trap\n"); - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { - struct amdgpu_mes_queue *queue; - - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; - - spin_lock(&adev->mes.queue_id_lock); - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); - if (queue) { - DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); - amdgpu_fence_process(queue->ring); - } - spin_unlock(&adev->mes.queue_id_lock); + if (drm_WARN_ON_ONCE(&adev->ddev, + adev->enable_mes && + (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG))) return 0; - } switch (entry->client_id) { case SOC15_IH_CLIENTID_SDMA0: diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c index 5bc45c3e00d1..0824cba48f2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c @@ -1494,24 +1494,13 @@ static int sdma_v7_1_process_trap_irq(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) { int inst, instances, queue, xcc_id = 0; - uint32_t mes_queue_id = entry->src_data[0]; DRM_DEBUG("IH: SDMA trap\n"); - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { - struct amdgpu_mes_queue *queue; - - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; - - spin_lock(&adev->mes.queue_id_lock); - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); - if (queue) { - DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); - amdgpu_fence_process(queue->ring); - } - spin_unlock(&adev->mes.queue_id_lock); + if (drm_WARN_ON_ONCE(&adev->ddev, + adev->enable_mes && + (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG))) return 0; - } queue = entry->ring_id & 0xf; if (adev->gfx.funcs && adev->gfx.funcs->ih_node_to_logical_xcc) -- cgit v1.2.3 From dda702172dc26e080fe048b8f170eaccb8097c1a Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Mon, 12 Jan 2026 10:22:34 +0000 Subject: drm/amdgpu: Simplify sorting of the bo list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sort function only cares about the sign so we can replace the conditionals with a single subtraction. Signed-off-by: Tvrtko Ursulin Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index 66fb37b64388..87ec46c56a6e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -60,11 +60,9 @@ static int amdgpu_bo_list_entry_cmp(const void *_a, const void *_b) { const struct amdgpu_bo_list_entry *a = _a, *b = _b; - if (a->priority > b->priority) - return 1; - if (a->priority < b->priority) - return -1; - return 0; + BUILD_BUG_ON(AMDGPU_BO_LIST_MAX_PRIORITY >= INT_MAX); + + return (int)a->priority - (int)b->priority; } int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp, -- cgit v1.2.3 From 1bf8b4642c5f511dd73653a25ed7cd0470118389 Mon Sep 17 00:00:00 2001 From: Shaoyun Liu Date: Thu, 22 Jan 2026 10:51:11 -0500 Subject: drm/amd/include : Update MES v12 API header - SUSPEND Update SUSPEND API to support sdma queues. It's been supportted since 0x82 for gfx12 Signed-off-by: Shaoyun Liu Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/mes_v12_api_def.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h b/drivers/gpu/drm/amd/include/mes_v12_api_def.h index 83e4f0142324..e541a43714a1 100644 --- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h @@ -492,8 +492,10 @@ union MESAPI__SUSPEND { union MES_API_HEADER header; /* false - suspend all gangs; true - specific gang */ struct { - uint32_t suspend_all_gangs : 1; - uint32_t reserved : 31; + uint32_t suspend_all_gangs : 1; // suspend all compute gangs (can be set together with suspend_all_sdma_gangs) + uint32_t query_status : 1; + uint32_t suspend_all_sdma_gangs : 1; // suspend all sdma gangs (can be set together with suspend_all_gangs) + uint32_t reserved : 29; }; /* gang_context_addr is valid only if suspend_all = false */ -- cgit v1.2.3 From 6194f60c707e3878e120adeb36997075664d8429 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Wed, 21 Jan 2026 11:04:06 +0800 Subject: drm/amd/pm: fix smu v13 soft clock frequency setting issue v1: resolve the issue where some freq frequencies cannot be set correctly due to insufficient floating-point precision. v2: patch this convert on 'max' value only. Signed-off-by: Yang Wang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 1 + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h index efeaa3d57712..b0d6b7b0946d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -55,6 +55,7 @@ #define SMUQ10_TO_UINT(x) ((x) >> 10) #define SMUQ10_FRAC(x) ((x) & 0x3ff) #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200)) +#define SMU_V13_SOFT_FREQ_ROUND(x) ((x) + 1) extern const int pmfw_decoded_link_speed[5]; extern const int pmfw_decoded_link_width[7]; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 51f96fdcec24..70581326dc36 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -1554,6 +1554,7 @@ int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, return clk_id; if (max > 0) { + max = SMU_V13_SOFT_FREQ_ROUND(max); if (automatic) param = (uint32_t)((clk_id << 16) | 0xffff); else -- cgit v1.2.3 From 53868dd8774344051999c880115740da92f97feb Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Wed, 21 Jan 2026 11:06:29 +0800 Subject: drm/amd/pm: fix smu v14 soft clock frequency setting issue v1: resolve the issue where some freq frequencies cannot be set correctly due to insufficient floating-point precision. v2: patch this convert on 'max' value only. Signed-off-by: Yang Wang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h | 1 + drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h index 613d4d36f32f..b453e6efc7c9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h @@ -56,6 +56,7 @@ extern const int decoded_link_width[8]; #define DECODE_GEN_SPEED(gen_speed_idx) (decoded_link_speed[gen_speed_idx]) #define DECODE_LANE_WIDTH(lane_width_idx) (decoded_link_width[lane_width_idx]) +#define SMU_V14_SOFT_FREQ_ROUND(x) ((x) + 1) struct smu_14_0_max_sustainable_clocks { uint32_t display_clock; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c index f85ba23f9d99..17caf98bd6dd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c @@ -1177,6 +1177,7 @@ int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, return clk_id; if (max > 0) { + max = SMU_V14_SOFT_FREQ_ROUND(max); if (automatic) param = (uint32_t)((clk_id << 16) | 0xffff); else -- cgit v1.2.3 From 6ce8d536c80aa1f059e82184f0d1994436b1d526 Mon Sep 17 00:00:00 2001 From: Jon Doron Date: Sat, 20 Dec 2025 15:04:40 +0200 Subject: drm/amdgpu: fix NULL pointer dereference in amdgpu_gmc_filter_faults_remove MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On APUs such as Raven and Renoir (GC 9.1.0, 9.2.2, 9.3.0), the ih1 and ih2 interrupt ring buffers are not initialized. This is by design, as these secondary IH rings are only available on discrete GPUs. See vega10_ih_sw_init() which explicitly skips ih1/ih2 initialization when AMD_IS_APU is set. However, amdgpu_gmc_filter_faults_remove() unconditionally uses ih1 to get the timestamp of the last interrupt entry. When retry faults are enabled on APUs (noretry=0), this function is called from the SVM page fault recovery path, resulting in a NULL pointer dereference when amdgpu_ih_decode_iv_ts_helper() attempts to access ih->ring[]. The crash manifests as: BUG: kernel NULL pointer dereference, address: 0000000000000004 RIP: 0010:amdgpu_ih_decode_iv_ts_helper+0x22/0x40 [amdgpu] Call Trace: amdgpu_gmc_filter_faults_remove+0x60/0x130 [amdgpu] svm_range_restore_pages+0xae5/0x11c0 [amdgpu] amdgpu_vm_handle_fault+0xc8/0x340 [amdgpu] gmc_v9_0_process_interrupt+0x191/0x220 [amdgpu] amdgpu_irq_dispatch+0xed/0x2c0 [amdgpu] amdgpu_ih_process+0x84/0x100 [amdgpu] This issue was exposed by commit 1446226d32a4 ("drm/amdgpu: Remove GC HW IP 9.3.0 from noretry=1") which changed the default for Renoir APU from noretry=1 to noretry=0, enabling retry fault handling and thus exercising the buggy code path. Fix this by adding a check for ih1.ring_size before attempting to use it. Also restore the soft_ih support from commit dd299441654f ("drm/amdgpu: Rework retry fault removal"). This is needed if the hardware doesn't support secondary HW IH rings. v2: additional updates (Alex) Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3814 Fixes: dd299441654f ("drm/amdgpu: Rework retry fault removal") Reviewed-by: Timur Kristóf Reviewed-by: Philip Yang Signed-off-by: Jon Doron Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index d9ff68a43178..b793ce17140c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -498,8 +498,13 @@ void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, if (adev->irq.retry_cam_enabled) return; + else if (adev->irq.ih1.ring_size) + ih = &adev->irq.ih1; + else if (adev->irq.ih_soft.enabled) + ih = &adev->irq.ih_soft; + else + return; - ih = &adev->irq.ih1; /* Get the WPTR of the last entry in IH ring */ last_wptr = amdgpu_ih_get_wptr(adev, ih); /* Order wptr with ring data. */ -- cgit v1.2.3 From 4a421335842bb622cb8685e66e0e177d4bae5363 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Thu, 8 Jan 2026 21:45:41 -0500 Subject: drm/amd/display: Enable vstateup hook for DCN401 to be reused Add the hook to the DCN401 header file so that it can be reused in other files Reviewed-by: Leo Chen Signed-off-by: Charlene Liu Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 875ae97489d3..1cdbb65da4a3 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1772,7 +1772,7 @@ static int dcn401_get_power_profile(const struct dc_state *context) return dpm_level; } -static unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx) +unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx) { return pipe_ctx->global_sync.dcn4x.vstartup_lines; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index 406246a9867e..08bec1755617 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -28,6 +28,8 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); +unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx); + /* Following are definitions for run time init of reg offsets */ /* HUBP */ -- cgit v1.2.3 From bdad08670278829771626ea7b57c4db531e2544f Mon Sep 17 00:00:00 2001 From: Matthew Stewart Date: Fri, 9 Jan 2026 13:32:42 -0500 Subject: drm/amd/display: Fix GFX12 family constant checks Using >=, <= for checking the family is not always correct. Reviewed-by: Aurabindo Pillai Signed-off-by: Matthew Stewart Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b4ba60e90c47..0b4fc654e76f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11867,7 +11867,7 @@ static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, * check tiling flags when the FB doesn't have a modifier. */ if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { - if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) { + if (adev->family == AMDGPU_FAMILY_GC_12_0_0) { linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; } else if (adev->family >= AMDGPU_FAMILY_AI) { linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 8c5912b59e19..b048092c5f19 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -278,7 +278,7 @@ static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev, if (!dcc->enable) return 0; - if (adev->family < AMDGPU_FAMILY_GC_12_0_0 && + if (adev->family != AMDGPU_FAMILY_GC_12_0_0 && format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return -EINVAL; @@ -901,7 +901,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, upper_32_bits(chroma_addr); } - if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) { + if (adev->family == AMDGPU_FAMILY_GC_12_0_0) { ret = amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(adev, afb, format, rotation, plane_size, tiling_info, dcc, -- cgit v1.2.3 From 7cdb3d0367860d8e5a058b8658cf7ae85a4796d3 Mon Sep 17 00:00:00 2001 From: Jack Chang Date: Fri, 1 Aug 2025 11:54:01 +0800 Subject: drm/amd/display: Add FR skipping CTS functions 1. To check whether Sink reaches maximum skipping number Reviewed-by: Robin Chen Signed-off-by: Jack Chang Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/include/dpcd_defs.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h index 7d8359a7d99d..1afa10e85eb5 100644 --- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h +++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h @@ -224,6 +224,7 @@ enum dpcd_psr_sink_states { #define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE 0x379 #define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A #define DP_SINK_EMISSION_RATE 0x37E +#define DP_SINK_PR_FRAME_SKIP_COUNT 0x337 /* Remove once drm_dp_helper.h is updated upstream */ #ifndef DP_TOTAL_LTTPR_CNT -- cgit v1.2.3 From 6cf32edb5d6307bb55764d9c6df0af4e73c415f2 Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Mon, 22 Dec 2025 16:30:35 +0800 Subject: drm/amd/display: Enable bootcrc on FW side [Why] The bootcrc feature is controlled on the FW side. [How] Pass the control bits in boot options to FW. Reviewed-by: ChiaHsuan (Tom) Chung Signed-off-by: Wayne Lin Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c index 6a2d35756c8c..639f9835e5e9 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c @@ -419,6 +419,9 @@ void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig; boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation; + boot_options.bits.bootcrc_en_at_preos = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_en_at_preos; + boot_options.bits.bootcrc_en_at_S0i3 = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_en_at_S0i3; + boot_options.bits.bootcrc_boot_mode = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_boot_mode; REG_WRITE(DMCUB_SCRATCH14, boot_options.all); } -- cgit v1.2.3 From 06fee4fba93112c198232c351ef4348614a94590 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Sun, 11 Jan 2026 12:20:51 -0500 Subject: drm/amd/display: perform clear update flags for all DCN asics Existing version check that limits the sequence to clear update flags should be performed for all asics. Exclude DCE asics for now. Reviewed-by: Sun peng (Leo) Li Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index ad8ce46ce310..cb85b7ac2697 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -7506,7 +7506,7 @@ struct dc_update_scratch_space *dc_update_planes_and_stream_init( .stream = stream, .stream_update = stream_update, .update_v3 = version >= DCN_VERSION_4_01 || version == DCN_VERSION_3_2 || version == DCN_VERSION_3_21, - .do_clear_update_flags = version >= DCN_VERSION_3_2 || version == DCN_VERSION_3_01, + .do_clear_update_flags = version >= DCN_VERSION_1_0, }; return scratch; -- cgit v1.2.3 From 26b5cf26885078c0173301a0c12304e17463ba10 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 12 Jan 2026 17:53:51 -0500 Subject: drm/amd/display: add setup_stereo for dcn4x or later [why] stereo_sync pin is removed, but we still support display stereo Reviewed-by: Ovidiu (Ovi) Bunea Signed-off-by: Charlene Liu Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 8a23763ca98e..73f469ce7cdd 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -3474,7 +3474,7 @@ void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx, triggers, params->num_frames); } -static void dcn10_config_stereo_parameters( +void dcn10_config_stereo_parameters( struct dc_stream_state *stream, struct crtc_stereo_flags *flags) { enum view_3d_format view_format = stream->view_format; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h index 57d30ea225f2..476095c5dd0c 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h @@ -217,5 +217,7 @@ void dcn10_update_visual_confirm_color( void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling); +void dcn10_config_stereo_parameters( + struct dc_stream_state *stream, struct crtc_stereo_flags *flags); #endif /* __DC_HWSS_DCN10_H__ */ -- cgit v1.2.3 From c37084e25f058b9e4c531ac6fc6f232533c566e8 Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Tue, 6 Jan 2026 15:46:49 +0800 Subject: drm/amd/display: Remove unnecessary DC FP guard [Why & How] For dcn2x_fast_validate_bw(), not only populate_dml_pipes needs FP guard but also dml_get_voltage_level(). Remove unnecessary DC_FP_START/DC_FP_END guard in dcn20_fast_validate_bw and dcn21_fast_validate_bw. FP guard is already there before calling dcn2x_validate_bandwidth_fp(). Reviewed-by: ChiaHsuan (Tom) Chung Signed-off-by: Wayne Lin Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 2 -- drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c | 2 -- 2 files changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index 8d10aac9c510..46985eb2a623 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -2022,9 +2022,7 @@ bool dcn20_fast_validate_bw( dcn20_merge_pipes_for_validate(dc, context); - DC_FP_START(); pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); - DC_FP_END(); *pipe_cnt_out = pipe_cnt; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 2060acd5ae09..967e813a45e5 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -785,9 +785,7 @@ bool dcn21_fast_validate_bw(struct dc *dc, dcn20_merge_pipes_for_validate(dc, context); - DC_FP_START(); pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); - DC_FP_END(); *pipe_cnt_out = pipe_cnt; -- cgit v1.2.3 From 15b1d7b77e9836ff4184093163174a1ef28bbdd7 Mon Sep 17 00:00:00 2001 From: Zhongwei Date: Tue, 13 Jan 2026 15:51:42 +0800 Subject: drm/amd/display: avoid dig reg access timeout on usb4 link training fail [Why] When usb4 link training fails, the dpia sym clock will be disabled and SYMCLK source should be changed back to phy clock. In enable_streams, it is assumed that link training succeeded and will switch from refclk to phy clock. But phy clk here might not be on. Dig reg access timeout will occur. [How] When enable_stream is hit, check if link training failed for usb4. If it did, fall back to the ref clock to avoid reg access timeout. Reviewed-by: Wenjing Liu Signed-off-by: Zhongwei Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 77ac7b22b8dc..16ea6179640e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -3058,9 +3058,17 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); } } else { - if (dccg->funcs->enable_symclk_se) - dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, + if (dccg->funcs->enable_symclk_se && link_enc) { + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA + && link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN + && !link->link_status.link_active) { + if (dccg->funcs->disable_symclk_se) + dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A); + } else + dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, + link_enc->transmitter - TRANSMITTER_UNIPHY_A); + } } if (dc->res_pool->dccg->funcs->set_pixel_rate_div) -- cgit v1.2.3 From 5b8cfb0cebf93bd0f8b316084ce0589df8fd57ac Mon Sep 17 00:00:00 2001 From: Michael Strauss Date: Thu, 15 Jan 2026 11:07:53 -0500 Subject: drm/amd/display: Add debug flag to override min dispclk [WHY] Enable dynamic ODM testing without needing a valid dispclk table [HOW] Create a debug flag to specify an override value for min dispclk Reviewed-by: Dmytro Laktyushkin Signed-off-by: Michael Strauss Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d377be76360c..472d0eeca85e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1210,6 +1210,7 @@ struct dc_debug_options { bool disable_deferred_minimal_transitions; unsigned int num_fast_flips_to_steady_state_override; bool enable_dmu_recovery; + unsigned int force_vmin_threshold; }; -- cgit v1.2.3 From ba448f9ed62cf5a89603a738e6de91fc6c42ab35 Mon Sep 17 00:00:00 2001 From: Muaaz Nisar Date: Thu, 18 Dec 2025 17:34:29 -0500 Subject: drm/amd/display: mouse event trigger to boost RR when idle [WHY+HOW] Add trigger event to boost refresh rate on mouse movement. Reviewed-by: Jun Lei Signed-off-by: Muaaz Nisar Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 9349cccc8438..f59020f1a722 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -515,6 +515,19 @@ bool dc_stream_program_cursor_position( } } + /* apply manual trigger */ + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + /* trigger event on first pipe with current stream */ + if (stream == pipe_ctx->stream) { + pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); + break; + } + } + return true; } -- cgit v1.2.3 From 592c5b80110d5e9e50873b5364818cb6f401e26d Mon Sep 17 00:00:00 2001 From: Bhuvanachandra Pinninti Date: Thu, 8 Jan 2026 19:11:31 +0530 Subject: drm/amd/display: Migrate HUBBUB register access from hwseq to hubbub component. [why] Direct HUBBUB register access in the hwseq layer was creating register conflicts. [how] Migrated HUBBUB registers from hwseq to the hubbub component. Reviewed-by: Martin Leung Signed-off-by: Bhuvanachandra Pinninti Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c | 18 ++++++++++++++++++ .../gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h | 4 ++++ .../gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 3 +-- .../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 4 ++-- .../gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 1 + .../gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 1 + .../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 1 + .../gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 1 + 8 files changed, 29 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c index 7847c1c4927b..97ef8281a476 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c @@ -944,3 +944,21 @@ void hubbub1_construct(struct hubbub *hubbub, hubbub1->debug_test_index_pstate = 0xB; } +void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv) +{ + struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); + + if (refdiv > 0) + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, refdiv); + + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, enable ? 1 : 0); +} + +void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value) +{ + struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); + + REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, fb_base_value); + REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, fb_offset_value); +} + diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h index 0a29a758d013..990d3cd8e050 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h @@ -519,4 +519,8 @@ bool hubbub1_program_pstate_watermarks( unsigned int refclk_mhz, bool safe_to_lower); +void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv); + +void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 73f469ce7cdd..c1586364ecd4 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -2678,8 +2678,7 @@ static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1, uint32_t fb_base_value; uint32_t fb_offset_value; - REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value); - REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value); + dcn10_hubbub_read_fb_aperture(hws->ctx->dc->res_pool->hubbub, &fb_base_value, &fb_offset_value); REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 16ea6179640e..a76436dcbe40 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -46,6 +46,7 @@ #include "dchubbub.h" #include "reg_helper.h" #include "dcn10/dcn10_cm_common.h" +#include "dcn10/dcn10_hubbub.h" #include "vm_helper.h" #include "dccg.h" #include "dc_dmub_srv.h" @@ -3153,8 +3154,7 @@ void dcn20_fpga_init_hw(struct dc *dc) REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); - REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); - REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); + dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2); if (REG(REFCLK_CNTL)) REG_WRITE(REFCLK_CNTL, 0); // diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c index 1635e5a552ad..482053c4ad22 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c @@ -39,6 +39,7 @@ #include "dccg.h" #include "clk_mgr.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #define CTX \ hws->ctx diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index 81bcadf5e57e..c02ddada723f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -36,6 +36,7 @@ #include "dcn10/dcn10_cm_common.h" #include "dcn30/dcn30_cm_common.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #include "abm.h" #include "clk_mgr.h" #include "hubp.h" diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index 20f700b59847..2adbcc105aa6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -32,6 +32,7 @@ #include "dce/dce_hwseq.h" #include "clk_mgr.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #include "abm.h" #include "hubp.h" #include "dchubbub.h" diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 2675d7dca586..f7e16fee7594 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -32,6 +32,7 @@ #include "dce/dce_hwseq.h" #include "clk_mgr.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #include "abm.h" #include "hubp.h" #include "dchubbub.h" -- cgit v1.2.3 From 0f2828150f7ab31a57fe3bce6c2d378103dab10a Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 16 Jan 2026 17:25:23 -0500 Subject: drm/amd/display: [FW Promotion] Release 0.1.44.0 * Panel Replay related features/bugfixes * BootCRC feature Signed-off-by: Taimur Hassan Signed-off-by: Aurabindo Pillai Reviewed-by: Alex Hung Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 55 ++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 6d82973ccc18..18e0bdfd6ff4 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -139,6 +139,33 @@ */ #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 +/** + * + * dirty rect cmd version legacy + */ +#define DMUB_CMD_DIRTY_RECTS_VERSION_UNKNOWN 0x0 +/** + * dirty rect cmd version with multi edp support + */ +#define DMUB_CMD_DIRTY_RECTS_VERSION_1 0x1 +/** + * dirty rect cmd version with external monitor support + */ +#define DMUB_CMD_DIRTY_RECTS_VERSION_2 0x2 + +/** + * + * Cursor update cmd version legacy + */ +#define DMUB_CMD_CURSOR_UPDATE_VERSION_UNKNOWN 0x0 +/** + * Cursor update cmd version with multi edp support + */ +#define DMUB_CMD_CURSOR_UPDATE_VERSION_1 0x1 +/** + * Cursor update cmd version with external monitor support + */ +#define DMUB_CMD_CURSOR_UPDATE_VERSION_2 0x2 /** * ABM control version legacy @@ -3929,7 +3956,7 @@ struct dmub_cmd_update_dirty_rect_data { */ union dmub_psr_su_debug_flags debug_flags; /** - * OTG HW instance. + * Pipe index. */ uint8_t pipe_idx; /** @@ -3937,7 +3964,7 @@ struct dmub_cmd_update_dirty_rect_data { */ uint8_t dirty_rect_count; /** - * PSR control version. + * dirty rects cmd version. */ uint8_t cmd_version; /** @@ -3946,6 +3973,14 @@ struct dmub_cmd_update_dirty_rect_data { * Currently the support is only for 0 or 1 */ uint8_t panel_inst; + /** + * OTG HW instance + */ + uint8_t otg_inst; + /** + * Padding for 4 byte alignment + */ + uint8_t padding[3]; }; /** @@ -4071,11 +4106,11 @@ struct dmub_cmd_update_cursor_payload0 { */ uint8_t enable; /** - * OTG HW instance. + * Pipe index. */ uint8_t pipe_idx; /** - * PSR control version. + * Cursor update cmd version. */ uint8_t cmd_version; /** @@ -4089,6 +4124,14 @@ struct dmub_cmd_update_cursor_payload0 { * Registers contains Hubp & Dpp modules */ struct dmub_cursor_position_cfg position_cfg; + /** + * OTG HW instance + */ + uint8_t otg_inst; + /** + * Padding for 4 byte alignment + */ + uint8_t padding[3]; }; struct dmub_cmd_update_cursor_payload1 { @@ -6629,9 +6672,9 @@ struct dmub_cmd_pr_copy_settings_data { */ uint8_t su_y_granularity; /** - * @pad: Align structure to 4 byte boundary. + * @main_link_activity_option: Indicates main link activity option selected */ - uint8_t pad; + uint8_t main_link_activity_option; }; /** -- cgit v1.2.3 From 37e6349e9328feb600568144411c18e3c35e3077 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 16 Jan 2026 20:09:08 -0500 Subject: drm/amd/display: Promote DC to 3.2.367 * Fw release 0.1.44.0 * Fixes for corruption on platforms older than DCN4x. * Bug fixes related to USB4 link training * Fixes related to FP guard * Debug helpers and other stability fixes. * Some refactors to improve code quality Signed-off-by: Taimur Hassan Signed-off-by: Aurabindo Pillai Reviewed-by: Alex Hung Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 472d0eeca85e..ab19b6230945 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.366" +#define DC_VER "3.2.367" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC -- cgit v1.2.3 From 7a3fbdfd19ec5992c0fc2d0bd83888644f5f2f38 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Tue, 27 Jan 2026 11:07:07 +0800 Subject: drm/amd/pm: fix race in power state check before mutex lock The power state check in amdgpu_dpm_set_powergating_by_smu() is done before acquiring the pm mutex, leading to a race condition where: 1. Thread A checks state and thinks no change is needed 2. Thread B acquires mutex and modifies the state 3. Thread A returns without updating state, causing inconsistency Fix this by moving the mutex lock before the power state check, ensuring atomicity of the state check and modification. Fixes: 6ee27ee27ba8 ("drm/amd/pm: avoid duplicate powergate/ungate setting") Signed-off-by: Yang Wang Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index 4214f7314963..feadf604b474 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -80,15 +80,15 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; + mutex_lock(&adev->pm.mutex); + if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && (!is_vcn || adev->vcn.num_vcn_inst == 1)) { dev_dbg(adev->dev, "IP block%d already in the target %s state!", block_type, gate ? "gate" : "ungate"); - return 0; + goto out_unlock; } - mutex_lock(&adev->pm.mutex); - switch (block_type) { case AMD_IP_BLOCK_TYPE_UVD: case AMD_IP_BLOCK_TYPE_VCE: @@ -115,6 +115,7 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, if (!ret) atomic_set(&adev->pm.pwr_state[block_type], pwr_state); +out_unlock: mutex_unlock(&adev->pm.mutex); return ret; -- cgit v1.2.3 From 91544c45fa6a165abde6f2363bb7ded5843ef840 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Tue, 27 Jan 2026 15:01:27 +0800 Subject: drm/amdgpu: Fix jpeg ring test order in vcn_v4_0_3 Fix the vcn reset sequence in vcn_v4_0_3_ring_reset() to restore JPEG power state and unlock the JPEG powergating mutex before running the JPEG ring post-reset helper. Fixes: d25c67fd9d6f ("drm/amdgpu/vcn4.0.3: rework reset handling") Reviewed-by: Lijo Lazar Signed-off-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index dd247abce1ab..e78526a4e521 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1742,11 +1742,11 @@ static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, goto unlock; } - r = vcn_v4_0_3_reset_jpeg_post_helper(adev, ring->me); if (pg_state) amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, AMD_PG_STATE_GATE); mutex_unlock(&adev->jpeg.jpeg_pg_lock); + r = vcn_v4_0_3_reset_jpeg_post_helper(adev, ring->me); unlock: mutex_unlock(&vinst->engine_reset_mutex); -- cgit v1.2.3 From e0d11bdb294cd1325eeccfec05e07d8c2534b43e Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Thu, 22 Jan 2026 10:19:28 -0500 Subject: drm/amdgpu: Send RMA CPER at bad page loading Some older builds weren't sending RMA CPERs when the bad page threshold was exceeded. Newer builds have resolved this, but there could be systems out there with bad page numbers higher than the threshold, that haven't sent out an RMA CPER. To be thorough and safe, send an RMA CPER when we load the table, if the threshold is met or exceeded, instead of waiting for the next UE to trigger the CPER. Signed-off-by: Kent Russell Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 64dd7a81bff5..469d04a39d7d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1712,6 +1712,10 @@ int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", control->ras_num_bad_pages, ras->bad_page_cnt_threshold); + if (amdgpu_bad_page_threshold != 0 && + control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) + amdgpu_dpm_send_rma_reason(adev); + } else if (hdr->header == RAS_TABLE_HDR_BAD && amdgpu_bad_page_threshold != 0) { if (hdr->version >= RAS_TABLE_VER_V2_1) { -- cgit v1.2.3 From e698127eb7249d6c70fa8f2bdba469c0e54f2e2b Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Wed, 23 Jul 2025 10:07:28 -0400 Subject: drm/amdkfd: add extended capabilities to device snapshot Add additional capabilities reporting. Signed-off-by: Jonathan Kim Reviewed-by: James Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 1 + include/uapi/linux/kfd_ioctl.h | 2 ++ 2 files changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c index 27176b2dc714..8f8a0975f1a7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c @@ -1108,6 +1108,7 @@ int kfd_dbg_trap_device_snapshot(struct kfd_process *target, device_info.num_xcc = NUM_XCC(pdd->dev->xcc_mask); device_info.capability = topo_dev->node_props.capability; device_info.debug_prop = topo_dev->node_props.debug_prop; + device_info.capability2 = topo_dev->node_props.capability2; if (exception_clear_mask) pdd->exception_status &= ~exception_clear_mask; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 047bcb1cc078..e72359370857 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -149,6 +149,8 @@ struct kfd_dbg_device_info_entry { __u32 num_xcc; __u32 capability; __u32 debug_prop; + __u32 capability2; + __u32 pad; }; /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ -- cgit v1.2.3 From 1197366cca89a4c44c541ddedb8ce8bf0757993d Mon Sep 17 00:00:00 2001 From: Jinzhou Su Date: Wed, 21 Jan 2026 16:42:11 +0800 Subject: drm/amd/pm: Fix null pointer dereference issue If SMU is disabled, during RAS initialization, there will be null pointer dereference issue here. Signed-off-by: Jinzhou Su Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 6b6b05e8f736..3f70731105a2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -619,6 +619,9 @@ int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type ms struct smu_context *smu = adev->powerplay.pp_handle; int ret = -EOPNOTSUPP; + if (!smu) + return ret; + if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); -- cgit v1.2.3 From 05762d9c7da1f7e8ec6c456f592a17390ad43ddd Mon Sep 17 00:00:00 2001 From: Jay Cornwall Date: Wed, 21 Jan 2026 15:25:09 -0600 Subject: drm/amdkfd: gfx12.1 trap handler instruction fixup for VOP3PX A trap may occur in the middle of VOP3PX instruction co-issue. The PC would be restored incorrectly if left unmodified. Identify this case by examining the instruction opcode and rewind the PC 8 bytes if it occurs. Signed-off-by: Jay Cornwall Reviewed-by: Lancelot Six Reviewed-by: Vladimir Indic Cc: Shweta Khatri Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 197 +++++++++++---------- .../gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm | 25 ++- 2 files changed, 121 insertions(+), 101 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 39bdc98b8b6d..54fa76f374c9 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -4587,14 +4587,14 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { }; static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { - 0xbfa00001, 0xbfa003ac, + 0xbfa00001, 0xbfa003be, 0xb0804009, 0xb8f8f804, 0x9178ff78, 0x00008c00, 0xb8fbf811, 0x8b6eff78, 0x00004000, 0xbfa10008, 0x8b6eff7b, 0x00000080, 0xbfa20018, 0x8b6ea07b, - 0xbfa200d1, 0xbf830010, + 0xbfa200da, 0xbf830010, 0xb8fbf811, 0xbfa0fffb, 0x8b6eff7b, 0x00000bd0, 0xbfa20010, 0xb8eef812, @@ -4605,7 +4605,7 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { 0xf0000000, 0xbfa20005, 0x8b6fff6f, 0x00000200, 0xbfa20002, 0x8b6ea07b, - 0xbfa200bb, 0x9177ff77, + 0xbfa200c4, 0x9177ff77, 0x007fc000, 0xb8fa04a1, 0x847a967a, 0x8c777a77, 0xb8fa0421, 0x847a957a, @@ -4632,43 +4632,46 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { 0xbfa00002, 0x806c846c, 0x826d806d, 0x8b6dff6d, 0x01ffffff, 0xb8fbf811, - 0xbf0d847b, 0xbfa20078, + 0xbf0d847b, 0xbfa20081, 0xf4003eb6, 0xf8000000, 0xbfc70000, 0xf4003bb6, 0xf8000008, 0x8b76ff7a, 0x80000000, 0xbfa20027, 0x9376ff7a, 0x00060019, 0x81f9a376, 0xbf0b8179, - 0xbfa20068, 0x81f9ac76, - 0xbf0b8179, 0xbfa20062, + 0xbfa2006e, 0x81f9ac76, + 0xbf0b8179, 0xbfa20068, 0x81f9b776, 0xbf0b8179, - 0xbfa2005f, 0x8b76ff7a, + 0xbfa20065, 0x8b76ff7a, 0x000001ff, 0xbf06ff76, - 0x000000fe, 0xbfa2005d, + 0x000000fe, 0xbfa20063, 0xbf06ff76, 0x000000ff, - 0xbfa20057, 0xbf06ff76, - 0x000000fa, 0xbfa20054, + 0xbfa2005d, 0xbf06ff76, + 0x000000fa, 0xbfa2005a, 0x81f9ff76, 0x000000e9, - 0xbf0b8179, 0xbfa20050, + 0xbf0b8179, 0xbfa20056, 0x8b76ff7b, 0xffff0000, 0xbf06ff76, 0xbf860000, - 0xbfa10051, 0x9376ff7b, + 0xbfa1005a, 0x9376ff7b, 0x0002000e, 0x8b79ff7b, 0x00003f00, 0x85798679, 0x8c767976, 0xb9763b01, - 0xbfa00049, 0x8b76ff7a, + 0xbfa00052, 0x8b76ff7a, 0xfc000000, 0xbf06ff76, - 0xd4000000, 0xbfa20013, + 0xd4000000, 0xbfa20019, 0xbf06ff76, 0xc8000000, - 0xbfa20027, 0x8b76ff7a, + 0xbfa2002d, 0x8b76ff7a, 0xff000000, 0xbf06ff76, - 0xcf000000, 0xbfa20039, + 0xcf000000, 0xbfa2003f, 0x8b79ff7a, 0xffff0000, + 0xbf06ff79, 0xcc330000, + 0xbfa2003d, 0xbf06ff79, + 0xcc880000, 0xbfa2003a, 0xbf06ff79, 0xcc350000, - 0xbfa20037, 0xbf06ff79, - 0xcc3a0000, 0xbfa20034, + 0xbfa2003a, 0xbf06ff79, + 0xcc3a0000, 0xbfa20037, 0xbf06ff76, 0xcc000000, - 0xbfa10031, 0x8b76ff7b, + 0xbfa10034, 0x8b76ff7b, 0x000001ff, 0xbf06ff76, 0x000000ff, 0xbfa20029, 0xbf06ff76, 0x000000fa, @@ -4691,86 +4694,92 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { 0x000001ff, 0xbf06ff76, 0x000000ff, 0xbfa20003, 0xbfc70000, 0xbefb006e, - 0xbfa0ffad, 0xbfc70000, - 0xbefb006f, 0xbfa0ffaa, - 0xbfc70000, 0x857a9677, - 0xb97a04a1, 0x857a9577, - 0xb97a0421, 0x857a8e77, - 0xb97a3021, 0x8bfe7e7e, - 0x8bea6a6a, 0x85788978, - 0xb9783244, 0xbe804a6c, - 0xb8faf802, 0xbf0d987a, - 0xbfa10001, 0xbfb00000, - 0x8b6dff6d, 0x01ffffff, - 0xbefa0080, 0xb97a0151, - 0x9177ff77, 0x007fc000, - 0xb8fa04a1, 0x847a967a, - 0x8c777a77, 0xb8fa0421, - 0x847a957a, 0x8c777a77, - 0xb8fa3021, 0x847a8e7a, - 0x8c777a77, 0xb980f821, - 0x00000000, 0xbf0d847b, - 0xbfa20078, 0xf4003eb6, - 0xf8000000, 0xbfc70000, - 0xf4003bb6, 0xf8000008, - 0x8b76ff7a, 0x80000000, - 0xbfa20027, 0x9376ff7a, - 0x00060019, 0x81f9a376, + 0xbfa0ffa7, 0xbfc70000, + 0xbefb006f, 0xbfa0ffa4, + 0x80ec886c, 0x82ed806d, + 0xbfa0fff7, 0xbfc70000, + 0x857a9677, 0xb97a04a1, + 0x857a9577, 0xb97a0421, + 0x857a8e77, 0xb97a3021, + 0x8bfe7e7e, 0x8bea6a6a, + 0x85788978, 0xb9783244, + 0xbe804a6c, 0xb8faf802, + 0xbf0d987a, 0xbfa10001, + 0xbfb00000, 0x8b6dff6d, + 0x01ffffff, 0xbefa0080, + 0xb97a0151, 0x9177ff77, + 0x007fc000, 0xb8fa04a1, + 0x847a967a, 0x8c777a77, + 0xb8fa0421, 0x847a957a, + 0x8c777a77, 0xb8fa3021, + 0x847a8e7a, 0x8c777a77, + 0xb980f821, 0x00000000, + 0xbf0d847b, 0xbfa20081, + 0xf4003eb6, 0xf8000000, + 0xbfc70000, 0xf4003bb6, + 0xf8000008, 0x8b76ff7a, + 0x80000000, 0xbfa20027, + 0x9376ff7a, 0x00060019, + 0x81f9a376, 0xbf0b8179, + 0xbfa2006e, 0x81f9ac76, 0xbf0b8179, 0xbfa20068, - 0x81f9ac76, 0xbf0b8179, - 0xbfa20062, 0x81f9b776, - 0xbf0b8179, 0xbfa2005f, - 0x8b76ff7a, 0x000001ff, - 0xbf06ff76, 0x000000fe, + 0x81f9b776, 0xbf0b8179, + 0xbfa20065, 0x8b76ff7a, + 0x000001ff, 0xbf06ff76, + 0x000000fe, 0xbfa20063, + 0xbf06ff76, 0x000000ff, 0xbfa2005d, 0xbf06ff76, - 0x000000ff, 0xbfa20057, + 0x000000fa, 0xbfa2005a, + 0x81f9ff76, 0x000000e9, + 0xbf0b8179, 0xbfa20056, + 0x8b76ff7b, 0xffff0000, + 0xbf06ff76, 0xbf860000, + 0xbfa1005a, 0x9376ff7b, + 0x0002000e, 0x8b79ff7b, + 0x00003f00, 0x85798679, + 0x8c767976, 0xb9763b01, + 0xbfa00052, 0x8b76ff7a, + 0xfc000000, 0xbf06ff76, + 0xd4000000, 0xbfa20019, + 0xbf06ff76, 0xc8000000, + 0xbfa2002d, 0x8b76ff7a, + 0xff000000, 0xbf06ff76, + 0xcf000000, 0xbfa2003f, + 0x8b79ff7a, 0xffff0000, + 0xbf06ff79, 0xcc330000, + 0xbfa2003d, 0xbf06ff79, + 0xcc880000, 0xbfa2003a, + 0xbf06ff79, 0xcc350000, + 0xbfa2003a, 0xbf06ff79, + 0xcc3a0000, 0xbfa20037, + 0xbf06ff76, 0xcc000000, + 0xbfa10034, 0x8b76ff7b, + 0x000001ff, 0xbf06ff76, + 0x000000ff, 0xbfa20029, 0xbf06ff76, 0x000000fa, - 0xbfa20054, 0x81f9ff76, - 0x000000e9, 0xbf0b8179, - 0xbfa20050, 0x8b76ff7b, - 0xffff0000, 0xbf06ff76, - 0xbf860000, 0xbfa10051, - 0x9376ff7b, 0x0002000e, - 0x8b79ff7b, 0x00003f00, - 0x85798679, 0x8c767976, - 0xb9763b01, 0xbfa00049, - 0x8b76ff7a, 0xfc000000, - 0xbf06ff76, 0xd4000000, - 0xbfa20013, 0xbf06ff76, - 0xc8000000, 0xbfa20027, - 0x8b76ff7a, 0xff000000, - 0xbf06ff76, 0xcf000000, - 0xbfa20039, 0x8b79ff7a, - 0xffff0000, 0xbf06ff79, - 0xcc350000, 0xbfa20037, - 0xbf06ff79, 0xcc3a0000, - 0xbfa20034, 0xbf06ff76, - 0xcc000000, 0xbfa10031, - 0x8b76ff7b, 0x000001ff, - 0xbf06ff76, 0x000000ff, - 0xbfa20029, 0xbf06ff76, - 0x000000fa, 0xbfa20026, - 0x81f6ff76, 0x000000e9, - 0xbf0b8176, 0xbfa20022, - 0x8b76ff7b, 0x0003fe00, - 0xbf06ff76, 0x0001fe00, - 0xbfa2001d, 0x8b76ff7b, - 0x07fc0000, 0xbf06ff76, - 0x03fc0000, 0xbfa20018, - 0xbfa00014, 0x9376ff7a, - 0x00040016, 0x81f68176, - 0xbf0b8176, 0xbfa20012, - 0x9376ff7a, 0x00050011, + 0xbfa20026, 0x81f6ff76, + 0x000000e9, 0xbf0b8176, + 0xbfa20022, 0x8b76ff7b, + 0x0003fe00, 0xbf06ff76, + 0x0001fe00, 0xbfa2001d, + 0x8b76ff7b, 0x07fc0000, + 0xbf06ff76, 0x03fc0000, + 0xbfa20018, 0xbfa00014, + 0x9376ff7a, 0x00040016, 0x81f68176, 0xbf0b8176, - 0xbfa2000d, 0x8b76ff7a, - 0x000001ff, 0xbf06ff76, - 0x000000ff, 0xbfa20008, - 0x8b76ff7b, 0x000001ff, + 0xbfa20012, 0x9376ff7a, + 0x00050011, 0x81f68176, + 0xbf0b8176, 0xbfa2000d, + 0x8b76ff7a, 0x000001ff, 0xbf06ff76, 0x000000ff, - 0xbfa20003, 0xbfc70000, - 0xbefb006e, 0xbfa0ffad, - 0xbfc70000, 0xbefb006f, - 0xbfa0ffaa, 0xbfc70000, + 0xbfa20008, 0x8b76ff7b, + 0x000001ff, 0xbf06ff76, + 0x000000ff, 0xbfa20003, + 0xbfc70000, 0xbefb006e, + 0xbfa0ffa7, 0xbfc70000, + 0xbefb006f, 0xbfa0ffa4, + 0x80ec886c, 0x82ed806d, + 0xbfa0fff7, 0xbfc70000, 0xbeee007e, 0xbeef007f, 0xbefe0180, 0xbefe4d84, 0xbf8a0000, 0x8b7aff7f, diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm index b1b1d15bb1e7..456db8199899 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm @@ -37,6 +37,7 @@ #define HAVE_CLUSTER_BARRIER (ASIC_FAMILY == CHIP_GC_12_0_3) #define CLUSTER_BARRIER_SERIALIZE_WORKAROUND (ASIC_FAMILY == CHIP_GC_12_0_3) #define RELAXED_SCHEDULING_IN_TRAP (ASIC_FAMILY == CHIP_GFX12) +#define HAVE_INSTRUCTION_FIXUP (ASIC_FAMILY == CHIP_GC_12_0_3) #define SINGLE_STEP_MISSED_WORKAROUND 1 //workaround for lost TRAP_AFTER_INST exception when SAVECTX raised #define HAVE_VALU_SGPR_HAZARD (ASIC_FAMILY == CHIP_GFX12) @@ -375,9 +376,9 @@ L_TRAP_CASE: L_EXIT_TRAP: s_and_b32 ttmp1, ttmp1, ADDRESS_HI32_MASK -#if HAVE_BANKED_VGPRS +#if HAVE_INSTRUCTION_FIXUP s_getreg_b32 s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) - fixup_vgpr_bank_selection() + fixup_instruction() #endif #if HAVE_XNACK @@ -418,8 +419,8 @@ L_HAVE_VGPRS: save_and_clear_xnack_state_priv(s_save_tmp) #endif -#if HAVE_BANKED_VGPRS - fixup_vgpr_bank_selection() +#if HAVE_INSTRUCTION_FIXUP + fixup_instruction() #endif /* inform SPI the readiness and wait for SPI's go signal */ @@ -1400,8 +1401,8 @@ L_BARRIER_RESTORE_LOOP: L_BARRIER_RESTORE_DONE: end -#if HAVE_BANKED_VGPRS -function fixup_vgpr_bank_selection +#if HAVE_INSTRUCTION_FIXUP +function fixup_instruction // PC read may fault if memory violation has been asserted. // In this case no further progress is expected so fixup is not needed. s_bitcmp1_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_SHIFT @@ -1480,8 +1481,13 @@ L_FIXUP_NOT_VOP12C: s_cmp_eq_u32 ttmp10, 0xcf000000 // If 31:24 = 0xcf, this is VOPD3 s_cbranch_scc1 L_FIXUP_THREE_DWORD // If VOPD3, 3 DWORD inst // Not VOP1, VOP2, VOPC, VOP3, VOP3SD, VOPD, or VOPD3. - // Might be in VOP3P, but we must ensure we are not VOP3PX2 + // Check if we are in the middle of VOP3PX. s_and_b32 ttmp13, ttmp14, 0xffff0000 // Bits 31:16 + s_cmp_eq_u32 ttmp13, 0xcc330000 // If 31:16 = 0xcc33, this is 8 bytes past VOP3PX + s_cbranch_scc1 L_FIXUP_VOP3PX_MIDDLE + s_cmp_eq_u32 ttmp13, 0xcc880000 // If 31:16 = 0xcc88, this is 8 bytes past VOP3PX + s_cbranch_scc1 L_FIXUP_VOP3PX_MIDDLE + // Might be in VOP3P, but we must ensure we are not VOP3PX2 s_cmp_eq_u32 ttmp13, 0xcc350000 // If 31:16 = 0xcc35, this is VOP3PX2 s_cbranch_scc1 L_FIXUP_DONE // If VOP3PX2, no fixup needed s_cmp_eq_u32 ttmp13, 0xcc3a0000 // If 31:16 = 0xcc3a, this is VOP3PX2 @@ -1542,6 +1548,11 @@ L_FIXUP_THREE_DWORD: s_mov_b32 ttmp15, ttmp3 // Move possible S_SET_VGPR_MSB into ttmp15 s_branch L_FIXUP_ONE_DWORD // Go to common logic that checks if it is S_SET_VGPR_MSB +L_FIXUP_VOP3PX_MIDDLE: + s_sub_co_u32 ttmp0, ttmp0, 8 // Rewind PC 8 bytes to beginning of instruction + s_sub_co_ci_u32 ttmp1, ttmp1, 0 + s_branch L_FIXUP_TWO_DWORD // 2 DWORD inst (2nd half of a 4 DWORD inst) + L_FIXUP_DONE: s_wait_kmcnt 0 // Ensure load of ttmp2 and ttmp3 is done end -- cgit v1.2.3 From 637fee3954d4bd509ea9d95ad1780fc174489860 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 16 Jan 2026 17:33:05 -0500 Subject: drm/amdgpu/soc21: fix xclk for APUs The reference clock is supposed to be 100Mhz, but it appears to actually be slightly lower (99.81Mhz). Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14451 Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc21.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 2da733b45c21..d9cc649d81ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -256,7 +256,13 @@ static u32 soc21_get_config_memsize(struct amdgpu_device *adev) static u32 soc21_get_xclk(struct amdgpu_device *adev) { - return adev->clock.spll.reference_freq; + u32 reference_clock = adev->clock.spll.reference_freq; + + /* reference clock is actually 99.81 Mhz rather than 100 Mhz */ + if ((adev->flags & AMD_IS_APU) && reference_clock == 10000) + return 9981; + + return reference_clock; } -- cgit v1.2.3 From ba205ac3d6e83f56c4f824f23f1b4522cb844ff3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 26 Jan 2026 23:44:45 -0500 Subject: drm/amdgpu: Fix cond_exec handling in amdgpu_ib_schedule() The EXEC_COUNT field must be > 0. In the gfx shadow handling we always emit a cond_exec packet after the gfx_shadow packet, but the EXEC_COUNT never gets patched. This leads to a hang when we try and reset queues on gfx11 APUs. Fixes: c68cbbfd54c6 ("drm/amdgpu: cleanup conditional execution") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4789 Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 72ec455fa932..44f230d67da2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -235,7 +235,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, amdgpu_ring_ib_begin(ring); - if (ring->funcs->emit_gfx_shadow) + if (ring->funcs->emit_gfx_shadow && adev->gfx.cp_gfx_shadow) amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va, init_shadow, vmid); @@ -291,7 +291,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, fence_flags | AMDGPU_FENCE_FLAG_64BIT); } - if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec) { + if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec && + adev->gfx.cp_gfx_shadow) { amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0); amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr); } -- cgit v1.2.3 From 8079b87c02e531cc91601f72ea8336dd2262fdf1 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Wed, 28 Jan 2026 11:35:57 +0800 Subject: drm/amdgpu: validate user queue size constraints MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add validation to ensure user queue sizes meet hardware requirements: - Size must be a power of two for efficient ring buffer wrapping - Size must be at least AMDGPU_GPU_PAGE_SIZE to prevent undersized allocations This prevents invalid configurations that could lead to GPU faults or unexpected behavior. Reviewed-by: Christian König Signed-off-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index b0ebf19db10b..b700c2b91465 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -932,6 +932,17 @@ static int amdgpu_userq_input_args_validate(struct drm_device *dev, drm_file_err(filp, "invalidate userq queue va or size\n"); return -EINVAL; } + + if (!is_power_of_2(args->in.queue_size)) { + drm_file_err(filp, "Queue size must be a power of 2\n"); + return -EINVAL; + } + + if (args->in.queue_size < AMDGPU_GPU_PAGE_SIZE) { + drm_file_err(filp, "Queue size smaller than AMDGPU_GPU_PAGE_SIZE\n"); + return -EINVAL; + } + if (!args->in.wptr_va || !args->in.rptr_va) { drm_file_err(filp, "invalidate userq queue rptr or wptr\n"); return -EINVAL; -- cgit v1.2.3 From 82a9ab369a6785499ad18453bb76b1128403122e Mon Sep 17 00:00:00 2001 From: Lang Yu Date: Mon, 26 Jan 2026 10:08:25 +0800 Subject: drm/amdgpu: Add a helper macro to align mqd size MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) as fence address and writes a 32 bit fence value to this address. Driver needs to allocate some extra memory(at least 4 DWs) in addition to sizeof(struct mqd) as mqd memory(limited to gfx/compute/sdma queue). For gfx11/12, sizeof(struct mqd) < PAGE_SIZE, KGD allocates mqd memory with PAGE_SIZE aligned works. For gfx12.1, sizeof(struct mqd) == PAGE_SIZE, it doesn't work. KFD mqd manager hardcodes mqd size to PAGE_SIZE/MQD_SIZE across different IP versions to solve this issue. To avoid hardcoding in differnet places and across different IP versions. Let's use AMDGPU_MQD_SIZE_ALIGN instead. It is used in two places. 1. mqd memory alloction 2. mqd stride handling for multi xcc config v2: Use AMDGPU_GPU_PAGE_ALIGN. (Mukul) Signed-off-by: Lang Yu Reviewed-by: David Belanger (v1) Reviewed-by: Hawking Zhang Reviewed-by: Mukul Joshi Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 9c11535c44c6..447e734c362b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1239,6 +1239,14 @@ struct amdgpu_device { struct amdgpu_kfd_dev kfd; }; +/* + * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) + * as fence address and writes a 32 bit fence value to this address. + * Driver needs to allocate at least 4 DWs extra memory in addition to + * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. + */ +#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) + static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, uint8_t ip, uint8_t inst) { -- cgit v1.2.3 From f28b0a13865f85f216d4ac9ede75bbf8745a524f Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 16 Jan 2026 12:07:39 +0530 Subject: drm/amd/pm: Add smu feature bits data struct Add a bitmap struct to represent smu feature bits and functions to set/clear features. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 81 +++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 1def04826f10..017df903a7bd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -472,6 +472,11 @@ struct smu_power_context { }; #define SMU_FEATURE_MAX (64) + +struct smu_feature_bits { + DECLARE_BITMAP(bits, SMU_FEATURE_MAX); +}; + struct smu_feature { uint32_t feature_num; DECLARE_BITMAP(supported, SMU_FEATURE_MAX); @@ -1974,4 +1979,80 @@ int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type ms void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id); bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id); + +static inline bool smu_feature_bits_is_set(const struct smu_feature_bits *bits, + unsigned int bit) +{ + if (bit >= SMU_FEATURE_MAX) + return false; + + return test_bit(bit, bits->bits); +} + +static inline void smu_feature_bits_set_bit(struct smu_feature_bits *bits, + unsigned int bit) +{ + if (bit < SMU_FEATURE_MAX) + __set_bit(bit, bits->bits); +} + +static inline void smu_feature_bits_clear_bit(struct smu_feature_bits *bits, + unsigned int bit) +{ + if (bit < SMU_FEATURE_MAX) + __clear_bit(bit, bits->bits); +} + +static inline void smu_feature_bits_clearall(struct smu_feature_bits *bits) +{ + bitmap_zero(bits->bits, SMU_FEATURE_MAX); +} + +static inline void smu_feature_bits_fill(struct smu_feature_bits *bits) +{ + bitmap_fill(bits->bits, SMU_FEATURE_MAX); +} + +static inline bool +smu_feature_bits_test_mask(const struct smu_feature_bits *bits, + const unsigned long *mask) +{ + return bitmap_intersects(bits->bits, mask, SMU_FEATURE_MAX); +} + +static inline void smu_feature_bits_from_arr32(struct smu_feature_bits *bits, + const uint32_t *arr, + unsigned int nbits) +{ + bitmap_from_arr32(bits->bits, arr, nbits); +} + +static inline void +smu_feature_bits_to_arr32(const struct smu_feature_bits *bits, uint32_t *arr, + unsigned int nbits) +{ + bitmap_to_arr32(arr, bits->bits, nbits); +} + +static inline bool smu_feature_bits_empty(const struct smu_feature_bits *bits, + unsigned int nbits) +{ + return bitmap_empty(bits->bits, nbits); +} + +static inline void smu_feature_bits_copy(struct smu_feature_bits *dst, + const unsigned long *src, + unsigned int nbits) +{ + bitmap_copy(dst->bits, src, nbits); +} + +static inline void smu_feature_bits_or(struct smu_feature_bits *dst, + const struct smu_feature_bits *src1, + const unsigned long *src2, + unsigned int nbits) +{ + bitmap_or(dst->bits, src1->bits, src2, nbits); +} + #endif -- cgit v1.2.3 From c99d381d2dcece1cb18ae28706b12da271517dde Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 19 Jan 2026 12:00:29 +0530 Subject: drm/amd/pm: Add smu feature interface functions Instead of using bitmap operations, add wrapper interface functions to operate on smu features. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 20 ++--- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 104 ++++++++++++++++++++++++- drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 5 +- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 4 +- drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 4 +- drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 4 +- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 6 +- 7 files changed, 120 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 3f70731105a2..b635792f5906 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -693,7 +693,6 @@ static int smu_sys_set_pp_table(void *handle, static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) { - struct smu_feature *feature = &smu->smu_feature; uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; int ret = 0; @@ -705,20 +704,19 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) * such scenario. */ if (smu->adev->scpm_enabled) { - bitmap_fill(feature->allowed, SMU_FEATURE_MAX); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } - bitmap_zero(feature->allowed, SMU_FEATURE_MAX); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, SMU_FEATURE_MAX/32); if (ret) return ret; - bitmap_or(feature->allowed, feature->allowed, - (unsigned long *)allowed_feature_mask, - feature->feature_num); + smu_feature_list_add_bits(smu, SMU_FEATURE_LIST_ALLOWED, + (unsigned long *)allowed_feature_mask); return ret; } @@ -1368,9 +1366,7 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block) int i, ret; smu->pool_size = adev->pm.smu_prv_buffer_size; - smu->smu_feature.feature_num = SMU_FEATURE_MAX; - bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); - bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); + smu_feature_init(smu, SMU_FEATURE_MAX); INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); @@ -1659,7 +1655,6 @@ static void smu_wbrf_fini(struct smu_context *smu) static int smu_smc_hw_setup(struct smu_context *smu) { - struct smu_feature *feature = &smu->smu_feature; struct amdgpu_device *adev = smu->adev; uint8_t pcie_gen = 0, pcie_width = 0; uint64_t features_supported; @@ -1822,9 +1817,8 @@ static int smu_smc_hw_setup(struct smu_context *smu) dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); return ret; } - bitmap_copy(feature->supported, - (unsigned long *)&features_supported, - feature->feature_num); + smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED, + (unsigned long *)&features_supported); if (!smu_is_dpm_running(smu)) dev_info(adev->dev, "dpm has been disabled\n"); diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 017df903a7bd..2290298579e1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -477,10 +477,15 @@ struct smu_feature_bits { DECLARE_BITMAP(bits, SMU_FEATURE_MAX); }; +enum smu_feature_list { + SMU_FEATURE_LIST_SUPPORTED, + SMU_FEATURE_LIST_ALLOWED, + SMU_FEATURE_LIST_MAX, +}; + struct smu_feature { uint32_t feature_num; - DECLARE_BITMAP(supported, SMU_FEATURE_MAX); - DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); + struct smu_feature_bits bits[SMU_FEATURE_LIST_MAX]; }; struct smu_clocks { @@ -2055,4 +2060,99 @@ static inline void smu_feature_bits_or(struct smu_feature_bits *dst, bitmap_or(dst->bits, src1->bits, src2, nbits); } +static inline struct smu_feature_bits * +__smu_feature_get_list(struct smu_context *smu, enum smu_feature_list list) +{ + if (unlikely(list >= SMU_FEATURE_LIST_MAX)) { + dev_warn(smu->adev->dev, "Invalid feature list: %d\n", list); + return &smu->smu_feature.bits[SMU_FEATURE_LIST_SUPPORTED]; + } + + return &smu->smu_feature.bits[list]; +} + +static inline bool smu_feature_list_is_set(struct smu_context *smu, + enum smu_feature_list list, + unsigned int bit) +{ + if (bit >= smu->smu_feature.feature_num) + return false; + + return smu_feature_bits_is_set(__smu_feature_get_list(smu, list), bit); +} + +static inline void smu_feature_list_set_bit(struct smu_context *smu, + enum smu_feature_list list, + unsigned int bit) +{ + if (bit >= smu->smu_feature.feature_num) + return; + + smu_feature_bits_set_bit(__smu_feature_get_list(smu, list), bit); +} + +static inline void smu_feature_list_clear_bit(struct smu_context *smu, + enum smu_feature_list list, + unsigned int bit) +{ + if (bit >= smu->smu_feature.feature_num) + return; + + smu_feature_bits_clear_bit(__smu_feature_get_list(smu, list), bit); +} + +static inline void smu_feature_list_set_all(struct smu_context *smu, + enum smu_feature_list list) +{ + smu_feature_bits_fill(__smu_feature_get_list(smu, list)); +} + +static inline void smu_feature_list_clear_all(struct smu_context *smu, + enum smu_feature_list list) +{ + smu_feature_bits_clearall(__smu_feature_get_list(smu, list)); +} + +static inline bool smu_feature_list_is_empty(struct smu_context *smu, + enum smu_feature_list list) +{ + return smu_feature_bits_empty(__smu_feature_get_list(smu, list), + smu->smu_feature.feature_num); +} + +static inline void smu_feature_list_set_bits(struct smu_context *smu, + enum smu_feature_list dst_list, + const unsigned long *src) +{ + smu_feature_bits_copy(__smu_feature_get_list(smu, dst_list), src, + smu->smu_feature.feature_num); +} + +static inline void smu_feature_list_add_bits(struct smu_context *smu, + enum smu_feature_list list, + const unsigned long *src) +{ + struct smu_feature_bits *bits = __smu_feature_get_list(smu, list); + + smu_feature_bits_or(bits, bits, src, smu->smu_feature.feature_num); +} + +static inline void smu_feature_list_to_arr32(struct smu_context *smu, + enum smu_feature_list list, + uint32_t *arr) +{ + smu_feature_bits_to_arr32(__smu_feature_get_list(smu, list), arr, + smu->smu_feature.feature_num); +} + +static inline void smu_feature_init(struct smu_context *smu, int feature_num) +{ + if (!feature_num || smu->smu_feature.feature_num != 0) + return; + + smu->smu_feature.feature_num = feature_num; + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_SUPPORTED); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); +} + #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index eb1b9faf8e5c..1d0f9f8ddf9b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -750,12 +750,13 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu) int ret = 0; uint32_t feature_mask[2]; - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) { + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || + feature->feature_num < 64) { ret = -EINVAL; goto failed; } - bitmap_to_arr32(feature_mask, feature->allowed, 64); + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, feature_mask[1], NULL); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 70581326dc36..3b0aa6a2e78e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -761,11 +761,11 @@ int smu_v13_0_set_allowed_mask(struct smu_context *smu) int ret = 0; uint32_t feature_mask[2]; - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || feature->feature_num < 64) return -EINVAL; - bitmap_to_arr32(feature_mask, feature->allowed, 64); + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, feature_mask[1], NULL); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c index 17caf98bd6dd..cabbd234c6e2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c @@ -746,11 +746,11 @@ int smu_v14_0_set_allowed_mask(struct smu_context *smu) int ret = 0; uint32_t feature_mask[2]; - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || feature->feature_num < 64) return -EINVAL; - bitmap_to_arr32(feature_mask, feature->allowed, 64); + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, feature_mask[1], NULL); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c index 6557085a7c72..d77eaac556d9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c @@ -715,11 +715,11 @@ int smu_v15_0_set_allowed_mask(struct smu_context *smu) int ret = 0; uint32_t feature_mask[2]; - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || feature->feature_num < 64) return -EINVAL; - bitmap_to_arr32(feature_mask, feature->allowed, 64); + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, feature_mask[1], NULL); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 24835600c1cd..9bb7e3760c0f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -677,7 +677,6 @@ int smu_cmn_to_asic_specific_index(struct smu_context *smu, int smu_cmn_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask) { - struct smu_feature *feature = &smu->smu_feature; int feature_id; feature_id = smu_cmn_to_asic_specific_index(smu, @@ -686,9 +685,8 @@ int smu_cmn_feature_is_supported(struct smu_context *smu, if (feature_id < 0) return 0; - WARN_ON(feature_id > feature->feature_num); - - return test_bit(feature_id, feature->supported); + return smu_feature_list_is_set(smu, SMU_FEATURE_LIST_SUPPORTED, + feature_id); } static int __smu_get_enabled_features(struct smu_context *smu, -- cgit v1.2.3 From 156c0ab1de4e917b106deb63cd7583fa45d7ce29 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 19 Jan 2026 12:14:47 +0530 Subject: drm/amd/pm: Remove unused logic in SMUv14.0.2 Remove commented and redundant logic in get_allowed_feature_mask implementation. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal Signed-off-by: Alex Deucher --- .../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 39 ---------------------- 1 file changed, 39 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index faae1da81bd4..d2aa5fabfca4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -268,50 +268,11 @@ static int smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) { - struct amdgpu_device *adev = smu->adev; - /*u32 smu_version;*/ - if (num > 2) return -EINVAL; memset(feature_mask, 0xff, sizeof(uint32_t) * num); - if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); - } -#if 0 - if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) || - !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); - - if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); - - /* PMFW 78.58 contains a critical fix for gfxoff feature */ - smu_cmn_get_smc_version(smu, NULL, &smu_version); - if ((smu_version < 0x004e3a00) || - !(adev->pm.pp_feature & PP_GFXOFF_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); - - if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); - } - - if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); - - if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT); - } - - if (!(adev->pm.pp_feature & PP_ULV_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT); -#endif - return 0; } -- cgit v1.2.3 From 0d9a49a2ce4738bb802cfc0c9ca5abdecd36e96e Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 19 Jan 2026 12:19:40 +0530 Subject: drm/amd/pm: Initialize allowed feature list Instead of returning feature bit mask of allowed features, initialize the allowed features in the callback implementation itself. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 17 +--- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 24 +----- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 11 +-- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 92 ++++++++++------------ .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 89 ++++++++++----------- drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 11 +-- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 35 ++++---- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 12 +-- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 80 +++++++++---------- .../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 11 +-- drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 2 +- 11 files changed, 158 insertions(+), 226 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index b635792f5906..75897ac203c3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -691,11 +691,8 @@ static int smu_sys_set_pp_table(void *handle, return ret; } -static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) +static int smu_init_driver_allowed_feature_mask(struct smu_context *smu) { - uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; - int ret = 0; - /* * With SCPM enabled, the allowed featuremasks setting(via * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. @@ -710,15 +707,7 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); - ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, - SMU_FEATURE_MAX/32); - if (ret) - return ret; - - smu_feature_list_add_bits(smu, SMU_FEATURE_LIST_ALLOWED, - (unsigned long *)allowed_feature_mask); - - return ret; + return smu_init_allowed_features(smu); } static int smu_set_funcs(struct amdgpu_device *adev) @@ -1949,7 +1938,7 @@ static int smu_hw_init(struct amdgpu_ip_block *ip_block) if (!smu->pm_enabled) return 0; - ret = smu_get_driver_allowed_feature_mask(smu); + ret = smu_init_driver_allowed_feature_mask(smu); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 2290298579e1..7c63c631f6d4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -812,11 +812,10 @@ struct pptable_funcs { int (*run_btc)(struct smu_context *smu); /** - * @get_allowed_feature_mask: Get allowed feature mask. - * &feature_mask: Array to store feature mask. - * &num: Elements in &feature_mask. + * @init_allowed_features: Initialize allowed features bitmap. + * Directly sets allowed features using smu_feature wrapper functions. */ - int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); + int (*init_allowed_features)(struct smu_context *smu); /** * @get_current_power_state: Get the current power state. @@ -2052,14 +2051,6 @@ static inline void smu_feature_bits_copy(struct smu_feature_bits *dst, bitmap_copy(dst->bits, src, nbits); } -static inline void smu_feature_bits_or(struct smu_feature_bits *dst, - const struct smu_feature_bits *src1, - const unsigned long *src2, - unsigned int nbits) -{ - bitmap_or(dst->bits, src1->bits, src2, nbits); -} - static inline struct smu_feature_bits * __smu_feature_get_list(struct smu_context *smu, enum smu_feature_list list) { @@ -2128,15 +2119,6 @@ static inline void smu_feature_list_set_bits(struct smu_context *smu, smu->smu_feature.feature_num); } -static inline void smu_feature_list_add_bits(struct smu_context *smu, - enum smu_feature_list list, - const unsigned long *src) -{ - struct smu_feature_bits *bits = __smu_feature_get_list(smu, list); - - smu_feature_bits_or(bits, bits, src, smu->smu_feature.feature_num); -} - static inline void smu_feature_list_to_arr32(struct smu_context *smu, enum smu_feature_list list, uint32_t *arr) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index 7c5ce6a6e2ca..b22a0e91826d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -345,14 +345,9 @@ static int arcturus_init_smc_tables(struct smu_context *smu) } static int -arcturus_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +arcturus_init_allowed_features(struct smu_context *smu) { - if (num > 2) - return -EINVAL; - - /* pptable will handle the features to enable */ - memset(feature_mask, 0xFF, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } @@ -1877,7 +1872,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, static const struct pptable_funcs arcturus_ppt_funcs = { /* init dpm */ - .get_allowed_feature_mask = arcturus_get_allowed_feature_mask, + .init_allowed_features = arcturus_init_allowed_features, /* btc */ .run_btc = arcturus_run_btc, /* dpm/clk tables */ diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index 1f84654bbc85..f14eed052526 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -275,89 +275,83 @@ static bool is_asic_secure(struct smu_context *smu) } static int -navi10_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +navi10_init_allowed_features(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0, sizeof(uint32_t) * num); - - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) - | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) - | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) - | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) - | FEATURE_MASK(FEATURE_PPT_BIT) - | FEATURE_MASK(FEATURE_TDC_BIT) - | FEATURE_MASK(FEATURE_GFX_EDC_BIT) - | FEATURE_MASK(FEATURE_APCC_PLUS_BIT) - | FEATURE_MASK(FEATURE_VR0HOT_BIT) - | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) - | FEATURE_MASK(FEATURE_THERMAL_BIT) - | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) - | FEATURE_MASK(FEATURE_DS_LCLK_BIT) - | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) - | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) - | FEATURE_MASK(FEATURE_BACO_BIT) - | FEATURE_MASK(FEATURE_GFX_SS_BIT) - | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) - | FEATURE_MASK(FEATURE_FW_CTF_BIT) - | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT) - | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); + + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_EDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_PLUS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_LED_DISPLAY_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TEMP_DEPENDENT_VMIN_BIT); if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT); if (adev->pm.pp_feature & PP_ULV_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); if (adev->pm.pp_feature & PP_GFXOFF_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VCN_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_JPEG_PG_BIT); if (smu->dc_controlled_by_gpio) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT); if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); - /* DPM UCLK enablement should be skipped for navi10 A0 secure board */ if (!(is_asic_secure(smu) && (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && (adev->rev_id == 0)) && - (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); + (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT); + } - /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */ if (is_asic_secure(smu) && (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && (adev->rev_id == 0)) - *(uint64_t *)feature_mask &= - ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); return 0; } @@ -3277,7 +3271,7 @@ static int navi10_set_config_table(struct smu_context *smu, } static const struct pptable_funcs navi10_ppt_funcs = { - .get_allowed_feature_mask = navi10_get_allowed_feature_mask, + .init_allowed_features = navi10_init_allowed_features, .set_default_dpm_table = navi10_set_default_dpm_table, .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable, .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index f930ba2733e9..98a02fc08214 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -276,85 +276,82 @@ static const uint8_t sienna_cichlid_throttler_map[] = { }; static int -sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +sienna_cichlid_init_allowed_features(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0, sizeof(uint32_t) * num); - - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) - | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) - | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) - | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) - | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) - | FEATURE_MASK(FEATURE_DS_FCLK_BIT) - | FEATURE_MASK(FEATURE_DS_UCLK_BIT) - | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) - | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) - | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) - | FEATURE_MASK(FEATURE_GFX_SS_BIT) - | FEATURE_MASK(FEATURE_VR0HOT_BIT) - | FEATURE_MASK(FEATURE_PPT_BIT) - | FEATURE_MASK(FEATURE_TDC_BIT) - | FEATURE_MASK(FEATURE_BACO_BIT) - | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) - | FEATURE_MASK(FEATURE_FW_CTF_BIT) - | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) - | FEATURE_MASK(FEATURE_THERMAL_BIT) - | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); + + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_UCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT); if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_GPO_BIT); } if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) && !(adev->flags & AMD_IS_APU)) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_DCS_BIT); - if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); + if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT); + } if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT); if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); if (adev->pm.pp_feature & PP_ULV_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); if (adev->pm.pp_feature & PP_GFXOFF_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_PG_BIT); if (smu->dc_controlled_by_gpio) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT); if (amdgpu_device_should_use_aspm(adev)) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); return 0; } @@ -3085,7 +3082,7 @@ out: } static const struct pptable_funcs sienna_cichlid_ppt_funcs = { - .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, + .init_allowed_features = sienna_cichlid_init_allowed_features, .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index 9de0b676bb7b..3b6a34644a92 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -329,14 +329,9 @@ static int aldebaran_init_smc_tables(struct smu_context *smu) return smu_v13_0_init_smc_tables(smu); } -static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +static int aldebaran_init_allowed_features(struct smu_context *smu) { - if (num > 2) - return -EINVAL; - - /* pptable will handle the features to enable */ - memset(feature_mask, 0xFF, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } @@ -1967,7 +1962,7 @@ static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu, static const struct pptable_funcs aldebaran_ppt_funcs = { /* init dpm */ - .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, + .init_allowed_features = aldebaran_init_allowed_features, /* dpm/clk tables */ .set_default_dpm_table = aldebaran_set_default_dpm_table, .populate_umd_state_clk = aldebaran_populate_umd_state_clk, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index ce52b616b935..9c4298736b28 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -287,49 +287,44 @@ static const uint8_t smu_v13_0_0_throttler_map[] = { }; static int -smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +smu_v13_0_0_init_allowed_features(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0xff, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT); } if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) || !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT); if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); - /* PMFW 78.58 contains a critical fix for gfxoff feature */ if ((smu->smc_fw_version < 0x004e3a00) || !(adev->pm.pp_feature & PP_GFXOFF_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT); } if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); } if (!(adev->pm.pp_feature & PP_ULV_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); return 0; } @@ -3130,7 +3125,7 @@ static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu, } static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { - .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask, + .init_allowed_features = smu_v13_0_0_init_allowed_features, .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table, .i2c_init = smu_v13_0_0_i2c_control_init, .i2c_fini = smu_v13_0_0_i2c_control_fini, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 1e82c43c851a..bd893e95515f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -742,15 +742,9 @@ static int smu_v13_0_6_fini_smc_tables(struct smu_context *smu) return smu_v13_0_fini_smc_tables(smu); } -static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, - uint32_t num) +static int smu_v13_0_6_init_allowed_features(struct smu_context *smu) { - if (num > 2) - return -EINVAL; - - /* pptable will handle the features to enable */ - memset(feature_mask, 0xFF, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } @@ -3836,7 +3830,7 @@ static int smu_v13_0_6_get_ras_smu_drv(struct smu_context *smu, const struct ras static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { /* init dpm */ - .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask, + .init_allowed_features = smu_v13_0_6_init_allowed_features, /* dpm/clk tables */ .set_default_dpm_table = smu_v13_0_6_set_default_dpm_table, .populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index 0375e8484b2a..415766dbfe6c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -265,71 +265,67 @@ static const uint8_t smu_v13_0_7_throttler_map[] = { }; static int -smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +smu_v13_0_7_init_allowed_features(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0, sizeof(uint32_t) * num); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DATA_READ_BIT); if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); } if (adev->pm.pp_feature & PP_GFXOFF_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT); } - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); if (adev->pm.pp_feature & PP_ULV_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); - - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); + + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_VCN_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THROTTLERS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_TEMP_READ_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_MPCLK_DS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_MPCLK_DS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_PCC_DFLL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_CG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT); if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCN_BIT); if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) && (adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT); return 0; } @@ -2736,7 +2732,7 @@ static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu, } static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { - .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask, + .init_allowed_features = smu_v13_0_7_init_allowed_features, .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table, .is_dpm_running = smu_v13_0_7_is_dpm_running, .init_microcode = smu_v13_0_init_microcode, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index d2aa5fabfca4..3c351ee41e68 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -264,14 +264,9 @@ static const uint8_t smu_v14_0_2_throttler_map[] = { [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), }; -static int -smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +static int smu_v14_0_2_init_allowed_features(struct smu_context *smu) { - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0xff, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } @@ -2757,7 +2752,7 @@ static int smu_v14_0_2_set_power_limit(struct smu_context *smu, } static const struct pptable_funcs smu_v14_0_2_ppt_funcs = { - .get_allowed_feature_mask = smu_v14_0_2_get_allowed_feature_mask, + .init_allowed_features = smu_v14_0_2_init_allowed_features, .set_default_dpm_table = smu_v14_0_2_set_default_dpm_table, .i2c_init = smu_v14_0_2_i2c_control_init, .i2c_fini = smu_v14_0_2_i2c_control_fini, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h index 0f7778410a3a..24848da90234 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h @@ -70,7 +70,7 @@ #define smu_apply_clocks_adjust_rules(smu) smu_ppt_funcs(apply_clocks_adjust_rules, 0, smu) #define smu_notify_smc_display_config(smu) smu_ppt_funcs(notify_smc_display_config, 0, smu) #define smu_run_btc(smu) smu_ppt_funcs(run_btc, 0, smu) -#define smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0, smu, feature_mask, num) +#define smu_init_allowed_features(smu) smu_ppt_funcs(init_allowed_features, 0, smu) #define smu_set_watermarks_table(smu, clock_ranges) smu_ppt_funcs(set_watermarks_table, 0, smu, clock_ranges) #define smu_thermal_temperature_range_update(smu, range, rw) smu_ppt_funcs(thermal_temperature_range_update, 0, smu, range, rw) #define smu_register_irq_handler(smu) smu_ppt_funcs(register_irq_handler, 0, smu) -- cgit v1.2.3 From a6a4dd519cbe1fdf1f33e2942356dcc9c7b4c682 Mon Sep 17 00:00:00 2001 From: Lang Yu Date: Mon, 26 Jan 2026 16:47:39 +0800 Subject: drm/amdgpu: Use AMDGPU_MQD_SIZE_ALIGN in KGD Use AMDGPU_MQD_SIZE_ALIGN for both kernel and user queue. Signed-off-by: Lang Yu Reviewed-by: David Belanger Reviewed-by: Hawking Zhang Reviewed-by: Mukul Joshi Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 18 ++++++++++-------- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 2 +- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 3 ++- 3 files changed, 13 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 8b5801d7109c..77578ecc6782 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -385,6 +385,8 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; struct amdgpu_ring *ring = &kiq->ring; u32 domain = AMDGPU_GEM_DOMAIN_GTT; + u32 gfx_mqd_size = max(adev->mqds[AMDGPU_HW_IP_GFX].mqd_size, mqd_size); + u32 compute_mqd_size = max(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size, mqd_size); #if !defined(CONFIG_ARM) && !defined(CONFIG_ARM64) /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */ @@ -424,17 +426,17 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, for (i = 0; i < adev->gfx.num_gfx_rings; i++) { ring = &adev->gfx.gfx_ring[i]; if (!ring->mqd_obj) { - r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, - domain, &ring->mqd_obj, + r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(gfx_mqd_size), + PAGE_SIZE, domain, &ring->mqd_obj, &ring->mqd_gpu_addr, &ring->mqd_ptr); if (r) { dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); return r; } - ring->mqd_size = mqd_size; + ring->mqd_size = gfx_mqd_size; /* prepare MQD backup */ - adev->gfx.me.mqd_backup[i] = kzalloc(mqd_size, GFP_KERNEL); + adev->gfx.me.mqd_backup[i] = kzalloc(gfx_mqd_size, GFP_KERNEL); if (!adev->gfx.me.mqd_backup[i]) { dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); return -ENOMEM; @@ -448,17 +450,17 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, j = i + xcc_id * adev->gfx.num_compute_rings; ring = &adev->gfx.compute_ring[j]; if (!ring->mqd_obj) { - r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, - domain, &ring->mqd_obj, + r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(compute_mqd_size), + PAGE_SIZE, domain, &ring->mqd_obj, &ring->mqd_gpu_addr, &ring->mqd_ptr); if (r) { dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); return r; } - ring->mqd_size = mqd_size; + ring->mqd_size = compute_mqd_size; /* prepare MQD backup */ - adev->gfx.mec.mqd_backup[j] = kzalloc(mqd_size, GFP_KERNEL); + adev->gfx.mec.mqd_backup[j] = kzalloc(compute_mqd_size, GFP_KERNEL); if (!adev->gfx.mec.mqd_backup[j]) { dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); return -ENOMEM; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 08ae50a6313f..eb9725ae1607 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -2236,7 +2236,7 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m, mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; mqd->cp_mqd_stride_size = prop->mqd_stride_size ? prop->mqd_stride_size : - sizeof(struct v12_1_compute_mqd); + AMDGPU_MQD_SIZE_ALIGN(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size); mqd->cp_hqd_active = prop->hqd_active; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index f2309d72bbe6..9508709abd49 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -289,7 +289,8 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, return -ENOMEM; } - r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, mqd_hw_default->mqd_size); + r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, + AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size)); if (r) { DRM_ERROR("Failed to create MQD object for userqueue\n"); goto free_props; -- cgit v1.2.3 From 3aca6f835ba1635e49d9b76d2102b218643d276e Mon Sep 17 00:00:00 2001 From: Lang Yu Date: Mon, 26 Jan 2026 16:57:01 +0800 Subject: drm/amdkfd: Adjust parameter of allocate_mqd Make allocate_mqd consistent with other callbacks. Prepare for next patch to use mqd_manager->mqd_size. Signed-off-by: Lang Yu Reviewed-by: David Belanger Reviewed-by: Hawking Zhang Reviewed-by: Mukul Joshi Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 6 ++++-- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 3 ++- 11 files changed, 24 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index b542de9d50d1..804851632c4c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -676,7 +676,7 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, /* Temporarily release dqm lock to avoid a circular lock dependency */ dqm_unlock(dqm); - q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); + q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties); dqm_lock(dqm); if (!q->mqd_mem_obj) { @@ -2002,7 +2002,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, dqm->asic_ops.init_sdma_vm(dqm, q, qpd); q->properties.tba_addr = qpd->tba_addr; q->properties.tma_addr = qpd->tma_addr; - q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); + q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties); if (!q->mqd_mem_obj) { retval = -ENOMEM; goto out_deallocate_doorbell; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c index 961a4b84e974..d987ff7ccfc9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c @@ -130,7 +130,7 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev, kq->queue->device = dev; - kq->queue->mqd_mem_obj = kq->mqd_mgr->allocate_mqd(kq->mqd_mgr->dev, + kq->queue->mqd_mem_obj = kq->mqd_mgr->allocate_mqd(kq->mqd_mgr, &kq->queue->properties); if (!kq->queue->mqd_mem_obj) goto err_allocate_mqd; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c index f78b249e1a41..ceb6566ff3e1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c @@ -46,9 +46,10 @@ int pipe_priority_map[] = { KFD_PIPE_PRIORITY_CS_HIGH }; -struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, struct queue_properties *q) +struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm, struct queue_properties *q) { struct kfd_mem_obj *mqd_mem_obj; + struct kfd_node *dev = mm->dev; mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); if (!mqd_mem_obj) @@ -61,10 +62,11 @@ struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, struct queue_properti return mqd_mem_obj; } -struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev, +struct kfd_mem_obj *allocate_sdma_mqd(struct mqd_manager *mm, struct queue_properties *q) { struct kfd_mem_obj *mqd_mem_obj; + struct kfd_node *dev = mm->dev; uint64_t offset; mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h index 17cc1f25c8d0..2429d278ef0e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h @@ -68,7 +68,7 @@ */ extern int pipe_priority_map[]; struct mqd_manager { - struct kfd_mem_obj* (*allocate_mqd)(struct kfd_node *kfd, + struct kfd_mem_obj* (*allocate_mqd)(struct mqd_manager *mm, struct queue_properties *q); void (*init_mqd)(struct mqd_manager *mm, void **mqd, @@ -153,10 +153,10 @@ struct mqd_user_context_save_area_header { uint32_t wave_state_size; }; -struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, +struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm, struct queue_properties *q); -struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev, +struct kfd_mem_obj *allocate_sdma_mqd(struct mqd_manager *mm, struct queue_properties *q); void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd, struct kfd_mem_obj *mqd_mem_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 05f3ac2eaef9..90ac3a30e81d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -73,9 +73,10 @@ static void set_priority(struct cik_mqd *m, struct queue_properties *q) m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *kfd = mm->dev; struct kfd_mem_obj *mqd_mem_obj; if (kfd_gtt_sa_allocate(kfd, sizeof(struct cik_mqd), diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 1695dd78ede8..97055f808d4a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -73,9 +73,10 @@ static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *kfd = mm->dev; struct kfd_mem_obj *mqd_mem_obj; if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd), diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 3c0ae28c5923..5c44d0987737 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -99,9 +99,10 @@ static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q) m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; int size; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index 729df66ebfb3..b7ac2dea8775 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -80,9 +80,10 @@ static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q) m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; /* diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c index 558216395a4d..0b0d802a0917 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c @@ -145,9 +145,10 @@ static void set_priority(struct v12_1_compute_mqd *m, struct queue_properties *q m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; unsigned int size; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index d867dccae675..dcf4bbfa641b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -120,10 +120,11 @@ static bool mqd_on_vram(struct amdgpu_device *adev) } } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { int retval; + struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj = NULL; /* For V9 only, due to a HW bug, the control stack of a user mode diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index c1fafc502515..09483f0862d4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -76,9 +76,10 @@ static void set_priority(struct vi_mqd *m, struct queue_properties *q) m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *kfd = mm->dev; struct kfd_mem_obj *mqd_mem_obj; if (kfd_gtt_sa_allocate(kfd, sizeof(struct vi_mqd), -- cgit v1.2.3 From 2bddc36c121918a523132ee369a6c76da702748c Mon Sep 17 00:00:00 2001 From: Lang Yu Date: Mon, 26 Jan 2026 17:38:01 +0800 Subject: drm/amdkfd: Use AMDGPU_MQD_SIZE_ALIGN in gfx11+ kfd mqd manager MES is enabled by default from gfx11+, use AMDGPU_MQD_SIZE_ALIGN unconditionally for gfx11+. Signed-off-by: Lang Yu Reviewed-by: David Belanger Reviewed-by: Hawking Zhang Reviewed-by: Mukul Joshi Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 3 +++ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 22 +++------------- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 10 +++----- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 29 +++++----------------- 4 files changed, 17 insertions(+), 47 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c index ceb6566ff3e1..d88d0de58edd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c @@ -292,6 +292,9 @@ void kfd_get_hiq_xcc_mqd(struct kfd_node *dev, struct kfd_mem_obj *mqd_mem_obj, uint64_t kfd_mqd_stride(struct mqd_manager *mm, struct queue_properties *q) { + if (KFD_GC_VERSION(mm->dev) >= IP_VERSION(11, 0, 0)) + return AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); + return mm->mqd_size; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 5c44d0987737..7e5a7ab6d0c0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -102,20 +102,11 @@ static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q) static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; - int size; - - /* - * MES write to areas beyond MQD size. So allocate - * 1 PAGE_SIZE memory for MQD is MES is enabled. - */ - if (node->kfd->shared_resources.enable_mes) - size = PAGE_SIZE; - else - size = sizeof(struct v11_compute_mqd); - if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj)) + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) return NULL; return mqd_mem_obj; @@ -127,18 +118,13 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, { uint64_t addr; struct v11_compute_mqd *m; - int size; + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff; m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr; addr = mqd_mem_obj->gpu_addr; - if (mm->dev->kfd->shared_resources.enable_mes) - size = PAGE_SIZE; - else - size = sizeof(struct v11_compute_mqd); - - memset(m, 0, size); + memset(m, 0, mqd_size); m->header = 0xC0310800; m->compute_pipelinestat_enable = 1; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index b7ac2dea8775..a51f217329db 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -83,14 +83,11 @@ static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q) static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; - /* - * Allocate one PAGE_SIZE memory for MQD as MES writes to areas beyond - * struct MQD size. - */ - if (kfd_gtt_sa_allocate(node, PAGE_SIZE, &mqd_mem_obj)) + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) return NULL; return mqd_mem_obj; @@ -102,11 +99,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, { uint64_t addr; struct v12_compute_mqd *m; + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); m = (struct v12_compute_mqd *) mqd_mem_obj->cpu_ptr; addr = mqd_mem_obj->gpu_addr; - memset(m, 0, PAGE_SIZE); + memset(m, 0, mqd_size); m->header = 0xC0310800; m->compute_pipelinestat_enable = 1; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c index 0b0d802a0917..d0776ba2cc99 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c @@ -32,17 +32,6 @@ #include "amdgpu_amdkfd.h" #include "kfd_device_queue_manager.h" -#define MQD_SIZE (2 * PAGE_SIZE) - -static uint64_t mqd_stride_v12_1(struct mqd_manager *mm, - struct queue_properties *q) -{ - if (q->type == KFD_QUEUE_TYPE_COMPUTE) - return MQD_SIZE; - else - return PAGE_SIZE; -} - static inline struct v12_1_compute_mqd *get_mqd(void *mqd) { return (struct v12_1_compute_mqd *)mqd; @@ -148,21 +137,14 @@ static void set_priority(struct v12_1_compute_mqd *m, struct queue_properties *q static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; - unsigned int size; - /* - * Allocate two PAGE_SIZE memory for Compute MQD as MES writes to areas beyond - * struct MQD size. Size of the Compute MQD is 1 PAGE_SIZE. - * For SDMA MQD, we allocate 1 Page_size. - */ if (q->type == KFD_QUEUE_TYPE_COMPUTE) - size = MQD_SIZE * NUM_XCC(node->xcc_mask); - else - size = PAGE_SIZE; + mqd_size *= NUM_XCC(node->xcc_mask); - if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj)) + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) return NULL; return mqd_mem_obj; @@ -174,11 +156,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, { uint64_t addr; struct v12_1_compute_mqd *m; + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); m = (struct v12_1_compute_mqd *) mqd_mem_obj->cpu_ptr; addr = mqd_mem_obj->gpu_addr; - memset(m, 0, MQD_SIZE); + memset(m, 0, mqd_size); m->header = 0xC0310800; m->compute_pipelinestat_enable = 1; @@ -681,7 +664,7 @@ struct mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type, mqd->is_occupied = kfd_is_occupied_cp; mqd->mqd_size = sizeof(struct v12_1_compute_mqd); mqd->get_wave_state = get_wave_state_v12_1; - mqd->mqd_stride = mqd_stride_v12_1; + mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) mqd->debugfs_show_mqd = debugfs_show_mqd; #endif -- cgit v1.2.3 From e80b1d1aa1073230b6c25a1a72e88f37e425ccda Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 28 Jan 2026 20:51:08 -0500 Subject: drm/amdgpu/gfx10: fix wptr reset in KGQ init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit wptr is a 64 bit value and we need to update the full value, not just 32 bits. Align with what we already do for KCQs. Reviewed-by: Timur Kristóf Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 41bbedb8e157..1893ceeeb26c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -6880,7 +6880,7 @@ static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); /* reset the ring */ ring->wptr = 0; - *ring->wptr_cpu_addr = 0; + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); amdgpu_ring_clear_ring(ring); } -- cgit v1.2.3 From 1f16866bdb1daed7a80ca79ae2837a9832a74fbc Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 28 Jan 2026 18:09:03 -0500 Subject: drm/amdgpu/gfx11: fix wptr reset in KGQ init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit wptr is a 64 bit value and we need to update the full value, not just 32 bits. Align with what we already do for KCQs. Reviewed-by: Timur Kristóf Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 3a4ca104b161..7bc593889c71 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4214,7 +4214,7 @@ static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); /* reset the ring */ ring->wptr = 0; - *ring->wptr_cpu_addr = 0; + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); amdgpu_ring_clear_ring(ring); } -- cgit v1.2.3 From a2918f958d3f677ea93c0ac257cb6ba69b7abb7c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 28 Jan 2026 18:13:16 -0500 Subject: drm/amdgpu/gfx12: fix wptr reset in KGQ init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit wptr is a 64 bit value and we need to update the full value, not just 32 bits. Align with what we already do for KCQs. Reviewed-by: Timur Kristóf Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 40660b05f979..3aec7ea773fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3085,7 +3085,7 @@ static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); /* reset the ring */ ring->wptr = 0; - *ring->wptr_cpu_addr = 0; + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); amdgpu_ring_clear_ring(ring); } -- cgit v1.2.3 From b340ff216fdabfe71ba0cdd47e9835a141d08e10 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 28 Jan 2026 22:55:46 -0500 Subject: drm/amdgpu/gfx11: adjust KGQ reset sequence MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Kernel gfx queues do not need to be reinitialized or remapped after a reset. This fixes queue reset failures on APUs. v2: preserve init and remap for MMIO case. Fixes: b3e9bfd86658 ("drm/amdgpu/gfx11: add ring reset callbacks") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4789 Reviewed-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 7bc593889c71..427975b5a1d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6828,11 +6828,12 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, struct amdgpu_fence *timedout_fence) { struct amdgpu_device *adev = ring->adev; + bool use_mmio = false; int r; amdgpu_ring_reset_helper_begin(ring, timedout_fence); - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false, 0); + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0); if (r) { dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); @@ -6841,16 +6842,18 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, return r; } - r = gfx_v11_0_kgq_init_queue(ring, true); - if (r) { - dev_err(adev->dev, "failed to init kgq\n"); - return r; - } + if (use_mmio) { + r = gfx_v11_0_kgq_init_queue(ring, true); + if (r) { + dev_err(adev->dev, "failed to init kgq\n"); + return r; + } - r = amdgpu_mes_map_legacy_queue(adev, ring, 0); - if (r) { - dev_err(adev->dev, "failed to remap kgq\n"); - return r; + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); + if (r) { + dev_err(adev->dev, "failed to remap kgq\n"); + return r; + } } return amdgpu_ring_reset_helper_end(ring, timedout_fence); -- cgit v1.2.3 From 0a6d6ed694d72b66b0ed7a483d5effa01acd3951 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 28 Jan 2026 23:05:50 -0500 Subject: drm/amdgpu/gfx12: adjust KGQ reset sequence MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Kernel gfx queues do not need to be reinitialized or remapped after a reset. Align with gfx11. v2: preserve init and remap for MMIO case. Reviewed-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 3aec7ea773fc..79ea1af363a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -5292,11 +5292,12 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, struct amdgpu_fence *timedout_fence) { struct amdgpu_device *adev = ring->adev; + bool use_mmio = false; int r; amdgpu_ring_reset_helper_begin(ring, timedout_fence); - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false, 0); + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0); if (r) { dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); r = gfx_v12_reset_gfx_pipe(ring); @@ -5304,16 +5305,18 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, return r; } - r = gfx_v12_0_kgq_init_queue(ring, true); - if (r) { - dev_err(adev->dev, "failed to init kgq\n"); - return r; - } + if (use_mmio) { + r = gfx_v12_0_kgq_init_queue(ring, true); + if (r) { + dev_err(adev->dev, "failed to init kgq\n"); + return r; + } - r = amdgpu_mes_map_legacy_queue(adev, ring, 0); - if (r) { - dev_err(adev->dev, "failed to remap kgq\n"); - return r; + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); + if (r) { + dev_err(adev->dev, "failed to remap kgq\n"); + return r; + } } return amdgpu_ring_reset_helper_end(ring, timedout_fence); -- cgit v1.2.3