From 9593bd07ec8eaaa30aba4281b2b3273282fc344f Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Thu, 24 Dec 2009 00:02:16 -0800 Subject: sony-laptop - remove private workqueue, use keventd instead If we reschedule work instead of having work function sleep for 10 msecs between reads from kfifo we can safely use the main workqueue (keventd) and not bother with creating driver-private one. Signed-off-by: Dmitry Torokhov Signed-off-by: Len Brown --- drivers/platform/x86/sony-laptop.c | 71 +++++++++++++++++++++----------------- 1 file changed, 39 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/platform/x86/sony-laptop.c b/drivers/platform/x86/sony-laptop.c index 5af53340da6f..c42d35ba73d6 100644 --- a/drivers/platform/x86/sony-laptop.c +++ b/drivers/platform/x86/sony-laptop.c @@ -145,7 +145,6 @@ struct sony_laptop_input_s { struct input_dev *key_dev; struct kfifo fifo; spinlock_t fifo_lock; - struct workqueue_struct *wq; }; static struct sony_laptop_input_s sony_laptop_input = { @@ -301,18 +300,28 @@ static int sony_laptop_input_keycode_map[] = { /* release buttons after a short delay if pressed */ static void do_sony_laptop_release_key(struct work_struct *work) { + struct delayed_work *dwork = + container_of(work, struct delayed_work, work); struct sony_laptop_keypress kp; + unsigned long flags; + + spin_lock_irqsave(&sony_laptop_input.fifo_lock, flags); - while (kfifo_out_locked(&sony_laptop_input.fifo, (unsigned char *)&kp, - sizeof(kp), &sony_laptop_input.fifo_lock) - == sizeof(kp)) { - msleep(10); + if (kfifo_out(&sony_laptop_input.fifo, + (unsigned char *)&kp, sizeof(kp)) == sizeof(kp)) { input_report_key(kp.dev, kp.key, 0); input_sync(kp.dev); } + + /* If there is something in the fifo schedule next release. */ + if (kfifo_len(&sony_laptop_input.fifo) != 0) + schedule_delayed_work(dwork, msecs_to_jiffies(10)); + + spin_unlock_irqrestore(&sony_laptop_input.fifo_lock, flags); } -static DECLARE_WORK(sony_laptop_release_key_work, - do_sony_laptop_release_key); + +static DECLARE_DELAYED_WORK(sony_laptop_release_key_work, + do_sony_laptop_release_key); /* forward event to the input subsystem */ static void sony_laptop_report_input_event(u8 event) @@ -366,13 +375,13 @@ static void sony_laptop_report_input_event(u8 event) /* we emit the scancode so we can always remap the key */ input_event(kp.dev, EV_MSC, MSC_SCAN, event); input_sync(kp.dev); - kfifo_in_locked(&sony_laptop_input.fifo, - (unsigned char *)&kp, sizeof(kp), - &sony_laptop_input.fifo_lock); - if (!work_pending(&sony_laptop_release_key_work)) - queue_work(sony_laptop_input.wq, - &sony_laptop_release_key_work); + /* schedule key release */ + kfifo_in_locked(&sony_laptop_input.fifo, + (unsigned char *)&kp, sizeof(kp), + &sony_laptop_input.fifo_lock); + schedule_delayed_work(&sony_laptop_release_key_work, + msecs_to_jiffies(10)); } else dprintk("unknown input event %.2x\n", event); } @@ -390,27 +399,18 @@ static int sony_laptop_setup_input(struct acpi_device *acpi_device) /* kfifo */ spin_lock_init(&sony_laptop_input.fifo_lock); - error = - kfifo_alloc(&sony_laptop_input.fifo, SONY_LAPTOP_BUF_SIZE, GFP_KERNEL); + error = kfifo_alloc(&sony_laptop_input.fifo, + SONY_LAPTOP_BUF_SIZE, GFP_KERNEL); if (error) { printk(KERN_ERR DRV_PFX "kfifo_alloc failed\n"); goto err_dec_users; } - /* init workqueue */ - sony_laptop_input.wq = create_singlethread_workqueue("sony-laptop"); - if (!sony_laptop_input.wq) { - printk(KERN_ERR DRV_PFX - "Unable to create workqueue.\n"); - error = -ENXIO; - goto err_free_kfifo; - } - /* input keys */ key_dev = input_allocate_device(); if (!key_dev) { error = -ENOMEM; - goto err_destroy_wq; + goto err_free_kfifo; } key_dev->name = "Sony Vaio Keys"; @@ -473,9 +473,6 @@ err_unregister_keydev: err_free_keydev: input_free_device(key_dev); -err_destroy_wq: - destroy_workqueue(sony_laptop_input.wq); - err_free_kfifo: kfifo_free(&sony_laptop_input.fifo); @@ -486,12 +483,23 @@ err_dec_users: static void sony_laptop_remove_input(void) { - /* cleanup only after the last user has gone */ + struct sony_laptop_keypress kp = { NULL }; + + /* Cleanup only after the last user has gone */ if (!atomic_dec_and_test(&sony_laptop_input.users)) return; - /* flush workqueue first */ - flush_workqueue(sony_laptop_input.wq); + cancel_delayed_work_sync(&sony_laptop_release_key_work); + + /* + * Generate key-up events for remaining keys. Note that we don't + * need locking since nobody is adding new events to the kfifo. + */ + while (kfifo_out(&sony_laptop_input.fifo, + (unsigned char *)&kp, sizeof(kp)) == sizeof(kp)) { + input_report_key(kp.dev, kp.key, 0); + input_sync(kp.dev); + } /* destroy input devs */ input_unregister_device(sony_laptop_input.key_dev); @@ -502,7 +510,6 @@ static void sony_laptop_remove_input(void) sony_laptop_input.jog_dev = NULL; } - destroy_workqueue(sony_laptop_input.wq); kfifo_free(&sony_laptop_input.fifo); } -- cgit v1.2.3 From c45bc9d62c39202b401d1bf7bb2812abb88798a1 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Thu, 24 Dec 2009 00:02:23 -0800 Subject: sony-laptop - simplify keymap initialization Also use input_set_capability() helper instead of manipulating bits directly. Signed-off-by: Dmitry Torokhov Signed-off-by: Len Brown --- drivers/platform/x86/sony-laptop.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/platform/x86/sony-laptop.c b/drivers/platform/x86/sony-laptop.c index c42d35ba73d6..b7aa959b0c05 100644 --- a/drivers/platform/x86/sony-laptop.c +++ b/drivers/platform/x86/sony-laptop.c @@ -419,18 +419,15 @@ static int sony_laptop_setup_input(struct acpi_device *acpi_device) key_dev->dev.parent = &acpi_device->dev; /* Initialize the Input Drivers: special keys */ - set_bit(EV_KEY, key_dev->evbit); - set_bit(EV_MSC, key_dev->evbit); - set_bit(MSC_SCAN, key_dev->mscbit); + input_set_capability(key_dev, EV_MSC, MSC_SCAN); + + __set_bit(EV_KEY, key_dev->evbit); key_dev->keycodesize = sizeof(sony_laptop_input_keycode_map[0]); key_dev->keycodemax = ARRAY_SIZE(sony_laptop_input_keycode_map); key_dev->keycode = &sony_laptop_input_keycode_map; - for (i = 0; i < ARRAY_SIZE(sony_laptop_input_keycode_map); i++) { - if (sony_laptop_input_keycode_map[i] != KEY_RESERVED) { - set_bit(sony_laptop_input_keycode_map[i], - key_dev->keybit); - } - } + for (i = 0; i < ARRAY_SIZE(sony_laptop_input_keycode_map); i++) + __set_bit(sony_laptop_input_keycode_map[i], key_dev->keybit); + __clear_bit(KEY_RESERVED, key_dev->keybit); error = input_register_device(key_dev); if (error) @@ -450,9 +447,8 @@ static int sony_laptop_setup_input(struct acpi_device *acpi_device) jog_dev->id.vendor = PCI_VENDOR_ID_SONY; key_dev->dev.parent = &acpi_device->dev; - jog_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REL); - jog_dev->keybit[BIT_WORD(BTN_MOUSE)] = BIT_MASK(BTN_MIDDLE); - jog_dev->relbit[0] = BIT_MASK(REL_WHEEL); + input_set_capability(jog_dev, EV_KEY, BTN_MIDDLE); + input_set_capability(jog_dev, EV_REL, REL_WHEEL); error = input_register_device(jog_dev); if (error) -- cgit v1.2.3 From cffdde993a016bedbc2f5eb60d00c3a766ffb612 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Thu, 24 Dec 2009 00:02:30 -0800 Subject: sony-laptop - switch from workqueue to a timer The function that is executing in workqueue context does not need to sleep so let's switch to a timer which is more lightweight. Signed-off-by: Dmitry Torokhov Signed-off-by: Len Brown --- drivers/platform/x86/sony-laptop.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/platform/x86/sony-laptop.c b/drivers/platform/x86/sony-laptop.c index b7aa959b0c05..cc7172ea19dd 100644 --- a/drivers/platform/x86/sony-laptop.c +++ b/drivers/platform/x86/sony-laptop.c @@ -145,6 +145,7 @@ struct sony_laptop_input_s { struct input_dev *key_dev; struct kfifo fifo; spinlock_t fifo_lock; + struct timer_list release_key_timer; }; static struct sony_laptop_input_s sony_laptop_input = { @@ -298,10 +299,8 @@ static int sony_laptop_input_keycode_map[] = { }; /* release buttons after a short delay if pressed */ -static void do_sony_laptop_release_key(struct work_struct *work) +static void do_sony_laptop_release_key(unsigned long unused) { - struct delayed_work *dwork = - container_of(work, struct delayed_work, work); struct sony_laptop_keypress kp; unsigned long flags; @@ -315,14 +314,12 @@ static void do_sony_laptop_release_key(struct work_struct *work) /* If there is something in the fifo schedule next release. */ if (kfifo_len(&sony_laptop_input.fifo) != 0) - schedule_delayed_work(dwork, msecs_to_jiffies(10)); + mod_timer(&sony_laptop_input.release_key_timer, + jiffies + msecs_to_jiffies(10)); spin_unlock_irqrestore(&sony_laptop_input.fifo_lock, flags); } -static DECLARE_DELAYED_WORK(sony_laptop_release_key_work, - do_sony_laptop_release_key); - /* forward event to the input subsystem */ static void sony_laptop_report_input_event(u8 event) { @@ -380,8 +377,8 @@ static void sony_laptop_report_input_event(u8 event) kfifo_in_locked(&sony_laptop_input.fifo, (unsigned char *)&kp, sizeof(kp), &sony_laptop_input.fifo_lock); - schedule_delayed_work(&sony_laptop_release_key_work, - msecs_to_jiffies(10)); + mod_timer(&sony_laptop_input.release_key_timer, + jiffies + msecs_to_jiffies(10)); } else dprintk("unknown input event %.2x\n", event); } @@ -406,6 +403,9 @@ static int sony_laptop_setup_input(struct acpi_device *acpi_device) goto err_dec_users; } + setup_timer(&sony_laptop_input.release_key_timer, + do_sony_laptop_release_key, 0); + /* input keys */ key_dev = input_allocate_device(); if (!key_dev) { @@ -485,7 +485,7 @@ static void sony_laptop_remove_input(void) if (!atomic_dec_and_test(&sony_laptop_input.users)) return; - cancel_delayed_work_sync(&sony_laptop_release_key_work); + del_timer_sync(&sony_laptop_input.release_key_timer); /* * Generate key-up events for remaining keys. Note that we don't -- cgit v1.2.3 From 0c99c5288eb9b1bbc9684b0ec0fd7efc578749b3 Mon Sep 17 00:00:00 2001 From: Zhang Rui Date: Thu, 17 Dec 2009 16:02:08 +0800 Subject: ACPI: Disable explicit power state retrieval on fans If the ACPI power state can be got both directly and indirectly, we prefer to get it indirectly. https://bugzilla.redhat.com/show_bug.cgi?id=531916 describes a system with a _PSC method for the fan that always returns "on". There's no benefit in us always requesting the state of the fan when performing transitions - we want to do everything we can to ensure that the fan turns on when it should do, not risk hardware damage by believing the hardware when it tells us the fan is already on. Given that the Leading Other OS(tm) works fine on this machine, it seems likely that it behaves in much this way. inspired-by: Matthew Garrett Signed-off-by: Zhang Rui Signed-off-by: Len Brown --- drivers/acpi/bus.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index cf761b904e4a..ae9226de93a6 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -190,16 +190,16 @@ int acpi_bus_get_power(acpi_handle handle, int *state) * Get the device's power state either directly (via _PSC) or * indirectly (via power resources). */ - if (device->power.flags.explicit_get) { + if (device->power.flags.power_resources) { + result = acpi_power_get_inferred_state(device); + if (result) + return result; + } else if (device->power.flags.explicit_get) { status = acpi_evaluate_integer(device->handle, "_PSC", NULL, &psc); if (ACPI_FAILURE(status)) return -ENODEV; device->power.state = (int)psc; - } else if (device->power.flags.power_resources) { - result = acpi_power_get_inferred_state(device); - if (result) - return result; } *state = device->power.state; -- cgit v1.2.3 From 4cd7d9247ffa2a27508c69563b66713519c196f5 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Fri, 8 Jan 2010 00:11:01 -0800 Subject: scc_pata: fix module unloading scc_pata host driver predated module unloading support for IDE host drivers so even though it supports PCI hot-unplug and implements PCI device ->remove method it doesn't allow module removal. Fix it. Add missing __init/__exit tags to module_init/module_exit functions while at it (from Peter Huewe). Noticed-by: Jiri Kosina Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/scc_pata.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/scc_pata.c b/drivers/ide/scc_pata.c index 1104bb301eb9..8066168992d7 100644 --- a/drivers/ide/scc_pata.c +++ b/drivers/ide/scc_pata.c @@ -872,20 +872,18 @@ static struct pci_driver scc_pci_driver = { .remove = __devexit_p(scc_remove), }; -static int scc_ide_init(void) +static int __init scc_ide_init(void) { return ide_pci_register_driver(&scc_pci_driver); } -module_init(scc_ide_init); -/* -- No exit code? -static void scc_ide_exit(void) +static void __exit scc_ide_exit(void) { - ide_pci_unregister_driver(&scc_pci_driver); + pci_unregister_driver(&scc_pci_driver); } -module_exit(scc_ide_exit); - */ +module_init(scc_ide_init); +module_exit(scc_ide_exit); MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 145434bee45bd353f9a93e9b411f7aa7cc677c08 Mon Sep 17 00:00:00 2001 From: David Vrabel Date: Mon, 11 Jan 2010 13:46:31 +0000 Subject: uwb: wlp: refactor wlp_get_() macros Refactor the wlp_get_() macros to call a common function. This save over 4k of space and remove a spurious uninitialized variable warning with some versions of gcc. Signed-off-by: David Vrabel --- drivers/uwb/wlp/messages.c | 106 ++++++++++++++++++++++++++------------------- 1 file changed, 61 insertions(+), 45 deletions(-) (limited to 'drivers') diff --git a/drivers/uwb/wlp/messages.c b/drivers/uwb/wlp/messages.c index aa42fcee4c4f..75164866c2d8 100644 --- a/drivers/uwb/wlp/messages.c +++ b/drivers/uwb/wlp/messages.c @@ -259,6 +259,63 @@ out: } +static ssize_t wlp_get_attribute(struct wlp *wlp, u16 type_code, + struct wlp_attr_hdr *attr_hdr, void *value, ssize_t value_len, + ssize_t buflen) +{ + struct device *dev = &wlp->rc->uwb_dev.dev; + ssize_t attr_len = sizeof(*attr_hdr) + value_len; + if (buflen < 0) + return -EINVAL; + if (buflen < attr_len) { + dev_err(dev, "WLP: Not enough space in buffer to parse" + " attribute field. Need %d, received %zu\n", + (int)attr_len, buflen); + return -EIO; + } + if (wlp_check_attr_hdr(wlp, attr_hdr, type_code, value_len) < 0) { + dev_err(dev, "WLP: Header verification failed. \n"); + return -EINVAL; + } + memcpy(value, (void *)attr_hdr + sizeof(*attr_hdr), value_len); + return attr_len; +} + +static ssize_t wlp_vget_attribute(struct wlp *wlp, u16 type_code, + struct wlp_attr_hdr *attr_hdr, void *value, ssize_t max_value_len, + ssize_t buflen) +{ + struct device *dev = &wlp->rc->uwb_dev.dev; + size_t len; + if (buflen < 0) + return -EINVAL; + if (buflen < sizeof(*attr_hdr)) { + dev_err(dev, "WLP: Not enough space in buffer to parse" + " header.\n"); + return -EIO; + } + if (le16_to_cpu(attr_hdr->type) != type_code) { + dev_err(dev, "WLP: Unexpected attribute type. Got %u, " + "expected %u.\n", le16_to_cpu(attr_hdr->type), + type_code); + return -EINVAL; + } + len = le16_to_cpu(attr_hdr->length); + if (len > max_value_len) { + dev_err(dev, "WLP: Attribute larger than maximum " + "allowed. Received %zu, max is %d.\n", len, + (int)max_value_len); + return -EFBIG; + } + if (buflen < sizeof(*attr_hdr) + len) { + dev_err(dev, "WLP: Not enough space in buffer to parse " + "variable data.\n"); + return -EIO; + } + memcpy(value, (void *)attr_hdr + sizeof(*attr_hdr), len); + return sizeof(*attr_hdr) + len; +} + /** * Get value of attribute from fixed size attribute field. * @@ -274,22 +331,8 @@ out: ssize_t wlp_get_##name(struct wlp *wlp, struct wlp_attr_##name *attr, \ type *value, ssize_t buflen) \ { \ - struct device *dev = &wlp->rc->uwb_dev.dev; \ - if (buflen < 0) \ - return -EINVAL; \ - if (buflen < sizeof(*attr)) { \ - dev_err(dev, "WLP: Not enough space in buffer to parse" \ - " attribute field. Need %d, received %zu\n", \ - (int)sizeof(*attr), buflen); \ - return -EIO; \ - } \ - if (wlp_check_attr_hdr(wlp, &attr->hdr, type_code, \ - sizeof(attr->name)) < 0) { \ - dev_err(dev, "WLP: Header verification failed. \n"); \ - return -EINVAL; \ - } \ - *value = attr->name; \ - return sizeof(*attr); \ + return wlp_get_attribute(wlp, (type_code), &attr->hdr, \ + value, sizeof(*value), buflen); \ } #define wlp_get_sparse(type, type_code, name) \ @@ -313,35 +356,8 @@ static ssize_t wlp_get_##name(struct wlp *wlp, \ struct wlp_attr_##name *attr, \ type_val *value, ssize_t buflen) \ { \ - struct device *dev = &wlp->rc->uwb_dev.dev; \ - size_t len; \ - if (buflen < 0) \ - return -EINVAL; \ - if (buflen < sizeof(*attr)) { \ - dev_err(dev, "WLP: Not enough space in buffer to parse" \ - " header.\n"); \ - return -EIO; \ - } \ - if (le16_to_cpu(attr->hdr.type) != type_code) { \ - dev_err(dev, "WLP: Unexpected attribute type. Got %u, " \ - "expected %u.\n", le16_to_cpu(attr->hdr.type), \ - type_code); \ - return -EINVAL; \ - } \ - len = le16_to_cpu(attr->hdr.length); \ - if (len > max) { \ - dev_err(dev, "WLP: Attribute larger than maximum " \ - "allowed. Received %zu, max is %d.\n", len, \ - (int)max); \ - return -EFBIG; \ - } \ - if (buflen < sizeof(*attr) + len) { \ - dev_err(dev, "WLP: Not enough space in buffer to parse "\ - "variable data.\n"); \ - return -EIO; \ - } \ - memcpy(value, (void *) attr + sizeof(*attr), len); \ - return sizeof(*attr) + len; \ + return wlp_vget_attribute(wlp, (type_code), &attr->hdr, \ + value, (max), buflen); \ } wlp_get(u8, WLP_ATTR_WLP_VER, version) -- cgit v1.2.3 From f75d4a238770d83d3a0475ce7f34e3fa37de161e Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Tue, 5 Jan 2010 07:07:27 +0000 Subject: icside: bring back ->maskproc method Bring back ->maskproc method since it is still needed for proper operation, as noticed by Russell King: > This change is bogus. > > writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1); > readb(base + ICS_ARCIN_V6_INTROFFSET_2); > > writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); > readb(base + ICS_ARCIN_V6_INTROFFSET_1); > > This sequence of code does: > > 1. enable interrupt 1 > 2. disable interrupt 2 > 3. enable interrupt 2 > 4. disable interrupt 1 > > which results in the interrupt for the second channel being enabled - > leaving channel 1 blocked. > > Firstly, icside shares its two IDE channels with one DMA engine - so it's > a simplex interface. IDE supports those (or did when the code was written) > serializing requests between the two interfaces. libata does not. > > Secondly, the interrupt lines on icside float when there's no drive connected > or when the drive has its NIEN bit set, which means that you get spurious > screaming interrupts which can kill off all expansion card interrupts on > the machine unless you disable the channel interrupt on the card. > > Since libata can not serialize the operation of the two channels like IDE > can, the libata version of the icside driver does not contain the interrupt > stearing logic. Instead, it looks at the status after reset, and if > nothing was found on that channel, it masks the interrupt from that > channel. This patch reverts changes done in commit dff8817 (I became confused due to non-standard & undocumented ->maskproc method, anyway sorry about that). Noticed-by: Russell King Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/icside.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 60 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/icside.c b/drivers/ide/icside.c index 0f67f1abbbd3..d7e6f09aa86b 100644 --- a/drivers/ide/icside.c +++ b/drivers/ide/icside.c @@ -65,6 +65,8 @@ static struct cardinfo icside_cardinfo_v6_2 = { }; struct icside_state { + unsigned int channel; + unsigned int enabled; void __iomem *irq_port; void __iomem *ioc_base; unsigned int sel; @@ -114,11 +116,18 @@ static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) struct icside_state *state = ec->irq_data; void __iomem *base = state->irq_port; - writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1); - readb(base + ICS_ARCIN_V6_INTROFFSET_2); + state->enabled = 1; - writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); - readb(base + ICS_ARCIN_V6_INTROFFSET_1); + switch (state->channel) { + case 0: + writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1); + readb(base + ICS_ARCIN_V6_INTROFFSET_2); + break; + case 1: + writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); + readb(base + ICS_ARCIN_V6_INTROFFSET_1); + break; + } } /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) @@ -128,6 +137,8 @@ static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) { struct icside_state *state = ec->irq_data; + state->enabled = 0; + readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); } @@ -149,6 +160,44 @@ static const expansioncard_ops_t icside_ops_arcin_v6 = { .irqpending = icside_irqpending_arcin_v6, }; +/* + * Handle routing of interrupts. This is called before + * we write the command to the drive. + */ +static void icside_maskproc(ide_drive_t *drive, int mask) +{ + ide_hwif_t *hwif = drive->hwif; + struct expansion_card *ec = ECARD_DEV(hwif->dev); + struct icside_state *state = ecard_get_drvdata(ec); + unsigned long flags; + + local_irq_save(flags); + + state->channel = hwif->channel; + + if (state->enabled && !mask) { + switch (hwif->channel) { + case 0: + writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); + readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); + break; + case 1: + writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); + readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); + break; + } + } else { + readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); + readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); + } + + local_irq_restore(flags); +} + +static const struct ide_port_ops icside_v6_no_dma_port_ops = { + .maskproc = icside_maskproc, +}; + #ifdef CONFIG_BLK_DEV_IDEDMA_ICS /* * SG-DMA support. @@ -228,6 +277,7 @@ static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode) static const struct ide_port_ops icside_v6_port_ops = { .set_dma_mode = icside_set_dma_mode, + .maskproc = icside_maskproc, }; static void icside_dma_host_set(ide_drive_t *drive, int on) @@ -271,6 +321,11 @@ static int icside_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) */ BUG_ON(dma_channel_active(ec->dma)); + /* + * Ensure that we have the right interrupt routed. + */ + icside_maskproc(drive, 0); + /* * Route the DMA signals to the correct interface. */ @@ -399,6 +454,7 @@ err_free: static const struct ide_port_info icside_v6_port_info __initdata = { .init_dma = icside_dma_off_init, + .port_ops = &icside_v6_no_dma_port_ops, .dma_ops = &icside_v6_dma_ops, .host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO, .mwdma_mask = ATA_MWDMA2, -- cgit v1.2.3 From c3be57b6f35ef96a980ce84e59d6a5a8ca6184ad Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 3 Jan 2010 12:35:42 +0000 Subject: ide: Fix Promise UDMA33 IDE driver (pdc202xx_old) On Sun, Jan 03, 2010 at 12:23:14AM +0000, Russell King wrote: > - with IDE > - locks the interrupt line, and makes the machine extremely painful - > about an hour to get to the point of being able to unload the > pdc202xx_old module. Having manually bisected kernel versions, I've narrowed it down to some change between 2.6.30 and 2.6.31. There's not much which has changed between the two kernels, but one change stands out like a sore thumb: +static int pdc202xx_test_irq(ide_hwif_t *hwif) +{ + struct pci_dev *dev = to_pci_dev(hwif->dev); + unsigned long high_16 = pci_resource_start(dev, 4); + u8 sc1d = inb(high_16 + 0x1d); + + if (hwif->channel) { + /* + * bit 7: error, bit 6: interrupting, + * bit 5: FIFO full, bit 4: FIFO empty + */ + return ((sc1d & 0x50) == 0x40) ? 1 : 0; + } else { + /* + * bit 3: error, bit 2: interrupting, + * bit 1: FIFO full, bit 0: FIFO empty + */ + return ((sc1d & 0x05) == 0x04) ? 1 : 0; + } +} Reading the (documented as a 32-bit) system control register when the interface is idle gives: 0x01da110c So, the byte at 0x1d is 0x11, which is documented as meaning that the primary and secondary FIFOs are empty. The code above, which is trying to see whether an IRQ is pending, checks for the IRQ bit to be one, and the FIFO bit to be zero - or in English, to be non-empty. Since during a BM-DMA read, the FIFOs will naturally be drained to the PCI bus, the chance of us getting to the interface before this happens are extremely small - and if we don't, it means we decide not to service the interrupt. Hence, the screaming interrupt problem with drivers/ide. Fix this by only indicating an interrupt is ready if both the interrupt and FIFO empty bits are at '1'. This bug only affects PDC20246/PDC20247 (Promise Ultra33) based cards, and has been tested on 2.6.31 and 2.6.33-rc2. Signed-off-by: Russell King Tested-by: Russell King Signed-off-by: David S. Miller --- drivers/ide/pdc202xx_old.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/pdc202xx_old.c b/drivers/ide/pdc202xx_old.c index 35161dd840a0..e3bca38a03f2 100644 --- a/drivers/ide/pdc202xx_old.c +++ b/drivers/ide/pdc202xx_old.c @@ -100,13 +100,13 @@ static int pdc202xx_test_irq(ide_hwif_t *hwif) * bit 7: error, bit 6: interrupting, * bit 5: FIFO full, bit 4: FIFO empty */ - return ((sc1d & 0x50) == 0x40) ? 1 : 0; + return ((sc1d & 0x50) == 0x50) ? 1 : 0; } else { /* * bit 3: error, bit 2: interrupting, * bit 1: FIFO full, bit 0: FIFO empty */ - return ((sc1d & 0x05) == 0x04) ? 1 : 0; + return ((sc1d & 0x05) == 0x05) ? 1 : 0; } } -- cgit v1.2.3 From 05227adff206c7290e8bbf1c28be771c2cbfa0ee Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 4 Jan 2010 06:24:00 +0000 Subject: ide_tape: kill off use of the ->ioctl operation Ready to get everything using unlocked_ioctl() For ide_tape we just push down as this is legacy code anyway Signed-off-by: Alan Cox Signed-off-by: David S. Miller --- drivers/ide/ide-tape.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/ide-tape.c b/drivers/ide/ide-tape.c index 6a0e62542167..b07232880ec9 100644 --- a/drivers/ide/ide-tape.c +++ b/drivers/ide/ide-tape.c @@ -1365,7 +1365,7 @@ static int idetape_mtioctop(ide_drive_t *drive, short mt_op, int mt_count) * supported here, and not in the corresponding block interface. Our own * ide-tape ioctls are supported on both interfaces. */ -static int idetape_chrdev_ioctl(struct inode *inode, struct file *file, +static long do_idetape_chrdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { struct ide_tape_obj *tape = file->private_data; @@ -1420,6 +1420,16 @@ static int idetape_chrdev_ioctl(struct inode *inode, struct file *file, } } +static long idetape_chrdev_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + long ret; + lock_kernel(); + ret = do_idetape_chrdev_ioctl(file, cmd, arg); + unlock_kernel(); + return ret; +} + /* * Do a mode sense page 0 with block descriptor and if it succeeds set the tape * block size with the reported value. @@ -1888,7 +1898,7 @@ static const struct file_operations idetape_fops = { .owner = THIS_MODULE, .read = idetape_chrdev_read, .write = idetape_chrdev_write, - .ioctl = idetape_chrdev_ioctl, + .unlocked_ioctl = idetape_chrdev_ioctl, .open = idetape_chrdev_open, .release = idetape_chrdev_release, }; -- cgit v1.2.3 From 0f1d683fb35d6c6f49ef696c95757f3970682a0e Mon Sep 17 00:00:00 2001 From: Naga Chumbalkar Date: Thu, 17 Dec 2009 20:18:27 +0000 Subject: [CPUFREQ] Processor Clocking Control interface driver Processor Clocking Control (PCC) is an interface between the BIOS and OSPM. Based on the server workload, OSPM can request what frequency it expects from a logical CPU, and the BIOS will achieve that frequency transparently. This patch introduces driver support for PCC. OSPM uses the PCC driver to communicate with the BIOS via the PCC interface. There is a Documentation file that provides a link to the PCC Specification, and also provides a summary of the PCC interface. Currently, certain HP ProLiant platforms implement the PCC interface. However, any platform whose BIOS implements the PCC Specification, can utilize this driver. V2 --> V1 changes (based on Dominik's suggestions): - Removed the dependency on CPU_FREQ_TABLE - "cpufreq_stats" will no longer PANIC. Actually, it will not load anymore because it is not applicable. - Removed the sanity check for target frequency in the ->target routine. NOTE: A patch to sanitize the target frequency requested by "ondemand" is needed to ensure that the target freq < policy->min. Can this driver be queued up for the 2.6.33 tree? Signed-off-by: Naga Chumbalkar Signed-off-by: Matthew Garrett Signed-off-by: Thomas Renninger Signed-off-by: Dave Jones --- Documentation/cpu-freq/pcc-cpufreq.txt | 207 ++++++++++ arch/x86/kernel/cpu/cpufreq/Kconfig | 14 + arch/x86/kernel/cpu/cpufreq/Makefile | 1 + arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c | 621 ++++++++++++++++++++++++++++++ drivers/acpi/processor_core.c | 2 + 5 files changed, 845 insertions(+) create mode 100644 Documentation/cpu-freq/pcc-cpufreq.txt create mode 100644 arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c (limited to 'drivers') diff --git a/Documentation/cpu-freq/pcc-cpufreq.txt b/Documentation/cpu-freq/pcc-cpufreq.txt new file mode 100644 index 000000000000..9e3c3b33514c --- /dev/null +++ b/Documentation/cpu-freq/pcc-cpufreq.txt @@ -0,0 +1,207 @@ +/* + * pcc-cpufreq.txt - PCC interface documentation + * + * Copyright (C) 2009 Red Hat, Matthew Garrett + * Copyright (C) 2009 Hewlett-Packard Development Company, L.P. + * Nagananda Chumbalkar + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or NON + * INFRINGEMENT. See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + */ + + + Processor Clocking Control Driver + --------------------------------- + +Contents: +--------- +1. Introduction +1.1 PCC interface +1.1.1 Get Average Frequency +1.1.2 Set Desired Frequency +1.2 Platforms affected +2. Driver and /sys details +2.1 scaling_available_frequencies +2.2 cpuinfo_transition_latency +2.3 cpuinfo_cur_freq +2.4 related_cpus +3. Caveats + +1. Introduction: +---------------- +Processor Clocking Control (PCC) is an interface between the platform +firmware and OSPM. It is a mechanism for coordinating processor +performance (ie: frequency) between the platform firmware and the OS. + +The PCC driver (pcc-cpufreq) allows OSPM to take advantage of the PCC +interface. + +OS utilizes the PCC interface to inform platform firmware what frequency the +OS wants for a logical processor. The platform firmware attempts to achieve +the requested frequency. If the request for the target frequency could not be +satisfied by platform firmware, then it usually means that power budget +conditions are in place, and "power capping" is taking place. + +1.1 PCC interface: +------------------ +The complete PCC specification is available here: +http://www.acpica.org/download/Processor-Clocking-Control-v1p0.pdf + +PCC relies on a shared memory region that provides a channel for communication +between the OS and platform firmware. PCC also implements a "doorbell" that +is used by the OS to inform the platform firmware that a command has been +sent. + +The ACPI PCCH() method is used to discover the location of the PCC shared +memory region. The shared memory region header contains the "command" and +"status" interface. PCCH() also contains details on how to access the platform +doorbell. + +The following commands are supported by the PCC interface: +* Get Average Frequency +* Set Desired Frequency + +The ACPI PCCP() method is implemented for each logical processor and is +used to discover the offsets for the input and output buffers in the shared +memory region. + +When PCC mode is enabled, the platform will not expose processor performance +or throttle states (_PSS, _TSS and related ACPI objects) to OSPM. Therefore, +the native P-state driver (such as acpi-cpufreq for Intel, powernow-k8 for +AMD) will not load. + +However, OSPM remains in control of policy. The governor (eg: "ondemand") +computes the required performance for each processor based on server workload. +The PCC driver fills in the command interface, and the input buffer and +communicates the request to the platform firmware. The platform firmware is +responsible for delivering the requested performance. + +Each PCC command is "global" in scope and can affect all the logical CPUs in +the system. Therefore, PCC is capable of performing "group" updates. With PCC +the OS is capable of getting/setting the frequency of all the logical CPUs in +the system with a single call to the BIOS. + +1.1.1 Get Average Frequency: +---------------------------- +This command is used by the OSPM to query the running frequency of the +processor since the last time this command was completed. The output buffer +indicates the average unhalted frequency of the logical processor expressed as +a percentage of the nominal (ie: maximum) CPU frequency. The output buffer +also signifies if the CPU frequency is limited by a power budget condition. + +1.1.2 Set Desired Frequency: +---------------------------- +This command is used by the OSPM to communicate to the platform firmware the +desired frequency for a logical processor. The output buffer is currently +ignored by OSPM. The next invocation of "Get Average Frequency" will inform +OSPM if the desired frequency was achieved or not. + +1.2 Platforms affected: +----------------------- +The PCC driver will load on any system where the platform firmware: +* supports the PCC interface, and the associated PCCH() and PCCP() methods +* assumes responsibility for managing the hardware clocking controls in order +to deliver the requested processor performance + +Currently, certain HP ProLiant platforms implement the PCC interface. On those +platforms PCC is the "default" choice. + +However, it is possible to disable this interface via a BIOS setting. In +such an instance, as is also the case on platforms where the PCC interface +is not implemented, the PCC driver will fail to load silently. + +2. Driver and /sys details: +--------------------------- +When the driver loads, it merely prints the lowest and the highest CPU +frequencies supported by the platform firmware. + +The PCC driver loads with a message such as: +pcc-cpufreq: (v1.00.00) driver loaded with frequency limits: 1600 MHz, 2933 +MHz + +This means that the OPSM can request the CPU to run at any frequency in +between the limits (1600 MHz, and 2933 MHz) specified in the message. + +Internally, there is no need for the driver to convert the "target" frequency +to a corresponding P-state. + +The VERSION number for the driver will be of the format v.xy.ab. +eg: 1.00.02 + ----- -- + | | + | -- this will increase with bug fixes/enhancements to the driver + |-- this is the version of the PCC specification the driver adheres to + + +The following is a brief discussion on some of the fields exported via the +/sys filesystem and how their values are affected by the PCC driver: + +2.1 scaling_available_frequencies: +---------------------------------- +scaling_available_frequencies is not created in /sys. No intermediate +frequencies need to be listed because the BIOS will try to achieve any +frequency, within limits, requested by the governor. A frequency does not have +to be strictly associated with a P-state. + +2.2 cpuinfo_transition_latency: +------------------------------- +The cpuinfo_transition_latency field is 0. The PCC specification does +not include a field to expose this value currently. + +2.3 cpuinfo_cur_freq: +--------------------- +A) Often cpuinfo_cur_freq will show a value different than what is declared +in the scaling_available_frequencies or scaling_cur_freq, or scaling_max_freq. +This is due to "turbo boost" available on recent Intel processors. If certain +conditions are met the BIOS can achieve a slightly higher speed than requested +by OSPM. An example: + +scaling_cur_freq : 2933000 +cpuinfo_cur_freq : 3196000 + +B) There is a round-off error associated with the cpuinfo_cur_freq value. +Since the driver obtains the current frequency as a "percentage" (%) of the +nominal frequency from the BIOS, sometimes, the values displayed by +scaling_cur_freq and cpuinfo_cur_freq may not match. An example: + +scaling_cur_freq : 1600000 +cpuinfo_cur_freq : 1583000 + +In this example, the nominal frequency is 2933 MHz. The driver obtains the +current frequency, cpuinfo_cur_freq, as 54% of the nominal frequency: + + 54% of 2933 MHz = 1583 MHz + +Nominal frequency is the maximum frequency of the processor, and it usually +corresponds to the frequency of the P0 P-state. + +2.4 related_cpus: +----------------- +The related_cpus field is identical to affected_cpus. + +affected_cpus : 4 +related_cpus : 4 + +Currently, the PCC driver does not evaluate _PSD. The platforms that support +PCC do not implement SW_ALL. So OSPM doesn't need to perform any coordination +to ensure that the same frequency is requested of all dependent CPUs. + +3. Caveats: +----------- +The "cpufreq_stats" module in its present form cannot be loaded and +expected to work with the PCC driver. Since the "cpufreq_stats" module +provides information wrt each P-state, it is not applicable to the PCC driver. diff --git a/arch/x86/kernel/cpu/cpufreq/Kconfig b/arch/x86/kernel/cpu/cpufreq/Kconfig index f138c6c389b9..870e6cc6ad28 100644 --- a/arch/x86/kernel/cpu/cpufreq/Kconfig +++ b/arch/x86/kernel/cpu/cpufreq/Kconfig @@ -10,6 +10,20 @@ if CPU_FREQ comment "CPUFreq processor drivers" +config X86_PCC_CPUFREQ + tristate "Processor Clocking Control interface driver" + depends on ACPI && ACPI_PROCESSOR + help + This driver adds support for the PCC interface. + + For details, take a look at: + . + + To compile this driver as a module, choose M here: the + module will be called pcc-cpufreq. + + If in doubt, say N. + config X86_ACPI_CPUFREQ tristate "ACPI Processor P-States driver" select CPU_FREQ_TABLE diff --git a/arch/x86/kernel/cpu/cpufreq/Makefile b/arch/x86/kernel/cpu/cpufreq/Makefile index 509296df294d..1840c0a5170b 100644 --- a/arch/x86/kernel/cpu/cpufreq/Makefile +++ b/arch/x86/kernel/cpu/cpufreq/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_X86_POWERNOW_K8) += powernow-k8.o obj-$(CONFIG_X86_ACPI_CPUFREQ) += acpi-cpufreq.o +obj-$(CONFIG_X86_PCC_CPUFREQ) += pcc-cpufreq.o obj-$(CONFIG_X86_POWERNOW_K6) += powernow-k6.o obj-$(CONFIG_X86_POWERNOW_K7) += powernow-k7.o obj-$(CONFIG_X86_LONGHAUL) += longhaul.o diff --git a/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c new file mode 100644 index 000000000000..29368854533c --- /dev/null +++ b/arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c @@ -0,0 +1,621 @@ +/* + * pcc-cpufreq.c - Processor Clocking Control firmware cpufreq interface + * + * Copyright (C) 2009 Red Hat, Matthew Garrett + * Copyright (C) 2009 Hewlett-Packard Development Company, L.P. + * Nagananda Chumbalkar + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or NON + * INFRINGEMENT. See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#define PCC_VERSION "1.00.00" +#define POLL_LOOPS 300 + +#define CMD_COMPLETE 0x1 +#define CMD_GET_FREQ 0x0 +#define CMD_SET_FREQ 0x1 + +#define BUF_SZ 4 + +#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \ + "pcc-cpufreq", msg) + +struct pcc_register_resource { + u8 descriptor; + u16 length; + u8 space_id; + u8 bit_width; + u8 bit_offset; + u8 access_size; + u64 address; +} __attribute__ ((packed)); + +struct pcc_memory_resource { + u8 descriptor; + u16 length; + u8 space_id; + u8 resource_usage; + u8 type_specific; + u64 granularity; + u64 minimum; + u64 maximum; + u64 translation_offset; + u64 address_length; +} __attribute__ ((packed)); + +static struct cpufreq_driver pcc_cpufreq_driver; + +struct pcc_header { + u32 signature; + u16 length; + u8 major; + u8 minor; + u32 features; + u16 command; + u16 status; + u32 latency; + u32 minimum_time; + u32 maximum_time; + u32 nominal; + u32 throttled_frequency; + u32 minimum_frequency; +}; + +static void __iomem *pcch_virt_addr; +static struct pcc_header __iomem *pcch_hdr; + +static DEFINE_SPINLOCK(pcc_lock); + +static struct acpi_generic_address doorbell; + +static u64 doorbell_preserve; +static u64 doorbell_write; + +static u8 OSC_UUID[16] = {0x63, 0x9B, 0x2C, 0x9F, 0x70, 0x91, 0x49, 0x1f, + 0xBB, 0x4F, 0xA5, 0x98, 0x2F, 0xA1, 0xB5, 0x46}; + +struct pcc_cpu { + u32 input_offset; + u32 output_offset; +}; + +static struct pcc_cpu *pcc_cpu_info; + +static int pcc_cpufreq_verify(struct cpufreq_policy *policy) +{ + cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, + policy->cpuinfo.max_freq); + return 0; +} + +static inline void pcc_cmd(void) +{ + u64 doorbell_value; + int i; + + acpi_read(&doorbell_value, &doorbell); + acpi_write((doorbell_value & doorbell_preserve) | doorbell_write, + &doorbell); + + for (i = 0; i < POLL_LOOPS; i++) { + if (ioread16(&pcch_hdr->status) & CMD_COMPLETE) + break; + } +} + +static inline void pcc_clear_mapping(void) +{ + if (pcch_virt_addr) + iounmap(pcch_virt_addr); + pcch_virt_addr = NULL; +} + +static unsigned int pcc_get_freq(unsigned int cpu) +{ + struct pcc_cpu *pcc_cpu_data; + unsigned int curr_freq; + unsigned int freq_limit; + u16 status; + u32 input_buffer; + u32 output_buffer; + + spin_lock(&pcc_lock); + + dprintk("get: get_freq for CPU %d\n", cpu); + pcc_cpu_data = per_cpu_ptr(pcc_cpu_info, cpu); + + input_buffer = 0x1; + iowrite32(input_buffer, + (pcch_virt_addr + pcc_cpu_data->input_offset)); + iowrite16(CMD_GET_FREQ, &pcch_hdr->command); + + pcc_cmd(); + + output_buffer = + ioread32(pcch_virt_addr + pcc_cpu_data->output_offset); + + /* Clear the input buffer - we are done with the current command */ + memset_io((pcch_virt_addr + pcc_cpu_data->input_offset), 0, BUF_SZ); + + status = ioread16(&pcch_hdr->status); + if (status != CMD_COMPLETE) { + dprintk("get: FAILED: for CPU %d, status is %d\n", + cpu, status); + goto cmd_incomplete; + } + iowrite16(0, &pcch_hdr->status); + curr_freq = (((ioread32(&pcch_hdr->nominal) * (output_buffer & 0xff)) + / 100) * 1000); + + dprintk("get: SUCCESS: (virtual) output_offset for cpu %d is " + "0x%x, contains a value of: 0x%x. Speed is: %d MHz\n", + cpu, (pcch_virt_addr + pcc_cpu_data->output_offset), + output_buffer, curr_freq); + + freq_limit = (output_buffer >> 8) & 0xff; + if (freq_limit != 0xff) { + dprintk("get: frequency for cpu %d is being temporarily" + " capped at %d\n", cpu, curr_freq); + } + + spin_unlock(&pcc_lock); + return curr_freq; + +cmd_incomplete: + iowrite16(0, &pcch_hdr->status); + spin_unlock(&pcc_lock); + return -EINVAL; +} + +static int pcc_cpufreq_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + struct pcc_cpu *pcc_cpu_data; + struct cpufreq_freqs freqs; + u16 status; + u32 input_buffer; + int cpu; + + spin_lock(&pcc_lock); + cpu = policy->cpu; + pcc_cpu_data = per_cpu_ptr(pcc_cpu_info, cpu); + + dprintk("target: CPU %d should go to target freq: %d " + "(virtual) input_offset is 0x%x\n", + cpu, target_freq, + (pcch_virt_addr + pcc_cpu_data->input_offset)); + + freqs.new = target_freq; + freqs.cpu = cpu; + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + input_buffer = 0x1 | (((target_freq * 100) + / (ioread32(&pcch_hdr->nominal) * 1000)) << 8); + iowrite32(input_buffer, + (pcch_virt_addr + pcc_cpu_data->input_offset)); + iowrite16(CMD_SET_FREQ, &pcch_hdr->command); + + pcc_cmd(); + + /* Clear the input buffer - we are done with the current command */ + memset_io((pcch_virt_addr + pcc_cpu_data->input_offset), 0, BUF_SZ); + + status = ioread16(&pcch_hdr->status); + if (status != CMD_COMPLETE) { + dprintk("target: FAILED for cpu %d, with status: 0x%x\n", + cpu, status); + goto cmd_incomplete; + } + iowrite16(0, &pcch_hdr->status); + + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + dprintk("target: was SUCCESSFUL for cpu %d\n", cpu); + spin_unlock(&pcc_lock); + + return 0; + +cmd_incomplete: + iowrite16(0, &pcch_hdr->status); + spin_unlock(&pcc_lock); + return -EINVAL; +} + +static int pcc_get_offset(int cpu) +{ + acpi_status status; + struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; + union acpi_object *pccp, *offset; + struct pcc_cpu *pcc_cpu_data; + struct acpi_processor *pr; + int ret = 0; + + pr = per_cpu(processors, cpu); + pcc_cpu_data = per_cpu_ptr(pcc_cpu_info, cpu); + + status = acpi_evaluate_object(pr->handle, "PCCP", NULL, &buffer); + if (ACPI_FAILURE(status)) + return -ENODEV; + + pccp = buffer.pointer; + if (!pccp || pccp->type != ACPI_TYPE_PACKAGE) { + ret = -ENODEV; + goto out_free; + }; + + offset = &(pccp->package.elements[0]); + if (!offset || offset->type != ACPI_TYPE_INTEGER) { + ret = -ENODEV; + goto out_free; + } + + pcc_cpu_data->input_offset = offset->integer.value; + + offset = &(pccp->package.elements[1]); + if (!offset || offset->type != ACPI_TYPE_INTEGER) { + ret = -ENODEV; + goto out_free; + } + + pcc_cpu_data->output_offset = offset->integer.value; + + memset_io((pcch_virt_addr + pcc_cpu_data->input_offset), 0, BUF_SZ); + memset_io((pcch_virt_addr + pcc_cpu_data->output_offset), 0, BUF_SZ); + + dprintk("pcc_get_offset: for CPU %d: pcc_cpu_data " + "input_offset: 0x%x, pcc_cpu_data output_offset: 0x%x\n", + cpu, pcc_cpu_data->input_offset, pcc_cpu_data->output_offset); +out_free: + kfree(buffer.pointer); + return ret; +} + +static int __init pcc_cpufreq_do_osc(acpi_handle *handle) +{ + acpi_status status; + struct acpi_object_list input; + struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; + union acpi_object in_params[4]; + union acpi_object *out_obj; + u32 capabilities[2]; + u32 errors; + u32 supported; + int ret = 0; + + input.count = 4; + input.pointer = in_params; + input.count = 4; + input.pointer = in_params; + in_params[0].type = ACPI_TYPE_BUFFER; + in_params[0].buffer.length = 16; + in_params[0].buffer.pointer = OSC_UUID; + in_params[1].type = ACPI_TYPE_INTEGER; + in_params[1].integer.value = 1; + in_params[2].type = ACPI_TYPE_INTEGER; + in_params[2].integer.value = 2; + in_params[3].type = ACPI_TYPE_BUFFER; + in_params[3].buffer.length = 8; + in_params[3].buffer.pointer = (u8 *)&capabilities; + + capabilities[0] = OSC_QUERY_ENABLE; + capabilities[1] = 0x1; + + status = acpi_evaluate_object(*handle, "_OSC", &input, &output); + if (ACPI_FAILURE(status)) + return -ENODEV; + + if (!output.length) + return -ENODEV; + + out_obj = output.pointer; + if (out_obj->type != ACPI_TYPE_BUFFER) { + ret = -ENODEV; + goto out_free; + } + + errors = *((u32 *)out_obj->buffer.pointer) & ~(1 << 0); + if (errors) { + ret = -ENODEV; + goto out_free; + } + + supported = *((u32 *)(out_obj->buffer.pointer + 4)); + if (!(supported & 0x1)) { + ret = -ENODEV; + goto out_free; + } + + kfree(output.pointer); + capabilities[0] = 0x0; + capabilities[1] = 0x1; + + status = acpi_evaluate_object(*handle, "_OSC", &input, &output); + if (ACPI_FAILURE(status)) + return -ENODEV; + + if (!output.length) + return -ENODEV; + + out_obj = output.pointer; + if (out_obj->type != ACPI_TYPE_BUFFER) { + ret = -ENODEV; + goto out_free; + } + + errors = *((u32 *)out_obj->buffer.pointer) & ~(1 << 0); + if (errors) { + ret = -ENODEV; + goto out_free; + } + + supported = *((u32 *)(out_obj->buffer.pointer + 4)); + if (!(supported & 0x1)) { + ret = -ENODEV; + goto out_free; + } + +out_free: + kfree(output.pointer); + return ret; +} + +static int __init pcc_cpufreq_probe(void) +{ + acpi_status status; + struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; + struct pcc_memory_resource *mem_resource; + struct pcc_register_resource *reg_resource; + union acpi_object *out_obj, *member; + acpi_handle handle, osc_handle; + int ret = 0; + + status = acpi_get_handle(NULL, "\\_SB", &handle); + if (ACPI_FAILURE(status)) + return -ENODEV; + + status = acpi_get_handle(handle, "_OSC", &osc_handle); + if (ACPI_SUCCESS(status)) { + ret = pcc_cpufreq_do_osc(&osc_handle); + if (ret) + dprintk("probe: _OSC evaluation did not succeed\n"); + /* Firmware's use of _OSC is optional */ + ret = 0; + } + + status = acpi_evaluate_object(handle, "PCCH", NULL, &output); + if (ACPI_FAILURE(status)) + return -ENODEV; + + out_obj = output.pointer; + if (out_obj->type != ACPI_TYPE_PACKAGE) { + ret = -ENODEV; + goto out_free; + } + + member = &out_obj->package.elements[0]; + if (member->type != ACPI_TYPE_BUFFER) { + ret = -ENODEV; + goto out_free; + } + + mem_resource = (struct pcc_memory_resource *)member->buffer.pointer; + + dprintk("probe: mem_resource descriptor: 0x%x," + " length: %d, space_id: %d, resource_usage: %d," + " type_specific: %d, granularity: 0x%llx," + " minimum: 0x%llx, maximum: 0x%llx," + " translation_offset: 0x%llx, address_length: 0x%llx\n", + mem_resource->descriptor, mem_resource->length, + mem_resource->space_id, mem_resource->resource_usage, + mem_resource->type_specific, mem_resource->granularity, + mem_resource->minimum, mem_resource->maximum, + mem_resource->translation_offset, + mem_resource->address_length); + + if (mem_resource->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) { + ret = -ENODEV; + goto out_free; + } + + pcch_virt_addr = ioremap_nocache(mem_resource->minimum, + mem_resource->address_length); + if (pcch_virt_addr == NULL) { + dprintk("probe: could not map shared mem region\n"); + goto out_free; + } + pcch_hdr = pcch_virt_addr; + + dprintk("probe: PCCH header (virtual) addr: 0x%llx\n", + (u64)pcch_hdr); + dprintk("probe: PCCH header is at physical address: 0x%llx," + " signature: 0x%x, length: %d bytes, major: %d, minor: %d," + " supported features: 0x%x, command field: 0x%x," + " status field: 0x%x, nominal latency: %d us\n", + mem_resource->minimum, ioread32(&pcch_hdr->signature), + ioread16(&pcch_hdr->length), ioread8(&pcch_hdr->major), + ioread8(&pcch_hdr->minor), ioread32(&pcch_hdr->features), + ioread16(&pcch_hdr->command), ioread16(&pcch_hdr->status), + ioread32(&pcch_hdr->latency)); + + dprintk("probe: min time between commands: %d us," + " max time between commands: %d us," + " nominal CPU frequency: %d MHz," + " minimum CPU frequency: %d MHz," + " minimum CPU frequency without throttling: %d MHz\n", + ioread32(&pcch_hdr->minimum_time), + ioread32(&pcch_hdr->maximum_time), + ioread32(&pcch_hdr->nominal), + ioread32(&pcch_hdr->throttled_frequency), + ioread32(&pcch_hdr->minimum_frequency)); + + member = &out_obj->package.elements[1]; + if (member->type != ACPI_TYPE_BUFFER) { + ret = -ENODEV; + goto pcch_free; + } + + reg_resource = (struct pcc_register_resource *)member->buffer.pointer; + + doorbell.space_id = reg_resource->space_id; + doorbell.bit_width = reg_resource->bit_width; + doorbell.bit_offset = reg_resource->bit_offset; + doorbell.access_width = 64; + doorbell.address = reg_resource->address; + + dprintk("probe: doorbell: space_id is %d, bit_width is %d, " + "bit_offset is %d, access_width is %d, address is 0x%llx\n", + doorbell.space_id, doorbell.bit_width, doorbell.bit_offset, + doorbell.access_width, reg_resource->address); + + member = &out_obj->package.elements[2]; + if (member->type != ACPI_TYPE_INTEGER) { + ret = -ENODEV; + goto pcch_free; + } + + doorbell_preserve = member->integer.value; + + member = &out_obj->package.elements[3]; + if (member->type != ACPI_TYPE_INTEGER) { + ret = -ENODEV; + goto pcch_free; + } + + doorbell_write = member->integer.value; + + dprintk("probe: doorbell_preserve: 0x%llx," + " doorbell_write: 0x%llx\n", + doorbell_preserve, doorbell_write); + + pcc_cpu_info = alloc_percpu(struct pcc_cpu); + if (!pcc_cpu_info) { + ret = -ENOMEM; + goto pcch_free; + } + + printk(KERN_DEBUG "pcc-cpufreq: (v%s) driver loaded with frequency" + " limits: %d MHz, %d MHz\n", PCC_VERSION, + ioread32(&pcch_hdr->minimum_frequency), + ioread32(&pcch_hdr->nominal)); + kfree(output.pointer); + return ret; +pcch_free: + pcc_clear_mapping(); +out_free: + kfree(output.pointer); + return ret; +} + +static int pcc_cpufreq_cpu_init(struct cpufreq_policy *policy) +{ + unsigned int cpu = policy->cpu; + unsigned int result = 0; + + if (!pcch_virt_addr) { + result = -1; + goto pcch_null; + } + + result = pcc_get_offset(cpu); + if (result) { + dprintk("init: PCCP evaluation failed\n"); + goto free; + } + + policy->max = policy->cpuinfo.max_freq = + ioread32(&pcch_hdr->nominal) * 1000; + policy->min = policy->cpuinfo.min_freq = + ioread32(&pcch_hdr->minimum_frequency) * 1000; + policy->cur = pcc_get_freq(cpu); + + dprintk("init: policy->max is %d, policy->min is %d\n", + policy->max, policy->min); + + return 0; +free: + pcc_clear_mapping(); + free_percpu(pcc_cpu_info); +pcch_null: + return result; +} + +static int pcc_cpufreq_cpu_exit(struct cpufreq_policy *policy) +{ + return 0; +} + +static struct cpufreq_driver pcc_cpufreq_driver = { + .flags = CPUFREQ_CONST_LOOPS, + .get = pcc_get_freq, + .verify = pcc_cpufreq_verify, + .target = pcc_cpufreq_target, + .init = pcc_cpufreq_cpu_init, + .exit = pcc_cpufreq_cpu_exit, + .name = "pcc-cpufreq", + .owner = THIS_MODULE, +}; + +static int __init pcc_cpufreq_init(void) +{ + int ret; + + if (acpi_disabled) + return 0; + + ret = pcc_cpufreq_probe(); + if (ret) { + dprintk("pcc_cpufreq_init: PCCH evaluation failed\n"); + return ret; + } + + ret = cpufreq_register_driver(&pcc_cpufreq_driver); + + return ret; +} + +static void __exit pcc_cpufreq_exit(void) +{ + cpufreq_unregister_driver(&pcc_cpufreq_driver); + + pcc_clear_mapping(); + + free_percpu(pcc_cpu_info); +} + +MODULE_AUTHOR("Matthew Garrett, Naga Chumbalkar"); +MODULE_VERSION(PCC_VERSION); +MODULE_DESCRIPTION("Processor Clocking Control interface driver"); +MODULE_LICENSE("GPL"); + +late_initcall(pcc_cpufreq_init); +module_exit(pcc_cpufreq_exit); diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 41731236f9a1..7fe413cc7d99 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -123,6 +123,8 @@ static const struct file_operations acpi_processor_info_fops = { #endif DEFINE_PER_CPU(struct acpi_processor *, processors); +EXPORT_PER_CPU_SYMBOL(processors); + struct acpi_processor_errata errata __read_mostly; static int set_no_mwait(const struct dmi_system_id *id) { -- cgit v1.2.3 From b6d0c1bda9038354ff2f0c77da23fd32e0f11a1f Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 14 Jan 2010 11:24:13 +0200 Subject: mtd: mxc_nand: add MX25 to Kconfig Signed-off-by: Baruch Siach Signed-off-by: Sascha Hauer --- drivers/mtd/nand/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 677cd53f18c3..4f99274b24c2 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -444,7 +444,7 @@ config MTD_NAND_FSL_UPM config MTD_NAND_MXC tristate "MXC NAND support" - depends on ARCH_MX2 || ARCH_MX3 + depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 help This enables the driver for the NAND flash controller on the MXC processors. -- cgit v1.2.3 From 34446d05dd255b34518c76d2b8760161e63fe0c1 Mon Sep 17 00:00:00 2001 From: Márton Németh Date: Tue, 12 Jan 2010 08:49:14 +0100 Subject: uwb: make USB device id table constant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The id_table field of the struct usb_device_id is constant in so it is worth to make the initialization data also constant. Signed-off-by: Márton Németh Signed-off-by: David Vrabel --- drivers/uwb/hwa-rc.c | 2 +- drivers/uwb/i1480/dfu/usb.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/uwb/hwa-rc.c b/drivers/uwb/hwa-rc.c index e7eeb63fab23..b409c228f254 100644 --- a/drivers/uwb/hwa-rc.c +++ b/drivers/uwb/hwa-rc.c @@ -891,7 +891,7 @@ static int hwarc_post_reset(struct usb_interface *iface) } /** USB device ID's that we handle */ -static struct usb_device_id hwarc_id_table[] = { +static const struct usb_device_id hwarc_id_table[] = { /* D-Link DUB-1210 */ { USB_DEVICE_AND_INTERFACE_INFO(0x07d1, 0x3d02, 0xe0, 0x01, 0x02), .driver_info = WUSB_QUIRK_WHCI_CMD_EVT }, diff --git a/drivers/uwb/i1480/dfu/usb.c b/drivers/uwb/i1480/dfu/usb.c index 0bb665a0c024..08f9a7b95c42 100644 --- a/drivers/uwb/i1480/dfu/usb.c +++ b/drivers/uwb/i1480/dfu/usb.c @@ -430,7 +430,7 @@ error: /** USB device ID's that we handle */ -static struct usb_device_id i1480_usb_id_table[] = { +static const struct usb_device_id i1480_usb_id_table[] = { i1480_USB_DEV(0x8086, 0xdf3b), i1480_USB_DEV(0x15a9, 0x0005), i1480_USB_DEV(0x07d1, 0x3802), -- cgit v1.2.3 From 35fb2a816a06ded2a3ff83d896c34b83c8e1d556 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Wed, 13 Jan 2010 23:41:50 +0000 Subject: uwb: declare MODULE_FIRMWARE() in i1480 DFU driver Signed-off-by: Ben Hutchings Signed-off-by: David Vrabel --- drivers/uwb/i1480/dfu/usb.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/uwb/i1480/dfu/usb.c b/drivers/uwb/i1480/dfu/usb.c index 08f9a7b95c42..a6a93755627e 100644 --- a/drivers/uwb/i1480/dfu/usb.c +++ b/drivers/uwb/i1480/dfu/usb.c @@ -413,6 +413,10 @@ error: return result; } +MODULE_FIRMWARE("i1480-pre-phy-0.0.bin"); +MODULE_FIRMWARE("i1480-usb-0.0.bin"); +MODULE_FIRMWARE("i1480-phy-0.0.bin"); + #define i1480_USB_DEV(v, p) \ { \ .match_flags = USB_DEVICE_ID_MATCH_DEVICE \ -- cgit v1.2.3 From d4ae5415c6f2dd8f14e027c24f09d708f11a8d60 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 15 Jan 2010 01:33:08 -0800 Subject: ide/ide-cs: fix order of releasing resources ide_detach() called first ide_release() and then release_region(). This produced the following warnings: Trying to free nonexistent resource <000000000000c10e-000000000000c10e> Trying to free nonexistent resource <000000000000c100-000000000000c107> This is true, because the callchain inside ide_release() is: ide_release -> pcmcia_disable_device -> pcmcia_release_io So, the whole io-block is already gone for release_region(). To fix this, just swap the order of releasing (and remove the now obsolete shadowing). bzolnier: - release resources in ide_release() to fix ordering of events - remove stale FIXME note while at it Signed-off-by: Wolfram Sang Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/ide-cs.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/ide-cs.c b/drivers/ide/ide-cs.c index dd6396384c25..ab87e4f7cec9 100644 --- a/drivers/ide/ide-cs.c +++ b/drivers/ide/ide-cs.c @@ -121,19 +121,11 @@ static int ide_probe(struct pcmcia_device *link) static void ide_detach(struct pcmcia_device *link) { ide_info_t *info = link->priv; - ide_hwif_t *hwif = info->host->ports[0]; - unsigned long data_addr, ctl_addr; dev_dbg(&link->dev, "ide_detach(0x%p)\n", link); - data_addr = hwif->io_ports.data_addr; - ctl_addr = hwif->io_ports.ctl_addr; - ide_release(link); - release_region(ctl_addr, 1); - release_region(data_addr, 8); - kfree(info); } /* ide_detach */ @@ -354,12 +346,19 @@ static void ide_release(struct pcmcia_device *link) dev_dbg(&link->dev, "ide_release(0x%p)\n", link); - if (info->ndev) - /* FIXME: if this fails we need to queue the cleanup somehow - -- need to investigate the required PCMCIA magic */ + if (info->ndev) { + ide_hwif_t *hwif = host->ports[0]; + unsigned long data_addr, ctl_addr; + + data_addr = hwif->io_ports.data_addr; + ctl_addr = hwif->io_ports.ctl_addr; + ide_host_remove(host); + info->ndev = 0; - info->ndev = 0; + release_region(ctl_addr, 1); + release_region(data_addr, 8); + } pcmcia_disable_device(link); } /* ide_release */ -- cgit v1.2.3 From 501dae90b3ae4dd3d8efdacfcb072c3d65eb5a33 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 14 Jan 2010 08:23:53 +0900 Subject: ARM: S5P6440: Add serial port support This patch adds UART serial port support for S5P6440 CPU. Most of the serial support of Samsung's 6400 CPU is reused for 6440 CPU. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/devs.h | 1 + arch/arm/plat-s5p/dev-uart.c | 165 ++++++++++++++++++++++++++++++++++ drivers/serial/Kconfig | 8 +- 3 files changed, 170 insertions(+), 4 deletions(-) create mode 100644 arch/arm/plat-s5p/dev-uart.c (limited to 'drivers') diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index c1c20b023917..8a4153b49f40 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -18,6 +18,7 @@ struct s3c24xx_uart_resources { extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; +extern struct s3c24xx_uart_resources s5p_uart_resources[]; extern struct platform_device *s3c24xx_uart_devs[]; extern struct platform_device *s3c24xx_uart_src[]; diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c new file mode 100644 index 000000000000..af726f47385e --- /dev/null +++ b/arch/arm/plat-s5p/dev-uart.c @@ -0,0 +1,165 @@ +/* linux/arch/arm/plat-s5p/dev-uart.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base S5P UART resource and device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + + /* Serial port registrations */ + +static struct resource s5p_uart0_resource[] = { + [0] = { + .start = S5P_PA_UART0, + .end = S5P_PA_UART0 + S5P_SZ_UART, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S5P_UART_RX0, + .end = IRQ_S5P_UART_RX0, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S5P_UART_TX0, + .end = IRQ_S5P_UART_TX0, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_S5P_UART_ERR0, + .end = IRQ_S5P_UART_ERR0, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource s5p_uart1_resource[] = { + [0] = { + .start = S5P_PA_UART1, + .end = S5P_PA_UART1 + S5P_SZ_UART, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S5P_UART_RX1, + .end = IRQ_S5P_UART_RX1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S5P_UART_TX1, + .end = IRQ_S5P_UART_TX1, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_S5P_UART_ERR1, + .end = IRQ_S5P_UART_ERR1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource s5p_uart2_resource[] = { + [0] = { + .start = S5P_PA_UART2, + .end = S5P_PA_UART2 + S5P_SZ_UART, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S5P_UART_RX2, + .end = IRQ_S5P_UART_RX2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S5P_UART_TX2, + .end = IRQ_S5P_UART_TX2, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_S5P_UART_ERR2, + .end = IRQ_S5P_UART_ERR2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource s5p_uart3_resource[] = { + [0] = { + .start = S5P_PA_UART3, + .end = S5P_PA_UART3 + S5P_SZ_UART, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S5P_UART_RX3, + .end = IRQ_S5P_UART_RX3, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S5P_UART_TX3, + .end = IRQ_S5P_UART_TX3, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_S5P_UART_ERR3, + .end = IRQ_S5P_UART_ERR3, + .flags = IORESOURCE_IRQ, + }, +}; + +struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = { + [0] = { + .resources = s5p_uart0_resource, + .nr_resources = ARRAY_SIZE(s5p_uart0_resource), + }, + [1] = { + .resources = s5p_uart1_resource, + .nr_resources = ARRAY_SIZE(s5p_uart1_resource), + }, + [2] = { + .resources = s5p_uart2_resource, + .nr_resources = ARRAY_SIZE(s5p_uart2_resource), + }, + [3] = { + .resources = s5p_uart3_resource, + .nr_resources = ARRAY_SIZE(s5p_uart3_resource), + }, +}; + +/* uart devices */ + +static struct platform_device s5p_uart_device0 = { + .id = 0, +}; + +static struct platform_device s5p_uart_device1 = { + .id = 1, +}; + +static struct platform_device s5p_uart_device2 = { + .id = 2, +}; + +static struct platform_device s5p_uart_device3 = { + .id = 3, +}; + +struct platform_device *s3c24xx_uart_src[4] = { + &s5p_uart_device0, + &s5p_uart_device1, + &s5p_uart_device2, + &s5p_uart_device3, +}; + +struct platform_device *s3c24xx_uart_devs[4] = { +}; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 9ff47db0b2ce..d7d687f0d201 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -459,7 +459,7 @@ config SERIAL_SAMSUNG_UARTS int depends on ARM && PLAT_S3C default 2 if ARCH_S3C2400 - default 4 if ARCH_S5PC1XX || ARCH_S3C64XX || CPU_S3C2443 + default 4 if ARCH_S5P6440 || ARCH_S5PC1XX || ARCH_S3C64XX || CPU_S3C2443 default 3 help Select the number of available UART ports for the Samsung S3C @@ -526,11 +526,11 @@ config SERIAL_S3C24A0 Serial port support for the Samsung S3C24A0 SoC config SERIAL_S3C6400 - tristate "Samsung S3C6400/S3C6410 Serial port support" - depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410) + tristate "Samsung S3C6400/S3C6410/S5P6440 Serial port support" + depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410 || CPU_S5P6440) default y help - Serial port support for the Samsung S3C6400 and S3C6410 + Serial port support for the Samsung S3C6400, S3C6410 and S5P6440 SoCs config SERIAL_S5PC100 -- cgit v1.2.3 From 7b3bcc4a1a7cd2d53b403ca29d06ceb5fa617eb7 Mon Sep 17 00:00:00 2001 From: Alexey Starikovskiy Date: Thu, 15 Oct 2009 14:31:24 +0400 Subject: ACPI: Battery: Add bit flags Signed-off-by: Alexey Starikovskiy Signed-off-by: Len Brown --- drivers/acpi/battery.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c index cada73ffdfa7..b2b48f8545c7 100644 --- a/drivers/acpi/battery.c +++ b/drivers/acpi/battery.c @@ -88,10 +88,13 @@ static const struct acpi_device_id battery_device_ids[] = { MODULE_DEVICE_TABLE(acpi, battery_device_ids); -/* For buggy DSDTs that report negative 16-bit values for either charging - * or discharging current and/or report 0 as 65536 due to bad math. - */ -#define QUIRK_SIGNED16_CURRENT 0x0001 +enum { + ACPI_BATTERY_ALARM_PRESENT, + /* For buggy DSDTs that report negative 16-bit values for either charging + * or discharging current and/or report 0 as 65536 due to bad math. + */ + ACPI_BATTERY_QUIRK_SIGNED16_CURRENT, +}; struct acpi_battery { struct mutex lock; @@ -118,8 +121,7 @@ struct acpi_battery { char oem_info[32]; int state; int power_unit; - u8 alarm_present; - long quirks; + unsigned long flags; }; #define to_acpi_battery(x) container_of(x, struct acpi_battery, bat); @@ -399,7 +401,7 @@ static int acpi_battery_get_state(struct acpi_battery *battery) battery->update_time = jiffies; kfree(buffer.pointer); - if ((battery->quirks & QUIRK_SIGNED16_CURRENT) && + if (test_bit(ACPI_BATTERY_QUIRK_SIGNED16_CURRENT, &battery->flags) && battery->rate_now != -1) battery->rate_now = abs((s16)battery->rate_now); @@ -412,7 +414,8 @@ static int acpi_battery_set_alarm(struct acpi_battery *battery) union acpi_object arg0 = { .type = ACPI_TYPE_INTEGER }; struct acpi_object_list arg_list = { 1, &arg0 }; - if (!acpi_battery_present(battery)|| !battery->alarm_present) + if (!acpi_battery_present(battery)|| + !test_bit(ACPI_BATTERY_ALARM_PRESENT, &battery->flags)) return -ENODEV; arg0.integer.value = battery->alarm; @@ -437,10 +440,10 @@ static int acpi_battery_init_alarm(struct acpi_battery *battery) /* See if alarms are supported, and if so, set default */ status = acpi_get_handle(battery->device->handle, "_BTP", &handle); if (ACPI_FAILURE(status)) { - battery->alarm_present = 0; + clear_bit(ACPI_BATTERY_ALARM_PRESENT, &battery->flags); return 0; } - battery->alarm_present = 1; + set_bit(ACPI_BATTERY_ALARM_PRESENT, &battery->flags); if (!battery->alarm) battery->alarm = battery->design_capacity_warning; return acpi_battery_set_alarm(battery); @@ -510,9 +513,8 @@ static void sysfs_remove_battery(struct acpi_battery *battery) static void acpi_battery_quirks(struct acpi_battery *battery) { - battery->quirks = 0; if (dmi_name_in_vendors("Acer") && battery->power_unit) { - battery->quirks |= QUIRK_SIGNED16_CURRENT; + set_bit(ACPI_BATTERY_QUIRK_SIGNED16_CURRENT, &battery->flags); } } -- cgit v1.2.3 From c955fe8e0bdd7be7a6bc2d49245d570a816f7cc5 Mon Sep 17 00:00:00 2001 From: Alexey Starikovskiy Date: Thu, 15 Oct 2009 14:31:30 +0400 Subject: POWER: Add support for cycle_count Signed-off-by: Alexey Starikovskiy Signed-off-by: Len Brown --- drivers/power/power_supply_sysfs.c | 1 + include/linux/power_supply.h | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/power/power_supply_sysfs.c b/drivers/power/power_supply_sysfs.c index c790e0c77d4b..ff05e6189768 100644 --- a/drivers/power/power_supply_sysfs.c +++ b/drivers/power/power_supply_sysfs.c @@ -99,6 +99,7 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(present), POWER_SUPPLY_ATTR(online), POWER_SUPPLY_ATTR(technology), + POWER_SUPPLY_ATTR(cycle_count), POWER_SUPPLY_ATTR(voltage_max), POWER_SUPPLY_ATTR(voltage_min), POWER_SUPPLY_ATTR(voltage_max_design), diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index b5d096d3a9be..ebd2b8fb00d0 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -82,6 +82,7 @@ enum power_supply_property { POWER_SUPPLY_PROP_PRESENT, POWER_SUPPLY_PROP_ONLINE, POWER_SUPPLY_PROP_TECHNOLOGY, + POWER_SUPPLY_PROP_CYCLE_COUNT, POWER_SUPPLY_PROP_VOLTAGE_MAX, POWER_SUPPLY_PROP_VOLTAGE_MIN, POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, -- cgit v1.2.3 From 16698857fba1b10af4890055272975adf5686e83 Mon Sep 17 00:00:00 2001 From: Alexey Starikovskiy Date: Thu, 15 Oct 2009 14:31:37 +0400 Subject: ACPI: SBS: Export cycle_count Signed-off-by: Alexey Starikovskiy Signed-off-by: Len Brown --- drivers/acpi/sbs.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/acpi/sbs.c b/drivers/acpi/sbs.c index 52b9db8afc20..38412ec2332d 100644 --- a/drivers/acpi/sbs.c +++ b/drivers/acpi/sbs.c @@ -217,6 +217,9 @@ static int acpi_sbs_battery_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_TECHNOLOGY: val->intval = acpi_battery_technology(battery); break; + case POWER_SUPPLY_PROP_CYCLE_COUNT: + val->intval = battery->cycle_count; + break; case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: val->intval = battery->design_voltage * acpi_battery_vscale(battery) * 1000; @@ -276,6 +279,7 @@ static enum power_supply_property sbs_charge_battery_props[] = { POWER_SUPPLY_PROP_STATUS, POWER_SUPPLY_PROP_PRESENT, POWER_SUPPLY_PROP_TECHNOLOGY, + POWER_SUPPLY_PROP_CYCLE_COUNT, POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, POWER_SUPPLY_PROP_VOLTAGE_NOW, POWER_SUPPLY_PROP_CURRENT_NOW, @@ -560,6 +564,7 @@ static int acpi_battery_read_info(struct seq_file *seq, void *offset) battery->design_voltage * acpi_battery_vscale(battery)); seq_printf(seq, "design capacity warning: unknown\n"); seq_printf(seq, "design capacity low: unknown\n"); + seq_printf(seq, "cycle count: %i\n", battery->cycle_count); seq_printf(seq, "capacity granularity 1: unknown\n"); seq_printf(seq, "capacity granularity 2: unknown\n"); seq_printf(seq, "model number: %s\n", battery->device_name); -- cgit v1.2.3 From c67fcd670b55e89e0c129fbf7fae854bd1f8bfa6 Mon Sep 17 00:00:00 2001 From: Alexey Starikovskiy Date: Thu, 15 Oct 2009 14:31:44 +0400 Subject: ACPI: Battery: Add support for _BIX extended info method Signed-off-by: Alexey Starikovskiy Signed-off-by: Len Brown --- drivers/acpi/battery.c | 68 ++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 58 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c index b2b48f8545c7..1ca0ea77115b 100644 --- a/drivers/acpi/battery.c +++ b/drivers/acpi/battery.c @@ -54,6 +54,7 @@ #define ACPI_BATTERY_DEVICE_NAME "Battery" #define ACPI_BATTERY_NOTIFY_STATUS 0x80 #define ACPI_BATTERY_NOTIFY_INFO 0x81 +#define ACPI_BATTERY_NOTIFY_THRESHOLD 0x82 #define _COMPONENT ACPI_BATTERY_COMPONENT @@ -90,9 +91,11 @@ MODULE_DEVICE_TABLE(acpi, battery_device_ids); enum { ACPI_BATTERY_ALARM_PRESENT, - /* For buggy DSDTs that report negative 16-bit values for either charging - * or discharging current and/or report 0 as 65536 due to bad math. - */ + ACPI_BATTERY_XINFO_PRESENT, + /* For buggy DSDTs that report negative 16-bit values for either + * charging or discharging current and/or report 0 as 65536 + * due to bad math. + */ ACPI_BATTERY_QUIRK_SIGNED16_CURRENT, }; @@ -112,6 +115,12 @@ struct acpi_battery { int design_voltage; int design_capacity_warning; int design_capacity_low; + int cycle_count; + int measurement_accuracy; + int max_sampling_time; + int min_sampling_time; + int max_averaging_interval; + int min_averaging_interval; int capacity_granularity_1; int capacity_granularity_2; int alarm; @@ -200,6 +209,9 @@ static int acpi_battery_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_TECHNOLOGY: val->intval = acpi_battery_technology(battery); break; + case POWER_SUPPLY_PROP_CYCLE_COUNT: + val->intval = battery->cycle_count; + break; case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: val->intval = battery->design_voltage * 1000; break; @@ -241,6 +253,7 @@ static enum power_supply_property charge_battery_props[] = { POWER_SUPPLY_PROP_STATUS, POWER_SUPPLY_PROP_PRESENT, POWER_SUPPLY_PROP_TECHNOLOGY, + POWER_SUPPLY_PROP_CYCLE_COUNT, POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, POWER_SUPPLY_PROP_VOLTAGE_NOW, POWER_SUPPLY_PROP_CURRENT_NOW, @@ -256,6 +269,7 @@ static enum power_supply_property energy_battery_props[] = { POWER_SUPPLY_PROP_STATUS, POWER_SUPPLY_PROP_PRESENT, POWER_SUPPLY_PROP_TECHNOLOGY, + POWER_SUPPLY_PROP_CYCLE_COUNT, POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, POWER_SUPPLY_PROP_VOLTAGE_NOW, POWER_SUPPLY_PROP_CURRENT_NOW, @@ -307,6 +321,28 @@ static struct acpi_offsets info_offsets[] = { {offsetof(struct acpi_battery, oem_info), 1}, }; +static struct acpi_offsets extended_info_offsets[] = { + {offsetof(struct acpi_battery, power_unit), 0}, + {offsetof(struct acpi_battery, design_capacity), 0}, + {offsetof(struct acpi_battery, full_charge_capacity), 0}, + {offsetof(struct acpi_battery, technology), 0}, + {offsetof(struct acpi_battery, design_voltage), 0}, + {offsetof(struct acpi_battery, design_capacity_warning), 0}, + {offsetof(struct acpi_battery, design_capacity_low), 0}, + {offsetof(struct acpi_battery, cycle_count), 0}, + {offsetof(struct acpi_battery, measurement_accuracy), 0}, + {offsetof(struct acpi_battery, max_sampling_time), 0}, + {offsetof(struct acpi_battery, min_sampling_time), 0}, + {offsetof(struct acpi_battery, max_averaging_interval), 0}, + {offsetof(struct acpi_battery, min_averaging_interval), 0}, + {offsetof(struct acpi_battery, capacity_granularity_1), 0}, + {offsetof(struct acpi_battery, capacity_granularity_2), 0}, + {offsetof(struct acpi_battery, model_number), 1}, + {offsetof(struct acpi_battery, serial_number), 1}, + {offsetof(struct acpi_battery, type), 1}, + {offsetof(struct acpi_battery, oem_info), 1}, +}; + static int extract_package(struct acpi_battery *battery, union acpi_object *package, struct acpi_offsets *offsets, int num) @@ -352,22 +388,29 @@ static int acpi_battery_get_info(struct acpi_battery *battery) { int result = -EFAULT; acpi_status status = 0; + char *name = test_bit(ACPI_BATTERY_XINFO_PRESENT, &battery->flags)? + "_BIX" : "_BIF"; + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; if (!acpi_battery_present(battery)) return 0; mutex_lock(&battery->lock); - status = acpi_evaluate_object(battery->device->handle, "_BIF", - NULL, &buffer); + status = acpi_evaluate_object(battery->device->handle, name, + NULL, &buffer); mutex_unlock(&battery->lock); if (ACPI_FAILURE(status)) { - ACPI_EXCEPTION((AE_INFO, status, "Evaluating _BIF")); + ACPI_EXCEPTION((AE_INFO, status, "Evaluating %s", name)); return -ENODEV; } - - result = extract_package(battery, buffer.pointer, - info_offsets, ARRAY_SIZE(info_offsets)); + if (test_bit(ACPI_BATTERY_XINFO_PRESENT, &battery->flags)) + result = extract_package(battery, buffer.pointer, + extended_info_offsets, + ARRAY_SIZE(extended_info_offsets)); + else + result = extract_package(battery, buffer.pointer, + info_offsets, ARRAY_SIZE(info_offsets)); kfree(buffer.pointer); return result; } @@ -414,7 +457,7 @@ static int acpi_battery_set_alarm(struct acpi_battery *battery) union acpi_object arg0 = { .type = ACPI_TYPE_INTEGER }; struct acpi_object_list arg_list = { 1, &arg0 }; - if (!acpi_battery_present(battery)|| + if (!acpi_battery_present(battery) || !test_bit(ACPI_BATTERY_ALARM_PRESENT, &battery->flags)) return -ENODEV; @@ -592,6 +635,7 @@ static int acpi_battery_print_info(struct seq_file *seq, int result) seq_printf(seq, "design capacity low: %d %sh\n", battery->design_capacity_low, acpi_battery_units(battery)); + seq_printf(seq, "cycle count: %i\n", battery->cycle_count); seq_printf(seq, "capacity granularity 1: %d %sh\n", battery->capacity_granularity_1, acpi_battery_units(battery)); @@ -843,6 +887,7 @@ static int acpi_battery_add(struct acpi_device *device) { int result = 0; struct acpi_battery *battery = NULL; + acpi_handle handle; if (!device) return -EINVAL; battery = kzalloc(sizeof(struct acpi_battery), GFP_KERNEL); @@ -853,6 +898,9 @@ static int acpi_battery_add(struct acpi_device *device) strcpy(acpi_device_class(device), ACPI_BATTERY_CLASS); device->driver_data = battery; mutex_init(&battery->lock); + if (ACPI_SUCCESS(acpi_get_handle(battery->device->handle, + "_BIX", &handle))) + set_bit(ACPI_BATTERY_XINFO_PRESENT, &battery->flags); acpi_battery_update(battery); #ifdef CONFIG_ACPI_PROCFS_POWER result = acpi_battery_add_fs(device); -- cgit v1.2.3 From 51fe52229e3765dc56b8d2dd5df656fbf8a20500 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Thu, 14 Jan 2010 15:05:38 +0900 Subject: ARM: SAMSUNG: serial: Modify console initialization. This patch modifies s3c24xx_serial_initconsole function to accept multiple platform UART information structures. This is required on platforms that have differences among the instances of UART ports. As an example, the FIFO sizes could be different for each UART instance and hence multiple platform UART information structures would be needed. This patch also modifies the s3c24xx_console_init macro since it wraps the call to the s3c24xx_serial_initconsole function. Signed-off-by: Thomas Abraham Signed-off-by: Ben Dooks --- drivers/serial/samsung.c | 6 +++--- drivers/serial/samsung.h | 19 ++++++++++++------- 2 files changed, 15 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c index 52e3df113ec0..6982243736d1 100644 --- a/drivers/serial/samsung.c +++ b/drivers/serial/samsung.c @@ -1374,7 +1374,7 @@ s3c24xx_serial_get_options(struct uart_port *port, int *baud, * data. */ -static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info) +static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info **info) { struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports; struct platform_device **platdev_ptr; @@ -1385,7 +1385,7 @@ static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info) platdev_ptr = s3c24xx_uart_devs; for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) { - s3c24xx_serial_init_port(ptr, info, *platdev_ptr); + s3c24xx_serial_init_port(ptr, info[i], *platdev_ptr); } return 0; @@ -1451,7 +1451,7 @@ static struct console s3c24xx_serial_console = { }; int s3c24xx_serial_initconsole(struct platform_driver *drv, - struct s3c24xx_uart_info *info) + struct s3c24xx_uart_info **info) { struct platform_device *dev = s3c24xx_uart_devs[0]; diff --git a/drivers/serial/samsung.h b/drivers/serial/samsung.h index 1fb22343df42..0ac06a07d25f 100644 --- a/drivers/serial/samsung.h +++ b/drivers/serial/samsung.h @@ -75,19 +75,24 @@ extern int s3c24xx_serial_probe(struct platform_device *dev, extern int __devexit s3c24xx_serial_remove(struct platform_device *dev); extern int s3c24xx_serial_initconsole(struct platform_driver *drv, - struct s3c24xx_uart_info *uart); + struct s3c24xx_uart_info **uart); extern int s3c24xx_serial_init(struct platform_driver *drv, struct s3c24xx_uart_info *info); #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE -#define s3c24xx_console_init(__drv, __inf) \ -static int __init s3c_serial_console_init(void) \ -{ \ - return s3c24xx_serial_initconsole(__drv, __inf); \ -} \ - \ +#define s3c24xx_console_init(__drv, __inf) \ +static int __init s3c_serial_console_init(void) \ +{ \ + struct s3c24xx_uart_info *uinfo[CONFIG_SERIAL_SAMSUNG_UARTS]; \ + int i; \ + \ + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) \ + uinfo[i] = __inf; \ + return s3c24xx_serial_initconsole(__drv, uinfo); \ +} \ + \ console_initcall(s3c_serial_console_init) #else -- cgit v1.2.3 From 2b7d03a5cdace237525643d48918e68fe24681ed Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:17:29 +0000 Subject: ide: use standard timing for XFER_PIO_SLOW mode in ide_timing_compute() Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/ide-timings.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/ide-timings.c b/drivers/ide/ide-timings.c index 001a56365be5..c6053ab2b6c6 100644 --- a/drivers/ide/ide-timings.c +++ b/drivers/ide/ide-timings.c @@ -166,12 +166,13 @@ int ide_timing_compute(ide_drive_t *drive, u8 speed, if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */ memset(&p, 0, sizeof(p)); - if (speed <= XFER_PIO_2) - p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; - else if ((speed <= XFER_PIO_4) || - (speed == XFER_PIO_5 && !ata_id_is_cfa(id))) - p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY]; - else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) + if (speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) { + if (speed <= XFER_PIO_2) + p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; + else if ((speed <= XFER_PIO_4) || + (speed == XFER_PIO_5 && !ata_id_is_cfa(id))) + p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY]; + } else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) p.cycle = id[ATA_ID_EIDE_DMA_MIN]; ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B); -- cgit v1.2.3 From 3c8cc8df5a67a539cd185026e6b6f49b576869ba Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:17:37 +0000 Subject: alim15x3: fix PIO timings calculations Just use the standard ide_timing_compute() helper to calculate PIO timings. This fixes many issues with the open-coded version like potential recovery timings underclocking or not accounting for the enhanced cycle time specified by the device. Based on libata pata_ali host driver. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/alim15x3.c | 34 +++++++++++++++------------------- 1 file changed, 15 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c index 0abc43f3101e..99c355e87850 100644 --- a/drivers/ide/alim15x3.c +++ b/drivers/ide/alim15x3.c @@ -8,7 +8,7 @@ * Copyright (C) 2002 Alan Cox * ALi (now ULi M5228) support by Clear Zhang * Copyright (C) 2007 MontaVista Software, Inc. - * Copyright (C) 2007 Bartlomiej Zolnierkiewicz + * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz * * (U)DMA capable version of ali 1533/1543(C), 1535(D) * @@ -60,28 +60,22 @@ static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio) { ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); - struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); - int s_time = t->setup, a_time = t->active, c_time = t->cycle; - u8 s_clc, a_clc, r_clc; unsigned long flags; int bus_speed = ide_pci_clk ? ide_pci_clk : 33; + unsigned long T = 1000000 / bus_speed; /* PCI clock based */ int port = hwif->channel ? 0x5c : 0x58; int portFIFO = hwif->channel ? 0x55 : 0x54; u8 cd_dma_fifo = 0, unit = drive->dn & 1; + struct ide_timing t; - if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8) - s_clc = 0; - if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8) - a_clc = 0; + ide_timing_compute(drive, XFER_PIO_0 + pio, &t, T, 1); + + t.setup = clamp_val(t.setup, 1, 8) & 7; + t.active = clamp_val(t.active, 1, 8) & 7; + t.recover = clamp_val(t.recover, 1, 16) & 15; - if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) { - r_clc = 1; - } else { - if (r_clc >= 16) - r_clc = 0; - } local_irq_save(flags); - + /* * PIO mode => ATA FIFO on, ATAPI FIFO off */ @@ -99,9 +93,11 @@ static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio) pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0); } } - - pci_write_config_byte(dev, port, s_clc); - pci_write_config_byte(dev, port + unit + 2, (a_clc << 4) | r_clc); + + pci_write_config_byte(dev, port, t.setup); + pci_write_config_byte(dev, port + unit + 2, + (t.active << 4) | t.recover); + local_irq_restore(flags); } @@ -584,6 +580,6 @@ static void __exit ali15x3_ide_exit(void) module_init(ali15x3_ide_init); module_exit(ali15x3_ide_exit); -MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox"); +MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox, Bartlomiej Zolnierkiewicz"); MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 293f18ad720f7c10f9f4b8a87827a1f0989e19ee Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:17:50 +0000 Subject: alim15x3: add ali_fifo_control() helper Based on libata pata_ali host driver. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/alim15x3.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c index 99c355e87850..4b47896df9f9 100644 --- a/drivers/ide/alim15x3.c +++ b/drivers/ide/alim15x3.c @@ -48,6 +48,19 @@ static u8 m5229_revision; static u8 chip_is_1543c_e; static struct pci_dev *isa_dev; +static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on) +{ + struct pci_dev *pdev = to_pci_dev(hwif->dev); + int pio_fifo = 0x54 + hwif->channel; + u8 fifo; + int shift = 4 * (drive->dn & 1); + + pci_read_config_byte(pdev, pio_fifo, &fifo); + fifo &= ~(0x0F << shift); + fifo |= (on << shift); + pci_write_config_byte(pdev, pio_fifo, fifo); +} + /** * ali_set_pio_mode - set host controller for PIO mode * @drive: drive @@ -64,8 +77,7 @@ static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio) int bus_speed = ide_pci_clk ? ide_pci_clk : 33; unsigned long T = 1000000 / bus_speed; /* PCI clock based */ int port = hwif->channel ? 0x5c : 0x58; - int portFIFO = hwif->channel ? 0x55 : 0x54; - u8 cd_dma_fifo = 0, unit = drive->dn & 1; + u8 unit = drive->dn & 1; struct ide_timing t; ide_timing_compute(drive, XFER_PIO_0 + pio, &t, T, 1); @@ -79,20 +91,7 @@ static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio) /* * PIO mode => ATA FIFO on, ATAPI FIFO off */ - pci_read_config_byte(dev, portFIFO, &cd_dma_fifo); - if (drive->media==ide_disk) { - if (unit) { - pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50); - } else { - pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05); - } - } else { - if (unit) { - pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F); - } else { - pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0); - } - } + ali_fifo_control(hwif, drive, (drive->media == ide_disk) ? 0x05 : 0x00); pci_write_config_byte(dev, port, t.setup); pci_write_config_byte(dev, port + unit + 2, -- cgit v1.2.3 From 5f6bd68ef539402b25e25d5e3324c59004541d77 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:17:59 +0000 Subject: alim15x3: remove superfluous locking from ali_set_pio_mode() Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/alim15x3.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c index 4b47896df9f9..dabd986216fe 100644 --- a/drivers/ide/alim15x3.c +++ b/drivers/ide/alim15x3.c @@ -73,7 +73,6 @@ static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio) { ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); - unsigned long flags; int bus_speed = ide_pci_clk ? ide_pci_clk : 33; unsigned long T = 1000000 / bus_speed; /* PCI clock based */ int port = hwif->channel ? 0x5c : 0x58; @@ -86,8 +85,6 @@ static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio) t.active = clamp_val(t.active, 1, 8) & 7; t.recover = clamp_val(t.recover, 1, 16) & 15; - local_irq_save(flags); - /* * PIO mode => ATA FIFO on, ATAPI FIFO off */ @@ -96,8 +93,6 @@ static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio) pci_write_config_byte(dev, port, t.setup); pci_write_config_byte(dev, port + unit + 2, (t.active << 4) | t.recover); - - local_irq_restore(flags); } /** -- cgit v1.2.3 From d23f33de3c7fdc4bcbdd7a75d3f7b7be32caf18e Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:18:07 +0000 Subject: alim15x3: cleanup ali_cable_detect() Remove leftover local_irq_[save,restore]() and FIXME note. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/alim15x3.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c index dabd986216fe..8f03cce055fa 100644 --- a/drivers/ide/alim15x3.c +++ b/drivers/ide/alim15x3.c @@ -345,19 +345,13 @@ static int ali_cable_override(struct pci_dev *pdev) * * This checks if the controller and the cable are capable * of UDMA66 transfers. It doesn't check the drives. - * But see note 2 below! - * - * FIXME: frobs bits that are not defined on newer ALi devicea */ static u8 ali_cable_detect(ide_hwif_t *hwif) { struct pci_dev *dev = to_pci_dev(hwif->dev); - unsigned long flags; u8 cbl = ATA_CBL_PATA40, tmpbyte; - local_irq_save(flags); - if (m5229_revision >= 0xC2) { /* * m5229 80-pin cable detection (from Host View) @@ -377,8 +371,6 @@ static u8 ali_cable_detect(ide_hwif_t *hwif) } } - local_irq_restore(flags); - return cbl; } -- cgit v1.2.3 From 31bbb668fbe71a207d38ecd1797f4cd5b8bd710b Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:18:17 +0000 Subject: amd74xx: don't change UDMA settings when programming PIO timings Based on libata pata_amd host driver. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/amd74xx.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/amd74xx.c b/drivers/ide/amd74xx.c index 628cd2e5fed8..108e9b676859 100644 --- a/drivers/ide/amd74xx.c +++ b/drivers/ide/amd74xx.c @@ -3,7 +3,7 @@ * IDE driver for Linux. * * Copyright (c) 2000-2002 Vojtech Pavlik - * Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz + * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz * * Based on the work of: * Andre Hedrick @@ -70,7 +70,8 @@ static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask, default: return; } - pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + (3 - dn), t); + if (timing->udma) + pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + 3 - dn, t); } /* @@ -340,6 +341,6 @@ static void __exit amd74xx_ide_exit(void) module_init(amd74xx_ide_init); module_exit(amd74xx_ide_exit); -MODULE_AUTHOR("Vojtech Pavlik"); +MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz"); MODULE_DESCRIPTION("AMD PCI IDE driver"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 60349ab99f2742a6f04da86724740498c7b1f885 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:18:26 +0000 Subject: cmd64x: fix PIO and MWDMA timings calculations Just use the standard ide_timing_compute() helper to calculate PIO and MWDMA timings. This fixes some issues with the open-coded version like allowing faster MWDMA timings than the ones required by the current PIO mode or not accounting for the enhanced MWDMA cycle time specified by the device. Based on libata pata_cmd64x host driver. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/cmd64x.c | 88 +++++++++++++++++----------------------------------- 1 file changed, 29 insertions(+), 59 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/cmd64x.c b/drivers/ide/cmd64x.c index f2500c8826bb..5c5dd90d032b 100644 --- a/drivers/ide/cmd64x.c +++ b/drivers/ide/cmd64x.c @@ -7,6 +7,7 @@ * Copyright (C) 1998 David S. Miller (davem@redhat.com) * * Copyright (C) 1999-2002 Andre Hedrick + * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz * Copyright (C) 2007,2009 MontaVista Software, Inc. */ @@ -50,72 +51,45 @@ #define UDIDETCR1 0x7B #define DTPR1 0x7C -static u8 quantize_timing(int timing, int quant) -{ - return (timing + quant - 1) / quant; -} - -/* - * This routine calculates active/recovery counts and then writes them into - * the chipset registers. - */ -static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time) +static void cmd64x_program_timings(ide_drive_t *drive, u8 mode) { + ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(drive->hwif->dev); - int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33); - u8 cycle_count, active_count, recovery_count, drwtim; + int bus_speed = ide_pci_clk ? ide_pci_clk : 33; + const unsigned long T = 1000000 / bus_speed; static const u8 recovery_values[] = {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; + static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0}; + static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23}; static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3}; + struct ide_timing t; + u8 arttim = 0; - cycle_count = quantize_timing( cycle_time, clock_time); - active_count = quantize_timing(active_time, clock_time); - recovery_count = cycle_count - active_count; + ide_timing_compute(drive, mode, &t, T, 0); /* * In case we've got too long recovery phase, try to lengthen * the active phase */ - if (recovery_count > 16) { - active_count += recovery_count - 16; - recovery_count = 16; + if (t.recover > 16) { + t.active += t.recover - 16; + t.recover = 16; } - if (active_count > 16) /* shouldn't actually happen... */ - active_count = 16; + if (t.active > 16) /* shouldn't actually happen... */ + t.active = 16; /* * Convert values to internal chipset representation */ - recovery_count = recovery_values[recovery_count]; - active_count &= 0x0f; + t.recover = recovery_values[t.recover]; + t.active &= 0x0f; /* Program the active/recovery counts into the DRWTIM register */ - drwtim = (active_count << 4) | recovery_count; - (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim); -} + pci_write_config_byte(dev, drwtim_regs[drive->dn], + (t.active << 4) | t.recover); -/* - * This routine writes into the chipset registers - * PIO setup/active/recovery timings. - */ -static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio) -{ - ide_hwif_t *hwif = drive->hwif; - struct pci_dev *dev = to_pci_dev(hwif->dev); - struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); - unsigned long setup_count; - unsigned int cycle_time; - u8 arttim = 0; - - static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0}; - static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23}; - - cycle_time = ide_pio_cycle_time(drive, pio); - - program_cycle_times(drive, cycle_time, t->active); - - setup_count = quantize_timing(t->setup, - 1000 / (ide_pci_clk ? ide_pci_clk : 33)); + if (mode >= XFER_SW_DMA_0) + return; /* * The primary channel has individual address setup timing registers @@ -126,15 +100,15 @@ static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio) if (hwif->channel) { ide_drive_t *pair = ide_get_pair_dev(drive); - ide_set_drivedata(drive, (void *)setup_count); + ide_set_drivedata(drive, (void *)(unsigned long)t.setup); if (pair) - setup_count = max_t(u8, setup_count, + t.setup = max_t(u8, t.setup, (unsigned long)ide_get_drivedata(pair)); } - if (setup_count > 5) /* shouldn't actually happen... */ - setup_count = 5; + if (t.setup > 5) /* shouldn't actually happen... */ + t.setup = 5; /* * Program the address setup clocks into the ARTTIM registers. @@ -144,7 +118,7 @@ static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio) if (hwif->channel) arttim &= ~ARTTIM23_INTR_CH1; arttim &= ~0xc0; - arttim |= setup_values[setup_count]; + arttim |= setup_values[t.setup]; (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim); } @@ -162,7 +136,7 @@ static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio) if (pio == 8 || pio == 9) return; - cmd64x_tune_pio(drive, pio); + cmd64x_program_timings(drive, XFER_PIO_0 + pio); } static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed) @@ -197,13 +171,9 @@ static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed) regU |= unit ? 0xC2 : 0x31; break; case XFER_MW_DMA_2: - program_cycle_times(drive, 120, 70); - break; case XFER_MW_DMA_1: - program_cycle_times(drive, 150, 80); - break; case XFER_MW_DMA_0: - program_cycle_times(drive, 480, 215); + cmd64x_program_timings(drive, speed); break; } @@ -471,6 +441,6 @@ static void __exit cmd64x_ide_exit(void) module_init(cmd64x_ide_init); module_exit(cmd64x_ide_exit); -MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick"); +MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz"); MODULE_DESCRIPTION("PCI driver module for CMD64x IDE"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 22cabc2619a58d3e5f95bb8df823da535e103bf4 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:18:38 +0000 Subject: cmd64x: remove superfluous checks from cmd64x_set_dma_mode() Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/cmd64x.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/cmd64x.c b/drivers/ide/cmd64x.c index 5c5dd90d032b..9f89f3116df0 100644 --- a/drivers/ide/cmd64x.c +++ b/drivers/ide/cmd64x.c @@ -146,10 +146,8 @@ static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed) u8 unit = drive->dn & 0x01; u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0; - if (speed >= XFER_SW_DMA_0) { - (void) pci_read_config_byte(dev, pciU, ®U); - regU &= ~(unit ? 0xCA : 0x35); - } + pci_read_config_byte(dev, pciU, ®U); + regU &= ~(unit ? 0xCA : 0x35); switch(speed) { case XFER_UDMA_5: @@ -177,8 +175,7 @@ static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed) break; } - if (speed >= XFER_SW_DMA_0) - (void) pci_write_config_byte(dev, pciU, regU); + pci_write_config_byte(dev, pciU, regU); } static void cmd648_clear_irq(ide_drive_t *drive) -- cgit v1.2.3 From 4d6b328943e87258efdc30110335a681f52d8367 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:18:47 +0000 Subject: cy82c693: fix PIO timings calculations Just use the standard ide_timing_compute() helper to calculate PIO timings. This fixes many issues with the open-coded version like using 16-bit timings when 8-bit ones should be used or not accounting for the enhanced cycle time specified by the device. Based on libata pata_cypress host driver. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/cy82c693.c | 106 ++++++++++--------------------------------------- 1 file changed, 20 insertions(+), 86 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/cy82c693.c b/drivers/ide/cy82c693.c index d6e2cbbc53a0..49dfb8d40dcf 100644 --- a/drivers/ide/cy82c693.c +++ b/drivers/ide/cy82c693.c @@ -1,6 +1,7 @@ /* * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer * Copyright (C) 1998-2002 Andre Hedrick , Integrator + * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz * * CYPRESS CY82C693 chipset IDE controller * @@ -81,80 +82,6 @@ #define CY82_INDEX_CHANNEL1 0x31 #define CY82_INDEX_TIMEOUT 0x32 -/* the min and max PCI bus speed in MHz - from datasheet */ -#define CY82C963_MIN_BUS_SPEED 25 -#define CY82C963_MAX_BUS_SPEED 33 - -/* the struct for the PIO mode timings */ -typedef struct pio_clocks_s { - u8 address_time; /* Address setup (clocks) */ - u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */ - u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */ - u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */ -} pio_clocks_t; - -/* - * calc clocks using bus_speed - * returns (rounded up) time in bus clocks for time in ns - */ -static int calc_clk(int time, int bus_speed) -{ - int clocks; - - clocks = (time*bus_speed+999)/1000 - 1; - - if (clocks < 0) - clocks = 0; - - if (clocks > 0x0F) - clocks = 0x0F; - - return clocks; -} - -/* - * compute the values for the clock registers for PIO - * mode and pci_clk [MHz] speed - * - * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used - * for mode 3 and 4 drives 8 and 16-bit timings are the same - * - */ -static void compute_clocks(u8 pio, pio_clocks_t *p_pclk) -{ - struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); - int clk1, clk2; - int bus_speed = ide_pci_clk ? ide_pci_clk : 33; - - /* we don't check against CY82C693's min and max speed, - * so you can play with the idebus=xx parameter - */ - - /* let's calc the address setup time clocks */ - p_pclk->address_time = (u8)calc_clk(t->setup, bus_speed); - - /* let's calc the active and recovery time clocks */ - clk1 = calc_clk(t->active, bus_speed); - - /* calc recovery timing */ - clk2 = t->cycle - t->active - t->setup; - - clk2 = calc_clk(clk2, bus_speed); - - clk1 = (clk1<<4)|clk2; /* combine active and recovery clocks */ - - /* note: we use the same values for 16bit IOR and IOW - * those are all the same, since I don't have other - * timings than those from ide-lib.c - */ - - p_pclk->time_16r = (u8)clk1; - p_pclk->time_16w = (u8)clk1; - - /* what are good values for 8bit ?? */ - p_pclk->time_8 = (u8)clk1; -} - /* * set DMA mode a specific channel for CY82C693 */ @@ -190,8 +117,11 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) { ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); - pio_clocks_t pclk; + int bus_speed = ide_pci_clk ? ide_pci_clk : 33; + const unsigned long T = 1000000 / bus_speed; unsigned int addrCtrl; + struct ide_timing t; + u8 time_16, time_8; /* select primary or secondary channel */ if (hwif->index > 0) { /* drive is on the secondary channel */ @@ -204,8 +134,12 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) } } - /* let's calc the values for this PIO mode */ - compute_clocks(pio, &pclk); + ide_timing_compute(drive, XFER_PIO_0 + pio, &t, T, 1); + + time_16 = clamp_val(t.recover - 1, 0, 15) | + (clamp_val(t.active - 1, 0, 15) << 4); + time_8 = clamp_val(t.act8b - 1, 0, 15) | + (clamp_val(t.rec8b - 1, 0, 15) << 4); /* now let's write the clocks registers */ if ((drive->dn & 1) == 0) { @@ -217,13 +151,13 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); addrCtrl &= (~0xF); - addrCtrl |= (unsigned int)pclk.address_time; + addrCtrl |= clamp_val(t.setup - 1, 0, 15); pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl); /* now let's set the remaining registers */ - pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r); - pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w); - pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8); + pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, time_16); + pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, time_16); + pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, time_8); } else { /* * set slave drive @@ -233,13 +167,13 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); addrCtrl &= (~0xF0); - addrCtrl |= ((unsigned int)pclk.address_time<<4); + addrCtrl |= (clamp_val(t.setup - 1, 0, 15) << 4); pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl); /* now let's set the remaining registers */ - pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r); - pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w); - pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8); + pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, time_16); + pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, time_16); + pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, time_8); } } @@ -325,6 +259,6 @@ static void __exit cy82c693_ide_exit(void) module_init(cy82c693_ide_init); module_exit(cy82c693_ide_exit); -MODULE_AUTHOR("Andreas Krebs, Andre Hedrick"); +MODULE_AUTHOR("Andreas Krebs, Andre Hedrick, Bartlomiej Zolnierkiewicz"); MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From bd37f65a60c3bb5ec11b47d7e8b539beb87324a9 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:18:58 +0000 Subject: cy82c693: remove stale driver history Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/cy82c693.c | 33 --------------------------------- 1 file changed, 33 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/cy82c693.c b/drivers/ide/cy82c693.c index 49dfb8d40dcf..fbf3dcc26577 100644 --- a/drivers/ide/cy82c693.c +++ b/drivers/ide/cy82c693.c @@ -6,39 +6,6 @@ * CYPRESS CY82C693 chipset IDE controller * * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards. - * Writing the driver was quite simple, since most of the job is - * done by the generic pci-ide support. - * The hard part was finding the CY82C693's datasheet on Cypress's - * web page :-(. But Altavista solved this problem :-). - * - * - * Notes: - * - I recently got a 16.8G IBM DTTA, so I was able to test it with - * a large and fast disk - the results look great, so I'd say the - * driver is working fine :-) - * hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA - * - this is my first linux driver, so there's probably a lot of room - * for optimizations and bug fixing, so feel free to do it. - * - if using PIO mode it's a good idea to set the PIO mode and - * 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda - * - I had some problems with my IBM DHEA with PIO modes < 2 - * (lost interrupts) ????? - * - first tests with DMA look okay, they seem to work, but there is a - * problem with sound - the BusMaster IDE TimeOut should fixed this - * - * Ancient History: - * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693 - * ASK@1999-01-23: v0.33 made a few minor code clean ups - * removed DMA clock speed setting by default - * added boot message - * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut - * added support to set DMA Controller Clock Speed - * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes - * on some drives. - * ASK@1998-10-29: v0.3 added support to set DMA modes - * ASK@1998-10-28: v0.2 added support to set PIO modes - * ASK@1998-10-27: v0.1 first version - chipset detection - * */ #include -- cgit v1.2.3 From fb7b0d5b4096ec2a0f76538a4461345af14e0781 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:19:06 +0000 Subject: opti621: remove stale driver history Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/opti621.c | 71 --------------------------------------------------- 1 file changed, 71 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/opti621.c b/drivers/ide/opti621.c index f1d70d6630fe..2052788fab7a 100644 --- a/drivers/ide/opti621.c +++ b/drivers/ide/opti621.c @@ -8,77 +8,6 @@ * Jan Harkes , * Mark Lord * Some parts of code are from ali14xx.c and from rz1000.c. - * - * OPTi is trademark of OPTi, Octek is trademark of Octek. - * - * I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps - * and disassembled/traced setupvic.exe (DOS program). - * It increases kernel code about 2 kB. - * I don't have this card no more, but I hope I can get some in case - * of needed development. - * My card is Octek PIDE 1.01 (on card) or OPTiViC (program). - * It has a place for a secondary connector in circuit, but nothing - * is there. Also BIOS says no address for - * secondary controller (see bellow in ide_init_opti621). - * I've only tested this on my system, which only has one disk. - * It's Western Digital WDAC2850, with PIO mode 3. The PCI bus - * is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random - * lockups). I tried the OCTEK double speed CD-ROM and - * it does not work! But I can't boot DOS also, so it's probably - * hardware fault. I have connected Conner 80MB, the Seagate 850MB (no - * problems) and Seagate 1GB (as slave, WD as master). My experiences - * with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes - * it slows to about 100kB/s! I don't know why and I have - * not this drive now, so I can't try it again. - * I write this driver because I lost the paper ("manual") with - * settings of jumpers on the card and I have to boot Linux with - * Loadlin except LILO, cause I have to run the setupvic.exe program - * already or I get disk errors (my test: rpm -Vf - * /usr/X11R6/bin/XF86_SVGA - or any big file). - * Some numbers from hdparm -t /dev/hda: - * Timing buffer-cache reads: 32 MB in 3.02 seconds =10.60 MB/sec - * Timing buffered disk reads: 16 MB in 5.52 seconds = 2.90 MB/sec - * I have 4 Megs/s before, but I don't know why (maybe changes - * in hdparm test). - * After release of 0.1, I got some successful reports, so it might work. - * - * The main problem with OPTi is that some timings for master - * and slave must be the same. For example, if you have master - * PIO 3 and slave PIO 0, driver have to set some timings of - * master for PIO 0. Second problem is that opti621_set_pio_mode - * got only one drive to set, but have to set both drives. - * This is solved in compute_pios. If you don't set - * the second drive, compute_pios use ide_get_best_pio_mode - * for autoselect mode (you can change it to PIO 0, if you want). - * If you then set the second drive to another PIO, the old value - * (automatically selected) will be overrided by yours. - * There is a 25/33MHz switch in configuration - * register, but driver is written for use at any frequency. - * - * Version 0.1, Nov 8, 1996 - * by Jaromir Koutek, for 2.1.8. - * Initial version of driver. - * - * Version 0.2 - * Number 0.2 skipped. - * - * Version 0.3, Nov 29, 1997 - * by Mark Lord (probably), for 2.1.68 - * Updates for use with new IDE block driver. - * - * Version 0.4, Dec 14, 1997 - * by Jan Harkes - * Fixed some errors and cleaned the code. - * - * Version 0.5, Jan 2, 1998 - * by Jaromir Koutek - * Updates for use with (again) new IDE block driver. - * Update of documentation. - * - * Version 0.6, Jan 2, 1999 - * by Jaromir Koutek - * Reversed to version 0.3 of the driver, because - * 0.5 doesn't work. */ #include -- cgit v1.2.3 From a337c2272731d538827153b32f547ef7c131a4cb Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:19:14 +0000 Subject: pdc202xx_old: add ->init_hwif method Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/pdc202xx_old.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/pdc202xx_old.c b/drivers/ide/pdc202xx_old.c index 35161dd840a0..1d20594ee420 100644 --- a/drivers/ide/pdc202xx_old.c +++ b/drivers/ide/pdc202xx_old.c @@ -1,7 +1,7 @@ /* * Copyright (C) 1998-2002 Andre Hedrick * Copyright (C) 2006-2007, 2009 MontaVista Software, Inc. - * Copyright (C) 2007 Bartlomiej Zolnierkiewicz + * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz * * Portions Copyright (C) 1999 Promise Technology, Inc. * Author: Frank Tiernan (frankt@promise.com) @@ -21,8 +21,6 @@ #define DRV_NAME "pdc202xx_old" -static void pdc_old_disable_66MHz_clock(ide_hwif_t *); - static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) { ide_hwif_t *hwif = drive->hwif; @@ -32,12 +30,6 @@ static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) u8 AP = 0, BP = 0, CP = 0; u8 TA = 0, TB = 0, TC = 0; - /* - * TODO: do this once per channel - */ - if (dev->device != PCI_DEVICE_ID_PROMISE_20246) - pdc_old_disable_66MHz_clock(hwif); - pci_read_config_byte(dev, drive_pci, &AP); pci_read_config_byte(dev, drive_pci + 1, &BP); pci_read_config_byte(dev, drive_pci + 2, &CP); @@ -145,6 +137,11 @@ static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif) outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); } +static void pdc2026x_init_hwif(ide_hwif_t *hwif) +{ + pdc_old_disable_66MHz_clock(hwif); +} + static void pdc202xx_dma_start(ide_drive_t *drive) { if (drive->current_speed > XFER_UDMA_2) @@ -261,6 +258,7 @@ static const struct ide_dma_ops pdc2026x_dma_ops = { { \ .name = DRV_NAME, \ .init_chipset = init_chipset_pdc202xx, \ + .init_hwif = pdc2026x_init_hwif, \ .port_ops = &pdc2026x_port_ops, \ .dma_ops = &pdc2026x_dma_ops, \ .host_flags = IDE_HFLAGS_PDC202XX, \ @@ -356,6 +354,6 @@ static void __exit pdc202xx_ide_exit(void) module_init(pdc202xx_ide_init); module_exit(pdc202xx_ide_exit); -MODULE_AUTHOR("Andre Hedrick, Frank Tiernan"); +MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz"); MODULE_DESCRIPTION("PCI driver module for older Promise IDE"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From e7593af6e5c24e323217c12d011ad7e43742ca6f Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:19:22 +0000 Subject: serverworks: cleanup svwks_udma_filter() * remove dead OSB4 UDMA support * remove unreachable code * make isa_dev local to ->init_chipset Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/serverworks.c | 40 +++++++++++----------------------------- 1 file changed, 11 insertions(+), 29 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/serverworks.c b/drivers/ide/serverworks.c index b6554ef92716..1777c919237e 100644 --- a/drivers/ide/serverworks.c +++ b/drivers/ide/serverworks.c @@ -2,7 +2,7 @@ * Copyright (C) 1998-2000 Michel Aubry * Copyright (C) 1998-2000 Andrzej Krzysztofowicz * Copyright (C) 1998-2000 Andre Hedrick - * Copyright (C) 2007 Bartlomiej Zolnierkiewicz + * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz * Portions copyright (c) 2001 Sun Microsystems * * @@ -52,8 +52,6 @@ static const char *svwks_bad_ata100[] = { NULL }; -static struct pci_dev *isa_dev; - static int check_in_drive_lists (ide_drive_t *drive, const char **list) { char *m = (char *)&drive->id[ATA_ID_PROD]; @@ -67,26 +65,14 @@ static int check_in_drive_lists (ide_drive_t *drive, const char **list) static u8 svwks_udma_filter(ide_drive_t *drive) { struct pci_dev *dev = to_pci_dev(drive->hwif->dev); - u8 mask = 0; - if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) + if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) { return 0x1f; - if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { - u32 reg = 0; - if (isa_dev) - pci_read_config_dword(isa_dev, 0x64, ®); - - /* - * Don't enable UDMA on disk devices for the moment - */ - if(drive->media == ide_disk) - return 0; - /* Check the OSB4 DMA33 enable bit */ - return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0; } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) { return 0x07; - } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) { - u8 btr = 0, mode; + } else { + u8 btr = 0, mode, mask; + pci_read_config_byte(dev, 0x5A, &btr); mode = btr & 0x3; @@ -101,13 +87,9 @@ static u8 svwks_udma_filter(ide_drive_t *drive) case 1: mask = 0x07; break; default: mask = 0x00; break; } - } - if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || - (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) && - (!(PCI_FUNC(dev->devfn) & 1))) - mask = 0x1f; - return mask; + return mask; + } } static u8 svwks_csb_check (struct pci_dev *dev) @@ -185,8 +167,9 @@ static int init_chipset_svwks(struct pci_dev *dev) /* OSB4 : South Bridge and IDE */ if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { - isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, - PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); + struct pci_dev *isa_dev = + pci_get_device(PCI_VENDOR_ID_SERVERWORKS, + PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); if (isa_dev) { pci_read_config_dword(isa_dev, 0x64, ®); reg &= ~0x00002000; /* disable 600ns interrupt mask */ @@ -343,7 +326,6 @@ static u8 svwks_cable_detect(ide_hwif_t *hwif) static const struct ide_port_ops osb4_port_ops = { .set_pio_mode = svwks_set_pio_mode, .set_dma_mode = svwks_set_dma_mode, - .udma_filter = svwks_udma_filter, }; static const struct ide_port_ops svwks_port_ops = { @@ -460,6 +442,6 @@ static void __exit svwks_ide_exit(void) module_init(svwks_ide_init); module_exit(svwks_ide_exit); -MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick"); +MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz"); MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From cb06fc3f4c25d33c188d77e3f7e46112e7d71f38 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:19:30 +0000 Subject: serverworks: add missing pci_dev_put() call Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/serverworks.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/ide/serverworks.c b/drivers/ide/serverworks.c index 1777c919237e..657f0433ec50 100644 --- a/drivers/ide/serverworks.c +++ b/drivers/ide/serverworks.c @@ -178,6 +178,7 @@ static int init_chipset_svwks(struct pci_dev *dev) "enabled.\n", pci_name(dev)); reg |= 0x00004000; /* enable UDMA/33 support */ pci_write_config_dword(isa_dev, 0x64, reg); + pci_dev_put(isa_dev); } } -- cgit v1.2.3 From 42036c85a68c82389f011eceab594c64956d0c2d Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:19:37 +0000 Subject: via82cxxx: vx855 is a single channel controller Based on commit e4d866c for pata_via host driver (PCI ID was later changed by commit 5993856). Update my credits while at it. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/via82cxxx.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/via82cxxx.c b/drivers/ide/via82cxxx.c index 028de26a25fe..29f3be311f8d 100644 --- a/drivers/ide/via82cxxx.c +++ b/drivers/ide/via82cxxx.c @@ -6,7 +6,7 @@ * vt8235, vt8237, vt8237a * * Copyright (c) 2000-2002 Vojtech Pavlik - * Copyright (c) 2007 Bartlomiej Zolnierkiewicz + * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz * * Based on the work of: * Michel Aubry @@ -55,6 +55,10 @@ #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */ #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */ +enum { + VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */ +}; + /* * VIA SouthBridge chips. */ @@ -436,10 +440,13 @@ static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_i via_clock = 33333; } - if (idx == 0) - d.host_flags |= IDE_HFLAG_NO_AUTODMA; - else + if (idx == 1) d.enablebits[1].reg = d.enablebits[0].reg = 0; + else + d.host_flags |= IDE_HFLAG_NO_AUTODMA; + + if (idx == VIA_IDFLAG_SINGLE) + d.host_flags |= IDE_HFLAG_SINGLE; if ((via_config->flags & VIA_NO_UNMASK) == 0) d.host_flags |= IDE_HFLAG_UNMASK_IRQS; @@ -475,7 +482,7 @@ static const struct pci_device_id via_pci_tbl[] = { { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 }, { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 }, { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 }, - { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), 0 }, + { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE }, { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 }, { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 }, { 0, }, @@ -504,6 +511,6 @@ static void __exit via_ide_exit(void) module_init(via_ide_init); module_exit(via_ide_exit); -MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick"); +MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick"); MODULE_DESCRIPTION("PCI driver module for VIA IDE"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 76937fa765bd65c052b87812e46d5b90094e57b8 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:19:44 +0000 Subject: ide: add SATA cable detection support Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/ide-iops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ide/ide-iops.c b/drivers/ide/ide-iops.c index 222c1ef65fb9..376f2dc410c5 100644 --- a/drivers/ide/ide-iops.c +++ b/drivers/ide/ide-iops.c @@ -231,7 +231,7 @@ u8 eighty_ninty_three(ide_drive_t *drive) u16 *id = drive->id; int ivb = ide_in_drive_list(id, ivb_list); - if (hwif->cbl == ATA_CBL_PATA40_SHORT) + if (hwif->cbl == ATA_CBL_SATA || hwif->cbl == ATA_CBL_PATA40_SHORT) return 1; if (ivb) -- cgit v1.2.3 From a13e4865fac374f2edf2666b66f2f88e527db2b7 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:19:53 +0000 Subject: via82cxxx: fix SATA cable detection Add VIA_SATA_PATA flag for cx700, vx800 and vx855 chipsets (the first port is SATA). Based on commits 7585eb1, bfce5e0 and e4d866c for pata_via host driver. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/via82cxxx.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/via82cxxx.c b/drivers/ide/via82cxxx.c index 29f3be311f8d..11b3e711451a 100644 --- a/drivers/ide/via82cxxx.c +++ b/drivers/ide/via82cxxx.c @@ -54,6 +54,7 @@ #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */ #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */ #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */ +#define VIA_SATA_PATA 0x80 /* SATA/PATA combined configuration */ enum { VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */ @@ -71,9 +72,9 @@ static struct via_isa_bridge { u8 udma_mask; u8 flags; } via_isa_bridges[] = { - { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, - { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, - { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, + { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, + { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, + { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, @@ -366,6 +367,9 @@ static u8 via82cxxx_cable_detect(ide_hwif_t *hwif) if (via_cable_override(pdev)) return ATA_CBL_PATA40_SHORT; + if ((vdev->via_config->flags & VIA_SATA_PATA) && hwif->channel == 0) + return ATA_CBL_SATA; + if ((vdev->via_80w >> hwif->channel) & 1) return ATA_CBL_PATA80; else -- cgit v1.2.3 From f931a5d5785d7b7c44871bd7ad2762e29dfddf29 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:20:00 +0000 Subject: via82cxxx: workaround h/w bugs Add custom struct ide_tp_ops instance to fix the internal bug of some VIA chipsets which will reset the device register after changing the nIEN bit in the device control register. Based on commit bfce5e0 for pata_via host driver. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/via82cxxx.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) (limited to 'drivers') diff --git a/drivers/ide/via82cxxx.c b/drivers/ide/via82cxxx.c index 11b3e711451a..46e8ddbdf031 100644 --- a/drivers/ide/via82cxxx.c +++ b/drivers/ide/via82cxxx.c @@ -107,6 +107,7 @@ struct via82cxxx_dev { struct via_isa_bridge *via_config; unsigned int via_80w; + u8 cached_device[2]; }; /** @@ -382,10 +383,66 @@ static const struct ide_port_ops via_port_ops = { .cable_detect = via82cxxx_cable_detect, }; +static void via_write_devctl(ide_hwif_t *hwif, u8 ctl) +{ + struct via82cxxx_dev *vdev = hwif->host->host_priv; + + outb(ctl, hwif->io_ports.ctl_addr); + outb(vdev->cached_device[hwif->channel], hwif->io_ports.device_addr); +} + +static void __via_dev_select(ide_drive_t *drive, u8 select) +{ + ide_hwif_t *hwif = drive->hwif; + struct via82cxxx_dev *vdev = hwif->host->host_priv; + + outb(select, hwif->io_ports.device_addr); + vdev->cached_device[hwif->channel] = select; +} + +static void via_dev_select(ide_drive_t *drive) +{ + __via_dev_select(drive, drive->select | ATA_DEVICE_OBS); +} + +static void via_tf_load(ide_drive_t *drive, struct ide_taskfile *tf, u8 valid) +{ + ide_hwif_t *hwif = drive->hwif; + struct ide_io_ports *io_ports = &hwif->io_ports; + + if (valid & IDE_VALID_FEATURE) + outb(tf->feature, io_ports->feature_addr); + if (valid & IDE_VALID_NSECT) + outb(tf->nsect, io_ports->nsect_addr); + if (valid & IDE_VALID_LBAL) + outb(tf->lbal, io_ports->lbal_addr); + if (valid & IDE_VALID_LBAM) + outb(tf->lbam, io_ports->lbam_addr); + if (valid & IDE_VALID_LBAH) + outb(tf->lbah, io_ports->lbah_addr); + if (valid & IDE_VALID_DEVICE) + __via_dev_select(drive, tf->device); +} + +const struct ide_tp_ops via_tp_ops = { + .exec_command = ide_exec_command, + .read_status = ide_read_status, + .read_altstatus = ide_read_altstatus, + .write_devctl = via_write_devctl, + + .dev_select = via_dev_select, + .tf_load = via_tf_load, + .tf_read = ide_tf_read, + + .input_data = ide_input_data, + .output_data = ide_output_data, +}; + static const struct ide_port_info via82cxxx_chipset __devinitdata = { .name = DRV_NAME, .init_chipset = init_chipset_via82cxxx, .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } }, + .tp_ops = &via_tp_ops, .port_ops = &via_port_ops, .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST | IDE_HFLAG_POST_SET_MODE | -- cgit v1.2.3 From 5b6c82ea0fd130a9f0bb7f4d86f6dbbf2fdaaa04 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:20:07 +0000 Subject: via82cxxx: add support for vt8261 and future chips Based on commit e4d866c for pata_via host driver. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/via82cxxx.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/via82cxxx.c b/drivers/ide/via82cxxx.c index 46e8ddbdf031..1a3214389ffb 100644 --- a/drivers/ide/via82cxxx.c +++ b/drivers/ide/via82cxxx.c @@ -75,6 +75,7 @@ static struct via_isa_bridge { { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, + { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, @@ -97,6 +98,7 @@ static struct via_isa_bridge { { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO }, { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK }, { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, + { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, { NULL } }; @@ -205,7 +207,8 @@ static struct via_isa_bridge *via_config_find(struct pci_dev **isa) { struct via_isa_bridge *via_config; - for (via_config = via_isa_bridges; via_config->id; via_config++) + for (via_config = via_isa_bridges; + via_config->id != PCI_DEVICE_ID_VIA_ANON; via_config++) if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA + !!(via_config->flags & VIA_BAD_ID), via_config->id, NULL))) { @@ -467,11 +470,6 @@ static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_i * Find the ISA bridge and check we know what it is. */ via_config = via_config_find(&isa); - if (!via_config->id) { - printk(KERN_WARNING DRV_NAME " %s: unknown chipset, skipping\n", - pci_name(dev)); - return -ENODEV; - } /* * Print the boot message. -- cgit v1.2.3 From a354ae8747d0687093ce244e76b15b6174d2f098 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:20:14 +0000 Subject: via82cxxx: add support for VT6415 PCIE PATA IDE Host Controller Based on commits 5955c7a and 7d948b1 for pata_via host driver. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/via82cxxx.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/ide/via82cxxx.c b/drivers/ide/via82cxxx.c index 1a3214389ffb..3db35b0142dc 100644 --- a/drivers/ide/via82cxxx.c +++ b/drivers/ide/via82cxxx.c @@ -78,6 +78,7 @@ static struct via_isa_bridge { { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, + { "vt6415", PCI_DEVICE_ID_VIA_6410, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST }, { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, @@ -543,6 +544,7 @@ static const struct pci_device_id via_pci_tbl[] = { { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 }, { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE }, { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 }, + { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6415), 1 }, { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 }, { 0, }, }; -- cgit v1.2.3 From 68d0a036162f12d8be07c9fc140507cc1c8c6120 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:20:21 +0000 Subject: via82cxxx: fix UDMA settings programming * preserve 80-wire cable detection bit * don't clear UDMA settings when programming PIO/MWDMA modes Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/via82cxxx.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/via82cxxx.c b/drivers/ide/via82cxxx.c index 3db35b0142dc..fbecf8ea8207 100644 --- a/drivers/ide/via82cxxx.c +++ b/drivers/ide/via82cxxx.c @@ -146,10 +146,25 @@ static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break; case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; - default: return; } - pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t); + /* Set UDMA unless device is not UDMA capable */ + if (vdev->via_config->udma_mask) { + u8 udma_etc; + + pci_read_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, &udma_etc); + + /* clear transfer mode bit */ + udma_etc &= ~0x20; + + if (timing->udma) { + /* preserve 80-wire cable detection bit */ + udma_etc &= 0x10; + udma_etc |= t; + } + + pci_write_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, udma_etc); + } } /** -- cgit v1.2.3 From d2d4e780aff2fab46a792ebc89f80d1a6872b325 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:20:28 +0000 Subject: ide: add drive->pio_mode field Add pio_mode field to ide_drive_t matching pio_mode field used in struct ata_device. The validity of the field is restricted to ->set_pio_mode method only currently in IDE subsystem. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/ide-devsets.c | 2 ++ drivers/ide/ide-probe.c | 2 ++ drivers/ide/ide-xfer-mode.c | 3 +++ include/linux/ide.h | 1 + 4 files changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/ide/ide-devsets.c b/drivers/ide/ide-devsets.c index 1099bf7cf968..cb3341ce655c 100644 --- a/drivers/ide/ide-devsets.c +++ b/drivers/ide/ide-devsets.c @@ -105,6 +105,8 @@ static int set_pio_mode(ide_drive_t *drive, int arg) return -ENOSYS; if (set_pio_mode_abuse(drive->hwif, arg)) { + drive->pio_mode = arg + XFER_PIO_0; + if (arg == 8 || arg == 9) { unsigned long flags; diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c index 4d76ba473097..9a9f10f4cf9f 100644 --- a/drivers/ide/ide-probe.c +++ b/drivers/ide/ide-probe.c @@ -1043,6 +1043,8 @@ static void ide_port_init_devices(ide_hwif_t *hwif) if (hwif->host_flags & IDE_HFLAG_NO_UNMASK_IRQS) drive->dev_flags |= IDE_DFLAG_NO_UNMASK; + drive->pio_mode = XFER_PIO_0; + if (port_ops && port_ops->init_dev) port_ops->init_dev(drive); } diff --git a/drivers/ide/ide-xfer-mode.c b/drivers/ide/ide-xfer-mode.c index 46d203ce60cc..cdae463f6b41 100644 --- a/drivers/ide/ide-xfer-mode.c +++ b/drivers/ide/ide-xfer-mode.c @@ -135,6 +135,7 @@ int ide_set_pio_mode(ide_drive_t *drive, const u8 mode) * set transfer mode on the device in ->set_pio_mode method... */ if (port_ops->set_dma_mode == NULL) { + drive->pio_mode = mode; port_ops->set_pio_mode(drive, mode - XFER_PIO_0); return 0; } @@ -142,9 +143,11 @@ int ide_set_pio_mode(ide_drive_t *drive, const u8 mode) if (hwif->host_flags & IDE_HFLAG_POST_SET_MODE) { if (ide_config_drive_speed(drive, mode)) return -1; + drive->pio_mode = mode; port_ops->set_pio_mode(drive, mode - XFER_PIO_0); return 0; } else { + drive->pio_mode = mode; port_ops->set_pio_mode(drive, mode - XFER_PIO_0); return ide_config_drive_speed(drive, mode); } diff --git a/include/linux/ide.h b/include/linux/ide.h index 0ec612959042..b5d2e9655059 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -515,6 +515,7 @@ struct ide_drive_s { u8 init_speed; /* transfer rate set at boot */ u8 current_speed; /* current transfer rate set */ u8 desired_speed; /* desired transfer rate set */ + u8 pio_mode; /* for ->set_pio_mode _only_ */ u8 dn; /* now wide spread use */ u8 acoustic; /* acoustic management */ u8 media; /* disk, cdrom, tape, floppy, ... */ -- cgit v1.2.3 From 3fccaa192b9501e79a57e02e62b6bf420d2b461e Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:20:35 +0000 Subject: ide: add drive->dma_mode field Add dma_mode field to ide_drive_t matching dma_mode field used in struct ata_device. The validity of the field is restricted to ->dma_pio_mode method only currently in IDE subsystem. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/aec62xx.c | 1 + drivers/ide/ide-xfer-mode.c | 2 ++ include/linux/ide.h | 1 + 3 files changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/ide/aec62xx.c b/drivers/ide/aec62xx.c index 878f8ec6dbe1..4c869872eb9a 100644 --- a/drivers/ide/aec62xx.c +++ b/drivers/ide/aec62xx.c @@ -136,6 +136,7 @@ static void aec6260_set_mode(ide_drive_t *drive, const u8 speed) static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio) { + drive->dma_mode = pio + XFER_PIO_0; drive->hwif->port_ops->set_dma_mode(drive, pio + XFER_PIO_0); } diff --git a/drivers/ide/ide-xfer-mode.c b/drivers/ide/ide-xfer-mode.c index cdae463f6b41..c2323869d92a 100644 --- a/drivers/ide/ide-xfer-mode.c +++ b/drivers/ide/ide-xfer-mode.c @@ -167,9 +167,11 @@ int ide_set_dma_mode(ide_drive_t *drive, const u8 mode) if (hwif->host_flags & IDE_HFLAG_POST_SET_MODE) { if (ide_config_drive_speed(drive, mode)) return -1; + drive->dma_mode = mode; port_ops->set_dma_mode(drive, mode); return 0; } else { + drive->dma_mode = mode; port_ops->set_dma_mode(drive, mode); return ide_config_drive_speed(drive, mode); } diff --git a/include/linux/ide.h b/include/linux/ide.h index b5d2e9655059..746ef9fdabcb 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -516,6 +516,7 @@ struct ide_drive_s { u8 current_speed; /* current transfer rate set */ u8 desired_speed; /* desired transfer rate set */ u8 pio_mode; /* for ->set_pio_mode _only_ */ + u8 dma_mode; /* for ->dma_pio_mode _only_ */ u8 dn; /* now wide spread use */ u8 acoustic; /* acoustic management */ u8 media; /* disk, cdrom, tape, floppy, ... */ -- cgit v1.2.3 From e085b3cae85af47eb0a3eda3186bd898310fb322 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Tue, 19 Jan 2010 01:44:41 -0800 Subject: ide: change ->set_pio_mode method parameters Change ->set_pio_mode method parameters to match ->set_piomode method used in struct ata_port_operations. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/aec62xx.c | 6 +++--- drivers/ide/ali14xx.c | 3 ++- drivers/ide/alim15x3.c | 7 +++---- drivers/ide/amd74xx.c | 4 ++-- drivers/ide/at91_ide.c | 5 +++-- drivers/ide/atiixp.c | 7 ++++--- drivers/ide/au1xxx-ide.c | 5 ++--- drivers/ide/cmd640.c | 3 ++- drivers/ide/cmd64x.c | 4 +++- drivers/ide/cs5520.c | 7 ++++--- drivers/ide/cs5530.c | 7 ++++--- drivers/ide/cs5535.c | 6 +++--- drivers/ide/cs5536.c | 7 ++++--- drivers/ide/cy82c693.c | 5 ++--- drivers/ide/dtc2278.c | 4 ++-- drivers/ide/hpt366.c | 4 ++-- drivers/ide/ht6560b.c | 3 ++- drivers/ide/ide-devsets.c | 4 ++-- drivers/ide/ide-xfer-mode.c | 6 +++--- drivers/ide/it8172.c | 10 +++++----- drivers/ide/it8213.c | 14 +++++++------- drivers/ide/it821x.c | 6 +++--- drivers/ide/jmicron.c | 2 +- drivers/ide/opti621.c | 6 +++--- drivers/ide/palm_bk3710.c | 5 +++-- drivers/ide/pdc202xx_new.c | 4 ++-- drivers/ide/pdc202xx_old.c | 4 ++-- drivers/ide/piix.c | 14 +++++++------- drivers/ide/pmac.c | 5 ++--- drivers/ide/qd65xx.c | 10 ++++------ drivers/ide/sc1200.c | 4 ++-- drivers/ide/scc_pata.c | 6 +++--- drivers/ide/serverworks.c | 5 +++-- drivers/ide/siimage.c | 6 +++--- drivers/ide/sis5513.c | 4 ++-- drivers/ide/sl82c105.c | 5 +++-- drivers/ide/slc90e66.c | 13 +++++++------ drivers/ide/tc86c001.c | 4 ++-- drivers/ide/triflex.c | 4 ++-- drivers/ide/tx4938ide.c | 5 ++--- drivers/ide/tx4939ide.c | 4 ++-- drivers/ide/umc8672.c | 5 +++-- drivers/ide/via82cxxx.c | 6 +++--- include/linux/ide.h | 2 +- 44 files changed, 129 insertions(+), 121 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/aec62xx.c b/drivers/ide/aec62xx.c index 4c869872eb9a..3790847361c3 100644 --- a/drivers/ide/aec62xx.c +++ b/drivers/ide/aec62xx.c @@ -134,10 +134,10 @@ static void aec6260_set_mode(ide_drive_t *drive, const u8 speed) local_irq_restore(flags); } -static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void aec_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - drive->dma_mode = pio + XFER_PIO_0; - drive->hwif->port_ops->set_dma_mode(drive, pio + XFER_PIO_0); + drive->dma_mode = drive->pio_mode; + hwif->port_ops->set_dma_mode(drive, drive->dma_mode); } static int init_chipset_aec62xx(struct pci_dev *dev) diff --git a/drivers/ide/ali14xx.c b/drivers/ide/ali14xx.c index 90da1f953ed0..25b9fe3a9f8e 100644 --- a/drivers/ide/ali14xx.c +++ b/drivers/ide/ali14xx.c @@ -109,13 +109,14 @@ static DEFINE_SPINLOCK(ali14xx_lock); * This function computes timing parameters * and sets controller registers accordingly. */ -static void ali14xx_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void ali14xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { int driveNum; int time1, time2; u8 param1, param2, param3, param4; unsigned long flags; int bus_speed = ide_vlb_clk ? ide_vlb_clk : 50; + const u8 pio = drive->pio_mode - XFER_PIO_0; struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); /* calculate timing, according to PIO mode */ diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c index 8f03cce055fa..28cee1055f76 100644 --- a/drivers/ide/alim15x3.c +++ b/drivers/ide/alim15x3.c @@ -63,15 +63,14 @@ static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on) /** * ali_set_pio_mode - set host controller for PIO mode + * @hwif: port * @drive: drive - * @pio: PIO mode number * * Program the controller for the given PIO mode. */ -static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); int bus_speed = ide_pci_clk ? ide_pci_clk : 33; unsigned long T = 1000000 / bus_speed; /* PCI clock based */ @@ -79,7 +78,7 @@ static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio) u8 unit = drive->dn & 1; struct ide_timing t; - ide_timing_compute(drive, XFER_PIO_0 + pio, &t, T, 1); + ide_timing_compute(drive, drive->pio_mode, &t, T, 1); t.setup = clamp_val(t.setup, 1, 8) & 7; t.active = clamp_val(t.active, 1, 8) & 7; diff --git a/drivers/ide/amd74xx.c b/drivers/ide/amd74xx.c index 108e9b676859..3eee7be7ca6f 100644 --- a/drivers/ide/amd74xx.c +++ b/drivers/ide/amd74xx.c @@ -108,9 +108,9 @@ static void amd_set_drive(ide_drive_t *drive, const u8 speed) * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning. */ -static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void amd_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - amd_set_drive(drive, XFER_PIO_0 + pio); + amd_set_drive(drive, drive->pio_mode); } static void amd7409_cable_detect(struct pci_dev *dev) diff --git a/drivers/ide/at91_ide.c b/drivers/ide/at91_ide.c index 248219a89a68..000a78e5246c 100644 --- a/drivers/ide/at91_ide.c +++ b/drivers/ide/at91_ide.c @@ -172,11 +172,12 @@ static void at91_ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd, leave_16bit(chipselect, mode); } -static void at91_ide_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void at91_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { struct ide_timing *timing; - u8 chipselect = drive->hwif->select_data; + u8 chipselect = hwif->select_data; int use_iordy = 0; + const u8 pio = drive->pio_mode - XFER_PIO_0; pdbg("chipselect %u pio %u\n", chipselect, pio); diff --git a/drivers/ide/atiixp.c b/drivers/ide/atiixp.c index 837322b10a4c..b6848dfb93b0 100644 --- a/drivers/ide/atiixp.c +++ b/drivers/ide/atiixp.c @@ -42,19 +42,20 @@ static DEFINE_SPINLOCK(atiixp_lock); /** * atiixp_set_pio_mode - set host controller for PIO mode + * @hwif: port * @drive: drive - * @pio: PIO mode number * * Set the interface PIO mode. */ -static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void atiixp_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - struct pci_dev *dev = to_pci_dev(drive->hwif->dev); + struct pci_dev *dev = to_pci_dev(hwif->dev); unsigned long flags; int timing_shift = (drive->dn ^ 1) * 8; u32 pio_timing_data; u16 pio_mode_data; + const u8 pio = drive->pio_mode - XFER_PIO_0; spin_lock_irqsave(&atiixp_lock, flags); diff --git a/drivers/ide/au1xxx-ide.c b/drivers/ide/au1xxx-ide.c index 87cef0c440ad..c90e9b0a9f6e 100644 --- a/drivers/ide/au1xxx-ide.c +++ b/drivers/ide/au1xxx-ide.c @@ -99,12 +99,11 @@ static void au1xxx_output_data(ide_drive_t *drive, struct ide_cmd *cmd, } #endif -static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void au1xxx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); - /* set pio mode! */ - switch(pio) { + switch (drive->pio_mode - XFER_PIO_0) { case 0: mem_sttime = SBC_IDE_TIMING(PIO0); diff --git a/drivers/ide/cmd640.c b/drivers/ide/cmd640.c index 1a32d62ed86b..c7d46a3d347a 100644 --- a/drivers/ide/cmd640.c +++ b/drivers/ide/cmd640.c @@ -572,9 +572,10 @@ static void cmd640_set_mode(ide_drive_t *drive, unsigned int index, program_drive_counts(drive, index); } -static void cmd640_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void cmd640_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { unsigned int index = 0, cycle_time; + const u8 pio = drive->pio_mode - XFER_PIO_0; u8 b; switch (pio) { diff --git a/drivers/ide/cmd64x.c b/drivers/ide/cmd64x.c index 9f89f3116df0..0b11745937e7 100644 --- a/drivers/ide/cmd64x.c +++ b/drivers/ide/cmd64x.c @@ -127,8 +127,10 @@ static void cmd64x_program_timings(ide_drive_t *drive, u8 mode) * Special cases are 8: prefetch off, 9: prefetch on (both never worked) */ -static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void cmd64x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { + const u8 pio = drive->pio_mode - XFER_PIO_0; + /* * Filter out the prefetch control values * to prevent PIO5 from being programmed diff --git a/drivers/ide/cs5520.c b/drivers/ide/cs5520.c index 09f98ed0731f..b8094f049f3e 100644 --- a/drivers/ide/cs5520.c +++ b/drivers/ide/cs5520.c @@ -57,11 +57,11 @@ static struct pio_clocks cs5520_pio_clocks[]={ {1, 2, 1} }; -static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void cs5520_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *pdev = to_pci_dev(hwif->dev); int controller = drive->dn > 1 ? 1 : 0; + const u8 pio = drive->pio_mode - XFER_PIO_0; /* 8bit CAT/CRT - 8bit command timing for channel */ pci_write_config_byte(pdev, 0x62 + controller, @@ -85,7 +85,8 @@ static void cs5520_set_dma_mode(ide_drive_t *drive, const u8 speed) { printk(KERN_ERR "cs55x0: bad ide timing.\n"); - cs5520_set_pio_mode(drive, 0); + drive->pio_mode = XFER_PIO_0 + 0; + cs5520_set_pio_mode(drive->hwif, drive); } static const struct ide_port_ops cs5520_port_ops = { diff --git a/drivers/ide/cs5530.c b/drivers/ide/cs5530.c index 40bf05eddf6e..4ced40255ad6 100644 --- a/drivers/ide/cs5530.c +++ b/drivers/ide/cs5530.c @@ -41,8 +41,8 @@ static unsigned int cs5530_pio_timings[2][5] = { /** * cs5530_set_pio_mode - set host controller for PIO mode + * @hwif: port * @drive: drive - * @pio: PIO mode number * * Handles setting of PIO mode for the chipset. * @@ -50,10 +50,11 @@ static unsigned int cs5530_pio_timings[2][5] = { * will have valid default PIO timings set up before we get here. */ -static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void cs5530_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - unsigned long basereg = CS5530_BASEREG(drive->hwif); + unsigned long basereg = CS5530_BASEREG(hwif); unsigned int format = (inl(basereg + 4) >> 31) & 1; + const u8 pio = drive->pio_mode - XFER_PIO_0; outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3)); } diff --git a/drivers/ide/cs5535.c b/drivers/ide/cs5535.c index b883838adc24..7974415ea89f 100644 --- a/drivers/ide/cs5535.c +++ b/drivers/ide/cs5535.c @@ -142,15 +142,15 @@ static void cs5535_set_dma_mode(ide_drive_t *drive, const u8 speed) /** * cs5535_set_pio_mode - set host controller for PIO mode + * @hwif: port * @drive: drive - * @pio: PIO mode number * * A callback from the upper layers for PIO-only tuning. */ -static void cs5535_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void cs5535_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - cs5535_set_speed(drive, XFER_PIO_0 + pio); + cs5535_set_speed(drive, drive->pio_mode); } static u8 cs5535_cable_detect(ide_hwif_t *hwif) diff --git a/drivers/ide/cs5536.c b/drivers/ide/cs5536.c index 9623b852c616..b518ef0e9a35 100644 --- a/drivers/ide/cs5536.c +++ b/drivers/ide/cs5536.c @@ -125,11 +125,11 @@ static u8 cs5536_cable_detect(ide_hwif_t *hwif) /** * cs5536_set_pio_mode - PIO timing setup + * @hwif: ATA port * @drive: ATA device - * @pio: PIO mode number */ -static void cs5536_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void cs5536_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { static const u8 drv_timings[5] = { 0x98, 0x55, 0x32, 0x21, 0x20, @@ -143,11 +143,12 @@ static void cs5536_set_pio_mode(ide_drive_t *drive, const u8 pio) 0x99, 0x92, 0x90, 0x22, 0x20, }; - struct pci_dev *pdev = to_pci_dev(drive->hwif->dev); + struct pci_dev *pdev = to_pci_dev(hwif->dev); ide_drive_t *pair = ide_get_pair_dev(drive); int cshift = (drive->dn & 1) ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT; unsigned long timings = (unsigned long)ide_get_drivedata(drive); u32 cast; + const u8 pio = drive->pio_mode - XFER_PIO_0; u8 cmd_pio = pio; if (pair) diff --git a/drivers/ide/cy82c693.c b/drivers/ide/cy82c693.c index fbf3dcc26577..ead65c394f00 100644 --- a/drivers/ide/cy82c693.c +++ b/drivers/ide/cy82c693.c @@ -80,9 +80,8 @@ static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode) outb(data, CY82_DATA_PORT); } -static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void cy82c693_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); int bus_speed = ide_pci_clk ? ide_pci_clk : 33; const unsigned long T = 1000000 / bus_speed; @@ -101,7 +100,7 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) } } - ide_timing_compute(drive, XFER_PIO_0 + pio, &t, T, 1); + ide_timing_compute(drive, drive->pio_mode, &t, T, 1); time_16 = clamp_val(t.recover - 1, 0, 15) | (clamp_val(t.active - 1, 0, 15) << 4); diff --git a/drivers/ide/dtc2278.c b/drivers/ide/dtc2278.c index c6b138122981..6929f7fce93a 100644 --- a/drivers/ide/dtc2278.c +++ b/drivers/ide/dtc2278.c @@ -68,11 +68,11 @@ static void sub22 (char b, char c) static DEFINE_SPINLOCK(dtc2278_lock); -static void dtc2278_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void dtc2278_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { unsigned long flags; - if (pio >= 3) { + if (drive->pio_mode >= XFER_PIO_3) { spin_lock_irqsave(&dtc2278_lock, flags); /* * This enables PIO mode4 (3?) on the first interface diff --git a/drivers/ide/hpt366.c b/drivers/ide/hpt366.c index 4d90ac2dbb1b..f1dec519a9e6 100644 --- a/drivers/ide/hpt366.c +++ b/drivers/ide/hpt366.c @@ -651,9 +651,9 @@ static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed) pci_write_config_dword(dev, itr_addr, new_itr); } -static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - hpt3xx_set_mode(drive, XFER_PIO_0 + pio); + hpt3xx_set_mode(drive, drive->pio_mode); } static void hpt3xx_maskproc(ide_drive_t *drive, int mask) diff --git a/drivers/ide/ht6560b.c b/drivers/ide/ht6560b.c index aafed8060e17..d81e49680c3f 100644 --- a/drivers/ide/ht6560b.c +++ b/drivers/ide/ht6560b.c @@ -279,9 +279,10 @@ static void ht_set_prefetch(ide_drive_t *drive, u8 state) #endif } -static void ht6560b_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void ht6560b_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { unsigned long flags, config; + const u8 pio = drive->pio_mode - XFER_PIO_0; u8 timing; switch (pio) { diff --git a/drivers/ide/ide-devsets.c b/drivers/ide/ide-devsets.c index cb3341ce655c..c6935c78757c 100644 --- a/drivers/ide/ide-devsets.c +++ b/drivers/ide/ide-devsets.c @@ -112,10 +112,10 @@ static int set_pio_mode(ide_drive_t *drive, int arg) /* take lock for IDE_DFLAG_[NO_]UNMASK/[NO_]IO_32BIT */ spin_lock_irqsave(&hwif->lock, flags); - port_ops->set_pio_mode(drive, arg); + port_ops->set_pio_mode(hwif, drive); spin_unlock_irqrestore(&hwif->lock, flags); } else - port_ops->set_pio_mode(drive, arg); + port_ops->set_pio_mode(hwif, drive); } else { int keep_dma = !!(drive->dev_flags & IDE_DFLAG_USING_DMA); diff --git a/drivers/ide/ide-xfer-mode.c b/drivers/ide/ide-xfer-mode.c index c2323869d92a..a62fb03fc1cc 100644 --- a/drivers/ide/ide-xfer-mode.c +++ b/drivers/ide/ide-xfer-mode.c @@ -136,7 +136,7 @@ int ide_set_pio_mode(ide_drive_t *drive, const u8 mode) */ if (port_ops->set_dma_mode == NULL) { drive->pio_mode = mode; - port_ops->set_pio_mode(drive, mode - XFER_PIO_0); + port_ops->set_pio_mode(hwif, drive); return 0; } @@ -144,11 +144,11 @@ int ide_set_pio_mode(ide_drive_t *drive, const u8 mode) if (ide_config_drive_speed(drive, mode)) return -1; drive->pio_mode = mode; - port_ops->set_pio_mode(drive, mode - XFER_PIO_0); + port_ops->set_pio_mode(hwif, drive); return 0; } else { drive->pio_mode = mode; - port_ops->set_pio_mode(drive, mode - XFER_PIO_0); + port_ops->set_pio_mode(hwif, drive); return ide_config_drive_speed(drive, mode); } } diff --git a/drivers/ide/it8172.c b/drivers/ide/it8172.c index 0d266a5b524d..9dfdc8741a7b 100644 --- a/drivers/ide/it8172.c +++ b/drivers/ide/it8172.c @@ -37,12 +37,12 @@ #define DRV_NAME "IT8172" -static void it8172_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void it8172_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); u16 drive_enables; u32 drive_timing; + const u8 pio = drive->pio_mode - XFER_PIO_0; /* * The highest value of DIOR/DIOW pulse width and recovery time @@ -98,14 +98,14 @@ static void it8172_set_dma_mode(ide_drive_t *drive, const u8 speed) pci_write_config_byte(dev, 0x4a, reg4a | u_speed); } else { const u8 mwdma_to_pio[] = { 0, 3, 4 }; - u8 pio; pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed); - pio = mwdma_to_pio[speed - XFER_MW_DMA_0]; + drive->pio_mode = + mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0; - it8172_set_pio_mode(drive, pio); + it8172_set_pio_mode(hwif, drive); } } diff --git a/drivers/ide/it8213.c b/drivers/ide/it8213.c index 47976167796a..492c07d5f4f3 100644 --- a/drivers/ide/it8213.c +++ b/drivers/ide/it8213.c @@ -17,15 +17,14 @@ /** * it8213_set_pio_mode - set host controller for PIO mode + * @hwif: port * @drive: drive - * @pio: PIO mode number * * Set the interface PIO mode. */ -static void it8213_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void it8213_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); int is_slave = drive->dn & 1; int master_port = 0x40; @@ -35,6 +34,7 @@ static void it8213_set_pio_mode(ide_drive_t *drive, const u8 pio) u8 slave_data; static DEFINE_SPINLOCK(tune_lock); int control = 0; + const u8 pio = drive->pio_mode - XFER_PIO_0; static const u8 timings[][2] = { { 0, 0 }, @@ -120,7 +120,6 @@ static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed) pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); } else { const u8 mwdma_to_pio[] = { 0, 3, 4 }; - u8 pio; if (reg48 & u_flag) pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); @@ -132,11 +131,12 @@ static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed) pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); if (speed >= XFER_MW_DMA_0) - pio = mwdma_to_pio[speed - XFER_MW_DMA_0]; + drive->pio_mode = + mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0; else - pio = 2; /* only SWDMA2 is allowed */ + drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */ - it8213_set_pio_mode(drive, pio); + it8213_set_pio_mode(hwif, drive); } } diff --git a/drivers/ide/it821x.c b/drivers/ide/it821x.c index 51aa745246dc..69becb7b9656 100644 --- a/drivers/ide/it821x.c +++ b/drivers/ide/it821x.c @@ -228,18 +228,18 @@ static void it821x_clock_strategy(ide_drive_t *drive) /** * it821x_set_pio_mode - set host controller for PIO mode + * @hwif: port * @drive: drive - * @pio: PIO mode number * * Tune the host to the desired PIO mode taking into the consideration * the maximum PIO mode supported by the other device on the cable. */ -static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void it821x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct it821x_dev *itdev = ide_get_hwifdata(hwif); ide_drive_t *pair = ide_get_pair_dev(drive); + const u8 pio = drive->pio_mode - XFER_PIO_0; u8 unit = drive->dn & 1, set_pio = pio; /* Spec says 89 ref driver uses 88 */ diff --git a/drivers/ide/jmicron.c b/drivers/ide/jmicron.c index bf2be6431b20..ebffb904ed24 100644 --- a/drivers/ide/jmicron.c +++ b/drivers/ide/jmicron.c @@ -80,7 +80,7 @@ static u8 jmicron_cable_detect(ide_hwif_t *hwif) return ATA_CBL_PATA80; } -static void jmicron_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void jmicron_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { } diff --git a/drivers/ide/opti621.c b/drivers/ide/opti621.c index 2052788fab7a..1a53a4c375ed 100644 --- a/drivers/ide/opti621.c +++ b/drivers/ide/opti621.c @@ -62,12 +62,12 @@ static u8 read_reg(int reg) return ret; } -static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void opti621_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; ide_drive_t *pair = ide_get_pair_dev(drive); unsigned long flags; - unsigned long mode = XFER_PIO_0 + pio, pair_mode; + unsigned long mode = drive->pio_mode, pair_mode; + const u8 pio = mode - XFER_PIO_0; u8 tim, misc, addr_pio = pio, clk; /* DRDY is default 2 (by OPTi Databook) */ diff --git a/drivers/ide/palm_bk3710.c b/drivers/ide/palm_bk3710.c index f8eddf05ecb8..0f262d07c378 100644 --- a/drivers/ide/palm_bk3710.c +++ b/drivers/ide/palm_bk3710.c @@ -203,12 +203,13 @@ static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed) } } -static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio) +static void palm_bk3710_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { unsigned int cycle_time; int is_slave = drive->dn & 1; ide_drive_t *mate; - void __iomem *base = (void *)drive->hwif->dma_base; + void __iomem *base = (void *)hwif->dma_base; + const u8 pio = drive->pio_mode - XFER_PIO_0; /* * Obtain the drive PIO data for tuning the Palm Chip registers diff --git a/drivers/ide/pdc202xx_new.c b/drivers/ide/pdc202xx_new.c index 65ba8239e7b5..874acd2bb6e6 100644 --- a/drivers/ide/pdc202xx_new.c +++ b/drivers/ide/pdc202xx_new.c @@ -167,11 +167,11 @@ static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed) } } -static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void pdcnew_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); u8 adj = (drive->dn & 1) ? 0x08 : 0x00; + const u8 pio = drive->pio_mode - XFER_PIO_0; if (max_dma_rate(dev) == 4) { set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c); diff --git a/drivers/ide/pdc202xx_old.c b/drivers/ide/pdc202xx_old.c index 1d20594ee420..402aab7f3baa 100644 --- a/drivers/ide/pdc202xx_old.c +++ b/drivers/ide/pdc202xx_old.c @@ -76,9 +76,9 @@ static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) } } -static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void pdc202xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - pdc202xx_set_mode(drive, XFER_PIO_0 + pio); + pdc202xx_set_mode(drive, drive->pio_mode); } static int pdc202xx_test_irq(ide_hwif_t *hwif) diff --git a/drivers/ide/piix.c b/drivers/ide/piix.c index bf14f39bd3a7..64b3041daa60 100644 --- a/drivers/ide/piix.c +++ b/drivers/ide/piix.c @@ -59,15 +59,14 @@ static int no_piix_dma; /** * piix_set_pio_mode - set host controller for PIO mode + * @port: port * @drive: drive - * @pio: PIO mode number * * Set the interface PIO mode based upon the settings done by AMI BIOS. */ -static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void piix_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); int is_slave = drive->dn & 1; int master_port = hwif->channel ? 0x42 : 0x40; @@ -77,6 +76,7 @@ static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio) u8 slave_data; static DEFINE_SPINLOCK(tune_lock); int control = 0; + const u8 pio = drive->pio_mode - XFER_PIO_0; /* ISP RTC */ static const u8 timings[][2]= { @@ -176,7 +176,6 @@ static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed) pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); } else { const u8 mwdma_to_pio[] = { 0, 3, 4 }; - u8 pio; if (reg48 & u_flag) pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); @@ -188,11 +187,12 @@ static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed) pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); if (speed >= XFER_MW_DMA_0) - pio = mwdma_to_pio[speed - XFER_MW_DMA_0]; + drive->pio_mode = + mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0; else - pio = 2; /* only SWDMA2 is allowed */ + drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */ - piix_set_pio_mode(drive, pio); + piix_set_pio_mode(hwif, drive); } } diff --git a/drivers/ide/pmac.c b/drivers/ide/pmac.c index 7a4e788cab2f..a167968a2d42 100644 --- a/drivers/ide/pmac.c +++ b/drivers/ide/pmac.c @@ -496,12 +496,11 @@ static void pmac_write_devctl(ide_hwif_t *hwif, u8 ctl) /* * Old tuning functions (called on hdparm -p), sets up drive PIO timings */ -static void -pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void pmac_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); + const u8 pio = drive->pio_mode - XFER_PIO_0; struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio); u32 *timings, t; unsigned accessTicks, recTicks; diff --git a/drivers/ide/qd65xx.c b/drivers/ide/qd65xx.c index 74696edc8d1d..3f0244fd8e62 100644 --- a/drivers/ide/qd65xx.c +++ b/drivers/ide/qd65xx.c @@ -189,15 +189,13 @@ static void qd_set_timing (ide_drive_t *drive, u8 timing) printk(KERN_DEBUG "%s: %#x\n", drive->name, timing); } -static void qd6500_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void qd6500_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { u16 *id = drive->id; int active_time = 175; int recovery_time = 415; /* worst case values from the dos driver */ - /* - * FIXME: use "pio" value - */ + /* FIXME: use drive->pio_mode value */ if (!qd_find_disk_type(drive, &active_time, &recovery_time) && (id[ATA_ID_OLD_PIO_MODES] & 0xff) && (id[ATA_ID_FIELD_VALID] & 2) && id[ATA_ID_EIDE_PIO] >= 240) { @@ -211,9 +209,9 @@ static void qd6500_set_pio_mode(ide_drive_t *drive, const u8 pio) active_time, recovery_time)); } -static void qd6580_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void qd6580_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; + const u8 pio = drive->pio_mode - XFER_PIO_0; struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); unsigned int cycle_time; int active_time = 175; diff --git a/drivers/ide/sc1200.c b/drivers/ide/sc1200.c index d467478d68da..bb0166e460ab 100644 --- a/drivers/ide/sc1200.c +++ b/drivers/ide/sc1200.c @@ -193,10 +193,10 @@ static int sc1200_dma_end(ide_drive_t *drive) * will have valid default PIO timings set up before we get here. */ -static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void sc1200_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; int mode = -1; + const u8 pio = drive->pio_mode - XFER_PIO_0; /* * bad abuse of ->set_pio_mode interface diff --git a/drivers/ide/scc_pata.c b/drivers/ide/scc_pata.c index 1104bb301eb9..23e16e4460ee 100644 --- a/drivers/ide/scc_pata.c +++ b/drivers/ide/scc_pata.c @@ -199,16 +199,15 @@ scc_ide_outsl(unsigned long port, void *addr, u32 count) /** * scc_set_pio_mode - set host controller for PIO mode + * @hwif: port * @drive: drive - * @pio: PIO mode number * * Load the timing settings for this device mode into the * controller. */ -static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void scc_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct scc_ports *ports = ide_get_hwifdata(hwif); unsigned long ctl_base = ports->ctl; unsigned long cckctrl_port = ctl_base + 0xff0; @@ -216,6 +215,7 @@ static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio) unsigned long pioct_port = ctl_base + 0x004; unsigned long reg; int offset; + const u8 pio = drive->pio_mode - XFER_PIO_0; reg = in_be32((void __iomem *)cckctrl_port); if (reg & CCKCTRL_ATACLKOEN) { diff --git a/drivers/ide/serverworks.c b/drivers/ide/serverworks.c index 657f0433ec50..a56bc51ae032 100644 --- a/drivers/ide/serverworks.c +++ b/drivers/ide/serverworks.c @@ -106,12 +106,13 @@ static u8 svwks_csb_check (struct pci_dev *dev) return 0; } -static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void svwks_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 }; - struct pci_dev *dev = to_pci_dev(drive->hwif->dev); + struct pci_dev *dev = to_pci_dev(hwif->dev); + const u8 pio = drive->pio_mode - XFER_PIO_0; pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]); diff --git a/drivers/ide/siimage.c b/drivers/ide/siimage.c index d95df528562f..97266958f744 100644 --- a/drivers/ide/siimage.c +++ b/drivers/ide/siimage.c @@ -229,19 +229,18 @@ static u8 sil_sata_udma_filter(ide_drive_t *drive) /** * sil_set_pio_mode - set host controller for PIO mode + * @hwif: port * @drive: drive - * @pio: PIO mode number * * Load the timing settings for this device mode into the * controller. */ -static void sil_set_pio_mode(ide_drive_t *drive, u8 pio) +static void sil_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); ide_drive_t *pair = ide_get_pair_dev(drive); u32 speedt = 0; @@ -249,6 +248,7 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio) unsigned long addr = siimage_seldev(drive, 0x04); unsigned long tfaddr = siimage_selreg(hwif, 0x02); unsigned long base = (unsigned long)hwif->hwif_data; + const u8 pio = drive->pio_mode - XFER_PIO_0; u8 tf_pio = pio; u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) diff --git a/drivers/ide/sis5513.c b/drivers/ide/sis5513.c index 468706082fb5..5a0192060531 100644 --- a/drivers/ide/sis5513.c +++ b/drivers/ide/sis5513.c @@ -290,10 +290,10 @@ static void config_drive_art_rwp(ide_drive_t *drive) pci_write_config_byte(dev, 0x4b, rw_prefetch); } -static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void sis_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { config_drive_art_rwp(drive); - sis_program_timings(drive, XFER_PIO_0 + pio); + sis_program_timings(drive, drive->pio_mode); } static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode) diff --git a/drivers/ide/sl82c105.c b/drivers/ide/sl82c105.c index 3c2bbf0057ea..419cd3bc6c84 100644 --- a/drivers/ide/sl82c105.c +++ b/drivers/ide/sl82c105.c @@ -63,12 +63,13 @@ static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio) /* * Configure the chipset for PIO mode. */ -static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void sl82c105_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - struct pci_dev *dev = to_pci_dev(drive->hwif->dev); + struct pci_dev *dev = to_pci_dev(hwif->dev); unsigned long timings = (unsigned long)ide_get_drivedata(drive); int reg = 0x44 + drive->dn * 4; u16 drv_ctrl; + const u8 pio = drive->pio_mode - XFER_PIO_0; drv_ctrl = get_pio_timings(drive, pio); diff --git a/drivers/ide/slc90e66.c b/drivers/ide/slc90e66.c index 1ccfb40e7215..019777522cd2 100644 --- a/drivers/ide/slc90e66.c +++ b/drivers/ide/slc90e66.c @@ -18,9 +18,8 @@ static DEFINE_SPINLOCK(slc90e66_lock); -static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void slc90e66_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); int is_slave = drive->dn & 1; int master_port = hwif->channel ? 0x42 : 0x40; @@ -29,6 +28,8 @@ static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio) u16 master_data; u8 slave_data; int control = 0; + const u8 pio = drive->pio_mode - XFER_PIO_0; + /* ISP RTC */ static const u8 timings[][2] = { { 0, 0 }, @@ -98,7 +99,6 @@ static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed) } } else { const u8 mwdma_to_pio[] = { 0, 3, 4 }; - u8 pio; if (reg48 & u_flag) pci_write_config_word(dev, 0x48, reg48 & ~u_flag); @@ -106,11 +106,12 @@ static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed) pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); if (speed >= XFER_MW_DMA_0) - pio = mwdma_to_pio[speed - XFER_MW_DMA_0]; + drive->pio_mode = + mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0; else - pio = 2; /* only SWDMA2 is allowed */ + drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */ - slc90e66_set_pio_mode(drive, pio); + slc90e66_set_pio_mode(hwif, drive); } } diff --git a/drivers/ide/tc86c001.c b/drivers/ide/tc86c001.c index 05a93d6baecc..f2cb62bf3f22 100644 --- a/drivers/ide/tc86c001.c +++ b/drivers/ide/tc86c001.c @@ -41,9 +41,9 @@ static void tc86c001_set_mode(ide_drive_t *drive, const u8 speed) outw(scr, scr_port); } -static void tc86c001_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void tc86c001_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - tc86c001_set_mode(drive, XFER_PIO_0 + pio); + tc86c001_set_mode(drive, drive->pio_mode); } /* diff --git a/drivers/ide/triflex.c b/drivers/ide/triflex.c index 8773c3ba7462..d34a7eecdea5 100644 --- a/drivers/ide/triflex.c +++ b/drivers/ide/triflex.c @@ -82,9 +82,9 @@ static void triflex_set_mode(ide_drive_t *drive, const u8 speed) pci_write_config_dword(dev, channel_offset, triflex_timings); } -static void triflex_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void triflex_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - triflex_set_mode(drive, XFER_PIO_0 + pio); + triflex_set_mode(drive, drive->pio_mode); } static const struct ide_port_ops triflex_port_ops = { diff --git a/drivers/ide/tx4938ide.c b/drivers/ide/tx4938ide.c index fd59c0d235b5..326d4683488b 100644 --- a/drivers/ide/tx4938ide.c +++ b/drivers/ide/tx4938ide.c @@ -56,11 +56,10 @@ static void tx4938ide_tune_ebusc(unsigned int ebus_ch, &tx4938_ebuscptr->cr[ebus_ch]); } -static void tx4938ide_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void tx4938ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct tx4938ide_platform_info *pdata = hwif->dev->platform_data; - u8 safe = pio; + u8 safe = drive->pio_mode - XFER_PIO_0; ide_drive_t *pair; pair = ide_get_pair_dev(drive); diff --git a/drivers/ide/tx4939ide.c b/drivers/ide/tx4939ide.c index 64b58ecc3f0e..5228a4786de5 100644 --- a/drivers/ide/tx4939ide.c +++ b/drivers/ide/tx4939ide.c @@ -104,11 +104,11 @@ static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg) #define TX4939IDE_BASE(hwif) ((void __iomem *)(hwif)->extra_base) -static void tx4939ide_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void tx4939ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; int is_slave = drive->dn; u32 mask, val; + const u8 pio = drive->pio_mode - XFER_PIO_0; u8 safe = pio; ide_drive_t *pair; diff --git a/drivers/ide/umc8672.c b/drivers/ide/umc8672.c index 60f936e2319c..47adcd09cb26 100644 --- a/drivers/ide/umc8672.c +++ b/drivers/ide/umc8672.c @@ -104,10 +104,11 @@ static void umc_set_speeds(u8 speeds[]) speeds[0], speeds[1], speeds[2], speeds[3]); } -static void umc_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void umc_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif, *mate = hwif->mate; + ide_hwif_t *mate = hwif->mate; unsigned long uninitialized_var(flags); + const u8 pio = drive->pio_mode - XFER_PIO_0; printk("%s: setting umc8672 to PIO mode%d (speed %d)\n", drive->name, pio, pio_to_umc[pio]); diff --git a/drivers/ide/via82cxxx.c b/drivers/ide/via82cxxx.c index fbecf8ea8207..6d995fc9d4f5 100644 --- a/drivers/ide/via82cxxx.c +++ b/drivers/ide/via82cxxx.c @@ -208,15 +208,15 @@ static void via_set_drive(ide_drive_t *drive, const u8 speed) /** * via_set_pio_mode - set host controller for PIO mode + * @hwif: port * @drive: drive - * @pio: PIO mode number * * A callback from the upper layers for PIO-only tuning. */ -static void via_set_pio_mode(ide_drive_t *drive, const u8 pio) +static void via_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - via_set_drive(drive, XFER_PIO_0 + pio); + via_set_drive(drive, drive->pio_mode); } static struct via_isa_bridge *via_config_find(struct pci_dev **isa) diff --git a/include/linux/ide.h b/include/linux/ide.h index 746ef9fdabcb..803ec306883c 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -624,7 +624,7 @@ extern const struct ide_tp_ops default_tp_ops; */ struct ide_port_ops { void (*init_dev)(ide_drive_t *); - void (*set_pio_mode)(ide_drive_t *, const u8); + void (*set_pio_mode)(struct hwif_s *, ide_drive_t *); void (*set_dma_mode)(ide_drive_t *, const u8); int (*reset_poll)(ide_drive_t *); void (*pre_reset)(ide_drive_t *); -- cgit v1.2.3 From 8776168ca2151850164af1de5565d01f7b8b2c53 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Tue, 19 Jan 2010 01:45:29 -0800 Subject: ide: change ->set_dma_mode method parameters Change ->set_dma_mode method parameters to match ->set_dmamode method used in struct ata_port_operations. Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ide/aec62xx.c | 10 +++++----- drivers/ide/alim15x3.c | 6 +++--- drivers/ide/amd74xx.c | 7 ++++--- drivers/ide/atiixp.c | 7 ++++--- drivers/ide/au1xxx-ide.c | 4 ++-- drivers/ide/cmd64x.c | 4 ++-- drivers/ide/cs5520.c | 4 ++-- drivers/ide/cs5530.c | 6 +++--- drivers/ide/cs5535.c | 6 +++--- drivers/ide/cs5536.c | 7 ++++--- drivers/ide/cy82c693.c | 4 ++-- drivers/ide/hpt366.c | 7 ++++--- drivers/ide/icside.c | 3 ++- drivers/ide/ide-xfer-mode.c | 4 ++-- drivers/ide/it8172.c | 4 ++-- drivers/ide/it8213.c | 6 +++--- drivers/ide/it821x.c | 6 ++++-- drivers/ide/jmicron.c | 4 ++-- drivers/ide/palm_bk3710.c | 5 +++-- drivers/ide/pdc202xx_new.c | 4 ++-- drivers/ide/pdc202xx_old.c | 7 ++++--- drivers/ide/piix.c | 6 +++--- drivers/ide/pmac.c | 4 ++-- drivers/ide/sc1200.c | 4 ++-- drivers/ide/scc_pata.c | 6 +++--- drivers/ide/serverworks.c | 4 ++-- drivers/ide/sgiioc4.c | 2 +- drivers/ide/siimage.c | 6 +++--- drivers/ide/sis5513.c | 4 +++- drivers/ide/sl82c105.c | 3 ++- drivers/ide/slc90e66.c | 4 ++-- drivers/ide/tc86c001.c | 7 ++++--- drivers/ide/triflex.c | 8 ++++---- drivers/ide/tx4939ide.c | 4 ++-- drivers/ide/via82cxxx.c | 9 +++++---- include/linux/ide.h | 2 +- 36 files changed, 101 insertions(+), 87 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/aec62xx.c b/drivers/ide/aec62xx.c index 3790847361c3..57d00caefc86 100644 --- a/drivers/ide/aec62xx.c +++ b/drivers/ide/aec62xx.c @@ -81,15 +81,15 @@ static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entr return chipset_table->ultra_settings; } -static void aec6210_set_mode(ide_drive_t *drive, const u8 speed) +static void aec6210_set_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); struct ide_host *host = pci_get_drvdata(dev); struct chipset_bus_clock_list_entry *bus_clock = host->host_priv; u16 d_conf = 0; u8 ultra = 0, ultra_conf = 0; u8 tmp0 = 0, tmp1 = 0, tmp2 = 0; + const u8 speed = drive->dma_mode; unsigned long flags; local_irq_save(flags); @@ -109,15 +109,15 @@ static void aec6210_set_mode(ide_drive_t *drive, const u8 speed) local_irq_restore(flags); } -static void aec6260_set_mode(ide_drive_t *drive, const u8 speed) +static void aec6260_set_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); struct ide_host *host = pci_get_drvdata(dev); struct chipset_bus_clock_list_entry *bus_clock = host->host_priv; u8 unit = drive->dn & 1; u8 tmp1 = 0, tmp2 = 0; u8 ultra = 0, drive_conf = 0, ultra_conf = 0; + const u8 speed = drive->dma_mode; unsigned long flags; local_irq_save(flags); @@ -137,7 +137,7 @@ static void aec6260_set_mode(ide_drive_t *drive, const u8 speed) static void aec_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { drive->dma_mode = drive->pio_mode; - hwif->port_ops->set_dma_mode(drive, drive->dma_mode); + hwif->port_ops->set_dma_mode(hwif, drive); } static int init_chipset_aec62xx(struct pci_dev *dev) diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c index 28cee1055f76..6f0debae4e27 100644 --- a/drivers/ide/alim15x3.c +++ b/drivers/ide/alim15x3.c @@ -121,16 +121,16 @@ static u8 ali_udma_filter(ide_drive_t *drive) /** * ali_set_dma_mode - set host controller for DMA mode + * @hwif: port * @drive: drive - * @speed: DMA mode * * Configure the hardware for the desired IDE transfer mode. */ -static void ali_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); + const u8 speed = drive->dma_mode; u8 speed1 = speed; u8 unit = drive->dn & 1; u8 tmpbyte = 0x00; diff --git a/drivers/ide/amd74xx.c b/drivers/ide/amd74xx.c index 3eee7be7ca6f..b7e105338205 100644 --- a/drivers/ide/amd74xx.c +++ b/drivers/ide/amd74xx.c @@ -79,14 +79,14 @@ static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask, * to a desired transfer mode. It also can be called by upper layers. */ -static void amd_set_drive(ide_drive_t *drive, const u8 speed) +static void amd_set_drive(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); ide_drive_t *peer = ide_get_pair_dev(drive); struct ide_timing t, p; int T, UT; u8 udma_mask = hwif->ultra_mask; + const u8 speed = drive->dma_mode; T = 1000000000 / amd_clock; UT = (udma_mask == ATA_UDMA2) ? T : (T / 2); @@ -110,7 +110,8 @@ static void amd_set_drive(ide_drive_t *drive, const u8 speed) static void amd_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - amd_set_drive(drive, drive->pio_mode); + drive->dma_mode = drive->pio_mode; + amd_set_drive(hwif, drive); } static void amd7409_cable_detect(struct pci_dev *dev) diff --git a/drivers/ide/atiixp.c b/drivers/ide/atiixp.c index b6848dfb93b0..15f0ead89f5c 100644 --- a/drivers/ide/atiixp.c +++ b/drivers/ide/atiixp.c @@ -75,21 +75,22 @@ static void atiixp_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) /** * atiixp_set_dma_mode - set host controller for DMA mode + * @hwif: port * @drive: drive - * @speed: DMA mode * * Set a ATIIXP host controller to the desired DMA mode. This involves * programming the right timing data into the PCI configuration space. */ -static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void atiixp_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - struct pci_dev *dev = to_pci_dev(drive->hwif->dev); + struct pci_dev *dev = to_pci_dev(hwif->dev); unsigned long flags; int timing_shift = (drive->dn ^ 1) * 8; u32 tmp32; u16 tmp16; u16 udma_ctl = 0; + const u8 speed = drive->dma_mode; spin_lock_irqsave(&atiixp_lock, flags); diff --git a/drivers/ide/au1xxx-ide.c b/drivers/ide/au1xxx-ide.c index c90e9b0a9f6e..e2fd378ba9de 100644 --- a/drivers/ide/au1xxx-ide.c +++ b/drivers/ide/au1xxx-ide.c @@ -160,11 +160,11 @@ static void au1xxx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) au_writel(mem_stcfg,MEM_STCFG2); } -static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void auide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); - switch(speed) { + switch (drive->dma_mode) { #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA case XFER_MW_DMA_2: mem_sttime = SBC_IDE_TIMING(MDMA2); diff --git a/drivers/ide/cmd64x.c b/drivers/ide/cmd64x.c index 0b11745937e7..a65a69171250 100644 --- a/drivers/ide/cmd64x.c +++ b/drivers/ide/cmd64x.c @@ -141,12 +141,12 @@ static void cmd64x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) cmd64x_program_timings(drive, XFER_PIO_0 + pio); } -static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void cmd64x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); u8 unit = drive->dn & 0x01; u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0; + const u8 speed = drive->dma_mode; pci_read_config_byte(dev, pciU, ®U); regU &= ~(unit ? 0xCA : 0x35); diff --git a/drivers/ide/cs5520.c b/drivers/ide/cs5520.c index b8094f049f3e..2c1e5f7cd261 100644 --- a/drivers/ide/cs5520.c +++ b/drivers/ide/cs5520.c @@ -81,12 +81,12 @@ static void cs5520_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) (cs5520_pio_clocks[pio].assert)); } -static void cs5520_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void cs5520_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { printk(KERN_ERR "cs55x0: bad ide timing.\n"); drive->pio_mode = XFER_PIO_0 + 0; - cs5520_set_pio_mode(drive->hwif, drive); + cs5520_set_pio_mode(hwif, drive); } static const struct ide_port_ops cs5520_port_ops = { diff --git a/drivers/ide/cs5530.c b/drivers/ide/cs5530.c index 4ced40255ad6..4dc4eb92b076 100644 --- a/drivers/ide/cs5530.c +++ b/drivers/ide/cs5530.c @@ -100,12 +100,12 @@ out: return mask; } -static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode) +static void cs5530_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { unsigned long basereg; unsigned int reg, timings = 0; - switch (mode) { + switch (drive->dma_mode) { case XFER_UDMA_0: timings = 0x00921250; break; case XFER_UDMA_1: timings = 0x00911140; break; case XFER_UDMA_2: timings = 0x00911030; break; @@ -113,7 +113,7 @@ static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode) case XFER_MW_DMA_1: timings = 0x00012121; break; case XFER_MW_DMA_2: timings = 0x00002020; break; } - basereg = CS5530_BASEREG(drive->hwif); + basereg = CS5530_BASEREG(hwif); reg = inl(basereg + 4); /* get drive0 config register */ timings |= reg & 0x80000000; /* preserve PIO format bit */ if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */ diff --git a/drivers/ide/cs5535.c b/drivers/ide/cs5535.c index 7974415ea89f..740002b2f3e8 100644 --- a/drivers/ide/cs5535.c +++ b/drivers/ide/cs5535.c @@ -129,15 +129,15 @@ static void cs5535_set_speed(ide_drive_t *drive, const u8 speed) /** * cs5535_set_dma_mode - set host controller for DMA mode + * @hwif: port * @drive: drive - * @speed: DMA mode * * Programs the chipset for DMA mode. */ -static void cs5535_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void cs5535_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - cs5535_set_speed(drive, speed); + cs5535_set_speed(drive, drive->dma_mode); } /** diff --git a/drivers/ide/cs5536.c b/drivers/ide/cs5536.c index b518ef0e9a35..70871fbc3c0a 100644 --- a/drivers/ide/cs5536.c +++ b/drivers/ide/cs5536.c @@ -173,11 +173,11 @@ static void cs5536_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) /** * cs5536_set_dma_mode - DMA timing setup + * @hwif: ATA port * @drive: ATA device - * @mode: DMA mode */ -static void cs5536_set_dma_mode(ide_drive_t *drive, const u8 mode) +static void cs5536_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { static const u8 udma_timings[6] = { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, @@ -187,10 +187,11 @@ static void cs5536_set_dma_mode(ide_drive_t *drive, const u8 mode) 0x67, 0x21, 0x20, }; - struct pci_dev *pdev = to_pci_dev(drive->hwif->dev); + struct pci_dev *pdev = to_pci_dev(hwif->dev); int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT; unsigned long timings = (unsigned long)ide_get_drivedata(drive); u32 etc; + const u8 mode = drive->dma_mode; cs5536_read(pdev, ETC, &etc); diff --git a/drivers/ide/cy82c693.c b/drivers/ide/cy82c693.c index ead65c394f00..9383f67deae1 100644 --- a/drivers/ide/cy82c693.c +++ b/drivers/ide/cy82c693.c @@ -53,9 +53,9 @@ * set DMA mode a specific channel for CY82C693 */ -static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode) +static void cy82c693_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; + const u8 mode = drive->dma_mode; u8 single = (mode & 0x10) >> 4, index = 0, data = 0; index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0; diff --git a/drivers/ide/hpt366.c b/drivers/ide/hpt366.c index f1dec519a9e6..b885c1d548f5 100644 --- a/drivers/ide/hpt366.c +++ b/drivers/ide/hpt366.c @@ -627,14 +627,14 @@ static u32 get_speed_setting(u8 speed, struct hpt_info *info) return info->timings->clock_table[info->clock][i]; } -static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed) +static void hpt3xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); struct hpt_info *info = hpt3xx_get_info(hwif->dev); struct hpt_timings *t = info->timings; u8 itr_addr = 0x40 + (drive->dn * 4); u32 old_itr = 0; + const u8 speed = drive->dma_mode; u32 new_itr = get_speed_setting(speed, info); u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask : (speed < XFER_UDMA_0 ? t->dma_mask : @@ -653,7 +653,8 @@ static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed) static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - hpt3xx_set_mode(drive, drive->pio_mode); + drive->dma_mode = drive->pio_mode; + hpt3xx_set_mode(hwif, drive); } static void hpt3xx_maskproc(ide_drive_t *drive, int mask) diff --git a/drivers/ide/icside.c b/drivers/ide/icside.c index 0f67f1abbbd3..26b6c0a1f772 100644 --- a/drivers/ide/icside.c +++ b/drivers/ide/icside.c @@ -185,10 +185,11 @@ static const expansioncard_ops_t icside_ops_arcin_v6 = { * MW1 80 50 50 150 C * MW2 70 25 25 120 C */ -static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode) +static void icside_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { unsigned long cycle_time; int use_dma_info = 0; + const u8 xfer_mode = drive->dma_mode; switch (xfer_mode) { case XFER_MW_DMA_2: diff --git a/drivers/ide/ide-xfer-mode.c b/drivers/ide/ide-xfer-mode.c index a62fb03fc1cc..9b549e4d1848 100644 --- a/drivers/ide/ide-xfer-mode.c +++ b/drivers/ide/ide-xfer-mode.c @@ -168,11 +168,11 @@ int ide_set_dma_mode(ide_drive_t *drive, const u8 mode) if (ide_config_drive_speed(drive, mode)) return -1; drive->dma_mode = mode; - port_ops->set_dma_mode(drive, mode); + port_ops->set_dma_mode(hwif, drive); return 0; } else { drive->dma_mode = mode; - port_ops->set_dma_mode(drive, mode); + port_ops->set_dma_mode(hwif, drive); return ide_config_drive_speed(drive, mode); } } diff --git a/drivers/ide/it8172.c b/drivers/ide/it8172.c index 9dfdc8741a7b..560e66d07659 100644 --- a/drivers/ide/it8172.c +++ b/drivers/ide/it8172.c @@ -77,14 +77,14 @@ static void it8172_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) pci_write_config_dword(dev, 0x44, drive_timing); } -static void it8172_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void it8172_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); int a_speed = 3 << (drive->dn * 4); int u_flag = 1 << drive->dn; int u_speed = 0; u8 reg48, reg4a; + const u8 speed = drive->dma_mode; pci_read_config_byte(dev, 0x48, ®48); pci_read_config_byte(dev, 0x4a, ®4a); diff --git a/drivers/ide/it8213.c b/drivers/ide/it8213.c index 492c07d5f4f3..46816ba26416 100644 --- a/drivers/ide/it8213.c +++ b/drivers/ide/it8213.c @@ -74,15 +74,14 @@ static void it8213_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) /** * it8213_set_dma_mode - set host controller for DMA mode + * @hwif: port * @drive: drive - * @speed: DMA mode * * Tune the ITE chipset for the DMA mode. */ -static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void it8213_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); u8 maslave = 0x40; int a_speed = 3 << (drive->dn * 4); @@ -92,6 +91,7 @@ static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed) int u_speed = 0; u16 reg4042, reg4a; u8 reg48, reg54, reg55; + const u8 speed = drive->dma_mode; pci_read_config_word(dev, maslave, ®4042); pci_read_config_byte(dev, 0x48, ®48); diff --git a/drivers/ide/it821x.c b/drivers/ide/it821x.c index 69becb7b9656..56b79194156b 100644 --- a/drivers/ide/it821x.c +++ b/drivers/ide/it821x.c @@ -393,14 +393,16 @@ static int it821x_dma_end(ide_drive_t *drive) /** * it821x_set_dma_mode - set host controller for DMA mode + * @hwif: port * @drive: drive - * @speed: DMA mode * * Tune the ITE chipset for the desired DMA mode. */ -static void it821x_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void it821x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { + const u8 speed = drive->dma_mode; + /* * MWDMA tuning is really hard because our MWDMA and PIO * timings are kept in the same place. We can switch in the diff --git a/drivers/ide/jmicron.c b/drivers/ide/jmicron.c index ebffb904ed24..74c2c4a6d909 100644 --- a/drivers/ide/jmicron.c +++ b/drivers/ide/jmicron.c @@ -86,13 +86,13 @@ static void jmicron_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) /** * jmicron_set_dma_mode - set host controller for DMA mode + * @hwif: port * @drive: drive - * @mode: DMA mode * * As the JMicron snoops for timings we don't need to do anything here. */ -static void jmicron_set_dma_mode(ide_drive_t *drive, const u8 mode) +static void jmicron_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { } diff --git a/drivers/ide/palm_bk3710.c b/drivers/ide/palm_bk3710.c index 0f262d07c378..35448c91b8c8 100644 --- a/drivers/ide/palm_bk3710.c +++ b/drivers/ide/palm_bk3710.c @@ -188,10 +188,11 @@ static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate, writel(val32, base + BK3710_REGRCVR); } -static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed) +static void palm_bk3710_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { int is_slave = drive->dn & 1; - void __iomem *base = (void *)drive->hwif->dma_base; + void __iomem *base = (void *)hwif->dma_base; + const u8 xferspeed = drive->dma_mode; if (xferspeed >= XFER_UDMA_0) { palm_bk3710_setudmamode(base, is_slave, diff --git a/drivers/ide/pdc202xx_new.c b/drivers/ide/pdc202xx_new.c index 874acd2bb6e6..9546fe2a93f7 100644 --- a/drivers/ide/pdc202xx_new.c +++ b/drivers/ide/pdc202xx_new.c @@ -129,11 +129,11 @@ static struct udma_timing { { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ }; -static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void pdcnew_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); u8 adj = (drive->dn & 1) ? 0x08 : 0x00; + const u8 speed = drive->dma_mode; /* * IDE core issues SETFEATURES_XFER to the drive first (thanks to diff --git a/drivers/ide/pdc202xx_old.c b/drivers/ide/pdc202xx_old.c index 402aab7f3baa..07cd37516ba6 100644 --- a/drivers/ide/pdc202xx_old.c +++ b/drivers/ide/pdc202xx_old.c @@ -21,11 +21,11 @@ #define DRV_NAME "pdc202xx_old" -static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) +static void pdc202xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); u8 drive_pci = 0x60 + (drive->dn << 2); + const u8 speed = drive->dma_mode; u8 AP = 0, BP = 0, CP = 0; u8 TA = 0, TB = 0, TC = 0; @@ -78,7 +78,8 @@ static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) static void pdc202xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - pdc202xx_set_mode(drive, drive->pio_mode); + drive->dma_mode = drive->pio_mode; + pdc202xx_set_mode(hwif, drive); } static int pdc202xx_test_irq(ide_hwif_t *hwif) diff --git a/drivers/ide/piix.c b/drivers/ide/piix.c index 64b3041daa60..1bdca49e5a03 100644 --- a/drivers/ide/piix.c +++ b/drivers/ide/piix.c @@ -127,16 +127,15 @@ static void piix_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) /** * piix_set_dma_mode - set host controller for DMA mode + * @hwif: port * @drive: drive - * @speed: DMA mode * * Set a PIIX host controller to the desired DMA mode. This involves * programming the right timing data into the PCI configuration space. */ -static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void piix_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); u8 maslave = hwif->channel ? 0x42 : 0x40; int a_speed = 3 << (drive->dn * 4); @@ -147,6 +146,7 @@ static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed) int sitre; u16 reg4042, reg4a; u8 reg48, reg54, reg55; + const u8 speed = drive->dma_mode; pci_read_config_word(dev, maslave, ®4042); sitre = (reg4042 & 0x4000) ? 1 : 0; diff --git a/drivers/ide/pmac.c b/drivers/ide/pmac.c index a167968a2d42..9fae1fb1468b 100644 --- a/drivers/ide/pmac.c +++ b/drivers/ide/pmac.c @@ -777,14 +777,14 @@ set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2, #endif } -static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void pmac_ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); int ret = 0; u32 *timings, *timings2, tl[2]; u8 unit = drive->dn & 1; + const u8 speed = drive->dma_mode; timings = &pmif->timings[unit]; timings2 = &pmif->timings[unit+2]; diff --git a/drivers/ide/sc1200.c b/drivers/ide/sc1200.c index bb0166e460ab..134f1fd13866 100644 --- a/drivers/ide/sc1200.c +++ b/drivers/ide/sc1200.c @@ -122,13 +122,13 @@ out: return mask; } -static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode) +static void sc1200_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); unsigned int reg, timings; unsigned short pci_clock; unsigned int basereg = hwif->channel ? 0x50 : 0x40; + const u8 mode = drive->dma_mode; static const u32 udma_timing[3][3] = { { 0x00921250, 0x00911140, 0x00911030 }, diff --git a/drivers/ide/scc_pata.c b/drivers/ide/scc_pata.c index 23e16e4460ee..e9d4b441d1c3 100644 --- a/drivers/ide/scc_pata.c +++ b/drivers/ide/scc_pata.c @@ -231,16 +231,15 @@ static void scc_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) /** * scc_set_dma_mode - set host controller for DMA mode + * @hwif: port * @drive: drive - * @speed: DMA mode * * Load the timing settings for this device mode into the * controller. */ -static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void scc_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct scc_ports *ports = ide_get_hwifdata(hwif); unsigned long ctl_base = ports->ctl; unsigned long cckctrl_port = ctl_base + 0xff0; @@ -254,6 +253,7 @@ static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed) int offset, idx; unsigned long reg; unsigned long jcactsel; + const u8 speed = drive->dma_mode; reg = in_be32((void __iomem *)cckctrl_port); if (reg & CCKCTRL_ATACLKOEN) { diff --git a/drivers/ide/serverworks.c b/drivers/ide/serverworks.c index a56bc51ae032..35fb8dabb55d 100644 --- a/drivers/ide/serverworks.c +++ b/drivers/ide/serverworks.c @@ -128,14 +128,14 @@ static void svwks_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) } } -static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void svwks_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 }; static const u8 dma_modes[] = { 0x77, 0x21, 0x20 }; static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 }; - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); + const u8 speed = drive->dma_mode; u8 unit = drive->dn & 1; u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0; diff --git a/drivers/ide/sgiioc4.c b/drivers/ide/sgiioc4.c index b7d61dc64096..e3ea591f66d3 100644 --- a/drivers/ide/sgiioc4.c +++ b/drivers/ide/sgiioc4.c @@ -255,7 +255,7 @@ static int sgiioc4_dma_end(ide_drive_t *drive) return dma_stat; } -static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void sgiioc4_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { } diff --git a/drivers/ide/siimage.c b/drivers/ide/siimage.c index 97266958f744..2009ac2ff658 100644 --- a/drivers/ide/siimage.c +++ b/drivers/ide/siimage.c @@ -289,19 +289,18 @@ static void sil_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) /** * sil_set_dma_mode - set host controller for DMA mode + * @hwif: port * @drive: drive - * @speed: DMA mode * * Tune the SiI chipset for the desired DMA mode. */ -static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void sil_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); unsigned long base = (unsigned long)hwif->hwif_data; u16 ultra = 0, multi = 0; @@ -311,6 +310,7 @@ static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed) : (mmio ? 0xB4 : 0x80); unsigned long ma = siimage_seldev(drive, 0x08); unsigned long ua = siimage_seldev(drive, 0x0C); + const u8 speed = drive->dma_mode; scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A)); mode = sil_ioread8 (dev, base + addr_mask); diff --git a/drivers/ide/sis5513.c b/drivers/ide/sis5513.c index 5a0192060531..db7f4e761dbc 100644 --- a/drivers/ide/sis5513.c +++ b/drivers/ide/sis5513.c @@ -340,8 +340,10 @@ static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode) sis_ata33_program_udma_timings(drive, mode); } -static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void sis_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { + const u8 speed = drive->dma_mode; + if (speed >= XFER_UDMA_0) sis_program_udma_timings(drive, speed); else diff --git a/drivers/ide/sl82c105.c b/drivers/ide/sl82c105.c index 419cd3bc6c84..f21dc2ad7682 100644 --- a/drivers/ide/sl82c105.c +++ b/drivers/ide/sl82c105.c @@ -92,11 +92,12 @@ static void sl82c105_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) /* * Configure the chipset for DMA mode. */ -static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void sl82c105_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200}; unsigned long timings = (unsigned long)ide_get_drivedata(drive); u16 drv_ctrl; + const u8 speed = drive->dma_mode; drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; diff --git a/drivers/ide/slc90e66.c b/drivers/ide/slc90e66.c index 019777522cd2..864ffe0e26d9 100644 --- a/drivers/ide/slc90e66.c +++ b/drivers/ide/slc90e66.c @@ -72,14 +72,14 @@ static void slc90e66_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) spin_unlock_irqrestore(&slc90e66_lock, flags); } -static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed) +static void slc90e66_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); u8 maslave = hwif->channel ? 0x42 : 0x40; int sitre = 0, a_speed = 7 << (drive->dn * 4); int u_speed = 0, u_flag = 1 << drive->dn; u16 reg4042, reg44, reg48, reg4a; + const u8 speed = drive->dma_mode; pci_read_config_word(dev, maslave, ®4042); sitre = (reg4042 & 0x4000) ? 1 : 0; diff --git a/drivers/ide/tc86c001.c b/drivers/ide/tc86c001.c index f2cb62bf3f22..e444d24934b3 100644 --- a/drivers/ide/tc86c001.c +++ b/drivers/ide/tc86c001.c @@ -13,11 +13,11 @@ #define DRV_NAME "tc86c001" -static void tc86c001_set_mode(ide_drive_t *drive, const u8 speed) +static void tc86c001_set_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; unsigned long scr_port = hwif->config_data + (drive->dn ? 0x02 : 0x00); u16 mode, scr = inw(scr_port); + const u8 speed = drive->dma_mode; switch (speed) { case XFER_UDMA_4: mode = 0x00c0; break; @@ -43,7 +43,8 @@ static void tc86c001_set_mode(ide_drive_t *drive, const u8 speed) static void tc86c001_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - tc86c001_set_mode(drive, drive->pio_mode); + drive->dma_mode = drive->pio_mode; + tc86c001_set_mode(hwif, drive); } /* diff --git a/drivers/ide/triflex.c b/drivers/ide/triflex.c index d34a7eecdea5..7953447eae0f 100644 --- a/drivers/ide/triflex.c +++ b/drivers/ide/triflex.c @@ -34,9 +34,8 @@ #define DRV_NAME "triflex" -static void triflex_set_mode(ide_drive_t *drive, const u8 speed) +static void triflex_set_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); u32 triflex_timings = 0; u16 timing = 0; @@ -44,7 +43,7 @@ static void triflex_set_mode(ide_drive_t *drive, const u8 speed) pci_read_config_dword(dev, channel_offset, &triflex_timings); - switch(speed) { + switch (drive->dma_mode) { case XFER_MW_DMA_2: timing = 0x0103; break; @@ -84,7 +83,8 @@ static void triflex_set_mode(ide_drive_t *drive, const u8 speed) static void triflex_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - triflex_set_mode(drive, drive->pio_mode); + drive->dma_mode = drive->pio_mode; + triflex_set_mode(hwif, drive); } static const struct ide_port_ops triflex_port_ops = { diff --git a/drivers/ide/tx4939ide.c b/drivers/ide/tx4939ide.c index 5228a4786de5..f210633a3d57 100644 --- a/drivers/ide/tx4939ide.c +++ b/drivers/ide/tx4939ide.c @@ -125,10 +125,10 @@ static void tx4939ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */ } -static void tx4939ide_set_dma_mode(ide_drive_t *drive, const u8 mode) +static void tx4939ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; u32 mask, val; + const u8 mode = drive->dma_mode; /* Update Data Transfer Mode for this drive. */ if (mode >= XFER_UDMA_0) diff --git a/drivers/ide/via82cxxx.c b/drivers/ide/via82cxxx.c index 6d995fc9d4f5..6769fe252b07 100644 --- a/drivers/ide/via82cxxx.c +++ b/drivers/ide/via82cxxx.c @@ -169,22 +169,22 @@ static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) /** * via_set_drive - configure transfer mode + * @hwif: port * @drive: Drive to set up - * @speed: desired speed * * via_set_drive() computes timing values configures the chipset to * a desired transfer mode. It also can be called by upper layers. */ -static void via_set_drive(ide_drive_t *drive, const u8 speed) +static void via_set_drive(ide_hwif_t *hwif, ide_drive_t *drive) { - ide_hwif_t *hwif = drive->hwif; ide_drive_t *peer = ide_get_pair_dev(drive); struct pci_dev *dev = to_pci_dev(hwif->dev); struct ide_host *host = pci_get_drvdata(dev); struct via82cxxx_dev *vdev = host->host_priv; struct ide_timing t, p; unsigned int T, UT; + const u8 speed = drive->dma_mode; T = 1000000000 / via_clock; @@ -216,7 +216,8 @@ static void via_set_drive(ide_drive_t *drive, const u8 speed) static void via_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - via_set_drive(drive, drive->pio_mode); + drive->dma_mode = drive->pio_mode; + via_set_drive(hwif, drive); } static struct via_isa_bridge *via_config_find(struct pci_dev **isa) diff --git a/include/linux/ide.h b/include/linux/ide.h index 803ec306883c..53ecdba82d72 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -625,7 +625,7 @@ extern const struct ide_tp_ops default_tp_ops; struct ide_port_ops { void (*init_dev)(ide_drive_t *); void (*set_pio_mode)(struct hwif_s *, ide_drive_t *); - void (*set_dma_mode)(ide_drive_t *, const u8); + void (*set_dma_mode)(struct hwif_s *, ide_drive_t *); int (*reset_poll)(ide_drive_t *); void (*pre_reset)(ide_drive_t *); void (*resetproc)(ide_drive_t *); -- cgit v1.2.3 From 8e714a074bc4da070807d019d4287dcd32af55f5 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Tue, 19 Jan 2010 01:47:29 -0800 Subject: ide-timings: use ->pio_mode value to determine fastest PIO speed Use the current PIO mode value instead of the physical maximum one to determine the fastest allowed PIO for shared PIO/DMA timings. Affected host drivers: amd74xx and via82cxxx. [ Update comment to match -DaveM ] Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/ide-timings.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/ide-timings.c b/drivers/ide/ide-timings.c index c6053ab2b6c6..c7a65ee72310 100644 --- a/drivers/ide/ide-timings.c +++ b/drivers/ide/ide-timings.c @@ -186,11 +186,10 @@ int ide_timing_compute(ide_drive_t *drive, u8 speed, /* * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, * S.M.A.R.T and some other commands. We have to ensure that the - * DMA cycle timing is slower/equal than the fastest PIO timing. + * DMA cycle timing is slower/equal than the current PIO timing. */ if (speed >= XFER_SW_DMA_0) { - u8 pio = ide_get_best_pio_mode(drive, 255, 5); - ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT); + ide_timing_compute(drive, drive->pio_mode, &p, T, UT); ide_timing_merge(&p, t, t, IDE_TIMING_ALL); } -- cgit v1.2.3 From cde727be967a86aee01042f35c8a861728272cf1 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:21:05 +0000 Subject: alim15x3: fix handling of address setup timings Account for the requirements of the other device on the port. Based on libata pata_ali host driver. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/alim15x3.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c index 6f0debae4e27..8e29801bbeb0 100644 --- a/drivers/ide/alim15x3.c +++ b/drivers/ide/alim15x3.c @@ -72,6 +72,7 @@ static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on) static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { struct pci_dev *dev = to_pci_dev(hwif->dev); + ide_drive_t *pair = ide_get_pair_dev(drive); int bus_speed = ide_pci_clk ? ide_pci_clk : 33; unsigned long T = 1000000 / bus_speed; /* PCI clock based */ int port = hwif->channel ? 0x5c : 0x58; @@ -79,6 +80,16 @@ static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) struct ide_timing t; ide_timing_compute(drive, drive->pio_mode, &t, T, 1); + if (pair) { + struct ide_timing p; + + ide_timing_compute(pair, pair->pio_mode, &p, T, 1); + ide_timing_merge(&p, &t, &t, IDE_TIMING_SETUP); + if (pair->dma_mode) { + ide_timing_compute(pair, pair->dma_mode, &p, T, 1); + ide_timing_merge(&p, &t, &t, IDE_TIMING_SETUP); + } + } t.setup = clamp_val(t.setup, 1, 8) & 7; t.active = clamp_val(t.active, 1, 8) & 7; -- cgit v1.2.3 From 5740345b877e2c8745cdf454674b45919679f231 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:21:12 +0000 Subject: alim15x3: fix handling of command timings Stop depending on the BIOS setup. Based on libata pata_ali host driver. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/alim15x3.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c index 8e29801bbeb0..529f8e2218ac 100644 --- a/drivers/ide/alim15x3.c +++ b/drivers/ide/alim15x3.c @@ -84,14 +84,18 @@ static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) struct ide_timing p; ide_timing_compute(pair, pair->pio_mode, &p, T, 1); - ide_timing_merge(&p, &t, &t, IDE_TIMING_SETUP); + ide_timing_merge(&p, &t, &t, + IDE_TIMING_SETUP | IDE_TIMING_8BIT); if (pair->dma_mode) { ide_timing_compute(pair, pair->dma_mode, &p, T, 1); - ide_timing_merge(&p, &t, &t, IDE_TIMING_SETUP); + ide_timing_merge(&p, &t, &t, + IDE_TIMING_SETUP | IDE_TIMING_8BIT); } } t.setup = clamp_val(t.setup, 1, 8) & 7; + t.act8b = clamp_val(t.act8b, 1, 8) & 7; + t.rec8b = clamp_val(t.rec8b, 1, 16) & 15; t.active = clamp_val(t.active, 1, 8) & 7; t.recover = clamp_val(t.recover, 1, 16) & 15; @@ -101,6 +105,7 @@ static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) ali_fifo_control(hwif, drive, (drive->media == ide_disk) ? 0x05 : 0x00); pci_write_config_byte(dev, port, t.setup); + pci_write_config_byte(dev, port + 1, (t.act8b << 4) | t.rec8b); pci_write_config_byte(dev, port + unit + 2, (t.active << 4) | t.recover); } -- cgit v1.2.3 From a345c7856e52bf8b21a5ae6a24fb824bfedefbe9 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:21:19 +0000 Subject: alim15x3: fix handling of DMA timings Stop depending on the BIOS setup. Based on libata pata_ali host driver. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/alim15x3.c | 55 +++++++++++++++++++++++++++++++++++--------------- 1 file changed, 39 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c index 529f8e2218ac..3ba7d0bdd25d 100644 --- a/drivers/ide/alim15x3.c +++ b/drivers/ide/alim15x3.c @@ -61,6 +61,25 @@ static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on) pci_write_config_byte(pdev, pio_fifo, fifo); } +static void ali_program_timings(ide_hwif_t *hwif, ide_drive_t *drive, + struct ide_timing *t) +{ + struct pci_dev *dev = to_pci_dev(hwif->dev); + int port = hwif->channel ? 0x5c : 0x58; + u8 unit = drive->dn & 1; + + t->setup = clamp_val(t->setup, 1, 8) & 7; + t->act8b = clamp_val(t->act8b, 1, 8) & 7; + t->rec8b = clamp_val(t->rec8b, 1, 16) & 15; + t->active = clamp_val(t->active, 1, 8) & 7; + t->recover = clamp_val(t->recover, 1, 16) & 15; + + pci_write_config_byte(dev, port, t->setup); + pci_write_config_byte(dev, port + 1, (t->act8b << 4) | t->rec8b); + pci_write_config_byte(dev, port + unit + 2, + (t->active << 4) | t->recover); +} + /** * ali_set_pio_mode - set host controller for PIO mode * @hwif: port @@ -71,12 +90,9 @@ static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on) static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { - struct pci_dev *dev = to_pci_dev(hwif->dev); ide_drive_t *pair = ide_get_pair_dev(drive); int bus_speed = ide_pci_clk ? ide_pci_clk : 33; unsigned long T = 1000000 / bus_speed; /* PCI clock based */ - int port = hwif->channel ? 0x5c : 0x58; - u8 unit = drive->dn & 1; struct ide_timing t; ide_timing_compute(drive, drive->pio_mode, &t, T, 1); @@ -93,21 +109,12 @@ static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) } } - t.setup = clamp_val(t.setup, 1, 8) & 7; - t.act8b = clamp_val(t.act8b, 1, 8) & 7; - t.rec8b = clamp_val(t.rec8b, 1, 16) & 15; - t.active = clamp_val(t.active, 1, 8) & 7; - t.recover = clamp_val(t.recover, 1, 16) & 15; - /* * PIO mode => ATA FIFO on, ATAPI FIFO off */ ali_fifo_control(hwif, drive, (drive->media == ide_disk) ? 0x05 : 0x00); - pci_write_config_byte(dev, port, t.setup); - pci_write_config_byte(dev, port + 1, (t.act8b << 4) | t.rec8b); - pci_write_config_byte(dev, port + unit + 2, - (t.active << 4) | t.recover); + ali_program_timings(hwif, drive, &t); } /** @@ -146,11 +153,15 @@ static u8 ali_udma_filter(ide_drive_t *drive) static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { struct pci_dev *dev = to_pci_dev(hwif->dev); + ide_drive_t *pair = ide_get_pair_dev(drive); + int bus_speed = ide_pci_clk ? ide_pci_clk : 33; + unsigned long T = 1000000 / bus_speed; /* PCI clock based */ const u8 speed = drive->dma_mode; u8 speed1 = speed; u8 unit = drive->dn & 1; u8 tmpbyte = 0x00; int m5229_udma = (hwif->channel) ? 0x57 : 0x56; + struct ide_timing t; if (speed == XFER_UDMA_6) speed1 = 0x47; @@ -164,9 +175,21 @@ static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) tmpbyte &= ultra_enable; pci_write_config_byte(dev, m5229_udma, tmpbyte); - /* - * FIXME: Oh, my... DMA timings are never set. - */ + ide_timing_compute(drive, drive->dma_mode, &t, T, 1); + if (pair) { + struct ide_timing p; + + ide_timing_compute(pair, pair->pio_mode, &p, T, 1); + ide_timing_merge(&p, &t, &t, + IDE_TIMING_SETUP | IDE_TIMING_8BIT); + if (pair->dma_mode) { + ide_timing_compute(pair, pair->dma_mode, + &p, T, 1); + ide_timing_merge(&p, &t, &t, + IDE_TIMING_SETUP | IDE_TIMING_8BIT); + } + } + ali_program_timings(hwif, drive, &t); } else { pci_read_config_byte(dev, m5229_udma, &tmpbyte); tmpbyte &= (0x0f << ((1-unit) << 2)); -- cgit v1.2.3 From e4c7112b5686c70ba7be86dbc83c989c75aca802 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:21:26 +0000 Subject: alim15x3: fix handling of UDMA enable bit Clear UDMA enable bit also for PIO modes. Based on libata pata_ali host driver. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/alim15x3.c | 43 ++++++++++++++++++------------------------- 1 file changed, 18 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c index 3ba7d0bdd25d..2c8016ad0e26 100644 --- a/drivers/ide/alim15x3.c +++ b/drivers/ide/alim15x3.c @@ -62,11 +62,22 @@ static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on) } static void ali_program_timings(ide_hwif_t *hwif, ide_drive_t *drive, - struct ide_timing *t) + struct ide_timing *t, u8 ultra) { struct pci_dev *dev = to_pci_dev(hwif->dev); int port = hwif->channel ? 0x5c : 0x58; - u8 unit = drive->dn & 1; + int udmat = 0x56 + hwif->channel; + u8 unit = drive->dn & 1, udma; + int shift = 4 * unit; + + /* Set up the UDMA */ + pci_read_config_byte(dev, udmat, &udma); + udma &= ~(0x0F << shift); + udma |= ultra << shift; + pci_write_config_byte(dev, udmat, udma); + + if (t == NULL) + return; t->setup = clamp_val(t->setup, 1, 8) & 7; t->act8b = clamp_val(t->act8b, 1, 8) & 7; @@ -114,7 +125,7 @@ static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) */ ali_fifo_control(hwif, drive, (drive->media == ide_disk) ? 0x05 : 0x00); - ali_program_timings(hwif, drive, &t); + ali_program_timings(hwif, drive, &t, 0); } /** @@ -152,29 +163,16 @@ static u8 ali_udma_filter(ide_drive_t *drive) static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) { + static u8 udma_timing[7] = { 0xC, 0xB, 0xA, 0x9, 0x8, 0xF, 0xD }; struct pci_dev *dev = to_pci_dev(hwif->dev); ide_drive_t *pair = ide_get_pair_dev(drive); int bus_speed = ide_pci_clk ? ide_pci_clk : 33; unsigned long T = 1000000 / bus_speed; /* PCI clock based */ const u8 speed = drive->dma_mode; - u8 speed1 = speed; - u8 unit = drive->dn & 1; u8 tmpbyte = 0x00; - int m5229_udma = (hwif->channel) ? 0x57 : 0x56; struct ide_timing t; - if (speed == XFER_UDMA_6) - speed1 = 0x47; - if (speed < XFER_UDMA_0) { - u8 ultra_enable = (unit) ? 0x7f : 0xf7; - /* - * clear "ultra enable" bit - */ - pci_read_config_byte(dev, m5229_udma, &tmpbyte); - tmpbyte &= ultra_enable; - pci_write_config_byte(dev, m5229_udma, tmpbyte); - ide_timing_compute(drive, drive->dma_mode, &t, T, 1); if (pair) { struct ide_timing p; @@ -189,15 +187,10 @@ static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) IDE_TIMING_SETUP | IDE_TIMING_8BIT); } } - ali_program_timings(hwif, drive, &t); + ali_program_timings(hwif, drive, &t, 0); } else { - pci_read_config_byte(dev, m5229_udma, &tmpbyte); - tmpbyte &= (0x0f << ((1-unit) << 2)); - /* - * enable ultra dma and set timing - */ - tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2)); - pci_write_config_byte(dev, m5229_udma, tmpbyte); + ali_program_timings(hwif, drive, NULL, + udma_timing[speed - XFER_UDMA_0]); if (speed >= XFER_UDMA_3) { pci_read_config_byte(dev, 0x4b, &tmpbyte); tmpbyte |= 1; -- cgit v1.2.3 From f6d23c2e2e398dc96c58494be2934f0c11285e3a Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:21:33 +0000 Subject: amd74xx: use ->pio_mode value to determine pair device speed Use the current PIO mode value instead of the current transfer speed of the pair device on the port to determine PIO commmand timings used for both devices on the port. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/amd74xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ide/amd74xx.c b/drivers/ide/amd74xx.c index b7e105338205..3747b2561f09 100644 --- a/drivers/ide/amd74xx.c +++ b/drivers/ide/amd74xx.c @@ -94,7 +94,7 @@ static void amd_set_drive(ide_hwif_t *hwif, ide_drive_t *drive) ide_timing_compute(drive, speed, &t, T, UT); if (peer) { - ide_timing_compute(peer, peer->current_speed, &p, T, UT); + ide_timing_compute(peer, peer->pio_mode, &p, T, UT); ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); } -- cgit v1.2.3 From 23d874054663efaf18340dc554df1b935820cbab Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:21:41 +0000 Subject: cmd64x: fix handling of address setup timings Account for the requirements of the DMA mode currently used. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/cmd64x.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/cmd64x.c b/drivers/ide/cmd64x.c index a65a69171250..5f80312e636b 100644 --- a/drivers/ide/cmd64x.c +++ b/drivers/ide/cmd64x.c @@ -88,9 +88,6 @@ static void cmd64x_program_timings(ide_drive_t *drive, u8 mode) pci_write_config_byte(dev, drwtim_regs[drive->dn], (t.active << 4) | t.recover); - if (mode >= XFER_SW_DMA_0) - return; - /* * The primary channel has individual address setup timing registers * for each drive and the hardware selects the slowest timing itself. @@ -100,11 +97,17 @@ static void cmd64x_program_timings(ide_drive_t *drive, u8 mode) if (hwif->channel) { ide_drive_t *pair = ide_get_pair_dev(drive); - ide_set_drivedata(drive, (void *)(unsigned long)t.setup); + if (pair) { + struct ide_timing tp; - if (pair) - t.setup = max_t(u8, t.setup, - (unsigned long)ide_get_drivedata(pair)); + ide_timing_compute(pair, pair->pio_mode, &tp, T, 0); + ide_timing_merge(&t, &tp, &t, IDE_TIMING_SETUP); + if (pair->dma_mode) { + ide_timing_compute(pair, pair->dma_mode, + &tp, T, 0); + ide_timing_merge(&tp, &t, &t, IDE_TIMING_SETUP); + } + } } if (t.setup > 5) /* shouldn't actually happen... */ -- cgit v1.2.3 From a298dc024c2b0b92d3889d61856117141d693b39 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:21:48 +0000 Subject: cs5535: use ->pio_mode value to determine pair device speed Use the current PIO mode value instead of the physical maximum one of the pair device on the port to determine PIO commmand timings used for both devices on the port. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/cs5535.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ide/cs5535.c b/drivers/ide/cs5535.c index 740002b2f3e8..5059fafadf29 100644 --- a/drivers/ide/cs5535.c +++ b/drivers/ide/cs5535.c @@ -86,7 +86,7 @@ static void cs5535_set_speed(ide_drive_t *drive, const u8 speed) cmd = pioa = speed - XFER_PIO_0; if (pair) { - u8 piob = ide_get_best_pio_mode(pair, 255, 4); + u8 piob = pair->pio_mode - XFER_PIO_0; if (piob < cmd) cmd = piob; -- cgit v1.2.3 From 280d69b127f75e1928f583c90f659d49cec4d177 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:21:55 +0000 Subject: cs5536: use ->pio_mode value to determine pair device speed Use the current PIO mode value instead of the physical maximum one of the pair device on the port to determine PIO commmand timings used for both devices on the port. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/cs5536.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ide/cs5536.c b/drivers/ide/cs5536.c index 70871fbc3c0a..24214ab60ac0 100644 --- a/drivers/ide/cs5536.c +++ b/drivers/ide/cs5536.c @@ -152,7 +152,7 @@ static void cs5536_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) u8 cmd_pio = pio; if (pair) - cmd_pio = min(pio, ide_get_best_pio_mode(pair, 255, 4)); + cmd_pio = min_t(u8, pio, pair->pio_mode - XFER_PIO_0); timings &= (IDE_DRV_MASK << 8); timings |= drv_timings[pio]; -- cgit v1.2.3 From f657911d73f5165c4a32627adbbd7fcf98a85eae Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:22:02 +0000 Subject: it821x: use ->pio_mode value to determine pair device speed Use the current PIO mode value instead of the physical maximum one of the pair device on the port to determine PIO commmand timings used for both devices on the port. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/it821x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ide/it821x.c b/drivers/ide/it821x.c index 56b79194156b..b2709c733485 100644 --- a/drivers/ide/it821x.c +++ b/drivers/ide/it821x.c @@ -252,7 +252,7 @@ static void it821x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) * on the cable. */ if (pair) { - u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); + u8 pair_pio = pair->pio_mode - XFER_PIO_0; /* trim PIO to the slowest of the master/slave */ if (pair_pio < set_pio) set_pio = pair_pio; -- cgit v1.2.3 From 0716302eec10c3a4c3c5110e43a5ac05ac4b2445 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:22:09 +0000 Subject: palm_bk3710: use ->pio_mode value to determine pair device speed Use the current PIO mode value instead of the physical maximum one of the pair device on the port to determine PIO commmand timings used for both devices on the port. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/palm_bk3710.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ide/palm_bk3710.c b/drivers/ide/palm_bk3710.c index 35448c91b8c8..9e8f4e1b0cc9 100644 --- a/drivers/ide/palm_bk3710.c +++ b/drivers/ide/palm_bk3710.c @@ -166,7 +166,7 @@ static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate, writel(val32, base + BK3710_DATRCVR); if (mate) { - u8 mode2 = ide_get_best_pio_mode(mate, 255, 4); + u8 mode2 = mate->pio_mode - XFER_PIO_0; if (mode2 < mode) mode = mode2; -- cgit v1.2.3 From bb430611930c526ff9bca991f254b259fc58ed3c Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:22:16 +0000 Subject: siimage: use ->pio_mode value to determine pair device speed Use the current PIO mode value instead of the physical maximum one of the pair device on the port to determine PIO commmand timings used for both devices on the port. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/siimage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ide/siimage.c b/drivers/ide/siimage.c index 2009ac2ff658..ddeda444a27a 100644 --- a/drivers/ide/siimage.c +++ b/drivers/ide/siimage.c @@ -258,7 +258,7 @@ static void sil_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) /* trim *taskfile* PIO to the slowest of the master/slave */ if (pair) { - u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); + u8 pair_pio = pair->pio_mode - XFER_PIO_0; if (pair_pio < tf_pio) tf_pio = pair_pio; -- cgit v1.2.3 From 040f6b4f14adb2ca5babb84e9fb2ebc6661e0be2 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:22:23 +0000 Subject: tx493xide: use ->pio_mode value to determine pair device speed Use the current PIO mode value instead of the physical maximum one of the pair device on the port to determine PIO commmand timings used for both devices on the port. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/tx4938ide.c | 2 +- drivers/ide/tx4939ide.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/tx4938ide.c b/drivers/ide/tx4938ide.c index 326d4683488b..1d80f1fdbc97 100644 --- a/drivers/ide/tx4938ide.c +++ b/drivers/ide/tx4938ide.c @@ -64,7 +64,7 @@ static void tx4938ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) pair = ide_get_pair_dev(drive); if (pair) - safe = min(safe, ide_get_best_pio_mode(pair, 255, 5)); + safe = min(safe, pair->pio_mode - XFER_PIO_0); tx4938ide_tune_ebusc(pdata->ebus_ch, pdata->gbus_clock, safe); } diff --git a/drivers/ide/tx4939ide.c b/drivers/ide/tx4939ide.c index f210633a3d57..3c7367751873 100644 --- a/drivers/ide/tx4939ide.c +++ b/drivers/ide/tx4939ide.c @@ -114,7 +114,7 @@ static void tx4939ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) pair = ide_get_pair_dev(drive); if (pair) - safe = min(safe, ide_get_best_pio_mode(pair, 255, 4)); + safe = min(safe, pair->pio_mode - XFER_PIO_0); /* * Update Command Transfer Mode for master/slave and Data * Transfer Mode for this drive. -- cgit v1.2.3 From f0e5f62d92531b18c98feb6907bdb3d7b2f67ceb Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:22:30 +0000 Subject: via82cxxx: use ->pio_mode value to determine pair device speed Use the current PIO mode value instead of the current transfer speed of the pair device on the port to determine PIO commmand timings used for both devices on the port. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/via82cxxx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ide/via82cxxx.c b/drivers/ide/via82cxxx.c index 6769fe252b07..e65d010b708d 100644 --- a/drivers/ide/via82cxxx.c +++ b/drivers/ide/via82cxxx.c @@ -199,7 +199,7 @@ static void via_set_drive(ide_hwif_t *hwif, ide_drive_t *drive) ide_timing_compute(drive, speed, &t, T, UT); if (peer) { - ide_timing_compute(peer, peer->current_speed, &p, T, UT); + ide_timing_compute(peer, peer->pio_mode, &p, T, UT); ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); } -- cgit v1.2.3 From 220c58bc6d1198c4c4e69a385d364602c38b6b1c Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:22:38 +0000 Subject: ide: make ide_get_best_pio_mode() static Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/ide-xfer-mode.c | 3 +-- include/linux/ide.h | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/ide-xfer-mode.c b/drivers/ide/ide-xfer-mode.c index 9b549e4d1848..5fc8d5c17de9 100644 --- a/drivers/ide/ide-xfer-mode.c +++ b/drivers/ide/ide-xfer-mode.c @@ -58,7 +58,7 @@ EXPORT_SYMBOL(ide_xfer_verbose); * This is used by most chipset support modules when "auto-tuning". */ -u8 ide_get_best_pio_mode(ide_drive_t *drive, u8 mode_wanted, u8 max_mode) +static u8 ide_get_best_pio_mode(ide_drive_t *drive, u8 mode_wanted, u8 max_mode) { u16 *id = drive->id; int pio_mode = -1, overridden = 0; @@ -105,7 +105,6 @@ u8 ide_get_best_pio_mode(ide_drive_t *drive, u8 mode_wanted, u8 max_mode) return pio_mode; } -EXPORT_SYMBOL_GPL(ide_get_best_pio_mode); int ide_pio_need_iordy(ide_drive_t *drive, const u8 pio) { diff --git a/include/linux/ide.h b/include/linux/ide.h index 53ecdba82d72..97e6ab435184 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -1496,7 +1496,6 @@ int ide_timing_compute(ide_drive_t *, u8, struct ide_timing *, int, int); #ifdef CONFIG_IDE_XFER_MODE int ide_scan_pio_blacklist(char *); const char *ide_xfer_verbose(u8); -u8 ide_get_best_pio_mode(ide_drive_t *, u8, u8); int ide_pio_need_iordy(ide_drive_t *, const u8); int ide_set_pio_mode(ide_drive_t *, u8); int ide_set_dma_mode(ide_drive_t *, u8); -- cgit v1.2.3 From 3dabcfef3e668f6dd32147d810a29ccbd55dc963 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Tue, 19 Jan 2010 11:30:09 -0800 Subject: ide: ide_timing_compute() fixup XFER_SW_DMA_0 mode should be excluded from the extended cycle timing computations. [ This is just a documentation fix -- code inside the affected 'if' block already makes sure to accept only PIO modes. ] Noticed-by: Sergei Shtylyov Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller --- drivers/ide/ide-timings.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ide/ide-timings.c b/drivers/ide/ide-timings.c index c7a65ee72310..0e05f75934c9 100644 --- a/drivers/ide/ide-timings.c +++ b/drivers/ide/ide-timings.c @@ -166,7 +166,7 @@ int ide_timing_compute(ide_drive_t *drive, u8 speed, if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */ memset(&p, 0, sizeof(p)); - if (speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) { + if (speed >= XFER_PIO_0 && speed < XFER_SW_DMA_0) { if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; else if ((speed <= XFER_PIO_4) || -- cgit v1.2.3 From 5b8a2fb34f5670b1f07483bfa40de9ce539dbdb2 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Sun, 17 Jan 2010 20:25:36 +0100 Subject: msm_sdcc.c: missing brackets in msmsdcc_resume() Since the curly brackets were missing the test and enable_irq(), if true, occurred twice. Signed-off-by: Roel Kluin --- drivers/mmc/host/msm_sdcc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index b31946e0b4ca..4c068e5fe6b2 100644 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c @@ -1250,9 +1250,7 @@ msmsdcc_resume(struct platform_device *dev) if (mmc->card && mmc->card->type != MMC_TYPE_SDIO) mmc_resume_host(mmc); - if (host->stat_irq) - enable_irq(host->stat_irq); - else if (host->stat_irq) + if (host->stat_irq) enable_irq(host->stat_irq); } return 0; -- cgit v1.2.3 From d85127319cc36c38eb99615c52531c6ef2f11369 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 22 Jan 2010 10:50:42 +0900 Subject: ARM: S5PV210: Add serial port support This patch adds UART serial port support for S5PV210. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/regs-serial.h | 30 ++++++ drivers/serial/Kconfig | 9 +- drivers/serial/Makefile | 1 + drivers/serial/s5pv210.c | 154 +++++++++++++++++++++++++++ 4 files changed, 193 insertions(+), 1 deletion(-) create mode 100644 drivers/serial/s5pv210.c (limited to 'drivers') diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h index 85d8904e7f24..60d6604185ea 100644 --- a/arch/arm/plat-s3c/include/plat/regs-serial.h +++ b/arch/arm/plat-s3c/include/plat/regs-serial.h @@ -194,6 +194,36 @@ #define S3C64XX_UINTSP 0x34 #define S3C64XX_UINTM 0x38 +/* Following are specific to S5PV210 and S5P6442 */ +#define S5PV210_UCON_CLKMASK (1<<10) +#define S5PV210_UCON_PCLK (0<<10) +#define S5PV210_UCON_UCLK (1<<10) + +#define S5PV210_UFCON_TXTRIG0 (0<<8) +#define S5PV210_UFCON_TXTRIG4 (1<<8) +#define S5PV210_UFCON_TXTRIG8 (2<<8) +#define S5PV210_UFCON_TXTRIG16 (3<<8) +#define S5PV210_UFCON_TXTRIG32 (4<<8) +#define S5PV210_UFCON_TXTRIG64 (5<<8) +#define S5PV210_UFCON_TXTRIG128 (6<<8) +#define S5PV210_UFCON_TXTRIG256 (7<<8) + +#define S5PV210_UFCON_RXTRIG1 (0<<4) +#define S5PV210_UFCON_RXTRIG4 (1<<4) +#define S5PV210_UFCON_RXTRIG8 (2<<4) +#define S5PV210_UFCON_RXTRIG16 (3<<4) +#define S5PV210_UFCON_RXTRIG32 (4<<4) +#define S5PV210_UFCON_RXTRIG64 (5<<4) +#define S5PV210_UFCON_RXTRIG128 (6<<4) +#define S5PV210_UFCON_RXTRIG256 (7<<4) + +#define S5PV210_UFSTAT_TXFULL (1<<24) +#define S5PV210_UFSTAT_RXFULL (1<<8) +#define S5PV210_UFSTAT_TXMASK (255<<16) +#define S5PV210_UFSTAT_TXSHIFT (16) +#define S5PV210_UFSTAT_RXMASK (255<<0) +#define S5PV210_UFSTAT_RXSHIFT (0) + #ifndef __ASSEMBLY__ /* struct s3c24xx_uart_clksrc diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index d7d687f0d201..ebdd2b984d16 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -459,7 +459,7 @@ config SERIAL_SAMSUNG_UARTS int depends on ARM && PLAT_S3C default 2 if ARCH_S3C2400 - default 4 if ARCH_S5P6440 || ARCH_S5PC1XX || ARCH_S3C64XX || CPU_S3C2443 + default 4 if ARCH_S5P6440 || ARCH_S5PC1XX || ARCH_S5PV210 || ARCH_S3C64XX || CPU_S3C2443 default 3 help Select the number of available UART ports for the Samsung S3C @@ -540,6 +540,13 @@ config SERIAL_S5PC100 help Serial port support for the Samsung S5PC100 SoCs +config SERIAL_S5PV210 + tristate "Samsung S5PV210 Serial port support" + depends on SERIAL_SAMSUNG && CPU_S5PV210 + default y + help + Serial port support for Samsung's S5P Family of SoC's + config SERIAL_MAX3100 tristate "MAX3100 support" depends on SPI diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 5548fe7df61d..6aa4723b74ee 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o obj-$(CONFIG_SERIAL_S5PC100) += s3c6400.o +obj-$(CONFIG_SERIAL_S5PV210) += s5pv210.o obj-$(CONFIG_SERIAL_MAX3100) += max3100.o obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o obj-$(CONFIG_SERIAL_MUX) += mux.o diff --git a/drivers/serial/s5pv210.c b/drivers/serial/s5pv210.c new file mode 100644 index 000000000000..8dc03837617b --- /dev/null +++ b/drivers/serial/s5pv210.c @@ -0,0 +1,154 @@ +/* linux/drivers/serial/s5pv210.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Based on drivers/serial/s3c6400.c + * + * Driver for Samsung S5PV210 SoC UARTs. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "samsung.h" + +static int s5pv210_serial_setsource(struct uart_port *port, + struct s3c24xx_uart_clksrc *clk) +{ + unsigned long ucon = rd_regl(port, S3C2410_UCON); + + if (strcmp(clk->name, "pclk") == 0) + ucon &= ~S5PV210_UCON_CLKMASK; + else if (strcmp(clk->name, "uclk1") == 0) + ucon |= S5PV210_UCON_CLKMASK; + else { + printk(KERN_ERR "unknown clock source %s\n", clk->name); + return -EINVAL; + } + + wr_regl(port, S3C2410_UCON, ucon); + return 0; +} + + +static int s5pv210_serial_getsource(struct uart_port *port, + struct s3c24xx_uart_clksrc *clk) +{ + u32 ucon = rd_regl(port, S3C2410_UCON); + + clk->divisor = 1; + + switch (ucon & S5PV210_UCON_CLKMASK) { + case S5PV210_UCON_PCLK: + clk->name = "pclk"; + break; + case S5PV210_UCON_UCLK: + clk->name = "uclk1"; + break; + } + + return 0; +} + +static int s5pv210_serial_resetport(struct uart_port *port, + struct s3c2410_uartcfg *cfg) +{ + unsigned long ucon = rd_regl(port, S3C2410_UCON); + + ucon &= S5PV210_UCON_CLKMASK; + wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); + wr_regl(port, S3C2410_ULCON, cfg->ulcon); + + /* reset both fifos */ + wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); + wr_regl(port, S3C2410_UFCON, cfg->ufcon); + + return 0; +} + +#define S5PV210_UART_DEFAULT_INFO(fifo_size) \ + .name = "Samsung S5PV210 UART0", \ + .type = PORT_S3C6400, \ + .fifosize = fifo_size, \ + .has_divslot = 1, \ + .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ + .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ + .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ + .tx_fifofull = S5PV210_UFSTAT_TXFULL, \ + .tx_fifomask = S5PV210_UFSTAT_TXMASK, \ + .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \ + .get_clksrc = s5pv210_serial_getsource, \ + .set_clksrc = s5pv210_serial_setsource, \ + .reset_port = s5pv210_serial_resetport + +static struct s3c24xx_uart_info s5p_port_fifo256 = { + S5PV210_UART_DEFAULT_INFO(256), +}; + +static struct s3c24xx_uart_info s5p_port_fifo64 = { + S5PV210_UART_DEFAULT_INFO(64), +}; + +static struct s3c24xx_uart_info s5p_port_fifo16 = { + S5PV210_UART_DEFAULT_INFO(16), +}; + +static struct s3c24xx_uart_info *s5p_uart_inf[] = { + [0] = &s5p_port_fifo256, + [1] = &s5p_port_fifo64, + [2] = &s5p_port_fifo16, + [3] = &s5p_port_fifo16, +}; + +/* device management */ +static int s5p_serial_probe(struct platform_device *pdev) +{ + return s3c24xx_serial_probe(pdev, s5p_uart_inf[pdev->id]); +} + +static struct platform_driver s5p_serial_drv = { + .probe = s5p_serial_probe, + .remove = __devexit_p(s3c24xx_serial_remove), + .driver = { + .name = "s5pv210-uart", + .owner = THIS_MODULE, + }, +}; + +static int __init s5pv210_serial_console_init(void) +{ + return s3c24xx_serial_initconsole(&s5p_serial_drv, s5p_uart_inf); +} + +console_initcall(s5pv210_serial_console_init); + +static int __init s5p_serial_init(void) +{ + return s3c24xx_serial_init(&s5p_serial_drv, *s5p_uart_inf); +} + +static void __exit s5p_serial_exit(void) +{ + platform_driver_unregister(&s5p_serial_drv); +} + +module_init(s5p_serial_init); +module_exit(s5p_serial_exit); + +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:s5pv210-uart"); +MODULE_DESCRIPTION("Samsung S5PV210 UART Driver support"); +MODULE_AUTHOR("Thomas Abraham "); -- cgit v1.2.3 From 8495fb1b8d016657133c01a2f258c5f192d2a1b7 Mon Sep 17 00:00:00 2001 From: Chris Frey Date: Thu, 28 Jan 2010 06:04:50 -0800 Subject: ide: fixed section mismatch warning in cmd640.c Signed-off-by: Chris Frey Signed-off-by: David S. Miller --- drivers/ide/cmd640.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ide/cmd640.c b/drivers/ide/cmd640.c index 1a32d62ed86b..cb11938ba684 100644 --- a/drivers/ide/cmd640.c +++ b/drivers/ide/cmd640.c @@ -605,7 +605,7 @@ static void cmd640_set_pio_mode(ide_drive_t *drive, const u8 pio) } #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */ -static void cmd640_init_dev(ide_drive_t *drive) +static void __init cmd640_init_dev(ide_drive_t *drive) { unsigned int i = drive->hwif->channel * 2 + (drive->dn & 1); -- cgit v1.2.3 From f8d94eb77e4ef6d80c6b7e5e02b92180d9a6f37b Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 27 Jan 2010 20:45:35 +0000 Subject: wm97xx_battery: Clean up some warnings Staticise work_lock (nothing outside the driver has any reason to see it) and specify dev when requesting the charger IRQ (since that's what we pass in when we free it). Signed-off-by: Mark Brown Acked-by: Marek Vasut Signed-off-by: Anton Vorontsov --- drivers/power/wm97xx_battery.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/power/wm97xx_battery.c b/drivers/power/wm97xx_battery.c index 6ea3cb5837c7..23eed356a854 100644 --- a/drivers/power/wm97xx_battery.c +++ b/drivers/power/wm97xx_battery.c @@ -26,7 +26,7 @@ static DEFINE_MUTEX(bat_lock); static struct work_struct bat_work; -struct mutex work_lock; +static struct mutex work_lock; static int bat_status = POWER_SUPPLY_STATUS_UNKNOWN; static struct wm97xx_batt_info *gpdata; static enum power_supply_property *prop; @@ -203,7 +203,7 @@ static int __devinit wm97xx_bat_probe(struct platform_device *dev) goto err2; ret = request_irq(gpio_to_irq(pdata->charge_gpio), wm97xx_chrg_irq, IRQF_DISABLED, - "AC Detect", 0); + "AC Detect", dev); if (ret) goto err2; props++; /* POWER_SUPPLY_PROP_STATUS */ -- cgit v1.2.3 From 9e0c7ef3f6c95357ce359a4f9223f0dfcd21cef7 Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Wed, 6 Jan 2010 14:20:31 +0200 Subject: UBI: mark few variables as __initdata The @mtd_devs and @mtd_dev_param variables are used only during the initialization, and all functions that use the variables have the __init prefix. This means we can safely mark the variables as __initdata, which is a tiny optimization. Impact: tiny RAM consumption optimization when UBI is used as a kernel module. Signed-off-by: Artem Bityutskiy --- drivers/mtd/ubi/build.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 14cec04c34f9..eb8f19f87c68 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -59,10 +59,10 @@ struct mtd_dev_param { }; /* Numbers of elements set in the @mtd_dev_param array */ -static int mtd_devs; +static int __initdata mtd_devs; /* MTD devices specification parameters */ -static struct mtd_dev_param mtd_dev_param[UBI_MAX_DEVICES]; +static struct mtd_dev_param __initdata mtd_dev_param[UBI_MAX_DEVICES]; /* Root UBI "class" object (corresponds to '//class/ubi/') */ struct class *ubi_class; -- cgit v1.2.3 From f9b0080e10e0ce3b8acbe91ae6a50da4f2ed7339 Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Tue, 5 Jan 2010 16:48:40 +0200 Subject: UBI: support attaching by MTD character device name This patch adds a capability to attach MTD devices by their character device paths. For example, one can do: $ modprobe ubi mtd=/dev/mtd0 to attach /dev/mtd0. Signed-off-by: Artem Bityutskiy --- drivers/mtd/ubi/build.c | 66 ++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 55 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index eb8f19f87c68..99ff57d3ac68 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -50,7 +51,8 @@ /** * struct mtd_dev_param - MTD device parameter description data structure. - * @name: MTD device name or number string + * @name: MTD character device node path, MTD device name, or MTD device number + * string * @vid_hdr_offs: VID header offset */ struct mtd_dev_param { @@ -1116,13 +1118,50 @@ int ubi_detach_mtd_dev(int ubi_num, int anyway) } /** - * find_mtd_device - open an MTD device by its name or number. - * @mtd_dev: name or number of the device + * open_mtd_by_chdev - open an MTD device by its character device node path. + * @mtd_dev: MTD character device node path + * + * This helper function opens an MTD device by its character node device path. + * Returns MTD device description object in case of success and a negative + * error code in case of failure. + */ +static struct mtd_info * __init open_mtd_by_chdev(const char *mtd_dev) +{ + int err, major, minor, mode; + struct path path; + + /* Probably this is an MTD character device node path */ + err = kern_path(mtd_dev, LOOKUP_FOLLOW, &path); + if (err) + return ERR_PTR(err); + + /* MTD device number is defined by the major / minor numbers */ + major = imajor(path.dentry->d_inode); + minor = iminor(path.dentry->d_inode); + mode = path.dentry->d_inode->i_mode; + path_put(&path); + if (major != MTD_CHAR_MAJOR || !S_ISCHR(mode)) + return ERR_PTR(-EINVAL); + + if (minor & 1) + /* + * Just do not think the "/dev/mtdrX" devices support is need, + * so do not support them to avoid doing extra work. + */ + return ERR_PTR(-EINVAL); + + return get_mtd_device(NULL, minor / 2); +} + +/** + * open_mtd_device - open MTD device by name, character device path, or number. + * @mtd_dev: name, character device node path, or MTD device device number * * This function tries to open and MTD device described by @mtd_dev string, - * which is first treated as an ASCII number, and if it is not true, it is - * treated as MTD device name. Returns MTD device description object in case of - * success and a negative error code in case of failure. + * which is first treated as ASCII MTD device number, and if it is not true, it + * is treated as MTD device name, and if that is also not true, it is treated + * as MTD character device node path. Returns MTD device description object in + * case of success and a negative error code in case of failure. */ static struct mtd_info * __init open_mtd_device(const char *mtd_dev) { @@ -1137,6 +1176,9 @@ static struct mtd_info * __init open_mtd_device(const char *mtd_dev) * MTD device name. */ mtd = get_mtd_device_nm(mtd_dev); + if (IS_ERR(mtd) && PTR_ERR(mtd) == -ENODEV) + /* Probably this is an MTD character device node path */ + mtd = open_mtd_by_chdev(mtd_dev); } else mtd = get_mtd_device(NULL, mtd_num); @@ -1352,13 +1394,15 @@ static int __init ubi_mtd_param_parse(const char *val, struct kernel_param *kp) module_param_call(mtd, ubi_mtd_param_parse, NULL, NULL, 000); MODULE_PARM_DESC(mtd, "MTD devices to attach. Parameter format: " - "mtd=[,].\n" + "mtd=[,].\n" "Multiple \"mtd\" parameters may be specified.\n" - "MTD devices may be specified by their number or name.\n" + "MTD devices may be specified by their number, name, or " + "path to the MTD character device node.\n" "Optional \"vid_hdr_offs\" parameter specifies UBI VID " - "header position and data starting position to be used " - "by UBI.\n" - "Example: mtd=content,1984 mtd=4 - attach MTD device" + "header position to be used by UBI.\n" + "Example 1: mtd=/dev/mtd0 - attach MTD device " + "/dev/mtd0.\n" + "Example 2: mtd=content,1984 mtd=4 - attach MTD device " "with name \"content\" using VID header offset 1984, and " "MTD device number 4 with default VID header offset."); -- cgit v1.2.3 From 0bf1c4399afee6a2031b0ee943a4c016e53f727c Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Tue, 12 Jan 2010 12:26:42 +0200 Subject: UBI: fix attaching error path In the error path of 'ubi_attach_mtd_dev()' we have a tricky situation: we have to release things differently depending on at which point the failure happening. Namely, if @ubi->dev is not initialized, we have to free everything ourselves. But if it was, we should not free the @ubi object, because it will be freed in the 'dev_release()' function. And we did not get this situation right. This patch introduces additional argument to the 'uif_init()' function. On exit, this argument indicates whether the final 'free(ubi)' will happen in 'dev_release()' or not. So the caller always knows how to properly release the resources. Impact: all memory is now correctly released when UBI fails to attach an MTD device. Signed-off-by: Artem Bityutskiy --- drivers/mtd/ubi/build.c | 63 +++++++++++++++++++++++-------------------------- 1 file changed, 30 insertions(+), 33 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 99ff57d3ac68..bc45ef9af17d 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -365,11 +365,13 @@ static void dev_release(struct device *dev) /** * ubi_sysfs_init - initialize sysfs for an UBI device. * @ubi: UBI device description object + * @ref: set to %1 on exit in case of failure if a reference to @ubi->dev was + * taken * * This function returns zero in case of success and a negative error code in * case of failure. */ -static int ubi_sysfs_init(struct ubi_device *ubi) +static int ubi_sysfs_init(struct ubi_device *ubi, int *ref) { int err; @@ -381,6 +383,7 @@ static int ubi_sysfs_init(struct ubi_device *ubi) if (err) return err; + *ref = 1; err = device_create_file(&ubi->dev, &dev_eraseblock_size); if (err) return err; @@ -436,7 +439,7 @@ static void ubi_sysfs_close(struct ubi_device *ubi) } /** - * kill_volumes - destroy all volumes. + * kill_volumes - destroy all user volumes. * @ubi: UBI device description object */ static void kill_volumes(struct ubi_device *ubi) @@ -448,37 +451,30 @@ static void kill_volumes(struct ubi_device *ubi) ubi_free_volume(ubi, ubi->volumes[i]); } -/** - * free_user_volumes - free all user volumes. - * @ubi: UBI device description object - * - * Normally the volumes are freed at the release function of the volume device - * objects. However, on error paths the volumes have to be freed before the - * device objects have been initialized. - */ -static void free_user_volumes(struct ubi_device *ubi) -{ - int i; - - for (i = 0; i < ubi->vtbl_slots; i++) - if (ubi->volumes[i]) { - kfree(ubi->volumes[i]->eba_tbl); - kfree(ubi->volumes[i]); - } -} - /** * uif_init - initialize user interfaces for an UBI device. * @ubi: UBI device description object + * @ref: set to %1 on exit in case of failure if a reference to @ubi->dev was + * taken, otherwise set to %0 + * + * This function initializes various user interfaces for an UBI device. If the + * initialization fails at an early stage, this function frees all the + * resources it allocated, returns an error, and @ref is set to %0. However, + * if the initialization fails after the UBI device was registered in the + * driver core subsystem, this function takes a reference to @ubi->dev, because + * otherwise the release function ('dev_release()') would free whole @ubi + * object. The @ref argument is set to %1 in this case. The caller has to put + * this reference. * * This function returns zero in case of success and a negative error code in - * case of failure. Note, this function destroys all volumes if it fails. + * case of failure. */ -static int uif_init(struct ubi_device *ubi) +static int uif_init(struct ubi_device *ubi, int *ref) { int i, err; dev_t dev; + *ref = 0; sprintf(ubi->ubi_name, UBI_NAME_STR "%d", ubi->ubi_num); /* @@ -506,7 +502,7 @@ static int uif_init(struct ubi_device *ubi) goto out_unreg; } - err = ubi_sysfs_init(ubi); + err = ubi_sysfs_init(ubi, ref); if (err) goto out_sysfs; @@ -524,6 +520,8 @@ static int uif_init(struct ubi_device *ubi) out_volumes: kill_volumes(ubi); out_sysfs: + if (*ref) + get_device(&ubi->dev); ubi_sysfs_close(ubi); cdev_del(&ubi->cdev); out_unreg: @@ -877,7 +875,7 @@ static int ubi_reboot_notifier(struct notifier_block *n, unsigned long state, int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset) { struct ubi_device *ubi; - int i, err, do_free = 1; + int i, err, ref = 0; /* * Check if we already have the same MTD device attached. @@ -977,9 +975,9 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset) goto out_detach; } - err = uif_init(ubi); + err = uif_init(ubi, &ref); if (err) - goto out_nofree; + goto out_detach; ubi->bgt_thread = kthread_create(ubi_thread, ubi, ubi->bgt_name); if (IS_ERR(ubi->bgt_thread)) { @@ -1027,12 +1025,8 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset) out_uif: uif_close(ubi); -out_nofree: - do_free = 0; out_detach: ubi_wl_close(ubi); - if (do_free) - free_user_volumes(ubi); free_internal_volumes(ubi); vfree(ubi->vtbl); out_free: @@ -1041,7 +1035,10 @@ out_free: #ifdef CONFIG_MTD_UBI_DEBUG_PARANOID vfree(ubi->dbg_peb_buf); #endif - kfree(ubi); + if (ref) + put_device(&ubi->dev); + else + kfree(ubi); return err; } @@ -1098,7 +1095,7 @@ int ubi_detach_mtd_dev(int ubi_num, int anyway) /* * Get a reference to the device in order to prevent 'dev_release()' - * from freeing @ubi object. + * from freeing the @ubi object. */ get_device(&ubi->dev); -- cgit v1.2.3 From adbf05e3ec6ea380ba145b6fa89d9125ed76eb98 Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Wed, 20 Jan 2010 10:28:58 +0200 Subject: UBI: simplify debugging return codes UBI debugging functions were a little bit over-engineered and returned more error codes than needed, and the callers had to do useless checks. Simplify the return codes. Impact: only debugging code is affected, which means that for non-developers this is a no-op patch. Signed-off-by: Artem Bityutskiy --- drivers/mtd/ubi/io.c | 50 +++++++++++++++++++++++++------------------------- drivers/mtd/ubi/scan.c | 11 ++++------- drivers/mtd/ubi/wl.c | 17 ++++++++--------- 3 files changed, 37 insertions(+), 41 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index 8aa51e7a6a7d..a2501299a67c 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -143,7 +143,7 @@ int ubi_io_read(const struct ubi_device *ubi, void *buf, int pnum, int offset, err = paranoid_check_not_bad(ubi, pnum); if (err) - return err > 0 ? -EINVAL : err; + return err; addr = (loff_t)pnum * ubi->peb_size + offset; retry: @@ -236,12 +236,12 @@ int ubi_io_write(struct ubi_device *ubi, const void *buf, int pnum, int offset, err = paranoid_check_not_bad(ubi, pnum); if (err) - return err > 0 ? -EINVAL : err; + return err; /* The area we are writing to has to contain all 0xFF bytes */ err = ubi_dbg_check_all_ff(ubi, pnum, offset, len); if (err) - return err > 0 ? -EINVAL : err; + return err; if (offset >= ubi->leb_start) { /* @@ -250,10 +250,10 @@ int ubi_io_write(struct ubi_device *ubi, const void *buf, int pnum, int offset, */ err = paranoid_check_peb_ec_hdr(ubi, pnum); if (err) - return err > 0 ? -EINVAL : err; + return err; err = paranoid_check_peb_vid_hdr(ubi, pnum); if (err) - return err > 0 ? -EINVAL : err; + return err; } if (ubi_dbg_is_write_failure()) { @@ -348,7 +348,7 @@ retry: err = ubi_dbg_check_all_ff(ubi, pnum, 0, ubi->peb_size); if (err) - return err > 0 ? -EINVAL : err; + return err; if (ubi_dbg_is_erase_failure() && !err) { dbg_err("cannot erase PEB %d (emulated)", pnum); @@ -542,7 +542,7 @@ int ubi_io_sync_erase(struct ubi_device *ubi, int pnum, int torture) err = paranoid_check_not_bad(ubi, pnum); if (err != 0) - return err > 0 ? -EINVAL : err; + return err; if (ubi->ro_mode) { ubi_err("read-only mode"); @@ -819,7 +819,7 @@ int ubi_io_write_ec_hdr(struct ubi_device *ubi, int pnum, err = paranoid_check_ec_hdr(ubi, pnum, ec_hdr); if (err) - return -EINVAL; + return err; err = ubi_io_write(ubi, ec_hdr, pnum, 0, ubi->ec_hdr_alsize); return err; @@ -1083,7 +1083,7 @@ int ubi_io_write_vid_hdr(struct ubi_device *ubi, int pnum, err = paranoid_check_peb_ec_hdr(ubi, pnum); if (err) - return err > 0 ? -EINVAL : err; + return err; vid_hdr->magic = cpu_to_be32(UBI_VID_HDR_MAGIC); vid_hdr->version = UBI_VERSION; @@ -1092,7 +1092,7 @@ int ubi_io_write_vid_hdr(struct ubi_device *ubi, int pnum, err = paranoid_check_vid_hdr(ubi, pnum, vid_hdr); if (err) - return -EINVAL; + return err; p = (char *)vid_hdr - ubi->vid_hdr_shift; err = ubi_io_write(ubi, p, pnum, ubi->vid_hdr_aloffset, @@ -1107,8 +1107,8 @@ int ubi_io_write_vid_hdr(struct ubi_device *ubi, int pnum, * @ubi: UBI device description object * @pnum: physical eraseblock number to check * - * This function returns zero if the physical eraseblock is good, a positive - * number if it is bad and a negative error code if an error occurred. + * This function returns zero if the physical eraseblock is good, %-EINVAL if + * it is bad and a negative error code if an error occurred. */ static int paranoid_check_not_bad(const struct ubi_device *ubi, int pnum) { @@ -1120,7 +1120,7 @@ static int paranoid_check_not_bad(const struct ubi_device *ubi, int pnum) ubi_err("paranoid check failed for PEB %d", pnum); ubi_dbg_dump_stack(); - return err; + return err > 0 ? -EINVAL : err; } /** @@ -1130,7 +1130,7 @@ static int paranoid_check_not_bad(const struct ubi_device *ubi, int pnum) * @ec_hdr: the erase counter header to check * * This function returns zero if the erase counter header contains valid - * values, and %1 if not. + * values, and %-EINVAL if not. */ static int paranoid_check_ec_hdr(const struct ubi_device *ubi, int pnum, const struct ubi_ec_hdr *ec_hdr) @@ -1156,7 +1156,7 @@ static int paranoid_check_ec_hdr(const struct ubi_device *ubi, int pnum, fail: ubi_dbg_dump_ec_hdr(ec_hdr); ubi_dbg_dump_stack(); - return 1; + return -EINVAL; } /** @@ -1164,8 +1164,8 @@ fail: * @ubi: UBI device description object * @pnum: the physical eraseblock number to check * - * This function returns zero if the erase counter header is all right, %1 if - * not, and a negative error code if an error occurred. + * This function returns zero if the erase counter header is all right and and + * a negative error code if not or if an error occurred. */ static int paranoid_check_peb_ec_hdr(const struct ubi_device *ubi, int pnum) { @@ -1188,7 +1188,7 @@ static int paranoid_check_peb_ec_hdr(const struct ubi_device *ubi, int pnum) ubi_err("paranoid check failed for PEB %d", pnum); ubi_dbg_dump_ec_hdr(ec_hdr); ubi_dbg_dump_stack(); - err = 1; + err = -EINVAL; goto exit; } @@ -1206,7 +1206,7 @@ exit: * @vid_hdr: the volume identifier header to check * * This function returns zero if the volume identifier header is all right, and - * %1 if not. + * %-EINVAL if not. */ static int paranoid_check_vid_hdr(const struct ubi_device *ubi, int pnum, const struct ubi_vid_hdr *vid_hdr) @@ -1233,7 +1233,7 @@ fail: ubi_err("paranoid check failed for PEB %d", pnum); ubi_dbg_dump_vid_hdr(vid_hdr); ubi_dbg_dump_stack(); - return 1; + return -EINVAL; } @@ -1243,7 +1243,7 @@ fail: * @pnum: the physical eraseblock number to check * * This function returns zero if the volume identifier header is all right, - * %1 if not, and a negative error code if an error occurred. + * and a negative error code if not or if an error occurred. */ static int paranoid_check_peb_vid_hdr(const struct ubi_device *ubi, int pnum) { @@ -1270,7 +1270,7 @@ static int paranoid_check_peb_vid_hdr(const struct ubi_device *ubi, int pnum) ubi_err("paranoid check failed for PEB %d", pnum); ubi_dbg_dump_vid_hdr(vid_hdr); ubi_dbg_dump_stack(); - err = 1; + err = -EINVAL; goto exit; } @@ -1289,8 +1289,8 @@ exit: * @len: the length of the region to check * * This function returns zero if only 0xFF bytes are present at offset - * @offset of the physical eraseblock @pnum, %1 if not, and a negative error - * code if an error occurred. + * @offset of the physical eraseblock @pnum, and a negative error code if not + * or if an error occurred. */ int ubi_dbg_check_all_ff(struct ubi_device *ubi, int pnum, int offset, int len) { @@ -1321,7 +1321,7 @@ fail: ubi_msg("hex dump of the %d-%d region", offset, offset + len); print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, ubi->dbg_peb_buf, len, 1); - err = 1; + err = -EINVAL; error: ubi_dbg_dump_stack(); mutex_unlock(&ubi->dbg_buf_mutex); diff --git a/drivers/mtd/ubi/scan.c b/drivers/mtd/ubi/scan.c index 90af61a2c3e4..594184bbd56a 100644 --- a/drivers/mtd/ubi/scan.c +++ b/drivers/mtd/ubi/scan.c @@ -974,11 +974,8 @@ struct ubi_scan_info *ubi_scan(struct ubi_device *ubi) seb->ec = si->mean_ec; err = paranoid_check_si(ubi, si); - if (err) { - if (err > 0) - err = -EINVAL; + if (err) goto out_vidh; - } ubi_free_vid_hdr(ubi, vidh); kfree(ech); @@ -1086,8 +1083,8 @@ void ubi_scan_destroy_si(struct ubi_scan_info *si) * @ubi: UBI device description object * @si: scanning information * - * This function returns zero if the scanning information is all right, %1 if - * not and a negative error code if an error occurred. + * This function returns zero if the scanning information is all right, and a + * negative error code if not or if an error occurred. */ static int paranoid_check_si(struct ubi_device *ubi, struct ubi_scan_info *si) { @@ -1346,7 +1343,7 @@ bad_vid_hdr: out: ubi_dbg_dump_stack(); - return 1; + return -EINVAL; } #endif /* CONFIG_MTD_UBI_DEBUG_PARANOID */ diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index 600c7229d5cf..f64ddabd4ac8 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -464,7 +464,7 @@ retry: ubi->peb_size - ubi->vid_hdr_aloffset); if (err) { ubi_err("new PEB %d does not contain all 0xFF bytes", e->pnum); - return err > 0 ? -EINVAL : err; + return err; } return e->pnum; @@ -513,7 +513,7 @@ static int sync_erase(struct ubi_device *ubi, struct ubi_wl_entry *e, dbg_wl("erase PEB %d, old EC %llu", e->pnum, ec); err = paranoid_check_ec(ubi, e->pnum, e->ec); - if (err > 0) + if (err) return -EINVAL; ec_hdr = kzalloc(ubi->ec_hdr_alsize, GFP_NOFS); @@ -1572,8 +1572,7 @@ void ubi_wl_close(struct ubi_device *ubi) * @ec: the erase counter to check * * This function returns zero if the erase counter of physical eraseblock @pnum - * is equivalent to @ec, %1 if not, and a negative error code if an error - * occurred. + * is equivalent to @ec, and a negative error code if not or if an error occurred. */ static int paranoid_check_ec(struct ubi_device *ubi, int pnum, int ec) { @@ -1611,8 +1610,8 @@ out_free: * @e: the wear-leveling entry to check * @root: the root of the tree * - * This function returns zero if @e is in the @root RB-tree and %1 if it is - * not. + * This function returns zero if @e is in the @root RB-tree and %-EINVAL if it + * is not. */ static int paranoid_check_in_wl_tree(struct ubi_wl_entry *e, struct rb_root *root) @@ -1623,7 +1622,7 @@ static int paranoid_check_in_wl_tree(struct ubi_wl_entry *e, ubi_err("paranoid check failed for PEB %d, EC %d, RB-tree %p ", e->pnum, e->ec, root); ubi_dbg_dump_stack(); - return 1; + return -EINVAL; } /** @@ -1632,7 +1631,7 @@ static int paranoid_check_in_wl_tree(struct ubi_wl_entry *e, * @ubi: UBI device description object * @e: the wear-leveling entry to check * - * This function returns zero if @e is in @ubi->pq and %1 if it is not. + * This function returns zero if @e is in @ubi->pq and %-EINVAL if it is not. */ static int paranoid_check_in_pq(struct ubi_device *ubi, struct ubi_wl_entry *e) { @@ -1647,6 +1646,6 @@ static int paranoid_check_in_pq(struct ubi_device *ubi, struct ubi_wl_entry *e) ubi_err("paranoid check failed for PEB %d, EC %d, Protect queue", e->pnum, e->ec); ubi_dbg_dump_stack(); - return 1; + return -EINVAL; } #endif /* CONFIG_MTD_UBI_DEBUG_PARANOID */ -- cgit v1.2.3 From 6e9065d756df5dac6dc02b94b82b4f5dbbf38caf Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Mon, 25 Jan 2010 17:09:30 +0200 Subject: UBI: add write checking Add an extra debugging check function which validates writes. After every write it reads the data back, compares it with the original data, and complains if they mismatch. Useful for debugging. No-op if extra debugging checks are disabled. Signed-off-by: Artem Bityutskiy --- drivers/mtd/ubi/debug.h | 4 +++ drivers/mtd/ubi/io.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) (limited to 'drivers') diff --git a/drivers/mtd/ubi/debug.h b/drivers/mtd/ubi/debug.h index f30bcb372c05..17a107129726 100644 --- a/drivers/mtd/ubi/debug.h +++ b/drivers/mtd/ubi/debug.h @@ -96,8 +96,11 @@ void ubi_dbg_dump_flash(struct ubi_device *ubi, int pnum, int offset, int len); #ifdef CONFIG_MTD_UBI_DEBUG_PARANOID int ubi_dbg_check_all_ff(struct ubi_device *ubi, int pnum, int offset, int len); +int ubi_dbg_check_write(struct ubi_device *ubi, const void *buf, int pnum, + int offset, int len); #else #define ubi_dbg_check_all_ff(ubi, pnum, offset, len) 0 +#define ubi_dbg_check_write(ubi, buf, pnum, offset, len) 0 #endif #ifdef CONFIG_MTD_UBI_DEBUG_DISABLE_BGT @@ -176,6 +179,7 @@ static inline int ubi_dbg_is_erase_failure(void) #define ubi_dbg_is_write_failure() 0 #define ubi_dbg_is_erase_failure() 0 #define ubi_dbg_check_all_ff(ubi, pnum, offset, len) 0 +#define ubi_dbg_check_write(ubi, buf, pnum, offset, len) 0 #endif /* !CONFIG_MTD_UBI_DEBUG */ #endif /* !__UBI_DEBUG_H__ */ diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index a2501299a67c..b4ecc84c7549 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -273,6 +273,21 @@ int ubi_io_write(struct ubi_device *ubi, const void *buf, int pnum, int offset, } else ubi_assert(written == len); + if (!err) { + err = ubi_dbg_check_write(ubi, buf, pnum, offset, len); + if (err) + return err; + + /* + * Since we always write sequentially, the rest of the PEB has + * to contain only 0xFF bytes. + */ + offset += len; + len = ubi->peb_size - offset; + if (len) + err = ubi_dbg_check_all_ff(ubi, pnum, offset, len); + } + return err; } @@ -1281,6 +1296,61 @@ exit: return err; } +/** + * ubi_dbg_check_write - make sure write succeeded. + * @ubi: UBI device description object + * @buf: buffer with data which were written + * @pnum: physical eraseblock number the data were written to + * @offset: offset within the physical eraseblock the data were written to + * @len: how many bytes were written + * + * This functions reads data which were recently written and compares it with + * the original data buffer - the data have to match. Returns zero if the data + * match and a negative error code if not or in case of failure. + */ +int ubi_dbg_check_write(struct ubi_device *ubi, const void *buf, int pnum, + int offset, int len) +{ + int err, i; + + mutex_lock(&ubi->dbg_buf_mutex); + err = ubi_io_read(ubi, ubi->dbg_peb_buf, pnum, offset, len); + if (err) + goto out_unlock; + + for (i = 0; i < len; i++) { + uint8_t c = ((uint8_t *)buf)[i]; + uint8_t c1 = ((uint8_t *)ubi->dbg_peb_buf)[i]; + int dump_len; + + if (c == c1) + continue; + + ubi_err("paranoid check failed for PEB %d:%d, len %d", + pnum, offset, len); + ubi_msg("data differ at position %d", i); + dump_len = max_t(int, 128, len - i); + ubi_msg("hex dump of the original buffer from %d to %d", + i, i + dump_len); + print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, + buf + i, dump_len, 1); + ubi_msg("hex dump of the read buffer from %d to %d", + i, i + dump_len); + print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, + ubi->dbg_peb_buf + i, dump_len, 1); + ubi_dbg_dump_stack(); + err = -EINVAL; + goto out_unlock; + } + mutex_unlock(&ubi->dbg_buf_mutex); + + return 0; + +out_unlock: + mutex_unlock(&ubi->dbg_buf_mutex); + return err; +} + /** * ubi_dbg_check_all_ff - check that a region of flash is empty. * @ubi: UBI device description object -- cgit v1.2.3 From 272ca655090978bdaa2630fc44fb2c03da5576fd Mon Sep 17 00:00:00 2001 From: Ira Snyder Date: Wed, 6 Jan 2010 13:33:59 +0000 Subject: fsldma: reduce kernel text size Some of the functions are written in a way where they use multiple reads and writes where a single read/write pair could suffice. This shrinks the kernel text size measurably, while making the functions easier to understand. add/remove: 0/0 grow/shrink: 1/4 up/down: 4/-196 (-192) function old new delta fsl_chan_set_request_count 120 124 +4 dma_halt 300 272 -28 fsl_chan_set_src_loop_size 208 156 -52 fsl_chan_set_dest_loop_size 208 156 -52 fsl_chan_xfer_ld_queue 500 436 -64 Signed-off-by: Ira W. Snyder Signed-off-by: Dan Williams --- drivers/dma/fsldma.c | 83 ++++++++++++++++++++++++++++------------------------ 1 file changed, 45 insertions(+), 38 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 296f9e747fac..0bad741765c6 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -143,43 +143,45 @@ static int dma_is_idle(struct fsl_dma_chan *fsl_chan) static void dma_start(struct fsl_dma_chan *fsl_chan) { - u32 mr_set = 0; - - if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { - DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32); - mr_set |= FSL_DMA_MR_EMP_EN; - } else if ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, - DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) - & ~FSL_DMA_MR_EMP_EN, 32); + u32 mode; + + mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); + + if ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { + if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { + DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32); + mode |= FSL_DMA_MR_EMP_EN; + } else { + mode &= ~FSL_DMA_MR_EMP_EN; + } } if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT) - mr_set |= FSL_DMA_MR_EMS_EN; + mode |= FSL_DMA_MR_EMS_EN; else - mr_set |= FSL_DMA_MR_CS; + mode |= FSL_DMA_MR_CS; - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, - DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) - | mr_set, 32); + DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); } static void dma_halt(struct fsl_dma_chan *fsl_chan) { + u32 mode; int i; - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, - DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA, - 32); - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, - DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS - | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32); + mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); + mode |= FSL_DMA_MR_CA; + DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); + + mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA); + DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); for (i = 0; i < 100; i++) { if (dma_is_idle(fsl_chan)) break; udelay(10); } + if (i >= 100 && !dma_is_idle(fsl_chan)) dev_err(fsl_chan->dev, "DMA halt timeout!\n"); } @@ -231,22 +233,23 @@ static void append_ld_queue(struct fsl_dma_chan *fsl_chan, */ static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size) { + u32 mode; + + mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); + switch (size) { case 0: - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, - DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & - (~FSL_DMA_MR_SAHE), 32); + mode &= ~FSL_DMA_MR_SAHE; break; case 1: case 2: case 4: case 8: - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, - DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | - FSL_DMA_MR_SAHE | (__ilog2(size) << 14), - 32); + mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); break; } + + DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); } /** @@ -262,22 +265,23 @@ static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size) */ static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size) { + u32 mode; + + mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); + switch (size) { case 0: - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, - DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & - (~FSL_DMA_MR_DAHE), 32); + mode &= ~FSL_DMA_MR_DAHE; break; case 1: case 2: case 4: case 8: - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, - DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | - FSL_DMA_MR_DAHE | (__ilog2(size) << 16), - 32); + mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); break; } + + DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); } /** @@ -294,11 +298,14 @@ static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size) */ static void fsl_chan_set_request_count(struct fsl_dma_chan *fsl_chan, int size) { + u32 mode; + BUG_ON(size > 1024); - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, - DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) - | ((__ilog2(size) << 24) & 0x0f000000), - 32); + + mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); + mode |= (__ilog2(size) << 24) & 0x0f000000; + + DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); } /** -- cgit v1.2.3 From 4ce0e953f6286777452bf07c83056342d6b9b257 Mon Sep 17 00:00:00 2001 From: Ira Snyder Date: Wed, 6 Jan 2010 13:34:00 +0000 Subject: fsldma: remove unused structure members Remove some unused members from the fsldma data structures. A few trivial uses of struct resource were converted to use the stack rather than keeping the memory allocated for the lifetime of the driver. Signed-off-by: Ira W. Snyder Signed-off-by: Dan Williams --- drivers/dma/fsldma.c | 17 ++++++++--------- drivers/dma/fsldma.h | 4 ---- 2 files changed, 8 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 0bad741765c6..0b4e6383f480 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -1072,6 +1072,7 @@ static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev, struct device_node *node, u32 feature, const char *compatible) { struct fsl_dma_chan *new_fsl_chan; + struct resource res; int err; /* alloc channel */ @@ -1083,7 +1084,7 @@ static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev, } /* get dma channel register base */ - err = of_address_to_resource(node, 0, &new_fsl_chan->reg); + err = of_address_to_resource(node, 0, &res); if (err) { dev_err(fdev->dev, "Can't get %s property 'reg'\n", node->full_name); @@ -1101,10 +1102,8 @@ static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev, WARN_ON(fdev->feature != new_fsl_chan->feature); new_fsl_chan->dev = fdev->dev; - new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start, - new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1); - - new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7; + new_fsl_chan->reg_base = ioremap(res.start, resource_size(&res)); + new_fsl_chan->id = ((res.start - 0x100) & 0xfff) >> 7; if (new_fsl_chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { dev_err(fdev->dev, "There is no %d channel!\n", new_fsl_chan->id); @@ -1183,6 +1182,7 @@ static int __devinit of_fsl_dma_probe(struct of_device *dev, int err; struct fsl_dma_device *fdev; struct device_node *child; + struct resource res; fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL); if (!fdev) { @@ -1193,7 +1193,7 @@ static int __devinit of_fsl_dma_probe(struct of_device *dev, INIT_LIST_HEAD(&fdev->common.channels); /* get DMA controller register base */ - err = of_address_to_resource(dev->node, 0, &fdev->reg); + err = of_address_to_resource(dev->node, 0, &res); if (err) { dev_err(&dev->dev, "Can't get %s property 'reg'\n", dev->node->full_name); @@ -1202,9 +1202,8 @@ static int __devinit of_fsl_dma_probe(struct of_device *dev, dev_info(&dev->dev, "Probe the Freescale DMA driver for %s " "controller at 0x%llx...\n", - match->compatible, (unsigned long long)fdev->reg.start); - fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end - - fdev->reg.start + 1); + match->compatible, (unsigned long long)res.start); + fdev->reg_base = ioremap(res.start, resource_size(&res)); dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index 0df14cbb8ca3..dbb5b5cce4c2 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -92,8 +92,6 @@ struct fsl_desc_sw { struct list_head node; struct list_head tx_list; struct dma_async_tx_descriptor async_tx; - struct list_head *ld; - void *priv; } __attribute__((aligned(32))); struct fsl_dma_chan_regs { @@ -111,7 +109,6 @@ struct fsl_dma_chan; struct fsl_dma_device { void __iomem *reg_base; /* DGSR register base */ - struct resource reg; /* Resource for register */ struct device *dev; struct dma_device common; struct fsl_dma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE]; @@ -138,7 +135,6 @@ struct fsl_dma_chan { struct dma_chan common; /* DMA common channel */ struct dma_pool *desc_pool; /* Descriptors pool */ struct device *dev; /* Channel device */ - struct resource reg; /* Resource for register */ int irq; /* Channel IRQ */ int id; /* Raw id of this channel */ struct tasklet_struct tasklet; -- cgit v1.2.3 From a4f56d4b103d4e5d1a59a9118db0185a6bd1a83b Mon Sep 17 00:00:00 2001 From: Ira Snyder Date: Wed, 6 Jan 2010 13:34:01 +0000 Subject: fsldma: rename struct fsl_dma_chan to struct fsldma_chan This is the beginning of a cleanup which will change all instances of "fsl_dma" to "fsldma" to match the name of the driver itself. Signed-off-by: Ira W. Snyder Signed-off-by: Dan Williams --- drivers/dma/fsldma.c | 128 +++++++++++++++++++++++++++------------------------ drivers/dma/fsldma.h | 26 +++++------ 2 files changed, 81 insertions(+), 73 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 0b4e6383f480..6795d96e3629 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -37,7 +37,7 @@ #include #include "fsldma.h" -static void dma_init(struct fsl_dma_chan *fsl_chan) +static void dma_init(struct fsldma_chan *fsl_chan) { /* Reset the channel */ DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32); @@ -64,23 +64,23 @@ static void dma_init(struct fsl_dma_chan *fsl_chan) } -static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val) +static void set_sr(struct fsldma_chan *fsl_chan, u32 val) { DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32); } -static u32 get_sr(struct fsl_dma_chan *fsl_chan) +static u32 get_sr(struct fsldma_chan *fsl_chan) { return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32); } -static void set_desc_cnt(struct fsl_dma_chan *fsl_chan, +static void set_desc_cnt(struct fsldma_chan *fsl_chan, struct fsl_dma_ld_hw *hw, u32 count) { hw->count = CPU_TO_DMA(fsl_chan, count, 32); } -static void set_desc_src(struct fsl_dma_chan *fsl_chan, +static void set_desc_src(struct fsldma_chan *fsl_chan, struct fsl_dma_ld_hw *hw, dma_addr_t src) { u64 snoop_bits; @@ -90,7 +90,7 @@ static void set_desc_src(struct fsl_dma_chan *fsl_chan, hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64); } -static void set_desc_dest(struct fsl_dma_chan *fsl_chan, +static void set_desc_dest(struct fsldma_chan *fsl_chan, struct fsl_dma_ld_hw *hw, dma_addr_t dest) { u64 snoop_bits; @@ -100,7 +100,7 @@ static void set_desc_dest(struct fsl_dma_chan *fsl_chan, hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64); } -static void set_desc_next(struct fsl_dma_chan *fsl_chan, +static void set_desc_next(struct fsldma_chan *fsl_chan, struct fsl_dma_ld_hw *hw, dma_addr_t next) { u64 snoop_bits; @@ -110,38 +110,38 @@ static void set_desc_next(struct fsl_dma_chan *fsl_chan, hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64); } -static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) +static void set_cdar(struct fsldma_chan *fsl_chan, dma_addr_t addr) { DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64); } -static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan) +static dma_addr_t get_cdar(struct fsldma_chan *fsl_chan) { return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN; } -static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) +static void set_ndar(struct fsldma_chan *fsl_chan, dma_addr_t addr) { DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64); } -static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan) +static dma_addr_t get_ndar(struct fsldma_chan *fsl_chan) { return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64); } -static u32 get_bcr(struct fsl_dma_chan *fsl_chan) +static u32 get_bcr(struct fsldma_chan *fsl_chan) { return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32); } -static int dma_is_idle(struct fsl_dma_chan *fsl_chan) +static int dma_is_idle(struct fsldma_chan *fsl_chan) { u32 sr = get_sr(fsl_chan); return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); } -static void dma_start(struct fsl_dma_chan *fsl_chan) +static void dma_start(struct fsldma_chan *fsl_chan) { u32 mode; @@ -164,7 +164,7 @@ static void dma_start(struct fsl_dma_chan *fsl_chan) DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); } -static void dma_halt(struct fsl_dma_chan *fsl_chan) +static void dma_halt(struct fsldma_chan *fsl_chan) { u32 mode; int i; @@ -186,7 +186,7 @@ static void dma_halt(struct fsl_dma_chan *fsl_chan) dev_err(fsl_chan->dev, "DMA halt timeout!\n"); } -static void set_ld_eol(struct fsl_dma_chan *fsl_chan, +static void set_ld_eol(struct fsldma_chan *fsl_chan, struct fsl_desc_sw *desc) { u64 snoop_bits; @@ -199,7 +199,7 @@ static void set_ld_eol(struct fsl_dma_chan *fsl_chan, | snoop_bits, 64); } -static void append_ld_queue(struct fsl_dma_chan *fsl_chan, +static void append_ld_queue(struct fsldma_chan *fsl_chan, struct fsl_desc_sw *new_desc) { struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev); @@ -231,7 +231,7 @@ static void append_ld_queue(struct fsl_dma_chan *fsl_chan, * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, * SA + 1 ... and so on. */ -static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size) +static void fsl_chan_set_src_loop_size(struct fsldma_chan *fsl_chan, int size) { u32 mode; @@ -263,7 +263,7 @@ static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size) * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, * TA + 1 ... and so on. */ -static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size) +static void fsl_chan_set_dest_loop_size(struct fsldma_chan *fsl_chan, int size) { u32 mode; @@ -296,7 +296,7 @@ static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size) * * A size of 0 disables external pause control. The maximum size is 1024. */ -static void fsl_chan_set_request_count(struct fsl_dma_chan *fsl_chan, int size) +static void fsl_chan_set_request_count(struct fsldma_chan *fsl_chan, int size) { u32 mode; @@ -317,7 +317,7 @@ static void fsl_chan_set_request_count(struct fsl_dma_chan *fsl_chan, int size) * The DMA Request Count feature should be used in addition to this feature * to set the number of bytes to transfer before pausing the channel. */ -static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int enable) +static void fsl_chan_toggle_ext_pause(struct fsldma_chan *fsl_chan, int enable) { if (enable) fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; @@ -335,7 +335,7 @@ static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int enable) * transfer immediately. The DMA channel will wait for the * control pin asserted. */ -static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable) +static void fsl_chan_toggle_ext_start(struct fsldma_chan *fsl_chan, int enable) { if (enable) fsl_chan->feature |= FSL_DMA_CHAN_START_EXT; @@ -345,7 +345,7 @@ static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable) static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) { - struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan); + struct fsldma_chan *fsl_chan = to_fsl_chan(tx->chan); struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); struct fsl_desc_sw *child; unsigned long flags; @@ -379,7 +379,7 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) * Return - The descriptor allocated. NULL for failed. */ static struct fsl_desc_sw *fsl_dma_alloc_descriptor( - struct fsl_dma_chan *fsl_chan) + struct fsldma_chan *fsl_chan) { dma_addr_t pdesc; struct fsl_desc_sw *desc_sw; @@ -408,7 +408,7 @@ static struct fsl_desc_sw *fsl_dma_alloc_descriptor( */ static int fsl_dma_alloc_chan_resources(struct dma_chan *chan) { - struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); + struct fsldma_chan *fsl_chan = to_fsl_chan(chan); /* Has this channel already been allocated? */ if (fsl_chan->desc_pool) @@ -435,7 +435,7 @@ static int fsl_dma_alloc_chan_resources(struct dma_chan *chan) */ static void fsl_dma_free_chan_resources(struct dma_chan *chan) { - struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); + struct fsldma_chan *fsl_chan = to_fsl_chan(chan); struct fsl_desc_sw *desc, *_desc; unsigned long flags; @@ -459,7 +459,7 @@ static void fsl_dma_free_chan_resources(struct dma_chan *chan) static struct dma_async_tx_descriptor * fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags) { - struct fsl_dma_chan *fsl_chan; + struct fsldma_chan *fsl_chan; struct fsl_desc_sw *new; if (!chan) @@ -489,7 +489,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, size_t len, unsigned long flags) { - struct fsl_dma_chan *fsl_chan; + struct fsldma_chan *fsl_chan; struct fsl_desc_sw *first = NULL, *prev = NULL, *new; struct list_head *list; size_t copy; @@ -575,7 +575,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_data_direction direction, unsigned long flags) { - struct fsl_dma_chan *fsl_chan; + struct fsldma_chan *fsl_chan; struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; struct fsl_dma_slave *slave; struct list_head *tx_list; @@ -759,7 +759,7 @@ fail: static void fsl_dma_device_terminate_all(struct dma_chan *chan) { - struct fsl_dma_chan *fsl_chan; + struct fsldma_chan *fsl_chan; struct fsl_desc_sw *desc, *tmp; unsigned long flags; @@ -786,7 +786,7 @@ static void fsl_dma_device_terminate_all(struct dma_chan *chan) * fsl_dma_update_completed_cookie - Update the completed cookie. * @fsl_chan : Freescale DMA channel */ -static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan) +static void fsl_dma_update_completed_cookie(struct fsldma_chan *fsl_chan) { struct fsl_desc_sw *cur_desc, *desc; dma_addr_t ld_phy; @@ -820,7 +820,7 @@ static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan) * If 'in_intr' is set, the function will move the link descriptor to * the recycle list. Otherwise, free it directly. */ -static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan) +static void fsl_chan_ld_cleanup(struct fsldma_chan *fsl_chan) { struct fsl_desc_sw *desc, *_desc; unsigned long flags; @@ -864,7 +864,7 @@ static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan) * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue. * @fsl_chan : Freescale DMA channel */ -static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan) +static void fsl_chan_xfer_ld_queue(struct fsldma_chan *fsl_chan) { struct list_head *ld_node; dma_addr_t next_dest_addr; @@ -912,7 +912,7 @@ out_unlock: */ static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan) { - struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); + struct fsldma_chan *fsl_chan = to_fsl_chan(chan); #ifdef FSL_DMA_LD_DEBUG struct fsl_desc_sw *ld; @@ -949,7 +949,7 @@ static enum dma_status fsl_dma_is_complete(struct dma_chan *chan, dma_cookie_t *done, dma_cookie_t *used) { - struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); + struct fsldma_chan *fsl_chan = to_fsl_chan(chan); dma_cookie_t last_used; dma_cookie_t last_complete; @@ -969,7 +969,7 @@ static enum dma_status fsl_dma_is_complete(struct dma_chan *chan, static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data) { - struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; + struct fsldma_chan *fsl_chan = data; u32 stat; int update_cookie = 0; int xfer_ld_q = 0; @@ -1050,9 +1050,9 @@ static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data) static irqreturn_t fsl_dma_do_interrupt(int irq, void *data) { - struct fsl_dma_device *fdev = (struct fsl_dma_device *)data; - u32 gsr; + struct fsldma_device *fdev = data; int ch_nr; + u32 gsr; gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base) : in_le32(fdev->reg_base); @@ -1064,19 +1064,23 @@ static irqreturn_t fsl_dma_do_interrupt(int irq, void *data) static void dma_do_tasklet(unsigned long data) { - struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; + struct fsldma_chan *fsl_chan = (struct fsldma_chan *)data; fsl_chan_ld_cleanup(fsl_chan); } -static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev, +/*----------------------------------------------------------------------------*/ +/* OpenFirmware Subsystem */ +/*----------------------------------------------------------------------------*/ + +static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, struct device_node *node, u32 feature, const char *compatible) { - struct fsl_dma_chan *new_fsl_chan; + struct fsldma_chan *new_fsl_chan; struct resource res; int err; /* alloc channel */ - new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL); + new_fsl_chan = kzalloc(sizeof(*new_fsl_chan), GFP_KERNEL); if (!new_fsl_chan) { dev_err(fdev->dev, "No free memory for allocating " "dma channels!\n"); @@ -1167,7 +1171,7 @@ err_no_reg: return err; } -static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan) +static void fsl_dma_chan_remove(struct fsldma_chan *fchan) { if (fchan->irq != NO_IRQ) free_irq(fchan->irq, fchan); @@ -1176,15 +1180,15 @@ static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan) kfree(fchan); } -static int __devinit of_fsl_dma_probe(struct of_device *dev, +static int __devinit fsldma_of_probe(struct of_device *dev, const struct of_device_id *match) { int err; - struct fsl_dma_device *fdev; + struct fsldma_device *fdev; struct device_node *child; struct resource res; - fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL); + fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); if (!fdev) { dev_err(&dev->dev, "No enough memory for 'priv'\n"); return -ENOMEM; @@ -1256,9 +1260,9 @@ err_no_reg: return err; } -static int of_fsl_dma_remove(struct of_device *of_dev) +static int fsldma_of_remove(struct of_device *of_dev) { - struct fsl_dma_device *fdev; + struct fsldma_device *fdev; unsigned int i; fdev = dev_get_drvdata(&of_dev->dev); @@ -1280,39 +1284,43 @@ static int of_fsl_dma_remove(struct of_device *of_dev) return 0; } -static struct of_device_id of_fsl_dma_ids[] = { +static struct of_device_id fsldma_of_ids[] = { { .compatible = "fsl,eloplus-dma", }, { .compatible = "fsl,elo-dma", }, {} }; -static struct of_platform_driver of_fsl_dma_driver = { - .name = "fsl-elo-dma", - .match_table = of_fsl_dma_ids, - .probe = of_fsl_dma_probe, - .remove = of_fsl_dma_remove, +static struct of_platform_driver fsldma_of_driver = { + .name = "fsl-elo-dma", + .match_table = fsldma_of_ids, + .probe = fsldma_of_probe, + .remove = fsldma_of_remove, }; -static __init int of_fsl_dma_init(void) +/*----------------------------------------------------------------------------*/ +/* Module Init / Exit */ +/*----------------------------------------------------------------------------*/ + +static __init int fsldma_init(void) { int ret; pr_info("Freescale Elo / Elo Plus DMA driver\n"); - ret = of_register_platform_driver(&of_fsl_dma_driver); + ret = of_register_platform_driver(&fsldma_of_driver); if (ret) pr_err("fsldma: failed to register platform driver\n"); return ret; } -static void __exit of_fsl_dma_exit(void) +static void __exit fsldma_exit(void) { - of_unregister_platform_driver(&of_fsl_dma_driver); + of_unregister_platform_driver(&fsldma_of_driver); } -subsys_initcall(of_fsl_dma_init); -module_exit(of_fsl_dma_exit); +subsys_initcall(fsldma_init); +module_exit(fsldma_exit); MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index dbb5b5cce4c2..f8c2baa6f41e 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -94,7 +94,7 @@ struct fsl_desc_sw { struct dma_async_tx_descriptor async_tx; } __attribute__((aligned(32))); -struct fsl_dma_chan_regs { +struct fsldma_chan_regs { u32 mr; /* 0x00 - Mode Register */ u32 sr; /* 0x04 - Status Register */ u64 cdar; /* 0x08 - Current descriptor address register */ @@ -104,19 +104,19 @@ struct fsl_dma_chan_regs { u64 ndar; /* 0x24 - Next Descriptor Address Register */ }; -struct fsl_dma_chan; +struct fsldma_chan; #define FSL_DMA_MAX_CHANS_PER_DEVICE 4 -struct fsl_dma_device { +struct fsldma_device { void __iomem *reg_base; /* DGSR register base */ struct device *dev; struct dma_device common; - struct fsl_dma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE]; + struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE]; u32 feature; /* The same as DMA channels */ int irq; /* Channel IRQ */ }; -/* Define macros for fsl_dma_chan->feature property */ +/* Define macros for fsldma_chan->feature property */ #define FSL_DMA_LITTLE_ENDIAN 0x00000000 #define FSL_DMA_BIG_ENDIAN 0x00000001 @@ -127,8 +127,8 @@ struct fsl_dma_device { #define FSL_DMA_CHAN_PAUSE_EXT 0x00001000 #define FSL_DMA_CHAN_START_EXT 0x00002000 -struct fsl_dma_chan { - struct fsl_dma_chan_regs __iomem *reg_base; +struct fsldma_chan { + struct fsldma_chan_regs __iomem *reg_base; dma_cookie_t completed_cookie; /* The maximum cookie completed */ spinlock_t desc_lock; /* Descriptor operation lock */ struct list_head ld_queue; /* Link descriptors queue */ @@ -140,14 +140,14 @@ struct fsl_dma_chan { struct tasklet_struct tasklet; u32 feature; - void (*toggle_ext_pause)(struct fsl_dma_chan *fsl_chan, int enable); - void (*toggle_ext_start)(struct fsl_dma_chan *fsl_chan, int enable); - void (*set_src_loop_size)(struct fsl_dma_chan *fsl_chan, int size); - void (*set_dest_loop_size)(struct fsl_dma_chan *fsl_chan, int size); - void (*set_request_count)(struct fsl_dma_chan *fsl_chan, int size); + void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable); + void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable); + void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size); + void (*set_dest_loop_size)(struct fsldma_chan *fsl_chan, int size); + void (*set_request_count)(struct fsldma_chan *fsl_chan, int size); }; -#define to_fsl_chan(chan) container_of(chan, struct fsl_dma_chan, common) +#define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common) #define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node) #define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx) -- cgit v1.2.3 From 738f5f7e1ae876448cb7d9c82bea258b69386647 Mon Sep 17 00:00:00 2001 From: Ira Snyder Date: Wed, 6 Jan 2010 13:34:02 +0000 Subject: fsldma: rename dest to dst for uniformity Most functions in the standard library use "dst" as a parameter, rather than "dest". This renames all use of "dest" to "dst" to match the usual convention. Signed-off-by: Ira W. Snyder Signed-off-by: Dan Williams --- drivers/dma/fsldma.c | 32 ++++++++++++++++---------------- drivers/dma/fsldma.h | 2 +- 2 files changed, 17 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 6795d96e3629..c2db7541c22b 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -90,14 +90,14 @@ static void set_desc_src(struct fsldma_chan *fsl_chan, hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64); } -static void set_desc_dest(struct fsldma_chan *fsl_chan, - struct fsl_dma_ld_hw *hw, dma_addr_t dest) +static void set_desc_dst(struct fsldma_chan *fsl_chan, + struct fsl_dma_ld_hw *hw, dma_addr_t dst) { u64 snoop_bits; snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; - hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64); + hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dst, 64); } static void set_desc_next(struct fsldma_chan *fsl_chan, @@ -253,7 +253,7 @@ static void fsl_chan_set_src_loop_size(struct fsldma_chan *fsl_chan, int size) } /** - * fsl_chan_set_dest_loop_size - Set destination address hold transfer size + * fsl_chan_set_dst_loop_size - Set destination address hold transfer size * @fsl_chan : Freescale DMA channel * @size : Address loop size, 0 for disable loop * @@ -263,7 +263,7 @@ static void fsl_chan_set_src_loop_size(struct fsldma_chan *fsl_chan, int size) * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, * TA + 1 ... and so on. */ -static void fsl_chan_set_dest_loop_size(struct fsldma_chan *fsl_chan, int size) +static void fsl_chan_set_dst_loop_size(struct fsldma_chan *fsl_chan, int size) { u32 mode; @@ -486,7 +486,7 @@ fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags) } static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( - struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, + struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src, size_t len, unsigned long flags) { struct fsldma_chan *fsl_chan; @@ -519,7 +519,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( set_desc_cnt(fsl_chan, &new->hw, copy); set_desc_src(fsl_chan, &new->hw, dma_src); - set_desc_dest(fsl_chan, &new->hw, dma_dest); + set_desc_dst(fsl_chan, &new->hw, dma_dst); if (!first) first = new; @@ -532,7 +532,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( prev = new; len -= copy; dma_src += copy; - dma_dest += copy; + dma_dst += copy; /* Insert the link descriptor to the LD ring */ list_add_tail(&new->node, &first->tx_list); @@ -680,7 +680,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( /* Fill in the descriptor */ set_desc_cnt(fsl_chan, &new->hw, copy); set_desc_src(fsl_chan, &new->hw, dma_src); - set_desc_dest(fsl_chan, &new->hw, dma_dst); + set_desc_dst(fsl_chan, &new->hw, dma_dst); /* * If this is not the first descriptor, chain the @@ -721,8 +721,8 @@ finished: if (fsl_chan->set_src_loop_size) fsl_chan->set_src_loop_size(fsl_chan, slave->src_loop_size); - if (fsl_chan->set_dest_loop_size) - fsl_chan->set_dest_loop_size(fsl_chan, slave->dst_loop_size); + if (fsl_chan->set_dst_loop_size) + fsl_chan->set_dst_loop_size(fsl_chan, slave->dst_loop_size); if (fsl_chan->toggle_ext_start) fsl_chan->toggle_ext_start(fsl_chan, slave->external_start); @@ -867,7 +867,7 @@ static void fsl_chan_ld_cleanup(struct fsldma_chan *fsl_chan) static void fsl_chan_xfer_ld_queue(struct fsldma_chan *fsl_chan) { struct list_head *ld_node; - dma_addr_t next_dest_addr; + dma_addr_t next_dst_addr; unsigned long flags; spin_lock_irqsave(&fsl_chan->desc_lock, flags); @@ -892,10 +892,10 @@ static void fsl_chan_xfer_ld_queue(struct fsldma_chan *fsl_chan) if (ld_node != &fsl_chan->ld_queue) { /* Get the ld start address from ld_queue */ - next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys; + next_dst_addr = to_fsl_desc(ld_node)->async_tx.phys; dev_dbg(fsl_chan->dev, "xfer LDs staring from 0x%llx\n", - (unsigned long long)next_dest_addr); - set_cdar(fsl_chan, next_dest_addr); + (unsigned long long)next_dst_addr); + set_cdar(fsl_chan, next_dst_addr); dma_start(fsl_chan); } else { set_cdar(fsl_chan, 0); @@ -1130,7 +1130,7 @@ static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, case FSL_DMA_IP_83XX: new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start; new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size; - new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size; + new_fsl_chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; new_fsl_chan->set_request_count = fsl_chan_set_request_count; } diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index f8c2baa6f41e..a67b8e3df0fa 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -143,7 +143,7 @@ struct fsldma_chan { void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable); void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable); void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size); - void (*set_dest_loop_size)(struct fsldma_chan *fsl_chan, int size); + void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size); void (*set_request_count)(struct fsldma_chan *fsl_chan, int size); }; -- cgit v1.2.3 From e7a29151de1bd52081f27f149b68074fac0323be Mon Sep 17 00:00:00 2001 From: Ira Snyder Date: Wed, 6 Jan 2010 13:34:03 +0000 Subject: fsldma: clean up the OF subsystem routines This fixes some errors in the cleanup paths of the OF subsystem, including missing checks for ioremap failing. Also, some variables were renamed for brevity. Signed-off-by: Ira W. Snyder Signed-off-by: Dan Williams --- drivers/dma/fsldma.c | 259 ++++++++++++++++++++++++++------------------------- drivers/dma/fsldma.h | 4 +- 2 files changed, 134 insertions(+), 129 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index c2db7541c22b..507b29716bbd 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -40,7 +40,7 @@ static void dma_init(struct fsldma_chan *fsl_chan) { /* Reset the channel */ - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32); + DMA_OUT(fsl_chan, &fsl_chan->regs->mr, 0, 32); switch (fsl_chan->feature & FSL_DMA_IP_MASK) { case FSL_DMA_IP_85XX: @@ -49,7 +49,7 @@ static void dma_init(struct fsldma_chan *fsl_chan) * EOSIE - End of segments interrupt enable (basic mode) * EOLNIE - End of links interrupt enable */ - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE + DMA_OUT(fsl_chan, &fsl_chan->regs->mr, FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); break; case FSL_DMA_IP_83XX: @@ -57,7 +57,7 @@ static void dma_init(struct fsldma_chan *fsl_chan) * EOTIE - End-of-transfer interrupt enable * PRC_RM - PCI read multiple */ - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE + DMA_OUT(fsl_chan, &fsl_chan->regs->mr, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM, 32); break; } @@ -66,12 +66,12 @@ static void dma_init(struct fsldma_chan *fsl_chan) static void set_sr(struct fsldma_chan *fsl_chan, u32 val) { - DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32); + DMA_OUT(fsl_chan, &fsl_chan->regs->sr, val, 32); } static u32 get_sr(struct fsldma_chan *fsl_chan) { - return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32); + return DMA_IN(fsl_chan, &fsl_chan->regs->sr, 32); } static void set_desc_cnt(struct fsldma_chan *fsl_chan, @@ -112,27 +112,27 @@ static void set_desc_next(struct fsldma_chan *fsl_chan, static void set_cdar(struct fsldma_chan *fsl_chan, dma_addr_t addr) { - DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64); + DMA_OUT(fsl_chan, &fsl_chan->regs->cdar, addr | FSL_DMA_SNEN, 64); } static dma_addr_t get_cdar(struct fsldma_chan *fsl_chan) { - return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN; + return DMA_IN(fsl_chan, &fsl_chan->regs->cdar, 64) & ~FSL_DMA_SNEN; } static void set_ndar(struct fsldma_chan *fsl_chan, dma_addr_t addr) { - DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64); + DMA_OUT(fsl_chan, &fsl_chan->regs->ndar, addr, 64); } static dma_addr_t get_ndar(struct fsldma_chan *fsl_chan) { - return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64); + return DMA_IN(fsl_chan, &fsl_chan->regs->ndar, 64); } static u32 get_bcr(struct fsldma_chan *fsl_chan) { - return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32); + return DMA_IN(fsl_chan, &fsl_chan->regs->bcr, 32); } static int dma_is_idle(struct fsldma_chan *fsl_chan) @@ -145,11 +145,11 @@ static void dma_start(struct fsldma_chan *fsl_chan) { u32 mode; - mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); + mode = DMA_IN(fsl_chan, &fsl_chan->regs->mr, 32); if ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { - DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32); + DMA_OUT(fsl_chan, &fsl_chan->regs->bcr, 0, 32); mode |= FSL_DMA_MR_EMP_EN; } else { mode &= ~FSL_DMA_MR_EMP_EN; @@ -161,7 +161,7 @@ static void dma_start(struct fsldma_chan *fsl_chan) else mode |= FSL_DMA_MR_CS; - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); + DMA_OUT(fsl_chan, &fsl_chan->regs->mr, mode, 32); } static void dma_halt(struct fsldma_chan *fsl_chan) @@ -169,12 +169,12 @@ static void dma_halt(struct fsldma_chan *fsl_chan) u32 mode; int i; - mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); + mode = DMA_IN(fsl_chan, &fsl_chan->regs->mr, 32); mode |= FSL_DMA_MR_CA; - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); + DMA_OUT(fsl_chan, &fsl_chan->regs->mr, mode, 32); mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA); - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); + DMA_OUT(fsl_chan, &fsl_chan->regs->mr, mode, 32); for (i = 0; i < 100; i++) { if (dma_is_idle(fsl_chan)) @@ -235,7 +235,7 @@ static void fsl_chan_set_src_loop_size(struct fsldma_chan *fsl_chan, int size) { u32 mode; - mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); + mode = DMA_IN(fsl_chan, &fsl_chan->regs->mr, 32); switch (size) { case 0: @@ -249,7 +249,7 @@ static void fsl_chan_set_src_loop_size(struct fsldma_chan *fsl_chan, int size) break; } - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); + DMA_OUT(fsl_chan, &fsl_chan->regs->mr, mode, 32); } /** @@ -267,7 +267,7 @@ static void fsl_chan_set_dst_loop_size(struct fsldma_chan *fsl_chan, int size) { u32 mode; - mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); + mode = DMA_IN(fsl_chan, &fsl_chan->regs->mr, 32); switch (size) { case 0: @@ -281,7 +281,7 @@ static void fsl_chan_set_dst_loop_size(struct fsldma_chan *fsl_chan, int size) break; } - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); + DMA_OUT(fsl_chan, &fsl_chan->regs->mr, mode, 32); } /** @@ -302,10 +302,10 @@ static void fsl_chan_set_request_count(struct fsldma_chan *fsl_chan, int size) BUG_ON(size > 1024); - mode = DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32); + mode = DMA_IN(fsl_chan, &fsl_chan->regs->mr, 32); mode |= (__ilog2(size) << 24) & 0x0f000000; - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, mode, 32); + DMA_OUT(fsl_chan, &fsl_chan->regs->mr, mode, 32); } /** @@ -967,7 +967,7 @@ static enum dma_status fsl_dma_is_complete(struct dma_chan *chan, return dma_async_is_complete(cookie, last_complete, last_used); } -static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data) +static irqreturn_t fsldma_chan_irq(int irq, void *data) { struct fsldma_chan *fsl_chan = data; u32 stat; @@ -1048,17 +1048,17 @@ static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data) return IRQ_HANDLED; } -static irqreturn_t fsl_dma_do_interrupt(int irq, void *data) +static irqreturn_t fsldma_irq(int irq, void *data) { struct fsldma_device *fdev = data; int ch_nr; u32 gsr; - gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base) - : in_le32(fdev->reg_base); + gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) + : in_le32(fdev->regs); ch_nr = (32 - ffs(gsr)) / 8; - return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq, + return fdev->chan[ch_nr] ? fsldma_chan_irq(irq, fdev->chan[ch_nr]) : IRQ_NONE; } @@ -1075,140 +1075,142 @@ static void dma_do_tasklet(unsigned long data) static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, struct device_node *node, u32 feature, const char *compatible) { - struct fsldma_chan *new_fsl_chan; + struct fsldma_chan *fchan; struct resource res; int err; /* alloc channel */ - new_fsl_chan = kzalloc(sizeof(*new_fsl_chan), GFP_KERNEL); - if (!new_fsl_chan) { - dev_err(fdev->dev, "No free memory for allocating " - "dma channels!\n"); - return -ENOMEM; + fchan = kzalloc(sizeof(*fchan), GFP_KERNEL); + if (!fchan) { + dev_err(fdev->dev, "no free memory for DMA channels!\n"); + err = -ENOMEM; + goto out_return; + } + + /* ioremap registers for use */ + fchan->regs = of_iomap(node, 0); + if (!fchan->regs) { + dev_err(fdev->dev, "unable to ioremap registers\n"); + err = -ENOMEM; + goto out_free_fchan; } - /* get dma channel register base */ err = of_address_to_resource(node, 0, &res); if (err) { - dev_err(fdev->dev, "Can't get %s property 'reg'\n", - node->full_name); - goto err_no_reg; + dev_err(fdev->dev, "unable to find 'reg' property\n"); + goto out_iounmap_regs; } - new_fsl_chan->feature = feature; - + fchan->feature = feature; if (!fdev->feature) - fdev->feature = new_fsl_chan->feature; + fdev->feature = fchan->feature; - /* If the DMA device's feature is different than its channels', - * report the bug. + /* + * If the DMA device's feature is different than the feature + * of its channels, report the bug */ - WARN_ON(fdev->feature != new_fsl_chan->feature); - - new_fsl_chan->dev = fdev->dev; - new_fsl_chan->reg_base = ioremap(res.start, resource_size(&res)); - new_fsl_chan->id = ((res.start - 0x100) & 0xfff) >> 7; - if (new_fsl_chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { - dev_err(fdev->dev, "There is no %d channel!\n", - new_fsl_chan->id); + WARN_ON(fdev->feature != fchan->feature); + + fchan->dev = fdev->dev; + fchan->id = ((res.start - 0x100) & 0xfff) >> 7; + if (fchan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { + dev_err(fdev->dev, "too many channels for device\n"); err = -EINVAL; - goto err_no_chan; + goto out_iounmap_regs; } - fdev->chan[new_fsl_chan->id] = new_fsl_chan; - tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet, - (unsigned long)new_fsl_chan); - /* Init the channel */ - dma_init(new_fsl_chan); + fdev->chan[fchan->id] = fchan; + tasklet_init(&fchan->tasklet, dma_do_tasklet, (unsigned long)fchan); + + /* Initialize the channel */ + dma_init(fchan); /* Clear cdar registers */ - set_cdar(new_fsl_chan, 0); + set_cdar(fchan, 0); - switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) { + switch (fchan->feature & FSL_DMA_IP_MASK) { case FSL_DMA_IP_85XX: - new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; + fchan->toggle_ext_pause = fsl_chan_toggle_ext_pause; case FSL_DMA_IP_83XX: - new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start; - new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size; - new_fsl_chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; - new_fsl_chan->set_request_count = fsl_chan_set_request_count; + fchan->toggle_ext_start = fsl_chan_toggle_ext_start; + fchan->set_src_loop_size = fsl_chan_set_src_loop_size; + fchan->set_dst_loop_size = fsl_chan_set_dst_loop_size; + fchan->set_request_count = fsl_chan_set_request_count; } - spin_lock_init(&new_fsl_chan->desc_lock); - INIT_LIST_HEAD(&new_fsl_chan->ld_queue); + spin_lock_init(&fchan->desc_lock); + INIT_LIST_HEAD(&fchan->ld_queue); - new_fsl_chan->common.device = &fdev->common; + fchan->common.device = &fdev->common; /* Add the channel to DMA device channel list */ - list_add_tail(&new_fsl_chan->common.device_node, - &fdev->common.channels); + list_add_tail(&fchan->common.device_node, &fdev->common.channels); fdev->common.chancnt++; - new_fsl_chan->irq = irq_of_parse_and_map(node, 0); - if (new_fsl_chan->irq != NO_IRQ) { - err = request_irq(new_fsl_chan->irq, - &fsl_dma_chan_do_interrupt, IRQF_SHARED, - "fsldma-channel", new_fsl_chan); + fchan->irq = irq_of_parse_and_map(node, 0); + if (fchan->irq != NO_IRQ) { + err = request_irq(fchan->irq, &fsldma_chan_irq, + IRQF_SHARED, "fsldma-channel", fchan); if (err) { - dev_err(fdev->dev, "DMA channel %s request_irq error " - "with return %d\n", node->full_name, err); - goto err_no_irq; + dev_err(fdev->dev, "unable to request IRQ " + "for channel %d\n", fchan->id); + goto out_list_del; } } - dev_info(fdev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id, - compatible, - new_fsl_chan->irq != NO_IRQ ? new_fsl_chan->irq : fdev->irq); + dev_info(fdev->dev, "#%d (%s), irq %d\n", fchan->id, compatible, + fchan->irq != NO_IRQ ? fchan->irq : fdev->irq); return 0; -err_no_irq: - list_del(&new_fsl_chan->common.device_node); -err_no_chan: - iounmap(new_fsl_chan->reg_base); -err_no_reg: - kfree(new_fsl_chan); +out_list_del: + irq_dispose_mapping(fchan->irq); + list_del_init(&fchan->common.device_node); +out_iounmap_regs: + iounmap(fchan->regs); +out_free_fchan: + kfree(fchan); +out_return: return err; } static void fsl_dma_chan_remove(struct fsldma_chan *fchan) { - if (fchan->irq != NO_IRQ) + if (fchan->irq != NO_IRQ) { free_irq(fchan->irq, fchan); + irq_dispose_mapping(fchan->irq); + } + list_del(&fchan->common.device_node); - iounmap(fchan->reg_base); + iounmap(fchan->regs); kfree(fchan); } -static int __devinit fsldma_of_probe(struct of_device *dev, +static int __devinit fsldma_of_probe(struct of_device *op, const struct of_device_id *match) { - int err; struct fsldma_device *fdev; struct device_node *child; - struct resource res; + int err; fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); if (!fdev) { - dev_err(&dev->dev, "No enough memory for 'priv'\n"); - return -ENOMEM; + dev_err(&op->dev, "No enough memory for 'priv'\n"); + err = -ENOMEM; + goto out_return; } - fdev->dev = &dev->dev; + + fdev->dev = &op->dev; INIT_LIST_HEAD(&fdev->common.channels); - /* get DMA controller register base */ - err = of_address_to_resource(dev->node, 0, &res); - if (err) { - dev_err(&dev->dev, "Can't get %s property 'reg'\n", - dev->node->full_name); - goto err_no_reg; + /* ioremap the registers for use */ + fdev->regs = of_iomap(op->node, 0); + if (!fdev->regs) { + dev_err(&op->dev, "unable to ioremap registers\n"); + err = -ENOMEM; + goto out_free_fdev; } - dev_info(&dev->dev, "Probe the Freescale DMA driver for %s " - "controller at 0x%llx...\n", - match->compatible, (unsigned long long)res.start); - fdev->reg_base = ioremap(res.start, resource_size(&res)); - dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); @@ -1220,66 +1222,69 @@ static int __devinit fsldma_of_probe(struct of_device *dev, fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; fdev->common.device_terminate_all = fsl_dma_device_terminate_all; - fdev->common.dev = &dev->dev; + fdev->common.dev = &op->dev; - fdev->irq = irq_of_parse_and_map(dev->node, 0); + fdev->irq = irq_of_parse_and_map(op->node, 0); if (fdev->irq != NO_IRQ) { - err = request_irq(fdev->irq, &fsl_dma_do_interrupt, IRQF_SHARED, - "fsldma-device", fdev); + err = request_irq(fdev->irq, &fsldma_irq, IRQF_SHARED, + "fsldma-device", fdev); if (err) { - dev_err(&dev->dev, "DMA device request_irq error " - "with return %d\n", err); - goto err; + dev_err(&op->dev, "unable to request IRQ\n"); + goto out_iounmap_regs; } } - dev_set_drvdata(&(dev->dev), fdev); + dev_set_drvdata(&op->dev, fdev); - /* We cannot use of_platform_bus_probe() because there is no - * of_platform_bus_remove. Instead, we manually instantiate every DMA + /* + * We cannot use of_platform_bus_probe() because there is no + * of_platform_bus_remove(). Instead, we manually instantiate every DMA * channel object. */ - for_each_child_of_node(dev->node, child) { - if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) + for_each_child_of_node(op->node, child) { + if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { fsl_dma_chan_probe(fdev, child, FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, "fsl,eloplus-dma-channel"); - if (of_device_is_compatible(child, "fsl,elo-dma-channel")) + } + + if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { fsl_dma_chan_probe(fdev, child, FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, "fsl,elo-dma-channel"); + } } dma_async_device_register(&fdev->common); return 0; -err: - iounmap(fdev->reg_base); -err_no_reg: +out_iounmap_regs: + iounmap(fdev->regs); +out_free_fdev: kfree(fdev); +out_return: return err; } -static int fsldma_of_remove(struct of_device *of_dev) +static int fsldma_of_remove(struct of_device *op) { struct fsldma_device *fdev; unsigned int i; - fdev = dev_get_drvdata(&of_dev->dev); - + fdev = dev_get_drvdata(&op->dev); dma_async_device_unregister(&fdev->common); - for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) + for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { if (fdev->chan[i]) fsl_dma_chan_remove(fdev->chan[i]); + } if (fdev->irq != NO_IRQ) free_irq(fdev->irq, fdev); - iounmap(fdev->reg_base); - + iounmap(fdev->regs); + dev_set_drvdata(&op->dev, NULL); kfree(fdev); - dev_set_drvdata(&of_dev->dev, NULL); return 0; } diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index a67b8e3df0fa..ea3b19c8708c 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -108,7 +108,7 @@ struct fsldma_chan; #define FSL_DMA_MAX_CHANS_PER_DEVICE 4 struct fsldma_device { - void __iomem *reg_base; /* DGSR register base */ + void __iomem *regs; /* DGSR register base */ struct device *dev; struct dma_device common; struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE]; @@ -128,7 +128,7 @@ struct fsldma_device { #define FSL_DMA_CHAN_START_EXT 0x00002000 struct fsldma_chan { - struct fsldma_chan_regs __iomem *reg_base; + struct fsldma_chan_regs __iomem *regs; dma_cookie_t completed_cookie; /* The maximum cookie completed */ spinlock_t desc_lock; /* Descriptor operation lock */ struct list_head ld_queue; /* Link descriptors queue */ -- cgit v1.2.3 From d3f620b2c4fecdc8e060b70e8d92d29fc01c6126 Mon Sep 17 00:00:00 2001 From: Ira Snyder Date: Wed, 6 Jan 2010 13:34:04 +0000 Subject: fsldma: simplify IRQ probing and handling The IRQ probing is needlessly complex. All off the 83xx device trees in arch/powerpc/boot/dts/ specify 5 interrupts per DMA controller: one for the controller, and one for each channel. These interrupts are all attached to the same IRQ line. This causes an interesting situation if two channels interrupt at the same time. The per-controller handler will handle the first channel, and the per-channel handler will handle the remaining channels. Instead of this mess, we fix the bug in the per-controller handler, and make it handle all channels that generated an interrupt. When a per-controller handler is specified in the device tree, we prefer to use the shared handler instead of the per-channel handler. The 85xx/86xx controllers do not have a per-controller interrupt, and instead use a per-channel interrupt. This behavior has not been changed. Signed-off-by: Ira W. Snyder Signed-off-by: Dan Williams --- Documentation/powerpc/dts-bindings/fsl/dma.txt | 8 ++ drivers/dma/fsldma.c | 173 ++++++++++++++++++------- 2 files changed, 137 insertions(+), 44 deletions(-) (limited to 'drivers') diff --git a/Documentation/powerpc/dts-bindings/fsl/dma.txt b/Documentation/powerpc/dts-bindings/fsl/dma.txt index 0732cdd05ba1..2a4b4bce6110 100644 --- a/Documentation/powerpc/dts-bindings/fsl/dma.txt +++ b/Documentation/powerpc/dts-bindings/fsl/dma.txt @@ -44,21 +44,29 @@ Example: compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; cell-index = <0>; reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; }; dma-channel@80 { compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; cell-index = <1>; reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; }; dma-channel@100 { compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; cell-index = <2>; reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; }; dma-channel@180 { compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; cell-index = <3>; reg = <0x180 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; }; }; diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 507b29716bbd..6a905929ef01 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -967,6 +967,10 @@ static enum dma_status fsl_dma_is_complete(struct dma_chan *chan, return dma_async_is_complete(cookie, last_complete, last_used); } +/*----------------------------------------------------------------------------*/ +/* Interrupt Handling */ +/*----------------------------------------------------------------------------*/ + static irqreturn_t fsldma_chan_irq(int irq, void *data) { struct fsldma_chan *fsl_chan = data; @@ -1048,24 +1052,116 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data) return IRQ_HANDLED; } -static irqreturn_t fsldma_irq(int irq, void *data) +static void dma_do_tasklet(unsigned long data) +{ + struct fsldma_chan *fsl_chan = (struct fsldma_chan *)data; + fsl_chan_ld_cleanup(fsl_chan); +} + +static irqreturn_t fsldma_ctrl_irq(int irq, void *data) { struct fsldma_device *fdev = data; - int ch_nr; - u32 gsr; + struct fsldma_chan *chan; + unsigned int handled = 0; + u32 gsr, mask; + int i; gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) - : in_le32(fdev->regs); - ch_nr = (32 - ffs(gsr)) / 8; + : in_le32(fdev->regs); + mask = 0xff000000; + dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); - return fdev->chan[ch_nr] ? fsldma_chan_irq(irq, - fdev->chan[ch_nr]) : IRQ_NONE; + for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { + chan = fdev->chan[i]; + if (!chan) + continue; + + if (gsr & mask) { + dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); + fsldma_chan_irq(irq, chan); + handled++; + } + + gsr &= ~mask; + mask >>= 8; + } + + return IRQ_RETVAL(handled); } -static void dma_do_tasklet(unsigned long data) +static void fsldma_free_irqs(struct fsldma_device *fdev) { - struct fsldma_chan *fsl_chan = (struct fsldma_chan *)data; - fsl_chan_ld_cleanup(fsl_chan); + struct fsldma_chan *chan; + int i; + + if (fdev->irq != NO_IRQ) { + dev_dbg(fdev->dev, "free per-controller IRQ\n"); + free_irq(fdev->irq, fdev); + return; + } + + for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { + chan = fdev->chan[i]; + if (chan && chan->irq != NO_IRQ) { + dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id); + free_irq(chan->irq, chan); + } + } +} + +static int fsldma_request_irqs(struct fsldma_device *fdev) +{ + struct fsldma_chan *chan; + int ret; + int i; + + /* if we have a per-controller IRQ, use that */ + if (fdev->irq != NO_IRQ) { + dev_dbg(fdev->dev, "request per-controller IRQ\n"); + ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, + "fsldma-controller", fdev); + return ret; + } + + /* no per-controller IRQ, use the per-channel IRQs */ + for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { + chan = fdev->chan[i]; + if (!chan) + continue; + + if (chan->irq == NO_IRQ) { + dev_err(fdev->dev, "no interrupts property defined for " + "DMA channel %d. Please fix your " + "device tree\n", chan->id); + ret = -ENODEV; + goto out_unwind; + } + + dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id); + ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, + "fsldma-chan", chan); + if (ret) { + dev_err(fdev->dev, "unable to request IRQ for DMA " + "channel %d\n", chan->id); + goto out_unwind; + } + } + + return 0; + +out_unwind: + for (/* none */; i >= 0; i--) { + chan = fdev->chan[i]; + if (!chan) + continue; + + if (chan->irq == NO_IRQ) + continue; + + free_irq(chan->irq, chan); + } + + return ret; } /*----------------------------------------------------------------------------*/ @@ -1143,29 +1239,18 @@ static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, fchan->common.device = &fdev->common; + /* find the IRQ line, if it exists in the device tree */ + fchan->irq = irq_of_parse_and_map(node, 0); + /* Add the channel to DMA device channel list */ list_add_tail(&fchan->common.device_node, &fdev->common.channels); fdev->common.chancnt++; - fchan->irq = irq_of_parse_and_map(node, 0); - if (fchan->irq != NO_IRQ) { - err = request_irq(fchan->irq, &fsldma_chan_irq, - IRQF_SHARED, "fsldma-channel", fchan); - if (err) { - dev_err(fdev->dev, "unable to request IRQ " - "for channel %d\n", fchan->id); - goto out_list_del; - } - } - dev_info(fdev->dev, "#%d (%s), irq %d\n", fchan->id, compatible, fchan->irq != NO_IRQ ? fchan->irq : fdev->irq); return 0; -out_list_del: - irq_dispose_mapping(fchan->irq); - list_del_init(&fchan->common.device_node); out_iounmap_regs: iounmap(fchan->regs); out_free_fchan: @@ -1176,11 +1261,7 @@ out_return: static void fsl_dma_chan_remove(struct fsldma_chan *fchan) { - if (fchan->irq != NO_IRQ) { - free_irq(fchan->irq, fchan); - irq_dispose_mapping(fchan->irq); - } - + irq_dispose_mapping(fchan->irq); list_del(&fchan->common.device_node); iounmap(fchan->regs); kfree(fchan); @@ -1211,6 +1292,9 @@ static int __devinit fsldma_of_probe(struct of_device *op, goto out_free_fdev; } + /* map the channel IRQ if it exists, but don't hookup the handler yet */ + fdev->irq = irq_of_parse_and_map(op->node, 0); + dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); @@ -1224,16 +1308,6 @@ static int __devinit fsldma_of_probe(struct of_device *op, fdev->common.device_terminate_all = fsl_dma_device_terminate_all; fdev->common.dev = &op->dev; - fdev->irq = irq_of_parse_and_map(op->node, 0); - if (fdev->irq != NO_IRQ) { - err = request_irq(fdev->irq, &fsldma_irq, IRQF_SHARED, - "fsldma-device", fdev); - if (err) { - dev_err(&op->dev, "unable to request IRQ\n"); - goto out_iounmap_regs; - } - } - dev_set_drvdata(&op->dev, fdev); /* @@ -1255,12 +1329,24 @@ static int __devinit fsldma_of_probe(struct of_device *op, } } + /* + * Hookup the IRQ handler(s) + * + * If we have a per-controller interrupt, we prefer that to the + * per-channel interrupts to reduce the number of shared interrupt + * handlers on the same IRQ line + */ + err = fsldma_request_irqs(fdev); + if (err) { + dev_err(fdev->dev, "unable to request IRQs\n"); + goto out_free_fdev; + } + dma_async_device_register(&fdev->common); return 0; -out_iounmap_regs: - iounmap(fdev->regs); out_free_fdev: + irq_dispose_mapping(fdev->irq); kfree(fdev); out_return: return err; @@ -1274,14 +1360,13 @@ static int fsldma_of_remove(struct of_device *op) fdev = dev_get_drvdata(&op->dev); dma_async_device_unregister(&fdev->common); + fsldma_free_irqs(fdev); + for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { if (fdev->chan[i]) fsl_dma_chan_remove(fdev->chan[i]); } - if (fdev->irq != NO_IRQ) - free_irq(fdev->irq, fdev); - iounmap(fdev->regs); dev_set_drvdata(&op->dev, NULL); kfree(fdev); -- cgit v1.2.3 From a1c03319018061304be28d131073ac13a5cb86fb Mon Sep 17 00:00:00 2001 From: Ira Snyder Date: Wed, 6 Jan 2010 13:34:05 +0000 Subject: fsldma: rename fsl_chan to chan The name fsl_chan seems too long, so it has been shortened to chan. There are only a few places where the higher level "struct dma_chan *chan" name conflicts. These have been changed to "struct dma_chan *dchan" instead. Signed-off-by: Ira W. Snyder Signed-off-by: Dan Williams --- drivers/dma/fsldma.c | 550 +++++++++++++++++++++++++-------------------------- 1 file changed, 275 insertions(+), 275 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 6a905929ef01..7b5f88cb495b 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -37,19 +37,19 @@ #include #include "fsldma.h" -static void dma_init(struct fsldma_chan *fsl_chan) +static void dma_init(struct fsldma_chan *chan) { /* Reset the channel */ - DMA_OUT(fsl_chan, &fsl_chan->regs->mr, 0, 32); + DMA_OUT(chan, &chan->regs->mr, 0, 32); - switch (fsl_chan->feature & FSL_DMA_IP_MASK) { + switch (chan->feature & FSL_DMA_IP_MASK) { case FSL_DMA_IP_85XX: /* Set the channel to below modes: * EIE - Error interrupt enable * EOSIE - End of segments interrupt enable (basic mode) * EOLNIE - End of links interrupt enable */ - DMA_OUT(fsl_chan, &fsl_chan->regs->mr, FSL_DMA_MR_EIE + DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); break; case FSL_DMA_IP_83XX: @@ -57,154 +57,154 @@ static void dma_init(struct fsldma_chan *fsl_chan) * EOTIE - End-of-transfer interrupt enable * PRC_RM - PCI read multiple */ - DMA_OUT(fsl_chan, &fsl_chan->regs->mr, FSL_DMA_MR_EOTIE + DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM, 32); break; } } -static void set_sr(struct fsldma_chan *fsl_chan, u32 val) +static void set_sr(struct fsldma_chan *chan, u32 val) { - DMA_OUT(fsl_chan, &fsl_chan->regs->sr, val, 32); + DMA_OUT(chan, &chan->regs->sr, val, 32); } -static u32 get_sr(struct fsldma_chan *fsl_chan) +static u32 get_sr(struct fsldma_chan *chan) { - return DMA_IN(fsl_chan, &fsl_chan->regs->sr, 32); + return DMA_IN(chan, &chan->regs->sr, 32); } -static void set_desc_cnt(struct fsldma_chan *fsl_chan, +static void set_desc_cnt(struct fsldma_chan *chan, struct fsl_dma_ld_hw *hw, u32 count) { - hw->count = CPU_TO_DMA(fsl_chan, count, 32); + hw->count = CPU_TO_DMA(chan, count, 32); } -static void set_desc_src(struct fsldma_chan *fsl_chan, +static void set_desc_src(struct fsldma_chan *chan, struct fsl_dma_ld_hw *hw, dma_addr_t src) { u64 snoop_bits; - snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) + snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; - hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64); + hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); } -static void set_desc_dst(struct fsldma_chan *fsl_chan, +static void set_desc_dst(struct fsldma_chan *chan, struct fsl_dma_ld_hw *hw, dma_addr_t dst) { u64 snoop_bits; - snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) + snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; - hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dst, 64); + hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); } -static void set_desc_next(struct fsldma_chan *fsl_chan, +static void set_desc_next(struct fsldma_chan *chan, struct fsl_dma_ld_hw *hw, dma_addr_t next) { u64 snoop_bits; - snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) + snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0; - hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64); + hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); } -static void set_cdar(struct fsldma_chan *fsl_chan, dma_addr_t addr) +static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) { - DMA_OUT(fsl_chan, &fsl_chan->regs->cdar, addr | FSL_DMA_SNEN, 64); + DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); } -static dma_addr_t get_cdar(struct fsldma_chan *fsl_chan) +static dma_addr_t get_cdar(struct fsldma_chan *chan) { - return DMA_IN(fsl_chan, &fsl_chan->regs->cdar, 64) & ~FSL_DMA_SNEN; + return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; } -static void set_ndar(struct fsldma_chan *fsl_chan, dma_addr_t addr) +static void set_ndar(struct fsldma_chan *chan, dma_addr_t addr) { - DMA_OUT(fsl_chan, &fsl_chan->regs->ndar, addr, 64); + DMA_OUT(chan, &chan->regs->ndar, addr, 64); } -static dma_addr_t get_ndar(struct fsldma_chan *fsl_chan) +static dma_addr_t get_ndar(struct fsldma_chan *chan) { - return DMA_IN(fsl_chan, &fsl_chan->regs->ndar, 64); + return DMA_IN(chan, &chan->regs->ndar, 64); } -static u32 get_bcr(struct fsldma_chan *fsl_chan) +static u32 get_bcr(struct fsldma_chan *chan) { - return DMA_IN(fsl_chan, &fsl_chan->regs->bcr, 32); + return DMA_IN(chan, &chan->regs->bcr, 32); } -static int dma_is_idle(struct fsldma_chan *fsl_chan) +static int dma_is_idle(struct fsldma_chan *chan) { - u32 sr = get_sr(fsl_chan); + u32 sr = get_sr(chan); return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); } -static void dma_start(struct fsldma_chan *fsl_chan) +static void dma_start(struct fsldma_chan *chan) { u32 mode; - mode = DMA_IN(fsl_chan, &fsl_chan->regs->mr, 32); + mode = DMA_IN(chan, &chan->regs->mr, 32); - if ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { - if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { - DMA_OUT(fsl_chan, &fsl_chan->regs->bcr, 0, 32); + if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { + if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { + DMA_OUT(chan, &chan->regs->bcr, 0, 32); mode |= FSL_DMA_MR_EMP_EN; } else { mode &= ~FSL_DMA_MR_EMP_EN; } } - if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT) + if (chan->feature & FSL_DMA_CHAN_START_EXT) mode |= FSL_DMA_MR_EMS_EN; else mode |= FSL_DMA_MR_CS; - DMA_OUT(fsl_chan, &fsl_chan->regs->mr, mode, 32); + DMA_OUT(chan, &chan->regs->mr, mode, 32); } -static void dma_halt(struct fsldma_chan *fsl_chan) +static void dma_halt(struct fsldma_chan *chan) { u32 mode; int i; - mode = DMA_IN(fsl_chan, &fsl_chan->regs->mr, 32); + mode = DMA_IN(chan, &chan->regs->mr, 32); mode |= FSL_DMA_MR_CA; - DMA_OUT(fsl_chan, &fsl_chan->regs->mr, mode, 32); + DMA_OUT(chan, &chan->regs->mr, mode, 32); mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA); - DMA_OUT(fsl_chan, &fsl_chan->regs->mr, mode, 32); + DMA_OUT(chan, &chan->regs->mr, mode, 32); for (i = 0; i < 100; i++) { - if (dma_is_idle(fsl_chan)) + if (dma_is_idle(chan)) break; udelay(10); } - if (i >= 100 && !dma_is_idle(fsl_chan)) - dev_err(fsl_chan->dev, "DMA halt timeout!\n"); + if (i >= 100 && !dma_is_idle(chan)) + dev_err(chan->dev, "DMA halt timeout!\n"); } -static void set_ld_eol(struct fsldma_chan *fsl_chan, +static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc) { u64 snoop_bits; - snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) + snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0; - desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, - DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL + desc->hw.next_ln_addr = CPU_TO_DMA(chan, + DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL | snoop_bits, 64); } -static void append_ld_queue(struct fsldma_chan *fsl_chan, +static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *new_desc) { - struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev); + struct fsl_desc_sw *queue_tail = to_fsl_desc(chan->ld_queue.prev); - if (list_empty(&fsl_chan->ld_queue)) + if (list_empty(&chan->ld_queue)) return; /* Link to the new descriptor physical address and @@ -214,15 +214,15 @@ static void append_ld_queue(struct fsldma_chan *fsl_chan, * * For FSL_DMA_IP_83xx, the snoop enable bit need be set. */ - queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, + queue_tail->hw.next_ln_addr = CPU_TO_DMA(chan, new_desc->async_tx.phys | FSL_DMA_EOSIE | - (((fsl_chan->feature & FSL_DMA_IP_MASK) + (((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64); } /** * fsl_chan_set_src_loop_size - Set source address hold transfer size - * @fsl_chan : Freescale DMA channel + * @chan : Freescale DMA channel * @size : Address loop size, 0 for disable loop * * The set source address hold transfer size. The source @@ -231,11 +231,11 @@ static void append_ld_queue(struct fsldma_chan *fsl_chan, * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, * SA + 1 ... and so on. */ -static void fsl_chan_set_src_loop_size(struct fsldma_chan *fsl_chan, int size) +static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) { u32 mode; - mode = DMA_IN(fsl_chan, &fsl_chan->regs->mr, 32); + mode = DMA_IN(chan, &chan->regs->mr, 32); switch (size) { case 0: @@ -249,12 +249,12 @@ static void fsl_chan_set_src_loop_size(struct fsldma_chan *fsl_chan, int size) break; } - DMA_OUT(fsl_chan, &fsl_chan->regs->mr, mode, 32); + DMA_OUT(chan, &chan->regs->mr, mode, 32); } /** * fsl_chan_set_dst_loop_size - Set destination address hold transfer size - * @fsl_chan : Freescale DMA channel + * @chan : Freescale DMA channel * @size : Address loop size, 0 for disable loop * * The set destination address hold transfer size. The destination @@ -263,11 +263,11 @@ static void fsl_chan_set_src_loop_size(struct fsldma_chan *fsl_chan, int size) * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, * TA + 1 ... and so on. */ -static void fsl_chan_set_dst_loop_size(struct fsldma_chan *fsl_chan, int size) +static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) { u32 mode; - mode = DMA_IN(fsl_chan, &fsl_chan->regs->mr, 32); + mode = DMA_IN(chan, &chan->regs->mr, 32); switch (size) { case 0: @@ -281,12 +281,12 @@ static void fsl_chan_set_dst_loop_size(struct fsldma_chan *fsl_chan, int size) break; } - DMA_OUT(fsl_chan, &fsl_chan->regs->mr, mode, 32); + DMA_OUT(chan, &chan->regs->mr, mode, 32); } /** * fsl_chan_set_request_count - Set DMA Request Count for external control - * @fsl_chan : Freescale DMA channel + * @chan : Freescale DMA channel * @size : Number of bytes to transfer in a single request * * The Freescale DMA channel can be controlled by the external signal DREQ#. @@ -296,38 +296,38 @@ static void fsl_chan_set_dst_loop_size(struct fsldma_chan *fsl_chan, int size) * * A size of 0 disables external pause control. The maximum size is 1024. */ -static void fsl_chan_set_request_count(struct fsldma_chan *fsl_chan, int size) +static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) { u32 mode; BUG_ON(size > 1024); - mode = DMA_IN(fsl_chan, &fsl_chan->regs->mr, 32); + mode = DMA_IN(chan, &chan->regs->mr, 32); mode |= (__ilog2(size) << 24) & 0x0f000000; - DMA_OUT(fsl_chan, &fsl_chan->regs->mr, mode, 32); + DMA_OUT(chan, &chan->regs->mr, mode, 32); } /** * fsl_chan_toggle_ext_pause - Toggle channel external pause status - * @fsl_chan : Freescale DMA channel + * @chan : Freescale DMA channel * @enable : 0 is disabled, 1 is enabled. * * The Freescale DMA channel can be controlled by the external signal DREQ#. * The DMA Request Count feature should be used in addition to this feature * to set the number of bytes to transfer before pausing the channel. */ -static void fsl_chan_toggle_ext_pause(struct fsldma_chan *fsl_chan, int enable) +static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) { if (enable) - fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; + chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; else - fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; + chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; } /** * fsl_chan_toggle_ext_start - Toggle channel external start status - * @fsl_chan : Freescale DMA channel + * @chan : Freescale DMA channel * @enable : 0 is disabled, 1 is enabled. * * If enable the external start, the channel can be started by an @@ -335,26 +335,26 @@ static void fsl_chan_toggle_ext_pause(struct fsldma_chan *fsl_chan, int enable) * transfer immediately. The DMA channel will wait for the * control pin asserted. */ -static void fsl_chan_toggle_ext_start(struct fsldma_chan *fsl_chan, int enable) +static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) { if (enable) - fsl_chan->feature |= FSL_DMA_CHAN_START_EXT; + chan->feature |= FSL_DMA_CHAN_START_EXT; else - fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT; + chan->feature &= ~FSL_DMA_CHAN_START_EXT; } static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) { - struct fsldma_chan *fsl_chan = to_fsl_chan(tx->chan); + struct fsldma_chan *chan = to_fsl_chan(tx->chan); struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); struct fsl_desc_sw *child; unsigned long flags; dma_cookie_t cookie; /* cookie increment and adding to ld_queue must be atomic */ - spin_lock_irqsave(&fsl_chan->desc_lock, flags); + spin_lock_irqsave(&chan->desc_lock, flags); - cookie = fsl_chan->common.cookie; + cookie = chan->common.cookie; list_for_each_entry(child, &desc->tx_list, node) { cookie++; if (cookie < 0) @@ -363,33 +363,33 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) desc->async_tx.cookie = cookie; } - fsl_chan->common.cookie = cookie; - append_ld_queue(fsl_chan, desc); - list_splice_init(&desc->tx_list, fsl_chan->ld_queue.prev); + chan->common.cookie = cookie; + append_ld_queue(chan, desc); + list_splice_init(&desc->tx_list, chan->ld_queue.prev); - spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); + spin_unlock_irqrestore(&chan->desc_lock, flags); return cookie; } /** * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. - * @fsl_chan : Freescale DMA channel + * @chan : Freescale DMA channel * * Return - The descriptor allocated. NULL for failed. */ static struct fsl_desc_sw *fsl_dma_alloc_descriptor( - struct fsldma_chan *fsl_chan) + struct fsldma_chan *chan) { dma_addr_t pdesc; struct fsl_desc_sw *desc_sw; - desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc); + desc_sw = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); if (desc_sw) { memset(desc_sw, 0, sizeof(struct fsl_desc_sw)); INIT_LIST_HEAD(&desc_sw->tx_list); dma_async_tx_descriptor_init(&desc_sw->async_tx, - &fsl_chan->common); + &chan->common); desc_sw->async_tx.tx_submit = fsl_dma_tx_submit; desc_sw->async_tx.phys = pdesc; } @@ -400,29 +400,29 @@ static struct fsl_desc_sw *fsl_dma_alloc_descriptor( /** * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. - * @fsl_chan : Freescale DMA channel + * @chan : Freescale DMA channel * * This function will create a dma pool for descriptor allocation. * * Return - The number of descriptors allocated. */ -static int fsl_dma_alloc_chan_resources(struct dma_chan *chan) +static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) { - struct fsldma_chan *fsl_chan = to_fsl_chan(chan); + struct fsldma_chan *chan = to_fsl_chan(dchan); /* Has this channel already been allocated? */ - if (fsl_chan->desc_pool) + if (chan->desc_pool) return 1; /* We need the descriptor to be aligned to 32bytes * for meeting FSL DMA specification requirement. */ - fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", - fsl_chan->dev, sizeof(struct fsl_desc_sw), + chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", + chan->dev, sizeof(struct fsl_desc_sw), 32, 0); - if (!fsl_chan->desc_pool) { - dev_err(fsl_chan->dev, "No memory for channel %d " - "descriptor dma pool.\n", fsl_chan->id); + if (!chan->desc_pool) { + dev_err(chan->dev, "No memory for channel %d " + "descriptor dma pool.\n", chan->id); return 0; } @@ -431,45 +431,45 @@ static int fsl_dma_alloc_chan_resources(struct dma_chan *chan) /** * fsl_dma_free_chan_resources - Free all resources of the channel. - * @fsl_chan : Freescale DMA channel + * @chan : Freescale DMA channel */ -static void fsl_dma_free_chan_resources(struct dma_chan *chan) +static void fsl_dma_free_chan_resources(struct dma_chan *dchan) { - struct fsldma_chan *fsl_chan = to_fsl_chan(chan); + struct fsldma_chan *chan = to_fsl_chan(dchan); struct fsl_desc_sw *desc, *_desc; unsigned long flags; - dev_dbg(fsl_chan->dev, "Free all channel resources.\n"); - spin_lock_irqsave(&fsl_chan->desc_lock, flags); - list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { + dev_dbg(chan->dev, "Free all channel resources.\n"); + spin_lock_irqsave(&chan->desc_lock, flags); + list_for_each_entry_safe(desc, _desc, &chan->ld_queue, node) { #ifdef FSL_DMA_LD_DEBUG - dev_dbg(fsl_chan->dev, + dev_dbg(chan->dev, "LD %p will be released.\n", desc); #endif list_del(&desc->node); /* free link descriptor */ - dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); } - spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); - dma_pool_destroy(fsl_chan->desc_pool); + spin_unlock_irqrestore(&chan->desc_lock, flags); + dma_pool_destroy(chan->desc_pool); - fsl_chan->desc_pool = NULL; + chan->desc_pool = NULL; } static struct dma_async_tx_descriptor * -fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags) +fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) { - struct fsldma_chan *fsl_chan; + struct fsldma_chan *chan; struct fsl_desc_sw *new; - if (!chan) + if (!dchan) return NULL; - fsl_chan = to_fsl_chan(chan); + chan = to_fsl_chan(dchan); - new = fsl_dma_alloc_descriptor(fsl_chan); + new = fsl_dma_alloc_descriptor(chan); if (!new) { - dev_err(fsl_chan->dev, "No free memory for link descriptor\n"); + dev_err(chan->dev, "No free memory for link descriptor\n"); return NULL; } @@ -480,51 +480,51 @@ fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags) list_add_tail(&new->node, &new->tx_list); /* Set End-of-link to the last link descriptor of new list*/ - set_ld_eol(fsl_chan, new); + set_ld_eol(chan, new); return &new->async_tx; } static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( - struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src, + struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src, size_t len, unsigned long flags) { - struct fsldma_chan *fsl_chan; + struct fsldma_chan *chan; struct fsl_desc_sw *first = NULL, *prev = NULL, *new; struct list_head *list; size_t copy; - if (!chan) + if (!dchan) return NULL; if (!len) return NULL; - fsl_chan = to_fsl_chan(chan); + chan = to_fsl_chan(dchan); do { /* Allocate the link descriptor from DMA pool */ - new = fsl_dma_alloc_descriptor(fsl_chan); + new = fsl_dma_alloc_descriptor(chan); if (!new) { - dev_err(fsl_chan->dev, + dev_err(chan->dev, "No free memory for link descriptor\n"); goto fail; } #ifdef FSL_DMA_LD_DEBUG - dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new); + dev_dbg(chan->dev, "new link desc alloc %p\n", new); #endif copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); - set_desc_cnt(fsl_chan, &new->hw, copy); - set_desc_src(fsl_chan, &new->hw, dma_src); - set_desc_dst(fsl_chan, &new->hw, dma_dst); + set_desc_cnt(chan, &new->hw, copy); + set_desc_src(chan, &new->hw, dma_src); + set_desc_dst(chan, &new->hw, dma_dst); if (!first) first = new; else - set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys); + set_desc_next(chan, &prev->hw, new->async_tx.phys); new->async_tx.cookie = 0; async_tx_ack(&new->async_tx); @@ -542,7 +542,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( new->async_tx.cookie = -EBUSY; /* Set End-of-link to the last link descriptor of new list*/ - set_ld_eol(fsl_chan, new); + set_ld_eol(chan, new); return &first->async_tx; @@ -553,7 +553,7 @@ fail: list = &first->tx_list; list_for_each_entry_safe_reverse(new, prev, list, node) { list_del(&new->node); - dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys); + dma_pool_free(chan->desc_pool, new, new->async_tx.phys); } return NULL; @@ -572,10 +572,10 @@ fail: * chan->private variable. */ static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( - struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, + struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, enum dma_data_direction direction, unsigned long flags) { - struct fsldma_chan *fsl_chan; + struct fsldma_chan *chan; struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; struct fsl_dma_slave *slave; struct list_head *tx_list; @@ -588,14 +588,14 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( struct fsl_dma_hw_addr *hw; dma_addr_t dma_dst, dma_src; - if (!chan) + if (!dchan) return NULL; - if (!chan->private) + if (!dchan->private) return NULL; - fsl_chan = to_fsl_chan(chan); - slave = chan->private; + chan = to_fsl_chan(dchan); + slave = dchan->private; if (list_empty(&slave->addresses)) return NULL; @@ -644,14 +644,14 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( } /* Allocate the link descriptor from DMA pool */ - new = fsl_dma_alloc_descriptor(fsl_chan); + new = fsl_dma_alloc_descriptor(chan); if (!new) { - dev_err(fsl_chan->dev, "No free memory for " + dev_err(chan->dev, "No free memory for " "link descriptor\n"); goto fail; } #ifdef FSL_DMA_LD_DEBUG - dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new); + dev_dbg(chan->dev, "new link desc alloc %p\n", new); #endif /* @@ -678,9 +678,9 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( } /* Fill in the descriptor */ - set_desc_cnt(fsl_chan, &new->hw, copy); - set_desc_src(fsl_chan, &new->hw, dma_src); - set_desc_dst(fsl_chan, &new->hw, dma_dst); + set_desc_cnt(chan, &new->hw, copy); + set_desc_src(chan, &new->hw, dma_src); + set_desc_dst(chan, &new->hw, dma_dst); /* * If this is not the first descriptor, chain the @@ -689,7 +689,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( if (!first) { first = new; } else { - set_desc_next(fsl_chan, &prev->hw, + set_desc_next(chan, &prev->hw, new->async_tx.phys); } @@ -715,23 +715,23 @@ finished: new->async_tx.cookie = -EBUSY; /* Set End-of-link to the last link descriptor of new list */ - set_ld_eol(fsl_chan, new); + set_ld_eol(chan, new); /* Enable extra controller features */ - if (fsl_chan->set_src_loop_size) - fsl_chan->set_src_loop_size(fsl_chan, slave->src_loop_size); + if (chan->set_src_loop_size) + chan->set_src_loop_size(chan, slave->src_loop_size); - if (fsl_chan->set_dst_loop_size) - fsl_chan->set_dst_loop_size(fsl_chan, slave->dst_loop_size); + if (chan->set_dst_loop_size) + chan->set_dst_loop_size(chan, slave->dst_loop_size); - if (fsl_chan->toggle_ext_start) - fsl_chan->toggle_ext_start(fsl_chan, slave->external_start); + if (chan->toggle_ext_start) + chan->toggle_ext_start(chan, slave->external_start); - if (fsl_chan->toggle_ext_pause) - fsl_chan->toggle_ext_pause(fsl_chan, slave->external_pause); + if (chan->toggle_ext_pause) + chan->toggle_ext_pause(chan, slave->external_pause); - if (fsl_chan->set_request_count) - fsl_chan->set_request_count(fsl_chan, slave->request_count); + if (chan->set_request_count) + chan->set_request_count(chan, slave->request_count); return &first->async_tx; @@ -751,62 +751,62 @@ fail: tx_list = &first->tx_list; list_for_each_entry_safe_reverse(new, prev, tx_list, node) { list_del_init(&new->node); - dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys); + dma_pool_free(chan->desc_pool, new, new->async_tx.phys); } return NULL; } -static void fsl_dma_device_terminate_all(struct dma_chan *chan) +static void fsl_dma_device_terminate_all(struct dma_chan *dchan) { - struct fsldma_chan *fsl_chan; + struct fsldma_chan *chan; struct fsl_desc_sw *desc, *tmp; unsigned long flags; - if (!chan) + if (!dchan) return; - fsl_chan = to_fsl_chan(chan); + chan = to_fsl_chan(dchan); /* Halt the DMA engine */ - dma_halt(fsl_chan); + dma_halt(chan); - spin_lock_irqsave(&fsl_chan->desc_lock, flags); + spin_lock_irqsave(&chan->desc_lock, flags); /* Remove and free all of the descriptors in the LD queue */ - list_for_each_entry_safe(desc, tmp, &fsl_chan->ld_queue, node) { + list_for_each_entry_safe(desc, tmp, &chan->ld_queue, node) { list_del(&desc->node); - dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); } - spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); + spin_unlock_irqrestore(&chan->desc_lock, flags); } /** * fsl_dma_update_completed_cookie - Update the completed cookie. - * @fsl_chan : Freescale DMA channel + * @chan : Freescale DMA channel */ -static void fsl_dma_update_completed_cookie(struct fsldma_chan *fsl_chan) +static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan) { struct fsl_desc_sw *cur_desc, *desc; dma_addr_t ld_phy; - ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK; + ld_phy = get_cdar(chan) & FSL_DMA_NLDA_MASK; if (ld_phy) { cur_desc = NULL; - list_for_each_entry(desc, &fsl_chan->ld_queue, node) + list_for_each_entry(desc, &chan->ld_queue, node) if (desc->async_tx.phys == ld_phy) { cur_desc = desc; break; } if (cur_desc && cur_desc->async_tx.cookie) { - if (dma_is_idle(fsl_chan)) - fsl_chan->completed_cookie = + if (dma_is_idle(chan)) + chan->completed_cookie = cur_desc->async_tx.cookie; else - fsl_chan->completed_cookie = + chan->completed_cookie = cur_desc->async_tx.cookie - 1; } } @@ -814,27 +814,27 @@ static void fsl_dma_update_completed_cookie(struct fsldma_chan *fsl_chan) /** * fsl_chan_ld_cleanup - Clean up link descriptors - * @fsl_chan : Freescale DMA channel + * @chan : Freescale DMA channel * * This function clean up the ld_queue of DMA channel. * If 'in_intr' is set, the function will move the link descriptor to * the recycle list. Otherwise, free it directly. */ -static void fsl_chan_ld_cleanup(struct fsldma_chan *fsl_chan) +static void fsl_chan_ld_cleanup(struct fsldma_chan *chan) { struct fsl_desc_sw *desc, *_desc; unsigned long flags; - spin_lock_irqsave(&fsl_chan->desc_lock, flags); + spin_lock_irqsave(&chan->desc_lock, flags); - dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n", - fsl_chan->completed_cookie); - list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { + dev_dbg(chan->dev, "chan completed_cookie = %d\n", + chan->completed_cookie); + list_for_each_entry_safe(desc, _desc, &chan->ld_queue, node) { dma_async_tx_callback callback; void *callback_param; if (dma_async_is_complete(desc->async_tx.cookie, - fsl_chan->completed_cookie, fsl_chan->common.cookie) + chan->completed_cookie, chan->common.cookie) == DMA_IN_PROGRESS) break; @@ -844,119 +844,119 @@ static void fsl_chan_ld_cleanup(struct fsldma_chan *fsl_chan) /* Remove from ld_queue list */ list_del(&desc->node); - dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n", + dev_dbg(chan->dev, "link descriptor %p will be recycle.\n", desc); - dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); /* Run the link descriptor callback function */ if (callback) { - spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); - dev_dbg(fsl_chan->dev, "link descriptor %p callback\n", + spin_unlock_irqrestore(&chan->desc_lock, flags); + dev_dbg(chan->dev, "link descriptor %p callback\n", desc); callback(callback_param); - spin_lock_irqsave(&fsl_chan->desc_lock, flags); + spin_lock_irqsave(&chan->desc_lock, flags); } } - spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); + spin_unlock_irqrestore(&chan->desc_lock, flags); } /** * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue. - * @fsl_chan : Freescale DMA channel + * @chan : Freescale DMA channel */ -static void fsl_chan_xfer_ld_queue(struct fsldma_chan *fsl_chan) +static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) { struct list_head *ld_node; dma_addr_t next_dst_addr; unsigned long flags; - spin_lock_irqsave(&fsl_chan->desc_lock, flags); + spin_lock_irqsave(&chan->desc_lock, flags); - if (!dma_is_idle(fsl_chan)) + if (!dma_is_idle(chan)) goto out_unlock; - dma_halt(fsl_chan); + dma_halt(chan); /* If there are some link descriptors * not transfered in queue. We need to start it. */ /* Find the first un-transfer desciptor */ - for (ld_node = fsl_chan->ld_queue.next; - (ld_node != &fsl_chan->ld_queue) + for (ld_node = chan->ld_queue.next; + (ld_node != &chan->ld_queue) && (dma_async_is_complete( to_fsl_desc(ld_node)->async_tx.cookie, - fsl_chan->completed_cookie, - fsl_chan->common.cookie) == DMA_SUCCESS); + chan->completed_cookie, + chan->common.cookie) == DMA_SUCCESS); ld_node = ld_node->next); - if (ld_node != &fsl_chan->ld_queue) { + if (ld_node != &chan->ld_queue) { /* Get the ld start address from ld_queue */ next_dst_addr = to_fsl_desc(ld_node)->async_tx.phys; - dev_dbg(fsl_chan->dev, "xfer LDs staring from 0x%llx\n", + dev_dbg(chan->dev, "xfer LDs staring from 0x%llx\n", (unsigned long long)next_dst_addr); - set_cdar(fsl_chan, next_dst_addr); - dma_start(fsl_chan); + set_cdar(chan, next_dst_addr); + dma_start(chan); } else { - set_cdar(fsl_chan, 0); - set_ndar(fsl_chan, 0); + set_cdar(chan, 0); + set_ndar(chan, 0); } out_unlock: - spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); + spin_unlock_irqrestore(&chan->desc_lock, flags); } /** * fsl_dma_memcpy_issue_pending - Issue the DMA start command - * @fsl_chan : Freescale DMA channel + * @chan : Freescale DMA channel */ -static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan) +static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) { - struct fsldma_chan *fsl_chan = to_fsl_chan(chan); + struct fsldma_chan *chan = to_fsl_chan(dchan); #ifdef FSL_DMA_LD_DEBUG struct fsl_desc_sw *ld; unsigned long flags; - spin_lock_irqsave(&fsl_chan->desc_lock, flags); - if (list_empty(&fsl_chan->ld_queue)) { - spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); + spin_lock_irqsave(&chan->desc_lock, flags); + if (list_empty(&chan->ld_queue)) { + spin_unlock_irqrestore(&chan->desc_lock, flags); return; } - dev_dbg(fsl_chan->dev, "--memcpy issue--\n"); - list_for_each_entry(ld, &fsl_chan->ld_queue, node) { + dev_dbg(chan->dev, "--memcpy issue--\n"); + list_for_each_entry(ld, &chan->ld_queue, node) { int i; - dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n", - fsl_chan->id, ld->async_tx.phys); + dev_dbg(chan->dev, "Ch %d, LD %08x\n", + chan->id, ld->async_tx.phys); for (i = 0; i < 8; i++) - dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n", + dev_dbg(chan->dev, "LD offset %d: %08x\n", i, *(((u32 *)&ld->hw) + i)); } - dev_dbg(fsl_chan->dev, "----------------\n"); - spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); + dev_dbg(chan->dev, "----------------\n"); + spin_unlock_irqrestore(&chan->desc_lock, flags); #endif - fsl_chan_xfer_ld_queue(fsl_chan); + fsl_chan_xfer_ld_queue(chan); } /** * fsl_dma_is_complete - Determine the DMA status - * @fsl_chan : Freescale DMA channel + * @chan : Freescale DMA channel */ -static enum dma_status fsl_dma_is_complete(struct dma_chan *chan, +static enum dma_status fsl_dma_is_complete(struct dma_chan *dchan, dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used) { - struct fsldma_chan *fsl_chan = to_fsl_chan(chan); + struct fsldma_chan *chan = to_fsl_chan(dchan); dma_cookie_t last_used; dma_cookie_t last_complete; - fsl_chan_ld_cleanup(fsl_chan); + fsl_chan_ld_cleanup(chan); - last_used = chan->cookie; - last_complete = fsl_chan->completed_cookie; + last_used = dchan->cookie; + last_complete = chan->completed_cookie; if (done) *done = last_complete; @@ -973,30 +973,30 @@ static enum dma_status fsl_dma_is_complete(struct dma_chan *chan, static irqreturn_t fsldma_chan_irq(int irq, void *data) { - struct fsldma_chan *fsl_chan = data; - u32 stat; + struct fsldma_chan *chan = data; int update_cookie = 0; int xfer_ld_q = 0; + u32 stat; - stat = get_sr(fsl_chan); - dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n", - fsl_chan->id, stat); - set_sr(fsl_chan, stat); /* Clear the event register */ + stat = get_sr(chan); + dev_dbg(chan->dev, "event: channel %d, stat = 0x%x\n", + chan->id, stat); + set_sr(chan, stat); /* Clear the event register */ stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); if (!stat) return IRQ_NONE; if (stat & FSL_DMA_SR_TE) - dev_err(fsl_chan->dev, "Transfer Error!\n"); + dev_err(chan->dev, "Transfer Error!\n"); /* Programming Error * The DMA_INTERRUPT async_tx is a NULL transfer, which will * triger a PE interrupt. */ if (stat & FSL_DMA_SR_PE) { - dev_dbg(fsl_chan->dev, "event: Programming Error INT\n"); - if (get_bcr(fsl_chan) == 0) { + dev_dbg(chan->dev, "event: Programming Error INT\n"); + if (get_bcr(chan) == 0) { /* BCR register is 0, this is a DMA_INTERRUPT async_tx. * Now, update the completed cookie, and continue the * next uncompleted transfer. @@ -1011,10 +1011,10 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data) * we will recycle the used descriptor. */ if (stat & FSL_DMA_SR_EOSI) { - dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n"); - dev_dbg(fsl_chan->dev, "event: clndar 0x%llx, nlndar 0x%llx\n", - (unsigned long long)get_cdar(fsl_chan), - (unsigned long long)get_ndar(fsl_chan)); + dev_dbg(chan->dev, "event: End-of-segments INT\n"); + dev_dbg(chan->dev, "event: clndar 0x%llx, nlndar 0x%llx\n", + (unsigned long long)get_cdar(chan), + (unsigned long long)get_ndar(chan)); stat &= ~FSL_DMA_SR_EOSI; update_cookie = 1; } @@ -1023,7 +1023,7 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data) * and start the next transfer if it exist. */ if (stat & FSL_DMA_SR_EOCDI) { - dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n"); + dev_dbg(chan->dev, "event: End-of-Chain link INT\n"); stat &= ~FSL_DMA_SR_EOCDI; update_cookie = 1; xfer_ld_q = 1; @@ -1034,28 +1034,28 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data) * prepare next transfer. */ if (stat & FSL_DMA_SR_EOLNI) { - dev_dbg(fsl_chan->dev, "event: End-of-link INT\n"); + dev_dbg(chan->dev, "event: End-of-link INT\n"); stat &= ~FSL_DMA_SR_EOLNI; xfer_ld_q = 1; } if (update_cookie) - fsl_dma_update_completed_cookie(fsl_chan); + fsl_dma_update_completed_cookie(chan); if (xfer_ld_q) - fsl_chan_xfer_ld_queue(fsl_chan); + fsl_chan_xfer_ld_queue(chan); if (stat) - dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n", + dev_dbg(chan->dev, "event: unhandled sr 0x%02x\n", stat); - dev_dbg(fsl_chan->dev, "event: Exit\n"); - tasklet_schedule(&fsl_chan->tasklet); + dev_dbg(chan->dev, "event: Exit\n"); + tasklet_schedule(&chan->tasklet); return IRQ_HANDLED; } static void dma_do_tasklet(unsigned long data) { - struct fsldma_chan *fsl_chan = (struct fsldma_chan *)data; - fsl_chan_ld_cleanup(fsl_chan); + struct fsldma_chan *chan = (struct fsldma_chan *)data; + fsl_chan_ld_cleanup(chan); } static irqreturn_t fsldma_ctrl_irq(int irq, void *data) @@ -1171,24 +1171,24 @@ out_unwind: static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, struct device_node *node, u32 feature, const char *compatible) { - struct fsldma_chan *fchan; + struct fsldma_chan *chan; struct resource res; int err; /* alloc channel */ - fchan = kzalloc(sizeof(*fchan), GFP_KERNEL); - if (!fchan) { + chan = kzalloc(sizeof(*chan), GFP_KERNEL); + if (!chan) { dev_err(fdev->dev, "no free memory for DMA channels!\n"); err = -ENOMEM; goto out_return; } /* ioremap registers for use */ - fchan->regs = of_iomap(node, 0); - if (!fchan->regs) { + chan->regs = of_iomap(node, 0); + if (!chan->regs) { dev_err(fdev->dev, "unable to ioremap registers\n"); err = -ENOMEM; - goto out_free_fchan; + goto out_free_chan; } err = of_address_to_resource(node, 0, &res); @@ -1197,74 +1197,74 @@ static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, goto out_iounmap_regs; } - fchan->feature = feature; + chan->feature = feature; if (!fdev->feature) - fdev->feature = fchan->feature; + fdev->feature = chan->feature; /* * If the DMA device's feature is different than the feature * of its channels, report the bug */ - WARN_ON(fdev->feature != fchan->feature); + WARN_ON(fdev->feature != chan->feature); - fchan->dev = fdev->dev; - fchan->id = ((res.start - 0x100) & 0xfff) >> 7; - if (fchan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { + chan->dev = fdev->dev; + chan->id = ((res.start - 0x100) & 0xfff) >> 7; + if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { dev_err(fdev->dev, "too many channels for device\n"); err = -EINVAL; goto out_iounmap_regs; } - fdev->chan[fchan->id] = fchan; - tasklet_init(&fchan->tasklet, dma_do_tasklet, (unsigned long)fchan); + fdev->chan[chan->id] = chan; + tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); /* Initialize the channel */ - dma_init(fchan); + dma_init(chan); /* Clear cdar registers */ - set_cdar(fchan, 0); + set_cdar(chan, 0); - switch (fchan->feature & FSL_DMA_IP_MASK) { + switch (chan->feature & FSL_DMA_IP_MASK) { case FSL_DMA_IP_85XX: - fchan->toggle_ext_pause = fsl_chan_toggle_ext_pause; + chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; case FSL_DMA_IP_83XX: - fchan->toggle_ext_start = fsl_chan_toggle_ext_start; - fchan->set_src_loop_size = fsl_chan_set_src_loop_size; - fchan->set_dst_loop_size = fsl_chan_set_dst_loop_size; - fchan->set_request_count = fsl_chan_set_request_count; + chan->toggle_ext_start = fsl_chan_toggle_ext_start; + chan->set_src_loop_size = fsl_chan_set_src_loop_size; + chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; + chan->set_request_count = fsl_chan_set_request_count; } - spin_lock_init(&fchan->desc_lock); - INIT_LIST_HEAD(&fchan->ld_queue); + spin_lock_init(&chan->desc_lock); + INIT_LIST_HEAD(&chan->ld_queue); - fchan->common.device = &fdev->common; + chan->common.device = &fdev->common; /* find the IRQ line, if it exists in the device tree */ - fchan->irq = irq_of_parse_and_map(node, 0); + chan->irq = irq_of_parse_and_map(node, 0); /* Add the channel to DMA device channel list */ - list_add_tail(&fchan->common.device_node, &fdev->common.channels); + list_add_tail(&chan->common.device_node, &fdev->common.channels); fdev->common.chancnt++; - dev_info(fdev->dev, "#%d (%s), irq %d\n", fchan->id, compatible, - fchan->irq != NO_IRQ ? fchan->irq : fdev->irq); + dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, + chan->irq != NO_IRQ ? chan->irq : fdev->irq); return 0; out_iounmap_regs: - iounmap(fchan->regs); -out_free_fchan: - kfree(fchan); + iounmap(chan->regs); +out_free_chan: + kfree(chan); out_return: return err; } -static void fsl_dma_chan_remove(struct fsldma_chan *fchan) +static void fsl_dma_chan_remove(struct fsldma_chan *chan) { - irq_dispose_mapping(fchan->irq); - list_del(&fchan->common.device_node); - iounmap(fchan->regs); - kfree(fchan); + irq_dispose_mapping(chan->irq); + list_del(&chan->common.device_node); + iounmap(chan->regs); + kfree(chan); } static int __devinit fsldma_of_probe(struct of_device *op, -- cgit v1.2.3 From 9c3a50b7d7ec45da34e73cac66cde12dd6092dd8 Mon Sep 17 00:00:00 2001 From: Ira Snyder Date: Wed, 6 Jan 2010 13:34:06 +0000 Subject: fsldma: major cleanups and fixes Fix locking. Use two queues in the driver, one for pending transacions, and one for transactions which are actually running on the hardware. Call dma_run_dependencies() on descriptor cleanup so that the async_tx API works correctly. There are a number of places throughout the code where lists of descriptors are freed in a loop. Create functions to handle this, and use them instead of open-coding the loop each time. Signed-off-by: Ira W. Snyder Signed-off-by: Dan Williams --- drivers/dma/fsldma.c | 386 +++++++++++++++++++++++++++------------------------ drivers/dma/fsldma.h | 3 +- 2 files changed, 207 insertions(+), 182 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 7b5f88cb495b..19011c20390b 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -61,7 +61,6 @@ static void dma_init(struct fsldma_chan *chan) | FSL_DMA_MR_PRC_RM, 32); break; } - } static void set_sr(struct fsldma_chan *chan, u32 val) @@ -120,11 +119,6 @@ static dma_addr_t get_cdar(struct fsldma_chan *chan) return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; } -static void set_ndar(struct fsldma_chan *chan, dma_addr_t addr) -{ - DMA_OUT(chan, &chan->regs->ndar, addr, 64); -} - static dma_addr_t get_ndar(struct fsldma_chan *chan) { return DMA_IN(chan, &chan->regs->ndar, 64); @@ -178,11 +172,12 @@ static void dma_halt(struct fsldma_chan *chan) for (i = 0; i < 100; i++) { if (dma_is_idle(chan)) - break; + return; + udelay(10); } - if (i >= 100 && !dma_is_idle(chan)) + if (!dma_is_idle(chan)) dev_err(chan->dev, "DMA halt timeout!\n"); } @@ -199,27 +194,6 @@ static void set_ld_eol(struct fsldma_chan *chan, | snoop_bits, 64); } -static void append_ld_queue(struct fsldma_chan *chan, - struct fsl_desc_sw *new_desc) -{ - struct fsl_desc_sw *queue_tail = to_fsl_desc(chan->ld_queue.prev); - - if (list_empty(&chan->ld_queue)) - return; - - /* Link to the new descriptor physical address and - * Enable End-of-segment interrupt for - * the last link descriptor. - * (the previous node's next link descriptor) - * - * For FSL_DMA_IP_83xx, the snoop enable bit need be set. - */ - queue_tail->hw.next_ln_addr = CPU_TO_DMA(chan, - new_desc->async_tx.phys | FSL_DMA_EOSIE | - (((chan->feature & FSL_DMA_IP_MASK) - == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64); -} - /** * fsl_chan_set_src_loop_size - Set source address hold transfer size * @chan : Freescale DMA channel @@ -343,6 +317,31 @@ static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) chan->feature &= ~FSL_DMA_CHAN_START_EXT; } +static void append_ld_queue(struct fsldma_chan *chan, + struct fsl_desc_sw *desc) +{ + struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); + + if (list_empty(&chan->ld_pending)) + goto out_splice; + + /* + * Add the hardware descriptor to the chain of hardware descriptors + * that already exists in memory. + * + * This will un-set the EOL bit of the existing transaction, and the + * last link in this transaction will become the EOL descriptor. + */ + set_desc_next(chan, &tail->hw, desc->async_tx.phys); + + /* + * Add the software descriptor and all children to the list + * of pending transactions + */ +out_splice: + list_splice_tail_init(&desc->tx_list, &chan->ld_pending); +} + static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) { struct fsldma_chan *chan = to_fsl_chan(tx->chan); @@ -351,9 +350,12 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) unsigned long flags; dma_cookie_t cookie; - /* cookie increment and adding to ld_queue must be atomic */ spin_lock_irqsave(&chan->desc_lock, flags); + /* + * assign cookies to all of the software descriptors + * that make up this transaction + */ cookie = chan->common.cookie; list_for_each_entry(child, &desc->tx_list, node) { cookie++; @@ -364,8 +366,9 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) } chan->common.cookie = cookie; + + /* put this transaction onto the tail of the pending queue */ append_ld_queue(chan, desc); - list_splice_init(&desc->tx_list, chan->ld_queue.prev); spin_unlock_irqrestore(&chan->desc_lock, flags); @@ -381,20 +384,22 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) static struct fsl_desc_sw *fsl_dma_alloc_descriptor( struct fsldma_chan *chan) { + struct fsl_desc_sw *desc; dma_addr_t pdesc; - struct fsl_desc_sw *desc_sw; - - desc_sw = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); - if (desc_sw) { - memset(desc_sw, 0, sizeof(struct fsl_desc_sw)); - INIT_LIST_HEAD(&desc_sw->tx_list); - dma_async_tx_descriptor_init(&desc_sw->async_tx, - &chan->common); - desc_sw->async_tx.tx_submit = fsl_dma_tx_submit; - desc_sw->async_tx.phys = pdesc; + + desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); + if (!desc) { + dev_dbg(chan->dev, "out of memory for link desc\n"); + return NULL; } - return desc_sw; + memset(desc, 0, sizeof(*desc)); + INIT_LIST_HEAD(&desc->tx_list); + dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); + desc->async_tx.tx_submit = fsl_dma_tx_submit; + desc->async_tx.phys = pdesc; + + return desc; } @@ -414,21 +419,53 @@ static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) if (chan->desc_pool) return 1; - /* We need the descriptor to be aligned to 32bytes + /* + * We need the descriptor to be aligned to 32bytes * for meeting FSL DMA specification requirement. */ chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", - chan->dev, sizeof(struct fsl_desc_sw), - 32, 0); + chan->dev, + sizeof(struct fsl_desc_sw), + __alignof__(struct fsl_desc_sw), 0); if (!chan->desc_pool) { - dev_err(chan->dev, "No memory for channel %d " - "descriptor dma pool.\n", chan->id); - return 0; + dev_err(chan->dev, "unable to allocate channel %d " + "descriptor pool\n", chan->id); + return -ENOMEM; } + /* there is at least one descriptor free to be allocated */ return 1; } +/** + * fsldma_free_desc_list - Free all descriptors in a queue + * @chan: Freescae DMA channel + * @list: the list to free + * + * LOCKING: must hold chan->desc_lock + */ +static void fsldma_free_desc_list(struct fsldma_chan *chan, + struct list_head *list) +{ + struct fsl_desc_sw *desc, *_desc; + + list_for_each_entry_safe(desc, _desc, list, node) { + list_del(&desc->node); + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); + } +} + +static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, + struct list_head *list) +{ + struct fsl_desc_sw *desc, *_desc; + + list_for_each_entry_safe_reverse(desc, _desc, list, node) { + list_del(&desc->node); + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); + } +} + /** * fsl_dma_free_chan_resources - Free all resources of the channel. * @chan : Freescale DMA channel @@ -436,23 +473,15 @@ static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) static void fsl_dma_free_chan_resources(struct dma_chan *dchan) { struct fsldma_chan *chan = to_fsl_chan(dchan); - struct fsl_desc_sw *desc, *_desc; unsigned long flags; dev_dbg(chan->dev, "Free all channel resources.\n"); spin_lock_irqsave(&chan->desc_lock, flags); - list_for_each_entry_safe(desc, _desc, &chan->ld_queue, node) { -#ifdef FSL_DMA_LD_DEBUG - dev_dbg(chan->dev, - "LD %p will be released.\n", desc); -#endif - list_del(&desc->node); - /* free link descriptor */ - dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); - } + fsldma_free_desc_list(chan, &chan->ld_pending); + fsldma_free_desc_list(chan, &chan->ld_running); spin_unlock_irqrestore(&chan->desc_lock, flags); - dma_pool_destroy(chan->desc_pool); + dma_pool_destroy(chan->desc_pool); chan->desc_pool = NULL; } @@ -491,7 +520,6 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( { struct fsldma_chan *chan; struct fsl_desc_sw *first = NULL, *prev = NULL, *new; - struct list_head *list; size_t copy; if (!dchan) @@ -550,12 +578,7 @@ fail: if (!first) return NULL; - list = &first->tx_list; - list_for_each_entry_safe_reverse(new, prev, list, node) { - list_del(&new->node); - dma_pool_free(chan->desc_pool, new, new->async_tx.phys); - } - + fsldma_free_desc_list_reverse(chan, &first->tx_list); return NULL; } @@ -578,7 +601,6 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( struct fsldma_chan *chan; struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; struct fsl_dma_slave *slave; - struct list_head *tx_list; size_t copy; int i; @@ -748,19 +770,13 @@ fail: * * We're re-using variables for the loop, oh well */ - tx_list = &first->tx_list; - list_for_each_entry_safe_reverse(new, prev, tx_list, node) { - list_del_init(&new->node); - dma_pool_free(chan->desc_pool, new, new->async_tx.phys); - } - + fsldma_free_desc_list_reverse(chan, &first->tx_list); return NULL; } static void fsl_dma_device_terminate_all(struct dma_chan *dchan) { struct fsldma_chan *chan; - struct fsl_desc_sw *desc, *tmp; unsigned long flags; if (!dchan) @@ -774,10 +790,8 @@ static void fsl_dma_device_terminate_all(struct dma_chan *dchan) spin_lock_irqsave(&chan->desc_lock, flags); /* Remove and free all of the descriptors in the LD queue */ - list_for_each_entry_safe(desc, tmp, &chan->ld_queue, node) { - list_del(&desc->node); - dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); - } + fsldma_free_desc_list(chan, &chan->ld_pending); + fsldma_free_desc_list(chan, &chan->ld_running); spin_unlock_irqrestore(&chan->desc_lock, flags); } @@ -785,31 +799,48 @@ static void fsl_dma_device_terminate_all(struct dma_chan *dchan) /** * fsl_dma_update_completed_cookie - Update the completed cookie. * @chan : Freescale DMA channel + * + * CONTEXT: hardirq */ static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan) { - struct fsl_desc_sw *cur_desc, *desc; - dma_addr_t ld_phy; - - ld_phy = get_cdar(chan) & FSL_DMA_NLDA_MASK; + struct fsl_desc_sw *desc; + unsigned long flags; + dma_cookie_t cookie; - if (ld_phy) { - cur_desc = NULL; - list_for_each_entry(desc, &chan->ld_queue, node) - if (desc->async_tx.phys == ld_phy) { - cur_desc = desc; - break; - } + spin_lock_irqsave(&chan->desc_lock, flags); - if (cur_desc && cur_desc->async_tx.cookie) { - if (dma_is_idle(chan)) - chan->completed_cookie = - cur_desc->async_tx.cookie; - else - chan->completed_cookie = - cur_desc->async_tx.cookie - 1; - } + if (list_empty(&chan->ld_running)) { + dev_dbg(chan->dev, "no running descriptors\n"); + goto out_unlock; } + + /* Get the last descriptor, update the cookie to that */ + desc = to_fsl_desc(chan->ld_running.prev); + if (dma_is_idle(chan)) + cookie = desc->async_tx.cookie; + else + cookie = desc->async_tx.cookie - 1; + + chan->completed_cookie = cookie; + +out_unlock: + spin_unlock_irqrestore(&chan->desc_lock, flags); +} + +/** + * fsldma_desc_status - Check the status of a descriptor + * @chan: Freescale DMA channel + * @desc: DMA SW descriptor + * + * This function will return the status of the given descriptor + */ +static enum dma_status fsldma_desc_status(struct fsldma_chan *chan, + struct fsl_desc_sw *desc) +{ + return dma_async_is_complete(desc->async_tx.cookie, + chan->completed_cookie, + chan->common.cookie); } /** @@ -817,8 +848,6 @@ static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan) * @chan : Freescale DMA channel * * This function clean up the ld_queue of DMA channel. - * If 'in_intr' is set, the function will move the link descriptor to - * the recycle list. Otherwise, free it directly. */ static void fsl_chan_ld_cleanup(struct fsldma_chan *chan) { @@ -827,80 +856,95 @@ static void fsl_chan_ld_cleanup(struct fsldma_chan *chan) spin_lock_irqsave(&chan->desc_lock, flags); - dev_dbg(chan->dev, "chan completed_cookie = %d\n", - chan->completed_cookie); - list_for_each_entry_safe(desc, _desc, &chan->ld_queue, node) { + dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie); + list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { dma_async_tx_callback callback; void *callback_param; - if (dma_async_is_complete(desc->async_tx.cookie, - chan->completed_cookie, chan->common.cookie) - == DMA_IN_PROGRESS) + if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS) break; - callback = desc->async_tx.callback; - callback_param = desc->async_tx.callback_param; - - /* Remove from ld_queue list */ + /* Remove from the list of running transactions */ list_del(&desc->node); - dev_dbg(chan->dev, "link descriptor %p will be recycle.\n", - desc); - dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); - /* Run the link descriptor callback function */ + callback = desc->async_tx.callback; + callback_param = desc->async_tx.callback_param; if (callback) { spin_unlock_irqrestore(&chan->desc_lock, flags); - dev_dbg(chan->dev, "link descriptor %p callback\n", - desc); + dev_dbg(chan->dev, "LD %p callback\n", desc); callback(callback_param); spin_lock_irqsave(&chan->desc_lock, flags); } + + /* Run any dependencies, then free the descriptor */ + dma_run_dependencies(&desc->async_tx); + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); } + spin_unlock_irqrestore(&chan->desc_lock, flags); } /** - * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue. + * fsl_chan_xfer_ld_queue - transfer any pending transactions * @chan : Freescale DMA channel + * + * This will make sure that any pending transactions will be run. + * If the DMA controller is idle, it will be started. Otherwise, + * the DMA controller's interrupt handler will start any pending + * transactions when it becomes idle. */ static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) { - struct list_head *ld_node; - dma_addr_t next_dst_addr; + struct fsl_desc_sw *desc; unsigned long flags; spin_lock_irqsave(&chan->desc_lock, flags); - if (!dma_is_idle(chan)) + /* + * If the list of pending descriptors is empty, then we + * don't need to do any work at all + */ + if (list_empty(&chan->ld_pending)) { + dev_dbg(chan->dev, "no pending LDs\n"); goto out_unlock; + } + /* + * The DMA controller is not idle, which means the interrupt + * handler will start any queued transactions when it runs + * at the end of the current transaction + */ + if (!dma_is_idle(chan)) { + dev_dbg(chan->dev, "DMA controller still busy\n"); + goto out_unlock; + } + + /* + * TODO: + * make sure the dma_halt() function really un-wedges the + * controller as much as possible + */ dma_halt(chan); - /* If there are some link descriptors - * not transfered in queue. We need to start it. + /* + * If there are some link descriptors which have not been + * transferred, we need to start the controller */ - /* Find the first un-transfer desciptor */ - for (ld_node = chan->ld_queue.next; - (ld_node != &chan->ld_queue) - && (dma_async_is_complete( - to_fsl_desc(ld_node)->async_tx.cookie, - chan->completed_cookie, - chan->common.cookie) == DMA_SUCCESS); - ld_node = ld_node->next); - - if (ld_node != &chan->ld_queue) { - /* Get the ld start address from ld_queue */ - next_dst_addr = to_fsl_desc(ld_node)->async_tx.phys; - dev_dbg(chan->dev, "xfer LDs staring from 0x%llx\n", - (unsigned long long)next_dst_addr); - set_cdar(chan, next_dst_addr); - dma_start(chan); - } else { - set_cdar(chan, 0); - set_ndar(chan, 0); - } + /* + * Move all elements from the queue of pending transactions + * onto the list of running transactions + */ + desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); + list_splice_tail_init(&chan->ld_pending, &chan->ld_running); + + /* + * Program the descriptor's address into the DMA controller, + * then start the DMA transaction + */ + set_cdar(chan, desc->async_tx.phys); + dma_start(chan); out_unlock: spin_unlock_irqrestore(&chan->desc_lock, flags); @@ -913,30 +957,6 @@ out_unlock: static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) { struct fsldma_chan *chan = to_fsl_chan(dchan); - -#ifdef FSL_DMA_LD_DEBUG - struct fsl_desc_sw *ld; - unsigned long flags; - - spin_lock_irqsave(&chan->desc_lock, flags); - if (list_empty(&chan->ld_queue)) { - spin_unlock_irqrestore(&chan->desc_lock, flags); - return; - } - - dev_dbg(chan->dev, "--memcpy issue--\n"); - list_for_each_entry(ld, &chan->ld_queue, node) { - int i; - dev_dbg(chan->dev, "Ch %d, LD %08x\n", - chan->id, ld->async_tx.phys); - for (i = 0; i < 8; i++) - dev_dbg(chan->dev, "LD offset %d: %08x\n", - i, *(((u32 *)&ld->hw) + i)); - } - dev_dbg(chan->dev, "----------------\n"); - spin_unlock_irqrestore(&chan->desc_lock, flags); -#endif - fsl_chan_xfer_ld_queue(chan); } @@ -978,10 +998,10 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data) int xfer_ld_q = 0; u32 stat; + /* save and clear the status register */ stat = get_sr(chan); - dev_dbg(chan->dev, "event: channel %d, stat = 0x%x\n", - chan->id, stat); - set_sr(chan, stat); /* Clear the event register */ + set_sr(chan, stat); + dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat); stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); if (!stat) @@ -990,12 +1010,13 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data) if (stat & FSL_DMA_SR_TE) dev_err(chan->dev, "Transfer Error!\n"); - /* Programming Error + /* + * Programming Error * The DMA_INTERRUPT async_tx is a NULL transfer, which will * triger a PE interrupt. */ if (stat & FSL_DMA_SR_PE) { - dev_dbg(chan->dev, "event: Programming Error INT\n"); + dev_dbg(chan->dev, "irq: Programming Error INT\n"); if (get_bcr(chan) == 0) { /* BCR register is 0, this is a DMA_INTERRUPT async_tx. * Now, update the completed cookie, and continue the @@ -1007,34 +1028,37 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data) stat &= ~FSL_DMA_SR_PE; } - /* If the link descriptor segment transfer finishes, + /* + * If the link descriptor segment transfer finishes, * we will recycle the used descriptor. */ if (stat & FSL_DMA_SR_EOSI) { - dev_dbg(chan->dev, "event: End-of-segments INT\n"); - dev_dbg(chan->dev, "event: clndar 0x%llx, nlndar 0x%llx\n", + dev_dbg(chan->dev, "irq: End-of-segments INT\n"); + dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n", (unsigned long long)get_cdar(chan), (unsigned long long)get_ndar(chan)); stat &= ~FSL_DMA_SR_EOSI; update_cookie = 1; } - /* For MPC8349, EOCDI event need to update cookie + /* + * For MPC8349, EOCDI event need to update cookie * and start the next transfer if it exist. */ if (stat & FSL_DMA_SR_EOCDI) { - dev_dbg(chan->dev, "event: End-of-Chain link INT\n"); + dev_dbg(chan->dev, "irq: End-of-Chain link INT\n"); stat &= ~FSL_DMA_SR_EOCDI; update_cookie = 1; xfer_ld_q = 1; } - /* If it current transfer is the end-of-transfer, + /* + * If it current transfer is the end-of-transfer, * we should clear the Channel Start bit for * prepare next transfer. */ if (stat & FSL_DMA_SR_EOLNI) { - dev_dbg(chan->dev, "event: End-of-link INT\n"); + dev_dbg(chan->dev, "irq: End-of-link INT\n"); stat &= ~FSL_DMA_SR_EOLNI; xfer_ld_q = 1; } @@ -1044,10 +1068,9 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data) if (xfer_ld_q) fsl_chan_xfer_ld_queue(chan); if (stat) - dev_dbg(chan->dev, "event: unhandled sr 0x%02x\n", - stat); + dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat); - dev_dbg(chan->dev, "event: Exit\n"); + dev_dbg(chan->dev, "irq: Exit\n"); tasklet_schedule(&chan->tasklet); return IRQ_HANDLED; } @@ -1235,7 +1258,8 @@ static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, } spin_lock_init(&chan->desc_lock); - INIT_LIST_HEAD(&chan->ld_queue); + INIT_LIST_HEAD(&chan->ld_pending); + INIT_LIST_HEAD(&chan->ld_running); chan->common.device = &fdev->common; diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index ea3b19c8708c..cb4d6ff51597 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -131,7 +131,8 @@ struct fsldma_chan { struct fsldma_chan_regs __iomem *regs; dma_cookie_t completed_cookie; /* The maximum cookie completed */ spinlock_t desc_lock; /* Descriptor operation lock */ - struct list_head ld_queue; /* Link descriptors queue */ + struct list_head ld_pending; /* Link descriptors queue */ + struct list_head ld_running; /* Link descriptors queue */ struct dma_chan common; /* DMA common channel */ struct dma_pool *desc_pool; /* Descriptors pool */ struct device *dev; /* Channel device */ -- cgit v1.2.3 From 5324dc0e3872324ed0bf372bce7bc437436910b6 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Tue, 2 Feb 2010 14:45:04 -0800 Subject: da9030_battery: fix spelling in comment platfrom -> platform monotor -> monitor Signed-off-by: Stefan Weil Cc: Anton Vorontsov Acked-by: Mike Rapoport Signed-off-by: Andrew Morton Signed-off-by: Anton Vorontsov --- drivers/power/da9030_battery.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/da9030_battery.c b/drivers/power/da9030_battery.c index 3364198134a1..a2e71f7b27fb 100644 --- a/drivers/power/da9030_battery.c +++ b/drivers/power/da9030_battery.c @@ -509,7 +509,7 @@ static int da9030_battery_probe(struct platform_device *pdev) charger->master = pdev->dev.parent; - /* 10 seconds between monotor runs unless platfrom defines other + /* 10 seconds between monitor runs unless platform defines other interval */ charger->interval = msecs_to_jiffies( (pdata->batmon_interval ? : 10) * 1000); -- cgit v1.2.3 From 21030403209f0c253d462492f881c613bd8eeda2 Mon Sep 17 00:00:00 2001 From: Michel Pollet Date: Wed, 27 Jan 2010 16:38:08 +0000 Subject: ARM: S3C2412: SoC has the fractional baud rate register The S3C2412 has a fractional baud rate register, this patch adds the corresponding flag to the UART definition to allow generation of more precise baud rates for the various clock combinations. Signed-off-by: Michel Pollet Signed-off-by: Ben Dooks --- drivers/serial/s3c2412.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/serial/s3c2412.c b/drivers/serial/s3c2412.c index ce75e28e36ef..1700b1a2fb7e 100644 --- a/drivers/serial/s3c2412.c +++ b/drivers/serial/s3c2412.c @@ -102,6 +102,7 @@ static struct s3c24xx_uart_info s3c2412_uart_inf = { .name = "Samsung S3C2412 UART", .type = PORT_S3C2412, .fifosize = 64, + .has_divslot = 1, .rx_fifomask = S3C2440_UFSTAT_RXMASK, .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, .rx_fifofull = S3C2440_UFSTAT_RXFULL, -- cgit v1.2.3 From 3bd9377e8761cb7f1000b3075763df779ab9aeca Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 10:52:02 +0900 Subject: ARM: SAMSUNG: Add SERIAL_SAMSUNG_UARTS_4 Kconfig option Add SERIAL_SAMSUNG_UARTS_4 to mop up the number of cases currently using four Samsung compatible UARTS. Signed-off-by: Ben Dooks --- drivers/serial/Kconfig | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ebdd2b984d16..1d47c770c3b8 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -455,11 +455,18 @@ config SERIAL_SAMSUNG provide all of these ports, depending on how the serial port pins are configured. +config SERIAL_SAMSUNG_UARTS_4 + bool + depends on ARM && PLAT_SAMSUNG + default y if CPU_S3C2443 + help + Internal node for the common case of 4 Samsung compatible UARTs + config SERIAL_SAMSUNG_UARTS int depends on ARM && PLAT_S3C default 2 if ARCH_S3C2400 - default 4 if ARCH_S5P6440 || ARCH_S5PC1XX || ARCH_S5PV210 || ARCH_S3C64XX || CPU_S3C2443 + default 4 if SERIAL_SAMSUNG_UARTS_4 default 3 help Select the number of available UART ports for the Samsung S3C @@ -526,8 +533,9 @@ config SERIAL_S3C24A0 Serial port support for the Samsung S3C24A0 SoC config SERIAL_S3C6400 - tristate "Samsung S3C6400/S3C6410/S5P6440 Serial port support" + tristate "Samsung S3C6400/S3C6410/S5P6440 Seria port support" depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410 || CPU_S5P6440) + select SERIAL_SAMSUNG_UARTS_4 default y help Serial port support for the Samsung S3C6400, S3C6410 and S5P6440 @@ -536,6 +544,7 @@ config SERIAL_S3C6400 config SERIAL_S5PC100 tristate "Samsung S5PC100 Serial port support" depends on SERIAL_SAMSUNG && CPU_S5PC100 + select SERIAL_SAMSUNG_UARTS_4 default y help Serial port support for the Samsung S5PC100 SoCs @@ -543,6 +552,7 @@ config SERIAL_S5PC100 config SERIAL_S5PV210 tristate "Samsung S5PV210 Serial port support" depends on SERIAL_SAMSUNG && CPU_S5PV210 + select SERIAL_SAMSUNG_UARTS_4 default y help Serial port support for Samsung's S5P Family of SoC's -- cgit v1.2.3 From 1de203adf6210b9dd81d907ea8cda587bc61cf4c Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 29 Jan 2010 10:53:35 +0900 Subject: ARM: SAMSUNG: Use PLAT_SAMSUNG instead of PLAT_S3C As part of the development process, it is hoped PLAT_S3C is either removed from all of the PLAT_SAMSUNG derived platforms or removed entirely. It is also better to use PLAT_SAMSUNG as this is the current base of all Samsung devices. Change the two places that use PLAT_S3C to use PLAT_SAMSUNG Signed-off-by: Ben Dooks --- drivers/serial/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 1d47c770c3b8..b2157c36566d 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -447,7 +447,7 @@ config SERIAL_CLPS711X_CONSOLE config SERIAL_SAMSUNG tristate "Samsung SoC serial support" - depends on ARM && PLAT_S3C + depends on ARM && PLAT_SAMSUNG select SERIAL_CORE help Support for the on-chip UARTs on the Samsung S3C24XX series CPUs, @@ -464,7 +464,7 @@ config SERIAL_SAMSUNG_UARTS_4 config SERIAL_SAMSUNG_UARTS int - depends on ARM && PLAT_S3C + depends on ARM && PLAT_SAMSUNG default 2 if ARCH_S3C2400 default 4 if SERIAL_SAMSUNG_UARTS_4 default 3 -- cgit v1.2.3 From 4b1cf1facca31b7db2a61d8aa2ba40d5a93a0957 Mon Sep 17 00:00:00 2001 From: Márton Németh Date: Tue, 2 Feb 2010 23:41:06 -0700 Subject: dma: make Open Firmware device id constant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The match_table field of the struct of_device_id is constant in so it is worth to make the initialization data also constant. The semantic match that finds this kind of pattern is as follows: (http://coccinelle.lip6.fr/) // @r@ disable decl_init,const_decl_init; identifier I1, I2, x; @@ struct I1 { ... const struct I2 *x; ... }; @s@ identifier r.I1, y; identifier r.x, E; @@ struct I1 y = { .x = E, }; @c@ identifier r.I2; identifier s.E; @@ const struct I2 E[] = ... ; @depends on !c@ identifier r.I2; identifier s.E; @@ + const struct I2 E[] = ...; // Signed-off-by: Márton Németh Cc: Julia Lawall Cc: cocci@diku.dk [dan.j.williams@intel.com: resolved conflict with recent fsldma updates] Signed-off-by: Dan Williams --- drivers/dma/fsldma.c | 2 +- drivers/dma/ppc4xx/adma.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 19011c20390b..92efa87258b9 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -1398,7 +1398,7 @@ static int fsldma_of_remove(struct of_device *op) return 0; } -static struct of_device_id fsldma_of_ids[] = { +static const struct of_device_id fsldma_of_ids[] = { { .compatible = "fsl,eloplus-dma", }, { .compatible = "fsl,elo-dma", }, {} diff --git a/drivers/dma/ppc4xx/adma.c b/drivers/dma/ppc4xx/adma.c index 0a3478e910f0..e69d87f24a25 100644 --- a/drivers/dma/ppc4xx/adma.c +++ b/drivers/dma/ppc4xx/adma.c @@ -4940,7 +4940,7 @@ out_free: return ret; } -static struct of_device_id __devinitdata ppc440spe_adma_of_match[] = { +static const struct of_device_id ppc440spe_adma_of_match[] __devinitconst = { { .compatible = "ibm,dma-440spe", }, { .compatible = "amcc,xor-accelerator", }, {}, -- cgit v1.2.3 From 9ad7bd2944bd979ef4877cd439719be44c5f3b47 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Wed, 20 Jan 2010 01:25:56 +0100 Subject: dma: cases IPU_PIX_FMT_BGRA32, BGR32 and ABGR32 are the same in ipu_ch_param_set_size() In these cases the same statements are executed. Signed-off-by: Roel Kluin Acked-by: Guennadi Liakhovetski Signed-off-by: Andrew Morton Signed-off-by: Dan Williams --- drivers/dma/ipu/ipu_idmac.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c index 9a5bc1a7389e..1c518f1cc49b 100644 --- a/drivers/dma/ipu/ipu_idmac.c +++ b/drivers/dma/ipu/ipu_idmac.c @@ -348,6 +348,7 @@ static void ipu_ch_param_set_size(union chan_param_mem *params, break; case IPU_PIX_FMT_BGRA32: case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_ABGR32: params->ip.bpp = 0; params->ip.pfs = 4; params->ip.npb = 7; @@ -376,20 +377,6 @@ static void ipu_ch_param_set_size(union chan_param_mem *params, params->ip.wid2 = 7; /* Blue bit width - 1 */ params->ip.wid3 = 7; /* Alpha bit width - 1 */ break; - case IPU_PIX_FMT_ABGR32: - params->ip.bpp = 0; - params->ip.pfs = 4; - params->ip.npb = 7; - params->ip.sat = 2; /* SAT = 32-bit access */ - params->ip.ofs0 = 8; /* Red bit offset */ - params->ip.ofs1 = 16; /* Green bit offset */ - params->ip.ofs2 = 24; /* Blue bit offset */ - params->ip.ofs3 = 0; /* Alpha bit offset */ - params->ip.wid0 = 7; /* Red bit width - 1 */ - params->ip.wid1 = 7; /* Green bit width - 1 */ - params->ip.wid2 = 7; /* Blue bit width - 1 */ - params->ip.wid3 = 7; /* Alpha bit width - 1 */ - break; case IPU_PIX_FMT_UYVY: params->ip.bpp = 2; params->ip.pfs = 6; -- cgit v1.2.3 From b1681c56f5b6bf551bed2617a395855055836571 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 3 Feb 2010 18:44:44 -0800 Subject: drivers/ide: Fix continuation line formats String constants that are continued on subsequent lines with \ are not good. Signed-off-by: Joe Perches Signed-off-by: David S. Miller --- drivers/ide/au1xxx-ide.c | 4 ++-- drivers/ide/pmac.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/ide/au1xxx-ide.c b/drivers/ide/au1xxx-ide.c index e2fd378ba9de..bd0930a60b0c 100644 --- a/drivers/ide/au1xxx-ide.c +++ b/drivers/ide/au1xxx-ide.c @@ -299,8 +299,8 @@ static int auide_dma_test_irq(ide_drive_t *drive) */ drive->waiting_for_dma++; if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) { - printk(KERN_WARNING "%s: timeout waiting for ddma to \ - complete\n", drive->name); + printk(KERN_WARNING "%s: timeout waiting for ddma to complete\n", + drive->name); return 1; } udelay(10); diff --git a/drivers/ide/pmac.c b/drivers/ide/pmac.c index 9fae1fb1468b..850ee452e9bb 100644 --- a/drivers/ide/pmac.c +++ b/drivers/ide/pmac.c @@ -1650,8 +1650,8 @@ pmac_ide_dma_test_irq (ide_drive_t *drive) if ((status & FLUSH) == 0) break; if (++timeout > 100) { - printk(KERN_WARNING "ide%d, ide_dma_test_irq \ - timeout flushing channel\n", hwif->index); + printk(KERN_WARNING "ide%d, ide_dma_test_irq timeout flushing channel\n", + hwif->index); break; } } -- cgit v1.2.3 From c5c7b32d3c67049ab4e509d0e8bf93811c433dfb Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Sun, 13 Dec 2009 20:07:31 +0100 Subject: ataflop: Killl warning about unused variable flags After commit e0c0978699a83f26f2341f7eedc1463b79e31aff ("ataflop: remove buggy/commented-out IRQ disable from do_fd_request()") the `flags' variable became unused: drivers/block/ataflop.c:1473: warning: unused variable 'flags' Hence remove it. Signed-off-by: Geert Uytterhoeven Signed-off-by: Jiri Kosina --- drivers/block/ataflop.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers') diff --git a/drivers/block/ataflop.c b/drivers/block/ataflop.c index a5af1d6dda8b..e35cf59cbfde 100644 --- a/drivers/block/ataflop.c +++ b/drivers/block/ataflop.c @@ -1470,8 +1470,6 @@ repeat: void do_fd_request(struct request_queue * q) { - unsigned long flags; - DPRINT(("do_fd_request for pid %d\n",current->pid)); while( fdc_busy ) sleep_on( &fdc_wait ); fdc_busy = 1; -- cgit v1.2.3 From c14e522b1aab6a1a3765db182aacca4f359f6d91 Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Wed, 16 Dec 2009 23:13:44 +0100 Subject: tree wide: remove execute flag from .c files Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Jiri Kosina --- arch/arm/mach-omap2/board-3630sdp.c | 0 arch/arm/mach-omap2/board-zoom-peripherals.c | 0 drivers/mtd/chips/cfi_util.c | 0 drivers/mtd/inftlcore.c | 0 4 files changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 arch/arm/mach-omap2/board-3630sdp.c mode change 100755 => 100644 arch/arm/mach-omap2/board-zoom-peripherals.c mode change 100755 => 100644 drivers/mtd/chips/cfi_util.c mode change 100755 => 100644 drivers/mtd/inftlcore.c (limited to 'drivers') diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c old mode 100755 new mode 100644 diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c old mode 100755 new mode 100644 diff --git a/drivers/mtd/chips/cfi_util.c b/drivers/mtd/chips/cfi_util.c old mode 100755 new mode 100644 diff --git a/drivers/mtd/inftlcore.c b/drivers/mtd/inftlcore.c old mode 100755 new mode 100644 -- cgit v1.2.3 From 303863f43fa5106637325a213717b2f306e2efc3 Mon Sep 17 00:00:00 2001 From: Adam Buchbinder Date: Fri, 11 Dec 2009 16:35:37 -0500 Subject: Fix a grammar error (redundant "be") in comment Signed-off-by: Adam Buchbinder Signed-off-by: Jiri Kosina --- drivers/net/wireless/zd1211rw/zd_mac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/wireless/zd1211rw/zd_mac.c b/drivers/net/wireless/zd1211rw/zd_mac.c index f14deb0c8514..7a24802df2e1 100644 --- a/drivers/net/wireless/zd1211rw/zd_mac.c +++ b/drivers/net/wireless/zd1211rw/zd_mac.c @@ -374,7 +374,7 @@ static void zd_mac_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, * zd_mac_tx_failed - callback for failed frames * @dev: the mac80211 wireless device * - * This function is called if a frame couldn't be successfully be + * This function is called if a frame couldn't be successfully * transferred. The first frame from the tx queue, will be selected and * reported as error to the upper layers. */ -- cgit v1.2.3 From a089377f29d3af0f62f3bdc6db0c5042513fc3f3 Mon Sep 17 00:00:00 2001 From: Adam Buchbinder Date: Fri, 11 Dec 2009 16:35:38 -0500 Subject: Fix misspelling of "truly" in a label. A label reads 'truely_dead' rather than 'truly_dead'; this fixes it. No change in functionality. Signed-off-by: Adam Buchbinder Signed-off-by: Jiri Kosina --- drivers/net/typhoon.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/typhoon.c b/drivers/net/typhoon.c index 39f1fc650be6..d1a80685e3a7 100644 --- a/drivers/net/typhoon.c +++ b/drivers/net/typhoon.c @@ -2113,7 +2113,7 @@ typhoon_tx_timeout(struct net_device *dev) if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) { printk(KERN_WARNING "%s: could not reset in tx timeout\n", dev->name); - goto truely_dead; + goto truly_dead; } /* If we ever start using the Hi ring, it will need cleaning too */ @@ -2123,13 +2123,13 @@ typhoon_tx_timeout(struct net_device *dev) if(typhoon_start_runtime(tp) < 0) { printk(KERN_ERR "%s: could not start runtime in tx timeout\n", dev->name); - goto truely_dead; + goto truly_dead; } netif_wake_queue(dev); return; -truely_dead: +truly_dead: /* Reset the hardware, and turn off carrier to avoid more timeouts */ typhoon_reset(tp->ioaddr, NoWait); netif_carrier_off(dev); -- cgit v1.2.3 From c41b20e721ea4f6f20f66a66e7f0c3c97a2ca9c2 Mon Sep 17 00:00:00 2001 From: Adam Buchbinder Date: Fri, 11 Dec 2009 16:35:39 -0500 Subject: Fix misspellings of "truly" in comments. Some comments misspell "truly"; this fixes them. No code changes. Signed-off-by: Adam Buchbinder Signed-off-by: Jiri Kosina --- drivers/char/random.c | 2 +- drivers/gpu/drm/radeon/radeon_state.c | 2 +- drivers/net/cs89x0.c | 2 +- fs/dlm/member.c | 2 +- fs/namei.c | 2 +- include/math-emu/op-common.h | 2 +- kernel/trace/ring_buffer.c | 4 ++-- 7 files changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/char/random.c b/drivers/char/random.c index 2849713d2231..2fd3d39995d5 100644 --- a/drivers/char/random.c +++ b/drivers/char/random.c @@ -1191,7 +1191,7 @@ const struct file_operations urandom_fops = { void generate_random_uuid(unsigned char uuid_out[16]) { get_random_bytes(uuid_out, 16); - /* Set UUID version to 4 --- truely random generation */ + /* Set UUID version to 4 --- truly random generation */ uuid_out[6] = (uuid_out[6] & 0x0F) | 0x40; /* Set the UUID variant to DCE */ uuid_out[8] = (uuid_out[8] & 0x3F) | 0x80; diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c index 067167cb39ca..1982a87386a1 100644 --- a/drivers/gpu/drm/radeon/radeon_state.c +++ b/drivers/gpu/drm/radeon/radeon_state.c @@ -1065,7 +1065,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev, /* judging by the first tile offset needed, could possibly directly address/clear 4x4 tiles instead of 8x2 * 4x4 macro tiles, though would still need clear mask for - right/bottom if truely 4x4 granularity is desired ? */ + right/bottom if truly 4x4 granularity is desired ? */ OUT_RING(tileoffset * 16); /* the number of tiles to clear */ OUT_RING(nrtilesx + 1); diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c index 0e79cef95c0a..9b5bbc6ea2fa 100644 --- a/drivers/net/cs89x0.c +++ b/drivers/net/cs89x0.c @@ -580,7 +580,7 @@ cs89x0_probe1(struct net_device *dev, int ioaddr, int modular) } #ifdef CONFIG_SH_HICOSH4 - /* truely reset the chip */ + /* truly reset the chip */ writeword(ioaddr, ADD_PORT, 0x0114); writeword(ioaddr, DATA_PORT, 0x0040); #endif diff --git a/fs/dlm/member.c b/fs/dlm/member.c index 84f70bfb0baf..b12532e553f8 100644 --- a/fs/dlm/member.c +++ b/fs/dlm/member.c @@ -312,7 +312,7 @@ int dlm_ls_stop(struct dlm_ls *ls) /* * This in_recovery lock does two things: * 1) Keeps this function from returning until all threads are out - * of locking routines and locking is truely stopped. + * of locking routines and locking is truly stopped. * 2) Keeps any new requests from being processed until it's unlocked * when recovery is complete. */ diff --git a/fs/namei.c b/fs/namei.c index 94a5e60779f9..e05c243105a0 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -2556,7 +2556,7 @@ SYSCALL_DEFINE2(link, const char __user *, oldname, const char __user *, newname * e) conversion from fhandle to dentry may come in the wrong moment - when * we are removing the target. Solution: we will have to grab ->i_mutex * in the fhandle_to_dentry code. [FIXME - current nfsfh.c relies on - * ->i_mutex on parents, which works but leads to some truely excessive + * ->i_mutex on parents, which works but leads to some truly excessive * locking]. */ static int vfs_rename_dir(struct inode *old_dir, struct dentry *old_dentry, diff --git a/include/math-emu/op-common.h b/include/math-emu/op-common.h index f456534dcaf9..fd882261225e 100644 --- a/include/math-emu/op-common.h +++ b/include/math-emu/op-common.h @@ -29,7 +29,7 @@ _FP_FRAC_DECL_##wc(X) /* - * Finish truely unpacking a native fp value by classifying the kind + * Finish truly unpacking a native fp value by classifying the kind * of fp value and normalizing both the exponent and the fraction. */ diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index 8c1b2d290718..9ab578f1bb65 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -2541,7 +2541,7 @@ EXPORT_SYMBOL_GPL(ring_buffer_record_disable); * @buffer: The ring buffer to enable writes * * Note, multiple disables will need the same number of enables - * to truely enable the writing (much like preempt_disable). + * to truly enable the writing (much like preempt_disable). */ void ring_buffer_record_enable(struct ring_buffer *buffer) { @@ -2577,7 +2577,7 @@ EXPORT_SYMBOL_GPL(ring_buffer_record_disable_cpu); * @cpu: The CPU to enable. * * Note, multiple disables will need the same number of enables - * to truely enable the writing (much like preempt_disable). + * to truly enable the writing (much like preempt_disable). */ void ring_buffer_record_enable_cpu(struct ring_buffer *buffer, int cpu) { -- cgit v1.2.3 From edf86baae2e92bc03615086b2a341cd6d56c20f2 Mon Sep 17 00:00:00 2001 From: Adam Buchbinder Date: Fri, 11 Dec 2009 16:35:41 -0500 Subject: Fix misspellings of "separate" in strings. Some string messages misspell "separate"; this fixes them. No change in functionality. Signed-off-by: Adam Buchbinder Signed-off-by: Jiri Kosina --- drivers/acpi/proc.c | 2 +- drivers/isdn/mISDN/l1oip_core.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/acpi/proc.c b/drivers/acpi/proc.c index d0d25e2e1ced..1ac678d2c51c 100644 --- a/drivers/acpi/proc.c +++ b/drivers/acpi/proc.c @@ -435,7 +435,7 @@ acpi_system_write_wakeup_device(struct file *file, found_dev->wakeup.gpe_device)) { printk(KERN_WARNING "ACPI: '%s' and '%s' have the same GPE, " - "can't disable/enable one seperately\n", + "can't disable/enable one separately\n", dev->pnp.bus_id, found_dev->pnp.bus_id); dev->wakeup.state.enabled = found_dev->wakeup.state.enabled; diff --git a/drivers/isdn/mISDN/l1oip_core.c b/drivers/isdn/mISDN/l1oip_core.c index f1e8af54dff0..0843fcf8b381 100644 --- a/drivers/isdn/mISDN/l1oip_core.c +++ b/drivers/isdn/mISDN/l1oip_core.c @@ -1509,7 +1509,7 @@ l1oip_init(void) printk(KERN_DEBUG "%s: interface %d is %s with %s.\n", __func__, l1oip_cnt, pri ? "PRI" : "BRI", bundle ? "bundled IP packet for all B-channels" : - "seperate IP packets for every B-channel"); + "separate IP packets for every B-channel"); hc = kzalloc(sizeof(struct l1oip), GFP_ATOMIC); if (!hc) { -- cgit v1.2.3 From 640462cbd659990bcceaf86ab17ccbc02147e62a Mon Sep 17 00:00:00 2001 From: Rudy Matela Date: Wed, 9 Dec 2009 11:35:40 -0300 Subject: Coding style correction of some wan drivers Added a space separating some if/switch/while keywords from the following parenthesis to conform to the CodingStyle. Signed-off-by: Rudy Matela Acked-by: Krzysztof Halasa Signed-off-by: Jiri Kosina --- drivers/net/wan/cosa.c | 10 +++++----- drivers/net/wan/hdlc_cisco.c | 8 ++++---- drivers/net/wan/hdlc_x25.c | 4 ++-- 3 files changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wan/cosa.c b/drivers/net/wan/cosa.c index b36bf96eb502..f0bd70fb650c 100644 --- a/drivers/net/wan/cosa.c +++ b/drivers/net/wan/cosa.c @@ -811,7 +811,7 @@ static ssize_t cosa_read(struct file *file, cosa_enable_rx(chan); spin_lock_irqsave(&cosa->lock, flags); add_wait_queue(&chan->rxwaitq, &wait); - while(!chan->rx_status) { + while (!chan->rx_status) { current->state = TASK_INTERRUPTIBLE; spin_unlock_irqrestore(&cosa->lock, flags); schedule(); @@ -896,7 +896,7 @@ static ssize_t cosa_write(struct file *file, spin_lock_irqsave(&cosa->lock, flags); add_wait_queue(&chan->txwaitq, &wait); - while(!chan->tx_status) { + while (!chan->tx_status) { current->state = TASK_INTERRUPTIBLE; spin_unlock_irqrestore(&cosa->lock, flags); schedule(); @@ -1153,7 +1153,7 @@ static int cosa_ioctl_common(struct cosa_data *cosa, struct channel_data *channel, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; - switch(cmd) { + switch (cmd) { case COSAIORSET: /* Reset the device */ if (!capable(CAP_NET_ADMIN)) return -EACCES; @@ -1704,7 +1704,7 @@ static inline void tx_interrupt(struct cosa_data *cosa, int status) spin_unlock_irqrestore(&cosa->lock, flags); return; } - while(1) { + while (1) { cosa->txchan++; i++; if (cosa->txchan >= cosa->nchannels) @@ -2010,7 +2010,7 @@ again: static void debug_status_in(struct cosa_data *cosa, int status) { char *s; - switch(status & SR_CMD_FROM_SRP_MASK) { + switch (status & SR_CMD_FROM_SRP_MASK) { case SR_UP_REQUEST: s = "RX_REQ"; break; diff --git a/drivers/net/wan/hdlc_cisco.c b/drivers/net/wan/hdlc_cisco.c index f1bff98acd1f..1ceccf1ca6c7 100644 --- a/drivers/net/wan/hdlc_cisco.c +++ b/drivers/net/wan/hdlc_cisco.c @@ -141,7 +141,7 @@ static __be16 cisco_type_trans(struct sk_buff *skb, struct net_device *dev) data->address != CISCO_UNICAST) return cpu_to_be16(ETH_P_HDLC); - switch(data->protocol) { + switch (data->protocol) { case cpu_to_be16(ETH_P_IP): case cpu_to_be16(ETH_P_IPX): case cpu_to_be16(ETH_P_IPV6): @@ -190,7 +190,7 @@ static int cisco_rx(struct sk_buff *skb) cisco_data = (struct cisco_packet*)(skb->data + sizeof (struct hdlc_header)); - switch(ntohl (cisco_data->type)) { + switch (ntohl (cisco_data->type)) { case CISCO_ADDR_REQ: /* Stolen from syncppp.c :-) */ in_dev = dev->ip_ptr; addr = 0; @@ -245,8 +245,8 @@ static int cisco_rx(struct sk_buff *skb) dev_kfree_skb_any(skb); return NET_RX_SUCCESS; - } /* switch(keepalive type) */ - } /* switch(protocol) */ + } /* switch (keepalive type) */ + } /* switch (protocol) */ printk(KERN_INFO "%s: Unsupported protocol %x\n", dev->name, ntohs(data->protocol)); diff --git a/drivers/net/wan/hdlc_x25.c b/drivers/net/wan/hdlc_x25.c index aa9248f8eb1a..6e1ca256effd 100644 --- a/drivers/net/wan/hdlc_x25.c +++ b/drivers/net/wan/hdlc_x25.c @@ -202,10 +202,10 @@ static int x25_ioctl(struct net_device *dev, struct ifreq *ifr) return 0; /* return protocol only, no settable parameters */ case IF_PROTO_X25: - if(!capable(CAP_NET_ADMIN)) + if (!capable(CAP_NET_ADMIN)) return -EPERM; - if(dev->flags & IFF_UP) + if (dev->flags & IFF_UP) return -EBUSY; result=hdlc->attach(dev, ENCODING_NRZ,PARITY_CRC16_PR1_CCITT); -- cgit v1.2.3 From ba593e5966440deec8684863e0cba9b502c4a377 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 4 Feb 2010 14:40:59 +0100 Subject: fsl_mx3_udc: Add i.MX35 support The i.MX35 works fine with this driver, but we do not have the usb_ahb clock. Signed-off-by: Sascha Hauer Cc: Guennadi Liakhovetski --- drivers/usb/gadget/fsl_mx3_udc.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/fsl_mx3_udc.c b/drivers/usb/gadget/fsl_mx3_udc.c index 4bc2bf3d602e..20a802ecaa15 100644 --- a/drivers/usb/gadget/fsl_mx3_udc.c +++ b/drivers/usb/gadget/fsl_mx3_udc.c @@ -17,6 +17,8 @@ #include #include +#include + static struct clk *mxc_ahb_clk; static struct clk *mxc_usb_clk; @@ -28,14 +30,16 @@ int fsl_udc_clk_init(struct platform_device *pdev) pdata = pdev->dev.platform_data; - mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb"); - if (IS_ERR(mxc_ahb_clk)) - return PTR_ERR(mxc_ahb_clk); + if (!cpu_is_mx35()) { + mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb"); + if (IS_ERR(mxc_ahb_clk)) + return PTR_ERR(mxc_ahb_clk); - ret = clk_enable(mxc_ahb_clk); - if (ret < 0) { - dev_err(&pdev->dev, "clk_enable(\"usb_ahb\") failed\n"); - goto eenahb; + ret = clk_enable(mxc_ahb_clk); + if (ret < 0) { + dev_err(&pdev->dev, "clk_enable(\"usb_ahb\") failed\n"); + goto eenahb; + } } /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */ @@ -50,6 +54,7 @@ int fsl_udc_clk_init(struct platform_device *pdev) if (pdata->phy_mode != FSL_USB2_PHY_ULPI && (freq < 59999000 || freq > 60001000)) { dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq); + ret = -EINVAL; goto eclkrate; } @@ -66,9 +71,11 @@ eclkrate: clk_put(mxc_usb_clk); mxc_usb_clk = NULL; egusb: - clk_disable(mxc_ahb_clk); + if (!cpu_is_mx35()) + clk_disable(mxc_ahb_clk); eenahb: - clk_put(mxc_ahb_clk); + if (!cpu_is_mx35()) + clk_put(mxc_ahb_clk); return ret; } @@ -90,6 +97,8 @@ void fsl_udc_clk_release(void) clk_disable(mxc_usb_clk); clk_put(mxc_usb_clk); } - clk_disable(mxc_ahb_clk); - clk_put(mxc_ahb_clk); + if (!cpu_is_mx35()) { + clk_disable(mxc_ahb_clk); + clk_put(mxc_ahb_clk); + } } -- cgit v1.2.3 From 5a6f98f5bff7f975c61d56b5c756b5a96c4db167 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 22 Dec 2009 15:04:48 -0500 Subject: drm/radeon/kms: add radeon i2c algo Currently just a wrapper around bit algo Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_combios.c | 40 ++++++------- drivers/gpu/drm/radeon/radeon_connectors.c | 14 +---- drivers/gpu/drm/radeon/radeon_display.c | 4 -- drivers/gpu/drm/radeon/radeon_i2c.c | 91 ++++++++++++++++++++++-------- drivers/gpu/drm/radeon/radeon_mode.h | 25 ++++---- 5 files changed, 102 insertions(+), 72 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index e7b19440102e..318afe83e6b0 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -2289,23 +2289,21 @@ void radeon_external_tmds_setup(struct drm_encoder *encoder) switch (tmds->dvo_chip) { case DVO_SIL164: /* sil 164 */ - radeon_i2c_do_lock(tmds->i2c_bus, 1); - radeon_i2c_sw_put_byte(tmds->i2c_bus, - tmds->slave_addr, - 0x08, 0x30); - radeon_i2c_sw_put_byte(tmds->i2c_bus, + radeon_i2c_put_byte(tmds->i2c_bus, + tmds->slave_addr, + 0x08, 0x30); + radeon_i2c_put_byte(tmds->i2c_bus, tmds->slave_addr, 0x09, 0x00); - radeon_i2c_sw_put_byte(tmds->i2c_bus, - tmds->slave_addr, - 0x0a, 0x90); - radeon_i2c_sw_put_byte(tmds->i2c_bus, - tmds->slave_addr, - 0x0c, 0x89); - radeon_i2c_sw_put_byte(tmds->i2c_bus, + radeon_i2c_put_byte(tmds->i2c_bus, + tmds->slave_addr, + 0x0a, 0x90); + radeon_i2c_put_byte(tmds->i2c_bus, + tmds->slave_addr, + 0x0c, 0x89); + radeon_i2c_put_byte(tmds->i2c_bus, tmds->slave_addr, 0x08, 0x3b); - radeon_i2c_do_lock(tmds->i2c_bus, 0); break; case DVO_SIL1178: /* sil 1178 - untested */ @@ -2390,11 +2388,9 @@ bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) index++; val = RBIOS8(index); index++; - radeon_i2c_do_lock(tmds->i2c_bus, 1); - radeon_i2c_sw_put_byte(tmds->i2c_bus, - slave_addr, - reg, val); - radeon_i2c_do_lock(tmds->i2c_bus, 0); + radeon_i2c_put_byte(tmds->i2c_bus, + slave_addr, + reg, val); break; default: DRM_ERROR("Unknown id %d\n", id >> 13); @@ -2447,11 +2443,9 @@ bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) reg = id & 0x1fff; val = RBIOS8(index); index += 1; - radeon_i2c_do_lock(tmds->i2c_bus, 1); - radeon_i2c_sw_put_byte(tmds->i2c_bus, - tmds->slave_addr, - reg, val); - radeon_i2c_do_lock(tmds->i2c_bus, 0); + radeon_i2c_put_byte(tmds->i2c_bus, + tmds->slave_addr, + reg, val); break; default: DRM_ERROR("Unknown id %d\n", id >> 13); diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index 2d8e5a70f284..6e9e7b59d67e 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c @@ -479,10 +479,8 @@ static enum drm_connector_status radeon_lvds_detect(struct drm_connector *connec ret = connector_status_connected; else { if (radeon_connector->ddc_bus) { - radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); - radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); if (radeon_connector->edid) ret = connector_status_connected; } @@ -587,17 +585,13 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect if (!encoder) ret = connector_status_disconnected; - radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); dret = radeon_ddc_probe(radeon_connector); - radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); if (dret) { if (radeon_connector->edid) { kfree(radeon_connector->edid); radeon_connector->edid = NULL; } - radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); - radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); if (!radeon_connector->edid) { DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", @@ -742,17 +736,13 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect enum drm_connector_status ret = connector_status_disconnected; bool dret; - radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); dret = radeon_ddc_probe(radeon_connector); - radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); if (dret) { if (radeon_connector->edid) { kfree(radeon_connector->edid); radeon_connector->edid = NULL; } - radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); - radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); if (!radeon_connector->edid) { DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", @@ -948,7 +938,7 @@ static void radeon_dp_connector_destroy(struct drm_connector *connector) if (radeon_connector->edid) kfree(radeon_connector->edid); if (radeon_dig_connector->dp_i2c_bus) - radeon_i2c_destroy(radeon_dig_connector->dp_i2c_bus); + radeon_i2c_destroy_dp(radeon_dig_connector->dp_i2c_bus); kfree(radeon_connector->con_priv); drm_sysfs_connector_remove(connector); drm_connector_cleanup(connector); @@ -984,12 +974,10 @@ static enum drm_connector_status radeon_dp_detect(struct drm_connector *connecto ret = connector_status_connected; } } else { - radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); if (radeon_ddc_probe(radeon_connector)) { radeon_dig_connector->dp_sink_type = sink_type; ret = connector_status_connected; } - radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); } return ret; diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 6a92f994cc26..ec3166bfaa49 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -364,9 +364,7 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) if (!radeon_connector->ddc_bus) return -1; if (!radeon_connector->edid) { - radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); - radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); } if (radeon_connector->edid) { @@ -386,9 +384,7 @@ static int radeon_ddc_dump(struct drm_connector *connector) if (!radeon_connector->ddc_bus) return -1; - radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); - radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); if (edid) { kfree(edid); } diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c index da3da1e89d00..75b090f60208 100644 --- a/drivers/gpu/drm/radeon/radeon_i2c.c +++ b/drivers/gpu/drm/radeon/radeon_i2c.c @@ -59,7 +59,7 @@ bool radeon_ddc_probe(struct radeon_connector *radeon_connector) } -void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) +static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) { struct radeon_device *rdev = i2c->dev->dev_private; struct radeon_i2c_bus_rec *rec = &i2c->rec; @@ -168,6 +168,32 @@ static void set_data(void *i2c_priv, int data) WREG32(rec->en_data_reg, val); } +static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg *msgs, int num) +{ + struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); + int ret; + + radeon_i2c_do_lock(i2c, 1); + if (i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num) == num) + ret = num; + else + ret = -1; + radeon_i2c_do_lock(i2c, 0); + + return ret; +} + +static u32 radeon_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm radeon_i2c_algo = { + .master_xfer = radeon_i2c_xfer, + .functionality = radeon_i2c_func, +}; + struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, struct radeon_i2c_bus_rec *rec, const char *name) @@ -179,21 +205,34 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, if (i2c == NULL) return NULL; - i2c->adapter.owner = THIS_MODULE; i2c->dev = dev; - i2c_set_adapdata(&i2c->adapter, i2c); - i2c->adapter.algo_data = &i2c->algo.bit; - i2c->algo.bit.setsda = set_data; - i2c->algo.bit.setscl = set_clock; - i2c->algo.bit.getsda = get_data; - i2c->algo.bit.getscl = get_clock; - i2c->algo.bit.udelay = 20; + i2c->rec = *rec; + /* set the internal bit adapter */ + i2c->algo.radeon.bit_adapter.owner = THIS_MODULE; + i2c_set_adapdata(&i2c->algo.radeon.bit_adapter, i2c); + sprintf(i2c->algo.radeon.bit_adapter.name, "Radeon internal i2c bit bus %s", name); + i2c->algo.radeon.bit_adapter.algo_data = &i2c->algo.radeon.bit_data; + i2c->algo.radeon.bit_data.setsda = set_data; + i2c->algo.radeon.bit_data.setscl = set_clock; + i2c->algo.radeon.bit_data.getsda = get_data; + i2c->algo.radeon.bit_data.getscl = get_clock; + i2c->algo.radeon.bit_data.udelay = 20; /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always * make this, 2 jiffies is a lot more reliable */ - i2c->algo.bit.timeout = 2; - i2c->algo.bit.data = i2c; - i2c->rec = *rec; - ret = i2c_bit_add_bus(&i2c->adapter); + i2c->algo.radeon.bit_data.timeout = 2; + i2c->algo.radeon.bit_data.data = i2c; + ret = i2c_bit_add_bus(&i2c->algo.radeon.bit_adapter); + if (ret) { + DRM_INFO("Failed to register internal bit i2c %s\n", name); + goto out_free; + } + /* set the radeon i2c adapter */ + i2c->adapter.owner = THIS_MODULE; + i2c_set_adapdata(&i2c->adapter, i2c); + sprintf(i2c->adapter.name, "Radeon i2c %s", name); + i2c->adapter.algo_data = &i2c->algo.radeon; + i2c->adapter.algo = &radeon_i2c_algo; + ret = i2c_add_adapter(&i2c->adapter); if (ret) { DRM_INFO("Failed to register i2c %s\n", name); goto out_free; @@ -237,8 +276,16 @@ out_free: } - void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) +{ + if (!i2c) + return; + i2c_del_adapter(&i2c->algo.radeon.bit_adapter); + i2c_del_adapter(&i2c->adapter); + kfree(i2c); +} + +void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c) { if (!i2c) return; @@ -252,10 +299,10 @@ struct drm_encoder *radeon_best_encoder(struct drm_connector *connector) return NULL; } -void radeon_i2c_sw_get_byte(struct radeon_i2c_chan *i2c_bus, - u8 slave_addr, - u8 addr, - u8 *val) +void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, + u8 slave_addr, + u8 addr, + u8 *val) { u8 out_buf[2]; u8 in_buf[2]; @@ -286,10 +333,10 @@ void radeon_i2c_sw_get_byte(struct radeon_i2c_chan *i2c_bus, } } -void radeon_i2c_sw_put_byte(struct radeon_i2c_chan *i2c_bus, - u8 slave_addr, - u8 addr, - u8 val) +void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, + u8 slave_addr, + u8 addr, + u8 val) { uint8_t out_buf[2]; struct i2c_msg msg = { diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index e81b2aeb6a8f..b884bacf09ff 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -159,12 +159,17 @@ struct radeon_pll { uint32_t id; }; +struct i2c_algo_radeon_data { + struct i2c_adapter bit_adapter; + struct i2c_algo_bit_data bit_data; +}; + struct radeon_i2c_chan { struct i2c_adapter adapter; struct drm_device *dev; union { struct i2c_algo_dp_aux_data dp; - struct i2c_algo_bit_data bit; + struct i2c_algo_radeon_data radeon; } algo; struct radeon_i2c_bus_rec rec; }; @@ -411,14 +416,15 @@ extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, struct radeon_i2c_bus_rec *rec, const char *name); extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); -extern void radeon_i2c_sw_get_byte(struct radeon_i2c_chan *i2c_bus, - u8 slave_addr, - u8 addr, - u8 *val); -extern void radeon_i2c_sw_put_byte(struct radeon_i2c_chan *i2c, - u8 slave_addr, - u8 addr, - u8 val); +extern void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c); +extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, + u8 slave_addr, + u8 addr, + u8 *val); +extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, + u8 slave_addr, + u8 addr, + u8 val); extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); @@ -531,7 +537,6 @@ void radeon_atombios_init_crtc(struct drm_device *dev, struct radeon_crtc *radeon_crtc); void radeon_legacy_init_crtc(struct drm_device *dev, struct radeon_crtc *radeon_crtc); -extern void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state); void radeon_get_clock_info(struct drm_device *dev); -- cgit v1.2.3 From c9404c9c392d557a4687c4cbda022b03cb787ce9 Mon Sep 17 00:00:00 2001 From: Adam Buchbinder Date: Fri, 18 Dec 2009 15:40:42 -0500 Subject: Fix misspelling of "should" and "shouldn't" in comments. Some comments misspell "should" or "shouldn't"; this fixes them. No code changes. Signed-off-by: Adam Buchbinder Signed-off-by: Jiri Kosina --- arch/x86/kernel/ptrace.c | 2 +- drivers/ata/libata-core.c | 2 +- drivers/gpu/drm/radeon/atombios.h | 2 +- drivers/ieee1394/pcilynx.c | 2 +- drivers/input/tablet/aiptek.c | 2 +- drivers/mmc/card/sdio_uart.c | 2 +- drivers/scsi/lpfc/lpfc_scsi.c | 4 ++-- drivers/video/sstfb.c | 2 +- fs/locks.c | 2 +- kernel/audit.c | 2 +- mm/slub.c | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c index 017d937639fe..118428085ea2 100644 --- a/arch/x86/kernel/ptrace.c +++ b/arch/x86/kernel/ptrace.c @@ -604,7 +604,7 @@ ptrace_modify_breakpoint(struct perf_event *bp, int len, int type, struct perf_event_attr attr; /* - * We shoud have at least an inactive breakpoint at this + * We should have at least an inactive breakpoint at this * slot. It means the user is writing dr7 without having * written the address register first */ diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 6728328f3bea..698ef474767e 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -2232,7 +2232,7 @@ retry: * Some drives were very specific about that exact sequence. * * Note that ATA4 says lba is mandatory so the second check - * shoud never trigger. + * should never trigger. */ if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) { err_mask = ata_dev_init_params(dev, id[3], id[6]); diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h index 91ad0d1c1b17..2a88029f6a1e 100644 --- a/drivers/gpu/drm/radeon/atombios.h +++ b/drivers/gpu/drm/radeon/atombios.h @@ -2275,7 +2275,7 @@ typedef struct _ATOM_LCD_RTS_RECORD { UCHAR ucRTSValue; } ATOM_LCD_RTS_RECORD; -/* !! If the record below exits, it shoud always be the first record for easy use in command table!!! */ +/* !! If the record below exits, it should always be the first record for easy use in command table!!! */ typedef struct _ATOM_LCD_MODE_CONTROL_CAP { UCHAR ucRecordType; USHORT usLCDCap; diff --git a/drivers/ieee1394/pcilynx.c b/drivers/ieee1394/pcilynx.c index 9555fd253865..bf47fee79808 100644 --- a/drivers/ieee1394/pcilynx.c +++ b/drivers/ieee1394/pcilynx.c @@ -1452,7 +1452,7 @@ static int __devinit add_card(struct pci_dev *dev, PRINT(KERN_ERR, lynx->id, "unable to read bus info block from i2c"); } else { PRINT(KERN_INFO, lynx->id, "got bus info block from serial eeprom"); - /* FIXME: probably we shoud rewrite the max_rec, max_ROM(1394a), + /* FIXME: probably we should rewrite the max_rec, max_ROM(1394a), * generation(1394a) and link_spd(1394a) field and recalculate * the CRC */ diff --git a/drivers/input/tablet/aiptek.c b/drivers/input/tablet/aiptek.c index 7d005a3616d7..4be039d7dcad 100644 --- a/drivers/input/tablet/aiptek.c +++ b/drivers/input/tablet/aiptek.c @@ -362,7 +362,7 @@ static const int macroKeyEvents[] = { }; /*********************************************************************** - * Map values to strings and back. Every map shoudl have the following + * Map values to strings and back. Every map should have the following * as its last element: { NULL, AIPTEK_INVALID_VALUE }. */ #define AIPTEK_INVALID_VALUE -1 diff --git a/drivers/mmc/card/sdio_uart.c b/drivers/mmc/card/sdio_uart.c index f53755533e7e..a4e37758be41 100644 --- a/drivers/mmc/card/sdio_uart.c +++ b/drivers/mmc/card/sdio_uart.c @@ -581,7 +581,7 @@ static int uart_carrier_raised(struct tty_port *tport) struct sdio_uart_port *port = container_of(tport, struct sdio_uart_port, port); unsigned int ret = sdio_uart_claim_func(port); - if (ret) /* Missing hardware shoudn't block for carrier */ + if (ret) /* Missing hardware shouldn't block for carrier */ return 1; ret = sdio_uart_get_mctrl(port); sdio_uart_release_func(port); diff --git a/drivers/scsi/lpfc/lpfc_scsi.c b/drivers/scsi/lpfc/lpfc_scsi.c index a246410ce9df..28c6bfd3e82e 100644 --- a/drivers/scsi/lpfc/lpfc_scsi.c +++ b/drivers/scsi/lpfc/lpfc_scsi.c @@ -1574,7 +1574,7 @@ lpfc_bg_scsi_prep_dma_buf(struct lpfc_hba *phba, case LPFC_PG_TYPE_NO_DIF: num_bde = lpfc_bg_setup_bpl(phba, scsi_cmnd, bpl, datasegcnt); - /* we shoud have 2 or more entries in buffer list */ + /* we should have 2 or more entries in buffer list */ if (num_bde < 2) goto err; break; @@ -1611,7 +1611,7 @@ lpfc_bg_scsi_prep_dma_buf(struct lpfc_hba *phba, num_bde = lpfc_bg_setup_bpl_prot(phba, scsi_cmnd, bpl, datasegcnt, protsegcnt); - /* we shoud have 3 or more entries in buffer list */ + /* we should have 3 or more entries in buffer list */ if (num_bde < 3) goto err; break; diff --git a/drivers/video/sstfb.c b/drivers/video/sstfb.c index 609d0a521ca2..79840f11fecb 100644 --- a/drivers/video/sstfb.c +++ b/drivers/video/sstfb.c @@ -1102,7 +1102,7 @@ static void sst_set_vidmod_ics(struct fb_info *info, const int bpp) * detect dac type * prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset, * dram refresh disabled, FbiInit remaped. - * TODO: mmh.. maybe i shoud put the "prerequisite" in the func ... + * TODO: mmh.. maybe i should put the "prerequisite" in the func ... */ diff --git a/fs/locks.c b/fs/locks.c index a8794f233bc9..cde572db112f 100644 --- a/fs/locks.c +++ b/fs/locks.c @@ -1454,7 +1454,7 @@ EXPORT_SYMBOL(generic_setlease); * leases held by processes on this node. * * There is also no break_lease method; filesystems that - * handle their own leases shoud break leases themselves from the + * handle their own leases should break leases themselves from the * filesystem's open, create, and (on truncate) setattr methods. * * Warning: the only current setlease methods exist only to disable diff --git a/kernel/audit.c b/kernel/audit.c index 5feed232be9d..78f7f86aa238 100644 --- a/kernel/audit.c +++ b/kernel/audit.c @@ -398,7 +398,7 @@ static void kauditd_send_skb(struct sk_buff *skb) skb_get(skb); err = netlink_unicast(audit_sock, skb, audit_nlk_pid, 0); if (err < 0) { - BUG_ON(err != -ECONNREFUSED); /* Shoudn't happen */ + BUG_ON(err != -ECONNREFUSED); /* Shouldn't happen */ printk(KERN_ERR "audit: *NO* daemon at audit_pid=%d\n", audit_pid); audit_log_lost("auditd dissapeared\n"); audit_pid = 0; diff --git a/mm/slub.c b/mm/slub.c index 8d71aaf888d7..00e0961b11fe 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -3086,7 +3086,7 @@ static void slab_mem_offline_callback(void *arg) /* * if n->nr_slabs > 0, slabs still exist on the node * that is going down. We were unable to free them, - * and offline_pages() function shoudn't call this + * and offline_pages() function shouldn't call this * callback. So, we must fail. */ BUG_ON(slabs_node(s, offline_node)); -- cgit v1.2.3 From 473a72a18bf446f51837f7731214db297981f0ed Mon Sep 17 00:00:00 2001 From: Peter Huewe Date: Tue, 22 Dec 2009 09:27:05 +0100 Subject: uwb/i1480: add __init/__exit macros Trivial patch which adds the __init/__exit macros to the module_init/ module_exit functions of uwb/i1480/i1480-est.c Signed-off-by: Peter Huewe Acked-by: David Vrabel Signed-off-by: Jiri Kosina --- drivers/uwb/i1480/i1480-est.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/uwb/i1480/i1480-est.c b/drivers/uwb/i1480/i1480-est.c index 7bf8c6febae7..f2eb4d8b76c9 100644 --- a/drivers/uwb/i1480/i1480-est.c +++ b/drivers/uwb/i1480/i1480-est.c @@ -54,7 +54,7 @@ static struct uwb_est_entry i1480_est_fd01[] = { .size = sizeof(struct i1480_rceb) + 2 }, }; -static int i1480_est_init(void) +static int __init i1480_est_init(void) { int result = uwb_est_register(i1480_CET_VS1, 0x00, 0x8086, 0x0c3b, i1480_est_fd00, @@ -73,7 +73,7 @@ static int i1480_est_init(void) } module_init(i1480_est_init); -static void i1480_est_exit(void) +static void __exit i1480_est_exit(void) { uwb_est_unregister(i1480_CET_VS1, 0x00, 0x8086, 0x0c3b, i1480_est_fd00, ARRAY_SIZE(i1480_est_fd00)); -- cgit v1.2.3 From 8885074038b219b90cb0f5cd1a049ba80c7e815b Mon Sep 17 00:00:00 2001 From: Peter Huewe Date: Tue, 22 Dec 2009 09:27:06 +0100 Subject: isdn/hardware: add __init/__exit macros to mISDNisar.c Trivial patch which adds the __init/__exit macros to the module_init/ module_exit functions of drivers/isdn/hardware/mISDN/mISDNisar.c Signed-off-by: Peter Huewe Signed-off-by: Jiri Kosina --- drivers/isdn/hardware/mISDN/mISDNisar.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/isdn/hardware/mISDN/mISDNisar.c b/drivers/isdn/hardware/mISDN/mISDNisar.c index 09095c747110..f0bc6fa95809 100644 --- a/drivers/isdn/hardware/mISDN/mISDNisar.c +++ b/drivers/isdn/hardware/mISDN/mISDNisar.c @@ -1712,13 +1712,13 @@ mISDNisar_init(struct isar_hw *isar, void *hw) } EXPORT_SYMBOL(mISDNisar_init); -static int isar_mod_init(void) +static int __init isar_mod_init(void) { pr_notice("mISDN: ISAR driver Rev. %s\n", ISAR_REV); return 0; } -static void isar_mod_cleanup(void) +static void __exit isar_mod_cleanup(void) { pr_notice("mISDN: ISAR module unloaded\n"); } -- cgit v1.2.3 From 73a98fce881c46eaeb33c1aef23ab607f4d03344 Mon Sep 17 00:00:00 2001 From: Peter Huewe Date: Tue, 22 Dec 2009 09:38:02 +0100 Subject: w1: add __init/__exit macros to w1.c Trivial patch which adds the __init/__exit macros to the module_init/ module_exit functions of drivers/w1/w1.c Signed-off-by: Peter Huewe Signed-off-by: Jiri Kosina --- drivers/w1/w1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/w1/w1.c b/drivers/w1/w1.c index acc7e3b7fe17..ad5897dc4495 100644 --- a/drivers/w1/w1.c +++ b/drivers/w1/w1.c @@ -986,7 +986,7 @@ int w1_process(void *data) return 0; } -static int w1_init(void) +static int __init w1_init(void) { int retval; @@ -1034,7 +1034,7 @@ err_out_exit_init: return retval; } -static void w1_fini(void) +static void __exit w1_fini(void) { struct w1_master *dev; -- cgit v1.2.3 From 60c14a1507a9fcd2e3b8eb53c218cb74ae404bcf Mon Sep 17 00:00:00 2001 From: Peter Huewe Date: Tue, 22 Dec 2009 09:38:14 +0100 Subject: media/dvb: add __init/__exit macros to bt878.c Trivial patch which adds the __init/__exit macros to the module_init/ module_exit functions of drivers/media/dvb/bt8xx/bt878.c Signed-off-by: Peter Huewe Acked-by: Jean Delvare Signed-off-by: Jiri Kosina --- drivers/media/dvb/bt8xx/bt878.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/media/dvb/bt8xx/bt878.c b/drivers/media/dvb/bt8xx/bt878.c index a24c125331f0..2a0886ad787f 100644 --- a/drivers/media/dvb/bt8xx/bt878.c +++ b/drivers/media/dvb/bt8xx/bt878.c @@ -582,7 +582,7 @@ static int bt878_pci_driver_registered; /* Module management functions */ /*******************************/ -static int bt878_init_module(void) +static int __init bt878_init_module(void) { bt878_num = 0; bt878_pci_driver_registered = 0; @@ -600,7 +600,7 @@ static int bt878_init_module(void) return pci_register_driver(&bt878_pci_driver); } -static void bt878_cleanup_module(void) +static void __exit bt878_cleanup_module(void) { if (bt878_pci_driver_registered) { bt878_pci_driver_registered = 0; -- cgit v1.2.3 From 3d956d1dfffef3b19d743aa1a443ab5a300051cb Mon Sep 17 00:00:00 2001 From: Peter Huewe Date: Tue, 22 Dec 2009 09:41:42 +0100 Subject: isdn/mISDN: add __init/__exit macros to dsp_core.c Trivial patch which adds the __init/__exit macros to the module_init/ module_exit functions of drivers/isdn/mISDN/dsp_core.c Signed-off-by: Peter Huewe Signed-off-by: Jiri Kosina --- drivers/isdn/mISDN/dsp_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/isdn/mISDN/dsp_core.c b/drivers/isdn/mISDN/dsp_core.c index 43ff4d3b046e..6eac588e0a37 100644 --- a/drivers/isdn/mISDN/dsp_core.c +++ b/drivers/isdn/mISDN/dsp_core.c @@ -1114,7 +1114,7 @@ static struct Bprotocol DSP = { .create = dspcreate }; -static int dsp_init(void) +static int __init dsp_init(void) { int err; int tics; @@ -1212,7 +1212,7 @@ static int dsp_init(void) } -static void dsp_cleanup(void) +static void __exit dsp_cleanup(void) { mISDN_unregister_Bprotocol(&DSP); -- cgit v1.2.3 From 947af2943576400628bba085eaa6b85143526133 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Thu, 7 Jan 2010 00:03:52 +0100 Subject: Fix spelling of 'platform' in comments and doc Replace platfrom -> platform. This is a frequent spelling bug. Signed-off-by: Stefan Weil Signed-off-by: Jiri Kosina --- Documentation/driver-model/platform.txt | 2 +- arch/arm/mach-davinci/include/mach/i2c.h | 2 +- arch/arm/mach-s3c2410/include/mach/spi-gpio.h | 2 +- arch/arm/plat-s3c/include/plat/nand.h | 2 +- arch/blackfin/include/asm/nand.h | 4 ++-- arch/powerpc/kernel/legacy_serial.c | 2 +- drivers/mtd/maps/plat-ram.c | 2 +- drivers/net/cxgb3/sge.c | 4 ++-- drivers/video/mbx/mbxfb.c | 2 +- include/linux/dm9000.h | 2 +- 10 files changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/Documentation/driver-model/platform.txt b/Documentation/driver-model/platform.txt index 2e2c2ea90ceb..41f41632ee55 100644 --- a/Documentation/driver-model/platform.txt +++ b/Documentation/driver-model/platform.txt @@ -192,7 +192,7 @@ command line. This will execute all matching early_param() callbacks. User specified early platform devices will be registered at this point. For the early serial console case the user can specify port on the kernel command line as "earlyprintk=serial.0" where "earlyprintk" is -the class string, "serial" is the name of the platfrom driver and +the class string, "serial" is the name of the platform driver and 0 is the platform device id. If the id is -1 then the dot and the id can be omitted. diff --git a/arch/arm/mach-davinci/include/mach/i2c.h b/arch/arm/mach-davinci/include/mach/i2c.h index c248e9b7e825..44bdea13cc8c 100644 --- a/arch/arm/mach-davinci/include/mach/i2c.h +++ b/arch/arm/mach-davinci/include/mach/i2c.h @@ -1,5 +1,5 @@ /* - * DaVinci I2C controller platfrom_device info + * DaVinci I2C controller platform_device info * * Author: Vladimir Barinov, MontaVista Software, Inc. * diff --git a/arch/arm/mach-s3c2410/include/mach/spi-gpio.h b/arch/arm/mach-s3c2410/include/mach/spi-gpio.h index 980a099e209c..dcef2287cb38 100644 --- a/arch/arm/mach-s3c2410/include/mach/spi-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/spi-gpio.h @@ -3,7 +3,7 @@ * Copyright (c) 2006 Simtec Electronics * Ben Dooks * - * S3C2410 - SPI Controller platfrom_device info + * S3C2410 - SPI Controller platform_device info * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h index 226147b7e026..b64115fa93a4 100644 --- a/arch/arm/plat-s3c/include/plat/nand.h +++ b/arch/arm/plat-s3c/include/plat/nand.h @@ -3,7 +3,7 @@ * Copyright (c) 2004 Simtec Electronics * Ben Dooks * - * S3C2410 - NAND device controller platfrom_device info + * S3C2410 - NAND device controller platform_device info * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/blackfin/include/asm/nand.h b/arch/blackfin/include/asm/nand.h index 3ae8b569edfc..3a1e79dfc8d9 100644 --- a/arch/blackfin/include/asm/nand.h +++ b/arch/blackfin/include/asm/nand.h @@ -1,5 +1,5 @@ /* - * BF5XX - NAND flash controller platfrom_device info + * BF5XX - NAND flash controller platform_device info * * Copyright 2007-2008 Analog Devices, Inc. * @@ -8,7 +8,7 @@ /* struct bf5xx_nand_platform * - * define a interface between platfrom board specific code and + * define a interface between platform board specific code and * bf54x NFC driver. * * nr_partitions = number of partitions pointed to be partitoons (or zero) diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/kernel/legacy_serial.c index 9ddfaef1a184..035ada5443ee 100644 --- a/arch/powerpc/kernel/legacy_serial.c +++ b/arch/powerpc/kernel/legacy_serial.c @@ -469,7 +469,7 @@ static int __init serial_dev_init(void) return -ENODEV; /* - * Before we register the platfrom serial devices, we need + * Before we register the platform serial devices, we need * to fixup their interrupts and their IO ports. */ DBG("Fixing serial ports interrupts and IO ports ...\n"); diff --git a/drivers/mtd/maps/plat-ram.c b/drivers/mtd/maps/plat-ram.c index dafb91944e70..76a76be5a7bd 100644 --- a/drivers/mtd/maps/plat-ram.c +++ b/drivers/mtd/maps/plat-ram.c @@ -4,7 +4,7 @@ * http://www.simtec.co.uk/products/SWLINUX/ * Ben Dooks * - * Generic platfrom device based RAM map + * Generic platform device based RAM map * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/net/cxgb3/sge.c b/drivers/net/cxgb3/sge.c index bdbd14727e4b..5dbc125822b9 100644 --- a/drivers/net/cxgb3/sge.c +++ b/drivers/net/cxgb3/sge.c @@ -196,13 +196,13 @@ static inline void refill_rspq(struct adapter *adapter, /** * need_skb_unmap - does the platform need unmapping of sk_buffs? * - * Returns true if the platfrom needs sk_buff unmapping. The compiler + * Returns true if the platform needs sk_buff unmapping. The compiler * optimizes away unecessary code if this returns true. */ static inline int need_skb_unmap(void) { /* - * This structure is used to tell if the platfrom needs buffer + * This structure is used to tell if the platform needs buffer * unmapping by checking if DECLARE_PCI_UNMAP_ADDR defines anything. */ struct dummy { diff --git a/drivers/video/mbx/mbxfb.c b/drivers/video/mbx/mbxfb.c index 01f77bcc68f9..afea9abbd678 100644 --- a/drivers/video/mbx/mbxfb.c +++ b/drivers/video/mbx/mbxfb.c @@ -693,7 +693,7 @@ static void __devinit setup_memc(struct fb_info *fbi) unsigned long tmp; int i; - /* FIXME: use platfrom specific parameters */ + /* FIXME: use platform specific parameters */ /* setup SDRAM controller */ write_reg_dly((LMCFG_LMC_DS | LMCFG_LMC_TS | LMCFG_LMD_TS | LMCFG_LMA_TS), diff --git a/include/linux/dm9000.h b/include/linux/dm9000.h index c30879cf93bc..96e87693d933 100644 --- a/include/linux/dm9000.h +++ b/include/linux/dm9000.h @@ -23,7 +23,7 @@ #define DM9000_PLATF_NO_EEPROM (0x0010) #define DM9000_PLATF_SIMPLE_PHY (0x0020) /* Use NSR to find LinkStatus */ -/* platfrom data for platfrom device structure's platfrom_data field */ +/* platform data for platform device structure's platform_data field */ struct dm9000_plat_data { unsigned int flags; -- cgit v1.2.3 From 0747e3bc54b43faaa88ab0b37eb5b6f50972965b Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Thu, 7 Jan 2010 00:44:08 +0100 Subject: Fix spelling of 'platform' in log messages Replace platfrom -> platform. Signed-off-by: Stefan Weil Signed-off-by: Jiri Kosina --- drivers/input/serio/i8042.c | 2 +- drivers/net/davinci_emac.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c index d84a36e545f6..33f3541aaf96 100644 --- a/drivers/input/serio/i8042.c +++ b/drivers/input/serio/i8042.c @@ -430,7 +430,7 @@ static bool i8042_filter(unsigned char data, unsigned char str, } if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { - dbg("Filtered out by platfrom filter\n"); + dbg("Filtered out by platform filter\n"); return true; } diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 33c4fe26178c..ea49d6ec4cba 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -2651,7 +2651,7 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev) pdata = pdev->dev.platform_data; if (!pdata) { - printk(KERN_ERR "DaVinci EMAC: No platfrom data\n"); + printk(KERN_ERR "DaVinci EMAC: No platform data\n"); return -ENODEV; } -- cgit v1.2.3 From 9ddc5b6f18fbac07d2746566b73b89e89fdd4e6a Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 20 Jan 2010 17:02:24 +0100 Subject: tree-wide: fix typos "ammount" -> "amount" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Jiri Kosina --- arch/powerpc/mm/init_32.c | 2 +- drivers/char/serial167.c | 2 +- drivers/isdn/sc/hardware.h | 2 +- drivers/message/i2o/iop.c | 2 +- drivers/net/ks8851.c | 2 +- drivers/platform/x86/thinkpad_acpi.c | 4 ++-- drivers/scsi/libfc/fc_fcp.c | 2 +- drivers/serial/samsung.c | 2 +- drivers/usb/serial/opticon.c | 2 +- drivers/usb/serial/symbolserial.c | 2 +- 10 files changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c index 4ec900af332f..b1dbd9ee87cc 100644 --- a/arch/powerpc/mm/init_32.c +++ b/arch/powerpc/mm/init_32.c @@ -47,7 +47,7 @@ #include "mmu_decl.h" #if defined(CONFIG_KERNEL_START_BOOL) || defined(CONFIG_LOWMEM_SIZE_BOOL) -/* The ammount of lowmem must be within 0xF0000000 - KERNELBASE. */ +/* The amount of lowmem must be within 0xF0000000 - KERNELBASE. */ #if (CONFIG_LOWMEM_SIZE > (0xF0000000 - PAGE_OFFSET)) #error "You must adjust CONFIG_LOWMEM_SIZE or CONFIG_START_KERNEL" #endif diff --git a/drivers/char/serial167.c b/drivers/char/serial167.c index 452370af95de..aee3c0d1759f 100644 --- a/drivers/char/serial167.c +++ b/drivers/char/serial167.c @@ -1990,7 +1990,7 @@ void mvme167_serial_console_setup(int cflag) /* * Attempt to set up all channels to something reasonable, and * bang out a INIT_CHAN command. We should then be able to limit - * the ammount of fiddling we have to do in normal running. + * the amount of fiddling we have to do in normal running. */ for (ch = 3; ch >= 0; ch--) { diff --git a/drivers/isdn/sc/hardware.h b/drivers/isdn/sc/hardware.h index 9e6d5302bf8e..627324856ead 100644 --- a/drivers/isdn/sc/hardware.h +++ b/drivers/isdn/sc/hardware.h @@ -87,7 +87,7 @@ #define BRI_CHANNELS 2 /* Number of B channels */ #define BRI_BASEPG_VAL 0x98 #define BRI_MAGIC 0x60000 /* Magic Number */ -#define BRI_MEMSIZE 0x10000 /* Ammount of RAM (64K) */ +#define BRI_MEMSIZE 0x10000 /* Amount of RAM (64K) */ #define BRI_PARTNO "72-029" #define BRI_FEATURES ISDN_FEATURE_L2_HDLC | ISDN_FEATURE_L3_TRANS; /* diff --git a/drivers/message/i2o/iop.c b/drivers/message/i2o/iop.c index e5ab62141503..ef5ce2676f05 100644 --- a/drivers/message/i2o/iop.c +++ b/drivers/message/i2o/iop.c @@ -539,7 +539,7 @@ static int i2o_iop_reset(struct i2o_controller *c) * which is indeterminate. We need to wait until the IOP has * rebooted before we can let the system talk to it. We read * the inbound Free_List until a message is available. If we - * can't read one in the given ammount of time, we assume the + * can't read one in the given amount of time, we assume the * IOP could not reboot properly. */ osm_debug("%s: Reset in progress, waiting for reboot...\n", diff --git a/drivers/net/ks8851.c b/drivers/net/ks8851.c index 6d3ac65bc35c..cfebe0e218fc 100644 --- a/drivers/net/ks8851.c +++ b/drivers/net/ks8851.c @@ -407,7 +407,7 @@ static irqreturn_t ks8851_irq(int irq, void *pw) * @buff: The buffer address * @len: The length of the data to read * - * Issue an RXQ FIFO read command and read the @len ammount of data from + * Issue an RXQ FIFO read command and read the @len amount of data from * the FIFO into the buffer specified by @buff. */ static void ks8851_rdfifo(struct ks8851_net *ks, u8 *buff, unsigned len) diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c index e67e4feb35cb..215621c31c5f 100644 --- a/drivers/platform/x86/thinkpad_acpi.c +++ b/drivers/platform/x86/thinkpad_acpi.c @@ -1667,7 +1667,7 @@ static void tpacpi_remove_driver_attributes(struct device_driver *drv) * Table of recommended minimum BIOS versions * * Reasons for listing: - * 1. Stable BIOS, listed because the unknown ammount of + * 1. Stable BIOS, listed because the unknown amount of * bugs and bad ACPI behaviour on older versions * * 2. BIOS or EC fw with known bugs that trigger on Linux @@ -7070,7 +7070,7 @@ static struct ibm_struct volume_driver_data = { * * Fan speed changes of any sort (including those caused by the * disengaged mode) are usually done slowly by the firmware as the - * maximum ammount of fan duty cycle change per second seems to be + * maximum amount of fan duty cycle change per second seems to be * limited. * * Reading is not available if GFAN exists. diff --git a/drivers/scsi/libfc/fc_fcp.c b/drivers/scsi/libfc/fc_fcp.c index 881d5dfe8c74..96ee599d9a05 100644 --- a/drivers/scsi/libfc/fc_fcp.c +++ b/drivers/scsi/libfc/fc_fcp.c @@ -522,7 +522,7 @@ crc_err: * * Called after receiving a Transfer Ready data descriptor. * If the LLD is capable of sequence offload then send down the - * seq_blen ammount of data in single frame, otherwise send + * seq_blen amount of data in single frame, otherwise send * multiple frames of the maximum frame payload supported by * the target port. */ diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c index 52e3df113ec0..03c010af966b 100644 --- a/drivers/serial/samsung.c +++ b/drivers/serial/samsung.c @@ -1271,7 +1271,7 @@ s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon) unsigned long ufstat, utrstat; if (ufcon & S3C2410_UFCON_FIFOMODE) { - /* fifo mode - check ammount of data in fifo registers... */ + /* fifo mode - check amount of data in fifo registers... */ ufstat = rd_regl(port, S3C2410_UFSTAT); return (ufstat & info->tx_fifofull) ? 0 : 1; diff --git a/drivers/usb/serial/opticon.c b/drivers/usb/serial/opticon.c index 4cdb975caa89..96937f1b8b97 100644 --- a/drivers/usb/serial/opticon.c +++ b/drivers/usb/serial/opticon.c @@ -120,7 +120,7 @@ static void opticon_bulk_callback(struct urb *urb) } } else { dev_dbg(&priv->udev->dev, - "Improper ammount of data received from the device, " + "Improper amount of data received from the device, " "%d bytes", urb->actual_length); } diff --git a/drivers/usb/serial/symbolserial.c b/drivers/usb/serial/symbolserial.c index b282c0f2d8e5..aebfcf699644 100644 --- a/drivers/usb/serial/symbolserial.c +++ b/drivers/usb/serial/symbolserial.c @@ -100,7 +100,7 @@ static void symbol_int_callback(struct urb *urb) } } else { dev_dbg(&priv->udev->dev, - "Improper ammount of data received from the device, " + "Improper amount of data received from the device, " "%d bytes", urb->actual_length); } -- cgit v1.2.3 From d9a5f04b6a8e0e681ae37fde84016a57ca17371f Mon Sep 17 00:00:00 2001 From: Shahar Havivi Date: Wed, 27 Jan 2010 10:18:28 +0100 Subject: vt: remove unused variables Remove unused fields in drivers/char/vt.c variables orig_buf and orig_count are assigned but never used. Signed-off-by: Shahar Havivi Signed-off-by: Jiri Kosina --- drivers/char/vt.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/char/vt.c b/drivers/char/vt.c index 50faa1fb0f06..94f530a29691 100644 --- a/drivers/char/vt.c +++ b/drivers/char/vt.c @@ -2119,8 +2119,6 @@ static int do_con_write(struct tty_struct *tty, const unsigned char *buf, int co uint8_t inverse; uint8_t width; u16 himask, charmask; - const unsigned char *orig_buf = NULL; - int orig_count; if (in_interrupt()) return count; @@ -2142,8 +2140,6 @@ static int do_con_write(struct tty_struct *tty, const unsigned char *buf, int co release_console_sem(); return 0; } - orig_buf = buf; - orig_count = count; himask = vc->vc_hi_font_mask; charmask = himask ? 0x1ff : 0xff; -- cgit v1.2.3 From 551e378ca1852dc51609b722014416d4da0770c6 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 28 Jan 2010 16:11:51 +0800 Subject: tree-wide: s/widht/width/g typo in comments Signed-off-by: Daniel Mack Cc: Jiri Kosina Signed-off-by: Jiri Kosina --- arch/m68k/include/asm/fbio.h | 2 +- arch/sparc/include/asm/fbio.h | 2 +- drivers/net/skfp/ess.c | 2 +- drivers/video/68328fb.c | 2 +- drivers/video/pm2fb.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/arch/m68k/include/asm/fbio.h b/arch/m68k/include/asm/fbio.h index b9215a0907d3..0a21da87f7d6 100644 --- a/arch/m68k/include/asm/fbio.h +++ b/arch/m68k/include/asm/fbio.h @@ -173,7 +173,7 @@ struct mdi_cfginfo { int mdi_ncluts; /* Number of implemented CLUTs in this MDI */ int mdi_type; /* FBTYPE name */ int mdi_height; /* height */ - int mdi_width; /* widht */ + int mdi_width; /* width */ int mdi_size; /* available ram */ int mdi_mode; /* 8bpp, 16bpp or 32bpp */ int mdi_pixfreq; /* pixel clock (from PROM) */ diff --git a/arch/sparc/include/asm/fbio.h b/arch/sparc/include/asm/fbio.h index b9215a0907d3..0a21da87f7d6 100644 --- a/arch/sparc/include/asm/fbio.h +++ b/arch/sparc/include/asm/fbio.h @@ -173,7 +173,7 @@ struct mdi_cfginfo { int mdi_ncluts; /* Number of implemented CLUTs in this MDI */ int mdi_type; /* FBTYPE name */ int mdi_height; /* height */ - int mdi_width; /* widht */ + int mdi_width; /* width */ int mdi_size; /* available ram */ int mdi_mode; /* 8bpp, 16bpp or 32bpp */ int mdi_pixfreq; /* pixel clock (from PROM) */ diff --git a/drivers/net/skfp/ess.c b/drivers/net/skfp/ess.c index a85efcfd9d0e..e8387d25f24a 100644 --- a/drivers/net/skfp/ess.c +++ b/drivers/net/skfp/ess.c @@ -557,7 +557,7 @@ static void ess_send_alc_req(struct s_smc *smc) /* * send never allocation request where the requested payload and - * overhead is zero or deallocate bandwidht when no bandwidth is + * overhead is zero or deallocate bandwidth when no bandwidth is * parsed */ if (!smc->mib.fddiESSPayload) { diff --git a/drivers/video/68328fb.c b/drivers/video/68328fb.c index 0b17824b0eb5..2110556f76b3 100644 --- a/drivers/video/68328fb.c +++ b/drivers/video/68328fb.c @@ -308,7 +308,7 @@ static int mc68x328fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, * Pseudocolor: * uses offset = 0 && length = RAMDAC register width. * var->{color}.offset is 0 - * var->{color}.length contains widht of DAC + * var->{color}.length contains width of DAC * cmap is not used * RAMDAC[X] is programmed to (red, green, blue) * Truecolor: diff --git a/drivers/video/pm2fb.c b/drivers/video/pm2fb.c index 36436ee6c1a4..27f93aab6ddc 100644 --- a/drivers/video/pm2fb.c +++ b/drivers/video/pm2fb.c @@ -896,7 +896,7 @@ static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green, * Pseudocolor: * uses offset = 0 && length = DAC register width. * var->{color}.offset is 0 - * var->{color}.length contains widht of DAC + * var->{color}.length contains width of DAC * cmap is not used * DAC[X] is programmed to (red, green, blue) * Truecolor: -- cgit v1.2.3 From 7d9b48ea81ee49779b95ecd0df5a8c2789e4f836 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 28 Jan 2010 22:09:43 +0100 Subject: fix typo "definetly" -> "definitely" in comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Jiri Kosina --- drivers/i2c/algos/i2c-algo-pcf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/i2c/algos/i2c-algo-pcf.c b/drivers/i2c/algos/i2c-algo-pcf.c index 7ce75775ec73..6b6bd06202b2 100644 --- a/drivers/i2c/algos/i2c-algo-pcf.c +++ b/drivers/i2c/algos/i2c-algo-pcf.c @@ -176,7 +176,7 @@ static int pcf_init_8584 (struct i2c_algo_pcf_data *adap) */ if (((temp = get_pcf(adap, 1)) & 0x7f) != (0)) { DEB2(printk(KERN_ERR "i2c-algo-pcf.o: PCF detection failed -- can't select S0 (0x%02x).\n", temp)); - return -ENXIO; /* definetly not PCF8584 */ + return -ENXIO; /* definitely not PCF8584 */ } /* load own address in S0, effective address is (own << 1) */ -- cgit v1.2.3 From b5218a87cbe0f01d551b2dae90b54cad8ded72df Mon Sep 17 00:00:00 2001 From: Pavel Roskin Date: Tue, 19 Jan 2010 13:25:50 +0100 Subject: drm/kms: fix spelling in error message Signed-off-by: Pavel Roskin [clemens@ladisch.de: merged into drm_fb_helper] Signed-off-by: Clemens Ladisch Signed-off-by: Jiri Kosina --- drivers/gpu/drm/drm_fb_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 0f9e90552dc4..6ce65f0a5cc0 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -694,7 +694,7 @@ int drm_fb_helper_set_par(struct fb_info *info) int i; if (var->pixclock != 0) { - DRM_ERROR("PIXEL CLCOK SET\n"); + DRM_ERROR("PIXEL CLOCK SET\n"); return -EINVAL; } -- cgit v1.2.3 From 1537a3638cbf741d3826c1002026cce487a6bee0 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 29 Jan 2010 15:57:49 +0800 Subject: tree-wide: fix 'lenght' typo in comments and code Some misspelled occurences of 'octet' and some comments were also fixed as I was on it. Signed-off-by: Daniel Mack Cc: Jiri Kosina Cc: Joe Perches Cc: Junio C Hamano Signed-off-by: Jiri Kosina --- arch/arm/mach-at91/include/mach/at91_mci.h | 2 +- arch/s390/crypto/sha_common.c | 2 +- drivers/crypto/hifn_795x.c | 2 +- drivers/isdn/mISDN/l1oip_core.c | 2 +- drivers/usb/wusbcore/wusbhc.h | 2 +- drivers/uwb/uwbd.c | 2 +- fs/cifs/asn1.c | 2 +- fs/ext4/mballoc.c | 2 +- fs/udf/inode.c | 2 +- kernel/trace/trace.h | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/arch/arm/mach-at91/include/mach/at91_mci.h b/arch/arm/mach-at91/include/mach/at91_mci.h index 550d503a1bca..57f8ee154943 100644 --- a/arch/arm/mach-at91/include/mach/at91_mci.h +++ b/arch/arm/mach-at91/include/mach/at91_mci.h @@ -77,7 +77,7 @@ #define AT91_MCI_BLKR 0x18 /* Block Register */ #define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ -#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ +#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block length */ #define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ #define AT91_MCR_RDR 0x30 /* Receive Data Register */ diff --git a/arch/s390/crypto/sha_common.c b/arch/s390/crypto/sha_common.c index 7903ec47e6b9..f42dbabc0d30 100644 --- a/arch/s390/crypto/sha_common.c +++ b/arch/s390/crypto/sha_common.c @@ -79,7 +79,7 @@ int s390_sha_final(struct shash_desc *desc, u8 *out) memset(ctx->buf + index, 0x00, end - index - 8); /* - * Append message length. Well, SHA-512 wants a 128 bit lenght value, + * Append message length. Well, SHA-512 wants a 128 bit length value, * nevertheless we use u64, should be enough for now... */ bits = ctx->count * 8; diff --git a/drivers/crypto/hifn_795x.c b/drivers/crypto/hifn_795x.c index 09ad9154d86c..73e8b1713b54 100644 --- a/drivers/crypto/hifn_795x.c +++ b/drivers/crypto/hifn_795x.c @@ -321,7 +321,7 @@ static atomic_t hifn_dev_number; #define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */ #define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */ #define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */ -#define HIFN_PUBOPLEN_EXP_S 7 /* exponent lenght shift */ +#define HIFN_PUBOPLEN_EXP_S 7 /* exponent length shift */ #define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */ #define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */ diff --git a/drivers/isdn/mISDN/l1oip_core.c b/drivers/isdn/mISDN/l1oip_core.c index 0843fcf8b381..325b1ad7d4b8 100644 --- a/drivers/isdn/mISDN/l1oip_core.c +++ b/drivers/isdn/mISDN/l1oip_core.c @@ -477,7 +477,7 @@ l1oip_socket_parse(struct l1oip *hc, struct sockaddr_in *sin, u8 *buf, int len) printk(KERN_DEBUG "%s: received frame, parsing... (%d)\n", __func__, len); - /* check lenght */ + /* check length */ if (len < 1+1+2) { printk(KERN_WARNING "%s: packet error - length %d below " "4 bytes\n", __func__, len); diff --git a/drivers/usb/wusbcore/wusbhc.h b/drivers/usb/wusbcore/wusbhc.h index fd2fd4e277e1..759cda55f7c3 100644 --- a/drivers/usb/wusbcore/wusbhc.h +++ b/drivers/usb/wusbcore/wusbhc.h @@ -198,7 +198,7 @@ struct wusb_port { * ports) this HC will take. Read-only. * * @port Array of port status for each fake root port. Guaranteed to - * always be the same lenght during device existence + * always be the same length during device existence * [this allows for some unlocked but referenced reading]. * * @mmcies_max Max number of Information Elements this HC can send diff --git a/drivers/uwb/uwbd.c b/drivers/uwb/uwbd.c index 5a777d8624da..6210fe1fd1bb 100644 --- a/drivers/uwb/uwbd.c +++ b/drivers/uwb/uwbd.c @@ -43,7 +43,7 @@ * * EVENTS * - * Events have a type, a subtype, a lenght, some other stuff and the + * Events have a type, a subtype, a length, some other stuff and the * data blob, which depends on the event. The header is 'struct * uwb_event'; for payloads, see 'struct uwbd_evt_*'. * diff --git a/fs/cifs/asn1.c b/fs/cifs/asn1.c index 20692fbfdb24..a20bea598933 100644 --- a/fs/cifs/asn1.c +++ b/fs/cifs/asn1.c @@ -136,7 +136,7 @@ asn1_enum_decode(struct asn1_ctx *ctx, __le32 *val) return 0; } - ch = *(ctx->pointer)++; /* ch has 0xa, ptr points to lenght octet */ + ch = *(ctx->pointer)++; /* ch has 0xa, ptr points to length octet */ if ((ch) == ASN1_ENUM) /* if ch value is ENUM, 0xa */ *val = *(++(ctx->pointer)); /* value has enum value */ else diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index d34afad3e137..b794dd8141a0 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -69,7 +69,7 @@ * * pa_lstart -> the logical start block for this prealloc space * pa_pstart -> the physical start block for this prealloc space - * pa_len -> lenght for this prealloc space + * pa_len -> length for this prealloc space * pa_free -> free space available in this prealloc space * * The inode preallocation space is used looking at the _logical_ start diff --git a/fs/udf/inode.c b/fs/udf/inode.c index f90231eb2916..772a4fa557f2 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -102,7 +102,7 @@ void udf_clear_inode(struct inode *inode) if (iinfo->i_alloc_type != ICBTAG_FLAG_AD_IN_ICB && inode->i_size != iinfo->i_lenExtents) { printk(KERN_WARNING "UDF-fs (%s): Inode %lu (mode %o) has " - "inode size %llu different from extent lenght %llu. " + "inode size %llu different from extent length %llu. " "Filesystem need not be standards compliant.\n", inode->i_sb->s_id, inode->i_ino, inode->i_mode, (unsigned long long)inode->i_size, diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h index 4df6a77eb196..e4b32c8aa85f 100644 --- a/kernel/trace/trace.h +++ b/kernel/trace/trace.h @@ -549,7 +549,7 @@ static inline int ftrace_trace_task(struct task_struct *task) * struct trace_parser - servers for reading the user input separated by spaces * @cont: set if the input is not complete - no final space char was found * @buffer: holds the parsed user input - * @idx: user input lenght + * @idx: user input length * @size: buffer size */ struct trace_parser { -- cgit v1.2.3 From 13d605de2ece8c8f7c17a88747d90b7931350ee5 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:15:15 +0000 Subject: sh: Build drivers/sh for ARM-based SH-Mobile CPUs. Build drivers/sh in the case of ARM-based SH-Mobile CPUs. Shared code for the interrupt controller (INTC) and the gpio/pinmux (PFC) is located there. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/Makefile b/drivers/Makefile index 6ee53c7a57a1..e94cb1b79633 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -99,6 +99,7 @@ obj-$(CONFIG_SGI_SN) += sn/ obj-y += firmware/ obj-$(CONFIG_CRYPTO) += crypto/ obj-$(CONFIG_SUPERH) += sh/ +obj-$(CONFIG_ARCH_SHMOBILE) += sh/ obj-$(CONFIG_GENERIC_TIME) += clocksource/ obj-$(CONFIG_DMA_ENGINE) += dma/ obj-$(CONFIG_DCA) += dca/ -- cgit v1.2.3 From 65a5b28f0af00dddd785b516914739460562638f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:15:25 +0000 Subject: sh: Let INTC set IRQF_VALID on ARM platforms. Reuse the SuperH INTC code on ARM by using set_irq_flags() to set IRQF_VALID on ARM platforms. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/sh/intc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c index d5d7f23c19a5..926013bece12 100644 --- a/drivers/sh/intc.c +++ b/drivers/sh/intc.c @@ -658,6 +658,10 @@ static void __init intc_register_irq(struct intc_desc *desc, if (desc->ack_regs) ack_handle[irq] = intc_ack_data(desc, d, enum_id); + +#ifdef CONFIG_ARM + set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */ +#endif } static unsigned int __init save_reg(struct intc_desc_int *d, @@ -902,8 +906,12 @@ static unsigned int create_irq_on_node(unsigned int irq_want, int node) out_unlock: spin_unlock_irqrestore(&vector_lock, flags); - if (irq > 0) + if (irq > 0) { dynamic_irq_init(irq); +#ifdef CONFIG_ARM + set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */ +#endif + } return irq; } -- cgit v1.2.3 From 8a77b8d0744ab21b59a9413c41c6a3d6cb9b0b4f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 5 Feb 2010 11:15:33 +0000 Subject: serial: sh-sci: Support ARM-based SH-Mobile CPUs. Add support for ARM-based SH-Mobile CPUs to the sh-sci driver. Also remove the SCLSR register that is missing on sh772x, sh7705 and SH-Mobile. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- drivers/serial/Kconfig | 2 +- drivers/serial/sh-sci.h | 22 ++++++++++++++-------- 2 files changed, 15 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 9ff47db0b2ce..406ad918cbac 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -996,7 +996,7 @@ config SERIAL_IP22_ZILOG_CONSOLE config SERIAL_SH_SCI tristate "SuperH SCI(F) serial port support" - depends on HAVE_CLK && (SUPERH || H8300) + depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE) select SERIAL_CORE config SERIAL_SH_SCI_NR_UARTS diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index f7d2589926d2..fad67d33b0bd 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h @@ -30,7 +30,8 @@ */ # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ # define PORT_PTCR 0xA405011EUL # define PORT_PVCR 0xA4050122UL @@ -228,7 +229,8 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) # define SCIF_ORER 0x0200 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) # define SCIF_RFDC_MASK 0x007f @@ -261,7 +263,8 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) @@ -356,7 +359,7 @@ SCI_OUT(sci_size, sci_offset, value); \ } -#ifdef CONFIG_CPU_SH3 +#if defined(CONFIG_CPU_SH3) || defined(CONFIG_ARCH_SHMOBILE) #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ @@ -366,7 +369,8 @@ CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) #define SCIF_FNS(name, scif_offset, scif_size) \ CPU_SCIF_FNS(name, scif_offset, scif_size) #else @@ -401,7 +405,8 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) SCIF_FNS(SCSMR, 0x00, 16) SCIF_FNS(SCBRR, 0x04, 8) @@ -413,7 +418,7 @@ SCIF_FNS(SCFCR, 0x18, 16) SCIF_FNS(SCFDR, 0x1c, 16) SCIF_FNS(SCxTDR, 0x20, 8) SCIF_FNS(SCxRDR, 0x24, 8) -SCIF_FNS(SCLSR, 0x24, 16) +SCIF_FNS(SCLSR, 0x00, 0) #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ defined(CONFIG_CPU_SUBTYPE_SH7724) SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) @@ -583,7 +588,8 @@ static inline int sci_rxd_in(struct uart_port *port) #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ - defined(CONFIG_CPU_SUBTYPE_SH7721) + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_ARCH_SHMOBILE) #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ defined(CONFIG_CPU_SUBTYPE_SH7724) -- cgit v1.2.3 From 40bacf1631a3e8654b1128aa9b72e73ca801c9e4 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 23 Dec 2009 03:23:21 -0500 Subject: drm/radeon/kms: add support for hw i2c on r1xx-r5xx wire hw i2c support into radeon i2c algo. fixes merged: - handle bus probing correctly - use meaningful error numbers - abort if transaction fails - The line mapping is different depending on the asic. - protect hw i2c engine with a mutex - rs300 doesn't have a pin select bit - r200 has a different pin select setup Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r500_reg.h | 100 +++--- drivers/gpu/drm/radeon/radeon.h | 1 + drivers/gpu/drm/radeon/radeon_combios.c | 71 +++- drivers/gpu/drm/radeon/radeon_device.c | 1 + drivers/gpu/drm/radeon/radeon_i2c.c | 597 +++++++++++++++++++++++++++++++- drivers/gpu/drm/radeon/radeon_reg.h | 48 +-- 6 files changed, 736 insertions(+), 82 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h index 74ad89bdf2b5..0cf2ad2a5585 100644 --- a/drivers/gpu/drm/radeon/r500_reg.h +++ b/drivers/gpu/drm/radeon/r500_reg.h @@ -717,54 +717,62 @@ #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 #define AVIVO_DC_GPIO_HPD_A 0x7e94 - -#define AVIVO_GPIO_0 0x7e30 -#define AVIVO_GPIO_1 0x7e40 -#define AVIVO_GPIO_2 0x7e50 -#define AVIVO_GPIO_3 0x7e60 - #define AVIVO_DC_GPIO_HPD_Y 0x7e9c -#define AVIVO_I2C_STATUS 0x7d30 -# define AVIVO_I2C_STATUS_DONE (1 << 0) -# define AVIVO_I2C_STATUS_NACK (1 << 1) -# define AVIVO_I2C_STATUS_HALT (1 << 2) -# define AVIVO_I2C_STATUS_GO (1 << 3) -# define AVIVO_I2C_STATUS_MASK 0x7 -/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe - * DONE? */ -# define AVIVO_I2C_STATUS_CMD_RESET 0x7 -# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) -#define AVIVO_I2C_STOP 0x7d34 -#define AVIVO_I2C_START_CNTL 0x7d38 -# define AVIVO_I2C_START (1 << 8) -# define AVIVO_I2C_CONNECTOR0 (0 << 16) -# define AVIVO_I2C_CONNECTOR1 (1 << 16) -#define R520_I2C_START (1<<0) -#define R520_I2C_STOP (1<<1) -#define R520_I2C_RX (1<<2) -#define R520_I2C_EN (1<<8) -#define R520_I2C_DDC1 (0<<16) -#define R520_I2C_DDC2 (1<<16) -#define R520_I2C_DDC3 (2<<16) -#define R520_I2C_DDC_MASK (3<<16) -#define AVIVO_I2C_CONTROL2 0x7d3c -# define AVIVO_I2C_7D3C_SIZE_SHIFT 8 -# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) -#define AVIVO_I2C_CONTROL3 0x7d40 -/* Reading is done 4 bytes at a time: read the bottom 8 bits from - * 7d44, four times in a row. - * Writing is a little more complex. First write DATA with - * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic - * magic number, zz is, I think, the slave address, and yy is the byte - * you want to write. */ -#define AVIVO_I2C_DATA 0x7d44 -#define R520_I2C_ADDR_COUNT_MASK (0x7) -#define R520_I2C_DATA_COUNT_SHIFT (8) -#define R520_I2C_DATA_COUNT_MASK (0xF00) -#define AVIVO_I2C_CNTL 0x7d50 -# define AVIVO_I2C_EN (1 << 0) -# define AVIVO_I2C_RESET (1 << 8) +#define AVIVO_DC_I2C_STATUS1 0x7d30 +# define AVIVO_DC_I2C_DONE (1 << 0) +# define AVIVO_DC_I2C_NACK (1 << 1) +# define AVIVO_DC_I2C_HALT (1 << 2) +# define AVIVO_DC_I2C_GO (1 << 3) +#define AVIVO_DC_I2C_RESET 0x7d34 +# define AVIVO_DC_I2C_SOFT_RESET (1 << 0) +# define AVIVO_DC_I2C_ABORT (1 << 8) +#define AVIVO_DC_I2C_CONTROL1 0x7d38 +# define AVIVO_DC_I2C_START (1 << 0) +# define AVIVO_DC_I2C_STOP (1 << 1) +# define AVIVO_DC_I2C_RECEIVE (1 << 2) +# define AVIVO_DC_I2C_EN (1 << 8) +# define AVIVO_DC_I2C_PIN_SELECT(x) ((x) << 16) +# define AVIVO_SEL_DDC1 0 +# define AVIVO_SEL_DDC2 1 +# define AVIVO_SEL_DDC3 2 +#define AVIVO_DC_I2C_CONTROL2 0x7d3c +# define AVIVO_DC_I2C_ADDR_COUNT(x) ((x) << 0) +# define AVIVO_DC_I2C_DATA_COUNT(x) ((x) << 8) +#define AVIVO_DC_I2C_CONTROL3 0x7d40 +# define AVIVO_DC_I2C_DATA_DRIVE_EN (1 << 0) +# define AVIVO_DC_I2C_DATA_DRIVE_SEL (1 << 1) +# define AVIVO_DC_I2C_CLK_DRIVE_EN (1 << 7) +# define AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY(x) ((x) << 8) +# define AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY(x) ((x) << 16) +# define AVIVO_DC_I2C_TIME_LIMIT(x) ((x) << 24) +#define AVIVO_DC_I2C_DATA 0x7d44 +#define AVIVO_DC_I2C_INTERRUPT_CONTROL 0x7d48 +# define AVIVO_DC_I2C_INTERRUPT_STATUS (1 << 0) +# define AVIVO_DC_I2C_INTERRUPT_AK (1 << 8) +# define AVIVO_DC_I2C_INTERRUPT_ENABLE (1 << 16) +#define AVIVO_DC_I2C_ARBITRATION 0x7d50 +# define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C (1 << 0) +# define AVIVO_DC_I2C_SW_CAN_USE_I2C (1 << 1) +# define AVIVO_DC_I2C_SW_DONE_USING_I2C (1 << 8) +# define AVIVO_DC_I2C_HW_NEEDS_I2C (1 << 9) +# define AVIVO_DC_I2C_ABORT_HDCP_I2C (1 << 16) +# define AVIVO_DC_I2C_HW_USING_I2C (1 << 17) + +#define AVIVO_DC_GPIO_DDC1_MASK 0x7e40 +#define AVIVO_DC_GPIO_DDC1_A 0x7e44 +#define AVIVO_DC_GPIO_DDC1_EN 0x7e48 +#define AVIVO_DC_GPIO_DDC1_Y 0x7e4c + +#define AVIVO_DC_GPIO_DDC2_MASK 0x7e50 +#define AVIVO_DC_GPIO_DDC2_A 0x7e54 +#define AVIVO_DC_GPIO_DDC2_EN 0x7e58 +#define AVIVO_DC_GPIO_DDC2_Y 0x7e5c + +#define AVIVO_DC_GPIO_DDC3_MASK 0x7e60 +#define AVIVO_DC_GPIO_DDC3_A 0x7e64 +#define AVIVO_DC_GPIO_DDC3_EN 0x7e68 +#define AVIVO_DC_GPIO_DDC3_Y 0x7e6c #define AVIVO_DISP_INTERRUPT_STATUS 0x7edc # define AVIVO_D1_VBLANK_INTERRUPT (1 << 4) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index f57480ba1355..88113f756ab7 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -829,6 +829,7 @@ struct radeon_device { struct r600_ih ih; /* r6/700 interrupt ring */ struct workqueue_struct *wq; struct work_struct hotplug_work; + struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ /* audio stuff */ struct timer_list audio_timer; diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index 318afe83e6b0..e208d730f514 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -486,9 +486,65 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde i2c.y_data_reg = ddc_line; } - if (rdev->family < CHIP_R200) - i2c.hw_capable = false; - else { + switch (rdev->family) { + case CHIP_R100: + case CHIP_RV100: + case CHIP_RS100: + case CHIP_RV200: + case CHIP_RS200: + case CHIP_RS300: + switch (ddc_line) { + case RADEON_GPIO_DVI_DDC: + /* in theory this should be hw capable, + * but it doesn't seem to work + */ + i2c.hw_capable = false; + break; + default: + i2c.hw_capable = false; + break; + } + break; + case CHIP_R200: + switch (ddc_line) { + case RADEON_GPIO_DVI_DDC: + case RADEON_GPIO_MONID: + i2c.hw_capable = true; + break; + default: + i2c.hw_capable = false; + break; + } + break; + case CHIP_RV250: + case CHIP_RV280: + switch (ddc_line) { + case RADEON_GPIO_VGA_DDC: + case RADEON_GPIO_DVI_DDC: + case RADEON_GPIO_CRT2_DDC: + i2c.hw_capable = true; + break; + default: + i2c.hw_capable = false; + break; + } + break; + case CHIP_R300: + case CHIP_R350: + switch (ddc_line) { + case RADEON_GPIO_VGA_DDC: + case RADEON_GPIO_DVI_DDC: + i2c.hw_capable = true; + break; + default: + i2c.hw_capable = false; + break; + } + break; + case CHIP_RV350: + case CHIP_RV380: + case CHIP_RS400: + case CHIP_RS480: switch (ddc_line) { case RADEON_GPIO_VGA_DDC: case RADEON_GPIO_DVI_DDC: @@ -504,6 +560,10 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde i2c.hw_capable = false; break; } + break; + default: + i2c.hw_capable = false; + break; } i2c.mm_i2c = false; i2c.i2c_id = 0; @@ -1253,7 +1313,10 @@ bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); break; case DDC_LCD: /* MM i2c */ - DRM_ERROR("MM i2c requires hw i2c engine\n"); + i2c_bus.valid = true; + i2c_bus.hw_capable = true; + i2c_bus.mm_i2c = true; + tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); break; default: DRM_ERROR("Unsupported gpio %d\n", gpio); diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 768b1509fa03..18ac29c505cf 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -638,6 +638,7 @@ int radeon_device_init(struct radeon_device *rdev, mutex_init(&rdev->cs_mutex); mutex_init(&rdev->ib_pool.mutex); mutex_init(&rdev->cp.mutex); + mutex_init(&rdev->dc_hw_i2c_mutex); if (rdev->family >= CHIP_R600) spin_lock_init(&rdev->ih.lock); mutex_init(&rdev->gem.mutex); diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c index 75b090f60208..b47a5615fe6a 100644 --- a/drivers/gpu/drm/radeon/radeon_i2c.c +++ b/drivers/gpu/drm/radeon/radeon_i2c.c @@ -26,6 +26,7 @@ #include "drmP.h" #include "radeon_drm.h" #include "radeon.h" +#include "atom.h" /** * radeon_ddc_probe @@ -71,13 +72,25 @@ static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) */ if (rec->hw_capable) { if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { - if (rec->a_clk_reg == RADEON_GPIO_MONID) { + u32 reg; + + if (rdev->family >= CHIP_RV350) + reg = RADEON_GPIO_MONID; + else if ((rdev->family == CHIP_R300) || + (rdev->family == CHIP_R350)) + reg = RADEON_GPIO_DVI_DDC; + else + reg = RADEON_GPIO_CRT2_DDC; + + mutex_lock(&rdev->dc_hw_i2c_mutex); + if (rec->a_clk_reg == reg) { WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); } else { WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); } + mutex_unlock(&rdev->dc_hw_i2c_mutex); } } @@ -168,22 +181,584 @@ static void set_data(void *i2c_priv, int data) WREG32(rec->en_data_reg, val); } -static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap, - struct i2c_msg *msgs, int num) +/* hw i2c engine for r1xx-4xx hardware + * hw can buffer up to 15 bytes + */ +static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg *msgs, int num) +{ + struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); + struct radeon_device *rdev = i2c->dev->dev_private; + struct radeon_i2c_bus_rec *rec = &i2c->rec; + struct i2c_msg *p; + int i, j, k, ret = num; + /* XXX: use get_engine_clock() to get the current sclk */ + u32 prescale = (((rdev->clock.default_sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; + u32 i2c_cntl_0, i2c_cntl_1, i2c_data; + u32 tmp, reg; + + mutex_lock(&rdev->dc_hw_i2c_mutex); + + reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | + RADEON_I2C_START | + RADEON_I2C_STOP | + RADEON_I2C_GO); + + if (rdev->is_atom_bios) { + tmp = RREG32(RADEON_BIOS_6_SCRATCH); + WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); + } + + if (rec->mm_i2c) { + i2c_cntl_0 = RADEON_I2C_CNTL_0; + i2c_cntl_1 = RADEON_I2C_CNTL_1; + i2c_data = RADEON_I2C_DATA; + } else { + i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; + i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; + i2c_data = RADEON_DVI_I2C_DATA; + + switch (rdev->family) { + case CHIP_R100: + case CHIP_RV100: + case CHIP_RS100: + case CHIP_RV200: + case CHIP_RS200: + case CHIP_RS300: + switch (rec->mask_clk_reg) { + case RADEON_GPIO_DVI_DDC: + /* no gpio select bit */ + break; + default: + DRM_ERROR("gpio not supported with hw i2c\n"); + ret = -EINVAL; + goto done; + } + break; + case CHIP_R200: + /* only bit 4 on r200 */ + switch (rec->mask_clk_reg) { + case RADEON_GPIO_DVI_DDC: + reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); + break; + case RADEON_GPIO_MONID: + reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); + break; + default: + DRM_ERROR("gpio not supported with hw i2c\n"); + ret = -EINVAL; + goto done; + } + break; + case CHIP_RV250: + case CHIP_RV280: + /* bits 3 and 4 */ + switch (rec->mask_clk_reg) { + case RADEON_GPIO_DVI_DDC: + reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); + break; + case RADEON_GPIO_VGA_DDC: + reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); + break; + case RADEON_GPIO_CRT2_DDC: + reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); + break; + default: + DRM_ERROR("gpio not supported with hw i2c\n"); + ret = -EINVAL; + goto done; + } + break; + case CHIP_R300: + case CHIP_R350: + /* only bit 4 on r300/r350 */ + switch (rec->mask_clk_reg) { + case RADEON_GPIO_VGA_DDC: + reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); + break; + case RADEON_GPIO_DVI_DDC: + reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); + break; + default: + DRM_ERROR("gpio not supported with hw i2c\n"); + ret = -EINVAL; + goto done; + } + break; + case CHIP_RV350: + case CHIP_RV380: + case CHIP_R420: + case CHIP_R423: + case CHIP_RV410: + case CHIP_RS400: + case CHIP_RS480: + /* bits 3 and 4 */ + switch (rec->mask_clk_reg) { + case RADEON_GPIO_VGA_DDC: + reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); + break; + case RADEON_GPIO_DVI_DDC: + reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); + break; + case RADEON_GPIO_MONID: + reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); + break; + default: + DRM_ERROR("gpio not supported with hw i2c\n"); + ret = -EINVAL; + goto done; + } + break; + default: + DRM_ERROR("unsupported asic\n"); + ret = -EINVAL; + goto done; + break; + } + } + + /* check for bus probe */ + p = &msgs[0]; + if ((num == 1) && (p->len == 0)) { + WREG32(i2c_cntl_0, (RADEON_I2C_DONE | + RADEON_I2C_NACK | + RADEON_I2C_HALT | + RADEON_I2C_SOFT_RST)); + WREG32(i2c_data, (p->addr << 1) & 0xff); + WREG32(i2c_data, 0); + WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | + (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | + RADEON_I2C_EN | + (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); + WREG32(i2c_cntl_0, reg); + for (k = 0; k < 32; k++) { + udelay(10); + tmp = RREG32(i2c_cntl_0); + if (tmp & RADEON_I2C_GO) + continue; + tmp = RREG32(i2c_cntl_0); + if (tmp & RADEON_I2C_DONE) + break; + else { + DRM_DEBUG("i2c write error 0x%08x\n", tmp); + WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); + ret = -EIO; + goto done; + } + } + goto done; + } + + for (i = 0; i < num; i++) { + p = &msgs[i]; + for (j = 0; j < p->len; j++) { + if (p->flags & I2C_M_RD) { + WREG32(i2c_cntl_0, (RADEON_I2C_DONE | + RADEON_I2C_NACK | + RADEON_I2C_HALT | + RADEON_I2C_SOFT_RST)); + WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); + WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | + (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | + RADEON_I2C_EN | + (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); + WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); + for (k = 0; k < 32; k++) { + udelay(10); + tmp = RREG32(i2c_cntl_0); + if (tmp & RADEON_I2C_GO) + continue; + tmp = RREG32(i2c_cntl_0); + if (tmp & RADEON_I2C_DONE) + break; + else { + DRM_DEBUG("i2c read error 0x%08x\n", tmp); + WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); + ret = -EIO; + goto done; + } + } + p->buf[j] = RREG32(i2c_data) & 0xff; + } else { + WREG32(i2c_cntl_0, (RADEON_I2C_DONE | + RADEON_I2C_NACK | + RADEON_I2C_HALT | + RADEON_I2C_SOFT_RST)); + WREG32(i2c_data, (p->addr << 1) & 0xff); + WREG32(i2c_data, p->buf[j]); + WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | + (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | + RADEON_I2C_EN | + (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); + WREG32(i2c_cntl_0, reg); + for (k = 0; k < 32; k++) { + udelay(10); + tmp = RREG32(i2c_cntl_0); + if (tmp & RADEON_I2C_GO) + continue; + tmp = RREG32(i2c_cntl_0); + if (tmp & RADEON_I2C_DONE) + break; + else { + DRM_DEBUG("i2c write error 0x%08x\n", tmp); + WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); + ret = -EIO; + goto done; + } + } + } + } + } + +done: + WREG32(i2c_cntl_0, 0); + WREG32(i2c_cntl_1, 0); + WREG32(i2c_cntl_0, (RADEON_I2C_DONE | + RADEON_I2C_NACK | + RADEON_I2C_HALT | + RADEON_I2C_SOFT_RST)); + + if (rdev->is_atom_bios) { + tmp = RREG32(RADEON_BIOS_6_SCRATCH); + tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; + WREG32(RADEON_BIOS_6_SCRATCH, tmp); + } + + mutex_unlock(&rdev->dc_hw_i2c_mutex); + + return ret; +} + +/* hw i2c engine for r5xx hardware + * hw can buffer up to 15 bytes + */ +static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg *msgs, int num) +{ + struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); + struct radeon_device *rdev = i2c->dev->dev_private; + struct radeon_i2c_bus_rec *rec = &i2c->rec; + struct i2c_msg *p; + int i2c_clock = 50; + int i, j, remaining, current_count, buffer_offset, ret = num; + /* XXX: use get_engine_clock() to get the current sclk */ + u32 prescale; + u32 tmp, reg; + u32 saved1, saved2; + + mutex_lock(&rdev->dc_hw_i2c_mutex); + + /* clear gpio mask bits */ + tmp = RREG32(rec->mask_clk_reg); + tmp &= ~rec->mask_clk_mask; + WREG32(rec->mask_clk_reg, tmp); + tmp = RREG32(rec->mask_clk_reg); + + tmp = RREG32(rec->mask_data_reg); + tmp &= ~rec->mask_data_mask; + WREG32(rec->mask_data_reg, tmp); + tmp = RREG32(rec->mask_data_reg); + + /* clear pin values */ + tmp = RREG32(rec->a_clk_reg); + tmp &= ~rec->a_clk_mask; + WREG32(rec->a_clk_reg, tmp); + tmp = RREG32(rec->a_clk_reg); + + tmp = RREG32(rec->a_data_reg); + tmp &= ~rec->a_data_mask; + WREG32(rec->a_data_reg, tmp); + tmp = RREG32(rec->a_data_reg); + + /* set the pins to input */ + tmp = RREG32(rec->en_clk_reg); + tmp &= ~rec->en_clk_mask; + WREG32(rec->en_clk_reg, tmp); + tmp = RREG32(rec->en_clk_reg); + + tmp = RREG32(rec->en_data_reg); + tmp &= ~rec->en_data_mask; + WREG32(rec->en_data_reg, tmp); + tmp = RREG32(rec->en_data_reg); + + /* */ + tmp = RREG32(RADEON_BIOS_6_SCRATCH); + WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); + saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); + saved2 = RREG32(0x494); + WREG32(0x494, saved2 | 0x1); + + WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); + for (i = 0; i < 50; i++) { + udelay(1); + if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) + break; + } + if (i == 50) { + DRM_ERROR("failed to get i2c bus\n"); + ret = -EBUSY; + goto done; + } + + if (rdev->family == CHIP_R520) + prescale = (127 << 8) + ((rdev->clock.default_sclk * 10) / (4 * 127 * i2c_clock)); + else + prescale = (((rdev->clock.default_sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; + + reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; + switch (rec->mask_clk_reg) { + case AVIVO_DC_GPIO_DDC1_MASK: + reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); + break; + case AVIVO_DC_GPIO_DDC2_MASK: + reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); + break; + case AVIVO_DC_GPIO_DDC3_MASK: + reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); + break; + default: + DRM_ERROR("gpio not supported with hw i2c\n"); + ret = -EINVAL; + goto done; + } + + /* check for bus probe */ + p = &msgs[0]; + if ((num == 1) && (p->len == 0)) { + WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | + AVIVO_DC_I2C_NACK | + AVIVO_DC_I2C_HALT)); + WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); + udelay(1); + WREG32(AVIVO_DC_I2C_RESET, 0); + + WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); + WREG32(AVIVO_DC_I2C_DATA, 0); + + WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); + WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | + AVIVO_DC_I2C_DATA_COUNT(1) | + (prescale << 16))); + WREG32(AVIVO_DC_I2C_CONTROL1, reg); + WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); + for (j = 0; j < 200; j++) { + udelay(50); + tmp = RREG32(AVIVO_DC_I2C_STATUS1); + if (tmp & AVIVO_DC_I2C_GO) + continue; + tmp = RREG32(AVIVO_DC_I2C_STATUS1); + if (tmp & AVIVO_DC_I2C_DONE) + break; + else { + DRM_DEBUG("i2c write error 0x%08x\n", tmp); + WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); + ret = -EIO; + goto done; + } + } + goto done; + } + + for (i = 0; i < num; i++) { + p = &msgs[i]; + remaining = p->len; + buffer_offset = 0; + if (p->flags & I2C_M_RD) { + while (remaining) { + if (remaining > 15) + current_count = 15; + else + current_count = remaining; + WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | + AVIVO_DC_I2C_NACK | + AVIVO_DC_I2C_HALT)); + WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); + udelay(1); + WREG32(AVIVO_DC_I2C_RESET, 0); + + WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); + WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); + WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | + AVIVO_DC_I2C_DATA_COUNT(current_count) | + (prescale << 16))); + WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); + WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); + for (j = 0; j < 200; j++) { + udelay(50); + tmp = RREG32(AVIVO_DC_I2C_STATUS1); + if (tmp & AVIVO_DC_I2C_GO) + continue; + tmp = RREG32(AVIVO_DC_I2C_STATUS1); + if (tmp & AVIVO_DC_I2C_DONE) + break; + else { + DRM_DEBUG("i2c read error 0x%08x\n", tmp); + WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); + ret = -EIO; + goto done; + } + } + for (j = 0; j < current_count; j++) + p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; + remaining -= current_count; + buffer_offset += current_count; + } + } else { + while (remaining) { + if (remaining > 15) + current_count = 15; + else + current_count = remaining; + WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | + AVIVO_DC_I2C_NACK | + AVIVO_DC_I2C_HALT)); + WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); + udelay(1); + WREG32(AVIVO_DC_I2C_RESET, 0); + + WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); + for (j = 0; j < current_count; j++) + WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); + + WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); + WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | + AVIVO_DC_I2C_DATA_COUNT(current_count) | + (prescale << 16))); + WREG32(AVIVO_DC_I2C_CONTROL1, reg); + WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); + for (j = 0; j < 200; j++) { + udelay(50); + tmp = RREG32(AVIVO_DC_I2C_STATUS1); + if (tmp & AVIVO_DC_I2C_GO) + continue; + tmp = RREG32(AVIVO_DC_I2C_STATUS1); + if (tmp & AVIVO_DC_I2C_DONE) + break; + else { + DRM_DEBUG("i2c write error 0x%08x\n", tmp); + WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); + ret = -EIO; + goto done; + } + } + remaining -= current_count; + buffer_offset += current_count; + } + } + } + +done: + WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | + AVIVO_DC_I2C_NACK | + AVIVO_DC_I2C_HALT)); + WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); + udelay(1); + WREG32(AVIVO_DC_I2C_RESET, 0); + + WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); + WREG32(AVIVO_DC_I2C_CONTROL1, saved1); + WREG32(0x494, saved2); + tmp = RREG32(RADEON_BIOS_6_SCRATCH); + tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; + WREG32(RADEON_BIOS_6_SCRATCH, tmp); + + mutex_unlock(&rdev->dc_hw_i2c_mutex); + + return ret; +} + +static int radeon_sw_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg *msgs, int num) { struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); int ret; radeon_i2c_do_lock(i2c, 1); - if (i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num) == num) - ret = num; - else - ret = -1; + ret = i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num); radeon_i2c_do_lock(i2c, 0); return ret; } +static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg *msgs, int num) +{ + struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); + struct radeon_device *rdev = i2c->dev->dev_private; + struct radeon_i2c_bus_rec *rec = &i2c->rec; + int ret; + + switch (rdev->family) { + case CHIP_R100: + case CHIP_RV100: + case CHIP_RS100: + case CHIP_RV200: + case CHIP_RS200: + case CHIP_R200: + case CHIP_RV250: + case CHIP_RS300: + case CHIP_RV280: + case CHIP_R300: + case CHIP_R350: + case CHIP_RV350: + case CHIP_RV380: + case CHIP_R420: + case CHIP_R423: + case CHIP_RV410: + case CHIP_RS400: + case CHIP_RS480: + if (rec->hw_capable) + ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); + else + ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num); + break; + case CHIP_RS600: + case CHIP_RS690: + case CHIP_RS740: + /* XXX fill in hw i2c implementation */ + ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num); + break; + case CHIP_RV515: + case CHIP_R520: + case CHIP_RV530: + case CHIP_RV560: + case CHIP_RV570: + case CHIP_R580: + if (rec->hw_capable) { + if (rec->mm_i2c) + ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); + else + ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); + } else + ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num); + break; + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + /* XXX fill in hw i2c implementation */ + ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num); + break; + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + /* XXX fill in hw i2c implementation */ + ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num); + break; + default: + DRM_ERROR("i2c: unhandled radeon chip\n"); + ret = -EIO; + break; + } + + return ret; +} + static u32 radeon_i2c_func(struct i2c_adapter *adap) { return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; @@ -205,8 +780,6 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, if (i2c == NULL) return NULL; - i2c->dev = dev; - i2c->rec = *rec; /* set the internal bit adapter */ i2c->algo.radeon.bit_adapter.owner = THIS_MODULE; i2c_set_adapdata(&i2c->algo.radeon.bit_adapter, i2c); @@ -223,10 +796,12 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, i2c->algo.radeon.bit_data.data = i2c; ret = i2c_bit_add_bus(&i2c->algo.radeon.bit_adapter); if (ret) { - DRM_INFO("Failed to register internal bit i2c %s\n", name); + DRM_ERROR("Failed to register internal bit i2c %s\n", name); goto out_free; } /* set the radeon i2c adapter */ + i2c->dev = dev; + i2c->rec = *rec; i2c->adapter.owner = THIS_MODULE; i2c_set_adapdata(&i2c->adapter, i2c); sprintf(i2c->adapter.name, "Radeon i2c %s", name); @@ -234,7 +809,7 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, i2c->adapter.algo = &radeon_i2c_algo; ret = i2c_add_adapter(&i2c->adapter); if (ret) { - DRM_INFO("Failed to register i2c %s\n", name); + DRM_ERROR("Failed to register i2c %s\n", name); goto out_free; } diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index 6d0a009dd4a1..b4a06676fff6 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h @@ -1060,32 +1060,38 @@ /* Multimedia I2C bus */ #define RADEON_I2C_CNTL_0 0x0090 -#define RADEON_I2C_DONE (1 << 0) -#define RADEON_I2C_NACK (1 << 1) -#define RADEON_I2C_HALT (1 << 2) -#define RADEON_I2C_SOFT_RST (1 << 5) -#define RADEON_I2C_DRIVE_EN (1 << 6) -#define RADEON_I2C_DRIVE_SEL (1 << 7) -#define RADEON_I2C_START (1 << 8) -#define RADEON_I2C_STOP (1 << 9) -#define RADEON_I2C_RECEIVE (1 << 10) -#define RADEON_I2C_ABORT (1 << 11) -#define RADEON_I2C_GO (1 << 12) -#define RADEON_I2C_PRESCALE_SHIFT 16 +# define RADEON_I2C_DONE (1 << 0) +# define RADEON_I2C_NACK (1 << 1) +# define RADEON_I2C_HALT (1 << 2) +# define RADEON_I2C_SOFT_RST (1 << 5) +# define RADEON_I2C_DRIVE_EN (1 << 6) +# define RADEON_I2C_DRIVE_SEL (1 << 7) +# define RADEON_I2C_START (1 << 8) +# define RADEON_I2C_STOP (1 << 9) +# define RADEON_I2C_RECEIVE (1 << 10) +# define RADEON_I2C_ABORT (1 << 11) +# define RADEON_I2C_GO (1 << 12) +# define RADEON_I2C_PRESCALE_SHIFT 16 #define RADEON_I2C_CNTL_1 0x0094 -#define RADEON_I2C_DATA_COUNT_SHIFT 0 -#define RADEON_I2C_ADDR_COUNT_SHIFT 4 -#define RADEON_I2C_INTRA_BYTE_DELAY_SHIFT 8 -#define RADEON_I2C_SEL (1 << 16) -#define RADEON_I2C_EN (1 << 17) -#define RADEON_I2C_TIME_LIMIT_SHIFT 24 +# define RADEON_I2C_DATA_COUNT_SHIFT 0 +# define RADEON_I2C_ADDR_COUNT_SHIFT 4 +# define RADEON_I2C_INTRA_BYTE_DELAY_SHIFT 8 +# define RADEON_I2C_SEL (1 << 16) +# define RADEON_I2C_EN (1 << 17) +# define RADEON_I2C_TIME_LIMIT_SHIFT 24 #define RADEON_I2C_DATA 0x0098 #define RADEON_DVI_I2C_CNTL_0 0x02e0 # define R200_DVI_I2C_PIN_SEL(x) ((x) << 3) -# define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */ -# define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */ -# define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */ +# define R200_SEL_DDC1 0 /* depends on asic */ +# define R200_SEL_DDC2 1 /* depends on asic */ +# define R200_SEL_DDC3 2 /* depends on asic */ +# define RADEON_SW_WANTS_TO_USE_DVI_I2C (1 << 13) +# define RADEON_SW_CAN_USE_DVI_I2C (1 << 13) +# define RADEON_SW_DONE_USING_DVI_I2C (1 << 14) +# define RADEON_HW_NEEDS_DVI_I2C (1 << 14) +# define RADEON_ABORT_HW_DVI_I2C (1 << 15) +# define RADEON_HW_USING_DVI_I2C (1 << 15) #define RADEON_DVI_I2C_CNTL_1 0x02e4 #define RADEON_DVI_I2C_DATA 0x02e8 -- cgit v1.2.3 From 2739d49cd7f1f44876cad614b072da698967b370 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 5 Feb 2010 03:34:16 -0500 Subject: drm/radeon/kms: add workaround for rn50/rv100 servers Some servers have two VGA ports but only report one in the bios connector tables. On these systems always set up the TV DAC so that it displays properly even if the bios is wrong. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r100.c | 65 +++++++++++++++++++++++++++++ drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 23 ---------- 2 files changed, 65 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index c0d4650cdb79..38209a61e515 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -1800,6 +1800,9 @@ int r100_gpu_reset(struct radeon_device *rdev) void r100_set_common_regs(struct radeon_device *rdev) { + struct drm_device *dev = rdev->ddev; + bool force_dac2 = false; + /* set these so they don't interfere with anything */ WREG32(RADEON_OV0_SCALE_CNTL, 0); WREG32(RADEON_SUBPIC_CNTL, 0); @@ -1808,6 +1811,68 @@ void r100_set_common_regs(struct radeon_device *rdev) WREG32(RADEON_DVI_I2C_CNTL_1, 0); WREG32(RADEON_CAP0_TRIG_CNTL, 0); WREG32(RADEON_CAP1_TRIG_CNTL, 0); + + /* always set up dac2 on rn50 and some rv100 as lots + * of servers seem to wire it up to a VGA port but + * don't report it in the bios connector + * table. + */ + switch (dev->pdev->device) { + /* RN50 */ + case 0x515e: + case 0x5969: + force_dac2 = true; + break; + /* RV100*/ + case 0x5159: + case 0x515a: + /* DELL triple head servers */ + if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && + ((dev->pdev->subsystem_device == 0x016c) || + (dev->pdev->subsystem_device == 0x016d) || + (dev->pdev->subsystem_device == 0x016e) || + (dev->pdev->subsystem_device == 0x016f) || + (dev->pdev->subsystem_device == 0x0170) || + (dev->pdev->subsystem_device == 0x017d) || + (dev->pdev->subsystem_device == 0x017e) || + (dev->pdev->subsystem_device == 0x0183) || + (dev->pdev->subsystem_device == 0x018a) || + (dev->pdev->subsystem_device == 0x019a))) + force_dac2 = true; + break; + } + + if (force_dac2) { + u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); + u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); + u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); + + /* For CRT on DAC2, don't turn it on if BIOS didn't + enable it, even it's detected. + */ + + /* force it to crtc0 */ + dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; + dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; + disp_hw_debug |= RADEON_CRT2_DISP1_SEL; + + /* set up the TV DAC */ + tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | + RADEON_TV_DAC_STD_MASK | + RADEON_TV_DAC_RDACPD | + RADEON_TV_DAC_GDACPD | + RADEON_TV_DAC_BDACPD | + RADEON_TV_DAC_BGADJ_MASK | + RADEON_TV_DAC_DACADJ_MASK); + tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | + RADEON_TV_DAC_NHOLD | + RADEON_TV_DAC_STD_PS2 | + (0x58 << 16)); + + WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); + WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); + WREG32(RADEON_DAC_CNTL2, dac2_cntl); + } } /* diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index b6d8081e1246..d6d69bb2ecea 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c @@ -582,29 +582,6 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod ? RADEON_CRTC_V_SYNC_POL : 0)); - /* TODO -> Dell Server */ - if (0) { - uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); - uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); - uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2); - uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); - - dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; - dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; - - /* For CRT on DAC2, don't turn it on if BIOS didn't - enable it, even it's detected. - */ - disp_hw_debug |= RADEON_CRT2_DISP1_SEL; - tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16)); - tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16)); - - WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); - WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); - WREG32(RADEON_DAC_CNTL2, dac2_cntl); - WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); - } - if (radeon_crtc->crtc_id) { uint32_t crtc2_gen_cntl; uint32_t disp2_merge_cntl; -- cgit v1.2.3 From 3c537889e17232e9073f75ae8710ea0f008c5a29 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 5 Feb 2010 04:21:19 -0500 Subject: drm/radeon/kms: add support for hardcoded edids in rom (v2) Some servers hardcode an edid in rom so that they will work properly with KVMs. This is a port of the relevant code from the ddx. [airlied: reworked to validate edid at boot stage - and remove special quirk, if there is a valid EDID in the BIOS rom we'll just try and use it.] Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/drm_edid.c | 30 +++++++++++++++--------------- drivers/gpu/drm/radeon/radeon_combios.c | 33 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/radeon/radeon_display.c | 14 +++++++++++++- drivers/gpu/drm/radeon/radeon_mode.h | 6 +++++- include/drm/drm_crtc.h | 2 ++ include/drm/drm_edid.h | 3 +++ 6 files changed, 71 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index f665b05592f3..f41e91ceaea6 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -60,8 +60,7 @@ #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) /* use +hsync +vsync for detailed mode */ #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) -/* define the number of Extension EDID block */ -#define MAX_EDID_EXT_NUM 4 + #define LEVEL_DMT 0 #define LEVEL_GTF 1 @@ -114,14 +113,14 @@ static const u8 edid_header[] = { }; /** - * edid_is_valid - sanity check EDID data + * drm_edid_is_valid - sanity check EDID data * @edid: EDID data * * Sanity check the EDID block by looking at the header, the version number * and the checksum. Return 0 if the EDID doesn't check out, or 1 if it's * valid. */ -static bool edid_is_valid(struct edid *edid) +bool drm_edid_is_valid(struct edid *edid) { int i, score = 0; u8 csum = 0; @@ -163,6 +162,7 @@ bad: } return 0; } +EXPORT_SYMBOL(drm_edid_is_valid); /** * edid_vendor - match a string against EDID's obfuscated vendor field @@ -1069,8 +1069,8 @@ static int add_detailed_info_eedid(struct drm_connector *connector, } /* Chose real EDID extension number */ - edid_ext_num = edid->extensions > MAX_EDID_EXT_NUM ? - MAX_EDID_EXT_NUM : edid->extensions; + edid_ext_num = edid->extensions > DRM_MAX_EDID_EXT_NUM ? + DRM_MAX_EDID_EXT_NUM : edid->extensions; /* Find CEA extension */ for (i = 0; i < edid_ext_num; i++) { @@ -1152,7 +1152,7 @@ static int drm_ddc_read_edid(struct drm_connector *connector, for (i = 0; i < 4; i++) { if (drm_do_probe_ddc_edid(adapter, buf, len)) return -1; - if (edid_is_valid((struct edid *)buf)) + if (drm_edid_is_valid((struct edid *)buf)) return 0; } @@ -1177,7 +1177,7 @@ struct edid *drm_get_edid(struct drm_connector *connector, int ret; struct edid *edid; - edid = kmalloc(EDID_LENGTH * (MAX_EDID_EXT_NUM + 1), + edid = kmalloc(EDID_LENGTH * (DRM_MAX_EDID_EXT_NUM + 1), GFP_KERNEL); if (edid == NULL) { dev_warn(&connector->dev->pdev->dev, @@ -1195,14 +1195,14 @@ struct edid *drm_get_edid(struct drm_connector *connector, if (edid->extensions != 0) { int edid_ext_num = edid->extensions; - if (edid_ext_num > MAX_EDID_EXT_NUM) { + if (edid_ext_num > DRM_MAX_EDID_EXT_NUM) { dev_warn(&connector->dev->pdev->dev, "The number of extension(%d) is " "over max (%d), actually read number (%d)\n", - edid_ext_num, MAX_EDID_EXT_NUM, - MAX_EDID_EXT_NUM); + edid_ext_num, DRM_MAX_EDID_EXT_NUM, + DRM_MAX_EDID_EXT_NUM); /* Reset EDID extension number to be read */ - edid_ext_num = MAX_EDID_EXT_NUM; + edid_ext_num = DRM_MAX_EDID_EXT_NUM; } /* Read EDID including extensions too */ ret = drm_ddc_read_edid(connector, adapter, (char *)edid, @@ -1245,8 +1245,8 @@ bool drm_detect_hdmi_monitor(struct edid *edid) goto end; /* Chose real EDID extension number */ - edid_ext_num = edid->extensions > MAX_EDID_EXT_NUM ? - MAX_EDID_EXT_NUM : edid->extensions; + edid_ext_num = edid->extensions > DRM_MAX_EDID_EXT_NUM ? + DRM_MAX_EDID_EXT_NUM : edid->extensions; /* Find CEA extension */ for (i = 0; i < edid_ext_num; i++) { @@ -1303,7 +1303,7 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) if (edid == NULL) { return 0; } - if (!edid_is_valid(edid)) { + if (!drm_edid_is_valid(edid)) { dev_warn(&connector->dev->pdev->dev, "%s: EDID invalid.\n", drm_get_connector_name(connector)); return 0; diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index e208d730f514..257ce1774e40 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -443,6 +443,39 @@ static uint16_t combios_get_table_offset(struct drm_device *dev, } +bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) +{ + int edid_info; + struct edid *edid; + edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); + if (!edid_info) + return false; + + edid = kmalloc(EDID_LENGTH * (DRM_MAX_EDID_EXT_NUM + 1), + GFP_KERNEL); + if (edid == NULL) + return false; + + memcpy((unsigned char *)edid, + (unsigned char *)(rdev->bios + edid_info), EDID_LENGTH); + + if (!drm_edid_is_valid(edid)) { + kfree(edid); + return false; + } + + rdev->mode_info.bios_hardcoded_edid = edid; + return true; +} + +struct edid * +radeon_combios_get_hardcoded_edid(struct radeon_device *rdev) +{ + if (rdev->mode_info.bios_hardcoded_edid) + return rdev->mode_info.bios_hardcoded_edid; + return NULL; +} + static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, int ddc_line) { diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index ec3166bfaa49..79634da7c311 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -352,6 +352,8 @@ static bool radeon_setup_enc_conn(struct drm_device *dev) int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) { + struct drm_device *dev = radeon_connector->base.dev; + struct radeon_device *rdev = dev->dev_private; int ret = 0; if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || @@ -366,7 +368,9 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) if (!radeon_connector->edid) { radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); } - + /* some servers provide a hardcoded edid in rom for KVMs */ + if (!radeon_connector->edid) + radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev); if (radeon_connector->edid) { drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); @@ -829,6 +833,12 @@ int radeon_modeset_init(struct radeon_device *rdev) return ret; } + /* check combios for a valid hardcoded EDID - Sun servers */ + if (!rdev->is_atom_bios) { + /* check for hardcoded EDID in BIOS */ + radeon_combios_check_hardcoded_edid(rdev); + } + if (rdev->flags & RADEON_SINGLE_CRTC) num_crtc = 1; @@ -850,6 +860,8 @@ int radeon_modeset_init(struct radeon_device *rdev) void radeon_modeset_fini(struct radeon_device *rdev) { + kfree(rdev->mode_info.bios_hardcoded_edid); + if (rdev->mode_info.mode_config_initialized) { radeon_hpd_fini(rdev); drm_mode_config_cleanup(rdev->ddev); diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index b884bacf09ff..71439ba2feeb 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -207,7 +207,8 @@ struct radeon_mode_info { struct drm_property *tv_std_property; /* legacy TMDS PLL detect */ struct drm_property *tmds_pll_property; - + /* hardcoded DFP edid from BIOS */ + struct edid *bios_hardcoded_edid; }; #define MAX_H_CODE_TIMING_LEN 32 @@ -479,6 +480,9 @@ extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, int x, int y); +extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); +extern struct edid * +radeon_combios_get_hardcoded_edid(struct radeon_device *rdev); extern bool radeon_atom_get_clock_info(struct drm_device *dev); extern bool radeon_combios_get_clock_info(struct drm_device *dev); extern struct radeon_encoder_atom_dig * diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index fdf43abc36db..1347524a8e30 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -801,4 +801,6 @@ extern struct drm_display_mode *drm_gtf_mode(struct drm_device *dev, bool interlaced, int margins); extern int drm_add_modes_noedid(struct drm_connector *connector, int hdisplay, int vdisplay); + +extern bool drm_edid_is_valid(struct edid *edid); #endif /* __DRM_CRTC_H__ */ diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index d33c3e038606..b4209898f115 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -201,4 +201,7 @@ struct edid { #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) +/* define the number of Extension EDID block */ +#define DRM_MAX_EDID_EXT_NUM 4 + #endif /* __DRM_EDID_H__ */ -- cgit v1.2.3 From 4612dc97991a09e1a9e4d5d981e16589d7cb150c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 5 Feb 2010 01:58:28 -0500 Subject: drm/radeon/kms: clean up some low-hanging magic numbers Switch some magic numbers to their proper defines. The register header madness needs to be cleaned up at some point. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r100.c | 12 ++++++------ drivers/gpu/drm/radeon/r300.c | 38 ++++++++++++++++++++------------------ drivers/gpu/drm/radeon/r420.c | 13 +++++++------ 3 files changed, 33 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 38209a61e515..597f85b283bc 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -366,8 +366,8 @@ void r100_fence_ring_emit(struct radeon_device *rdev, radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL); /* Wait until IDLE & CLEAN */ - radeon_ring_write(rdev, PACKET0(0x1720, 0)); - radeon_ring_write(rdev, (1 << 16) | (1 << 17)); + radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); + radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); radeon_ring_write(rdev, rdev->config.r100.hdp_cntl | RADEON_HDP_READ_BUFFER_INVALIDATE); @@ -1701,7 +1701,7 @@ int r100_gui_wait_for_idle(struct radeon_device *rdev) } for (i = 0; i < rdev->usec_timeout; i++) { tmp = RREG32(RADEON_RBBM_STATUS); - if (!(tmp & (1 << 31))) { + if (!(tmp & RADEON_RBBM_ACTIVE)) { return 0; } DRM_UDELAY(1); @@ -1716,8 +1716,8 @@ int r100_mc_wait_for_idle(struct radeon_device *rdev) for (i = 0; i < rdev->usec_timeout; i++) { /* read MC_STATUS */ - tmp = RREG32(0x0150); - if (tmp & (1 << 2)) { + tmp = RREG32(RADEON_MC_STATUS); + if (tmp & RADEON_MC_IDLE) { return 0; } DRM_UDELAY(1); @@ -1790,7 +1790,7 @@ int r100_gpu_reset(struct radeon_device *rdev) } /* Check if GPU is idle */ status = RREG32(RADEON_RBBM_STATUS); - if (status & (1 << 31)) { + if (status & RADEON_RBBM_ACTIVE) { DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); return -1; } diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 43b55a030b4d..748335c5fa84 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -174,18 +174,20 @@ void r300_fence_ring_emit(struct radeon_device *rdev, /* Who ever call radeon_fence_emit should call ring_lock and ask * for enough space (today caller are ib schedule and buffer move) */ /* Write SC register so SC & US assert idle */ - radeon_ring_write(rdev, PACKET0(0x43E0, 0)); + radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0)); radeon_ring_write(rdev, 0); - radeon_ring_write(rdev, PACKET0(0x43E4, 0)); + radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0)); radeon_ring_write(rdev, 0); /* Flush 3D cache */ - radeon_ring_write(rdev, PACKET0(0x4E4C, 0)); - radeon_ring_write(rdev, (2 << 0)); - radeon_ring_write(rdev, PACKET0(0x4F18, 0)); - radeon_ring_write(rdev, (1 << 0)); + radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); + radeon_ring_write(rdev, R300_RB3D_DC_FLUSH); + radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); + radeon_ring_write(rdev, R300_ZC_FLUSH); /* Wait until IDLE & CLEAN */ - radeon_ring_write(rdev, PACKET0(0x1720, 0)); - radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9)); + radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); + radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN | + RADEON_WAIT_2D_IDLECLEAN | + RADEON_WAIT_DMA_GUI_IDLE)); radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); radeon_ring_write(rdev, rdev->config.r300.hdp_cntl | RADEON_HDP_READ_BUFFER_INVALIDATE); @@ -219,7 +221,7 @@ int r300_copy_dma(struct radeon_device *rdev, } /* Must wait for 2D idle & clean before DMA or hangs might happen */ radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 )); - radeon_ring_write(rdev, (1 << 16)); + radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN); for (i = 0; i < num_loops; i++) { cur_size = size; if (cur_size > 0x1FFFFF) { @@ -281,8 +283,8 @@ void r300_ring_start(struct radeon_device *rdev) radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); - radeon_ring_write(rdev, PACKET0(0x170C, 0)); - radeon_ring_write(rdev, 1 << 31); + radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0)); + radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG); radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); radeon_ring_write(rdev, 0); radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); @@ -349,8 +351,8 @@ int r300_mc_wait_for_idle(struct radeon_device *rdev) for (i = 0; i < rdev->usec_timeout; i++) { /* read MC_STATUS */ - tmp = RREG32(0x0150); - if (tmp & (1 << 4)) { + tmp = RREG32(RADEON_MC_STATUS); + if (tmp & R300_MC_IDLE) { return 0; } DRM_UDELAY(1); @@ -395,8 +397,8 @@ void r300_gpu_init(struct radeon_device *rdev) "programming pipes. Bad things might happen.\n"); } - tmp = RREG32(0x170C); - WREG32(0x170C, tmp | (1 << 31)); + tmp = RREG32(R300_DST_PIPE_CONFIG); + WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); WREG32(R300_RB2D_DSTCACHE_MODE, R300_DC_AUTOFLUSH_ENABLE | @@ -437,8 +439,8 @@ int r300_ga_reset(struct radeon_device *rdev) /* GA still busy soft reset it */ WREG32(0x429C, 0x200); WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0); - WREG32(0x43E0, 0); - WREG32(0x43E4, 0); + WREG32(R300_RE_SCISSORS_TL, 0); + WREG32(R300_RE_SCISSORS_BR, 0); WREG32(0x24AC, 0); } /* Wait to prevent race in RBBM_STATUS */ @@ -488,7 +490,7 @@ int r300_gpu_reset(struct radeon_device *rdev) } /* Check if GPU is idle */ status = RREG32(RADEON_RBBM_STATUS); - if (status & (1 << 31)) { + if (status & RADEON_RBBM_ACTIVE) { DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); return -1; } diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index d9373246c97f..12ebbdb83d1c 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c @@ -69,7 +69,8 @@ void r420_pipes_init(struct radeon_device *rdev) unsigned num_pipes; /* GA_ENHANCE workaround TCL deadlock issue */ - WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)); + WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | + (1 << 2) | (1 << 3)); /* add idle wait as per freedesktop.org bug 24041 */ if (r100_gui_wait_for_idle(rdev)) { printk(KERN_WARNING "Failed to wait GUI idle while " @@ -97,17 +98,17 @@ void r420_pipes_init(struct radeon_device *rdev) tmp = (7 << 1); break; } - WREG32(0x42C8, (1 << num_pipes) - 1); + WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); /* Sub pixel 1/12 so we can have 4K rendering according to doc */ - tmp |= (1 << 4) | (1 << 0); - WREG32(0x4018, tmp); + tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; + WREG32(R300_GB_TILE_CONFIG, tmp); if (r100_gui_wait_for_idle(rdev)) { printk(KERN_WARNING "Failed to wait GUI idle while " "programming pipes. Bad things might happen.\n"); } - tmp = RREG32(0x170C); - WREG32(0x170C, tmp | (1 << 31)); + tmp = RREG32(R300_DST_PIPE_CONFIG); + WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); WREG32(R300_RB2D_DSTCACHE_MODE, RREG32(R300_RB2D_DSTCACHE_MODE) | -- cgit v1.2.3 From 7c27f87d2bde885e9bcda74c208a7aae8bef8e76 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 2 Feb 2010 12:05:01 -0500 Subject: drm/radeon/kms: rework pll algo selection Rework the pll algo selection so that the pll algo in use can be selected more easily. This allows us to select different pll divider selection algos for specific monitors that work better with one algo or the other. This is needed for the next patch which adds an LVDS pll quirk for a specific notebook. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/atombios_crtc.c | 28 ++++++++++------- drivers/gpu/drm/radeon/radeon_atombios.c | 8 +++++ drivers/gpu/drm/radeon/radeon_display.c | 49 ++++++++++++++++++++--------- drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 1 + drivers/gpu/drm/radeon/radeon_mode.h | 18 ++++++----- 5 files changed, 70 insertions(+), 34 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index af464e351fbd..4bae5511ea60 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -424,6 +424,15 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, /* reset the pll flags */ pll->flags = 0; + /* select the PLL algo */ + if (ASIC_IS_AVIVO(rdev)) { + if (radeon_new_pll) + pll->algo = PLL_ALGO_AVIVO; + else + pll->algo = PLL_ALGO_LEGACY; + } else + pll->algo = PLL_ALGO_LEGACY; + if (ASIC_IS_AVIVO(rdev)) { if ((rdev->family == CHIP_RS600) || (rdev->family == CHIP_RS690) || @@ -452,6 +461,11 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) adjusted_clock = mode->clock * 2; + /* LVDS PLL quirks */ + if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { + struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; + pll->algo = dig->pll_algo; + } } else { if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; @@ -550,18 +564,8 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) /* adjust pixel clock as needed */ adjusted_clock = atombios_adjust_pll(crtc, mode, pll); - if (ASIC_IS_AVIVO(rdev)) { - if (radeon_new_pll) - radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, - &fb_div, &frac_fb_div, - &ref_div, &post_div); - else - radeon_compute_pll(pll, adjusted_clock, &pll_clock, - &fb_div, &frac_fb_div, - &ref_div, &post_div); - } else - radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, - &ref_div, &post_div); + radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, + &ref_div, &post_div); index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index fa82ca74324e..667f099e84af 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -1143,6 +1143,14 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id); + if (ASIC_IS_AVIVO(rdev)) { + if (radeon_new_pll) + lvds->pll_algo = PLL_ALGO_AVIVO; + else + lvds->pll_algo = PLL_ALGO_LEGACY; + } else + lvds->pll_algo = PLL_ALGO_LEGACY; + encoder->native_mode = lvds->native_mode; } return lvds; diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 79634da7c311..62fe66c02341 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -405,13 +405,13 @@ static inline uint32_t radeon_div(uint64_t n, uint32_t d) return n; } -void radeon_compute_pll(struct radeon_pll *pll, - uint64_t freq, - uint32_t *dot_clock_p, - uint32_t *fb_div_p, - uint32_t *frac_fb_div_p, - uint32_t *ref_div_p, - uint32_t *post_div_p) +static void radeon_compute_pll_legacy(struct radeon_pll *pll, + uint64_t freq, + uint32_t *dot_clock_p, + uint32_t *fb_div_p, + uint32_t *frac_fb_div_p, + uint32_t *ref_div_p, + uint32_t *post_div_p) { uint32_t min_ref_div = pll->min_ref_div; uint32_t max_ref_div = pll->max_ref_div; @@ -571,13 +571,13 @@ void radeon_compute_pll(struct radeon_pll *pll, *post_div_p = best_post_div; } -void radeon_compute_pll_avivo(struct radeon_pll *pll, - uint64_t freq, - uint32_t *dot_clock_p, - uint32_t *fb_div_p, - uint32_t *frac_fb_div_p, - uint32_t *ref_div_p, - uint32_t *post_div_p) +static void radeon_compute_pll_avivo(struct radeon_pll *pll, + uint64_t freq, + uint32_t *dot_clock_p, + uint32_t *fb_div_p, + uint32_t *frac_fb_div_p, + uint32_t *ref_div_p, + uint32_t *post_div_p) { fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq; fixed20_12 pll_out_max, pll_out_min; @@ -662,6 +662,27 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p); } +void radeon_compute_pll(struct radeon_pll *pll, + uint64_t freq, + uint32_t *dot_clock_p, + uint32_t *fb_div_p, + uint32_t *frac_fb_div_p, + uint32_t *ref_div_p, + uint32_t *post_div_p) +{ + switch (pll->algo) { + case PLL_ALGO_AVIVO: + radeon_compute_pll_avivo(pll, freq, dot_clock_p, fb_div_p, + frac_fb_div_p, ref_div_p, post_div_p); + break; + case PLL_ALGO_LEGACY: + default: + radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p, + frac_fb_div_p, ref_div_p, post_div_p); + break; + } +} + static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) { struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index d6d69bb2ecea..83d4dbd6d067 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c @@ -703,6 +703,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) pll = &rdev->clock.p1pll; pll->flags = RADEON_PLL_LEGACY; + pll->algo = PLL_ALGO_LEGACY; if (mode->clock > 200000) /* range limits??? */ pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 71439ba2feeb..d1e859d1dbf9 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -113,6 +113,7 @@ struct radeon_tmds_pll { #define RADEON_MAX_BIOS_CONNECTOR 16 +/* pll flags */ #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) #define RADEON_PLL_USE_REF_DIV (1 << 2) @@ -127,6 +128,12 @@ struct radeon_tmds_pll { #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) #define RADEON_PLL_USE_POST_DIV (1 << 12) +/* pll algo */ +enum radeon_pll_algo { + PLL_ALGO_LEGACY, + PLL_ALGO_AVIVO +}; + struct radeon_pll { /* reference frequency */ uint32_t reference_freq; @@ -157,6 +164,8 @@ struct radeon_pll { /* pll id */ uint32_t id; + /* pll algo */ + enum radeon_pll_algo algo; }; struct i2c_algo_radeon_data { @@ -309,6 +318,7 @@ struct radeon_encoder_atom_dig { /* atom lvds */ uint32_t lvds_misc; uint16_t panel_pwr_delay; + enum radeon_pll_algo pll_algo; struct radeon_atom_ss *ss; /* panel mode */ struct drm_display_mode native_mode; @@ -439,14 +449,6 @@ extern void radeon_compute_pll(struct radeon_pll *pll, uint32_t *ref_div_p, uint32_t *post_div_p); -extern void radeon_compute_pll_avivo(struct radeon_pll *pll, - uint64_t freq, - uint32_t *dot_clock_p, - uint32_t *fb_div_p, - uint32_t *frac_fb_div_p, - uint32_t *ref_div_p, - uint32_t *post_div_p); - extern void radeon_setup_encoder_clones(struct drm_device *dev); struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); -- cgit v1.2.3 From 093972788f009cabf8f8fb726dc5267b60b3d09e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 2 Feb 2010 12:06:28 -0500 Subject: drm/radeon/kms: add pll quirk for toshiba laptop panel The panel on the Toshiba A300-1BU laptop does not like the PLL dividers selected by the avivo pll algo, but works fine using the older method. Add a quirk to handle it. Should fix fdo bug 26358. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_atombios.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 667f099e84af..d33fb4174b13 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -1073,6 +1073,21 @@ static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct return ss; } +static void radeon_atom_apply_lvds_quirks(struct drm_device *dev, + struct radeon_encoder_atom_dig *lvds) +{ + + /* Toshiba A300-1BU laptop panel doesn't like new pll divider algo */ + if ((dev->pdev->device == 0x95c4) && + (dev->pdev->subsystem_vendor == 0x1179) && + (dev->pdev->subsystem_device == 0xff50)) { + if ((lvds->native_mode.hdisplay == 1280) && + (lvds->native_mode.vdisplay == 800)) + lvds->pll_algo = PLL_ALGO_LEGACY; + } + +} + union lvds_info { struct _ATOM_LVDS_INFO info; struct _ATOM_LVDS_INFO_V12 info_12; @@ -1151,6 +1166,9 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct } else lvds->pll_algo = PLL_ALGO_LEGACY; + /* LVDS quirks */ + radeon_atom_apply_lvds_quirks(dev, lvds); + encoder->native_mode = lvds->native_mode; } return lvds; -- cgit v1.2.3 From 26b9fc3ab13587d4e86b217be43d1fb7ca934576 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 1 Feb 2010 16:39:11 -0500 Subject: drm/radeon/kms/atom: clean up spread spectrum code use a union for the atom args. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/atombios_crtc.c | 38 ++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 4bae5511ea60..bb45517719ae 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -349,6 +349,11 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc, atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); } +union atom_enable_ss { + ENABLE_LVDS_SS_PARAMETERS legacy; + ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; +}; + static void atombios_set_ss(struct drm_crtc *crtc, int enable) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); @@ -358,8 +363,7 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable) struct radeon_encoder *radeon_encoder = NULL; struct radeon_encoder_atom_dig *dig = NULL; int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); - ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION args; - ENABLE_LVDS_SS_PARAMETERS legacy_args; + union atom_enable_ss args; uint16_t percentage = 0; uint8_t type = 0, step = 0, delay = 0, range = 0; @@ -386,25 +390,23 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable) if (!radeon_encoder) return; + memset(&args, 0, sizeof(args)); if (ASIC_IS_AVIVO(rdev)) { - memset(&args, 0, sizeof(args)); - args.usSpreadSpectrumPercentage = cpu_to_le16(percentage); - args.ucSpreadSpectrumType = type; - args.ucSpreadSpectrumStep = step; - args.ucSpreadSpectrumDelay = delay; - args.ucSpreadSpectrumRange = range; - args.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; - args.ucEnable = enable; - atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); + args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage); + args.v1.ucSpreadSpectrumType = type; + args.v1.ucSpreadSpectrumStep = step; + args.v1.ucSpreadSpectrumDelay = delay; + args.v1.ucSpreadSpectrumRange = range; + args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; + args.v1.ucEnable = enable; } else { - memset(&legacy_args, 0, sizeof(legacy_args)); - legacy_args.usSpreadSpectrumPercentage = cpu_to_le16(percentage); - legacy_args.ucSpreadSpectrumType = type; - legacy_args.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2; - legacy_args.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4; - legacy_args.ucEnable = enable; - atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&legacy_args); + args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage); + args.legacy.ucSpreadSpectrumType = type; + args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2; + args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4; + args.legacy.ucEnable = enable; } + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); } union adjust_pixel_clock { -- cgit v1.2.3 From 9ae4786712166638a8daed902886ef400e88ab24 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 1 Feb 2010 19:06:06 -0500 Subject: drm/radeon/kms/atom: add a helper function to get the radeon connector priv This is used in a lot of places in the atom encoder code. While here fix the spelling of crtc_source_params. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_encoders.c | 107 ++++++++++++++----------------- 1 file changed, 48 insertions(+), 59 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index 3c91724457ca..c5ba1e30a43f 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c @@ -228,6 +228,32 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder) return NULL; } +static struct radeon_connector_atom_dig * +radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + struct drm_connector *connector; + struct radeon_connector *radeon_connector; + struct radeon_connector_atom_dig *dig_connector; + + if (!rdev->is_atom_bios) + return NULL; + + connector = radeon_get_connector_for_encoder(encoder); + if (!connector) + return NULL; + + radeon_connector = to_radeon_connector(connector); + + if (!radeon_connector->con_priv) + return NULL; + + dig_connector = radeon_connector->con_priv; + + return dig_connector; +} + static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) @@ -458,34 +484,20 @@ atombios_digital_setup(struct drm_encoder *encoder, int action) struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; + struct radeon_connector_atom_dig *dig_connector = + radeon_get_atom_connector_priv_from_encoder(encoder); union lvds_encoder_control args; int index = 0; int hdmi_detected = 0; uint8_t frev, crev; - struct radeon_encoder_atom_dig *dig; - struct drm_connector *connector; - struct radeon_connector *radeon_connector; - struct radeon_connector_atom_dig *dig_connector; - - connector = radeon_get_connector_for_encoder(encoder); - if (!connector) - return; - - radeon_connector = to_radeon_connector(connector); - if (!radeon_encoder->enc_priv) - return; - - dig = radeon_encoder->enc_priv; - - if (!radeon_connector->con_priv) + if (!dig || !dig_connector) return; - if (drm_detect_hdmi_monitor(radeon_connector->edid)) + if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) hdmi_detected = 1; - dig_connector = radeon_connector->con_priv; - memset(&args, 0, sizeof(args)); switch (radeon_encoder->encoder_id) { @@ -586,7 +598,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) { struct drm_connector *connector; struct radeon_connector *radeon_connector; - struct radeon_connector_atom_dig *radeon_dig_connector; + struct radeon_connector_atom_dig *dig_connector; connector = radeon_get_connector_for_encoder(encoder); if (!connector) @@ -617,9 +629,9 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) break; case DRM_MODE_CONNECTOR_DisplayPort: case DRM_MODE_CONNECTOR_eDP: - radeon_dig_connector = radeon_connector->con_priv; - if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || - (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) + dig_connector = radeon_connector->con_priv; + if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || + (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) return ATOM_ENCODER_MODE_DP; else if (drm_detect_hdmi_monitor(radeon_connector->edid)) return ATOM_ENCODER_MODE_HDMI; @@ -670,30 +682,16 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; + struct radeon_connector_atom_dig *dig_connector = + radeon_get_atom_connector_priv_from_encoder(encoder); DIG_ENCODER_CONTROL_PS_ALLOCATION args; int index = 0, num = 0; uint8_t frev, crev; - struct radeon_encoder_atom_dig *dig; - struct drm_connector *connector; - struct radeon_connector *radeon_connector; - struct radeon_connector_atom_dig *dig_connector; - - connector = radeon_get_connector_for_encoder(encoder); - if (!connector) - return; - - radeon_connector = to_radeon_connector(connector); - - if (!radeon_connector->con_priv) - return; - - dig_connector = radeon_connector->con_priv; - if (!radeon_encoder->enc_priv) + if (!dig || !dig_connector) return; - dig = radeon_encoder->enc_priv; - memset(&args, 0, sizeof(args)); if (dig->dig_encoder) @@ -761,31 +759,22 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; + struct radeon_connector_atom_dig *dig_connector = + radeon_get_atom_connector_priv_from_encoder(encoder); + struct drm_connector *connector; + struct radeon_connector *radeon_connector; union dig_transmitter_control args; int index = 0, num = 0; uint8_t frev, crev; - struct radeon_encoder_atom_dig *dig; - struct drm_connector *connector; - struct radeon_connector *radeon_connector; - struct radeon_connector_atom_dig *dig_connector; bool is_dp = false; - connector = radeon_get_connector_for_encoder(encoder); - if (!connector) + if (!dig || !dig_connector) return; + connector = radeon_get_connector_for_encoder(encoder); radeon_connector = to_radeon_connector(connector); - if (!radeon_encoder->enc_priv) - return; - - dig = radeon_encoder->enc_priv; - - if (!radeon_connector->con_priv) - return; - - dig_connector = radeon_connector->con_priv; - if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) is_dp = true; @@ -1026,7 +1015,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); } -union crtc_sourc_param { +union crtc_source_param { SELECT_CRTC_SOURCE_PS_ALLOCATION v1; SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; }; @@ -1038,7 +1027,7 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) struct radeon_device *rdev = dev->dev_private; struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); - union crtc_sourc_param args; + union crtc_source_param args; int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); uint8_t frev, crev; struct radeon_encoder_atom_dig *dig; -- cgit v1.2.3 From a0c07a69bc5d060362e4861d6c4f7c67dab57f1e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 3 Feb 2010 19:17:14 +1000 Subject: drm/radeon/kms: switch all KMS driver ioctls to unlocked. Internal locking should be sufficent for all these cases. Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_kms.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index f23b05606eb5..3c5002ea3f8f 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c @@ -276,17 +276,17 @@ struct drm_ioctl_desc radeon_ioctls_kms[] = { DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), /* KMS */ - DRM_IOCTL_DEF(DRM_RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), }; int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); -- cgit v1.2.3 From 44224c3f455886190b101dbb00befbaff5e98466 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 4 Feb 2010 11:01:52 -0500 Subject: drm/radeon/kms/r600: reduce gpu cache flushing Only flush the gpu caches before we submit a fence. This leads to a small performance boost when we take the extra gpu cache flushes out of the ddx and mesa. Once this patch is in and the drm version is bumped, we can remove the flushes from the ddx and drm. Also, remove the extra cache flushes from the blit routine. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600.c | 7 +++++++ drivers/gpu/drm/radeon/r600_blit_kms.c | 13 ++----------- drivers/gpu/drm/radeon/r600_blit_shaders.c | 10 ---------- 3 files changed, 9 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 9661a469f3bd..7c32a233b236 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -1783,6 +1783,13 @@ void r600_fence_ring_emit(struct radeon_device *rdev, struct radeon_fence *fence) { /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */ + + radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); + radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); + /* wait for 3D idle clean */ + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); + radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); + radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); /* Emit fence sequence & fire IRQ */ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c index af1c3ca8a4cb..2d7d16e14f9e 100644 --- a/drivers/gpu/drm/radeon/r600_blit_kms.c +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c @@ -403,8 +403,6 @@ set_default_state(struct radeon_device *rdev) radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); radeon_ring_write(rdev, dwords); - radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); - radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); /* SQ config */ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); @@ -581,9 +579,9 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) ring_size = num_loops * dwords_per_loop; /* set default + shaders */ ring_size += 40; /* shaders + def state */ - ring_size += 7; /* fence emit for VB IB */ + ring_size += 12; /* fence emit for VB IB */ ring_size += 5; /* done copy */ - ring_size += 7; /* fence emit for done copy */ + ring_size += 12; /* fence emit for done copy */ r = radeon_ring_lock(rdev, ring_size); if (r) return r; @@ -597,13 +595,6 @@ void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) { int r; - radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); - radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); - /* wait for 3D idle clean */ - radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); - radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); - radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); - if (rdev->r600_blit.vb_ib) r600_vb_ib_put(rdev); diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c index d745e815c2e8..a112c59f9d82 100644 --- a/drivers/gpu/drm/radeon/r600_blit_shaders.c +++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c @@ -9,11 +9,6 @@ const u32 r6xx_default_state[] = 0xc0012800, 0x80000000, 0x80000000, - 0xc0004600, - 0x00000016, - 0xc0016800, - 0x00000010, - 0x00028000, 0xc0016800, 0x00000010, 0x00008000, @@ -531,11 +526,6 @@ const u32 r7xx_default_state[] = 0xc0012800, 0x80000000, 0x80000000, - 0xc0004600, - 0x00000016, - 0xc0016800, - 0x00000010, - 0x00028000, 0xc0016800, 0x00000010, 0x00008000, -- cgit v1.2.3 From 18917b60bca094e7830e4046e336d024f73f1c90 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 1 Feb 2010 16:02:25 -0500 Subject: drm/radeon/kms: consolidate crtc count in rdev Set the number of crtcs in rdev at crtc init and use it whenever we need the crtc count rather than recalculating it everytime. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon.h | 1 + drivers/gpu/drm/radeon/radeon_display.c | 8 +++++--- drivers/gpu/drm/radeon/radeon_fb.c | 7 +------ 3 files changed, 7 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 88113f756ab7..29ae3839c212 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -829,6 +829,7 @@ struct radeon_device { struct r600_ih ih; /* r6/700 interrupt ring */ struct workqueue_struct *wq; struct work_struct hotplug_work; + int num_crtc; /* number of crtcs */ struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ /* audio stuff */ diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 62fe66c02341..a41ed40c13fb 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -831,7 +831,7 @@ static int radeon_modeset_create_props(struct radeon_device *rdev) int radeon_modeset_init(struct radeon_device *rdev) { - int num_crtc = 2, i; + int i; int ret; drm_mode_config_init(rdev->ddev); @@ -861,10 +861,12 @@ int radeon_modeset_init(struct radeon_device *rdev) } if (rdev->flags & RADEON_SINGLE_CRTC) - num_crtc = 1; + rdev->num_crtc = 1; + else + rdev->num_crtc = 2; /* allocate crtcs */ - for (i = 0; i < num_crtc; i++) { + for (i = 0; i < rdev->num_crtc; i++) { radeon_crtc_init(rdev->ddev, i); } diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index 66055b3d8668..105c678fa73a 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -148,7 +148,6 @@ int radeonfb_create(struct drm_device *dev, unsigned long tmp; bool fb_tiled = false; /* useful for testing */ u32 tiling_flags = 0; - int crtc_count; mode_cmd.width = surface_width; mode_cmd.height = surface_height; @@ -239,11 +238,7 @@ int radeonfb_create(struct drm_device *dev, rfbdev = info->par; rfbdev->helper.funcs = &radeon_fb_helper_funcs; rfbdev->helper.dev = dev; - if (rdev->flags & RADEON_SINGLE_CRTC) - crtc_count = 1; - else - crtc_count = 2; - ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, crtc_count, + ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, rdev->num_crtc, RADEONFB_CONN_LIMIT); if (ret) goto out_unref; -- cgit v1.2.3 From c913e23a145ae07b6f9f88aae8cd5ad06b5729ff Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Tue, 22 Dec 2009 23:02:16 +0100 Subject: drm/radeon/kms: add dynamic engine reclocking (V9) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit V2: reorganize functions, fix modesetting calls V3: rebase patch, use radeon's workqueue V4: enable on tested chipsets only, request VBLANK IRQs V5: enable PM on older hardware (IRQs, mode_fixup, dpms) V6: use separate dynpm module parameter V7: drop RADEON_ prefix, set minimum mode for dpms off V8: update legacy encoder call, fix order in rs600 IRQ V9: update compute_clocks call in legacy, not only DPMS_OFF Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r100.c | 4 + drivers/gpu/drm/radeon/r600.c | 4 + drivers/gpu/drm/radeon/radeon.h | 28 +++ drivers/gpu/drm/radeon/radeon_device.c | 1 + drivers/gpu/drm/radeon/radeon_drv.c | 4 + drivers/gpu/drm/radeon/radeon_encoders.c | 6 + drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 20 ++ drivers/gpu/drm/radeon/radeon_pm.c | 241 +++++++++++++++++++++++- drivers/gpu/drm/radeon/rs600.c | 10 +- 9 files changed, 314 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 597f85b283bc..05502bf042b9 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -312,9 +312,13 @@ int r100_irq_process(struct radeon_device *rdev) /* Vertical blank interrupts */ if (status & RADEON_CRTC_VBLANK_STAT) { drm_handle_vblank(rdev->ddev, 0); + if (rdev->pm.vblank_callback) + queue_work(rdev->wq, &rdev->pm.reclock_work); } if (status & RADEON_CRTC2_VBLANK_STAT) { drm_handle_vblank(rdev->ddev, 1); + if (rdev->pm.vblank_callback) + queue_work(rdev->wq, &rdev->pm.reclock_work); } if (status & RADEON_FP_DETECT_STAT) { queue_hotplug = true; diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 7c32a233b236..65daf55af2d9 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -2744,6 +2744,8 @@ restart_ih: case 0: /* D1 vblank */ if (disp_int & LB_D1_VBLANK_INTERRUPT) { drm_handle_vblank(rdev->ddev, 0); + if (rdev->pm.vblank_callback) + queue_work(rdev->wq, &rdev->pm.reclock_work); disp_int &= ~LB_D1_VBLANK_INTERRUPT; DRM_DEBUG("IH: D1 vblank\n"); } @@ -2764,6 +2766,8 @@ restart_ih: case 0: /* D2 vblank */ if (disp_int & LB_D2_VBLANK_INTERRUPT) { drm_handle_vblank(rdev->ddev, 1); + if (rdev->pm.vblank_callback) + queue_work(rdev->wq, &rdev->pm.reclock_work); disp_int &= ~LB_D2_VBLANK_INTERRUPT; DRM_DEBUG("IH: D2 vblank\n"); } diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 29ae3839c212..d7da6e742de8 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -89,6 +89,7 @@ extern int radeon_testing; extern int radeon_connector_table; extern int radeon_tv; extern int radeon_new_pll; +extern int radeon_dynpm; extern int radeon_audio; /* @@ -148,6 +149,7 @@ struct radeon_clock { * Power management */ int radeon_pm_init(struct radeon_device *rdev); +void radeon_pm_compute_clocks(struct radeon_device *rdev); /* * Fences. @@ -569,7 +571,33 @@ struct radeon_wb { * Equation between gpu/memory clock and available bandwidth is hw dependent * (type of memory, bus size, efficiency, ...) */ +enum radeon_pm_state { + PM_STATE_DISABLED, + PM_STATE_MINIMUM, + PM_STATE_PAUSED, + PM_STATE_ACTIVE +}; +enum radeon_pm_action { + PM_ACTION_NONE, + PM_ACTION_MINIMUM, + PM_ACTION_DOWNCLOCK, + PM_ACTION_UPCLOCK +}; struct radeon_pm { + struct mutex mutex; + struct work_struct reclock_work; + struct delayed_work idle_work; + enum radeon_pm_state state; + enum radeon_pm_action planned_action; + unsigned long action_timeout; + bool downclocked; + bool vblank_callback; + int active_crtcs; + int req_vblank; + uint32_t min_gpu_engine_clock; + uint32_t min_gpu_memory_clock; + uint32_t min_mode_engine_clock; + uint32_t min_mode_memory_clock; fixed20_12 max_bandwidth; fixed20_12 igp_sideport_mclk; fixed20_12 igp_system_mclk; diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 18ac29c505cf..a1c937d03845 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -642,6 +642,7 @@ int radeon_device_init(struct radeon_device *rdev, if (rdev->family >= CHIP_R600) spin_lock_init(&rdev->ih.lock); mutex_init(&rdev->gem.mutex); + mutex_init(&rdev->pm.mutex); rwlock_init(&rdev->fence_drv.lock); INIT_LIST_HEAD(&rdev->gem.objects); diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 8ba3de7994d4..a9572e6d4d64 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -87,6 +87,7 @@ int radeon_testing = 0; int radeon_connector_table = 0; int radeon_tv = 1; int radeon_new_pll = 1; +int radeon_dynpm = -1; int radeon_audio = 1; MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); @@ -125,6 +126,9 @@ module_param_named(tv, radeon_tv, int, 0444); MODULE_PARM_DESC(new_pll, "Select new PLL code for AVIVO chips"); module_param_named(new_pll, radeon_new_pll, int, 0444); +MODULE_PARM_DESC(dynpm, "Disable/Enable dynamic power management (1 = enable)"); +module_param_named(dynpm, radeon_dynpm, int, 0444); + MODULE_PARM_DESC(audio, "Audio enable (0 = disable)"); module_param_named(audio, radeon_audio, int, 0444); diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index c5ba1e30a43f..f7d6078876c5 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c @@ -262,6 +262,9 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; + /* adjust pm to upcoming mode change */ + radeon_pm_compute_clocks(rdev); + /* set the active encoder to connector routing */ radeon_encoder_set_active_device(encoder); drm_mode_set_crtcinfo(adjusted_mode, 0); @@ -1013,6 +1016,9 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); } radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); + + /* adjust pm to dpms change */ + radeon_pm_compute_clocks(rdev); } union crtc_source_param { diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c index 38e45e231ef5..cf389ce50a8a 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c @@ -115,6 +115,9 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); else radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); + + /* adjust pm to dpms change */ + radeon_pm_compute_clocks(rdev); } static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder) @@ -214,6 +217,11 @@ static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *adjusted_mode) { struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + + /* adjust pm to upcoming mode change */ + radeon_pm_compute_clocks(rdev); /* set the active encoder to connector routing */ radeon_encoder_set_active_device(encoder); @@ -285,6 +293,9 @@ static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); else radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); + + /* adjust pm to dpms change */ + radeon_pm_compute_clocks(rdev); } static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder) @@ -470,6 +481,9 @@ static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode) radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); else radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); + + /* adjust pm to dpms change */ + radeon_pm_compute_clocks(rdev); } static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder) @@ -635,6 +649,9 @@ static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode) radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); else radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); + + /* adjust pm to dpms change */ + radeon_pm_compute_clocks(rdev); } static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder) @@ -842,6 +859,9 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); else radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); + + /* adjust pm to dpms change */ + radeon_pm_compute_clocks(rdev); } static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder) diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 8bce64cdc320..a9c61f435c06 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -22,17 +22,253 @@ #include "drmP.h" #include "radeon.h" -int radeon_debugfs_pm_init(struct radeon_device *rdev); +#define RADEON_IDLE_LOOP_MS 100 +#define RADEON_RECLOCK_DELAY_MS 200 + +static void radeon_pm_check_limits(struct radeon_device *rdev); +static void radeon_pm_set_clocks_locked(struct radeon_device *rdev); +static void radeon_pm_set_clocks(struct radeon_device *rdev); +static void radeon_pm_reclock_work_handler(struct work_struct *work); +static void radeon_pm_idle_work_handler(struct work_struct *work); +static int radeon_debugfs_pm_init(struct radeon_device *rdev); + +static const char *pm_state_names[4] = { + "PM_STATE_DISABLED", + "PM_STATE_MINIMUM", + "PM_STATE_PAUSED", + "PM_STATE_ACTIVE" +}; int radeon_pm_init(struct radeon_device *rdev) { + rdev->pm.state = PM_STATE_DISABLED; + rdev->pm.planned_action = PM_ACTION_NONE; + rdev->pm.downclocked = false; + rdev->pm.vblank_callback = false; + + radeon_pm_check_limits(rdev); + if (radeon_debugfs_pm_init(rdev)) { DRM_ERROR("Failed to register debugfs file for PM!\n"); } + INIT_WORK(&rdev->pm.reclock_work, radeon_pm_reclock_work_handler); + INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler); + + if (radeon_dynpm != -1 && radeon_dynpm) { + rdev->pm.state = PM_STATE_PAUSED; + DRM_INFO("radeon: dynamic power management enabled\n"); + } + + DRM_INFO("radeon: power management initialized\n"); + return 0; } +static void radeon_pm_check_limits(struct radeon_device *rdev) +{ + rdev->pm.min_gpu_engine_clock = rdev->clock.default_sclk - 5000; + rdev->pm.min_gpu_memory_clock = rdev->clock.default_mclk - 5000; +} + +void radeon_pm_compute_clocks(struct radeon_device *rdev) +{ + struct drm_device *ddev = rdev->ddev; + struct drm_connector *connector; + struct radeon_crtc *radeon_crtc; + int count = 0; + + if (rdev->pm.state == PM_STATE_DISABLED) + return; + + mutex_lock(&rdev->pm.mutex); + + rdev->pm.active_crtcs = 0; + list_for_each_entry(connector, + &ddev->mode_config.connector_list, head) { + if (connector->encoder && + connector->dpms != DRM_MODE_DPMS_OFF) { + radeon_crtc = to_radeon_crtc(connector->encoder->crtc); + rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); + ++count; + } + } + + if (count > 1) { + if (rdev->pm.state == PM_STATE_ACTIVE) { + wait_queue_head_t wait; + init_waitqueue_head(&wait); + + cancel_delayed_work(&rdev->pm.idle_work); + + rdev->pm.state = PM_STATE_PAUSED; + rdev->pm.planned_action = PM_ACTION_UPCLOCK; + rdev->pm.vblank_callback = true; + + mutex_unlock(&rdev->pm.mutex); + + wait_event_timeout(wait, !rdev->pm.downclocked, + msecs_to_jiffies(300)); + if (!rdev->pm.downclocked) + radeon_pm_set_clocks(rdev); + + DRM_DEBUG("radeon: dynamic power management deactivated\n"); + } else { + mutex_unlock(&rdev->pm.mutex); + } + } else if (count == 1) { + rdev->pm.min_mode_engine_clock = rdev->pm.min_gpu_engine_clock; + rdev->pm.min_mode_memory_clock = rdev->pm.min_gpu_memory_clock; + /* TODO: Increase clocks if needed for current mode */ + + if (rdev->pm.state == PM_STATE_MINIMUM) { + rdev->pm.state = PM_STATE_ACTIVE; + rdev->pm.planned_action = PM_ACTION_UPCLOCK; + radeon_pm_set_clocks_locked(rdev); + + queue_delayed_work(rdev->wq, &rdev->pm.idle_work, + msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); + } + else if (rdev->pm.state == PM_STATE_PAUSED) { + rdev->pm.state = PM_STATE_ACTIVE; + queue_delayed_work(rdev->wq, &rdev->pm.idle_work, + msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); + DRM_DEBUG("radeon: dynamic power management activated\n"); + } + + mutex_unlock(&rdev->pm.mutex); + } + else { /* count == 0 */ + if (rdev->pm.state != PM_STATE_MINIMUM) { + cancel_delayed_work(&rdev->pm.idle_work); + + rdev->pm.state = PM_STATE_MINIMUM; + rdev->pm.planned_action = PM_ACTION_MINIMUM; + radeon_pm_set_clocks_locked(rdev); + } + + mutex_unlock(&rdev->pm.mutex); + } +} + +static void radeon_pm_set_clocks_locked(struct radeon_device *rdev) +{ + /*radeon_fence_wait_last(rdev);*/ + switch (rdev->pm.planned_action) { + case PM_ACTION_UPCLOCK: + radeon_set_engine_clock(rdev, rdev->clock.default_sclk); + rdev->pm.downclocked = false; + break; + case PM_ACTION_DOWNCLOCK: + radeon_set_engine_clock(rdev, + rdev->pm.min_mode_engine_clock); + rdev->pm.downclocked = true; + break; + case PM_ACTION_MINIMUM: + radeon_set_engine_clock(rdev, + rdev->pm.min_gpu_engine_clock); + break; + case PM_ACTION_NONE: + DRM_ERROR("%s: PM_ACTION_NONE\n", __func__); + break; + } + + rdev->pm.planned_action = PM_ACTION_NONE; +} + +static void radeon_pm_set_clocks(struct radeon_device *rdev) +{ + mutex_lock(&rdev->pm.mutex); + /* new VBLANK irq may come before handling previous one */ + if (rdev->pm.vblank_callback) { + mutex_lock(&rdev->cp.mutex); + if (rdev->pm.req_vblank & (1 << 0)) { + rdev->pm.req_vblank &= ~(1 << 0); + drm_vblank_put(rdev->ddev, 0); + } + if (rdev->pm.req_vblank & (1 << 1)) { + rdev->pm.req_vblank &= ~(1 << 1); + drm_vblank_put(rdev->ddev, 1); + } + rdev->pm.vblank_callback = false; + radeon_pm_set_clocks_locked(rdev); + mutex_unlock(&rdev->cp.mutex); + } + mutex_unlock(&rdev->pm.mutex); +} + +static void radeon_pm_reclock_work_handler(struct work_struct *work) +{ + struct radeon_device *rdev; + rdev = container_of(work, struct radeon_device, + pm.reclock_work); + radeon_pm_set_clocks(rdev); +} + +static void radeon_pm_idle_work_handler(struct work_struct *work) +{ + struct radeon_device *rdev; + rdev = container_of(work, struct radeon_device, + pm.idle_work.work); + + mutex_lock(&rdev->pm.mutex); + if (rdev->pm.state == PM_STATE_ACTIVE && + !rdev->pm.vblank_callback) { + unsigned long irq_flags; + int not_processed = 0; + + read_lock_irqsave(&rdev->fence_drv.lock, irq_flags); + if (!list_empty(&rdev->fence_drv.emited)) { + struct list_head *ptr; + list_for_each(ptr, &rdev->fence_drv.emited) { + /* count up to 3, that's enought info */ + if (++not_processed >= 3) + break; + } + } + read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); + + if (not_processed >= 3) { /* should upclock */ + if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) { + rdev->pm.planned_action = PM_ACTION_NONE; + } else if (rdev->pm.planned_action == PM_ACTION_NONE && + rdev->pm.downclocked) { + rdev->pm.planned_action = + PM_ACTION_UPCLOCK; + rdev->pm.action_timeout = jiffies + + msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); + } + } else if (not_processed == 0) { /* should downclock */ + if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) { + rdev->pm.planned_action = PM_ACTION_NONE; + } else if (rdev->pm.planned_action == PM_ACTION_NONE && + !rdev->pm.downclocked) { + rdev->pm.planned_action = + PM_ACTION_DOWNCLOCK; + rdev->pm.action_timeout = jiffies + + msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); + } + } + + if (rdev->pm.planned_action != PM_ACTION_NONE && + jiffies > rdev->pm.action_timeout) { + if (rdev->pm.active_crtcs & (1 << 0)) { + rdev->pm.req_vblank |= (1 << 0); + drm_vblank_get(rdev->ddev, 0); + } + if (rdev->pm.active_crtcs & (1 << 1)) { + rdev->pm.req_vblank |= (1 << 1); + drm_vblank_get(rdev->ddev, 1); + } + rdev->pm.vblank_callback = true; + } + } + mutex_unlock(&rdev->pm.mutex); + + queue_delayed_work(rdev->wq, &rdev->pm.idle_work, + msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); +} + /* * Debugfs info */ @@ -44,6 +280,7 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data) struct drm_device *dev = node->minor->dev; struct radeon_device *rdev = dev->dev_private; + seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]); seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk); seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk); @@ -58,7 +295,7 @@ static struct drm_info_list radeon_pm_info_list[] = { }; #endif -int radeon_debugfs_pm_init(struct radeon_device *rdev) +static int radeon_debugfs_pm_init(struct radeon_device *rdev) { #if defined(CONFIG_DEBUG_FS) return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index c3818562a13e..a581fdead4dd 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c @@ -406,10 +406,16 @@ int rs600_irq_process(struct radeon_device *rdev) if (G_000044_SW_INT(status)) radeon_fence_process(rdev); /* Vertical blank interrupts */ - if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) + if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) { drm_handle_vblank(rdev->ddev, 0); - if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) + if (rdev->pm.vblank_callback) + queue_work(rdev->wq, &rdev->pm.reclock_work); + } + if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) { drm_handle_vblank(rdev->ddev, 1); + if (rdev->pm.vblank_callback) + queue_work(rdev->wq, &rdev->pm.reclock_work); + } if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) { queue_hotplug = true; DRM_DEBUG("HPD1\n"); -- cgit v1.2.3 From c836a4126768cd76af9ee33b3c11f57695d5fda6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 23 Dec 2009 10:07:50 -0500 Subject: drm/radeon/kms: add functions to get current pcie lanes Currently unused. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r300.c | 31 +++++++++++++++++++++++++++++++ drivers/gpu/drm/radeon/radeon.h | 2 ++ drivers/gpu/drm/radeon/radeon_asic.h | 11 +++++++++++ 3 files changed, 44 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 748335c5fa84..5897bd00591e 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -580,6 +580,37 @@ void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) } +int rv370_get_pcie_lanes(struct radeon_device *rdev) +{ + u32 link_width_cntl; + + if (rdev->flags & RADEON_IS_IGP) + return 0; + + if (!(rdev->flags & RADEON_IS_PCIE)) + return 0; + + /* FIXME wait for idle */ + + link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); + + switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { + case RADEON_PCIE_LC_LINK_WIDTH_X0: + return 0; + case RADEON_PCIE_LC_LINK_WIDTH_X1: + return 1; + case RADEON_PCIE_LC_LINK_WIDTH_X2: + return 2; + case RADEON_PCIE_LC_LINK_WIDTH_X4: + return 4; + case RADEON_PCIE_LC_LINK_WIDTH_X8: + return 8; + case RADEON_PCIE_LC_LINK_WIDTH_X16: + default: + return 16; + } +} + #if defined(CONFIG_DEBUG_FS) static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) { diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index d7da6e742de8..df21edcbae16 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -678,6 +678,7 @@ struct radeon_asic { void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); uint32_t (*get_memory_clock)(struct radeon_device *rdev); void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); + int (*get_pcie_lanes)(struct radeon_device *rdev); void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); void (*set_clock_gating)(struct radeon_device *rdev, int enable); int (*set_surface_reg)(struct radeon_device *rdev, int reg, @@ -1044,6 +1045,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) +#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 05ee1aeac3fd..d758b1ffb74c 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -108,6 +108,7 @@ static struct radeon_asic r100_asic = { .set_engine_clock = &radeon_legacy_set_engine_clock, .get_memory_clock = &radeon_legacy_get_memory_clock, .set_memory_clock = NULL, + .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = &radeon_legacy_set_clock_gating, .set_surface_reg = r100_set_surface_reg, @@ -138,6 +139,7 @@ extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); +extern int rv370_get_pcie_lanes(struct radeon_device *rdev); extern int r300_copy_dma(struct radeon_device *rdev, uint64_t src_offset, uint64_t dst_offset, @@ -168,6 +170,7 @@ static struct radeon_asic r300_asic = { .set_engine_clock = &radeon_legacy_set_engine_clock, .get_memory_clock = &radeon_legacy_get_memory_clock, .set_memory_clock = NULL, + .get_pcie_lanes = &rv370_get_pcie_lanes, .set_pcie_lanes = &rv370_set_pcie_lanes, .set_clock_gating = &radeon_legacy_set_clock_gating, .set_surface_reg = r100_set_surface_reg, @@ -212,6 +215,7 @@ static struct radeon_asic r420_asic = { .set_engine_clock = &radeon_atom_set_engine_clock, .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, + .get_pcie_lanes = &rv370_get_pcie_lanes, .set_pcie_lanes = &rv370_set_pcie_lanes, .set_clock_gating = &radeon_atom_set_clock_gating, .set_surface_reg = r100_set_surface_reg, @@ -261,6 +265,7 @@ static struct radeon_asic rs400_asic = { .set_engine_clock = &radeon_legacy_set_engine_clock, .get_memory_clock = &radeon_legacy_get_memory_clock, .set_memory_clock = NULL, + .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = &radeon_legacy_set_clock_gating, .set_surface_reg = r100_set_surface_reg, @@ -320,6 +325,7 @@ static struct radeon_asic rs600_asic = { .set_engine_clock = &radeon_atom_set_engine_clock, .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, + .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = &radeon_atom_set_clock_gating, .bandwidth_update = &rs600_bandwidth_update, @@ -366,6 +372,7 @@ static struct radeon_asic rs690_asic = { .set_engine_clock = &radeon_atom_set_engine_clock, .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, + .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = &radeon_atom_set_clock_gating, .set_surface_reg = r100_set_surface_reg, @@ -418,6 +425,7 @@ static struct radeon_asic rv515_asic = { .set_engine_clock = &radeon_atom_set_engine_clock, .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, + .get_pcie_lanes = &rv370_get_pcie_lanes, .set_pcie_lanes = &rv370_set_pcie_lanes, .set_clock_gating = &radeon_atom_set_clock_gating, .set_surface_reg = r100_set_surface_reg, @@ -461,6 +469,7 @@ static struct radeon_asic r520_asic = { .set_engine_clock = &radeon_atom_set_engine_clock, .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, + .get_pcie_lanes = &rv370_get_pcie_lanes, .set_pcie_lanes = &rv370_set_pcie_lanes, .set_clock_gating = &radeon_atom_set_clock_gating, .set_surface_reg = r100_set_surface_reg, @@ -538,6 +547,7 @@ static struct radeon_asic r600_asic = { .set_engine_clock = &radeon_atom_set_engine_clock, .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, + .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = &radeon_atom_set_clock_gating, .set_surface_reg = r600_set_surface_reg, @@ -583,6 +593,7 @@ static struct radeon_asic rv770_asic = { .set_engine_clock = &radeon_atom_set_engine_clock, .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, + .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = &radeon_atom_set_clock_gating, .set_surface_reg = r600_set_surface_reg, -- cgit v1.2.3 From 56278a8edacee9ae9e3bc9d8c8e2d37e9969f3eb Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 28 Dec 2009 13:58:44 -0500 Subject: drm/radeon/kms: pull power mode info from bios tables (v3) The general idea is to validate the current hw state against the set of power states and select a power state based on that. This patch just pulls the power states from the bios and prints the information. It is not currently hooked up in the actual power management code. Hooking it up will require reworking the the current power state selection code and will be handled in a future patch. Additionally, we'd need to decide on some default lower power states for cards without power tables. v2 - increment state_index after checking for default state v3 - fix typo in pm init on pre-atom cards, handle pre-atom cards without x86 bioses Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon.h | 61 +++++++ drivers/gpu/drm/radeon/radeon_atombios.c | 299 +++++++++++++++++++++++++++++++ drivers/gpu/drm/radeon/radeon_combios.c | 108 +++++++++++ drivers/gpu/drm/radeon/radeon_pm.c | 38 ++++ 4 files changed, 506 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index df21edcbae16..d73d37d5effd 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -150,6 +150,8 @@ struct radeon_clock { */ int radeon_pm_init(struct radeon_device *rdev); void radeon_pm_compute_clocks(struct radeon_device *rdev); +void radeon_combios_get_power_modes(struct radeon_device *rdev); +void radeon_atombios_get_power_modes(struct radeon_device *rdev); /* * Fences. @@ -583,6 +585,59 @@ enum radeon_pm_action { PM_ACTION_DOWNCLOCK, PM_ACTION_UPCLOCK }; + +enum radeon_voltage_type { + VOLTAGE_NONE = 0, + VOLTAGE_GPIO, + VOLTAGE_VDDC, + VOLTAGE_SW +}; + +struct radeon_voltage { + enum radeon_voltage_type type; + /* gpio voltage */ + struct radeon_gpio_rec gpio; + u32 delay; /* delay in usec from voltage drop to sclk change */ + bool active_high; /* voltage drop is active when bit is high */ + /* VDDC voltage */ + u8 vddc_id; /* index into vddc voltage table */ + u8 vddci_id; /* index into vddci voltage table */ + bool vddci_enabled; + /* r6xx+ sw */ + u32 voltage; +}; + +struct radeon_pm_non_clock_info { + /* pcie lanes */ + int pcie_lanes; + /* standardized non-clock flags */ + u32 flags; +}; + +struct radeon_pm_clock_info { + /* memory clock */ + u32 mclk; + /* engine clock */ + u32 sclk; + /* voltage info */ + struct radeon_voltage voltage; + /* standardized clock flags - not sure we'll need these */ + u32 flags; +}; + +struct radeon_power_state { + /* XXX: use a define for num clock modes */ + struct radeon_pm_clock_info clock_info[8]; + /* number of valid clock modes in this power state */ + int num_clock_modes; + /* currently selected clock mode */ + struct radeon_pm_clock_info *current_clock_mode; + struct radeon_pm_clock_info *default_clock_mode; + /* non clock info about this state */ + struct radeon_pm_non_clock_info non_clock_info; + bool voltage_drop_active; +}; + struct radeon_pm { struct mutex mutex; struct work_struct reclock_work; @@ -609,6 +664,12 @@ struct radeon_pm { fixed20_12 core_bandwidth; fixed20_12 sclk; fixed20_12 needed_bandwidth; + /* XXX: use a define for num power modes */ + struct radeon_power_state power_state[8]; + /* number of valid power states */ + int num_power_states; + struct radeon_power_state *current_power_state; + struct radeon_power_state *default_power_state; }; diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index d33fb4174b13..adf900e368ac 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -1393,6 +1393,305 @@ radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) return tv_dac; } +union power_info { + struct _ATOM_POWERPLAY_INFO info; + struct _ATOM_POWERPLAY_INFO_V2 info_2; + struct _ATOM_POWERPLAY_INFO_V3 info_3; + struct _ATOM_PPLIB_POWERPLAYTABLE info_4; +}; + +void radeon_atombios_get_power_modes(struct radeon_device *rdev) +{ + struct radeon_mode_info *mode_info = &rdev->mode_info; + int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); + u16 data_offset; + u8 frev, crev; + u32 misc, misc2 = 0, sclk, mclk; + union power_info *power_info; + struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; + struct _ATOM_PPLIB_STATE *power_state; + int num_modes = 0, i, j; + int state_index = 0, mode_index = 0; + + atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); + + power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); + + rdev->pm.default_power_state = NULL; + rdev->pm.current_power_state = NULL; + + if (power_info) { + if (frev < 4) { + num_modes = power_info->info.ucNumOfPowerModeEntries; + if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) + num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; + for (i = 0; i < num_modes; i++) { + rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; + switch (frev) { + case 1: + rdev->pm.power_state[state_index].num_clock_modes = 1; + rdev->pm.power_state[state_index].clock_info[0].mclk = + le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); + rdev->pm.power_state[state_index].clock_info[0].sclk = + le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); + /* skip invalid modes */ + if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || + (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) + continue; + /* skip overclock modes for now */ + if ((rdev->pm.power_state[state_index].clock_info[0].mclk > + rdev->clock.default_mclk) || + (rdev->pm.power_state[state_index].clock_info[0].sclk > + rdev->clock.default_sclk)) + continue; + rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = + power_info->info.asPowerPlayInfo[i].ucNumPciELanes; + misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); + if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { + rdev->pm.power_state[state_index].clock_info[0].voltage.type = + VOLTAGE_GPIO; + rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = + radeon_lookup_gpio(rdev, + power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); + if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) + rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = + true; + else + rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = + false; + } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { + rdev->pm.power_state[state_index].clock_info[0].voltage.type = + VOLTAGE_VDDC; + rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = + power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; + } + if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { + rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; + rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; + rdev->pm.power_state[state_index].default_clock_mode = + &rdev->pm.power_state[state_index].clock_info[0]; + rdev->pm.power_state[state_index].current_clock_mode = + &rdev->pm.power_state[state_index].clock_info[0]; + } + state_index++; + break; + case 2: + rdev->pm.power_state[state_index].num_clock_modes = 1; + rdev->pm.power_state[state_index].clock_info[0].mclk = + le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); + rdev->pm.power_state[state_index].clock_info[0].sclk = + le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); + /* skip invalid modes */ + if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || + (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) + continue; + /* skip overclock modes for now */ + if ((rdev->pm.power_state[state_index].clock_info[0].mclk > + rdev->clock.default_mclk) || + (rdev->pm.power_state[state_index].clock_info[0].sclk > + rdev->clock.default_sclk)) + continue; + rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = + power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; + misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); + misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); + if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { + rdev->pm.power_state[state_index].clock_info[0].voltage.type = + VOLTAGE_GPIO; + rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = + radeon_lookup_gpio(rdev, + power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); + if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) + rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = + true; + else + rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = + false; + } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { + rdev->pm.power_state[state_index].clock_info[0].voltage.type = + VOLTAGE_VDDC; + rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = + power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; + } + if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { + rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; + rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; + rdev->pm.power_state[state_index].default_clock_mode = + &rdev->pm.power_state[state_index].clock_info[0]; + rdev->pm.power_state[state_index].current_clock_mode = + &rdev->pm.power_state[state_index].clock_info[0]; + } + state_index++; + break; + case 3: + rdev->pm.power_state[state_index].num_clock_modes = 1; + rdev->pm.power_state[state_index].clock_info[0].mclk = + le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); + rdev->pm.power_state[state_index].clock_info[0].sclk = + le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); + /* skip invalid modes */ + if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || + (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) + continue; + /* skip overclock modes for now */ + if ((rdev->pm.power_state[state_index].clock_info[0].mclk > + rdev->clock.default_mclk) || + (rdev->pm.power_state[state_index].clock_info[0].sclk > + rdev->clock.default_sclk)) + continue; + rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = + power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; + misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); + misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); + if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { + rdev->pm.power_state[state_index].clock_info[0].voltage.type = + VOLTAGE_GPIO; + rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = + radeon_lookup_gpio(rdev, + power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); + if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) + rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = + true; + else + rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = + false; + } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { + rdev->pm.power_state[state_index].clock_info[0].voltage.type = + VOLTAGE_VDDC; + rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = + power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; + if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { + rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = + true; + rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = + power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; + } + } + if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { + rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; + rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; + rdev->pm.power_state[state_index].default_clock_mode = + &rdev->pm.power_state[state_index].clock_info[0]; + rdev->pm.power_state[state_index].current_clock_mode = + &rdev->pm.power_state[state_index].clock_info[0]; + } + state_index++; + break; + } + } + } else if (frev == 4) { + for (i = 0; i < power_info->info_4.ucNumStates; i++) { + mode_index = 0; + power_state = (struct _ATOM_PPLIB_STATE *) + (mode_info->atom_context->bios + + data_offset + + le16_to_cpu(power_info->info_4.usStateArrayOffset) + + i * power_info->info_4.ucStateEntrySize); + non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) + (mode_info->atom_context->bios + + data_offset + + le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) + + (power_state->ucNonClockStateIndex * + power_info->info_4.ucNonClockSize)); + misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); + rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = + ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> + ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; + for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) { + if (rdev->flags & RADEON_IS_IGP) { + struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info = + (struct _ATOM_PPLIB_RS780_CLOCK_INFO *) + (mode_info->atom_context->bios + + data_offset + + le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) + + (power_state->ucClockStateIndices[j] * + power_info->info_4.ucClockInfoSize)); + sclk = le16_to_cpu(clock_info->usLowEngineClockLow); + sclk |= clock_info->ucLowEngineClockHigh << 16; + rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; + /* skip invalid modes */ + if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) + continue; + /* skip overclock modes for now */ + if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk > + rdev->clock.default_sclk) + continue; + rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = + VOLTAGE_SW; + rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = + clock_info->usVDDC; + mode_index++; + } else { + struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info = + (struct _ATOM_PPLIB_R600_CLOCK_INFO *) + (mode_info->atom_context->bios + + data_offset + + le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) + + (power_state->ucClockStateIndices[j] * + power_info->info_4.ucClockInfoSize)); + sclk = le16_to_cpu(clock_info->usEngineClockLow); + sclk |= clock_info->ucEngineClockHigh << 16; + mclk = le16_to_cpu(clock_info->usMemoryClockLow); + mclk |= clock_info->ucMemoryClockHigh << 16; + rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; + rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; + /* skip invalid modes */ + if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || + (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) + continue; + /* skip overclock modes for now */ + if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk > + rdev->clock.default_mclk) || + (rdev->pm.power_state[state_index].clock_info[mode_index].sclk > + rdev->clock.default_sclk)) + continue; + rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = + VOLTAGE_SW; + rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = + clock_info->usVDDC; + mode_index++; + } + } + rdev->pm.power_state[state_index].num_clock_modes = mode_index; + if (mode_index) { + misc2 = le16_to_cpu(non_clock_info->usClassification); + if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { + rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; + rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; + rdev->pm.power_state[state_index].default_clock_mode = + &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; + rdev->pm.power_state[state_index].current_clock_mode = + &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; + } + state_index++; + } + } + } + } else { + /* XXX figure out some good default low power mode for cards w/out power tables */ + } + + if (rdev->pm.default_power_state == NULL) { + /* add the default mode */ + rdev->pm.power_state[state_index].num_clock_modes = 1; + rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; + rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; + rdev->pm.power_state[state_index].default_clock_mode = + &rdev->pm.power_state[state_index].clock_info[0]; + rdev->pm.power_state[state_index].current_clock_mode = + &rdev->pm.power_state[state_index].clock_info[0]; + rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; + if (rdev->asic->get_pcie_lanes) + rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); + else + rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; + rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; + rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; + state_index++; + } + rdev->pm.num_power_states = state_index; +} + void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) { DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index 257ce1774e40..eac2174abc5b 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -2374,6 +2374,114 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) return true; } +void radeon_combios_get_power_modes(struct radeon_device *rdev) +{ + struct drm_device *dev = rdev->ddev; + u16 offset, misc, misc2 = 0; + u8 rev, blocks, tmp; + int state_index = 0; + + rdev->pm.default_power_state = NULL; + rdev->pm.current_power_state = NULL; + + /* XXX mac/sparc cards */ + if (rdev->bios == NULL) + goto default_mode; + + if (rdev->flags & RADEON_IS_MOBILITY) { + offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); + if (offset) { + rev = RBIOS8(offset); + blocks = RBIOS8(offset + 0x2); + /* power mode 0 tends to be the only valid one */ + rdev->pm.power_state[state_index].num_clock_modes = 1; + rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); + rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); + if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || + (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) + goto default_mode; + /* skip overclock modes for now */ + if ((rdev->pm.power_state[state_index].clock_info[0].mclk > + rdev->clock.default_mclk) || + (rdev->pm.power_state[state_index].clock_info[0].sclk > + rdev->clock.default_sclk)) + goto default_mode; + misc = RBIOS16(offset + 0x5 + 0x0); + if (rev > 4) + misc2 = RBIOS16(offset + 0x5 + 0xe); + if (misc & 0x4) { + rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; + if (misc & 0x8) + rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = + true; + else + rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = + false; + rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; + if (rev < 6) { + rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = + RBIOS16(offset + 0x5 + 0xb) * 4; + tmp = RBIOS8(offset + 0x5 + 0xd); + rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); + } else { + u8 entries = RBIOS8(offset + 0x5 + 0xb); + u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); + if (entries && voltage_table_offset) { + rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = + RBIOS16(voltage_table_offset) * 4; + tmp = RBIOS8(voltage_table_offset + 0x2); + rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); + } else + rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; + } + switch ((misc2 & 0x700) >> 8) { + case 0: + default: + rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; + break; + case 1: + rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; + break; + case 2: + rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; + break; + case 3: + rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; + break; + case 4: + rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; + break; + } + } else + rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; + if (rev > 6) + rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = + RBIOS8(offset + 0x5 + 0x10); + state_index++; + } else { + /* XXX figure out some good default low power mode for mobility cards w/out power tables */ + } + } else { + /* XXX figure out some good default low power mode for desktop cards */ + } + +default_mode: + /* add the default mode */ + rdev->pm.power_state[state_index].num_clock_modes = 1; + rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; + rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; + rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; + rdev->pm.power_state[state_index].current_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; + rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; + if (rdev->asic->get_pcie_lanes) + rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); + else + rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; + rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; + rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; + rdev->pm.num_power_states = state_index + 1; +} + void radeon_external_tmds_setup(struct drm_encoder *encoder) { struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index a9c61f435c06..6eb0e0b3264b 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -18,6 +18,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * * Authors: RafaÅ‚ MiÅ‚ecki + * Alex Deucher */ #include "drmP.h" #include "radeon.h" @@ -39,6 +40,35 @@ static const char *pm_state_names[4] = { "PM_STATE_ACTIVE" }; +static void radeon_print_power_mode_info(struct radeon_device *rdev) +{ + int i, j; + bool is_default; + + DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states); + for (i = 0; i < rdev->pm.num_power_states; i++) { + if (rdev->pm.default_power_state == &rdev->pm.power_state[i]) + is_default = true; + else + is_default = false; + DRM_INFO("State %d %s\n", i, is_default ? "(default)" : ""); + if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) + DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes); + DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes); + for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) { + if (rdev->flags & RADEON_IS_IGP) + DRM_INFO("\t\t%d engine: %d\n", + j, + rdev->pm.power_state[i].clock_info[j].sclk * 10); + else + DRM_INFO("\t\t%d engine/memory: %d/%d\n", + j, + rdev->pm.power_state[i].clock_info[j].sclk * 10, + rdev->pm.power_state[i].clock_info[j].mclk * 10); + } + } +} + int radeon_pm_init(struct radeon_device *rdev) { rdev->pm.state = PM_STATE_DISABLED; @@ -46,6 +76,14 @@ int radeon_pm_init(struct radeon_device *rdev) rdev->pm.downclocked = false; rdev->pm.vblank_callback = false; + if (rdev->bios) { + if (rdev->is_atom_bios) + radeon_atombios_get_power_modes(rdev); + else + radeon_combios_get_power_modes(rdev); + radeon_print_power_mode_info(rdev); + } + radeon_pm_check_limits(rdev); if (radeon_debugfs_pm_init(rdev)) { -- cgit v1.2.3 From 845db70da0bd285813b25bb522a0281f28efbf89 Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Wed, 23 Dec 2009 00:42:43 +0100 Subject: drm/radeon/kms: don't set pcie lanes for ignored power_state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_atombios.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index adf900e368ac..e8fbae6395c7 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -1593,10 +1593,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) + (power_state->ucNonClockStateIndex * power_info->info_4.ucNonClockSize)); - misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); - rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = - ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> - ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) { if (rdev->flags & RADEON_IS_IGP) { struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info = @@ -1654,7 +1650,11 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) } rdev->pm.power_state[state_index].num_clock_modes = mode_index; if (mode_index) { + misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); misc2 = le16_to_cpu(non_clock_info->usClassification); + rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = + ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> + ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; -- cgit v1.2.3 From 0ec0e74f784ca08eab0354ab1dada46924c39b73 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 23 Dec 2009 13:21:58 -0500 Subject: drm/radeon/kms: add a power state type based on power state flags The idea is to flag a power state with a certain type and use that type to decide on what state to select. On r6xx+, we select a state and then transition between clock modes in that state. On pre-r6xx, we transition between states directly. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon.h | 9 ++++ drivers/gpu/drm/radeon/radeon_atombios.c | 78 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/radeon/radeon_combios.c | 4 ++ drivers/gpu/drm/radeon/radeon_pm.c | 12 ++++- 4 files changed, 102 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index d73d37d5effd..53468680de70 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -593,6 +593,14 @@ enum radeon_voltage_type { VOLTAGE_SW }; +enum radeon_pm_state_type { + POWER_STATE_TYPE_DEFAULT, + POWER_STATE_TYPE_POWERSAVE, + POWER_STATE_TYPE_BATTERY, + POWER_STATE_TYPE_BALANCED, + POWER_STATE_TYPE_PERFORMANCE, +}; + struct radeon_voltage { enum radeon_voltage_type type; /* gpio voltage */ @@ -626,6 +634,7 @@ struct radeon_pm_clock_info { }; struct radeon_power_state { + enum radeon_pm_state_type type; /* XXX: use a define for num clock modes */ struct radeon_pm_clock_info clock_info[8]; /* number of valid clock modes in this power state */ diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index e8fbae6395c7..b55012fedb94 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -1465,7 +1465,25 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; } + /* order matters! */ + if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_POWERSAVE; + if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BATTERY; + if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BATTERY; + if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BALANCED; + if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_PERFORMANCE; if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_DEFAULT; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.power_state[state_index].default_clock_mode = @@ -1513,7 +1531,28 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; } + /* order matters! */ + if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_POWERSAVE; + if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BATTERY; + if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BATTERY; + if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BALANCED; + if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_PERFORMANCE; + if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BALANCED; if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_DEFAULT; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.power_state[state_index].default_clock_mode = @@ -1567,7 +1606,28 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; } } + /* order matters! */ + if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_POWERSAVE; + if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BATTERY; + if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BATTERY; + if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BALANCED; + if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_PERFORMANCE; + if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BALANCED; if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_DEFAULT; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.power_state[state_index].default_clock_mode = @@ -1655,7 +1715,23 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; + switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { + case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BATTERY; + break; + case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BALANCED; + break; + case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_PERFORMANCE; + break; + } if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_DEFAULT; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.power_state[state_index].default_clock_mode = @@ -1673,6 +1749,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) if (rdev->pm.default_power_state == NULL) { /* add the default mode */ + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_DEFAULT; rdev->pm.power_state[state_index].num_clock_modes = 1; rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index eac2174abc5b..a4d40de50434 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -2406,6 +2406,8 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) (rdev->pm.power_state[state_index].clock_info[0].sclk > rdev->clock.default_sclk)) goto default_mode; + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_BATTERY; misc = RBIOS16(offset + 0x5 + 0x0); if (rev > 4) misc2 = RBIOS16(offset + 0x5 + 0xe); @@ -2467,6 +2469,8 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) default_mode: /* add the default mode */ + rdev->pm.power_state[state_index].type = + POWER_STATE_TYPE_DEFAULT; rdev->pm.power_state[state_index].num_clock_modes = 1; rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 6eb0e0b3264b..93ba0fb27e9d 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -40,6 +40,14 @@ static const char *pm_state_names[4] = { "PM_STATE_ACTIVE" }; +static const char *pm_state_types[5] = { + "Default", + "Powersave", + "Battery", + "Balanced", + "Performance", +}; + static void radeon_print_power_mode_info(struct radeon_device *rdev) { int i, j; @@ -51,7 +59,9 @@ static void radeon_print_power_mode_info(struct radeon_device *rdev) is_default = true; else is_default = false; - DRM_INFO("State %d %s\n", i, is_default ? "(default)" : ""); + DRM_INFO("State %d %s %s\n", i, + pm_state_types[rdev->pm.power_state[i].type], + is_default ? "(default)" : ""); if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes); DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes); -- cgit v1.2.3 From 516d0e46c80d2d20391f4145c2c5e3915253b8bf Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 23 Dec 2009 14:28:05 -0500 Subject: drm/radeon/kms: add code to select power state not hooked up yet. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon.h | 9 +++ drivers/gpu/drm/radeon/radeon_pm.c | 122 +++++++++++++++++++++++++++++++++++++ 2 files changed, 131 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 53468680de70..ece84fde76a6 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -601,6 +601,13 @@ enum radeon_pm_state_type { POWER_STATE_TYPE_PERFORMANCE, }; +enum radeon_pm_clock_mode_type { + POWER_MODE_TYPE_DEFAULT, + POWER_MODE_TYPE_LOW, + POWER_MODE_TYPE_MID, + POWER_MODE_TYPE_HIGH, +}; + struct radeon_voltage { enum radeon_voltage_type type; /* gpio voltage */ @@ -641,6 +648,7 @@ struct radeon_power_state { int num_clock_modes; /* currently selected clock mode */ struct radeon_pm_clock_info *current_clock_mode; + struct radeon_pm_clock_info *requested_clock_mode; struct radeon_pm_clock_info *default_clock_mode; /* non clock info about this state */ struct radeon_pm_non_clock_info non_clock_info; @@ -678,6 +686,7 @@ struct radeon_pm { /* number of valid power states */ int num_power_states; struct radeon_power_state *current_power_state; + struct radeon_power_state *requested_power_state; struct radeon_power_state *default_power_state; }; diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 93ba0fb27e9d..87d2776624bb 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -79,6 +79,128 @@ static void radeon_print_power_mode_info(struct radeon_device *rdev) } } +static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev, + enum radeon_pm_state_type type) +{ + int i; + struct radeon_power_state *power_state = NULL; + + switch (type) { + case POWER_STATE_TYPE_DEFAULT: + default: + return rdev->pm.default_power_state; + case POWER_STATE_TYPE_POWERSAVE: + for (i = 0; i < rdev->pm.num_power_states; i++) { + if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_POWERSAVE) { + power_state = &rdev->pm.power_state[i]; + break; + } + } + if (power_state == NULL) { + for (i = 0; i < rdev->pm.num_power_states; i++) { + if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY) { + power_state = &rdev->pm.power_state[i]; + break; + } + } + } + break; + case POWER_STATE_TYPE_BATTERY: + for (i = 0; i < rdev->pm.num_power_states; i++) { + if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY) { + power_state = &rdev->pm.power_state[i]; + break; + } + } + if (power_state == NULL) { + for (i = 0; i < rdev->pm.num_power_states; i++) { + if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_POWERSAVE) { + power_state = &rdev->pm.power_state[i]; + break; + } + } + } + break; + case POWER_STATE_TYPE_BALANCED: + case POWER_STATE_TYPE_PERFORMANCE: + for (i = 0; i < rdev->pm.num_power_states; i++) { + if (rdev->pm.power_state[i].type == type) { + power_state = &rdev->pm.power_state[i]; + break; + } + } + break; + } + + if (power_state == NULL) + return rdev->pm.default_power_state; + + return power_state; +} + +static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev, + struct radeon_power_state *power_state, + enum radeon_pm_clock_mode_type type) +{ + switch (type) { + case POWER_MODE_TYPE_DEFAULT: + default: + return power_state->default_clock_mode; + case POWER_MODE_TYPE_LOW: + return &power_state->clock_info[0]; + case POWER_MODE_TYPE_MID: + if (power_state->num_clock_modes > 2) + return &power_state->clock_info[1]; + else + return &power_state->clock_info[0]; + break; + case POWER_MODE_TYPE_HIGH: + return &power_state->clock_info[power_state->num_clock_modes - 1]; + } + +} + +static void radeon_get_power_state(struct radeon_device *rdev, + enum radeon_pm_action action) +{ + switch (action) { + case PM_ACTION_NONE: + default: + rdev->pm.requested_power_state = rdev->pm.current_power_state; + rdev->pm.requested_power_state->requested_clock_mode = + rdev->pm.requested_power_state->current_clock_mode; + break; + case PM_ACTION_MINIMUM: + rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY); + rdev->pm.requested_power_state->requested_clock_mode = + radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW); + break; + case PM_ACTION_DOWNCLOCK: + rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE); + rdev->pm.requested_power_state->requested_clock_mode = + radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID); + break; + case PM_ACTION_UPCLOCK: + rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT); + rdev->pm.requested_power_state->requested_clock_mode = + radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH); + break; + } +} + +static void radeon_set_power_state(struct radeon_device *rdev) +{ + if (rdev->pm.requested_power_state == rdev->pm.current_power_state) + return; + /* set pcie lanes */ + /* set voltage */ + /* set engine clock */ + radeon_set_engine_clock(rdev, rdev->pm.requested_power_state->requested_clock_mode->sclk); + /* set memory clock */ + + rdev->pm.current_power_state = rdev->pm.requested_power_state; +} + int radeon_pm_init(struct radeon_device *rdev) { rdev->pm.state = PM_STATE_DISABLED; -- cgit v1.2.3 From 530079a8f3f35828a80ba4981c1be902982363e7 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 23 Dec 2009 14:39:36 -0500 Subject: drm/radeon/kms: use power states for dynamic reclocking Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon.h | 4 ---- drivers/gpu/drm/radeon/radeon_pm.c | 31 ++++++++++++++----------------- 2 files changed, 14 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index ece84fde76a6..da1177375976 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -666,10 +666,6 @@ struct radeon_pm { bool vblank_callback; int active_crtcs; int req_vblank; - uint32_t min_gpu_engine_clock; - uint32_t min_gpu_memory_clock; - uint32_t min_mode_engine_clock; - uint32_t min_mode_memory_clock; fixed20_12 max_bandwidth; fixed20_12 igp_sideport_mclk; fixed20_12 igp_system_mclk; diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 87d2776624bb..f500c8d200e7 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -26,7 +26,6 @@ #define RADEON_IDLE_LOOP_MS 100 #define RADEON_RECLOCK_DELAY_MS 200 -static void radeon_pm_check_limits(struct radeon_device *rdev); static void radeon_pm_set_clocks_locked(struct radeon_device *rdev); static void radeon_pm_set_clocks(struct radeon_device *rdev); static void radeon_pm_reclock_work_handler(struct work_struct *work); @@ -186,12 +185,21 @@ static void radeon_get_power_state(struct radeon_device *rdev, radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH); break; } + DRM_INFO("Requested: e: %d m: %d p: %d\n", + rdev->pm.requested_power_state->requested_clock_mode->sclk, + rdev->pm.requested_power_state->requested_clock_mode->mclk, + rdev->pm.requested_power_state->non_clock_info.pcie_lanes); } static void radeon_set_power_state(struct radeon_device *rdev) { if (rdev->pm.requested_power_state == rdev->pm.current_power_state) return; + + DRM_INFO("Setting: e: %d m: %d p: %d\n", + rdev->pm.requested_power_state->requested_clock_mode->sclk, + rdev->pm.requested_power_state->requested_clock_mode->mclk, + rdev->pm.requested_power_state->non_clock_info.pcie_lanes); /* set pcie lanes */ /* set voltage */ /* set engine clock */ @@ -216,8 +224,6 @@ int radeon_pm_init(struct radeon_device *rdev) radeon_print_power_mode_info(rdev); } - radeon_pm_check_limits(rdev); - if (radeon_debugfs_pm_init(rdev)) { DRM_ERROR("Failed to register debugfs file for PM!\n"); } @@ -235,12 +241,6 @@ int radeon_pm_init(struct radeon_device *rdev) return 0; } -static void radeon_pm_check_limits(struct radeon_device *rdev) -{ - rdev->pm.min_gpu_engine_clock = rdev->clock.default_sclk - 5000; - rdev->pm.min_gpu_memory_clock = rdev->clock.default_mclk - 5000; -} - void radeon_pm_compute_clocks(struct radeon_device *rdev) { struct drm_device *ddev = rdev->ddev; @@ -287,8 +287,6 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev) mutex_unlock(&rdev->pm.mutex); } } else if (count == 1) { - rdev->pm.min_mode_engine_clock = rdev->pm.min_gpu_engine_clock; - rdev->pm.min_mode_memory_clock = rdev->pm.min_gpu_memory_clock; /* TODO: Increase clocks if needed for current mode */ if (rdev->pm.state == PM_STATE_MINIMUM) { @@ -326,23 +324,22 @@ static void radeon_pm_set_clocks_locked(struct radeon_device *rdev) /*radeon_fence_wait_last(rdev);*/ switch (rdev->pm.planned_action) { case PM_ACTION_UPCLOCK: - radeon_set_engine_clock(rdev, rdev->clock.default_sclk); + radeon_get_power_state(rdev, PM_ACTION_UPCLOCK); rdev->pm.downclocked = false; break; case PM_ACTION_DOWNCLOCK: - radeon_set_engine_clock(rdev, - rdev->pm.min_mode_engine_clock); + radeon_get_power_state(rdev, PM_ACTION_DOWNCLOCK); rdev->pm.downclocked = true; break; case PM_ACTION_MINIMUM: - radeon_set_engine_clock(rdev, - rdev->pm.min_gpu_engine_clock); + radeon_get_power_state(rdev, PM_ACTION_MINIMUM); break; case PM_ACTION_NONE: + radeon_get_power_state(rdev, PM_ACTION_NONE); DRM_ERROR("%s: PM_ACTION_NONE\n", __func__); break; } - + radeon_set_power_state(rdev); rdev->pm.planned_action = PM_ACTION_NONE; } -- cgit v1.2.3 From a0eb38eb8637a81bb7770d34036e498d2ba63a26 Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Thu, 24 Dec 2009 03:28:33 +0100 Subject: drm/radeon/kms: get_power_state early, not when processing IRQ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_pm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index f500c8d200e7..1cecd7346ab9 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -273,6 +273,7 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev) rdev->pm.state = PM_STATE_PAUSED; rdev->pm.planned_action = PM_ACTION_UPCLOCK; + radeon_get_power_state(rdev, rdev->pm.planned_action); rdev->pm.vblank_callback = true; mutex_unlock(&rdev->pm.mutex); @@ -292,6 +293,7 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev) if (rdev->pm.state == PM_STATE_MINIMUM) { rdev->pm.state = PM_STATE_ACTIVE; rdev->pm.planned_action = PM_ACTION_UPCLOCK; + radeon_get_power_state(rdev, rdev->pm.planned_action); radeon_pm_set_clocks_locked(rdev); queue_delayed_work(rdev->wq, &rdev->pm.idle_work, @@ -312,6 +314,7 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev) rdev->pm.state = PM_STATE_MINIMUM; rdev->pm.planned_action = PM_ACTION_MINIMUM; + radeon_get_power_state(rdev, rdev->pm.planned_action); radeon_pm_set_clocks_locked(rdev); } @@ -324,18 +327,14 @@ static void radeon_pm_set_clocks_locked(struct radeon_device *rdev) /*radeon_fence_wait_last(rdev);*/ switch (rdev->pm.planned_action) { case PM_ACTION_UPCLOCK: - radeon_get_power_state(rdev, PM_ACTION_UPCLOCK); rdev->pm.downclocked = false; break; case PM_ACTION_DOWNCLOCK: - radeon_get_power_state(rdev, PM_ACTION_DOWNCLOCK); rdev->pm.downclocked = true; break; case PM_ACTION_MINIMUM: - radeon_get_power_state(rdev, PM_ACTION_MINIMUM); break; case PM_ACTION_NONE: - radeon_get_power_state(rdev, PM_ACTION_NONE); DRM_ERROR("%s: PM_ACTION_NONE\n", __func__); break; } @@ -427,6 +426,7 @@ static void radeon_pm_idle_work_handler(struct work_struct *work) rdev->pm.req_vblank |= (1 << 1); drm_vblank_get(rdev->ddev, 1); } + radeon_get_power_state(rdev, rdev->pm.planned_action); rdev->pm.vblank_callback = true; } } -- cgit v1.2.3 From 6d7f2d8da106ecf794a5a3e98c4239f348119e3c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 5 Feb 2010 00:55:32 -0500 Subject: drm/radeon/kms: dynclks fixes - only r4xx/r5xx/rs6xx/rs740 have clock gating atom table, so disable it on r6xx. it's already disabled on r7xx - check to make sure the clock_gating hook exists before calling it. This avoids a segfault on asics without that function. - remove unused static power management function. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_asic.h | 2 +- drivers/gpu/drm/radeon/radeon_atombios.c | 10 ---------- drivers/gpu/drm/radeon/radeon_clocks.c | 6 ++++-- 3 files changed, 5 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index d758b1ffb74c..3f3c7a2169f1 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -549,7 +549,7 @@ static struct radeon_asic r600_asic = { .set_memory_clock = &radeon_atom_set_memory_clock, .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, - .set_clock_gating = &radeon_atom_set_clock_gating, + .set_clock_gating = NULL, .set_surface_reg = r600_set_surface_reg, .clear_surface_reg = r600_clear_surface_reg, .bandwidth_update = &rv515_bandwidth_update, diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index b55012fedb94..c3198453528f 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -1780,16 +1780,6 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); } -void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable) -{ - ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args; - int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt); - - args.ucEnable = enable; - - atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); -} - uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) { GET_ENGINE_CLOCK_PS_ALLOCATION args; diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c index 73c4405bf42f..3ec94a0d3109 100644 --- a/drivers/gpu/drm/radeon/radeon_clocks.c +++ b/drivers/gpu/drm/radeon/radeon_clocks.c @@ -846,8 +846,10 @@ int radeon_static_clocks_init(struct drm_device *dev) /* XXX make sure engine is idle */ if (radeon_dynclks != -1) { - if (radeon_dynclks) - radeon_set_clock_gating(rdev, 1); + if (radeon_dynclks) { + if (rdev->asic->set_clock_gating) + radeon_set_clock_gating(rdev, 1); + } } radeon_apply_clock_quirks(rdev); return 0; -- cgit v1.2.3 From 57fcab620d05c3eb32b4787ce7501565c4c3162d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sat, 6 Feb 2010 17:06:42 -0500 Subject: drm/radeon/kms: take the pm mutex when using hw i2c we need a constant sclk for i2c prescale. Also, get the current sclk when calculating prescale rather than using the default sclk. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_i2c.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c index b47a5615fe6a..272c45db5cec 100644 --- a/drivers/gpu/drm/radeon/radeon_i2c.c +++ b/drivers/gpu/drm/radeon/radeon_i2c.c @@ -192,12 +192,16 @@ static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, struct radeon_i2c_bus_rec *rec = &i2c->rec; struct i2c_msg *p; int i, j, k, ret = num; - /* XXX: use get_engine_clock() to get the current sclk */ - u32 prescale = (((rdev->clock.default_sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; + u32 sclk, prescale; u32 i2c_cntl_0, i2c_cntl_1, i2c_data; u32 tmp, reg; mutex_lock(&rdev->dc_hw_i2c_mutex); + /* take the pm lock since we need a constant sclk */ + mutex_lock(&rdev->pm.mutex); + + sclk = radeon_get_engine_clock(rdev); + prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | RADEON_I2C_START | @@ -424,6 +428,7 @@ done: WREG32(RADEON_BIOS_6_SCRATCH, tmp); } + mutex_unlock(&rdev->pm.mutex); mutex_unlock(&rdev->dc_hw_i2c_mutex); return ret; @@ -441,12 +446,19 @@ static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *p; int i2c_clock = 50; int i, j, remaining, current_count, buffer_offset, ret = num; - /* XXX: use get_engine_clock() to get the current sclk */ - u32 prescale; + u32 sclk, prescale; u32 tmp, reg; u32 saved1, saved2; mutex_lock(&rdev->dc_hw_i2c_mutex); + /* take the pm lock since we need a constant sclk */ + mutex_lock(&rdev->pm.mutex); + + sclk = radeon_get_engine_clock(rdev); + if (rdev->family == CHIP_R520) + prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); + else + prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; /* clear gpio mask bits */ tmp = RREG32(rec->mask_clk_reg); @@ -500,11 +512,6 @@ static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, goto done; } - if (rdev->family == CHIP_R520) - prescale = (127 << 8) + ((rdev->clock.default_sclk * 10) / (4 * 127 * i2c_clock)); - else - prescale = (((rdev->clock.default_sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; - reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; switch (rec->mask_clk_reg) { case AVIVO_DC_GPIO_DDC1_MASK: @@ -662,6 +669,7 @@ done: tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; WREG32(RADEON_BIOS_6_SCRATCH, tmp); + mutex_unlock(&rdev->pm.mutex); mutex_unlock(&rdev->dc_hw_i2c_mutex); return ret; -- cgit v1.2.3 From 20d6c346f69ec68f3f4956c726d830c978f911a8 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 31 Jan 2010 07:07:14 +1000 Subject: drm/radeon/kms: use udelay for short delays For usec delays use udelay instead of scheduling, this should allow reclocking to happen faster. Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/atom.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c index e3b44562d265..bd0c843872b2 100644 --- a/drivers/gpu/drm/radeon/atom.c +++ b/drivers/gpu/drm/radeon/atom.c @@ -640,7 +640,8 @@ static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) uint8_t count = U8((*ptr)++); SDEBUG(" count: %d\n", count); if (arg == ATOM_UNIT_MICROSEC) - schedule_timeout_uninterruptible(usecs_to_jiffies(count)); + udelay(count); + // schedule_timeout_uninterruptible(usecs_to_jiffies(count)); else schedule_timeout_uninterruptible(msecs_to_jiffies(count)); } -- cgit v1.2.3 From 73a6d3fc104827db574e4bd206a025299fef0bb1 Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Fri, 8 Jan 2010 00:22:47 +0100 Subject: drm/radeon/kms: use wait queue (events) for VBLANK sync MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This already simplifies code significally and makes it maintaible in case of adding memory reclocking plus voltage changing in future. Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r100.c | 6 +-- drivers/gpu/drm/radeon/r600.c | 6 +-- drivers/gpu/drm/radeon/radeon.h | 3 +- drivers/gpu/drm/radeon/radeon_device.c | 1 + drivers/gpu/drm/radeon/radeon_pm.c | 93 ++++++++++++---------------------- drivers/gpu/drm/radeon/rs600.c | 6 +-- 6 files changed, 41 insertions(+), 74 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 05502bf042b9..346ae3d7e0d4 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -312,13 +312,11 @@ int r100_irq_process(struct radeon_device *rdev) /* Vertical blank interrupts */ if (status & RADEON_CRTC_VBLANK_STAT) { drm_handle_vblank(rdev->ddev, 0); - if (rdev->pm.vblank_callback) - queue_work(rdev->wq, &rdev->pm.reclock_work); + wake_up(&rdev->irq.vblank_queue); } if (status & RADEON_CRTC2_VBLANK_STAT) { drm_handle_vblank(rdev->ddev, 1); - if (rdev->pm.vblank_callback) - queue_work(rdev->wq, &rdev->pm.reclock_work); + wake_up(&rdev->irq.vblank_queue); } if (status & RADEON_FP_DETECT_STAT) { queue_hotplug = true; diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 65daf55af2d9..05769fa77a21 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -2744,8 +2744,7 @@ restart_ih: case 0: /* D1 vblank */ if (disp_int & LB_D1_VBLANK_INTERRUPT) { drm_handle_vblank(rdev->ddev, 0); - if (rdev->pm.vblank_callback) - queue_work(rdev->wq, &rdev->pm.reclock_work); + wake_up(&rdev->irq.vblank_queue); disp_int &= ~LB_D1_VBLANK_INTERRUPT; DRM_DEBUG("IH: D1 vblank\n"); } @@ -2766,8 +2765,7 @@ restart_ih: case 0: /* D2 vblank */ if (disp_int & LB_D2_VBLANK_INTERRUPT) { drm_handle_vblank(rdev->ddev, 1); - if (rdev->pm.vblank_callback) - queue_work(rdev->wq, &rdev->pm.reclock_work); + wake_up(&rdev->irq.vblank_queue); disp_int &= ~LB_D2_VBLANK_INTERRUPT; DRM_DEBUG("IH: D2 vblank\n"); } diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index da1177375976..3f353131bb38 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -351,6 +351,7 @@ struct radeon_irq { bool sw_int; /* FIXME: use a define max crtc rather than hardcode it */ bool crtc_vblank_int[2]; + wait_queue_head_t vblank_queue; /* FIXME: use defines for max hpd/dacs */ bool hpd[6]; spinlock_t sw_lock; @@ -657,13 +658,11 @@ struct radeon_power_state { struct radeon_pm { struct mutex mutex; - struct work_struct reclock_work; struct delayed_work idle_work; enum radeon_pm_state state; enum radeon_pm_action planned_action; unsigned long action_timeout; bool downclocked; - bool vblank_callback; int active_crtcs; int req_vblank; fixed20_12 max_bandwidth; diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index a1c937d03845..c90f8d370266 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -645,6 +645,7 @@ int radeon_device_init(struct radeon_device *rdev, mutex_init(&rdev->pm.mutex); rwlock_init(&rdev->fence_drv.lock); INIT_LIST_HEAD(&rdev->gem.objects); + init_waitqueue_head(&rdev->irq.vblank_queue); /* setup workqueue */ rdev->wq = create_workqueue("radeon"); diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 1cecd7346ab9..a8e151ec1351 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -25,10 +25,10 @@ #define RADEON_IDLE_LOOP_MS 100 #define RADEON_RECLOCK_DELAY_MS 200 +#define RADEON_WAIT_VBLANK_TIMEOUT 200 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev); static void radeon_pm_set_clocks(struct radeon_device *rdev); -static void radeon_pm_reclock_work_handler(struct work_struct *work); static void radeon_pm_idle_work_handler(struct work_struct *work); static int radeon_debugfs_pm_init(struct radeon_device *rdev); @@ -214,7 +214,6 @@ int radeon_pm_init(struct radeon_device *rdev) rdev->pm.state = PM_STATE_DISABLED; rdev->pm.planned_action = PM_ACTION_NONE; rdev->pm.downclocked = false; - rdev->pm.vblank_callback = false; if (rdev->bios) { if (rdev->is_atom_bios) @@ -228,7 +227,6 @@ int radeon_pm_init(struct radeon_device *rdev) DRM_ERROR("Failed to register debugfs file for PM!\n"); } - INIT_WORK(&rdev->pm.reclock_work, radeon_pm_reclock_work_handler); INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler); if (radeon_dynpm != -1 && radeon_dynpm) { @@ -266,26 +264,14 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev) if (count > 1) { if (rdev->pm.state == PM_STATE_ACTIVE) { - wait_queue_head_t wait; - init_waitqueue_head(&wait); - cancel_delayed_work(&rdev->pm.idle_work); rdev->pm.state = PM_STATE_PAUSED; rdev->pm.planned_action = PM_ACTION_UPCLOCK; - radeon_get_power_state(rdev, rdev->pm.planned_action); - rdev->pm.vblank_callback = true; - - mutex_unlock(&rdev->pm.mutex); - - wait_event_timeout(wait, !rdev->pm.downclocked, - msecs_to_jiffies(300)); - if (!rdev->pm.downclocked) + if (rdev->pm.downclocked) radeon_pm_set_clocks(rdev); DRM_DEBUG("radeon: dynamic power management deactivated\n"); - } else { - mutex_unlock(&rdev->pm.mutex); } } else if (count == 1) { /* TODO: Increase clocks if needed for current mode */ @@ -293,8 +279,7 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev) if (rdev->pm.state == PM_STATE_MINIMUM) { rdev->pm.state = PM_STATE_ACTIVE; rdev->pm.planned_action = PM_ACTION_UPCLOCK; - radeon_get_power_state(rdev, rdev->pm.planned_action); - radeon_pm_set_clocks_locked(rdev); + radeon_pm_set_clocks(rdev); queue_delayed_work(rdev->wq, &rdev->pm.idle_work, msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); @@ -305,8 +290,6 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev) msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); DRM_DEBUG("radeon: dynamic power management activated\n"); } - - mutex_unlock(&rdev->pm.mutex); } else { /* count == 0 */ if (rdev->pm.state != PM_STATE_MINIMUM) { @@ -314,12 +297,11 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev) rdev->pm.state = PM_STATE_MINIMUM; rdev->pm.planned_action = PM_ACTION_MINIMUM; - radeon_get_power_state(rdev, rdev->pm.planned_action); - radeon_pm_set_clocks_locked(rdev); + radeon_pm_set_clocks(rdev); } - - mutex_unlock(&rdev->pm.mutex); } + + mutex_unlock(&rdev->pm.mutex); } static void radeon_pm_set_clocks_locked(struct radeon_device *rdev) @@ -344,31 +326,32 @@ static void radeon_pm_set_clocks_locked(struct radeon_device *rdev) static void radeon_pm_set_clocks(struct radeon_device *rdev) { - mutex_lock(&rdev->pm.mutex); - /* new VBLANK irq may come before handling previous one */ - if (rdev->pm.vblank_callback) { - mutex_lock(&rdev->cp.mutex); - if (rdev->pm.req_vblank & (1 << 0)) { - rdev->pm.req_vblank &= ~(1 << 0); - drm_vblank_put(rdev->ddev, 0); - } - if (rdev->pm.req_vblank & (1 << 1)) { - rdev->pm.req_vblank &= ~(1 << 1); - drm_vblank_put(rdev->ddev, 1); - } - rdev->pm.vblank_callback = false; - radeon_pm_set_clocks_locked(rdev); - mutex_unlock(&rdev->cp.mutex); + radeon_get_power_state(rdev, rdev->pm.planned_action); + mutex_lock(&rdev->cp.mutex); + + if (rdev->pm.active_crtcs & (1 << 0)) { + rdev->pm.req_vblank |= (1 << 0); + drm_vblank_get(rdev->ddev, 0); + } + if (rdev->pm.active_crtcs & (1 << 1)) { + rdev->pm.req_vblank |= (1 << 1); + drm_vblank_get(rdev->ddev, 1); + } + if (rdev->pm.active_crtcs) + wait_event_interruptible_timeout( + rdev->irq.vblank_queue, 0, + msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); + if (rdev->pm.req_vblank & (1 << 0)) { + rdev->pm.req_vblank &= ~(1 << 0); + drm_vblank_put(rdev->ddev, 0); + } + if (rdev->pm.req_vblank & (1 << 1)) { + rdev->pm.req_vblank &= ~(1 << 1); + drm_vblank_put(rdev->ddev, 1); } - mutex_unlock(&rdev->pm.mutex); -} -static void radeon_pm_reclock_work_handler(struct work_struct *work) -{ - struct radeon_device *rdev; - rdev = container_of(work, struct radeon_device, - pm.reclock_work); - radeon_pm_set_clocks(rdev); + radeon_pm_set_clocks_locked(rdev); + mutex_unlock(&rdev->cp.mutex); } static void radeon_pm_idle_work_handler(struct work_struct *work) @@ -378,8 +361,7 @@ static void radeon_pm_idle_work_handler(struct work_struct *work) pm.idle_work.work); mutex_lock(&rdev->pm.mutex); - if (rdev->pm.state == PM_STATE_ACTIVE && - !rdev->pm.vblank_callback) { + if (rdev->pm.state == PM_STATE_ACTIVE) { unsigned long irq_flags; int not_processed = 0; @@ -417,17 +399,8 @@ static void radeon_pm_idle_work_handler(struct work_struct *work) } if (rdev->pm.planned_action != PM_ACTION_NONE && - jiffies > rdev->pm.action_timeout) { - if (rdev->pm.active_crtcs & (1 << 0)) { - rdev->pm.req_vblank |= (1 << 0); - drm_vblank_get(rdev->ddev, 0); - } - if (rdev->pm.active_crtcs & (1 << 1)) { - rdev->pm.req_vblank |= (1 << 1); - drm_vblank_get(rdev->ddev, 1); - } - radeon_get_power_state(rdev, rdev->pm.planned_action); - rdev->pm.vblank_callback = true; + jiffies > rdev->pm.action_timeout) { + radeon_pm_set_clocks(rdev); } } mutex_unlock(&rdev->pm.mutex); diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index a581fdead4dd..979b00034de9 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c @@ -408,13 +408,11 @@ int rs600_irq_process(struct radeon_device *rdev) /* Vertical blank interrupts */ if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) { drm_handle_vblank(rdev->ddev, 0); - if (rdev->pm.vblank_callback) - queue_work(rdev->wq, &rdev->pm.reclock_work); + wake_up(&rdev->irq.vblank_queue); } if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) { drm_handle_vblank(rdev->ddev, 1); - if (rdev->pm.vblank_callback) - queue_work(rdev->wq, &rdev->pm.reclock_work); + wake_up(&rdev->irq.vblank_queue); } if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) { queue_hotplug = true; -- cgit v1.2.3 From 9f93ed39804a9cfe10577cfae66059fe6bc6e3a5 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Thu, 28 Jan 2010 18:22:31 +0100 Subject: drm/radeon/kms: bogus cs recorder utilities This add an utilities function radeon_ib_bogus_add which will save an ib into a list of ib which can then be dumped using debugfs. Once dumped the ib is removed from the list. This should allow to save & capute ib for further debugging. Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon.h | 2 ++ drivers/gpu/drm/radeon/radeon_ring.c | 66 ++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 3f353131bb38..b519d7db2dcb 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -383,6 +383,7 @@ struct radeon_ib_pool { struct mutex mutex; struct radeon_bo *robj; struct list_head scheduled_ibs; + struct list_head bogus_ib; struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; bool ready; DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); @@ -437,6 +438,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); int radeon_ib_pool_init(struct radeon_device *rdev); void radeon_ib_pool_fini(struct radeon_device *rdev); int radeon_ib_test(struct radeon_device *rdev); +extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); /* Ring access between begin & end cannot sleep */ void radeon_ring_free_size(struct radeon_device *rdev); int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index 4d12b2d17b4d..e3bee59ef6c3 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c @@ -34,6 +34,36 @@ int radeon_debugfs_ib_init(struct radeon_device *rdev); +void radeon_ib_bogus_cleanup(struct radeon_device *rdev) +{ + struct radeon_ib *ib, *n; + + list_for_each_entry_safe(ib, n, &rdev->ib_pool.bogus_ib, list) { + list_del(&ib->list); + vfree(ib->ptr); + kfree(ib); + } +} + +void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib) +{ + struct radeon_ib *bib; + + bib = kmalloc(sizeof(*bib), GFP_KERNEL); + if (bib == NULL) + return; + bib->ptr = vmalloc(ib->length_dw * 4); + if (bib->ptr == NULL) { + kfree(bib); + return; + } + memcpy(bib->ptr, ib->ptr, ib->length_dw * 4); + bib->length_dw = ib->length_dw; + mutex_lock(&rdev->ib_pool.mutex); + list_add_tail(&bib->list, &rdev->ib_pool.bogus_ib); + mutex_unlock(&rdev->ib_pool.mutex); +} + /* * IB. */ @@ -163,6 +193,7 @@ int radeon_ib_pool_init(struct radeon_device *rdev) if (rdev->ib_pool.robj) return 0; + INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib); /* Allocate 1M object buffer */ INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs); r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024, @@ -214,6 +245,7 @@ void radeon_ib_pool_fini(struct radeon_device *rdev) return; } mutex_lock(&rdev->ib_pool.mutex); + radeon_ib_bogus_cleanup(rdev); bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); if (rdev->ib_pool.robj) { r = radeon_bo_reserve(rdev->ib_pool.robj, false); @@ -372,15 +404,49 @@ static int radeon_debugfs_ib_info(struct seq_file *m, void *data) return 0; } +static int radeon_debugfs_ib_bogus_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct radeon_device *rdev = node->info_ent->data; + struct radeon_ib *ib; + unsigned i; + + mutex_lock(&rdev->ib_pool.mutex); + if (list_empty(&rdev->ib_pool.bogus_ib)) { + mutex_unlock(&rdev->ib_pool.mutex); + seq_printf(m, "no bogus IB recorded\n"); + return 0; + } + ib = list_first_entry(&rdev->ib_pool.bogus_ib, struct radeon_ib, list); + list_del_init(&ib->list); + mutex_unlock(&rdev->ib_pool.mutex); + seq_printf(m, "IB size %05u dwords\n", ib->length_dw); + for (i = 0; i < ib->length_dw; i++) { + seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]); + } + vfree(ib->ptr); + kfree(ib); + return 0; +} + static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE]; static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32]; + +static struct drm_info_list radeon_debugfs_ib_bogus_info_list[] = { + {"radeon_ib_bogus", radeon_debugfs_ib_bogus_info, 0, NULL}, +}; #endif int radeon_debugfs_ib_init(struct radeon_device *rdev) { #if defined(CONFIG_DEBUG_FS) unsigned i; + int r; + radeon_debugfs_ib_bogus_info_list[0].data = rdev; + r = radeon_debugfs_add_files(rdev, radeon_debugfs_ib_bogus_info_list, 1); + if (r) + return r; for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i); radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i]; -- cgit v1.2.3 From e97bd974448ce90f8e4720499d84580bcd6a2f7a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 12 Jan 2010 17:17:33 -0500 Subject: drm/radeon/kms: update atombios.h to latest upstream. This merges ugly whitespace we want to keep for consistency along with the latest upstream changes. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/atombios.h | 7300 +++++++++++++++++++++---------------- 1 file changed, 4185 insertions(+), 3115 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h index 8e28842080df..6732b5dd8ff4 100644 --- a/drivers/gpu/drm/radeon/atombios.h +++ b/drivers/gpu/drm/radeon/atombios.h @@ -1,5 +1,5 @@ /* - * Copyright 2006-2007 Advanced Micro Devices, Inc. + * Copyright 2006-2007 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,10 +20,12 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/****************************************************************************/ + +/****************************************************************************/ /*Portion I: Definitions shared between VBIOS and Driver */ /****************************************************************************/ + #ifndef _ATOMBIOS_H #define _ATOMBIOS_H @@ -40,39 +42,46 @@ #endif #ifdef _H2INC -#ifndef ULONG -typedef unsigned long ULONG; -#endif + #ifndef ULONG + typedef unsigned long ULONG; + #endif -#ifndef UCHAR -typedef unsigned char UCHAR; -#endif + #ifndef UCHAR + typedef unsigned char UCHAR; + #endif -#ifndef USHORT -typedef unsigned short USHORT; -#endif + #ifndef USHORT + typedef unsigned short USHORT; + #endif #endif - -#define ATOM_DAC_A 0 + +#define ATOM_DAC_A 0 #define ATOM_DAC_B 1 #define ATOM_EXT_DAC 2 #define ATOM_CRTC1 0 #define ATOM_CRTC2 1 +#define ATOM_CRTC3 2 +#define ATOM_CRTC4 3 +#define ATOM_CRTC5 4 +#define ATOM_CRTC6 5 +#define ATOM_CRTC_INVALID 0xFF #define ATOM_DIGA 0 #define ATOM_DIGB 1 #define ATOM_PPLL1 0 #define ATOM_PPLL2 1 +#define ATOM_DCPLL 2 +#define ATOM_PPLL_INVALID 0xFF #define ATOM_SCALER1 0 #define ATOM_SCALER2 1 -#define ATOM_SCALER_DISABLE 0 -#define ATOM_SCALER_CENTER 1 -#define ATOM_SCALER_EXPANSION 2 -#define ATOM_SCALER_MULTI_EX 3 +#define ATOM_SCALER_DISABLE 0 +#define ATOM_SCALER_CENTER 1 +#define ATOM_SCALER_EXPANSION 2 +#define ATOM_SCALER_MULTI_EX 3 #define ATOM_DISABLE 0 #define ATOM_ENABLE 1 @@ -82,6 +91,7 @@ typedef unsigned short USHORT; #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) #define ATOM_ENCODER_INIT (ATOM_DISABLE+7) +#define ATOM_GET_STATUS (ATOM_DISABLE+8) #define ATOM_BLANKING 1 #define ATOM_BLANKING_OFF 0 @@ -114,7 +124,7 @@ typedef unsigned short USHORT; #define ATOM_DAC2_CV ATOM_DAC1_CV #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC #define ATOM_DAC2_PAL ATOM_DAC1_PAL - + #define ATOM_PM_ON 0 #define ATOM_PM_STANDBY 1 #define ATOM_PM_SUSPEND 2 @@ -134,6 +144,7 @@ typedef unsigned short USHORT; #define ATOM_PANEL_MISC_TEMPORAL 0x00000040 #define ATOM_PANEL_MISC_API_ENABLED 0x00000080 + #define MEMTYPE_DDR1 "DDR1" #define MEMTYPE_DDR2 "DDR2" #define MEMTYPE_DDR3 "DDR3" @@ -145,19 +156,19 @@ typedef unsigned short USHORT; /* Maximum size of that FireGL flag string */ -#define ATOM_FIREGL_FLAG_STRING "FGL" /* Flag used to enable FireGL Support */ -#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 /* sizeof( ATOM_FIREGL_FLAG_STRING ) */ +#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support +#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) -#define ATOM_FAKE_DESKTOP_STRING "DSK" /* Flag used to enable mobile ASIC on Desktop */ -#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING +#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop +#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING -#define ATOM_M54T_FLAG_STRING "M54T" /* Flag used to enable M54T Support */ -#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 /* sizeof( ATOM_M54T_FLAG_STRING ) */ +#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support +#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) #define HW_ASSISTED_I2C_STATUS_FAILURE 2 #define HW_ASSISTED_I2C_STATUS_SUCCESS 1 -#pragma pack(1) /* BIOS data must use byte aligment */ +#pragma pack(1) /* BIOS data must use byte aligment */ /* Define offset to location of ROM header. */ @@ -165,367 +176,410 @@ typedef unsigned short USHORT; #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 -#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ +#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e /* Common header for all ROM Data tables. - Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. + Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. And the pointer actually points to this header. */ -typedef struct _ATOM_COMMON_TABLE_HEADER { - USHORT usStructureSize; - UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ - UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ - /*Image can't be updated, while Driver needs to carry the new table! */ -} ATOM_COMMON_TABLE_HEADER; - -typedef struct _ATOM_ROM_HEADER { - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, - atombios should init it as "ATOM", don't change the position */ - USHORT usBiosRuntimeSegmentAddress; - USHORT usProtectedModeInfoOffset; - USHORT usConfigFilenameOffset; - USHORT usCRC_BlockOffset; - USHORT usBIOS_BootupMessageOffset; - USHORT usInt10Offset; - USHORT usPciBusDevInitCode; - USHORT usIoBaseAddress; - USHORT usSubsystemVendorID; - USHORT usSubsystemID; - USHORT usPCI_InfoOffset; - USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ - USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ - UCHAR ucExtendedFunctionCode; - UCHAR ucReserved; -} ATOM_ROM_HEADER; +typedef struct _ATOM_COMMON_TABLE_HEADER +{ + USHORT usStructureSize; + UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ + UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ + /*Image can't be updated, while Driver needs to carry the new table! */ +}ATOM_COMMON_TABLE_HEADER; + +typedef struct _ATOM_ROM_HEADER +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, + atombios should init it as "ATOM", don't change the position */ + USHORT usBiosRuntimeSegmentAddress; + USHORT usProtectedModeInfoOffset; + USHORT usConfigFilenameOffset; + USHORT usCRC_BlockOffset; + USHORT usBIOS_BootupMessageOffset; + USHORT usInt10Offset; + USHORT usPciBusDevInitCode; + USHORT usIoBaseAddress; + USHORT usSubsystemVendorID; + USHORT usSubsystemID; + USHORT usPCI_InfoOffset; + USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ + USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ + UCHAR ucExtendedFunctionCode; + UCHAR ucReserved; +}ATOM_ROM_HEADER; /*==============================Command Table Portion==================================== */ #ifdef UEFI_BUILD -#define UTEMP USHORT -#define USHORT void* + #define UTEMP USHORT + #define USHORT void* #endif -typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES { - USHORT ASIC_Init; /* Function Table, used by various SW components,latest version 1.1 */ - USHORT GetDisplaySurfaceSize; /* Atomic Table, Used by Bios when enabling HW ICON */ - USHORT ASIC_RegistersInit; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ - USHORT VRAM_BlockVenderDetection; /* Atomic Table, used only by Bios */ - USHORT DIGxEncoderControl; /* Only used by Bios */ - USHORT MemoryControllerInit; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ - USHORT EnableCRTCMemReq; /* Function Table,directly used by various SW components,latest version 2.1 */ - USHORT MemoryParamAdjust; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed */ - USHORT DVOEncoderControl; /* Function Table,directly used by various SW components,latest version 1.2 */ - USHORT GPIOPinControl; /* Atomic Table, only used by Bios */ - USHORT SetEngineClock; /*Function Table,directly used by various SW components,latest version 1.1 */ - USHORT SetMemoryClock; /* Function Table,directly used by various SW components,latest version 1.1 */ - USHORT SetPixelClock; /*Function Table,directly used by various SW components,latest version 1.2 */ - USHORT DynamicClockGating; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ - USHORT ResetMemoryDLL; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ - USHORT ResetMemoryDevice; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ - USHORT MemoryPLLInit; - USHORT AdjustDisplayPll; /* only used by Bios */ - USHORT AdjustMemoryController; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ - USHORT EnableASIC_StaticPwrMgt; /* Atomic Table, only used by Bios */ - USHORT ASIC_StaticPwrMgtStatusChange; /* Obsolete, only used by Bios */ - USHORT DAC_LoadDetection; /* Atomic Table, directly used by various SW components,latest version 1.2 */ - USHORT LVTMAEncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.3 */ - USHORT LCD1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT DAC1EncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT DAC2EncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT DVOOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT CV1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT GetConditionalGoldenSetting; /* only used by Bios */ - USHORT TVEncoderControl; /* Function Table,directly used by various SW components,latest version 1.1 */ - USHORT TMDSAEncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.3 */ - USHORT LVDSEncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.3 */ - USHORT TV1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT EnableScaler; /* Atomic Table, used only by Bios */ - USHORT BlankCRTC; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT EnableCRTC; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT GetPixelClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT EnableVGA_Render; /* Function Table,directly used by various SW components,latest version 1.1 */ - USHORT EnableVGA_Access; /* Obsolete , only used by Bios */ - USHORT SetCRTC_Timing; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT SetCRTC_OverScan; /* Atomic Table, used by various SW components,latest version 1.1 */ - USHORT SetCRTC_Replication; /* Atomic Table, used only by Bios */ - USHORT SelectCRTC_Source; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT EnableGraphSurfaces; /* Atomic Table, used only by Bios */ - USHORT UpdateCRTC_DoubleBufferRegisters; - USHORT LUT_AutoFill; /* Atomic Table, only used by Bios */ - USHORT EnableHW_IconCursor; /* Atomic Table, only used by Bios */ - USHORT GetMemoryClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT GetEngineClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT SetCRTC_UsingDTDTiming; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT ExternalEncoderControl; /* Atomic Table, directly used by various SW components,latest version 2.1 */ - USHORT LVTMAOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT VRAM_BlockDetectionByStrap; /* Atomic Table, used only by Bios */ - USHORT MemoryCleanUp; /* Atomic Table, only used by Bios */ - USHORT ProcessI2cChannelTransaction; /* Function Table,only used by Bios */ - USHORT WriteOneByteToHWAssistedI2C; /* Function Table,indirectly used by various SW components */ - USHORT ReadHWAssistedI2CStatus; /* Atomic Table, indirectly used by various SW components */ - USHORT SpeedFanControl; /* Function Table,indirectly used by various SW components,called from ASIC_Init */ - USHORT PowerConnectorDetection; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT MC_Synchronization; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ - USHORT ComputeMemoryEnginePLL; /* Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock */ - USHORT MemoryRefreshConversion; /* Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock */ - USHORT VRAM_GetCurrentInfoBlock; /* Atomic Table, used only by Bios */ - USHORT DynamicMemorySettings; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ - USHORT MemoryTraining; /* Atomic Table, used only by Bios */ - USHORT EnableSpreadSpectrumOnPPLL; /* Atomic Table, directly used by various SW components,latest version 1.2 */ - USHORT TMDSAOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT SetVoltage; /* Function Table,directly and/or indirectly used by various SW components,latest version 1.1 */ - USHORT DAC1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT DAC2OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ - USHORT SetupHWAssistedI2CStatus; /* Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" */ - USHORT ClockSource; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ - USHORT MemoryDeviceInit; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ - USHORT EnableYUV; /* Atomic Table, indirectly used by various SW components,called from EnableVGARender */ - USHORT DIG1EncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ - USHORT DIG2EncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ - USHORT DIG1TransmitterControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ - USHORT DIG2TransmitterControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ - USHORT ProcessAuxChannelTransaction; /* Function Table,only used by Bios */ - USHORT DPEncoderService; /* Function Table,only used by Bios */ -} ATOM_MASTER_LIST_OF_COMMAND_TABLES; - -/* For backward compatible */ +typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ + USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 + USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON + USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init + USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios + USHORT DIGxEncoderControl; //Only used by Bios + USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init + USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 + USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed + USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 + USHORT GPIOPinControl; //Atomic Table, only used by Bios + USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 + USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 + USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 + USHORT DynamicClockGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init + USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT MemoryPLLInit; + USHORT AdjustDisplayPll; //only used by Bios + USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios + USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios + USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 + USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 + USHORT LCD1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead + USHORT GetConditionalGoldenSetting; //only used by Bios + USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 + USHORT TMDSAEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 + USHORT LVDSEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 + USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead + USHORT EnableScaler; //Atomic Table, used only by Bios + USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 + USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios + USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 + USHORT SetCRTC_Replication; //Atomic Table, used only by Bios + USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios + USHORT UpdateCRTC_DoubleBufferRegisters; + USHORT LUT_AutoFill; //Atomic Table, only used by Bios + USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios + USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 + USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios + USHORT MemoryCleanUp; //Atomic Table, only used by Bios + USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios + USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components + USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components + USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init + USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock + USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock + USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios + USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT MemoryTraining; //Atomic Table, used only by Bios + USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 + USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 + USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT SetupHWAssistedI2CStatus; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" + USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init + USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT EnableYUV; //Atomic Table, indirectly used by various SW components,called from EnableVGARender + USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios + USHORT DPEncoderService; //Function Table,only used by Bios +}ATOM_MASTER_LIST_OF_COMMAND_TABLES; + +// For backward compatible #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction #define UNIPHYTransmitterControl DIG1TransmitterControl #define LVTMATransmitterControl DIG2TransmitterControl #define SetCRTC_DPM_State GetConditionalGoldenSetting #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange +#define HPDInterruptService ReadHWAssistedI2CStatus +#define EnableVGA_Access GetSCLKOverMCLKRatio -typedef struct _ATOM_MASTER_COMMAND_TABLE { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; -} ATOM_MASTER_COMMAND_TABLE; - -/****************************************************************************/ -/* Structures used in every command table */ -/****************************************************************************/ -typedef struct _ATOM_TABLE_ATTRIBUTE { +typedef struct _ATOM_MASTER_COMMAND_TABLE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; +}ATOM_MASTER_COMMAND_TABLE; + +/****************************************************************************/ +// Structures used in every command table +/****************************************************************************/ +typedef struct _ATOM_TABLE_ATTRIBUTE +{ #if ATOM_BIG_ENDIAN - USHORT UpdatedByUtility:1; /* [15]=Table updated by utility flag */ - USHORT PS_SizeInBytes:7; /* [14:8]=Size of parameter space in Bytes (multiple of a dword), */ - USHORT WS_SizeInBytes:8; /* [7:0]=Size of workspace in Bytes (in multiple of a dword), */ + USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag + USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), + USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), #else - USHORT WS_SizeInBytes:8; /* [7:0]=Size of workspace in Bytes (in multiple of a dword), */ - USHORT PS_SizeInBytes:7; /* [14:8]=Size of parameter space in Bytes (multiple of a dword), */ - USHORT UpdatedByUtility:1; /* [15]=Table updated by utility flag */ + USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), + USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), + USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag #endif -} ATOM_TABLE_ATTRIBUTE; - -typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS { - ATOM_TABLE_ATTRIBUTE sbfAccess; - USHORT susAccess; -} ATOM_TABLE_ATTRIBUTE_ACCESS; +}ATOM_TABLE_ATTRIBUTE; -/****************************************************************************/ -/* Common header for all command tables. */ -/* Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. */ -/* And the pointer actually points to this header. */ -/****************************************************************************/ -typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER { - ATOM_COMMON_TABLE_HEADER CommonHeader; - ATOM_TABLE_ATTRIBUTE TableAttribute; -} ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; +typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS +{ + ATOM_TABLE_ATTRIBUTE sbfAccess; + USHORT susAccess; +}ATOM_TABLE_ATTRIBUTE_ACCESS; + +/****************************************************************************/ +// Common header for all command tables. +// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. +// And the pointer actually points to this header. +/****************************************************************************/ +typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER +{ + ATOM_COMMON_TABLE_HEADER CommonHeader; + ATOM_TABLE_ATTRIBUTE TableAttribute; +}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; -/****************************************************************************/ -/* Structures used by ComputeMemoryEnginePLLTable */ -/****************************************************************************/ +/****************************************************************************/ +// Structures used by ComputeMemoryEnginePLLTable +/****************************************************************************/ #define COMPUTE_MEMORY_PLL_PARAM 1 #define COMPUTE_ENGINE_PLL_PARAM 2 -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS { - ULONG ulClock; /* When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div */ - UCHAR ucAction; /* 0:reserved //1:Memory //2:Engine */ - UCHAR ucReserved; /* may expand to return larger Fbdiv later */ - UCHAR ucFbDiv; /* return value */ - UCHAR ucPostDiv; /* return value */ -} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; - -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 { - ULONG ulClock; /* When return, [23:0] return real clock */ - UCHAR ucAction; /* 0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register */ - USHORT usFbDiv; /* return Feedback value to be written to register */ - UCHAR ucPostDiv; /* return post div to be written to register */ -} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS +{ + ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div + UCHAR ucAction; //0:reserved //1:Memory //2:Engine + UCHAR ucReserved; //may expand to return larger Fbdiv later + UCHAR ucFbDiv; //return value + UCHAR ucPostDiv; //return value +}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; + +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 +{ + ULONG ulClock; //When return, [23:0] return real clock + UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register + USHORT usFbDiv; //return Feedback value to be written to register + UCHAR ucPostDiv; //return post div to be written to register +}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS -#define SET_CLOCK_FREQ_MASK 0x00FFFFFF /* Clock change tables only take bit [23:0] as the requested clock value */ -#define USE_NON_BUS_CLOCK_MASK 0x01000000 /* Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) */ -#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 /* Only applicable to memory clock change, when set, using memory self refresh during clock transition */ -#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 /* Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change */ -#define FIRST_TIME_CHANGE_CLOCK 0x08000000 /* Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup */ -#define SKIP_SW_PROGRAM_PLL 0x10000000 /* Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL */ + +#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value +#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) +#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition +#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change +#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup +#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK -#define b3USE_NON_BUS_CLOCK_MASK 0x01 /* Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) */ -#define b3USE_MEMORY_SELF_REFRESH 0x02 /* Only applicable to memory clock change, when set, using memory self refresh during clock transition */ -#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 /* Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change */ -#define b3FIRST_TIME_CHANGE_CLOCK 0x08 /* Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup */ -#define b3SKIP_SW_PROGRAM_PLL 0x10 /* Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL */ +#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) +#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition +#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change +#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup +#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL -typedef struct _ATOM_COMPUTE_CLOCK_FREQ { +typedef struct _ATOM_COMPUTE_CLOCK_FREQ +{ #if ATOM_BIG_ENDIAN - ULONG ulComputeClockFlag:8; /* =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM */ - ULONG ulClockFreq:24; /* in unit of 10kHz */ + ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM + ULONG ulClockFreq:24; // in unit of 10kHz #else - ULONG ulClockFreq:24; /* in unit of 10kHz */ - ULONG ulComputeClockFlag:8; /* =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM */ + ULONG ulClockFreq:24; // in unit of 10kHz + ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM #endif -} ATOM_COMPUTE_CLOCK_FREQ; - -typedef struct _ATOM_S_MPLL_FB_DIVIDER { - USHORT usFbDivFrac; - USHORT usFbDiv; -} ATOM_S_MPLL_FB_DIVIDER; +}ATOM_COMPUTE_CLOCK_FREQ; -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 { - union { - ATOM_COMPUTE_CLOCK_FREQ ulClock; /* Input Parameter */ - ATOM_S_MPLL_FB_DIVIDER ulFbDiv; /* Output Parameter */ - }; - UCHAR ucRefDiv; /* Output Parameter */ - UCHAR ucPostDiv; /* Output Parameter */ - UCHAR ucCntlFlag; /* Output Parameter */ - UCHAR ucReserved; -} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; +typedef struct _ATOM_S_MPLL_FB_DIVIDER +{ + USHORT usFbDivFrac; + USHORT usFbDiv; +}ATOM_S_MPLL_FB_DIVIDER; -/* ucCntlFlag */ +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 +{ + union + { + ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter + ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter + }; + UCHAR ucRefDiv; //Output Parameter + UCHAR ucPostDiv; //Output Parameter + UCHAR ucCntlFlag; //Output Parameter + UCHAR ucReserved; +}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; + +// ucCntlFlag #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 +#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 -typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER { - ATOM_COMPUTE_CLOCK_FREQ ulClock; - ULONG ulReserved[2]; -} DYNAMICE_MEMORY_SETTINGS_PARAMETER; -typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER { - ATOM_COMPUTE_CLOCK_FREQ ulClock; - ULONG ulMemoryClock; - ULONG ulReserved; -} DYNAMICE_ENGINE_SETTINGS_PARAMETER; - -/****************************************************************************/ -/* Structures used by SetEngineClockTable */ -/****************************************************************************/ -typedef struct _SET_ENGINE_CLOCK_PARAMETERS { - ULONG ulTargetEngineClock; /* In 10Khz unit */ -} SET_ENGINE_CLOCK_PARAMETERS; - -typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION { - ULONG ulTargetEngineClock; /* In 10Khz unit */ - COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; -} SET_ENGINE_CLOCK_PS_ALLOCATION; +// V4 are only used for APU which PLL outside GPU +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 +{ +#if ATOM_BIG_ENDIAN + ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly + ULONG ulClock:24; //Input= target clock, output = actual clock +#else + ULONG ulClock:24; //Input= target clock, output = actual clock + ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly +#endif +}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; -/****************************************************************************/ -/* Structures used by SetMemoryClockTable */ -/****************************************************************************/ -typedef struct _SET_MEMORY_CLOCK_PARAMETERS { - ULONG ulTargetMemoryClock; /* In 10Khz unit */ -} SET_MEMORY_CLOCK_PARAMETERS; +typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER +{ + ATOM_COMPUTE_CLOCK_FREQ ulClock; + ULONG ulReserved[2]; +}DYNAMICE_MEMORY_SETTINGS_PARAMETER; -typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION { - ULONG ulTargetMemoryClock; /* In 10Khz unit */ - COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; -} SET_MEMORY_CLOCK_PS_ALLOCATION; +typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER +{ + ATOM_COMPUTE_CLOCK_FREQ ulClock; + ULONG ulMemoryClock; + ULONG ulReserved; +}DYNAMICE_ENGINE_SETTINGS_PARAMETER; + +/****************************************************************************/ +// Structures used by SetEngineClockTable +/****************************************************************************/ +typedef struct _SET_ENGINE_CLOCK_PARAMETERS +{ + ULONG ulTargetEngineClock; //In 10Khz unit +}SET_ENGINE_CLOCK_PARAMETERS; -/****************************************************************************/ -/* Structures used by ASIC_Init.ctb */ -/****************************************************************************/ -typedef struct _ASIC_INIT_PARAMETERS { - ULONG ulDefaultEngineClock; /* In 10Khz unit */ - ULONG ulDefaultMemoryClock; /* In 10Khz unit */ -} ASIC_INIT_PARAMETERS; +typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION +{ + ULONG ulTargetEngineClock; //In 10Khz unit + COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; +}SET_ENGINE_CLOCK_PS_ALLOCATION; + +/****************************************************************************/ +// Structures used by SetMemoryClockTable +/****************************************************************************/ +typedef struct _SET_MEMORY_CLOCK_PARAMETERS +{ + ULONG ulTargetMemoryClock; //In 10Khz unit +}SET_MEMORY_CLOCK_PARAMETERS; -typedef struct _ASIC_INIT_PS_ALLOCATION { - ASIC_INIT_PARAMETERS sASICInitClocks; - SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; /* Caller doesn't need to init this structure */ -} ASIC_INIT_PS_ALLOCATION; +typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION +{ + ULONG ulTargetMemoryClock; //In 10Khz unit + COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; +}SET_MEMORY_CLOCK_PS_ALLOCATION; + +/****************************************************************************/ +// Structures used by ASIC_Init.ctb +/****************************************************************************/ +typedef struct _ASIC_INIT_PARAMETERS +{ + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit +}ASIC_INIT_PARAMETERS; -/****************************************************************************/ -/* Structure used by DynamicClockGatingTable.ctb */ -/****************************************************************************/ -typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS { - UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ - UCHAR ucPadding[3]; -} DYNAMIC_CLOCK_GATING_PARAMETERS; +typedef struct _ASIC_INIT_PS_ALLOCATION +{ + ASIC_INIT_PARAMETERS sASICInitClocks; + SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure +}ASIC_INIT_PS_ALLOCATION; + +/****************************************************************************/ +// Structure used by DynamicClockGatingTable.ctb +/****************************************************************************/ +typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS +{ + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[3]; +}DYNAMIC_CLOCK_GATING_PARAMETERS; #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS -/****************************************************************************/ -/* Structure used by EnableASIC_StaticPwrMgtTable.ctb */ -/****************************************************************************/ -typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS { - UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ - UCHAR ucPadding[3]; -} ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; +/****************************************************************************/ +// Structure used by EnableASIC_StaticPwrMgtTable.ctb +/****************************************************************************/ +typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS +{ + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[3]; +}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS -/****************************************************************************/ -/* Structures used by DAC_LoadDetectionTable.ctb */ -/****************************************************************************/ -typedef struct _DAC_LOAD_DETECTION_PARAMETERS { - USHORT usDeviceID; /* {ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} */ - UCHAR ucDacType; /* {ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} */ - UCHAR ucMisc; /* Valid only when table revision =1.3 and above */ -} DAC_LOAD_DETECTION_PARAMETERS; +/****************************************************************************/ +// Structures used by DAC_LoadDetectionTable.ctb +/****************************************************************************/ +typedef struct _DAC_LOAD_DETECTION_PARAMETERS +{ + USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} + UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} + UCHAR ucMisc; //Valid only when table revision =1.3 and above +}DAC_LOAD_DETECTION_PARAMETERS; -/* DAC_LOAD_DETECTION_PARAMETERS.ucMisc */ +// DAC_LOAD_DETECTION_PARAMETERS.ucMisc #define DAC_LOAD_MISC_YPrPb 0x01 -typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION { - DAC_LOAD_DETECTION_PARAMETERS sDacload; - ULONG Reserved[2]; /* Don't set this one, allocation for EXT DAC */ -} DAC_LOAD_DETECTION_PS_ALLOCATION; - -/****************************************************************************/ -/* Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb */ -/****************************************************************************/ -typedef struct _DAC_ENCODER_CONTROL_PARAMETERS { - USHORT usPixelClock; /* in 10KHz; for bios convenient */ - UCHAR ucDacStandard; /* See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) */ - UCHAR ucAction; /* 0: turn off encoder */ - /* 1: setup and turn on encoder */ - /* 7: ATOM_ENCODER_INIT Initialize DAC */ -} DAC_ENCODER_CONTROL_PARAMETERS; +typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION +{ + DAC_LOAD_DETECTION_PARAMETERS sDacload; + ULONG Reserved[2];// Don't set this one, allocation for EXT DAC +}DAC_LOAD_DETECTION_PS_ALLOCATION; + +/****************************************************************************/ +// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb +/****************************************************************************/ +typedef struct _DAC_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder + // 7: ATOM_ENCODER_INIT Initialize DAC +}DAC_ENCODER_CONTROL_PARAMETERS; #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS -/****************************************************************************/ -/* Structures used by DIG1EncoderControlTable */ -/* DIG2EncoderControlTable */ -/* ExternalEncoderControlTable */ -/****************************************************************************/ -typedef struct _DIG_ENCODER_CONTROL_PARAMETERS { - USHORT usPixelClock; /* in 10KHz; for bios convenient */ - UCHAR ucConfig; - /* [2] Link Select: */ - /* =0: PHY linkA if bfLane<3 */ - /* =1: PHY linkB if bfLanes<3 */ - /* =0: PHY linkA+B if bfLanes=3 */ - /* [3] Transmitter Sel */ - /* =0: UNIPHY or PCIEPHY */ - /* =1: LVTMA */ - UCHAR ucAction; /* =0: turn off encoder */ - /* =1: turn on encoder */ - UCHAR ucEncoderMode; - /* =0: DP encoder */ - /* =1: LVDS encoder */ - /* =2: DVI encoder */ - /* =3: HDMI encoder */ - /* =4: SDVO encoder */ - UCHAR ucLaneNum; /* how many lanes to enable */ - UCHAR ucReserved[2]; -} DIG_ENCODER_CONTROL_PARAMETERS; +/****************************************************************************/ +// Structures used by DIG1EncoderControlTable +// DIG2EncoderControlTable +// ExternalEncoderControlTable +/****************************************************************************/ +typedef struct _DIG_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucConfig; + // [2] Link Select: + // =0: PHY linkA if bfLane<3 + // =1: PHY linkB if bfLanes<3 + // =0: PHY linkA+B if bfLanes=3 + // [3] Transmitter Sel + // =0: UNIPHY or PCIEPHY + // =1: LVTMA + UCHAR ucAction; // =0: turn off encoder + // =1: turn on encoder + UCHAR ucEncoderMode; + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder + // =3: HDMI encoder + // =4: SDVO encoder + UCHAR ucLaneNum; // how many lanes to enable + UCHAR ucReserved[2]; +}DIG_ENCODER_CONTROL_PARAMETERS; #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS -/* ucConfig */ +//ucConfig #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 @@ -539,52 +593,57 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS { #define ATOM_ENCODER_CONFIG_LVTMA 0x08 #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 -#define ATOM_ENCODER_CONFIG_DIGB 0x80 /* VBIOS Internal use, outside SW should set this bit=0 */ -/* ucAction */ -/* ATOM_ENABLE: Enable Encoder */ -/* ATOM_DISABLE: Disable Encoder */ +#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 +// ucAction +// ATOM_ENABLE: Enable Encoder +// ATOM_DISABLE: Disable Encoder -/* ucEncoderMode */ +//ucEncoderMode #define ATOM_ENCODER_MODE_DP 0 #define ATOM_ENCODER_MODE_LVDS 1 #define ATOM_ENCODER_MODE_DVI 2 #define ATOM_ENCODER_MODE_HDMI 3 #define ATOM_ENCODER_MODE_SDVO 4 +#define ATOM_ENCODER_MODE_DP_AUDIO 5 #define ATOM_ENCODER_MODE_TV 13 #define ATOM_ENCODER_MODE_CV 14 #define ATOM_ENCODER_MODE_CRT 15 -typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 { +typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 +{ #if ATOM_BIG_ENDIAN - UCHAR ucReserved1:2; - UCHAR ucTransmitterSel:2; /* =0: UniphyAB, =1: UniphyCD =2: UniphyEF */ - UCHAR ucLinkSel:1; /* =0: linkA/C/E =1: linkB/D/F */ - UCHAR ucReserved:1; - UCHAR ucDPLinkRate:1; /* =0: 1.62Ghz, =1: 2.7Ghz */ + UCHAR ucReserved1:2; + UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF + UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F + UCHAR ucReserved:1; + UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz #else - UCHAR ucDPLinkRate:1; /* =0: 1.62Ghz, =1: 2.7Ghz */ - UCHAR ucReserved:1; - UCHAR ucLinkSel:1; /* =0: linkA/C/E =1: linkB/D/F */ - UCHAR ucTransmitterSel:2; /* =0: UniphyAB, =1: UniphyCD =2: UniphyEF */ - UCHAR ucReserved1:2; + UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz + UCHAR ucReserved:1; + UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F + UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF + UCHAR ucReserved1:2; #endif -} ATOM_DIG_ENCODER_CONFIG_V2; +}ATOM_DIG_ENCODER_CONFIG_V2; -typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 { - USHORT usPixelClock; /* in 10KHz; for bios convenient */ - ATOM_DIG_ENCODER_CONFIG_V2 acConfig; - UCHAR ucAction; - UCHAR ucEncoderMode; - /* =0: DP encoder */ - /* =1: LVDS encoder */ - /* =2: DVI encoder */ - /* =3: HDMI encoder */ - /* =4: SDVO encoder */ - UCHAR ucLaneNum; /* how many lanes to enable */ - UCHAR ucReserved[2]; -} DIG_ENCODER_CONTROL_PARAMETERS_V2; -/* ucConfig */ +typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + ATOM_DIG_ENCODER_CONFIG_V2 acConfig; + UCHAR ucAction; + UCHAR ucEncoderMode; + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder + // =3: HDMI encoder + // =4: SDVO encoder + UCHAR ucLaneNum; // how many lanes to enable + UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS + UCHAR ucReserved; +}DIG_ENCODER_CONTROL_PARAMETERS_V2; + +//ucConfig #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 @@ -596,58 +655,122 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 { #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 -/****************************************************************************/ -/* Structures used by UNIPHYTransmitterControlTable */ -/* LVTMATransmitterControlTable */ -/* DVOOutputControlTable */ -/****************************************************************************/ -typedef struct _ATOM_DP_VS_MODE { - UCHAR ucLaneSel; - UCHAR ucLaneSet; -} ATOM_DP_VS_MODE; - -typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS { - union { - USHORT usPixelClock; /* in 10KHz; for bios convenient */ - USHORT usInitInfo; /* when init uniphy,lower 8bit is used for connector type defined in objectid.h */ - ATOM_DP_VS_MODE asMode; /* DP Voltage swing mode */ +// ucAction: +// ATOM_DISABLE +// ATOM_ENABLE +#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 +#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 +#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a +#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b +#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c +#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d +#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e +#define ATOM_ENCODER_CMD_SETUP 0x0f + +// ucStatus +#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 +#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 + +// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver +typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 +{ +#if ATOM_BIG_ENDIAN + UCHAR ucReserved1:1; + UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F + UCHAR ucReserved:3; + UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz +#else + UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz + UCHAR ucReserved:3; + UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F + UCHAR ucReserved1:1; +#endif +}ATOM_DIG_ENCODER_CONFIG_V3; + +#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 + + +typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + ATOM_DIG_ENCODER_CONFIG_V3 acConfig; + UCHAR ucAction; + UCHAR ucEncoderMode; + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder + // =3: HDMI encoder + // =4: SDVO encoder + // =5: DP audio + UCHAR ucLaneNum; // how many lanes to enable + UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP + UCHAR ucReserved; +}DIG_ENCODER_CONTROL_PARAMETERS_V3; + + +// define ucBitPerColor: +#define PANEL_BPC_UNDEFINE 0x00 +#define PANEL_6BIT_PER_COLOR 0x01 +#define PANEL_8BIT_PER_COLOR 0x02 +#define PANEL_10BIT_PER_COLOR 0x03 +#define PANEL_12BIT_PER_COLOR 0x04 +#define PANEL_16BIT_PER_COLOR 0x05 + +/****************************************************************************/ +// Structures used by UNIPHYTransmitterControlTable +// LVTMATransmitterControlTable +// DVOOutputControlTable +/****************************************************************************/ +typedef struct _ATOM_DP_VS_MODE +{ + UCHAR ucLaneSel; + UCHAR ucLaneSet; +}ATOM_DP_VS_MODE; + +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS +{ + union + { + USHORT usPixelClock; // in 10KHz; for bios convenient + USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h + ATOM_DP_VS_MODE asMode; // DP Voltage swing mode }; - UCHAR ucConfig; - /* [0]=0: 4 lane Link, */ - /* =1: 8 lane Link ( Dual Links TMDS ) */ - /* [1]=0: InCoherent mode */ - /* =1: Coherent Mode */ - /* [2] Link Select: */ - /* =0: PHY linkA if bfLane<3 */ - /* =1: PHY linkB if bfLanes<3 */ - /* =0: PHY linkA+B if bfLanes=3 */ - /* [5:4]PCIE lane Sel */ - /* =0: lane 0~3 or 0~7 */ - /* =1: lane 4~7 */ - /* =2: lane 8~11 or 8~15 */ - /* =3: lane 12~15 */ - UCHAR ucAction; /* =0: turn off encoder */ - /* =1: turn on encoder */ - UCHAR ucReserved[4]; -} DIG_TRANSMITTER_CONTROL_PARAMETERS; - -#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS - -/* ucInitInfo */ -#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff - -/* ucConfig */ + UCHAR ucConfig; + // [0]=0: 4 lane Link, + // =1: 8 lane Link ( Dual Links TMDS ) + // [1]=0: InCoherent mode + // =1: Coherent Mode + // [2] Link Select: + // =0: PHY linkA if bfLane<3 + // =1: PHY linkB if bfLanes<3 + // =0: PHY linkA+B if bfLanes=3 + // [5:4]PCIE lane Sel + // =0: lane 0~3 or 0~7 + // =1: lane 4~7 + // =2: lane 8~11 or 8~15 + // =3: lane 12~15 + UCHAR ucAction; // =0: turn off encoder + // =1: turn on encoder + UCHAR ucReserved[4]; +}DIG_TRANSMITTER_CONTROL_PARAMETERS; + +#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS + +//ucInitInfo +#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff + +//ucConfig #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 -#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 +#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 -#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */ -#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */ -#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */ +#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE +#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE +#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 @@ -661,7 +784,7 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS { #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 -/* ucAction */ +//ucAction #define ATOM_TRANSMITTER_ACTION_DISABLE 0 #define ATOM_TRANSMITTER_ACTION_ENABLE 1 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 @@ -674,93 +797,168 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS { #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 #define ATOM_TRANSMITTER_ACTION_SETUP 10 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 +#define ATOM_TRANSMITTER_ACTION_POWER_ON 12 +#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 -/* Following are used for DigTransmitterControlTable ver1.2 */ -typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 { +// Following are used for DigTransmitterControlTable ver1.2 +typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 +{ #if ATOM_BIG_ENDIAN - UCHAR ucTransmitterSel:2; /* bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) */ - /* =1 Dig Transmitter 2 ( Uniphy CD ) */ - /* =2 Dig Transmitter 3 ( Uniphy EF ) */ - UCHAR ucReserved:1; - UCHAR fDPConnector:1; /* bit4=0: DP connector =1: None DP connector */ - UCHAR ucEncoderSel:1; /* bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) */ - UCHAR ucLinkSel:1; /* bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E */ - /* =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F */ - - UCHAR fCoherentMode:1; /* bit1=1: Coherent Mode ( for DVI/HDMI mode ) */ - UCHAR fDualLinkConnector:1; /* bit0=1: Dual Link DVI connector */ + UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) + // =1 Dig Transmitter 2 ( Uniphy CD ) + // =2 Dig Transmitter 3 ( Uniphy EF ) + UCHAR ucReserved:1; + UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector + UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) + UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E + // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F + + UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) + UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector #else - UCHAR fDualLinkConnector:1; /* bit0=1: Dual Link DVI connector */ - UCHAR fCoherentMode:1; /* bit1=1: Coherent Mode ( for DVI/HDMI mode ) */ - UCHAR ucLinkSel:1; /* bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E */ - /* =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F */ - UCHAR ucEncoderSel:1; /* bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) */ - UCHAR fDPConnector:1; /* bit4=0: DP connector =1: None DP connector */ - UCHAR ucReserved:1; - UCHAR ucTransmitterSel:2; /* bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) */ - /* =1 Dig Transmitter 2 ( Uniphy CD ) */ - /* =2 Dig Transmitter 3 ( Uniphy EF ) */ + UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector + UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) + UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E + // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F + UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) + UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector + UCHAR ucReserved:1; + UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) + // =1 Dig Transmitter 2 ( Uniphy CD ) + // =2 Dig Transmitter 3 ( Uniphy EF ) #endif -} ATOM_DIG_TRANSMITTER_CONFIG_V2; +}ATOM_DIG_TRANSMITTER_CONFIG_V2; -/* ucConfig */ -/* Bit0 */ +//ucConfig +//Bit0 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 -/* Bit1 */ +//Bit1 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 -/* Bit2 */ +//Bit2 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 -#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 +#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 -/* Bit3 */ +// Bit3 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 -#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 /* only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP */ -#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 /* only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP */ +#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP +#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP -/* Bit4 */ +// Bit4 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 -/* Bit7:6 */ +// Bit7:6 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 -#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 /* AB */ -#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 /* CD */ -#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 /* EF */ - -typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 { - union { - USHORT usPixelClock; /* in 10KHz; for bios convenient */ - USHORT usInitInfo; /* when init uniphy,lower 8bit is used for connector type defined in objectid.h */ - ATOM_DP_VS_MODE asMode; /* DP Voltage swing mode */ +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF + +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 +{ + union + { + USHORT usPixelClock; // in 10KHz; for bios convenient + USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h + ATOM_DP_VS_MODE asMode; // DP Voltage swing mode }; - ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; - UCHAR ucAction; /* define as ATOM_TRANSMITER_ACTION_XXX */ - UCHAR ucReserved[4]; -} DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; + ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; + UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX + UCHAR ucReserved[4]; +}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; -/****************************************************************************/ -/* Structures used by DAC1OuputControlTable */ -/* DAC2OuputControlTable */ -/* LVTMAOutputControlTable (Before DEC30) */ -/* TMDSAOutputControlTable (Before DEC30) */ -/****************************************************************************/ -typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS { - UCHAR ucAction; /* Possible input:ATOM_ENABLE||ATOMDISABLE */ - /* When the display is LCD, in addition to above: */ - /* ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| */ - /* ATOM_LCD_SELFTEST_STOP */ +typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 +{ +#if ATOM_BIG_ENDIAN + UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) + // =1 Dig Transmitter 2 ( Uniphy CD ) + // =2 Dig Transmitter 3 ( Uniphy EF ) + UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 + UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F + UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E + // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F + UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) + UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector +#else + UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector + UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) + UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E + // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F + UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F + UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 + UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) + // =1 Dig Transmitter 2 ( Uniphy CD ) + // =2 Dig Transmitter 3 ( Uniphy EF ) +#endif +}ATOM_DIG_TRANSMITTER_CONFIG_V3; - UCHAR aucPadding[3]; /* padding to DWORD aligned */ -} DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 +{ + union + { + USHORT usPixelClock; // in 10KHz; for bios convenient + USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h + ATOM_DP_VS_MODE asMode; // DP Voltage swing mode + }; + ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; + UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX + UCHAR ucLaneNum; + UCHAR ucReserved[3]; +}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; + +//ucConfig +//Bit0 +#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 + +//Bit1 +#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 + +//Bit2 +#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 +#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 +#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 + +// Bit3 +#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 +#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 +#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 + +// Bit5:4 +#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 +#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 +#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 +#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 + +// Bit7:6 +#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 +#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB +#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD +#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF + +/****************************************************************************/ +// Structures used by DAC1OuputControlTable +// DAC2OuputControlTable +// LVTMAOutputControlTable (Before DEC30) +// TMDSAOutputControlTable (Before DEC30) +/****************************************************************************/ +typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +{ + UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE + // When the display is LCD, in addition to above: + // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| + // ATOM_LCD_SELFTEST_STOP + + UCHAR aucPadding[3]; // padding to DWORD aligned +}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS + +#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION -#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS @@ -782,397 +980,550 @@ typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS { #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS -/****************************************************************************/ -/* Structures used by BlankCRTCTable */ -/****************************************************************************/ -typedef struct _BLANK_CRTC_PARAMETERS { - UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ - UCHAR ucBlanking; /* ATOM_BLANKING or ATOM_BLANKINGOFF */ - USHORT usBlackColorRCr; - USHORT usBlackColorGY; - USHORT usBlackColorBCb; -} BLANK_CRTC_PARAMETERS; +/****************************************************************************/ +// Structures used by BlankCRTCTable +/****************************************************************************/ +typedef struct _BLANK_CRTC_PARAMETERS +{ + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF + USHORT usBlackColorRCr; + USHORT usBlackColorGY; + USHORT usBlackColorBCb; +}BLANK_CRTC_PARAMETERS; #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS -/****************************************************************************/ -/* Structures used by EnableCRTCTable */ -/* EnableCRTCMemReqTable */ -/* UpdateCRTC_DoubleBufferRegistersTable */ -/****************************************************************************/ -typedef struct _ENABLE_CRTC_PARAMETERS { - UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ - UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ - UCHAR ucPadding[2]; -} ENABLE_CRTC_PARAMETERS; +/****************************************************************************/ +// Structures used by EnableCRTCTable +// EnableCRTCMemReqTable +// UpdateCRTC_DoubleBufferRegistersTable +/****************************************************************************/ +typedef struct _ENABLE_CRTC_PARAMETERS +{ + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[2]; +}ENABLE_CRTC_PARAMETERS; #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS -/****************************************************************************/ -/* Structures used by SetCRTC_OverScanTable */ -/****************************************************************************/ -typedef struct _SET_CRTC_OVERSCAN_PARAMETERS { - USHORT usOverscanRight; /* right */ - USHORT usOverscanLeft; /* left */ - USHORT usOverscanBottom; /* bottom */ - USHORT usOverscanTop; /* top */ - UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ - UCHAR ucPadding[3]; -} SET_CRTC_OVERSCAN_PARAMETERS; +/****************************************************************************/ +// Structures used by SetCRTC_OverScanTable +/****************************************************************************/ +typedef struct _SET_CRTC_OVERSCAN_PARAMETERS +{ + USHORT usOverscanRight; // right + USHORT usOverscanLeft; // left + USHORT usOverscanBottom; // bottom + USHORT usOverscanTop; // top + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucPadding[3]; +}SET_CRTC_OVERSCAN_PARAMETERS; #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS -/****************************************************************************/ -/* Structures used by SetCRTC_ReplicationTable */ -/****************************************************************************/ -typedef struct _SET_CRTC_REPLICATION_PARAMETERS { - UCHAR ucH_Replication; /* horizontal replication */ - UCHAR ucV_Replication; /* vertical replication */ - UCHAR usCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ - UCHAR ucPadding; -} SET_CRTC_REPLICATION_PARAMETERS; +/****************************************************************************/ +// Structures used by SetCRTC_ReplicationTable +/****************************************************************************/ +typedef struct _SET_CRTC_REPLICATION_PARAMETERS +{ + UCHAR ucH_Replication; // horizontal replication + UCHAR ucV_Replication; // vertical replication + UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucPadding; +}SET_CRTC_REPLICATION_PARAMETERS; #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS -/****************************************************************************/ -/* Structures used by SelectCRTC_SourceTable */ -/****************************************************************************/ -typedef struct _SELECT_CRTC_SOURCE_PARAMETERS { - UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ - UCHAR ucDevice; /* ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... */ - UCHAR ucPadding[2]; -} SELECT_CRTC_SOURCE_PARAMETERS; +/****************************************************************************/ +// Structures used by SelectCRTC_SourceTable +/****************************************************************************/ +typedef struct _SELECT_CRTC_SOURCE_PARAMETERS +{ + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... + UCHAR ucPadding[2]; +}SELECT_CRTC_SOURCE_PARAMETERS; #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS -typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 { - UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ - UCHAR ucEncoderID; /* DAC1/DAC2/TVOUT/DIG1/DIG2/DVO */ - UCHAR ucEncodeMode; /* Encoding mode, only valid when using DIG1/DIG2/DVO */ - UCHAR ucPadding; -} SELECT_CRTC_SOURCE_PARAMETERS_V2; - -/* ucEncoderID */ -/* #define ASIC_INT_DAC1_ENCODER_ID 0x00 */ -/* #define ASIC_INT_TV_ENCODER_ID 0x02 */ -/* #define ASIC_INT_DIG1_ENCODER_ID 0x03 */ -/* #define ASIC_INT_DAC2_ENCODER_ID 0x04 */ -/* #define ASIC_EXT_TV_ENCODER_ID 0x06 */ -/* #define ASIC_INT_DVO_ENCODER_ID 0x07 */ -/* #define ASIC_INT_DIG2_ENCODER_ID 0x09 */ -/* #define ASIC_EXT_DIG_ENCODER_ID 0x05 */ - -/* ucEncodeMode */ -/* #define ATOM_ENCODER_MODE_DP 0 */ -/* #define ATOM_ENCODER_MODE_LVDS 1 */ -/* #define ATOM_ENCODER_MODE_DVI 2 */ -/* #define ATOM_ENCODER_MODE_HDMI 3 */ -/* #define ATOM_ENCODER_MODE_SDVO 4 */ -/* #define ATOM_ENCODER_MODE_TV 13 */ -/* #define ATOM_ENCODER_MODE_CV 14 */ -/* #define ATOM_ENCODER_MODE_CRT 15 */ - -/****************************************************************************/ -/* Structures used by SetPixelClockTable */ -/* GetPixelClockTable */ -/****************************************************************************/ -/* Major revision=1., Minor revision=1 */ -typedef struct _PIXEL_CLOCK_PARAMETERS { - USHORT usPixelClock; /* in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) */ - /* 0 means disable PPLL */ - USHORT usRefDiv; /* Reference divider */ - USHORT usFbDiv; /* feedback divider */ - UCHAR ucPostDiv; /* post divider */ - UCHAR ucFracFbDiv; /* fractional feedback divider */ - UCHAR ucPpll; /* ATOM_PPLL1 or ATOM_PPL2 */ - UCHAR ucRefDivSrc; /* ATOM_PJITTER or ATO_NONPJITTER */ - UCHAR ucCRTC; /* Which CRTC uses this Ppll */ - UCHAR ucPadding; -} PIXEL_CLOCK_PARAMETERS; - -/* Major revision=1., Minor revision=2, add ucMiscIfno */ -/* ucMiscInfo: */ +typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 +{ + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO + UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO + UCHAR ucPadding; +}SELECT_CRTC_SOURCE_PARAMETERS_V2; + +//ucEncoderID +//#define ASIC_INT_DAC1_ENCODER_ID 0x00 +//#define ASIC_INT_TV_ENCODER_ID 0x02 +//#define ASIC_INT_DIG1_ENCODER_ID 0x03 +//#define ASIC_INT_DAC2_ENCODER_ID 0x04 +//#define ASIC_EXT_TV_ENCODER_ID 0x06 +//#define ASIC_INT_DVO_ENCODER_ID 0x07 +//#define ASIC_INT_DIG2_ENCODER_ID 0x09 +//#define ASIC_EXT_DIG_ENCODER_ID 0x05 + +//ucEncodeMode +//#define ATOM_ENCODER_MODE_DP 0 +//#define ATOM_ENCODER_MODE_LVDS 1 +//#define ATOM_ENCODER_MODE_DVI 2 +//#define ATOM_ENCODER_MODE_HDMI 3 +//#define ATOM_ENCODER_MODE_SDVO 4 +//#define ATOM_ENCODER_MODE_TV 13 +//#define ATOM_ENCODER_MODE_CV 14 +//#define ATOM_ENCODER_MODE_CRT 15 + +/****************************************************************************/ +// Structures used by SetPixelClockTable +// GetPixelClockTable +/****************************************************************************/ +//Major revision=1., Minor revision=1 +typedef struct _PIXEL_CLOCK_PARAMETERS +{ + USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) + // 0 means disable PPLL + USHORT usRefDiv; // Reference divider + USHORT usFbDiv; // feedback divider + UCHAR ucPostDiv; // post divider + UCHAR ucFracFbDiv; // fractional feedback divider + UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 + UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER + UCHAR ucCRTC; // Which CRTC uses this Ppll + UCHAR ucPadding; +}PIXEL_CLOCK_PARAMETERS; + +//Major revision=1., Minor revision=2, add ucMiscIfno +//ucMiscInfo: #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 #define MISC_DEVICE_INDEX_MASK 0xF0 #define MISC_DEVICE_INDEX_SHIFT 4 -typedef struct _PIXEL_CLOCK_PARAMETERS_V2 { - USHORT usPixelClock; /* in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) */ - /* 0 means disable PPLL */ - USHORT usRefDiv; /* Reference divider */ - USHORT usFbDiv; /* feedback divider */ - UCHAR ucPostDiv; /* post divider */ - UCHAR ucFracFbDiv; /* fractional feedback divider */ - UCHAR ucPpll; /* ATOM_PPLL1 or ATOM_PPL2 */ - UCHAR ucRefDivSrc; /* ATOM_PJITTER or ATO_NONPJITTER */ - UCHAR ucCRTC; /* Which CRTC uses this Ppll */ - UCHAR ucMiscInfo; /* Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog */ -} PIXEL_CLOCK_PARAMETERS_V2; - -/* Major revision=1., Minor revision=3, structure/definition change */ -/* ucEncoderMode: */ -/* ATOM_ENCODER_MODE_DP */ -/* ATOM_ENOCDER_MODE_LVDS */ -/* ATOM_ENOCDER_MODE_DVI */ -/* ATOM_ENOCDER_MODE_HDMI */ -/* ATOM_ENOCDER_MODE_SDVO */ -/* ATOM_ENCODER_MODE_TV 13 */ -/* ATOM_ENCODER_MODE_CV 14 */ -/* ATOM_ENCODER_MODE_CRT 15 */ - -/* ucDVOConfig */ -/* #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 */ -/* #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 */ -/* #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 */ -/* #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c */ -/* #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 */ -/* #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 */ -/* #define DVO_ENCODER_CONFIG_24BIT 0x08 */ - -/* ucMiscInfo: also changed, see below */ +typedef struct _PIXEL_CLOCK_PARAMETERS_V2 +{ + USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) + // 0 means disable PPLL + USHORT usRefDiv; // Reference divider + USHORT usFbDiv; // feedback divider + UCHAR ucPostDiv; // post divider + UCHAR ucFracFbDiv; // fractional feedback divider + UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 + UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER + UCHAR ucCRTC; // Which CRTC uses this Ppll + UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog +}PIXEL_CLOCK_PARAMETERS_V2; + +//Major revision=1., Minor revision=3, structure/definition change +//ucEncoderMode: +//ATOM_ENCODER_MODE_DP +//ATOM_ENOCDER_MODE_LVDS +//ATOM_ENOCDER_MODE_DVI +//ATOM_ENOCDER_MODE_HDMI +//ATOM_ENOCDER_MODE_SDVO +//ATOM_ENCODER_MODE_TV 13 +//ATOM_ENCODER_MODE_CV 14 +//ATOM_ENCODER_MODE_CRT 15 + +//ucDVOConfig +//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 +//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 +//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 +//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c +//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 +//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 +//#define DVO_ENCODER_CONFIG_24BIT 0x08 + +//ucMiscInfo: also changed, see below #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 #define PIXEL_CLOCK_MISC_VGA_MODE 0x02 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 +#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 +// V1.4 for RoadRunner +#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 +#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 -typedef struct _PIXEL_CLOCK_PARAMETERS_V3 { - USHORT usPixelClock; /* in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) */ - /* 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. */ - USHORT usRefDiv; /* Reference divider */ - USHORT usFbDiv; /* feedback divider */ - UCHAR ucPostDiv; /* post divider */ - UCHAR ucFracFbDiv; /* fractional feedback divider */ - UCHAR ucPpll; /* ATOM_PPLL1 or ATOM_PPL2 */ - UCHAR ucTransmitterId; /* graphic encoder id defined in objectId.h */ - union { - UCHAR ucEncoderMode; /* encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ */ - UCHAR ucDVOConfig; /* when use DVO, need to know SDR/DDR, 12bit or 24bit */ +typedef struct _PIXEL_CLOCK_PARAMETERS_V3 +{ + USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) + // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. + USHORT usRefDiv; // Reference divider + USHORT usFbDiv; // feedback divider + UCHAR ucPostDiv; // post divider + UCHAR ucFracFbDiv; // fractional feedback divider + UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 + UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h + union + { + UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ + UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit }; - UCHAR ucMiscInfo; /* bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel */ - /* bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source */ -} PIXEL_CLOCK_PARAMETERS_V3; + UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel + // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source + // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider +}PIXEL_CLOCK_PARAMETERS_V3; #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST -/****************************************************************************/ -/* Structures used by AdjustDisplayPllTable */ -/****************************************************************************/ -typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS { +typedef struct _PIXEL_CLOCK_PARAMETERS_V5 +{ + UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to + // drive the pixel clock. not used for DCPLL case. + union{ + UCHAR ucReserved; + UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. + }; + USHORT usPixelClock; // target the pixel clock to drive the CRTC timing + // 0 means disable PPLL/DCPLL. + USHORT usFbDiv; // feedback divider integer part. + UCHAR ucPostDiv; // post divider. + UCHAR ucRefDiv; // Reference divider + UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL + UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, + // indicate which graphic encoder will be used. + UCHAR ucEncoderMode; // Encoder mode: + UCHAR ucMiscInfo; // bit[0]= Force program PPLL + // bit[1]= when VGA timing is used. + // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp + // bit[4]= RefClock source for PPLL. + // =0: XTLAIN( default mode ) + // =1: other external clock source, which is pre-defined + // by VBIOS depend on the feature required. + // bit[7:5]: reserved. + ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) + +}PIXEL_CLOCK_PARAMETERS_V5; + +#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 +#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 +#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c +#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 +#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 +#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 +#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 + +typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 +{ + PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; +}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; + +typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 +{ + UCHAR ucStatus; + UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock + UCHAR ucReserved[2]; +}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; + +typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 +{ + PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; +}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; + +/****************************************************************************/ +// Structures used by AdjustDisplayPllTable +/****************************************************************************/ +typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS +{ USHORT usPixelClock; UCHAR ucTransmitterID; UCHAR ucEncodeMode; - union { - UCHAR ucDVOConfig; /* if DVO, need passing link rate and output 12bitlow or 24bit */ - UCHAR ucConfig; /* if none DVO, not defined yet */ + union + { + UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit + UCHAR ucConfig; //if none DVO, not defined yet }; UCHAR ucReserved[3]; -} ADJUST_DISPLAY_PLL_PARAMETERS; +}ADJUST_DISPLAY_PLL_PARAMETERS; #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 - #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS -/****************************************************************************/ -/* Structures used by EnableYUVTable */ -/****************************************************************************/ -typedef struct _ENABLE_YUV_PARAMETERS { - UCHAR ucEnable; /* ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) */ - UCHAR ucCRTC; /* Which CRTC needs this YUV or RGB format */ - UCHAR ucPadding[2]; -} ENABLE_YUV_PARAMETERS; +typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 +{ + USHORT usPixelClock; // target pixel clock + UCHAR ucTransmitterID; // transmitter id defined in objectid.h + UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI + UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX + UCHAR ucReserved[3]; +}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; + +// usDispPllConfig v1.2 for RoadRunner +#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS +#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI +#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS + + +typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 +{ + ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc + UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) + UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider + UCHAR ucReserved[2]; +}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; + +typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 +{ + union + { + ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; + ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; + }; +} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; + +/****************************************************************************/ +// Structures used by EnableYUVTable +/****************************************************************************/ +typedef struct _ENABLE_YUV_PARAMETERS +{ + UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) + UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format + UCHAR ucPadding[2]; +}ENABLE_YUV_PARAMETERS; #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS -/****************************************************************************/ -/* Structures used by GetMemoryClockTable */ -/****************************************************************************/ -typedef struct _GET_MEMORY_CLOCK_PARAMETERS { - ULONG ulReturnMemoryClock; /* current memory speed in 10KHz unit */ +/****************************************************************************/ +// Structures used by GetMemoryClockTable +/****************************************************************************/ +typedef struct _GET_MEMORY_CLOCK_PARAMETERS +{ + ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit } GET_MEMORY_CLOCK_PARAMETERS; #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS -/****************************************************************************/ -/* Structures used by GetEngineClockTable */ -/****************************************************************************/ -typedef struct _GET_ENGINE_CLOCK_PARAMETERS { - ULONG ulReturnEngineClock; /* current engine speed in 10KHz unit */ +/****************************************************************************/ +// Structures used by GetEngineClockTable +/****************************************************************************/ +typedef struct _GET_ENGINE_CLOCK_PARAMETERS +{ + ULONG ulReturnEngineClock; // current engine speed in 10KHz unit } GET_ENGINE_CLOCK_PARAMETERS; #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS -/****************************************************************************/ -/* Following Structures and constant may be obsolete */ -/****************************************************************************/ -/* Maxium 8 bytes,the data read in will be placed in the parameter space. */ -/* Read operaion successeful when the paramter space is non-zero, otherwise read operation failed */ -typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS { - USHORT usPrescale; /* Ratio between Engine clock and I2C clock */ - USHORT usVRAMAddress; /* Adress in Frame Buffer where to pace raw EDID */ - USHORT usStatus; /* When use output: lower byte EDID checksum, high byte hardware status */ - /* WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte */ - UCHAR ucSlaveAddr; /* Read from which slave */ - UCHAR ucLineNumber; /* Read from which HW assisted line */ -} READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; +/****************************************************************************/ +// Following Structures and constant may be obsolete +/****************************************************************************/ +//Maxium 8 bytes,the data read in will be placed in the parameter space. +//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed +typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS +{ + USHORT usPrescale; //Ratio between Engine clock and I2C clock + USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID + USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status + //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte + UCHAR ucSlaveAddr; //Read from which slave + UCHAR ucLineNumber; //Read from which HW assisted line +}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS + #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 -typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS { - USHORT usPrescale; /* Ratio between Engine clock and I2C clock */ - USHORT usByteOffset; /* Write to which byte */ - /* Upper portion of usByteOffset is Format of data */ - /* 1bytePS+offsetPS */ - /* 2bytesPS+offsetPS */ - /* blockID+offsetPS */ - /* blockID+offsetID */ - /* blockID+counterID+offsetID */ - UCHAR ucData; /* PS data1 */ - UCHAR ucStatus; /* Status byte 1=success, 2=failure, Also is used as PS data2 */ - UCHAR ucSlaveAddr; /* Write to which slave */ - UCHAR ucLineNumber; /* Write from which HW assisted line */ -} WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; +typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS +{ + USHORT usPrescale; //Ratio between Engine clock and I2C clock + USHORT usByteOffset; //Write to which byte + //Upper portion of usByteOffset is Format of data + //1bytePS+offsetPS + //2bytesPS+offsetPS + //blockID+offsetPS + //blockID+offsetID + //blockID+counterID+offsetID + UCHAR ucData; //PS data1 + UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 + UCHAR ucSlaveAddr; //Write to which slave + UCHAR ucLineNumber; //Write from which HW assisted line +}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS -typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS { - USHORT usPrescale; /* Ratio between Engine clock and I2C clock */ - UCHAR ucSlaveAddr; /* Write to which slave */ - UCHAR ucLineNumber; /* Write from which HW assisted line */ -} SET_UP_HW_I2C_DATA_PARAMETERS; +typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS +{ + USHORT usPrescale; //Ratio between Engine clock and I2C clock + UCHAR ucSlaveAddr; //Write to which slave + UCHAR ucLineNumber; //Write from which HW assisted line +}SET_UP_HW_I2C_DATA_PARAMETERS; + /**************************************************************************/ #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS -/****************************************************************************/ -/* Structures used by PowerConnectorDetectionTable */ -/****************************************************************************/ -typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS { - UCHAR ucPowerConnectorStatus; /* Used for return value 0: detected, 1:not detected */ - UCHAR ucPwrBehaviorId; - USHORT usPwrBudget; /* how much power currently boot to in unit of watt */ -} POWER_CONNECTOR_DETECTION_PARAMETERS; - -typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION { - UCHAR ucPowerConnectorStatus; /* Used for return value 0: detected, 1:not detected */ - UCHAR ucReserved; - USHORT usPwrBudget; /* how much power currently boot to in unit of watt */ - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; -} POWER_CONNECTOR_DETECTION_PS_ALLOCATION; +/****************************************************************************/ +// Structures used by PowerConnectorDetectionTable +/****************************************************************************/ +typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS +{ + UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected + UCHAR ucPwrBehaviorId; + USHORT usPwrBudget; //how much power currently boot to in unit of watt +}POWER_CONNECTOR_DETECTION_PARAMETERS; + +typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION +{ + UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected + UCHAR ucReserved; + USHORT usPwrBudget; //how much power currently boot to in unit of watt + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; +}POWER_CONNECTOR_DETECTION_PS_ALLOCATION; /****************************LVDS SS Command Table Definitions**********************/ -/****************************************************************************/ -/* Structures used by EnableSpreadSpectrumOnPPLLTable */ -/****************************************************************************/ -typedef struct _ENABLE_LVDS_SS_PARAMETERS { - USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */ - UCHAR ucSpreadSpectrumStepSize_Delay; /* bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY */ - UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ - UCHAR ucPadding[3]; -} ENABLE_LVDS_SS_PARAMETERS; - -/* ucTableFormatRevision=1,ucTableContentRevision=2 */ -typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 { - USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */ - UCHAR ucSpreadSpectrumStep; /* */ - UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ - UCHAR ucSpreadSpectrumDelay; - UCHAR ucSpreadSpectrumRange; - UCHAR ucPadding; -} ENABLE_LVDS_SS_PARAMETERS_V2; - -/* This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. */ -typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL { - USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */ - UCHAR ucSpreadSpectrumStep; /* */ - UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ - UCHAR ucSpreadSpectrumDelay; - UCHAR ucSpreadSpectrumRange; - UCHAR ucPpll; /* ATOM_PPLL1/ATOM_PPLL2 */ -} ENABLE_SPREAD_SPECTRUM_ON_PPLL; +/****************************************************************************/ +// Structures used by EnableSpreadSpectrumOnPPLLTable +/****************************************************************************/ +typedef struct _ENABLE_LVDS_SS_PARAMETERS +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD + UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY + UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[3]; +}ENABLE_LVDS_SS_PARAMETERS; + +//ucTableFormatRevision=1,ucTableContentRevision=2 +typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD + UCHAR ucSpreadSpectrumStep; // + UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE + UCHAR ucSpreadSpectrumDelay; + UCHAR ucSpreadSpectrumRange; + UCHAR ucPadding; +}ENABLE_LVDS_SS_PARAMETERS_V2; + +//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. +typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD + UCHAR ucSpreadSpectrumStep; // + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucSpreadSpectrumDelay; + UCHAR ucSpreadSpectrumRange; + UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 +}ENABLE_SPREAD_SPECTRUM_ON_PPLL; + +typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. + // Bit[1]: 1-Ext. 0-Int. + // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL + // Bits[7:4] reserved + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] + USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC +}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; + +#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 +#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 +#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 +#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c +#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 +#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 +#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 +#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF +#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 +#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 +#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL /**************************************************************************/ -typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION { - PIXEL_CLOCK_PARAMETERS sPCLKInput; - ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved; /* Caller doesn't need to init this portion */ -} SET_PIXEL_CLOCK_PS_ALLOCATION; +typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION +{ + PIXEL_CLOCK_PARAMETERS sPCLKInput; + ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion +}SET_PIXEL_CLOCK_PS_ALLOCATION; #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION -/****************************************************************************/ -/* Structures used by ### */ -/****************************************************************************/ -typedef struct _MEMORY_TRAINING_PARAMETERS { - ULONG ulTargetMemoryClock; /* In 10Khz unit */ -} MEMORY_TRAINING_PARAMETERS; +/****************************************************************************/ +// Structures used by ### +/****************************************************************************/ +typedef struct _MEMORY_TRAINING_PARAMETERS +{ + ULONG ulTargetMemoryClock; //In 10Khz unit +}MEMORY_TRAINING_PARAMETERS; #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS + /****************************LVDS and other encoder command table definitions **********************/ -/****************************************************************************/ -/* Structures used by LVDSEncoderControlTable (Before DCE30) */ -/* LVTMAEncoderControlTable (Before DCE30) */ -/* TMDSAEncoderControlTable (Before DCE30) */ -/****************************************************************************/ -typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS { - USHORT usPixelClock; /* in 10KHz; for bios convenient */ - UCHAR ucMisc; /* bit0=0: Enable single link */ - /* =1: Enable dual link */ - /* Bit1=0: 666RGB */ - /* =1: 888RGB */ - UCHAR ucAction; /* 0: turn off encoder */ - /* 1: setup and turn on encoder */ -} LVDS_ENCODER_CONTROL_PARAMETERS; -#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS +/****************************************************************************/ +// Structures used by LVDSEncoderControlTable (Before DCE30) +// LVTMAEncoderControlTable (Before DCE30) +// TMDSAEncoderControlTable (Before DCE30) +/****************************************************************************/ +typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucMisc; // bit0=0: Enable single link + // =1: Enable dual link + // Bit1=0: 666RGB + // =1: 888RGB + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder +}LVDS_ENCODER_CONTROL_PARAMETERS; +#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS + #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS -/* ucTableFormatRevision=1,ucTableContentRevision=2 */ -typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 { - USHORT usPixelClock; /* in 10KHz; for bios convenient */ - UCHAR ucMisc; /* see PANEL_ENCODER_MISC_xx defintions below */ - UCHAR ucAction; /* 0: turn off encoder */ - /* 1: setup and turn on encoder */ - UCHAR ucTruncate; /* bit0=0: Disable truncate */ - /* =1: Enable truncate */ - /* bit4=0: 666RGB */ - /* =1: 888RGB */ - UCHAR ucSpatial; /* bit0=0: Disable spatial dithering */ - /* =1: Enable spatial dithering */ - /* bit4=0: 666RGB */ - /* =1: 888RGB */ - UCHAR ucTemporal; /* bit0=0: Disable temporal dithering */ - /* =1: Enable temporal dithering */ - /* bit4=0: 666RGB */ - /* =1: 888RGB */ - /* bit5=0: Gray level 2 */ - /* =1: Gray level 4 */ - UCHAR ucFRC; /* bit4=0: 25FRC_SEL pattern E */ - /* =1: 25FRC_SEL pattern F */ - /* bit6:5=0: 50FRC_SEL pattern A */ - /* =1: 50FRC_SEL pattern B */ - /* =2: 50FRC_SEL pattern C */ - /* =3: 50FRC_SEL pattern D */ - /* bit7=0: 75FRC_SEL pattern E */ - /* =1: 75FRC_SEL pattern F */ -} LVDS_ENCODER_CONTROL_PARAMETERS_V2; -#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 +//ucTableFormatRevision=1,ucTableContentRevision=2 +typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder + UCHAR ucTruncate; // bit0=0: Disable truncate + // =1: Enable truncate + // bit4=0: 666RGB + // =1: 888RGB + UCHAR ucSpatial; // bit0=0: Disable spatial dithering + // =1: Enable spatial dithering + // bit4=0: 666RGB + // =1: 888RGB + UCHAR ucTemporal; // bit0=0: Disable temporal dithering + // =1: Enable temporal dithering + // bit4=0: 666RGB + // =1: 888RGB + // bit5=0: Gray level 2 + // =1: Gray level 4 + UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E + // =1: 25FRC_SEL pattern F + // bit6:5=0: 50FRC_SEL pattern A + // =1: 50FRC_SEL pattern B + // =2: 50FRC_SEL pattern C + // =3: 50FRC_SEL pattern D + // bit7=0: 75FRC_SEL pattern E + // =1: 75FRC_SEL pattern F +}LVDS_ENCODER_CONTROL_PARAMETERS_V2; +#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 + #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 - + #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 @@ -1185,38 +1536,42 @@ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 { #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 -/****************************************************************************/ -/* Structures used by ### */ -/****************************************************************************/ -typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS { - UCHAR ucEnable; /* Enable or Disable External TMDS encoder */ - UCHAR ucMisc; /* Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} */ - UCHAR ucPadding[2]; -} ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; - -typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION { - ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Caller doesn't need to init this portion */ -} ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; +/****************************************************************************/ +// Structures used by ### +/****************************************************************************/ +typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS +{ + UCHAR ucEnable; // Enable or Disable External TMDS encoder + UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} + UCHAR ucPadding[2]; +}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; + +typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION +{ + ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion +}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 -typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 { - ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Caller doesn't need to init this portion */ -} ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; +typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 +{ + ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion +}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; -typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION { - DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; -} EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; +typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION +{ + DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; +}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; -/****************************************************************************/ -/* Structures used by DVOEncoderControlTable */ -/****************************************************************************/ -/* ucTableFormatRevision=1,ucTableContentRevision=3 */ +/****************************************************************************/ +// Structures used by DVOEncoderControlTable +/****************************************************************************/ +//ucTableFormatRevision=1,ucTableContentRevision=3 -/* ucDVOConfig: */ +//ucDVOConfig: #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 @@ -1225,21 +1580,22 @@ typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION { #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 #define DVO_ENCODER_CONFIG_24BIT 0x08 -typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 { - USHORT usPixelClock; - UCHAR ucDVOConfig; - UCHAR ucAction; /* ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT */ - UCHAR ucReseved[4]; -} DVO_ENCODER_CONTROL_PARAMETERS_V3; +typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 +{ + USHORT usPixelClock; + UCHAR ucDVOConfig; + UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT + UCHAR ucReseved[4]; +}DVO_ENCODER_CONTROL_PARAMETERS_V3; #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 -/* ucTableFormatRevision=1 */ -/* ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for */ -/* bit1=0: non-coherent mode */ -/* =1: coherent mode */ +//ucTableFormatRevision=1 +//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for +// bit1=0: non-coherent mode +// =1: coherent mode -/* ========================================================================================== */ -/* Only change is here next time when changing encoder parameter definitions again! */ +//========================================================================================== +//Only change is here next time when changing encoder parameter definitions again! #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST @@ -1252,7 +1608,7 @@ typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 { #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION -/* ========================================================================================== */ +//========================================================================================== #define PANEL_ENCODER_MISC_DUAL 0x01 #define PANEL_ENCODER_MISC_COHERENT 0x02 #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 @@ -1281,159 +1637,159 @@ typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 { #define PANEL_ENCODER_75FRC_E 0x00 #define PANEL_ENCODER_75FRC_F 0x80 -/****************************************************************************/ -/* Structures used by SetVoltageTable */ -/****************************************************************************/ +/****************************************************************************/ +// Structures used by SetVoltageTable +/****************************************************************************/ #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 #define SET_VOLTAGE_INIT_MODE 5 -#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 /* Gets the Max. voltage for the soldered Asic */ +#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 -#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 +#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 -typedef struct _SET_VOLTAGE_PARAMETERS { - UCHAR ucVoltageType; /* To tell which voltage to set up, VDDC/MVDDC/MVDDQ */ - UCHAR ucVoltageMode; /* To set all, to set source A or source B or ... */ - UCHAR ucVoltageIndex; /* An index to tell which voltage level */ - UCHAR ucReserved; -} SET_VOLTAGE_PARAMETERS; - -typedef struct _SET_VOLTAGE_PARAMETERS_V2 { - UCHAR ucVoltageType; /* To tell which voltage to set up, VDDC/MVDDC/MVDDQ */ - UCHAR ucVoltageMode; /* Not used, maybe use for state machine for differen power mode */ - USHORT usVoltageLevel; /* real voltage level */ -} SET_VOLTAGE_PARAMETERS_V2; - -typedef struct _SET_VOLTAGE_PS_ALLOCATION { - SET_VOLTAGE_PARAMETERS sASICSetVoltage; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; -} SET_VOLTAGE_PS_ALLOCATION; - -/****************************************************************************/ -/* Structures used by TVEncoderControlTable */ -/****************************************************************************/ -typedef struct _TV_ENCODER_CONTROL_PARAMETERS { - USHORT usPixelClock; /* in 10KHz; for bios convenient */ - UCHAR ucTvStandard; /* See definition "ATOM_TV_NTSC ..." */ - UCHAR ucAction; /* 0: turn off encoder */ - /* 1: setup and turn on encoder */ -} TV_ENCODER_CONTROL_PARAMETERS; - -typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION { - TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Don't set this one */ -} TV_ENCODER_CONTROL_PS_ALLOCATION; - -/* ==============================Data Table Portion==================================== */ - -#ifdef UEFI_BUILD -#define UTEMP USHORT -#define USHORT void* -#endif - -/****************************************************************************/ -/* Structure used in Data.mtb */ -/****************************************************************************/ -typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES { - USHORT UtilityPipeLine; /* Offest for the utility to get parser info,Don't change this position! */ - USHORT MultimediaCapabilityInfo; /* Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios */ - USHORT MultimediaConfigInfo; /* Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios */ - USHORT StandardVESA_Timing; /* Only used by Bios */ - USHORT FirmwareInfo; /* Shared by various SW components,latest version 1.4 */ - USHORT DAC_Info; /* Will be obsolete from R600 */ - USHORT LVDS_Info; /* Shared by various SW components,latest version 1.1 */ - USHORT TMDS_Info; /* Will be obsolete from R600 */ - USHORT AnalogTV_Info; /* Shared by various SW components,latest version 1.1 */ - USHORT SupportedDevicesInfo; /* Will be obsolete from R600 */ - USHORT GPIO_I2C_Info; /* Shared by various SW components,latest version 1.2 will be used from R600 */ - USHORT VRAM_UsageByFirmware; /* Shared by various SW components,latest version 1.3 will be used from R600 */ - USHORT GPIO_Pin_LUT; /* Shared by various SW components,latest version 1.1 */ - USHORT VESA_ToInternalModeLUT; /* Only used by Bios */ - USHORT ComponentVideoInfo; /* Shared by various SW components,latest version 2.1 will be used from R600 */ - USHORT PowerPlayInfo; /* Shared by various SW components,latest version 2.1,new design from R600 */ - USHORT CompassionateData; /* Will be obsolete from R600 */ - USHORT SaveRestoreInfo; /* Only used by Bios */ - USHORT PPLL_SS_Info; /* Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info */ - USHORT OemInfo; /* Defined and used by external SW, should be obsolete soon */ - USHORT XTMDS_Info; /* Will be obsolete from R600 */ - USHORT MclkSS_Info; /* Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used */ - USHORT Object_Header; /* Shared by various SW components,latest version 1.1 */ - USHORT IndirectIOAccess; /* Only used by Bios,this table position can't change at all!! */ - USHORT MC_InitParameter; /* Only used by command table */ - USHORT ASIC_VDDC_Info; /* Will be obsolete from R600 */ - USHORT ASIC_InternalSS_Info; /* New tabel name from R600, used to be called "ASIC_MVDDC_Info" */ - USHORT TV_VideoMode; /* Only used by command table */ - USHORT VRAM_Info; /* Only used by command table, latest version 1.3 */ - USHORT MemoryTrainingInfo; /* Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 */ - USHORT IntegratedSystemInfo; /* Shared by various SW components */ - USHORT ASIC_ProfilingInfo; /* New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 */ - USHORT VoltageObjectInfo; /* Shared by various SW components, latest version 1.1 */ - USHORT PowerSourceInfo; /* Shared by various SW components, latest versoin 1.1 */ -} ATOM_MASTER_LIST_OF_DATA_TABLES; +typedef struct _SET_VOLTAGE_PARAMETERS +{ + UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ + UCHAR ucVoltageMode; // To set all, to set source A or source B or ... + UCHAR ucVoltageIndex; // An index to tell which voltage level + UCHAR ucReserved; +}SET_VOLTAGE_PARAMETERS; -#ifdef UEFI_BUILD -#define USHORT UTEMP -#endif +typedef struct _SET_VOLTAGE_PARAMETERS_V2 +{ + UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ + UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode + USHORT usVoltageLevel; // real voltage level +}SET_VOLTAGE_PARAMETERS_V2; -typedef struct _ATOM_MASTER_DATA_TABLE { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; -} ATOM_MASTER_DATA_TABLE; +typedef struct _SET_VOLTAGE_PS_ALLOCATION +{ + SET_VOLTAGE_PARAMETERS sASICSetVoltage; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; +}SET_VOLTAGE_PS_ALLOCATION; + +/****************************************************************************/ +// Structures used by TVEncoderControlTable +/****************************************************************************/ +typedef struct _TV_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder +}TV_ENCODER_CONTROL_PARAMETERS; -/****************************************************************************/ -/* Structure used in MultimediaCapabilityInfoTable */ -/****************************************************************************/ -typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulSignature; /* HW info table signature string "$ATI" */ - UCHAR ucI2C_Type; /* I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) */ - UCHAR ucTV_OutInfo; /* Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) */ - UCHAR ucVideoPortInfo; /* Provides the video port capabilities */ - UCHAR ucHostPortInfo; /* Provides host port configuration information */ -} ATOM_MULTIMEDIA_CAPABILITY_INFO; +typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION +{ + TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one +}TV_ENCODER_CONTROL_PS_ALLOCATION; -/****************************************************************************/ -/* Structure used in MultimediaConfigInfoTable */ -/****************************************************************************/ -typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulSignature; /* MM info table signature sting "$MMT" */ - UCHAR ucTunerInfo; /* Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) */ - UCHAR ucAudioChipInfo; /* List the audio chip type (3:0) product type (4) and OEM revision (7:5) */ - UCHAR ucProductID; /* Defines as OEM ID or ATI board ID dependent on product type setting */ - UCHAR ucMiscInfo1; /* Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) */ - UCHAR ucMiscInfo2; /* I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) */ - UCHAR ucMiscInfo3; /* Video Decoder Type (3:0) Video In Standard/Crystal (7:4) */ - UCHAR ucMiscInfo4; /* Video Decoder Host Config (2:0) reserved (7:3) */ - UCHAR ucVideoInput0Info; /* Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ - UCHAR ucVideoInput1Info; /* Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ - UCHAR ucVideoInput2Info; /* Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ - UCHAR ucVideoInput3Info; /* Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ - UCHAR ucVideoInput4Info; /* Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ -} ATOM_MULTIMEDIA_CONFIG_INFO; +//==============================Data Table Portion==================================== -/****************************************************************************/ -/* Structures used in FirmwareInfoTable */ -/****************************************************************************/ - -/* usBIOSCapability Defintion: */ -/* Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; */ -/* Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; */ -/* Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; */ -/* Others: Reserved */ +/****************************************************************************/ +// Structure used in Data.mtb +/****************************************************************************/ +typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES +{ + USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! + USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios + USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios + USHORT StandardVESA_Timing; // Only used by Bios + USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 + USHORT DAC_Info; // Will be obsolete from R600 + USHORT LVDS_Info; // Shared by various SW components,latest version 1.1 + USHORT TMDS_Info; // Will be obsolete from R600 + USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 + USHORT SupportedDevicesInfo; // Will be obsolete from R600 + USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 + USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 + USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 + USHORT VESA_ToInternalModeLUT; // Only used by Bios + USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 + USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 + USHORT CompassionateData; // Will be obsolete from R600 + USHORT SaveRestoreInfo; // Only used by Bios + USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info + USHORT OemInfo; // Defined and used by external SW, should be obsolete soon + USHORT XTMDS_Info; // Will be obsolete from R600 + USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used + USHORT Object_Header; // Shared by various SW components,latest version 1.1 + USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! + USHORT MC_InitParameter; // Only used by command table + USHORT ASIC_VDDC_Info; // Will be obsolete from R600 + USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" + USHORT TV_VideoMode; // Only used by command table + USHORT VRAM_Info; // Only used by command table, latest version 1.3 + USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 + USHORT IntegratedSystemInfo; // Shared by various SW components + USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 + USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 + USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 +}ATOM_MASTER_LIST_OF_DATA_TABLES; + +typedef struct _ATOM_MASTER_DATA_TABLE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; +}ATOM_MASTER_DATA_TABLE; + +/****************************************************************************/ +// Structure used in MultimediaCapabilityInfoTable +/****************************************************************************/ +typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulSignature; // HW info table signature string "$ATI" + UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) + UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) + UCHAR ucVideoPortInfo; // Provides the video port capabilities + UCHAR ucHostPortInfo; // Provides host port configuration information +}ATOM_MULTIMEDIA_CAPABILITY_INFO; + +/****************************************************************************/ +// Structure used in MultimediaConfigInfoTable +/****************************************************************************/ +typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulSignature; // MM info table signature sting "$MMT" + UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) + UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) + UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting + UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) + UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) + UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) + UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) + UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) + UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) + UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) + UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) + UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) +}ATOM_MULTIMEDIA_CONFIG_INFO; + +/****************************************************************************/ +// Structures used in FirmwareInfoTable +/****************************************************************************/ + +// usBIOSCapability Defintion: +// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; +// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; +// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; +// Others: Reserved #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 -#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 -#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 +#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. +#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 @@ -1441,242 +1797,292 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO { #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 +#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip +#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip #ifndef _H2INC -/* Please don't add or expand this bitfield structure below, this one will retire soon.! */ -typedef struct _ATOM_FIRMWARE_CAPABILITY { +//Please don't add or expand this bitfield structure below, this one will retire soon.! +typedef struct _ATOM_FIRMWARE_CAPABILITY +{ #if ATOM_BIG_ENDIAN - USHORT Reserved:3; - USHORT HyperMemory_Size:4; - USHORT HyperMemory_Support:1; - USHORT PPMode_Assigned:1; - USHORT WMI_SUPPORT:1; - USHORT GPUControlsBL:1; - USHORT EngineClockSS_Support:1; - USHORT MemoryClockSS_Support:1; - USHORT ExtendedDesktopSupport:1; - USHORT DualCRTC_Support:1; - USHORT FirmwarePosted:1; + USHORT Reserved:3; + USHORT HyperMemory_Size:4; + USHORT HyperMemory_Support:1; + USHORT PPMode_Assigned:1; + USHORT WMI_SUPPORT:1; + USHORT GPUControlsBL:1; + USHORT EngineClockSS_Support:1; + USHORT MemoryClockSS_Support:1; + USHORT ExtendedDesktopSupport:1; + USHORT DualCRTC_Support:1; + USHORT FirmwarePosted:1; #else - USHORT FirmwarePosted:1; - USHORT DualCRTC_Support:1; - USHORT ExtendedDesktopSupport:1; - USHORT MemoryClockSS_Support:1; - USHORT EngineClockSS_Support:1; - USHORT GPUControlsBL:1; - USHORT WMI_SUPPORT:1; - USHORT PPMode_Assigned:1; - USHORT HyperMemory_Support:1; - USHORT HyperMemory_Size:4; - USHORT Reserved:3; + USHORT FirmwarePosted:1; + USHORT DualCRTC_Support:1; + USHORT ExtendedDesktopSupport:1; + USHORT MemoryClockSS_Support:1; + USHORT EngineClockSS_Support:1; + USHORT GPUControlsBL:1; + USHORT WMI_SUPPORT:1; + USHORT PPMode_Assigned:1; + USHORT HyperMemory_Support:1; + USHORT HyperMemory_Size:4; + USHORT Reserved:3; #endif -} ATOM_FIRMWARE_CAPABILITY; +}ATOM_FIRMWARE_CAPABILITY; -typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS { - ATOM_FIRMWARE_CAPABILITY sbfAccess; - USHORT susAccess; -} ATOM_FIRMWARE_CAPABILITY_ACCESS; +typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS +{ + ATOM_FIRMWARE_CAPABILITY sbfAccess; + USHORT susAccess; +}ATOM_FIRMWARE_CAPABILITY_ACCESS; #else -typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS { - USHORT susAccess; -} ATOM_FIRMWARE_CAPABILITY_ACCESS; +typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS +{ + USHORT susAccess; +}ATOM_FIRMWARE_CAPABILITY_ACCESS; #endif -typedef struct _ATOM_FIRMWARE_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulFirmwareRevision; - ULONG ulDefaultEngineClock; /* In 10Khz unit */ - ULONG ulDefaultMemoryClock; /* In 10Khz unit */ - ULONG ulDriverTargetEngineClock; /* In 10Khz unit */ - ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */ - ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */ - ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */ - ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */ - ULONG ulASICMaxEngineClock; /* In 10Khz unit */ - ULONG ulASICMaxMemoryClock; /* In 10Khz unit */ - UCHAR ucASICMaxTemperature; - UCHAR ucPadding[3]; /* Don't use them */ - ULONG aulReservedForBIOS[3]; /* Don't use them */ - USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */ - USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */ - USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */ - USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */ - USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */ - USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */ - USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */ - USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */ - USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */ - USHORT usMinPixelClockPLL_Output; /* In 10Khz unit, the definitions above can't change!!! */ - ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; /* In 10Khz unit */ - USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */ - UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */ - UCHAR ucDesign_ID; /* Indicate what is the board design */ - UCHAR ucMemoryModule_ID; /* Indicate what is the board design */ -} ATOM_FIRMWARE_INFO; - -typedef struct _ATOM_FIRMWARE_INFO_V1_2 { - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulFirmwareRevision; - ULONG ulDefaultEngineClock; /* In 10Khz unit */ - ULONG ulDefaultMemoryClock; /* In 10Khz unit */ - ULONG ulDriverTargetEngineClock; /* In 10Khz unit */ - ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */ - ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */ - ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */ - ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */ - ULONG ulASICMaxEngineClock; /* In 10Khz unit */ - ULONG ulASICMaxMemoryClock; /* In 10Khz unit */ - UCHAR ucASICMaxTemperature; - UCHAR ucMinAllowedBL_Level; - UCHAR ucPadding[2]; /* Don't use them */ - ULONG aulReservedForBIOS[2]; /* Don't use them */ - ULONG ulMinPixelClockPLL_Output; /* In 10Khz unit */ - USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */ - USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */ - USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */ - USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */ - USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */ - USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */ - USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */ - USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */ - USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */ - USHORT usMinPixelClockPLL_Output; /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */ - ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; /* In 10Khz unit */ - USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */ - UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */ - UCHAR ucDesign_ID; /* Indicate what is the board design */ - UCHAR ucMemoryModule_ID; /* Indicate what is the board design */ -} ATOM_FIRMWARE_INFO_V1_2; - -typedef struct _ATOM_FIRMWARE_INFO_V1_3 { - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulFirmwareRevision; - ULONG ulDefaultEngineClock; /* In 10Khz unit */ - ULONG ulDefaultMemoryClock; /* In 10Khz unit */ - ULONG ulDriverTargetEngineClock; /* In 10Khz unit */ - ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */ - ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */ - ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */ - ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */ - ULONG ulASICMaxEngineClock; /* In 10Khz unit */ - ULONG ulASICMaxMemoryClock; /* In 10Khz unit */ - UCHAR ucASICMaxTemperature; - UCHAR ucMinAllowedBL_Level; - UCHAR ucPadding[2]; /* Don't use them */ - ULONG aulReservedForBIOS; /* Don't use them */ - ULONG ul3DAccelerationEngineClock; /* In 10Khz unit */ - ULONG ulMinPixelClockPLL_Output; /* In 10Khz unit */ - USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */ - USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */ - USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */ - USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */ - USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */ - USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */ - USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */ - USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */ - USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */ - USHORT usMinPixelClockPLL_Output; /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */ - ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; /* In 10Khz unit */ - USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */ - UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */ - UCHAR ucDesign_ID; /* Indicate what is the board design */ - UCHAR ucMemoryModule_ID; /* Indicate what is the board design */ -} ATOM_FIRMWARE_INFO_V1_3; - -typedef struct _ATOM_FIRMWARE_INFO_V1_4 { - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulFirmwareRevision; - ULONG ulDefaultEngineClock; /* In 10Khz unit */ - ULONG ulDefaultMemoryClock; /* In 10Khz unit */ - ULONG ulDriverTargetEngineClock; /* In 10Khz unit */ - ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */ - ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */ - ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */ - ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */ - ULONG ulASICMaxEngineClock; /* In 10Khz unit */ - ULONG ulASICMaxMemoryClock; /* In 10Khz unit */ - UCHAR ucASICMaxTemperature; - UCHAR ucMinAllowedBL_Level; - USHORT usBootUpVDDCVoltage; /* In MV unit */ - USHORT usLcdMinPixelClockPLL_Output; /* In MHz unit */ - USHORT usLcdMaxPixelClockPLL_Output; /* In MHz unit */ - ULONG ul3DAccelerationEngineClock; /* In 10Khz unit */ - ULONG ulMinPixelClockPLL_Output; /* In 10Khz unit */ - USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */ - USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */ - USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */ - USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */ - USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */ - USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */ - USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */ - USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */ - USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */ - USHORT usMinPixelClockPLL_Output; /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */ - ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; /* In 10Khz unit */ - USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */ - UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */ - UCHAR ucDesign_ID; /* Indicate what is the board design */ - UCHAR ucMemoryModule_ID; /* Indicate what is the board design */ -} ATOM_FIRMWARE_INFO_V1_4; - -#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V1_4 - -/****************************************************************************/ -/* Structures used in IntegratedSystemInfoTable */ -/****************************************************************************/ +typedef struct _ATOM_FIRMWARE_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulDriverTargetEngineClock; //In 10Khz unit + ULONG ulDriverTargetMemoryClock; //In 10Khz unit + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulASICMaxEngineClock; //In 10Khz unit + ULONG ulASICMaxMemoryClock; //In 10Khz unit + UCHAR ucASICMaxTemperature; + UCHAR ucPadding[3]; //Don't use them + ULONG aulReservedForBIOS[3]; //Don't use them + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit + UCHAR ucDesign_ID; //Indicate what is the board design + UCHAR ucMemoryModule_ID; //Indicate what is the board design +}ATOM_FIRMWARE_INFO; + +typedef struct _ATOM_FIRMWARE_INFO_V1_2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulDriverTargetEngineClock; //In 10Khz unit + ULONG ulDriverTargetMemoryClock; //In 10Khz unit + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulASICMaxEngineClock; //In 10Khz unit + ULONG ulASICMaxMemoryClock; //In 10Khz unit + UCHAR ucASICMaxTemperature; + UCHAR ucMinAllowedBL_Level; + UCHAR ucPadding[2]; //Don't use them + ULONG aulReservedForBIOS[2]; //Don't use them + ULONG ulMinPixelClockPLL_Output; //In 10Khz unit + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit + UCHAR ucDesign_ID; //Indicate what is the board design + UCHAR ucMemoryModule_ID; //Indicate what is the board design +}ATOM_FIRMWARE_INFO_V1_2; + +typedef struct _ATOM_FIRMWARE_INFO_V1_3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulDriverTargetEngineClock; //In 10Khz unit + ULONG ulDriverTargetMemoryClock; //In 10Khz unit + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulASICMaxEngineClock; //In 10Khz unit + ULONG ulASICMaxMemoryClock; //In 10Khz unit + UCHAR ucASICMaxTemperature; + UCHAR ucMinAllowedBL_Level; + UCHAR ucPadding[2]; //Don't use them + ULONG aulReservedForBIOS; //Don't use them + ULONG ul3DAccelerationEngineClock;//In 10Khz unit + ULONG ulMinPixelClockPLL_Output; //In 10Khz unit + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit + UCHAR ucDesign_ID; //Indicate what is the board design + UCHAR ucMemoryModule_ID; //Indicate what is the board design +}ATOM_FIRMWARE_INFO_V1_3; + +typedef struct _ATOM_FIRMWARE_INFO_V1_4 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulDriverTargetEngineClock; //In 10Khz unit + ULONG ulDriverTargetMemoryClock; //In 10Khz unit + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulASICMaxEngineClock; //In 10Khz unit + ULONG ulASICMaxMemoryClock; //In 10Khz unit + UCHAR ucASICMaxTemperature; + UCHAR ucMinAllowedBL_Level; + USHORT usBootUpVDDCVoltage; //In MV unit + USHORT usLcdMinPixelClockPLL_Output; // In MHz unit + USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit + ULONG ul3DAccelerationEngineClock;//In 10Khz unit + ULONG ulMinPixelClockPLL_Output; //In 10Khz unit + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit + UCHAR ucDesign_ID; //Indicate what is the board design + UCHAR ucMemoryModule_ID; //Indicate what is the board design +}ATOM_FIRMWARE_INFO_V1_4; + +//the structure below to be used from Cypress +typedef struct _ATOM_FIRMWARE_INFO_V2_1 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulReserved1; + ULONG ulReserved2; + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock + ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit + UCHAR ucReserved1; //Was ucASICMaxTemperature; + UCHAR ucMinAllowedBL_Level; + USHORT usBootUpVDDCVoltage; //In MV unit + USHORT usLcdMinPixelClockPLL_Output; // In MHz unit + USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit + ULONG ulReserved4; //Was ulAsicMaximumVoltage + ULONG ulMinPixelClockPLL_Output; //In 10Khz unit + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usCoreReferenceClock; //In 10Khz unit + USHORT usMemoryReferenceClock; //In 10Khz unit + USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock + UCHAR ucMemoryModule_ID; //Indicate what is the board design + UCHAR ucReserved4[3]; +}ATOM_FIRMWARE_INFO_V2_1; + + +#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_1 + +/****************************************************************************/ +// Structures used in IntegratedSystemInfoTable +/****************************************************************************/ #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 #define IGP_CAP_FLAG_AC_CARD 0x4 #define IGP_CAP_FLAG_SDVO_CARD 0x8 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 -typedef struct _ATOM_INTEGRATED_SYSTEM_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulBootUpEngineClock; /* in 10kHz unit */ - ULONG ulBootUpMemoryClock; /* in 10kHz unit */ - ULONG ulMaxSystemMemoryClock; /* in 10kHz unit */ - ULONG ulMinSystemMemoryClock; /* in 10kHz unit */ - UCHAR ucNumberOfCyclesInPeriodHi; - UCHAR ucLCDTimingSel; /* =0:not valid.!=0 sel this timing descriptor from LCD EDID. */ - USHORT usReserved1; - USHORT usInterNBVoltageLow; /* An intermidiate PMW value to set the voltage */ - USHORT usInterNBVoltageHigh; /* Another intermidiate PMW value to set the voltage */ - ULONG ulReserved[2]; - - USHORT usFSBClock; /* In MHz unit */ - USHORT usCapabilityFlag; /* Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable */ - /* Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card */ - /* Bit[4]==1: P/2 mode, ==0: P/1 mode */ - USHORT usPCIENBCfgReg7; /* bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal */ - USHORT usK8MemoryClock; /* in MHz unit */ - USHORT usK8SyncStartDelay; /* in 0.01 us unit */ - USHORT usK8DataReturnTime; /* in 0.01 us unit */ - UCHAR ucMaxNBVoltage; - UCHAR ucMinNBVoltage; - UCHAR ucMemoryType; /* [7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved */ - UCHAR ucNumberOfCyclesInPeriod; /* CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod */ - UCHAR ucStartingPWM_HighTime; /* CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime */ - UCHAR ucHTLinkWidth; /* 16 bit vs. 8 bit */ - UCHAR ucMaxNBVoltageHigh; - UCHAR ucMinNBVoltageHigh; -} ATOM_INTEGRATED_SYSTEM_INFO; +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; //in 10kHz unit + ULONG ulBootUpMemoryClock; //in 10kHz unit + ULONG ulMaxSystemMemoryClock; //in 10kHz unit + ULONG ulMinSystemMemoryClock; //in 10kHz unit + UCHAR ucNumberOfCyclesInPeriodHi; + UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. + USHORT usReserved1; + USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage + USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage + ULONG ulReserved[2]; + + USHORT usFSBClock; //In MHz unit + USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable + //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card + //Bit[4]==1: P/2 mode, ==0: P/1 mode + USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal + USHORT usK8MemoryClock; //in MHz unit + USHORT usK8SyncStartDelay; //in 0.01 us unit + USHORT usK8DataReturnTime; //in 0.01 us unit + UCHAR ucMaxNBVoltage; + UCHAR ucMinNBVoltage; + UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved + UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod + UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime + UCHAR ucHTLinkWidth; //16 bit vs. 8 bit + UCHAR ucMaxNBVoltageHigh; + UCHAR ucMinNBVoltageHigh; +}ATOM_INTEGRATED_SYSTEM_INFO; /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO -ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock +ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 For AMD IGP,for now this can be 0 -ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 +ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 For AMD IGP,for now this can be 0 -usFSBClock: For Intel IGP,it's FSB Freq +usFSBClock: For Intel IGP,it's FSB Freq For AMD IGP,it's HT Link Speed usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 @@ -1687,98 +2093,113 @@ VC:Voltage Control ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. -ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. -ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 +ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. +ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. + usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. */ + /* The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; -Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. +Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. SW components can access the IGP system infor structure in the same way as before */ -typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 { - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulBootUpEngineClock; /* in 10kHz unit */ - ULONG ulReserved1[2]; /* must be 0x0 for the reserved */ - ULONG ulBootUpUMAClock; /* in 10kHz unit */ - ULONG ulBootUpSidePortClock; /* in 10kHz unit */ - ULONG ulMinSidePortClock; /* in 10kHz unit */ - ULONG ulReserved2[6]; /* must be 0x0 for the reserved */ - ULONG ulSystemConfig; /* see explanation below */ - ULONG ulBootUpReqDisplayVector; - ULONG ulOtherDisplayMisc; - ULONG ulDDISlot1Config; - ULONG ulDDISlot2Config; - UCHAR ucMemoryType; /* [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved */ - UCHAR ucUMAChannelNumber; - UCHAR ucDockingPinBit; - UCHAR ucDockingPinPolarity; - ULONG ulDockingPinCFGInfo; - ULONG ulCPUCapInfo; - USHORT usNumberOfCyclesInPeriod; - USHORT usMaxNBVoltage; - USHORT usMinNBVoltage; - USHORT usBootUpNBVoltage; - ULONG ulHTLinkFreq; /* in 10Khz */ - USHORT usMinHTLinkWidth; - USHORT usMaxHTLinkWidth; - USHORT usUMASyncStartDelay; - USHORT usUMADataReturnTime; - USHORT usLinkStatusZeroTime; - USHORT usReserved; - ULONG ulHighVoltageHTLinkFreq; /* in 10Khz */ - ULONG ulLowVoltageHTLinkFreq; /* in 10Khz */ - USHORT usMaxUpStreamHTLinkWidth; - USHORT usMaxDownStreamHTLinkWidth; - USHORT usMinUpStreamHTLinkWidth; - USHORT usMinDownStreamHTLinkWidth; - ULONG ulReserved3[97]; /* must be 0x0 */ -} ATOM_INTEGRATED_SYSTEM_INFO_V2; + +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; //in 10kHz unit + ULONG ulReserved1[2]; //must be 0x0 for the reserved + ULONG ulBootUpUMAClock; //in 10kHz unit + ULONG ulBootUpSidePortClock; //in 10kHz unit + ULONG ulMinSidePortClock; //in 10kHz unit + ULONG ulReserved2[6]; //must be 0x0 for the reserved + ULONG ulSystemConfig; //see explanation below + ULONG ulBootUpReqDisplayVector; + ULONG ulOtherDisplayMisc; + ULONG ulDDISlot1Config; + ULONG ulDDISlot2Config; + UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved + UCHAR ucUMAChannelNumber; + UCHAR ucDockingPinBit; + UCHAR ucDockingPinPolarity; + ULONG ulDockingPinCFGInfo; + ULONG ulCPUCapInfo; + USHORT usNumberOfCyclesInPeriod; + USHORT usMaxNBVoltage; + USHORT usMinNBVoltage; + USHORT usBootUpNBVoltage; + ULONG ulHTLinkFreq; //in 10Khz + USHORT usMinHTLinkWidth; + USHORT usMaxHTLinkWidth; + USHORT usUMASyncStartDelay; + USHORT usUMADataReturnTime; + USHORT usLinkStatusZeroTime; + USHORT usDACEfuse; //for storing badgap value (for RS880 only) + ULONG ulHighVoltageHTLinkFreq; // in 10Khz + ULONG ulLowVoltageHTLinkFreq; // in 10Khz + USHORT usMaxUpStreamHTLinkWidth; + USHORT usMaxDownStreamHTLinkWidth; + USHORT usMinUpStreamHTLinkWidth; + USHORT usMinDownStreamHTLinkWidth; + USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. + USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. + ULONG ulReserved3[96]; //must be 0x0 +}ATOM_INTEGRATED_SYSTEM_INFO_V2; /* ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock -ulSystemConfig: -Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; +ulSystemConfig: +Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state =0: system boots up at driver control state. Power state depends on PowerPlay table. Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. Bit[3]=1: Only one power state(Performance) will be supported. =0: Multiple power states supported from PowerPlay table. -Bit[4]=1: CLMC is supported and enabled on current system. - =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. -Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. +Bit[4]=1: CLMC is supported and enabled on current system. + =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. +Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. =0: Voltage settings is determined by powerplay table. Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. +Bit[8]=1: CDLF is supported and enabled on current system. + =0: CDLF is not supported or enabled on current system. +Bit[9]=1: DLL Shut Down feature is enabled on current system. + =0: DLL Shut Down feature is not enabled or supported on current system. ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; - [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; + [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition; ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) - [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) - [15:8] - Lane configuration attribute; + [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) + When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. + in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: + one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. + + [15:8] - Lane configuration attribute; [23:16]- Connector type, possible value: CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D CONNECTOR_OBJECT_ID_HDMI_TYPE_A CONNECTOR_OBJECT_ID_DISPLAYPORT + CONNECTOR_OBJECT_ID_eDP [31:24]- Reserved ulDDISlot2Config: Same as Slot1. @@ -1787,29 +2208,31 @@ For IGP, Hypermemory is the only memory type showed in CCC. ucUMAChannelNumber: how many channels for the UMA; -ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin +ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin ucDockingPinBit: which bit in this register to read the pin status; ucDockingPinPolarity:Polarity of the pin when docked; ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. -usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. + +usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE + usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. ulHTLinkFreq: Bootup HT link Frequency in 10Khz. -usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. - If CDLW enabled, both upstream and downstream width should be the same during bootup. -usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. +usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. If CDLW enabled, both upstream and downstream width should be the same during bootup. +usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. + If CDLW enabled, both upstream and downstream width should be the same during bootup. -usUMASyncStartDelay: Memory access latency, required for watermark calculation +usUMASyncStartDelay: Memory access latency, required for watermark calculation usUMADataReturnTime: Memory access latency, required for watermark calculation -usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us +usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us for Griffin or Greyhound. SBIOS needs to convert to actual time by: if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) @@ -1817,7 +2240,7 @@ for Griffin or Greyhound. SBIOS needs to convert to actual time by: if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. - This must be less than or equal to ulHTLinkFreq(bootup frequency). + This must be less than or equal to ulHTLinkFreq(bootup frequency). ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. This must be less than or equal to ulHighVoltageHTLinkFreq. @@ -1827,14 +2250,17 @@ usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to rep usMinDownStreamHTLinkWidth: same as above. */ + #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 -#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 +#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 +#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 +#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF @@ -1851,6 +2277,41 @@ usMinDownStreamHTLinkWidth: same as above. #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 +// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; //in 10kHz unit + ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. + ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge + ULONG ulBootUpUMAClock; //in 10kHz unit + ULONG ulReserved1[8]; //must be 0x0 for the reserved + ULONG ulBootUpReqDisplayVector; + ULONG ulOtherDisplayMisc; + ULONG ulReserved2[4]; //must be 0x0 for the reserved + ULONG ulSystemConfig; //TBD + ULONG ulCPUCapInfo; //TBD + USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; + USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; + USHORT usBootUpNBVoltage; //boot up NB voltage + UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD + UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD + ULONG ulReserved3[4]; //must be 0x0 for the reserved + ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition + ULONG ulDDISlot2Config; + ULONG ulDDISlot3Config; + ULONG ulDDISlot4Config; + ULONG ulReserved4[4]; //must be 0x0 for the reserved + UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved + UCHAR ucUMAChannelNumber; + USHORT usReserved; + ULONG ulReserved5[4]; //must be 0x0 for the reserved + ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default + ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback + ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications + ULONG ulReserved6[61]; //must be 0x0 +}ATOM_INTEGRATED_SYSTEM_INFO_V5; + #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 @@ -1866,8 +2327,8 @@ usMinDownStreamHTLinkWidth: same as above. #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D -/* define ASIC internal encoder id ( bit vector ) */ -#define ASIC_INT_DAC1_ENCODER_ID 0x00 +// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable +#define ASIC_INT_DAC1_ENCODER_ID 0x00 #define ASIC_INT_TV_ENCODER_ID 0x02 #define ASIC_INT_DIG1_ENCODER_ID 0x03 #define ASIC_INT_DAC2_ENCODER_ID 0x04 @@ -1875,10 +2336,24 @@ usMinDownStreamHTLinkWidth: same as above. #define ASIC_INT_DVO_ENCODER_ID 0x07 #define ASIC_INT_DIG2_ENCODER_ID 0x09 #define ASIC_EXT_DIG_ENCODER_ID 0x05 +#define ASIC_EXT_DIG2_ENCODER_ID 0x08 +#define ASIC_INT_DIG3_ENCODER_ID 0x0a +#define ASIC_INT_DIG4_ENCODER_ID 0x0b +#define ASIC_INT_DIG5_ENCODER_ID 0x0c +#define ASIC_INT_DIG6_ENCODER_ID 0x0d -/* define Encoder attribute */ +//define Encoder attribute #define ATOM_ANALOG_ENCODER 0 -#define ATOM_DIGITAL_ENCODER 1 +#define ATOM_DIGITAL_ENCODER 1 +#define ATOM_DP_ENCODER 2 + +#define ATOM_ENCODER_ENUM_MASK 0x70 +#define ATOM_ENCODER_ENUM_ID1 0x00 +#define ATOM_ENCODER_ENUM_ID2 0x10 +#define ATOM_ENCODER_ENUM_ID3 0x20 +#define ATOM_ENCODER_ENUM_ID4 0x30 +#define ATOM_ENCODER_ENUM_ID5 0x40 +#define ATOM_ENCODER_ENUM_ID6 0x50 #define ATOM_DEVICE_CRT1_INDEX 0x00000000 #define ATOM_DEVICE_LCD1_INDEX 0x00000001 @@ -1886,45 +2361,40 @@ usMinDownStreamHTLinkWidth: same as above. #define ATOM_DEVICE_DFP1_INDEX 0x00000003 #define ATOM_DEVICE_CRT2_INDEX 0x00000004 #define ATOM_DEVICE_LCD2_INDEX 0x00000005 -#define ATOM_DEVICE_TV2_INDEX 0x00000006 +#define ATOM_DEVICE_DFP6_INDEX 0x00000006 #define ATOM_DEVICE_DFP2_INDEX 0x00000007 #define ATOM_DEVICE_CV_INDEX 0x00000008 -#define ATOM_DEVICE_DFP3_INDEX 0x00000009 -#define ATOM_DEVICE_DFP4_INDEX 0x0000000A -#define ATOM_DEVICE_DFP5_INDEX 0x0000000B +#define ATOM_DEVICE_DFP3_INDEX 0x00000009 +#define ATOM_DEVICE_DFP4_INDEX 0x0000000A +#define ATOM_DEVICE_DFP5_INDEX 0x0000000B + #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO -#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1) +#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) -#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX) -#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX) -#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX) -#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX) -#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX) -#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX) -#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) -#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX) -#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX) -#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX) -#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) -#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX) - -#define ATOM_DEVICE_CRT_SUPPORT \ - (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) -#define ATOM_DEVICE_DFP_SUPPORT \ - (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | \ - ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | \ - ATOM_DEVICE_DFP5_SUPPORT) -#define ATOM_DEVICE_TV_SUPPORT \ - (ATOM_DEVICE_TV1_SUPPORT | ATOM_DEVICE_TV2_SUPPORT) -#define ATOM_DEVICE_LCD_SUPPORT \ - (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) +#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) +#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) +#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) +#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) +#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) +#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) +#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) +#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) +#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) +#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) +#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) +#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) + +#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) +#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) +#define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT) +#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 @@ -1942,6 +2412,7 @@ usMinDownStreamHTLinkWidth: same as above. #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F + #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 @@ -1958,139 +2429,150 @@ usMinDownStreamHTLinkWidth: same as above. #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 -#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 /* For IGP RS600 */ -#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 /* For IGP RS690 */ +#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 +#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 -/* usDeviceSupport: */ -/* Bits0 = 0 - no CRT1 support= 1- CRT1 is supported */ -/* Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported */ -/* Bit 2 = 0 - no TV1 support= 1- TV1 is supported */ -/* Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported */ -/* Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported */ -/* Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported */ -/* Bit 6 = 0 - no TV2 support= 1- TV2 is supported */ -/* Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported */ -/* Bit 8 = 0 - no CV support= 1- CV is supported */ -/* Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported */ -/* Byte1 (Supported Device Info) */ -/* Bit 0 = = 0 - no CV support= 1- CV is supported */ -/* */ -/* */ - -/* ucI2C_ConfigID */ -/* [7:0] - I2C LINE Associate ID */ -/* = 0 - no I2C */ -/* [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) */ -/* = 0, [6:0]=SW assisted I2C ID */ -/* [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use */ -/* = 2, HW engine for Multimedia use */ -/* = 3-7 Reserved for future I2C engines */ -/* [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C */ - -typedef struct _ATOM_I2C_ID_CONFIG { -#if ATOM_BIG_ENDIAN - UCHAR bfHW_Capable:1; - UCHAR bfHW_EngineID:3; - UCHAR bfI2C_LineMux:4; -#else - UCHAR bfI2C_LineMux:4; - UCHAR bfHW_EngineID:3; - UCHAR bfHW_Capable:1; -#endif -} ATOM_I2C_ID_CONFIG; - -typedef union _ATOM_I2C_ID_CONFIG_ACCESS { - ATOM_I2C_ID_CONFIG sbfAccess; - UCHAR ucAccess; -} ATOM_I2C_ID_CONFIG_ACCESS; +// usDeviceSupport: +// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported +// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported +// Bit 2 = 0 - no TV1 support= 1- TV1 is supported +// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported +// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported +// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported +// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported +// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported +// Bit 8 = 0 - no CV support= 1- CV is supported +// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported +// Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported +// Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported +// +// /****************************************************************************/ -/* Structure used in GPIO_I2C_InfoTable */ +/* Structure used in MclkSS_InfoTable */ /****************************************************************************/ -typedef struct _ATOM_GPIO_I2C_ASSIGMENT { - USHORT usClkMaskRegisterIndex; - USHORT usClkEnRegisterIndex; - USHORT usClkY_RegisterIndex; - USHORT usClkA_RegisterIndex; - USHORT usDataMaskRegisterIndex; - USHORT usDataEnRegisterIndex; - USHORT usDataY_RegisterIndex; - USHORT usDataA_RegisterIndex; - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; - UCHAR ucClkMaskShift; - UCHAR ucClkEnShift; - UCHAR ucClkY_Shift; - UCHAR ucClkA_Shift; - UCHAR ucDataMaskShift; - UCHAR ucDataEnShift; - UCHAR ucDataY_Shift; - UCHAR ucDataA_Shift; - UCHAR ucReserved1; - UCHAR ucReserved2; -} ATOM_GPIO_I2C_ASSIGMENT; - -typedef struct _ATOM_GPIO_I2C_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; -} ATOM_GPIO_I2C_INFO; +// ucI2C_ConfigID +// [7:0] - I2C LINE Associate ID +// = 0 - no I2C +// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) +// = 0, [6:0]=SW assisted I2C ID +// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use +// = 2, HW engine for Multimedia use +// = 3-7 Reserved for future I2C engines +// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C + +typedef struct _ATOM_I2C_ID_CONFIG +{ +#if ATOM_BIG_ENDIAN + UCHAR bfHW_Capable:1; + UCHAR bfHW_EngineID:3; + UCHAR bfI2C_LineMux:4; +#else + UCHAR bfI2C_LineMux:4; + UCHAR bfHW_EngineID:3; + UCHAR bfHW_Capable:1; +#endif +}ATOM_I2C_ID_CONFIG; -/****************************************************************************/ -/* Common Structure used in other structures */ -/****************************************************************************/ +typedef union _ATOM_I2C_ID_CONFIG_ACCESS +{ + ATOM_I2C_ID_CONFIG sbfAccess; + UCHAR ucAccess; +}ATOM_I2C_ID_CONFIG_ACCESS; + + +/****************************************************************************/ +// Structure used in GPIO_I2C_InfoTable +/****************************************************************************/ +typedef struct _ATOM_GPIO_I2C_ASSIGMENT +{ + USHORT usClkMaskRegisterIndex; + USHORT usClkEnRegisterIndex; + USHORT usClkY_RegisterIndex; + USHORT usClkA_RegisterIndex; + USHORT usDataMaskRegisterIndex; + USHORT usDataEnRegisterIndex; + USHORT usDataY_RegisterIndex; + USHORT usDataA_RegisterIndex; + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; + UCHAR ucClkMaskShift; + UCHAR ucClkEnShift; + UCHAR ucClkY_Shift; + UCHAR ucClkA_Shift; + UCHAR ucDataMaskShift; + UCHAR ucDataEnShift; + UCHAR ucDataY_Shift; + UCHAR ucDataA_Shift; + UCHAR ucReserved1; + UCHAR ucReserved2; +}ATOM_GPIO_I2C_ASSIGMENT; + +typedef struct _ATOM_GPIO_I2C_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; +}ATOM_GPIO_I2C_INFO; + +/****************************************************************************/ +// Common Structure used in other structures +/****************************************************************************/ #ifndef _H2INC - -/* Please don't add or expand this bitfield structure below, this one will retire soon.! */ -typedef struct _ATOM_MODE_MISC_INFO { + +//Please don't add or expand this bitfield structure below, this one will retire soon.! +typedef struct _ATOM_MODE_MISC_INFO +{ #if ATOM_BIG_ENDIAN - USHORT Reserved:6; - USHORT RGB888:1; - USHORT DoubleClock:1; - USHORT Interlace:1; - USHORT CompositeSync:1; - USHORT V_ReplicationBy2:1; - USHORT H_ReplicationBy2:1; - USHORT VerticalCutOff:1; - USHORT VSyncPolarity:1; /* 0=Active High, 1=Active Low */ - USHORT HSyncPolarity:1; /* 0=Active High, 1=Active Low */ - USHORT HorizontalCutOff:1; + USHORT Reserved:6; + USHORT RGB888:1; + USHORT DoubleClock:1; + USHORT Interlace:1; + USHORT CompositeSync:1; + USHORT V_ReplicationBy2:1; + USHORT H_ReplicationBy2:1; + USHORT VerticalCutOff:1; + USHORT VSyncPolarity:1; //0=Active High, 1=Active Low + USHORT HSyncPolarity:1; //0=Active High, 1=Active Low + USHORT HorizontalCutOff:1; #else - USHORT HorizontalCutOff:1; - USHORT HSyncPolarity:1; /* 0=Active High, 1=Active Low */ - USHORT VSyncPolarity:1; /* 0=Active High, 1=Active Low */ - USHORT VerticalCutOff:1; - USHORT H_ReplicationBy2:1; - USHORT V_ReplicationBy2:1; - USHORT CompositeSync:1; - USHORT Interlace:1; - USHORT DoubleClock:1; - USHORT RGB888:1; - USHORT Reserved:6; + USHORT HorizontalCutOff:1; + USHORT HSyncPolarity:1; //0=Active High, 1=Active Low + USHORT VSyncPolarity:1; //0=Active High, 1=Active Low + USHORT VerticalCutOff:1; + USHORT H_ReplicationBy2:1; + USHORT V_ReplicationBy2:1; + USHORT CompositeSync:1; + USHORT Interlace:1; + USHORT DoubleClock:1; + USHORT RGB888:1; + USHORT Reserved:6; #endif -} ATOM_MODE_MISC_INFO; - -typedef union _ATOM_MODE_MISC_INFO_ACCESS { - ATOM_MODE_MISC_INFO sbfAccess; - USHORT usAccess; -} ATOM_MODE_MISC_INFO_ACCESS; - +}ATOM_MODE_MISC_INFO; + +typedef union _ATOM_MODE_MISC_INFO_ACCESS +{ + ATOM_MODE_MISC_INFO sbfAccess; + USHORT usAccess; +}ATOM_MODE_MISC_INFO_ACCESS; + #else - -typedef union _ATOM_MODE_MISC_INFO_ACCESS { - USHORT usAccess; -} ATOM_MODE_MISC_INFO_ACCESS; - + +typedef union _ATOM_MODE_MISC_INFO_ACCESS +{ + USHORT usAccess; +}ATOM_MODE_MISC_INFO_ACCESS; + #endif -/* usModeMiscInfo- */ +// usModeMiscInfo- #define ATOM_H_CUTOFF 0x01 -#define ATOM_HSYNC_POLARITY 0x02 /* 0=Active High, 1=Active Low */ -#define ATOM_VSYNC_POLARITY 0x04 /* 0=Active High, 1=Active Low */ +#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low +#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low #define ATOM_V_CUTOFF 0x08 #define ATOM_H_REPLICATIONBY2 0x10 #define ATOM_V_REPLICATIONBY2 0x20 @@ -2099,10 +2581,10 @@ typedef union _ATOM_MODE_MISC_INFO_ACCESS { #define ATOM_DOUBLE_CLOCK_MODE 0x100 #define ATOM_RGB888_MODE 0x200 -/* usRefreshRate- */ +//usRefreshRate- #define ATOM_REFRESH_43 43 #define ATOM_REFRESH_47 47 -#define ATOM_REFRESH_56 56 +#define ATOM_REFRESH_56 56 #define ATOM_REFRESH_60 60 #define ATOM_REFRESH_65 65 #define ATOM_REFRESH_70 70 @@ -2110,192 +2592,233 @@ typedef union _ATOM_MODE_MISC_INFO_ACCESS { #define ATOM_REFRESH_75 75 #define ATOM_REFRESH_85 85 -/* ATOM_MODE_TIMING data are exactly the same as VESA timing data. */ -/* Translation from EDID to ATOM_MODE_TIMING, use the following formula. */ -/* */ -/* VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK */ -/* = EDID_HA + EDID_HBL */ -/* VESA_HDISP = VESA_ACTIVE = EDID_HA */ -/* VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH */ -/* = EDID_HA + EDID_HSO */ -/* VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW */ -/* VESA_BORDER = EDID_BORDER */ - -/****************************************************************************/ -/* Structure used in SetCRTC_UsingDTDTimingTable */ -/****************************************************************************/ -typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS { - USHORT usH_Size; - USHORT usH_Blanking_Time; - USHORT usV_Size; - USHORT usV_Blanking_Time; - USHORT usH_SyncOffset; - USHORT usH_SyncWidth; - USHORT usV_SyncOffset; - USHORT usV_SyncWidth; - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; - UCHAR ucH_Border; /* From DFP EDID */ - UCHAR ucV_Border; - UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ - UCHAR ucPadding[3]; -} SET_CRTC_USING_DTD_TIMING_PARAMETERS; - -/****************************************************************************/ -/* Structure used in SetCRTC_TimingTable */ -/****************************************************************************/ -typedef struct _SET_CRTC_TIMING_PARAMETERS { - USHORT usH_Total; /* horizontal total */ - USHORT usH_Disp; /* horizontal display */ - USHORT usH_SyncStart; /* horozontal Sync start */ - USHORT usH_SyncWidth; /* horizontal Sync width */ - USHORT usV_Total; /* vertical total */ - USHORT usV_Disp; /* vertical display */ - USHORT usV_SyncStart; /* vertical Sync start */ - USHORT usV_SyncWidth; /* vertical Sync width */ - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; - UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ - UCHAR ucOverscanRight; /* right */ - UCHAR ucOverscanLeft; /* left */ - UCHAR ucOverscanBottom; /* bottom */ - UCHAR ucOverscanTop; /* top */ - UCHAR ucReserved; -} SET_CRTC_TIMING_PARAMETERS; +// ATOM_MODE_TIMING data are exactly the same as VESA timing data. +// Translation from EDID to ATOM_MODE_TIMING, use the following formula. +// +// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK +// = EDID_HA + EDID_HBL +// VESA_HDISP = VESA_ACTIVE = EDID_HA +// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH +// = EDID_HA + EDID_HSO +// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW +// VESA_BORDER = EDID_BORDER + +/****************************************************************************/ +// Structure used in SetCRTC_UsingDTDTimingTable +/****************************************************************************/ +typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS +{ + USHORT usH_Size; + USHORT usH_Blanking_Time; + USHORT usV_Size; + USHORT usV_Blanking_Time; + USHORT usH_SyncOffset; + USHORT usH_SyncWidth; + USHORT usV_SyncOffset; + USHORT usV_SyncWidth; + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + UCHAR ucH_Border; // From DFP EDID + UCHAR ucV_Border; + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucPadding[3]; +}SET_CRTC_USING_DTD_TIMING_PARAMETERS; + +/****************************************************************************/ +// Structure used in SetCRTC_TimingTable +/****************************************************************************/ +typedef struct _SET_CRTC_TIMING_PARAMETERS +{ + USHORT usH_Total; // horizontal total + USHORT usH_Disp; // horizontal display + USHORT usH_SyncStart; // horozontal Sync start + USHORT usH_SyncWidth; // horizontal Sync width + USHORT usV_Total; // vertical total + USHORT usV_Disp; // vertical display + USHORT usV_SyncStart; // vertical Sync start + USHORT usV_SyncWidth; // vertical Sync width + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucOverscanRight; // right + UCHAR ucOverscanLeft; // left + UCHAR ucOverscanBottom; // bottom + UCHAR ucOverscanTop; // top + UCHAR ucReserved; +}SET_CRTC_TIMING_PARAMETERS; #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS -/****************************************************************************/ -/* Structure used in StandardVESA_TimingTable */ -/* AnalogTV_InfoTable */ -/* ComponentVideoInfoTable */ -/****************************************************************************/ -typedef struct _ATOM_MODE_TIMING { - USHORT usCRTC_H_Total; - USHORT usCRTC_H_Disp; - USHORT usCRTC_H_SyncStart; - USHORT usCRTC_H_SyncWidth; - USHORT usCRTC_V_Total; - USHORT usCRTC_V_Disp; - USHORT usCRTC_V_SyncStart; - USHORT usCRTC_V_SyncWidth; - USHORT usPixelClock; /* in 10Khz unit */ - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; - USHORT usCRTC_OverscanRight; - USHORT usCRTC_OverscanLeft; - USHORT usCRTC_OverscanBottom; - USHORT usCRTC_OverscanTop; - USHORT usReserve; - UCHAR ucInternalModeNumber; - UCHAR ucRefreshRate; -} ATOM_MODE_TIMING; - -typedef struct _ATOM_DTD_FORMAT { - USHORT usPixClk; - USHORT usHActive; - USHORT usHBlanking_Time; - USHORT usVActive; - USHORT usVBlanking_Time; - USHORT usHSyncOffset; - USHORT usHSyncWidth; - USHORT usVSyncOffset; - USHORT usVSyncWidth; - USHORT usImageHSize; - USHORT usImageVSize; - UCHAR ucHBorder; - UCHAR ucVBorder; - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; - UCHAR ucInternalModeNumber; - UCHAR ucRefreshRate; -} ATOM_DTD_FORMAT; - -/****************************************************************************/ -/* Structure used in LVDS_InfoTable */ -/* * Need a document to describe this table */ -/****************************************************************************/ +/****************************************************************************/ +// Structure used in StandardVESA_TimingTable +// AnalogTV_InfoTable +// ComponentVideoInfoTable +/****************************************************************************/ +typedef struct _ATOM_MODE_TIMING +{ + USHORT usCRTC_H_Total; + USHORT usCRTC_H_Disp; + USHORT usCRTC_H_SyncStart; + USHORT usCRTC_H_SyncWidth; + USHORT usCRTC_V_Total; + USHORT usCRTC_V_Disp; + USHORT usCRTC_V_SyncStart; + USHORT usCRTC_V_SyncWidth; + USHORT usPixelClock; //in 10Khz unit + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + USHORT usCRTC_OverscanRight; + USHORT usCRTC_OverscanLeft; + USHORT usCRTC_OverscanBottom; + USHORT usCRTC_OverscanTop; + USHORT usReserve; + UCHAR ucInternalModeNumber; + UCHAR ucRefreshRate; +}ATOM_MODE_TIMING; + +typedef struct _ATOM_DTD_FORMAT +{ + USHORT usPixClk; + USHORT usHActive; + USHORT usHBlanking_Time; + USHORT usVActive; + USHORT usVBlanking_Time; + USHORT usHSyncOffset; + USHORT usHSyncWidth; + USHORT usVSyncOffset; + USHORT usVSyncWidth; + USHORT usImageHSize; + USHORT usImageVSize; + UCHAR ucHBorder; + UCHAR ucVBorder; + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + UCHAR ucInternalModeNumber; + UCHAR ucRefreshRate; +}ATOM_DTD_FORMAT; + +/****************************************************************************/ +// Structure used in LVDS_InfoTable +// * Need a document to describe this table +/****************************************************************************/ #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 -/* Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. */ -/* Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL */ -#define LCDPANEL_CAP_READ_EDID 0x1 - -/* ucTableFormatRevision=1 */ -/* ucTableContentRevision=1 */ -typedef struct _ATOM_LVDS_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_DTD_FORMAT sLCDTiming; - USHORT usModePatchTableOffset; - USHORT usSupportedRefreshRate; /* Refer to panel info table in ATOMBIOS extension Spec. */ - USHORT usOffDelayInMs; - UCHAR ucPowerSequenceDigOntoDEin10Ms; - UCHAR ucPowerSequenceDEtoBLOnin10Ms; - UCHAR ucLVDS_Misc; /* Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} */ - /* Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} */ - /* Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} */ - /* Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} */ - UCHAR ucPanelDefaultRefreshRate; - UCHAR ucPanelIdentification; - UCHAR ucSS_Id; -} ATOM_LVDS_INFO; - -/* ucTableFormatRevision=1 */ -/* ucTableContentRevision=2 */ -typedef struct _ATOM_LVDS_INFO_V12 { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_DTD_FORMAT sLCDTiming; - USHORT usExtInfoTableOffset; - USHORT usSupportedRefreshRate; /* Refer to panel info table in ATOMBIOS extension Spec. */ - USHORT usOffDelayInMs; - UCHAR ucPowerSequenceDigOntoDEin10Ms; - UCHAR ucPowerSequenceDEtoBLOnin10Ms; - UCHAR ucLVDS_Misc; /* Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} */ - /* Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} */ - /* Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} */ - /* Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} */ - UCHAR ucPanelDefaultRefreshRate; - UCHAR ucPanelIdentification; - UCHAR ucSS_Id; - USHORT usLCDVenderID; - USHORT usLCDProductID; - UCHAR ucLCDPanel_SpecialHandlingCap; - UCHAR ucPanelInfoSize; /* start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable */ - UCHAR ucReserved[2]; -} ATOM_LVDS_INFO_V12; +//ucTableFormatRevision=1 +//ucTableContentRevision=1 +typedef struct _ATOM_LVDS_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_DTD_FORMAT sLCDTiming; + USHORT usModePatchTableOffset; + USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. + USHORT usOffDelayInMs; + UCHAR ucPowerSequenceDigOntoDEin10Ms; + UCHAR ucPowerSequenceDEtoBLOnin10Ms; + UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} + // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} + // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} + // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} + UCHAR ucPanelDefaultRefreshRate; + UCHAR ucPanelIdentification; + UCHAR ucSS_Id; +}ATOM_LVDS_INFO; + +//ucTableFormatRevision=1 +//ucTableContentRevision=2 +typedef struct _ATOM_LVDS_INFO_V12 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_DTD_FORMAT sLCDTiming; + USHORT usExtInfoTableOffset; + USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. + USHORT usOffDelayInMs; + UCHAR ucPowerSequenceDigOntoDEin10Ms; + UCHAR ucPowerSequenceDEtoBLOnin10Ms; + UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} + // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} + // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} + // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} + UCHAR ucPanelDefaultRefreshRate; + UCHAR ucPanelIdentification; + UCHAR ucSS_Id; + USHORT usLCDVenderID; + USHORT usLCDProductID; + UCHAR ucLCDPanel_SpecialHandlingCap; + UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable + UCHAR ucReserved[2]; +}ATOM_LVDS_INFO_V12; + +//Definitions for ucLCDPanel_SpecialHandlingCap: + +//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. +//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL +#define LCDPANEL_CAP_READ_EDID 0x1 + +//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together +//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static +//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 +#define LCDPANEL_CAP_DRR_SUPPORTED 0x2 + +//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. +#define LCDPANEL_CAP_eDP 0x4 + + +//Color Bit Depth definition in EDID V1.4 @BYTE 14h +//Bit 6 5 4 + // 0 0 0 - Color bit depth is undefined + // 0 0 1 - 6 Bits per Primary Color + // 0 1 0 - 8 Bits per Primary Color + // 0 1 1 - 10 Bits per Primary Color + // 1 0 0 - 12 Bits per Primary Color + // 1 0 1 - 14 Bits per Primary Color + // 1 1 0 - 16 Bits per Primary Color + // 1 1 1 - Reserved + +#define PANEL_COLOR_BIT_DEPTH_MASK 0x70 + +// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} +#define PANEL_RANDOM_DITHER 0x80 +#define PANEL_RANDOM_DITHER_MASK 0x80 + #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 -typedef struct _ATOM_PATCH_RECORD_MODE { - UCHAR ucRecordType; - USHORT usHDisp; - USHORT usVDisp; -} ATOM_PATCH_RECORD_MODE; +typedef struct _ATOM_PATCH_RECORD_MODE +{ + UCHAR ucRecordType; + USHORT usHDisp; + USHORT usVDisp; +}ATOM_PATCH_RECORD_MODE; -typedef struct _ATOM_LCD_RTS_RECORD { - UCHAR ucRecordType; - UCHAR ucRTSValue; -} ATOM_LCD_RTS_RECORD; +typedef struct _ATOM_LCD_RTS_RECORD +{ + UCHAR ucRecordType; + UCHAR ucRTSValue; +}ATOM_LCD_RTS_RECORD; -/* !! If the record below exits, it shoud always be the first record for easy use in command table!!! */ -typedef struct _ATOM_LCD_MODE_CONTROL_CAP { - UCHAR ucRecordType; - USHORT usLCDCap; -} ATOM_LCD_MODE_CONTROL_CAP; +//!! If the record below exits, it shoud always be the first record for easy use in command table!!! +// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. +typedef struct _ATOM_LCD_MODE_CONTROL_CAP +{ + UCHAR ucRecordType; + USHORT usLCDCap; +}ATOM_LCD_MODE_CONTROL_CAP; #define LCD_MODE_CAP_BL_OFF 1 #define LCD_MODE_CAP_CRTC_OFF 2 #define LCD_MODE_CAP_PANEL_OFF 4 -typedef struct _ATOM_FAKE_EDID_PATCH_RECORD { - UCHAR ucRecordType; - UCHAR ucFakeEDIDLength; - UCHAR ucFakeEDIDString[1]; /* This actually has ucFakeEdidLength elements. */ +typedef struct _ATOM_FAKE_EDID_PATCH_RECORD +{ + UCHAR ucRecordType; + UCHAR ucFakeEDIDLength; + UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. } ATOM_FAKE_EDID_PATCH_RECORD; -typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD { - UCHAR ucRecordType; - USHORT usHSize; - USHORT usVSize; -} ATOM_PANEL_RESOLUTION_PATCH_RECORD; +typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD +{ + UCHAR ucRecordType; + USHORT usHSize; + USHORT usVSize; +}ATOM_PANEL_RESOLUTION_PATCH_RECORD; #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 #define LCD_RTS_RECORD_TYPE 2 @@ -2306,21 +2829,25 @@ typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD { /****************************Spread Spectrum Info Table Definitions **********************/ -/* ucTableFormatRevision=1 */ -/* ucTableContentRevision=2 */ -typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT { - USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */ - UCHAR ucSS_Step; - UCHAR ucSS_Delay; - UCHAR ucSS_Id; - UCHAR ucRecommendedRef_Div; - UCHAR ucSS_Range; /* it was reserved for V11 */ -} ATOM_SPREAD_SPECTRUM_ASSIGNMENT; +//ucTableFormatRevision=1 +//ucTableContentRevision=2 +typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD + UCHAR ucSS_Step; + UCHAR ucSS_Delay; + UCHAR ucSS_Id; + UCHAR ucRecommendedRef_Div; + UCHAR ucSS_Range; //it was reserved for V11 +}ATOM_SPREAD_SPECTRUM_ASSIGNMENT; #define ATOM_MAX_SS_ENTRY 16 -#define ATOM_DP_SS_ID1 0x0f1 /* SS modulation freq=30k */ -#define ATOM_DP_SS_ID2 0x0f2 /* SS modulation freq=33k */ +#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. +#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. +#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz +#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz + #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 @@ -2329,29 +2856,30 @@ typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT { #define ATOM_INTERNAL_SS_MASK 0x00000000 #define ATOM_EXTERNAL_SS_MASK 0x00000002 #define EXEC_SS_STEP_SIZE_SHIFT 2 -#define EXEC_SS_DELAY_SHIFT 4 +#define EXEC_SS_DELAY_SHIFT 4 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 -typedef struct _ATOM_SPREAD_SPECTRUM_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; -} ATOM_SPREAD_SPECTRUM_INFO; - -/****************************************************************************/ -/* Structure used in AnalogTV_InfoTable (Top level) */ -/****************************************************************************/ -/* ucTVBootUpDefaultStd definiton: */ - -/* ATOM_TV_NTSC 1 */ -/* ATOM_TV_NTSCJ 2 */ -/* ATOM_TV_PAL 3 */ -/* ATOM_TV_PALM 4 */ -/* ATOM_TV_PALCN 5 */ -/* ATOM_TV_PALN 6 */ -/* ATOM_TV_PAL60 7 */ -/* ATOM_TV_SECAM 8 */ - -/* ucTVSuppportedStd definition: */ +typedef struct _ATOM_SPREAD_SPECTRUM_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; +}ATOM_SPREAD_SPECTRUM_INFO; + +/****************************************************************************/ +// Structure used in AnalogTV_InfoTable (Top level) +/****************************************************************************/ +//ucTVBootUpDefaultStd definiton: + +//ATOM_TV_NTSC 1 +//ATOM_TV_NTSCJ 2 +//ATOM_TV_PAL 3 +//ATOM_TV_PALM 4 +//ATOM_TV_PALCN 5 +//ATOM_TV_PALN 6 +//ATOM_TV_PAL60 7 +//ATOM_TV_SECAM 8 + +//ucTVSupportedStd definition: #define NTSC_SUPPORT 0x1 #define NTSCJ_SUPPORT 0x2 @@ -2364,46 +2892,58 @@ typedef struct _ATOM_SPREAD_SPECTRUM_INFO { #define MAX_SUPPORTED_TV_TIMING 2 -typedef struct _ATOM_ANALOG_TV_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucTV_SupportedStandard; - UCHAR ucTV_BootUpDefaultStandard; - UCHAR ucExt_TV_ASIC_ID; - UCHAR ucExt_TV_ASIC_SlaveAddr; - /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; */ - ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; -} ATOM_ANALOG_TV_INFO; +typedef struct _ATOM_ANALOG_TV_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucTV_SupportedStandard; + UCHAR ucTV_BootUpDefaultStandard; + UCHAR ucExt_TV_ASIC_ID; + UCHAR ucExt_TV_ASIC_SlaveAddr; + /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ + ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; +}ATOM_ANALOG_TV_INFO; #define MAX_SUPPORTED_TV_TIMING_V1_2 3 -typedef struct _ATOM_ANALOG_TV_INFO_V1_2 { - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucTV_SupportedStandard; - UCHAR ucTV_BootUpDefaultStandard; - UCHAR ucExt_TV_ASIC_ID; - UCHAR ucExt_TV_ASIC_SlaveAddr; - ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; -} ATOM_ANALOG_TV_INFO_V1_2; +typedef struct _ATOM_ANALOG_TV_INFO_V1_2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucTV_SupportedStandard; + UCHAR ucTV_BootUpDefaultStandard; + UCHAR ucExt_TV_ASIC_ID; + UCHAR ucExt_TV_ASIC_SlaveAddr; + ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; +}ATOM_ANALOG_TV_INFO_V1_2; + +typedef struct _ATOM_DPCD_INFO +{ + UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 + UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane + UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP + UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) +}ATOM_DPCD_INFO; + +#define ATOM_DPCD_MAX_LANE_MASK 0x1F /**************************************************************************/ -/* VRAM usage and their defintions */ +// VRAM usage and their defintions -/* One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. */ -/* Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. */ -/* All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! */ -/* To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR */ -/* To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX */ +// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. +// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. +// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! +// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR +// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX #ifndef VESA_MEMORY_IN_64K_BLOCK -#define VESA_MEMORY_IN_64K_BLOCK 0x100 /* 256*64K=16Mb (Max. VESA memory is 16Mb!) */ +#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) #endif -#define ATOM_EDID_RAW_DATASIZE 256 /* In Bytes */ -#define ATOM_HWICON_SURFACE_SIZE 4096 /* In Bytes */ +#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes +#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes #define ATOM_HWICON_INFOTABLE_SIZE 32 #define MAX_DTD_MODE_IN_VRAM 6 -#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) /* 28= (SIZEOF ATOM_DTD_FORMAT) */ -#define ATOM_STD_MODE_SUPPORT_TBL_SIZE (32*8) /* 32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) */ +#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) +#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) #define DFP_ENCODER_TYPE_OFFSET 0x80 #define DP_ENCODER_LANE_NUM_OFFSET 0x84 #define DP_ENCODER_LINK_RATE_OFFSET 0x88 @@ -2417,7 +2957,7 @@ typedef struct _ATOM_ANALOG_TV_INFO_V1_2 { #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) @@ -2431,13 +2971,13 @@ typedef struct _ATOM_ANALOG_TV_INFO_V1_2 { #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_TV2_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_TV2_DTD_MODE_TBL_ADDR (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_TV2_STD_MODE_TBL_ADDR (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_DFP2_EDID_ADDR (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) @@ -2457,533 +2997,850 @@ typedef struct _ATOM_ANALOG_TV_INFO_V1_2 { #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 256) -#define ATOM_STACK_STORAGE_END (ATOM_STACK_STORAGE_START + 512) +#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256) +#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512 -/* The size below is in Kb! */ +//The size below is in Kb! #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) - + #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 -/***********************************************************************************/ -/* Structure used in VRAM_UsageByFirmwareTable */ -/* Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm */ -/* at running time. */ -/* note2: From RV770, the memory is more than 32bit addressable, so we will change */ -/* ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains */ -/* exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware */ -/* (in offset to start of memory address) is KB aligned instead of byte aligend. */ -/***********************************************************************************/ +/***********************************************************************************/ +// Structure used in VRAM_UsageByFirmwareTable +// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm +// at running time. +// note2: From RV770, the memory is more than 32bit addressable, so we will change +// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains +// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware +// (in offset to start of memory address) is KB aligned instead of byte aligend. +/***********************************************************************************/ +// Note3: +/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, +for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: + +If (ulStartAddrUsedByFirmware!=0) +FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; +Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose +else //Non VGA case + if (FB_Size<=2Gb) + FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; + else + FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB + +CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ + #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 -typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO { - ULONG ulStartAddrUsedByFirmware; - USHORT usFirmwareUseInKb; - USHORT usReserved; -} ATOM_FIRMWARE_VRAM_RESERVE_INFO; +typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO +{ + ULONG ulStartAddrUsedByFirmware; + USHORT usFirmwareUseInKb; + USHORT usReserved; +}ATOM_FIRMWARE_VRAM_RESERVE_INFO; -typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_FIRMWARE_VRAM_RESERVE_INFO - asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; -} ATOM_VRAM_USAGE_BY_FIRMWARE; +typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; +}ATOM_VRAM_USAGE_BY_FIRMWARE; -/****************************************************************************/ -/* Structure used in GPIO_Pin_LUTTable */ -/****************************************************************************/ -typedef struct _ATOM_GPIO_PIN_ASSIGNMENT { - USHORT usGpioPin_AIndex; - UCHAR ucGpioPinBitShift; - UCHAR ucGPIO_ID; -} ATOM_GPIO_PIN_ASSIGNMENT; +// change verion to 1.5, when allow driver to allocate the vram area for command table access. +typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 +{ + ULONG ulStartAddrUsedByFirmware; + USHORT usFirmwareUseInKb; + USHORT usFBUsedByDrvInKb; +}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; -typedef struct _ATOM_GPIO_PIN_LUT { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; -} ATOM_GPIO_PIN_LUT; +typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; +}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; + +/****************************************************************************/ +// Structure used in GPIO_Pin_LUTTable +/****************************************************************************/ +typedef struct _ATOM_GPIO_PIN_ASSIGNMENT +{ + USHORT usGpioPin_AIndex; + UCHAR ucGpioPinBitShift; + UCHAR ucGPIO_ID; +}ATOM_GPIO_PIN_ASSIGNMENT; -/****************************************************************************/ -/* Structure used in ComponentVideoInfoTable */ -/****************************************************************************/ +typedef struct _ATOM_GPIO_PIN_LUT +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; +}ATOM_GPIO_PIN_LUT; + +/****************************************************************************/ +// Structure used in ComponentVideoInfoTable +/****************************************************************************/ #define GPIO_PIN_ACTIVE_HIGH 0x1 #define MAX_SUPPORTED_CV_STANDARDS 5 -/* definitions for ATOM_D_INFO.ucSettings */ -#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F /* [4:0] */ -#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 /* [6:5] = must be zeroed out */ -#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 /* [7] */ +// definitions for ATOM_D_INFO.ucSettings +#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] +#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out +#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] -typedef struct _ATOM_GPIO_INFO { - USHORT usAOffset; - UCHAR ucSettings; - UCHAR ucReserved; -} ATOM_GPIO_INFO; +typedef struct _ATOM_GPIO_INFO +{ + USHORT usAOffset; + UCHAR ucSettings; + UCHAR ucReserved; +}ATOM_GPIO_INFO; -/* definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) */ +// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 -/* definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i */ -#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 /* [7]; */ -#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F /* [6:0] */ - -/* definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode */ -/* Line 3 out put 5V. */ -#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 /* represent gpio 3 state for 16:9 */ -#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 /* represent gpio 4 state for 16:9 */ -#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 - -/* Line 3 out put 2.2V */ -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 /* represent gpio 3 state for 4:3 Letter box */ -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 /* represent gpio 4 state for 4:3 Letter box */ -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 - -/* Line 3 out put 0V */ -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 /* represent gpio 3 state for 4:3 */ -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 /* represent gpio 4 state for 4:3 */ -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 - -#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F /* bit [5:0] */ - -#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 /* bit 7 */ - -/* GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. */ -#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 /* bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. */ -#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 /* bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. */ - -typedef struct _ATOM_COMPONENT_VIDEO_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMask_PinRegisterIndex; - USHORT usEN_PinRegisterIndex; - USHORT usY_PinRegisterIndex; - USHORT usA_PinRegisterIndex; - UCHAR ucBitShift; - UCHAR ucPinActiveState; /* ucPinActiveState: Bit0=1 active high, =0 active low */ - ATOM_DTD_FORMAT sReserved; /* must be zeroed out */ - UCHAR ucMiscInfo; - UCHAR uc480i; - UCHAR uc480p; - UCHAR uc720p; - UCHAR uc1080i; - UCHAR ucLetterBoxMode; - UCHAR ucReserved[3]; - UCHAR ucNumOfWbGpioBlocks; /* For Component video D-Connector support. If zere, NTSC type connector */ - ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; - ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; -} ATOM_COMPONENT_VIDEO_INFO; - -/* ucTableFormatRevision=2 */ -/* ucTableContentRevision=1 */ -typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 { - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucMiscInfo; - UCHAR uc480i; - UCHAR uc480p; - UCHAR uc720p; - UCHAR uc1080i; - UCHAR ucReserved; - UCHAR ucLetterBoxMode; - UCHAR ucNumOfWbGpioBlocks; /* For Component video D-Connector support. If zere, NTSC type connector */ - ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; - ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; -} ATOM_COMPONENT_VIDEO_INFO_V21; +// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i +#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; +#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] + +// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode +//Line 3 out put 5V. +#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 +#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 +#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 + +//Line 3 out put 2.2V +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 + +//Line 3 out put 0V +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 + +#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] + +#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 + +//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. +#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. +#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. + + +typedef struct _ATOM_COMPONENT_VIDEO_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMask_PinRegisterIndex; + USHORT usEN_PinRegisterIndex; + USHORT usY_PinRegisterIndex; + USHORT usA_PinRegisterIndex; + UCHAR ucBitShift; + UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low + ATOM_DTD_FORMAT sReserved; // must be zeroed out + UCHAR ucMiscInfo; + UCHAR uc480i; + UCHAR uc480p; + UCHAR uc720p; + UCHAR uc1080i; + UCHAR ucLetterBoxMode; + UCHAR ucReserved[3]; + UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector + ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; + ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; +}ATOM_COMPONENT_VIDEO_INFO; + +//ucTableFormatRevision=2 +//ucTableContentRevision=1 +typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucMiscInfo; + UCHAR uc480i; + UCHAR uc480p; + UCHAR uc720p; + UCHAR uc1080i; + UCHAR ucReserved; + UCHAR ucLetterBoxMode; + UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector + ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; + ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; +}ATOM_COMPONENT_VIDEO_INFO_V21; #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 -/****************************************************************************/ -/* Structure used in object_InfoTable */ -/****************************************************************************/ -typedef struct _ATOM_OBJECT_HEADER { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - USHORT usConnectorObjectTableOffset; - USHORT usRouterObjectTableOffset; - USHORT usEncoderObjectTableOffset; - USHORT usProtectionObjectTableOffset; /* only available when Protection block is independent. */ - USHORT usDisplayPathTableOffset; -} ATOM_OBJECT_HEADER; - -typedef struct _ATOM_DISPLAY_OBJECT_PATH { - USHORT usDeviceTag; /* supported device */ - USHORT usSize; /* the size of ATOM_DISPLAY_OBJECT_PATH */ - USHORT usConnObjectId; /* Connector Object ID */ - USHORT usGPUObjectId; /* GPU ID */ - USHORT usGraphicObjIds[1]; /* 1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. */ -} ATOM_DISPLAY_OBJECT_PATH; - -typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE { - UCHAR ucNumOfDispPath; - UCHAR ucVersion; - UCHAR ucPadding[2]; - ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; -} ATOM_DISPLAY_OBJECT_PATH_TABLE; - -typedef struct _ATOM_OBJECT /* each object has this structure */ -{ - USHORT usObjectID; - USHORT usSrcDstTableOffset; - USHORT usRecordOffset; /* this pointing to a bunch of records defined below */ - USHORT usReserved; -} ATOM_OBJECT; - -typedef struct _ATOM_OBJECT_TABLE /* Above 4 object table offset pointing to a bunch of objects all have this structure */ -{ - UCHAR ucNumberOfObjects; - UCHAR ucPadding[3]; - ATOM_OBJECT asObjects[1]; -} ATOM_OBJECT_TABLE; - -typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT /* usSrcDstTableOffset pointing to this structure */ -{ - UCHAR ucNumberOfSrc; - USHORT usSrcObjectID[1]; - UCHAR ucNumberOfDst; - USHORT usDstObjectID[1]; -} ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; - -/* Related definitions, all records are differnt but they have a commond header */ -typedef struct _ATOM_COMMON_RECORD_HEADER { - UCHAR ucRecordType; /* An emun to indicate the record type */ - UCHAR ucRecordSize; /* The size of the whole record in byte */ -} ATOM_COMMON_RECORD_HEADER; - -#define ATOM_I2C_RECORD_TYPE 1 +/****************************************************************************/ +// Structure used in object_InfoTable +/****************************************************************************/ +typedef struct _ATOM_OBJECT_HEADER +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + USHORT usConnectorObjectTableOffset; + USHORT usRouterObjectTableOffset; + USHORT usEncoderObjectTableOffset; + USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. + USHORT usDisplayPathTableOffset; +}ATOM_OBJECT_HEADER; + +typedef struct _ATOM_OBJECT_HEADER_V3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + USHORT usConnectorObjectTableOffset; + USHORT usRouterObjectTableOffset; + USHORT usEncoderObjectTableOffset; + USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. + USHORT usDisplayPathTableOffset; + USHORT usMiscObjectTableOffset; +}ATOM_OBJECT_HEADER_V3; + +typedef struct _ATOM_DISPLAY_OBJECT_PATH +{ + USHORT usDeviceTag; //supported device + USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH + USHORT usConnObjectId; //Connector Object ID + USHORT usGPUObjectId; //GPU ID + USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. +}ATOM_DISPLAY_OBJECT_PATH; + +typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE +{ + UCHAR ucNumOfDispPath; + UCHAR ucVersion; + UCHAR ucPadding[2]; + ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; +}ATOM_DISPLAY_OBJECT_PATH_TABLE; + + +typedef struct _ATOM_OBJECT //each object has this structure +{ + USHORT usObjectID; + USHORT usSrcDstTableOffset; + USHORT usRecordOffset; //this pointing to a bunch of records defined below + USHORT usReserved; +}ATOM_OBJECT; + +typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure +{ + UCHAR ucNumberOfObjects; + UCHAR ucPadding[3]; + ATOM_OBJECT asObjects[1]; +}ATOM_OBJECT_TABLE; + +typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure +{ + UCHAR ucNumberOfSrc; + USHORT usSrcObjectID[1]; + UCHAR ucNumberOfDst; + USHORT usDstObjectID[1]; +}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; + + +//Two definitions below are for OPM on MXM module designs + +#define EXT_HPDPIN_LUTINDEX_0 0 +#define EXT_HPDPIN_LUTINDEX_1 1 +#define EXT_HPDPIN_LUTINDEX_2 2 +#define EXT_HPDPIN_LUTINDEX_3 3 +#define EXT_HPDPIN_LUTINDEX_4 4 +#define EXT_HPDPIN_LUTINDEX_5 5 +#define EXT_HPDPIN_LUTINDEX_6 6 +#define EXT_HPDPIN_LUTINDEX_7 7 +#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) + +#define EXT_AUXDDC_LUTINDEX_0 0 +#define EXT_AUXDDC_LUTINDEX_1 1 +#define EXT_AUXDDC_LUTINDEX_2 2 +#define EXT_AUXDDC_LUTINDEX_3 3 +#define EXT_AUXDDC_LUTINDEX_4 4 +#define EXT_AUXDDC_LUTINDEX_5 5 +#define EXT_AUXDDC_LUTINDEX_6 6 +#define EXT_AUXDDC_LUTINDEX_7 7 +#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) + +typedef struct _EXT_DISPLAY_PATH +{ + USHORT usDeviceTag; //A bit vector to show what devices are supported + USHORT usDeviceACPIEnum; //16bit device ACPI id. + USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions + UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT + UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT + USHORT usExtEncoderObjId; //external encoder object id + USHORT usReserved[3]; +}EXT_DISPLAY_PATH; + +#define NUMBER_OF_UCHAR_FOR_GUID 16 +#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 + +typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string + EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. + UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. + UCHAR Reserved [7]; // for potential expansion +}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; + +//Related definitions, all records are differnt but they have a commond header +typedef struct _ATOM_COMMON_RECORD_HEADER +{ + UCHAR ucRecordType; //An emun to indicate the record type + UCHAR ucRecordSize; //The size of the whole record in byte +}ATOM_COMMON_RECORD_HEADER; + + +#define ATOM_I2C_RECORD_TYPE 1 #define ATOM_HPD_INT_RECORD_TYPE 2 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 -#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */ -#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */ +#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE +#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 -#define ATOM_JTAG_RECORD_TYPE 8 /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */ +#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 -#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 -#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 - -/* Must be updated when new record type is added,equal to that record definition! */ -#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_CF_RECORD_TYPE - -typedef struct _ATOM_I2C_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - ATOM_I2C_ID_CONFIG sucI2cId; - UCHAR ucI2CAddr; /* The slave address, it's 0 when the record is attached to connector for DDC */ -} ATOM_I2C_RECORD; - -typedef struct _ATOM_HPD_INT_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucHPDIntGPIOID; /* Corresponding block in GPIO_PIN_INFO table gives the pin info */ - UCHAR ucPlugged_PinState; -} ATOM_HPD_INT_RECORD; - -typedef struct _ATOM_OUTPUT_PROTECTION_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucProtectionFlag; - UCHAR ucReserved; -} ATOM_OUTPUT_PROTECTION_RECORD; - -typedef struct _ATOM_CONNECTOR_DEVICE_TAG { - ULONG ulACPIDeviceEnum; /* Reserved for now */ - USHORT usDeviceID; /* This Id is same as "ATOM_DEVICE_XXX_SUPPORT" */ - USHORT usPadding; -} ATOM_CONNECTOR_DEVICE_TAG; - -typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucNumberOfDevice; - UCHAR ucReserved; - ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; /* This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation */ -} ATOM_CONNECTOR_DEVICE_TAG_RECORD; - -typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucConfigGPIOID; - UCHAR ucConfigGPIOState; /* Set to 1 when it's active high to enable external flow in */ - UCHAR ucFlowinGPIPID; - UCHAR ucExtInGPIPID; -} ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; - -typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucCTL1GPIO_ID; - UCHAR ucCTL1GPIOState; /* Set to 1 when it's active high */ - UCHAR ucCTL2GPIO_ID; - UCHAR ucCTL2GPIOState; /* Set to 1 when it's active high */ - UCHAR ucCTL3GPIO_ID; - UCHAR ucCTL3GPIOState; /* Set to 1 when it's active high */ - UCHAR ucCTLFPGA_IN_ID; - UCHAR ucPadding[3]; -} ATOM_ENCODER_FPGA_CONTROL_RECORD; - -typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucGPIOID; /* Corresponding block in GPIO_PIN_INFO table gives the pin info */ - UCHAR ucTVActiveState; /* Indicating when the pin==0 or 1 when TV is connected */ -} ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; - -typedef struct _ATOM_JTAG_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucTMSGPIO_ID; - UCHAR ucTMSGPIOState; /* Set to 1 when it's active high */ - UCHAR ucTCKGPIO_ID; - UCHAR ucTCKGPIOState; /* Set to 1 when it's active high */ - UCHAR ucTDOGPIO_ID; - UCHAR ucTDOGPIOState; /* Set to 1 when it's active high */ - UCHAR ucTDIGPIO_ID; - UCHAR ucTDIGPIOState; /* Set to 1 when it's active high */ - UCHAR ucPadding[2]; -} ATOM_JTAG_RECORD; - -/* The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually */ -typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR { - UCHAR ucGPIOID; /* GPIO_ID, find the corresponding ID in GPIO_LUT table */ - UCHAR ucGPIO_PinState; /* Pin state showing how to set-up the pin */ -} ATOM_GPIO_PIN_CONTROL_PAIR; - -typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucFlags; /* Future expnadibility */ - UCHAR ucNumberOfPins; /* Number of GPIO pins used to control the object */ - ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; /* the real gpio pin pair determined by number of pins ucNumberOfPins */ -} ATOM_OBJECT_GPIO_CNTL_RECORD; - -/* Definitions for GPIO pin state */ +#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 +#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 +#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table +#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table +#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record +#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 + + +//Must be updated when new record type is added,equal to that record definition! +#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE + +typedef struct _ATOM_I2C_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + ATOM_I2C_ID_CONFIG sucI2cId; + UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC +}ATOM_I2C_RECORD; + +typedef struct _ATOM_HPD_INT_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info + UCHAR ucPlugged_PinState; +}ATOM_HPD_INT_RECORD; + + +typedef struct _ATOM_OUTPUT_PROTECTION_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucProtectionFlag; + UCHAR ucReserved; +}ATOM_OUTPUT_PROTECTION_RECORD; + +typedef struct _ATOM_CONNECTOR_DEVICE_TAG +{ + ULONG ulACPIDeviceEnum; //Reserved for now + USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" + USHORT usPadding; +}ATOM_CONNECTOR_DEVICE_TAG; + +typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucNumberOfDevice; + UCHAR ucReserved; + ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation +}ATOM_CONNECTOR_DEVICE_TAG_RECORD; + + +typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucConfigGPIOID; + UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in + UCHAR ucFlowinGPIPID; + UCHAR ucExtInGPIPID; +}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; + +typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucCTL1GPIO_ID; + UCHAR ucCTL1GPIOState; //Set to 1 when it's active high + UCHAR ucCTL2GPIO_ID; + UCHAR ucCTL2GPIOState; //Set to 1 when it's active high + UCHAR ucCTL3GPIO_ID; + UCHAR ucCTL3GPIOState; //Set to 1 when it's active high + UCHAR ucCTLFPGA_IN_ID; + UCHAR ucPadding[3]; +}ATOM_ENCODER_FPGA_CONTROL_RECORD; + +typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info + UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected +}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; + +typedef struct _ATOM_JTAG_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucTMSGPIO_ID; + UCHAR ucTMSGPIOState; //Set to 1 when it's active high + UCHAR ucTCKGPIO_ID; + UCHAR ucTCKGPIOState; //Set to 1 when it's active high + UCHAR ucTDOGPIO_ID; + UCHAR ucTDOGPIOState; //Set to 1 when it's active high + UCHAR ucTDIGPIO_ID; + UCHAR ucTDIGPIOState; //Set to 1 when it's active high + UCHAR ucPadding[2]; +}ATOM_JTAG_RECORD; + + +//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually +typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR +{ + UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table + UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin +}ATOM_GPIO_PIN_CONTROL_PAIR; + +typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucFlags; // Future expnadibility + UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object + ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins +}ATOM_OBJECT_GPIO_CNTL_RECORD; + +//Definitions for GPIO pin state #define GPIO_PIN_TYPE_INPUT 0x00 #define GPIO_PIN_TYPE_OUTPUT 0x10 #define GPIO_PIN_TYPE_HW_CONTROL 0x20 -/* For GPIO_PIN_TYPE_OUTPUT the following is defined */ +//For GPIO_PIN_TYPE_OUTPUT the following is defined #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 -typedef struct _ATOM_ENCODER_DVO_CF_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - ULONG ulStrengthControl; /* DVOA strength control for CF */ - UCHAR ucPadding[2]; -} ATOM_ENCODER_DVO_CF_RECORD; +// Indexes to GPIO array in GLSync record +#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 +#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 +#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 +#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 +#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 +#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 +#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 +#define ATOM_GPIO_INDEX_GLSYNC_MAX 7 + +typedef struct _ATOM_ENCODER_DVO_CF_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + ULONG ulStrengthControl; // DVOA strength control for CF + UCHAR ucPadding[2]; +}ATOM_ENCODER_DVO_CF_RECORD; -/* value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle */ +// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 -typedef struct _ATOM_CONNECTOR_CF_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - USHORT usMaxPixClk; - UCHAR ucFlowCntlGpioId; - UCHAR ucSwapCntlGpioId; - UCHAR ucConnectedDvoBundle; - UCHAR ucPadding; -} ATOM_CONNECTOR_CF_RECORD; - -typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - ATOM_DTD_FORMAT asTiming; -} ATOM_CONNECTOR_HARDCODE_DTD_RECORD; - -typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; /* ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE */ - UCHAR ucSubConnectorType; /* CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A */ - UCHAR ucReserved; -} ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; - -typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucMuxType; /* decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state */ - UCHAR ucMuxControlPin; - UCHAR ucMuxState[2]; /* for alligment purpose */ -} ATOM_ROUTER_DDC_PATH_SELECT_RECORD; - -typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucMuxType; - UCHAR ucMuxControlPin; - UCHAR ucMuxState[2]; /* for alligment purpose */ -} ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; - -/* define ucMuxType */ +typedef struct _ATOM_CONNECTOR_CF_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + USHORT usMaxPixClk; + UCHAR ucFlowCntlGpioId; + UCHAR ucSwapCntlGpioId; + UCHAR ucConnectedDvoBundle; + UCHAR ucPadding; +}ATOM_CONNECTOR_CF_RECORD; + +typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + ATOM_DTD_FORMAT asTiming; +}ATOM_CONNECTOR_HARDCODE_DTD_RECORD; + +typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE + UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A + UCHAR ucReserved; +}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; + + +typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state + UCHAR ucMuxControlPin; + UCHAR ucMuxState[2]; //for alligment purpose +}ATOM_ROUTER_DDC_PATH_SELECT_RECORD; + +typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucMuxType; + UCHAR ucMuxControlPin; + UCHAR ucMuxState[2]; //for alligment purpose +}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; + +// define ucMuxType #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 -/****************************************************************************/ -/* ASIC voltage data table */ -/****************************************************************************/ -typedef struct _ATOM_VOLTAGE_INFO_HEADER { - USHORT usVDDCBaseLevel; /* In number of 50mv unit */ - USHORT usReserved; /* For possible extension table offset */ - UCHAR ucNumOfVoltageEntries; - UCHAR ucBytesPerVoltageEntry; - UCHAR ucVoltageStep; /* Indicating in how many mv increament is one step, 0.5mv unit */ - UCHAR ucDefaultVoltageEntry; - UCHAR ucVoltageControlI2cLine; - UCHAR ucVoltageControlAddress; - UCHAR ucVoltageControlOffset; -} ATOM_VOLTAGE_INFO_HEADER; - -typedef struct _ATOM_VOLTAGE_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VOLTAGE_INFO_HEADER viHeader; - UCHAR ucVoltageEntries[64]; /* 64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry */ -} ATOM_VOLTAGE_INFO; - -typedef struct _ATOM_VOLTAGE_FORMULA { - USHORT usVoltageBaseLevel; /* In number of 1mv unit */ - USHORT usVoltageStep; /* Indicating in how many mv increament is one step, 1mv unit */ - UCHAR ucNumOfVoltageEntries; /* Number of Voltage Entry, which indicate max Voltage */ - UCHAR ucFlag; /* bit0=0 :step is 1mv =1 0.5mv */ - UCHAR ucBaseVID; /* if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep */ - UCHAR ucReserved; - UCHAR ucVIDAdjustEntries[32]; /* 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries */ -} ATOM_VOLTAGE_FORMULA; - -typedef struct _ATOM_VOLTAGE_CONTROL { - UCHAR ucVoltageControlId; /* Indicate it is controlled by I2C or GPIO or HW state machine */ - UCHAR ucVoltageControlI2cLine; - UCHAR ucVoltageControlAddress; - UCHAR ucVoltageControlOffset; - USHORT usGpioPin_AIndex; /* GPIO_PAD register index */ - UCHAR ucGpioPinBitShift[9]; /* at most 8 pin support 255 VIDs, termintate with 0xff */ - UCHAR ucReserved; -} ATOM_VOLTAGE_CONTROL; - -/* Define ucVoltageControlId */ +typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table +}ATOM_CONNECTOR_HPDPIN_LUT_RECORD; + +typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE +{ + ATOM_COMMON_RECORD_HEADER sheader; + ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID +}ATOM_CONNECTOR_AUXDDC_LUT_RECORD; + +typedef struct _ATOM_OBJECT_LINK_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + USHORT usObjectID; //could be connector, encorder or other object in object.h +}ATOM_OBJECT_LINK_RECORD; + +typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + USHORT usReserved; +}ATOM_CONNECTOR_REMOTE_CAP_RECORD; + +/****************************************************************************/ +// ASIC voltage data table +/****************************************************************************/ +typedef struct _ATOM_VOLTAGE_INFO_HEADER +{ + USHORT usVDDCBaseLevel; //In number of 50mv unit + USHORT usReserved; //For possible extension table offset + UCHAR ucNumOfVoltageEntries; + UCHAR ucBytesPerVoltageEntry; + UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit + UCHAR ucDefaultVoltageEntry; + UCHAR ucVoltageControlI2cLine; + UCHAR ucVoltageControlAddress; + UCHAR ucVoltageControlOffset; +}ATOM_VOLTAGE_INFO_HEADER; + +typedef struct _ATOM_VOLTAGE_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_INFO_HEADER viHeader; + UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry +}ATOM_VOLTAGE_INFO; + + +typedef struct _ATOM_VOLTAGE_FORMULA +{ + USHORT usVoltageBaseLevel; // In number of 1mv unit + USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit + UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage + UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv + UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep + UCHAR ucReserved; + UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries +}ATOM_VOLTAGE_FORMULA; + +typedef struct _VOLTAGE_LUT_ENTRY +{ + USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code + USHORT usVoltageValue; // The corresponding Voltage Value, in mV +}VOLTAGE_LUT_ENTRY; + +typedef struct _ATOM_VOLTAGE_FORMULA_V2 +{ + UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage + UCHAR ucReserved[3]; + VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries +}ATOM_VOLTAGE_FORMULA_V2; + +typedef struct _ATOM_VOLTAGE_CONTROL +{ + UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine + UCHAR ucVoltageControlI2cLine; + UCHAR ucVoltageControlAddress; + UCHAR ucVoltageControlOffset; + USHORT usGpioPin_AIndex; //GPIO_PAD register index + UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff + UCHAR ucReserved; +}ATOM_VOLTAGE_CONTROL; + +// Define ucVoltageControlId #define VOLTAGE_CONTROLLED_BY_HW 0x00 #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 -#define VOLTAGE_CONTROL_ID_LM64 0x01 /* I2C control, used for R5xx Core Voltage */ -#define VOLTAGE_CONTROL_ID_DAC 0x02 /* I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI */ -#define VOLTAGE_CONTROL_ID_VT116xM 0x03 /* I2C control, used for R6xx Core Voltage */ -#define VOLTAGE_CONTROL_ID_DS4402 0x04 - -typedef struct _ATOM_VOLTAGE_OBJECT { - UCHAR ucVoltageType; /* Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI */ - UCHAR ucSize; /* Size of Object */ - ATOM_VOLTAGE_CONTROL asControl; /* describ how to control */ - ATOM_VOLTAGE_FORMULA asFormula; /* Indicate How to convert real Voltage to VID */ -} ATOM_VOLTAGE_OBJECT; - -typedef struct _ATOM_VOLTAGE_OBJECT_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VOLTAGE_OBJECT asVoltageObj[3]; /* Info for Voltage control */ -} ATOM_VOLTAGE_OBJECT_INFO; - -typedef struct _ATOM_LEAKID_VOLTAGE { - UCHAR ucLeakageId; - UCHAR ucReserved; - USHORT usVoltage; -} ATOM_LEAKID_VOLTAGE; - -typedef struct _ATOM_ASIC_PROFILE_VOLTAGE { - UCHAR ucProfileId; - UCHAR ucReserved; - USHORT usSize; - USHORT usEfuseSpareStartAddr; - USHORT usFuseIndex[8]; /* from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, */ - ATOM_LEAKID_VOLTAGE asLeakVol[2]; /* Leakid and relatd voltage */ -} ATOM_ASIC_PROFILE_VOLTAGE; - -/* ucProfileId */ -#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 +#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage +#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI +#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage +#define VOLTAGE_CONTROL_ID_DS4402 0x04 + +typedef struct _ATOM_VOLTAGE_OBJECT +{ + UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI + UCHAR ucSize; //Size of Object + ATOM_VOLTAGE_CONTROL asControl; //describ how to control + ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID +}ATOM_VOLTAGE_OBJECT; + +typedef struct _ATOM_VOLTAGE_OBJECT_V2 +{ + UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI + UCHAR ucSize; //Size of Object + ATOM_VOLTAGE_CONTROL asControl; //describ how to control + ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID +}ATOM_VOLTAGE_OBJECT_V2; + +typedef struct _ATOM_VOLTAGE_OBJECT_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control +}ATOM_VOLTAGE_OBJECT_INFO; + +typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control +}ATOM_VOLTAGE_OBJECT_INFO_V2; + +typedef struct _ATOM_LEAKID_VOLTAGE +{ + UCHAR ucLeakageId; + UCHAR ucReserved; + USHORT usVoltage; +}ATOM_LEAKID_VOLTAGE; + +typedef struct _ATOM_ASIC_PROFILE_VOLTAGE +{ + UCHAR ucProfileId; + UCHAR ucReserved; + USHORT usSize; + USHORT usEfuseSpareStartAddr; + USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, + ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage +}ATOM_ASIC_PROFILE_VOLTAGE; + +//ucProfileId +#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 -typedef struct _ATOM_ASIC_PROFILING_INFO { - ATOM_COMMON_TABLE_HEADER asHeader; - ATOM_ASIC_PROFILE_VOLTAGE asVoltage; -} ATOM_ASIC_PROFILING_INFO; - -typedef struct _ATOM_POWER_SOURCE_OBJECT { - UCHAR ucPwrSrcId; /* Power source */ - UCHAR ucPwrSensorType; /* GPIO, I2C or none */ - UCHAR ucPwrSensId; /* if GPIO detect, it is GPIO id, if I2C detect, it is I2C id */ - UCHAR ucPwrSensSlaveAddr; /* Slave address if I2C detect */ - UCHAR ucPwrSensRegIndex; /* I2C register Index if I2C detect */ - UCHAR ucPwrSensRegBitMask; /* detect which bit is used if I2C detect */ - UCHAR ucPwrSensActiveState; /* high active or low active */ - UCHAR ucReserve[3]; /* reserve */ - USHORT usSensPwr; /* in unit of watt */ -} ATOM_POWER_SOURCE_OBJECT; - -typedef struct _ATOM_POWER_SOURCE_INFO { - ATOM_COMMON_TABLE_HEADER asHeader; - UCHAR asPwrbehave[16]; - ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; -} ATOM_POWER_SOURCE_INFO; - -/* Define ucPwrSrcId */ +typedef struct _ATOM_ASIC_PROFILING_INFO +{ + ATOM_COMMON_TABLE_HEADER asHeader; + ATOM_ASIC_PROFILE_VOLTAGE asVoltage; +}ATOM_ASIC_PROFILING_INFO; + +typedef struct _ATOM_POWER_SOURCE_OBJECT +{ + UCHAR ucPwrSrcId; // Power source + UCHAR ucPwrSensorType; // GPIO, I2C or none + UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id + UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect + UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect + UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect + UCHAR ucPwrSensActiveState; // high active or low active + UCHAR ucReserve[3]; // reserve + USHORT usSensPwr; // in unit of watt +}ATOM_POWER_SOURCE_OBJECT; + +typedef struct _ATOM_POWER_SOURCE_INFO +{ + ATOM_COMMON_TABLE_HEADER asHeader; + UCHAR asPwrbehave[16]; + ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; +}ATOM_POWER_SOURCE_INFO; + + +//Define ucPwrSrcId #define POWERSOURCE_PCIE_ID1 0x00 #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 -/* define ucPwrSensorId */ +//define ucPwrSensorId #define POWER_SENSOR_ALWAYS 0x00 #define POWER_SENSOR_GPIO 0x01 #define POWER_SENSOR_I2C 0x02 +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; + ULONG ulDentistVCOFreq; + ULONG ulBootUpUMAClock; + ULONG ulReserved1[8]; + ULONG ulBootUpReqDisplayVector; + ULONG ulOtherDisplayMisc; + ULONG ulGPUCapInfo; + ULONG ulReserved2[3]; + ULONG ulSystemConfig; + ULONG ulCPUCapInfo; + USHORT usMaxNBVoltage; + USHORT usMinNBVoltage; + USHORT usBootUpNBVoltage; + USHORT usExtDispConnInfoOffset; + UCHAR ucHtcTmpLmt; + UCHAR ucTjOffset; + UCHAR ucMemoryType; + UCHAR ucUMAChannelNumber; + ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; + ULONG ulCSR_M3_ARB_CNTL_UVD[10]; + ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; + ULONG ulReserved3[42]; + ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; +}ATOM_INTEGRATED_SYSTEM_INFO_V6; + +/********************************************************************************************************************** +// ATOM_INTEGRATED_SYSTEM_INFO_V6 Description +//ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. +//ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. +//ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. +//ulReserved1[8] Reserved by now, must be 0x0. +//ulBootUpReqDisplayVector VBIOS boot up display IDs +// ATOM_DEVICE_CRT1_SUPPORT 0x0001 +// ATOM_DEVICE_CRT2_SUPPORT 0x0010 +// ATOM_DEVICE_DFP1_SUPPORT 0x0008 +// ATOM_DEVICE_DFP6_SUPPORT 0x0040 +// ATOM_DEVICE_DFP2_SUPPORT 0x0080 +// ATOM_DEVICE_DFP3_SUPPORT 0x0200 +// ATOM_DEVICE_DFP4_SUPPORT 0x0400 +// ATOM_DEVICE_DFP5_SUPPORT 0x0800 +// ATOM_DEVICE_LCD1_SUPPORT 0x0002 +//ulOtherDisplayMisc Other display related flags, not defined yet. +//ulGPUCapInfo TBD +//ulReserved2[3] must be 0x0 for the reserved. +//ulSystemConfig TBD +//ulCPUCapInfo TBD +//usMaxNBVoltage High NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. +//usMinNBVoltage Low NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. +//usBootUpNBVoltage Boot up NB voltage in unit of mv. +//ucHtcTmpLmt Bit [22:16] of D24F3x64 Thermal Control (HTC) Register. +//ucTjOffset Bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed. +//ucMemoryType [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. +//ucUMAChannelNumber System memory channel numbers. +//usExtDispConnectionInfoOffset ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO offset relative to beginning of this table. +//ulCSR_M3_ARB_CNTL_DEFAULT[10] Arrays with values for CSR M3 arbiter for default +//ulCSR_M3_ARB_CNTL_UVD[10] Arrays with values for CSR M3 arbiter for UVD playback. +//ulCSR_M3_ARB_CNTL_FS3D[10] Arrays with values for CSR M3 arbiter for Full Screen 3D applications. +**********************************************************************************************************************/ + /**************************************************************************/ -/* This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design */ -/* Memory SS Info Table */ -/* Define Memory Clock SS chip ID */ +// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design +//Memory SS Info Table +//Define Memory Clock SS chip ID #define ICS91719 1 #define ICS91720 2 -/* Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol */ -typedef struct _ATOM_I2C_DATA_RECORD { - UCHAR ucNunberOfBytes; /* Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" */ - UCHAR ucI2CData[1]; /* I2C data in bytes, should be less than 16 bytes usually */ -} ATOM_I2C_DATA_RECORD; - -/* Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information */ -typedef struct _ATOM_I2C_DEVICE_SETUP_INFO { - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; /* I2C line and HW/SW assisted cap. */ - UCHAR ucSSChipID; /* SS chip being used */ - UCHAR ucSSChipSlaveAddr; /* Slave Address to set up this SS chip */ - UCHAR ucNumOfI2CDataRecords; /* number of data block */ - ATOM_I2C_DATA_RECORD asI2CData[1]; -} ATOM_I2C_DEVICE_SETUP_INFO; - -/* ========================================================================================== */ -typedef struct _ATOM_ASIC_MVDD_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; -} ATOM_ASIC_MVDD_INFO; - -/* ========================================================================================== */ +//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol +typedef struct _ATOM_I2C_DATA_RECORD +{ + UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" + UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually +}ATOM_I2C_DATA_RECORD; + + +//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information +typedef struct _ATOM_I2C_DEVICE_SETUP_INFO +{ + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. + UCHAR ucSSChipID; //SS chip being used + UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip + UCHAR ucNumOfI2CDataRecords; //number of data block + ATOM_I2C_DATA_RECORD asI2CData[1]; +}ATOM_I2C_DEVICE_SETUP_INFO; + +//========================================================================================== +typedef struct _ATOM_ASIC_MVDD_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; +}ATOM_ASIC_MVDD_INFO; + +//========================================================================================== #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO -/* ========================================================================================== */ +//========================================================================================== /**************************************************************************/ -typedef struct _ATOM_ASIC_SS_ASSIGNMENT { - ULONG ulTargetClockRange; /* Clock Out frequence (VCO ), in unit of 10Khz */ - USHORT usSpreadSpectrumPercentage; /* in unit of 0.01% */ - USHORT usSpreadRateInKhz; /* in unit of kHz, modulation freq */ - UCHAR ucClockIndication; /* Indicate which clock source needs SS */ - UCHAR ucSpreadSpectrumMode; /* Bit1=0 Down Spread,=1 Center Spread. */ - UCHAR ucReserved[2]; -} ATOM_ASIC_SS_ASSIGNMENT; - -/* Define ucSpreadSpectrumType */ +typedef struct _ATOM_ASIC_SS_ASSIGNMENT +{ + ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz + USHORT usSpreadSpectrumPercentage; //in unit of 0.01% + USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq + UCHAR ucClockIndication; //Indicate which clock source needs SS + UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. + UCHAR ucReserved[2]; +}ATOM_ASIC_SS_ASSIGNMENT; + +//Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type. +//SS is not required or enabled if a match is not found. #define ASIC_INTERNAL_MEMORY_SS 1 #define ASIC_INTERNAL_ENGINE_SS 2 -#define ASIC_INTERNAL_UVD_SS 3 +#define ASIC_INTERNAL_UVD_SS 3 +#define ASIC_INTERNAL_SS_ON_TMDS 4 +#define ASIC_INTERNAL_SS_ON_HDMI 5 +#define ASIC_INTERNAL_SS_ON_LVDS 6 +#define ASIC_INTERNAL_SS_ON_DP 7 +#define ASIC_INTERNAL_SS_ON_DCPLL 8 + +typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 +{ + ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz + //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) + USHORT usSpreadSpectrumPercentage; //in unit of 0.01% + USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq + UCHAR ucClockIndication; //Indicate which clock source needs SS + UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS + UCHAR ucReserved[2]; +}ATOM_ASIC_SS_ASSIGNMENT_V2; + +//ucSpreadSpectrumMode +//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 +//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 +//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 +//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 +//#define ATOM_INTERNAL_SS_MASK 0x00000000 +//#define ATOM_EXTERNAL_SS_MASK 0x00000002 + +typedef struct _ATOM_ASIC_INTERNAL_SS_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; +}ATOM_ASIC_INTERNAL_SS_INFO; + +typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. +}ATOM_ASIC_INTERNAL_SS_INFO_V2; + +typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 +{ + ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz + //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) + USHORT usSpreadSpectrumPercentage; //in unit of 0.01% + USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq + UCHAR ucClockIndication; //Indicate which clock source needs SS + UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS + UCHAR ucReserved[2]; +}ATOM_ASIC_SS_ASSIGNMENT_V3; + +typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. +}ATOM_ASIC_INTERNAL_SS_INFO_V3; -typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; -} ATOM_ASIC_INTERNAL_SS_INFO; -/* ==============================Scratch Pad Definition Portion=============================== */ +//==============================Scratch Pad Definition Portion=============================== #define ATOM_DEVICE_CONNECT_INFO_DEF 0 #define ATOM_ROM_LOCATION_DEF 1 #define ATOM_TV_STANDARD_DEF 2 @@ -2995,7 +3852,8 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_I2C_CHANNEL_STATUS_DEF 8 #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 -/* BIOS_0_SCRATCH Definition */ + +// BIOS_0_SCRATCH Definition #define ATOM_S0_CRT1_MONO 0x00000001L #define ATOM_S0_CRT1_COLOR 0x00000002L #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) @@ -3008,6 +3866,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S0_CV_DIN_A 0x00000020L #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) + #define ATOM_S0_CRT2_MONO 0x00000100L #define ATOM_S0_CRT2_COLOR 0x00000200L #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) @@ -3025,28 +3884,27 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S0_DFP2 0x00020000L #define ATOM_S0_LCD1 0x00040000L #define ATOM_S0_LCD2 0x00080000L -#define ATOM_S0_TV2 0x00100000L -#define ATOM_S0_DFP3 0x00200000L -#define ATOM_S0_DFP4 0x00400000L -#define ATOM_S0_DFP5 0x00800000L +#define ATOM_S0_DFP6 0x00100000L +#define ATOM_S0_DFP3 0x00200000L +#define ATOM_S0_DFP4 0x00400000L +#define ATOM_S0_DFP5 0x00800000L -#define ATOM_S0_DFP_MASK \ - (ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5) +#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 -#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L /* If set, indicates we are running a PCIE asic with */ - /* the FAD/HDP reg access bug. Bit is read by DAL */ +#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with + // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L #define ATOM_S0_THERMAL_STATE_SHIFT 26 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L -#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 +#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 -/* Byte aligned defintion for BIOS usage */ +//Byte aligned defintion for BIOS usage #define ATOM_S0_CRT1_MONOb0 0x01 #define ATOM_S0_CRT1_COLORb0 0x02 #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) @@ -3076,8 +3934,11 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S0_DFP2b2 0x02 #define ATOM_S0_LCD1b2 0x04 #define ATOM_S0_LCD2b2 0x08 -#define ATOM_S0_TV2b2 0x10 -#define ATOM_S0_DFP3b2 0x20 +#define ATOM_S0_DFP6b2 0x10 +#define ATOM_S0_DFP3b2 0x20 +#define ATOM_S0_DFP4b2 0x40 +#define ATOM_S0_DFP5b2 0x80 + #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C #define ATOM_S0_THERMAL_STATE_SHIFTb3 2 @@ -3085,43 +3946,20 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 #define ATOM_S0_LCD1_SHIFT 18 -/* BIOS_1_SCRATCH Definition */ +// BIOS_1_SCRATCH Definition #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L -/* BIOS_2_SCRATCH Definition */ +// BIOS_2_SCRATCH Definition #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 -#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L -#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L -#define ATOM_S2_TV1_DPMS_STATE 0x00040000L -#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L -#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L -#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L -#define ATOM_S2_TV2_DPMS_STATE 0x00400000L -#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L -#define ATOM_S2_CV_DPMS_STATE 0x01000000L -#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L -#define ATOM_S2_DFP4_DPMS_STATE 0x04000000L -#define ATOM_S2_DFP5_DPMS_STATE 0x08000000L - -#define ATOM_S2_DFP_DPM_STATE \ - (ATOM_S2_DFP1_DPMS_STATE | ATOM_S2_DFP2_DPMS_STATE | \ - ATOM_S2_DFP3_DPMS_STATE | ATOM_S2_DFP4_DPMS_STATE | \ - ATOM_S2_DFP5_DPMS_STATE) - -#define ATOM_S2_DEVICE_DPMS_STATE \ - (ATOM_S2_CRT1_DPMS_STATE + ATOM_S2_LCD1_DPMS_STATE + \ - ATOM_S2_TV1_DPMS_STATE + ATOM_S2_DFP_DPMS_STATE + \ - ATOM_S2_CRT2_DPMS_STATE + ATOM_S2_LCD2_DPMS_STATE + \ - ATOM_S2_TV2_DPMS_STATE + ATOM_S2_CV_DPMS_STATE) - #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L +#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 @@ -3131,21 +3969,11 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L -/* Byte aligned defintion for BIOS usage */ + +//Byte aligned defintion for BIOS usage #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF -#define ATOM_S2_CRT1_DPMS_STATEb2 0x01 -#define ATOM_S2_LCD1_DPMS_STATEb2 0x02 -#define ATOM_S2_TV1_DPMS_STATEb2 0x04 -#define ATOM_S2_DFP1_DPMS_STATEb2 0x08 -#define ATOM_S2_CRT2_DPMS_STATEb2 0x10 -#define ATOM_S2_LCD2_DPMS_STATEb2 0x20 -#define ATOM_S2_TV2_DPMS_STATEb2 0x40 -#define ATOM_S2_DFP2_DPMS_STATEb2 0x80 -#define ATOM_S2_CV_DPMS_STATEb3 0x01 -#define ATOM_S2_DFP3_DPMS_STATEb3 0x02 -#define ATOM_S2_DFP4_DPMS_STATEb3 0x04 -#define ATOM_S2_DFP5_DPMS_STATEb3 0x08 +#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 #define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C @@ -3153,21 +3981,22 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 -/* BIOS_3_SCRATCH Definition */ + +// BIOS_3_SCRATCH Definition #define ATOM_S3_CRT1_ACTIVE 0x00000001L #define ATOM_S3_LCD1_ACTIVE 0x00000002L #define ATOM_S3_TV1_ACTIVE 0x00000004L #define ATOM_S3_DFP1_ACTIVE 0x00000008L #define ATOM_S3_CRT2_ACTIVE 0x00000010L #define ATOM_S3_LCD2_ACTIVE 0x00000020L -#define ATOM_S3_TV2_ACTIVE 0x00000040L +#define ATOM_S3_DFP6_ACTIVE 0x00000040L #define ATOM_S3_DFP2_ACTIVE 0x00000080L #define ATOM_S3_CV_ACTIVE 0x00000100L #define ATOM_S3_DFP3_ACTIVE 0x00000200L #define ATOM_S3_DFP4_ACTIVE 0x00000400L #define ATOM_S3_DFP5_ACTIVE 0x00000800L -#define ATOM_S3_DEVICE_ACTIVE_MASK 0x000003FFL +#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L @@ -3178,7 +4007,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L -#define ATOM_S3_TV2_CRTC_ACTIVE 0x00400000L +#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L @@ -3187,17 +4016,18 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L +//Below two definitions are not supported in pplib, but in the old powerplay in DAL #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L -/* Byte aligned defintion for BIOS usage */ +//Byte aligned defintion for BIOS usage #define ATOM_S3_CRT1_ACTIVEb0 0x01 #define ATOM_S3_LCD1_ACTIVEb0 0x02 #define ATOM_S3_TV1_ACTIVEb0 0x04 #define ATOM_S3_DFP1_ACTIVEb0 0x08 #define ATOM_S3_CRT2_ACTIVEb0 0x10 #define ATOM_S3_LCD2_ACTIVEb0 0x20 -#define ATOM_S3_TV2_ACTIVEb0 0x40 +#define ATOM_S3_DFP6_ACTIVEb0 0x40 #define ATOM_S3_DFP2_ACTIVEb0 0x80 #define ATOM_S3_CV_ACTIVEb1 0x01 #define ATOM_S3_DFP3_ACTIVEb1 0x02 @@ -3212,7 +4042,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 -#define ATOM_S3_TV2_CRTC_ACTIVEb2 0x40 +#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 @@ -3221,35 +4051,31 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF -#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 -#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 -#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 - -/* BIOS_4_SCRATCH Definition */ +// BIOS_4_SCRATCH Definition #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L #define ATOM_S4_LCD1_REFRESH_SHIFT 8 -/* Byte aligned defintion for BIOS usage */ +//Byte aligned defintion for BIOS usage #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 -/* BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! */ +// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! #define ATOM_S5_DOS_REQ_CRT1b0 0x01 #define ATOM_S5_DOS_REQ_LCD1b0 0x02 #define ATOM_S5_DOS_REQ_TV1b0 0x04 #define ATOM_S5_DOS_REQ_DFP1b0 0x08 #define ATOM_S5_DOS_REQ_CRT2b0 0x10 #define ATOM_S5_DOS_REQ_LCD2b0 0x20 -#define ATOM_S5_DOS_REQ_TV2b0 0x40 +#define ATOM_S5_DOS_REQ_DFP6b0 0x40 #define ATOM_S5_DOS_REQ_DFP2b0 0x80 #define ATOM_S5_DOS_REQ_CVb1 0x01 #define ATOM_S5_DOS_REQ_DFP3b1 0x02 #define ATOM_S5_DOS_REQ_DFP4b1 0x04 #define ATOM_S5_DOS_REQ_DFP5b1 0x08 -#define ATOM_S5_DOS_REQ_DEVICEw0 0x03FF +#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF #define ATOM_S5_DOS_REQ_CRT1 0x0001 #define ATOM_S5_DOS_REQ_LCD1 0x0002 @@ -3257,22 +4083,21 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S5_DOS_REQ_DFP1 0x0008 #define ATOM_S5_DOS_REQ_CRT2 0x0010 #define ATOM_S5_DOS_REQ_LCD2 0x0020 -#define ATOM_S5_DOS_REQ_TV2 0x0040 +#define ATOM_S5_DOS_REQ_DFP6 0x0040 #define ATOM_S5_DOS_REQ_DFP2 0x0080 #define ATOM_S5_DOS_REQ_CV 0x0100 -#define ATOM_S5_DOS_REQ_DFP3 0x0200 -#define ATOM_S5_DOS_REQ_DFP4 0x0400 -#define ATOM_S5_DOS_REQ_DFP5 0x0800 +#define ATOM_S5_DOS_REQ_DFP3 0x0200 +#define ATOM_S5_DOS_REQ_DFP4 0x0400 +#define ATOM_S5_DOS_REQ_DFP5 0x0800 #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 -#define ATOM_S5_DOS_FORCE_DEVICEw1 \ - (ATOM_S5_DOS_FORCE_CRT1b2 + ATOM_S5_DOS_FORCE_TV1b2 + \ - ATOM_S5_DOS_FORCE_CRT2b2 + (ATOM_S5_DOS_FORCE_CVb3 << 8)) +#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ + (ATOM_S5_DOS_FORCE_CVb3<<8)) -/* BIOS_6_SCRATCH Definition */ +// BIOS_6_SCRATCH Definition #define ATOM_S6_DEVICE_CHANGE 0x00000001L #define ATOM_S6_SCALER_CHANGE 0x00000002L #define ATOM_S6_LID_CHANGE 0x00000004L @@ -3285,11 +4110,11 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L -#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L /* Normal expansion Request bit for LCD */ -#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L /* Aspect ratio expansion Request bit for LCD */ +#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD +#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD -#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L /* This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion */ -#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L /* This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion */ +#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion +#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion #define ATOM_S6_ACC_REQ_CRT1 0x00010000L #define ATOM_S6_ACC_REQ_LCD1 0x00020000L @@ -3297,7 +4122,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S6_ACC_REQ_DFP1 0x00080000L #define ATOM_S6_ACC_REQ_CRT2 0x00100000L #define ATOM_S6_ACC_REQ_LCD2 0x00200000L -#define ATOM_S6_ACC_REQ_TV2 0x00400000L +#define ATOM_S6_ACC_REQ_DFP6 0x00400000L #define ATOM_S6_ACC_REQ_DFP2 0x00800000L #define ATOM_S6_ACC_REQ_CV 0x01000000L #define ATOM_S6_ACC_REQ_DFP3 0x02000000L @@ -3310,7 +4135,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L -/* Byte aligned defintion for BIOS usage */ +//Byte aligned defintion for BIOS usage #define ATOM_S6_DEVICE_CHANGEb0 0x01 #define ATOM_S6_SCALER_CHANGEb0 0x02 #define ATOM_S6_LID_CHANGEb0 0x04 @@ -3320,11 +4145,11 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S6_LID_STATEb0 0x40 #define ATOM_S6_DOCK_STATEb0 0x80 #define ATOM_S6_CRITICAL_STATEb1 0x01 -#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 +#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 -#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 -#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 +#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 +#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 #define ATOM_S6_ACC_REQ_CRT1b2 0x01 #define ATOM_S6_ACC_REQ_LCD1b2 0x02 @@ -3332,12 +4157,12 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S6_ACC_REQ_DFP1b2 0x08 #define ATOM_S6_ACC_REQ_CRT2b2 0x10 #define ATOM_S6_ACC_REQ_LCD2b2 0x20 -#define ATOM_S6_ACC_REQ_TV2b2 0x40 +#define ATOM_S6_ACC_REQ_DFP6b2 0x40 #define ATOM_S6_ACC_REQ_DFP2b2 0x80 #define ATOM_S6_ACC_REQ_CVb3 0x01 -#define ATOM_S6_ACC_REQ_DFP3b3 0x02 -#define ATOM_S6_ACC_REQ_DFP4b3 0x04 -#define ATOM_S6_ACC_REQ_DFP5b3 0x08 +#define ATOM_S6_ACC_REQ_DFP3b3 0x02 +#define ATOM_S6_ACC_REQ_DFP4b3 0x04 +#define ATOM_S6_ACC_REQ_DFP5b3 0x08 #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 @@ -3366,7 +4191,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 -/* BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! */ +// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! #define ATOM_S7_DOS_MODE_TYPEb0 0x03 #define ATOM_S7_DOS_MODE_VGAb0 0x00 #define ATOM_S7_DOS_MODE_VESAb0 0x01 @@ -3378,220 +4203,194 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 -/* BIOS_8_SCRATCH Definition */ +// BIOS_8_SCRATCH Definition #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF -#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 +#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 -/* BIOS_9_SCRATCH Definition */ -#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK +// BIOS_9_SCRATCH Definition +#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF #endif -#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK +#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 #endif -#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT +#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 #endif -#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT +#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 #endif + #define ATOM_FLAG_SET 0x20 #define ATOM_FLAG_CLEAR 0 -#define CLEAR_ATOM_S6_ACC_MODE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) -#define SET_ATOM_S6_DEVICE_CHANGE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_SCALER_CHANGE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_LID_CHANGE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) - -#define SET_ATOM_S6_LID_STATE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) |\ - ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S6_LID_STATE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) - -#define SET_ATOM_S6_DOCK_CHANGE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8)| \ - ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_DOCK_STATE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S6_DOCK_STATE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) - -#define SET_ATOM_S6_THERMAL_STATE_CHANGE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) - -#define SET_ATOM_S6_CRITICAL_STATE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S6_CRITICAL_STATE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) - -#define SET_ATOM_S6_REQ_SCALER \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S6_REQ_SCALER \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) - -#define SET_ATOM_S6_REQ_SCALER_ARATIO \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) -#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) - -#define SET_ATOM_S6_I2C_STATE_CHANGE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) - -#define SET_ATOM_S6_DISPLAY_STATE_CHANGE \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) - -#define SET_ATOM_S6_DEVICE_RECONFIG \ - ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ - ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S0_LCD1 \ - ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 ) | \ - ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) -#define SET_ATOM_S7_DOS_8BIT_DAC_EN \ - ((ATOM_DOS_MODE_INFO_DEF << 8) | \ - ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) -#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN \ - ((ATOM_DOS_MODE_INFO_DEF << 8) | \ - ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) +#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) +#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) -/****************************************************************************/ -/* Portion II: Definitinos only used in Driver */ +#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) + +#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) + +#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) + +#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) + +#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) + +#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) +#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) + +#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) + +#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) + +#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) +#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) +#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) + +/****************************************************************************/ +//Portion II: Definitinos only used in Driver /****************************************************************************/ -/* Macros used by driver */ +// Macros used by driver +#ifdef __cplusplus +#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast(&(static_cast(0))->FieldName)-static_cast(0))/sizeof(USHORT)) -#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char *)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES *)0)->FieldName)-(char *)0)/sizeof(USHORT)) +#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) +#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) +#else // not __cplusplus +#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) +#endif // __cplusplus #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION -/****************************************************************************/ -/* Portion III: Definitinos only used in VBIOS */ +/****************************************************************************/ +//Portion III: Definitinos only used in VBIOS /****************************************************************************/ #define ATOM_DAC_SRC 0x80 #define ATOM_SRC_DAC1 0 #define ATOM_SRC_DAC2 0x80 -#ifdef UEFI_BUILD -#define USHORT UTEMP -#endif - -typedef struct _MEMORY_PLLINIT_PARAMETERS { - ULONG ulTargetMemoryClock; /* In 10Khz unit */ - UCHAR ucAction; /* not define yet */ - UCHAR ucFbDiv_Hi; /* Fbdiv Hi byte */ - UCHAR ucFbDiv; /* FB value */ - UCHAR ucPostDiv; /* Post div */ -} MEMORY_PLLINIT_PARAMETERS; +typedef struct _MEMORY_PLLINIT_PARAMETERS +{ + ULONG ulTargetMemoryClock; //In 10Khz unit + UCHAR ucAction; //not define yet + UCHAR ucFbDiv_Hi; //Fbdiv Hi byte + UCHAR ucFbDiv; //FB value + UCHAR ucPostDiv; //Post div +}MEMORY_PLLINIT_PARAMETERS; #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS -#define GPIO_PIN_WRITE 0x01 + +#define GPIO_PIN_WRITE 0x01 #define GPIO_PIN_READ 0x00 -typedef struct _GPIO_PIN_CONTROL_PARAMETERS { - UCHAR ucGPIO_ID; /* return value, read from GPIO pins */ - UCHAR ucGPIOBitShift; /* define which bit in uGPIOBitVal need to be update */ - UCHAR ucGPIOBitVal; /* Set/Reset corresponding bit defined in ucGPIOBitMask */ - UCHAR ucAction; /* =GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write */ -} GPIO_PIN_CONTROL_PARAMETERS; - -typedef struct _ENABLE_SCALER_PARAMETERS { - UCHAR ucScaler; /* ATOM_SCALER1, ATOM_SCALER2 */ - UCHAR ucEnable; /* ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION */ - UCHAR ucTVStandard; /* */ - UCHAR ucPadding[1]; -} ENABLE_SCALER_PARAMETERS; -#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS - -/* ucEnable: */ +typedef struct _GPIO_PIN_CONTROL_PARAMETERS +{ + UCHAR ucGPIO_ID; //return value, read from GPIO pins + UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update + UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask + UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write +}GPIO_PIN_CONTROL_PARAMETERS; + +typedef struct _ENABLE_SCALER_PARAMETERS +{ + UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 + UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION + UCHAR ucTVStandard; // + UCHAR ucPadding[1]; +}ENABLE_SCALER_PARAMETERS; +#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS + +//ucEnable: #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 #define SCALER_ENABLE_2TAP_ALPHA_MODE 2 #define SCALER_ENABLE_MULTITAP_MODE 3 -typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS { - ULONG usHWIconHorzVertPosn; /* Hardware Icon Vertical position */ - UCHAR ucHWIconVertOffset; /* Hardware Icon Vertical offset */ - UCHAR ucHWIconHorzOffset; /* Hardware Icon Horizontal offset */ - UCHAR ucSelection; /* ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 */ - UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ -} ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; - -typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION { - ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; - ENABLE_CRTC_PARAMETERS sReserved; -} ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; - -typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS { - USHORT usHight; /* Image Hight */ - USHORT usWidth; /* Image Width */ - UCHAR ucSurface; /* Surface 1 or 2 */ - UCHAR ucPadding[3]; -} ENABLE_GRAPH_SURFACE_PARAMETERS; - -typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 { - USHORT usHight; /* Image Hight */ - USHORT usWidth; /* Image Width */ - UCHAR ucSurface; /* Surface 1 or 2 */ - UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ - UCHAR ucPadding[2]; -} ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; - -typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION { - ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; - ENABLE_YUV_PS_ALLOCATION sReserved; /* Don't set this one */ -} ENABLE_GRAPH_SURFACE_PS_ALLOCATION; - -typedef struct _MEMORY_CLEAN_UP_PARAMETERS { - USHORT usMemoryStart; /* in 8Kb boundry, offset from memory base address */ - USHORT usMemorySize; /* 8Kb blocks aligned */ -} MEMORY_CLEAN_UP_PARAMETERS; +typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS +{ + ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position + UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset + UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset + UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE +}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; + +typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION +{ + ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; + ENABLE_CRTC_PARAMETERS sReserved; +}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; + +typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS +{ + USHORT usHight; // Image Hight + USHORT usWidth; // Image Width + UCHAR ucSurface; // Surface 1 or 2 + UCHAR ucPadding[3]; +}ENABLE_GRAPH_SURFACE_PARAMETERS; + +typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 +{ + USHORT usHight; // Image Hight + USHORT usWidth; // Image Width + UCHAR ucSurface; // Surface 1 or 2 + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[2]; +}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; + +typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 +{ + USHORT usHight; // Image Hight + USHORT usWidth; // Image Width + UCHAR ucSurface; // Surface 1 or 2 + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. +}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; + +typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION +{ + ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; + ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one +}ENABLE_GRAPH_SURFACE_PS_ALLOCATION; + +typedef struct _MEMORY_CLEAN_UP_PARAMETERS +{ + USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address + USHORT usMemorySize; //8Kb blocks aligned +}MEMORY_CLEAN_UP_PARAMETERS; #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS -typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS { - USHORT usX_Size; /* When use as input parameter, usX_Size indicates which CRTC */ - USHORT usY_Size; -} GET_DISPLAY_SURFACE_SIZE_PARAMETERS; +typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS +{ + USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC + USHORT usY_Size; +}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; -typedef struct _INDIRECT_IO_ACCESS { - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR IOAccessSequence[256]; +typedef struct _INDIRECT_IO_ACCESS +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR IOAccessSequence[256]; } INDIRECT_IO_ACCESS; #define INDIRECT_READ 0x00 @@ -3615,93 +4414,108 @@ typedef struct _INDIRECT_IO_ACCESS { #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE -typedef struct _ATOM_OEM_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; -} ATOM_OEM_INFO; - -typedef struct _ATOM_TV_MODE { - UCHAR ucVMode_Num; /* Video mode number */ - UCHAR ucTV_Mode_Num; /* Internal TV mode number */ -} ATOM_TV_MODE; - -typedef struct _ATOM_BIOS_INT_TVSTD_MODE { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usTV_Mode_LUT_Offset; /* Pointer to standard to internal number conversion table */ - USHORT usTV_FIFO_Offset; /* Pointer to FIFO entry table */ - USHORT usNTSC_Tbl_Offset; /* Pointer to SDTV_Mode_NTSC table */ - USHORT usPAL_Tbl_Offset; /* Pointer to SDTV_Mode_PAL table */ - USHORT usCV_Tbl_Offset; /* Pointer to SDTV_Mode_PAL table */ -} ATOM_BIOS_INT_TVSTD_MODE; - -typedef struct _ATOM_TV_MODE_SCALER_PTR { - USHORT ucFilter0_Offset; /* Pointer to filter format 0 coefficients */ - USHORT usFilter1_Offset; /* Pointer to filter format 0 coefficients */ - UCHAR ucTV_Mode_Num; -} ATOM_TV_MODE_SCALER_PTR; - -typedef struct _ATOM_STANDARD_VESA_TIMING { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_DTD_FORMAT aModeTimings[16]; /* 16 is not the real array number, just for initial allocation */ -} ATOM_STANDARD_VESA_TIMING; - -typedef struct _ATOM_STD_FORMAT { - USHORT usSTD_HDisp; - USHORT usSTD_VDisp; - USHORT usSTD_RefreshRate; - USHORT usReserved; -} ATOM_STD_FORMAT; - -typedef struct _ATOM_VESA_TO_EXTENDED_MODE { - USHORT usVESA_ModeNumber; - USHORT usExtendedModeNumber; -} ATOM_VESA_TO_EXTENDED_MODE; - -typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; -} ATOM_VESA_TO_INTENAL_MODE_LUT; +typedef struct _ATOM_OEM_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; +}ATOM_OEM_INFO; + +typedef struct _ATOM_TV_MODE +{ + UCHAR ucVMode_Num; //Video mode number + UCHAR ucTV_Mode_Num; //Internal TV mode number +}ATOM_TV_MODE; + +typedef struct _ATOM_BIOS_INT_TVSTD_MODE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table + USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table + USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table + USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table + USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table +}ATOM_BIOS_INT_TVSTD_MODE; + + +typedef struct _ATOM_TV_MODE_SCALER_PTR +{ + USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients + USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients + UCHAR ucTV_Mode_Num; +}ATOM_TV_MODE_SCALER_PTR; + +typedef struct _ATOM_STANDARD_VESA_TIMING +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation +}ATOM_STANDARD_VESA_TIMING; + + +typedef struct _ATOM_STD_FORMAT +{ + USHORT usSTD_HDisp; + USHORT usSTD_VDisp; + USHORT usSTD_RefreshRate; + USHORT usReserved; +}ATOM_STD_FORMAT; + +typedef struct _ATOM_VESA_TO_EXTENDED_MODE +{ + USHORT usVESA_ModeNumber; + USHORT usExtendedModeNumber; +}ATOM_VESA_TO_EXTENDED_MODE; + +typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; +}ATOM_VESA_TO_INTENAL_MODE_LUT; /*************** ATOM Memory Related Data Structure ***********************/ -typedef struct _ATOM_MEMORY_VENDOR_BLOCK { - UCHAR ucMemoryType; - UCHAR ucMemoryVendor; - UCHAR ucAdjMCId; - UCHAR ucDynClkId; - ULONG ulDllResetClkRange; -} ATOM_MEMORY_VENDOR_BLOCK; - -typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG { +typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ + UCHAR ucMemoryType; + UCHAR ucMemoryVendor; + UCHAR ucAdjMCId; + UCHAR ucDynClkId; + ULONG ulDllResetClkRange; +}ATOM_MEMORY_VENDOR_BLOCK; + + +typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ #if ATOM_BIG_ENDIAN - ULONG ucMemBlkId:8; - ULONG ulMemClockRange:24; + ULONG ucMemBlkId:8; + ULONG ulMemClockRange:24; #else - ULONG ulMemClockRange:24; - ULONG ucMemBlkId:8; + ULONG ulMemClockRange:24; + ULONG ucMemBlkId:8; #endif -} ATOM_MEMORY_SETTING_ID_CONFIG; - -typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS { - ATOM_MEMORY_SETTING_ID_CONFIG slAccess; - ULONG ulAccess; -} ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; - -typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK { - ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; - ULONG aulMemData[1]; -} ATOM_MEMORY_SETTING_DATA_BLOCK; - -typedef struct _ATOM_INIT_REG_INDEX_FORMAT { - USHORT usRegIndex; /* MC register index */ - UCHAR ucPreRegDataLength; /* offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf */ -} ATOM_INIT_REG_INDEX_FORMAT; - -typedef struct _ATOM_INIT_REG_BLOCK { - USHORT usRegIndexTblSize; /* size of asRegIndexBuf */ - USHORT usRegDataBlkSize; /* size of ATOM_MEMORY_SETTING_DATA_BLOCK */ - ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; - ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; -} ATOM_INIT_REG_BLOCK; +}ATOM_MEMORY_SETTING_ID_CONFIG; + +typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS +{ + ATOM_MEMORY_SETTING_ID_CONFIG slAccess; + ULONG ulAccess; +}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; + + +typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ + ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; + ULONG aulMemData[1]; +}ATOM_MEMORY_SETTING_DATA_BLOCK; + + +typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ + USHORT usRegIndex; // MC register index + UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf +}ATOM_INIT_REG_INDEX_FORMAT; + + +typedef struct _ATOM_INIT_REG_BLOCK{ + USHORT usRegIndexTblSize; //size of asRegIndexBuf + USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK + ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; + ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; +}ATOM_INIT_REG_BLOCK; #define END_OF_REG_INDEX_BLOCK 0x0ffff #define END_OF_REG_DATA_BLOCK 0x00000000 @@ -3716,16 +4530,19 @@ typedef struct _ATOM_INIT_REG_BLOCK { #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) -typedef struct _ATOM_MC_INIT_PARAM_TABLE { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usAdjustARB_SEQDataOffset; - USHORT usMCInitMemTypeTblOffset; - USHORT usMCInitCommonTblOffset; - USHORT usMCInitPowerDownTblOffset; - ULONG ulARB_SEQDataBuf[32]; - ATOM_INIT_REG_BLOCK asMCInitMemType; - ATOM_INIT_REG_BLOCK asMCInitCommon; -} ATOM_MC_INIT_PARAM_TABLE; + +typedef struct _ATOM_MC_INIT_PARAM_TABLE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usAdjustARB_SEQDataOffset; + USHORT usMCInitMemTypeTblOffset; + USHORT usMCInitCommonTblOffset; + USHORT usMCInitPowerDownTblOffset; + ULONG ulARB_SEQDataBuf[32]; + ATOM_INIT_REG_BLOCK asMCInitMemType; + ATOM_INIT_REG_BLOCK asMCInitCommon; +}ATOM_MC_INIT_PARAM_TABLE; + #define _4Mx16 0x2 #define _4Mx32 0x3 @@ -3751,221 +4568,272 @@ typedef struct _ATOM_MC_INIT_PARAM_TABLE { #define QIMONDA INFINEON #define PROMOS MOSEL +#define KRETON INFINEON -/* ///////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// */ +/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// #define UCODE_ROM_START_ADDRESS 0x1c000 -#define UCODE_SIGNATURE 0x4375434d /* 'MCuC' - MC uCode */ - -/* uCode block header for reference */ - -typedef struct _MCuCodeHeader { - ULONG ulSignature; - UCHAR ucRevision; - UCHAR ucChecksum; - UCHAR ucReserved1; - UCHAR ucReserved2; - USHORT usParametersLength; - USHORT usUCodeLength; - USHORT usReserved1; - USHORT usReserved2; +#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode + +//uCode block header for reference + +typedef struct _MCuCodeHeader +{ + ULONG ulSignature; + UCHAR ucRevision; + UCHAR ucChecksum; + UCHAR ucReserved1; + UCHAR ucReserved2; + USHORT usParametersLength; + USHORT usUCodeLength; + USHORT usReserved1; + USHORT usReserved2; } MCuCodeHeader; -/* //////////////////////////////////////////////////////////////////////////////// */ +////////////////////////////////////////////////////////////////////////////////// #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF -typedef struct _ATOM_VRAM_MODULE_V1 { - ULONG ulReserved; - USHORT usEMRSValue; - USHORT usMRSValue; - USHORT usReserved; - UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ - UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; */ - UCHAR ucMemoryVenderID; /* Predefined,never change across designs or memory type/vender */ - UCHAR ucMemoryDeviceCfg; /* [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... */ - UCHAR ucRow; /* Number of Row,in power of 2; */ - UCHAR ucColumn; /* Number of Column,in power of 2; */ - UCHAR ucBank; /* Nunber of Bank; */ - UCHAR ucRank; /* Number of Rank, in power of 2 */ - UCHAR ucChannelNum; /* Number of channel; */ - UCHAR ucChannelConfig; /* [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 */ - UCHAR ucDefaultMVDDQ_ID; /* Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; */ - UCHAR ucDefaultMVDDC_ID; /* Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; */ - UCHAR ucReserved[2]; -} ATOM_VRAM_MODULE_V1; - -typedef struct _ATOM_VRAM_MODULE_V2 { - ULONG ulReserved; - ULONG ulFlags; /* To enable/disable functionalities based on memory type */ - ULONG ulEngineClock; /* Override of default engine clock for particular memory type */ - ULONG ulMemoryClock; /* Override of default memory clock for particular memory type */ - USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */ - USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */ - USHORT usEMRSValue; - USHORT usMRSValue; - USHORT usReserved; - UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ - UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; */ - UCHAR ucMemoryVenderID; /* Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed */ - UCHAR ucMemoryDeviceCfg; /* [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... */ - UCHAR ucRow; /* Number of Row,in power of 2; */ - UCHAR ucColumn; /* Number of Column,in power of 2; */ - UCHAR ucBank; /* Nunber of Bank; */ - UCHAR ucRank; /* Number of Rank, in power of 2 */ - UCHAR ucChannelNum; /* Number of channel; */ - UCHAR ucChannelConfig; /* [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 */ - UCHAR ucDefaultMVDDQ_ID; /* Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; */ - UCHAR ucDefaultMVDDC_ID; /* Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; */ - UCHAR ucRefreshRateFactor; - UCHAR ucReserved[3]; -} ATOM_VRAM_MODULE_V2; - -typedef struct _ATOM_MEMORY_TIMING_FORMAT { - ULONG ulClkRange; /* memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing */ - union { - USHORT usMRS; /* mode register */ - USHORT usDDR3_MR0; - }; - union { - USHORT usEMRS; /* extended mode register */ - USHORT usDDR3_MR1; - }; - UCHAR ucCL; /* CAS latency */ - UCHAR ucWL; /* WRITE Latency */ - UCHAR uctRAS; /* tRAS */ - UCHAR uctRC; /* tRC */ - UCHAR uctRFC; /* tRFC */ - UCHAR uctRCDR; /* tRCDR */ - UCHAR uctRCDW; /* tRCDW */ - UCHAR uctRP; /* tRP */ - UCHAR uctRRD; /* tRRD */ - UCHAR uctWR; /* tWR */ - UCHAR uctWTR; /* tWTR */ - UCHAR uctPDIX; /* tPDIX */ - UCHAR uctFAW; /* tFAW */ - UCHAR uctAOND; /* tAOND */ - union { - struct { - UCHAR ucflag; /* flag to control memory timing calculation. bit0= control EMRS2 Infineon */ - UCHAR ucReserved; - }; - USHORT usDDR3_MR2; - }; -} ATOM_MEMORY_TIMING_FORMAT; - -typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 { - ULONG ulClkRange; /* memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing */ - USHORT usMRS; /* mode register */ - USHORT usEMRS; /* extended mode register */ - UCHAR ucCL; /* CAS latency */ - UCHAR ucWL; /* WRITE Latency */ - UCHAR uctRAS; /* tRAS */ - UCHAR uctRC; /* tRC */ - UCHAR uctRFC; /* tRFC */ - UCHAR uctRCDR; /* tRCDR */ - UCHAR uctRCDW; /* tRCDW */ - UCHAR uctRP; /* tRP */ - UCHAR uctRRD; /* tRRD */ - UCHAR uctWR; /* tWR */ - UCHAR uctWTR; /* tWTR */ - UCHAR uctPDIX; /* tPDIX */ - UCHAR uctFAW; /* tFAW */ - UCHAR uctAOND; /* tAOND */ - UCHAR ucflag; /* flag to control memory timing calculation. bit0= control EMRS2 Infineon */ -/* ///////////////////////GDDR parameters/////////////////////////////////// */ - UCHAR uctCCDL; /* */ - UCHAR uctCRCRL; /* */ - UCHAR uctCRCWL; /* */ - UCHAR uctCKE; /* */ - UCHAR uctCKRSE; /* */ - UCHAR uctCKRSX; /* */ - UCHAR uctFAW32; /* */ - UCHAR ucReserved1; /* */ - UCHAR ucReserved2; /* */ - UCHAR ucTerminator; -} ATOM_MEMORY_TIMING_FORMAT_V1; - -typedef struct _ATOM_MEMORY_FORMAT { - ULONG ulDllDisClock; /* memory DLL will be disable when target memory clock is below this clock */ - union { - USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */ - USHORT usDDR3_Reserved; /* Not used for DDR3 memory */ - }; - union { - USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */ - USHORT usDDR3_MR3; /* Used for DDR3 memory */ - }; - UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; */ - UCHAR ucMemoryVenderID; /* Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed */ - UCHAR ucRow; /* Number of Row,in power of 2; */ - UCHAR ucColumn; /* Number of Column,in power of 2; */ - UCHAR ucBank; /* Nunber of Bank; */ - UCHAR ucRank; /* Number of Rank, in power of 2 */ - UCHAR ucBurstSize; /* burst size, 0= burst size=4 1= burst size=8 */ - UCHAR ucDllDisBit; /* position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) */ - UCHAR ucRefreshRateFactor; /* memory refresh rate in unit of ms */ - UCHAR ucDensity; /* _8Mx32, _16Mx32, _16Mx16, _32Mx16 */ - UCHAR ucPreamble; /* [7:4] Write Preamble, [3:0] Read Preamble */ - UCHAR ucMemAttrib; /* Memory Device Addribute, like RDBI/WDBI etc */ - ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; /* Memory Timing block sort from lower clock to higher clock */ -} ATOM_MEMORY_FORMAT; - -typedef struct _ATOM_VRAM_MODULE_V3 { - ULONG ulChannelMapCfg; /* board dependent paramenter:Channel combination */ - USHORT usSize; /* size of ATOM_VRAM_MODULE_V3 */ - USHORT usDefaultMVDDQ; /* board dependent parameter:Default Memory Core Voltage */ - USHORT usDefaultMVDDC; /* board dependent parameter:Default Memory IO Voltage */ - UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ - UCHAR ucChannelNum; /* board dependent parameter:Number of channel; */ - UCHAR ucChannelSize; /* board dependent parameter:32bit or 64bit */ - UCHAR ucVREFI; /* board dependnt parameter: EXT or INT +160mv to -140mv */ - UCHAR ucNPL_RT; /* board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */ - UCHAR ucFlag; /* To enable/disable functionalities based on memory type */ - ATOM_MEMORY_FORMAT asMemory; /* describ all of video memory parameters from memory spec */ -} ATOM_VRAM_MODULE_V3; - -/* ATOM_VRAM_MODULE_V3.ucNPL_RT */ +typedef struct _ATOM_VRAM_MODULE_V1 +{ + ULONG ulReserved; + USHORT usEMRSValue; + USHORT usMRSValue; + USHORT usReserved; + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; + UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender + UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... + UCHAR ucRow; // Number of Row,in power of 2; + UCHAR ucColumn; // Number of Column,in power of 2; + UCHAR ucBank; // Nunber of Bank; + UCHAR ucRank; // Number of Rank, in power of 2 + UCHAR ucChannelNum; // Number of channel; + UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 + UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; + UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; + UCHAR ucReserved[2]; +}ATOM_VRAM_MODULE_V1; + + +typedef struct _ATOM_VRAM_MODULE_V2 +{ + ULONG ulReserved; + ULONG ulFlags; // To enable/disable functionalities based on memory type + ULONG ulEngineClock; // Override of default engine clock for particular memory type + ULONG ulMemoryClock; // Override of default memory clock for particular memory type + USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type + USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type + USHORT usEMRSValue; + USHORT usMRSValue; + USHORT usReserved; + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; + UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed + UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... + UCHAR ucRow; // Number of Row,in power of 2; + UCHAR ucColumn; // Number of Column,in power of 2; + UCHAR ucBank; // Nunber of Bank; + UCHAR ucRank; // Number of Rank, in power of 2 + UCHAR ucChannelNum; // Number of channel; + UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 + UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; + UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; + UCHAR ucRefreshRateFactor; + UCHAR ucReserved[3]; +}ATOM_VRAM_MODULE_V2; + + +typedef struct _ATOM_MEMORY_TIMING_FORMAT +{ + ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing + union{ + USHORT usMRS; // mode register + USHORT usDDR3_MR0; + }; + union{ + USHORT usEMRS; // extended mode register + USHORT usDDR3_MR1; + }; + UCHAR ucCL; // CAS latency + UCHAR ucWL; // WRITE Latency + UCHAR uctRAS; // tRAS + UCHAR uctRC; // tRC + UCHAR uctRFC; // tRFC + UCHAR uctRCDR; // tRCDR + UCHAR uctRCDW; // tRCDW + UCHAR uctRP; // tRP + UCHAR uctRRD; // tRRD + UCHAR uctWR; // tWR + UCHAR uctWTR; // tWTR + UCHAR uctPDIX; // tPDIX + UCHAR uctFAW; // tFAW + UCHAR uctAOND; // tAOND + union + { + struct { + UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon + UCHAR ucReserved; + }; + USHORT usDDR3_MR2; + }; +}ATOM_MEMORY_TIMING_FORMAT; + + +typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 +{ + ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing + USHORT usMRS; // mode register + USHORT usEMRS; // extended mode register + UCHAR ucCL; // CAS latency + UCHAR ucWL; // WRITE Latency + UCHAR uctRAS; // tRAS + UCHAR uctRC; // tRC + UCHAR uctRFC; // tRFC + UCHAR uctRCDR; // tRCDR + UCHAR uctRCDW; // tRCDW + UCHAR uctRP; // tRP + UCHAR uctRRD; // tRRD + UCHAR uctWR; // tWR + UCHAR uctWTR; // tWTR + UCHAR uctPDIX; // tPDIX + UCHAR uctFAW; // tFAW + UCHAR uctAOND; // tAOND + UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon +////////////////////////////////////GDDR parameters/////////////////////////////////// + UCHAR uctCCDL; // + UCHAR uctCRCRL; // + UCHAR uctCRCWL; // + UCHAR uctCKE; // + UCHAR uctCKRSE; // + UCHAR uctCKRSX; // + UCHAR uctFAW32; // + UCHAR ucMR5lo; // + UCHAR ucMR5hi; // + UCHAR ucTerminator; +}ATOM_MEMORY_TIMING_FORMAT_V1; + +typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 +{ + ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing + USHORT usMRS; // mode register + USHORT usEMRS; // extended mode register + UCHAR ucCL; // CAS latency + UCHAR ucWL; // WRITE Latency + UCHAR uctRAS; // tRAS + UCHAR uctRC; // tRC + UCHAR uctRFC; // tRFC + UCHAR uctRCDR; // tRCDR + UCHAR uctRCDW; // tRCDW + UCHAR uctRP; // tRP + UCHAR uctRRD; // tRRD + UCHAR uctWR; // tWR + UCHAR uctWTR; // tWTR + UCHAR uctPDIX; // tPDIX + UCHAR uctFAW; // tFAW + UCHAR uctAOND; // tAOND + UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon +////////////////////////////////////GDDR parameters/////////////////////////////////// + UCHAR uctCCDL; // + UCHAR uctCRCRL; // + UCHAR uctCRCWL; // + UCHAR uctCKE; // + UCHAR uctCKRSE; // + UCHAR uctCKRSX; // + UCHAR uctFAW32; // + UCHAR ucMR4lo; // + UCHAR ucMR4hi; // + UCHAR ucMR5lo; // + UCHAR ucMR5hi; // + UCHAR ucTerminator; + UCHAR ucReserved; +}ATOM_MEMORY_TIMING_FORMAT_V2; + +typedef struct _ATOM_MEMORY_FORMAT +{ + ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock + union{ + USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type + USHORT usDDR3_Reserved; // Not used for DDR3 memory + }; + union{ + USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type + USHORT usDDR3_MR3; // Used for DDR3 memory + }; + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; + UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed + UCHAR ucRow; // Number of Row,in power of 2; + UCHAR ucColumn; // Number of Column,in power of 2; + UCHAR ucBank; // Nunber of Bank; + UCHAR ucRank; // Number of Rank, in power of 2 + UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 + UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) + UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms + UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 + UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble + UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc + ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock +}ATOM_MEMORY_FORMAT; + + +typedef struct _ATOM_VRAM_MODULE_V3 +{ + ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination + USHORT usSize; // size of ATOM_VRAM_MODULE_V3 + USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage + USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucChannelNum; // board dependent parameter:Number of channel; + UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit + UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv + UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters + UCHAR ucFlag; // To enable/disable functionalities based on memory type + ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec +}ATOM_VRAM_MODULE_V3; + + +//ATOM_VRAM_MODULE_V3.ucNPL_RT #define NPL_RT_MASK 0x0f #define BATTERY_ODT_MASK 0xc0 #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 -typedef struct _ATOM_VRAM_MODULE_V4 { - ULONG ulChannelMapCfg; /* board dependent parameter: Channel combination */ - USHORT usModuleSize; /* size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE */ - USHORT usPrivateReserved; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */ - /* MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) */ - USHORT usReserved; - UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ - UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; */ - UCHAR ucChannelNum; /* Number of channels present in this module config */ - UCHAR ucChannelWidth; /* 0 - 32 bits; 1 - 64 bits */ - UCHAR ucDensity; /* _8Mx32, _16Mx32, _16Mx16, _32Mx16 */ - UCHAR ucFlag; /* To enable/disable functionalities based on memory type */ - UCHAR ucMisc; /* bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 */ - UCHAR ucVREFI; /* board dependent parameter */ - UCHAR ucNPL_RT; /* board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */ - UCHAR ucPreamble; /* [7:4] Write Preamble, [3:0] Read Preamble */ - UCHAR ucMemorySize; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */ - /* Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros */ - UCHAR ucReserved[3]; - -/* compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level */ - union { - USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */ - USHORT usDDR3_Reserved; - }; - union { - USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */ - USHORT usDDR3_MR3; /* Used for DDR3 memory */ - }; - UCHAR ucMemoryVenderID; /* Predefined, If not predefined, vendor detection table gets executed */ - UCHAR ucRefreshRateFactor; /* [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) */ - UCHAR ucReserved2[2]; - ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; /* Memory Timing block sort from lower clock to higher clock */ -} ATOM_VRAM_MODULE_V4; +typedef struct _ATOM_VRAM_MODULE_V4 +{ + ULONG ulChannelMapCfg; // board dependent parameter: Channel combination + USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE + USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! + // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) + USHORT usReserved; + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; + UCHAR ucChannelNum; // Number of channels present in this module config + UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits + UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 + UCHAR ucFlag; // To enable/disable functionalities based on memory type + UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 + UCHAR ucVREFI; // board dependent parameter + UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters + UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble + UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! + // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros + UCHAR ucReserved[3]; + +//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level + union{ + USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type + USHORT usDDR3_Reserved; + }; + union{ + USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type + USHORT usDDR3_MR3; // Used for DDR3 memory + }; + UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed + UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) + UCHAR ucReserved2[2]; + ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock +}ATOM_VRAM_MODULE_V4; #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 @@ -3973,96 +4841,139 @@ typedef struct _ATOM_VRAM_MODULE_V4 { #define VRAM_MODULE_V4_MISC_BL8 0x4 #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 -typedef struct _ATOM_VRAM_MODULE_V5 { - ULONG ulChannelMapCfg; /* board dependent parameter: Channel combination */ - USHORT usModuleSize; /* size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE */ - USHORT usPrivateReserved; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */ - /* MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) */ - USHORT usReserved; - UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ - UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; */ - UCHAR ucChannelNum; /* Number of channels present in this module config */ - UCHAR ucChannelWidth; /* 0 - 32 bits; 1 - 64 bits */ - UCHAR ucDensity; /* _8Mx32, _16Mx32, _16Mx16, _32Mx16 */ - UCHAR ucFlag; /* To enable/disable functionalities based on memory type */ - UCHAR ucMisc; /* bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 */ - UCHAR ucVREFI; /* board dependent parameter */ - UCHAR ucNPL_RT; /* board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */ - UCHAR ucPreamble; /* [7:4] Write Preamble, [3:0] Read Preamble */ - UCHAR ucMemorySize; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */ - /* Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros */ - UCHAR ucReserved[3]; +typedef struct _ATOM_VRAM_MODULE_V5 +{ + ULONG ulChannelMapCfg; // board dependent parameter: Channel combination + USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE + USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! + // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) + USHORT usReserved; + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; + UCHAR ucChannelNum; // Number of channels present in this module config + UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits + UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 + UCHAR ucFlag; // To enable/disable functionalities based on memory type + UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 + UCHAR ucVREFI; // board dependent parameter + UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters + UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble + UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! + // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros + UCHAR ucReserved[3]; + +//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level + USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type + USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type + UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed + UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) + UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth + UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth + ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock +}ATOM_VRAM_MODULE_V5; + +typedef struct _ATOM_VRAM_MODULE_V6 +{ + ULONG ulChannelMapCfg; // board dependent parameter: Channel combination + USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE + USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! + // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) + USHORT usReserved; + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; + UCHAR ucChannelNum; // Number of channels present in this module config + UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits + UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 + UCHAR ucFlag; // To enable/disable functionalities based on memory type + UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 + UCHAR ucVREFI; // board dependent parameter + UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters + UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble + UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! + // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros + UCHAR ucReserved[3]; + +//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level + USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type + USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type + UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed + UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) + UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth + UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth + ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock +}ATOM_VRAM_MODULE_V6; + + + +typedef struct _ATOM_VRAM_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucNumOfVRAMModule; + ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; +}ATOM_VRAM_INFO_V2; -/* compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level */ - USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */ - USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */ - UCHAR ucMemoryVenderID; /* Predefined, If not predefined, vendor detection table gets executed */ - UCHAR ucRefreshRateFactor; /* [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) */ - UCHAR ucFIFODepth; /* FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth */ - UCHAR ucCDR_Bandwidth; /* [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth */ - ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5]; /* Memory Timing block sort from lower clock to higher clock */ -} ATOM_VRAM_MODULE_V5; - -typedef struct _ATOM_VRAM_INFO_V2 { - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucNumOfVRAMModule; - ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; /* just for allocation, real number of blocks is in ucNumOfVRAMModule; */ -} ATOM_VRAM_INFO_V2; - -typedef struct _ATOM_VRAM_INFO_V3 { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMemAdjustTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting */ - USHORT usMemClkPatchTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting */ - USHORT usRerseved; - UCHAR aVID_PinsShift[9]; /* 8 bit strap maximum+terminator */ - UCHAR ucNumOfVRAMModule; - ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; /* just for allocation, real number of blocks is in ucNumOfVRAMModule; */ - ATOM_INIT_REG_BLOCK asMemPatch; /* for allocation */ - /* ATOM_INIT_REG_BLOCK aMemAdjust; */ -} ATOM_VRAM_INFO_V3; +typedef struct _ATOM_VRAM_INFO_V3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting + USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting + USHORT usRerseved; + UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator + UCHAR ucNumOfVRAMModule; + ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; + ATOM_INIT_REG_BLOCK asMemPatch; // for allocation + // ATOM_INIT_REG_BLOCK aMemAdjust; +}ATOM_VRAM_INFO_V3; #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 -typedef struct _ATOM_VRAM_INFO_V4 { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMemAdjustTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting */ - USHORT usMemClkPatchTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting */ - USHORT usRerseved; - UCHAR ucMemDQ7_0ByteRemap; /* DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 */ - ULONG ulMemDQ7_0BitRemap; /* each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] */ - UCHAR ucReservde[4]; - UCHAR ucNumOfVRAMModule; - ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; /* just for allocation, real number of blocks is in ucNumOfVRAMModule; */ - ATOM_INIT_REG_BLOCK asMemPatch; /* for allocation */ - /* ATOM_INIT_REG_BLOCK aMemAdjust; */ -} ATOM_VRAM_INFO_V4; - -typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR aVID_PinsShift[9]; /* 8 bit strap maximum+terminator */ -} ATOM_VRAM_GPIO_DETECTION_INFO; - -typedef struct _ATOM_MEMORY_TRAINING_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucTrainingLoop; - UCHAR ucReserved[3]; - ATOM_INIT_REG_BLOCK asMemTrainingSetting; -} ATOM_MEMORY_TRAINING_INFO; - -typedef struct SW_I2C_CNTL_DATA_PARAMETERS { - UCHAR ucControl; - UCHAR ucData; - UCHAR ucSatus; - UCHAR ucTemp; +typedef struct _ATOM_VRAM_INFO_V4 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting + USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting + USHORT usRerseved; + UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 + ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] + UCHAR ucReservde[4]; + UCHAR ucNumOfVRAMModule; + ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; + ATOM_INIT_REG_BLOCK asMemPatch; // for allocation + // ATOM_INIT_REG_BLOCK aMemAdjust; +}ATOM_VRAM_INFO_V4; + +typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator +}ATOM_VRAM_GPIO_DETECTION_INFO; + + +typedef struct _ATOM_MEMORY_TRAINING_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucTrainingLoop; + UCHAR ucReserved[3]; + ATOM_INIT_REG_BLOCK asMemTrainingSetting; +}ATOM_MEMORY_TRAINING_INFO; + + +typedef struct SW_I2C_CNTL_DATA_PARAMETERS +{ + UCHAR ucControl; + UCHAR ucData; + UCHAR ucSatus; + UCHAR ucTemp; } SW_I2C_CNTL_DATA_PARAMETERS; #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS -typedef struct _SW_I2C_IO_DATA_PARAMETERS { - USHORT GPIO_Info; - UCHAR ucAct; - UCHAR ucData; -} SW_I2C_IO_DATA_PARAMETERS; +typedef struct _SW_I2C_IO_DATA_PARAMETERS +{ + USHORT GPIO_Info; + UCHAR ucAct; + UCHAR ucData; + } SW_I2C_IO_DATA_PARAMETERS; #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS @@ -4087,127 +4998,136 @@ typedef struct _SW_I2C_IO_DATA_PARAMETERS { #define SW_I2C_CNTL_CLOSE 5 #define SW_I2C_CNTL_WRITE1BIT 6 -/* ==============================VESA definition Portion=============================== */ +//==============================VESA definition Portion=============================== #define VESA_OEM_PRODUCT_REV '01.00' -#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB /* refer to VBE spec p.32, no TTY support */ +#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support #define VESA_MODE_WIN_ATTRIBUTE 7 #define VESA_WIN_SIZE 64 -typedef struct _PTR_32_BIT_STRUCTURE { - USHORT Offset16; - USHORT Segment16; +typedef struct _PTR_32_BIT_STRUCTURE +{ + USHORT Offset16; + USHORT Segment16; } PTR_32_BIT_STRUCTURE; -typedef union _PTR_32_BIT_UNION { - PTR_32_BIT_STRUCTURE SegmentOffset; - ULONG Ptr32_Bit; +typedef union _PTR_32_BIT_UNION +{ + PTR_32_BIT_STRUCTURE SegmentOffset; + ULONG Ptr32_Bit; } PTR_32_BIT_UNION; -typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE { - UCHAR VbeSignature[4]; - USHORT VbeVersion; - PTR_32_BIT_UNION OemStringPtr; - UCHAR Capabilities[4]; - PTR_32_BIT_UNION VideoModePtr; - USHORT TotalMemory; +typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE +{ + UCHAR VbeSignature[4]; + USHORT VbeVersion; + PTR_32_BIT_UNION OemStringPtr; + UCHAR Capabilities[4]; + PTR_32_BIT_UNION VideoModePtr; + USHORT TotalMemory; } VBE_1_2_INFO_BLOCK_UPDATABLE; -typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE { - VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; - USHORT OemSoftRev; - PTR_32_BIT_UNION OemVendorNamePtr; - PTR_32_BIT_UNION OemProductNamePtr; - PTR_32_BIT_UNION OemProductRevPtr; + +typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE +{ + VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; + USHORT OemSoftRev; + PTR_32_BIT_UNION OemVendorNamePtr; + PTR_32_BIT_UNION OemProductNamePtr; + PTR_32_BIT_UNION OemProductRevPtr; } VBE_2_0_INFO_BLOCK_UPDATABLE; -typedef union _VBE_VERSION_UNION { - VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; - VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; +typedef union _VBE_VERSION_UNION +{ + VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; + VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; } VBE_VERSION_UNION; -typedef struct _VBE_INFO_BLOCK { - VBE_VERSION_UNION UpdatableVBE_Info; - UCHAR Reserved[222]; - UCHAR OemData[256]; +typedef struct _VBE_INFO_BLOCK +{ + VBE_VERSION_UNION UpdatableVBE_Info; + UCHAR Reserved[222]; + UCHAR OemData[256]; } VBE_INFO_BLOCK; -typedef struct _VBE_FP_INFO { - USHORT HSize; - USHORT VSize; - USHORT FPType; - UCHAR RedBPP; - UCHAR GreenBPP; - UCHAR BlueBPP; - UCHAR ReservedBPP; - ULONG RsvdOffScrnMemSize; - ULONG RsvdOffScrnMEmPtr; - UCHAR Reserved[14]; +typedef struct _VBE_FP_INFO +{ + USHORT HSize; + USHORT VSize; + USHORT FPType; + UCHAR RedBPP; + UCHAR GreenBPP; + UCHAR BlueBPP; + UCHAR ReservedBPP; + ULONG RsvdOffScrnMemSize; + ULONG RsvdOffScrnMEmPtr; + UCHAR Reserved[14]; } VBE_FP_INFO; -typedef struct _VESA_MODE_INFO_BLOCK { -/* Mandatory information for all VBE revisions */ - USHORT ModeAttributes; /* dw ? ; mode attributes */ - UCHAR WinAAttributes; /* db ? ; window A attributes */ - UCHAR WinBAttributes; /* db ? ; window B attributes */ - USHORT WinGranularity; /* dw ? ; window granularity */ - USHORT WinSize; /* dw ? ; window size */ - USHORT WinASegment; /* dw ? ; window A start segment */ - USHORT WinBSegment; /* dw ? ; window B start segment */ - ULONG WinFuncPtr; /* dd ? ; real mode pointer to window function */ - USHORT BytesPerScanLine; /* dw ? ; bytes per scan line */ - -/* ; Mandatory information for VBE 1.2 and above */ - USHORT XResolution; /* dw ? ; horizontal resolution in pixels or characters */ - USHORT YResolution; /* dw ? ; vertical resolution in pixels or characters */ - UCHAR XCharSize; /* db ? ; character cell width in pixels */ - UCHAR YCharSize; /* db ? ; character cell height in pixels */ - UCHAR NumberOfPlanes; /* db ? ; number of memory planes */ - UCHAR BitsPerPixel; /* db ? ; bits per pixel */ - UCHAR NumberOfBanks; /* db ? ; number of banks */ - UCHAR MemoryModel; /* db ? ; memory model type */ - UCHAR BankSize; /* db ? ; bank size in KB */ - UCHAR NumberOfImagePages; /* db ? ; number of images */ - UCHAR ReservedForPageFunction; /* db 1 ; reserved for page function */ - -/* ; Direct Color fields(required for direct/6 and YUV/7 memory models) */ - UCHAR RedMaskSize; /* db ? ; size of direct color red mask in bits */ - UCHAR RedFieldPosition; /* db ? ; bit position of lsb of red mask */ - UCHAR GreenMaskSize; /* db ? ; size of direct color green mask in bits */ - UCHAR GreenFieldPosition; /* db ? ; bit position of lsb of green mask */ - UCHAR BlueMaskSize; /* db ? ; size of direct color blue mask in bits */ - UCHAR BlueFieldPosition; /* db ? ; bit position of lsb of blue mask */ - UCHAR RsvdMaskSize; /* db ? ; size of direct color reserved mask in bits */ - UCHAR RsvdFieldPosition; /* db ? ; bit position of lsb of reserved mask */ - UCHAR DirectColorModeInfo; /* db ? ; direct color mode attributes */ - -/* ; Mandatory information for VBE 2.0 and above */ - ULONG PhysBasePtr; /* dd ? ; physical address for flat memory frame buffer */ - ULONG Reserved_1; /* dd 0 ; reserved - always set to 0 */ - USHORT Reserved_2; /* dw 0 ; reserved - always set to 0 */ - -/* ; Mandatory information for VBE 3.0 and above */ - USHORT LinBytesPerScanLine; /* dw ? ; bytes per scan line for linear modes */ - UCHAR BnkNumberOfImagePages; /* db ? ; number of images for banked modes */ - UCHAR LinNumberOfImagPages; /* db ? ; number of images for linear modes */ - UCHAR LinRedMaskSize; /* db ? ; size of direct color red mask(linear modes) */ - UCHAR LinRedFieldPosition; /* db ? ; bit position of lsb of red mask(linear modes) */ - UCHAR LinGreenMaskSize; /* db ? ; size of direct color green mask(linear modes) */ - UCHAR LinGreenFieldPosition; /* db ? ; bit position of lsb of green mask(linear modes) */ - UCHAR LinBlueMaskSize; /* db ? ; size of direct color blue mask(linear modes) */ - UCHAR LinBlueFieldPosition; /* db ? ; bit position of lsb of blue mask(linear modes) */ - UCHAR LinRsvdMaskSize; /* db ? ; size of direct color reserved mask(linear modes) */ - UCHAR LinRsvdFieldPosition; /* db ? ; bit position of lsb of reserved mask(linear modes) */ - ULONG MaxPixelClock; /* dd ? ; maximum pixel clock(in Hz) for graphics mode */ - UCHAR Reserved; /* db 190 dup (0) */ +typedef struct _VESA_MODE_INFO_BLOCK +{ +// Mandatory information for all VBE revisions + USHORT ModeAttributes; // dw ? ; mode attributes + UCHAR WinAAttributes; // db ? ; window A attributes + UCHAR WinBAttributes; // db ? ; window B attributes + USHORT WinGranularity; // dw ? ; window granularity + USHORT WinSize; // dw ? ; window size + USHORT WinASegment; // dw ? ; window A start segment + USHORT WinBSegment; // dw ? ; window B start segment + ULONG WinFuncPtr; // dd ? ; real mode pointer to window function + USHORT BytesPerScanLine;// dw ? ; bytes per scan line + +//; Mandatory information for VBE 1.2 and above + USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters + USHORT YResolution; // dw ? ; vertical resolution in pixels or characters + UCHAR XCharSize; // db ? ; character cell width in pixels + UCHAR YCharSize; // db ? ; character cell height in pixels + UCHAR NumberOfPlanes; // db ? ; number of memory planes + UCHAR BitsPerPixel; // db ? ; bits per pixel + UCHAR NumberOfBanks; // db ? ; number of banks + UCHAR MemoryModel; // db ? ; memory model type + UCHAR BankSize; // db ? ; bank size in KB + UCHAR NumberOfImagePages;// db ? ; number of images + UCHAR ReservedForPageFunction;//db 1 ; reserved for page function + +//; Direct Color fields(required for direct/6 and YUV/7 memory models) + UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits + UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask + UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits + UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask + UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits + UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask + UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits + UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask + UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes + +//; Mandatory information for VBE 2.0 and above + ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer + ULONG Reserved_1; // dd 0 ; reserved - always set to 0 + USHORT Reserved_2; // dw 0 ; reserved - always set to 0 + +//; Mandatory information for VBE 3.0 and above + USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes + UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes + UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes + UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) + UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) + UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) + UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) + UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) + UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) + UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) + UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) + ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode + UCHAR Reserved; // db 190 dup (0) } VESA_MODE_INFO_BLOCK; -/* BIOS function CALLS */ -#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 /* ATI Extended Function code */ +// BIOS function CALLS +#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code #define ATOM_BIOS_FUNCTION_COP_MODE 0x00 #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 -#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B +#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F #define ATOM_BIOS_FUNCTION_STV_STD 0x16 @@ -4217,100 +5137,135 @@ typedef struct _VESA_MODE_INFO_BLOCK { #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 -#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A +#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B -#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 /* Sub function 80 */ -#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 /* Sub function 80 */ +#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 +#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E -#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F -#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 /* Sub function 03 */ -#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 /* Sub function 7 */ -#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 /* Notify caller the current thermal state */ -#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 /* Notify caller the current critical state */ -#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 /* Sub function 85 */ -#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900 /* Sub function 89 */ -#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 /* Notify caller that ADC is supported */ - -#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 /* Set DPMS */ -#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 /* BL: Sub function 01 */ -#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 /* BL: Sub function 02 */ -#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 /* BH Parameter for DPMS ON. */ -#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 /* BH Parameter for DPMS STANDBY */ -#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 /* BH Parameter for DPMS SUSPEND */ -#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 /* BH Parameter for DPMS OFF */ -#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 /* BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) */ +#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F +#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 +#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 +#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state +#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state +#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 +#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 +#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported + + +#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS +#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 +#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 +#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. +#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY +#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND +#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF +#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL -/* structure used for VBIOS only */ +// structure used for VBIOS only -/* DispOutInfoTable */ -typedef struct _ASIC_TRANSMITTER_INFO { +//DispOutInfoTable +typedef struct _ASIC_TRANSMITTER_INFO +{ USHORT usTransmitterObjId; USHORT usSupportDevice; - UCHAR ucTransmitterCmdTblId; - UCHAR ucConfig; - UCHAR ucEncoderID; /* available 1st encoder ( default ) */ - UCHAR ucOptionEncoderID; /* available 2nd encoder ( optional ) */ - UCHAR uc2ndEncoderID; - UCHAR ucReserved; -} ASIC_TRANSMITTER_INFO; - -typedef struct _ASIC_ENCODER_INFO { + UCHAR ucTransmitterCmdTblId; + UCHAR ucConfig; + UCHAR ucEncoderID; //available 1st encoder ( default ) + UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) + UCHAR uc2ndEncoderID; + UCHAR ucReserved; +}ASIC_TRANSMITTER_INFO; + +typedef struct _ASIC_ENCODER_INFO +{ UCHAR ucEncoderID; UCHAR ucEncoderConfig; - USHORT usEncoderCmdTblId; -} ASIC_ENCODER_INFO; + USHORT usEncoderCmdTblId; +}ASIC_ENCODER_INFO; -typedef struct _ATOM_DISP_OUT_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; +typedef struct _ATOM_DISP_OUT_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT ptrTransmitterInfo; + USHORT ptrEncoderInfo; + ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; + ASIC_ENCODER_INFO asEncoderInfo[1]; +}ATOM_DISP_OUT_INFO; + +typedef struct _ATOM_DISP_OUT_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; USHORT ptrTransmitterInfo; USHORT ptrEncoderInfo; - ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; - ASIC_ENCODER_INFO asEncoderInfo[1]; -} ATOM_DISP_OUT_INFO; + USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. + ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; + ASIC_ENCODER_INFO asEncoderInfo[1]; +}ATOM_DISP_OUT_INFO_V2; -/* DispDevicePriorityInfo */ -typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; +// DispDevicePriorityInfo +typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; USHORT asDevicePriority[16]; -} ATOM_DISPLAY_DEVICE_PRIORITY_INFO; - -/* ProcessAuxChannelTransactionTable */ -typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS { - USHORT lpAuxRequest; - USHORT lpDataOut; - UCHAR ucChannelID; - union { - UCHAR ucReplyStatus; - UCHAR ucDelay; +}ATOM_DISPLAY_DEVICE_PRIORITY_INFO; + +//ProcessAuxChannelTransactionTable +typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS +{ + USHORT lpAuxRequest; + USHORT lpDataOut; + UCHAR ucChannelID; + union + { + UCHAR ucReplyStatus; + UCHAR ucDelay; }; - UCHAR ucDataOutLen; - UCHAR ucReserved; -} PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; + UCHAR ucDataOutLen; + UCHAR ucReserved; +}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; + +//ProcessAuxChannelTransactionTable +typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 +{ + USHORT lpAuxRequest; + USHORT lpDataOut; + UCHAR ucChannelID; + union + { + UCHAR ucReplyStatus; + UCHAR ucDelay; + }; + UCHAR ucDataOutLen; + UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 +}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS -/* GetSinkType */ +//GetSinkType -typedef struct _DP_ENCODER_SERVICE_PARAMETERS { +typedef struct _DP_ENCODER_SERVICE_PARAMETERS +{ USHORT ucLinkClock; - union { - UCHAR ucConfig; /* for DP training command */ - UCHAR ucI2cId; /* use for GET_SINK_TYPE command */ + union + { + UCHAR ucConfig; // for DP training command + UCHAR ucI2cId; // use for GET_SINK_TYPE command }; UCHAR ucAction; UCHAR ucStatus; UCHAR ucLaneNum; UCHAR ucReserved[2]; -} DP_ENCODER_SERVICE_PARAMETERS; +}DP_ENCODER_SERVICE_PARAMETERS; -/* ucAction */ +// ucAction #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 +/* obselete */ #define ATOM_DP_ACTION_TRAINING_START 0x02 #define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 @@ -4318,7 +5273,7 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS { #define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 #define ATOM_DP_ACTION_BLANKING 0x07 -/* ucConfig */ +// ucConfig #define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 #define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 #define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 @@ -4326,14 +5281,14 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS { #define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 #define ATOM_DP_CONFIG_LINK_A 0x00 #define ATOM_DP_CONFIG_LINK_B 0x04 - +/* /obselete */ #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS -/* DP_TRAINING_TABLE */ -#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR +// DP_TRAINING_TABLE +#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) -#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16) -#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24) +#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) +#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) @@ -4341,183 +5296,241 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS { #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) -#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) +#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) +#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) -typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS { - UCHAR ucI2CSpeed; - union { - UCHAR ucRegIndex; - UCHAR ucStatus; +typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS +{ + UCHAR ucI2CSpeed; + union + { + UCHAR ucRegIndex; + UCHAR ucStatus; }; - USHORT lpI2CDataOut; - UCHAR ucFlag; - UCHAR ucTransBytes; - UCHAR ucSlaveAddr; - UCHAR ucLineNumber; -} PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; + USHORT lpI2CDataOut; + UCHAR ucFlag; + UCHAR ucTransBytes; + UCHAR ucSlaveAddr; + UCHAR ucLineNumber; +}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS -/* ucFlag */ +//ucFlag #define HW_I2C_WRITE 1 #define HW_I2C_READ 0 +#define I2C_2BYTE_ADDR 0x02 +typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 +{ + UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... + UCHAR ucReserved[3]; +}SET_HWBLOCK_INSTANCE_PARAMETER_V2; + +#define HWBLKINST_INSTANCE_MASK 0x07 +#define HWBLKINST_HWBLK_MASK 0xF0 +#define HWBLKINST_HWBLK_SHIFT 0x04 + +//ucHWBlock +#define SELECT_DISP_ENGINE 0 +#define SELECT_DISP_PLL 1 +#define SELECT_DCIO_UNIPHY_LINK0 2 +#define SELECT_DCIO_UNIPHY_LINK1 3 +#define SELECT_DCIO_IMPCAL 4 +#define SELECT_DCIO_DIG 6 +#define SELECT_CRTC_PIXEL_RATE 7 + +/****************************************************************************/ +//Portion VI: Definitinos for vbios MC scratch registers that driver used /****************************************************************************/ -/* Portion VI: Definitinos being oboselete */ + +#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 +#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 +#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 +#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 +#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 +#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 +#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 + +/****************************************************************************/ +//Portion VI: Definitinos being oboselete /****************************************************************************/ -/* ========================================================================================== */ -/* Remove the definitions below when driver is ready! */ -typedef struct _ATOM_DAC_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMaxFrequency; /* in 10kHz unit */ - USHORT usReserved; -} ATOM_DAC_INFO; - -typedef struct _COMPASSIONATE_DATA { - ATOM_COMMON_TABLE_HEADER sHeader; - - /* ============================== DAC1 portion */ - UCHAR ucDAC1_BG_Adjustment; - UCHAR ucDAC1_DAC_Adjustment; - USHORT usDAC1_FORCE_Data; - /* ============================== DAC2 portion */ - UCHAR ucDAC2_CRT2_BG_Adjustment; - UCHAR ucDAC2_CRT2_DAC_Adjustment; - USHORT usDAC2_CRT2_FORCE_Data; - USHORT usDAC2_CRT2_MUX_RegisterIndex; - UCHAR ucDAC2_CRT2_MUX_RegisterInfo; /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */ - UCHAR ucDAC2_NTSC_BG_Adjustment; - UCHAR ucDAC2_NTSC_DAC_Adjustment; - USHORT usDAC2_TV1_FORCE_Data; - USHORT usDAC2_TV1_MUX_RegisterIndex; - UCHAR ucDAC2_TV1_MUX_RegisterInfo; /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */ - UCHAR ucDAC2_CV_BG_Adjustment; - UCHAR ucDAC2_CV_DAC_Adjustment; - USHORT usDAC2_CV_FORCE_Data; - USHORT usDAC2_CV_MUX_RegisterIndex; - UCHAR ucDAC2_CV_MUX_RegisterInfo; /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */ - UCHAR ucDAC2_PAL_BG_Adjustment; - UCHAR ucDAC2_PAL_DAC_Adjustment; - USHORT usDAC2_TV2_FORCE_Data; -} COMPASSIONATE_DATA; +//========================================================================================== +//Remove the definitions below when driver is ready! +typedef struct _ATOM_DAC_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMaxFrequency; // in 10kHz unit + USHORT usReserved; +}ATOM_DAC_INFO; + + +typedef struct _COMPASSIONATE_DATA +{ + ATOM_COMMON_TABLE_HEADER sHeader; + + //============================== DAC1 portion + UCHAR ucDAC1_BG_Adjustment; + UCHAR ucDAC1_DAC_Adjustment; + USHORT usDAC1_FORCE_Data; + //============================== DAC2 portion + UCHAR ucDAC2_CRT2_BG_Adjustment; + UCHAR ucDAC2_CRT2_DAC_Adjustment; + USHORT usDAC2_CRT2_FORCE_Data; + USHORT usDAC2_CRT2_MUX_RegisterIndex; + UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low + UCHAR ucDAC2_NTSC_BG_Adjustment; + UCHAR ucDAC2_NTSC_DAC_Adjustment; + USHORT usDAC2_TV1_FORCE_Data; + USHORT usDAC2_TV1_MUX_RegisterIndex; + UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low + UCHAR ucDAC2_CV_BG_Adjustment; + UCHAR ucDAC2_CV_DAC_Adjustment; + USHORT usDAC2_CV_FORCE_Data; + USHORT usDAC2_CV_MUX_RegisterIndex; + UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low + UCHAR ucDAC2_PAL_BG_Adjustment; + UCHAR ucDAC2_PAL_DAC_Adjustment; + USHORT usDAC2_TV2_FORCE_Data; +}COMPASSIONATE_DATA; /****************************Supported Device Info Table Definitions**********************/ -/* ucConnectInfo: */ -/* [7:4] - connector type */ -/* = 1 - VGA connector */ -/* = 2 - DVI-I */ -/* = 3 - DVI-D */ -/* = 4 - DVI-A */ -/* = 5 - SVIDEO */ -/* = 6 - COMPOSITE */ -/* = 7 - LVDS */ -/* = 8 - DIGITAL LINK */ -/* = 9 - SCART */ -/* = 0xA - HDMI_type A */ -/* = 0xB - HDMI_type B */ -/* = 0xE - Special case1 (DVI+DIN) */ -/* Others=TBD */ -/* [3:0] - DAC Associated */ -/* = 0 - no DAC */ -/* = 1 - DACA */ -/* = 2 - DACB */ -/* = 3 - External DAC */ -/* Others=TBD */ -/* */ - -typedef struct _ATOM_CONNECTOR_INFO { +// ucConnectInfo: +// [7:4] - connector type +// = 1 - VGA connector +// = 2 - DVI-I +// = 3 - DVI-D +// = 4 - DVI-A +// = 5 - SVIDEO +// = 6 - COMPOSITE +// = 7 - LVDS +// = 8 - DIGITAL LINK +// = 9 - SCART +// = 0xA - HDMI_type A +// = 0xB - HDMI_type B +// = 0xE - Special case1 (DVI+DIN) +// Others=TBD +// [3:0] - DAC Associated +// = 0 - no DAC +// = 1 - DACA +// = 2 - DACB +// = 3 - External DAC +// Others=TBD +// + +typedef struct _ATOM_CONNECTOR_INFO +{ #if ATOM_BIG_ENDIAN - UCHAR bfConnectorType:4; - UCHAR bfAssociatedDAC:4; + UCHAR bfConnectorType:4; + UCHAR bfAssociatedDAC:4; #else - UCHAR bfAssociatedDAC:4; - UCHAR bfConnectorType:4; + UCHAR bfAssociatedDAC:4; + UCHAR bfConnectorType:4; #endif -} ATOM_CONNECTOR_INFO; +}ATOM_CONNECTOR_INFO; + +typedef union _ATOM_CONNECTOR_INFO_ACCESS +{ + ATOM_CONNECTOR_INFO sbfAccess; + UCHAR ucAccess; +}ATOM_CONNECTOR_INFO_ACCESS; -typedef union _ATOM_CONNECTOR_INFO_ACCESS { - ATOM_CONNECTOR_INFO sbfAccess; - UCHAR ucAccess; -} ATOM_CONNECTOR_INFO_ACCESS; +typedef struct _ATOM_CONNECTOR_INFO_I2C +{ + ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; +}ATOM_CONNECTOR_INFO_I2C; -typedef struct _ATOM_CONNECTOR_INFO_I2C { - ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; -} ATOM_CONNECTOR_INFO_I2C; -typedef struct _ATOM_SUPPORTED_DEVICES_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; -} ATOM_SUPPORTED_DEVICES_INFO; +typedef struct _ATOM_SUPPORTED_DEVICES_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; +}ATOM_SUPPORTED_DEVICES_INFO; #define NO_INT_SRC_MAPPED 0xFF -typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP { - UCHAR ucIntSrcBitmap; -} ATOM_CONNECTOR_INC_SRC_BITMAP; - -typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; - ATOM_CONNECTOR_INC_SRC_BITMAP - asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; -} ATOM_SUPPORTED_DEVICES_INFO_2; - -typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; - ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; -} ATOM_SUPPORTED_DEVICES_INFO_2d1; +typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP +{ + UCHAR ucIntSrcBitmap; +}ATOM_CONNECTOR_INC_SRC_BITMAP; + +typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; + ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; +}ATOM_SUPPORTED_DEVICES_INFO_2; + +typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; + ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; +}ATOM_SUPPORTED_DEVICES_INFO_2d1; #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 -typedef struct _ATOM_MISC_CONTROL_INFO { - USHORT usFrequency; - UCHAR ucPLL_ChargePump; /* PLL charge-pump gain control */ - UCHAR ucPLL_DutyCycle; /* PLL duty cycle control */ - UCHAR ucPLL_VCO_Gain; /* PLL VCO gain control */ - UCHAR ucPLL_VoltageSwing; /* PLL driver voltage swing control */ -} ATOM_MISC_CONTROL_INFO; + + +typedef struct _ATOM_MISC_CONTROL_INFO +{ + USHORT usFrequency; + UCHAR ucPLL_ChargePump; // PLL charge-pump gain control + UCHAR ucPLL_DutyCycle; // PLL duty cycle control + UCHAR ucPLL_VCO_Gain; // PLL VCO gain control + UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control +}ATOM_MISC_CONTROL_INFO; + #define ATOM_MAX_MISC_INFO 4 -typedef struct _ATOM_TMDS_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMaxFrequency; /* in 10Khz */ - ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; -} ATOM_TMDS_INFO; +typedef struct _ATOM_TMDS_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMaxFrequency; // in 10Khz + ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; +}ATOM_TMDS_INFO; + -typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE { - UCHAR ucTVStandard; /* Same as TV standards defined above, */ - UCHAR ucPadding[1]; -} ATOM_ENCODER_ANALOG_ATTRIBUTE; +typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE +{ + UCHAR ucTVStandard; //Same as TV standards defined above, + UCHAR ucPadding[1]; +}ATOM_ENCODER_ANALOG_ATTRIBUTE; -typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE { - UCHAR ucAttribute; /* Same as other digital encoder attributes defined above */ - UCHAR ucPadding[1]; -} ATOM_ENCODER_DIGITAL_ATTRIBUTE; +typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE +{ + UCHAR ucAttribute; //Same as other digital encoder attributes defined above + UCHAR ucPadding[1]; +}ATOM_ENCODER_DIGITAL_ATTRIBUTE; -typedef union _ATOM_ENCODER_ATTRIBUTE { - ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; - ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; -} ATOM_ENCODER_ATTRIBUTE; +typedef union _ATOM_ENCODER_ATTRIBUTE +{ + ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; + ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; +}ATOM_ENCODER_ATTRIBUTE; -typedef struct _DVO_ENCODER_CONTROL_PARAMETERS { - USHORT usPixelClock; - USHORT usEncoderID; - UCHAR ucDeviceType; /* Use ATOM_DEVICE_xxx1_Index to indicate device type only. */ - UCHAR ucAction; /* ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT */ - ATOM_ENCODER_ATTRIBUTE usDevAttr; -} DVO_ENCODER_CONTROL_PARAMETERS; -typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION { - DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Caller doesn't need to init this portion */ -} DVO_ENCODER_CONTROL_PS_ALLOCATION; +typedef struct _DVO_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; + USHORT usEncoderID; + UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. + UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT + ATOM_ENCODER_ATTRIBUTE usDevAttr; +}DVO_ENCODER_CONTROL_PARAMETERS; + +typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION +{ + DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion +}DVO_ENCODER_CONTROL_PS_ALLOCATION; + #define ATOM_XTMDS_ASIC_SI164_ID 1 #define ATOM_XTMDS_ASIC_SI178_ID 2 @@ -4526,27 +5539,30 @@ typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION { #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 #define ATOM_XTMDS_MVPU_FPGA 0x00000004 -typedef struct _ATOM_XTMDS_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usSingleLinkMaxFrequency; - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; /* Point the ID on which I2C is used to control external chip */ - UCHAR ucXtransimitterID; - UCHAR ucSupportedLink; /* Bit field, bit0=1, single link supported;bit1=1,dual link supported */ - UCHAR ucSequnceAlterID; /* Even with the same external TMDS asic, it's possible that the program seqence alters */ - /* due to design. This ID is used to alert driver that the sequence is not "standard"! */ - UCHAR ucMasterAddress; /* Address to control Master xTMDS Chip */ - UCHAR ucSlaveAddress; /* Address to control Slave xTMDS Chip */ -} ATOM_XTMDS_INFO; - -typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS { - UCHAR ucEnable; /* ATOM_ENABLE=On or ATOM_DISABLE=Off */ - UCHAR ucDevice; /* ATOM_DEVICE_DFP1_INDEX.... */ - UCHAR ucPadding[2]; -} DFP_DPMS_STATUS_CHANGE_PARAMETERS; + +typedef struct _ATOM_XTMDS_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usSingleLinkMaxFrequency; + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip + UCHAR ucXtransimitterID; + UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported + UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters + // due to design. This ID is used to alert driver that the sequence is not "standard"! + UCHAR ucMasterAddress; // Address to control Master xTMDS Chip + UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip +}ATOM_XTMDS_INFO; + +typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS +{ + UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off + UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... + UCHAR ucPadding[2]; +}DFP_DPMS_STATUS_CHANGE_PARAMETERS; /****************************Legacy Power Play Table Definitions **********************/ -/* Definitions for ulPowerPlayMiscInfo */ +//Definitions for ulPowerPlayMiscInfo #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L @@ -4558,8 +5574,8 @@ typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS { #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L -#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L /* When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program */ - +#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program + #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L @@ -4569,22 +5585,22 @@ typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS { #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L -#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L +#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L -#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L /* 0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved */ -#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 +#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved +#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L -#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L /* When set, Dynamic */ -#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L /* When set, Dynamic */ -#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L /* When set, This mode is for acceleated 3D mode */ +#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic +#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic +#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode -#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L /* 1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) */ +#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L @@ -4594,55 +5610,59 @@ typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS { #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L -#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L /* If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. */ - /* If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback */ +#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. + //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L -#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L - -/* ucTableFormatRevision=1 */ -/* ucTableContentRevision=1 */ -typedef struct _ATOM_POWERMODE_INFO { - ULONG ulMiscInfo; /* The power level should be arranged in ascending order */ - ULONG ulReserved1; /* must set to 0 */ - ULONG ulReserved2; /* must set to 0 */ - USHORT usEngineClock; - USHORT usMemoryClock; - UCHAR ucVoltageDropIndex; /* index to GPIO table */ - UCHAR ucSelectedPanel_RefreshRate; /* panel refresh rate */ - UCHAR ucMinTemperature; - UCHAR ucMaxTemperature; - UCHAR ucNumPciELanes; /* number of PCIE lanes */ -} ATOM_POWERMODE_INFO; - -/* ucTableFormatRevision=2 */ -/* ucTableContentRevision=1 */ -typedef struct _ATOM_POWERMODE_INFO_V2 { - ULONG ulMiscInfo; /* The power level should be arranged in ascending order */ - ULONG ulMiscInfo2; - ULONG ulEngineClock; - ULONG ulMemoryClock; - UCHAR ucVoltageDropIndex; /* index to GPIO table */ - UCHAR ucSelectedPanel_RefreshRate; /* panel refresh rate */ - UCHAR ucMinTemperature; - UCHAR ucMaxTemperature; - UCHAR ucNumPciELanes; /* number of PCIE lanes */ -} ATOM_POWERMODE_INFO_V2; - -/* ucTableFormatRevision=2 */ -/* ucTableContentRevision=2 */ -typedef struct _ATOM_POWERMODE_INFO_V3 { - ULONG ulMiscInfo; /* The power level should be arranged in ascending order */ - ULONG ulMiscInfo2; - ULONG ulEngineClock; - ULONG ulMemoryClock; - UCHAR ucVoltageDropIndex; /* index to Core (VDDC) votage table */ - UCHAR ucSelectedPanel_RefreshRate; /* panel refresh rate */ - UCHAR ucMinTemperature; - UCHAR ucMaxTemperature; - UCHAR ucNumPciELanes; /* number of PCIE lanes */ - UCHAR ucVDDCI_VoltageDropIndex; /* index to VDDCI votage table */ -} ATOM_POWERMODE_INFO_V3; +#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L + +//ucTableFormatRevision=1 +//ucTableContentRevision=1 +typedef struct _ATOM_POWERMODE_INFO +{ + ULONG ulMiscInfo; //The power level should be arranged in ascending order + ULONG ulReserved1; // must set to 0 + ULONG ulReserved2; // must set to 0 + USHORT usEngineClock; + USHORT usMemoryClock; + UCHAR ucVoltageDropIndex; // index to GPIO table + UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate + UCHAR ucMinTemperature; + UCHAR ucMaxTemperature; + UCHAR ucNumPciELanes; // number of PCIE lanes +}ATOM_POWERMODE_INFO; + +//ucTableFormatRevision=2 +//ucTableContentRevision=1 +typedef struct _ATOM_POWERMODE_INFO_V2 +{ + ULONG ulMiscInfo; //The power level should be arranged in ascending order + ULONG ulMiscInfo2; + ULONG ulEngineClock; + ULONG ulMemoryClock; + UCHAR ucVoltageDropIndex; // index to GPIO table + UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate + UCHAR ucMinTemperature; + UCHAR ucMaxTemperature; + UCHAR ucNumPciELanes; // number of PCIE lanes +}ATOM_POWERMODE_INFO_V2; + +//ucTableFormatRevision=2 +//ucTableContentRevision=2 +typedef struct _ATOM_POWERMODE_INFO_V3 +{ + ULONG ulMiscInfo; //The power level should be arranged in ascending order + ULONG ulMiscInfo2; + ULONG ulEngineClock; + ULONG ulMemoryClock; + UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table + UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate + UCHAR ucMinTemperature; + UCHAR ucMaxTemperature; + UCHAR ucNumPciELanes; // number of PCIE lanes + UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table +}ATOM_POWERMODE_INFO_V3; + #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 @@ -4655,40 +5675,44 @@ typedef struct _ATOM_POWERMODE_INFO_V3 { #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 /* Andigilog */ - -typedef struct _ATOM_POWERPLAY_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucOverdriveThermalController; - UCHAR ucOverdriveI2cLine; - UCHAR ucOverdriveIntBitmap; - UCHAR ucOverdriveControllerAddress; - UCHAR ucSizeOfPowerModeEntry; - UCHAR ucNumOfPowerModeEntries; - ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; -} ATOM_POWERPLAY_INFO; - -typedef struct _ATOM_POWERPLAY_INFO_V2 { - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucOverdriveThermalController; - UCHAR ucOverdriveI2cLine; - UCHAR ucOverdriveIntBitmap; - UCHAR ucOverdriveControllerAddress; - UCHAR ucSizeOfPowerModeEntry; - UCHAR ucNumOfPowerModeEntries; - ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; -} ATOM_POWERPLAY_INFO_V2; - -typedef struct _ATOM_POWERPLAY_INFO_V3 { - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucOverdriveThermalController; - UCHAR ucOverdriveI2cLine; - UCHAR ucOverdriveIntBitmap; - UCHAR ucOverdriveControllerAddress; - UCHAR ucSizeOfPowerModeEntry; - UCHAR ucNumOfPowerModeEntries; - ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; -} ATOM_POWERPLAY_INFO_V3; +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog + + +typedef struct _ATOM_POWERPLAY_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucOverdriveThermalController; + UCHAR ucOverdriveI2cLine; + UCHAR ucOverdriveIntBitmap; + UCHAR ucOverdriveControllerAddress; + UCHAR ucSizeOfPowerModeEntry; + UCHAR ucNumOfPowerModeEntries; + ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; +}ATOM_POWERPLAY_INFO; + +typedef struct _ATOM_POWERPLAY_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucOverdriveThermalController; + UCHAR ucOverdriveI2cLine; + UCHAR ucOverdriveIntBitmap; + UCHAR ucOverdriveControllerAddress; + UCHAR ucSizeOfPowerModeEntry; + UCHAR ucNumOfPowerModeEntries; + ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; +}ATOM_POWERPLAY_INFO_V2; + +typedef struct _ATOM_POWERPLAY_INFO_V3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucOverdriveThermalController; + UCHAR ucOverdriveI2cLine; + UCHAR ucOverdriveIntBitmap; + UCHAR ucOverdriveControllerAddress; + UCHAR ucSizeOfPowerModeEntry; + UCHAR ucNumOfPowerModeEntries; + ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; +}ATOM_POWERPLAY_INFO_V3; /* New PPlib */ /**************************************************************************/ @@ -4873,40 +5897,42 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement. USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). - ULONG ulFlags; + ULONG ulFlags; } ATOM_PPLIB_RS780_CLOCK_INFO; -#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 -#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 -#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 -#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 +#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 +#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 +#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 +#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 -#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 -#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 -#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 +#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 +#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 +#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 /**************************************************************************/ -/* Following definitions are for compatiblity issue in different SW components. */ + +// Following definitions are for compatiblity issue in different SW components. #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 -#define Object_Info Object_Header +#define Object_Info Object_Header #define AdjustARB_SEQ MC_InitParameter #define VRAM_GPIO_DetectionInfo VoltageObjectInfo -#define ASIC_VDDCI_Info ASIC_ProfilingInfo +#define ASIC_VDDCI_Info ASIC_ProfilingInfo #define ASIC_MVDDQ_Info MemoryTrainingInfo -#define SS_Info PPLL_SS_Info +#define SS_Info PPLL_SS_Info #define ASIC_MVDDC_Info ASIC_InternalSS_Info #define DispDevicePriorityInfo SaveRestoreInfo #define DispOutInfo TV_VideoMode + #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE -/* New device naming, remove them when both DAL/VBIOS is ready */ +//New device naming, remove them when both DAL/VBIOS is ready #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS @@ -4921,7 +5947,7 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX - + #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) @@ -4939,7 +5965,7 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO #define ATOM_S3_DFP2I_ACTIVEb1 0x02 -#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE +#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE #define ATOM_S3_DFP2I_ACTIVE 0x00000200L @@ -4958,14 +5984,14 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L -#define TMDS1XEncoderControl DVOEncoderControl +#define TMDS1XEncoderControl DVOEncoderControl #define DFP1XOutputControl DVOOutputControl #define ExternalDFPOutputControl DFP1XOutputControl #define EnableExternalTMDS_Encoder TMDS1XEncoderControl #define DFP1IOutputControl TMDSAOutputControl -#define DFP2IOutputControl LVTMAOutputControl +#define DFP2IOutputControl LVTMAOutputControl #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION @@ -4974,7 +6000,7 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION #define ucDac1Standard ucDacStandard -#define ucDac2Standard ucDacStandard +#define ucDac2Standard ucDacStandard #define TMDS1EncoderControl TMDSAEncoderControl #define TMDS2EncoderControl LVTMAEncoderControl @@ -4984,12 +6010,56 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO #define CRT1OutputControl DAC1OutputControl #define CRT2OutputControl DAC2OutputControl -/* These two lines will be removed for sure in a few days, will follow up with Michael V. */ +//These two lines will be removed for sure in a few days, will follow up with Michael V. #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL -#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL +#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL + +//#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L +//#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE +//#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE +//#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE +//#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE + +#define ATOM_S6_ACC_REQ_TV2 0x00400000L +#define ATOM_DEVICE_TV2_INDEX 0x00000006 +#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) +#define ATOM_S0_TV2 0x00100000L +#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE +#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE + +// +#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L +#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L +#define ATOM_S2_TV1_DPMS_STATE 0x00040000L +#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L +#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L +#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L +#define ATOM_S2_TV2_DPMS_STATE 0x00400000L +#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L +#define ATOM_S2_CV_DPMS_STATE 0x01000000L +#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L +#define ATOM_S2_DFP4_DPMS_STATE 0x04000000L +#define ATOM_S2_DFP5_DPMS_STATE 0x08000000L + +#define ATOM_S2_CRT1_DPMS_STATEb2 0x01 +#define ATOM_S2_LCD1_DPMS_STATEb2 0x02 +#define ATOM_S2_TV1_DPMS_STATEb2 0x04 +#define ATOM_S2_DFP1_DPMS_STATEb2 0x08 +#define ATOM_S2_CRT2_DPMS_STATEb2 0x10 +#define ATOM_S2_LCD2_DPMS_STATEb2 0x20 +#define ATOM_S2_TV2_DPMS_STATEb2 0x40 +#define ATOM_S2_DFP2_DPMS_STATEb2 0x80 +#define ATOM_S2_CV_DPMS_STATEb3 0x01 +#define ATOM_S2_DFP3_DPMS_STATEb3 0x02 +#define ATOM_S2_DFP4_DPMS_STATEb3 0x04 +#define ATOM_S2_DFP5_DPMS_STATEb3 0x08 + +#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 +#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 +#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 /*********************************************************************************/ -#pragma pack() /* BIOS data must use byte aligment */ +#pragma pack() // BIOS data must use byte aligment #endif /* _ATOMBIOS_H */ -- cgit v1.2.3 From bcc1c2a1d22974215e39dc87ce746ba9a39223e5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 12 Jan 2010 17:54:34 -0500 Subject: drm/radeon/kms: add initial Evergreen support (Radeon HD 5xxx) This adds initial Evergreen KMS support, it doesn't include any acceleration features or interrupt handling yet. Major changes are DCE4 handling for PLLs for the > 2 crtcs. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/Makefile | 3 +- drivers/gpu/drm/radeon/atombios_crtc.c | 370 ++++++++++++-- drivers/gpu/drm/radeon/atombios_dp.c | 62 ++- drivers/gpu/drm/radeon/evergreen.c | 794 +++++++++++++++++++++++++++++++ drivers/gpu/drm/radeon/evergreen_reg.h | 176 +++++++ drivers/gpu/drm/radeon/radeon.h | 13 +- drivers/gpu/drm/radeon/radeon_asic.h | 50 ++ drivers/gpu/drm/radeon/radeon_atombios.c | 25 +- drivers/gpu/drm/radeon/radeon_clocks.c | 12 + drivers/gpu/drm/radeon/radeon_combios.c | 1 + drivers/gpu/drm/radeon/radeon_cursor.c | 37 +- drivers/gpu/drm/radeon/radeon_device.c | 20 +- drivers/gpu/drm/radeon/radeon_display.c | 42 +- drivers/gpu/drm/radeon/radeon_encoders.c | 241 +++++++--- drivers/gpu/drm/radeon/radeon_family.h | 5 + drivers/gpu/drm/radeon/radeon_mode.h | 6 +- drivers/gpu/drm/radeon/radeon_reg.h | 2 +- drivers/gpu/drm/radeon/rv770d.h | 2 + include/drm/drm_pciids.h | 35 ++ 19 files changed, 1775 insertions(+), 121 deletions(-) create mode 100644 drivers/gpu/drm/radeon/evergreen.c create mode 100644 drivers/gpu/drm/radeon/evergreen_reg.h (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 1cc7b937b1ea..83c59079193b 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -54,7 +54,8 @@ radeon-y += radeon_device.o radeon_kms.o \ radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \ r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ - r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o + r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \ + evergreen.o radeon-$(CONFIG_COMPAT) += radeon_ioc32.o diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index bb45517719ae..7e7c0b32bb65 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -249,13 +249,17 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) if (ASIC_IS_DCE3(rdev)) atombios_enable_crtc_memreq(crtc, 1); atombios_blank_crtc(crtc, 0); - drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); + /* XXX re-enable when interrupt support is added */ + if (!ASIC_IS_DCE4(rdev)) + drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); radeon_crtc_load_lut(crtc); break; case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_OFF: - drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); + /* XXX re-enable when interrupt support is added */ + if (!ASIC_IS_DCE4(rdev)) + drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); atombios_blank_crtc(crtc, 1); if (ASIC_IS_DCE3(rdev)) atombios_enable_crtc_memreq(crtc, 0); @@ -367,6 +371,10 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable) uint16_t percentage = 0; uint8_t type = 0, step = 0, delay = 0, range = 0; + /* XXX add ss support for DCE4 */ + if (ASIC_IS_DCE4(rdev)) + return; + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { if (encoder->crtc == crtc) { radeon_encoder = to_radeon_encoder(encoder); @@ -411,6 +419,7 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable) union adjust_pixel_clock { ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; + ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; }; static u32 atombios_adjust_pll(struct drm_crtc *crtc, @@ -422,6 +431,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, struct drm_encoder *encoder = NULL; struct radeon_encoder *radeon_encoder = NULL; u32 adjusted_clock = mode->clock; + int encoder_mode = 0; /* reset the pll flags */ pll->flags = 0; @@ -459,6 +469,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { if (encoder->crtc == crtc) { radeon_encoder = to_radeon_encoder(encoder); + encoder_mode = atombios_get_encoder_mode(encoder); if (ASIC_IS_AVIVO(rdev)) { /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) @@ -484,14 +495,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, */ if (ASIC_IS_DCE3(rdev)) { union adjust_pixel_clock args; - struct radeon_encoder_atom_dig *dig; u8 frev, crev; int index; - if (!radeon_encoder->enc_priv) - return adjusted_clock; - dig = radeon_encoder->enc_priv; - index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); @@ -505,12 +511,51 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, case 2: args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); args.v1.ucTransmitterID = radeon_encoder->encoder_id; - args.v1.ucEncodeMode = atombios_get_encoder_mode(encoder); + args.v1.ucEncodeMode = encoder_mode; atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; break; + case 3: + args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); + args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; + args.v3.sInput.ucEncodeMode = encoder_mode; + args.v3.sInput.ucDispPllConfig = 0; + if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { + struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; + + if (encoder_mode == ATOM_ENCODER_MODE_DP) + args.v3.sInput.ucDispPllConfig |= + DISPPLL_CONFIG_COHERENT_MODE; + else { + if (dig->coherent_mode) + args.v3.sInput.ucDispPllConfig |= + DISPPLL_CONFIG_COHERENT_MODE; + if (mode->clock > 165000) + args.v3.sInput.ucDispPllConfig |= + DISPPLL_CONFIG_DUAL_LINK; + } + } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { + /* may want to enable SS on DP/eDP eventually */ + args.v3.sInput.ucDispPllConfig |= + DISPPLL_CONFIG_SS_ENABLE; + if (mode->clock > 165000) + args.v3.sInput.ucDispPllConfig |= + DISPPLL_CONFIG_DUAL_LINK; + } + atom_execute_table(rdev->mode_info.atom_context, + index, (uint32_t *)&args); + adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; + if (args.v3.sOutput.ucRefDiv) { + pll->flags |= RADEON_PLL_USE_REF_DIV; + pll->reference_div = args.v3.sOutput.ucRefDiv; + } + if (args.v3.sOutput.ucPostDiv) { + pll->flags |= RADEON_PLL_USE_POST_DIV; + pll->post_div = args.v3.sOutput.ucPostDiv; + } + break; default: DRM_ERROR("Unknown table version %d %d\n", frev, crev); return adjusted_clock; @@ -529,9 +574,47 @@ union set_pixel_clock { PIXEL_CLOCK_PARAMETERS v1; PIXEL_CLOCK_PARAMETERS_V2 v2; PIXEL_CLOCK_PARAMETERS_V3 v3; + PIXEL_CLOCK_PARAMETERS_V5 v5; }; -void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) +static void atombios_crtc_set_dcpll(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct radeon_device *rdev = dev->dev_private; + u8 frev, crev; + int index; + union set_pixel_clock args; + + memset(&args, 0, sizeof(args)); + + index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); + atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, + &crev); + + switch (frev) { + case 1: + switch (crev) { + case 5: + /* if the default dcpll clock is specified, + * SetPixelClock provides the dividers + */ + args.v5.ucCRTC = ATOM_CRTC_INVALID; + args.v5.usPixelClock = rdev->clock.default_dispclk; + args.v5.ucPpll = ATOM_DCPLL; + break; + default: + DRM_ERROR("Unknown table version %d %d\n", frev, crev); + return; + } + break; + default: + DRM_ERROR("Unknown table version %d %d\n", frev, crev); + return; + } + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); +} + +static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct drm_device *dev = crtc->dev; @@ -545,12 +628,14 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; struct radeon_pll *pll; u32 adjusted_clock; + int encoder_mode = 0; memset(&args, 0, sizeof(args)); list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { if (encoder->crtc == crtc) { radeon_encoder = to_radeon_encoder(encoder); + encoder_mode = atombios_get_encoder_mode(encoder); break; } } @@ -558,10 +643,18 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) if (!radeon_encoder) return; - if (radeon_crtc->crtc_id == 0) + switch (radeon_crtc->pll_id) { + case ATOM_PPLL1: pll = &rdev->clock.p1pll; - else + break; + case ATOM_PPLL2: pll = &rdev->clock.p2pll; + break; + case ATOM_DCPLL: + case ATOM_PPLL_INVALID: + pll = &rdev->clock.dcpll; + break; + } /* adjust pixel clock as needed */ adjusted_clock = atombios_adjust_pll(crtc, mode, pll); @@ -582,8 +675,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) args.v1.usFbDiv = cpu_to_le16(fb_div); args.v1.ucFracFbDiv = frac_fb_div; args.v1.ucPostDiv = post_div; - args.v1.ucPpll = - radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; + args.v1.ucPpll = radeon_crtc->pll_id; args.v1.ucCRTC = radeon_crtc->crtc_id; args.v1.ucRefDivSrc = 1; break; @@ -593,8 +685,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) args.v2.usFbDiv = cpu_to_le16(fb_div); args.v2.ucFracFbDiv = frac_fb_div; args.v2.ucPostDiv = post_div; - args.v2.ucPpll = - radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; + args.v2.ucPpll = radeon_crtc->pll_id; args.v2.ucCRTC = radeon_crtc->crtc_id; args.v2.ucRefDivSrc = 1; break; @@ -604,12 +695,22 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) args.v3.usFbDiv = cpu_to_le16(fb_div); args.v3.ucFracFbDiv = frac_fb_div; args.v3.ucPostDiv = post_div; - args.v3.ucPpll = - radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; - args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2); + args.v3.ucPpll = radeon_crtc->pll_id; + args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2); args.v3.ucTransmitterId = radeon_encoder->encoder_id; - args.v3.ucEncoderMode = - atombios_get_encoder_mode(encoder); + args.v3.ucEncoderMode = encoder_mode; + break; + case 5: + args.v5.ucCRTC = radeon_crtc->crtc_id; + args.v5.usPixelClock = cpu_to_le16(mode->clock / 10); + args.v5.ucRefDiv = ref_div; + args.v5.usFbDiv = cpu_to_le16(fb_div); + args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); + args.v5.ucPostDiv = post_div; + args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ + args.v5.ucTransmitterID = radeon_encoder->encoder_id; + args.v5.ucEncoderMode = encoder_mode; + args.v5.ucPpll = radeon_crtc->pll_id; break; default: DRM_ERROR("Unknown table version %d %d\n", frev, crev); @@ -624,6 +725,140 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); } +static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y, + struct drm_framebuffer *old_fb) +{ + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_framebuffer *radeon_fb; + struct drm_gem_object *obj; + struct radeon_bo *rbo; + uint64_t fb_location; + uint32_t fb_format, fb_pitch_pixels, tiling_flags; + int r; + + /* no fb bound */ + if (!crtc->fb) { + DRM_DEBUG("No FB bound\n"); + return 0; + } + + radeon_fb = to_radeon_framebuffer(crtc->fb); + + /* Pin framebuffer & get tilling informations */ + obj = radeon_fb->obj; + rbo = obj->driver_private; + r = radeon_bo_reserve(rbo, false); + if (unlikely(r != 0)) + return r; + r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); + if (unlikely(r != 0)) { + radeon_bo_unreserve(rbo); + return -EINVAL; + } + radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); + radeon_bo_unreserve(rbo); + + switch (crtc->fb->bits_per_pixel) { + case 8: + fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | + EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); + break; + case 15: + fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | + EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); + break; + case 16: + fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | + EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); + break; + case 24: + case 32: + fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | + EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); + break; + default: + DRM_ERROR("Unsupported screen depth %d\n", + crtc->fb->bits_per_pixel); + return -EINVAL; + } + + switch (radeon_crtc->crtc_id) { + case 0: + WREG32(AVIVO_D1VGA_CONTROL, 0); + break; + case 1: + WREG32(AVIVO_D2VGA_CONTROL, 0); + break; + case 2: + WREG32(EVERGREEN_D3VGA_CONTROL, 0); + break; + case 3: + WREG32(EVERGREEN_D4VGA_CONTROL, 0); + break; + case 4: + WREG32(EVERGREEN_D5VGA_CONTROL, 0); + break; + case 5: + WREG32(EVERGREEN_D6VGA_CONTROL, 0); + break; + default: + break; + } + + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, + upper_32_bits(fb_location)); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, + upper_32_bits(fb_location)); + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, + (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, + (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); + WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); + + WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); + WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); + WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); + WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); + WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); + WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); + + fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); + WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); + WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); + + WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, + crtc->mode.vdisplay); + x &= ~3; + y &= ~1; + WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, + (x << 16) | y); + WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, + (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); + + if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) + WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, + EVERGREEN_INTERLEAVE_EN); + else + WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); + + if (old_fb && old_fb != crtc->fb) { + radeon_fb = to_radeon_framebuffer(old_fb); + rbo = radeon_fb->obj->driver_private; + r = radeon_bo_reserve(rbo, false); + if (unlikely(r != 0)) + return r; + radeon_bo_unpin(rbo); + radeon_bo_unreserve(rbo); + } + + /* Bytes per pixel may have changed */ + radeon_bandwidth_update(rdev); + + return 0; +} + static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { @@ -761,7 +996,9 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, struct drm_device *dev = crtc->dev; struct radeon_device *rdev = dev->dev_private; - if (ASIC_IS_AVIVO(rdev)) + if (ASIC_IS_DCE4(rdev)) + return evergreen_crtc_set_base(crtc, x, y, old_fb); + else if (ASIC_IS_AVIVO(rdev)) return avivo_crtc_set_base(crtc, x, y, old_fb); else return radeon_crtc_set_base(crtc, x, y, old_fb); @@ -791,6 +1028,46 @@ static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) } } +static int radeon_atom_pick_pll(struct drm_crtc *crtc) +{ + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct radeon_device *rdev = dev->dev_private; + struct drm_encoder *test_encoder; + struct drm_crtc *test_crtc; + uint32_t pll_in_use = 0; + + if (ASIC_IS_DCE4(rdev)) { + /* if crtc is driving DP and we have an ext clock, use that */ + list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { + if (test_encoder->crtc && (test_encoder->crtc == crtc)) { + if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { + if (rdev->clock.dp_extclk) + return ATOM_PPLL_INVALID; + } + } + } + + /* otherwise, pick one of the plls */ + list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { + struct radeon_crtc *radeon_test_crtc; + + if (crtc == test_crtc) + continue; + + radeon_test_crtc = to_radeon_crtc(test_crtc); + if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && + (radeon_test_crtc->pll_id <= ATOM_PPLL2)) + pll_in_use |= (1 << radeon_test_crtc->pll_id); + } + if (!(pll_in_use & 1)) + return ATOM_PPLL1; + return ATOM_PPLL2; + } else + return radeon_crtc->crtc_id; + +} + int atombios_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode, @@ -802,19 +1079,27 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, /* TODO color tiling */ + /* pick pll */ + radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); + atombios_set_ss(crtc, 0); + /* always set DCPLL */ + if (ASIC_IS_DCE4(rdev)) + atombios_crtc_set_dcpll(crtc); atombios_crtc_set_pll(crtc, adjusted_mode); atombios_set_ss(crtc, 1); - atombios_crtc_set_timing(crtc, adjusted_mode); - if (ASIC_IS_AVIVO(rdev)) - atombios_crtc_set_base(crtc, x, y, old_fb); + if (ASIC_IS_DCE4(rdev)) + atombios_set_crtc_dtd_timing(crtc, adjusted_mode); + else if (ASIC_IS_AVIVO(rdev)) + atombios_crtc_set_timing(crtc, adjusted_mode); else { + atombios_crtc_set_timing(crtc, adjusted_mode); if (radeon_crtc->crtc_id == 0) atombios_set_crtc_dtd_timing(crtc, adjusted_mode); - atombios_crtc_set_base(crtc, x, y, old_fb); radeon_legacy_atom_fixup(crtc); } + atombios_crtc_set_base(crtc, x, y, old_fb); atombios_overscan_setup(crtc, mode, adjusted_mode); atombios_scaler_setup(crtc); return 0; @@ -854,8 +1139,37 @@ static const struct drm_crtc_helper_funcs atombios_helper_funcs = { void radeon_atombios_init_crtc(struct drm_device *dev, struct radeon_crtc *radeon_crtc) { - if (radeon_crtc->crtc_id == 1) - radeon_crtc->crtc_offset = - AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; + struct radeon_device *rdev = dev->dev_private; + + if (ASIC_IS_DCE4(rdev)) { + switch (radeon_crtc->crtc_id) { + case 0: + default: + radeon_crtc->crtc_id = EVERGREEN_CRTC0_REGISTER_OFFSET; + break; + case 1: + radeon_crtc->crtc_id = EVERGREEN_CRTC1_REGISTER_OFFSET; + break; + case 2: + radeon_crtc->crtc_id = EVERGREEN_CRTC2_REGISTER_OFFSET; + break; + case 3: + radeon_crtc->crtc_id = EVERGREEN_CRTC3_REGISTER_OFFSET; + break; + case 4: + radeon_crtc->crtc_id = EVERGREEN_CRTC4_REGISTER_OFFSET; + break; + case 5: + radeon_crtc->crtc_id = EVERGREEN_CRTC5_REGISTER_OFFSET; + break; + } + } else { + if (radeon_crtc->crtc_id == 1) + radeon_crtc->crtc_offset = + AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; + else + radeon_crtc->crtc_offset = 0; + } + radeon_crtc->pll_id = -1; drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); } diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index 71060114d5de..0b6f2cef1c52 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c @@ -321,6 +321,10 @@ static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], train_set[lane] = v | p; } +union aux_channel_transaction { + PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; + PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; +}; /* radeon aux chan functions */ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes, @@ -329,7 +333,7 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes, { struct drm_device *dev = chan->dev; struct radeon_device *rdev = dev->dev_private; - PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args; + union aux_channel_transaction args; int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); unsigned char *base; @@ -339,29 +343,31 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes, memcpy(base, req_bytes, num_bytes); - args.lpAuxRequest = 0; - args.lpDataOut = 16; - args.ucDataOutLen = 0; - args.ucChannelID = chan->rec.i2c_id; - args.ucDelay = delay / 10; + args.v1.lpAuxRequest = 0; + args.v1.lpDataOut = 16; + args.v1.ucDataOutLen = 0; + args.v1.ucChannelID = chan->rec.i2c_id; + args.v1.ucDelay = delay / 10; + if (ASIC_IS_DCE4(rdev)) + args.v2.ucHPD_ID = chan->rec.hpd_id; atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); - if (args.ucReplyStatus) { + if (args.v1.ucReplyStatus) { DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n", req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], - chan->rec.i2c_id, args.ucReplyStatus); + chan->rec.i2c_id, args.v1.ucReplyStatus); return false; } - if (args.ucDataOutLen && read_byte && read_buf_len) { - if (read_buf_len < args.ucDataOutLen) { + if (args.v1.ucDataOutLen && read_byte && read_buf_len) { + if (read_buf_len < args.v1.ucDataOutLen) { DRM_ERROR("Buffer to small for return answer %d %d\n", - read_buf_len, args.ucDataOutLen); + read_buf_len, args.v1.ucDataOutLen); return false; } { - int len = min(read_buf_len, args.ucDataOutLen); + int len = min(read_buf_len, args.v1.ucDataOutLen); memcpy(read_byte, base + 16, len); } } @@ -622,12 +628,19 @@ void dp_link_train(struct drm_encoder *encoder, dp_set_link_bw_lanes(radeon_connector, link_configuration); /* disable downspread on the sink */ dp_set_downspread(radeon_connector, 0); - /* start training on the source */ - radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START, - dig_connector->dp_clock, enc_id, 0); - /* set training pattern 1 on the source */ - radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, - dig_connector->dp_clock, enc_id, 0); + if (ASIC_IS_DCE4(rdev)) { + /* start training on the source */ + atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_START); + /* set training pattern 1 on the source */ + atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1); + } else { + /* start training on the source */ + radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START, + dig_connector->dp_clock, enc_id, 0); + /* set training pattern 1 on the source */ + radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, + dig_connector->dp_clock, enc_id, 0); + } /* set initial vs/emph */ memset(train_set, 0, 4); @@ -687,8 +700,11 @@ void dp_link_train(struct drm_encoder *encoder, /* set training pattern 2 on the sink */ dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2); /* set training pattern 2 on the source */ - radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, - dig_connector->dp_clock, enc_id, 1); + if (ASIC_IS_DCE4(rdev)) + atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2); + else + radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, + dig_connector->dp_clock, enc_id, 1); /* channel equalization loop */ tries = 0; @@ -725,7 +741,11 @@ void dp_link_train(struct drm_encoder *encoder, >> DP_TRAIN_PRE_EMPHASIS_SHIFT); /* disable the training pattern on the sink */ - dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE); + if (ASIC_IS_DCE4(rdev)) + atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE); + else + radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, + dig_connector->dp_clock, enc_id, 0); radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, dig_connector->dp_clock, enc_id, 0); diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c new file mode 100644 index 000000000000..c2f9752e4ee0 --- /dev/null +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -0,0 +1,794 @@ +/* + * Copyright 2010 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ +#include +#include +#include "drmP.h" +#include "radeon.h" +#include "radeon_drm.h" +#include "rv770d.h" +#include "atom.h" +#include "avivod.h" +#include "evergreen_reg.h" + +static void evergreen_gpu_init(struct radeon_device *rdev); +void evergreen_fini(struct radeon_device *rdev); + +bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) +{ + bool connected = false; + /* XXX */ + return connected; +} + +void evergreen_hpd_set_polarity(struct radeon_device *rdev, + enum radeon_hpd_id hpd) +{ + /* XXX */ +} + +void evergreen_hpd_init(struct radeon_device *rdev) +{ + /* XXX */ +} + + +void evergreen_bandwidth_update(struct radeon_device *rdev) +{ + /* XXX */ +} + +void evergreen_hpd_fini(struct radeon_device *rdev) +{ + /* XXX */ +} + +static int evergreen_mc_wait_for_idle(struct radeon_device *rdev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < rdev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(SRBM_STATUS) & 0x1F00; + if (!tmp) + return 0; + udelay(1); + } + return -1; +} + +/* + * GART + */ +int evergreen_pcie_gart_enable(struct radeon_device *rdev) +{ + u32 tmp; + int r, i; + + if (rdev->gart.table.vram.robj == NULL) { + dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); + return -EINVAL; + } + r = radeon_gart_table_vram_pin(rdev); + if (r) + return r; + /* Setup L2 cache */ + WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | + ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | + EFFECTIVE_L2_QUEUE_SIZE(7)); + WREG32(VM_L2_CNTL2, 0); + WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); + /* Setup TLB control */ + tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | + SYSTEM_ACCESS_MODE_NOT_IN_SYS | + SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | + EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); + WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); + WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); + WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); + WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); + WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, + (u32)(rdev->dummy_page.addr >> 12)); + for (i = 1; i < 7; i++) + WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); + + r600_pcie_gart_tlb_flush(rdev); + rdev->gart.ready = true; + return 0; +} + +void evergreen_pcie_gart_disable(struct radeon_device *rdev) +{ + u32 tmp; + int i, r; + + /* Disable all tables */ + for (i = 0; i < 7; i++) + WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); + + /* Setup L2 cache */ + WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | + EFFECTIVE_L2_QUEUE_SIZE(7)); + WREG32(VM_L2_CNTL2, 0); + WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); + /* Setup TLB control */ + tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); + WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); + if (rdev->gart.table.vram.robj) { + r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); + if (likely(r == 0)) { + radeon_bo_kunmap(rdev->gart.table.vram.robj); + radeon_bo_unpin(rdev->gart.table.vram.robj); + radeon_bo_unreserve(rdev->gart.table.vram.robj); + } + } +} + +void evergreen_pcie_gart_fini(struct radeon_device *rdev) +{ + evergreen_pcie_gart_disable(rdev); + radeon_gart_table_vram_free(rdev); + radeon_gart_fini(rdev); +} + + +void evergreen_agp_enable(struct radeon_device *rdev) +{ + u32 tmp; + int i; + + /* Setup L2 cache */ + WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | + ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | + EFFECTIVE_L2_QUEUE_SIZE(7)); + WREG32(VM_L2_CNTL2, 0); + WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); + /* Setup TLB control */ + tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | + SYSTEM_ACCESS_MODE_NOT_IN_SYS | + SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | + EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); + WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); + for (i = 0; i < 7; i++) + WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); +} + +static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) +{ + save->vga_control[0] = RREG32(D1VGA_CONTROL); + save->vga_control[1] = RREG32(D2VGA_CONTROL); + save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); + save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); + save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); + save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); + save->vga_render_control = RREG32(VGA_RENDER_CONTROL); + save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); + save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); + save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); + save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); + save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); + save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); + save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); + + /* Stop all video */ + WREG32(VGA_RENDER_CONTROL, 0); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); + WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); + + WREG32(D1VGA_CONTROL, 0); + WREG32(D2VGA_CONTROL, 0); + WREG32(EVERGREEN_D3VGA_CONTROL, 0); + WREG32(EVERGREEN_D4VGA_CONTROL, 0); + WREG32(EVERGREEN_D5VGA_CONTROL, 0); + WREG32(EVERGREEN_D6VGA_CONTROL, 0); +} + +static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) +{ + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, + upper_32_bits(rdev->mc.vram_start)); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, + upper_32_bits(rdev->mc.vram_start)); + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, + (u32)rdev->mc.vram_start); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, + (u32)rdev->mc.vram_start); + + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, + upper_32_bits(rdev->mc.vram_start)); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, + upper_32_bits(rdev->mc.vram_start)); + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, + (u32)rdev->mc.vram_start); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, + (u32)rdev->mc.vram_start); + + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, + upper_32_bits(rdev->mc.vram_start)); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, + upper_32_bits(rdev->mc.vram_start)); + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, + (u32)rdev->mc.vram_start); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, + (u32)rdev->mc.vram_start); + + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, + upper_32_bits(rdev->mc.vram_start)); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, + upper_32_bits(rdev->mc.vram_start)); + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, + (u32)rdev->mc.vram_start); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, + (u32)rdev->mc.vram_start); + + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, + upper_32_bits(rdev->mc.vram_start)); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, + upper_32_bits(rdev->mc.vram_start)); + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, + (u32)rdev->mc.vram_start); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, + (u32)rdev->mc.vram_start); + + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, + upper_32_bits(rdev->mc.vram_start)); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, + upper_32_bits(rdev->mc.vram_start)); + WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, + (u32)rdev->mc.vram_start); + WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, + (u32)rdev->mc.vram_start); + + WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); + WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); + /* Unlock host access */ + WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); + mdelay(1); + /* Restore video state */ + WREG32(D1VGA_CONTROL, save->vga_control[0]); + WREG32(D2VGA_CONTROL, save->vga_control[1]); + WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); + WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); + WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); + WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); + WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); + WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); + WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); + WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); + WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); + WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); + WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); + WREG32(VGA_RENDER_CONTROL, save->vga_render_control); +} + +static void evergreen_mc_program(struct radeon_device *rdev) +{ + struct evergreen_mc_save save; + u32 tmp; + int i, j; + + /* Initialize HDP */ + for (i = 0, j = 0; i < 32; i++, j += 0x18) { + WREG32((0x2c14 + j), 0x00000000); + WREG32((0x2c18 + j), 0x00000000); + WREG32((0x2c1c + j), 0x00000000); + WREG32((0x2c20 + j), 0x00000000); + WREG32((0x2c24 + j), 0x00000000); + } + WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); + + evergreen_mc_stop(rdev, &save); + if (evergreen_mc_wait_for_idle(rdev)) { + dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); + } + /* Lockout access through VGA aperture*/ + WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); + /* Update configuration */ + if (rdev->flags & RADEON_IS_AGP) { + if (rdev->mc.vram_start < rdev->mc.gtt_start) { + /* VRAM before AGP */ + WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, + rdev->mc.vram_start >> 12); + WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, + rdev->mc.gtt_end >> 12); + } else { + /* VRAM after AGP */ + WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, + rdev->mc.gtt_start >> 12); + WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, + rdev->mc.vram_end >> 12); + } + } else { + WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, + rdev->mc.vram_start >> 12); + WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, + rdev->mc.vram_end >> 12); + } + WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); + tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; + tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); + WREG32(MC_VM_FB_LOCATION, tmp); + WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); + WREG32(HDP_NONSURFACE_INFO, (2 << 7)); + WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); + if (rdev->flags & RADEON_IS_AGP) { + WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); + WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); + WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); + } else { + WREG32(MC_VM_AGP_BASE, 0); + WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); + WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); + } + if (evergreen_mc_wait_for_idle(rdev)) { + dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); + } + evergreen_mc_resume(rdev, &save); + /* we need to own VRAM, so turn off the VGA renderer here + * to stop it overwriting our objects */ + rv515_vga_render_disable(rdev); +} + +#if 0 +/* + * CP. + */ +static void evergreen_cp_stop(struct radeon_device *rdev) +{ + /* XXX */ +} + + +static int evergreen_cp_load_microcode(struct radeon_device *rdev) +{ + /* XXX */ + + return 0; +} + + +/* + * Core functions + */ +static u32 evergreen_get_tile_pipe_to_backend_map(u32 num_tile_pipes, + u32 num_backends, + u32 backend_disable_mask) +{ + u32 backend_map = 0; + + return backend_map; +} +#endif + +static void evergreen_gpu_init(struct radeon_device *rdev) +{ + /* XXX */ +} + +int evergreen_mc_init(struct radeon_device *rdev) +{ + fixed20_12 a; + u32 tmp; + int chansize, numchan; + int r; + + /* Get VRAM informations */ + rdev->mc.vram_is_ddr = true; + tmp = RREG32(MC_ARB_RAMCFG); + if (tmp & CHANSIZE_OVERRIDE) { + chansize = 16; + } else if (tmp & CHANSIZE_MASK) { + chansize = 64; + } else { + chansize = 32; + } + tmp = RREG32(MC_SHARED_CHMAP); + switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { + case 0: + default: + numchan = 1; + break; + case 1: + numchan = 2; + break; + case 2: + numchan = 4; + break; + case 3: + numchan = 8; + break; + } + rdev->mc.vram_width = numchan * chansize; + /* Could aper size report 0 ? */ + rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); + rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); + /* Setup GPU memory space */ + /* size in MB on evergreen */ + rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; + rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; + + if (rdev->mc.mc_vram_size > rdev->mc.aper_size) + rdev->mc.mc_vram_size = rdev->mc.aper_size; + + if (rdev->mc.real_vram_size > rdev->mc.aper_size) + rdev->mc.real_vram_size = rdev->mc.aper_size; + + if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) + return r; + /* gtt_size is setup by radeon_agp_init */ + rdev->mc.gtt_location = rdev->mc.agp_base; + tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; + /* Try to put vram before or after AGP because we + * we want SYSTEM_APERTURE to cover both VRAM and + * AGP so that GPU can catch out of VRAM/AGP access + */ + if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { + /* Enought place before */ + rdev->mc.vram_location = rdev->mc.gtt_location - + rdev->mc.mc_vram_size; + } else if (tmp > rdev->mc.mc_vram_size) { + /* Enought place after */ + rdev->mc.vram_location = rdev->mc.gtt_location + + rdev->mc.gtt_size; + } else { + /* Try to setup VRAM then AGP might not + * not work on some card + */ + rdev->mc.vram_location = 0x00000000UL; + rdev->mc.gtt_location = rdev->mc.mc_vram_size; + } + } else { + rdev->mc.vram_location = 0x00000000UL; + rdev->mc.gtt_location = rdev->mc.mc_vram_size; + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; + } + rdev->mc.vram_start = rdev->mc.vram_location; + rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; + rdev->mc.gtt_start = rdev->mc.gtt_location; + rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; + /* FIXME: we should enforce default clock in case GPU is not in + * default setup + */ + a.full = rfixed_const(100); + rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); + rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); + return 0; +} +int evergreen_gpu_reset(struct radeon_device *rdev) +{ + /* FIXME: implement for evergreen */ + return 0; +} + +static int evergreen_startup(struct radeon_device *rdev) +{ +#if 0 + int r; + + if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { + r = r600_init_microcode(rdev); + if (r) { + DRM_ERROR("Failed to load firmware!\n"); + return r; + } + } +#endif + evergreen_mc_program(rdev); +#if 0 + if (rdev->flags & RADEON_IS_AGP) { + evergreem_agp_enable(rdev); + } else { + r = evergreen_pcie_gart_enable(rdev); + if (r) + return r; + } +#endif + evergreen_gpu_init(rdev); +#if 0 + if (!rdev->r600_blit.shader_obj) { + r = r600_blit_init(rdev); + if (r) { + DRM_ERROR("radeon: failed blitter (%d).\n", r); + return r; + } + } + + r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); + if (unlikely(r != 0)) + return r; + r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, + &rdev->r600_blit.shader_gpu_addr); + radeon_bo_unreserve(rdev->r600_blit.shader_obj); + if (r) { + DRM_ERROR("failed to pin blit object %d\n", r); + return r; + } + + /* Enable IRQ */ + r = r600_irq_init(rdev); + if (r) { + DRM_ERROR("radeon: IH init failed (%d).\n", r); + radeon_irq_kms_fini(rdev); + return r; + } + r600_irq_set(rdev); + + r = radeon_ring_init(rdev, rdev->cp.ring_size); + if (r) + return r; + r = evergreen_cp_load_microcode(rdev); + if (r) + return r; + r = r600_cp_resume(rdev); + if (r) + return r; + /* write back buffer are not vital so don't worry about failure */ + r600_wb_enable(rdev); +#endif + return 0; +} + +int evergreen_resume(struct radeon_device *rdev) +{ + int r; + + /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, + * posting will perform necessary task to bring back GPU into good + * shape. + */ + /* post card */ + atom_asic_init(rdev->mode_info.atom_context); + /* Initialize clocks */ + r = radeon_clocks_init(rdev); + if (r) { + return r; + } + + r = evergreen_startup(rdev); + if (r) { + DRM_ERROR("r600 startup failed on resume\n"); + return r; + } +#if 0 + r = r600_ib_test(rdev); + if (r) { + DRM_ERROR("radeon: failled testing IB (%d).\n", r); + return r; + } +#endif + return r; + +} + +int evergreen_suspend(struct radeon_device *rdev) +{ +#if 0 + int r; + + /* FIXME: we should wait for ring to be empty */ + r700_cp_stop(rdev); + rdev->cp.ready = false; + r600_wb_disable(rdev); + evergreen_pcie_gart_disable(rdev); + /* unpin shaders bo */ + r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); + if (likely(r == 0)) { + radeon_bo_unpin(rdev->r600_blit.shader_obj); + radeon_bo_unreserve(rdev->r600_blit.shader_obj); + } +#endif + return 0; +} + +static bool evergreen_card_posted(struct radeon_device *rdev) +{ + u32 reg; + + /* first check CRTCs */ + reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | + RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | + RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | + RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | + RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | + RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); + if (reg & EVERGREEN_CRTC_MASTER_EN) + return true; + + /* then check MEM_SIZE, in case the crtcs are off */ + if (RREG32(CONFIG_MEMSIZE)) + return true; + + return false; +} + +/* Plan is to move initialization in that function and use + * helper function so that radeon_device_init pretty much + * do nothing more than calling asic specific function. This + * should also allow to remove a bunch of callback function + * like vram_info. + */ +int evergreen_init(struct radeon_device *rdev) +{ + int r; + + r = radeon_dummy_page_init(rdev); + if (r) + return r; + /* This don't do much */ + r = radeon_gem_init(rdev); + if (r) + return r; + /* Read BIOS */ + if (!radeon_get_bios(rdev)) { + if (ASIC_IS_AVIVO(rdev)) + return -EINVAL; + } + /* Must be an ATOMBIOS */ + if (!rdev->is_atom_bios) { + dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); + return -EINVAL; + } + r = radeon_atombios_init(rdev); + if (r) + return r; + /* Post card if necessary */ + if (!evergreen_card_posted(rdev)) { + if (!rdev->bios) { + dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); + return -EINVAL; + } + DRM_INFO("GPU not posted. posting now...\n"); + atom_asic_init(rdev->mode_info.atom_context); + } + /* Initialize scratch registers */ + r600_scratch_init(rdev); + /* Initialize surface registers */ + radeon_surface_init(rdev); + /* Initialize clocks */ + radeon_get_clock_info(rdev->ddev); + r = radeon_clocks_init(rdev); + if (r) + return r; + /* Initialize power management */ + radeon_pm_init(rdev); + /* Fence driver */ + r = radeon_fence_driver_init(rdev); + if (r) + return r; + r = evergreen_mc_init(rdev); + if (r) + return r; + /* Memory manager */ + r = radeon_bo_init(rdev); + if (r) + return r; +#if 0 + r = radeon_irq_kms_init(rdev); + if (r) + return r; + + rdev->cp.ring_obj = NULL; + r600_ring_init(rdev, 1024 * 1024); + + rdev->ih.ring_obj = NULL; + r600_ih_ring_init(rdev, 64 * 1024); + + r = r600_pcie_gart_init(rdev); + if (r) + return r; +#endif + rdev->accel_working = false; + r = evergreen_startup(rdev); + if (r) { + evergreen_suspend(rdev); + /*r600_wb_fini(rdev);*/ + /*radeon_ring_fini(rdev);*/ + /*evergreen_pcie_gart_fini(rdev);*/ + rdev->accel_working = false; + } + if (rdev->accel_working) { + r = radeon_ib_pool_init(rdev); + if (r) { + DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); + rdev->accel_working = false; + } + r = r600_ib_test(rdev); + if (r) { + DRM_ERROR("radeon: failed testing IB (%d).\n", r); + rdev->accel_working = false; + } + } + return 0; +} + +void evergreen_fini(struct radeon_device *rdev) +{ + evergreen_suspend(rdev); +#if 0 + r600_blit_fini(rdev); + r600_irq_fini(rdev); + radeon_irq_kms_fini(rdev); + radeon_ring_fini(rdev); + r600_wb_fini(rdev); + evergreen_pcie_gart_fini(rdev); +#endif + radeon_gem_fini(rdev); + radeon_fence_driver_fini(rdev); + radeon_clocks_fini(rdev); + radeon_agp_fini(rdev); + radeon_bo_fini(rdev); + radeon_atombios_fini(rdev); + kfree(rdev->bios); + rdev->bios = NULL; + radeon_dummy_page_fini(rdev); +} diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h new file mode 100644 index 000000000000..f7c7c9643433 --- /dev/null +++ b/drivers/gpu/drm/radeon/evergreen_reg.h @@ -0,0 +1,176 @@ +/* + * Copyright 2010 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ +#ifndef __EVERGREEN_REG_H__ +#define __EVERGREEN_REG_H__ + +/* evergreen */ +#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310 +#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324 +#define EVERGREEN_D3VGA_CONTROL 0x3e0 +#define EVERGREEN_D4VGA_CONTROL 0x3e4 +#define EVERGREEN_D5VGA_CONTROL 0x3e8 +#define EVERGREEN_D6VGA_CONTROL 0x3ec + +#define EVERGREEN_P1PLL_SS_CNTL 0x414 +#define EVERGREEN_P2PLL_SS_CNTL 0x454 +# define EVERGREEN_PxPLL_SS_EN (1 << 12) +/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */ +#define EVERGREEN_GRPH_ENABLE 0x6800 +#define EVERGREEN_GRPH_CONTROL 0x6804 +# define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) +# define EVERGREEN_GRPH_DEPTH_8BPP 0 +# define EVERGREEN_GRPH_DEPTH_16BPP 1 +# define EVERGREEN_GRPH_DEPTH_32BPP 2 +# define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) +/* 8 BPP */ +# define EVERGREEN_GRPH_FORMAT_INDEXED 0 +/* 16 BPP */ +# define EVERGREEN_GRPH_FORMAT_ARGB1555 0 +# define EVERGREEN_GRPH_FORMAT_ARGB565 1 +# define EVERGREEN_GRPH_FORMAT_ARGB4444 2 +# define EVERGREEN_GRPH_FORMAT_AI88 3 +# define EVERGREEN_GRPH_FORMAT_MONO16 4 +# define EVERGREEN_GRPH_FORMAT_BGRA5551 5 +/* 32 BPP */ +# define EVERGREEN_GRPH_FORMAT_ARGB8888 0 +# define EVERGREEN_GRPH_FORMAT_ARGB2101010 1 +# define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2 +# define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3 +# define EVERGREEN_GRPH_FORMAT_BGRA1010102 4 +# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5 +# define EVERGREEN_GRPH_FORMAT_RGB111110 6 +# define EVERGREEN_GRPH_FORMAT_BGR101111 7 +#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c +# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) +# define EVERGREEN_GRPH_ENDIAN_NONE 0 +# define EVERGREEN_GRPH_ENDIAN_8IN16 1 +# define EVERGREEN_GRPH_ENDIAN_8IN32 2 +# define EVERGREEN_GRPH_ENDIAN_8IN64 3 +# define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) +# define EVERGREEN_GRPH_RED_SEL_R 0 +# define EVERGREEN_GRPH_RED_SEL_G 1 +# define EVERGREEN_GRPH_RED_SEL_B 2 +# define EVERGREEN_GRPH_RED_SEL_A 3 +# define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) +# define EVERGREEN_GRPH_GREEN_SEL_G 0 +# define EVERGREEN_GRPH_GREEN_SEL_B 1 +# define EVERGREEN_GRPH_GREEN_SEL_A 2 +# define EVERGREEN_GRPH_GREEN_SEL_R 3 +# define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) +# define EVERGREEN_GRPH_BLUE_SEL_B 0 +# define EVERGREEN_GRPH_BLUE_SEL_A 1 +# define EVERGREEN_GRPH_BLUE_SEL_R 2 +# define EVERGREEN_GRPH_BLUE_SEL_G 3 +# define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) +# define EVERGREEN_GRPH_ALPHA_SEL_A 0 +# define EVERGREEN_GRPH_ALPHA_SEL_R 1 +# define EVERGREEN_GRPH_ALPHA_SEL_G 2 +# define EVERGREEN_GRPH_ALPHA_SEL_B 3 +#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810 +#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814 +# define EVERGREEN_GRPH_DFQ_ENABLE (1 << 0) +# define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00 +#define EVERGREEN_GRPH_PITCH 0x6818 +#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c +#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820 +#define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824 +#define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828 +#define EVERGREEN_GRPH_X_START 0x682c +#define EVERGREEN_GRPH_Y_START 0x6830 +#define EVERGREEN_GRPH_X_END 0x6834 +#define EVERGREEN_GRPH_Y_END 0x6838 + +/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ +#define EVERGREEN_CUR_CONTROL 0x6998 +# define EVERGREEN_CURSOR_EN (1 << 0) +# define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) +# define EVERGREEN_CURSOR_MONO 0 +# define EVERGREEN_CURSOR_24_1 1 +# define EVERGREEN_CURSOR_24_8_PRE_MULT 2 +# define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3 +# define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16) +# define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20) +# define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) +# define EVERGREEN_CURSOR_URGENT_ALWAYS 0 +# define EVERGREEN_CURSOR_URGENT_1_8 1 +# define EVERGREEN_CURSOR_URGENT_1_4 2 +# define EVERGREEN_CURSOR_URGENT_3_8 3 +# define EVERGREEN_CURSOR_URGENT_1_2 4 +#define EVERGREEN_CUR_SURFACE_ADDRESS 0x699c +# define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000 +#define EVERGREEN_CUR_SIZE 0x69a0 +#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x69a4 +#define EVERGREEN_CUR_POSITION 0x69a8 +#define EVERGREEN_CUR_HOT_SPOT 0x69ac +#define EVERGREEN_CUR_COLOR1 0x69b0 +#define EVERGREEN_CUR_COLOR2 0x69b4 +#define EVERGREEN_CUR_UPDATE 0x69b8 +# define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0) +# define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1) +# define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16) +# define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) + +/* LUT blocks at 0x69e0, 0x75e0, 0x101e0, 0x10de0, 0x119e0, 0x125e0 */ +#define EVERGREEN_DC_LUT_RW_MODE 0x69e0 +#define EVERGREEN_DC_LUT_RW_INDEX 0x69e4 +#define EVERGREEN_DC_LUT_SEQ_COLOR 0x69e8 +#define EVERGREEN_DC_LUT_PWL_DATA 0x69ec +#define EVERGREEN_DC_LUT_30_COLOR 0x69f0 +#define EVERGREEN_DC_LUT_VGA_ACCESS_ENABLE 0x69f4 +#define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x69f8 +#define EVERGREEN_DC_LUT_AUTOFILL 0x69fc +#define EVERGREEN_DC_LUT_CONTROL 0x6a00 +#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x6a04 +#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x6a08 +#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x6a0c +#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x6a10 +#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x6a14 +#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x6a18 + +#define EVERGREEN_DATA_FORMAT 0x6b00 +# define EVERGREEN_INTERLEAVE_EN (1 << 0) +#define EVERGREEN_DESKTOP_HEIGHT 0x6b04 + +#define EVERGREEN_VIEWPORT_START 0x6d70 +#define EVERGREEN_VIEWPORT_SIZE 0x6d74 + +/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ +#define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0) +#define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0) +#define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0) +#define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) +#define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) +#define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) + +/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ +#define EVERGREEN_CRTC_CONTROL 0x6e70 +# define EVERGREEN_CRTC_MASTER_EN (1 << 0) +#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4 + +#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0 +#define EVERGREEN_DC_GPIO_HPD_A 0x64b4 +#define EVERGREEN_DC_GPIO_HPD_EN 0x64b8 +#define EVERGREEN_DC_GPIO_HPD_Y 0x64bc + +#endif diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index b519d7db2dcb..a7a96a240844 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -138,11 +138,14 @@ void radeon_dummy_page_fini(struct radeon_device *rdev); struct radeon_clock { struct radeon_pll p1pll; struct radeon_pll p2pll; + struct radeon_pll dcpll; struct radeon_pll spll; struct radeon_pll mpll; /* 10 Khz units */ uint32_t default_mclk; uint32_t default_sclk; + uint32_t default_dispclk; + uint32_t dp_extclk; }; /* @@ -1062,7 +1065,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev); #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) - +#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) /* * BIOS helpers. @@ -1296,6 +1299,14 @@ extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, uint8_t status_bits, uint8_t category_code); +/* evergreen */ +struct evergreen_mc_save { + u32 vga_control[6]; + u32 vga_render_control; + u32 vga_hdp_control; + u32 crtc_control[6]; +}; + #include "radeon_object.h" #endif diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 3f3c7a2169f1..4b0cb67a379a 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -606,4 +606,54 @@ static struct radeon_asic rv770_asic = { .ioctl_wait_idle = r600_ioctl_wait_idle, }; +/* + * evergreen + */ +int evergreen_init(struct radeon_device *rdev); +void evergreen_fini(struct radeon_device *rdev); +int evergreen_suspend(struct radeon_device *rdev); +int evergreen_resume(struct radeon_device *rdev); +int evergreen_gpu_reset(struct radeon_device *rdev); +void evergreen_bandwidth_update(struct radeon_device *rdev); +void evergreen_hpd_init(struct radeon_device *rdev); +void evergreen_hpd_fini(struct radeon_device *rdev); +bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); +void evergreen_hpd_set_polarity(struct radeon_device *rdev, + enum radeon_hpd_id hpd); + +static struct radeon_asic evergreen_asic = { + .init = &evergreen_init, + .fini = &evergreen_fini, + .suspend = &evergreen_suspend, + .resume = &evergreen_resume, + .cp_commit = NULL, + .gpu_reset = &evergreen_gpu_reset, + .vga_set_state = &r600_vga_set_state, + .gart_tlb_flush = &r600_pcie_gart_tlb_flush, + .gart_set_page = &rs600_gart_set_page, + .ring_test = NULL, + .ring_ib_execute = NULL, + .irq_set = NULL, + .irq_process = NULL, + .get_vblank_counter = NULL, + .fence_ring_emit = NULL, + .cs_parse = NULL, + .copy_blit = NULL, + .copy_dma = NULL, + .copy = NULL, + .get_engine_clock = &radeon_atom_get_engine_clock, + .set_engine_clock = &radeon_atom_set_engine_clock, + .get_memory_clock = &radeon_atom_get_memory_clock, + .set_memory_clock = &radeon_atom_set_memory_clock, + .set_pcie_lanes = NULL, + .set_clock_gating = NULL, + .set_surface_reg = r600_set_surface_reg, + .clear_surface_reg = r600_clear_surface_reg, + .bandwidth_update = &evergreen_bandwidth_update, + .hpd_init = &evergreen_hpd_init, + .hpd_fini = &evergreen_hpd_fini, + .hpd_sense = &evergreen_hpd_sense, + .hpd_set_polarity = &evergreen_hpd_set_polarity, +}; + #endif diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index c3198453528f..4f7dbce9883a 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -159,8 +159,15 @@ static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device struct radeon_gpio_rec *gpio) { struct radeon_hpd hpd; + u32 reg; + + if (ASIC_IS_DCE4(rdev)) + reg = EVERGREEN_DC_GPIO_HPD_A; + else + reg = AVIVO_DC_GPIO_HPD_A; + hpd.gpio = *gpio; - if (gpio->reg == AVIVO_DC_GPIO_HPD_A) { + if (gpio->reg == reg) { switch(gpio->mask) { case (1 << 0): hpd.hpd = RADEON_HPD_1; @@ -556,6 +563,9 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) ddc_bus.valid = false; } + /* needed for aux chan transactions */ + ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0; + conn_id = le16_to_cpu(path->usConnObjectId); if (!radeon_atom_apply_quirks @@ -820,6 +830,7 @@ union firmware_info { ATOM_FIRMWARE_INFO_V1_2 info_12; ATOM_FIRMWARE_INFO_V1_3 info_13; ATOM_FIRMWARE_INFO_V1_4 info_14; + ATOM_FIRMWARE_INFO_V2_1 info_21; }; bool radeon_atom_get_clock_info(struct drm_device *dev) @@ -831,6 +842,7 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) uint8_t frev, crev; struct radeon_pll *p1pll = &rdev->clock.p1pll; struct radeon_pll *p2pll = &rdev->clock.p2pll; + struct radeon_pll *dcpll = &rdev->clock.dcpll; struct radeon_pll *spll = &rdev->clock.spll; struct radeon_pll *mpll = &rdev->clock.mpll; uint16_t data_offset; @@ -933,8 +945,19 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) rdev->clock.default_mclk = le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); + if (ASIC_IS_DCE4(rdev)) { + rdev->clock.default_dispclk = + le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); + if (rdev->clock.default_dispclk == 0) + rdev->clock.default_dispclk = 60000; /* 600 Mhz */ + rdev->clock.dp_extclk = + le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); + } + *dcpll = *p1pll; + return true; } + return false; } diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c index 3ec94a0d3109..f64936cc4dd9 100644 --- a/drivers/gpu/drm/radeon/radeon_clocks.c +++ b/drivers/gpu/drm/radeon/radeon_clocks.c @@ -96,6 +96,7 @@ void radeon_get_clock_info(struct drm_device *dev) struct radeon_device *rdev = dev->dev_private; struct radeon_pll *p1pll = &rdev->clock.p1pll; struct radeon_pll *p2pll = &rdev->clock.p2pll; + struct radeon_pll *dcpll = &rdev->clock.dcpll; struct radeon_pll *spll = &rdev->clock.spll; struct radeon_pll *mpll = &rdev->clock.mpll; int ret; @@ -204,6 +205,17 @@ void radeon_get_clock_info(struct drm_device *dev) p2pll->max_frac_feedback_div = 0; } + /* dcpll is DCE4 only */ + dcpll->min_post_div = 2; + dcpll->max_post_div = 0x7f; + dcpll->min_frac_feedback_div = 0; + dcpll->max_frac_feedback_div = 9; + dcpll->min_ref_div = 2; + dcpll->max_ref_div = 0x3ff; + dcpll->min_feedback_div = 4; + dcpll->max_feedback_div = 0xfff; + dcpll->best_vco = 0; + p1pll->min_ref_div = 2; p1pll->max_ref_div = 0x3ff; p1pll->min_feedback_div = 4; diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index a4d40de50434..26fb42450cb2 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -600,6 +600,7 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde } i2c.mm_i2c = false; i2c.i2c_id = 0; + i2c.hpd_id = 0; if (ddc_line) i2c.valid = true; diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c index 28772a37009c..9514f3275357 100644 --- a/drivers/gpu/drm/radeon/radeon_cursor.c +++ b/drivers/gpu/drm/radeon/radeon_cursor.c @@ -36,7 +36,14 @@ static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock) struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); uint32_t cur_lock; - if (ASIC_IS_AVIVO(rdev)) { + if (ASIC_IS_DCE4(rdev)) { + cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); + if (lock) + cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; + else + cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; + WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); + } else if (ASIC_IS_AVIVO(rdev)) { cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); if (lock) cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; @@ -58,7 +65,10 @@ static void radeon_hide_cursor(struct drm_crtc *crtc) struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct radeon_device *rdev = crtc->dev->dev_private; - if (ASIC_IS_AVIVO(rdev)) { + if (ASIC_IS_DCE4(rdev)) { + WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); + WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); + } else if (ASIC_IS_AVIVO(rdev)) { WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); } else { @@ -81,10 +91,14 @@ static void radeon_show_cursor(struct drm_crtc *crtc) struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct radeon_device *rdev = crtc->dev->dev_private; - if (ASIC_IS_AVIVO(rdev)) { + if (ASIC_IS_DCE4(rdev)) { + WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); + WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | + EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); + } else if (ASIC_IS_AVIVO(rdev)) { WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | - (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); + (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); } else { switch (radeon_crtc->crtc_id) { case 0: @@ -109,7 +123,10 @@ static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct radeon_device *rdev = crtc->dev->dev_private; - if (ASIC_IS_AVIVO(rdev)) { + if (ASIC_IS_DCE4(rdev)) { + WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0); + WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); + } else if (ASIC_IS_AVIVO(rdev)) { if (rdev->family >= CHIP_RV770) { if (radeon_crtc->crtc_id) WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0); @@ -201,7 +218,15 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc, yorigin = CURSOR_HEIGHT - 1; radeon_lock_cursor(crtc, true); - if (ASIC_IS_AVIVO(rdev)) { + if (ASIC_IS_DCE4(rdev)) { + /* XXX: check if evergreen has the same issues as avivo chips */ + WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, + ((xorigin ? 0 : x) << 16) | + (yorigin ? 0 : y)); + WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); + WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, + ((radeon_crtc->cursor_width - 1) << 16) | (radeon_crtc->cursor_height - 1)); + } else if (ASIC_IS_AVIVO(rdev)) { int w = radeon_crtc->cursor_width; int i = 0; struct drm_crtc *crtc_p; diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index c90f8d370266..c224c1d944ef 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -182,7 +182,16 @@ bool radeon_card_posted(struct radeon_device *rdev) uint32_t reg; /* first check CRTCs */ - if (ASIC_IS_AVIVO(rdev)) { + if (ASIC_IS_DCE4(rdev)) { + reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | + RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | + RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | + RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | + RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | + RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); + if (reg & EVERGREEN_CRTC_MASTER_EN) + return true; + } else if (ASIC_IS_AVIVO(rdev)) { reg = RREG32(AVIVO_D1CRTC_CONTROL) | RREG32(AVIVO_D2CRTC_CONTROL); if (reg & AVIVO_CRTC_EN) { @@ -310,7 +319,7 @@ void radeon_register_accessor_init(struct radeon_device *rdev) rdev->mc_rreg = &rs600_mc_rreg; rdev->mc_wreg = &rs600_mc_wreg; } - if (rdev->family >= CHIP_R600) { + if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) { rdev->pciep_rreg = &r600_pciep_rreg; rdev->pciep_wreg = &r600_pciep_wreg; } @@ -387,6 +396,13 @@ int radeon_asic_init(struct radeon_device *rdev) case CHIP_RV740: rdev->asic = &rv770_asic; break; + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + rdev->asic = &evergreen_asic; + break; default: /* FIXME: not supported yet */ return -EINVAL; diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index a41ed40c13fb..257827806aee 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -68,6 +68,36 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc) WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); } +static void evergreen_crtc_load_lut(struct drm_crtc *crtc) +{ + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct radeon_device *rdev = dev->dev_private; + int i; + + DRM_DEBUG("%d\n", radeon_crtc->crtc_id); + WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); + + WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); + WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); + WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); + + WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); + WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); + WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); + + WREG32(EVERGREEN_DC_LUT_RW_MODE, radeon_crtc->crtc_id); + WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007); + + WREG32(EVERGREEN_DC_LUT_RW_INDEX, 0); + for (i = 0; i < 256; i++) { + WREG32(EVERGREEN_DC_LUT_30_COLOR, + (radeon_crtc->lut_r[i] << 20) | + (radeon_crtc->lut_g[i] << 10) | + (radeon_crtc->lut_b[i] << 0)); + } +} + static void legacy_crtc_load_lut(struct drm_crtc *crtc) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); @@ -100,7 +130,9 @@ void radeon_crtc_load_lut(struct drm_crtc *crtc) if (!crtc->enabled) return; - if (ASIC_IS_AVIVO(rdev)) + if (ASIC_IS_DCE4(rdev)) + evergreen_crtc_load_lut(crtc); + else if (ASIC_IS_AVIVO(rdev)) avivo_crtc_load_lut(crtc); else legacy_crtc_load_lut(crtc); @@ -862,8 +894,12 @@ int radeon_modeset_init(struct radeon_device *rdev) if (rdev->flags & RADEON_SINGLE_CRTC) rdev->num_crtc = 1; - else - rdev->num_crtc = 2; + else { + if (ASIC_IS_DCE4(rdev)) + rdev->num_crtc = 6; + else + rdev->num_crtc = 2; + } /* allocate crtcs */ for (i = 0; i < rdev->num_crtc; i++) { diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index f7d6078876c5..bc926ea0a530 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c @@ -53,7 +53,7 @@ static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) /* DVO requires 2x ppll clocks depending on tmds chip */ if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) return index_mask; - + count = -1; list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); @@ -671,6 +671,18 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) * - 2 DIG encoder blocks. * DIG1/2 can drive UNIPHY0/1/2 link A or link B * + * DCE 4.0 + * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B). + * Supports up to 6 digital outputs + * - 6 DIG encoder blocks. + * - DIG to PHY mapping is hardcoded + * DIG1 drives UNIPHY0 link A, A+B + * DIG2 drives UNIPHY0 link B + * DIG3 drives UNIPHY1 link A, A+B + * DIG4 drives UNIPHY1 link B + * DIG5 drives UNIPHY2 link A, A+B + * DIG6 drives UNIPHY2 link B + * * Routing * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) * Examples: @@ -679,7 +691,14 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI */ -static void + +union dig_encoder_control { + DIG_ENCODER_CONTROL_PS_ALLOCATION v1; + DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; + DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; +}; + +void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) { struct drm_device *dev = encoder->dev; @@ -688,7 +707,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; struct radeon_connector_atom_dig *dig_connector = radeon_get_atom_connector_priv_from_encoder(encoder); - DIG_ENCODER_CONTROL_PS_ALLOCATION args; + union dig_encoder_control args; int index = 0, num = 0; uint8_t frev, crev; @@ -697,56 +716,53 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) memset(&args, 0, sizeof(args)); - if (dig->dig_encoder) - index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); - else - index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); + if (ASIC_IS_DCE4(rdev)) + index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); + else { + if (dig->dig_encoder) + index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); + else + index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); + } num = dig->dig_encoder + 1; atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); - args.ucAction = action; - args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); + args.v1.ucAction = action; + args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); + args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); - if (ASIC_IS_DCE32(rdev)) { + if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) { + if (dig_connector->dp_clock == 270000) + args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; + args.v1.ucLaneNum = dig_connector->dp_lane_count; + } else if (radeon_encoder->pixel_clock > 165000) + args.v1.ucLaneNum = 8; + else + args.v1.ucLaneNum = 4; + + if (ASIC_IS_DCE4(rdev)) { + args.v3.acConfig.ucDigSel = dig->dig_encoder; + args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; + } else { switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; + args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; break; case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: + args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; break; case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; - break; - } - } else { - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1; - break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: - args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2; + args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; break; } + if (dig_connector->linkb) + args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; + else + args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; } - args.ucEncoderMode = atombios_get_encoder_mode(encoder); - - if (args.ucEncoderMode == ATOM_ENCODER_MODE_DP) { - if (dig_connector->dp_clock == 270000) - args.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; - args.ucLaneNum = dig_connector->dp_lane_count; - } else if (radeon_encoder->pixel_clock > 165000) - args.ucLaneNum = 8; - else - args.ucLaneNum = 4; - - if (dig_connector->linkb) - args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; - else - args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; - atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); } @@ -754,6 +770,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) union dig_transmitter_control { DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; + DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; }; void @@ -771,6 +788,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t int index = 0, num = 0; uint8_t frev, crev; bool is_dp = false; + int pll_id = 0; if (!dig || !dig_connector) return; @@ -783,7 +801,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t memset(&args, 0, sizeof(args)); - if (ASIC_IS_DCE32(rdev)) + if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev)) index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); else { switch (radeon_encoder->encoder_id) { @@ -813,7 +831,54 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t else args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); } - if (ASIC_IS_DCE32(rdev)) { + if (ASIC_IS_DCE4(rdev)) { + if (is_dp) + args.v3.ucLaneNum = dig_connector->dp_lane_count; + else if (radeon_encoder->pixel_clock > 165000) + args.v3.ucLaneNum = 8; + else + args.v3.ucLaneNum = 4; + + if (dig_connector->linkb) { + args.v3.acConfig.ucLinkSel = 1; + args.v3.acConfig.ucEncoderSel = 1; + } + + /* Select the PLL for the PHY + * DP PHY should be clocked from external src if there is + * one. + */ + if (encoder->crtc) { + struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); + pll_id = radeon_crtc->pll_id; + } + if (is_dp && rdev->clock.dp_extclk) + args.v3.acConfig.ucRefClkSource = 2; /* external src */ + else + args.v3.acConfig.ucRefClkSource = pll_id; + + switch (radeon_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + args.v3.acConfig.ucTransmitterSel = 0; + num = 0; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + args.v3.acConfig.ucTransmitterSel = 1; + num = 1; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + args.v3.acConfig.ucTransmitterSel = 2; + num = 2; + break; + } + + if (is_dp) + args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ + else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { + if (dig->coherent_mode) + args.v3.acConfig.fCoherentMode = 1; + } + } else if (ASIC_IS_DCE32(rdev)) { if (dig->dig_encoder == 1) args.v2.acConfig.ucEncoderSel = 1; if (dig_connector->linkb) @@ -841,7 +906,6 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t args.v2.acConfig.fCoherentMode = 1; } } else { - args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; if (dig->dig_encoder) @@ -1102,10 +1166,26 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: dig = radeon_encoder->enc_priv; - if (dig->dig_encoder) - args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; - else + switch (dig->dig_encoder) { + case 0: args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; + break; + case 1: + args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; + break; + case 2: + args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; + break; + case 3: + args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; + break; + case 4: + args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; + break; + case 5: + args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; + break; + } break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; @@ -1162,6 +1242,7 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder, } /* set scaler clears this on some chips */ + /* XXX check DCE4 */ if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, @@ -1178,6 +1259,33 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) struct drm_encoder *test_encoder; struct radeon_encoder_atom_dig *dig; uint32_t dig_enc_in_use = 0; + + if (ASIC_IS_DCE4(rdev)) { + struct radeon_connector_atom_dig *dig_connector = + radeon_get_atom_connector_priv_from_encoder(encoder); + + switch (radeon_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + if (dig_connector->linkb) + return 1; + else + return 0; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + if (dig_connector->linkb) + return 3; + else + return 2; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + if (dig_connector->linkb) + return 5; + else + return 4; + break; + } + } + /* on DCE32 and encoder can driver any block so just crtc id */ if (ASIC_IS_DCE32(rdev)) { return radeon_crtc->crtc_id; @@ -1249,15 +1357,26 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: - /* disable the encoder and transmitter */ - atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); - atombios_dig_encoder_setup(encoder, ATOM_DISABLE); - - /* setup and enable the encoder and transmitter */ - atombios_dig_encoder_setup(encoder, ATOM_ENABLE); - atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); - atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); - atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); + if (ASIC_IS_DCE4(rdev)) { + /* disable the transmitter */ + atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); + /* setup and enable the encoder */ + atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP); + + /* init and enable the transmitter */ + atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); + atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); + } else { + /* disable the encoder and transmitter */ + atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); + atombios_dig_encoder_setup(encoder, ATOM_DISABLE); + + /* setup and enable the encoder and transmitter */ + atombios_dig_encoder_setup(encoder, ATOM_ENABLE); + atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); + atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); + atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); + } break; case ENCODER_OBJECT_ID_INTERNAL_DDI: atombios_ddia_setup(encoder, ATOM_ENABLE); @@ -1277,7 +1396,9 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, } atombios_apply_encoder_quirks(encoder, adjusted_mode); - r600_hdmi_setmode(encoder, adjusted_mode); + /* XXX */ + if (!ASIC_IS_DCE4(rdev)) + r600_hdmi_setmode(encoder, adjusted_mode); } static bool @@ -1475,10 +1596,18 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su return; encoder = &radeon_encoder->base; - if (rdev->flags & RADEON_SINGLE_CRTC) + switch (rdev->num_crtc) { + case 1: encoder->possible_crtcs = 0x1; - else + break; + case 2: + default: encoder->possible_crtcs = 0x3; + break; + case 6: + encoder->possible_crtcs = 0x3f; + break; + } radeon_encoder->enc_priv = NULL; diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h index 797972e344a6..93c7d5d41914 100644 --- a/drivers/gpu/drm/radeon/radeon_family.h +++ b/drivers/gpu/drm/radeon/radeon_family.h @@ -75,6 +75,11 @@ enum radeon_family { CHIP_RV730, CHIP_RV710, CHIP_RV740, + CHIP_CEDAR, + CHIP_REDWOOD, + CHIP_JUNIPER, + CHIP_CYPRESS, + CHIP_HEMLOCK, CHIP_LAST, }; diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index d1e859d1dbf9..8912f2e8e640 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -83,6 +83,8 @@ struct radeon_i2c_bus_rec { bool valid; /* id used by atom */ uint8_t i2c_id; + /* id used by atom */ + uint8_t hpd_id; /* can be used with hw i2c engine */ bool hw_capable; /* uses multi-media i2c engine */ @@ -207,7 +209,7 @@ struct radeon_mode_info { struct card_info *atom_card_info; enum radeon_connector_table connector_table; bool mode_config_initialized; - struct radeon_crtc *crtcs[2]; + struct radeon_crtc *crtcs[6]; /* DVI-I properties */ struct drm_property *coherent_mode_property; /* DAC enable load detect */ @@ -252,6 +254,7 @@ struct radeon_crtc { fixed20_12 vsc; fixed20_12 hsc; struct drm_display_mode native_mode; + int pll_id; }; struct radeon_encoder_primary_dac { @@ -414,6 +417,7 @@ extern void dp_link_train(struct drm_encoder *encoder, struct drm_connector *connector); extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); +extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action); extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set); diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index b4a06676fff6..5c0dc082d330 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h @@ -54,7 +54,7 @@ #include "r300_reg.h" #include "r500_reg.h" #include "r600_reg.h" - +#include "evergreen_reg.h" #define RADEON_MC_AGP_LOCATION 0x014c #define RADEON_MC_AGP_START_MASK 0x0000FFFF diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h index a1367ab6f261..9506f8cb99e0 100644 --- a/drivers/gpu/drm/radeon/rv770d.h +++ b/drivers/gpu/drm/radeon/rv770d.h @@ -343,4 +343,6 @@ #define WAIT_UNTIL 0x8040 +#define SRBM_STATUS 0x0E50 + #endif diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h index e6f3b120f51a..403490c7b647 100644 --- a/include/drm/drm_pciids.h +++ b/include/drm/drm_pciids.h @@ -141,6 +141,41 @@ {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x6880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x6888, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x6889, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x688A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x6898, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x6899, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x689c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x689d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x689e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68a0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68a1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68a8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68a9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68b9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68be, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68c8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68c9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68e0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68e1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68e5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68e8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68e9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68f1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68f8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68f9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x68fe, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ -- cgit v1.2.3 From 3ad2f3fbb961429d2aa627465ae4829758bc7e07 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Wed, 3 Feb 2010 08:01:28 +0800 Subject: tree-wide: Assorted spelling fixes In particular, several occurances of funny versions of 'success', 'unknown', 'therefore', 'acknowledge', 'argument', 'achieve', 'address', 'beginning', 'desirable', 'separate' and 'necessary' are fixed. Signed-off-by: Daniel Mack Cc: Joe Perches Cc: Junio C Hamano Signed-off-by: Jiri Kosina --- Documentation/DocBook/mtdnand.tmpl | 6 +++--- Documentation/DocBook/v4l/common.xml | 2 +- Documentation/DocBook/v4l/vidioc-g-parm.xml | 2 +- Documentation/arm/Samsung-S3C24XX/CPUfreq.txt | 4 ++-- Documentation/hwmon/abituguru | 2 +- Documentation/input/rotary-encoder.txt | 2 +- Documentation/networking/skfp.txt | 2 +- Documentation/s390/kvm.txt | 2 +- Documentation/scsi/ChangeLog.lpfc | 10 +++++----- Documentation/trace/ftrace.txt | 2 +- arch/arm/mach-ep93xx/micro9.c | 2 +- arch/arm/mach-nomadik/board-nhk8815.c | 2 +- arch/arm/mach-u300/core.c | 4 ++-- arch/arm/mach-u300/include/mach/debug-macro.S | 2 +- arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h | 2 +- arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h | 2 +- arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h | 2 +- arch/cris/arch-v10/lib/old_checksum.c | 2 +- arch/cris/arch-v32/mm/tlb.c | 2 +- arch/h8300/include/asm/io.h | 2 +- arch/ia64/sn/kernel/setup.c | 2 +- arch/m68k/atari/atakeyb.c | 2 +- arch/m68k/include/asm/io_no.h | 2 +- arch/powerpc/boot/dts/kmeter1.dts | 2 +- arch/s390/include/asm/cio.h | 2 +- arch/s390/kernel/sclp.S | 2 +- arch/sparc/kernel/leon_kernel.c | 2 +- arch/sparc/kernel/perf_event.c | 2 +- arch/x86/crypto/twofish-i586-asm_32.S | 10 +++++----- arch/x86/crypto/twofish-x86_64-asm_64.S | 20 ++++++++++---------- arch/x86/kernel/head_64.S | 2 +- arch/x86/kernel/pci-calgary_64.c | 2 +- arch/x86/kernel/tsc.c | 2 +- arch/xtensa/kernel/entry.S | 4 ++-- block/bsg.c | 2 +- drivers/acpi/dock.c | 2 +- drivers/ata/libata-sff.c | 2 +- drivers/ata/pata_acpi.c | 2 +- drivers/ata/pata_hpt3x3.c | 2 +- drivers/ata/pata_pcmcia.c | 2 +- drivers/block/drbd/drbd_int.h | 4 ++-- drivers/block/drbd/drbd_req.h | 2 +- drivers/char/agp/intel-agp.c | 2 +- drivers/char/applicom.c | 2 +- drivers/char/hvc_iseries.c | 2 +- drivers/char/hw_random/n2-drv.c | 2 +- drivers/char/ip2/i2hw.h | 2 +- drivers/char/pty.c | 2 +- drivers/char/tty_io.c | 2 +- drivers/char/vt.c | 2 +- drivers/dma/coh901318_lli.h | 2 +- drivers/gpu/drm/nouveau/nouveau_bios.c | 2 +- drivers/gpu/drm/nouveau/nouveau_drv.h | 2 +- drivers/gpu/drm/via/via_irq.c | 4 ++-- drivers/i2c/busses/i2c-pxa.c | 2 +- drivers/infiniband/hw/ehca/ehca_qes.h | 4 ++-- drivers/infiniband/hw/ehca/ehca_reqs.c | 2 +- drivers/input/misc/yealink.h | 2 +- drivers/isdn/i4l/isdn_common.c | 2 +- drivers/media/dvb/dvb-core/dvb_frontend.h | 8 ++++---- drivers/media/video/bt8xx/bttv-cards.c | 4 ++-- drivers/media/video/gspca/ov519.c | 2 +- drivers/media/video/pwc/philips.txt | 2 +- drivers/media/video/sn9c102/sn9c102_sensor.h | 2 +- drivers/media/video/tea6420.c | 2 +- drivers/mfd/sm501.c | 8 ++++---- drivers/mmc/host/mxcmmc.c | 2 +- drivers/mtd/chips/jedec_probe.c | 2 +- drivers/mtd/nand/bcm_umi_nand.c | 4 ++-- drivers/mtd/nand/mxc_nand.c | 2 +- drivers/net/atlx/atl2.h | 2 +- drivers/net/chelsio/sge.c | 2 +- drivers/net/e1000e/82571.c | 2 +- drivers/net/e1000e/lib.c | 2 +- drivers/net/igb/igb_main.c | 2 +- drivers/net/irda/sa1100_ir.c | 2 +- drivers/net/qlge/qlge_ethtool.c | 2 +- drivers/net/qlge/qlge_main.c | 2 +- drivers/net/sfc/regs.h | 2 +- drivers/net/smsc9420.c | 2 +- drivers/net/spider_net.c | 4 ++-- drivers/net/sungem.c | 2 +- drivers/net/tehuti.c | 2 +- drivers/net/tokenring/tms380tr.c | 4 ++-- drivers/net/tun.c | 2 +- drivers/net/ucc_geth.c | 2 +- drivers/net/wimax/i2400m/fw.c | 2 +- drivers/net/wimax/i2400m/i2400m.h | 2 +- drivers/net/wimax/i2400m/sdio.c | 4 ++-- drivers/net/wimax/i2400m/usb.c | 4 ++-- drivers/net/wireless/ath/ar9170/main.c | 2 +- drivers/net/wireless/iwmc3200wifi/lmac.h | 2 +- drivers/net/wireless/rt2x00/rt2500usb.c | 4 ++-- drivers/net/wireless/rt2x00/rt2800usb.c | 4 ++-- drivers/net/wireless/rt2x00/rt2x00debug.c | 2 +- drivers/net/wireless/rt2x00/rt2x00dev.c | 2 +- drivers/net/wireless/rt2x00/rt2x00queue.c | 2 +- drivers/net/wireless/rt2x00/rt61pci.c | 2 +- drivers/net/wireless/rt2x00/rt73usb.c | 6 +++--- drivers/s390/char/raw3270.c | 2 +- drivers/s390/char/sclp.c | 2 +- drivers/scsi/a100u2w.c | 2 +- drivers/scsi/initio.c | 2 +- drivers/scsi/libfc/fc_fcp.c | 2 +- drivers/scsi/lpfc/lpfc_els.c | 4 ++-- drivers/scsi/pcmcia/nsp_cs.h | 2 +- drivers/scsi/pm8001/pm8001_hwi.c | 2 +- drivers/scsi/pm8001/pm8001_sas.c | 2 +- drivers/scsi/pmcraid.h | 2 +- drivers/scsi/sd.c | 2 +- drivers/spi/spi_s3c24xx.c | 2 +- drivers/usb/musb/musb_regs.h | 2 +- drivers/usb/serial/cypress_m8.c | 2 +- drivers/video/omap/lcdc.c | 2 +- drivers/video/s1d13xxxfb.c | 4 ++-- drivers/video/sm501fb.c | 2 +- fs/affs/bitmap.c | 2 +- fs/binfmt_elf_fdpic.c | 2 +- fs/cifs/cifs_dfs_ref.c | 2 +- fs/cifs/cifssmb.c | 2 +- fs/ext4/move_extent.c | 2 +- fs/fuse/inode.c | 2 +- fs/gfs2/ops_fstype.c | 2 +- fs/jbd/transaction.c | 2 +- fs/nfsd/nfs4xdr.c | 2 +- fs/ocfs2/dlmglue.c | 2 +- fs/ocfs2/extent_map.c | 2 +- fs/reiserfs/bitmap.c | 2 +- include/linux/hil.h | 16 ++++++++-------- include/linux/lru_cache.h | 2 +- include/linux/sched.h | 2 +- include/media/davinci/vpfe_capture.h | 2 +- net/ipv4/tcp_timer.c | 2 +- net/mac80211/mesh_plink.c | 2 +- net/netfilter/nf_conntrack_sip.c | 4 ++-- net/netfilter/xt_hashlimit.c | 2 +- net/sctp/sm_sideeffect.c | 2 +- scripts/gfp-translate | 2 +- sound/pci/rme9652/hdspm.c | 2 +- sound/soc/codecs/wm8990.c | 2 +- tools/perf/util/hist.c | 2 +- 141 files changed, 192 insertions(+), 192 deletions(-) (limited to 'drivers') diff --git a/Documentation/DocBook/mtdnand.tmpl b/Documentation/DocBook/mtdnand.tmpl index 5e7d84b48505..133cd6c3f3c1 100644 --- a/Documentation/DocBook/mtdnand.tmpl +++ b/Documentation/DocBook/mtdnand.tmpl @@ -488,7 +488,7 @@ static void board_select_chip (struct mtd_info *mtd, int chip) The ECC bytes must be placed immidiately after the data bytes in order to make the syndrome generator work. This is contrary to the usual layout used by software ECC. The - seperation of data and out of band area is not longer + separation of data and out of band area is not longer possible. The nand driver code handles this layout and the remaining free bytes in the oob area are managed by the autoplacement code. Provide a matching oob-layout @@ -560,7 +560,7 @@ static void board_select_chip (struct mtd_info *mtd, int chip) bad blocks. They have factory marked good blocks. The marker pattern is erased when the block is erased to be reused. So in case of powerloss before writing the pattern back to the chip this block - would be lost and added to the bad blocks. Therefor we scan the + would be lost and added to the bad blocks. Therefore we scan the chip(s) when we detect them the first time for good blocks and store this information in a bad block table before erasing any of the blocks. @@ -1094,7 +1094,7 @@ in this page manufacturers specifications. This applies similar to the spare area. - Therefor NAND aware filesystems must either write in page size chunks + Therefore NAND aware filesystems must either write in page size chunks or hold a writebuffer to collect smaller writes until they sum up to pagesize. Available NAND aware filesystems: JFFS2, YAFFS. diff --git a/Documentation/DocBook/v4l/common.xml b/Documentation/DocBook/v4l/common.xml index c65f0ac9b6ee..cea23e1c4fc6 100644 --- a/Documentation/DocBook/v4l/common.xml +++ b/Documentation/DocBook/v4l/common.xml @@ -1170,7 +1170,7 @@ frames per second. If less than this number of frames is to be captured or output, applications can request frame skipping or duplicating on the driver side. This is especially useful when using the &func-read; or &func-write;, which are not augmented by timestamps -or sequence counters, and to avoid unneccessary data copying. +or sequence counters, and to avoid unnecessary data copying. Finally these ioctls can be used to determine the number of buffers used internally by a driver in read/write mode. For diff --git a/Documentation/DocBook/v4l/vidioc-g-parm.xml b/Documentation/DocBook/v4l/vidioc-g-parm.xml index 78332d365ce9..392aa9e5571e 100644 --- a/Documentation/DocBook/v4l/vidioc-g-parm.xml +++ b/Documentation/DocBook/v4l/vidioc-g-parm.xml @@ -55,7 +55,7 @@ captured or output, applications can request frame skipping or duplicating on the driver side. This is especially useful when using the read() or write(), which are not augmented by timestamps or sequence counters, and to avoid -unneccessary data copying. +unnecessary data copying. Further these ioctls can be used to determine the number of buffers used internally by a driver in read/write mode. For diff --git a/Documentation/arm/Samsung-S3C24XX/CPUfreq.txt b/Documentation/arm/Samsung-S3C24XX/CPUfreq.txt index 76b3a11e90be..fa968aa99d67 100644 --- a/Documentation/arm/Samsung-S3C24XX/CPUfreq.txt +++ b/Documentation/arm/Samsung-S3C24XX/CPUfreq.txt @@ -14,8 +14,8 @@ Introduction how the clocks are arranged. The first implementation used as single PLL to feed the ARM, memory and peripherals via a series of dividers and muxes and this is the implementation that is documented here. A - newer version where there is a seperate PLL and clock divider for the - ARM core is available as a seperate driver. + newer version where there is a separate PLL and clock divider for the + ARM core is available as a separate driver. Layout diff --git a/Documentation/hwmon/abituguru b/Documentation/hwmon/abituguru index 87ffa0f5ec70..5eb3b9d5f0d5 100644 --- a/Documentation/hwmon/abituguru +++ b/Documentation/hwmon/abituguru @@ -30,7 +30,7 @@ Supported chips: bank1_types=1,1,0,0,0,0,0,2,0,0,0,0,2,0,0,1 You may also need to specify the fan_sensors option for these boards fan_sensors=5 - 2) There is a seperate abituguru3 driver for these motherboards, + 2) There is a separate abituguru3 driver for these motherboards, the abituguru (without the 3 !) driver will not work on these motherboards (and visa versa)! diff --git a/Documentation/input/rotary-encoder.txt b/Documentation/input/rotary-encoder.txt index 3a6aec40c0b0..8b4129de1d2d 100644 --- a/Documentation/input/rotary-encoder.txt +++ b/Documentation/input/rotary-encoder.txt @@ -75,7 +75,7 @@ and the number of steps or will clamp at the maximum and zero depending on the configuration. Because GPIO to IRQ mapping is platform specific, this information must -be given in seperately to the driver. See the example below. +be given in separately to the driver. See the example below. ------------------ diff --git a/Documentation/networking/skfp.txt b/Documentation/networking/skfp.txt index abfddf81e34a..203ec66c9fb4 100644 --- a/Documentation/networking/skfp.txt +++ b/Documentation/networking/skfp.txt @@ -68,7 +68,7 @@ Compaq adapters (not tested): ======================= From v2.01 on, the driver is integrated in the linux kernel sources. -Therefor, the installation is the same as for any other adapter +Therefore, the installation is the same as for any other adapter supported by the kernel. Refer to the manual of your distribution about the installation of network adapters. diff --git a/Documentation/s390/kvm.txt b/Documentation/s390/kvm.txt index 6f5ceb0f09fc..85f3280d7ef6 100644 --- a/Documentation/s390/kvm.txt +++ b/Documentation/s390/kvm.txt @@ -102,7 +102,7 @@ args: unsigned long see also: include/linux/kvm.h This ioctl stores the state of the cpu at the guest real address given as argument, unless one of the following values defined in include/linux/kvm.h -is given as arguement: +is given as argument: KVM_S390_STORE_STATUS_NOADDR - the CPU stores its status to the save area in absolute lowcore as defined by the principles of operation KVM_S390_STORE_STATUS_PREFIXED - the CPU stores its status to the save area in diff --git a/Documentation/scsi/ChangeLog.lpfc b/Documentation/scsi/ChangeLog.lpfc index ff19a52fe004..2ffc1148eb95 100644 --- a/Documentation/scsi/ChangeLog.lpfc +++ b/Documentation/scsi/ChangeLog.lpfc @@ -989,8 +989,8 @@ Changes from 20040709 to 20040716 * Remove redundant port_cmp != 2 check in if (!port_cmp) { .... if (port_cmp != 2).... } * Clock changes: removed struct clk_data and timerList. - * Clock changes: seperate nodev_tmo and els_retry_delay into 2 - seperate timers and convert to 1 argument changed + * Clock changes: separate nodev_tmo and els_retry_delay into 2 + separate timers and convert to 1 argument changed LPFC_NODE_FARP_PEND_t to struct lpfc_node_farp_pend convert ipfarp_tmo to 1 argument convert target struct tmofunc and rtplunfunc to 1 argument * cr_count, cr_delay and @@ -1514,7 +1514,7 @@ Changes from 20040402 to 20040409 * Remove unused elxclock declaration in elx_sli.h. * Since everywhere IOCB_ENTRY is used, the return value is cast, move the cast into the macro. - * Split ioctls out into seperate files + * Split ioctls out into separate files Changes from 20040326 to 20040402 @@ -1534,7 +1534,7 @@ Changes from 20040326 to 20040402 * Unused variable cleanup * Use Linux list macros for DMABUF_t * Break up ioctls into 3 sections, dfc, util, hbaapi - rearranged code so this could be easily seperated into a + rearranged code so this could be easily separated into a differnet module later All 3 are currently turned on by defines in lpfc_ioctl.c LPFC_DFC_IOCTL, LPFC_UTIL_IOCTL, LPFC_HBAAPI_IOCTL @@ -1551,7 +1551,7 @@ Changes from 20040326 to 20040402 started by lpfc_online(). lpfc_offline() only stopped els_timeout routine. It now stops all timeout routines associated with that hba. - * Replace seperate next and prev pointers in struct + * Replace separate next and prev pointers in struct lpfc_bindlist with list_head type. In elxHBA_t, replace fc_nlpbind_start and _end with fc_nlpbind_list and use list_head macros to access it. diff --git a/Documentation/trace/ftrace.txt b/Documentation/trace/ftrace.txt index bab3040da548..03485bfbd797 100644 --- a/Documentation/trace/ftrace.txt +++ b/Documentation/trace/ftrace.txt @@ -1588,7 +1588,7 @@ module author does not need to worry about it. When tracing is enabled, kstop_machine is called to prevent races with the CPUS executing code being modified (which can -cause the CPU to do undesireable things), and the nops are +cause the CPU to do undesirable things), and the nops are patched back to calls. But this time, they do not call mcount (which is just a function stub). They now call into the ftrace infrastructure. diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c index f3757a1c5a10..c33360e82868 100644 --- a/arch/arm/mach-ep93xx/micro9.c +++ b/arch/arm/mach-ep93xx/micro9.c @@ -28,7 +28,7 @@ * * Micro9-High has up to 64MB of 32-bit flash on CS1 * Micro9-Mid has up to 64MB of either 32-bit or 16-bit flash on CS1 - * Micro9-Lite uses a seperate MTD map driver for flash support + * Micro9-Lite uses a separate MTD map driver for flash support * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1 *************************************************************************/ static struct physmap_flash_data micro9_flash_data; diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c index 9438bf6613a3..ab3712c86d2b 100644 --- a/arch/arm/mach-nomadik/board-nhk8815.c +++ b/arch/arm/mach-nomadik/board-nhk8815.c @@ -38,7 +38,7 @@ #define SRC_CR_INIT_MASK 0x00007fff #define SRC_CR_INIT_VAL 0x2aaa8000 -/* These adresses span 16MB, so use three individual pages */ +/* These addresses span 16MB, so use three individual pages */ static struct resource nhk8815_nand_resources[] = { { .name = "nand_addr", diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 653e25be3dd8..d0cb5e940776 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -356,7 +356,7 @@ static struct resource ave_resources[] = { /* * The AVE3e requires two regions of 256MB that it considers * "invisible". The hardware will not be able to access these - * adresses, so they should never point to system RAM. + * addresses, so they should never point to system RAM. */ { .name = "AVE3e Reserved 0", @@ -571,7 +571,7 @@ static void __init u300_init_check_chip(void) /* * Some devices and their resources require reserved physical memory from * the end of the available RAM. This function traverses the list of devices - * and assigns actual adresses to these. + * and assigns actual addresses to these. */ static void __init u300_assign_physmem(void) { diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/mach-u300/include/mach/debug-macro.S index f3a1cbbeeab3..d591fe13ed13 100644 --- a/arch/arm/mach-u300/include/mach/debug-macro.S +++ b/arch/arm/mach-u300/include/mach/debug-macro.S @@ -11,7 +11,7 @@ #include .macro addruart,rx - /* If we move the adress using MMU, use this. */ + /* If we move the address using MMU, use this. */ mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? ldreq \rx, = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h index 652e2bbdaa20..dda19da037ad 100644 --- a/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h +++ b/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h @@ -78,7 +78,7 @@ extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, * others = Special functions (dependant on bank) * * Note, since the code to deal with the case where there are two control - * registers instead of one, we do not have a seperate set of functions for + * registers instead of one, we do not have a separate set of functions for * each case. */ extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h index 36a85f5000c8..a111ad871833 100644 --- a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h +++ b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h @@ -12,7 +12,7 @@ * published by the Free Software Foundation. */ -/* Note, this is a seperate header file as some of the clock framework +/* Note, this is a separate header file as some of the clock framework * needs to touch this if the clk_48m is used as the USB OHCI or other * peripheral source. */ diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h index 33d421d78bad..d623235ae961 100644 --- a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h +++ b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h @@ -135,7 +135,7 @@ struct s3c_cpufreq_config { * @locktime_m: The lock-time in uS for the MPLL. * @locktime_u: The lock-time in uS for the UPLL. * @locttime_bits: The number of bits each LOCKTIME field. - * @need_pll: Set if this driver needs to change the PLL values to acheive + * @need_pll: Set if this driver needs to change the PLL values to achieve * any frequency changes. This is really only need by devices like the * S3C2410 where there is no or limited divider between the PLL and the * ARMCLK. diff --git a/arch/cris/arch-v10/lib/old_checksum.c b/arch/cris/arch-v10/lib/old_checksum.c index 1734b467efa6..8f79163f1394 100644 --- a/arch/cris/arch-v10/lib/old_checksum.c +++ b/arch/cris/arch-v10/lib/old_checksum.c @@ -77,7 +77,7 @@ __wsum csum_partial(const void *p, int len, __wsum __sum) sum += *buff++; if (endMarker > buff) - sum += *(const u8 *)buff; /* add extra byte seperately */ + sum += *(const u8 *)buff; /* add extra byte separately */ BITOFF; return (__force __wsum)sum; diff --git a/arch/cris/arch-v32/mm/tlb.c b/arch/cris/arch-v32/mm/tlb.c index 6779bcb28ab0..c030d020660a 100644 --- a/arch/cris/arch-v32/mm/tlb.c +++ b/arch/cris/arch-v32/mm/tlb.c @@ -189,7 +189,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, spin_unlock(&mmu_context_lock); /* - * Remember the pgd for the fault handlers. Keep a seperate + * Remember the pgd for the fault handlers. Keep a separate * copy of it because current and active_mm might be invalid * at points where * there's still a need to derefer the pgd. */ diff --git a/arch/h8300/include/asm/io.h b/arch/h8300/include/asm/io.h index 33e842f3284b..c1a8df22080f 100644 --- a/arch/h8300/include/asm/io.h +++ b/arch/h8300/include/asm/io.h @@ -25,7 +25,7 @@ * memory location directly. */ /* ++roman: The assignments to temp. vars avoid that gcc sometimes generates - * two accesses to memory, which may be undesireable for some devices. + * two accesses to memory, which may be undesirable for some devices. */ /* diff --git a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c index ece1bf994499..c6c6d9381126 100644 --- a/arch/ia64/sn/kernel/setup.c +++ b/arch/ia64/sn/kernel/setup.c @@ -241,7 +241,7 @@ static void __cpuinit sn_check_for_wars(void) * Note: This stuff is duped here because Altix requires the PCDP to * locate a usable VGA device due to lack of proper ACPI support. Structures * could be used from drivers/firmware/pcdp.h, but it was decided that moving - * this file to a more public location just for Altix use was undesireable. + * this file to a more public location just for Altix use was undesirable. */ struct hcdp_uart_desc { diff --git a/arch/m68k/atari/atakeyb.c b/arch/m68k/atari/atakeyb.c index 4add96d13b19..5890897d28bf 100644 --- a/arch/m68k/atari/atakeyb.c +++ b/arch/m68k/atari/atakeyb.c @@ -121,7 +121,7 @@ KEYBOARD_STATE kb_state; * bytes have been lost and in which state of the packet structure we are now. * This usually causes keyboards bytes to be interpreted as mouse movements * and vice versa, which is very annoying. It seems better to throw away some - * bytes (that are usually mouse bytes) than to misinterpret them. Therefor I + * bytes (that are usually mouse bytes) than to misinterpret them. Therefore I * introduced the RESYNC state for IKBD data. In this state, the bytes up to * one that really looks like a key event (0x04..0xf2) or the start of a mouse * packet (0xf8..0xfb) are thrown away, but at most 2 bytes. This at least diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h index 359065d5a9f2..6e2413e518cb 100644 --- a/arch/m68k/include/asm/io_no.h +++ b/arch/m68k/include/asm/io_no.h @@ -16,7 +16,7 @@ * memory location directly. */ /* ++roman: The assignments to temp. vars avoid that gcc sometimes generates - * two accesses to memory, which may be undesireable for some devices. + * two accesses to memory, which may be undesirable for some devices. */ /* diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts index 65b8b4f27efe..d8b5d12fb663 100644 --- a/arch/powerpc/boot/dts/kmeter1.dts +++ b/arch/powerpc/boot/dts/kmeter1.dts @@ -490,7 +490,7 @@ compatible = "cfi-flash"; /* * The Intel P30 chip has 2 non-identical chips on - * one die, so we need to define 2 seperate regions + * one die, so we need to define 2 separate regions * that are scanned by physmap_of independantly. */ reg = <0 0x00000000 0x02000000 diff --git a/arch/s390/include/asm/cio.h b/arch/s390/include/asm/cio.h index e85679af54dd..e34347d567a6 100644 --- a/arch/s390/include/asm/cio.h +++ b/arch/s390/include/asm/cio.h @@ -20,7 +20,7 @@ /** * struct ccw1 - channel command word * @cmd_code: command code - * @flags: flags, like IDA adressing, etc. + * @flags: flags, like IDA addressing, etc. * @count: byte count * @cda: data address * diff --git a/arch/s390/kernel/sclp.S b/arch/s390/kernel/sclp.S index e27ca63076d1..27c1a2e236d1 100644 --- a/arch/s390/kernel/sclp.S +++ b/arch/s390/kernel/sclp.S @@ -221,7 +221,7 @@ _sclp_print: lh %r9,0(%r8) # update sccb length ar %r9,%r6 sth %r9,0(%r8) - ar %r7,%r6 # update current mto adress + ar %r7,%r6 # update current mto address ltr %r0,%r0 # more characters? jnz .LinitmtoS4 l %r2,.LwritedataS4-.LbaseS4(%r13)# write data diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c index 87f1760c0aa2..554e0b80bcde 100644 --- a/arch/sparc/kernel/leon_kernel.c +++ b/arch/sparc/kernel/leon_kernel.c @@ -124,7 +124,7 @@ void __init leon_init_timers(irq_handler_t counter_fn) if (!(LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->config) & (1< -/* return adress at 0 */ +/* return address at 0 */ #define in_blk 12 /* input byte array address parameter*/ #define out_blk 8 /* output byte array address parameter*/ @@ -230,8 +230,8 @@ twofish_enc_blk: push %edi mov tfm + 16(%esp), %ebp /* abuse the base pointer: set new base bointer to the crypto tfm */ - add $crypto_tfm_ctx_offset, %ebp /* ctx adress */ - mov in_blk+16(%esp),%edi /* input adress in edi */ + add $crypto_tfm_ctx_offset, %ebp /* ctx address */ + mov in_blk+16(%esp),%edi /* input address in edi */ mov (%edi), %eax mov b_offset(%edi), %ebx @@ -286,8 +286,8 @@ twofish_dec_blk: mov tfm + 16(%esp), %ebp /* abuse the base pointer: set new base bointer to the crypto tfm */ - add $crypto_tfm_ctx_offset, %ebp /* ctx adress */ - mov in_blk+16(%esp),%edi /* input adress in edi */ + add $crypto_tfm_ctx_offset, %ebp /* ctx address */ + mov in_blk+16(%esp),%edi /* input address in edi */ mov (%edi), %eax mov b_offset(%edi), %ebx diff --git a/arch/x86/crypto/twofish-x86_64-asm_64.S b/arch/x86/crypto/twofish-x86_64-asm_64.S index 35974a586615..573aa102542e 100644 --- a/arch/x86/crypto/twofish-x86_64-asm_64.S +++ b/arch/x86/crypto/twofish-x86_64-asm_64.S @@ -221,11 +221,11 @@ twofish_enc_blk: pushq R1 - /* %rdi contains the crypto tfm adress */ - /* %rsi contains the output adress */ - /* %rdx contains the input adress */ - add $crypto_tfm_ctx_offset, %rdi /* set ctx adress */ - /* ctx adress is moved to free one non-rex register + /* %rdi contains the crypto tfm address */ + /* %rsi contains the output address */ + /* %rdx contains the input address */ + add $crypto_tfm_ctx_offset, %rdi /* set ctx address */ + /* ctx address is moved to free one non-rex register as target for the 8bit high operations */ mov %rdi, %r11 @@ -274,11 +274,11 @@ twofish_enc_blk: twofish_dec_blk: pushq R1 - /* %rdi contains the crypto tfm adress */ - /* %rsi contains the output adress */ - /* %rdx contains the input adress */ - add $crypto_tfm_ctx_offset, %rdi /* set ctx adress */ - /* ctx adress is moved to free one non-rex register + /* %rdi contains the crypto tfm address */ + /* %rsi contains the output address */ + /* %rdx contains the input address */ + add $crypto_tfm_ctx_offset, %rdi /* set ctx address */ + /* ctx address is moved to free one non-rex register as target for the 8bit high operations */ mov %rdi, %r11 diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 2d8b5035371c..3d1e6f16b7a6 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -27,7 +27,7 @@ #define GET_CR2_INTO_RCX movq %cr2, %rcx #endif -/* we are not able to switch in one step to the final KERNEL ADRESS SPACE +/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE * because we need identity-mapped pages. * */ diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c index 2bbde6078143..fb99f7edb341 100644 --- a/arch/x86/kernel/pci-calgary_64.c +++ b/arch/x86/kernel/pci-calgary_64.c @@ -1309,7 +1309,7 @@ static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl) /* * get_tce_space_from_tar(): * Function for kdump case. Get the tce tables from first kernel - * by reading the contents of the base adress register of calgary iommu + * by reading the contents of the base address register of calgary iommu */ static void __init get_tce_space_from_tar(void) { diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 597683aa5ba0..dec8f68e3eda 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -50,7 +50,7 @@ u64 native_sched_clock(void) * unstable. We do this because unlike Time Of Day, * the scheduler clock tolerates small errors and it's * very important for it to be as fast as the platform - * can achive it. ) + * can achieve it. ) */ if (unlikely(tsc_disabled)) { /* No locking but a rare wrong value is not a big deal: */ diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S index 80d24c485fd3..77fc9f6dc016 100644 --- a/arch/xtensa/kernel/entry.S +++ b/arch/xtensa/kernel/entry.S @@ -104,7 +104,7 @@ * excsave has been restored, and * stack pointer (a1) has been set. * - * Note: _user_exception might be at an odd adress. Don't use call0..call12 + * Note: _user_exception might be at an odd address. Don't use call0..call12 */ ENTRY(user_exception) @@ -244,7 +244,7 @@ _user_exception: * excsave has been restored, and * stack pointer (a1) has been set. * - * Note: _kernel_exception might be at an odd adress. Don't use call0..call12 + * Note: _kernel_exception might be at an odd address. Don't use call0..call12 */ ENTRY(kernel_exception) diff --git a/block/bsg.c b/block/bsg.c index a9fd2d84b53a..46597a6bd112 100644 --- a/block/bsg.c +++ b/block/bsg.c @@ -260,7 +260,7 @@ bsg_map_hdr(struct bsg_device *bd, struct sg_io_v4 *hdr, fmode_t has_write_perm, return ERR_PTR(ret); /* - * map scatter-gather elements seperately and string them to request + * map scatter-gather elements separately and string them to request */ rq = blk_get_request(q, rw, GFP_KERNEL); if (!rq) diff --git a/drivers/acpi/dock.c b/drivers/acpi/dock.c index bbc2c1315c47..d7f363f9435f 100644 --- a/drivers/acpi/dock.c +++ b/drivers/acpi/dock.c @@ -605,7 +605,7 @@ register_hotplug_dock_device(acpi_handle handle, struct acpi_dock_ops *ops, list_for_each_entry(dock_station, &dock_stations, sibling) { /* * An ATA bay can be in a dock and itself can be ejected - * seperately, so there are two 'dock stations' which need the + * separately, so there are two 'dock stations' which need the * ops */ dd = find_dock_dependent_device(dock_station, handle); diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c index 741065c9da67..7f2c94a07c00 100644 --- a/drivers/ata/libata-sff.c +++ b/drivers/ata/libata-sff.c @@ -2258,7 +2258,7 @@ EXPORT_SYMBOL_GPL(ata_sff_postreset); * @qc: command * * Drain the FIFO and device of any stuck data following a command - * failing to complete. In some cases this is neccessary before a + * failing to complete. In some cases this is necessary before a * reset will recover the device. * */ diff --git a/drivers/ata/pata_acpi.c b/drivers/ata/pata_acpi.c index d8f35fe44421..9e33da9565d9 100644 --- a/drivers/ata/pata_acpi.c +++ b/drivers/ata/pata_acpi.c @@ -161,7 +161,7 @@ static void pacpi_set_dmamode(struct ata_port *ap, struct ata_device *adev) * * Called when the libata layer is about to issue a command. We wrap * this interface so that we can load the correct ATA timings if - * neccessary. + * necessary. */ static unsigned int pacpi_qc_issue(struct ata_queued_cmd *qc) diff --git a/drivers/ata/pata_hpt3x3.c b/drivers/ata/pata_hpt3x3.c index c86c71639a95..727a81ce4c9f 100644 --- a/drivers/ata/pata_hpt3x3.c +++ b/drivers/ata/pata_hpt3x3.c @@ -180,7 +180,7 @@ static void hpt3x3_init_chipset(struct pci_dev *dev) * @id: Entry in match table * * Perform basic initialisation. We set the device up so we access all - * ports via BAR4. This is neccessary to work around errata. + * ports via BAR4. This is necessary to work around errata. */ static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id) diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c index 1b392c9e8531..416aebb8b913 100644 --- a/drivers/ata/pata_pcmcia.c +++ b/drivers/ata/pata_pcmcia.c @@ -131,7 +131,7 @@ static unsigned int ata_data_xfer_8bit(struct ata_device *dev, * @qc: command * * Drain the FIFO and device of any stuck data following a command - * failing to complete. In some cases this is neccessary before a + * failing to complete. In some cases this is necessary before a * reset will recover the device. * */ diff --git a/drivers/block/drbd/drbd_int.h b/drivers/block/drbd/drbd_int.h index 2bf3a6ef3684..d9301e861d9f 100644 --- a/drivers/block/drbd/drbd_int.h +++ b/drivers/block/drbd/drbd_int.h @@ -95,7 +95,7 @@ extern char usermode_helper[]; /* All EEs on the free list should have ID_VACANT (== 0) * freshly allocated EEs get !ID_VACANT (== 1) - * so if it says "cannot dereference null pointer at adress 0x00000001", + * so if it says "cannot dereference null pointer at address 0x00000001", * it is most likely one of these :( */ #define ID_IN_SYNC (4711ULL) @@ -1171,7 +1171,7 @@ extern int drbd_bitmap_io(struct drbd_conf *mdev, int (*io_fn)(struct drbd_conf /* Meta data layout We reserve a 128MB Block (4k aligned) * either at the end of the backing device - * or on a seperate meta data device. */ + * or on a separate meta data device. */ #define MD_RESERVED_SECT (128LU << 11) /* 128 MB, unit sectors */ /* The following numbers are sectors */ diff --git a/drivers/block/drbd/drbd_req.h b/drivers/block/drbd/drbd_req.h index f22c1bc8ec7e..16119d7056cc 100644 --- a/drivers/block/drbd/drbd_req.h +++ b/drivers/block/drbd/drbd_req.h @@ -57,7 +57,7 @@ * * It may me handed over to the local disk subsystem. * It may be completed by the local disk subsystem, - * either sucessfully or with io-error. + * either successfully or with io-error. * In case it is a READ request, and it failed locally, * it may be retried remotely. * diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index 3999a5f25f38..45a22f9bfec2 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c @@ -269,7 +269,7 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem, j++; } } else { - /* sg may merge pages, but we have to seperate + /* sg may merge pages, but we have to separate * per-page addr for GTT */ unsigned int len, m; diff --git a/drivers/char/applicom.c b/drivers/char/applicom.c index fe2cb2f5db17..a7424bf7eacf 100644 --- a/drivers/char/applicom.c +++ b/drivers/char/applicom.c @@ -14,7 +14,7 @@ /* et passe en argument a acinit, mais est scrute sur le bus pour s'adapter */ /* au nombre de cartes presentes sur le bus. IOCL code 6 affichait V2.4.3 */ /* F.LAFORSE 28/11/95 creation de fichiers acXX.o avec les differentes */ -/* adresses de base des cartes, IOCTL 6 plus complet */ +/* addresses de base des cartes, IOCTL 6 plus complet */ /* J.PAGET le 19/08/96 copie de la version V2.6 en V2.8.0 sans modification */ /* de code autre que le texte V2.6.1 en V2.8.0 */ /*****************************************************************************/ diff --git a/drivers/char/hvc_iseries.c b/drivers/char/hvc_iseries.c index 936d05bf37fa..0794925d8042 100644 --- a/drivers/char/hvc_iseries.c +++ b/drivers/char/hvc_iseries.c @@ -353,7 +353,7 @@ static void hvc_close_event(struct HvLpEvent *event) if (!hvlpevent_is_int(event)) { printk(KERN_WARNING - "hvc: got unexpected close acknowlegement\n"); + "hvc: got unexpected close acknowledgement\n"); return; } diff --git a/drivers/char/hw_random/n2-drv.c b/drivers/char/hw_random/n2-drv.c index 9b3e09cd41f9..10f868eefaa6 100644 --- a/drivers/char/hw_random/n2-drv.c +++ b/drivers/char/hw_random/n2-drv.c @@ -71,7 +71,7 @@ MODULE_VERSION(DRV_MODULE_VERSION); * x22 + x21 + x17 + x15 + x13 + x12 + x11 + x7 + x5 + x + 1 * * The RNG_CTL_VCO value of each noise cell must be programmed - * seperately. This is why 4 control register values must be provided + * separately. This is why 4 control register values must be provided * to the hypervisor. During a write, the hypervisor writes them all, * one at a time, to the actual RNG_CTL register. The first three * values are used to setup the desired RNG_CTL_VCO for each entropy diff --git a/drivers/char/ip2/i2hw.h b/drivers/char/ip2/i2hw.h index 8aa6e7ab8d5b..c0ba6c05f0cd 100644 --- a/drivers/char/ip2/i2hw.h +++ b/drivers/char/ip2/i2hw.h @@ -559,7 +559,7 @@ Loadware may be sent to the board in two ways: 2) It may be hard-coded into your source by including a .h file (typically supplied by Computone), which declares a data array and initializes every - element. This acheives the same result as if an entire loadware file had + element. This achieves the same result as if an entire loadware file had been read into the array. This requires more data space in your program, but access to the file system diff --git a/drivers/char/pty.c b/drivers/char/pty.c index 385c44b3034f..5ee424817263 100644 --- a/drivers/char/pty.c +++ b/drivers/char/pty.c @@ -220,7 +220,7 @@ static void pty_set_termios(struct tty_struct *tty, * @tty: tty being resized * @ws: window size being set. * - * Update the termios variables and send the neccessary signals to + * Update the termios variables and send the necessary signals to * peform a terminal resize correctly */ diff --git a/drivers/char/tty_io.c b/drivers/char/tty_io.c index c6f3b48be9dd..56b11c1c7aeb 100644 --- a/drivers/char/tty_io.c +++ b/drivers/char/tty_io.c @@ -2026,7 +2026,7 @@ static int tiocgwinsz(struct tty_struct *tty, struct winsize __user *arg) * @rows: rows (character) * @cols: cols (character) * - * Update the termios variables and send the neccessary signals to + * Update the termios variables and send the necessary signals to * peform a terminal resize correctly */ diff --git a/drivers/char/vt.c b/drivers/char/vt.c index 94f530a29691..bd1d1164fec5 100644 --- a/drivers/char/vt.c +++ b/drivers/char/vt.c @@ -821,7 +821,7 @@ static inline int resize_screen(struct vc_data *vc, int width, int height, * * Resize a virtual console, clipping according to the actual constraints. * If the caller passes a tty structure then update the termios winsize - * information and perform any neccessary signal handling. + * information and perform any necessary signal handling. * * Caller must hold the console semaphore. Takes the termios mutex and * ctrl_lock of the tty IFF a tty is passed. diff --git a/drivers/dma/coh901318_lli.h b/drivers/dma/coh901318_lli.h index 7bf713b79c6b..7a5c80990e9e 100644 --- a/drivers/dma/coh901318_lli.h +++ b/drivers/dma/coh901318_lli.h @@ -30,7 +30,7 @@ struct device; * @pool: pool handle * @dev: dma device * @lli_nbr: number of lli:s in the pool - * @algin: adress alignemtn of lli:s + * @algin: address alignemtn of lli:s * returns 0 on success otherwise none zero */ int coh901318_pool_create(struct coh901318_pool *pool, diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index d7f8d8b4a4b8..52fb371784e1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -3544,7 +3544,7 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b * at which modes should be set up in the dual link style. * * Following the header, the BMP (ver 0xa) table has several records, - * indexed by a seperate xlat table, indexed in turn by the fp strap in + * indexed by a separate xlat table, indexed in turn by the fp strap in * EXTDEV_BOOT. Each record had a config byte, followed by 6 script * numbers for use by INIT_SUB which controlled panel init and power, * and finally a dword of ms to sleep between power off and on diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 6b9690418bc7..23664058690f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -544,7 +544,7 @@ struct drm_nouveau_private { uint32_t ramro_offset; uint32_t ramro_size; - /* base physical adresses */ + /* base physical addresses */ uint64_t fb_phys; uint64_t fb_available_size; uint64_t fb_mappable_pages; diff --git a/drivers/gpu/drm/via/via_irq.c b/drivers/gpu/drm/via/via_irq.c index 5935b8842e86..34079f251cd4 100644 --- a/drivers/gpu/drm/via/via_irq.c +++ b/drivers/gpu/drm/via/via_irq.c @@ -150,7 +150,7 @@ irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS) cur_irq++; } - /* Acknowlege interrupts */ + /* Acknowledge interrupts */ VIA_WRITE(VIA_REG_INTERRUPT, status); @@ -165,7 +165,7 @@ static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv) u32 status; if (dev_priv) { - /* Acknowlege interrupts */ + /* Acknowledge interrupts */ status = VIA_READ(VIA_REG_INTERRUPT); VIA_WRITE(VIA_REG_INTERRUPT, status | dev_priv->irq_pending_mask); diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c index 7647a20523a0..90ffbf6f9d4f 100644 --- a/drivers/i2c/busses/i2c-pxa.c +++ b/drivers/i2c/busses/i2c-pxa.c @@ -12,7 +12,7 @@ * * History: * Apr 2002: Initial version [CS] - * Jun 2002: Properly seperated algo/adap [FB] + * Jun 2002: Properly separated algo/adap [FB] * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] * Jan 2003: added limited signal handling [Kai-Uwe Bloem] * Sep 2004: Major rework to ensure efficient bus handling [RMK] diff --git a/drivers/infiniband/hw/ehca/ehca_qes.h b/drivers/infiniband/hw/ehca/ehca_qes.h index 5d28e3e98a20..90c4efa67586 100644 --- a/drivers/infiniband/hw/ehca/ehca_qes.h +++ b/drivers/infiniband/hw/ehca/ehca_qes.h @@ -46,7 +46,7 @@ #include "ehca_tools.h" -/* virtual scatter gather entry to specify remote adresses with length */ +/* virtual scatter gather entry to specify remote addresses with length */ struct ehca_vsgentry { u64 vaddr; u32 lkey; @@ -148,7 +148,7 @@ struct ehca_wqe { u32 immediate_data; union { struct { - u64 remote_virtual_adress; + u64 remote_virtual_address; u32 rkey; u32 reserved; u64 atomic_1st_op_dma_len; diff --git a/drivers/infiniband/hw/ehca/ehca_reqs.c b/drivers/infiniband/hw/ehca/ehca_reqs.c index e3ec7fdd67bd..9a3fbfca9b41 100644 --- a/drivers/infiniband/hw/ehca/ehca_reqs.c +++ b/drivers/infiniband/hw/ehca/ehca_reqs.c @@ -269,7 +269,7 @@ static inline int ehca_write_swqe(struct ehca_qp *qp, /* no break is intentional here */ case IB_QPT_RC: /* TODO: atomic not implemented */ - wqe_p->u.nud.remote_virtual_adress = + wqe_p->u.nud.remote_virtual_address = send_wr->wr.rdma.remote_addr; wqe_p->u.nud.rkey = send_wr->wr.rdma.rkey; diff --git a/drivers/input/misc/yealink.h b/drivers/input/misc/yealink.h index 48af0be9cbdf..1e0f52397010 100644 --- a/drivers/input/misc/yealink.h +++ b/drivers/input/misc/yealink.h @@ -127,7 +127,7 @@ struct yld_ctl_packet { * yld_status struct. */ -/* LCD, each segment must be driven seperately. +/* LCD, each segment must be driven separately. * * Layout: * diff --git a/drivers/isdn/i4l/isdn_common.c b/drivers/isdn/i4l/isdn_common.c index adb1e8c36b46..00c60e2e0ff7 100644 --- a/drivers/isdn/i4l/isdn_common.c +++ b/drivers/isdn/i4l/isdn_common.c @@ -1347,7 +1347,7 @@ isdn_ioctl(struct inode *inode, struct file *file, uint cmd, ulong arg) /* * isdn net devices manage lots of configuration variables as linked lists. * Those lists must only be manipulated from user space. Some of the ioctl's - * service routines access user space and are not atomic. Therefor, ioctl's + * service routines access user space and are not atomic. Therefore, ioctl's * manipulating the lists and ioctl's sleeping while accessing the lists * are serialized by means of a semaphore. */ diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.h b/drivers/media/dvb/dvb-core/dvb_frontend.h index 52e4ce4304ee..80dda308ff74 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.h +++ b/drivers/media/dvb/dvb-core/dvb_frontend.h @@ -214,14 +214,14 @@ struct dvb_tuner_ops { int (*get_status)(struct dvb_frontend *fe, u32 *status); int (*get_rf_strength)(struct dvb_frontend *fe, u16 *strength); - /** These are provided seperately from set_params in order to facilitate silicon - * tuners which require sophisticated tuning loops, controlling each parameter seperately. */ + /** These are provided separately from set_params in order to facilitate silicon + * tuners which require sophisticated tuning loops, controlling each parameter separately. */ int (*set_frequency)(struct dvb_frontend *fe, u32 frequency); int (*set_bandwidth)(struct dvb_frontend *fe, u32 bandwidth); /* - * These are provided seperately from set_params in order to facilitate silicon - * tuners which require sophisticated tuning loops, controlling each parameter seperately. + * These are provided separately from set_params in order to facilitate silicon + * tuners which require sophisticated tuning loops, controlling each parameter separately. */ int (*set_state)(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state); int (*get_state)(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state); diff --git a/drivers/media/video/bt8xx/bttv-cards.c b/drivers/media/video/bt8xx/bttv-cards.c index 12279f6d9bc4..716870ae85d5 100644 --- a/drivers/media/video/bt8xx/bttv-cards.c +++ b/drivers/media/video/bt8xx/bttv-cards.c @@ -4404,7 +4404,7 @@ static void rv605_muxsel(struct bttv *btv, unsigned int input) /* Tibet Systems 'Progress DVR' CS16 muxsel helper [Chris Fanning] * * The CS16 (available on eBay cheap) is a PCI board with four Fusion - * 878A chips, a PCI bridge, an Atmel microcontroller, four sync seperator + * 878A chips, a PCI bridge, an Atmel microcontroller, four sync separator * chips, ten eight input analog multiplexors, a not chip and a few * other components. * @@ -4426,7 +4426,7 @@ static void rv605_muxsel(struct bttv *btv, unsigned int input) * * There is an ATMEL microcontroller with an 8031 core on board. I have not * determined what function (if any) it provides. With the microcontroller - * and sync seperator chips a guess is that it might have to do with video + * and sync separator chips a guess is that it might have to do with video * switching and maybe some digital I/O. */ static void tibetCS16_muxsel(struct bttv *btv, unsigned int input) diff --git a/drivers/media/video/gspca/ov519.c b/drivers/media/video/gspca/ov519.c index b4f965731244..e5e4c4440d39 100644 --- a/drivers/media/video/gspca/ov519.c +++ b/drivers/media/video/gspca/ov519.c @@ -503,7 +503,7 @@ static const struct v4l2_pix_format ovfx2_ov3610_mode[] = { /* * The FX2 chip does not give us a zero length read at end of frame. * It does, however, give a short read at the end of a frame, if - * neccessary, rather than run two frames together. + * necessary, rather than run two frames together. * * By choosing the right bulk transfer size, we are guaranteed to always * get a short read for the last read of each frame. Frame sizes are diff --git a/drivers/media/video/pwc/philips.txt b/drivers/media/video/pwc/philips.txt index f9f3584281d8..d38dd791511e 100644 --- a/drivers/media/video/pwc/philips.txt +++ b/drivers/media/video/pwc/philips.txt @@ -33,7 +33,7 @@ a lot of extra information, a FAQ, and the binary plugin 'PWCX'. This plugin contains decompression routines that allow you to use higher image sizes and framerates; in addition the webcam uses less bandwidth on the USB bus (handy if you want to run more than 1 camera simultaneously). These routines fall -under a NDA, and may therefor not be distributed as source; however, its use +under a NDA, and may therefore not be distributed as source; however, its use is completely optional. You can build this code either into your kernel, or as a module. I recommend diff --git a/drivers/media/video/sn9c102/sn9c102_sensor.h b/drivers/media/video/sn9c102/sn9c102_sensor.h index 4af7382da5c5..494957b10bac 100644 --- a/drivers/media/video/sn9c102/sn9c102_sensor.h +++ b/drivers/media/video/sn9c102/sn9c102_sensor.h @@ -120,7 +120,7 @@ extern int sn9c102_write_regs(struct sn9c102_device*, const u8 valreg[][2], /* Write multiple registers with constant values. For example: sn9c102_write_const_regs(cam, {0x00, 0x14}, {0x60, 0x17}, {0x0f, 0x18}); - Register adresses must be < 256. + Register addresses must be < 256. */ #define sn9c102_write_const_regs(sn9c102_device, data...) \ ({ static const u8 _valreg[][2] = {data}; \ diff --git a/drivers/media/video/tea6420.c b/drivers/media/video/tea6420.c index 0446524d3543..6bf6bc7dbc7f 100644 --- a/drivers/media/video/tea6420.c +++ b/drivers/media/video/tea6420.c @@ -6,7 +6,7 @@ The tea6420 is a bus controlled audio-matrix with 5 stereo inputs, 4 stereo outputs and gain control for each output. - It is cascadable, i.e. it can be found at the adresses 0x98 + It is cascadable, i.e. it can be found at the addresses 0x98 and 0x9a on the i2c-bus. For detailed informations download the specifications directly diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c index 0cc5eeff5ee8..10491e4e305d 100644 --- a/drivers/mfd/sm501.c +++ b/drivers/mfd/sm501.c @@ -523,7 +523,7 @@ unsigned long sm501_set_clock(struct device *dev, unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK); unsigned char reg; unsigned int pll_reg = 0; - unsigned long sm501_freq; /* the actual frequency acheived */ + unsigned long sm501_freq; /* the actual frequency achieved */ struct sm501_clock to; @@ -533,7 +533,7 @@ unsigned long sm501_set_clock(struct device *dev, switch (clksrc) { case SM501_CLOCK_P2XCLK: - /* This clock is divided in half so to achive the + /* This clock is divided in half so to achieve the * requested frequency the value must be multiplied by * 2. This clock also has an additional pre divisor */ @@ -562,7 +562,7 @@ unsigned long sm501_set_clock(struct device *dev, break; case SM501_CLOCK_V2XCLK: - /* This clock is divided in half so to achive the + /* This clock is divided in half so to achieve the * requested frequency the value must be multiplied by 2. */ sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); @@ -648,7 +648,7 @@ unsigned long sm501_find_clock(struct device *dev, unsigned long req_freq) { struct sm501_devdata *sm = dev_get_drvdata(dev); - unsigned long sm501_freq; /* the frequency achiveable by the 501 */ + unsigned long sm501_freq; /* the frequency achieveable by the 501 */ struct sm501_clock to; switch (clksrc) { diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c index 60a2b69e54f5..16cc91c827c9 100644 --- a/drivers/mmc/host/mxcmmc.c +++ b/drivers/mmc/host/mxcmmc.c @@ -4,7 +4,7 @@ * This is a driver for the SDHC controller found in Freescale MX2/MX3 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). * Unlike the hardware found on MX1, this hardware just works and does - * not need all the quirks found in imxmmc.c, hence the seperate driver. + * not need all the quirks found in imxmmc.c, hence the separate driver. * * Copyright (C) 2008 Sascha Hauer, Pengutronix * Copyright (C) 2006 Pavel Pisa, PiKRON diff --git a/drivers/mtd/chips/jedec_probe.c b/drivers/mtd/chips/jedec_probe.c index 1bec5e1ce6ac..8db1148dfa47 100644 --- a/drivers/mtd/chips/jedec_probe.c +++ b/drivers/mtd/chips/jedec_probe.c @@ -226,7 +226,7 @@ struct unlock_addr { * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore, * should not be used. The problem is that structures with * initializers have extra fields initialized to 0. It is _very_ - * desireable to have the unlock address entries for unsupported + * desirable to have the unlock address entries for unsupported * data widths automatically initialized - that means that * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here * must go unused. diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c index 087bcd745bb7..7d1cca7a31a9 100644 --- a/drivers/mtd/nand/bcm_umi_nand.c +++ b/drivers/mtd/nand/bcm_umi_nand.c @@ -381,7 +381,7 @@ static int __devinit bcm_umi_nand_probe(struct platform_device *pdev) if (!r) return -ENXIO; - /* map physical adress */ + /* map physical address */ bcm_umi_io_base = ioremap(r->start, r->end - r->start + 1); if (!bcm_umi_io_base) { @@ -525,7 +525,7 @@ static int bcm_umi_nand_remove(struct platform_device *pdev) /* Release resources, unregister device */ nand_release(board_mtd); - /* unmap physical adress */ + /* unmap physical address */ iounmap(bcm_umi_io_base); /* Free the MTD device structure */ diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 45dec5770da0..b2900d8406d3 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -507,7 +507,7 @@ static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) * MXC NANDFC can only perform full page+spare or * spare-only read/write. When the upper layers * layers perform a read/write buf operation, - * we will used the saved column adress to index into + * we will used the saved column address to index into * the full page. */ send_addr(host, 0, page_addr == -1); diff --git a/drivers/net/atlx/atl2.h b/drivers/net/atlx/atl2.h index d918bbe621ea..927e4de6474d 100644 --- a/drivers/net/atlx/atl2.h +++ b/drivers/net/atlx/atl2.h @@ -442,7 +442,7 @@ struct atl2_hw { struct atl2_ring_header { /* pointer to the descriptor ring memory */ void *desc; - /* physical adress of the descriptor ring */ + /* physical address of the descriptor ring */ dma_addr_t dma; /* length of descriptor ring in bytes */ unsigned int size; diff --git a/drivers/net/chelsio/sge.c b/drivers/net/chelsio/sge.c index 109d2783e4d8..bef02330464d 100644 --- a/drivers/net/chelsio/sge.c +++ b/drivers/net/chelsio/sge.c @@ -248,7 +248,7 @@ static void restart_sched(unsigned long); * * Interrupts are handled by a single CPU and it is likely that on a MP system * the application is migrated to another CPU. In that scenario, we try to - * seperate the RX(in irq context) and TX state in order to decrease memory + * separate the RX(in irq context) and TX state in order to decrease memory * contention. */ struct sge { diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c index 02d67d047d96..dc4eb87309c5 100644 --- a/drivers/net/e1000e/82571.c +++ b/drivers/net/e1000e/82571.c @@ -1363,7 +1363,7 @@ static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) * * 1) down * 2) autoneg_progress - * 3) autoneg_complete (the link sucessfully autonegotiated) + * 3) autoneg_complete (the link successfully autonegotiated) * 4) forced_up (the link has been forced up, it did not autonegotiate) * **/ diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c index 2fa9b36a2c5a..3af0b1b82832 100644 --- a/drivers/net/e1000e/lib.c +++ b/drivers/net/e1000e/lib.c @@ -587,7 +587,7 @@ s32 e1000e_check_for_serdes_link(struct e1000_hw *hw) if (!(rxcw & E1000_RXCW_IV)) { mac->serdes_has_link = true; e_dbg("SERDES: Link up - autoneg " - "completed sucessfully.\n"); + "completed successfully.\n"); } else { mac->serdes_has_link = false; e_dbg("SERDES: Link down - invalid" diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c index 997124d2992a..e2ce8f8a21a7 100644 --- a/drivers/net/igb/igb_main.c +++ b/drivers/net/igb/igb_main.c @@ -674,7 +674,7 @@ static void igb_set_interrupt_capability(struct igb_adapter *adapter) /* start with one vector for every rx queue */ numvecs = adapter->num_rx_queues; - /* if tx handler is seperate add 1 for every tx queue */ + /* if tx handler is separate add 1 for every tx queue */ if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) numvecs += adapter->num_tx_queues; diff --git a/drivers/net/irda/sa1100_ir.c b/drivers/net/irda/sa1100_ir.c index c412e8026173..1dcdce0631aa 100644 --- a/drivers/net/irda/sa1100_ir.c +++ b/drivers/net/irda/sa1100_ir.c @@ -331,7 +331,7 @@ static int sa1100_irda_resume(struct platform_device *pdev) * If we missed a speed change, initialise at the new speed * directly. It is debatable whether this is actually * required, but in the interests of continuing from where - * we left off it is desireable. The converse argument is + * we left off it is desirable. The converse argument is * that we should re-negotiate at 9600 baud again. */ if (si->newspeed) { diff --git a/drivers/net/qlge/qlge_ethtool.c b/drivers/net/qlge/qlge_ethtool.c index 058fa0a48c6f..b8d21ab212c6 100644 --- a/drivers/net/qlge/qlge_ethtool.c +++ b/drivers/net/qlge/qlge_ethtool.c @@ -402,7 +402,7 @@ static int ql_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) u32 wol = 0; status = ql_mb_wol_mode(qdev, wol); QPRINTK(qdev, DRV, ERR, "WOL %s (wol code 0x%x) on %s\n", - (status == 0) ? "cleared sucessfully" : "clear failed", + (status == 0) ? "cleared successfully" : "clear failed", wol, qdev->ndev->name); } diff --git a/drivers/net/qlge/qlge_main.c b/drivers/net/qlge/qlge_main.c index 894a7c84faef..a35845b48ea4 100644 --- a/drivers/net/qlge/qlge_main.c +++ b/drivers/net/qlge/qlge_main.c @@ -3517,7 +3517,7 @@ int ql_wol(struct ql_adapter *qdev) wol |= MB_WOL_MODE_ON; status = ql_mb_wol_mode(qdev, wol); QPRINTK(qdev, DRV, ERR, "WOL %s (wol code 0x%x) on %s\n", - (status == 0) ? "Sucessfully set" : "Failed", wol, + (status == 0) ? "Successfully set" : "Failed", wol, qdev->ndev->name); } diff --git a/drivers/net/sfc/regs.h b/drivers/net/sfc/regs.h index 89d606fe9248..18a3be428348 100644 --- a/drivers/net/sfc/regs.h +++ b/drivers/net/sfc/regs.h @@ -95,7 +95,7 @@ #define FRF_AA_INT_ACK_KER_FIELD_LBN 0 #define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32 -/* INT_ISR0_REG: Function 0 Interrupt Acknowlege Status register */ +/* INT_ISR0_REG: Function 0 Interrupt Acknowledge Status register */ #define FR_BZ_INT_ISR0 0x00000090 #define FRF_BZ_INT_ISR_REG_LBN 0 #define FRF_BZ_INT_ISR_REG_WIDTH 64 diff --git a/drivers/net/smsc9420.c b/drivers/net/smsc9420.c index 12f0f5d74e3c..2ae1972bcb46 100644 --- a/drivers/net/smsc9420.c +++ b/drivers/net/smsc9420.c @@ -1348,7 +1348,7 @@ static int smsc9420_open(struct net_device *dev) netif_carrier_off(dev); - /* disable, mask and acknowlege all interrupts */ + /* disable, mask and acknowledge all interrupts */ spin_lock_irqsave(&pd->int_lock, flags); int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); smsc9420_reg_write(pd, INT_CFG, int_cfg); diff --git a/drivers/net/spider_net.c b/drivers/net/spider_net.c index 218524857bfc..839b1f065d3c 100644 --- a/drivers/net/spider_net.c +++ b/drivers/net/spider_net.c @@ -474,7 +474,7 @@ spider_net_prepare_rx_descr(struct spider_net_card *card, * spider_net_enable_rxchtails - sets RX dmac chain tail addresses * @card: card structure * - * spider_net_enable_rxchtails sets the RX DMAC chain tail adresses in the + * spider_net_enable_rxchtails sets the RX DMAC chain tail addresses in the * chip by writing to the appropriate register. DMA is enabled in * spider_net_enable_rxdmac. */ @@ -1820,7 +1820,7 @@ spider_net_enable_card(struct spider_net_card *card) spider_net_write_reg(card, SPIDER_NET_ECMODE, SPIDER_NET_ECMODE_VALUE); - /* set chain tail adress for RX chains and + /* set chain tail address for RX chains and * enable DMA */ spider_net_enable_rxchtails(card); spider_net_enable_rxdmac(card); diff --git a/drivers/net/sungem.c b/drivers/net/sungem.c index b571a1babab9..a88fcb39ba15 100644 --- a/drivers/net/sungem.c +++ b/drivers/net/sungem.c @@ -782,7 +782,7 @@ static int gem_rx(struct gem *gp, int work_to_do) break; /* When writing back RX descriptor, GEM writes status - * then buffer address, possibly in seperate transactions. + * then buffer address, possibly in separate transactions. * If we don't wait for the chip to write both, we could * post a new buffer to this descriptor then have GEM spam * on the buffer address. We sync on the RX completion diff --git a/drivers/net/tehuti.c b/drivers/net/tehuti.c index 80b404f2b938..ed4e9c42935c 100644 --- a/drivers/net/tehuti.c +++ b/drivers/net/tehuti.c @@ -1857,7 +1857,7 @@ static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size) * @data - desc's data * @size - desc's size * - * NOTE: this func does check for available space and, if neccessary, waits for + * NOTE: this func does check for available space and, if necessary, waits for * NIC to read existing data before writing new one. */ static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size) diff --git a/drivers/net/tokenring/tms380tr.c b/drivers/net/tokenring/tms380tr.c index e3c42f5ac4a9..4e4c402319c9 100644 --- a/drivers/net/tokenring/tms380tr.c +++ b/drivers/net/tokenring/tms380tr.c @@ -693,7 +693,7 @@ static netdev_tx_t tms380tr_hardware_send_packet(struct sk_buff *skb, * NOTE: This function should be used whenever the status of any TPL must be * modified by the driver, because the compiler may otherwise change the * order of instructions such that writing the TPL status may be executed at - * an undesireable time. When this function is used, the status is always + * an undesirable time. When this function is used, the status is always * written when the function is called. */ static void tms380tr_write_tpl_status(TPL *tpl, unsigned int Status) @@ -2266,7 +2266,7 @@ static void tms380tr_rcv_status_irq(struct net_device *dev) * This function should be used whenever the status of any RPL must be * modified by the driver, because the compiler may otherwise change the * order of instructions such that writing the RPL status may be executed - * at an undesireable time. When this function is used, the status is + * at an undesirable time. When this function is used, the status is * always written when the function is called. */ static void tms380tr_write_rpl_status(RPL *rpl, unsigned int Status) diff --git a/drivers/net/tun.c b/drivers/net/tun.c index 2834a01bae24..e572ecc09a44 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -1365,7 +1365,7 @@ static int tun_chr_close(struct inode *inode, struct file *file) __tun_detach(tun); - /* If desireable, unregister the netdevice. */ + /* If desirable, unregister the netdevice. */ if (!(tun->flags & TUN_PERSIST)) { rtnl_lock(); if (dev->reg_state == NETREG_REGISTERED) diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c index eb8fe7e16c6c..8eec97799e05 100644 --- a/drivers/net/ucc_geth.c +++ b/drivers/net/ucc_geth.c @@ -429,7 +429,7 @@ static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth, ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); /* Ethernet frames are defined in Little Endian mode, - therefor to insert */ + therefore to insert */ /* the address to the hash (Big Endian mode), we reverse the bytes.*/ set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr); diff --git a/drivers/net/wimax/i2400m/fw.c b/drivers/net/wimax/i2400m/fw.c index 64cdfeb299ca..6c459f5cb5df 100644 --- a/drivers/net/wimax/i2400m/fw.c +++ b/drivers/net/wimax/i2400m/fw.c @@ -612,7 +612,7 @@ ssize_t i2400m_bm_cmd(struct i2400m *i2400m, goto error_wait_for_ack; } rx_bytes = result; - /* verify the ack and read more if neccessary [result is the + /* verify the ack and read more if necessary [result is the * final amount of bytes we get in the ack] */ result = __i2400m_bm_ack_verify(i2400m, opcode, ack, ack_size, flags); if (result < 0) diff --git a/drivers/net/wimax/i2400m/i2400m.h b/drivers/net/wimax/i2400m/i2400m.h index 04df9bbe340f..820b128705ec 100644 --- a/drivers/net/wimax/i2400m/i2400m.h +++ b/drivers/net/wimax/i2400m/i2400m.h @@ -627,7 +627,7 @@ enum i2400m_bm_cmd_flags { * @I2400M_BRI_NO_REBOOT: Do not reboot the device and proceed * directly to wait for a reboot barker from the device. * @I2400M_BRI_MAC_REINIT: We need to reinitialize the boot - * rom after reading the MAC adress. This is quite a dirty hack, + * rom after reading the MAC address. This is quite a dirty hack, * if you ask me -- the device requires the bootrom to be * intialized after reading the MAC address. */ diff --git a/drivers/net/wimax/i2400m/sdio.c b/drivers/net/wimax/i2400m/sdio.c index 76a50ac02ebb..14f876b1358b 100644 --- a/drivers/net/wimax/i2400m/sdio.c +++ b/drivers/net/wimax/i2400m/sdio.c @@ -304,7 +304,7 @@ error_kzalloc: * * The device will be fully reset internally, but won't be * disconnected from the bus (so no reenumeration will - * happen). Firmware upload will be neccessary. + * happen). Firmware upload will be necessary. * * The device will send a reboot barker that will trigger the driver * to reinitialize the state via __i2400m_dev_reset_handle. @@ -314,7 +314,7 @@ error_kzalloc: * * The device will be fully reset internally, disconnected from the * bus an a reenumeration will happen. Firmware upload will be - * neccessary. Thus, we don't do any locking or struct + * necessary. Thus, we don't do any locking or struct * reinitialization, as we are going to be fully disconnected and * reenumerated. * diff --git a/drivers/net/wimax/i2400m/usb.c b/drivers/net/wimax/i2400m/usb.c index 98f4f8c5fb68..99f04c475898 100644 --- a/drivers/net/wimax/i2400m/usb.c +++ b/drivers/net/wimax/i2400m/usb.c @@ -246,7 +246,7 @@ error_kzalloc: * * The device will be fully reset internally, but won't be * disconnected from the USB bus (so no reenumeration will - * happen). Firmware upload will be neccessary. + * happen). Firmware upload will be necessary. * * The device will send a reboot barker in the notification endpoint * that will trigger the driver to reinitialize the state @@ -257,7 +257,7 @@ error_kzalloc: * * The device will be fully reset internally, disconnected from the * USB bus an a reenumeration will happen. Firmware upload will be - * neccessary. Thus, we don't do any locking or struct + * necessary. Thus, we don't do any locking or struct * reinitialization, as we are going to be fully disconnected and * reenumerated. * diff --git a/drivers/net/wireless/ath/ar9170/main.c b/drivers/net/wireless/ath/ar9170/main.c index f9d6db8d013e..46a1e19c6787 100644 --- a/drivers/net/wireless/ath/ar9170/main.c +++ b/drivers/net/wireless/ath/ar9170/main.c @@ -2535,7 +2535,7 @@ void *ar9170_alloc(size_t priv_size) /* * this buffer is used for rx stream reconstruction. * Under heavy load this device (or the transport layer?) - * tends to split the streams into seperate rx descriptors. + * tends to split the streams into separate rx descriptors. */ skb = __dev_alloc_skb(AR9170_MAX_RX_BUFFER_SIZE, GFP_KERNEL); diff --git a/drivers/net/wireless/iwmc3200wifi/lmac.h b/drivers/net/wireless/iwmc3200wifi/lmac.h index a3a79b5e2898..a855a99e49b8 100644 --- a/drivers/net/wireless/iwmc3200wifi/lmac.h +++ b/drivers/net/wireless/iwmc3200wifi/lmac.h @@ -262,7 +262,7 @@ struct iwm_ct_kill_cfg_cmd { /* Power Management */ #define POWER_TABLE_CMD 0x77 -#define SAVE_RESTORE_ADRESS_CMD 0x78 +#define SAVE_RESTORE_ADDRESS_CMD 0x78 #define REPLY_WATERMARK_CMD 0x79 #define PM_DEBUG_STATISTIC_NOTIFIC 0x7B #define PD_FLUSH_N_NOTIFICATION 0x7C diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c index 83f2592c59de..486c93559c29 100644 --- a/drivers/net/wireless/rt2x00/rt2500usb.c +++ b/drivers/net/wireless/rt2x00/rt2500usb.c @@ -368,7 +368,7 @@ static int rt2500usb_config_key(struct rt2x00_dev *rt2x00dev, /* * The encryption key doesn't fit within the CSR cache, - * this means we should allocate it seperately and use + * this means we should allocate it separately and use * rt2x00usb_vendor_request() to send the key to the hardware. */ reg = KEY_ENTRY(key->hw_key_idx); @@ -382,7 +382,7 @@ static int rt2500usb_config_key(struct rt2x00_dev *rt2x00dev, /* * The driver does not support the IV/EIV generation * in hardware. However it demands the data to be provided - * both seperately as well as inside the frame. + * both separately as well as inside the frame. * We already provided the CONFIG_CRYPTO_COPY_IV to rt2x00lib * to ensure rt2x00lib will not strip the data from the * frame after the copy, now we must tell mac80211 diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c index ab95346cf6a3..2e5c8a13758b 100644 --- a/drivers/net/wireless/rt2x00/rt2800usb.c +++ b/drivers/net/wireless/rt2x00/rt2800usb.c @@ -100,7 +100,7 @@ static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev, * There are 2 variations of the rt2870 firmware. * a) size: 4kb * b) size: 8kb - * Note that (b) contains 2 seperate firmware blobs of 4k + * Note that (b) contains 2 separate firmware blobs of 4k * within the file. The first blob is the same firmware as (a), * but the second blob is for the additional chipsets. */ @@ -118,7 +118,7 @@ static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev, /* * 8kb firmware files must be checked as if it were - * 2 seperate firmware files. + * 2 separate firmware files. */ while (offset < len) { if (!rt2800usb_check_crc(data + offset, 4096)) diff --git a/drivers/net/wireless/rt2x00/rt2x00debug.c b/drivers/net/wireless/rt2x00/rt2x00debug.c index 7d323a763b54..afee806affc2 100644 --- a/drivers/net/wireless/rt2x00/rt2x00debug.c +++ b/drivers/net/wireless/rt2x00/rt2x00debug.c @@ -109,7 +109,7 @@ struct rt2x00debug_intf { /* * HW crypto statistics. - * All statistics are stored seperately per cipher type. + * All statistics are stored separately per cipher type. */ struct rt2x00debug_crypto crypto_stats[CIPHER_MAX]; diff --git a/drivers/net/wireless/rt2x00/rt2x00dev.c b/drivers/net/wireless/rt2x00/rt2x00dev.c index 265e66dba552..5e1d5167fff4 100644 --- a/drivers/net/wireless/rt2x00/rt2x00dev.c +++ b/drivers/net/wireless/rt2x00/rt2x00dev.c @@ -397,7 +397,7 @@ void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev, /* * Hardware might have stripped the IV/EIV/ICV data, * in that case it is possible that the data was - * provided seperately (through hardware descriptor) + * provided separately (through hardware descriptor) * in which case we should reinsert the data into the frame. */ if ((rxdesc.dev_flags & RXDONE_CRYPTO_IV) && diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.c b/drivers/net/wireless/rt2x00/rt2x00queue.c index 9915a09141ef..38ffca9b0fe7 100644 --- a/drivers/net/wireless/rt2x00/rt2x00queue.c +++ b/drivers/net/wireless/rt2x00/rt2x00queue.c @@ -502,7 +502,7 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb, /* * When hardware encryption is supported, and this frame * is to be encrypted, we should strip the IV/EIV data from - * the frame so we can provide it to the driver seperately. + * the frame so we can provide it to the driver separately. */ if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) && !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) { diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c index 0ca589306d71..99459db61efd 100644 --- a/drivers/net/wireless/rt2x00/rt61pci.c +++ b/drivers/net/wireless/rt2x00/rt61pci.c @@ -476,7 +476,7 @@ static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, * The driver does not support the IV/EIV generation * in hardware. However it doesn't support the IV/EIV * inside the ieee80211 frame either, but requires it - * to be provided seperately for the descriptor. + * to be provided separately for the descriptor. * rt2x00lib will cut the IV/EIV data out of all frames * given to us by mac80211, but we must tell mac80211 * to generate the IV/EIV data. diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c index ced3b6ab5e16..527368a45fd5 100644 --- a/drivers/net/wireless/rt2x00/rt73usb.c +++ b/drivers/net/wireless/rt2x00/rt73usb.c @@ -339,7 +339,7 @@ static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev, * The driver does not support the IV/EIV generation * in hardware. However it doesn't support the IV/EIV * inside the ieee80211 frame either, but requires it - * to be provided seperately for the descriptor. + * to be provided separately for the descriptor. * rt2x00lib will cut the IV/EIV data out of all frames * given to us by mac80211, but we must tell mac80211 * to generate the IV/EIV data. @@ -439,7 +439,7 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev, * The driver does not support the IV/EIV generation * in hardware. However it doesn't support the IV/EIV * inside the ieee80211 frame either, but requires it - * to be provided seperately for the descriptor. + * to be provided separately for the descriptor. * rt2x00lib will cut the IV/EIV data out of all frames * given to us by mac80211, but we must tell mac80211 * to generate the IV/EIV data. @@ -1665,7 +1665,7 @@ static void rt73usb_fill_rxdone(struct queue_entry *entry, /* * Hardware has stripped IV/EIV data from 802.11 frame during - * decryption. It has provided the data seperately but rt2x00lib + * decryption. It has provided the data separately but rt2x00lib * should decide if it should be reinserted. */ rxdesc->flags |= RX_FLAG_IV_STRIPPED; diff --git a/drivers/s390/char/raw3270.c b/drivers/s390/char/raw3270.c index 62ddf5202b79..2a4c566456e7 100644 --- a/drivers/s390/char/raw3270.c +++ b/drivers/s390/char/raw3270.c @@ -373,7 +373,7 @@ raw3270_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb) rq->rc = ccw_device_start(rp->cdev, &rq->ccw, (unsigned long) rq, 0, 0); if (rq->rc == 0) - return; /* Sucessfully restarted. */ + return; /* Successfully restarted. */ break; case RAW3270_IO_STOP: if (!rq) diff --git a/drivers/s390/char/sclp.c b/drivers/s390/char/sclp.c index ec88c59842e3..f6d72e1f2a38 100644 --- a/drivers/s390/char/sclp.c +++ b/drivers/s390/char/sclp.c @@ -196,7 +196,7 @@ __sclp_start_request(struct sclp_req *req) req->start_count++; if (rc == 0) { - /* Sucessfully started request */ + /* Successfully started request */ req->status = SCLP_REQ_RUNNING; sclp_running_state = sclp_running_state_running; __sclp_set_request_timer(SCLP_RETRY_INTERVAL * HZ, diff --git a/drivers/scsi/a100u2w.c b/drivers/scsi/a100u2w.c index 208d6df9ed59..ff5716d5f044 100644 --- a/drivers/scsi/a100u2w.c +++ b/drivers/scsi/a100u2w.c @@ -492,7 +492,7 @@ static void init_alloc_map(struct orc_host * host) * init_orchid - initialise the host adapter * @host:host adapter to initialise * - * Initialise the controller and if neccessary load the firmware. + * Initialise the controller and if necessary load the firmware. * * Returns -1 if the initialisation fails. */ diff --git a/drivers/scsi/initio.c b/drivers/scsi/initio.c index 89a59484be02..a7714160fbc3 100644 --- a/drivers/scsi/initio.c +++ b/drivers/scsi/initio.c @@ -531,7 +531,7 @@ static void initio_read_eeprom(unsigned long base) * initio_stop_bm - stop bus master * @host: InitIO we are stopping * - * Stop any pending DMA operation, aborting the DMA if neccessary + * Stop any pending DMA operation, aborting the DMA if necessary */ static void initio_stop_bm(struct initio_host * host) diff --git a/drivers/scsi/libfc/fc_fcp.c b/drivers/scsi/libfc/fc_fcp.c index 96ee599d9a05..96446a85e008 100644 --- a/drivers/scsi/libfc/fc_fcp.c +++ b/drivers/scsi/libfc/fc_fcp.c @@ -48,7 +48,7 @@ struct kmem_cache *scsi_pkt_cachep; #define FC_SRB_CMD_SENT (1 << 0) /* cmd has been sent */ #define FC_SRB_RCV_STATUS (1 << 1) /* response has arrived */ #define FC_SRB_ABORT_PENDING (1 << 2) /* cmd abort sent to device */ -#define FC_SRB_ABORTED (1 << 3) /* abort acknowleged */ +#define FC_SRB_ABORTED (1 << 3) /* abort acknowledged */ #define FC_SRB_DISCONTIG (1 << 4) /* non-sequential data recvd */ #define FC_SRB_COMPL (1 << 5) /* fc_io_compl has been run */ #define FC_SRB_FCP_PROCESSING_TMO (1 << 6) /* timer function processing */ diff --git a/drivers/scsi/lpfc/lpfc_els.c b/drivers/scsi/lpfc/lpfc_els.c index 2cc39684ce97..c898f47f30ba 100644 --- a/drivers/scsi/lpfc/lpfc_els.c +++ b/drivers/scsi/lpfc/lpfc_els.c @@ -969,7 +969,7 @@ lpfc_issue_els_flogi(struct lpfc_vport *vport, struct lpfc_nodelist *ndlp, * function returns, it does not guarantee all the IOCBs are actually aborted. * * Return code - * 0 - Sucessfully issued abort iocb on all outstanding flogis (Always 0) + * 0 - Successfully issued abort iocb on all outstanding flogis (Always 0) **/ int lpfc_els_abort_flogi(struct lpfc_hba *phba) @@ -3117,7 +3117,7 @@ lpfc_cmpl_els_rsp(struct lpfc_hba *phba, struct lpfc_iocbq *cmdiocb, if (ndlp && NLP_CHK_NODE_ACT(ndlp) && (*((uint32_t *) (pcmd)) == ELS_CMD_LS_RJT)) { /* A LS_RJT associated with Default RPI cleanup has its own - * seperate code path. + * separate code path. */ if (!(ndlp->nlp_flag & NLP_RM_DFLT_RPI)) ls_rjt = 1; diff --git a/drivers/scsi/pcmcia/nsp_cs.h b/drivers/scsi/pcmcia/nsp_cs.h index 7db28cd49446..8c61a4fe1db9 100644 --- a/drivers/scsi/pcmcia/nsp_cs.h +++ b/drivers/scsi/pcmcia/nsp_cs.h @@ -187,7 +187,7 @@ #define S_IO BIT(1) /* Input/Output line from SCSI bus */ #define S_CD BIT(2) /* Command/Data line from SCSI bus */ #define S_BUSY BIT(3) /* Busy line from SCSI bus */ -#define S_ACK BIT(4) /* Acknowlege line from SCSI bus */ +#define S_ACK BIT(4) /* Acknowledge line from SCSI bus */ #define S_REQUEST BIT(5) /* Request line from SCSI bus */ #define S_SELECT BIT(6) /* */ #define S_ATN BIT(7) /* */ diff --git a/drivers/scsi/pm8001/pm8001_hwi.c b/drivers/scsi/pm8001/pm8001_hwi.c index 9b44c6f1b10e..7985ae45d688 100644 --- a/drivers/scsi/pm8001/pm8001_hwi.c +++ b/drivers/scsi/pm8001/pm8001_hwi.c @@ -2924,7 +2924,7 @@ hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) break; default: PM8001_MSG_DBG(pm8001_ha, - pm8001_printk("unkown device type(%x)\n", deviceType)); + pm8001_printk("unknown device type(%x)\n", deviceType)); break; } phy->phy_type |= PORT_TYPE_SAS; diff --git a/drivers/scsi/pm8001/pm8001_sas.c b/drivers/scsi/pm8001/pm8001_sas.c index 7f9c83a76390..3b2c98fba834 100644 --- a/drivers/scsi/pm8001/pm8001_sas.c +++ b/drivers/scsi/pm8001/pm8001_sas.c @@ -600,7 +600,7 @@ static void pm8001_free_dev(struct pm8001_device *pm8001_dev) * by the command "OPC_INB_REG_DEV", after that the HBA will assign a * device ID(according to device's sas address) and returned it to LLDD. From * now on, we communicate with HBA FW with the device ID which HBA assigned - * rather than sas address. it is the neccessary step for our HBA but it is + * rather than sas address. it is the necessary step for our HBA but it is * the optional for other HBA driver. */ static int pm8001_dev_found_notify(struct domain_device *dev) diff --git a/drivers/scsi/pmcraid.h b/drivers/scsi/pmcraid.h index 92f89d50850c..b8ad07c3449e 100644 --- a/drivers/scsi/pmcraid.h +++ b/drivers/scsi/pmcraid.h @@ -938,7 +938,7 @@ static struct pmcraid_ioasc_error pmcraid_ioasc_error_table[] = { /* * pmcraid_ioctl_header - definition of header structure that preceeds all the - * buffers given as ioctl arguements. + * buffers given as ioctl arguments. * * .signature : always ASCII string, "PMCRAID" * .reserved : not used diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c index 255da53e5a01..5d94772d449d 100644 --- a/drivers/scsi/sd.c +++ b/drivers/scsi/sd.c @@ -2105,7 +2105,7 @@ static int sd_revalidate_disk(struct gendisk *disk) * which is followed by sdaaa. * * This is basically 26 base counting with one extra 'nil' entry - * at the beggining from the second digit on and can be + * at the beginning from the second digit on and can be * determined using similar method as 26 base conversion with the * index shifted -1 after each digit is computed. * diff --git a/drivers/spi/spi_s3c24xx.c b/drivers/spi/spi_s3c24xx.c index c010733877ae..1fabede9e061 100644 --- a/drivers/spi/spi_s3c24xx.c +++ b/drivers/spi/spi_s3c24xx.c @@ -275,7 +275,7 @@ static inline u32 ack_bit(unsigned int irq) * Claim the FIQ handler (only one can be active at any one time) and * then setup the correct transfer code for this transfer. * - * This call updates all the necessary state information if sucessful, + * This call updates all the necessary state information if successful, * so the caller does not need to do anything more than start the transfer * as normal, since the IRQ will have been re-routed to the FIQ handler. */ diff --git a/drivers/usb/musb/musb_regs.h b/drivers/usb/musb/musb_regs.h index 473a94ef905f..7c14d5c5a8ac 100644 --- a/drivers/usb/musb/musb_regs.h +++ b/drivers/usb/musb/musb_regs.h @@ -436,7 +436,7 @@ static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum, #define MUSB_FLAT_OFFSET(_epnum, _offset) \ (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset)) -/* Not implemented - HW has seperate Tx/Rx FIFO */ +/* Not implemented - HW has separate Tx/Rx FIFO */ #define MUSB_TXCSR_MODE 0x0000 static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size) diff --git a/drivers/usb/serial/cypress_m8.c b/drivers/usb/serial/cypress_m8.c index a591ebec0f89..52a81a312b86 100644 --- a/drivers/usb/serial/cypress_m8.c +++ b/drivers/usb/serial/cypress_m8.c @@ -154,7 +154,7 @@ struct cypress_private { int isthrottled; /* if throttled, discard reads */ wait_queue_head_t delta_msr_wait; /* used for TIOCMIWAIT */ char prev_status, diff_status; /* used for TIOCMIWAIT */ - /* we pass a pointer to this as the arguement sent to + /* we pass a pointer to this as the argument sent to cypress_set_termios old_termios */ struct ktermios tmp_termios; /* stores the old termios settings */ }; diff --git a/drivers/video/omap/lcdc.c b/drivers/video/omap/lcdc.c index a33483910dc8..9557f963662e 100644 --- a/drivers/video/omap/lcdc.c +++ b/drivers/video/omap/lcdc.c @@ -389,7 +389,7 @@ static int omap_lcdc_enable_plane(int plane, int enable) /* * Configure the LCD DMA for a palette load operation and do the palette * downloading synchronously. We don't use the frame+palette load mode of - * the controller, since the palette can always be downloaded seperately. + * the controller, since the palette can always be downloaded separately. */ static void load_palette(void) { diff --git a/drivers/video/s1d13xxxfb.c b/drivers/video/s1d13xxxfb.c index 0deb0a8867b7..7b63429f1a7c 100644 --- a/drivers/video/s1d13xxxfb.c +++ b/drivers/video/s1d13xxxfb.c @@ -517,12 +517,12 @@ s1d13xxxfb_bitblt_copyarea(struct fb_info *info, const struct fb_copyarea *area) src = (sy * stride) + (bpp * sx); } - /* set source adress */ + /* set source address */ s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START0, (src & 0xff)); s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START1, (src >> 8) & 0x00ff); s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START2, (src >> 16) & 0x00ff); - /* set destination adress */ + /* set destination address */ s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dst & 0xff)); s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, (dst >> 8) & 0x00ff); s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, (dst >> 16) & 0x00ff); diff --git a/drivers/video/sm501fb.c b/drivers/video/sm501fb.c index 35370d0ecf03..b7dc1800efa9 100644 --- a/drivers/video/sm501fb.c +++ b/drivers/video/sm501fb.c @@ -411,7 +411,7 @@ static int sm501fb_set_par_common(struct fb_info *info, struct sm501fb_par *par = info->par; struct sm501fb_info *fbi = par->info; unsigned long pixclock; /* pixelclock in Hz */ - unsigned long sm501pixclock; /* pixelclock the 501 can achive in Hz */ + unsigned long sm501pixclock; /* pixelclock the 501 can achieve in Hz */ unsigned int mem_type; unsigned int clock_type; unsigned int head_addr; diff --git a/fs/affs/bitmap.c b/fs/affs/bitmap.c index dc5ef14bdc1c..8306d53307ed 100644 --- a/fs/affs/bitmap.c +++ b/fs/affs/bitmap.c @@ -128,7 +128,7 @@ err_range: /* * Allocate a block in the given allocation zone. * Since we have to byte-swap the bitmap on little-endian - * machines, this is rather expensive. Therefor we will + * machines, this is rather expensive. Therefore we will * preallocate up to 16 blocks from the same word, if * possible. We are not doing preallocations in the * header zone, though. diff --git a/fs/binfmt_elf_fdpic.c b/fs/binfmt_elf_fdpic.c index 18d77297ccc8..364fcfc0c5df 100644 --- a/fs/binfmt_elf_fdpic.c +++ b/fs/binfmt_elf_fdpic.c @@ -1393,7 +1393,7 @@ static inline void fill_note(struct memelfnote *note, const char *name, int type /* * fill up all the fields in prstatus from the given task struct, except - * registers which need to be filled up seperately. + * registers which need to be filled up separately. */ static void fill_prstatus(struct elf_prstatus *prstatus, struct task_struct *p, long signr) diff --git a/fs/cifs/cifs_dfs_ref.c b/fs/cifs/cifs_dfs_ref.c index b44ce0a0711c..b1d61d0bdfc7 100644 --- a/fs/cifs/cifs_dfs_ref.c +++ b/fs/cifs/cifs_dfs_ref.c @@ -54,7 +54,7 @@ void cifs_dfs_release_automount_timer(void) * Extracts sharename form full UNC. * i.e. strips from UNC trailing path that is not part of share * name and fixup missing '\' in the begining of DFS node refferal - * if neccessary. + * if necessary. * Returns pointer to share name on success or ERR_PTR on error. * Caller is responsible for freeing returned string. */ diff --git a/fs/cifs/cifssmb.c b/fs/cifs/cifssmb.c index 941441d3e386..0e22440d2f0f 100644 --- a/fs/cifs/cifssmb.c +++ b/fs/cifs/cifssmb.c @@ -3886,7 +3886,7 @@ parse_DFS_referrals(TRANSACTION2_GET_DFS_REFER_RSP *pSMBr, goto parse_DFS_referrals_exit; } - /* collect neccessary data from referrals */ + /* collect necessary data from referrals */ for (i = 0; i < *num_of_nodes; i++) { char *temp; int max_len; diff --git a/fs/ext4/move_extent.c b/fs/ext4/move_extent.c index 82c415be87a4..12a9ec73a888 100644 --- a/fs/ext4/move_extent.c +++ b/fs/ext4/move_extent.c @@ -928,7 +928,7 @@ out2: } /** - * mext_check_argumants - Check whether move extent can be done + * mext_check_arguments - Check whether move extent can be done * * @orig_inode: original inode * @donor_inode: donor inode diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c index 1a822ce2b24b..ec14d19ce501 100644 --- a/fs/fuse/inode.c +++ b/fs/fuse/inode.c @@ -850,7 +850,7 @@ static void fuse_send_init(struct fuse_conn *fc, struct fuse_req *req) req->in.args[0].size = sizeof(*arg); req->in.args[0].value = arg; req->out.numargs = 1; - /* Variable length arguement used for backward compatibility + /* Variable length argument used for backward compatibility with interface version < 7.5. Rest of init_out is zeroed by do_get_request(), so a short reply is not a problem */ req->out.argvar = 1; diff --git a/fs/gfs2/ops_fstype.c b/fs/gfs2/ops_fstype.c index edfee24f3636..0556f7fededd 100644 --- a/fs/gfs2/ops_fstype.c +++ b/fs/gfs2/ops_fstype.c @@ -992,7 +992,7 @@ static const struct lm_lockops nolock_ops = { /** * gfs2_lm_mount - mount a locking protocol * @sdp: the filesystem - * @args: mount arguements + * @args: mount arguments * @silent: if 1, don't complain if the FS isn't a GFS2 fs * * Returns: errno diff --git a/fs/jbd/transaction.c b/fs/jbd/transaction.c index 006f9ad838a2..57ae203c8abf 100644 --- a/fs/jbd/transaction.c +++ b/fs/jbd/transaction.c @@ -1398,7 +1398,7 @@ int journal_stop(handle_t *handle) * the case where our storage is so fast that it is more optimal to go * ahead and force a flush and wait for the transaction to be committed * than it is to wait for an arbitrary amount of time for new writers to - * join the transaction. We acheive this by measuring how long it takes + * join the transaction. We achieve this by measuring how long it takes * to commit a transaction, and compare it with how long this * transaction has been running, and if run time < commit time then we * sleep for the delta and commit. This greatly helps super fast disks diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c index a8587e90fd5a..143d43a93b72 100644 --- a/fs/nfsd/nfs4xdr.c +++ b/fs/nfsd/nfs4xdr.c @@ -1528,7 +1528,7 @@ static void write_cinfo(__be32 **p, struct nfsd4_change_info *c) } } while (0); /* Encode as an array of strings the string given with components - * seperated @sep. + * separated @sep. */ static __be32 nfsd4_encode_components(char sep, char *components, __be32 **pp, int *buflen) diff --git a/fs/ocfs2/dlmglue.c b/fs/ocfs2/dlmglue.c index c5e4a49e3a12..ccb9c44f478d 100644 --- a/fs/ocfs2/dlmglue.c +++ b/fs/ocfs2/dlmglue.c @@ -1757,7 +1757,7 @@ out: * ocfs2_file_lock() and ocfs2_file_unlock() map to a single pair of * flock() calls. The locking approach this requires is sufficiently * different from all other cluster lock types that we implement a - * seperate path to the "low-level" dlm calls. In particular: + * separate path to the "low-level" dlm calls. In particular: * * - No optimization of lock levels is done - we take at exactly * what's been requested. diff --git a/fs/ocfs2/extent_map.c b/fs/ocfs2/extent_map.c index d35a27f4523e..83e9b1249aed 100644 --- a/fs/ocfs2/extent_map.c +++ b/fs/ocfs2/extent_map.c @@ -453,7 +453,7 @@ static int ocfs2_get_clusters_nocache(struct inode *inode, if (i == -1) { /* * Holes can be larger than the maximum size of an - * extent, so we return their lengths in a seperate + * extent, so we return their lengths in a separate * field. */ if (hole_len) { diff --git a/fs/reiserfs/bitmap.c b/fs/reiserfs/bitmap.c index 65c872761177..ecc04b5ede57 100644 --- a/fs/reiserfs/bitmap.c +++ b/fs/reiserfs/bitmap.c @@ -169,7 +169,7 @@ static int scan_bitmap_block(struct reiserfs_transaction_handle *th, return 0; // No free blocks in this bitmap } - /* search for a first zero bit -- beggining of a window */ + /* search for a first zero bit -- beginning of a window */ *beg = reiserfs_find_next_zero_le_bit ((unsigned long *)(bh->b_data), boundary, *beg); diff --git a/include/linux/hil.h b/include/linux/hil.h index 13352d7d0caf..523785a9de70 100644 --- a/include/linux/hil.h +++ b/include/linux/hil.h @@ -168,14 +168,14 @@ enum hil_command { HIL_CMD_PR6 = 0x45, /* Prompt6 */ HIL_CMD_PR7 = 0x46, /* Prompt7 */ HIL_CMD_PRM = 0x47, /* Prompt (General Purpose) */ - HIL_CMD_AK1 = 0x48, /* Acknowlege1 */ - HIL_CMD_AK2 = 0x49, /* Acknowlege2 */ - HIL_CMD_AK3 = 0x4a, /* Acknowlege3 */ - HIL_CMD_AK4 = 0x4b, /* Acknowlege4 */ - HIL_CMD_AK5 = 0x4c, /* Acknowlege5 */ - HIL_CMD_AK6 = 0x4d, /* Acknowlege6 */ - HIL_CMD_AK7 = 0x4e, /* Acknowlege7 */ - HIL_CMD_ACK = 0x4f, /* Acknowlege (General Purpose) */ + HIL_CMD_AK1 = 0x48, /* Acknowledge1 */ + HIL_CMD_AK2 = 0x49, /* Acknowledge2 */ + HIL_CMD_AK3 = 0x4a, /* Acknowledge3 */ + HIL_CMD_AK4 = 0x4b, /* Acknowledge4 */ + HIL_CMD_AK5 = 0x4c, /* Acknowledge5 */ + HIL_CMD_AK6 = 0x4d, /* Acknowledge6 */ + HIL_CMD_AK7 = 0x4e, /* Acknowledge7 */ + HIL_CMD_ACK = 0x4f, /* Acknowledge (General Purpose) */ /* 0x50 to 0x78 reserved for future use */ /* 0x80 to 0xEF device-specific commands */ diff --git a/include/linux/lru_cache.h b/include/linux/lru_cache.h index 3a2b2d9b0472..de48d167568b 100644 --- a/include/linux/lru_cache.h +++ b/include/linux/lru_cache.h @@ -64,7 +64,7 @@ For crash recovery after replication node failure, usually the condition is softened to regions that _may_ have been target of in-flight WRITE IO, e.g. by only lazily clearing the on-disk write-intent bitmap, trading frequency of meta data transactions against amount of - (possibly unneccessary) resync traffic. + (possibly unnecessary) resync traffic. If we set a hard limit on the area that may be "hot" at any given time, we limit the amount of resync traffic needed for crash recovery. diff --git a/include/linux/sched.h b/include/linux/sched.h index abdfacc58653..a70957b138ed 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -1533,7 +1533,7 @@ struct task_struct { struct list_head *scm_work_list; #ifdef CONFIG_FUNCTION_GRAPH_TRACER - /* Index of current stored adress in ret_stack */ + /* Index of current stored address in ret_stack */ int curr_ret_stack; /* Stack of return addresses for return function tracing */ struct ftrace_ret_stack *ret_stack; diff --git a/include/media/davinci/vpfe_capture.h b/include/media/davinci/vpfe_capture.h index d863e5e8426d..4314a5f6a087 100644 --- a/include/media/davinci/vpfe_capture.h +++ b/include/media/davinci/vpfe_capture.h @@ -165,7 +165,7 @@ struct vpfe_device { u8 started; /* * offset where second field starts from the starting of the - * buffer for field seperated YCbCr formats + * buffer for field separated YCbCr formats */ u32 field_off; }; diff --git a/net/ipv4/tcp_timer.c b/net/ipv4/tcp_timer.c index 8816a20c2597..aff48d657181 100644 --- a/net/ipv4/tcp_timer.c +++ b/net/ipv4/tcp_timer.c @@ -133,7 +133,7 @@ static void tcp_mtu_probing(struct inet_connection_sock *icsk, struct sock *sk) } /* This function calculates a "timeout" which is equivalent to the timeout of a - * TCP connection after "boundary" unsucessful, exponentially backed-off + * TCP connection after "boundary" unsuccessful, exponentially backed-off * retransmissions with an initial RTO of TCP_RTO_MIN. */ static bool retransmits_timed_out(struct sock *sk, diff --git a/net/mac80211/mesh_plink.c b/net/mac80211/mesh_plink.c index 0f7c6e6a4248..54e4c8bb23e7 100644 --- a/net/mac80211/mesh_plink.c +++ b/net/mac80211/mesh_plink.c @@ -743,7 +743,7 @@ void mesh_rx_plink_frame(struct ieee80211_sub_if_data *sdata, struct ieee80211_m break; default: /* should not get here, PLINK_BLOCKED is dealt with at the - * beggining of the function + * beginning of the function */ spin_unlock_bh(&sta->lock); break; diff --git a/net/netfilter/nf_conntrack_sip.c b/net/netfilter/nf_conntrack_sip.c index 023966b569bf..fbe94adee7ac 100644 --- a/net/netfilter/nf_conntrack_sip.c +++ b/net/netfilter/nf_conntrack_sip.c @@ -276,7 +276,7 @@ EXPORT_SYMBOL_GPL(ct_sip_parse_request); * tabs, spaces and continuation lines, which are treated as a single whitespace * character. * - * Some headers may appear multiple times. A comma seperated list of values is + * Some headers may appear multiple times. A comma separated list of values is * equivalent to multiple headers. */ static const struct sip_header ct_sip_hdrs[] = { @@ -412,7 +412,7 @@ int ct_sip_get_header(const struct nf_conn *ct, const char *dptr, } EXPORT_SYMBOL_GPL(ct_sip_get_header); -/* Get next header field in a list of comma seperated values */ +/* Get next header field in a list of comma separated values */ static int ct_sip_next_header(const struct nf_conn *ct, const char *dptr, unsigned int dataoff, unsigned int datalen, enum sip_header_types type, diff --git a/net/netfilter/xt_hashlimit.c b/net/netfilter/xt_hashlimit.c index dd16e404424f..cbaac92dad59 100644 --- a/net/netfilter/xt_hashlimit.c +++ b/net/netfilter/xt_hashlimit.c @@ -1,6 +1,6 @@ /* * xt_hashlimit - Netfilter module to limit the number of packets per time - * seperately for each hashbucket (sourceip/sourceport/dstip/dstport) + * separately for each hashbucket (sourceip/sourceport/dstip/dstport) * * (C) 2003-2004 by Harald Welte * Copyright © CC Computer Consultants GmbH, 2007 - 2008 diff --git a/net/sctp/sm_sideeffect.c b/net/sctp/sm_sideeffect.c index 4e4ca65cd320..500886bda9b4 100644 --- a/net/sctp/sm_sideeffect.c +++ b/net/sctp/sm_sideeffect.c @@ -475,7 +475,7 @@ static void sctp_do_8_2_transport_strike(struct sctp_association *asoc, * used to provide an upper bound to this doubling operation. * * Special Case: the first HB doesn't trigger exponential backoff. - * The first unacknowleged HB triggers it. We do this with a flag + * The first unacknowledged HB triggers it. We do this with a flag * that indicates that we have an outstanding HB. */ if (!is_hb || transport->hb_sent) { diff --git a/scripts/gfp-translate b/scripts/gfp-translate index 073cb6d152a0..d81b968d864e 100644 --- a/scripts/gfp-translate +++ b/scripts/gfp-translate @@ -19,7 +19,7 @@ usage() { exit 0 } -# Parse command-line arguements +# Parse command-line arguments while [ $# -gt 0 ]; do case $1 in --source) diff --git a/sound/pci/rme9652/hdspm.c b/sound/pci/rme9652/hdspm.c index a1b10d1a384d..db0ed1cbd982 100644 --- a/sound/pci/rme9652/hdspm.c +++ b/sound/pci/rme9652/hdspm.c @@ -2479,7 +2479,7 @@ static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, on MADICARD - playback mixer matrix: [channelout+64] [output] [value] - input(thru) mixer matrix: [channelin] [output] [value] - (better do 2 kontrols for seperation ?) + (better do 2 kontrols for separation ?) */ #define HDSPM_MIXER(xname, xindex) \ diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c index 341481e0e830..427614a2762b 100644 --- a/sound/soc/codecs/wm8990.c +++ b/sound/soc/codecs/wm8990.c @@ -990,7 +990,7 @@ static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, reg = snd_soc_read(codec, WM8990_CLOCKING_2); snd_soc_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC); - /* set up N , fractional mode and pre-divisor if neccessary */ + /* set up N , fractional mode and pre-divisor if necessary */ snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM | (pll_div.div2?WM8990_PRESCALE:0)); snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8)); diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c index e8daf5ca6fd2..44408c2621cf 100644 --- a/tools/perf/util/hist.c +++ b/tools/perf/util/hist.c @@ -321,7 +321,7 @@ static size_t __callchain__fprintf_graph(FILE *fp, struct callchain_node *self, new_depth_mask &= ~(1 << (depth - 1)); /* - * But we keep the older depth mask for the line seperator + * But we keep the older depth mask for the line separator * to keep the level link until we reach the last child */ ret += ipchain__fprintf_graph_line(fp, depth, depth_mask, -- cgit v1.2.3 From 9dad76e8be982b3c72bc89a72f7d603bae87fa96 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 8 Feb 2010 14:34:43 -0500 Subject: drm/radeon/kms: fix prescale calculations Pre-pcie chips seem to use the reference clock rather than the sclk. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_i2c.c | 95 +++++++++++++++++++++++++++++++++---- 1 file changed, 85 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c index 272c45db5cec..d15fa5e62bb5 100644 --- a/drivers/gpu/drm/radeon/radeon_i2c.c +++ b/drivers/gpu/drm/radeon/radeon_i2c.c @@ -181,6 +181,87 @@ static void set_data(void *i2c_priv, int data) WREG32(rec->en_data_reg, val); } +static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) +{ + struct radeon_pll *spll = &rdev->clock.spll; + u32 sclk = radeon_get_engine_clock(rdev); + u32 prescale = 0; + u32 n, m; + u8 loop; + int i2c_clock; + + switch (rdev->family) { + case CHIP_R100: + case CHIP_RV100: + case CHIP_RS100: + case CHIP_RV200: + case CHIP_RS200: + case CHIP_R200: + case CHIP_RV250: + case CHIP_RS300: + case CHIP_RV280: + case CHIP_R300: + case CHIP_R350: + case CHIP_RV350: + n = (spll->reference_freq) / (4 * 6); + for (loop = 1; loop < 255; loop++) { + if ((loop * (loop - 1)) > n) + break; + } + m = loop - 1; + prescale = m | (loop << 8); + break; + case CHIP_RV380: + case CHIP_RS400: + case CHIP_RS480: + case CHIP_R420: + case CHIP_R423: + case CHIP_RV410: + sclk = radeon_get_engine_clock(rdev); + prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; + break; + case CHIP_RS600: + case CHIP_RS690: + case CHIP_RS740: + /* todo */ + break; + case CHIP_RV515: + case CHIP_R520: + case CHIP_RV530: + case CHIP_RV560: + case CHIP_RV570: + case CHIP_R580: + i2c_clock = 50; + sclk = radeon_get_engine_clock(rdev); + if (rdev->family == CHIP_R520) + prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); + else + prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; + break; + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + /* todo */ + break; + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + /* todo */ + break; + default: + DRM_ERROR("i2c: unhandled radeon chip\n"); + break; + } + return prescale; +} + + /* hw i2c engine for r1xx-4xx hardware * hw can buffer up to 15 bytes */ @@ -192,7 +273,7 @@ static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, struct radeon_i2c_bus_rec *rec = &i2c->rec; struct i2c_msg *p; int i, j, k, ret = num; - u32 sclk, prescale; + u32 prescale; u32 i2c_cntl_0, i2c_cntl_1, i2c_data; u32 tmp, reg; @@ -200,8 +281,7 @@ static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, /* take the pm lock since we need a constant sclk */ mutex_lock(&rdev->pm.mutex); - sclk = radeon_get_engine_clock(rdev); - prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; + prescale = radeon_get_i2c_prescale(rdev); reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | RADEON_I2C_START | @@ -444,9 +524,8 @@ static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, struct radeon_device *rdev = i2c->dev->dev_private; struct radeon_i2c_bus_rec *rec = &i2c->rec; struct i2c_msg *p; - int i2c_clock = 50; int i, j, remaining, current_count, buffer_offset, ret = num; - u32 sclk, prescale; + u32 prescale; u32 tmp, reg; u32 saved1, saved2; @@ -454,11 +533,7 @@ static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, /* take the pm lock since we need a constant sclk */ mutex_lock(&rdev->pm.mutex); - sclk = radeon_get_engine_clock(rdev); - if (rdev->family == CHIP_R520) - prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); - else - prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; + prescale = radeon_get_i2c_prescale(rdev); /* clear gpio mask bits */ tmp = RREG32(rec->mask_clk_reg); -- cgit v1.2.3 From 37b4390ec7f12f82e47a2ef56dccee094f26d34f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 9 Feb 2010 12:04:43 -0500 Subject: drm/radeon/kms/atom: replace 0/1 in crtc code with ATOM_DISABLE/ATOM_ENABLE Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/atombios_crtc.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 7e7c0b32bb65..925b4530ce1b 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -245,10 +245,10 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) switch (mode) { case DRM_MODE_DPMS_ON: - atombios_enable_crtc(crtc, 1); + atombios_enable_crtc(crtc, ATOM_ENABLE); if (ASIC_IS_DCE3(rdev)) - atombios_enable_crtc_memreq(crtc, 1); - atombios_blank_crtc(crtc, 0); + atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); + atombios_blank_crtc(crtc, ATOM_DISABLE); /* XXX re-enable when interrupt support is added */ if (!ASIC_IS_DCE4(rdev)) drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); @@ -260,10 +260,10 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) /* XXX re-enable when interrupt support is added */ if (!ASIC_IS_DCE4(rdev)) drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); - atombios_blank_crtc(crtc, 1); + atombios_blank_crtc(crtc, ATOM_ENABLE); if (ASIC_IS_DCE3(rdev)) - atombios_enable_crtc_memreq(crtc, 0); - atombios_enable_crtc(crtc, 0); + atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); + atombios_enable_crtc(crtc, ATOM_DISABLE); break; } } @@ -1116,14 +1116,14 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, static void atombios_crtc_prepare(struct drm_crtc *crtc) { - atombios_lock_crtc(crtc, 1); + atombios_lock_crtc(crtc, ATOM_ENABLE); atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); } static void atombios_crtc_commit(struct drm_crtc *crtc) { atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); - atombios_lock_crtc(crtc, 0); + atombios_lock_crtc(crtc, ATOM_DISABLE); } static const struct drm_crtc_helper_funcs atombios_helper_funcs = { -- cgit v1.2.3 From 12d7798f71107e7f4391a532af8c6690bda16f66 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 9 Feb 2010 17:18:48 -0500 Subject: drm/radeon/kms/evergreen: fix multi-head Fix a typo in crtc offset setup that set the crtc instances wrong for all crtcs except the first. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/atombios_crtc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 925b4530ce1b..0ec6934c3a26 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -1145,22 +1145,22 @@ void radeon_atombios_init_crtc(struct drm_device *dev, switch (radeon_crtc->crtc_id) { case 0: default: - radeon_crtc->crtc_id = EVERGREEN_CRTC0_REGISTER_OFFSET; + radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; break; case 1: - radeon_crtc->crtc_id = EVERGREEN_CRTC1_REGISTER_OFFSET; + radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; break; case 2: - radeon_crtc->crtc_id = EVERGREEN_CRTC2_REGISTER_OFFSET; + radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; break; case 3: - radeon_crtc->crtc_id = EVERGREEN_CRTC3_REGISTER_OFFSET; + radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; break; case 4: - radeon_crtc->crtc_id = EVERGREEN_CRTC4_REGISTER_OFFSET; + radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; break; case 5: - radeon_crtc->crtc_id = EVERGREEN_CRTC5_REGISTER_OFFSET; + radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; break; } } else { -- cgit v1.2.3 From 4c36b678a23d33b82d614afe4f958a9d244ede5d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 9 Feb 2010 18:22:00 -0500 Subject: drm/radeon/kms/evergreen: adapt to i2c changes original evergreen patches we against a kernel tree without my radeon i2c algo changes. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_i2c.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c index d15fa5e62bb5..4ae50c19589f 100644 --- a/drivers/gpu/drm/radeon/radeon_i2c.c +++ b/drivers/gpu/drm/radeon/radeon_i2c.c @@ -254,6 +254,13 @@ static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) case CHIP_RV740: /* todo */ break; + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + /* todo */ + break; default: DRM_ERROR("i2c: unhandled radeon chip\n"); break; @@ -833,6 +840,14 @@ static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap, /* XXX fill in hw i2c implementation */ ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num); break; + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + /* XXX fill in hw i2c implementation */ + ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num); + break; default: DRM_ERROR("i2c: unhandled radeon chip\n"); ret = -EIO; -- cgit v1.2.3 From c3ae90c099bb62387507e86da7cf799850444b08 Mon Sep 17 00:00:00 2001 From: Luca Barbieri Date: Tue, 9 Feb 2010 05:49:11 +0000 Subject: drm: introduce drm_gem_object_[handle_]unreference_unlocked This patch introduces the drm_gem_object_unreference_unlocked and drm_gem_object_handle_unreference_unlocked functions that do not require holding struct_mutex. drm_gem_object_unreference_unlocked calls the new ->gem_free_object_unlocked entry point if available, and otherwise just takes struct_mutex and just calls ->gem_free_object Signed-off-by: Luca Barbieri Signed-off-by: Dave Airlie --- drivers/gpu/drm/drm_gem.c | 49 ++++++++++++++++++++++++++++++++++++++++++----- include/drm/drmP.h | 28 ++++++++++++++++++++++++--- 2 files changed, 69 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index 8bf3770f294e..4018b3bfc72e 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -411,8 +411,19 @@ drm_gem_release(struct drm_device *dev, struct drm_file *file_private) mutex_unlock(&dev->struct_mutex); } +static void +drm_gem_object_free_common(struct drm_gem_object *obj) +{ + struct drm_device *dev = obj->dev; + fput(obj->filp); + atomic_dec(&dev->object_count); + atomic_sub(obj->size, &dev->object_memory); + kfree(obj); +} + /** * Called after the last reference to the object has been lost. + * Must be called holding struct_ mutex * * Frees the object */ @@ -427,13 +438,39 @@ drm_gem_object_free(struct kref *kref) if (dev->driver->gem_free_object != NULL) dev->driver->gem_free_object(obj); - fput(obj->filp); - atomic_dec(&dev->object_count); - atomic_sub(obj->size, &dev->object_memory); - kfree(obj); + drm_gem_object_free_common(obj); } EXPORT_SYMBOL(drm_gem_object_free); +/** + * Called after the last reference to the object has been lost. + * Must be called without holding struct_mutex + * + * Frees the object + */ +void +drm_gem_object_free_unlocked(struct kref *kref) +{ + struct drm_gem_object *obj = (struct drm_gem_object *) kref; + struct drm_device *dev = obj->dev; + + if (dev->driver->gem_free_object_unlocked != NULL) + dev->driver->gem_free_object_unlocked(obj); + else if (dev->driver->gem_free_object != NULL) { + mutex_lock(&dev->struct_mutex); + dev->driver->gem_free_object(obj); + mutex_unlock(&dev->struct_mutex); + } + + drm_gem_object_free_common(obj); +} +EXPORT_SYMBOL(drm_gem_object_free_unlocked); + +static void drm_gem_object_ref_bug(struct kref *list_kref) +{ + BUG(); +} + /** * Called after the last handle to the object has been closed * @@ -458,8 +495,10 @@ drm_gem_object_handle_free(struct kref *kref) /* * The object name held a reference to this object, drop * that now. + * + * This cannot be the last reference, since the handle holds one too. */ - drm_gem_object_unreference(obj); + kref_put(&obj->refcount, drm_gem_object_ref_bug); } else spin_unlock(&dev->object_name_lock); diff --git a/include/drm/drmP.h b/include/drm/drmP.h index ffac157fb5b2..4a3c4e441027 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -801,6 +801,7 @@ struct drm_driver { */ int (*gem_init_object) (struct drm_gem_object *obj); void (*gem_free_object) (struct drm_gem_object *obj); + void (*gem_free_object_unlocked) (struct drm_gem_object *obj); /* vga arb irq handler */ void (*vgaarb_irq)(struct drm_device *dev, bool state); @@ -1427,6 +1428,7 @@ extern void drm_sysfs_connector_remove(struct drm_connector *connector); int drm_gem_init(struct drm_device *dev); void drm_gem_destroy(struct drm_device *dev); void drm_gem_object_free(struct kref *kref); +void drm_gem_object_free_unlocked(struct kref *kref); struct drm_gem_object *drm_gem_object_alloc(struct drm_device *dev, size_t size); void drm_gem_object_handle_free(struct kref *kref); @@ -1443,10 +1445,15 @@ drm_gem_object_reference(struct drm_gem_object *obj) static inline void drm_gem_object_unreference(struct drm_gem_object *obj) { - if (obj == NULL) - return; + if (obj != NULL) + kref_put(&obj->refcount, drm_gem_object_free); +} - kref_put(&obj->refcount, drm_gem_object_free); +static inline void +drm_gem_object_unreference_unlocked(struct drm_gem_object *obj) +{ + if (obj != NULL) + kref_put(&obj->refcount, drm_gem_object_free_unlocked); } int drm_gem_handle_create(struct drm_file *file_priv, @@ -1475,6 +1482,21 @@ drm_gem_object_handle_unreference(struct drm_gem_object *obj) drm_gem_object_unreference(obj); } +static inline void +drm_gem_object_handle_unreference_unlocked(struct drm_gem_object *obj) +{ + if (obj == NULL) + return; + + /* + * Must bump handle count first as this may be the last + * ref, in which case the object would disappear before we + * checked for a name + */ + kref_put(&obj->handlecount, drm_gem_object_handle_free); + drm_gem_object_unreference_unlocked(obj); +} + struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev, struct drm_file *filp, u32 handle); -- cgit v1.2.3 From bc9025bdc4e2b591734cca17697093845007b63d Mon Sep 17 00:00:00 2001 From: Luca Barbieri Date: Tue, 9 Feb 2010 05:49:12 +0000 Subject: Use drm_gem_object_[handle_]unreference_unlocked where possible Mostly obvious simplifications. The i915 pread/pwrite ioctls, intel_overlay_put_image and nouveau_gem_new were incorrectly using the locked versions without locking: this is also fixed in this patch. Signed-off-by: Luca Barbieri Signed-off-by: Dave Airlie --- drivers/gpu/drm/drm_gem.c | 21 +++++------------ drivers/gpu/drm/i915/i915_gem.c | 16 +++++-------- drivers/gpu/drm/i915/i915_gem_tiling.c | 4 +--- drivers/gpu/drm/i915/intel_display.c | 13 ++++------- drivers/gpu/drm/i915/intel_overlay.c | 2 +- drivers/gpu/drm/nouveau/nouveau_display.c | 7 ++---- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 4 +--- drivers/gpu/drm/nouveau/nouveau_gem.c | 26 ++++++--------------- drivers/gpu/drm/nouveau/nouveau_notifier.c | 9 +++----- drivers/gpu/drm/nouveau/nv04_crtc.c | 4 +--- drivers/gpu/drm/nouveau/nv50_crtc.c | 4 +--- drivers/gpu/drm/radeon/radeon_cs.c | 7 ++---- drivers/gpu/drm/radeon/radeon_cursor.c | 8 ++----- drivers/gpu/drm/radeon/radeon_display.c | 7 ++---- drivers/gpu/drm/radeon/radeon_gem.c | 36 ++++++++---------------------- 15 files changed, 47 insertions(+), 121 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index 4018b3bfc72e..aa89d4b0b4c4 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -192,9 +192,7 @@ drm_gem_handle_delete(struct drm_file *filp, u32 handle) idr_remove(&filp->object_idr, handle); spin_unlock(&filp->table_lock); - mutex_lock(&dev->struct_mutex); - drm_gem_object_handle_unreference(obj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_handle_unreference_unlocked(obj); return 0; } @@ -325,9 +323,7 @@ again: } err: - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(obj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(obj); return ret; } @@ -358,9 +354,7 @@ drm_gem_open_ioctl(struct drm_device *dev, void *data, return -ENOENT; ret = drm_gem_handle_create(file_priv, obj, &handle); - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(obj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(obj); if (ret) return ret; @@ -390,7 +384,7 @@ drm_gem_object_release_handle(int id, void *ptr, void *data) { struct drm_gem_object *obj = ptr; - drm_gem_object_handle_unreference(obj); + drm_gem_object_handle_unreference_unlocked(obj); return 0; } @@ -403,12 +397,10 @@ drm_gem_object_release_handle(int id, void *ptr, void *data) void drm_gem_release(struct drm_device *dev, struct drm_file *file_private) { - mutex_lock(&dev->struct_mutex); idr_for_each(&file_private->object_idr, &drm_gem_object_release_handle, NULL); idr_destroy(&file_private->object_idr); - mutex_unlock(&dev->struct_mutex); } static void @@ -516,11 +508,8 @@ EXPORT_SYMBOL(drm_gem_vm_open); void drm_gem_vm_close(struct vm_area_struct *vma) { struct drm_gem_object *obj = vma->vm_private_data; - struct drm_device *dev = obj->dev; - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(obj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(obj); } EXPORT_SYMBOL(drm_gem_vm_close); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index b4c8c0230689..6844ca4f4265 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -128,9 +128,7 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data, return -ENOMEM; ret = drm_gem_handle_create(file_priv, obj, &handle); - mutex_lock(&dev->struct_mutex); - drm_gem_object_handle_unreference(obj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_handle_unreference_unlocked(obj); if (ret) return ret; @@ -488,7 +486,7 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data, */ if (args->offset > obj->size || args->size > obj->size || args->offset + args->size > obj->size) { - drm_gem_object_unreference(obj); + drm_gem_object_unreference_unlocked(obj); return -EINVAL; } @@ -501,7 +499,7 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data, file_priv); } - drm_gem_object_unreference(obj); + drm_gem_object_unreference_unlocked(obj); return ret; } @@ -961,7 +959,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, */ if (args->offset > obj->size || args->size > obj->size || args->offset + args->size > obj->size) { - drm_gem_object_unreference(obj); + drm_gem_object_unreference_unlocked(obj); return -EINVAL; } @@ -995,7 +993,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, DRM_INFO("pwrite failed %d\n", ret); #endif - drm_gem_object_unreference(obj); + drm_gem_object_unreference_unlocked(obj); return ret; } @@ -1138,9 +1136,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data, PROT_READ | PROT_WRITE, MAP_SHARED, args->offset); up_write(¤t->mm->mmap_sem); - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(obj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(obj); if (IS_ERR((void *)addr)) return addr; diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index df278b2685bf..137e888427f1 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -438,9 +438,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, obj_priv = obj->driver_private; if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) { - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(obj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(obj); return -EINVAL; } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 12775df1bbfd..8f72d0bfa7c5 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3434,11 +3434,10 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc, intel_crtc->cursor_bo = bo; return 0; -fail: - mutex_lock(&dev->struct_mutex); fail_locked: - drm_gem_object_unreference(bo); mutex_unlock(&dev->struct_mutex); +fail: + drm_gem_object_unreference_unlocked(bo); return ret; } @@ -4351,9 +4350,7 @@ static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) intelfb_remove(dev, fb); drm_framebuffer_cleanup(fb); - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(intel_fb->obj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(intel_fb->obj); kfree(intel_fb); } @@ -4416,9 +4413,7 @@ intel_user_framebuffer_create(struct drm_device *dev, ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj); if (ret) { - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(obj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(obj); return NULL; } diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 2639591c72e9..1b50d61c5aaa 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -1179,7 +1179,7 @@ int intel_overlay_put_image(struct drm_device *dev, void *data, out_unlock: mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->mode_config.mutex); - drm_gem_object_unreference(new_bo); + drm_gem_object_unreference_unlocked(new_bo); kfree(params); return ret; diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index dfc94391d71e..cf1c5c0a0abe 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -39,11 +39,8 @@ nouveau_user_framebuffer_destroy(struct drm_framebuffer *drm_fb) if (drm_fb->fbdev) nouveau_fbcon_remove(dev, drm_fb); - if (fb->nvbo) { - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(fb->nvbo->gem); - mutex_unlock(&dev->struct_mutex); - } + if (fb->nvbo) + drm_gem_object_unreference_unlocked(fb->nvbo->gem); drm_framebuffer_cleanup(drm_fb); kfree(fb); diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index ea879a2efef3..d48c59cdefe4 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -401,10 +401,8 @@ nouveau_fbcon_remove(struct drm_device *dev, struct drm_framebuffer *fb) unregister_framebuffer(info); nouveau_bo_unmap(nouveau_fb->nvbo); - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(nouveau_fb->nvbo->gem); + drm_gem_object_unreference_unlocked(nouveau_fb->nvbo->gem); nouveau_fb->nvbo = NULL; - mutex_unlock(&dev->struct_mutex); if (par) drm_fb_helper_free(&par->helper); framebuffer_release(info); diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 70cc30803e3b..34063c561899 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -167,12 +167,10 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data, ret = drm_gem_handle_create(file_priv, nvbo->gem, &req->info.handle); out: - mutex_lock(&dev->struct_mutex); - drm_gem_object_handle_unreference(nvbo->gem); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_handle_unreference_unlocked(nvbo->gem); if (ret) - drm_gem_object_unreference(nvbo->gem); + drm_gem_object_unreference_unlocked(nvbo->gem); return ret; } @@ -865,9 +863,7 @@ nouveau_gem_ioctl_pin(struct drm_device *dev, void *data, req->domain = NOUVEAU_GEM_DOMAIN_VRAM; out: - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gem); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gem); return ret; } @@ -891,9 +887,7 @@ nouveau_gem_ioctl_unpin(struct drm_device *dev, void *data, ret = nouveau_bo_unpin(nouveau_gem_object(gem)); - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gem); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gem); return ret; } @@ -935,9 +929,7 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data, } out: - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gem); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gem); return ret; } @@ -965,9 +957,7 @@ nouveau_gem_ioctl_cpu_fini(struct drm_device *dev, void *data, ret = 0; out: - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gem); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gem); return ret; } @@ -986,9 +976,7 @@ nouveau_gem_ioctl_info(struct drm_device *dev, void *data, return -EINVAL; ret = nouveau_gem_info(gem, req); - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gem); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gem); return ret; } diff --git a/drivers/gpu/drm/nouveau/nouveau_notifier.c b/drivers/gpu/drm/nouveau/nouveau_notifier.c index d99dc087f9b1..9537f3e30115 100644 --- a/drivers/gpu/drm/nouveau/nouveau_notifier.c +++ b/drivers/gpu/drm/nouveau/nouveau_notifier.c @@ -61,11 +61,8 @@ nouveau_notifier_init_channel(struct nouveau_channel *chan) chan->notifier_bo = ntfy; out_err: - if (ret) { - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(ntfy->gem); - mutex_unlock(&dev->struct_mutex); - } + if (ret) + drm_gem_object_unreference_unlocked(ntfy->gem); return ret; } @@ -81,8 +78,8 @@ nouveau_notifier_takedown_channel(struct nouveau_channel *chan) nouveau_bo_unmap(chan->notifier_bo); mutex_lock(&dev->struct_mutex); nouveau_bo_unpin(chan->notifier_bo); - drm_gem_object_unreference(chan->notifier_bo->gem); mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(chan->notifier_bo->gem); nouveau_mem_takedown(&chan->notifier_heap); } diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c index d2f143ed97c1..a1d1ebb073d9 100644 --- a/drivers/gpu/drm/nouveau/nv04_crtc.c +++ b/drivers/gpu/drm/nouveau/nv04_crtc.c @@ -926,9 +926,7 @@ nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); nv_crtc->cursor.show(nv_crtc, true); out: - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gem); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gem); return ret; } diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c index d1a651e3400c..cfabeb974a56 100644 --- a/drivers/gpu/drm/nouveau/nv50_crtc.c +++ b/drivers/gpu/drm/nouveau/nv50_crtc.c @@ -358,9 +358,7 @@ nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, nv_crtc->cursor.show(nv_crtc, true); out: - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gem); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gem); return ret; } diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index 1190148cf5e6..da59f5e78e09 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -196,11 +196,8 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) radeon_bo_list_unreserve(&parser->validated); } for (i = 0; i < parser->nrelocs; i++) { - if (parser->relocs[i].gobj) { - mutex_lock(&parser->rdev->ddev->struct_mutex); - drm_gem_object_unreference(parser->relocs[i].gobj); - mutex_unlock(&parser->rdev->ddev->struct_mutex); - } + if (parser->relocs[i].gobj) + drm_gem_object_unreference_unlocked(parser->relocs[i].gobj); } kfree(parser->track); kfree(parser->relocs); diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c index 28772a37009c..6f4a5534a99e 100644 --- a/drivers/gpu/drm/radeon/radeon_cursor.c +++ b/drivers/gpu/drm/radeon/radeon_cursor.c @@ -169,17 +169,13 @@ int radeon_crtc_cursor_set(struct drm_crtc *crtc, unpin: if (radeon_crtc->cursor_bo) { radeon_gem_object_unpin(radeon_crtc->cursor_bo); - mutex_lock(&crtc->dev->struct_mutex); - drm_gem_object_unreference(radeon_crtc->cursor_bo); - mutex_unlock(&crtc->dev->struct_mutex); + drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo); } radeon_crtc->cursor_bo = obj; return 0; fail: - mutex_lock(&crtc->dev->struct_mutex); - drm_gem_object_unreference(obj); - mutex_unlock(&crtc->dev->struct_mutex); + drm_gem_object_unreference_unlocked(obj); return 0; } diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 7e17a362b54b..3db825505626 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -679,11 +679,8 @@ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) if (fb->fbdev) radeonfb_remove(dev, fb); - if (radeon_fb->obj) { - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(radeon_fb->obj); - mutex_unlock(&dev->struct_mutex); - } + if (radeon_fb->obj) + drm_gem_object_unreference_unlocked(radeon_fb->obj); drm_framebuffer_cleanup(fb); kfree(radeon_fb); } diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index db8e9a355a01..ef92d147d8f0 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -69,9 +69,7 @@ int radeon_gem_object_create(struct radeon_device *rdev, int size, if (r != -ERESTARTSYS) DRM_ERROR("Failed to allocate GEM object (%d, %d, %u, %d)\n", size, initial_domain, alignment, r); - mutex_lock(&rdev->ddev->struct_mutex); - drm_gem_object_unreference(gobj); - mutex_unlock(&rdev->ddev->struct_mutex); + drm_gem_object_unreference_unlocked(gobj); return r; } gobj->driver_private = robj; @@ -202,14 +200,10 @@ int radeon_gem_create_ioctl(struct drm_device *dev, void *data, } r = drm_gem_handle_create(filp, gobj, &handle); if (r) { - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gobj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gobj); return r; } - mutex_lock(&dev->struct_mutex); - drm_gem_object_handle_unreference(gobj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_handle_unreference_unlocked(gobj); args->handle = handle; return 0; } @@ -236,9 +230,7 @@ int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain); - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gobj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gobj); return r; } @@ -255,9 +247,7 @@ int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, } robj = gobj->driver_private; args->addr_ptr = radeon_bo_mmap_offset(robj); - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gobj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gobj); return 0; } @@ -288,9 +278,7 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, default: break; } - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gobj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gobj); return r; } @@ -311,9 +299,7 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, /* callback hw specific functions if any */ if (robj->rdev->asic->ioctl_wait_idle) robj->rdev->asic->ioctl_wait_idle(robj->rdev, robj); - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gobj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gobj); return r; } @@ -331,9 +317,7 @@ int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, return -EINVAL; robj = gobj->driver_private; r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gobj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gobj); return r; } @@ -356,8 +340,6 @@ int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); radeon_bo_unreserve(rbo); out: - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gobj); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(gobj); return r; } -- cgit v1.2.3 From 9a1420d1185693b6e24719d3937a0c20a3e0e31d Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 3 Feb 2010 19:14:35 +1000 Subject: drm: switch all GEM/KMS ioctls to unlocked ioctl status. These ioctls are all protected by their own locking mechanisms so should be fine to not bother locking around. Signed-off-by: Dave Airlie --- drivers/gpu/drm/drm_drv.c | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index 766c46875a20..f3c58e2bd75c 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -125,28 +125,28 @@ static struct drm_ioctl_desc drm_ioctls[] = { DRM_IOCTL_DEF(DRM_IOCTL_UPDATE_DRAW, drm_update_drawable_info, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_IOCTL_GEM_CLOSE, drm_gem_close_ioctl, 0), - DRM_IOCTL_DEF(DRM_IOCTL_GEM_FLINK, drm_gem_flink_ioctl, DRM_AUTH), - DRM_IOCTL_DEF(DRM_IOCTL_GEM_OPEN, drm_gem_open_ioctl, DRM_AUTH), - - DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETRESOURCES, drm_mode_getresources, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCRTC, drm_mode_getcrtc, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETCRTC, drm_mode_setcrtc, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR, drm_mode_cursor_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETGAMMA, drm_mode_gamma_get_ioctl, DRM_MASTER), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETGAMMA, drm_mode_gamma_set_ioctl, DRM_MASTER), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETENCODER, drm_mode_getencoder, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCONNECTOR, drm_mode_getconnector, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_ATTACHMODE, drm_mode_attachmode_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_DETACHMODE, drm_mode_detachmode_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPERTY, drm_mode_getproperty_ioctl, DRM_MASTER | DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPROPERTY, drm_mode_connector_property_set_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPBLOB, drm_mode_getblob_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETFB, drm_mode_getfb, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB, drm_mode_addfb, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_PAGE_FLIP, drm_mode_page_flip_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW), - DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW) + DRM_IOCTL_DEF(DRM_IOCTL_GEM_CLOSE, drm_gem_close_ioctl, DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_GEM_FLINK, drm_gem_flink_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_GEM_OPEN, drm_gem_open_ioctl, DRM_AUTH|DRM_UNLOCKED), + + DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETRESOURCES, drm_mode_getresources, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCRTC, drm_mode_getcrtc, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETCRTC, drm_mode_setcrtc, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR, drm_mode_cursor_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETGAMMA, drm_mode_gamma_get_ioctl, DRM_MASTER|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETGAMMA, drm_mode_gamma_set_ioctl, DRM_MASTER|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETENCODER, drm_mode_getencoder, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCONNECTOR, drm_mode_getconnector, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_ATTACHMODE, drm_mode_attachmode_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_DETACHMODE, drm_mode_detachmode_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPERTY, drm_mode_getproperty_ioctl, DRM_MASTER | DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPROPERTY, drm_mode_connector_property_set_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPBLOB, drm_mode_getblob_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETFB, drm_mode_getfb, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB, drm_mode_addfb, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_PAGE_FLIP, drm_mode_page_flip_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED) }; #define DRM_CORE_IOCTL_COUNT ARRAY_SIZE( drm_ioctls ) -- cgit v1.2.3 From 3b40a4434f4d65321332dec590a079d7a75077d8 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 2 Feb 2010 14:40:32 -0800 Subject: drivers/gpu/drm/drm_fb_helper.c: don't use private implementation of atoi() Kernel has simple_strtol() which would be used as atoi(). This is quite the same fix as in 2cb96f86628d6e97fcbda5fe4d8d74876239834c ("fbdev: drop custom atoi from drivers/video/modedb.c") because code in drivers/gpu/drm/drm_fb_helper.c is based on drivers/video/modedb.c. Signed-off-by: Andy Shevchenko Cc: Jesse Barnes Signed-off-by: Andrew Morton Signed-off-by: Dave Airlie --- drivers/gpu/drm/drm_fb_helper.c | 24 +++++------------------- 1 file changed, 5 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 0f9e90552dc4..989c4debbecb 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -27,6 +27,7 @@ * Dave Airlie * Jesse Barnes */ +#include #include #include #include "drmP.h" @@ -50,21 +51,6 @@ int drm_fb_helper_add_connector(struct drm_connector *connector) } EXPORT_SYMBOL(drm_fb_helper_add_connector); -static int my_atoi(const char *name) -{ - int val = 0; - - for (;; name++) { - switch (*name) { - case '0' ... '9': - val = 10*val+(*name-'0'); - break; - default: - return val; - } - } -} - /** * drm_fb_helper_connector_parse_command_line - parse command line for connector * @connector - connector to parse line for @@ -111,7 +97,7 @@ static bool drm_fb_helper_connector_parse_command_line(struct drm_connector *con namelen = i; if (!refresh_specified && !bpp_specified && !yres_specified) { - refresh = my_atoi(&name[i+1]); + refresh = simple_strtol(&name[i+1], NULL, 10); refresh_specified = 1; if (cvt || rb) cvt = 0; @@ -121,7 +107,7 @@ static bool drm_fb_helper_connector_parse_command_line(struct drm_connector *con case '-': namelen = i; if (!bpp_specified && !yres_specified) { - bpp = my_atoi(&name[i+1]); + bpp = simple_strtol(&name[i+1], NULL, 10); bpp_specified = 1; if (cvt || rb) cvt = 0; @@ -130,7 +116,7 @@ static bool drm_fb_helper_connector_parse_command_line(struct drm_connector *con break; case 'x': if (!yres_specified) { - yres = my_atoi(&name[i+1]); + yres = simple_strtol(&name[i+1], NULL, 10); yres_specified = 1; } else goto done; @@ -170,7 +156,7 @@ static bool drm_fb_helper_connector_parse_command_line(struct drm_connector *con } } if (i < 0 && yres_specified) { - xres = my_atoi(name); + xres = simple_strtol(name, NULL, 10); res_specified = 1; } done: -- cgit v1.2.3 From 8dff4742a6a718e71d15a9b7a8d3d2255bfbc91a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 11 Feb 2010 14:28:58 +1000 Subject: drm/kms: fix fb_changed = true else statement a patch from Roel was wrong, fix this properly, really if the fb ptrs are different fb changed shuold be true. Signed-off-by: Dave Airlie --- drivers/gpu/drm/drm_crtc_helper.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index 7d0f00a935fa..f2aaf39be398 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -836,11 +836,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) mode_changed = true; } else if (set->fb == NULL) { mode_changed = true; - } else if ((set->fb->bits_per_pixel != - set->crtc->fb->bits_per_pixel) || - set->fb->depth != set->crtc->fb->depth) - fb_changed = true; - else + } else fb_changed = true; } -- cgit v1.2.3 From 172e91f535dc3607a7dba1d249ab9e918444548a Mon Sep 17 00:00:00 2001 From: Pavel Roskin Date: Thu, 11 Feb 2010 14:31:32 +1000 Subject: drm/kms: fix spelling of "CLOCK" Signed-off-by: Pavel Roskin [clemens@ladisch.de: merged into drm_fb_helper] Signed-off-by: Clemens Ladisch Signed-off-by: Dave Airlie --- drivers/gpu/drm/drm_fb_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 989c4debbecb..50549703584f 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -680,7 +680,7 @@ int drm_fb_helper_set_par(struct fb_info *info) int i; if (var->pixclock != 0) { - DRM_ERROR("PIXEL CLCOK SET\n"); + DRM_ERROR("PIXEL CLOCK SET\n"); return -EINVAL; } -- cgit v1.2.3 From 961fb597c17e2e4f55407d56b7211c188ab41eff Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 10 Feb 2010 22:30:05 +0000 Subject: drm/radeon/kms: r600/r700 command stream checker This patch add cs checker to r600/r700 hw. Command stream checking will rewrite some of the cs value in order to restrict GPU access to BO size. This doesn't break old userspace but just enforce safe value. It should break any things that was using the r600/r700 cs ioctl to do forbidden things (malicious software), though we are not aware of such things. Here is the list of thing we check : - enforcing resource size - enforcing color buffer slice tile max, will restrict cb access - enforcing db buffer slice tile max, will restrict db access We don't check for shader bigger than the BO in which they are supposed to be, such use would lead to GPU lockup and is harmless from security POV, as far as we can tell (note that even checking for this wouldn't prevent someone to write bogus shader that lead to lockup). This patch has received as much testing as humanly possible with old userspace to check that it didn't break such configuration. However not all the applications out there were tested, thus it might broke some odd, rare applications. [airlied: fix rules for cs checker for parallel builds] Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/Makefile | 5 + drivers/gpu/drm/radeon/r600.c | 6 + drivers/gpu/drm/radeon/r600_cp.c | 31 ++ drivers/gpu/drm/radeon/r600_cs.c | 826 ++++++++++++++++++++++++++++------ drivers/gpu/drm/radeon/r600d.h | 467 ++++++++++++++++++- drivers/gpu/drm/radeon/radeon.h | 6 + drivers/gpu/drm/radeon/radeon_drv.h | 3 + drivers/gpu/drm/radeon/reg_srcs/r600 | 837 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/radeon/rv770.c | 6 + 9 files changed, 2058 insertions(+), 129 deletions(-) create mode 100644 drivers/gpu/drm/radeon/reg_srcs/r600 (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 83c59079193b..b46f115d1c25 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -30,6 +30,9 @@ $(obj)/r420_reg_safe.h: $(src)/reg_srcs/r420 $(obj)/mkregtable $(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable $(call if_changed,mkregtable) +$(obj)/r600_reg_safe.h: $(src)/reg_srcs/r600 $(obj)/mkregtable + $(call if_changed,mkregtable) + $(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h $(obj)/r200.o: $(obj)/r200_reg_safe.h @@ -42,6 +45,8 @@ $(obj)/r420.o: $(obj)/r420_reg_safe.h $(obj)/rs600.o: $(obj)/rs600_reg_safe.h +$(obj)/r600_cs.o: $(obj)/r600_reg_safe.h + radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \ radeon_irq.o r300_cmdbuf.o r600_cp.o # add KMS driver diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 05769fa77a21..c9723daee357 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -1077,21 +1077,27 @@ void r600_gpu_init(struct radeon_device *rdev) switch (rdev->config.r600.max_tile_pipes) { case 1: tiling_config |= PIPE_TILING(0); + rdev->config.r600.tiling_npipes = 1; break; case 2: tiling_config |= PIPE_TILING(1); + rdev->config.r600.tiling_npipes = 2; break; case 4: tiling_config |= PIPE_TILING(2); + rdev->config.r600.tiling_npipes = 4; break; case 8: tiling_config |= PIPE_TILING(3); + rdev->config.r600.tiling_npipes = 8; break; default: break; } + rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); tiling_config |= GROUP_SIZE(0); + rdev->config.r600.tiling_group_size = 256; tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; if (tmp > 3) { tiling_config |= ROW_TILING(3); diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c index 6d5a711c2e91..d9712a1023b1 100644 --- a/drivers/gpu/drm/radeon/r600_cp.c +++ b/drivers/gpu/drm/radeon/r600_cp.c @@ -873,6 +873,17 @@ static void r600_gfx_init(struct drm_device *dev, RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); + if (gb_tiling_config & 0xc0) { + dev_priv->r600_group_size = 512; + } else { + dev_priv->r600_group_size = 256; + } + dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); + if (gb_tiling_config & 0x30) { + dev_priv->r600_nbanks = 8; + } else { + dev_priv->r600_nbanks = 4; + } RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); @@ -1444,6 +1455,17 @@ static void r700_gfx_init(struct drm_device *dev, RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); + if (gb_tiling_config & 0xc0) { + dev_priv->r600_group_size = 512; + } else { + dev_priv->r600_group_size = 256; + } + dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); + if (gb_tiling_config & 0x30) { + dev_priv->r600_nbanks = 8; + } else { + dev_priv->r600_nbanks = 4; + } RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); @@ -2526,3 +2548,12 @@ out: mutex_unlock(&dev_priv->cs_mutex); return r; } + +void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size) +{ + struct drm_radeon_private *dev_priv = dev->dev_private; + + *npipes = dev_priv->r600_npipes; + *nbanks = dev_priv->r600_nbanks; + *group_size = dev_priv->r600_group_size; +} diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index e4c45ec16507..ac67d6488a95 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -28,6 +28,7 @@ #include "drmP.h" #include "radeon.h" #include "r600d.h" +#include "r600_reg_safe.h" static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, struct radeon_cs_reloc **cs_reloc); @@ -35,11 +36,313 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, struct radeon_cs_reloc **cs_reloc); typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**); static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm; +extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size); + struct r600_cs_track { - u32 cb_color0_base_last; + /* configuration we miror so that we use same code btw kms/ums */ + u32 group_size; + u32 nbanks; + u32 npipes; + /* value we track */ + u32 nsamples; + u32 cb_color_base_last[8]; + struct radeon_bo *cb_color_bo[8]; + u32 cb_color_bo_offset[8]; + struct radeon_bo *cb_color_frag_bo[8]; + struct radeon_bo *cb_color_tile_bo[8]; + u32 cb_color_info[8]; + u32 cb_color_size_idx[8]; + u32 cb_target_mask; + u32 cb_shader_mask; + u32 cb_color_size[8]; + u32 vgt_strmout_en; + u32 vgt_strmout_buffer_en; + u32 db_depth_control; + u32 db_depth_info; + u32 db_depth_size_idx; + u32 db_depth_view; + u32 db_depth_size; + u32 db_offset; + struct radeon_bo *db_bo; }; +static inline int r600_bpe_from_format(u32 *bpe, u32 format) +{ + switch (format) { + case V_038004_COLOR_8: + case V_038004_COLOR_4_4: + case V_038004_COLOR_3_3_2: + case V_038004_FMT_1: + *bpe = 1; + break; + case V_038004_COLOR_16: + case V_038004_COLOR_16_FLOAT: + case V_038004_COLOR_8_8: + case V_038004_COLOR_5_6_5: + case V_038004_COLOR_6_5_5: + case V_038004_COLOR_1_5_5_5: + case V_038004_COLOR_4_4_4_4: + case V_038004_COLOR_5_5_5_1: + *bpe = 2; + break; + case V_038004_FMT_8_8_8: + *bpe = 3; + break; + case V_038004_COLOR_32: + case V_038004_COLOR_32_FLOAT: + case V_038004_COLOR_16_16: + case V_038004_COLOR_16_16_FLOAT: + case V_038004_COLOR_8_24: + case V_038004_COLOR_8_24_FLOAT: + case V_038004_COLOR_24_8: + case V_038004_COLOR_24_8_FLOAT: + case V_038004_COLOR_10_11_11: + case V_038004_COLOR_10_11_11_FLOAT: + case V_038004_COLOR_11_11_10: + case V_038004_COLOR_11_11_10_FLOAT: + case V_038004_COLOR_2_10_10_10: + case V_038004_COLOR_8_8_8_8: + case V_038004_COLOR_10_10_10_2: + case V_038004_FMT_5_9_9_9_SHAREDEXP: + case V_038004_FMT_32_AS_8: + case V_038004_FMT_32_AS_8_8: + *bpe = 4; + break; + case V_038004_COLOR_X24_8_32_FLOAT: + case V_038004_COLOR_32_32: + case V_038004_COLOR_32_32_FLOAT: + case V_038004_COLOR_16_16_16_16: + case V_038004_COLOR_16_16_16_16_FLOAT: + *bpe = 8; + break; + case V_038004_FMT_16_16_16: + case V_038004_FMT_16_16_16_FLOAT: + *bpe = 6; + break; + case V_038004_FMT_32_32_32: + case V_038004_FMT_32_32_32_FLOAT: + *bpe = 12; + break; + case V_038004_COLOR_32_32_32_32: + case V_038004_COLOR_32_32_32_32_FLOAT: + *bpe = 16; + break; + case V_038004_FMT_GB_GR: + case V_038004_FMT_BG_RG: + case V_038004_COLOR_INVALID: + *bpe = 16; + return -EINVAL; + } + return 0; +} + +static void r600_cs_track_init(struct r600_cs_track *track) +{ + int i; + + for (i = 0; i < 8; i++) { + track->cb_color_base_last[i] = 0; + track->cb_color_size[i] = 0; + track->cb_color_size_idx[i] = 0; + track->cb_color_info[i] = 0; + track->cb_color_bo[i] = NULL; + track->cb_color_bo_offset[i] = 0xFFFFFFFF; + } + track->cb_target_mask = 0xFFFFFFFF; + track->cb_shader_mask = 0xFFFFFFFF; + track->db_bo = NULL; + /* assume the biggest format and that htile is enabled */ + track->db_depth_info = 7 | (1 << 25); + track->db_depth_view = 0xFFFFC000; + track->db_depth_size = 0xFFFFFFFF; + track->db_depth_size_idx = 0; + track->db_depth_control = 0xFFFFFFFF; +} + +static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) +{ + struct r600_cs_track *track = p->track; + u32 bpe, pitch, slice_tile_max, size, tmp, height; + volatile u32 *ib = p->ib->ptr; + + if (G_0280A0_TILE_MODE(track->cb_color_info[i])) { + dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n"); + return -EINVAL; + } + size = radeon_bo_size(track->cb_color_bo[i]); + if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) { + dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", + __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]), + i, track->cb_color_info[i]); + return -EINVAL; + } + pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) << 3; + slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1; + if (!pitch) { + dev_warn(p->dev, "%s:%d cb pitch (%d) for %d invalid (0x%08X)\n", + __func__, __LINE__, pitch, i, track->cb_color_size[i]); + return -EINVAL; + } + height = size / (pitch * bpe); + if (height > 8192) + height = 8192; + switch (G_0280A0_ARRAY_MODE(track->cb_color_info[i])) { + case V_0280A0_ARRAY_LINEAR_GENERAL: + case V_0280A0_ARRAY_LINEAR_ALIGNED: + if (pitch & 0x3f) { + dev_warn(p->dev, "%s:%d cb pitch (%d x %d = %d) invalid\n", + __func__, __LINE__, pitch, bpe, pitch * bpe); + return -EINVAL; + } + if ((pitch * bpe) & (track->group_size - 1)) { + dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", + __func__, __LINE__, pitch); + return -EINVAL; + } + break; + case V_0280A0_ARRAY_1D_TILED_THIN1: + if ((pitch * 8 * bpe * track->nsamples) & (track->group_size - 1)) { + dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", + __func__, __LINE__, pitch); + return -EINVAL; + } + height &= ~0x7; + if (!height) + height = 8; + break; + case V_0280A0_ARRAY_2D_TILED_THIN1: + if (pitch & ((8 * track->nbanks) - 1)) { + dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", + __func__, __LINE__, pitch); + return -EINVAL; + } + tmp = pitch * 8 * bpe * track->nsamples; + tmp = tmp / track->nbanks; + if (tmp & (track->group_size - 1)) { + dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", + __func__, __LINE__, pitch); + return -EINVAL; + } + height &= ~((16 * track->npipes) - 1); + if (!height) + height = 16 * track->npipes; + break; + default: + dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, + G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, + track->cb_color_info[i]); + return -EINVAL; + } + /* check offset */ + tmp = height * pitch; + if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { + dev_warn(p->dev, "%s offset[%d] %d to big\n", __func__, i, track->cb_color_bo_offset[i]); + return -EINVAL; + } + /* limit max tile */ + tmp = (height * pitch) >> 6; + if (tmp < slice_tile_max) + slice_tile_max = tmp; + tmp = S_028060_PITCH_TILE_MAX((pitch >> 3) - 1) | + S_028060_SLICE_TILE_MAX(slice_tile_max - 1); + ib[track->cb_color_size_idx[i]] = tmp; + return 0; +} + +static int r600_cs_track_check(struct radeon_cs_parser *p) +{ + struct r600_cs_track *track = p->track; + u32 tmp; + int r, i; + volatile u32 *ib = p->ib->ptr; + + /* on legacy kernel we don't perform advanced check */ + if (p->rdev == NULL) + return 0; + /* we don't support out buffer yet */ + if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) { + dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n"); + return -EINVAL; + } + /* check that we have a cb for each enabled target, we don't check + * shader_mask because it seems mesa isn't always setting it :( + */ + tmp = track->cb_target_mask; + for (i = 0; i < 8; i++) { + if ((tmp >> (i * 4)) & 0xF) { + /* at least one component is enabled */ + if (track->cb_color_bo[i] == NULL) { + dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", + __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); + return -EINVAL; + } + /* perform rewrite of CB_COLOR[0-7]_SIZE */ + r = r600_cs_track_validate_cb(p, i); + if (r) + return r; + } + } + /* Check depth buffer */ + if (G_028800_STENCIL_ENABLE(track->db_depth_control) || + G_028800_Z_ENABLE(track->db_depth_control)) { + u32 nviews, bpe, ntiles; + if (track->db_bo == NULL) { + dev_warn(p->dev, "z/stencil with no depth buffer\n"); + return -EINVAL; + } + if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) { + dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n"); + return -EINVAL; + } + switch (G_028010_FORMAT(track->db_depth_info)) { + case V_028010_DEPTH_16: + bpe = 2; + break; + case V_028010_DEPTH_X8_24: + case V_028010_DEPTH_8_24: + case V_028010_DEPTH_X8_24_FLOAT: + case V_028010_DEPTH_8_24_FLOAT: + case V_028010_DEPTH_32_FLOAT: + bpe = 4; + break; + case V_028010_DEPTH_X24_8_32_FLOAT: + bpe = 8; + break; + default: + dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info)); + return -EINVAL; + } + if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { + if (!track->db_depth_size_idx) { + dev_warn(p->dev, "z/stencil buffer size not set\n"); + return -EINVAL; + } + printk_once(KERN_WARNING "You have old & broken userspace please consider updating mesa\n"); + tmp = radeon_bo_size(track->db_bo) - track->db_offset; + tmp = (tmp / bpe) >> 6; + if (!tmp) { + dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n", + track->db_depth_size, bpe, track->db_offset, + radeon_bo_size(track->db_bo)); + return -EINVAL; + } + ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); + } else { + ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; + nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; + tmp = ntiles * bpe * 64 * nviews; + if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { + dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %d have %ld)\n", + track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, + radeon_bo_size(track->db_bo)); + return -EINVAL; + } + } + } + return 0; +} + /** * r600_cs_packet_parse() - parse cp packet and point ib index to next packet * @parser: parser structure holding parsing context. @@ -359,6 +662,334 @@ static int r600_cs_parse_packet0(struct radeon_cs_parser *p, return 0; } +/** + * r600_cs_check_reg() - check if register is authorized or not + * @parser: parser structure holding parsing context + * @reg: register we are testing + * @idx: index into the cs buffer + * + * This function will test against r600_reg_safe_bm and return 0 + * if register is safe. If register is not flag as safe this function + * will test it against a list of register needind special handling. + */ +static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +{ + struct r600_cs_track *track = (struct r600_cs_track *)p->track; + struct radeon_cs_reloc *reloc; + u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm); + u32 m, i, tmp, *ib; + int r; + + i = (reg >> 7); + if (i > last_reg) { + dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); + return -EINVAL; + } + m = 1 << ((reg >> 2) & 31); + if (!(r600_reg_safe_bm[i] & m)) + return 0; + ib = p->ib->ptr; + switch (reg) { + /* force following reg to 0 in an attemp to disable out buffer + * which will need us to better understand how it works to perform + * security check on it (Jerome) + */ + case R_0288A8_SQ_ESGS_RING_ITEMSIZE: + case R_008C44_SQ_ESGS_RING_SIZE: + case R_0288B0_SQ_ESTMP_RING_ITEMSIZE: + case R_008C54_SQ_ESTMP_RING_SIZE: + case R_0288C0_SQ_FBUF_RING_ITEMSIZE: + case R_008C74_SQ_FBUF_RING_SIZE: + case R_0288B4_SQ_GSTMP_RING_ITEMSIZE: + case R_008C5C_SQ_GSTMP_RING_SIZE: + case R_0288AC_SQ_GSVS_RING_ITEMSIZE: + case R_008C4C_SQ_GSVS_RING_SIZE: + case R_0288BC_SQ_PSTMP_RING_ITEMSIZE: + case R_008C6C_SQ_PSTMP_RING_SIZE: + case R_0288C4_SQ_REDUC_RING_ITEMSIZE: + case R_008C7C_SQ_REDUC_RING_SIZE: + case R_0288B8_SQ_VSTMP_RING_ITEMSIZE: + case R_008C64_SQ_VSTMP_RING_SIZE: + case R_0288C8_SQ_GS_VERT_ITEMSIZE: + /* get value to populate the IB don't remove */ + tmp =radeon_get_ib_value(p, idx); + ib[idx] = 0; + break; + case R_028800_DB_DEPTH_CONTROL: + track->db_depth_control = radeon_get_ib_value(p, idx); + break; + case R_028010_DB_DEPTH_INFO: + track->db_depth_info = radeon_get_ib_value(p, idx); + break; + case R_028004_DB_DEPTH_VIEW: + track->db_depth_view = radeon_get_ib_value(p, idx); + break; + case R_028000_DB_DEPTH_SIZE: + track->db_depth_size = radeon_get_ib_value(p, idx); + track->db_depth_size_idx = idx; + break; + case R_028AB0_VGT_STRMOUT_EN: + track->vgt_strmout_en = radeon_get_ib_value(p, idx); + break; + case R_028B20_VGT_STRMOUT_BUFFER_EN: + track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); + break; + case R_028238_CB_TARGET_MASK: + track->cb_target_mask = radeon_get_ib_value(p, idx); + break; + case R_02823C_CB_SHADER_MASK: + track->cb_shader_mask = radeon_get_ib_value(p, idx); + break; + case R_028C04_PA_SC_AA_CONFIG: + tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); + track->nsamples = 1 << tmp; + break; + case R_0280A0_CB_COLOR0_INFO: + case R_0280A4_CB_COLOR1_INFO: + case R_0280A8_CB_COLOR2_INFO: + case R_0280AC_CB_COLOR3_INFO: + case R_0280B0_CB_COLOR4_INFO: + case R_0280B4_CB_COLOR5_INFO: + case R_0280B8_CB_COLOR6_INFO: + case R_0280BC_CB_COLOR7_INFO: + tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; + track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); + break; + case R_028060_CB_COLOR0_SIZE: + case R_028064_CB_COLOR1_SIZE: + case R_028068_CB_COLOR2_SIZE: + case R_02806C_CB_COLOR3_SIZE: + case R_028070_CB_COLOR4_SIZE: + case R_028074_CB_COLOR5_SIZE: + case R_028078_CB_COLOR6_SIZE: + case R_02807C_CB_COLOR7_SIZE: + tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4; + track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); + track->cb_color_size_idx[tmp] = idx; + break; + /* This register were added late, there is userspace + * which does provide relocation for those but set + * 0 offset. In order to avoid breaking old userspace + * we detect this and set address to point to last + * CB_COLOR0_BASE, note that if userspace doesn't set + * CB_COLOR0_BASE before this register we will report + * error. Old userspace always set CB_COLOR0_BASE + * before any of this. + */ + case R_0280E0_CB_COLOR0_FRAG: + case R_0280E4_CB_COLOR1_FRAG: + case R_0280E8_CB_COLOR2_FRAG: + case R_0280EC_CB_COLOR3_FRAG: + case R_0280F0_CB_COLOR4_FRAG: + case R_0280F4_CB_COLOR5_FRAG: + case R_0280F8_CB_COLOR6_FRAG: + case R_0280FC_CB_COLOR7_FRAG: + tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4; + if (!r600_cs_packet_next_is_pkt3_nop(p)) { + if (!track->cb_color_base_last[tmp]) { + dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); + return -EINVAL; + } + ib[idx] = track->cb_color_base_last[tmp]; + printk_once(KERN_WARNING "You have old & broken userspace " + "please consider updating mesa & xf86-video-ati\n"); + track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp]; + } else { + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); + return -EINVAL; + } + ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + track->cb_color_frag_bo[tmp] = reloc->robj; + } + break; + case R_0280C0_CB_COLOR0_TILE: + case R_0280C4_CB_COLOR1_TILE: + case R_0280C8_CB_COLOR2_TILE: + case R_0280CC_CB_COLOR3_TILE: + case R_0280D0_CB_COLOR4_TILE: + case R_0280D4_CB_COLOR5_TILE: + case R_0280D8_CB_COLOR6_TILE: + case R_0280DC_CB_COLOR7_TILE: + tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4; + if (!r600_cs_packet_next_is_pkt3_nop(p)) { + if (!track->cb_color_base_last[tmp]) { + dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); + return -EINVAL; + } + ib[idx] = track->cb_color_base_last[tmp]; + printk_once(KERN_WARNING "You have old & broken userspace " + "please consider updating mesa & xf86-video-ati\n"); + track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp]; + } else { + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); + return -EINVAL; + } + ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + track->cb_color_tile_bo[tmp] = reloc->robj; + } + break; + case CB_COLOR0_BASE: + case CB_COLOR1_BASE: + case CB_COLOR2_BASE: + case CB_COLOR3_BASE: + case CB_COLOR4_BASE: + case CB_COLOR5_BASE: + case CB_COLOR6_BASE: + case CB_COLOR7_BASE: + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + dev_warn(p->dev, "bad SET_CONTEXT_REG " + "0x%04X\n", reg); + return -EINVAL; + } + track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); + ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + tmp = (reg - CB_COLOR0_BASE) / 4; + track->cb_color_base_last[tmp] = ib[idx]; + track->cb_color_bo[tmp] = reloc->robj; + break; + case DB_DEPTH_BASE: + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + dev_warn(p->dev, "bad SET_CONTEXT_REG " + "0x%04X\n", reg); + return -EINVAL; + } + track->db_offset = radeon_get_ib_value(p, idx); + ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + track->db_bo = reloc->robj; + break; + case DB_HTILE_DATA_BASE: + case SQ_PGM_START_FS: + case SQ_PGM_START_ES: + case SQ_PGM_START_VS: + case SQ_PGM_START_GS: + case SQ_PGM_START_PS: + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + dev_warn(p->dev, "bad SET_CONTEXT_REG " + "0x%04X\n", reg); + return -EINVAL; + } + ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + break; + default: + dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); + return -EINVAL; + } + return 0; +} + +static inline unsigned minify(unsigned size, unsigned levels) +{ + size = size >> levels; + if (size < 1) + size = 1; + return size; +} + +static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels, + unsigned w0, unsigned h0, unsigned d0, unsigned bpe, + unsigned *l0_size, unsigned *mipmap_size) +{ + unsigned offset, i, level, face; + unsigned width, height, depth, rowstride, size; + + w0 = minify(w0, 0); + h0 = minify(h0, 0); + d0 = minify(d0, 0); + for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) { + width = minify(w0, i); + height = minify(h0, i); + depth = minify(d0, i); + for(face = 0; face < nfaces; face++) { + rowstride = ((width * bpe) + 255) & ~255; + size = height * rowstride * depth; + offset += size; + offset = (offset + 0x1f) & ~0x1f; + } + } + *l0_size = (((w0 * bpe) + 255) & ~255) * h0 * d0; + *mipmap_size = offset; + if (!blevel) + *mipmap_size -= *l0_size; + if (!nlevels) + *mipmap_size = *l0_size; +} + +/** + * r600_check_texture_resource() - check if register is authorized or not + * @p: parser structure holding parsing context + * @idx: index into the cs buffer + * @texture: texture's bo structure + * @mipmap: mipmap's bo structure + * + * This function will check that the resource has valid field and that + * the texture and mipmap bo object are big enough to cover this resource. + */ +static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, + struct radeon_bo *texture, + struct radeon_bo *mipmap) +{ + u32 nfaces, nlevels, blevel, w0, h0, d0, bpe; + u32 word0, word1, l0_size, mipmap_size; + + /* on legacy kernel we don't perform advanced check */ + if (p->rdev == NULL) + return 0; + word0 = radeon_get_ib_value(p, idx + 0); + word1 = radeon_get_ib_value(p, idx + 1); + w0 = G_038000_TEX_WIDTH(word0) + 1; + h0 = G_038004_TEX_HEIGHT(word1) + 1; + d0 = G_038004_TEX_DEPTH(word1); + nfaces = 1; + switch (G_038000_DIM(word0)) { + case V_038000_SQ_TEX_DIM_1D: + case V_038000_SQ_TEX_DIM_2D: + case V_038000_SQ_TEX_DIM_3D: + break; + case V_038000_SQ_TEX_DIM_CUBEMAP: + nfaces = 6; + break; + case V_038000_SQ_TEX_DIM_1D_ARRAY: + case V_038000_SQ_TEX_DIM_2D_ARRAY: + case V_038000_SQ_TEX_DIM_2D_MSAA: + case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA: + default: + dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); + return -EINVAL; + } + if (r600_bpe_from_format(&bpe, G_038004_DATA_FORMAT(word1))) { + dev_warn(p->dev, "%s:%d texture invalid format %d\n", + __func__, __LINE__, G_038004_DATA_FORMAT(word1)); + return -EINVAL; + } + word0 = radeon_get_ib_value(p, idx + 4); + word1 = radeon_get_ib_value(p, idx + 5); + blevel = G_038010_BASE_LEVEL(word0); + nlevels = G_038014_LAST_LEVEL(word1); + r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe, &l0_size, &mipmap_size); + /* using get ib will give us the offset into the texture bo */ + word0 = radeon_get_ib_value(p, idx + 2); + if ((l0_size + word0) > radeon_bo_size(texture)) { + dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n", + w0, h0, bpe, word0, l0_size, radeon_bo_size(texture)); + return -EINVAL; + } + /* using get ib will give us the offset into the mipmap bo */ + word0 = radeon_get_ib_value(p, idx + 3); + if ((mipmap_size + word0) > radeon_bo_size(mipmap)) { + dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", + w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture)); + return -EINVAL; + } + return 0; +} + static int r600_packet3_check(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt) { @@ -408,12 +1039,22 @@ static int r600_packet3_check(struct radeon_cs_parser *p, } ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + r = r600_cs_track_check(p); + if (r) { + dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); + return r; + } break; case PACKET3_DRAW_INDEX_AUTO: if (pkt->count != 1) { DRM_ERROR("bad DRAW_INDEX_AUTO\n"); return -EINVAL; } + r = r600_cs_track_check(p); + if (r) { + dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); + return r; + } break; case PACKET3_DRAW_INDEX_IMMD_BE: case PACKET3_DRAW_INDEX_IMMD: @@ -421,6 +1062,11 @@ static int r600_packet3_check(struct radeon_cs_parser *p, DRM_ERROR("bad DRAW_INDEX_IMMD\n"); return -EINVAL; } + r = r600_cs_track_check(p); + if (r) { + dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); + return r; + } break; case PACKET3_WAIT_REG_MEM: if (pkt->count != 5) { @@ -493,30 +1139,9 @@ static int r600_packet3_check(struct radeon_cs_parser *p, } for (i = 0; i < pkt->count; i++) { reg = start_reg + (4 * i); - switch (reg) { - case SQ_ESGS_RING_BASE: - case SQ_GSVS_RING_BASE: - case SQ_ESTMP_RING_BASE: - case SQ_GSTMP_RING_BASE: - case SQ_VSTMP_RING_BASE: - case SQ_PSTMP_RING_BASE: - case SQ_FBUF_RING_BASE: - case SQ_REDUC_RING_BASE: - case SX_MEMORY_EXPORT_BASE: - r = r600_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("bad SET_CONFIG_REG " - "0x%04X\n", reg); - return -EINVAL; - } - ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); - break; - case CP_COHER_BASE: - /* use PACKET3_SURFACE_SYNC */ - return -EINVAL; - default: - break; - } + r = r600_cs_check_reg(p, reg, idx+1+i); + if (r) + return r; } break; case PACKET3_SET_CONTEXT_REG: @@ -530,106 +1155,9 @@ static int r600_packet3_check(struct radeon_cs_parser *p, } for (i = 0; i < pkt->count; i++) { reg = start_reg + (4 * i); - switch (reg) { - /* This register were added late, there is userspace - * which does provide relocation for those but set - * 0 offset. In order to avoid breaking old userspace - * we detect this and set address to point to last - * CB_COLOR0_BASE, note that if userspace doesn't set - * CB_COLOR0_BASE before this register we will report - * error. Old userspace always set CB_COLOR0_BASE - * before any of this. - */ - case R_0280E0_CB_COLOR0_FRAG: - case R_0280E4_CB_COLOR1_FRAG: - case R_0280E8_CB_COLOR2_FRAG: - case R_0280EC_CB_COLOR3_FRAG: - case R_0280F0_CB_COLOR4_FRAG: - case R_0280F4_CB_COLOR5_FRAG: - case R_0280F8_CB_COLOR6_FRAG: - case R_0280FC_CB_COLOR7_FRAG: - case R_0280C0_CB_COLOR0_TILE: - case R_0280C4_CB_COLOR1_TILE: - case R_0280C8_CB_COLOR2_TILE: - case R_0280CC_CB_COLOR3_TILE: - case R_0280D0_CB_COLOR4_TILE: - case R_0280D4_CB_COLOR5_TILE: - case R_0280D8_CB_COLOR6_TILE: - case R_0280DC_CB_COLOR7_TILE: - if (!r600_cs_packet_next_is_pkt3_nop(p)) { - if (!track->cb_color0_base_last) { - dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); - return -EINVAL; - } - ib[idx+1+i] = track->cb_color0_base_last; - printk_once(KERN_WARNING "radeon: You have old & broken userspace " - "please consider updating mesa & xf86-video-ati\n"); - } else { - r = r600_cs_packet_next_reloc(p, &reloc); - if (r) { - dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); - return -EINVAL; - } - ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); - } - break; - case DB_DEPTH_BASE: - case DB_HTILE_DATA_BASE: - case CB_COLOR0_BASE: - r = r600_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("bad SET_CONTEXT_REG " - "0x%04X\n", reg); - return -EINVAL; - } - ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); - track->cb_color0_base_last = ib[idx+1+i]; - break; - case CB_COLOR1_BASE: - case CB_COLOR2_BASE: - case CB_COLOR3_BASE: - case CB_COLOR4_BASE: - case CB_COLOR5_BASE: - case CB_COLOR6_BASE: - case CB_COLOR7_BASE: - case SQ_PGM_START_FS: - case SQ_PGM_START_ES: - case SQ_PGM_START_VS: - case SQ_PGM_START_GS: - case SQ_PGM_START_PS: - r = r600_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("bad SET_CONTEXT_REG " - "0x%04X\n", reg); - return -EINVAL; - } - ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); - break; - case VGT_DMA_BASE: - case VGT_DMA_BASE_HI: - /* These should be handled by DRAW_INDEX packet 3 */ - case VGT_STRMOUT_BASE_OFFSET_0: - case VGT_STRMOUT_BASE_OFFSET_1: - case VGT_STRMOUT_BASE_OFFSET_2: - case VGT_STRMOUT_BASE_OFFSET_3: - case VGT_STRMOUT_BASE_OFFSET_HI_0: - case VGT_STRMOUT_BASE_OFFSET_HI_1: - case VGT_STRMOUT_BASE_OFFSET_HI_2: - case VGT_STRMOUT_BASE_OFFSET_HI_3: - case VGT_STRMOUT_BUFFER_BASE_0: - case VGT_STRMOUT_BUFFER_BASE_1: - case VGT_STRMOUT_BUFFER_BASE_2: - case VGT_STRMOUT_BUFFER_BASE_3: - case VGT_STRMOUT_BUFFER_OFFSET_0: - case VGT_STRMOUT_BUFFER_OFFSET_1: - case VGT_STRMOUT_BUFFER_OFFSET_2: - case VGT_STRMOUT_BUFFER_OFFSET_3: - /* These should be handled by STRMOUT_BUFFER packet 3 */ - DRM_ERROR("bad context reg: 0x%08x\n", reg); - return -EINVAL; - default: - break; - } + r = r600_cs_check_reg(p, reg, idx+1+i); + if (r) + return r; } break; case PACKET3_SET_RESOURCE: @@ -646,6 +1174,9 @@ static int r600_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } for (i = 0; i < (pkt->count / 7); i++) { + struct radeon_bo *texture, *mipmap; + u32 size, offset; + switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { case SQ_TEX_VTX_VALID_TEXTURE: /* tex base */ @@ -655,6 +1186,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + texture = reloc->robj; /* tex mip base */ r = r600_cs_packet_next_reloc(p, &reloc); if (r) { @@ -662,6 +1194,11 @@ static int r600_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + mipmap = reloc->robj; + r = r600_check_texture_resource(p, idx+(i*7)+1, + texture, mipmap); + if (r) + return r; break; case SQ_TEX_VTX_VALID_BUFFER: /* vtx base */ @@ -670,6 +1207,13 @@ static int r600_packet3_check(struct radeon_cs_parser *p, DRM_ERROR("bad SET_RESOURCE\n"); return -EINVAL; } + offset = radeon_get_ib_value(p, idx+1+(i*7)+0); + size = radeon_get_ib_value(p, idx+1+(i*7)+1); + if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { + /* force size to size of the buffer */ + dev_warn(p->dev, "vbo resource seems too big for the bo\n"); + ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj); + } ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; break; @@ -760,8 +1304,23 @@ int r600_cs_parse(struct radeon_cs_parser *p) struct r600_cs_track *track; int r; - track = kzalloc(sizeof(*track), GFP_KERNEL); - p->track = track; + if (p->track == NULL) { + /* initialize tracker, we are in kms */ + track = kzalloc(sizeof(*track), GFP_KERNEL); + if (track == NULL) + return -ENOMEM; + r600_cs_track_init(track); + if (p->rdev->family < CHIP_RV770) { + track->npipes = p->rdev->config.r600.tiling_npipes; + track->nbanks = p->rdev->config.r600.tiling_nbanks; + track->group_size = p->rdev->config.r600.tiling_group_size; + } else if (p->rdev->family <= CHIP_RV740) { + track->npipes = p->rdev->config.rv770.tiling_npipes; + track->nbanks = p->rdev->config.rv770.tiling_nbanks; + track->group_size = p->rdev->config.rv770.tiling_group_size; + } + p->track = track; + } do { r = r600_cs_packet_parse(p, &pkt, p->idx); if (r) { @@ -779,9 +1338,11 @@ int r600_cs_parse(struct radeon_cs_parser *p) break; default: DRM_ERROR("Unknown packet type %d !\n", pkt.type); + kfree(p->track); return -EINVAL; } if (r) { + kfree(p->track); return r; } } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); @@ -791,6 +1352,7 @@ int r600_cs_parse(struct radeon_cs_parser *p) mdelay(1); } #endif + kfree(p->track); return 0; } @@ -833,9 +1395,16 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, { struct radeon_cs_parser parser; struct radeon_cs_chunk *ib_chunk; - struct radeon_ib fake_ib; + struct radeon_ib fake_ib; + struct r600_cs_track *track; int r; + /* initialize tracker */ + track = kzalloc(sizeof(*track), GFP_KERNEL); + if (track == NULL) + return -ENOMEM; + r600_cs_track_init(track); + r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size); /* initialize parser */ memset(&parser, 0, sizeof(struct radeon_cs_parser)); parser.filp = filp; @@ -843,6 +1412,7 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, parser.rdev = NULL; parser.family = family; parser.ib = &fake_ib; + parser.track = track; fake_ib.ptr = ib; r = radeon_cs_parser_init(&parser, data); if (r) { diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index 30480881aed1..5b2e4d442823 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h @@ -883,6 +883,16 @@ #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 +#define R_028C04_PA_SC_AA_CONFIG 0x028C04 +#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) +#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) +#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC +#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) +#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) +#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF +#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) +#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) +#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF #define R_0280E0_CB_COLOR0_FRAG 0x0280E0 #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) @@ -905,6 +915,461 @@ #define R_0280D4_CB_COLOR5_TILE 0x0280D4 #define R_0280D8_CB_COLOR6_TILE 0x0280D8 #define R_0280DC_CB_COLOR7_TILE 0x0280DC - +#define R_0280A0_CB_COLOR0_INFO 0x0280A0 +#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) +#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) +#define C_0280A0_ENDIAN 0xFFFFFFFC +#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) +#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) +#define C_0280A0_FORMAT 0xFFFFFF03 +#define V_0280A0_COLOR_INVALID 0x00000000 +#define V_0280A0_COLOR_8 0x00000001 +#define V_0280A0_COLOR_4_4 0x00000002 +#define V_0280A0_COLOR_3_3_2 0x00000003 +#define V_0280A0_COLOR_16 0x00000005 +#define V_0280A0_COLOR_16_FLOAT 0x00000006 +#define V_0280A0_COLOR_8_8 0x00000007 +#define V_0280A0_COLOR_5_6_5 0x00000008 +#define V_0280A0_COLOR_6_5_5 0x00000009 +#define V_0280A0_COLOR_1_5_5_5 0x0000000A +#define V_0280A0_COLOR_4_4_4_4 0x0000000B +#define V_0280A0_COLOR_5_5_5_1 0x0000000C +#define V_0280A0_COLOR_32 0x0000000D +#define V_0280A0_COLOR_32_FLOAT 0x0000000E +#define V_0280A0_COLOR_16_16 0x0000000F +#define V_0280A0_COLOR_16_16_FLOAT 0x00000010 +#define V_0280A0_COLOR_8_24 0x00000011 +#define V_0280A0_COLOR_8_24_FLOAT 0x00000012 +#define V_0280A0_COLOR_24_8 0x00000013 +#define V_0280A0_COLOR_24_8_FLOAT 0x00000014 +#define V_0280A0_COLOR_10_11_11 0x00000015 +#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 +#define V_0280A0_COLOR_11_11_10 0x00000017 +#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 +#define V_0280A0_COLOR_2_10_10_10 0x00000019 +#define V_0280A0_COLOR_8_8_8_8 0x0000001A +#define V_0280A0_COLOR_10_10_10_2 0x0000001B +#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C +#define V_0280A0_COLOR_32_32 0x0000001D +#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E +#define V_0280A0_COLOR_16_16_16_16 0x0000001F +#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 +#define V_0280A0_COLOR_32_32_32_32 0x00000022 +#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 +#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) +#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) +#define C_0280A0_ARRAY_MODE 0xFFFFF0FF +#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 +#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 +#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 +#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 +#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) +#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) +#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF +#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) +#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) +#define C_0280A0_READ_SIZE 0xFFFF7FFF +#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) +#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) +#define C_0280A0_COMP_SWAP 0xFFFCFFFF +#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) +#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) +#define C_0280A0_TILE_MODE 0xFFF3FFFF +#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) +#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) +#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF +#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) +#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) +#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF +#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) +#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) +#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF +#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) +#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) +#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF +#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) +#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) +#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF +#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) +#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) +#define C_0280A0_ROUND_MODE 0xFDFFFFFF +#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) +#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) +#define C_0280A0_TILE_COMPACT 0xFBFFFFFF +#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) +#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) +#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF +#define R_0280A4_CB_COLOR1_INFO 0x0280A4 +#define R_0280A8_CB_COLOR2_INFO 0x0280A8 +#define R_0280AC_CB_COLOR3_INFO 0x0280AC +#define R_0280B0_CB_COLOR4_INFO 0x0280B0 +#define R_0280B4_CB_COLOR5_INFO 0x0280B4 +#define R_0280B8_CB_COLOR6_INFO 0x0280B8 +#define R_0280BC_CB_COLOR7_INFO 0x0280BC +#define R_028060_CB_COLOR0_SIZE 0x028060 +#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028060_PITCH_TILE_MAX 0xFFFFFC00 +#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) +#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) +#define C_028060_SLICE_TILE_MAX 0xC00003FF +#define R_028064_CB_COLOR1_SIZE 0x028064 +#define R_028068_CB_COLOR2_SIZE 0x028068 +#define R_02806C_CB_COLOR3_SIZE 0x02806C +#define R_028070_CB_COLOR4_SIZE 0x028070 +#define R_028074_CB_COLOR5_SIZE 0x028074 +#define R_028078_CB_COLOR6_SIZE 0x028078 +#define R_02807C_CB_COLOR7_SIZE 0x02807C +#define R_028238_CB_TARGET_MASK 0x028238 +#define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) +#define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) +#define C_028238_TARGET0_ENABLE 0xFFFFFFF0 +#define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) +#define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) +#define C_028238_TARGET1_ENABLE 0xFFFFFF0F +#define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) +#define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) +#define C_028238_TARGET2_ENABLE 0xFFFFF0FF +#define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) +#define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) +#define C_028238_TARGET3_ENABLE 0xFFFF0FFF +#define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) +#define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) +#define C_028238_TARGET4_ENABLE 0xFFF0FFFF +#define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) +#define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) +#define C_028238_TARGET5_ENABLE 0xFF0FFFFF +#define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) +#define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) +#define C_028238_TARGET6_ENABLE 0xF0FFFFFF +#define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) +#define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) +#define C_028238_TARGET7_ENABLE 0x0FFFFFFF +#define R_02823C_CB_SHADER_MASK 0x02823C +#define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) +#define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) +#define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 +#define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) +#define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) +#define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F +#define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) +#define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) +#define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF +#define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) +#define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) +#define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF +#define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) +#define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) +#define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF +#define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) +#define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) +#define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF +#define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) +#define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) +#define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF +#define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) +#define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) +#define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF +#define R_028AB0_VGT_STRMOUT_EN 0x028AB0 +#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) +#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) +#define C_028AB0_STREAMOUT 0xFFFFFFFE +#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 +#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) +#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) +#define C_028B20_BUFFER_0_EN 0xFFFFFFFE +#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) +#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) +#define C_028B20_BUFFER_1_EN 0xFFFFFFFD +#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) +#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) +#define C_028B20_BUFFER_2_EN 0xFFFFFFFB +#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) +#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) +#define C_028B20_BUFFER_3_EN 0xFFFFFFF7 +#define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028B20_SIZE 0x00000000 +#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 +#define S_038000_DIM(x) (((x) & 0x7) << 0) +#define G_038000_DIM(x) (((x) >> 0) & 0x7) +#define C_038000_DIM 0xFFFFFFF8 +#define V_038000_SQ_TEX_DIM_1D 0x00000000 +#define V_038000_SQ_TEX_DIM_2D 0x00000001 +#define V_038000_SQ_TEX_DIM_3D 0x00000002 +#define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 +#define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 +#define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 +#define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 +#define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 +#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) +#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) +#define C_038000_TILE_MODE 0xFFFFFF87 +#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) +#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) +#define C_038000_TILE_TYPE 0xFFFFFF7F +#define S_038000_PITCH(x) (((x) & 0x7FF) << 8) +#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) +#define C_038000_PITCH 0xFFF800FF +#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) +#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) +#define C_038000_TEX_WIDTH 0x0007FFFF +#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 +#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) +#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) +#define C_038004_TEX_HEIGHT 0xFFFFE000 +#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) +#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) +#define C_038004_TEX_DEPTH 0xFC001FFF +#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) +#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) +#define C_038004_DATA_FORMAT 0x03FFFFFF +#define V_038004_COLOR_INVALID 0x00000000 +#define V_038004_COLOR_8 0x00000001 +#define V_038004_COLOR_4_4 0x00000002 +#define V_038004_COLOR_3_3_2 0x00000003 +#define V_038004_COLOR_16 0x00000005 +#define V_038004_COLOR_16_FLOAT 0x00000006 +#define V_038004_COLOR_8_8 0x00000007 +#define V_038004_COLOR_5_6_5 0x00000008 +#define V_038004_COLOR_6_5_5 0x00000009 +#define V_038004_COLOR_1_5_5_5 0x0000000A +#define V_038004_COLOR_4_4_4_4 0x0000000B +#define V_038004_COLOR_5_5_5_1 0x0000000C +#define V_038004_COLOR_32 0x0000000D +#define V_038004_COLOR_32_FLOAT 0x0000000E +#define V_038004_COLOR_16_16 0x0000000F +#define V_038004_COLOR_16_16_FLOAT 0x00000010 +#define V_038004_COLOR_8_24 0x00000011 +#define V_038004_COLOR_8_24_FLOAT 0x00000012 +#define V_038004_COLOR_24_8 0x00000013 +#define V_038004_COLOR_24_8_FLOAT 0x00000014 +#define V_038004_COLOR_10_11_11 0x00000015 +#define V_038004_COLOR_10_11_11_FLOAT 0x00000016 +#define V_038004_COLOR_11_11_10 0x00000017 +#define V_038004_COLOR_11_11_10_FLOAT 0x00000018 +#define V_038004_COLOR_2_10_10_10 0x00000019 +#define V_038004_COLOR_8_8_8_8 0x0000001A +#define V_038004_COLOR_10_10_10_2 0x0000001B +#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C +#define V_038004_COLOR_32_32 0x0000001D +#define V_038004_COLOR_32_32_FLOAT 0x0000001E +#define V_038004_COLOR_16_16_16_16 0x0000001F +#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 +#define V_038004_COLOR_32_32_32_32 0x00000022 +#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 +#define V_038004_FMT_1 0x00000025 +#define V_038004_FMT_GB_GR 0x00000027 +#define V_038004_FMT_BG_RG 0x00000028 +#define V_038004_FMT_32_AS_8 0x00000029 +#define V_038004_FMT_32_AS_8_8 0x0000002A +#define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B +#define V_038004_FMT_8_8_8 0x0000002C +#define V_038004_FMT_16_16_16 0x0000002D +#define V_038004_FMT_16_16_16_FLOAT 0x0000002E +#define V_038004_FMT_32_32_32 0x0000002F +#define V_038004_FMT_32_32_32_FLOAT 0x00000030 +#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 +#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) +#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) +#define C_038010_FORMAT_COMP_X 0xFFFFFFFC +#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) +#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) +#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 +#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) +#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) +#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF +#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) +#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) +#define C_038010_FORMAT_COMP_W 0xFFFFFF3F +#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) +#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) +#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF +#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) +#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) +#define C_038010_SRF_MODE_ALL 0xFFFFFBFF +#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) +#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) +#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF +#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) +#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) +#define C_038010_ENDIAN_SWAP 0xFFFFCFFF +#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) +#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) +#define C_038010_REQUEST_SIZE 0xFFFF3FFF +#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) +#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) +#define C_038010_DST_SEL_X 0xFFF8FFFF +#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) +#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) +#define C_038010_DST_SEL_Y 0xFFC7FFFF +#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) +#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) +#define C_038010_DST_SEL_Z 0xFE3FFFFF +#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) +#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) +#define C_038010_DST_SEL_W 0xF1FFFFFF +#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) +#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) +#define C_038010_BASE_LEVEL 0x0FFFFFFF +#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 +#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) +#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) +#define C_038014_LAST_LEVEL 0xFFFFFFF0 +#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) +#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) +#define C_038014_BASE_ARRAY 0xFFFE000F +#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) +#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) +#define C_038014_LAST_ARRAY 0xC001FFFF +#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 +#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288A8_ITEMSIZE 0xFFFF8000 +#define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 +#define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_008C44_MEM_SIZE 0x00000000 +#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 +#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288B0_ITEMSIZE 0xFFFF8000 +#define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 +#define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_008C54_MEM_SIZE 0x00000000 +#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 +#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288C0_ITEMSIZE 0xFFFF8000 +#define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 +#define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_008C74_MEM_SIZE 0x00000000 +#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 +#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288B4_ITEMSIZE 0xFFFF8000 +#define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C +#define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_008C5C_MEM_SIZE 0x00000000 +#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC +#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288AC_ITEMSIZE 0xFFFF8000 +#define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C +#define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_008C4C_MEM_SIZE 0x00000000 +#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC +#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288BC_ITEMSIZE 0xFFFF8000 +#define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C +#define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_008C6C_MEM_SIZE 0x00000000 +#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 +#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288C4_ITEMSIZE 0xFFFF8000 +#define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C +#define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_008C7C_MEM_SIZE 0x00000000 +#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 +#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288B8_ITEMSIZE 0xFFFF8000 +#define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 +#define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_008C64_MEM_SIZE 0x00000000 +#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 +#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288C8_ITEMSIZE 0xFFFF8000 +#define R_028010_DB_DEPTH_INFO 0x028010 +#define S_028010_FORMAT(x) (((x) & 0x7) << 0) +#define G_028010_FORMAT(x) (((x) >> 0) & 0x7) +#define C_028010_FORMAT 0xFFFFFFF8 +#define V_028010_DEPTH_INVALID 0x00000000 +#define V_028010_DEPTH_16 0x00000001 +#define V_028010_DEPTH_X8_24 0x00000002 +#define V_028010_DEPTH_8_24 0x00000003 +#define V_028010_DEPTH_X8_24_FLOAT 0x00000004 +#define V_028010_DEPTH_8_24_FLOAT 0x00000005 +#define V_028010_DEPTH_32_FLOAT 0x00000006 +#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 +#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) +#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) +#define C_028010_READ_SIZE 0xFFFFFFF7 +#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) +#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) +#define C_028010_ARRAY_MODE 0xFFF87FFF +#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) +#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) +#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF +#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) +#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) +#define C_028010_TILE_COMPACT 0xFBFFFFFF +#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) +#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) +#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF +#define R_028000_DB_DEPTH_SIZE 0x028000 +#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028000_PITCH_TILE_MAX 0xFFFFFC00 +#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) +#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) +#define C_028000_SLICE_TILE_MAX 0xC00003FF +#define R_028004_DB_DEPTH_VIEW 0x028004 +#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) +#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) +#define C_028004_SLICE_START 0xFFFFF800 +#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) +#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) +#define C_028004_SLICE_MAX 0xFF001FFF +#define R_028800_DB_DEPTH_CONTROL 0x028800 +#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) +#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028800_STENCIL_ENABLE 0xFFFFFFFE +#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) +#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) +#define C_028800_Z_ENABLE 0xFFFFFFFD +#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) +#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) +#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB +#define S_028800_ZFUNC(x) (((x) & 0x7) << 4) +#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) +#define C_028800_ZFUNC 0xFFFFFF8F +#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) +#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) +#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F +#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) +#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) +#define C_028800_STENCILFUNC 0xFFFFF8FF +#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) +#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) +#define C_028800_STENCILFAIL 0xFFFFC7FF +#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) +#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) +#define C_028800_STENCILZPASS 0xFFFE3FFF +#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) +#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) +#define C_028800_STENCILZFAIL 0xFFF1FFFF +#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) +#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) +#define C_028800_STENCILFUNC_BF 0xFF8FFFFF +#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) +#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) +#define C_028800_STENCILFAIL_BF 0xFC7FFFFF +#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) +#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) +#define C_028800_STENCILZPASS_BF 0xE3FFFFFF +#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) +#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) +#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF #endif diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index a7a96a240844..9eeca6f07222 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -808,6 +808,9 @@ struct r600_asic { unsigned sx_max_export_pos_size; unsigned sx_max_export_smx_size; unsigned sq_num_cf_insts; + unsigned tiling_nbanks; + unsigned tiling_npipes; + unsigned tiling_group_size; }; struct rv770_asic { @@ -828,6 +831,9 @@ struct rv770_asic { unsigned sc_prim_fifo_size; unsigned sc_hiz_tile_fifo_size; unsigned sc_earlyz_tile_fifo_fize; + unsigned tiling_nbanks; + unsigned tiling_npipes; + unsigned tiling_group_size; }; union radeon_asic_config { diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index e13785282a82..b058316e311f 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h @@ -294,6 +294,9 @@ typedef struct drm_radeon_private { int r700_sc_prim_fifo_size; int r700_sc_hiz_tile_fifo_size; int r700_sc_earlyz_tile_fifo_fize; + int r600_group_size; + int r600_npipes; + int r600_nbanks; struct mutex cs_mutex; u32 cs_id_scnt; diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600 new file mode 100644 index 000000000000..8f414a5f520f --- /dev/null +++ b/drivers/gpu/drm/radeon/reg_srcs/r600 @@ -0,0 +1,837 @@ +r600 0x9400 +0x000287A0 R7xx_CB_SHADER_CONTROL +0x00028230 R7xx_PA_SC_EDGERULE +0x000286C8 R7xx_SPI_THREAD_GROUPING +0x00008D8C R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ +0x000088C4 VGT_CACHE_INVALIDATION +0x00028A50 VGT_ENHANCE +0x000088CC VGT_ES_PER_GS +0x00028A2C VGT_GROUP_DECR +0x00028A28 VGT_GROUP_FIRST_DECR +0x00028A24 VGT_GROUP_PRIM_TYPE +0x00028A30 VGT_GROUP_VECT_0_CNTL +0x00028A38 VGT_GROUP_VECT_0_FMT_CNTL +0x00028A34 VGT_GROUP_VECT_1_CNTL +0x00028A3C VGT_GROUP_VECT_1_FMT_CNTL +0x00028A40 VGT_GS_MODE +0x00028A6C VGT_GS_OUT_PRIM_TYPE +0x000088C8 VGT_GS_PER_ES +0x000088E8 VGT_GS_PER_VS +0x000088D4 VGT_GS_VERTEX_REUSE +0x00028A14 VGT_HOS_CNTL +0x00028A18 VGT_HOS_MAX_TESS_LEVEL +0x00028A1C VGT_HOS_MIN_TESS_LEVEL +0x00028A20 VGT_HOS_REUSE_DEPTH +0x0000895C VGT_INDEX_TYPE +0x00028408 VGT_INDX_OFFSET +0x00028AA0 VGT_INSTANCE_STEP_RATE_0 +0x00028AA4 VGT_INSTANCE_STEP_RATE_1 +0x000088C0 VGT_LAST_COPY_STATE +0x00028400 VGT_MAX_VTX_INDX +0x000088D8 VGT_MC_LAT_CNTL +0x00028404 VGT_MIN_VTX_INDX +0x00028A94 VGT_MULTI_PRIM_IB_RESET_EN +0x0002840C VGT_MULTI_PRIM_IB_RESET_INDX +0x00008970 VGT_NUM_INDICES +0x00008974 VGT_NUM_INSTANCES +0x00028A10 VGT_OUTPUT_PATH_CNTL +0x00028C5C VGT_OUT_DEALLOC_CNTL +0x00028A84 VGT_PRIMITIVEID_EN +0x00008958 VGT_PRIMITIVE_TYPE +0x00028AB4 VGT_REUSE_OFF +0x00028C58 VGT_VERTEX_REUSE_BLOCK_CNTL +0x00028AB8 VGT_VTX_CNT_EN +0x000088B0 VGT_VTX_VECT_EJECT_REG +0x00028810 PA_CL_CLIP_CNTL +0x00008A14 PA_CL_ENHANCE +0x00028C14 PA_CL_GB_HORZ_CLIP_ADJ +0x00028C18 PA_CL_GB_HORZ_DISC_ADJ +0x00028C0C PA_CL_GB_VERT_CLIP_ADJ +0x00028C10 PA_CL_GB_VERT_DISC_ADJ +0x00028820 PA_CL_NANINF_CNTL +0x00028E1C PA_CL_POINT_CULL_RAD +0x00028E18 PA_CL_POINT_SIZE +0x00028E10 PA_CL_POINT_X_RAD +0x00028E14 PA_CL_POINT_Y_RAD +0x00028E2C PA_CL_UCP_0_W +0x00028E3C PA_CL_UCP_1_W +0x00028E4C PA_CL_UCP_2_W +0x00028E5C PA_CL_UCP_3_W +0x00028E6C PA_CL_UCP_4_W +0x00028E7C PA_CL_UCP_5_W +0x00028E20 PA_CL_UCP_0_X +0x00028E30 PA_CL_UCP_1_X +0x00028E40 PA_CL_UCP_2_X +0x00028E50 PA_CL_UCP_3_X +0x00028E60 PA_CL_UCP_4_X +0x00028E70 PA_CL_UCP_5_X +0x00028E24 PA_CL_UCP_0_Y +0x00028E34 PA_CL_UCP_1_Y +0x00028E44 PA_CL_UCP_2_Y +0x00028E54 PA_CL_UCP_3_Y +0x00028E64 PA_CL_UCP_4_Y +0x00028E74 PA_CL_UCP_5_Y +0x00028E28 PA_CL_UCP_0_Z +0x00028E38 PA_CL_UCP_1_Z +0x00028E48 PA_CL_UCP_2_Z +0x00028E58 PA_CL_UCP_3_Z +0x00028E68 PA_CL_UCP_4_Z +0x00028E78 PA_CL_UCP_5_Z +0x00028440 PA_CL_VPORT_XOFFSET_0 +0x00028458 PA_CL_VPORT_XOFFSET_1 +0x00028470 PA_CL_VPORT_XOFFSET_2 +0x00028488 PA_CL_VPORT_XOFFSET_3 +0x000284A0 PA_CL_VPORT_XOFFSET_4 +0x000284B8 PA_CL_VPORT_XOFFSET_5 +0x000284D0 PA_CL_VPORT_XOFFSET_6 +0x000284E8 PA_CL_VPORT_XOFFSET_7 +0x00028500 PA_CL_VPORT_XOFFSET_8 +0x00028518 PA_CL_VPORT_XOFFSET_9 +0x00028530 PA_CL_VPORT_XOFFSET_10 +0x00028548 PA_CL_VPORT_XOFFSET_11 +0x00028560 PA_CL_VPORT_XOFFSET_12 +0x00028578 PA_CL_VPORT_XOFFSET_13 +0x00028590 PA_CL_VPORT_XOFFSET_14 +0x000285A8 PA_CL_VPORT_XOFFSET_15 +0x0002843C PA_CL_VPORT_XSCALE_0 +0x00028454 PA_CL_VPORT_XSCALE_1 +0x0002846C PA_CL_VPORT_XSCALE_2 +0x00028484 PA_CL_VPORT_XSCALE_3 +0x0002849C PA_CL_VPORT_XSCALE_4 +0x000284B4 PA_CL_VPORT_XSCALE_5 +0x000284CC PA_CL_VPORT_XSCALE_6 +0x000284E4 PA_CL_VPORT_XSCALE_7 +0x000284FC PA_CL_VPORT_XSCALE_8 +0x00028514 PA_CL_VPORT_XSCALE_9 +0x0002852C PA_CL_VPORT_XSCALE_10 +0x00028544 PA_CL_VPORT_XSCALE_11 +0x0002855C PA_CL_VPORT_XSCALE_12 +0x00028574 PA_CL_VPORT_XSCALE_13 +0x0002858C PA_CL_VPORT_XSCALE_14 +0x000285A4 PA_CL_VPORT_XSCALE_15 +0x00028448 PA_CL_VPORT_YOFFSET_0 +0x00028460 PA_CL_VPORT_YOFFSET_1 +0x00028478 PA_CL_VPORT_YOFFSET_2 +0x00028490 PA_CL_VPORT_YOFFSET_3 +0x000284A8 PA_CL_VPORT_YOFFSET_4 +0x000284C0 PA_CL_VPORT_YOFFSET_5 +0x000284D8 PA_CL_VPORT_YOFFSET_6 +0x000284F0 PA_CL_VPORT_YOFFSET_7 +0x00028508 PA_CL_VPORT_YOFFSET_8 +0x00028520 PA_CL_VPORT_YOFFSET_9 +0x00028538 PA_CL_VPORT_YOFFSET_10 +0x00028550 PA_CL_VPORT_YOFFSET_11 +0x00028568 PA_CL_VPORT_YOFFSET_12 +0x00028580 PA_CL_VPORT_YOFFSET_13 +0x00028598 PA_CL_VPORT_YOFFSET_14 +0x000285B0 PA_CL_VPORT_YOFFSET_15 +0x00028444 PA_CL_VPORT_YSCALE_0 +0x0002845C PA_CL_VPORT_YSCALE_1 +0x00028474 PA_CL_VPORT_YSCALE_2 +0x0002848C PA_CL_VPORT_YSCALE_3 +0x000284A4 PA_CL_VPORT_YSCALE_4 +0x000284BC PA_CL_VPORT_YSCALE_5 +0x000284D4 PA_CL_VPORT_YSCALE_6 +0x000284EC PA_CL_VPORT_YSCALE_7 +0x00028504 PA_CL_VPORT_YSCALE_8 +0x0002851C PA_CL_VPORT_YSCALE_9 +0x00028534 PA_CL_VPORT_YSCALE_10 +0x0002854C PA_CL_VPORT_YSCALE_11 +0x00028564 PA_CL_VPORT_YSCALE_12 +0x0002857C PA_CL_VPORT_YSCALE_13 +0x00028594 PA_CL_VPORT_YSCALE_14 +0x000285AC PA_CL_VPORT_YSCALE_15 +0x00028450 PA_CL_VPORT_ZOFFSET_0 +0x00028468 PA_CL_VPORT_ZOFFSET_1 +0x00028480 PA_CL_VPORT_ZOFFSET_2 +0x00028498 PA_CL_VPORT_ZOFFSET_3 +0x000284B0 PA_CL_VPORT_ZOFFSET_4 +0x000284C8 PA_CL_VPORT_ZOFFSET_5 +0x000284E0 PA_CL_VPORT_ZOFFSET_6 +0x000284F8 PA_CL_VPORT_ZOFFSET_7 +0x00028510 PA_CL_VPORT_ZOFFSET_8 +0x00028528 PA_CL_VPORT_ZOFFSET_9 +0x00028540 PA_CL_VPORT_ZOFFSET_10 +0x00028558 PA_CL_VPORT_ZOFFSET_11 +0x00028570 PA_CL_VPORT_ZOFFSET_12 +0x00028588 PA_CL_VPORT_ZOFFSET_13 +0x000285A0 PA_CL_VPORT_ZOFFSET_14 +0x000285B8 PA_CL_VPORT_ZOFFSET_15 +0x0002844C PA_CL_VPORT_ZSCALE_0 +0x00028464 PA_CL_VPORT_ZSCALE_1 +0x0002847C PA_CL_VPORT_ZSCALE_2 +0x00028494 PA_CL_VPORT_ZSCALE_3 +0x000284AC PA_CL_VPORT_ZSCALE_4 +0x000284C4 PA_CL_VPORT_ZSCALE_5 +0x000284DC PA_CL_VPORT_ZSCALE_6 +0x000284F4 PA_CL_VPORT_ZSCALE_7 +0x0002850C PA_CL_VPORT_ZSCALE_8 +0x00028524 PA_CL_VPORT_ZSCALE_9 +0x0002853C PA_CL_VPORT_ZSCALE_10 +0x00028554 PA_CL_VPORT_ZSCALE_11 +0x0002856C PA_CL_VPORT_ZSCALE_12 +0x00028584 PA_CL_VPORT_ZSCALE_13 +0x0002859C PA_CL_VPORT_ZSCALE_14 +0x000285B4 PA_CL_VPORT_ZSCALE_15 +0x0002881C PA_CL_VS_OUT_CNTL +0x00028818 PA_CL_VTE_CNTL +0x00028C48 PA_SC_AA_MASK +0x00008B40 PA_SC_AA_SAMPLE_LOCS_2S +0x00008B44 PA_SC_AA_SAMPLE_LOCS_4S +0x00008B48 PA_SC_AA_SAMPLE_LOCS_8S_WD0 +0x00008B4C PA_SC_AA_SAMPLE_LOCS_8S_WD1 +0x00028C20 PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX +0x00028C1C PA_SC_AA_SAMPLE_LOCS_MCTX +0x00028214 PA_SC_CLIPRECT_0_BR +0x0002821C PA_SC_CLIPRECT_1_BR +0x00028224 PA_SC_CLIPRECT_2_BR +0x0002822C PA_SC_CLIPRECT_3_BR +0x00028210 PA_SC_CLIPRECT_0_TL +0x00028218 PA_SC_CLIPRECT_1_TL +0x00028220 PA_SC_CLIPRECT_2_TL +0x00028228 PA_SC_CLIPRECT_3_TL +0x0002820C PA_SC_CLIPRECT_RULE +0x00008BF0 PA_SC_ENHANCE +0x00028244 PA_SC_GENERIC_SCISSOR_BR +0x00028240 PA_SC_GENERIC_SCISSOR_TL +0x00028C00 PA_SC_LINE_CNTL +0x00028A0C PA_SC_LINE_STIPPLE +0x00008B10 PA_SC_LINE_STIPPLE_STATE +0x00028A4C PA_SC_MODE_CNTL +0x00028A48 PA_SC_MPASS_PS_CNTL +0x00008B20 PA_SC_MULTI_CHIP_CNTL +0x00028034 PA_SC_SCREEN_SCISSOR_BR +0x00028030 PA_SC_SCREEN_SCISSOR_TL +0x00028254 PA_SC_VPORT_SCISSOR_0_BR +0x0002825C PA_SC_VPORT_SCISSOR_1_BR +0x00028264 PA_SC_VPORT_SCISSOR_2_BR +0x0002826C PA_SC_VPORT_SCISSOR_3_BR +0x00028274 PA_SC_VPORT_SCISSOR_4_BR +0x0002827C PA_SC_VPORT_SCISSOR_5_BR +0x00028284 PA_SC_VPORT_SCISSOR_6_BR +0x0002828C PA_SC_VPORT_SCISSOR_7_BR +0x00028294 PA_SC_VPORT_SCISSOR_8_BR +0x0002829C PA_SC_VPORT_SCISSOR_9_BR +0x000282A4 PA_SC_VPORT_SCISSOR_10_BR +0x000282AC PA_SC_VPORT_SCISSOR_11_BR +0x000282B4 PA_SC_VPORT_SCISSOR_12_BR +0x000282BC PA_SC_VPORT_SCISSOR_13_BR +0x000282C4 PA_SC_VPORT_SCISSOR_14_BR +0x000282CC PA_SC_VPORT_SCISSOR_15_BR +0x00028250 PA_SC_VPORT_SCISSOR_0_TL +0x00028258 PA_SC_VPORT_SCISSOR_1_TL +0x00028260 PA_SC_VPORT_SCISSOR_2_TL +0x00028268 PA_SC_VPORT_SCISSOR_3_TL +0x00028270 PA_SC_VPORT_SCISSOR_4_TL +0x00028278 PA_SC_VPORT_SCISSOR_5_TL +0x00028280 PA_SC_VPORT_SCISSOR_6_TL +0x00028288 PA_SC_VPORT_SCISSOR_7_TL +0x00028290 PA_SC_VPORT_SCISSOR_8_TL +0x00028298 PA_SC_VPORT_SCISSOR_9_TL +0x000282A0 PA_SC_VPORT_SCISSOR_10_TL +0x000282A8 PA_SC_VPORT_SCISSOR_11_TL +0x000282B0 PA_SC_VPORT_SCISSOR_12_TL +0x000282B8 PA_SC_VPORT_SCISSOR_13_TL +0x000282C0 PA_SC_VPORT_SCISSOR_14_TL +0x000282C8 PA_SC_VPORT_SCISSOR_15_TL +0x000282D4 PA_SC_VPORT_ZMAX_0 +0x000282DC PA_SC_VPORT_ZMAX_1 +0x000282E4 PA_SC_VPORT_ZMAX_2 +0x000282EC PA_SC_VPORT_ZMAX_3 +0x000282F4 PA_SC_VPORT_ZMAX_4 +0x000282FC PA_SC_VPORT_ZMAX_5 +0x00028304 PA_SC_VPORT_ZMAX_6 +0x0002830C PA_SC_VPORT_ZMAX_7 +0x00028314 PA_SC_VPORT_ZMAX_8 +0x0002831C PA_SC_VPORT_ZMAX_9 +0x00028324 PA_SC_VPORT_ZMAX_10 +0x0002832C PA_SC_VPORT_ZMAX_11 +0x00028334 PA_SC_VPORT_ZMAX_12 +0x0002833C PA_SC_VPORT_ZMAX_13 +0x00028344 PA_SC_VPORT_ZMAX_14 +0x0002834C PA_SC_VPORT_ZMAX_15 +0x000282D0 PA_SC_VPORT_ZMIN_0 +0x000282D8 PA_SC_VPORT_ZMIN_1 +0x000282E0 PA_SC_VPORT_ZMIN_2 +0x000282E8 PA_SC_VPORT_ZMIN_3 +0x000282F0 PA_SC_VPORT_ZMIN_4 +0x000282F8 PA_SC_VPORT_ZMIN_5 +0x00028300 PA_SC_VPORT_ZMIN_6 +0x00028308 PA_SC_VPORT_ZMIN_7 +0x00028310 PA_SC_VPORT_ZMIN_8 +0x00028318 PA_SC_VPORT_ZMIN_9 +0x00028320 PA_SC_VPORT_ZMIN_10 +0x00028328 PA_SC_VPORT_ZMIN_11 +0x00028330 PA_SC_VPORT_ZMIN_12 +0x00028338 PA_SC_VPORT_ZMIN_13 +0x00028340 PA_SC_VPORT_ZMIN_14 +0x00028348 PA_SC_VPORT_ZMIN_15 +0x00028200 PA_SC_WINDOW_OFFSET +0x00028208 PA_SC_WINDOW_SCISSOR_BR +0x00028204 PA_SC_WINDOW_SCISSOR_TL +0x00028A08 PA_SU_LINE_CNTL +0x00028A04 PA_SU_POINT_MINMAX +0x00028A00 PA_SU_POINT_SIZE +0x00028E0C PA_SU_POLY_OFFSET_BACK_OFFSET +0x00028E08 PA_SU_POLY_OFFSET_BACK_SCALE +0x00028DFC PA_SU_POLY_OFFSET_CLAMP +0x00028DF8 PA_SU_POLY_OFFSET_DB_FMT_CNTL +0x00028E04 PA_SU_POLY_OFFSET_FRONT_OFFSET +0x00028E00 PA_SU_POLY_OFFSET_FRONT_SCALE +0x00028814 PA_SU_SC_MODE_CNTL +0x00028C08 PA_SU_VTX_CNTL +0x00008C00 SQ_CONFIG +0x00008C04 SQ_GPR_RESOURCE_MGMT_1 +0x00008C08 SQ_GPR_RESOURCE_MGMT_2 +0x00008C10 SQ_STACK_RESOURCE_MGMT_1 +0x00008C14 SQ_STACK_RESOURCE_MGMT_2 +0x00008C0C SQ_THREAD_RESOURCE_MGMT +0x00028380 SQ_VTX_SEMANTIC_0 +0x00028384 SQ_VTX_SEMANTIC_1 +0x00028388 SQ_VTX_SEMANTIC_2 +0x0002838C SQ_VTX_SEMANTIC_3 +0x00028390 SQ_VTX_SEMANTIC_4 +0x00028394 SQ_VTX_SEMANTIC_5 +0x00028398 SQ_VTX_SEMANTIC_6 +0x0002839C SQ_VTX_SEMANTIC_7 +0x000283A0 SQ_VTX_SEMANTIC_8 +0x000283A4 SQ_VTX_SEMANTIC_9 +0x000283A8 SQ_VTX_SEMANTIC_10 +0x000283AC SQ_VTX_SEMANTIC_11 +0x000283B0 SQ_VTX_SEMANTIC_12 +0x000283B4 SQ_VTX_SEMANTIC_13 +0x000283B8 SQ_VTX_SEMANTIC_14 +0x000283BC SQ_VTX_SEMANTIC_15 +0x000283C0 SQ_VTX_SEMANTIC_16 +0x000283C4 SQ_VTX_SEMANTIC_17 +0x000283C8 SQ_VTX_SEMANTIC_18 +0x000283CC SQ_VTX_SEMANTIC_19 +0x000283D0 SQ_VTX_SEMANTIC_20 +0x000283D4 SQ_VTX_SEMANTIC_21 +0x000283D8 SQ_VTX_SEMANTIC_22 +0x000283DC SQ_VTX_SEMANTIC_23 +0x000283E0 SQ_VTX_SEMANTIC_24 +0x000283E4 SQ_VTX_SEMANTIC_25 +0x000283E8 SQ_VTX_SEMANTIC_26 +0x000283EC SQ_VTX_SEMANTIC_27 +0x000283F0 SQ_VTX_SEMANTIC_28 +0x000283F4 SQ_VTX_SEMANTIC_29 +0x000283F8 SQ_VTX_SEMANTIC_30 +0x000283FC SQ_VTX_SEMANTIC_31 +0x000288E0 SQ_VTX_SEMANTIC_CLEAR +0x0003CFF4 SQ_VTX_START_INST_LOC +0x0003C000 SQ_TEX_SAMPLER_WORD0_0 +0x0003C004 SQ_TEX_SAMPLER_WORD1_0 +0x0003C008 SQ_TEX_SAMPLER_WORD2_0 +0x00030000 SQ_ALU_CONSTANT0_0 +0x00030004 SQ_ALU_CONSTANT1_0 +0x00030008 SQ_ALU_CONSTANT2_0 +0x0003000C SQ_ALU_CONSTANT3_0 +0x0003E380 SQ_BOOL_CONST_0 +0x0003E384 SQ_BOOL_CONST_1 +0x0003E388 SQ_BOOL_CONST_2 +0x0003E200 SQ_LOOP_CONST_0 +0x0003E200 SQ_LOOP_CONST_DX10_0 +0x000281C0 SQ_ALU_CONST_BUFFER_SIZE_GS_0 +0x000281C4 SQ_ALU_CONST_BUFFER_SIZE_GS_1 +0x000281C8 SQ_ALU_CONST_BUFFER_SIZE_GS_2 +0x000281CC SQ_ALU_CONST_BUFFER_SIZE_GS_3 +0x000281D0 SQ_ALU_CONST_BUFFER_SIZE_GS_4 +0x000281D4 SQ_ALU_CONST_BUFFER_SIZE_GS_5 +0x000281D8 SQ_ALU_CONST_BUFFER_SIZE_GS_6 +0x000281DC SQ_ALU_CONST_BUFFER_SIZE_GS_7 +0x000281E0 SQ_ALU_CONST_BUFFER_SIZE_GS_8 +0x000281E4 SQ_ALU_CONST_BUFFER_SIZE_GS_9 +0x000281E8 SQ_ALU_CONST_BUFFER_SIZE_GS_10 +0x000281EC SQ_ALU_CONST_BUFFER_SIZE_GS_11 +0x000281F0 SQ_ALU_CONST_BUFFER_SIZE_GS_12 +0x000281F4 SQ_ALU_CONST_BUFFER_SIZE_GS_13 +0x000281F8 SQ_ALU_CONST_BUFFER_SIZE_GS_14 +0x000281FC SQ_ALU_CONST_BUFFER_SIZE_GS_15 +0x00028140 SQ_ALU_CONST_BUFFER_SIZE_PS_0 +0x00028144 SQ_ALU_CONST_BUFFER_SIZE_PS_1 +0x00028148 SQ_ALU_CONST_BUFFER_SIZE_PS_2 +0x0002814C SQ_ALU_CONST_BUFFER_SIZE_PS_3 +0x00028150 SQ_ALU_CONST_BUFFER_SIZE_PS_4 +0x00028154 SQ_ALU_CONST_BUFFER_SIZE_PS_5 +0x00028158 SQ_ALU_CONST_BUFFER_SIZE_PS_6 +0x0002815C SQ_ALU_CONST_BUFFER_SIZE_PS_7 +0x00028160 SQ_ALU_CONST_BUFFER_SIZE_PS_8 +0x00028164 SQ_ALU_CONST_BUFFER_SIZE_PS_9 +0x00028168 SQ_ALU_CONST_BUFFER_SIZE_PS_10 +0x0002816C SQ_ALU_CONST_BUFFER_SIZE_PS_11 +0x00028170 SQ_ALU_CONST_BUFFER_SIZE_PS_12 +0x00028174 SQ_ALU_CONST_BUFFER_SIZE_PS_13 +0x00028178 SQ_ALU_CONST_BUFFER_SIZE_PS_14 +0x0002817C SQ_ALU_CONST_BUFFER_SIZE_PS_15 +0x00028180 SQ_ALU_CONST_BUFFER_SIZE_VS_0 +0x00028184 SQ_ALU_CONST_BUFFER_SIZE_VS_1 +0x00028188 SQ_ALU_CONST_BUFFER_SIZE_VS_2 +0x0002818C SQ_ALU_CONST_BUFFER_SIZE_VS_3 +0x00028190 SQ_ALU_CONST_BUFFER_SIZE_VS_4 +0x00028194 SQ_ALU_CONST_BUFFER_SIZE_VS_5 +0x00028198 SQ_ALU_CONST_BUFFER_SIZE_VS_6 +0x0002819C SQ_ALU_CONST_BUFFER_SIZE_VS_7 +0x000281A0 SQ_ALU_CONST_BUFFER_SIZE_VS_8 +0x000281A4 SQ_ALU_CONST_BUFFER_SIZE_VS_9 +0x000281A8 SQ_ALU_CONST_BUFFER_SIZE_VS_10 +0x000281AC SQ_ALU_CONST_BUFFER_SIZE_VS_11 +0x000281B0 SQ_ALU_CONST_BUFFER_SIZE_VS_12 +0x000281B4 SQ_ALU_CONST_BUFFER_SIZE_VS_13 +0x000281B8 SQ_ALU_CONST_BUFFER_SIZE_VS_14 +0x000281BC SQ_ALU_CONST_BUFFER_SIZE_VS_15 +0x000289C0 SQ_ALU_CONST_CACHE_GS_0 +0x000289C4 SQ_ALU_CONST_CACHE_GS_1 +0x000289C8 SQ_ALU_CONST_CACHE_GS_2 +0x000289CC SQ_ALU_CONST_CACHE_GS_3 +0x000289D0 SQ_ALU_CONST_CACHE_GS_4 +0x000289D4 SQ_ALU_CONST_CACHE_GS_5 +0x000289D8 SQ_ALU_CONST_CACHE_GS_6 +0x000289DC SQ_ALU_CONST_CACHE_GS_7 +0x000289E0 SQ_ALU_CONST_CACHE_GS_8 +0x000289E4 SQ_ALU_CONST_CACHE_GS_9 +0x000289E8 SQ_ALU_CONST_CACHE_GS_10 +0x000289EC SQ_ALU_CONST_CACHE_GS_11 +0x000289F0 SQ_ALU_CONST_CACHE_GS_12 +0x000289F4 SQ_ALU_CONST_CACHE_GS_13 +0x000289F8 SQ_ALU_CONST_CACHE_GS_14 +0x000289FC SQ_ALU_CONST_CACHE_GS_15 +0x00028940 SQ_ALU_CONST_CACHE_PS_0 +0x00028944 SQ_ALU_CONST_CACHE_PS_1 +0x00028948 SQ_ALU_CONST_CACHE_PS_2 +0x0002894C SQ_ALU_CONST_CACHE_PS_3 +0x00028950 SQ_ALU_CONST_CACHE_PS_4 +0x00028954 SQ_ALU_CONST_CACHE_PS_5 +0x00028958 SQ_ALU_CONST_CACHE_PS_6 +0x0002895C SQ_ALU_CONST_CACHE_PS_7 +0x00028960 SQ_ALU_CONST_CACHE_PS_8 +0x00028964 SQ_ALU_CONST_CACHE_PS_9 +0x00028968 SQ_ALU_CONST_CACHE_PS_10 +0x0002896C SQ_ALU_CONST_CACHE_PS_11 +0x00028970 SQ_ALU_CONST_CACHE_PS_12 +0x00028974 SQ_ALU_CONST_CACHE_PS_13 +0x00028978 SQ_ALU_CONST_CACHE_PS_14 +0x0002897C SQ_ALU_CONST_CACHE_PS_15 +0x00028980 SQ_ALU_CONST_CACHE_VS_0 +0x00028984 SQ_ALU_CONST_CACHE_VS_1 +0x00028988 SQ_ALU_CONST_CACHE_VS_2 +0x0002898C SQ_ALU_CONST_CACHE_VS_3 +0x00028990 SQ_ALU_CONST_CACHE_VS_4 +0x00028994 SQ_ALU_CONST_CACHE_VS_5 +0x00028998 SQ_ALU_CONST_CACHE_VS_6 +0x0002899C SQ_ALU_CONST_CACHE_VS_7 +0x000289A0 SQ_ALU_CONST_CACHE_VS_8 +0x000289A4 SQ_ALU_CONST_CACHE_VS_9 +0x000289A8 SQ_ALU_CONST_CACHE_VS_10 +0x000289AC SQ_ALU_CONST_CACHE_VS_11 +0x000289B0 SQ_ALU_CONST_CACHE_VS_12 +0x000289B4 SQ_ALU_CONST_CACHE_VS_13 +0x000289B8 SQ_ALU_CONST_CACHE_VS_14 +0x000289BC SQ_ALU_CONST_CACHE_VS_15 +0x000288D8 SQ_PGM_CF_OFFSET_ES +0x000288DC SQ_PGM_CF_OFFSET_FS +0x000288D4 SQ_PGM_CF_OFFSET_GS +0x000288CC SQ_PGM_CF_OFFSET_PS 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TD_VS_SAMPLER10_BORDER_ALPHA +0x0000A6BC TD_VS_SAMPLER11_BORDER_ALPHA +0x0000A6CC TD_VS_SAMPLER12_BORDER_ALPHA +0x0000A6DC TD_VS_SAMPLER13_BORDER_ALPHA +0x0000A6EC TD_VS_SAMPLER14_BORDER_ALPHA +0x0000A6FC TD_VS_SAMPLER15_BORDER_ALPHA +0x0000A70C TD_VS_SAMPLER16_BORDER_ALPHA +0x0000A71C TD_VS_SAMPLER17_BORDER_ALPHA +0x0000A608 TD_VS_SAMPLER0_BORDER_BLUE +0x0000A618 TD_VS_SAMPLER1_BORDER_BLUE +0x0000A628 TD_VS_SAMPLER2_BORDER_BLUE +0x0000A638 TD_VS_SAMPLER3_BORDER_BLUE +0x0000A648 TD_VS_SAMPLER4_BORDER_BLUE +0x0000A658 TD_VS_SAMPLER5_BORDER_BLUE +0x0000A668 TD_VS_SAMPLER6_BORDER_BLUE +0x0000A678 TD_VS_SAMPLER7_BORDER_BLUE +0x0000A688 TD_VS_SAMPLER8_BORDER_BLUE +0x0000A698 TD_VS_SAMPLER9_BORDER_BLUE +0x0000A6A8 TD_VS_SAMPLER10_BORDER_BLUE +0x0000A6B8 TD_VS_SAMPLER11_BORDER_BLUE +0x0000A6C8 TD_VS_SAMPLER12_BORDER_BLUE +0x0000A6D8 TD_VS_SAMPLER13_BORDER_BLUE +0x0000A6E8 TD_VS_SAMPLER14_BORDER_BLUE +0x0000A6F8 TD_VS_SAMPLER15_BORDER_BLUE +0x0000A708 TD_VS_SAMPLER16_BORDER_BLUE +0x0000A718 TD_VS_SAMPLER17_BORDER_BLUE +0x0000A604 TD_VS_SAMPLER0_BORDER_GREEN +0x0000A614 TD_VS_SAMPLER1_BORDER_GREEN +0x0000A624 TD_VS_SAMPLER2_BORDER_GREEN +0x0000A634 TD_VS_SAMPLER3_BORDER_GREEN +0x0000A644 TD_VS_SAMPLER4_BORDER_GREEN +0x0000A654 TD_VS_SAMPLER5_BORDER_GREEN +0x0000A664 TD_VS_SAMPLER6_BORDER_GREEN +0x0000A674 TD_VS_SAMPLER7_BORDER_GREEN +0x0000A684 TD_VS_SAMPLER8_BORDER_GREEN +0x0000A694 TD_VS_SAMPLER9_BORDER_GREEN +0x0000A6A4 TD_VS_SAMPLER10_BORDER_GREEN +0x0000A6B4 TD_VS_SAMPLER11_BORDER_GREEN +0x0000A6C4 TD_VS_SAMPLER12_BORDER_GREEN +0x0000A6D4 TD_VS_SAMPLER13_BORDER_GREEN +0x0000A6E4 TD_VS_SAMPLER14_BORDER_GREEN +0x0000A6F4 TD_VS_SAMPLER15_BORDER_GREEN +0x0000A704 TD_VS_SAMPLER16_BORDER_GREEN +0x0000A714 TD_VS_SAMPLER17_BORDER_GREEN +0x0000A600 TD_VS_SAMPLER0_BORDER_RED +0x0000A610 TD_VS_SAMPLER1_BORDER_RED +0x0000A620 TD_VS_SAMPLER2_BORDER_RED +0x0000A630 TD_VS_SAMPLER3_BORDER_RED +0x0000A640 TD_VS_SAMPLER4_BORDER_RED +0x0000A650 TD_VS_SAMPLER5_BORDER_RED +0x0000A660 TD_VS_SAMPLER6_BORDER_RED +0x0000A670 TD_VS_SAMPLER7_BORDER_RED +0x0000A680 TD_VS_SAMPLER8_BORDER_RED +0x0000A690 TD_VS_SAMPLER9_BORDER_RED +0x0000A6A0 TD_VS_SAMPLER10_BORDER_RED +0x0000A6B0 TD_VS_SAMPLER11_BORDER_RED +0x0000A6C0 TD_VS_SAMPLER12_BORDER_RED +0x0000A6D0 TD_VS_SAMPLER13_BORDER_RED +0x0000A6E0 TD_VS_SAMPLER14_BORDER_RED +0x0000A6F0 TD_VS_SAMPLER15_BORDER_RED +0x0000A700 TD_VS_SAMPLER16_BORDER_RED +0x0000A710 TD_VS_SAMPLER17_BORDER_RED +0x00009508 TA_CNTL_AUX +0x0002802C DB_DEPTH_CLEAR +0x00028D24 DB_HTILE_SURFACE +0x00028D34 DB_PREFETCH_LIMIT +0x00028D30 DB_PRELOAD_CONTROL +0x00028D0C DB_RENDER_CONTROL +0x00028D10 DB_RENDER_OVERRIDE +0x0002880C DB_SHADER_CONTROL +0x00028D2C DB_SRESULTS_COMPARE_STATE1 +0x00028430 DB_STENCILREFMASK +0x00028434 DB_STENCILREFMASK_BF +0x00028028 DB_STENCIL_CLEAR +0x00028780 CB_BLEND0_CONTROL +0x00028784 CB_BLEND1_CONTROL +0x00028788 CB_BLEND2_CONTROL +0x0002878C CB_BLEND3_CONTROL +0x00028790 CB_BLEND4_CONTROL +0x00028794 CB_BLEND5_CONTROL +0x00028798 CB_BLEND6_CONTROL +0x0002879C CB_BLEND7_CONTROL +0x00028804 CB_BLEND_CONTROL +0x00028420 CB_BLEND_ALPHA +0x0002841C CB_BLEND_BLUE +0x00028418 CB_BLEND_GREEN +0x00028414 CB_BLEND_RED +0x0002812C CB_CLEAR_ALPHA +0x00028128 CB_CLEAR_BLUE +0x00028124 CB_CLEAR_GREEN +0x00028120 CB_CLEAR_RED +0x00028C30 CB_CLRCMP_CONTROL +0x00028C38 CB_CLRCMP_DST +0x00028C3C CB_CLRCMP_MSK +0x00028C34 CB_CLRCMP_SRC +0x00028100 CB_COLOR0_MASK +0x00028104 CB_COLOR1_MASK +0x00028108 CB_COLOR2_MASK +0x0002810C CB_COLOR3_MASK +0x00028110 CB_COLOR4_MASK +0x00028114 CB_COLOR5_MASK +0x00028118 CB_COLOR6_MASK +0x0002811C CB_COLOR7_MASK +0x00028080 CB_COLOR0_VIEW +0x00028084 CB_COLOR1_VIEW +0x00028088 CB_COLOR2_VIEW +0x0002808C CB_COLOR3_VIEW +0x00028090 CB_COLOR4_VIEW +0x00028094 CB_COLOR5_VIEW +0x00028098 CB_COLOR6_VIEW +0x0002809C CB_COLOR7_VIEW +0x00028808 CB_COLOR_CONTROL +0x0002842C CB_FOG_BLUE +0x00028428 CB_FOG_GREEN +0x00028424 CB_FOG_RED +0x00008040 WAIT_UNTIL +0x00008950 CC_GC_SHADER_PIPE_CONFIG +0x00008954 GC_USER_SHADER_PIPE_CONFIG +0x00009714 VC_ENHANCE +0x00009830 DB_DEBUG +0x00009838 DB_WATERMARKS +0x00028D28 DB_SRESULTS_COMPARE_STATE0 +0x00028D44 DB_ALPHA_TO_MASK +0x00009504 TA_CNTL +0x00009700 VC_CNTL +0x00009718 VC_CONFIG +0x0000A02C SMX_DC_MC_INTF_CTL diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index c9320e727986..3ecd138815d8 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -516,15 +516,19 @@ static void rv770_gpu_init(struct radeon_device *rdev) switch (rdev->config.rv770.max_tile_pipes) { case 1: gb_tiling_config |= PIPE_TILING(0); + rdev->config.rv770.tiling_npipes = 1; break; case 2: gb_tiling_config |= PIPE_TILING(1); + rdev->config.rv770.tiling_npipes = 2; break; case 4: gb_tiling_config |= PIPE_TILING(2); + rdev->config.rv770.tiling_npipes = 4; break; case 8: gb_tiling_config |= PIPE_TILING(3); + rdev->config.rv770.tiling_npipes = 8; break; default: break; @@ -534,8 +538,10 @@ static void rv770_gpu_init(struct radeon_device *rdev) gb_tiling_config |= BANK_TILING(1); else gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); + rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); gb_tiling_config |= GROUP_SIZE(0); + rdev->config.rv770.tiling_group_size = 256; if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { gb_tiling_config |= ROW_TILING(3); -- cgit v1.2.3 From 03047cdf724d8de9fbfd38b53d768c190225290f Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Wed, 10 Feb 2010 11:05:11 +0100 Subject: drm/radeon/kms: Test rdev->bios centrally in combios_get_table_offset(). MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's happened time and time again (most recently with the support for EDID hardcoded in the BIOS ROM) that new code didn't check for rdev->bios being non-NULL before triggering dereferences of it. This would result in an oops/panic on setups with no BIOS ROM. Hopefully this central test will be more robust. Signed-off-by: Michel Dänzer Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_combios.c | 40 ++++----------------------------- 1 file changed, 4 insertions(+), 36 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index 26fb42450cb2..9989d22a4d8f 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -150,6 +150,9 @@ static uint16_t combios_get_table_offset(struct drm_device *dev, int rev; uint16_t offset = 0, check_offset; + if (!rdev->bios) + return 0; + switch (table) { /* absolute offset tables */ case COMBIOS_ASIC_INIT_1_TABLE: @@ -621,9 +624,6 @@ bool radeon_combios_get_clock_info(struct drm_device *dev) int8_t rev; uint16_t sclk, mclk; - if (rdev->bios == NULL) - return false; - pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); if (pll_info) { rev = RBIOS8(pll_info); @@ -748,9 +748,6 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct if (!p_dac) return NULL; - if (rdev->bios == NULL) - goto out; - /* check CRT table */ dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); if (dac_info) { @@ -767,7 +764,6 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct found = 1; } -out: if (!found) /* fallback to defaults */ radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); @@ -781,9 +777,6 @@ radeon_combios_get_tv_info(struct radeon_device *rdev) uint16_t tv_info; enum radeon_tv_std tv_std = TV_STD_NTSC; - if (rdev->bios == NULL) - return tv_std; - tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); if (tv_info) { if (RBIOS8(tv_info + 6) == 'T') { @@ -887,9 +880,6 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct if (!tv_dac) return NULL; - if (rdev->bios == NULL) - goto out; - /* first check TV table */ dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); if (dac_info) { @@ -951,7 +941,6 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct } } -out: if (!found) /* fallback to defaults */ radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); @@ -1039,11 +1028,6 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder int tmp, i; struct radeon_encoder_lvds *lvds = NULL; - if (rdev->bios == NULL) { - lvds = radeon_legacy_get_lvds_info_from_regs(rdev); - goto out; - } - lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); if (lcd_info) { @@ -1144,7 +1128,7 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder DRM_INFO("No panel info found in BIOS\n"); lvds = radeon_legacy_get_lvds_info_from_regs(rdev); } -out: + if (lvds) encoder->native_mode = lvds->native_mode; return lvds; @@ -1196,9 +1180,6 @@ bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, int i, n; uint8_t ver; - if (rdev->bios == NULL) - return false; - tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); if (tmds_info) { @@ -1278,9 +1259,6 @@ bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder enum radeon_combios_ddc gpio; struct radeon_i2c_bus_rec i2c_bus; - if (rdev->bios == NULL) - return false; - tmds->i2c_bus = NULL; if (rdev->flags & RADEON_IS_IGP) { offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); @@ -2006,9 +1984,6 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) struct radeon_i2c_bus_rec ddc_i2c; struct radeon_hpd hpd; - if (rdev->bios == NULL) - return false; - conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); if (conn_info) { for (i = 0; i < 4; i++) { @@ -2385,10 +2360,6 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) rdev->pm.default_power_state = NULL; rdev->pm.current_power_state = NULL; - /* XXX mac/sparc cards */ - if (rdev->bios == NULL) - goto default_mode; - if (rdev->flags & RADEON_IS_MOBILITY) { offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); if (offset) { @@ -2545,9 +2516,6 @@ bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) uint32_t reg, val, and_mask, or_mask; struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; - if (rdev->bios == NULL) - return false; - if (!tmds) return false; -- cgit v1.2.3 From e34398952e056bbd99f9099fae77be26e5c6aa78 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 11 Feb 2010 15:38:23 +1000 Subject: drm/radeon/kms: check for valid PCI bios and not OF rom stops us trying to treat a OF rom as a PCI rom. Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_bios.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c index 906921740c60..26856ed8d972 100644 --- a/drivers/gpu/drm/radeon/radeon_bios.c +++ b/drivers/gpu/drm/radeon/radeon_bios.c @@ -411,6 +411,12 @@ bool radeon_get_bios(struct radeon_device *rdev) goto free_bios; } + tmp = RBIOS16(0x18); + if (RBIOS8(tmp + 0x14) != 0x0) { + DRM_INFO("Not an x86 BIOS ROM, not using.\n"); + goto free_bios; + } + rdev->bios_header_start = RBIOS16(0x48); if (!rdev->bios_header_start) { goto free_bios; -- cgit v1.2.3 From 82568565683b4991964a5fc89a9ca0c7122818e8 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 5 Feb 2010 16:00:07 +1000 Subject: drm/radeon/kms: set gart pages to invalid on unbind and point to dummy page this uses a new entrypoint to invalidate gart entries instead of using 0. Changed to rather than pointing to 0 address point empty entry to dummy page. This might help to avoid hard lockup if for some wrong reasons GPU try to access unmapped GART entry. I'm not 100% sure this is going to work, we probably need to allocate a dummy page and point all the GTT entries at it similiar to what AGP does. but we can test this first I suppose. Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/evergreen.c | 1 + drivers/gpu/drm/radeon/r100.c | 1 + drivers/gpu/drm/radeon/r300.c | 1 + drivers/gpu/drm/radeon/r600.c | 1 + drivers/gpu/drm/radeon/radeon.h | 2 +- drivers/gpu/drm/radeon/radeon_device.c | 2 ++ drivers/gpu/drm/radeon/radeon_gart.c | 32 ++++++++++++++++++++++++++++++-- drivers/gpu/drm/radeon/rs400.c | 1 + drivers/gpu/drm/radeon/rs600.c | 1 + drivers/gpu/drm/radeon/rv770.c | 1 + 10 files changed, 40 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index c2f9752e4ee0..3368920df5f4 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -93,6 +93,7 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev) r = radeon_gart_table_vram_pin(rdev); if (r) return r; + radeon_gart_restore(rdev); /* Setup L2 cache */ WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 346ae3d7e0d4..bc7d9e9211c8 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -197,6 +197,7 @@ int r100_pci_gart_enable(struct radeon_device *rdev) { uint32_t tmp; + radeon_gart_restore(rdev); /* discard memory request outside of configured range */ tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; WREG32(RADEON_AIC_CNTL, tmp); diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 5897bd00591e..654aca1cdf05 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -117,6 +117,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev) r = radeon_gart_table_vram_pin(rdev); if (r) return r; + radeon_gart_restore(rdev); /* discard memory request outside of configured range */ tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index c9723daee357..4facbab20456 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -416,6 +416,7 @@ int r600_pcie_gart_enable(struct radeon_device *rdev) r = radeon_gart_table_vram_pin(rdev); if (r) return r; + radeon_gart_restore(rdev); /* Setup L2 cache */ WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 9eeca6f07222..993cdf20d8e6 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1145,6 +1145,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) /* AGP */ extern void radeon_agp_disable(struct radeon_device *rdev); extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); +extern void radeon_gart_restore(struct radeon_device *rdev); extern int radeon_modeset_init(struct radeon_device *rdev); extern void radeon_modeset_fini(struct radeon_device *rdev); extern bool radeon_card_posted(struct radeon_device *rdev); @@ -1269,7 +1270,6 @@ extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); extern int r600_cp_resume(struct radeon_device *rdev); extern void r600_cp_fini(struct radeon_device *rdev); extern int r600_count_pipe_bits(uint32_t val); -extern int r600_gart_clear_page(struct radeon_device *rdev, int i); extern int r600_mc_wait_for_idle(struct radeon_device *rdev); extern int r600_pcie_gart_init(struct radeon_device *rdev); extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index c224c1d944ef..fb55faf8e284 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -238,6 +238,8 @@ bool radeon_boot_test_post_card(struct radeon_device *rdev) int radeon_dummy_page_init(struct radeon_device *rdev) { + if (rdev->dummy_page.page) + return 0; rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); if (rdev->dummy_page.page == NULL) return -ENOMEM; diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c index e73d56e83fa6..1770d3c07fd0 100644 --- a/drivers/gpu/drm/radeon/radeon_gart.c +++ b/drivers/gpu/drm/radeon/radeon_gart.c @@ -139,6 +139,7 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, unsigned t; unsigned p; int i, j; + u64 page_base; if (!rdev->gart.ready) { WARN(1, "trying to unbind memory to unitialized GART !\n"); @@ -151,9 +152,11 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p], PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); rdev->gart.pages[p] = NULL; - rdev->gart.pages_addr[p] = 0; + rdev->gart.pages_addr[p] = rdev->dummy_page.addr; + page_base = rdev->gart.pages_addr[p]; for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { - radeon_gart_set_page(rdev, t, 0); + radeon_gart_set_page(rdev, t, page_base); + page_base += RADEON_GPU_PAGE_SIZE; } } } @@ -199,8 +202,26 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, return 0; } +void radeon_gart_restore(struct radeon_device *rdev) +{ + int i, j, t; + u64 page_base; + + for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) { + page_base = rdev->gart.pages_addr[i]; + for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { + radeon_gart_set_page(rdev, t, page_base); + page_base += RADEON_GPU_PAGE_SIZE; + } + } + mb(); + radeon_gart_tlb_flush(rdev); +} + int radeon_gart_init(struct radeon_device *rdev) { + int r, i; + if (rdev->gart.pages) { return 0; } @@ -209,6 +230,9 @@ int radeon_gart_init(struct radeon_device *rdev) DRM_ERROR("Page size is smaller than GPU page size!\n"); return -EINVAL; } + r = radeon_dummy_page_init(rdev); + if (r) + return r; /* Compute table size */ rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE; rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE; @@ -227,6 +251,10 @@ int radeon_gart_init(struct radeon_device *rdev) radeon_gart_fini(rdev); return -ENOMEM; } + /* set GART entry to point to the dummy page by default */ + for (i = 0; i < rdev->gart.num_cpu_pages; i++) { + rdev->gart.pages_addr[i] = rdev->dummy_page.addr; + } return 0; } diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c index 287fcebfb4e6..1e4582e27c14 100644 --- a/drivers/gpu/drm/radeon/rs400.c +++ b/drivers/gpu/drm/radeon/rs400.c @@ -113,6 +113,7 @@ int rs400_gart_enable(struct radeon_device *rdev) uint32_t size_reg; uint32_t tmp; + radeon_gart_restore(rdev); tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index 979b00034de9..28c8690c7a35 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c @@ -213,6 +213,7 @@ int rs600_gart_enable(struct radeon_device *rdev) r = radeon_gart_table_vram_pin(rdev); if (r) return r; + radeon_gart_restore(rdev); /* Enable bus master */ tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; WREG32(R_00004C_BUS_CNTL, tmp); diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 3ecd138815d8..6f1f4abbe88c 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -56,6 +56,7 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev) r = radeon_gart_table_vram_pin(rdev); if (r) return r; + radeon_gart_restore(rdev); /* Setup L2 cache */ WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | -- cgit v1.2.3 From 7cb72ef4d39978e6e07415a2d552b06d567c3079 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Thu, 11 Feb 2010 12:44:32 +0100 Subject: drm/radeon/kms: fix r600/r700 cs checker to avoid double kfree radeon_cs kfree the tracker structure but for r6xx/r7xx we want to kfree it inside the parse function because we share it with the UMS code path. Set tracker to NULL after freeing it will avoid double free. Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600_cs.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index ac67d6488a95..00e69c585fbf 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -846,9 +846,9 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx "0x%04X\n", reg); return -EINVAL; } + tmp = (reg - CB_COLOR0_BASE) / 4; track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); - tmp = (reg - CB_COLOR0_BASE) / 4; track->cb_color_base_last[tmp] = ib[idx]; track->cb_color_bo[tmp] = reloc->robj; break; @@ -1324,6 +1324,8 @@ int r600_cs_parse(struct radeon_cs_parser *p) do { r = r600_cs_packet_parse(p, &pkt, p->idx); if (r) { + kfree(p->track); + p->track = NULL; return r; } p->idx += pkt.count + 2; @@ -1339,10 +1341,12 @@ int r600_cs_parse(struct radeon_cs_parser *p) default: DRM_ERROR("Unknown packet type %d !\n", pkt.type); kfree(p->track); + p->track = NULL; return -EINVAL; } if (r) { kfree(p->track); + p->track = NULL; return r; } } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); @@ -1353,6 +1357,7 @@ int r600_cs_parse(struct radeon_cs_parser *p) } #endif kfree(p->track); + p->track = NULL; return 0; } -- cgit v1.2.3 From 6b79b264ce04e2acd24330140e147801cdbaa39f Mon Sep 17 00:00:00 2001 From: Jiri Kosina Date: Fri, 12 Feb 2010 10:31:37 +0100 Subject: No need to patch AMD-provided drivers/gpu/drm/radeon/atombios.h This is partial revert of commit 9404c9c392d5 ("Fix misspelling of "should" and "shouldn't" in comments"). According to Dave Airlie: "Can we drop any cleanups to atombios.h? This file comes from AMD and we normally drop it into place, so they just get overwritten next time." Reported-by: Dave Airlie Signed-off-by: Jiri Kosina --- drivers/gpu/drm/radeon/atombios.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h index 2a88029f6a1e..91ad0d1c1b17 100644 --- a/drivers/gpu/drm/radeon/atombios.h +++ b/drivers/gpu/drm/radeon/atombios.h @@ -2275,7 +2275,7 @@ typedef struct _ATOM_LCD_RTS_RECORD { UCHAR ucRTSValue; } ATOM_LCD_RTS_RECORD; -/* !! If the record below exits, it should always be the first record for easy use in command table!!! */ +/* !! If the record below exits, it shoud always be the first record for easy use in command table!!! */ typedef struct _ATOM_LCD_MODE_CONTROL_CAP { UCHAR ucRecordType; USHORT usLCDCap; -- cgit v1.2.3 From 2e98f10a7a87ebae4dcc3949028a32008b46ceef Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 15 Feb 2010 15:54:45 +1000 Subject: drm/radeon/kms: flush HDP cache on GART table updates. Suggested by Alex Deucher @ AMD Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 4facbab20456..6434d6af7d52 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -370,6 +370,9 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) unsigned i; u32 tmp; + /* flush hdp cache so updates hit vram */ + WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); + WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); -- cgit v1.2.3 From dfff0615d28bdb3e8d213e5537dd069265912667 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 12 Feb 2010 21:58:11 +0100 Subject: tree-wide: fix typos "ass?o[sc]iac?te" -> "associate" in comments MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Jiri Kosina --- drivers/usb/musb/davinci.c | 2 +- drivers/zorro/zorro.ids | 2 +- include/net/irda/irttp.h | 2 +- kernel/irq/chip.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c index 66913811af5e..a883f9dd3f8a 100644 --- a/drivers/usb/musb/davinci.c +++ b/drivers/usb/musb/davinci.c @@ -274,7 +274,7 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci) /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through * the Mentor registers (except for setup), use the TI ones and EOI. * - * Docs describe irq "vector" registers asociated with the CPPI and + * Docs describe irq "vector" registers associated with the CPPI and * USB EOI registers. These hold a bitmask corresponding to the * current IRQ, not an irq handler address. Would using those bits * resolve some of the races observed in this dispatch code?? diff --git a/drivers/zorro/zorro.ids b/drivers/zorro/zorro.ids index 0c0f99e2dd62..de24e3decedd 100644 --- a/drivers/zorro/zorro.ids +++ b/drivers/zorro/zorro.ids @@ -108,7 +108,7 @@ 0c00 500XP/SupraDrive WordSync [SCSI Host Adapter] 0d00 SupraDrive WordSync II [SCSI Host Adapter] 1000 2400zi+ [Modem] -0422 Computer Systems Assosiates +0422 Computer Systems Associates 1100 Magnum 40 [Accelerator and SCSI Host Adapter] 1500 12 Gauge [SCSI Host Adapter] 0439 Marc Michael Groth diff --git a/include/net/irda/irttp.h b/include/net/irda/irttp.h index 0788c23d2828..11aee7a2972a 100644 --- a/include/net/irda/irttp.h +++ b/include/net/irda/irttp.h @@ -97,7 +97,7 @@ #define TTP_MAX_SDU_SIZE 0x01 /* - * This structure contains all data assosiated with one instance of a TTP + * This structure contains all data associated with one instance of a TTP * connection. */ struct tsap_cb { diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index ecc3fa28f666..ec8a96382461 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -520,7 +520,7 @@ out: * signal. The occurence is latched into the irq controller hardware * and must be acked in order to be reenabled. After the ack another * interrupt can happen on the same source even before the first one - * is handled by the assosiacted event handler. If this happens it + * is handled by the associated event handler. If this happens it * might be necessary to disable (mask) the interrupt depending on the * controller hardware. This requires to reenable the interrupt inside * of the loop which handles the interrupts which have arrived while -- cgit v1.2.3 From e821767bebdae6a46f6d897a4385f6218bee7f27 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Mon, 15 Feb 2010 21:36:13 +0100 Subject: drm/radeon/kms: fix indirect buffer management V2 There is 3 different distinct states for an indirect buffer (IB) : 1- free with no fence 2- free with a fence 3- non free (fence doesn't matter) Previous code mixed case 2 & 3 in a single one leading to possible catastrophique failure. This patch rework the handling and properly separate each case. So when you get ib we set the ib as non free and fence status doesn't matter. Fence become active (ie has a meaning for the ib code) once the ib is scheduled or free. This patch also get rid of the alloc bitmap as it was overkill, we know go through IB pool list like in a ring buffer as the oldest IB is the first one the will be free. Fix : https://bugs.freedesktop.org/show_bug.cgi?id=26438 and likely other bugs. V2 remove the scheduled list, it's useless now, fix free ib scanning Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600_blit_kms.c | 3 - drivers/gpu/drm/radeon/radeon.h | 9 +-- drivers/gpu/drm/radeon/radeon_ring.c | 105 +++++++++++++-------------------- 3 files changed, 45 insertions(+), 72 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c index 2d7d16e14f9e..ec49dada887d 100644 --- a/drivers/gpu/drm/radeon/r600_blit_kms.c +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c @@ -541,9 +541,6 @@ int r600_vb_ib_get(struct radeon_device *rdev) void r600_vb_ib_put(struct radeon_device *rdev) { radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence); - mutex_lock(&rdev->ib_pool.mutex); - list_add_tail(&rdev->r600_blit.vb_ib->list, &rdev->ib_pool.scheduled_ibs); - mutex_unlock(&rdev->ib_pool.mutex); radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); } diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 993cdf20d8e6..9f35beed13e8 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -97,6 +97,7 @@ extern int radeon_audio; * symbol; */ #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ +/* RADEON_IB_POOL_SIZE must be a power of 2 */ #define RADEON_IB_POOL_SIZE 16 #define RADEON_DEBUGFS_MAX_NUM_FILES 32 #define RADEONFB_CONN_LIMIT 4 @@ -371,11 +372,12 @@ void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); */ struct radeon_ib { struct list_head list; - unsigned long idx; + unsigned idx; uint64_t gpu_addr; struct radeon_fence *fence; - uint32_t *ptr; + uint32_t *ptr; uint32_t length_dw; + bool free; }; /* @@ -385,11 +387,10 @@ struct radeon_ib { struct radeon_ib_pool { struct mutex mutex; struct radeon_bo *robj; - struct list_head scheduled_ibs; struct list_head bogus_ib; struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; bool ready; - DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); + unsigned head_id; }; struct radeon_cp { diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index e3bee59ef6c3..38fa14429320 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c @@ -71,68 +71,55 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) { struct radeon_fence *fence; struct radeon_ib *nib; - unsigned long i; - int r = 0; + int r = 0, i, c; *ib = NULL; r = radeon_fence_create(rdev, &fence); if (r) { - DRM_ERROR("failed to create fence for new IB\n"); + dev_err(rdev->dev, "failed to create fence for new IB\n"); return r; } mutex_lock(&rdev->ib_pool.mutex); - i = find_first_zero_bit(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); - if (i < RADEON_IB_POOL_SIZE) { - set_bit(i, rdev->ib_pool.alloc_bm); - rdev->ib_pool.ibs[i].length_dw = 0; - *ib = &rdev->ib_pool.ibs[i]; - mutex_unlock(&rdev->ib_pool.mutex); - goto out; + for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) { + i &= (RADEON_IB_POOL_SIZE - 1); + if (rdev->ib_pool.ibs[i].free) { + nib = &rdev->ib_pool.ibs[i]; + break; + } } - if (list_empty(&rdev->ib_pool.scheduled_ibs)) { - /* we go do nothings here */ + if (nib == NULL) { + /* This should never happen, it means we allocated all + * IB and haven't scheduled one yet, return EBUSY to + * userspace hoping that on ioctl recall we get better + * luck + */ + dev_err(rdev->dev, "no free indirect buffer !\n"); mutex_unlock(&rdev->ib_pool.mutex); - DRM_ERROR("all IB allocated none scheduled.\n"); - r = -EINVAL; - goto out; + radeon_fence_unref(&fence); + return -EBUSY; } - /* get the first ib on the scheduled list */ - nib = list_entry(rdev->ib_pool.scheduled_ibs.next, - struct radeon_ib, list); - if (nib->fence == NULL) { - /* we go do nothings here */ + rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1); + nib->free = false; + if (nib->fence) { mutex_unlock(&rdev->ib_pool.mutex); - DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx); - r = -EINVAL; - goto out; - } - mutex_unlock(&rdev->ib_pool.mutex); - - r = radeon_fence_wait(nib->fence, false); - if (r) { - DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx, - (unsigned long)nib->gpu_addr, nib->length_dw); - DRM_ERROR("radeon: GPU lockup detected, fail to get a IB\n"); - goto out; + r = radeon_fence_wait(nib->fence, false); + if (r) { + dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n", + nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw); + mutex_lock(&rdev->ib_pool.mutex); + nib->free = true; + mutex_unlock(&rdev->ib_pool.mutex); + radeon_fence_unref(&fence); + return r; + } + mutex_lock(&rdev->ib_pool.mutex); } radeon_fence_unref(&nib->fence); - + nib->fence = fence; nib->length_dw = 0; - - /* scheduled list is accessed here */ - mutex_lock(&rdev->ib_pool.mutex); - list_del(&nib->list); - INIT_LIST_HEAD(&nib->list); mutex_unlock(&rdev->ib_pool.mutex); - *ib = nib; -out: - if (r) { - radeon_fence_unref(&fence); - } else { - (*ib)->fence = fence; - } - return r; + return 0; } void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) @@ -144,18 +131,7 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) return; } mutex_lock(&rdev->ib_pool.mutex); - if (!list_empty(&tmp->list) && !radeon_fence_signaled(tmp->fence)) { - /* IB is scheduled & not signaled don't do anythings */ - mutex_unlock(&rdev->ib_pool.mutex); - return; - } - list_del(&tmp->list); - INIT_LIST_HEAD(&tmp->list); - if (tmp->fence) - radeon_fence_unref(&tmp->fence); - - tmp->length_dw = 0; - clear_bit(tmp->idx, rdev->ib_pool.alloc_bm); + tmp->free = true; mutex_unlock(&rdev->ib_pool.mutex); } @@ -165,7 +141,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) if (!ib->length_dw || !rdev->cp.ready) { /* TODO: Nothings in the ib we should report. */ - DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx); + DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx); return -EINVAL; } @@ -178,7 +154,8 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) radeon_ring_ib_execute(rdev, ib); radeon_fence_emit(rdev, ib->fence); mutex_lock(&rdev->ib_pool.mutex); - list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs); + /* once scheduled IB is considered free and protected by the fence */ + ib->free = true; mutex_unlock(&rdev->ib_pool.mutex); radeon_ring_unlock_commit(rdev); return 0; @@ -195,7 +172,6 @@ int radeon_ib_pool_init(struct radeon_device *rdev) return 0; INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib); /* Allocate 1M object buffer */ - INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs); r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024, true, RADEON_GEM_DOMAIN_GTT, &rdev->ib_pool.robj); @@ -226,9 +202,9 @@ int radeon_ib_pool_init(struct radeon_device *rdev) rdev->ib_pool.ibs[i].ptr = ptr + offset; rdev->ib_pool.ibs[i].idx = i; rdev->ib_pool.ibs[i].length_dw = 0; - INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].list); + rdev->ib_pool.ibs[i].free = true; } - bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); + rdev->ib_pool.head_id = 0; rdev->ib_pool.ready = true; DRM_INFO("radeon: ib pool ready.\n"); if (radeon_debugfs_ib_init(rdev)) { @@ -246,7 +222,6 @@ void radeon_ib_pool_fini(struct radeon_device *rdev) } mutex_lock(&rdev->ib_pool.mutex); radeon_ib_bogus_cleanup(rdev); - bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); if (rdev->ib_pool.robj) { r = radeon_bo_reserve(rdev->ib_pool.robj, false); if (likely(r == 0)) { @@ -395,7 +370,7 @@ static int radeon_debugfs_ib_info(struct seq_file *m, void *data) if (ib == NULL) { return 0; } - seq_printf(m, "IB %04lu\n", ib->idx); + seq_printf(m, "IB %04u\n", ib->idx); seq_printf(m, "IB fence %p\n", ib->fence); seq_printf(m, "IB size %05u dwords\n", ib->length_dw); for (i = 0; i < ib->length_dw; i++) { -- cgit v1.2.3 From 6cb8e1f71c407930f0f07feceeea1da73881038b Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Mon, 15 Feb 2010 21:36:33 +0100 Subject: drm/radeon/kms: fix bo's fence association Previous code did associate fence to bo before the fence was emited and it also didn't lock protected access to ttm sync_obj member. Both of this flaw leads to possible race between different code path. This patch fix this by associating fence only once the fence is emitted and properly lock protect access to sync_obj member of ttm. Fix: https://bugs.freedesktop.org/show_bug.cgi?id=26438 and likely similar others bugs Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_cs.c | 10 ++++------ drivers/gpu/drm/radeon/radeon_object.c | 36 ++++++++++++++-------------------- drivers/gpu/drm/radeon/radeon_object.h | 4 ++-- 3 files changed, 21 insertions(+), 29 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index 1190148cf5e6..e9d085021c1f 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -86,7 +86,7 @@ int radeon_cs_parser_relocs(struct radeon_cs_parser *p) &p->validated); } } - return radeon_bo_list_validate(&p->validated, p->ib->fence); + return radeon_bo_list_validate(&p->validated); } int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) @@ -189,12 +189,10 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) { unsigned i; - if (error && parser->ib) { - radeon_bo_list_unvalidate(&parser->validated, - parser->ib->fence); - } else { - radeon_bo_list_unreserve(&parser->validated); + if (!error && parser->ib) { + radeon_bo_list_fence(&parser->validated, parser->ib->fence); } + radeon_bo_list_unreserve(&parser->validated); for (i = 0; i < parser->nrelocs; i++) { if (parser->relocs[i].gobj) { mutex_lock(&parser->rdev->ddev->struct_mutex); diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index d72a71bff218..f1da370928eb 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -306,11 +306,10 @@ void radeon_bo_list_unreserve(struct list_head *head) } } -int radeon_bo_list_validate(struct list_head *head, void *fence) +int radeon_bo_list_validate(struct list_head *head) { struct radeon_bo_list *lobj; struct radeon_bo *bo; - struct radeon_fence *old_fence = NULL; int r; r = radeon_bo_list_reserve(head); @@ -334,32 +333,27 @@ int radeon_bo_list_validate(struct list_head *head, void *fence) } lobj->gpu_offset = radeon_bo_gpu_offset(bo); lobj->tiling_flags = bo->tiling_flags; - if (fence) { - old_fence = (struct radeon_fence *)bo->tbo.sync_obj; - bo->tbo.sync_obj = radeon_fence_ref(fence); - bo->tbo.sync_obj_arg = NULL; - } - if (old_fence) { - radeon_fence_unref(&old_fence); - } } return 0; } -void radeon_bo_list_unvalidate(struct list_head *head, void *fence) +void radeon_bo_list_fence(struct list_head *head, void *fence) { struct radeon_bo_list *lobj; - struct radeon_fence *old_fence; - - if (fence) - list_for_each_entry(lobj, head, list) { - old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj); - if (old_fence == fence) { - lobj->bo->tbo.sync_obj = NULL; - radeon_fence_unref(&old_fence); - } + struct radeon_bo *bo; + struct radeon_fence *old_fence = NULL; + + list_for_each_entry(lobj, head, list) { + bo = lobj->bo; + spin_lock(&bo->tbo.lock); + old_fence = (struct radeon_fence *)bo->tbo.sync_obj; + bo->tbo.sync_obj = radeon_fence_ref(fence); + bo->tbo.sync_obj_arg = NULL; + spin_unlock(&bo->tbo.lock); + if (old_fence) { + radeon_fence_unref(&old_fence); } - radeon_bo_list_unreserve(head); + } } int radeon_bo_fbdev_mmap(struct radeon_bo *bo, diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h index a02f18011ad1..7ab43de1e244 100644 --- a/drivers/gpu/drm/radeon/radeon_object.h +++ b/drivers/gpu/drm/radeon/radeon_object.h @@ -156,8 +156,8 @@ extern void radeon_bo_list_add_object(struct radeon_bo_list *lobj, struct list_head *head); extern int radeon_bo_list_reserve(struct list_head *head); extern void radeon_bo_list_unreserve(struct list_head *head); -extern int radeon_bo_list_validate(struct list_head *head, void *fence); -extern void radeon_bo_list_unvalidate(struct list_head *head, void *fence); +extern int radeon_bo_list_validate(struct list_head *head); +extern void radeon_bo_list_fence(struct list_head *head, void *fence); extern int radeon_bo_fbdev_mmap(struct radeon_bo *bo, struct vm_area_struct *vma); extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo, -- cgit v1.2.3 From 0e026445fb36852d3102cb8bb24868765fe5816a Mon Sep 17 00:00:00 2001 From: Len Brown Date: Tue, 16 Feb 2010 03:01:42 -0500 Subject: ACPI: delete unused acpi_evaluate_string() Roel found a logic issue in the #if 0 acpi_evaluate_string(): - || (element->type != ACPI_TYPE_BUFFER) + && (element->type != ACPI_TYPE_BUFFER) delete the dead code. pointed-out-by: Roel Kluin Signed-off-by: Len Brown --- drivers/acpi/utils.c | 45 --------------------------------------------- 1 file changed, 45 deletions(-) (limited to 'drivers') diff --git a/drivers/acpi/utils.c b/drivers/acpi/utils.c index 811fec10462b..592dffb43694 100644 --- a/drivers/acpi/utils.c +++ b/drivers/acpi/utils.c @@ -289,51 +289,6 @@ acpi_evaluate_integer(acpi_handle handle, EXPORT_SYMBOL(acpi_evaluate_integer); -#if 0 -acpi_status -acpi_evaluate_string(acpi_handle handle, - acpi_string pathname, - acpi_object_list * arguments, acpi_string * data) -{ - acpi_status status = AE_OK; - acpi_object *element = NULL; - acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; - - - if (!data) - return AE_BAD_PARAMETER; - - status = acpi_evaluate_object(handle, pathname, arguments, &buffer); - if (ACPI_FAILURE(status)) { - acpi_util_eval_error(handle, pathname, status); - return status; - } - - element = (acpi_object *) buffer.pointer; - - if ((element->type != ACPI_TYPE_STRING) - || (element->type != ACPI_TYPE_BUFFER) - || !element->string.length) { - acpi_util_eval_error(handle, pathname, AE_BAD_DATA); - return AE_BAD_DATA; - } - - *data = kzalloc(element->string.length + 1, GFP_KERNEL); - if (!data) { - printk(KERN_ERR PREFIX "Memory allocation\n"); - return -ENOMEM; - } - - memcpy(*data, element->string.pointer, element->string.length); - - ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Return value [%s]\n", *data)); - - kfree(buffer.pointer); - - return AE_OK; -} -#endif - acpi_status acpi_evaluate_reference(acpi_handle handle, acpi_string pathname, -- cgit v1.2.3 From ded180e7ebfc324b36a94931f99d0705dcd8da29 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Tue, 2 Feb 2010 14:37:55 -0800 Subject: ACPI: remove superfluous NULL pointer check from acpi_processor_get_throttling_info() Dan's list contains: drivers/acpi/processor_throttling.c +1139 acpi_processor_get_throttling_info(11) warning: variable derefenced before check 'pr' acpi_processor_get_throttling_info() is never called with pr == NULL. [ bart: the potential NULL pointer dereference was finally fixed in (much later than mine) commit 5cfa245 but my patch is still valid ] Reported-by: Dan Carpenter Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Len Brown --- drivers/acpi/processor_throttling.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers') diff --git a/drivers/acpi/processor_throttling.c b/drivers/acpi/processor_throttling.c index 1c5d7a8b2fdf..649b2b9b4759 100644 --- a/drivers/acpi/processor_throttling.c +++ b/drivers/acpi/processor_throttling.c @@ -1133,9 +1133,6 @@ int acpi_processor_get_throttling_info(struct acpi_processor *pr) int result = 0; struct acpi_processor_throttling *pthrottling; - if (!pr) - return -EINVAL; - ACPI_DEBUG_PRINT((ACPI_DB_INFO, "pblk_address[0x%08x] duty_offset[%d] duty_width[%d]\n", pr->throttling.address, -- cgit v1.2.3 From 38bcb37a6f63fcdfcc0dd0af3ec5c03a4b7be48e Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Tue, 2 Feb 2010 14:37:56 -0800 Subject: ACPICA: fix acpi_ex_release_mutex() comment trivial, leftover from my NULL pointer dereference patch which got 'superseded' by commit fbc3be2 Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Len Brown --- drivers/acpi/acpica/exmutex.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/acpi/acpica/exmutex.c b/drivers/acpi/acpica/exmutex.c index 3c456bd575d0..c4a47dda17e0 100644 --- a/drivers/acpi/acpica/exmutex.c +++ b/drivers/acpi/acpica/exmutex.c @@ -375,8 +375,7 @@ acpi_ex_release_mutex(union acpi_operand_object *obj_desc, return_ACPI_STATUS(AE_AML_MUTEX_NOT_ACQUIRED); } - /* Must have a valid thread ID */ - + /* Must have a valid thread. */ if (!walk_state->thread) { ACPI_ERROR((AE_INFO, "Cannot release Mutex [%4.4s], null thread info", -- cgit v1.2.3 From 94d32f99c6aba8b702a9cf78cb328aeb7882b1e5 Mon Sep 17 00:00:00 2001 From: Andy Green Date: Mon, 1 Feb 2010 13:28:54 +0100 Subject: imx-serial-excessive-status-clearing-on-break.patch cc: Sasha Hauer We noticed that we were only able to communicate once with a GSM module per session, if we powered down the module then the serial driver was broken until reset, no traffic or /proc/interrupts activity could be seen any more. Volker noticed it was provoked by a long "break" seen on the wire when the RX was not driven during powerdown, we discovered we could kill the serial driver just by forcing RX low extenally for a little while. I saw that the processing for BREAK in the driver gets too excited and clears down all set bits in USR2, including that a character is pending. This stops all further characters getting processed. The attached one-liner makes the serial driver immortal against BREAK. Signed-off-by: Andy Green Signed-off-by: Volker Ernst Signed-off-by: Sascha Hauer --- drivers/serial/imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c index 18130f11238e..c5b546a98520 100644 --- a/drivers/serial/imx.c +++ b/drivers/serial/imx.c @@ -440,7 +440,7 @@ static irqreturn_t imx_rxint(int irq, void *dev_id) temp = readl(sport->port.membase + USR2); if (temp & USR2_BRCD) { - writel(temp | USR2_BRCD, sport->port.membase + USR2); + writel(USR2_BRCD, sport->port.membase + USR2); if (uart_handle_break(&sport->port)) continue; } -- cgit v1.2.3 From 97f70c23a1fa1bffe79187563dc5c6f2c72420a2 Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Fri, 12 Feb 2010 23:56:46 +0200 Subject: power_supply: bq27x00: remove double endian swap The bq27x00 registers are little endian, so just read them as such and don't do double endian swap on LE machines. This also gets rid of strange looking shift that was done after reading 8bit register because endian swap in bq27x00_read() was messing it up. Signed-off-by: Grazvydas Ignotas Acked-by: Rodolfo Giometti Signed-off-by: Anton Vorontsov --- drivers/power/bq27x00_battery.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/power/bq27x00_battery.c b/drivers/power/bq27x00_battery.c index 62bb98124e26..537915cc491e 100644 --- a/drivers/power/bq27x00_battery.c +++ b/drivers/power/bq27x00_battery.c @@ -74,12 +74,7 @@ static enum power_supply_property bq27x00_battery_props[] = { static int bq27x00_read(u8 reg, int *rt_value, int b_single, struct bq27x00_device_info *di) { - int ret; - - ret = di->bus->read(reg, rt_value, b_single, di); - *rt_value = be16_to_cpu(*rt_value); - - return ret; + return di->bus->read(reg, rt_value, b_single, di); } /* @@ -161,7 +156,7 @@ static int bq27x00_battery_rsoc(struct bq27x00_device_info *di) return ret; } - return rsoc >> 8; + return rsoc; } #define to_bq27x00_device_info(x) container_of((x), \ @@ -238,7 +233,7 @@ static int bq27200_read(u8 reg, int *rt_value, int b_single, err = i2c_transfer(client->adapter, msg, 1); if (err >= 0) { if (!b_single) - *rt_value = get_unaligned_be16(data); + *rt_value = get_unaligned_le16(data); else *rt_value = data[0]; -- cgit v1.2.3 From ba96f8717e77f1ef68c160f6e9a454b3ce2c045b Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Fri, 12 Feb 2010 23:57:02 +0200 Subject: power_supply: bq27x00: remove unused struct fields These are probably leftover from old TI code. Signed-off-by: Grazvydas Ignotas Acked-by: Rodolfo Giometti Signed-off-by: Anton Vorontsov --- drivers/power/bq27x00_battery.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/power/bq27x00_battery.c b/drivers/power/bq27x00_battery.c index 537915cc491e..3ae3e08a1f4c 100644 --- a/drivers/power/bq27x00_battery.c +++ b/drivers/power/bq27x00_battery.c @@ -49,10 +49,6 @@ struct bq27x00_access_methods { struct bq27x00_device_info { struct device *dev; int id; - int voltage_uV; - int current_uA; - int temp_C; - int charge_rsoc; struct bq27x00_access_methods *bus; struct power_supply bat; -- cgit v1.2.3 From b4de3608156311b615da4bcc4c095913abc44825 Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Fri, 12 Feb 2010 23:57:13 +0200 Subject: power_supply: bq27x00: fix temperature conversion The power supply class requires tenths of degree Celsius. Signed-off-by: Grazvydas Ignotas Acked-by: Rodolfo Giometti Signed-off-by: Anton Vorontsov --- drivers/power/bq27x00_battery.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/power/bq27x00_battery.c b/drivers/power/bq27x00_battery.c index 3ae3e08a1f4c..3da9e0aa705a 100644 --- a/drivers/power/bq27x00_battery.c +++ b/drivers/power/bq27x00_battery.c @@ -74,7 +74,7 @@ static int bq27x00_read(u8 reg, int *rt_value, int b_single, } /* - * Return the battery temperature in Celsius degrees + * Return the battery temperature in tenths of degree Celsius * Or < 0 if something fails. */ static int bq27x00_battery_temperature(struct bq27x00_device_info *di) @@ -88,7 +88,7 @@ static int bq27x00_battery_temperature(struct bq27x00_device_info *di) return ret; } - return (temp >> 2) - 273; + return ((temp >> 2) - 273) * 10; } /* -- cgit v1.2.3 From e20908d95e89d04b9537aefecc0734d2e4f7faed Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Fri, 12 Feb 2010 23:57:23 +0200 Subject: power_supply: bq27x00: add BQ27500 support BQ27500 is newer fuel gauge chip from TI with slightly changed register layout and some different register semantics. Add new i2c ID for it and handle differences where needed. Also rename bq27200 functions to bq27x00, as they are no longer bq27200 specific. Signed-off-by: Grazvydas Ignotas Acked-by: Rodolfo Giometti Signed-off-by: Anton Vorontsov --- drivers/power/Kconfig | 4 +-- drivers/power/bq27x00_battery.c | 77 ++++++++++++++++++++++++++--------------- 2 files changed, 51 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index d4b3d67f0548..bf1467213954 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -98,10 +98,10 @@ config BATTERY_WM97XX Say Y to enable support for battery measured by WM97xx aux port. config BATTERY_BQ27x00 - tristate "BQ27200 battery driver" + tristate "BQ27x00 battery driver" depends on I2C help - Say Y here to enable support for batteries with BQ27200(I2C) chip. + Say Y here to enable support for batteries with BQ27x00 (I2C) chips. config BATTERY_DA9030 tristate "DA9030 battery driver" diff --git a/drivers/power/bq27x00_battery.c b/drivers/power/bq27x00_battery.c index 3da9e0aa705a..1526d020cbc6 100644 --- a/drivers/power/bq27x00_battery.c +++ b/drivers/power/bq27x00_battery.c @@ -26,14 +26,17 @@ #include #include -#define DRIVER_VERSION "1.0.0" +#define DRIVER_VERSION "1.1.0" #define BQ27x00_REG_TEMP 0x06 #define BQ27x00_REG_VOLT 0x08 -#define BQ27x00_REG_RSOC 0x0B /* Relative State-of-Charge */ #define BQ27x00_REG_AI 0x14 #define BQ27x00_REG_FLAGS 0x0A +#define BQ27000_REG_RSOC 0x0B /* Relative State-of-Charge */ + +#define BQ27500_REG_SOC 0x2c + /* If the system has several batteries we need a different name for each * of them... */ @@ -46,11 +49,14 @@ struct bq27x00_access_methods { struct bq27x00_device_info *di); }; +enum bq27x00_chip { BQ27000, BQ27500 }; + struct bq27x00_device_info { struct device *dev; int id; struct bq27x00_access_methods *bus; struct power_supply bat; + enum bq27x00_chip chip; struct i2c_client *client; }; @@ -88,7 +94,10 @@ static int bq27x00_battery_temperature(struct bq27x00_device_info *di) return ret; } - return ((temp >> 2) - 273) * 10; + if (di->chip == BQ27500) + return temp - 2731; + else + return ((temp >> 2) - 273) * 10; } /* @@ -125,15 +134,22 @@ static int bq27x00_battery_current(struct bq27x00_device_info *di) dev_err(di->dev, "error reading current\n"); return 0; } - ret = bq27x00_read(BQ27x00_REG_FLAGS, &flags, 0, di); - if (ret < 0) { - dev_err(di->dev, "error reading flags\n"); - return 0; - } - if ((flags & (1 << 7)) != 0) { - dev_dbg(di->dev, "negative current!\n"); - return -curr; + + if (di->chip == BQ27500) { + /* bq27500 returns signed value */ + curr = (int)(s16)curr; + } else { + ret = bq27x00_read(BQ27x00_REG_FLAGS, &flags, 0, di); + if (ret < 0) { + dev_err(di->dev, "error reading flags\n"); + return 0; + } + if ((flags & (1 << 7)) != 0) { + dev_dbg(di->dev, "negative current!\n"); + return -curr; + } } + return curr; } @@ -146,7 +162,10 @@ static int bq27x00_battery_rsoc(struct bq27x00_device_info *di) int ret; int rsoc = 0; - ret = bq27x00_read(BQ27x00_REG_RSOC, &rsoc, 1, di); + if (di->chip == BQ27500) + ret = bq27x00_read(BQ27500_REG_SOC, &rsoc, 0, di); + else + ret = bq27x00_read(BQ27000_REG_RSOC, &rsoc, 1, di); if (ret) { dev_err(di->dev, "error reading relative State-of-Charge\n"); return ret; @@ -197,10 +216,10 @@ static void bq27x00_powersupply_init(struct bq27x00_device_info *di) } /* - * BQ27200 specific code + * i2c specific code */ -static int bq27200_read(u8 reg, int *rt_value, int b_single, +static int bq27x00_read_i2c(u8 reg, int *rt_value, int b_single, struct bq27x00_device_info *di) { struct i2c_client *client = di->client; @@ -239,7 +258,7 @@ static int bq27200_read(u8 reg, int *rt_value, int b_single, return err; } -static int bq27200_battery_probe(struct i2c_client *client, +static int bq27x00_battery_probe(struct i2c_client *client, const struct i2c_device_id *id) { char *name; @@ -258,7 +277,7 @@ static int bq27200_battery_probe(struct i2c_client *client, if (retval < 0) return retval; - name = kasprintf(GFP_KERNEL, "bq27200-%d", num); + name = kasprintf(GFP_KERNEL, "%s-%d", id->name, num); if (!name) { dev_err(&client->dev, "failed to allocate device name\n"); retval = -ENOMEM; @@ -272,6 +291,7 @@ static int bq27200_battery_probe(struct i2c_client *client, goto batt_failed_2; } di->id = num; + di->chip = id->driver_data; bus = kzalloc(sizeof(*bus), GFP_KERNEL); if (!bus) { @@ -284,7 +304,7 @@ static int bq27200_battery_probe(struct i2c_client *client, i2c_set_clientdata(client, di); di->dev = &client->dev; di->bat.name = name; - bus->read = &bq27200_read; + bus->read = &bq27x00_read_i2c; di->bus = bus; di->client = client; @@ -314,7 +334,7 @@ batt_failed_1: return retval; } -static int bq27200_battery_remove(struct i2c_client *client) +static int bq27x00_battery_remove(struct i2c_client *client) { struct bq27x00_device_info *di = i2c_get_clientdata(client); @@ -335,27 +355,28 @@ static int bq27200_battery_remove(struct i2c_client *client) * Module stuff */ -static const struct i2c_device_id bq27200_id[] = { - { "bq27200", 0 }, +static const struct i2c_device_id bq27x00_id[] = { + { "bq27200", BQ27000 }, /* bq27200 is same as bq27000, but with i2c */ + { "bq27500", BQ27500 }, {}, }; -static struct i2c_driver bq27200_battery_driver = { +static struct i2c_driver bq27x00_battery_driver = { .driver = { - .name = "bq27200-battery", + .name = "bq27x00-battery", }, - .probe = bq27200_battery_probe, - .remove = bq27200_battery_remove, - .id_table = bq27200_id, + .probe = bq27x00_battery_probe, + .remove = bq27x00_battery_remove, + .id_table = bq27x00_id, }; static int __init bq27x00_battery_init(void) { int ret; - ret = i2c_add_driver(&bq27200_battery_driver); + ret = i2c_add_driver(&bq27x00_battery_driver); if (ret) - printk(KERN_ERR "Unable to register BQ27200 driver\n"); + printk(KERN_ERR "Unable to register BQ27x00 driver\n"); return ret; } @@ -363,7 +384,7 @@ module_init(bq27x00_battery_init); static void __exit bq27x00_battery_exit(void) { - i2c_del_driver(&bq27200_battery_driver); + i2c_del_driver(&bq27x00_battery_driver); } module_exit(bq27x00_battery_exit); -- cgit v1.2.3 From 29105ccc43ead5a0179d04b1404611981e92e278 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 7 Jan 2010 10:39:13 +0000 Subject: drm/i915: Replace open-coded eviction in i915_gem_idle() With the introduction of the hang-check, we can safely expect that i915_wait_request() will always return even when the GPU hangs, and so do not need to open code the wait in order to manually check for the hang. Also we do not need to always evict all buffers, so only flush the GPU (and wait for it to idle) for KMS, but continue to evict for UMS. Signed-off-by: Chris Wilson Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_gem.c | 144 ++++++++++++---------------------------- 1 file changed, 44 insertions(+), 100 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index ec8a0d7ffa39..129ac36ddc58 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4441,129 +4441,73 @@ i915_gem_evict_from_inactive_list(struct drm_device *dev) return 0; } -int -i915_gem_idle(struct drm_device *dev) +static int +i915_gpu_idle(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; - uint32_t seqno, cur_seqno, last_seqno; - int stuck, ret; + bool lists_empty; + uint32_t seqno; - mutex_lock(&dev->struct_mutex); + spin_lock(&dev_priv->mm.active_list_lock); + lists_empty = list_empty(&dev_priv->mm.flushing_list) && + list_empty(&dev_priv->mm.active_list); + spin_unlock(&dev_priv->mm.active_list_lock); - if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) { - mutex_unlock(&dev->struct_mutex); + if (lists_empty) return 0; - } - - /* Hack! Don't let anybody do execbuf while we don't control the chip. - * We need to replace this with a semaphore, or something. - */ - dev_priv->mm.suspended = 1; - del_timer(&dev_priv->hangcheck_timer); - - /* Cancel the retire work handler, wait for it to finish if running - */ - mutex_unlock(&dev->struct_mutex); - cancel_delayed_work_sync(&dev_priv->mm.retire_work); - mutex_lock(&dev->struct_mutex); - i915_kernel_lost_context(dev); - - /* Flush the GPU along with all non-CPU write domains - */ + /* Flush everything onto the inactive list. */ i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); - - if (seqno == 0) { - mutex_unlock(&dev->struct_mutex); + if (seqno == 0) return -ENOMEM; - } - - dev_priv->mm.waiting_gem_seqno = seqno; - last_seqno = 0; - stuck = 0; - for (;;) { - cur_seqno = i915_get_gem_seqno(dev); - if (i915_seqno_passed(cur_seqno, seqno)) - break; - if (last_seqno == cur_seqno) { - if (stuck++ > 100) { - DRM_ERROR("hardware wedged\n"); - atomic_set(&dev_priv->mm.wedged, 1); - DRM_WAKEUP(&dev_priv->irq_queue); - break; - } - } - msleep(10); - last_seqno = cur_seqno; - } - dev_priv->mm.waiting_gem_seqno = 0; - - i915_gem_retire_requests(dev); - - spin_lock(&dev_priv->mm.active_list_lock); - if (!atomic_read(&dev_priv->mm.wedged)) { - /* Active and flushing should now be empty as we've - * waited for a sequence higher than any pending execbuffer - */ - WARN_ON(!list_empty(&dev_priv->mm.active_list)); - WARN_ON(!list_empty(&dev_priv->mm.flushing_list)); - /* Request should now be empty as we've also waited - * for the last request in the list - */ - WARN_ON(!list_empty(&dev_priv->mm.request_list)); - } - - /* Empty the active and flushing lists to inactive. If there's - * anything left at this point, it means that we're wedged and - * nothing good's going to happen by leaving them there. So strip - * the GPU domains and just stuff them onto inactive. - */ - while (!list_empty(&dev_priv->mm.active_list)) { - struct drm_gem_object *obj; - uint32_t old_write_domain; - - obj = list_first_entry(&dev_priv->mm.active_list, - struct drm_i915_gem_object, - list)->obj; - old_write_domain = obj->write_domain; - obj->write_domain &= ~I915_GEM_GPU_DOMAINS; - i915_gem_object_move_to_inactive(obj); - trace_i915_gem_object_change_domain(obj, - obj->read_domains, - old_write_domain); - } - spin_unlock(&dev_priv->mm.active_list_lock); + return i915_wait_request(dev, seqno); +} - while (!list_empty(&dev_priv->mm.flushing_list)) { - struct drm_gem_object *obj; - uint32_t old_write_domain; +int +i915_gem_idle(struct drm_device *dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + int ret; - obj = list_first_entry(&dev_priv->mm.flushing_list, - struct drm_i915_gem_object, - list)->obj; - old_write_domain = obj->write_domain; - obj->write_domain &= ~I915_GEM_GPU_DOMAINS; - i915_gem_object_move_to_inactive(obj); + mutex_lock(&dev->struct_mutex); - trace_i915_gem_object_change_domain(obj, - obj->read_domains, - old_write_domain); + if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) { + mutex_unlock(&dev->struct_mutex); + return 0; } - - /* Move all inactive buffers out of the GTT. */ - ret = i915_gem_evict_from_inactive_list(dev); - WARN_ON(!list_empty(&dev_priv->mm.inactive_list)); + ret = i915_gpu_idle(dev); if (ret) { mutex_unlock(&dev->struct_mutex); return ret; } + /* Under UMS, be paranoid and evict. */ + if (!drm_core_check_feature(dev, DRIVER_MODESET)) { + ret = i915_gem_evict_from_inactive_list(dev); + if (ret) { + mutex_unlock(&dev->struct_mutex); + return ret; + } + } + + /* Hack! Don't let anybody do execbuf while we don't control the chip. + * We need to replace this with a semaphore, or something. + * And not confound mm.suspended! + */ + dev_priv->mm.suspended = 1; + del_timer(&dev_priv->hangcheck_timer); + + i915_kernel_lost_context(dev); i915_gem_cleanup_ringbuffer(dev); + mutex_unlock(&dev->struct_mutex); + /* Cancel the retire work handler, which should be idle now. */ + cancel_delayed_work_sync(&dev_priv->mm.retire_work); + return 0; } -- cgit v1.2.3 From c4804411691bdd7d8a57e942cbb502fd52a90074 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Thu, 17 Dec 2009 14:48:43 +0800 Subject: drm/i915: Keep MCHBAR always enabled As we need more and more controls within MCHBAR for memory config and power management, this trys to keep MCHBAR enabled from driver load and only tear down in driver unload. Signed-off-by: Zhenyu Wang Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_dma.c | 121 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_tiling.c | 122 --------------------------------- 3 files changed, 122 insertions(+), 122 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 2307f98349f7..3afe361ec552 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -35,6 +35,8 @@ #include "i915_drv.h" #include "i915_trace.h" #include +#include +#include /* Really want an OS-independent resettable timer. Would like to have * this loop run for (eg) 3 sec, but have the timer reset every time @@ -933,6 +935,120 @@ static int i915_get_bridge_dev(struct drm_device *dev) return 0; } +#define MCHBAR_I915 0x44 +#define MCHBAR_I965 0x48 +#define MCHBAR_SIZE (4*4096) + +#define DEVEN_REG 0x54 +#define DEVEN_MCHBAR_EN (1 << 28) + +/* Allocate space for the MCH regs if needed, return nonzero on error */ +static int +intel_alloc_mchbar_resource(struct drm_device *dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; + u32 temp_lo, temp_hi = 0; + u64 mchbar_addr; + int ret = 0; + + if (IS_I965G(dev)) + pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); + pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); + mchbar_addr = ((u64)temp_hi << 32) | temp_lo; + + /* If ACPI doesn't have it, assume we need to allocate it ourselves */ +#ifdef CONFIG_PNP + if (mchbar_addr && + pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { + ret = 0; + goto out; + } +#endif + + /* Get some space for it */ + ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res, + MCHBAR_SIZE, MCHBAR_SIZE, + PCIBIOS_MIN_MEM, + 0, pcibios_align_resource, + dev_priv->bridge_dev); + if (ret) { + DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); + dev_priv->mch_res.start = 0; + goto out; + } + + if (IS_I965G(dev)) + pci_write_config_dword(dev_priv->bridge_dev, reg + 4, + upper_32_bits(dev_priv->mch_res.start)); + + pci_write_config_dword(dev_priv->bridge_dev, reg, + lower_32_bits(dev_priv->mch_res.start)); +out: + return ret; +} + +/* Setup MCHBAR if possible, return true if we should disable it again */ +static void +intel_setup_mchbar(struct drm_device *dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; + u32 temp; + bool enabled; + + dev_priv->mchbar_need_disable = false; + + if (IS_I915G(dev) || IS_I915GM(dev)) { + pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); + enabled = !!(temp & DEVEN_MCHBAR_EN); + } else { + pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); + enabled = temp & 1; + } + + /* If it's already enabled, don't have to do anything */ + if (enabled) + return; + + if (intel_alloc_mchbar_resource(dev)) + return; + + dev_priv->mchbar_need_disable = true; + + /* Space is allocated or reserved, so enable it. */ + if (IS_I915G(dev) || IS_I915GM(dev)) { + pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, + temp | DEVEN_MCHBAR_EN); + } else { + pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); + pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); + } +} + +static void +intel_teardown_mchbar(struct drm_device *dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; + u32 temp; + + if (dev_priv->mchbar_need_disable) { + if (IS_I915G(dev) || IS_I915GM(dev)) { + pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); + temp &= ~DEVEN_MCHBAR_EN; + pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); + } else { + pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); + temp &= ~1; + pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); + } + } + + if (dev_priv->mch_res.start) + release_resource(&dev_priv->mch_res); +} + /** * i915_probe_agp - get AGP bootup configuration * @pdev: PCI device @@ -1450,6 +1566,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) dev->driver->get_vblank_counter = gm45_get_vblank_counter; } + /* Try to make sure MCHBAR is enabled before poking at it */ + intel_setup_mchbar(dev); + i915_gem_load(dev); /* Init HWS */ @@ -1569,6 +1688,8 @@ int i915_driver_unload(struct drm_device *dev) intel_cleanup_overlay(dev); } + intel_teardown_mchbar(dev); + pci_dev_put(dev_priv->bridge_dev); kfree(dev->dev_private); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b99b6a841d95..f2742d6d3f54 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -590,6 +590,7 @@ typedef struct drm_i915_private { int child_dev_num; struct child_device_config *child_dev; struct drm_connector *int_lvds_connector; + bool mchbar_need_disable; } drm_i915_private_t; /** driver private structure attached to each drm_gem_object */ diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index df278b2685bf..f308fdf43725 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -25,8 +25,6 @@ * */ -#include -#include #include "linux/string.h" #include "linux/bitops.h" #include "drmP.h" @@ -83,120 +81,6 @@ * to match what the GPU expects. */ -#define MCHBAR_I915 0x44 -#define MCHBAR_I965 0x48 -#define MCHBAR_SIZE (4*4096) - -#define DEVEN_REG 0x54 -#define DEVEN_MCHBAR_EN (1 << 28) - -/* Allocate space for the MCH regs if needed, return nonzero on error */ -static int -intel_alloc_mchbar_resource(struct drm_device *dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; - u32 temp_lo, temp_hi = 0; - u64 mchbar_addr; - int ret = 0; - - if (IS_I965G(dev)) - pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); - pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); - mchbar_addr = ((u64)temp_hi << 32) | temp_lo; - - /* If ACPI doesn't have it, assume we need to allocate it ourselves */ -#ifdef CONFIG_PNP - if (mchbar_addr && - pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { - ret = 0; - goto out; - } -#endif - - /* Get some space for it */ - ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res, - MCHBAR_SIZE, MCHBAR_SIZE, - PCIBIOS_MIN_MEM, - 0, pcibios_align_resource, - dev_priv->bridge_dev); - if (ret) { - DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); - dev_priv->mch_res.start = 0; - goto out; - } - - if (IS_I965G(dev)) - pci_write_config_dword(dev_priv->bridge_dev, reg + 4, - upper_32_bits(dev_priv->mch_res.start)); - - pci_write_config_dword(dev_priv->bridge_dev, reg, - lower_32_bits(dev_priv->mch_res.start)); -out: - return ret; -} - -/* Setup MCHBAR if possible, return true if we should disable it again */ -static bool -intel_setup_mchbar(struct drm_device *dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; - u32 temp; - bool need_disable = false, enabled; - - if (IS_I915G(dev) || IS_I915GM(dev)) { - pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); - enabled = !!(temp & DEVEN_MCHBAR_EN); - } else { - pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); - enabled = temp & 1; - } - - /* If it's already enabled, don't have to do anything */ - if (enabled) - goto out; - - if (intel_alloc_mchbar_resource(dev)) - goto out; - - need_disable = true; - - /* Space is allocated or reserved, so enable it. */ - if (IS_I915G(dev) || IS_I915GM(dev)) { - pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, - temp | DEVEN_MCHBAR_EN); - } else { - pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); - pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); - } -out: - return need_disable; -} - -static void -intel_teardown_mchbar(struct drm_device *dev, bool disable) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; - u32 temp; - - if (disable) { - if (IS_I915G(dev) || IS_I915GM(dev)) { - pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); - temp &= ~DEVEN_MCHBAR_EN; - pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); - } else { - pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); - temp &= ~1; - pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); - } - } - - if (dev_priv->mch_res.start) - release_resource(&dev_priv->mch_res); -} - /** * Detects bit 6 swizzling of address lookup between IGD access and CPU * access through main memory. @@ -207,7 +91,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) drm_i915_private_t *dev_priv = dev->dev_private; uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; - bool need_disable; if (IS_IRONLAKE(dev)) { /* On Ironlake whatever DRAM config, GPU always do @@ -224,9 +107,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) } else if (IS_MOBILE(dev)) { uint32_t dcc; - /* Try to make sure MCHBAR is enabled before poking at it */ - need_disable = intel_setup_mchbar(dev); - /* On mobile 9xx chipsets, channel interleave by the CPU is * determined by DCC. For single-channel, neither the CPU * nor the GPU do swizzling. For dual channel interleaved, @@ -266,8 +146,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; } - - intel_teardown_mchbar(dev, need_disable); } else { /* The 965, G33, and newer, have a very flexible memory * configuration. It will enable dual-channel mode -- cgit v1.2.3 From b397c836eff58cd9a43f7bd8b853a51b3ecc3420 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 26 Jan 2010 09:43:10 -0800 Subject: drm/i915: Don't reserve compatibility fence regs in KMS mode. The fence start is for compatibility with UMS X Servers before fence management. KMS X Servers only started doing tiling after fence management appeared. Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 129ac36ddc58..4a141993a37a 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4794,7 +4794,8 @@ i915_gem_load(struct drm_device *dev) spin_unlock(&shrink_list_lock); /* Old X drivers will take 0-2 for front, back, depth buffers */ - dev_priv->fence_reg_start = 3; + if (!drm_core_check_feature(dev, DRIVER_MODESET)) + dev_priv->fence_reg_start = 3; if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) dev_priv->num_fence_regs = 16; -- cgit v1.2.3 From 71b10d8762b2a548c4ac2e4461b46d9b205a5c77 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 16 Feb 2010 11:28:36 -0500 Subject: drm/radeon/r600: fix warnings in CS checker MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/radeon/r600_cs.c: In function ‘r600_cs_track_check’: drivers/gpu/drm/radeon/r600_cs.c:166: warning: ‘bpe’ may be used uninitialized in this function drivers/gpu/drm/radeon/r600_cs.c:166: note: ‘bpe’ was declared here drivers/gpu/drm/radeon/r600_cs.c: In function ‘r600_cs_parse’: drivers/gpu/drm/radeon/r600_cs.c:938: warning: ‘bpe’ may be used uninitialized in this function drivers/gpu/drm/radeon/r600_cs.c:938: note: ‘bpe’ was declared here Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600_cs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 00e69c585fbf..cd2c63bce501 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -163,7 +163,7 @@ static void r600_cs_track_init(struct r600_cs_track *track) static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) { struct r600_cs_track *track = p->track; - u32 bpe, pitch, slice_tile_max, size, tmp, height; + u32 bpe = 0, pitch, slice_tile_max, size, tmp, height; volatile u32 *ib = p->ib->ptr; if (G_0280A0_TILE_MODE(track->cb_color_info[i])) { @@ -935,7 +935,7 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i struct radeon_bo *texture, struct radeon_bo *mipmap) { - u32 nfaces, nlevels, blevel, w0, h0, d0, bpe; + u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0; u32 word0, word1, l0_size, mipmap_size; /* on legacy kernel we don't perform advanced check */ -- cgit v1.2.3 From 5230aea62c0d8f53edcc3e014c3404132afcfeb4 Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Thu, 11 Feb 2010 22:58:52 +0100 Subject: drm/radeon/kms: isolate audio engine management, change fini order MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We should stop audio-state-reading timer before we turn off engine Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600_audio.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c index b1c1d3433454..d7f6909afc01 100644 --- a/drivers/gpu/drm/radeon/r600_audio.c +++ b/drivers/gpu/drm/radeon/r600_audio.c @@ -146,6 +146,15 @@ static void r600_audio_update_hdmi(unsigned long param) jiffies + msecs_to_jiffies(AUDIO_TIMER_INTERVALL)); } +/* + * turn on/off audio engine + */ +static void r600_audio_engine_enable(struct radeon_device *rdev, bool enable) +{ + DRM_INFO("%s audio support", enable ? "Enabling" : "Disabling"); + WREG32_P(R600_AUDIO_ENABLE, enable ? 0x81000000 : 0x0, ~0x81000000); +} + /* * initialize the audio vars and register the update timer */ @@ -154,8 +163,7 @@ int r600_audio_init(struct radeon_device *rdev) if (!r600_audio_chipset_supported(rdev)) return 0; - DRM_INFO("%s audio support", radeon_audio ? "Enabling" : "Disabling"); - WREG32_P(R600_AUDIO_ENABLE, radeon_audio ? 0x81000000 : 0x0, ~0x81000000); + r600_audio_engine_enable(rdev, radeon_audio); rdev->audio_channels = -1; rdev->audio_rate = -1; @@ -261,7 +269,7 @@ void r600_audio_fini(struct radeon_device *rdev) if (!r600_audio_chipset_supported(rdev)) return; - WREG32_P(R600_AUDIO_ENABLE, 0x0, ~0x81000000); - del_timer(&rdev->audio_timer); + + r600_audio_engine_enable(rdev, false); } -- cgit v1.2.3 From 2745932495ca3634b11a8662b464d2bf0325ae78 Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Thu, 11 Feb 2010 22:16:36 +0000 Subject: drm/radeon/kms: accept slightly overclocked power modes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes fdo bug #26329 Signed-off-by: RafaÅ‚ MiÅ‚ecki Tested-by: Tobias Jakobi Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon.h | 5 +++++ drivers/gpu/drm/radeon/radeon_atombios.c | 18 +++++++++--------- drivers/gpu/drm/radeon/radeon_combios.c | 4 ++-- 3 files changed, 16 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 9f35beed13e8..350ae71953e9 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -662,6 +662,11 @@ struct radeon_power_state { bool voltage_drop_active; }; +/* + * Some modes are overclocked by very low value, accept them + */ +#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ + struct radeon_pm { struct mutex mutex; struct delayed_work idle_work; diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 4f7dbce9883a..731210bef744 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -1463,9 +1463,9 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) continue; /* skip overclock modes for now */ if ((rdev->pm.power_state[state_index].clock_info[0].mclk > - rdev->clock.default_mclk) || + rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) || (rdev->pm.power_state[state_index].clock_info[0].sclk > - rdev->clock.default_sclk)) + rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)) continue; rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = power_info->info.asPowerPlayInfo[i].ucNumPciELanes; @@ -1528,9 +1528,9 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) continue; /* skip overclock modes for now */ if ((rdev->pm.power_state[state_index].clock_info[0].mclk > - rdev->clock.default_mclk) || + rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) || (rdev->pm.power_state[state_index].clock_info[0].sclk > - rdev->clock.default_sclk)) + rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)) continue; rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; @@ -1597,9 +1597,9 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) continue; /* skip overclock modes for now */ if ((rdev->pm.power_state[state_index].clock_info[0].mclk > - rdev->clock.default_mclk) || + rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) || (rdev->pm.power_state[state_index].clock_info[0].sclk > - rdev->clock.default_sclk)) + rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)) continue; rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; @@ -1693,7 +1693,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) continue; /* skip overclock modes for now */ if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk > - rdev->clock.default_sclk) + rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN) continue; rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = VOLTAGE_SW; @@ -1720,9 +1720,9 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) continue; /* skip overclock modes for now */ if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk > - rdev->clock.default_mclk) || + rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) || (rdev->pm.power_state[state_index].clock_info[mode_index].sclk > - rdev->clock.default_sclk)) + rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)) continue; rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = VOLTAGE_SW; diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index 9989d22a4d8f..5ef791be5036 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -2374,9 +2374,9 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) goto default_mode; /* skip overclock modes for now */ if ((rdev->pm.power_state[state_index].clock_info[0].mclk > - rdev->clock.default_mclk) || + rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) || (rdev->pm.power_state[state_index].clock_info[0].sclk > - rdev->clock.default_sclk)) + rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)) goto default_mode; rdev->pm.power_state[state_index].type = POWER_STATE_TYPE_BATTERY; -- cgit v1.2.3 From bc4624cad9b53b3fd3248fe3086b432471fc0fe0 Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Thu, 11 Feb 2010 21:50:06 +0000 Subject: drm/radeon/kms: simplify picking power state Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_pm.c | 57 ++++++++++++-------------------------- 1 file changed, 18 insertions(+), 39 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index a8e151ec1351..f0234351fd57 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -81,60 +81,39 @@ static void radeon_print_power_mode_info(struct radeon_device *rdev) static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev, enum radeon_pm_state_type type) { - int i; - struct radeon_power_state *power_state = NULL; + int i, j; + enum radeon_pm_state_type wanted_types[2]; + int wanted_count; switch (type) { case POWER_STATE_TYPE_DEFAULT: default: return rdev->pm.default_power_state; case POWER_STATE_TYPE_POWERSAVE: - for (i = 0; i < rdev->pm.num_power_states; i++) { - if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_POWERSAVE) { - power_state = &rdev->pm.power_state[i]; - break; - } - } - if (power_state == NULL) { - for (i = 0; i < rdev->pm.num_power_states; i++) { - if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY) { - power_state = &rdev->pm.power_state[i]; - break; - } - } - } + wanted_types[0] = POWER_STATE_TYPE_POWERSAVE; + wanted_types[1] = POWER_STATE_TYPE_BATTERY; + wanted_count = 2; break; case POWER_STATE_TYPE_BATTERY: - for (i = 0; i < rdev->pm.num_power_states; i++) { - if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY) { - power_state = &rdev->pm.power_state[i]; - break; - } - } - if (power_state == NULL) { - for (i = 0; i < rdev->pm.num_power_states; i++) { - if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_POWERSAVE) { - power_state = &rdev->pm.power_state[i]; - break; - } - } - } + wanted_types[0] = POWER_STATE_TYPE_BATTERY; + wanted_types[1] = POWER_STATE_TYPE_POWERSAVE; + wanted_count = 2; break; case POWER_STATE_TYPE_BALANCED: case POWER_STATE_TYPE_PERFORMANCE: - for (i = 0; i < rdev->pm.num_power_states; i++) { - if (rdev->pm.power_state[i].type == type) { - power_state = &rdev->pm.power_state[i]; - break; - } - } + wanted_types[0] = type; + wanted_count = 1; break; } - if (power_state == NULL) - return rdev->pm.default_power_state; + for (i = 0; i < wanted_count; i++) { + for (j = 0; j < rdev->pm.num_power_states; j++) { + if (rdev->pm.power_state[j].type == wanted_types[i]) + return &rdev->pm.power_state[j]; + } + } - return power_state; + return rdev->pm.default_power_state; } static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev, -- cgit v1.2.3 From 8e0d84a63af351f5367103b83478f2cd4d9a3727 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 16 Feb 2010 11:44:21 -0500 Subject: drm/radeon/kms: add LVDS pll quirk for Dell Studio 15 fixes fdo bug 26358 Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_atombios.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 731210bef744..79d445373c34 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -1109,6 +1109,15 @@ static void radeon_atom_apply_lvds_quirks(struct drm_device *dev, lvds->pll_algo = PLL_ALGO_LEGACY; } + /* Dell Studio 15 laptop panel doesn't like new pll divider algo */ + if ((dev->pdev->device == 0x95c4) && + (dev->pdev->subsystem_vendor == 0x1028) && + (dev->pdev->subsystem_device == 0x029f)) { + if ((lvds->native_mode.hdisplay == 1280) && + (lvds->native_mode.vdisplay == 800)) + lvds->pll_algo = PLL_ALGO_LEGACY; + } + } union lvds_info { -- cgit v1.2.3 From 6ad86c311a8b8a6d856527a1b6ba21790ab7054b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 11 Feb 2010 10:47:52 -0500 Subject: drm/radeon/kms: remove HDP flushes from fence emit (v2) r600_ioctl_wait_idle() now handles this. v2: update blit fence counts Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600.c | 2 -- drivers/gpu/drm/radeon/r600_blit_kms.c | 4 ++-- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 6434d6af7d52..f040ee6755d7 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -1804,8 +1804,6 @@ void r600_fence_ring_emit(struct radeon_device *rdev, radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); radeon_ring_write(rdev, fence->seq); - radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); - radeon_ring_write(rdev, 1); /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); radeon_ring_write(rdev, RB_INT_STAT); diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c index ec49dada887d..de8bbbcfe117 100644 --- a/drivers/gpu/drm/radeon/r600_blit_kms.c +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c @@ -576,9 +576,9 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) ring_size = num_loops * dwords_per_loop; /* set default + shaders */ ring_size += 40; /* shaders + def state */ - ring_size += 12; /* fence emit for VB IB */ + ring_size += 10; /* fence emit for VB IB */ ring_size += 5; /* done copy */ - ring_size += 12; /* fence emit for done copy */ + ring_size += 10; /* fence emit for done copy */ r = radeon_ring_lock(rdev, ring_size); if (r) return r; -- cgit v1.2.3 From 93f319d31cc42a77bd5e953e861a8f2bfb277ad1 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 11 Feb 2010 11:00:13 -0500 Subject: drm/radeon/kms: remove unused r600_gart_clear_page r6xx/r7xx use the rs600 variant. This old one just confuses things. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600.c | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index f040ee6755d7..a865946d2d08 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -353,18 +353,6 @@ void r600_hpd_fini(struct radeon_device *rdev) /* * R600 PCIE GART */ -int r600_gart_clear_page(struct radeon_device *rdev, int i) -{ - void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; - u64 pte; - - if (i < 0 || i > rdev->gart.num_gpu_pages) - return -EINVAL; - pte = 0; - writeq(pte, ((void __iomem *)ptr) + (i * 8)); - return 0; -} - void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) { unsigned i; -- cgit v1.2.3 From d80eeb0f347b6effa06e11e7cbcb2e6c559bf404 Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Thu, 11 Feb 2010 17:55:35 +0000 Subject: drm/radeon/kms: Create asic structure for r300 pcie cards. Setting global asic structure to point to different function would cause problem in system where is multiple r300 cards with different bus type. r300_asic_pcie is just copy from r300_asic with gart tlb functions replaced with pcie versions. Signed-off-by: Pauli Nieminen Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_asic.h | 38 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/radeon/radeon_device.c | 9 ++++---- 2 files changed, 42 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 4b0cb67a379a..9d2a113f78eb 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -183,6 +183,44 @@ static struct radeon_asic r300_asic = { .ioctl_wait_idle = NULL, }; + +static struct radeon_asic r300_asic_pcie = { + .init = &r300_init, + .fini = &r300_fini, + .suspend = &r300_suspend, + .resume = &r300_resume, + .vga_set_state = &r100_vga_set_state, + .gpu_reset = &r300_gpu_reset, + .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, + .gart_set_page = &rv370_pcie_gart_set_page, + .cp_commit = &r100_cp_commit, + .ring_start = &r300_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .irq_set = &r100_irq_set, + .irq_process = &r100_irq_process, + .get_vblank_counter = &r100_get_vblank_counter, + .fence_ring_emit = &r300_fence_ring_emit, + .cs_parse = &r300_cs_parse, + .copy_blit = &r100_copy_blit, + .copy_dma = &r200_copy_dma, + .copy = &r100_copy_blit, + .get_engine_clock = &radeon_legacy_get_engine_clock, + .set_engine_clock = &radeon_legacy_set_engine_clock, + .get_memory_clock = &radeon_legacy_get_memory_clock, + .set_memory_clock = NULL, + .set_pcie_lanes = &rv370_set_pcie_lanes, + .set_clock_gating = &radeon_legacy_set_clock_gating, + .set_surface_reg = r100_set_surface_reg, + .clear_surface_reg = r100_clear_surface_reg, + .bandwidth_update = &r100_bandwidth_update, + .hpd_init = &r100_hpd_init, + .hpd_fini = &r100_hpd_fini, + .hpd_sense = &r100_hpd_sense, + .hpd_set_polarity = &r100_hpd_set_polarity, + .ioctl_wait_idle = NULL, +}; + /* * r420,r423,rv410 */ diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index fb55faf8e284..7a30f6955e41 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -350,11 +350,10 @@ int radeon_asic_init(struct radeon_device *rdev) case CHIP_R350: case CHIP_RV350: case CHIP_RV380: - rdev->asic = &r300_asic; - if (rdev->flags & RADEON_IS_PCIE) { - rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; - rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; - } + if (rdev->flags & RADEON_IS_PCIE) + rdev->asic = &r300_asic_pcie; + else + rdev->asic = &r300_asic; break; case CHIP_R420: case CHIP_R423: -- cgit v1.2.3 From 44ca7478d46aaad488d916f7262253e000ee60f9 Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Thu, 11 Feb 2010 17:25:47 +0000 Subject: drm/radeon: Add asic hook for dma copy to r200 cards. r200 cards have dma engine which can be used to tranfer data between vram and system memory. r300 dma engine registers match r200 dma engine. Enabling dma copy for r200 is simple as hooking r200 asic to already existing function r300_copy_dma. Rename r300_dma_copy to r200_dma_copyto reflect that supports starts from r200 cards. v2: Created a new asic object for r200 cards. Signed-off-by: Pauli Nieminen Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r200.c | 46 +++++++++++++++++++++++ drivers/gpu/drm/radeon/r300.c | 44 ---------------------- drivers/gpu/drm/radeon/radeon_asic.h | 69 +++++++++++++++++++++++++++------- drivers/gpu/drm/radeon/radeon_device.c | 4 +- 4 files changed, 104 insertions(+), 59 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c index ff1e0cd608bf..1146c9909c2c 100644 --- a/drivers/gpu/drm/radeon/r200.c +++ b/drivers/gpu/drm/radeon/r200.c @@ -31,6 +31,7 @@ #include "radeon_reg.h" #include "radeon.h" +#include "r100d.h" #include "r200_reg_safe.h" #include "r100_track.h" @@ -79,6 +80,51 @@ static int r200_get_vtx_size_0(uint32_t vtx_fmt_0) return vtx_size; } +int r200_copy_dma(struct radeon_device *rdev, + uint64_t src_offset, + uint64_t dst_offset, + unsigned num_pages, + struct radeon_fence *fence) +{ + uint32_t size; + uint32_t cur_size; + int i, num_loops; + int r = 0; + + /* radeon pitch is /64 */ + size = num_pages << PAGE_SHIFT; + num_loops = DIV_ROUND_UP(size, 0x1FFFFF); + r = radeon_ring_lock(rdev, num_loops * 4 + 64); + if (r) { + DRM_ERROR("radeon: moving bo (%d).\n", r); + return r; + } + /* Must wait for 2D idle & clean before DMA or hangs might happen */ + radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); + radeon_ring_write(rdev, (1 << 16)); + for (i = 0; i < num_loops; i++) { + cur_size = size; + if (cur_size > 0x1FFFFF) { + cur_size = 0x1FFFFF; + } + size -= cur_size; + radeon_ring_write(rdev, PACKET0(0x720, 2)); + radeon_ring_write(rdev, src_offset); + radeon_ring_write(rdev, dst_offset); + radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); + src_offset += cur_size; + dst_offset += cur_size; + } + radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); + radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); + if (fence) { + r = radeon_fence_emit(rdev, fence); + } + radeon_ring_unlock_commit(rdev); + return r; +} + + static int r200_get_vtx_size_1(uint32_t vtx_fmt_1) { int vtx_size, i, tex_size; diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 654aca1cdf05..a4f395226b34 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -201,50 +201,6 @@ void r300_fence_ring_emit(struct radeon_device *rdev, radeon_ring_write(rdev, RADEON_SW_INT_FIRE); } -int r300_copy_dma(struct radeon_device *rdev, - uint64_t src_offset, - uint64_t dst_offset, - unsigned num_pages, - struct radeon_fence *fence) -{ - uint32_t size; - uint32_t cur_size; - int i, num_loops; - int r = 0; - - /* radeon pitch is /64 */ - size = num_pages << PAGE_SHIFT; - num_loops = DIV_ROUND_UP(size, 0x1FFFFF); - r = radeon_ring_lock(rdev, num_loops * 4 + 64); - if (r) { - DRM_ERROR("radeon: moving bo (%d).\n", r); - return r; - } - /* Must wait for 2D idle & clean before DMA or hangs might happen */ - radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 )); - radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN); - for (i = 0; i < num_loops; i++) { - cur_size = size; - if (cur_size > 0x1FFFFF) { - cur_size = 0x1FFFFF; - } - size -= cur_size; - radeon_ring_write(rdev, PACKET0(0x720, 2)); - radeon_ring_write(rdev, src_offset); - radeon_ring_write(rdev, dst_offset); - radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); - src_offset += cur_size; - dst_offset += cur_size; - } - radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); - radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); - if (fence) { - r = radeon_fence_emit(rdev, fence); - } - radeon_ring_unlock_commit(rdev); - return r; -} - void r300_ring_start(struct radeon_device *rdev) { unsigned gb_tile_config; diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 9d2a113f78eb..b7030d7c0396 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -43,7 +43,7 @@ void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); /* - * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 + * r100,rv100,rs100,rv200,rs200 */ extern int r100_init(struct radeon_device *rdev); extern void r100_fini(struct radeon_device *rdev); @@ -121,6 +121,51 @@ static struct radeon_asic r100_asic = { .ioctl_wait_idle = NULL, }; +/* + * r200,rv250,rs300,rv280 + */ +extern int r200_copy_dma(struct radeon_device *rdev, + uint64_t src_offset, + uint64_t dst_offset, + unsigned num_pages, + struct radeon_fence *fence); +static struct radeon_asic r200_asic = { + .init = &r100_init, + .fini = &r100_fini, + .suspend = &r100_suspend, + .resume = &r100_resume, + .vga_set_state = &r100_vga_set_state, + .gpu_reset = &r100_gpu_reset, + .gart_tlb_flush = &r100_pci_gart_tlb_flush, + .gart_set_page = &r100_pci_gart_set_page, + .cp_commit = &r100_cp_commit, + .ring_start = &r100_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .irq_set = &r100_irq_set, + .irq_process = &r100_irq_process, + .get_vblank_counter = &r100_get_vblank_counter, + .fence_ring_emit = &r100_fence_ring_emit, + .cs_parse = &r100_cs_parse, + .copy_blit = &r100_copy_blit, + .copy_dma = &r200_copy_dma, + .copy = &r100_copy_blit, + .get_engine_clock = &radeon_legacy_get_engine_clock, + .set_engine_clock = &radeon_legacy_set_engine_clock, + .get_memory_clock = &radeon_legacy_get_memory_clock, + .set_memory_clock = NULL, + .set_pcie_lanes = NULL, + .set_clock_gating = &radeon_legacy_set_clock_gating, + .set_surface_reg = r100_set_surface_reg, + .clear_surface_reg = r100_clear_surface_reg, + .bandwidth_update = &r100_bandwidth_update, + .hpd_init = &r100_hpd_init, + .hpd_fini = &r100_hpd_fini, + .hpd_sense = &r100_hpd_sense, + .hpd_set_polarity = &r100_hpd_set_polarity, + .ioctl_wait_idle = NULL, +}; + /* * r300,r350,rv350,rv380 @@ -140,11 +185,7 @@ extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); extern int rv370_get_pcie_lanes(struct radeon_device *rdev); -extern int r300_copy_dma(struct radeon_device *rdev, - uint64_t src_offset, - uint64_t dst_offset, - unsigned num_pages, - struct radeon_fence *fence); + static struct radeon_asic r300_asic = { .init = &r300_init, .fini = &r300_fini, @@ -164,7 +205,7 @@ static struct radeon_asic r300_asic = { .fence_ring_emit = &r300_fence_ring_emit, .cs_parse = &r300_cs_parse, .copy_blit = &r100_copy_blit, - .copy_dma = &r300_copy_dma, + .copy_dma = &r200_copy_dma, .copy = &r100_copy_blit, .get_engine_clock = &radeon_legacy_get_engine_clock, .set_engine_clock = &radeon_legacy_set_engine_clock, @@ -247,7 +288,7 @@ static struct radeon_asic r420_asic = { .fence_ring_emit = &r300_fence_ring_emit, .cs_parse = &r300_cs_parse, .copy_blit = &r100_copy_blit, - .copy_dma = &r300_copy_dma, + .copy_dma = &r200_copy_dma, .copy = &r100_copy_blit, .get_engine_clock = &radeon_atom_get_engine_clock, .set_engine_clock = &radeon_atom_set_engine_clock, @@ -297,7 +338,7 @@ static struct radeon_asic rs400_asic = { .fence_ring_emit = &r300_fence_ring_emit, .cs_parse = &r300_cs_parse, .copy_blit = &r100_copy_blit, - .copy_dma = &r300_copy_dma, + .copy_dma = &r200_copy_dma, .copy = &r100_copy_blit, .get_engine_clock = &radeon_legacy_get_engine_clock, .set_engine_clock = &radeon_legacy_set_engine_clock, @@ -357,7 +398,7 @@ static struct radeon_asic rs600_asic = { .fence_ring_emit = &r300_fence_ring_emit, .cs_parse = &r300_cs_parse, .copy_blit = &r100_copy_blit, - .copy_dma = &r300_copy_dma, + .copy_dma = &r200_copy_dma, .copy = &r100_copy_blit, .get_engine_clock = &radeon_atom_get_engine_clock, .set_engine_clock = &radeon_atom_set_engine_clock, @@ -404,8 +445,8 @@ static struct radeon_asic rs690_asic = { .fence_ring_emit = &r300_fence_ring_emit, .cs_parse = &r300_cs_parse, .copy_blit = &r100_copy_blit, - .copy_dma = &r300_copy_dma, - .copy = &r300_copy_dma, + .copy_dma = &r200_copy_dma, + .copy = &r200_copy_dma, .get_engine_clock = &radeon_atom_get_engine_clock, .set_engine_clock = &radeon_atom_set_engine_clock, .get_memory_clock = &radeon_atom_get_memory_clock, @@ -457,7 +498,7 @@ static struct radeon_asic rv515_asic = { .fence_ring_emit = &r300_fence_ring_emit, .cs_parse = &r300_cs_parse, .copy_blit = &r100_copy_blit, - .copy_dma = &r300_copy_dma, + .copy_dma = &r200_copy_dma, .copy = &r100_copy_blit, .get_engine_clock = &radeon_atom_get_engine_clock, .set_engine_clock = &radeon_atom_set_engine_clock, @@ -501,7 +542,7 @@ static struct radeon_asic r520_asic = { .fence_ring_emit = &r300_fence_ring_emit, .cs_parse = &r300_cs_parse, .copy_blit = &r100_copy_blit, - .copy_dma = &r300_copy_dma, + .copy_dma = &r200_copy_dma, .copy = &r100_copy_blit, .get_engine_clock = &radeon_atom_get_engine_clock, .set_engine_clock = &radeon_atom_set_engine_clock, diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 7a30f6955e41..7be3a6968463 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -340,11 +340,13 @@ int radeon_asic_init(struct radeon_device *rdev) case CHIP_RS100: case CHIP_RV200: case CHIP_RS200: + rdev->asic = &r100_asic; + break; case CHIP_R200: case CHIP_RV250: case CHIP_RS300: case CHIP_RV280: - rdev->asic = &r100_asic; + rdev->asic = &r200_asic; break; case CHIP_R300: case CHIP_R350: -- cgit v1.2.3 From d594e46ace22afa1621254f6f669e65430048153 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 17 Feb 2010 21:54:29 +0000 Subject: drm/radeon/kms: simplify memory controller setup V2 Get rid of _location and use _start/_end also simplify the computation of vram_start|end & gtt_start|end. For R1XX-R2XX we place VRAM at the same address of PCI aperture, those GPU shouldn't have much memory and seems to behave better when setup that way. For R3XX and newer we place VRAM at 0. For R6XX-R7XX AGP we place VRAM before or after AGP aperture this might limit to limit the VRAM size but it's very unlikely. For IGP we don't change the VRAM placement. Tested on (compiz,quake3,suspend/resume): PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710 AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730 IGP:RS480(RPB*),RS690,RS780(RPB*),RS880 RPB: resume previously broken V2 correct commit message to reflect more accurately the bug and move VRAM placement to 0 for most of the GPU to avoid limiting VRAM. Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/evergreen.c | 51 ++------- drivers/gpu/drm/radeon/r100.c | 93 ++++++---------- drivers/gpu/drm/radeon/r300.c | 27 ++--- drivers/gpu/drm/radeon/r420.c | 36 ++----- drivers/gpu/drm/radeon/r520.c | 21 ++-- drivers/gpu/drm/radeon/r600.c | 123 ++++++++++++---------- drivers/gpu/drm/radeon/radeon.h | 13 +-- drivers/gpu/drm/radeon/radeon_agp.c | 4 + drivers/gpu/drm/radeon/radeon_device.c | 157 ++++++++++++++++------------ drivers/gpu/drm/radeon/radeon_fb.c | 2 +- drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 2 +- drivers/gpu/drm/radeon/radeon_test.c | 2 +- drivers/gpu/drm/radeon/radeon_ttm.c | 12 +-- drivers/gpu/drm/radeon/rs400.c | 38 ++----- drivers/gpu/drm/radeon/rs600.c | 42 ++------ drivers/gpu/drm/radeon/rs690.c | 40 ++----- drivers/gpu/drm/radeon/rv515.c | 21 ++-- drivers/gpu/drm/radeon/rv770.c | 41 +------- 18 files changed, 301 insertions(+), 424 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 3368920df5f4..3f973d411d61 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -439,7 +439,6 @@ int evergreen_mc_init(struct radeon_device *rdev) fixed20_12 a; u32 tmp; int chansize, numchan; - int r; /* Get VRAM informations */ rdev->mc.vram_is_ddr = true; @@ -475,48 +474,12 @@ int evergreen_mc_init(struct radeon_device *rdev) /* size in MB on evergreen */ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; - - if (rdev->mc.mc_vram_size > rdev->mc.aper_size) + /* FIXME remove this once we support unmappable VRAM */ + if (rdev->mc.mc_vram_size > rdev->mc.aper_size) { rdev->mc.mc_vram_size = rdev->mc.aper_size; - - if (rdev->mc.real_vram_size > rdev->mc.aper_size) rdev->mc.real_vram_size = rdev->mc.aper_size; - - if (rdev->flags & RADEON_IS_AGP) { - r = radeon_agp_init(rdev); - if (r) - return r; - /* gtt_size is setup by radeon_agp_init */ - rdev->mc.gtt_location = rdev->mc.agp_base; - tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; - /* Try to put vram before or after AGP because we - * we want SYSTEM_APERTURE to cover both VRAM and - * AGP so that GPU can catch out of VRAM/AGP access - */ - if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { - /* Enought place before */ - rdev->mc.vram_location = rdev->mc.gtt_location - - rdev->mc.mc_vram_size; - } else if (tmp > rdev->mc.mc_vram_size) { - /* Enought place after */ - rdev->mc.vram_location = rdev->mc.gtt_location + - rdev->mc.gtt_size; - } else { - /* Try to setup VRAM then AGP might not - * not work on some card - */ - rdev->mc.vram_location = 0x00000000UL; - rdev->mc.gtt_location = rdev->mc.mc_vram_size; - } - } else { - rdev->mc.vram_location = 0x00000000UL; - rdev->mc.gtt_location = rdev->mc.mc_vram_size; - rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; } - rdev->mc.vram_start = rdev->mc.vram_location; - rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; - rdev->mc.gtt_start = rdev->mc.gtt_location; - rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; + r600_vram_gtt_location(rdev, &rdev->mc); /* FIXME: we should enforce default clock in case GPU is not in * default setup */ @@ -525,6 +488,7 @@ int evergreen_mc_init(struct radeon_device *rdev) rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); return 0; } + int evergreen_gpu_reset(struct radeon_device *rdev) { /* FIXME: implement for evergreen */ @@ -726,6 +690,13 @@ int evergreen_init(struct radeon_device *rdev) r = radeon_fence_driver_init(rdev); if (r) return r; + /* initialize AGP */ + if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) + radeon_agp_disable(rdev); + } + /* initialize memory controller */ r = evergreen_mc_init(rdev); if (r) return r; diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index bc7d9e9211c8..1fdd793343b9 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -202,9 +202,8 @@ int r100_pci_gart_enable(struct radeon_device *rdev) tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; WREG32(RADEON_AIC_CNTL, tmp); /* set address range for PCI address translate */ - WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location); - tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; - WREG32(RADEON_AIC_HI_ADDR, tmp); + WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); + WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); /* set PCI GART page-table base address */ WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; @@ -1957,17 +1956,17 @@ static u32 r100_get_accessible_vram(struct radeon_device *rdev) void r100_vram_init_sizes(struct radeon_device *rdev) { u64 config_aper_size; - u32 accessible; + /* work out accessible VRAM */ + rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); + rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); + rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); - if (rdev->flags & RADEON_IS_IGP) { uint32_t tom; /* read NB_TOM to get the amount of ram stolen for the GPU */ tom = RREG32(RADEON_NB_TOM); rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); - /* for IGPs we need to keep VRAM where it was put by the BIOS */ - rdev->mc.vram_location = (tom & 0xffff) << 16; WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); rdev->mc.mc_vram_size = rdev->mc.real_vram_size; } else { @@ -1979,30 +1978,19 @@ void r100_vram_init_sizes(struct radeon_device *rdev) rdev->mc.real_vram_size = 8192 * 1024; WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); } - /* let driver place VRAM */ - rdev->mc.vram_location = 0xFFFFFFFFUL; - /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - - * Novell bug 204882 + along with lots of ubuntu ones */ + /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - + * Novell bug 204882 + along with lots of ubuntu ones + */ if (config_aper_size > rdev->mc.real_vram_size) rdev->mc.mc_vram_size = config_aper_size; else rdev->mc.mc_vram_size = rdev->mc.real_vram_size; } - - /* work out accessible VRAM */ - accessible = r100_get_accessible_vram(rdev); - - rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); - rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); - - if (accessible > rdev->mc.aper_size) - accessible = rdev->mc.aper_size; - - if (rdev->mc.mc_vram_size > rdev->mc.aper_size) + /* FIXME remove this once we support unmappable VRAM */ + if (rdev->mc.mc_vram_size > rdev->mc.aper_size) { rdev->mc.mc_vram_size = rdev->mc.aper_size; - - if (rdev->mc.real_vram_size > rdev->mc.aper_size) rdev->mc.real_vram_size = rdev->mc.aper_size; + } } void r100_vga_set_state(struct radeon_device *rdev, bool state) @@ -2019,11 +2007,18 @@ void r100_vga_set_state(struct radeon_device *rdev, bool state) WREG32(RADEON_CONFIG_CNTL, temp); } -void r100_vram_info(struct radeon_device *rdev) +void r100_mc_init(struct radeon_device *rdev) { - r100_vram_get_type(rdev); + u64 base; + r100_vram_get_type(rdev); r100_vram_init_sizes(rdev); + base = rdev->mc.aper_base; + if (rdev->flags & RADEON_IS_IGP) + base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; + radeon_vram_location(rdev, &rdev->mc, base); + if (!(rdev->flags & RADEON_IS_AGP)) + radeon_gtt_location(rdev, &rdev->mc); } @@ -3294,10 +3289,9 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) { /* Update base address for crtc */ - WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location); + WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); if (!(rdev->flags & RADEON_SINGLE_CRTC)) { - WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, - rdev->mc.vram_location); + WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); } /* Restore CRTC registers */ WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); @@ -3458,32 +3452,6 @@ void r100_fini(struct radeon_device *rdev) rdev->bios = NULL; } -int r100_mc_init(struct radeon_device *rdev) -{ - int r; - u32 tmp; - - /* Setup GPU memory space */ - rdev->mc.vram_location = 0xFFFFFFFFUL; - rdev->mc.gtt_location = 0xFFFFFFFFUL; - if (rdev->flags & RADEON_IS_IGP) { - tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM)); - rdev->mc.vram_location = tmp << 16; - } - if (rdev->flags & RADEON_IS_AGP) { - r = radeon_agp_init(rdev); - if (r) { - radeon_agp_disable(rdev); - } else { - rdev->mc.gtt_location = rdev->mc.agp_base; - } - } - r = radeon_mc_setup(rdev); - if (r) - return r; - return 0; -} - int r100_init(struct radeon_device *rdev) { int r; @@ -3526,12 +3494,15 @@ int r100_init(struct radeon_device *rdev) radeon_get_clock_info(rdev->ddev); /* Initialize power management */ radeon_pm_init(rdev); - /* Get vram informations */ - r100_vram_info(rdev); - /* Initialize memory controller (also test AGP) */ - r = r100_mc_init(rdev); - if (r) - return r; + /* initialize AGP */ + if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) { + radeon_agp_disable(rdev); + } + } + /* initialize VRAM */ + r100_mc_init(rdev); /* Fence driver */ r = radeon_fence_driver_init(rdev); if (r) diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index a4f395226b34..7e9f95653cbe 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -121,15 +121,15 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev) /* discard memory request outside of configured range */ tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); - WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location); - tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE; + WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); + tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); table_addr = rdev->gart.table_addr; WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); /* FIXME: setup default page */ - WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location); + WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); /* Clear error */ WREG32_PCIE(0x18, 0); @@ -459,13 +459,12 @@ int r300_gpu_reset(struct radeon_device *rdev) /* * r300,r350,rv350,rv380 VRAM info */ -void r300_vram_info(struct radeon_device *rdev) +void r300_mc_init(struct radeon_device *rdev) { uint32_t tmp; /* DDR for all card after R300 & IGP */ rdev->mc.vram_is_ddr = true; - tmp = RREG32(RADEON_MEM_CNTL); tmp &= R300_MEM_NUM_CHANNELS_MASK; switch (tmp) { @@ -474,8 +473,9 @@ void r300_vram_info(struct radeon_device *rdev) case 2: rdev->mc.vram_width = 256; break; default: rdev->mc.vram_width = 128; break; } - r100_vram_init_sizes(rdev); + if (!(rdev->flags & RADEON_IS_AGP)) + radeon_gtt_location(rdev, &rdev->mc); } void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) @@ -1377,12 +1377,15 @@ int r300_init(struct radeon_device *rdev) radeon_get_clock_info(rdev->ddev); /* Initialize power management */ radeon_pm_init(rdev); - /* Get vram informations */ - r300_vram_info(rdev); - /* Initialize memory controller (also test AGP) */ - r = r420_mc_init(rdev); - if (r) - return r; + /* initialize AGP */ + if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) { + radeon_agp_disable(rdev); + } + } + /* initialize memory controller */ + r300_mc_init(rdev); /* Fence driver */ r = radeon_fence_driver_init(rdev); if (r) diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index 12ebbdb83d1c..c7593b8f58ee 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c @@ -40,28 +40,6 @@ static void r420_set_reg_safe(struct radeon_device *rdev) rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); } -int r420_mc_init(struct radeon_device *rdev) -{ - int r; - - /* Setup GPU memory space */ - rdev->mc.vram_location = 0xFFFFFFFFUL; - rdev->mc.gtt_location = 0xFFFFFFFFUL; - if (rdev->flags & RADEON_IS_AGP) { - r = radeon_agp_init(rdev); - if (r) { - radeon_agp_disable(rdev); - } else { - rdev->mc.gtt_location = rdev->mc.agp_base; - } - } - r = radeon_mc_setup(rdev); - if (r) { - return r; - } - return 0; -} - void r420_pipes_init(struct radeon_device *rdev) { unsigned tmp; @@ -349,13 +327,15 @@ int r420_init(struct radeon_device *rdev) radeon_get_clock_info(rdev->ddev); /* Initialize power management */ radeon_pm_init(rdev); - /* Get vram informations */ - r300_vram_info(rdev); - /* Initialize memory controller (also test AGP) */ - r = r420_mc_init(rdev); - if (r) { - return r; + /* initialize AGP */ + if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) { + radeon_agp_disable(rdev); + } } + /* initialize memory controller */ + r300_mc_init(rdev); r420_debugfs(rdev); /* Fence driver */ r = radeon_fence_driver_init(rdev); diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c index ddf5731eba0d..2b8a5dd13516 100644 --- a/drivers/gpu/drm/radeon/r520.c +++ b/drivers/gpu/drm/radeon/r520.c @@ -119,13 +119,15 @@ static void r520_vram_get_type(struct radeon_device *rdev) rdev->mc.vram_width *= 2; } -void r520_vram_info(struct radeon_device *rdev) +void r520_mc_init(struct radeon_device *rdev) { fixed20_12 a; r520_vram_get_type(rdev); - r100_vram_init_sizes(rdev); + radeon_vram_location(rdev, &rdev->mc, 0); + if (!(rdev->flags & RADEON_IS_AGP)) + radeon_gtt_location(rdev, &rdev->mc); /* FIXME: we should enforce default clock in case GPU is not in * default setup */ @@ -267,12 +269,15 @@ int r520_init(struct radeon_device *rdev) radeon_get_clock_info(rdev->ddev); /* Initialize power management */ radeon_pm_init(rdev); - /* Get vram informations */ - r520_vram_info(rdev); - /* Initialize memory controller (also test AGP) */ - r = r420_mc_init(rdev); - if (r) - return r; + /* initialize AGP */ + if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) { + radeon_agp_disable(rdev); + } + } + /* initialize memory controller */ + r520_mc_init(rdev); rv515_debugfs(rdev); /* Fence driver */ r = radeon_fence_driver_init(rdev); diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index a865946d2d08..694a4c564f52 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -611,6 +611,68 @@ static void r600_mc_program(struct radeon_device *rdev) rv515_vga_render_disable(rdev); } +/** + * r600_vram_gtt_location - try to find VRAM & GTT location + * @rdev: radeon device structure holding all necessary informations + * @mc: memory controller structure holding memory informations + * + * Function will place try to place VRAM at same place as in CPU (PCI) + * address space as some GPU seems to have issue when we reprogram at + * different address space. + * + * If there is not enough space to fit the unvisible VRAM after the + * aperture then we limit the VRAM size to the aperture. + * + * If we are using AGP then place VRAM adjacent to AGP aperture are we need + * them to be in one from GPU point of view so that we can program GPU to + * catch access outside them (weird GPU policy see ??). + * + * This function will never fails, worst case are limiting VRAM or GTT. + * + * Note: GTT start, end, size should be initialized before calling this + * function on AGP platform. + */ +void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) +{ + u64 size_bf, size_af; + + if (mc->mc_vram_size > 0xE0000000) { + /* leave room for at least 512M GTT */ + dev_warn(rdev->dev, "limiting VRAM\n"); + mc->real_vram_size = 0xE0000000; + mc->mc_vram_size = 0xE0000000; + } + if (rdev->flags & RADEON_IS_AGP) { + size_bf = mc->gtt_start; + size_af = 0xFFFFFFFF - mc->gtt_end + 1; + if (size_bf > size_af) { + if (mc->mc_vram_size > size_bf) { + dev_warn(rdev->dev, "limiting VRAM\n"); + mc->real_vram_size = size_bf; + mc->mc_vram_size = size_bf; + } + mc->vram_start = mc->gtt_start - mc->mc_vram_size; + } else { + if (mc->mc_vram_size > size_af) { + dev_warn(rdev->dev, "limiting VRAM\n"); + mc->real_vram_size = size_af; + mc->mc_vram_size = size_af; + } + mc->vram_start = mc->gtt_end; + } + mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; + dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", + mc->mc_vram_size >> 20, mc->vram_start, + mc->vram_end, mc->real_vram_size >> 20); + } else { + u64 base = 0; + if (rdev->flags & RADEON_IS_IGP) + base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; + radeon_vram_location(rdev, &rdev->mc, base); + radeon_gtt_location(rdev, mc); + } +} + int r600_mc_init(struct radeon_device *rdev) { fixed20_12 a; @@ -650,75 +712,20 @@ int r600_mc_init(struct radeon_device *rdev) /* Setup GPU memory space */ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); - - if (rdev->mc.mc_vram_size > rdev->mc.aper_size) + /* FIXME remove this once we support unmappable VRAM */ + if (rdev->mc.mc_vram_size > rdev->mc.aper_size) { rdev->mc.mc_vram_size = rdev->mc.aper_size; - - if (rdev->mc.real_vram_size > rdev->mc.aper_size) rdev->mc.real_vram_size = rdev->mc.aper_size; - - if (rdev->flags & RADEON_IS_AGP) { - /* gtt_size is setup by radeon_agp_init */ - rdev->mc.gtt_location = rdev->mc.agp_base; - tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; - /* Try to put vram before or after AGP because we - * we want SYSTEM_APERTURE to cover both VRAM and - * AGP so that GPU can catch out of VRAM/AGP access - */ - if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { - /* Enought place before */ - rdev->mc.vram_location = rdev->mc.gtt_location - - rdev->mc.mc_vram_size; - } else if (tmp > rdev->mc.mc_vram_size) { - /* Enought place after */ - rdev->mc.vram_location = rdev->mc.gtt_location + - rdev->mc.gtt_size; - } else { - /* Try to setup VRAM then AGP might not - * not work on some card - */ - rdev->mc.vram_location = 0x00000000UL; - rdev->mc.gtt_location = rdev->mc.mc_vram_size; - } - } else { - rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; - rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) & - 0xFFFF) << 24; - tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; - if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { - /* Enough place after vram */ - rdev->mc.gtt_location = tmp; - } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) { - /* Enough place before vram */ - rdev->mc.gtt_location = 0; - } else { - /* Not enough place after or before shrink - * gart size - */ - if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) { - rdev->mc.gtt_location = 0; - rdev->mc.gtt_size = rdev->mc.vram_location; - } else { - rdev->mc.gtt_location = tmp; - rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp; - } - } - rdev->mc.gtt_location = rdev->mc.mc_vram_size; } - rdev->mc.vram_start = rdev->mc.vram_location; - rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; - rdev->mc.gtt_start = rdev->mc.gtt_location; - rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; + r600_vram_gtt_location(rdev, &rdev->mc); /* FIXME: we should enforce default clock in case GPU is not in * default setup */ a.full = rfixed_const(100); rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); - if (rdev->flags & RADEON_IS_IGP) rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); - return 0; } diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 350ae71953e9..0ca83ca91111 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -282,6 +282,7 @@ union radeon_gart_table { }; #define RADEON_GPU_PAGE_SIZE 4096 +#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) struct radeon_gart { dma_addr_t table_addr; @@ -316,21 +317,19 @@ struct radeon_mc { /* for some chips with <= 32MB we need to lie * about vram size near mc fb location */ u64 mc_vram_size; - u64 gtt_location; + u64 visible_vram_size; u64 gtt_size; u64 gtt_start; u64 gtt_end; - u64 vram_location; u64 vram_start; u64 vram_end; unsigned vram_width; u64 real_vram_size; int vram_mtrr; bool vram_is_ddr; - bool igp_sideport_enabled; + bool igp_sideport_enabled; }; -int radeon_mc_setup(struct radeon_device *rdev); bool radeon_combios_sideport_present(struct radeon_device *rdev); bool radeon_atombios_sideport_present(struct radeon_device *rdev); @@ -1165,6 +1164,8 @@ extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enabl extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); +extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); +extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ struct r100_mc_save { @@ -1219,7 +1220,7 @@ extern void r200_set_safe_registers(struct radeon_device *rdev); /* r300,r350,rv350,rv370,rv380 */ extern void r300_set_reg_safe(struct radeon_device *rdev); extern void r300_mc_program(struct radeon_device *rdev); -extern void r300_vram_info(struct radeon_device *rdev); +extern void r300_mc_init(struct radeon_device *rdev); extern void r300_clock_startup(struct radeon_device *rdev); extern int r300_mc_wait_for_idle(struct radeon_device *rdev); extern int rv370_pcie_gart_init(struct radeon_device *rdev); @@ -1228,7 +1229,6 @@ extern int rv370_pcie_gart_enable(struct radeon_device *rdev); extern void rv370_pcie_gart_disable(struct radeon_device *rdev); /* r420,r423,rv410 */ -extern int r420_mc_init(struct radeon_device *rdev); extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); @@ -1270,6 +1270,7 @@ extern void rs690_line_buffer_adjust(struct radeon_device *rdev, struct drm_display_mode *mode2); /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ +extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); extern bool r600_card_posted(struct radeon_device *rdev); extern void r600_cp_stop(struct radeon_device *rdev); extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c index c0681a5556dc..c4457791dff1 100644 --- a/drivers/gpu/drm/radeon/radeon_agp.c +++ b/drivers/gpu/drm/radeon/radeon_agp.c @@ -237,6 +237,10 @@ int radeon_agp_init(struct radeon_device *rdev) rdev->mc.agp_base = rdev->ddev->agp->agp_info.aper_base; rdev->mc.gtt_size = rdev->ddev->agp->agp_info.aper_size << 20; + rdev->mc.gtt_start = rdev->mc.agp_base; + rdev->mc.gtt_end = rdev->mc.gtt_start + rdev->mc.gtt_size - 1; + dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", + rdev->mc.gtt_size >> 20, rdev->mc.gtt_start, rdev->mc.gtt_end); /* workaround some hw issues */ if (rdev->family < CHIP_R200) { diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 7be3a6968463..91a9b966238e 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -100,80 +100,103 @@ void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) } } -/* - * MC common functions +/** + * radeon_vram_location - try to find VRAM location + * @rdev: radeon device structure holding all necessary informations + * @mc: memory controller structure holding memory informations + * @base: base address at which to put VRAM + * + * Function will place try to place VRAM at base address provided + * as parameter (which is so far either PCI aperture address or + * for IGP TOM base address). + * + * If there is not enough space to fit the unvisible VRAM in the 32bits + * address space then we limit the VRAM size to the aperture. + * + * If we are using AGP and if the AGP aperture doesn't allow us to have + * room for all the VRAM than we restrict the VRAM to the PCI aperture + * size and print a warning. + * + * This function will never fails, worst case are limiting VRAM. + * + * Note: GTT start, end, size should be initialized before calling this + * function on AGP platform. + * + * Note: We don't explictly enforce VRAM start to be aligned on VRAM size, + * this shouldn't be a problem as we are using the PCI aperture as a reference. + * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but + * not IGP. + * + * Note: we use mc_vram_size as on some board we need to program the mc to + * cover the whole aperture even if VRAM size is inferior to aperture size + * Novell bug 204882 + along with lots of ubuntu ones + * + * Note: when limiting vram it's safe to overwritte real_vram_size because + * we are not in case where real_vram_size is inferior to mc_vram_size (ie + * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu + * ones) + * + * Note: IGP TOM addr should be the same as the aperture addr, we don't + * explicitly check for that thought. + * + * FIXME: when reducing VRAM size align new size on power of 2. */ -int radeon_mc_setup(struct radeon_device *rdev) +void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) +{ + mc->vram_start = base; + if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { + dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); + mc->real_vram_size = mc->aper_size; + mc->mc_vram_size = mc->aper_size; + } + mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; + if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) { + dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); + mc->real_vram_size = mc->aper_size; + mc->mc_vram_size = mc->aper_size; + } + mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; + dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", + mc->mc_vram_size >> 20, mc->vram_start, + mc->vram_end, mc->real_vram_size >> 20); +} + +/** + * radeon_gtt_location - try to find GTT location + * @rdev: radeon device structure holding all necessary informations + * @mc: memory controller structure holding memory informations + * + * Function will place try to place GTT before or after VRAM. + * + * If GTT size is bigger than space left then we ajust GTT size. + * Thus function will never fails. + * + * FIXME: when reducing GTT size align new size on power of 2. + */ +void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) { - uint32_t tmp; + u64 size_af, size_bf; - /* Some chips have an "issue" with the memory controller, the - * location must be aligned to the size. We just align it down, - * too bad if we walk over the top of system memory, we don't - * use DMA without a remapped anyway. - * Affected chips are rv280, all r3xx, and all r4xx, but not IGP - */ - /* FGLRX seems to setup like this, VRAM a 0, then GART. - */ - /* - * Note: from R6xx the address space is 40bits but here we only - * use 32bits (still have to see a card which would exhaust 4G - * address space). - */ - if (rdev->mc.vram_location != 0xFFFFFFFFUL) { - /* vram location was already setup try to put gtt after - * if it fits */ - tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; - tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); - if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { - rdev->mc.gtt_location = tmp; - } else { - if (rdev->mc.gtt_size >= rdev->mc.vram_location) { - printk(KERN_ERR "[drm] GTT too big to fit " - "before or after vram location.\n"); - return -EINVAL; - } - rdev->mc.gtt_location = 0; - } - } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { - /* gtt location was already setup try to put vram before - * if it fits */ - if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) { - rdev->mc.vram_location = 0; - } else { - tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; - tmp += (rdev->mc.mc_vram_size - 1); - tmp &= ~(rdev->mc.mc_vram_size - 1); - if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) { - rdev->mc.vram_location = tmp; - } else { - printk(KERN_ERR "[drm] vram too big to fit " - "before or after GTT location.\n"); - return -EINVAL; - } + size_af = 0xFFFFFFFF - mc->vram_end; + size_bf = mc->vram_start; + if (size_bf > size_af) { + if (mc->gtt_size > size_bf) { + dev_warn(rdev->dev, "limiting GTT\n"); + mc->gtt_size = size_bf; } + mc->gtt_start = mc->vram_start - mc->gtt_size; } else { - rdev->mc.vram_location = 0; - tmp = rdev->mc.mc_vram_size; - tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); - rdev->mc.gtt_location = tmp; - } - rdev->mc.vram_start = rdev->mc.vram_location; - rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; - rdev->mc.gtt_start = rdev->mc.gtt_location; - rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; - DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20)); - DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", - (unsigned)rdev->mc.vram_location, - (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1)); - DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20)); - DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", - (unsigned)rdev->mc.gtt_location, - (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1)); - return 0; + if (mc->gtt_size > size_af) { + dev_warn(rdev->dev, "limiting GTT\n"); + mc->gtt_size = size_af; + } + mc->gtt_start = mc->vram_end + 1; + } + mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; + dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", + mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); } - /* * GPU helpers function. */ diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index 105c678fa73a..c39ddda13840 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -252,7 +252,7 @@ int radeonfb_create(struct drm_device *dev, info->flags = FBINFO_DEFAULT; info->fbops = &radeonfb_ops; - tmp = fb_gpuaddr - rdev->mc.vram_location; + tmp = fb_gpuaddr - rdev->mc.vram_start; info->fix.smem_start = rdev->mc.aper_base + tmp; info->fix.smem_len = size; info->screen_base = fbptr; diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index 83d4dbd6d067..643251719f1c 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c @@ -403,7 +403,7 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, /* if scanout was in GTT this really wouldn't work */ /* crtc offset is from display base addr not FB location */ - radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location; + radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; base -= radeon_crtc->legacy_display_base_addr; diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c index 9f5e2f929da9..313c96bc09da 100644 --- a/drivers/gpu/drm/radeon/radeon_test.c +++ b/drivers/gpu/drm/radeon/radeon_test.c @@ -186,7 +186,7 @@ void radeon_test_moves(struct radeon_device *rdev) radeon_bo_kunmap(gtt_obj[i]); DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n", - gtt_addr - rdev->mc.gtt_location); + gtt_addr - rdev->mc.gtt_start); } out_cleanup: diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index db820ae9a034..1157e0f758fa 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -150,7 +150,7 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, man->default_caching = TTM_PL_FLAG_CACHED; break; case TTM_PL_TT: - man->gpu_offset = rdev->mc.gtt_location; + man->gpu_offset = rdev->mc.gtt_start; man->available_caching = TTM_PL_MASK_CACHING; man->default_caching = TTM_PL_FLAG_CACHED; man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; @@ -180,7 +180,7 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, break; case TTM_PL_VRAM: /* "On-card" video ram */ - man->gpu_offset = rdev->mc.vram_location; + man->gpu_offset = rdev->mc.vram_start; man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_NEEDS_IOREMAP | TTM_MEMTYPE_FLAG_MAPPABLE; @@ -262,10 +262,10 @@ static int radeon_move_blit(struct ttm_buffer_object *bo, switch (old_mem->mem_type) { case TTM_PL_VRAM: - old_start += rdev->mc.vram_location; + old_start += rdev->mc.vram_start; break; case TTM_PL_TT: - old_start += rdev->mc.gtt_location; + old_start += rdev->mc.gtt_start; break; default: DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); @@ -273,10 +273,10 @@ static int radeon_move_blit(struct ttm_buffer_object *bo, } switch (new_mem->mem_type) { case TTM_PL_VRAM: - new_start += rdev->mc.vram_location; + new_start += rdev->mc.vram_start; break; case TTM_PL_TT: - new_start += rdev->mc.gtt_location; + new_start += rdev->mc.gtt_start; break; default: DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c index 1e4582e27c14..626d51891ee9 100644 --- a/drivers/gpu/drm/radeon/rs400.c +++ b/drivers/gpu/drm/radeon/rs400.c @@ -151,9 +151,8 @@ int rs400_gart_enable(struct radeon_device *rdev) WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); WREG32(RS480_AGP_BASE_2, 0); } - tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; - tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16); - tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16); + tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); + tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; @@ -252,14 +251,19 @@ void rs400_gpu_init(struct radeon_device *rdev) } } -void rs400_vram_info(struct radeon_device *rdev) +void rs400_mc_init(struct radeon_device *rdev) { + u64 base; + rs400_gart_adjust_size(rdev); + rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); /* DDR for all card after R300 & IGP */ rdev->mc.vram_is_ddr = true; rdev->mc.vram_width = 128; - r100_vram_init_sizes(rdev); + base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; + radeon_vram_location(rdev, &rdev->mc, base); + radeon_gtt_location(rdev, &rdev->mc); } uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) @@ -363,22 +367,6 @@ static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) #endif } -static int rs400_mc_init(struct radeon_device *rdev) -{ - int r; - u32 tmp; - - /* Setup GPU memory space */ - tmp = RREG32(R_00015C_NB_TOM); - rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16; - rdev->mc.gtt_location = 0xFFFFFFFFUL; - r = radeon_mc_setup(rdev); - rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); - if (r) - return r; - return 0; -} - void rs400_mc_program(struct radeon_device *rdev) { struct r100_mc_save save; @@ -517,12 +505,8 @@ int rs400_init(struct radeon_device *rdev) radeon_get_clock_info(rdev->ddev); /* Initialize power management */ radeon_pm_init(rdev); - /* Get vram informations */ - rs400_vram_info(rdev); - /* Initialize memory controller (also test AGP) */ - r = rs400_mc_init(rdev); - if (r) - return r; + /* initialize memory controller */ + rs400_mc_init(rdev); /* Fence driver */ r = radeon_fence_driver_init(rdev); if (r) diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index 28c8690c7a35..d5aeb2a31d59 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c @@ -45,23 +45,6 @@ void rs600_gpu_init(struct radeon_device *rdev); int rs600_mc_wait_for_idle(struct radeon_device *rdev); -int rs600_mc_init(struct radeon_device *rdev) -{ - /* read back the MC value from the hw */ - int r; - u32 tmp; - - /* Setup GPU memory space */ - tmp = RREG32_MC(R_000004_MC_FB_LOCATION); - rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16; - rdev->mc.gtt_location = 0xffffffffUL; - r = radeon_mc_setup(rdev); - rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); - if (r) - return r; - return 0; -} - /* hpd for digital panel detect/disconnect */ bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) { @@ -475,22 +458,21 @@ void rs600_gpu_init(struct radeon_device *rdev) dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); } -void rs600_vram_info(struct radeon_device *rdev) +void rs600_mc_init(struct radeon_device *rdev) { + u64 base; + rdev->mc.vram_is_ddr = true; rdev->mc.vram_width = 128; - rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); rdev->mc.mc_vram_size = rdev->mc.real_vram_size; - rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); - - if (rdev->mc.mc_vram_size > rdev->mc.aper_size) - rdev->mc.mc_vram_size = rdev->mc.aper_size; - - if (rdev->mc.real_vram_size > rdev->mc.aper_size) - rdev->mc.real_vram_size = rdev->mc.aper_size; + rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); + base = RREG32_MC(R_000004_MC_FB_LOCATION); + base = G_000004_MC_FB_START(base) << 16; + radeon_vram_location(rdev, &rdev->mc, base); + radeon_gtt_location(rdev, &rdev->mc); } void rs600_bandwidth_update(struct radeon_device *rdev) @@ -666,12 +648,8 @@ int rs600_init(struct radeon_device *rdev) radeon_get_clock_info(rdev->ddev); /* Initialize power management */ radeon_pm_init(rdev); - /* Get vram informations */ - rs600_vram_info(rdev); - /* Initialize memory controller (also test AGP) */ - r = rs600_mc_init(rdev); - if (r) - return r; + /* initialize memory controller */ + rs600_mc_init(rdev); rs600_debugfs(rdev); /* Fence driver */ r = radeon_fence_driver_init(rdev); diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index 06e2771aee5a..8d37501da7df 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c @@ -129,27 +129,20 @@ void rs690_pm_info(struct radeon_device *rdev) rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp); } -void rs690_vram_info(struct radeon_device *rdev) +void rs690_mc_init(struct radeon_device *rdev) { fixed20_12 a; + u64 base; rs400_gart_adjust_size(rdev); - rdev->mc.vram_is_ddr = true; rdev->mc.vram_width = 128; - rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); rdev->mc.mc_vram_size = rdev->mc.real_vram_size; - rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); - - if (rdev->mc.mc_vram_size > rdev->mc.aper_size) - rdev->mc.mc_vram_size = rdev->mc.aper_size; - - if (rdev->mc.real_vram_size > rdev->mc.aper_size) - rdev->mc.real_vram_size = rdev->mc.aper_size; - + base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); + base = G_000100_MC_FB_START(base) << 16; rs690_pm_info(rdev); /* FIXME: we should enforce default clock in case GPU is not in * default setup @@ -160,22 +153,9 @@ void rs690_vram_info(struct radeon_device *rdev) a.full = rfixed_const(16); /* core_bandwidth = sclk(Mhz) * 16 */ rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a); -} - -static int rs690_mc_init(struct radeon_device *rdev) -{ - int r; - u32 tmp; - - /* Setup GPU memory space */ - tmp = RREG32_MC(R_000100_MCCFG_FB_LOCATION); - rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16; - rdev->mc.gtt_location = 0xFFFFFFFFUL; - r = radeon_mc_setup(rdev); rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); - if (r) - return r; - return 0; + radeon_vram_location(rdev, &rdev->mc, base); + radeon_gtt_location(rdev, &rdev->mc); } void rs690_line_buffer_adjust(struct radeon_device *rdev, @@ -728,12 +708,8 @@ int rs690_init(struct radeon_device *rdev) radeon_get_clock_info(rdev->ddev); /* Initialize power management */ radeon_pm_init(rdev); - /* Get vram informations */ - rs690_vram_info(rdev); - /* Initialize memory controller (also test AGP) */ - r = rs690_mc_init(rdev); - if (r) - return r; + /* initialize memory controller */ + rs690_mc_init(rdev); rv515_debugfs(rdev); /* Fence driver */ r = radeon_fence_driver_init(rdev); diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 0e1e6b8632b8..bea747da123f 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c @@ -277,13 +277,15 @@ static void rv515_vram_get_type(struct radeon_device *rdev) } } -void rv515_vram_info(struct radeon_device *rdev) +void rv515_mc_init(struct radeon_device *rdev) { fixed20_12 a; rv515_vram_get_type(rdev); - r100_vram_init_sizes(rdev); + radeon_vram_location(rdev, &rdev->mc, 0); + if (!(rdev->flags & RADEON_IS_AGP)) + radeon_gtt_location(rdev, &rdev->mc); /* FIXME: we should enforce default clock in case GPU is not in * default setup */ @@ -587,12 +589,15 @@ int rv515_init(struct radeon_device *rdev) radeon_get_clock_info(rdev->ddev); /* Initialize power management */ radeon_pm_init(rdev); - /* Get vram informations */ - rv515_vram_info(rdev); - /* Initialize memory controller (also test AGP) */ - r = r420_mc_init(rdev); - if (r) - return r; + /* initialize AGP */ + if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) { + radeon_agp_disable(rdev); + } + } + /* initialize memory controller */ + rv515_mc_init(rdev); rv515_debugfs(rdev); /* Fence driver */ r = radeon_fence_driver_init(rdev); diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 6f1f4abbe88c..323fa6be5082 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -820,45 +820,12 @@ int rv770_mc_init(struct radeon_device *rdev) /* Setup GPU memory space */ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); - - if (rdev->mc.mc_vram_size > rdev->mc.aper_size) + /* FIXME remove this once we support unmappable VRAM */ + if (rdev->mc.mc_vram_size > rdev->mc.aper_size) { rdev->mc.mc_vram_size = rdev->mc.aper_size; - - if (rdev->mc.real_vram_size > rdev->mc.aper_size) rdev->mc.real_vram_size = rdev->mc.aper_size; - - if (rdev->flags & RADEON_IS_AGP) { - /* gtt_size is setup by radeon_agp_init */ - rdev->mc.gtt_location = rdev->mc.agp_base; - tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; - /* Try to put vram before or after AGP because we - * we want SYSTEM_APERTURE to cover both VRAM and - * AGP so that GPU can catch out of VRAM/AGP access - */ - if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { - /* Enought place before */ - rdev->mc.vram_location = rdev->mc.gtt_location - - rdev->mc.mc_vram_size; - } else if (tmp > rdev->mc.mc_vram_size) { - /* Enought place after */ - rdev->mc.vram_location = rdev->mc.gtt_location + - rdev->mc.gtt_size; - } else { - /* Try to setup VRAM then AGP might not - * not work on some card - */ - rdev->mc.vram_location = 0x00000000UL; - rdev->mc.gtt_location = rdev->mc.mc_vram_size; - } - } else { - rdev->mc.vram_location = 0x00000000UL; - rdev->mc.gtt_location = rdev->mc.mc_vram_size; - rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; } - rdev->mc.vram_start = rdev->mc.vram_location; - rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; - rdev->mc.gtt_start = rdev->mc.gtt_location; - rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; + r600_vram_gtt_location(rdev, &rdev->mc); /* FIXME: we should enforce default clock in case GPU is not in * default setup */ @@ -867,6 +834,7 @@ int rv770_mc_init(struct radeon_device *rdev) rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); return 0; } + int rv770_gpu_reset(struct radeon_device *rdev) { /* FIXME: implement any rv770 specific bits */ @@ -1042,6 +1010,7 @@ int rv770_init(struct radeon_device *rdev) r = radeon_fence_driver_init(rdev); if (r) return r; + /* initialize AGP */ if (rdev->flags & RADEON_IS_AGP) { r = radeon_agp_init(rdev); if (r) -- cgit v1.2.3 From f601441916d1e19291d0b4f044b4a7551e2924d0 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Wed, 17 Feb 2010 12:33:23 +0200 Subject: imxfb: add support for i.MX25 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The commit also introduces the HAVE_FB_IMX config that is to be selected from the MX25 platform config. Once this commit gets merged, the two other i.MX archs, ARCH_MX1 and ARCH_MX2, should follow this one. Signed-off-by: Baruch Siach Acked-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/Kconfig | 1 + drivers/video/Kconfig | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index cea51a0ae9f7..cdee9176a775 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -24,6 +24,7 @@ config ARCH_MX25 bool "MX25-based" select CPU_ARM926T select COMMON_CLKDEV + select HAVE_FB_IMX help This enables support for systems based on the Freescale i.MX25 family diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 5a5c303a6373..83d40ed2f2d6 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -400,9 +400,12 @@ config FB_SA1100 If you plan to use the LCD display with your SA-1100 system, say Y here. +config HAVE_FB_IMX + bool + config FB_IMX tristate "Motorola i.MX LCD support" - depends on FB && (ARCH_MX1 || ARCH_MX2) + depends on FB && (HAVE_FB_IMX || ARCH_MX1 || ARCH_MX2) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT -- cgit v1.2.3 From 1ef8a5be834117fa54db6cb595fc2d45c14a38cf Mon Sep 17 00:00:00 2001 From: Jonathan Corbet Date: Thu, 18 Feb 2010 09:52:00 -0700 Subject: Remove drivers/char/ChangeLog The ChangeLog file under drivers/char is 30K of stuff dedicated to the mid-90's TTY exploits of Ted Ts'o; it has been updated once since 1998 - and that was in 2001. It's interesting history, but we don't normally carry that kind of history inline with the code. Let's remove it. Signed-off-by: Jonathan Corbet Acked-by: Alan Cox Acked-by: "Theodore Ts'o" Signed-off-by: Jiri Kosina --- drivers/char/ChangeLog | 775 ------------------------------------------------- 1 file changed, 775 deletions(-) delete mode 100644 drivers/char/ChangeLog (limited to 'drivers') diff --git a/drivers/char/ChangeLog b/drivers/char/ChangeLog deleted file mode 100644 index 56b8a2e76ab1..000000000000 --- a/drivers/char/ChangeLog +++ /dev/null @@ -1,775 +0,0 @@ -2001-08-11 Tim Waugh - - * serial.c (get_pci_port): Deal with awkward Titan cards. - -1998-08-26 Theodore Ts'o - - * serial.c (rs_open): Correctly decrement the module in-use count - on errors. - -Thu Feb 19 14:24:08 1998 Theodore Ts'o - - * tty_io.c (tty_name): Remove the non-reentrant (and non-SMP safe) - version of tty_name, and rename the reentrant _tty_name - function to be tty_name. - (tty_open): Add a warning message stating callout devices - are deprecated. - -Mon Dec 1 08:24:15 1997 Theodore Ts'o - - * tty_io.c (tty_get_baud_rate): Print a warning syslog if the - tty->alt_speed kludge is used; this means the system is - using the deprecated SPD_HI ioctls. - -Mon Nov 24 10:37:49 1997 Theodore Ts'o - - * serial.c, esp.c, rocket.c: Change drivers to take advantage of - tty_get_baud_rate(). - - * tty_io.c (tty_get_baud_rate): New function which computes the - correct baud rate for the tty. More factoring out of - common code out of the serial driver to the high-level tty - functions.... - -Sat Nov 22 07:53:36 1997 Theodore Ts'o - - * serial.c, esp.c, rocket.c: Add tty->driver.break() routine, and - allow high-level tty code to handle the break and soft - carrier ioctls. - - * tty_ioctl.c (n_tty_ioctl): Support TIOCGSOFTCAR and - TIOCSSOFTCAR, so that device drivers don't have to support - it. - - * serial.c (autoconfig): Change 16750 test to hopefully eliminate - false results by people with strange 16550As being - detected as 16750s. Hopefully 16750s will still be - detected as 16750, and other weird UARTs won't get poorly - autodetected. If this doesn't work, I'll have to disable - the auto identification for the 16750. - - * tty_io.c (tty_hangup): Now actually do the tty hangup - processing during the timer processing, and disable - interrupts while doing the hangup processing. This avoids - several nasty race conditions which happened when the - hangup processing was done asynchronously. - (tty_ioctl): Do break handling in the tty driver if - driver's break function is supported. - (tty_flip_buffer_push): New exported function which should - be used by drivers to push characters in the flip buffer - to the tty handler. This may either be done using a task - queue function for better CPU efficiency, or directly for - low latency operation. - - * serial.c (rs_set_termios): Fix bug rs_set_termios when - transitioning away from B0, submitted by Stanislav - Voronyi. - -Thu Jun 19 20:05:58 1997 Theodore Ts'o - - * serial.c (begin_break, end_break, rs_ioctl): Applied patch - to support BSD ioctls to set and clear the break - condition explicitly. - - * console.c (scrup, scrdown, insert_line, delete_line): Applied - fix suggested by Aaron Tiensivu to speed up block scrolls - up and down. - - * n_tty.c (opost_block, write_chan): Added a modified "fast - console" patch which processes a block of text via - "cooking" efficiently. - -Wed Jun 18 15:25:50 1997 Theodore Ts'o - - * tty_io.c (init_dev, release_dev): Applied fix suggested by Bill - Hawes to prevent race conditions in the tty code. - - * n_tty.c (n_tty_chars_in_buffer): Applied fix suggested by Bill - Hawes so that n_tty_chars_in_buffer returns the correct - value in the case when the tty is in cannonical mode. (To - avoid a pty deadlock with telnetd.) - -Thu Feb 27 01:53:08 1997 Theodore Ts'o - - * serial.c (change_speed): Add support for the termios flag - CMSPAR, which allows the user to select stick parity. - (i.e, if PARODD is set, the parity bit is always 1; if - PARRODD is not set, then the parity bit is always 0). - -Wed Feb 26 19:03:10 1997 Theodore Ts'o - - * serial.c (cleanup_module): Fix memory leak when using the serial - driver as a module; make sure tmp_buf gets freed! - -Tue Feb 25 11:01:59 1997 Theodore Ts'o - - * serial.c (set_modem_info): Add support for setting and clearing - the OUT1 and OUT2 bits. (For special case UART's, usually - for half-duplex.) - (autoconfig, change_speed): Fix TI 16750 support. - -Sun Feb 16 00:14:43 1997 Theodore Ts'o - - * tty_io.c (release_dev): Add sanity check to make sure there are - no waiters on tty->read_wait or tty->write_wait. - - * serial.c (rs_init): Don't autoconfig a device if the I/O region - is already reserved. - - * serial.c (serial_proc_info): Add support for /proc/serial. - -Thu Feb 13 00:49:10 1997 Theodore Ts'o - - * serial.c (receive_chars): When the UART repotrs an overrun - condition, it does so with a valid character. Changed to - not throw away the valid character, but instead report the - overrun after the valid character. - - * serial.c: Added new #ifdef's for some of the advanced serial - driver features. A minimal driver that only supports COM - 1/2/3/4 without sharing serial interrupts only takes 17k; - the full driver takes 32k. - -Wed Feb 12 14:50:44 1997 Theodore Ts'o - - * vt.c: - * pty.c: - * tty_ioctl.c: - * serial.c: Update routines to use the new 2.1 memory access - routines. - -Wed Dec 4 07:51:52 1996 Theodore Ts'o - - * serial.c (change_speed): Use save_flags(); cli() and - restore_flags() in order to ensure we don't accidentally - turn on interrupts when starting up the port. - (startup): Move the insertion of serial structure into the - IRQ chain earlier into the startup processing. Interrupts - should be off this whole time, but we eventually will want - to reduce this window. - -Thu Nov 21 10:05:22 1996 Theodore Ts'o - - * tty_ioctl.c (tty_wait_until_sent): Always check the driver - wait_until_ready routine, even if there are no characters - in the xmit buffer. (There may be charactes in the device - FIFO.) - (n_tty_ioctl): Add new flag tty->flow_stopped which - indicates whether the tty is stopped due to a request by - the TCXONC ioctl (used by tcflow). If so, don't let an - incoming XOFF character restart the tty. The tty can only - be restarted by another TCXONC request. - - * tty_io.c (start_tty): Don't allow the tty to be restarted if - tty->flow_stopped is true. - - * n_tty.c (n_tty_receive_char): If tty->flow_stopped is true, and - IXANY is set, don't eat a character trying to restart the - tty. - - * serial.c (startup): Remove need for MCR_noint from the - async_struct structure. Only turn on DTR and RTS if the - baud rate is not zero. - (change_speed): More accurately calculate the timeout - value based on the word size. Move responsibility of - hangup when speed becomes B0 to rs_set_termios() - (set_serial_info): When changing the UART type set the - current xmit_fifo_size as well as the permanent - xmit_fifo_size. - (rs_ioctl): Fix TCSBRK (used by tcdrain) and TCSBRKP - ioctls to return EINTR if interrupted by a signal. - (rs_set_termios): If the baud rate changes to or from B0, - this function is now responsible for setting or clearing - DTR and RTS. DTR and RTS are only be changed on the - transition to or from the B0 state. - (rs_close): Wait for the characters to drain based on - info->timeout. At low baud rates (50 bps), it may take a - long time for the FIFO to completely drain out! - (rs_wait_until_sent): Fixed timeout handling. Now - releases control to the scheduler, but checks frequently - enough so that the function is sensitive enough to pass - the timing requirements of the NIST-PCTS. - (block_til_ready): When opening the device, don't turn on - DTR and RTS if the baud rate is B0. - -Thu Nov 14 00:06:09 1996 Theodore Ts'o - - * serial.c (autoconfig): Fix autoconfiguration problems; - info->flags wasn't getting initialized from the state - structure. Put in more paranoid test for the 16750. - -Fri Nov 8 20:19:50 1996 Theodore Ts'o - - * n_tty.c (n_tty_flush_buffer): Only call driver->unthrottle() if - the tty was previous throttled. - (n_tty_set_termios, write_chan): Add changes suggested by - Simon P. Allen to allow hardware cooking. - - * tty_ioctl.c (set_termios): If we get a signal while waiting for - the tty to drain, return -EINTR. - - * serial.c (change_speed): Add support for CREAD, as required by - POSIX. - -Sat Nov 2 20:43:10 1996 Theodore Ts'o - - * serial.c: Wholesale changes. Added support for the Startech - 16650 and 16650V2 chips. (WARNING: the new startech - 16650A may or may not work!) Added support for the - TI16750 (not yet tested). Split async_struct into a - transient part (async_struct) and a permanent part - (serial_state) which contains the configuration - information for the ports. Added new driver routines - wait_until_sent() and send_xchar() to help with POSIX - compliance. Added support for radio clocks which waggle - the carrier detect line (CONFIG_HARD_PPS). - - * tty_ioctl.c (tty_wait_until_sent): Added call to new driver - function tty->driver.wait_until_sent(), which returns when - the tty's device xmit buffers are drained. Needed for - full POSIX compliance. - - (send_prio_char): New function, called by the ioctl's - TCIOFF and TCION; uses the new driver call send_xchar(), - which will send the XON or XOFF character at high priority - (and even if tty output is stopped). - -Wed Jun 5 18:52:04 1996 Theodore Ts'o - - * pty.c (pty_close): When closing a pty, make sure packet mode is - cleared. - -Sun May 26 09:33:52 1996 Theodore Ts'o - - * vesa_blank.c (set_vesa_blanking): Add missing verify_area() call. - - * selection.c (set_selection): Add missing verify_area() call. - - * tty_io.c (tty_ioctl): Add missing verify_area() calls. - - * serial.c (rs_ioctl): Add missing verify_area() calls. - (rs_init): Allow initialization of serial driver - configuration from a module. - - * random.c (extract_entropy): Add missing verify_area call. - Don't limit number of characters returned to - 32,768. Extract entropy is now no longer a inlined - function. - - (random_read): Check return value in case extract_entropy - returns an error. - - (secure_tcp_sequence_number): New function which returns a - secure TCP sequence number. This is needed to prevent some - nasty TCP hijacking attacks. - - (init_std_data): Initialize using gettimeofday() instead of - struct timeval xtime. - - (fast_add_entropy_word, add_entropy_word): Rename the - inline function add_entropy_word() to - fast_add_entropy_word(). Make add_entropy_word() be the - non-inlined function which is used in non-timing critical - places, in order to save space. - - (initialize_benchmark, begin_benchmark, end_benchmark): New - functions defined when RANDOM_BENCHMARK is defined. They - allow us to benchmark the speed of the - add_timer_randomness() call. - - (int_ln, rotate_left): Add two new inline functions with - i386 optimized asm instructions. This speeds up the - critical add_entropy_word() and add_timer_randomness() - functions, which are called from interrupt handlers. - -Tue May 7 22:51:11 1996 - - * random.c (add_timer_randomness): Limit the amount randomness - that we estimate to 12 bits. (An arbitrary amount). - - (extract_entropy): To make it harder to analyze the hash - function, fold the hash function in half using XOR, and - use the folded result as the value to emit to the user. - Also, add timer randomness each pass through the - exact_entropy call, to increase the amount of unknown - values during the extraction process. - - (random_ioctl): Use IOR/IOW definitions to define the - ioctl values used by the /dev/random driver. Allow the - old ioctl values to be used for backwards compatibility - (for a limited amount of time). - -Wed Apr 24 14:02:04 1996 Theodore Ts'o - - * random.c (add_timer_randomness): Use 2nd derivative as well to - better estimate entropy. - - (rand_initialize): Explicitly initialize all the pointers - to NULL. (Clearing pointers using memset isn't portable.) - Initialize the random pool with OS-dependent data. - - (random_write): Add sanity checking to the arguments to - random_write(), so that bad arguments won't cause a kernel - SEGV. - - (random_read): Update the access time of the device inode - when you return data to the user. - - (random_ioctl): Wake up the random_wait channel when there - are only WAIT_INPUT_BITS available. Add more paranoia - checks to make sure entropy_count doesn't go beyond the - bounds of (0, POOLSIZE). Add a few missing verify_area - checks. Add support for the RNDCLEARPOOL ioctl, which - zaps the random pool. - - (add_timer_randomness): Wake up the random_wait - channel only when there are WAIT_INPUT_BITS available. - - (random_select): Allow a random refresh daemon process to - select on /dev/random for writing; wake up the daemon when - there are less than WAIT_OUTPUT_BITS bits of randomness - available. - -Tue Apr 23 22:56:07 1996 - - * tty_io.c (init_dev): Change return code when user attempts to - open master pty which is already open from EAGAIN to EIO, - to match with BSD expectations. EIO is more correct - anyway, since EAGAIN implies that retrying will be - successful --- which it might be.... Eventually!! - - * pty.c (pty_open, pty_close): Fix wait loop so that we don't - busy loop while waiting for the master side to open. - Fix tty opening/closing logic. TTY_SLAVE_CLOSED was - renamed to TTY_OTHER_CLOSED, so that the name is more - descriptive. Also fixed code so that the tty flag - actually works correctly now.... - -Mon Apr 1 10:22:01 1996 - - * serial.c (rs_close): Cleaned up modularization changes. - Remove code which forced line discipline back to N_TTY - this is done in the tty upper layers, and there's no - reason to do it here. (Making this change also - removed the requirement that the serial module access - the internal kernel symbol "ldiscs".) - - * tty_io.c (tty_init): Formally register a tty_driver entry for - /dev/tty (device 4, 0) and /dev/console (device 5, 0). - This guarantees that major device numbers 4 and 5 will be - reserved for the tty subsystem (as they have to be because - of /dev/tty and /dev/console). Removed tty_regdev, as - this interface is no longer necessary. - -Sun Mar 17 20:42:47 GMT 1996 - - * serial.c : modularisation (changes in linux/fs/device.c allow - kerneld to automatically load the serial module). - - * Makefile, Config.in : serial modularisation adds. - - * tty_io.c : tty_init_ctty used by to register "cua" driver just - for the /dev/tty device (5,0). Added tty_regdev. - - * serial.c (shutdown, rs_ioctl) : when port shuts down wakeup processes - waiting on delta_msr_wait. The TIOCMIWAIT ioctl returns EIO - if no change was done since the time of call. - -Sat Mar 16 14:33:13 1996 - - * tty_io.c (disassociate_ctty): If disassociate_ctty is called by - exit, do not perform an implicit vhangup on a pty. - -Fri Feb 9 14:15:47 1996 - - * serial.c (block_til_ready): Fixed another race condition which - happens if a hangup happens during the open. - -Wed Jan 10 10:08:00 1996 - - * serial.c (block_til_ready): Remove race condition which happened - if a hangup condition happened during the setup of the - UART, before rs_open() called block_til_ready(). This - caused the info->count counter to be erroneously - decremented. - - * serial.c (startup, rs_open): Remove race condition that could - cause a memory leak of one page. (Fortunately, both race - conditions were relatively rare in practice.) - -Tue Dec 5 13:21:27 1995 - - * serial.c (check_modem_status, rs_ioctl): Support the new - ioctl()'s TIOCGICOUNT, TIOCMIWAIT. These allow an - application program to wait on a modem serial register - status bit change, and to find out how many changes have - taken place for the MSR bits. - - (rs_write): Eliminate a race condition which is introduced - if it is necessary to wait for the semaphore. - -Sat Nov 4 17:14:45 1995 - - * tty_io.c (tty_init): Move registration of TTY_MAJOR and - TTY_AUX_MAJOR to the end, so that /proc/devices looks - prettier. - - * pty.c (pty_init): Use new major numbers for PTY master and slave - devices. This allow us to have more than 64 pty's. We - register the old pty devices for backwards compatibility. - Note that a system should either be using the old pty - devices or the new pty devices --- in general, it should - try to use both, since they map into the same pty table. - The old pty devices are strictly for backwards compatibility. - -Wed Oct 11 12:45:24 1995 - - * tty_io.c (disassociate_ctty): If disassociate_ctty is called by - exit, perform an implicit vhangup on the tty. - - * pty.c (pty_close): When the master pty is closed, send a hangup - to the slave pty. - (pty_open): Use the flag TTY_SLAVE_CLOSED to test to see - if there are any open slave ptys, instead of using - tty->link->count. The old method got confused if there - were processes that had hung-up file descriptors on the - slave tty. - -Tue May 2 00:53:25 1995 - - * tty_io.c (tty_set_ldisc): Wait until the output buffer is - drained before closing the old line discipline --- needed - in only one case: XON/XOFF processing. - - * n_tty.c (n_tty_close): Don't bother waiting until the output - driver is closed; in general, the line discipline - shouldn't care if the hardware is finished - transmitting before the line discipline terminates. - - * tty_io.c (release_dev): Shutdown the line discipline after - decrementing the tty count variable; but set the - TTY_CLOSING flag so that we know that this tty structure - isn't long for this world. - - * tty_io.c (init_dev): Add sanity code to check to see if - TTY_CLOSING is set on a tty structure; if so, something - bad has happened (probably a line discipline close blocked - when it shouldn't have; so do a kernel printk and then - return an error). - -Wed Apr 26 10:23:44 1995 Theodore Y. Ts'o - - * tty_io.c (release_dev): Try to shutdown the line discipline - *before* decrementing the tty count variable; this removes - a potential race condition which occurs when the line - discipline close blocks, and another process then tries - open the same serial port. - - * serial.c (rs_hangup): When hanging up, flush the output buffer - before shutting down the UART. Otherwise the line - discipline close blocks waiting for the characters to get - flushed, which never happens until the serial port gets reused. - -Wed Apr 12 08:06:16 1995 Theodore Y. Ts'o - - * serial.c (do_serial_hangup, do_softint, check_modem_status, - rs_init): Hangups are now scheduled via a separate tqueue - structure in the async_struct structure, tqueue_hangup. - This task is pushed on to the tq_schedule queue, so that - it is processed synchronously by the scheduler. - -Sat Feb 18 12:13:51 1995 Theodore Y. Ts'o (tytso@rt-11) - - * tty_io.c (disassociate_ctty, tty_open, tty_ioctl): Clear - current->tty_old_pgrp field when a session leader - acquires a controlling tty, and after a session leader - has disassociated from a controlling tty. - -Fri Feb 17 09:34:09 1995 Theodore Y. Ts'o (tytso@rt-11) - - * serial.c (rs_interrupt_single, rs_interrupt, rs_interrupt_multi): - Change the number of passes made from 64 to be 256, - configurable with the #define RS_ISR_PASS_LIMIT. - - * serial.c (rs_init, set_serial_info, get_serial_info, rs_close): - Remove support for closing_wait2. Instead, set - tty->closing and rely on the line discipline to prevent - echo wars. - - * n_tty.c (n_tty_receive_char): IEXTEN does not need to be - enabled in order for IXANY to be active. - - If tty->closing is set, then only process XON and XOFF - characters. - -Sun Feb 12 23:57:48 1995 Theodore Y. Ts'o (tytso@rt-11) - - * serial.c (rs_timer): Change the interrupt poll time from 60 - seconds to 10 seconds, configurable with the #define - RS_STROBE_TIME. - - * serial.c (rs_interrupt_multi, startup, shutdown, rs_ioctl, - set_multiport_struct, get_multiport_struct): Add - provisions for a new type of interrupt service routine, - which better supports multiple serial ports on a single - IRQ. - -Sun Feb 5 19:35:11 1995 Theodore Y. Ts'o (tytso@rt-11) - - * tty_ioctl.c (n_tty_ioctl, set_termios, tty_wait_until_sent): - * serial.c (rs_ioctl, rs_close): - * cyclades.c (cy_ioctl, cy_close): - * n_tty.c (n_tty_close): Rename wait_until_sent to - tty_wait_until_sent, so that it's a better name to export - in ksyms.c. - -Sat Feb 4 23:36:20 1995 Theodore Y. Ts'o (tytso@rt-11) - - * serial.c (rs_close): Added missing check for closing_wait2 being - ASYNC_CLOSING_WAIT_NONE. - -Thu Jan 26 09:02:49 1995 Theodore Y. Ts'o (tytso@rt-11) - - * serial.c (rs_init, set_serial_info, get_serial_info, - rs_close): Support close_wait in the serial driver. - This is helpful for slow devices (like serial - plotters) so that their outputs don't get flushed upon - device close. This has to be configurable because - normally we don't want ports to be hung up for long - periods of time during a close when they are not - connected to a device, or the device is powered off. - - The default is to wait 30 seconds; in the case of a - very slow device, the close_wait timeout should be - lengthened. If it is set to 0, the kernel will wait - forever for all of the data to be transmitted. - -Thu Jan 17 01:17:20 1995 Theodore Y. Ts'o (tytso@rt-11) - - * serial.c (startup, change_speed, rs_init): Add support to detect - the StarTech 16650 chip. Treat it as a 16450 for now, - because of its FIFO bugs. - -Thu Jan 5 21:21:57 1995 - - * serial.c: (receive_char): Added counter to prevent infinite loop - when a PCMCIA serial device is ejected. - -Thu Dec 29 17:53:48 1994 - - * tty_io.c (check_tty_count): New procedure which checks - tty->count to make sure that it matches with the number of - open file descriptors which point at the structure. If - the number doesn't match, it prints a warning message. - -Wed Dec 28 15:41:51 1994 - - * tty_io.c (do_tty_hangup, disassociate_ctty): At hangup time, - save the tty's current foreground process group in the - session leader's task structure. When the session leader - terminates, send a SIGHUP, SIGCONT to that process group. - This is not required by POSIX, but it's not prohibited - either, and it appears to be the least intrusive way - to fix a problem that dialup servers have with - orphaned process groups caused by modem hangups. - -Thu Dec 8 14:52:11 1994 - - * serial.c (rs_ioctl): Don't allow most ioctl's if the serial port - isn't initialized. - - * serial.c (rs_close): Don't clear the IER if the serial port - isn't initialized. - - * serial.c (block_til_ready): Don't try to block on the dialin - port if the serial port isn't initialized. - -Wed Dec 7 10:48:30 1994 Si Park (si@wimpol.demon.co.uk) - * tty_io.c (tty_register_driver): Fix bug when linking onto - the tty_drivers list. We now test that there are elements - already on the list before setting the back link from the - first element to the new driver. - - * tty_io.c (tty_unregister_driver): Fix bug in unlinking the - specified driver from the tty_drivers list. We were not - setting the back link correctly. This used to result in - a dangling back link pointer and cause panics on the next - call to get_tty_driver(). - -Tue Nov 29 10:21:09 1994 Theodore Y. Ts'o (tytso@rt-11) - - * tty_io.c (tty_unregister_driver): Fix bug in - tty_unregister_driver where the pointer to the refcount is - tested, instead of the refcount itself. This caused - tty_unregister_driver to always return EBUSY. - -Sat Nov 26 11:59:24 1994 Theodore Y. Ts'o (tytso@rt-11) - - * tty_io.c (tty_ioctl): Add support for the new ioctl - TIOCTTYGSTRUCT, which allow a kernel debugging program - direct read access to the tty and tty_driver structures. - -Fri Nov 25 17:26:22 1994 Theodore Y. Ts'o (tytso@rt-11) - - * serial.c (rs_set_termios): Don't wake up processes blocked in - open when the CLOCAL flag changes, since a blocking - open only samples the CLOCAL flag once when it blocks, - and doesn't check it again. (n.b. FreeBSD has a - different behavior for blocking opens; it's not clear - whether Linux or FreeBSD's interpretation is correct. - POSIX doesn't give clear guidance on this issue, so - this may change in the future....) - - * serial.c (block_til_ready): Use the correct termios structure to - check the CLOCAL flag. If the cuaXX device is active, - then check the saved termios for the ttySXX device. - Otherwise, use the currently active termios structure. - -Sun Nov 6 21:05:44 1994 Theodore Y. Ts'o (tytso@rt-11) - - * serial.c (change_speed): Add support for direct access of - 57,600 and 115,200 bps. - -Wed Nov 2 10:32:36 1994 Theodore Y. Ts'o (tytso@rt-11) - - * n_tty.c (n_tty_receive_room): Only allow excess characters - through if we are in ICANON mode *and* there are other no - pending lines in the buffer. Otherwise cut and paste over - 4k breaks. - -Sat Oct 29 18:17:34 1994 Theodore Y. Ts'o (tytso@rt-11) - - * serial.c (rs_ioctl, get_lsr_info): Added patch suggested by Arne - Riiber so that user mode programs can tell when the - transmitter shift register is empty. - -Thu Oct 27 23:14:29 1994 Theodore Y. Ts'o (tytso@rt-11) - - * tty_ioctl.c (wait_until_sent): Added debugging printk statements - (under the #ifdef TTY_DEBUG_WAIT_UNTIL_SENT) - - * serial.c (rs_interrupt, rs_interrupt_single, receive_chars, - change_speed, rs_close): rs_close now disables receiver - interrupts when closing the serial port. This allows the - serial port to close quickly when Linux and a modem (or a - mouse) are engaged in an echo war; when closing the serial - port, we now first stop listening to incoming characters, - and *then* wait for the transmit buffer to drain. - - In order to make this change, the info->read_status_mask - is now used to control what bits of the line status - register are looked at in the interrupt routine in all - cases; previously it was only used in receive_chars to - select a few of the status bits. - -Mon Oct 24 23:36:21 1994 Theodore Y. Ts'o (tytso@rt-11) - - * serial.c (rs_close): Add a timeout to the transmitter flush - loop; this is just a sanity check in case we have flaky - (or non-existent-but-configured-by-the-user) hardware. - -Fri Oct 21 09:37:23 1994 Theodore Y. Ts'o (tytso@rt-11) - - * tty_io.c (tty_fasync): When asynchronous I/O is enabled, if the - process or process group has not be specified yet, set it - to be the tty's process group, or if that is not yet set, - to the current process's pid. - -Thu Oct 20 23:17:28 1994 Theodore Y. Ts'o (tytso@rt-11) - - * n_tty.c (n_tty_receive_room): If we are doing input - canonicalization, let as many characters through as - possible, so that the excess characters can be "beeped". - -Tue Oct 18 10:02:43 1994 Theodore Y. Ts'o (tytso@rt-11) - - * serial.c (rs_start): Removed an incorrect '!' that was - preventing transmit interrupts from being re-enabled in - rs_start(). Fortunately in most cases it would be - re-enabled elsewhere, but this still should be fixed - correctly. - -Sun Oct 9 23:46:03 1994 Theodore Y. Ts'o (tytso@rt-11) - - * tty_io.c (do_tty_hangup): If the tty driver flags - TTY_DRIVER_RESET_TERMIOS is set, then reset the termios - settings back to the driver's initial configuration. This - allows the termios settings to be reset even if a process - has hung up file descriptors keeping a pty's termios from - being freed and reset. - - * tty_io.c (release_dev): Fix memory leak. The pty's other - termios structure should also be freed. - - * serial.c (rs_close, shutdown): Change how we wait for the - transmitter to completely drain before shutting down the - serial port. We now do it by scheduling in another - process instead of busy looping with the interrupts turned - on. This may eliminate some race condition problems that - some people seem to be reporting. - -Sun Sep 25 14:18:14 1994 Theodore Y. Ts'o (tytso@rt-11) - - * tty_io.c (release_dev): When freeing a tty make sure that both - the tty and the o_tty (if present) aren't a process's - controlling tty. (Previously, we only checked the tty.) - - * serial.c (change_speed): Only enable the Modem Status - Interrupt for a port if CLOCAL is not set or CRTSCTS - is set. If we're not checking the carrier detect and - CTS line, there's no point in enabling the modem - status interrupt. This will save spurious interrupts - from slowing down systems who have terminals that - don't support either line. (Of course, if you want - only one of CD and CTS support, you will need a - properly wired serial cable.) - -Thu Sep 22 08:32:48 1994 Theodore Y. Ts'o (tytso@rt-11) - - * tty_io.c (do_SAK): Return if tty is null. - - * tty_io.c (_tty_name): Return "NULL tty" if the passed in tty is - NULL. - -Sat Sep 17 13:19:25 1994 Theodore Y. Ts'o (tytso@rt-11) - - * tty_ioctl.c (n_tty_ioctl): Fix TIOCGLCKTRMIOS and - TIOCSLCKTRMIOS, which were totally broken. Remove - extra indirection from argument; it should be a struct - termios *, not a struct termios **. - &real_tty->termios_locked should have been - real_tty->termios_locked. This caused us to be - reading and writing the termios_locked structure to - random places in kernel memory. - - * tty_io.c (release_dev): Oops! Forgot to delete a critical kfree - of the locked_termios. This leaves the locked_termios - structure pointed at a freed object. - -Fri Sep 16 08:13:25 1994 Theodore Y. Ts'o (tytso@rt-11) - - * tty_io.c (tty_open): Don't check for an exclusive open until - after the device specific open routine has been called. - Otherwise, the serial device ref counting will be screwed - up. - - * serial.c (rs_open, block_til_ready): Don't set termios structure - until after block_til_ready has returned successfully. - Modify block_til_ready to check the normal_termios - structure directly, so it doesn't rely on termios being - set before it's called. - -Thu Sep 15 23:34:01 1994 Theodore Y. Ts'o (tytso@rt-11) - - * serial.c (rs_close): Turn off interrupts during rs_close() to - prevent a race condition with the hangup code (which - runs during a software interrupt). - - * tty_io.c (release_dev): Don't free the locked_termios structure; - its state must be retained across device opens. - - - * tty_io.c (tty_unregister_driver): Added function to unregister a - tty driver. (For loadable device drivers.) - - -- cgit v1.2.3 From b7e9f6219d01ccb4af6fe5ad082150032ecae8ab Mon Sep 17 00:00:00 2001 From: Jiri Kosina Date: Fri, 19 Feb 2010 00:44:42 +0100 Subject: Remove drivers/parport/ChangeLog Remove outdated drivers/parport/ChangeLog. No need for such files since we have git. Acked-by: Alan Cox Signed-off-by: Jiri Kosina --- drivers/parport/ChangeLog | 583 ---------------------------------------------- 1 file changed, 583 deletions(-) delete mode 100644 drivers/parport/ChangeLog (limited to 'drivers') diff --git a/drivers/parport/ChangeLog b/drivers/parport/ChangeLog deleted file mode 100644 index 8565bbbeb6ec..000000000000 --- a/drivers/parport/ChangeLog +++ /dev/null @@ -1,583 +0,0 @@ -2001-10-11 Tim Waugh - * parport_pc.c, parport_serial.c: Support for NetMos cards. - + Patch originally from Michael Reinelt . - -2002-04-25 Tim Waugh - - * parport_serial.c, parport_pc.c: Move some SIIG cards around. - Patch from Andrey Panin. - -2002-01-20 Tim Waugh - - * parport_pc.c (parport_pc_compat_write_block_pio, - parport_pc_ecp_write_block_pio, parport_pc_ecp_read_block_pio): - Use the default implementations if the caller wants to use - O_NONBLOCK. - -2002-02-25 Tim Waugh - - * parport_pc.c: Make sure that priv->ctr_writable includes IntEn - even if IRQ is given as a parameter. - -2002-01-21 Tim Waugh - - * daisy.c: Apply patch from Max Vorobiev to make parport_daisy_select - work for ECP/EPP modes. - -2002-01-13 Niels Kristian Bech Jensen - - * parport_pc.c: Change some occurrences of frob_set_mode to - ECR_WRITE. This fixes PLIP. - -2002-01-04 Tim Waugh - - * share.c (parport_claim_or_block): Sleep interruptibly to prevent - a possible deadlock. - -2001-12-07 Damian Gruszka - - * parport_pc.c (ECR_WRITE): Define. If there are forbidden bits - in the ECR register for some chips, this will be a useful place to - put that knowledge. - (change_mode): Use ECR_WRITE. - (parport_pc_restore_state): Likewise. - (parport_ECPPS2_supported): Likewise. - (parport_ECPEPP_supported): Likewise. - (irq_probe_EPP): Likewise. - (programmable_irq_support): Likewise. - (programmable_dma_support): Likewise. - (parport_pc_probe_port): Likewise. - - (frob_set_mode): New function. Set the mode bits of the ECR. - (get_fifo_residue): Use frob_set_mode. - (parport_pc_ecpepp_read_data): Likewise. - (parport_pc_ecpepp_write_data): Likewise. - (parport_pc_ecpepp_read_addr): Likewise. - (parport_pc_ecpepp_write_addr): Likewise. - (parport_pc_compat_write_block_pio): Likewise. - (parport_pc_ecp_write_block_pio): Likewise. - (parport_ECR_present): Likewise. - (parport_ECP_supported): Likewise. - (parport_EPP_supported): Likewise. - (parport_ECPEPP_supported): Likewise. - (programmable_irq_support): Likewise. - (irq_probe_ECP): Likewise. - (programmable_dma_support): Likewise. - - (parport_pc_enable_irq): Only enable interrupts if we know which - IRQ line they will come from. - (parport_pc_init_state): Set nErrIntrEn at initialisation. - (parport_pc_restore_state): Only write writable bits of CTR. - (parport_irq_probe): If no IRQ is found, take ackIntEn out of the - writable bit set. - -2001-12-07 Tim Waugh - - * parport_pc.c (parport_pc_fifo_write_block_pio): Correct typo. - (parport_pc_init_state): Only set ackIntEn if we know which IRQ - line the interrupts will come from. - -2001-12-07 Tim Waugh - - * ieee1284_ops.c (parport_ieee1284_epp_write_addr, - parport_ieee1284_epp_read_addr): Actually do something useful. - -2001-12-07 Tim Waugh - - * parport_pc.c (dmaval): Don't use DMA by default. It seems to be - too buggy at the moment. Use 'dma=auto' to restore the previous - behaviour. - -2001-12-07 Tim Waugh - - * daisy.c (DEBUG): Undefine. - -2001-12-06 Tim Waugh - - * ieee1284_ops.c (parport_ieee1284_ecp_read_data): Mask off - PARPORT_CONTROL_AUTOFD as well. Bug spotted by Joe - . - -2001-12-03 Rich Liu - - * parport_pc.c (sio_ite_8872_probe): ITE8873 is a single-port - serial board, not a serial+parallel. - -2001-11-30 Niels Kristian Bech Jensen - - * parport_pc.c: Fix compiler warning. - -2001-11-14 Tim Waugh - - * parport_pc.c (parport_pc_pci_probe): Hooks for PCI cards before - and after probing for ports. - * parport_serial.c (parport_register): Likewise. - -2001-11-12 Tim Waugh - - * parport_pc.c (init_module): Warn when parameters are ignored. - -2001-11-01 Damian Gruszka - - * parport_serial.c (serial_register): Set base_baud before - calling register_serial. - -2001-10-26 Tim Waugh - - * parport_pc.c (parport_irq_probe): When ECR programmable IRQ - support fails, generate interrupts using the FIFO even if we don't - want to use the FIFO for real data transfers. - (parport_pc_probe_port): Display the ECR address if we have an - ECR, not just if we will use the FIFO. - -2001-10-24 Dave Strauss - - * parport_pc.c (parport_pc_compat_write_block_pio, - parport_pc_ecp_write_block_pio): Allow a few seconds for an ECP - transfer to finish up. - -2001-10-11 Tim Waugh - - * parport_pc (sio_ite_8872_probe): New function, submitted by Rich - Liu from ITE. Cleaned up, removed bogus phys_to_virt calls. - -2001-10-24 Tim Waugh - - * parport_pc.c: Support for AKS AladdinCARD. Patch from - Aladdin Knowledge Systems (Christian Groessler). - -2001-10-24 Tim Waugh - - * ieee1284_ops.c (parport_ieee1284_ecp_read_data): Try to minimise - turnaround time. - - * ieee1284.c (parport_poll_peripheral): Try a couple of times - first without delaying. - -2001-10-10 Tim Waugh - - * parport_pc.c: Support for OX16PCI954 PCI card. - -2001-10-10 Tim Waugh - - * parport_pc.c: Support for OX12PCI840 PCI card (reported by - mk@daveg.com). Lock-ups diagnosed by Ronnie Arosa (and now we - just don't trust its ECR). - -2001-10-10 Gunther Mayer - - * parport_pc.c: Support for AVLAB cards. - -2001-10-10 Tim Waugh - - * ieee1284_ops.c (ecp_forward_to_reverse, ecp_reverse_to_forward): - Remember to retry direction switch if it fails. Patch from David - Lambert. - -2001-10-08 David C. Hansen - - * share.c: Make driverlist_lock and parportlist_lock static. - -2001-10-08 Philip Blundell - - * parport_pc.c: New modular parameter verbose_logging. - Make port->modes indicate the modes that we are prepared to use, - rather than the modes that are available. - -2001-10-07 Tim Waugh - - * parport_pc.c (parport_pc_probe_port): Fix memory leak spotted by - Kipp Cannon. - -2001-10-07 Tim Waugh - - * parport_serial.c: Remove NetMos support, since it causes problems - for some people. - -2001-08-30 Tim Waugh - - * parport_serial.c (parport_serial_pci_probe): Clean-up on partial - registration failure. - -2001-08-14 Tim Waugh - - * parport_pc.c (parport_pc_init_superio): Allow for more than one - SuperIO device. Patch from Rich Lio (ITE). - -2001-08-11 Tim Waugh - - * parport_pc.c: Support for Titan Electronics cards. - -2001-08-08 Tim Waugh - - * share.c (parport_unregister_device): Remove device from wait list - too. - -2001-06-20 Tim Waugh - - * parport_pc.c: Make 'io_hi=0' work. - -2001-05-31 Tim Waugh - - * parport_serial.c: New file. - -2001-06-05 Tim Waugh - - * parport_pc.c (parport_pc_unregister_port): New exported function. - Do the opposite of parport_pc_probe_port. - (cleanup_module): Use it. - -2001-05-22 Juan Quintela - - * parport_amiga.c: Set printk levels. - * parport_gsc.c: Likewise. - * parport_mfc3.c: Likewise. - * parport_pc.c: Likewise. - * parport_sunbpp.c: Likewise. - * probe.c: Likewise. - * share.c: Likewise. - -2001-05-10 Fred Barnes - - * parport_pc.c (parport_pc_epp_read_data): added support for - reading from a w91284pic peripheral, flag is PARPORT_W91284PIC. - -2001-05-07 Fred Barnes - - * parport_pc.c (parport_pc_epp_read_data, - parport_pc_epp_write_data, parport_pc_epp_read_addr, - parport_pc_epp_write_addr): support for fast reads/writes using - the PARPORT_EPP_FAST flag. - - * ieee1284.c (parport_read, parport_write): added code to handle - software EPP mode (IEEE1284_MODE_EPPSWE). Added code to allow - BYTE mode reverse transfers (previously always went for NIBBLE - mode). - - * ieee1284_ops.c (parport_ieee1284_epp_read_data, - parport_ieee1284_epp_write_data): fixed various polarity problems. - Also (theoretically) fixed address versions (.._addr), but no - hardware to test this on. - - * parport_pc.h: added parport_dump_state() function for debugging. - Needs to have DEBUG_PARPORT to be defined for it to be included. - -2001-05-03 Tim Waugh - - * parport_pc.c: Fix the compile problem I introduce from the last - change. - -2001-04-20 Paul Gortmaker - - * parport_pc.c: Cut down the size quite a bit (more than 4k off - the object, about 1k off the zImage) for the older non-PCI - machines which are typically resource starved anyway... - -2001-03-26 R Horn - - * parport_pc.c: Some commentary changes. - -2001-04-19 Tim Waugh - - * parport_pc.c (parport_pc_probe_port): Remove __devinit - attribute. Export unconditionally. - -2001-04-14 Jeff Garzik - - Merged: 2001-03-30 Tim Waugh - - * drivers/parport/parport_pc.c: Make Via SuperIO chipsets behave - like everything else with respect to irq= and dma= parameters. - -2001-04-08 Tim Waugh - - * parport_pc.c (parport_pc_save_state): Read from the soft copy of - the control port. - (parport_pc_restore_state): Update the soft copy of the control - port. - -2001-03-26 Tim Waugh - - * share.c (parport_find_number, parport_find_base): Trigger - a lowlevel driver load if there are no ports yet. - -2001-03-26 Tim Waugh - - * parport_pc.c (parport_ECP_supported): Remove the IRQ conflict - check since it seems totally unreliable. - -2001-03-02 Tim Waugh - - * ieee1284_ops.c (parport_ieee1284_read_nibble): Reset nAutoFd - on timeout. Matches 2.2.x behaviour. - -2001-03-02 Andrew Morton - - * parport_pc.c (registered_parport): New static variable. - (parport_pc_find_ports): Set it when we register PCI driver. - (init_module): Unregister PCI driver if necessary when we - fail. - -2001-03-02 Tim Waugh - - * ieee1284_ops.c (parport_ieee1284_write_compat): Don't use - down_trylock to reset the IRQ count. Don't even use sema_init, - because it's not even necessary to reset the count. I can't - remember why we ever did. - -2001-01-04 Peter Osterlund - - * ieee1284.c (parport_negotiate): Fix missing printk argument. - -2001-01-03 Paul Schleger - - * probe.c (parse_data): Get rid of trailing blanks in values. - Needed for XEROX XJ8C printer. - -2001-01-03 Tim Waugh - - * parport_pc.c (parport_pc_probe_port): Say something when probes - are omitted. - -2001-01-03 Tim Waugh - - * parport_pc.c (sio_via_686a_probe): Correct dma=255 fix. - -2000-11-21 Tim Waugh - - * parport_pc.c (parport_pc_ecp_write_block_pio): Fix - reverse-to-forward logic. Spotted by Roland Kuck - . - -2000-09-16 Cesar Eduardo Barros - - * parport_pc.c (sio_via_686a_probe): Handle case - where hardware returns 255 for IRQ or DMA. - -2000-07-20 Eddie C. Dost - - * share.c (attach_driver_chain): attach[i](port) needs to be - replaced by attach[count](port). - -2000-07-20 Eddie C. Dost - - * daisy.c (add_dev): kmalloc args are in wrong order. - -2000-07-12 Tim Waugh - - * share.c: Documentation for parport_{get,port}_port, - parport_find_{number,base}. - -2000-07-12 Tim Waugh - - * share.c (parport_unregister_device): Remove unneeded locking - (test cad==dev). - (parport_claim): Likewise. - (parport_find_number): New function. - -2000-07-12 Tim Waugh - - * share.c (parport_register_port): Hold the parportlist_lock while - looking for a free parport number. - (parport_register_driver): Make sure that attach can block. - (attach_driver_chain): Likewise. - -2000-07-12 Tim Waugh - - * share.c (call_driver_chain): Do reference counting things. - (parport_get_port): New function. - (parport_put_port): New function. - (parport_register_port): Initialise reference count to zero. - (parport_unregister_port): Check reference count rather than - driver list to see if we can free the port. - -2000-07-12 Tim Waugh - - * share.c: Clarifications in doc comments. - -2000-07-12 Tim Waugh - - * share.c (parport_unregister_port): Fix typo in comment. - -2000-07-11 Gunther Mayer - - * parport_pc.c: Support for the full range of Timedia cards. - -2000-07-08 Tim Waugh - - * daisy.c: License block comments as part of parportbook. - * ieee1284.c: Likewise. - * share.c: Likewise. - -2000-06-30 Petr Vandrovec - - * procfs.c (do_hardware_modes): Generated string can be up to 34 - chars long. - -2000-06-20 Gunther Mayer - - * parport_pc.c (parport_pc_compat_write_block_pio): Warn about - change_mode failures. - (parport_pc_ecp_write_block_pio): Likewise. - (parport_pc_ecp_read_block_pio): Likewise. - -2000-06-20 Gunther Mayer - - * parport_pc.c (parport_SPP_supported): Warn more about possibly - incorrect parameters. - -2000-06-15 Tim Waugh - - * parport_pc.c (parport_ECP_supported): Set PARPORT_MODE_COMPAT - for ECP ports, since they can all do hardware accelerated - compatibility mode (I assume). - -2000-06-13 Tim Waugh - - * parport_pc.c (cleanup_module): Remark about possible bugs. - -2000-06-13 Tim Waugh - - * procfs.c: Break 'hardware' out into separate files. - -2000-05-28 Gunther Mayer - - * Fix PCI ID printk for non-superio PCI cards. - -2000-05-28 Tim Waugh - - * share.c (call_driver_chain): Get the driverlist_lock. - (parport_register_device): Make sure that port->devices always - looks consistent. - (parport_register_driver): Ensure that parport drivers are given - parameters that are valid for the duration of the callback by - locking the portlist against changes. - (parport_unregister_driver): Likewise. - (parport_claim): Don't overwrite flags. - -2000-05-28 Tim Waugh - - * daisy.c (assign_addrs): Avoid double-probing daisy-chain devices - if the first probe succeeds. - -2000-05-16 Tim Waugh - - * share.c (parport_claim): Fix SMP race. - -2000-05-15 Gunther Mayer - - * parport_pc.c (parport_pc_compat_write_block_pio): Check for - timeouts. - (parport_pc_ecp_write_block_pio): Likewise. - (parport_pc_ecp_read_block_pio): Likewise. - -2000-05-02 Gunther Mayer - - * parport_pc.c: PCI SYBA patch and verbose PCI detection. - -2000-05-02 Gunther Mayer - - * parport_pc.c (decode_smsc): Fix SMSC 665/666 identification. - -2000-04-28 Tim Waugh - - * ieee1284.c: Short function descriptions can't be multiline. - - * daisy.c: Short function descriptions can't be multiline. - -2000-04-19 Tim Waugh - - * parport_pc.c (parport_pc_fifo_write_block_dma): Make maxlen - calculation a bit clearer. - - * ieee1284.c (parport_negotiate): Turn on data line drivers. - - * ieee1284_ops.c (parport_ieee1284_read_byte): Turn off data line - drivers. - (parport_ieee1284_write_compat): Turn on data line drivers. - - * daisy.c (assign_addrs): Turn on data line drivers. - (cpp_mux): Likewise. - (cpp_daisy): Likewise. - -2000-04-04 Tim Waugh - - * parport_pc.c: Add support for another PCI card. - -2000-04-04 Tim Waugh - - * daisy.c: Documentation in kernel-doc format. - - * ieee1284.c: Likewise. - - * share.c: Likewise. - -2000-04-01 Tim Waugh - - * share.c (parport_register_device): Need to hold the module - reference counts before sleeping. - -2000-03-27 Tim Waugh - - * parport_pc.c (parport_pc_ecp_read_block_pio): Correct operation - when peripheral is trying to send data when we stop listening. - -2000-03-22 Tim Waugh - - * init.c (parport_setup): Fix return value. - -2000-03-21 Tim Waugh - - * parport_pc.c (parport_pc_pci_probe): Fix return value; call - pci_enable_device. - -2000-03-16 Tim Waugh - - * parport_pc.c (parport_ECP_supported): This seems to trigger on - machines that don't have an IRQ conflict; toned down the warning - message accordingly. - -2000-03-16 Gunther Mayer - - * parport_pc.c (show_parconfig_smsc37c669): Fix typo. - (decode_winbond): More IDs. - (winbond_check): Protect against false positives. - (winbond_check2): Likewise. - (smsc_check): Likewise. - -2000-03-15 Tim Waugh - - * parport_pc.c (cleanup_module): Don't call pci_unregister_driver - if we didn't call pci_register_driver first. - -2000-03-13 Tim Waugh - - * parport_pc.c (parport_pc_init): Moved from asm/parport.h. - - * Config.in: CONFIG_PARPORT_PC_SUPERIO: new option. - - * parport_pc.c (show_parconfig_smsc37c669): Make __devinit. - (show_parconfig_winbond): Likewise. - (decode_winbond): Likewise. - (decode_smsc): Likewise. - (winbond_check): Likewise. - (winbond_check2): Likewise. - (smsc_check): Likewise. - (detect_and_report_winbond): Likewise. - (detect_and_report_smsc): Likewise. - (get_superio_dma): Likewise. - (get_superio_irq): Likewise. - (parport_pc_find_isa_ports): New function. - (parport_pc_find_ports): New function. - (init_module): Make superio a config option, not a parameter. - -2000-03-10 Tim Waugh - - * parport_pc.c (decode_winbond): Use correct 83877ATF chip ID. - (decode_winbond): Fix typo. - -2000-03-09 Tim Waugh - - * parport_pc.c: Integrate SuperIO PCI probe with normal PCI card - probe, so that the MODULE_DEVICE_TABLE is complete. - -- cgit v1.2.3 From 8b7ef6d8f16274da42344cd50746ddb1c93c25ea Mon Sep 17 00:00:00 2001 From: Thomas Renninger Date: Tue, 16 Feb 2010 22:55:51 +0100 Subject: ACPI thermal: Check for thermal zone requirement ACPI spec says (11.5 Thermal Zone Interface Requirements): A thermal zone must contain at least one trip point (critical, near critical, active, or passive) Check this once at init time. Signed-off-by: Thomas Renninger Tested-by: clarkt@cnsp.com Signed-off-by: Len Brown --- drivers/acpi/thermal.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c index 9073ada88835..e9f28e075cf8 100644 --- a/drivers/acpi/thermal.c +++ b/drivers/acpi/thermal.c @@ -575,7 +575,23 @@ static int acpi_thermal_trips_update(struct acpi_thermal *tz, int flag) static int acpi_thermal_get_trip_points(struct acpi_thermal *tz) { - return acpi_thermal_trips_update(tz, ACPI_TRIPS_INIT); + int i, valid, ret = acpi_thermal_trips_update(tz, ACPI_TRIPS_INIT); + + if (ret) + return ret; + + valid = tz->trips.critical.flags.valid | + tz->trips.hot.flags.valid | + tz->trips.passive.flags.valid; + + for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE; i++) + valid |= tz->trips.active[i].flags.valid; + + if (!valid) { + printk(KERN_WARNING FW_BUG "No valid trip found\n"); + return -ENODEV; + } + return 0; } static void acpi_thermal_check(void *data) -- cgit v1.2.3 From cf4c43dd439b90a1a876b3f836ebe745abb9a269 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Wed, 15 Jul 2009 13:13:00 -0700 Subject: PCI: Add pci_bus_find_ext_capability For use by code that needs to walk extended capability lists before pci_dev structures are set up. Signed-off-by: Jesse Barnes LKML-Reference: <43F901BD926A4E43B106BF17856F07559FB80CFD@orsmsx508.amr.corp.intel.com> Signed-off-by: Jacob Pan Signed-off-by: H. Peter Anvin --- drivers/pci/pci.c | 43 +++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 2 ++ 2 files changed, 45 insertions(+) (limited to 'drivers') diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 315fea47e784..aad62af2b4c6 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -297,6 +297,49 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap) } EXPORT_SYMBOL_GPL(pci_find_ext_capability); +/** + * pci_bus_find_ext_capability - find an extended capability + * @bus: the PCI bus to query + * @devfn: PCI device to query + * @cap: capability code + * + * Like pci_find_ext_capability() but works for pci devices that do not have a + * pci_dev structure set up yet. + * + * Returns the address of the requested capability structure within the + * device's PCI configuration space or 0 in case the device does not + * support it. + */ +int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn, + int cap) +{ + u32 header; + int ttl; + int pos = PCI_CFG_SPACE_SIZE; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + if (!pci_bus_read_config_dword(bus, devfn, pos, &header)) + return 0; + if (header == 0xffffffff || header == 0) + return 0; + + while (ttl-- > 0) { + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (pos < PCI_CFG_SPACE_SIZE) + break; + + if (!pci_bus_read_config_dword(bus, devfn, pos, &header)) + break; + } + + return 0; +} + static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) { int rc, ttl = PCI_FIND_CAP_TTL; diff --git a/include/linux/pci.h b/include/linux/pci.h index c1968f464c38..65f8a8f9d3e5 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -631,6 +631,8 @@ enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); int pci_find_capability(struct pci_dev *dev, int cap); int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); int pci_find_ext_capability(struct pci_dev *dev, int cap); +int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn, + int cap); int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); struct pci_bus *pci_find_next_bus(const struct pci_bus *from); -- cgit v1.2.3 From ee980b8003a25fbfed50c3367f2b426c870eaf90 Mon Sep 17 00:00:00 2001 From: Li Peng Date: Wed, 27 Jan 2010 19:01:11 +0800 Subject: drm/i915: enable memory self refresh on 9xx Enabling memory self refresh (SR) on 9xx needs to set additional register bits. On 945, we need bit 31 of FW_BLC_SELF to enable the write to self refresh bit and bit 16 to enable the write of self refresh watermark. On 915, bit 12 of INSTPM is used to enable SR. SR will take effect when CPU enters C3+ state and its entry/exit should be automatically controlled by H/W, driver only needs to set SR enable bits in wm update. But this isn't safe in my test on 945 because GPU is hung. So this patch explicitly enables SR when GPU is idle, and disables SR when it is busy. In my test on a netbook of 945GSE chipset, it saves about 0.8W idle power. Signed-off-by: Li Peng [anholt: rebased against 33c5fd121eabbccc9103daf6cda36941eb3c349f by adding disable of INSTPM SR bit on 915GM for two pipe setup] Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_reg.h | 5 ++++- drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ab1bd2d3d3b6..6defb7f47348 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -306,11 +306,14 @@ #define I915_ERROR_MEMORY_REFRESH (1<<1) #define I915_ERROR_INSTRUCTION (1<<0) #define INSTPM 0x020c0 +#define INSTPM_SELF_EN (1<<12) /* 915GM only */ #define ACTHD 0x020c8 #define FW_BLC 0x020d8 #define FW_BLC2 0x020dc #define FW_BLC_SELF 0x020e0 /* 915+ only */ -#define FW_BLC_SELF_EN (1<<15) +#define FW_BLC_SELF_EN_MASK (1<<31) +#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ +#define FW_BLC_SELF_EN (1<<15) /* 945 only */ #define MM_BURST_LENGTH 0x00700000 #define MM_FIFO_WATERMARK 0x0001F000 #define LM_BURST_LENGTH 0x00000700 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b27202d23ebc..af9ec217cd1d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2757,11 +2757,22 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, srwm = total_size - sr_entries; if (srwm < 0) srwm = 1; - I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); + + if (IS_I945G(dev) || IS_I945GM(dev)) + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); + else if (IS_I915GM(dev)) { + /* 915M has a smaller SRWM field */ + I915_WRITE(FW_BLC_SELF, srwm & 0x3f); + I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); + } } else { /* Turn off self refresh if both pipes are enabled */ - I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) - & ~FW_BLC_SELF_EN); + if (IS_I945G(dev) || IS_I945GM(dev)) { + I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) + & ~FW_BLC_SELF_EN); + } else if (IS_I915GM(dev)) { + I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); + } } DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", @@ -4011,6 +4022,11 @@ static void intel_idle_update(struct work_struct *work) mutex_lock(&dev->struct_mutex); + if (IS_I945G(dev) || IS_I945GM(dev)) { + DRM_DEBUG_DRIVER("enable memory self refresh on 945\n"); + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); + } + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { /* Skip inactive CRTCs */ if (!crtc->fb) @@ -4044,6 +4060,15 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) if (!drm_core_check_feature(dev, DRIVER_MODESET)) return; + if (IS_I945G(dev) || IS_I945GM(dev)) { + u32 fw_blc_self; + + DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); + fw_blc_self = I915_READ(FW_BLC_SELF); + fw_blc_self &= ~FW_BLC_SELF_EN; + I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); + } + if (!dev_priv->busy) dev_priv->busy = true; else -- cgit v1.2.3 From f97108d1d0facc7902134ebc453b226bbd4d1cdb Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Fri, 29 Jan 2010 11:27:07 -0800 Subject: drm/i915: add dynamic performance control support for Ironlake Ironlake (and 965GM, which this patch doesn't support) supports a hardware performance and power management feature that allows it to adjust to changes in GPU load over time with software help. The goal if this is to maximize performance/power for a given workload. This patch enables that feature, which is also a requirement for supporting Intelligent Power Sharing, a feature which allows for dynamic budgeting of power between the CPU and GPU in Arrandale platforms. Tested-by: ykzhao [anholt: Resolved against the irq handler loop removal] Signed-off-by: Jesse Barnes Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_debugfs.c | 96 ++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.c | 5 ++ drivers/gpu/drm/i915/i915_drv.h | 6 ++ drivers/gpu/drm/i915/i915_irq.c | 63 ++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 141 ++++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/i915_suspend.c | 8 ++ drivers/gpu/drm/i915/intel_display.c | 100 +++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_drv.h | 2 + 8 files changed, 411 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index a894ade03093..55340de618ea 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -386,6 +386,97 @@ out: return 0; } +static int i915_rstdby_delays(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + u16 crstanddelay = I915_READ16(CRSTANDVID); + + seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); + + return 0; +} + +static int i915_cur_delayinfo(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + u16 rgvswctl = I915_READ16(MEMSWCTL); + + seq_printf(m, "Last command: 0x%01x\n", (rgvswctl >> 13) & 0x3); + seq_printf(m, "Command status: %d\n", (rgvswctl >> 12) & 1); + seq_printf(m, "P%d DELAY 0x%02x\n", (rgvswctl >> 8) & 0xf, + rgvswctl & 0x3f); + + return 0; +} + +static int i915_delayfreq_table(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + u32 delayfreq; + int i; + + for (i = 0; i < 16; i++) { + delayfreq = I915_READ(PXVFREQ_BASE + i * 4); + seq_printf(m, "P%02dVIDFREQ: 0x%08x\n", i, delayfreq); + } + + return 0; +} + +static inline int MAP_TO_MV(int map) +{ + return 1250 - (map * 25); +} + +static int i915_inttoext_table(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + u32 inttoext; + int i; + + for (i = 1; i <= 32; i++) { + inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); + seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); + } + + return 0; +} + +static int i915_drpc_info(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + u32 rgvmodectl = I915_READ(MEMMODECTL); + + seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? + "yes" : "no"); + seq_printf(m, "Boost freq: %d\n", + (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> + MEMMODE_BOOST_FREQ_SHIFT); + seq_printf(m, "HW control enabled: %s\n", + rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); + seq_printf(m, "SW control enabled: %s\n", + rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); + seq_printf(m, "Gated voltage change: %s\n", + rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); + seq_printf(m, "Starting frequency: P%d\n", + (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); + seq_printf(m, "Max frequency: P%d\n", + (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); + seq_printf(m, "Min frequency: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); + + return 0; +} + static int i915_wedged_open(struct inode *inode, struct file *filp) @@ -503,6 +594,11 @@ static struct drm_info_list i915_debugfs_list[] = { {"i915_ringbuffer_info", i915_ringbuffer_info, 0}, {"i915_batchbuffers", i915_batchbuffer_info, 0}, {"i915_error_state", i915_error_state, 0}, + {"i915_rstdby_delays", i915_rstdby_delays, 0}, + {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, + {"i915_delayfreq_table", i915_delayfreq_table, 0}, + {"i915_inttoext_table", i915_inttoext_table, 0}, + {"i915_drpc_info", i915_drpc_info, 0}, }; #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 79beffcf5936..89f1cb86c32b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -583,6 +583,11 @@ static int __init i915_init(void) driver.driver_features &= ~DRIVER_MODESET; #endif + if (!(driver.driver_features & DRIVER_MODESET)) { + driver.suspend = i915_suspend; + driver.resume = i915_resume; + } + return drm_init(&driver); } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f2742d6d3f54..2e493ec1042b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -452,6 +452,7 @@ typedef struct drm_i915_private { u32 savePIPEB_DATA_N1; u32 savePIPEB_LINK_M1; u32 savePIPEB_LINK_N1; + u32 saveRSTDBYCTL; struct { struct drm_mm gtt_space; @@ -590,7 +591,12 @@ typedef struct drm_i915_private { int child_dev_num; struct child_device_config *child_dev; struct drm_connector *int_lvds_connector; + bool mchbar_need_disable; + + u8 cur_delay; + u8 min_delay; + u8 max_delay; } drm_i915_private_t; /** driver private structure attached to each drm_gem_object */ diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index a17d6bdfe63e..8b35f5e1c511 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -269,6 +269,57 @@ static void i915_hotplug_work_func(struct work_struct *work) drm_sysfs_hotplug_event(dev); } +static void i915_handle_rps_change(struct drm_device *dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + u32 slow_up, slow_down, max_avg, min_avg; + u16 rgvswctl; + u8 new_delay = dev_priv->cur_delay; + + I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG); + slow_up = I915_READ(RCPREVBSYTUPAVG); + slow_down = I915_READ(RCPREVBSYTDNAVG); + max_avg = I915_READ(RCBMAXAVG); + min_avg = I915_READ(RCBMINAVG); + + /* Handle RCS change request from hw */ + if (slow_up > max_avg) { + if (dev_priv->cur_delay != dev_priv->max_delay) + new_delay = dev_priv->cur_delay - 1; + if (new_delay < dev_priv->max_delay) + new_delay = dev_priv->max_delay; + } else if (slow_down < min_avg) { + if (dev_priv->cur_delay != dev_priv->min_delay) + new_delay = dev_priv->cur_delay + 1; + if (new_delay > dev_priv->min_delay) + new_delay = dev_priv->min_delay; + } + + DRM_DEBUG("rps change requested: %d -> %d\n", + dev_priv->cur_delay, new_delay); + + rgvswctl = I915_READ(MEMSWCTL); + if (rgvswctl & MEMCTL_CMD_STS) { + DRM_ERROR("gpu slow, RCS change rejected\n"); + return; /* still slow with another command */ + } + + /* Program the new state */ + rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | + (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; + I915_WRITE(MEMSWCTL, rgvswctl); + POSTING_READ(MEMSWCTL); + + rgvswctl |= MEMCTL_CMD_STS; + I915_WRITE(MEMSWCTL, rgvswctl); + + dev_priv->cur_delay = new_delay; + + DRM_DEBUG("rps changed\n"); + + return; +} + irqreturn_t ironlake_irq_handler(struct drm_device *dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; @@ -331,6 +382,11 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev) queue_work(dev_priv->wq, &dev_priv->hotplug_work); } + if (de_iir & DE_PCU_EVENT) { + I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS)); + i915_handle_rps_change(dev); + } + /* should clear PCH hotplug event before clear CPU irq */ I915_WRITE(SDEIIR, pch_iir); I915_WRITE(GTIIR, gt_iir); @@ -1064,6 +1120,13 @@ static int ironlake_irq_postinstall(struct drm_device *dev) I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg); (void) I915_READ(SDEIER); + if (IS_IRONLAKE_M(dev)) { + /* Clear & enable PCU event interrupts */ + I915_WRITE(DEIIR, DE_PCU_EVENT); + I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); + ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); + } + return 0; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6defb7f47348..c3948ee37c13 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -61,6 +61,7 @@ #define GC_CLOCK_100_200 (1 << 0) #define GC_CLOCK_100_133 (2 << 0) #define GC_CLOCK_166_250 (3 << 0) +#define GCFGC2 0xda #define GCFGC 0xf0 /* 915+ only */ #define GC_LOW_FREQUENCY_ENABLE (1 << 7) #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) @@ -282,7 +283,7 @@ #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) #define I915_DISPLAY_PORT_INTERRUPT (1<<17) #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ #define I915_HWB_OOM_INTERRUPT (1<<13) #define I915_SYNC_STATUS_INTERRUPT (1<<12) #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) @@ -787,10 +788,144 @@ #define CLKCFG_MEM_800 (3 << 4) #define CLKCFG_MEM_MASK (7 << 4) -/** GM965 GM45 render standby register */ -#define MCHBAR_RENDER_STANDBY 0x111B8 +#define CRSTANDVID 0x11100 +#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ +#define PXVFREQ_PX_MASK 0x7f000000 +#define PXVFREQ_PX_SHIFT 24 +#define VIDFREQ_BASE 0x11110 +#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ +#define VIDFREQ2 0x11114 +#define VIDFREQ3 0x11118 +#define VIDFREQ4 0x1111c +#define VIDFREQ_P0_MASK 0x1f000000 +#define VIDFREQ_P0_SHIFT 24 +#define VIDFREQ_P0_CSCLK_MASK 0x00f00000 +#define VIDFREQ_P0_CSCLK_SHIFT 20 +#define VIDFREQ_P0_CRCLK_MASK 0x000f0000 +#define VIDFREQ_P0_CRCLK_SHIFT 16 +#define VIDFREQ_P1_MASK 0x00001f00 +#define VIDFREQ_P1_SHIFT 8 +#define VIDFREQ_P1_CSCLK_MASK 0x000000f0 +#define VIDFREQ_P1_CSCLK_SHIFT 4 +#define VIDFREQ_P1_CRCLK_MASK 0x0000000f +#define INTTOEXT_BASE_ILK 0x11300 +#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ +#define INTTOEXT_MAP3_SHIFT 24 +#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) +#define INTTOEXT_MAP2_SHIFT 16 +#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) +#define INTTOEXT_MAP1_SHIFT 8 +#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) +#define INTTOEXT_MAP0_SHIFT 0 +#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) +#define MEMSWCTL 0x11170 /* Ironlake only */ +#define MEMCTL_CMD_MASK 0xe000 +#define MEMCTL_CMD_SHIFT 13 +#define MEMCTL_CMD_RCLK_OFF 0 +#define MEMCTL_CMD_RCLK_ON 1 +#define MEMCTL_CMD_CHFREQ 2 +#define MEMCTL_CMD_CHVID 3 +#define MEMCTL_CMD_VMMOFF 4 +#define MEMCTL_CMD_VMMON 5 +#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears + when command complete */ +#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ +#define MEMCTL_FREQ_SHIFT 8 +#define MEMCTL_SFCAVM (1<<7) +#define MEMCTL_TGT_VID_MASK 0x007f +#define MEMIHYST 0x1117c +#define MEMINTREN 0x11180 /* 16 bits */ +#define MEMINT_RSEXIT_EN (1<<8) +#define MEMINT_CX_SUPR_EN (1<<7) +#define MEMINT_CONT_BUSY_EN (1<<6) +#define MEMINT_AVG_BUSY_EN (1<<5) +#define MEMINT_EVAL_CHG_EN (1<<4) +#define MEMINT_MON_IDLE_EN (1<<3) +#define MEMINT_UP_EVAL_EN (1<<2) +#define MEMINT_DOWN_EVAL_EN (1<<1) +#define MEMINT_SW_CMD_EN (1<<0) +#define MEMINTRSTR 0x11182 /* 16 bits */ +#define MEM_RSEXIT_MASK 0xc000 +#define MEM_RSEXIT_SHIFT 14 +#define MEM_CONT_BUSY_MASK 0x3000 +#define MEM_CONT_BUSY_SHIFT 12 +#define MEM_AVG_BUSY_MASK 0x0c00 +#define MEM_AVG_BUSY_SHIFT 10 +#define MEM_EVAL_CHG_MASK 0x0300 +#define MEM_EVAL_BUSY_SHIFT 8 +#define MEM_MON_IDLE_MASK 0x00c0 +#define MEM_MON_IDLE_SHIFT 6 +#define MEM_UP_EVAL_MASK 0x0030 +#define MEM_UP_EVAL_SHIFT 4 +#define MEM_DOWN_EVAL_MASK 0x000c +#define MEM_DOWN_EVAL_SHIFT 2 +#define MEM_SW_CMD_MASK 0x0003 +#define MEM_INT_STEER_GFX 0 +#define MEM_INT_STEER_CMR 1 +#define MEM_INT_STEER_SMI 2 +#define MEM_INT_STEER_SCI 3 +#define MEMINTRSTS 0x11184 +#define MEMINT_RSEXIT (1<<7) +#define MEMINT_CONT_BUSY (1<<6) +#define MEMINT_AVG_BUSY (1<<5) +#define MEMINT_EVAL_CHG (1<<4) +#define MEMINT_MON_IDLE (1<<3) +#define MEMINT_UP_EVAL (1<<2) +#define MEMINT_DOWN_EVAL (1<<1) +#define MEMINT_SW_CMD (1<<0) +#define MEMMODECTL 0x11190 +#define MEMMODE_BOOST_EN (1<<31) +#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ +#define MEMMODE_BOOST_FREQ_SHIFT 24 +#define MEMMODE_IDLE_MODE_MASK 0x00030000 +#define MEMMODE_IDLE_MODE_SHIFT 16 +#define MEMMODE_IDLE_MODE_EVAL 0 +#define MEMMODE_IDLE_MODE_CONT 1 +#define MEMMODE_HWIDLE_EN (1<<15) +#define MEMMODE_SWMODE_EN (1<<14) +#define MEMMODE_RCLK_GATE (1<<13) +#define MEMMODE_HW_UPDATE (1<<12) +#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ +#define MEMMODE_FSTART_SHIFT 8 +#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ +#define MEMMODE_FMAX_SHIFT 4 +#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ +#define RCBMAXAVG 0x1119c +#define MEMSWCTL2 0x1119e /* Cantiga only */ +#define SWMEMCMD_RENDER_OFF (0 << 13) +#define SWMEMCMD_RENDER_ON (1 << 13) +#define SWMEMCMD_SWFREQ (2 << 13) +#define SWMEMCMD_TARVID (3 << 13) +#define SWMEMCMD_VRM_OFF (4 << 13) +#define SWMEMCMD_VRM_ON (5 << 13) +#define CMDSTS (1<<12) +#define SFCAVM (1<<11) +#define SWFREQ_MASK 0x0380 /* P0-7 */ +#define SWFREQ_SHIFT 7 +#define TARVID_MASK 0x001f +#define MEMSTAT_CTG 0x111a0 +#define RCBMINAVG 0x111a0 +#define RCUPEI 0x111b0 +#define RCDNEI 0x111b4 +#define RSTDBYCTL 0x111b8 #define RCX_SW_EXIT (1<<23) #define RSX_STATUS_MASK 0x00700000 +#define VIDCTL 0x111c0 +#define VIDSTS 0x111c8 +#define VIDSTART 0x111cc /* 8 bits */ +#define MEMSTAT_ILK 0x111f8 +#define MEMSTAT_VID_MASK 0x7f00 +#define MEMSTAT_VID_SHIFT 8 +#define MEMSTAT_PSTATE_MASK 0x00f8 +#define MEMSTAT_PSTATE_SHIFT 3 +#define MEMSTAT_MON_ACTV (1<<2) +#define MEMSTAT_SRC_CTL_MASK 0x0003 +#define MEMSTAT_SRC_CTL_CORE 0 +#define MEMSTAT_SRC_CTL_TRB 1 +#define MEMSTAT_SRC_CTL_THM 2 +#define MEMSTAT_SRC_CTL_STDBY 3 +#define RCPREVBSYTUPAVG 0x113b8 +#define RCPREVBSYTDNAVG 0x113bc #define PEG_BAND_GAP_DATA 0x14d68 /* diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index a3b90c9561dc..2c346645acfa 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -682,6 +682,7 @@ void i915_restore_display(struct drm_device *dev) I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR); I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL); + I915_WRITE(RSTDBYCTL, dev_priv->saveRSTDBYCTL); } else { I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); @@ -745,11 +746,15 @@ int i915_save_state(struct drm_device *dev) dev_priv->saveGTIMR = I915_READ(GTIMR); dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR); dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR); + dev_priv->saveRSTDBYCTL = I915_READ(RSTDBYCTL); } else { dev_priv->saveIER = I915_READ(IER); dev_priv->saveIMR = I915_READ(IMR); } + if (IS_IRONLAKE_M(dev)) + ironlake_disable_drps(dev); + /* Cache mode state */ dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); @@ -820,6 +825,9 @@ int i915_restore_state(struct drm_device *dev) /* Clock gating state */ intel_init_clock_gating(dev); + if (IS_IRONLAKE_M(dev)) + ironlake_enable_drps(dev); + /* Cache mode state */ I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index af9ec217cd1d..4a93f7a0f58d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4616,6 +4616,91 @@ err_unref: return NULL; } +void ironlake_enable_drps(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl; + u8 fmax, fmin, fstart, vstart; + int i = 0; + + /* 100ms RC evaluation intervals */ + I915_WRITE(RCUPEI, 100000); + I915_WRITE(RCDNEI, 100000); + + /* Set max/min thresholds to 90ms and 80ms respectively */ + I915_WRITE(RCBMAXAVG, 90000); + I915_WRITE(RCBMINAVG, 80000); + + I915_WRITE(MEMIHYST, 1); + + /* Set up min, max, and cur for interrupt handling */ + fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; + fmin = (rgvmodectl & MEMMODE_FMIN_MASK); + fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> + MEMMODE_FSTART_SHIFT; + vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> + PXVFREQ_PX_SHIFT; + + dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */ + dev_priv->min_delay = fmin; + dev_priv->cur_delay = fstart; + + I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); + + /* + * Interrupts will be enabled in ironlake_irq_postinstall + */ + + I915_WRITE(VIDSTART, vstart); + POSTING_READ(VIDSTART); + + rgvmodectl |= MEMMODE_SWMODE_EN; + I915_WRITE(MEMMODECTL, rgvmodectl); + + while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) { + if (i++ > 100) { + DRM_ERROR("stuck trying to change perf mode\n"); + break; + } + msleep(1); + } + msleep(1); + + rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | + (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; + I915_WRITE(MEMSWCTL, rgvswctl); + POSTING_READ(MEMSWCTL); + + rgvswctl |= MEMCTL_CMD_STS; + I915_WRITE(MEMSWCTL, rgvswctl); +} + +void ironlake_disable_drps(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u32 rgvswctl; + u8 fstart; + + /* Ack interrupts, disable EFC interrupt */ + I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); + I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); + I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); + I915_WRITE(DEIIR, DE_PCU_EVENT); + I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); + + /* Go back to the starting frequency */ + fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >> + MEMMODE_FSTART_SHIFT; + rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | + (fstart << MEMCTL_FREQ_SHIFT); + I915_WRITE(MEMSWCTL, rgvswctl); + msleep(1); + rgvswctl |= MEMCTL_CMD_STS; + I915_WRITE(MEMSWCTL, rgvswctl); + msleep(1); + +} + void intel_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -4685,8 +4770,8 @@ void intel_init_clock_gating(struct drm_device *dev) if (obj_priv) { I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); - I915_WRITE(MCHBAR_RENDER_STANDBY, - I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); + I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & + ~RCX_SW_EXIT); } } } @@ -4799,11 +4884,6 @@ void intel_modeset_init(struct drm_device *dev) DRM_DEBUG_KMS("%d display pipe%s available.\n", num_pipe, num_pipe > 1 ? "s" : ""); - if (IS_I85X(dev)) - pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock); - else if (IS_I9XX(dev) || IS_G4X(dev)) - pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock); - for (i = 0; i < num_pipe; i++) { intel_crtc_init(dev, i); } @@ -4812,6 +4892,9 @@ void intel_modeset_init(struct drm_device *dev) intel_init_clock_gating(dev); + if (IS_IRONLAKE_M(dev)) + ironlake_enable_drps(dev); + INIT_WORK(&dev_priv->idle_work, intel_idle_update); setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, (unsigned long)dev); @@ -4859,6 +4942,9 @@ void intel_modeset_cleanup(struct drm_device *dev) drm_gem_object_unreference(dev_priv->pwrctx); } + if (IS_IRONLAKE_M(dev)) + ironlake_disable_drps(dev); + mutex_unlock(&dev->struct_mutex); drm_mode_config_cleanup(dev); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index a51573da1ff6..3a467ca57857 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -209,6 +209,8 @@ extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, int regno); extern void intel_init_clock_gating(struct drm_device *dev); +extern void ironlake_enable_drps(struct drm_device *dev); +extern void ironlake_disable_drps(struct drm_device *dev); extern int intel_framebuffer_create(struct drm_device *dev, struct drm_mode_fb_cmd *mode_cmd, -- cgit v1.2.3 From b5b72e891a5a6056c849ef8eaf259f126090f88b Mon Sep 17 00:00:00 2001 From: Matthew Garrett Date: Tue, 2 Feb 2010 18:30:47 +0000 Subject: drm/i915: Deobfuscate the render p-state obfuscation The ironlake render p-state support includes some rather odd variable names. Clean them up in order to improve the readability of the code. Signed-off-by: Matthew Garrett Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_irq.c | 14 +++++++------- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/i915_suspend.c | 6 ++++-- drivers/gpu/drm/i915/intel_display.c | 4 ++-- 5 files changed, 15 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2e493ec1042b..7df89ae8172f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -452,7 +452,7 @@ typedef struct drm_i915_private { u32 savePIPEB_DATA_N1; u32 savePIPEB_LINK_M1; u32 savePIPEB_LINK_N1; - u32 saveRSTDBYCTL; + u32 saveMCHBAR_RENDER_STANDBY; struct { struct drm_mm gtt_space; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 8b35f5e1c511..1a56ae7b5a78 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -272,23 +272,23 @@ static void i915_hotplug_work_func(struct work_struct *work) static void i915_handle_rps_change(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; - u32 slow_up, slow_down, max_avg, min_avg; + u32 busy_up, busy_down, max_avg, min_avg; u16 rgvswctl; u8 new_delay = dev_priv->cur_delay; I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG); - slow_up = I915_READ(RCPREVBSYTUPAVG); - slow_down = I915_READ(RCPREVBSYTDNAVG); + busy_up = I915_READ(RCPREVBSYTUPAVG); + busy_down = I915_READ(RCPREVBSYTDNAVG); max_avg = I915_READ(RCBMAXAVG); min_avg = I915_READ(RCBMINAVG); /* Handle RCS change request from hw */ - if (slow_up > max_avg) { + if (busy_up > max_avg) { if (dev_priv->cur_delay != dev_priv->max_delay) new_delay = dev_priv->cur_delay - 1; if (new_delay < dev_priv->max_delay) new_delay = dev_priv->max_delay; - } else if (slow_down < min_avg) { + } else if (busy_down < min_avg) { if (dev_priv->cur_delay != dev_priv->min_delay) new_delay = dev_priv->cur_delay + 1; if (new_delay > dev_priv->min_delay) @@ -300,8 +300,8 @@ static void i915_handle_rps_change(struct drm_device *dev) rgvswctl = I915_READ(MEMSWCTL); if (rgvswctl & MEMCTL_CMD_STS) { - DRM_ERROR("gpu slow, RCS change rejected\n"); - return; /* still slow with another command */ + DRM_ERROR("gpu busy, RCS change rejected\n"); + return; /* still busy with another command */ } /* Program the new state */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c3948ee37c13..d344c031f188 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -907,7 +907,7 @@ #define RCBMINAVG 0x111a0 #define RCUPEI 0x111b0 #define RCDNEI 0x111b4 -#define RSTDBYCTL 0x111b8 +#define MCHBAR_RENDER_STANDBY 0x111b8 #define RCX_SW_EXIT (1<<23) #define RSX_STATUS_MASK 0x00700000 #define VIDCTL 0x111c0 diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 2c346645acfa..ac0d1a73ac22 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -682,7 +682,8 @@ void i915_restore_display(struct drm_device *dev) I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR); I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL); - I915_WRITE(RSTDBYCTL, dev_priv->saveRSTDBYCTL); + I915_WRITE(MCHBAR_RENDER_STANDBY, + dev_priv->saveMCHBAR_RENDER_STANDBY); } else { I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); @@ -746,7 +747,8 @@ int i915_save_state(struct drm_device *dev) dev_priv->saveGTIMR = I915_READ(GTIMR); dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR); dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR); - dev_priv->saveRSTDBYCTL = I915_READ(RSTDBYCTL); + dev_priv->saveMCHBAR_RENDER_STANDBY = + I915_READ(MCHBAR_RENDER_STANDBY); } else { dev_priv->saveIER = I915_READ(IER); dev_priv->saveIMR = I915_READ(IMR); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4a93f7a0f58d..9e80020ae2fe 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4770,8 +4770,8 @@ void intel_init_clock_gating(struct drm_device *dev) if (obj_priv) { I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); - I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & - ~RCX_SW_EXIT); + I915_WRITE(MCHBAR_RENDER_STANDBY, + I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); } } } -- cgit v1.2.3 From 060e645ac0181f499478a7be0ccb8a5600edc71a Mon Sep 17 00:00:00 2001 From: Li Peng Date: Wed, 10 Feb 2010 01:54:24 +0800 Subject: drm/i915: Fix OGLC performance regression on 945 He Shuang reported an OGLC performance regression introduced in the patch "enable memory self refresh on 9xx", In that patch, SR on 945 is disabled everytime when calling intel_mark_busy(), while too much of such operation will impact performance. Actually disable SR is necessary only when GPU and Crtc changing from idle to busy. This patch make such optimization. It fixes upstream bug http://bugs.freedesktop.org/show_bug.cgi?id=26422 Signed-off-by: Li Peng Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/intel_display.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9e80020ae2fe..cba51c2b512f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4060,18 +4060,17 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) if (!drm_core_check_feature(dev, DRIVER_MODESET)) return; - if (IS_I945G(dev) || IS_I945GM(dev)) { - u32 fw_blc_self; - - DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); - fw_blc_self = I915_READ(FW_BLC_SELF); - fw_blc_self &= ~FW_BLC_SELF_EN; - I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); - } + if (!dev_priv->busy) { + if (IS_I945G(dev) || IS_I945GM(dev)) { + u32 fw_blc_self; - if (!dev_priv->busy) + DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); + fw_blc_self = I915_READ(FW_BLC_SELF); + fw_blc_self &= ~FW_BLC_SELF_EN; + I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); + } dev_priv->busy = true; - else + } else mod_timer(&dev_priv->idle_timer, jiffies + msecs_to_jiffies(GPU_IDLE_TIMEOUT)); @@ -4083,6 +4082,14 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) intel_fb = to_intel_framebuffer(crtc->fb); if (intel_fb->obj == obj) { if (!intel_crtc->busy) { + if (IS_I945G(dev) || IS_I945GM(dev)) { + u32 fw_blc_self; + + DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); + fw_blc_self = I915_READ(FW_BLC_SELF); + fw_blc_self &= ~FW_BLC_SELF_EN; + I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); + } /* Non-busy -> busy, upclock */ intel_increase_pllclock(crtc, true); intel_crtc->busy = true; -- cgit v1.2.3 From 357b13c3e498bb658f511f91a9e4f09c9553be6e Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 4 Feb 2010 14:17:47 -0800 Subject: drm/i915: fix drps disable so unload & re-load works At unload time, we need to disable DRPS, but we need to do it correctly or the GPU will hang and we won't be able to load the module again. So set the SFCAVM bit so we can properly restore the DRPS config at unload. Signed-off-by: Jesse Barnes Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cba51c2b512f..e879885f4754 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4699,7 +4699,7 @@ void ironlake_disable_drps(struct drm_device *dev) fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT; rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | - (fstart << MEMCTL_FREQ_SHIFT); + (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; I915_WRITE(MEMSWCTL, rgvswctl); msleep(1); rgvswctl |= MEMCTL_CMD_STS; -- cgit v1.2.3 From b5e50c3f56ee4aa0d0168eab5ece413ac5df76aa Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Fri, 5 Feb 2010 12:42:41 -0800 Subject: drm/i915: provide FBC status in debugfs Tools like powertop want to check the current FBC status and report it to the user. So add a debugfs file indicating whether FBC is enabled, and if not, why. Signed-off-by: Jesse Barnes Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_debugfs.c | 49 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_dma.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 10 ++++++++ drivers/gpu/drm/i915/intel_display.c | 5 ++++ 4 files changed, 66 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 55340de618ea..96e8b9b2cb32 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -477,6 +477,54 @@ static int i915_drpc_info(struct seq_file *m, void *unused) return 0; } +static int i915_fbc_status(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct drm_crtc *crtc; + drm_i915_private_t *dev_priv = dev->dev_private; + bool fbc_enabled = false; + + if (!dev_priv->display.fbc_enabled) { + seq_printf(m, "FBC unsupported on this chipset\n"); + return 0; + } + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + if (!crtc->enabled) + continue; + if (dev_priv->display.fbc_enabled(crtc)) + fbc_enabled = true; + } + + if (fbc_enabled) { + seq_printf(m, "FBC enabled\n"); + } else { + seq_printf(m, "FBC disabled: "); + switch (dev_priv->no_fbc_reason) { + case FBC_STOLEN_TOO_SMALL: + seq_printf(m, "not enough stolen memory"); + break; + case FBC_UNSUPPORTED_MODE: + seq_printf(m, "mode not supported"); + break; + case FBC_MODE_TOO_LARGE: + seq_printf(m, "mode too large"); + break; + case FBC_BAD_PLANE: + seq_printf(m, "FBC unsupported on plane"); + break; + case FBC_NOT_TILED: + seq_printf(m, "scanout buffer not tiled"); + break; + default: + seq_printf(m, "unknown reason"); + } + seq_printf(m, "\n"); + } + return 0; +} + static int i915_wedged_open(struct inode *inode, struct file *filp) @@ -599,6 +647,7 @@ static struct drm_info_list i915_debugfs_list[] = { {"i915_delayfreq_table", i915_delayfreq_table, 0}, {"i915_inttoext_table", i915_inttoext_table, 0}, {"i915_drpc_info", i915_drpc_info, 0}, + {"i915_fbc_status", i915_fbc_status, 0}, }; #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 3afe361ec552..47805a41395e 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1249,6 +1249,7 @@ static void i915_setup_compression(struct drm_device *dev, int size) /* Leave 1M for line length buffer & misc. */ compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0); if (!compressed_fb) { + dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; i915_warn_stolen(dev); return; } @@ -1256,6 +1257,7 @@ static void i915_setup_compression(struct drm_device *dev, int size) compressed_fb = drm_mm_get_block(compressed_fb, size, 4096); if (!compressed_fb) { i915_warn_stolen(dev); + dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; return; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7df89ae8172f..953ad64e0553 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -192,6 +192,14 @@ struct intel_device_info { u8 cursor_needs_physical : 1; }; +enum no_fbc_reason { + FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ + FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ + FBC_MODE_TOO_LARGE, /* mode too large for compression */ + FBC_BAD_PLANE, /* fbc not supported on plane */ + FBC_NOT_TILED, /* buffer not tiled */ +}; + typedef struct drm_i915_private { struct drm_device *dev; @@ -597,6 +605,8 @@ typedef struct drm_i915_private { u8 cur_delay; u8 min_delay; u8 max_delay; + + enum no_fbc_reason no_fbc_reason; } drm_i915_private_t; /** driver private structure attached to each drm_gem_object */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e879885f4754..a483f41e9f22 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1188,25 +1188,30 @@ static void intel_update_fbc(struct drm_crtc *crtc, if (intel_fb->obj->size > dev_priv->cfb_size) { DRM_DEBUG_KMS("framebuffer too large, disabling " "compression\n"); + dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; goto out_disable; } if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || (mode->flags & DRM_MODE_FLAG_DBLSCAN)) { DRM_DEBUG_KMS("mode incompatible with compression, " "disabling\n"); + dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; goto out_disable; } if ((mode->hdisplay > 2048) || (mode->vdisplay > 1536)) { DRM_DEBUG_KMS("mode too large for compression, disabling\n"); + dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; goto out_disable; } if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) { DRM_DEBUG_KMS("plane not 0, disabling compression\n"); + dev_priv->no_fbc_reason = FBC_BAD_PLANE; goto out_disable; } if (obj_priv->tiling_mode != I915_TILING_X) { DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n"); + dev_priv->no_fbc_reason = FBC_NOT_TILED; goto out_disable; } -- cgit v1.2.3 From 4a9bef37e5cf2c73b61ecc9ead52cad2eb4a372b Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Fri, 5 Feb 2010 12:47:35 -0800 Subject: drm/i915: provide self-refresh status in debugfs Signed-off-by: Jesse Barnes Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 96e8b9b2cb32..56095b3d28ce 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -525,6 +525,26 @@ static int i915_fbc_status(struct seq_file *m, void *unused) return 0; } +static int i915_sr_status(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + bool sr_enabled = false; + + if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev)) + sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; + else if (IS_I915GM(dev)) + sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; + else if (IS_PINEVIEW(dev)) + sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; + + seq_printf(m, "self-refresh: %s\n", sr_enabled ? "enabled" : + "disabled"); + + return 0; +} + static int i915_wedged_open(struct inode *inode, struct file *filp) @@ -648,6 +668,7 @@ static struct drm_info_list i915_debugfs_list[] = { {"i915_inttoext_table", i915_inttoext_table, 0}, {"i915_drpc_info", i915_drpc_info, 0}, {"i915_fbc_status", i915_fbc_status, 0}, + {"i915_sr_status", i915_sr_status, 0}, }; #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) -- cgit v1.2.3 From 4667a4a52ffc3789c45f46096cdffb053591a8e1 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 11 Feb 2010 14:14:42 +0100 Subject: drm/i915: overlay: nuke readback to flush wc caches I retested this and whatever this papered over, the problem doesn't seem to exist anymore. Signed-off-by: Daniel Vetter Reviewed-by: Eric Anholt [anholt: fixed up compile warning] Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/intel_overlay.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 2639591c72e9..1257dc3cb474 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -199,16 +199,11 @@ static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_over static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay) { - struct drm_device *dev = overlay->dev; - drm_i915_private_t *dev_priv = dev->dev_private; - if (OVERLAY_NONPHYSICAL(overlay->dev)) io_mapping_unmap_atomic(overlay->virt_addr); overlay->virt_addr = NULL; - I915_READ(OVADD); /* flush wc cashes */ - return; } -- cgit v1.2.3 From 4f8a567c4666c73284832240db89fdadb2c50bd5 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 11 Feb 2010 14:14:43 +0100 Subject: drm/i915: overlay: drop superflous gpu flushes Cache-coherency is maintained by gem. Drop these leftover MI_FLUSH commands from the userspace code. Signed-off-by: Daniel Vetter Acked-by: Chris Wilson Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/intel_overlay.c | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 1257dc3cb474..f3086fd4773f 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -220,9 +220,7 @@ static int intel_overlay_on(struct intel_overlay *overlay) overlay->active = 1; overlay->hw_wedged = NEEDS_WAIT_FOR_FLIP; - BEGIN_LP_RING(6); - OUT_RING(MI_FLUSH); - OUT_RING(MI_NOOP); + BEGIN_LP_RING(4); OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON); OUT_RING(overlay->flip_addr | OFC_UPDATE); OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); @@ -262,9 +260,7 @@ static void intel_overlay_continue(struct intel_overlay *overlay, if (tmp & (1 << 17)) DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); - BEGIN_LP_RING(4); - OUT_RING(MI_FLUSH); - OUT_RING(MI_NOOP); + BEGIN_LP_RING(2); OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); OUT_RING(flip_addr); ADVANCE_LP_RING(); @@ -333,9 +329,7 @@ static int intel_overlay_off(struct intel_overlay *overlay) /* wait for overlay to go idle */ overlay->hw_wedged = SWITCH_OFF_STAGE_1; - BEGIN_LP_RING(6); - OUT_RING(MI_FLUSH); - OUT_RING(MI_NOOP); + BEGIN_LP_RING(4); OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); OUT_RING(flip_addr); OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); @@ -353,9 +347,7 @@ static int intel_overlay_off(struct intel_overlay *overlay) /* turn overlay off */ overlay->hw_wedged = SWITCH_OFF_STAGE_2; - BEGIN_LP_RING(6); - OUT_RING(MI_FLUSH); - OUT_RING(MI_NOOP); + BEGIN_LP_RING(4); OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF); OUT_RING(flip_addr); OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); @@ -430,9 +422,7 @@ int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay, overlay->hw_wedged = SWITCH_OFF_STAGE_2; - BEGIN_LP_RING(6); - OUT_RING(MI_FLUSH); - OUT_RING(MI_NOOP); + BEGIN_LP_RING(4); OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF); OUT_RING(flip_addr); OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); -- cgit v1.2.3 From af86d4b0f064413d2f353a41cdc23b7dbff0823d Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Wed, 10 Feb 2010 10:39:33 +0800 Subject: agp/intel: official names for Pineview and Ironlake Print official names for Pineview and Ironlake, which is Intel GMA3150 and Intel HD graphics. Signed-off-by: Zhenyu Wang Signed-off-by: Eric Anholt --- drivers/char/agp/intel-agp.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index 3999a5f25f38..e5ffefee34a0 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c @@ -2345,9 +2345,9 @@ static const struct intel_driver_description { NULL, &intel_g33_driver }, { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", NULL, &intel_g33_driver }, - { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "Pineview", + { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "GMA3150", NULL, &intel_g33_driver }, - { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "Pineview", + { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "GMA3150", NULL, &intel_g33_driver }, { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, "GM45", NULL, &intel_i965_driver }, @@ -2362,13 +2362,13 @@ static const struct intel_driver_description { { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, "G41", NULL, &intel_i965_driver }, { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 0, - "Ironlake/D", NULL, &intel_i965_driver }, + "HD Graphics", NULL, &intel_i965_driver }, { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, - "Ironlake/M", NULL, &intel_i965_driver }, + "HD Graphics", NULL, &intel_i965_driver }, { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, - "Ironlake/MA", NULL, &intel_i965_driver }, + "HD Graphics", NULL, &intel_i965_driver }, { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, - "Ironlake/MC2", NULL, &intel_i965_driver }, + "HD Graphics", NULL, &intel_i965_driver }, { 0, 0, 0, NULL, NULL, NULL } }; -- cgit v1.2.3 From 4a7266123fce399f695b62b7f87b467b317f1487 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Mon, 1 Feb 2010 13:59:16 +0100 Subject: drm/i915: move a gtt flush to the correct place No functional change, because gtt flushing is a no-op. Still, try to keep the bookkeeping accurate. The if is still slightly wrong for with execbuf2 even i915-class hw doesn't always need a fence reg for gpu access. But that's for somewhen lateron. Signed-off-by: Daniel Vetter Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 4a141993a37a..a236bfb30844 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2552,12 +2552,12 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj) int ret; i915_gem_object_flush_gpu_write_domain(obj); - i915_gem_object_flush_gtt_write_domain(obj); ret = i915_gem_object_wait_rendering(obj); if (ret != 0) return ret; } + i915_gem_object_flush_gtt_write_domain(obj); i915_gem_clear_fence_reg (obj); return 0; -- cgit v1.2.3 From 10ae9bd25acf394c8fa2f9d795dfa9cec4d19ed6 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Mon, 1 Feb 2010 13:59:17 +0100 Subject: drm/i915: blow away userspace mappings before fence change This aligns it with the other user of i915_gem_clear_fence_reg, which blows away the mapping before changing the fence reg. Only affects userspace if it races against itself when changing tiling parameters, i.e. behaviour is undefined, anyway. Signed-off-by: Daniel Vetter Reviewed-by: Chris Wilson Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_gem.c | 6 ++++++ drivers/gpu/drm/i915/i915_gem_tiling.c | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a236bfb30844..7b12604a9eb8 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2544,6 +2544,12 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj) if (obj_priv->fence_reg == I915_FENCE_REG_NONE) return 0; + /* If we've changed tiling, GTT-mappings of the object + * need to re-fault to ensure that the correct fence register + * setup is in place. + */ + i915_gem_release_mmap(obj); + /* On the i915, GPU access to tiled buffers is via a fence, * therefore we must wait for any outstanding access to complete * before clearing the fence. diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index f308fdf43725..b0cbe3a62f84 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -371,12 +371,6 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, goto err; } - /* If we've changed tiling, GTT-mappings of the object - * need to re-fault to ensure that the correct fence register - * setup is in place. - */ - i915_gem_release_mmap(obj); - obj_priv->tiling_mode = args->tiling_mode; obj_priv->stride = args->stride; } -- cgit v1.2.3 From f590d279eb4978352af163a88b001f156c7147d2 Mon Sep 17 00:00:00 2001 From: Owain Ainsworth Date: Thu, 18 Feb 2010 15:33:00 +0000 Subject: drm/i915: reduce some of the duplication of tiling checking i915_gem_object_fenceable was mostly just a repeat of the i915_gem_object_fence_offset_ok, but also checking the size (which was checkecd when we allowed that BO to be tiled in the first place). So instead, export the latter function and use it in place. Signed-Off-By: Owain G. Ainsworth Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_drv.h | 3 ++- drivers/gpu/drm/i915/i915_gem.c | 3 ++- drivers/gpu/drm/i915/i915_gem_tiling.c | 35 +--------------------------------- 3 files changed, 5 insertions(+), 36 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 953ad64e0553..40b0da37b1f1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -914,7 +914,8 @@ void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); bool i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode); -bool i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj); +bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, + int tiling_mode); /* i915_gem_debug.c */ void i915_gem_dump_object(struct drm_gem_object *obj, int len, diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 7b12604a9eb8..59dcce054d1e 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3253,7 +3253,8 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, obj_priv->tiling_mode != I915_TILING_NONE; /* Check fence reg constraints and rebind if necessary */ - if (need_fence && !i915_obj_fenceable(dev, obj)) + if (need_fence && !i915_gem_object_fence_offset_ok(obj, + obj_priv->tiling_mode)) i915_gem_object_unbind(obj); /* Choose the GTT offset for our buffer and put it there. */ diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index b0cbe3a62f84..ba247d1f9bc7 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -180,39 +180,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) dev_priv->mm.bit_6_swizzle_y = swizzle_y; } - -/** - * Returns whether an object is currently fenceable. If not, it may need - * to be unbound and have its pitch adjusted. - */ -bool -i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj) -{ - struct drm_i915_gem_object *obj_priv = obj->driver_private; - - if (IS_I965G(dev)) { - /* The 965 can have fences at any page boundary. */ - if (obj->size & 4095) - return false; - return true; - } else if (IS_I9XX(dev)) { - if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK) - return false; - } else { - if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK) - return false; - } - - /* Power of two sized... */ - if (obj->size & (obj->size - 1)) - return false; - - /* Objects must be size aligned as well */ - if (obj_priv->gtt_offset & (obj->size - 1)) - return false; - return true; -} - /* Check pitch constriants for all chips & tiling formats */ bool i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) @@ -269,7 +236,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) return true; } -static bool +bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, int tiling_mode) { struct drm_device *dev = obj->dev; -- cgit v1.2.3 From 7b9c5abee98c54f85bcc04bd4d7ec8d5094c73f4 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Fri, 12 Feb 2010 09:30:00 -0800 Subject: drm/i915: give up on 8xx lid status These old machines more often than not lie about their lid state. So don't use it to detect LVDS presence, but leave the event handler to deal with lid open/close, when we might need to reset the mode. Fixes kernel bug #15248 Signed-off-by: Jesse Barnes Cc: stable@kernel.org Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/intel_lvds.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index b1d0acbae4e4..1740577c6173 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -648,8 +648,15 @@ static const struct dmi_system_id bad_lid_status[] = { */ static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector) { + struct drm_device *dev = connector->dev; enum drm_connector_status status = connector_status_connected; + /* ACPI lid methods were generally unreliable in this generation, so + * don't even bother. + */ + if (IS_I8XX(dev)) + return connector_status_connected; + if (!dmi_check_system(bad_lid_status) && !acpi_lid_open()) status = connector_status_disconnected; -- cgit v1.2.3 From 9df30794f609d9412f14cfd0eb7b45dd64d0b14e Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 18 Feb 2010 10:24:56 +0000 Subject: drm/i915: Record batch buffer following GPU error In order to improve our diagnostic capabilities following a GPU hang and subsequent reset, we need to record the batch buffer that triggered the error. We assume that the current batch buffer, plus a few details about what else is on the active list, will be sufficient -- at the very least an improvement over nothing. The extra information is stored in /debug/dri/.../i915_error_state following an error, and may be decoded using intel_gpu_tools/tools/intel_error_decode. v2: Avoid excessive work under spinlocks. v3: Include ringbuffer for later analysis. v4: Use kunmap correctly and record more buffer state. v5: Search ringbuffer for current batch buffer v6: Use a work fn for the impossible IRQ error case. v7: Avoid non-atomic paths whilst in IRQ context. Signed-off-by: Chris Wilson Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_debugfs.c | 85 ++++++++++++++ drivers/gpu/drm/i915/i915_dma.c | 2 + drivers/gpu/drm/i915/i915_drv.h | 21 ++++ drivers/gpu/drm/i915/i915_irq.c | 224 ++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 1 + 5 files changed, 326 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 56095b3d28ce..5eed46312442 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -350,6 +350,36 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data) return 0; } +static const char *pin_flag(int pinned) +{ + if (pinned > 0) + return " P"; + else if (pinned < 0) + return " p"; + else + return ""; +} + +static const char *tiling_flag(int tiling) +{ + switch (tiling) { + default: + case I915_TILING_NONE: return ""; + case I915_TILING_X: return " X"; + case I915_TILING_Y: return " Y"; + } +} + +static const char *dirty_flag(int dirty) +{ + return dirty ? " dirty" : ""; +} + +static const char *purgeable_flag(int purgeable) +{ + return purgeable ? " purgeable" : ""; +} + static int i915_error_state(struct seq_file *m, void *unused) { struct drm_info_node *node = (struct drm_info_node *) m->private; @@ -357,6 +387,7 @@ static int i915_error_state(struct seq_file *m, void *unused) drm_i915_private_t *dev_priv = dev->dev_private; struct drm_i915_error_state *error; unsigned long flags; + int i, page, offset, elt; spin_lock_irqsave(&dev_priv->error_lock, flags); if (!dev_priv->first_error) { @@ -368,6 +399,7 @@ static int i915_error_state(struct seq_file *m, void *unused) seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, error->time.tv_usec); + seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); seq_printf(m, "EIR: 0x%08x\n", error->eir); seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er); seq_printf(m, " INSTPM: 0x%08x\n", error->instpm); @@ -379,6 +411,59 @@ static int i915_error_state(struct seq_file *m, void *unused) seq_printf(m, " INSTPS: 0x%08x\n", error->instps); seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); } + seq_printf(m, "seqno: 0x%08x\n", error->seqno); + + if (error->active_bo_count) { + seq_printf(m, "Buffers [%d]:\n", error->active_bo_count); + + for (i = 0; i < error->active_bo_count; i++) { + seq_printf(m, " %08x %8zd %08x %08x %08x%s%s%s%s", + error->active_bo[i].gtt_offset, + error->active_bo[i].size, + error->active_bo[i].read_domains, + error->active_bo[i].write_domain, + error->active_bo[i].seqno, + pin_flag(error->active_bo[i].pinned), + tiling_flag(error->active_bo[i].tiling), + dirty_flag(error->active_bo[i].dirty), + purgeable_flag(error->active_bo[i].purgeable)); + + if (error->active_bo[i].name) + seq_printf(m, " (name: %d)", error->active_bo[i].name); + if (error->active_bo[i].fence_reg != I915_FENCE_REG_NONE) + seq_printf(m, " (fence: %d)", error->active_bo[i].fence_reg); + + seq_printf(m, "\n"); + } + } + + for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) { + if (error->batchbuffer[i]) { + struct drm_i915_error_object *obj = error->batchbuffer[i]; + + seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset); + offset = 0; + for (page = 0; page < obj->page_count; page++) { + for (elt = 0; elt < PAGE_SIZE/4; elt++) { + seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); + offset += 4; + } + } + } + } + + if (error->ringbuffer) { + struct drm_i915_error_object *obj = error->ringbuffer; + + seq_printf(m, "--- ringbuffer = 0x%08x\n", obj->gtt_offset); + offset = 0; + for (page = 0; page < obj->page_count; page++) { + for (elt = 0; elt < PAGE_SIZE/4; elt++) { + seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); + offset += 4; + } + } + } out: spin_unlock_irqrestore(&dev_priv->error_lock, flags); diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 47805a41395e..dbfe07c90cbc 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1644,6 +1644,8 @@ int i915_driver_unload(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + i915_destroy_error_state(dev); + destroy_workqueue(dev_priv->wq); del_timer_sync(&dev_priv->hangcheck_timer); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 40b0da37b1f1..ec06d4865a5f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -150,7 +150,27 @@ struct drm_i915_error_state { u32 instps; u32 instdone1; u32 seqno; + u64 bbaddr; struct timeval time; + struct drm_i915_error_object { + int page_count; + u32 gtt_offset; + u32 *pages[0]; + } *ringbuffer, *batchbuffer[2]; + struct drm_i915_error_buffer { + size_t size; + u32 name; + u32 seqno; + u32 gtt_offset; + u32 read_domains; + u32 write_domain; + u32 fence_reg; + s32 pinned:2; + u32 tiling:2; + u32 dirty:1; + u32 purgeable:1; + } *active_bo; + u32 active_bo_count; }; struct drm_i915_display_funcs { @@ -778,6 +798,7 @@ extern int i965_reset(struct drm_device *dev, u8 flags); /* i915_irq.c */ void i915_hangcheck_elapsed(unsigned long data); +void i915_destroy_error_state(struct drm_device *dev); extern int i915_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); extern int i915_irq_wait(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 1a56ae7b5a78..ba1d8314c1ce 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -432,6 +432,121 @@ static void i915_error_work_func(struct work_struct *work) } } +static struct drm_i915_error_object * +i915_error_object_create(struct drm_device *dev, + struct drm_gem_object *src) +{ + struct drm_i915_error_object *dst; + struct drm_i915_gem_object *src_priv; + int page, page_count; + + if (src == NULL) + return NULL; + + src_priv = src->driver_private; + if (src_priv->pages == NULL) + return NULL; + + page_count = src->size / PAGE_SIZE; + + dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); + if (dst == NULL) + return NULL; + + for (page = 0; page < page_count; page++) { + void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC); + if (d == NULL) + goto unwind; + s = kmap_atomic(src_priv->pages[page], KM_USER0); + memcpy(d, s, PAGE_SIZE); + kunmap_atomic(s, KM_USER0); + dst->pages[page] = d; + } + dst->page_count = page_count; + dst->gtt_offset = src_priv->gtt_offset; + + return dst; + +unwind: + while (page--) + kfree(dst->pages[page]); + kfree(dst); + return NULL; +} + +static void +i915_error_object_free(struct drm_i915_error_object *obj) +{ + int page; + + if (obj == NULL) + return; + + for (page = 0; page < obj->page_count; page++) + kfree(obj->pages[page]); + + kfree(obj); +} + +static void +i915_error_state_free(struct drm_device *dev, + struct drm_i915_error_state *error) +{ + i915_error_object_free(error->batchbuffer[0]); + i915_error_object_free(error->batchbuffer[1]); + i915_error_object_free(error->ringbuffer); + kfree(error->active_bo); + kfree(error); +} + +static u32 +i915_get_bbaddr(struct drm_device *dev, u32 *ring) +{ + u32 cmd; + + if (IS_I830(dev) || IS_845G(dev)) + cmd = MI_BATCH_BUFFER; + else if (IS_I965G(dev)) + cmd = (MI_BATCH_BUFFER_START | (2 << 6) | + MI_BATCH_NON_SECURE_I965); + else + cmd = (MI_BATCH_BUFFER_START | (2 << 6)); + + return ring[0] == cmd ? ring[1] : 0; +} + +static u32 +i915_ringbuffer_last_batch(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u32 head, bbaddr; + u32 *ring; + + /* Locate the current position in the ringbuffer and walk back + * to find the most recently dispatched batch buffer. + */ + bbaddr = 0; + head = I915_READ(PRB0_HEAD) & HEAD_ADDR; + ring = (u32 *)(dev_priv->ring.virtual_start + head); + + while (--ring >= (u32 *)dev_priv->ring.virtual_start) { + bbaddr = i915_get_bbaddr(dev, ring); + if (bbaddr) + break; + } + + if (bbaddr == 0) { + ring = (u32 *)(dev_priv->ring.virtual_start + dev_priv->ring.Size); + while (--ring >= (u32 *)dev_priv->ring.virtual_start) { + bbaddr = i915_get_bbaddr(dev, ring); + if (bbaddr) + break; + } + } + + return bbaddr; +} + /** * i915_capture_error_state - capture an error record for later analysis * @dev: drm device @@ -444,19 +559,26 @@ static void i915_error_work_func(struct work_struct *work) static void i915_capture_error_state(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_gem_object *obj_priv; struct drm_i915_error_state *error; + struct drm_gem_object *batchbuffer[2]; unsigned long flags; + u32 bbaddr; + int count; spin_lock_irqsave(&dev_priv->error_lock, flags); - if (dev_priv->first_error) - goto out; + error = dev_priv->first_error; + spin_unlock_irqrestore(&dev_priv->error_lock, flags); + if (error) + return; error = kmalloc(sizeof(*error), GFP_ATOMIC); if (!error) { - DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n"); - goto out; + DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); + return; } + error->seqno = i915_get_gem_seqno(dev); error->eir = I915_READ(EIR); error->pgtbl_er = I915_READ(PGTBL_ER); error->pipeastat = I915_READ(PIPEASTAT); @@ -467,6 +589,7 @@ static void i915_capture_error_state(struct drm_device *dev) error->ipehr = I915_READ(IPEHR); error->instdone = I915_READ(INSTDONE); error->acthd = I915_READ(ACTHD); + error->bbaddr = 0; } else { error->ipeir = I915_READ(IPEIR_I965); error->ipehr = I915_READ(IPEHR_I965); @@ -474,14 +597,101 @@ static void i915_capture_error_state(struct drm_device *dev) error->instps = I915_READ(INSTPS); error->instdone1 = I915_READ(INSTDONE1); error->acthd = I915_READ(ACTHD_I965); + error->bbaddr = I915_READ64(BB_ADDR); } - do_gettimeofday(&error->time); + bbaddr = i915_ringbuffer_last_batch(dev); + + /* Grab the current batchbuffer, most likely to have crashed. */ + batchbuffer[0] = NULL; + batchbuffer[1] = NULL; + count = 0; + list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) { + struct drm_gem_object *obj = obj_priv->obj; + + if (batchbuffer[0] == NULL && + bbaddr >= obj_priv->gtt_offset && + bbaddr < obj_priv->gtt_offset + obj->size) + batchbuffer[0] = obj; + + if (batchbuffer[1] == NULL && + error->acthd >= obj_priv->gtt_offset && + error->acthd < obj_priv->gtt_offset + obj->size && + batchbuffer[0] != obj) + batchbuffer[1] = obj; + + count++; + } - dev_priv->first_error = error; + /* We need to copy these to an anonymous buffer as the simplest + * method to avoid being overwritten by userpace. + */ + error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]); + error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]); + + /* Record the ringbuffer */ + error->ringbuffer = i915_error_object_create(dev, dev_priv->ring.ring_obj); + + /* Record buffers on the active list. */ + error->active_bo = NULL; + error->active_bo_count = 0; + + if (count) + error->active_bo = kmalloc(sizeof(*error->active_bo)*count, + GFP_ATOMIC); + + if (error->active_bo) { + int i = 0; + list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) { + struct drm_gem_object *obj = obj_priv->obj; + + error->active_bo[i].size = obj->size; + error->active_bo[i].name = obj->name; + error->active_bo[i].seqno = obj_priv->last_rendering_seqno; + error->active_bo[i].gtt_offset = obj_priv->gtt_offset; + error->active_bo[i].read_domains = obj->read_domains; + error->active_bo[i].write_domain = obj->write_domain; + error->active_bo[i].fence_reg = obj_priv->fence_reg; + error->active_bo[i].pinned = 0; + if (obj_priv->pin_count > 0) + error->active_bo[i].pinned = 1; + if (obj_priv->user_pin_count > 0) + error->active_bo[i].pinned = -1; + error->active_bo[i].tiling = obj_priv->tiling_mode; + error->active_bo[i].dirty = obj_priv->dirty; + error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED; + + if (++i == count) + break; + } + error->active_bo_count = i; + } + + do_gettimeofday(&error->time); -out: + spin_lock_irqsave(&dev_priv->error_lock, flags); + if (dev_priv->first_error == NULL) { + dev_priv->first_error = error; + error = NULL; + } spin_unlock_irqrestore(&dev_priv->error_lock, flags); + + if (error) + i915_error_state_free(dev, error); +} + +void i915_destroy_error_state(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_error_state *error; + + spin_lock(&dev_priv->error_lock); + error = dev_priv->first_error; + dev_priv->first_error = NULL; + spin_unlock(&dev_priv->error_lock); + + if (error) + i915_error_state_free(dev, error); } /** diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d344c031f188..eff8d850a758 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -328,6 +328,7 @@ #define CM0_COLOR_EVICT_DISABLE (1<<3) #define CM0_DEPTH_WRITE_DISABLE (1<<1) #define CM0_RC_OP_FLUSH_DISABLE (1<<0) +#define BB_ADDR 0x02140 /* 8 bytes */ #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ -- cgit v1.2.3 From 7a9f0dd9c49425e2b0e39ada4757bc7a38c84873 Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Mon, 1 Feb 2010 19:11:15 +0200 Subject: drm: Add generic multipart buffer. Allocating multiple pages of memory for data that is coming from user space may fail. To fix memory allocation failures the buffer object should be split to multiple independ pages. drm buffer provides generic interface to copy and process large data arrays from user space. Interface includes allocation and free functions to allocate the buffer object and data storage pages. All access operations are performed relative to a internal pointer which is advanced with drm_buffer_advance function. The buffer can be accessed using drm_buffer_pointer_to_XXX functions if it is known that requested object doesn't split over a page boundary. These functions don't do any error checking to maximize performance. If there is large object which could be split there is special drm_buffer_read_object function. drm_buffer_read_object takes a pointer as argument which is used as temporary store for data if it is split over boundary in the buffer. Signed-off-by: Pauli Nieminen Signed-off-by: Dave Airlie --- drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/drm_buffer.c | 184 +++++++++++++++++++++++++++++++++++++++++++ include/drm/drm_buffer.h | 148 ++++++++++++++++++++++++++++++++++ 3 files changed, 333 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/drm_buffer.c create mode 100644 include/drm/drm_buffer.h (limited to 'drivers') diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 39c5aa75b8f1..abe3f446ca48 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -4,7 +4,7 @@ ccflags-y := -Iinclude/drm -drm-y := drm_auth.o drm_bufs.o drm_cache.o \ +drm-y := drm_auth.o drm_buffer.o drm_bufs.o drm_cache.o \ drm_context.o drm_dma.o drm_drawable.o \ drm_drv.o drm_fops.o drm_gem.o drm_ioctl.o drm_irq.o \ drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \ diff --git a/drivers/gpu/drm/drm_buffer.c b/drivers/gpu/drm/drm_buffer.c new file mode 100644 index 000000000000..55d03ed05000 --- /dev/null +++ b/drivers/gpu/drm/drm_buffer.c @@ -0,0 +1,184 @@ +/************************************************************************** + * + * Copyright 2010 Pauli Nieminen. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * + **************************************************************************/ +/* + * Multipart buffer for coping data which is larger than the page size. + * + * Authors: + * Pauli Nieminen + */ + +#include "drm_buffer.h" + +/** + * Allocate the drm buffer object. + * + * buf: Pointer to a pointer where the object is stored. + * size: The number of bytes to allocate. + */ +int drm_buffer_alloc(struct drm_buffer **buf, int size) +{ + int nr_pages = size / PAGE_SIZE + 1; + int idx; + + /* Allocating pointer table to end of structure makes drm_buffer + * variable sized */ + *buf = kzalloc(sizeof(struct drm_buffer) + nr_pages*sizeof(char *), + GFP_KERNEL); + + if (*buf == NULL) { + DRM_ERROR("Failed to allocate drm buffer object to hold" + " %d bytes in %d pages.\n", + size, nr_pages); + return -ENOMEM; + } + + (*buf)->size = size; + + for (idx = 0; idx < nr_pages; ++idx) { + + (*buf)->data[idx] = + kmalloc(min(PAGE_SIZE, size - idx * PAGE_SIZE), + GFP_KERNEL); + + + if ((*buf)->data[idx] == NULL) { + DRM_ERROR("Failed to allocate %dth page for drm" + " buffer with %d bytes and %d pages.\n", + idx + 1, size, nr_pages); + goto error_out; + } + + } + + return 0; + +error_out: + + /* Only last element can be null pointer so check for it first. */ + if ((*buf)->data[idx]) + kfree((*buf)->data[idx]); + + for (--idx; idx >= 0; --idx) + kfree((*buf)->data[idx]); + + kfree(*buf); + return -ENOMEM; +} +EXPORT_SYMBOL(drm_buffer_alloc); + +/** + * Copy the user data to the begin of the buffer and reset the processing + * iterator. + * + * user_data: A pointer the data that is copied to the buffer. + * size: The Number of bytes to copy. + */ +extern int drm_buffer_copy_from_user(struct drm_buffer *buf, + void __user *user_data, int size) +{ + int nr_pages = size / PAGE_SIZE + 1; + int idx; + + if (size > buf->size) { + DRM_ERROR("Requesting to copy %d bytes to a drm buffer with" + " %d bytes space\n", + size, buf->size); + return -EFAULT; + } + + for (idx = 0; idx < nr_pages; ++idx) { + + if (DRM_COPY_FROM_USER(buf->data[idx], + user_data + idx * PAGE_SIZE, + min(PAGE_SIZE, size - idx * PAGE_SIZE))) { + DRM_ERROR("Failed to copy user data (%p) to drm buffer" + " (%p) %dth page.\n", + user_data, buf, idx); + return -EFAULT; + + } + } + buf->iterator = 0; + return 0; +} +EXPORT_SYMBOL(drm_buffer_copy_from_user); + +/** + * Free the drm buffer object + */ +void drm_buffer_free(struct drm_buffer *buf) +{ + + if (buf != NULL) { + + int nr_pages = buf->size / PAGE_SIZE + 1; + int idx; + for (idx = 0; idx < nr_pages; ++idx) + kfree(buf->data[idx]); + + kfree(buf); + } +} +EXPORT_SYMBOL(drm_buffer_free); + +/** + * Read an object from buffer that may be split to multiple parts. If object + * is not split function just returns the pointer to object in buffer. But in + * case of split object data is copied to given stack object that is suplied + * by caller. + * + * The processing location of the buffer is also advanced to the next byte + * after the object. + * + * objsize: The size of the objet in bytes. + * stack_obj: A pointer to a memory location where object can be copied. + */ +void *drm_buffer_read_object(struct drm_buffer *buf, + int objsize, void *stack_obj) +{ + int idx = drm_buffer_index(buf); + int page = drm_buffer_page(buf); + void *obj = 0; + + if (idx + objsize <= PAGE_SIZE) { + obj = &buf->data[page][idx]; + } else { + /* The object is split which forces copy to temporary object.*/ + int beginsz = PAGE_SIZE - idx; + memcpy(stack_obj, &buf->data[page][idx], beginsz); + + memcpy(stack_obj + beginsz, &buf->data[page + 1][0], + objsize - beginsz); + + obj = stack_obj; + } + + drm_buffer_advance(buf, objsize); + return obj; +} +EXPORT_SYMBOL(drm_buffer_read_object); diff --git a/include/drm/drm_buffer.h b/include/drm/drm_buffer.h new file mode 100644 index 000000000000..322dbff3f861 --- /dev/null +++ b/include/drm/drm_buffer.h @@ -0,0 +1,148 @@ +/************************************************************************** + * + * Copyright 2010 Pauli Nieminen. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * + **************************************************************************/ +/* + * Multipart buffer for coping data which is larger than the page size. + * + * Authors: + * Pauli Nieminen + */ + +#ifndef _DRM_BUFFER_H_ +#define _DRM_BUFFER_H_ + +#include "drmP.h" + +struct drm_buffer { + int iterator; + int size; + char *data[]; +}; + + +/** + * Return the index of page that buffer is currently pointing at. + */ +static inline int drm_buffer_page(struct drm_buffer *buf) +{ + return buf->iterator / PAGE_SIZE; +} +/** + * Return the index of the current byte in the page + */ +static inline int drm_buffer_index(struct drm_buffer *buf) +{ + return buf->iterator & (PAGE_SIZE - 1); +} +/** + * Return number of bytes that is left to process + */ +static inline int drm_buffer_unprocessed(struct drm_buffer *buf) +{ + return buf->size - buf->iterator; +} + +/** + * Advance the buffer iterator number of bytes that is given. + */ +static inline void drm_buffer_advance(struct drm_buffer *buf, int bytes) +{ + buf->iterator += bytes; +} + +/** + * Allocate the drm buffer object. + * + * buf: A pointer to a pointer where the object is stored. + * size: The number of bytes to allocate. + */ +extern int drm_buffer_alloc(struct drm_buffer **buf, int size); + +/** + * Copy the user data to the begin of the buffer and reset the processing + * iterator. + * + * user_data: A pointer the data that is copied to the buffer. + * size: The Number of bytes to copy. + */ +extern int drm_buffer_copy_from_user(struct drm_buffer *buf, + void __user *user_data, int size); + +/** + * Free the drm buffer object + */ +extern void drm_buffer_free(struct drm_buffer *buf); + +/** + * Read an object from buffer that may be split to multiple parts. If object + * is not split function just returns the pointer to object in buffer. But in + * case of split object data is copied to given stack object that is suplied + * by caller. + * + * The processing location of the buffer is also advanced to the next byte + * after the object. + * + * objsize: The size of the objet in bytes. + * stack_obj: A pointer to a memory location where object can be copied. + */ +extern void *drm_buffer_read_object(struct drm_buffer *buf, + int objsize, void *stack_obj); + +/** + * Returns the pointer to the dword which is offset number of elements from the + * current processing location. + * + * Caller must make sure that dword is not split in the buffer. This + * requirement is easily met if all the sizes of objects in buffer are + * multiples of dword and PAGE_SIZE is multiple dword. + * + * Call to this function doesn't change the processing location. + * + * offset: The index of the dword relative to the internat iterator. + */ +static inline void *drm_buffer_pointer_to_dword(struct drm_buffer *buffer, + int offset) +{ + int iter = buffer->iterator + offset * 4; + return &buffer->data[iter / PAGE_SIZE][iter & (PAGE_SIZE - 1)]; +} +/** + * Returns the pointer to the dword which is offset number of elements from + * the current processing location. + * + * Call to this function doesn't change the processing location. + * + * offset: The index of the byte relative to the internat iterator. + */ +static inline void *drm_buffer_pointer_to_byte(struct drm_buffer *buffer, + int offset) +{ + int iter = buffer->iterator + offset; + return &buffer->data[iter / PAGE_SIZE][iter & (PAGE_SIZE - 1)]; +} + +#endif -- cgit v1.2.3 From b4fe945405e477cded91772b4fec854705443dd5 Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Mon, 1 Feb 2010 19:11:16 +0200 Subject: drm/radeon: Fix memory allocation failures in the preKMS command stream checking. Allocation of single large block of memory may fail under memory presure. drm_buffer object can hold one large block of data in multiple independ pages which preents alloation failures. This patch converts all access to command stream to use drm_buffer interface. All direct access to array has to go tough drm_buffer functions to get correct pointer. Outputting the command stream to ring buffer needs to be awear of the split nature of drm_buffer. The output operation requires the new OUT_RING_DRM_BUFFER. Signed-off-by: Pauli Nieminen Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r300_cmdbuf.c | 280 ++++++++++++++++------------------ drivers/gpu/drm/radeon/radeon_drv.h | 32 +++- drivers/gpu/drm/radeon/radeon_state.c | 197 ++++++++++++------------ 3 files changed, 262 insertions(+), 247 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c index 34bffa0e4b73..7f59352cd637 100644 --- a/drivers/gpu/drm/radeon/r300_cmdbuf.c +++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c @@ -33,6 +33,7 @@ #include "drmP.h" #include "drm.h" +#include "drm_buffer.h" #include "radeon_drm.h" #include "radeon_drv.h" #include "r300_reg.h" @@ -299,46 +300,42 @@ static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t * int reg; int sz; int i; - int values[64]; + u32 *value; RING_LOCALS; sz = header.packet0.count; reg = (header.packet0.reghi << 8) | header.packet0.reglo; if ((sz > 64) || (sz < 0)) { - DRM_ERROR - ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n", - reg, sz); + DRM_ERROR("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n", + reg, sz); return -EINVAL; } + for (i = 0; i < sz; i++) { - values[i] = ((int *)cmdbuf->buf)[i]; switch (r300_reg_flags[(reg >> 2) + i]) { case MARK_SAFE: break; case MARK_CHECK_OFFSET: - if (!radeon_check_offset(dev_priv, (u32) values[i])) { - DRM_ERROR - ("Offset failed range check (reg=%04x sz=%d)\n", - reg, sz); + value = drm_buffer_pointer_to_dword(cmdbuf->buffer, i); + if (!radeon_check_offset(dev_priv, *value)) { + DRM_ERROR("Offset failed range check (reg=%04x sz=%d)\n", + reg, sz); return -EINVAL; } break; default: DRM_ERROR("Register %04x failed check as flag=%02x\n", - reg + i * 4, r300_reg_flags[(reg >> 2) + i]); + reg + i * 4, r300_reg_flags[(reg >> 2) + i]); return -EINVAL; } } BEGIN_RING(1 + sz); OUT_RING(CP_PACKET0(reg, sz - 1)); - OUT_RING_TABLE(values, sz); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz); ADVANCE_RING(); - cmdbuf->buf += sz * 4; - cmdbuf->bufsz -= sz * 4; - return 0; } @@ -362,7 +359,7 @@ static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv, if (!sz) return 0; - if (sz * 4 > cmdbuf->bufsz) + if (sz * 4 > drm_buffer_unprocessed(cmdbuf->buffer)) return -EINVAL; if (reg + sz * 4 >= 0x10000) { @@ -380,12 +377,9 @@ static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv, BEGIN_RING(1 + sz); OUT_RING(CP_PACKET0(reg, sz - 1)); - OUT_RING_TABLE((int *)cmdbuf->buf, sz); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz); ADVANCE_RING(); - cmdbuf->buf += sz * 4; - cmdbuf->bufsz -= sz * 4; - return 0; } @@ -407,7 +401,7 @@ static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv, if (!sz) return 0; - if (sz * 16 > cmdbuf->bufsz) + if (sz * 16 > drm_buffer_unprocessed(cmdbuf->buffer)) return -EINVAL; /* VAP is very sensitive so we purge cache before we program it @@ -426,7 +420,7 @@ static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv, BEGIN_RING(3 + sz * 4); OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr); OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1)); - OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz * 4); ADVANCE_RING(); BEGIN_RING(2); @@ -434,9 +428,6 @@ static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv, OUT_RING(0); ADVANCE_RING(); - cmdbuf->buf += sz * 16; - cmdbuf->bufsz -= sz * 16; - return 0; } @@ -449,14 +440,14 @@ static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv, { RING_LOCALS; - if (8 * 4 > cmdbuf->bufsz) + if (8 * 4 > drm_buffer_unprocessed(cmdbuf->buffer)) return -EINVAL; BEGIN_RING(10); OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | (1 << R300_PRIM_NUM_VERTICES_SHIFT)); - OUT_RING_TABLE((int *)cmdbuf->buf, 8); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, 8); ADVANCE_RING(); BEGIN_RING(4); @@ -468,9 +459,6 @@ static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv, /* set flush flag */ dev_priv->track_flush |= RADEON_FLUSH_EMITED; - cmdbuf->buf += 8 * 4; - cmdbuf->bufsz -= 8 * 4; - return 0; } @@ -480,28 +468,29 @@ static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, { int count, i, k; #define MAX_ARRAY_PACKET 64 - u32 payload[MAX_ARRAY_PACKET]; + u32 *data; u32 narrays; RING_LOCALS; - count = (header >> 16) & 0x3fff; + count = (header & RADEON_CP_PACKET_COUNT_MASK) >> 16; if ((count + 1) > MAX_ARRAY_PACKET) { DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", count); return -EINVAL; } - memset(payload, 0, MAX_ARRAY_PACKET * 4); - memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4); - /* carefully check packet contents */ - narrays = payload[0]; + /* We have already read the header so advance the buffer. */ + drm_buffer_advance(cmdbuf->buffer, 4); + + narrays = *(u32 *)drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); k = 0; i = 1; while ((k < narrays) && (i < (count + 1))) { i++; /* skip attribute field */ - if (!radeon_check_offset(dev_priv, payload[i])) { + data = drm_buffer_pointer_to_dword(cmdbuf->buffer, i); + if (!radeon_check_offset(dev_priv, *data)) { DRM_ERROR ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", k, i); @@ -512,7 +501,8 @@ static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, if (k == narrays) break; /* have one more to process, they come in pairs */ - if (!radeon_check_offset(dev_priv, payload[i])) { + data = drm_buffer_pointer_to_dword(cmdbuf->buffer, i); + if (!radeon_check_offset(dev_priv, *data)) { DRM_ERROR ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", k, i); @@ -533,30 +523,30 @@ static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, BEGIN_RING(count + 2); OUT_RING(header); - OUT_RING_TABLE(payload, count + 1); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, count + 1); ADVANCE_RING(); - cmdbuf->buf += (count + 2) * 4; - cmdbuf->bufsz -= (count + 2) * 4; - return 0; } static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv, drm_radeon_kcmd_buffer_t *cmdbuf) { - u32 *cmd = (u32 *) cmdbuf->buf; + u32 *cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); int count, ret; RING_LOCALS; - count=(cmd[0]>>16) & 0x3fff; - if (cmd[0] & 0x8000) { - u32 offset; + count = (*cmd & RADEON_CP_PACKET_COUNT_MASK) >> 16; - if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL + if (*cmd & 0x8000) { + u32 offset; + u32 *cmd1 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1); + if (*cmd1 & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { - offset = cmd[2] << 10; + + u32 *cmd2 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2); + offset = *cmd2 << 10; ret = !radeon_check_offset(dev_priv, offset); if (ret) { DRM_ERROR("Invalid bitblt first offset is %08X\n", offset); @@ -564,9 +554,10 @@ static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv, } } - if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && - (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { - offset = cmd[3] << 10; + if ((*cmd1 & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && + (*cmd1 & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { + u32 *cmd3 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 3); + offset = *cmd3 << 10; ret = !radeon_check_offset(dev_priv, offset); if (ret) { DRM_ERROR("Invalid bitblt second offset is %08X\n", offset); @@ -577,28 +568,25 @@ static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv, } BEGIN_RING(count+2); - OUT_RING(cmd[0]); - OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, count + 2); ADVANCE_RING(); - cmdbuf->buf += (count+2)*4; - cmdbuf->bufsz -= (count+2)*4; - return 0; } static __inline__ int r300_emit_draw_indx_2(drm_radeon_private_t *dev_priv, drm_radeon_kcmd_buffer_t *cmdbuf) { - u32 *cmd; + u32 *cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); + u32 *cmd1 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1); int count; int expected_count; RING_LOCALS; - cmd = (u32 *) cmdbuf->buf; - count = (cmd[0]>>16) & 0x3fff; - expected_count = cmd[1] >> 16; - if (!(cmd[1] & R300_VAP_VF_CNTL__INDEX_SIZE_32bit)) + count = (*cmd & RADEON_CP_PACKET_COUNT_MASK) >> 16; + + expected_count = *cmd1 >> 16; + if (!(*cmd1 & R300_VAP_VF_CNTL__INDEX_SIZE_32bit)) expected_count = (expected_count+1)/2; if (count && count != expected_count) { @@ -608,55 +596,53 @@ static __inline__ int r300_emit_draw_indx_2(drm_radeon_private_t *dev_priv, } BEGIN_RING(count+2); - OUT_RING(cmd[0]); - OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, count + 2); ADVANCE_RING(); - cmdbuf->buf += (count+2)*4; - cmdbuf->bufsz -= (count+2)*4; - if (!count) { - drm_r300_cmd_header_t header; + drm_r300_cmd_header_t stack_header, *header; + u32 *cmd1, *cmd2, *cmd3; - if (cmdbuf->bufsz < 4*4 + sizeof(header)) { + if (drm_buffer_unprocessed(cmdbuf->buffer) + < 4*4 + sizeof(stack_header)) { DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER, but stream is too short.\n"); return -EINVAL; } - header.u = *(unsigned int *)cmdbuf->buf; + header = drm_buffer_read_object(cmdbuf->buffer, + sizeof(stack_header), &stack_header); - cmdbuf->buf += sizeof(header); - cmdbuf->bufsz -= sizeof(header); - cmd = (u32 *) cmdbuf->buf; + cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); + cmd1 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1); + cmd2 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2); + cmd3 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 3); - if (header.header.cmd_type != R300_CMD_PACKET3 || - header.packet3.packet != R300_CMD_PACKET3_RAW || - cmd[0] != CP_PACKET3(RADEON_CP_INDX_BUFFER, 2)) { + if (header->header.cmd_type != R300_CMD_PACKET3 || + header->packet3.packet != R300_CMD_PACKET3_RAW || + *cmd != CP_PACKET3(RADEON_CP_INDX_BUFFER, 2)) { DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER.\n"); return -EINVAL; } - if ((cmd[1] & 0x8000ffff) != 0x80000810) { - DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]); + if ((*cmd1 & 0x8000ffff) != 0x80000810) { + DRM_ERROR("Invalid indx_buffer reg address %08X\n", + *cmd1); return -EINVAL; } - if (!radeon_check_offset(dev_priv, cmd[2])) { - DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]); + if (!radeon_check_offset(dev_priv, *cmd2)) { + DRM_ERROR("Invalid indx_buffer offset is %08X\n", + *cmd2); return -EINVAL; } - if (cmd[3] != expected_count) { + if (*cmd3 != expected_count) { DRM_ERROR("INDX_BUFFER: buffer size %i, expected %i\n", - cmd[3], expected_count); + *cmd3, expected_count); return -EINVAL; } BEGIN_RING(4); - OUT_RING(cmd[0]); - OUT_RING_TABLE((int *)(cmdbuf->buf + 4), 3); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, 4); ADVANCE_RING(); - - cmdbuf->buf += 4*4; - cmdbuf->bufsz -= 4*4; } return 0; @@ -665,39 +651,39 @@ static __inline__ int r300_emit_draw_indx_2(drm_radeon_private_t *dev_priv, static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, drm_radeon_kcmd_buffer_t *cmdbuf) { - u32 header; + u32 *header; int count; RING_LOCALS; - if (4 > cmdbuf->bufsz) + if (4 > drm_buffer_unprocessed(cmdbuf->buffer)) return -EINVAL; /* Fixme !! This simply emits a packet without much checking. We need to be smarter. */ /* obtain first word - actual packet3 header */ - header = *(u32 *) cmdbuf->buf; + header = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); /* Is it packet 3 ? */ - if ((header >> 30) != 0x3) { - DRM_ERROR("Not a packet3 header (0x%08x)\n", header); + if ((*header >> 30) != 0x3) { + DRM_ERROR("Not a packet3 header (0x%08x)\n", *header); return -EINVAL; } - count = (header >> 16) & 0x3fff; + count = (*header >> 16) & 0x3fff; /* Check again now that we know how much data to expect */ - if ((count + 2) * 4 > cmdbuf->bufsz) { + if ((count + 2) * 4 > drm_buffer_unprocessed(cmdbuf->buffer)) { DRM_ERROR ("Expected packet3 of length %d but have only %d bytes left\n", - (count + 2) * 4, cmdbuf->bufsz); + (count + 2) * 4, drm_buffer_unprocessed(cmdbuf->buffer)); return -EINVAL; } /* Is it a packet type we know about ? */ - switch (header & 0xff00) { + switch (*header & 0xff00) { case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */ - return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header); + return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, *header); case RADEON_CNTL_BITBLT_MULTI: return r300_emit_bitblt_multi(dev_priv, cmdbuf); @@ -723,18 +709,14 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, /* these packets are safe */ break; default: - DRM_ERROR("Unknown packet3 header (0x%08x)\n", header); + DRM_ERROR("Unknown packet3 header (0x%08x)\n", *header); return -EINVAL; } BEGIN_RING(count + 2); - OUT_RING(header); - OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, count + 2); ADVANCE_RING(); - cmdbuf->buf += (count + 2) * 4; - cmdbuf->bufsz -= (count + 2) * 4; - return 0; } @@ -748,8 +730,7 @@ static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv, { int n; int ret; - char *orig_buf = cmdbuf->buf; - int orig_bufsz = cmdbuf->bufsz; + int orig_iter = cmdbuf->buffer->iterator; /* This is a do-while-loop so that we run the interior at least once, * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale. @@ -761,8 +742,7 @@ static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv, if (ret) return ret; - cmdbuf->buf = orig_buf; - cmdbuf->bufsz = orig_bufsz; + cmdbuf->buffer->iterator = orig_iter; } switch (header.packet3.packet) { @@ -785,9 +765,9 @@ static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv, break; default: - DRM_ERROR("bad packet3 type %i at %p\n", + DRM_ERROR("bad packet3 type %i at byte %d\n", header.packet3.packet, - cmdbuf->buf - sizeof(header)); + cmdbuf->buffer->iterator - sizeof(header)); return -EINVAL; } @@ -923,12 +903,13 @@ static int r300_scratch(drm_radeon_private_t *dev_priv, drm_r300_cmd_header_t header) { u32 *ref_age_base; - u32 i, buf_idx, h_pending; - u64 ptr_addr; + u32 i, *buf_idx, h_pending; + u64 *ptr_addr; + u64 stack_ptr_addr; RING_LOCALS; - if (cmdbuf->bufsz < - (sizeof(u64) + header.scratch.n_bufs * sizeof(buf_idx))) { + if (drm_buffer_unprocessed(cmdbuf->buffer) < + (sizeof(u64) + header.scratch.n_bufs * sizeof(*buf_idx))) { return -EINVAL; } @@ -938,36 +919,35 @@ static int r300_scratch(drm_radeon_private_t *dev_priv, dev_priv->scratch_ages[header.scratch.reg]++; - ptr_addr = get_unaligned((u64 *)cmdbuf->buf); - ref_age_base = (u32 *)(unsigned long)ptr_addr; - - cmdbuf->buf += sizeof(u64); - cmdbuf->bufsz -= sizeof(u64); + ptr_addr = drm_buffer_read_object(cmdbuf->buffer, + sizeof(stack_ptr_addr), &stack_ptr_addr); + ref_age_base = (u32 *)(unsigned long)*ptr_addr; for (i=0; i < header.scratch.n_bufs; i++) { - buf_idx = *(u32 *)cmdbuf->buf; - buf_idx *= 2; /* 8 bytes per buf */ + buf_idx = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); + *buf_idx *= 2; /* 8 bytes per buf */ - if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) { + if (DRM_COPY_TO_USER(ref_age_base + *buf_idx, + &dev_priv->scratch_ages[header.scratch.reg], + sizeof(u32))) return -EINVAL; - } - if (DRM_COPY_FROM_USER(&h_pending, ref_age_base + buf_idx + 1, sizeof(u32))) { + if (DRM_COPY_FROM_USER(&h_pending, + ref_age_base + *buf_idx + 1, + sizeof(u32))) return -EINVAL; - } - if (h_pending == 0) { + if (h_pending == 0) return -EINVAL; - } h_pending--; - if (DRM_COPY_TO_USER(ref_age_base + buf_idx + 1, &h_pending, sizeof(u32))) { + if (DRM_COPY_TO_USER(ref_age_base + *buf_idx + 1, + &h_pending, + sizeof(u32))) return -EINVAL; - } - cmdbuf->buf += sizeof(buf_idx); - cmdbuf->bufsz -= sizeof(buf_idx); + drm_buffer_advance(cmdbuf->buffer, sizeof(*buf_idx)); } BEGIN_RING(2); @@ -1009,19 +989,16 @@ static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv, DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type); if (!sz) return 0; - if (sz * stride * 4 > cmdbuf->bufsz) + if (sz * stride * 4 > drm_buffer_unprocessed(cmdbuf->buffer)) return -EINVAL; BEGIN_RING(3 + sz * stride); OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr); OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1)); - OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz * stride); ADVANCE_RING(); - cmdbuf->buf += sz * stride * 4; - cmdbuf->bufsz -= sz * stride * 4; - return 0; } @@ -1053,19 +1030,18 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, goto cleanup; } - while (cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) { + while (drm_buffer_unprocessed(cmdbuf->buffer) + >= sizeof(drm_r300_cmd_header_t)) { int idx; - drm_r300_cmd_header_t header; - - header.u = *(unsigned int *)cmdbuf->buf; + drm_r300_cmd_header_t *header, stack_header; - cmdbuf->buf += sizeof(header); - cmdbuf->bufsz -= sizeof(header); + header = drm_buffer_read_object(cmdbuf->buffer, + sizeof(stack_header), &stack_header); - switch (header.header.cmd_type) { + switch (header->header.cmd_type) { case R300_CMD_PACKET0: DRM_DEBUG("R300_CMD_PACKET0\n"); - ret = r300_emit_packet0(dev_priv, cmdbuf, header); + ret = r300_emit_packet0(dev_priv, cmdbuf, *header); if (ret) { DRM_ERROR("r300_emit_packet0 failed\n"); goto cleanup; @@ -1074,7 +1050,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, case R300_CMD_VPU: DRM_DEBUG("R300_CMD_VPU\n"); - ret = r300_emit_vpu(dev_priv, cmdbuf, header); + ret = r300_emit_vpu(dev_priv, cmdbuf, *header); if (ret) { DRM_ERROR("r300_emit_vpu failed\n"); goto cleanup; @@ -1083,7 +1059,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, case R300_CMD_PACKET3: DRM_DEBUG("R300_CMD_PACKET3\n"); - ret = r300_emit_packet3(dev_priv, cmdbuf, header); + ret = r300_emit_packet3(dev_priv, cmdbuf, *header); if (ret) { DRM_ERROR("r300_emit_packet3 failed\n"); goto cleanup; @@ -1117,8 +1093,8 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, int i; RING_LOCALS; - BEGIN_RING(header.delay.count); - for (i = 0; i < header.delay.count; i++) + BEGIN_RING(header->delay.count); + for (i = 0; i < header->delay.count; i++) OUT_RING(RADEON_CP_PACKET2); ADVANCE_RING(); } @@ -1126,7 +1102,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, case R300_CMD_DMA_DISCARD: DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); - idx = header.dma.buf_idx; + idx = header->dma.buf_idx; if (idx < 0 || idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", idx, dma->buf_count - 1); @@ -1149,12 +1125,12 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, case R300_CMD_WAIT: DRM_DEBUG("R300_CMD_WAIT\n"); - r300_cmd_wait(dev_priv, header); + r300_cmd_wait(dev_priv, *header); break; case R300_CMD_SCRATCH: DRM_DEBUG("R300_CMD_SCRATCH\n"); - ret = r300_scratch(dev_priv, cmdbuf, header); + ret = r300_scratch(dev_priv, cmdbuf, *header); if (ret) { DRM_ERROR("r300_scratch failed\n"); goto cleanup; @@ -1168,16 +1144,16 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, goto cleanup; } DRM_DEBUG("R300_CMD_R500FP\n"); - ret = r300_emit_r500fp(dev_priv, cmdbuf, header); + ret = r300_emit_r500fp(dev_priv, cmdbuf, *header); if (ret) { DRM_ERROR("r300_emit_r500fp failed\n"); goto cleanup; } break; default: - DRM_ERROR("bad cmd_type %i at %p\n", - header.header.cmd_type, - cmdbuf->buf - sizeof(header)); + DRM_ERROR("bad cmd_type %i at byte %d\n", + header->header.cmd_type, + cmdbuf->buffer->iterator - sizeof(*header)); ret = -EINVAL; goto cleanup; } diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index b058316e311f..f6d20cee5705 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h @@ -312,9 +312,11 @@ typedef struct drm_radeon_buf_priv { u32 age; } drm_radeon_buf_priv_t; +struct drm_buffer; + typedef struct drm_radeon_kcmd_buffer { int bufsz; - char *buf; + struct drm_buffer *buffer; int nbox; struct drm_clip_rect __user *boxes; } drm_radeon_kcmd_buffer_t; @@ -2124,4 +2126,32 @@ extern void radeon_commit_ring(drm_radeon_private_t *dev_priv); write &= mask; \ } while (0) +/** + * Copy given number of dwords from drm buffer to the ring buffer. + */ +#define OUT_RING_DRM_BUFFER(buf, sz) do { \ + int _size = (sz) * 4; \ + struct drm_buffer *_buf = (buf); \ + int _part_size; \ + while (_size > 0) { \ + _part_size = _size; \ + \ + if (write + _part_size/4 > mask) \ + _part_size = ((mask + 1) - write)*4; \ + \ + if (drm_buffer_index(_buf) + _part_size > PAGE_SIZE) \ + _part_size = PAGE_SIZE - drm_buffer_index(_buf);\ + \ + \ + \ + memcpy(ring + write, &_buf->data[drm_buffer_page(_buf)] \ + [drm_buffer_index(_buf)], _part_size); \ + \ + _size -= _part_size; \ + write = (write + _part_size/4) & mask; \ + drm_buffer_advance(_buf, _part_size); \ + } \ +} while (0) + + #endif /* __RADEON_DRV_H__ */ diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c index 38537d971a3e..44b6d66b0ab3 100644 --- a/drivers/gpu/drm/radeon/radeon_state.c +++ b/drivers/gpu/drm/radeon/radeon_state.c @@ -29,6 +29,7 @@ #include "drmP.h" #include "drm.h" +#include "drm_buffer.h" #include "drm_sarea.h" #include "radeon_drm.h" #include "radeon_drv.h" @@ -91,21 +92,26 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * dev_priv, struct drm_file *file_priv, - int id, u32 *data) + int id, struct drm_buffer *buf) { + u32 *data; switch (id) { case RADEON_EMIT_PP_MISC: - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) { + data = drm_buffer_pointer_to_dword(buf, + (RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4); + + if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) { DRM_ERROR("Invalid depth buffer offset\n"); return -EINVAL; } break; case RADEON_EMIT_PP_CNTL: - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) { + data = drm_buffer_pointer_to_dword(buf, + (RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4); + + if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) { DRM_ERROR("Invalid colour buffer offset\n"); return -EINVAL; } @@ -117,8 +123,8 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * case R200_EMIT_PP_TXOFFSET_3: case R200_EMIT_PP_TXOFFSET_4: case R200_EMIT_PP_TXOFFSET_5: - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &data[0])) { + data = drm_buffer_pointer_to_dword(buf, 0); + if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) { DRM_ERROR("Invalid R200 texture offset\n"); return -EINVAL; } @@ -127,8 +133,9 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * case RADEON_EMIT_PP_TXFILTER_0: case RADEON_EMIT_PP_TXFILTER_1: case RADEON_EMIT_PP_TXFILTER_2: - if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) { + data = drm_buffer_pointer_to_dword(buf, + (RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4); + if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) { DRM_ERROR("Invalid R100 texture offset\n"); return -EINVAL; } @@ -142,9 +149,10 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * case R200_EMIT_PP_CUBIC_OFFSETS_5:{ int i; for (i = 0; i < 5; i++) { + data = drm_buffer_pointer_to_dword(buf, i); if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &data[i])) { + data)) { DRM_ERROR ("Invalid R200 cubic texture offset\n"); return -EINVAL; @@ -158,9 +166,10 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{ int i; for (i = 0; i < 5; i++) { + data = drm_buffer_pointer_to_dword(buf, i); if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &data[i])) { + data)) { DRM_ERROR ("Invalid R100 cubic texture offset\n"); return -EINVAL; @@ -269,23 +278,24 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * cmdbuf, unsigned int *cmdsz) { - u32 *cmd = (u32 *) cmdbuf->buf; + u32 *cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); u32 offset, narrays; int count, i, k; - *cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16); + count = ((*cmd & RADEON_CP_PACKET_COUNT_MASK) >> 16); + *cmdsz = 2 + count; - if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) { + if ((*cmd & 0xc0000000) != RADEON_CP_PACKET3) { DRM_ERROR("Not a type 3 packet\n"); return -EINVAL; } - if (4 * *cmdsz > cmdbuf->bufsz) { + if (4 * *cmdsz > drm_buffer_unprocessed(cmdbuf->buffer)) { DRM_ERROR("Packet size larger than size of data provided\n"); return -EINVAL; } - switch(cmd[0] & 0xff00) { + switch (*cmd & 0xff00) { /* XXX Are there old drivers needing other packets? */ case RADEON_3D_DRAW_IMMD: @@ -312,7 +322,6 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * break; case RADEON_3D_LOAD_VBPNTR: - count = (cmd[0] >> 16) & 0x3fff; if (count > 18) { /* 12 arrays max */ DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", @@ -321,13 +330,16 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * } /* carefully check packet contents */ - narrays = cmd[1] & ~0xc000; + cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1); + + narrays = *cmd & ~0xc000; k = 0; i = 2; while ((k < narrays) && (i < (count + 2))) { i++; /* skip attribute field */ + cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, i); if (radeon_check_and_fixup_offset(dev_priv, file_priv, - &cmd[i])) { + cmd)) { DRM_ERROR ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", k, i); @@ -338,8 +350,10 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * if (k == narrays) break; /* have one more to process, they come in pairs */ + cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, i); + if (radeon_check_and_fixup_offset(dev_priv, - file_priv, &cmd[i])) + file_priv, cmd)) { DRM_ERROR ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", @@ -363,7 +377,9 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * DRM_ERROR("Invalid 3d packet for r200-class chip\n"); return -EINVAL; } - if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[1])) { + + cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1); + if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) { DRM_ERROR("Invalid rndr_gen_indx offset\n"); return -EINVAL; } @@ -374,12 +390,15 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * DRM_ERROR("Invalid 3d packet for r100-class chip\n"); return -EINVAL; } - if ((cmd[1] & 0x8000ffff) != 0x80000810) { - DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]); + + cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1); + if ((*cmd & 0x8000ffff) != 0x80000810) { + DRM_ERROR("Invalid indx_buffer reg address %08X\n", *cmd); return -EINVAL; } - if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[2])) { - DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]); + cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2); + if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) { + DRM_ERROR("Invalid indx_buffer offset is %08X\n", *cmd); return -EINVAL; } break; @@ -388,31 +407,34 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * case RADEON_CNTL_PAINT_MULTI: case RADEON_CNTL_BITBLT_MULTI: /* MSB of opcode: next DWORD GUI_CNTL */ - if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL + cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1); + if (*cmd & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { - offset = cmd[2] << 10; + u32 *cmd2 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2); + offset = *cmd2 << 10; if (radeon_check_and_fixup_offset (dev_priv, file_priv, &offset)) { DRM_ERROR("Invalid first packet offset\n"); return -EINVAL; } - cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10; + *cmd2 = (*cmd2 & 0xffc00000) | offset >> 10; } - if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && - (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { - offset = cmd[3] << 10; + if ((*cmd & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && + (*cmd & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { + u32 *cmd3 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 3); + offset = *cmd << 10; if (radeon_check_and_fixup_offset (dev_priv, file_priv, &offset)) { DRM_ERROR("Invalid second packet offset\n"); return -EINVAL; } - cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10; + *cmd3 = (*cmd3 & 0xffc00000) | offset >> 10; } break; default: - DRM_ERROR("Invalid packet type %x\n", cmd[0] & 0xff00); + DRM_ERROR("Invalid packet type %x\n", *cmd & 0xff00); return -EINVAL; } @@ -2611,7 +2633,6 @@ static int radeon_emit_packets(drm_radeon_private_t * dev_priv, { int id = (int)header.packet.packet_id; int sz, reg; - int *data = (int *)cmdbuf->buf; RING_LOCALS; if (id >= RADEON_MAX_STATE_PACKETS) @@ -2620,23 +2641,22 @@ static int radeon_emit_packets(drm_radeon_private_t * dev_priv, sz = packet[id].len; reg = packet[id].start; - if (sz * sizeof(int) > cmdbuf->bufsz) { + if (sz * sizeof(u32) > drm_buffer_unprocessed(cmdbuf->buffer)) { DRM_ERROR("Packet size provided larger than data provided\n"); return -EINVAL; } - if (radeon_check_and_fixup_packets(dev_priv, file_priv, id, data)) { + if (radeon_check_and_fixup_packets(dev_priv, file_priv, id, + cmdbuf->buffer)) { DRM_ERROR("Packet verification failed\n"); return -EINVAL; } BEGIN_RING(sz + 1); OUT_RING(CP_PACKET0(reg, (sz - 1))); - OUT_RING_TABLE(data, sz); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz); ADVANCE_RING(); - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); return 0; } @@ -2653,10 +2673,8 @@ static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv, OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); - OUT_RING_TABLE(cmdbuf->buf, sz); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz); ADVANCE_RING(); - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); return 0; } @@ -2675,10 +2693,8 @@ static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv, OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); - OUT_RING_TABLE(cmdbuf->buf, sz); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz); ADVANCE_RING(); - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); return 0; } @@ -2696,11 +2712,9 @@ static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv, OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); - OUT_RING_TABLE(cmdbuf->buf, sz); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz); ADVANCE_RING(); - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); return 0; } @@ -2714,7 +2728,7 @@ static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv, if (!sz) return 0; - if (sz * 4 > cmdbuf->bufsz) + if (sz * 4 > drm_buffer_unprocessed(cmdbuf->buffer)) return -EINVAL; BEGIN_RING(5 + sz); @@ -2722,11 +2736,9 @@ static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv, OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); - OUT_RING_TABLE(cmdbuf->buf, sz); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz); ADVANCE_RING(); - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); return 0; } @@ -2748,11 +2760,9 @@ static int radeon_emit_packet3(struct drm_device * dev, } BEGIN_RING(cmdsz); - OUT_RING_TABLE(cmdbuf->buf, cmdsz); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, cmdsz); ADVANCE_RING(); - cmdbuf->buf += cmdsz * 4; - cmdbuf->bufsz -= cmdsz * 4; return 0; } @@ -2805,16 +2815,16 @@ static int radeon_emit_packet3_cliprect(struct drm_device *dev, } BEGIN_RING(cmdsz); - OUT_RING_TABLE(cmdbuf->buf, cmdsz); + OUT_RING_DRM_BUFFER(cmdbuf->buffer, cmdsz); ADVANCE_RING(); } while (++i < cmdbuf->nbox); if (cmdbuf->nbox == 1) cmdbuf->nbox = 0; + return 0; out: - cmdbuf->buf += cmdsz * 4; - cmdbuf->bufsz -= cmdsz * 4; + drm_buffer_advance(cmdbuf->buffer, cmdsz * 4); return 0; } @@ -2847,16 +2857,16 @@ static int radeon_emit_wait(struct drm_device * dev, int flags) return 0; } -static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv) +static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, + struct drm_file *file_priv) { drm_radeon_private_t *dev_priv = dev->dev_private; struct drm_device_dma *dma = dev->dma; struct drm_buf *buf = NULL; + drm_radeon_cmd_header_t stack_header; int idx; drm_radeon_kcmd_buffer_t *cmdbuf = data; - drm_radeon_cmd_header_t header; - int orig_nbox, orig_bufsz; - char *kbuf = NULL; + int orig_nbox; LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -2871,17 +2881,16 @@ static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file * races between checking values and using those values in other code, * and simply to avoid a lot of function calls to copy in data. */ - orig_bufsz = cmdbuf->bufsz; - if (orig_bufsz != 0) { - kbuf = kmalloc(cmdbuf->bufsz, GFP_KERNEL); - if (kbuf == NULL) - return -ENOMEM; - if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf->buf, - cmdbuf->bufsz)) { - kfree(kbuf); - return -EFAULT; - } - cmdbuf->buf = kbuf; + if (cmdbuf->bufsz != 0) { + int rv; + void __user *buffer = cmdbuf->buffer; + rv = drm_buffer_alloc(&cmdbuf->buffer, cmdbuf->bufsz); + if (rv) + return rv; + rv = drm_buffer_copy_from_user(cmdbuf->buffer, buffer, + cmdbuf->bufsz); + if (rv) + return rv; } orig_nbox = cmdbuf->nbox; @@ -2890,24 +2899,24 @@ static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file int temp; temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf); - if (orig_bufsz != 0) - kfree(kbuf); + if (cmdbuf->bufsz != 0) + drm_buffer_free(cmdbuf->buffer); return temp; } /* microcode_version != r300 */ - while (cmdbuf->bufsz >= sizeof(header)) { + while (drm_buffer_unprocessed(cmdbuf->buffer) >= sizeof(stack_header)) { - header.i = *(int *)cmdbuf->buf; - cmdbuf->buf += sizeof(header); - cmdbuf->bufsz -= sizeof(header); + drm_radeon_cmd_header_t *header; + header = drm_buffer_read_object(cmdbuf->buffer, + sizeof(stack_header), &stack_header); - switch (header.header.cmd_type) { + switch (header->header.cmd_type) { case RADEON_CMD_PACKET: DRM_DEBUG("RADEON_CMD_PACKET\n"); if (radeon_emit_packets - (dev_priv, file_priv, header, cmdbuf)) { + (dev_priv, file_priv, *header, cmdbuf)) { DRM_ERROR("radeon_emit_packets failed\n"); goto err; } @@ -2915,7 +2924,7 @@ static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file case RADEON_CMD_SCALARS: DRM_DEBUG("RADEON_CMD_SCALARS\n"); - if (radeon_emit_scalars(dev_priv, header, cmdbuf)) { + if (radeon_emit_scalars(dev_priv, *header, cmdbuf)) { DRM_ERROR("radeon_emit_scalars failed\n"); goto err; } @@ -2923,7 +2932,7 @@ static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file case RADEON_CMD_VECTORS: DRM_DEBUG("RADEON_CMD_VECTORS\n"); - if (radeon_emit_vectors(dev_priv, header, cmdbuf)) { + if (radeon_emit_vectors(dev_priv, *header, cmdbuf)) { DRM_ERROR("radeon_emit_vectors failed\n"); goto err; } @@ -2931,7 +2940,7 @@ static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file case RADEON_CMD_DMA_DISCARD: DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); - idx = header.dma.buf_idx; + idx = header->dma.buf_idx; if (idx < 0 || idx >= dma->buf_count) { DRM_ERROR("buffer index %d (of %d max)\n", idx, dma->buf_count - 1); @@ -2968,7 +2977,7 @@ static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file case RADEON_CMD_SCALARS2: DRM_DEBUG("RADEON_CMD_SCALARS2\n"); - if (radeon_emit_scalars2(dev_priv, header, cmdbuf)) { + if (radeon_emit_scalars2(dev_priv, *header, cmdbuf)) { DRM_ERROR("radeon_emit_scalars2 failed\n"); goto err; } @@ -2976,37 +2985,37 @@ static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file case RADEON_CMD_WAIT: DRM_DEBUG("RADEON_CMD_WAIT\n"); - if (radeon_emit_wait(dev, header.wait.flags)) { + if (radeon_emit_wait(dev, header->wait.flags)) { DRM_ERROR("radeon_emit_wait failed\n"); goto err; } break; case RADEON_CMD_VECLINEAR: DRM_DEBUG("RADEON_CMD_VECLINEAR\n"); - if (radeon_emit_veclinear(dev_priv, header, cmdbuf)) { + if (radeon_emit_veclinear(dev_priv, *header, cmdbuf)) { DRM_ERROR("radeon_emit_veclinear failed\n"); goto err; } break; default: - DRM_ERROR("bad cmd_type %d at %p\n", - header.header.cmd_type, - cmdbuf->buf - sizeof(header)); + DRM_ERROR("bad cmd_type %d at byte %d\n", + header->header.cmd_type, + cmdbuf->buffer->iterator); goto err; } } - if (orig_bufsz != 0) - kfree(kbuf); + if (cmdbuf->bufsz != 0) + drm_buffer_free(cmdbuf->buffer); DRM_DEBUG("DONE\n"); COMMIT_RING(); return 0; err: - if (orig_bufsz != 0) - kfree(kbuf); + if (cmdbuf->bufsz != 0) + drm_buffer_free(cmdbuf->buffer); return -EINVAL; } -- cgit v1.2.3 From f735261baab3a275a273533c391d2d1b86a9e66a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 18 Feb 2010 15:58:36 +1000 Subject: [rfc] drm/radeon/kms: pm debugging check for vbl. This patch adds a check on avivo chips to see if we are in the VBL region for the active crtcs when we trigger the engine change. I appear to have glitches locally on pm transistion (not sure all fixes are in yet) and this at least seems to be correct here, maybe others can test on systems with no glitches. --- drivers/gpu/drm/radeon/avivod.h | 2 ++ drivers/gpu/drm/radeon/radeon_pm.c | 27 +++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/avivod.h b/drivers/gpu/drm/radeon/avivod.h index d4e6e6e4a938..3c391e7e9fd4 100644 --- a/drivers/gpu/drm/radeon/avivod.h +++ b/drivers/gpu/drm/radeon/avivod.h @@ -30,11 +30,13 @@ #define D1CRTC_CONTROL 0x6080 #define CRTC_EN (1 << 0) +#define D1CRTC_STATUS 0x609c #define D1CRTC_UPDATE_LOCK 0x60E8 #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 #define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 #define D2CRTC_CONTROL 0x6880 +#define D2CRTC_STATUS 0x689c #define D2CRTC_UPDATE_LOCK 0x68E8 #define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 #define D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index f0234351fd57..6dbfdf48a5f5 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -22,6 +22,7 @@ */ #include "drmP.h" #include "radeon.h" +#include "avivod.h" #define RADEON_IDLE_LOOP_MS 100 #define RADEON_RECLOCK_DELAY_MS 200 @@ -283,6 +284,28 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev) mutex_unlock(&rdev->pm.mutex); } +static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) +{ + u32 stat_crtc1 = 0, stat_crtc2 = 0; + bool in_vbl = true; + + if (ASIC_IS_AVIVO(rdev)) { + if (rdev->pm.active_crtcs & (1 << 0)) { + stat_crtc1 = RREG32(D1CRTC_STATUS); + if (!(stat_crtc1 & 1)) + in_vbl = false; + } + if (rdev->pm.active_crtcs & (1 << 1)) { + stat_crtc2 = RREG32(D2CRTC_STATUS); + if (!(stat_crtc2 & 1)) + in_vbl = false; + } + } + if (in_vbl == false) + DRM_INFO("not in vbl for pm change %08x %08x at %s\n", stat_crtc1, + stat_crtc2, finish ? "exit" : "entry"); + return in_vbl; +} static void radeon_pm_set_clocks_locked(struct radeon_device *rdev) { /*radeon_fence_wait_last(rdev);*/ @@ -299,7 +322,11 @@ static void radeon_pm_set_clocks_locked(struct radeon_device *rdev) DRM_ERROR("%s: PM_ACTION_NONE\n", __func__); break; } + + /* check if we are in vblank */ + radeon_pm_debug_check_in_vbl(rdev, false); radeon_set_power_state(rdev); + radeon_pm_debug_check_in_vbl(rdev, true); rdev->pm.planned_action = PM_ACTION_NONE; } -- cgit v1.2.3 From 8e36113082821980c60ce89a6c5d45fc9492fc26 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Thu, 18 Feb 2010 14:23:49 +0000 Subject: drm/radeon/kms: fix R3XX/R4XX memory controller initialization Version 2 of memory controller did break the initialization for R3XX/R4XX hardware. This patch fix it. Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r300.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 7e9f95653cbe..b188aae764cc 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -461,7 +461,8 @@ int r300_gpu_reset(struct radeon_device *rdev) */ void r300_mc_init(struct radeon_device *rdev) { - uint32_t tmp; + u64 base; + u32 tmp; /* DDR for all card after R300 & IGP */ rdev->mc.vram_is_ddr = true; @@ -474,6 +475,10 @@ void r300_mc_init(struct radeon_device *rdev) default: rdev->mc.vram_width = 128; break; } r100_vram_init_sizes(rdev); + base = rdev->mc.aper_base; + if (rdev->flags & RADEON_IS_IGP) + base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; + radeon_vram_location(rdev, &rdev->mc, base); if (!(rdev->flags & RADEON_IS_AGP)) radeon_gtt_location(rdev, &rdev->mc); } -- cgit v1.2.3 From 6271901d828b34b27607314026deaf417f9f9b75 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 19 Feb 2010 16:07:02 -0500 Subject: drm/radeon/rv740: fix backend setup This patch fixes occlusion queries and rendering errors on rv740 boards. Hardcoding the backend map is not an optimal solution, but a better fix is being worked on. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600_cp.c | 9 ++++++--- drivers/gpu/drm/radeon/rv770.c | 9 ++++++--- 2 files changed, 12 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c index d9712a1023b1..fca96aa28818 100644 --- a/drivers/gpu/drm/radeon/r600_cp.c +++ b/drivers/gpu/drm/radeon/r600_cp.c @@ -1439,9 +1439,12 @@ static void r700_gfx_init(struct drm_device *dev, gb_tiling_config |= R600_BANK_SWAPS(1); - backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, - dev_priv->r600_max_backends, - (0xff << dev_priv->r600_max_backends) & 0xff); + if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740) + backend_map = 0x28; + else + backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, + dev_priv->r600_max_backends, + (0xff << dev_priv->r600_max_backends) & 0xff); gb_tiling_config |= R600_BACKEND_MAP(backend_map); cc_gc_shader_pipe_config = diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 323fa6be5082..f4bb0b129a0f 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -556,9 +556,12 @@ static void rv770_gpu_init(struct radeon_device *rdev) gb_tiling_config |= BANK_SWAPS(1); - backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes, - rdev->config.rv770.max_backends, - (0xff << rdev->config.rv770.max_backends) & 0xff); + if (rdev->family == CHIP_RV740) + backend_map = 0x28; + else + backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes, + rdev->config.rv770.max_backends, + (0xff << rdev->config.rv770.max_backends) & 0xff); gb_tiling_config |= BACKEND_MAP(backend_map); cc_gc_shader_pipe_config = -- cgit v1.2.3 From d03f5d5971f2dd4bd259c46e065299661d8fdc9f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 19 Feb 2010 16:22:31 -0500 Subject: drm/radeon: fixes for r6xx/r7xx gfx init - updated swizzle modes for backend map setup - fix programming of a few gfx regs - properly handle pipe/backend setup on LE cards Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600.c | 41 ++++--- drivers/gpu/drm/radeon/r600_cp.c | 231 ++++++++++++++++++++++++++------------- drivers/gpu/drm/radeon/rv770.c | 218 ++++++++++++++++++++++++------------ 3 files changed, 331 insertions(+), 159 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 694a4c564f52..b3c7e0f87b91 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -980,6 +980,9 @@ void r600_gpu_init(struct radeon_device *rdev) { u32 tiling_config; u32 ramcfg; + u32 backend_map; + u32 cc_rb_backend_disable; + u32 cc_gc_shader_pipe_config; u32 tmp; int i, j; u32 sq_config; @@ -1076,23 +1079,20 @@ void r600_gpu_init(struct radeon_device *rdev) switch (rdev->config.r600.max_tile_pipes) { case 1: tiling_config |= PIPE_TILING(0); - rdev->config.r600.tiling_npipes = 1; break; case 2: tiling_config |= PIPE_TILING(1); - rdev->config.r600.tiling_npipes = 2; break; case 4: tiling_config |= PIPE_TILING(2); - rdev->config.r600.tiling_npipes = 4; break; case 8: tiling_config |= PIPE_TILING(3); - rdev->config.r600.tiling_npipes = 8; break; default: break; } + rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); tiling_config |= GROUP_SIZE(0); @@ -1106,24 +1106,33 @@ void r600_gpu_init(struct radeon_device *rdev) tiling_config |= SAMPLE_SPLIT(tmp); } tiling_config |= BANK_SWAPS(1); - tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, - rdev->config.r600.max_backends, - (0xff << rdev->config.r600.max_backends) & 0xff); - tiling_config |= BACKEND_MAP(tmp); + + cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; + cc_rb_backend_disable |= + BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); + + cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; + cc_gc_shader_pipe_config |= + INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); + cc_gc_shader_pipe_config |= + INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); + + backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, + (R6XX_MAX_BACKENDS - + r600_count_pipe_bits((cc_rb_backend_disable & + R6XX_MAX_BACKENDS_MASK) >> 16)), + (cc_rb_backend_disable >> 16)); + + tiling_config |= BACKEND_MAP(backend_map); WREG32(GB_TILING_CONFIG, tiling_config); WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); - tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); - WREG32(CC_RB_BACKEND_DISABLE, tmp); - /* Setup pipes */ - tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); - tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); - WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp); - WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp); + WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); + WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); - tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK); + tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c index fca96aa28818..40416c068d9f 100644 --- a/drivers/gpu/drm/radeon/r600_cp.c +++ b/drivers/gpu/drm/radeon/r600_cp.c @@ -734,8 +734,8 @@ static void r600_gfx_init(struct drm_device *dev, u32 hdp_host_path_cntl; u32 backend_map; u32 gb_tiling_config = 0; - u32 cc_rb_backend_disable = 0; - u32 cc_gc_shader_pipe_config = 0; + u32 cc_rb_backend_disable; + u32 cc_gc_shader_pipe_config; u32 ramcfg; /* setup chip specs */ @@ -857,18 +857,22 @@ static void r600_gfx_init(struct drm_device *dev, gb_tiling_config |= R600_BANK_SWAPS(1); - backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, - dev_priv->r600_max_backends, - (0xff << dev_priv->r600_max_backends) & 0xff); - gb_tiling_config |= R600_BACKEND_MAP(backend_map); + cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; + cc_rb_backend_disable |= + R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); - cc_gc_shader_pipe_config = + cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; + cc_gc_shader_pipe_config |= R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); cc_gc_shader_pipe_config |= R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); - cc_rb_backend_disable = - R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); + backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, + (R6XX_MAX_BACKENDS - + r600_count_pipe_bits((cc_rb_backend_disable & + R6XX_MAX_BACKENDS_MASK) >> 16)), + (cc_rb_backend_disable >> 16)); + gb_tiling_config |= R600_BACKEND_MAP(backend_map); RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); @@ -890,7 +894,7 @@ static void r600_gfx_init(struct drm_device *dev, RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); num_qd_pipes = - R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); + R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); @@ -1162,7 +1166,8 @@ static void r600_gfx_init(struct drm_device *dev, } -static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, +static u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv, + u32 num_tile_pipes, u32 num_backends, u32 backend_disable_mask) { @@ -1173,6 +1178,7 @@ static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, u32 swizzle_pipe[R7XX_MAX_PIPES]; u32 cur_backend; u32 i; + bool force_no_swizzle; if (num_tile_pipes > R7XX_MAX_PIPES) num_tile_pipes = R7XX_MAX_PIPES; @@ -1202,6 +1208,18 @@ static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, if (enabled_backends_count != num_backends) num_backends = enabled_backends_count; + switch (dev_priv->flags & RADEON_FAMILY_MASK) { + case CHIP_RV770: + case CHIP_RV730: + force_no_swizzle = false; + break; + case CHIP_RV710: + case CHIP_RV740: + default: + force_no_swizzle = true; + break; + } + memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); switch (num_tile_pipes) { case 1: @@ -1212,49 +1230,100 @@ static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, swizzle_pipe[1] = 1; break; case 3: - swizzle_pipe[0] = 0; - swizzle_pipe[1] = 2; - swizzle_pipe[2] = 1; + if (force_no_swizzle) { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + } else { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 1; + } break; case 4: - swizzle_pipe[0] = 0; - swizzle_pipe[1] = 2; - swizzle_pipe[2] = 3; - swizzle_pipe[3] = 1; + if (force_no_swizzle) { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + } else { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 3; + swizzle_pipe[3] = 1; + } break; case 5: - swizzle_pipe[0] = 0; - swizzle_pipe[1] = 2; - swizzle_pipe[2] = 4; - swizzle_pipe[3] = 1; - swizzle_pipe[4] = 3; + if (force_no_swizzle) { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + swizzle_pipe[4] = 4; + } else { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 1; + swizzle_pipe[4] = 3; + } break; case 6: - swizzle_pipe[0] = 0; - swizzle_pipe[1] = 2; - swizzle_pipe[2] = 4; - swizzle_pipe[3] = 5; - swizzle_pipe[4] = 3; - swizzle_pipe[5] = 1; + if (force_no_swizzle) { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + swizzle_pipe[4] = 4; + swizzle_pipe[5] = 5; + } else { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 5; + swizzle_pipe[4] = 3; + swizzle_pipe[5] = 1; + } break; case 7: - swizzle_pipe[0] = 0; - swizzle_pipe[1] = 2; - swizzle_pipe[2] = 4; - swizzle_pipe[3] = 6; - swizzle_pipe[4] = 3; - swizzle_pipe[5] = 1; - swizzle_pipe[6] = 5; + if (force_no_swizzle) { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + swizzle_pipe[4] = 4; + swizzle_pipe[5] = 5; + swizzle_pipe[6] = 6; + } else { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 6; + swizzle_pipe[4] = 3; + swizzle_pipe[5] = 1; + swizzle_pipe[6] = 5; + } break; case 8: - swizzle_pipe[0] = 0; - swizzle_pipe[1] = 2; - swizzle_pipe[2] = 4; - swizzle_pipe[3] = 6; - swizzle_pipe[4] = 3; - swizzle_pipe[5] = 1; - swizzle_pipe[6] = 7; - swizzle_pipe[7] = 5; + if (force_no_swizzle) { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + swizzle_pipe[4] = 4; + swizzle_pipe[5] = 5; + swizzle_pipe[6] = 6; + swizzle_pipe[7] = 7; + } else { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 6; + swizzle_pipe[4] = 3; + swizzle_pipe[5] = 1; + swizzle_pipe[6] = 7; + swizzle_pipe[7] = 5; + } break; } @@ -1275,8 +1344,10 @@ static void r700_gfx_init(struct drm_device *dev, drm_radeon_private_t *dev_priv) { int i, j, num_qd_pipes; + u32 ta_aux_cntl; u32 sx_debug_1; u32 smx_dc_ctl0; + u32 db_debug3; u32 num_gs_verts_per_thread; u32 vgt_gs_per_es; u32 gs_prim_buffer_depth = 0; @@ -1287,8 +1358,8 @@ static void r700_gfx_init(struct drm_device *dev, u32 sq_dyn_gpr_size_simd_ab_0; u32 backend_map; u32 gb_tiling_config = 0; - u32 cc_rb_backend_disable = 0; - u32 cc_gc_shader_pipe_config = 0; + u32 cc_rb_backend_disable; + u32 cc_gc_shader_pipe_config; u32 mc_arb_ramcfg; u32 db_debug4; @@ -1439,21 +1510,26 @@ static void r700_gfx_init(struct drm_device *dev, gb_tiling_config |= R600_BANK_SWAPS(1); - if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740) - backend_map = 0x28; - else - backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, - dev_priv->r600_max_backends, - (0xff << dev_priv->r600_max_backends) & 0xff); - gb_tiling_config |= R600_BACKEND_MAP(backend_map); + cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; + cc_rb_backend_disable |= + R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); - cc_gc_shader_pipe_config = + cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; + cc_gc_shader_pipe_config |= R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); cc_gc_shader_pipe_config |= R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); - cc_rb_backend_disable = - R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); + if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740) + backend_map = 0x28; + else + backend_map = r700_get_tile_pipe_to_backend_map(dev_priv, + dev_priv->r600_max_tile_pipes, + (R7XX_MAX_BACKENDS - + r600_count_pipe_bits((cc_rb_backend_disable & + R7XX_MAX_BACKENDS_MASK) >> 16)), + (cc_rb_backend_disable >> 16)); + gb_tiling_config |= R600_BACKEND_MAP(backend_map); RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); @@ -1472,16 +1548,13 @@ static void r700_gfx_init(struct drm_device *dev, RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); - RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); - RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); - RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); num_qd_pipes = - R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); + R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); @@ -1491,10 +1564,8 @@ static void r700_gfx_init(struct drm_device *dev, RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); - RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | - R600_SYNC_GRADIENT | - R600_SYNC_WALKER | - R600_SYNC_ALIGNER)); + ta_aux_cntl = RADEON_READ(R600_TA_CNTL_AUX); + RADEON_WRITE(R600_TA_CNTL_AUX, ta_aux_cntl | R600_DISABLE_CUBE_ANISO); sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1); sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS; @@ -1505,14 +1576,28 @@ static void r700_gfx_init(struct drm_device *dev, smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); - RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | - R700_GS_FLUSH_CTL(4) | - R700_ACK_FLUSH_CTL(3) | - R700_SYNC_FLUSH_CTL)); + if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740) + RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | + R700_GS_FLUSH_CTL(4) | + R700_ACK_FLUSH_CTL(3) | + R700_SYNC_FLUSH_CTL)); - if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) - RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f)); - else { + db_debug3 = RADEON_READ(R700_DB_DEBUG3); + db_debug3 &= ~R700_DB_CLK_OFF_DELAY(0x1f); + switch (dev_priv->flags & RADEON_FAMILY_MASK) { + case CHIP_RV770: + case CHIP_RV740: + db_debug3 |= R700_DB_CLK_OFF_DELAY(0x1f); + break; + case CHIP_RV710: + case CHIP_RV730: + default: + db_debug3 |= R700_DB_CLK_OFF_DELAY(2); + break; + } + RADEON_WRITE(R700_DB_DEBUG3, db_debug3); + + if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) { db_debug4 = RADEON_READ(RV700_DB_DEBUG4); db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER; RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); @@ -1541,10 +1626,10 @@ static void r700_gfx_init(struct drm_device *dev, R600_ALU_UPDATE_FIFO_HIWATER(0x8)); switch (dev_priv->flags & RADEON_FAMILY_MASK) { case CHIP_RV770: - sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); - break; case CHIP_RV730: case CHIP_RV710: + sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); + break; case CHIP_RV740: default: sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index f4bb0b129a0f..88356b0a1f63 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -274,9 +274,10 @@ static int rv770_cp_load_microcode(struct radeon_device *rdev) /* * Core functions */ -static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, - u32 num_backends, - u32 backend_disable_mask) +static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev, + u32 num_tile_pipes, + u32 num_backends, + u32 backend_disable_mask) { u32 backend_map = 0; u32 enabled_backends_mask; @@ -285,6 +286,7 @@ static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, u32 swizzle_pipe[R7XX_MAX_PIPES]; u32 cur_backend; u32 i; + bool force_no_swizzle; if (num_tile_pipes > R7XX_MAX_PIPES) num_tile_pipes = R7XX_MAX_PIPES; @@ -314,6 +316,18 @@ static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, if (enabled_backends_count != num_backends) num_backends = enabled_backends_count; + switch (rdev->family) { + case CHIP_RV770: + case CHIP_RV730: + force_no_swizzle = false; + break; + case CHIP_RV710: + case CHIP_RV740: + default: + force_no_swizzle = true; + break; + } + memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); switch (num_tile_pipes) { case 1: @@ -324,49 +338,100 @@ static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, swizzle_pipe[1] = 1; break; case 3: - swizzle_pipe[0] = 0; - swizzle_pipe[1] = 2; - swizzle_pipe[2] = 1; + if (force_no_swizzle) { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + } else { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 1; + } break; case 4: - swizzle_pipe[0] = 0; - swizzle_pipe[1] = 2; - swizzle_pipe[2] = 3; - swizzle_pipe[3] = 1; + if (force_no_swizzle) { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + } else { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 3; + swizzle_pipe[3] = 1; + } break; case 5: - swizzle_pipe[0] = 0; - swizzle_pipe[1] = 2; - swizzle_pipe[2] = 4; - swizzle_pipe[3] = 1; - swizzle_pipe[4] = 3; + if (force_no_swizzle) { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + swizzle_pipe[4] = 4; + } else { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 1; + swizzle_pipe[4] = 3; + } break; case 6: - swizzle_pipe[0] = 0; - swizzle_pipe[1] = 2; - swizzle_pipe[2] = 4; - swizzle_pipe[3] = 5; - swizzle_pipe[4] = 3; - swizzle_pipe[5] = 1; + if (force_no_swizzle) { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + swizzle_pipe[4] = 4; + swizzle_pipe[5] = 5; + } else { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 5; + swizzle_pipe[4] = 3; + swizzle_pipe[5] = 1; + } break; case 7: - swizzle_pipe[0] = 0; - swizzle_pipe[1] = 2; - swizzle_pipe[2] = 4; - swizzle_pipe[3] = 6; - swizzle_pipe[4] = 3; - swizzle_pipe[5] = 1; - swizzle_pipe[6] = 5; + if (force_no_swizzle) { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + swizzle_pipe[4] = 4; + swizzle_pipe[5] = 5; + swizzle_pipe[6] = 6; + } else { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 6; + swizzle_pipe[4] = 3; + swizzle_pipe[5] = 1; + swizzle_pipe[6] = 5; + } break; case 8: - swizzle_pipe[0] = 0; - swizzle_pipe[1] = 2; - swizzle_pipe[2] = 4; - swizzle_pipe[3] = 6; - swizzle_pipe[4] = 3; - swizzle_pipe[5] = 1; - swizzle_pipe[6] = 7; - swizzle_pipe[7] = 5; + if (force_no_swizzle) { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + swizzle_pipe[4] = 4; + swizzle_pipe[5] = 5; + swizzle_pipe[6] = 6; + swizzle_pipe[7] = 7; + } else { + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 6; + swizzle_pipe[4] = 3; + swizzle_pipe[5] = 1; + swizzle_pipe[6] = 7; + swizzle_pipe[7] = 5; + } break; } @@ -386,8 +451,10 @@ static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, static void rv770_gpu_init(struct radeon_device *rdev) { int i, j, num_qd_pipes; + u32 ta_aux_cntl; u32 sx_debug_1; u32 smx_dc_ctl0; + u32 db_debug3; u32 num_gs_verts_per_thread; u32 vgt_gs_per_es; u32 gs_prim_buffer_depth = 0; @@ -516,24 +583,20 @@ static void rv770_gpu_init(struct radeon_device *rdev) switch (rdev->config.rv770.max_tile_pipes) { case 1: + default: gb_tiling_config |= PIPE_TILING(0); - rdev->config.rv770.tiling_npipes = 1; break; case 2: gb_tiling_config |= PIPE_TILING(1); - rdev->config.rv770.tiling_npipes = 2; break; case 4: gb_tiling_config |= PIPE_TILING(2); - rdev->config.rv770.tiling_npipes = 4; break; case 8: gb_tiling_config |= PIPE_TILING(3); - rdev->config.rv770.tiling_npipes = 8; - break; - default: break; } + rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; if (rdev->family == CHIP_RV770) gb_tiling_config |= BANK_TILING(1); @@ -556,21 +619,27 @@ static void rv770_gpu_init(struct radeon_device *rdev) gb_tiling_config |= BANK_SWAPS(1); - if (rdev->family == CHIP_RV740) - backend_map = 0x28; - else - backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes, - rdev->config.rv770.max_backends, - (0xff << rdev->config.rv770.max_backends) & 0xff); - gb_tiling_config |= BACKEND_MAP(backend_map); + cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; + cc_rb_backend_disable |= + BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); - cc_gc_shader_pipe_config = + cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; + cc_gc_shader_pipe_config |= INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); cc_gc_shader_pipe_config |= INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); - cc_rb_backend_disable = - BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); + if (rdev->family == CHIP_RV740) + backend_map = 0x28; + else + backend_map = r700_get_tile_pipe_to_backend_map(rdev, + rdev->config.rv770.max_tile_pipes, + (R7XX_MAX_BACKENDS - + r600_count_pipe_bits((cc_rb_backend_disable & + R7XX_MAX_BACKENDS_MASK) >> 16)), + (cc_rb_backend_disable >> 16)); + gb_tiling_config |= BACKEND_MAP(backend_map); + WREG32(GB_TILING_CONFIG, gb_tiling_config); WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); @@ -578,16 +647,13 @@ static void rv770_gpu_init(struct radeon_device *rdev) WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); - WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); + WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); - WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); WREG32(CGTS_SYS_TCC_DISABLE, 0); WREG32(CGTS_TCC_DISABLE, 0); - WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); - WREG32(CGTS_USER_TCC_DISABLE, 0); num_qd_pipes = - R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK); + R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); @@ -597,10 +663,8 @@ static void rv770_gpu_init(struct radeon_device *rdev) WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); - WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | - SYNC_GRADIENT | - SYNC_WALKER | - SYNC_ALIGNER)); + ta_aux_cntl = RREG32(TA_CNTL_AUX); + WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); sx_debug_1 = RREG32(SX_DEBUG_1); sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; @@ -611,14 +675,28 @@ static void rv770_gpu_init(struct radeon_device *rdev) smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); WREG32(SMX_DC_CTL0, smx_dc_ctl0); - WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | - GS_FLUSH_CTL(4) | - ACK_FLUSH_CTL(3) | - SYNC_FLUSH_CTL)); + if (rdev->family != CHIP_RV740) + WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | + GS_FLUSH_CTL(4) | + ACK_FLUSH_CTL(3) | + SYNC_FLUSH_CTL)); - if (rdev->family == CHIP_RV770) - WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f)); - else { + db_debug3 = RREG32(DB_DEBUG3); + db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); + switch (rdev->family) { + case CHIP_RV770: + case CHIP_RV740: + db_debug3 |= DB_CLK_OFF_DELAY(0x1f); + break; + case CHIP_RV710: + case CHIP_RV730: + default: + db_debug3 |= DB_CLK_OFF_DELAY(2); + break; + } + WREG32(DB_DEBUG3, db_debug3); + + if (rdev->family != CHIP_RV770) { db_debug4 = RREG32(DB_DEBUG4); db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; WREG32(DB_DEBUG4, db_debug4); @@ -647,10 +725,10 @@ static void rv770_gpu_init(struct radeon_device *rdev) ALU_UPDATE_FIFO_HIWATER(0x8)); switch (rdev->family) { case CHIP_RV770: - sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); - break; case CHIP_RV730: case CHIP_RV710: + sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); + break; case CHIP_RV740: default: sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); -- cgit v1.2.3 From 9038dfdf699a3227004f1f6da32a3ef4ef3ba5a4 Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Sat, 20 Feb 2010 23:15:04 +0000 Subject: drm/radeon/kms: simplify storing current and requested PM mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We kept pointers to requested and current clock modes in every power state. That was useless, more /global/ pointers in power struct are enough. Signed-off-by: RafaÅ‚ MiÅ‚ecki Reviewed-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon.h | 5 ++--- drivers/gpu/drm/radeon/radeon_atombios.c | 20 ++++---------------- drivers/gpu/drm/radeon/radeon_combios.c | 7 ++++--- drivers/gpu/drm/radeon/radeon_pm.c | 30 +++++++++++++++--------------- 4 files changed, 25 insertions(+), 37 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 0ca83ca91111..fc9044edc0aa 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -652,9 +652,6 @@ struct radeon_power_state { struct radeon_pm_clock_info clock_info[8]; /* number of valid clock modes in this power state */ int num_clock_modes; - /* currently selected clock mode */ - struct radeon_pm_clock_info *current_clock_mode; - struct radeon_pm_clock_info *requested_clock_mode; struct radeon_pm_clock_info *default_clock_mode; /* non clock info about this state */ struct radeon_pm_non_clock_info non_clock_info; @@ -691,7 +688,9 @@ struct radeon_pm { /* number of valid power states */ int num_power_states; struct radeon_power_state *current_power_state; + struct radeon_pm_clock_info *current_clock_mode; struct radeon_power_state *requested_power_state; + struct radeon_pm_clock_info *requested_clock_mode; struct radeon_power_state *default_power_state; }; diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 79d445373c34..33aed6c2d41a 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -1450,7 +1450,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); rdev->pm.default_power_state = NULL; - rdev->pm.current_power_state = NULL; if (power_info) { if (frev < 4) { @@ -1517,11 +1516,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.power_state[state_index].type = POWER_STATE_TYPE_DEFAULT; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; - rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; - rdev->pm.power_state[state_index].current_clock_mode = - &rdev->pm.power_state[state_index].clock_info[0]; } state_index++; break; @@ -1586,11 +1582,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.power_state[state_index].type = POWER_STATE_TYPE_DEFAULT; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; - rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; - rdev->pm.power_state[state_index].current_clock_mode = - &rdev->pm.power_state[state_index].clock_info[0]; } state_index++; break; @@ -1661,11 +1654,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.power_state[state_index].type = POWER_STATE_TYPE_DEFAULT; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; - rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; - rdev->pm.power_state[state_index].current_clock_mode = - &rdev->pm.power_state[state_index].clock_info[0]; } state_index++; break; @@ -1765,11 +1755,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.power_state[state_index].type = POWER_STATE_TYPE_DEFAULT; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; - rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; - rdev->pm.power_state[state_index].current_clock_mode = - &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; } state_index++; } @@ -1788,18 +1775,19 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; - rdev->pm.power_state[state_index].current_clock_mode = - &rdev->pm.power_state[state_index].clock_info[0]; rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; if (rdev->asic->get_pcie_lanes) rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); else rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; - rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; state_index++; } rdev->pm.num_power_states = state_index; + + rdev->pm.current_power_state = rdev->pm.default_power_state; + rdev->pm.current_clock_mode = + rdev->pm.default_power_state->default_clock_mode; } void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index 5ef791be5036..69af81d9f5ae 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -2358,7 +2358,6 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) int state_index = 0; rdev->pm.default_power_state = NULL; - rdev->pm.current_power_state = NULL; if (rdev->flags & RADEON_IS_MOBILITY) { offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); @@ -2447,15 +2446,17 @@ default_mode: rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; - rdev->pm.power_state[state_index].current_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; if (rdev->asic->get_pcie_lanes) rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); else rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; - rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.num_power_states = state_index + 1; + + rdev->pm.current_power_state = rdev->pm.default_power_state; + rdev->pm.current_clock_mode = + rdev->pm.default_power_state->default_clock_mode; } void radeon_external_tmds_setup(struct drm_encoder *encoder) diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 6dbfdf48a5f5..8960acf14155 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -143,50 +143,50 @@ static void radeon_get_power_state(struct radeon_device *rdev, enum radeon_pm_action action) { switch (action) { - case PM_ACTION_NONE: - default: - rdev->pm.requested_power_state = rdev->pm.current_power_state; - rdev->pm.requested_power_state->requested_clock_mode = - rdev->pm.requested_power_state->current_clock_mode; - break; case PM_ACTION_MINIMUM: rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY); - rdev->pm.requested_power_state->requested_clock_mode = + rdev->pm.requested_clock_mode = radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW); break; case PM_ACTION_DOWNCLOCK: rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE); - rdev->pm.requested_power_state->requested_clock_mode = + rdev->pm.requested_clock_mode = radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID); break; case PM_ACTION_UPCLOCK: rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT); - rdev->pm.requested_power_state->requested_clock_mode = + rdev->pm.requested_clock_mode = radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH); break; + case PM_ACTION_NONE: + default: + DRM_ERROR("Requested mode for not defined action\n"); + return; } DRM_INFO("Requested: e: %d m: %d p: %d\n", - rdev->pm.requested_power_state->requested_clock_mode->sclk, - rdev->pm.requested_power_state->requested_clock_mode->mclk, + rdev->pm.requested_clock_mode->sclk, + rdev->pm.requested_clock_mode->mclk, rdev->pm.requested_power_state->non_clock_info.pcie_lanes); } static void radeon_set_power_state(struct radeon_device *rdev) { - if (rdev->pm.requested_power_state == rdev->pm.current_power_state) + /* if *_clock_mode are the same, *_power_state are as well */ + if (rdev->pm.requested_clock_mode == rdev->pm.current_clock_mode) return; DRM_INFO("Setting: e: %d m: %d p: %d\n", - rdev->pm.requested_power_state->requested_clock_mode->sclk, - rdev->pm.requested_power_state->requested_clock_mode->mclk, + rdev->pm.requested_clock_mode->sclk, + rdev->pm.requested_clock_mode->mclk, rdev->pm.requested_power_state->non_clock_info.pcie_lanes); /* set pcie lanes */ /* set voltage */ /* set engine clock */ - radeon_set_engine_clock(rdev, rdev->pm.requested_power_state->requested_clock_mode->sclk); + radeon_set_engine_clock(rdev, rdev->pm.requested_clock_mode->sclk); /* set memory clock */ rdev->pm.current_power_state = rdev->pm.requested_power_state; + rdev->pm.current_clock_mode = rdev->pm.requested_clock_mode; } int radeon_pm_init(struct radeon_device *rdev) -- cgit v1.2.3 From 08ff2a7a7a13c562e81a406722193f43cbb4e4ef Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Sun, 21 Feb 2010 22:46:30 +0000 Subject: drm/radeon/kms: for downclocking non-mobility check PERFORMANCE state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit AtomBIOS tables on non-mobility GPU do not contain POWERSAVE/BATTERY. Signed-off-by: RafaÅ‚ MiÅ‚ecki Reviewed-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_pm.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 8960acf14155..d174d93c9386 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -91,14 +91,24 @@ static struct radeon_power_state * radeon_pick_power_state(struct radeon_device default: return rdev->pm.default_power_state; case POWER_STATE_TYPE_POWERSAVE: - wanted_types[0] = POWER_STATE_TYPE_POWERSAVE; - wanted_types[1] = POWER_STATE_TYPE_BATTERY; - wanted_count = 2; + if (rdev->flags & RADEON_IS_MOBILITY) { + wanted_types[0] = POWER_STATE_TYPE_POWERSAVE; + wanted_types[1] = POWER_STATE_TYPE_BATTERY; + wanted_count = 2; + } else { + wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE; + wanted_count = 1; + } break; case POWER_STATE_TYPE_BATTERY: - wanted_types[0] = POWER_STATE_TYPE_BATTERY; - wanted_types[1] = POWER_STATE_TYPE_POWERSAVE; - wanted_count = 2; + if (rdev->flags & RADEON_IS_MOBILITY) { + wanted_types[0] = POWER_STATE_TYPE_BATTERY; + wanted_types[1] = POWER_STATE_TYPE_POWERSAVE; + wanted_count = 2; + } else { + wanted_types[0] = POWER_STATE_TYPE_PERFORMANCE; + wanted_count = 1; + } break; case POWER_STATE_TYPE_BALANCED: case POWER_STATE_TYPE_PERFORMANCE: -- cgit v1.2.3 From aa5120d2ef228042416d3023fb7eda9ee487dcf9 Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Thu, 18 Feb 2010 20:24:28 +0000 Subject: drm/radeon/kms: implement reading active PCIE lanes on R600+ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r300.c | 5 ++++- drivers/gpu/drm/radeon/radeon.h | 2 ++ drivers/gpu/drm/radeon/radeon_asic.h | 4 ++-- drivers/gpu/drm/radeon/radeon_pm.c | 2 ++ 4 files changed, 10 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index b188aae764cc..dc32cd13a837 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -554,7 +554,10 @@ int rv370_get_pcie_lanes(struct radeon_device *rdev) /* FIXME wait for idle */ - link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); + if (rdev->family < CHIP_R600) + link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); + else + link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { case RADEON_PCIE_LC_LINK_WIDTH_X0: diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index fc9044edc0aa..2434d553bbbc 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1014,6 +1014,8 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) +#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) +#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) #define WREG32_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32(reg); \ diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index b7030d7c0396..4572a6699884 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -626,7 +626,7 @@ static struct radeon_asic r600_asic = { .set_engine_clock = &radeon_atom_set_engine_clock, .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, - .get_pcie_lanes = NULL, + .get_pcie_lanes = &rv370_get_pcie_lanes, .set_pcie_lanes = NULL, .set_clock_gating = NULL, .set_surface_reg = r600_set_surface_reg, @@ -672,7 +672,7 @@ static struct radeon_asic rv770_asic = { .set_engine_clock = &radeon_atom_set_engine_clock, .get_memory_clock = &radeon_atom_get_memory_clock, .set_memory_clock = &radeon_atom_set_memory_clock, - .get_pcie_lanes = NULL, + .get_pcie_lanes = &rv370_get_pcie_lanes, .set_pcie_lanes = NULL, .set_clock_gating = &radeon_atom_set_clock_gating, .set_surface_reg = r600_set_surface_reg, diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index d174d93c9386..d4d1c39a0e99 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -442,6 +442,8 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data) seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk); if (rdev->asic->get_memory_clock) seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); + if (rdev->asic->get_pcie_lanes) + seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); return 0; } -- cgit v1.2.3 From fa80945269f312bc609e8384302f58b03c916e12 Mon Sep 17 00:00:00 2001 From: Thomas Renninger Date: Sat, 20 Feb 2010 11:44:27 +0100 Subject: ACPI thermal: Don't invalidate thermal zone if critical trip point is bad V2: Corrected integer/long conversion. Some BIOSes return a negative value for the critical trip point. Especially since Windows 2006... We currently invalidate the whole thermal zone in this case. But it may still be needed for cooling, also without critical trip point. This patch invalidates the critical trip point if no _CRT function is found or if it returns negative values, but does not invalidate the whole thermal zone in this case. Reference: http://bugzilla.novell.com/show_bug.cgi?id=531547 Signed-off-by: Thomas Renninger Tested-by: clarkt@cnsp.com Acked-by: Zhang Rui Signed-off-by: Len Brown --- drivers/acpi/thermal.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c index 9073ada88835..77b8e1eaa717 100644 --- a/drivers/acpi/thermal.c +++ b/drivers/acpi/thermal.c @@ -368,7 +368,7 @@ static int acpi_thermal_trips_update(struct acpi_thermal *tz, int flag) int valid = 0; int i; - /* Critical Shutdown (required) */ + /* Critical Shutdown */ if (flag & ACPI_TRIPS_CRITICAL) { status = acpi_evaluate_integer(tz->device->handle, "_CRT", NULL, &tmp); @@ -379,17 +379,19 @@ static int acpi_thermal_trips_update(struct acpi_thermal *tz, int flag) * Below zero (Celsius) values clearly aren't right for sure.. * ... so lets discard those as invalid. */ - if (ACPI_FAILURE(status) || - tz->trips.critical.temperature <= 2732) { + if (ACPI_FAILURE(status)) { + tz->trips.critical.flags.valid = 0; + ACPI_DEBUG_PRINT((ACPI_DB_INFO, + "No critical threshold\n")); + } else if (tmp <= 2732) { + printk(KERN_WARNING FW_BUG "Invalid critical threshold " + "(%llu)\n", tmp); tz->trips.critical.flags.valid = 0; - ACPI_EXCEPTION((AE_INFO, status, - "No or invalid critical threshold")); - return -ENODEV; } else { tz->trips.critical.flags.valid = 1; ACPI_DEBUG_PRINT((ACPI_DB_INFO, - "Found critical threshold [%lu]\n", - tz->trips.critical.temperature)); + "Found critical threshold [%lu]\n", + tz->trips.critical.temperature)); } if (tz->trips.critical.flags.valid == 1) { if (crt == -1) { -- cgit v1.2.3 From 03843a1294073c19783b43f60f3a455dd0672685 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 29 Jan 2010 10:23:40 +0900 Subject: ARM: S5P6442: Add serial port support This patch adds UART serial port support for S5P6442. Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/plat-s5p/dev-uart.c | 2 ++ drivers/serial/Kconfig | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c index 23c75316d491..a89331ef4ae1 100644 --- a/arch/arm/plat-s5p/dev-uart.c +++ b/arch/arm/plat-s5p/dev-uart.c @@ -95,6 +95,7 @@ static struct resource s5p_uart2_resource[] = { }; static struct resource s5p_uart3_resource[] = { +#if CONFIG_SERIAL_SAMSUNG_UARTS > 3 [0] = { .start = S5P_PA_UART3, .end = S5P_PA_UART3 + S5P_SZ_UART, @@ -115,6 +116,7 @@ static struct resource s5p_uart3_resource[] = { .end = IRQ_S5P_UART_ERR3, .flags = IORESOURCE_IRQ, }, +#endif }; struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = { diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index b2157c36566d..86590e9a92f5 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -551,7 +551,7 @@ config SERIAL_S5PC100 config SERIAL_S5PV210 tristate "Samsung S5PV210 Serial port support" - depends on SERIAL_SAMSUNG && CPU_S5PV210 + depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442) select SERIAL_SAMSUNG_UARTS_4 default y help -- cgit v1.2.3 From 1088f336ccc73feaaff2f95eec6fb5b6e7e94337 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 24 Feb 2010 01:46:10 +0000 Subject: ARM: SAMSUNG: Fix UART number for S5P6442 The recent changes in the UART code mean that we need to ensure that the 4 UART case is only selected if S5PV210 is being compiled. Signed-off-by: Ben Dooks --- drivers/serial/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 86590e9a92f5..c53e13a26084 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -552,7 +552,7 @@ config SERIAL_S5PC100 config SERIAL_S5PV210 tristate "Samsung S5PV210 Serial port support" depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442) - select SERIAL_SAMSUNG_UARTS_4 + select SERIAL_SAMSUNG_UARTS_4 if CPU_S5PV210 default y help Serial port support for Samsung's S5P Family of SoC's -- cgit v1.2.3 From 22e6dd7e700111c1aa49581d27f2b349cbc798dd Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 23 Feb 2010 13:12:43 -0500 Subject: drm/radeon/kms/evergreen: fix typo in cursor code cursor x/y are surface relative. fixes fdo bug 26551 Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_cursor.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c index 9514f3275357..7ecf5e1b39c1 100644 --- a/drivers/gpu/drm/radeon/radeon_cursor.c +++ b/drivers/gpu/drm/radeon/radeon_cursor.c @@ -219,6 +219,11 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc, radeon_lock_cursor(crtc, true); if (ASIC_IS_DCE4(rdev)) { + /* cursors are offset into the total surface */ + x += crtc->x; + y += crtc->y; + DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); + /* XXX: check if evergreen has the same issues as avivo chips */ WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16) | -- cgit v1.2.3 From 51e5fcd353a55364984bda3dd1391742e4dec53c Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Fri, 19 Feb 2010 14:33:54 +0000 Subject: drm/radeon/kms: force pinning buffer into visible VRAM This patch properly set visible VRAM and enforce any pinned buffer to be into visible VRAM. We might later add a flag to release this constraint for some newer hw more clever than previous. Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/evergreen.c | 1 + drivers/gpu/drm/radeon/r100.c | 5 ++++- drivers/gpu/drm/radeon/r600.c | 1 + drivers/gpu/drm/radeon/radeon_object.c | 3 ++- drivers/gpu/drm/radeon/rs600.c | 5 +++-- drivers/gpu/drm/radeon/rs690.c | 1 + drivers/gpu/drm/radeon/rv770.c | 1 + 7 files changed, 13 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 3f973d411d61..bd2e7aa85c1d 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -474,6 +474,7 @@ int evergreen_mc_init(struct radeon_device *rdev) /* size in MB on evergreen */ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; + rdev->mc.visible_vram_size = rdev->mc.aper_size; /* FIXME remove this once we support unmappable VRAM */ if (rdev->mc.mc_vram_size > rdev->mc.aper_size) { rdev->mc.mc_vram_size = rdev->mc.aper_size; diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 1fdd793343b9..91eb762eb3f9 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -1958,9 +1958,12 @@ void r100_vram_init_sizes(struct radeon_device *rdev) u64 config_aper_size; /* work out accessible VRAM */ - rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); + rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); + /* FIXME we don't use the second aperture yet when we could use it */ + if (rdev->mc.visible_vram_size > rdev->mc.aper_size) + rdev->mc.visible_vram_size = rdev->mc.aper_size; config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); if (rdev->flags & RADEON_IS_IGP) { uint32_t tom; diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index b3c7e0f87b91..f9a83358aa5a 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -712,6 +712,7 @@ int r600_mc_init(struct radeon_device *rdev) /* Setup GPU memory space */ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); + rdev->mc.visible_vram_size = rdev->mc.aper_size; /* FIXME remove this once we support unmappable VRAM */ if (rdev->mc.mc_vram_size > rdev->mc.aper_size) { rdev->mc.mc_vram_size = rdev->mc.aper_size; diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index f1da370928eb..fc9d00ac6b15 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -178,7 +178,6 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) { int r, i; - radeon_ttm_placement_from_domain(bo, domain); if (bo->pin_count) { bo->pin_count++; if (gpu_addr) @@ -186,6 +185,8 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) return 0; } radeon_ttm_placement_from_domain(bo, domain); + /* force to pin into visible video ram */ + bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index d5aeb2a31d59..47f046b78c6b 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c @@ -462,12 +462,13 @@ void rs600_mc_init(struct radeon_device *rdev) { u64 base; + rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); + rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); rdev->mc.vram_is_ddr = true; rdev->mc.vram_width = 128; rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); rdev->mc.mc_vram_size = rdev->mc.real_vram_size; - rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); - rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); + rdev->mc.visible_vram_size = rdev->mc.aper_size; rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); base = RREG32_MC(R_000004_MC_FB_LOCATION); base = G_000004_MC_FB_START(base) << 16; diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index 8d37501da7df..83b9174f76f2 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c @@ -141,6 +141,7 @@ void rs690_mc_init(struct radeon_device *rdev) rdev->mc.mc_vram_size = rdev->mc.real_vram_size; rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); + rdev->mc.visible_vram_size = rdev->mc.aper_size; base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); base = G_000100_MC_FB_START(base) << 16; rs690_pm_info(rdev); diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 88356b0a1f63..37887dee12af 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -901,6 +901,7 @@ int rv770_mc_init(struct radeon_device *rdev) /* Setup GPU memory space */ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); + rdev->mc.visible_vram_size = rdev->mc.aper_size; /* FIXME remove this once we support unmappable VRAM */ if (rdev->mc.mc_vram_size > rdev->mc.aper_size) { rdev->mc.mc_vram_size = rdev->mc.aper_size; -- cgit v1.2.3 From 939461d59d6ac4e5142f767d24810c9b4b5caa38 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Sun, 14 Feb 2010 07:10:10 +0100 Subject: drm/radeon/kms: add support for square microtiles on r3xx-r5xx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marek Olšák Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r300.c | 8 +++++++- drivers/gpu/drm/radeon/r300_reg.h | 2 ++ include/drm/radeon_drm.h | 1 + 3 files changed, 10 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index dc32cd13a837..4cef90cd74e5 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -705,6 +705,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p, tile_flags |= R300_TXO_MACRO_TILE; if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) tile_flags |= R300_TXO_MICRO_TILE; + else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) + tile_flags |= R300_TXO_MICRO_TILE_SQUARE; tmp = idx_value + ((u32)reloc->lobj.gpu_offset); tmp |= tile_flags; @@ -755,6 +757,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p, tile_flags |= R300_COLOR_TILE_ENABLE; if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) tile_flags |= R300_COLOR_MICROTILE_ENABLE; + else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) + tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; tmp = idx_value & ~(0x7 << 16); tmp |= tile_flags; @@ -826,7 +830,9 @@ static int r300_packet0_check(struct radeon_cs_parser *p, if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) tile_flags |= R300_DEPTHMACROTILE_ENABLE; if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) - tile_flags |= R300_DEPTHMICROTILE_TILED;; + tile_flags |= R300_DEPTHMICROTILE_TILED; + else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) + tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; tmp = idx_value & ~(0x7 << 16); tmp |= tile_flags; diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h index 1735a2b69580..1a0d5362cd79 100644 --- a/drivers/gpu/drm/radeon/r300_reg.h +++ b/drivers/gpu/drm/radeon/r300_reg.h @@ -952,6 +952,7 @@ # define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0) # define R300_TXO_MACRO_TILE (1 << 2) # define R300_TXO_MICRO_TILE (1 << 3) +# define R300_TXO_MICRO_TILE_SQUARE (2 << 3) # define R300_TXO_OFFSET_MASK 0xffffffe0 # define R300_TXO_OFFSET_SHIFT 5 /* END: Guess from R200 */ @@ -1360,6 +1361,7 @@ # define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */ # define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */ # define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */ +# define R300_COLOR_MICROTILE_SQUARE_ENABLE (2 << 17) # define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ # define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ # define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h index 39537f3cf98a..81e614bf2dc3 100644 --- a/include/drm/radeon_drm.h +++ b/include/drm/radeon_drm.h @@ -808,6 +808,7 @@ struct drm_radeon_gem_create { #define RADEON_TILING_SWAP_32BIT 0x8 #define RADEON_TILING_SURFACE 0x10 /* this object requires a surface * when mapped - i.e. front buffer */ +#define RADEON_TILING_MICRO_SQUARE 0x20 struct drm_radeon_gem_set_tiling { uint32_t handle; -- cgit v1.2.3 From 383be5d1789d9a7a2e77dca1cb0aca89507d069e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 23 Feb 2010 03:24:38 -0500 Subject: drm/radeon/kms: update new pll algo - add support for pre-avivo chips - add support for fixed post/ref dividers - add support for non-fractional fb dividers By default avivo chips use the new algo and pre-avivo chips use the old algo. Use the "new_pll" module option to toggle between them. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/atombios_crtc.c | 12 +- drivers/gpu/drm/radeon/radeon_atombios.c | 12 +- drivers/gpu/drm/radeon/radeon_display.c | 232 +++++++++++++++++++--------- drivers/gpu/drm/radeon/radeon_drv.c | 4 +- drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 5 +- drivers/gpu/drm/radeon/radeon_mode.h | 2 +- 6 files changed, 178 insertions(+), 89 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 0ec6934c3a26..dd9fdf560611 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -438,12 +438,16 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, /* select the PLL algo */ if (ASIC_IS_AVIVO(rdev)) { - if (radeon_new_pll) - pll->algo = PLL_ALGO_AVIVO; + if (radeon_new_pll == 0) + pll->algo = PLL_ALGO_LEGACY; + else + pll->algo = PLL_ALGO_NEW; + } else { + if (radeon_new_pll == 1) + pll->algo = PLL_ALGO_NEW; else pll->algo = PLL_ALGO_LEGACY; - } else - pll->algo = PLL_ALGO_LEGACY; + } if (ASIC_IS_AVIVO(rdev)) { if ((rdev->family == CHIP_RS600) || diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 33aed6c2d41a..6f8619cd1a0d 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -1191,12 +1191,16 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id); if (ASIC_IS_AVIVO(rdev)) { - if (radeon_new_pll) - lvds->pll_algo = PLL_ALGO_AVIVO; + if (radeon_new_pll == 0) + lvds->pll_algo = PLL_ALGO_LEGACY; + else + lvds->pll_algo = PLL_ALGO_NEW; + } else { + if (radeon_new_pll == 1) + lvds->pll_algo = PLL_ALGO_NEW; else lvds->pll_algo = PLL_ALGO_LEGACY; - } else - lvds->pll_algo = PLL_ALGO_LEGACY; + } /* LVDS quirks */ radeon_atom_apply_lvds_quirks(dev, lvds); diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 257827806aee..e35cc3da8f22 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -603,95 +603,173 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll, *post_div_p = best_post_div; } -static void radeon_compute_pll_avivo(struct radeon_pll *pll, - uint64_t freq, - uint32_t *dot_clock_p, - uint32_t *fb_div_p, - uint32_t *frac_fb_div_p, - uint32_t *ref_div_p, - uint32_t *post_div_p) +static bool +calc_fb_div(struct radeon_pll *pll, + uint32_t freq, + uint32_t post_div, + uint32_t ref_div, + uint32_t *fb_div, + uint32_t *fb_div_frac) { - fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq; - fixed20_12 pll_out_max, pll_out_min; - fixed20_12 pll_in_max, pll_in_min; - fixed20_12 reference_freq; - fixed20_12 error, ffreq, a, b; - - pll_out_max.full = rfixed_const(pll->pll_out_max); - pll_out_min.full = rfixed_const(pll->pll_out_min); - pll_in_max.full = rfixed_const(pll->pll_in_max); - pll_in_min.full = rfixed_const(pll->pll_in_min); - reference_freq.full = rfixed_const(pll->reference_freq); - do_div(freq, 10); + fixed20_12 feedback_divider, a, b; + u32 vco_freq; + + vco_freq = freq * post_div; + /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */ + a.full = rfixed_const(pll->reference_freq); + feedback_divider.full = rfixed_const(vco_freq); + feedback_divider.full = rfixed_div(feedback_divider, a); + a.full = rfixed_const(ref_div); + feedback_divider.full = rfixed_mul(feedback_divider, a); + + if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { + /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */ + a.full = rfixed_const(10); + feedback_divider.full = rfixed_mul(feedback_divider, a); + feedback_divider.full += rfixed_const_half(0); + feedback_divider.full = rfixed_floor(feedback_divider); + feedback_divider.full = rfixed_div(feedback_divider, a); + + /* *fb_div = floor(feedback_divider); */ + a.full = rfixed_floor(feedback_divider); + *fb_div = rfixed_trunc(a); + /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */ + a.full = rfixed_const(10); + b.full = rfixed_mul(feedback_divider, a); + + feedback_divider.full = rfixed_floor(feedback_divider); + feedback_divider.full = rfixed_mul(feedback_divider, a); + feedback_divider.full = b.full - feedback_divider.full; + *fb_div_frac = rfixed_trunc(feedback_divider); + } else { + /* *fb_div = floor(feedback_divider + 0.5); */ + feedback_divider.full += rfixed_const_half(0); + feedback_divider.full = rfixed_floor(feedback_divider); + + *fb_div = rfixed_trunc(feedback_divider); + *fb_div_frac = 0; + } + + if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div)) + return false; + else + return true; +} + +static bool +calc_fb_ref_div(struct radeon_pll *pll, + uint32_t freq, + uint32_t post_div, + uint32_t *fb_div, + uint32_t *fb_div_frac, + uint32_t *ref_div) +{ + fixed20_12 ffreq, max_error, error, pll_out, a; + u32 vco; + ffreq.full = rfixed_const(freq); - error.full = rfixed_const(100 * 100); + /* max_error = ffreq * 0.0025; */ + a.full = rfixed_const(400); + max_error.full = rfixed_div(ffreq, a); + + for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) { + if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) { + vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac)); + vco = vco / ((*ref_div) * 10); + + if ((vco < pll->pll_out_min) || (vco > pll->pll_out_max)) + continue; - /* max p */ - p.full = rfixed_div(pll_out_max, ffreq); - p.full = rfixed_floor(p); + /* pll_out = vco / post_div; */ + a.full = rfixed_const(post_div); + pll_out.full = rfixed_const(vco); + pll_out.full = rfixed_div(pll_out, a); - /* min m */ - m.full = rfixed_div(reference_freq, pll_in_max); - m.full = rfixed_ceil(m); + if (pll_out.full >= ffreq.full) { + error.full = pll_out.full - ffreq.full; + if (error.full <= max_error.full) + return true; + } + } + } + return false; +} - while (1) { - n.full = rfixed_div(ffreq, reference_freq); - n.full = rfixed_mul(n, m); - n.full = rfixed_mul(n, p); +static void radeon_compute_pll_new(struct radeon_pll *pll, + uint64_t freq, + uint32_t *dot_clock_p, + uint32_t *fb_div_p, + uint32_t *frac_fb_div_p, + uint32_t *ref_div_p, + uint32_t *post_div_p) +{ + u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0; + u32 best_freq = 0, vco_frequency; - f_vco.full = rfixed_div(n, m); - f_vco.full = rfixed_mul(f_vco, reference_freq); + /* freq = freq / 10; */ + do_div(freq, 10); - f_pclk.full = rfixed_div(f_vco, p); + if (pll->flags & RADEON_PLL_USE_POST_DIV) { + post_div = pll->post_div; + if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div)) + goto done; + + vco_frequency = freq * post_div; + if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) + goto done; + + if (pll->flags & RADEON_PLL_USE_REF_DIV) { + ref_div = pll->reference_div; + if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) + goto done; + if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac)) + goto done; + } + } else { + for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) { + if (pll->flags & RADEON_PLL_LEGACY) { + if ((post_div == 5) || + (post_div == 7) || + (post_div == 9) || + (post_div == 10) || + (post_div == 11)) + continue; + } - if (f_pclk.full > ffreq.full) - error.full = f_pclk.full - ffreq.full; - else - error.full = ffreq.full - f_pclk.full; - error.full = rfixed_div(error, f_pclk); - a.full = rfixed_const(100 * 100); - error.full = rfixed_mul(error, a); - - a.full = rfixed_mul(m, p); - a.full = rfixed_div(n, a); - best_freq.full = rfixed_mul(reference_freq, a); - - if (rfixed_trunc(error) < 25) - break; - - a.full = rfixed_const(1); - m.full = m.full + a.full; - a.full = rfixed_div(reference_freq, m); - if (a.full >= pll_in_min.full) - continue; + if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) + continue; - m.full = rfixed_div(reference_freq, pll_in_max); - m.full = rfixed_ceil(m); - a.full= rfixed_const(1); - p.full = p.full - a.full; - a.full = rfixed_mul(p, ffreq); - if (a.full >= pll_out_min.full) - continue; - else { - DRM_ERROR("Unable to find pll dividers\n"); - break; + vco_frequency = freq * post_div; + if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) + continue; + if (pll->flags & RADEON_PLL_USE_REF_DIV) { + ref_div = pll->reference_div; + if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) + goto done; + if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac)) + break; + } else { + if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div)) + break; + } } } - a.full = rfixed_const(10); - b.full = rfixed_mul(n, a); + best_freq = pll->reference_freq * 10 * fb_div; + best_freq += pll->reference_freq * fb_div_frac; + best_freq = best_freq / (ref_div * post_div); - frac_n.full = rfixed_floor(n); - frac_n.full = rfixed_mul(frac_n, a); - frac_n.full = b.full - frac_n.full; +done: + if (best_freq == 0) + DRM_ERROR("Couldn't find valid PLL dividers\n"); - *dot_clock_p = rfixed_trunc(best_freq); - *fb_div_p = rfixed_trunc(n); - *frac_fb_div_p = rfixed_trunc(frac_n); - *ref_div_p = rfixed_trunc(m); - *post_div_p = rfixed_trunc(p); + *dot_clock_p = best_freq / 10; + *fb_div_p = fb_div; + *frac_fb_div_p = fb_div_frac; + *ref_div_p = ref_div; + *post_div_p = post_div; - DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p); + DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p); } void radeon_compute_pll(struct radeon_pll *pll, @@ -703,9 +781,9 @@ void radeon_compute_pll(struct radeon_pll *pll, uint32_t *post_div_p) { switch (pll->algo) { - case PLL_ALGO_AVIVO: - radeon_compute_pll_avivo(pll, freq, dot_clock_p, fb_div_p, - frac_fb_div_p, ref_div_p, post_div_p); + case PLL_ALGO_NEW: + radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p, + frac_fb_div_p, ref_div_p, post_div_p); break; case PLL_ALGO_LEGACY: default: diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index a9572e6d4d64..be99d4e55a34 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -86,7 +86,7 @@ int radeon_benchmarking = 0; int radeon_testing = 0; int radeon_connector_table = 0; int radeon_tv = 1; -int radeon_new_pll = 1; +int radeon_new_pll = -1; int radeon_dynpm = -1; int radeon_audio = 1; @@ -123,7 +123,7 @@ module_param_named(connector_table, radeon_connector_table, int, 0444); MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); module_param_named(tv, radeon_tv, int, 0444); -MODULE_PARM_DESC(new_pll, "Select new PLL code for AVIVO chips"); +MODULE_PARM_DESC(new_pll, "Select new PLL code"); module_param_named(new_pll, radeon_new_pll, int, 0444); MODULE_PARM_DESC(dynpm, "Disable/Enable dynamic power management (1 = enable)"); diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index 643251719f1c..df23d6a01d02 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c @@ -703,7 +703,10 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) pll = &rdev->clock.p1pll; pll->flags = RADEON_PLL_LEGACY; - pll->algo = PLL_ALGO_LEGACY; + if (radeon_new_pll == 1) + pll->algo = PLL_ALGO_NEW; + else + pll->algo = PLL_ALGO_LEGACY; if (mode->clock > 200000) /* range limits??? */ pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 8912f2e8e640..1702b820aa4d 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -133,7 +133,7 @@ struct radeon_tmds_pll { /* pll algo */ enum radeon_pll_algo { PLL_ALGO_LEGACY, - PLL_ALGO_AVIVO + PLL_ALGO_NEW }; struct radeon_pll { -- cgit v1.2.3 From 6a8a2d702b33c6ed5c789f21b4e89fdf221f01ca Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 23 Feb 2010 21:56:12 -0500 Subject: drm/radeon/kms/atom: fix shr/shl ops The whole attribute table is valid for shr/shl ops. Fixes fdo bug 26668 Signed-off-by: Alex Deucher Cc: stable@kernel.org Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/atom.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c index e3b44562d265..614295a11dfb 100644 --- a/drivers/gpu/drm/radeon/atom.c +++ b/drivers/gpu/drm/radeon/atom.c @@ -878,8 +878,6 @@ static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg) uint8_t attr = U8((*ptr)++), shift; uint32_t saved, dst; int dptr = *ptr; - attr &= 0x38; - attr |= atom_def_dst[attr >> 3] << 6; SDEBUG(" dst: "); dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); shift = atom_get_src(ctx, attr, ptr); @@ -894,8 +892,6 @@ static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg) uint8_t attr = U8((*ptr)++), shift; uint32_t saved, dst; int dptr = *ptr; - attr &= 0x38; - attr |= atom_def_dst[attr >> 3] << 6; SDEBUG(" dst: "); dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); shift = atom_get_src(ctx, attr, ptr); -- cgit v1.2.3 From 290e55056ec3d25c72088628245d8cae037b30db Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Sat, 20 Feb 2010 03:22:21 +0100 Subject: drm/ttm: handle OOM in ttm_tt_swapout - Without this change I get a general protection fault. - Also use PTR_ERR where applicable. Signed-off-by: Maarten Maathuis Reviewed-by: Dave Airlie Acked-by: Thomas Hellstrom Cc: stable@kernel.org Signed-off-by: Dave Airlie --- drivers/gpu/drm/ttm/ttm_tt.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index e2123af7775a..160c2745f8d8 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -476,7 +476,7 @@ static int ttm_tt_swapin(struct ttm_tt *ttm) void *from_virtual; void *to_virtual; int i; - int ret; + int ret = -ENOMEM; if (ttm->page_flags & TTM_PAGE_FLAG_USER) { ret = ttm_tt_set_user(ttm, ttm->tsk, ttm->start, @@ -495,8 +495,10 @@ static int ttm_tt_swapin(struct ttm_tt *ttm) for (i = 0; i < ttm->num_pages; ++i) { from_page = read_mapping_page(swap_space, i, NULL); - if (IS_ERR(from_page)) + if (IS_ERR(from_page)) { + ret = PTR_ERR(from_page); goto out_err; + } to_page = __ttm_tt_get_page(ttm, i); if (unlikely(to_page == NULL)) goto out_err; @@ -519,7 +521,7 @@ static int ttm_tt_swapin(struct ttm_tt *ttm) return 0; out_err: ttm_tt_free_alloced_pages(ttm); - return -ENOMEM; + return ret; } int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistant_swap_storage) @@ -531,6 +533,7 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistant_swap_storage) void *from_virtual; void *to_virtual; int i; + int ret = -ENOMEM; BUG_ON(ttm->state != tt_unbound && ttm->state != tt_unpopulated); BUG_ON(ttm->caching_state != tt_cached); @@ -553,7 +556,7 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistant_swap_storage) 0); if (unlikely(IS_ERR(swap_storage))) { printk(KERN_ERR "Failed allocating swap storage.\n"); - return -ENOMEM; + return PTR_ERR(swap_storage); } } else swap_storage = persistant_swap_storage; @@ -565,9 +568,10 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistant_swap_storage) if (unlikely(from_page == NULL)) continue; to_page = read_mapping_page(swap_space, i, NULL); - if (unlikely(to_page == NULL)) + if (unlikely(IS_ERR(to_page))) { + ret = PTR_ERR(to_page); goto out_err; - + } preempt_disable(); from_virtual = kmap_atomic(from_page, KM_USER0); to_virtual = kmap_atomic(to_page, KM_USER1); @@ -591,5 +595,5 @@ out_err: if (!persistant_swap_storage) fput(swap_storage); - return -ENOMEM; + return ret; } -- cgit v1.2.3 From 9fd1de52945e06ed88a440c99ca92dab74b9b33c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 25 Feb 2010 14:05:09 +1000 Subject: fb: for framebuffer handover don't exit the loop early. An offb machine has been seen in the fields which adds two offb nodes, so continue scanning the list after removing one. Signed-off-by: Dave Airlie --- drivers/video/fbmem.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c index 99bbd282ce63..a15b44e9c003 100644 --- a/drivers/video/fbmem.c +++ b/drivers/video/fbmem.c @@ -1513,7 +1513,6 @@ register_framebuffer(struct fb_info *fb_info) fb_info->fix.id, registered_fb[i]->fix.id); unregister_framebuffer(registered_fb[i]); - break; } } } -- cgit v1.2.3 From ff9e5279b14dc024599cc705ee199dadb94e90a3 Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Mon, 1 Feb 2010 20:58:27 +0100 Subject: drm/nouveau: protect channel create/destroy and irq handler with a spinlock The nv50 pgraph handler (for example) could reenable pgraph fifo access and that would be bad when pgraph context is being unloaded (we need the guarantee a ctxprog isn't running). Signed-off-by: Maarten Maathuis Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_channel.c | 13 ++++++++++++- drivers/gpu/drm/nouveau/nouveau_drv.h | 3 +++ drivers/gpu/drm/nouveau/nouveau_irq.c | 5 +++++ drivers/gpu/drm/nouveau/nouveau_state.c | 1 + drivers/gpu/drm/nouveau/nv04_fifo.c | 5 +++++ drivers/gpu/drm/nouveau/nv40_fifo.c | 5 +++++ drivers/gpu/drm/nouveau/nv50_fifo.c | 5 +++++ 7 files changed, 36 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c index 2281f99da7fc..f7ca95003f54 100644 --- a/drivers/gpu/drm/nouveau/nouveau_channel.c +++ b/drivers/gpu/drm/nouveau/nouveau_channel.c @@ -275,9 +275,18 @@ nouveau_channel_free(struct nouveau_channel *chan) */ nouveau_fence_fini(chan); - /* Ensure the channel is no longer active on the GPU */ + /* This will prevent pfifo from switching channels. */ pfifo->reassign(dev, false); + /* We want to give pgraph a chance to idle and get rid of all potential + * errors. We need to do this before the lock, otherwise the irq handler + * is unable to process them. + */ + if (pgraph->channel(dev) == chan) + nouveau_wait_for_idle(dev); + + spin_lock_irqsave(&dev_priv->context_switch_lock, flags); + pgraph->fifo_access(dev, false); if (pgraph->channel(dev) == chan) pgraph->unload_context(dev); @@ -293,6 +302,8 @@ nouveau_channel_free(struct nouveau_channel *chan) pfifo->reassign(dev, true); + spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); + /* Release the channel's resources */ nouveau_gpuobj_ref_del(dev, &chan->pushbuf); if (chan->pushbuf_bo) { diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 1c15ef37b71c..52cc13bd02b9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -533,6 +533,9 @@ struct drm_nouveau_private { struct nouveau_engine engine; struct nouveau_channel *channel; + /* For PFIFO and PGRAPH. */ + spinlock_t context_switch_lock; + /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ struct nouveau_gpuobj *ramht; uint32_t ramin_rsvd_vram; diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c index 447f9f69d6b1..95220ddebb45 100644 --- a/drivers/gpu/drm/nouveau/nouveau_irq.c +++ b/drivers/gpu/drm/nouveau/nouveau_irq.c @@ -691,11 +691,14 @@ nouveau_irq_handler(DRM_IRQ_ARGS) struct drm_device *dev = (struct drm_device *)arg; struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t status, fbdev_flags = 0; + unsigned long flags; status = nv_rd32(dev, NV03_PMC_INTR_0); if (!status) return IRQ_NONE; + spin_lock_irqsave(&dev_priv->context_switch_lock, flags); + if (dev_priv->fbdev_info) { fbdev_flags = dev_priv->fbdev_info->flags; dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED; @@ -733,5 +736,7 @@ nouveau_irq_handler(DRM_IRQ_ARGS) if (dev_priv->fbdev_info) dev_priv->fbdev_info->flags = fbdev_flags; + spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); + return IRQ_HANDLED; } diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index a4851af5b05e..ed5ac0b9a0ac 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c @@ -391,6 +391,7 @@ nouveau_card_init(struct drm_device *dev) goto out; engine = &dev_priv->engine; dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED; + spin_lock_init(&dev_priv->context_switch_lock); /* Parse BIOS tables / Run init tables if card not POSTed */ if (drm_core_check_feature(dev, DRIVER_MODESET)) { diff --git a/drivers/gpu/drm/nouveau/nv04_fifo.c b/drivers/gpu/drm/nouveau/nv04_fifo.c index f31347b8c9b0..66fe55983b6e 100644 --- a/drivers/gpu/drm/nouveau/nv04_fifo.c +++ b/drivers/gpu/drm/nouveau/nv04_fifo.c @@ -117,6 +117,7 @@ nv04_fifo_create_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; + unsigned long flags; int ret; ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0, @@ -127,6 +128,8 @@ nv04_fifo_create_context(struct nouveau_channel *chan) if (ret) return ret; + spin_lock_irqsave(&dev_priv->context_switch_lock, flags); + /* Setup initial state */ dev_priv->engine.instmem.prepare_access(dev, true); RAMFC_WR(DMA_PUT, chan->pushbuf_base); @@ -144,6 +147,8 @@ nv04_fifo_create_context(struct nouveau_channel *chan) /* enable the fifo dma operation */ nv_wr32(dev, NV04_PFIFO_MODE, nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id)); + + spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); return 0; } diff --git a/drivers/gpu/drm/nouveau/nv40_fifo.c b/drivers/gpu/drm/nouveau/nv40_fifo.c index b4f19ccb8b41..6b2ef4a9fce1 100644 --- a/drivers/gpu/drm/nouveau/nv40_fifo.c +++ b/drivers/gpu/drm/nouveau/nv40_fifo.c @@ -37,6 +37,7 @@ nv40_fifo_create_context(struct nouveau_channel *chan) struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; uint32_t fc = NV40_RAMFC(chan->id); + unsigned long flags; int ret; ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0, @@ -45,6 +46,8 @@ nv40_fifo_create_context(struct nouveau_channel *chan) if (ret) return ret; + spin_lock_irqsave(&dev_priv->context_switch_lock, flags); + dev_priv->engine.instmem.prepare_access(dev, true); nv_wi32(dev, fc + 0, chan->pushbuf_base); nv_wi32(dev, fc + 4, chan->pushbuf_base); @@ -63,6 +66,8 @@ nv40_fifo_create_context(struct nouveau_channel *chan) /* enable the fifo dma operation */ nv_wr32(dev, NV04_PFIFO_MODE, nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id)); + + spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); return 0; } diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c index 204a79ff10f4..369ecb4cee57 100644 --- a/drivers/gpu/drm/nouveau/nv50_fifo.c +++ b/drivers/gpu/drm/nouveau/nv50_fifo.c @@ -243,6 +243,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan) struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *ramfc = NULL; + unsigned long flags; int ret; NV_DEBUG(dev, "ch%d\n", chan->id); @@ -278,6 +279,8 @@ nv50_fifo_create_context(struct nouveau_channel *chan) return ret; } + spin_lock_irqsave(&dev_priv->context_switch_lock, flags); + dev_priv->engine.instmem.prepare_access(dev, true); nv_wo32(dev, ramfc, 0x08/4, chan->pushbuf_base); @@ -306,10 +309,12 @@ nv50_fifo_create_context(struct nouveau_channel *chan) ret = nv50_fifo_channel_enable(dev, chan->id, false); if (ret) { NV_ERROR(dev, "error enabling ch%d: %d\n", chan->id, ret); + spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); nouveau_gpuobj_ref_del(dev, &chan->ramfc); return ret; } + spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); return 0; } -- cgit v1.2.3 From 9a391ad8a2cdd7e5be9b6aabb56f4a46683ba377 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 11 Feb 2010 16:37:26 +1000 Subject: drm/nv50: switch to indirect push buffer controls PFIFO on G80 and up has a new mode where the main ring buffer is simply a ring of pointers to indirect buffers containing the actual command/data packets. In order to be able to implement index buffers in the 3D driver we need to be able to submit data-only push buffers right after the cmd packet header, which is only possible using the new command submission method. This commit doesn't make it possible to implement index buffers yet, some userspace interface changes will be required, but it does allow for testing/debugging of the hardware-side support in the meantime. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_debugfs.c | 11 +++ drivers/gpu/drm/nouveau/nouveau_dma.c | 108 +++++++++++++++++++++++++++++- drivers/gpu/drm/nouveau/nouveau_dma.h | 21 ++++-- drivers/gpu/drm/nouveau/nouveau_drv.h | 7 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 15 ++++- drivers/gpu/drm/nouveau/nv50_fifo.c | 8 +-- 6 files changed, 155 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c index d79db3698f16..89e36ee057c8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c +++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c @@ -47,12 +47,23 @@ nouveau_debugfs_channel_info(struct seq_file *m, void *data) seq_printf(m, " cur: 0x%08x\n", chan->dma.cur << 2); seq_printf(m, " put: 0x%08x\n", chan->dma.put << 2); seq_printf(m, " free: 0x%08x\n", chan->dma.free << 2); + if (chan->dma.ib_max) { + seq_printf(m, " ib max: 0x%08x\n", chan->dma.ib_max); + seq_printf(m, " ib put: 0x%08x\n", chan->dma.ib_put); + seq_printf(m, " ib free: 0x%08x\n", chan->dma.ib_free); + } seq_printf(m, "gpu fifo state:\n"); seq_printf(m, " get: 0x%08x\n", nvchan_rd32(chan, chan->user_get)); seq_printf(m, " put: 0x%08x\n", nvchan_rd32(chan, chan->user_put)); + if (chan->dma.ib_max) { + seq_printf(m, " ib get: 0x%08x\n", + nvchan_rd32(chan, 0x88)); + seq_printf(m, " ib put: 0x%08x\n", + nvchan_rd32(chan, 0x8c)); + } seq_printf(m, "last fence : %d\n", chan->fence.sequence); seq_printf(m, "last signalled: %d\n", chan->fence.sequence_ack); diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c index 50d9e67745af..b9c80bb17250 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.c +++ b/drivers/gpu/drm/nouveau/nouveau_dma.c @@ -32,7 +32,22 @@ void nouveau_dma_pre_init(struct nouveau_channel *chan) { - chan->dma.max = (chan->pushbuf_bo->bo.mem.size >> 2) - 2; + struct drm_nouveau_private *dev_priv = chan->dev->dev_private; + struct nouveau_bo *pushbuf = chan->pushbuf_bo; + + if (dev_priv->card_type == NV_50) { + const int ib_size = pushbuf->bo.mem.size / 2; + + chan->dma.ib_base = (pushbuf->bo.mem.size - ib_size) >> 2; + chan->dma.ib_max = (ib_size / 8) - 1; + chan->dma.ib_put = 0; + chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; + + chan->dma.max = (pushbuf->bo.mem.size - ib_size) >> 2; + } else { + chan->dma.max = (pushbuf->bo.mem.size >> 2) - 2; + } + chan->dma.put = 0; chan->dma.cur = chan->dma.put; chan->dma.free = chan->dma.max - chan->dma.cur; @@ -162,12 +177,101 @@ READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout) return (val - chan->pushbuf_base) >> 2; } +void +nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo, + int delta, int dwords) +{ + struct nouveau_bo *pb = chan->pushbuf_bo; + uint64_t offset = (bo->bo.mem.mm_node->start << PAGE_SHIFT) + delta; + int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base; + + BUG_ON(chan->dma.ib_free < 1); + nouveau_bo_wr32(pb, ip++, offset); + nouveau_bo_wr32(pb, ip++, dwords << 10); + + chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max; + nvchan_wr32(chan, 0x8c, chan->dma.ib_put); + chan->dma.ib_free--; +} + +static int +nv50_dma_push_wait(struct nouveau_channel *chan, int count) +{ + uint32_t cnt = 0, prev_get = 0; + + while (chan->dma.ib_free < count) { + uint32_t get = nvchan_rd32(chan, 0x88); + if (get != prev_get) { + prev_get = get; + cnt = 0; + } + + if ((++cnt & 0xff) == 0) { + DRM_UDELAY(1); + if (cnt > 100000) + return -EBUSY; + } + + chan->dma.ib_free = get - chan->dma.ib_put; + if (chan->dma.ib_free <= 0) + chan->dma.ib_free += chan->dma.ib_max + 1; + } + + return 0; +} + +static int +nv50_dma_wait(struct nouveau_channel *chan, int slots, int count) +{ + uint32_t cnt = 0, prev_get = 0; + int ret; + + ret = nv50_dma_push_wait(chan, slots + 1); + if (unlikely(ret)) + return ret; + + while (chan->dma.free < count) { + int get = READ_GET(chan, &prev_get, &cnt); + if (unlikely(get < 0)) { + if (get == -EINVAL) + continue; + + return get; + } + + if (get <= chan->dma.cur) { + chan->dma.free = chan->dma.max - chan->dma.cur; + if (chan->dma.free >= count) + break; + + FIRE_RING(chan); + do { + get = READ_GET(chan, &prev_get, &cnt); + if (unlikely(get < 0)) { + if (get == -EINVAL) + continue; + return get; + } + } while (get == 0); + chan->dma.cur = 0; + chan->dma.put = 0; + } + + chan->dma.free = get - chan->dma.cur - 1; + } + + return 0; +} + int -nouveau_dma_wait(struct nouveau_channel *chan, int size) +nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size) { uint32_t prev_get = 0, cnt = 0; int get; + if (chan->dma.ib_max) + return nv50_dma_wait(chan, slots, size); + while (chan->dma.free < size) { get = READ_GET(chan, &prev_get, &cnt); if (unlikely(get == -EBUSY)) diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index dabfd655f93e..da6e16dafa4d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -31,6 +31,9 @@ #define NOUVEAU_DMA_DEBUG 0 #endif +void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *, + int delta, int dwords); + /* * There's a hw race condition where you can't jump to your PUT offset, * to avoid this we jump to offset + SKIPS and fill the difference with @@ -96,13 +99,11 @@ enum { static __must_check inline int RING_SPACE(struct nouveau_channel *chan, int size) { - if (chan->dma.free < size) { - int ret; + int ret; - ret = nouveau_dma_wait(chan, size); - if (ret) - return ret; - } + ret = nouveau_dma_wait(chan, 1, size); + if (ret) + return ret; chan->dma.free -= size; return 0; @@ -146,7 +147,13 @@ FIRE_RING(struct nouveau_channel *chan) return; chan->accel_done = true; - WRITE_PUT(chan->dma.cur); + if (chan->dma.ib_max) { + nv50_dma_push(chan, chan->pushbuf_bo, chan->dma.put << 2, + chan->dma.cur - chan->dma.put); + } else { + WRITE_PUT(chan->dma.cur); + } + chan->dma.put = chan->dma.cur; } diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 52cc13bd02b9..d221044e0793 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -239,6 +239,11 @@ struct nouveau_channel { int cur; int put; /* access via pushbuf_bo */ + + int ib_base; + int ib_max; + int ib_free; + int ib_put; } dma; uint32_t sw_subchannel[8]; @@ -848,7 +853,7 @@ nouveau_debugfs_channel_fini(struct nouveau_channel *chan) /* nouveau_dma.c */ extern void nouveau_dma_pre_init(struct nouveau_channel *); extern int nouveau_dma_init(struct nouveau_channel *); -extern int nouveau_dma_wait(struct nouveau_channel *, int size); +extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); /* nouveau_acpi.c */ #ifdef CONFIG_ACPI diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 70cc30803e3b..986b67099f6c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -707,7 +707,7 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data, uint32_t retaddy; if (chan->dma.free < 4 + NOUVEAU_DMA_SKIPS) { - ret = nouveau_dma_wait(chan, 4 + NOUVEAU_DMA_SKIPS); + ret = nouveau_dma_wait(chan, 0, 4 + NOUVEAU_DMA_SKIPS); if (ret) { NV_ERROR(dev, "jmp_space: %d\n", ret); goto out; @@ -754,6 +754,15 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data, } } + if (chan->dma.ib_max) { + ret = nouveau_dma_wait(chan, 2, 6); + if (ret) { + NV_INFO(dev, "nv50cal_space: %d\n", ret); + goto out; + } + + nv50_dma_push(chan, pbbo, req->offset, req->nr_dwords); + } else if (PUSHBUF_CAL) { ret = RING_SPACE(chan, 2); if (ret) { @@ -792,6 +801,10 @@ out: kfree(bo); out_next: + if (chan->dma.ib_max) { + req->suffix0 = 0x00000000; + req->suffix1 = 0x00000000; + } else if (PUSHBUF_CAL) { req->suffix0 = 0x00020000; req->suffix1 = 0x00000000; diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c index 369ecb4cee57..e20c0e2474f3 100644 --- a/drivers/gpu/drm/nouveau/nv50_fifo.c +++ b/drivers/gpu/drm/nouveau/nv50_fifo.c @@ -283,17 +283,17 @@ nv50_fifo_create_context(struct nouveau_channel *chan) dev_priv->engine.instmem.prepare_access(dev, true); - nv_wo32(dev, ramfc, 0x08/4, chan->pushbuf_base); - nv_wo32(dev, ramfc, 0x10/4, chan->pushbuf_base); nv_wo32(dev, ramfc, 0x48/4, chan->pushbuf->instance >> 4); nv_wo32(dev, ramfc, 0x80/4, (0xc << 24) | (chan->ramht->instance >> 4)); - nv_wo32(dev, ramfc, 0x3c/4, 0x00086078); nv_wo32(dev, ramfc, 0x44/4, 0x2101ffff); nv_wo32(dev, ramfc, 0x60/4, 0x7fffffff); nv_wo32(dev, ramfc, 0x40/4, 0x00000000); nv_wo32(dev, ramfc, 0x7c/4, 0x30000001); nv_wo32(dev, ramfc, 0x78/4, 0x00000000); - nv_wo32(dev, ramfc, 0x4c/4, 0xffffffff); + nv_wo32(dev, ramfc, 0x3c/4, 0x403f6078); + nv_wo32(dev, ramfc, 0x50/4, chan->pushbuf_base + + chan->dma.ib_base * 4); + nv_wo32(dev, ramfc, 0x54/4, drm_order(chan->dma.ib_max + 1) << 16); if (!IS_G80) { nv_wo32(dev, chan->ramin->gpuobj, 0, chan->id); -- cgit v1.2.3 From 2ccb04ecc704618d9cd2e26aad067dbb2a057366 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 12 Feb 2010 09:05:42 +1000 Subject: drm/nouveau: remove PUSHBUF_CAL macro Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_gem.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 986b67099f6c..df72cd847025 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -614,8 +614,6 @@ out: return ret; } -#define PUSHBUF_CAL (dev_priv->card_type >= NV_20) - int nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data, struct drm_file *file_priv) @@ -703,7 +701,7 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data, /* If presumed return address doesn't match, we need to map the * push buffer and fix it.. */ - if (!PUSHBUF_CAL) { + if (dev_priv->card_type < NV_20) { uint32_t retaddy; if (chan->dma.free < 4 + NOUVEAU_DMA_SKIPS) { @@ -741,7 +739,7 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data, req->offset / 4, pbvirt, is_iomem); - if (!PUSHBUF_CAL) { + if (dev_priv->card_type < NV_20) { nouveau_bo_wr32(pbbo, req->offset / 4 + req->nr_dwords - 2, req->suffix0); @@ -763,7 +761,7 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data, nv50_dma_push(chan, pbbo, req->offset, req->nr_dwords); } else - if (PUSHBUF_CAL) { + if (dev_priv->card_type >= NV_20) { ret = RING_SPACE(chan, 2); if (ret) { NV_ERROR(dev, "cal_space: %d\n", ret); @@ -805,7 +803,7 @@ out_next: req->suffix0 = 0x00000000; req->suffix1 = 0x00000000; } else - if (PUSHBUF_CAL) { + if (dev_priv->card_type >= NV_20) { req->suffix0 = 0x00020000; req->suffix1 = 0x00000000; } else { -- cgit v1.2.3 From d87897d4c853a5c136f60efa858d0d4cb3740f57 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 12 Feb 2010 11:11:54 +1000 Subject: drm/nv50: make pushbuf dma object cover entire vm This allows us to submit push buffers from any memtype to the hardware. We'll need this ability for VRAM index buffers at some point. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_channel.c | 13 +++++++++---- drivers/gpu/drm/nouveau/nouveau_dma.c | 6 +++--- 2 files changed, 12 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c index f7ca95003f54..ceb83961b16f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_channel.c +++ b/drivers/gpu/drm/nouveau/nouveau_channel.c @@ -35,22 +35,27 @@ nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan) struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_bo *pb = chan->pushbuf_bo; struct nouveau_gpuobj *pushbuf = NULL; - uint32_t start = pb->bo.mem.mm_node->start << PAGE_SHIFT; int ret; + if (dev_priv->card_type >= NV_50) { + ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0, + dev_priv->vm_end, NV_DMA_ACCESS_RO, + NV_DMA_TARGET_AGP, &pushbuf); + chan->pushbuf_base = pb->bo.offset; + } else if (pb->bo.mem.mem_type == TTM_PL_TT) { ret = nouveau_gpuobj_gart_dma_new(chan, 0, dev_priv->gart_info.aper_size, NV_DMA_ACCESS_RO, &pushbuf, NULL); - chan->pushbuf_base = start; + chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT; } else if (dev_priv->card_type != NV_04) { ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0, dev_priv->fb_available_size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM, &pushbuf); - chan->pushbuf_base = start; + chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT; } else { /* NV04 cmdbuf hack, from original ddx.. not sure of it's * exact reason for existing :) PCI access to cmdbuf in @@ -61,7 +66,7 @@ nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan) dev_priv->fb_available_size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_PCI, &pushbuf); - chan->pushbuf_base = start; + chan->pushbuf_base = pb->bo.mem.mm_node->start << PAGE_SHIFT; } ret = nouveau_gpuobj_ref_add(dev, chan, 0, pushbuf, &chan->pushbuf); diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c index b9c80bb17250..679b03c28df1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.c +++ b/drivers/gpu/drm/nouveau/nouveau_dma.c @@ -182,12 +182,12 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo, int delta, int dwords) { struct nouveau_bo *pb = chan->pushbuf_bo; - uint64_t offset = (bo->bo.mem.mm_node->start << PAGE_SHIFT) + delta; + uint64_t offset = bo->bo.offset + delta; int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base; BUG_ON(chan->dma.ib_free < 1); - nouveau_bo_wr32(pb, ip++, offset); - nouveau_bo_wr32(pb, ip++, dwords << 10); + nouveau_bo_wr32(pb, ip++, lower_32_bits(offset)); + nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | dwords << 10); chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max; nvchan_wr32(chan, 0x8c, chan->dma.ib_put); -- cgit v1.2.3 From a1606a9596e54da90ad6209071b357a4c1b0fa82 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 12 Feb 2010 10:27:35 +1000 Subject: drm/nouveau: new gem pushbuf interface, bump to 0.0.16 This commit breaks the userspace interface, and requires a new libdrm for nouveau to operate again. The multiple GEM_PUSHBUF ioctls that were present in 0.0.15 for compatibility purposes are now gone, and replaced with the new ioctl which allows for multiple push buffers to be submitted (necessary for hw index buffers in the nv50 3d driver) and relocations to be applied on any buffer. A number of other ioctls (CARD_INIT, GEM_PIN, GEM_UNPIN) that were needed for userspace modesetting have also been removed. Signed-off-by: Ben Skeggs Signed-off-by: Francisco Jerez --- drivers/gpu/drm/nouveau/nouveau_channel.c | 13 +- drivers/gpu/drm/nouveau/nouveau_dma.c | 4 +- drivers/gpu/drm/nouveau/nouveau_dma.h | 4 +- drivers/gpu/drm/nouveau/nouveau_drv.h | 19 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 479 ++++++++++-------------------- drivers/gpu/drm/nouveau/nouveau_state.c | 7 - include/drm/nouveau_drm.h | 86 ++---- 7 files changed, 208 insertions(+), 404 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c index ceb83961b16f..6dfb425cbae9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_channel.c +++ b/drivers/gpu/drm/nouveau/nouveau_channel.c @@ -385,6 +385,14 @@ nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, return ret; init->channel = chan->id; + if (chan->dma.ib_max) + init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM | + NOUVEAU_GEM_DOMAIN_GART; + else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM) + init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM; + else + init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART; + init->subchan[0].handle = NvM2MF; if (dev_priv->card_type < NV_50) init->subchan[0].grclass = 0x0039; @@ -424,7 +432,6 @@ nouveau_ioctl_fifo_free(struct drm_device *dev, void *data, ***********************************/ struct drm_ioctl_desc nouveau_ioctls[] = { - DRM_IOCTL_DEF(DRM_NOUVEAU_CARD_INIT, nouveau_ioctl_card_init, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH), @@ -434,13 +441,9 @@ struct drm_ioctl_desc nouveau_ioctls[] = { DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF_CALL, nouveau_gem_ioctl_pushbuf_call, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PIN, nouveau_gem_ioctl_pin, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_UNPIN, nouveau_gem_ioctl_unpin, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH), DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH), - DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF_CALL2, nouveau_gem_ioctl_pushbuf_call2, DRM_AUTH), }; int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls); diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c index 679b03c28df1..c8482a108a78 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.c +++ b/drivers/gpu/drm/nouveau/nouveau_dma.c @@ -179,7 +179,7 @@ READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout) void nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo, - int delta, int dwords) + int delta, int length) { struct nouveau_bo *pb = chan->pushbuf_bo; uint64_t offset = bo->bo.offset + delta; @@ -187,7 +187,7 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo, BUG_ON(chan->dma.ib_free < 1); nouveau_bo_wr32(pb, ip++, lower_32_bits(offset)); - nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | dwords << 10); + nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8); chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max; nvchan_wr32(chan, 0x8c, chan->dma.ib_put); diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index da6e16dafa4d..8b05c15866d5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -32,7 +32,7 @@ #endif void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *, - int delta, int dwords); + int delta, int length); /* * There's a hw race condition where you can't jump to your PUT offset, @@ -149,7 +149,7 @@ FIRE_RING(struct nouveau_channel *chan) if (chan->dma.ib_max) { nv50_dma_push(chan, chan->pushbuf_bo, chan->dma.put << 2, - chan->dma.cur - chan->dma.put); + (chan->dma.cur - chan->dma.put) << 2); } else { WRITE_PUT(chan->dma.cur); } diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index d221044e0793..a33423622860 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -34,7 +34,7 @@ #define DRIVER_MAJOR 0 #define DRIVER_MINOR 0 -#define DRIVER_PATCHLEVEL 15 +#define DRIVER_PATCHLEVEL 16 #define NOUVEAU_FAMILY 0x0000FFFF #define NOUVEAU_FLAGS 0xFFFF0000 @@ -83,6 +83,7 @@ struct nouveau_bo { struct drm_file *reserved_by; struct list_head entry; int pbbo_index; + bool validate_mapped; struct nouveau_channel *channel; @@ -704,12 +705,6 @@ extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, uint32_t reg, uint32_t mask, uint32_t val); extern bool nouveau_wait_for_idle(struct drm_device *); extern int nouveau_card_init(struct drm_device *); -extern int nouveau_ioctl_card_init(struct drm_device *, void *data, - struct drm_file *); -extern int nouveau_ioctl_suspend(struct drm_device *, void *data, - struct drm_file *); -extern int nouveau_ioctl_resume(struct drm_device *, void *data, - struct drm_file *); /* nouveau_mem.c */ extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start, @@ -1160,16 +1155,6 @@ extern int nouveau_gem_ioctl_new(struct drm_device *, void *, struct drm_file *); extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, struct drm_file *); -extern int nouveau_gem_ioctl_pushbuf_call(struct drm_device *, void *, - struct drm_file *); -extern int nouveau_gem_ioctl_pushbuf_call2(struct drm_device *, void *, - struct drm_file *); -extern int nouveau_gem_ioctl_pin(struct drm_device *, void *, - struct drm_file *); -extern int nouveau_gem_ioctl_unpin(struct drm_device *, void *, - struct drm_file *); -extern int nouveau_gem_ioctl_tile(struct drm_device *, void *, - struct drm_file *); extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, struct drm_file *); extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index df72cd847025..fee959c72f40 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -243,6 +243,11 @@ validate_fini_list(struct list_head *list, struct nouveau_fence *fence) nouveau_fence_unref((void *)&prev_fence); } + if (unlikely(nvbo->validate_mapped)) { + ttm_bo_kunmap(&nvbo->kmap); + nvbo->validate_mapped = false; + } + list_del(&nvbo->entry); nvbo->reserved_by = NULL; ttm_bo_unreserve(&nvbo->bo); @@ -302,11 +307,14 @@ retry: if (ret == -EAGAIN) ret = ttm_bo_wait_unreserved(&nvbo->bo, false); drm_gem_object_unreference(gem); - if (ret) + if (ret) { + NV_ERROR(dev, "fail reserve\n"); return ret; + } goto retry; } + b->user_priv = (uint64_t)(unsigned long)nvbo; nvbo->reserved_by = file_priv; nvbo->pbbo_index = i; if ((b->valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) && @@ -336,8 +344,10 @@ retry: } ret = ttm_bo_wait_cpu(&nvbo->bo, false); - if (ret) + if (ret) { + NV_ERROR(dev, "fail wait_cpu\n"); return ret; + } goto retry; } } @@ -351,6 +361,7 @@ validate_list(struct nouveau_channel *chan, struct list_head *list, { struct drm_nouveau_gem_pushbuf_bo __user *upbbo = (void __force __user *)(uintptr_t)user_pbbo_ptr; + struct drm_device *dev = chan->dev; struct nouveau_bo *nvbo; int ret, relocs = 0; @@ -362,39 +373,46 @@ validate_list(struct nouveau_channel *chan, struct list_head *list, spin_lock(&nvbo->bo.lock); ret = ttm_bo_wait(&nvbo->bo, false, false, false); spin_unlock(&nvbo->bo.lock); - if (unlikely(ret)) + if (unlikely(ret)) { + NV_ERROR(dev, "fail wait other chan\n"); return ret; + } } ret = nouveau_gem_set_domain(nvbo->gem, b->read_domains, b->write_domains, b->valid_domains); - if (unlikely(ret)) + if (unlikely(ret)) { + NV_ERROR(dev, "fail set_domain\n"); return ret; + } nvbo->channel = chan; ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, false, false); nvbo->channel = NULL; - if (unlikely(ret)) + if (unlikely(ret)) { + NV_ERROR(dev, "fail ttm_validate\n"); return ret; + } - if (nvbo->bo.offset == b->presumed_offset && + if (nvbo->bo.offset == b->presumed.offset && ((nvbo->bo.mem.mem_type == TTM_PL_VRAM && - b->presumed_domain & NOUVEAU_GEM_DOMAIN_VRAM) || + b->presumed.domain & NOUVEAU_GEM_DOMAIN_VRAM) || (nvbo->bo.mem.mem_type == TTM_PL_TT && - b->presumed_domain & NOUVEAU_GEM_DOMAIN_GART))) + b->presumed.domain & NOUVEAU_GEM_DOMAIN_GART))) continue; if (nvbo->bo.mem.mem_type == TTM_PL_TT) - b->presumed_domain = NOUVEAU_GEM_DOMAIN_GART; + b->presumed.domain = NOUVEAU_GEM_DOMAIN_GART; else - b->presumed_domain = NOUVEAU_GEM_DOMAIN_VRAM; - b->presumed_offset = nvbo->bo.offset; - b->presumed_ok = 0; + b->presumed.domain = NOUVEAU_GEM_DOMAIN_VRAM; + b->presumed.offset = nvbo->bo.offset; + b->presumed.valid = 0; relocs++; - if (DRM_COPY_TO_USER(&upbbo[nvbo->pbbo_index], b, sizeof(*b))) + if (DRM_COPY_TO_USER(&upbbo[nvbo->pbbo_index].presumed, + &b->presumed, sizeof(b->presumed))) return -EFAULT; } @@ -408,6 +426,7 @@ nouveau_gem_pushbuf_validate(struct nouveau_channel *chan, uint64_t user_buffers, int nr_buffers, struct validate_op *op, int *apply_relocs) { + struct drm_device *dev = chan->dev; int ret, relocs = 0; INIT_LIST_HEAD(&op->vram_list); @@ -418,11 +437,14 @@ nouveau_gem_pushbuf_validate(struct nouveau_channel *chan, return 0; ret = validate_init(chan, file_priv, pbbo, nr_buffers, op); - if (unlikely(ret)) + if (unlikely(ret)) { + NV_ERROR(dev, "validate_init\n"); return ret; + } ret = validate_list(chan, &op->vram_list, pbbo, user_buffers); if (unlikely(ret < 0)) { + NV_ERROR(dev, "validate vram_list\n"); validate_fini(op, NULL); return ret; } @@ -430,6 +452,7 @@ nouveau_gem_pushbuf_validate(struct nouveau_channel *chan, ret = validate_list(chan, &op->gart_list, pbbo, user_buffers); if (unlikely(ret < 0)) { + NV_ERROR(dev, "validate gart_list\n"); validate_fini(op, NULL); return ret; } @@ -437,6 +460,7 @@ nouveau_gem_pushbuf_validate(struct nouveau_channel *chan, ret = validate_list(chan, &op->both_list, pbbo, user_buffers); if (unlikely(ret < 0)) { + NV_ERROR(dev, "validate both_list\n"); validate_fini(op, NULL); return ret; } @@ -465,59 +489,82 @@ u_memcpya(uint64_t user, unsigned nmemb, unsigned size) } static int -nouveau_gem_pushbuf_reloc_apply(struct nouveau_channel *chan, int nr_bo, - struct drm_nouveau_gem_pushbuf_bo *bo, - unsigned nr_relocs, uint64_t ptr_relocs, - unsigned nr_dwords, unsigned first_dword, - uint32_t *pushbuf, bool is_iomem) +nouveau_gem_pushbuf_reloc_apply(struct drm_device *dev, + struct drm_nouveau_gem_pushbuf *req, + struct drm_nouveau_gem_pushbuf_bo *bo) { struct drm_nouveau_gem_pushbuf_reloc *reloc = NULL; - struct drm_device *dev = chan->dev; int ret = 0; unsigned i; - reloc = u_memcpya(ptr_relocs, nr_relocs, sizeof(*reloc)); + reloc = u_memcpya(req->relocs, req->nr_relocs, sizeof(*reloc)); if (IS_ERR(reloc)) return PTR_ERR(reloc); - for (i = 0; i < nr_relocs; i++) { + for (i = 0; i < req->nr_relocs; i++) { struct drm_nouveau_gem_pushbuf_reloc *r = &reloc[i]; struct drm_nouveau_gem_pushbuf_bo *b; + struct nouveau_bo *nvbo; uint32_t data; - if (r->bo_index >= nr_bo || r->reloc_index < first_dword || - r->reloc_index >= first_dword + nr_dwords) { - NV_ERROR(dev, "Bad relocation %d\n", i); - NV_ERROR(dev, " bo: %d max %d\n", r->bo_index, nr_bo); - NV_ERROR(dev, " id: %d max %d\n", r->reloc_index, nr_dwords); + if (unlikely(r->bo_index > req->nr_buffers)) { + NV_ERROR(dev, "reloc bo index invalid\n"); ret = -EINVAL; break; } b = &bo[r->bo_index]; - if (b->presumed_ok) + if (b->presumed.valid) continue; + if (unlikely(r->reloc_bo_index > req->nr_buffers)) { + NV_ERROR(dev, "reloc container bo index invalid\n"); + ret = -EINVAL; + break; + } + nvbo = (void *)(unsigned long)bo[r->reloc_bo_index].user_priv; + + if (unlikely(r->reloc_bo_offset + 4 > + nvbo->bo.mem.num_pages << PAGE_SHIFT)) { + NV_ERROR(dev, "reloc outside of bo\n"); + ret = -EINVAL; + break; + } + + if (!nvbo->kmap.virtual) { + ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, + &nvbo->kmap); + if (ret) { + NV_ERROR(dev, "failed kmap for reloc\n"); + break; + } + nvbo->validate_mapped = true; + } + if (r->flags & NOUVEAU_GEM_RELOC_LOW) - data = b->presumed_offset + r->data; + data = b->presumed.offset + r->data; else if (r->flags & NOUVEAU_GEM_RELOC_HIGH) - data = (b->presumed_offset + r->data) >> 32; + data = (b->presumed.offset + r->data) >> 32; else data = r->data; if (r->flags & NOUVEAU_GEM_RELOC_OR) { - if (b->presumed_domain == NOUVEAU_GEM_DOMAIN_GART) + if (b->presumed.domain == NOUVEAU_GEM_DOMAIN_GART) data |= r->tor; else data |= r->vor; } - if (is_iomem) - iowrite32_native(data, (void __force __iomem *) - &pushbuf[r->reloc_index]); - else - pushbuf[r->reloc_index] = data; + spin_lock(&nvbo->bo.lock); + ret = ttm_bo_wait(&nvbo->bo, false, false, false); + if (ret) { + NV_ERROR(dev, "reloc wait_idle failed: %d\n", ret); + break; + } + spin_unlock(&nvbo->bo.lock); + + nouveau_bo_wr32(nvbo, r->reloc_bo_offset >> 2, data); } kfree(reloc); @@ -528,125 +575,50 @@ int nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, struct drm_file *file_priv) { + struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_gem_pushbuf *req = data; - struct drm_nouveau_gem_pushbuf_bo *bo = NULL; + struct drm_nouveau_gem_pushbuf_push *push; + struct drm_nouveau_gem_pushbuf_bo *bo; struct nouveau_channel *chan; struct validate_op op; - struct nouveau_fence* fence = 0; - uint32_t *pushbuf = NULL; - int ret = 0, do_reloc = 0, i; + struct nouveau_fence *fence = 0; + int i, j, ret = 0, do_reloc = 0; NOUVEAU_CHECK_INITIALISED_WITH_RETURN; NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(req->channel, file_priv, chan); - if (req->nr_dwords >= chan->dma.max || - req->nr_buffers > NOUVEAU_GEM_MAX_BUFFERS || - req->nr_relocs > NOUVEAU_GEM_MAX_RELOCS) { - NV_ERROR(dev, "Pushbuf config exceeds limits:\n"); - NV_ERROR(dev, " dwords : %d max %d\n", req->nr_dwords, - chan->dma.max - 1); - NV_ERROR(dev, " buffers: %d max %d\n", req->nr_buffers, - NOUVEAU_GEM_MAX_BUFFERS); - NV_ERROR(dev, " relocs : %d max %d\n", req->nr_relocs, - NOUVEAU_GEM_MAX_RELOCS); - return -EINVAL; - } - - pushbuf = u_memcpya(req->dwords, req->nr_dwords, sizeof(uint32_t)); - if (IS_ERR(pushbuf)) - return PTR_ERR(pushbuf); - - bo = u_memcpya(req->buffers, req->nr_buffers, sizeof(*bo)); - if (IS_ERR(bo)) { - kfree(pushbuf); - return PTR_ERR(bo); - } - - mutex_lock(&dev->struct_mutex); - - /* Validate buffer list */ - ret = nouveau_gem_pushbuf_validate(chan, file_priv, bo, req->buffers, - req->nr_buffers, &op, &do_reloc); - if (ret) - goto out; - - /* Apply any relocations that are required */ - if (do_reloc) { - ret = nouveau_gem_pushbuf_reloc_apply(chan, req->nr_buffers, - bo, req->nr_relocs, - req->relocs, - req->nr_dwords, 0, - pushbuf, false); - if (ret) - goto out; - } - - /* Emit push buffer to the hw - */ - ret = RING_SPACE(chan, req->nr_dwords); - if (ret) - goto out; - - OUT_RINGp(chan, pushbuf, req->nr_dwords); + req->vram_available = dev_priv->fb_aper_free; + req->gart_available = dev_priv->gart_info.aper_free; + if (unlikely(req->nr_push == 0)) + goto out_next; - ret = nouveau_fence_new(chan, &fence, true); - if (ret) { - NV_ERROR(dev, "error fencing pushbuf: %d\n", ret); - WIND_RING(chan); - goto out; + if (unlikely(req->nr_push > NOUVEAU_GEM_MAX_PUSH)) { + NV_ERROR(dev, "pushbuf push count exceeds limit: %d max %d\n", + req->nr_push, NOUVEAU_GEM_MAX_PUSH); + return -EINVAL; } - if (nouveau_gem_pushbuf_sync(chan)) { - ret = nouveau_fence_wait(fence, NULL, false, false); - if (ret) { - for (i = 0; i < req->nr_dwords; i++) - NV_ERROR(dev, "0x%08x\n", pushbuf[i]); - NV_ERROR(dev, "^^ above push buffer is fail :(\n"); - } + if (unlikely(req->nr_buffers > NOUVEAU_GEM_MAX_BUFFERS)) { + NV_ERROR(dev, "pushbuf bo count exceeds limit: %d max %d\n", + req->nr_buffers, NOUVEAU_GEM_MAX_BUFFERS); + return -EINVAL; } -out: - validate_fini(&op, fence); - nouveau_fence_unref((void**)&fence); - mutex_unlock(&dev->struct_mutex); - kfree(pushbuf); - kfree(bo); - return ret; -} - -int -nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_gem_pushbuf_call *req = data; - struct drm_nouveau_gem_pushbuf_bo *bo = NULL; - struct nouveau_channel *chan; - struct drm_gem_object *gem; - struct nouveau_bo *pbbo; - struct validate_op op; - struct nouveau_fence* fence = 0; - int i, ret = 0, do_reloc = 0; - - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(req->channel, file_priv, chan); - - if (unlikely(req->handle == 0)) - goto out_next; - - if (req->nr_buffers > NOUVEAU_GEM_MAX_BUFFERS || - req->nr_relocs > NOUVEAU_GEM_MAX_RELOCS) { - NV_ERROR(dev, "Pushbuf config exceeds limits:\n"); - NV_ERROR(dev, " buffers: %d max %d\n", req->nr_buffers, - NOUVEAU_GEM_MAX_BUFFERS); - NV_ERROR(dev, " relocs : %d max %d\n", req->nr_relocs, - NOUVEAU_GEM_MAX_RELOCS); + if (unlikely(req->nr_relocs > NOUVEAU_GEM_MAX_RELOCS)) { + NV_ERROR(dev, "pushbuf reloc count exceeds limit: %d max %d\n", + req->nr_relocs, NOUVEAU_GEM_MAX_RELOCS); return -EINVAL; } + push = u_memcpya(req->push, req->nr_push, sizeof(*push)); + if (IS_ERR(push)) + return PTR_ERR(push); + bo = u_memcpya(req->buffers, req->nr_buffers, sizeof(*bo)); - if (IS_ERR(bo)) + if (IS_ERR(bo)) { + kfree(push); return PTR_ERR(bo); + } mutex_lock(&dev->struct_mutex); @@ -658,94 +630,9 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data, goto out; } - /* Validate DMA push buffer */ - gem = drm_gem_object_lookup(dev, file_priv, req->handle); - if (!gem) { - NV_ERROR(dev, "Unknown pb handle 0x%08x\n", req->handle); - ret = -EINVAL; - goto out; - } - pbbo = nouveau_gem_object(gem); - - if ((req->offset & 3) || req->nr_dwords < 2 || - (unsigned long)req->offset > (unsigned long)pbbo->bo.mem.size || - (unsigned long)req->nr_dwords > - ((unsigned long)(pbbo->bo.mem.size - req->offset ) >> 2)) { - NV_ERROR(dev, "pb call misaligned or out of bounds: " - "%d + %d * 4 > %ld\n", - req->offset, req->nr_dwords, pbbo->bo.mem.size); - ret = -EINVAL; - drm_gem_object_unreference(gem); - goto out; - } - - ret = ttm_bo_reserve(&pbbo->bo, false, false, true, - chan->fence.sequence); - if (ret) { - NV_ERROR(dev, "resv pb: %d\n", ret); - drm_gem_object_unreference(gem); - goto out; - } - - nouveau_bo_placement_set(pbbo, 1 << chan->pushbuf_bo->bo.mem.mem_type); - ret = ttm_bo_validate(&pbbo->bo, &pbbo->placement, false, false); - if (ret) { - NV_ERROR(dev, "validate pb: %d\n", ret); - ttm_bo_unreserve(&pbbo->bo); - drm_gem_object_unreference(gem); - goto out; - } - - list_add_tail(&pbbo->entry, &op.both_list); - - /* If presumed return address doesn't match, we need to map the - * push buffer and fix it.. - */ - if (dev_priv->card_type < NV_20) { - uint32_t retaddy; - - if (chan->dma.free < 4 + NOUVEAU_DMA_SKIPS) { - ret = nouveau_dma_wait(chan, 0, 4 + NOUVEAU_DMA_SKIPS); - if (ret) { - NV_ERROR(dev, "jmp_space: %d\n", ret); - goto out; - } - } - - retaddy = chan->pushbuf_base + ((chan->dma.cur + 2) << 2); - retaddy |= 0x20000000; - if (retaddy != req->suffix0) { - req->suffix0 = retaddy; - do_reloc = 1; - } - } - /* Apply any relocations that are required */ if (do_reloc) { - void *pbvirt; - bool is_iomem; - ret = ttm_bo_kmap(&pbbo->bo, 0, pbbo->bo.mem.num_pages, - &pbbo->kmap); - if (ret) { - NV_ERROR(dev, "kmap pb: %d\n", ret); - goto out; - } - - pbvirt = ttm_kmap_obj_virtual(&pbbo->kmap, &is_iomem); - ret = nouveau_gem_pushbuf_reloc_apply(chan, req->nr_buffers, bo, - req->nr_relocs, - req->relocs, - req->nr_dwords, - req->offset / 4, - pbvirt, is_iomem); - - if (dev_priv->card_type < NV_20) { - nouveau_bo_wr32(pbbo, - req->offset / 4 + req->nr_dwords - 2, - req->suffix0); - } - - ttm_bo_kunmap(&pbbo->kmap); + ret = nouveau_gem_pushbuf_reloc_apply(dev, req, bo); if (ret) { NV_ERROR(dev, "reloc apply: %d\n", ret); goto out; @@ -753,36 +640,74 @@ nouveau_gem_ioctl_pushbuf_call(struct drm_device *dev, void *data, } if (chan->dma.ib_max) { - ret = nouveau_dma_wait(chan, 2, 6); + ret = nouveau_dma_wait(chan, req->nr_push + 1, 6); if (ret) { NV_INFO(dev, "nv50cal_space: %d\n", ret); goto out; } - nv50_dma_push(chan, pbbo, req->offset, req->nr_dwords); + for (i = 0; i < req->nr_push; i++) { + struct nouveau_bo *nvbo = (void *)(unsigned long) + bo[push[i].bo_index].user_priv; + + nv50_dma_push(chan, nvbo, push[i].offset, + push[i].length); + } } else if (dev_priv->card_type >= NV_20) { - ret = RING_SPACE(chan, 2); + ret = RING_SPACE(chan, req->nr_push * 2); if (ret) { NV_ERROR(dev, "cal_space: %d\n", ret); goto out; } - OUT_RING(chan, ((pbbo->bo.mem.mm_node->start << PAGE_SHIFT) + - req->offset) | 2); - OUT_RING(chan, 0); + + for (i = 0; i < req->nr_push; i++) { + struct nouveau_bo *nvbo = (void *)(unsigned long) + bo[push[i].bo_index].user_priv; + struct drm_mm_node *mem = nvbo->bo.mem.mm_node; + + OUT_RING(chan, ((mem->start << PAGE_SHIFT) + + push[i].offset) | 2); + OUT_RING(chan, 0); + } } else { - ret = RING_SPACE(chan, 2 + NOUVEAU_DMA_SKIPS); + ret = RING_SPACE(chan, req->nr_push * (2 + NOUVEAU_DMA_SKIPS)); if (ret) { NV_ERROR(dev, "jmp_space: %d\n", ret); goto out; } - OUT_RING(chan, ((pbbo->bo.mem.mm_node->start << PAGE_SHIFT) + - req->offset) | 0x20000000); - OUT_RING(chan, 0); - /* Space the jumps apart with NOPs. */ - for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) + for (i = 0; i < req->nr_push; i++) { + struct nouveau_bo *nvbo = (void *)(unsigned long) + bo[push[i].bo_index].user_priv; + struct drm_mm_node *mem = nvbo->bo.mem.mm_node; + uint32_t cmd; + + cmd = chan->pushbuf_base + ((chan->dma.cur + 2) << 2); + cmd |= 0x20000000; + if (unlikely(cmd != req->suffix0)) { + if (!nvbo->kmap.virtual) { + ret = ttm_bo_kmap(&nvbo->bo, 0, + nvbo->bo.mem. + num_pages, + &nvbo->kmap); + if (ret) { + WIND_RING(chan); + goto out; + } + nvbo->validate_mapped = true; + } + + nouveau_bo_wr32(nvbo, (push[i].offset + + push[i].length - 8) / 4, cmd); + } + + OUT_RING(chan, ((mem->start << PAGE_SHIFT) + + push[i].offset) | 0x20000000); OUT_RING(chan, 0); + for (j = 0; j < NOUVEAU_DMA_SKIPS; j++) + OUT_RING(chan, 0); + } } ret = nouveau_fence_new(chan, &fence, true); @@ -797,6 +722,7 @@ out: nouveau_fence_unref((void**)&fence); mutex_unlock(&dev->struct_mutex); kfree(bo); + kfree(push); out_next: if (chan->dma.ib_max) { @@ -815,19 +741,6 @@ out_next: return ret; } -int -nouveau_gem_ioctl_pushbuf_call2(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct drm_nouveau_gem_pushbuf_call *req = data; - - req->vram_available = dev_priv->fb_aper_free; - req->gart_available = dev_priv->gart_info.aper_free; - - return nouveau_gem_ioctl_pushbuf_call(dev, data, file_priv); -} - static inline uint32_t domain_to_ttm(struct nouveau_bo *nvbo, uint32_t domain) { @@ -841,74 +754,6 @@ domain_to_ttm(struct nouveau_bo *nvbo, uint32_t domain) return flags; } -int -nouveau_gem_ioctl_pin(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_nouveau_gem_pin *req = data; - struct drm_gem_object *gem; - struct nouveau_bo *nvbo; - int ret = 0; - - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - - if (drm_core_check_feature(dev, DRIVER_MODESET)) { - NV_ERROR(dev, "pin only allowed without kernel modesetting\n"); - return -EINVAL; - } - - if (!DRM_SUSER(DRM_CURPROC)) - return -EPERM; - - gem = drm_gem_object_lookup(dev, file_priv, req->handle); - if (!gem) - return -EINVAL; - nvbo = nouveau_gem_object(gem); - - ret = nouveau_bo_pin(nvbo, domain_to_ttm(nvbo, req->domain)); - if (ret) - goto out; - - req->offset = nvbo->bo.offset; - if (nvbo->bo.mem.mem_type == TTM_PL_TT) - req->domain = NOUVEAU_GEM_DOMAIN_GART; - else - req->domain = NOUVEAU_GEM_DOMAIN_VRAM; - -out: - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gem); - mutex_unlock(&dev->struct_mutex); - - return ret; -} - -int -nouveau_gem_ioctl_unpin(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_nouveau_gem_pin *req = data; - struct drm_gem_object *gem; - int ret; - - NOUVEAU_CHECK_INITIALISED_WITH_RETURN; - - if (drm_core_check_feature(dev, DRIVER_MODESET)) - return -EINVAL; - - gem = drm_gem_object_lookup(dev, file_priv, req->handle); - if (!gem) - return -EINVAL; - - ret = nouveau_bo_unpin(nouveau_gem_object(gem)); - - mutex_lock(&dev->struct_mutex); - drm_gem_object_unreference(gem); - mutex_unlock(&dev->struct_mutex); - - return ret; -} - int nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data, struct drm_file *file_priv) diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index ed5ac0b9a0ac..516a8d36cb10 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c @@ -777,13 +777,6 @@ int nouveau_unload(struct drm_device *dev) return 0; } -int -nouveau_ioctl_card_init(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - return nouveau_card_init(dev); -} - int nouveau_ioctl_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) { diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h index f745948b61e4..a6a9f4af5ebd 100644 --- a/include/drm/nouveau_drm.h +++ b/include/drm/nouveau_drm.h @@ -25,13 +25,14 @@ #ifndef __NOUVEAU_DRM_H__ #define __NOUVEAU_DRM_H__ -#define NOUVEAU_DRM_HEADER_PATCHLEVEL 15 +#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16 struct drm_nouveau_channel_alloc { uint32_t fb_ctxdma_handle; uint32_t tt_ctxdma_handle; int channel; + uint32_t pushbuf_domains; /* Notifier memory */ uint32_t notifier_handle; @@ -109,68 +110,58 @@ struct drm_nouveau_gem_new { uint32_t align; }; +#define NOUVEAU_GEM_MAX_BUFFERS 1024 +struct drm_nouveau_gem_pushbuf_bo_presumed { + uint32_t valid; + uint32_t domain; + uint64_t offset; +}; + struct drm_nouveau_gem_pushbuf_bo { uint64_t user_priv; uint32_t handle; uint32_t read_domains; uint32_t write_domains; uint32_t valid_domains; - uint32_t presumed_ok; - uint32_t presumed_domain; - uint64_t presumed_offset; + struct drm_nouveau_gem_pushbuf_bo_presumed presumed; }; #define NOUVEAU_GEM_RELOC_LOW (1 << 0) #define NOUVEAU_GEM_RELOC_HIGH (1 << 1) #define NOUVEAU_GEM_RELOC_OR (1 << 2) +#define NOUVEAU_GEM_MAX_RELOCS 1024 struct drm_nouveau_gem_pushbuf_reloc { + uint32_t reloc_bo_index; + uint32_t reloc_bo_offset; uint32_t bo_index; - uint32_t reloc_index; uint32_t flags; uint32_t data; uint32_t vor; uint32_t tor; }; -#define NOUVEAU_GEM_MAX_BUFFERS 1024 -#define NOUVEAU_GEM_MAX_RELOCS 1024 +#define NOUVEAU_GEM_MAX_PUSH 512 +struct drm_nouveau_gem_pushbuf_push { + uint32_t bo_index; + uint32_t pad; + uint64_t offset; + uint64_t length; +}; struct drm_nouveau_gem_pushbuf { uint32_t channel; - uint32_t nr_dwords; uint32_t nr_buffers; - uint32_t nr_relocs; - uint64_t dwords; uint64_t buffers; - uint64_t relocs; -}; - -struct drm_nouveau_gem_pushbuf_call { - uint32_t channel; - uint32_t handle; - uint32_t offset; - uint32_t nr_buffers; uint32_t nr_relocs; - uint32_t nr_dwords; - uint64_t buffers; + uint32_t nr_push; uint64_t relocs; + uint64_t push; uint32_t suffix0; uint32_t suffix1; - /* below only accessed for CALL2 */ uint64_t vram_available; uint64_t gart_available; }; -struct drm_nouveau_gem_pin { - uint32_t handle; - uint32_t domain; - uint64_t offset; -}; - -struct drm_nouveau_gem_unpin { - uint32_t handle; -}; - #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 #define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 @@ -183,14 +174,6 @@ struct drm_nouveau_gem_cpu_fini { uint32_t handle; }; -struct drm_nouveau_gem_tile { - uint32_t handle; - uint32_t offset; - uint32_t size; - uint32_t tile_mode; - uint32_t tile_flags; -}; - enum nouveau_bus_type { NV_AGP = 0, NV_PCI = 1, @@ -200,22 +183,17 @@ enum nouveau_bus_type { struct drm_nouveau_sarea { }; -#define DRM_NOUVEAU_CARD_INIT 0x00 -#define DRM_NOUVEAU_GETPARAM 0x01 -#define DRM_NOUVEAU_SETPARAM 0x02 -#define DRM_NOUVEAU_CHANNEL_ALLOC 0x03 -#define DRM_NOUVEAU_CHANNEL_FREE 0x04 -#define DRM_NOUVEAU_GROBJ_ALLOC 0x05 -#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06 -#define DRM_NOUVEAU_GPUOBJ_FREE 0x07 +#define DRM_NOUVEAU_GETPARAM 0x00 +#define DRM_NOUVEAU_SETPARAM 0x01 +#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 +#define DRM_NOUVEAU_CHANNEL_FREE 0x03 +#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 +#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 +#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 #define DRM_NOUVEAU_GEM_NEW 0x40 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 -#define DRM_NOUVEAU_GEM_PUSHBUF_CALL 0x42 -#define DRM_NOUVEAU_GEM_PIN 0x43 /* !KMS only */ -#define DRM_NOUVEAU_GEM_UNPIN 0x44 /* !KMS only */ -#define DRM_NOUVEAU_GEM_CPU_PREP 0x45 -#define DRM_NOUVEAU_GEM_CPU_FINI 0x46 -#define DRM_NOUVEAU_GEM_INFO 0x47 -#define DRM_NOUVEAU_GEM_PUSHBUF_CALL2 0x48 +#define DRM_NOUVEAU_GEM_CPU_PREP 0x42 +#define DRM_NOUVEAU_GEM_CPU_FINI 0x43 +#define DRM_NOUVEAU_GEM_INFO 0x44 #endif /* __NOUVEAU_DRM_H__ */ -- cgit v1.2.3 From df31ef4dbd48eca2772d8d88b12ee5eb5117c86e Mon Sep 17 00:00:00 2001 From: Marcin Slusarz Date: Wed, 17 Feb 2010 19:04:00 +0100 Subject: drm/nouveau: fix pramdac_table range checking get_tmds_index_reg reads some value from stack when mlv happens to be equal to size of pramdac_table array. Fix it. Reported-by: Dan Carpenter Signed-off-by: Marcin Slusarz Signed-off-by: Francisco Jerez Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index 0e9cd1d49130..c1cee919b3cf 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -762,7 +762,7 @@ static uint32_t get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) dacoffset ^= 8; return 0x6808b0 + dacoffset; } else { - if (mlv > ARRAY_SIZE(pramdac_table)) { + if (mlv >= ARRAY_SIZE(pramdac_table)) { NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n", mlv); return 0; -- cgit v1.2.3 From b762b8ce53da7c7a7a4d660878887681c86be61b Mon Sep 17 00:00:00 2001 From: Marcin Slusarz Date: Wed, 17 Feb 2010 19:04:01 +0100 Subject: drm/nouveau: fix nouveau_i2c_find bounds checking Reported-by: Dan Carpenter Signed-off-by: Marcin Slusarz Signed-off-by: Francisco Jerez Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_i2c.c b/drivers/gpu/drm/nouveau/nouveau_i2c.c index 70e994d28122..f0162c4a6b90 100644 --- a/drivers/gpu/drm/nouveau/nouveau_i2c.c +++ b/drivers/gpu/drm/nouveau/nouveau_i2c.c @@ -256,7 +256,7 @@ nouveau_i2c_find(struct drm_device *dev, int index) struct drm_nouveau_private *dev_priv = dev->dev_private; struct nvbios *bios = &dev_priv->VBIOS; - if (index > DCB_MAX_NUM_I2C_ENTRIES) + if (index >= DCB_MAX_NUM_I2C_ENTRIES) return NULL; if (!bios->bdcb.dcb.i2c[index].chan) { -- cgit v1.2.3 From 761c5a69751967f4fe7430eb65b3a0ea92f3b673 Mon Sep 17 00:00:00 2001 From: Marcin Slusarz Date: Mon, 15 Feb 2010 23:24:49 +0100 Subject: drm/nouveau: fix i2ctable bounds checking i2c_entries seems to be the number of i2c entries, so with index equal to this number, we could read invalid data from i2ctable. Fix it. Signed-off-by: Marcin Slusarz Signed-off-by: Francisco Jerez Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bios.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index c1cee919b3cf..ef2fe964e9ab 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -4984,7 +4984,8 @@ read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, i else NV_WARN(dev, "DCB I2C table has more entries than indexable " - "(%d entries, max index 15)\n", i2ctable[2]); + "(%d entries, max %d)\n", i2ctable[2], + DCB_MAX_NUM_I2C_ENTRIES); entry_len = i2ctable[3]; /* [4] is i2c_default_indices, read in parse_dcb_table() */ } @@ -5000,8 +5001,8 @@ read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, i if (index == 0xf) return 0; - if (index > i2c_entries) { - NV_ERROR(dev, "DCB I2C index too big (%d > %d)\n", + if (index >= i2c_entries) { + NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n", index, i2ctable[2]); return -ENOENT; } -- cgit v1.2.3 From e32b2c883bfe9b57c660b5db31a62cea96c0c046 Mon Sep 17 00:00:00 2001 From: Luca Barbieri Date: Sat, 20 Feb 2010 11:08:56 +0100 Subject: drm/nouveau: fix missing spin_unlock in failure path Found by sparse. Signed-off-by: Luca Barbieri Signed-off-by: Francisco Jerez Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index fee959c72f40..8265fed528fd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -558,11 +558,11 @@ nouveau_gem_pushbuf_reloc_apply(struct drm_device *dev, spin_lock(&nvbo->bo.lock); ret = ttm_bo_wait(&nvbo->bo, false, false, false); + spin_unlock(&nvbo->bo.lock); if (ret) { NV_ERROR(dev, "reloc wait_idle failed: %d\n", ret); break; } - spin_unlock(&nvbo->bo.lock); nouveau_bo_wr32(nvbo, r->reloc_bo_offset >> 2, data); } -- cgit v1.2.3 From b42861f40f5ea3261d9fa1d5533496bf1fc812cf Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 23 Feb 2010 11:39:02 +1000 Subject: drm/nouveau: allow retrieval of vbios image from debugfs It's very useful to be able to access this without additional tools for debugging purposes. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_debugfs.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c index 89e36ee057c8..ac6af471649b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c +++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c @@ -144,9 +144,22 @@ nouveau_debugfs_memory_info(struct seq_file *m, void *data) return 0; } +static int +nouveau_debugfs_vbios_image(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_nouveau_private *dev_priv = node->minor->dev->dev_private; + int i; + + for (i = 0; i < dev_priv->VBIOS.length; i++) + seq_printf(m, "%c", dev_priv->VBIOS.data[i]); + return 0; +} + static struct drm_info_list nouveau_debugfs_list[] = { { "chipset", nouveau_debugfs_chipset_info, 0, NULL }, { "memory", nouveau_debugfs_memory_info, 0, NULL }, + { "vbios.rom", nouveau_debugfs_vbios_image, 0, NULL }, }; #define NOUVEAU_DEBUGFS_ENTRIES ARRAY_SIZE(nouveau_debugfs_list) -- cgit v1.2.3 From a6678b2ace023912000119a14eeb39a56050bc7c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 24 Feb 2010 09:46:27 +1000 Subject: drm/nouveau: rename parsed_dcb_gpio to dcb_gpio_table Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bios.c | 2 +- drivers/gpu/drm/nouveau/nouveau_bios.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index ef2fe964e9ab..ab0ec225140e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -5037,7 +5037,7 @@ read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, i static struct dcb_gpio_entry * new_gpio_entry(struct nvbios *bios) { - struct parsed_dcb_gpio *gpio = &bios->bdcb.gpio; + struct dcb_gpio_table *gpio = &bios->bdcb.gpio; return &gpio->entry[gpio->entries++]; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h index fd94bd6dc264..73e6499e79d7 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.h +++ b/drivers/gpu/drm/nouveau/nouveau_bios.h @@ -94,7 +94,7 @@ struct dcb_gpio_entry { bool invert; }; -struct parsed_dcb_gpio { +struct dcb_gpio_table { int entries; struct dcb_gpio_entry entry[DCB_MAX_NUM_GPIO_ENTRIES]; }; @@ -120,7 +120,7 @@ struct bios_parsed_dcb { uint8_t i2c_default_indices; uint16_t gpio_table_ptr; - struct parsed_dcb_gpio gpio; + struct dcb_gpio_table gpio; uint16_t connector_table_ptr; struct dcb_connector_table connector; }; -- cgit v1.2.3 From 7f245b20e30515264b94f6373ef7d721155990a4 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 24 Feb 2010 09:56:18 +1000 Subject: drm/nouveau: merge parsed_dcb and bios_parsed_dcb into dcb_table Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bios.c | 148 ++++++++++++++++----------------- drivers/gpu/drm/nouveau/nouveau_bios.h | 16 ++-- drivers/gpu/drm/nouveau/nouveau_i2c.c | 6 +- drivers/gpu/drm/nouveau/nv04_display.c | 2 +- drivers/gpu/drm/nouveau/nv04_tv.c | 2 +- drivers/gpu/drm/nouveau/nv50_display.c | 6 +- 6 files changed, 85 insertions(+), 95 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index ab0ec225140e..e3baa84df62c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -700,7 +700,7 @@ static int dcb_entry_idx_from_crtchead(struct drm_device *dev) uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0); - if (dcb_entry > bios->bdcb.dcb.entries) { + if (dcb_entry > bios->dcb.entries) { NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently " "(%02X)\n", dcb_entry); dcb_entry = 0x7f; /* unused / invalid marker */ @@ -713,25 +713,26 @@ static struct nouveau_i2c_chan * init_i2c_device_find(struct drm_device *dev, int i2c_index) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct bios_parsed_dcb *bdcb = &dev_priv->VBIOS.bdcb; + struct dcb_table *dcb = &dev_priv->VBIOS.dcb; if (i2c_index == 0xff) { /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ int idx = dcb_entry_idx_from_crtchead(dev), shift = 0; - int default_indices = bdcb->i2c_default_indices; + int default_indices = dcb->i2c_default_indices; - if (idx != 0x7f && bdcb->dcb.entry[idx].i2c_upper_default) + if (idx != 0x7f && dcb->entry[idx].i2c_upper_default) shift = 4; i2c_index = (default_indices >> shift) & 0xf; } if (i2c_index == 0x80) /* g80+ */ - i2c_index = bdcb->i2c_default_indices & 0xf; + i2c_index = dcb->i2c_default_indices & 0xf; return nouveau_i2c_find(dev, i2c_index); } -static uint32_t get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) +static uint32_t +get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) { /* * For mlv < 0x80, it is an index into a table of TMDS base addresses. @@ -744,6 +745,7 @@ static uint32_t get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) */ struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nvbios *bios = &dev_priv->VBIOS; const int pramdac_offset[13] = { 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; const uint32_t pramdac_table[4] = { @@ -756,8 +758,7 @@ static uint32_t get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) dcb_entry = dcb_entry_idx_from_crtchead(dev); if (dcb_entry == 0x7f) return 0; - dacoffset = pramdac_offset[ - dev_priv->VBIOS.bdcb.dcb.entry[dcb_entry].or]; + dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or]; if (mlv == 0x81) dacoffset ^= 8; return 0x6808b0 + dacoffset; @@ -2574,19 +2575,19 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; - const uint8_t *gpio_table = &bios->data[bios->bdcb.gpio_table_ptr]; + const uint8_t *gpio_table = &bios->data[bios->dcb.gpio_table_ptr]; const uint8_t *gpio_entry; int i; if (!iexec->execute) return 1; - if (bios->bdcb.version != 0x40) { + if (bios->dcb.version != 0x40) { NV_ERROR(bios->dev, "DCB table not version 4.0\n"); return 0; } - if (!bios->bdcb.gpio_table_ptr) { + if (!bios->dcb.gpio_table_ptr) { NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n"); return 0; } @@ -4796,10 +4797,10 @@ static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsi uint16_t legacy_scripts_offset, legacy_i2c_offset; /* load needed defaults in case we can't parse this info */ - bios->bdcb.dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX; - bios->bdcb.dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX; - bios->bdcb.dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX; - bios->bdcb.dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX; + bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX; + bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX; + bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX; + bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX; bios->pub.digital_min_front_porch = 0x4b; bios->fmaxvco = 256000; bios->fminvco = 128000; @@ -4907,10 +4908,10 @@ static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsi bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; - bios->bdcb.dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4]; - bios->bdcb.dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5]; - bios->bdcb.dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6]; - bios->bdcb.dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7]; + bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4]; + bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5]; + bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6]; + bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7]; if (bmplength > 74) { bios->fmaxvco = ROM32(bmp[67]); @@ -5037,7 +5038,7 @@ read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, i static struct dcb_gpio_entry * new_gpio_entry(struct nvbios *bios) { - struct dcb_gpio_table *gpio = &bios->bdcb.gpio; + struct dcb_gpio_table *gpio = &bios->dcb.gpio; return &gpio->entry[gpio->entries++]; } @@ -5049,11 +5050,11 @@ nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag) struct nvbios *bios = &dev_priv->VBIOS; int i; - for (i = 0; i < bios->bdcb.gpio.entries; i++) { - if (bios->bdcb.gpio.entry[i].tag != tag) + for (i = 0; i < bios->dcb.gpio.entries; i++) { + if (bios->dcb.gpio.entry[i].tag != tag) continue; - return &bios->bdcb.gpio.entry[i]; + return &bios->dcb.gpio.entry[i]; } return NULL; @@ -5101,7 +5102,7 @@ static void parse_dcb_gpio_table(struct nvbios *bios) { struct drm_device *dev = bios->dev; - uint16_t gpio_table_ptr = bios->bdcb.gpio_table_ptr; + uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr; uint8_t *gpio_table = &bios->data[gpio_table_ptr]; int header_len = gpio_table[1], entries = gpio_table[2], @@ -5109,7 +5110,7 @@ parse_dcb_gpio_table(struct nvbios *bios) void (*parse_entry)(struct nvbios *, uint16_t) = NULL; int i; - if (bios->bdcb.version >= 0x40) { + if (bios->dcb.version >= 0x40) { if (gpio_table_ptr && entry_len != 4) { NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); return; @@ -5117,7 +5118,7 @@ parse_dcb_gpio_table(struct nvbios *bios) parse_entry = parse_dcb40_gpio_entry; - } else if (bios->bdcb.version >= 0x30) { + } else if (bios->dcb.version >= 0x30) { if (gpio_table_ptr && entry_len != 2) { NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); return; @@ -5125,7 +5126,7 @@ parse_dcb_gpio_table(struct nvbios *bios) parse_entry = parse_dcb30_gpio_entry; - } else if (bios->bdcb.version >= 0x22) { + } else if (bios->dcb.version >= 0x22) { /* * DCBs older than v3.0 don't really have a GPIO * table, instead they keep some GPIO info at fixed @@ -5162,10 +5163,10 @@ nouveau_bios_connector_entry(struct drm_device *dev, int index) struct nvbios *bios = &dev_priv->VBIOS; struct dcb_connector_table_entry *cte; - if (index >= bios->bdcb.connector.entries) + if (index >= bios->dcb.connector.entries) return NULL; - cte = &bios->bdcb.connector.entry[index]; + cte = &bios->dcb.connector.entry[index]; if (cte->type == 0xff) return NULL; @@ -5176,13 +5177,13 @@ static void parse_dcb_connector_table(struct nvbios *bios) { struct drm_device *dev = bios->dev; - struct dcb_connector_table *ct = &bios->bdcb.connector; + struct dcb_connector_table *ct = &bios->dcb.connector; struct dcb_connector_table_entry *cte; - uint8_t *conntab = &bios->data[bios->bdcb.connector_table_ptr]; + uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr]; uint8_t *entry; int i; - if (!bios->bdcb.connector_table_ptr) { + if (!bios->dcb.connector_table_ptr) { NV_DEBUG_KMS(dev, "No DCB connector table present\n"); return; } @@ -5232,7 +5233,7 @@ parse_dcb_connector_table(struct nvbios *bios) } } -static struct dcb_entry *new_dcb_entry(struct parsed_dcb *dcb) +static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) { struct dcb_entry *entry = &dcb->entry[dcb->entries]; @@ -5242,7 +5243,7 @@ static struct dcb_entry *new_dcb_entry(struct parsed_dcb *dcb) return entry; } -static void fabricate_vga_output(struct parsed_dcb *dcb, int i2c, int heads) +static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads) { struct dcb_entry *entry = new_dcb_entry(dcb); @@ -5253,7 +5254,7 @@ static void fabricate_vga_output(struct parsed_dcb *dcb, int i2c, int heads) /* "or" mostly unused in early gen crt modesetting, 0 is fine */ } -static void fabricate_dvi_i_output(struct parsed_dcb *dcb, bool twoHeads) +static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads) { struct dcb_entry *entry = new_dcb_entry(dcb); @@ -5280,7 +5281,7 @@ static void fabricate_dvi_i_output(struct parsed_dcb *dcb, bool twoHeads) #endif } -static void fabricate_tv_output(struct parsed_dcb *dcb, bool twoHeads) +static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads) { struct dcb_entry *entry = new_dcb_entry(dcb); @@ -5291,13 +5292,13 @@ static void fabricate_tv_output(struct parsed_dcb *dcb, bool twoHeads) } static bool -parse_dcb20_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb, +parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, uint32_t conn, uint32_t conf, struct dcb_entry *entry) { entry->type = conn & 0xf; entry->i2c_index = (conn >> 4) & 0xf; entry->heads = (conn >> 8) & 0xf; - if (bdcb->version >= 0x40) + if (dcb->version >= 0x40) entry->connector = (conn >> 12) & 0xf; entry->bus = (conn >> 16) & 0xf; entry->location = (conn >> 20) & 0x3; @@ -5315,7 +5316,7 @@ parse_dcb20_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb, * Although the rest of a CRT conf dword is usually * zeros, mac biosen have stuff there so we must mask */ - entry->crtconf.maxfreq = (bdcb->version < 0x30) ? + entry->crtconf.maxfreq = (dcb->version < 0x30) ? (conf & 0xffff) * 10 : (conf & 0xff) * 10000; break; @@ -5324,7 +5325,7 @@ parse_dcb20_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb, uint32_t mask; if (conf & 0x1) entry->lvdsconf.use_straps_for_mode = true; - if (bdcb->version < 0x22) { + if (dcb->version < 0x22) { mask = ~0xd; /* * The laptop in bug 14567 lies and claims to not use @@ -5348,7 +5349,7 @@ parse_dcb20_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb, * Until we even try to use these on G8x, it's * useless reporting unknown bits. They all are. */ - if (bdcb->version >= 0x40) + if (dcb->version >= 0x40) break; NV_ERROR(dev, "Unknown LVDS configuration bits, " @@ -5358,7 +5359,7 @@ parse_dcb20_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb, } case OUTPUT_TV: { - if (bdcb->version >= 0x30) + if (dcb->version >= 0x30) entry->tvconf.has_component_output = conf & (0x8 << 4); else entry->tvconf.has_component_output = false; @@ -5385,7 +5386,7 @@ parse_dcb20_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb, break; case 0xe: /* weird g80 mobile type that "nv" treats as a terminator */ - bdcb->dcb.entries--; + dcb->entries--; return false; } @@ -5397,7 +5398,7 @@ parse_dcb20_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb, } static bool -parse_dcb15_entry(struct drm_device *dev, struct parsed_dcb *dcb, +parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, uint32_t conn, uint32_t conf, struct dcb_entry *entry) { switch (conn & 0x0000000f) { @@ -5463,27 +5464,27 @@ parse_dcb15_entry(struct drm_device *dev, struct parsed_dcb *dcb, return true; } -static bool parse_dcb_entry(struct drm_device *dev, struct bios_parsed_dcb *bdcb, +static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb, uint32_t conn, uint32_t conf) { - struct dcb_entry *entry = new_dcb_entry(&bdcb->dcb); + struct dcb_entry *entry = new_dcb_entry(dcb); bool ret; - if (bdcb->version >= 0x20) - ret = parse_dcb20_entry(dev, bdcb, conn, conf, entry); + if (dcb->version >= 0x20) + ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); else - ret = parse_dcb15_entry(dev, &bdcb->dcb, conn, conf, entry); + ret = parse_dcb15_entry(dev, dcb, conn, conf, entry); if (!ret) return ret; - read_dcb_i2c_entry(dev, bdcb->version, bdcb->i2c_table, - entry->i2c_index, &bdcb->dcb.i2c[entry->i2c_index]); + read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, + entry->i2c_index, &dcb->i2c[entry->i2c_index]); return true; } static -void merge_like_dcb_entries(struct drm_device *dev, struct parsed_dcb *dcb) +void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) { /* * DCB v2.0 lists each output combination separately. @@ -5535,8 +5536,7 @@ static int parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct bios_parsed_dcb *bdcb = &bios->bdcb; - struct parsed_dcb *dcb; + struct dcb_table *dcb = &bios->dcb; uint16_t dcbptr = 0, i2ctabptr = 0; uint8_t *dcbtable; uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES; @@ -5544,9 +5544,6 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) int recordlength = 8, confofs = 4; int i; - dcb = bios->pub.dcb = &bdcb->dcb; - dcb->entries = 0; - /* get the offset from 0x36 */ if (dev_priv->card_type > NV_04) { dcbptr = ROM16(bios->data[0x36]); @@ -5568,21 +5565,21 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) dcbtable = &bios->data[dcbptr]; /* get DCB version */ - bdcb->version = dcbtable[0]; + dcb->version = dcbtable[0]; NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n", - bdcb->version >> 4, bdcb->version & 0xf); + dcb->version >> 4, dcb->version & 0xf); - if (bdcb->version >= 0x20) { /* NV17+ */ + if (dcb->version >= 0x20) { /* NV17+ */ uint32_t sig; - if (bdcb->version >= 0x30) { /* NV40+ */ + if (dcb->version >= 0x30) { /* NV40+ */ headerlen = dcbtable[1]; entries = dcbtable[2]; recordlength = dcbtable[3]; i2ctabptr = ROM16(dcbtable[4]); sig = ROM32(dcbtable[6]); - bdcb->gpio_table_ptr = ROM16(dcbtable[10]); - bdcb->connector_table_ptr = ROM16(dcbtable[20]); + dcb->gpio_table_ptr = ROM16(dcbtable[10]); + dcb->connector_table_ptr = ROM16(dcbtable[20]); } else { i2ctabptr = ROM16(dcbtable[2]); sig = ROM32(dcbtable[4]); @@ -5594,7 +5591,7 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) "signature (%08X)\n", sig); return -EINVAL; } - } else if (bdcb->version >= 0x15) { /* some NV11 and NV20 */ + } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */ char sig[8] = { 0 }; strncpy(sig, (char *)&dcbtable[-7], 7); @@ -5642,9 +5639,9 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) if (!i2ctabptr) NV_WARN(dev, "No pointer to DCB I2C port table\n"); else { - bdcb->i2c_table = &bios->data[i2ctabptr]; - if (bdcb->version >= 0x30) - bdcb->i2c_default_indices = bdcb->i2c_table[4]; + dcb->i2c_table = &bios->data[i2ctabptr]; + if (dcb->version >= 0x30) + dcb->i2c_default_indices = dcb->i2c_table[4]; } parse_dcb_gpio_table(bios); @@ -5674,7 +5671,7 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n", dcb->entries, connection, config); - if (!parse_dcb_entry(dev, bdcb, connection, config)) + if (!parse_dcb_entry(dev, dcb, connection, config)) break; } @@ -5682,7 +5679,7 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) * apart for v2.1+ not being known for requiring merging, this * guarantees dcbent->index is the index of the entry in the rom image */ - if (bdcb->version < 0x21) + if (dcb->version < 0x21) merge_like_dcb_entries(dev, dcb); return dcb->entries ? 0 : -ENXIO; @@ -5691,8 +5688,7 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) static void fixup_legacy_connector(struct nvbios *bios) { - struct bios_parsed_dcb *bdcb = &bios->bdcb; - struct parsed_dcb *dcb = &bdcb->dcb; + struct dcb_table *dcb = &bios->dcb; int high = 0, i; /* @@ -5701,7 +5697,7 @@ fixup_legacy_connector(struct nvbios *bios) * indices are all 0. We don't need the connector indices on pre-G80 * chips (yet?) so limit the use to DCB 4.0 and above. */ - if (bdcb->version >= 0x40) + if (dcb->version >= 0x40) return; /* @@ -5741,7 +5737,7 @@ fixup_legacy_connector(struct nvbios *bios) static void fixup_legacy_i2c(struct nvbios *bios) { - struct parsed_dcb *dcb = &bios->bdcb.dcb; + struct dcb_table *dcb = &bios->dcb; int i; for (i = 0; i < dcb->entries; i++) { @@ -5947,9 +5943,9 @@ nouveau_run_vbios_init(struct drm_device *dev) } if (dev_priv->card_type >= NV_50) { - for (i = 0; i < bios->bdcb.dcb.entries; i++) { + for (i = 0; i < bios->dcb.entries; i++) { nouveau_bios_run_display_table(dev, - &bios->bdcb.dcb.entry[i], + &bios->dcb.entry[i], 0, 0); } } @@ -5967,7 +5963,7 @@ nouveau_bios_i2c_devices_takedown(struct drm_device *dev) struct dcb_i2c_entry *entry; int i; - entry = &bios->bdcb.dcb.i2c[0]; + entry = &bios->dcb.i2c[0]; for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++) nouveau_i2c_fini(dev, entry); } diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h index 73e6499e79d7..449a5f3d47d0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.h +++ b/drivers/gpu/drm/nouveau/nouveau_bios.h @@ -77,12 +77,6 @@ struct dcb_i2c_entry { struct nouveau_i2c_chan *chan; }; -struct parsed_dcb { - int entries; - struct dcb_entry entry[DCB_MAX_NUM_ENTRIES]; - struct dcb_i2c_entry i2c[DCB_MAX_NUM_I2C_ENTRIES]; -}; - enum dcb_gpio_tag { DCB_GPIO_TVDAC0 = 0xc, DCB_GPIO_TVDAC1 = 0x2d, @@ -111,13 +105,15 @@ struct dcb_connector_table { struct dcb_connector_table_entry entry[DCB_MAX_NUM_CONNECTOR_ENTRIES]; }; -struct bios_parsed_dcb { +struct dcb_table { uint8_t version; - struct parsed_dcb dcb; + int entries; + struct dcb_entry entry[DCB_MAX_NUM_ENTRIES]; uint8_t *i2c_table; uint8_t i2c_default_indices; + struct dcb_i2c_entry i2c[DCB_MAX_NUM_I2C_ENTRIES]; uint16_t gpio_table_ptr; struct dcb_gpio_table gpio; @@ -191,8 +187,6 @@ struct pll_lims { }; struct nouveau_bios_info { - struct parsed_dcb *dcb; - uint8_t chip_version; uint32_t dactestval; @@ -234,7 +228,7 @@ struct nvbios { uint16_t some_script_ptr; /* BIT I + 14 */ uint16_t init96_tbl_ptr; /* BIT I + 16 */ - struct bios_parsed_dcb bdcb; + struct dcb_table dcb; struct { int crtchead; diff --git a/drivers/gpu/drm/nouveau/nouveau_i2c.c b/drivers/gpu/drm/nouveau/nouveau_i2c.c index f0162c4a6b90..05fa4983c7fb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_i2c.c +++ b/drivers/gpu/drm/nouveau/nouveau_i2c.c @@ -259,11 +259,11 @@ nouveau_i2c_find(struct drm_device *dev, int index) if (index >= DCB_MAX_NUM_I2C_ENTRIES) return NULL; - if (!bios->bdcb.dcb.i2c[index].chan) { - if (nouveau_i2c_init(dev, &bios->bdcb.dcb.i2c[index], index)) + if (!bios->dcb.i2c[index].chan) { + if (nouveau_i2c_init(dev, &bios->dcb.i2c[index], index)) return NULL; } - return bios->bdcb.dcb.i2c[index].chan; + return bios->dcb.i2c[index].chan; } diff --git a/drivers/gpu/drm/nouveau/nv04_display.c b/drivers/gpu/drm/nouveau/nv04_display.c index ef77215fa5b9..07a8b5502b62 100644 --- a/drivers/gpu/drm/nouveau/nv04_display.c +++ b/drivers/gpu/drm/nouveau/nv04_display.c @@ -93,7 +93,7 @@ int nv04_display_create(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct parsed_dcb *dcb = dev_priv->vbios->dcb; + struct dcb_table *dcb = &dev_priv->VBIOS.dcb; struct drm_encoder *encoder; struct drm_crtc *crtc; uint16_t connector[16] = { 0 }; diff --git a/drivers/gpu/drm/nouveau/nv04_tv.c b/drivers/gpu/drm/nouveau/nv04_tv.c index 9c63099e9c42..ce247123cde1 100644 --- a/drivers/gpu/drm/nouveau/nv04_tv.c +++ b/drivers/gpu/drm/nouveau/nv04_tv.c @@ -262,7 +262,7 @@ int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry) nv_encoder->or = ffs(entry->or) - 1; /* Run the slave-specific initialization */ - adap = &dev_priv->vbios->dcb->i2c[i2c_index].chan->adapter; + adap = &dev_priv->VBIOS.dcb.i2c[i2c_index].chan->adapter; was_locked = NVLockVgaCrtcs(dev, false); diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 90f0bf59fbcd..34af3b277413 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -465,7 +465,7 @@ static int nv50_display_disable(struct drm_device *dev) int nv50_display_create(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct parsed_dcb *dcb = dev_priv->vbios->dcb; + struct dcb_table *dcb = &dev_priv->VBIOS.dcb; uint32_t connector[16] = {}; int ret, i; @@ -667,8 +667,8 @@ nv50_display_irq_head(struct drm_device *dev, int *phead, return -1; } - for (i = 0; i < dev_priv->vbios->dcb->entries; i++) { - struct dcb_entry *dcbent = &dev_priv->vbios->dcb->entry[i]; + for (i = 0; i < dev_priv->VBIOS.dcb.entries; i++) { + struct dcb_entry *dcbent = &dev_priv->VBIOS.dcb.entry[i]; if (dcbent->type != type) continue; -- cgit v1.2.3 From 04a39c577f4114a3f098ee8ef0e20f7778b5ddad Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 24 Feb 2010 10:03:05 +1000 Subject: drm/nouveau: merge nvbios and nouveau_bios_info Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bios.c | 82 ++++++++++++++--------------- drivers/gpu/drm/nouveau/nouveau_bios.h | 9 ++-- drivers/gpu/drm/nouveau/nouveau_calc.c | 4 +- drivers/gpu/drm/nouveau/nouveau_connector.c | 6 +-- drivers/gpu/drm/nouveau/nouveau_debugfs.c | 4 +- drivers/gpu/drm/nouveau/nouveau_drv.h | 3 +- drivers/gpu/drm/nouveau/nouveau_hw.c | 6 +-- drivers/gpu/drm/nouveau/nouveau_i2c.c | 2 +- drivers/gpu/drm/nouveau/nv04_dac.c | 8 +-- drivers/gpu/drm/nouveau/nv04_dfp.c | 4 +- drivers/gpu/drm/nouveau/nv04_display.c | 2 +- drivers/gpu/drm/nouveau/nv04_tv.c | 2 +- drivers/gpu/drm/nouveau/nv17_tv.c | 6 +-- drivers/gpu/drm/nouveau/nv50_dac.c | 4 +- drivers/gpu/drm/nouveau/nv50_display.c | 12 ++--- 15 files changed, 73 insertions(+), 81 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index e3baa84df62c..ea71ce4267e1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -311,11 +311,11 @@ valid_reg(struct nvbios *bios, uint32_t reg) /* C51 has misaligned regs on purpose. Marvellous */ if (reg & 0x2 || - (reg & 0x1 && dev_priv->VBIOS.pub.chip_version != 0x51)) + (reg & 0x1 && dev_priv->vbios.chip_version != 0x51)) NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg); /* warn on C51 regs that haven't been verified accessible in tracing */ - if (reg & 0x1 && dev_priv->VBIOS.pub.chip_version == 0x51 && + if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 && reg != 0x130d && reg != 0x1311 && reg != 0x60081d) NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", reg); @@ -420,7 +420,7 @@ bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data) LOG_OLD_VALUE(bios_rd32(bios, reg)); BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data); - if (dev_priv->VBIOS.execute) { + if (dev_priv->vbios.execute) { still_alive(); nv_wr32(bios->dev, reg, data); } @@ -647,7 +647,7 @@ nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16); reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1; - if (dev_priv->VBIOS.execute) { + if (dev_priv->vbios.execute) { still_alive(); nv_wr32(dev, reg + 4, reg1); nv_wr32(dev, reg + 0, reg0); @@ -689,7 +689,7 @@ setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk) static int dcb_entry_idx_from_crtchead(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; /* * For the results of this function to be correct, CR44 must have been @@ -713,7 +713,7 @@ static struct nouveau_i2c_chan * init_i2c_device_find(struct drm_device *dev, int i2c_index) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct dcb_table *dcb = &dev_priv->VBIOS.dcb; + struct dcb_table *dcb = &dev_priv->vbios.dcb; if (i2c_index == 0xff) { /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ @@ -745,7 +745,7 @@ get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) */ struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; const int pramdac_offset[13] = { 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; const uint32_t pramdac_table[4] = { @@ -3124,7 +3124,7 @@ run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, struct dcb_entry *dcbent, int head, bool dl) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; struct init_exec iexec = {true, false}; NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", @@ -3141,7 +3141,7 @@ run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0); uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); @@ -3195,7 +3195,7 @@ static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int * of a list of pxclks and script pointers. */ struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; unsigned int outputset = (dcbent->or == 4) ? 1 : 0; uint16_t scriptptr = 0, clktable; uint8_t clktableptr = 0; @@ -3262,7 +3262,7 @@ int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, */ struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; uint32_t sel_clk_binding, sel_clk; int ret; @@ -3396,7 +3396,7 @@ static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) #ifndef __powerpc__ NV_ERROR(dev, "Pointer to flat panel table invalid\n"); #endif - bios->pub.digital_min_front_porch = 0x4b; + bios->digital_min_front_porch = 0x4b; return 0; } @@ -3429,7 +3429,7 @@ static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) * fptable[4] is the minimum * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap */ - bios->pub.digital_min_front_porch = fptable[4]; + bios->digital_min_front_porch = fptable[4]; ofs = -7; break; default: @@ -3468,7 +3468,7 @@ static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ if (lth.lvds_ver > 0x10) - bios->pub.fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; + bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; /* * If either the strap or xlated fpindex value are 0xf there is no @@ -3492,7 +3492,7 @@ static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; if (!mode) /* just checking whether we can produce a mode */ @@ -3563,11 +3563,11 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b * until later, when this function should be called with non-zero pxclk */ struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; struct lvdstableheader lth; uint16_t lvdsofs; - int ret, chip_version = bios->pub.chip_version; + int ret, chip_version = bios->chip_version; ret = parse_lvds_manufacturer_table_header(dev, bios, <h); if (ret) @@ -3683,7 +3683,7 @@ bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent, uint16_t record, int record_len, int record_nr) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; uint32_t entry; uint16_t table; int i, v; @@ -3717,7 +3717,7 @@ nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent, int *length) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; uint8_t *table; if (!bios->display.dp_table_ptr) { @@ -3766,7 +3766,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, */ struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; uint8_t *table = &bios->data[bios->display.script_table_ptr]; uint8_t *otable = NULL; uint16_t script; @@ -3919,8 +3919,8 @@ int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, i */ struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; - int cv = bios->pub.chip_version; + struct nvbios *bios = &dev_priv->vbios; + int cv = bios->chip_version; uint16_t clktable = 0, scriptptr; uint32_t sel_clk_binding, sel_clk; @@ -3979,8 +3979,8 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims */ struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; - int cv = bios->pub.chip_version, pllindex = 0; + struct nvbios *bios = &dev_priv->vbios; + int cv = bios->chip_version, pllindex = 0; uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0; uint32_t crystal_strap_mask, crystal_straps; @@ -4333,7 +4333,7 @@ static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint */ bios->major_version = bios->data[offset + 3]; - bios->pub.chip_version = bios->data[offset + 2]; + bios->chip_version = bios->data[offset + 2]; NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n", bios->data[offset + 3], bios->data[offset + 2], bios->data[offset + 1], bios->data[offset]); @@ -4403,7 +4403,7 @@ static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, st } /* First entry is normal dac, 2nd tv-out perhaps? */ - bios->pub.dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; + bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; return 0; } @@ -4527,8 +4527,8 @@ static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, st return -ENOSYS; } - bios->pub.dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); - bios->pub.tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); + bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); + bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); return 0; } @@ -4801,7 +4801,7 @@ static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsi bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX; bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX; bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX; - bios->pub.digital_min_front_porch = 0x4b; + bios->digital_min_front_porch = 0x4b; bios->fmaxvco = 256000; bios->fminvco = 128000; bios->fp.duallink_transition_clk = 90000; @@ -5047,7 +5047,7 @@ struct dcb_gpio_entry * nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; int i; for (i = 0; i < bios->dcb.gpio.entries; i++) { @@ -5160,7 +5160,7 @@ struct dcb_connector_table_entry * nouveau_bios_connector_entry(struct drm_device *dev, int index) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; struct dcb_connector_table_entry *cte; if (index >= bios->dcb.connector.entries) @@ -5823,7 +5823,7 @@ static int load_nv17_hw_sequencer_ucode(struct drm_device *dev, uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; const uint8_t edid_sig[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; uint16_t offset = 0; @@ -5856,7 +5856,7 @@ nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, struct dcb_entry *dcbent) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; struct init_exec iexec = { true, false }; mutex_lock(&bios->lock); @@ -5869,7 +5869,7 @@ nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, static bool NVInitVBIOS(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; memset(bios, 0, sizeof(struct nvbios)); mutex_init(&bios->lock); @@ -5885,7 +5885,7 @@ static bool NVInitVBIOS(struct drm_device *dev) static int nouveau_parse_vbios_struct(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' }; const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 }; int offset; @@ -5912,7 +5912,7 @@ int nouveau_run_vbios_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; int i, ret = 0; NVLockVgaCrtcs(dev, false); @@ -5959,7 +5959,7 @@ static void nouveau_bios_i2c_devices_takedown(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; struct dcb_i2c_entry *entry; int i; @@ -5972,13 +5972,11 @@ int nouveau_bios_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; uint32_t saved_nv_pextdev_boot_0; bool was_locked; int ret; - dev_priv->vbios = &bios->pub; - if (!NVInitVBIOS(dev)) return -ENODEV; @@ -6020,10 +6018,8 @@ nouveau_bios_init(struct drm_device *dev) bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0); ret = nouveau_run_vbios_init(dev); - if (ret) { - dev_priv->vbios = NULL; + if (ret) return ret; - } /* feature_byte on BMP is poor, but init always sets CR4B */ was_locked = NVLockVgaCrtcs(dev, false); diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h index 449a5f3d47d0..38c856fae141 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.h +++ b/drivers/gpu/drm/nouveau/nouveau_bios.h @@ -186,18 +186,15 @@ struct pll_lims { int refclk; }; -struct nouveau_bios_info { +struct nvbios { + struct drm_device *dev; + uint8_t chip_version; uint32_t dactestval; uint32_t tvdactestval; uint8_t digital_min_front_porch; bool fp_no_ddc; -}; - -struct nvbios { - struct drm_device *dev; - struct nouveau_bios_info pub; struct mutex lock; diff --git a/drivers/gpu/drm/nouveau/nouveau_calc.c b/drivers/gpu/drm/nouveau/nouveau_calc.c index ee2b84504d05..88f9bc0941eb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_calc.c +++ b/drivers/gpu/drm/nouveau/nouveau_calc.c @@ -274,7 +274,7 @@ getMNP_single(struct drm_device *dev, struct pll_lims *pll_lim, int clk, * returns calculated clock */ struct drm_nouveau_private *dev_priv = dev->dev_private; - int cv = dev_priv->vbios->chip_version; + int cv = dev_priv->vbios.chip_version; int minvco = pll_lim->vco1.minfreq, maxvco = pll_lim->vco1.maxfreq; int minM = pll_lim->vco1.min_m, maxM = pll_lim->vco1.max_m; int minN = pll_lim->vco1.min_n, maxN = pll_lim->vco1.max_n; @@ -373,7 +373,7 @@ getMNP_double(struct drm_device *dev, struct pll_lims *pll_lim, int clk, * returns calculated clock */ struct drm_nouveau_private *dev_priv = dev->dev_private; - int chip_version = dev_priv->vbios->chip_version; + int chip_version = dev_priv->vbios.chip_version; int minvco1 = pll_lim->vco1.minfreq, maxvco1 = pll_lim->vco1.maxfreq; int minvco2 = pll_lim->vco2.minfreq, maxvco2 = pll_lim->vco2.maxfreq; int minU1 = pll_lim->vco1.min_inputfreq, minU2 = pll_lim->vco2.min_inputfreq; diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index d2f63353ea97..e73ce240c4b5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -680,7 +680,7 @@ nouveau_connector_create_lvds(struct drm_device *dev, /* Firstly try getting EDID over DDC, if allowed and I2C channel * is available. */ - if (!dev_priv->VBIOS.pub.fp_no_ddc && nv_encoder->dcb->i2c_index < 0xf) + if (!dev_priv->vbios.fp_no_ddc && nv_encoder->dcb->i2c_index < 0xf) i2c = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index); if (i2c) { @@ -695,7 +695,7 @@ nouveau_connector_create_lvds(struct drm_device *dev, */ if (!nv_connector->edid && nouveau_bios_fp_mode(dev, &native) && (nv_encoder->dcb->lvdsconf.use_straps_for_mode || - dev_priv->VBIOS.pub.fp_no_ddc)) { + dev_priv->vbios.fp_no_ddc)) { nv_connector->native_mode = drm_mode_duplicate(dev, &native); goto out; } @@ -704,7 +704,7 @@ nouveau_connector_create_lvds(struct drm_device *dev, * stored for the panel stored in them. */ if (!nv_connector->edid && !nv_connector->native_mode && - !dev_priv->VBIOS.pub.fp_no_ddc) { + !dev_priv->vbios.fp_no_ddc) { struct edid *edid = (struct edid *)nouveau_bios_embedded_edid(dev); if (edid) { diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c index ac6af471649b..8ff9ef5d4b47 100644 --- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c +++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c @@ -151,8 +151,8 @@ nouveau_debugfs_vbios_image(struct seq_file *m, void *data) struct drm_nouveau_private *dev_priv = node->minor->dev->dev_private; int i; - for (i = 0; i < dev_priv->VBIOS.length; i++) - seq_printf(m, "%c", dev_priv->VBIOS.data[i]); + for (i = 0; i < dev_priv->vbios.length; i++) + seq_printf(m, "%c", dev_priv->vbios.data[i]); return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index a33423622860..6fa9c87083c0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -605,8 +605,7 @@ struct drm_nouveau_private { struct list_head gpuobj_list; - struct nvbios VBIOS; - struct nouveau_bios_info *vbios; + struct nvbios vbios; struct nv04_mode_state mode_reg; struct nv04_mode_state saved_reg; diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c b/drivers/gpu/drm/nouveau/nouveau_hw.c index dc46792a5c96..7855b35effc3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_hw.c +++ b/drivers/gpu/drm/nouveau/nouveau_hw.c @@ -160,7 +160,7 @@ static void setPLL_single(struct drm_device *dev, uint32_t reg, struct nouveau_pll_vals *pv) { struct drm_nouveau_private *dev_priv = dev->dev_private; - int chip_version = dev_priv->vbios->chip_version; + int chip_version = dev_priv->vbios.chip_version; uint32_t oldpll = NVReadRAMDAC(dev, 0, reg); int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff; uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; @@ -216,7 +216,7 @@ setPLL_double_highregs(struct drm_device *dev, uint32_t reg1, struct nouveau_pll_vals *pv) { struct drm_nouveau_private *dev_priv = dev->dev_private; - int chip_version = dev_priv->vbios->chip_version; + int chip_version = dev_priv->vbios.chip_version; bool nv3035 = chip_version == 0x30 || chip_version == 0x35; uint32_t reg2 = reg1 + ((reg1 == NV_RAMDAC_VPLL2) ? 0x5c : 0x70); uint32_t oldpll1 = NVReadRAMDAC(dev, 0, reg1); @@ -374,7 +374,7 @@ nouveau_hw_setpll(struct drm_device *dev, uint32_t reg1, struct nouveau_pll_vals *pv) { struct drm_nouveau_private *dev_priv = dev->dev_private; - int cv = dev_priv->vbios->chip_version; + int cv = dev_priv->vbios.chip_version; if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || cv >= 0x40) { diff --git a/drivers/gpu/drm/nouveau/nouveau_i2c.c b/drivers/gpu/drm/nouveau/nouveau_i2c.c index 05fa4983c7fb..88583e7bf651 100644 --- a/drivers/gpu/drm/nouveau/nouveau_i2c.c +++ b/drivers/gpu/drm/nouveau/nouveau_i2c.c @@ -254,7 +254,7 @@ struct nouveau_i2c_chan * nouveau_i2c_find(struct drm_device *dev, int index) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; if (index >= DCB_MAX_NUM_I2C_ENTRIES) return NULL; diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c index 1d73b15d70da..1cb19e3acb55 100644 --- a/drivers/gpu/drm/nouveau/nv04_dac.c +++ b/drivers/gpu/drm/nouveau/nv04_dac.c @@ -230,13 +230,13 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) if (dcb->type == OUTPUT_TV) { testval = RGB_TEST_DATA(0xa0, 0xa0, 0xa0); - if (dev_priv->vbios->tvdactestval) - testval = dev_priv->vbios->tvdactestval; + if (dev_priv->vbios.tvdactestval) + testval = dev_priv->vbios.tvdactestval; } else { testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */ - if (dev_priv->vbios->dactestval) - testval = dev_priv->vbios->dactestval; + if (dev_priv->vbios.dactestval) + testval = dev_priv->vbios.dactestval; } saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c index 483f875bdb6a..41634d4752fe 100644 --- a/drivers/gpu/drm/nouveau/nv04_dfp.c +++ b/drivers/gpu/drm/nouveau/nv04_dfp.c @@ -269,10 +269,10 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder, regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; if (!nv_gf4_disp_arch(dev) || (output_mode->hsync_start - output_mode->hdisplay) >= - dev_priv->vbios->digital_min_front_porch) + dev_priv->vbios.digital_min_front_porch) regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay; else - regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios->digital_min_front_porch - 1; + regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios.digital_min_front_porch - 1; regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1; regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew; diff --git a/drivers/gpu/drm/nouveau/nv04_display.c b/drivers/gpu/drm/nouveau/nv04_display.c index 07a8b5502b62..76060f4423f4 100644 --- a/drivers/gpu/drm/nouveau/nv04_display.c +++ b/drivers/gpu/drm/nouveau/nv04_display.c @@ -93,7 +93,7 @@ int nv04_display_create(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct dcb_table *dcb = &dev_priv->VBIOS.dcb; + struct dcb_table *dcb = &dev_priv->vbios.dcb; struct drm_encoder *encoder; struct drm_crtc *crtc; uint16_t connector[16] = { 0 }; diff --git a/drivers/gpu/drm/nouveau/nv04_tv.c b/drivers/gpu/drm/nouveau/nv04_tv.c index ce247123cde1..c4e3404337d4 100644 --- a/drivers/gpu/drm/nouveau/nv04_tv.c +++ b/drivers/gpu/drm/nouveau/nv04_tv.c @@ -262,7 +262,7 @@ int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry) nv_encoder->or = ffs(entry->or) - 1; /* Run the slave-specific initialization */ - adap = &dev_priv->VBIOS.dcb.i2c[i2c_index].chan->adapter; + adap = &dev_priv->vbios.dcb.i2c[i2c_index].chan->adapter; was_locked = NVLockVgaCrtcs(dev, false); diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c index 21ac6e49b6ee..74c880374fb9 100644 --- a/drivers/gpu/drm/nouveau/nv17_tv.c +++ b/drivers/gpu/drm/nouveau/nv17_tv.c @@ -45,8 +45,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20) testval = RGB_TEST_DATA(0x82, 0xeb, 0x82); - if (dev_priv->vbios->tvdactestval) - testval = dev_priv->vbios->tvdactestval; + if (dev_priv->vbios.tvdactestval) + testval = dev_priv->vbios.tvdactestval; dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset); head = (dacclk & 0x100) >> 8; @@ -367,7 +367,7 @@ static void nv17_tv_prepare(struct drm_encoder *encoder) !enc->crtc && nv04_dfp_get_bound_head(dev, dcb) == head) { nv04_dfp_bind_head(dev, dcb, head ^ 1, - dev_priv->VBIOS.fp.dual_link); + dev_priv->vbios.fp.dual_link); } } diff --git a/drivers/gpu/drm/nouveau/nv50_dac.c b/drivers/gpu/drm/nouveau/nv50_dac.c index f08f042a8e10..1fd9537beff6 100644 --- a/drivers/gpu/drm/nouveau/nv50_dac.c +++ b/drivers/gpu/drm/nouveau/nv50_dac.c @@ -79,8 +79,8 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) } /* Use bios provided value if possible. */ - if (dev_priv->vbios->dactestval) { - load_pattern = dev_priv->vbios->dactestval; + if (dev_priv->vbios.dactestval) { + load_pattern = dev_priv->vbios.dactestval; NV_DEBUG_KMS(dev, "Using bios provided load_pattern of %d\n", load_pattern); } else { diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 34af3b277413..c406be6fdc5f 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -465,7 +465,7 @@ static int nv50_display_disable(struct drm_device *dev) int nv50_display_create(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; - struct dcb_table *dcb = &dev_priv->VBIOS.dcb; + struct dcb_table *dcb = &dev_priv->vbios.dcb; uint32_t connector[16] = {}; int ret, i; @@ -526,7 +526,7 @@ int nv50_display_create(struct drm_device *dev) connector[entry->connector] |= (1 << entry->type); } - /* It appears that DCB 3.0+ VBIOS has a connector table, however, + /* It appears that DCB 3.0+ vbios has a connector table, however, * I'm not 100% certain how to decode it correctly yet so just * look at what encoders are present on each connector index and * attempt to derive the connector type from that. @@ -667,8 +667,8 @@ nv50_display_irq_head(struct drm_device *dev, int *phead, return -1; } - for (i = 0; i < dev_priv->VBIOS.dcb.entries; i++) { - struct dcb_entry *dcbent = &dev_priv->VBIOS.dcb.entry[i]; + for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { + struct dcb_entry *dcbent = &dev_priv->vbios.dcb.entry[i]; if (dcbent->type != type) continue; @@ -692,7 +692,7 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent, struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_connector *nv_connector = NULL; struct drm_encoder *encoder; - struct nvbios *bios = &dev_priv->VBIOS; + struct nvbios *bios = &dev_priv->vbios; uint32_t mc, script = 0, or; list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { @@ -710,7 +710,7 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent, switch (dcbent->type) { case OUTPUT_LVDS: script = (mc >> 8) & 0xf; - if (bios->pub.fp_no_ddc) { + if (bios->fp_no_ddc) { if (bios->fp.dual_link) script |= 0x0100; if (bios->fp.if_is_24bit) -- cgit v1.2.3 From e7cc51c5652a8195bc638ce52987fb265ace2a9a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 24 Feb 2010 10:31:39 +1000 Subject: drm/nouveau: reorganise bios header, add dcb connector type enums Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bios.c | 2 + drivers/gpu/drm/nouveau/nouveau_bios.h | 102 ++++++++++++++++------------ drivers/gpu/drm/nouveau/nouveau_connector.c | 3 + 3 files changed, 63 insertions(+), 44 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index ea71ce4267e1..ca65a5b11fa8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -5388,6 +5388,8 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, /* weird g80 mobile type that "nv" treats as a terminator */ dcb->entries--; return false; + default: + break; } /* unsure what DCB version introduces this, 3.0? */ diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h index 38c856fae141..e3163f1123bd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.h +++ b/drivers/gpu/drm/nouveau/nouveau_bios.h @@ -34,9 +34,66 @@ #define DCB_LOC_ON_CHIP 0 +struct dcb_i2c_entry { + uint8_t port_type; + uint8_t read, write; + struct nouveau_i2c_chan *chan; +}; + +enum dcb_gpio_tag { + DCB_GPIO_TVDAC0 = 0xc, + DCB_GPIO_TVDAC1 = 0x2d, +}; + +struct dcb_gpio_entry { + enum dcb_gpio_tag tag; + int line; + bool invert; +}; + +struct dcb_gpio_table { + int entries; + struct dcb_gpio_entry entry[DCB_MAX_NUM_GPIO_ENTRIES]; +}; + +enum dcb_connector_type { + DCB_CONNECTOR_VGA = 0x00, + DCB_CONNECTOR_TV_0 = 0x10, + DCB_CONNECTOR_TV_1 = 0x11, + DCB_CONNECTOR_TV_3 = 0x13, + DCB_CONNECTOR_DVI_I = 0x30, + DCB_CONNECTOR_DVI_D = 0x31, + DCB_CONNECTOR_LVDS = 0x40, + DCB_CONNECTOR_DP = 0x46, + DCB_CONNECTOR_eDP = 0x47, + DCB_CONNECTOR_HDMI_0 = 0x60, + DCB_CONNECTOR_HDMI_1 = 0x61, +}; + +struct dcb_connector_table_entry { + uint32_t entry; + enum dcb_connector_type type; + uint8_t index; + uint8_t gpio_tag; +}; + +struct dcb_connector_table { + int entries; + struct dcb_connector_table_entry entry[DCB_MAX_NUM_CONNECTOR_ENTRIES]; +}; + +enum dcb_type { + OUTPUT_ANALOG = 0, + OUTPUT_TV = 1, + OUTPUT_TMDS = 2, + OUTPUT_LVDS = 3, + OUTPUT_DP = 6, + OUTPUT_ANY = -1 +}; + struct dcb_entry { int index; /* may not be raw dcb index if merging has happened */ - uint8_t type; + enum dcb_type type; uint8_t i2c_index; uint8_t heads; uint8_t connector; @@ -71,40 +128,6 @@ struct dcb_entry { bool i2c_upper_default; }; -struct dcb_i2c_entry { - uint8_t port_type; - uint8_t read, write; - struct nouveau_i2c_chan *chan; -}; - -enum dcb_gpio_tag { - DCB_GPIO_TVDAC0 = 0xc, - DCB_GPIO_TVDAC1 = 0x2d, -}; - -struct dcb_gpio_entry { - enum dcb_gpio_tag tag; - int line; - bool invert; -}; - -struct dcb_gpio_table { - int entries; - struct dcb_gpio_entry entry[DCB_MAX_NUM_GPIO_ENTRIES]; -}; - -struct dcb_connector_table_entry { - uint32_t entry; - uint8_t type; - uint8_t index; - uint8_t gpio_tag; -}; - -struct dcb_connector_table { - int entries; - struct dcb_connector_table_entry entry[DCB_MAX_NUM_CONNECTOR_ENTRIES]; -}; - struct dcb_table { uint8_t version; @@ -121,15 +144,6 @@ struct dcb_table { struct dcb_connector_table connector; }; -enum nouveau_encoder_type { - OUTPUT_ANALOG = 0, - OUTPUT_TV = 1, - OUTPUT_TMDS = 2, - OUTPUT_LVDS = 3, - OUTPUT_DP = 6, - OUTPUT_ANY = -1 -}; - enum nouveau_or { OUTPUT_A = (1 << 0), OUTPUT_B = (1 << 1), diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index e73ce240c4b5..36a9692c4654 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -613,6 +613,9 @@ nouveau_connector_mode_valid(struct drm_connector *connector, clock *= 3; break; + default: + BUG_ON(1); + return MODE_BAD; } if (clock < min_clock) -- cgit v1.2.3 From 54abb5ddae28f6e676f659902cfc8c3ce63b3e16 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 24 Feb 2010 10:48:16 +1000 Subject: drm/nouveau: parse dcb gpio/connector tables after encoders Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bios.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index ca65a5b11fa8..ea690a735325 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -5646,9 +5646,6 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) dcb->i2c_default_indices = dcb->i2c_table[4]; } - parse_dcb_gpio_table(bios); - parse_dcb_connector_table(bios); - if (entries > DCB_MAX_NUM_ENTRIES) entries = DCB_MAX_NUM_ENTRIES; @@ -5684,7 +5681,12 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) if (dcb->version < 0x21) merge_like_dcb_entries(dev, dcb); - return dcb->entries ? 0 : -ENXIO; + if (!dcb->entries) + return -ENXIO; + + parse_dcb_gpio_table(bios); + parse_dcb_connector_table(bios); + return 0; } static void -- cgit v1.2.3 From f66fa771d5046fd8c3e3c6f09407e9168e261b8d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 24 Feb 2010 11:09:20 +1000 Subject: drm/nouveau: check for known dcb connector types Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bios.c | 61 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/nouveau/nouveau_bios.h | 1 + 2 files changed, 62 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index ea690a735325..8dd97b28df36 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -5173,6 +5173,43 @@ nouveau_bios_connector_entry(struct drm_device *dev, int index) return cte; } +static enum dcb_connector_type +divine_connector_type(struct nvbios *bios, int index) +{ + struct dcb_table *dcb = &bios->dcb; + unsigned encoders = 0, type = DCB_CONNECTOR_NONE; + int i; + + for (i = 0; i < dcb->entries; i++) { + if (dcb->entry[i].connector == index) + encoders |= (1 << dcb->entry[i].type); + } + + if (encoders & (1 << OUTPUT_DP)) { + if (encoders & (1 << OUTPUT_TMDS)) + type = DCB_CONNECTOR_DP; + else + type = DCB_CONNECTOR_eDP; + } else + if (encoders & (1 << OUTPUT_TMDS)) { + if (encoders & (1 << OUTPUT_ANALOG)) + type = DCB_CONNECTOR_DVI_I; + else + type = DCB_CONNECTOR_DVI_D; + } else + if (encoders & (1 << OUTPUT_ANALOG)) { + type = DCB_CONNECTOR_VGA; + } else + if (encoders & (1 << OUTPUT_LVDS)) { + type = DCB_CONNECTOR_LVDS; + } else + if (encoders & (1 << OUTPUT_TV)) { + type = DCB_CONNECTOR_TV_0; + } + + return type; +} + static void parse_dcb_connector_table(struct nvbios *bios) { @@ -5205,6 +5242,7 @@ parse_dcb_connector_table(struct nvbios *bios) cte->entry = ROM16(entry[0]); else cte->entry = ROM32(entry[0]); + cte->type = (cte->entry & 0x000000ff) >> 0; cte->index = (cte->entry & 0x00000f00) >> 8; switch (cte->entry & 0x00033000) { @@ -5230,6 +5268,29 @@ parse_dcb_connector_table(struct nvbios *bios) NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n", i, cte->entry, cte->type, cte->index, cte->gpio_tag); + + /* check for known types, fallback to guessing the type + * from attached encoders if we hit an unknown. + */ + switch (cte->type) { + case DCB_CONNECTOR_VGA: + case DCB_CONNECTOR_TV_0: + case DCB_CONNECTOR_TV_1: + case DCB_CONNECTOR_TV_3: + case DCB_CONNECTOR_DVI_I: + case DCB_CONNECTOR_DVI_D: + case DCB_CONNECTOR_LVDS: + case DCB_CONNECTOR_DP: + case DCB_CONNECTOR_eDP: + case DCB_CONNECTOR_HDMI_0: + case DCB_CONNECTOR_HDMI_1: + break; + default: + cte->type = divine_connector_type(bios, cte->index); + NV_WARN(dev, "unknown type, using 0x%02x", cte->type); + break; + } + } } diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h index e3163f1123bd..9f688aa9a655 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.h +++ b/drivers/gpu/drm/nouveau/nouveau_bios.h @@ -68,6 +68,7 @@ enum dcb_connector_type { DCB_CONNECTOR_eDP = 0x47, DCB_CONNECTOR_HDMI_0 = 0x60, DCB_CONNECTOR_HDMI_1 = 0x61, + DCB_CONNECTOR_NONE = 0xff }; struct dcb_connector_table_entry { -- cgit v1.2.3 From dc5bc4ed3815dfec2f3ecfbf6f7983440040fe22 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 24 Feb 2010 11:53:59 +1000 Subject: drm/nouveau: construct a connector table for cards that lack a real one Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bios.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index 8dd97b28df36..bcf843f22b7d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -5754,7 +5754,7 @@ static void fixup_legacy_connector(struct nvbios *bios) { struct dcb_table *dcb = &bios->dcb; - int high = 0, i; + int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { }; /* * DCB 3.0 also has the table in most cases, but there are some cards @@ -5765,6 +5765,8 @@ fixup_legacy_connector(struct nvbios *bios) if (dcb->version >= 0x40) return; + dcb->connector.entries = 0; + /* * No known connector info before v3.0, so make it up. the rule here * is: anything on the same i2c bus is considered to be on the same @@ -5772,30 +5774,31 @@ fixup_legacy_connector(struct nvbios *bios) * its own unique connector index. */ for (i = 0; i < dcb->entries; i++) { - if (dcb->entry[i].i2c_index == 0xf) - continue; - /* * Ignore the I2C index for on-chip TV-out, as there * are cards with bogus values (nv31m in bug 23212), * and it's otherwise useless. */ if (dcb->entry[i].type == OUTPUT_TV && - dcb->entry[i].location == DCB_LOC_ON_CHIP) { + dcb->entry[i].location == DCB_LOC_ON_CHIP) dcb->entry[i].i2c_index = 0xf; + i2c = dcb->entry[i].i2c_index; + + if (i2c_conn[i2c]) { + dcb->entry[i].connector = i2c_conn[i2c] - 1; continue; } - dcb->entry[i].connector = dcb->entry[i].i2c_index; - if (dcb->entry[i].connector > high) - high = dcb->entry[i].connector; + dcb->entry[i].connector = dcb->connector.entries++; + if (i2c != 0xf) + i2c_conn[i2c] = dcb->connector.entries; } - for (i = 0; i < dcb->entries; i++) { - if (dcb->entry[i].i2c_index != 0xf) - continue; - - dcb->entry[i].connector = ++high; + /* Fake the connector table as well as just connector indices */ + for (i = 0; i < dcb->connector.entries; i++) { + dcb->connector.entry[i].index = i; + dcb->connector.entry[i].type = divine_connector_type(bios, i); + dcb->connector.entry[i].gpio_tag = 0xff; } } -- cgit v1.2.3 From 7f612d87f8b4b1ddbcee04264a93e5af7b9f21c7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 24 Feb 2010 12:07:31 +1000 Subject: drm/nouveau: use dcb connector table for creating drm connectors This makes this code common to both the nv04 and nv50 paths. For the moment, we keep the previous behaviour with HDMI/eDP connectors and report them as DVI-D/DP instead. This will be fixed once the rest of the code has been fixed to deal with those types. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_connector.c | 87 ++++++++++++++++++----------- drivers/gpu/drm/nouveau/nouveau_connector.h | 3 +- drivers/gpu/drm/nouveau/nv04_display.c | 47 +--------------- drivers/gpu/drm/nouveau/nv50_display.c | 40 ++----------- 4 files changed, 62 insertions(+), 115 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 36a9692c4654..9d118737f88f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -742,46 +742,60 @@ out: } int -nouveau_connector_create(struct drm_device *dev, int index, int type) +nouveau_connector_create(struct drm_device *dev, + struct dcb_connector_table_entry *dcb) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_connector *nv_connector = NULL; struct drm_connector *connector; struct drm_encoder *encoder; - int ret; + int ret, type; NV_DEBUG_KMS(dev, "\n"); - nv_connector = kzalloc(sizeof(*nv_connector), GFP_KERNEL); - if (!nv_connector) - return -ENOMEM; - nv_connector->dcb = nouveau_bios_connector_entry(dev, index); - connector = &nv_connector->base; - - switch (type) { - case DRM_MODE_CONNECTOR_VGA: + switch (dcb->type) { + case DCB_CONNECTOR_NONE: + return 0; + case DCB_CONNECTOR_VGA: NV_INFO(dev, "Detected a VGA connector\n"); + type = DRM_MODE_CONNECTOR_VGA; break; - case DRM_MODE_CONNECTOR_DVID: - NV_INFO(dev, "Detected a DVI-D connector\n"); + case DCB_CONNECTOR_TV_0: + case DCB_CONNECTOR_TV_1: + case DCB_CONNECTOR_TV_3: + NV_INFO(dev, "Detected a TV connector\n"); + type = DRM_MODE_CONNECTOR_TV; break; - case DRM_MODE_CONNECTOR_DVII: + case DCB_CONNECTOR_DVI_I: NV_INFO(dev, "Detected a DVI-I connector\n"); + type = DRM_MODE_CONNECTOR_DVII; break; - case DRM_MODE_CONNECTOR_LVDS: - NV_INFO(dev, "Detected a LVDS connector\n"); + case DCB_CONNECTOR_DVI_D: + case DCB_CONNECTOR_HDMI_0: + case DCB_CONNECTOR_HDMI_1: + NV_INFO(dev, "Detected a DVI-D connector\n"); + type = DRM_MODE_CONNECTOR_DVID; break; - case DRM_MODE_CONNECTOR_TV: - NV_INFO(dev, "Detected a TV connector\n"); + case DCB_CONNECTOR_LVDS: + NV_INFO(dev, "Detected a LVDS connector\n"); + type = DRM_MODE_CONNECTOR_LVDS; break; - case DRM_MODE_CONNECTOR_DisplayPort: + case DCB_CONNECTOR_DP: + case DCB_CONNECTOR_eDP: NV_INFO(dev, "Detected a DisplayPort connector\n"); + type = DRM_MODE_CONNECTOR_DisplayPort; break; default: - NV_ERROR(dev, "Unknown connector, this is not good.\n"); - break; + NV_ERROR(dev, "unknown connector type: 0x%02x!!\n", dcb->type); + return -EINVAL; } + nv_connector = kzalloc(sizeof(*nv_connector), GFP_KERNEL); + if (!nv_connector) + return -ENOMEM; + nv_connector->dcb = dcb; + connector = &nv_connector->base; + /* defaults, will get overridden in detect() */ connector->interlace_allowed = false; connector->doublescan_allowed = false; @@ -789,6 +803,26 @@ nouveau_connector_create(struct drm_device *dev, int index, int type) drm_connector_init(dev, connector, &nouveau_connector_funcs, type); drm_connector_helper_add(connector, &nouveau_connector_helper_funcs); + /* attach encoders */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); + + if (nv_encoder->dcb->connector != dcb->index) + continue; + + if (get_slave_funcs(nv_encoder)) + get_slave_funcs(nv_encoder)->create_resources(encoder, connector); + + drm_mode_connector_attach_encoder(connector, encoder); + } + + if (!connector->encoder_ids[0]) { + NV_WARN(dev, " no encoders, ignoring\n"); + drm_connector_cleanup(connector); + kfree(connector); + return 0; + } + /* Init DVI-I specific properties */ if (type == DRM_MODE_CONNECTOR_DVII) { drm_mode_create_dvi_i_properties(dev); @@ -822,19 +856,6 @@ nouveau_connector_create(struct drm_device *dev, int index, int type) } } - /* attach encoders */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); - - if (nv_encoder->dcb->connector != index) - continue; - - if (get_slave_funcs(nv_encoder)) - get_slave_funcs(nv_encoder)->create_resources(encoder, connector); - - drm_mode_connector_attach_encoder(connector, encoder); - } - drm_sysfs_connector_add(connector); if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h index 728b8090e5ff..4ef38abc2d9c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.h +++ b/drivers/gpu/drm/nouveau/nouveau_connector.h @@ -49,6 +49,7 @@ static inline struct nouveau_connector *nouveau_connector( return container_of(con, struct nouveau_connector, base); } -int nouveau_connector_create(struct drm_device *dev, int i2c_index, int type); +int nouveau_connector_create(struct drm_device *, + struct dcb_connector_table_entry *); #endif /* __NOUVEAU_CONNECTOR_H__ */ diff --git a/drivers/gpu/drm/nouveau/nv04_display.c b/drivers/gpu/drm/nouveau/nv04_display.c index 76060f4423f4..c7898b4f6dfb 100644 --- a/drivers/gpu/drm/nouveau/nv04_display.c +++ b/drivers/gpu/drm/nouveau/nv04_display.c @@ -96,7 +96,6 @@ nv04_display_create(struct drm_device *dev) struct dcb_table *dcb = &dev_priv->vbios.dcb; struct drm_encoder *encoder; struct drm_crtc *crtc; - uint16_t connector[16] = { 0 }; int i, ret; NV_DEBUG_KMS(dev, "\n"); @@ -154,52 +153,10 @@ nv04_display_create(struct drm_device *dev) if (ret) continue; - - connector[dcbent->connector] |= (1 << dcbent->type); } - for (i = 0; i < dcb->entries; i++) { - struct dcb_entry *dcbent = &dcb->entry[i]; - uint16_t encoders; - int type; - - encoders = connector[dcbent->connector]; - if (!(encoders & (1 << dcbent->type))) - continue; - connector[dcbent->connector] = 0; - - switch (dcbent->type) { - case OUTPUT_ANALOG: - if (!MULTIPLE_ENCODERS(encoders)) - type = DRM_MODE_CONNECTOR_VGA; - else - type = DRM_MODE_CONNECTOR_DVII; - break; - case OUTPUT_TMDS: - if (!MULTIPLE_ENCODERS(encoders)) - type = DRM_MODE_CONNECTOR_DVID; - else - type = DRM_MODE_CONNECTOR_DVII; - break; - case OUTPUT_LVDS: - type = DRM_MODE_CONNECTOR_LVDS; -#if 0 - /* don't create i2c adapter when lvds ddc not allowed */ - if (dcbent->lvdsconf.use_straps_for_mode || - dev_priv->vbios->fp_no_ddc) - i2c_index = 0xf; -#endif - break; - case OUTPUT_TV: - type = DRM_MODE_CONNECTOR_TV; - break; - default: - type = DRM_MODE_CONNECTOR_Unknown; - continue; - } - - nouveau_connector_create(dev, dcbent->connector, type); - } + for (i = 0; i < dcb->connector.entries; i++) + nouveau_connector_create(dev, &dcb->connector.entry[i]); /* Save previous state */ NVLockVgaCrtcs(dev, false); diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index c406be6fdc5f..ebcd8bf2406f 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -466,7 +466,6 @@ int nv50_display_create(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct dcb_table *dcb = &dev_priv->vbios.dcb; - uint32_t connector[16] = {}; int ret, i; NV_DEBUG_KMS(dev, "\n"); @@ -522,44 +521,13 @@ int nv50_display_create(struct drm_device *dev) NV_WARN(dev, "DCB encoder %d unknown\n", entry->type); continue; } - - connector[entry->connector] |= (1 << entry->type); } - /* It appears that DCB 3.0+ vbios has a connector table, however, - * I'm not 100% certain how to decode it correctly yet so just - * look at what encoders are present on each connector index and - * attempt to derive the connector type from that. - */ - for (i = 0 ; i < dcb->entries; i++) { - struct dcb_entry *entry = &dcb->entry[i]; - uint16_t encoders; - int type; - - encoders = connector[entry->connector]; - if (!(encoders & (1 << entry->type))) + for (i = 0 ; i < dcb->connector.entries; i++) { + if (i != 0 && dcb->connector.entry[i].index == + dcb->connector.entry[i - 1].index) continue; - connector[entry->connector] = 0; - - if (encoders & (1 << OUTPUT_DP)) { - type = DRM_MODE_CONNECTOR_DisplayPort; - } else if (encoders & (1 << OUTPUT_TMDS)) { - if (encoders & (1 << OUTPUT_ANALOG)) - type = DRM_MODE_CONNECTOR_DVII; - else - type = DRM_MODE_CONNECTOR_DVID; - } else if (encoders & (1 << OUTPUT_ANALOG)) { - type = DRM_MODE_CONNECTOR_VGA; - } else if (encoders & (1 << OUTPUT_LVDS)) { - type = DRM_MODE_CONNECTOR_LVDS; - } else { - type = DRM_MODE_CONNECTOR_Unknown; - } - - if (type == DRM_MODE_CONNECTOR_Unknown) - continue; - - nouveau_connector_create(dev, entry->connector, type); + nouveau_connector_create(dev, &dcb->connector.entry[i]); } ret = nv50_display_init(dev); -- cgit v1.2.3 From 1157563931dd773df2420b98eef61598205d39ec Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 24 Feb 2010 13:45:57 +1000 Subject: drm/nv50: enable hpd on any connector we know the gpio line for Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nv50_display.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index ebcd8bf2406f..61a89f2dc553 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -370,9 +370,7 @@ nv50_display_init(struct drm_device *dev) struct nouveau_connector *conn = nouveau_connector(connector); struct dcb_gpio_entry *gpio; - if (connector->connector_type != DRM_MODE_CONNECTOR_DVII && - connector->connector_type != DRM_MODE_CONNECTOR_DVID && - connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) + if (conn->dcb->gpio_tag == 0xff) continue; gpio = nouveau_bios_gpio_entry(dev, conn->dcb->gpio_tag); -- cgit v1.2.3 From be079e97b5a6a569ceff73731aa9433b6113cb87 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 24 Feb 2010 14:01:40 +1000 Subject: drm/nouveau: use dcb connector types throughout the driver Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_connector.c | 73 ++++++++++++++++------------- 1 file changed, 41 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 9d118737f88f..dee52c81b100 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -218,7 +218,7 @@ nouveau_connector_set_encoder(struct drm_connector *connector, connector->interlace_allowed = true; } - if (connector->connector_type == DRM_MODE_CONNECTOR_DVII) { + if (nv_connector->dcb->type == DCB_CONNECTOR_DVI_I) { drm_connector_property_set_value(connector, dev->mode_config.dvi_i_subconnector_property, nv_encoder->dcb->type == OUTPUT_TMDS ? @@ -236,7 +236,7 @@ nouveau_connector_detect(struct drm_connector *connector) struct nouveau_i2c_chan *i2c; int type, flags; - if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) + if (nv_connector->dcb->type == DCB_CONNECTOR_LVDS) nv_encoder = find_encoder_by_type(connector, OUTPUT_LVDS); if (nv_encoder && nv_connector->native_mode) { #ifdef CONFIG_ACPI @@ -279,7 +279,7 @@ nouveau_connector_detect(struct drm_connector *connector) * same i2c channel so the value returned from ddc_detect * isn't necessarily correct. */ - if (connector->connector_type == DRM_MODE_CONNECTOR_DVII) { + if (nv_connector->dcb->type == DCB_CONNECTOR_DVI_I) { if (nv_connector->edid->input & DRM_EDID_INPUT_DIGITAL) type = OUTPUT_TMDS; else @@ -321,11 +321,11 @@ detect_analog: static void nouveau_connector_force(struct drm_connector *connector) { - struct drm_device *dev = connector->dev; + struct nouveau_connector *nv_connector = nouveau_connector(connector); struct nouveau_encoder *nv_encoder; int type; - if (connector->connector_type == DRM_MODE_CONNECTOR_DVII) { + if (nv_connector->dcb->type == DCB_CONNECTOR_DVI_I) { if (connector->force == DRM_FORCE_ON_DIGITAL) type = OUTPUT_TMDS; else @@ -335,7 +335,7 @@ nouveau_connector_force(struct drm_connector *connector) nv_encoder = find_encoder_by_type(connector, type); if (!nv_encoder) { - NV_ERROR(dev, "can't find encoder to force %s on!\n", + NV_ERROR(connector->dev, "can't find encoder to force %s on!\n", drm_get_connector_name(connector)); connector->status = connector_status_disconnected; return; @@ -369,7 +369,7 @@ nouveau_connector_set_property(struct drm_connector *connector, } /* LVDS always needs gpu scaling */ - if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS && + if (nv_connector->dcb->type == DCB_CONNECTOR_LVDS && value == DRM_MODE_SCALE_NONE) return -EINVAL; @@ -535,7 +535,7 @@ nouveau_connector_get_modes(struct drm_connector *connector) /* If we're not LVDS, destroy the previous native mode, the attached * monitor could have changed. */ - if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS && + if (nv_connector->dcb->type != DCB_CONNECTOR_LVDS && nv_connector->native_mode) { drm_mode_destroy(dev, nv_connector->native_mode); nv_connector->native_mode = NULL; @@ -563,7 +563,7 @@ nouveau_connector_get_modes(struct drm_connector *connector) ret = get_slave_funcs(nv_encoder)-> get_modes(to_drm_encoder(nv_encoder), connector); - if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) + if (nv_encoder->dcb->type == OUTPUT_LVDS) ret += nouveau_connector_scaler_modes_add(connector); return ret; @@ -771,20 +771,26 @@ nouveau_connector_create(struct drm_device *dev, type = DRM_MODE_CONNECTOR_DVII; break; case DCB_CONNECTOR_DVI_D: - case DCB_CONNECTOR_HDMI_0: - case DCB_CONNECTOR_HDMI_1: NV_INFO(dev, "Detected a DVI-D connector\n"); type = DRM_MODE_CONNECTOR_DVID; break; + case DCB_CONNECTOR_HDMI_0: + case DCB_CONNECTOR_HDMI_1: + NV_INFO(dev, "Detected a HDMI connector\n"); + type = DRM_MODE_CONNECTOR_HDMIA; + break; case DCB_CONNECTOR_LVDS: NV_INFO(dev, "Detected a LVDS connector\n"); type = DRM_MODE_CONNECTOR_LVDS; break; case DCB_CONNECTOR_DP: - case DCB_CONNECTOR_eDP: NV_INFO(dev, "Detected a DisplayPort connector\n"); type = DRM_MODE_CONNECTOR_DisplayPort; break; + case DCB_CONNECTOR_eDP: + NV_INFO(dev, "Detected an eDP connector\n"); + type = DRM_MODE_CONNECTOR_eDP; + break; default: NV_ERROR(dev, "unknown connector type: 0x%02x!!\n", dcb->type); return -EINVAL; @@ -824,41 +830,44 @@ nouveau_connector_create(struct drm_device *dev, } /* Init DVI-I specific properties */ - if (type == DRM_MODE_CONNECTOR_DVII) { + if (dcb->type == DCB_CONNECTOR_DVI_I) { drm_mode_create_dvi_i_properties(dev); drm_connector_attach_property(connector, dev->mode_config.dvi_i_subconnector_property, 0); drm_connector_attach_property(connector, dev->mode_config.dvi_i_select_subconnector_property, 0); } - if (type != DRM_MODE_CONNECTOR_LVDS) + if (dcb->type != DCB_CONNECTOR_LVDS) nv_connector->use_dithering = false; - if (type == DRM_MODE_CONNECTOR_DVID || - type == DRM_MODE_CONNECTOR_DVII || - type == DRM_MODE_CONNECTOR_LVDS || - type == DRM_MODE_CONNECTOR_DisplayPort) { - nv_connector->scaling_mode = DRM_MODE_SCALE_FULLSCREEN; - - drm_connector_attach_property(connector, dev->mode_config.scaling_mode_property, - nv_connector->scaling_mode); - drm_connector_attach_property(connector, dev->mode_config.dithering_mode_property, - nv_connector->use_dithering ? DRM_MODE_DITHERING_ON - : DRM_MODE_DITHERING_OFF); - - } else { - nv_connector->scaling_mode = DRM_MODE_SCALE_NONE; - - if (type == DRM_MODE_CONNECTOR_VGA && - dev_priv->card_type >= NV_50) { + switch (dcb->type) { + case DCB_CONNECTOR_VGA: + if (dev_priv->card_type >= NV_50) { drm_connector_attach_property(connector, dev->mode_config.scaling_mode_property, nv_connector->scaling_mode); } + /* fall-through */ + case DCB_CONNECTOR_TV_0: + case DCB_CONNECTOR_TV_1: + case DCB_CONNECTOR_TV_3: + nv_connector->scaling_mode = DRM_MODE_SCALE_NONE; + break; + default: + nv_connector->scaling_mode = DRM_MODE_SCALE_FULLSCREEN; + + drm_connector_attach_property(connector, + dev->mode_config.scaling_mode_property, + nv_connector->scaling_mode); + drm_connector_attach_property(connector, + dev->mode_config.dithering_mode_property, + nv_connector->use_dithering ? + DRM_MODE_DITHERING_ON : DRM_MODE_DITHERING_OFF); + break; } drm_sysfs_connector_add(connector); - if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { + if (dcb->type == DCB_CONNECTOR_LVDS) { ret = nouveau_connector_create_lvds(dev, connector); if (ret) { connector->funcs->destroy(connector); -- cgit v1.2.3 From d5f3c90d4f3ad6b054f9855b7b69137b97bda131 Mon Sep 17 00:00:00 2001 From: Marcin KoÅ›cielnicki Date: Thu, 25 Feb 2010 00:54:02 +0000 Subject: drm/nv50: Implement ctxprog/state generation. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This removes dependence on external firmware for NV50 generation cards. If the generated ctxprogs don't work for you for some reason, please report it. Signed-off-by: Marcin KoÅ›cielnicki Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/Makefile | 2 +- drivers/gpu/drm/nouveau/nouveau_drv.h | 1 + drivers/gpu/drm/nouveau/nv50_graph.c | 74 +- drivers/gpu/drm/nouveau/nv50_grctx.c | 2367 +++++++++++++++++++++++++++++++++ 4 files changed, 2411 insertions(+), 33 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nv50_grctx.c (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index 48c290b5da8c..32db806f3b5a 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile @@ -16,7 +16,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o \ nv04_graph.o nv10_graph.o nv20_graph.o \ nv40_graph.o nv50_graph.o \ - nv40_grctx.o \ + nv40_grctx.o nv50_grctx.o \ nv04_instmem.o nv50_instmem.o \ nv50_crtc.o nv50_dac.o nv50_sor.o \ nv50_cursor.o nv50_display.o nv50_fbcon.o \ diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 6fa9c87083c0..2f8ce42f0725 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -1029,6 +1029,7 @@ extern void nv50_graph_destroy_context(struct nouveau_channel *); extern int nv50_graph_load_context(struct nouveau_channel *); extern int nv50_graph_unload_context(struct drm_device *); extern void nv50_graph_context_switch(struct drm_device *); +extern int nv50_grctx_init(struct nouveau_grctx *); /* nouveau_grctx.c */ extern int nouveau_grctx_prog_load(struct drm_device *); diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c index 6d504801b514..857a09671a39 100644 --- a/drivers/gpu/drm/nouveau/nv50_graph.c +++ b/drivers/gpu/drm/nouveau/nv50_graph.c @@ -28,30 +28,7 @@ #include "drm.h" #include "nouveau_drv.h" -MODULE_FIRMWARE("nouveau/nv50.ctxprog"); -MODULE_FIRMWARE("nouveau/nv50.ctxvals"); -MODULE_FIRMWARE("nouveau/nv84.ctxprog"); -MODULE_FIRMWARE("nouveau/nv84.ctxvals"); -MODULE_FIRMWARE("nouveau/nv86.ctxprog"); -MODULE_FIRMWARE("nouveau/nv86.ctxvals"); -MODULE_FIRMWARE("nouveau/nv92.ctxprog"); -MODULE_FIRMWARE("nouveau/nv92.ctxvals"); -MODULE_FIRMWARE("nouveau/nv94.ctxprog"); -MODULE_FIRMWARE("nouveau/nv94.ctxvals"); -MODULE_FIRMWARE("nouveau/nv96.ctxprog"); -MODULE_FIRMWARE("nouveau/nv96.ctxvals"); -MODULE_FIRMWARE("nouveau/nv98.ctxprog"); -MODULE_FIRMWARE("nouveau/nv98.ctxvals"); -MODULE_FIRMWARE("nouveau/nva0.ctxprog"); -MODULE_FIRMWARE("nouveau/nva0.ctxvals"); -MODULE_FIRMWARE("nouveau/nva5.ctxprog"); -MODULE_FIRMWARE("nouveau/nva5.ctxvals"); -MODULE_FIRMWARE("nouveau/nva8.ctxprog"); -MODULE_FIRMWARE("nouveau/nva8.ctxvals"); -MODULE_FIRMWARE("nouveau/nvaa.ctxprog"); -MODULE_FIRMWARE("nouveau/nvaa.ctxvals"); -MODULE_FIRMWARE("nouveau/nvac.ctxprog"); -MODULE_FIRMWARE("nouveau/nvac.ctxvals"); +#include "nouveau_grctx.h" #define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50) @@ -111,9 +88,34 @@ nv50_graph_init_ctxctl(struct drm_device *dev) NV_DEBUG(dev, "\n"); - nouveau_grctx_prog_load(dev); - if (!dev_priv->engine.graph.ctxprog) - dev_priv->engine.graph.accel_blocked = true; + if (nouveau_ctxfw) { + nouveau_grctx_prog_load(dev); + dev_priv->engine.graph.grctx_size = 0x70000; + } + if (!dev_priv->engine.graph.ctxprog) { + struct nouveau_grctx ctx = {}; + uint32_t *cp = kmalloc(512 * 4, GFP_KERNEL); + int i; + if (!cp) { + NV_ERROR(dev, "Couldn't alloc ctxprog! Disabling acceleration.\n"); + dev_priv->engine.graph.accel_blocked = true; + return 0; + } + ctx.dev = dev; + ctx.mode = NOUVEAU_GRCTX_PROG; + ctx.data = cp; + ctx.ctxprog_max = 512; + if (!nv50_grctx_init(&ctx)) { + dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4; + + nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); + for (i = 0; i < ctx.ctxprog_len; i++) + nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]); + } else { + dev_priv->engine.graph.accel_blocked = true; + } + kfree(cp); + } nv_wr32(dev, 0x400320, 4); nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0); @@ -193,13 +195,13 @@ nv50_graph_create_context(struct nouveau_channel *chan) struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; struct nouveau_gpuobj *ctx; - uint32_t grctx_size = 0x70000; + struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; int hdr, ret; NV_DEBUG(dev, "ch%d\n", chan->id); - ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, grctx_size, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC | + ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx); if (ret) return ret; @@ -209,7 +211,7 @@ nv50_graph_create_context(struct nouveau_channel *chan) dev_priv->engine.instmem.prepare_access(dev, true); nv_wo32(dev, ramin, (hdr + 0x00)/4, 0x00190002); nv_wo32(dev, ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance + - grctx_size - 1); + pgraph->grctx_size - 1); nv_wo32(dev, ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance); nv_wo32(dev, ramin, (hdr + 0x0c)/4, 0); nv_wo32(dev, ramin, (hdr + 0x10)/4, 0); @@ -217,7 +219,15 @@ nv50_graph_create_context(struct nouveau_channel *chan) dev_priv->engine.instmem.finish_access(dev); dev_priv->engine.instmem.prepare_access(dev, true); - nouveau_grctx_vals_load(dev, ctx); + if (!pgraph->ctxprog) { + struct nouveau_grctx ctx = {}; + ctx.dev = chan->dev; + ctx.mode = NOUVEAU_GRCTX_VALS; + ctx.data = chan->ramin_grctx->gpuobj; + nv50_grctx_init(&ctx); + } else { + nouveau_grctx_vals_load(dev, ctx); + } nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12); if ((dev_priv->chipset & 0xf0) == 0xa0) nv_wo32(dev, ctx, 0x00004/4, 0x00000000); diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c new file mode 100644 index 000000000000..d105fcd42ca0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nv50_grctx.c @@ -0,0 +1,2367 @@ +/* + * Copyright 2009 Marcin KoÅ›cielnicki + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#define CP_FLAG_CLEAR 0 +#define CP_FLAG_SET 1 +#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) +#define CP_FLAG_SWAP_DIRECTION_LOAD 0 +#define CP_FLAG_SWAP_DIRECTION_SAVE 1 +#define CP_FLAG_UNK01 ((0 * 32) + 1) +#define CP_FLAG_UNK01_CLEAR 0 +#define CP_FLAG_UNK01_SET 1 +#define CP_FLAG_UNK03 ((0 * 32) + 3) +#define CP_FLAG_UNK03_CLEAR 0 +#define CP_FLAG_UNK03_SET 1 +#define CP_FLAG_USER_SAVE ((0 * 32) + 5) +#define CP_FLAG_USER_SAVE_NOT_PENDING 0 +#define CP_FLAG_USER_SAVE_PENDING 1 +#define CP_FLAG_USER_LOAD ((0 * 32) + 6) +#define CP_FLAG_USER_LOAD_NOT_PENDING 0 +#define CP_FLAG_USER_LOAD_PENDING 1 +#define CP_FLAG_UNK0B ((0 * 32) + 0xb) +#define CP_FLAG_UNK0B_CLEAR 0 +#define CP_FLAG_UNK0B_SET 1 +#define CP_FLAG_UNK1D ((0 * 32) + 0x1d) +#define CP_FLAG_UNK1D_CLEAR 0 +#define CP_FLAG_UNK1D_SET 1 +#define CP_FLAG_UNK20 ((1 * 32) + 0) +#define CP_FLAG_UNK20_CLEAR 0 +#define CP_FLAG_UNK20_SET 1 +#define CP_FLAG_STATUS ((2 * 32) + 0) +#define CP_FLAG_STATUS_BUSY 0 +#define CP_FLAG_STATUS_IDLE 1 +#define CP_FLAG_AUTO_SAVE ((2 * 32) + 4) +#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 +#define CP_FLAG_AUTO_SAVE_PENDING 1 +#define CP_FLAG_AUTO_LOAD ((2 * 32) + 5) +#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 +#define CP_FLAG_AUTO_LOAD_PENDING 1 +#define CP_FLAG_XFER ((2 * 32) + 11) +#define CP_FLAG_XFER_IDLE 0 +#define CP_FLAG_XFER_BUSY 1 +#define CP_FLAG_NEWCTX ((2 * 32) + 12) +#define CP_FLAG_NEWCTX_BUSY 0 +#define CP_FLAG_NEWCTX_DONE 1 +#define CP_FLAG_ALWAYS ((2 * 32) + 13) +#define CP_FLAG_ALWAYS_FALSE 0 +#define CP_FLAG_ALWAYS_TRUE 1 + +#define CP_CTX 0x00100000 +#define CP_CTX_COUNT 0x000f0000 +#define CP_CTX_COUNT_SHIFT 16 +#define CP_CTX_REG 0x00003fff +#define CP_LOAD_SR 0x00200000 +#define CP_LOAD_SR_VALUE 0x000fffff +#define CP_BRA 0x00400000 +#define CP_BRA_IP 0x0001ff00 +#define CP_BRA_IP_SHIFT 8 +#define CP_BRA_IF_CLEAR 0x00000080 +#define CP_BRA_FLAG 0x0000007f +#define CP_WAIT 0x00500000 +#define CP_WAIT_SET 0x00000080 +#define CP_WAIT_FLAG 0x0000007f +#define CP_SET 0x00700000 +#define CP_SET_1 0x00000080 +#define CP_SET_FLAG 0x0000007f +#define CP_NEWCTX 0x00600004 +#define CP_NEXT_TO_SWAP 0x00600005 +#define CP_SET_CONTEXT_POINTER 0x00600006 +#define CP_SET_XFER_POINTER 0x00600007 +#define CP_ENABLE 0x00600009 +#define CP_END 0x0060000c +#define CP_NEXT_TO_CURRENT 0x0060000d +#define CP_DISABLE1 0x0090ffff +#define CP_DISABLE2 0x0091ffff +#define CP_XFER_1 0x008000ff +#define CP_XFER_2 0x008800ff +#define CP_SEEK_1 0x00c000ff +#define CP_SEEK_2 0x00c800ff + +#include "drmP.h" +#include "nouveau_drv.h" +#include "nouveau_grctx.h" + +/* + * This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's + * the GPU itself that does context-switching, but it needs a special + * microcode to do it. And it's the driver's task to supply this microcode, + * further known as ctxprog, as well as the initial context values, known + * as ctxvals. + * + * Without ctxprog, you cannot switch contexts. Not even in software, since + * the majority of context [xfer strands] isn't accessible directly. You're + * stuck with a single channel, and you also suffer all the problems resulting + * from missing ctxvals, since you cannot load them. + * + * Without ctxvals, you're stuck with PGRAPH's default context. It's enough to + * run 2d operations, but trying to utilise 3d or CUDA will just lock you up, + * since you don't have... some sort of needed setup. + * + * Nouveau will just disable acceleration if not given ctxprog + ctxvals, since + * it's too much hassle to handle no-ctxprog as a special case. + */ + +/* + * How ctxprogs work. + * + * The ctxprog is written in its own kind of microcode, with very small and + * crappy set of available commands. You upload it to a small [512 insns] + * area of memory on PGRAPH, and it'll be run when PFIFO wants PGRAPH to + * switch channel. or when the driver explicitely requests it. Stuff visible + * to ctxprog consists of: PGRAPH MMIO registers, PGRAPH context strands, + * the per-channel context save area in VRAM [known as ctxvals or grctx], + * 4 flags registers, a scratch register, two grctx pointers, plus many + * random poorly-understood details. + * + * When ctxprog runs, it's supposed to check what operations are asked of it, + * save old context if requested, optionally reset PGRAPH and switch to the + * new channel, and load the new context. Context consists of three major + * parts: subset of MMIO registers and two "xfer areas". + */ + +/* TODO: + * - document unimplemented bits compared to nvidia + * - NVAx: make a TP subroutine, use it. + * - use 0x4008fc instead of 0x1540? + */ + +enum cp_label { + cp_check_load = 1, + cp_setup_auto_load, + cp_setup_load, + cp_setup_save, + cp_swap_state, + cp_prepare_exit, + cp_exit, +}; + +static void nv50_graph_construct_mmio(struct nouveau_grctx *ctx); +static void nv50_graph_construct_xfer1(struct nouveau_grctx *ctx); +static void nv50_graph_construct_xfer2(struct nouveau_grctx *ctx); + +/* Main function: construct the ctxprog skeleton, call the other functions. */ + +int +nv50_grctx_init(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + + switch (dev_priv->chipset) { + case 0x50: + case 0x84: + case 0x86: + case 0x92: + case 0x94: + case 0x96: + case 0x98: + case 0xa0: + case 0xa5: + case 0xa8: + case 0xaa: + case 0xac: + break; + default: + NV_ERROR(ctx->dev, "I don't know how to make a ctxprog for " + "your NV%x card.\n", dev_priv->chipset); + NV_ERROR(ctx->dev, "Disabling acceleration. Please contact " + "the devs.\n"); + return -ENOSYS; + } + /* decide whether we're loading/unloading the context */ + cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); + cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); + + cp_name(ctx, cp_check_load); + cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); + cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); + cp_bra (ctx, ALWAYS, TRUE, cp_exit); + + /* setup for context load */ + cp_name(ctx, cp_setup_auto_load); + cp_out (ctx, CP_DISABLE1); + cp_out (ctx, CP_DISABLE2); + cp_out (ctx, CP_ENABLE); + cp_out (ctx, CP_NEXT_TO_SWAP); + cp_set (ctx, UNK01, SET); + cp_name(ctx, cp_setup_load); + cp_out (ctx, CP_NEWCTX); + cp_wait(ctx, NEWCTX, BUSY); + cp_set (ctx, UNK1D, CLEAR); + cp_set (ctx, SWAP_DIRECTION, LOAD); + cp_bra (ctx, UNK0B, SET, cp_prepare_exit); + cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); + + /* setup for context save */ + cp_name(ctx, cp_setup_save); + cp_set (ctx, UNK1D, SET); + cp_wait(ctx, STATUS, BUSY); + cp_set (ctx, UNK01, SET); + cp_set (ctx, SWAP_DIRECTION, SAVE); + + /* general PGRAPH state */ + cp_name(ctx, cp_swap_state); + cp_set (ctx, UNK03, SET); + cp_pos (ctx, 0x00004/4); + cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */ + cp_pos (ctx, 0x00100/4); + nv50_graph_construct_mmio(ctx); + nv50_graph_construct_xfer1(ctx); + nv50_graph_construct_xfer2(ctx); + + cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); + + cp_set (ctx, UNK20, SET); + cp_set (ctx, SWAP_DIRECTION, SAVE); /* no idea why this is needed, but fixes at least one lockup. */ + cp_lsr (ctx, ctx->ctxvals_base); + cp_out (ctx, CP_SET_XFER_POINTER); + cp_lsr (ctx, 4); + cp_out (ctx, CP_SEEK_1); + cp_out (ctx, CP_XFER_1); + cp_wait(ctx, XFER, BUSY); + + /* pre-exit state updates */ + cp_name(ctx, cp_prepare_exit); + cp_set (ctx, UNK01, CLEAR); + cp_set (ctx, UNK03, CLEAR); + cp_set (ctx, UNK1D, CLEAR); + + cp_bra (ctx, USER_SAVE, PENDING, cp_exit); + cp_out (ctx, CP_NEXT_TO_CURRENT); + + cp_name(ctx, cp_exit); + cp_set (ctx, USER_SAVE, NOT_PENDING); + cp_set (ctx, USER_LOAD, NOT_PENDING); + cp_out (ctx, CP_END); + ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */ + + return 0; +} + +/* + * Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which + * registers to save/restore and the default values for them. + */ + +static void +nv50_graph_construct_mmio(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + int i, j; + int offset, base; + uint32_t units = nv_rd32 (ctx->dev, 0x1540); + + /* 0800 */ + cp_ctx(ctx, 0x400808, 7); + gr_def(ctx, 0x400814, 0x00000030); + cp_ctx(ctx, 0x400834, 0x32); + if (dev_priv->chipset == 0x50) { + gr_def(ctx, 0x400834, 0xff400040); + gr_def(ctx, 0x400838, 0xfff00080); + gr_def(ctx, 0x40083c, 0xfff70090); + gr_def(ctx, 0x400840, 0xffe806a8); + } + gr_def(ctx, 0x400844, 0x00000002); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + gr_def(ctx, 0x400894, 0x00001000); + gr_def(ctx, 0x4008e8, 0x00000003); + gr_def(ctx, 0x4008ec, 0x00001000); + if (dev_priv->chipset == 0x50) + cp_ctx(ctx, 0x400908, 0xb); + else if (dev_priv->chipset < 0xa0) + cp_ctx(ctx, 0x400908, 0xc); + else + cp_ctx(ctx, 0x400908, 0xe); + + if (dev_priv->chipset >= 0xa0) + cp_ctx(ctx, 0x400b00, 0x1); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { + cp_ctx(ctx, 0x400b10, 0x1); + gr_def(ctx, 0x400b10, 0x0001629d); + cp_ctx(ctx, 0x400b20, 0x1); + gr_def(ctx, 0x400b20, 0x0001629d); + } + + /* 0C00 */ + cp_ctx(ctx, 0x400c08, 0x2); + gr_def(ctx, 0x400c08, 0x0000fe0c); + + /* 1000 */ + if (dev_priv->chipset < 0xa0) { + cp_ctx(ctx, 0x401008, 0x4); + gr_def(ctx, 0x401014, 0x00001000); + } else if (dev_priv->chipset == 0xa0 || dev_priv->chipset >= 0xaa) { + cp_ctx(ctx, 0x401008, 0x5); + gr_def(ctx, 0x401018, 0x00001000); + } else { + cp_ctx(ctx, 0x401008, 0x5); + gr_def(ctx, 0x401018, 0x00004000); + } + + /* 1400 */ + cp_ctx(ctx, 0x401400, 0x8); + cp_ctx(ctx, 0x401424, 0x3); + if (dev_priv->chipset == 0x50) + gr_def(ctx, 0x40142c, 0x0001fd87); + else + gr_def(ctx, 0x40142c, 0x00000187); + cp_ctx(ctx, 0x401540, 0x5); + gr_def(ctx, 0x401550, 0x00001018); + + /* 1800 */ + cp_ctx(ctx, 0x401814, 0x1); + gr_def(ctx, 0x401814, 0x000000ff); + if (dev_priv->chipset == 0x50) { + cp_ctx(ctx, 0x40181c, 0xe); + gr_def(ctx, 0x401850, 0x00000004); + } else if (dev_priv->chipset < 0xa0) { + cp_ctx(ctx, 0x40181c, 0xf); + gr_def(ctx, 0x401854, 0x00000004); + } else { + cp_ctx(ctx, 0x40181c, 0x13); + gr_def(ctx, 0x401864, 0x00000004); + } + + /* 1C00 */ + cp_ctx(ctx, 0x401c00, 0x1); + switch (dev_priv->chipset) { + case 0x50: + gr_def(ctx, 0x401c00, 0x0001005f); + break; + case 0x84: + case 0x86: + case 0x94: + gr_def(ctx, 0x401c00, 0x044d00df); + break; + case 0x92: + case 0x96: + case 0x98: + case 0xa0: + case 0xaa: + case 0xac: + gr_def(ctx, 0x401c00, 0x042500df); + break; + case 0xa5: + case 0xa8: + gr_def(ctx, 0x401c00, 0x142500df); + break; + } + + /* 2400 */ + cp_ctx(ctx, 0x402400, 0x1); + if (dev_priv->chipset == 0x50) + cp_ctx(ctx, 0x402408, 0x1); + else + cp_ctx(ctx, 0x402408, 0x2); + gr_def(ctx, 0x402408, 0x00000600); + + /* 2800 */ + cp_ctx(ctx, 0x402800, 0x1); + if (dev_priv->chipset == 0x50) + gr_def(ctx, 0x402800, 0x00000006); + + /* 2C00 */ + cp_ctx(ctx, 0x402c08, 0x6); + if (dev_priv->chipset != 0x50) + gr_def(ctx, 0x402c14, 0x01000000); + gr_def(ctx, 0x402c18, 0x000000ff); + if (dev_priv->chipset == 0x50) + cp_ctx(ctx, 0x402ca0, 0x1); + else + cp_ctx(ctx, 0x402ca0, 0x2); + if (dev_priv->chipset < 0xa0) + gr_def(ctx, 0x402ca0, 0x00000400); + else if (dev_priv->chipset == 0xa0 || dev_priv->chipset >= 0xaa) + gr_def(ctx, 0x402ca0, 0x00000800); + else + gr_def(ctx, 0x402ca0, 0x00000400); + cp_ctx(ctx, 0x402cac, 0x4); + + /* 3000 */ + cp_ctx(ctx, 0x403004, 0x1); + gr_def(ctx, 0x403004, 0x00000001); + + /* 3404 */ + if (dev_priv->chipset >= 0xa0) { + cp_ctx(ctx, 0x403404, 0x1); + gr_def(ctx, 0x403404, 0x00000001); + } + + /* 5000 */ + cp_ctx(ctx, 0x405000, 0x1); + switch (dev_priv->chipset) { + case 0x50: + gr_def(ctx, 0x405000, 0x00300080); + break; + case 0x84: + case 0xa0: + case 0xa5: + case 0xa8: + case 0xaa: + case 0xac: + gr_def(ctx, 0x405000, 0x000e0080); + break; + case 0x86: + case 0x92: + case 0x94: + case 0x96: + case 0x98: + gr_def(ctx, 0x405000, 0x00000080); + break; + } + cp_ctx(ctx, 0x405014, 0x1); + gr_def(ctx, 0x405014, 0x00000004); + cp_ctx(ctx, 0x40501c, 0x1); + cp_ctx(ctx, 0x405024, 0x1); + cp_ctx(ctx, 0x40502c, 0x1); + + /* 5400 or maybe 4800 */ + if (dev_priv->chipset == 0x50) { + offset = 0x405400; + cp_ctx(ctx, 0x405400, 0xea); + } else if (dev_priv->chipset < 0x94) { + offset = 0x405400; + cp_ctx(ctx, 0x405400, 0xcb); + } else if (dev_priv->chipset < 0xa0) { + offset = 0x405400; + cp_ctx(ctx, 0x405400, 0xcc); + } else if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { + offset = 0x404800; + cp_ctx(ctx, 0x404800, 0xda); + } else { + offset = 0x405400; + cp_ctx(ctx, 0x405400, 0xd4); + } + gr_def(ctx, offset + 0x0c, 0x00000002); + gr_def(ctx, offset + 0x10, 0x00000001); + if (dev_priv->chipset >= 0x94) + offset += 4; + gr_def(ctx, offset + 0x1c, 0x00000001); + gr_def(ctx, offset + 0x20, 0x00000100); + gr_def(ctx, offset + 0x38, 0x00000002); + gr_def(ctx, offset + 0x3c, 0x00000001); + gr_def(ctx, offset + 0x40, 0x00000001); + gr_def(ctx, offset + 0x50, 0x00000001); + gr_def(ctx, offset + 0x54, 0x003fffff); + gr_def(ctx, offset + 0x58, 0x00001fff); + gr_def(ctx, offset + 0x60, 0x00000001); + gr_def(ctx, offset + 0x64, 0x00000001); + gr_def(ctx, offset + 0x6c, 0x00000001); + gr_def(ctx, offset + 0x70, 0x00000001); + gr_def(ctx, offset + 0x74, 0x00000001); + gr_def(ctx, offset + 0x78, 0x00000004); + gr_def(ctx, offset + 0x7c, 0x00000001); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + offset += 4; + gr_def(ctx, offset + 0x80, 0x00000001); + gr_def(ctx, offset + 0x84, 0x00000001); + gr_def(ctx, offset + 0x88, 0x00000007); + gr_def(ctx, offset + 0x8c, 0x00000001); + gr_def(ctx, offset + 0x90, 0x00000007); + gr_def(ctx, offset + 0x94, 0x00000001); + gr_def(ctx, offset + 0x98, 0x00000001); + gr_def(ctx, offset + 0x9c, 0x00000001); + if (dev_priv->chipset == 0x50) { + gr_def(ctx, offset + 0xb0, 0x00000001); + gr_def(ctx, offset + 0xb4, 0x00000001); + gr_def(ctx, offset + 0xbc, 0x00000001); + gr_def(ctx, offset + 0xc0, 0x0000000a); + gr_def(ctx, offset + 0xd0, 0x00000040); + gr_def(ctx, offset + 0xd8, 0x00000002); + gr_def(ctx, offset + 0xdc, 0x00000100); + gr_def(ctx, offset + 0xe0, 0x00000001); + gr_def(ctx, offset + 0xe4, 0x00000100); + gr_def(ctx, offset + 0x100, 0x00000001); + gr_def(ctx, offset + 0x124, 0x00000004); + gr_def(ctx, offset + 0x13c, 0x00000001); + gr_def(ctx, offset + 0x140, 0x00000100); + gr_def(ctx, offset + 0x148, 0x00000001); + gr_def(ctx, offset + 0x154, 0x00000100); + gr_def(ctx, offset + 0x158, 0x00000001); + gr_def(ctx, offset + 0x15c, 0x00000100); + gr_def(ctx, offset + 0x164, 0x00000001); + gr_def(ctx, offset + 0x170, 0x00000100); + gr_def(ctx, offset + 0x174, 0x00000001); + gr_def(ctx, offset + 0x17c, 0x00000001); + gr_def(ctx, offset + 0x188, 0x00000002); + gr_def(ctx, offset + 0x190, 0x00000001); + gr_def(ctx, offset + 0x198, 0x00000001); + gr_def(ctx, offset + 0x1ac, 0x00000003); + offset += 0xd0; + } else { + gr_def(ctx, offset + 0xb0, 0x00000001); + gr_def(ctx, offset + 0xb4, 0x00000100); + gr_def(ctx, offset + 0xbc, 0x00000001); + gr_def(ctx, offset + 0xc8, 0x00000100); + gr_def(ctx, offset + 0xcc, 0x00000001); + gr_def(ctx, offset + 0xd0, 0x00000100); + gr_def(ctx, offset + 0xd8, 0x00000001); + gr_def(ctx, offset + 0xe4, 0x00000100); + } + gr_def(ctx, offset + 0xf8, 0x00000004); + gr_def(ctx, offset + 0xfc, 0x00000070); + gr_def(ctx, offset + 0x100, 0x00000080); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + offset += 4; + gr_def(ctx, offset + 0x114, 0x0000000c); + if (dev_priv->chipset == 0x50) + offset -= 4; + gr_def(ctx, offset + 0x11c, 0x00000008); + gr_def(ctx, offset + 0x120, 0x00000014); + if (dev_priv->chipset == 0x50) { + gr_def(ctx, offset + 0x124, 0x00000026); + offset -= 0x18; + } else { + gr_def(ctx, offset + 0x128, 0x00000029); + gr_def(ctx, offset + 0x12c, 0x00000027); + gr_def(ctx, offset + 0x130, 0x00000026); + gr_def(ctx, offset + 0x134, 0x00000008); + gr_def(ctx, offset + 0x138, 0x00000004); + gr_def(ctx, offset + 0x13c, 0x00000027); + } + gr_def(ctx, offset + 0x148, 0x00000001); + gr_def(ctx, offset + 0x14c, 0x00000002); + gr_def(ctx, offset + 0x150, 0x00000003); + gr_def(ctx, offset + 0x154, 0x00000004); + gr_def(ctx, offset + 0x158, 0x00000005); + gr_def(ctx, offset + 0x15c, 0x00000006); + gr_def(ctx, offset + 0x160, 0x00000007); + gr_def(ctx, offset + 0x164, 0x00000001); + gr_def(ctx, offset + 0x1a8, 0x000000cf); + if (dev_priv->chipset == 0x50) + offset -= 4; + gr_def(ctx, offset + 0x1d8, 0x00000080); + gr_def(ctx, offset + 0x1dc, 0x00000004); + gr_def(ctx, offset + 0x1e0, 0x00000004); + if (dev_priv->chipset == 0x50) + offset -= 4; + else + gr_def(ctx, offset + 0x1e4, 0x00000003); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { + gr_def(ctx, offset + 0x1ec, 0x00000003); + offset += 8; + } + gr_def(ctx, offset + 0x1e8, 0x00000001); + if (dev_priv->chipset == 0x50) + offset -= 4; + gr_def(ctx, offset + 0x1f4, 0x00000012); + gr_def(ctx, offset + 0x1f8, 0x00000010); + gr_def(ctx, offset + 0x1fc, 0x0000000c); + gr_def(ctx, offset + 0x200, 0x00000001); + gr_def(ctx, offset + 0x210, 0x00000004); + gr_def(ctx, offset + 0x214, 0x00000002); + gr_def(ctx, offset + 0x218, 0x00000004); + if (dev_priv->chipset >= 0xa0) + offset += 4; + gr_def(ctx, offset + 0x224, 0x003fffff); + gr_def(ctx, offset + 0x228, 0x00001fff); + if (dev_priv->chipset == 0x50) + offset -= 0x20; + else if (dev_priv->chipset >= 0xa0) { + gr_def(ctx, offset + 0x250, 0x00000001); + gr_def(ctx, offset + 0x254, 0x00000001); + gr_def(ctx, offset + 0x258, 0x00000002); + offset += 0x10; + } + gr_def(ctx, offset + 0x250, 0x00000004); + gr_def(ctx, offset + 0x254, 0x00000014); + gr_def(ctx, offset + 0x258, 0x00000001); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + offset += 4; + gr_def(ctx, offset + 0x264, 0x00000002); + if (dev_priv->chipset >= 0xa0) + offset += 8; + gr_def(ctx, offset + 0x270, 0x00000001); + gr_def(ctx, offset + 0x278, 0x00000002); + gr_def(ctx, offset + 0x27c, 0x00001000); + if (dev_priv->chipset == 0x50) + offset -= 0xc; + else { + gr_def(ctx, offset + 0x280, 0x00000e00); + gr_def(ctx, offset + 0x284, 0x00001000); + gr_def(ctx, offset + 0x288, 0x00001e00); + } + gr_def(ctx, offset + 0x290, 0x00000001); + gr_def(ctx, offset + 0x294, 0x00000001); + gr_def(ctx, offset + 0x298, 0x00000001); + gr_def(ctx, offset + 0x29c, 0x00000001); + gr_def(ctx, offset + 0x2a0, 0x00000001); + gr_def(ctx, offset + 0x2b0, 0x00000200); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { + gr_def(ctx, offset + 0x2b4, 0x00000200); + offset += 4; + } + if (dev_priv->chipset < 0xa0) { + gr_def(ctx, offset + 0x2b8, 0x00000001); + gr_def(ctx, offset + 0x2bc, 0x00000070); + gr_def(ctx, offset + 0x2c0, 0x00000080); + gr_def(ctx, offset + 0x2cc, 0x00000001); + gr_def(ctx, offset + 0x2d0, 0x00000070); + gr_def(ctx, offset + 0x2d4, 0x00000080); + } else { + gr_def(ctx, offset + 0x2b8, 0x00000001); + gr_def(ctx, offset + 0x2bc, 0x000000f0); + gr_def(ctx, offset + 0x2c0, 0x000000ff); + gr_def(ctx, offset + 0x2cc, 0x00000001); + gr_def(ctx, offset + 0x2d0, 0x000000f0); + gr_def(ctx, offset + 0x2d4, 0x000000ff); + gr_def(ctx, offset + 0x2dc, 0x00000009); + offset += 4; + } + gr_def(ctx, offset + 0x2e4, 0x00000001); + gr_def(ctx, offset + 0x2e8, 0x000000cf); + gr_def(ctx, offset + 0x2f0, 0x00000001); + gr_def(ctx, offset + 0x300, 0x000000cf); + gr_def(ctx, offset + 0x308, 0x00000002); + gr_def(ctx, offset + 0x310, 0x00000001); + gr_def(ctx, offset + 0x318, 0x00000001); + gr_def(ctx, offset + 0x320, 0x000000cf); + gr_def(ctx, offset + 0x324, 0x000000cf); + gr_def(ctx, offset + 0x328, 0x00000001); + + /* 6000? */ + if (dev_priv->chipset == 0x50) + cp_ctx(ctx, 0x4063e0, 0x1); + + /* 6800 */ + if (dev_priv->chipset < 0x90) { + cp_ctx(ctx, 0x406814, 0x2b); + gr_def(ctx, 0x406818, 0x00000f80); + gr_def(ctx, 0x406860, 0x007f0080); + gr_def(ctx, 0x40689c, 0x007f0080); + } else { + cp_ctx(ctx, 0x406814, 0x4); + if (dev_priv->chipset == 0x98) + gr_def(ctx, 0x406818, 0x00000f80); + else + gr_def(ctx, 0x406818, 0x00001f80); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + gr_def(ctx, 0x40681c, 0x00000030); + cp_ctx(ctx, 0x406830, 0x3); + } + + /* 7000: per-ROP group state */ + for (i = 0; i < 8; i++) { + if (units & (1<<(i+16))) { + cp_ctx(ctx, 0x407000 + (i<<8), 3); + if (dev_priv->chipset == 0x50) + gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820); + else if (dev_priv->chipset != 0xa5) + gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821); + else + gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821); + gr_def(ctx, 0x407004 + (i<<8), 0x89058001); + + if (dev_priv->chipset == 0x50) { + cp_ctx(ctx, 0x407010 + (i<<8), 1); + } else if (dev_priv->chipset < 0xa0) { + cp_ctx(ctx, 0x407010 + (i<<8), 2); + gr_def(ctx, 0x407010 + (i<<8), 0x00001000); + gr_def(ctx, 0x407014 + (i<<8), 0x0000001f); + } else { + cp_ctx(ctx, 0x407010 + (i<<8), 3); + gr_def(ctx, 0x407010 + (i<<8), 0x00001000); + if (dev_priv->chipset != 0xa5) + gr_def(ctx, 0x407014 + (i<<8), 0x000000ff); + else + gr_def(ctx, 0x407014 + (i<<8), 0x000001ff); + } + + cp_ctx(ctx, 0x407080 + (i<<8), 4); + if (dev_priv->chipset != 0xa5) + gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa); + else + gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa); + if (dev_priv->chipset == 0x50) + gr_def(ctx, 0x407084 + (i<<8), 0x000000c0); + else + gr_def(ctx, 0x407084 + (i<<8), 0x400000c0); + gr_def(ctx, 0x407088 + (i<<8), 0xb7892080); + + if (dev_priv->chipset < 0xa0) + cp_ctx(ctx, 0x407094 + (i<<8), 1); + else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) + cp_ctx(ctx, 0x407094 + (i<<8), 3); + else { + cp_ctx(ctx, 0x407094 + (i<<8), 4); + gr_def(ctx, 0x4070a0 + (i<<8), 1); + } + } + } + + cp_ctx(ctx, 0x407c00, 0x3); + if (dev_priv->chipset < 0x90) + gr_def(ctx, 0x407c00, 0x00010040); + else if (dev_priv->chipset < 0xa0) + gr_def(ctx, 0x407c00, 0x00390040); + else + gr_def(ctx, 0x407c00, 0x003d0040); + gr_def(ctx, 0x407c08, 0x00000022); + if (dev_priv->chipset >= 0xa0) { + cp_ctx(ctx, 0x407c10, 0x3); + cp_ctx(ctx, 0x407c20, 0x1); + cp_ctx(ctx, 0x407c2c, 0x1); + } + + if (dev_priv->chipset < 0xa0) { + cp_ctx(ctx, 0x407d00, 0x9); + } else { + cp_ctx(ctx, 0x407d00, 0x15); + } + if (dev_priv->chipset == 0x98) + gr_def(ctx, 0x407d08, 0x00380040); + else { + if (dev_priv->chipset < 0x90) + gr_def(ctx, 0x407d08, 0x00010040); + else if (dev_priv->chipset < 0xa0) + gr_def(ctx, 0x407d08, 0x00390040); + else + gr_def(ctx, 0x407d08, 0x003d0040); + gr_def(ctx, 0x407d0c, 0x00000022); + } + + /* 8000+: per-TP state */ + for (i = 0; i < 10; i++) { + if (units & (1<chipset < 0xa0) + base = 0x408000 + (i<<12); + else + base = 0x408000 + (i<<11); + if (dev_priv->chipset < 0xa0) + offset = base + 0xc00; + else + offset = base + 0x80; + cp_ctx(ctx, offset + 0x00, 1); + gr_def(ctx, offset + 0x00, 0x0000ff0a); + cp_ctx(ctx, offset + 0x08, 1); + + /* per-MP state */ + for (j = 0; j < (dev_priv->chipset < 0xa0 ? 2 : 4); j++) { + if (!(units & (1 << (j+24)))) continue; + if (dev_priv->chipset < 0xa0) + offset = base + 0x200 + (j<<7); + else + offset = base + 0x100 + (j<<7); + cp_ctx(ctx, offset, 0x20); + gr_def(ctx, offset + 0x00, 0x01800000); + gr_def(ctx, offset + 0x04, 0x00160000); + gr_def(ctx, offset + 0x08, 0x01800000); + gr_def(ctx, offset + 0x18, 0x0003ffff); + switch (dev_priv->chipset) { + case 0x50: + gr_def(ctx, offset + 0x1c, 0x00080000); + break; + case 0x84: + gr_def(ctx, offset + 0x1c, 0x00880000); + break; + case 0x86: + gr_def(ctx, offset + 0x1c, 0x008c0000); + break; + case 0x92: + case 0x96: + case 0x98: + gr_def(ctx, offset + 0x1c, 0x118c0000); + break; + case 0x94: + gr_def(ctx, offset + 0x1c, 0x10880000); + break; + case 0xa0: + case 0xa5: + gr_def(ctx, offset + 0x1c, 0x310c0000); + break; + case 0xa8: + case 0xaa: + case 0xac: + gr_def(ctx, offset + 0x1c, 0x300c0000); + break; + } + gr_def(ctx, offset + 0x40, 0x00010401); + if (dev_priv->chipset == 0x50) + gr_def(ctx, offset + 0x48, 0x00000040); + else + gr_def(ctx, offset + 0x48, 0x00000078); + gr_def(ctx, offset + 0x50, 0x000000bf); + gr_def(ctx, offset + 0x58, 0x00001210); + if (dev_priv->chipset == 0x50) + gr_def(ctx, offset + 0x5c, 0x00000080); + else + gr_def(ctx, offset + 0x5c, 0x08000080); + if (dev_priv->chipset >= 0xa0) + gr_def(ctx, offset + 0x68, 0x0000003e); + } + + if (dev_priv->chipset < 0xa0) + cp_ctx(ctx, base + 0x300, 0x4); + else + cp_ctx(ctx, base + 0x300, 0x5); + if (dev_priv->chipset == 0x50) + gr_def(ctx, base + 0x304, 0x00007070); + else if (dev_priv->chipset < 0xa0) + gr_def(ctx, base + 0x304, 0x00027070); + else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) + gr_def(ctx, base + 0x304, 0x01127070); + else + gr_def(ctx, base + 0x304, 0x05127070); + + if (dev_priv->chipset < 0xa0) + cp_ctx(ctx, base + 0x318, 1); + else + cp_ctx(ctx, base + 0x320, 1); + if (dev_priv->chipset == 0x50) + gr_def(ctx, base + 0x318, 0x0003ffff); + else if (dev_priv->chipset < 0xa0) + gr_def(ctx, base + 0x318, 0x03ffffff); + else + gr_def(ctx, base + 0x320, 0x07ffffff); + + if (dev_priv->chipset < 0xa0) + cp_ctx(ctx, base + 0x324, 5); + else + cp_ctx(ctx, base + 0x328, 4); + + if (dev_priv->chipset < 0xa0) { + cp_ctx(ctx, base + 0x340, 9); + offset = base + 0x340; + } else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) { + cp_ctx(ctx, base + 0x33c, 0xb); + offset = base + 0x344; + } else { + cp_ctx(ctx, base + 0x33c, 0xd); + offset = base + 0x344; + } + gr_def(ctx, offset + 0x0, 0x00120407); + gr_def(ctx, offset + 0x4, 0x05091507); + if (dev_priv->chipset == 0x84) + gr_def(ctx, offset + 0x8, 0x05100202); + else + gr_def(ctx, offset + 0x8, 0x05010202); + gr_def(ctx, offset + 0xc, 0x00030201); + + cp_ctx(ctx, base + 0x400, 2); + gr_def(ctx, base + 0x404, 0x00000040); + cp_ctx(ctx, base + 0x40c, 2); + gr_def(ctx, base + 0x40c, 0x0d0c0b0a); + gr_def(ctx, base + 0x410, 0x00141210); + + if (dev_priv->chipset < 0xa0) + offset = base + 0x800; + else + offset = base + 0x500; + cp_ctx(ctx, offset, 6); + gr_def(ctx, offset + 0x0, 0x000001f0); + gr_def(ctx, offset + 0x4, 0x00000001); + gr_def(ctx, offset + 0x8, 0x00000003); + if (dev_priv->chipset == 0x50 || dev_priv->chipset >= 0xaa) + gr_def(ctx, offset + 0xc, 0x00008000); + gr_def(ctx, offset + 0x14, 0x00039e00); + cp_ctx(ctx, offset + 0x1c, 2); + if (dev_priv->chipset == 0x50) + gr_def(ctx, offset + 0x1c, 0x00000040); + else + gr_def(ctx, offset + 0x1c, 0x00000100); + gr_def(ctx, offset + 0x20, 0x00003800); + + if (dev_priv->chipset >= 0xa0) { + cp_ctx(ctx, base + 0x54c, 2); + if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) + gr_def(ctx, base + 0x54c, 0x003fe006); + else + gr_def(ctx, base + 0x54c, 0x003fe007); + gr_def(ctx, base + 0x550, 0x003fe000); + } + + if (dev_priv->chipset < 0xa0) + offset = base + 0xa00; + else + offset = base + 0x680; + cp_ctx(ctx, offset, 1); + gr_def(ctx, offset, 0x00404040); + + if (dev_priv->chipset < 0xa0) + offset = base + 0xe00; + else + offset = base + 0x700; + cp_ctx(ctx, offset, 2); + if (dev_priv->chipset < 0xa0) + gr_def(ctx, offset, 0x0077f005); + else if (dev_priv->chipset == 0xa5) + gr_def(ctx, offset, 0x6cf7f007); + else if (dev_priv->chipset == 0xa8) + gr_def(ctx, offset, 0x6cfff007); + else if (dev_priv->chipset == 0xac) + gr_def(ctx, offset, 0x0cfff007); + else + gr_def(ctx, offset, 0x0cf7f007); + if (dev_priv->chipset == 0x50) + gr_def(ctx, offset + 0x4, 0x00007fff); + else if (dev_priv->chipset < 0xa0) + gr_def(ctx, offset + 0x4, 0x003f7fff); + else + gr_def(ctx, offset + 0x4, 0x02bf7fff); + cp_ctx(ctx, offset + 0x2c, 1); + if (dev_priv->chipset == 0x50) { + cp_ctx(ctx, offset + 0x50, 9); + gr_def(ctx, offset + 0x54, 0x000003ff); + gr_def(ctx, offset + 0x58, 0x00000003); + gr_def(ctx, offset + 0x5c, 0x00000003); + gr_def(ctx, offset + 0x60, 0x000001ff); + gr_def(ctx, offset + 0x64, 0x0000001f); + gr_def(ctx, offset + 0x68, 0x0000000f); + gr_def(ctx, offset + 0x6c, 0x0000000f); + } else if(dev_priv->chipset < 0xa0) { + cp_ctx(ctx, offset + 0x50, 1); + cp_ctx(ctx, offset + 0x70, 1); + } else { + cp_ctx(ctx, offset + 0x50, 1); + cp_ctx(ctx, offset + 0x60, 5); + } + } + } +} + +/* + * xfer areas. These are a pain. + * + * There are 2 xfer areas: the first one is big and contains all sorts of + * stuff, the second is small and contains some per-TP context. + * + * Each area is split into 8 "strands". The areas, when saved to grctx, + * are made of 8-word blocks. Each block contains a single word from + * each strand. The strands are independent of each other, their + * addresses are unrelated to each other, and data in them is closely + * packed together. The strand layout varies a bit between cards: here + * and there, a single word is thrown out in the middle and the whole + * strand is offset by a bit from corresponding one on another chipset. + * For this reason, addresses of stuff in strands are almost useless. + * Knowing sequence of stuff and size of gaps between them is much more + * useful, and that's how we build the strands in our generator. + * + * NVA0 takes this mess to a whole new level by cutting the old strands + * into a few dozen pieces [known as genes], rearranging them randomly, + * and putting them back together to make new strands. Hopefully these + * genes correspond more or less directly to the same PGRAPH subunits + * as in 400040 register. + * + * The most common value in default context is 0, and when the genes + * are separated by 0's, gene bounduaries are quite speculative... + * some of them can be clearly deduced, others can be guessed, and yet + * others won't be resolved without figuring out the real meaning of + * given ctxval. For the same reason, ending point of each strand + * is unknown. Except for strand 0, which is the longest strand and + * its end corresponds to end of the whole xfer. + * + * An unsolved mystery is the seek instruction: it takes an argument + * in bits 8-18, and that argument is clearly the place in strands to + * seek to... but the offsets don't seem to correspond to offsets as + * seen in grctx. Perhaps there's another, real, not randomly-changing + * addressing in strands, and the xfer insn just happens to skip over + * the unused bits? NV10-NV30 PIPE comes to mind... + * + * As far as I know, there's no way to access the xfer areas directly + * without the help of ctxprog. + */ + +static inline void +xf_emit(struct nouveau_grctx *ctx, int num, uint32_t val) { + int i; + if (val && ctx->mode == NOUVEAU_GRCTX_VALS) + for (i = 0; i < num; i++) + nv_wo32(ctx->dev, ctx->data, ctx->ctxvals_pos + (i << 3), val); + ctx->ctxvals_pos += num << 3; +} + +/* Gene declarations... */ + +static void nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx); +static void nv50_graph_construct_gene_unk1(struct nouveau_grctx *ctx); +static void nv50_graph_construct_gene_unk2(struct nouveau_grctx *ctx); +static void nv50_graph_construct_gene_unk3(struct nouveau_grctx *ctx); +static void nv50_graph_construct_gene_unk4(struct nouveau_grctx *ctx); +static void nv50_graph_construct_gene_unk5(struct nouveau_grctx *ctx); +static void nv50_graph_construct_gene_unk6(struct nouveau_grctx *ctx); +static void nv50_graph_construct_gene_unk7(struct nouveau_grctx *ctx); +static void nv50_graph_construct_gene_unk8(struct nouveau_grctx *ctx); +static void nv50_graph_construct_gene_unk9(struct nouveau_grctx *ctx); +static void nv50_graph_construct_gene_unk10(struct nouveau_grctx *ctx); +static void nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx); +static void nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx); + +static void +nv50_graph_construct_xfer1(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + int i; + int offset; + int size = 0; + uint32_t units = nv_rd32 (ctx->dev, 0x1540); + + offset = (ctx->ctxvals_pos+0x3f)&~0x3f; + ctx->ctxvals_base = offset; + + if (dev_priv->chipset < 0xa0) { + /* Strand 0 */ + ctx->ctxvals_pos = offset; + switch (dev_priv->chipset) { + case 0x50: + xf_emit(ctx, 0x99, 0); + break; + case 0x84: + case 0x86: + xf_emit(ctx, 0x384, 0); + break; + case 0x92: + case 0x94: + case 0x96: + case 0x98: + xf_emit(ctx, 0x380, 0); + break; + } + nv50_graph_construct_gene_m2mf (ctx); + switch (dev_priv->chipset) { + case 0x50: + case 0x84: + case 0x86: + case 0x98: + xf_emit(ctx, 0x4c4, 0); + break; + case 0x92: + case 0x94: + case 0x96: + xf_emit(ctx, 0x984, 0); + break; + } + nv50_graph_construct_gene_unk5(ctx); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 0xa, 0); + else + xf_emit(ctx, 0xb, 0); + nv50_graph_construct_gene_unk4(ctx); + nv50_graph_construct_gene_unk3(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 1 */ + ctx->ctxvals_pos = offset + 0x1; + nv50_graph_construct_gene_unk6(ctx); + nv50_graph_construct_gene_unk7(ctx); + nv50_graph_construct_gene_unk8(ctx); + switch (dev_priv->chipset) { + case 0x50: + case 0x92: + xf_emit(ctx, 0xfb, 0); + break; + case 0x84: + xf_emit(ctx, 0xd3, 0); + break; + case 0x94: + case 0x96: + xf_emit(ctx, 0xab, 0); + break; + case 0x86: + case 0x98: + xf_emit(ctx, 0x6b, 0); + break; + } + xf_emit(ctx, 2, 0x4e3bfdf); + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 0x0fac6881); + xf_emit(ctx, 0xb, 0); + xf_emit(ctx, 2, 0x4e3bfdf); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 2 */ + ctx->ctxvals_pos = offset + 0x2; + switch (dev_priv->chipset) { + case 0x50: + case 0x92: + xf_emit(ctx, 0xa80, 0); + break; + case 0x84: + xf_emit(ctx, 0xa7e, 0); + break; + case 0x94: + case 0x96: + xf_emit(ctx, 0xa7c, 0); + break; + case 0x86: + case 0x98: + xf_emit(ctx, 0xa7a, 0); + break; + } + xf_emit(ctx, 1, 0x3fffff); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x1fff); + xf_emit(ctx, 0xe, 0); + nv50_graph_construct_gene_unk9(ctx); + nv50_graph_construct_gene_unk2(ctx); + nv50_graph_construct_gene_unk1(ctx); + nv50_graph_construct_gene_unk10(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 3: per-ROP group state */ + ctx->ctxvals_pos = offset + 3; + for (i = 0; i < 6; i++) + if (units & (1 << (i + 16))) + nv50_graph_construct_gene_ropc(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strands 4-7: per-TP state */ + for (i = 0; i < 4; i++) { + ctx->ctxvals_pos = offset + 4 + i; + if (units & (1 << (2 * i))) + nv50_graph_construct_xfer_tp(ctx); + if (units & (1 << (2 * i + 1))) + nv50_graph_construct_xfer_tp(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + } + } else { + /* Strand 0 */ + ctx->ctxvals_pos = offset; + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 0x385, 0); + else + xf_emit(ctx, 0x384, 0); + nv50_graph_construct_gene_m2mf(ctx); + xf_emit(ctx, 0x950, 0); + nv50_graph_construct_gene_unk10(ctx); + xf_emit(ctx, 1, 0x0fac6881); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { + xf_emit(ctx, 1, 1); + xf_emit(ctx, 3, 0); + } + nv50_graph_construct_gene_unk8(ctx); + if (dev_priv->chipset == 0xa0) + xf_emit(ctx, 0x189, 0); + else if (dev_priv->chipset < 0xa8) + xf_emit(ctx, 0x99, 0); + else if (dev_priv->chipset == 0xaa) + xf_emit(ctx, 0x65, 0); + else + xf_emit(ctx, 0x6d, 0); + nv50_graph_construct_gene_unk9(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 1 */ + ctx->ctxvals_pos = offset + 1; + nv50_graph_construct_gene_unk1(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 2 */ + ctx->ctxvals_pos = offset + 2; + if (dev_priv->chipset == 0xa0) { + nv50_graph_construct_gene_unk2(ctx); + } + xf_emit(ctx, 0x36, 0); + nv50_graph_construct_gene_unk5(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 3 */ + ctx->ctxvals_pos = offset + 3; + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + nv50_graph_construct_gene_unk6(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 4 */ + ctx->ctxvals_pos = offset + 4; + if (dev_priv->chipset == 0xa0) + xf_emit(ctx, 0xa80, 0); + else + xf_emit(ctx, 0xa7a, 0); + xf_emit(ctx, 1, 0x3fffff); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x1fff); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 5 */ + ctx->ctxvals_pos = offset + 5; + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x0fac6881); + xf_emit(ctx, 0xb, 0); + xf_emit(ctx, 2, 0x4e3bfdf); + xf_emit(ctx, 3, 0); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 2, 0x4e3bfdf); + xf_emit(ctx, 2, 0); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 1, 0); + for (i = 0; i < 8; i++) + if (units & (1<<(i+16))) + nv50_graph_construct_gene_ropc(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 6 */ + ctx->ctxvals_pos = offset + 6; + nv50_graph_construct_gene_unk3(ctx); + xf_emit(ctx, 0xb, 0); + nv50_graph_construct_gene_unk4(ctx); + nv50_graph_construct_gene_unk7(ctx); + if (units & (1 << 0)) + nv50_graph_construct_xfer_tp(ctx); + if (units & (1 << 1)) + nv50_graph_construct_xfer_tp(ctx); + if (units & (1 << 2)) + nv50_graph_construct_xfer_tp(ctx); + if (units & (1 << 3)) + nv50_graph_construct_xfer_tp(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 7 */ + ctx->ctxvals_pos = offset + 7; + if (dev_priv->chipset == 0xa0) { + if (units & (1 << 4)) + nv50_graph_construct_xfer_tp(ctx); + if (units & (1 << 5)) + nv50_graph_construct_xfer_tp(ctx); + if (units & (1 << 6)) + nv50_graph_construct_xfer_tp(ctx); + if (units & (1 << 7)) + nv50_graph_construct_xfer_tp(ctx); + if (units & (1 << 8)) + nv50_graph_construct_xfer_tp(ctx); + if (units & (1 << 9)) + nv50_graph_construct_xfer_tp(ctx); + } else { + nv50_graph_construct_gene_unk2(ctx); + } + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + } + + ctx->ctxvals_pos = offset + size * 8; + ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; + cp_lsr (ctx, offset); + cp_out (ctx, CP_SET_XFER_POINTER); + cp_lsr (ctx, size); + cp_out (ctx, CP_SEEK_1); + cp_out (ctx, CP_XFER_1); + cp_wait(ctx, XFER, BUSY); +} + +/* + * non-trivial demagiced parts of ctx init go here + */ + +static void +nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx) +{ + /* m2mf state */ + xf_emit (ctx, 1, 0); /* DMA_NOTIFY instance >> 4 */ + xf_emit (ctx, 1, 0); /* DMA_BUFFER_IN instance >> 4 */ + xf_emit (ctx, 1, 0); /* DMA_BUFFER_OUT instance >> 4 */ + xf_emit (ctx, 1, 0); /* OFFSET_IN */ + xf_emit (ctx, 1, 0); /* OFFSET_OUT */ + xf_emit (ctx, 1, 0); /* PITCH_IN */ + xf_emit (ctx, 1, 0); /* PITCH_OUT */ + xf_emit (ctx, 1, 0); /* LINE_LENGTH */ + xf_emit (ctx, 1, 0); /* LINE_COUNT */ + xf_emit (ctx, 1, 0x21); /* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */ + xf_emit (ctx, 1, 1); /* LINEAR_IN */ + xf_emit (ctx, 1, 0x2); /* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */ + xf_emit (ctx, 1, 0x100); /* TILING_PITCH_IN */ + xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_IN */ + xf_emit (ctx, 1, 1); /* TILING_DEPTH_IN */ + xf_emit (ctx, 1, 0); /* TILING_POSITION_IN_Z */ + xf_emit (ctx, 1, 0); /* TILING_POSITION_IN */ + xf_emit (ctx, 1, 1); /* LINEAR_OUT */ + xf_emit (ctx, 1, 0x2); /* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */ + xf_emit (ctx, 1, 0x100); /* TILING_PITCH_OUT */ + xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_OUT */ + xf_emit (ctx, 1, 1); /* TILING_DEPTH_OUT */ + xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT_Z */ + xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT */ + xf_emit (ctx, 1, 0); /* OFFSET_IN_HIGH */ + xf_emit (ctx, 1, 0); /* OFFSET_OUT_HIGH */ +} + +static void +nv50_graph_construct_gene_unk1(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + /* end of area 2 on pre-NVA0, area 1 on NVAx */ + xf_emit(ctx, 2, 4); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x80); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 0x80c14); + xf_emit(ctx, 1, 0); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 1, 0x3ff); + else + xf_emit(ctx, 1, 0x7ff); + switch (dev_priv->chipset) { + case 0x50: + case 0x86: + case 0x98: + case 0xaa: + case 0xac: + xf_emit(ctx, 0x542, 0); + break; + case 0x84: + case 0x92: + case 0x94: + case 0x96: + xf_emit(ctx, 0x942, 0); + break; + case 0xa0: + xf_emit(ctx, 0x2042, 0); + break; + case 0xa5: + case 0xa8: + xf_emit(ctx, 0x842, 0); + break; + } + xf_emit(ctx, 2, 4); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x80); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x27); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x26); + xf_emit(ctx, 3, 0); +} + +static void +nv50_graph_construct_gene_unk10(struct nouveau_grctx *ctx) +{ + /* end of area 2 on pre-NVA0, area 1 on NVAx */ + xf_emit(ctx, 0x10, 0x04000000); + xf_emit(ctx, 0x24, 0); + xf_emit(ctx, 2, 0x04e3bfdf); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x1fe21); +} + +static void +nv50_graph_construct_gene_unk2(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + /* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */ + if (dev_priv->chipset != 0x50) { + xf_emit(ctx, 5, 0); + xf_emit(ctx, 1, 0x80c14); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x804); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 2, 4); + xf_emit(ctx, 1, 0x8100c12); + } + xf_emit(ctx, 1, 0); + xf_emit(ctx, 2, 4); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x10); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 3, 0); + else + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 0x804); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0x1a); + if (dev_priv->chipset != 0x50) + xf_emit(ctx, 1, 0x7f); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0x80c14); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x8100c12); + xf_emit(ctx, 2, 4); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x10); + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0x8100c12); + xf_emit(ctx, 6, 0); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 1, 0x3ff); + else + xf_emit(ctx, 1, 0x7ff); + xf_emit(ctx, 1, 0x80c14); + xf_emit(ctx, 0x38, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x10); + xf_emit(ctx, 0x38, 0); + xf_emit(ctx, 2, 0x88); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 0x16, 0); + xf_emit(ctx, 1, 0x26); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x3f800000); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 4, 0); + else + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 0x1a); + xf_emit(ctx, 1, 0x10); + if (dev_priv->chipset != 0x50) + xf_emit(ctx, 0x28, 0); + else + xf_emit(ctx, 0x25, 0); + xf_emit(ctx, 1, 0x52); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x26); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 2, 4); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x1a); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x00ffff00); + xf_emit(ctx, 1, 0); +} + +static void +nv50_graph_construct_gene_unk3(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + /* end of area 0 on pre-NVA0, beginning of area 6 on NVAx */ + xf_emit(ctx, 1, 0x3f); + xf_emit(ctx, 0xa, 0); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 2, 0x04000000); + xf_emit(ctx, 8, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 4); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 0x10, 0); + else + xf_emit(ctx, 0x11, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0x1001); + xf_emit(ctx, 4, 0xffff); + xf_emit(ctx, 0x20, 0); + xf_emit(ctx, 0x10, 0x3f800000); + xf_emit(ctx, 1, 0x10); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 1, 0); + else + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 3); + xf_emit(ctx, 2, 0); +} + +static void +nv50_graph_construct_gene_unk4(struct nouveau_grctx *ctx) +{ + /* middle of area 0 on pre-NVA0, middle of area 6 on NVAx */ + xf_emit(ctx, 2, 0x04000000); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x80); + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 0x80); + xf_emit(ctx, 1, 0); +} + +static void +nv50_graph_construct_gene_unk5(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + /* middle of area 0 on pre-NVA0 [after m2mf], end of area 2 on NVAx */ + xf_emit(ctx, 2, 4); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 0x1c4d, 0); + else + xf_emit(ctx, 0x1c4b, 0); + xf_emit(ctx, 2, 4); + xf_emit(ctx, 1, 0x8100c12); + if (dev_priv->chipset != 0x50) + xf_emit(ctx, 1, 3); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x8100c12); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x80c14); + xf_emit(ctx, 1, 1); + if (dev_priv->chipset >= 0xa0) + xf_emit(ctx, 2, 4); + xf_emit(ctx, 1, 0x80c14); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x8100c12); + xf_emit(ctx, 1, 0x27); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 0x3c1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 0x16, 0); + xf_emit(ctx, 1, 0x8100c12); + xf_emit(ctx, 1, 0); +} + +static void +nv50_graph_construct_gene_unk6(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + /* beginning of area 1 on pre-NVA0 [after m2mf], area 3 on NVAx */ + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 0xf); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 8, 0); + else + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 0x20); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 0x11, 0); + else if (dev_priv->chipset >= 0xa0) + xf_emit(ctx, 0xf, 0); + else + xf_emit(ctx, 0xe, 0); + xf_emit(ctx, 1, 0x1a); + xf_emit(ctx, 0xd, 0); + xf_emit(ctx, 2, 4); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 8); + xf_emit(ctx, 1, 0); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 1, 0x3ff); + else + xf_emit(ctx, 1, 0x7ff); + if (dev_priv->chipset == 0xa8) + xf_emit(ctx, 1, 0x1e00); + xf_emit(ctx, 0xc, 0); + xf_emit(ctx, 1, 0xf); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 0x125, 0); + else if (dev_priv->chipset < 0xa0) + xf_emit(ctx, 0x126, 0); + else if (dev_priv->chipset == 0xa0 || dev_priv->chipset >= 0xaa) + xf_emit(ctx, 0x124, 0); + else + xf_emit(ctx, 0x1f7, 0); + xf_emit(ctx, 1, 0xf); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 3, 0); + else + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 0xa1, 0); + else + xf_emit(ctx, 0x5a, 0); + xf_emit(ctx, 1, 0xf); + if (dev_priv->chipset < 0xa0) + xf_emit(ctx, 0x834, 0); + else if (dev_priv->chipset == 0xa0) + xf_emit(ctx, 0x1873, 0); + else if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 0x8ba, 0); + else + xf_emit(ctx, 0x833, 0); + xf_emit(ctx, 1, 0xf); + xf_emit(ctx, 0xf, 0); +} + +static void +nv50_graph_construct_gene_unk7(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + /* middle of area 1 on pre-NVA0 [after m2mf], middle of area 6 on NVAx */ + xf_emit(ctx, 2, 0); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 2, 1); + else + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 2, 0x100); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 8); + xf_emit(ctx, 5, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 3, 1); + xf_emit(ctx, 1, 0xcf); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 6, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 3, 1); + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0x15); + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 0x4444480); + xf_emit(ctx, 0x37, 0); +} + +static void +nv50_graph_construct_gene_unk8(struct nouveau_grctx *ctx) +{ + /* middle of area 1 on pre-NVA0 [after m2mf], middle of area 0 on NVAx */ + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 0x8100c12); + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 0x100); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x10001); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x10001); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0x10001); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 2); +} + +static void +nv50_graph_construct_gene_unk9(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + /* middle of area 2 on pre-NVA0 [after m2mf], end of area 0 on NVAx */ + xf_emit(ctx, 1, 0x3f800000); + xf_emit(ctx, 6, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 0x1a); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 0x12, 0); + xf_emit(ctx, 1, 0x00ffff00); + xf_emit(ctx, 6, 0); + xf_emit(ctx, 1, 0xf); + xf_emit(ctx, 7, 0); + xf_emit(ctx, 1, 0x0fac6881); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 0xf, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 2, 0); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 1, 3); + else if (dev_priv->chipset >= 0xa0) + xf_emit(ctx, 1, 1); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 2, 0x04000000); + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 5); + xf_emit(ctx, 1, 0x52); + if (dev_priv->chipset == 0x50) { + xf_emit(ctx, 0x13, 0); + } else { + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 1); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 0x11, 0); + else + xf_emit(ctx, 0x10, 0); + } + xf_emit(ctx, 0x10, 0x3f800000); + xf_emit(ctx, 1, 0x10); + xf_emit(ctx, 0x26, 0); + xf_emit(ctx, 1, 0x8100c12); + xf_emit(ctx, 1, 5); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 4, 0xffff); + if (dev_priv->chipset != 0x50) + xf_emit(ctx, 1, 3); + if (dev_priv->chipset < 0xa0) + xf_emit(ctx, 0x1f, 0); + else if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 0xc, 0); + else + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 0x00ffff00); + xf_emit(ctx, 1, 0x1a); + if (dev_priv->chipset != 0x50) { + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 3); + } + if (dev_priv->chipset < 0xa0) + xf_emit(ctx, 0x26, 0); + else + xf_emit(ctx, 0x3c, 0); + xf_emit(ctx, 1, 0x102); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 4, 4); + if (dev_priv->chipset >= 0xa0) + xf_emit(ctx, 8, 0); + xf_emit(ctx, 2, 4); + xf_emit(ctx, 1, 0); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 1, 0x3ff); + else + xf_emit(ctx, 1, 0x7ff); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x102); + xf_emit(ctx, 9, 0); + xf_emit(ctx, 4, 4); + xf_emit(ctx, 0x2c, 0); +} + +static void +nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + int magic2; + if (dev_priv->chipset == 0x50) { + magic2 = 0x00003e60; + } else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) { + magic2 = 0x001ffe67; + } else { + magic2 = 0x00087e67; + } + xf_emit(ctx, 8, 0); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, magic2); + xf_emit(ctx, 4, 0); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 1, 1); + xf_emit(ctx, 7, 0); + if (dev_priv->chipset >= 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 1, 0x15); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0x10); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 4, 0); + if (dev_priv->chipset == 0x86 || dev_priv->chipset == 0x92 || dev_priv->chipset == 0x98 || dev_priv->chipset >= 0xa0) { + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 0x400); + xf_emit(ctx, 1, 0x300); + xf_emit(ctx, 1, 0x1001); + if (dev_priv->chipset != 0xa0) { + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 1, 0); + else + xf_emit(ctx, 1, 0x15); + } + xf_emit(ctx, 3, 0); + } + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 8, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0x10); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 0x13, 0); + xf_emit(ctx, 1, 0x10); + xf_emit(ctx, 0x10, 0); + xf_emit(ctx, 0x10, 0x3f800000); + xf_emit(ctx, 0x19, 0); + xf_emit(ctx, 1, 0x10); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x3f); + xf_emit(ctx, 6, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + if (dev_priv->chipset >= 0xa0) { + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x1001); + xf_emit(ctx, 0xb, 0); + } else { + xf_emit(ctx, 0xc, 0); + } + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 7, 0); + xf_emit(ctx, 1, 0xf); + xf_emit(ctx, 7, 0); + xf_emit(ctx, 1, 0x11); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 4, 0); + else + xf_emit(ctx, 6, 0); + xf_emit(ctx, 3, 1); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, magic2); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x0fac6881); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { + xf_emit(ctx, 1, 0); + xf_emit(ctx, 0x18, 1); + xf_emit(ctx, 8, 2); + xf_emit(ctx, 8, 1); + xf_emit(ctx, 8, 2); + xf_emit(ctx, 8, 1); + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 5, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 0x16, 0); + } else { + if (dev_priv->chipset >= 0xa0) + xf_emit(ctx, 0x1b, 0); + else + xf_emit(ctx, 0x15, 0); + } + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 2, 1); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 2, 1); + if (dev_priv->chipset >= 0xa0) + xf_emit(ctx, 4, 0); + else + xf_emit(ctx, 3, 0); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { + xf_emit(ctx, 0x10, 1); + xf_emit(ctx, 8, 2); + xf_emit(ctx, 0x10, 1); + xf_emit(ctx, 8, 2); + xf_emit(ctx, 8, 1); + xf_emit(ctx, 3, 0); + } + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 0x5b, 0); +} + +static void +nv50_graph_construct_xfer_tp_x1(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + int magic3; + if (dev_priv->chipset == 0x50) + magic3 = 0x1000; + else if (dev_priv->chipset == 0x86 || dev_priv->chipset == 0x98 || dev_priv->chipset >= 0xa8) + magic3 = 0x1e00; + else + magic3 = 0; + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 4); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 0x24, 0); + else if (dev_priv->chipset >= 0xa0) + xf_emit(ctx, 0x14, 0); + else + xf_emit(ctx, 0x15, 0); + xf_emit(ctx, 2, 4); + if (dev_priv->chipset >= 0xa0) + xf_emit(ctx, 1, 0x03020100); + else + xf_emit(ctx, 1, 0x00608080); + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 2, 4); + xf_emit(ctx, 1, 0x80); + if (magic3) + xf_emit(ctx, 1, magic3); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 0x24, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 0x80); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 0x03020100); + xf_emit(ctx, 1, 3); + if (magic3) + xf_emit(ctx, 1, magic3); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 3); + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 4); + if (dev_priv->chipset == 0x94 || dev_priv->chipset == 0x96) + xf_emit(ctx, 0x1024, 0); + else if (dev_priv->chipset < 0xa0) + xf_emit(ctx, 0xa24, 0); + else if (dev_priv->chipset == 0xa0 || dev_priv->chipset >= 0xaa) + xf_emit(ctx, 0x214, 0); + else + xf_emit(ctx, 0x414, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 3); + xf_emit(ctx, 2, 0); +} + +static void +nv50_graph_construct_xfer_tp_x2(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + int magic1, magic2; + if (dev_priv->chipset == 0x50) { + magic1 = 0x3ff; + magic2 = 0x00003e60; + } else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) { + magic1 = 0x7ff; + magic2 = 0x001ffe67; + } else { + magic1 = 0x7ff; + magic2 = 0x00087e67; + } + xf_emit(ctx, 3, 0); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 1, 1); + xf_emit(ctx, 0xc, 0); + xf_emit(ctx, 1, 0xf); + xf_emit(ctx, 0xb, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 4, 0xffff); + xf_emit(ctx, 8, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 5, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 2, 0); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { + xf_emit(ctx, 1, 3); + xf_emit(ctx, 1, 0); + } else if (dev_priv->chipset >= 0xa0) + xf_emit(ctx, 1, 1); + xf_emit(ctx, 0xa, 0); + xf_emit(ctx, 2, 1); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 2, 1); + xf_emit(ctx, 1, 2); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { + xf_emit(ctx, 1, 0); + xf_emit(ctx, 0x18, 1); + xf_emit(ctx, 8, 2); + xf_emit(ctx, 8, 1); + xf_emit(ctx, 8, 2); + xf_emit(ctx, 8, 1); + xf_emit(ctx, 1, 0); + } + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 7, 0); + xf_emit(ctx, 1, 0x0fac6881); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 3, 0xcf); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 1, 1); + xf_emit(ctx, 0xa, 0); + xf_emit(ctx, 2, 1); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 2, 1); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 8, 1); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 7, 0); + xf_emit(ctx, 1, 0x0fac6881); + xf_emit(ctx, 1, 0xf); + xf_emit(ctx, 7, 0); + xf_emit(ctx, 1, magic2); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x11); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 2, 1); + else + xf_emit(ctx, 1, 1); + if(dev_priv->chipset == 0x50) + xf_emit(ctx, 1, 0); + else + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 5, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 7, 0); + xf_emit(ctx, 1, 0x0fac6881); + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, magic1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 2, 0); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 1, 1); + xf_emit(ctx, 0x28, 0); + xf_emit(ctx, 8, 8); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 7, 0); + xf_emit(ctx, 1, 0x0fac6881); + xf_emit(ctx, 8, 0x400); + xf_emit(ctx, 8, 0x300); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0xf); + xf_emit(ctx, 7, 0); + xf_emit(ctx, 1, 0x20); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 1, 0x100); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x40); + xf_emit(ctx, 1, 0x100); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 3); + xf_emit(ctx, 4, 0); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, magic2); + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 1, 0x0fac6881); + xf_emit(ctx, 9, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0x400); + xf_emit(ctx, 1, 0x300); + xf_emit(ctx, 1, 0x1001); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 4, 0); + else + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 7, 0); + xf_emit(ctx, 1, 0x0fac6881); + xf_emit(ctx, 1, 0xf); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { + xf_emit(ctx, 0x15, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 3, 0); + } else + xf_emit(ctx, 0x17, 0); + if (dev_priv->chipset >= 0xa0) + xf_emit(ctx, 1, 0x0fac6881); + xf_emit(ctx, 1, magic2); + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 2, 1); + xf_emit(ctx, 3, 0); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 2, 1); + else + xf_emit(ctx, 1, 1); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 2, 0); + else if (dev_priv->chipset != 0x50) + xf_emit(ctx, 1, 0); +} + +static void +nv50_graph_construct_xfer_tp_x3(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 2, 0); + else + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 0x2a712488); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x4085c000); + xf_emit(ctx, 1, 0x40); + xf_emit(ctx, 1, 0x100); + xf_emit(ctx, 1, 0x10100); + xf_emit(ctx, 1, 0x02800000); +} + +static void +nv50_graph_construct_xfer_tp_x4(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + xf_emit(ctx, 2, 0x04e3bfdf); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x00ffff00); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 2, 1); + else + xf_emit(ctx, 1, 1); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 0x00ffff00); + xf_emit(ctx, 8, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0x30201000); + xf_emit(ctx, 1, 0x70605040); + xf_emit(ctx, 1, 0xb8a89888); + xf_emit(ctx, 1, 0xf8e8d8c8); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x1a); +} + +static void +nv50_graph_construct_xfer_tp_x5(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 0xfac6881); + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 2, 1); + xf_emit(ctx, 2, 0); + xf_emit(ctx, 1, 1); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 0xb, 0); + else + xf_emit(ctx, 0xa, 0); + xf_emit(ctx, 8, 1); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 7, 0); + xf_emit(ctx, 1, 0xfac6881); + xf_emit(ctx, 1, 0xf); + xf_emit(ctx, 7, 0); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 1, 1); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { + xf_emit(ctx, 6, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 6, 0); + } else { + xf_emit(ctx, 0xb, 0); + } +} + +static void +nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + if (dev_priv->chipset < 0xa0) { + nv50_graph_construct_xfer_tp_x1(ctx); + nv50_graph_construct_xfer_tp_x2(ctx); + nv50_graph_construct_xfer_tp_x3(ctx); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 0xf, 0); + else + xf_emit(ctx, 0x12, 0); + nv50_graph_construct_xfer_tp_x4(ctx); + } else { + nv50_graph_construct_xfer_tp_x3(ctx); + if (dev_priv->chipset < 0xaa) + xf_emit(ctx, 0xc, 0); + else + xf_emit(ctx, 0xa, 0); + nv50_graph_construct_xfer_tp_x2(ctx); + nv50_graph_construct_xfer_tp_x5(ctx); + nv50_graph_construct_xfer_tp_x4(ctx); + nv50_graph_construct_xfer_tp_x1(ctx); + } +} + +static void +nv50_graph_construct_xfer_tp2(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + int i, mpcnt; + if (dev_priv->chipset == 0x98 || dev_priv->chipset == 0xaa) + mpcnt = 1; + else if (dev_priv->chipset < 0xa0 || dev_priv->chipset >= 0xa8) + mpcnt = 2; + else + mpcnt = 3; + for (i = 0; i < mpcnt; i++) { + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x80); + xf_emit(ctx, 1, 0x80007004); + xf_emit(ctx, 1, 0x04000400); + if (dev_priv->chipset >= 0xa0) + xf_emit(ctx, 1, 0xc0); + xf_emit(ctx, 1, 0x1000); + xf_emit(ctx, 2, 0); + if (dev_priv->chipset == 0x86 || dev_priv->chipset == 0x98 || dev_priv->chipset >= 0xa8) { + xf_emit(ctx, 1, 0xe00); + xf_emit(ctx, 1, 0x1e00); + } + xf_emit(ctx, 1, 1); + xf_emit(ctx, 2, 0); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 2, 0x1000); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 2); + if (dev_priv->chipset >= 0xaa) + xf_emit(ctx, 0xb, 0); + else if (dev_priv->chipset >= 0xa0) + xf_emit(ctx, 0xc, 0); + else + xf_emit(ctx, 0xa, 0); + } + xf_emit(ctx, 1, 0x08100c12); + xf_emit(ctx, 1, 0); + if (dev_priv->chipset >= 0xa0) { + xf_emit(ctx, 1, 0x1fe21); + } + xf_emit(ctx, 5, 0); + xf_emit(ctx, 4, 0xffff); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 2, 0x10001); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 0x1fe21); + xf_emit(ctx, 1, 0); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 1, 1); + xf_emit(ctx, 4, 0); + xf_emit(ctx, 1, 0x08100c12); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 8, 0); + xf_emit(ctx, 1, 0xfac6881); + xf_emit(ctx, 1, 0); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) + xf_emit(ctx, 1, 3); + xf_emit(ctx, 3, 0); + xf_emit(ctx, 1, 4); + xf_emit(ctx, 9, 0); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 2, 1); + xf_emit(ctx, 1, 2); + xf_emit(ctx, 3, 1); + xf_emit(ctx, 1, 0); + if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { + xf_emit(ctx, 8, 2); + xf_emit(ctx, 0x10, 1); + xf_emit(ctx, 8, 2); + xf_emit(ctx, 0x18, 1); + xf_emit(ctx, 3, 0); + } + xf_emit(ctx, 1, 4); + if (dev_priv->chipset == 0x50) + xf_emit(ctx, 0x3a0, 0); + else if (dev_priv->chipset < 0x94) + xf_emit(ctx, 0x3a2, 0); + else if (dev_priv->chipset == 0x98 || dev_priv->chipset == 0xaa) + xf_emit(ctx, 0x39f, 0); + else + xf_emit(ctx, 0x3a3, 0); + xf_emit(ctx, 1, 0x11); + xf_emit(ctx, 1, 0); + xf_emit(ctx, 1, 1); + xf_emit(ctx, 0x2d, 0); +} + +static void +nv50_graph_construct_xfer2(struct nouveau_grctx *ctx) +{ + struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; + int i; + uint32_t offset; + uint32_t units = nv_rd32 (ctx->dev, 0x1540); + int size = 0; + + offset = (ctx->ctxvals_pos+0x3f)&~0x3f; + + if (dev_priv->chipset < 0xa0) { + for (i = 0; i < 8; i++) { + ctx->ctxvals_pos = offset + i; + if (i == 0) + xf_emit(ctx, 1, 0x08100c12); + if (units & (1 << i)) + nv50_graph_construct_xfer_tp2(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + } + } else { + /* Strand 0: TPs 0, 1 */ + ctx->ctxvals_pos = offset; + xf_emit(ctx, 1, 0x08100c12); + if (units & (1 << 0)) + nv50_graph_construct_xfer_tp2(ctx); + if (units & (1 << 1)) + nv50_graph_construct_xfer_tp2(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 0: TPs 2, 3 */ + ctx->ctxvals_pos = offset + 1; + if (units & (1 << 2)) + nv50_graph_construct_xfer_tp2(ctx); + if (units & (1 << 3)) + nv50_graph_construct_xfer_tp2(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 0: TPs 4, 5, 6 */ + ctx->ctxvals_pos = offset + 2; + if (units & (1 << 4)) + nv50_graph_construct_xfer_tp2(ctx); + if (units & (1 << 5)) + nv50_graph_construct_xfer_tp2(ctx); + if (units & (1 << 6)) + nv50_graph_construct_xfer_tp2(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + + /* Strand 0: TPs 7, 8, 9 */ + ctx->ctxvals_pos = offset + 3; + if (units & (1 << 7)) + nv50_graph_construct_xfer_tp2(ctx); + if (units & (1 << 8)) + nv50_graph_construct_xfer_tp2(ctx); + if (units & (1 << 9)) + nv50_graph_construct_xfer_tp2(ctx); + if ((ctx->ctxvals_pos-offset)/8 > size) + size = (ctx->ctxvals_pos-offset)/8; + } + ctx->ctxvals_pos = offset + size * 8; + ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; + cp_lsr (ctx, offset); + cp_out (ctx, CP_SET_XFER_POINTER); + cp_lsr (ctx, size); + cp_out (ctx, CP_SEEK_2); + cp_out (ctx, CP_XFER_2); + cp_wait(ctx, XFER, BUSY); +} -- cgit v1.2.3 From 81e2d42200cd8fa37ec4ebdc66373d0db0e05678 Mon Sep 17 00:00:00 2001 From: Marcin KoÅ›cielnicki Date: Thu, 25 Feb 2010 00:54:04 +0000 Subject: drm/nouveau: Fix noaccel/nofbaccel option descriptions. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marcin KoÅ›cielnicki Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c index da3b93b84502..874adf55a43f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.c +++ b/drivers/gpu/drm/nouveau/nouveau_drv.c @@ -75,11 +75,11 @@ MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status"); int nouveau_ignorelid = 0; module_param_named(ignorelid, nouveau_ignorelid, int, 0400); -MODULE_PARM_DESC(noagp, "Disable all acceleration"); +MODULE_PARM_DESC(noaccel, "Disable all acceleration"); int nouveau_noaccel = 0; module_param_named(noaccel, nouveau_noaccel, int, 0400); -MODULE_PARM_DESC(noagp, "Disable fbcon acceleration"); +MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration"); int nouveau_nofbaccel = 0; module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400); -- cgit v1.2.3 From c52e53fd38b195169c67a8cc9ed1af0125d2655c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 25 Feb 2010 11:53:00 +1000 Subject: drm/nouveau: support version 0x20 displayport tables Not entirely identical to 0x21, the per-encoder table header lacks the third init table pointer. However, our current parsing of the table should work just fine. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index bcf843f22b7d..71247da17da5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -3726,7 +3726,7 @@ nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent, } table = &bios->data[bios->display.dp_table_ptr]; - if (table[0] != 0x21) { + if (table[0] != 0x20 && table[0] != 0x21) { NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n", table[0]); return NULL; -- cgit v1.2.3 From b30083bdb990bcc2829fce83d871a86059ff4fc1 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 25 Feb 2010 12:12:09 +1000 Subject: drm/nouveau: report unknown connector state if lid closed This is in preference to disconnected. If there's no other outputs connected this will cause LVDS to be programmed even with the lid closed rather than having X fail to start because of no available outputs. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_connector.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index dee52c81b100..24327f468c4b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -239,12 +239,14 @@ nouveau_connector_detect(struct drm_connector *connector) if (nv_connector->dcb->type == DCB_CONNECTOR_LVDS) nv_encoder = find_encoder_by_type(connector, OUTPUT_LVDS); if (nv_encoder && nv_connector->native_mode) { + unsigned status = connector_status_connected; + #ifdef CONFIG_ACPI if (!nouveau_ignorelid && !acpi_lid_open()) - return connector_status_disconnected; + status = connector_status_unknown; #endif nouveau_connector_set_encoder(connector, nv_encoder); - return connector_status_connected; + return status; } /* Cleanup the previous EDID block. */ -- cgit v1.2.3 From 3bfc7d22d0400e85a93e835d4398dcbe0af68b0b Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Wed, 24 Feb 2010 23:27:10 -0500 Subject: drm/nouveau: use ALIGN instead of open coding it CC: Ben Skeggs Signed-off-by: Matt Turner Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nv04_fbcon.c | 2 +- drivers/gpu/drm/nouveau/nv50_fbcon.c | 2 +- drivers/gpu/drm/nouveau/nv50_instmem.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index fd01caabd5c3..3da90c2c4e63 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c @@ -118,7 +118,7 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) return; } - width = (image->width + 31) & ~31; + width = ALIGN(image->width, 32); dsize = (width * image->height) >> 5; if (info->fix.visual == FB_VISUAL_TRUECOLOR || diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index 0f57cdf7ccb2..993c7126fbde 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -109,7 +109,7 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) return; } - width = (image->width + 31) & ~31; + width = ALIGN(image->width, 32); dwords = (width * image->height) >> 5; BEGIN_RING(chan, NvSub2D, 0x0814, 2); diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c index f0dc4e36ef05..de1f5b0062c5 100644 --- a/drivers/gpu/drm/nouveau/nv50_instmem.c +++ b/drivers/gpu/drm/nouveau/nv50_instmem.c @@ -390,7 +390,7 @@ nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, if (gpuobj->im_backing) return -EINVAL; - *sz = (*sz + (NV50_INSTMEM_PAGE_SIZE-1)) & ~(NV50_INSTMEM_PAGE_SIZE-1); + *sz = ALIGN(*sz, NV50_INSTMEM_PAGE_SIZE); if (*sz == 0) return -EINVAL; -- cgit v1.2.3 From bcf59e2c4dea780e4abf48d5e673f5d79f9ee064 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 23 Feb 2010 15:04:23 +0300 Subject: uwb: remove duplicate cpu_to_le16() These parameters should be passed as cpu endian because we change it to little endian inside usb_control_msg(). On x86 cpu_to_le16() doesn't do anything so either way works but I think the original code would break on big endian systems. I removed the masks as well because that usb_control_msg() parameters are __u16 so we already only use the lower bits. Signed-off-by: Dan Carpenter Signed-off-by: David Vrabel --- drivers/uwb/i1480/dfu/usb.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/uwb/i1480/dfu/usb.c b/drivers/uwb/i1480/dfu/usb.c index a6a93755627e..a99e211a1b87 100644 --- a/drivers/uwb/i1480/dfu/usb.c +++ b/drivers/uwb/i1480/dfu/usb.c @@ -120,8 +120,7 @@ int i1480_usb_write(struct i1480 *i1480, u32 memory_address, result = usb_control_msg( i1480_usb->usb_dev, usb_sndctrlpipe(i1480_usb->usb_dev, 0), 0xf0, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, - cpu_to_le16(memory_address & 0xffff), - cpu_to_le16((memory_address >> 16) & 0xffff), + memory_address, (memory_address >> 16), i1480->cmd_buf, buffer_size, 100 /* FIXME: arbitrary */); if (result < 0) break; @@ -166,8 +165,7 @@ int i1480_usb_read(struct i1480 *i1480, u32 addr, size_t size) result = usb_control_msg( i1480_usb->usb_dev, usb_rcvctrlpipe(i1480_usb->usb_dev, 0), 0xf0, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, - cpu_to_le16(itr_addr & 0xffff), - cpu_to_le16((itr_addr >> 16) & 0xffff), + itr_addr, (itr_addr >> 16), i1480->cmd_buf + itr, itr_size, 100 /* FIXME: arbitrary */); if (result < 0) { -- cgit v1.2.3 From 1089e3009572e07a1fe12c3408828f27c96453be Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 22 Oct 2009 16:10:52 -0700 Subject: agp/intel: Add support for Sandybridge. Signed-off-by: Eric Anholt --- drivers/char/agp/intel-agp.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index e5ffefee34a0..df85ed9c7531 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c @@ -64,6 +64,8 @@ #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 +#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 +#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102 /* cover 915 and 945 variants */ #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ @@ -98,7 +100,8 @@ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \ - agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB) + agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \ + agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) extern int agp_memory_reserved; @@ -705,6 +708,12 @@ static void intel_i830_init_gtt_entries(void) gtt_entries = 0; break; } + } else if (agp_bridge->dev->device == + PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) { + /* XXX: This is what my A1 silicon has. What's the right + * answer? + */ + gtt_entries = MB(64) - KB(size); } else { switch (gmch_ctrl & I855_GMCH_GMS_MASK) { case I855_GMCH_GMS_STOLEN_1M: @@ -1364,6 +1373,7 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB: case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB: case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB: + case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB: *gtt_offset = *gtt_size = MB(2); break; default: @@ -2369,6 +2379,8 @@ static const struct intel_driver_description { "HD Graphics", NULL, &intel_i965_driver }, { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, "HD Graphics", NULL, &intel_i965_driver }, + { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG, 0, + "Sandybridge", NULL, &intel_i965_driver }, { 0, 0, 0, NULL, NULL, NULL } }; @@ -2575,6 +2587,7 @@ static struct pci_device_id agp_intel_pci_table[] = { ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB), ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB), ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB), + ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB), { } }; -- cgit v1.2.3 From bad720ff3e8e47a04bd88d9bbc8317e7d7e049d3 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 22 Oct 2009 16:11:14 -0700 Subject: drm/i915: Add initial bits for VGA modesetting bringup on Sandybridge. Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_dma.c | 16 +++++++--- drivers/gpu/drm/i915/i915_drv.h | 26 +++++++++++++++- drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_gem_tiling.c | 2 +- drivers/gpu/drm/i915/i915_irq.c | 18 +++++------ drivers/gpu/drm/i915/intel_bios.c | 3 +- drivers/gpu/drm/i915/intel_crt.c | 14 ++++----- drivers/gpu/drm/i915/intel_display.c | 56 +++++++++++++++++----------------- drivers/gpu/drm/i915/intel_lvds.c | 2 +- drivers/gpu/drm/i915/intel_overlay.c | 2 +- include/drm/drm_pciids.h | 1 + 12 files changed, 88 insertions(+), 56 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 5eed46312442..1376dfe44c95 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -162,7 +162,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) struct drm_device *dev = node->minor->dev; drm_i915_private_t *dev_priv = dev->dev_private; - if (!IS_IRONLAKE(dev)) { + if (!HAS_PCH_SPLIT(dev)) { seq_printf(m, "Interrupt enable: %08x\n", I915_READ(IER)); seq_printf(m, "Interrupt identity: %08x\n", diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index dbfe07c90cbc..7bfded5e90bb 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1094,15 +1094,21 @@ static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, * Some of the preallocated space is taken by the GTT * and popup. GTT is 1K per MB of aperture size, and popup is 4K. */ - if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev)) + if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) overhead = 4096; else overhead = (*aperture_size / 1024) + 4096; switch (tmp & INTEL_GMCH_GMS_MASK) { case INTEL_855_GMCH_GMS_DISABLED: - DRM_ERROR("video memory is disabled\n"); - return -1; + /* XXX: This is what my A1 silicon has. */ + if (IS_GEN6(dev)) { + stolen = 64 * 1024 * 1024; + } else { + DRM_ERROR("video memory is disabled\n"); + return -1; + } + break; case INTEL_855_GMCH_GMS_STOLEN_1M: stolen = 1 * 1024 * 1024; break; @@ -1180,7 +1186,7 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev, int gtt_offset, gtt_size; if (IS_I965G(dev)) { - if (IS_G4X(dev) || IS_IRONLAKE(dev)) { + if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) { gtt_offset = 2*1024*1024; gtt_size = 2*1024*1024; } else { @@ -1563,7 +1569,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) dev->driver->get_vblank_counter = i915_get_vblank_counter; dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ - if (IS_G4X(dev) || IS_IRONLAKE(dev)) { + if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) { dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ dev->driver->get_vblank_counter = gm45_get_vblank_counter; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ec06d4865a5f..f97592609da4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1065,7 +1065,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define IS_845G(dev) ((dev)->pci_device == 0x2562) #define IS_I85X(dev) ((dev)->pci_device == 0x3582) #define IS_I865G(dev) ((dev)->pci_device == 0x2572) -#define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx) +#define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx) #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) #define IS_I945G(dev) ((dev)->pci_device == 0x2772) @@ -1084,8 +1084,29 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) +#define IS_GEN3(dev) (IS_I915G(dev) || \ + IS_I915GM(dev) || \ + IS_I945G(dev) || \ + IS_I945GM(dev) || \ + IS_G33(dev) || \ + IS_PINEVIEW(dev)) +#define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \ + (dev)->pci_device == 0x2982 || \ + (dev)->pci_device == 0x2992 || \ + (dev)->pci_device == 0x29A2 || \ + (dev)->pci_device == 0x2A02 || \ + (dev)->pci_device == 0x2A12 || \ + (dev)->pci_device == 0x2E02 || \ + (dev)->pci_device == 0x2E12 || \ + (dev)->pci_device == 0x2E22 || \ + (dev)->pci_device == 0x2E32 || \ + (dev)->pci_device == 0x2A42 || \ + (dev)->pci_device == 0x2E42) + #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) +#define IS_GEN6(dev) ((dev)->pci_device == 0x0102) + /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte * rows, which changed the alignment requirements and fence programming. */ @@ -1106,6 +1127,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) +#define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \ + IS_GEN6(dev)) + #define PRIMARY_RINGBUFFER_SIZE (128*1024) #endif diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index b5df30ca0fa2..a35dc8c0882b 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1818,7 +1818,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible) return -EIO; if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) { - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) ier = I915_READ(DEIER) | I915_READ(GTIER); else ier = I915_READ(IER); diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index 20653776965a..b5c55d88ff76 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -92,7 +92,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; - if (IS_IRONLAKE(dev)) { + if (IS_IRONLAKE(dev) || IS_GEN6(dev)) { /* On Ironlake whatever DRAM config, GPU always do * same swizzling setup. */ diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index ba1d8314c1ce..ef79d9423f0a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -842,7 +842,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) atomic_inc(&dev_priv->irq_received); - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) return ironlake_irq_handler(dev); iir = I915_READ(IIR); @@ -1003,7 +1003,7 @@ void i915_user_irq_get(struct drm_device *dev) spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); else i915_enable_irq(dev_priv, I915_USER_INTERRUPT); @@ -1019,7 +1019,7 @@ void i915_user_irq_put(struct drm_device *dev) spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); else i915_disable_irq(dev_priv, I915_USER_INTERRUPT); @@ -1127,7 +1127,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe) return -EINVAL; spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) ironlake_enable_display_irq(dev_priv, (pipe == 0) ? DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); else if (IS_I965G(dev)) @@ -1149,7 +1149,7 @@ void i915_disable_vblank(struct drm_device *dev, int pipe) unsigned long irqflags; spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) ironlake_disable_display_irq(dev_priv, (pipe == 0) ? DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); else @@ -1163,7 +1163,7 @@ void i915_enable_interrupt (struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (!IS_IRONLAKE(dev)) + if (!HAS_PCH_SPLIT(dev)) opregion_enable_asle(dev); dev_priv->irq_enabled = 1; } @@ -1349,7 +1349,7 @@ void i915_driver_irq_preinstall(struct drm_device * dev) INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); INIT_WORK(&dev_priv->error_work, i915_error_work_func); - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { ironlake_irq_preinstall(dev); return; } @@ -1381,7 +1381,7 @@ int i915_driver_irq_postinstall(struct drm_device *dev) dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) return ironlake_irq_postinstall(dev); /* Unmask the interrupts that we always want on. */ @@ -1469,7 +1469,7 @@ void i915_driver_irq_uninstall(struct drm_device * dev) dev_priv->vblank_pipe = 0; - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { ironlake_irq_uninstall(dev); return; } diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 15fbc1b5a83e..70c9d4ba7042 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -247,6 +247,7 @@ static void parse_general_features(struct drm_i915_private *dev_priv, struct bdb_header *bdb) { + struct drm_device *dev = dev_priv->dev; struct bdb_general_features *general; /* Set sensible defaults in case we can't find the general block */ @@ -263,7 +264,7 @@ parse_general_features(struct drm_i915_private *dev_priv, if (IS_I85X(dev_priv->dev)) dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48; - else if (IS_IRONLAKE(dev_priv->dev)) + else if (IS_IRONLAKE(dev_priv->dev) || IS_GEN6(dev)) dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 120; else diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 79dd4026586f..fccf07470c8f 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -39,7 +39,7 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode) struct drm_i915_private *dev_priv = dev->dev_private; u32 temp, reg; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) reg = PCH_ADPA; else reg = ADPA; @@ -113,7 +113,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder, else dpll_md_reg = DPLL_B_MD; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) adpa_reg = PCH_ADPA; else adpa_reg = ADPA; @@ -122,7 +122,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder, * Disable separate mode multiplier used when cloning SDVO to CRT * XXX this needs to be adjusted when we really are cloning */ - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) { + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { dpll_md = I915_READ(dpll_md_reg); I915_WRITE(dpll_md_reg, dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); @@ -136,11 +136,11 @@ static void intel_crt_mode_set(struct drm_encoder *encoder, if (intel_crtc->pipe == 0) { adpa |= ADPA_PIPE_A_SELECT; - if (!IS_IRONLAKE(dev)) + if (!HAS_PCH_SPLIT(dev)) I915_WRITE(BCLRPAT_A, 0); } else { adpa |= ADPA_PIPE_B_SELECT; - if (!IS_IRONLAKE(dev)) + if (!HAS_PCH_SPLIT(dev)) I915_WRITE(BCLRPAT_B, 0); } @@ -202,7 +202,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) u32 hotplug_en; int i, tries = 0; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) return intel_ironlake_crt_detect_hotplug(connector); /* @@ -524,7 +524,7 @@ void intel_crt_init(struct drm_device *dev) &intel_output->enc); /* Set up the DDC bus. */ - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) i2c_reg = PCH_GPIOA; else { i2c_reg = GPIOA; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1b5cd833bc70..ce28f18e0852 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -232,7 +232,7 @@ struct intel_limit { #define G4X_P2_DISPLAY_PORT_FAST 10 #define G4X_P2_DISPLAY_PORT_LIMIT 0 -/* Ironlake */ +/* Ironlake / Sandybridge */ /* as we calculate clock using (register_value + 2) for N/M1/M2, so here the range value for them is (actual_value-2). */ @@ -690,7 +690,7 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc) struct drm_device *dev = crtc->dev; const intel_limit_t *limit; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) limit = intel_ironlake_limit(crtc); else if (IS_G4X(dev)) { limit = intel_g4x_limit(crtc); @@ -1371,7 +1371,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, dspcntr &= ~DISPPLANE_TILED; } - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) /* must disable */ dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; @@ -1432,7 +1432,7 @@ static void i915_disable_vga (struct drm_device *dev) u8 sr1; u32 vga_reg; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) vga_reg = CPU_VGACNTRL; else vga_reg = VGACNTRL; @@ -2116,7 +2116,7 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *adjusted_mode) { struct drm_device *dev = crtc->dev; - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { /* FDI link clock is fixed at 2.7G */ if (mode->clock * 3 > 27000 * 4) return MODE_CLOCK_HIGH; @@ -2983,7 +2983,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, refclk / 1000); } else if (IS_I9XX(dev)) { refclk = 96000; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) refclk = 120000; /* 120Mhz refclk */ } else { refclk = 48000; @@ -3041,7 +3041,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, } /* FDI link */ - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { int lane, link_bw, bpp; /* eDP doesn't require FDI link, so just set DP M/N according to current link config */ @@ -3118,7 +3118,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, * PCH B stepping, previous chipset stepping should be * ignoring this setting. */ - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { temp = I915_READ(PCH_DREF_CONTROL); /* Always enable nonspread source */ temp &= ~DREF_NONSPREAD_SOURCE_MASK; @@ -3165,7 +3165,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, reduced_clock.m2; } - if (!IS_IRONLAKE(dev)) + if (!HAS_PCH_SPLIT(dev)) dpll = DPLL_VGA_MODE_DIS; if (IS_I9XX(dev)) { @@ -3178,7 +3178,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; - else if (IS_IRONLAKE(dev)) + else if (HAS_PCH_SPLIT(dev)) dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; } if (is_dp) @@ -3190,7 +3190,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, else { dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; /* also FPA1 */ - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; if (IS_G4X(dev) && has_reduced_clock) dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; @@ -3209,7 +3209,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; break; } - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); } else { if (is_lvds) { @@ -3243,7 +3243,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, /* Ironlake's plane is forced to pipe, bit 24 is to enable color space conversion */ - if (!IS_IRONLAKE(dev)) { + if (!HAS_PCH_SPLIT(dev)) { if (pipe == 0) dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; else @@ -3270,14 +3270,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, /* Disable the panel fitter if it was on our pipe */ - if (!IS_IRONLAKE(dev) && intel_panel_fitter_pipe(dev) == pipe) + if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe) I915_WRITE(PFIT_CONTROL, 0); DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); drm_mode_debug_printmodeline(mode); /* assign to Ironlake registers */ - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { fp_reg = pch_fp_reg; dpll_reg = pch_dpll_reg; } @@ -3298,7 +3298,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, if (is_lvds) { u32 lvds; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) lvds_reg = PCH_LVDS; lvds = I915_READ(lvds_reg); @@ -3344,7 +3344,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, /* Wait for the clocks to stabilize. */ udelay(150); - if (IS_I965G(dev) && !IS_IRONLAKE(dev)) { + if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { if (is_sdvo) { sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | @@ -3391,14 +3391,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, /* pipesrc and dspsize control the size that is scaled from, which should * always be the user's requested size. */ - if (!IS_IRONLAKE(dev)) { + if (!HAS_PCH_SPLIT(dev)) { I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); I915_WRITE(dsppos_reg, 0); } I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m); I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n); I915_WRITE(link_m1_reg, m_n.link_m); @@ -3419,7 +3419,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, intel_wait_for_vblank(dev); - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { /* enable address swizzle for tiling buffer */ temp = I915_READ(DISP_ARB_CTL); I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); @@ -3454,7 +3454,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc) return; /* use legacy palette for Ironlake */ - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : LGC_PALETTE_B; @@ -3937,7 +3937,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule) int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; int dpll = I915_READ(dpll_reg); - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) return; if (!dev_priv->lvds_downclock_avail) @@ -3976,7 +3976,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc) int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; int dpll = I915_READ(dpll_reg); - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) return; if (!dev_priv->lvds_downclock_avail) @@ -4418,7 +4418,7 @@ static void intel_setup_outputs(struct drm_device *dev) if (IS_MOBILE(dev) && !IS_I830(dev)) intel_lvds_init(dev); - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { int found; if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED)) @@ -4487,7 +4487,7 @@ static void intel_setup_outputs(struct drm_device *dev) DRM_DEBUG_KMS("probing DP_D\n"); intel_dp_init(dev, DP_D); } - } else if (IS_I8XX(dev)) + } else if (IS_GEN2(dev)) intel_dvo_init(dev); if (SUPPORTS_TV(dev)) @@ -4716,7 +4716,7 @@ void intel_init_clock_gating(struct drm_device *dev) * Disable clock gating reported to work incorrectly according to the * specs, but enable as much else as we can. */ - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { return; } else if (IS_G4X(dev)) { uint32_t dspclk_gate; @@ -4789,7 +4789,7 @@ static void intel_init_display(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; /* We always want a DPMS function */ - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) dev_priv->display.dpms = ironlake_crtc_dpms; else dev_priv->display.dpms = i9xx_crtc_dpms; @@ -4832,7 +4832,7 @@ static void intel_init_display(struct drm_device *dev) i830_get_display_clock_speed; /* For FIFO watermark updates */ - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) dev_priv->display.update_wm = NULL; else if (IS_G4X(dev)) dev_priv->display.update_wm = g4x_update_wm; diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 93031a75d112..e91e81de5c71 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -661,7 +661,7 @@ static enum drm_connector_status intel_lvds_detect(struct drm_connector *connect /* ACPI lid methods were generally unreliable in this generation, so * don't even bother. */ - if (IS_I8XX(dev)) + if (IS_GEN2(dev)) return connector_status_connected; if (!dmi_check_system(bad_lid_status) && !acpi_lid_open()) diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index c3fa406912b3..d355d1d527e7 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -172,7 +172,7 @@ struct overlay_registers { #define OFC_UPDATE 0x1 #define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev)) -#define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev)) +#define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev) && !IS_GEN6(dev)) static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay) diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h index 403490c7b647..676104b7818c 100644 --- a/include/drm/drm_pciids.h +++ b/include/drm/drm_pciids.h @@ -593,4 +593,5 @@ {0x8086, 0x35e8, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0x8086, 0x0042, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0x8086, 0x0046, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x0102, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0, 0, 0} -- cgit v1.2.3 From 4e901fdc263d32d4cb4c59ec16ff0874129ec8c9 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 26 Oct 2009 16:44:17 -0700 Subject: drm/i915: Set up fence registers on sandybridge. Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_gem.c | 33 ++++++++++++++++++++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 33 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a35dc8c0882b..715eaac62dbd 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2261,6 +2261,28 @@ i915_gem_object_get_pages(struct drm_gem_object *obj, return 0; } +static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) +{ + struct drm_gem_object *obj = reg->obj; + struct drm_device *dev = obj->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + struct drm_i915_gem_object *obj_priv = obj->driver_private; + int regnum = obj_priv->fence_reg; + uint64_t val; + + val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & + 0xfffff000) << 32; + val |= obj_priv->gtt_offset & 0xfffff000; + val |= (uint64_t)((obj_priv->stride / 128) - 1) << + SANDYBRIDGE_FENCE_PITCH_SHIFT; + + if (obj_priv->tiling_mode == I915_TILING_Y) + val |= 1 << I965_FENCE_TILING_Y_SHIFT; + val |= I965_FENCE_REG_VALID; + + I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); +} + static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) { struct drm_gem_object *obj = reg->obj; @@ -2478,7 +2500,9 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj) reg->obj = obj; - if (IS_I965G(dev)) + if (IS_GEN6(dev)) + sandybridge_write_fence_reg(reg); + else if (IS_I965G(dev)) i965_write_fence_reg(reg); else if (IS_I9XX(dev)) i915_write_fence_reg(reg); @@ -2504,9 +2528,12 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj) drm_i915_private_t *dev_priv = dev->dev_private; struct drm_i915_gem_object *obj_priv = obj->driver_private; - if (IS_I965G(dev)) + if (IS_GEN6(dev)) { + I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + + (obj_priv->fence_reg * 8), 0); + } else if (IS_I965G(dev)) { I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); - else { + } else { uint32_t fence_reg; if (obj_priv->fence_reg < 8) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eff8d850a758..1232229450e7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -235,6 +235,9 @@ #define I965_FENCE_REG_VALID (1<<0) #define I965_FENCE_MAX_PITCH_VAL 0x0400 +#define FENCE_REG_SANDYBRIDGE_0 0x100000 +#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 + /* * Instruction and interrupt control regs */ -- cgit v1.2.3 From f6e450a6417460db6a74241de8aaab5116cac140 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 2 Nov 2009 12:08:22 -0800 Subject: drm/i915: Fix sandybridge status page setup. The register's moved to the same location as the one for the BCS, it seems. Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_drv.c | 7 +++++++ drivers/gpu/drm/i915/i915_gem.c | 9 +++++++-- drivers/gpu/drm/i915/i915_reg.h | 1 + 3 files changed, 15 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 742bd8f738ca..b57efca02901 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -136,6 +136,12 @@ const static struct intel_device_info intel_ironlake_m_info = { .has_hotplug = 1, }; +const static struct intel_device_info intel_sandybridge_d_info = { + .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1, + .has_pipe_cxsr = 1, + .has_hotplug = 1, +}; + const static struct pci_device_id pciidlist[] = { INTEL_VGA_DEVICE(0x3577, &intel_i830_info), INTEL_VGA_DEVICE(0x2562, &intel_845g_info), @@ -167,6 +173,7 @@ const static struct pci_device_id pciidlist[] = { INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), + INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), {0, 0, 0} }; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 715eaac62dbd..c73da4049c81 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4581,8 +4581,13 @@ i915_gem_init_hws(struct drm_device *dev) } dev_priv->hws_obj = obj; memset(dev_priv->hw_status_page, 0, PAGE_SIZE); - I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); - I915_READ(HWS_PGA); /* posting read */ + if (IS_GEN6(dev)) { + I915_WRITE(HWS_PGA_GEN6, dev_priv->status_gfx_addr); + I915_READ(HWS_PGA_GEN6); /* posting read */ + } else { + I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); + I915_READ(HWS_PGA); /* posting read */ + } DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr); return 0; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1232229450e7..2a312b674a72 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -269,6 +269,7 @@ #define INSTDONE1 0x0207c /* 965+ only */ #define ACTHD_I965 0x02074 #define HWS_PGA 0x02080 +#define HWS_PGA_GEN6 0x04080 #define HWS_ADDRESS_MASK 0xfffff000 #define HWS_START_ADDRESS_SHIFT 4 #define PWRCTXA 0x2088 /* 965GM+ only */ -- cgit v1.2.3 From e3deb204c69c485c88c990f07b71be10a464e508 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 2 Nov 2009 15:33:05 -0800 Subject: agp/intel: Use a non-reserved value for the cache field of the PTEs. I don't know if this is what we'll want to be using long term, we'll see. Signed-off-by: Eric Anholt --- drivers/char/agp/intel-agp.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index df85ed9c7531..c3c870bf5678 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c @@ -296,6 +296,11 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem, off_t pg_start, int mask_type) { int i, j; + u32 cache_bits = 0; + + if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) { + cache_bits = I830_PTE_SYSTEM_CACHED; + } for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { writel(agp_bridge->driver->mask_memory(agp_bridge, -- cgit v1.2.3 From c2416fc6bb16fa87bcc4b9d90a7632f3531bdee6 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 5 Nov 2009 15:30:35 -0800 Subject: drm/i915: Disable the surface tile swizzling on Sandybridge. I can't explain this, except that it makes my display correct. Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ce28f18e0852..3fe90730b0ff 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3419,7 +3419,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, intel_wait_for_vblank(dev); - if (HAS_PCH_SPLIT(dev)) { + if (IS_IRONLAKE(dev)) { /* enable address swizzle for tiling buffer */ temp = I915_READ(DISP_ARB_CTL); I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); -- cgit v1.2.3 From 21099537dbacc5c8999d833e6bfd1b72edd89189 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 9 Nov 2009 14:57:34 -0800 Subject: drm/i915: Correct locking in the modesetting failure path, fixing a BUG_ON. Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_dma.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 7bfded5e90bb..281faca3e37c 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1405,7 +1405,9 @@ static int i915_load_modeset_init(struct drm_device *dev, return 0; destroy_ringbuffer: + mutex_lock(&dev->struct_mutex); i915_gem_cleanup_ringbuffer(dev); + mutex_unlock(&dev->struct_mutex); out: return ret; } -- cgit v1.2.3 From 14bc490bbdf1b194ad1f5f3d2a0a27edfdf78986 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Wed, 11 Nov 2009 01:25:25 +0800 Subject: drm/i915, agp/intel: Fix stolen memory size on Sandybridge New memory control config reg at 0x50 should be used for stolen memory size detection on Sandybridge. Signed-off-by: Zhenyu Wang Signed-off-by: Eric Anholt --- drivers/char/agp/intel-agp.c | 78 ++++++++++++++++++-- drivers/gpu/drm/i915/i915_dma.c | 156 +++++++++++++++++++++++++++------------- drivers/gpu/drm/i915/i915_reg.h | 19 +++++ 3 files changed, 200 insertions(+), 53 deletions(-) (limited to 'drivers') diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index c3c870bf5678..9a551bc34c39 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c @@ -150,6 +150,25 @@ extern int agp_memory_reserved; #define INTEL_I7505_AGPCTRL 0x70 #define INTEL_I7505_MCHCFG 0x50 +#define SNB_GMCH_CTRL 0x50 +#define SNB_GMCH_GMS_STOLEN_MASK 0xF8 +#define SNB_GMCH_GMS_STOLEN_32M (1 << 3) +#define SNB_GMCH_GMS_STOLEN_64M (2 << 3) +#define SNB_GMCH_GMS_STOLEN_96M (3 << 3) +#define SNB_GMCH_GMS_STOLEN_128M (4 << 3) +#define SNB_GMCH_GMS_STOLEN_160M (5 << 3) +#define SNB_GMCH_GMS_STOLEN_192M (6 << 3) +#define SNB_GMCH_GMS_STOLEN_224M (7 << 3) +#define SNB_GMCH_GMS_STOLEN_256M (8 << 3) +#define SNB_GMCH_GMS_STOLEN_288M (9 << 3) +#define SNB_GMCH_GMS_STOLEN_320M (0xa << 3) +#define SNB_GMCH_GMS_STOLEN_352M (0xb << 3) +#define SNB_GMCH_GMS_STOLEN_384M (0xc << 3) +#define SNB_GMCH_GMS_STOLEN_416M (0xd << 3) +#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) +#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) +#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) + static const struct aper_size_info_fixed intel_i810_sizes[] = { {64, 16384, 4}, @@ -621,7 +640,7 @@ static struct aper_size_info_fixed intel_i830_sizes[] = static void intel_i830_init_gtt_entries(void) { u16 gmch_ctrl; - int gtt_entries; + int gtt_entries = 0; u8 rdct; int local = 0; static const int ddt[4] = { 0, 16, 32, 64 }; @@ -715,10 +734,61 @@ static void intel_i830_init_gtt_entries(void) } } else if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) { - /* XXX: This is what my A1 silicon has. What's the right - * answer? + /* + * SandyBridge has new memory control reg at 0x50.w */ - gtt_entries = MB(64) - KB(size); + u16 snb_gmch_ctl; + pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); + switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { + case SNB_GMCH_GMS_STOLEN_32M: + gtt_entries = MB(32) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_64M: + gtt_entries = MB(64) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_96M: + gtt_entries = MB(96) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_128M: + gtt_entries = MB(128) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_160M: + gtt_entries = MB(160) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_192M: + gtt_entries = MB(192) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_224M: + gtt_entries = MB(224) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_256M: + gtt_entries = MB(256) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_288M: + gtt_entries = MB(288) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_320M: + gtt_entries = MB(320) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_352M: + gtt_entries = MB(352) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_384M: + gtt_entries = MB(384) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_416M: + gtt_entries = MB(416) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_448M: + gtt_entries = MB(448) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_480M: + gtt_entries = MB(480) - KB(size); + break; + case SNB_GMCH_GMS_STOLEN_512M: + gtt_entries = MB(512) - KB(size); + break; + } } else { switch (gmch_ctrl & I855_GMCH_GMS_MASK) { case I855_GMCH_GMS_STOLEN_1M: diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 281faca3e37c..3e658d6a6b7d 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1099,60 +1099,118 @@ static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, else overhead = (*aperture_size / 1024) + 4096; - switch (tmp & INTEL_GMCH_GMS_MASK) { - case INTEL_855_GMCH_GMS_DISABLED: - /* XXX: This is what my A1 silicon has. */ - if (IS_GEN6(dev)) { + if (IS_GEN6(dev)) { + /* SNB has memory control reg at 0x50.w */ + pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp); + + switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) { + case INTEL_855_GMCH_GMS_DISABLED: + DRM_ERROR("video memory is disabled\n"); + return -1; + case SNB_GMCH_GMS_STOLEN_32M: + stolen = 32 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_64M: stolen = 64 * 1024 * 1024; - } else { + break; + case SNB_GMCH_GMS_STOLEN_96M: + stolen = 96 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_128M: + stolen = 128 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_160M: + stolen = 160 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_192M: + stolen = 192 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_224M: + stolen = 224 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_256M: + stolen = 256 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_288M: + stolen = 288 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_320M: + stolen = 320 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_352M: + stolen = 352 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_384M: + stolen = 384 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_416M: + stolen = 416 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_448M: + stolen = 448 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_480M: + stolen = 480 * 1024 * 1024; + break; + case SNB_GMCH_GMS_STOLEN_512M: + stolen = 512 * 1024 * 1024; + break; + default: + DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", + tmp & SNB_GMCH_GMS_STOLEN_MASK); + return -1; + } + } else { + switch (tmp & INTEL_GMCH_GMS_MASK) { + case INTEL_855_GMCH_GMS_DISABLED: DRM_ERROR("video memory is disabled\n"); return -1; + case INTEL_855_GMCH_GMS_STOLEN_1M: + stolen = 1 * 1024 * 1024; + break; + case INTEL_855_GMCH_GMS_STOLEN_4M: + stolen = 4 * 1024 * 1024; + break; + case INTEL_855_GMCH_GMS_STOLEN_8M: + stolen = 8 * 1024 * 1024; + break; + case INTEL_855_GMCH_GMS_STOLEN_16M: + stolen = 16 * 1024 * 1024; + break; + case INTEL_855_GMCH_GMS_STOLEN_32M: + stolen = 32 * 1024 * 1024; + break; + case INTEL_915G_GMCH_GMS_STOLEN_48M: + stolen = 48 * 1024 * 1024; + break; + case INTEL_915G_GMCH_GMS_STOLEN_64M: + stolen = 64 * 1024 * 1024; + break; + case INTEL_GMCH_GMS_STOLEN_128M: + stolen = 128 * 1024 * 1024; + break; + case INTEL_GMCH_GMS_STOLEN_256M: + stolen = 256 * 1024 * 1024; + break; + case INTEL_GMCH_GMS_STOLEN_96M: + stolen = 96 * 1024 * 1024; + break; + case INTEL_GMCH_GMS_STOLEN_160M: + stolen = 160 * 1024 * 1024; + break; + case INTEL_GMCH_GMS_STOLEN_224M: + stolen = 224 * 1024 * 1024; + break; + case INTEL_GMCH_GMS_STOLEN_352M: + stolen = 352 * 1024 * 1024; + break; + default: + DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", + tmp & INTEL_GMCH_GMS_MASK); + return -1; } - break; - case INTEL_855_GMCH_GMS_STOLEN_1M: - stolen = 1 * 1024 * 1024; - break; - case INTEL_855_GMCH_GMS_STOLEN_4M: - stolen = 4 * 1024 * 1024; - break; - case INTEL_855_GMCH_GMS_STOLEN_8M: - stolen = 8 * 1024 * 1024; - break; - case INTEL_855_GMCH_GMS_STOLEN_16M: - stolen = 16 * 1024 * 1024; - break; - case INTEL_855_GMCH_GMS_STOLEN_32M: - stolen = 32 * 1024 * 1024; - break; - case INTEL_915G_GMCH_GMS_STOLEN_48M: - stolen = 48 * 1024 * 1024; - break; - case INTEL_915G_GMCH_GMS_STOLEN_64M: - stolen = 64 * 1024 * 1024; - break; - case INTEL_GMCH_GMS_STOLEN_128M: - stolen = 128 * 1024 * 1024; - break; - case INTEL_GMCH_GMS_STOLEN_256M: - stolen = 256 * 1024 * 1024; - break; - case INTEL_GMCH_GMS_STOLEN_96M: - stolen = 96 * 1024 * 1024; - break; - case INTEL_GMCH_GMS_STOLEN_160M: - stolen = 160 * 1024 * 1024; - break; - case INTEL_GMCH_GMS_STOLEN_224M: - stolen = 224 * 1024 * 1024; - break; - case INTEL_GMCH_GMS_STOLEN_352M: - stolen = 352 * 1024 * 1024; - break; - default: - DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n", - tmp & INTEL_GMCH_GMS_MASK); - return -1; } + *preallocated_size = stolen - overhead; *start = overhead; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2a312b674a72..3d59862c7ccd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -53,6 +53,25 @@ #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) +#define SNB_GMCH_CTRL 0x50 +#define SNB_GMCH_GMS_STOLEN_MASK 0xF8 +#define SNB_GMCH_GMS_STOLEN_32M (1 << 3) +#define SNB_GMCH_GMS_STOLEN_64M (2 << 3) +#define SNB_GMCH_GMS_STOLEN_96M (3 << 3) +#define SNB_GMCH_GMS_STOLEN_128M (4 << 3) +#define SNB_GMCH_GMS_STOLEN_160M (5 << 3) +#define SNB_GMCH_GMS_STOLEN_192M (6 << 3) +#define SNB_GMCH_GMS_STOLEN_224M (7 << 3) +#define SNB_GMCH_GMS_STOLEN_256M (8 << 3) +#define SNB_GMCH_GMS_STOLEN_288M (9 << 3) +#define SNB_GMCH_GMS_STOLEN_320M (0xa << 3) +#define SNB_GMCH_GMS_STOLEN_352M (0xb << 3) +#define SNB_GMCH_GMS_STOLEN_384M (0xc << 3) +#define SNB_GMCH_GMS_STOLEN_416M (0xd << 3) +#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) +#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) +#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) + /* PCI config space */ #define HPLLCC 0xc0 /* 855 only */ -- cgit v1.2.3 From 954bce507acdcb76520b2f30535400fc036e7c20 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 7 Jan 2010 16:21:46 -0800 Subject: agp/intel: Add a new Sandybridge HB/IG PCI ID combo. Signed-off-by: Eric Anholt --- drivers/char/agp/intel-agp.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index 9a551bc34c39..918e484f41b7 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c @@ -66,6 +66,8 @@ #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102 +#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 +#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG 0x0106 /* cover 915 and 945 variants */ #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ @@ -101,7 +103,8 @@ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \ - agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) + agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \ + agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) extern int agp_memory_reserved; @@ -317,7 +320,9 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem, int i, j; u32 cache_bits = 0; - if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) { + if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || + agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) + { cache_bits = I830_PTE_SYSTEM_CACHED; } @@ -732,8 +737,8 @@ static void intel_i830_init_gtt_entries(void) gtt_entries = 0; break; } - } else if (agp_bridge->dev->device == - PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) { + } else if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || + agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) { /* * SandyBridge has new memory control reg at 0x50.w */ @@ -1449,6 +1454,7 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB: case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB: case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB: + case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB: *gtt_offset = *gtt_size = MB(2); break; default: @@ -2456,6 +2462,8 @@ static const struct intel_driver_description { "HD Graphics", NULL, &intel_i965_driver }, { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG, 0, "Sandybridge", NULL, &intel_i965_driver }, + { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG, 0, + "Sandybridge", NULL, &intel_i965_driver }, { 0, 0, 0, NULL, NULL, NULL } }; @@ -2663,6 +2671,7 @@ static struct pci_device_id agp_intel_pci_table[] = { ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB), ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB), ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB), + ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB), { } }; -- cgit v1.2.3 From a13e4093cbd3db91cc65ac8b8c2baadffa603ee9 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 7 Jan 2010 15:08:18 -0800 Subject: drm/i915: Add a new mobile Sandybridge PCI ID. Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_drv.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b57efca02901..94e74a426ef9 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -142,6 +142,12 @@ const static struct intel_device_info intel_sandybridge_d_info = { .has_hotplug = 1, }; +const static struct intel_device_info intel_sandybridge_m_info = { + .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1, + .has_pipe_cxsr = 1, + .has_hotplug = 1, +}; + const static struct pci_device_id pciidlist[] = { INTEL_VGA_DEVICE(0x3577, &intel_i830_info), INTEL_VGA_DEVICE(0x2562, &intel_845g_info), @@ -174,6 +180,7 @@ const static struct pci_device_id pciidlist[] = { INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), + INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), {0, 0, 0} }; -- cgit v1.2.3 From b9201c14d9c22fb3b3f313f69ee4f967353ca960 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 8 Jan 2010 14:25:16 -0800 Subject: drm/i915: Disable the hangcheck reset on Sandybridge until we add support. Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_irq.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index ef79d9423f0a..f93f822fa72c 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1239,7 +1239,11 @@ void i915_hangcheck_elapsed(unsigned long data) struct drm_device *dev = (struct drm_device *)data; drm_i915_private_t *dev_priv = dev->dev_private; uint32_t acthd; - + + /* No reset support on this chip yet. */ + if (IS_GEN6(dev)) + return; + if (!IS_I965G(dev)) acthd = I915_READ(ACTHD); else -- cgit v1.2.3 From faa7bde6cb1227d13d011042f17bda0869c3bd1e Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 28 Jan 2010 16:13:29 -0800 Subject: drm/i915: Correct the Sandybridge chipset info structs. Disables CXSR until it's done, and sets the mobile bit on mobile. Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_drv.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 94e74a426ef9..2a9178bb2748 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -138,13 +138,11 @@ const static struct intel_device_info intel_ironlake_m_info = { const static struct intel_device_info intel_sandybridge_d_info = { .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1, - .has_pipe_cxsr = 1, .has_hotplug = 1, }; const static struct intel_device_info intel_sandybridge_m_info = { - .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1, - .has_pipe_cxsr = 1, + .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1, .need_gfx_hws = 1, .has_hotplug = 1, }; -- cgit v1.2.3 From c619eed4b2ee1b2bde3e02464eb81632a08bb976 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 28 Jan 2010 16:45:52 -0800 Subject: drm/i915: More s/IS_IRONLAKE/HAS_PCH_SPLIT for Sandybridge. I think this is pretty much correct. Not really tested. Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_irq.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 6 +++--- drivers/gpu/drm/i915/intel_dp.c | 6 +++--- drivers/gpu/drm/i915/intel_hdmi.c | 4 ++-- drivers/gpu/drm/i915/intel_i2c.c | 2 +- drivers/gpu/drm/i915/intel_lvds.c | 24 ++++++++++++------------ 6 files changed, 22 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index f93f822fa72c..5388354da0d1 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -166,7 +166,7 @@ void intel_enable_asle (struct drm_device *dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) ironlake_enable_display_irq(dev_priv, DE_GSE); else i915_enable_pipestat(dev_priv, 1, diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3fe90730b0ff..9cd6de5f9906 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -886,7 +886,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { int lvds_reg; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) lvds_reg = PCH_LVDS; else lvds_reg = LVDS; @@ -3320,12 +3320,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, /* set the dithering flag */ if (IS_I965G(dev)) { if (dev_priv->lvds_dither) { - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) pipeconf |= PIPE_ENABLE_DITHER; else lvds |= LVDS_ENABLE_DITHER; } else { - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) pipeconf &= ~PIPE_ENABLE_DITHER; else lvds &= ~LVDS_ENABLE_DITHER; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 439506cefc14..3ef3a0d0edd0 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -231,7 +231,7 @@ intel_dp_aux_ch(struct intel_output *intel_output, */ if (IS_eDP(intel_output)) aux_clock_divider = 225; /* eDP input clock at 450Mhz */ - else if (IS_IRONLAKE(dev)) + else if (HAS_PCH_SPLIT(dev)) aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ else aux_clock_divider = intel_hrawclk(dev) / 2; @@ -584,7 +584,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, intel_dp_compute_m_n(3, lane_count, mode->clock, adjusted_mode->clock, &m_n); - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { if (intel_crtc->pipe == 0) { I915_WRITE(TRANSA_DATA_M1, ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | @@ -1176,7 +1176,7 @@ intel_dp_detect(struct drm_connector *connector) dp_priv->has_audio = false; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) return ironlake_dp_detect(connector); temp = I915_READ(PORT_HOTPLUG_EN); diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 0e268deed761..a30f8bfc1985 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -82,7 +82,7 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) /* HW workaround, need to toggle enable bit off and on for 12bpc, but * we do this anyway which shows more stable in testing. */ - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE); POSTING_READ(hdmi_priv->sdvox_reg); } @@ -99,7 +99,7 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) /* HW workaround, need to write this twice for issue that may result * in first write getting masked. */ - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { I915_WRITE(hdmi_priv->sdvox_reg, temp); POSTING_READ(hdmi_priv->sdvox_reg); } diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 8673c735b8ab..fcc753ca5d94 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -128,7 +128,7 @@ intel_i2c_reset_gmbus(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { I915_WRITE(PCH_GMBUS0, 0); } else { I915_WRITE(GMBUS0, 0); diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index e91e81de5c71..222459ad178d 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -56,7 +56,7 @@ static void intel_lvds_set_backlight(struct drm_device *dev, int level) struct drm_i915_private *dev_priv = dev->dev_private; u32 blc_pwm_ctl, reg; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) reg = BLC_PWM_CPU_CTL; else reg = BLC_PWM_CTL; @@ -74,7 +74,7 @@ static u32 intel_lvds_get_max_backlight(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; u32 reg; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) reg = BLC_PWM_PCH_CTL2; else reg = BLC_PWM_CTL; @@ -91,7 +91,7 @@ static void intel_lvds_set_power(struct drm_device *dev, bool on) struct drm_i915_private *dev_priv = dev->dev_private; u32 pp_status, ctl_reg, status_reg; - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { ctl_reg = PCH_PP_CONTROL; status_reg = PCH_PP_STATUS; } else { @@ -137,7 +137,7 @@ static void intel_lvds_save(struct drm_connector *connector) u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; u32 pwm_ctl_reg; - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { pp_on_reg = PCH_PP_ON_DELAYS; pp_off_reg = PCH_PP_OFF_DELAYS; pp_ctl_reg = PCH_PP_CONTROL; @@ -174,7 +174,7 @@ static void intel_lvds_restore(struct drm_connector *connector) u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; u32 pwm_ctl_reg; - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { pp_on_reg = PCH_PP_ON_DELAYS; pp_off_reg = PCH_PP_OFF_DELAYS; pp_ctl_reg = PCH_PP_CONTROL; @@ -297,7 +297,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, } /* full screen scale for now */ - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) goto out; /* 965+ wants fuzzy fitting */ @@ -327,7 +327,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, * to register description and PRM. * Change the value here to see the borders for debugging */ - if (!IS_IRONLAKE(dev)) { + if (!HAS_PCH_SPLIT(dev)) { I915_WRITE(BCLRPAT_A, 0); I915_WRITE(BCLRPAT_B, 0); } @@ -548,7 +548,7 @@ static void intel_lvds_prepare(struct drm_encoder *encoder) struct drm_i915_private *dev_priv = dev->dev_private; u32 reg; - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) reg = BLC_PWM_CPU_CTL; else reg = BLC_PWM_CTL; @@ -587,7 +587,7 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder, * settings. */ - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) return; /* @@ -1027,7 +1027,7 @@ void intel_lvds_init(struct drm_device *dev) return; } - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) return; if (dev_priv->edp_support) { @@ -1130,7 +1130,7 @@ void intel_lvds_init(struct drm_device *dev) */ /* Ironlake: FIXME if still fail, not try pipe mode now */ - if (IS_IRONLAKE(dev)) + if (HAS_PCH_SPLIT(dev)) goto failed; lvds = I915_READ(LVDS); @@ -1151,7 +1151,7 @@ void intel_lvds_init(struct drm_device *dev) goto failed; out: - if (IS_IRONLAKE(dev)) { + if (HAS_PCH_SPLIT(dev)) { u32 pwm; /* make sure PWM is enabled */ pwm = I915_READ(BLC_PWM_CPU_CTL2); -- cgit v1.2.3 From 1f7a6e372e9cb4d749f34c0738d832e6cadb4071 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Tue, 23 Feb 2010 14:05:24 +0800 Subject: drm/i915: Add dependency on the intel agp module See http://bugzilla.kernel.org/show_bug.cgi?id=15021 Make sure that the appropriate AGP module is loaded and probed before trying to set up the DRM. The DRM already depends on the AGP core, but in this case we know the specific AGP driver we need too, and can help users avoid the trap of loading the AGP driver after the DRM driver. Signed-off-by: Zhenyu Wang Signed-off-by: Eric Anholt --- drivers/char/agp/intel-agp.c | 10 ++++++++-- drivers/gpu/drm/i915/i915_drv.c | 6 ++++++ 2 files changed, 14 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index 918e484f41b7..c1c07a2ccb11 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c @@ -10,6 +10,9 @@ #include #include "agp.h" +int intel_agp_enabled; +EXPORT_SYMBOL(intel_agp_enabled); + /* * If we have Intel graphics, we're not going to have anything other than * an Intel IOMMU. So make the correct use of the PCI DMA API contingent @@ -2473,7 +2476,7 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev, struct agp_bridge_data *bridge; u8 cap_ptr = 0; struct resource *r; - int i; + int i, err; cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); @@ -2565,7 +2568,10 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev, } pci_set_drvdata(pdev, bridge); - return agp_add_bridge(bridge); + err = agp_add_bridge(bridge); + if (!err) + intel_agp_enabled = 1; + return err; } static void __devexit agp_intel_remove(struct pci_dev *pdev) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 2a9178bb2748..85ad020125c8 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -49,6 +49,7 @@ unsigned int i915_lvds_downclock = 0; module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); static struct drm_driver driver; +extern int intel_agp_enabled; #define INTEL_VGA_DEVICE(id, info) { \ .class = PCI_CLASS_DISPLAY_VGA << 8, \ @@ -558,6 +559,11 @@ static struct drm_driver driver = { static int __init i915_init(void) { + if (!intel_agp_enabled) { + DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); + return -ENODEV; + } + driver.num_ioctls = i915_max_ioctl; i915_gem_shrinker_init(); -- cgit v1.2.3 From 798750e30d3de7932b0ac420f8fae2a970f2ac34 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 19 Feb 2010 11:51:56 +0100 Subject: drm/i915: reuse i915_gem_object_put_fence_reg for fence stealing code This has a few functional changes against the old code: * a few more unnecessary loads and stores to the drm_i915_fence_reg objects. Also an unnecessary store to the hw fence register. * zaps any userspace mappings before doing other flushes. Only changes anything when userspace does racy stuff against itself. * also flush GTT domain. This is a noop, but still try to keep the bookkeeping correct. Signed-off-by: Daniel Vetter Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_gem.c | 29 +++-------------------------- 1 file changed, 3 insertions(+), 26 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index c73da4049c81..302e096c3ca0 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2460,39 +2460,16 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj) */ drm_gem_object_reference(old_obj); - /* i915 uses fences for GPU access to tiled buffers */ - if (IS_I965G(dev) || !old_obj_priv->active) - break; - - /* This brings the object to the head of the LRU if it - * had been written to. The only way this should - * result in us waiting longer than the expected - * optimal amount of time is if there was a - * fence-using buffer later that was read-only. - */ - i915_gem_object_flush_gpu_write_domain(old_obj); - ret = i915_gem_object_wait_rendering(old_obj); - if (ret != 0) { - drm_gem_object_unreference(old_obj); - return ret; - } - break; } - /* - * Zap this virtual mapping so we can set up a fence again - * for this object next time we need it. - */ - i915_gem_release_mmap(old_obj); - i = old_obj_priv->fence_reg; reg = &dev_priv->fence_regs[i]; - old_obj_priv->fence_reg = I915_FENCE_REG_NONE; - list_del_init(&old_obj_priv->fence_list); - + ret = i915_gem_object_put_fence_reg(old_obj); drm_gem_object_unreference(old_obj); + if (ret != 0) + return ret; } obj_priv->fence_reg = i; -- cgit v1.2.3 From 4a87b8ca2185199c5d1b37b570efffd2e46fe813 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 19 Feb 2010 11:51:57 +0100 Subject: drm/i915: fixup active list locking in object_unbind All other accesses take this spinlock, so do this here, too. Signed-off-by: Daniel Vetter Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_gem.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 302e096c3ca0..e6b85cdbc60f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1987,6 +1987,7 @@ int i915_gem_object_unbind(struct drm_gem_object *obj) { struct drm_device *dev = obj->dev; + drm_i915_private_t *dev_priv = dev->dev_private; struct drm_i915_gem_object *obj_priv = obj->driver_private; int ret = 0; @@ -2042,8 +2043,10 @@ i915_gem_object_unbind(struct drm_gem_object *obj) } /* Remove ourselves from the LRU list if present. */ + spin_lock(&dev_priv->mm.active_list_lock); if (!list_empty(&obj_priv->list)) list_del_init(&obj_priv->list); + spin_unlock(&dev_priv->mm.active_list_lock); if (i915_gem_object_is_purgeable(obj_priv)) i915_gem_object_truncate(obj); -- cgit v1.2.3 From ae3db24aab398fb5f985696c12362eb12ef65812 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 19 Feb 2010 11:51:58 +0100 Subject: drm/i915: extract fence stealing code The spaghetti logic in there tripped up my brain's code parser for a few secs. Prevent this from happening again by extracting the fence stealing code into a seperate functions. IMHO this slightly clears up the code flow. v2: Beautified according to ickle's comments. v3: ickle forgot to flush his comment queue ... Now there's also a we-are-paranoid BUG_ON in there. v4: I've forgotten to switch on my brain when doing v3. Now the BUG_ON actually checks something useful. v5: Clean up a stale comment as noted by Eric Anholt. Signed-off-by: Daniel Vetter Reviewed-by: Chris Wilson Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_gem.c | 107 ++++++++++++++++++++++------------------ 1 file changed, 60 insertions(+), 47 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e6b85cdbc60f..ce1c0262bc63 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2382,6 +2382,58 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); } +static int i915_find_fence_reg(struct drm_device *dev) +{ + struct drm_i915_fence_reg *reg = NULL; + struct drm_i915_gem_object *obj_priv = NULL; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_gem_object *obj = NULL; + int i, avail, ret; + + /* First try to find a free reg */ + avail = 0; + for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { + reg = &dev_priv->fence_regs[i]; + if (!reg->obj) + return i; + + obj_priv = reg->obj->driver_private; + if (!obj_priv->pin_count) + avail++; + } + + if (avail == 0) + return -ENOSPC; + + /* None available, try to steal one or wait for a user to finish */ + i = I915_FENCE_REG_NONE; + list_for_each_entry(obj_priv, &dev_priv->mm.fence_list, + fence_list) { + obj = obj_priv->obj; + + if (obj_priv->pin_count) + continue; + + /* found one! */ + i = obj_priv->fence_reg; + break; + } + + BUG_ON(i == I915_FENCE_REG_NONE); + + /* We only have a reference on obj from the active list. put_fence_reg + * might drop that one, causing a use-after-free in it. So hold a + * private reference to obj like the other callers of put_fence_reg + * (set_tiling ioctl) do. */ + drm_gem_object_reference(obj); + ret = i915_gem_object_put_fence_reg(obj); + drm_gem_object_unreference(obj); + if (ret != 0) + return ret; + + return i; +} + /** * i915_gem_object_get_fence_reg - set up a fence reg for an object * @obj: object to map through a fence reg @@ -2402,8 +2454,7 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj) struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_object *obj_priv = obj->driver_private; struct drm_i915_fence_reg *reg = NULL; - struct drm_i915_gem_object *old_obj_priv = NULL; - int i, ret, avail; + int ret; /* Just update our place in the LRU if our fence is getting used. */ if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { @@ -2431,51 +2482,12 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj) break; } - /* First try to find a free reg */ - avail = 0; - for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { - reg = &dev_priv->fence_regs[i]; - if (!reg->obj) - break; - - old_obj_priv = reg->obj->driver_private; - if (!old_obj_priv->pin_count) - avail++; - } - - /* None available, try to steal one or wait for a user to finish */ - if (i == dev_priv->num_fence_regs) { - struct drm_gem_object *old_obj = NULL; - - if (avail == 0) - return -ENOSPC; - - list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list, - fence_list) { - old_obj = old_obj_priv->obj; - - if (old_obj_priv->pin_count) - continue; - - /* Take a reference, as otherwise the wait_rendering - * below may cause the object to get freed out from - * under us. - */ - drm_gem_object_reference(old_obj); - - break; - } - - i = old_obj_priv->fence_reg; - reg = &dev_priv->fence_regs[i]; - - ret = i915_gem_object_put_fence_reg(old_obj); - drm_gem_object_unreference(old_obj); - if (ret != 0) - return ret; - } + ret = i915_find_fence_reg(dev); + if (ret < 0) + return ret; - obj_priv->fence_reg = i; + obj_priv->fence_reg = ret; + reg = &dev_priv->fence_regs[obj_priv->fence_reg]; list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list); reg->obj = obj; @@ -2489,7 +2501,8 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj) else i830_write_fence_reg(reg); - trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode); + trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, + obj_priv->tiling_mode); return 0; } -- cgit v1.2.3 From 63560396536e9eb8858826fcbfc14d4015a41a95 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 19 Feb 2010 11:51:59 +0100 Subject: drm/i915: ensure lru ordering of fence_list The fence_list should be lru ordered for otherwise we might try to steal a fence reg from an active object even though there are fences from inactive objects available. lru ordering was obeyed for gpu access everywhere save when moving dirty objects from flushing_list to active_list. Fixing this cause the code to indent way to much, so I've extracted the flushing_list processing logic into its on function. Signed-off-by: Daniel Vetter Reviewed-by: Chris Wilson Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_gem.c | 57 ++++++++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index ce1c0262bc63..4b6d427ff7cd 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1558,6 +1558,38 @@ i915_gem_object_move_to_inactive(struct drm_gem_object *obj) i915_verify_inactive(dev, __FILE__, __LINE__); } +static void +i915_gem_process_flushing_list(struct drm_device *dev, + uint32_t flush_domains, uint32_t seqno) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + struct drm_i915_gem_object *obj_priv, *next; + + list_for_each_entry_safe(obj_priv, next, + &dev_priv->mm.gpu_write_list, + gpu_write_list) { + struct drm_gem_object *obj = obj_priv->obj; + + if ((obj->write_domain & flush_domains) == + obj->write_domain) { + uint32_t old_write_domain = obj->write_domain; + + obj->write_domain = 0; + list_del_init(&obj_priv->gpu_write_list); + i915_gem_object_move_to_active(obj, seqno); + + /* update the fence lru list */ + if (obj_priv->fence_reg != I915_FENCE_REG_NONE) + list_move_tail(&obj_priv->fence_list, + &dev_priv->mm.fence_list); + + trace_i915_gem_object_change_domain(obj, + obj->read_domains, + old_write_domain); + } + } +} + /** * Creates a new sequence number, emitting a write of it to the status page * plus an interrupt, which will trigger i915_user_interrupt_handler. @@ -1616,29 +1648,8 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv, /* Associate any objects on the flushing list matching the write * domain we're flushing with our flush. */ - if (flush_domains != 0) { - struct drm_i915_gem_object *obj_priv, *next; - - list_for_each_entry_safe(obj_priv, next, - &dev_priv->mm.gpu_write_list, - gpu_write_list) { - struct drm_gem_object *obj = obj_priv->obj; - - if ((obj->write_domain & flush_domains) == - obj->write_domain) { - uint32_t old_write_domain = obj->write_domain; - - obj->write_domain = 0; - list_del_init(&obj_priv->gpu_write_list); - i915_gem_object_move_to_active(obj, seqno); - - trace_i915_gem_object_change_domain(obj, - obj->read_domains, - old_write_domain); - } - } - - } + if (flush_domains != 0) + i915_gem_process_flushing_list(dev, flush_domains, seqno); if (!dev_priv->mm.suspended) { mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); -- cgit v1.2.3 From 4df2faf4512c2e2ffa6793e055c73a4e7b8b5e36 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 19 Feb 2010 11:52:00 +0100 Subject: drm/i915: reuse i915_gpu_idle helper We have it, so use it. This required moving the function to avoid a forward declaration. Signed-off-by: Daniel Vetter Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_gem.c | 56 ++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 31 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 4b6d427ff7cd..2571d1f543ef 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2094,12 +2094,35 @@ i915_gem_find_inactive_object(struct drm_device *dev, int min_size) return best ? best : first; } +static int +i915_gpu_idle(struct drm_device *dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + bool lists_empty; + uint32_t seqno; + + spin_lock(&dev_priv->mm.active_list_lock); + lists_empty = list_empty(&dev_priv->mm.flushing_list) && + list_empty(&dev_priv->mm.active_list); + spin_unlock(&dev_priv->mm.active_list_lock); + + if (lists_empty) + return 0; + + /* Flush everything onto the inactive list. */ + i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); + seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); + if (seqno == 0) + return -ENOMEM; + + return i915_wait_request(dev, seqno); +} + static int i915_gem_evict_everything(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; int ret; - uint32_t seqno; bool lists_empty; spin_lock(&dev_priv->mm.active_list_lock); @@ -2112,12 +2135,7 @@ i915_gem_evict_everything(struct drm_device *dev) return -ENOSPC; /* Flush everything (on to the inactive lists) and evict */ - i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); - seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); - if (seqno == 0) - return -ENOMEM; - - ret = i915_wait_request(dev, seqno); + ret = i915_gpu_idle(dev); if (ret) return ret; @@ -4475,30 +4493,6 @@ i915_gem_evict_from_inactive_list(struct drm_device *dev) return 0; } -static int -i915_gpu_idle(struct drm_device *dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - bool lists_empty; - uint32_t seqno; - - spin_lock(&dev_priv->mm.active_list_lock); - lists_empty = list_empty(&dev_priv->mm.flushing_list) && - list_empty(&dev_priv->mm.active_list); - spin_unlock(&dev_priv->mm.active_list_lock); - - if (lists_empty) - return 0; - - /* Flush everything onto the inactive list. */ - i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); - seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); - if (seqno == 0) - return -ENOMEM; - - return i915_wait_request(dev, seqno); -} - int i915_gem_idle(struct drm_device *dev) { -- cgit v1.2.3 From 922a2efc1b6ef48e2783f7efeb3a94e952c7ed14 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 19 Feb 2010 11:52:01 +0100 Subject: drm/i915: clean-up i915_gem_flush_gpu_write_domain Now that we have an exact gpu write domain tracking, we don't need to move objects to the active list ourself. i915_add_request will take care of that under all circumstances. Idea stolen from a patch by Chris Wilson . Signed-off-by: Daniel Vetter Signed-off-by: Chris Wilson Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_gem.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 2571d1f543ef..6fe54db8f33c 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2748,7 +2748,6 @@ static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) { struct drm_device *dev = obj->dev; - uint32_t seqno; uint32_t old_write_domain; if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) @@ -2757,9 +2756,8 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) /* Queue the GPU write cache flushing we need. */ old_write_domain = obj->write_domain; i915_gem_flush(dev, 0, obj->write_domain); - seqno = i915_add_request(dev, NULL, obj->write_domain); + (void) i915_add_request(dev, NULL, obj->write_domain); BUG_ON(obj->write_domain); - i915_gem_object_move_to_active(obj, seqno); trace_i915_gem_object_change_domain(obj, obj->read_domains, -- cgit v1.2.3 From 16edd55029fcedaa0d03f24ee607c3a882871a10 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 19 Feb 2010 11:52:02 +0100 Subject: drm/i915: check for multiple write domains in pin_and_relocate The assumption that an object has only ever one write domain is deeply threaded into gem (it's even encoded the the singular of the variable name). Don't let userspace screw us over. Signed-off-by: Daniel Vetter Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_gem.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 6fe54db8f33c..fba37e9f775d 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3367,6 +3367,16 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, } /* Validate that the target is in a valid r/w GPU domain */ + if (reloc->write_domain & (reloc->write_domain - 1)) { + DRM_ERROR("reloc with multiple write domains: " + "obj %p target %d offset %d " + "read %08x write %08x", + obj, reloc->target_handle, + (int) reloc->offset, + reloc->read_domains, + reloc->write_domain); + return -EINVAL; + } if (reloc->write_domain & I915_GEM_DOMAIN_CPU || reloc->read_domains & I915_GEM_DOMAIN_CPU) { DRM_ERROR("reloc with read/write CPU domains: " -- cgit v1.2.3 From 469d129664c5b83f37ca74913700d416d584833b Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 11 Feb 2010 12:41:05 -0800 Subject: drm/i915: enable/disable LVDS port at DPMS time It would be good to disable the LVDS port when we shut down the panel to save power. We haven't done so until now because we had trouble getting the right LVDS parameters from the BIOS. I think we're past that now, so enabling and disabling the port should be safe, though it would probably be made cleaner with some additional changes to the display code, where we also bang on the LVDS reg to set the pairing correctly etc. Seems to save a bit of power (up to 300mW in my basic wattsup meter testing). Signed-off-by: Jesse Barnes Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/intel_lvds.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 222459ad178d..14e516fdc2dd 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -89,17 +89,22 @@ static u32 intel_lvds_get_max_backlight(struct drm_device *dev) static void intel_lvds_set_power(struct drm_device *dev, bool on) { struct drm_i915_private *dev_priv = dev->dev_private; - u32 pp_status, ctl_reg, status_reg; + u32 pp_status, ctl_reg, status_reg, lvds_reg; if (HAS_PCH_SPLIT(dev)) { ctl_reg = PCH_PP_CONTROL; status_reg = PCH_PP_STATUS; + lvds_reg = PCH_LVDS; } else { ctl_reg = PP_CONTROL; status_reg = PP_STATUS; + lvds_reg = LVDS; } if (on) { + I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); + POSTING_READ(lvds_reg); + I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); do { @@ -115,6 +120,9 @@ static void intel_lvds_set_power(struct drm_device *dev, bool on) do { pp_status = I915_READ(status_reg); } while (pp_status & PP_ON); + + I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); + POSTING_READ(lvds_reg); } } -- cgit v1.2.3 From 6070a4a928f8c92b9fae7d6717ebbb05f425d6b2 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Mon, 8 Feb 2010 21:35:12 +0800 Subject: drm/i915: Use a dmi quirk to skip a broken SDVO TV output. This IBM system has a multi-function SDVO card that reports both VGA and TV, but the system has no TV connector. The TV connector always reported as connected, which would lead to poor modesetting choices. https://bugs.freedesktop.org/show_bug.cgi?id=25787 Signed-off-by: Zhao Yakui Tested-by: Vance Cc: stable@kernel.org Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/intel_sdvo.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 82678d30ab06..48daee5c9c63 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -35,6 +35,7 @@ #include "i915_drm.h" #include "i915_drv.h" #include "intel_sdvo_regs.h" +#include static char *tv_format_names[] = { "NTSC_M" , "NTSC_J" , "NTSC_443", @@ -2283,6 +2284,25 @@ intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device) return 0x72; } +static int intel_sdvo_bad_tv_callback(const struct dmi_system_id *id) +{ + DRM_DEBUG_KMS("Ignoring bad SDVO TV connector for %s\n", id->ident); + return 1; +} + +static struct dmi_system_id intel_sdvo_bad_tv[] = { + { + .callback = intel_sdvo_bad_tv_callback, + .ident = "IntelG45/ICH10R/DME1737", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "IBM CORPORATION"), + DMI_MATCH(DMI_PRODUCT_NAME, "4800784"), + }, + }, + + { } /* terminating entry */ +}; + static bool intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags) { @@ -2323,7 +2343,8 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags) (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | (1 << INTEL_ANALOG_CLONE_BIT); } - } else if (flags & SDVO_OUTPUT_SVID0) { + } else if ((flags & SDVO_OUTPUT_SVID0) && + !dmi_check_system(intel_sdvo_bad_tv)) { sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0; encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; -- cgit v1.2.3 From 4e924a814ac78e325653840190e9e4762e6f4b7c Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Sat, 27 Feb 2010 17:06:09 +0200 Subject: power_supply: bq27x00: add status and time properties The BQ27x00 series of chips can report time-to-empty and time-to-full, so let's add corresponding properties. Also report charge status based on status flag register. Signed-off-by: Grazvydas Ignotas Signed-off-by: Anton Vorontsov --- drivers/power/bq27x00_battery.c | 81 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/power/bq27x00_battery.c b/drivers/power/bq27x00_battery.c index 1526d020cbc6..5d940fad8d43 100644 --- a/drivers/power/bq27x00_battery.c +++ b/drivers/power/bq27x00_battery.c @@ -32,10 +32,16 @@ #define BQ27x00_REG_VOLT 0x08 #define BQ27x00_REG_AI 0x14 #define BQ27x00_REG_FLAGS 0x0A +#define BQ27x00_REG_TTE 0x16 +#define BQ27x00_REG_TTF 0x18 +#define BQ27x00_REG_TTECP 0x26 #define BQ27000_REG_RSOC 0x0B /* Relative State-of-Charge */ +#define BQ27000_FLAG_CHGS BIT(7) #define BQ27500_REG_SOC 0x2c +#define BQ27500_FLAG_DSC BIT(0) +#define BQ27500_FLAG_FC BIT(9) /* If the system has several batteries we need a different name for each * of them... @@ -62,11 +68,15 @@ struct bq27x00_device_info { }; static enum power_supply_property bq27x00_battery_props[] = { + POWER_SUPPLY_PROP_STATUS, POWER_SUPPLY_PROP_PRESENT, POWER_SUPPLY_PROP_VOLTAGE_NOW, POWER_SUPPLY_PROP_CURRENT_NOW, POWER_SUPPLY_PROP_CAPACITY, POWER_SUPPLY_PROP_TEMP, + POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW, + POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG, + POWER_SUPPLY_PROP_TIME_TO_FULL_NOW, }; /* @@ -144,7 +154,7 @@ static int bq27x00_battery_current(struct bq27x00_device_info *di) dev_err(di->dev, "error reading flags\n"); return 0; } - if ((flags & (1 << 7)) != 0) { + if (flags & BQ27000_FLAG_CHGS) { dev_dbg(di->dev, "negative current!\n"); return -curr; } @@ -174,6 +184,60 @@ static int bq27x00_battery_rsoc(struct bq27x00_device_info *di) return rsoc; } +static int bq27x00_battery_status(struct bq27x00_device_info *di, + union power_supply_propval *val) +{ + int flags = 0; + int status; + int ret; + + ret = bq27x00_read(BQ27x00_REG_FLAGS, &flags, 0, di); + if (ret < 0) { + dev_err(di->dev, "error reading flags\n"); + return ret; + } + + if (di->chip == BQ27500) { + if (flags & BQ27500_FLAG_FC) + status = POWER_SUPPLY_STATUS_FULL; + else if (flags & BQ27500_FLAG_DSC) + status = POWER_SUPPLY_STATUS_DISCHARGING; + else + status = POWER_SUPPLY_STATUS_CHARGING; + } else { + if (flags & BQ27000_FLAG_CHGS) + status = POWER_SUPPLY_STATUS_CHARGING; + else + status = POWER_SUPPLY_STATUS_DISCHARGING; + } + + val->intval = status; + return 0; +} + +/* + * Read a time register. + * Return < 0 if something fails. + */ +static int bq27x00_battery_time(struct bq27x00_device_info *di, int reg, + union power_supply_propval *val) +{ + int tval = 0; + int ret; + + ret = bq27x00_read(reg, &tval, 0, di); + if (ret) { + dev_err(di->dev, "error reading register %02x\n", reg); + return ret; + } + + if (tval == 65535) + return -ENODATA; + + val->intval = tval * 60; + return 0; +} + #define to_bq27x00_device_info(x) container_of((x), \ struct bq27x00_device_info, bat); @@ -181,9 +245,13 @@ static int bq27x00_battery_get_property(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) { + int ret = 0; struct bq27x00_device_info *di = to_bq27x00_device_info(psy); switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + ret = bq27x00_battery_status(di, val); + break; case POWER_SUPPLY_PROP_VOLTAGE_NOW: case POWER_SUPPLY_PROP_PRESENT: val->intval = bq27x00_battery_voltage(di); @@ -199,11 +267,20 @@ static int bq27x00_battery_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_TEMP: val->intval = bq27x00_battery_temperature(di); break; + case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW: + ret = bq27x00_battery_time(di, BQ27x00_REG_TTE, val); + break; + case POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG: + ret = bq27x00_battery_time(di, BQ27x00_REG_TTECP, val); + break; + case POWER_SUPPLY_PROP_TIME_TO_FULL_NOW: + ret = bq27x00_battery_time(di, BQ27x00_REG_TTF, val); + break; default: return -EINVAL; } - return 0; + return ret; } static void bq27x00_powersupply_init(struct bq27x00_device_info *di) -- cgit v1.2.3 From afbc74fdc5b96552c384e57119b3cc13c840bf06 Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Sat, 27 Feb 2010 17:06:44 +0200 Subject: power_supply: bq27x00: fix voltage and current units The chip returns voltage and current in mV and mA, but power supply class uses uV and uA, so add missing conversion. Signed-off-by: Grazvydas Ignotas Signed-off-by: Anton Vorontsov --- drivers/power/bq27x00_battery.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/power/bq27x00_battery.c b/drivers/power/bq27x00_battery.c index 5d940fad8d43..bece33ed873c 100644 --- a/drivers/power/bq27x00_battery.c +++ b/drivers/power/bq27x00_battery.c @@ -125,7 +125,7 @@ static int bq27x00_battery_voltage(struct bq27x00_device_info *di) return ret; } - return volt; + return volt * 1000; } /* @@ -156,11 +156,11 @@ static int bq27x00_battery_current(struct bq27x00_device_info *di) } if (flags & BQ27000_FLAG_CHGS) { dev_dbg(di->dev, "negative current!\n"); - return -curr; + curr = -curr; } } - return curr; + return curr * 1000; } /* -- cgit v1.2.3 From 6ca3a7a96e91b1aa8c704153c992b191d35b5747 Mon Sep 17 00:00:00 2001 From: "Steven J. Magnani" Date: Thu, 25 Feb 2010 13:39:30 -0600 Subject: fsldma: Fix cookie issues fsl_dma_tx_submit() only sets the cookie on the first descriptor of a transaction. It should set the cookie on all. Signed-off-by: Steven J. Magnani Acked-by: Ira W. Snyder Signed-off-by: Dan Williams --- drivers/dma/fsldma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 92efa87258b9..6541ebf8bf63 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -362,7 +362,7 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) if (cookie < 0) cookie = 1; - desc->async_tx.cookie = cookie; + child->async_tx.cookie = cookie; } chan->common.cookie = cookie; -- cgit v1.2.3 From 76bd061f5c7b7550cdaed68ad6219ea7cee288fc Mon Sep 17 00:00:00 2001 From: "Steven J. Magnani" Date: Sun, 28 Feb 2010 22:18:16 -0700 Subject: fsldma: Fix cookie issues fsl_dma_update_completed_cookie() appears to calculate the last completed cookie incorrectly in the corner case where DMA on cookie 1 is in progress just following a cookie wrap. Signed-off-by: Steven J. Magnani Acked-by: Ira W. Snyder [dan.j.williams@intel.com: fix an integer overflow warning with INT_MAX] Signed-off-by: Dan Williams --- drivers/dma/fsldma.c | 5 ++++- include/linux/dmaengine.h | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 6541ebf8bf63..bbb4be5a3ff4 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -819,8 +819,11 @@ static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan) desc = to_fsl_desc(chan->ld_running.prev); if (dma_is_idle(chan)) cookie = desc->async_tx.cookie; - else + else { cookie = desc->async_tx.cookie - 1; + if (unlikely(cookie < DMA_MIN_COOKIE)) + cookie = DMA_MAX_COOKIE; + } chan->completed_cookie = cookie; diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 78784982b33e..4d8d619f28bc 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -31,6 +31,8 @@ * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code */ typedef s32 dma_cookie_t; +#define DMA_MIN_COOKIE 1 +#define DMA_MAX_COOKIE INT_MAX #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) -- cgit v1.2.3 From 94de648d72c8bc833590523f22386d4babbea988 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Mon, 15 Feb 2010 22:35:23 +0100 Subject: dmatest: correct raid6 PQ test The number of PQ sources specified by module parameter "pq_sources" is always forced odd to fit into dmatest's destination verificaton scheme. But number of PQ sources and coefficients as passed to the driver's prep_dma_pq() is not adjusted accordingly. Fix it now to get correct PQ testing results in the case passed "pq_sources" parameter is even. Signed-off-by: Anatolij Gustschin Signed-off-by: Andrew Morton Cc: Maciej Sosnowski Signed-off-by: Dan Williams --- drivers/dma/dmatest.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c index 8b905161fbf4..cc0f3294a766 100644 --- a/drivers/dma/dmatest.c +++ b/drivers/dma/dmatest.c @@ -237,7 +237,7 @@ static int dmatest_func(void *data) dma_cookie_t cookie; enum dma_status status; enum dma_ctrl_flags flags; - u8 pq_coefs[pq_sources]; + u8 pq_coefs[pq_sources + 1]; int ret; int src_cnt; int dst_cnt; @@ -257,7 +257,7 @@ static int dmatest_func(void *data) } else if (thread->type == DMA_PQ) { src_cnt = pq_sources | 1; /* force odd to ensure dst = src */ dst_cnt = 2; - for (i = 0; i < pq_sources; i++) + for (i = 0; i < src_cnt; i++) pq_coefs[i] = 1; } else goto err_srcs; @@ -355,7 +355,7 @@ static int dmatest_func(void *data) for (i = 0; i < dst_cnt; i++) dma_pq[i] = dma_dsts[i] + dst_off; tx = dev->device_prep_dma_pq(chan, dma_pq, dma_srcs, - pq_sources, pq_coefs, + src_cnt, pq_coefs, len, flags); } -- cgit v1.2.3 From 67b9124f734b22b30d9adf18c39fe795e2901070 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Sun, 28 Feb 2010 22:20:18 -0700 Subject: dmatest: fix handling of an even number of xor_sources Just like commit ac5d73fc, we need to be careful to use 'src_cnt' as it contains the fixed up number of xor sources (forced odd) to meet dmatest's data verification scheme. Signed-off-by: Dan Williams --- drivers/dma/dmatest.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c index cc0f3294a766..8e409fb50fc0 100644 --- a/drivers/dma/dmatest.c +++ b/drivers/dma/dmatest.c @@ -347,7 +347,7 @@ static int dmatest_func(void *data) else if (thread->type == DMA_XOR) tx = dev->device_prep_dma_xor(chan, dma_dsts[0] + dst_off, - dma_srcs, xor_sources, + dma_srcs, src_cnt, len, flags); else if (thread->type == DMA_PQ) { dma_addr_t dma_pq[dst_cnt]; -- cgit v1.2.3 From 32b3c2abaf8c61c80a8b02071c73f05252122ffe Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Fri, 26 Feb 2010 19:14:12 +0000 Subject: drm/radeon/kms: initialize set_surface_reg reg for rs600 asic rs600 asic was missing set_surface_reg callback leading to oops. Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_asic.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 4572a6699884..d3a157b2bcb7 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -407,6 +407,8 @@ static struct radeon_asic rs600_asic = { .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = &radeon_atom_set_clock_gating, + .set_surface_reg = r100_set_surface_reg, + .clear_surface_reg = r100_clear_surface_reg, .bandwidth_update = &rs600_bandwidth_update, .hpd_init = &rs600_hpd_init, .hpd_fini = &rs600_hpd_fini, -- cgit v1.2.3 From d964fc54ed06cea45dfd10832ed3d34f3ddb661b Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Thu, 25 Feb 2010 04:23:31 +0000 Subject: drm/radeon: use ALIGN instead of open coding it Cc: Jerome Glisse Cc: Alex Deucher Signed-off-by: Matt Turner Reviewed-by: Corbin Simpson Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600_blit.c | 2 +- drivers/gpu/drm/radeon/r600_blit_kms.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c index 5ea432347589..f4fb88ece2bb 100644 --- a/drivers/gpu/drm/radeon/r600_blit.c +++ b/drivers/gpu/drm/radeon/r600_blit.c @@ -49,7 +49,7 @@ set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 RING_LOCALS; DRM_DEBUG("\n"); - h = (h + 7) & ~7; + h = ALIGN(h, 8); if (h < 8) h = 8; diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c index de8bbbcfe117..f6c6c77db7e0 100644 --- a/drivers/gpu/drm/radeon/r600_blit_kms.c +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c @@ -25,7 +25,7 @@ set_render_target(struct radeon_device *rdev, int format, u32 cb_color_info; int pitch, slice; - h = (h + 7) & ~7; + h = ALIGN(h, 8); if (h < 8) h = 8; @@ -396,7 +396,7 @@ set_default_state(struct radeon_device *rdev) NUM_ES_STACK_ENTRIES(num_es_stack_entries)); /* emit an IB pointing at default state */ - dwords = (rdev->r600_blit.state_len + 0xf) & ~0xf; + dwords = ALIGN(rdev->r600_blit.state_len, 0x10); gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); -- cgit v1.2.3 From 566d84d172161cb6c0c4dd834c34abbac6bf7b38 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 24 Feb 2010 17:17:13 +1000 Subject: drm/radeon: r100/r200 ums: block ability for userspace app to trash 0 page and beyond radeon's have a special ability to passthrough writes in their internal memory space directly to PCI, this ability means that if some of the internal surfaces like the depth buffer point at 0x0, any writes to these will go directly to RAM at 0x0 via PCI busmastering. Now mesa used to always emit clears after emitting state, since the radeon mesa driver was refactored a year or more ago, it was found it could generate a clear request without ever sending any setup state to the card. So the clear would attempt to clear the depth buffer at 0x0, which would overwrite main memory at this point. fs corruption ensues. Also once one app did this correctly, it would never get set back to 0 making this messy to reproduce. The kernel should block this from happening as mesa runs without privs, though it does require the user be connected to the current running X session. This patch implements a check to make sure the depth offset has been set before a depth clear occurs and if it finds one it prints a warning and ignores the depth clear request. There is also a mesa fix to avoid sending the badness going into mesa. This only affects r100/r200 GPUs in user modesetting mode. Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_cp.c | 1 + drivers/gpu/drm/radeon/radeon_drv.h | 2 ++ drivers/gpu/drm/radeon/radeon_state.c | 6 ++++++ 3 files changed, 9 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c index 06123ba31d31..dc6eba6b96dd 100644 --- a/drivers/gpu/drm/radeon/radeon_cp.c +++ b/drivers/gpu/drm/radeon/radeon_cp.c @@ -1644,6 +1644,7 @@ static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_pri radeon_cp_load_microcode(dev_priv); radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); + dev_priv->have_z_offset = 0; radeon_do_engine_reset(dev); radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index f6d20cee5705..ee484b61bc5c 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h @@ -267,6 +267,8 @@ typedef struct drm_radeon_private { u32 scratch_ages[5]; + int have_z_offset; + /* starting from here on, data is preserved accross an open */ uint32_t flags; /* see radeon_chip_flags */ resource_size_t fb_aper_offset; diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c index 44b6d66b0ab3..8e69dc485dcb 100644 --- a/drivers/gpu/drm/radeon/radeon_state.c +++ b/drivers/gpu/drm/radeon/radeon_state.c @@ -105,6 +105,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * DRM_ERROR("Invalid depth buffer offset\n"); return -EINVAL; } + dev_priv->have_z_offset = 1; break; case RADEON_EMIT_PP_CNTL: @@ -898,6 +899,11 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev, if (tmp & RADEON_BACK) flags |= RADEON_FRONT; } + if (flags & (RADEON_DEPTH|RADEON_STENCIL)) { + if (!dev_priv->have_z_offset) + printk_once(KERN_ERR "radeon: illegal depth clear request. Buggy mesa detected - please update.\n"); + flags &= ~(RADEON_DEPTH | RADEON_STENCIL); + } if (flags & (RADEON_FRONT | RADEON_BACK)) { -- cgit v1.2.3 From c8792d5e6cdfeb7db186f6ea654dee90ca3b9c0c Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Fri, 26 Feb 2010 08:46:33 +0000 Subject: drm/radeon/kms: do not preset audio stuff and start timer when not using audio MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600_audio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c index 387abaa275a4..668ff4b11c60 100644 --- a/drivers/gpu/drm/radeon/r600_audio.c +++ b/drivers/gpu/drm/radeon/r600_audio.c @@ -160,10 +160,10 @@ static void r600_audio_engine_enable(struct radeon_device *rdev, bool enable) */ int r600_audio_init(struct radeon_device *rdev) { - if (!r600_audio_chipset_supported(rdev)) + if (!radeon_audio || !r600_audio_chipset_supported(rdev)) return 0; - r600_audio_engine_enable(rdev, radeon_audio); + r600_audio_engine_enable(rdev, true); rdev->audio_channels = -1; rdev->audio_rate = -1; @@ -266,7 +266,7 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock) */ void r600_audio_fini(struct radeon_device *rdev) { - if (!r600_audio_chipset_supported(rdev)) + if (!radeon_audio || !r600_audio_chipset_supported(rdev)) return; del_timer(&rdev->audio_timer); -- cgit v1.2.3 From 3464f114967b2f98f1bfe0eaf0a413bb51b4df1d Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Fri, 26 Feb 2010 08:44:57 +0000 Subject: Revert "drm/radeon/kms: disable HDMI audio for now on rv710/rv730" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit "disabled" audio on RV710 and RV740 only, leaving RV770 and RV730. The order is: CHIP_RV770 < CHIP_RV730 < CHIP_RV710 < CHIP_RV740. It is not needed anway, as we do not even try to enable audio on RV770 and newer. We call initializing function in r600.c only, not in rv770.c. If there is something causing green tinges, it's HDMI mode setting for encoder and I will try to debug that. Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600_audio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c index 668ff4b11c60..58c3cb32f7b0 100644 --- a/drivers/gpu/drm/radeon/r600_audio.c +++ b/drivers/gpu/drm/radeon/r600_audio.c @@ -35,7 +35,7 @@ */ static int r600_audio_chipset_supported(struct radeon_device *rdev) { - return (rdev->family >= CHIP_R600 && rdev->family < CHIP_RV710) + return rdev->family >= CHIP_R600 || rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740; -- cgit v1.2.3 From 6d9c13513661c1991bf5f4e6e1363c721292d819 Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Fri, 26 Feb 2010 08:46:32 +0000 Subject: drm/radeon/kms: do not disable audio engine twice MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600_audio.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c index 58c3cb32f7b0..db928016d034 100644 --- a/drivers/gpu/drm/radeon/r600_audio.c +++ b/drivers/gpu/drm/radeon/r600_audio.c @@ -270,7 +270,6 @@ void r600_audio_fini(struct radeon_device *rdev) return; del_timer(&rdev->audio_timer); - WREG32_P(R600_AUDIO_ENABLE, 0x0, ~0x81000000); r600_audio_engine_enable(rdev, false); } -- cgit v1.2.3 From 6a9ee8af344e3bd7dbd61e67037096cdf7f83289 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 1 Feb 2010 15:38:10 +1000 Subject: vga_switcheroo: initial implementation (v15) Many new laptops now come with 2 gpus, one to be used for low power modes and one for gaming/on-ac applications. These GPUs are typically wired to the laptop panel and VGA ports via a multiplexer unit which is controlled via ACPI methods. 4 combinations of systems typically exist - with 2 ACPI methods. Intel/ATI - Lenovo W500/T500 - use ATPX ACPI method ATI/ATI - some ASUS - use ATPX ACPI Method Intel/Nvidia - - use _DSM ACPI method Nvidia/Nvidia - - use _DSM ACPI method. TODO: This patch adds support for the ATPX method and initial bits for the _DSM methods that need to written by someone with access to the hardware. Add a proper non-debugfs interface - need to get some proper testing first. v2: add power up/down support for both devices on W500 puts i915/radeon into D3 and cuts power to radeon. v3: redo probing methods, no DMI list, drm devices call to register with switcheroo, it tries to find an ATPX method on any device and once there is two devices + ATPX it inits the switcher. v4: ATPX msg handling using buffers - should work on more machines v5: rearchitect after more mjg59 discussion - move ATPX handling to radeon driver. v6: add file headers + initial nouveau bits (to be filled out). v7: merge delayed switcher code. v8: avoid suspend/resume of gpu that is off v9: rearchitect - mjg59 is always right. - move all ATPX code to radeon, should allow simpler DSM also proper ATRM handling v10: add ATRM support for radeon BIOS, add mutex to lock vgasr_priv v11: fix bug in resuming Intel for 2nd time. v12: start fixing up nvidia code blindly. v13: blindly guess at finishing nvidia code v14: remove radeon audio hacks - fix up intel resume more like upstream v15: clean up printks + remove unnecessary igd/dis pointers mount debugfs /sys/kernel/debug/vgaswitcheroo/switch - should exist if ATPX detected + 2 cards. DIS - immediate change to discrete IGD - immediate change to IGD DDIS - delayed change to discrete DIGD - delayed change to IGD ON - turn on not in use OFF - turn off not in use Tested on W500 (Intel/ATI) and T500 (Intel/ATI) Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/i915_dma.c | 35 +++ drivers/gpu/drm/i915/i915_drv.c | 4 +- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/intel_fb.c | 2 + drivers/gpu/drm/nouveau/nouveau_acpi.c | 160 +++++++--- drivers/gpu/drm/nouveau/nouveau_drv.c | 9 +- drivers/gpu/drm/nouveau/nouveau_drv.h | 19 +- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 2 + drivers/gpu/drm/nouveau/nouveau_state.c | 32 +- drivers/gpu/drm/radeon/Makefile | 3 +- drivers/gpu/drm/radeon/radeon.h | 8 + drivers/gpu/drm/radeon/radeon_atpx_handler.c | 258 +++++++++++++++ drivers/gpu/drm/radeon/radeon_bios.c | 44 ++- drivers/gpu/drm/radeon/radeon_device.c | 40 +++ drivers/gpu/drm/radeon/radeon_drv.c | 2 + drivers/gpu/drm/radeon/radeon_drv.h | 3 + drivers/gpu/drm/radeon/radeon_fb.c | 3 + drivers/gpu/drm/radeon/radeon_kms.c | 3 + drivers/gpu/vga/Kconfig | 13 + drivers/gpu/vga/Makefile | 1 + drivers/gpu/vga/vga_switcheroo.c | 453 +++++++++++++++++++++++++++ drivers/video/console/fbcon.c | 18 ++ include/linux/fb.h | 2 + include/linux/vga_switcheroo.h | 58 ++++ 24 files changed, 1104 insertions(+), 70 deletions(-) create mode 100644 drivers/gpu/drm/radeon/radeon_atpx_handler.c create mode 100644 drivers/gpu/vga/vga_switcheroo.c create mode 100644 include/linux/vga_switcheroo.h (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 2307f98349f7..42ca07f04a21 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -35,6 +35,7 @@ #include "i915_drv.h" #include "i915_trace.h" #include +#include /* Really want an OS-independent resettable timer. Would like to have * this loop run for (eg) 3 sec, but have the timer reset every time @@ -1199,6 +1200,32 @@ static unsigned int i915_vga_set_decode(void *cookie, bool state) return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; } +static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) +{ + struct drm_device *dev = pci_get_drvdata(pdev); + pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; + if (state == VGA_SWITCHEROO_ON) { + printk(KERN_INFO "i915: switched off\n"); + /* i915 resume handler doesn't set to D0 */ + pci_set_power_state(dev->pdev, PCI_D0); + i915_resume(dev); + } else { + printk(KERN_ERR "i915: switched off\n"); + i915_suspend(dev, pmm); + } +} + +static bool i915_switcheroo_can_switch(struct pci_dev *pdev) +{ + struct drm_device *dev = pci_get_drvdata(pdev); + bool can_switch; + + spin_lock(&dev->count_lock); + can_switch = (dev->open_count == 0); + spin_unlock(&dev->count_lock); + return can_switch; +} + static int i915_load_modeset_init(struct drm_device *dev, unsigned long prealloc_start, unsigned long prealloc_size, @@ -1260,6 +1287,12 @@ static int i915_load_modeset_init(struct drm_device *dev, if (ret) goto destroy_ringbuffer; + ret = vga_switcheroo_register_client(dev->pdev, + i915_switcheroo_set_state, + i915_switcheroo_can_switch); + if (ret) + goto destroy_ringbuffer; + intel_modeset_init(dev); ret = drm_irq_install(dev); @@ -1544,6 +1577,7 @@ int i915_driver_unload(struct drm_device *dev) dev_priv->child_dev_num = 0; } drm_irq_uninstall(dev); + vga_switcheroo_unregister_client(dev->pdev); vga_client_register(dev->pdev, NULL, NULL, NULL); } @@ -1611,6 +1645,7 @@ void i915_driver_lastclose(struct drm_device * dev) if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { drm_fb_helper_restore(); + vga_switcheroo_process_delayed_switch(); return; } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index cf4cb3e9a0c2..fd739efe73ce 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -201,7 +201,7 @@ static int i915_drm_freeze(struct drm_device *dev) return 0; } -static int i915_suspend(struct drm_device *dev, pm_message_t state) +int i915_suspend(struct drm_device *dev, pm_message_t state) { int error; @@ -255,7 +255,7 @@ static int i915_drm_thaw(struct drm_device *dev) return error; } -static int i915_resume(struct drm_device *dev) +int i915_resume(struct drm_device *dev) { if (pci_enable_device(dev->pdev)) return -EIO; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b99b6a841d95..d77e56651352 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -736,6 +736,8 @@ extern unsigned int i915_fbpercrtc; extern unsigned int i915_powersave; extern unsigned int i915_lvds_downclock; +extern int i915_suspend(struct drm_device *dev, pm_message_t state); +extern int i915_resume(struct drm_device *dev); extern void i915_save_display(struct drm_device *dev); extern void i915_restore_display(struct drm_device *dev); extern int i915_master_create(struct drm_device *dev, struct drm_master *master); diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c index aaabbcbe5905..8cd791dc5b29 100644 --- a/drivers/gpu/drm/i915/intel_fb.c +++ b/drivers/gpu/drm/i915/intel_fb.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "drmP.h" #include "drm.h" @@ -235,6 +236,7 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, obj_priv->gtt_offset, fbo); mutex_unlock(&dev->struct_mutex); + vga_switcheroo_client_fb_set(dev->pdev, info); return 0; out_unpin: diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c index 48227e744753..0e0730a53137 100644 --- a/drivers/gpu/drm/nouveau/nouveau_acpi.c +++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c @@ -11,6 +11,8 @@ #include "nouveau_drm.h" #include "nv50_display.h" +#include + #define NOUVEAU_DSM_SUPPORTED 0x00 #define NOUVEAU_DSM_SUPPORTED_FUNCTIONS 0x00 @@ -28,31 +30,30 @@ #define NOUVEAU_DSM_POWER_SPEED 0x01 #define NOUVEAU_DSM_POWER_STAMINA 0x02 -static int nouveau_dsm(struct drm_device *dev, int func, int arg, int *result) -{ - static char muid[] = { - 0xA0, 0xA0, 0x95, 0x9D, 0x60, 0x00, 0x48, 0x4D, - 0xB3, 0x4D, 0x7E, 0x5F, 0xEA, 0x12, 0x9F, 0xD4, - }; +static struct nouveau_dsm_priv { + bool dsm_detected; + acpi_handle dhandle; + acpi_handle dsm_handle; +} nouveau_dsm_priv; + +static const char nouveau_dsm_muid[] = { + 0xA0, 0xA0, 0x95, 0x9D, 0x60, 0x00, 0x48, 0x4D, + 0xB3, 0x4D, 0x7E, 0x5F, 0xEA, 0x12, 0x9F, 0xD4, +}; - struct pci_dev *pdev = dev->pdev; - struct acpi_handle *handle; +static int nouveau_dsm(acpi_handle handle, int func, int arg, int *result) +{ struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL }; struct acpi_object_list input; union acpi_object params[4]; union acpi_object *obj; int err; - handle = DEVICE_ACPI_HANDLE(&pdev->dev); - - if (!handle) - return -ENODEV; - input.count = 4; input.pointer = params; params[0].type = ACPI_TYPE_BUFFER; - params[0].buffer.length = sizeof(muid); - params[0].buffer.pointer = (char *)muid; + params[0].buffer.length = sizeof(nouveau_dsm_muid); + params[0].buffer.pointer = (char *)nouveau_dsm_muid; params[1].type = ACPI_TYPE_INTEGER; params[1].integer.value = 0x00000102; params[2].type = ACPI_TYPE_INTEGER; @@ -62,7 +63,7 @@ static int nouveau_dsm(struct drm_device *dev, int func, int arg, int *result) err = acpi_evaluate_object(handle, "_DSM", &input, &output); if (err) { - NV_INFO(dev, "failed to evaluate _DSM: %d\n", err); + printk(KERN_INFO "failed to evaluate _DSM: %d\n", err); return err; } @@ -86,40 +87,119 @@ static int nouveau_dsm(struct drm_device *dev, int func, int arg, int *result) return 0; } -int nouveau_hybrid_setup(struct drm_device *dev) +static int nouveau_dsm_switch_mux(acpi_handle handle, int mux_id) { - int result; - - if (nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_STATE, - &result)) - return -ENODEV; - - NV_INFO(dev, "_DSM hardware status gave 0x%x\n", result); - - if (result) { /* Ensure that the external GPU is enabled */ - nouveau_dsm(dev, NOUVEAU_DSM_LED, NOUVEAU_DSM_LED_SPEED, NULL); - nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_SPEED, - NULL); - } else { /* Stamina mode - disable the external GPU */ - nouveau_dsm(dev, NOUVEAU_DSM_LED, NOUVEAU_DSM_LED_STAMINA, - NULL); - nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_STAMINA, - NULL); - } + return nouveau_dsm(handle, NOUVEAU_DSM_LED, mux_id, NULL); +} + +static int nouveau_dsm_set_discrete_state(acpi_handle handle, enum vga_switcheroo_state state) +{ + int arg; + if (state == VGA_SWITCHEROO_ON) + arg = NOUVEAU_DSM_POWER_SPEED; + else + arg = NOUVEAU_DSM_POWER_STAMINA; + nouveau_dsm(handle, NOUVEAU_DSM_POWER, arg, NULL); + return 0; +} + +static int nouveau_dsm_switchto(enum vga_switcheroo_client_id id) +{ + if (id == VGA_SWITCHEROO_IGD) + return nouveau_dsm_switch_mux(nouveau_dsm_priv.dsm_handle, NOUVEAU_DSM_LED_STAMINA); + else + return nouveau_dsm_switch_mux(nouveau_dsm_priv.dsm_handle, NOUVEAU_DSM_LED_SPEED); +} +static int nouveau_dsm_power_state(enum vga_switcheroo_client_id id, + enum vga_switcheroo_state state) +{ + if (id == VGA_SWITCHEROO_IGD) + return 0; + + return nouveau_dsm_set_discrete_state(nouveau_dsm_priv.dsm_handle, state); +} + +static int nouveau_dsm_init(void) +{ return 0; } -bool nouveau_dsm_probe(struct drm_device *dev) +static int nouveau_dsm_get_client_id(struct pci_dev *pdev) { - int support = 0; + if (nouveau_dsm_priv.dhandle == DEVICE_ACPI_HANDLE(&pdev->dev)) + return VGA_SWITCHEROO_IGD; + else + return VGA_SWITCHEROO_DIS; +} + +static struct vga_switcheroo_handler nouveau_dsm_handler = { + .switchto = nouveau_dsm_switchto, + .power_state = nouveau_dsm_power_state, + .init = nouveau_dsm_init, + .get_client_id = nouveau_dsm_get_client_id, +}; - if (nouveau_dsm(dev, NOUVEAU_DSM_SUPPORTED, - NOUVEAU_DSM_SUPPORTED_FUNCTIONS, &support)) +static bool nouveau_dsm_pci_probe(struct pci_dev *pdev) +{ + acpi_handle dhandle, nvidia_handle; + acpi_status status; + int ret; + uint32_t result; + + dhandle = DEVICE_ACPI_HANDLE(&pdev->dev); + if (!dhandle) + return false; + status = acpi_get_handle(dhandle, "_DSM", &nvidia_handle); + if (ACPI_FAILURE(status)) { return false; + } - if (!support) + ret= nouveau_dsm(nvidia_handle, NOUVEAU_DSM_SUPPORTED, + NOUVEAU_DSM_SUPPORTED_FUNCTIONS, &result); + if (ret < 0) return false; + nouveau_dsm_priv.dhandle = dhandle; + nouveau_dsm_priv.dsm_handle = nvidia_handle; return true; } + +static bool nouveau_dsm_detect(void) +{ + char acpi_method_name[255] = { 0 }; + struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name}; + struct pci_dev *pdev = NULL; + int has_dsm = 0; + int vga_count = 0; + while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { + vga_count++; + + has_dsm |= (nouveau_dsm_pci_probe(pdev) == true); + } + + if (vga_count == 2 && has_dsm) { + acpi_get_name(nouveau_dsm_priv.dsm_handle, ACPI_FULL_PATHNAME, &buffer); + printk(KERN_INFO "VGA switcheroo: detected DSM switching method %s handle\n", + acpi_method_name); + nouveau_dsm_priv.dsm_detected = true; + return true; + } + return false; +} + +void nouveau_register_dsm_handler(void) +{ + bool r; + + r = nouveau_dsm_detect(); + if (!r) + return; + + vga_switcheroo_register_handler(&nouveau_dsm_handler); +} + +void nouveau_unregister_dsm_handler(void) +{ + vga_switcheroo_unregister_handler(); +} diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c index da3b93b84502..f83ec65addba 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.c +++ b/drivers/gpu/drm/nouveau/nouveau_drv.c @@ -135,7 +135,7 @@ nouveau_pci_remove(struct pci_dev *pdev) drm_put_dev(dev); } -static int +int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state) { struct drm_device *dev = pci_get_drvdata(pdev); @@ -233,7 +233,7 @@ out_abort: return ret; } -static int +int nouveau_pci_resume(struct pci_dev *pdev) { struct drm_device *dev = pci_get_drvdata(pdev); @@ -402,8 +402,10 @@ static int __init nouveau_init(void) nouveau_modeset = 1; } - if (nouveau_modeset == 1) + if (nouveau_modeset == 1) { driver.driver_features |= DRIVER_MODESET; + nouveau_register_dsm_handler(); + } return drm_init(&driver); } @@ -411,6 +413,7 @@ static int __init nouveau_init(void) static void __exit nouveau_exit(void) { drm_exit(&driver); + nouveau_unregister_dsm_handler(); } module_init(nouveau_init); diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 1c15ef37b71c..85c05feab4f0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -614,7 +614,6 @@ struct drm_nouveau_private { } susres; struct backlight_device *backlight; - bool acpi_dsm; struct nouveau_channel *evo; @@ -682,6 +681,9 @@ extern int nouveau_ignorelid; extern int nouveau_nofbaccel; extern int nouveau_noaccel; +extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); +extern int nouveau_pci_resume(struct pci_dev *pdev); + /* nouveau_state.c */ extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); extern int nouveau_load(struct drm_device *, unsigned long flags); @@ -848,19 +850,8 @@ extern int nouveau_dma_init(struct nouveau_channel *); extern int nouveau_dma_wait(struct nouveau_channel *, int size); /* nouveau_acpi.c */ -#ifdef CONFIG_ACPI -extern int nouveau_hybrid_setup(struct drm_device *dev); -extern bool nouveau_dsm_probe(struct drm_device *dev); -#else -static inline int nouveau_hybrid_setup(struct drm_device *dev) -{ - return 0; -} -static inline bool nouveau_dsm_probe(struct drm_device *dev) -{ - return false; -} -#endif +void nouveau_register_dsm_handler(void); +void nouveau_unregister_dsm_handler(void); /* nouveau_backlight.c */ #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index ea879a2efef3..1ebf22b664dd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -36,6 +36,7 @@ #include #include #include +#include #include "drmP.h" #include "drm.h" @@ -370,6 +371,7 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width, nvbo->bo.offset, nvbo); mutex_unlock(&dev->struct_mutex); + vga_switcheroo_client_fb_set(dev->pdev, info); return 0; out_unref: diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index a4851af5b05e..85d65b91389c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c @@ -29,6 +29,7 @@ #include "drm_sarea.h" #include "drm_crtc_helper.h" #include +#include #include "nouveau_drv.h" #include "nouveau_drm.h" @@ -371,6 +372,30 @@ out_err: return ret; } +static void nouveau_switcheroo_set_state(struct pci_dev *pdev, + enum vga_switcheroo_state state) +{ + pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; + if (state == VGA_SWITCHEROO_ON) { + printk(KERN_ERR "VGA switcheroo: switched nouveau on\n"); + nouveau_pci_resume(pdev); + } else { + printk(KERN_ERR "VGA switcheroo: switched nouveau off\n"); + nouveau_pci_suspend(pdev, pmm); + } +} + +static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev) +{ + struct drm_device *dev = pci_get_drvdata(pdev); + bool can_switch; + + spin_lock(&dev->count_lock); + can_switch = (dev->open_count == 0); + spin_unlock(&dev->count_lock); + return can_switch; +} + int nouveau_card_init(struct drm_device *dev) { @@ -384,6 +409,8 @@ nouveau_card_init(struct drm_device *dev) return 0; vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode); + vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state, + nouveau_switcheroo_can_switch); /* Initialise internal driver API hooks */ ret = nouveau_init_engine_ptrs(dev); @@ -617,11 +644,6 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n", dev->pci_vendor, dev->pci_device, dev->pdev->class); - dev_priv->acpi_dsm = nouveau_dsm_probe(dev); - - if (dev_priv->acpi_dsm) - nouveau_hybrid_setup(dev); - dev_priv->wq = create_workqueue("nouveau"); if (!dev_priv->wq) return -EINVAL; diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 1cc7b937b1ea..8e62fe13e31c 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -54,7 +54,8 @@ radeon-y += radeon_device.o radeon_kms.o \ radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \ r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ - r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o + r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \ + radeon_atpx_handler.o radeon-$(CONFIG_COMPAT) += radeon_ioc32.o diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index c0356bb193e5..a5dfb1557d3e 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -118,6 +118,10 @@ struct radeon_device; /* * BIOS. */ +#define ATRM_BIOS_PAGE 4096 + +bool radeon_atrm_supported(struct pci_dev *pdev); +int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); bool radeon_get_bios(struct radeon_device *rdev); @@ -838,6 +842,8 @@ struct radeon_device { int audio_bits_per_sample; uint8_t audio_status_bits; uint8_t audio_category_code; + + bool powered_down; }; int radeon_device_init(struct radeon_device *rdev, @@ -1042,6 +1048,8 @@ extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enabl extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); +extern int radeon_resume_kms(struct drm_device *dev); +extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ struct r100_mc_save { diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c new file mode 100644 index 000000000000..0ae52f19071d --- /dev/null +++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2010 Red Hat Inc. + * Author : Dave Airlie + * + * Licensed under GPLv2 + * + * ATPX support for both Intel/ATI + */ + +#include +#include +#include +#include + +#define ATPX_VERSION 0 +#define ATPX_GPU_PWR 2 +#define ATPX_MUX_SELECT 3 + +#define ATPX_INTEGRATED 0 +#define ATPX_DISCRETE 1 + +#define ATPX_MUX_IGD 0 +#define ATPX_MUX_DISCRETE 1 + +static struct radeon_atpx_priv { + bool atpx_detected; + /* handle for device - and atpx */ + acpi_handle dhandle; + acpi_handle atpx_handle; + acpi_handle atrm_handle; +} radeon_atpx_priv; + +/* retrieve the ROM in 4k blocks */ +static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, + int offset, int len) +{ + acpi_status status; + union acpi_object atrm_arg_elements[2], *obj; + struct acpi_object_list atrm_arg; + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; + + atrm_arg.count = 2; + atrm_arg.pointer = &atrm_arg_elements[0]; + + atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; + atrm_arg_elements[0].integer.value = offset; + + atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; + atrm_arg_elements[1].integer.value = len; + + status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); + if (ACPI_FAILURE(status)) { + printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); + return -ENODEV; + } + + obj = (union acpi_object *)buffer.pointer; + memcpy(bios+offset, obj->buffer.pointer, len); + kfree(buffer.pointer); + return len; +} + +bool radeon_atrm_supported(struct pci_dev *pdev) +{ + /* get the discrete ROM only via ATRM */ + if (!radeon_atpx_priv.atpx_detected) + return false; + + if (radeon_atpx_priv.dhandle == DEVICE_ACPI_HANDLE(&pdev->dev)) + return false; + return true; +} + + +int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len) +{ + return radeon_atrm_call(radeon_atpx_priv.atrm_handle, bios, offset, len); +} + +static int radeon_atpx_get_version(acpi_handle handle) +{ + acpi_status status; + union acpi_object atpx_arg_elements[2], *obj; + struct acpi_object_list atpx_arg; + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + + atpx_arg.count = 2; + atpx_arg.pointer = &atpx_arg_elements[0]; + + atpx_arg_elements[0].type = ACPI_TYPE_INTEGER; + atpx_arg_elements[0].integer.value = ATPX_VERSION; + + atpx_arg_elements[1].type = ACPI_TYPE_INTEGER; + atpx_arg_elements[1].integer.value = ATPX_VERSION; + + status = acpi_evaluate_object(handle, NULL, &atpx_arg, &buffer); + if (ACPI_FAILURE(status)) { + printk("%s: failed to call ATPX: %s\n", __func__, acpi_format_exception(status)); + return -ENOSYS; + } + obj = (union acpi_object *)buffer.pointer; + if (obj && (obj->type == ACPI_TYPE_BUFFER)) + printk(KERN_INFO "radeon atpx: version is %d\n", *((u8 *)(obj->buffer.pointer) + 2)); + kfree(buffer.pointer); + return 0; +} + +static int radeon_atpx_execute(acpi_handle handle, int cmd_id, u16 value) +{ + acpi_status status; + union acpi_object atpx_arg_elements[2]; + struct acpi_object_list atpx_arg; + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + uint8_t buf[4] = {0}; + + if (!handle) + return -EINVAL; + + atpx_arg.count = 2; + atpx_arg.pointer = &atpx_arg_elements[0]; + + atpx_arg_elements[0].type = ACPI_TYPE_INTEGER; + atpx_arg_elements[0].integer.value = cmd_id; + + buf[2] = value & 0xff; + buf[3] = (value >> 8) & 0xff; + + atpx_arg_elements[1].type = ACPI_TYPE_BUFFER; + atpx_arg_elements[1].buffer.length = 4; + atpx_arg_elements[1].buffer.pointer = buf; + + status = acpi_evaluate_object(handle, NULL, &atpx_arg, &buffer); + if (ACPI_FAILURE(status)) { + printk("%s: failed to call ATPX: %s\n", __func__, acpi_format_exception(status)); + return -ENOSYS; + } + kfree(buffer.pointer); + + return 0; +} + +static int radeon_atpx_set_discrete_state(acpi_handle handle, int state) +{ + return radeon_atpx_execute(handle, ATPX_GPU_PWR, state); +} + +static int radeon_atpx_switch_mux(acpi_handle handle, int mux_id) +{ + return radeon_atpx_execute(handle, ATPX_MUX_SELECT, mux_id); +} + + +static int radeon_atpx_switchto(enum vga_switcheroo_client_id id) +{ + if (id == VGA_SWITCHEROO_IGD) + radeon_atpx_switch_mux(radeon_atpx_priv.atpx_handle, 0); + else + radeon_atpx_switch_mux(radeon_atpx_priv.atpx_handle, 1); + return 0; +} + +static int radeon_atpx_power_state(enum vga_switcheroo_client_id id, + enum vga_switcheroo_state state) +{ + /* on w500 ACPI can't change intel gpu state */ + if (id == VGA_SWITCHEROO_IGD) + return 0; + + radeon_atpx_set_discrete_state(radeon_atpx_priv.atpx_handle, state); + return 0; +} + +static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev) +{ + acpi_handle dhandle, atpx_handle, atrm_handle; + acpi_status status; + + dhandle = DEVICE_ACPI_HANDLE(&pdev->dev); + if (!dhandle) + return false; + + status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); + if (ACPI_FAILURE(status)) + return false; + + status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); + if (ACPI_FAILURE(status)) + return false; + + radeon_atpx_priv.dhandle = dhandle; + radeon_atpx_priv.atpx_handle = atpx_handle; + radeon_atpx_priv.atrm_handle = atrm_handle; + return true; +} + +static int radeon_atpx_init(void) +{ + /* set up the ATPX handle */ + + radeon_atpx_get_version(radeon_atpx_priv.atpx_handle); + return 0; +} + +static int radeon_atpx_get_client_id(struct pci_dev *pdev) +{ + if (radeon_atpx_priv.dhandle == DEVICE_ACPI_HANDLE(&pdev->dev)) + return VGA_SWITCHEROO_IGD; + else + return VGA_SWITCHEROO_DIS; +} + +static struct vga_switcheroo_handler radeon_atpx_handler = { + .switchto = radeon_atpx_switchto, + .power_state = radeon_atpx_power_state, + .init = radeon_atpx_init, + .get_client_id = radeon_atpx_get_client_id, +}; + +static bool radeon_atpx_detect(void) +{ + char acpi_method_name[255] = { 0 }; + struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name}; + struct pci_dev *pdev = NULL; + bool has_atpx = false; + int vga_count = 0; + + while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { + vga_count++; + + has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true); + } + + if (has_atpx && vga_count == 2) { + acpi_get_name(radeon_atpx_priv.atpx_handle, ACPI_FULL_PATHNAME, &buffer); + printk(KERN_INFO "VGA switcheroo: detected switching method %s handle\n", + acpi_method_name); + radeon_atpx_priv.atpx_detected = true; + return true; + } + return false; +} + +void radeon_register_atpx_handler(void) +{ + bool r; + + /* detect if we have any ATPX + 2 VGA in the system */ + r = radeon_atpx_detect(); + if (!r) + return; + + vga_switcheroo_register_handler(&radeon_atpx_handler); +} + +void radeon_unregister_atpx_handler(void) +{ + vga_switcheroo_unregister_handler(); +} diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c index 906921740c60..a34b909485b8 100644 --- a/drivers/gpu/drm/radeon/radeon_bios.c +++ b/drivers/gpu/drm/radeon/radeon_bios.c @@ -30,6 +30,7 @@ #include "radeon.h" #include "atom.h" +#include /* * BIOS. */ @@ -62,7 +63,7 @@ static bool igp_read_bios_from_vram(struct radeon_device *rdev) iounmap(bios); return false; } - memcpy(rdev->bios, bios, size); + memcpy_fromio(rdev->bios, bios, size); iounmap(bios); return true; } @@ -93,6 +94,38 @@ static bool radeon_read_bios(struct radeon_device *rdev) return true; } +/* ATRM is used to get the BIOS on the discrete cards in + * dual-gpu systems. + */ +static bool radeon_atrm_get_bios(struct radeon_device *rdev) +{ + int ret; + int size = 64 * 1024; + int i; + + if (!radeon_atrm_supported(rdev->pdev)) + return false; + + rdev->bios = kmalloc(size, GFP_KERNEL); + if (!rdev->bios) { + DRM_ERROR("Unable to allocate bios\n"); + return false; + } + + for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { + ret = radeon_atrm_get_bios_chunk(rdev->bios, + (i * ATRM_BIOS_PAGE), + ATRM_BIOS_PAGE); + if (ret <= 0) + break; + } + + if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { + kfree(rdev->bios); + return false; + } + return true; +} static bool r700_read_disabled_bios(struct radeon_device *rdev) { uint32_t viph_control; @@ -388,16 +421,16 @@ static bool radeon_read_disabled_bios(struct radeon_device *rdev) return legacy_read_disabled_bios(rdev); } + bool radeon_get_bios(struct radeon_device *rdev) { bool r; uint16_t tmp; - if (rdev->flags & RADEON_IS_IGP) { + r = radeon_atrm_get_bios(rdev); + if (r == false) r = igp_read_bios_from_vram(rdev); - if (r == false) - r = radeon_read_bios(rdev); - } else + if (r == false) r = radeon_read_bios(rdev); if (r == false) { r = radeon_read_disabled_bios(rdev); @@ -408,6 +441,7 @@ bool radeon_get_bios(struct radeon_device *rdev) return false; } if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { + printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); goto free_bios; } diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 768b1509fa03..cb8d9a1dd69c 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "radeon_reg.h" #include "radeon.h" #include "radeon_asic.h" @@ -613,6 +614,36 @@ void radeon_check_arguments(struct radeon_device *rdev) } } +static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) +{ + struct drm_device *dev = pci_get_drvdata(pdev); + struct radeon_device *rdev = dev->dev_private; + pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; + if (state == VGA_SWITCHEROO_ON) { + printk(KERN_INFO "radeon: switched on\n"); + /* don't suspend or resume card normally */ + rdev->powered_down = false; + radeon_resume_kms(dev); + } else { + printk(KERN_INFO "radeon: switched off\n"); + radeon_suspend_kms(dev, pmm); + /* don't suspend or resume card normally */ + rdev->powered_down = true; + } +} + +static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) +{ + struct drm_device *dev = pci_get_drvdata(pdev); + bool can_switch; + + spin_lock(&dev->count_lock); + can_switch = (dev->open_count == 0); + spin_unlock(&dev->count_lock); + return can_switch; +} + + int radeon_device_init(struct radeon_device *rdev, struct drm_device *ddev, struct pci_dev *pdev, @@ -692,6 +723,9 @@ int radeon_device_init(struct radeon_device *rdev, /* this will fail for cards that aren't VGA class devices, just * ignore it */ vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); + vga_switcheroo_register_client(rdev->pdev, + radeon_switcheroo_set_state, + radeon_switcheroo_can_switch); r = radeon_init(rdev); if (r) @@ -723,6 +757,7 @@ void radeon_device_fini(struct radeon_device *rdev) rdev->shutdown = true; radeon_fini(rdev); destroy_workqueue(rdev->wq); + vga_switcheroo_unregister_client(rdev->pdev); vga_client_register(rdev->pdev, NULL, NULL, NULL); iounmap(rdev->rmmio); rdev->rmmio = NULL; @@ -746,6 +781,8 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) } rdev = dev->dev_private; + if (rdev->powered_down) + return 0; /* unpin the front buffers */ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); @@ -791,6 +828,9 @@ int radeon_resume_kms(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; + if (rdev->powered_down) + return 0; + acquire_console_sem(); pci_set_power_state(dev->pdev, PCI_D0); pci_restore_state(dev->pdev); diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 8ba3de7994d4..4ab53aa163b2 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -339,6 +339,7 @@ static int __init radeon_init(void) driver = &kms_driver; driver->driver_features |= DRIVER_MODESET; driver->num_ioctls = radeon_max_kms_ioctl; + radeon_register_atpx_handler(); } /* if the vga console setting is enabled still * let modprobe override it */ @@ -348,6 +349,7 @@ static int __init radeon_init(void) static void __exit radeon_exit(void) { drm_exit(driver); + radeon_unregister_atpx_handler(); } module_init(radeon_init); diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index c57ad606504d..736237195143 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h @@ -455,6 +455,9 @@ extern void r600_blit_swap(struct drm_device *dev, int sx, int sy, int dx, int dy, int w, int h, int src_pitch, int dst_pitch, int cpp); +/* atpx handler */ +void radeon_register_atpx_handler(void); +void radeon_unregister_atpx_handler(void); /* Flags for stats.boxes */ #define RADEON_BOX_DMA_IDLE 0x1 diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index d71e346e9ab5..561719223988 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -39,6 +39,8 @@ #include "drm_fb_helper.h" +#include + struct radeon_fb_device { struct drm_fb_helper helper; struct radeon_framebuffer *rfb; @@ -291,6 +293,7 @@ int radeonfb_create(struct drm_device *dev, rfbdev->rdev = rdev; mutex_unlock(&rdev->ddev->struct_mutex); + vga_switcheroo_client_fb_set(rdev->ddev->pdev, info); return 0; out_unref: diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index f23b05606eb5..5db7af6b91f4 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c @@ -30,6 +30,8 @@ #include "radeon.h" #include "radeon_drm.h" +#include + int radeon_driver_unload_kms(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; @@ -136,6 +138,7 @@ int radeon_driver_firstopen_kms(struct drm_device *dev) void radeon_driver_lastclose_kms(struct drm_device *dev) { + vga_switcheroo_process_delayed_switch(); } int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) diff --git a/drivers/gpu/vga/Kconfig b/drivers/gpu/vga/Kconfig index 790e675b13eb..6116a0196214 100644 --- a/drivers/gpu/vga/Kconfig +++ b/drivers/gpu/vga/Kconfig @@ -8,3 +8,16 @@ config VGA_ARB are accessed at same time they need some kind of coordination. Please see Documentation/vgaarbiter.txt for more details. Select this to enable VGA arbiter. + +config VGA_SWITCHEROO + bool "Laptop Hybrid Grapics - GPU switching support" + default y + depends on X86 + depends on ACPI + help + Many laptops released in 2008/9/10 have two gpus with a multiplxer + to switch between them. This adds support for dynamic switching when + X isn't running and delayed switching until the next logoff. This + features is called hybrid graphics, ATI PowerXpress, and Nvidia + HybridPower. + diff --git a/drivers/gpu/vga/Makefile b/drivers/gpu/vga/Makefile index 7cc8c1ed645b..14ca30b75d0a 100644 --- a/drivers/gpu/vga/Makefile +++ b/drivers/gpu/vga/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_VGA_ARB) += vgaarb.o +obj-$(CONFIG_VGA_SWITCHEROO) += vga_switcheroo.o diff --git a/drivers/gpu/vga/vga_switcheroo.c b/drivers/gpu/vga/vga_switcheroo.c new file mode 100644 index 000000000000..a3f587a0aba9 --- /dev/null +++ b/drivers/gpu/vga/vga_switcheroo.c @@ -0,0 +1,453 @@ +/* + * Copyright (c) 2010 Red Hat Inc. + * Author : Dave Airlie + * + * + * Licensed under GPLv2 + * + * vga_switcheroo.c - Support for laptop with dual GPU using one set of outputs + + Switcher interface - methods require for ATPX and DCM + - switchto - this throws the output MUX switch + - discrete_set_power - sets the power state for the discrete card + + GPU driver interface + - set_gpu_state - this should do the equiv of s/r for the card + - this should *not* set the discrete power state + - switch_check - check if the device is in a position to switch now + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +struct vga_switcheroo_client { + struct pci_dev *pdev; + struct fb_info *fb_info; + int pwr_state; + void (*set_gpu_state)(struct pci_dev *pdev, enum vga_switcheroo_state); + bool (*can_switch)(struct pci_dev *pdev); + int id; + bool active; +}; + +static DEFINE_MUTEX(vgasr_mutex); + +struct vgasr_priv { + + bool active; + bool delayed_switch_active; + enum vga_switcheroo_client_id delayed_client_id; + + struct dentry *debugfs_root; + struct dentry *switch_file; + + int registered_clients; + struct vga_switcheroo_client clients[VGA_SWITCHEROO_MAX_CLIENTS]; + + struct vga_switcheroo_handler *handler; +}; + +static int vga_switcheroo_debugfs_init(struct vgasr_priv *priv); +static void vga_switcheroo_debugfs_fini(struct vgasr_priv *priv); + +/* only one switcheroo per system */ +static struct vgasr_priv vgasr_priv; + +int vga_switcheroo_register_handler(struct vga_switcheroo_handler *handler) +{ + mutex_lock(&vgasr_mutex); + if (vgasr_priv.handler) { + mutex_unlock(&vgasr_mutex); + return -EINVAL; + } + + vgasr_priv.handler = handler; + mutex_unlock(&vgasr_mutex); + return 0; +} +EXPORT_SYMBOL(vga_switcheroo_register_handler); + +void vga_switcheroo_unregister_handler(void) +{ + mutex_lock(&vgasr_mutex); + vgasr_priv.handler = NULL; + mutex_unlock(&vgasr_mutex); +} +EXPORT_SYMBOL(vga_switcheroo_unregister_handler); + +static void vga_switcheroo_enable(void) +{ + int i; + int ret; + /* call the handler to init */ + vgasr_priv.handler->init(); + + for (i = 0; i < VGA_SWITCHEROO_MAX_CLIENTS; i++) { + ret = vgasr_priv.handler->get_client_id(vgasr_priv.clients[i].pdev); + if (ret < 0) + return; + + vgasr_priv.clients[i].id = ret; + } + vga_switcheroo_debugfs_init(&vgasr_priv); + vgasr_priv.active = true; +} + +int vga_switcheroo_register_client(struct pci_dev *pdev, + void (*set_gpu_state)(struct pci_dev *pdev, enum vga_switcheroo_state), + bool (*can_switch)(struct pci_dev *pdev)) +{ + int index; + + mutex_lock(&vgasr_mutex); + /* don't do IGD vs DIS here */ + if (vgasr_priv.registered_clients & 1) + index = 1; + else + index = 0; + + vgasr_priv.clients[index].pwr_state = VGA_SWITCHEROO_ON; + vgasr_priv.clients[index].pdev = pdev; + vgasr_priv.clients[index].set_gpu_state = set_gpu_state; + vgasr_priv.clients[index].can_switch = can_switch; + vgasr_priv.clients[index].id = -1; + if (pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW) + vgasr_priv.clients[index].active = true; + + vgasr_priv.registered_clients |= (1 << index); + + /* if we get two clients + handler */ + if (vgasr_priv.registered_clients == 0x3 && vgasr_priv.handler) { + printk(KERN_INFO "vga_switcheroo: enabled\n"); + vga_switcheroo_enable(); + } + mutex_unlock(&vgasr_mutex); + return 0; +} +EXPORT_SYMBOL(vga_switcheroo_register_client); + +void vga_switcheroo_unregister_client(struct pci_dev *pdev) +{ + int i; + + mutex_lock(&vgasr_mutex); + for (i = 0; i < VGA_SWITCHEROO_MAX_CLIENTS; i++) { + if (vgasr_priv.clients[i].pdev == pdev) { + vgasr_priv.registered_clients &= ~(1 << i); + break; + } + } + + printk(KERN_INFO "vga_switcheroo: disabled\n"); + vga_switcheroo_debugfs_fini(&vgasr_priv); + vgasr_priv.active = false; + mutex_unlock(&vgasr_mutex); +} +EXPORT_SYMBOL(vga_switcheroo_unregister_client); + +void vga_switcheroo_client_fb_set(struct pci_dev *pdev, + struct fb_info *info) +{ + int i; + + mutex_lock(&vgasr_mutex); + for (i = 0; i < VGA_SWITCHEROO_MAX_CLIENTS; i++) { + if (vgasr_priv.clients[i].pdev == pdev) { + vgasr_priv.clients[i].fb_info = info; + break; + } + } + mutex_unlock(&vgasr_mutex); +} +EXPORT_SYMBOL(vga_switcheroo_client_fb_set); + +static int vga_switcheroo_show(struct seq_file *m, void *v) +{ + int i; + mutex_lock(&vgasr_mutex); + for (i = 0; i < VGA_SWITCHEROO_MAX_CLIENTS; i++) { + seq_printf(m, "%d:%c:%s:%s\n", i, + vgasr_priv.clients[i].active ? '+' : ' ', + vgasr_priv.clients[i].pwr_state ? "Pwr" : "Off", + pci_name(vgasr_priv.clients[i].pdev)); + } + mutex_unlock(&vgasr_mutex); + return 0; +} + +static int vga_switcheroo_debugfs_open(struct inode *inode, struct file *file) +{ + return single_open(file, vga_switcheroo_show, NULL); +} + +static int vga_switchon(struct vga_switcheroo_client *client) +{ + int ret; + + ret = vgasr_priv.handler->power_state(client->id, VGA_SWITCHEROO_ON); + /* call the driver callback to turn on device */ + client->set_gpu_state(client->pdev, VGA_SWITCHEROO_ON); + client->pwr_state = VGA_SWITCHEROO_ON; + return 0; +} + +static int vga_switchoff(struct vga_switcheroo_client *client) +{ + /* call the driver callback to turn off device */ + client->set_gpu_state(client->pdev, VGA_SWITCHEROO_OFF); + vgasr_priv.handler->power_state(client->id, VGA_SWITCHEROO_OFF); + client->pwr_state = VGA_SWITCHEROO_OFF; + return 0; +} + +static int vga_switchto(struct vga_switcheroo_client *new_client) +{ + int ret; + int i; + struct vga_switcheroo_client *active = NULL; + + if (new_client->active == true) + return 0; + + for (i = 0; i < VGA_SWITCHEROO_MAX_CLIENTS; i++) { + if (vgasr_priv.clients[i].active == true) { + active = &vgasr_priv.clients[i]; + break; + } + } + if (!active) + return 0; + + /* power up the first device */ + ret = pci_enable_device(new_client->pdev); + if (ret) + return ret; + + if (new_client->pwr_state == VGA_SWITCHEROO_OFF) + vga_switchon(new_client); + + /* swap shadow resource to denote boot VGA device has changed so X starts on new device */ + active->active = false; + + active->pdev->resource[PCI_ROM_RESOURCE].flags &= ~IORESOURCE_ROM_SHADOW; + new_client->pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW; + + if (new_client->fb_info) { + struct fb_event event; + event.info = new_client->fb_info; + fb_notifier_call_chain(FB_EVENT_REMAP_ALL_CONSOLE, &event); + } + + ret = vgasr_priv.handler->switchto(new_client->id); + if (ret) + return ret; + + if (active->pwr_state == VGA_SWITCHEROO_ON) + vga_switchoff(active); + + new_client->active = true; + return 0; +} + +static ssize_t +vga_switcheroo_debugfs_write(struct file *filp, const char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + char usercmd[64]; + const char *pdev_name; + int i, ret; + bool delay = false, can_switch; + int client_id = -1; + struct vga_switcheroo_client *client = NULL; + + if (cnt > 63) + cnt = 63; + + if (copy_from_user(usercmd, ubuf, cnt)) + return -EFAULT; + + mutex_lock(&vgasr_mutex); + + if (!vgasr_priv.active) + return -EINVAL; + + /* pwr off the device not in use */ + if (strncmp(usercmd, "OFF", 3) == 0) { + for (i = 0; i < VGA_SWITCHEROO_MAX_CLIENTS; i++) { + if (vgasr_priv.clients[i].active) + continue; + if (vgasr_priv.clients[i].pwr_state == VGA_SWITCHEROO_ON) + vga_switchoff(&vgasr_priv.clients[i]); + } + goto out; + } + /* pwr on the device not in use */ + if (strncmp(usercmd, "ON", 2) == 0) { + for (i = 0; i < VGA_SWITCHEROO_MAX_CLIENTS; i++) { + if (vgasr_priv.clients[i].active) + continue; + if (vgasr_priv.clients[i].pwr_state == VGA_SWITCHEROO_OFF) + vga_switchon(&vgasr_priv.clients[i]); + } + goto out; + } + + /* request a delayed switch - test can we switch now */ + if (strncmp(usercmd, "DIGD", 4) == 0) { + client_id = VGA_SWITCHEROO_IGD; + delay = true; + } + + if (strncmp(usercmd, "DDIS", 4) == 0) { + client_id = VGA_SWITCHEROO_DIS; + delay = true; + } + + if (strncmp(usercmd, "IGD", 3) == 0) + client_id = VGA_SWITCHEROO_IGD; + + if (strncmp(usercmd, "DIS", 3) == 0) + client_id = VGA_SWITCHEROO_DIS; + + if (client_id == -1) + goto out; + + for (i = 0; i < VGA_SWITCHEROO_MAX_CLIENTS; i++) { + if (vgasr_priv.clients[i].id == client_id) { + client = &vgasr_priv.clients[i]; + break; + } + } + + vgasr_priv.delayed_switch_active = false; + /* okay we want a switch - test if devices are willing to switch */ + can_switch = true; + for (i = 0; i < VGA_SWITCHEROO_MAX_CLIENTS; i++) { + can_switch = vgasr_priv.clients[i].can_switch(vgasr_priv.clients[i].pdev); + if (can_switch == false) { + printk(KERN_ERR "vga_switcheroo: client %d refused switch\n", i); + break; + } + } + + if (can_switch == false && delay == false) + goto out; + + if (can_switch == true) { + pdev_name = pci_name(client->pdev); + ret = vga_switchto(client); + if (ret) + printk(KERN_ERR "vga_switcheroo: switching failed %d\n", ret); + } else { + printk(KERN_INFO "vga_switcheroo: setting delayed switch to client %d\n", client->id); + vgasr_priv.delayed_switch_active = true; + vgasr_priv.delayed_client_id = client_id; + + /* we should at least power up the card to + make the switch faster */ + if (client->pwr_state == VGA_SWITCHEROO_OFF) + vga_switchon(client); + } + +out: + mutex_unlock(&vgasr_mutex); + return cnt; +} + +static const struct file_operations vga_switcheroo_debugfs_fops = { + .owner = THIS_MODULE, + .open = vga_switcheroo_debugfs_open, + .write = vga_switcheroo_debugfs_write, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static void vga_switcheroo_debugfs_fini(struct vgasr_priv *priv) +{ + if (priv->switch_file) { + debugfs_remove(priv->switch_file); + priv->switch_file = NULL; + } + if (priv->debugfs_root) { + debugfs_remove(priv->debugfs_root); + priv->debugfs_root = NULL; + } +} + +static int vga_switcheroo_debugfs_init(struct vgasr_priv *priv) +{ + /* already initialised */ + if (priv->debugfs_root) + return 0; + priv->debugfs_root = debugfs_create_dir("vgaswitcheroo", NULL); + + if (!priv->debugfs_root) { + printk(KERN_ERR "vga_switcheroo: Cannot create /sys/kernel/debug/vgaswitcheroo\n"); + goto fail; + } + + priv->switch_file = debugfs_create_file("switch", 0644, + priv->debugfs_root, NULL, &vga_switcheroo_debugfs_fops); + if (!priv->switch_file) { + printk(KERN_ERR "vga_switcheroo: cannot create /sys/kernel/debug/vgaswitcheroo/switch\n"); + goto fail; + } + return 0; +fail: + vga_switcheroo_debugfs_fini(priv); + return -1; +} + +int vga_switcheroo_process_delayed_switch(void) +{ + struct vga_switcheroo_client *client = NULL; + const char *pdev_name; + bool can_switch = true; + int i; + int ret; + int err = -EINVAL; + + mutex_lock(&vgasr_mutex); + if (!vgasr_priv.delayed_switch_active) + goto err; + + printk(KERN_INFO "vga_switcheroo: processing delayed switch to %d\n", vgasr_priv.delayed_client_id); + + for (i = 0; i < VGA_SWITCHEROO_MAX_CLIENTS; i++) { + if (vgasr_priv.clients[i].id == vgasr_priv.delayed_client_id) + client = &vgasr_priv.clients[i]; + can_switch = vgasr_priv.clients[i].can_switch(vgasr_priv.clients[i].pdev); + if (can_switch == false) { + printk(KERN_ERR "vga_switcheroo: client %d refused switch\n", i); + break; + } + } + + if (can_switch == false || client == NULL) + goto err; + + pdev_name = pci_name(client->pdev); + ret = vga_switchto(client); + if (ret) + printk(KERN_ERR "vga_switcheroo: delayed switching failed %d\n", ret); + + vgasr_priv.delayed_switch_active = false; + err = 0; +err: + mutex_unlock(&vgasr_mutex); + return err; +} +EXPORT_SYMBOL(vga_switcheroo_process_delayed_switch); + diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c index 3681c6a88212..b0a3fa00706d 100644 --- a/drivers/video/console/fbcon.c +++ b/drivers/video/console/fbcon.c @@ -3025,6 +3025,20 @@ static int fbcon_fb_unregistered(struct fb_info *info) return 0; } +static void fbcon_remap_all(int idx) +{ + int i; + for (i = first_fb_vc; i <= last_fb_vc; i++) + set_con2fb_map(i, idx, 0); + + if (con_is_bound(&fb_con)) { + printk(KERN_INFO "fbcon: Remapping primary device, " + "fb%i, to tty %i-%i\n", idx, + first_fb_vc + 1, last_fb_vc + 1); + info_idx = idx; + } +} + #ifdef CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY static void fbcon_select_primary(struct fb_info *info) { @@ -3225,6 +3239,10 @@ static int fbcon_event_notify(struct notifier_block *self, caps = event->data; fbcon_get_requirement(info, caps); break; + case FB_EVENT_REMAP_ALL_CONSOLE: + idx = info->node; + fbcon_remap_all(idx); + break; } done: return ret; diff --git a/include/linux/fb.h b/include/linux/fb.h index 369767bd873e..c10163b4c40e 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -543,6 +543,8 @@ struct fb_cursor_user { #define FB_EVENT_GET_REQ 0x0D /* Unbind from the console if possible */ #define FB_EVENT_FB_UNBIND 0x0E +/* CONSOLE-SPECIFIC: remap all consoles to new fb - for vga switcheroo */ +#define FB_EVENT_REMAP_ALL_CONSOLE 0x0F struct fb_event { struct fb_info *info; diff --git a/include/linux/vga_switcheroo.h b/include/linux/vga_switcheroo.h new file mode 100644 index 000000000000..4b58ab1e8612 --- /dev/null +++ b/include/linux/vga_switcheroo.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2010 Red Hat Inc. + * Author : Dave Airlie + * + * Licensed under GPLv2 + * + * vga_switcheroo.h - Support for laptop with dual GPU using one set of outputs + */ + +#include +#include + +enum vga_switcheroo_state { + VGA_SWITCHEROO_OFF, + VGA_SWITCHEROO_ON, +}; + +enum vga_switcheroo_client_id { + VGA_SWITCHEROO_IGD, + VGA_SWITCHEROO_DIS, + VGA_SWITCHEROO_MAX_CLIENTS, +}; + +struct vga_switcheroo_handler { + int (*switchto)(enum vga_switcheroo_client_id id); + int (*power_state)(enum vga_switcheroo_client_id id, + enum vga_switcheroo_state state); + int (*init)(void); + int (*get_client_id)(struct pci_dev *pdev); +}; + + +#if defined(CONFIG_VGA_SWITCHEROO) +void vga_switcheroo_unregister_client(struct pci_dev *dev); +int vga_switcheroo_register_client(struct pci_dev *dev, + void (*set_gpu_state)(struct pci_dev *dev, enum vga_switcheroo_state), + bool (*can_switch)(struct pci_dev *dev)); + +void vga_switcheroo_client_fb_set(struct pci_dev *dev, + struct fb_info *info); + +int vga_switcheroo_register_handler(struct vga_switcheroo_handler *handler); +void vga_switcheroo_unregister_handler(void); + +int vga_switcheroo_process_delayed_switch(void); + +#else + +static inline void vga_switcheroo_unregister_client(struct pci_dev *dev) {} +static inline int vga_switcheroo_register_client(struct pci_dev *dev, + void (*set_gpu_state)(struct pci_dev *dev, enum vga_switcheroo_state), + bool (*can_switch)(struct pci_dev *dev)) { return 0; } +static inline void vga_switcheroo_client_fb_set(struct pci_dev *dev, struct fb_info *info) {} +static inline int vga_switcheroo_register_handler(struct vga_switcheroo_handler *handler) { return 0; } +static inline void vga_switcheroo_unregister_handler(void) {} +static inline int vga_switcheroo_process_delayed_switch(void) { return 0; } + +#endif -- cgit v1.2.3 From 0de1a57bedce0899c98da4c0910d4f38c9b7c8f4 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 1 Mar 2010 16:32:15 +1000 Subject: drm/radeon/kms: bump the KMS version number for square tiling support. Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_drv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index f6456e02d1fe..6eec0ece6a6c 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -40,9 +40,11 @@ /* * KMS wrapper. + * - 2.0.0 - initial interface + * - 2.1.0 - add square tiling interface */ #define KMS_DRIVER_MAJOR 2 -#define KMS_DRIVER_MINOR 0 +#define KMS_DRIVER_MINOR 1 #define KMS_DRIVER_PATCHLEVEL 0 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); int radeon_driver_unload_kms(struct drm_device *dev); -- cgit v1.2.3 From 55a5cb5d594c18b3147a2288b00ea359c1a38cf8 Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Mon, 1 Mar 2010 11:37:11 +0200 Subject: drm/radeon: Fix printf type warning in 64bit system. Type of iterator was promoted to unsigned long in 64bit systems. *header is small structure so it is alwas safe to cast return value of sizeof operator to int. Signed-off-by: Pauli Nieminen --- drivers/gpu/drm/radeon/r300_cmdbuf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c index 7f59352cd637..ea46d558e8f3 100644 --- a/drivers/gpu/drm/radeon/r300_cmdbuf.c +++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c @@ -767,7 +767,7 @@ static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv, default: DRM_ERROR("bad packet3 type %i at byte %d\n", header.packet3.packet, - cmdbuf->buffer->iterator - sizeof(header)); + cmdbuf->buffer->iterator - (int)sizeof(header)); return -EINVAL; } @@ -1153,7 +1153,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, default: DRM_ERROR("bad cmd_type %i at byte %d\n", header->header.cmd_type, - cmdbuf->buffer->iterator - sizeof(*header)); + cmdbuf->buffer->iterator - (int)sizeof(*header)); ret = -EINVAL; goto cleanup; } -- cgit v1.2.3 From 8edb381d6705811b278527907a5ae2a9c4db8074 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 1 Mar 2010 21:50:01 +1100 Subject: vga_switcheroo: fix build on platforms with no ACPI radeon was always including the atpx code unnecessarily, also core switcheroo was including acpi headers. Signed-off-by: Dave Airlie --- drivers/gpu/drm/nouveau/nouveau_drv.h | 5 +++++ drivers/gpu/drm/radeon/Makefile | 3 ++- drivers/gpu/drm/radeon/radeon.h | 11 +++++++++++ drivers/gpu/drm/radeon/radeon_atpx_handler.c | 1 - drivers/gpu/drm/radeon/radeon_drv.h | 6 ++++++ drivers/gpu/vga/vga_switcheroo.c | 3 --- include/linux/vga_switcheroo.h | 1 - 7 files changed, 24 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index a2e24f252e84..f5b3cbe7dc80 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -852,8 +852,13 @@ extern int nouveau_dma_init(struct nouveau_channel *); extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); /* nouveau_acpi.c */ +#if defined(CONFIG_VGA_SWITCHEROO) void nouveau_register_dsm_handler(void); void nouveau_unregister_dsm_handler(void); +#else +static inline void nouveau_register_dsm_handler(void) {} +static inline void nouveau_unregister_dsm_handler(void) {} +#endif /* nouveau_backlight.c */ #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 0a4d526e4f44..0adf49eea7fa 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -60,8 +60,9 @@ radeon-y += radeon_device.o radeon_kms.o \ rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \ r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \ - evergreen.o radeon_atpx_handler.o + evergreen.o radeon-$(CONFIG_COMPAT) += radeon_ioc32.o +radeon-$(CONFIG_VGA_SWITCHEROO) += radone_atpx_handler.o obj-$(CONFIG_DRM_RADEON)+= radeon.o diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index ad9d55f94398..829e26e8a4bb 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -121,8 +121,19 @@ struct radeon_device; */ #define ATRM_BIOS_PAGE 4096 +#if defined(CONFIG_VGA_SWITCHEROO) bool radeon_atrm_supported(struct pci_dev *pdev); int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); +#else +static inline bool radeon_atrm_supported(struct pci_dev *pdev) +{ + return false; +} + +static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ + return -EINVAL; +} +#endif bool radeon_get_bios(struct radeon_device *rdev); diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c index 0ae52f19071d..3f557c4151e0 100644 --- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c +++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c @@ -6,7 +6,6 @@ * * ATPX support for both Intel/ATI */ - #include #include #include diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index 4fe16461bb1b..ec55f2b23c22 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h @@ -463,8 +463,14 @@ extern void r600_blit_swap(struct drm_device *dev, int w, int h, int src_pitch, int dst_pitch, int cpp); /* atpx handler */ +#if defined(CONFIG_VGA_SWITCHEROO) void radeon_register_atpx_handler(void); void radeon_unregister_atpx_handler(void); +#else +static inline void radeon_register_atpx_handler(void) {} +static inline void radeon_unregister_atpx_handler(void) {} +#endif + /* Flags for stats.boxes */ #define RADEON_BOX_DMA_IDLE 0x1 diff --git a/drivers/gpu/vga/vga_switcheroo.c b/drivers/gpu/vga/vga_switcheroo.c index a3f587a0aba9..d6d1149d525d 100644 --- a/drivers/gpu/vga/vga_switcheroo.c +++ b/drivers/gpu/vga/vga_switcheroo.c @@ -25,9 +25,6 @@ #include #include -#include -#include - #include #include diff --git a/include/linux/vga_switcheroo.h b/include/linux/vga_switcheroo.h index 4b58ab1e8612..ae9ab13b963d 100644 --- a/include/linux/vga_switcheroo.h +++ b/include/linux/vga_switcheroo.h @@ -7,7 +7,6 @@ * vga_switcheroo.h - Support for laptop with dual GPU using one set of outputs */ -#include #include enum vga_switcheroo_state { -- cgit v1.2.3 From 1d40ddd10dab332456e3863fed2a6e71aa6635ab Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 1 Mar 2010 16:19:23 +0000 Subject: MTD: fix pismo build error Signed-off-by: Russell King --- drivers/mtd/maps/pismo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/maps/pismo.c b/drivers/mtd/maps/pismo.c index c48cad271f5d..30e12c88d1da 100644 --- a/drivers/mtd/maps/pismo.c +++ b/drivers/mtd/maps/pismo.c @@ -118,7 +118,7 @@ static int __devinit pismo_add_device(struct pismo_data *pismo, int i, { struct platform_device *dev; struct resource res = { }; - phys_addr_t base = region.base; + phys_addr_t base = region->base; int ret; if (base == ~0) -- cgit v1.2.3 From 9b11fe5f4902c3f26b0d7d9ad5bd46eae624cf32 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 1 Mar 2010 14:23:31 -0500 Subject: drm/radeon: fix typo in Makefile Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 0adf49eea7fa..ed38262d9985 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -63,6 +63,6 @@ radeon-y += radeon_device.o radeon_kms.o \ evergreen.o radeon-$(CONFIG_COMPAT) += radeon_ioc32.o -radeon-$(CONFIG_VGA_SWITCHEROO) += radone_atpx_handler.o +radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o obj-$(CONFIG_DRM_RADEON)+= radeon.o -- cgit v1.2.3 From da8065ac3ea29d1bfdb5a163be346fbe35066f8d Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Thu, 4 Feb 2010 17:13:55 -0800 Subject: [ARM] locomo: avoid unnecessary cascaded keyboard IRQ It is not necessary and is over-complicated for IRQ_LOCOMO_KEY to be a cascaded IRQ of IRQ_LOCOMO_KEY_BASE. Removed and introduced locomokbd_{open,close} for masking/unmasking of the keyboard IRQ. Signed-off-by: Eric Miao --- arch/arm/common/locomo.c | 63 +++----------------------------- arch/arm/mach-pxa/include/mach/irqs.h | 3 +- arch/arm/mach-sa1100/include/mach/irqs.h | 3 +- drivers/input/keyboard/locomokbd.c | 32 +++++++++++++++- 4 files changed, 39 insertions(+), 62 deletions(-) (limited to 'drivers') diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index bd36c778c819..96cd0730167d 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -143,12 +143,10 @@ static struct locomo_dev_info locomo_devices[] = { * IRQ_LOCOMO_*_BASE and those handlers generate more interrupts * * hardware irq reads LOCOMO_ICR & 0x0f00 - * IRQ_LOCOMO_KEY_BASE + * IRQ_LOCOMO_KEY * IRQ_LOCOMO_GPIO_BASE * IRQ_LOCOMO_LT_BASE * IRQ_LOCOMO_SPI_BASE - * IRQ_LOCOMO_KEY_BASE reads LOCOMO_KIC & 0x0001 - * IRQ_LOCOMO_KEY * IRQ_LOCOMO_GPIO_BASE reads LOCOMO_GIR & LOCOMO_GPD & 0xffff * IRQ_LOCOMO_GPIO[0-15] * IRQ_LOCOMO_LT_BASE reads LOCOMO_LTINT & 0x0001 @@ -160,8 +158,7 @@ static struct locomo_dev_info locomo_devices[] = { * IRQ_LOCOMO_SPI_TEND */ -#define LOCOMO_IRQ_START (IRQ_LOCOMO_KEY_BASE) -#define LOCOMO_IRQ_KEY_START (IRQ_LOCOMO_KEY) +#define LOCOMO_IRQ_START (IRQ_LOCOMO_KEY) #define LOCOMO_IRQ_GPIO_START (IRQ_LOCOMO_GPIO0) #define LOCOMO_IRQ_LT_START (IRQ_LOCOMO_LT) #define LOCOMO_IRQ_SPI_START (IRQ_LOCOMO_SPI_RFR) @@ -218,49 +215,6 @@ static struct irq_chip locomo_chip = { .unmask = locomo_unmask_irq, }; -static void locomo_key_handler(unsigned int irq, struct irq_desc *desc) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - - if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) { - generic_handle_irq(LOCOMO_IRQ_KEY_START); - } -} - -static void locomo_key_ack_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); - r &= ~(0x0100 << (irq - LOCOMO_IRQ_KEY_START)); - locomo_writel(r, mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); -} - -static void locomo_key_mask_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); - r &= ~(0x0010 << (irq - LOCOMO_IRQ_KEY_START)); - locomo_writel(r, mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); -} - -static void locomo_key_unmask_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); - r |= (0x0010 << (irq - LOCOMO_IRQ_KEY_START)); - locomo_writel(r, mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); -} - -static struct irq_chip locomo_key_chip = { - .name = "LOCOMO-key", - .ack = locomo_key_ack_irq, - .mask = locomo_key_mask_irq, - .unmask = locomo_key_unmask_irq, -}; - static void locomo_gpio_handler(unsigned int irq, struct irq_desc *desc) { int req, i; @@ -468,9 +422,10 @@ static void locomo_setup_irq(struct locomo *lchip) set_irq_chained_handler(lchip->irq, locomo_handler); /* Install handlers for IRQ_LOCOMO_*_BASE */ - set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip); - set_irq_chip_data(IRQ_LOCOMO_KEY_BASE, irqbase); - set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler); + set_irq_chip(IRQ_LOCOMO_KEY, &locomo_chip); + set_irq_chip_data(IRQ_LOCOMO_KEY, irqbase); + set_irq_handler(IRQ_LOCOMO_KEY, handle_edge_irq); + set_irq_flags(IRQ_LOCOMO_KEY, IRQF_VALID | IRQF_PROBE); set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip); set_irq_chip_data(IRQ_LOCOMO_GPIO_BASE, irqbase); @@ -484,12 +439,6 @@ static void locomo_setup_irq(struct locomo *lchip) set_irq_chip_data(IRQ_LOCOMO_SPI_BASE, irqbase); set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler); - /* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */ - set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip); - set_irq_chip_data(LOCOMO_IRQ_KEY_START, irqbase); - set_irq_handler(LOCOMO_IRQ_KEY_START, handle_edge_irq); - set_irq_flags(LOCOMO_IRQ_KEY_START, IRQF_VALID | IRQF_PROBE); - /* install handlers for IRQ_LOCOMO_GPIO_BASE generated interrupts */ for (irq = LOCOMO_IRQ_GPIO_START; irq < LOCOMO_IRQ_GPIO_START + 16; irq++) { set_irq_chip(irq, &locomo_gpio_chip); diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index 3677a9af9c87..33a4f33de271 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -188,7 +188,6 @@ #define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54) #define IRQ_LOCOMO_START (IRQ_BOARD_END) -#define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0) #define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1) #define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2) #define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3) @@ -274,7 +273,7 @@ #define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) /* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */ -#define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0) +#define IRQ_LOCOMO_KEY (IRQ_BOARD_START + 0) #define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) #define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) #define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h index ae81f80b0cf9..9731c7814a32 100644 --- a/arch/arm/mach-sa1100/include/mach/irqs.h +++ b/arch/arm/mach-sa1100/include/mach/irqs.h @@ -121,7 +121,6 @@ #define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54) #define IRQ_LOCOMO_START (IRQ_BOARD_END) -#define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0) #define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1) #define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2) #define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3) @@ -168,7 +167,7 @@ #define IRQ_NEPONSET_SA1111 (IRQ_BOARD_START + 2) /* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */ -#define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0) +#define IRQ_LOCOMO_KEY (IRQ_BOARD_START + 0) #define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) #define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) #define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) diff --git a/drivers/input/keyboard/locomokbd.c b/drivers/input/keyboard/locomokbd.c index 9caed30f3bbb..b1ab29861e1c 100644 --- a/drivers/input/keyboard/locomokbd.c +++ b/drivers/input/keyboard/locomokbd.c @@ -192,11 +192,18 @@ static void locomokbd_scankeyboard(struct locomokbd *locomokbd) static irqreturn_t locomokbd_interrupt(int irq, void *dev_id) { struct locomokbd *locomokbd = dev_id; + u16 r; + + r = locomo_readl(locomokbd->base + LOCOMO_KIC); + if ((r & 0x0001) == 0) + return IRQ_HANDLED; + + locomo_writel(r & ~0x0100, locomokbd->base + LOCOMO_KIC); /* Ack */ + /** wait chattering delay **/ udelay(100); locomokbd_scankeyboard(locomokbd); - return IRQ_HANDLED; } @@ -210,6 +217,25 @@ static void locomokbd_timer_callback(unsigned long data) locomokbd_scankeyboard(locomokbd); } +static int locomokbd_open(struct input_dev *dev) +{ + struct locomokbd *locomokbd = input_get_drvdata(dev); + u16 r; + + r = locomo_readl(locomokbd->base + LOCOMO_KIC) | 0x0010; + locomo_writel(r, locomokbd->base + LOCOMO_KIC); + return 0; +} + +static void locomokbd_close(struct input_dev *dev) +{ + struct locomokbd *locomokbd = input_get_drvdata(dev); + u16 r; + + r = locomo_readl(locomokbd->base + LOCOMO_KIC) & ~0x0010; + locomo_writel(r, locomokbd->base + LOCOMO_KIC); +} + static int __devinit locomokbd_probe(struct locomo_dev *dev) { struct locomokbd *locomokbd; @@ -253,6 +279,8 @@ static int __devinit locomokbd_probe(struct locomo_dev *dev) input_dev->id.vendor = 0x0001; input_dev->id.product = 0x0001; input_dev->id.version = 0x0100; + input_dev->open = locomokbd_open; + input_dev->close = locomokbd_close; input_dev->dev.parent = &dev->dev; input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP) | @@ -261,6 +289,8 @@ static int __devinit locomokbd_probe(struct locomo_dev *dev) input_dev->keycodesize = sizeof(locomokbd_keycode[0]); input_dev->keycodemax = ARRAY_SIZE(locomokbd_keycode); + input_set_drvdata(input_dev, locomokbd); + memcpy(locomokbd->keycode, locomokbd_keycode, sizeof(locomokbd->keycode)); for (i = 0; i < LOCOMOKBD_NUMKEYS; i++) set_bit(locomokbd->keycode[i], input_dev->keybit); -- cgit v1.2.3 From 08fa159003aa510027951671b94aadc380ab2d2a Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Sat, 26 Dec 2009 12:32:38 +0800 Subject: [ARM] sa1111: avoid using hardcoded IRQ numbers for PCMCIA driver The IRQs for card detect and status change are currently hardcoded in SA1111 PCMCIA driver, which can be actually obtained from the .irq[] from 'struct sa1111_dev' to keep it generic. Signed-off-by: Eric Miao --- drivers/pcmcia/sa1111_generic.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/pcmcia/sa1111_generic.c b/drivers/pcmcia/sa1111_generic.c index de6bc333d299..db79ca61cf96 100644 --- a/drivers/pcmcia/sa1111_generic.c +++ b/drivers/pcmcia/sa1111_generic.c @@ -21,11 +21,18 @@ #include "sa1111_generic.h" +#define IDX_IRQ_S0_READY_NINT (0) +#define IDX_IRQ_S0_CD_VALID (1) +#define IDX_IRQ_S0_BVD1_STSCHG (2) +#define IDX_IRQ_S1_READY_NINT (3) +#define IDX_IRQ_S1_CD_VALID (4) +#define IDX_IRQ_S1_BVD1_STSCHG (5) + static struct pcmcia_irqs irqs[] = { - { 0, IRQ_S0_CD_VALID, "SA1111 PCMCIA card detect" }, - { 0, IRQ_S0_BVD1_STSCHG, "SA1111 PCMCIA BVD1" }, - { 1, IRQ_S1_CD_VALID, "SA1111 CF card detect" }, - { 1, IRQ_S1_BVD1_STSCHG, "SA1111 CF BVD1" }, + { 0, NO_IRQ, "SA1111 PCMCIA card detect" }, + { 0, NO_IRQ, "SA1111 PCMCIA BVD1" }, + { 1, NO_IRQ, "SA1111 CF card detect" }, + { 1, NO_IRQ, "SA1111 CF BVD1" }, }; static int sa1111_pcmcia_hw_init(struct soc_pcmcia_socket *skt) @@ -136,7 +143,9 @@ int sa1111_pcmcia_add(struct sa1111_dev *dev, struct pcmcia_low_level *ops, s->soc.ops = ops; s->soc.socket.owner = ops->owner; s->soc.socket.dev.parent = &dev->dev; - s->soc.socket.pci_irq = s->soc.nr ? IRQ_S1_READY_NINT : IRQ_S0_READY_NINT; + s->soc.socket.pci_irq = s->soc.nr ? + dev->irq[IDX_IRQ_S0_READY_NINT] : + dev->irq[IDX_IRQ_S1_READY_NINT]; s->dev = dev; ret = add(&s->soc); @@ -162,6 +171,12 @@ static int pcmcia_probe(struct sa1111_dev *dev) base = dev->mapbase; + /* Initialize PCMCIA IRQs */ + irqs[0].irq = dev->irq[IDX_IRQ_S0_CD_VALID]; + irqs[1].irq = dev->irq[IDX_IRQ_S0_BVD1_STSCHG]; + irqs[2].irq = dev->irq[IDX_IRQ_S1_CD_VALID]; + irqs[3].irq = dev->irq[IDX_IRQ_S1_BVD1_STSCHG]; + /* * Initialise the suspend state. */ -- cgit v1.2.3 From 0dc726bb264ca5ecfdfab94a6937e0e9b9b26f64 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Sun, 27 Dec 2009 23:01:25 +0800 Subject: [ARM] pxa: move board board IRQ definitions out of irqs.h Signed-off-by: Eric Miao --- arch/arm/include/asm/hardware/it8152.h | 12 ++++++ arch/arm/mach-pxa/include/mach/balloon3.h | 10 +++++ arch/arm/mach-pxa/include/mach/irqs.h | 67 +----------------------------- arch/arm/mach-pxa/include/mach/lpd270.h | 4 ++ arch/arm/mach-pxa/include/mach/lubbock.h | 11 +++++ arch/arm/mach-pxa/include/mach/mainstone.h | 17 ++++++++ arch/arm/mach-pxa/include/mach/pcm027.h | 7 ++++ drivers/usb/gadget/pxa25x_udc.c | 4 ++ 8 files changed, 66 insertions(+), 66 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h index 74b5fff7f575..6700c7fc7ebd 100644 --- a/arch/arm/include/asm/hardware/it8152.h +++ b/arch/arm/include/asm/hardware/it8152.h @@ -75,6 +75,18 @@ extern unsigned long it8152_base_address; IT8152_PD_IRQ(1) USB (USBR) IT8152_PD_IRQ(0) Audio controller (ACR) */ +#define IT8152_IRQ(x) (IRQ_BOARD_END + (x)) + +/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */ +#define IT8152_LD_IRQ_COUNT 9 +#define IT8152_LP_IRQ_COUNT 16 +#define IT8152_PD_IRQ_COUNT 15 + +/* Priorities: */ +#define IT8152_PD_IRQ(i) IT8152_IRQ(i) +#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT) +#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT) + /* frequently used interrupts */ #define IT8152_PCISERR IT8152_PD_IRQ(14) #define IT8152_H2PTADR IT8152_PD_IRQ(13) diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h index bfec09b1814b..1a741065045f 100644 --- a/arch/arm/mach-pxa/include/mach/balloon3.h +++ b/arch/arm/mach-pxa/include/mach/balloon3.h @@ -129,6 +129,16 @@ enum balloon3_features { #define CPLD_AROUTING_LOONR2INT_BIT 6 #define CPLD_AROUTING_LOONR2EXT_BIT 7 +/* Balloon3 Interrupts */ +#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x)) + +#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0) +#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1) + +#define BALLOON3_AUX_NIRQ IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ) +#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) +#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) + extern int balloon3_has(enum balloon3_features feature); #endif diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index b35b3ac86e45..ffc8314520f2 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -150,74 +150,9 @@ #define NR_IRQS (IRQ_BOARD_START) #endif -/* - * Board specific IRQs. Define them here. - * Do not surround them with ifdefs. - */ -#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x)) -#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) -#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) -#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ -#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3) -#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4) -#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5) -#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ -#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) - -#define LPD270_IRQ(x) (IRQ_BOARD_START + (x)) -#define LPD270_USBC_IRQ LPD270_IRQ(2) -#define LPD270_ETHERNET_IRQ LPD270_IRQ(3) -#define LPD270_AC97_IRQ LPD270_IRQ(4) - -#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) -#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) -#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) -#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) -#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3) -#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4) -#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5) -#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6) -#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7) -#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9) -#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10) -#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11) -#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) -#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) -#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) - -/* Balloon3 Interrupts */ -#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x)) - -#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0) -#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1) - -#define BALLOON3_AUX_NIRQ IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ) -#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) -#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) - -/* phyCORE-PXA270 (PCM027) Interrupts */ -#define PCM027_IRQ(x) (IRQ_BOARD_START + (x)) -#define PCM027_BTDET_IRQ PCM027_IRQ(0) -#define PCM027_FF_RI_IRQ PCM027_IRQ(1) -#define PCM027_MMCDET_IRQ PCM027_IRQ(2) -#define PCM027_PM_5V_IRQ PCM027_IRQ(3) - -/* ITE8152 irqs */ /* add IT8152 IRQs beyond BOARD_END */ #ifdef CONFIG_PCI_HOST_ITE8152 -#define IT8152_IRQ(x) (IRQ_BOARD_END + (x)) - -/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */ -#define IT8152_LD_IRQ_COUNT 9 -#define IT8152_LP_IRQ_COUNT 16 -#define IT8152_PD_IRQ_COUNT 15 - -/* Priorities: */ -#define IT8152_PD_IRQ(i) IT8152_IRQ(i) -#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT) -#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT) - -#define IT8152_LAST_IRQ IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1) +#define IT8152_LAST_IRQ (IRQ_BOARD_END + 40) #if NR_IRQS < (IT8152_LAST_IRQ+1) #undef NR_IRQS diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h index f89fb715266b..0e6440c81683 100644 --- a/arch/arm/mach-pxa/include/mach/lpd270.h +++ b/arch/arm/mach-pxa/include/mach/lpd270.h @@ -34,5 +34,9 @@ #define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ #define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */ +#define LPD270_IRQ(x) (IRQ_BOARD_START + (x)) +#define LPD270_USBC_IRQ LPD270_IRQ(2) +#define LPD270_ETHERNET_IRQ LPD270_IRQ(3) +#define LPD270_AC97_IRQ LPD270_IRQ(4) #endif diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h index 751b74811d0f..a0d4247f08fc 100644 --- a/arch/arm/mach-pxa/include/mach/lubbock.h +++ b/arch/arm/mach-pxa/include/mach/lubbock.h @@ -34,6 +34,17 @@ #define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0) #define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100) +/* Board specific IRQs */ +#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x)) +#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) +#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) +#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ +#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3) +#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4) +#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5) +#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ +#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) + #ifndef __ASSEMBLY__ extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set); #endif diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h index 3461c4302ff4..86e623abd64d 100644 --- a/arch/arm/mach-pxa/include/mach/mainstone.h +++ b/arch/arm/mach-pxa/include/mach/mainstone.h @@ -117,4 +117,21 @@ #define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */ #define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ +/* board specific IRQs */ +#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) +#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) +#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) +#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) +#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3) +#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4) +#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5) +#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6) +#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7) +#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9) +#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10) +#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11) +#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) +#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) +#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) + #endif diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h index 4dcd2e8baa61..04083263167e 100644 --- a/arch/arm/mach-pxa/include/mach/pcm027.h +++ b/arch/arm/mach-pxa/include/mach/pcm027.h @@ -23,6 +23,13 @@ * Definitions of CPU card resources only */ +/* phyCORE-PXA270 (PCM027) Interrupts */ +#define PCM027_IRQ(x) (IRQ_BOARD_START + (x)) +#define PCM027_BTDET_IRQ PCM027_IRQ(0) +#define PCM027_FF_RI_IRQ PCM027_IRQ(1) +#define PCM027_MMCDET_IRQ PCM027_IRQ(2) +#define PCM027_PM_5V_IRQ PCM027_IRQ(3) + /* I2C RTC */ #define PCM027_RTC_IRQ_GPIO 0 #define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO) diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c index e6fedbd5a654..be5fb34d9602 100644 --- a/drivers/usb/gadget/pxa25x_udc.c +++ b/drivers/usb/gadget/pxa25x_udc.c @@ -65,6 +65,10 @@ #include #endif +#ifdef CONFIG_ARCH_LUBBOCK +#include +#endif + #include -- cgit v1.2.3 From 47a4dc26eeb89a3746f9b1e2092602b40469640a Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 11 Feb 2010 16:50:05 +0000 Subject: dmaengine: shdma: fix DMA error handling. Present DMA error ISR in shdma.c is bogus, it locks the system hard in multiple ways. Fix it to abort all queued transactions on all channels on the affected controller and giving submitters a chance to get a DMA_ERROR status for aborted transactions. Afterwards further functionality is again possible without the need to re-load the driver. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt --- drivers/dma/shdma.c | 89 +++++++++++++++++++++++++++++++---------------------- 1 file changed, 53 insertions(+), 36 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c index b75ce8b84c46..77311698c046 100644 --- a/drivers/dma/shdma.c +++ b/drivers/dma/shdma.c @@ -73,7 +73,7 @@ static void sh_dmae_ctl_stop(int id) { unsigned short dmaor = dmaor_read_reg(id); - dmaor &= ~(DMAOR_NMIF | DMAOR_AE); + dmaor &= ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME); dmaor_write_reg(id, dmaor); } @@ -86,7 +86,7 @@ static int sh_dmae_rst(int id) dmaor_write_reg(id, dmaor); if (dmaor_read_reg(id) & (DMAOR_AE | DMAOR_NMIF)) { - pr_warning(KERN_ERR "dma-sh: Can't initialize DMAOR.\n"); + pr_warning("dma-sh: Can't initialize DMAOR.\n"); return -EINVAL; } return 0; @@ -661,7 +661,7 @@ static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all) static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan) { - struct sh_desc *sd; + struct sh_desc *desc; spin_lock_bh(&sh_chan->desc_lock); /* DMA work check */ @@ -671,10 +671,10 @@ static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan) } /* Find the first not transferred desciptor */ - list_for_each_entry(sd, &sh_chan->ld_queue, node) - if (sd->mark == DESC_SUBMITTED) { + list_for_each_entry(desc, &sh_chan->ld_queue, node) + if (desc->mark == DESC_SUBMITTED) { /* Get the ld start address from ld_queue */ - dmae_set_reg(sh_chan, &sd->hw); + dmae_set_reg(sh_chan, &desc->hw); dmae_start(sh_chan); break; } @@ -696,6 +696,7 @@ static enum dma_status sh_dmae_is_complete(struct dma_chan *chan, struct sh_dmae_chan *sh_chan = to_sh_chan(chan); dma_cookie_t last_used; dma_cookie_t last_complete; + enum dma_status status; sh_dmae_chan_ld_cleanup(sh_chan, false); @@ -709,7 +710,27 @@ static enum dma_status sh_dmae_is_complete(struct dma_chan *chan, if (used) *used = last_used; - return dma_async_is_complete(cookie, last_complete, last_used); + spin_lock_bh(&sh_chan->desc_lock); + + status = dma_async_is_complete(cookie, last_complete, last_used); + + /* + * If we don't find cookie on the queue, it has been aborted and we have + * to report error + */ + if (status != DMA_SUCCESS) { + struct sh_desc *desc; + status = DMA_ERROR; + list_for_each_entry(desc, &sh_chan->ld_queue, node) + if (desc->cookie == cookie) { + status = DMA_IN_PROGRESS; + break; + } + } + + spin_unlock_bh(&sh_chan->desc_lock); + + return status; } static irqreturn_t sh_dmae_interrupt(int irq, void *data) @@ -732,40 +753,36 @@ static irqreturn_t sh_dmae_interrupt(int irq, void *data) #if defined(CONFIG_CPU_SH4) static irqreturn_t sh_dmae_err(int irq, void *data) { - int err = 0; struct sh_dmae_device *shdev = (struct sh_dmae_device *)data; + int i; - /* IRQ Multi */ - if (shdev->pdata.mode & SHDMA_MIX_IRQ) { - int __maybe_unused cnt = 0; - switch (irq) { -#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ) - case DMTE6_IRQ: - cnt++; -#endif - case DMTE0_IRQ: - if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) { - disable_irq(irq); - return IRQ_HANDLED; + /* halt the dma controller */ + sh_dmae_ctl_stop(0); + if (shdev->pdata.mode & SHDMA_DMAOR1) + sh_dmae_ctl_stop(1); + + /* We cannot detect, which channel caused the error, have to reset all */ + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + struct sh_dmae_chan *sh_chan = shdev->chan[i]; + if (sh_chan) { + struct sh_desc *desc; + /* Stop the channel */ + dmae_halt(sh_chan); + /* Complete all */ + list_for_each_entry(desc, &sh_chan->ld_queue, node) { + struct dma_async_tx_descriptor *tx = &desc->async_tx; + desc->mark = DESC_IDLE; + if (tx->callback) + tx->callback(tx->callback_param); } - default: - return IRQ_NONE; + list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free); } - } else { - /* reset dma controller */ - err = sh_dmae_rst(0); - if (err) - return err; -#ifdef SH_DMAC_BASE1 - if (shdev->pdata.mode & SHDMA_DMAOR1) { - err = sh_dmae_rst(1); - if (err) - return err; - } -#endif - disable_irq(irq); - return IRQ_HANDLED; } + sh_dmae_rst(0); + if (shdev->pdata.mode & SHDMA_DMAOR1) + sh_dmae_rst(1); + + return IRQ_HANDLED; } #endif -- cgit v1.2.3 From 027811b9b81a6b3ae5aa20c3302897bee9dcf09e Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 11 Feb 2010 16:50:10 +0000 Subject: dmaengine: shdma: convert to platform device resources The shdma dmaengine driver currently uses numerous macros to support various platforms, selected by ifdef's. Convert it to use platform device resources and lists of channel descriptors to specify register locations, interrupt numbers and other system-specific configuration variants. Unavoidably, we have to simultaneously convert all shdma users to provide those resources. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt --- arch/sh/include/asm/dma-sh.h | 13 +- arch/sh/kernel/cpu/sh4a/setup-sh7722.c | 70 +++++++- arch/sh/kernel/cpu/sh4a/setup-sh7724.c | 159 ++++++++++++++++- arch/sh/kernel/cpu/sh4a/setup-sh7780.c | 113 +++++++++++- arch/sh/kernel/cpu/sh4a/setup-sh7785.c | 113 +++++++++++- drivers/dma/shdma.c | 318 ++++++++++++++++++++------------- drivers/dma/shdma.h | 6 +- 7 files changed, 636 insertions(+), 156 deletions(-) (limited to 'drivers') diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h index e934a2e66651..2e3631d6e273 100644 --- a/arch/sh/include/asm/dma-sh.h +++ b/arch/sh/include/asm/dma-sh.h @@ -154,10 +154,17 @@ struct sh_dmae_slave_config { char mid_rid; }; +struct sh_dmae_channel { + unsigned int offset; + unsigned int dmars; + unsigned int dmars_bit; +}; + struct sh_dmae_pdata { - unsigned int mode; - struct sh_dmae_slave_config *config; - int config_num; + struct sh_dmae_slave_config *slave; + int slave_num; + struct sh_dmae_channel *channel; + int channel_num; }; struct device; diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index 538280a3dc66..aec182bed8a1 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c @@ -75,15 +75,79 @@ static struct sh_dmae_slave_config sh7722_dmae_slaves[] = { }, }; +static struct sh_dmae_channel sh7722_dmae_channels[] = { + { + .offset = 0, + .dmars = 0, + .dmars_bit = 0, + }, { + .offset = 0x10, + .dmars = 0, + .dmars_bit = 8, + }, { + .offset = 0x20, + .dmars = 4, + .dmars_bit = 0, + }, { + .offset = 0x30, + .dmars = 4, + .dmars_bit = 8, + }, { + .offset = 0x50, + .dmars = 8, + .dmars_bit = 0, + }, { + .offset = 0x60, + .dmars = 8, + .dmars_bit = 8, + } +}; + static struct sh_dmae_pdata dma_platform_data = { - .mode = 0, - .config = sh7722_dmae_slaves, - .config_num = ARRAY_SIZE(sh7722_dmae_slaves), + .slave = sh7722_dmae_slaves, + .slave_num = ARRAY_SIZE(sh7722_dmae_slaves), + .channel = sh7722_dmae_channels, + .channel_num = ARRAY_SIZE(sh7722_dmae_channels), +}; + +static struct resource sh7722_dmae_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xfe008020, + .end = 0xfe00808f, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* DMARSx */ + .start = 0xfe009000, + .end = 0xfe00900b, + .flags = IORESOURCE_MEM, + }, + { + /* DMA error IRQ */ + .start = 78, + .end = 78, + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 0-3 */ + .start = 48, + .end = 51, + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 4-5 */ + .start = 76, + .end = 77, + .flags = IORESOURCE_IRQ, + }, }; struct platform_device dma_device = { .name = "sh-dma-engine", .id = -1, + .resource = sh7722_dmae_resources, + .num_resources = ARRAY_SIZE(sh7722_dmae_resources), .dev = { .platform_data = &dma_platform_data, }, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 31e3451f7e3d..aca1fb2c571b 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c @@ -28,15 +28,157 @@ #include /* DMA */ -static struct sh_dmae_pdata dma_platform_data = { - .mode = SHDMA_DMAOR1, +static struct sh_dmae_channel sh7724_dmae0_channels[] = { + { + .offset = 0, + .dmars = 0, + .dmars_bit = 0, + }, { + .offset = 0x10, + .dmars = 0, + .dmars_bit = 8, + }, { + .offset = 0x20, + .dmars = 4, + .dmars_bit = 0, + }, { + .offset = 0x30, + .dmars = 4, + .dmars_bit = 8, + }, { + .offset = 0x50, + .dmars = 8, + .dmars_bit = 0, + }, { + .offset = 0x60, + .dmars = 8, + .dmars_bit = 8, + } +}; + +static struct sh_dmae_channel sh7724_dmae1_channels[] = { + { + .offset = 0, + .dmars = 0, + .dmars_bit = 0, + }, { + .offset = 0x10, + .dmars = 0, + .dmars_bit = 8, + }, { + .offset = 0x20, + .dmars = 4, + .dmars_bit = 0, + }, { + .offset = 0x30, + .dmars = 4, + .dmars_bit = 8, + }, { + .offset = 0x50, + .dmars = 8, + .dmars_bit = 0, + }, { + .offset = 0x60, + .dmars = 8, + .dmars_bit = 8, + } +}; + +static struct sh_dmae_pdata dma0_platform_data = { + .channel = sh7724_dmae0_channels, + .channel_num = ARRAY_SIZE(sh7724_dmae0_channels), +}; + +static struct sh_dmae_pdata dma1_platform_data = { + .channel = sh7724_dmae1_channels, + .channel_num = ARRAY_SIZE(sh7724_dmae1_channels), +}; + +/* Resource order important! */ +static struct resource sh7724_dmae0_resources[] = { + { + /* Channel registers and DMAOR */ + .start = 0xfe008020, + .end = 0xfe00808f, + .flags = IORESOURCE_MEM, + }, + { + /* DMARSx */ + .start = 0xfe009000, + .end = 0xfe00900b, + .flags = IORESOURCE_MEM, + }, + { + /* DMA error IRQ */ + .start = 78, + .end = 78, + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 0-3 */ + .start = 48, + .end = 51, + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 4-5 */ + .start = 76, + .end = 77, + .flags = IORESOURCE_IRQ, + }, }; -static struct platform_device dma_device = { - .name = "sh-dma-engine", - .id = -1, - .dev = { - .platform_data = &dma_platform_data, +/* Resource order important! */ +static struct resource sh7724_dmae1_resources[] = { + { + /* Channel registers and DMAOR */ + .start = 0xfdc08020, + .end = 0xfdc0808f, + .flags = IORESOURCE_MEM, + }, + { + /* DMARSx */ + .start = 0xfdc09000, + .end = 0xfdc0900b, + .flags = IORESOURCE_MEM, + }, + { + /* DMA error IRQ */ + .start = 74, + .end = 74, + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 0-3 */ + .start = 40, + .end = 43, + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 4-5 */ + .start = 72, + .end = 73, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dma0_device = { + .name = "sh-dma-engine", + .id = 0, + .resource = sh7724_dmae0_resources, + .num_resources = ARRAY_SIZE(sh7724_dmae0_resources), + .dev = { + .platform_data = &dma0_platform_data, + }, +}; + +static struct platform_device dma1_device = { + .name = "sh-dma-engine", + .id = 1, + .resource = sh7724_dmae1_resources, + .num_resources = ARRAY_SIZE(sh7724_dmae1_resources), + .dev = { + .platform_data = &dma1_platform_data, }, }; @@ -663,7 +805,8 @@ static struct platform_device *sh7724_devices[] __initdata = { &tmu3_device, &tmu4_device, &tmu5_device, - &dma_device, + &dma0_device, + &dma1_device, &rtc_device, &iic0_device, &iic1_device, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c index f8f21618d785..338dfc2c2bb5 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c @@ -247,15 +247,115 @@ static struct platform_device rtc_device = { .resource = rtc_resources, }; -static struct sh_dmae_pdata dma_platform_data = { - .mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1), +/* DMA */ +static struct sh_dmae_channel sh7780_dmae0_channels[] = { + { + .offset = 0, + .dmars = 0, + .dmars_bit = 0, + }, { + .offset = 0x10, + .dmars = 0, + .dmars_bit = 8, + }, { + .offset = 0x20, + .dmars = 4, + .dmars_bit = 0, + }, { + .offset = 0x30, + .dmars = 4, + .dmars_bit = 8, + }, { + .offset = 0x50, + .dmars = 8, + .dmars_bit = 0, + }, { + .offset = 0x60, + .dmars = 8, + .dmars_bit = 8, + } +}; + +static struct sh_dmae_channel sh7780_dmae1_channels[] = { + { + .offset = 0, + }, { + .offset = 0x10, + }, { + .offset = 0x20, + }, { + .offset = 0x30, + }, { + .offset = 0x50, + }, { + .offset = 0x60, + } +}; + +static struct sh_dmae_pdata dma0_platform_data = { + .channel = sh7780_dmae0_channels, + .channel_num = ARRAY_SIZE(sh7780_dmae0_channels), +}; + +static struct sh_dmae_pdata dma1_platform_data = { + .channel = sh7780_dmae1_channels, + .channel_num = ARRAY_SIZE(sh7780_dmae1_channels), +}; + +static struct resource sh7780_dmae0_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xfc808020, + .end = 0xfc80808f, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* DMARSx */ + .start = 0xfc809000, + .end = 0xfc80900b, + .flags = IORESOURCE_MEM, + }, + { + /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */ + .start = 34, + .end = 34, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, +}; + +static struct resource sh7780_dmae1_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xfc818020, + .end = 0xfc81808f, + .flags = IORESOURCE_MEM, + }, + /* DMAC1 has no DMARS */ + { + /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */ + .start = 46, + .end = 46, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, }; -static struct platform_device dma_device = { +static struct platform_device dma0_device = { .name = "sh-dma-engine", - .id = -1, + .id = 0, + .resource = sh7780_dmae0_resources, + .num_resources = ARRAY_SIZE(sh7780_dmae0_resources), .dev = { - .platform_data = &dma_platform_data, + .platform_data = &dma0_platform_data, + }, +}; + +static struct platform_device dma1_device = { + .name = "sh-dma-engine", + .id = 1, + .resource = sh7780_dmae1_resources, + .num_resources = ARRAY_SIZE(sh7780_dmae1_resources), + .dev = { + .platform_data = &dma1_platform_data, }, }; @@ -269,7 +369,8 @@ static struct platform_device *sh7780_devices[] __initdata = { &tmu4_device, &tmu5_device, &rtc_device, - &dma_device, + &dma0_device, + &dma1_device, }; static int __init sh7780_devices_setup(void) diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index 23448d8c6711..fbb5d1f51f1a 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c @@ -295,15 +295,115 @@ static struct platform_device tmu5_device = { .num_resources = ARRAY_SIZE(tmu5_resources), }; -static struct sh_dmae_pdata dma_platform_data = { - .mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1), +/* DMA */ +static struct sh_dmae_channel sh7785_dmae0_channels[] = { + { + .offset = 0, + .dmars = 0, + .dmars_bit = 0, + }, { + .offset = 0x10, + .dmars = 0, + .dmars_bit = 8, + }, { + .offset = 0x20, + .dmars = 4, + .dmars_bit = 0, + }, { + .offset = 0x30, + .dmars = 4, + .dmars_bit = 8, + }, { + .offset = 0x50, + .dmars = 8, + .dmars_bit = 0, + }, { + .offset = 0x60, + .dmars = 8, + .dmars_bit = 8, + } +}; + +static struct sh_dmae_channel sh7785_dmae1_channels[] = { + { + .offset = 0, + }, { + .offset = 0x10, + }, { + .offset = 0x20, + }, { + .offset = 0x30, + }, { + .offset = 0x50, + }, { + .offset = 0x60, + } +}; + +static struct sh_dmae_pdata dma0_platform_data = { + .channel = sh7785_dmae0_channels, + .channel_num = ARRAY_SIZE(sh7785_dmae0_channels), +}; + +static struct sh_dmae_pdata dma1_platform_data = { + .channel = sh7785_dmae1_channels, + .channel_num = ARRAY_SIZE(sh7785_dmae1_channels), +}; + +static struct resource sh7785_dmae0_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xfc808020, + .end = 0xfc80808f, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* DMARSx */ + .start = 0xfc809000, + .end = 0xfc80900b, + .flags = IORESOURCE_MEM, + }, + { + /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */ + .start = 33, + .end = 33, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, +}; + +static struct resource sh7785_dmae1_resources[] = { + [0] = { + /* Channel registers and DMAOR */ + .start = 0xfcc08020, + .end = 0xfcc0808f, + .flags = IORESOURCE_MEM, + }, + /* DMAC1 has no DMARS */ + { + /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */ + .start = 52, + .end = 52, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, + }, }; -static struct platform_device dma_device = { +static struct platform_device dma0_device = { .name = "sh-dma-engine", - .id = -1, + .id = 0, + .resource = sh7785_dmae0_resources, + .num_resources = ARRAY_SIZE(sh7785_dmae0_resources), .dev = { - .platform_data = &dma_platform_data, + .platform_data = &dma0_platform_data, + }, +}; + +static struct platform_device dma1_device = { + .name = "sh-dma-engine", + .id = 1, + .resource = sh7785_dmae1_resources, + .num_resources = ARRAY_SIZE(sh7785_dmae1_resources), + .dev = { + .platform_data = &dma1_platform_data, }, }; @@ -320,7 +420,8 @@ static struct platform_device *sh7785_devices[] __initdata = { &tmu3_device, &tmu4_device, &tmu5_device, - &dma_device, + &dma0_device, + &dma1_device, }; static int __init sh7785_devices_setup(void) diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c index 77311698c046..ab12fa5a1296 100644 --- a/drivers/dma/shdma.c +++ b/drivers/dma/shdma.c @@ -53,15 +53,24 @@ static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)]; static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all); -#define SH_DMAC_CHAN_BASE(id) (dma_base_addr[id]) static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) { - ctrl_outl(data, SH_DMAC_CHAN_BASE(sh_dc->id) + reg); + __raw_writel(data, sh_dc->base + reg / sizeof(u32)); } static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) { - return ctrl_inl(SH_DMAC_CHAN_BASE(sh_dc->id) + reg); + return __raw_readl(sh_dc->base + reg / sizeof(u32)); +} + +static u16 dmaor_read(struct sh_dmae_device *shdev) +{ + return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32)); +} + +static void dmaor_write(struct sh_dmae_device *shdev, u16 data) +{ + __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32)); } /* @@ -69,23 +78,22 @@ static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) * * SH7780 has two DMAOR register */ -static void sh_dmae_ctl_stop(int id) +static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev) { - unsigned short dmaor = dmaor_read_reg(id); + unsigned short dmaor = dmaor_read(shdev); - dmaor &= ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME); - dmaor_write_reg(id, dmaor); + dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME)); } -static int sh_dmae_rst(int id) +static int sh_dmae_rst(struct sh_dmae_device *shdev) { unsigned short dmaor; - sh_dmae_ctl_stop(id); - dmaor = dmaor_read_reg(id) | DMAOR_INIT; + sh_dmae_ctl_stop(shdev); + dmaor = dmaor_read(shdev) | DMAOR_INIT; - dmaor_write_reg(id, dmaor); - if (dmaor_read_reg(id) & (DMAOR_AE | DMAOR_NMIF)) { + dmaor_write(shdev, dmaor); + if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) { pr_warning("dma-sh: Can't initialize DMAOR.\n"); return -EINVAL; } @@ -153,31 +161,20 @@ static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) return 0; } -#define DMARS_SHIFT 8 -#define DMARS_CHAN_MSK 0x01 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) { - u32 addr; - int shift = 0; + struct sh_dmae_device *shdev = container_of(sh_chan->common.device, + struct sh_dmae_device, common); + struct sh_dmae_pdata *pdata = shdev->pdata; + struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id]; + u16 __iomem *addr = shdev->dmars + chan_pdata->dmars / sizeof(u16); + int shift = chan_pdata->dmars_bit; if (dmae_is_busy(sh_chan)) return -EBUSY; - if (sh_chan->id & DMARS_CHAN_MSK) - shift = DMARS_SHIFT; - - if (sh_chan->id < 6) - /* DMA0RS0 - DMA0RS2 */ - addr = SH_DMARS_BASE0 + (sh_chan->id / 2) * 4; -#ifdef SH_DMARS_BASE1 - else if (sh_chan->id < 12) - /* DMA1RS0 - DMA1RS2 */ - addr = SH_DMARS_BASE1 + ((sh_chan->id - 6) / 2) * 4; -#endif - else - return -EINVAL; - - ctrl_outw((val << shift) | (ctrl_inw(addr) & (0xFF00 >> shift)), addr); + __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift), + addr); return 0; } @@ -251,15 +248,15 @@ static struct sh_dmae_slave_config *sh_dmae_find_slave( struct dma_device *dma_dev = sh_chan->common.device; struct sh_dmae_device *shdev = container_of(dma_dev, struct sh_dmae_device, common); - struct sh_dmae_pdata *pdata = &shdev->pdata; + struct sh_dmae_pdata *pdata = shdev->pdata; int i; if ((unsigned)slave_id >= SHDMA_SLAVE_NUMBER) return NULL; - for (i = 0; i < pdata->config_num; i++) - if (pdata->config[i].slave_id == slave_id) - return pdata->config + i; + for (i = 0; i < pdata->slave_num; i++) + if (pdata->slave[i].slave_id == slave_id) + return pdata->slave + i; return NULL; } @@ -757,9 +754,7 @@ static irqreturn_t sh_dmae_err(int irq, void *data) int i; /* halt the dma controller */ - sh_dmae_ctl_stop(0); - if (shdev->pdata.mode & SHDMA_DMAOR1) - sh_dmae_ctl_stop(1); + sh_dmae_ctl_stop(shdev); /* We cannot detect, which channel caused the error, have to reset all */ for (i = 0; i < MAX_DMA_CHANNELS; i++) { @@ -778,9 +773,7 @@ static irqreturn_t sh_dmae_err(int irq, void *data) list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free); } } - sh_dmae_rst(0); - if (shdev->pdata.mode & SHDMA_DMAOR1) - sh_dmae_rst(1); + sh_dmae_rst(shdev); return IRQ_HANDLED; } @@ -813,19 +806,12 @@ static void dmae_do_tasklet(unsigned long data) sh_dmae_chan_ld_cleanup(sh_chan, false); } -static unsigned int get_dmae_irq(unsigned int id) -{ - unsigned int irq = 0; - if (id < ARRAY_SIZE(dmte_irq_map)) - irq = dmte_irq_map[id]; - return irq; -} - -static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id) +static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, + int irq, unsigned long flags) { int err; - unsigned int irq = get_dmae_irq(id); - unsigned long irqflags = IRQF_DISABLED; + struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id]; + struct platform_device *pdev = to_platform_device(shdev->common.dev); struct sh_dmae_chan *new_sh_chan; /* alloc channel */ @@ -838,6 +824,8 @@ static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id) new_sh_chan->dev = shdev->common.dev; new_sh_chan->id = id; + new_sh_chan->irq = irq; + new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32); /* Init DMA tasklet */ tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet, @@ -860,21 +848,15 @@ static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id) &shdev->common.channels); shdev->common.chancnt++; - if (shdev->pdata.mode & SHDMA_MIX_IRQ) { - irqflags = IRQF_SHARED; -#if defined(DMTE6_IRQ) - if (irq >= DMTE6_IRQ) - irq = DMTE6_IRQ; - else -#endif - irq = DMTE0_IRQ; - } - - snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id), - "sh-dmae%d", new_sh_chan->id); + if (pdev->id >= 0) + snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id), + "sh-dmae%d.%d", pdev->id, new_sh_chan->id); + else + snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id), + "sh-dma%d", new_sh_chan->id); /* set up channel irq */ - err = request_irq(irq, &sh_dmae_interrupt, irqflags, + err = request_irq(irq, &sh_dmae_interrupt, flags, new_sh_chan->dev_id, new_sh_chan); if (err) { dev_err(shdev->common.dev, "DMA channel %d request_irq error " @@ -898,12 +880,12 @@ static void sh_dmae_chan_remove(struct sh_dmae_device *shdev) for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) { if (shdev->chan[i]) { - struct sh_dmae_chan *shchan = shdev->chan[i]; - if (!(shdev->pdata.mode & SHDMA_MIX_IRQ)) - free_irq(dmte_irq_map[i], shchan); + struct sh_dmae_chan *sh_chan = shdev->chan[i]; + + free_irq(sh_chan->irq, sh_chan); - list_del(&shchan->common.device_node); - kfree(shchan); + list_del(&sh_chan->common.device_node); + kfree(sh_chan); shdev->chan[i] = NULL; } } @@ -912,47 +894,81 @@ static void sh_dmae_chan_remove(struct sh_dmae_device *shdev) static int __init sh_dmae_probe(struct platform_device *pdev) { - int err = 0, cnt, ecnt; - unsigned long irqflags = IRQF_DISABLED; -#if defined(CONFIG_CPU_SH4) - int eirq[] = { DMAE0_IRQ, -#if defined(DMAE1_IRQ) - DMAE1_IRQ -#endif - }; -#endif + struct sh_dmae_pdata *pdata = pdev->dev.platform_data; + unsigned long irqflags = IRQF_DISABLED, + chan_flag[MAX_DMA_CHANNELS] = {}; + int errirq, chan_irq[MAX_DMA_CHANNELS]; + int err, i, irq_cnt = 0, irqres = 0; struct sh_dmae_device *shdev; + struct resource *chan, *dmars, *errirq_res, *chanirq_res; /* get platform data */ - if (!pdev->dev.platform_data) + if (!pdata || !pdata->channel_num) return -ENODEV; + chan = platform_get_resource(pdev, IORESOURCE_MEM, 0); + /* DMARS area is optional, if absent, this controller cannot do slave DMA */ + dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1); + /* + * IRQ resources: + * 1. there always must be at least one IRQ IO-resource. On SH4 it is + * the error IRQ, in which case it is the only IRQ in this resource: + * start == end. If it is the only IRQ resource, all channels also + * use the same IRQ. + * 2. DMA channel IRQ resources can be specified one per resource or in + * ranges (start != end) + * 3. iff all events (channels and, optionally, error) on this + * controller use the same IRQ, only one IRQ resource can be + * specified, otherwise there must be one IRQ per channel, even if + * some of them are equal + * 4. if all IRQs on this controller are equal or if some specific IRQs + * specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be + * requested with the IRQF_SHARED flag + */ + errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!chan || !errirq_res) + return -ENODEV; + + if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) { + dev_err(&pdev->dev, "DMAC register region already claimed\n"); + return -EBUSY; + } + + if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) { + dev_err(&pdev->dev, "DMAC DMARS region already claimed\n"); + err = -EBUSY; + goto ermrdmars; + } + + err = -ENOMEM; shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL); if (!shdev) { - dev_err(&pdev->dev, "No enough memory\n"); - return -ENOMEM; + dev_err(&pdev->dev, "Not enough memory\n"); + goto ealloc; + } + + shdev->chan_reg = ioremap(chan->start, resource_size(chan)); + if (!shdev->chan_reg) + goto emapchan; + if (dmars) { + shdev->dmars = ioremap(dmars->start, resource_size(dmars)); + if (!shdev->dmars) + goto emapdmars; } /* platform data */ - memcpy(&shdev->pdata, pdev->dev.platform_data, - sizeof(struct sh_dmae_pdata)); + shdev->pdata = pdata; /* reset dma controller */ - err = sh_dmae_rst(0); + err = sh_dmae_rst(shdev); if (err) goto rst_err; - /* SH7780/85/23 has DMAOR1 */ - if (shdev->pdata.mode & SHDMA_DMAOR1) { - err = sh_dmae_rst(1); - if (err) - goto rst_err; - } - INIT_LIST_HEAD(&shdev->common.channels); dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask); - dma_cap_set(DMA_SLAVE, shdev->common.cap_mask); + if (dmars) + dma_cap_set(DMA_SLAVE, shdev->common.cap_mask); shdev->common.device_alloc_chan_resources = sh_dmae_alloc_chan_resources; @@ -970,30 +986,63 @@ static int __init sh_dmae_probe(struct platform_device *pdev) shdev->common.copy_align = 5; #if defined(CONFIG_CPU_SH4) - /* Non Mix IRQ mode SH7722/SH7730 etc... */ - if (shdev->pdata.mode & SHDMA_MIX_IRQ) { + chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); + + if (!chanirq_res) + chanirq_res = errirq_res; + else + irqres++; + + if (chanirq_res == errirq_res || + (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE) irqflags = IRQF_SHARED; - eirq[0] = DMTE0_IRQ; -#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ) - eirq[1] = DMTE6_IRQ; -#endif + + errirq = errirq_res->start; + + err = request_irq(errirq, sh_dmae_err, irqflags, + "DMAC Address Error", shdev); + if (err) { + dev_err(&pdev->dev, + "DMA failed requesting irq #%d, error %d\n", + errirq, err); + goto eirq_err; } - for (ecnt = 0 ; ecnt < ARRAY_SIZE(eirq); ecnt++) { - err = request_irq(eirq[ecnt], sh_dmae_err, irqflags, - "DMAC Address Error", shdev); - if (err) { - dev_err(&pdev->dev, "DMA device request_irq" - "error (irq %d) with return %d\n", - eirq[ecnt], err); - goto eirq_err; +#else + chanirq_res = errirq_res; +#endif /* CONFIG_CPU_SH4 */ + + if (chanirq_res->start == chanirq_res->end && + !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) { + /* Special case - all multiplexed */ + for (; irq_cnt < pdata->channel_num; irq_cnt++) { + chan_irq[irq_cnt] = chanirq_res->start; + chan_flag[irq_cnt] = IRQF_SHARED; } + } else { + do { + for (i = chanirq_res->start; i <= chanirq_res->end; i++) { + if ((errirq_res->flags & IORESOURCE_BITS) == + IORESOURCE_IRQ_SHAREABLE) + chan_flag[irq_cnt] = IRQF_SHARED; + else + chan_flag[irq_cnt] = IRQF_DISABLED; + dev_dbg(&pdev->dev, + "Found IRQ %d for channel %d\n", + i, irq_cnt); + chan_irq[irq_cnt++] = i; + } + chanirq_res = platform_get_resource(pdev, + IORESOURCE_IRQ, ++irqres); + } while (irq_cnt < pdata->channel_num && chanirq_res); } -#endif /* CONFIG_CPU_SH4 */ + + if (irq_cnt < pdata->channel_num) + goto eirqres; /* Create DMA Channel */ - for (cnt = 0 ; cnt < MAX_DMA_CHANNELS ; cnt++) { - err = sh_dmae_chan_probe(shdev, cnt); + for (i = 0; i < pdata->channel_num; i++) { + err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]); if (err) goto chan_probe_err; } @@ -1005,13 +1054,23 @@ static int __init sh_dmae_probe(struct platform_device *pdev) chan_probe_err: sh_dmae_chan_remove(shdev); - +eirqres: +#if defined(CONFIG_CPU_SH4) + free_irq(errirq, shdev); eirq_err: - for (ecnt-- ; ecnt >= 0; ecnt--) - free_irq(eirq[ecnt], shdev); - +#endif rst_err: + if (dmars) + iounmap(shdev->dmars); +emapdmars: + iounmap(shdev->chan_reg); +emapchan: kfree(shdev); +ealloc: + if (dmars) + release_mem_region(dmars->start, resource_size(dmars)); +ermrdmars: + release_mem_region(chan->start, resource_size(chan)); return err; } @@ -1019,36 +1078,37 @@ rst_err: static int __exit sh_dmae_remove(struct platform_device *pdev) { struct sh_dmae_device *shdev = platform_get_drvdata(pdev); + struct resource *res; + int errirq = platform_get_irq(pdev, 0); dma_async_device_unregister(&shdev->common); - if (shdev->pdata.mode & SHDMA_MIX_IRQ) { - free_irq(DMTE0_IRQ, shdev); -#if defined(DMTE6_IRQ) - free_irq(DMTE6_IRQ, shdev); -#endif - } + if (errirq > 0) + free_irq(errirq, shdev); /* channel data remove */ sh_dmae_chan_remove(shdev); - if (!(shdev->pdata.mode & SHDMA_MIX_IRQ)) { - free_irq(DMAE0_IRQ, shdev); -#if defined(DMAE1_IRQ) - free_irq(DMAE1_IRQ, shdev); -#endif - } + if (shdev->dmars) + iounmap(shdev->dmars); + iounmap(shdev->chan_reg); + kfree(shdev); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res) + release_mem_region(res->start, resource_size(res)); + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) + release_mem_region(res->start, resource_size(res)); + return 0; } static void sh_dmae_shutdown(struct platform_device *pdev) { struct sh_dmae_device *shdev = platform_get_drvdata(pdev); - sh_dmae_ctl_stop(0); - if (shdev->pdata.mode & SHDMA_DMAOR1) - sh_dmae_ctl_stop(1); + sh_dmae_ctl_stop(shdev); } static struct platform_driver sh_dmae_driver = { diff --git a/drivers/dma/shdma.h b/drivers/dma/shdma.h index 7e227f3c87c4..800fd884be83 100644 --- a/drivers/dma/shdma.h +++ b/drivers/dma/shdma.h @@ -47,14 +47,18 @@ struct sh_dmae_chan { struct tasklet_struct tasklet; /* Tasklet */ int descs_allocated; /* desc count */ int xmit_shift; /* log_2(bytes_per_xfer) */ + int irq; int id; /* Raw id of this channel */ + u32 __iomem *base; char dev_id[16]; /* unique name per DMAC of channel */ }; struct sh_dmae_device { struct dma_device common; struct sh_dmae_chan *chan[MAX_DMA_CHANNELS]; - struct sh_dmae_pdata pdata; + struct sh_dmae_pdata *pdata; + u32 __iomem *chan_reg; + u16 __iomem *dmars; }; #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common) -- cgit v1.2.3 From 8b1935e6a36b0967efc593d67ed3aebbfbc1f5b1 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 11 Feb 2010 16:50:14 +0000 Subject: dmaengine: shdma: separate DMA headers. Separate SH DMA headers into ones, commonly used by both drivers, and ones, specific to each of them. This will make the future development of the dmaengine driver easier. Signed-off-by: Guennadi Liakhovetski Acked-by: Mark Brown Signed-off-by: Paul Mundt --- arch/sh/include/asm/dma-register.h | 51 +++++++++++++ arch/sh/include/asm/dma-sh.h | 95 +---------------------- arch/sh/include/asm/dmaengine.h | 73 ++++++++++++++++++ arch/sh/include/asm/siu.h | 2 +- arch/sh/include/cpu-sh3/cpu/dma-register.h | 41 ++++++++++ arch/sh/include/cpu-sh3/cpu/dma.h | 27 ------- arch/sh/include/cpu-sh4/cpu/dma-register.h | 116 +++++++++++++++++++++++++++++ arch/sh/include/cpu-sh4/cpu/dma-sh4a.h | 62 --------------- arch/sh/include/cpu-sh4/cpu/dma.h | 36 +-------- arch/sh/kernel/cpu/sh4a/setup-sh7722.c | 20 ++++- arch/sh/kernel/cpu/sh4a/setup-sh7724.c | 21 +++++- arch/sh/kernel/cpu/sh4a/setup-sh7780.c | 21 +++++- arch/sh/kernel/cpu/sh4a/setup-sh7785.c | 21 +++++- drivers/dma/shdma.c | 79 ++++++++++++-------- drivers/dma/shdma.h | 4 +- sound/soc/sh/siu.h | 2 +- sound/soc/sh/siu_pcm.c | 2 +- 17 files changed, 415 insertions(+), 258 deletions(-) create mode 100644 arch/sh/include/asm/dma-register.h create mode 100644 arch/sh/include/asm/dmaengine.h create mode 100644 arch/sh/include/cpu-sh3/cpu/dma-register.h create mode 100644 arch/sh/include/cpu-sh4/cpu/dma-register.h (limited to 'drivers') diff --git a/arch/sh/include/asm/dma-register.h b/arch/sh/include/asm/dma-register.h new file mode 100644 index 000000000000..51cd78feacff --- /dev/null +++ b/arch/sh/include/asm/dma-register.h @@ -0,0 +1,51 @@ +/* + * Common header for the legacy SH DMA driver and the new dmaengine driver + * + * extracted from arch/sh/include/asm/dma-sh.h: + * + * Copyright (C) 2000 Takashi YOSHII + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef DMA_REGISTER_H +#define DMA_REGISTER_H + +/* DMA register */ +#define SAR 0x00 +#define DAR 0x04 +#define TCR 0x08 +#define CHCR 0x0C +#define DMAOR 0x40 + +/* DMAOR definitions */ +#define DMAOR_AE 0x00000004 +#define DMAOR_NMIF 0x00000002 +#define DMAOR_DME 0x00000001 + +/* Definitions for the SuperH DMAC */ +#define REQ_L 0x00000000 +#define REQ_E 0x00080000 +#define RACK_H 0x00000000 +#define RACK_L 0x00040000 +#define ACK_R 0x00000000 +#define ACK_W 0x00020000 +#define ACK_H 0x00000000 +#define ACK_L 0x00010000 +#define DM_INC 0x00004000 +#define DM_DEC 0x00008000 +#define DM_FIX 0x0000c000 +#define SM_INC 0x00001000 +#define SM_DEC 0x00002000 +#define SM_FIX 0x00003000 +#define RS_IN 0x00000200 +#define RS_OUT 0x00000300 +#define TS_BLK 0x00000040 +#define TM_BUR 0x00000020 +#define CHCR_DE 0x00000001 +#define CHCR_TE 0x00000002 +#define CHCR_IE 0x00000004 + +#endif diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h index 2e3631d6e273..f3acb8e34c6b 100644 --- a/arch/sh/include/asm/dma-sh.h +++ b/arch/sh/include/asm/dma-sh.h @@ -11,7 +11,8 @@ #ifndef __DMA_SH_H #define __DMA_SH_H -#include +#include +#include #include /* DMAOR contorl: The DMAOR access size is different by CPU.*/ @@ -53,34 +54,6 @@ static int dmte_irq_map[] __maybe_unused = { #endif }; -/* Definitions for the SuperH DMAC */ -#define REQ_L 0x00000000 -#define REQ_E 0x00080000 -#define RACK_H 0x00000000 -#define RACK_L 0x00040000 -#define ACK_R 0x00000000 -#define ACK_W 0x00020000 -#define ACK_H 0x00000000 -#define ACK_L 0x00010000 -#define DM_INC 0x00004000 -#define DM_DEC 0x00008000 -#define DM_FIX 0x0000c000 -#define SM_INC 0x00001000 -#define SM_DEC 0x00002000 -#define SM_FIX 0x00003000 -#define RS_IN 0x00000200 -#define RS_OUT 0x00000300 -#define TS_BLK 0x00000040 -#define TM_BUR 0x00000020 -#define CHCR_DE 0x00000001 -#define CHCR_TE 0x00000002 -#define CHCR_IE 0x00000004 - -/* DMAOR definitions */ -#define DMAOR_AE 0x00000004 -#define DMAOR_NMIF 0x00000002 -#define DMAOR_DME 0x00000001 - /* * Define the default configuration for dual address memory-memory transfer. * The 0x400 value represents auto-request, external->external. @@ -111,68 +84,4 @@ static u32 dma_base_addr[] __maybe_unused = { #endif }; -/* DMA register */ -#define SAR 0x00 -#define DAR 0x04 -#define TCR 0x08 -#define CHCR 0x0C -#define DMAOR 0x40 - -/* - * for dma engine - * - * SuperH DMA mode - */ -#define SHDMA_MIX_IRQ (1 << 1) -#define SHDMA_DMAOR1 (1 << 2) -#define SHDMA_DMAE1 (1 << 3) - -enum sh_dmae_slave_chan_id { - SHDMA_SLAVE_SCIF0_TX, - SHDMA_SLAVE_SCIF0_RX, - SHDMA_SLAVE_SCIF1_TX, - SHDMA_SLAVE_SCIF1_RX, - SHDMA_SLAVE_SCIF2_TX, - SHDMA_SLAVE_SCIF2_RX, - SHDMA_SLAVE_SCIF3_TX, - SHDMA_SLAVE_SCIF3_RX, - SHDMA_SLAVE_SCIF4_TX, - SHDMA_SLAVE_SCIF4_RX, - SHDMA_SLAVE_SCIF5_TX, - SHDMA_SLAVE_SCIF5_RX, - SHDMA_SLAVE_SIUA_TX, - SHDMA_SLAVE_SIUA_RX, - SHDMA_SLAVE_SIUB_TX, - SHDMA_SLAVE_SIUB_RX, - SHDMA_SLAVE_NUMBER, /* Must stay last */ -}; - -struct sh_dmae_slave_config { - enum sh_dmae_slave_chan_id slave_id; - dma_addr_t addr; - u32 chcr; - char mid_rid; -}; - -struct sh_dmae_channel { - unsigned int offset; - unsigned int dmars; - unsigned int dmars_bit; -}; - -struct sh_dmae_pdata { - struct sh_dmae_slave_config *slave; - int slave_num; - struct sh_dmae_channel *channel; - int channel_num; -}; - -struct device; - -struct sh_dmae_slave { - enum sh_dmae_slave_chan_id slave_id; /* Set by the platform */ - struct device *dma_dev; /* Set by the platform */ - struct sh_dmae_slave_config *config; /* Set by the driver */ -}; - #endif /* __DMA_SH_H */ diff --git a/arch/sh/include/asm/dmaengine.h b/arch/sh/include/asm/dmaengine.h new file mode 100644 index 000000000000..9586e4a482b1 --- /dev/null +++ b/arch/sh/include/asm/dmaengine.h @@ -0,0 +1,73 @@ +/* + * Header for the new SH dmaengine driver + * + * Copyright (C) 2010 Guennadi Liakhovetski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef ASM_DMAENGINE_H +#define ASM_DMAENGINE_H + +#include + +#define SH_DMAC_MAX_CHANNELS 6 + +enum sh_dmae_slave_chan_id { + SHDMA_SLAVE_SCIF0_TX, + SHDMA_SLAVE_SCIF0_RX, + SHDMA_SLAVE_SCIF1_TX, + SHDMA_SLAVE_SCIF1_RX, + SHDMA_SLAVE_SCIF2_TX, + SHDMA_SLAVE_SCIF2_RX, + SHDMA_SLAVE_SCIF3_TX, + SHDMA_SLAVE_SCIF3_RX, + SHDMA_SLAVE_SCIF4_TX, + SHDMA_SLAVE_SCIF4_RX, + SHDMA_SLAVE_SCIF5_TX, + SHDMA_SLAVE_SCIF5_RX, + SHDMA_SLAVE_SIUA_TX, + SHDMA_SLAVE_SIUA_RX, + SHDMA_SLAVE_SIUB_TX, + SHDMA_SLAVE_SIUB_RX, + SHDMA_SLAVE_NUMBER, /* Must stay last */ +}; + +struct sh_dmae_slave_config { + enum sh_dmae_slave_chan_id slave_id; + dma_addr_t addr; + u32 chcr; + char mid_rid; +}; + +struct sh_dmae_channel { + unsigned int offset; + unsigned int dmars; + unsigned int dmars_bit; +}; + +struct sh_dmae_pdata { + struct sh_dmae_slave_config *slave; + int slave_num; + struct sh_dmae_channel *channel; + int channel_num; + unsigned int ts_low_shift; + unsigned int ts_low_mask; + unsigned int ts_high_shift; + unsigned int ts_high_mask; + unsigned int *ts_shift; + int ts_shift_num; + u16 dmaor_init; +}; + +struct device; + +/* Used by slave DMA clients to request DMA to/from a specific peripheral */ +struct sh_dmae_slave { + enum sh_dmae_slave_chan_id slave_id; /* Set by the platform */ + struct device *dma_dev; /* Set by the platform */ + struct sh_dmae_slave_config *config; /* Set by the driver */ +}; + +#endif diff --git a/arch/sh/include/asm/siu.h b/arch/sh/include/asm/siu.h index 57565a3b551f..f1b1e6944a5f 100644 --- a/arch/sh/include/asm/siu.h +++ b/arch/sh/include/asm/siu.h @@ -11,7 +11,7 @@ #ifndef ASM_SIU_H #define ASM_SIU_H -#include +#include struct device; diff --git a/arch/sh/include/cpu-sh3/cpu/dma-register.h b/arch/sh/include/cpu-sh3/cpu/dma-register.h new file mode 100644 index 000000000000..2349e488c9a6 --- /dev/null +++ b/arch/sh/include/cpu-sh3/cpu/dma-register.h @@ -0,0 +1,41 @@ +/* + * SH3 CPU-specific DMA definitions, used by both DMA drivers + * + * Copyright (C) 2010 Guennadi Liakhovetski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef CPU_DMA_REGISTER_H +#define CPU_DMA_REGISTER_H + +#define CHCR_TS_LOW_MASK 0x18 +#define CHCR_TS_LOW_SHIFT 3 +#define CHCR_TS_HIGH_MASK 0 +#define CHCR_TS_HIGH_SHIFT 0 + +#define DMAOR_INIT DMAOR_DME + +/* + * The SuperH DMAC supports a number of transmit sizes, we list them here, + * with their respective values as they appear in the CHCR registers. + */ +enum { + XMIT_SZ_8BIT, + XMIT_SZ_16BIT, + XMIT_SZ_32BIT, + XMIT_SZ_128BIT, +}; + +/* log2(size / 8) - used to calculate number of transfers */ +#define TS_SHIFT { \ + [XMIT_SZ_8BIT] = 0, \ + [XMIT_SZ_16BIT] = 1, \ + [XMIT_SZ_32BIT] = 2, \ + [XMIT_SZ_128BIT] = 4, \ +} + +#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT) + +#endif diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h index 207811a7a650..24e28b91c9d5 100644 --- a/arch/sh/include/cpu-sh3/cpu/dma.h +++ b/arch/sh/include/cpu-sh3/cpu/dma.h @@ -20,31 +20,4 @@ #define TS_32 0x00000010 #define TS_128 0x00000018 -#define CHCR_TS_LOW_MASK 0x18 -#define CHCR_TS_LOW_SHIFT 3 -#define CHCR_TS_HIGH_MASK 0 -#define CHCR_TS_HIGH_SHIFT 0 - -#define DMAOR_INIT DMAOR_DME - -/* - * The SuperH DMAC supports a number of transmit sizes, we list them here, - * with their respective values as they appear in the CHCR registers. - */ -enum { - XMIT_SZ_8BIT, - XMIT_SZ_16BIT, - XMIT_SZ_32BIT, - XMIT_SZ_128BIT, -}; - -#define TS_SHIFT { \ - [XMIT_SZ_8BIT] = 0, \ - [XMIT_SZ_16BIT] = 1, \ - [XMIT_SZ_32BIT] = 2, \ - [XMIT_SZ_128BIT] = 4, \ -} - -#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT) - #endif /* __ASM_CPU_SH3_DMA_H */ diff --git a/arch/sh/include/cpu-sh4/cpu/dma-register.h b/arch/sh/include/cpu-sh4/cpu/dma-register.h new file mode 100644 index 000000000000..008e7fc8f6c0 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/dma-register.h @@ -0,0 +1,116 @@ +/* + * SH4 CPU-specific DMA definitions, used by both DMA drivers + * + * Copyright (C) 2010 Guennadi Liakhovetski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef CPU_DMA_REGISTER_H +#define CPU_DMA_REGISTER_H + +/* SH7751/7760/7780 DMA IRQ sources */ + +#ifdef CONFIG_CPU_SH4A + +#define DMAOR_INIT DMAOR_DME + +#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \ + defined(CONFIG_CPU_SUBTYPE_SH7730) +#define CHCR_TS_LOW_MASK 0x00000018 +#define CHCR_TS_LOW_SHIFT 3 +#define CHCR_TS_HIGH_MASK 0 +#define CHCR_TS_HIGH_SHIFT 0 +#elif defined(CONFIG_CPU_SUBTYPE_SH7722) +#define CHCR_TS_LOW_MASK 0x00000018 +#define CHCR_TS_LOW_SHIFT 3 +#define CHCR_TS_HIGH_MASK 0x00300000 +#define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ +#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ + defined(CONFIG_CPU_SUBTYPE_SH7764) +#define CHCR_TS_LOW_MASK 0x00000018 +#define CHCR_TS_LOW_SHIFT 3 +#define CHCR_TS_HIGH_MASK 0 +#define CHCR_TS_HIGH_SHIFT 0 +#elif defined(CONFIG_CPU_SUBTYPE_SH7723) +#define CHCR_TS_LOW_MASK 0x00000018 +#define CHCR_TS_LOW_SHIFT 3 +#define CHCR_TS_HIGH_MASK 0 +#define CHCR_TS_HIGH_SHIFT 0 +#elif defined(CONFIG_CPU_SUBTYPE_SH7724) +#define CHCR_TS_LOW_MASK 0x00000018 +#define CHCR_TS_LOW_SHIFT 3 +#define CHCR_TS_HIGH_MASK 0x00600000 +#define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ +#elif defined(CONFIG_CPU_SUBTYPE_SH7780) +#define CHCR_TS_LOW_MASK 0x00000018 +#define CHCR_TS_LOW_SHIFT 3 +#define CHCR_TS_HIGH_MASK 0 +#define CHCR_TS_HIGH_SHIFT 0 +#else /* SH7785 */ +#define CHCR_TS_LOW_MASK 0x00000018 +#define CHCR_TS_LOW_SHIFT 3 +#define CHCR_TS_HIGH_MASK 0 +#define CHCR_TS_HIGH_SHIFT 0 +#endif + +/* Transmit sizes and respective CHCR register values */ +enum { + XMIT_SZ_8BIT = 0, + XMIT_SZ_16BIT = 1, + XMIT_SZ_32BIT = 2, + XMIT_SZ_64BIT = 7, + XMIT_SZ_128BIT = 3, + XMIT_SZ_256BIT = 4, + XMIT_SZ_128BIT_BLK = 0xb, + XMIT_SZ_256BIT_BLK = 0xc, +}; + +/* log2(size / 8) - used to calculate number of transfers */ +#define TS_SHIFT { \ + [XMIT_SZ_8BIT] = 0, \ + [XMIT_SZ_16BIT] = 1, \ + [XMIT_SZ_32BIT] = 2, \ + [XMIT_SZ_64BIT] = 3, \ + [XMIT_SZ_128BIT] = 4, \ + [XMIT_SZ_256BIT] = 5, \ + [XMIT_SZ_128BIT_BLK] = 4, \ + [XMIT_SZ_256BIT_BLK] = 5, \ +} + +#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \ + ((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT)) + +#else /* CONFIG_CPU_SH4A */ + +#define DMAOR_INIT (0x8000 | DMAOR_DME) + +#define CHCR_TS_LOW_MASK 0x70 +#define CHCR_TS_LOW_SHIFT 4 +#define CHCR_TS_HIGH_MASK 0 +#define CHCR_TS_HIGH_SHIFT 0 + +/* Transmit sizes and respective CHCR register values */ +enum { + XMIT_SZ_8BIT = 1, + XMIT_SZ_16BIT = 2, + XMIT_SZ_32BIT = 3, + XMIT_SZ_64BIT = 0, + XMIT_SZ_256BIT = 4, +}; + +/* log2(size / 8) - used to calculate number of transfers */ +#define TS_SHIFT { \ + [XMIT_SZ_8BIT] = 0, \ + [XMIT_SZ_16BIT] = 1, \ + [XMIT_SZ_32BIT] = 2, \ + [XMIT_SZ_64BIT] = 3, \ + [XMIT_SZ_256BIT] = 5, \ +} + +#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT) + +#endif /* CONFIG_CPU_SH4A */ + +#endif diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h index e734ea47d8a0..9647e681fd27 100644 --- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h +++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h @@ -8,20 +8,12 @@ #define DMAE0_IRQ 78 /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 #define SH_DMARS_BASE0 0xFE009000 -#define CHCR_TS_LOW_MASK 0x00000018 -#define CHCR_TS_LOW_SHIFT 3 -#define CHCR_TS_HIGH_MASK 0 -#define CHCR_TS_HIGH_SHIFT 0 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) #define DMTE0_IRQ 48 #define DMTE4_IRQ 76 #define DMAE0_IRQ 78 /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 #define SH_DMARS_BASE0 0xFE009000 -#define CHCR_TS_LOW_MASK 0x00000018 -#define CHCR_TS_LOW_SHIFT 3 -#define CHCR_TS_HIGH_MASK 0x00300000 -#define CHCR_TS_HIGH_SHIFT 20 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ defined(CONFIG_CPU_SUBTYPE_SH7764) #define DMTE0_IRQ 34 @@ -29,10 +21,6 @@ #define DMAE0_IRQ 38 #define SH_DMAC_BASE0 0xFF608020 #define SH_DMARS_BASE0 0xFF609000 -#define CHCR_TS_LOW_MASK 0x00000018 -#define CHCR_TS_LOW_SHIFT 3 -#define CHCR_TS_HIGH_MASK 0 -#define CHCR_TS_HIGH_SHIFT 0 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) #define DMTE0_IRQ 48 /* DMAC0A*/ #define DMTE4_IRQ 76 /* DMAC0B */ @@ -46,10 +34,6 @@ #define SH_DMAC_BASE0 0xFE008020 #define SH_DMAC_BASE1 0xFDC08020 #define SH_DMARS_BASE0 0xFDC09000 -#define CHCR_TS_LOW_MASK 0x00000018 -#define CHCR_TS_LOW_SHIFT 3 -#define CHCR_TS_HIGH_MASK 0 -#define CHCR_TS_HIGH_SHIFT 0 #elif defined(CONFIG_CPU_SUBTYPE_SH7724) #define DMTE0_IRQ 48 /* DMAC0A*/ #define DMTE4_IRQ 76 /* DMAC0B */ @@ -64,10 +48,6 @@ #define SH_DMAC_BASE1 0xFDC08020 #define SH_DMARS_BASE0 0xFE009000 #define SH_DMARS_BASE1 0xFDC09000 -#define CHCR_TS_LOW_MASK 0x00000018 -#define CHCR_TS_LOW_SHIFT 3 -#define CHCR_TS_HIGH_MASK 0x00600000 -#define CHCR_TS_HIGH_SHIFT 21 #elif defined(CONFIG_CPU_SUBTYPE_SH7780) #define DMTE0_IRQ 34 #define DMTE4_IRQ 44 @@ -80,10 +60,6 @@ #define SH_DMAC_BASE0 0xFC808020 #define SH_DMAC_BASE1 0xFC818020 #define SH_DMARS_BASE0 0xFC809000 -#define CHCR_TS_LOW_MASK 0x00000018 -#define CHCR_TS_LOW_SHIFT 3 -#define CHCR_TS_HIGH_MASK 0 -#define CHCR_TS_HIGH_SHIFT 0 #else /* SH7785 */ #define DMTE0_IRQ 33 #define DMTE4_IRQ 37 @@ -97,10 +73,6 @@ #define SH_DMAC_BASE0 0xFC808020 #define SH_DMAC_BASE1 0xFCC08020 #define SH_DMARS_BASE0 0xFC809000 -#define CHCR_TS_LOW_MASK 0x00000018 -#define CHCR_TS_LOW_SHIFT 3 -#define CHCR_TS_HIGH_MASK 0 -#define CHCR_TS_HIGH_SHIFT 0 #endif #define REQ_HE 0x000000C0 @@ -108,38 +80,4 @@ #define REQ_LE 0x00000040 #define TM_BURST 0x00000020 -/* - * The SuperH DMAC supports a number of transmit sizes, we list them here, - * with their respective values as they appear in the CHCR registers. - * - * Defaults to a 64-bit transfer size. - */ -enum { - XMIT_SZ_8BIT = 0, - XMIT_SZ_16BIT = 1, - XMIT_SZ_32BIT = 2, - XMIT_SZ_64BIT = 7, - XMIT_SZ_128BIT = 3, - XMIT_SZ_256BIT = 4, - XMIT_SZ_128BIT_BLK = 0xb, - XMIT_SZ_256BIT_BLK = 0xc, -}; - -/* - * The DMA count is defined as the number of bytes to transfer. - */ -#define TS_SHIFT { \ - [XMIT_SZ_8BIT] = 0, \ - [XMIT_SZ_16BIT] = 1, \ - [XMIT_SZ_32BIT] = 2, \ - [XMIT_SZ_64BIT] = 3, \ - [XMIT_SZ_128BIT] = 4, \ - [XMIT_SZ_256BIT] = 5, \ - [XMIT_SZ_128BIT_BLK] = 4, \ - [XMIT_SZ_256BIT_BLK] = 5, \ -} - -#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \ - ((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT)) - #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */ diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h index 114a369705bc..ca747e93c2ed 100644 --- a/arch/sh/include/cpu-sh4/cpu/dma.h +++ b/arch/sh/include/cpu-sh4/cpu/dma.h @@ -5,9 +5,8 @@ #ifdef CONFIG_CPU_SH4A -#define DMAOR_INIT (DMAOR_DME) - #include + #else /* CONFIG_CPU_SH4A */ /* * SH7750/SH7751/SH7760 @@ -17,7 +16,6 @@ #define DMTE6_IRQ 46 #define DMAE0_IRQ 38 -#define DMAOR_INIT (0x8000|DMAOR_DME) #define SH_DMAC_BASE0 0xffa00000 #define SH_DMAC_BASE1 0xffa00070 /* Definitions for the SuperH DMAC */ @@ -27,40 +25,8 @@ #define TS_32 0x00000030 #define TS_64 0x00000000 -#define CHCR_TS_LOW_MASK 0x70 -#define CHCR_TS_LOW_SHIFT 4 -#define CHCR_TS_HIGH_MASK 0 -#define CHCR_TS_HIGH_SHIFT 0 - #define DMAOR_COD 0x00000008 -/* - * The SuperH DMAC supports a number of transmit sizes, we list them here, - * with their respective values as they appear in the CHCR registers. - * - * Defaults to a 64-bit transfer size. - */ -enum { - XMIT_SZ_8BIT = 1, - XMIT_SZ_16BIT = 2, - XMIT_SZ_32BIT = 3, - XMIT_SZ_64BIT = 0, - XMIT_SZ_256BIT = 4, -}; - -/* - * The DMA count is defined as the number of bytes to transfer. - */ -#define TS_SHIFT { \ - [XMIT_SZ_8BIT] = 0, \ - [XMIT_SZ_16BIT] = 1, \ - [XMIT_SZ_32BIT] = 2, \ - [XMIT_SZ_64BIT] = 3, \ - [XMIT_SZ_256BIT] = 5, \ -} - -#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT) - #endif #endif /* __ASM_CPU_SH4_DMA_H */ diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index aec182bed8a1..89f84911c356 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c @@ -7,18 +7,21 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. */ -#include #include +#include +#include #include #include -#include +#include #include #include -#include + #include +#include #include -#include #include + +#include #include static struct sh_dmae_slave_config sh7722_dmae_slaves[] = { @@ -103,11 +106,20 @@ static struct sh_dmae_channel sh7722_dmae_channels[] = { } }; +static unsigned int ts_shift[] = TS_SHIFT; + static struct sh_dmae_pdata dma_platform_data = { .slave = sh7722_dmae_slaves, .slave_num = ARRAY_SIZE(sh7722_dmae_slaves), .channel = sh7722_dmae_channels, .channel_num = ARRAY_SIZE(sh7722_dmae_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, }; static struct resource sh7722_dmae_resources[] = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index aca1fb2c571b..d9cb2c471a31 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c @@ -21,10 +21,13 @@ #include #include #include + #include #include -#include +#include #include + +#include #include /* DMA */ @@ -84,14 +87,30 @@ static struct sh_dmae_channel sh7724_dmae1_channels[] = { } }; +static unsigned int ts_shift[] = TS_SHIFT; + static struct sh_dmae_pdata dma0_platform_data = { .channel = sh7724_dmae0_channels, .channel_num = ARRAY_SIZE(sh7724_dmae0_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, }; static struct sh_dmae_pdata dma1_platform_data = { .channel = sh7724_dmae1_channels, .channel_num = ARRAY_SIZE(sh7724_dmae1_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, }; /* Resource order important! */ diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c index 338dfc2c2bb5..02e792c90de6 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c @@ -13,7 +13,10 @@ #include #include #include -#include + +#include + +#include static struct plat_sci_port scif0_platform_data = { .mapbase = 0xffe00000, @@ -292,14 +295,30 @@ static struct sh_dmae_channel sh7780_dmae1_channels[] = { } }; +static unsigned int ts_shift[] = TS_SHIFT; + static struct sh_dmae_pdata dma0_platform_data = { .channel = sh7780_dmae0_channels, .channel_num = ARRAY_SIZE(sh7780_dmae0_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, }; static struct sh_dmae_pdata dma1_platform_data = { .channel = sh7780_dmae1_channels, .channel_num = ARRAY_SIZE(sh7780_dmae1_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, }; static struct resource sh7780_dmae0_resources[] = { diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index fbb5d1f51f1a..1fcd88b1671e 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c @@ -14,9 +14,12 @@ #include #include #include -#include + +#include #include +#include + static struct plat_sci_port scif0_platform_data = { .mapbase = 0xffea0000, .flags = UPF_BOOT_AUTOCONF, @@ -340,14 +343,30 @@ static struct sh_dmae_channel sh7785_dmae1_channels[] = { } }; +static unsigned int ts_shift[] = TS_SHIFT; + static struct sh_dmae_pdata dma0_platform_data = { .channel = sh7785_dmae0_channels, .channel_num = ARRAY_SIZE(sh7785_dmae0_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, }; static struct sh_dmae_pdata dma1_platform_data = { .channel = sh7785_dmae1_channels, .channel_num = ARRAY_SIZE(sh7785_dmae1_channels), + .ts_low_shift = CHCR_TS_LOW_SHIFT, + .ts_low_mask = CHCR_TS_LOW_MASK, + .ts_high_shift = CHCR_TS_HIGH_SHIFT, + .ts_high_mask = CHCR_TS_HIGH_MASK, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_INIT, }; static struct resource sh7785_dmae0_resources[] = { diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c index ab12fa5a1296..b419afaa2389 100644 --- a/drivers/dma/shdma.c +++ b/drivers/dma/shdma.c @@ -24,8 +24,7 @@ #include #include #include -#include -#include +#include #include "shdma.h" /* DMA descriptor control */ @@ -38,15 +37,8 @@ enum sh_dmae_desc_status { }; #define NR_DESCS_PER_CHANNEL 32 -/* - * Define the default configuration for dual address memory-memory transfer. - * The 0x400 value represents auto-request, external->external. - * - * And this driver set 4byte burst mode. - * If you want to change mode, you need to change RS_DEFAULT of value. - * (ex 1byte burst mode -> (RS_DUAL & ~TS_32) - */ -#define RS_DEFAULT (RS_DUAL) +/* Default MEMCPY transfer size = 2^2 = 4 bytes */ +#define LOG2_DEFAULT_XFER_SIZE 2 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */ static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)]; @@ -90,7 +82,7 @@ static int sh_dmae_rst(struct sh_dmae_device *shdev) unsigned short dmaor; sh_dmae_ctl_stop(shdev); - dmaor = dmaor_read(shdev) | DMAOR_INIT; + dmaor = dmaor_read(shdev) | shdev->pdata->dmaor_init; dmaor_write(shdev, dmaor); if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) { @@ -110,13 +102,36 @@ static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) return false; /* waiting */ } -static unsigned int ts_shift[] = TS_SHIFT; -static inline unsigned int calc_xmit_shift(u32 chcr) +static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr) { - int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) | - ((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT); + struct sh_dmae_device *shdev = container_of(sh_chan->common.device, + struct sh_dmae_device, common); + struct sh_dmae_pdata *pdata = shdev->pdata; + int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) | + ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift); + + if (cnt >= pdata->ts_shift_num) + cnt = 0; - return ts_shift[cnt]; + return pdata->ts_shift[cnt]; +} + +static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size) +{ + struct sh_dmae_device *shdev = container_of(sh_chan->common.device, + struct sh_dmae_device, common); + struct sh_dmae_pdata *pdata = shdev->pdata; + int i; + + for (i = 0; i < pdata->ts_shift_num; i++) + if (pdata->ts_shift[i] == l2size) + break; + + if (i == pdata->ts_shift_num) + i = 0; + + return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) | + ((i << pdata->ts_high_shift) & pdata->ts_high_mask); } static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) @@ -144,8 +159,13 @@ static void dmae_halt(struct sh_dmae_chan *sh_chan) static void dmae_init(struct sh_dmae_chan *sh_chan) { - u32 chcr = RS_DEFAULT; /* default is DUAL mode */ - sh_chan->xmit_shift = calc_xmit_shift(chcr); + /* + * Default configuration for dual address memory-memory transfer. + * 0x400 represents auto-request. + */ + u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan, + LOG2_DEFAULT_XFER_SIZE); + sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr); sh_dmae_writel(sh_chan, chcr, CHCR); } @@ -155,7 +175,7 @@ static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) if (dmae_is_busy(sh_chan)) return -EBUSY; - sh_chan->xmit_shift = calc_xmit_shift(val); + sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val); sh_dmae_writel(sh_chan, val, CHCR); return 0; @@ -285,9 +305,8 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan) dmae_set_dmars(sh_chan, cfg->mid_rid); dmae_set_chcr(sh_chan, cfg->chcr); - } else { - if ((sh_dmae_readl(sh_chan, CHCR) & 0x700) != 0x400) - dmae_set_chcr(sh_chan, RS_DEFAULT); + } else if ((sh_dmae_readl(sh_chan, CHCR) & 0xf00) != 0x400) { + dmae_init(sh_chan); } spin_lock_bh(&sh_chan->desc_lock); @@ -757,7 +776,7 @@ static irqreturn_t sh_dmae_err(int irq, void *data) sh_dmae_ctl_stop(shdev); /* We cannot detect, which channel caused the error, have to reset all */ - for (i = 0; i < MAX_DMA_CHANNELS; i++) { + for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) { struct sh_dmae_chan *sh_chan = shdev->chan[i]; if (sh_chan) { struct sh_desc *desc; @@ -822,6 +841,9 @@ static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, return -ENOMEM; } + /* copy struct dma_device */ + new_sh_chan->common.device = &shdev->common; + new_sh_chan->dev = shdev->common.dev; new_sh_chan->id = id; new_sh_chan->irq = irq; @@ -840,9 +862,6 @@ static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, INIT_LIST_HEAD(&new_sh_chan->ld_queue); INIT_LIST_HEAD(&new_sh_chan->ld_free); - /* copy struct dma_device */ - new_sh_chan->common.device = &shdev->common; - /* Add the channel to DMA device channel list */ list_add_tail(&new_sh_chan->common.device_node, &shdev->common.channels); @@ -896,8 +915,8 @@ static int __init sh_dmae_probe(struct platform_device *pdev) { struct sh_dmae_pdata *pdata = pdev->dev.platform_data; unsigned long irqflags = IRQF_DISABLED, - chan_flag[MAX_DMA_CHANNELS] = {}; - int errirq, chan_irq[MAX_DMA_CHANNELS]; + chan_flag[SH_DMAC_MAX_CHANNELS] = {}; + int errirq, chan_irq[SH_DMAC_MAX_CHANNELS]; int err, i, irq_cnt = 0, irqres = 0; struct sh_dmae_device *shdev; struct resource *chan, *dmars, *errirq_res, *chanirq_res; @@ -983,7 +1002,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev) shdev->common.dev = &pdev->dev; /* Default transfer size of 32 bytes requires 32-byte alignment */ - shdev->common.copy_align = 5; + shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE; #if defined(CONFIG_CPU_SH4) chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); diff --git a/drivers/dma/shdma.h b/drivers/dma/shdma.h index 800fd884be83..9f0897f7fe34 100644 --- a/drivers/dma/shdma.h +++ b/drivers/dma/shdma.h @@ -17,6 +17,8 @@ #include #include +#include + #define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */ struct sh_dmae_regs { @@ -55,7 +57,7 @@ struct sh_dmae_chan { struct sh_dmae_device { struct dma_device common; - struct sh_dmae_chan *chan[MAX_DMA_CHANNELS]; + struct sh_dmae_chan *chan[SH_DMAC_MAX_CHANNELS]; struct sh_dmae_pdata *pdata; u32 __iomem *chan_reg; u16 __iomem *dmars; diff --git a/sound/soc/sh/siu.h b/sound/soc/sh/siu.h index 9cc04ab2bce7..c0bfab8fed3d 100644 --- a/sound/soc/sh/siu.h +++ b/sound/soc/sh/siu.h @@ -72,7 +72,7 @@ struct siu_firmware { #include #include -#include +#include #include #include diff --git a/sound/soc/sh/siu_pcm.c b/sound/soc/sh/siu_pcm.c index c5efc30f0136..ba7f8d05d977 100644 --- a/sound/soc/sh/siu_pcm.c +++ b/sound/soc/sh/siu_pcm.c @@ -32,7 +32,7 @@ #include #include -#include +#include #include #include "siu.h" -- cgit v1.2.3 From 20f2a3b5d57701c54bdd59b89dd37fe775926bae Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 11 Feb 2010 16:50:18 +0000 Subject: dmaengine: shdma: add runtime PM support. Provided platforms implement runtime PM, this disables the controller, when not in use. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt --- drivers/dma/shdma.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers') diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c index b419afaa2389..ea6779f3e73f 100644 --- a/drivers/dma/shdma.c +++ b/drivers/dma/shdma.c @@ -24,7 +24,10 @@ #include #include #include +#include + #include + #include "shdma.h" /* DMA descriptor control */ @@ -287,6 +290,8 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan) struct sh_desc *desc; struct sh_dmae_slave *param = chan->private; + pm_runtime_get_sync(sh_chan->dev); + /* * This relies on the guarantee from dmaengine that alloc_chan_resources * never runs concurrently with itself or free_chan_resources. @@ -328,6 +333,9 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan) } spin_unlock_bh(&sh_chan->desc_lock); + if (!sh_chan->descs_allocated) + pm_runtime_put(sh_chan->dev); + return sh_chan->descs_allocated; } @@ -339,6 +347,7 @@ static void sh_dmae_free_chan_resources(struct dma_chan *chan) struct sh_dmae_chan *sh_chan = to_sh_chan(chan); struct sh_desc *desc, *_desc; LIST_HEAD(list); + int descs = sh_chan->descs_allocated; dmae_halt(sh_chan); @@ -359,6 +368,9 @@ static void sh_dmae_free_chan_resources(struct dma_chan *chan) spin_unlock_bh(&sh_chan->desc_lock); + if (descs > 0) + pm_runtime_put(sh_chan->dev); + list_for_each_entry_safe(desc, _desc, &list, node) kfree(desc); } @@ -978,6 +990,9 @@ static int __init sh_dmae_probe(struct platform_device *pdev) /* platform data */ shdev->pdata = pdata; + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + /* reset dma controller */ err = sh_dmae_rst(shdev); if (err) @@ -1066,6 +1081,8 @@ static int __init sh_dmae_probe(struct platform_device *pdev) goto chan_probe_err; } + pm_runtime_put(&pdev->dev); + platform_set_drvdata(pdev, shdev); dma_async_device_register(&shdev->common); @@ -1079,6 +1096,7 @@ eirqres: eirq_err: #endif rst_err: + pm_runtime_put(&pdev->dev); if (dmars) iounmap(shdev->dmars); emapdmars: @@ -1108,6 +1126,8 @@ static int __exit sh_dmae_remove(struct platform_device *pdev) /* channel data remove */ sh_dmae_chan_remove(shdev); + pm_runtime_disable(&pdev->dev); + if (shdev->dmars) iounmap(shdev->dmars); iounmap(shdev->chan_reg); -- cgit v1.2.3 From c014906a870ce70e009def0c9d170ccabeb0be63 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 18 Feb 2010 16:30:02 +0000 Subject: dmaengine: shdma: extend .device_terminate_all() to record partial transfer This patch extends the .device_terminate_all() method of the shdma driver to return number of bytes transfered in the current descriptor. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt --- arch/sh/include/asm/dmaengine.h | 20 ++++++++++++++++++++ drivers/dma/shdma.c | 16 ++++++++++++++++ drivers/dma/shdma.h | 16 ---------------- 3 files changed, 36 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/arch/sh/include/asm/dmaengine.h b/arch/sh/include/asm/dmaengine.h index 9586e4a482b1..bf2f30cf0a27 100644 --- a/arch/sh/include/asm/dmaengine.h +++ b/arch/sh/include/asm/dmaengine.h @@ -10,6 +10,9 @@ #ifndef ASM_DMAENGINE_H #define ASM_DMAENGINE_H +#include +#include + #include #define SH_DMAC_MAX_CHANNELS 6 @@ -70,4 +73,21 @@ struct sh_dmae_slave { struct sh_dmae_slave_config *config; /* Set by the driver */ }; +struct sh_dmae_regs { + u32 sar; /* SAR / source address */ + u32 dar; /* DAR / destination address */ + u32 tcr; /* TCR / transfer count */ +}; + +struct sh_desc { + struct sh_dmae_regs hw; + struct list_head node; + struct dma_async_tx_descriptor async_tx; + enum dma_data_direction direction; + dma_cookie_t cookie; + size_t partial; + int chunks; + int mark; +}; + #endif diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c index ea6779f3e73f..5d17e09cb625 100644 --- a/drivers/dma/shdma.c +++ b/drivers/dma/shdma.c @@ -587,6 +587,19 @@ static void sh_dmae_terminate_all(struct dma_chan *chan) if (!chan) return; + dmae_halt(sh_chan); + + spin_lock_bh(&sh_chan->desc_lock); + if (!list_empty(&sh_chan->ld_queue)) { + /* Record partial transfer */ + struct sh_desc *desc = list_entry(sh_chan->ld_queue.next, + struct sh_desc, node); + desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) << + sh_chan->xmit_shift; + + } + spin_unlock_bh(&sh_chan->desc_lock); + sh_dmae_chan_ld_cleanup(sh_chan, true); } @@ -701,6 +714,9 @@ static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan) /* Find the first not transferred desciptor */ list_for_each_entry(desc, &sh_chan->ld_queue, node) if (desc->mark == DESC_SUBMITTED) { + dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n", + desc->async_tx.cookie, sh_chan->id, + desc->hw.tcr, desc->hw.sar, desc->hw.dar); /* Get the ld start address from ld_queue */ dmae_set_reg(sh_chan, &desc->hw); dmae_start(sh_chan); diff --git a/drivers/dma/shdma.h b/drivers/dma/shdma.h index 9f0897f7fe34..153609a1e96c 100644 --- a/drivers/dma/shdma.h +++ b/drivers/dma/shdma.h @@ -21,22 +21,6 @@ #define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */ -struct sh_dmae_regs { - u32 sar; /* SAR / source address */ - u32 dar; /* DAR / destination address */ - u32 tcr; /* TCR / transfer count */ -}; - -struct sh_desc { - struct sh_dmae_regs hw; - struct list_head node; - struct dma_async_tx_descriptor async_tx; - enum dma_data_direction direction; - dma_cookie_t cookie; - int chunks; - int mark; -}; - struct device; struct sh_dmae_chan { -- cgit v1.2.3 From 73a19e4c0301908ce6346715fd08a74308451f5a Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 2 Mar 2010 11:39:15 +0900 Subject: serial: sh-sci: Add DMA support. Support using DMA for sending and receiving data over SCI(F) interfaces of various SH SoCs. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt --- drivers/serial/Kconfig | 4 + drivers/serial/sh-sci.c | 618 +++++++++++++++++++++++++++++++++++++++++---- include/linux/serial_sci.h | 6 + 3 files changed, 582 insertions(+), 46 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 888a0ce91c4b..11ebe862457b 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -1009,6 +1009,10 @@ config SERIAL_SH_SCI_CONSOLE depends on SERIAL_SH_SCI=y select SERIAL_CORE_CONSOLE +config SERIAL_SH_SCI_DMA + bool "DMA support" + depends on SERIAL_SH_SCI && SH_DMAE && EXPERIMENTAL + config SERIAL_PNX8XXX bool "Enable PNX8XXX SoCs' UART Support" depends on MIPS && (SOC_PNX8550 || SOC_PNX833X) diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c index 42f3333c4ad0..f3841cd8fc5d 100644 --- a/drivers/serial/sh-sci.c +++ b/drivers/serial/sh-sci.c @@ -48,6 +48,9 @@ #include #include #include +#include +#include +#include #ifdef CONFIG_SUPERH #include @@ -84,6 +87,27 @@ struct sci_port { struct clk *dclk; struct list_head node; + struct dma_chan *chan_tx; + struct dma_chan *chan_rx; +#ifdef CONFIG_SERIAL_SH_SCI_DMA + struct device *dma_dev; + enum sh_dmae_slave_chan_id slave_tx; + enum sh_dmae_slave_chan_id slave_rx; + struct dma_async_tx_descriptor *desc_tx; + struct dma_async_tx_descriptor *desc_rx[2]; + dma_cookie_t cookie_tx; + dma_cookie_t cookie_rx[2]; + dma_cookie_t active_rx; + struct scatterlist sg_tx; + unsigned int sg_len_tx; + struct scatterlist sg_rx[2]; + size_t buf_len_rx; + struct sh_dmae_slave param_tx; + struct sh_dmae_slave param_rx; + struct work_struct work_tx; + struct work_struct work_rx; + struct timer_list rx_timer; +#endif }; struct sh_sci_priv { @@ -269,29 +293,44 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) defined(CONFIG_CPU_SUBTYPE_SH7780) || \ defined(CONFIG_CPU_SUBTYPE_SH7785) || \ defined(CONFIG_CPU_SUBTYPE_SH7786) -static inline int scif_txroom(struct uart_port *port) +static int scif_txfill(struct uart_port *port) { - return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); + return sci_in(port, SCTFDR) & 0xff; } -static inline int scif_rxroom(struct uart_port *port) +static int scif_txroom(struct uart_port *port) +{ + return SCIF_TXROOM_MAX - scif_txfill(port); +} + +static int scif_rxfill(struct uart_port *port) { return sci_in(port, SCRFDR) & 0xff; } #elif defined(CONFIG_CPU_SUBTYPE_SH7763) -static inline int scif_txroom(struct uart_port *port) +static int scif_txfill(struct uart_port *port) { - if ((port->mapbase == 0xffe00000) || - (port->mapbase == 0xffe08000)) { + if (port->mapbase == 0xffe00000 || + port->mapbase == 0xffe08000) /* SCIF0/1*/ - return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); - } else { + return sci_in(port, SCTFDR) & 0xff; + else /* SCIF2 */ - return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); - } + return sci_in(port, SCFDR) >> 8; +} + +static int scif_txroom(struct uart_port *port) +{ + if (port->mapbase == 0xffe00000 || + port->mapbase == 0xffe08000) + /* SCIF0/1*/ + return SCIF_TXROOM_MAX - scif_txfill(port); + else + /* SCIF2 */ + return SCIF2_TXROOM_MAX - scif_txfill(port); } -static inline int scif_rxroom(struct uart_port *port) +static int scif_rxfill(struct uart_port *port) { if ((port->mapbase == 0xffe00000) || (port->mapbase == 0xffe08000)) { @@ -303,23 +342,33 @@ static inline int scif_rxroom(struct uart_port *port) } } #else -static inline int scif_txroom(struct uart_port *port) +static int scif_txfill(struct uart_port *port) { - return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); + return sci_in(port, SCFDR) >> 8; } -static inline int scif_rxroom(struct uart_port *port) +static int scif_txroom(struct uart_port *port) +{ + return SCIF_TXROOM_MAX - scif_txfill(port); +} + +static int scif_rxfill(struct uart_port *port) { return sci_in(port, SCFDR) & SCIF_RFDC_MASK; } #endif -static inline int sci_txroom(struct uart_port *port) +static int sci_txfill(struct uart_port *port) { - return (sci_in(port, SCxSR) & SCI_TDRE) != 0; + return !(sci_in(port, SCxSR) & SCI_TDRE); } -static inline int sci_rxroom(struct uart_port *port) +static int sci_txroom(struct uart_port *port) +{ + return !sci_txfill(port); +} + +static int sci_rxfill(struct uart_port *port) { return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; } @@ -406,9 +455,9 @@ static inline void sci_receive_chars(struct uart_port *port) while (1) { if (port->type == PORT_SCI) - count = sci_rxroom(port); + count = sci_rxfill(port); else - count = scif_rxroom(port); + count = scif_rxfill(port); /* Don't copy more bytes than there is room for in the buffer */ count = tty_buffer_request_room(tty, count); @@ -453,10 +502,10 @@ static inline void sci_receive_chars(struct uart_port *port) } /* Store data and status */ - if (status&SCxSR_FER(port)) { + if (status & SCxSR_FER(port)) { flag = TTY_FRAME; dev_notice(port->dev, "frame error\n"); - } else if (status&SCxSR_PER(port)) { + } else if (status & SCxSR_PER(port)) { flag = TTY_PARITY; dev_notice(port->dev, "parity error\n"); } else @@ -618,13 +667,39 @@ static inline int sci_handle_breaks(struct uart_port *port) return copied; } -static irqreturn_t sci_rx_interrupt(int irq, void *port) +static irqreturn_t sci_rx_interrupt(int irq, void *ptr) { +#ifdef CONFIG_SERIAL_SH_SCI_DMA + struct uart_port *port = ptr; + struct sci_port *s = to_sci_port(port); + + if (s->chan_rx) { + unsigned long tout; + u16 scr = sci_in(port, SCSCR); + u16 ssr = sci_in(port, SCxSR); + + /* Disable future Rx interrupts */ + sci_out(port, SCSCR, scr & ~SCI_CTRL_FLAGS_RIE); + /* Clear current interrupt */ + sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); + /* Calculate delay for 1.5 DMA buffers */ + tout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / + port->fifosize / 2; + dev_dbg(port->dev, "Rx IRQ: setup timeout in %u ms\n", + tout * 1000 / HZ); + if (tout < 2) + tout = 2; + mod_timer(&s->rx_timer, jiffies + tout); + + return IRQ_HANDLED; + } +#endif + /* I think sci_receive_chars has to be called irrespective * of whether the I_IXOFF is set, otherwise, how is the interrupt * to be disabled? */ - sci_receive_chars(port); + sci_receive_chars(ptr); return IRQ_HANDLED; } @@ -680,6 +755,7 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) { unsigned short ssr_status, scr_status, err_enabled; struct uart_port *port = ptr; + struct sci_port *s = to_sci_port(port); irqreturn_t ret = IRQ_NONE; ssr_status = sci_in(port, SCxSR); @@ -687,10 +763,15 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE); /* Tx Interrupt */ - if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE)) + if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE) && + !s->chan_tx) ret = sci_tx_interrupt(irq, ptr); - /* Rx Interrupt */ - if ((ssr_status & SCxSR_RDxF(port)) && (scr_status & SCI_CTRL_FLAGS_RIE)) + /* + * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / + * DR flags + */ + if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && + (scr_status & SCI_CTRL_FLAGS_RIE)) ret = sci_rx_interrupt(irq, ptr); /* Error Interrupt */ if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) @@ -699,6 +780,10 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) if ((ssr_status & SCxSR_BRK(port)) && err_enabled) ret = sci_br_interrupt(irq, ptr); + WARN_ONCE(ret == IRQ_NONE, + "%s: %d IRQ %d, status %x, control %x\n", __func__, + irq, port->line, ssr_status, scr_status); + return ret; } @@ -800,7 +885,9 @@ static void sci_free_irq(struct sci_port *port) static unsigned int sci_tx_empty(struct uart_port *port) { unsigned short status = sci_in(port, SCxSR); - return status & SCxSR_TEND(port) ? TIOCSER_TEMT : 0; + unsigned short in_tx_fifo = scif_txfill(port); + + return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; } static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) @@ -812,16 +899,299 @@ static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) static unsigned int sci_get_mctrl(struct uart_port *port) { - /* This routine is used for geting signals of: DTR, DCD, DSR, RI, + /* This routine is used for getting signals of: DTR, DCD, DSR, RI, and CTS/RTS */ return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR; } +#ifdef CONFIG_SERIAL_SH_SCI_DMA +static void sci_dma_tx_complete(void *arg) +{ + struct sci_port *s = arg; + struct uart_port *port = &s->port; + struct circ_buf *xmit = &port->state->xmit; + unsigned long flags; + + dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); + + spin_lock_irqsave(&port->lock, flags); + + xmit->tail += s->sg_tx.length; + xmit->tail &= UART_XMIT_SIZE - 1; + + port->icount.tx += s->sg_tx.length; + + async_tx_ack(s->desc_tx); + s->cookie_tx = -EINVAL; + s->desc_tx = NULL; + + spin_unlock_irqrestore(&port->lock, flags); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); + + if (uart_circ_chars_pending(xmit)) + schedule_work(&s->work_tx); +} + +/* Locking: called with port lock held */ +static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty, + size_t count) +{ + struct uart_port *port = &s->port; + int i, active, room; + + room = tty_buffer_request_room(tty, count); + + if (s->active_rx == s->cookie_rx[0]) { + active = 0; + } else if (s->active_rx == s->cookie_rx[1]) { + active = 1; + } else { + dev_err(port->dev, "cookie %d not found!\n", s->active_rx); + return 0; + } + + if (room < count) + dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", + count - room); + if (!room) + return room; + + for (i = 0; i < room; i++) + tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i], + TTY_NORMAL); + + port->icount.rx += room; + + return room; +} + +static void sci_dma_rx_complete(void *arg) +{ + struct sci_port *s = arg; + struct uart_port *port = &s->port; + struct tty_struct *tty = port->state->port.tty; + unsigned long flags; + int count; + + dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); + + spin_lock_irqsave(&port->lock, flags); + + count = sci_dma_rx_push(s, tty, s->buf_len_rx); + + mod_timer(&s->rx_timer, jiffies + msecs_to_jiffies(5)); + + spin_unlock_irqrestore(&port->lock, flags); + + if (count) + tty_flip_buffer_push(tty); + + schedule_work(&s->work_rx); +} + +static void sci_start_rx(struct uart_port *port); +static void sci_start_tx(struct uart_port *port); + +static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) +{ + struct dma_chan *chan = s->chan_rx; + struct uart_port *port = &s->port; + unsigned long flags; + + s->chan_rx = NULL; + s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; + dma_release_channel(chan); + dma_free_coherent(port->dev, s->buf_len_rx * 2, + sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); + if (enable_pio) + sci_start_rx(port); +} + +static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) +{ + struct dma_chan *chan = s->chan_tx; + struct uart_port *port = &s->port; + unsigned long flags; + + s->chan_tx = NULL; + s->cookie_tx = -EINVAL; + dma_release_channel(chan); + if (enable_pio) + sci_start_tx(port); +} + +static void sci_submit_rx(struct sci_port *s) +{ + struct dma_chan *chan = s->chan_rx; + int i; + + for (i = 0; i < 2; i++) { + struct scatterlist *sg = &s->sg_rx[i]; + struct dma_async_tx_descriptor *desc; + + desc = chan->device->device_prep_slave_sg(chan, + sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT); + + if (desc) { + s->desc_rx[i] = desc; + desc->callback = sci_dma_rx_complete; + desc->callback_param = s; + s->cookie_rx[i] = desc->tx_submit(desc); + } + + if (!desc || s->cookie_rx[i] < 0) { + if (i) { + async_tx_ack(s->desc_rx[0]); + s->cookie_rx[0] = -EINVAL; + } + if (desc) { + async_tx_ack(desc); + s->cookie_rx[i] = -EINVAL; + } + dev_warn(s->port.dev, + "failed to re-start DMA, using PIO\n"); + sci_rx_dma_release(s, true); + return; + } + } + + s->active_rx = s->cookie_rx[0]; + + dma_async_issue_pending(chan); +} + +static void work_fn_rx(struct work_struct *work) +{ + struct sci_port *s = container_of(work, struct sci_port, work_rx); + struct uart_port *port = &s->port; + struct dma_async_tx_descriptor *desc; + int new; + + if (s->active_rx == s->cookie_rx[0]) { + new = 0; + } else if (s->active_rx == s->cookie_rx[1]) { + new = 1; + } else { + dev_err(port->dev, "cookie %d not found!\n", s->active_rx); + return; + } + desc = s->desc_rx[new]; + + if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != + DMA_SUCCESS) { + /* Handle incomplete DMA receive */ + struct tty_struct *tty = port->state->port.tty; + struct dma_chan *chan = s->chan_rx; + struct sh_desc *sh_desc = container_of(desc, struct sh_desc, + async_tx); + unsigned long flags; + int count; + + chan->device->device_terminate_all(chan); + dev_dbg(port->dev, "Read %u bytes with cookie %d\n", + sh_desc->partial, sh_desc->cookie); + + spin_lock_irqsave(&port->lock, flags); + count = sci_dma_rx_push(s, tty, sh_desc->partial); + spin_unlock_irqrestore(&port->lock, flags); + + if (count) + tty_flip_buffer_push(tty); + + sci_submit_rx(s); + + return; + } + + s->cookie_rx[new] = desc->tx_submit(desc); + if (s->cookie_rx[new] < 0) { + dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); + sci_rx_dma_release(s, true); + return; + } + + dev_dbg(port->dev, "%s: cookie %d #%d\n", __func__, + s->cookie_rx[new], new); + + s->active_rx = s->cookie_rx[!new]; +} + +static void work_fn_tx(struct work_struct *work) +{ + struct sci_port *s = container_of(work, struct sci_port, work_tx); + struct dma_async_tx_descriptor *desc; + struct dma_chan *chan = s->chan_tx; + struct uart_port *port = &s->port; + struct circ_buf *xmit = &port->state->xmit; + struct scatterlist *sg = &s->sg_tx; + + /* + * DMA is idle now. + * Port xmit buffer is already mapped, and it is one page... Just adjust + * offsets and lengths. Since it is a circular buffer, we have to + * transmit till the end, and then the rest. Take the port lock to get a + * consistent xmit buffer state. + */ + spin_lock_irq(&port->lock); + sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); + sg->dma_address = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + + sg->offset; + sg->length = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), + CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); + sg->dma_length = sg->length; + spin_unlock_irq(&port->lock); + + BUG_ON(!sg->length); + + desc = chan->device->device_prep_slave_sg(chan, + sg, s->sg_len_tx, DMA_TO_DEVICE, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc) { + /* switch to PIO */ + sci_tx_dma_release(s, true); + return; + } + + dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); + + spin_lock_irq(&port->lock); + s->desc_tx = desc; + desc->callback = sci_dma_tx_complete; + desc->callback_param = s; + spin_unlock_irq(&port->lock); + s->cookie_tx = desc->tx_submit(desc); + if (s->cookie_tx < 0) { + dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); + /* switch to PIO */ + sci_tx_dma_release(s, true); + return; + } + + dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, + xmit->buf, xmit->tail, xmit->head, s->cookie_tx); + + dma_async_issue_pending(chan); +} +#endif + static void sci_start_tx(struct uart_port *port) { unsigned short ctrl; +#ifdef CONFIG_SERIAL_SH_SCI_DMA + struct sci_port *s = to_sci_port(port); + + if (s->chan_tx) { + if (!uart_circ_empty(&s->port.state->xmit) && s->cookie_tx < 0) + schedule_work(&s->work_tx); + + return; + } +#endif + /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ ctrl = sci_in(port, SCSCR); ctrl |= SCI_CTRL_FLAGS_TIE; @@ -838,13 +1208,12 @@ static void sci_stop_tx(struct uart_port *port) sci_out(port, SCSCR, ctrl); } -static void sci_start_rx(struct uart_port *port, unsigned int tty_start) +static void sci_start_rx(struct uart_port *port) { - unsigned short ctrl; + unsigned short ctrl = SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE; /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ - ctrl = sci_in(port, SCSCR); - ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE; + ctrl |= sci_in(port, SCSCR); sci_out(port, SCSCR, ctrl); } @@ -868,16 +1237,154 @@ static void sci_break_ctl(struct uart_port *port, int break_state) /* Nothing here yet .. */ } +#ifdef CONFIG_SERIAL_SH_SCI_DMA +static bool filter(struct dma_chan *chan, void *slave) +{ + struct sh_dmae_slave *param = slave; + + dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, + param->slave_id); + + if (param->dma_dev == chan->device->dev) { + chan->private = param; + return true; + } else { + return false; + } +} + +static void rx_timer_fn(unsigned long arg) +{ + struct sci_port *s = (struct sci_port *)arg; + struct uart_port *port = &s->port; + + u16 scr = sci_in(port, SCSCR); + sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE); + dev_dbg(port->dev, "DMA Rx timed out\n"); + schedule_work(&s->work_rx); +} + +static void sci_request_dma(struct uart_port *port) +{ + struct sci_port *s = to_sci_port(port); + struct sh_dmae_slave *param; + struct dma_chan *chan; + dma_cap_mask_t mask; + int nent; + + dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__, + port->line, s->dma_dev); + + if (!s->dma_dev) + return; + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + + param = &s->param_tx; + + /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ + param->slave_id = s->slave_tx; + param->dma_dev = s->dma_dev; + + s->cookie_tx = -EINVAL; + chan = dma_request_channel(mask, filter, param); + dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); + if (chan) { + s->chan_tx = chan; + sg_init_table(&s->sg_tx, 1); + /* UART circular tx buffer is an aligned page. */ + BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); + sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), + UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK); + nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); + if (!nent) + sci_tx_dma_release(s, false); + else + dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, + sg_dma_len(&s->sg_tx), + port->state->xmit.buf, sg_dma_address(&s->sg_tx)); + + s->sg_len_tx = nent; + + INIT_WORK(&s->work_tx, work_fn_tx); + } + + param = &s->param_rx; + + /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ + param->slave_id = s->slave_rx; + param->dma_dev = s->dma_dev; + + chan = dma_request_channel(mask, filter, param); + dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); + if (chan) { + dma_addr_t dma[2]; + void *buf[2]; + int i; + + s->chan_rx = chan; + + s->buf_len_rx = 2 * max(16, (int)port->fifosize); + buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, + &dma[0], GFP_KERNEL); + + if (!buf[0]) { + dev_warn(port->dev, + "failed to allocate dma buffer, using PIO\n"); + sci_rx_dma_release(s, true); + return; + } + + buf[1] = buf[0] + s->buf_len_rx; + dma[1] = dma[0] + s->buf_len_rx; + + for (i = 0; i < 2; i++) { + struct scatterlist *sg = &s->sg_rx[i]; + + sg_init_table(sg, 1); + sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, + (int)buf[i] & ~PAGE_MASK); + sg->dma_address = dma[i]; + sg->dma_length = sg->length; + } + + INIT_WORK(&s->work_rx, work_fn_rx); + setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); + + sci_submit_rx(s); + } +} + +static void sci_free_dma(struct uart_port *port) +{ + struct sci_port *s = to_sci_port(port); + + if (!s->dma_dev) + return; + + if (s->chan_tx) + sci_tx_dma_release(s, false); + if (s->chan_rx) + sci_rx_dma_release(s, false); +} +#endif + static int sci_startup(struct uart_port *port) { struct sci_port *s = to_sci_port(port); + dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); + if (s->enable) s->enable(port); sci_request_irq(s); +#ifdef CONFIG_SERIAL_SH_SCI_DMA + sci_request_dma(port); +#endif sci_start_tx(port); - sci_start_rx(port, 1); + sci_start_rx(port); return 0; } @@ -886,8 +1393,13 @@ static void sci_shutdown(struct uart_port *port) { struct sci_port *s = to_sci_port(port); + dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); + sci_stop_rx(port); sci_stop_tx(port); +#ifdef CONFIG_SERIAL_SH_SCI_DMA + sci_free_dma(port); +#endif sci_free_irq(s); if (s->disable) @@ -937,6 +1449,9 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, sci_out(port, SCSMR, smr_val); + dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t, + SCSCR_INIT(port)); + if (t > 0) { if (t >= 256) { sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); @@ -954,7 +1469,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, sci_out(port, SCSCR, SCSCR_INIT(port)); if ((termios->c_cflag & CREAD) != 0) - sci_start_rx(port, 0); + sci_start_rx(port); } static const char *sci_type(struct uart_port *port) @@ -1049,19 +1564,21 @@ static void __devinit sci_init_single(struct platform_device *dev, unsigned int index, struct plat_sci_port *p) { - sci_port->port.ops = &sci_uart_ops; - sci_port->port.iotype = UPIO_MEM; - sci_port->port.line = index; + struct uart_port *port = &sci_port->port; + + port->ops = &sci_uart_ops; + port->iotype = UPIO_MEM; + port->line = index; switch (p->type) { case PORT_SCIFA: - sci_port->port.fifosize = 64; + port->fifosize = 64; break; case PORT_SCIF: - sci_port->port.fifosize = 16; + port->fifosize = 16; break; default: - sci_port->port.fifosize = 1; + port->fifosize = 1; break; } @@ -1070,19 +1587,28 @@ static void __devinit sci_init_single(struct platform_device *dev, sci_port->dclk = clk_get(&dev->dev, "peripheral_clk"); sci_port->enable = sci_clk_enable; sci_port->disable = sci_clk_disable; - sci_port->port.dev = &dev->dev; + port->dev = &dev->dev; } sci_port->break_timer.data = (unsigned long)sci_port; sci_port->break_timer.function = sci_break_timer; init_timer(&sci_port->break_timer); - sci_port->port.mapbase = p->mapbase; - sci_port->port.membase = p->membase; + port->mapbase = p->mapbase; + port->membase = p->membase; - sci_port->port.irq = p->irqs[SCIx_TXI_IRQ]; - sci_port->port.flags = p->flags; - sci_port->type = sci_port->port.type = p->type; + port->irq = p->irqs[SCIx_TXI_IRQ]; + port->flags = p->flags; + sci_port->type = port->type = p->type; + +#ifdef CONFIG_SERIAL_SH_SCI_DMA + sci_port->dma_dev = p->dma_dev; + sci_port->slave_tx = p->dma_slave_tx; + sci_port->slave_rx = p->dma_slave_rx; + + dev_dbg(port->dev, "%s: DMA device %p, tx %d, rx %d\n", __func__, + p->dma_dev, p->dma_slave_tx, p->dma_slave_rx); +#endif memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs)); } diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h index 1c297ddc9d5a..1b177d29a7f0 100644 --- a/include/linux/serial_sci.h +++ b/include/linux/serial_sci.h @@ -2,6 +2,7 @@ #define __LINUX_SERIAL_SCI_H #include +#include /* * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts) @@ -16,6 +17,8 @@ enum { SCIx_NR_IRQS, }; +struct device; + /* * Platform device specific platform_data struct */ @@ -26,6 +29,9 @@ struct plat_sci_port { unsigned int type; /* SCI / SCIF / IRDA */ upf_t flags; /* UPF_* flags */ char *clk; /* clock string */ + struct device *dma_dev; + enum sh_dmae_slave_chan_id dma_slave_tx; + enum sh_dmae_slave_chan_id dma_slave_rx; }; #endif /* __LINUX_SERIAL_SCI_H */ -- cgit v1.2.3 From c6efd46b98f30863ca3a9982312db87b826cf715 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 2 Mar 2010 11:53:54 +0900 Subject: serial: sh-sci: Tidy up build warnings. The recent sh-sci DMA support introduces a number of trivial build warnings, clean them up. Signed-off-by: Paul Mundt --- drivers/serial/sh-sci.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c index f3841cd8fc5d..980f39449ee5 100644 --- a/drivers/serial/sh-sci.c +++ b/drivers/serial/sh-sci.c @@ -685,7 +685,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr) /* Calculate delay for 1.5 DMA buffers */ tout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / port->fifosize / 2; - dev_dbg(port->dev, "Rx IRQ: setup timeout in %u ms\n", + dev_dbg(port->dev, "Rx IRQ: setup timeout in %lu ms\n", tout * 1000 / HZ); if (tout < 2) tout = 2; @@ -999,7 +999,6 @@ static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) { struct dma_chan *chan = s->chan_rx; struct uart_port *port = &s->port; - unsigned long flags; s->chan_rx = NULL; s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; @@ -1014,7 +1013,6 @@ static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) { struct dma_chan *chan = s->chan_tx; struct uart_port *port = &s->port; - unsigned long flags; s->chan_tx = NULL; s->cookie_tx = -EINVAL; -- cgit v1.2.3 From 6c664a8915f5341c2e7f1df0bb4b9b4a88f6ad77 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 9 Feb 2010 22:34:54 +0100 Subject: Debugging options for the DMA engine subsystem This adds Kconfig options for DEBUG and VERBOSE_DEBUG to the DMA engine subsystem, I got tired of editing the Makefile manually each time I want to debug things in here, modelled this on the debug switches for other subsystems and works like a charm when working on our DMA engines. Signed-off-by: Linus Walleij Signed-off-by: Dan Williams --- drivers/dma/Kconfig | 16 ++++++++++++++++ drivers/dma/Makefile | 7 +++++++ 2 files changed, 23 insertions(+) (limited to 'drivers') diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index e02d74b1e892..1f4bbd66258d 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -13,6 +13,22 @@ menuconfig DMADEVICES DMA Device drivers supported by the configured arch, it may be empty in some cases. +config DMADEVICES_DEBUG + bool "DMA Engine debugging" + depends on DMADEVICES != n + help + This is an option for use by developers; most people should + say N here. This enables DMA engine core and driver debugging. + +config DMADEVICES_VDEBUG + bool "DMA Engine verbose debugging" + depends on DMADEVICES_DEBUG != n + help + This is an option for use by developers; most people should + say N here. This enables deeper (more verbose) debugging of + the DMA engine core and drivers. + + if DMADEVICES comment "DMA Devices" diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 807053d48232..54112d67ab2e 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -1,3 +1,10 @@ +ifeq ($(CONFIG_DMADEVICES_DEBUG),y) + EXTRA_CFLAGS += -DDEBUG +endif +ifeq ($(CONFIG_DMADEVICES_VDEBUG),y) + EXTRA_CFLAGS += -DVERBOSE_DEBUG +endif + obj-$(CONFIG_DMA_ENGINE) += dmaengine.o obj-$(CONFIG_NET_DMA) += iovlock.o obj-$(CONFIG_DMATEST) += dmatest.o -- cgit v1.2.3 From 0fb6f739bb612bc989d295056877374b749e721b Mon Sep 17 00:00:00 2001 From: Piotr Ziecik Date: Fri, 5 Feb 2010 03:42:52 +0000 Subject: dma: Add MPC512x DMA driver Adds initial version of MPC512x DMA driver. Only memory to memory transfers are currenly supported. Signed-off-by: Piotr Ziecik Signed-off-by: Wolfgang Denk Signed-off-by: Anatolij Gustschin Cc: John Rigby Acked-by: Grant Likely Signed-off-by: Dan Williams --- drivers/dma/Kconfig | 7 + drivers/dma/Makefile | 1 + drivers/dma/mpc512x_dma.c | 800 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 808 insertions(+) create mode 100644 drivers/dma/mpc512x_dma.c (limited to 'drivers') diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 1f4bbd66258d..c27f80e5d531 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -85,6 +85,13 @@ config FSL_DMA The Elo is the DMA controller on some 82xx and 83xx parts, and the Elo Plus is the DMA controller on 85xx and 86xx parts. +config MPC512X_DMA + tristate "Freescale MPC512x built-in DMA engine support" + depends on PPC_MPC512x + select DMA_ENGINE + ---help--- + Enable support for the Freescale MPC512x built-in DMA engine. + config MV_XOR bool "Marvell XOR engine support" depends on PLAT_ORION diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 54112d67ab2e..22bba3d5e2b6 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_DMATEST) += dmatest.o obj-$(CONFIG_INTEL_IOATDMA) += ioat/ obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o obj-$(CONFIG_FSL_DMA) += fsldma.o +obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o obj-$(CONFIG_MV_XOR) += mv_xor.o obj-$(CONFIG_DW_DMAC) += dw_dmac.o obj-$(CONFIG_AT_HDMAC) += at_hdmac.o diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c new file mode 100644 index 000000000000..3fdf1f46bd63 --- /dev/null +++ b/drivers/dma/mpc512x_dma.c @@ -0,0 +1,800 @@ +/* + * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008. + * Copyright (C) Semihalf 2009 + * + * Written by Piotr Ziecik . Hardware description + * (defines, structures and comments) was taken from MPC5121 DMA driver + * written by Hongjun Chen . + * + * Approved as OSADL project by a majority of OSADL members and funded + * by OSADL membership fees in 2009; for details see www.osadl.org. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * The full GNU General Public License is included in this distribution in the + * file called COPYING. + */ + +/* + * This is initial version of MPC5121 DMA driver. Only memory to memory + * transfers are supported (tested using dmatest module). + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Number of DMA Transfer descriptors allocated per channel */ +#define MPC_DMA_DESCRIPTORS 64 + +/* Macro definitions */ +#define MPC_DMA_CHANNELS 64 +#define MPC_DMA_TCD_OFFSET 0x1000 + +/* Arbitration mode of group and channel */ +#define MPC_DMA_DMACR_EDCG (1 << 31) +#define MPC_DMA_DMACR_ERGA (1 << 3) +#define MPC_DMA_DMACR_ERCA (1 << 2) + +/* Error codes */ +#define MPC_DMA_DMAES_VLD (1 << 31) +#define MPC_DMA_DMAES_GPE (1 << 15) +#define MPC_DMA_DMAES_CPE (1 << 14) +#define MPC_DMA_DMAES_ERRCHN(err) \ + (((err) >> 8) & 0x3f) +#define MPC_DMA_DMAES_SAE (1 << 7) +#define MPC_DMA_DMAES_SOE (1 << 6) +#define MPC_DMA_DMAES_DAE (1 << 5) +#define MPC_DMA_DMAES_DOE (1 << 4) +#define MPC_DMA_DMAES_NCE (1 << 3) +#define MPC_DMA_DMAES_SGE (1 << 2) +#define MPC_DMA_DMAES_SBE (1 << 1) +#define MPC_DMA_DMAES_DBE (1 << 0) + +#define MPC_DMA_TSIZE_1 0x00 +#define MPC_DMA_TSIZE_2 0x01 +#define MPC_DMA_TSIZE_4 0x02 +#define MPC_DMA_TSIZE_16 0x04 +#define MPC_DMA_TSIZE_32 0x05 + +/* MPC5121 DMA engine registers */ +struct __attribute__ ((__packed__)) mpc_dma_regs { + /* 0x00 */ + u32 dmacr; /* DMA control register */ + u32 dmaes; /* DMA error status */ + /* 0x08 */ + u32 dmaerqh; /* DMA enable request high(channels 63~32) */ + u32 dmaerql; /* DMA enable request low(channels 31~0) */ + u32 dmaeeih; /* DMA enable error interrupt high(ch63~32) */ + u32 dmaeeil; /* DMA enable error interrupt low(ch31~0) */ + /* 0x18 */ + u8 dmaserq; /* DMA set enable request */ + u8 dmacerq; /* DMA clear enable request */ + u8 dmaseei; /* DMA set enable error interrupt */ + u8 dmaceei; /* DMA clear enable error interrupt */ + /* 0x1c */ + u8 dmacint; /* DMA clear interrupt request */ + u8 dmacerr; /* DMA clear error */ + u8 dmassrt; /* DMA set start bit */ + u8 dmacdne; /* DMA clear DONE status bit */ + /* 0x20 */ + u32 dmainth; /* DMA interrupt request high(ch63~32) */ + u32 dmaintl; /* DMA interrupt request low(ch31~0) */ + u32 dmaerrh; /* DMA error high(ch63~32) */ + u32 dmaerrl; /* DMA error low(ch31~0) */ + /* 0x30 */ + u32 dmahrsh; /* DMA hw request status high(ch63~32) */ + u32 dmahrsl; /* DMA hardware request status low(ch31~0) */ + u32 dmaihsa; /* DMA interrupt high select AXE(ch63~32) */ + u32 dmailsa; /* DMA interrupt low select AXE(ch31~0) */ + /* 0x40 ~ 0xff */ + u32 reserve0[48]; /* Reserved */ + /* 0x100 */ + u8 dchpri[MPC_DMA_CHANNELS]; + /* DMA channels(0~63) priority */ +}; + +struct __attribute__ ((__packed__)) mpc_dma_tcd { + /* 0x00 */ + u32 saddr; /* Source address */ + + u32 smod:5; /* Source address modulo */ + u32 ssize:3; /* Source data transfer size */ + u32 dmod:5; /* Destination address modulo */ + u32 dsize:3; /* Destination data transfer size */ + u32 soff:16; /* Signed source address offset */ + + /* 0x08 */ + u32 nbytes; /* Inner "minor" byte count */ + u32 slast; /* Last source address adjustment */ + u32 daddr; /* Destination address */ + + /* 0x14 */ + u32 citer_elink:1; /* Enable channel-to-channel linking on + * minor loop complete + */ + u32 citer_linkch:6; /* Link channel for minor loop complete */ + u32 citer:9; /* Current "major" iteration count */ + u32 doff:16; /* Signed destination address offset */ + + /* 0x18 */ + u32 dlast_sga; /* Last Destination address adjustment/scatter + * gather address + */ + + /* 0x1c */ + u32 biter_elink:1; /* Enable channel-to-channel linking on major + * loop complete + */ + u32 biter_linkch:6; + u32 biter:9; /* Beginning "major" iteration count */ + u32 bwc:2; /* Bandwidth control */ + u32 major_linkch:6; /* Link channel number */ + u32 done:1; /* Channel done */ + u32 active:1; /* Channel active */ + u32 major_elink:1; /* Enable channel-to-channel linking on major + * loop complete + */ + u32 e_sg:1; /* Enable scatter/gather processing */ + u32 d_req:1; /* Disable request */ + u32 int_half:1; /* Enable an interrupt when major counter is + * half complete + */ + u32 int_maj:1; /* Enable an interrupt when major iteration + * count completes + */ + u32 start:1; /* Channel start */ +}; + +struct mpc_dma_desc { + struct dma_async_tx_descriptor desc; + struct mpc_dma_tcd *tcd; + dma_addr_t tcd_paddr; + int error; + struct list_head node; +}; + +struct mpc_dma_chan { + struct dma_chan chan; + struct list_head free; + struct list_head prepared; + struct list_head queued; + struct list_head active; + struct list_head completed; + struct mpc_dma_tcd *tcd; + dma_addr_t tcd_paddr; + dma_cookie_t completed_cookie; + + /* Lock for this structure */ + spinlock_t lock; +}; + +struct mpc_dma { + struct dma_device dma; + struct tasklet_struct tasklet; + struct mpc_dma_chan channels[MPC_DMA_CHANNELS]; + struct mpc_dma_regs __iomem *regs; + struct mpc_dma_tcd __iomem *tcd; + int irq; + uint error_status; + + /* Lock for error_status field in this structure */ + spinlock_t error_status_lock; +}; + +#define DRV_NAME "mpc512x_dma" + +/* Convert struct dma_chan to struct mpc_dma_chan */ +static inline struct mpc_dma_chan *dma_chan_to_mpc_dma_chan(struct dma_chan *c) +{ + return container_of(c, struct mpc_dma_chan, chan); +} + +/* Convert struct dma_chan to struct mpc_dma */ +static inline struct mpc_dma *dma_chan_to_mpc_dma(struct dma_chan *c) +{ + struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(c); + return container_of(mchan, struct mpc_dma, channels[c->chan_id]); +} + +/* + * Execute all queued DMA descriptors. + * + * Following requirements must be met while calling mpc_dma_execute(): + * a) mchan->lock is acquired, + * b) mchan->active list is empty, + * c) mchan->queued list contains at least one entry. + */ +static void mpc_dma_execute(struct mpc_dma_chan *mchan) +{ + struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan); + struct mpc_dma_desc *first = NULL; + struct mpc_dma_desc *prev = NULL; + struct mpc_dma_desc *mdesc; + int cid = mchan->chan.chan_id; + + /* Move all queued descriptors to active list */ + list_splice_tail_init(&mchan->queued, &mchan->active); + + /* Chain descriptors into one transaction */ + list_for_each_entry(mdesc, &mchan->active, node) { + if (!first) + first = mdesc; + + if (!prev) { + prev = mdesc; + continue; + } + + prev->tcd->dlast_sga = mdesc->tcd_paddr; + prev->tcd->e_sg = 1; + mdesc->tcd->start = 1; + + prev = mdesc; + } + + prev->tcd->start = 0; + prev->tcd->int_maj = 1; + + /* Send first descriptor in chain into hardware */ + memcpy_toio(&mdma->tcd[cid], first->tcd, sizeof(struct mpc_dma_tcd)); + out_8(&mdma->regs->dmassrt, cid); +} + +/* Handle interrupt on one half of DMA controller (32 channels) */ +static void mpc_dma_irq_process(struct mpc_dma *mdma, u32 is, u32 es, int off) +{ + struct mpc_dma_chan *mchan; + struct mpc_dma_desc *mdesc; + u32 status = is | es; + int ch; + + while ((ch = fls(status) - 1) >= 0) { + status &= ~(1 << ch); + mchan = &mdma->channels[ch + off]; + + spin_lock(&mchan->lock); + + /* Check error status */ + if (es & (1 << ch)) + list_for_each_entry(mdesc, &mchan->active, node) + mdesc->error = -EIO; + + /* Execute queued descriptors */ + list_splice_tail_init(&mchan->active, &mchan->completed); + if (!list_empty(&mchan->queued)) + mpc_dma_execute(mchan); + + spin_unlock(&mchan->lock); + } +} + +/* Interrupt handler */ +static irqreturn_t mpc_dma_irq(int irq, void *data) +{ + struct mpc_dma *mdma = data; + uint es; + + /* Save error status register */ + es = in_be32(&mdma->regs->dmaes); + spin_lock(&mdma->error_status_lock); + if ((es & MPC_DMA_DMAES_VLD) && mdma->error_status == 0) + mdma->error_status = es; + spin_unlock(&mdma->error_status_lock); + + /* Handle interrupt on each channel */ + mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmainth), + in_be32(&mdma->regs->dmaerrh), 32); + mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmaintl), + in_be32(&mdma->regs->dmaerrl), 0); + + /* Ack interrupt on all channels */ + out_be32(&mdma->regs->dmainth, 0xFFFFFFFF); + out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF); + out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF); + out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF); + + /* Schedule tasklet */ + tasklet_schedule(&mdma->tasklet); + + return IRQ_HANDLED; +} + +/* DMA Tasklet */ +static void mpc_dma_tasklet(unsigned long data) +{ + struct mpc_dma *mdma = (void *)data; + dma_cookie_t last_cookie = 0; + struct mpc_dma_chan *mchan; + struct mpc_dma_desc *mdesc; + struct dma_async_tx_descriptor *desc; + unsigned long flags; + LIST_HEAD(list); + uint es; + int i; + + spin_lock_irqsave(&mdma->error_status_lock, flags); + es = mdma->error_status; + mdma->error_status = 0; + spin_unlock_irqrestore(&mdma->error_status_lock, flags); + + /* Print nice error report */ + if (es) { + dev_err(mdma->dma.dev, + "Hardware reported following error(s) on channel %u:\n", + MPC_DMA_DMAES_ERRCHN(es)); + + if (es & MPC_DMA_DMAES_GPE) + dev_err(mdma->dma.dev, "- Group Priority Error\n"); + if (es & MPC_DMA_DMAES_CPE) + dev_err(mdma->dma.dev, "- Channel Priority Error\n"); + if (es & MPC_DMA_DMAES_SAE) + dev_err(mdma->dma.dev, "- Source Address Error\n"); + if (es & MPC_DMA_DMAES_SOE) + dev_err(mdma->dma.dev, "- Source Offset" + " Configuration Error\n"); + if (es & MPC_DMA_DMAES_DAE) + dev_err(mdma->dma.dev, "- Destination Address" + " Error\n"); + if (es & MPC_DMA_DMAES_DOE) + dev_err(mdma->dma.dev, "- Destination Offset" + " Configuration Error\n"); + if (es & MPC_DMA_DMAES_NCE) + dev_err(mdma->dma.dev, "- NBytes/Citter" + " Configuration Error\n"); + if (es & MPC_DMA_DMAES_SGE) + dev_err(mdma->dma.dev, "- Scatter/Gather" + " Configuration Error\n"); + if (es & MPC_DMA_DMAES_SBE) + dev_err(mdma->dma.dev, "- Source Bus Error\n"); + if (es & MPC_DMA_DMAES_DBE) + dev_err(mdma->dma.dev, "- Destination Bus Error\n"); + } + + for (i = 0; i < mdma->dma.chancnt; i++) { + mchan = &mdma->channels[i]; + + /* Get all completed descriptors */ + spin_lock_irqsave(&mchan->lock, flags); + if (!list_empty(&mchan->completed)) + list_splice_tail_init(&mchan->completed, &list); + spin_unlock_irqrestore(&mchan->lock, flags); + + if (list_empty(&list)) + continue; + + /* Execute callbacks and run dependencies */ + list_for_each_entry(mdesc, &list, node) { + desc = &mdesc->desc; + + if (desc->callback) + desc->callback(desc->callback_param); + + last_cookie = desc->cookie; + dma_run_dependencies(desc); + } + + /* Free descriptors */ + spin_lock_irqsave(&mchan->lock, flags); + list_splice_tail_init(&list, &mchan->free); + mchan->completed_cookie = last_cookie; + spin_unlock_irqrestore(&mchan->lock, flags); + } +} + +/* Submit descriptor to hardware */ +static dma_cookie_t mpc_dma_tx_submit(struct dma_async_tx_descriptor *txd) +{ + struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(txd->chan); + struct mpc_dma_desc *mdesc; + unsigned long flags; + dma_cookie_t cookie; + + mdesc = container_of(txd, struct mpc_dma_desc, desc); + + spin_lock_irqsave(&mchan->lock, flags); + + /* Move descriptor to queue */ + list_move_tail(&mdesc->node, &mchan->queued); + + /* If channel is idle, execute all queued descriptors */ + if (list_empty(&mchan->active)) + mpc_dma_execute(mchan); + + /* Update cookie */ + cookie = mchan->chan.cookie + 1; + if (cookie <= 0) + cookie = 1; + + mchan->chan.cookie = cookie; + mdesc->desc.cookie = cookie; + + spin_unlock_irqrestore(&mchan->lock, flags); + + return cookie; +} + +/* Alloc channel resources */ +static int mpc_dma_alloc_chan_resources(struct dma_chan *chan) +{ + struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan); + struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); + struct mpc_dma_desc *mdesc; + struct mpc_dma_tcd *tcd; + dma_addr_t tcd_paddr; + unsigned long flags; + LIST_HEAD(descs); + int i; + + /* Alloc DMA memory for Transfer Control Descriptors */ + tcd = dma_alloc_coherent(mdma->dma.dev, + MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd), + &tcd_paddr, GFP_KERNEL); + if (!tcd) + return -ENOMEM; + + /* Alloc descriptors for this channel */ + for (i = 0; i < MPC_DMA_DESCRIPTORS; i++) { + mdesc = kzalloc(sizeof(struct mpc_dma_desc), GFP_KERNEL); + if (!mdesc) { + dev_notice(mdma->dma.dev, "Memory allocation error. " + "Allocated only %u descriptors\n", i); + break; + } + + dma_async_tx_descriptor_init(&mdesc->desc, chan); + mdesc->desc.flags = DMA_CTRL_ACK; + mdesc->desc.tx_submit = mpc_dma_tx_submit; + + mdesc->tcd = &tcd[i]; + mdesc->tcd_paddr = tcd_paddr + (i * sizeof(struct mpc_dma_tcd)); + + list_add_tail(&mdesc->node, &descs); + } + + /* Return error only if no descriptors were allocated */ + if (i == 0) { + dma_free_coherent(mdma->dma.dev, + MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd), + tcd, tcd_paddr); + return -ENOMEM; + } + + spin_lock_irqsave(&mchan->lock, flags); + mchan->tcd = tcd; + mchan->tcd_paddr = tcd_paddr; + list_splice_tail_init(&descs, &mchan->free); + spin_unlock_irqrestore(&mchan->lock, flags); + + /* Enable Error Interrupt */ + out_8(&mdma->regs->dmaseei, chan->chan_id); + + return 0; +} + +/* Free channel resources */ +static void mpc_dma_free_chan_resources(struct dma_chan *chan) +{ + struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan); + struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); + struct mpc_dma_desc *mdesc, *tmp; + struct mpc_dma_tcd *tcd; + dma_addr_t tcd_paddr; + unsigned long flags; + LIST_HEAD(descs); + + spin_lock_irqsave(&mchan->lock, flags); + + /* Channel must be idle */ + BUG_ON(!list_empty(&mchan->prepared)); + BUG_ON(!list_empty(&mchan->queued)); + BUG_ON(!list_empty(&mchan->active)); + BUG_ON(!list_empty(&mchan->completed)); + + /* Move data */ + list_splice_tail_init(&mchan->free, &descs); + tcd = mchan->tcd; + tcd_paddr = mchan->tcd_paddr; + + spin_unlock_irqrestore(&mchan->lock, flags); + + /* Free DMA memory used by descriptors */ + dma_free_coherent(mdma->dma.dev, + MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd), + tcd, tcd_paddr); + + /* Free descriptors */ + list_for_each_entry_safe(mdesc, tmp, &descs, node) + kfree(mdesc); + + /* Disable Error Interrupt */ + out_8(&mdma->regs->dmaceei, chan->chan_id); +} + +/* Send all pending descriptor to hardware */ +static void mpc_dma_issue_pending(struct dma_chan *chan) +{ + /* + * We are posting descriptors to the hardware as soon as + * they are ready, so this function does nothing. + */ +} + +/* Check request completion status */ +static enum dma_status +mpc_dma_is_tx_complete(struct dma_chan *chan, dma_cookie_t cookie, + dma_cookie_t *done, dma_cookie_t *used) +{ + struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); + unsigned long flags; + dma_cookie_t last_used; + dma_cookie_t last_complete; + + spin_lock_irqsave(&mchan->lock, flags); + last_used = mchan->chan.cookie; + last_complete = mchan->completed_cookie; + spin_unlock_irqrestore(&mchan->lock, flags); + + if (done) + *done = last_complete; + + if (used) + *used = last_used; + + return dma_async_is_complete(cookie, last_complete, last_used); +} + +/* Prepare descriptor for memory to memory copy */ +static struct dma_async_tx_descriptor * +mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, + size_t len, unsigned long flags) +{ + struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); + struct mpc_dma_desc *mdesc = NULL; + struct mpc_dma_tcd *tcd; + unsigned long iflags; + + /* Get free descriptor */ + spin_lock_irqsave(&mchan->lock, iflags); + if (!list_empty(&mchan->free)) { + mdesc = list_first_entry(&mchan->free, struct mpc_dma_desc, + node); + list_del(&mdesc->node); + } + spin_unlock_irqrestore(&mchan->lock, iflags); + + if (!mdesc) + return NULL; + + mdesc->error = 0; + tcd = mdesc->tcd; + + /* Prepare Transfer Control Descriptor for this transaction */ + memset(tcd, 0, sizeof(struct mpc_dma_tcd)); + + if (IS_ALIGNED(src | dst | len, 32)) { + tcd->ssize = MPC_DMA_TSIZE_32; + tcd->dsize = MPC_DMA_TSIZE_32; + tcd->soff = 32; + tcd->doff = 32; + } else if (IS_ALIGNED(src | dst | len, 16)) { + tcd->ssize = MPC_DMA_TSIZE_16; + tcd->dsize = MPC_DMA_TSIZE_16; + tcd->soff = 16; + tcd->doff = 16; + } else if (IS_ALIGNED(src | dst | len, 4)) { + tcd->ssize = MPC_DMA_TSIZE_4; + tcd->dsize = MPC_DMA_TSIZE_4; + tcd->soff = 4; + tcd->doff = 4; + } else if (IS_ALIGNED(src | dst | len, 2)) { + tcd->ssize = MPC_DMA_TSIZE_2; + tcd->dsize = MPC_DMA_TSIZE_2; + tcd->soff = 2; + tcd->doff = 2; + } else { + tcd->ssize = MPC_DMA_TSIZE_1; + tcd->dsize = MPC_DMA_TSIZE_1; + tcd->soff = 1; + tcd->doff = 1; + } + + tcd->saddr = src; + tcd->daddr = dst; + tcd->nbytes = len; + tcd->biter = 1; + tcd->citer = 1; + + /* Place descriptor in prepared list */ + spin_lock_irqsave(&mchan->lock, iflags); + list_add_tail(&mdesc->node, &mchan->prepared); + spin_unlock_irqrestore(&mchan->lock, iflags); + + return &mdesc->desc; +} + +static int __devinit mpc_dma_probe(struct of_device *op, + const struct of_device_id *match) +{ + struct device_node *dn = op->node; + struct device *dev = &op->dev; + struct dma_device *dma; + struct mpc_dma *mdma; + struct mpc_dma_chan *mchan; + struct resource res; + ulong regs_start, regs_size; + int retval, i; + + mdma = devm_kzalloc(dev, sizeof(struct mpc_dma), GFP_KERNEL); + if (!mdma) { + dev_err(dev, "Memory exhausted!\n"); + return -ENOMEM; + } + + mdma->irq = irq_of_parse_and_map(dn, 0); + if (mdma->irq == NO_IRQ) { + dev_err(dev, "Error mapping IRQ!\n"); + return -EINVAL; + } + + retval = of_address_to_resource(dn, 0, &res); + if (retval) { + dev_err(dev, "Error parsing memory region!\n"); + return retval; + } + + regs_start = res.start; + regs_size = res.end - res.start + 1; + + if (!devm_request_mem_region(dev, regs_start, regs_size, DRV_NAME)) { + dev_err(dev, "Error requesting memory region!\n"); + return -EBUSY; + } + + mdma->regs = devm_ioremap(dev, regs_start, regs_size); + if (!mdma->regs) { + dev_err(dev, "Error mapping memory region!\n"); + return -ENOMEM; + } + + mdma->tcd = (struct mpc_dma_tcd *)((u8 *)(mdma->regs) + + MPC_DMA_TCD_OFFSET); + + retval = devm_request_irq(dev, mdma->irq, &mpc_dma_irq, 0, DRV_NAME, + mdma); + if (retval) { + dev_err(dev, "Error requesting IRQ!\n"); + return -EINVAL; + } + + spin_lock_init(&mdma->error_status_lock); + + dma = &mdma->dma; + dma->dev = dev; + dma->chancnt = MPC_DMA_CHANNELS; + dma->device_alloc_chan_resources = mpc_dma_alloc_chan_resources; + dma->device_free_chan_resources = mpc_dma_free_chan_resources; + dma->device_issue_pending = mpc_dma_issue_pending; + dma->device_is_tx_complete = mpc_dma_is_tx_complete; + dma->device_prep_dma_memcpy = mpc_dma_prep_memcpy; + + INIT_LIST_HEAD(&dma->channels); + dma_cap_set(DMA_MEMCPY, dma->cap_mask); + + for (i = 0; i < dma->chancnt; i++) { + mchan = &mdma->channels[i]; + + mchan->chan.device = dma; + mchan->chan.chan_id = i; + mchan->chan.cookie = 1; + mchan->completed_cookie = mchan->chan.cookie; + + INIT_LIST_HEAD(&mchan->free); + INIT_LIST_HEAD(&mchan->prepared); + INIT_LIST_HEAD(&mchan->queued); + INIT_LIST_HEAD(&mchan->active); + INIT_LIST_HEAD(&mchan->completed); + + spin_lock_init(&mchan->lock); + list_add_tail(&mchan->chan.device_node, &dma->channels); + } + + tasklet_init(&mdma->tasklet, mpc_dma_tasklet, (unsigned long)mdma); + + /* + * Configure DMA Engine: + * - Dynamic clock, + * - Round-robin group arbitration, + * - Round-robin channel arbitration. + */ + out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG | + MPC_DMA_DMACR_ERGA | MPC_DMA_DMACR_ERCA); + + /* Disable hardware DMA requests */ + out_be32(&mdma->regs->dmaerqh, 0); + out_be32(&mdma->regs->dmaerql, 0); + + /* Disable error interrupts */ + out_be32(&mdma->regs->dmaeeih, 0); + out_be32(&mdma->regs->dmaeeil, 0); + + /* Clear interrupts status */ + out_be32(&mdma->regs->dmainth, 0xFFFFFFFF); + out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF); + out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF); + out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF); + + /* Route interrupts to IPIC */ + out_be32(&mdma->regs->dmaihsa, 0); + out_be32(&mdma->regs->dmailsa, 0); + + /* Register DMA engine */ + dev_set_drvdata(dev, mdma); + retval = dma_async_device_register(dma); + if (retval) { + devm_free_irq(dev, mdma->irq, mdma); + irq_dispose_mapping(mdma->irq); + } + + return retval; +} + +static int __devexit mpc_dma_remove(struct of_device *op) +{ + struct device *dev = &op->dev; + struct mpc_dma *mdma = dev_get_drvdata(dev); + + dma_async_device_unregister(&mdma->dma); + devm_free_irq(dev, mdma->irq, mdma); + irq_dispose_mapping(mdma->irq); + + return 0; +} + +static struct of_device_id mpc_dma_match[] = { + { .compatible = "fsl,mpc5121-dma", }, + {}, +}; + +static struct of_platform_driver mpc_dma_driver = { + .match_table = mpc_dma_match, + .probe = mpc_dma_probe, + .remove = __devexit_p(mpc_dma_remove), + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init mpc_dma_init(void) +{ + return of_register_platform_driver(&mpc_dma_driver); +} +module_init(mpc_dma_init); + +static void __exit mpc_dma_exit(void) +{ + of_unregister_platform_driver(&mpc_dma_driver); +} +module_exit(mpc_dma_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Piotr Ziecik "); -- cgit v1.2.3 From 57e413d95b0f92b9a5569408ddc3441e0f20e856 Mon Sep 17 00:00:00 2001 From: Ping Cheng Date: Mon, 1 Mar 2010 23:50:24 -0800 Subject: Input: wacom - replace WACOM_PKGLEN_PENABLED Replacing WACOM_PKGLEN_PENABLED with WACOM_PKGLEN_GRAPHIRE since they both represent the same value, 8. This value will be used for both Tablet PC and Bamboo with touch devices. Signed-off-by: Ping Cheng Signed-off-by: Dmitry Torokhov --- drivers/input/tablet/wacom_sys.c | 4 ++-- drivers/input/tablet/wacom_wac.c | 2 +- drivers/input/tablet/wacom_wac.h | 1 - 3 files changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c index a1770e6feeec..8b5d2873f0c4 100644 --- a/drivers/input/tablet/wacom_sys.c +++ b/drivers/input/tablet/wacom_sys.c @@ -371,7 +371,7 @@ static int wacom_parse_hid(struct usb_interface *intf, struct hid_descriptor *hi } else if (pen) { /* penabled only accepts exact bytes of data */ if (features->type == TABLETPC2FG) - features->pktlen = WACOM_PKGLEN_PENABLED; + features->pktlen = WACOM_PKGLEN_GRAPHIRE; features->device_type = BTN_TOOL_PEN; features->x_max = wacom_le16_to_cpu(&report[i + 3]); @@ -410,7 +410,7 @@ static int wacom_parse_hid(struct usb_interface *intf, struct hid_descriptor *hi } else if (pen) { /* penabled only accepts exact bytes of data */ if (features->type == TABLETPC2FG) - features->pktlen = WACOM_PKGLEN_PENABLED; + features->pktlen = WACOM_PKGLEN_GRAPHIRE; features->device_type = BTN_TOOL_PEN; features->y_max = wacom_le16_to_cpu(&report[i + 3]); diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c index 3d81443e683a..4a852d815c68 100644 --- a/drivers/input/tablet/wacom_wac.c +++ b/drivers/input/tablet/wacom_wac.c @@ -1028,7 +1028,7 @@ static const struct wacom_features wacom_features_0x93 = static const struct wacom_features wacom_features_0x9A = { "Wacom ISDv4 9A", WACOM_PKGLEN_GRAPHIRE, 26202, 16325, 255, 0, TABLETPC }; static const struct wacom_features wacom_features_0x9F = - { "Wacom ISDv4 9F", WACOM_PKGLEN_PENABLED, 26202, 16325, 255, 0, TABLETPC }; + { "Wacom ISDv4 9F", WACOM_PKGLEN_GRAPHIRE, 26202, 16325, 255, 0, TABLETPC }; static const struct wacom_features wacom_features_0xE2 = { "Wacom ISDv4 E2", WACOM_PKGLEN_TPC2FG, 26202, 16325, 255, 0, TABLETPC2FG }; static const struct wacom_features wacom_features_0xE3 = diff --git a/drivers/input/tablet/wacom_wac.h b/drivers/input/tablet/wacom_wac.h index 8590b1e8ec37..b50cf04e61a8 100644 --- a/drivers/input/tablet/wacom_wac.h +++ b/drivers/input/tablet/wacom_wac.h @@ -17,7 +17,6 @@ #define WACOM_PKGLEN_GRAPHIRE 8 #define WACOM_PKGLEN_BBFUN 9 #define WACOM_PKGLEN_INTUOS 10 -#define WACOM_PKGLEN_PENABLED 8 #define WACOM_PKGLEN_TPC1FG 5 #define WACOM_PKGLEN_TPC2FG 14 -- cgit v1.2.3 From bc505f373979692d51a86d40925f77a8b09d17b9 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Sun, 29 Nov 2009 17:52:00 +0200 Subject: virtio: set pci bus master enable bit As all virtio devices perform DMA, we must enable bus mastering for them to be spec compliant. This patch fixes hotplug of virtio devices with Linux guests and qemu 0.11-0.12. Tested-by: Alexander Graf Signed-off-by: Michael S. Tsirkin --- drivers/virtio/virtio_pci.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/virtio/virtio_pci.c b/drivers/virtio/virtio_pci.c index 1b6573216998..625447f645d9 100644 --- a/drivers/virtio/virtio_pci.c +++ b/drivers/virtio/virtio_pci.c @@ -649,6 +649,7 @@ static int __devinit virtio_pci_probe(struct pci_dev *pci_dev, goto out_req_regions; pci_set_drvdata(pci_dev, vp_dev); + pci_set_master(pci_dev); /* we use the subsystem vendor/device id as the virtio vendor/device * id. this allows us to use the same PCI vendor/device id for all -- cgit v1.2.3 From 6510b8917948283005a125c8337d3312a8a0561c Mon Sep 17 00:00:00 2001 From: Stanislaw Gruszka Date: Fri, 26 Feb 2010 15:10:28 +0100 Subject: airo: return from set_wep_key() when key length is zero Even if keylen == 0 is a bug and should not really happen, better avoid possibility of passing bad value to firmware. Signed-off-by: Stanislaw Gruszka Signed-off-by: John W. Linville --- drivers/net/wireless/airo.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/wireless/airo.c b/drivers/net/wireless/airo.c index 698d5672a070..dc5018a6d9ed 100644 --- a/drivers/net/wireless/airo.c +++ b/drivers/net/wireless/airo.c @@ -5255,7 +5255,8 @@ static int set_wep_key(struct airo_info *ai, u16 index, const char *key, WepKeyRid wkr; int rc; - WARN_ON(keylen == 0); + if (WARN_ON(keylen == 0)) + return -1; memset(&wkr, 0, sizeof(wkr)); wkr.len = cpu_to_le16(sizeof(wkr)); -- cgit v1.2.3 From 86baf712295a00d664da8566186b67041c89b15b Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sat, 27 Feb 2010 09:12:34 +0300 Subject: zd1211rw: fix potential array underflow The first chunk fixes a debugging assert to print a warning about array underflows. The second chunk corrects a potential array underflow. I also removed an assert in the second chunk because it can no longer happen. Signed-off-by: Dan Carpenter Acked-by: Benoit Papillault Signed-off-by: John W. Linville --- drivers/net/wireless/zd1211rw/zd_mac.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/zd1211rw/zd_mac.c b/drivers/net/wireless/zd1211rw/zd_mac.c index 2d555cc30508..e24099613d91 100644 --- a/drivers/net/wireless/zd1211rw/zd_mac.c +++ b/drivers/net/wireless/zd1211rw/zd_mac.c @@ -350,7 +350,7 @@ static void zd_mac_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, first_idx = info->status.rates[0].idx; ZD_ASSERT(0<=first_idx && first_idxcount); + ZD_ASSERT(1 <= retry && retry <= retries->count); info->status.rates[0].idx = retries->rate[0]; info->status.rates[0].count = 1; // (retry > 1 ? 2 : 1); @@ -360,7 +360,7 @@ static void zd_mac_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, info->status.rates[i].count = 1; // ((i==retry-1) && success ? 1:2); } for (; istatus.rates[i].idx = retries->rate[retry-1]; + info->status.rates[i].idx = retries->rate[retry - 1]; info->status.rates[i].count = 1; // (success ? 1:2); } if (istatus.rates[0].idx; ZD_ASSERT(0<=first_idx && first_idx retries->count) { + if (retry <= 0 || retry > retries->count) continue; - } - ZD_ASSERT(0<=retry && retry<=retries->count); - final_idx = retries->rate[retry-1]; + final_idx = retries->rate[retry - 1]; final_rate = zd_rates[final_idx].hw_value; if (final_rate != tx_status->rate) { -- cgit v1.2.3 From a9f042cbe5284f34ccff15f3084477e11b39b17b Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Sun, 28 Feb 2010 00:56:24 +0800 Subject: ath9k: fix lockdep warning when unloading module Since txq->axq_lock may be hold in softirq context, it must be acquired with spin_lock_bh() instead of spin_lock() if softieq is enabled. The patch fixes the lockdep warning below when unloading ath9k modules. ================================= [ INFO: inconsistent lock state ] 2.6.33-wl #12 --------------------------------- inconsistent {IN-SOFTIRQ-W} -> {SOFTIRQ-ON-W} usage. rmmod/3642 [HC0[0]:SC0[0]:HE1:SE1] takes: (&(&txq->axq_lock)->rlock){+.?...}, at: [] ath_tx_node_cleanup+0x62/0x180 [ath9k] {IN-SOFTIRQ-W} state was registered at: [] __lock_acquire+0x2f6/0xd35 [] lock_acquire+0xcd/0xf1 [] _raw_spin_lock_bh+0x3b/0x6e [] spin_lock_bh+0xe/0x10 [ath9k] [] ath_tx_tasklet+0xcd/0x391 [ath9k] [] ath9k_tasklet+0x70/0xc8 [ath9k] [] tasklet_action+0x8c/0xf4 [] __do_softirq+0xf8/0x1cd [] call_softirq+0x1c/0x30 [] do_softirq+0x4b/0xa3 [] irq_exit+0x4a/0x8c [] do_IRQ+0xac/0xc3 [] ret_from_intr+0x0/0x16 [] cpuidle_idle_call+0x9e/0xf8 [] cpu_idle+0x62/0x9d [] rest_init+0x7e/0x80 [] start_kernel+0x3e8/0x3f3 [] x86_64_start_reservations+0xa7/0xab [] x86_64_start_kernel+0xf8/0x107 irq event stamp: 42037 hardirqs last enabled at (42037): [] _raw_spin_unlock_irqrestore+0x47/0x56 hardirqs last disabled at (42036): [] _raw_spin_lock_irqsave+0x2b/0x88 softirqs last enabled at (42000): [] spin_unlock_bh+0xe/0x10 [ath9k] softirqs last disabled at (41998): [] _raw_spin_lock_bh+0x18/0x6e other info that might help us debug this: 4 locks held by rmmod/3642: #0: (rtnl_mutex){+.+.+.}, at: [] rtnl_lock+0x17/0x19 #1: (&wdev->mtx){+.+.+.}, at: [] cfg80211_netdev_notifier_call+0x28d/0x46d [cfg80211] #2: (&ifmgd->mtx){+.+.+.}, at: [] ieee80211_mgd_deauth+0x3f/0x17e [mac80211] #3: (&local->sta_mtx){+.+.+.}, at: [] sta_info_destroy_addr+0x2b/0x5e [mac80211] stack backtrace: Pid: 3642, comm: rmmod Not tainted 2.6.33-wl #12 Call Trace: [] valid_state+0x178/0x18b [] ? save_stack_trace+0x2f/0x4c [] ? check_usage_backwards+0x0/0x88 [] mark_lock+0x113/0x230 [] __lock_acquire+0x36a/0xd35 [] ? native_sched_clock+0x2d/0x5f [] ? ath_tx_node_cleanup+0x62/0x180 [ath9k] [] lock_acquire+0xcd/0xf1 [] ? ath_tx_node_cleanup+0x62/0x180 [ath9k] [] ? trace_hardirqs_off+0xd/0xf [] _raw_spin_lock+0x36/0x69 [] ? ath_tx_node_cleanup+0x62/0x180 [ath9k] [] ath_tx_node_cleanup+0x62/0x180 [ath9k] [] ? trace_hardirqs_on+0xd/0xf [] ath9k_sta_remove+0x22/0x26 [ath9k] [] __sta_info_destroy+0x1ad/0x38c [mac80211] [] sta_info_destroy_addr+0x3e/0x5e [mac80211] [] ieee80211_set_disassoc+0x175/0x180 [mac80211] [] ieee80211_mgd_deauth+0x58/0x17e [mac80211] [] ? __mutex_lock_common+0x37f/0x3a4 [] ? cfg80211_netdev_notifier_call+0x28d/0x46d [cfg80211] [] ieee80211_deauth+0x1e/0x20 [mac80211] [] __cfg80211_mlme_deauth+0x130/0x13f [cfg80211] [] ? cfg80211_netdev_notifier_call+0x28d/0x46d [cfg80211] [] ? trace_hardirqs_off+0xd/0xf [] __cfg80211_disconnect+0x111/0x189 [cfg80211] [] cfg80211_netdev_notifier_call+0x2ce/0x46d [cfg80211] [] notifier_call_chain+0x37/0x63 [] raw_notifier_call_chain+0x14/0x16 [] call_netdevice_notifiers+0x1b/0x1d [] dev_close+0x6a/0xa6 [] rollback_registered_many+0xb6/0x2f4 [] unregister_netdevice_many+0x1b/0x66 [] ieee80211_remove_interfaces+0xc5/0xd0 [mac80211] [] ieee80211_unregister_hw+0x47/0xe8 [mac80211] [] ath9k_deinit_device+0x7a/0x9b [ath9k] [] ath_pci_remove+0x38/0x76 [ath9k] [] pci_device_remove+0x2d/0x51 [] __device_release_driver+0x7b/0xd1 [] driver_detach+0x98/0xbe [] bus_remove_driver+0x94/0xb7 [] driver_unregister+0x6c/0x74 [] pci_unregister_driver+0x46/0xad [] ath_pci_exit+0x15/0x17 [ath9k] [] ath9k_exit+0xe/0x2f [ath9k] [] sys_delete_module+0x1c7/0x236 [] ? retint_swapgs+0x13/0x1b [] ? trace_hardirqs_on_caller+0x119/0x144 [] ? audit_syscall_entry+0x11e/0x14a [] system_call_fastpath+0x16/0x1b wlan1: deauthenticating from 00:23:cd:e1:f9:b2 by local choice (reason=3) PM: Removing info for No Bus:wlan1 cfg80211: Calling CRDA to update world regulatory domain PM: Removing info for No Bus:rfkill2 PM: Removing info for No Bus:phy1 ath9k 0000:16:00.0: PCI INT A disabled Signed-off-by: Ming Lei Signed-off-by: John W. Linville --- drivers/net/wireless/ath/ath9k/xmit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c index 47294f90bbe5..b2c8207f7bc1 100644 --- a/drivers/net/wireless/ath/ath9k/xmit.c +++ b/drivers/net/wireless/ath/ath9k/xmit.c @@ -2258,7 +2258,7 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) if (ATH_TXQ_SETUP(sc, i)) { txq = &sc->tx.txq[i]; - spin_lock(&txq->axq_lock); + spin_lock_bh(&txq->axq_lock); list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { @@ -2279,7 +2279,7 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) } } - spin_unlock(&txq->axq_lock); + spin_unlock_bh(&txq->axq_lock); } } } -- cgit v1.2.3 From 51b2853fd91a3c8fd9f3adc1549569d2c1dc2a2d Mon Sep 17 00:00:00 2001 From: Bryan Polk Date: Mon, 1 Mar 2010 12:23:28 -0500 Subject: rt2x00: Add USB ID for CEIVA adapter to rt73usb This adds support for CEIVA USB wireless adapters to the rt73usb driver. Signed-off-by: Bryan Polk Acked-by: Ivo van Doorn Acked-by: Gertjan van Wingerde Signed-off-by: John W. Linville --- drivers/net/wireless/rt2x00/rt73usb.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c index f39a8ed17841..47f3e4a26d77 100644 --- a/drivers/net/wireless/rt2x00/rt73usb.c +++ b/drivers/net/wireless/rt2x00/rt73usb.c @@ -2352,6 +2352,8 @@ static struct usb_device_id rt73usb_device_table[] = { { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) }, { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) }, { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) }, + /* CEIVA */ + { USB_DEVICE(0x178d, 0x02be), USB_DEVICE_DATA(&rt73usb_ops) }, /* CNet */ { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) }, { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) }, -- cgit v1.2.3 From 6e93d7195e75741e9ebe23ca5591977d0b39ecc0 Mon Sep 17 00:00:00 2001 From: Helmut Schaa Date: Tue, 2 Mar 2010 16:34:49 +0100 Subject: rt2x00: fix rt2800pci compilation with SoC Compiling rt2800pci with CONFIG_RT2800PCI_SOC fails with "... rt2880pci.c: error: incompatible type for argument 2 of 'rt2x00soc_probe'". Fix this by using &rt2800pci_ops instead of rt2800pci_ops. Signed-off-by: Helmut Schaa Signed-off-by: John W. Linville --- drivers/net/wireless/rt2x00/rt2800pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c index aca8c124f434..91cce2d0f6db 100644 --- a/drivers/net/wireless/rt2x00/rt2800pci.c +++ b/drivers/net/wireless/rt2x00/rt2800pci.c @@ -1225,7 +1225,7 @@ MODULE_LICENSE("GPL"); #ifdef CONFIG_RT2800PCI_SOC static int rt2800soc_probe(struct platform_device *pdev) { - return rt2x00soc_probe(pdev, rt2800pci_ops); + return rt2x00soc_probe(pdev, &rt2800pci_ops); } static struct platform_driver rt2800soc_driver = { -- cgit v1.2.3 From 535765179fd4e8af26b69d2240d7ec33702a370a Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Wed, 23 Dec 2009 13:15:30 +0100 Subject: ar9170: load firmware asynchronously This converts ar9170 to load firmware asynchronously out of ->probe() and only register with mac80211 when all firmware has been loaded successfully. If, on the other hand, any firmware fails to load, it will now unbind from the device. Signed-off-by: Johannes Berg Signed-off-by: John W. Linville --- drivers/net/wireless/ath/ar9170/ar9170.h | 1 + drivers/net/wireless/ath/ar9170/main.c | 10 +- drivers/net/wireless/ath/ar9170/usb.c | 170 +++++++++++++++++++------------ 3 files changed, 111 insertions(+), 70 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/ath/ar9170/ar9170.h b/drivers/net/wireless/ath/ar9170/ar9170.h index 8c8ce67971e9..dc662b76a1c8 100644 --- a/drivers/net/wireless/ath/ar9170/ar9170.h +++ b/drivers/net/wireless/ath/ar9170/ar9170.h @@ -166,6 +166,7 @@ struct ar9170 { struct ath_common common; struct mutex mutex; enum ar9170_device_state state; + bool registered; unsigned long bad_hw_nagger; int (*open)(struct ar9170 *); diff --git a/drivers/net/wireless/ath/ar9170/main.c b/drivers/net/wireless/ath/ar9170/main.c index 8a964f130367..f4650fcdebc9 100644 --- a/drivers/net/wireless/ath/ar9170/main.c +++ b/drivers/net/wireless/ath/ar9170/main.c @@ -2701,7 +2701,8 @@ int ar9170_register(struct ar9170 *ar, struct device *pdev) dev_info(pdev, "Atheros AR9170 is registered as '%s'\n", wiphy_name(ar->hw->wiphy)); - return err; + ar->registered = true; + return 0; err_unreg: ieee80211_unregister_hw(ar->hw); @@ -2712,11 +2713,14 @@ err_out: void ar9170_unregister(struct ar9170 *ar) { + if (ar->registered) { #ifdef CONFIG_AR9170_LEDS - ar9170_unregister_leds(ar); + ar9170_unregister_leds(ar); #endif /* CONFIG_AR9170_LEDS */ - kfree_skb(ar->rx_failover); ieee80211_unregister_hw(ar->hw); + } + + kfree_skb(ar->rx_failover); mutex_destroy(&ar->mutex); } diff --git a/drivers/net/wireless/ath/ar9170/usb.c b/drivers/net/wireless/ath/ar9170/usb.c index 0f361186b78f..4e30197afff6 100644 --- a/drivers/net/wireless/ath/ar9170/usb.c +++ b/drivers/net/wireless/ath/ar9170/usb.c @@ -582,43 +582,6 @@ static int ar9170_usb_upload(struct ar9170_usb *aru, const void *data, return 0; } -static int ar9170_usb_request_firmware(struct ar9170_usb *aru) -{ - int err = 0; - - err = request_firmware(&aru->firmware, "ar9170.fw", - &aru->udev->dev); - if (!err) { - aru->init_values = NULL; - return 0; - } - - if (aru->req_one_stage_fw) { - dev_err(&aru->udev->dev, "ar9170.fw firmware file " - "not found and is required for this device\n"); - return -EINVAL; - } - - dev_err(&aru->udev->dev, "ar9170.fw firmware file " - "not found, trying old firmware...\n"); - - err = request_firmware(&aru->init_values, "ar9170-1.fw", - &aru->udev->dev); - if (err) { - dev_err(&aru->udev->dev, "file with init values not found.\n"); - return err; - } - - err = request_firmware(&aru->firmware, "ar9170-2.fw", &aru->udev->dev); - if (err) { - release_firmware(aru->init_values); - dev_err(&aru->udev->dev, "firmware file not found.\n"); - return err; - } - - return err; -} - static int ar9170_usb_reset(struct ar9170_usb *aru) { int ret, lock = (aru->intf->condition != USB_INTERFACE_BINDING); @@ -757,6 +720,103 @@ err_out: return err; } +static void ar9170_usb_firmware_failed(struct ar9170_usb *aru) +{ + struct device *parent = aru->udev->dev.parent; + + /* unbind anything failed */ + if (parent) + down(&parent->sem); + device_release_driver(&aru->udev->dev); + if (parent) + up(&parent->sem); +} + +static void ar9170_usb_firmware_finish(const struct firmware *fw, void *context) +{ + struct ar9170_usb *aru = context; + int err; + + aru->firmware = fw; + + if (!fw) { + dev_err(&aru->udev->dev, "firmware file not found.\n"); + goto err_freefw; + } + + err = ar9170_usb_init_device(aru); + if (err) + goto err_freefw; + + err = ar9170_usb_open(&aru->common); + if (err) + goto err_unrx; + + err = ar9170_register(&aru->common, &aru->udev->dev); + + ar9170_usb_stop(&aru->common); + if (err) + goto err_unrx; + + return; + + err_unrx: + ar9170_usb_cancel_urbs(aru); + + err_freefw: + ar9170_usb_firmware_failed(aru); +} + +static void ar9170_usb_firmware_inits(const struct firmware *fw, + void *context) +{ + struct ar9170_usb *aru = context; + int err; + + if (!fw) { + dev_err(&aru->udev->dev, "file with init values not found.\n"); + ar9170_usb_firmware_failed(aru); + return; + } + + aru->init_values = fw; + + /* ok so we have the init values -- get code for two-stage */ + + err = request_firmware_nowait(THIS_MODULE, 1, "ar9170-2.fw", + &aru->udev->dev, GFP_KERNEL, aru, + ar9170_usb_firmware_finish); + if (err) + ar9170_usb_firmware_failed(aru); +} + +static void ar9170_usb_firmware_step2(const struct firmware *fw, void *context) +{ + struct ar9170_usb *aru = context; + int err; + + if (fw) { + ar9170_usb_firmware_finish(fw, context); + return; + } + + if (aru->req_one_stage_fw) { + dev_err(&aru->udev->dev, "ar9170.fw firmware file " + "not found and is required for this device\n"); + ar9170_usb_firmware_failed(aru); + return; + } + + dev_err(&aru->udev->dev, "ar9170.fw firmware file " + "not found, trying old firmware...\n"); + + err = request_firmware_nowait(THIS_MODULE, 1, "ar9170-1.fw", + &aru->udev->dev, GFP_KERNEL, aru, + ar9170_usb_firmware_inits); + if (err) + ar9170_usb_firmware_failed(aru); +} + static bool ar9170_requires_one_stage(const struct usb_device_id *id) { if (!id->driver_info) @@ -814,33 +874,9 @@ static int ar9170_usb_probe(struct usb_interface *intf, if (err) goto err_freehw; - err = ar9170_usb_request_firmware(aru); - if (err) - goto err_freehw; - - err = ar9170_usb_init_device(aru); - if (err) - goto err_freefw; - - err = ar9170_usb_open(ar); - if (err) - goto err_unrx; - - err = ar9170_register(ar, &udev->dev); - - ar9170_usb_stop(ar); - if (err) - goto err_unrx; - - return 0; - -err_unrx: - ar9170_usb_cancel_urbs(aru); - -err_freefw: - release_firmware(aru->init_values); - release_firmware(aru->firmware); - + return request_firmware_nowait(THIS_MODULE, 1, "ar9170.fw", + &aru->udev->dev, GFP_KERNEL, aru, + ar9170_usb_firmware_step2); err_freehw: usb_set_intfdata(intf, NULL); usb_put_dev(udev); @@ -860,12 +896,12 @@ static void ar9170_usb_disconnect(struct usb_interface *intf) ar9170_unregister(&aru->common); ar9170_usb_cancel_urbs(aru); - release_firmware(aru->init_values); - release_firmware(aru->firmware); - usb_put_dev(aru->udev); usb_set_intfdata(intf, NULL); ieee80211_free_hw(aru->common.hw); + + release_firmware(aru->init_values); + release_firmware(aru->firmware); } #ifdef CONFIG_PM -- cgit v1.2.3 From b08dfd0435333818a03b38867c556ebcbb3abc02 Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Fri, 29 Jan 2010 11:54:56 -0800 Subject: iwlwifi: load firmware asynchronously before mac80211 registration At the wireless summit in Portland we discussed a way of loading firmware asynchronously from ->probe() before registration to mac80211, in order to register with the wireless subsystems with complete information in cases where firmware is required to know parameters. This is not yet the case in iwlwifi, but for some new features we're working on it will be the case since those will only be supported by new firmware images. Hence, to start with, convert iwlwifi to load firmware asynchronously from probe, unbinding the device when firmware loading fails, and only registering with the wireless subsystems after firmware has been loaded successfully. Future patches will hook into this to register the new firmware capabilities, depending on the firmware API version. Signed-off-by: Johannes Berg Signed-off-by: Reinette Chatre Signed-off-by: John W. Linville --- drivers/net/wireless/iwlwifi/iwl-agn.c | 157 +++++++++++++++++---------------- drivers/net/wireless/iwlwifi/iwl-dev.h | 2 + 2 files changed, 81 insertions(+), 78 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index 6aeb82b6992f..47b021477967 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c @@ -1463,59 +1463,66 @@ static void iwl_nic_start(struct iwl_priv *priv) } +static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context); +static int iwl_mac_setup_register(struct iwl_priv *priv); + +static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first) +{ + const char *name_pre = priv->cfg->fw_name_pre; + + if (first) + priv->fw_index = priv->cfg->ucode_api_max; + else + priv->fw_index--; + + if (priv->fw_index < priv->cfg->ucode_api_min) { + IWL_ERR(priv, "no suitable firmware found!\n"); + return -ENOENT; + } + + sprintf(priv->firmware_name, "%s%d%s", + name_pre, priv->fw_index, ".ucode"); + + IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n", + priv->firmware_name); + + return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name, + &priv->pci_dev->dev, GFP_KERNEL, priv, + iwl_ucode_callback); +} + /** - * iwl_read_ucode - Read uCode images from disk file. + * iwl_ucode_callback - callback when firmware was loaded * - * Copy into buffers for card to fetch via bus-mastering + * If loaded successfully, copies the firmware into buffers + * for the card to fetch (via DMA). */ -static int iwl_read_ucode(struct iwl_priv *priv) +static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) { + struct iwl_priv *priv = context; struct iwl_ucode_header *ucode; - int ret = -EINVAL, index; - const struct firmware *ucode_raw; - const char *name_pre = priv->cfg->fw_name_pre; const unsigned int api_max = priv->cfg->ucode_api_max; const unsigned int api_min = priv->cfg->ucode_api_min; - char buf[25]; u8 *src; size_t len; u32 api_ver, build; u32 inst_size, data_size, init_size, init_data_size, boot_size; + int err; u16 eeprom_ver; - /* Ask kernel firmware_class module to get the boot firmware off disk. - * request_firmware() is synchronous, file is in memory on return. */ - for (index = api_max; index >= api_min; index--) { - sprintf(buf, "%s%d%s", name_pre, index, ".ucode"); - ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); - if (ret < 0) { - IWL_ERR(priv, "%s firmware file req failed: %d\n", - buf, ret); - if (ret == -ENOENT) - continue; - else - goto error; - } else { - if (index < api_max) - IWL_ERR(priv, "Loaded firmware %s, " - "which is deprecated. " - "Please use API v%u instead.\n", - buf, api_max); - - IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n", - buf, ucode_raw->size); - break; - } + if (!ucode_raw) { + IWL_ERR(priv, "request for firmware file '%s' failed.\n", + priv->firmware_name); + goto try_again; } - if (ret < 0) - goto error; + IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n", + priv->firmware_name, ucode_raw->size); /* Make sure that we got at least the v1 header! */ if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) { IWL_ERR(priv, "File size way too small!\n"); - ret = -EINVAL; - goto err_release; + goto try_again; } /* Data from ucode file: header followed by uCode images */ @@ -1540,10 +1547,9 @@ static int iwl_read_ucode(struct iwl_priv *priv) IWL_ERR(priv, "Driver unable to support your firmware API. " "Driver supports v%u, firmware is v%u.\n", api_max, api_ver); - priv->ucode_ver = 0; - ret = -EINVAL; - goto err_release; + goto try_again; } + if (api_ver != api_max) IWL_ERR(priv, "Firmware has old API version. Expected v%u, " "got v%u. New firmware can be obtained " @@ -1585,6 +1591,12 @@ static int iwl_read_ucode(struct iwl_priv *priv) IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", boot_size); + /* + * For any of the failures below (before allocating pci memory) + * we will try to load a version with a smaller API -- maybe the + * user just got a corrupted version of the latest API. + */ + /* Verify size of file vs. image size info in file's header */ if (ucode_raw->size != priv->cfg->ops->ucode->get_header_size(api_ver) + @@ -1594,41 +1606,35 @@ static int iwl_read_ucode(struct iwl_priv *priv) IWL_DEBUG_INFO(priv, "uCode file size %d does not match expected size\n", (int)ucode_raw->size); - ret = -EINVAL; - goto err_release; + goto try_again; } /* Verify that uCode images will fit in card's SRAM */ if (inst_size > priv->hw_params.max_inst_size) { IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", inst_size); - ret = -EINVAL; - goto err_release; + goto try_again; } if (data_size > priv->hw_params.max_data_size) { IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", data_size); - ret = -EINVAL; - goto err_release; + goto try_again; } if (init_size > priv->hw_params.max_inst_size) { IWL_INFO(priv, "uCode init instr len %d too large to fit in\n", init_size); - ret = -EINVAL; - goto err_release; + goto try_again; } if (init_data_size > priv->hw_params.max_data_size) { IWL_INFO(priv, "uCode init data len %d too large to fit in\n", init_data_size); - ret = -EINVAL; - goto err_release; + goto try_again; } if (boot_size > priv->hw_params.max_bsm_size) { IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n", boot_size); - ret = -EINVAL; - goto err_release; + goto try_again; } /* Allocate ucode buffers for card's bus-master loading ... */ @@ -1712,20 +1718,36 @@ static int iwl_read_ucode(struct iwl_priv *priv) IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len); memcpy(priv->ucode_boot.v_addr, src, len); + /************************************************** + * This is still part of probe() in a sense... + * + * 9. Setup and register with mac80211 and debugfs + **************************************************/ + err = iwl_mac_setup_register(priv); + if (err) + goto out_unbind; + + err = iwl_dbgfs_register(priv, DRV_NAME); + if (err) + IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); + /* We have our copies now, allow OS release its copies */ release_firmware(ucode_raw); - return 0; + return; + + try_again: + /* try next, if any */ + if (iwl_request_firmware(priv, false)) + goto out_unbind; + release_firmware(ucode_raw); + return; err_pci_alloc: IWL_ERR(priv, "failed to allocate pci memory\n"); - ret = -ENOMEM; iwl_dealloc_ucode_pci(priv); - - err_release: + out_unbind: + device_release_driver(&priv->pci_dev->dev); release_firmware(ucode_raw); - - error: - return ret; } static const char *desc_lookup_text[] = { @@ -2667,21 +2689,7 @@ static int iwl_mac_start(struct ieee80211_hw *hw) /* we should be verifying the device is ready to be opened */ mutex_lock(&priv->mutex); - - /* fetch ucode file from disk, alloc and copy to bus-master buffers ... - * ucode filename and max sizes are card-specific. */ - - if (!priv->ucode_code.len) { - ret = iwl_read_ucode(priv); - if (ret) { - IWL_ERR(priv, "Could not read microcode: %d\n", ret); - mutex_unlock(&priv->mutex); - return ret; - } - } - ret = __iwl_up(priv); - mutex_unlock(&priv->mutex); if (ret) @@ -3654,17 +3662,10 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) iwl_power_initialize(priv); iwl_tt_initialize(priv); - /************************************************** - * 9. Setup and register with mac80211 and debugfs - **************************************************/ - err = iwl_mac_setup_register(priv); + err = iwl_request_firmware(priv, true); if (err) goto out_remove_sysfs; - err = iwl_dbgfs_register(priv, DRV_NAME); - if (err) - IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); - return 0; out_remove_sysfs: diff --git a/drivers/net/wireless/iwlwifi/iwl-dev.h b/drivers/net/wireless/iwlwifi/iwl-dev.h index ab891b958042..6054c5fba0c1 100644 --- a/drivers/net/wireless/iwlwifi/iwl-dev.h +++ b/drivers/net/wireless/iwlwifi/iwl-dev.h @@ -1132,6 +1132,7 @@ struct iwl_priv { u8 rev_id; /* uCode images, save to reload in case of failure */ + int fw_index; /* firmware we're trying to load */ u32 ucode_ver; /* version of ucode, copy of iwl_ucode.ver */ struct fw_desc ucode_code; /* runtime inst */ @@ -1142,6 +1143,7 @@ struct iwl_priv { struct fw_desc ucode_boot; /* bootstrap inst */ enum ucode_type ucode_type; u8 ucode_write_complete; /* the image write is complete */ + char firmware_name[25]; struct iwl_rxon_time_cmd rxon_timing; -- cgit v1.2.3 From 848ad121240f539e14a59eddd69e164aea9560b2 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 2 Mar 2010 14:17:15 -0700 Subject: DMAENGINE: COH 901 318 cleanups This cleans up the some debug code that was not working in the COH 901 318 driver, adds some helpful comments and rearrange the code a bit. Signed-off-by: Linus Walleij Signed-off-by: Dan Williams --- drivers/dma/coh901318.c | 42 ++++++++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c index 64a937262a40..f1bf4f74ad8f 100644 --- a/drivers/dma/coh901318.c +++ b/drivers/dma/coh901318.c @@ -80,18 +80,16 @@ struct coh901318_chan { static void coh901318_list_print(struct coh901318_chan *cohc, struct coh901318_lli *lli) { - struct coh901318_lli *l; - dma_addr_t addr = virt_to_phys(lli); + struct coh901318_lli *l = lli; int i = 0; - while (addr) { - l = phys_to_virt(addr); + while (l) { dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x" - ", dst 0x%x, link 0x%x link_virt 0x%p\n", + ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n", i, l, l->control, l->src_addr, l->dst_addr, - l->link_addr, phys_to_virt(l->link_addr)); + l->link_addr, l->virt_link_addr); i++; - addr = l->link_addr; + l = l->virt_link_addr; } } @@ -125,7 +123,7 @@ static int coh901318_debugfs_read(struct file *file, char __user *buf, goto err_kmalloc; tmp = dev_buf; - tmp += sprintf(tmp, "DMA -- enable dma channels\n"); + tmp += sprintf(tmp, "DMA -- enabled dma channels\n"); for (i = 0; i < debugfs_dma_base->platform->max_channels; i++) if (started_channels & (1 << i)) @@ -592,6 +590,10 @@ static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc) return cohd_que; } +/* + * This tasklet is called from the interrupt handler to + * handle each descriptor (DMA job) that is sent to a channel. + */ static void dma_tasklet(unsigned long data) { struct coh901318_chan *cohc = (struct coh901318_chan *) data; @@ -600,9 +602,13 @@ static void dma_tasklet(unsigned long data) dma_async_tx_callback callback; void *callback_param; + dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d" + " nbr_active_done %ld\n", __func__, + cohc->id, cohc->nbr_active_done); + spin_lock_irqsave(&cohc->lock, flags); - /* get first active entry from list */ + /* get first active descriptor entry from list */ cohd_fin = coh901318_first_active_get(cohc); BUG_ON(cohd_fin->pending_irqs == 0); @@ -636,10 +642,19 @@ static void dma_tasklet(unsigned long data) coh901318_desc_free(cohc, cohd_fin); } + /* + * If another interrupt fired while the tasklet was scheduling, + * we don't get called twice, so we have this number of active + * counter that keep track of the number of IRQs expected to + * be handled for this channel. If there happen to be more than + * one IRQ to be ack:ed, we simply schedule this tasklet again. + */ if (cohc->nbr_active_done) cohc->nbr_active_done--; if (cohc->nbr_active_done) { + dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs " + "came in while we were scheduling this tasklet\n"); if (cohc_chan_conf(cohc)->priority_high) tasklet_hi_schedule(&cohc->tasklet); else @@ -994,6 +1009,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, len += factor; } + pr_debug("Allocate %d lli:s for this transfer\n", len); data = coh901318_lli_alloc(&cohc->base->pool, len); if (data == NULL) @@ -1092,9 +1108,8 @@ coh901318_terminate_all(struct dma_chan *chan) /* release the lli allocation*/ coh901318_lli_free(&cohc->base->pool, &cohd->data); - coh901318_desc_remove(cohd); - /* return desc to free-list */ + coh901318_desc_remove(cohd); coh901318_desc_free(cohc, cohd); } @@ -1102,9 +1117,8 @@ coh901318_terminate_all(struct dma_chan *chan) /* release the lli allocation*/ coh901318_lli_free(&cohc->base->pool, &cohd->data); - coh901318_desc_remove(cohd); - /* return desc to free-list */ + coh901318_desc_remove(cohd); coh901318_desc_free(cohc, cohd); } @@ -1259,7 +1273,7 @@ static int __init coh901318_probe(struct platform_device *pdev) if (err) goto err_register_memcpy; - dev_dbg(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n", + dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n", (u32) base->virtbase); return err; -- cgit v1.2.3 From b87108a772e001af3fa79f9cfd87b190375f47a2 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 2 Mar 2010 14:17:20 -0700 Subject: DMAENGINE: COH 901 318 descriptor pool refactoring This centralize some spread-out initialization of descriptors into one function and cleans up the error paths. Signed-off-by: Linus Walleij Signed-off-by: Dan Williams --- arch/arm/mach-u300/include/mach/coh901318.h | 2 +- drivers/dma/coh901318.c | 54 +++++++++++++---------------- 2 files changed, 26 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h index f4cfee9c7d28..b8155b4e5ffa 100644 --- a/arch/arm/mach-u300/include/mach/coh901318.h +++ b/arch/arm/mach-u300/include/mach/coh901318.h @@ -53,7 +53,7 @@ struct coh901318_params { * struct coh_dma_channel - dma channel base * @name: ascii name of dma channel * @number: channel id number - * @desc_nbr_max: number of preallocated descriptortors + * @desc_nbr_max: number of preallocated descriptors * @priority_high: prio of channel, 0 low otherwise high. * @param: configuration parameters * @dev_addr: physical address of periphal connected to channel diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c index f1bf4f74ad8f..12a7a151be6a 100644 --- a/drivers/dma/coh901318.c +++ b/drivers/dma/coh901318.c @@ -335,16 +335,22 @@ coh901318_desc_get(struct coh901318_chan *cohc) * TODO: alloc a pile of descs instead of just one, * avoid many small allocations. */ - desc = kmalloc(sizeof(struct coh901318_desc), GFP_NOWAIT); + desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT); if (desc == NULL) goto out; INIT_LIST_HEAD(&desc->node); + dma_async_tx_descriptor_init(&desc->desc, &cohc->chan); } else { /* Reuse an old desc. */ desc = list_first_entry(&cohc->free, struct coh901318_desc, node); list_del(&desc->node); + /* Initialize it a bit so it's not insane */ + desc->sg = NULL; + desc->sg_len = 0; + desc->desc.callback = NULL; + desc->desc.callback_param = NULL; } out: @@ -885,6 +891,7 @@ coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, struct coh901318_chan *cohc = to_coh901318_chan(chan); int lli_len; u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last; + int ret; spin_lock_irqsave(&cohc->lock, flg); @@ -905,22 +912,19 @@ coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, if (data == NULL) goto err; - cohd = coh901318_desc_get(cohc); - cohd->sg = NULL; - cohd->sg_len = 0; - cohd->data = data; - - cohd->pending_irqs = - coh901318_lli_fill_memcpy( - &cohc->base->pool, data, src, size, dest, - cohc_chan_param(cohc)->ctrl_lli_chained, - ctrl_last); - cohd->flags = flags; + ret = coh901318_lli_fill_memcpy( + &cohc->base->pool, data, src, size, dest, + cohc_chan_param(cohc)->ctrl_lli_chained, + ctrl_last); + if (ret) + goto err; COH_DBG(coh901318_list_print(cohc, data)); - dma_async_tx_descriptor_init(&cohd->desc, chan); - + /* Pick a descriptor to handle this transfer */ + cohd = coh901318_desc_get(cohc); + cohd->data = data; + cohd->flags = flags; cohd->desc.tx_submit = coh901318_tx_submit; spin_unlock_irqrestore(&cohc->lock, flg); @@ -962,11 +966,6 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, /* Trigger interrupt after last lli */ ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE; - cohd = coh901318_desc_get(cohc); - cohd->sg = NULL; - cohd->sg_len = 0; - cohd->dir = direction; - if (direction == DMA_TO_DEVICE) { u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE; @@ -984,11 +983,6 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, } else goto err_direction; - dma_async_tx_descriptor_init(&cohd->desc, chan); - - cohd->desc.tx_submit = coh901318_tx_submit; - - /* The dma only supports transmitting packages up to * MAX_DMA_PACKET_SIZE. Calculate to total number of * dma elemts required to send the entire sg list @@ -1023,19 +1017,21 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, ctrl, ctrl_last, direction, COH901318_CX_CTRL_TC_IRQ_ENABLE); - cohd->data = data; - - cohd->flags = flags; COH_DBG(coh901318_list_print(cohc, data)); + /* Pick a descriptor to handle this transfer */ + cohd = coh901318_desc_get(cohc); + cohd->dir = direction; + cohd->flags = flags; + cohd->desc.tx_submit = coh901318_tx_submit; + cohd->data = data; + spin_unlock_irqrestore(&cohc->lock, flg); return &cohd->desc; err_dma_alloc: err_direction: - coh901318_desc_remove(cohd); - coh901318_desc_free(cohc, cohd); spin_unlock_irqrestore(&cohc->lock, flg); out: return NULL; -- cgit v1.2.3 From 0b58828c923e57f1bfbbd2c4277ceb60666314fa Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 2 Mar 2010 14:17:44 -0700 Subject: DMAENGINE: COH 901 318 remove irq counting This removes the pointless irq counting for the COH 901 318, as it turns out the hardware will only ever fire one IRQ for a linked list anyway. In the process also a missing spinlock was introduced. Signed-off-by: Linus Walleij Signed-off-by: Dan Williams --- drivers/dma/coh901318.c | 76 ++++++++++++++++++--------------------------- drivers/dma/coh901318_lli.c | 13 ++------ 2 files changed, 34 insertions(+), 55 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c index 12a7a151be6a..544c46278f84 100644 --- a/drivers/dma/coh901318.c +++ b/drivers/dma/coh901318.c @@ -39,7 +39,6 @@ struct coh901318_desc { unsigned int sg_len; struct coh901318_lli *data; enum dma_data_direction dir; - int pending_irqs; unsigned long flags; }; @@ -72,7 +71,6 @@ struct coh901318_chan { unsigned long nbr_active_done; unsigned long busy; - int pending_irqs; struct coh901318_base *base; }; @@ -368,10 +366,6 @@ static void coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc) { list_add_tail(&desc->node, &cohc->active); - - BUG_ON(cohc->pending_irqs != 0); - - cohc->pending_irqs = desc->pending_irqs; } static struct coh901318_desc * @@ -617,36 +611,30 @@ static void dma_tasklet(unsigned long data) /* get first active descriptor entry from list */ cohd_fin = coh901318_first_active_get(cohc); - BUG_ON(cohd_fin->pending_irqs == 0); - if (cohd_fin == NULL) goto err; - cohd_fin->pending_irqs--; - cohc->completed = cohd_fin->desc.cookie; + /* locate callback to client */ + callback = cohd_fin->desc.callback; + callback_param = cohd_fin->desc.callback_param; - if (cohc->nbr_active_done == 0) - return; + /* sign this job as completed on the channel */ + cohc->completed = cohd_fin->desc.cookie; - if (!cohd_fin->pending_irqs) { - /* release the lli allocation*/ - coh901318_lli_free(&cohc->base->pool, &cohd_fin->data); - } + /* release the lli allocation and remove the descriptor */ + coh901318_lli_free(&cohc->base->pool, &cohd_fin->data); - dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d pending_irqs %d" - " nbr_active_done %ld\n", __func__, - cohc->id, cohc->pending_irqs, cohc->nbr_active_done); + /* return desc to free-list */ + coh901318_desc_remove(cohd_fin); + coh901318_desc_free(cohc, cohd_fin); - /* callback to client */ - callback = cohd_fin->desc.callback; - callback_param = cohd_fin->desc.callback_param; + spin_unlock_irqrestore(&cohc->lock, flags); - if (!cohd_fin->pending_irqs) { - coh901318_desc_remove(cohd_fin); + /* Call the callback when we're done */ + if (callback) + callback(callback_param); - /* return desc to free-list */ - coh901318_desc_free(cohc, cohd_fin); - } + spin_lock_irqsave(&cohc->lock, flags); /* * If another interrupt fired while the tasklet was scheduling, @@ -655,9 +643,7 @@ static void dma_tasklet(unsigned long data) * be handled for this channel. If there happen to be more than * one IRQ to be ack:ed, we simply schedule this tasklet again. */ - if (cohc->nbr_active_done) - cohc->nbr_active_done--; - + cohc->nbr_active_done--; if (cohc->nbr_active_done) { dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs " "came in while we were scheduling this tasklet\n"); @@ -666,10 +652,8 @@ static void dma_tasklet(unsigned long data) else tasklet_schedule(&cohc->tasklet); } - spin_unlock_irqrestore(&cohc->lock, flags); - if (callback) - callback(callback_param); + spin_unlock_irqrestore(&cohc->lock, flags); return; @@ -688,16 +672,17 @@ static void dma_tc_handle(struct coh901318_chan *cohc) if (!cohc->allocated) return; - BUG_ON(cohc->pending_irqs == 0); + spin_lock(&cohc->lock); - cohc->pending_irqs--; cohc->nbr_active_done++; - if (cohc->pending_irqs == 0 && coh901318_queue_start(cohc) == NULL) + if (coh901318_queue_start(cohc) == NULL) cohc->busy = 0; BUG_ON(list_empty(&cohc->active)); + spin_unlock(&cohc->lock); + if (cohc_chan_conf(cohc)->priority_high) tasklet_hi_schedule(&cohc->tasklet); else @@ -951,6 +936,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, u32 ctrl = cohc_chan_param(cohc)->ctrl_lli; u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last; unsigned long flg; + int ret; if (!sgl) goto out; @@ -1010,13 +996,14 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, goto err_dma_alloc; /* initiate allocated data list */ - cohd->pending_irqs = - coh901318_lli_fill_sg(&cohc->base->pool, data, sgl, sg_len, - cohc_dev_addr(cohc), - ctrl_chained, - ctrl, - ctrl_last, - direction, COH901318_CX_CTRL_TC_IRQ_ENABLE); + ret = coh901318_lli_fill_sg(&cohc->base->pool, data, sgl, sg_len, + cohc_dev_addr(cohc), + ctrl_chained, + ctrl, + ctrl_last, + direction, COH901318_CX_CTRL_TC_IRQ_ENABLE); + if (ret) + goto err_lli_fill; COH_DBG(coh901318_list_print(cohc, data)); @@ -1030,6 +1017,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, spin_unlock_irqrestore(&cohc->lock, flg); return &cohd->desc; + err_lli_fill: err_dma_alloc: err_direction: spin_unlock_irqrestore(&cohc->lock, flg); @@ -1121,7 +1109,6 @@ coh901318_terminate_all(struct dma_chan *chan) cohc->nbr_active_done = 0; cohc->busy = 0; - cohc->pending_irqs = 0; spin_unlock_irqrestore(&cohc->lock, flags); } @@ -1148,7 +1135,6 @@ void coh901318_base_init(struct dma_device *dma, const int *pick_chans, spin_lock_init(&cohc->lock); - cohc->pending_irqs = 0; cohc->nbr_active_done = 0; cohc->busy = 0; INIT_LIST_HEAD(&cohc->free); diff --git a/drivers/dma/coh901318_lli.c b/drivers/dma/coh901318_lli.c index f5120f238a4d..5f9af1956eab 100644 --- a/drivers/dma/coh901318_lli.c +++ b/drivers/dma/coh901318_lli.c @@ -166,8 +166,7 @@ coh901318_lli_fill_memcpy(struct coh901318_pool *pool, lli->src_addr = src; lli->dst_addr = dst; - /* One irq per single transfer */ - return 1; + return 0; } int @@ -223,8 +222,7 @@ coh901318_lli_fill_single(struct coh901318_pool *pool, lli->src_addr = src; lli->dst_addr = dst; - /* One irq per single transfer */ - return 1; + return 0; } int @@ -240,7 +238,6 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool, u32 ctrl_sg; dma_addr_t src = 0; dma_addr_t dst = 0; - int nbr_of_irq = 0; u32 bytes_to_transfer; u32 elem_size; @@ -269,9 +266,6 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool, ctrl_sg = ctrl ? ctrl : ctrl_last; - if ((ctrl_sg & ctrl_irq_mask)) - nbr_of_irq++; - if (dir == DMA_TO_DEVICE) /* increment source address */ src = sg_dma_address(sg); @@ -310,8 +304,7 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool, } spin_unlock(&pool->lock); - /* There can be many IRQs per sg transfer */ - return nbr_of_irq; + return 0; err: spin_unlock(&pool->lock); return -EINVAL; -- cgit v1.2.3 From 516fd4305e5f5718475e81fe5c17c95888a8157b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 2 Mar 2010 20:12:46 +0100 Subject: DMAENGINE: COH 901 318 configure channel direction This makes the COH 901 318 configure channel direction (to or from device) dynamically, instead of being passed in from the platform data. This was necessary in order to get the MMC/SD-card channel bidirectional (all other channels on the U300 were either RX or TX but this one was both). This also sets memcpy() alignent to even 2^2 (32bit) boundaries, which makes the memcpy() stress tests start working. Signed-off-by: Linus Walleij Signed-off-by: Dan Williams --- drivers/dma/coh901318.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers') diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c index 544c46278f84..1656fdcdb6c2 100644 --- a/drivers/dma/coh901318.c +++ b/drivers/dma/coh901318.c @@ -928,6 +928,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, struct coh901318_chan *cohc = to_coh901318_chan(chan); struct coh901318_lli *data; struct coh901318_desc *cohd; + const struct coh901318_params *params; struct scatterlist *sg; int len = 0; int size; @@ -935,6 +936,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained; u32 ctrl = cohc_chan_param(cohc)->ctrl_lli; u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last; + u32 config; unsigned long flg; int ret; @@ -952,10 +954,14 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, /* Trigger interrupt after last lli */ ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE; + params = cohc_chan_param(cohc); + config = params->config; + if (direction == DMA_TO_DEVICE) { u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE; + config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY; ctrl_chained |= tx_flags; ctrl_last |= tx_flags; ctrl |= tx_flags; @@ -963,12 +969,15 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE; + config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY; ctrl_chained |= rx_flags; ctrl_last |= rx_flags; ctrl |= rx_flags; } else goto err_direction; + coh901318_set_conf(cohc, config); + /* The dma only supports transmitting packages up to * MAX_DMA_PACKET_SIZE. Calculate to total number of * dma elemts required to send the entire sg list @@ -1250,6 +1259,11 @@ static int __init coh901318_probe(struct platform_device *pdev) base->dma_memcpy.device_issue_pending = coh901318_issue_pending; base->dma_memcpy.device_terminate_all = coh901318_terminate_all; base->dma_memcpy.dev = &pdev->dev; + /* + * This controller can only access address at even 32bit boundaries, + * i.e. 2^2 + */ + base->dma_memcpy.copy_align = 2; err = dma_async_device_register(&base->dma_memcpy); if (err) -- cgit v1.2.3 From 56a5d3cf21c71963c8fc506e9b9d3f71641d9c71 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 2 Mar 2010 20:12:56 +0100 Subject: DMAENGINE: COH 901 318 lli sg offset fix This makes the COH 901 318 respect the scatter offset field by using the sg_phys() rather than the sg_dma_address() so we get a pointer to the actual data we want to send rather than the beginning of the buffer. Also initialize the lli:s a bit more thoroughly. Signed-off-by: Linus Walleij Signed-off-by: Dan Williams --- drivers/dma/coh901318_lli.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/coh901318_lli.c b/drivers/dma/coh901318_lli.c index 5f9af1956eab..71d58c1a1e86 100644 --- a/drivers/dma/coh901318_lli.c +++ b/drivers/dma/coh901318_lli.c @@ -74,6 +74,8 @@ coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len) lli = head; lli->phy_this = phy; + lli->link_addr = 0x00000000; + lli->virt_link_addr = 0x00000000U; for (i = 1; i < len; i++) { lli_prev = lli; @@ -85,13 +87,13 @@ coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len) DEBUGFS_POOL_COUNTER_ADD(pool, 1); lli->phy_this = phy; + lli->link_addr = 0x00000000; + lli->virt_link_addr = 0x00000000U; lli_prev->link_addr = phy; lli_prev->virt_link_addr = lli; } - lli->link_addr = 0x00000000U; - spin_unlock(&pool->lock); return head; @@ -268,10 +270,10 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool, if (dir == DMA_TO_DEVICE) /* increment source address */ - src = sg_dma_address(sg); + src = sg_phys(sg); else /* increment destination address */ - dst = sg_dma_address(sg); + dst = sg_phys(sg); bytes_to_transfer = sg_dma_len(sg); -- cgit v1.2.3 From f3d4ae431d819200bb61e943cb23572b10744e93 Mon Sep 17 00:00:00 2001 From: Michal Pecio Date: Tue, 2 Feb 2010 14:39:47 -0800 Subject: yenta_socket: ENE CB712 CardBus bridge needs special treatment with Echo Audio Indigo soundcards Indigos are well known for distortions when running on some buggy ENE controllers. There is a workaround in the yenta driver, but for some reason it isn't activated on CB712. However, I own a laptop with such chip and it seems that it also is affected - I can clearly hear occasional cracks, especially under heavy network load, and in Windows XP the card is completely unusable. This simple change fixed things for me. Addresses http://bugzilla.kernel.org/show_bug.cgi?id=15191 [linux@dominikbrodowski.net: extend it to the other ENE bridges] Signed-off-by: Michal Pecio Signed-off-by: Andrew Morton Signed-off-by: Dominik Brodowski --- drivers/pcmcia/yenta_socket.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/pcmcia/yenta_socket.c b/drivers/pcmcia/yenta_socket.c index b85375f87622..967c766f53ba 100644 --- a/drivers/pcmcia/yenta_socket.c +++ b/drivers/pcmcia/yenta_socket.c @@ -1408,10 +1408,10 @@ static struct pci_device_id yenta_table[] = { CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_7510, TI12XX), CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_7610, TI12XX), - CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_710, TI12XX), - CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_712, TI12XX), - CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_720, TI12XX), - CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_722, TI12XX), + CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_710, ENE), + CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_712, ENE), + CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_720, ENE), + CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_722, ENE), CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_1211, ENE), CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_1225, ENE), CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_1410, ENE), -- cgit v1.2.3 From f9097dce5d799462e086adca28815dac5006bb30 Mon Sep 17 00:00:00 2001 From: Komuro Date: Sun, 28 Feb 2010 15:39:33 +0900 Subject: pcmcia: remove irq_list parameter from pd6729 Remoe the irq_list parameter from pd6729, as it can and should be set via sysfs (and -- if available -- pcmciautils, which reads the information from /etc/pcmcia/config.opts ) [linux@dominikbrodowski.net: updated commit message] Signed-off-by: Komuro Signed-off-by: Dominik Brodowski --- drivers/pcmcia/pd6729.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/pcmcia/pd6729.c b/drivers/pcmcia/pd6729.c index e1741cd875aa..7c204910a777 100644 --- a/drivers/pcmcia/pd6729.c +++ b/drivers/pcmcia/pd6729.c @@ -48,23 +48,13 @@ MODULE_AUTHOR("Jun Komuro "); * Specifies the interrupt delivery mode. The default (1) is to use PCI * interrupts; a value of 0 selects ISA interrupts. This must be set for * correct operation of PCI card readers. - * - * irq_list=i,j,... - * This list limits the set of interrupts that can be used by PCMCIA - * cards. - * The default list is 3,4,5,7,9,10,11. - * (irq_list parameter is not used, if irq_mode = 1) */ static int irq_mode = 1; /* 0 = ISA interrupt, 1 = PCI interrupt */ -static int irq_list[16]; -static unsigned int irq_list_count = 0; module_param(irq_mode, int, 0444); -module_param_array(irq_list, int, &irq_list_count, 0444); MODULE_PARM_DESC(irq_mode, "interrupt delivery mode. 0 = ISA, 1 = PCI. default is 1"); -MODULE_PARM_DESC(irq_list, "interrupts that can be used by PCMCIA cards"); static DEFINE_SPINLOCK(port_lock); @@ -605,13 +595,7 @@ static u_int __devinit pd6729_isa_scan(void) return 0; } - if (irq_list_count == 0) - mask0 = 0xffff; - else - for (i = mask0 = 0; i < irq_list_count; i++) - mask0 |= (1< Date: Mon, 1 Mar 2010 21:40:56 +0100 Subject: pcmcia: alchemy: fixup wrong comments Commit 11b897cf84c37e6522db914793677e933ef311fb changed expected pcmcia area addresses from the 32bit pseudo to the real 36bit addresses, but did not update the comments. Signed-off-by: Manuel Lauss Signed-off-by: Dominik Brodowski --- drivers/pcmcia/db1xxx_ss.c | 19 ++++--------------- drivers/pcmcia/xxs1500_ss.c | 16 +++------------- 2 files changed, 7 insertions(+), 28 deletions(-) (limited to 'drivers') diff --git a/drivers/pcmcia/db1xxx_ss.c b/drivers/pcmcia/db1xxx_ss.c index 3889cf07d6ce..9254ab0b29b1 100644 --- a/drivers/pcmcia/db1xxx_ss.c +++ b/drivers/pcmcia/db1xxx_ss.c @@ -42,7 +42,6 @@ struct db1x_pcmcia_sock { int nr; /* socket number */ void *virt_io; - /* the "pseudo" addresses of the PCMCIA space. */ phys_addr_t phys_io; phys_addr_t phys_attr; phys_addr_t phys_mem; @@ -437,7 +436,7 @@ static int __devinit db1x_pcmcia_socket_probe(struct platform_device *pdev) * This includes IRQs for Carddetection/ejection, the card * itself and optional status change detection. * Also, the memory areas covered by a socket. For these - * we require the 32bit "pseudo" addresses (see the au1000.h + * we require the real 36bit addresses (see the au1000.h * header for more information). */ @@ -459,11 +458,7 @@ static int __devinit db1x_pcmcia_socket_probe(struct platform_device *pdev) ret = -ENODEV; - /* - * pseudo-attr: The 32bit address of the PCMCIA attribute space - * for this socket (usually the 36bit address shifted 4 to the - * right). - */ + /* 36bit PCMCIA Attribute area address */ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcmcia-attr"); if (!r) { printk(KERN_ERR "pcmcia%d has no 'pseudo-attr' resource!\n", @@ -472,10 +467,7 @@ static int __devinit db1x_pcmcia_socket_probe(struct platform_device *pdev) } sock->phys_attr = r->start; - /* - * pseudo-mem: The 32bit address of the PCMCIA memory space for - * this socket (usually the 36bit address shifted 4 to the right) - */ + /* 36bit PCMCIA Memory area address */ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcmcia-mem"); if (!r) { printk(KERN_ERR "pcmcia%d has no 'pseudo-mem' resource!\n", @@ -484,10 +476,7 @@ static int __devinit db1x_pcmcia_socket_probe(struct platform_device *pdev) } sock->phys_mem = r->start; - /* - * pseudo-io: The 32bit address of the PCMCIA IO space for this - * socket (usually the 36bit address shifted 4 to the right). - */ + /* 36bit PCMCIA IO area address */ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcmcia-io"); if (!r) { printk(KERN_ERR "pcmcia%d has no 'pseudo-io' resource!\n", diff --git a/drivers/pcmcia/xxs1500_ss.c b/drivers/pcmcia/xxs1500_ss.c index 61560cd6e287..f9009d34254b 100644 --- a/drivers/pcmcia/xxs1500_ss.c +++ b/drivers/pcmcia/xxs1500_ss.c @@ -218,11 +218,7 @@ static int __devinit xxs1500_pcmcia_probe(struct platform_device *pdev) ret = -ENODEV; - /* - * pseudo-attr: The 32bit address of the PCMCIA attribute space - * for this socket (usually the 36bit address shifted 4 to the - * right). - */ + /* 36bit PCMCIA Attribute area address */ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcmcia-attr"); if (!r) { dev_err(&pdev->dev, "missing 'pcmcia-attr' resource!\n"); @@ -230,10 +226,7 @@ static int __devinit xxs1500_pcmcia_probe(struct platform_device *pdev) } sock->phys_attr = r->start; - /* - * pseudo-mem: The 32bit address of the PCMCIA memory space for - * this socket (usually the 36bit address shifted 4 to the right) - */ + /* 36bit PCMCIA Memory area address */ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcmcia-mem"); if (!r) { dev_err(&pdev->dev, "missing 'pcmcia-mem' resource!\n"); @@ -241,10 +234,7 @@ static int __devinit xxs1500_pcmcia_probe(struct platform_device *pdev) } sock->phys_mem = r->start; - /* - * pseudo-io: The 32bit address of the PCMCIA IO space for this - * socket (usually the 36bit address shifted 4 to the right). - */ + /* 36bit PCMCIA IO area address */ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcmcia-io"); if (!r) { dev_err(&pdev->dev, "missing 'pcmcia-io' resource!\n"); -- cgit v1.2.3 From 2f41a7f11c4bb93c41715008a693cadaee5efd82 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 3 Mar 2010 09:20:25 +1000 Subject: drm/nouveau: fix *staging* driver build with switcheroo off. This driver is in *staging*. Fix the build with the switcheroo off. Signed-off-by: Dave Airlie --- drivers/gpu/drm/nouveau/nouveau_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index f5b3cbe7dc80..5f8d987af363 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -852,7 +852,7 @@ extern int nouveau_dma_init(struct nouveau_channel *); extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); /* nouveau_acpi.c */ -#if defined(CONFIG_VGA_SWITCHEROO) +#if defined(CONFIG_ACPI) void nouveau_register_dsm_handler(void); void nouveau_unregister_dsm_handler(void); #else -- cgit v1.2.3 From d424b925f7092b9d95e0a8556872349abe79d9b6 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 3 Mar 2010 09:26:35 +1000 Subject: vga_switcheroo: disable default y by new rules. Another undocumented rule of kernel folklore, no default y config options anymore, apparantly hinting to distros they might want something isn't preferred anymore. Signed-off-by: Dave Airlie --- drivers/gpu/vga/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/vga/Kconfig b/drivers/gpu/vga/Kconfig index 6116a0196214..34b08a6b0cbe 100644 --- a/drivers/gpu/vga/Kconfig +++ b/drivers/gpu/vga/Kconfig @@ -11,7 +11,6 @@ config VGA_ARB config VGA_SWITCHEROO bool "Laptop Hybrid Grapics - GPU switching support" - default y depends on X86 depends on ACPI help -- cgit v1.2.3 From 6e83ee075ed74941ccaad4fec503f6b24646e7e0 Mon Sep 17 00:00:00 2001 From: Dominik Brodowski Date: Tue, 2 Mar 2010 08:57:33 +0100 Subject: pcmcia: CodingStyle fixes Fix most of the remaining CodingStyle issues in drivers/pcmcia , which related to wrong indent -- PCMCIA historically used 4 spaces. Also, remove a custom min() implementation with the generic one. Signed-off-by: Dominik Brodowski --- drivers/pcmcia/cardbus.c | 2 +- drivers/pcmcia/cistpl.c | 1908 ++++++++++++++++++++++----------------------- drivers/pcmcia/rsrc_mgr.c | 3 +- 3 files changed, 942 insertions(+), 971 deletions(-) (limited to 'drivers') diff --git a/drivers/pcmcia/cardbus.c b/drivers/pcmcia/cardbus.c index ac0686efbf75..e6ab2a47d8cb 100644 --- a/drivers/pcmcia/cardbus.c +++ b/drivers/pcmcia/cardbus.c @@ -71,7 +71,7 @@ int __ref cb_alloc(struct pcmcia_socket *s) unsigned int max, pass; s->functions = pci_scan_slot(bus, PCI_DEVFN(0, 0)); - pci_fixup_cardbus(bus); + pci_fixup_cardbus(bus); max = bus->secondary; for (pass = 0; pass < 2; pass++) diff --git a/drivers/pcmcia/cistpl.c b/drivers/pcmcia/cistpl.c index 2f3622dd4b69..f230f6543bff 100644 --- a/drivers/pcmcia/cistpl.c +++ b/drivers/pcmcia/cistpl.c @@ -54,46 +54,44 @@ static const u_int exponent[] = { /* Upper limit on reasonable # of tuples */ #define MAX_TUPLES 200 -/*====================================================================*/ - -/* Parameters that can be set with 'insmod' */ - /* 16-bit CIS? */ static int cis_width; module_param(cis_width, int, 0444); void release_cis_mem(struct pcmcia_socket *s) { - mutex_lock(&s->ops_mutex); - if (s->cis_mem.flags & MAP_ACTIVE) { - s->cis_mem.flags &= ~MAP_ACTIVE; - s->ops->set_mem_map(s, &s->cis_mem); - if (s->cis_mem.res) { - release_resource(s->cis_mem.res); - kfree(s->cis_mem.res); - s->cis_mem.res = NULL; + mutex_lock(&s->ops_mutex); + if (s->cis_mem.flags & MAP_ACTIVE) { + s->cis_mem.flags &= ~MAP_ACTIVE; + s->ops->set_mem_map(s, &s->cis_mem); + if (s->cis_mem.res) { + release_resource(s->cis_mem.res); + kfree(s->cis_mem.res); + s->cis_mem.res = NULL; + } + iounmap(s->cis_virt); + s->cis_virt = NULL; } - iounmap(s->cis_virt); - s->cis_virt = NULL; - } - mutex_unlock(&s->ops_mutex); + mutex_unlock(&s->ops_mutex); } -/* - * Map the card memory at "card_offset" into virtual space. +/** + * set_cis_map() - map the card memory at "card_offset" into virtual space. + * * If flags & MAP_ATTRIB, map the attribute space, otherwise * map the memory space. * * Must be called with ops_mutex held. */ -static void __iomem * -set_cis_map(struct pcmcia_socket *s, unsigned int card_offset, unsigned int flags) +static void __iomem *set_cis_map(struct pcmcia_socket *s, + unsigned int card_offset, unsigned int flags) { pccard_mem_map *mem = &s->cis_mem; int ret; if (!(s->features & SS_CAP_STATIC_MAP) && (mem->res == NULL)) { - mem->res = pcmcia_find_mem_region(0, s->map_size, s->map_size, 0, s); + mem->res = pcmcia_find_mem_region(0, s->map_size, + s->map_size, 0, s); if (mem->res == NULL) { dev_printk(KERN_NOTICE, &s->dev, "cs: unable to map card memory!\n"); @@ -124,165 +122,170 @@ set_cis_map(struct pcmcia_socket *s, unsigned int card_offset, unsigned int flag return s->cis_virt; } -/*====================================================================== - - Low-level functions to read and write CIS memory. I think the - write routine is only useful for writing one-byte registers. - -======================================================================*/ /* Bits in attr field */ #define IS_ATTR 1 #define IS_INDIRECT 8 +/** + * pcmcia_read_cis_mem() - low-level function to read CIS memory + */ int pcmcia_read_cis_mem(struct pcmcia_socket *s, int attr, u_int addr, u_int len, void *ptr) { - void __iomem *sys, *end; - unsigned char *buf = ptr; - - dev_dbg(&s->dev, "pcmcia_read_cis_mem(%d, %#x, %u)\n", attr, addr, len); - - mutex_lock(&s->ops_mutex); - if (attr & IS_INDIRECT) { - /* Indirect accesses use a bunch of special registers at fixed - locations in common memory */ - u_char flags = ICTRL0_COMMON|ICTRL0_AUTOINC|ICTRL0_BYTEGRAN; - if (attr & IS_ATTR) { - addr *= 2; - flags = ICTRL0_AUTOINC; - } + void __iomem *sys, *end; + unsigned char *buf = ptr; - sys = set_cis_map(s, 0, MAP_ACTIVE | ((cis_width) ? MAP_16BIT : 0)); - if (!sys) { - dev_dbg(&s->dev, "could not map memory\n"); - memset(ptr, 0xff, len); - mutex_unlock(&s->ops_mutex); - return -1; - } + dev_dbg(&s->dev, "pcmcia_read_cis_mem(%d, %#x, %u)\n", attr, addr, len); - writeb(flags, sys+CISREG_ICTRL0); - writeb(addr & 0xff, sys+CISREG_IADDR0); - writeb((addr>>8) & 0xff, sys+CISREG_IADDR1); - writeb((addr>>16) & 0xff, sys+CISREG_IADDR2); - writeb((addr>>24) & 0xff, sys+CISREG_IADDR3); - for ( ; len > 0; len--, buf++) - *buf = readb(sys+CISREG_IDATA0); - } else { - u_int inc = 1, card_offset, flags; - - if (addr > CISTPL_MAX_CIS_SIZE) - dev_dbg(&s->dev, "attempt to read CIS mem at addr %#x", addr); - - flags = MAP_ACTIVE | ((cis_width) ? MAP_16BIT : 0); - if (attr) { - flags |= MAP_ATTRIB; - inc++; - addr *= 2; - } + mutex_lock(&s->ops_mutex); + if (attr & IS_INDIRECT) { + /* Indirect accesses use a bunch of special registers at fixed + locations in common memory */ + u_char flags = ICTRL0_COMMON|ICTRL0_AUTOINC|ICTRL0_BYTEGRAN; + if (attr & IS_ATTR) { + addr *= 2; + flags = ICTRL0_AUTOINC; + } - card_offset = addr & ~(s->map_size-1); - while (len) { - sys = set_cis_map(s, card_offset, flags); - if (!sys) { - dev_dbg(&s->dev, "could not map memory\n"); - memset(ptr, 0xff, len); - mutex_unlock(&s->ops_mutex); - return -1; - } - end = sys + s->map_size; - sys = sys + (addr & (s->map_size-1)); - for ( ; len > 0; len--, buf++, sys += inc) { - if (sys == end) - break; - *buf = readb(sys); - } - card_offset += s->map_size; - addr = 0; + sys = set_cis_map(s, 0, MAP_ACTIVE | + ((cis_width) ? MAP_16BIT : 0)); + if (!sys) { + dev_dbg(&s->dev, "could not map memory\n"); + memset(ptr, 0xff, len); + mutex_unlock(&s->ops_mutex); + return -1; + } + + writeb(flags, sys+CISREG_ICTRL0); + writeb(addr & 0xff, sys+CISREG_IADDR0); + writeb((addr>>8) & 0xff, sys+CISREG_IADDR1); + writeb((addr>>16) & 0xff, sys+CISREG_IADDR2); + writeb((addr>>24) & 0xff, sys+CISREG_IADDR3); + for ( ; len > 0; len--, buf++) + *buf = readb(sys+CISREG_IDATA0); + } else { + u_int inc = 1, card_offset, flags; + + if (addr > CISTPL_MAX_CIS_SIZE) + dev_dbg(&s->dev, + "attempt to read CIS mem at addr %#x", addr); + + flags = MAP_ACTIVE | ((cis_width) ? MAP_16BIT : 0); + if (attr) { + flags |= MAP_ATTRIB; + inc++; + addr *= 2; + } + + card_offset = addr & ~(s->map_size-1); + while (len) { + sys = set_cis_map(s, card_offset, flags); + if (!sys) { + dev_dbg(&s->dev, "could not map memory\n"); + memset(ptr, 0xff, len); + mutex_unlock(&s->ops_mutex); + return -1; + } + end = sys + s->map_size; + sys = sys + (addr & (s->map_size-1)); + for ( ; len > 0; len--, buf++, sys += inc) { + if (sys == end) + break; + *buf = readb(sys); + } + card_offset += s->map_size; + addr = 0; + } } - } - mutex_unlock(&s->ops_mutex); - dev_dbg(&s->dev, " %#2.2x %#2.2x %#2.2x %#2.2x ...\n", - *(u_char *)(ptr+0), *(u_char *)(ptr+1), - *(u_char *)(ptr+2), *(u_char *)(ptr+3)); - return 0; + mutex_unlock(&s->ops_mutex); + dev_dbg(&s->dev, " %#2.2x %#2.2x %#2.2x %#2.2x ...\n", + *(u_char *)(ptr+0), *(u_char *)(ptr+1), + *(u_char *)(ptr+2), *(u_char *)(ptr+3)); + return 0; } +/** + * pcmcia_write_cis_mem() - low-level function to write CIS memory + * + * Probably only useful for writing one-byte registers. + */ void pcmcia_write_cis_mem(struct pcmcia_socket *s, int attr, u_int addr, u_int len, void *ptr) { - void __iomem *sys, *end; - unsigned char *buf = ptr; - - dev_dbg(&s->dev, "pcmcia_write_cis_mem(%d, %#x, %u)\n", attr, addr, len); - - mutex_lock(&s->ops_mutex); - if (attr & IS_INDIRECT) { - /* Indirect accesses use a bunch of special registers at fixed - locations in common memory */ - u_char flags = ICTRL0_COMMON|ICTRL0_AUTOINC|ICTRL0_BYTEGRAN; - if (attr & IS_ATTR) { - addr *= 2; - flags = ICTRL0_AUTOINC; - } + void __iomem *sys, *end; + unsigned char *buf = ptr; - sys = set_cis_map(s, 0, MAP_ACTIVE | ((cis_width) ? MAP_16BIT : 0)); - if (!sys) { - dev_dbg(&s->dev, "could not map memory\n"); - mutex_unlock(&s->ops_mutex); - return; /* FIXME: Error */ - } + dev_dbg(&s->dev, + "pcmcia_write_cis_mem(%d, %#x, %u)\n", attr, addr, len); - writeb(flags, sys+CISREG_ICTRL0); - writeb(addr & 0xff, sys+CISREG_IADDR0); - writeb((addr>>8) & 0xff, sys+CISREG_IADDR1); - writeb((addr>>16) & 0xff, sys+CISREG_IADDR2); - writeb((addr>>24) & 0xff, sys+CISREG_IADDR3); - for ( ; len > 0; len--, buf++) - writeb(*buf, sys+CISREG_IDATA0); - } else { - u_int inc = 1, card_offset, flags; - - flags = MAP_ACTIVE | ((cis_width) ? MAP_16BIT : 0); - if (attr & IS_ATTR) { - flags |= MAP_ATTRIB; - inc++; - addr *= 2; - } + mutex_lock(&s->ops_mutex); + if (attr & IS_INDIRECT) { + /* Indirect accesses use a bunch of special registers at fixed + locations in common memory */ + u_char flags = ICTRL0_COMMON|ICTRL0_AUTOINC|ICTRL0_BYTEGRAN; + if (attr & IS_ATTR) { + addr *= 2; + flags = ICTRL0_AUTOINC; + } - card_offset = addr & ~(s->map_size-1); - while (len) { - sys = set_cis_map(s, card_offset, flags); - if (!sys) { - dev_dbg(&s->dev, "could not map memory\n"); - mutex_unlock(&s->ops_mutex); - return; /* FIXME: error */ - } - - end = sys + s->map_size; - sys = sys + (addr & (s->map_size-1)); - for ( ; len > 0; len--, buf++, sys += inc) { - if (sys == end) - break; - writeb(*buf, sys); - } - card_offset += s->map_size; - addr = 0; - } - } - mutex_unlock(&s->ops_mutex); -} + sys = set_cis_map(s, 0, MAP_ACTIVE | + ((cis_width) ? MAP_16BIT : 0)); + if (!sys) { + dev_dbg(&s->dev, "could not map memory\n"); + mutex_unlock(&s->ops_mutex); + return; /* FIXME: Error */ + } + + writeb(flags, sys+CISREG_ICTRL0); + writeb(addr & 0xff, sys+CISREG_IADDR0); + writeb((addr>>8) & 0xff, sys+CISREG_IADDR1); + writeb((addr>>16) & 0xff, sys+CISREG_IADDR2); + writeb((addr>>24) & 0xff, sys+CISREG_IADDR3); + for ( ; len > 0; len--, buf++) + writeb(*buf, sys+CISREG_IDATA0); + } else { + u_int inc = 1, card_offset, flags; + flags = MAP_ACTIVE | ((cis_width) ? MAP_16BIT : 0); + if (attr & IS_ATTR) { + flags |= MAP_ATTRIB; + inc++; + addr *= 2; + } -/*====================================================================== + card_offset = addr & ~(s->map_size-1); + while (len) { + sys = set_cis_map(s, card_offset, flags); + if (!sys) { + dev_dbg(&s->dev, "could not map memory\n"); + mutex_unlock(&s->ops_mutex); + return; /* FIXME: error */ + } - This is a wrapper around read_cis_mem, with the same interface, - but which caches information, for cards whose CIS may not be - readable all the time. + end = sys + s->map_size; + sys = sys + (addr & (s->map_size-1)); + for ( ; len > 0; len--, buf++, sys += inc) { + if (sys == end) + break; + writeb(*buf, sys); + } + card_offset += s->map_size; + addr = 0; + } + } + mutex_unlock(&s->ops_mutex); +} -======================================================================*/ +/** + * read_cis_cache() - read CIS memory or its associated cache + * + * This is a wrapper around read_cis_mem, with the same interface, + * but which caches information, for cards whose CIS may not be + * readable all the time. + */ static int read_cis_cache(struct pcmcia_socket *s, int attr, u_int addr, size_t len, void *ptr) { @@ -353,7 +356,6 @@ remove_cis_cache(struct pcmcia_socket *s, int attr, u_int addr, u_int len) * This destroys the CIS cache but keeps any fake CIS alive. Must be * called with ops_mutex held. */ - void destroy_cis_cache(struct pcmcia_socket *s) { struct list_head *l, *n; @@ -366,13 +368,9 @@ void destroy_cis_cache(struct pcmcia_socket *s) } } -/*====================================================================== - - This verifies if the CIS of a card matches what is in the CIS - cache. - -======================================================================*/ - +/** + * verify_cis_cache() - does the CIS match what is in the CIS cache? + */ int verify_cis_cache(struct pcmcia_socket *s) { struct cis_cache_entry *cis; @@ -404,13 +402,12 @@ int verify_cis_cache(struct pcmcia_socket *s) return 0; } -/*====================================================================== - - For really bad cards, we provide a facility for uploading a - replacement CIS. - -======================================================================*/ - +/** + * pcmcia_replace_cis() - use a replacement CIS instead of the card's CIS + * + * For really bad cards, we provide a facility for uploading a + * replacement CIS. + */ int pcmcia_replace_cis(struct pcmcia_socket *s, const u8 *data, const size_t len) { @@ -433,17 +430,13 @@ int pcmcia_replace_cis(struct pcmcia_socket *s, return 0; } -/*====================================================================== - - The high-level CIS tuple services - -======================================================================*/ +/* The high-level CIS tuple services */ typedef struct tuple_flags { - u_int link_space:4; - u_int has_link:1; - u_int mfc_fn:3; - u_int space:4; + u_int link_space:4; + u_int has_link:1; + u_int mfc_fn:3; + u_int space:4; } tuple_flags; #define LINK_SPACE(f) (((tuple_flags *)(&(f)))->link_space) @@ -451,982 +444,961 @@ typedef struct tuple_flags { #define MFC_FN(f) (((tuple_flags *)(&(f)))->mfc_fn) #define SPACE(f) (((tuple_flags *)(&(f)))->space) -int pccard_get_first_tuple(struct pcmcia_socket *s, unsigned int function, tuple_t *tuple) +int pccard_get_first_tuple(struct pcmcia_socket *s, unsigned int function, + tuple_t *tuple) { - if (!s) - return -EINVAL; - - if (!(s->state & SOCKET_PRESENT) || (s->state & SOCKET_CARDBUS)) - return -ENODEV; - tuple->TupleLink = tuple->Flags = 0; - - /* Assume presence of a LONGLINK_C to address 0 */ - tuple->CISOffset = tuple->LinkOffset = 0; - SPACE(tuple->Flags) = HAS_LINK(tuple->Flags) = 1; - - if ((s->functions > 1) && !(tuple->Attributes & TUPLE_RETURN_COMMON)) { - cisdata_t req = tuple->DesiredTuple; - tuple->DesiredTuple = CISTPL_LONGLINK_MFC; - if (pccard_get_next_tuple(s, function, tuple) == 0) { - tuple->DesiredTuple = CISTPL_LINKTARGET; - if (pccard_get_next_tuple(s, function, tuple) != 0) - return -ENOSPC; - } else - tuple->CISOffset = tuple->TupleLink = 0; - tuple->DesiredTuple = req; - } - return pccard_get_next_tuple(s, function, tuple); + if (!s) + return -EINVAL; + + if (!(s->state & SOCKET_PRESENT) || (s->state & SOCKET_CARDBUS)) + return -ENODEV; + tuple->TupleLink = tuple->Flags = 0; + + /* Assume presence of a LONGLINK_C to address 0 */ + tuple->CISOffset = tuple->LinkOffset = 0; + SPACE(tuple->Flags) = HAS_LINK(tuple->Flags) = 1; + + if ((s->functions > 1) && !(tuple->Attributes & TUPLE_RETURN_COMMON)) { + cisdata_t req = tuple->DesiredTuple; + tuple->DesiredTuple = CISTPL_LONGLINK_MFC; + if (pccard_get_next_tuple(s, function, tuple) == 0) { + tuple->DesiredTuple = CISTPL_LINKTARGET; + if (pccard_get_next_tuple(s, function, tuple) != 0) + return -ENOSPC; + } else + tuple->CISOffset = tuple->TupleLink = 0; + tuple->DesiredTuple = req; + } + return pccard_get_next_tuple(s, function, tuple); } static int follow_link(struct pcmcia_socket *s, tuple_t *tuple) { - u_char link[5]; - u_int ofs; - int ret; - - if (MFC_FN(tuple->Flags)) { - /* Get indirect link from the MFC tuple */ - ret = read_cis_cache(s, LINK_SPACE(tuple->Flags), - tuple->LinkOffset, 5, link); - if (ret) + u_char link[5]; + u_int ofs; + int ret; + + if (MFC_FN(tuple->Flags)) { + /* Get indirect link from the MFC tuple */ + ret = read_cis_cache(s, LINK_SPACE(tuple->Flags), + tuple->LinkOffset, 5, link); + if (ret) + return -1; + ofs = get_unaligned_le32(link + 1); + SPACE(tuple->Flags) = (link[0] == CISTPL_MFC_ATTR); + /* Move to the next indirect link */ + tuple->LinkOffset += 5; + MFC_FN(tuple->Flags)--; + } else if (HAS_LINK(tuple->Flags)) { + ofs = tuple->LinkOffset; + SPACE(tuple->Flags) = LINK_SPACE(tuple->Flags); + HAS_LINK(tuple->Flags) = 0; + } else return -1; - ofs = get_unaligned_le32(link + 1); - SPACE(tuple->Flags) = (link[0] == CISTPL_MFC_ATTR); - /* Move to the next indirect link */ - tuple->LinkOffset += 5; - MFC_FN(tuple->Flags)--; - } else if (HAS_LINK(tuple->Flags)) { - ofs = tuple->LinkOffset; - SPACE(tuple->Flags) = LINK_SPACE(tuple->Flags); - HAS_LINK(tuple->Flags) = 0; - } else { - return -1; - } - if (SPACE(tuple->Flags)) { - /* This is ugly, but a common CIS error is to code the long - link offset incorrectly, so we check the right spot... */ + + if (SPACE(tuple->Flags)) { + /* This is ugly, but a common CIS error is to code the long + link offset incorrectly, so we check the right spot... */ + ret = read_cis_cache(s, SPACE(tuple->Flags), ofs, 5, link); + if (ret) + return -1; + if ((link[0] == CISTPL_LINKTARGET) && (link[1] >= 3) && + (strncmp(link+2, "CIS", 3) == 0)) + return ofs; + remove_cis_cache(s, SPACE(tuple->Flags), ofs, 5); + /* Then, we try the wrong spot... */ + ofs = ofs >> 1; + } ret = read_cis_cache(s, SPACE(tuple->Flags), ofs, 5, link); if (ret) return -1; if ((link[0] == CISTPL_LINKTARGET) && (link[1] >= 3) && - (strncmp(link+2, "CIS", 3) == 0)) - return ofs; + (strncmp(link+2, "CIS", 3) == 0)) + return ofs; remove_cis_cache(s, SPACE(tuple->Flags), ofs, 5); - /* Then, we try the wrong spot... */ - ofs = ofs >> 1; - } - ret = read_cis_cache(s, SPACE(tuple->Flags), ofs, 5, link); - if (ret) - return -1; - if ((link[0] == CISTPL_LINKTARGET) && (link[1] >= 3) && - (strncmp(link+2, "CIS", 3) == 0)) - return ofs; - remove_cis_cache(s, SPACE(tuple->Flags), ofs, 5); - return -1; + return -1; } -int pccard_get_next_tuple(struct pcmcia_socket *s, unsigned int function, tuple_t *tuple) +int pccard_get_next_tuple(struct pcmcia_socket *s, unsigned int function, + tuple_t *tuple) { - u_char link[2], tmp; - int ofs, i, attr; - int ret; - - if (!s) - return -EINVAL; - if (!(s->state & SOCKET_PRESENT) || (s->state & SOCKET_CARDBUS)) - return -ENODEV; - - link[1] = tuple->TupleLink; - ofs = tuple->CISOffset + tuple->TupleLink; - attr = SPACE(tuple->Flags); - - for (i = 0; i < MAX_TUPLES; i++) { - if (link[1] == 0xff) { - link[0] = CISTPL_END; - } else { - ret = read_cis_cache(s, attr, ofs, 2, link); - if (ret) - return -1; - if (link[0] == CISTPL_NULL) { - ofs++; continue; - } - } + u_char link[2], tmp; + int ofs, i, attr; + int ret; - /* End of chain? Follow long link if possible */ - if (link[0] == CISTPL_END) { - ofs = follow_link(s, tuple); - if (ofs < 0) - return -ENOSPC; - attr = SPACE(tuple->Flags); - ret = read_cis_cache(s, attr, ofs, 2, link); - if (ret) - return -1; - } + if (!s) + return -EINVAL; + if (!(s->state & SOCKET_PRESENT) || (s->state & SOCKET_CARDBUS)) + return -ENODEV; - /* Is this a link tuple? Make a note of it */ - if ((link[0] == CISTPL_LONGLINK_A) || - (link[0] == CISTPL_LONGLINK_C) || - (link[0] == CISTPL_LONGLINK_MFC) || - (link[0] == CISTPL_LINKTARGET) || - (link[0] == CISTPL_INDIRECT) || - (link[0] == CISTPL_NO_LINK)) { - switch (link[0]) { - case CISTPL_LONGLINK_A: - HAS_LINK(tuple->Flags) = 1; - LINK_SPACE(tuple->Flags) = attr | IS_ATTR; - ret = read_cis_cache(s, attr, ofs+2, 4, &tuple->LinkOffset); - if (ret) - return -1; - break; - case CISTPL_LONGLINK_C: - HAS_LINK(tuple->Flags) = 1; - LINK_SPACE(tuple->Flags) = attr & ~IS_ATTR; - ret = read_cis_cache(s, attr, ofs+2, 4, &tuple->LinkOffset); - if (ret) - return -1; - break; - case CISTPL_INDIRECT: - HAS_LINK(tuple->Flags) = 1; - LINK_SPACE(tuple->Flags) = IS_ATTR | IS_INDIRECT; - tuple->LinkOffset = 0; - break; - case CISTPL_LONGLINK_MFC: - tuple->LinkOffset = ofs + 3; - LINK_SPACE(tuple->Flags) = attr; - if (function == BIND_FN_ALL) { - /* Follow all the MFC links */ - ret = read_cis_cache(s, attr, ofs+2, 1, &tmp); - if (ret) - return -1; - MFC_FN(tuple->Flags) = tmp; - } else { - /* Follow exactly one of the links */ - MFC_FN(tuple->Flags) = 1; - tuple->LinkOffset += function * 5; + link[1] = tuple->TupleLink; + ofs = tuple->CISOffset + tuple->TupleLink; + attr = SPACE(tuple->Flags); + + for (i = 0; i < MAX_TUPLES; i++) { + if (link[1] == 0xff) + link[0] = CISTPL_END; + else { + ret = read_cis_cache(s, attr, ofs, 2, link); + if (ret) + return -1; + if (link[0] == CISTPL_NULL) { + ofs++; + continue; + } } - break; - case CISTPL_NO_LINK: - HAS_LINK(tuple->Flags) = 0; - break; - } - if ((tuple->Attributes & TUPLE_RETURN_LINK) && - (tuple->DesiredTuple == RETURN_FIRST_TUPLE)) - break; - } else - if (tuple->DesiredTuple == RETURN_FIRST_TUPLE) - break; - if (link[0] == tuple->DesiredTuple) - break; - ofs += link[1] + 2; - } - if (i == MAX_TUPLES) { - dev_dbg(&s->dev, "cs: overrun in pcmcia_get_next_tuple\n"); - return -ENOSPC; - } - - tuple->TupleCode = link[0]; - tuple->TupleLink = link[1]; - tuple->CISOffset = ofs + 2; - return 0; -} + /* End of chain? Follow long link if possible */ + if (link[0] == CISTPL_END) { + ofs = follow_link(s, tuple); + if (ofs < 0) + return -ENOSPC; + attr = SPACE(tuple->Flags); + ret = read_cis_cache(s, attr, ofs, 2, link); + if (ret) + return -1; + } -/*====================================================================*/ + /* Is this a link tuple? Make a note of it */ + if ((link[0] == CISTPL_LONGLINK_A) || + (link[0] == CISTPL_LONGLINK_C) || + (link[0] == CISTPL_LONGLINK_MFC) || + (link[0] == CISTPL_LINKTARGET) || + (link[0] == CISTPL_INDIRECT) || + (link[0] == CISTPL_NO_LINK)) { + switch (link[0]) { + case CISTPL_LONGLINK_A: + HAS_LINK(tuple->Flags) = 1; + LINK_SPACE(tuple->Flags) = attr | IS_ATTR; + ret = read_cis_cache(s, attr, ofs+2, 4, + &tuple->LinkOffset); + if (ret) + return -1; + break; + case CISTPL_LONGLINK_C: + HAS_LINK(tuple->Flags) = 1; + LINK_SPACE(tuple->Flags) = attr & ~IS_ATTR; + ret = read_cis_cache(s, attr, ofs+2, 4, + &tuple->LinkOffset); + if (ret) + return -1; + break; + case CISTPL_INDIRECT: + HAS_LINK(tuple->Flags) = 1; + LINK_SPACE(tuple->Flags) = IS_ATTR | + IS_INDIRECT; + tuple->LinkOffset = 0; + break; + case CISTPL_LONGLINK_MFC: + tuple->LinkOffset = ofs + 3; + LINK_SPACE(tuple->Flags) = attr; + if (function == BIND_FN_ALL) { + /* Follow all the MFC links */ + ret = read_cis_cache(s, attr, ofs+2, + 1, &tmp); + if (ret) + return -1; + MFC_FN(tuple->Flags) = tmp; + } else { + /* Follow exactly one of the links */ + MFC_FN(tuple->Flags) = 1; + tuple->LinkOffset += function * 5; + } + break; + case CISTPL_NO_LINK: + HAS_LINK(tuple->Flags) = 0; + break; + } + if ((tuple->Attributes & TUPLE_RETURN_LINK) && + (tuple->DesiredTuple == RETURN_FIRST_TUPLE)) + break; + } else + if (tuple->DesiredTuple == RETURN_FIRST_TUPLE) + break; + + if (link[0] == tuple->DesiredTuple) + break; + ofs += link[1] + 2; + } + if (i == MAX_TUPLES) { + dev_dbg(&s->dev, "cs: overrun in pcmcia_get_next_tuple\n"); + return -ENOSPC; + } -#define _MIN(a, b) (((a) < (b)) ? (a) : (b)) + tuple->TupleCode = link[0]; + tuple->TupleLink = link[1]; + tuple->CISOffset = ofs + 2; + return 0; +} int pccard_get_tuple_data(struct pcmcia_socket *s, tuple_t *tuple) { - u_int len; - int ret; + u_int len; + int ret; - if (!s) - return -EINVAL; + if (!s) + return -EINVAL; - if (tuple->TupleLink < tuple->TupleOffset) - return -ENOSPC; - len = tuple->TupleLink - tuple->TupleOffset; - tuple->TupleDataLen = tuple->TupleLink; - if (len == 0) + if (tuple->TupleLink < tuple->TupleOffset) + return -ENOSPC; + len = tuple->TupleLink - tuple->TupleOffset; + tuple->TupleDataLen = tuple->TupleLink; + if (len == 0) + return 0; + ret = read_cis_cache(s, SPACE(tuple->Flags), + tuple->CISOffset + tuple->TupleOffset, + min(len, (u_int) tuple->TupleDataMax), + tuple->TupleData); + if (ret) + return -1; return 0; - ret = read_cis_cache(s, SPACE(tuple->Flags), - tuple->CISOffset + tuple->TupleOffset, - _MIN(len, tuple->TupleDataMax), tuple->TupleData); - if (ret) - return -1; - return 0; } -/*====================================================================== - - Parsing routines for individual tuples - -======================================================================*/ +/* Parsing routines for individual tuples */ static int parse_device(tuple_t *tuple, cistpl_device_t *device) { - int i; - u_char scale; - u_char *p, *q; + int i; + u_char scale; + u_char *p, *q; - p = (u_char *)tuple->TupleData; - q = p + tuple->TupleDataLen; + p = (u_char *)tuple->TupleData; + q = p + tuple->TupleDataLen; - device->ndev = 0; - for (i = 0; i < CISTPL_MAX_DEVICES; i++) { + device->ndev = 0; + for (i = 0; i < CISTPL_MAX_DEVICES; i++) { - if (*p == 0xff) - break; - device->dev[i].type = (*p >> 4); - device->dev[i].wp = (*p & 0x08) ? 1 : 0; - switch (*p & 0x07) { - case 0: - device->dev[i].speed = 0; - break; - case 1: - device->dev[i].speed = 250; - break; - case 2: - device->dev[i].speed = 200; - break; - case 3: - device->dev[i].speed = 150; - break; - case 4: - device->dev[i].speed = 100; - break; - case 7: - if (++p == q) - return -EINVAL; - device->dev[i].speed = SPEED_CVT(*p); - while (*p & 0x80) + if (*p == 0xff) + break; + device->dev[i].type = (*p >> 4); + device->dev[i].wp = (*p & 0x08) ? 1 : 0; + switch (*p & 0x07) { + case 0: + device->dev[i].speed = 0; + break; + case 1: + device->dev[i].speed = 250; + break; + case 2: + device->dev[i].speed = 200; + break; + case 3: + device->dev[i].speed = 150; + break; + case 4: + device->dev[i].speed = 100; + break; + case 7: if (++p == q) return -EINVAL; - break; - default: - return -EINVAL; - } + device->dev[i].speed = SPEED_CVT(*p); + while (*p & 0x80) + if (++p == q) + return -EINVAL; + break; + default: + return -EINVAL; + } - if (++p == q) - return -EINVAL; - if (*p == 0xff) - break; - scale = *p & 7; - if (scale == 7) - return -EINVAL; - device->dev[i].size = ((*p >> 3) + 1) * (512 << (scale*2)); - device->ndev++; - if (++p == q) - break; - } + if (++p == q) + return -EINVAL; + if (*p == 0xff) + break; + scale = *p & 7; + if (scale == 7) + return -EINVAL; + device->dev[i].size = ((*p >> 3) + 1) * (512 << (scale*2)); + device->ndev++; + if (++p == q) + break; + } - return 0; + return 0; } -/*====================================================================*/ static int parse_checksum(tuple_t *tuple, cistpl_checksum_t *csum) { - u_char *p; - if (tuple->TupleDataLen < 5) - return -EINVAL; - p = (u_char *) tuple->TupleData; - csum->addr = tuple->CISOffset + get_unaligned_le16(p) - 2; - csum->len = get_unaligned_le16(p + 2); - csum->sum = *(p + 4); - return 0; + u_char *p; + if (tuple->TupleDataLen < 5) + return -EINVAL; + p = (u_char *) tuple->TupleData; + csum->addr = tuple->CISOffset + get_unaligned_le16(p) - 2; + csum->len = get_unaligned_le16(p + 2); + csum->sum = *(p + 4); + return 0; } -/*====================================================================*/ static int parse_longlink(tuple_t *tuple, cistpl_longlink_t *link) { - if (tuple->TupleDataLen < 4) - return -EINVAL; - link->addr = get_unaligned_le32(tuple->TupleData); - return 0; + if (tuple->TupleDataLen < 4) + return -EINVAL; + link->addr = get_unaligned_le32(tuple->TupleData); + return 0; } -/*====================================================================*/ -static int parse_longlink_mfc(tuple_t *tuple, - cistpl_longlink_mfc_t *link) +static int parse_longlink_mfc(tuple_t *tuple, cistpl_longlink_mfc_t *link) { - u_char *p; - int i; - - p = (u_char *)tuple->TupleData; - - link->nfn = *p; p++; - if (tuple->TupleDataLen <= link->nfn*5) - return -EINVAL; - for (i = 0; i < link->nfn; i++) { - link->fn[i].space = *p; p++; - link->fn[i].addr = get_unaligned_le32(p); - p += 4; - } - return 0; + u_char *p; + int i; + + p = (u_char *)tuple->TupleData; + + link->nfn = *p; p++; + if (tuple->TupleDataLen <= link->nfn*5) + return -EINVAL; + for (i = 0; i < link->nfn; i++) { + link->fn[i].space = *p; p++; + link->fn[i].addr = get_unaligned_le32(p); + p += 4; + } + return 0; } -/*====================================================================*/ static int parse_strings(u_char *p, u_char *q, int max, char *s, u_char *ofs, u_char *found) { - int i, j, ns; + int i, j, ns; - if (p == q) - return -EINVAL; - ns = 0; j = 0; - for (i = 0; i < max; i++) { - if (*p == 0xff) - break; - ofs[i] = j; - ns++; - for (;;) { - s[j++] = (*p == 0xff) ? '\0' : *p; - if ((*p == '\0') || (*p == 0xff)) - break; - if (++p == q) - return -EINVAL; + if (p == q) + return -EINVAL; + ns = 0; j = 0; + for (i = 0; i < max; i++) { + if (*p == 0xff) + break; + ofs[i] = j; + ns++; + for (;;) { + s[j++] = (*p == 0xff) ? '\0' : *p; + if ((*p == '\0') || (*p == 0xff)) + break; + if (++p == q) + return -EINVAL; + } + if ((*p == 0xff) || (++p == q)) + break; } - if ((*p == 0xff) || (++p == q)) - break; - } - if (found) { - *found = ns; - return 0; - } else { + if (found) { + *found = ns; + return 0; + } + return (ns == max) ? 0 : -EINVAL; - } } -/*====================================================================*/ static int parse_vers_1(tuple_t *tuple, cistpl_vers_1_t *vers_1) { - u_char *p, *q; + u_char *p, *q; - p = (u_char *)tuple->TupleData; - q = p + tuple->TupleDataLen; + p = (u_char *)tuple->TupleData; + q = p + tuple->TupleDataLen; - vers_1->major = *p; p++; - vers_1->minor = *p; p++; - if (p >= q) - return -EINVAL; + vers_1->major = *p; p++; + vers_1->minor = *p; p++; + if (p >= q) + return -EINVAL; - return parse_strings(p, q, CISTPL_VERS_1_MAX_PROD_STRINGS, - vers_1->str, vers_1->ofs, &vers_1->ns); + return parse_strings(p, q, CISTPL_VERS_1_MAX_PROD_STRINGS, + vers_1->str, vers_1->ofs, &vers_1->ns); } -/*====================================================================*/ static int parse_altstr(tuple_t *tuple, cistpl_altstr_t *altstr) { - u_char *p, *q; + u_char *p, *q; - p = (u_char *)tuple->TupleData; - q = p + tuple->TupleDataLen; + p = (u_char *)tuple->TupleData; + q = p + tuple->TupleDataLen; - return parse_strings(p, q, CISTPL_MAX_ALTSTR_STRINGS, - altstr->str, altstr->ofs, &altstr->ns); + return parse_strings(p, q, CISTPL_MAX_ALTSTR_STRINGS, + altstr->str, altstr->ofs, &altstr->ns); } -/*====================================================================*/ static int parse_jedec(tuple_t *tuple, cistpl_jedec_t *jedec) { - u_char *p, *q; - int nid; + u_char *p, *q; + int nid; - p = (u_char *)tuple->TupleData; - q = p + tuple->TupleDataLen; + p = (u_char *)tuple->TupleData; + q = p + tuple->TupleDataLen; - for (nid = 0; nid < CISTPL_MAX_DEVICES; nid++) { - if (p > q-2) - break; - jedec->id[nid].mfr = p[0]; - jedec->id[nid].info = p[1]; - p += 2; - } - jedec->nid = nid; - return 0; + for (nid = 0; nid < CISTPL_MAX_DEVICES; nid++) { + if (p > q-2) + break; + jedec->id[nid].mfr = p[0]; + jedec->id[nid].info = p[1]; + p += 2; + } + jedec->nid = nid; + return 0; } -/*====================================================================*/ static int parse_manfid(tuple_t *tuple, cistpl_manfid_t *m) { - if (tuple->TupleDataLen < 4) - return -EINVAL; - m->manf = get_unaligned_le16(tuple->TupleData); - m->card = get_unaligned_le16(tuple->TupleData + 2); - return 0; + if (tuple->TupleDataLen < 4) + return -EINVAL; + m->manf = get_unaligned_le16(tuple->TupleData); + m->card = get_unaligned_le16(tuple->TupleData + 2); + return 0; } -/*====================================================================*/ static int parse_funcid(tuple_t *tuple, cistpl_funcid_t *f) { - u_char *p; - if (tuple->TupleDataLen < 2) - return -EINVAL; - p = (u_char *)tuple->TupleData; - f->func = p[0]; - f->sysinit = p[1]; - return 0; + u_char *p; + if (tuple->TupleDataLen < 2) + return -EINVAL; + p = (u_char *)tuple->TupleData; + f->func = p[0]; + f->sysinit = p[1]; + return 0; } -/*====================================================================*/ static int parse_funce(tuple_t *tuple, cistpl_funce_t *f) { - u_char *p; - int i; - if (tuple->TupleDataLen < 1) - return -EINVAL; - p = (u_char *)tuple->TupleData; - f->type = p[0]; - for (i = 1; i < tuple->TupleDataLen; i++) - f->data[i-1] = p[i]; - return 0; + u_char *p; + int i; + if (tuple->TupleDataLen < 1) + return -EINVAL; + p = (u_char *)tuple->TupleData; + f->type = p[0]; + for (i = 1; i < tuple->TupleDataLen; i++) + f->data[i-1] = p[i]; + return 0; } -/*====================================================================*/ static int parse_config(tuple_t *tuple, cistpl_config_t *config) { - int rasz, rmsz, i; - u_char *p; - - p = (u_char *)tuple->TupleData; - rasz = *p & 0x03; - rmsz = (*p & 0x3c) >> 2; - if (tuple->TupleDataLen < rasz+rmsz+4) - return -EINVAL; - config->last_idx = *(++p); - p++; - config->base = 0; - for (i = 0; i <= rasz; i++) - config->base += p[i] << (8*i); - p += rasz+1; - for (i = 0; i < 4; i++) - config->rmask[i] = 0; - for (i = 0; i <= rmsz; i++) - config->rmask[i>>2] += p[i] << (8*(i%4)); - config->subtuples = tuple->TupleDataLen - (rasz+rmsz+4); - return 0; + int rasz, rmsz, i; + u_char *p; + + p = (u_char *)tuple->TupleData; + rasz = *p & 0x03; + rmsz = (*p & 0x3c) >> 2; + if (tuple->TupleDataLen < rasz+rmsz+4) + return -EINVAL; + config->last_idx = *(++p); + p++; + config->base = 0; + for (i = 0; i <= rasz; i++) + config->base += p[i] << (8*i); + p += rasz+1; + for (i = 0; i < 4; i++) + config->rmask[i] = 0; + for (i = 0; i <= rmsz; i++) + config->rmask[i>>2] += p[i] << (8*(i%4)); + config->subtuples = tuple->TupleDataLen - (rasz+rmsz+4); + return 0; } -/*====================================================================== +/* The following routines are all used to parse the nightmarish + * config table entries. + */ + +static u_char *parse_power(u_char *p, u_char *q, cistpl_power_t *pwr) +{ + int i; + u_int scale; - The following routines are all used to parse the nightmarish - config table entries. + if (p == q) + return NULL; + pwr->present = *p; + pwr->flags = 0; + p++; + for (i = 0; i < 7; i++) + if (pwr->present & (1<param[i] = POWER_CVT(*p); + scale = POWER_SCALE(*p); + while (*p & 0x80) { + if (++p == q) + return NULL; + if ((*p & 0x7f) < 100) + pwr->param[i] += + (*p & 0x7f) * scale / 100; + else if (*p == 0x7d) + pwr->flags |= CISTPL_POWER_HIGHZ_OK; + else if (*p == 0x7e) + pwr->param[i] = 0; + else if (*p == 0x7f) + pwr->flags |= CISTPL_POWER_HIGHZ_REQ; + else + return NULL; + } + p++; + } + return p; +} -======================================================================*/ -static u_char *parse_power(u_char *p, u_char *q, - cistpl_power_t *pwr) +static u_char *parse_timing(u_char *p, u_char *q, cistpl_timing_t *timing) { - int i; - u_int scale; - - if (p == q) - return NULL; - pwr->present = *p; - pwr->flags = 0; - p++; - for (i = 0; i < 7; i++) - if (pwr->present & (1<param[i] = POWER_CVT(*p); - scale = POWER_SCALE(*p); - while (*p & 0x80) { + u_char scale; + + if (p == q) + return NULL; + scale = *p; + if ((scale & 3) != 3) { if (++p == q) return NULL; - if ((*p & 0x7f) < 100) - pwr->param[i] += (*p & 0x7f) * scale / 100; - else if (*p == 0x7d) - pwr->flags |= CISTPL_POWER_HIGHZ_OK; - else if (*p == 0x7e) - pwr->param[i] = 0; - else if (*p == 0x7f) - pwr->flags |= CISTPL_POWER_HIGHZ_REQ; - else - return NULL; - } - p++; - } - return p; + timing->wait = SPEED_CVT(*p); + timing->waitscale = exponent[scale & 3]; + } else + timing->wait = 0; + scale >>= 2; + if ((scale & 7) != 7) { + if (++p == q) + return NULL; + timing->ready = SPEED_CVT(*p); + timing->rdyscale = exponent[scale & 7]; + } else + timing->ready = 0; + scale >>= 3; + if (scale != 7) { + if (++p == q) + return NULL; + timing->reserved = SPEED_CVT(*p); + timing->rsvscale = exponent[scale]; + } else + timing->reserved = 0; + p++; + return p; } -/*====================================================================*/ -static u_char *parse_timing(u_char *p, u_char *q, - cistpl_timing_t *timing) +static u_char *parse_io(u_char *p, u_char *q, cistpl_io_t *io) { - u_char scale; + int i, j, bsz, lsz; - if (p == q) - return NULL; - scale = *p; - if ((scale & 3) != 3) { - if (++p == q) - return NULL; - timing->wait = SPEED_CVT(*p); - timing->waitscale = exponent[scale & 3]; - } else - timing->wait = 0; - scale >>= 2; - if ((scale & 7) != 7) { - if (++p == q) + if (p == q) return NULL; - timing->ready = SPEED_CVT(*p); - timing->rdyscale = exponent[scale & 7]; - } else - timing->ready = 0; - scale >>= 3; - if (scale != 7) { + io->flags = *p; + + if (!(*p & 0x80)) { + io->nwin = 1; + io->win[0].base = 0; + io->win[0].len = (1 << (io->flags & CISTPL_IO_LINES_MASK)); + return p+1; + } + if (++p == q) return NULL; - timing->reserved = SPEED_CVT(*p); - timing->rsvscale = exponent[scale]; - } else - timing->reserved = 0; - p++; - return p; -} - -/*====================================================================*/ + io->nwin = (*p & 0x0f) + 1; + bsz = (*p & 0x30) >> 4; + if (bsz == 3) + bsz++; + lsz = (*p & 0xc0) >> 6; + if (lsz == 3) + lsz++; + p++; -static u_char *parse_io(u_char *p, u_char *q, cistpl_io_t *io) -{ - int i, j, bsz, lsz; - - if (p == q) - return NULL; - io->flags = *p; - - if (!(*p & 0x80)) { - io->nwin = 1; - io->win[0].base = 0; - io->win[0].len = (1 << (io->flags & CISTPL_IO_LINES_MASK)); - return p+1; - } - - if (++p == q) - return NULL; - io->nwin = (*p & 0x0f) + 1; - bsz = (*p & 0x30) >> 4; - if (bsz == 3) - bsz++; - lsz = (*p & 0xc0) >> 6; - if (lsz == 3) - lsz++; - p++; - - for (i = 0; i < io->nwin; i++) { - io->win[i].base = 0; - io->win[i].len = 1; - for (j = 0; j < bsz; j++, p++) { - if (p == q) - return NULL; - io->win[i].base += *p << (j*8); - } - for (j = 0; j < lsz; j++, p++) { - if (p == q) - return NULL; - io->win[i].len += *p << (j*8); + for (i = 0; i < io->nwin; i++) { + io->win[i].base = 0; + io->win[i].len = 1; + for (j = 0; j < bsz; j++, p++) { + if (p == q) + return NULL; + io->win[i].base += *p << (j*8); + } + for (j = 0; j < lsz; j++, p++) { + if (p == q) + return NULL; + io->win[i].len += *p << (j*8); + } } - } - return p; + return p; } -/*====================================================================*/ static u_char *parse_mem(u_char *p, u_char *q, cistpl_mem_t *mem) { - int i, j, asz, lsz, has_ha; - u_int len, ca, ha; - - if (p == q) - return NULL; - - mem->nwin = (*p & 0x07) + 1; - lsz = (*p & 0x18) >> 3; - asz = (*p & 0x60) >> 5; - has_ha = (*p & 0x80); - if (++p == q) - return NULL; - - for (i = 0; i < mem->nwin; i++) { - len = ca = ha = 0; - for (j = 0; j < lsz; j++, p++) { - if (p == q) - return NULL; - len += *p << (j*8); - } - for (j = 0; j < asz; j++, p++) { - if (p == q) - return NULL; - ca += *p << (j*8); + int i, j, asz, lsz, has_ha; + u_int len, ca, ha; + + if (p == q) + return NULL; + + mem->nwin = (*p & 0x07) + 1; + lsz = (*p & 0x18) >> 3; + asz = (*p & 0x60) >> 5; + has_ha = (*p & 0x80); + if (++p == q) + return NULL; + + for (i = 0; i < mem->nwin; i++) { + len = ca = ha = 0; + for (j = 0; j < lsz; j++, p++) { + if (p == q) + return NULL; + len += *p << (j*8); + } + for (j = 0; j < asz; j++, p++) { + if (p == q) + return NULL; + ca += *p << (j*8); + } + if (has_ha) + for (j = 0; j < asz; j++, p++) { + if (p == q) + return NULL; + ha += *p << (j*8); + } + mem->win[i].len = len << 8; + mem->win[i].card_addr = ca << 8; + mem->win[i].host_addr = ha << 8; } - if (has_ha) - for (j = 0; j < asz; j++, p++) { - if (p == q) - return NULL; - ha += *p << (j*8); - } - mem->win[i].len = len << 8; - mem->win[i].card_addr = ca << 8; - mem->win[i].host_addr = ha << 8; - } - return p; + return p; } -/*====================================================================*/ static u_char *parse_irq(u_char *p, u_char *q, cistpl_irq_t *irq) { - if (p == q) - return NULL; - irq->IRQInfo1 = *p; p++; - if (irq->IRQInfo1 & IRQ_INFO2_VALID) { - if (p+2 > q) + if (p == q) return NULL; - irq->IRQInfo2 = (p[1]<<8) + p[0]; - p += 2; - } - return p; + irq->IRQInfo1 = *p; p++; + if (irq->IRQInfo1 & IRQ_INFO2_VALID) { + if (p+2 > q) + return NULL; + irq->IRQInfo2 = (p[1]<<8) + p[0]; + p += 2; + } + return p; } -/*====================================================================*/ static int parse_cftable_entry(tuple_t *tuple, cistpl_cftable_entry_t *entry) { - u_char *p, *q, features; - - p = tuple->TupleData; - q = p + tuple->TupleDataLen; - entry->index = *p & 0x3f; - entry->flags = 0; - if (*p & 0x40) - entry->flags |= CISTPL_CFTABLE_DEFAULT; - if (*p & 0x80) { - if (++p == q) - return -EINVAL; - if (*p & 0x10) - entry->flags |= CISTPL_CFTABLE_BVDS; - if (*p & 0x20) - entry->flags |= CISTPL_CFTABLE_WP; + u_char *p, *q, features; + + p = tuple->TupleData; + q = p + tuple->TupleDataLen; + entry->index = *p & 0x3f; + entry->flags = 0; if (*p & 0x40) - entry->flags |= CISTPL_CFTABLE_RDYBSY; - if (*p & 0x80) - entry->flags |= CISTPL_CFTABLE_MWAIT; - entry->interface = *p & 0x0f; - } else - entry->interface = 0; - - /* Process optional features */ - if (++p == q) - return -EINVAL; - features = *p; p++; - - /* Power options */ - if ((features & 3) > 0) { - p = parse_power(p, q, &entry->vcc); - if (p == NULL) - return -EINVAL; - } else - entry->vcc.present = 0; - if ((features & 3) > 1) { - p = parse_power(p, q, &entry->vpp1); - if (p == NULL) - return -EINVAL; - } else - entry->vpp1.present = 0; - if ((features & 3) > 2) { - p = parse_power(p, q, &entry->vpp2); - if (p == NULL) - return -EINVAL; - } else - entry->vpp2.present = 0; + entry->flags |= CISTPL_CFTABLE_DEFAULT; + if (*p & 0x80) { + if (++p == q) + return -EINVAL; + if (*p & 0x10) + entry->flags |= CISTPL_CFTABLE_BVDS; + if (*p & 0x20) + entry->flags |= CISTPL_CFTABLE_WP; + if (*p & 0x40) + entry->flags |= CISTPL_CFTABLE_RDYBSY; + if (*p & 0x80) + entry->flags |= CISTPL_CFTABLE_MWAIT; + entry->interface = *p & 0x0f; + } else + entry->interface = 0; - /* Timing options */ - if (features & 0x04) { - p = parse_timing(p, q, &entry->timing); - if (p == NULL) - return -EINVAL; - } else { - entry->timing.wait = 0; - entry->timing.ready = 0; - entry->timing.reserved = 0; - } - - /* I/O window options */ - if (features & 0x08) { - p = parse_io(p, q, &entry->io); - if (p == NULL) + /* Process optional features */ + if (++p == q) return -EINVAL; - } else - entry->io.nwin = 0; + features = *p; p++; - /* Interrupt options */ - if (features & 0x10) { - p = parse_irq(p, q, &entry->irq); - if (p == NULL) - return -EINVAL; - } else - entry->irq.IRQInfo1 = 0; - - switch (features & 0x60) { - case 0x00: - entry->mem.nwin = 0; - break; - case 0x20: - entry->mem.nwin = 1; - entry->mem.win[0].len = get_unaligned_le16(p) << 8; - entry->mem.win[0].card_addr = 0; - entry->mem.win[0].host_addr = 0; - p += 2; - if (p > q) - return -EINVAL; - break; - case 0x40: - entry->mem.nwin = 1; - entry->mem.win[0].len = get_unaligned_le16(p) << 8; - entry->mem.win[0].card_addr = get_unaligned_le16(p + 2) << 8; - entry->mem.win[0].host_addr = 0; - p += 4; - if (p > q) - return -EINVAL; - break; - case 0x60: - p = parse_mem(p, q, &entry->mem); - if (p == NULL) - return -EINVAL; - break; - } + /* Power options */ + if ((features & 3) > 0) { + p = parse_power(p, q, &entry->vcc); + if (p == NULL) + return -EINVAL; + } else + entry->vcc.present = 0; + if ((features & 3) > 1) { + p = parse_power(p, q, &entry->vpp1); + if (p == NULL) + return -EINVAL; + } else + entry->vpp1.present = 0; + if ((features & 3) > 2) { + p = parse_power(p, q, &entry->vpp2); + if (p == NULL) + return -EINVAL; + } else + entry->vpp2.present = 0; - /* Misc features */ - if (features & 0x80) { - if (p == q) - return -EINVAL; - entry->flags |= (*p << 8); - while (*p & 0x80) - if (++p == q) - return -EINVAL; - p++; - } + /* Timing options */ + if (features & 0x04) { + p = parse_timing(p, q, &entry->timing); + if (p == NULL) + return -EINVAL; + } else { + entry->timing.wait = 0; + entry->timing.ready = 0; + entry->timing.reserved = 0; + } - entry->subtuples = q-p; + /* I/O window options */ + if (features & 0x08) { + p = parse_io(p, q, &entry->io); + if (p == NULL) + return -EINVAL; + } else + entry->io.nwin = 0; + + /* Interrupt options */ + if (features & 0x10) { + p = parse_irq(p, q, &entry->irq); + if (p == NULL) + return -EINVAL; + } else + entry->irq.IRQInfo1 = 0; + + switch (features & 0x60) { + case 0x00: + entry->mem.nwin = 0; + break; + case 0x20: + entry->mem.nwin = 1; + entry->mem.win[0].len = get_unaligned_le16(p) << 8; + entry->mem.win[0].card_addr = 0; + entry->mem.win[0].host_addr = 0; + p += 2; + if (p > q) + return -EINVAL; + break; + case 0x40: + entry->mem.nwin = 1; + entry->mem.win[0].len = get_unaligned_le16(p) << 8; + entry->mem.win[0].card_addr = get_unaligned_le16(p + 2) << 8; + entry->mem.win[0].host_addr = 0; + p += 4; + if (p > q) + return -EINVAL; + break; + case 0x60: + p = parse_mem(p, q, &entry->mem); + if (p == NULL) + return -EINVAL; + break; + } + + /* Misc features */ + if (features & 0x80) { + if (p == q) + return -EINVAL; + entry->flags |= (*p << 8); + while (*p & 0x80) + if (++p == q) + return -EINVAL; + p++; + } + + entry->subtuples = q-p; - return 0; + return 0; } -/*====================================================================*/ static int parse_device_geo(tuple_t *tuple, cistpl_device_geo_t *geo) { - u_char *p, *q; - int n; + u_char *p, *q; + int n; - p = (u_char *)tuple->TupleData; - q = p + tuple->TupleDataLen; + p = (u_char *)tuple->TupleData; + q = p + tuple->TupleDataLen; - for (n = 0; n < CISTPL_MAX_DEVICES; n++) { - if (p > q-6) - break; - geo->geo[n].buswidth = p[0]; - geo->geo[n].erase_block = 1 << (p[1]-1); - geo->geo[n].read_block = 1 << (p[2]-1); - geo->geo[n].write_block = 1 << (p[3]-1); - geo->geo[n].partition = 1 << (p[4]-1); - geo->geo[n].interleave = 1 << (p[5]-1); - p += 6; - } - geo->ngeo = n; - return 0; + for (n = 0; n < CISTPL_MAX_DEVICES; n++) { + if (p > q-6) + break; + geo->geo[n].buswidth = p[0]; + geo->geo[n].erase_block = 1 << (p[1]-1); + geo->geo[n].read_block = 1 << (p[2]-1); + geo->geo[n].write_block = 1 << (p[3]-1); + geo->geo[n].partition = 1 << (p[4]-1); + geo->geo[n].interleave = 1 << (p[5]-1); + p += 6; + } + geo->ngeo = n; + return 0; } -/*====================================================================*/ static int parse_vers_2(tuple_t *tuple, cistpl_vers_2_t *v2) { - u_char *p, *q; - - if (tuple->TupleDataLen < 10) - return -EINVAL; - - p = tuple->TupleData; - q = p + tuple->TupleDataLen; - - v2->vers = p[0]; - v2->comply = p[1]; - v2->dindex = get_unaligned_le16(p + 2); - v2->vspec8 = p[6]; - v2->vspec9 = p[7]; - v2->nhdr = p[8]; - p += 9; - return parse_strings(p, q, 2, v2->str, &v2->vendor, NULL); + u_char *p, *q; + + if (tuple->TupleDataLen < 10) + return -EINVAL; + + p = tuple->TupleData; + q = p + tuple->TupleDataLen; + + v2->vers = p[0]; + v2->comply = p[1]; + v2->dindex = get_unaligned_le16(p + 2); + v2->vspec8 = p[6]; + v2->vspec9 = p[7]; + v2->nhdr = p[8]; + p += 9; + return parse_strings(p, q, 2, v2->str, &v2->vendor, NULL); } -/*====================================================================*/ static int parse_org(tuple_t *tuple, cistpl_org_t *org) { - u_char *p, *q; - int i; - - p = tuple->TupleData; - q = p + tuple->TupleDataLen; - if (p == q) - return -EINVAL; - org->data_org = *p; - if (++p == q) - return -EINVAL; - for (i = 0; i < 30; i++) { - org->desc[i] = *p; - if (*p == '\0') - break; + u_char *p, *q; + int i; + + p = tuple->TupleData; + q = p + tuple->TupleDataLen; + if (p == q) + return -EINVAL; + org->data_org = *p; if (++p == q) return -EINVAL; - } - return 0; + for (i = 0; i < 30; i++) { + org->desc[i] = *p; + if (*p == '\0') + break; + if (++p == q) + return -EINVAL; + } + return 0; } -/*====================================================================*/ static int parse_format(tuple_t *tuple, cistpl_format_t *fmt) { - u_char *p; + u_char *p; - if (tuple->TupleDataLen < 10) - return -EINVAL; + if (tuple->TupleDataLen < 10) + return -EINVAL; - p = tuple->TupleData; + p = tuple->TupleData; - fmt->type = p[0]; - fmt->edc = p[1]; - fmt->offset = get_unaligned_le32(p + 2); - fmt->length = get_unaligned_le32(p + 6); + fmt->type = p[0]; + fmt->edc = p[1]; + fmt->offset = get_unaligned_le32(p + 2); + fmt->length = get_unaligned_le32(p + 6); - return 0; + return 0; } -/*====================================================================*/ int pcmcia_parse_tuple(tuple_t *tuple, cisparse_t *parse) { - int ret = 0; - - if (tuple->TupleDataLen > tuple->TupleDataMax) - return -EINVAL; - switch (tuple->TupleCode) { - case CISTPL_DEVICE: - case CISTPL_DEVICE_A: - ret = parse_device(tuple, &parse->device); - break; - case CISTPL_CHECKSUM: - ret = parse_checksum(tuple, &parse->checksum); - break; - case CISTPL_LONGLINK_A: - case CISTPL_LONGLINK_C: - ret = parse_longlink(tuple, &parse->longlink); - break; - case CISTPL_LONGLINK_MFC: - ret = parse_longlink_mfc(tuple, &parse->longlink_mfc); - break; - case CISTPL_VERS_1: - ret = parse_vers_1(tuple, &parse->version_1); - break; - case CISTPL_ALTSTR: - ret = parse_altstr(tuple, &parse->altstr); - break; - case CISTPL_JEDEC_A: - case CISTPL_JEDEC_C: - ret = parse_jedec(tuple, &parse->jedec); - break; - case CISTPL_MANFID: - ret = parse_manfid(tuple, &parse->manfid); - break; - case CISTPL_FUNCID: - ret = parse_funcid(tuple, &parse->funcid); - break; - case CISTPL_FUNCE: - ret = parse_funce(tuple, &parse->funce); - break; - case CISTPL_CONFIG: - ret = parse_config(tuple, &parse->config); - break; - case CISTPL_CFTABLE_ENTRY: - ret = parse_cftable_entry(tuple, &parse->cftable_entry); - break; - case CISTPL_DEVICE_GEO: - case CISTPL_DEVICE_GEO_A: - ret = parse_device_geo(tuple, &parse->device_geo); - break; - case CISTPL_VERS_2: - ret = parse_vers_2(tuple, &parse->vers_2); - break; - case CISTPL_ORG: - ret = parse_org(tuple, &parse->org); - break; - case CISTPL_FORMAT: - case CISTPL_FORMAT_A: - ret = parse_format(tuple, &parse->format); - break; - case CISTPL_NO_LINK: - case CISTPL_LINKTARGET: - ret = 0; - break; - default: - ret = -EINVAL; - break; - } - if (ret) - pr_debug("parse_tuple failed %d\n", ret); - return ret; + int ret = 0; + + if (tuple->TupleDataLen > tuple->TupleDataMax) + return -EINVAL; + switch (tuple->TupleCode) { + case CISTPL_DEVICE: + case CISTPL_DEVICE_A: + ret = parse_device(tuple, &parse->device); + break; + case CISTPL_CHECKSUM: + ret = parse_checksum(tuple, &parse->checksum); + break; + case CISTPL_LONGLINK_A: + case CISTPL_LONGLINK_C: + ret = parse_longlink(tuple, &parse->longlink); + break; + case CISTPL_LONGLINK_MFC: + ret = parse_longlink_mfc(tuple, &parse->longlink_mfc); + break; + case CISTPL_VERS_1: + ret = parse_vers_1(tuple, &parse->version_1); + break; + case CISTPL_ALTSTR: + ret = parse_altstr(tuple, &parse->altstr); + break; + case CISTPL_JEDEC_A: + case CISTPL_JEDEC_C: + ret = parse_jedec(tuple, &parse->jedec); + break; + case CISTPL_MANFID: + ret = parse_manfid(tuple, &parse->manfid); + break; + case CISTPL_FUNCID: + ret = parse_funcid(tuple, &parse->funcid); + break; + case CISTPL_FUNCE: + ret = parse_funce(tuple, &parse->funce); + break; + case CISTPL_CONFIG: + ret = parse_config(tuple, &parse->config); + break; + case CISTPL_CFTABLE_ENTRY: + ret = parse_cftable_entry(tuple, &parse->cftable_entry); + break; + case CISTPL_DEVICE_GEO: + case CISTPL_DEVICE_GEO_A: + ret = parse_device_geo(tuple, &parse->device_geo); + break; + case CISTPL_VERS_2: + ret = parse_vers_2(tuple, &parse->vers_2); + break; + case CISTPL_ORG: + ret = parse_org(tuple, &parse->org); + break; + case CISTPL_FORMAT: + case CISTPL_FORMAT_A: + ret = parse_format(tuple, &parse->format); + break; + case CISTPL_NO_LINK: + case CISTPL_LINKTARGET: + ret = 0; + break; + default: + ret = -EINVAL; + break; + } + if (ret) + pr_debug("parse_tuple failed %d\n", ret); + return ret; } EXPORT_SYMBOL(pcmcia_parse_tuple); -/*====================================================================== - This is used internally by Card Services to look up CIS stuff. - -======================================================================*/ - -int pccard_read_tuple(struct pcmcia_socket *s, unsigned int function, cisdata_t code, void *parse) +/** + * pccard_read_tuple() - internal CIS tuple access + * @s: the struct pcmcia_socket where the card is inserted + * @function: the device function we loop for + * @code: which CIS code shall we look for? + * @parse: buffer where the tuple shall be parsed (or NULL, if no parse) + * + * pccard_read_tuple() reads out one tuple and attempts to parse it + */ +int pccard_read_tuple(struct pcmcia_socket *s, unsigned int function, + cisdata_t code, void *parse) { - tuple_t tuple; - cisdata_t *buf; - int ret; - - buf = kmalloc(256, GFP_KERNEL); - if (buf == NULL) { - dev_printk(KERN_WARNING, &s->dev, "no memory to read tuple\n"); - return -ENOMEM; - } - tuple.DesiredTuple = code; - tuple.Attributes = 0; - if (function == BIND_FN_ALL) - tuple.Attributes = TUPLE_RETURN_COMMON; - ret = pccard_get_first_tuple(s, function, &tuple); - if (ret != 0) - goto done; - tuple.TupleData = buf; - tuple.TupleOffset = 0; - tuple.TupleDataMax = 255; - ret = pccard_get_tuple_data(s, &tuple); - if (ret != 0) - goto done; - ret = pcmcia_parse_tuple(&tuple, parse); + tuple_t tuple; + cisdata_t *buf; + int ret; + + buf = kmalloc(256, GFP_KERNEL); + if (buf == NULL) { + dev_printk(KERN_WARNING, &s->dev, "no memory to read tuple\n"); + return -ENOMEM; + } + tuple.DesiredTuple = code; + tuple.Attributes = 0; + if (function == BIND_FN_ALL) + tuple.Attributes = TUPLE_RETURN_COMMON; + ret = pccard_get_first_tuple(s, function, &tuple); + if (ret != 0) + goto done; + tuple.TupleData = buf; + tuple.TupleOffset = 0; + tuple.TupleDataMax = 255; + ret = pccard_get_tuple_data(s, &tuple); + if (ret != 0) + goto done; + ret = pcmcia_parse_tuple(&tuple, parse); done: - kfree(buf); - return ret; + kfree(buf); + return ret; } diff --git a/drivers/pcmcia/rsrc_mgr.c b/drivers/pcmcia/rsrc_mgr.c index e6f7d410aed6..452c83b512c4 100644 --- a/drivers/pcmcia/rsrc_mgr.c +++ b/drivers/pcmcia/rsrc_mgr.c @@ -79,9 +79,8 @@ static resource_size_t pcmcia_align(void *align_data, #ifdef CONFIG_X86 if (res->flags & IORESOURCE_IO) { - if (start & 0x300) { + if (start & 0x300) start = (start + 0x3ff) & ~0x3ff; - } } #endif -- cgit v1.2.3 From a3f916f2c84f2b9e1d32cc0dbfe326a9e380dbfb Mon Sep 17 00:00:00 2001 From: Dominik Brodowski Date: Fri, 15 Jan 2010 23:55:21 +0100 Subject: pcmcia: disable pcmcia ioctl for !ARM, prepare for removal The PCMCIA ioctl -- deprecated for years -- suffers from insufficient locking. As it already has been deprecated for years, with its removal long overdue, limit it to !SMP and !PREEMPT. Furthermore, the last legitimate use of the ioctl to be reported relates to the ARM architecture in 2008.[1] Attempts to resolve this issue turned out unsuccessful so far.[2] Other usages have only been reported as hear-say. If there are any legitiate and necessary use-cases remaining, please speak out before the end of the grace period until 2.6.3{5,6}(-rc1). [1] http://lists.infradead.org/pipermail/linux-pcmcia/2008-April/005440.html see also: http://lkml.org/lkml/2008/2/27/291 [2] http://lists.infradead.org/pipermail/linux-pcmcia/2008-April/005450.html http://lists.infradead.org/pipermail/linux-pcmcia/2010-January/006740.html see also: http://lists.infradead.org/pipermail/linux-pcmcia/2008-April/005453.html CC: Russell King CC: Alan Cox CC: Robert P. J. Day CC: Jaswinder Singh Rajput CC: linux-kernel@vger.kernel.org Signed-off-by: Dominik Brodowski --- Documentation/feature-removal-schedule.txt | 12 +++++++++--- drivers/pcmcia/Kconfig | 14 ++++++++++---- 2 files changed, 19 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt index 732b1fa48cf2..3e57a7502e86 100644 --- a/Documentation/feature-removal-schedule.txt +++ b/Documentation/feature-removal-schedule.txt @@ -138,19 +138,25 @@ Who: Mauro Carvalho Chehab --------------------------- What: PCMCIA control ioctl (needed for pcmcia-cs [cardmgr, cardctl]) -When: November 2005 +When: 2.6.35/2.6.36 Files: drivers/pcmcia/: pcmcia_ioctl.c Why: With the 16-bit PCMCIA subsystem now behaving (almost) like a normal hotpluggable bus, and with it using the default kernel infrastructure (hotplug, driver core, sysfs) keeping the PCMCIA control ioctl needed by cardmgr and cardctl from pcmcia-cs is - unnecessary, and makes further cleanups and integration of the + unnecessary and potentially harmful (it does not provide for + proper locking), and makes further cleanups and integration of the PCMCIA subsystem into the Linux kernel device driver model more difficult. The features provided by cardmgr and cardctl are either handled by the kernel itself now or are available in the new pcmciautils package available at http://kernel.org/pub/linux/utils/kernel/pcmcia/ -Who: Dominik Brodowski + + For all architectures except ARM, the associated config symbol + has been removed from kernel 2.6.34; for ARM, it will be likely + be removed from kernel 2.6.35. The actual code will then likely + be removed from kernel 2.6.36. +Who: Dominik Brodowski --------------------------- diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index 0a6601c76809..d189e4743e69 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -51,17 +51,23 @@ config PCMCIA_LOAD_CIS config PCMCIA_IOCTL bool "PCMCIA control ioctl (obsolete)" - depends on PCMCIA + depends on PCMCIA && ARM && !SMP && !PREEMPT default y help If you say Y here, the deprecated ioctl interface to the PCMCIA - subsystem will be built. It is needed by cardmgr and cardctl - (pcmcia-cs) to function properly. + subsystem will be built. It is needed by the deprecated pcmcia-cs + tools (cardmgr, cardctl) to function properly. You should use the new pcmciautils package instead (see for location and details). - If unsure, say Y. + This config option will most likely be removed from kernel 2.6.35, + the associated code from kernel 2.6.36. + + As the PCMCIA ioctl is not locking safe, it depends on !SMP and + !PREEMPT. + + If unsure, say N. config CARDBUS bool "32-bit CardBus support" -- cgit v1.2.3 From 48a29516e8b0b8cd59f5afec90a14f49dd9cf967 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 2 Mar 2010 22:46:10 +0000 Subject: cpmac: use after free The original code dereferenced "cpmac_mii" after calling "mdiobus_free(cpmac_mii);" Signed-off-by: Dan Carpenter Reviewed-by: Jiri Pirko Signed-off-by: David S. Miller --- drivers/net/cpmac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c index b85c81f60d10..9d489421535e 100644 --- a/drivers/net/cpmac.c +++ b/drivers/net/cpmac.c @@ -1290,8 +1290,8 @@ void __devexit cpmac_exit(void) { platform_driver_unregister(&cpmac_driver); mdiobus_unregister(cpmac_mii); - mdiobus_free(cpmac_mii); iounmap(cpmac_mii->priv); + mdiobus_free(cpmac_mii); } module_init(cpmac_init); -- cgit v1.2.3 From 9fe969345b10931319b3f1e7034fbdeb786de234 Mon Sep 17 00:00:00 2001 From: Sarveshwar Bandi Date: Tue, 2 Mar 2010 22:37:28 +0000 Subject: be2net: download NCSI section during firmware update Adding code to update NCSI section while updating firmware on the controller. Signed-off-by: Sarveshwar Bandi Signed-off-by: David S. Miller --- drivers/net/benet/be_hw.h | 5 +++-- drivers/net/benet/be_main.c | 14 +++++++++++--- 2 files changed, 14 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/net/benet/be_hw.h b/drivers/net/benet/be_hw.h index 5ffb149181ad..2d4a4b827637 100644 --- a/drivers/net/benet/be_hw.h +++ b/drivers/net/benet/be_hw.h @@ -114,8 +114,7 @@ #define IMG_TYPE_ISCSI_BACKUP 9 #define IMG_TYPE_FCOE_FW_ACTIVE 10 #define IMG_TYPE_FCOE_FW_BACKUP 11 -#define IMG_TYPE_NCSI_BITFILE 13 -#define IMG_TYPE_NCSI_8051 14 +#define IMG_TYPE_NCSI_FW 13 #define FLASHROM_OPER_FLASH 1 #define FLASHROM_OPER_SAVE 2 @@ -127,6 +126,7 @@ #define FLASH_IMAGE_MAX_SIZE_g3 (2097152) /* Max fw image size */ #define FLASH_BIOS_IMAGE_MAX_SIZE_g3 (524288) /* Max OPTION ROM img sz */ #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576) /* Max Redboot image sz */ +#define FLASH_NCSI_IMAGE_MAX_SIZE_g3 (262144) /* Max NSCI image sz */ #define FLASH_NCSI_MAGIC (0x16032009) #define FLASH_NCSI_DISABLED (0) @@ -144,6 +144,7 @@ #define FLASH_FCoE_BIOS_START_g2 (524288) #define FLASH_REDBOOT_START_g2 (0) +#define FLASH_NCSI_START_g3 (15990784) #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152) #define FLASH_iSCSI_BACKUP_IMAGE_START_g3 (4194304) #define FLASH_FCoE_PRIMARY_IMAGE_START_g3 (6291456) diff --git a/drivers/net/benet/be_main.c b/drivers/net/benet/be_main.c index a703ed8e24fe..22f787f2a30b 100644 --- a/drivers/net/benet/be_main.c +++ b/drivers/net/benet/be_main.c @@ -1880,8 +1880,9 @@ static int be_flash_data(struct be_adapter *adapter, const u8 *p = fw->data; struct be_cmd_write_flashrom *req = flash_cmd->va; struct flash_comp *pflashcomp; + int num_comp; - struct flash_comp gen3_flash_types[8] = { + struct flash_comp gen3_flash_types[9] = { { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE, FLASH_IMAGE_MAX_SIZE_g3}, { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT, @@ -1897,7 +1898,9 @@ static int be_flash_data(struct be_adapter *adapter, { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE, FLASH_IMAGE_MAX_SIZE_g3}, { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP, - FLASH_IMAGE_MAX_SIZE_g3} + FLASH_IMAGE_MAX_SIZE_g3}, + { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW, + FLASH_NCSI_IMAGE_MAX_SIZE_g3} }; struct flash_comp gen2_flash_types[8] = { { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE, @@ -1921,11 +1924,16 @@ static int be_flash_data(struct be_adapter *adapter, if (adapter->generation == BE_GEN3) { pflashcomp = gen3_flash_types; filehdr_size = sizeof(struct flash_file_hdr_g3); + num_comp = 9; } else { pflashcomp = gen2_flash_types; filehdr_size = sizeof(struct flash_file_hdr_g2); + num_comp = 8; } - for (i = 0; i < 8; i++) { + for (i = 0; i < num_comp; i++) { + if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) && + memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0) + continue; if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) && (!be_flash_redboot(adapter, fw->data, pflashcomp[i].offset, pflashcomp[i].size, -- cgit v1.2.3 From bf829370a8d664d87a61697c8a0d6d780c336aa4 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 2 Mar 2010 22:22:41 +0000 Subject: cassini: fix off by one There are only 6 link_modes. Signed-off-by: Dan Carpenter Signed-off-by: David S. Miller --- drivers/net/cassini.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/cassini.c b/drivers/net/cassini.c index 7cbcfb0ade1c..9bd155e4111c 100644 --- a/drivers/net/cassini.c +++ b/drivers/net/cassini.c @@ -5072,7 +5072,7 @@ static int __devinit cas_init_one(struct pci_dev *pdev, INIT_WORK(&cp->reset_task, cas_reset_task); /* Default link parameters */ - if (link_mode >= 0 && link_mode <= 6) + if (link_mode >= 0 && link_mode < 6) cp->link_cntl = link_modes[link_mode]; else cp->link_cntl = BMCR_ANENABLE; -- cgit v1.2.3 From 4d27b87785a743fdae653d395a3a4e763269c53c Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 2 Mar 2010 21:07:24 +0000 Subject: davinci_emac: off by one This off by one error was found by smatch. drivers/net/davinci_emac.c +2390 emac_dev_open(13) error: buffer overflow 'priv->mac_addr' 6 <= 6 Signed-off-by: Dan Carpenter Signed-off-by: David S. Miller --- drivers/net/davinci_emac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 1ac9440eb3fb..32960b9b02ae 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -2385,7 +2385,7 @@ static int emac_dev_open(struct net_device *ndev) struct emac_priv *priv = netdev_priv(ndev); netif_carrier_off(ndev); - for (cnt = 0; cnt <= ETH_ALEN; cnt++) + for (cnt = 0; cnt < ETH_ALEN; cnt++) ndev->dev_addr[cnt] = priv->mac_addr[cnt]; /* Configuration items */ -- cgit v1.2.3 From 6c71dcb28ff9b63b814a0b76a256f5dae08d3e0d Mon Sep 17 00:00:00 2001 From: Hannes Reinecke Date: Wed, 2 Dec 2009 14:28:48 -0600 Subject: [SCSI] scsi_dh_emc: fix mode select request setup This patch fixes the request setup code for mode selects. I got the fixes from Hannes Reinecke while trying to hunt down some problems and merged it into one patch. I am sending it because Hannes is busy with other things. The patch fixes: - setting of the length for mode selects. - setting of the data direction for mode select 10. Signed-off-by: Hannes Reinecke Signed-off-by: Mike Christie Signed-off-by: James Bottomley --- drivers/scsi/device_handler/scsi_dh_emc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/device_handler/scsi_dh_emc.c b/drivers/scsi/device_handler/scsi_dh_emc.c index 61966750bd60..63032ec3db92 100644 --- a/drivers/scsi/device_handler/scsi_dh_emc.c +++ b/drivers/scsi/device_handler/scsi_dh_emc.c @@ -272,7 +272,7 @@ static struct request *get_req(struct scsi_device *sdev, int cmd, int len = 0; rq = blk_get_request(sdev->request_queue, - (cmd == MODE_SELECT) ? WRITE : READ, GFP_NOIO); + (cmd != INQUIRY) ? WRITE : READ, GFP_NOIO); if (!rq) { sdev_printk(KERN_INFO, sdev, "get_req: blk_get_request failed"); return NULL; @@ -286,14 +286,17 @@ static struct request *get_req(struct scsi_device *sdev, int cmd, len = sizeof(short_trespass); rq->cmd_flags |= REQ_RW; rq->cmd[1] = 0x10; + rq->cmd[4] = len; break; case MODE_SELECT_10: len = sizeof(long_trespass); rq->cmd_flags |= REQ_RW; rq->cmd[1] = 0x10; + rq->cmd[8] = len; break; case INQUIRY: len = CLARIION_BUFFER_SIZE; + rq->cmd[4] = len; memset(buffer, 0, len); break; default: @@ -301,7 +304,6 @@ static struct request *get_req(struct scsi_device *sdev, int cmd, break; } - rq->cmd[4] = len; rq->cmd_type = REQ_TYPE_BLOCK_PC; rq->cmd_flags |= REQ_FAILFAST_DEV | REQ_FAILFAST_TRANSPORT | REQ_FAILFAST_DRIVER; -- cgit v1.2.3 From a32c055feed74246747bf4f45adb765136d3a4d3 Mon Sep 17 00:00:00 2001 From: Wayne Boyer Date: Fri, 19 Feb 2010 13:23:36 -0800 Subject: [SCSI] ipr: add support for new adapter command structures for the next generation chip Change the adapter command structures such that both 32 bit and 64 bit based adapters can work with the driver. Signed-off-by: Wayne Boyer Signed-off-by: James Bottomley --- drivers/scsi/ipr.c | 450 +++++++++++++++++++++++++++++++++++++++-------------- drivers/scsi/ipr.h | 61 ++++++-- 2 files changed, 385 insertions(+), 126 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index 032f0d0e6cb4..359882eadc26 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -131,13 +131,13 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = { }; static const struct ipr_chip_t ipr_chip[] = { - { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE, IPR_USE_LSI, &ipr_chip_cfg[0] }, - { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, IPR_USE_LSI, &ipr_chip_cfg[0] }, - { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN, IPR_USE_LSI, &ipr_chip_cfg[0] }, - { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN, IPR_USE_LSI, &ipr_chip_cfg[0] }, - { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, IPR_USE_MSI, &ipr_chip_cfg[0] }, - { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE, IPR_USE_LSI, &ipr_chip_cfg[1] }, - { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, IPR_USE_LSI, &ipr_chip_cfg[1] } + { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE, IPR_USE_LSI, IPR_SIS32, &ipr_chip_cfg[0] }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, IPR_USE_LSI, IPR_SIS32, &ipr_chip_cfg[0] }, + { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN, IPR_USE_LSI, IPR_SIS32, &ipr_chip_cfg[0] }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN, IPR_USE_LSI, IPR_SIS32, &ipr_chip_cfg[0] }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, IPR_USE_MSI, IPR_SIS32, &ipr_chip_cfg[0] }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE, IPR_USE_LSI, IPR_SIS32, &ipr_chip_cfg[1] }, + { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, IPR_USE_LSI, IPR_SIS32, &ipr_chip_cfg[1] } }; static int ipr_max_bus_speeds [] = { @@ -468,7 +468,10 @@ static void ipr_trc_hook(struct ipr_cmnd *ipr_cmd, trace_entry->time = jiffies; trace_entry->op_code = ipr_cmd->ioarcb.cmd_pkt.cdb[0]; trace_entry->type = type; - trace_entry->ata_op_code = ipr_cmd->ioarcb.add_data.u.regs.command; + if (ipr_cmd->ioa_cfg->sis64) + trace_entry->ata_op_code = ipr_cmd->i.ata_ioadl.regs.command; + else + trace_entry->ata_op_code = ipr_cmd->ioarcb.u.add_data.u.regs.command; trace_entry->cmd_index = ipr_cmd->cmd_index & 0xff; trace_entry->res_handle = ipr_cmd->ioarcb.res_handle; trace_entry->u.add_data = add_data; @@ -488,16 +491,23 @@ static void ipr_reinit_ipr_cmnd(struct ipr_cmnd *ipr_cmd) { struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; struct ipr_ioasa *ioasa = &ipr_cmd->ioasa; - dma_addr_t dma_addr = be32_to_cpu(ioarcb->ioarcb_host_pci_addr); + dma_addr_t dma_addr = ipr_cmd->dma_addr; memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt)); - ioarcb->write_data_transfer_length = 0; + ioarcb->data_transfer_length = 0; ioarcb->read_data_transfer_length = 0; - ioarcb->write_ioadl_len = 0; + ioarcb->ioadl_len = 0; ioarcb->read_ioadl_len = 0; - ioarcb->write_ioadl_addr = - cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, ioadl)); - ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr; + + if (ipr_cmd->ioa_cfg->sis64) + ioarcb->u.sis64_addr_data.data_ioadl_addr = + cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64)); + else { + ioarcb->write_ioadl_addr = + cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl)); + ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr; + } + ioasa->ioasc = 0; ioasa->residual_data_len = 0; ioasa->u.gata.status = 0; @@ -692,6 +702,35 @@ static void ipr_fail_all_ops(struct ipr_ioa_cfg *ioa_cfg) LEAVE; } +/** + * ipr_send_command - Send driver initiated requests. + * @ipr_cmd: ipr command struct + * + * This function sends a command to the adapter using the correct write call. + * In the case of sis64, calculate the ioarcb size required. Then or in the + * appropriate bits. + * + * Return value: + * none + **/ +static void ipr_send_command(struct ipr_cmnd *ipr_cmd) +{ + struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg; + dma_addr_t send_dma_addr = ipr_cmd->dma_addr; + + if (ioa_cfg->sis64) { + /* The default size is 256 bytes */ + send_dma_addr |= 0x1; + + /* If the number of ioadls * size of ioadl > 128 bytes, + then use a 512 byte ioarcb */ + if (ipr_cmd->dma_use_sg * sizeof(struct ipr_ioadl64_desc) > 128 ) + send_dma_addr |= 0x4; + writeq(send_dma_addr, ioa_cfg->regs.ioarrin_reg); + } else + writel(send_dma_addr, ioa_cfg->regs.ioarrin_reg); +} + /** * ipr_do_req - Send driver initiated requests. * @ipr_cmd: ipr command struct @@ -724,8 +763,8 @@ static void ipr_do_req(struct ipr_cmnd *ipr_cmd, ipr_trc_hook(ipr_cmd, IPR_TRACE_START, 0); mb(); - writel(be32_to_cpu(ipr_cmd->ioarcb.ioarcb_host_pci_addr), - ioa_cfg->regs.ioarrin_reg); + + ipr_send_command(ipr_cmd); } /** @@ -746,6 +785,51 @@ static void ipr_internal_cmd_done(struct ipr_cmnd *ipr_cmd) complete(&ipr_cmd->completion); } +/** + * ipr_init_ioadl - initialize the ioadl for the correct SIS type + * @ipr_cmd: ipr command struct + * @dma_addr: dma address + * @len: transfer length + * @flags: ioadl flag value + * + * This function initializes an ioadl in the case where there is only a single + * descriptor. + * + * Return value: + * nothing + **/ +static void ipr_init_ioadl(struct ipr_cmnd *ipr_cmd, dma_addr_t dma_addr, + u32 len, int flags) +{ + struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl; + struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64; + + ipr_cmd->dma_use_sg = 1; + + if (ipr_cmd->ioa_cfg->sis64) { + ioadl64->flags = cpu_to_be32(flags); + ioadl64->data_len = cpu_to_be32(len); + ioadl64->address = cpu_to_be64(dma_addr); + + ipr_cmd->ioarcb.ioadl_len = + cpu_to_be32(sizeof(struct ipr_ioadl64_desc)); + ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len); + } else { + ioadl->flags_and_data_len = cpu_to_be32(flags | len); + ioadl->address = cpu_to_be32(dma_addr); + + if (flags == IPR_IOADL_FLAGS_READ_LAST) { + ipr_cmd->ioarcb.read_ioadl_len = + cpu_to_be32(sizeof(struct ipr_ioadl_desc)); + ipr_cmd->ioarcb.read_data_transfer_length = cpu_to_be32(len); + } else { + ipr_cmd->ioarcb.ioadl_len = + cpu_to_be32(sizeof(struct ipr_ioadl_desc)); + ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len); + } + } +} + /** * ipr_send_blocking_cmd - Send command and sleep on its completion. * @ipr_cmd: ipr command struct @@ -803,11 +887,8 @@ static void ipr_send_hcam(struct ipr_ioa_cfg *ioa_cfg, u8 type, ioarcb->cmd_pkt.cdb[7] = (sizeof(hostrcb->hcam) >> 8) & 0xff; ioarcb->cmd_pkt.cdb[8] = sizeof(hostrcb->hcam) & 0xff; - ioarcb->read_data_transfer_length = cpu_to_be32(sizeof(hostrcb->hcam)); - ioarcb->read_ioadl_len = cpu_to_be32(sizeof(struct ipr_ioadl_desc)); - ipr_cmd->ioadl[0].flags_and_data_len = - cpu_to_be32(IPR_IOADL_FLAGS_READ_LAST | sizeof(hostrcb->hcam)); - ipr_cmd->ioadl[0].address = cpu_to_be32(hostrcb->hostrcb_dma); + ipr_init_ioadl(ipr_cmd, hostrcb->hostrcb_dma, + sizeof(hostrcb->hcam), IPR_IOADL_FLAGS_READ_LAST); if (type == IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE) ipr_cmd->done = ipr_process_ccn; @@ -817,8 +898,8 @@ static void ipr_send_hcam(struct ipr_ioa_cfg *ioa_cfg, u8 type, ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_IOA_RES_ADDR); mb(); - writel(be32_to_cpu(ipr_cmd->ioarcb.ioarcb_host_pci_addr), - ioa_cfg->regs.ioarrin_reg); + + ipr_send_command(ipr_cmd); } else { list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q); } @@ -2975,6 +3056,37 @@ static int ipr_copy_ucode_buffer(struct ipr_sglist *sglist, return result; } +/** + * ipr_build_ucode_ioadl64 - Build a microcode download IOADL + * @ipr_cmd: ipr command struct + * @sglist: scatter/gather list + * + * Builds a microcode download IOA data list (IOADL). + * + **/ +static void ipr_build_ucode_ioadl64(struct ipr_cmnd *ipr_cmd, + struct ipr_sglist *sglist) +{ + struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; + struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64; + struct scatterlist *scatterlist = sglist->scatterlist; + int i; + + ipr_cmd->dma_use_sg = sglist->num_dma_sg; + ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ; + ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len); + + ioarcb->ioadl_len = + cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg); + for (i = 0; i < ipr_cmd->dma_use_sg; i++) { + ioadl64[i].flags = cpu_to_be32(IPR_IOADL_FLAGS_WRITE); + ioadl64[i].data_len = cpu_to_be32(sg_dma_len(&scatterlist[i])); + ioadl64[i].address = cpu_to_be64(sg_dma_address(&scatterlist[i])); + } + + ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST); +} + /** * ipr_build_ucode_ioadl - Build a microcode download IOADL * @ipr_cmd: ipr command struct @@ -2987,14 +3099,15 @@ static void ipr_build_ucode_ioadl(struct ipr_cmnd *ipr_cmd, struct ipr_sglist *sglist) { struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; - struct ipr_ioadl_desc *ioadl = ipr_cmd->ioadl; + struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl; struct scatterlist *scatterlist = sglist->scatterlist; int i; ipr_cmd->dma_use_sg = sglist->num_dma_sg; ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ; - ioarcb->write_data_transfer_length = cpu_to_be32(sglist->buffer_len); - ioarcb->write_ioadl_len = + ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len); + + ioarcb->ioadl_len = cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg); for (i = 0; i < ipr_cmd->dma_use_sg; i++) { @@ -3828,14 +3941,19 @@ static int ipr_device_reset(struct ipr_ioa_cfg *ioa_cfg, ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg); ioarcb = &ipr_cmd->ioarcb; cmd_pkt = &ioarcb->cmd_pkt; - regs = &ioarcb->add_data.u.regs; + + if (ipr_cmd->ioa_cfg->sis64) { + regs = &ipr_cmd->i.ata_ioadl.regs; + ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb)); + } else + regs = &ioarcb->u.add_data.u.regs; ioarcb->res_handle = res->cfgte.res_handle; cmd_pkt->request_type = IPR_RQTYPE_IOACMD; cmd_pkt->cdb[0] = IPR_RESET_DEVICE; if (ipr_is_gata(res)) { cmd_pkt->cdb[2] = IPR_ATA_PHY_RESET; - ioarcb->add_cmd_parms_len = cpu_to_be32(sizeof(regs->flags)); + ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(regs->flags)); regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION; } @@ -4308,6 +4426,53 @@ static irqreturn_t ipr_isr(int irq, void *devp) return rc; } +/** + * ipr_build_ioadl64 - Build a scatter/gather list and map the buffer + * @ioa_cfg: ioa config struct + * @ipr_cmd: ipr command struct + * + * Return value: + * 0 on success / -1 on failure + **/ +static int ipr_build_ioadl64(struct ipr_ioa_cfg *ioa_cfg, + struct ipr_cmnd *ipr_cmd) +{ + int i, nseg; + struct scatterlist *sg; + u32 length; + u32 ioadl_flags = 0; + struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd; + struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; + struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64; + + length = scsi_bufflen(scsi_cmd); + if (!length) + return 0; + + nseg = scsi_dma_map(scsi_cmd); + if (nseg < 0) { + dev_err(&ioa_cfg->pdev->dev, "pci_map_sg failed!\n"); + return -1; + } + + ipr_cmd->dma_use_sg = nseg; + + if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) { + ioadl_flags = IPR_IOADL_FLAGS_WRITE; + ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ; + } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE) + ioadl_flags = IPR_IOADL_FLAGS_READ; + + scsi_for_each_sg(scsi_cmd, sg, ipr_cmd->dma_use_sg, i) { + ioadl64[i].flags = cpu_to_be32(ioadl_flags); + ioadl64[i].data_len = cpu_to_be32(sg_dma_len(sg)); + ioadl64[i].address = cpu_to_be64(sg_dma_address(sg)); + } + + ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST); + return 0; +} + /** * ipr_build_ioadl - Build a scatter/gather list and map the buffer * @ioa_cfg: ioa config struct @@ -4325,7 +4490,7 @@ static int ipr_build_ioadl(struct ipr_ioa_cfg *ioa_cfg, u32 ioadl_flags = 0; struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd; struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; - struct ipr_ioadl_desc *ioadl = ipr_cmd->ioadl; + struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl; length = scsi_bufflen(scsi_cmd); if (!length) @@ -4342,8 +4507,8 @@ static int ipr_build_ioadl(struct ipr_ioa_cfg *ioa_cfg, if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) { ioadl_flags = IPR_IOADL_FLAGS_WRITE; ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ; - ioarcb->write_data_transfer_length = cpu_to_be32(length); - ioarcb->write_ioadl_len = + ioarcb->data_transfer_length = cpu_to_be32(length); + ioarcb->ioadl_len = cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg); } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE) { ioadl_flags = IPR_IOADL_FLAGS_READ; @@ -4352,11 +4517,10 @@ static int ipr_build_ioadl(struct ipr_ioa_cfg *ioa_cfg, cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg); } - if (ipr_cmd->dma_use_sg <= ARRAY_SIZE(ioarcb->add_data.u.ioadl)) { - ioadl = ioarcb->add_data.u.ioadl; - ioarcb->write_ioadl_addr = - cpu_to_be32(be32_to_cpu(ioarcb->ioarcb_host_pci_addr) + - offsetof(struct ipr_ioarcb, add_data)); + if (ipr_cmd->dma_use_sg <= ARRAY_SIZE(ioarcb->u.add_data.u.ioadl)) { + ioadl = ioarcb->u.add_data.u.ioadl; + ioarcb->write_ioadl_addr = cpu_to_be32((ipr_cmd->dma_addr) + + offsetof(struct ipr_ioarcb, u.add_data)); ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr; } @@ -4446,18 +4610,24 @@ static void ipr_reinit_ipr_cmnd_for_erp(struct ipr_cmnd *ipr_cmd) { struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; struct ipr_ioasa *ioasa = &ipr_cmd->ioasa; - dma_addr_t dma_addr = be32_to_cpu(ioarcb->ioarcb_host_pci_addr); + dma_addr_t dma_addr = ipr_cmd->dma_addr; memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt)); - ioarcb->write_data_transfer_length = 0; + ioarcb->data_transfer_length = 0; ioarcb->read_data_transfer_length = 0; - ioarcb->write_ioadl_len = 0; + ioarcb->ioadl_len = 0; ioarcb->read_ioadl_len = 0; ioasa->ioasc = 0; ioasa->residual_data_len = 0; - ioarcb->write_ioadl_addr = - cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, ioadl)); - ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr; + + if (ipr_cmd->ioa_cfg->sis64) + ioarcb->u.sis64_addr_data.data_ioadl_addr = + cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64)); + else { + ioarcb->write_ioadl_addr = + cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl)); + ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr; + } } /** @@ -4489,15 +4659,8 @@ static void ipr_erp_request_sense(struct ipr_cmnd *ipr_cmd) cmd_pkt->flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK; cmd_pkt->timeout = cpu_to_be16(IPR_REQUEST_SENSE_TIMEOUT / HZ); - ipr_cmd->ioadl[0].flags_and_data_len = - cpu_to_be32(IPR_IOADL_FLAGS_READ_LAST | SCSI_SENSE_BUFFERSIZE); - ipr_cmd->ioadl[0].address = - cpu_to_be32(ipr_cmd->sense_buffer_dma); - - ipr_cmd->ioarcb.read_ioadl_len = - cpu_to_be32(sizeof(struct ipr_ioadl_desc)); - ipr_cmd->ioarcb.read_data_transfer_length = - cpu_to_be32(SCSI_SENSE_BUFFERSIZE); + ipr_init_ioadl(ipr_cmd, ipr_cmd->sense_buffer_dma, + SCSI_SENSE_BUFFERSIZE, IPR_IOADL_FLAGS_READ_LAST); ipr_do_req(ipr_cmd, ipr_erp_done, ipr_timeout, IPR_REQUEST_SENSE_TIMEOUT * 2); @@ -4916,13 +5079,16 @@ static int ipr_queuecommand(struct scsi_cmnd *scsi_cmd, (!ipr_is_gscsi(res) || scsi_cmd->cmnd[0] == IPR_QUERY_RSRC_STATE)) ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD; - if (likely(rc == 0)) - rc = ipr_build_ioadl(ioa_cfg, ipr_cmd); + if (likely(rc == 0)) { + if (ioa_cfg->sis64) + rc = ipr_build_ioadl64(ioa_cfg, ipr_cmd); + else + rc = ipr_build_ioadl(ioa_cfg, ipr_cmd); + } if (likely(rc == 0)) { mb(); - writel(be32_to_cpu(ipr_cmd->ioarcb.ioarcb_host_pci_addr), - ioa_cfg->regs.ioarrin_reg); + ipr_send_command(ipr_cmd); } else { list_move_tail(&ipr_cmd->queue, &ioa_cfg->free_q); return SCSI_MLQUEUE_HOST_BUSY; @@ -5145,6 +5311,52 @@ static void ipr_sata_done(struct ipr_cmnd *ipr_cmd) ata_qc_complete(qc); } +/** + * ipr_build_ata_ioadl64 - Build an ATA scatter/gather list + * @ipr_cmd: ipr command struct + * @qc: ATA queued command + * + **/ +static void ipr_build_ata_ioadl64(struct ipr_cmnd *ipr_cmd, + struct ata_queued_cmd *qc) +{ + u32 ioadl_flags = 0; + struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; + struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64; + struct ipr_ioadl64_desc *last_ioadl64 = NULL; + int len = qc->nbytes; + struct scatterlist *sg; + unsigned int si; + dma_addr_t dma_addr = ipr_cmd->dma_addr; + + if (len == 0) + return; + + if (qc->dma_dir == DMA_TO_DEVICE) { + ioadl_flags = IPR_IOADL_FLAGS_WRITE; + ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ; + } else if (qc->dma_dir == DMA_FROM_DEVICE) + ioadl_flags = IPR_IOADL_FLAGS_READ; + + ioarcb->data_transfer_length = cpu_to_be32(len); + ioarcb->ioadl_len = + cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg); + ioarcb->u.sis64_addr_data.data_ioadl_addr = + cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ata_ioadl)); + + for_each_sg(qc->sg, sg, qc->n_elem, si) { + ioadl64->flags = cpu_to_be32(ioadl_flags); + ioadl64->data_len = cpu_to_be32(sg_dma_len(sg)); + ioadl64->address = cpu_to_be64(sg_dma_address(sg)); + + last_ioadl64 = ioadl64; + ioadl64++; + } + + if (likely(last_ioadl64)) + last_ioadl64->flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST); +} + /** * ipr_build_ata_ioadl - Build an ATA scatter/gather list * @ipr_cmd: ipr command struct @@ -5156,7 +5368,7 @@ static void ipr_build_ata_ioadl(struct ipr_cmnd *ipr_cmd, { u32 ioadl_flags = 0; struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; - struct ipr_ioadl_desc *ioadl = ipr_cmd->ioadl; + struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl; struct ipr_ioadl_desc *last_ioadl = NULL; int len = qc->nbytes; struct scatterlist *sg; @@ -5168,8 +5380,8 @@ static void ipr_build_ata_ioadl(struct ipr_cmnd *ipr_cmd, if (qc->dma_dir == DMA_TO_DEVICE) { ioadl_flags = IPR_IOADL_FLAGS_WRITE; ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ; - ioarcb->write_data_transfer_length = cpu_to_be32(len); - ioarcb->write_ioadl_len = + ioarcb->data_transfer_length = cpu_to_be32(len); + ioarcb->ioadl_len = cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg); } else if (qc->dma_dir == DMA_FROM_DEVICE) { ioadl_flags = IPR_IOADL_FLAGS_READ; @@ -5212,10 +5424,15 @@ static unsigned int ipr_qc_issue(struct ata_queued_cmd *qc) ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg); ioarcb = &ipr_cmd->ioarcb; - regs = &ioarcb->add_data.u.regs; - memset(&ioarcb->add_data, 0, sizeof(ioarcb->add_data)); - ioarcb->add_cmd_parms_len = cpu_to_be32(sizeof(ioarcb->add_data.u.regs)); + if (ioa_cfg->sis64) { + regs = &ipr_cmd->i.ata_ioadl.regs; + ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb)); + } else + regs = &ioarcb->u.add_data.u.regs; + + memset(regs, 0, sizeof(*regs)); + ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(*regs)); list_add_tail(&ipr_cmd->queue, &ioa_cfg->pending_q); ipr_cmd->qc = qc; @@ -5226,7 +5443,11 @@ static unsigned int ipr_qc_issue(struct ata_queued_cmd *qc) ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK; ipr_cmd->dma_use_sg = qc->n_elem; - ipr_build_ata_ioadl(ipr_cmd, qc); + if (ioa_cfg->sis64) + ipr_build_ata_ioadl64(ipr_cmd, qc); + else + ipr_build_ata_ioadl(ipr_cmd, qc); + regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION; ipr_copy_sata_tf(regs, &qc->tf); memcpy(ioarcb->cmd_pkt.cdb, qc->cdb, IPR_MAX_CDB_LEN); @@ -5257,8 +5478,9 @@ static unsigned int ipr_qc_issue(struct ata_queued_cmd *qc) } mb(); - writel(be32_to_cpu(ioarcb->ioarcb_host_pci_addr), - ioa_cfg->regs.ioarrin_reg); + + ipr_send_command(ipr_cmd); + return 0; } @@ -5459,7 +5681,7 @@ static void ipr_set_sup_dev_dflt(struct ipr_supported_device *supported_dev, * ipr_set_supported_devs - Send Set Supported Devices for a device * @ipr_cmd: ipr command struct * - * This function send a Set Supported Devices to the adapter + * This function sends a Set Supported Devices to the adapter * * Return value: * IPR_RC_JOB_CONTINUE / IPR_RC_JOB_RETURN @@ -5468,7 +5690,6 @@ static int ipr_set_supported_devs(struct ipr_cmnd *ipr_cmd) { struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg; struct ipr_supported_device *supp_dev = &ioa_cfg->vpd_cbs->supp_dev; - struct ipr_ioadl_desc *ioadl = ipr_cmd->ioadl; struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; struct ipr_resource_entry *res = ipr_cmd->u.res; @@ -5489,13 +5710,11 @@ static int ipr_set_supported_devs(struct ipr_cmnd *ipr_cmd) ioarcb->cmd_pkt.cdb[7] = (sizeof(struct ipr_supported_device) >> 8) & 0xff; ioarcb->cmd_pkt.cdb[8] = sizeof(struct ipr_supported_device) & 0xff; - ioadl->flags_and_data_len = cpu_to_be32(IPR_IOADL_FLAGS_WRITE_LAST | - sizeof(struct ipr_supported_device)); - ioadl->address = cpu_to_be32(ioa_cfg->vpd_cbs_dma + - offsetof(struct ipr_misc_cbs, supp_dev)); - ioarcb->write_ioadl_len = cpu_to_be32(sizeof(struct ipr_ioadl_desc)); - ioarcb->write_data_transfer_length = - cpu_to_be32(sizeof(struct ipr_supported_device)); + ipr_init_ioadl(ipr_cmd, + ioa_cfg->vpd_cbs_dma + + offsetof(struct ipr_misc_cbs, supp_dev), + sizeof(struct ipr_supported_device), + IPR_IOADL_FLAGS_WRITE_LAST); ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_SET_SUP_DEVICE_TIMEOUT); @@ -5695,10 +5914,9 @@ static void ipr_modify_ioafp_mode_page_28(struct ipr_ioa_cfg *ioa_cfg, * none **/ static void ipr_build_mode_select(struct ipr_cmnd *ipr_cmd, - __be32 res_handle, u8 parm, u32 dma_addr, - u8 xfer_len) + __be32 res_handle, u8 parm, + dma_addr_t dma_addr, u8 xfer_len) { - struct ipr_ioadl_desc *ioadl = ipr_cmd->ioadl; struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; ioarcb->res_handle = res_handle; @@ -5708,11 +5926,7 @@ static void ipr_build_mode_select(struct ipr_cmnd *ipr_cmd, ioarcb->cmd_pkt.cdb[1] = parm; ioarcb->cmd_pkt.cdb[4] = xfer_len; - ioadl->flags_and_data_len = - cpu_to_be32(IPR_IOADL_FLAGS_WRITE_LAST | xfer_len); - ioadl->address = cpu_to_be32(dma_addr); - ioarcb->write_ioadl_len = cpu_to_be32(sizeof(struct ipr_ioadl_desc)); - ioarcb->write_data_transfer_length = cpu_to_be32(xfer_len); + ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_WRITE_LAST); } /** @@ -5762,9 +5976,8 @@ static int ipr_ioafp_mode_select_page28(struct ipr_cmnd *ipr_cmd) **/ static void ipr_build_mode_sense(struct ipr_cmnd *ipr_cmd, __be32 res_handle, - u8 parm, u32 dma_addr, u8 xfer_len) + u8 parm, dma_addr_t dma_addr, u8 xfer_len) { - struct ipr_ioadl_desc *ioadl = ipr_cmd->ioadl; struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; ioarcb->res_handle = res_handle; @@ -5773,11 +5986,7 @@ static void ipr_build_mode_sense(struct ipr_cmnd *ipr_cmd, ioarcb->cmd_pkt.cdb[4] = xfer_len; ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB; - ioadl->flags_and_data_len = - cpu_to_be32(IPR_IOADL_FLAGS_READ_LAST | xfer_len); - ioadl->address = cpu_to_be32(dma_addr); - ioarcb->read_ioadl_len = cpu_to_be32(sizeof(struct ipr_ioadl_desc)); - ioarcb->read_data_transfer_length = cpu_to_be32(xfer_len); + ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST); } /** @@ -6033,7 +6242,6 @@ static int ipr_ioafp_query_ioa_cfg(struct ipr_cmnd *ipr_cmd) { struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg; struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; - struct ipr_ioadl_desc *ioadl = ipr_cmd->ioadl; struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data; struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap; @@ -6050,13 +6258,9 @@ static int ipr_ioafp_query_ioa_cfg(struct ipr_cmnd *ipr_cmd) ioarcb->cmd_pkt.cdb[7] = (sizeof(struct ipr_config_table) >> 8) & 0xff; ioarcb->cmd_pkt.cdb[8] = sizeof(struct ipr_config_table) & 0xff; - ioarcb->read_ioadl_len = cpu_to_be32(sizeof(struct ipr_ioadl_desc)); - ioarcb->read_data_transfer_length = - cpu_to_be32(sizeof(struct ipr_config_table)); - - ioadl->address = cpu_to_be32(ioa_cfg->cfg_table_dma); - ioadl->flags_and_data_len = - cpu_to_be32(IPR_IOADL_FLAGS_READ_LAST | sizeof(struct ipr_config_table)); + ipr_init_ioadl(ipr_cmd, ioa_cfg->cfg_table_dma, + sizeof(struct ipr_config_table), + IPR_IOADL_FLAGS_READ_LAST); ipr_cmd->job_step = ipr_init_res_table; @@ -6076,10 +6280,9 @@ static int ipr_ioafp_query_ioa_cfg(struct ipr_cmnd *ipr_cmd) * none **/ static void ipr_ioafp_inquiry(struct ipr_cmnd *ipr_cmd, u8 flags, u8 page, - u32 dma_addr, u8 xfer_len) + dma_addr_t dma_addr, u8 xfer_len) { struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; - struct ipr_ioadl_desc *ioadl = ipr_cmd->ioadl; ENTER; ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB; @@ -6090,12 +6293,7 @@ static void ipr_ioafp_inquiry(struct ipr_cmnd *ipr_cmd, u8 flags, u8 page, ioarcb->cmd_pkt.cdb[2] = page; ioarcb->cmd_pkt.cdb[4] = xfer_len; - ioarcb->read_ioadl_len = cpu_to_be32(sizeof(struct ipr_ioadl_desc)); - ioarcb->read_data_transfer_length = cpu_to_be32(xfer_len); - - ioadl->address = cpu_to_be32(dma_addr); - ioadl->flags_and_data_len = - cpu_to_be32(IPR_IOADL_FLAGS_READ_LAST | xfer_len); + ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST); ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT); LEAVE; @@ -6785,7 +6983,10 @@ static int ipr_reset_ucode_download(struct ipr_cmnd *ipr_cmd) ipr_cmd->ioarcb.cmd_pkt.cdb[7] = (sglist->buffer_len & 0x00ff00) >> 8; ipr_cmd->ioarcb.cmd_pkt.cdb[8] = sglist->buffer_len & 0x0000ff; - ipr_build_ucode_ioadl(ipr_cmd, sglist); + if (ioa_cfg->sis64) + ipr_build_ucode_ioadl64(ipr_cmd, sglist); + else + ipr_build_ucode_ioadl(ipr_cmd, sglist); ipr_cmd->job_step = ipr_reset_ucode_download_done; ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, @@ -7209,7 +7410,7 @@ static int __devinit ipr_alloc_cmd_blks(struct ipr_ioa_cfg *ioa_cfg) int i; ioa_cfg->ipr_cmd_pool = pci_pool_create (IPR_NAME, ioa_cfg->pdev, - sizeof(struct ipr_cmnd), 8, 0); + sizeof(struct ipr_cmnd), 16, 0); if (!ioa_cfg->ipr_cmd_pool) return -ENOMEM; @@ -7227,13 +7428,25 @@ static int __devinit ipr_alloc_cmd_blks(struct ipr_ioa_cfg *ioa_cfg) ioa_cfg->ipr_cmnd_list_dma[i] = dma_addr; ioarcb = &ipr_cmd->ioarcb; - ioarcb->ioarcb_host_pci_addr = cpu_to_be32(dma_addr); + ipr_cmd->dma_addr = dma_addr; + if (ioa_cfg->sis64) + ioarcb->a.ioarcb_host_pci_addr64 = cpu_to_be64(dma_addr); + else + ioarcb->a.ioarcb_host_pci_addr = cpu_to_be32(dma_addr); + ioarcb->host_response_handle = cpu_to_be32(i << 2); - ioarcb->write_ioadl_addr = - cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, ioadl)); - ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr; - ioarcb->ioasa_host_pci_addr = - cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, ioasa)); + if (ioa_cfg->sis64) { + ioarcb->u.sis64_addr_data.data_ioadl_addr = + cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64)); + ioarcb->u.sis64_addr_data.ioasa_host_pci_addr = + cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, ioasa)); + } else { + ioarcb->write_ioadl_addr = + cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl)); + ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr; + ioarcb->ioasa_host_pci_addr = + cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, ioasa)); + } ioarcb->ioasa_len = cpu_to_be16(sizeof(struct ipr_ioasa)); ipr_cmd->cmd_index = i; ipr_cmd->ioa_cfg = ioa_cfg; @@ -7578,6 +7791,8 @@ static int __devinit ipr_probe_ioa(struct pci_dev *pdev, goto out_scsi_host_put; } + /* set SIS 32 or SIS 64 */ + ioa_cfg->sis64 = ioa_cfg->ipr_chip->sis_type == IPR_SIS64 ? 1 : 0; ioa_cfg->chip_cfg = ioa_cfg->ipr_chip->cfg; if (ipr_transop_timeout) @@ -7615,7 +7830,16 @@ static int __devinit ipr_probe_ioa(struct pci_dev *pdev, pci_set_master(pdev); - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + if (ioa_cfg->sis64) { + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); + if (rc < 0) { + dev_dbg(&pdev->dev, "Failed to set 64 bit PCI DMA mask\n"); + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + } + + } else + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + if (rc < 0) { dev_err(&pdev->dev, "Failed to set PCI DMA mask\n"); goto cleanup_nomem; diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h index 19bbcf39f0c9..64e41df2a196 100644 --- a/drivers/scsi/ipr.h +++ b/drivers/scsi/ipr.h @@ -381,7 +381,7 @@ struct ipr_cmd_pkt { #define IPR_RQTYPE_HCAM 0x02 #define IPR_RQTYPE_ATA_PASSTHRU 0x04 - u8 luntar_luntrn; + u8 reserved2; u8 flags_hi; #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80 @@ -403,7 +403,7 @@ struct ipr_cmd_pkt { __be16 timeout; }__attribute__ ((packed, aligned(4))); -struct ipr_ioarcb_ata_regs { +struct ipr_ioarcb_ata_regs { /* 22 bytes */ u8 flags; #define IPR_ATA_FLAG_PACKET_CMD 0x80 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40 @@ -442,28 +442,49 @@ struct ipr_ioadl_desc { __be32 address; }__attribute__((packed, aligned (8))); +struct ipr_ioadl64_desc { + __be32 flags; + __be32 data_len; + __be64 address; +}__attribute__((packed, aligned (16))); + +struct ipr_ata64_ioadl { + struct ipr_ioarcb_ata_regs regs; + u16 reserved[5]; + struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES]; +}__attribute__((packed, aligned (16))); + struct ipr_ioarcb_add_data { union { struct ipr_ioarcb_ata_regs regs; struct ipr_ioadl_desc ioadl[5]; __be32 add_cmd_parms[10]; - }u; -}__attribute__ ((packed, aligned(4))); + } u; +}__attribute__ ((packed, aligned (4))); + +struct ipr_ioarcb_sis64_add_addr_ecb { + __be64 ioasa_host_pci_addr; + __be64 data_ioadl_addr; + __be64 reserved; + __be32 ext_control_buf[4]; +}__attribute__((packed, aligned (8))); /* IOA Request Control Block 128 bytes */ struct ipr_ioarcb { - __be32 ioarcb_host_pci_addr; - __be32 reserved; + union { + __be32 ioarcb_host_pci_addr; + __be64 ioarcb_host_pci_addr64; + } a; __be32 res_handle; __be32 host_response_handle; __be32 reserved1; __be32 reserved2; __be32 reserved3; - __be32 write_data_transfer_length; + __be32 data_transfer_length; __be32 read_data_transfer_length; __be32 write_ioadl_addr; - __be32 write_ioadl_len; + __be32 ioadl_len; __be32 read_ioadl_addr; __be32 read_ioadl_len; @@ -473,8 +494,14 @@ struct ipr_ioarcb { struct ipr_cmd_pkt cmd_pkt; - __be32 add_cmd_parms_len; - struct ipr_ioarcb_add_data add_data; + __be16 add_cmd_parms_offset; + __be16 add_cmd_parms_len; + + union { + struct ipr_ioarcb_add_data add_data; + struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data; + } u; + }__attribute__((packed, aligned (4))); struct ipr_ioasa_vset { @@ -1029,6 +1056,9 @@ struct ipr_chip_t { u16 intr_type; #define IPR_USE_LSI 0x00 #define IPR_USE_MSI 0x01 + u16 sis_type; +#define IPR_SIS32 0x00 +#define IPR_SIS64 0x01 const struct ipr_chip_cfg_t *cfg; }; @@ -1099,6 +1129,7 @@ struct ipr_ioa_cfg { u8 dual_raid:1; u8 needs_warm_reset:1; u8 msi_received:1; + u8 sis64:1; u8 revid; @@ -1202,13 +1233,17 @@ struct ipr_ioa_cfg { char ipr_cmd_label[8]; #define IPR_CMD_LABEL "ipr_cmd" struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS]; - u32 ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS]; + dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS]; }; struct ipr_cmnd { struct ipr_ioarcb ioarcb; + union { + struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES]; + struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES]; + struct ipr_ata64_ioadl ata_ioadl; + } i; struct ipr_ioasa ioasa; - struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES]; struct list_head queue; struct scsi_cmnd *scsi_cmd; struct ata_queued_cmd *qc; @@ -1221,7 +1256,7 @@ struct ipr_cmnd { u8 sense_buffer[SCSI_SENSE_BUFFERSIZE]; dma_addr_t sense_buffer_dma; unsigned short dma_use_sg; - dma_addr_t dma_handle; + dma_addr_t dma_addr; struct ipr_cmnd *sibling; union { enum ipr_shutdown_type shutdown_type; -- cgit v1.2.3 From a74c16390a47dcb6c96b20b572ffc9936073d4b1 Mon Sep 17 00:00:00 2001 From: Wayne Boyer Date: Fri, 19 Feb 2010 13:23:51 -0800 Subject: [SCSI] ipr: define new offsets to registers for the next generation chip This patch adds the entry to the ipr_chip_cfg array that defines the register offsets for the next generation 64 bit IOA PCI interface chip. Signed-off-by: Wayne Boyer Signed-off-by: James Bottomley --- drivers/scsi/ipr.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers') diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index 359882eadc26..e6bab3fb6945 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -128,6 +128,21 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = { .clr_uproc_interrupt_reg = 0x00294 } }, + { /* CRoC */ + .mailbox = 0x00040, + .cache_line_size = 0x20, + { + .set_interrupt_mask_reg = 0x00010, + .clr_interrupt_mask_reg = 0x00018, + .sense_interrupt_mask_reg = 0x00010, + .clr_interrupt_reg = 0x00008, + .sense_interrupt_reg = 0x00000, + .ioarrin_reg = 0x00070, + .sense_uproc_interrupt_reg = 0x00020, + .set_uproc_interrupt_reg = 0x00020, + .clr_uproc_interrupt_reg = 0x00028 + } + }, }; static const struct ipr_chip_t ipr_chip[] = { -- cgit v1.2.3 From 3e7ebdfa58ddaef361f9538219e66a7226fb1e5d Mon Sep 17 00:00:00 2001 From: Wayne Boyer Date: Fri, 19 Feb 2010 13:23:59 -0800 Subject: [SCSI] ipr: update the configuration table code for the next generation chip This patch changes the configuration table structures and related code such that both 32 bit and 64 bit based adapters can work with the driver. This patch also implements the code to generate the virtual bus/id/lun values for devices connected to the new adapters. It also implements support for the new device resource path. Signed-off-by: Wayne Boyer Signed-off-by: James Bottomley --- drivers/scsi/ipr.c | 512 +++++++++++++++++++++++++++++++++++++++++++---------- drivers/scsi/ipr.h | 174 ++++++++++++------ 2 files changed, 538 insertions(+), 148 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index e6bab3fb6945..91e330a12721 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -72,6 +72,7 @@ #include #include #include +#include #include #include #include @@ -93,6 +94,7 @@ static unsigned int ipr_fastfail = 0; static unsigned int ipr_transop_timeout = 0; static unsigned int ipr_enable_cache = 1; static unsigned int ipr_debug = 0; +static unsigned int ipr_max_devs = IPR_DEFAULT_SIS64_DEVS; static unsigned int ipr_dual_ioa_raid = 1; static DEFINE_SPINLOCK(ipr_driver_lock); @@ -177,6 +179,9 @@ module_param_named(debug, ipr_debug, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(debug, "Enable device driver debugging logging. Set to 1 to enable. (default: 0)"); module_param_named(dual_ioa_raid, ipr_dual_ioa_raid, int, 0); MODULE_PARM_DESC(dual_ioa_raid, "Enable dual adapter RAID support. Set to 1 to enable. (default: 1)"); +module_param_named(max_devs, ipr_max_devs, int, 0); +MODULE_PARM_DESC(max_devs, "Specify the maximum number of physical devices. " + "[Default=" __stringify(IPR_DEFAULT_SIS64_DEVS) "]"); MODULE_LICENSE("GPL"); MODULE_VERSION(IPR_DRIVER_VERSION); @@ -920,15 +925,47 @@ static void ipr_send_hcam(struct ipr_ioa_cfg *ioa_cfg, u8 type, } } +/** + * ipr_update_ata_class - Update the ata class in the resource entry + * @res: resource entry struct + * @proto: cfgte device bus protocol value + * + * Return value: + * none + **/ +static void ipr_update_ata_class(struct ipr_resource_entry *res, unsigned int proto) +{ + switch(proto) { + case IPR_PROTO_SATA: + case IPR_PROTO_SAS_STP: + res->ata_class = ATA_DEV_ATA; + break; + case IPR_PROTO_SATA_ATAPI: + case IPR_PROTO_SAS_STP_ATAPI: + res->ata_class = ATA_DEV_ATAPI; + break; + default: + res->ata_class = ATA_DEV_UNKNOWN; + break; + }; +} + /** * ipr_init_res_entry - Initialize a resource entry struct. * @res: resource entry struct + * @cfgtew: config table entry wrapper struct * * Return value: * none **/ -static void ipr_init_res_entry(struct ipr_resource_entry *res) +static void ipr_init_res_entry(struct ipr_resource_entry *res, + struct ipr_config_table_entry_wrapper *cfgtew) { + int found = 0; + unsigned int proto; + struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg; + struct ipr_resource_entry *gscsi_res = NULL; + res->needs_sync_complete = 0; res->in_erp = 0; res->add_to_ml = 0; @@ -936,6 +973,205 @@ static void ipr_init_res_entry(struct ipr_resource_entry *res) res->resetting_device = 0; res->sdev = NULL; res->sata_port = NULL; + + if (ioa_cfg->sis64) { + proto = cfgtew->u.cfgte64->proto; + res->res_flags = cfgtew->u.cfgte64->res_flags; + res->qmodel = IPR_QUEUEING_MODEL64(res); + res->type = cfgtew->u.cfgte64->res_type & 0x0f; + + memcpy(res->res_path, &cfgtew->u.cfgte64->res_path, + sizeof(res->res_path)); + + res->bus = 0; + res->lun = scsilun_to_int(&res->dev_lun); + + if (res->type == IPR_RES_TYPE_GENERIC_SCSI) { + list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue) { + if (gscsi_res->dev_id == cfgtew->u.cfgte64->dev_id) { + found = 1; + res->target = gscsi_res->target; + break; + } + } + if (!found) { + res->target = find_first_zero_bit(ioa_cfg->target_ids, + ioa_cfg->max_devs_supported); + set_bit(res->target, ioa_cfg->target_ids); + } + + memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun, + sizeof(res->dev_lun.scsi_lun)); + } else if (res->type == IPR_RES_TYPE_IOAFP) { + res->bus = IPR_IOAFP_VIRTUAL_BUS; + res->target = 0; + } else if (res->type == IPR_RES_TYPE_ARRAY) { + res->bus = IPR_ARRAY_VIRTUAL_BUS; + res->target = find_first_zero_bit(ioa_cfg->array_ids, + ioa_cfg->max_devs_supported); + set_bit(res->target, ioa_cfg->array_ids); + } else if (res->type == IPR_RES_TYPE_VOLUME_SET) { + res->bus = IPR_VSET_VIRTUAL_BUS; + res->target = find_first_zero_bit(ioa_cfg->vset_ids, + ioa_cfg->max_devs_supported); + set_bit(res->target, ioa_cfg->vset_ids); + } else { + res->target = find_first_zero_bit(ioa_cfg->target_ids, + ioa_cfg->max_devs_supported); + set_bit(res->target, ioa_cfg->target_ids); + } + } else { + proto = cfgtew->u.cfgte->proto; + res->qmodel = IPR_QUEUEING_MODEL(res); + res->flags = cfgtew->u.cfgte->flags; + if (res->flags & IPR_IS_IOA_RESOURCE) + res->type = IPR_RES_TYPE_IOAFP; + else + res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f; + + res->bus = cfgtew->u.cfgte->res_addr.bus; + res->target = cfgtew->u.cfgte->res_addr.target; + res->lun = cfgtew->u.cfgte->res_addr.lun; + } + + ipr_update_ata_class(res, proto); +} + +/** + * ipr_is_same_device - Determine if two devices are the same. + * @res: resource entry struct + * @cfgtew: config table entry wrapper struct + * + * Return value: + * 1 if the devices are the same / 0 otherwise + **/ +static int ipr_is_same_device(struct ipr_resource_entry *res, + struct ipr_config_table_entry_wrapper *cfgtew) +{ + if (res->ioa_cfg->sis64) { + if (!memcmp(&res->dev_id, &cfgtew->u.cfgte64->dev_id, + sizeof(cfgtew->u.cfgte64->dev_id)) && + !memcmp(&res->lun, &cfgtew->u.cfgte64->lun, + sizeof(cfgtew->u.cfgte64->lun))) { + return 1; + } + } else { + if (res->bus == cfgtew->u.cfgte->res_addr.bus && + res->target == cfgtew->u.cfgte->res_addr.target && + res->lun == cfgtew->u.cfgte->res_addr.lun) + return 1; + } + + return 0; +} + +/** + * ipr_format_resource_path - Format the resource path for printing. + * @res_path: resource path + * @buf: buffer + * + * Return value: + * pointer to buffer + **/ +static char *ipr_format_resource_path(u8 *res_path, char *buffer) +{ + int i; + + sprintf(buffer, "%02X", res_path[0]); + for (i=1; res_path[i] != 0xff; i++) + sprintf(buffer, "%s:%02X", buffer, res_path[i]); + + return buffer; +} + +/** + * ipr_update_res_entry - Update the resource entry. + * @res: resource entry struct + * @cfgtew: config table entry wrapper struct + * + * Return value: + * none + **/ +static void ipr_update_res_entry(struct ipr_resource_entry *res, + struct ipr_config_table_entry_wrapper *cfgtew) +{ + char buffer[IPR_MAX_RES_PATH_LENGTH]; + unsigned int proto; + int new_path = 0; + + if (res->ioa_cfg->sis64) { + res->flags = cfgtew->u.cfgte64->flags; + res->res_flags = cfgtew->u.cfgte64->res_flags; + res->type = cfgtew->u.cfgte64->res_type & 0x0f; + + memcpy(&res->std_inq_data, &cfgtew->u.cfgte64->std_inq_data, + sizeof(struct ipr_std_inq_data)); + + res->qmodel = IPR_QUEUEING_MODEL64(res); + proto = cfgtew->u.cfgte64->proto; + res->res_handle = cfgtew->u.cfgte64->res_handle; + res->dev_id = cfgtew->u.cfgte64->dev_id; + + memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun, + sizeof(res->dev_lun.scsi_lun)); + + if (memcmp(res->res_path, &cfgtew->u.cfgte64->res_path, + sizeof(res->res_path))) { + memcpy(res->res_path, &cfgtew->u.cfgte64->res_path, + sizeof(res->res_path)); + new_path = 1; + } + + if (res->sdev && new_path) + sdev_printk(KERN_INFO, res->sdev, "Resource path: %s\n", + ipr_format_resource_path(&res->res_path[0], &buffer[0])); + } else { + res->flags = cfgtew->u.cfgte->flags; + if (res->flags & IPR_IS_IOA_RESOURCE) + res->type = IPR_RES_TYPE_IOAFP; + else + res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f; + + memcpy(&res->std_inq_data, &cfgtew->u.cfgte->std_inq_data, + sizeof(struct ipr_std_inq_data)); + + res->qmodel = IPR_QUEUEING_MODEL(res); + proto = cfgtew->u.cfgte->proto; + res->res_handle = cfgtew->u.cfgte->res_handle; + } + + ipr_update_ata_class(res, proto); +} + +/** + * ipr_clear_res_target - Clear the bit in the bit map representing the target + * for the resource. + * @res: resource entry struct + * @cfgtew: config table entry wrapper struct + * + * Return value: + * none + **/ +static void ipr_clear_res_target(struct ipr_resource_entry *res) +{ + struct ipr_resource_entry *gscsi_res = NULL; + struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg; + + if (!ioa_cfg->sis64) + return; + + if (res->bus == IPR_ARRAY_VIRTUAL_BUS) + clear_bit(res->target, ioa_cfg->array_ids); + else if (res->bus == IPR_VSET_VIRTUAL_BUS) + clear_bit(res->target, ioa_cfg->vset_ids); + else if (res->bus == 0 && res->type == IPR_RES_TYPE_GENERIC_SCSI) { + list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue) + if (gscsi_res->dev_id == res->dev_id && gscsi_res != res) + return; + clear_bit(res->target, ioa_cfg->target_ids); + + } else if (res->bus == 0) + clear_bit(res->target, ioa_cfg->target_ids); } /** @@ -947,17 +1183,24 @@ static void ipr_init_res_entry(struct ipr_resource_entry *res) * none **/ static void ipr_handle_config_change(struct ipr_ioa_cfg *ioa_cfg, - struct ipr_hostrcb *hostrcb) + struct ipr_hostrcb *hostrcb) { struct ipr_resource_entry *res = NULL; - struct ipr_config_table_entry *cfgte; + struct ipr_config_table_entry_wrapper cfgtew; + __be32 cc_res_handle; + u32 is_ndn = 1; - cfgte = &hostrcb->hcam.u.ccn.cfgte; + if (ioa_cfg->sis64) { + cfgtew.u.cfgte64 = &hostrcb->hcam.u.ccn.u.cfgte64; + cc_res_handle = cfgtew.u.cfgte64->res_handle; + } else { + cfgtew.u.cfgte = &hostrcb->hcam.u.ccn.u.cfgte; + cc_res_handle = cfgtew.u.cfgte->res_handle; + } list_for_each_entry(res, &ioa_cfg->used_res_q, queue) { - if (!memcmp(&res->cfgte.res_addr, &cfgte->res_addr, - sizeof(cfgte->res_addr))) { + if (res->res_handle == cc_res_handle) { is_ndn = 0; break; } @@ -975,20 +1218,22 @@ static void ipr_handle_config_change(struct ipr_ioa_cfg *ioa_cfg, struct ipr_resource_entry, queue); list_del(&res->queue); - ipr_init_res_entry(res); + ipr_init_res_entry(res, &cfgtew); list_add_tail(&res->queue, &ioa_cfg->used_res_q); } - memcpy(&res->cfgte, cfgte, sizeof(struct ipr_config_table_entry)); + ipr_update_res_entry(res, &cfgtew); if (hostrcb->hcam.notify_type == IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY) { if (res->sdev) { res->del_from_ml = 1; - res->cfgte.res_handle = IPR_INVALID_RES_HANDLE; + res->res_handle = IPR_INVALID_RES_HANDLE; if (ioa_cfg->allow_ml_add_del) schedule_work(&ioa_cfg->work_q); - } else + } else { + ipr_clear_res_target(res); list_move_tail(&res->queue, &ioa_cfg->free_res_q); + } } else if (!res->sdev) { res->add_to_ml = 1; if (ioa_cfg->allow_ml_add_del) @@ -1941,12 +2186,14 @@ static const struct ipr_ses_table_entry * ipr_find_ses_entry(struct ipr_resource_entry *res) { int i, j, matches; + struct ipr_std_inq_vpids *vpids; const struct ipr_ses_table_entry *ste = ipr_ses_table; for (i = 0; i < ARRAY_SIZE(ipr_ses_table); i++, ste++) { for (j = 0, matches = 0; j < IPR_PROD_ID_LEN; j++) { if (ste->compare_product_id_byte[j] == 'X') { - if (res->cfgte.std_inq_data.vpids.product_id[j] == ste->product_id[j]) + vpids = &res->std_inq_data.vpids; + if (vpids->product_id[j] == ste->product_id[j]) matches++; else break; @@ -1981,10 +2228,10 @@ static u32 ipr_get_max_scsi_speed(struct ipr_ioa_cfg *ioa_cfg, u8 bus, u8 bus_wi /* Loop through each config table entry in the config table buffer */ list_for_each_entry(res, &ioa_cfg->used_res_q, queue) { - if (!(IPR_IS_SES_DEVICE(res->cfgte.std_inq_data))) + if (!(IPR_IS_SES_DEVICE(res->std_inq_data))) continue; - if (bus != res->cfgte.res_addr.bus) + if (bus != res->bus) continue; if (!(ste = ipr_find_ses_entry(res))) @@ -2518,9 +2765,9 @@ restart: list_for_each_entry(res, &ioa_cfg->used_res_q, queue) { if (res->add_to_ml) { - bus = res->cfgte.res_addr.bus; - target = res->cfgte.res_addr.target; - lun = res->cfgte.res_addr.lun; + bus = res->bus; + target = res->target; + lun = res->lun; res->add_to_ml = 0; spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); scsi_add_device(ioa_cfg->host, bus, target, lun); @@ -3578,7 +3825,7 @@ static ssize_t ipr_show_adapter_handle(struct device *dev, struct device_attribu spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags); res = (struct ipr_resource_entry *)sdev->hostdata; if (res) - len = snprintf(buf, PAGE_SIZE, "%08X\n", res->cfgte.res_handle); + len = snprintf(buf, PAGE_SIZE, "%08X\n", res->res_handle); spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); return len; } @@ -3591,8 +3838,43 @@ static struct device_attribute ipr_adapter_handle_attr = { .show = ipr_show_adapter_handle }; +/** + * ipr_show_resource_path - Show the resource path for this device. + * @dev: device struct + * @buf: buffer + * + * Return value: + * number of bytes printed to buffer + **/ +static ssize_t ipr_show_resource_path(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct scsi_device *sdev = to_scsi_device(dev); + struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata; + struct ipr_resource_entry *res; + unsigned long lock_flags = 0; + ssize_t len = -ENXIO; + char buffer[IPR_MAX_RES_PATH_LENGTH]; + + spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags); + res = (struct ipr_resource_entry *)sdev->hostdata; + if (res) + len = snprintf(buf, PAGE_SIZE, "%s\n", + ipr_format_resource_path(&res->res_path[0], &buffer[0])); + spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); + return len; +} + +static struct device_attribute ipr_resource_path_attr = { + .attr = { + .name = "resource_path", + .mode = S_IRUSR, + }, + .show = ipr_show_resource_path +}; + static struct device_attribute *ipr_dev_attrs[] = { &ipr_adapter_handle_attr, + &ipr_resource_path_attr, NULL, }; @@ -3645,9 +3927,9 @@ static struct ipr_resource_entry *ipr_find_starget(struct scsi_target *starget) struct ipr_resource_entry *res; list_for_each_entry(res, &ioa_cfg->used_res_q, queue) { - if ((res->cfgte.res_addr.bus == starget->channel) && - (res->cfgte.res_addr.target == starget->id) && - (res->cfgte.res_addr.lun == 0)) { + if ((res->bus == starget->channel) && + (res->target == starget->id) && + (res->lun == 0)) { return res; } } @@ -3717,6 +3999,17 @@ static int ipr_target_alloc(struct scsi_target *starget) static void ipr_target_destroy(struct scsi_target *starget) { struct ipr_sata_port *sata_port = starget->hostdata; + struct Scsi_Host *shost = dev_to_shost(&starget->dev); + struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata; + + if (ioa_cfg->sis64) { + if (starget->channel == IPR_ARRAY_VIRTUAL_BUS) + clear_bit(starget->id, ioa_cfg->array_ids); + else if (starget->channel == IPR_VSET_VIRTUAL_BUS) + clear_bit(starget->id, ioa_cfg->vset_ids); + else if (starget->channel == 0) + clear_bit(starget->id, ioa_cfg->target_ids); + } if (sata_port) { starget->hostdata = NULL; @@ -3738,9 +4031,9 @@ static struct ipr_resource_entry *ipr_find_sdev(struct scsi_device *sdev) struct ipr_resource_entry *res; list_for_each_entry(res, &ioa_cfg->used_res_q, queue) { - if ((res->cfgte.res_addr.bus == sdev->channel) && - (res->cfgte.res_addr.target == sdev->id) && - (res->cfgte.res_addr.lun == sdev->lun)) + if ((res->bus == sdev->channel) && + (res->target == sdev->id) && + (res->lun == sdev->lun)) return res; } @@ -3789,6 +4082,7 @@ static int ipr_slave_configure(struct scsi_device *sdev) struct ipr_resource_entry *res; struct ata_port *ap = NULL; unsigned long lock_flags = 0; + char buffer[IPR_MAX_RES_PATH_LENGTH]; spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags); res = sdev->hostdata; @@ -3815,6 +4109,9 @@ static int ipr_slave_configure(struct scsi_device *sdev) ata_sas_slave_configure(sdev, ap); } else scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun); + if (ioa_cfg->sis64) + sdev_printk(KERN_INFO, sdev, "Resource path: %s\n", + ipr_format_resource_path(&res->res_path[0], &buffer[0])); return 0; } spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); @@ -3963,7 +4260,7 @@ static int ipr_device_reset(struct ipr_ioa_cfg *ioa_cfg, } else regs = &ioarcb->u.add_data.u.regs; - ioarcb->res_handle = res->cfgte.res_handle; + ioarcb->res_handle = res->res_handle; cmd_pkt->request_type = IPR_RQTYPE_IOACMD; cmd_pkt->cdb[0] = IPR_RESET_DEVICE; if (ipr_is_gata(res)) { @@ -4013,19 +4310,7 @@ static int ipr_sata_reset(struct ata_link *link, unsigned int *classes, res = sata_port->res; if (res) { rc = ipr_device_reset(ioa_cfg, res); - switch(res->cfgte.proto) { - case IPR_PROTO_SATA: - case IPR_PROTO_SAS_STP: - *classes = ATA_DEV_ATA; - break; - case IPR_PROTO_SATA_ATAPI: - case IPR_PROTO_SAS_STP_ATAPI: - *classes = ATA_DEV_ATAPI; - break; - default: - *classes = ATA_DEV_UNKNOWN; - break; - }; + *classes = res->ata_class; } spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); @@ -4070,7 +4355,7 @@ static int __ipr_eh_dev_reset(struct scsi_cmnd * scsi_cmd) return FAILED; list_for_each_entry(ipr_cmd, &ioa_cfg->pending_q, queue) { - if (ipr_cmd->ioarcb.res_handle == res->cfgte.res_handle) { + if (ipr_cmd->ioarcb.res_handle == res->res_handle) { if (ipr_cmd->scsi_cmd) ipr_cmd->done = ipr_scsi_eh_done; if (ipr_cmd->qc) @@ -4092,7 +4377,7 @@ static int __ipr_eh_dev_reset(struct scsi_cmnd * scsi_cmd) spin_lock_irq(scsi_cmd->device->host->host_lock); list_for_each_entry(ipr_cmd, &ioa_cfg->pending_q, queue) { - if (ipr_cmd->ioarcb.res_handle == res->cfgte.res_handle) { + if (ipr_cmd->ioarcb.res_handle == res->res_handle) { rc = -EIO; break; } @@ -4131,13 +4416,13 @@ static void ipr_bus_reset_done(struct ipr_cmnd *ipr_cmd) struct ipr_resource_entry *res; ENTER; - list_for_each_entry(res, &ioa_cfg->used_res_q, queue) { - if (!memcmp(&res->cfgte.res_handle, &ipr_cmd->ioarcb.res_handle, - sizeof(res->cfgte.res_handle))) { - scsi_report_bus_reset(ioa_cfg->host, res->cfgte.res_addr.bus); - break; + if (!ioa_cfg->sis64) + list_for_each_entry(res, &ioa_cfg->used_res_q, queue) { + if (res->res_handle == ipr_cmd->ioarcb.res_handle) { + scsi_report_bus_reset(ioa_cfg->host, res->bus); + break; + } } - } /* * If abort has not completed, indicate the reset has, else call the @@ -4235,7 +4520,7 @@ static int ipr_cancel_op(struct scsi_cmnd * scsi_cmd) return SUCCESS; ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg); - ipr_cmd->ioarcb.res_handle = res->cfgte.res_handle; + ipr_cmd->ioarcb.res_handle = res->res_handle; cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt; cmd_pkt->request_type = IPR_RQTYPE_IOACMD; cmd_pkt->cdb[0] = IPR_CANCEL_ALL_REQUESTS; @@ -5071,9 +5356,9 @@ static int ipr_queuecommand(struct scsi_cmnd *scsi_cmd, memcpy(ioarcb->cmd_pkt.cdb, scsi_cmd->cmnd, scsi_cmd->cmd_len); ipr_cmd->scsi_cmd = scsi_cmd; - ioarcb->res_handle = res->cfgte.res_handle; + ioarcb->res_handle = res->res_handle; ipr_cmd->done = ipr_scsi_done; - ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_PHYS_LOC(res->cfgte.res_addr)); + ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res)); if (ipr_is_gscsi(res) || ipr_is_vset_device(res)) { if (scsi_cmd->underflow == 0) @@ -5216,20 +5501,9 @@ static void ipr_ata_phy_reset(struct ata_port *ap) goto out_unlock; } - switch(res->cfgte.proto) { - case IPR_PROTO_SATA: - case IPR_PROTO_SAS_STP: - ap->link.device[0].class = ATA_DEV_ATA; - break; - case IPR_PROTO_SATA_ATAPI: - case IPR_PROTO_SAS_STP_ATAPI: - ap->link.device[0].class = ATA_DEV_ATAPI; - break; - default: - ap->link.device[0].class = ATA_DEV_UNKNOWN; + ap->link.device[0].class = res->ata_class; + if (ap->link.device[0].class == ATA_DEV_UNKNOWN) ata_port_disable(ap); - break; - }; out_unlock: spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags); @@ -5315,8 +5589,7 @@ static void ipr_sata_done(struct ipr_cmnd *ipr_cmd) ipr_dump_ioasa(ioa_cfg, ipr_cmd, res); if (be32_to_cpu(ipr_cmd->ioasa.ioasc_specific) & IPR_ATA_DEVICE_WAS_RESET) - scsi_report_device_reset(ioa_cfg->host, res->cfgte.res_addr.bus, - res->cfgte.res_addr.target); + scsi_report_device_reset(ioa_cfg->host, res->bus, res->target); if (IPR_IOASC_SENSE_KEY(ioasc) > RECOVERED_ERROR) qc->err_mask |= __ac_err_mask(ipr_cmd->ioasa.u.gata.status); @@ -5452,7 +5725,7 @@ static unsigned int ipr_qc_issue(struct ata_queued_cmd *qc) list_add_tail(&ipr_cmd->queue, &ioa_cfg->pending_q); ipr_cmd->qc = qc; ipr_cmd->done = ipr_sata_done; - ipr_cmd->ioarcb.res_handle = res->cfgte.res_handle; + ipr_cmd->ioarcb.res_handle = res->res_handle; ioarcb->cmd_pkt.request_type = IPR_RQTYPE_ATA_PASSTHRU; ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC; ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK; @@ -5466,7 +5739,7 @@ static unsigned int ipr_qc_issue(struct ata_queued_cmd *qc) regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION; ipr_copy_sata_tf(regs, &qc->tf); memcpy(ioarcb->cmd_pkt.cdb, qc->cdb, IPR_MAX_CDB_LEN); - ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_PHYS_LOC(res->cfgte.res_addr)); + ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res)); switch (qc->tf.protocol) { case ATA_PROT_NODATA: @@ -5715,13 +5988,14 @@ static int ipr_set_supported_devs(struct ipr_cmnd *ipr_cmd) continue; ipr_cmd->u.res = res; - ipr_set_sup_dev_dflt(supp_dev, &res->cfgte.std_inq_data.vpids); + ipr_set_sup_dev_dflt(supp_dev, &res->std_inq_data.vpids); ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE); ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ; ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD; ioarcb->cmd_pkt.cdb[0] = IPR_SET_SUPPORTED_DEVICES; + ioarcb->cmd_pkt.cdb[1] = IPR_SET_ALL_SUPPORTED_DEVICES; ioarcb->cmd_pkt.cdb[7] = (sizeof(struct ipr_supported_device) >> 8) & 0xff; ioarcb->cmd_pkt.cdb[8] = sizeof(struct ipr_supported_device) & 0xff; @@ -5734,7 +6008,8 @@ static int ipr_set_supported_devs(struct ipr_cmnd *ipr_cmd) ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_SET_SUP_DEVICE_TIMEOUT); - ipr_cmd->job_step = ipr_set_supported_devs; + if (!ioa_cfg->sis64) + ipr_cmd->job_step = ipr_set_supported_devs; return IPR_RC_JOB_RETURN; } @@ -6182,24 +6457,36 @@ static int ipr_init_res_table(struct ipr_cmnd *ipr_cmd) { struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg; struct ipr_resource_entry *res, *temp; - struct ipr_config_table_entry *cfgte; - int found, i; + struct ipr_config_table_entry_wrapper cfgtew; + int entries, found, flag, i; LIST_HEAD(old_res); ENTER; - if (ioa_cfg->cfg_table->hdr.flags & IPR_UCODE_DOWNLOAD_REQ) + if (ioa_cfg->sis64) + flag = ioa_cfg->u.cfg_table64->hdr64.flags; + else + flag = ioa_cfg->u.cfg_table->hdr.flags; + + if (flag & IPR_UCODE_DOWNLOAD_REQ) dev_err(&ioa_cfg->pdev->dev, "Microcode download required\n"); list_for_each_entry_safe(res, temp, &ioa_cfg->used_res_q, queue) list_move_tail(&res->queue, &old_res); - for (i = 0; i < ioa_cfg->cfg_table->hdr.num_entries; i++) { - cfgte = &ioa_cfg->cfg_table->dev[i]; + if (ioa_cfg->sis64) + entries = ioa_cfg->u.cfg_table64->hdr64.num_entries; + else + entries = ioa_cfg->u.cfg_table->hdr.num_entries; + + for (i = 0; i < entries; i++) { + if (ioa_cfg->sis64) + cfgtew.u.cfgte64 = &ioa_cfg->u.cfg_table64->dev[i]; + else + cfgtew.u.cfgte = &ioa_cfg->u.cfg_table->dev[i]; found = 0; list_for_each_entry_safe(res, temp, &old_res, queue) { - if (!memcmp(&res->cfgte.res_addr, - &cfgte->res_addr, sizeof(cfgte->res_addr))) { + if (ipr_is_same_device(res, &cfgtew)) { list_move_tail(&res->queue, &ioa_cfg->used_res_q); found = 1; break; @@ -6216,24 +6503,27 @@ static int ipr_init_res_table(struct ipr_cmnd *ipr_cmd) res = list_entry(ioa_cfg->free_res_q.next, struct ipr_resource_entry, queue); list_move_tail(&res->queue, &ioa_cfg->used_res_q); - ipr_init_res_entry(res); + ipr_init_res_entry(res, &cfgtew); res->add_to_ml = 1; } if (found) - memcpy(&res->cfgte, cfgte, sizeof(struct ipr_config_table_entry)); + ipr_update_res_entry(res, &cfgtew); } list_for_each_entry_safe(res, temp, &old_res, queue) { if (res->sdev) { res->del_from_ml = 1; - res->cfgte.res_handle = IPR_INVALID_RES_HANDLE; + res->res_handle = IPR_INVALID_RES_HANDLE; list_move_tail(&res->queue, &ioa_cfg->used_res_q); - } else { - list_move_tail(&res->queue, &ioa_cfg->free_res_q); } } + list_for_each_entry_safe(res, temp, &old_res, queue) { + ipr_clear_res_target(res); + list_move_tail(&res->queue, &ioa_cfg->free_res_q); + } + if (ioa_cfg->dual_raid && ipr_dual_ioa_raid) ipr_cmd->job_step = ipr_ioafp_mode_sense_page24; else @@ -6270,11 +6560,10 @@ static int ipr_ioafp_query_ioa_cfg(struct ipr_cmnd *ipr_cmd) ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE); ioarcb->cmd_pkt.cdb[0] = IPR_QUERY_IOA_CONFIG; - ioarcb->cmd_pkt.cdb[7] = (sizeof(struct ipr_config_table) >> 8) & 0xff; - ioarcb->cmd_pkt.cdb[8] = sizeof(struct ipr_config_table) & 0xff; + ioarcb->cmd_pkt.cdb[7] = (ioa_cfg->cfg_table_size >> 8) & 0xff; + ioarcb->cmd_pkt.cdb[8] = ioa_cfg->cfg_table_size & 0xff; - ipr_init_ioadl(ipr_cmd, ioa_cfg->cfg_table_dma, - sizeof(struct ipr_config_table), + ipr_init_ioadl(ipr_cmd, ioa_cfg->cfg_table_dma, ioa_cfg->cfg_table_size, IPR_IOADL_FLAGS_READ_LAST); ipr_cmd->job_step = ipr_init_res_table; @@ -6567,7 +6856,7 @@ static void ipr_init_ioa_mem(struct ipr_ioa_cfg *ioa_cfg) ioa_cfg->toggle_bit = 1; /* Zero out config table */ - memset(ioa_cfg->cfg_table, 0, sizeof(struct ipr_config_table)); + memset(ioa_cfg->u.cfg_table, 0, ioa_cfg->cfg_table_size); } /** @@ -7370,8 +7659,8 @@ static void ipr_free_mem(struct ipr_ioa_cfg *ioa_cfg) ipr_free_cmd_blks(ioa_cfg); pci_free_consistent(ioa_cfg->pdev, sizeof(u32) * IPR_NUM_CMD_BLKS, ioa_cfg->host_rrq, ioa_cfg->host_rrq_dma); - pci_free_consistent(ioa_cfg->pdev, sizeof(struct ipr_config_table), - ioa_cfg->cfg_table, + pci_free_consistent(ioa_cfg->pdev, ioa_cfg->cfg_table_size, + ioa_cfg->u.cfg_table, ioa_cfg->cfg_table_dma); for (i = 0; i < IPR_NUM_HCAMS; i++) { @@ -7488,13 +7777,24 @@ static int __devinit ipr_alloc_mem(struct ipr_ioa_cfg *ioa_cfg) ENTER; ioa_cfg->res_entries = kzalloc(sizeof(struct ipr_resource_entry) * - IPR_MAX_PHYSICAL_DEVS, GFP_KERNEL); + ioa_cfg->max_devs_supported, GFP_KERNEL); if (!ioa_cfg->res_entries) goto out; - for (i = 0; i < IPR_MAX_PHYSICAL_DEVS; i++) + if (ioa_cfg->sis64) { + ioa_cfg->target_ids = kzalloc(sizeof(unsigned long) * + BITS_TO_LONGS(ioa_cfg->max_devs_supported), GFP_KERNEL); + ioa_cfg->array_ids = kzalloc(sizeof(unsigned long) * + BITS_TO_LONGS(ioa_cfg->max_devs_supported), GFP_KERNEL); + ioa_cfg->vset_ids = kzalloc(sizeof(unsigned long) * + BITS_TO_LONGS(ioa_cfg->max_devs_supported), GFP_KERNEL); + } + + for (i = 0; i < ioa_cfg->max_devs_supported; i++) { list_add_tail(&ioa_cfg->res_entries[i].queue, &ioa_cfg->free_res_q); + ioa_cfg->res_entries[i].ioa_cfg = ioa_cfg; + } ioa_cfg->vpd_cbs = pci_alloc_consistent(ioa_cfg->pdev, sizeof(struct ipr_misc_cbs), @@ -7513,11 +7813,11 @@ static int __devinit ipr_alloc_mem(struct ipr_ioa_cfg *ioa_cfg) if (!ioa_cfg->host_rrq) goto out_ipr_free_cmd_blocks; - ioa_cfg->cfg_table = pci_alloc_consistent(ioa_cfg->pdev, - sizeof(struct ipr_config_table), - &ioa_cfg->cfg_table_dma); + ioa_cfg->u.cfg_table = pci_alloc_consistent(ioa_cfg->pdev, + ioa_cfg->cfg_table_size, + &ioa_cfg->cfg_table_dma); - if (!ioa_cfg->cfg_table) + if (!ioa_cfg->u.cfg_table) goto out_free_host_rrq; for (i = 0; i < IPR_NUM_HCAMS; i++) { @@ -7551,8 +7851,9 @@ out_free_hostrcb_dma: ioa_cfg->hostrcb[i], ioa_cfg->hostrcb_dma[i]); } - pci_free_consistent(pdev, sizeof(struct ipr_config_table), - ioa_cfg->cfg_table, ioa_cfg->cfg_table_dma); + pci_free_consistent(pdev, ioa_cfg->cfg_table_size, + ioa_cfg->u.cfg_table, + ioa_cfg->cfg_table_dma); out_free_host_rrq: pci_free_consistent(pdev, sizeof(u32) * IPR_NUM_CMD_BLKS, ioa_cfg->host_rrq, ioa_cfg->host_rrq_dma); @@ -7633,9 +7934,19 @@ static void __devinit ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg, ioa_cfg->cache_state = CACHE_DISABLED; ipr_initialize_bus_attr(ioa_cfg); + ioa_cfg->max_devs_supported = ipr_max_devs; - host->max_id = IPR_MAX_NUM_TARGETS_PER_BUS; - host->max_lun = IPR_MAX_NUM_LUNS_PER_TARGET; + if (ioa_cfg->sis64) { + host->max_id = IPR_MAX_SIS64_TARGETS_PER_BUS; + host->max_lun = IPR_MAX_SIS64_LUNS_PER_TARGET; + if (ipr_max_devs > IPR_MAX_SIS64_DEVS) + ioa_cfg->max_devs_supported = IPR_MAX_SIS64_DEVS; + } else { + host->max_id = IPR_MAX_NUM_TARGETS_PER_BUS; + host->max_lun = IPR_MAX_NUM_LUNS_PER_TARGET; + if (ipr_max_devs > IPR_MAX_PHYSICAL_DEVS) + ioa_cfg->max_devs_supported = IPR_MAX_PHYSICAL_DEVS; + } host->max_channel = IPR_MAX_BUS_TO_SCAN; host->unique_id = host->host_no; host->max_cmd_len = IPR_MAX_CDB_LEN; @@ -7896,6 +8207,15 @@ static int __devinit ipr_probe_ioa(struct pci_dev *pdev, if ((rc = ipr_set_pcix_cmd_reg(ioa_cfg))) goto cleanup_nomem; + if (ioa_cfg->sis64) + ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr64) + + ((sizeof(struct ipr_config_table_entry64) + * ioa_cfg->max_devs_supported))); + else + ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr) + + ((sizeof(struct ipr_config_table_entry) + * ioa_cfg->max_devs_supported))); + rc = ipr_alloc_mem(ioa_cfg); if (rc < 0) { dev_err(&pdev->dev, diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h index 64e41df2a196..f10c57b3d215 100644 --- a/drivers/scsi/ipr.h +++ b/drivers/scsi/ipr.h @@ -118,6 +118,10 @@ #define IPR_NUM_LOG_HCAMS 2 #define IPR_NUM_CFG_CHG_HCAMS 2 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS) + +#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024 +#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff + #define IPR_MAX_NUM_TARGETS_PER_BUS 256 #define IPR_MAX_NUM_LUNS_PER_TARGET 256 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8 @@ -139,6 +143,8 @@ IPR_NUM_INTERNAL_CMD_BLKS) #define IPR_MAX_PHYSICAL_DEVS 192 +#define IPR_DEFAULT_SIS64_DEVS 1024 +#define IPR_MAX_SIS64_DEVS 4096 #define IPR_MAX_SGLIST 64 #define IPR_IOA_MAX_SECTORS 32767 @@ -173,6 +179,7 @@ #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02 #define IPR_SET_SUPPORTED_DEVICES 0xFB +#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80 #define IPR_IOA_SHUTDOWN 0xF7 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05 @@ -318,27 +325,27 @@ struct ipr_std_inq_data { u8 serial_num[IPR_SERIAL_NUM_LEN]; }__attribute__ ((packed)); +#define IPR_RES_TYPE_AF_DASD 0x00 +#define IPR_RES_TYPE_GENERIC_SCSI 0x01 +#define IPR_RES_TYPE_VOLUME_SET 0x02 +#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03 +#define IPR_RES_TYPE_GENERIC_ATA 0x04 +#define IPR_RES_TYPE_ARRAY 0x05 +#define IPR_RES_TYPE_IOAFP 0xff + struct ipr_config_table_entry { u8 proto; #define IPR_PROTO_SATA 0x02 #define IPR_PROTO_SATA_ATAPI 0x03 #define IPR_PROTO_SAS_STP 0x06 -#define IPR_PROTO_SAS_STP_ATAPI 0x07 +#define IPR_PROTO_SAS_STP_ATAPI 0x07 u8 array_id; u8 flags; -#define IPR_IS_IOA_RESOURCE 0x80 -#define IPR_IS_ARRAY_MEMBER 0x20 -#define IPR_IS_HOT_SPARE 0x10 - +#define IPR_IS_IOA_RESOURCE 0x80 u8 rsvd_subtype; -#define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f) -#define IPR_SUBTYPE_AF_DASD 0 -#define IPR_SUBTYPE_GENERIC_SCSI 1 -#define IPR_SUBTYPE_VOLUME_SET 2 -#define IPR_SUBTYPE_GENERIC_ATA 4 - -#define IPR_QUEUEING_MODEL(res) ((((res)->cfgte.flags) & 0x70) >> 4) -#define IPR_QUEUE_FROZEN_MODEL 0 + +#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4) +#define IPR_QUEUE_FROZEN_MODEL 0 #define IPR_QUEUE_NACA_MODEL 1 struct ipr_res_addr res_addr; @@ -347,6 +354,28 @@ struct ipr_config_table_entry { struct ipr_std_inq_data std_inq_data; }__attribute__ ((packed, aligned (4))); +struct ipr_config_table_entry64 { + u8 res_type; + u8 proto; + u8 vset_num; + u8 array_id; + __be16 flags; + __be16 res_flags; +#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12) + __be32 res_handle; + u8 dev_id_type; + u8 reserved[3]; + __be64 dev_id; + __be64 lun; + __be64 lun_wwn[2]; +#define IPR_MAX_RES_PATH_LENGTH 24 + __be64 res_path; + struct ipr_std_inq_data std_inq_data; + u8 reserved2[4]; + __be64 reserved3[2]; // description text + u8 reserved4[8]; +}__attribute__ ((packed, aligned (8))); + struct ipr_config_table_hdr { u8 num_entries; u8 flags; @@ -354,13 +383,35 @@ struct ipr_config_table_hdr { __be16 reserved; }__attribute__((packed, aligned (4))); +struct ipr_config_table_hdr64 { + __be16 num_entries; + __be16 reserved; + u8 flags; + u8 reserved2[11]; +}__attribute__((packed, aligned (4))); + struct ipr_config_table { struct ipr_config_table_hdr hdr; - struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS]; + struct ipr_config_table_entry dev[0]; }__attribute__((packed, aligned (4))); +struct ipr_config_table64 { + struct ipr_config_table_hdr64 hdr64; + struct ipr_config_table_entry64 dev[0]; +}__attribute__((packed, aligned (8))); + +struct ipr_config_table_entry_wrapper { + union { + struct ipr_config_table_entry *cfgte; + struct ipr_config_table_entry64 *cfgte64; + } u; +}; + struct ipr_hostrcb_cfg_ch_not { - struct ipr_config_table_entry cfgte; + union { + struct ipr_config_table_entry cfgte; + struct ipr_config_table_entry64 cfgte64; + } u; u8 reserved[936]; }__attribute__((packed, aligned (4))); @@ -987,28 +1038,48 @@ struct ipr_sata_port { }; struct ipr_resource_entry { - struct ipr_config_table_entry cfgte; u8 needs_sync_complete:1; u8 in_erp:1; u8 add_to_ml:1; u8 del_from_ml:1; u8 resetting_device:1; + u32 bus; /* AKA channel */ + u32 target; /* AKA id */ + u32 lun; +#define IPR_ARRAY_VIRTUAL_BUS 0x1 +#define IPR_VSET_VIRTUAL_BUS 0x2 +#define IPR_IOAFP_VIRTUAL_BUS 0x3 + +#define IPR_GET_RES_PHYS_LOC(res) \ + (((res)->bus << 24) | ((res)->target << 8) | (res)->lun) + + u8 ata_class; + + u8 flags; + __be16 res_flags; + + __be32 type; + + u8 qmodel; + struct ipr_std_inq_data std_inq_data; + + __be32 res_handle; + __be64 dev_id; + struct scsi_lun dev_lun; + u8 res_path[8]; + + struct ipr_ioa_cfg *ioa_cfg; struct scsi_device *sdev; struct ipr_sata_port *sata_port; struct list_head queue; -}; +}; /* struct ipr_resource_entry */ struct ipr_resource_hdr { u16 num_entries; u16 reserved; }; -struct ipr_resource_table { - struct ipr_resource_hdr hdr; - struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS]; -}; - struct ipr_misc_cbs { struct ipr_ioa_vpd ioa_vpd; struct ipr_inquiry_page0 page0_data; @@ -1133,6 +1204,13 @@ struct ipr_ioa_cfg { u8 revid; + /* + * Bitmaps for SIS64 generated target values + */ + unsigned long *target_ids; + unsigned long *array_ids; + unsigned long *vset_ids; + enum ipr_cache_state cache_state; u16 type; /* CCIN of the card */ @@ -1164,8 +1242,13 @@ struct ipr_ioa_cfg { char cfg_table_start[8]; #define IPR_CFG_TBL_START "cfg" - struct ipr_config_table *cfg_table; + union { + struct ipr_config_table *cfg_table; + struct ipr_config_table64 *cfg_table64; + } u; dma_addr_t cfg_table_dma; + u32 cfg_table_size; + u32 max_devs_supported; char resource_table_label[8]; #define IPR_RES_TABLE_LABEL "res_tbl" @@ -1234,7 +1317,7 @@ struct ipr_ioa_cfg { #define IPR_CMD_LABEL "ipr_cmd" struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS]; dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS]; -}; +}; /* struct ipr_ioa_cfg */ struct ipr_cmnd { struct ipr_ioarcb ioarcb; @@ -1412,6 +1495,13 @@ struct ipr_ucode_image_header { #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__) #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)) +#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \ + printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ + bus, target, lun, ##__VA_ARGS__) + +#define ipr_res_err(ioa_cfg, res, fmt, ...) \ + ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__) + #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \ printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__) @@ -1419,9 +1509,6 @@ struct ipr_ucode_image_header { #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \ ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__) -#define ipr_res_err(ioa_cfg, res, fmt, ...) \ - ipr_ra_err(ioa_cfg, (res)->cfgte.res_addr, fmt, ##__VA_ARGS__) - #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \ { \ if ((res).bus >= IPR_MAX_NUM_BUSES) { \ @@ -1467,7 +1554,7 @@ ipr_err("----------------------------------------------------------\n") **/ static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res) { - return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0; + return res->type == IPR_RES_TYPE_IOAFP; } /** @@ -1479,12 +1566,8 @@ static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res) **/ static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res) { - if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) && - !ipr_is_ioa_resource(res) && - IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD) - return 1; - else - return 0; + return res->type == IPR_RES_TYPE_AF_DASD || + res->type == IPR_RES_TYPE_REMOTE_AF_DASD; } /** @@ -1496,12 +1579,7 @@ static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res) **/ static inline int ipr_is_vset_device(struct ipr_resource_entry *res) { - if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) && - !ipr_is_ioa_resource(res) && - IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET) - return 1; - else - return 0; + return res->type == IPR_RES_TYPE_VOLUME_SET; } /** @@ -1513,11 +1591,7 @@ static inline int ipr_is_vset_device(struct ipr_resource_entry *res) **/ static inline int ipr_is_gscsi(struct ipr_resource_entry *res) { - if (!ipr_is_ioa_resource(res) && - IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI) - return 1; - else - return 0; + return res->type == IPR_RES_TYPE_GENERIC_SCSI; } /** @@ -1530,7 +1604,7 @@ static inline int ipr_is_gscsi(struct ipr_resource_entry *res) static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res) { if (ipr_is_af_dasd_device(res) || - (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data))) + (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data))) return 1; else return 0; @@ -1545,11 +1619,7 @@ static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res) **/ static inline int ipr_is_gata(struct ipr_resource_entry *res) { - if (!ipr_is_ioa_resource(res) && - IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_ATA) - return 1; - else - return 0; + return res->type == IPR_RES_TYPE_GENERIC_ATA; } /** @@ -1561,7 +1631,7 @@ static inline int ipr_is_gata(struct ipr_resource_entry *res) **/ static inline int ipr_is_naca_model(struct ipr_resource_entry *res) { - if (ipr_is_gscsi(res) && IPR_QUEUEING_MODEL(res) == IPR_QUEUE_NACA_MODEL) + if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL) return 1; return 0; } -- cgit v1.2.3 From 4565e3706329f65b5e64328b5369c53b6ab2715c Mon Sep 17 00:00:00 2001 From: Wayne Boyer Date: Fri, 19 Feb 2010 13:24:07 -0800 Subject: [SCSI] ipr: add error handling updates for the next generation chip Add support for the new log data notification and overlay IDs. Signed-off-by: Wayne Boyer Signed-off-by: James Bottomley --- drivers/scsi/ipr.c | 257 ++++++++++++++++++++++++++++++++++++++++++++++++++--- drivers/scsi/ipr.h | 160 +++++++++++++++++++++++++++++---- 2 files changed, 388 insertions(+), 29 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index 91e330a12721..b2e60bd4a0c6 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -1079,7 +1079,7 @@ static char *ipr_format_resource_path(u8 *res_path, char *buffer) sprintf(buffer, "%02X", res_path[0]); for (i=1; res_path[i] != 0xff; i++) - sprintf(buffer, "%s:%02X", buffer, res_path[i]); + sprintf(buffer, "%s-%02X", buffer, res_path[i]); return buffer; } @@ -1385,8 +1385,12 @@ static void ipr_log_ext_vpd(struct ipr_ext_vpd *vpd) static void ipr_log_enhanced_cache_error(struct ipr_ioa_cfg *ioa_cfg, struct ipr_hostrcb *hostrcb) { - struct ipr_hostrcb_type_12_error *error = - &hostrcb->hcam.u.error.u.type_12_error; + struct ipr_hostrcb_type_12_error *error; + + if (ioa_cfg->sis64) + error = &hostrcb->hcam.u.error64.u.type_12_error; + else + error = &hostrcb->hcam.u.error.u.type_12_error; ipr_err("-----Current Configuration-----\n"); ipr_err("Cache Directory Card Information:\n"); @@ -1478,6 +1482,48 @@ static void ipr_log_enhanced_config_error(struct ipr_ioa_cfg *ioa_cfg, } } +/** + * ipr_log_sis64_config_error - Log a device error. + * @ioa_cfg: ioa config struct + * @hostrcb: hostrcb struct + * + * Return value: + * none + **/ +static void ipr_log_sis64_config_error(struct ipr_ioa_cfg *ioa_cfg, + struct ipr_hostrcb *hostrcb) +{ + int errors_logged, i; + struct ipr_hostrcb64_device_data_entry_enhanced *dev_entry; + struct ipr_hostrcb_type_23_error *error; + char buffer[IPR_MAX_RES_PATH_LENGTH]; + + error = &hostrcb->hcam.u.error64.u.type_23_error; + errors_logged = be32_to_cpu(error->errors_logged); + + ipr_err("Device Errors Detected/Logged: %d/%d\n", + be32_to_cpu(error->errors_detected), errors_logged); + + dev_entry = error->dev; + + for (i = 0; i < errors_logged; i++, dev_entry++) { + ipr_err_separator; + + ipr_err("Device %d : %s", i + 1, + ipr_format_resource_path(&dev_entry->res_path[0], &buffer[0])); + ipr_log_ext_vpd(&dev_entry->vpd); + + ipr_err("-----New Device Information-----\n"); + ipr_log_ext_vpd(&dev_entry->new_vpd); + + ipr_err("Cache Directory Card Information:\n"); + ipr_log_ext_vpd(&dev_entry->ioa_last_with_dev_vpd); + + ipr_err("Adapter Card Information:\n"); + ipr_log_ext_vpd(&dev_entry->cfc_last_with_dev_vpd); + } +} + /** * ipr_log_config_error - Log a configuration error. * @ioa_cfg: ioa config struct @@ -1672,7 +1718,11 @@ static void ipr_log_enhanced_dual_ioa_error(struct ipr_ioa_cfg *ioa_cfg, { struct ipr_hostrcb_type_17_error *error; - error = &hostrcb->hcam.u.error.u.type_17_error; + if (ioa_cfg->sis64) + error = &hostrcb->hcam.u.error64.u.type_17_error; + else + error = &hostrcb->hcam.u.error.u.type_17_error; + error->failure_reason[sizeof(error->failure_reason) - 1] = '\0'; strim(error->failure_reason); @@ -1779,6 +1829,42 @@ static void ipr_log_fabric_path(struct ipr_hostrcb *hostrcb, fabric->ioa_port, fabric->cascaded_expander, fabric->phy); } +/** + * ipr_log64_fabric_path - Log a fabric path error + * @hostrcb: hostrcb struct + * @fabric: fabric descriptor + * + * Return value: + * none + **/ +static void ipr_log64_fabric_path(struct ipr_hostrcb *hostrcb, + struct ipr_hostrcb64_fabric_desc *fabric) +{ + int i, j; + u8 path_state = fabric->path_state; + u8 active = path_state & IPR_PATH_ACTIVE_MASK; + u8 state = path_state & IPR_PATH_STATE_MASK; + char buffer[IPR_MAX_RES_PATH_LENGTH]; + + for (i = 0; i < ARRAY_SIZE(path_active_desc); i++) { + if (path_active_desc[i].active != active) + continue; + + for (j = 0; j < ARRAY_SIZE(path_state_desc); j++) { + if (path_state_desc[j].state != state) + continue; + + ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s\n", + path_active_desc[i].desc, path_state_desc[j].desc, + ipr_format_resource_path(&fabric->res_path[0], &buffer[0])); + return; + } + } + + ipr_err("Path state=%02X Resource Path=%s\n", path_state, + ipr_format_resource_path(&fabric->res_path[0], &buffer[0])); +} + static const struct { u8 type; char *desc; @@ -1887,6 +1973,49 @@ static void ipr_log_path_elem(struct ipr_hostrcb *hostrcb, be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1])); } +/** + * ipr_log64_path_elem - Log a fabric path element. + * @hostrcb: hostrcb struct + * @cfg: fabric path element struct + * + * Return value: + * none + **/ +static void ipr_log64_path_elem(struct ipr_hostrcb *hostrcb, + struct ipr_hostrcb64_config_element *cfg) +{ + int i, j; + u8 desc_id = cfg->descriptor_id & IPR_DESCRIPTOR_MASK; + u8 type = cfg->type_status & IPR_PATH_CFG_TYPE_MASK; + u8 status = cfg->type_status & IPR_PATH_CFG_STATUS_MASK; + char buffer[IPR_MAX_RES_PATH_LENGTH]; + + if (type == IPR_PATH_CFG_NOT_EXIST || desc_id != IPR_DESCRIPTOR_SIS64) + return; + + for (i = 0; i < ARRAY_SIZE(path_type_desc); i++) { + if (path_type_desc[i].type != type) + continue; + + for (j = 0; j < ARRAY_SIZE(path_status_desc); j++) { + if (path_status_desc[j].status != status) + continue; + + ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s, Link rate=%s, WWN=%08X%08X\n", + path_status_desc[j].desc, path_type_desc[i].desc, + ipr_format_resource_path(&cfg->res_path[0], &buffer[0]), + link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK], + be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1])); + return; + } + } + ipr_hcam_err(hostrcb, "Path element=%02X: Resource Path=%s, Link rate=%s " + "WWN=%08X%08X\n", cfg->type_status, + ipr_format_resource_path(&cfg->res_path[0], &buffer[0]), + link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK], + be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1])); +} + /** * ipr_log_fabric_error - Log a fabric error. * @ioa_cfg: ioa config struct @@ -1924,6 +2053,96 @@ static void ipr_log_fabric_error(struct ipr_ioa_cfg *ioa_cfg, ipr_log_hex_data(ioa_cfg, (u32 *)fabric, add_len); } +/** + * ipr_log_sis64_array_error - Log a sis64 array error. + * @ioa_cfg: ioa config struct + * @hostrcb: hostrcb struct + * + * Return value: + * none + **/ +static void ipr_log_sis64_array_error(struct ipr_ioa_cfg *ioa_cfg, + struct ipr_hostrcb *hostrcb) +{ + int i, num_entries; + struct ipr_hostrcb_type_24_error *error; + struct ipr_hostrcb64_array_data_entry *array_entry; + char buffer[IPR_MAX_RES_PATH_LENGTH]; + const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' }; + + error = &hostrcb->hcam.u.error64.u.type_24_error; + + ipr_err_separator; + + ipr_err("RAID %s Array Configuration: %s\n", + error->protection_level, + ipr_format_resource_path(&error->last_res_path[0], &buffer[0])); + + ipr_err_separator; + + array_entry = error->array_member; + num_entries = min_t(u32, be32_to_cpu(error->num_entries), + sizeof(error->array_member)); + + for (i = 0; i < num_entries; i++, array_entry++) { + + if (!memcmp(array_entry->vpd.vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN)) + continue; + + if (error->exposed_mode_adn == i) + ipr_err("Exposed Array Member %d:\n", i); + else + ipr_err("Array Member %d:\n", i); + + ipr_err("Array Member %d:\n", i); + ipr_log_ext_vpd(&array_entry->vpd); + ipr_err("Current Location: %s", + ipr_format_resource_path(&array_entry->res_path[0], &buffer[0])); + ipr_err("Expected Location: %s", + ipr_format_resource_path(&array_entry->expected_res_path[0], &buffer[0])); + + ipr_err_separator; + } +} + +/** + * ipr_log_sis64_fabric_error - Log a sis64 fabric error. + * @ioa_cfg: ioa config struct + * @hostrcb: hostrcb struct + * + * Return value: + * none + **/ +static void ipr_log_sis64_fabric_error(struct ipr_ioa_cfg *ioa_cfg, + struct ipr_hostrcb *hostrcb) +{ + struct ipr_hostrcb_type_30_error *error; + struct ipr_hostrcb64_fabric_desc *fabric; + struct ipr_hostrcb64_config_element *cfg; + int i, add_len; + + error = &hostrcb->hcam.u.error64.u.type_30_error; + + error->failure_reason[sizeof(error->failure_reason) - 1] = '\0'; + ipr_hcam_err(hostrcb, "%s\n", error->failure_reason); + + add_len = be32_to_cpu(hostrcb->hcam.length) - + (offsetof(struct ipr_hostrcb64_error, u) + + offsetof(struct ipr_hostrcb_type_30_error, desc)); + + for (i = 0, fabric = error->desc; i < error->num_entries; i++) { + ipr_log64_fabric_path(hostrcb, fabric); + for_each_fabric_cfg(fabric, cfg) + ipr_log64_path_elem(hostrcb, cfg); + + add_len -= be16_to_cpu(fabric->length); + fabric = (struct ipr_hostrcb64_fabric_desc *) + ((unsigned long)fabric + be16_to_cpu(fabric->length)); + } + + ipr_log_hex_data(ioa_cfg, (u32 *)fabric, add_len); +} + /** * ipr_log_generic_error - Log an adapter error. * @ioa_cfg: ioa config struct @@ -1983,13 +2202,16 @@ static void ipr_handle_log_data(struct ipr_ioa_cfg *ioa_cfg, if (hostrcb->hcam.notifications_lost == IPR_HOST_RCB_NOTIFICATIONS_LOST) dev_err(&ioa_cfg->pdev->dev, "Error notifications lost\n"); - ioasc = be32_to_cpu(hostrcb->hcam.u.error.failing_dev_ioasc); + if (ioa_cfg->sis64) + ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc); + else + ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc); - if (ioasc == IPR_IOASC_BUS_WAS_RESET || - ioasc == IPR_IOASC_BUS_WAS_RESET_BY_OTHER) { + if (!ioa_cfg->sis64 && (ioasc == IPR_IOASC_BUS_WAS_RESET || + ioasc == IPR_IOASC_BUS_WAS_RESET_BY_OTHER)) { /* Tell the midlayer we had a bus reset so it will handle the UA properly */ scsi_report_bus_reset(ioa_cfg->host, - hostrcb->hcam.u.error.failing_dev_res_addr.bus); + hostrcb->hcam.u.error.fd_res_addr.bus); } error_index = ipr_get_error(ioasc); @@ -2037,6 +2259,16 @@ static void ipr_handle_log_data(struct ipr_ioa_cfg *ioa_cfg, case IPR_HOST_RCB_OVERLAY_ID_20: ipr_log_fabric_error(ioa_cfg, hostrcb); break; + case IPR_HOST_RCB_OVERLAY_ID_23: + ipr_log_sis64_config_error(ioa_cfg, hostrcb); + break; + case IPR_HOST_RCB_OVERLAY_ID_24: + case IPR_HOST_RCB_OVERLAY_ID_26: + ipr_log_sis64_array_error(ioa_cfg, hostrcb); + break; + case IPR_HOST_RCB_OVERLAY_ID_30: + ipr_log_sis64_fabric_error(ioa_cfg, hostrcb); + break; case IPR_HOST_RCB_OVERLAY_ID_1: case IPR_HOST_RCB_OVERLAY_ID_DEFAULT: default: @@ -2061,7 +2293,12 @@ static void ipr_process_error(struct ipr_cmnd *ipr_cmd) struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg; struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb; u32 ioasc = be32_to_cpu(ipr_cmd->ioasa.ioasc); - u32 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error.failing_dev_ioasc); + u32 fd_ioasc; + + if (ioa_cfg->sis64) + fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc); + else + fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc); list_del(&hostrcb->queue); list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q); @@ -6996,7 +7233,7 @@ static void ipr_get_unit_check_buffer(struct ipr_ioa_cfg *ioa_cfg) if (!rc) { ipr_handle_log_data(ioa_cfg, hostrcb); - ioasc = be32_to_cpu(hostrcb->hcam.u.error.failing_dev_ioasc); + ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc); if (ioasc == IPR_IOASC_NR_IOA_RESET_REQUIRED && ioa_cfg->sdt_state == GET_DUMP) ioa_cfg->sdt_state = WAIT_FOR_DUMP; diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h index f10c57b3d215..e6e90179e45e 100644 --- a/drivers/scsi/ipr.h +++ b/drivers/scsi/ipr.h @@ -754,12 +754,29 @@ struct ipr_hostrcb_device_data_entry_enhanced { struct ipr_ext_vpd cfc_last_with_dev_vpd; }__attribute__((packed, aligned (4))); +struct ipr_hostrcb64_device_data_entry_enhanced { + struct ipr_ext_vpd vpd; + u8 ccin[4]; + u8 res_path[8]; + struct ipr_ext_vpd new_vpd; + u8 new_ccin[4]; + struct ipr_ext_vpd ioa_last_with_dev_vpd; + struct ipr_ext_vpd cfc_last_with_dev_vpd; +}__attribute__((packed, aligned (4))); + struct ipr_hostrcb_array_data_entry { struct ipr_vpd vpd; struct ipr_res_addr expected_dev_res_addr; struct ipr_res_addr dev_res_addr; }__attribute__((packed, aligned (4))); +struct ipr_hostrcb64_array_data_entry { + struct ipr_ext_vpd vpd; + u8 ccin[4]; + u8 expected_res_path[8]; + u8 res_path[8]; +}__attribute__((packed, aligned (4))); + struct ipr_hostrcb_array_data_entry_enhanced { struct ipr_ext_vpd vpd; u8 ccin[4]; @@ -811,6 +828,14 @@ struct ipr_hostrcb_type_13_error { struct ipr_hostrcb_device_data_entry_enhanced dev[3]; }__attribute__((packed, aligned (4))); +struct ipr_hostrcb_type_23_error { + struct ipr_ext_vpd ioa_vpd; + struct ipr_ext_vpd cfc_vpd; + __be32 errors_detected; + __be32 errors_logged; + struct ipr_hostrcb64_device_data_entry_enhanced dev[3]; +}__attribute__((packed, aligned (4))); + struct ipr_hostrcb_type_04_error { struct ipr_vpd ioa_vpd; struct ipr_vpd cfc_vpd; @@ -838,6 +863,22 @@ struct ipr_hostrcb_type_14_error { struct ipr_hostrcb_array_data_entry_enhanced array_member[18]; }__attribute__((packed, aligned (4))); +struct ipr_hostrcb_type_24_error { + struct ipr_ext_vpd ioa_vpd; + struct ipr_ext_vpd cfc_vpd; + u8 reserved[2]; + u8 exposed_mode_adn; +#define IPR_INVALID_ARRAY_DEV_NUM 0xff + u8 array_id; + u8 last_res_path[8]; + u8 protection_level[8]; + struct ipr_ext_vpd array_vpd; + u8 description[16]; + u8 reserved2[3]; + u8 num_entries; + struct ipr_hostrcb64_array_data_entry array_member[32]; +}__attribute__((packed, aligned (4))); + struct ipr_hostrcb_type_07_error { u8 failure_reason[64]; struct ipr_vpd vpd; @@ -875,6 +916,22 @@ struct ipr_hostrcb_config_element { __be32 wwid[2]; }__attribute__((packed, aligned (4))); +struct ipr_hostrcb64_config_element { + __be16 length; + u8 descriptor_id; +#define IPR_DESCRIPTOR_MASK 0xC0 +#define IPR_DESCRIPTOR_SIS64 0x00 + + u8 reserved; + u8 type_status; + + u8 reserved2[2]; + u8 link_rate; + + u8 res_path[8]; + __be32 wwid[2]; +}__attribute__((packed, aligned (8))); + struct ipr_hostrcb_fabric_desc { __be16 length; u8 ioa_port; @@ -896,6 +953,20 @@ struct ipr_hostrcb_fabric_desc { struct ipr_hostrcb_config_element elem[1]; }__attribute__((packed, aligned (4))); +struct ipr_hostrcb64_fabric_desc { + __be16 length; + u8 descriptor_id; + + u8 reserved; + u8 path_state; + + u8 reserved2[2]; + u8 res_path[8]; + u8 reserved3[6]; + __be16 num_entries; + struct ipr_hostrcb64_config_element elem[1]; +}__attribute__((packed, aligned (8))); + #define for_each_fabric_cfg(fabric, cfg) \ for (cfg = (fabric)->elem; \ cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \ @@ -908,10 +979,17 @@ struct ipr_hostrcb_type_20_error { struct ipr_hostrcb_fabric_desc desc[1]; }__attribute__((packed, aligned (4))); +struct ipr_hostrcb_type_30_error { + u8 failure_reason[64]; + u8 reserved[3]; + u8 num_entries; + struct ipr_hostrcb64_fabric_desc desc[1]; +}__attribute__((packed, aligned (4))); + struct ipr_hostrcb_error { - __be32 failing_dev_ioasc; - struct ipr_res_addr failing_dev_res_addr; - __be32 failing_dev_res_handle; + __be32 fd_ioasc; + struct ipr_res_addr fd_res_addr; + __be32 fd_res_handle; __be32 prc; union { struct ipr_hostrcb_type_ff_error type_ff_error; @@ -928,6 +1006,26 @@ struct ipr_hostrcb_error { } u; }__attribute__((packed, aligned (4))); +struct ipr_hostrcb64_error { + __be32 fd_ioasc; + __be32 ioa_fw_level; + __be32 fd_res_handle; + __be32 prc; + __be64 fd_dev_id; + __be64 fd_lun; + u8 fd_res_path[8]; + __be64 time_stamp; + u8 reserved[2]; + union { + struct ipr_hostrcb_type_ff_error type_ff_error; + struct ipr_hostrcb_type_12_error type_12_error; + struct ipr_hostrcb_type_17_error type_17_error; + struct ipr_hostrcb_type_23_error type_23_error; + struct ipr_hostrcb_type_24_error type_24_error; + struct ipr_hostrcb_type_30_error type_30_error; + } u; +}__attribute__((packed, aligned (8))); + struct ipr_hostrcb_raw { __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)]; }__attribute__((packed, aligned (4))); @@ -965,7 +1063,11 @@ struct ipr_hcam { #define IPR_HOST_RCB_OVERLAY_ID_16 0x16 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20 -#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF +#define IPR_HOST_RCB_OVERLAY_ID_23 0x23 +#define IPR_HOST_RCB_OVERLAY_ID_24 0x24 +#define IPR_HOST_RCB_OVERLAY_ID_26 0x26 +#define IPR_HOST_RCB_OVERLAY_ID_30 0x30 +#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF u8 reserved1[3]; __be32 ilid; @@ -975,6 +1077,7 @@ struct ipr_hcam { union { struct ipr_hostrcb_error error; + struct ipr_hostrcb64_error error64; struct ipr_hostrcb_cfg_ch_not ccn; struct ipr_hostrcb_raw raw; } u; @@ -985,6 +1088,7 @@ struct ipr_hostrcb { dma_addr_t hostrcb_dma; struct list_head queue; struct ipr_ioa_cfg *ioa_cfg; + char rp_buffer[IPR_MAX_RES_PATH_LENGTH]; }; /* IPR smart dump table structures */ @@ -1521,14 +1625,21 @@ struct ipr_ucode_image_header { } #define ipr_hcam_err(hostrcb, fmt, ...) \ -{ \ - if (ipr_is_device(&(hostrcb)->hcam.u.error.failing_dev_res_addr)) { \ - ipr_ra_err((hostrcb)->ioa_cfg, \ - (hostrcb)->hcam.u.error.failing_dev_res_addr, \ - fmt, ##__VA_ARGS__); \ - } else { \ - dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, ##__VA_ARGS__); \ - } \ +{ \ + if (ipr_is_device(hostrcb)) { \ + if ((hostrcb)->ioa_cfg->sis64) { \ + printk(KERN_ERR IPR_NAME ": %s: " fmt, \ + ipr_format_resource_path(&hostrcb->hcam.u.error64.fd_res_path[0], \ + &hostrcb->rp_buffer[0]), \ + __VA_ARGS__); \ + } else { \ + ipr_ra_err((hostrcb)->ioa_cfg, \ + (hostrcb)->hcam.u.error.fd_res_addr, \ + fmt, __VA_ARGS__); \ + } \ + } else { \ + dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \ + } \ } #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\ @@ -1637,18 +1748,29 @@ static inline int ipr_is_naca_model(struct ipr_resource_entry *res) } /** - * ipr_is_device - Determine if resource address is that of a device - * @res_addr: resource address struct + * ipr_is_device - Determine if the hostrcb structure is related to a device + * @hostrcb: host resource control blocks struct * * Return value: * 1 if AF / 0 if not AF **/ -static inline int ipr_is_device(struct ipr_res_addr *res_addr) +static inline int ipr_is_device(struct ipr_hostrcb *hostrcb) { - if ((res_addr->bus < IPR_MAX_NUM_BUSES) && - (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1))) - return 1; - + struct ipr_res_addr *res_addr; + u8 *res_path; + + if (hostrcb->ioa_cfg->sis64) { + res_path = &hostrcb->hcam.u.error64.fd_res_path[0]; + if ((res_path[0] == 0x00 || res_path[0] == 0x80 || + res_path[0] == 0x81) && res_path[2] != 0xFF) + return 1; + } else { + res_addr = &hostrcb->hcam.u.error.fd_res_addr; + + if ((res_addr->bus < IPR_MAX_NUM_BUSES) && + (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1))) + return 1; + } return 0; } -- cgit v1.2.3 From dcbad00e6b403089b1846e788bc1a0c67b2bfd2d Mon Sep 17 00:00:00 2001 From: Wayne Boyer Date: Fri, 19 Feb 2010 13:24:14 -0800 Subject: [SCSI] ipr: add hardware assisted smart dump functionality This patch adds the hardware assisted smart dump functionality for the next generation IOA PCI interface chip. Signea-off-by: Wayne Boyer Signed-off-by: James Bottomley --- drivers/scsi/ipr.c | 81 +++++++++++++++++++++++++++++++++++++++++++----------- drivers/scsi/ipr.h | 16 +++++++---- 2 files changed, 75 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index b2e60bd4a0c6..dd12486ba520 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -142,7 +142,9 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = { .ioarrin_reg = 0x00070, .sense_uproc_interrupt_reg = 0x00020, .set_uproc_interrupt_reg = 0x00020, - .clr_uproc_interrupt_reg = 0x00028 + .clr_uproc_interrupt_reg = 0x00028, + .dump_addr_reg = 0x00064, + .dump_data_reg = 0x00068 } }, }; @@ -2513,6 +2515,31 @@ static int ipr_wait_iodbg_ack(struct ipr_ioa_cfg *ioa_cfg, int max_delay) return -EIO; } +/** + * ipr_get_sis64_dump_data_section - Dump IOA memory + * @ioa_cfg: ioa config struct + * @start_addr: adapter address to dump + * @dest: destination kernel buffer + * @length_in_words: length to dump in 4 byte words + * + * Return value: + * 0 on success + **/ +static int ipr_get_sis64_dump_data_section(struct ipr_ioa_cfg *ioa_cfg, + u32 start_addr, + __be32 *dest, u32 length_in_words) +{ + int i; + + for (i = 0; i < length_in_words; i++) { + writel(start_addr+(i*4), ioa_cfg->regs.dump_addr_reg); + *dest = cpu_to_be32(readl(ioa_cfg->regs.dump_data_reg)); + dest++; + } + + return 0; +} + /** * ipr_get_ldump_data_section - Dump IOA memory * @ioa_cfg: ioa config struct @@ -2530,6 +2557,10 @@ static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg, volatile u32 temp_pcii_reg; int i, delay = 0; + if (ioa_cfg->sis64) + return ipr_get_sis64_dump_data_section(ioa_cfg, start_addr, + dest, length_in_words); + /* Write IOA interrupt reg starting LDUMP state */ writel((IPR_UPROCI_RESET_ALERT | IPR_UPROCI_IO_DEBUG_ALERT), ioa_cfg->regs.set_uproc_interrupt_reg); @@ -2787,6 +2818,7 @@ static void ipr_get_ioa_dump(struct ipr_ioa_cfg *ioa_cfg, struct ipr_dump *dump) u32 num_entries, start_off, end_off; u32 bytes_to_copy, bytes_copied, rc; struct ipr_sdt *sdt; + int valid = 1; int i; ENTER; @@ -2800,7 +2832,7 @@ static void ipr_get_ioa_dump(struct ipr_ioa_cfg *ioa_cfg, struct ipr_dump *dump) start_addr = readl(ioa_cfg->ioa_mailbox); - if (!ipr_sdt_is_fmt2(start_addr)) { + if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(start_addr)) { dev_err(&ioa_cfg->pdev->dev, "Invalid dump table format: %lx\n", start_addr); spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); @@ -2829,7 +2861,6 @@ static void ipr_get_ioa_dump(struct ipr_ioa_cfg *ioa_cfg, struct ipr_dump *dump) /* IOA Dump entry */ ipr_init_dump_entry_hdr(&ioa_dump->hdr); - ioa_dump->format = IPR_SDT_FMT2; ioa_dump->hdr.len = 0; ioa_dump->hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY; ioa_dump->hdr.id = IPR_DUMP_IOA_DUMP_ID; @@ -2844,7 +2875,8 @@ static void ipr_get_ioa_dump(struct ipr_ioa_cfg *ioa_cfg, struct ipr_dump *dump) sizeof(struct ipr_sdt) / sizeof(__be32)); /* Smart Dump table is ready to use and the first entry is valid */ - if (rc || (be32_to_cpu(sdt->hdr.state) != IPR_FMT2_SDT_READY_TO_USE)) { + if (rc || ((be32_to_cpu(sdt->hdr.state) != IPR_FMT3_SDT_READY_TO_USE) && + (be32_to_cpu(sdt->hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) { dev_err(&ioa_cfg->pdev->dev, "Dump of IOA failed. Dump table not valid: %d, %X.\n", rc, be32_to_cpu(sdt->hdr.state)); @@ -2868,12 +2900,19 @@ static void ipr_get_ioa_dump(struct ipr_ioa_cfg *ioa_cfg, struct ipr_dump *dump) } if (sdt->entry[i].flags & IPR_SDT_VALID_ENTRY) { - sdt_word = be32_to_cpu(sdt->entry[i].bar_str_offset); - start_off = sdt_word & IPR_FMT2_MBX_ADDR_MASK; - end_off = be32_to_cpu(sdt->entry[i].end_offset); - - if (ipr_sdt_is_fmt2(sdt_word) && sdt_word) { - bytes_to_copy = end_off - start_off; + sdt_word = be32_to_cpu(sdt->entry[i].start_token); + if (ioa_cfg->sis64) + bytes_to_copy = be32_to_cpu(sdt->entry[i].end_token); + else { + start_off = sdt_word & IPR_FMT2_MBX_ADDR_MASK; + end_off = be32_to_cpu(sdt->entry[i].end_token); + + if (ipr_sdt_is_fmt2(sdt_word) && sdt_word) + bytes_to_copy = end_off - start_off; + else + valid = 0; + } + if (valid) { if (bytes_to_copy > IPR_MAX_IOA_DUMP_SIZE) { sdt->entry[i].flags &= ~IPR_SDT_VALID_ENTRY; continue; @@ -7202,7 +7241,7 @@ static void ipr_get_unit_check_buffer(struct ipr_ioa_cfg *ioa_cfg) mailbox = readl(ioa_cfg->ioa_mailbox); - if (!ipr_sdt_is_fmt2(mailbox)) { + if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(mailbox)) { ipr_unit_check_no_data(ioa_cfg); return; } @@ -7211,15 +7250,20 @@ static void ipr_get_unit_check_buffer(struct ipr_ioa_cfg *ioa_cfg) rc = ipr_get_ldump_data_section(ioa_cfg, mailbox, (__be32 *) &sdt, (sizeof(struct ipr_uc_sdt)) / sizeof(__be32)); - if (rc || (be32_to_cpu(sdt.hdr.state) != IPR_FMT2_SDT_READY_TO_USE) || - !(sdt.entry[0].flags & IPR_SDT_VALID_ENTRY)) { + if (rc || !(sdt.entry[0].flags & IPR_SDT_VALID_ENTRY) || + ((be32_to_cpu(sdt.hdr.state) != IPR_FMT3_SDT_READY_TO_USE) && + (be32_to_cpu(sdt.hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) { ipr_unit_check_no_data(ioa_cfg); return; } /* Find length of the first sdt entry (UC buffer) */ - length = (be32_to_cpu(sdt.entry[0].end_offset) - - be32_to_cpu(sdt.entry[0].bar_str_offset)) & IPR_FMT2_MBX_ADDR_MASK; + if (be32_to_cpu(sdt.hdr.state) == IPR_FMT3_SDT_READY_TO_USE) + length = be32_to_cpu(sdt.entry[0].end_token); + else + length = (be32_to_cpu(sdt.entry[0].end_token) - + be32_to_cpu(sdt.entry[0].start_token)) & + IPR_FMT2_MBX_ADDR_MASK; hostrcb = list_entry(ioa_cfg->hostrcb_free_q.next, struct ipr_hostrcb, queue); @@ -7227,7 +7271,7 @@ static void ipr_get_unit_check_buffer(struct ipr_ioa_cfg *ioa_cfg) memset(&hostrcb->hcam, 0, sizeof(hostrcb->hcam)); rc = ipr_get_ldump_data_section(ioa_cfg, - be32_to_cpu(sdt.entry[0].bar_str_offset), + be32_to_cpu(sdt.entry[0].start_token), (__be32 *)&hostrcb->hcam, min(length, (int)sizeof(hostrcb->hcam)) / sizeof(__be32)); @@ -8202,6 +8246,11 @@ static void __devinit ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg, t->sense_uproc_interrupt_reg = base + p->sense_uproc_interrupt_reg; t->set_uproc_interrupt_reg = base + p->set_uproc_interrupt_reg; t->clr_uproc_interrupt_reg = base + p->clr_uproc_interrupt_reg; + + if (ioa_cfg->sis64) { + t->dump_addr_reg = base + p->dump_addr_reg; + t->dump_data_reg = base + p->dump_data_reg; + } } /** diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h index e6e90179e45e..4f2f1d2e9875 100644 --- a/drivers/scsi/ipr.h +++ b/drivers/scsi/ipr.h @@ -228,6 +228,7 @@ #define IPR_SDT_FMT2_BAR5_SEL 0x5 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2 +#define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3 #define IPR_DOORBELL 0x82800000 #define IPR_RUNTIME_RESET 0x40000000 @@ -1093,10 +1094,9 @@ struct ipr_hostrcb { /* IPR smart dump table structures */ struct ipr_sdt_entry { - __be32 bar_str_offset; - __be32 end_offset; - u8 entry_byte; - u8 reserved[3]; + __be32 start_token; + __be32 end_token; + u8 reserved[4]; u8 flags; #define IPR_SDT_ENDIAN 0x80 @@ -1204,6 +1204,9 @@ struct ipr_interrupt_offsets { unsigned long sense_uproc_interrupt_reg; unsigned long set_uproc_interrupt_reg; unsigned long clr_uproc_interrupt_reg; + + unsigned long dump_addr_reg; + unsigned long dump_data_reg; }; struct ipr_interrupts { @@ -1217,6 +1220,9 @@ struct ipr_interrupts { void __iomem *sense_uproc_interrupt_reg; void __iomem *set_uproc_interrupt_reg; void __iomem *clr_uproc_interrupt_reg; + + void __iomem *dump_addr_reg; + void __iomem *dump_data_reg; }; struct ipr_chip_cfg_t { @@ -1536,8 +1542,6 @@ struct ipr_ioa_dump { u32 next_page_index; u32 page_offset; u32 format; -#define IPR_SDT_FMT2 2 -#define IPR_SDT_UNKNOWN 3 }__attribute__((packed, aligned (4))); struct ipr_dump { -- cgit v1.2.3 From f72919ec2bbbe1c42cdda7857a96c0c40e1d78aa Mon Sep 17 00:00:00 2001 From: Wayne Boyer Date: Fri, 19 Feb 2010 13:24:21 -0800 Subject: [SCSI] ipr: implement shutdown changes and remove obsolete write cache parameter This patch adds a reboot notifier that will issue a shutdown prepare command to all adapters. This helps to prevent a problem where the primary adapter can get shut down before the secondary adapter and cause the secondary adapter to fail over and log and error. This patch also removes the "enable_cache" paramater as it is obsolete. Write cache for an adapter is now controlled from the iprconfig utility. Signed-off-by: Wayne Boyer Signed-off-by: James Bottomley --- drivers/scsi/ipr.c | 208 +++++++++++++++++------------------------------------ drivers/scsi/ipr.h | 10 +-- 2 files changed, 66 insertions(+), 152 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index dd12486ba520..a64fb5085882 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -72,6 +72,7 @@ #include #include #include +#include #include #include #include @@ -92,7 +93,6 @@ static unsigned int ipr_max_speed = 1; static int ipr_testmode = 0; static unsigned int ipr_fastfail = 0; static unsigned int ipr_transop_timeout = 0; -static unsigned int ipr_enable_cache = 1; static unsigned int ipr_debug = 0; static unsigned int ipr_max_devs = IPR_DEFAULT_SIS64_DEVS; static unsigned int ipr_dual_ioa_raid = 1; @@ -175,8 +175,6 @@ module_param_named(fastfail, ipr_fastfail, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(fastfail, "Reduce timeouts and retries"); module_param_named(transop_timeout, ipr_transop_timeout, int, 0); MODULE_PARM_DESC(transop_timeout, "Time in seconds to wait for adapter to come operational (default: 300)"); -module_param_named(enable_cache, ipr_enable_cache, int, 0); -MODULE_PARM_DESC(enable_cache, "Enable adapter's non-volatile write cache (default: 1)"); module_param_named(debug, ipr_debug, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(debug, "Enable device driver debugging logging. Set to 1 to enable. (default: 0)"); module_param_named(dual_ioa_raid, ipr_dual_ioa_raid, int, 0); @@ -3097,105 +3095,6 @@ static struct bin_attribute ipr_trace_attr = { }; #endif -static const struct { - enum ipr_cache_state state; - char *name; -} cache_state [] = { - { CACHE_NONE, "none" }, - { CACHE_DISABLED, "disabled" }, - { CACHE_ENABLED, "enabled" } -}; - -/** - * ipr_show_write_caching - Show the write caching attribute - * @dev: device struct - * @buf: buffer - * - * Return value: - * number of bytes printed to buffer - **/ -static ssize_t ipr_show_write_caching(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct Scsi_Host *shost = class_to_shost(dev); - struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata; - unsigned long lock_flags = 0; - int i, len = 0; - - spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags); - for (i = 0; i < ARRAY_SIZE(cache_state); i++) { - if (cache_state[i].state == ioa_cfg->cache_state) { - len = snprintf(buf, PAGE_SIZE, "%s\n", cache_state[i].name); - break; - } - } - spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); - return len; -} - - -/** - * ipr_store_write_caching - Enable/disable adapter write cache - * @dev: device struct - * @buf: buffer - * @count: buffer size - * - * This function will enable/disable adapter write cache. - * - * Return value: - * count on success / other on failure - **/ -static ssize_t ipr_store_write_caching(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct Scsi_Host *shost = class_to_shost(dev); - struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata; - unsigned long lock_flags = 0; - enum ipr_cache_state new_state = CACHE_INVALID; - int i; - - if (!capable(CAP_SYS_ADMIN)) - return -EACCES; - if (ioa_cfg->cache_state == CACHE_NONE) - return -EINVAL; - - for (i = 0; i < ARRAY_SIZE(cache_state); i++) { - if (!strncmp(cache_state[i].name, buf, strlen(cache_state[i].name))) { - new_state = cache_state[i].state; - break; - } - } - - if (new_state != CACHE_DISABLED && new_state != CACHE_ENABLED) - return -EINVAL; - - spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags); - if (ioa_cfg->cache_state == new_state) { - spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); - return count; - } - - ioa_cfg->cache_state = new_state; - dev_info(&ioa_cfg->pdev->dev, "%s adapter write cache.\n", - new_state == CACHE_ENABLED ? "Enabling" : "Disabling"); - if (!ioa_cfg->in_reset_reload) - ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL); - spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); - wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload); - - return count; -} - -static struct device_attribute ipr_ioa_cache_attr = { - .attr = { - .name = "write_cache", - .mode = S_IRUGO | S_IWUSR, - }, - .show = ipr_show_write_caching, - .store = ipr_store_write_caching -}; - /** * ipr_show_fw_version - Show the firmware version * @dev: class device struct @@ -3797,7 +3696,6 @@ static struct device_attribute *ipr_ioa_attrs[] = { &ipr_ioa_state_attr, &ipr_ioa_reset_attr, &ipr_update_fw_attr, - &ipr_ioa_cache_attr, NULL, }; @@ -6292,36 +6190,6 @@ static int ipr_set_supported_devs(struct ipr_cmnd *ipr_cmd) return IPR_RC_JOB_CONTINUE; } -/** - * ipr_setup_write_cache - Disable write cache if needed - * @ipr_cmd: ipr command struct - * - * This function sets up adapters write cache to desired setting - * - * Return value: - * IPR_RC_JOB_CONTINUE / IPR_RC_JOB_RETURN - **/ -static int ipr_setup_write_cache(struct ipr_cmnd *ipr_cmd) -{ - struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg; - - ipr_cmd->job_step = ipr_set_supported_devs; - ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next, - struct ipr_resource_entry, queue); - - if (ioa_cfg->cache_state != CACHE_DISABLED) - return IPR_RC_JOB_CONTINUE; - - ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE); - ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD; - ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN; - ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_SHUTDOWN_PREPARE_FOR_NORMAL; - - ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT); - - return IPR_RC_JOB_RETURN; -} - /** * ipr_get_mode_page - Locate specified mode page * @mode_pages: mode page buffer @@ -6522,7 +6390,9 @@ static int ipr_ioafp_mode_select_page28(struct ipr_cmnd *ipr_cmd) ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, mode_pages), length); - ipr_cmd->job_step = ipr_setup_write_cache; + ipr_cmd->job_step = ipr_set_supported_devs; + ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next, + struct ipr_resource_entry, queue); ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT); LEAVE; @@ -6590,10 +6460,13 @@ static int ipr_reset_cmd_failed(struct ipr_cmnd *ipr_cmd) **/ static int ipr_reset_mode_sense_failed(struct ipr_cmnd *ipr_cmd) { + struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg; u32 ioasc = be32_to_cpu(ipr_cmd->ioasa.ioasc); if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT) { - ipr_cmd->job_step = ipr_setup_write_cache; + ipr_cmd->job_step = ipr_set_supported_devs; + ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next, + struct ipr_resource_entry, queue); return IPR_RC_JOB_CONTINUE; } @@ -6944,13 +6817,9 @@ static int ipr_ioafp_cap_inquiry(struct ipr_cmnd *ipr_cmd) static int ipr_ioafp_page3_inquiry(struct ipr_cmnd *ipr_cmd) { struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg; - struct ipr_inquiry_page0 *page0 = &ioa_cfg->vpd_cbs->page0_data; ENTER; - if (!ipr_inquiry_page_supported(page0, 1)) - ioa_cfg->cache_state = CACHE_NONE; - ipr_cmd->job_step = ipr_ioafp_cap_inquiry; ipr_ioafp_inquiry(ipr_cmd, 1, 3, @@ -8209,10 +8078,6 @@ static void __devinit ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg, init_waitqueue_head(&ioa_cfg->reset_wait_q); init_waitqueue_head(&ioa_cfg->msi_wait_q); ioa_cfg->sdt_state = INACTIVE; - if (ipr_enable_cache) - ioa_cfg->cache_state = CACHE_ENABLED; - else - ioa_cfg->cache_state = CACHE_DISABLED; ipr_initialize_bus_attr(ioa_cfg); ioa_cfg->max_devs_supported = ipr_max_devs; @@ -8841,6 +8706,61 @@ static struct pci_driver ipr_driver = { .err_handler = &ipr_err_handler, }; +/** + * ipr_halt_done - Shutdown prepare completion + * + * Return value: + * none + **/ +static void ipr_halt_done(struct ipr_cmnd *ipr_cmd) +{ + struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg; + + list_add_tail(&ipr_cmd->queue, &ioa_cfg->free_q); +} + +/** + * ipr_halt - Issue shutdown prepare to all adapters + * + * Return value: + * NOTIFY_OK on success / NOTIFY_DONE on failure + **/ +static int ipr_halt(struct notifier_block *nb, ulong event, void *buf) +{ + struct ipr_cmnd *ipr_cmd; + struct ipr_ioa_cfg *ioa_cfg; + unsigned long flags = 0; + + if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF) + return NOTIFY_DONE; + + spin_lock(&ipr_driver_lock); + + list_for_each_entry(ioa_cfg, &ipr_ioa_head, queue) { + spin_lock_irqsave(ioa_cfg->host->host_lock, flags); + if (!ioa_cfg->allow_cmds) { + spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags); + continue; + } + + ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg); + ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE); + ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD; + ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN; + ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_SHUTDOWN_PREPARE_FOR_NORMAL; + + ipr_do_req(ipr_cmd, ipr_halt_done, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT); + spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags); + } + spin_unlock(&ipr_driver_lock); + + return NOTIFY_OK; +} + +static struct notifier_block ipr_notifier = { + ipr_halt, NULL, 0 +}; + /** * ipr_init - Module entry point * @@ -8852,6 +8772,7 @@ static int __init ipr_init(void) ipr_info("IBM Power RAID SCSI Device Driver version: %s %s\n", IPR_DRIVER_VERSION, IPR_DRIVER_DATE); + register_reboot_notifier(&ipr_notifier); return pci_register_driver(&ipr_driver); } @@ -8865,6 +8786,7 @@ static int __init ipr_init(void) **/ static void __exit ipr_exit(void) { + unregister_reboot_notifier(&ipr_notifier); pci_unregister_driver(&ipr_driver); } diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h index 4f2f1d2e9875..36736b512846 100644 --- a/drivers/scsi/ipr.h +++ b/drivers/scsi/ipr.h @@ -136,7 +136,7 @@ /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */ #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \ - ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3) + ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4) #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \ @@ -1284,13 +1284,6 @@ enum ipr_sdt_state { DUMP_OBTAINED }; -enum ipr_cache_state { - CACHE_NONE, - CACHE_DISABLED, - CACHE_ENABLED, - CACHE_INVALID -}; - /* Per-controller data */ struct ipr_ioa_cfg { char eye_catcher[8]; @@ -1321,7 +1314,6 @@ struct ipr_ioa_cfg { unsigned long *array_ids; unsigned long *vset_ids; - enum ipr_cache_state cache_state; u16 type; /* CCIN of the card */ u8 log_level; -- cgit v1.2.3 From 214777ba125e2902c9b84c764be38099c94d0bd2 Mon Sep 17 00:00:00 2001 From: Wayne Boyer Date: Fri, 19 Feb 2010 13:24:26 -0800 Subject: [SCSI] ipr: add support for multiple stages of initialization This patch adds support for using the new IOA initialization feedback register. It also enables 64 bit support in the ipr_ioafp_identify_hrrq and ipr_mask_and_clear_interrupts routines. Signed-off-by: Wayne Boyer Signed-off-by: James Bottomley --- drivers/scsi/ipr.c | 185 ++++++++++++++++++++++++++++++++++++++++++++--------- drivers/scsi/ipr.h | 25 ++++++++ 2 files changed, 180 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index a64fb5085882..10b162d607ac 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -106,13 +106,20 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = { { .set_interrupt_mask_reg = 0x0022C, .clr_interrupt_mask_reg = 0x00230, + .clr_interrupt_mask_reg32 = 0x00230, .sense_interrupt_mask_reg = 0x0022C, + .sense_interrupt_mask_reg32 = 0x0022C, .clr_interrupt_reg = 0x00228, + .clr_interrupt_reg32 = 0x00228, .sense_interrupt_reg = 0x00224, + .sense_interrupt_reg32 = 0x00224, .ioarrin_reg = 0x00404, .sense_uproc_interrupt_reg = 0x00214, + .sense_uproc_interrupt_reg32 = 0x00214, .set_uproc_interrupt_reg = 0x00214, - .clr_uproc_interrupt_reg = 0x00218 + .set_uproc_interrupt_reg32 = 0x00214, + .clr_uproc_interrupt_reg = 0x00218, + .clr_uproc_interrupt_reg32 = 0x00218 } }, { /* Snipe and Scamp */ @@ -121,13 +128,20 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = { { .set_interrupt_mask_reg = 0x00288, .clr_interrupt_mask_reg = 0x0028C, + .clr_interrupt_mask_reg32 = 0x0028C, .sense_interrupt_mask_reg = 0x00288, + .sense_interrupt_mask_reg32 = 0x00288, .clr_interrupt_reg = 0x00284, + .clr_interrupt_reg32 = 0x00284, .sense_interrupt_reg = 0x00280, + .sense_interrupt_reg32 = 0x00280, .ioarrin_reg = 0x00504, .sense_uproc_interrupt_reg = 0x00290, + .sense_uproc_interrupt_reg32 = 0x00290, .set_uproc_interrupt_reg = 0x00290, - .clr_uproc_interrupt_reg = 0x00294 + .set_uproc_interrupt_reg32 = 0x00290, + .clr_uproc_interrupt_reg = 0x00294, + .clr_uproc_interrupt_reg32 = 0x00294 } }, { /* CRoC */ @@ -136,13 +150,21 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = { { .set_interrupt_mask_reg = 0x00010, .clr_interrupt_mask_reg = 0x00018, + .clr_interrupt_mask_reg32 = 0x0001C, .sense_interrupt_mask_reg = 0x00010, + .sense_interrupt_mask_reg32 = 0x00014, .clr_interrupt_reg = 0x00008, + .clr_interrupt_reg32 = 0x0000C, .sense_interrupt_reg = 0x00000, + .sense_interrupt_reg32 = 0x00004, .ioarrin_reg = 0x00070, .sense_uproc_interrupt_reg = 0x00020, + .sense_uproc_interrupt_reg32 = 0x00024, .set_uproc_interrupt_reg = 0x00020, + .set_uproc_interrupt_reg32 = 0x00024, .clr_uproc_interrupt_reg = 0x00028, + .clr_uproc_interrupt_reg32 = 0x0002C, + .init_feedback_reg = 0x0005C, .dump_addr_reg = 0x00064, .dump_data_reg = 0x00068 } @@ -592,10 +614,15 @@ static void ipr_mask_and_clear_interrupts(struct ipr_ioa_cfg *ioa_cfg, ioa_cfg->allow_interrupts = 0; /* Set interrupt mask to stop all new interrupts */ - writel(~0, ioa_cfg->regs.set_interrupt_mask_reg); + if (ioa_cfg->sis64) + writeq(~0, ioa_cfg->regs.set_interrupt_mask_reg); + else + writel(~0, ioa_cfg->regs.set_interrupt_mask_reg); /* Clear any pending interrupts */ - writel(clr_ints, ioa_cfg->regs.clr_interrupt_reg); + if (ioa_cfg->sis64) + writel(~0, ioa_cfg->regs.clr_interrupt_reg); + writel(clr_ints, ioa_cfg->regs.clr_interrupt_reg32); int_reg = readl(ioa_cfg->regs.sense_interrupt_reg); } @@ -2561,7 +2588,7 @@ static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg, /* Write IOA interrupt reg starting LDUMP state */ writel((IPR_UPROCI_RESET_ALERT | IPR_UPROCI_IO_DEBUG_ALERT), - ioa_cfg->regs.set_uproc_interrupt_reg); + ioa_cfg->regs.set_uproc_interrupt_reg32); /* Wait for IO debug acknowledge */ if (ipr_wait_iodbg_ack(ioa_cfg, @@ -2580,7 +2607,7 @@ static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg, /* Signal address valid - clear IOA Reset alert */ writel(IPR_UPROCI_RESET_ALERT, - ioa_cfg->regs.clr_uproc_interrupt_reg); + ioa_cfg->regs.clr_uproc_interrupt_reg32); for (i = 0; i < length_in_words; i++) { /* Wait for IO debug acknowledge */ @@ -2605,10 +2632,10 @@ static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg, /* Signal end of block transfer. Set reset alert then clear IO debug ack */ writel(IPR_UPROCI_RESET_ALERT, - ioa_cfg->regs.set_uproc_interrupt_reg); + ioa_cfg->regs.set_uproc_interrupt_reg32); writel(IPR_UPROCI_IO_DEBUG_ALERT, - ioa_cfg->regs.clr_uproc_interrupt_reg); + ioa_cfg->regs.clr_uproc_interrupt_reg32); /* Signal dump data received - Clear IO debug Ack */ writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, @@ -2617,7 +2644,7 @@ static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg, /* Wait for IOA to signal LDUMP exit - IOA reset alert will be cleared */ while (delay < IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC) { temp_pcii_reg = - readl(ioa_cfg->regs.sense_uproc_interrupt_reg); + readl(ioa_cfg->regs.sense_uproc_interrupt_reg32); if (!(temp_pcii_reg & IPR_UPROCI_RESET_ALERT)) return 0; @@ -4831,11 +4858,29 @@ static irqreturn_t ipr_isr(int irq, void *devp) return IRQ_NONE; } - int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg); - int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg; + int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg32); + int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32) & ~int_mask_reg; - /* If an interrupt on the adapter did not occur, ignore it */ + /* If an interrupt on the adapter did not occur, ignore it. + * Or in the case of SIS 64, check for a stage change interrupt. + */ if (unlikely((int_reg & IPR_PCII_OPER_INTERRUPTS) == 0)) { + if (ioa_cfg->sis64) { + int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg); + int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg; + if (int_reg & IPR_PCII_IPL_STAGE_CHANGE) { + + /* clear stage change */ + writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_reg); + int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg; + list_del(&ioa_cfg->reset_cmd->queue); + del_timer(&ioa_cfg->reset_cmd->timer); + ipr_reset_ioa_job(ioa_cfg->reset_cmd); + spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); + return IRQ_HANDLED; + } + } + spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); return IRQ_NONE; } @@ -4878,8 +4923,8 @@ static irqreturn_t ipr_isr(int irq, void *devp) if (ipr_cmd != NULL) { /* Clear the PCI interrupt */ do { - writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg); - int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg; + writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg32); + int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32) & ~int_mask_reg; } while (int_reg & IPR_PCII_HRRQ_UPDATED && num_hrrq++ < IPR_MAX_HRRQ_RETRIES); @@ -6887,7 +6932,7 @@ static int ipr_ioafp_std_inquiry(struct ipr_cmnd *ipr_cmd) } /** - * ipr_ioafp_indentify_hrrq - Send Identify Host RRQ. + * ipr_ioafp_identify_hrrq - Send Identify Host RRQ. * @ipr_cmd: ipr command struct * * This function send an Identify Host Request Response Queue @@ -6896,7 +6941,7 @@ static int ipr_ioafp_std_inquiry(struct ipr_cmnd *ipr_cmd) * Return value: * IPR_RC_JOB_RETURN **/ -static int ipr_ioafp_indentify_hrrq(struct ipr_cmnd *ipr_cmd) +static int ipr_ioafp_identify_hrrq(struct ipr_cmnd *ipr_cmd) { struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg; struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; @@ -6908,19 +6953,32 @@ static int ipr_ioafp_indentify_hrrq(struct ipr_cmnd *ipr_cmd) ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE); ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD; + if (ioa_cfg->sis64) + ioarcb->cmd_pkt.cdb[1] = 0x1; ioarcb->cmd_pkt.cdb[2] = - ((u32) ioa_cfg->host_rrq_dma >> 24) & 0xff; + ((u64) ioa_cfg->host_rrq_dma >> 24) & 0xff; ioarcb->cmd_pkt.cdb[3] = - ((u32) ioa_cfg->host_rrq_dma >> 16) & 0xff; + ((u64) ioa_cfg->host_rrq_dma >> 16) & 0xff; ioarcb->cmd_pkt.cdb[4] = - ((u32) ioa_cfg->host_rrq_dma >> 8) & 0xff; + ((u64) ioa_cfg->host_rrq_dma >> 8) & 0xff; ioarcb->cmd_pkt.cdb[5] = - ((u32) ioa_cfg->host_rrq_dma) & 0xff; + ((u64) ioa_cfg->host_rrq_dma) & 0xff; ioarcb->cmd_pkt.cdb[7] = ((sizeof(u32) * IPR_NUM_CMD_BLKS) >> 8) & 0xff; ioarcb->cmd_pkt.cdb[8] = (sizeof(u32) * IPR_NUM_CMD_BLKS) & 0xff; + if (ioa_cfg->sis64) { + ioarcb->cmd_pkt.cdb[10] = + ((u64) ioa_cfg->host_rrq_dma >> 56) & 0xff; + ioarcb->cmd_pkt.cdb[11] = + ((u64) ioa_cfg->host_rrq_dma >> 48) & 0xff; + ioarcb->cmd_pkt.cdb[12] = + ((u64) ioa_cfg->host_rrq_dma >> 40) & 0xff; + ioarcb->cmd_pkt.cdb[13] = + ((u64) ioa_cfg->host_rrq_dma >> 32) & 0xff; + } + ipr_cmd->job_step = ipr_ioafp_std_inquiry; ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT); @@ -7004,6 +7062,57 @@ static void ipr_init_ioa_mem(struct ipr_ioa_cfg *ioa_cfg) memset(ioa_cfg->u.cfg_table, 0, ioa_cfg->cfg_table_size); } +/** + * ipr_reset_next_stage - Process IPL stage change based on feedback register. + * @ipr_cmd: ipr command struct + * + * Return value: + * IPR_RC_JOB_CONTINUE / IPR_RC_JOB_RETURN + **/ +static int ipr_reset_next_stage(struct ipr_cmnd *ipr_cmd) +{ + unsigned long stage, stage_time; + u32 feedback; + volatile u32 int_reg; + struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg; + u64 maskval = 0; + + feedback = readl(ioa_cfg->regs.init_feedback_reg); + stage = feedback & IPR_IPL_INIT_STAGE_MASK; + stage_time = feedback & IPR_IPL_INIT_STAGE_TIME_MASK; + + ipr_dbg("IPL stage = 0x%lx, IPL stage time = %ld\n", stage, stage_time); + + /* sanity check the stage_time value */ + if (stage_time < IPR_IPL_INIT_MIN_STAGE_TIME) + stage_time = IPR_IPL_INIT_MIN_STAGE_TIME; + else if (stage_time > IPR_LONG_OPERATIONAL_TIMEOUT) + stage_time = IPR_LONG_OPERATIONAL_TIMEOUT; + + if (stage == IPR_IPL_INIT_STAGE_UNKNOWN) { + writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.set_interrupt_mask_reg); + int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg); + stage_time = ioa_cfg->transop_timeout; + ipr_cmd->job_step = ipr_ioafp_identify_hrrq; + } else if (stage == IPR_IPL_INIT_STAGE_TRANSOP) { + ipr_cmd->job_step = ipr_ioafp_identify_hrrq; + maskval = IPR_PCII_IPL_STAGE_CHANGE; + maskval = (maskval << 32) | IPR_PCII_IOA_TRANS_TO_OPER; + writeq(maskval, ioa_cfg->regs.set_interrupt_mask_reg); + int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg); + return IPR_RC_JOB_CONTINUE; + } + + ipr_cmd->timer.data = (unsigned long) ipr_cmd; + ipr_cmd->timer.expires = jiffies + stage_time * HZ; + ipr_cmd->timer.function = (void (*)(unsigned long))ipr_oper_timeout; + ipr_cmd->done = ipr_reset_ioa_job; + add_timer(&ipr_cmd->timer); + list_add_tail(&ipr_cmd->queue, &ioa_cfg->pending_q); + + return IPR_RC_JOB_RETURN; +} + /** * ipr_reset_enable_ioa - Enable the IOA following a reset. * @ipr_cmd: ipr command struct @@ -7020,7 +7129,7 @@ static int ipr_reset_enable_ioa(struct ipr_cmnd *ipr_cmd) volatile u32 int_reg; ENTER; - ipr_cmd->job_step = ipr_ioafp_indentify_hrrq; + ipr_cmd->job_step = ipr_ioafp_identify_hrrq; ipr_init_ioa_mem(ioa_cfg); ioa_cfg->allow_interrupts = 1; @@ -7028,19 +7137,27 @@ static int ipr_reset_enable_ioa(struct ipr_cmnd *ipr_cmd) if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) { writel((IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED), - ioa_cfg->regs.clr_interrupt_mask_reg); + ioa_cfg->regs.clr_interrupt_mask_reg32); int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg); return IPR_RC_JOB_CONTINUE; } /* Enable destructive diagnostics on IOA */ - writel(ioa_cfg->doorbell, ioa_cfg->regs.set_uproc_interrupt_reg); + writel(ioa_cfg->doorbell, ioa_cfg->regs.set_uproc_interrupt_reg32); + + writel(IPR_PCII_OPER_INTERRUPTS, ioa_cfg->regs.clr_interrupt_mask_reg32); + if (ioa_cfg->sis64) + writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_mask_reg); - writel(IPR_PCII_OPER_INTERRUPTS, ioa_cfg->regs.clr_interrupt_mask_reg); int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg); dev_info(&ioa_cfg->pdev->dev, "Initializing IOA.\n"); + if (ioa_cfg->sis64) { + ipr_cmd->job_step = ipr_reset_next_stage; + return IPR_RC_JOB_CONTINUE; + } + ipr_cmd->timer.data = (unsigned long) ipr_cmd; ipr_cmd->timer.expires = jiffies + (ioa_cfg->transop_timeout * HZ); ipr_cmd->timer.function = (void (*)(unsigned long))ipr_oper_timeout; @@ -7374,7 +7491,7 @@ static int ipr_reset_alert(struct ipr_cmnd *ipr_cmd) if ((rc == PCIBIOS_SUCCESSFUL) && (cmd_reg & PCI_COMMAND_MEMORY)) { ipr_mask_and_clear_interrupts(ioa_cfg, ~0); - writel(IPR_UPROCI_RESET_ALERT, ioa_cfg->regs.set_uproc_interrupt_reg); + writel(IPR_UPROCI_RESET_ALERT, ioa_cfg->regs.set_uproc_interrupt_reg32); ipr_cmd->job_step = ipr_reset_wait_to_start_bist; } else { ipr_cmd->job_step = ioa_cfg->reset; @@ -8104,15 +8221,23 @@ static void __devinit ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg, t->set_interrupt_mask_reg = base + p->set_interrupt_mask_reg; t->clr_interrupt_mask_reg = base + p->clr_interrupt_mask_reg; + t->clr_interrupt_mask_reg32 = base + p->clr_interrupt_mask_reg32; t->sense_interrupt_mask_reg = base + p->sense_interrupt_mask_reg; + t->sense_interrupt_mask_reg32 = base + p->sense_interrupt_mask_reg32; t->clr_interrupt_reg = base + p->clr_interrupt_reg; + t->clr_interrupt_reg32 = base + p->clr_interrupt_reg32; t->sense_interrupt_reg = base + p->sense_interrupt_reg; + t->sense_interrupt_reg32 = base + p->sense_interrupt_reg32; t->ioarrin_reg = base + p->ioarrin_reg; t->sense_uproc_interrupt_reg = base + p->sense_uproc_interrupt_reg; + t->sense_uproc_interrupt_reg32 = base + p->sense_uproc_interrupt_reg32; t->set_uproc_interrupt_reg = base + p->set_uproc_interrupt_reg; + t->set_uproc_interrupt_reg32 = base + p->set_uproc_interrupt_reg32; t->clr_uproc_interrupt_reg = base + p->clr_uproc_interrupt_reg; + t->clr_uproc_interrupt_reg32 = base + p->clr_uproc_interrupt_reg32; if (ioa_cfg->sis64) { + t->init_feedback_reg = base + p->init_feedback_reg; t->dump_addr_reg = base + p->dump_addr_reg; t->dump_data_reg = base + p->dump_data_reg; } @@ -8187,7 +8312,7 @@ static int __devinit ipr_test_msi(struct ipr_ioa_cfg *ioa_cfg, init_waitqueue_head(&ioa_cfg->msi_wait_q); ioa_cfg->msi_received = 0; ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER); - writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.clr_interrupt_mask_reg); + writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.clr_interrupt_mask_reg32); int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg); spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags); @@ -8198,7 +8323,7 @@ static int __devinit ipr_test_msi(struct ipr_ioa_cfg *ioa_cfg, } else if (ipr_debug) dev_info(&pdev->dev, "IRQ assigned: %d\n", pdev->irq); - writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.sense_interrupt_reg); + writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.sense_interrupt_reg32); int_reg = readl(ioa_cfg->regs.sense_interrupt_reg); wait_event_timeout(ioa_cfg->msi_wait_q, ioa_cfg->msi_received, HZ); ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER); @@ -8378,9 +8503,9 @@ static int __devinit ipr_probe_ioa(struct pci_dev *pdev, * If HRRQ updated interrupt is not masked, or reset alert is set, * the card is in an unknown state and needs a hard reset */ - mask = readl(ioa_cfg->regs.sense_interrupt_mask_reg); - interrupts = readl(ioa_cfg->regs.sense_interrupt_reg); - uproc = readl(ioa_cfg->regs.sense_uproc_interrupt_reg); + mask = readl(ioa_cfg->regs.sense_interrupt_mask_reg32); + interrupts = readl(ioa_cfg->regs.sense_interrupt_reg32); + uproc = readl(ioa_cfg->regs.sense_uproc_interrupt_reg32); if ((mask & IPR_PCII_HRRQ_UPDATED) == 0 || (uproc & IPR_UPROCI_RESET_ALERT)) ioa_cfg->needs_hard_reset = 1; if (interrupts & IPR_PCII_ERROR_INTERRUPTS) diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h index 36736b512846..137217e592fe 100644 --- a/drivers/scsi/ipr.h +++ b/drivers/scsi/ipr.h @@ -232,6 +232,13 @@ #define IPR_DOORBELL 0x82800000 #define IPR_RUNTIME_RESET 0x40000000 +#define IPR_IPL_INIT_MIN_STAGE_TIME 5 +#define IPR_IPL_INIT_STAGE_UNKNOWN 0x0 +#define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000 +#define IPR_IPL_INIT_STAGE_MASK 0xff000000 +#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff +#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0) + #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0) #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3) #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4) @@ -1196,14 +1203,23 @@ struct ipr_misc_cbs { struct ipr_interrupt_offsets { unsigned long set_interrupt_mask_reg; unsigned long clr_interrupt_mask_reg; + unsigned long clr_interrupt_mask_reg32; unsigned long sense_interrupt_mask_reg; + unsigned long sense_interrupt_mask_reg32; unsigned long clr_interrupt_reg; + unsigned long clr_interrupt_reg32; unsigned long sense_interrupt_reg; + unsigned long sense_interrupt_reg32; unsigned long ioarrin_reg; unsigned long sense_uproc_interrupt_reg; + unsigned long sense_uproc_interrupt_reg32; unsigned long set_uproc_interrupt_reg; + unsigned long set_uproc_interrupt_reg32; unsigned long clr_uproc_interrupt_reg; + unsigned long clr_uproc_interrupt_reg32; + + unsigned long init_feedback_reg; unsigned long dump_addr_reg; unsigned long dump_data_reg; @@ -1212,14 +1228,23 @@ struct ipr_interrupt_offsets { struct ipr_interrupts { void __iomem *set_interrupt_mask_reg; void __iomem *clr_interrupt_mask_reg; + void __iomem *clr_interrupt_mask_reg32; void __iomem *sense_interrupt_mask_reg; + void __iomem *sense_interrupt_mask_reg32; void __iomem *clr_interrupt_reg; + void __iomem *clr_interrupt_reg32; void __iomem *sense_interrupt_reg; + void __iomem *sense_interrupt_reg32; void __iomem *ioarrin_reg; void __iomem *sense_uproc_interrupt_reg; + void __iomem *sense_uproc_interrupt_reg32; void __iomem *set_uproc_interrupt_reg; + void __iomem *set_uproc_interrupt_reg32; void __iomem *clr_uproc_interrupt_reg; + void __iomem *clr_uproc_interrupt_reg32; + + void __iomem *init_feedback_reg; void __iomem *dump_addr_reg; void __iomem *dump_data_reg; -- cgit v1.2.3 From 5aa3a333eaae1016f5a72f9e0e2dce39c08762f8 Mon Sep 17 00:00:00 2001 From: Wayne Boyer Date: Fri, 19 Feb 2010 13:24:32 -0800 Subject: [SCSI] ipr: add support for new IOASCs This patch adds support for new errors that can be received from adapters using the next generation 64 bit IOA PCI interface chip. Signed-off-by: Wayne Boyer Signed-off-by: James Bottomley --- drivers/scsi/ipr.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers') diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index 10b162d607ac..7dc9fb1e14e3 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -222,6 +222,20 @@ struct ipr_error_table_t ipr_error_table[] = { "FFFE: Soft device bus error recovered by the IOA"}, {0x01088100, 0, IPR_DEFAULT_LOG_LEVEL, "4101: Soft device bus fabric error"}, + {0x01100100, 0, IPR_DEFAULT_LOG_LEVEL, + "FFFC: Logical block guard error recovered by the device"}, + {0x01100300, 0, IPR_DEFAULT_LOG_LEVEL, + "FFFC: Logical block reference tag error recovered by the device"}, + {0x01108300, 0, IPR_DEFAULT_LOG_LEVEL, + "4171: Recovered scatter list tag / sequence number error"}, + {0x01109000, 0, IPR_DEFAULT_LOG_LEVEL, + "FF3D: Recovered logical block CRC error on IOA to Host transfer"}, + {0x01109200, 0, IPR_DEFAULT_LOG_LEVEL, + "4171: Recovered logical block sequence number error on IOA to Host transfer"}, + {0x0110A000, 0, IPR_DEFAULT_LOG_LEVEL, + "FFFD: Recovered logical block reference tag error detected by the IOA"}, + {0x0110A100, 0, IPR_DEFAULT_LOG_LEVEL, + "FFFD: Logical block guard error recovered by the IOA"}, {0x01170600, 0, IPR_DEFAULT_LOG_LEVEL, "FFF9: Device sector reassign successful"}, {0x01170900, 0, IPR_DEFAULT_LOG_LEVEL, @@ -278,12 +292,28 @@ struct ipr_error_table_t ipr_error_table[] = { "3120: SCSI bus is not operational"}, {0x04088100, 0, IPR_DEFAULT_LOG_LEVEL, "4100: Hard device bus fabric error"}, + {0x04100100, 0, IPR_DEFAULT_LOG_LEVEL, + "310C: Logical block guard error detected by the device"}, + {0x04100300, 0, IPR_DEFAULT_LOG_LEVEL, + "310C: Logical block reference tag error detected by the device"}, + {0x04108300, 1, IPR_DEFAULT_LOG_LEVEL, + "4170: Scatter list tag / sequence number error"}, + {0x04109000, 1, IPR_DEFAULT_LOG_LEVEL, + "8150: Logical block CRC error on IOA to Host transfer"}, + {0x04109200, 1, IPR_DEFAULT_LOG_LEVEL, + "4170: Logical block sequence number error on IOA to Host transfer"}, + {0x0410A000, 0, IPR_DEFAULT_LOG_LEVEL, + "310D: Logical block reference tag error detected by the IOA"}, + {0x0410A100, 0, IPR_DEFAULT_LOG_LEVEL, + "310D: Logical block guard error detected by the IOA"}, {0x04118000, 0, IPR_DEFAULT_LOG_LEVEL, "9000: IOA reserved area data check"}, {0x04118100, 0, IPR_DEFAULT_LOG_LEVEL, "9001: IOA reserved area invalid data pattern"}, {0x04118200, 0, IPR_DEFAULT_LOG_LEVEL, "9002: IOA reserved area LRC error"}, + {0x04118300, 1, IPR_DEFAULT_LOG_LEVEL, + "Hardware Error, IOA metadata access error"}, {0x04320000, 0, IPR_DEFAULT_LOG_LEVEL, "102E: Out of alternate sectors for disk storage"}, {0x04330000, 1, IPR_DEFAULT_LOG_LEVEL, @@ -348,6 +378,8 @@ struct ipr_error_table_t ipr_error_table[] = { "Illegal request, commands not allowed to this device"}, {0x05258100, 0, 0, "Illegal request, command not allowed to a secondary adapter"}, + {0x05258200, 0, 0, + "Illegal request, command not allowed to a non-optimized resource"}, {0x05260000, 0, 0, "Illegal request, invalid field in parameter list"}, {0x05260100, 0, 0, -- cgit v1.2.3 From d7b4627f5f3390a2f350f16c047b3fc3eccce6d8 Mon Sep 17 00:00:00 2001 From: Wayne Boyer Date: Fri, 19 Feb 2010 13:24:38 -0800 Subject: [SCSI] ipr: adds PCI ID definitions for new adapters This patch adds the PCI ID definitions for new adapters based on the next generation 64 bit IOA PCI interface chip. New entries have been added to the ipr_pci_table[] array for the adapters and to the ipr_chip[] array for the new versions of the chip. Older entries have been removed for cards that did not ship. Signed-off-by: Wayne Boyer Signed-off-by: James Bottomley --- drivers/scsi/ipr.c | 26 +++++++++++++++++++------- drivers/scsi/ipr.h | 21 ++++++++++++++++----- 2 files changed, 35 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index 7dc9fb1e14e3..c79cd98eb6bf 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -178,7 +178,9 @@ static const struct ipr_chip_t ipr_chip[] = { { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN, IPR_USE_LSI, IPR_SIS32, &ipr_chip_cfg[0] }, { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, IPR_USE_MSI, IPR_SIS32, &ipr_chip_cfg[0] }, { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE, IPR_USE_LSI, IPR_SIS32, &ipr_chip_cfg[1] }, - { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, IPR_USE_LSI, IPR_SIS32, &ipr_chip_cfg[1] } + { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, IPR_USE_LSI, IPR_SIS32, &ipr_chip_cfg[1] }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, IPR_USE_MSI, IPR_SIS64, &ipr_chip_cfg[2] }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2, IPR_USE_MSI, IPR_SIS64, &ipr_chip_cfg[2] } }; static int ipr_max_bus_speeds [] = { @@ -8824,9 +8826,6 @@ static struct pci_device_id ipr_pci_table[] __devinitdata = { { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574E, 0, 0, IPR_USE_LONG_TRANSOP_TIMEOUT }, - { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, - PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575D, 0, 0, - IPR_USE_LONG_TRANSOP_TIMEOUT }, { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B3, 0, 0, 0 }, { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, @@ -8842,9 +8841,22 @@ static struct pci_device_id ipr_pci_table[] __devinitdata = { { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572F, 0, 0, IPR_USE_LONG_TRANSOP_TIMEOUT }, - { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SCAMP_E, - PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574D, 0, 0, - IPR_USE_LONG_TRANSOP_TIMEOUT }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, + PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B5, 0, 0, 0 }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, + PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574D, 0, 0, 0 }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, + PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B2, 0, 0, 0 }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2, + PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B4, 0, 0, 0 }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2, + PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B1, 0, 0, 0 }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2, + PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C6, 0, 0, 0 }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2, + PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575D, 0, 0, 0 }, + { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_ASIC_E2, + PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CE, 0, 0, 0 }, { } }; MODULE_DEVICE_TABLE(pci, ipr_pci_table); diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h index 137217e592fe..4c267b5e0b96 100644 --- a/drivers/scsi/ipr.h +++ b/drivers/scsi/ipr.h @@ -37,8 +37,8 @@ /* * Literals */ -#define IPR_DRIVER_VERSION "2.4.3" -#define IPR_DRIVER_DATE "(June 10, 2009)" +#define IPR_DRIVER_VERSION "2.5.0" +#define IPR_DRIVER_DATE "(February 11, 2010)" /* * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding @@ -55,7 +55,9 @@ #define IPR_NUM_BASE_CMD_BLKS 100 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339 -#define PCI_DEVICE_ID_IBM_SCAMP_E 0x034A + +#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D +#define PCI_DEVICE_ID_IBM_CROC_ASIC_E2 0x034A #define IPR_SUBS_DEV_ID_2780 0x0264 #define IPR_SUBS_DEV_ID_5702 0x0266 @@ -70,15 +72,24 @@ #define IPR_SUBS_DEV_ID_572A 0x02C1 #define IPR_SUBS_DEV_ID_572B 0x02C2 #define IPR_SUBS_DEV_ID_572F 0x02C3 -#define IPR_SUBS_DEV_ID_574D 0x030B #define IPR_SUBS_DEV_ID_574E 0x030A #define IPR_SUBS_DEV_ID_575B 0x030D #define IPR_SUBS_DEV_ID_575C 0x0338 -#define IPR_SUBS_DEV_ID_575D 0x033E #define IPR_SUBS_DEV_ID_57B3 0x033A #define IPR_SUBS_DEV_ID_57B7 0x0360 #define IPR_SUBS_DEV_ID_57B8 0x02C2 +#define IPR_SUBS_DEV_ID_57B4 0x033B +#define IPR_SUBS_DEV_ID_57B2 0x035F +#define IPR_SUBS_DEV_ID_57C6 0x0357 + +#define IPR_SUBS_DEV_ID_57B5 0x033C +#define IPR_SUBS_DEV_ID_57CE 0x035E +#define IPR_SUBS_DEV_ID_57B1 0x0355 + +#define IPR_SUBS_DEV_ID_574D 0x0356 +#define IPR_SUBS_DEV_ID_575D 0x035D + #define IPR_NAME "ipr" /* -- cgit v1.2.3 From 309ce156aa27f29338438011d292a8d6496623d3 Mon Sep 17 00:00:00 2001 From: Jayamohan Kallickal Date: Sat, 20 Feb 2010 08:02:10 +0530 Subject: [SCSI] libiscsi: Make iscsi_eh_target_reset start with session reset The iscsi_eh_target_reset has been modified to attempt target reset only. If it fails, then iscsi_eh_session_reset will be called. Signed-off-by: Mike Christie Signed-off-by: Jayamohan Kallickal Signed-off-by: James Bottomley --- drivers/infiniband/ulp/iser/iscsi_iser.c | 2 +- drivers/scsi/be2iscsi/be_main.c | 2 +- drivers/scsi/bnx2i/bnx2i_iscsi.c | 2 +- drivers/scsi/cxgb3i/cxgb3i_iscsi.c | 2 +- drivers/scsi/iscsi_tcp.c | 2 +- drivers/scsi/libiscsi.c | 23 +++++++++++++++++++---- include/scsi/libiscsi.h | 3 ++- 7 files changed, 26 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.c b/drivers/infiniband/ulp/iser/iscsi_iser.c index 5f7a6fca0a4d..5472b7e9abdc 100644 --- a/drivers/infiniband/ulp/iser/iscsi_iser.c +++ b/drivers/infiniband/ulp/iser/iscsi_iser.c @@ -596,7 +596,7 @@ static struct scsi_host_template iscsi_iser_sht = { .cmd_per_lun = ISER_DEF_CMD_PER_LUN, .eh_abort_handler = iscsi_eh_abort, .eh_device_reset_handler= iscsi_eh_device_reset, - .eh_target_reset_handler= iscsi_eh_target_reset, + .eh_target_reset_handler = iscsi_eh_recover_target, .target_alloc = iscsi_target_alloc, .use_clustering = DISABLE_CLUSTERING, .proc_name = "iscsi_iser", diff --git a/drivers/scsi/be2iscsi/be_main.c b/drivers/scsi/be2iscsi/be_main.c index 7c22616ab141..4d269b434a78 100644 --- a/drivers/scsi/be2iscsi/be_main.c +++ b/drivers/scsi/be2iscsi/be_main.c @@ -79,7 +79,7 @@ static struct scsi_host_template beiscsi_sht = { .slave_configure = beiscsi_slave_configure, .target_alloc = iscsi_target_alloc, .eh_device_reset_handler = iscsi_eh_device_reset, - .eh_target_reset_handler = iscsi_eh_target_reset, + .eh_target_reset_handler = iscsi_eh_session_reset, .sg_tablesize = BEISCSI_SGLIST_ELEMENTS, .can_queue = BE2_IO_DEPTH, .this_id = -1, diff --git a/drivers/scsi/bnx2i/bnx2i_iscsi.c b/drivers/scsi/bnx2i/bnx2i_iscsi.c index 1c4d1215769d..cb71dc984797 100644 --- a/drivers/scsi/bnx2i/bnx2i_iscsi.c +++ b/drivers/scsi/bnx2i/bnx2i_iscsi.c @@ -1989,7 +1989,7 @@ static struct scsi_host_template bnx2i_host_template = { .queuecommand = iscsi_queuecommand, .eh_abort_handler = iscsi_eh_abort, .eh_device_reset_handler = iscsi_eh_device_reset, - .eh_target_reset_handler = iscsi_eh_target_reset, + .eh_target_reset_handler = iscsi_eh_recover_target, .change_queue_depth = iscsi_change_queue_depth, .can_queue = 1024, .max_sectors = 127, diff --git a/drivers/scsi/cxgb3i/cxgb3i_iscsi.c b/drivers/scsi/cxgb3i/cxgb3i_iscsi.c index 412853c65372..b7c30585dadd 100644 --- a/drivers/scsi/cxgb3i/cxgb3i_iscsi.c +++ b/drivers/scsi/cxgb3i/cxgb3i_iscsi.c @@ -915,7 +915,7 @@ static struct scsi_host_template cxgb3i_host_template = { .cmd_per_lun = ISCSI_DEF_CMD_PER_LUN, .eh_abort_handler = iscsi_eh_abort, .eh_device_reset_handler = iscsi_eh_device_reset, - .eh_target_reset_handler = iscsi_eh_target_reset, + .eh_target_reset_handler = iscsi_eh_recover_target, .target_alloc = iscsi_target_alloc, .use_clustering = DISABLE_CLUSTERING, .this_id = -1, diff --git a/drivers/scsi/iscsi_tcp.c b/drivers/scsi/iscsi_tcp.c index 8a89ba900588..249053a9d4fa 100644 --- a/drivers/scsi/iscsi_tcp.c +++ b/drivers/scsi/iscsi_tcp.c @@ -874,7 +874,7 @@ static struct scsi_host_template iscsi_sw_tcp_sht = { .cmd_per_lun = ISCSI_DEF_CMD_PER_LUN, .eh_abort_handler = iscsi_eh_abort, .eh_device_reset_handler= iscsi_eh_device_reset, - .eh_target_reset_handler= iscsi_eh_target_reset, + .eh_target_reset_handler = iscsi_eh_recover_target, .use_clustering = DISABLE_CLUSTERING, .slave_alloc = iscsi_sw_tcp_slave_alloc, .slave_configure = iscsi_sw_tcp_slave_configure, diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c index 703eb6a88790..685eaec53218 100644 --- a/drivers/scsi/libiscsi.c +++ b/drivers/scsi/libiscsi.c @@ -2338,7 +2338,7 @@ EXPORT_SYMBOL_GPL(iscsi_session_recovery_timedout); * This function will wait for a relogin, session termination from * userspace, or a recovery/replacement timeout. */ -static int iscsi_eh_session_reset(struct scsi_cmnd *sc) +int iscsi_eh_session_reset(struct scsi_cmnd *sc) { struct iscsi_cls_session *cls_session; struct iscsi_session *session; @@ -2389,6 +2389,7 @@ failed: mutex_unlock(&session->eh_mutex); return SUCCESS; } +EXPORT_SYMBOL_GPL(iscsi_eh_session_reset); static void iscsi_prep_tgt_reset_pdu(struct scsi_cmnd *sc, struct iscsi_tm *hdr) { @@ -2403,8 +2404,7 @@ static void iscsi_prep_tgt_reset_pdu(struct scsi_cmnd *sc, struct iscsi_tm *hdr) * iscsi_eh_target_reset - reset target * @sc: scsi command * - * This will attempt to send a warm target reset. If that fails - * then we will drop the session and attempt ERL0 recovery. + * This will attempt to send a warm target reset. */ int iscsi_eh_target_reset(struct scsi_cmnd *sc) { @@ -2476,12 +2476,27 @@ done: ISCSI_DBG_EH(session, "tgt %s reset result = %s\n", session->targetname, rc == SUCCESS ? "SUCCESS" : "FAILED"); mutex_unlock(&session->eh_mutex); + return rc; +} +EXPORT_SYMBOL_GPL(iscsi_eh_target_reset); +/** + * iscsi_eh_recover_target - reset target and possibly the session + * @sc: scsi command + * + * This will attempt to send a warm target reset. If that fails, + * we will escalate to ERL0 session recovery. + */ +int iscsi_eh_recover_target(struct scsi_cmnd *sc) +{ + int rc; + + rc = iscsi_eh_target_reset(sc); if (rc == FAILED) rc = iscsi_eh_session_reset(sc); return rc; } -EXPORT_SYMBOL_GPL(iscsi_eh_target_reset); +EXPORT_SYMBOL_GPL(iscsi_eh_recover_target); /* * Pre-allocate a pool of @max items of @item_size. By default, the pool diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index ff92b46f5153..ae5196aae1a5 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -338,7 +338,8 @@ struct iscsi_host { extern int iscsi_change_queue_depth(struct scsi_device *sdev, int depth, int reason); extern int iscsi_eh_abort(struct scsi_cmnd *sc); -extern int iscsi_eh_target_reset(struct scsi_cmnd *sc); +extern int iscsi_eh_recover_target(struct scsi_cmnd *sc); +extern int iscsi_eh_session_reset(struct scsi_cmnd *sc); extern int iscsi_eh_device_reset(struct scsi_cmnd *sc); extern int iscsi_queuecommand(struct scsi_cmnd *sc, void (*done)(struct scsi_cmnd *)); -- cgit v1.2.3 From 4183122dbc7c489f11971c5afa8e42011bca7fa2 Mon Sep 17 00:00:00 2001 From: Jayamohan Kallickal Date: Sat, 20 Feb 2010 08:02:39 +0530 Subject: [SCSI] be2iscsi: Cleanup of resets for device and target This patch cleans up device and target reset handling for the driver Signed-off-by: Mike Christie Signed-off-by: Jayamohan Kallickal Signed-off-by: James Bottomley --- drivers/scsi/be2iscsi/be_main.c | 134 +++++++++++++++++++++++++++++++++++++--- drivers/scsi/be2iscsi/be_main.h | 7 +++ drivers/scsi/be2iscsi/be_mgmt.c | 14 +++-- drivers/scsi/be2iscsi/be_mgmt.h | 8 +-- 4 files changed, 145 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/be2iscsi/be_main.c b/drivers/scsi/be2iscsi/be_main.c index 4d269b434a78..eab31a515de3 100644 --- a/drivers/scsi/be2iscsi/be_main.c +++ b/drivers/scsi/be2iscsi/be_main.c @@ -58,6 +58,123 @@ static int beiscsi_slave_configure(struct scsi_device *sdev) return 0; } +static int beiscsi_eh_abort(struct scsi_cmnd *sc) +{ + struct iscsi_cls_session *cls_session; + struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr; + struct beiscsi_io_task *aborted_io_task; + struct iscsi_conn *conn; + struct beiscsi_conn *beiscsi_conn; + struct beiscsi_hba *phba; + struct iscsi_session *session; + struct invalidate_command_table *inv_tbl; + unsigned int cid, tag, num_invalidate; + + cls_session = starget_to_session(scsi_target(sc->device)); + session = cls_session->dd_data; + + spin_lock_bh(&session->lock); + if (!aborted_task || !aborted_task->sc) { + /* we raced */ + spin_unlock_bh(&session->lock); + return SUCCESS; + } + + aborted_io_task = aborted_task->dd_data; + if (!aborted_io_task->scsi_cmnd) { + /* raced or invalid command */ + spin_unlock_bh(&session->lock); + return SUCCESS; + } + spin_unlock_bh(&session->lock); + conn = aborted_task->conn; + beiscsi_conn = conn->dd_data; + phba = beiscsi_conn->phba; + + /* invalidate iocb */ + cid = beiscsi_conn->beiscsi_conn_cid; + inv_tbl = phba->inv_tbl; + memset(inv_tbl, 0x0, sizeof(*inv_tbl)); + inv_tbl->cid = cid; + inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index; + num_invalidate = 1; + tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate, cid); + if (!tag) { + shost_printk(KERN_WARNING, phba->shost, + "mgmt_invalidate_icds could not be" + " submitted\n"); + return FAILED; + } else { + wait_event_interruptible(phba->ctrl.mcc_wait[tag], + phba->ctrl.mcc_numtag[tag]); + free_mcc_tag(&phba->ctrl, tag); + } + + return iscsi_eh_abort(sc); +} + +static int beiscsi_eh_device_reset(struct scsi_cmnd *sc) +{ + struct iscsi_task *abrt_task; + struct beiscsi_io_task *abrt_io_task; + struct iscsi_conn *conn; + struct beiscsi_conn *beiscsi_conn; + struct beiscsi_hba *phba; + struct iscsi_session *session; + struct iscsi_cls_session *cls_session; + struct invalidate_command_table *inv_tbl; + unsigned int cid, tag, i, num_invalidate; + int rc = FAILED; + + /* invalidate iocbs */ + cls_session = starget_to_session(scsi_target(sc->device)); + session = cls_session->dd_data; + spin_lock_bh(&session->lock); + if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) + goto unlock; + + conn = session->leadconn; + beiscsi_conn = conn->dd_data; + phba = beiscsi_conn->phba; + cid = beiscsi_conn->beiscsi_conn_cid; + inv_tbl = phba->inv_tbl; + memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN); + num_invalidate = 0; + for (i = 0; i < conn->session->cmds_max; i++) { + abrt_task = conn->session->cmds[i]; + abrt_io_task = abrt_task->dd_data; + if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE) + continue; + + if (abrt_task->sc->device->lun != abrt_task->sc->device->lun) + continue; + + inv_tbl->cid = cid; + inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index; + num_invalidate++; + inv_tbl++; + } + spin_unlock_bh(&session->lock); + inv_tbl = phba->inv_tbl; + + tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate, cid); + if (!tag) { + shost_printk(KERN_WARNING, phba->shost, + "mgmt_invalidate_icds could not be" + " submitted\n"); + return FAILED; + } else { + wait_event_interruptible(phba->ctrl.mcc_wait[tag], + phba->ctrl.mcc_numtag[tag]); + free_mcc_tag(&phba->ctrl, tag); + } + + return iscsi_eh_device_reset(sc); +unlock: + spin_unlock_bh(&session->lock); + return rc; +} + /*------------------- PCI Driver operations and data ----------------- */ static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = { { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) }, @@ -74,11 +191,11 @@ static struct scsi_host_template beiscsi_sht = { .name = "ServerEngines 10Gbe open-iscsi Initiator Driver", .proc_name = DRV_NAME, .queuecommand = iscsi_queuecommand, - .eh_abort_handler = iscsi_eh_abort, .change_queue_depth = iscsi_change_queue_depth, .slave_configure = beiscsi_slave_configure, .target_alloc = iscsi_target_alloc, - .eh_device_reset_handler = iscsi_eh_device_reset, + .eh_abort_handler = beiscsi_eh_abort, + .eh_device_reset_handler = beiscsi_eh_device_reset, .eh_target_reset_handler = iscsi_eh_session_reset, .sg_tablesize = BEISCSI_SGLIST_ELEMENTS, .can_queue = BE2_IO_DEPTH, @@ -3486,9 +3603,9 @@ static int beiscsi_mtask(struct iscsi_task *task) struct hwi_wrb_context *pwrb_context; struct wrb_handle *pwrb_handle; unsigned int doorbell = 0; - unsigned int i, cid; + struct invalidate_command_table *inv_tbl; struct iscsi_task *aborted_task; - unsigned int tag; + unsigned int i, cid, tag, num_invalidate; cid = beiscsi_conn->beiscsi_conn_cid; pwrb = io_task->pwrb_handle->pwrb; @@ -3538,9 +3655,12 @@ static int beiscsi_mtask(struct iscsi_task *task) if (!aborted_io_task->scsi_cmnd) return 0; - tag = mgmt_invalidate_icds(phba, - aborted_io_task->psgl_handle->sgl_index, - cid); + inv_tbl = phba->inv_tbl; + memset(inv_tbl, 0x0, sizeof(*inv_tbl)); + inv_tbl->cid = cid; + inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index; + num_invalidate = 1; + tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate, cid); if (!tag) { shost_printk(KERN_WARNING, phba->shost, "mgmt_invalidate_icds could not be" diff --git a/drivers/scsi/be2iscsi/be_main.h b/drivers/scsi/be2iscsi/be_main.h index c53a80ab796c..d4d31dc09088 100644 --- a/drivers/scsi/be2iscsi/be_main.h +++ b/drivers/scsi/be2iscsi/be_main.h @@ -257,6 +257,11 @@ struct hba_parameters { unsigned int num_sge; }; +struct invalidate_command_table { + unsigned short icd; + unsigned short cid; +} __packed; + struct beiscsi_hba { struct hba_parameters params; struct hwi_controller *phwi_ctrlr; @@ -329,6 +334,8 @@ struct beiscsi_hba { struct work_struct work_cqs; /* The work being queued */ struct be_ctrl_info ctrl; unsigned int generation; + struct invalidate_command_table inv_tbl[128]; + }; struct beiscsi_session { diff --git a/drivers/scsi/be2iscsi/be_mgmt.c b/drivers/scsi/be2iscsi/be_mgmt.c index 317bcd042ced..72617b650a7e 100644 --- a/drivers/scsi/be2iscsi/be_mgmt.c +++ b/drivers/scsi/be2iscsi/be_mgmt.c @@ -145,14 +145,15 @@ unsigned char mgmt_epfw_cleanup(struct beiscsi_hba *phba, unsigned short chute) } unsigned char mgmt_invalidate_icds(struct beiscsi_hba *phba, - unsigned int icd, unsigned int cid) + struct invalidate_command_table *inv_tbl, + unsigned int num_invalidate, unsigned int cid) { struct be_dma_mem nonemb_cmd; struct be_ctrl_info *ctrl = &phba->ctrl; struct be_mcc_wrb *wrb; struct be_sge *sge; struct invalidate_commands_params_in *req; - unsigned int tag = 0; + unsigned int i, tag = 0; spin_lock(&ctrl->mbox_lock); tag = alloc_mcc_tag(phba); @@ -183,9 +184,12 @@ unsigned char mgmt_invalidate_icds(struct beiscsi_hba *phba, sizeof(*req)); req->ref_handle = 0; req->cleanup_type = CMD_ISCSI_COMMAND_INVALIDATE; - req->icd_count = 0; - req->table[req->icd_count].icd = icd; - req->table[req->icd_count].cid = cid; + for (i = 0; i < num_invalidate; i++) { + req->table[i].icd = inv_tbl->icd; + req->table[i].cid = inv_tbl->cid; + req->icd_count++; + inv_tbl++; + } sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd.dma)); sge->pa_lo = cpu_to_le32(nonemb_cmd.dma & 0xFFFFFFFF); sge->len = cpu_to_le32(nonemb_cmd.size); diff --git a/drivers/scsi/be2iscsi/be_mgmt.h b/drivers/scsi/be2iscsi/be_mgmt.h index ecead6a5aa56..3d316b82feb1 100644 --- a/drivers/scsi/be2iscsi/be_mgmt.h +++ b/drivers/scsi/be2iscsi/be_mgmt.h @@ -94,7 +94,8 @@ unsigned char mgmt_upload_connection(struct beiscsi_hba *phba, unsigned short cid, unsigned int upload_flag); unsigned char mgmt_invalidate_icds(struct beiscsi_hba *phba, - unsigned int icd, unsigned int cid); + struct invalidate_command_table *inv_tbl, + unsigned int num_invalidate, unsigned int cid); struct iscsi_invalidate_connection_params_in { struct be_cmd_req_hdr hdr; @@ -116,11 +117,6 @@ union iscsi_invalidate_connection_params { struct iscsi_invalidate_connection_params_out response; } __packed; -struct invalidate_command_table { - unsigned short icd; - unsigned short cid; -} __packed; - struct invalidate_commands_params_in { struct be_cmd_req_hdr hdr; unsigned int ref_handle; -- cgit v1.2.3 From 944b2fbce26ce39555363fd092386807fa5ea08c Mon Sep 17 00:00:00 2001 From: Jayamohan Kallickal Date: Sat, 20 Feb 2010 08:03:24 +0530 Subject: [SCSI] be2iscsi: Fix for a possible udelay while holding lock This patch fixes a situation where we could call udelay while holding spin_lock Signed-off-by: Jayamohan Kallickal Signed-off-by: James Bottomley --- drivers/scsi/be2iscsi/be_cmds.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/be2iscsi/be_cmds.c b/drivers/scsi/be2iscsi/be_cmds.c index 67098578fba4..cda6642c7368 100644 --- a/drivers/scsi/be2iscsi/be_cmds.c +++ b/drivers/scsi/be2iscsi/be_cmds.c @@ -32,18 +32,11 @@ void be_mcc_notify(struct beiscsi_hba *phba) unsigned int alloc_mcc_tag(struct beiscsi_hba *phba) { unsigned int tag = 0; - unsigned int num = 0; -mcc_tag_rdy: if (phba->ctrl.mcc_tag_available) { tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index]; phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0; phba->ctrl.mcc_numtag[tag] = 0; - } else { - udelay(100); - num++; - if (num < mcc_timeout) - goto mcc_tag_rdy; } if (tag) { phba->ctrl.mcc_tag_available--; -- cgit v1.2.3 From dafab8e079f432268cca5cf378b92d6acfacc393 Mon Sep 17 00:00:00 2001 From: Jayamohan Kallickal Date: Sat, 20 Feb 2010 08:03:56 +0530 Subject: [SCSI] be2iscsi: cleans up abort handling This patch cleans up abort handling when TMF is sent Signed-off-by: Jayamohan Kallickal Signed-off-by: James Bottomley --- drivers/scsi/be2iscsi/be_main.c | 62 ++++++++--------------------------------- 1 file changed, 11 insertions(+), 51 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/be2iscsi/be_main.c b/drivers/scsi/be2iscsi/be_main.c index eab31a515de3..aee3734d8617 100644 --- a/drivers/scsi/be2iscsi/be_main.c +++ b/drivers/scsi/be2iscsi/be_main.c @@ -1063,14 +1063,18 @@ static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn, case HWH_TYPE_IO: case HWH_TYPE_IO_RD: if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == - ISCSI_OP_NOOP_OUT) { + ISCSI_OP_NOOP_OUT) be_complete_nopin_resp(beiscsi_conn, task, psol); - } else + else be_complete_io(beiscsi_conn, task, psol); break; case HWH_TYPE_LOGOUT: - be_complete_logout(beiscsi_conn, task, psol); + if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT) + be_complete_logout(beiscsi_conn, task, psol); + else + be_complete_tmf(beiscsi_conn, task, psol); + break; case HWH_TYPE_LOGIN: @@ -1079,10 +1083,6 @@ static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn, "- Solicited path \n"); break; - case HWH_TYPE_TMF: - be_complete_tmf(beiscsi_conn, task, psol); - break; - case HWH_TYPE_NOP: be_complete_nopin_resp(beiscsi_conn, task, psol); break; @@ -3593,19 +3593,13 @@ static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg, static int beiscsi_mtask(struct iscsi_task *task) { - struct beiscsi_io_task *aborted_io_task, *io_task = task->dd_data; + struct beiscsi_io_task *io_task = task->dd_data; struct iscsi_conn *conn = task->conn; struct beiscsi_conn *beiscsi_conn = conn->dd_data; struct beiscsi_hba *phba = beiscsi_conn->phba; - struct iscsi_session *session; struct iscsi_wrb *pwrb = NULL; - struct hwi_controller *phwi_ctrlr; - struct hwi_wrb_context *pwrb_context; - struct wrb_handle *pwrb_handle; unsigned int doorbell = 0; - struct invalidate_command_table *inv_tbl; - struct iscsi_task *aborted_task; - unsigned int i, cid, tag, num_invalidate; + unsigned int cid; cid = beiscsi_conn->beiscsi_conn_cid; pwrb = io_task->pwrb_handle->pwrb; @@ -3616,6 +3610,7 @@ static int beiscsi_mtask(struct iscsi_task *task) io_task->pwrb_handle->wrb_index); AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb, io_task->psgl_handle->sgl_index); + switch (task->hdr->opcode & ISCSI_OPCODE_MASK) { case ISCSI_OP_LOGIN: AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, @@ -3640,36 +3635,6 @@ static int beiscsi_mtask(struct iscsi_task *task) hwi_write_buffer(pwrb, task); break; case ISCSI_OP_SCSI_TMFUNC: - session = conn->session; - i = ((struct iscsi_tm *)task->hdr)->rtt; - phwi_ctrlr = phba->phwi_ctrlr; - pwrb_context = &phwi_ctrlr->wrb_context[cid - - phba->fw_config.iscsi_cid_start]; - pwrb_handle = pwrb_context->pwrb_handle_basestd[be32_to_cpu(i) - >> 16]; - aborted_task = pwrb_handle->pio_handle; - if (!aborted_task) - return 0; - - aborted_io_task = aborted_task->dd_data; - if (!aborted_io_task->scsi_cmnd) - return 0; - - inv_tbl = phba->inv_tbl; - memset(inv_tbl, 0x0, sizeof(*inv_tbl)); - inv_tbl->cid = cid; - inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index; - num_invalidate = 1; - tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate, cid); - if (!tag) { - shost_printk(KERN_WARNING, phba->shost, - "mgmt_invalidate_icds could not be" - " submitted\n"); - } else { - wait_event_interruptible(phba->ctrl.mcc_wait[tag], - phba->ctrl.mcc_numtag[tag]); - free_mcc_tag(&phba->ctrl, tag); - } AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, INI_TMF_CMD); AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0); @@ -3678,7 +3643,7 @@ static int beiscsi_mtask(struct iscsi_task *task) case ISCSI_OP_LOGOUT: AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0); AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, - HWH_TYPE_LOGOUT); + HWH_TYPE_LOGOUT); hwi_write_buffer(pwrb, task); break; @@ -3704,17 +3669,12 @@ static int beiscsi_mtask(struct iscsi_task *task) static int beiscsi_task_xmit(struct iscsi_task *task) { - struct iscsi_conn *conn = task->conn; struct beiscsi_io_task *io_task = task->dd_data; struct scsi_cmnd *sc = task->sc; - struct beiscsi_conn *beiscsi_conn = conn->dd_data; struct scatterlist *sg; int num_sg; unsigned int writedir = 0, xferlen = 0; - SE_DEBUG(DBG_LVL_4, "\n cid=%d In beiscsi_task_xmit task=%p conn=%p \t" - "beiscsi_conn=%p \n", beiscsi_conn->beiscsi_conn_cid, - task, conn, beiscsi_conn); if (!sc) return beiscsi_mtask(task); -- cgit v1.2.3 From 90a289e87648f80b63178c463aa7daaf5205805c Mon Sep 17 00:00:00 2001 From: Jayamohan Kallickal Date: Sat, 20 Feb 2010 08:04:28 +0530 Subject: [SCSI] be2iscsi: Remove debug code This patch removes some debug lines which are unnecessary and also aligns some lines in code Signed-off-by: Jayamohan Kallickal Signed-off-by: James Bottomley --- drivers/scsi/be2iscsi/be_iscsi.c | 4 ++-- drivers/scsi/be2iscsi/be_main.c | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/be2iscsi/be_iscsi.c b/drivers/scsi/be2iscsi/be_iscsi.c index 29a3aaf35f9f..c3928cb8b042 100644 --- a/drivers/scsi/be2iscsi/be_iscsi.c +++ b/drivers/scsi/be2iscsi/be_iscsi.c @@ -482,7 +482,7 @@ static int beiscsi_open_conn(struct iscsi_endpoint *ep, tag = mgmt_open_connection(phba, dst_addr, beiscsi_ep); if (!tag) { SE_DEBUG(DBG_LVL_1, - "mgmt_invalidate_connection Failed for cid=%d \n", + "mgmt_open_connection Failed for cid=%d \n", beiscsi_ep->ep_cid); } else { wait_event_interruptible(phba->ctrl.mcc_wait[tag], @@ -701,7 +701,7 @@ void beiscsi_conn_stop(struct iscsi_cls_conn *cls_conn, int flag) if (!tag) { SE_DEBUG(DBG_LVL_1, "mgmt_invalidate_connection Failed for cid=%d \n", - beiscsi_ep->ep_cid); + beiscsi_ep->ep_cid); } else { wait_event_interruptible(phba->ctrl.mcc_wait[tag], phba->ctrl.mcc_numtag[tag]); diff --git a/drivers/scsi/be2iscsi/be_main.c b/drivers/scsi/be2iscsi/be_main.c index aee3734d8617..b5dca45bae96 100644 --- a/drivers/scsi/be2iscsi/be_main.c +++ b/drivers/scsi/be2iscsi/be_main.c @@ -3779,7 +3779,6 @@ static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev, " Failed in beiscsi_hba_alloc \n"); goto disable_pci; } - SE_DEBUG(DBG_LVL_8, " phba = %p \n", phba); switch (pcidev->device) { case BE_DEVICE_ID1: -- cgit v1.2.3 From ed58ea2ab58c7d80a07a829a1cc2c4161c300494 Mon Sep 17 00:00:00 2001 From: Jayamohan Kallickal Date: Sat, 20 Feb 2010 08:05:07 +0530 Subject: [SCSI] be2iscsi: Fixing memory allocation for connection This patch fixes some situations where enough resources were not avaialable when targets exceeded a certain limit Signed-off-by: Jayamohan Kallickal Signed-off-by: James Bottomley --- drivers/scsi/be2iscsi/be_main.c | 4 ++-- drivers/scsi/be2iscsi/be_main.h | 4 +--- 2 files changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/be2iscsi/be_main.c b/drivers/scsi/be2iscsi/be_main.c index b5dca45bae96..5887d7a0e3ff 100644 --- a/drivers/scsi/be2iscsi/be_main.c +++ b/drivers/scsi/be2iscsi/be_main.c @@ -359,7 +359,7 @@ static void beiscsi_get_params(struct beiscsi_hba *phba) + BE2_TMFS + BE2_NOPOUT_REQ)); phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count; - phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count;; + phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2; phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;; phba->params.num_sge_per_io = BE2_SGE; phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ; @@ -2169,7 +2169,7 @@ static void beiscsi_init_wrb_handle(struct beiscsi_hba *phba) num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) / ((sizeof(struct iscsi_wrb) * phba->params.wrbs_per_cxn)); - for (index = 0; index < phba->params.cxns_per_ctrl; index += 2) { + for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) { pwrb_context = &phwi_ctrlr->wrb_context[index]; if (num_cxn_wrb) { for (j = 0; j < phba->params.wrbs_per_cxn; j++) { diff --git a/drivers/scsi/be2iscsi/be_main.h b/drivers/scsi/be2iscsi/be_main.h index d4d31dc09088..87ec21280a37 100644 --- a/drivers/scsi/be2iscsi/be_main.h +++ b/drivers/scsi/be2iscsi/be_main.h @@ -498,8 +498,6 @@ struct hwi_async_entry { struct list_head data_busy_list; }; -#define BE_MIN_ASYNC_ENTRIES 128 - struct hwi_async_pdu_context { struct { struct be_bus_address pa_base; @@ -540,7 +538,7 @@ struct hwi_async_pdu_context { * This is a varying size list! Do not add anything * after this entry!! */ - struct hwi_async_entry async_entry[BE_MIN_ASYNC_ENTRIES]; + struct hwi_async_entry async_entry[BE2_MAX_SESSIONS * 2]; }; #define PDUCQE_CODE_MASK 0x0000003F -- cgit v1.2.3 From c03af1ae1cce97a5530b907ea03625ce6e00214e Mon Sep 17 00:00:00 2001 From: Jayamohan Kallickal Date: Sat, 20 Feb 2010 08:05:43 +0530 Subject: [SCSI] be2iscsi: Alloc only one EQ if intr mode This patch ensures that we alloc only one EQ if we are if we are not in msix mode Signed-off-by: Jayamohan Kallickal Signed-off-by: James Bottomley --- drivers/scsi/be2iscsi/be_main.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/be2iscsi/be_main.c b/drivers/scsi/be2iscsi/be_main.c index 5887d7a0e3ff..fcfb29e02d8a 100644 --- a/drivers/scsi/be2iscsi/be_main.c +++ b/drivers/scsi/be2iscsi/be_main.c @@ -3190,14 +3190,18 @@ static unsigned char hwi_enable_intr(struct beiscsi_hba *phba) reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; SE_DEBUG(DBG_LVL_8, "reg =x%08x addr=%p \n", reg, addr); iowrite32(reg, addr); - for (i = 0; i <= phba->num_cpus; i++) { - eq = &phwi_context->be_eq[i].q; + if (!phba->msix_enabled) { + eq = &phwi_context->be_eq[0].q; SE_DEBUG(DBG_LVL_8, "eq->id=%d \n", eq->id); hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); + } else { + for (i = 0; i <= phba->num_cpus; i++) { + eq = &phwi_context->be_eq[i].q; + SE_DEBUG(DBG_LVL_8, "eq->id=%d \n", eq->id); + hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); + } } - } else - shost_printk(KERN_WARNING, phba->shost, - "In hwi_enable_intr, Not Enabled \n"); + } return true; } -- cgit v1.2.3 From 64355b929dec0cb6271e4ac7834c9cf262961e40 Mon Sep 17 00:00:00 2001 From: Brian King Date: Sun, 21 Feb 2010 10:37:57 -0600 Subject: [SCSI] ibmvscsi: Add suspend/resume support Adds support for resuming from suspend for IBM VSCSI devices. We may have lost an interrupt over the suspend, so we just kick the interrupt handler to process anything that is outstanding. We expect to find a transport event indicating we need to reestablish our CRQ. Signed-off-by: Brian King Signed-off-by: James Bottomley --- drivers/scsi/ibmvscsi/ibmvscsi.c | 19 +++++++++++++++++++ drivers/scsi/ibmvscsi/ibmvscsi.h | 1 + drivers/scsi/ibmvscsi/iseries_vscsi.c | 6 ++++++ drivers/scsi/ibmvscsi/rpa_vscsi.c | 13 +++++++++++++ 4 files changed, 39 insertions(+) (limited to 'drivers') diff --git a/drivers/scsi/ibmvscsi/ibmvscsi.c b/drivers/scsi/ibmvscsi/ibmvscsi.c index e3a18e0ef276..dc1bcbe3b176 100644 --- a/drivers/scsi/ibmvscsi/ibmvscsi.c +++ b/drivers/scsi/ibmvscsi/ibmvscsi.c @@ -71,6 +71,7 @@ #include #include #include +#include #include #include #include @@ -1990,6 +1991,19 @@ static int ibmvscsi_remove(struct vio_dev *vdev) return 0; } +/** + * ibmvscsi_resume: Resume from suspend + * @dev: device struct + * + * We may have lost an interrupt across suspend/resume, so kick the + * interrupt handler + */ +static int ibmvscsi_resume(struct device *dev) +{ + struct ibmvscsi_host_data *hostdata = dev_get_drvdata(dev); + return ibmvscsi_ops->resume(hostdata); +} + /** * ibmvscsi_device_table: Used by vio.c to match devices in the device tree we * support. @@ -2000,6 +2014,10 @@ static struct vio_device_id ibmvscsi_device_table[] __devinitdata = { }; MODULE_DEVICE_TABLE(vio, ibmvscsi_device_table); +static struct dev_pm_ops ibmvscsi_pm_ops = { + .resume = ibmvscsi_resume +}; + static struct vio_driver ibmvscsi_driver = { .id_table = ibmvscsi_device_table, .probe = ibmvscsi_probe, @@ -2008,6 +2026,7 @@ static struct vio_driver ibmvscsi_driver = { .driver = { .name = "ibmvscsi", .owner = THIS_MODULE, + .pm = &ibmvscsi_pm_ops, } }; diff --git a/drivers/scsi/ibmvscsi/ibmvscsi.h b/drivers/scsi/ibmvscsi/ibmvscsi.h index 76425303def0..9cb7c6a773e1 100644 --- a/drivers/scsi/ibmvscsi/ibmvscsi.h +++ b/drivers/scsi/ibmvscsi/ibmvscsi.h @@ -120,6 +120,7 @@ struct ibmvscsi_ops { struct ibmvscsi_host_data *hostdata); int (*send_crq)(struct ibmvscsi_host_data *hostdata, u64 word1, u64 word2); + int (*resume) (struct ibmvscsi_host_data *hostdata); }; extern struct ibmvscsi_ops iseriesvscsi_ops; diff --git a/drivers/scsi/ibmvscsi/iseries_vscsi.c b/drivers/scsi/ibmvscsi/iseries_vscsi.c index 0775fdee5fa8..f4776451a754 100644 --- a/drivers/scsi/ibmvscsi/iseries_vscsi.c +++ b/drivers/scsi/ibmvscsi/iseries_vscsi.c @@ -158,10 +158,16 @@ static int iseriesvscsi_send_crq(struct ibmvscsi_host_data *hostdata, 0); } +static int iseriesvscsi_resume(struct ibmvscsi_host_data *hostdata) +{ + return 0; +} + struct ibmvscsi_ops iseriesvscsi_ops = { .init_crq_queue = iseriesvscsi_init_crq_queue, .release_crq_queue = iseriesvscsi_release_crq_queue, .reset_crq_queue = iseriesvscsi_reset_crq_queue, .reenable_crq_queue = iseriesvscsi_reenable_crq_queue, .send_crq = iseriesvscsi_send_crq, + .resume = iseriesvscsi_resume, }; diff --git a/drivers/scsi/ibmvscsi/rpa_vscsi.c b/drivers/scsi/ibmvscsi/rpa_vscsi.c index 462a8574dad9..63a30cbbf9de 100644 --- a/drivers/scsi/ibmvscsi/rpa_vscsi.c +++ b/drivers/scsi/ibmvscsi/rpa_vscsi.c @@ -334,10 +334,23 @@ static int rpavscsi_reenable_crq_queue(struct crq_queue *queue, return rc; } +/** + * rpavscsi_resume: - resume after suspend + * @hostdata: ibmvscsi_host_data of host + * + */ +static int rpavscsi_resume(struct ibmvscsi_host_data *hostdata) +{ + vio_disable_interrupts(to_vio_dev(hostdata->dev)); + tasklet_schedule(&hostdata->srp_task); + return 0; +} + struct ibmvscsi_ops rpavscsi_ops = { .init_crq_queue = rpavscsi_init_crq_queue, .release_crq_queue = rpavscsi_release_crq_queue, .reset_crq_queue = rpavscsi_reset_crq_queue, .reenable_crq_queue = rpavscsi_reenable_crq_queue, .send_crq = rpavscsi_send_crq, + .resume = rpavscsi_resume, }; -- cgit v1.2.3 From b0f4d4cf12d0eaa0bd766686bba843fc105b6a60 Mon Sep 17 00:00:00 2001 From: Brian King Date: Sun, 21 Feb 2010 10:37:58 -0600 Subject: [SCSI] ibmvfc: Add suspend/resume support Adds support for resuming from suspend for IBM VFC devices. We may have lost an interrupt over the suspend, so we just kick the interrupt handler to process anything that is outstanding. We expect to find a transport event indicating we need to reestablish our CRQ. Signed-off-by: Brian King Signed-off-by: James Bottomley --- drivers/scsi/ibmvscsi/ibmvfc.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'drivers') diff --git a/drivers/scsi/ibmvscsi/ibmvfc.c b/drivers/scsi/ibmvscsi/ibmvfc.c index 732f6d35b4a8..4e577e2fee38 100644 --- a/drivers/scsi/ibmvscsi/ibmvfc.c +++ b/drivers/scsi/ibmvscsi/ibmvfc.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -4735,6 +4736,27 @@ static int ibmvfc_remove(struct vio_dev *vdev) return 0; } +/** + * ibmvfc_resume - Resume from suspend + * @dev: device struct + * + * We may have lost an interrupt across suspend/resume, so kick the + * interrupt handler + * + */ +static int ibmvfc_resume(struct device *dev) +{ + unsigned long flags; + struct ibmvfc_host *vhost = dev_get_drvdata(dev); + struct vio_dev *vdev = to_vio_dev(dev); + + spin_lock_irqsave(vhost->host->host_lock, flags); + vio_disable_interrupts(vdev); + tasklet_schedule(&vhost->tasklet); + spin_unlock_irqrestore(vhost->host->host_lock, flags); + return 0; +} + /** * ibmvfc_get_desired_dma - Calculate DMA resources needed by the driver * @vdev: vio device struct @@ -4755,6 +4777,10 @@ static struct vio_device_id ibmvfc_device_table[] __devinitdata = { }; MODULE_DEVICE_TABLE(vio, ibmvfc_device_table); +static struct dev_pm_ops ibmvfc_pm_ops = { + .resume = ibmvfc_resume +}; + static struct vio_driver ibmvfc_driver = { .id_table = ibmvfc_device_table, .probe = ibmvfc_probe, @@ -4763,6 +4789,7 @@ static struct vio_driver ibmvfc_driver = { .driver = { .name = IBMVFC_NAME, .owner = THIS_MODULE, + .pm = &ibmvfc_pm_ops, } }; -- cgit v1.2.3 From 667e23d4e968f6826dc5d3e81238a7f1f343fb4f Mon Sep 17 00:00:00 2001 From: "Stephen M. Cameron" Date: Thu, 25 Feb 2010 14:02:51 -0600 Subject: [SCSI] hpsa: allow modifying device queue depth. Signed-off-by: Stephen M. Cameron Signed-off-by: James Bottomley --- drivers/scsi/hpsa.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'drivers') diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c index 03697ba94251..745c62444d25 100644 --- a/drivers/scsi/hpsa.c +++ b/drivers/scsi/hpsa.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -134,6 +135,8 @@ static int hpsa_scsi_queue_command(struct scsi_cmnd *cmd, static void hpsa_scan_start(struct Scsi_Host *); static int hpsa_scan_finished(struct Scsi_Host *sh, unsigned long elapsed_time); +static int hpsa_change_queue_depth(struct scsi_device *sdev, + int qdepth, int reason); static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd); static int hpsa_slave_alloc(struct scsi_device *sdev); @@ -182,6 +185,7 @@ static struct scsi_host_template hpsa_driver_template = { .queuecommand = hpsa_scsi_queue_command, .scan_start = hpsa_scan_start, .scan_finished = hpsa_scan_finished, + .change_queue_depth = hpsa_change_queue_depth, .this_id = -1, .sg_tablesize = MAXSGENTRIES, .use_clustering = ENABLE_CLUSTERING, @@ -2077,6 +2081,23 @@ static int hpsa_scan_finished(struct Scsi_Host *sh, return finished; } +static int hpsa_change_queue_depth(struct scsi_device *sdev, + int qdepth, int reason) +{ + struct ctlr_info *h = sdev_to_hba(sdev); + + if (reason != SCSI_QDEPTH_DEFAULT) + return -ENOTSUPP; + + if (qdepth < 1) + qdepth = 1; + else + if (qdepth > h->nr_cmds) + qdepth = h->nr_cmds; + scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth); + return sdev->queue_depth; +} + static void hpsa_unregister_scsi(struct ctlr_info *h) { /* we are being forcibly unloaded, and may not refuse. */ -- cgit v1.2.3 From f0edafc6628f924a424ab4059df74f46f4f4241e Mon Sep 17 00:00:00 2001 From: "Stephen M. Cameron" Date: Thu, 25 Feb 2010 14:02:56 -0600 Subject: [SCSI] hpsa: fix firmwart typo Signed-off-by: Stephen M. Cameron Signed-off-by: James Bottomley --- drivers/scsi/hpsa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c index 745c62444d25..3734f31d08a8 100644 --- a/drivers/scsi/hpsa.c +++ b/drivers/scsi/hpsa.c @@ -2982,7 +2982,7 @@ static irqreturn_t do_hpsa_intr(int irq, void *dev_id) return IRQ_HANDLED; } -/* Send a message CDB to the firmwart. */ +/* Send a message CDB to the firmware. */ static __devinit int hpsa_message(struct pci_dev *pdev, unsigned char opcode, unsigned char type) { -- cgit v1.2.3 From 5512672f75611e9239669c6a4dce648b8d60fedd Mon Sep 17 00:00:00 2001 From: "Stephen M. Cameron" Date: Thu, 25 Feb 2010 14:03:01 -0600 Subject: [SCSI] hpsa: fix scsi status mis-shift The SCSI status does not need to be shifted. Signed-off-by: Stephen M. Cameron Signed-off-by: James Bottomley --- drivers/scsi/hpsa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c index 3734f31d08a8..604b4c95a440 100644 --- a/drivers/scsi/hpsa.c +++ b/drivers/scsi/hpsa.c @@ -1006,7 +1006,7 @@ static void complete_scsi_command(struct CommandList *cp, cmd->result = (DID_OK << 16); /* host byte */ cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ - cmd->result |= (ei->ScsiStatus << 1); + cmd->result |= ei->ScsiStatus; /* copy the sense data whether we need to or not. */ memcpy(cmd->sense_buffer, ei->SenseInfo, -- cgit v1.2.3 From e9ea04a65ad842452cbee92b5c865af7fed17f63 Mon Sep 17 00:00:00 2001 From: "Stephen M. Cameron" Date: Thu, 25 Feb 2010 14:03:06 -0600 Subject: [SCSI] hpsa: return -ENOMEM, not -1 Signed-off-by: Stephen M. Cameron Signed-off-by: James Bottomley --- drivers/scsi/hpsa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c index 604b4c95a440..a72a18eabe24 100644 --- a/drivers/scsi/hpsa.c +++ b/drivers/scsi/hpsa.c @@ -1386,7 +1386,7 @@ static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr) if (c == NULL) { /* trouble... */ dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n"); - return -1; + return -ENOMEM; } fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, scsi3addr, TYPE_MSG); -- cgit v1.2.3 From 31468401ccf64322ca99fe05fbe64f1551240f57 Mon Sep 17 00:00:00 2001 From: Mike Miller Date: Thu, 25 Feb 2010 14:03:12 -0600 Subject: [SCSI] hpsa: remove scan thread The intent of the scan thread was to allow a UNIT ATTENTION/LUN DATA CHANGED condition encountered in the interrupt handler to trigger a rescan of devices, which can't be done in interrupt context. However, we weren't able to get this to work, due to multiple such UNIT ATTENTION conditions arriving during the rescan, during updating of the SCSI mid layer, etc. There's no way to tell the devices, "stand still while I scan you!" Since it doesn't work, there's no point in having the thread, as the rescan triggered via ioctl or sysfs can be done without such a thread. Signed-off-by: Mike Miller Signed-off-by: Stephen M. Cameron Signed-off-by: James Bottomley --- drivers/scsi/hpsa.c | 167 ++-------------------------------------------------- drivers/scsi/hpsa.h | 3 - 2 files changed, 4 insertions(+), 166 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c index a72a18eabe24..3d43bb245ac8 100644 --- a/drivers/scsi/hpsa.c +++ b/drivers/scsi/hpsa.c @@ -53,7 +53,7 @@ #include "hpsa.h" /* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */ -#define HPSA_DRIVER_VERSION "2.0.1-3" +#define HPSA_DRIVER_VERSION "2.0.2-1" #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")" /* How long to wait (in milliseconds) for board to go into simple mode */ @@ -212,133 +212,6 @@ static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh) return (struct ctlr_info *) *priv; } -static struct task_struct *hpsa_scan_thread; -static DEFINE_MUTEX(hpsa_scan_mutex); -static LIST_HEAD(hpsa_scan_q); -static int hpsa_scan_func(void *data); - -/** - * add_to_scan_list() - add controller to rescan queue - * @h: Pointer to the controller. - * - * Adds the controller to the rescan queue if not already on the queue. - * - * returns 1 if added to the queue, 0 if skipped (could be on the - * queue already, or the controller could be initializing or shutting - * down). - **/ -static int add_to_scan_list(struct ctlr_info *h) -{ - struct ctlr_info *test_h; - int found = 0; - int ret = 0; - - if (h->busy_initializing) - return 0; - - /* - * If we don't get the lock, it means the driver is unloading - * and there's no point in scheduling a new scan. - */ - if (!mutex_trylock(&h->busy_shutting_down)) - return 0; - - mutex_lock(&hpsa_scan_mutex); - list_for_each_entry(test_h, &hpsa_scan_q, scan_list) { - if (test_h == h) { - found = 1; - break; - } - } - if (!found && !h->busy_scanning) { - INIT_COMPLETION(h->scan_wait); - list_add_tail(&h->scan_list, &hpsa_scan_q); - ret = 1; - } - mutex_unlock(&hpsa_scan_mutex); - mutex_unlock(&h->busy_shutting_down); - - return ret; -} - -/** - * remove_from_scan_list() - remove controller from rescan queue - * @h: Pointer to the controller. - * - * Removes the controller from the rescan queue if present. Blocks if - * the controller is currently conducting a rescan. The controller - * can be in one of three states: - * 1. Doesn't need a scan - * 2. On the scan list, but not scanning yet (we remove it) - * 3. Busy scanning (and not on the list). In this case we want to wait for - * the scan to complete to make sure the scanning thread for this - * controller is completely idle. - **/ -static void remove_from_scan_list(struct ctlr_info *h) -{ - struct ctlr_info *test_h, *tmp_h; - - mutex_lock(&hpsa_scan_mutex); - list_for_each_entry_safe(test_h, tmp_h, &hpsa_scan_q, scan_list) { - if (test_h == h) { /* state 2. */ - list_del(&h->scan_list); - complete_all(&h->scan_wait); - mutex_unlock(&hpsa_scan_mutex); - return; - } - } - if (h->busy_scanning) { /* state 3. */ - mutex_unlock(&hpsa_scan_mutex); - wait_for_completion(&h->scan_wait); - } else { /* state 1, nothing to do. */ - mutex_unlock(&hpsa_scan_mutex); - } -} - -/* hpsa_scan_func() - kernel thread used to rescan controllers - * @data: Ignored. - * - * A kernel thread used scan for drive topology changes on - * controllers. The thread processes only one controller at a time - * using a queue. Controllers are added to the queue using - * add_to_scan_list() and removed from the queue either after done - * processing or using remove_from_scan_list(). - * - * returns 0. - **/ -static int hpsa_scan_func(__attribute__((unused)) void *data) -{ - struct ctlr_info *h; - int host_no; - - while (1) { - set_current_state(TASK_INTERRUPTIBLE); - schedule(); - if (kthread_should_stop()) - break; - - while (1) { - mutex_lock(&hpsa_scan_mutex); - if (list_empty(&hpsa_scan_q)) { - mutex_unlock(&hpsa_scan_mutex); - break; - } - h = list_entry(hpsa_scan_q.next, struct ctlr_info, - scan_list); - list_del(&h->scan_list); - h->busy_scanning = 1; - mutex_unlock(&hpsa_scan_mutex); - host_no = h->scsi_host ? h->scsi_host->host_no : -1; - hpsa_scan_start(h->scsi_host); - complete_all(&h->scan_wait); - mutex_lock(&hpsa_scan_mutex); - h->busy_scanning = 0; - mutex_unlock(&hpsa_scan_mutex); - } - } - return 0; -} - static int check_for_unit_attention(struct ctlr_info *h, struct CommandList *c) { @@ -356,21 +229,8 @@ static int check_for_unit_attention(struct ctlr_info *h, break; case REPORT_LUNS_CHANGED: dev_warn(&h->pdev->dev, "hpsa%d: report LUN data " - "changed\n", h->ctlr); + "changed, action required\n", h->ctlr); /* - * Here, we could call add_to_scan_list and wake up the scan thread, - * except that it's quite likely that we will get more than one - * REPORT_LUNS_CHANGED condition in quick succession, which means - * that those which occur after the first one will likely happen - * *during* the hpsa_scan_thread's rescan. And the rescan code is not - * robust enough to restart in the middle, undoing what it has already - * done, and it's not clear that it's even possible to do this, since - * part of what it does is notify the SCSI mid layer, which starts - * doing it's own i/o to read partition tables and so on, and the - * driver doesn't have visibility to know what might need undoing. - * In any event, if possible, it is horribly complicated to get right - * so we just don't do it for now. - * * Note: this REPORT_LUNS_CHANGED condition only occurs on the MSA2012. */ break; @@ -397,10 +257,7 @@ static ssize_t host_store_rescan(struct device *dev, struct ctlr_info *h; struct Scsi_Host *shost = class_to_shost(dev); h = shost_to_hba(shost); - if (add_to_scan_list(h)) { - wake_up_process(hpsa_scan_thread); - wait_for_completion_interruptible(&h->scan_wait); - } + hpsa_scan_start(h->scsi_host); return count; } @@ -3553,8 +3410,6 @@ static int __devinit hpsa_init_one(struct pci_dev *pdev, h->busy_initializing = 1; INIT_HLIST_HEAD(&h->cmpQ); INIT_HLIST_HEAD(&h->reqQ); - mutex_init(&h->busy_shutting_down); - init_completion(&h->scan_wait); rc = hpsa_pci_init(h, pdev); if (rc != 0) goto clean1; @@ -3702,8 +3557,6 @@ static void __devexit hpsa_remove_one(struct pci_dev *pdev) return; } h = pci_get_drvdata(pdev); - mutex_lock(&h->busy_shutting_down); - remove_from_scan_list(h); hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */ hpsa_shutdown(pdev); iounmap(h->vaddr); @@ -3724,7 +3577,6 @@ static void __devexit hpsa_remove_one(struct pci_dev *pdev) */ pci_release_regions(pdev); pci_set_drvdata(pdev, NULL); - mutex_unlock(&h->busy_shutting_down); kfree(h); } @@ -3878,23 +3730,12 @@ clean_up: */ static int __init hpsa_init(void) { - int err; - /* Start the scan thread */ - hpsa_scan_thread = kthread_run(hpsa_scan_func, NULL, "hpsa_scan"); - if (IS_ERR(hpsa_scan_thread)) { - err = PTR_ERR(hpsa_scan_thread); - return -ENODEV; - } - err = pci_register_driver(&hpsa_pci_driver); - if (err) - kthread_stop(hpsa_scan_thread); - return err; + return pci_register_driver(&hpsa_pci_driver); } static void __exit hpsa_cleanup(void) { pci_unregister_driver(&hpsa_pci_driver); - kthread_stop(hpsa_scan_thread); } module_init(hpsa_init); diff --git a/drivers/scsi/hpsa.h b/drivers/scsi/hpsa.h index a0502b3ac17e..fc15215145d9 100644 --- a/drivers/scsi/hpsa.h +++ b/drivers/scsi/hpsa.h @@ -97,9 +97,6 @@ struct ctlr_info { int scan_finished; spinlock_t scan_lock; wait_queue_head_t scan_wait_queue; - struct mutex busy_shutting_down; - struct list_head scan_list; - struct completion scan_wait; struct Scsi_Host *scsi_host; spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ -- cgit v1.2.3 From ff9fea94546afa2a496c15354533f06088347f6e Mon Sep 17 00:00:00 2001 From: "Stephen M. Cameron" Date: Thu, 25 Feb 2010 14:03:17 -0600 Subject: [SCSI] hpsa: mark hpsa_pci_init as __devinit Signed-off-by: Stephen M. Cameron Signed-off-by: James Bottomley --- drivers/scsi/hpsa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c index 3d43bb245ac8..2e1edce9b20e 100644 --- a/drivers/scsi/hpsa.c +++ b/drivers/scsi/hpsa.c @@ -3174,7 +3174,7 @@ default_int_mode: h->intr[PERF_MODE_INT] = pdev->irq; } -static int hpsa_pci_init(struct ctlr_info *h, struct pci_dev *pdev) +static int __devinit hpsa_pci_init(struct ctlr_info *h, struct pci_dev *pdev) { ushort subsystem_vendor_id, subsystem_device_id, command; u32 board_id, scratchpad = 0; -- cgit v1.2.3 From db61bfcfe2a68dc71402c270686cd73b80971efc Mon Sep 17 00:00:00 2001 From: "Stephen M. Cameron" Date: Thu, 25 Feb 2010 14:03:22 -0600 Subject: [SCSI] hpsa: Clarify calculation of padding for commandlist structure Signed-off-by: Stephen M. Cameron Signed-off-by: James Bottomley --- drivers/scsi/hpsa_cmd.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/hpsa_cmd.h b/drivers/scsi/hpsa_cmd.h index 3e0abdf76689..43b6f1cffe34 100644 --- a/drivers/scsi/hpsa_cmd.h +++ b/drivers/scsi/hpsa_cmd.h @@ -313,12 +313,18 @@ struct CommandList { void *scsi_cmd; /* on 64 bit architectures, to get this to be 32-byte-aligned - * it so happens we need no padding, on 32 bit systems, - * we need 8 bytes of padding. This does that. + * it so happens we need PAD_64 bytes of padding, on 32 bit systems, + * we need PAD_32 bytes of padding (see below). This does that. + * If it happens that 64 bit and 32 bit systems need different + * padding, PAD_32 and PAD_64 can be set independently, and. + * the code below will do the right thing. */ -#define COMMANDLIST_PAD ((8 - sizeof(long))/4 * 8) +#define IS_32_BIT ((8 - sizeof(long))/4) +#define IS_64_BIT (!IS_32_BIT) +#define PAD_32 (8) +#define PAD_64 (0) +#define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64) u8 pad[COMMANDLIST_PAD]; - }; /* Configuration Table Structure */ -- cgit v1.2.3 From 33a2ffce51d9598380d73c515a27fc6cff3bd9c4 Mon Sep 17 00:00:00 2001 From: "Stephen M. Cameron" Date: Thu, 25 Feb 2010 14:03:27 -0600 Subject: [SCSI] hpsa: Increase the number of scatter gather elements supported. This uses the scatter-gather chaining feature of Smart Array controllers. 32 scatter-gather elements are embedded in the "command list", and the last element in the list may be marked as a "chain pointer", and point to an additional block of scatter gather elements. The precise number of scatter gather elements supported is dependent on the particular kind of Smart Array, and is determined at runtime by querying the hardware. Signed-off-by: Stephen M. Cameron Signed-off-by: James Bottomley --- drivers/scsi/hpsa.c | 134 ++++++++++++++++++++++++++++++++++++++++++++---- drivers/scsi/hpsa.h | 4 ++ drivers/scsi/hpsa_cmd.h | 7 +-- 3 files changed, 131 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c index 2e1edce9b20e..183d3a43c280 100644 --- a/drivers/scsi/hpsa.c +++ b/drivers/scsi/hpsa.c @@ -187,7 +187,6 @@ static struct scsi_host_template hpsa_driver_template = { .scan_finished = hpsa_scan_finished, .change_queue_depth = hpsa_change_queue_depth, .this_id = -1, - .sg_tablesize = MAXSGENTRIES, .use_clustering = ENABLE_CLUSTERING, .eh_device_reset_handler = hpsa_eh_device_reset_handler, .ioctl = hpsa_ioctl, @@ -844,6 +843,76 @@ static void hpsa_scsi_setup(struct ctlr_info *h) spin_lock_init(&h->devlock); } +static void hpsa_free_sg_chain_blocks(struct ctlr_info *h) +{ + int i; + + if (!h->cmd_sg_list) + return; + for (i = 0; i < h->nr_cmds; i++) { + kfree(h->cmd_sg_list[i]); + h->cmd_sg_list[i] = NULL; + } + kfree(h->cmd_sg_list); + h->cmd_sg_list = NULL; +} + +static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h) +{ + int i; + + if (h->chainsize <= 0) + return 0; + + h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds, + GFP_KERNEL); + if (!h->cmd_sg_list) + return -ENOMEM; + for (i = 0; i < h->nr_cmds; i++) { + h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) * + h->chainsize, GFP_KERNEL); + if (!h->cmd_sg_list[i]) + goto clean; + } + return 0; + +clean: + hpsa_free_sg_chain_blocks(h); + return -ENOMEM; +} + +static void hpsa_map_sg_chain_block(struct ctlr_info *h, + struct CommandList *c) +{ + struct SGDescriptor *chain_sg, *chain_block; + u64 temp64; + + chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; + chain_block = h->cmd_sg_list[c->cmdindex]; + chain_sg->Ext = HPSA_SG_CHAIN; + chain_sg->Len = sizeof(*chain_sg) * + (c->Header.SGTotal - h->max_cmd_sg_entries); + temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len, + PCI_DMA_TODEVICE); + chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL); + chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL); +} + +static void hpsa_unmap_sg_chain_block(struct ctlr_info *h, + struct CommandList *c) +{ + struct SGDescriptor *chain_sg; + union u64bit temp64; + + if (c->Header.SGTotal <= h->max_cmd_sg_entries) + return; + + chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; + temp64.val32.lower = chain_sg->Addr.lower; + temp64.val32.upper = chain_sg->Addr.upper; + pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE); +} + static void complete_scsi_command(struct CommandList *cp, int timeout, u32 tag) { @@ -860,6 +929,8 @@ static void complete_scsi_command(struct CommandList *cp, h = cp->h; scsi_dma_unmap(cmd); /* undo the DMA mappings */ + if (cp->Header.SGTotal > h->max_cmd_sg_entries) + hpsa_unmap_sg_chain_block(h, cp); cmd->result = (DID_OK << 16); /* host byte */ cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ @@ -1064,6 +1135,7 @@ static int hpsa_scsi_detect(struct ctlr_info *h) sh->max_id = HPSA_MAX_LUN; sh->can_queue = h->nr_cmds; sh->cmd_per_lun = h->nr_cmds; + sh->sg_tablesize = h->maxsgentries; h->scsi_host = sh; sh->hostdata[0] = (unsigned long) h; sh->irq = h->intr[PERF_MODE_INT]; @@ -1765,16 +1837,17 @@ out: * dma mapping and fills in the scatter gather entries of the * hpsa command, cp. */ -static int hpsa_scatter_gather(struct pci_dev *pdev, +static int hpsa_scatter_gather(struct ctlr_info *h, struct CommandList *cp, struct scsi_cmnd *cmd) { unsigned int len; struct scatterlist *sg; u64 addr64; - int use_sg, i; + int use_sg, i, sg_index, chained; + struct SGDescriptor *curr_sg; - BUG_ON(scsi_sg_count(cmd) > MAXSGENTRIES); + BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); use_sg = scsi_dma_map(cmd); if (use_sg < 0) @@ -1783,15 +1856,33 @@ static int hpsa_scatter_gather(struct pci_dev *pdev, if (!use_sg) goto sglist_finished; + curr_sg = cp->SG; + chained = 0; + sg_index = 0; scsi_for_each_sg(cmd, sg, use_sg, i) { + if (i == h->max_cmd_sg_entries - 1 && + use_sg > h->max_cmd_sg_entries) { + chained = 1; + curr_sg = h->cmd_sg_list[cp->cmdindex]; + sg_index = 0; + } addr64 = (u64) sg_dma_address(sg); len = sg_dma_len(sg); - cp->SG[i].Addr.lower = - (u32) (addr64 & (u64) 0x00000000FFFFFFFF); - cp->SG[i].Addr.upper = - (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF); - cp->SG[i].Len = len; - cp->SG[i].Ext = 0; /* we are not chaining */ + curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL); + curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL); + curr_sg->Len = len; + curr_sg->Ext = 0; /* we are not chaining */ + curr_sg++; + } + + if (use_sg + chained > h->maxSG) + h->maxSG = use_sg + chained; + + if (chained) { + cp->Header.SGList = h->max_cmd_sg_entries; + cp->Header.SGTotal = (u16) (use_sg + 1); + hpsa_map_sg_chain_block(h, cp); + return 0; } sglist_finished: @@ -1887,7 +1978,7 @@ static int hpsa_scsi_queue_command(struct scsi_cmnd *cmd, break; } - if (hpsa_scatter_gather(h->pdev, c, cmd) < 0) { /* Fill SG list */ + if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */ cmd_free(h, c); return SCSI_MLQUEUE_HOST_BUSY; } @@ -3283,6 +3374,23 @@ static int __devinit hpsa_pci_init(struct ctlr_info *h, struct pci_dev *pdev) h->board_id = board_id; h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands)); + h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements)); + + /* + * Limit in-command s/g elements to 32 save dma'able memory. + * Howvever spec says if 0, use 31 + */ + + h->max_cmd_sg_entries = 31; + if (h->maxsgentries > 512) { + h->max_cmd_sg_entries = 32; + h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1; + h->maxsgentries--; /* save one for chain pointer */ + } else { + h->maxsgentries = 31; /* default to traditional values */ + h->chainsize = 0; + } + h->product_name = products[prod_index].product_name; h->access = *(products[prod_index].access); /* Allow room for some ioctls */ @@ -3463,6 +3571,8 @@ static int __devinit hpsa_init_one(struct pci_dev *pdev, rc = -ENOMEM; goto clean4; } + if (hpsa_allocate_sg_chain_blocks(h)) + goto clean4; spin_lock_init(&h->lock); spin_lock_init(&h->scan_lock); init_waitqueue_head(&h->scan_wait_queue); @@ -3485,6 +3595,7 @@ static int __devinit hpsa_init_one(struct pci_dev *pdev, return 1; clean4: + hpsa_free_sg_chain_blocks(h); kfree(h->cmd_pool_bits); if (h->cmd_pool) pci_free_consistent(h->pdev, @@ -3560,6 +3671,7 @@ static void __devexit hpsa_remove_one(struct pci_dev *pdev) hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */ hpsa_shutdown(pdev); iounmap(h->vaddr); + hpsa_free_sg_chain_blocks(h); pci_free_consistent(h->pdev, h->nr_cmds * sizeof(struct CommandList), h->cmd_pool, h->cmd_pool_dhandle); diff --git a/drivers/scsi/hpsa.h b/drivers/scsi/hpsa.h index fc15215145d9..1bb5233b09a0 100644 --- a/drivers/scsi/hpsa.h +++ b/drivers/scsi/hpsa.h @@ -83,6 +83,10 @@ struct ctlr_info { unsigned int maxQsinceinit; unsigned int maxSG; spinlock_t lock; + int maxsgentries; + u8 max_cmd_sg_entries; + int chainsize; + struct SGDescriptor **cmd_sg_list; /* pointers to command and error info pool */ struct CommandList *cmd_pool; diff --git a/drivers/scsi/hpsa_cmd.h b/drivers/scsi/hpsa_cmd.h index 43b6f1cffe34..cb0c2385f3f6 100644 --- a/drivers/scsi/hpsa_cmd.h +++ b/drivers/scsi/hpsa_cmd.h @@ -23,7 +23,8 @@ /* general boundary defintions */ #define SENSEINFOBYTES 32 /* may vary between hbas */ -#define MAXSGENTRIES 31 +#define MAXSGENTRIES 32 +#define HPSA_SG_CHAIN 0x80000000 #define MAXREPLYQS 256 /* Command Status value */ @@ -321,8 +322,8 @@ struct CommandList { */ #define IS_32_BIT ((8 - sizeof(long))/4) #define IS_64_BIT (!IS_32_BIT) -#define PAD_32 (8) -#define PAD_64 (0) +#define PAD_32 (24) +#define PAD_64 (16) #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64) u8 pad[COMMANDLIST_PAD]; }; -- cgit v1.2.3 From 43aebfa12e7631124472237dc945c27af54ca646 Mon Sep 17 00:00:00 2001 From: "Stephen M. Cameron" Date: Thu, 25 Feb 2010 14:03:32 -0600 Subject: [SCSI] hpsa: remove unused members next, prev, and retry_count from command list structure. Signed-off-by: Stephen M. Cameron Signed-off-by: James Bottomley --- drivers/scsi/hpsa_cmd.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/hpsa_cmd.h b/drivers/scsi/hpsa_cmd.h index cb0c2385f3f6..56fb9827681e 100644 --- a/drivers/scsi/hpsa_cmd.h +++ b/drivers/scsi/hpsa_cmd.h @@ -306,11 +306,8 @@ struct CommandList { int cmd_type; long cmdindex; struct hlist_node list; - struct CommandList *prev; - struct CommandList *next; struct request *rq; struct completion *waiting; - int retry_count; void *scsi_cmd; /* on 64 bit architectures, to get this to be 32-byte-aligned @@ -322,8 +319,8 @@ struct CommandList { */ #define IS_32_BIT ((8 - sizeof(long))/4) #define IS_64_BIT (!IS_32_BIT) -#define PAD_32 (24) -#define PAD_64 (16) +#define PAD_32 (4) +#define PAD_64 (4) #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64) u8 pad[COMMANDLIST_PAD]; }; -- cgit v1.2.3 From 9f1177a3f8eee22427eb97e6e00b62ff0be2871f Mon Sep 17 00:00:00 2001 From: James Smart Date: Fri, 26 Feb 2010 14:12:57 -0500 Subject: [SCSI] lpfc 8.3.10: Fix Initialization issues - Add NULL checks to the pointers for the config_async mailbox and dump_wakeup_params mailbox. - Add code to check return value of lpfc_read_sparams everywhere and handle failures appropriately. Signed-off-by: James Smart Signed-off-by: James Bottomley --- drivers/scsi/lpfc/lpfc_hbadisc.c | 32 ++++++++++++++++++-------------- drivers/scsi/lpfc/lpfc_init.c | 19 +++++++++++++++++-- drivers/scsi/lpfc/lpfc_sli.c | 8 +++++++- drivers/scsi/lpfc/lpfc_vport.c | 7 ++++++- 4 files changed, 48 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/lpfc/lpfc_hbadisc.c b/drivers/scsi/lpfc/lpfc_hbadisc.c index 2359d0bfb734..e58d8aeec09e 100644 --- a/drivers/scsi/lpfc/lpfc_hbadisc.c +++ b/drivers/scsi/lpfc/lpfc_hbadisc.c @@ -2024,8 +2024,6 @@ lpfc_mbx_process_link_up(struct lpfc_hba *phba, READ_LA_VAR *la) int rc; struct fcf_record *fcf_record; - sparam_mbox = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL); - spin_lock_irq(&phba->hbalock); switch (la->UlnkSpeed) { case LA_1GHZ_LINK: @@ -2117,18 +2115,24 @@ lpfc_mbx_process_link_up(struct lpfc_hba *phba, READ_LA_VAR *la) spin_unlock_irq(&phba->hbalock); lpfc_linkup(phba); - if (sparam_mbox) { - lpfc_read_sparam(phba, sparam_mbox, 0); - sparam_mbox->vport = vport; - sparam_mbox->mbox_cmpl = lpfc_mbx_cmpl_read_sparam; - rc = lpfc_sli_issue_mbox(phba, sparam_mbox, MBX_NOWAIT); - if (rc == MBX_NOT_FINISHED) { - mp = (struct lpfc_dmabuf *) sparam_mbox->context1; - lpfc_mbuf_free(phba, mp->virt, mp->phys); - kfree(mp); - mempool_free(sparam_mbox, phba->mbox_mem_pool); - goto out; - } + sparam_mbox = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL); + if (!sparam_mbox) + goto out; + + rc = lpfc_read_sparam(phba, sparam_mbox, 0); + if (rc) { + mempool_free(sparam_mbox, phba->mbox_mem_pool); + goto out; + } + sparam_mbox->vport = vport; + sparam_mbox->mbox_cmpl = lpfc_mbx_cmpl_read_sparam; + rc = lpfc_sli_issue_mbox(phba, sparam_mbox, MBX_NOWAIT); + if (rc == MBX_NOT_FINISHED) { + mp = (struct lpfc_dmabuf *) sparam_mbox->context1; + lpfc_mbuf_free(phba, mp->virt, mp->phys); + kfree(mp); + mempool_free(sparam_mbox, phba->mbox_mem_pool); + goto out; } if (!(phba->hba_flag & HBA_FCOE_SUPPORT)) { diff --git a/drivers/scsi/lpfc/lpfc_init.c b/drivers/scsi/lpfc/lpfc_init.c index d29ac7c317d9..b64cecafa7ab 100644 --- a/drivers/scsi/lpfc/lpfc_init.c +++ b/drivers/scsi/lpfc/lpfc_init.c @@ -350,7 +350,12 @@ lpfc_config_port_post(struct lpfc_hba *phba) mb = &pmb->u.mb; /* Get login parameters for NID. */ - lpfc_read_sparam(phba, pmb, 0); + rc = lpfc_read_sparam(phba, pmb, 0); + if (rc) { + mempool_free(pmb, phba->mbox_mem_pool); + return -ENOMEM; + } + pmb->vport = vport; if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) { lpfc_printf_log(phba, KERN_ERR, LOG_INIT, @@ -359,7 +364,7 @@ lpfc_config_port_post(struct lpfc_hba *phba) mb->mbxCommand, mb->mbxStatus); phba->link_state = LPFC_HBA_ERROR; mp = (struct lpfc_dmabuf *) pmb->context1; - mempool_free( pmb, phba->mbox_mem_pool); + mempool_free(pmb, phba->mbox_mem_pool); lpfc_mbuf_free(phba, mp->virt, mp->phys); kfree(mp); return -EIO; @@ -571,6 +576,11 @@ lpfc_config_port_post(struct lpfc_hba *phba) } /* MBOX buffer will be freed in mbox compl */ pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL); + if (!pmb) { + phba->link_state = LPFC_HBA_ERROR; + return -ENOMEM; + } + lpfc_config_async(phba, pmb, LPFC_ELS_RING); pmb->mbox_cmpl = lpfc_config_async_cmpl; pmb->vport = phba->pport; @@ -588,6 +598,11 @@ lpfc_config_port_post(struct lpfc_hba *phba) /* Get Option rom version */ pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL); + if (!pmb) { + phba->link_state = LPFC_HBA_ERROR; + return -ENOMEM; + } + lpfc_dump_wakeup_param(phba, pmb); pmb->mbox_cmpl = lpfc_dump_wakeup_param_cmpl; pmb->vport = phba->pport; diff --git a/drivers/scsi/lpfc/lpfc_sli.c b/drivers/scsi/lpfc/lpfc_sli.c index 35e3b96d4e07..d51ee7e3273b 100644 --- a/drivers/scsi/lpfc/lpfc_sli.c +++ b/drivers/scsi/lpfc/lpfc_sli.c @@ -4388,7 +4388,13 @@ lpfc_sli4_hba_setup(struct lpfc_hba *phba) spin_unlock_irq(&phba->hbalock); /* Read the port's service parameters. */ - lpfc_read_sparam(phba, mboxq, vport->vpi); + rc = lpfc_read_sparam(phba, mboxq, vport->vpi); + if (rc) { + phba->link_state = LPFC_HBA_ERROR; + rc = -ENOMEM; + goto out_free_vpd; + } + mboxq->vport = vport; rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL); mp = (struct lpfc_dmabuf *) mboxq->context1; diff --git a/drivers/scsi/lpfc/lpfc_vport.c b/drivers/scsi/lpfc/lpfc_vport.c index dc86e873102a..869f76cbc58a 100644 --- a/drivers/scsi/lpfc/lpfc_vport.c +++ b/drivers/scsi/lpfc/lpfc_vport.c @@ -123,7 +123,12 @@ lpfc_vport_sparm(struct lpfc_hba *phba, struct lpfc_vport *vport) } mb = &pmb->u.mb; - lpfc_read_sparam(phba, pmb, vport->vpi); + rc = lpfc_read_sparam(phba, pmb, vport->vpi); + if (rc) { + mempool_free(pmb, phba->mbox_mem_pool); + return -ENOMEM; + } + /* * Grab buffer pointer and clear context1 so we can use * lpfc_sli_issue_box_wait -- cgit v1.2.3 From e40a02c12581f710877da372b5d7e15b68a1c5c3 Mon Sep 17 00:00:00 2001 From: James Smart Date: Fri, 26 Feb 2010 14:13:54 -0500 Subject: [SCSI] lpfc 8.3.10: Fix user interface issues - Add Logging message for critial errors. - Remove unused variable from lpfc_nodev_tmo_show - Update supress_link_up parameter with #define values. Signed-off-by: James Smart Signed-off-by: James Bottomley --- drivers/scsi/lpfc/lpfc.h | 3 +++ drivers/scsi/lpfc/lpfc_attr.c | 7 ++++--- drivers/scsi/lpfc/lpfc_els.c | 21 ++++++++++++++++++--- drivers/scsi/lpfc/lpfc_init.c | 4 ++-- drivers/scsi/lpfc/lpfc_scsi.c | 14 ++++++++++++-- drivers/scsi/lpfc/lpfc_sli.c | 11 ++++++++++- 6 files changed, 49 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/lpfc/lpfc.h b/drivers/scsi/lpfc/lpfc.h index 84b696463a58..ce0599dcc814 100644 --- a/drivers/scsi/lpfc/lpfc.h +++ b/drivers/scsi/lpfc/lpfc.h @@ -623,6 +623,9 @@ struct lpfc_hba { uint32_t cfg_log_verbose; uint32_t cfg_aer_support; uint32_t cfg_suppress_link_up; +#define LPFC_INITIALIZE_LINK 0 /* do normal init_link mbox */ +#define LPFC_DELAY_INIT_LINK 1 /* layered driver hold off */ +#define LPFC_DELAY_INIT_LINK_INDEFINITELY 2 /* wait, manual intervention */ lpfc_vpd_t vpd; /* vital product data */ diff --git a/drivers/scsi/lpfc/lpfc_attr.c b/drivers/scsi/lpfc/lpfc_attr.c index c992e8328f9e..64cd17eedb64 100644 --- a/drivers/scsi/lpfc/lpfc_attr.c +++ b/drivers/scsi/lpfc/lpfc_attr.c @@ -1939,7 +1939,9 @@ static DEVICE_ATTR(lpfc_enable_npiv, S_IRUGO, # 0x2 = never bring up link # Default value is 0. */ -LPFC_ATTR_R(suppress_link_up, 0, 0, 2, "Suppress Link Up at initialization"); +LPFC_ATTR_R(suppress_link_up, LPFC_INITIALIZE_LINK, LPFC_INITIALIZE_LINK, + LPFC_DELAY_INIT_LINK_INDEFINITELY, + "Suppress Link Up at initialization"); /* # lpfc_nodev_tmo: If set, it will hold all I/O errors on devices that disappear @@ -1966,8 +1968,7 @@ lpfc_nodev_tmo_show(struct device *dev, struct device_attribute *attr, { struct Scsi_Host *shost = class_to_shost(dev); struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata; - int val = 0; - val = vport->cfg_devloss_tmo; + return snprintf(buf, PAGE_SIZE, "%d\n", vport->cfg_devloss_tmo); } diff --git a/drivers/scsi/lpfc/lpfc_els.c b/drivers/scsi/lpfc/lpfc_els.c index 08b6634cb994..4623323da577 100644 --- a/drivers/scsi/lpfc/lpfc_els.c +++ b/drivers/scsi/lpfc/lpfc_els.c @@ -806,9 +806,8 @@ lpfc_cmpl_els_flogi(struct lpfc_hba *phba, struct lpfc_iocbq *cmdiocb, } /* FLOGI failure */ - lpfc_printf_vlog(vport, KERN_INFO, LOG_ELS, - "0100 FLOGI failure Data: x%x x%x " - "x%x\n", + lpfc_printf_vlog(vport, KERN_ERR, LOG_ELS, + "0100 FLOGI failure Status:x%x/x%x TMO:x%x\n", irsp->ulpStatus, irsp->un.ulpWord[4], irsp->ulpTimeout); goto flogifail; @@ -1409,6 +1408,10 @@ lpfc_cmpl_els_plogi(struct lpfc_hba *phba, struct lpfc_iocbq *cmdiocb, goto out; } /* PLOGI failed */ + lpfc_printf_vlog(vport, KERN_ERR, LOG_ELS, + "2753 PLOGI failure DID:%06X Status:x%x/x%x\n", + ndlp->nlp_DID, irsp->ulpStatus, + irsp->un.ulpWord[4]); /* Do not call DSM for lpfc_els_abort'ed ELS cmds */ if (lpfc_error_lost_link(irsp)) rc = NLP_STE_FREED_NODE; @@ -1577,6 +1580,10 @@ lpfc_cmpl_els_prli(struct lpfc_hba *phba, struct lpfc_iocbq *cmdiocb, goto out; } /* PRLI failed */ + lpfc_printf_vlog(vport, KERN_ERR, LOG_ELS, + "2754 PRLI failure DID:%06X Status:x%x/x%x\n", + ndlp->nlp_DID, irsp->ulpStatus, + irsp->un.ulpWord[4]); /* Do not call DSM for lpfc_els_abort'ed ELS cmds */ if (lpfc_error_lost_link(irsp)) goto out; @@ -1860,6 +1867,10 @@ lpfc_cmpl_els_adisc(struct lpfc_hba *phba, struct lpfc_iocbq *cmdiocb, goto out; } /* ADISC failed */ + lpfc_printf_vlog(vport, KERN_ERR, LOG_ELS, + "2755 ADISC failure DID:%06X Status:x%x/x%x\n", + ndlp->nlp_DID, irsp->ulpStatus, + irsp->un.ulpWord[4]); /* Do not call DSM for lpfc_els_abort'ed ELS cmds */ if (!lpfc_error_lost_link(irsp)) lpfc_disc_state_machine(vport, ndlp, cmdiocb, @@ -2009,6 +2020,10 @@ lpfc_cmpl_els_logo(struct lpfc_hba *phba, struct lpfc_iocbq *cmdiocb, /* ELS command is being retried */ goto out; /* LOGO failed */ + lpfc_printf_vlog(vport, KERN_ERR, LOG_ELS, + "2756 LOGO failure DID:%06X Status:x%x/x%x\n", + ndlp->nlp_DID, irsp->ulpStatus, + irsp->un.ulpWord[4]); /* Do not call DSM for lpfc_els_abort'ed ELS cmds */ if (lpfc_error_lost_link(irsp)) goto out; diff --git a/drivers/scsi/lpfc/lpfc_init.c b/drivers/scsi/lpfc/lpfc_init.c index b64cecafa7ab..437ddc92ebea 100644 --- a/drivers/scsi/lpfc/lpfc_init.c +++ b/drivers/scsi/lpfc/lpfc_init.c @@ -549,7 +549,7 @@ lpfc_config_port_post(struct lpfc_hba *phba) mempool_free(pmb, phba->mbox_mem_pool); return -EIO; } - } else if (phba->cfg_suppress_link_up == 0) { + } else if (phba->cfg_suppress_link_up == LPFC_INITIALIZE_LINK) { lpfc_init_link(phba, pmb, phba->cfg_topology, phba->cfg_link_speed); pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl; @@ -667,7 +667,7 @@ lpfc_hba_init_link(struct lpfc_hba *phba) mempool_free(pmb, phba->mbox_mem_pool); return -EIO; } - phba->cfg_suppress_link_up = 0; + phba->cfg_suppress_link_up = LPFC_INITIALIZE_LINK; return 0; } diff --git a/drivers/scsi/lpfc/lpfc_scsi.c b/drivers/scsi/lpfc/lpfc_scsi.c index 7f21b47db791..889a7b9ec92b 100644 --- a/drivers/scsi/lpfc/lpfc_scsi.c +++ b/drivers/scsi/lpfc/lpfc_scsi.c @@ -2079,8 +2079,7 @@ lpfc_handle_fcp_err(struct lpfc_vport *vport, struct lpfc_scsi_buf *lpfc_cmd, if (resp_info & RSP_LEN_VALID) { rsplen = be32_to_cpu(fcprsp->rspRspLen); - if ((rsplen != 0 && rsplen != 4 && rsplen != 8) || - (fcprsp->rspInfo3 != RSP_NO_FAILURE)) { + if (rsplen != 0 && rsplen != 4 && rsplen != 8) { lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP, "2719 Invalid response length: " "tgt x%x lun x%x cmnd x%x rsplen x%x\n", @@ -2090,6 +2089,17 @@ lpfc_handle_fcp_err(struct lpfc_vport *vport, struct lpfc_scsi_buf *lpfc_cmd, host_status = DID_ERROR; goto out; } + if (fcprsp->rspInfo3 != RSP_NO_FAILURE) { + lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP, + "2757 Protocol failure detected during " + "processing of FCP I/O op: " + "tgt x%x lun x%x cmnd x%x rspInfo3 x%x\n", + cmnd->device->id, + cmnd->device->lun, cmnd->cmnd[0], + fcprsp->rspInfo3); + host_status = DID_ERROR; + goto out; + } } if ((resp_info & SNS_LEN_VALID) && fcprsp->rspSnsLen) { diff --git a/drivers/scsi/lpfc/lpfc_sli.c b/drivers/scsi/lpfc/lpfc_sli.c index d51ee7e3273b..49bed3e8c95d 100644 --- a/drivers/scsi/lpfc/lpfc_sli.c +++ b/drivers/scsi/lpfc/lpfc_sli.c @@ -3091,6 +3091,12 @@ lpfc_sli_brdready_s3(struct lpfc_hba *phba, uint32_t mask) /* Check to see if any errors occurred during init */ if ((status & HS_FFERM) || (i >= 20)) { + lpfc_printf_log(phba, KERN_ERR, LOG_INIT, + "2751 Adapter failed to restart, " + "status reg x%x, FW Data: A8 x%x AC x%x\n", + status, + readl(phba->MBslimaddr + 0xa8), + readl(phba->MBslimaddr + 0xac)); phba->link_state = LPFC_HBA_ERROR; retval = 1; } @@ -3278,6 +3284,9 @@ lpfc_sli_brdkill(struct lpfc_hba *phba) if (retval != MBX_SUCCESS) { if (retval != MBX_BUSY) mempool_free(pmb, phba->mbox_mem_pool); + lpfc_printf_log(phba, KERN_ERR, LOG_SLI, + "2752 KILL_BOARD command failed retval %d\n", + retval); spin_lock_irq(&phba->hbalock); phba->link_flag &= ~LS_IGNORE_ERATT; spin_unlock_irq(&phba->hbalock); @@ -4035,7 +4044,7 @@ lpfc_sli_hba_setup(struct lpfc_hba *phba) lpfc_sli_hba_setup_error: phba->link_state = LPFC_HBA_ERROR; - lpfc_printf_log(phba, KERN_INFO, LOG_INIT, + lpfc_printf_log(phba, KERN_ERR, LOG_INIT, "0445 Firmware initialization failed\n"); return rc; } -- cgit v1.2.3 From 0f65ff680f90281d49ee864965f06774eba9657d Mon Sep 17 00:00:00 2001 From: James Smart Date: Fri, 26 Feb 2010 14:14:23 -0500 Subject: [SCSI] lpfc 8.3.10: Update SLI interface areas - Clear LPFC_DRIVER_ABORTED on FCP command completion. - Clear exchange busy flag when I/O is aborted and found on aborted list. - Free sglq when XRI_ABORTED event is processed before release of IOCB. - Only process iocb as aborted when LPFC_DRIVER_ABORTED is set. Signed-off-by: James Smart Signed-off-by: James Bottomley --- drivers/scsi/lpfc/lpfc.h | 1 - drivers/scsi/lpfc/lpfc_crtn.h | 2 +- drivers/scsi/lpfc/lpfc_els.c | 23 +++++--- drivers/scsi/lpfc/lpfc_init.c | 7 +++ drivers/scsi/lpfc/lpfc_scsi.c | 35 +++++++++--- drivers/scsi/lpfc/lpfc_sli.c | 128 +++++++++++++++++++++++++++--------------- drivers/scsi/lpfc/lpfc_sli.h | 1 + drivers/scsi/lpfc/lpfc_sli4.h | 7 +++ 8 files changed, 141 insertions(+), 63 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/lpfc/lpfc.h b/drivers/scsi/lpfc/lpfc.h index ce0599dcc814..4d45e6939783 100644 --- a/drivers/scsi/lpfc/lpfc.h +++ b/drivers/scsi/lpfc/lpfc.h @@ -509,7 +509,6 @@ struct lpfc_hba { int (*lpfc_hba_down_link) (struct lpfc_hba *); - /* SLI4 specific HBA data structure */ struct lpfc_sli4_hba sli4_hba; diff --git a/drivers/scsi/lpfc/lpfc_crtn.h b/drivers/scsi/lpfc/lpfc_crtn.h index 6f0fb51eb461..e7f548281b94 100644 --- a/drivers/scsi/lpfc/lpfc_crtn.h +++ b/drivers/scsi/lpfc/lpfc_crtn.h @@ -385,7 +385,7 @@ void lpfc_parse_fcoe_conf(struct lpfc_hba *, uint8_t *, uint32_t); int lpfc_parse_vpd(struct lpfc_hba *, uint8_t *, int); void lpfc_start_fdiscs(struct lpfc_hba *phba); struct lpfc_vport *lpfc_find_vport_by_vpid(struct lpfc_hba *, uint16_t); - +struct lpfc_sglq *__lpfc_get_active_sglq(struct lpfc_hba *, uint16_t); #define ScsiResult(host_code, scsi_code) (((host_code) << 16) | scsi_code) #define HBA_EVENT_RSCN 5 #define HBA_EVENT_LINK_UP 2 diff --git a/drivers/scsi/lpfc/lpfc_els.c b/drivers/scsi/lpfc/lpfc_els.c index 4623323da577..6a2135a0d03a 100644 --- a/drivers/scsi/lpfc/lpfc_els.c +++ b/drivers/scsi/lpfc/lpfc_els.c @@ -6234,7 +6234,8 @@ lpfc_cmpl_els_fdisc(struct lpfc_hba *phba, struct lpfc_iocbq *cmdiocb, lpfc_mbx_unreg_vpi(vport); spin_lock_irq(shost->host_lock); vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI; - vport->fc_flag |= FC_VPORT_NEEDS_INIT_VPI; + if (phba->sli_rev == LPFC_SLI_REV4) + vport->fc_flag |= FC_VPORT_NEEDS_INIT_VPI; spin_unlock_irq(shost->host_lock); } @@ -6812,21 +6813,27 @@ lpfc_sli4_els_xri_aborted(struct lpfc_hba *phba, struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL; unsigned long iflag = 0; - spin_lock_irqsave(&phba->sli4_hba.abts_sgl_list_lock, iflag); + spin_lock_irqsave(&phba->hbalock, iflag); + spin_lock(&phba->sli4_hba.abts_sgl_list_lock); list_for_each_entry_safe(sglq_entry, sglq_next, &phba->sli4_hba.lpfc_abts_els_sgl_list, list) { if (sglq_entry->sli4_xritag == xri) { list_del(&sglq_entry->list); - spin_unlock_irqrestore( - &phba->sli4_hba.abts_sgl_list_lock, - iflag); - spin_lock_irqsave(&phba->hbalock, iflag); - list_add_tail(&sglq_entry->list, &phba->sli4_hba.lpfc_sgl_list); + sglq_entry->state = SGL_FREED; + spin_unlock(&phba->sli4_hba.abts_sgl_list_lock); spin_unlock_irqrestore(&phba->hbalock, iflag); return; } } - spin_unlock_irqrestore(&phba->sli4_hba.abts_sgl_list_lock, iflag); + spin_unlock(&phba->sli4_hba.abts_sgl_list_lock); + sglq_entry = __lpfc_get_active_sglq(phba, xri); + if (!sglq_entry || (sglq_entry->sli4_xritag != xri)) { + spin_unlock_irqrestore(&phba->hbalock, iflag); + return; + } + sglq_entry->state = SGL_XRI_ABORTED; + spin_unlock_irqrestore(&phba->hbalock, iflag); + return; } diff --git a/drivers/scsi/lpfc/lpfc_init.c b/drivers/scsi/lpfc/lpfc_init.c index 437ddc92ebea..b7889c53fe23 100644 --- a/drivers/scsi/lpfc/lpfc_init.c +++ b/drivers/scsi/lpfc/lpfc_init.c @@ -822,6 +822,8 @@ lpfc_hba_down_post_s4(struct lpfc_hba *phba) LIST_HEAD(aborts); int ret; unsigned long iflag = 0; + struct lpfc_sglq *sglq_entry = NULL; + ret = lpfc_hba_down_post_s3(phba); if (ret) return ret; @@ -837,6 +839,10 @@ lpfc_hba_down_post_s4(struct lpfc_hba *phba) * list. */ spin_lock(&phba->sli4_hba.abts_sgl_list_lock); + list_for_each_entry(sglq_entry, + &phba->sli4_hba.lpfc_abts_els_sgl_list, list) + sglq_entry->state = SGL_FREED; + list_splice_init(&phba->sli4_hba.lpfc_abts_els_sgl_list, &phba->sli4_hba.lpfc_sgl_list); spin_unlock(&phba->sli4_hba.abts_sgl_list_lock); @@ -4412,6 +4418,7 @@ lpfc_init_sgl_list(struct lpfc_hba *phba) /* The list order is used by later block SGL registraton */ spin_lock_irq(&phba->hbalock); + sglq_entry->state = SGL_FREED; list_add_tail(&sglq_entry->list, &phba->sli4_hba.lpfc_sgl_list); phba->sli4_hba.lpfc_els_sgl_array[i] = sglq_entry; phba->sli4_hba.total_sglq_bufs++; diff --git a/drivers/scsi/lpfc/lpfc_scsi.c b/drivers/scsi/lpfc/lpfc_scsi.c index 889a7b9ec92b..a4881f26ab1b 100644 --- a/drivers/scsi/lpfc/lpfc_scsi.c +++ b/drivers/scsi/lpfc/lpfc_scsi.c @@ -620,23 +620,40 @@ lpfc_sli4_fcp_xri_aborted(struct lpfc_hba *phba, uint16_t xri = bf_get(lpfc_wcqe_xa_xri, axri); struct lpfc_scsi_buf *psb, *next_psb; unsigned long iflag = 0; + struct lpfc_iocbq *iocbq; + int i; - spin_lock_irqsave(&phba->sli4_hba.abts_scsi_buf_list_lock, iflag); + spin_lock_irqsave(&phba->hbalock, iflag); + spin_lock(&phba->sli4_hba.abts_scsi_buf_list_lock); list_for_each_entry_safe(psb, next_psb, &phba->sli4_hba.lpfc_abts_scsi_buf_list, list) { if (psb->cur_iocbq.sli4_xritag == xri) { list_del(&psb->list); psb->exch_busy = 0; psb->status = IOSTAT_SUCCESS; - spin_unlock_irqrestore( - &phba->sli4_hba.abts_scsi_buf_list_lock, - iflag); + spin_unlock( + &phba->sli4_hba.abts_scsi_buf_list_lock); + spin_unlock_irqrestore(&phba->hbalock, iflag); lpfc_release_scsi_buf_s4(phba, psb); return; } } - spin_unlock_irqrestore(&phba->sli4_hba.abts_scsi_buf_list_lock, - iflag); + spin_unlock(&phba->sli4_hba.abts_scsi_buf_list_lock); + for (i = 1; i <= phba->sli.last_iotag; i++) { + iocbq = phba->sli.iocbq_lookup[i]; + + if (!(iocbq->iocb_flag & LPFC_IO_FCP) || + (iocbq->iocb_flag & LPFC_IO_LIBDFC)) + continue; + if (iocbq->sli4_xritag != xri) + continue; + psb = container_of(iocbq, struct lpfc_scsi_buf, cur_iocbq); + psb->exch_busy = 0; + spin_unlock_irqrestore(&phba->hbalock, iflag); + return; + + } + spin_unlock_irqrestore(&phba->hbalock, iflag); } /** @@ -1006,6 +1023,7 @@ lpfc_scsi_prep_dma_buf_s3(struct lpfc_hba *phba, struct lpfc_scsi_buf *lpfc_cmd) struct scatterlist *sgel = NULL; struct fcp_cmnd *fcp_cmnd = lpfc_cmd->fcp_cmnd; struct ulp_bde64 *bpl = lpfc_cmd->fcp_bpl; + struct lpfc_iocbq *iocbq = &lpfc_cmd->cur_iocbq; IOCB_t *iocb_cmd = &lpfc_cmd->cur_iocbq.iocb; struct ulp_bde64 *data_bde = iocb_cmd->unsli3.fcp_ext.dbde; dma_addr_t physaddr; @@ -1056,6 +1074,7 @@ lpfc_scsi_prep_dma_buf_s3(struct lpfc_hba *phba, struct lpfc_scsi_buf *lpfc_cmd) physaddr = sg_dma_address(sgel); if (phba->sli_rev == 3 && !(phba->sli3_options & LPFC_SLI3_BG_ENABLED) && + !(iocbq->iocb_flag & DSS_SECURITY_OP) && nseg <= LPFC_EXT_DATA_BDE_COUNT) { data_bde->tus.f.bdeFlags = BUFF_TYPE_BDE_64; data_bde->tus.f.bdeSize = sg_dma_len(sgel); @@ -1082,7 +1101,8 @@ lpfc_scsi_prep_dma_buf_s3(struct lpfc_hba *phba, struct lpfc_scsi_buf *lpfc_cmd) * explicitly reinitialized since all iocb memory resources are reused. */ if (phba->sli_rev == 3 && - !(phba->sli3_options & LPFC_SLI3_BG_ENABLED)) { + !(phba->sli3_options & LPFC_SLI3_BG_ENABLED) && + !(iocbq->iocb_flag & DSS_SECURITY_OP)) { if (num_bde > LPFC_EXT_DATA_BDE_COUNT) { /* * The extended IOCB format can only fit 3 BDE or a BPL. @@ -1107,6 +1127,7 @@ lpfc_scsi_prep_dma_buf_s3(struct lpfc_hba *phba, struct lpfc_scsi_buf *lpfc_cmd) } else { iocb_cmd->un.fcpi64.bdl.bdeSize = ((num_bde + 2) * sizeof(struct ulp_bde64)); + iocb_cmd->unsli3.fcp_ext.ebde_count = (num_bde + 1); } fcp_cmnd->fcpDl = cpu_to_be32(scsi_bufflen(scsi_cmnd)); diff --git a/drivers/scsi/lpfc/lpfc_sli.c b/drivers/scsi/lpfc/lpfc_sli.c index 49bed3e8c95d..9feeaff47a52 100644 --- a/drivers/scsi/lpfc/lpfc_sli.c +++ b/drivers/scsi/lpfc/lpfc_sli.c @@ -494,7 +494,7 @@ __lpfc_clear_active_sglq(struct lpfc_hba *phba, uint16_t xritag) * * Returns sglq ponter = success, NULL = Failure. **/ -static struct lpfc_sglq * +struct lpfc_sglq * __lpfc_get_active_sglq(struct lpfc_hba *phba, uint16_t xritag) { uint16_t adj_xri; @@ -526,6 +526,7 @@ __lpfc_sli_get_sglq(struct lpfc_hba *phba) return NULL; adj_xri = sglq->sli4_xritag - phba->sli4_hba.max_cfg_param.xri_base; phba->sli4_hba.lpfc_sglq_active_list[adj_xri] = sglq; + sglq->state = SGL_ALLOCATED; return sglq; } @@ -580,15 +581,18 @@ __lpfc_sli_release_iocbq_s4(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq) else sglq = __lpfc_clear_active_sglq(phba, iocbq->sli4_xritag); if (sglq) { - if (iocbq->iocb_flag & LPFC_EXCHANGE_BUSY) { + if ((iocbq->iocb_flag & LPFC_EXCHANGE_BUSY) && + (sglq->state != SGL_XRI_ABORTED)) { spin_lock_irqsave(&phba->sli4_hba.abts_sgl_list_lock, iflag); list_add(&sglq->list, &phba->sli4_hba.lpfc_abts_els_sgl_list); spin_unlock_irqrestore( &phba->sli4_hba.abts_sgl_list_lock, iflag); - } else + } else { + sglq->state = SGL_FREED; list_add(&sglq->list, &phba->sli4_hba.lpfc_sgl_list); + } } @@ -2258,41 +2262,56 @@ lpfc_sli_process_sol_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring, spin_unlock_irqrestore(&phba->hbalock, iflag); } - if ((phba->sli_rev == LPFC_SLI_REV4) && - (saveq->iocb_flag & LPFC_EXCHANGE_BUSY)) { - /* Set cmdiocb flag for the exchange - * busy so sgl (xri) will not be - * released until the abort xri is - * received from hba, clear the - * LPFC_DRIVER_ABORTED bit in case - * it was driver initiated abort. - */ - spin_lock_irqsave(&phba->hbalock, - iflag); - cmdiocbp->iocb_flag &= - ~LPFC_DRIVER_ABORTED; - cmdiocbp->iocb_flag |= - LPFC_EXCHANGE_BUSY; - spin_unlock_irqrestore(&phba->hbalock, - iflag); - cmdiocbp->iocb.ulpStatus = - IOSTAT_LOCAL_REJECT; - cmdiocbp->iocb.un.ulpWord[4] = - IOERR_ABORT_REQUESTED; - /* - * For SLI4, irsiocb contains NO_XRI - * in sli_xritag, it shall not affect - * releasing sgl (xri) process. - */ - saveq->iocb.ulpStatus = - IOSTAT_LOCAL_REJECT; - saveq->iocb.un.ulpWord[4] = - IOERR_SLI_ABORTED; - spin_lock_irqsave(&phba->hbalock, - iflag); - saveq->iocb_flag |= LPFC_DELAY_MEM_FREE; - spin_unlock_irqrestore(&phba->hbalock, - iflag); + if (phba->sli_rev == LPFC_SLI_REV4) { + if (saveq->iocb_flag & + LPFC_EXCHANGE_BUSY) { + /* Set cmdiocb flag for the + * exchange busy so sgl (xri) + * will not be released until + * the abort xri is received + * from hba. + */ + spin_lock_irqsave( + &phba->hbalock, iflag); + cmdiocbp->iocb_flag |= + LPFC_EXCHANGE_BUSY; + spin_unlock_irqrestore( + &phba->hbalock, iflag); + } + if (cmdiocbp->iocb_flag & + LPFC_DRIVER_ABORTED) { + /* + * Clear LPFC_DRIVER_ABORTED + * bit in case it was driver + * initiated abort. + */ + spin_lock_irqsave( + &phba->hbalock, iflag); + cmdiocbp->iocb_flag &= + ~LPFC_DRIVER_ABORTED; + spin_unlock_irqrestore( + &phba->hbalock, iflag); + cmdiocbp->iocb.ulpStatus = + IOSTAT_LOCAL_REJECT; + cmdiocbp->iocb.un.ulpWord[4] = + IOERR_ABORT_REQUESTED; + /* + * For SLI4, irsiocb contains + * NO_XRI in sli_xritag, it + * shall not affect releasing + * sgl (xri) process. + */ + saveq->iocb.ulpStatus = + IOSTAT_LOCAL_REJECT; + saveq->iocb.un.ulpWord[4] = + IOERR_SLI_ABORTED; + spin_lock_irqsave( + &phba->hbalock, iflag); + saveq->iocb_flag |= + LPFC_DELAY_MEM_FREE; + spin_unlock_irqrestore( + &phba->hbalock, iflag); + } } } (cmdiocbp->iocb_cmpl) (phba, cmdiocbp, saveq); @@ -2515,14 +2534,16 @@ lpfc_sli_handle_fast_ring_event(struct lpfc_hba *phba, cmdiocbq = lpfc_sli_iocbq_lookup(phba, pring, &rspiocbq); - if ((cmdiocbq) && (cmdiocbq->iocb_cmpl)) { - spin_unlock_irqrestore(&phba->hbalock, - iflag); - (cmdiocbq->iocb_cmpl)(phba, cmdiocbq, - &rspiocbq); - spin_lock_irqsave(&phba->hbalock, - iflag); - } + if (unlikely(!cmdiocbq)) + break; + if (cmdiocbq->iocb_flag & LPFC_DRIVER_ABORTED) + cmdiocbq->iocb_flag &= ~LPFC_DRIVER_ABORTED; + if (cmdiocbq->iocb_cmpl) { + spin_unlock_irqrestore(&phba->hbalock, iflag); + (cmdiocbq->iocb_cmpl)(phba, cmdiocbq, + &rspiocbq); + spin_lock_irqsave(&phba->hbalock, iflag); + } break; case LPFC_UNSOL_IOCB: spin_unlock_irqrestore(&phba->hbalock, iflag); @@ -7451,6 +7472,7 @@ lpfc_sli_wake_iocb_wait(struct lpfc_hba *phba, { wait_queue_head_t *pdone_q; unsigned long iflags; + struct lpfc_scsi_buf *lpfc_cmd; spin_lock_irqsave(&phba->hbalock, iflags); cmdiocbq->iocb_flag |= LPFC_IO_WAKE; @@ -7458,6 +7480,14 @@ lpfc_sli_wake_iocb_wait(struct lpfc_hba *phba, memcpy(&((struct lpfc_iocbq *)cmdiocbq->context2)->iocb, &rspiocbq->iocb, sizeof(IOCB_t)); + /* Set the exchange busy flag for task management commands */ + if ((cmdiocbq->iocb_flag & LPFC_IO_FCP) && + !(cmdiocbq->iocb_flag & LPFC_IO_LIBDFC)) { + lpfc_cmd = container_of(cmdiocbq, struct lpfc_scsi_buf, + cur_iocbq); + lpfc_cmd->exch_busy = rspiocbq->iocb_flag & LPFC_EXCHANGE_BUSY; + } + pdone_q = cmdiocbq->context_un.wait_queue; if (pdone_q) wake_up(pdone_q); @@ -9076,6 +9106,12 @@ lpfc_sli4_fp_handle_fcp_wcqe(struct lpfc_hba *phba, /* Fake the irspiocb and copy necessary response information */ lpfc_sli4_iocb_param_transfer(phba, &irspiocbq, cmdiocbq, wcqe); + if (cmdiocbq->iocb_flag & LPFC_DRIVER_ABORTED) { + spin_lock_irqsave(&phba->hbalock, iflags); + cmdiocbq->iocb_flag &= ~LPFC_DRIVER_ABORTED; + spin_unlock_irqrestore(&phba->hbalock, iflags); + } + /* Pass the cmd_iocb and the rsp state to the upper layer */ (cmdiocbq->iocb_cmpl)(phba, cmdiocbq, &irspiocbq); } diff --git a/drivers/scsi/lpfc/lpfc_sli.h b/drivers/scsi/lpfc/lpfc_sli.h index dfcf5437d1f5..b4a639c47616 100644 --- a/drivers/scsi/lpfc/lpfc_sli.h +++ b/drivers/scsi/lpfc/lpfc_sli.h @@ -62,6 +62,7 @@ struct lpfc_iocbq { #define LPFC_DELAY_MEM_FREE 0x20 /* Defer free'ing of FC data */ #define LPFC_EXCHANGE_BUSY 0x40 /* SLI4 hba reported XB in response */ #define LPFC_USE_FCPWQIDX 0x80 /* Submit to specified FCPWQ index */ +#define DSS_SECURITY_OP 0x100 /* security IO */ #define LPFC_FIP_ELS_ID_MASK 0xc000 /* ELS_ID range 0-3, non-shifted mask */ #define LPFC_FIP_ELS_ID_SHIFT 14 diff --git a/drivers/scsi/lpfc/lpfc_sli4.h b/drivers/scsi/lpfc/lpfc_sli4.h index 86308836600f..04fd7829cf39 100644 --- a/drivers/scsi/lpfc/lpfc_sli4.h +++ b/drivers/scsi/lpfc/lpfc_sli4.h @@ -431,11 +431,18 @@ enum lpfc_sge_type { SCSI_BUFF_TYPE }; +enum lpfc_sgl_state { + SGL_FREED, + SGL_ALLOCATED, + SGL_XRI_ABORTED +}; + struct lpfc_sglq { /* lpfc_sglqs are used in double linked lists */ struct list_head list; struct list_head clist; enum lpfc_sge_type buff_type; /* is this a scsi sgl */ + enum lpfc_sgl_state state; uint16_t iotag; /* pre-assigned IO tag */ uint16_t sli4_xritag; /* pre-assigned XRI, (OXID) tag. */ struct sli4_sge *sgl; /* pre-assigned SGL */ -- cgit v1.2.3 From e2aed29f29d0d289df3b0b627b122832d4dc80fe Mon Sep 17 00:00:00 2001 From: James Smart Date: Fri, 26 Feb 2010 14:15:00 -0500 Subject: [SCSI] lpfc 8.3.10: Added management for LP21000 through BSG. Signed-off-by: James Smart Signed-off-by: James Bottomley --- drivers/scsi/lpfc/lpfc.h | 6 + drivers/scsi/lpfc/lpfc_bsg.c | 332 ++++++++++++++++++++++++++++++++++++++++++ drivers/scsi/lpfc/lpfc_bsg.h | 12 ++ drivers/scsi/lpfc/lpfc_init.c | 8 + 4 files changed, 358 insertions(+) (limited to 'drivers') diff --git a/drivers/scsi/lpfc/lpfc.h b/drivers/scsi/lpfc/lpfc.h index 4d45e6939783..565e16dd74fc 100644 --- a/drivers/scsi/lpfc/lpfc.h +++ b/drivers/scsi/lpfc/lpfc.h @@ -37,6 +37,9 @@ struct lpfc_sli2_slim; the NameServer before giving up. */ #define LPFC_CMD_PER_LUN 3 /* max outstanding cmds per lun */ #define LPFC_DEFAULT_SG_SEG_CNT 64 /* sg element count per scsi cmnd */ +#define LPFC_DEFAULT_MENLO_SG_SEG_CNT 128 /* sg element count per scsi + cmnd for menlo needs nearly twice as for firmware + downloads using bsg */ #define LPFC_DEFAULT_PROT_SG_SEG_CNT 4096 /* sg protection elements count */ #define LPFC_MAX_SG_SEG_CNT 4096 /* sg element count per scsi cmnd */ #define LPFC_MAX_PROT_SG_SEG_CNT 4096 /* prot sg element count per scsi cmd*/ @@ -806,6 +809,9 @@ struct lpfc_hba { struct list_head ct_ev_waiters; struct unsol_rcv_ct_ctx ct_ctx[64]; uint32_t ctx_idx; + + uint8_t menlo_flag; /* menlo generic flags */ +#define HBA_MENLO_SUPPORT 0x1 /* HBA supports menlo commands */ }; static inline struct Scsi_Host * diff --git a/drivers/scsi/lpfc/lpfc_bsg.c b/drivers/scsi/lpfc/lpfc_bsg.c index f3f1bf1a0a71..692c29f6048e 100644 --- a/drivers/scsi/lpfc/lpfc_bsg.c +++ b/drivers/scsi/lpfc/lpfc_bsg.c @@ -83,15 +83,28 @@ struct lpfc_bsg_mbox { struct fc_bsg_job *set_job; }; +#define MENLO_DID 0x0000FC0E + +struct lpfc_bsg_menlo { + struct lpfc_iocbq *cmdiocbq; + struct lpfc_iocbq *rspiocbq; + struct lpfc_dmabuf *bmp; + + /* job waiting for this iocb to finish */ + struct fc_bsg_job *set_job; +}; + #define TYPE_EVT 1 #define TYPE_IOCB 2 #define TYPE_MBOX 3 +#define TYPE_MENLO 4 struct bsg_job_data { uint32_t type; union { struct lpfc_bsg_event *evt; struct lpfc_bsg_iocb iocb; struct lpfc_bsg_mbox mbox; + struct lpfc_bsg_menlo menlo; } context_un; }; @@ -2456,6 +2469,18 @@ static int lpfc_bsg_check_cmd_access(struct lpfc_hba *phba, case MBX_PORT_IOV_CONTROL: break; case MBX_SET_VARIABLE: + lpfc_printf_log(phba, KERN_INFO, LOG_INIT, + "1226 mbox: set_variable 0x%x, 0x%x\n", + mb->un.varWords[0], + mb->un.varWords[1]); + if ((mb->un.varWords[0] == SETVAR_MLOMNT) + && (mb->un.varWords[1] == 1)) { + phba->wait_4_mlo_maint_flg = 1; + } else if (mb->un.varWords[0] == SETVAR_MLORST) { + phba->link_flag &= ~LS_LOOPBACK_MODE; + phba->fc_topology = TOPOLOGY_PT_PT; + } + break; case MBX_RUN_BIU_DIAG64: case MBX_READ_EVENT_LOG: case MBX_READ_SPARM64: @@ -2637,6 +2662,297 @@ job_error: return rc; } +/** + * lpfc_bsg_menlo_cmd_cmp - lpfc_menlo_cmd completion handler + * @phba: Pointer to HBA context object. + * @cmdiocbq: Pointer to command iocb. + * @rspiocbq: Pointer to response iocb. + * + * This function is the completion handler for iocbs issued using + * lpfc_menlo_cmd function. This function is called by the + * ring event handler function without any lock held. This function + * can be called from both worker thread context and interrupt + * context. This function also can be called from another thread which + * cleans up the SLI layer objects. + * This function copies the contents of the response iocb to the + * response iocb memory object provided by the caller of + * lpfc_sli_issue_iocb_wait and then wakes up the thread which + * sleeps for the iocb completion. + **/ +static void +lpfc_bsg_menlo_cmd_cmp(struct lpfc_hba *phba, + struct lpfc_iocbq *cmdiocbq, + struct lpfc_iocbq *rspiocbq) +{ + struct bsg_job_data *dd_data; + struct fc_bsg_job *job; + IOCB_t *rsp; + struct lpfc_dmabuf *bmp; + struct lpfc_bsg_menlo *menlo; + unsigned long flags; + struct menlo_response *menlo_resp; + int rc = 0; + + spin_lock_irqsave(&phba->ct_ev_lock, flags); + dd_data = cmdiocbq->context1; + if (!dd_data) { + spin_unlock_irqrestore(&phba->ct_ev_lock, flags); + return; + } + + menlo = &dd_data->context_un.menlo; + job = menlo->set_job; + job->dd_data = NULL; /* so timeout handler does not reply */ + + spin_lock_irqsave(&phba->hbalock, flags); + cmdiocbq->iocb_flag |= LPFC_IO_WAKE; + if (cmdiocbq->context2 && rspiocbq) + memcpy(&((struct lpfc_iocbq *)cmdiocbq->context2)->iocb, + &rspiocbq->iocb, sizeof(IOCB_t)); + spin_unlock_irqrestore(&phba->hbalock, flags); + + bmp = menlo->bmp; + rspiocbq = menlo->rspiocbq; + rsp = &rspiocbq->iocb; + + pci_unmap_sg(phba->pcidev, job->request_payload.sg_list, + job->request_payload.sg_cnt, DMA_TO_DEVICE); + pci_unmap_sg(phba->pcidev, job->reply_payload.sg_list, + job->reply_payload.sg_cnt, DMA_FROM_DEVICE); + + /* always return the xri, this would be used in the case + * of a menlo download to allow the data to be sent as a continuation + * of the exchange. + */ + menlo_resp = (struct menlo_response *) + job->reply->reply_data.vendor_reply.vendor_rsp; + menlo_resp->xri = rsp->ulpContext; + if (rsp->ulpStatus) { + if (rsp->ulpStatus == IOSTAT_LOCAL_REJECT) { + switch (rsp->un.ulpWord[4] & 0xff) { + case IOERR_SEQUENCE_TIMEOUT: + rc = -ETIMEDOUT; + break; + case IOERR_INVALID_RPI: + rc = -EFAULT; + break; + default: + rc = -EACCES; + break; + } + } else + rc = -EACCES; + } else + job->reply->reply_payload_rcv_len = + rsp->un.genreq64.bdl.bdeSize; + + lpfc_mbuf_free(phba, bmp->virt, bmp->phys); + lpfc_sli_release_iocbq(phba, rspiocbq); + lpfc_sli_release_iocbq(phba, cmdiocbq); + kfree(bmp); + kfree(dd_data); + /* make error code available to userspace */ + job->reply->result = rc; + /* complete the job back to userspace */ + job->job_done(job); + spin_unlock_irqrestore(&phba->ct_ev_lock, flags); + return; +} + +/** + * lpfc_menlo_cmd - send an ioctl for menlo hardware + * @job: fc_bsg_job to handle + * + * This function issues a gen request 64 CR ioctl for all menlo cmd requests, + * all the command completions will return the xri for the command. + * For menlo data requests a gen request 64 CX is used to continue the exchange + * supplied in the menlo request header xri field. + **/ +static int +lpfc_menlo_cmd(struct fc_bsg_job *job) +{ + struct lpfc_vport *vport = (struct lpfc_vport *)job->shost->hostdata; + struct lpfc_hba *phba = vport->phba; + struct lpfc_iocbq *cmdiocbq, *rspiocbq; + IOCB_t *cmd, *rsp; + int rc = 0; + struct menlo_command *menlo_cmd; + struct menlo_response *menlo_resp; + struct lpfc_dmabuf *bmp = NULL; + int request_nseg; + int reply_nseg; + struct scatterlist *sgel = NULL; + int numbde; + dma_addr_t busaddr; + struct bsg_job_data *dd_data; + struct ulp_bde64 *bpl = NULL; + + /* in case no data is returned return just the return code */ + job->reply->reply_payload_rcv_len = 0; + + if (job->request_len < + sizeof(struct fc_bsg_request) + + sizeof(struct menlo_command)) { + lpfc_printf_log(phba, KERN_WARNING, LOG_LIBDFC, + "2784 Received MENLO_CMD request below " + "minimum size\n"); + rc = -ERANGE; + goto no_dd_data; + } + + if (job->reply_len < + sizeof(struct fc_bsg_request) + sizeof(struct menlo_response)) { + lpfc_printf_log(phba, KERN_WARNING, LOG_LIBDFC, + "2785 Received MENLO_CMD reply below " + "minimum size\n"); + rc = -ERANGE; + goto no_dd_data; + } + + if (!(phba->menlo_flag & HBA_MENLO_SUPPORT)) { + lpfc_printf_log(phba, KERN_WARNING, LOG_LIBDFC, + "2786 Adapter does not support menlo " + "commands\n"); + rc = -EPERM; + goto no_dd_data; + } + + menlo_cmd = (struct menlo_command *) + job->request->rqst_data.h_vendor.vendor_cmd; + + menlo_resp = (struct menlo_response *) + job->reply->reply_data.vendor_reply.vendor_rsp; + + /* allocate our bsg tracking structure */ + dd_data = kmalloc(sizeof(struct bsg_job_data), GFP_KERNEL); + if (!dd_data) { + lpfc_printf_log(phba, KERN_WARNING, LOG_LIBDFC, + "2787 Failed allocation of dd_data\n"); + rc = -ENOMEM; + goto no_dd_data; + } + + bmp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL); + if (!bmp) { + rc = -ENOMEM; + goto free_dd; + } + + cmdiocbq = lpfc_sli_get_iocbq(phba); + if (!cmdiocbq) { + rc = -ENOMEM; + goto free_bmp; + } + + rspiocbq = lpfc_sli_get_iocbq(phba); + if (!rspiocbq) { + rc = -ENOMEM; + goto free_cmdiocbq; + } + + rsp = &rspiocbq->iocb; + + bmp->virt = lpfc_mbuf_alloc(phba, 0, &bmp->phys); + if (!bmp->virt) { + rc = -ENOMEM; + goto free_rspiocbq; + } + + INIT_LIST_HEAD(&bmp->list); + bpl = (struct ulp_bde64 *) bmp->virt; + request_nseg = pci_map_sg(phba->pcidev, job->request_payload.sg_list, + job->request_payload.sg_cnt, DMA_TO_DEVICE); + for_each_sg(job->request_payload.sg_list, sgel, request_nseg, numbde) { + busaddr = sg_dma_address(sgel); + bpl->tus.f.bdeFlags = BUFF_TYPE_BDE_64; + bpl->tus.f.bdeSize = sg_dma_len(sgel); + bpl->tus.w = cpu_to_le32(bpl->tus.w); + bpl->addrLow = cpu_to_le32(putPaddrLow(busaddr)); + bpl->addrHigh = cpu_to_le32(putPaddrHigh(busaddr)); + bpl++; + } + + reply_nseg = pci_map_sg(phba->pcidev, job->reply_payload.sg_list, + job->reply_payload.sg_cnt, DMA_FROM_DEVICE); + for_each_sg(job->reply_payload.sg_list, sgel, reply_nseg, numbde) { + busaddr = sg_dma_address(sgel); + bpl->tus.f.bdeFlags = BUFF_TYPE_BDE_64I; + bpl->tus.f.bdeSize = sg_dma_len(sgel); + bpl->tus.w = cpu_to_le32(bpl->tus.w); + bpl->addrLow = cpu_to_le32(putPaddrLow(busaddr)); + bpl->addrHigh = cpu_to_le32(putPaddrHigh(busaddr)); + bpl++; + } + + cmd = &cmdiocbq->iocb; + cmd->un.genreq64.bdl.ulpIoTag32 = 0; + cmd->un.genreq64.bdl.addrHigh = putPaddrHigh(bmp->phys); + cmd->un.genreq64.bdl.addrLow = putPaddrLow(bmp->phys); + cmd->un.genreq64.bdl.bdeFlags = BUFF_TYPE_BLP_64; + cmd->un.genreq64.bdl.bdeSize = + (request_nseg + reply_nseg) * sizeof(struct ulp_bde64); + cmd->un.genreq64.w5.hcsw.Fctl = (SI | LA); + cmd->un.genreq64.w5.hcsw.Dfctl = 0; + cmd->un.genreq64.w5.hcsw.Rctl = FC_RCTL_DD_UNSOL_CMD; + cmd->un.genreq64.w5.hcsw.Type = MENLO_TRANSPORT_TYPE; /* 0xfe */ + cmd->ulpBdeCount = 1; + cmd->ulpClass = CLASS3; + cmd->ulpOwner = OWN_CHIP; + cmd->ulpLe = 1; /* Limited Edition */ + cmdiocbq->iocb_flag |= LPFC_IO_LIBDFC; + cmdiocbq->vport = phba->pport; + /* We want the firmware to timeout before we do */ + cmd->ulpTimeout = MENLO_TIMEOUT - 5; + cmdiocbq->context3 = bmp; + cmdiocbq->context2 = rspiocbq; + cmdiocbq->iocb_cmpl = lpfc_bsg_menlo_cmd_cmp; + cmdiocbq->context1 = dd_data; + cmdiocbq->context2 = rspiocbq; + if (menlo_cmd->cmd == LPFC_BSG_VENDOR_MENLO_CMD) { + cmd->ulpCommand = CMD_GEN_REQUEST64_CR; + cmd->ulpPU = MENLO_PU; /* 3 */ + cmd->un.ulpWord[4] = MENLO_DID; /* 0x0000FC0E */ + cmd->ulpContext = MENLO_CONTEXT; /* 0 */ + } else { + cmd->ulpCommand = CMD_GEN_REQUEST64_CX; + cmd->ulpPU = 1; + cmd->un.ulpWord[4] = 0; + cmd->ulpContext = menlo_cmd->xri; + } + + dd_data->type = TYPE_MENLO; + dd_data->context_un.menlo.cmdiocbq = cmdiocbq; + dd_data->context_un.menlo.rspiocbq = rspiocbq; + dd_data->context_un.menlo.set_job = job; + dd_data->context_un.menlo.bmp = bmp; + + rc = lpfc_sli_issue_iocb(phba, LPFC_ELS_RING, cmdiocbq, + MENLO_TIMEOUT - 5); + if (rc == IOCB_SUCCESS) + return 0; /* done for now */ + + /* iocb failed so cleanup */ + pci_unmap_sg(phba->pcidev, job->request_payload.sg_list, + job->request_payload.sg_cnt, DMA_TO_DEVICE); + pci_unmap_sg(phba->pcidev, job->reply_payload.sg_list, + job->reply_payload.sg_cnt, DMA_FROM_DEVICE); + + lpfc_mbuf_free(phba, bmp->virt, bmp->phys); + +free_rspiocbq: + lpfc_sli_release_iocbq(phba, rspiocbq); +free_cmdiocbq: + lpfc_sli_release_iocbq(phba, cmdiocbq); +free_bmp: + kfree(bmp); +free_dd: + kfree(dd_data); +no_dd_data: + /* make error code available to userspace */ + job->reply->result = rc; + job->dd_data = NULL; + return rc; +} /** * lpfc_bsg_hst_vendor - process a vendor-specific fc_bsg_job * @job: fc_bsg_job to handle @@ -2669,6 +2985,10 @@ lpfc_bsg_hst_vendor(struct fc_bsg_job *job) case LPFC_BSG_VENDOR_MBOX: rc = lpfc_bsg_mbox_cmd(job); break; + case LPFC_BSG_VENDOR_MENLO_CMD: + case LPFC_BSG_VENDOR_MENLO_DATA: + rc = lpfc_menlo_cmd(job); + break; default: rc = -EINVAL; job->reply->reply_payload_rcv_len = 0; @@ -2728,6 +3048,7 @@ lpfc_bsg_timeout(struct fc_bsg_job *job) struct lpfc_bsg_event *evt; struct lpfc_bsg_iocb *iocb; struct lpfc_bsg_mbox *mbox; + struct lpfc_bsg_menlo *menlo; struct lpfc_sli_ring *pring = &phba->sli.ring[LPFC_ELS_RING]; struct bsg_job_data *dd_data; unsigned long flags; @@ -2775,6 +3096,17 @@ lpfc_bsg_timeout(struct fc_bsg_job *job) spin_unlock_irqrestore(&phba->ct_ev_lock, flags); job->job_done(job); break; + case TYPE_MENLO: + menlo = &dd_data->context_un.menlo; + cmdiocb = menlo->cmdiocbq; + /* hint to completion handler that the job timed out */ + job->reply->result = -EAGAIN; + spin_unlock_irqrestore(&phba->ct_ev_lock, flags); + /* this will call our completion handler */ + spin_lock_irq(&phba->hbalock); + lpfc_sli_issue_abort_iotag(phba, pring, cmdiocb); + spin_unlock_irq(&phba->hbalock); + break; default: spin_unlock_irqrestore(&phba->ct_ev_lock, flags); break; diff --git a/drivers/scsi/lpfc/lpfc_bsg.h b/drivers/scsi/lpfc/lpfc_bsg.h index 6c8f87e39b98..5bc630819b9e 100644 --- a/drivers/scsi/lpfc/lpfc_bsg.h +++ b/drivers/scsi/lpfc/lpfc_bsg.h @@ -31,6 +31,8 @@ #define LPFC_BSG_VENDOR_DIAG_TEST 5 #define LPFC_BSG_VENDOR_GET_MGMT_REV 6 #define LPFC_BSG_VENDOR_MBOX 7 +#define LPFC_BSG_VENDOR_MENLO_CMD 8 +#define LPFC_BSG_VENDOR_MENLO_DATA 9 struct set_ct_event { uint32_t command; @@ -96,3 +98,13 @@ struct dfc_mbox_req { uint8_t mbOffset; }; +/* Used for menlo command or menlo data. The xri is only used for menlo data */ +struct menlo_command { + uint32_t cmd; + uint32_t xri; +}; + +struct menlo_response { + uint32_t xri; /* return the xri of the iocb exchange */ +}; + diff --git a/drivers/scsi/lpfc/lpfc_init.c b/drivers/scsi/lpfc/lpfc_init.c index b7889c53fe23..88e02a453e0e 100644 --- a/drivers/scsi/lpfc/lpfc_init.c +++ b/drivers/scsi/lpfc/lpfc_init.c @@ -2597,6 +2597,14 @@ lpfc_create_port(struct lpfc_hba *phba, int instance, struct device *dev) init_timer(&vport->els_tmofunc); vport->els_tmofunc.function = lpfc_els_timeout; vport->els_tmofunc.data = (unsigned long)vport; + if (phba->pcidev->device == PCI_DEVICE_ID_HORNET) { + phba->menlo_flag |= HBA_MENLO_SUPPORT; + /* check for menlo minimum sg count */ + if (phba->cfg_sg_seg_cnt < LPFC_DEFAULT_MENLO_SG_SEG_CNT) { + phba->cfg_sg_seg_cnt = LPFC_DEFAULT_MENLO_SG_SEG_CNT; + shost->sg_tablesize = phba->cfg_sg_seg_cnt; + } + } error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev); if (error) -- cgit v1.2.3 From fc2b989be9190f3311a5ae41289828e24897a20e Mon Sep 17 00:00:00 2001 From: James Smart Date: Fri, 26 Feb 2010 14:15:29 -0500 Subject: [SCSI] lpfc 8.3.10: Fix Discovery issues - Prevent Vport discovery after reg_new_vport completes when physical logged in using FDISC. - Remove fast FCF failover fabric name matching. Allow failover to FCFs connected to different fabrics. - Added fast FCF failover in response to FCF DEAD event on current FCF record. Signed-off-by: James Smart Signed-off-by: James Bottomley --- drivers/scsi/lpfc/lpfc_crtn.h | 1 + drivers/scsi/lpfc/lpfc_els.c | 7 +- drivers/scsi/lpfc/lpfc_hbadisc.c | 27 ++++---- drivers/scsi/lpfc/lpfc_init.c | 140 +++++++++++++++++++++++++++++++-------- drivers/scsi/lpfc/lpfc_sli.c | 54 +++++++++++++-- drivers/scsi/lpfc/lpfc_sli4.h | 8 ++- 6 files changed, 186 insertions(+), 51 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/lpfc/lpfc_crtn.h b/drivers/scsi/lpfc/lpfc_crtn.h index e7f548281b94..39739a707ed4 100644 --- a/drivers/scsi/lpfc/lpfc_crtn.h +++ b/drivers/scsi/lpfc/lpfc_crtn.h @@ -221,6 +221,7 @@ void lpfc_unregister_fcf_rescan(struct lpfc_hba *); void lpfc_unregister_unused_fcf(struct lpfc_hba *); int lpfc_sli4_redisc_fcf_table(struct lpfc_hba *); void lpfc_fcf_redisc_wait_start_timer(struct lpfc_hba *); +void lpfc_sli4_fcf_dead_failthrough(struct lpfc_hba *); int lpfc_mem_alloc(struct lpfc_hba *, int align); void lpfc_mem_free(struct lpfc_hba *); diff --git a/drivers/scsi/lpfc/lpfc_els.c b/drivers/scsi/lpfc/lpfc_els.c index 6a2135a0d03a..a81d43306d17 100644 --- a/drivers/scsi/lpfc/lpfc_els.c +++ b/drivers/scsi/lpfc/lpfc_els.c @@ -6004,7 +6004,12 @@ lpfc_cmpl_reg_new_vport(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmb) if (phba->sli_rev < LPFC_SLI_REV4) lpfc_issue_fabric_reglogin(vport); else { - lpfc_start_fdiscs(phba); + /* + * If the physical port is instantiated using + * FDISC, do not start vport discovery. + */ + if (vport->port_state != LPFC_FDISC) + lpfc_start_fdiscs(phba); lpfc_do_scr_ns_plogi(phba, vport); } } else diff --git a/drivers/scsi/lpfc/lpfc_hbadisc.c b/drivers/scsi/lpfc/lpfc_hbadisc.c index e58d8aeec09e..f28ce40dc349 100644 --- a/drivers/scsi/lpfc/lpfc_hbadisc.c +++ b/drivers/scsi/lpfc/lpfc_hbadisc.c @@ -1504,7 +1504,9 @@ lpfc_check_pending_fcoe_event(struct lpfc_hba *phba, uint8_t unreg_fcf) */ spin_lock_irq(&phba->hbalock); phba->hba_flag &= ~FCF_DISC_INPROGRESS; - phba->fcf.fcf_flag &= ~FCF_REDISC_FOV; + phba->fcf.fcf_flag &= ~(FCF_REDISC_FOV | + FCF_DEAD_FOVER | + FCF_CVL_FOVER); spin_unlock_irq(&phba->hbalock); } @@ -1649,7 +1651,9 @@ lpfc_mbx_cmpl_read_fcf_record(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) __lpfc_sli4_stop_fcf_redisc_wait_timer(phba); else if (phba->fcf.fcf_flag & FCF_REDISC_FOV) /* If in fast failover, mark it's completed */ - phba->fcf.fcf_flag &= ~FCF_REDISC_FOV; + phba->fcf.fcf_flag &= ~(FCF_REDISC_FOV | + FCF_DEAD_FOVER | + FCF_CVL_FOVER); spin_unlock_irqrestore(&phba->hbalock, iflags); goto out; } @@ -1669,14 +1673,9 @@ lpfc_mbx_cmpl_read_fcf_record(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) * Update on failover FCF record only if it's in FCF fast-failover * period; otherwise, update on current FCF record. */ - if (phba->fcf.fcf_flag & FCF_REDISC_FOV) { - /* Fast FCF failover only to the same fabric name */ - if (lpfc_fab_name_match(phba->fcf.current_rec.fabric_name, - new_fcf_record)) - fcf_rec = &phba->fcf.failover_rec; - else - goto read_next_fcf; - } else + if (phba->fcf.fcf_flag & FCF_REDISC_FOV) + fcf_rec = &phba->fcf.failover_rec; + else fcf_rec = &phba->fcf.current_rec; if (phba->fcf.fcf_flag & FCF_AVAILABLE) { @@ -1705,8 +1704,7 @@ lpfc_mbx_cmpl_read_fcf_record(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) * If the new hba FCF record has lower priority value * than the driver FCF record, use the new record. */ - if (lpfc_fab_name_match(fcf_rec->fabric_name, new_fcf_record) && - (new_fcf_record->fip_priority < fcf_rec->priority)) { + if (new_fcf_record->fip_priority < fcf_rec->priority) { /* Choose this FCF record */ __lpfc_update_fcf_record(phba, fcf_rec, new_fcf_record, addr_mode, vlan_id, 0); @@ -1762,7 +1760,9 @@ read_next_fcf: sizeof(struct lpfc_fcf_rec)); /* mark the FCF fast failover completed */ spin_lock_irqsave(&phba->hbalock, iflags); - phba->fcf.fcf_flag &= ~FCF_REDISC_FOV; + phba->fcf.fcf_flag &= ~(FCF_REDISC_FOV | + FCF_DEAD_FOVER | + FCF_CVL_FOVER); spin_unlock_irqrestore(&phba->hbalock, iflags); /* Register to the new FCF record */ lpfc_register_fcf(phba); @@ -4760,6 +4760,7 @@ lpfc_unregister_fcf_rescan(struct lpfc_hba *phba) return; /* Reset HBA FCF states after successful unregister FCF */ phba->fcf.fcf_flag = 0; + phba->fcf.current_rec.flag = 0; /* * If driver is not unloading, check if there is any other diff --git a/drivers/scsi/lpfc/lpfc_init.c b/drivers/scsi/lpfc/lpfc_init.c index 88e02a453e0e..ff45e336917a 100644 --- a/drivers/scsi/lpfc/lpfc_init.c +++ b/drivers/scsi/lpfc/lpfc_init.c @@ -2199,8 +2199,10 @@ lpfc_stop_vport_timers(struct lpfc_vport *vport) void __lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba) { - /* Clear pending FCF rediscovery wait timer */ - phba->fcf.fcf_flag &= ~FCF_REDISC_PEND; + /* Clear pending FCF rediscovery wait and failover in progress flags */ + phba->fcf.fcf_flag &= ~(FCF_REDISC_PEND | + FCF_DEAD_FOVER | + FCF_CVL_FOVER); /* Now, try to stop the timer */ del_timer(&phba->fcf.redisc_wait); } @@ -3211,6 +3213,68 @@ out_free_pmb: mempool_free(pmb, phba->mbox_mem_pool); } +/** + * lpfc_sli4_perform_vport_cvl - Perform clear virtual link on a vport + * @vport: pointer to vport data structure. + * + * This routine is to perform Clear Virtual Link (CVL) on a vport in + * response to a CVL event. + * + * Return the pointer to the ndlp with the vport if successful, otherwise + * return NULL. + **/ +static struct lpfc_nodelist * +lpfc_sli4_perform_vport_cvl(struct lpfc_vport *vport) +{ + struct lpfc_nodelist *ndlp; + struct Scsi_Host *shost; + struct lpfc_hba *phba; + + if (!vport) + return NULL; + ndlp = lpfc_findnode_did(vport, Fabric_DID); + if (!ndlp) + return NULL; + phba = vport->phba; + if (!phba) + return NULL; + if (phba->pport->port_state <= LPFC_FLOGI) + return NULL; + /* If virtual link is not yet instantiated ignore CVL */ + if (vport->port_state <= LPFC_FDISC) + return NULL; + shost = lpfc_shost_from_vport(vport); + if (!shost) + return NULL; + lpfc_linkdown_port(vport); + lpfc_cleanup_pending_mbox(vport); + spin_lock_irq(shost->host_lock); + vport->fc_flag |= FC_VPORT_CVL_RCVD; + spin_unlock_irq(shost->host_lock); + + return ndlp; +} + +/** + * lpfc_sli4_perform_all_vport_cvl - Perform clear virtual link on all vports + * @vport: pointer to lpfc hba data structure. + * + * This routine is to perform Clear Virtual Link (CVL) on all vports in + * response to a FCF dead event. + **/ +static void +lpfc_sli4_perform_all_vport_cvl(struct lpfc_hba *phba) +{ + struct lpfc_vport **vports; + int i; + + vports = lpfc_create_vport_work_array(phba); + if (vports) + for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) + lpfc_sli4_perform_vport_cvl(vports[i]); + lpfc_destroy_vport_work_array(phba, vports); +} + /** * lpfc_sli4_async_fcoe_evt - Process the asynchronous fcoe event * @phba: pointer to lpfc hba data structure. @@ -3227,7 +3291,6 @@ lpfc_sli4_async_fcoe_evt(struct lpfc_hba *phba, struct lpfc_vport *vport; struct lpfc_nodelist *ndlp; struct Scsi_Host *shost; - uint32_t link_state; int active_vlink_present; struct lpfc_vport **vports; int i; @@ -3284,16 +3347,35 @@ lpfc_sli4_async_fcoe_evt(struct lpfc_hba *phba, /* If the event is not for currently used fcf do nothing */ if (phba->fcf.current_rec.fcf_indx != acqe_fcoe->index) break; - /* - * Currently, driver support only one FCF - so treat this as - * a link down, but save the link state because we don't want - * it to be changed to Link Down unless it is already down. + /* We request port to rediscover the entire FCF table for + * a fast recovery from case that the current FCF record + * is no longer valid if the last CVL event hasn't already + * triggered process. */ - link_state = phba->link_state; - lpfc_linkdown(phba); - phba->link_state = link_state; - /* Unregister FCF if no devices connected to it */ - lpfc_unregister_unused_fcf(phba); + spin_lock_irq(&phba->hbalock); + if (phba->fcf.fcf_flag & FCF_CVL_FOVER) { + spin_unlock_irq(&phba->hbalock); + break; + } + /* Mark the fast failover process in progress */ + phba->fcf.fcf_flag |= FCF_DEAD_FOVER; + spin_unlock_irq(&phba->hbalock); + rc = lpfc_sli4_redisc_fcf_table(phba); + if (rc) { + spin_lock_irq(&phba->hbalock); + phba->fcf.fcf_flag &= ~FCF_DEAD_FOVER; + spin_unlock_irq(&phba->hbalock); + /* + * Last resort will fail over by treating this + * as a link down to FCF registration. + */ + lpfc_sli4_fcf_dead_failthrough(phba); + } else + /* Handling fast FCF failover to a DEAD FCF event + * is considered equalivant to receiving CVL to all + * vports. + */ + lpfc_sli4_perform_all_vport_cvl(phba); break; case LPFC_FCOE_EVENT_TYPE_CVL: lpfc_printf_log(phba, KERN_ERR, LOG_DISCOVERY, @@ -3301,23 +3383,9 @@ lpfc_sli4_async_fcoe_evt(struct lpfc_hba *phba, " tag 0x%x\n", acqe_fcoe->index, acqe_fcoe->event_tag); vport = lpfc_find_vport_by_vpid(phba, acqe_fcoe->index - phba->vpi_base); - if (!vport) - break; - ndlp = lpfc_findnode_did(vport, Fabric_DID); + ndlp = lpfc_sli4_perform_vport_cvl(vport); if (!ndlp) break; - shost = lpfc_shost_from_vport(vport); - if (phba->pport->port_state <= LPFC_FLOGI) - break; - /* If virtual link is not yet instantiated ignore CVL */ - if (vport->port_state <= LPFC_FDISC) - break; - - lpfc_linkdown_port(vport); - lpfc_cleanup_pending_mbox(vport); - spin_lock_irq(shost->host_lock); - vport->fc_flag |= FC_VPORT_CVL_RCVD; - spin_unlock_irq(shost->host_lock); active_vlink_present = 0; vports = lpfc_create_vport_work_array(phba); @@ -3340,6 +3408,7 @@ lpfc_sli4_async_fcoe_evt(struct lpfc_hba *phba, * re-instantiate the Vlink using FDISC. */ mod_timer(&ndlp->nlp_delayfunc, jiffies + HZ); + shost = lpfc_shost_from_vport(vport); spin_lock_irq(shost->host_lock); ndlp->nlp_flag |= NLP_DELAY_TMO; spin_unlock_irq(shost->host_lock); @@ -3350,15 +3419,28 @@ lpfc_sli4_async_fcoe_evt(struct lpfc_hba *phba, * Otherwise, we request port to rediscover * the entire FCF table for a fast recovery * from possible case that the current FCF - * is no longer valid. + * is no longer valid if the FCF_DEAD event + * hasn't already triggered process. */ + spin_lock_irq(&phba->hbalock); + if (phba->fcf.fcf_flag & FCF_DEAD_FOVER) { + spin_unlock_irq(&phba->hbalock); + break; + } + /* Mark the fast failover process in progress */ + phba->fcf.fcf_flag |= FCF_CVL_FOVER; + spin_unlock_irq(&phba->hbalock); rc = lpfc_sli4_redisc_fcf_table(phba); - if (rc) + if (rc) { + spin_lock_irq(&phba->hbalock); + phba->fcf.fcf_flag &= ~FCF_CVL_FOVER; + spin_unlock_irq(&phba->hbalock); /* * Last resort will be re-try on the * the current registered FCF entry. */ lpfc_retry_pport_discovery(phba); + } } break; default: diff --git a/drivers/scsi/lpfc/lpfc_sli.c b/drivers/scsi/lpfc/lpfc_sli.c index 9feeaff47a52..bb6a4426d469 100644 --- a/drivers/scsi/lpfc/lpfc_sli.c +++ b/drivers/scsi/lpfc/lpfc_sli.c @@ -4519,6 +4519,10 @@ lpfc_sli4_hba_setup(struct lpfc_hba *phba) /* Post receive buffers to the device */ lpfc_sli4_rb_setup(phba); + /* Reset HBA FCF states after HBA reset */ + phba->fcf.fcf_flag = 0; + phba->fcf.current_rec.flag = 0; + /* Start the ELS watchdog timer */ mod_timer(&vport->els_tmofunc, jiffies + HZ * (phba->fc_ratov * 2)); @@ -12069,11 +12073,26 @@ lpfc_mbx_cmpl_redisc_fcf_table(struct lpfc_hba *phba, LPFC_MBOXQ_t *mbox) "2746 Requesting for FCF rediscovery failed " "status x%x add_status x%x\n", shdr_status, shdr_add_status); - /* - * Request failed, last resort to re-try current - * registered FCF entry - */ - lpfc_retry_pport_discovery(phba); + if (phba->fcf.fcf_flag & FCF_CVL_FOVER) { + spin_lock_irq(&phba->hbalock); + phba->fcf.fcf_flag &= ~FCF_CVL_FOVER; + spin_unlock_irq(&phba->hbalock); + /* + * CVL event triggered FCF rediscover request failed, + * last resort to re-try current registered FCF entry. + */ + lpfc_retry_pport_discovery(phba); + } else { + spin_lock_irq(&phba->hbalock); + phba->fcf.fcf_flag &= ~FCF_DEAD_FOVER; + spin_unlock_irq(&phba->hbalock); + /* + * DEAD FCF event triggered FCF rediscover request + * failed, last resort to fail over as a link down + * to FCF registration. + */ + lpfc_sli4_fcf_dead_failthrough(phba); + } } else /* * Start FCF rediscovery wait timer for pending FCF @@ -12128,6 +12147,31 @@ lpfc_sli4_redisc_fcf_table(struct lpfc_hba *phba) return 0; } +/** + * lpfc_sli4_fcf_dead_failthrough - Failthrough routine to fcf dead event + * @phba: pointer to lpfc hba data structure. + * + * This function is the failover routine as a last resort to the FCF DEAD + * event when driver failed to perform fast FCF failover. + **/ +void +lpfc_sli4_fcf_dead_failthrough(struct lpfc_hba *phba) +{ + uint32_t link_state; + + /* + * Last resort as FCF DEAD event failover will treat this as + * a link down, but save the link state because we don't want + * it to be changed to Link Down unless it is already down. + */ + link_state = phba->link_state; + lpfc_linkdown(phba); + phba->link_state = link_state; + + /* Unregister FCF if no devices connected to it */ + lpfc_unregister_unused_fcf(phba); +} + /** * lpfc_sli_read_link_ste - Read region 23 to decide if link is disabled. * @phba: pointer to lpfc hba data structure. diff --git a/drivers/scsi/lpfc/lpfc_sli4.h b/drivers/scsi/lpfc/lpfc_sli4.h index 04fd7829cf39..2169cd24d90c 100644 --- a/drivers/scsi/lpfc/lpfc_sli4.h +++ b/drivers/scsi/lpfc/lpfc_sli4.h @@ -153,9 +153,11 @@ struct lpfc_fcf { #define FCF_REGISTERED 0x02 /* FCF registered with FW */ #define FCF_SCAN_DONE 0x04 /* FCF table scan done */ #define FCF_IN_USE 0x08 /* Atleast one discovery completed */ -#define FCF_REDISC_PEND 0x10 /* FCF rediscovery pending */ -#define FCF_REDISC_EVT 0x20 /* FCF rediscovery event to worker thread */ -#define FCF_REDISC_FOV 0x40 /* Post FCF rediscovery fast failover */ +#define FCF_DEAD_FOVER 0x10 /* FCF DEAD triggered fast FCF failover */ +#define FCF_CVL_FOVER 0x20 /* CVL triggered fast FCF failover */ +#define FCF_REDISC_PEND 0x40 /* FCF rediscovery pending */ +#define FCF_REDISC_EVT 0x80 /* FCF rediscovery event to worker thread */ +#define FCF_REDISC_FOV 0x100 /* Post FCF rediscovery fast failover */ uint32_t addr_mode; struct lpfc_fcf_rec current_rec; struct lpfc_fcf_rec failover_rec; -- cgit v1.2.3 From 0c9ab6f5cb28199ef5de84874d135ed44f64d92b Mon Sep 17 00:00:00 2001 From: James Smart Date: Fri, 26 Feb 2010 14:15:57 -0500 Subject: [SCSI] lpfc 8.3.10: Added round robin FCF failover - Added round robin FCF failover on initial or FCF rediscovery FLOGI failure. Signed-off-by: James Smart Signed-off-by: James Bottomley --- drivers/scsi/lpfc/lpfc_crtn.h | 4 + drivers/scsi/lpfc/lpfc_els.c | 91 +++++++- drivers/scsi/lpfc/lpfc_hbadisc.c | 486 +++++++++++++++++++++++++++++++-------- drivers/scsi/lpfc/lpfc_init.c | 123 +++++++--- drivers/scsi/lpfc/lpfc_logmsg.h | 1 + drivers/scsi/lpfc/lpfc_mbox.c | 8 +- drivers/scsi/lpfc/lpfc_sli.c | 218 ++++++++++++++++-- drivers/scsi/lpfc/lpfc_sli4.h | 33 ++- 8 files changed, 802 insertions(+), 162 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/lpfc/lpfc_crtn.h b/drivers/scsi/lpfc/lpfc_crtn.h index 39739a707ed4..5087c4211b43 100644 --- a/drivers/scsi/lpfc/lpfc_crtn.h +++ b/drivers/scsi/lpfc/lpfc_crtn.h @@ -63,6 +63,7 @@ void lpfc_linkdown_port(struct lpfc_vport *); void lpfc_port_link_failure(struct lpfc_vport *); void lpfc_mbx_cmpl_read_la(struct lpfc_hba *, LPFC_MBOXQ_t *); void lpfc_init_vpi_cmpl(struct lpfc_hba *, LPFC_MBOXQ_t *); +void lpfc_cancel_all_vport_retry_delay_timer(struct lpfc_hba *); void lpfc_retry_pport_discovery(struct lpfc_hba *); void lpfc_mbx_cmpl_reg_login(struct lpfc_hba *, LPFC_MBOXQ_t *); @@ -222,6 +223,9 @@ void lpfc_unregister_unused_fcf(struct lpfc_hba *); int lpfc_sli4_redisc_fcf_table(struct lpfc_hba *); void lpfc_fcf_redisc_wait_start_timer(struct lpfc_hba *); void lpfc_sli4_fcf_dead_failthrough(struct lpfc_hba *); +uint16_t lpfc_sli4_fcf_rr_next_index_get(struct lpfc_hba *); +int lpfc_sli4_fcf_rr_index_set(struct lpfc_hba *, uint16_t); +void lpfc_sli4_fcf_rr_index_clear(struct lpfc_hba *, uint16_t); int lpfc_mem_alloc(struct lpfc_hba *, int align); void lpfc_mem_free(struct lpfc_hba *); diff --git a/drivers/scsi/lpfc/lpfc_els.c b/drivers/scsi/lpfc/lpfc_els.c index a81d43306d17..d807f36ba4f9 100644 --- a/drivers/scsi/lpfc/lpfc_els.c +++ b/drivers/scsi/lpfc/lpfc_els.c @@ -771,6 +771,7 @@ lpfc_cmpl_els_flogi(struct lpfc_hba *phba, struct lpfc_iocbq *cmdiocb, struct lpfc_nodelist *ndlp = cmdiocb->context1; struct lpfc_dmabuf *pcmd = cmdiocb->context2, *prsp; struct serv_parm *sp; + uint16_t fcf_index; int rc; /* Check to see if link went down during discovery */ @@ -788,6 +789,54 @@ lpfc_cmpl_els_flogi(struct lpfc_hba *phba, struct lpfc_iocbq *cmdiocb, vport->port_state); if (irsp->ulpStatus) { + /* + * In case of FIP mode, perform round robin FCF failover + * due to new FCF discovery + */ + if ((phba->hba_flag & HBA_FIP_SUPPORT) && + (phba->fcf.fcf_flag & FCF_DISCOVERY)) { + lpfc_printf_log(phba, KERN_WARNING, LOG_FIP | LOG_ELS, + "2611 FLOGI failed on registered " + "FCF record fcf_index:%d, trying " + "to perform round robin failover\n", + phba->fcf.current_rec.fcf_indx); + fcf_index = lpfc_sli4_fcf_rr_next_index_get(phba); + if (fcf_index == LPFC_FCOE_FCF_NEXT_NONE) { + /* + * Exhausted the eligible FCF record list, + * fail through to retry FLOGI on current + * FCF record. + */ + lpfc_printf_log(phba, KERN_WARNING, + LOG_FIP | LOG_ELS, + "2760 FLOGI exhausted FCF " + "round robin failover list, " + "retry FLOGI on the current " + "registered FCF index:%d\n", + phba->fcf.current_rec.fcf_indx); + spin_lock_irq(&phba->hbalock); + phba->fcf.fcf_flag &= ~FCF_DISCOVERY; + spin_unlock_irq(&phba->hbalock); + } else { + rc = lpfc_sli4_fcf_rr_read_fcf_rec(phba, + fcf_index); + if (rc) { + lpfc_printf_log(phba, KERN_WARNING, + LOG_FIP | LOG_ELS, + "2761 FLOGI round " + "robin FCF failover " + "read FCF failed " + "rc:x%x, fcf_index:" + "%d\n", rc, + phba->fcf.current_rec.fcf_indx); + spin_lock_irq(&phba->hbalock); + phba->fcf.fcf_flag &= ~FCF_DISCOVERY; + spin_unlock_irq(&phba->hbalock); + } else + goto out; + } + } + /* Check for retry */ if (lpfc_els_retry(phba, cmdiocb, rspiocb)) goto out; @@ -841,8 +890,18 @@ lpfc_cmpl_els_flogi(struct lpfc_hba *phba, struct lpfc_iocbq *cmdiocb, else rc = lpfc_cmpl_els_flogi_nport(vport, ndlp, sp); - if (!rc) + if (!rc) { + /* Mark the FCF discovery process done */ + lpfc_printf_vlog(vport, KERN_INFO, LOG_FIP | LOG_ELS, + "2769 FLOGI successful on FCF record: " + "current_fcf_index:x%x, terminate FCF " + "round robin failover process\n", + phba->fcf.current_rec.fcf_indx); + spin_lock_irq(&phba->hbalock); + phba->fcf.fcf_flag &= ~FCF_DISCOVERY; + spin_unlock_irq(&phba->hbalock); goto out; + } } flogifail: @@ -6075,21 +6134,18 @@ mbox_err_exit: } /** - * lpfc_retry_pport_discovery - Start timer to retry FLOGI. + * lpfc_cancel_all_vport_retry_delay_timer - Cancel all vport retry delay timer * @phba: pointer to lpfc hba data structure. * - * This routine abort all pending discovery commands and - * start a timer to retry FLOGI for the physical port - * discovery. + * This routine cancels the retry delay timers to all the vports. **/ void -lpfc_retry_pport_discovery(struct lpfc_hba *phba) +lpfc_cancel_all_vport_retry_delay_timer(struct lpfc_hba *phba) { struct lpfc_vport **vports; struct lpfc_nodelist *ndlp; - struct Scsi_Host *shost; - int i; uint32_t link_state; + int i; /* Treat this failure as linkdown for all vports */ link_state = phba->link_state; @@ -6107,13 +6163,30 @@ lpfc_retry_pport_discovery(struct lpfc_hba *phba) } lpfc_destroy_vport_work_array(phba, vports); } +} + +/** + * lpfc_retry_pport_discovery - Start timer to retry FLOGI. + * @phba: pointer to lpfc hba data structure. + * + * This routine abort all pending discovery commands and + * start a timer to retry FLOGI for the physical port + * discovery. + **/ +void +lpfc_retry_pport_discovery(struct lpfc_hba *phba) +{ + struct lpfc_nodelist *ndlp; + struct Scsi_Host *shost; + + /* Cancel the all vports retry delay retry timers */ + lpfc_cancel_all_vport_retry_delay_timer(phba); /* If fabric require FLOGI, then re-instantiate physical login */ ndlp = lpfc_findnode_did(phba->pport, Fabric_DID); if (!ndlp) return; - shost = lpfc_shost_from_vport(phba->pport); mod_timer(&ndlp->nlp_delayfunc, jiffies + HZ); spin_lock_irq(shost->host_lock); diff --git a/drivers/scsi/lpfc/lpfc_hbadisc.c b/drivers/scsi/lpfc/lpfc_hbadisc.c index f28ce40dc349..c555e3b7f202 100644 --- a/drivers/scsi/lpfc/lpfc_hbadisc.c +++ b/drivers/scsi/lpfc/lpfc_hbadisc.c @@ -1481,8 +1481,6 @@ lpfc_match_fcf_conn_list(struct lpfc_hba *phba, int lpfc_check_pending_fcoe_event(struct lpfc_hba *phba, uint8_t unreg_fcf) { - LPFC_MBOXQ_t *mbox; - int rc; /* * If the Link is up and no FCoE events while in the * FCF discovery, no need to restart FCF discovery. @@ -1491,88 +1489,70 @@ lpfc_check_pending_fcoe_event(struct lpfc_hba *phba, uint8_t unreg_fcf) (phba->fcoe_eventtag == phba->fcoe_eventtag_at_fcf_scan)) return 0; + lpfc_printf_log(phba, KERN_INFO, LOG_FIP, + "2768 Pending link or FCF event during current " + "handling of the previous event: link_state:x%x, " + "evt_tag_at_scan:x%x, evt_tag_current:x%x\n", + phba->link_state, phba->fcoe_eventtag_at_fcf_scan, + phba->fcoe_eventtag); + spin_lock_irq(&phba->hbalock); phba->fcf.fcf_flag &= ~FCF_AVAILABLE; spin_unlock_irq(&phba->hbalock); - if (phba->link_state >= LPFC_LINK_UP) - lpfc_sli4_read_fcf_record(phba, LPFC_FCOE_FCF_GET_FIRST); - else { + if (phba->link_state >= LPFC_LINK_UP) { + lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY, + "2780 Restart FCF table scan due to " + "pending FCF event:evt_tag_at_scan:x%x, " + "evt_tag_current:x%x\n", + phba->fcoe_eventtag_at_fcf_scan, + phba->fcoe_eventtag); + lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST); + } else { /* * Do not continue FCF discovery and clear FCF_DISC_INPROGRESS * flag */ spin_lock_irq(&phba->hbalock); phba->hba_flag &= ~FCF_DISC_INPROGRESS; - phba->fcf.fcf_flag &= ~(FCF_REDISC_FOV | - FCF_DEAD_FOVER | - FCF_CVL_FOVER); + phba->fcf.fcf_flag &= ~(FCF_REDISC_FOV | FCF_DISCOVERY); spin_unlock_irq(&phba->hbalock); } + /* Unregister the currently registered FCF if required */ if (unreg_fcf) { spin_lock_irq(&phba->hbalock); phba->fcf.fcf_flag &= ~FCF_REGISTERED; spin_unlock_irq(&phba->hbalock); - mbox = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL); - if (!mbox) { - lpfc_printf_log(phba, KERN_ERR, - LOG_DISCOVERY|LOG_MBOX, - "2610 UNREG_FCFI mbox allocation failed\n"); - return 1; - } - lpfc_unreg_fcfi(mbox, phba->fcf.fcfi); - mbox->vport = phba->pport; - mbox->mbox_cmpl = lpfc_unregister_fcfi_cmpl; - rc = lpfc_sli_issue_mbox(phba, mbox, MBX_NOWAIT); - if (rc == MBX_NOT_FINISHED) { - lpfc_printf_log(phba, KERN_ERR, LOG_DISCOVERY|LOG_MBOX, - "2611 UNREG_FCFI issue mbox failed\n"); - mempool_free(mbox, phba->mbox_mem_pool); - } + lpfc_sli4_unregister_fcf(phba); } - return 1; } /** - * lpfc_mbx_cmpl_read_fcf_record - Completion handler for read_fcf mbox. + * lpfc_sli4_fcf_rec_mbox_parse - parse non-embedded fcf record mailbox command * @phba: pointer to lpfc hba data structure. * @mboxq: pointer to mailbox object. + * @next_fcf_index: pointer to holder of next fcf index. * - * This function iterate through all the fcf records available in - * HBA and choose the optimal FCF record for discovery. After finding - * the FCF for discovery it register the FCF record and kick start - * discovery. - * If FCF_IN_USE flag is set in currently used FCF, the routine try to - * use a FCF record which match fabric name and mac address of the - * currently used FCF record. - * If the driver support only one FCF, it will try to use the FCF record - * used by BOOT_BIOS. + * This routine parses the non-embedded fcf mailbox command by performing the + * necessarily error checking, non-embedded read FCF record mailbox command + * SGE parsing, and endianness swapping. + * + * Returns the pointer to the new FCF record in the non-embedded mailbox + * command DMA memory if successfully, other NULL. */ -void -lpfc_mbx_cmpl_read_fcf_record(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) +static struct fcf_record * +lpfc_sli4_fcf_rec_mbox_parse(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq, + uint16_t *next_fcf_index) { void *virt_addr; dma_addr_t phys_addr; - uint8_t *bytep; struct lpfc_mbx_sge sge; struct lpfc_mbx_read_fcf_tbl *read_fcf; uint32_t shdr_status, shdr_add_status; union lpfc_sli4_cfg_shdr *shdr; struct fcf_record *new_fcf_record; - uint32_t boot_flag, addr_mode; - uint32_t next_fcf_index; - struct lpfc_fcf_rec *fcf_rec = NULL; - unsigned long iflags; - uint16_t vlan_id; - int rc; - - /* If there is pending FCoE event restart FCF table scan */ - if (lpfc_check_pending_fcoe_event(phba, 0)) { - lpfc_sli4_mbox_cmd_free(phba, mboxq); - return; - } /* Get the first SGE entry from the non-embedded DMA memory. This * routine only uses a single SGE. @@ -1583,59 +1563,183 @@ lpfc_mbx_cmpl_read_fcf_record(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) lpfc_printf_log(phba, KERN_ERR, LOG_MBOX, "2524 Failed to get the non-embedded SGE " "virtual address\n"); - goto out; + return NULL; } virt_addr = mboxq->sge_array->addr[0]; shdr = (union lpfc_sli4_cfg_shdr *)virt_addr; shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response); - shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, - &shdr->response); - /* - * The FCF Record was read and there is no reason for the driver - * to maintain the FCF record data or memory. Instead, just need - * to book keeping the FCFIs can be used. - */ + shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response); if (shdr_status || shdr_add_status) { - if (shdr_status == STATUS_FCF_TABLE_EMPTY) { - lpfc_printf_log(phba, KERN_ERR, LOG_INIT, + if (shdr_status == STATUS_FCF_TABLE_EMPTY) + lpfc_printf_log(phba, KERN_ERR, LOG_FIP, "2726 READ_FCF_RECORD Indicates empty " "FCF table.\n"); - } else { - lpfc_printf_log(phba, KERN_ERR, LOG_INIT, + else + lpfc_printf_log(phba, KERN_ERR, LOG_FIP, "2521 READ_FCF_RECORD mailbox failed " - "with status x%x add_status x%x, mbx\n", - shdr_status, shdr_add_status); - } - goto out; + "with status x%x add_status x%x, " + "mbx\n", shdr_status, shdr_add_status); + return NULL; } - /* Interpreting the returned information of FCF records */ + + /* Interpreting the returned information of the FCF record */ read_fcf = (struct lpfc_mbx_read_fcf_tbl *)virt_addr; lpfc_sli_pcimem_bcopy(read_fcf, read_fcf, sizeof(struct lpfc_mbx_read_fcf_tbl)); - next_fcf_index = bf_get(lpfc_mbx_read_fcf_tbl_nxt_vindx, read_fcf); - + *next_fcf_index = bf_get(lpfc_mbx_read_fcf_tbl_nxt_vindx, read_fcf); new_fcf_record = (struct fcf_record *)(virt_addr + sizeof(struct lpfc_mbx_read_fcf_tbl)); lpfc_sli_pcimem_bcopy(new_fcf_record, new_fcf_record, sizeof(struct fcf_record)); - bytep = virt_addr + sizeof(union lpfc_sli4_cfg_shdr); + return new_fcf_record; +} + +/** + * lpfc_sli4_log_fcf_record_info - Log the information of a fcf record + * @phba: pointer to lpfc hba data structure. + * @fcf_record: pointer to the fcf record. + * @vlan_id: the lowest vlan identifier associated to this fcf record. + * @next_fcf_index: the index to the next fcf record in hba's fcf table. + * + * This routine logs the detailed FCF record if the LOG_FIP loggin is + * enabled. + **/ +static void +lpfc_sli4_log_fcf_record_info(struct lpfc_hba *phba, + struct fcf_record *fcf_record, + uint16_t vlan_id, + uint16_t next_fcf_index) +{ + lpfc_printf_log(phba, KERN_INFO, LOG_FIP, + "2764 READ_FCF_RECORD:\n" + "\tFCF_Index : x%x\n" + "\tFCF_Avail : x%x\n" + "\tFCF_Valid : x%x\n" + "\tFIP_Priority : x%x\n" + "\tMAC_Provider : x%x\n" + "\tLowest VLANID : x%x\n" + "\tFCF_MAC Addr : x%x:%x:%x:%x:%x:%x\n" + "\tFabric_Name : x%x:%x:%x:%x:%x:%x:%x:%x\n" + "\tSwitch_Name : x%x:%x:%x:%x:%x:%x:%x:%x\n" + "\tNext_FCF_Index: x%x\n", + bf_get(lpfc_fcf_record_fcf_index, fcf_record), + bf_get(lpfc_fcf_record_fcf_avail, fcf_record), + bf_get(lpfc_fcf_record_fcf_valid, fcf_record), + fcf_record->fip_priority, + bf_get(lpfc_fcf_record_mac_addr_prov, fcf_record), + vlan_id, + bf_get(lpfc_fcf_record_mac_0, fcf_record), + bf_get(lpfc_fcf_record_mac_1, fcf_record), + bf_get(lpfc_fcf_record_mac_2, fcf_record), + bf_get(lpfc_fcf_record_mac_3, fcf_record), + bf_get(lpfc_fcf_record_mac_4, fcf_record), + bf_get(lpfc_fcf_record_mac_5, fcf_record), + bf_get(lpfc_fcf_record_fab_name_0, fcf_record), + bf_get(lpfc_fcf_record_fab_name_1, fcf_record), + bf_get(lpfc_fcf_record_fab_name_2, fcf_record), + bf_get(lpfc_fcf_record_fab_name_3, fcf_record), + bf_get(lpfc_fcf_record_fab_name_4, fcf_record), + bf_get(lpfc_fcf_record_fab_name_5, fcf_record), + bf_get(lpfc_fcf_record_fab_name_6, fcf_record), + bf_get(lpfc_fcf_record_fab_name_7, fcf_record), + bf_get(lpfc_fcf_record_switch_name_0, fcf_record), + bf_get(lpfc_fcf_record_switch_name_1, fcf_record), + bf_get(lpfc_fcf_record_switch_name_2, fcf_record), + bf_get(lpfc_fcf_record_switch_name_3, fcf_record), + bf_get(lpfc_fcf_record_switch_name_4, fcf_record), + bf_get(lpfc_fcf_record_switch_name_5, fcf_record), + bf_get(lpfc_fcf_record_switch_name_6, fcf_record), + bf_get(lpfc_fcf_record_switch_name_7, fcf_record), + next_fcf_index); +} + +/** + * lpfc_mbx_cmpl_fcf_scan_read_fcf_rec - fcf scan read_fcf mbox cmpl handler. + * @phba: pointer to lpfc hba data structure. + * @mboxq: pointer to mailbox object. + * + * This function iterates through all the fcf records available in + * HBA and chooses the optimal FCF record for discovery. After finding + * the FCF for discovery it registers the FCF record and kicks start + * discovery. + * If FCF_IN_USE flag is set in currently used FCF, the routine tries to + * use an FCF record which matches fabric name and mac address of the + * currently used FCF record. + * If the driver supports only one FCF, it will try to use the FCF record + * used by BOOT_BIOS. + */ +void +lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) +{ + struct fcf_record *new_fcf_record; + uint32_t boot_flag, addr_mode; + uint16_t fcf_index, next_fcf_index; + struct lpfc_fcf_rec *fcf_rec = NULL; + uint16_t vlan_id; + int rc; + + /* If there is pending FCoE event restart FCF table scan */ + if (lpfc_check_pending_fcoe_event(phba, 0)) { + lpfc_sli4_mbox_cmd_free(phba, mboxq); + return; + } + + /* Parse the FCF record from the non-embedded mailbox command */ + new_fcf_record = lpfc_sli4_fcf_rec_mbox_parse(phba, mboxq, + &next_fcf_index); + if (!new_fcf_record) { + lpfc_printf_log(phba, KERN_WARNING, LOG_FIP, + "2765 Mailbox command READ_FCF_RECORD " + "failed to retrieve a FCF record.\n"); + /* Let next new FCF event trigger fast failover */ + spin_lock_irq(&phba->hbalock); + phba->hba_flag &= ~FCF_DISC_INPROGRESS; + spin_unlock_irq(&phba->hbalock); + lpfc_sli4_mbox_cmd_free(phba, mboxq); + return; + } + + /* Check the FCF record against the connection list */ rc = lpfc_match_fcf_conn_list(phba, new_fcf_record, &boot_flag, &addr_mode, &vlan_id); + + /* Log the FCF record information if turned on */ + lpfc_sli4_log_fcf_record_info(phba, new_fcf_record, vlan_id, + next_fcf_index); + /* * If the fcf record does not match with connect list entries - * read the next entry. + * read the next entry; otherwise, this is an eligible FCF + * record for round robin FCF failover. */ - if (!rc) + if (!rc) { + lpfc_printf_log(phba, KERN_WARNING, LOG_FIP, + "2781 FCF record fcf_index:x%x failed FCF " + "connection list check, fcf_avail:x%x, " + "fcf_valid:x%x\n", + bf_get(lpfc_fcf_record_fcf_index, + new_fcf_record), + bf_get(lpfc_fcf_record_fcf_avail, + new_fcf_record), + bf_get(lpfc_fcf_record_fcf_valid, + new_fcf_record)); goto read_next_fcf; + } else { + fcf_index = bf_get(lpfc_fcf_record_fcf_index, new_fcf_record); + rc = lpfc_sli4_fcf_rr_index_set(phba, fcf_index); + if (rc) + goto read_next_fcf; + } + /* * If this is not the first FCF discovery of the HBA, use last * FCF record for the discovery. The condition that a rescan * matches the in-use FCF record: fabric name, switch name, mac * address, and vlan_id. */ - spin_lock_irqsave(&phba->hbalock, iflags); + spin_lock_irq(&phba->hbalock); if (phba->fcf.fcf_flag & FCF_IN_USE) { if (lpfc_fab_name_match(phba->fcf.current_rec.fabric_name, new_fcf_record) && @@ -1652,9 +1756,8 @@ lpfc_mbx_cmpl_read_fcf_record(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) else if (phba->fcf.fcf_flag & FCF_REDISC_FOV) /* If in fast failover, mark it's completed */ phba->fcf.fcf_flag &= ~(FCF_REDISC_FOV | - FCF_DEAD_FOVER | - FCF_CVL_FOVER); - spin_unlock_irqrestore(&phba->hbalock, iflags); + FCF_DISCOVERY); + spin_unlock_irq(&phba->hbalock); goto out; } /* @@ -1665,7 +1768,7 @@ lpfc_mbx_cmpl_read_fcf_record(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) * next candidate. */ if (!(phba->fcf.fcf_flag & FCF_REDISC_FOV)) { - spin_unlock_irqrestore(&phba->hbalock, iflags); + spin_unlock_irq(&phba->hbalock); goto read_next_fcf; } } @@ -1688,7 +1791,7 @@ lpfc_mbx_cmpl_read_fcf_record(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) /* Choose this FCF record */ __lpfc_update_fcf_record(phba, fcf_rec, new_fcf_record, addr_mode, vlan_id, BOOT_ENABLE); - spin_unlock_irqrestore(&phba->hbalock, iflags); + spin_unlock_irq(&phba->hbalock); goto read_next_fcf; } /* @@ -1697,7 +1800,7 @@ lpfc_mbx_cmpl_read_fcf_record(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) * the next FCF record. */ if (!boot_flag && (fcf_rec->flag & BOOT_ENABLE)) { - spin_unlock_irqrestore(&phba->hbalock, iflags); + spin_unlock_irq(&phba->hbalock); goto read_next_fcf; } /* @@ -1709,7 +1812,7 @@ lpfc_mbx_cmpl_read_fcf_record(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) __lpfc_update_fcf_record(phba, fcf_rec, new_fcf_record, addr_mode, vlan_id, 0); } - spin_unlock_irqrestore(&phba->hbalock, iflags); + spin_unlock_irq(&phba->hbalock); goto read_next_fcf; } /* @@ -1722,7 +1825,7 @@ lpfc_mbx_cmpl_read_fcf_record(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) BOOT_ENABLE : 0)); phba->fcf.fcf_flag |= FCF_AVAILABLE; } - spin_unlock_irqrestore(&phba->hbalock, iflags); + spin_unlock_irq(&phba->hbalock); goto read_next_fcf; read_next_fcf: @@ -1738,9 +1841,22 @@ read_next_fcf: * FCF scan inprogress, and do nothing */ if (!(phba->fcf.failover_rec.flag & RECORD_VALID)) { - spin_lock_irqsave(&phba->hbalock, iflags); + lpfc_printf_log(phba, KERN_WARNING, LOG_FIP, + "2782 No suitable FCF record " + "found during this round of " + "post FCF rediscovery scan: " + "fcf_evt_tag:x%x, fcf_index: " + "x%x\n", + phba->fcoe_eventtag_at_fcf_scan, + bf_get(lpfc_fcf_record_fcf_index, + new_fcf_record)); + /* + * Let next new FCF event trigger fast + * failover + */ + spin_lock_irq(&phba->hbalock); phba->hba_flag &= ~FCF_DISC_INPROGRESS; - spin_unlock_irqrestore(&phba->hbalock, iflags); + spin_unlock_irq(&phba->hbalock); return; } /* @@ -1752,18 +1868,23 @@ read_next_fcf: * record. */ - /* unregister the current in-use FCF record */ + /* Unregister the current in-use FCF record */ lpfc_unregister_fcf(phba); - /* replace in-use record with the new record */ + + /* Replace in-use record with the new record */ memcpy(&phba->fcf.current_rec, &phba->fcf.failover_rec, sizeof(struct lpfc_fcf_rec)); /* mark the FCF fast failover completed */ - spin_lock_irqsave(&phba->hbalock, iflags); - phba->fcf.fcf_flag &= ~(FCF_REDISC_FOV | - FCF_DEAD_FOVER | - FCF_CVL_FOVER); - spin_unlock_irqrestore(&phba->hbalock, iflags); + spin_lock_irq(&phba->hbalock); + phba->fcf.fcf_flag &= ~FCF_REDISC_FOV; + spin_unlock_irq(&phba->hbalock); + /* + * Set up the initial registered FCF index for FLOGI + * round robin FCF failover. + */ + phba->fcf.fcf_rr_init_indx = + phba->fcf.failover_rec.fcf_indx; /* Register to the new FCF record */ lpfc_register_fcf(phba); } else { @@ -1776,13 +1897,25 @@ read_next_fcf: return; /* * Otherwise, initial scan or post linkdown rescan, - * register with the best fit FCF record found so - * far through the scanning process. + * register with the best FCF record found so far + * through the FCF scanning process. + */ + + /* mark the initial FCF discovery completed */ + spin_lock_irq(&phba->hbalock); + phba->fcf.fcf_flag &= ~FCF_INIT_DISC; + spin_unlock_irq(&phba->hbalock); + /* + * Set up the initial registered FCF index for FLOGI + * round robin FCF failover */ + phba->fcf.fcf_rr_init_indx = + phba->fcf.current_rec.fcf_indx; + /* Register to the new FCF record */ lpfc_register_fcf(phba); } } else - lpfc_sli4_read_fcf_record(phba, next_fcf_index); + lpfc_sli4_fcf_scan_read_fcf_rec(phba, next_fcf_index); return; out: @@ -1792,6 +1925,141 @@ out: return; } +/** + * lpfc_mbx_cmpl_fcf_rr_read_fcf_rec - fcf round robin read_fcf mbox cmpl hdler + * @phba: pointer to lpfc hba data structure. + * @mboxq: pointer to mailbox object. + * + * This is the callback function for FLOGI failure round robin FCF failover + * read FCF record mailbox command from the eligible FCF record bmask for + * performing the failover. If the FCF read back is not valid/available, it + * fails through to retrying FLOGI to the currently registered FCF again. + * Otherwise, if the FCF read back is valid and available, it will set the + * newly read FCF record to the failover FCF record, unregister currently + * registered FCF record, copy the failover FCF record to the current + * FCF record, and then register the current FCF record before proceeding + * to trying FLOGI on the new failover FCF. + */ +void +lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) +{ + struct fcf_record *new_fcf_record; + uint32_t boot_flag, addr_mode; + uint16_t next_fcf_index; + uint16_t current_fcf_index; + uint16_t vlan_id; + + /* If link state is not up, stop the round robin failover process */ + if (phba->link_state < LPFC_LINK_UP) { + spin_lock_irq(&phba->hbalock); + phba->fcf.fcf_flag &= ~FCF_DISCOVERY; + spin_unlock_irq(&phba->hbalock); + lpfc_sli4_mbox_cmd_free(phba, mboxq); + return; + } + + /* Parse the FCF record from the non-embedded mailbox command */ + new_fcf_record = lpfc_sli4_fcf_rec_mbox_parse(phba, mboxq, + &next_fcf_index); + if (!new_fcf_record) { + lpfc_printf_log(phba, KERN_WARNING, LOG_FIP, + "2766 Mailbox command READ_FCF_RECORD " + "failed to retrieve a FCF record.\n"); + goto out; + } + + /* Get the needed parameters from FCF record */ + lpfc_match_fcf_conn_list(phba, new_fcf_record, &boot_flag, + &addr_mode, &vlan_id); + + /* Log the FCF record information if turned on */ + lpfc_sli4_log_fcf_record_info(phba, new_fcf_record, vlan_id, + next_fcf_index); + + /* Upload new FCF record to the failover FCF record */ + spin_lock_irq(&phba->hbalock); + __lpfc_update_fcf_record(phba, &phba->fcf.failover_rec, + new_fcf_record, addr_mode, vlan_id, + (boot_flag ? BOOT_ENABLE : 0)); + spin_unlock_irq(&phba->hbalock); + + current_fcf_index = phba->fcf.current_rec.fcf_indx; + + /* Unregister the current in-use FCF record */ + lpfc_unregister_fcf(phba); + + /* Replace in-use record with the new record */ + memcpy(&phba->fcf.current_rec, &phba->fcf.failover_rec, + sizeof(struct lpfc_fcf_rec)); + + lpfc_printf_log(phba, KERN_INFO, LOG_FIP, + "2783 FLOGI round robin FCF failover from FCF " + "(index:x%x) to FCF (index:x%x).\n", + current_fcf_index, + bf_get(lpfc_fcf_record_fcf_index, new_fcf_record)); + +out: + lpfc_sli4_mbox_cmd_free(phba, mboxq); + lpfc_register_fcf(phba); +} + +/** + * lpfc_mbx_cmpl_read_fcf_rec - read fcf completion handler. + * @phba: pointer to lpfc hba data structure. + * @mboxq: pointer to mailbox object. + * + * This is the callback function of read FCF record mailbox command for + * updating the eligible FCF bmask for FLOGI failure round robin FCF + * failover when a new FCF event happened. If the FCF read back is + * valid/available and it passes the connection list check, it updates + * the bmask for the eligible FCF record for round robin failover. + */ +void +lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq) +{ + struct fcf_record *new_fcf_record; + uint32_t boot_flag, addr_mode; + uint16_t fcf_index, next_fcf_index; + uint16_t vlan_id; + int rc; + + /* If link state is not up, no need to proceed */ + if (phba->link_state < LPFC_LINK_UP) + goto out; + + /* If FCF discovery period is over, no need to proceed */ + if (phba->fcf.fcf_flag & FCF_DISCOVERY) + goto out; + + /* Parse the FCF record from the non-embedded mailbox command */ + new_fcf_record = lpfc_sli4_fcf_rec_mbox_parse(phba, mboxq, + &next_fcf_index); + if (!new_fcf_record) { + lpfc_printf_log(phba, KERN_INFO, LOG_FIP, + "2767 Mailbox command READ_FCF_RECORD " + "failed to retrieve a FCF record.\n"); + goto out; + } + + /* Check the connection list for eligibility */ + rc = lpfc_match_fcf_conn_list(phba, new_fcf_record, &boot_flag, + &addr_mode, &vlan_id); + + /* Log the FCF record information if turned on */ + lpfc_sli4_log_fcf_record_info(phba, new_fcf_record, vlan_id, + next_fcf_index); + + if (!rc) + goto out; + + /* Update the eligible FCF record index bmask */ + fcf_index = bf_get(lpfc_fcf_record_fcf_index, new_fcf_record); + rc = lpfc_sli4_fcf_rr_index_set(phba, fcf_index); + +out: + lpfc_sli4_mbox_cmd_free(phba, mboxq); +} + /** * lpfc_init_vpi_cmpl - Completion handler for init_vpi mbox command. * @phba: pointer to lpfc hba data structure. @@ -2190,10 +2458,20 @@ lpfc_mbx_process_link_up(struct lpfc_hba *phba, READ_LA_VAR *la) spin_unlock_irq(&phba->hbalock); return; } + /* This is the initial FCF discovery scan */ + phba->fcf.fcf_flag |= FCF_INIT_DISC; spin_unlock_irq(&phba->hbalock); - rc = lpfc_sli4_read_fcf_record(phba, LPFC_FCOE_FCF_GET_FIRST); - if (rc) + lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY, + "2778 Start FCF table scan at linkup\n"); + + rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, + LPFC_FCOE_FCF_GET_FIRST); + if (rc) { + spin_lock_irq(&phba->hbalock); + phba->fcf.fcf_flag &= ~FCF_INIT_DISC; + spin_unlock_irq(&phba->hbalock); goto out; + } } return; @@ -3383,8 +3661,12 @@ lpfc_unreg_hba_rpis(struct lpfc_hba *phba) shost = lpfc_shost_from_vport(vports[i]); spin_lock_irq(shost->host_lock); list_for_each_entry(ndlp, &vports[i]->fc_nodes, nlp_listp) { - if (ndlp->nlp_flag & NLP_RPI_VALID) + if (ndlp->nlp_flag & NLP_RPI_VALID) { + /* The mempool_alloc might sleep */ + spin_unlock_irq(shost->host_lock); lpfc_unreg_rpi(vports[i], ndlp); + spin_lock_irq(shost->host_lock); + } } spin_unlock_irq(shost->host_lock); } @@ -4770,13 +5052,21 @@ lpfc_unregister_fcf_rescan(struct lpfc_hba *phba) (phba->link_state < LPFC_LINK_UP)) return; - rc = lpfc_sli4_read_fcf_record(phba, LPFC_FCOE_FCF_GET_FIRST); + /* This is considered as the initial FCF discovery scan */ + spin_lock_irq(&phba->hbalock); + phba->fcf.fcf_flag |= FCF_INIT_DISC; + spin_unlock_irq(&phba->hbalock); + rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST); - if (rc) + if (rc) { + spin_lock_irq(&phba->hbalock); + phba->fcf.fcf_flag &= ~FCF_INIT_DISC; + spin_unlock_irq(&phba->hbalock); lpfc_printf_log(phba, KERN_ERR, LOG_DISCOVERY|LOG_MBOX, "2553 lpfc_unregister_unused_fcf failed " "to read FCF record HBA state x%x\n", phba->pport->port_state); + } } /** diff --git a/drivers/scsi/lpfc/lpfc_init.c b/drivers/scsi/lpfc/lpfc_init.c index ff45e336917a..ea44239eeb33 100644 --- a/drivers/scsi/lpfc/lpfc_init.c +++ b/drivers/scsi/lpfc/lpfc_init.c @@ -2201,8 +2201,8 @@ __lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba) { /* Clear pending FCF rediscovery wait and failover in progress flags */ phba->fcf.fcf_flag &= ~(FCF_REDISC_PEND | - FCF_DEAD_FOVER | - FCF_CVL_FOVER); + FCF_DEAD_DISC | + FCF_ACVL_DISC); /* Now, try to stop the timer */ del_timer(&phba->fcf.redisc_wait); } @@ -2943,6 +2943,9 @@ lpfc_sli4_fcf_redisc_wait_tmo(unsigned long ptr) /* FCF rediscovery event to worker thread */ phba->fcf.fcf_flag |= FCF_REDISC_EVT; spin_unlock_irq(&phba->hbalock); + lpfc_printf_log(phba, KERN_INFO, LOG_FIP, + "2776 FCF rediscover wait timer expired, post " + "a worker thread event for FCF table scan\n"); /* wake up worker thread */ lpfc_worker_wake_up(phba); } @@ -3300,10 +3303,11 @@ lpfc_sli4_async_fcoe_evt(struct lpfc_hba *phba, switch (event_type) { case LPFC_FCOE_EVENT_TYPE_NEW_FCF: case LPFC_FCOE_EVENT_TYPE_FCF_PARAM_MOD: - lpfc_printf_log(phba, KERN_ERR, LOG_DISCOVERY, - "2546 New FCF found index 0x%x tag 0x%x\n", - acqe_fcoe->index, - acqe_fcoe->event_tag); + lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY, + "2546 New FCF found/FCF parameter modified event: " + "evt_tag:x%x, fcf_index:x%x\n", + acqe_fcoe->event_tag, acqe_fcoe->index); + spin_lock_irq(&phba->hbalock); if ((phba->fcf.fcf_flag & FCF_SCAN_DONE) || (phba->hba_flag & FCF_DISC_INPROGRESS)) { @@ -3314,6 +3318,7 @@ lpfc_sli4_async_fcoe_evt(struct lpfc_hba *phba, spin_unlock_irq(&phba->hbalock); break; } + if (phba->fcf.fcf_flag & FCF_REDISC_EVT) { /* * If fast FCF failover rescan event is pending, @@ -3324,12 +3329,33 @@ lpfc_sli4_async_fcoe_evt(struct lpfc_hba *phba, } spin_unlock_irq(&phba->hbalock); - /* Read the FCF table and re-discover SAN. */ - rc = lpfc_sli4_read_fcf_record(phba, LPFC_FCOE_FCF_GET_FIRST); + if ((phba->fcf.fcf_flag & FCF_DISCOVERY) && + !(phba->fcf.fcf_flag & FCF_REDISC_FOV)) { + /* + * During period of FCF discovery, read the FCF + * table record indexed by the event to update + * FCF round robin failover eligible FCF bmask. + */ + lpfc_printf_log(phba, KERN_INFO, LOG_FIP | + LOG_DISCOVERY, + "2779 Read new FCF record with " + "fcf_index:x%x for updating FCF " + "round robin failover bmask\n", + acqe_fcoe->index); + rc = lpfc_sli4_read_fcf_rec(phba, acqe_fcoe->index); + } + + /* Otherwise, scan the entire FCF table and re-discover SAN */ + lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY, + "2770 Start FCF table scan due to new FCF " + "event: evt_tag:x%x, fcf_index:x%x\n", + acqe_fcoe->event_tag, acqe_fcoe->index); + rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, + LPFC_FCOE_FCF_GET_FIRST); if (rc) - lpfc_printf_log(phba, KERN_ERR, LOG_DISCOVERY, - "2547 Read FCF record failed 0x%x\n", - rc); + lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY, + "2547 Issue FCF scan read FCF mailbox " + "command failed 0x%x\n", rc); break; case LPFC_FCOE_EVENT_TYPE_FCF_TABLE_FULL: @@ -3340,7 +3366,7 @@ lpfc_sli4_async_fcoe_evt(struct lpfc_hba *phba, break; case LPFC_FCOE_EVENT_TYPE_FCF_DEAD: - lpfc_printf_log(phba, KERN_ERR, LOG_DISCOVERY, + lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY, "2549 FCF disconnected from network index 0x%x" " tag 0x%x\n", acqe_fcoe->index, acqe_fcoe->event_tag); @@ -3349,21 +3375,32 @@ lpfc_sli4_async_fcoe_evt(struct lpfc_hba *phba, break; /* We request port to rediscover the entire FCF table for * a fast recovery from case that the current FCF record - * is no longer valid if the last CVL event hasn't already - * triggered process. + * is no longer valid if we are not in the middle of FCF + * failover process already. */ spin_lock_irq(&phba->hbalock); - if (phba->fcf.fcf_flag & FCF_CVL_FOVER) { + if (phba->fcf.fcf_flag & FCF_DISCOVERY) { spin_unlock_irq(&phba->hbalock); + /* Update FLOGI FCF failover eligible FCF bmask */ + lpfc_sli4_fcf_rr_index_clear(phba, acqe_fcoe->index); break; } /* Mark the fast failover process in progress */ - phba->fcf.fcf_flag |= FCF_DEAD_FOVER; + phba->fcf.fcf_flag |= FCF_DEAD_DISC; spin_unlock_irq(&phba->hbalock); + lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY, + "2771 Start FCF fast failover process due to " + "FCF DEAD event: evt_tag:x%x, fcf_index:x%x " + "\n", acqe_fcoe->event_tag, acqe_fcoe->index); rc = lpfc_sli4_redisc_fcf_table(phba); if (rc) { + lpfc_printf_log(phba, KERN_ERR, LOG_FIP | + LOG_DISCOVERY, + "2772 Issue FCF rediscover mabilbox " + "command failed, fail through to FCF " + "dead event\n"); spin_lock_irq(&phba->hbalock); - phba->fcf.fcf_flag &= ~FCF_DEAD_FOVER; + phba->fcf.fcf_flag &= ~FCF_DEAD_DISC; spin_unlock_irq(&phba->hbalock); /* * Last resort will fail over by treating this @@ -3378,7 +3415,7 @@ lpfc_sli4_async_fcoe_evt(struct lpfc_hba *phba, lpfc_sli4_perform_all_vport_cvl(phba); break; case LPFC_FCOE_EVENT_TYPE_CVL: - lpfc_printf_log(phba, KERN_ERR, LOG_DISCOVERY, + lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY, "2718 Clear Virtual Link Received for VPI 0x%x" " tag 0x%x\n", acqe_fcoe->index, acqe_fcoe->event_tag); vport = lpfc_find_vport_by_vpid(phba, @@ -3419,21 +3456,31 @@ lpfc_sli4_async_fcoe_evt(struct lpfc_hba *phba, * Otherwise, we request port to rediscover * the entire FCF table for a fast recovery * from possible case that the current FCF - * is no longer valid if the FCF_DEAD event - * hasn't already triggered process. + * is no longer valid if we are not already + * in the FCF failover process. */ spin_lock_irq(&phba->hbalock); - if (phba->fcf.fcf_flag & FCF_DEAD_FOVER) { + if (phba->fcf.fcf_flag & FCF_DISCOVERY) { spin_unlock_irq(&phba->hbalock); break; } /* Mark the fast failover process in progress */ - phba->fcf.fcf_flag |= FCF_CVL_FOVER; + phba->fcf.fcf_flag |= FCF_ACVL_DISC; spin_unlock_irq(&phba->hbalock); + lpfc_printf_log(phba, KERN_INFO, LOG_FIP | + LOG_DISCOVERY, + "2773 Start FCF fast failover due " + "to CVL event: evt_tag:x%x\n", + acqe_fcoe->event_tag); rc = lpfc_sli4_redisc_fcf_table(phba); if (rc) { + lpfc_printf_log(phba, KERN_ERR, LOG_FIP | + LOG_DISCOVERY, + "2774 Issue FCF rediscover " + "mabilbox command failed, " + "through to CVL event\n"); spin_lock_irq(&phba->hbalock); - phba->fcf.fcf_flag &= ~FCF_CVL_FOVER; + phba->fcf.fcf_flag &= ~FCF_ACVL_DISC; spin_unlock_irq(&phba->hbalock); /* * Last resort will be re-try on the @@ -3537,11 +3584,14 @@ void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *phba) spin_unlock_irq(&phba->hbalock); /* Scan FCF table from the first entry to re-discover SAN */ - rc = lpfc_sli4_read_fcf_record(phba, LPFC_FCOE_FCF_GET_FIRST); + lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY, + "2777 Start FCF table scan after FCF " + "rediscovery quiescent period over\n"); + rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST); if (rc) - lpfc_printf_log(phba, KERN_ERR, LOG_DISCOVERY, - "2747 Post FCF rediscovery read FCF record " - "failed 0x%x\n", rc); + lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY, + "2747 Issue FCF scan read FCF mailbox " + "command failed 0x%x\n", rc); } /** @@ -3833,6 +3883,7 @@ lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba) int rc, i, hbq_count, buf_size, dma_buf_size, max_buf_size; uint8_t pn_page[LPFC_MAX_SUPPORTED_PAGES] = {0}; struct lpfc_mqe *mqe; + int longs; /* Before proceed, wait for POST done and device ready */ rc = lpfc_sli4_post_status_check(phba); @@ -4009,13 +4060,24 @@ lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba) goto out_free_active_sgl; } + /* Allocate eligible FCF bmask memory for FCF round robin failover */ + longs = (LPFC_SLI4_FCF_TBL_INDX_MAX + BITS_PER_LONG - 1)/BITS_PER_LONG; + phba->fcf.fcf_rr_bmask = kzalloc(longs * sizeof(unsigned long), + GFP_KERNEL); + if (!phba->fcf.fcf_rr_bmask) { + lpfc_printf_log(phba, KERN_ERR, LOG_INIT, + "2759 Failed allocate memory for FCF round " + "robin failover bmask\n"); + goto out_remove_rpi_hdrs; + } + phba->sli4_hba.fcp_eq_hdl = kzalloc((sizeof(struct lpfc_fcp_eq_hdl) * phba->cfg_fcp_eq_count), GFP_KERNEL); if (!phba->sli4_hba.fcp_eq_hdl) { lpfc_printf_log(phba, KERN_ERR, LOG_INIT, "2572 Failed allocate memory for fast-path " "per-EQ handle array\n"); - goto out_remove_rpi_hdrs; + goto out_free_fcf_rr_bmask; } phba->sli4_hba.msix_entries = kzalloc((sizeof(struct msix_entry) * @@ -4068,6 +4130,8 @@ lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba) out_free_fcp_eq_hdl: kfree(phba->sli4_hba.fcp_eq_hdl); +out_free_fcf_rr_bmask: + kfree(phba->fcf.fcf_rr_bmask); out_remove_rpi_hdrs: lpfc_sli4_remove_rpi_hdrs(phba); out_free_active_sgl: @@ -4113,6 +4177,9 @@ lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba) lpfc_sli4_remove_rpi_hdrs(phba); lpfc_sli4_remove_rpis(phba); + /* Free eligible FCF index bmask */ + kfree(phba->fcf.fcf_rr_bmask); + /* Free the ELS sgl list */ lpfc_free_active_sgl(phba); lpfc_free_sgl_list(phba); diff --git a/drivers/scsi/lpfc/lpfc_logmsg.h b/drivers/scsi/lpfc/lpfc_logmsg.h index 954ba57970a3..bb59e9273126 100644 --- a/drivers/scsi/lpfc/lpfc_logmsg.h +++ b/drivers/scsi/lpfc/lpfc_logmsg.h @@ -35,6 +35,7 @@ #define LOG_VPORT 0x00004000 /* NPIV events */ #define LOF_SECURITY 0x00008000 /* Security events */ #define LOG_EVENT 0x00010000 /* CT,TEMP,DUMP, logging */ +#define LOG_FIP 0x00020000 /* FIP events */ #define LOG_ALL_MSG 0xffffffff /* LOG all messages */ #define lpfc_printf_vlog(vport, level, mask, fmt, arg...) \ diff --git a/drivers/scsi/lpfc/lpfc_mbox.c b/drivers/scsi/lpfc/lpfc_mbox.c index 6c4dce1a30ca..1e61ae3bc4eb 100644 --- a/drivers/scsi/lpfc/lpfc_mbox.c +++ b/drivers/scsi/lpfc/lpfc_mbox.c @@ -1748,7 +1748,7 @@ lpfc_sli4_mbox_opcode_get(struct lpfc_hba *phba, struct lpfcMboxq *mbox) } /** - * lpfc_sli4_mbx_read_fcf_record - Allocate and construct read fcf mbox cmd + * lpfc_sli4_mbx_read_fcf_rec - Allocate and construct read fcf mbox cmd * @phba: pointer to lpfc hba data structure. * @fcf_index: index to fcf table. * @@ -1759,9 +1759,9 @@ lpfc_sli4_mbox_opcode_get(struct lpfc_hba *phba, struct lpfcMboxq *mbox) * NULL. **/ int -lpfc_sli4_mbx_read_fcf_record(struct lpfc_hba *phba, - struct lpfcMboxq *mboxq, - uint16_t fcf_index) +lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *phba, + struct lpfcMboxq *mboxq, + uint16_t fcf_index) { void *virt_addr; dma_addr_t phys_addr; diff --git a/drivers/scsi/lpfc/lpfc_sli.c b/drivers/scsi/lpfc/lpfc_sli.c index bb6a4426d469..fe6660ca6452 100644 --- a/drivers/scsi/lpfc/lpfc_sli.c +++ b/drivers/scsi/lpfc/lpfc_sli.c @@ -11996,15 +11996,19 @@ lpfc_sli4_build_dflt_fcf_record(struct lpfc_hba *phba, } /** - * lpfc_sli4_read_fcf_record - Read the driver's default FCF Record. + * lpfc_sli4_fcf_scan_read_fcf_rec - Read hba fcf record for fcf scan. * @phba: pointer to lpfc hba data structure. * @fcf_index: FCF table entry offset. * - * This routine is invoked to read up to @fcf_num of FCF record from the - * device starting with the given @fcf_index. + * This routine is invoked to scan the entire FCF table by reading FCF + * record and processing it one at a time starting from the @fcf_index + * for initial FCF discovery or fast FCF failover rediscovery. + * + * Return 0 if the mailbox command is submitted sucessfully, none 0 + * otherwise. **/ int -lpfc_sli4_read_fcf_record(struct lpfc_hba *phba, uint16_t fcf_index) +lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *phba, uint16_t fcf_index) { int rc = 0, error; LPFC_MBOXQ_t *mboxq; @@ -12016,17 +12020,17 @@ lpfc_sli4_read_fcf_record(struct lpfc_hba *phba, uint16_t fcf_index) "2000 Failed to allocate mbox for " "READ_FCF cmd\n"); error = -ENOMEM; - goto fail_fcfscan; + goto fail_fcf_scan; } /* Construct the read FCF record mailbox command */ - rc = lpfc_sli4_mbx_read_fcf_record(phba, mboxq, fcf_index); + rc = lpfc_sli4_mbx_read_fcf_rec(phba, mboxq, fcf_index); if (rc) { error = -EINVAL; - goto fail_fcfscan; + goto fail_fcf_scan; } /* Issue the mailbox command asynchronously */ mboxq->vport = phba->pport; - mboxq->mbox_cmpl = lpfc_mbx_cmpl_read_fcf_record; + mboxq->mbox_cmpl = lpfc_mbx_cmpl_fcf_scan_read_fcf_rec; rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_NOWAIT); if (rc == MBX_NOT_FINISHED) error = -EIO; @@ -12034,9 +12038,13 @@ lpfc_sli4_read_fcf_record(struct lpfc_hba *phba, uint16_t fcf_index) spin_lock_irq(&phba->hbalock); phba->hba_flag |= FCF_DISC_INPROGRESS; spin_unlock_irq(&phba->hbalock); + /* Reset FCF round robin index bmask for new scan */ + if (fcf_index == LPFC_FCOE_FCF_GET_FIRST) + memset(phba->fcf.fcf_rr_bmask, 0, + sizeof(*phba->fcf.fcf_rr_bmask)); error = 0; } -fail_fcfscan: +fail_fcf_scan: if (error) { if (mboxq) lpfc_sli4_mbox_cmd_free(phba, mboxq); @@ -12048,6 +12056,181 @@ fail_fcfscan: return error; } +/** + * lpfc_sli4_fcf_rr_read_fcf_rec - Read hba fcf record for round robin fcf. + * @phba: pointer to lpfc hba data structure. + * @fcf_index: FCF table entry offset. + * + * This routine is invoked to read an FCF record indicated by @fcf_index + * and to use it for FLOGI round robin FCF failover. + * + * Return 0 if the mailbox command is submitted sucessfully, none 0 + * otherwise. + **/ +int +lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *phba, uint16_t fcf_index) +{ + int rc = 0, error; + LPFC_MBOXQ_t *mboxq; + + mboxq = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL); + if (!mboxq) { + lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_INIT, + "2763 Failed to allocate mbox for " + "READ_FCF cmd\n"); + error = -ENOMEM; + goto fail_fcf_read; + } + /* Construct the read FCF record mailbox command */ + rc = lpfc_sli4_mbx_read_fcf_rec(phba, mboxq, fcf_index); + if (rc) { + error = -EINVAL; + goto fail_fcf_read; + } + /* Issue the mailbox command asynchronously */ + mboxq->vport = phba->pport; + mboxq->mbox_cmpl = lpfc_mbx_cmpl_fcf_rr_read_fcf_rec; + rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_NOWAIT); + if (rc == MBX_NOT_FINISHED) + error = -EIO; + else + error = 0; + +fail_fcf_read: + if (error && mboxq) + lpfc_sli4_mbox_cmd_free(phba, mboxq); + return error; +} + +/** + * lpfc_sli4_read_fcf_rec - Read hba fcf record for update eligible fcf bmask. + * @phba: pointer to lpfc hba data structure. + * @fcf_index: FCF table entry offset. + * + * This routine is invoked to read an FCF record indicated by @fcf_index to + * determine whether it's eligible for FLOGI round robin failover list. + * + * Return 0 if the mailbox command is submitted sucessfully, none 0 + * otherwise. + **/ +int +lpfc_sli4_read_fcf_rec(struct lpfc_hba *phba, uint16_t fcf_index) +{ + int rc = 0, error; + LPFC_MBOXQ_t *mboxq; + + mboxq = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL); + if (!mboxq) { + lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_INIT, + "2758 Failed to allocate mbox for " + "READ_FCF cmd\n"); + error = -ENOMEM; + goto fail_fcf_read; + } + /* Construct the read FCF record mailbox command */ + rc = lpfc_sli4_mbx_read_fcf_rec(phba, mboxq, fcf_index); + if (rc) { + error = -EINVAL; + goto fail_fcf_read; + } + /* Issue the mailbox command asynchronously */ + mboxq->vport = phba->pport; + mboxq->mbox_cmpl = lpfc_mbx_cmpl_read_fcf_rec; + rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_NOWAIT); + if (rc == MBX_NOT_FINISHED) + error = -EIO; + else + error = 0; + +fail_fcf_read: + if (error && mboxq) + lpfc_sli4_mbox_cmd_free(phba, mboxq); + return error; +} + +/** + * lpfc_sli4_fcf_rr_next_index_get - Get next eligible fcf record index + * @phba: pointer to lpfc hba data structure. + * + * This routine is to get the next eligible FCF record index in a round + * robin fashion. If the next eligible FCF record index equals to the + * initial round robin FCF record index, LPFC_FCOE_FCF_NEXT_NONE (0xFFFF) + * shall be returned, otherwise, the next eligible FCF record's index + * shall be returned. + **/ +uint16_t +lpfc_sli4_fcf_rr_next_index_get(struct lpfc_hba *phba) +{ + uint16_t next_fcf_index; + + /* Search from the currently registered FCF index */ + next_fcf_index = find_next_bit(phba->fcf.fcf_rr_bmask, + LPFC_SLI4_FCF_TBL_INDX_MAX, + phba->fcf.current_rec.fcf_indx); + /* Wrap around condition on phba->fcf.fcf_rr_bmask */ + if (next_fcf_index >= LPFC_SLI4_FCF_TBL_INDX_MAX) + next_fcf_index = find_next_bit(phba->fcf.fcf_rr_bmask, + LPFC_SLI4_FCF_TBL_INDX_MAX, 0); + /* Round robin failover stop condition */ + if (next_fcf_index == phba->fcf.fcf_rr_init_indx) + return LPFC_FCOE_FCF_NEXT_NONE; + + return next_fcf_index; +} + +/** + * lpfc_sli4_fcf_rr_index_set - Set bmask with eligible fcf record index + * @phba: pointer to lpfc hba data structure. + * + * This routine sets the FCF record index in to the eligible bmask for + * round robin failover search. It checks to make sure that the index + * does not go beyond the range of the driver allocated bmask dimension + * before setting the bit. + * + * Returns 0 if the index bit successfully set, otherwise, it returns + * -EINVAL. + **/ +int +lpfc_sli4_fcf_rr_index_set(struct lpfc_hba *phba, uint16_t fcf_index) +{ + if (fcf_index >= LPFC_SLI4_FCF_TBL_INDX_MAX) { + lpfc_printf_log(phba, KERN_ERR, LOG_FIP, + "2610 HBA FCF index reached driver's " + "book keeping dimension: fcf_index:%d, " + "driver_bmask_max:%d\n", + fcf_index, LPFC_SLI4_FCF_TBL_INDX_MAX); + return -EINVAL; + } + /* Set the eligible FCF record index bmask */ + set_bit(fcf_index, phba->fcf.fcf_rr_bmask); + + return 0; +} + +/** + * lpfc_sli4_fcf_rr_index_set - Clear bmask from eligible fcf record index + * @phba: pointer to lpfc hba data structure. + * + * This routine clears the FCF record index from the eligible bmask for + * round robin failover search. It checks to make sure that the index + * does not go beyond the range of the driver allocated bmask dimension + * before clearing the bit. + **/ +void +lpfc_sli4_fcf_rr_index_clear(struct lpfc_hba *phba, uint16_t fcf_index) +{ + if (fcf_index >= LPFC_SLI4_FCF_TBL_INDX_MAX) { + lpfc_printf_log(phba, KERN_ERR, LOG_FIP, + "2762 HBA FCF index goes beyond driver's " + "book keeping dimension: fcf_index:%d, " + "driver_bmask_max:%d\n", + fcf_index, LPFC_SLI4_FCF_TBL_INDX_MAX); + return; + } + /* Clear the eligible FCF record index bmask */ + clear_bit(fcf_index, phba->fcf.fcf_rr_bmask); +} + /** * lpfc_mbx_cmpl_redisc_fcf_table - completion routine for rediscover FCF table * @phba: pointer to lpfc hba data structure. @@ -12069,13 +12252,13 @@ lpfc_mbx_cmpl_redisc_fcf_table(struct lpfc_hba *phba, LPFC_MBOXQ_t *mbox) shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &redisc_fcf->header.cfg_shdr.response); if (shdr_status || shdr_add_status) { - lpfc_printf_log(phba, KERN_ERR, LOG_SLI, + lpfc_printf_log(phba, KERN_ERR, LOG_FIP, "2746 Requesting for FCF rediscovery failed " "status x%x add_status x%x\n", shdr_status, shdr_add_status); - if (phba->fcf.fcf_flag & FCF_CVL_FOVER) { + if (phba->fcf.fcf_flag & FCF_ACVL_DISC) { spin_lock_irq(&phba->hbalock); - phba->fcf.fcf_flag &= ~FCF_CVL_FOVER; + phba->fcf.fcf_flag &= ~FCF_ACVL_DISC; spin_unlock_irq(&phba->hbalock); /* * CVL event triggered FCF rediscover request failed, @@ -12084,7 +12267,7 @@ lpfc_mbx_cmpl_redisc_fcf_table(struct lpfc_hba *phba, LPFC_MBOXQ_t *mbox) lpfc_retry_pport_discovery(phba); } else { spin_lock_irq(&phba->hbalock); - phba->fcf.fcf_flag &= ~FCF_DEAD_FOVER; + phba->fcf.fcf_flag &= ~FCF_DEAD_DISC; spin_unlock_irq(&phba->hbalock); /* * DEAD FCF event triggered FCF rediscover request @@ -12093,12 +12276,16 @@ lpfc_mbx_cmpl_redisc_fcf_table(struct lpfc_hba *phba, LPFC_MBOXQ_t *mbox) */ lpfc_sli4_fcf_dead_failthrough(phba); } - } else + } else { + lpfc_printf_log(phba, KERN_INFO, LOG_FIP, + "2775 Start FCF rediscovery quiescent period " + "wait timer before scaning FCF table\n"); /* * Start FCF rediscovery wait timer for pending FCF * before rescan FCF record table. */ lpfc_fcf_redisc_wait_start_timer(phba); + } mempool_free(mbox, phba->mbox_mem_pool); } @@ -12117,6 +12304,9 @@ lpfc_sli4_redisc_fcf_table(struct lpfc_hba *phba) struct lpfc_mbx_redisc_fcf_tbl *redisc_fcf; int rc, length; + /* Cancel retry delay timers to all vports before FCF rediscover */ + lpfc_cancel_all_vport_retry_delay_timer(phba); + mbox = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL); if (!mbox) { lpfc_printf_log(phba, KERN_ERR, LOG_SLI, diff --git a/drivers/scsi/lpfc/lpfc_sli4.h b/drivers/scsi/lpfc/lpfc_sli4.h index 2169cd24d90c..4a35e7b9bc5b 100644 --- a/drivers/scsi/lpfc/lpfc_sli4.h +++ b/drivers/scsi/lpfc/lpfc_sli4.h @@ -153,17 +153,27 @@ struct lpfc_fcf { #define FCF_REGISTERED 0x02 /* FCF registered with FW */ #define FCF_SCAN_DONE 0x04 /* FCF table scan done */ #define FCF_IN_USE 0x08 /* Atleast one discovery completed */ -#define FCF_DEAD_FOVER 0x10 /* FCF DEAD triggered fast FCF failover */ -#define FCF_CVL_FOVER 0x20 /* CVL triggered fast FCF failover */ -#define FCF_REDISC_PEND 0x40 /* FCF rediscovery pending */ -#define FCF_REDISC_EVT 0x80 /* FCF rediscovery event to worker thread */ -#define FCF_REDISC_FOV 0x100 /* Post FCF rediscovery fast failover */ +#define FCF_INIT_DISC 0x10 /* Initial FCF discovery */ +#define FCF_DEAD_DISC 0x20 /* FCF DEAD fast FCF failover discovery */ +#define FCF_ACVL_DISC 0x40 /* All CVL fast FCF failover discovery */ +#define FCF_DISCOVERY (FCF_INIT_DISC | FCF_DEAD_DISC | FCF_ACVL_DISC) +#define FCF_REDISC_PEND 0x80 /* FCF rediscovery pending */ +#define FCF_REDISC_EVT 0x100 /* FCF rediscovery event to worker thread */ +#define FCF_REDISC_FOV 0x200 /* Post FCF rediscovery fast failover */ uint32_t addr_mode; + uint16_t fcf_rr_init_indx; struct lpfc_fcf_rec current_rec; struct lpfc_fcf_rec failover_rec; struct timer_list redisc_wait; + unsigned long *fcf_rr_bmask; /* Eligible FCF indexes for RR failover */ }; +/* + * Maximum FCF table index, it is for driver internal book keeping, it + * just needs to be no less than the supported HBA's FCF table size. + */ +#define LPFC_SLI4_FCF_TBL_INDX_MAX 32 + #define LPFC_REGION23_SIGNATURE "RG23" #define LPFC_REGION23_VERSION 1 #define LPFC_REGION23_LAST_REC 0xff @@ -472,8 +482,8 @@ void lpfc_sli4_mbox_cmd_free(struct lpfc_hba *, struct lpfcMboxq *); void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t); void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t, struct lpfc_mbx_sge *); -int lpfc_sli4_mbx_read_fcf_record(struct lpfc_hba *, struct lpfcMboxq *, - uint16_t); +int lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *, struct lpfcMboxq *, + uint16_t); void lpfc_sli4_hba_reset(struct lpfc_hba *); struct lpfc_queue *lpfc_sli4_queue_alloc(struct lpfc_hba *, uint32_t, @@ -532,8 +542,13 @@ int lpfc_sli4_init_vpi(struct lpfc_hba *, uint16_t); uint32_t lpfc_sli4_cq_release(struct lpfc_queue *, bool); uint32_t lpfc_sli4_eq_release(struct lpfc_queue *, bool); void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t); -int lpfc_sli4_read_fcf_record(struct lpfc_hba *, uint16_t); -void lpfc_mbx_cmpl_read_fcf_record(struct lpfc_hba *, LPFC_MBOXQ_t *); +int lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *, uint16_t); +int lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *, uint16_t); +int lpfc_sli4_read_fcf_rec(struct lpfc_hba *, uint16_t); +void lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *); +void lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *); +void lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *); +int lpfc_sli4_unregister_fcf(struct lpfc_hba *); int lpfc_sli4_post_status_check(struct lpfc_hba *); uint8_t lpfc_sli4_mbox_opcode_get(struct lpfc_hba *, struct lpfcMboxq *); -- cgit v1.2.3 From 74315ad00b8ed41e9f97fe322942fa9883517ed1 Mon Sep 17 00:00:00 2001 From: James Smart Date: Fri, 26 Feb 2010 14:16:25 -0500 Subject: [SCSI] lpfc 8.3.10: Update Driver version to 8.3.10 Signed-off-by: James Smart Signed-off-by: James Bottomley --- drivers/scsi/lpfc/lpfc_version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/scsi/lpfc/lpfc_version.h b/drivers/scsi/lpfc/lpfc_version.h index ac276aa46fba..013deec5dae8 100644 --- a/drivers/scsi/lpfc/lpfc_version.h +++ b/drivers/scsi/lpfc/lpfc_version.h @@ -18,7 +18,7 @@ * included with this package. * *******************************************************************/ -#define LPFC_DRIVER_VERSION "8.3.9" +#define LPFC_DRIVER_VERSION "8.3.10" #define LPFC_DRIVER_NAME "lpfc" #define LPFC_SP_DRIVER_HANDLER_NAME "lpfc:sp" #define LPFC_FP_DRIVER_HANDLER_NAME "lpfc:fp" -- cgit v1.2.3 From bb2d3de1885cd69a5fc92af99c4e0c05eb5fc122 Mon Sep 17 00:00:00 2001 From: "Martin K. Petersen" Date: Tue, 2 Mar 2010 08:44:34 -0500 Subject: [SCSI] sd: Fix VPD buffer allocations Commit e3deec09 incorrectly assumed that the B0 and B1 page lengths were limited to 32 bytes. The B0 VPD page length is defined to be 64 bytes when the device supports thin provisioning. B1 is always defined to be 64 bytes. Signed-off-by: Martin K. Petersen Reported-by: Dan Carpenter Signed-off-by: James Bottomley --- drivers/scsi/sd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c index 1dd4d8407694..f9995388a574 100644 --- a/drivers/scsi/sd.c +++ b/drivers/scsi/sd.c @@ -1948,7 +1948,7 @@ static void sd_read_block_limits(struct scsi_disk *sdkp) { struct request_queue *q = sdkp->disk->queue; unsigned int sector_sz = sdkp->device->sector_size; - const int vpd_len = 32; + const int vpd_len = 64; unsigned char *buffer = kmalloc(vpd_len, GFP_KERNEL); if (!buffer || @@ -1998,7 +1998,7 @@ static void sd_read_block_characteristics(struct scsi_disk *sdkp) { unsigned char *buffer; u16 rot; - const int vpd_len = 32; + const int vpd_len = 64; buffer = kmalloc(vpd_len, GFP_KERNEL); -- cgit v1.2.3 From 1bd588fd9d2611d2573066f49477fb5be2aa13de Mon Sep 17 00:00:00 2001 From: Alberto Panizzo Date: Mon, 14 Dec 2009 18:26:38 +0100 Subject: regulator: add voltage selection capability to mc13783 regulators v2 . This patch, complete the mc13783 regulator subsystem driver with voltage selecting capability. Main Switches (SW1AB, SW2AB) are not supported yet. version 2 diffs: - delete the "Switchers PLL" enable and multiplication factor value selecting capability because it is not a voltage or current regulator. This will be a part of Main switcher supporting task. - Correct many coding style problems pointed me out. Signed-off-by: Alberto Panizzo Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/mc13783-regulator.c | 345 +++++++++++++++++++++++++++++++--- 1 file changed, 315 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/mc13783-regulator.c b/drivers/regulator/mc13783-regulator.c index 39c495300045..a40e35ab8555 100644 --- a/drivers/regulator/mc13783-regulator.c +++ b/drivers/regulator/mc13783-regulator.c @@ -2,6 +2,7 @@ * Regulator Driver for Freescale MC13783 PMIC * * Copyright (C) 2008 Sascha Hauer, Pengutronix + * Copyright 2009 Alberto Panizzo * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -16,11 +17,44 @@ #include #include -#define MC13783_REG_SWITCHERS4 28 -#define MC13783_REG_SWITCHERS4_PLLEN (1 << 18) - #define MC13783_REG_SWITCHERS5 29 #define MC13783_REG_SWITCHERS5_SW3EN (1 << 20) +#define MC13783_REG_SWITCHERS5_SW3VSEL 18 +#define MC13783_REG_SWITCHERS5_SW3VSEL_M (3 << 18) + +#define MC13783_REG_REGULATORSETTING0 30 +#define MC13783_REG_REGULATORSETTING0_VIOLOVSEL 2 +#define MC13783_REG_REGULATORSETTING0_VDIGVSEL 4 +#define MC13783_REG_REGULATORSETTING0_VGENVSEL 6 +#define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL 9 +#define MC13783_REG_REGULATORSETTING0_VRFREFVSEL 11 +#define MC13783_REG_REGULATORSETTING0_VRFCPVSEL 13 +#define MC13783_REG_REGULATORSETTING0_VSIMVSEL 14 +#define MC13783_REG_REGULATORSETTING0_VESIMVSEL 15 +#define MC13783_REG_REGULATORSETTING0_VCAMVSEL 16 + +#define MC13783_REG_REGULATORSETTING0_VIOLOVSEL_M (3 << 2) +#define MC13783_REG_REGULATORSETTING0_VDIGVSEL_M (3 << 4) +#define MC13783_REG_REGULATORSETTING0_VGENVSEL_M (7 << 6) +#define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL_M (3 << 9) +#define MC13783_REG_REGULATORSETTING0_VRFREFVSEL_M (3 << 11) +#define MC13783_REG_REGULATORSETTING0_VRFCPVSEL_M (1 << 13) +#define MC13783_REG_REGULATORSETTING0_VSIMVSEL_M (1 << 14) +#define MC13783_REG_REGULATORSETTING0_VESIMVSEL_M (1 << 15) +#define MC13783_REG_REGULATORSETTING0_VCAMVSEL_M (7 << 16) + +#define MC13783_REG_REGULATORSETTING1 31 +#define MC13783_REG_REGULATORSETTING1_VVIBVSEL 0 +#define MC13783_REG_REGULATORSETTING1_VRF1VSEL 2 +#define MC13783_REG_REGULATORSETTING1_VRF2VSEL 4 +#define MC13783_REG_REGULATORSETTING1_VMMC1VSEL 6 +#define MC13783_REG_REGULATORSETTING1_VMMC2VSEL 9 + +#define MC13783_REG_REGULATORSETTING1_VVIBVSEL_M (3 << 0) +#define MC13783_REG_REGULATORSETTING1_VRF1VSEL_M (3 << 2) +#define MC13783_REG_REGULATORSETTING1_VRF2VSEL_M (3 << 4) +#define MC13783_REG_REGULATORSETTING1_VMMC1VSEL_M (7 << 6) +#define MC13783_REG_REGULATORSETTING1_VMMC2VSEL_M (7 << 9) #define MC13783_REG_REGULATORMODE0 32 #define MC13783_REG_REGULATORMODE0_VAUDIOEN (1 << 0) @@ -53,14 +87,88 @@ struct mc13783_regulator { struct regulator_desc desc; int reg; int enable_bit; + int vsel_reg; + int vsel_shift; + int vsel_mask; + int const *voltages; +}; + +/* Voltage Values */ +static const int const mc13783_sw3_val[] = { + 5000000, 5000000, 5000000, 5500000, +}; + +static const int const mc13783_vaudio_val[] = { + 2775000, +}; + +static const int const mc13783_viohi_val[] = { + 2775000, +}; + +static const int const mc13783_violo_val[] = { + 1200000, 1300000, 1500000, 1800000, +}; + +static const int const mc13783_vdig_val[] = { + 1200000, 1300000, 1500000, 1800000, +}; + +static const int const mc13783_vgen_val[] = { + 1200000, 1300000, 1500000, 1800000, + 1100000, 2000000, 2775000, 2400000, +}; + +static const int const mc13783_vrfdig_val[] = { + 1200000, 1500000, 1800000, 1875000, +}; + +static const int const mc13783_vrfref_val[] = { + 2475000, 2600000, 2700000, 2775000, +}; + +static const int const mc13783_vrfcp_val[] = { + 2700000, 2775000, +}; + +static const int const mc13783_vsim_val[] = { + 1800000, 2900000, 3000000, +}; + +static const int const mc13783_vesim_val[] = { + 1800000, 2900000, +}; + +static const int const mc13783_vcam_val[] = { + 1500000, 1800000, 2500000, 2550000, + 2600000, 2750000, 2800000, 3000000, +}; + +static const int const mc13783_vrfbg_val[] = { + 1250000, +}; + +static const int const mc13783_vvib_val[] = { + 1300000, 1800000, 2000000, 3000000, +}; + +static const int const mc13783_vmmc_val[] = { + 1600000, 1800000, 2000000, 2600000, + 2700000, 2800000, 2900000, 3000000, +}; + +static const int const mc13783_vrf_val[] = { + 1500000, 1875000, 2700000, 2775000, }; static struct regulator_ops mc13783_regulator_ops; +static struct regulator_ops mc13783_fixed_regulator_ops; -#define MC13783_DEFINE(prefix, _name, _reg) \ +#define MC13783_DEFINE(prefix, _name, _reg, _vsel_reg, _voltages) \ [MC13783_ ## prefix ## _ ## _name] = { \ .desc = { \ .name = #prefix "_" #_name, \ + .n_voltages = ARRAY_SIZE(_voltages), \ .ops = &mc13783_regulator_ops, \ .type = REGULATOR_VOLTAGE, \ .id = MC13783_ ## prefix ## _ ## _name, \ @@ -68,36 +176,83 @@ static struct regulator_ops mc13783_regulator_ops; }, \ .reg = MC13783_REG_ ## _reg, \ .enable_bit = MC13783_REG_ ## _reg ## _ ## _name ## EN, \ + .vsel_reg = MC13783_REG_ ## _vsel_reg, \ + .vsel_shift = MC13783_REG_ ## _vsel_reg ## _ ## _name ## VSEL,\ + .vsel_mask = MC13783_REG_ ## _vsel_reg ## _ ## _name ## VSEL_M,\ + .voltages = _voltages, \ } -#define MC13783_DEFINE_SW(_name, _reg) MC13783_DEFINE(SW, _name, _reg) -#define MC13783_DEFINE_REGU(_name, _reg) MC13783_DEFINE(REGU, _name, _reg) +#define MC13783_FIXED_DEFINE(prefix, _name, _reg, _voltages) \ + [MC13783_ ## prefix ## _ ## _name] = { \ + .desc = { \ + .name = #prefix "_" #_name, \ + .n_voltages = ARRAY_SIZE(_voltages), \ + .ops = &mc13783_fixed_regulator_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MC13783_ ## prefix ## _ ## _name, \ + .owner = THIS_MODULE, \ + }, \ + .reg = MC13783_REG_ ## _reg, \ + .enable_bit = MC13783_REG_ ## _reg ## _ ## _name ## EN, \ + .voltages = _voltages, \ + } + +#define MC13783_GPO_DEFINE(prefix, _name, _reg) \ + [MC13783_ ## prefix ## _ ## _name] = { \ + .desc = { \ + .name = #prefix "_" #_name, \ + .ops = &mc13783_regulator_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MC13783_ ## prefix ## _ ## _name, \ + .owner = THIS_MODULE, \ + }, \ + .reg = MC13783_REG_ ## _reg, \ + .enable_bit = MC13783_REG_ ## _reg ## _ ## _name ## EN, \ + } + +#define MC13783_DEFINE_SW(_name, _reg, _vsel_reg, _voltages) \ + MC13783_DEFINE(SW, _name, _reg, _vsel_reg, _voltages) +#define MC13783_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages) \ + MC13783_DEFINE(REGU, _name, _reg, _vsel_reg, _voltages) static struct mc13783_regulator mc13783_regulators[] = { - MC13783_DEFINE_SW(SW3, SWITCHERS5), - MC13783_DEFINE_SW(PLL, SWITCHERS4), - - MC13783_DEFINE_REGU(VAUDIO, REGULATORMODE0), - MC13783_DEFINE_REGU(VIOHI, REGULATORMODE0), - MC13783_DEFINE_REGU(VIOLO, REGULATORMODE0), - MC13783_DEFINE_REGU(VDIG, REGULATORMODE0), - MC13783_DEFINE_REGU(VGEN, REGULATORMODE0), - MC13783_DEFINE_REGU(VRFDIG, REGULATORMODE0), - MC13783_DEFINE_REGU(VRFREF, REGULATORMODE0), - MC13783_DEFINE_REGU(VRFCP, REGULATORMODE0), - MC13783_DEFINE_REGU(VSIM, REGULATORMODE1), - MC13783_DEFINE_REGU(VESIM, REGULATORMODE1), - MC13783_DEFINE_REGU(VCAM, REGULATORMODE1), - MC13783_DEFINE_REGU(VRFBG, REGULATORMODE1), - MC13783_DEFINE_REGU(VVIB, REGULATORMODE1), - MC13783_DEFINE_REGU(VRF1, REGULATORMODE1), - MC13783_DEFINE_REGU(VRF2, REGULATORMODE1), - MC13783_DEFINE_REGU(VMMC1, REGULATORMODE1), - MC13783_DEFINE_REGU(VMMC2, REGULATORMODE1), - MC13783_DEFINE_REGU(GPO1, POWERMISC), - MC13783_DEFINE_REGU(GPO2, POWERMISC), - MC13783_DEFINE_REGU(GPO3, POWERMISC), - MC13783_DEFINE_REGU(GPO4, POWERMISC), + MC13783_DEFINE_SW(SW3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val), + + MC13783_FIXED_DEFINE(REGU, VAUDIO, REGULATORMODE0, mc13783_vaudio_val), + MC13783_FIXED_DEFINE(REGU, VIOHI, REGULATORMODE0, mc13783_viohi_val), + MC13783_DEFINE_REGU(VIOLO, REGULATORMODE0, REGULATORSETTING0, \ + mc13783_violo_val), + MC13783_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0, \ + mc13783_vdig_val), + MC13783_DEFINE_REGU(VGEN, REGULATORMODE0, REGULATORSETTING0, \ + mc13783_vgen_val), + MC13783_DEFINE_REGU(VRFDIG, REGULATORMODE0, REGULATORSETTING0, \ + mc13783_vrfdig_val), + MC13783_DEFINE_REGU(VRFREF, REGULATORMODE0, REGULATORSETTING0, \ + mc13783_vrfref_val), + MC13783_DEFINE_REGU(VRFCP, REGULATORMODE0, REGULATORSETTING0, \ + mc13783_vrfcp_val), + MC13783_DEFINE_REGU(VSIM, REGULATORMODE1, REGULATORSETTING0, \ + mc13783_vsim_val), + MC13783_DEFINE_REGU(VESIM, REGULATORMODE1, REGULATORSETTING0, \ + mc13783_vesim_val), + MC13783_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0, \ + mc13783_vcam_val), + MC13783_FIXED_DEFINE(REGU, VRFBG, REGULATORMODE1, mc13783_vrfbg_val), + MC13783_DEFINE_REGU(VVIB, REGULATORMODE1, REGULATORSETTING1, \ + mc13783_vvib_val), + MC13783_DEFINE_REGU(VRF1, REGULATORMODE1, REGULATORSETTING1, \ + mc13783_vrf_val), + MC13783_DEFINE_REGU(VRF2, REGULATORMODE1, REGULATORSETTING1, \ + mc13783_vrf_val), + MC13783_DEFINE_REGU(VMMC1, REGULATORMODE1, REGULATORSETTING1, \ + mc13783_vmmc_val), + MC13783_DEFINE_REGU(VMMC2, REGULATORMODE1, REGULATORSETTING1, \ + mc13783_vmmc_val), + MC13783_GPO_DEFINE(REGU, GPO1, POWERMISC), + MC13783_GPO_DEFINE(REGU, GPO2, POWERMISC), + MC13783_GPO_DEFINE(REGU, GPO3, POWERMISC), + MC13783_GPO_DEFINE(REGU, GPO4, POWERMISC), }; struct mc13783_regulator_priv { @@ -154,10 +309,140 @@ static int mc13783_regulator_is_enabled(struct regulator_dev *rdev) return (val & mc13783_regulators[id].enable_bit) != 0; } +static int mc13783_regulator_list_voltage(struct regulator_dev *rdev, + unsigned selector) +{ + int id = rdev_get_id(rdev); + + if (selector >= mc13783_regulators[id].desc.n_voltages) + return -EINVAL; + + return mc13783_regulators[id].voltages[selector]; +} + +static int mc13783_get_best_voltage_index(struct regulator_dev *rdev, + int min_uV, int max_uV) +{ + int reg_id = rdev_get_id(rdev); + int i; + int bestmatch; + int bestindex; + + /* + * Locate the minimum voltage fitting the criteria on + * this regulator. The switchable voltages are not + * in strict falling order so we need to check them + * all for the best match. + */ + bestmatch = INT_MAX; + bestindex = -1; + for (i = 0; i < mc13783_regulators[reg_id].desc.n_voltages; i++) { + if (mc13783_regulators[reg_id].voltages[i] >= min_uV && + mc13783_regulators[reg_id].voltages[i] < bestmatch) { + bestmatch = mc13783_regulators[reg_id].voltages[i]; + bestindex = i; + } + } + + if (bestindex < 0 || bestmatch > max_uV) { + dev_warn(&rdev->dev, "no possible value for %d<=x<=%d uV\n", + min_uV, max_uV); + return -EINVAL; + } + return bestindex; +} + +static int mc13783_regulator_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV) +{ + struct mc13783_regulator_priv *priv = rdev_get_drvdata(rdev); + int value, id = rdev_get_id(rdev); + int ret; + + dev_dbg(rdev_get_dev(rdev), "%s id: %d min_uV: %d max_uV: %d\n", + __func__, id, min_uV, max_uV); + + /* Find the best index */ + value = mc13783_get_best_voltage_index(rdev, min_uV, max_uV); + dev_dbg(rdev_get_dev(rdev), "%s best value: %d \n", __func__, value); + if (value < 0) + return value; + + mc13783_lock(priv->mc13783); + ret = mc13783_reg_rmw(priv->mc13783, mc13783_regulators[id].vsel_reg, + mc13783_regulators[id].vsel_mask, + value << mc13783_regulators[id].vsel_shift); + mc13783_unlock(priv->mc13783); + + return ret; +} + +static int mc13783_regulator_get_voltage(struct regulator_dev *rdev) +{ + struct mc13783_regulator_priv *priv = rdev_get_drvdata(rdev); + int ret, id = rdev_get_id(rdev); + unsigned int val; + + dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); + + mc13783_lock(priv->mc13783); + ret = mc13783_reg_read(priv->mc13783, + mc13783_regulators[id].vsel_reg, &val); + mc13783_unlock(priv->mc13783); + + if (ret) + return ret; + + val = (val & mc13783_regulators[id].vsel_mask) + >> mc13783_regulators[id].vsel_shift; + + dev_dbg(rdev_get_dev(rdev), "%s id: %d val: %d\n", __func__, id, val); + + BUG_ON(val < 0 || val > mc13783_regulators[id].desc.n_voltages); + + return mc13783_regulators[id].voltages[val]; +} + static struct regulator_ops mc13783_regulator_ops = { .enable = mc13783_regulator_enable, .disable = mc13783_regulator_disable, .is_enabled = mc13783_regulator_is_enabled, + .list_voltage = mc13783_regulator_list_voltage, + .set_voltage = mc13783_regulator_set_voltage, + .get_voltage = mc13783_regulator_get_voltage, +}; + +static int mc13783_fixed_regulator_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV) +{ + int id = rdev_get_id(rdev); + + dev_dbg(rdev_get_dev(rdev), "%s id: %d min_uV: %d max_uV: %d\n", + __func__, id, min_uV, max_uV); + + if (min_uV > mc13783_regulators[id].voltages[0] && + max_uV < mc13783_regulators[id].voltages[0]) + return 0; + else + return -EINVAL; +} + +static int mc13783_fixed_regulator_get_voltage(struct regulator_dev *rdev) +{ + int id = rdev_get_id(rdev); + + dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); + + return mc13783_regulators[id].voltages[0]; +} + +static struct regulator_ops mc13783_fixed_regulator_ops = { + .enable = mc13783_regulator_enable, + .disable = mc13783_regulator_disable, + .is_enabled = mc13783_regulator_is_enabled, + .list_voltage = mc13783_regulator_list_voltage, + .set_voltage = mc13783_fixed_regulator_set_voltage, + .get_voltage = mc13783_fixed_regulator_get_voltage, }; static int __devinit mc13783_regulator_probe(struct platform_device *pdev) -- cgit v1.2.3 From 6faa7e0a4bb1215fb0a0093a0d426a72599e5982 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Wed, 23 Dec 2009 14:13:17 +0100 Subject: regulator/lp3971: Storage class should be before const qualifier The C99 specification states in section 6.11.5: The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature. Signed-off-by: Tobias Klauser Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/lp3971.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/lp3971.c b/drivers/regulator/lp3971.c index 4f33a0f4a179..3ea639f29e95 100644 --- a/drivers/regulator/lp3971.c +++ b/drivers/regulator/lp3971.c @@ -54,7 +54,7 @@ static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val); #define LP3971_BUCK2_BASE 0x29 #define LP3971_BUCK3_BASE 0x32 -const static int buck_base_addr[] = { +static const int buck_base_addr[] = { LP3971_BUCK1_BASE, LP3971_BUCK2_BASE, LP3971_BUCK3_BASE, @@ -63,7 +63,7 @@ const static int buck_base_addr[] = { #define LP3971_BUCK_TARGET_VOL1_REG(x) (buck_base_addr[x]) #define LP3971_BUCK_TARGET_VOL2_REG(x) (buck_base_addr[x]+1) -const static int buck_voltage_map[] = { +static const int buck_voltage_map[] = { 0, 800, 850, 900, 950, 1000, 1050, 1100, 1150, 1200, 1250, 1300, 1350, 1400, 1450, 1500, 1550, 1600, 1650, 1700, 1800, 1900, 2500, 2800, @@ -96,17 +96,17 @@ const static int buck_voltage_map[] = { #define LDO_VOL_CONTR_SHIFT(x) ((x & 1) << 2) #define LDO_VOL_CONTR_MASK 0x0f -const static int ldo45_voltage_map[] = { +static const int ldo45_voltage_map[] = { 1000, 1050, 1100, 1150, 1200, 1250, 1300, 1350, 1400, 1500, 1800, 1900, 2500, 2800, 3000, 3300, }; -const static int ldo123_voltage_map[] = { +static const int ldo123_voltage_map[] = { 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, 3200, 3300, }; -const static int *ldo_voltage_map[] = { +static const int *ldo_voltage_map[] = { ldo123_voltage_map, /* LDO1 */ ldo123_voltage_map, /* LDO2 */ ldo123_voltage_map, /* LDO3 */ -- cgit v1.2.3 From 84b6826306119dc3c41ef9d7ed6c408112f63301 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 1 Dec 2009 21:12:27 +0000 Subject: regulator: Add notifier event on regulator disable The intended use case is for drivers which disable regulators to save power but need to do some work to restore the hardware state when restarting. If the supplies are not actually disabled due to board limits or sharing with other active devices this notifier allows the driver to avoid unneeded reinitialisation, particularly when used with runtime PM. Signed-off-by: Mark Brown --- drivers/regulator/core.c | 7 +++++-- include/linux/regulator/consumer.h | 4 +++- 2 files changed, 8 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index b60a4c9f8f16..6d2ce8a05331 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -1341,6 +1341,9 @@ static int _regulator_disable(struct regulator_dev *rdev) __func__, rdev_get_name(rdev)); return ret; } + + _notifier_call_chain(rdev, REGULATOR_EVENT_DISABLE, + NULL); } /* decrease our supplies ref count and disable if required */ @@ -1399,8 +1402,8 @@ static int _regulator_force_disable(struct regulator_dev *rdev) return ret; } /* notify other consumers that power has been forced off */ - _notifier_call_chain(rdev, REGULATOR_EVENT_FORCE_DISABLE, - NULL); + _notifier_call_chain(rdev, REGULATOR_EVENT_FORCE_DISABLE | + REGULATOR_EVENT_DISABLE, NULL); } /* decrease our supplies ref count and disable if required */ diff --git a/include/linux/regulator/consumer.h b/include/linux/regulator/consumer.h index 030d92255c7a..28c9fd020d39 100644 --- a/include/linux/regulator/consumer.h +++ b/include/linux/regulator/consumer.h @@ -89,8 +89,9 @@ * REGULATION_OUT Regulator output is out of regulation. * FAIL Regulator output has failed. * OVER_TEMP Regulator over temp. - * FORCE_DISABLE Regulator shut down by software. + * FORCE_DISABLE Regulator forcibly shut down by software. * VOLTAGE_CHANGE Regulator voltage changed. + * DISABLE Regulator was disabled. * * NOTE: These events can be OR'ed together when passed into handler. */ @@ -102,6 +103,7 @@ #define REGULATOR_EVENT_OVER_TEMP 0x10 #define REGULATOR_EVENT_FORCE_DISABLE 0x20 #define REGULATOR_EVENT_VOLTAGE_CHANGE 0x40 +#define REGULATOR_EVENT_DISABLE 0x80 struct regulator; -- cgit v1.2.3 From 31aae2beeb3d601d556b6a8c39085940ad1e9f42 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 21 Dec 2009 12:21:52 +0000 Subject: regulator: Allow regulators to specify the time taken to ramp on enable Regulators may sometimes take longer to enable than the control operation used to do so, either because the regulator has ramp rate control used to limit inrush current or because the control operation is very fast (GPIO being the most common example of this). In order to ensure that consumers do not rely on the regulator before it is enabled provide an enable_time() operation and have the core delay for that time before returning to the caller. This is implemented as a function since the ramp rate may be specified in voltage per unit time and therefore the time depend on the configuration. In future it would be desirable to allow the bulk operations to run the delays for multiple enables in parallel but this is not currently supported. Signed-off-by: Mark Brown --- drivers/regulator/core.c | 41 ++++++++++++++++++++++++++++++++++------ include/linux/regulator/driver.h | 6 ++++++ 2 files changed, 41 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 6d2ce8a05331..ca8e1642538b 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -1084,6 +1085,13 @@ overflow_err: return NULL; } +static int _regulator_get_enable_time(struct regulator_dev *rdev) +{ + if (!rdev->desc->ops->enable_time) + return 0; + return rdev->desc->ops->enable_time(rdev); +} + /* Internal regulator request function */ static struct regulator *_regulator_get(struct device *dev, const char *id, int exclusive) @@ -1251,7 +1259,7 @@ static int _regulator_can_change_status(struct regulator_dev *rdev) /* locks held by regulator_enable() */ static int _regulator_enable(struct regulator_dev *rdev) { - int ret; + int ret, delay; /* do we need to enable the supply regulator first */ if (rdev->supply) { @@ -1275,13 +1283,34 @@ static int _regulator_enable(struct regulator_dev *rdev) if (!_regulator_can_change_status(rdev)) return -EPERM; - if (rdev->desc->ops->enable) { - ret = rdev->desc->ops->enable(rdev); - if (ret < 0) - return ret; - } else { + if (!rdev->desc->ops->enable) return -EINVAL; + + /* Query before enabling in case configuration + * dependant. */ + ret = _regulator_get_enable_time(rdev); + if (ret >= 0) { + delay = ret; + } else { + printk(KERN_WARNING + "%s: enable_time() failed for %s: %d\n", + __func__, rdev_get_name(rdev), + ret); + delay = 0; } + + /* Allow the regulator to ramp; it would be useful + * to extend this for bulk operations so that the + * regulators can ramp together. */ + ret = rdev->desc->ops->enable(rdev); + if (ret < 0) + return ret; + + if (delay >= 1000) + mdelay(delay / 1000); + else if (delay) + udelay(delay); + } else if (ret < 0) { printk(KERN_ERR "%s: is_enabled() failed for %s: %d\n", __func__, rdev_get_name(rdev), ret); diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h index 31f2055eae28..592cd7c642c2 100644 --- a/include/linux/regulator/driver.h +++ b/include/linux/regulator/driver.h @@ -58,6 +58,9 @@ enum regulator_status { * @get_optimum_mode: Get the most efficient operating mode for the regulator * when running with the specified parameters. * + * @enable_time: Time taken for the regulator voltage output voltage to + * stabalise after being enabled, in microseconds. + * * @set_suspend_voltage: Set the voltage for the regulator when the system * is suspended. * @set_suspend_enable: Mark the regulator as enabled when the system is @@ -93,6 +96,9 @@ struct regulator_ops { int (*set_mode) (struct regulator_dev *, unsigned int mode); unsigned int (*get_mode) (struct regulator_dev *); + /* Time taken to enable the regulator */ + int (*enable_time) (struct regulator_dev *); + /* report regulator status ... most other accessors report * control inputs, this reports results of combining inputs * from Linux (and other sources) with the actual load. -- cgit v1.2.3 From 75c8ac22e4b8ebea8169a090e64d034a96758644 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Jan 2010 17:24:01 +0000 Subject: regulator: Implement enable_time() for WM835x ISINKs Signed-off-by: Mark Brown --- drivers/regulator/wm8350-regulator.c | 46 ++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'drivers') diff --git a/drivers/regulator/wm8350-regulator.c b/drivers/regulator/wm8350-regulator.c index e7b89e704af6..94227dd6ba7b 100644 --- a/drivers/regulator/wm8350-regulator.c +++ b/drivers/regulator/wm8350-regulator.c @@ -290,6 +290,51 @@ static int wm8350_isink_is_enabled(struct regulator_dev *rdev) return -EINVAL; } +static int wm8350_isink_enable_time(struct regulator_dev *rdev) +{ + struct wm8350 *wm8350 = rdev_get_drvdata(rdev); + int isink = rdev_get_id(rdev); + int reg; + + switch (isink) { + case WM8350_ISINK_A: + reg = wm8350_reg_read(wm8350, WM8350_CSA_FLASH_CONTROL); + break; + case WM8350_ISINK_B: + reg = wm8350_reg_read(wm8350, WM8350_CSB_FLASH_CONTROL); + break; + default: + return -EINVAL; + } + + if (reg & WM8350_CS1_FLASH_MODE) { + switch (reg & WM8350_CS1_ON_RAMP_MASK) { + case 0: + return 0; + case 1: + return 1950; + case 2: + return 3910; + case 3: + return 7800; + } + } else { + switch (reg & WM8350_CS1_ON_RAMP_MASK) { + case 0: + return 0; + case 1: + return 250000; + case 2: + return 500000; + case 3: + return 1000000; + } + } + + return -EINVAL; +} + + int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode, u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp, u16 drive) @@ -1221,6 +1266,7 @@ static struct regulator_ops wm8350_isink_ops = { .enable = wm8350_isink_enable, .disable = wm8350_isink_disable, .is_enabled = wm8350_isink_is_enabled, + .enable_time = wm8350_isink_enable_time, }; static struct regulator_desc wm8350_reg[NUM_WM8350_REGULATORS] = { -- cgit v1.2.3 From eda79a3041a2cada0d4ee9491c99c3874b322356 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Tue, 12 Jan 2010 12:25:13 +0200 Subject: regulator: Add 'start-up time' to fixed voltage regulators Add a field to specify a delay for the start-up time of a fixed voltage regulator. Signed-off-by: Adrian Hunter Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/fixed.c | 5 +++++ include/linux/regulator/fixed.h | 2 ++ 2 files changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/regulator/fixed.c b/drivers/regulator/fixed.c index f9f516a3028a..ee3e7eb97b1c 100644 --- a/drivers/regulator/fixed.c +++ b/drivers/regulator/fixed.c @@ -24,12 +24,14 @@ #include #include #include +#include struct fixed_voltage_data { struct regulator_desc desc; struct regulator_dev *dev; int microvolts; int gpio; + unsigned startup_delay; unsigned enable_high:1; unsigned is_enabled:1; }; @@ -48,6 +50,8 @@ static int fixed_voltage_enable(struct regulator_dev *dev) if (gpio_is_valid(data->gpio)) { gpio_set_value_cansleep(data->gpio, data->enable_high); data->is_enabled = 1; + if (data->startup_delay) + udelay(data->startup_delay); } return 0; @@ -117,6 +121,7 @@ static int regulator_fixed_voltage_probe(struct platform_device *pdev) drvdata->microvolts = config->microvolts; drvdata->gpio = config->gpio; + drvdata->startup_delay = config->startup_delay; if (gpio_is_valid(config->gpio)) { drvdata->enable_high = config->enable_high; diff --git a/include/linux/regulator/fixed.h b/include/linux/regulator/fixed.h index e94a4a1c7c8a..ffd7d508e726 100644 --- a/include/linux/regulator/fixed.h +++ b/include/linux/regulator/fixed.h @@ -25,6 +25,7 @@ struct regulator_init_data; * @microvolts: Output voltage of regulator * @gpio: GPIO to use for enable control * set to -EINVAL if not used + * @startup_delay: Start-up time in microseconds * @enable_high: Polarity of enable GPIO * 1 = Active high, 0 = Active low * @enabled_at_boot: Whether regulator has been enabled at @@ -41,6 +42,7 @@ struct fixed_voltage_config { const char *supply_name; int microvolts; int gpio; + unsigned startup_delay; unsigned enable_high:1; unsigned enabled_at_boot:1; struct regulator_init_data *init_data; -- cgit v1.2.3 From f4b97b36b7c6b2d4455f27d6371869f915cbe8fd Mon Sep 17 00:00:00 2001 From: Alberto Panizzo Date: Tue, 19 Jan 2010 12:48:54 +0100 Subject: regulator: mc13783: consider Power Gates as digital regulators. GPO regulators are digital outputs that can be enabled or disabled by a dedicated bit in mc13783 POWERMISC register. In this family can be count in also Power Gates (PWGT1 and 2): enabled by a dedicated pin a Power Gate is an hardware driven supply where the output (PWGTnDRV) follow this law: Bit PWGTxSPIEN | Pin PWGTxEN | PWGTxDRV | Read Back 0 = default | | | PWGTxSPIEN ---------------+-------------+----------+------------ 1 | x | Low | 0 0 | 0 | High | 1 0 | 1 | Low | 0 As read back value of control bit reflects the PWGTxDRV state (not the control value previously written) and mc13783 POWERMISC register contain only regulator related bits, a dedicated function to manage these bits is created here with the aim of tracing the real value of PWGTxSPIEN bits and reproduce it on next writes. All POWERMISC users _must_ use the new function to not accidentally disable Power Gates supplies. v2 changes: -Better utilization of abstraction layers. -Voltage query support. GPO's and PWGTxDRV are fixed voltage regulator with voltage value of 3.1V and 5.5V respectively. Signed-off-by: Alberto Panizzo Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/mc13783-regulator.c | 132 ++++++++++++++++++++++++++++++++-- include/linux/mfd/mc13783.h | 2 + 2 files changed, 128 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/mc13783-regulator.c b/drivers/regulator/mc13783-regulator.c index a40e35ab8555..f7b81845a196 100644 --- a/drivers/regulator/mc13783-regulator.c +++ b/drivers/regulator/mc13783-regulator.c @@ -82,6 +82,11 @@ #define MC13783_REG_POWERMISC_GPO2EN (1 << 8) #define MC13783_REG_POWERMISC_GPO3EN (1 << 10) #define MC13783_REG_POWERMISC_GPO4EN (1 << 12) +#define MC13783_REG_POWERMISC_PWGT1SPIEN (1 << 15) +#define MC13783_REG_POWERMISC_PWGT2SPIEN (1 << 16) + +#define MC13783_REG_POWERMISC_PWGTSPI_M (3 << 15) + struct mc13783_regulator { struct regulator_desc desc; @@ -161,8 +166,17 @@ static const int const mc13783_vrf_val[] = { 1500000, 1875000, 2700000, 2775000, }; +static const int const mc13783_gpo_val[] = { + 3100000, +}; + +static const int const mc13783_pwgtdrv_val[] = { + 5500000, +}; + static struct regulator_ops mc13783_regulator_ops; static struct regulator_ops mc13783_fixed_regulator_ops; +static struct regulator_ops mc13783_gpo_regulator_ops; #define MC13783_DEFINE(prefix, _name, _reg, _vsel_reg, _voltages) \ [MC13783_ ## prefix ## _ ## _name] = { \ @@ -197,17 +211,19 @@ static struct regulator_ops mc13783_fixed_regulator_ops; .voltages = _voltages, \ } -#define MC13783_GPO_DEFINE(prefix, _name, _reg) \ +#define MC13783_GPO_DEFINE(prefix, _name, _reg, _voltages) \ [MC13783_ ## prefix ## _ ## _name] = { \ .desc = { \ .name = #prefix "_" #_name, \ - .ops = &mc13783_regulator_ops, \ + .n_voltages = ARRAY_SIZE(_voltages), \ + .ops = &mc13783_gpo_regulator_ops, \ .type = REGULATOR_VOLTAGE, \ .id = MC13783_ ## prefix ## _ ## _name, \ .owner = THIS_MODULE, \ }, \ .reg = MC13783_REG_ ## _reg, \ .enable_bit = MC13783_REG_ ## _reg ## _ ## _name ## EN, \ + .voltages = _voltages, \ } #define MC13783_DEFINE_SW(_name, _reg, _vsel_reg, _voltages) \ @@ -249,14 +265,17 @@ static struct mc13783_regulator mc13783_regulators[] = { mc13783_vmmc_val), MC13783_DEFINE_REGU(VMMC2, REGULATORMODE1, REGULATORSETTING1, \ mc13783_vmmc_val), - MC13783_GPO_DEFINE(REGU, GPO1, POWERMISC), - MC13783_GPO_DEFINE(REGU, GPO2, POWERMISC), - MC13783_GPO_DEFINE(REGU, GPO3, POWERMISC), - MC13783_GPO_DEFINE(REGU, GPO4, POWERMISC), + MC13783_GPO_DEFINE(REGU, GPO1, POWERMISC, mc13783_gpo_val), + MC13783_GPO_DEFINE(REGU, GPO2, POWERMISC, mc13783_gpo_val), + MC13783_GPO_DEFINE(REGU, GPO3, POWERMISC, mc13783_gpo_val), + MC13783_GPO_DEFINE(REGU, GPO4, POWERMISC, mc13783_gpo_val), + MC13783_GPO_DEFINE(REGU, PWGT1SPI, POWERMISC, mc13783_pwgtdrv_val), + MC13783_GPO_DEFINE(REGU, PWGT2SPI, POWERMISC, mc13783_pwgtdrv_val), }; struct mc13783_regulator_priv { struct mc13783 *mc13783; + u32 powermisc_pwgt_state; struct regulator_dev *regulators[]; }; @@ -445,6 +464,107 @@ static struct regulator_ops mc13783_fixed_regulator_ops = { .get_voltage = mc13783_fixed_regulator_get_voltage, }; +int mc13783_powermisc_rmw(struct mc13783_regulator_priv *priv, u32 mask, + u32 val) +{ + struct mc13783 *mc13783 = priv->mc13783; + int ret; + u32 valread; + + BUG_ON(val & ~mask); + + ret = mc13783_reg_read(mc13783, MC13783_REG_POWERMISC, &valread); + if (ret) + return ret; + + /* Update the stored state for Power Gates. */ + priv->powermisc_pwgt_state = + (priv->powermisc_pwgt_state & ~mask) | val; + priv->powermisc_pwgt_state &= MC13783_REG_POWERMISC_PWGTSPI_M; + + /* Construct the new register value */ + valread = (valread & ~mask) | val; + /* Overwrite the PWGTxEN with the stored version */ + valread = (valread & ~MC13783_REG_POWERMISC_PWGTSPI_M) | + priv->powermisc_pwgt_state; + + return mc13783_reg_write(mc13783, MC13783_REG_POWERMISC, valread); +} + +static int mc13783_gpo_regulator_enable(struct regulator_dev *rdev) +{ + struct mc13783_regulator_priv *priv = rdev_get_drvdata(rdev); + int id = rdev_get_id(rdev); + int ret; + u32 en_val = mc13783_regulators[id].enable_bit; + + dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); + + /* Power Gate enable value is 0 */ + if (id == MC13783_REGU_PWGT1SPI || + id == MC13783_REGU_PWGT2SPI) + en_val = 0; + + mc13783_lock(priv->mc13783); + ret = mc13783_powermisc_rmw(priv, mc13783_regulators[id].enable_bit, + en_val); + mc13783_unlock(priv->mc13783); + + return ret; +} + +static int mc13783_gpo_regulator_disable(struct regulator_dev *rdev) +{ + struct mc13783_regulator_priv *priv = rdev_get_drvdata(rdev); + int id = rdev_get_id(rdev); + int ret; + u32 dis_val = 0; + + dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); + + /* Power Gate disable value is 1 */ + if (id == MC13783_REGU_PWGT1SPI || + id == MC13783_REGU_PWGT2SPI) + dis_val = mc13783_regulators[id].enable_bit; + + mc13783_lock(priv->mc13783); + ret = mc13783_powermisc_rmw(priv, mc13783_regulators[id].enable_bit, + dis_val); + mc13783_unlock(priv->mc13783); + + return ret; +} + +static int mc13783_gpo_regulator_is_enabled(struct regulator_dev *rdev) +{ + struct mc13783_regulator_priv *priv = rdev_get_drvdata(rdev); + int ret, id = rdev_get_id(rdev); + unsigned int val; + + mc13783_lock(priv->mc13783); + ret = mc13783_reg_read(priv->mc13783, mc13783_regulators[id].reg, &val); + mc13783_unlock(priv->mc13783); + + if (ret) + return ret; + + /* Power Gates state is stored in powermisc_pwgt_state + * where the meaning of bits is negated */ + val = (val & ~MC13783_REG_POWERMISC_PWGTSPI_M) | + (priv->powermisc_pwgt_state ^ MC13783_REG_POWERMISC_PWGTSPI_M); + + return (val & mc13783_regulators[id].enable_bit) != 0; +} + +static struct regulator_ops mc13783_gpo_regulator_ops = { + .enable = mc13783_gpo_regulator_enable, + .disable = mc13783_gpo_regulator_disable, + .is_enabled = mc13783_gpo_regulator_is_enabled, + .list_voltage = mc13783_regulator_list_voltage, + .set_voltage = mc13783_fixed_regulator_set_voltage, + .get_voltage = mc13783_fixed_regulator_get_voltage, +}; + static int __devinit mc13783_regulator_probe(struct platform_device *pdev) { struct mc13783_regulator_priv *priv; diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h index 35680409b8cf..94cb51a64037 100644 --- a/include/linux/mfd/mc13783.h +++ b/include/linux/mfd/mc13783.h @@ -108,6 +108,8 @@ int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode, #define MC13783_REGU_V2 28 #define MC13783_REGU_V3 29 #define MC13783_REGU_V4 30 +#define MC13783_REGU_PWGT1SPI 31 +#define MC13783_REGU_PWGT2SPI 32 #define MC13783_IRQ_ADCDONE 0 #define MC13783_IRQ_ADCBISDONE 1 -- cgit v1.2.3 From 79ac9bc32094be15732c421ea1d9a18751ec1ecf Mon Sep 17 00:00:00 2001 From: Alex Chiang Date: Mon, 25 Jan 2010 21:14:37 -0700 Subject: regulator: trivial: fix typos in user-visible Kconfig text Fix Kconfig text for some Wolfson Micro devices. Cc: Mark Brown Signed-off-by: Alex Chiang Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 262f62eec837..c565e0d87287 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -91,14 +91,14 @@ config REGULATOR_WM831X of PMIC devices. config REGULATOR_WM8350 - tristate "Wolfson Microelectroncis WM8350 AudioPlus PMIC" + tristate "Wolfson Microelectronics WM8350 AudioPlus PMIC" depends on MFD_WM8350 help This driver provides support for the voltage and current regulators of the WM8350 AudioPlus PMIC. config REGULATOR_WM8400 - tristate "Wolfson Microelectroncis WM8400 AudioPlus PMIC" + tristate "Wolfson Microelectronics WM8400 AudioPlus PMIC" depends on MFD_WM8400 help This driver provides support for the voltage regulators of the -- cgit v1.2.3 From a71b797fdc672714bfff1fdc142042a95e97d7ba Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 25 Jan 2010 10:24:09 -0500 Subject: regulator: enable max8649 regulator driver Signed-off-by: Haojian Zhuang Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/Kconfig | 7 + drivers/regulator/Makefile | 1 + drivers/regulator/max8649.c | 408 ++++++++++++++++++++++++++++++++++++++ include/linux/regulator/max8649.h | 44 ++++ 4 files changed, 460 insertions(+) create mode 100644 drivers/regulator/max8649.c create mode 100644 include/linux/regulator/max8649.h (limited to 'drivers') diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index c565e0d87287..2bc01ee9d9f2 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -69,6 +69,13 @@ config REGULATOR_MAX1586 regulator via I2C bus. The provided regulator is suitable for PXA27x chips to control VCC_CORE and VCC_USIM voltages. +config REGULATOR_MAX8649 + tristate "Maxim 8649 voltage regulator" + depends on I2C + help + This driver controls a Maxim 8649 voltage output regulator via + I2C bus. + config REGULATOR_MAX8660 tristate "Maxim 8660/8661 voltage regulator" depends on I2C diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index b3c806c79415..075835be4396 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o obj-$(CONFIG_REGULATOR_TWL4030) += twl-regulator.o +obj-$(CONFIG_REGULATOR_MAX8649) += max8649.o obj-$(CONFIG_REGULATOR_MAX8660) += max8660.o obj-$(CONFIG_REGULATOR_WM831X) += wm831x-dcdc.o obj-$(CONFIG_REGULATOR_WM831X) += wm831x-isink.o diff --git a/drivers/regulator/max8649.c b/drivers/regulator/max8649.c new file mode 100644 index 000000000000..3ebdf698c648 --- /dev/null +++ b/drivers/regulator/max8649.c @@ -0,0 +1,408 @@ +/* + * Regulators driver for Maxim max8649 + * + * Copyright (C) 2009-2010 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include + +#define MAX8649_DCDC_VMIN 750000 /* uV */ +#define MAX8649_DCDC_VMAX 1380000 /* uV */ +#define MAX8649_DCDC_STEP 10000 /* uV */ +#define MAX8649_VOL_MASK 0x3f + +/* Registers */ +#define MAX8649_MODE0 0x00 +#define MAX8649_MODE1 0x01 +#define MAX8649_MODE2 0x02 +#define MAX8649_MODE3 0x03 +#define MAX8649_CONTROL 0x04 +#define MAX8649_SYNC 0x05 +#define MAX8649_RAMP 0x06 +#define MAX8649_CHIP_ID1 0x08 +#define MAX8649_CHIP_ID2 0x09 + +/* Bits */ +#define MAX8649_EN_PD (1 << 7) +#define MAX8649_VID0_PD (1 << 6) +#define MAX8649_VID1_PD (1 << 5) +#define MAX8649_VID_MASK (3 << 5) + +#define MAX8649_FORCE_PWM (1 << 7) +#define MAX8649_SYNC_EXTCLK (1 << 6) + +#define MAX8649_EXT_MASK (3 << 6) + +#define MAX8649_RAMP_MASK (7 << 5) +#define MAX8649_RAMP_DOWN (1 << 1) + +struct max8649_regulator_info { + struct regulator_dev *regulator; + struct i2c_client *i2c; + struct device *dev; + struct mutex io_lock; + + int vol_reg; + unsigned mode:2; /* bit[1:0] = VID1, VID0 */ + unsigned extclk_freq:2; + unsigned extclk:1; + unsigned ramp_timing:3; + unsigned ramp_down:1; +}; + +/* I2C operations */ + +static inline int max8649_read_device(struct i2c_client *i2c, + int reg, int bytes, void *dest) +{ + unsigned char data; + int ret; + + data = (unsigned char)reg; + ret = i2c_master_send(i2c, &data, 1); + if (ret < 0) + return ret; + ret = i2c_master_recv(i2c, dest, bytes); + if (ret < 0) + return ret; + return 0; +} + +static inline int max8649_write_device(struct i2c_client *i2c, + int reg, int bytes, void *src) +{ + unsigned char buf[bytes + 1]; + int ret; + + buf[0] = (unsigned char)reg; + memcpy(&buf[1], src, bytes); + + ret = i2c_master_send(i2c, buf, bytes + 1); + if (ret < 0) + return ret; + return 0; +} + +static int max8649_reg_read(struct i2c_client *i2c, int reg) +{ + struct max8649_regulator_info *info = i2c_get_clientdata(i2c); + unsigned char data; + int ret; + + mutex_lock(&info->io_lock); + ret = max8649_read_device(i2c, reg, 1, &data); + mutex_unlock(&info->io_lock); + + if (ret < 0) + return ret; + return (int)data; +} + +static int max8649_set_bits(struct i2c_client *i2c, int reg, + unsigned char mask, unsigned char data) +{ + struct max8649_regulator_info *info = i2c_get_clientdata(i2c); + unsigned char value; + int ret; + + mutex_lock(&info->io_lock); + ret = max8649_read_device(i2c, reg, 1, &value); + if (ret < 0) + goto out; + value &= ~mask; + value |= data; + ret = max8649_write_device(i2c, reg, 1, &value); +out: + mutex_unlock(&info->io_lock); + return ret; +} + +static inline int check_range(int min_uV, int max_uV) +{ + if ((min_uV < MAX8649_DCDC_VMIN) || (max_uV > MAX8649_DCDC_VMAX) + || (min_uV > max_uV)) + return -EINVAL; + return 0; +} + +static int max8649_list_voltage(struct regulator_dev *rdev, unsigned index) +{ + return (MAX8649_DCDC_VMIN + index * MAX8649_DCDC_STEP); +} + +static int max8649_get_voltage(struct regulator_dev *rdev) +{ + struct max8649_regulator_info *info = rdev_get_drvdata(rdev); + unsigned char data; + int ret; + + ret = max8649_reg_read(info->i2c, info->vol_reg); + if (ret < 0) + return ret; + data = (unsigned char)ret & MAX8649_VOL_MASK; + return max8649_list_voltage(rdev, data); +} + +static int max8649_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV) +{ + struct max8649_regulator_info *info = rdev_get_drvdata(rdev); + unsigned char data, mask; + + if (check_range(min_uV, max_uV)) { + dev_err(info->dev, "invalid voltage range (%d, %d) uV\n", + min_uV, max_uV); + return -EINVAL; + } + data = (min_uV - MAX8649_DCDC_VMIN + MAX8649_DCDC_STEP - 1) + / MAX8649_DCDC_STEP; + mask = MAX8649_VOL_MASK; + + return max8649_set_bits(info->i2c, info->vol_reg, mask, data); +} + +/* EN_PD means pulldown on EN input */ +static int max8649_enable(struct regulator_dev *rdev) +{ + struct max8649_regulator_info *info = rdev_get_drvdata(rdev); + return max8649_set_bits(info->i2c, MAX8649_CONTROL, MAX8649_EN_PD, 0); +} + +/* + * Applied internal pulldown resistor on EN input pin. + * If pulldown EN pin outside, it would be better. + */ +static int max8649_disable(struct regulator_dev *rdev) +{ + struct max8649_regulator_info *info = rdev_get_drvdata(rdev); + return max8649_set_bits(info->i2c, MAX8649_CONTROL, MAX8649_EN_PD, + MAX8649_EN_PD); +} + +static int max8649_is_enabled(struct regulator_dev *rdev) +{ + struct max8649_regulator_info *info = rdev_get_drvdata(rdev); + int ret; + + ret = max8649_reg_read(info->i2c, MAX8649_CONTROL); + if (ret < 0) + return ret; + return !((unsigned char)ret & MAX8649_EN_PD); +} + +static int max8649_enable_time(struct regulator_dev *rdev) +{ + struct max8649_regulator_info *info = rdev_get_drvdata(rdev); + int voltage, rate, ret; + + /* get voltage */ + ret = max8649_reg_read(info->i2c, info->vol_reg); + if (ret < 0) + return ret; + ret &= MAX8649_VOL_MASK; + voltage = max8649_list_voltage(rdev, (unsigned char)ret); /* uV */ + + /* get rate */ + ret = max8649_reg_read(info->i2c, MAX8649_RAMP); + if (ret < 0) + return ret; + ret = (ret & MAX8649_RAMP_MASK) >> 5; + rate = (32 * 1000) >> ret; /* uV/uS */ + + return (voltage / rate); +} + +static int max8649_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + struct max8649_regulator_info *info = rdev_get_drvdata(rdev); + + switch (mode) { + case REGULATOR_MODE_FAST: + max8649_set_bits(info->i2c, info->vol_reg, MAX8649_FORCE_PWM, + MAX8649_FORCE_PWM); + break; + case REGULATOR_MODE_NORMAL: + max8649_set_bits(info->i2c, info->vol_reg, + MAX8649_FORCE_PWM, 0); + break; + default: + return -EINVAL; + } + return 0; +} + +static unsigned int max8649_get_mode(struct regulator_dev *rdev) +{ + struct max8649_regulator_info *info = rdev_get_drvdata(rdev); + int ret; + + ret = max8649_reg_read(info->i2c, info->vol_reg); + if (ret & MAX8649_FORCE_PWM) + return REGULATOR_MODE_FAST; + return REGULATOR_MODE_NORMAL; +} + +static struct regulator_ops max8649_dcdc_ops = { + .set_voltage = max8649_set_voltage, + .get_voltage = max8649_get_voltage, + .list_voltage = max8649_list_voltage, + .enable = max8649_enable, + .disable = max8649_disable, + .is_enabled = max8649_is_enabled, + .enable_time = max8649_enable_time, + .set_mode = max8649_set_mode, + .get_mode = max8649_get_mode, + +}; + +static struct regulator_desc dcdc_desc = { + .name = "max8649", + .ops = &max8649_dcdc_ops, + .type = REGULATOR_VOLTAGE, + .n_voltages = 1 << 6, + .owner = THIS_MODULE, +}; + +static int __devinit max8649_regulator_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct max8649_platform_data *pdata = client->dev.platform_data; + struct max8649_regulator_info *info = NULL; + unsigned char data; + int ret; + + info = kzalloc(sizeof(struct max8649_regulator_info), GFP_KERNEL); + if (!info) { + dev_err(&client->dev, "No enough memory\n"); + return -ENOMEM; + } + + info->i2c = client; + info->dev = &client->dev; + mutex_init(&info->io_lock); + i2c_set_clientdata(client, info); + + info->mode = pdata->mode; + switch (info->mode) { + case 0: + info->vol_reg = MAX8649_MODE0; + break; + case 1: + info->vol_reg = MAX8649_MODE1; + break; + case 2: + info->vol_reg = MAX8649_MODE2; + break; + case 3: + info->vol_reg = MAX8649_MODE3; + break; + default: + break; + } + + ret = max8649_reg_read(info->i2c, MAX8649_CHIP_ID1); + if (ret < 0) { + dev_err(info->dev, "Failed to detect ID of MAX8649:%d\n", + ret); + goto out; + } + dev_info(info->dev, "Detected MAX8649 (ID:%x)\n", ret); + + /* enable VID0 & VID1 */ + max8649_set_bits(info->i2c, MAX8649_CONTROL, MAX8649_VID_MASK, 0); + + /* enable/disable external clock synchronization */ + info->extclk = pdata->extclk; + data = (info->extclk) ? MAX8649_SYNC_EXTCLK : 0; + max8649_set_bits(info->i2c, info->vol_reg, MAX8649_SYNC_EXTCLK, data); + if (info->extclk) { + /* set external clock frequency */ + info->extclk_freq = pdata->extclk_freq; + max8649_set_bits(info->i2c, MAX8649_SYNC, MAX8649_EXT_MASK, + info->extclk_freq); + } + + if (pdata->ramp_timing) { + info->ramp_timing = pdata->ramp_timing; + max8649_set_bits(info->i2c, MAX8649_RAMP, MAX8649_RAMP_MASK, + info->ramp_timing << 5); + } + + info->ramp_down = pdata->ramp_down; + if (info->ramp_down) { + max8649_set_bits(info->i2c, MAX8649_RAMP, MAX8649_RAMP_DOWN, + MAX8649_RAMP_DOWN); + } + + info->regulator = regulator_register(&dcdc_desc, &client->dev, + pdata->regulator, info); + if (IS_ERR(info->regulator)) { + dev_err(info->dev, "failed to register regulator %s\n", + dcdc_desc.name); + ret = PTR_ERR(info->regulator); + goto out; + } + + dev_info(info->dev, "Max8649 regulator device is detected.\n"); + return 0; +out: + kfree(info); + return ret; +} + +static int __devexit max8649_regulator_remove(struct i2c_client *client) +{ + struct max8649_regulator_info *info = i2c_get_clientdata(client); + + if (info) { + if (info->regulator) + regulator_unregister(info->regulator); + kfree(info); + } + i2c_set_clientdata(client, NULL); + + return 0; +} + +static const struct i2c_device_id max8649_id[] = { + { "max8649", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, max8649_id); + +static struct i2c_driver max8649_driver = { + .probe = max8649_regulator_probe, + .remove = __devexit_p(max8649_regulator_remove), + .driver = { + .name = "max8649", + }, + .id_table = max8649_id, +}; + +static int __init max8649_init(void) +{ + return i2c_add_driver(&max8649_driver); +} +subsys_initcall(max8649_init); + +static void __exit max8649_exit(void) +{ + i2c_del_driver(&max8649_driver); +} +module_exit(max8649_exit); + +/* Module information */ +MODULE_DESCRIPTION("MAXIM 8649 voltage regulator driver"); +MODULE_AUTHOR("Haojian Zhuang "); +MODULE_LICENSE("GPL"); + diff --git a/include/linux/regulator/max8649.h b/include/linux/regulator/max8649.h new file mode 100644 index 000000000000..417d14ecd5cb --- /dev/null +++ b/include/linux/regulator/max8649.h @@ -0,0 +1,44 @@ +/* + * Interface of Maxim max8649 + * + * Copyright (C) 2009-2010 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_REGULATOR_MAX8649_H +#define __LINUX_REGULATOR_MAX8649_H + +#include + +enum { + MAX8649_EXTCLK_26MHZ = 0, + MAX8649_EXTCLK_13MHZ, + MAX8649_EXTCLK_19MHZ, /* 19.2MHz */ +}; + +enum { + MAX8649_RAMP_32MV = 0, + MAX8649_RAMP_16MV, + MAX8649_RAMP_8MV, + MAX8649_RAMP_4MV, + MAX8649_RAMP_2MV, + MAX8649_RAMP_1MV, + MAX8649_RAMP_0_5MV, + MAX8649_RAMP_0_25MV, +}; + +struct max8649_platform_data { + struct regulator_init_data *regulator; + + unsigned mode:2; /* bit[1:0] = VID1,VID0 */ + unsigned extclk_freq:2; + unsigned extclk:1; + unsigned ramp_timing:3; + unsigned ramp_down:1; +}; + +#endif /* __LINUX_REGULATOR_MAX8649_H */ -- cgit v1.2.3 From 69dc16c325bef32b0a1a1abf15ae4047174cafc1 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 25 Jan 2010 19:41:57 +0000 Subject: regulator: Add WM8994 regulator support The WM8994 contains two LDOs with mixed hardware/software control to minimise the number of external supplies required while delivering optimal voltages to minimise power consumption. Signed-off-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/Kconfig | 7 + drivers/regulator/Makefile | 1 + drivers/regulator/wm8994-regulator.c | 304 +++++++++++++++++++++++++++++++++++ 3 files changed, 312 insertions(+) create mode 100644 drivers/regulator/wm8994-regulator.c (limited to 'drivers') diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 2bc01ee9d9f2..3c07169498cf 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -111,6 +111,13 @@ config REGULATOR_WM8400 This driver provides support for the voltage regulators of the WM8400 AudioPlus PMIC. +config REGULATOR_WM8994 + tristate "Wolfson Microelectronics WM8994 CODEC" + depends on MFD_WM8994 + help + This driver provides support for the voltage regulators on the + WM8994 CODEC. + config REGULATOR_DA903X tristate "Support regulators on Dialog Semiconductor DA9030/DA9034 PMIC" depends on PMIC_DA903X diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 075835be4396..7c59bcb10613 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_REGULATOR_WM831X) += wm831x-isink.o obj-$(CONFIG_REGULATOR_WM831X) += wm831x-ldo.o obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o +obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o obj-$(CONFIG_REGULATOR_DA903X) += da903x.o obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o obj-$(CONFIG_REGULATOR_PCAP) += pcap-regulator.o diff --git a/drivers/regulator/wm8994-regulator.c b/drivers/regulator/wm8994-regulator.c new file mode 100644 index 000000000000..d09e018b3177 --- /dev/null +++ b/drivers/regulator/wm8994-regulator.c @@ -0,0 +1,304 @@ +/* + * wm8994-regulator.c -- Regulator driver for the WM8994 + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +struct wm8994_ldo { + int enable; + int is_enabled; + struct regulator_dev *regulator; + struct wm8994 *wm8994; +}; + +#define WM8994_LDO1_MAX_SELECTOR 0x7 +#define WM8994_LDO2_MAX_SELECTOR 0x3 + +static int wm8994_ldo_enable(struct regulator_dev *rdev) +{ + struct wm8994_ldo *ldo = rdev_get_drvdata(rdev); + + /* If we have no soft control assume that the LDO is always enabled. */ + if (!ldo->enable) + return 0; + + gpio_set_value(ldo->enable, 1); + ldo->is_enabled = 1; + + return 0; +} + +static int wm8994_ldo_disable(struct regulator_dev *rdev) +{ + struct wm8994_ldo *ldo = rdev_get_drvdata(rdev); + + /* If we have no soft control assume that the LDO is always enabled. */ + if (!ldo->enable) + return -EINVAL; + + gpio_set_value(ldo->enable, 0); + ldo->is_enabled = 0; + + return 0; +} + +static int wm8994_ldo_is_enabled(struct regulator_dev *rdev) +{ + struct wm8994_ldo *ldo = rdev_get_drvdata(rdev); + + return ldo->is_enabled; +} + +static int wm8994_ldo_enable_time(struct regulator_dev *rdev) +{ + /* 3ms is fairly conservative but this shouldn't be too performance + * critical; can be tweaked per-system if required. */ + return 3000; +} + +static int wm8994_ldo1_list_voltage(struct regulator_dev *rdev, + unsigned int selector) +{ + if (selector > WM8994_LDO1_MAX_SELECTOR) + return -EINVAL; + + return (selector * 100000) + 2400000; +} + +static int wm8994_ldo1_get_voltage(struct regulator_dev *rdev) +{ + struct wm8994_ldo *ldo = rdev_get_drvdata(rdev); + int val; + + val = wm8994_reg_read(ldo->wm8994, WM8994_LDO_1); + if (val < 0) + return val; + + val = (val & WM8994_LDO1_VSEL_MASK) >> WM8994_LDO1_VSEL_SHIFT; + + return wm8994_ldo1_list_voltage(rdev, val); +} + +static int wm8994_ldo1_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV) +{ + struct wm8994_ldo *ldo = rdev_get_drvdata(rdev); + int selector, v; + + selector = (min_uV - 2400000) / 100000; + v = wm8994_ldo1_list_voltage(rdev, selector); + if (v < 0 || v > max_uV) + return -EINVAL; + + selector <<= WM8994_LDO1_VSEL_SHIFT; + + return wm8994_set_bits(ldo->wm8994, WM8994_LDO_1, + WM8994_LDO1_VSEL_MASK, selector); +} + +static struct regulator_ops wm8994_ldo1_ops = { + .enable = wm8994_ldo_enable, + .disable = wm8994_ldo_disable, + .is_enabled = wm8994_ldo_is_enabled, + .enable_time = wm8994_ldo_enable_time, + + .list_voltage = wm8994_ldo1_list_voltage, + .get_voltage = wm8994_ldo1_get_voltage, + .set_voltage = wm8994_ldo1_set_voltage, +}; + +static int wm8994_ldo2_list_voltage(struct regulator_dev *rdev, + unsigned int selector) +{ + if (selector > WM8994_LDO2_MAX_SELECTOR) + return -EINVAL; + + return (selector * 100000) + 900000; +} + +static int wm8994_ldo2_get_voltage(struct regulator_dev *rdev) +{ + struct wm8994_ldo *ldo = rdev_get_drvdata(rdev); + int val; + + val = wm8994_reg_read(ldo->wm8994, WM8994_LDO_2); + if (val < 0) + return val; + + val = (val & WM8994_LDO2_VSEL_MASK) >> WM8994_LDO2_VSEL_SHIFT; + + return wm8994_ldo2_list_voltage(rdev, val); +} + +static int wm8994_ldo2_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV) +{ + struct wm8994_ldo *ldo = rdev_get_drvdata(rdev); + int selector, v; + + selector = (min_uV - 900000) / 100000; + v = wm8994_ldo2_list_voltage(rdev, selector); + if (v < 0 || v > max_uV) + return -EINVAL; + + selector <<= WM8994_LDO2_VSEL_SHIFT; + + return wm8994_set_bits(ldo->wm8994, WM8994_LDO_2, + WM8994_LDO2_VSEL_MASK, selector); +} + +static struct regulator_ops wm8994_ldo2_ops = { + .enable = wm8994_ldo_enable, + .disable = wm8994_ldo_disable, + .is_enabled = wm8994_ldo_is_enabled, + .enable_time = wm8994_ldo_enable_time, + + .list_voltage = wm8994_ldo2_list_voltage, + .get_voltage = wm8994_ldo2_get_voltage, + .set_voltage = wm8994_ldo2_set_voltage, +}; + +static struct regulator_desc wm8994_ldo_desc[] = { + { + .name = "LDO1", + .id = 1, + .type = REGULATOR_VOLTAGE, + .n_voltages = WM8994_LDO1_MAX_SELECTOR + 1, + .ops = &wm8994_ldo1_ops, + .owner = THIS_MODULE, + }, + { + .name = "LDO2", + .id = 2, + .type = REGULATOR_VOLTAGE, + .n_voltages = WM8994_LDO2_MAX_SELECTOR + 1, + .ops = &wm8994_ldo2_ops, + .owner = THIS_MODULE, + }, +}; + +static __devinit int wm8994_ldo_probe(struct platform_device *pdev) +{ + struct wm8994 *wm8994 = dev_get_drvdata(pdev->dev.parent); + struct wm8994_pdata *pdata = wm8994->dev->platform_data; + int id = pdev->id % ARRAY_SIZE(pdata->ldo); + struct wm8994_ldo *ldo; + int ret; + + dev_dbg(&pdev->dev, "Probing LDO%d\n", id + 1); + + if (!pdata) + return -ENODEV; + + ldo = kzalloc(sizeof(struct wm8994_ldo), GFP_KERNEL); + if (ldo == NULL) { + dev_err(&pdev->dev, "Unable to allocate private data\n"); + return -ENOMEM; + } + + ldo->wm8994 = wm8994; + + ldo->is_enabled = 1; + + if (pdata->ldo[id].enable && gpio_is_valid(pdata->ldo[id].enable)) { + ldo->enable = pdata->ldo[id].enable; + + ret = gpio_request(ldo->enable, "WM8994 LDO enable"); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to get enable GPIO: %d\n", + ret); + goto err; + } + + ret = gpio_direction_output(ldo->enable, ldo->is_enabled); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to set GPIO up: %d\n", + ret); + goto err_gpio; + } + } + + ldo->regulator = regulator_register(&wm8994_ldo_desc[id], &pdev->dev, + pdata->ldo[id].init_data, ldo); + if (IS_ERR(ldo->regulator)) { + ret = PTR_ERR(ldo->regulator); + dev_err(wm8994->dev, "Failed to register LDO%d: %d\n", + id + 1, ret); + goto err_gpio; + } + + platform_set_drvdata(pdev, ldo); + + return 0; + +err_gpio: + if (gpio_is_valid(ldo->enable)) + gpio_free(ldo->enable); +err: + kfree(ldo); + return ret; +} + +static __devexit int wm8994_ldo_remove(struct platform_device *pdev) +{ + struct wm8994_ldo *ldo = platform_get_drvdata(pdev); + + regulator_unregister(ldo->regulator); + if (gpio_is_valid(ldo->enable)) + gpio_free(ldo->enable); + kfree(ldo); + + return 0; +} + +static struct platform_driver wm8994_ldo_driver = { + .probe = wm8994_ldo_probe, + .remove = __devexit_p(wm8994_ldo_remove), + .driver = { + .name = "wm8994-ldo", + }, +}; + +static int __init wm8994_ldo_init(void) +{ + int ret; + + ret = platform_driver_register(&wm8994_ldo_driver); + if (ret != 0) + pr_err("Failed to register Wm8994 GP LDO driver: %d\n", ret); + + return ret; +} +subsys_initcall(wm8994_ldo_init); + +static void __exit wm8994_ldo_exit(void) +{ + platform_driver_unregister(&wm8994_ldo_driver); +} +module_exit(wm8994_ldo_exit); + +/* Module information */ +MODULE_AUTHOR("Mark Brown "); +MODULE_DESCRIPTION("WM8994 LDO driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:wm8994-ldo"); -- cgit v1.2.3 From 17133dc82422cb118c843c3e9bbd565c37506ec8 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 28 Jan 2010 10:21:05 +0000 Subject: regulator: Convert fixed voltage regulator to use enable_time() It had an open coded version in enable(). Signed-off-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/fixed.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/fixed.c b/drivers/regulator/fixed.c index ee3e7eb97b1c..a3d3bfc24b1f 100644 --- a/drivers/regulator/fixed.c +++ b/drivers/regulator/fixed.c @@ -50,8 +50,6 @@ static int fixed_voltage_enable(struct regulator_dev *dev) if (gpio_is_valid(data->gpio)) { gpio_set_value_cansleep(data->gpio, data->enable_high); data->is_enabled = 1; - if (data->startup_delay) - udelay(data->startup_delay); } return 0; @@ -69,6 +67,13 @@ static int fixed_voltage_disable(struct regulator_dev *dev) return 0; } +static int fixed_voltage_enable_time(struct regulator_dev *dev) +{ + struct fixed_voltage_data *data = rdev_get_drvdata(dev); + + return data->startup_delay; +} + static int fixed_voltage_get_voltage(struct regulator_dev *dev) { struct fixed_voltage_data *data = rdev_get_drvdata(dev); @@ -91,6 +96,7 @@ static struct regulator_ops fixed_voltage_ops = { .is_enabled = fixed_voltage_is_enabled, .enable = fixed_voltage_enable, .disable = fixed_voltage_disable, + .enable_time = fixed_voltage_enable_time, .get_voltage = fixed_voltage_get_voltage, .list_voltage = fixed_voltage_list_voltage, }; -- cgit v1.2.3 From 9a7f6a4c6edc84748c6477c9df56691a0e61b8fd Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 11 Feb 2010 17:22:45 +0000 Subject: regulator: Assume regulators are enabled if they don't report anything If a regulator driver does not provide a way to query if the driver is enabled then assume that it is enabled. This is very likely to reflect the actual state is more useful for callers than reporting an error. Signed-off-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index ca8e1642538b..75a26f780918 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -1466,9 +1466,9 @@ EXPORT_SYMBOL_GPL(regulator_force_disable); static int _regulator_is_enabled(struct regulator_dev *rdev) { - /* sanity check */ + /* If we don't know then assume that the regulator is always on */ if (!rdev->desc->ops->is_enabled) - return -EINVAL; + return 1; return rdev->desc->ops->is_enabled(rdev); } -- cgit v1.2.3 From 34abbd68efe09765465b81dfedeee9994f13302f Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 12 Feb 2010 10:18:08 +0000 Subject: regulator: Provide optional dummy regulator for consumers In order to ease transitions with drivers are boards start using regulators provide an option to cause all regulator_get() calls to succeed, with a dummy always on regulator being supplied where one has not been configured. A warning is printed whenever the dummy regulator is used to aid system development. This regulator does not implement any regulator operations but will allow simple consumers which only do enable() and disable() calls to run. It is kept separate from the fixed voltage regulator to avoid Kconfig confusion on the part of users when it is extended to allow boards to explicitly use the dummy regulator to simplify cases where the majority of supplies are from fixed regulators without software control. This option is currently only effective for systems which do not specify full constriants. If required an override could also be provided to allow these systems to use the dummy regulator, though it is likely that unconfigured supplies on such systems will lead to error due to regulators being powered down more aggressively when not in use. Signed-off-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/Kconfig | 11 ++++++++ drivers/regulator/Makefile | 1 + drivers/regulator/core.c | 27 ++++++++++++++++++- drivers/regulator/dummy.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/regulator/dummy.h | 31 ++++++++++++++++++++++ 5 files changed, 135 insertions(+), 1 deletion(-) create mode 100644 drivers/regulator/dummy.c create mode 100644 drivers/regulator/dummy.h (limited to 'drivers') diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 3c07169498cf..834b48441829 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -27,6 +27,17 @@ config REGULATOR_DEBUG help Say yes here to enable debugging support. +config REGULATOR_DUMMY + bool "Provide a dummy regulator if regulator lookups fail" + help + If this option is enabled then when a regulator lookup fails + and the board has not specified that it has provided full + constraints then the regulator core will provide an always + enabled dummy regulator will be provided, allowing consumer + drivers to continue. + + A warning will be generated when this substitution is done. + config REGULATOR_FIXED_VOLTAGE tristate "Fixed voltage regulator support" help diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 7c59bcb10613..e845b66ad59c 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER) += virtual.o obj-$(CONFIG_REGULATOR_USERSPACE_CONSUMER) += userspace-consumer.o obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o +obj-$(CONFIG_REGULATOR_DUMMY) += dummy.o obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o obj-$(CONFIG_REGULATOR_TWL4030) += twl-regulator.o diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 75a26f780918..c7bbe30010f7 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -24,6 +24,8 @@ #include #include +#include "dummy.h" + #define REGULATOR_VERSION "0.5" static DEFINE_MUTEX(regulator_list_mutex); @@ -1123,6 +1125,22 @@ static struct regulator *_regulator_get(struct device *dev, const char *id, goto found; } } + +#ifdef CONFIG_REGULATOR_DUMMY + if (!devname) + devname = "deviceless"; + + /* If the board didn't flag that it was fully constrained then + * substitute in a dummy regulator so consumers can continue. + */ + if (!has_full_constraints) { + pr_warning("%s supply %s not found, using dummy regulator\n", + devname, id); + rdev = dummy_regulator_rdev; + goto found; + } +#endif + mutex_unlock(®ulator_list_mutex); return regulator; @@ -2483,8 +2501,15 @@ EXPORT_SYMBOL_GPL(regulator_get_init_drvdata); static int __init regulator_init(void) { + int ret; + printk(KERN_INFO "regulator: core version %s\n", REGULATOR_VERSION); - return class_register(®ulator_class); + + ret = class_register(®ulator_class); + + regulator_dummy_init(); + + return ret; } /* init early to allow our consumers to complete system booting */ diff --git a/drivers/regulator/dummy.c b/drivers/regulator/dummy.c new file mode 100644 index 000000000000..c7410bde7b5d --- /dev/null +++ b/drivers/regulator/dummy.c @@ -0,0 +1,66 @@ +/* + * dummy.c + * + * Copyright 2010 Wolfson Microelectronics PLC. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This is useful for systems with mixed controllable and + * non-controllable regulators, as well as for allowing testing on + * systems with no controllable regulators. + */ + +#include +#include +#include +#include + +#include "dummy.h" + +struct regulator_dev *dummy_regulator_rdev; + +static struct regulator_init_data dummy_initdata; + +static struct regulator_ops dummy_ops; + +static struct regulator_desc dummy_desc = { + .name = "dummy", + .id = -1, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, + .ops = &dummy_ops, +}; + +static struct platform_device *dummy_pdev; + +void __init regulator_dummy_init(void) +{ + int ret; + + dummy_pdev = platform_device_alloc("reg-dummy", -1); + if (!dummy_pdev) { + pr_err("Failed to allocate dummy regulator device\n"); + return; + } + + ret = platform_device_add(dummy_pdev); + if (ret != 0) { + pr_err("Failed to register dummy regulator device: %d\n", ret); + platform_device_put(dummy_pdev); + return; + } + + dummy_regulator_rdev = regulator_register(&dummy_desc, NULL, + &dummy_initdata, NULL); + if (IS_ERR(dummy_regulator_rdev)) { + ret = PTR_ERR(dummy_regulator_rdev); + pr_err("Failed to register regulator: %d\n", ret); + platform_device_unregister(dummy_pdev); + return; + } +} diff --git a/drivers/regulator/dummy.h b/drivers/regulator/dummy.h new file mode 100644 index 000000000000..3921c0e24249 --- /dev/null +++ b/drivers/regulator/dummy.h @@ -0,0 +1,31 @@ +/* + * dummy.h + * + * Copyright 2010 Wolfson Microelectronics PLC. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This is useful for systems with mixed controllable and + * non-controllable regulators, as well as for allowing testing on + * systems with no controllable regulators. + */ + +#ifndef _DUMMY_H +#define _DUMMY_H + +struct regulator_dev; + +extern struct regulator_dev *dummy_regulator_rdev; + +#ifdef CONFIG_REGULATOR_DUMMY +void __init regulator_dummy_init(void); +#else +static inline void regulator_dummy_init(void) { } +#endif + +#endif -- cgit v1.2.3 From 2ebcf63245b4496808712ed884f6a330d73bc807 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 17 Feb 2010 20:54:15 +0530 Subject: twl6030: regulator: Configure STATE register instead of REMAP This is no REMAP register on twl6030, instead there is a STATE register to drive a resource to a given state. The state register can be used to specify what state the resource should enter when its associated with a GRP. Register Bit field description is as below. The patch programmes the corresponding STATE registers for all LDO's to turn ON when assocaited with GRP_P1. STATE REG: Bit7 |Bit6 |Bit5 |Bit4 |Bit3 |Bit2 |Bit1 |Bit0 P3_GRP |P2_GRP |P1_GRP |RES |RES |RES |State1 |State0 State can be specified as below 00: OFF 01: ON 10: OFF 11: SLEEP Signed-off-by: Rajendra Nayak Cc: Liam Girdwood Cc: Samuel Ortiz Cc: Mark Brown Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/twl-regulator.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/twl-regulator.c b/drivers/regulator/twl-regulator.c index 7e674859bd59..5f394bb8701f 100644 --- a/drivers/regulator/twl-regulator.c +++ b/drivers/regulator/twl-regulator.c @@ -519,16 +519,16 @@ static struct twlreg_info twl_regs[] = { /* 6030 REG with base as PMC Slave Misc : 0x0030 */ /* Turnon-delay and remap configuration values for 6030 are not verified since the specification is not public */ - TWL6030_ADJUSTABLE_LDO(VAUX1_6030, 0x54, 1, 0, 0x08), - TWL6030_ADJUSTABLE_LDO(VAUX2_6030, 0x58, 2, 0, 0x08), - TWL6030_ADJUSTABLE_LDO(VAUX3_6030, 0x5c, 3, 0, 0x08), - TWL6030_ADJUSTABLE_LDO(VMMC, 0x68, 4, 0, 0x08), - TWL6030_ADJUSTABLE_LDO(VPP, 0x6c, 5, 0, 0x08), - TWL6030_ADJUSTABLE_LDO(VUSIM, 0x74, 7, 0, 0x08), - TWL6030_FIXED_LDO(VANA, 0x50, 2100, 15, 0, 0x08), - TWL6030_FIXED_LDO(VCXIO, 0x60, 1800, 16, 0, 0x08), - TWL6030_FIXED_LDO(VDAC, 0x64, 1800, 17, 0, 0x08), - TWL6030_FIXED_LDO(VUSB, 0x70, 3300, 18, 0, 0x08) + TWL6030_ADJUSTABLE_LDO(VAUX1_6030, 0x54, 1, 0, 0x21), + TWL6030_ADJUSTABLE_LDO(VAUX2_6030, 0x58, 2, 0, 0x21), + TWL6030_ADJUSTABLE_LDO(VAUX3_6030, 0x5c, 3, 0, 0x21), + TWL6030_ADJUSTABLE_LDO(VMMC, 0x68, 4, 0, 0x21), + TWL6030_ADJUSTABLE_LDO(VPP, 0x6c, 5, 0, 0x21), + TWL6030_ADJUSTABLE_LDO(VUSIM, 0x74, 7, 0, 0x21), + TWL6030_FIXED_LDO(VANA, 0x50, 2100, 15, 0, 0x21), + TWL6030_FIXED_LDO(VCXIO, 0x60, 1800, 16, 0, 0x21), + TWL6030_FIXED_LDO(VDAC, 0x64, 1800, 17, 0, 0x21), + TWL6030_FIXED_LDO(VUSB, 0x70, 3300, 18, 0, 0x21) }; static int twlreg_probe(struct platform_device *pdev) -- cgit v1.2.3 From 4cf95663c829ddd47c76ba5b749e88864beef0a7 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 23 Feb 2010 23:37:44 -0800 Subject: Regulators: virtual - use sysfs attribute groups Instead of open-coding sysfs attribute group use canned solution. Also add __devinit/__devexit markups for probe and remove methods and use 'bool' where it makes sense. Signed-off-by: Dmitry Torokhov Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/virtual.c | 64 +++++++++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 31 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/virtual.c b/drivers/regulator/virtual.c index addc032c84bf..d96cecaac73d 100644 --- a/drivers/regulator/virtual.c +++ b/drivers/regulator/virtual.c @@ -19,7 +19,7 @@ struct virtual_consumer_data { struct mutex lock; struct regulator *regulator; - int enabled; + bool enabled; int min_uV; int max_uV; int min_uA; @@ -49,7 +49,7 @@ static void update_voltage_constraints(struct device *dev, dev_dbg(dev, "Enabling regulator\n"); ret = regulator_enable(data->regulator); if (ret == 0) - data->enabled = 1; + data->enabled = true; else dev_err(dev, "regulator_enable() failed: %d\n", ret); @@ -59,7 +59,7 @@ static void update_voltage_constraints(struct device *dev, dev_dbg(dev, "Disabling regulator\n"); ret = regulator_disable(data->regulator); if (ret == 0) - data->enabled = 0; + data->enabled = false; else dev_err(dev, "regulator_disable() failed: %d\n", ret); @@ -89,7 +89,7 @@ static void update_current_limit_constraints(struct device *dev, dev_dbg(dev, "Enabling regulator\n"); ret = regulator_enable(data->regulator); if (ret == 0) - data->enabled = 1; + data->enabled = true; else dev_err(dev, "regulator_enable() failed: %d\n", ret); @@ -99,7 +99,7 @@ static void update_current_limit_constraints(struct device *dev, dev_dbg(dev, "Disabling regulator\n"); ret = regulator_disable(data->regulator); if (ret == 0) - data->enabled = 0; + data->enabled = false; else dev_err(dev, "regulator_disable() failed: %d\n", ret); @@ -270,24 +270,28 @@ static DEVICE_ATTR(min_microamps, 0666, show_min_uA, set_min_uA); static DEVICE_ATTR(max_microamps, 0666, show_max_uA, set_max_uA); static DEVICE_ATTR(mode, 0666, show_mode, set_mode); -static struct device_attribute *attributes[] = { - &dev_attr_min_microvolts, - &dev_attr_max_microvolts, - &dev_attr_min_microamps, - &dev_attr_max_microamps, - &dev_attr_mode, +static struct attribute *regulator_virtual_attributes[] = { + &dev_attr_min_microvolts.attr, + &dev_attr_max_microvolts.attr, + &dev_attr_min_microamps.attr, + &dev_attr_max_microamps.attr, + &dev_attr_mode.attr, + NULL }; -static int regulator_virtual_consumer_probe(struct platform_device *pdev) +static const struct attribute_group regulator_virtual_attr_group = { + .attrs = regulator_virtual_attributes, +}; + +static int __devinit regulator_virtual_probe(struct platform_device *pdev) { char *reg_id = pdev->dev.platform_data; struct virtual_consumer_data *drvdata; - int ret, i; + int ret; drvdata = kzalloc(sizeof(struct virtual_consumer_data), GFP_KERNEL); - if (drvdata == NULL) { + if (drvdata == NULL) return -ENOMEM; - } mutex_init(&drvdata->lock); @@ -299,13 +303,12 @@ static int regulator_virtual_consumer_probe(struct platform_device *pdev) goto err; } - for (i = 0; i < ARRAY_SIZE(attributes); i++) { - ret = device_create_file(&pdev->dev, attributes[i]); - if (ret != 0) { - dev_err(&pdev->dev, "Failed to create attr %d: %d\n", - i, ret); - goto err_regulator; - } + ret = sysfs_create_group(&pdev->dev.kobj, + ®ulator_virtual_attr_group); + if (ret != 0) { + dev_err(&pdev->dev, + "Failed to create attribute group: %d\n", ret); + goto err_regulator; } drvdata->mode = regulator_get_mode(drvdata->regulator); @@ -317,37 +320,36 @@ static int regulator_virtual_consumer_probe(struct platform_device *pdev) err_regulator: regulator_put(drvdata->regulator); err: - for (i = 0; i < ARRAY_SIZE(attributes); i++) - device_remove_file(&pdev->dev, attributes[i]); kfree(drvdata); return ret; } -static int regulator_virtual_consumer_remove(struct platform_device *pdev) +static int __devexit regulator_virtual_remove(struct platform_device *pdev) { struct virtual_consumer_data *drvdata = platform_get_drvdata(pdev); - int i; - for (i = 0; i < ARRAY_SIZE(attributes); i++) - device_remove_file(&pdev->dev, attributes[i]); + sysfs_remove_group(&pdev->dev.kobj, ®ulator_virtual_attr_group); + if (drvdata->enabled) regulator_disable(drvdata->regulator); regulator_put(drvdata->regulator); kfree(drvdata); + platform_set_drvdata(pdev, NULL); + return 0; } static struct platform_driver regulator_virtual_consumer_driver = { - .probe = regulator_virtual_consumer_probe, - .remove = regulator_virtual_consumer_remove, + .probe = regulator_virtual_probe, + .remove = __devexit_p(regulator_virtual_remove), .driver = { .name = "reg-virt-consumer", + .owner = THIS_MODULE, }, }; - static int __init regulator_virtual_consumer_init(void) { return platform_driver_register(®ulator_virtual_consumer_driver); -- cgit v1.2.3 From 98bf7c057b35eaf418ac063c4aba4f9f86220b09 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 23 Feb 2010 23:37:50 -0800 Subject: Regulators: ab3100 - fix probe and remove annotations Probe and remove methods should not be marked as __init/__exit but rather __devinit/__devexit so that the needed sections stay in memory in presence of CONFIG_HOTPLUG. This is needed even on non hotpluggable buses. Signed-off-by: Dmitry Torokhov Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/ab3100.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/ab3100.c b/drivers/regulator/ab3100.c index b349db4504b7..7de950959ed2 100644 --- a/drivers/regulator/ab3100.c +++ b/drivers/regulator/ab3100.c @@ -561,7 +561,7 @@ ab3100_regulator_desc[AB3100_NUM_REGULATORS] = { * for all the different regulators. */ -static int __init ab3100_regulators_probe(struct platform_device *pdev) +static int __devinit ab3100_regulators_probe(struct platform_device *pdev) { struct ab3100_platform_data *plfdata = pdev->dev.platform_data; struct ab3100 *ab3100 = platform_get_drvdata(pdev); @@ -641,7 +641,7 @@ static int __init ab3100_regulators_probe(struct platform_device *pdev) return 0; } -static int __exit ab3100_regulators_remove(struct platform_device *pdev) +static int __devexit ab3100_regulators_remove(struct platform_device *pdev) { int i; @@ -659,7 +659,7 @@ static struct platform_driver ab3100_regulators_driver = { .owner = THIS_MODULE, }, .probe = ab3100_regulators_probe, - .remove = __exit_p(ab3100_regulators_remove), + .remove = __devexit_p(ab3100_regulators_remove), }; static __init int ab3100_regulators_init(void) -- cgit v1.2.3 From 8ab3343dc61552cb8ad653e1013b1853cea9bea6 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 23 Feb 2010 23:37:55 -0800 Subject: Regulators: fixed - annotate probe and remove methods Add __devinit/__devexit markings to probe and remove methids of the driver, change types of variables containing boolean data to boolean, set up driver's owner field so we have proper sysfs link between driver and the module. Signed-off-by: Dmitry Torokhov Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/fixed.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/fixed.c b/drivers/regulator/fixed.c index a3d3bfc24b1f..d11f7622430b 100644 --- a/drivers/regulator/fixed.c +++ b/drivers/regulator/fixed.c @@ -32,8 +32,8 @@ struct fixed_voltage_data { int microvolts; int gpio; unsigned startup_delay; - unsigned enable_high:1; - unsigned is_enabled:1; + bool enable_high; + bool is_enabled; }; static int fixed_voltage_is_enabled(struct regulator_dev *dev) @@ -49,7 +49,7 @@ static int fixed_voltage_enable(struct regulator_dev *dev) if (gpio_is_valid(data->gpio)) { gpio_set_value_cansleep(data->gpio, data->enable_high); - data->is_enabled = 1; + data->is_enabled = true; } return 0; @@ -61,7 +61,7 @@ static int fixed_voltage_disable(struct regulator_dev *dev) if (gpio_is_valid(data->gpio)) { gpio_set_value_cansleep(data->gpio, !data->enable_high); - data->is_enabled = 0; + data->is_enabled = false; } return 0; @@ -101,7 +101,7 @@ static struct regulator_ops fixed_voltage_ops = { .list_voltage = fixed_voltage_list_voltage, }; -static int regulator_fixed_voltage_probe(struct platform_device *pdev) +static int __devinit reg_fixed_voltage_probe(struct platform_device *pdev) { struct fixed_voltage_config *config = pdev->dev.platform_data; struct fixed_voltage_data *drvdata; @@ -174,7 +174,7 @@ static int regulator_fixed_voltage_probe(struct platform_device *pdev) /* Regulator without GPIO control is considered * always enabled */ - drvdata->is_enabled = 1; + drvdata->is_enabled = true; } drvdata->dev = regulator_register(&drvdata->desc, &pdev->dev, @@ -202,7 +202,7 @@ err: return ret; } -static int regulator_fixed_voltage_remove(struct platform_device *pdev) +static int __devexit reg_fixed_voltage_remove(struct platform_device *pdev) { struct fixed_voltage_data *drvdata = platform_get_drvdata(pdev); @@ -216,10 +216,11 @@ static int regulator_fixed_voltage_remove(struct platform_device *pdev) } static struct platform_driver regulator_fixed_voltage_driver = { - .probe = regulator_fixed_voltage_probe, - .remove = regulator_fixed_voltage_remove, + .probe = reg_fixed_voltage_probe, + .remove = __devexit_p(reg_fixed_voltage_remove), .driver = { .name = "reg-fixed-voltage", + .owner = THIS_MODULE, }, }; -- cgit v1.2.3 From 24c29020bac8a35729e1f58270b3622abc2941a2 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 23 Feb 2010 23:38:01 -0800 Subject: Regulators: twl-regulator - mark probe function as __devinit Signed-off-by: Dmitry Torokhov Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/twl-regulator.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/regulator/twl-regulator.c b/drivers/regulator/twl-regulator.c index 5f394bb8701f..9729d760fb4d 100644 --- a/drivers/regulator/twl-regulator.c +++ b/drivers/regulator/twl-regulator.c @@ -531,7 +531,7 @@ static struct twlreg_info twl_regs[] = { TWL6030_FIXED_LDO(VUSB, 0x70, 3300, 18, 0, 0x21) }; -static int twlreg_probe(struct platform_device *pdev) +static int __devinit twlreg_probe(struct platform_device *pdev) { int i; struct twlreg_info *info; -- cgit v1.2.3 From 54d13ab1038911249fc5769efee87fed000623c0 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 23 Feb 2010 23:38:06 -0800 Subject: Regulators: tps65023-regulator - mark probe method as __devinit Also move error handling in probe() out of line and do not bother to reset fields in structures that are about to be freed. Signed-off-by: Dmitry Torokhov Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/tps65023-regulator.c | 35 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/tps65023-regulator.c b/drivers/regulator/tps65023-regulator.c index 07fda0a75adf..1f183543bdbd 100644 --- a/drivers/regulator/tps65023-regulator.c +++ b/drivers/regulator/tps65023-regulator.c @@ -457,8 +457,8 @@ static struct regulator_ops tps65023_ldo_ops = { .list_voltage = tps65023_ldo_list_voltage, }; -static -int tps_65023_probe(struct i2c_client *client, const struct i2c_device_id *id) +static int __devinit tps_65023_probe(struct i2c_client *client, + const struct i2c_device_id *id) { static int desc_id; const struct tps_info *info = (void *)id->driver_data; @@ -466,6 +466,7 @@ int tps_65023_probe(struct i2c_client *client, const struct i2c_device_id *id) struct regulator_dev *rdev; struct tps_pmic *tps; int i; + int error; if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) return -EIO; @@ -475,7 +476,6 @@ int tps_65023_probe(struct i2c_client *client, const struct i2c_device_id *id) * coming from the board-evm file. */ init_data = client->dev.platform_data; - if (!init_data) return -EIO; @@ -502,21 +502,12 @@ int tps_65023_probe(struct i2c_client *client, const struct i2c_device_id *id) /* Register the regulators */ rdev = regulator_register(&tps->desc[i], &client->dev, - init_data, tps); + init_data, tps); if (IS_ERR(rdev)) { dev_err(&client->dev, "failed to register %s\n", id->name); - - /* Unregister */ - while (i) - regulator_unregister(tps->rdev[--i]); - - tps->client = NULL; - - /* clear the client data in i2c */ - i2c_set_clientdata(client, NULL); - kfree(tps); - return PTR_ERR(rdev); + error = PTR_ERR(rdev); + goto fail; } /* Save regulator for cleanup */ @@ -526,6 +517,13 @@ int tps_65023_probe(struct i2c_client *client, const struct i2c_device_id *id) i2c_set_clientdata(client, tps); return 0; + + fail: + while (--i >= 0) + regulator_unregister(tps->rdev[i]); + + kfree(tps); + return error; } /** @@ -539,13 +537,12 @@ static int __devexit tps_65023_remove(struct i2c_client *client) struct tps_pmic *tps = i2c_get_clientdata(client); int i; + /* clear the client data in i2c */ + i2c_set_clientdata(client, NULL); + for (i = 0; i < TPS65023_NUM_REGULATOR; i++) regulator_unregister(tps->rdev[i]); - tps->client = NULL; - - /* clear the client data in i2c */ - i2c_set_clientdata(client, NULL); kfree(tps); return 0; -- cgit v1.2.3 From 56c23492b2266fcbe38f26a3de217902c70a895b Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 23 Feb 2010 23:38:12 -0800 Subject: Regulators: tps6507x-regulator - mark probe method as __devinit Also move error handling in probe() out of line and do not bother to reset fields in structures that are about to be freed. Signed-off-by: Dmitry Torokhov Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/tps6507x-regulator.c | 34 +++++++++++++++------------------- 1 file changed, 15 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/tps6507x-regulator.c b/drivers/regulator/tps6507x-regulator.c index f8a6dfbef751..c2a9539acd72 100644 --- a/drivers/regulator/tps6507x-regulator.c +++ b/drivers/regulator/tps6507x-regulator.c @@ -538,8 +538,8 @@ static struct regulator_ops tps6507x_ldo_ops = { .list_voltage = tps6507x_ldo_list_voltage, }; -static -int tps_6507x_probe(struct i2c_client *client, const struct i2c_device_id *id) +static int __devinit tps_6507x_probe(struct i2c_client *client, + const struct i2c_device_id *id) { static int desc_id; const struct tps_info *info = (void *)id->driver_data; @@ -547,6 +547,7 @@ int tps_6507x_probe(struct i2c_client *client, const struct i2c_device_id *id) struct regulator_dev *rdev; struct tps_pmic *tps; int i; + int error; if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) @@ -557,7 +558,6 @@ int tps_6507x_probe(struct i2c_client *client, const struct i2c_device_id *id) * coming from the board-evm file. */ init_data = client->dev.platform_data; - if (!init_data) return -EIO; @@ -586,18 +586,8 @@ int tps_6507x_probe(struct i2c_client *client, const struct i2c_device_id *id) if (IS_ERR(rdev)) { dev_err(&client->dev, "failed to register %s\n", id->name); - - /* Unregister */ - while (i) - regulator_unregister(tps->rdev[--i]); - - tps->client = NULL; - - /* clear the client data in i2c */ - i2c_set_clientdata(client, NULL); - - kfree(tps); - return PTR_ERR(rdev); + error = PTR_ERR(rdev); + goto fail; } /* Save regulator for cleanup */ @@ -607,6 +597,13 @@ int tps_6507x_probe(struct i2c_client *client, const struct i2c_device_id *id) i2c_set_clientdata(client, tps); return 0; + +fail: + while (--i >= 0) + regulator_unregister(tps->rdev[i]); + + kfree(tps); + return error; } /** @@ -620,13 +617,12 @@ static int __devexit tps_6507x_remove(struct i2c_client *client) struct tps_pmic *tps = i2c_get_clientdata(client); int i; + /* clear the client data in i2c */ + i2c_set_clientdata(client, NULL); + for (i = 0; i < TPS6507X_NUM_REGULATOR; i++) regulator_unregister(tps->rdev[i]); - tps->client = NULL; - - /* clear the client data in i2c */ - i2c_set_clientdata(client, NULL); kfree(tps); return 0; -- cgit v1.2.3 From ebbed04fe7f89c9cb00df32f7123bc1b84b456cb Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 23 Feb 2010 23:38:17 -0800 Subject: Regulators: lp3971 - fail if platform data was not supplied There is no point in completing probe if platform data is missing so let's abort loading early. Also, use kcalloc when allocating several instances of the same data structure and mark setup_regulators() as __devinit since it is only called from lp3971_i2c_probe() which is __devinit. Signed-off-by: Dmitry Torokhov Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/lp3971.c | 58 +++++++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 29 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/lp3971.c b/drivers/regulator/lp3971.c index 3ea639f29e95..f5532ed79272 100644 --- a/drivers/regulator/lp3971.c +++ b/drivers/regulator/lp3971.c @@ -431,20 +431,20 @@ static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val) return ret; } -static int setup_regulators(struct lp3971 *lp3971, - struct lp3971_platform_data *pdata) +static int __devinit setup_regulators(struct lp3971 *lp3971, + struct lp3971_platform_data *pdata) { int i, err; - int num_regulators = pdata->num_regulators; - lp3971->num_regulators = num_regulators; - lp3971->rdev = kzalloc(sizeof(struct regulator_dev *) * num_regulators, - GFP_KERNEL); + + lp3971->num_regulators = pdata->num_regulators; + lp3971->rdev = kcalloc(pdata->num_regulators, + sizeof(struct regulator_dev *), GFP_KERNEL); /* Instantiate the regulators */ - for (i = 0; i < num_regulators; i++) { - int id = pdata->regulators[i].id; - lp3971->rdev[i] = regulator_register(®ulators[id], - lp3971->dev, pdata->regulators[i].initdata, lp3971); + for (i = 0; i < pdata->num_regulators; i++) { + struct lp3971_regulator_subdev *reg = &pdata->regulators[i]; + lp3971->rdev[i] = regulator_register(®ulators[reg->id], + lp3971->dev, reg->initdata, lp3971); if (IS_ERR(lp3971->rdev[i])) { err = PTR_ERR(lp3971->rdev[i]); @@ -455,10 +455,10 @@ static int setup_regulators(struct lp3971 *lp3971, } return 0; + error: - for (i = 0; i < num_regulators; i++) - if (lp3971->rdev[i]) - regulator_unregister(lp3971->rdev[i]); + while (--i >= 0) + regulator_unregister(lp3971->rdev[i]); kfree(lp3971->rdev); lp3971->rdev = NULL; return err; @@ -472,15 +472,17 @@ static int __devinit lp3971_i2c_probe(struct i2c_client *i2c, int ret; u16 val; - lp3971 = kzalloc(sizeof(struct lp3971), GFP_KERNEL); - if (lp3971 == NULL) { - ret = -ENOMEM; - goto err; + if (!pdata) { + dev_dbg(&i2c->dev, "No platform init data supplied\n"); + return -ENODEV; } + lp3971 = kzalloc(sizeof(struct lp3971), GFP_KERNEL); + if (lp3971 == NULL) + return -ENOMEM; + lp3971->i2c = i2c; lp3971->dev = &i2c->dev; - i2c_set_clientdata(i2c, lp3971); mutex_init(&lp3971->io_lock); @@ -493,19 +495,15 @@ static int __devinit lp3971_i2c_probe(struct i2c_client *i2c, goto err_detect; } - if (pdata) { - ret = setup_regulators(lp3971, pdata); - if (ret < 0) - goto err_detect; - } else - dev_warn(lp3971->dev, "No platform init data supplied\n"); + ret = setup_regulators(lp3971, pdata); + if (ret < 0) + goto err_detect; + i2c_set_clientdata(i2c, lp3971); return 0; err_detect: - i2c_set_clientdata(i2c, NULL); kfree(lp3971); -err: return ret; } @@ -513,11 +511,13 @@ static int __devexit lp3971_i2c_remove(struct i2c_client *i2c) { struct lp3971 *lp3971 = i2c_get_clientdata(i2c); int i; + + i2c_set_clientdata(i2c, NULL); + for (i = 0; i < lp3971->num_regulators; i++) - if (lp3971->rdev[i]) - regulator_unregister(lp3971->rdev[i]); + regulator_unregister(lp3971->rdev[i]); + kfree(lp3971->rdev); - i2c_set_clientdata(i2c, NULL); kfree(lp3971); return 0; -- cgit v1.2.3 From bd88c9b285b76f329243d5c80960c23a04004043 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 23 Feb 2010 23:38:23 -0800 Subject: Regulators: max1586 - annotate probe and remove methods Signed-off-by: Dmitry Torokhov Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/max1586.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/max1586.c b/drivers/regulator/max1586.c index 2c082d3ef484..a49fc952c9a9 100644 --- a/drivers/regulator/max1586.c +++ b/drivers/regulator/max1586.c @@ -179,8 +179,8 @@ static struct regulator_desc max1586_reg[] = { }, }; -static int max1586_pmic_probe(struct i2c_client *client, - const struct i2c_device_id *i2c_id) +static int __devinit max1586_pmic_probe(struct i2c_client *client, + const struct i2c_device_id *i2c_id) { struct regulator_dev **rdev; struct max1586_platform_data *pdata = client->dev.platform_data; @@ -235,7 +235,7 @@ out: return ret; } -static int max1586_pmic_remove(struct i2c_client *client) +static int __devexit max1586_pmic_remove(struct i2c_client *client) { struct regulator_dev **rdev = i2c_get_clientdata(client); int i; @@ -257,9 +257,10 @@ MODULE_DEVICE_TABLE(i2c, max1586_id); static struct i2c_driver max1586_pmic_driver = { .probe = max1586_pmic_probe, - .remove = max1586_pmic_remove, + .remove = __devexit_p(max1586_pmic_remove), .driver = { .name = "max1586", + .owner = THIS_MODULE, }, .id_table = max1586_id, }; -- cgit v1.2.3 From 308f100f2ef8e8b9f65b0f3c2a1c7044ec0e65a5 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 23 Feb 2010 23:38:28 -0800 Subject: Regulators: max8660 - annotate probe and remove methods Signed-off-by: Dmitry Torokhov Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/max8660.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/max8660.c b/drivers/regulator/max8660.c index acc2fb7b6087..f12f1bb62138 100644 --- a/drivers/regulator/max8660.c +++ b/drivers/regulator/max8660.c @@ -345,8 +345,8 @@ static struct regulator_desc max8660_reg[] = { }, }; -static int max8660_probe(struct i2c_client *client, - const struct i2c_device_id *i2c_id) +static int __devinit max8660_probe(struct i2c_client *client, + const struct i2c_device_id *i2c_id) { struct regulator_dev **rdev; struct max8660_platform_data *pdata = client->dev.platform_data; @@ -354,7 +354,7 @@ static int max8660_probe(struct i2c_client *client, int boot_on, i, id, ret = -EINVAL; if (pdata->num_subdevs > MAX8660_V_END) { - dev_err(&client->dev, "Too much regulators found!\n"); + dev_err(&client->dev, "Too many regulators found!\n"); goto out; } @@ -462,7 +462,7 @@ out: return ret; } -static int max8660_remove(struct i2c_client *client) +static int __devexit max8660_remove(struct i2c_client *client) { struct regulator_dev **rdev = i2c_get_clientdata(client); int i; @@ -485,9 +485,10 @@ MODULE_DEVICE_TABLE(i2c, max8660_id); static struct i2c_driver max8660_driver = { .probe = max8660_probe, - .remove = max8660_remove, + .remove = __devexit_p(max8660_remove), .driver = { .name = "max8660", + .owner = THIS_MODULE, }, .id_table = max8660_id, }; -- cgit v1.2.3 From 6a74857d1b75e4f58f1a09472b972058499258a4 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 23 Feb 2010 23:38:33 -0800 Subject: Regulators: pcap-regulator - clean up driver data after removal It is a good tone to reset driver data after unbinding the device. Signed-off-by: Dmitry Torokhov Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/pcap-regulator.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/pcap-regulator.c b/drivers/regulator/pcap-regulator.c index 33d7d899e030..29d0566379ae 100644 --- a/drivers/regulator/pcap-regulator.c +++ b/drivers/regulator/pcap-regulator.c @@ -288,16 +288,18 @@ static int __devexit pcap_regulator_remove(struct platform_device *pdev) struct regulator_dev *rdev = platform_get_drvdata(pdev); regulator_unregister(rdev); + platform_set_drvdata(pdev, NULL); return 0; } static struct platform_driver pcap_regulator_driver = { .driver = { - .name = "pcap-regulator", + .name = "pcap-regulator", + .owner = THIS_MODULE, }, - .probe = pcap_regulator_probe, - .remove = __devexit_p(pcap_regulator_remove), + .probe = pcap_regulator_probe, + .remove = __devexit_p(pcap_regulator_remove), }; static int __init pcap_regulator_init(void) -- cgit v1.2.3 From eb66d565e8eb73ab0c471fd3dac822dc663fe8ea Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 23 Feb 2010 23:38:39 -0800 Subject: Regulators: wm831x-xxx - clean up driver data after removal It is a good tone to reset driver data after unbinding the device. Also set up drivers owner. Signed-off-by: Dmitry Torokhov Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/wm831x-dcdc.c | 12 ++++++++++++ drivers/regulator/wm831x-isink.c | 3 +++ drivers/regulator/wm831x-ldo.c | 5 +++++ 3 files changed, 20 insertions(+) (limited to 'drivers') diff --git a/drivers/regulator/wm831x-dcdc.c b/drivers/regulator/wm831x-dcdc.c index 0a6577577e8d..6e18e56d850b 100644 --- a/drivers/regulator/wm831x-dcdc.c +++ b/drivers/regulator/wm831x-dcdc.c @@ -600,6 +600,8 @@ static __devexit int wm831x_buckv_remove(struct platform_device *pdev) struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev); struct wm831x *wm831x = dcdc->wm831x; + platform_set_drvdata(pdev, NULL); + wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "HC"), dcdc); wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), dcdc); regulator_unregister(dcdc->regulator); @@ -615,6 +617,7 @@ static struct platform_driver wm831x_buckv_driver = { .remove = __devexit_p(wm831x_buckv_remove), .driver = { .name = "wm831x-buckv", + .owner = THIS_MODULE, }, }; @@ -769,6 +772,8 @@ static __devexit int wm831x_buckp_remove(struct platform_device *pdev) struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev); struct wm831x *wm831x = dcdc->wm831x; + platform_set_drvdata(pdev, NULL); + wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), dcdc); regulator_unregister(dcdc->regulator); kfree(dcdc); @@ -781,6 +786,7 @@ static struct platform_driver wm831x_buckp_driver = { .remove = __devexit_p(wm831x_buckp_remove), .driver = { .name = "wm831x-buckp", + .owner = THIS_MODULE, }, }; @@ -895,6 +901,8 @@ static __devexit int wm831x_boostp_remove(struct platform_device *pdev) struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev); struct wm831x *wm831x = dcdc->wm831x; + platform_set_drvdata(pdev, NULL); + wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), dcdc); regulator_unregister(dcdc->regulator); kfree(dcdc); @@ -907,6 +915,7 @@ static struct platform_driver wm831x_boostp_driver = { .remove = __devexit_p(wm831x_boostp_remove), .driver = { .name = "wm831x-boostp", + .owner = THIS_MODULE, }, }; @@ -979,6 +988,8 @@ static __devexit int wm831x_epe_remove(struct platform_device *pdev) { struct wm831x_dcdc *dcdc = platform_get_drvdata(pdev); + platform_set_drvdata(pdev, NULL); + regulator_unregister(dcdc->regulator); kfree(dcdc); @@ -990,6 +1001,7 @@ static struct platform_driver wm831x_epe_driver = { .remove = __devexit_p(wm831x_epe_remove), .driver = { .name = "wm831x-epe", + .owner = THIS_MODULE, }, }; diff --git a/drivers/regulator/wm831x-isink.c b/drivers/regulator/wm831x-isink.c index 48857008758c..ca0f6b6c384b 100644 --- a/drivers/regulator/wm831x-isink.c +++ b/drivers/regulator/wm831x-isink.c @@ -222,6 +222,8 @@ static __devexit int wm831x_isink_remove(struct platform_device *pdev) struct wm831x_isink *isink = platform_get_drvdata(pdev); struct wm831x *wm831x = isink->wm831x; + platform_set_drvdata(pdev, NULL); + wm831x_free_irq(wm831x, platform_get_irq(pdev, 0), isink); regulator_unregister(isink->regulator); @@ -235,6 +237,7 @@ static struct platform_driver wm831x_isink_driver = { .remove = __devexit_p(wm831x_isink_remove), .driver = { .name = "wm831x-isink", + .owner = THIS_MODULE, }, }; diff --git a/drivers/regulator/wm831x-ldo.c b/drivers/regulator/wm831x-ldo.c index 61e02ac2fda3..d2406c1519a1 100644 --- a/drivers/regulator/wm831x-ldo.c +++ b/drivers/regulator/wm831x-ldo.c @@ -371,6 +371,8 @@ static __devexit int wm831x_gp_ldo_remove(struct platform_device *pdev) struct wm831x_ldo *ldo = platform_get_drvdata(pdev); struct wm831x *wm831x = ldo->wm831x; + platform_set_drvdata(pdev, NULL); + wm831x_free_irq(wm831x, platform_get_irq_byname(pdev, "UV"), ldo); regulator_unregister(ldo->regulator); kfree(ldo); @@ -383,6 +385,7 @@ static struct platform_driver wm831x_gp_ldo_driver = { .remove = __devexit_p(wm831x_gp_ldo_remove), .driver = { .name = "wm831x-ldo", + .owner = THIS_MODULE, }, }; @@ -640,6 +643,7 @@ static struct platform_driver wm831x_aldo_driver = { .remove = __devexit_p(wm831x_aldo_remove), .driver = { .name = "wm831x-aldo", + .owner = THIS_MODULE, }, }; @@ -811,6 +815,7 @@ static struct platform_driver wm831x_alive_ldo_driver = { .remove = __devexit_p(wm831x_alive_ldo_remove), .driver = { .name = "wm831x-alive-ldo", + .owner = THIS_MODULE, }, }; -- cgit v1.2.3 From 598b3578ab9ee8e3eef322128485719668d8b93b Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 23 Feb 2010 23:38:44 -0800 Subject: Regulators: wm8994 - clean up driver data after removal It is a good tone to reset driver data after unbinding the device. Signed-off-by: Dmitry Torokhov Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/wm8994-regulator.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/wm8994-regulator.c b/drivers/regulator/wm8994-regulator.c index d09e018b3177..95454a4637b7 100644 --- a/drivers/regulator/wm8994-regulator.c +++ b/drivers/regulator/wm8994-regulator.c @@ -26,7 +26,7 @@ struct wm8994_ldo { int enable; - int is_enabled; + bool is_enabled; struct regulator_dev *regulator; struct wm8994 *wm8994; }; @@ -43,7 +43,7 @@ static int wm8994_ldo_enable(struct regulator_dev *rdev) return 0; gpio_set_value(ldo->enable, 1); - ldo->is_enabled = 1; + ldo->is_enabled = true; return 0; } @@ -57,7 +57,7 @@ static int wm8994_ldo_disable(struct regulator_dev *rdev) return -EINVAL; gpio_set_value(ldo->enable, 0); - ldo->is_enabled = 0; + ldo->is_enabled = false; return 0; } @@ -218,7 +218,7 @@ static __devinit int wm8994_ldo_probe(struct platform_device *pdev) ldo->wm8994 = wm8994; - ldo->is_enabled = 1; + ldo->is_enabled = true; if (pdata->ldo[id].enable && gpio_is_valid(pdata->ldo[id].enable)) { ldo->enable = pdata->ldo[id].enable; @@ -263,6 +263,8 @@ static __devexit int wm8994_ldo_remove(struct platform_device *pdev) { struct wm8994_ldo *ldo = platform_get_drvdata(pdev); + platform_set_drvdata(pdev, NULL); + regulator_unregister(ldo->regulator); if (gpio_is_valid(ldo->enable)) gpio_free(ldo->enable); @@ -276,6 +278,7 @@ static struct platform_driver wm8994_ldo_driver = { .remove = __devexit_p(wm8994_ldo_remove), .driver = { .name = "wm8994-ldo", + .owner = THIS_MODULE, }, }; -- cgit v1.2.3 From 1ad02bbce64e5226b0582af85df4e481e2f6b7b9 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Thu, 25 Feb 2010 01:55:37 -0800 Subject: Regulators: wm8400 - cleanup platform driver data handling On Wed, Feb 24, 2010 at 08:40:56PM +0000, Mark Brown wrote: > On Wed, Feb 24, 2010 at 11:21:26AM -0800, Dmitry Torokhov wrote: > > On Wed, Feb 24, 2010 at 07:14:03PM +0000, Mark Brown wrote: > > > > This doesn't help unless you also provide a way for users to obtain a > > > struct wm8400. > > > Why would they need it? Only code that creates instances of wm8400 needs > > to know the definition of the sturcture, the rest can simply pass the > > pointer around. > > > I guess there is disconnect between us and I do not see any users of > > wm8400_register_regulator() in linux-next... Is there another tree I > > could peek at? > > There are no users in mainline. This would be called by board specific > code from the init callback of the wm8400 - you'd need to pass that > callback the struct wm8400. > > In any case, this is clearly an unrelated change to whatever else you > were doing to the driver so should be split off into a separate patch, > but if this is being changed at all then it'd be much more sensible to > change it to use a more modern pattern which completely removes the > wm8400_register_regulator() function and just uses platform data. Fair enough, I removed the offending part, updated patch below. -- Dmitry regulator: wm8400 - cleanup platform driver data handling Driver data set by platform_set_drvdata() is for private use of the driver currently bound to teh device and not for use by parent, subsystem and anyone else. Signed-off-by: Dmitry Torokhov Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- drivers/regulator/wm8400-regulator.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/wm8400-regulator.c b/drivers/regulator/wm8400-regulator.c index d9a2c988c6e7..924c7eb29ee9 100644 --- a/drivers/regulator/wm8400-regulator.c +++ b/drivers/regulator/wm8400-regulator.c @@ -317,14 +317,17 @@ static struct regulator_desc regulators[] = { static int __devinit wm8400_regulator_probe(struct platform_device *pdev) { + struct wm8400 *wm8400 = container_of(pdev, struct wm8400, regulators[pdev->id]); struct regulator_dev *rdev; rdev = regulator_register(®ulators[pdev->id], &pdev->dev, - pdev->dev.platform_data, dev_get_drvdata(&pdev->dev)); + pdev->dev.platform_data, wm8400); if (IS_ERR(rdev)) return PTR_ERR(rdev); + platform_set_drvdata(pdev, rdev); + return 0; } @@ -332,6 +335,7 @@ static int __devexit wm8400_regulator_remove(struct platform_device *pdev) { struct regulator_dev *rdev = platform_get_drvdata(pdev); + platform_set_drvdata(pdev, NULL); regulator_unregister(rdev); return 0; @@ -370,7 +374,6 @@ int wm8400_register_regulator(struct device *dev, int reg, wm8400->regulators[reg].id = reg; wm8400->regulators[reg].dev.parent = dev; wm8400->regulators[reg].dev.platform_data = initdata; - dev_set_drvdata(&wm8400->regulators[reg].dev, wm8400); return platform_device_register(&wm8400->regulators[reg]); } -- cgit v1.2.3 From 98e1e0f07c3f1820b8ac424569ee9e9916d3665b Mon Sep 17 00:00:00 2001 From: Boaz Harrosh Date: Fri, 19 Feb 2010 11:46:24 -0800 Subject: [SCSI] libosd: Fix unchecked err return found by smatch Doing CHECK="smatch --two-passes gives: drivers/scsi/osd/osd_initiator.c +1435 osd_finalize_request warning: assignment to 'ret' was never used Which is an unchecked possible allocation failure, Fixed. Reported-by: Dan Carpenter Signed-off-by: Boaz Harrosh Signed-off-by: James Bottomley --- drivers/scsi/osd/osd_initiator.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/scsi/osd/osd_initiator.c b/drivers/scsi/osd/osd_initiator.c index 24223473f573..60de85091502 100644 --- a/drivers/scsi/osd/osd_initiator.c +++ b/drivers/scsi/osd/osd_initiator.c @@ -1433,6 +1433,10 @@ int osd_finalize_request(struct osd_request *or, cdbh->command_specific_options |= or->attributes_mode; if (or->attributes_mode == OSD_CDB_GET_ATTR_PAGE_SET_ONE) { ret = _osd_req_finalize_attr_page(or); + if (ret) { + OSD_DEBUG("_osd_req_finalize_attr_page failed\n"); + return ret; + } } else { /* TODO: I think that for the GET_ATTR command these 2 should * be reversed to keep them in execution order (for embeded -- cgit v1.2.3 From fac829fdcaf451a20106cbc468ff886466320956 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Wed, 3 Mar 2010 11:06:56 +0530 Subject: [SCSI] raid_attrs: fix dependency problems RAID attributes uses scsi_is_sdev_device() to gate some SCSI specific checking code. This causes two problems. Firstly if SCSI == n just defining scsi_is_sdev_device() to return false might not be enough to prevent gcc from emitting the code (and thus referring to undefined symbols), so this needs surrounding with an ifdef. Secondly, using scsi_is_sdev_device() when SCSI is either y or m gives a subtle problem in the m case: raid_attrs must also be m to use the symbol. Do the usual Kconfig jiggery-pokery to fix this. Reported-by: Randy Dunlap Signed-off-by: James Bottomley --- drivers/scsi/Kconfig | 6 ++++++ drivers/scsi/raid_class.c | 2 ++ 2 files changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index 9191d1ea6451..75f2336807cb 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -1,9 +1,15 @@ menu "SCSI device support" +config SCSI_MOD + tristate + default y if SCSI=n || SCSI=y + default m if SCSI=m + config RAID_ATTRS tristate "RAID Transport Class" default n depends on BLOCK + depends on SCSI_MOD ---help--- Provides RAID diff --git a/drivers/scsi/raid_class.c b/drivers/scsi/raid_class.c index bd88349b8526..2c146b44d95f 100644 --- a/drivers/scsi/raid_class.c +++ b/drivers/scsi/raid_class.c @@ -63,6 +63,7 @@ static int raid_match(struct attribute_container *cont, struct device *dev) * emulated RAID devices, so start with SCSI */ struct raid_internal *i = ac_to_raid_internal(cont); +#if defined(CONFIG_SCSI) || defined(CONFIG_SCSI_MODULE) if (scsi_is_sdev_device(dev)) { struct scsi_device *sdev = to_scsi_device(dev); @@ -71,6 +72,7 @@ static int raid_match(struct attribute_container *cont, struct device *dev) return i->f->is_raid(dev); } +#endif /* FIXME: look at other subsystems too */ return 0; } -- cgit v1.2.3 From 773d9e2d8dbf02cfaf65786cf9100eef02c9fda4 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 3 Mar 2010 11:47:42 -0700 Subject: ioat3: cleanup, don't enable DCA completion writes We already disallow raid operations while DCA is globally enabled, so having it locally enabled is a nop and confusing when reading the code. Signed-off-by: Dan Williams --- drivers/dma/ioat/dma_v3.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index 9908c9e94b2d..f270fa11275b 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -334,8 +334,7 @@ static void ioat3_cleanup_tasklet(unsigned long data) struct ioat2_dma_chan *ioat = (void *) data; ioat3_cleanup(ioat); - writew(IOAT_CHANCTRL_RUN | IOAT3_CHANCTRL_COMPL_DCA_EN, - ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); + writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); } static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) -- cgit v1.2.3 From b372ec2d900a5b50e47ef9e9624536ad146236be Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 3 Mar 2010 11:47:42 -0700 Subject: ioat3: use ioat2_quiesce() Replace open coded ioat2_quiesce() call in ioat3_restart_channel Signed-off-by: Dan Williams --- drivers/dma/ioat/dma_v3.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index f270fa11275b..bff48e8cffc4 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -341,16 +341,8 @@ static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) { struct ioat_chan_common *chan = &ioat->base; unsigned long phys_complete; - u32 status; - - status = ioat_chansts(chan); - if (is_ioat_active(status) || is_ioat_idle(status)) - ioat_suspend(chan); - while (is_ioat_active(status) || is_ioat_idle(status)) { - status = ioat_chansts(chan); - cpu_relax(); - } + ioat2_quiesce(chan, 0); if (ioat_cleanup_preamble(chan, &phys_complete)) __cleanup(ioat, phys_complete); -- cgit v1.2.3 From 281befa5592b0c5f9a3856b5666c62ac66d3d9ee Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 3 Mar 2010 11:47:43 -0700 Subject: ioat2: kill pending flag The pending == 2 case no longer exists in the driver so, we can use ioat2_ring_pending() outside the lock to determine if there might be any descriptors in the ring that the hardware has not seen. Signed-off-by: Dan Williams --- drivers/dma/ioat/dma_v2.c | 34 ++++++++++++---------------------- drivers/dma/ioat/dma_v2.h | 2 -- 2 files changed, 12 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 5f7a500e18d0..c6e4531fe524 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -51,48 +51,40 @@ MODULE_PARM_DESC(ioat_ring_max_alloc_order, void __ioat2_issue_pending(struct ioat2_dma_chan *ioat) { - void * __iomem reg_base = ioat->base.reg_base; + struct ioat_chan_common *chan = &ioat->base; - ioat->pending = 0; ioat->dmacount += ioat2_ring_pending(ioat); ioat->issued = ioat->head; /* make descriptor updates globally visible before notifying channel */ wmb(); - writew(ioat->dmacount, reg_base + IOAT_CHAN_DMACOUNT_OFFSET); - dev_dbg(to_dev(&ioat->base), + writew(ioat->dmacount, chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); + dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x count: %#x\n", __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount); } -void ioat2_issue_pending(struct dma_chan *chan) +void ioat2_issue_pending(struct dma_chan *c) { - struct ioat2_dma_chan *ioat = to_ioat2_chan(chan); + struct ioat2_dma_chan *ioat = to_ioat2_chan(c); - spin_lock_bh(&ioat->ring_lock); - if (ioat->pending == 1) + if (ioat2_ring_pending(ioat)) { + spin_lock_bh(&ioat->ring_lock); __ioat2_issue_pending(ioat); - spin_unlock_bh(&ioat->ring_lock); + spin_unlock_bh(&ioat->ring_lock); + } } /** * ioat2_update_pending - log pending descriptors * @ioat: ioat2+ channel * - * set pending to '1' unless pending is already set to '2', pending == 2 - * indicates that submission is temporarily blocked due to an in-flight - * reset. If we are already above the ioat_pending_level threshold then - * just issue pending. - * - * called with ring_lock held + * Check if the number of unsubmitted descriptors has exceeded the + * watermark. Called with ring_lock held */ static void ioat2_update_pending(struct ioat2_dma_chan *ioat) { - if (unlikely(ioat->pending == 2)) - return; - else if (ioat2_ring_pending(ioat) > ioat_pending_level) + if (ioat2_ring_pending(ioat) > ioat_pending_level) __ioat2_issue_pending(ioat); - else - ioat->pending = 1; } static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat) @@ -546,7 +538,6 @@ int ioat2_alloc_chan_resources(struct dma_chan *c) ioat->head = 0; ioat->issued = 0; ioat->tail = 0; - ioat->pending = 0; ioat->alloc_order = order; spin_unlock_bh(&ioat->ring_lock); @@ -815,7 +806,6 @@ void ioat2_free_chan_resources(struct dma_chan *c) chan->last_completion = 0; chan->completion_dma = 0; - ioat->pending = 0; ioat->dmacount = 0; } diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h index 3afad8da43cc..d211335b48f8 100644 --- a/drivers/dma/ioat/dma_v2.h +++ b/drivers/dma/ioat/dma_v2.h @@ -47,7 +47,6 @@ extern int ioat_ring_alloc_order; * @head: allocated index * @issued: hardware notification point * @tail: cleanup index - * @pending: lock free indicator for issued != head * @dmacount: identical to 'head' except for occasionally resetting to zero * @alloc_order: log2 of the number of allocated descriptors * @ring: software ring buffer implementation of hardware ring @@ -61,7 +60,6 @@ struct ioat2_dma_chan { u16 tail; u16 dmacount; u16 alloc_order; - int pending; struct ioat_ring_ent **ring; spinlock_t ring_lock; }; -- cgit v1.2.3 From b1e4594ba097634e9436cc4c6ba95f70a2d627ff Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 18 Jan 2010 01:38:00 -0500 Subject: switch infiniband uverbs to anon_inodes Signed-off-by: Al Viro --- drivers/infiniband/Kconfig | 1 + drivers/infiniband/core/uverbs.h | 2 +- drivers/infiniband/core/uverbs_cmd.c | 25 ++++++++--- drivers/infiniband/core/uverbs_main.c | 82 +++-------------------------------- 4 files changed, 29 insertions(+), 81 deletions(-) (limited to 'drivers') diff --git a/drivers/infiniband/Kconfig b/drivers/infiniband/Kconfig index dd0db67bf8d7..975adce5f40c 100644 --- a/drivers/infiniband/Kconfig +++ b/drivers/infiniband/Kconfig @@ -20,6 +20,7 @@ config INFINIBAND_USER_MAD config INFINIBAND_USER_ACCESS tristate "InfiniBand userspace access (verbs and CM)" + select ANON_INODES ---help--- Userspace InfiniBand access support. This enables the kernel side of userspace verbs and the userspace diff --git a/drivers/infiniband/core/uverbs.h b/drivers/infiniband/core/uverbs.h index b3ea9587dc80..0b3862080c0f 100644 --- a/drivers/infiniband/core/uverbs.h +++ b/drivers/infiniband/core/uverbs.h @@ -145,7 +145,7 @@ extern struct idr ib_uverbs_srq_idr; void idr_remove_uobj(struct idr *idp, struct ib_uobject *uobj); struct file *ib_uverbs_alloc_event_file(struct ib_uverbs_file *uverbs_file, - int is_async, int *fd); + int is_async); struct ib_uverbs_event_file *ib_uverbs_lookup_comp_file(int fd); void ib_uverbs_release_ucq(struct ib_uverbs_file *file, diff --git a/drivers/infiniband/core/uverbs_cmd.c b/drivers/infiniband/core/uverbs_cmd.c index 112d3970222a..f71cf138d674 100644 --- a/drivers/infiniband/core/uverbs_cmd.c +++ b/drivers/infiniband/core/uverbs_cmd.c @@ -301,10 +301,15 @@ ssize_t ib_uverbs_get_context(struct ib_uverbs_file *file, resp.num_comp_vectors = file->device->num_comp_vectors; - filp = ib_uverbs_alloc_event_file(file, 1, &resp.async_fd); + ret = get_unused_fd(); + if (ret < 0) + goto err_free; + resp.async_fd = ret; + + filp = ib_uverbs_alloc_event_file(file, 1); if (IS_ERR(filp)) { ret = PTR_ERR(filp); - goto err_free; + goto err_fd; } if (copy_to_user((void __user *) (unsigned long) cmd.response, @@ -332,9 +337,11 @@ ssize_t ib_uverbs_get_context(struct ib_uverbs_file *file, return in_len; err_file: - put_unused_fd(resp.async_fd); fput(filp); +err_fd: + put_unused_fd(resp.async_fd); + err_free: ibdev->dealloc_ucontext(ucontext); @@ -715,6 +722,7 @@ ssize_t ib_uverbs_create_comp_channel(struct ib_uverbs_file *file, struct ib_uverbs_create_comp_channel cmd; struct ib_uverbs_create_comp_channel_resp resp; struct file *filp; + int ret; if (out_len < sizeof resp) return -ENOSPC; @@ -722,9 +730,16 @@ ssize_t ib_uverbs_create_comp_channel(struct ib_uverbs_file *file, if (copy_from_user(&cmd, buf, sizeof cmd)) return -EFAULT; - filp = ib_uverbs_alloc_event_file(file, 0, &resp.fd); - if (IS_ERR(filp)) + ret = get_unused_fd(); + if (ret < 0) + return ret; + resp.fd = ret; + + filp = ib_uverbs_alloc_event_file(file, 0); + if (IS_ERR(filp)) { + put_unused_fd(resp.fd); return PTR_ERR(filp); + } if (copy_to_user((void __user *) (unsigned long) cmd.response, &resp, sizeof resp)) { diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c index 5f284ffd430e..810f277739e2 100644 --- a/drivers/infiniband/core/uverbs_main.c +++ b/drivers/infiniband/core/uverbs_main.c @@ -41,8 +41,8 @@ #include #include #include +#include #include -#include #include #include @@ -53,8 +53,6 @@ MODULE_AUTHOR("Roland Dreier"); MODULE_DESCRIPTION("InfiniBand userspace verbs access"); MODULE_LICENSE("Dual BSD/GPL"); -#define INFINIBANDEVENTFS_MAGIC 0x49426576 /* "IBev" */ - enum { IB_UVERBS_MAJOR = 231, IB_UVERBS_BASE_MINOR = 192, @@ -111,8 +109,6 @@ static ssize_t (*uverbs_cmd_table[])(struct ib_uverbs_file *file, [IB_USER_VERBS_CMD_DESTROY_SRQ] = ib_uverbs_destroy_srq, }; -static struct vfsmount *uverbs_event_mnt; - static void ib_uverbs_add_one(struct ib_device *device); static void ib_uverbs_remove_one(struct ib_device *device); @@ -489,12 +485,10 @@ void ib_uverbs_event_handler(struct ib_event_handler *handler, } struct file *ib_uverbs_alloc_event_file(struct ib_uverbs_file *uverbs_file, - int is_async, int *fd) + int is_async) { struct ib_uverbs_event_file *ev_file; - struct path path; struct file *filp; - int ret; ev_file = kmalloc(sizeof *ev_file, GFP_KERNEL); if (!ev_file) @@ -509,38 +503,12 @@ struct file *ib_uverbs_alloc_event_file(struct ib_uverbs_file *uverbs_file, ev_file->is_async = is_async; ev_file->is_closed = 0; - *fd = get_unused_fd(); - if (*fd < 0) { - ret = *fd; - goto err; - } - - /* - * fops_get() can't fail here, because we're coming from a - * system call on a uverbs file, which will already have a - * module reference. - */ - path.mnt = uverbs_event_mnt; - path.dentry = uverbs_event_mnt->mnt_root; - path_get(&path); - filp = alloc_file(&path, FMODE_READ, fops_get(&uverbs_event_fops)); - if (!filp) { - ret = -ENFILE; - goto err_fd; - } - - filp->private_data = ev_file; + filp = anon_inode_getfile("[infinibandevent]", &uverbs_event_fops, + ev_file, O_RDONLY); + if (IS_ERR(filp)) + kfree(ev_file); return filp; - -err_fd: - fops_put(&uverbs_event_fops); - path_put(&path); - put_unused_fd(*fd); - -err: - kfree(ev_file); - return ERR_PTR(ret); } /* @@ -825,21 +793,6 @@ static void ib_uverbs_remove_one(struct ib_device *device) kfree(uverbs_dev); } -static int uverbs_event_get_sb(struct file_system_type *fs_type, int flags, - const char *dev_name, void *data, - struct vfsmount *mnt) -{ - return get_sb_pseudo(fs_type, "infinibandevent:", NULL, - INFINIBANDEVENTFS_MAGIC, mnt); -} - -static struct file_system_type uverbs_event_fs = { - /* No owner field so module can be unloaded */ - .name = "infinibandeventfs", - .get_sb = uverbs_event_get_sb, - .kill_sb = kill_litter_super -}; - static int __init ib_uverbs_init(void) { int ret; @@ -864,33 +817,14 @@ static int __init ib_uverbs_init(void) goto out_class; } - ret = register_filesystem(&uverbs_event_fs); - if (ret) { - printk(KERN_ERR "user_verbs: couldn't register infinibandeventfs\n"); - goto out_class; - } - - uverbs_event_mnt = kern_mount(&uverbs_event_fs); - if (IS_ERR(uverbs_event_mnt)) { - ret = PTR_ERR(uverbs_event_mnt); - printk(KERN_ERR "user_verbs: couldn't mount infinibandeventfs\n"); - goto out_fs; - } - ret = ib_register_client(&uverbs_client); if (ret) { printk(KERN_ERR "user_verbs: couldn't register client\n"); - goto out_mnt; + goto out_class; } return 0; -out_mnt: - mntput(uverbs_event_mnt); - -out_fs: - unregister_filesystem(&uverbs_event_fs); - out_class: class_destroy(uverbs_class); @@ -904,8 +838,6 @@ out: static void __exit ib_uverbs_cleanup(void) { ib_unregister_client(&uverbs_client); - mntput(uverbs_event_mnt); - unregister_filesystem(&uverbs_event_fs); class_destroy(uverbs_class); unregister_chrdev_region(IB_UVERBS_BASE_DEV, IB_UVERBS_MAX_DEVICES); idr_destroy(&ib_uverbs_pd_idr); -- cgit v1.2.3 From 2ecdc82ef0b03e67ce5ecee79d0d108177a704df Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 26 Jan 2010 17:27:20 +0100 Subject: kill unused invalidate_inode_pages helper No one is calling this anymore as everyone has switched to invalidate_mapping_pages long time ago. Also update a few references to it in comments. nfs has two more, but I can't easily figure what they are actually referring to, so I left them as-is. Signed-off-by: Christoph Hellwig Signed-off-by: Al Viro --- drivers/usb/gadget/f_mass_storage.c | 2 +- drivers/usb/gadget/file_storage.c | 2 +- include/linux/fs.h | 6 ------ mm/filemap.c | 2 +- 4 files changed, 3 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index a37640eba434..77fcd1b697e8 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -1041,7 +1041,7 @@ static void invalidate_sub(struct fsg_lun *curlun) unsigned long rc; rc = invalidate_mapping_pages(inode->i_mapping, 0, -1); - VLDBG(curlun, "invalidate_inode_pages -> %ld\n", rc); + VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc); } static int do_verify(struct fsg_common *common) diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c index 29dfb0277ffb..7dcdbda49cac 100644 --- a/drivers/usb/gadget/file_storage.c +++ b/drivers/usb/gadget/file_storage.c @@ -1448,7 +1448,7 @@ static void invalidate_sub(struct fsg_lun *curlun) unsigned long rc; rc = invalidate_mapping_pages(inode->i_mapping, 0, -1); - VLDBG(curlun, "invalidate_inode_pages -> %ld\n", rc); + VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc); } static int do_verify(struct fsg_dev *fsg) diff --git a/include/linux/fs.h b/include/linux/fs.h index aa76dae673eb..d443c9dd3caa 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -2058,12 +2058,6 @@ extern int invalidate_inodes(struct super_block *); unsigned long invalidate_mapping_pages(struct address_space *mapping, pgoff_t start, pgoff_t end); -static inline unsigned long __deprecated -invalidate_inode_pages(struct address_space *mapping) -{ - return invalidate_mapping_pages(mapping, 0, ~0UL); -} - static inline void invalidate_remote_inode(struct inode *inode) { if (S_ISREG(inode->i_mode) || S_ISDIR(inode->i_mode) || diff --git a/mm/filemap.c b/mm/filemap.c index 698ea80f2102..148b52a5bb7e 100644 --- a/mm/filemap.c +++ b/mm/filemap.c @@ -1117,7 +1117,7 @@ readpage: if (!PageUptodate(page)) { if (page->mapping == NULL) { /* - * invalidate_inode_pages got it + * invalidate_mapping_pages got it */ unlock_page(page); page_cache_release(page); -- cgit v1.2.3 From 4fa004373133ece3d9b1c0a7e243b0e53760b165 Mon Sep 17 00:00:00 2001 From: Sujith Date: Mon, 1 Mar 2010 14:42:57 +0530 Subject: mac80211: Fix HT rate control configuration Handling HT configuration changes involved setting the channel with the new HT parameters and then issuing a rate_update() notification to the driver. This behavior changed after the off-channel changes. Now, the channel is not updated with the new HT params in enable_ht() - instead, it is now done when the scan work terminates. This results in the driver depending on stale information, defaulting to non-HT mode always. Fix this by passing the new channel type to the driver. Cc: stable@kernel.org Signed-off-by: Sujith Signed-off-by: John W. Linville --- drivers/net/wireless/ath/ath9k/rc.c | 6 +++--- include/net/mac80211.h | 3 ++- net/mac80211/mlme.c | 3 ++- net/mac80211/rate.h | 5 +++-- 4 files changed, 10 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c index ac34a055c713..0e79e58cf4c9 100644 --- a/drivers/net/wireless/ath/ath9k/rc.c +++ b/drivers/net/wireless/ath/ath9k/rc.c @@ -1323,7 +1323,7 @@ static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband, static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband, struct ieee80211_sta *sta, void *priv_sta, - u32 changed) + u32 changed, enum nl80211_channel_type oper_chan_type) { struct ath_softc *sc = priv; struct ath_rate_priv *ath_rc_priv = priv_sta; @@ -1340,8 +1340,8 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband, if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) return; - if (sc->hw->conf.channel_type == NL80211_CHAN_HT40MINUS || - sc->hw->conf.channel_type == NL80211_CHAN_HT40PLUS) + if (oper_chan_type == NL80211_CHAN_HT40MINUS || + oper_chan_type == NL80211_CHAN_HT40PLUS) oper_cw40 = true; oper_sgi40 = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? diff --git a/include/net/mac80211.h b/include/net/mac80211.h index 80eb7cc42ce9..45d7d44d7cbe 100644 --- a/include/net/mac80211.h +++ b/include/net/mac80211.h @@ -2426,7 +2426,8 @@ struct rate_control_ops { struct ieee80211_sta *sta, void *priv_sta); void (*rate_update)(void *priv, struct ieee80211_supported_band *sband, struct ieee80211_sta *sta, - void *priv_sta, u32 changed); + void *priv_sta, u32 changed, + enum nl80211_channel_type oper_chan_type); void (*free_sta)(void *priv, struct ieee80211_sta *sta, void *priv_sta); diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c index 5a268761e4c5..0ab284c32135 100644 --- a/net/mac80211/mlme.c +++ b/net/mac80211/mlme.c @@ -177,7 +177,8 @@ static u32 ieee80211_enable_ht(struct ieee80211_sub_if_data *sdata, sta = sta_info_get(sdata, bssid); if (sta) rate_control_rate_update(local, sband, sta, - IEEE80211_RC_HT_CHANGED); + IEEE80211_RC_HT_CHANGED, + local->oper_channel_type); rcu_read_unlock(); } diff --git a/net/mac80211/rate.h b/net/mac80211/rate.h index b6108bca96d4..065a96190e32 100644 --- a/net/mac80211/rate.h +++ b/net/mac80211/rate.h @@ -66,7 +66,8 @@ static inline void rate_control_rate_init(struct sta_info *sta) static inline void rate_control_rate_update(struct ieee80211_local *local, struct ieee80211_supported_band *sband, - struct sta_info *sta, u32 changed) + struct sta_info *sta, u32 changed, + enum nl80211_channel_type oper_chan_type) { struct rate_control_ref *ref = local->rate_ctrl; struct ieee80211_sta *ista = &sta->sta; @@ -74,7 +75,7 @@ static inline void rate_control_rate_update(struct ieee80211_local *local, if (ref && ref->ops->rate_update) ref->ops->rate_update(ref->priv, sband, ista, - priv_sta, changed); + priv_sta, changed, oper_chan_type); } static inline void *rate_control_alloc_sta(struct rate_control_ref *ref, -- cgit v1.2.3 From 31f66be44a657a14e0ab3536e4877c66c9ce031e Mon Sep 17 00:00:00 2001 From: Helmut Schaa Date: Wed, 3 Mar 2010 17:42:55 +0100 Subject: rt2x00: Export rt2x00soc_probe from rt2x00soc Export rt2x00soc_probe from rt2x00soc as it is used in rt2800pci. Otherwise loading rt2800pci gives "rt2800pci: Unknown symbol rt2x00soc_probe". Signed-off-by: Helmut Schaa Acked-by: Gertjan van Wingerde Signed-off-by: John W. Linville --- drivers/net/wireless/rt2x00/rt2x00soc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/net/wireless/rt2x00/rt2x00soc.c b/drivers/net/wireless/rt2x00/rt2x00soc.c index 4efdc96010f6..111c0ff5c6c7 100644 --- a/drivers/net/wireless/rt2x00/rt2x00soc.c +++ b/drivers/net/wireless/rt2x00/rt2x00soc.c @@ -112,6 +112,7 @@ exit_free_device: return retval; } +EXPORT_SYMBOL_GPL(rt2x00soc_probe); int rt2x00soc_remove(struct platform_device *pdev) { -- cgit v1.2.3 From 90454a28d2e825e13f4a0334e017a438e4ccfc8a Mon Sep 17 00:00:00 2001 From: Bruce Beare Date: Fri, 20 Nov 2009 15:46:09 -0800 Subject: Staging: comedi: pcmad: Cleanup: code indent warning messages use tabs instead of leading spaces Signed-off-by: Bruce Beare Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcmad.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcmad.c b/drivers/staging/comedi/drivers/pcmad.c index acac67090810..202bfd482992 100644 --- a/drivers/staging/comedi/drivers/pcmad.c +++ b/drivers/staging/comedi/drivers/pcmad.c @@ -34,11 +34,11 @@ Configuration options: [0] - I/O port base [1] - unused [2] - Analog input reference - 0 = single ended - 1 = differential + 0 = single ended + 1 = differential [3] - Analog input encoding (must match jumpers) - 0 = straight binary - 1 = two's complement + 0 = straight binary + 1 = two's complement */ #include -- cgit v1.2.3 From 71a74bd951dd292dcda623539fa7b45005d72436 Mon Sep 17 00:00:00 2001 From: Bruce Beare Date: Fri, 20 Nov 2009 15:46:10 -0800 Subject: Staging: comedi: pcmad: Cleanup: Remove unneeded braces Signed-off-by: Bruce Beare Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcmad.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcmad.c b/drivers/staging/comedi/drivers/pcmad.c index 202bfd482992..787aea28afb8 100644 --- a/drivers/staging/comedi/drivers/pcmad.c +++ b/drivers/staging/comedi/drivers/pcmad.c @@ -113,9 +113,8 @@ static int pcmad_ai_insn_read(struct comedi_device *dev, data[n] = inb(dev->iobase + PCMAD_LSB); data[n] |= (inb(dev->iobase + PCMAD_MSB) << 8); - if (devpriv->twos_comp) { + if (devpriv->twos_comp) data[n] ^= (1 << (this_board->n_ai_bits - 1)); - } } return n; @@ -168,9 +167,8 @@ static int pcmad_detach(struct comedi_device *dev) { printk("comedi%d: pcmad: remove\n", dev->minor); - if (dev->irq) { + if (dev->irq) free_irq(dev->irq, dev); - } if (dev->iobase) release_region(dev->iobase, PCMAD_SIZE); -- cgit v1.2.3 From fcc55b309fc0d037b5d435712cf70589c6a0c7be Mon Sep 17 00:00:00 2001 From: Bruce Beare Date: Fri, 20 Nov 2009 15:46:11 -0800 Subject: Staging: comedi: pcmad: [PATCH 3/3] cleanup printk() warnings cleanup printk() warnings for including the facility level. cleanup add a printk("\n") to terminate the print for the non-error case. Signed-off-by: Bruce Beare Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcmad.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcmad.c b/drivers/staging/comedi/drivers/pcmad.c index 787aea28afb8..44ed777599c4 100644 --- a/drivers/staging/comedi/drivers/pcmad.c +++ b/drivers/staging/comedi/drivers/pcmad.c @@ -134,11 +134,12 @@ static int pcmad_attach(struct comedi_device *dev, struct comedi_devconfig *it) unsigned long iobase; iobase = it->options[0]; - printk("comedi%d: pcmad: 0x%04lx ", dev->minor, iobase); + printk(KERN_NOTICE "comedi%d: pcmad: 0x%04lx ", dev->minor, iobase); if (!request_region(iobase, PCMAD_SIZE, "pcmad")) { - printk("I/O port conflict\n"); + printk(KERN_CONT "I/O port conflict\n"); return -EIO; } + printk(KERN_CONT "\n"); dev->iobase = iobase; ret = alloc_subdevices(dev, 1); @@ -165,7 +166,7 @@ static int pcmad_attach(struct comedi_device *dev, struct comedi_devconfig *it) static int pcmad_detach(struct comedi_device *dev) { - printk("comedi%d: pcmad: remove\n", dev->minor); + printk(KERN_NOTICE "comedi%d: pcmad: remove\n", dev->minor); if (dev->irq) free_irq(dev->irq, dev); -- cgit v1.2.3 From e79753edf88d858a3783c946c12cc4726f6590f6 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Sat, 21 Nov 2009 09:16:12 +0100 Subject: Staging: dream: add missing include files Add missing files/includes neccessary for Dream compilation. Mark flash support as broken -- it is not present on released Dream, anyway. Signed-off-by: Pavel Machek Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dream/camera/Kconfig | 2 +- drivers/staging/dream/camera/Makefile | 1 + drivers/staging/dream/include/linux/android_pmem.h | 80 ++ drivers/staging/dream/include/linux/gpio_event.h | 154 ++++ drivers/staging/dream/include/linux/msm_adsp.h | 84 ++ drivers/staging/dream/include/linux/msm_audio.h | 115 +++ .../staging/dream/include/linux/msm_rpcrouter.h | 47 ++ drivers/staging/dream/include/linux/wakelock.h | 91 ++ drivers/staging/dream/include/mach/camera.h | 279 +++++++ drivers/staging/dream/include/mach/msm_adsp.h | 112 +++ drivers/staging/dream/include/mach/msm_rpcrouter.h | 179 ++++ drivers/staging/dream/include/mach/msm_smd.h | 107 +++ .../dream/include/mach/qdsp5/qdsp5audplaycmdi.h | 94 +++ .../dream/include/mach/qdsp5/qdsp5audplaymsg.h | 70 ++ .../dream/include/mach/qdsp5/qdsp5audppcmdi.h | 914 +++++++++++++++++++++ .../dream/include/mach/qdsp5/qdsp5audppmsg.h | 318 +++++++ .../dream/include/mach/qdsp5/qdsp5audpreproccmdi.h | 256 ++++++ .../dream/include/mach/qdsp5/qdsp5audpreprocmsg.h | 85 ++ .../dream/include/mach/qdsp5/qdsp5audreccmdi.h | 176 ++++ .../dream/include/mach/qdsp5/qdsp5audrecmsg.h | 127 +++ .../dream/include/mach/qdsp5/qdsp5jpegcmdi.h | 376 +++++++++ .../dream/include/mach/qdsp5/qdsp5jpegmsg.h | 177 ++++ .../dream/include/mach/qdsp5/qdsp5lpmcmdi.h | 82 ++ .../staging/dream/include/mach/qdsp5/qdsp5lpmmsg.h | 80 ++ .../dream/include/mach/qdsp5/qdsp5vdeccmdi.h | 235 ++++++ .../dream/include/mach/qdsp5/qdsp5vdecmsg.h | 107 +++ .../dream/include/mach/qdsp5/qdsp5venccmdi.h | 212 +++++ .../dream/include/mach/qdsp5/qdsp5vfecmdi.h | 910 ++++++++++++++++++++ .../staging/dream/include/mach/qdsp5/qdsp5vfemsg.h | 290 +++++++ drivers/staging/dream/include/media/msm_camera.h | 388 +++++++++ drivers/staging/dream/qdsp5/Makefile | 1 + drivers/staging/dream/smd/Makefile | 1 + 32 files changed, 6149 insertions(+), 1 deletion(-) create mode 100644 drivers/staging/dream/include/linux/android_pmem.h create mode 100644 drivers/staging/dream/include/linux/gpio_event.h create mode 100644 drivers/staging/dream/include/linux/msm_adsp.h create mode 100644 drivers/staging/dream/include/linux/msm_audio.h create mode 100644 drivers/staging/dream/include/linux/msm_rpcrouter.h create mode 100644 drivers/staging/dream/include/linux/wakelock.h create mode 100644 drivers/staging/dream/include/mach/camera.h create mode 100644 drivers/staging/dream/include/mach/msm_adsp.h create mode 100644 drivers/staging/dream/include/mach/msm_rpcrouter.h create mode 100644 drivers/staging/dream/include/mach/msm_smd.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5audplaycmdi.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5audplaymsg.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5audppcmdi.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5audppmsg.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5audpreproccmdi.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5audpreprocmsg.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5audreccmdi.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5audrecmsg.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5jpegcmdi.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5jpegmsg.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5lpmcmdi.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5lpmmsg.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5vdeccmdi.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5vdecmsg.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5venccmdi.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5vfecmdi.h create mode 100644 drivers/staging/dream/include/mach/qdsp5/qdsp5vfemsg.h create mode 100644 drivers/staging/dream/include/media/msm_camera.h (limited to 'drivers') diff --git a/drivers/staging/dream/camera/Kconfig b/drivers/staging/dream/camera/Kconfig index 0a3e903b3363..bfb6d241d807 100644 --- a/drivers/staging/dream/camera/Kconfig +++ b/drivers/staging/dream/camera/Kconfig @@ -15,7 +15,7 @@ config MSM_CAMERA_DEBUG config MSM_CAMERA_FLASH bool "Qualcomm MSM camera flash support" - depends on MSM_CAMERA + depends on MSM_CAMERA && BROKEN ---help--- Enable support for LED flash for msm camera diff --git a/drivers/staging/dream/camera/Makefile b/drivers/staging/dream/camera/Makefile index 4429ae5fcafd..db228d7d1136 100644 --- a/drivers/staging/dream/camera/Makefile +++ b/drivers/staging/dream/camera/Makefile @@ -1,3 +1,4 @@ +EXTRA_CFLAGS=-Idrivers/staging/dream/include obj-$(CONFIG_MT9T013) += mt9t013.o mt9t013_reg.o obj-$(CONFIG_MT9D112) += mt9d112.o mt9d112_reg.o obj-$(CONFIG_MT9P012) += mt9p012_fox.o mt9p012_reg.o diff --git a/drivers/staging/dream/include/linux/android_pmem.h b/drivers/staging/dream/include/linux/android_pmem.h new file mode 100644 index 000000000000..2fc05d7d335b --- /dev/null +++ b/drivers/staging/dream/include/linux/android_pmem.h @@ -0,0 +1,80 @@ +/* drivers/staging/dream/include/linux/android_pmem.h + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _ANDROID_PMEM_H_ +#define _ANDROID_PMEM_H_ + +#define PMEM_IOCTL_MAGIC 'p' +#define PMEM_GET_PHYS _IOW(PMEM_IOCTL_MAGIC, 1, unsigned int) +#define PMEM_MAP _IOW(PMEM_IOCTL_MAGIC, 2, unsigned int) +#define PMEM_GET_SIZE _IOW(PMEM_IOCTL_MAGIC, 3, unsigned int) +#define PMEM_UNMAP _IOW(PMEM_IOCTL_MAGIC, 4, unsigned int) +/* This ioctl will allocate pmem space, backing the file, it will fail + * if the file already has an allocation, pass it the len as the argument + * to the ioctl */ +#define PMEM_ALLOCATE _IOW(PMEM_IOCTL_MAGIC, 5, unsigned int) +/* This will connect a one pmem file to another, pass the file that is already + * backed in memory as the argument to the ioctl + */ +#define PMEM_CONNECT _IOW(PMEM_IOCTL_MAGIC, 6, unsigned int) +/* Returns the total size of the pmem region it is sent to as a pmem_region + * struct (with offset set to 0). + */ +#define PMEM_GET_TOTAL_SIZE _IOW(PMEM_IOCTL_MAGIC, 7, unsigned int) +/* Revokes gpu registers and resets the gpu. Pass a pointer to the + * start of the mapped gpu regs (the vaddr returned by mmap) as the argument. + */ +#define HW3D_REVOKE_GPU _IOW(PMEM_IOCTL_MAGIC, 8, unsigned int) +#define HW3D_GRANT_GPU _IOW(PMEM_IOCTL_MAGIC, 9, unsigned int) +#define HW3D_WAIT_FOR_INTERRUPT _IOW(PMEM_IOCTL_MAGIC, 10, unsigned int) + +int get_pmem_file(int fd, unsigned long *start, unsigned long *vstart, + unsigned long *end, struct file **filp); +int get_pmem_user_addr(struct file *file, unsigned long *start, + unsigned long *end); +void put_pmem_file(struct file* file); +void flush_pmem_file(struct file *file, unsigned long start, unsigned long len); + +struct android_pmem_platform_data +{ + const char* name; + /* starting physical address of memory region */ + unsigned long start; + /* size of memory region */ + unsigned long size; + /* set to indicate the region should not be managed with an allocator */ + unsigned no_allocator; + /* set to indicate maps of this region should be cached, if a mix of + * cached and uncached is desired, set this and open the device with + * O_SYNC to get an uncached region */ + unsigned cached; + /* The MSM7k has bits to enable a write buffer in the bus controller*/ + unsigned buffered; +}; + +struct pmem_region { + unsigned long offset; + unsigned long len; +}; + +int pmem_setup(struct android_pmem_platform_data *pdata, + long (*ioctl)(struct file *, unsigned int, unsigned long), + int (*release)(struct inode *, struct file *)); + +int pmem_remap(struct pmem_region *region, struct file *file, + unsigned operation); + +#endif //_ANDROID_PPP_H_ + diff --git a/drivers/staging/dream/include/linux/gpio_event.h b/drivers/staging/dream/include/linux/gpio_event.h new file mode 100644 index 000000000000..ffc5da392ad7 --- /dev/null +++ b/drivers/staging/dream/include/linux/gpio_event.h @@ -0,0 +1,154 @@ +/* drivers/staging/dream/include/linux/gpio_event.h + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_GPIO_EVENT_H +#define _LINUX_GPIO_EVENT_H + +#include + +enum { + GPIO_EVENT_FUNC_UNINIT = 0x0, + GPIO_EVENT_FUNC_INIT = 0x1, + GPIO_EVENT_FUNC_SUSPEND = 0x2, + GPIO_EVENT_FUNC_RESUME = 0x3, +}; +struct gpio_event_info { + int (*func)(struct input_dev *input_dev, + struct gpio_event_info *info, + void **data, int func); + int (*event)(struct input_dev *input_dev, + struct gpio_event_info *info, + void **data, unsigned int type, + unsigned int code, int value); /* out events */ +}; + +struct gpio_event_platform_data { + const char *name; + struct gpio_event_info **info; + size_t info_count; + int (*power)(const struct gpio_event_platform_data *pdata, bool on); +}; + +#define GPIO_EVENT_DEV_NAME "gpio-event" + +/* Key matrix */ + +enum gpio_event_matrix_flags { + /* unset: drive active output low, set: drive active output high */ + GPIOKPF_ACTIVE_HIGH = 1U << 0, + GPIOKPF_DEBOUNCE = 1U << 1, + GPIOKPF_REMOVE_SOME_PHANTOM_KEYS = 1U << 2, + GPIOKPF_REMOVE_PHANTOM_KEYS = GPIOKPF_REMOVE_SOME_PHANTOM_KEYS | + GPIOKPF_DEBOUNCE, + GPIOKPF_DRIVE_INACTIVE = 1U << 3, + GPIOKPF_LEVEL_TRIGGERED_IRQ = 1U << 4, + GPIOKPF_PRINT_UNMAPPED_KEYS = 1U << 16, + GPIOKPF_PRINT_MAPPED_KEYS = 1U << 17, + GPIOKPF_PRINT_PHANTOM_KEYS = 1U << 18, +}; + +extern int gpio_event_matrix_func(struct input_dev *input_dev, + struct gpio_event_info *info, void **data, int func); +struct gpio_event_matrix_info { + /* initialize to gpio_event_matrix_func */ + struct gpio_event_info info; + /* size must be ninputs * noutputs */ + const unsigned short *keymap; + unsigned int *input_gpios; + unsigned int *output_gpios; + unsigned int ninputs; + unsigned int noutputs; + /* time to wait before reading inputs after driving each output */ + ktime_t settle_time; + /* time to wait before scanning the keypad a second time */ + ktime_t debounce_delay; + ktime_t poll_time; + unsigned flags; +}; + +/* Directly connected inputs and outputs */ + +enum gpio_event_direct_flags { + GPIOEDF_ACTIVE_HIGH = 1U << 0, +/* GPIOEDF_USE_DOWN_IRQ = 1U << 1, */ +/* GPIOEDF_USE_IRQ = (1U << 2) | GPIOIDF_USE_DOWN_IRQ, */ + GPIOEDF_PRINT_KEYS = 1U << 8, + GPIOEDF_PRINT_KEY_DEBOUNCE = 1U << 9, +}; + +struct gpio_event_direct_entry { + uint32_t gpio:23; + uint32_t code:9; +}; + +/* inputs */ +extern int gpio_event_input_func(struct input_dev *input_dev, + struct gpio_event_info *info, void **data, int func); +struct gpio_event_input_info { + /* initialize to gpio_event_input_func */ + struct gpio_event_info info; + ktime_t debounce_time; + ktime_t poll_time; + uint16_t flags; + uint16_t type; + const struct gpio_event_direct_entry *keymap; + size_t keymap_size; +}; + +/* outputs */ +extern int gpio_event_output_func(struct input_dev *input_dev, + struct gpio_event_info *info, void **data, int func); +extern int gpio_event_output_event(struct input_dev *input_dev, + struct gpio_event_info *info, void **data, + unsigned int type, unsigned int code, int value); +struct gpio_event_output_info { + /* initialize to gpio_event_output_func and gpio_event_output_event */ + struct gpio_event_info info; + uint16_t flags; + uint16_t type; + const struct gpio_event_direct_entry *keymap; + size_t keymap_size; +}; + + +/* axes */ + +enum gpio_event_axis_flags { + GPIOEAF_PRINT_UNKNOWN_DIRECTION = 1U << 16, + GPIOEAF_PRINT_RAW = 1U << 17, + GPIOEAF_PRINT_EVENT = 1U << 18, +}; + +extern int gpio_event_axis_func(struct input_dev *input_dev, + struct gpio_event_info *info, void **data, int func); +struct gpio_event_axis_info { + /* initialize to gpio_event_axis_func */ + struct gpio_event_info info; + uint8_t count; + uint8_t type; /* EV_REL or EV_ABS */ + uint16_t code; + uint16_t decoded_size; + uint16_t (*map)(struct gpio_event_axis_info *info, uint16_t in); + uint32_t *gpio; + uint32_t flags; +}; +#define gpio_axis_2bit_gray_map gpio_axis_4bit_gray_map +#define gpio_axis_3bit_gray_map gpio_axis_4bit_gray_map +uint16_t gpio_axis_4bit_gray_map( + struct gpio_event_axis_info *info, uint16_t in); +uint16_t gpio_axis_5bit_singletrack_map( + struct gpio_event_axis_info *info, uint16_t in); + +#endif diff --git a/drivers/staging/dream/include/linux/msm_adsp.h b/drivers/staging/dream/include/linux/msm_adsp.h new file mode 100644 index 000000000000..e775f3e94f1d --- /dev/null +++ b/drivers/staging/dream/include/linux/msm_adsp.h @@ -0,0 +1,84 @@ +/* drivers/staging/dream/include/linux/msm_adsp.h + * + * Copyright (c) QUALCOMM Incorporated + * Copyright (C) 2007 Google, Inc. + * Author: Iliyan Malchev + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __LINUX_MSM_ADSP_H +#define __LINUX_MSM_ADSP_H + +#include +#include + +#define ADSP_IOCTL_MAGIC 'q' + +/* ADSP_IOCTL_WRITE_COMMAND */ +struct adsp_command_t { + uint16_t queue; + uint32_t len; /* bytes */ + uint8_t *data; +}; + +/* ADSP_IOCTL_GET_EVENT */ +struct adsp_event_t { + uint16_t type; /* 1 == event (RPC), 0 == message (adsp) */ + uint32_t timeout_ms; /* -1 for infinite, 0 for immediate return */ + uint16_t msg_id; + uint16_t flags; /* 1 == 16--bit event, 0 == 32-bit event */ + uint32_t len; /* size in, number of bytes out */ + uint8_t *data; +}; + +#define ADSP_IOCTL_ENABLE \ + _IOR(ADSP_IOCTL_MAGIC, 1, unsigned) + +#define ADSP_IOCTL_DISABLE \ + _IOR(ADSP_IOCTL_MAGIC, 2, unsigned) + +#define ADSP_IOCTL_DISABLE_ACK \ + _IOR(ADSP_IOCTL_MAGIC, 3, unsigned) + +#define ADSP_IOCTL_WRITE_COMMAND \ + _IOR(ADSP_IOCTL_MAGIC, 4, struct adsp_command_t *) + +#define ADSP_IOCTL_GET_EVENT \ + _IOWR(ADSP_IOCTL_MAGIC, 5, struct adsp_event_data_t *) + +#define ADSP_IOCTL_SET_CLKRATE \ + _IOR(ADSP_IOCTL_MAGIC, 6, unsigned) + +#define ADSP_IOCTL_DISABLE_EVENT_RSP \ + _IOR(ADSP_IOCTL_MAGIC, 10, unsigned) + +struct adsp_pmem_info { + int fd; + void *vaddr; +}; + +#define ADSP_IOCTL_REGISTER_PMEM \ + _IOW(ADSP_IOCTL_MAGIC, 13, unsigned) + +#define ADSP_IOCTL_UNREGISTER_PMEM \ + _IOW(ADSP_IOCTL_MAGIC, 14, unsigned) + +/* Cause any further GET_EVENT ioctls to fail (-ENODEV) + * until the device is closed and reopened. Useful for + * terminating event dispatch threads + */ +#define ADSP_IOCTL_ABORT_EVENT_READ \ + _IOW(ADSP_IOCTL_MAGIC, 15, unsigned) + +#define ADSP_IOCTL_LINK_TASK \ + _IOW(ADSP_IOCTL_MAGIC, 16, unsigned) + +#endif diff --git a/drivers/staging/dream/include/linux/msm_audio.h b/drivers/staging/dream/include/linux/msm_audio.h new file mode 100644 index 000000000000..cfbdaa0d98b2 --- /dev/null +++ b/drivers/staging/dream/include/linux/msm_audio.h @@ -0,0 +1,115 @@ +/* drivers/staging/dream/include/linux/msm_audio.h + * + * Copyright (C) 2008 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LINUX_MSM_AUDIO_H +#define __LINUX_MSM_AUDIO_H + +#include +#include +#include + +/* PCM Audio */ + +#define AUDIO_IOCTL_MAGIC 'a' + +#define AUDIO_START _IOW(AUDIO_IOCTL_MAGIC, 0, unsigned) +#define AUDIO_STOP _IOW(AUDIO_IOCTL_MAGIC, 1, unsigned) +#define AUDIO_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 2, unsigned) +#define AUDIO_GET_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 3, unsigned) +#define AUDIO_SET_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 4, unsigned) +#define AUDIO_GET_STATS _IOR(AUDIO_IOCTL_MAGIC, 5, unsigned) +#define AUDIO_ENABLE_AUDPP _IOW(AUDIO_IOCTL_MAGIC, 6, unsigned) +#define AUDIO_SET_ADRC _IOW(AUDIO_IOCTL_MAGIC, 7, unsigned) +#define AUDIO_SET_EQ _IOW(AUDIO_IOCTL_MAGIC, 8, unsigned) +#define AUDIO_SET_RX_IIR _IOW(AUDIO_IOCTL_MAGIC, 9, unsigned) +#define AUDIO_SET_VOLUME _IOW(AUDIO_IOCTL_MAGIC, 10, unsigned) +#define AUDIO_ENABLE_AUDPRE _IOW(AUDIO_IOCTL_MAGIC, 11, unsigned) +#define AUDIO_SET_AGC _IOW(AUDIO_IOCTL_MAGIC, 12, unsigned) +#define AUDIO_SET_NS _IOW(AUDIO_IOCTL_MAGIC, 13, unsigned) +#define AUDIO_SET_TX_IIR _IOW(AUDIO_IOCTL_MAGIC, 14, unsigned) +#define AUDIO_PAUSE _IOW(AUDIO_IOCTL_MAGIC, 15, unsigned) +#define AUDIO_GET_PCM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 30, unsigned) +#define AUDIO_SET_PCM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 31, unsigned) +#define AUDIO_SWITCH_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 32, unsigned) + +#define AUDIO_MAX_COMMON_IOCTL_NUM 100 + +#define AUDIO_MAX_COMMON_IOCTL_NUM 100 + +struct msm_audio_config { + uint32_t buffer_size; + uint32_t buffer_count; + uint32_t channel_count; + uint32_t sample_rate; + uint32_t type; + uint32_t unused[3]; +}; + +struct msm_audio_stats { + uint32_t byte_count; + uint32_t sample_count; + uint32_t unused[2]; +}; + +/* Audio routing */ + +#define SND_IOCTL_MAGIC 's' + +#define SND_MUTE_UNMUTED 0 +#define SND_MUTE_MUTED 1 + +struct msm_snd_device_config { + uint32_t device; + uint32_t ear_mute; + uint32_t mic_mute; +}; + +#define SND_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_device_config *) + +#define SND_METHOD_VOICE 0 + +struct msm_snd_volume_config { + uint32_t device; + uint32_t method; + uint32_t volume; +}; + +#define SND_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_snd_volume_config *) + +/* Returns the number of SND endpoints supported. */ + +#define SND_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned *) + +struct msm_snd_endpoint { + int id; /* input and output */ + char name[64]; /* output only */ +}; + +/* Takes an index between 0 and one less than the number returned by + * SND_GET_NUM_ENDPOINTS, and returns the SND index and name of a + * SND endpoint. On input, the .id field contains the number of the + * endpoint, and on exit it contains the SND index, while .name contains + * the description of the endpoint. + */ + +#define SND_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_snd_endpoint *) + +struct msm_audio_pcm_config { + uint32_t pcm_feedback; /* 0 - disable > 0 - enable */ + uint32_t buffer_count; /* Number of buffers to allocate */ + uint32_t buffer_size; /* Size of buffer for capturing of + PCM samples */ +}; +#endif diff --git a/drivers/staging/dream/include/linux/msm_rpcrouter.h b/drivers/staging/dream/include/linux/msm_rpcrouter.h new file mode 100644 index 000000000000..64845fb481f1 --- /dev/null +++ b/drivers/staging/dream/include/linux/msm_rpcrouter.h @@ -0,0 +1,47 @@ +/* drivers/staging/dream/include/linux/msm_rpcrouter.h + * + * Copyright (c) QUALCOMM Incorporated + * Copyright (C) 2007 Google, Inc. + * Author: San Mehat + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __LINUX_MSM_RPCROUTER_H +#define __LINUX_MSM_RPCROUTER_H + +#include +#include + +#define RPC_ROUTER_VERSION_V1 0x00010000 + +struct rpcrouter_ioctl_server_args { + uint32_t prog; + uint32_t vers; +}; + +#define RPC_ROUTER_IOCTL_MAGIC (0xC1) + +#define RPC_ROUTER_IOCTL_GET_VERSION \ + _IOR(RPC_ROUTER_IOCTL_MAGIC, 0, unsigned int) + +#define RPC_ROUTER_IOCTL_GET_MTU \ + _IOR(RPC_ROUTER_IOCTL_MAGIC, 1, unsigned int) + +#define RPC_ROUTER_IOCTL_REGISTER_SERVER \ + _IOWR(RPC_ROUTER_IOCTL_MAGIC, 2, unsigned int) + +#define RPC_ROUTER_IOCTL_UNREGISTER_SERVER \ + _IOWR(RPC_ROUTER_IOCTL_MAGIC, 3, unsigned int) + +#define RPC_ROUTER_IOCTL_GET_MINOR_VERSION \ + _IOW(RPC_ROUTER_IOCTL_MAGIC, 4, unsigned int) + +#endif diff --git a/drivers/staging/dream/include/linux/wakelock.h b/drivers/staging/dream/include/linux/wakelock.h new file mode 100644 index 000000000000..93c31a4d1ca7 --- /dev/null +++ b/drivers/staging/dream/include/linux/wakelock.h @@ -0,0 +1,91 @@ +/* drivers/staging/dream/include/linux/wakelock.h + * + * Copyright (C) 2007-2008 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_WAKELOCK_H +#define _LINUX_WAKELOCK_H + +#include +#include + +/* A wake_lock prevents the system from entering suspend or other low power + * states when active. If the type is set to WAKE_LOCK_SUSPEND, the wake_lock + * prevents a full system suspend. If the type is WAKE_LOCK_IDLE, low power + * states that cause large interrupt latencies or that disable a set of + * interrupts will not entered from idle until the wake_locks are released. + */ + +enum { + WAKE_LOCK_SUSPEND, /* Prevent suspend */ + WAKE_LOCK_IDLE, /* Prevent low power idle */ + WAKE_LOCK_TYPE_COUNT +}; + +struct wake_lock { +#ifdef CONFIG_HAS_WAKELOCK + struct list_head link; + int flags; + const char *name; + unsigned long expires; +#ifdef CONFIG_WAKELOCK_STAT + struct { + int count; + int expire_count; + int wakeup_count; + ktime_t total_time; + ktime_t prevent_suspend_time; + ktime_t max_time; + ktime_t last_time; + } stat; +#endif +#endif +}; + +#ifdef CONFIG_HAS_WAKELOCK + +void wake_lock_init(struct wake_lock *lock, int type, const char *name); +void wake_lock_destroy(struct wake_lock *lock); +void wake_lock(struct wake_lock *lock); +void wake_lock_timeout(struct wake_lock *lock, long timeout); +void wake_unlock(struct wake_lock *lock); + +/* wake_lock_active returns a non-zero value if the wake_lock is currently + * locked. If the wake_lock has a timeout, it does not check the timeout + * but if the timeout had aready been checked it will return 0. + */ +int wake_lock_active(struct wake_lock *lock); + +/* has_wake_lock returns 0 if no wake locks of the specified type are active, + * and non-zero if one or more wake locks are held. Specifically it returns + * -1 if one or more wake locks with no timeout are active or the + * number of jiffies until all active wake locks time out. + */ +long has_wake_lock(int type); + +#else + +static inline void wake_lock_init(struct wake_lock *lock, int type, + const char *name) {} +static inline void wake_lock_destroy(struct wake_lock *lock) {} +static inline void wake_lock(struct wake_lock *lock) {} +static inline void wake_lock_timeout(struct wake_lock *lock, long timeout) {} +static inline void wake_unlock(struct wake_lock *lock) {} + +static inline int wake_lock_active(struct wake_lock *lock) { return 0; } +static inline long has_wake_lock(int type) { return 0; } + +#endif + +#endif + diff --git a/drivers/staging/dream/include/mach/camera.h b/drivers/staging/dream/include/mach/camera.h new file mode 100644 index 000000000000..c20f0423abd4 --- /dev/null +++ b/drivers/staging/dream/include/mach/camera.h @@ -0,0 +1,279 @@ +/* + * Copyright (C) 2008-2009 QUALCOMM Incorporated. + */ + +#ifndef __ASM__ARCH_CAMERA_H +#define __ASM__ARCH_CAMERA_H + +#include +#include +#include +#include +#include "linux/types.h" + +#include +#include + +#ifdef CONFIG_MSM_CAMERA_DEBUG +#define CDBG(fmt, args...) printk(KERN_INFO "msm_camera: " fmt, ##args) +#else +#define CDBG(fmt, args...) do { } while (0) +#endif + +#define MSM_CAMERA_MSG 0 +#define MSM_CAMERA_EVT 1 +#define NUM_WB_EXP_NEUTRAL_REGION_LINES 4 +#define NUM_WB_EXP_STAT_OUTPUT_BUFFERS 3 +#define NUM_AUTOFOCUS_MULTI_WINDOW_GRIDS 16 +#define NUM_AF_STAT_OUTPUT_BUFFERS 3 + +enum msm_queue { + MSM_CAM_Q_CTRL, /* control command or control command status */ + MSM_CAM_Q_VFE_EVT, /* adsp event */ + MSM_CAM_Q_VFE_MSG, /* adsp message */ + MSM_CAM_Q_V4L2_REQ, /* v4l2 request */ +}; + +enum vfe_resp_msg { + VFE_EVENT, + VFE_MSG_GENERAL, + VFE_MSG_SNAPSHOT, + VFE_MSG_OUTPUT1, + VFE_MSG_OUTPUT2, + VFE_MSG_STATS_AF, + VFE_MSG_STATS_WE, +}; + +struct msm_vfe_phy_info { + uint32_t sbuf_phy; + uint32_t y_phy; + uint32_t cbcr_phy; +}; + +struct msm_vfe_resp { + enum vfe_resp_msg type; + struct msm_vfe_evt_msg evt_msg; + struct msm_vfe_phy_info phy; + void *extdata; + int32_t extlen; +}; + +struct msm_vfe_callback { + void (*vfe_resp)(struct msm_vfe_resp *, + enum msm_queue, void *syncdata); + void* (*vfe_alloc)(int, void *syncdata); +}; + +struct msm_camvfe_fn { + int (*vfe_init)(struct msm_vfe_callback *, struct platform_device *); + int (*vfe_enable)(struct camera_enable_cmd *); + int (*vfe_config)(struct msm_vfe_cfg_cmd *, void *); + int (*vfe_disable)(struct camera_enable_cmd *, + struct platform_device *dev); + void (*vfe_release)(struct platform_device *); +}; + +struct msm_sensor_ctrl { + int (*s_init)(const struct msm_camera_sensor_info *); + int (*s_release)(void); + int (*s_config)(void __user *); +}; + +struct msm_sync { + /* These two queues are accessed from a process context only. */ + struct hlist_head frame; /* most-frequently accessed */ + struct hlist_head stats; + + /* The message queue is used by the control thread to send commands + * to the config thread, and also by the DSP to send messages to the + * config thread. Thus it is the only queue that is accessed from + * both interrupt and process context. + */ + spinlock_t msg_event_q_lock; + struct list_head msg_event_q; + wait_queue_head_t msg_event_wait; + + /* This queue contains preview frames. It is accessed by the DSP (in + * in interrupt context, and by the frame thread. + */ + spinlock_t prev_frame_q_lock; + struct list_head prev_frame_q; + wait_queue_head_t prev_frame_wait; + int unblock_poll_frame; + + /* This queue contains snapshot frames. It is accessed by the DSP (in + * interrupt context, and by the control thread. + */ + spinlock_t pict_frame_q_lock; + struct list_head pict_frame_q; + wait_queue_head_t pict_frame_wait; + + struct msm_camera_sensor_info *sdata; + struct msm_camvfe_fn vfefn; + struct msm_sensor_ctrl sctrl; + struct platform_device *pdev; + uint8_t opencnt; + void *cropinfo; + int croplen; + unsigned pict_pp; + + const char *apps_id; + + struct mutex lock; + struct list_head list; +}; + +#define MSM_APPS_ID_V4L2 "msm_v4l2" +#define MSM_APPS_ID_PROP "msm_qct" + +struct msm_device { + struct msm_sync *sync; /* most-frequently accessed */ + struct device *device; + struct cdev cdev; + /* opened is meaningful only for the config and frame nodes, + * which may be opened only once. + */ + atomic_t opened; +}; + +struct msm_control_device_queue { + spinlock_t ctrl_status_q_lock; + struct list_head ctrl_status_q; + wait_queue_head_t ctrl_status_wait; +}; + +struct msm_control_device { + struct msm_device *pmsm; + + /* This queue used by the config thread to send responses back to the + * control thread. It is accessed only from a process context. + */ + struct msm_control_device_queue ctrl_q; +}; + +/* this structure is used in kernel */ +struct msm_queue_cmd { + struct list_head list; + enum msm_queue type; + void *command; +}; + +struct register_address_value_pair { + uint16_t register_address; + uint16_t register_value; +}; + +struct msm_pmem_region { + struct hlist_node list; + int type; + void *vaddr; + unsigned long paddr; + unsigned long len; + struct file *file; + uint32_t y_off; + uint32_t cbcr_off; + int fd; + uint8_t active; +}; + +struct axidata { + uint32_t bufnum1; + uint32_t bufnum2; + struct msm_pmem_region *region; +}; + +#ifdef CONFIG_MSM_CAMERA_FLASH +int msm_camera_flash_set_led_state(unsigned led_state); +#else +static inline int msm_camera_flash_set_led_state(unsigned led_state) +{ + return -ENOTSUPP; +} +#endif + +/* Below functions are added for V4L2 kernel APIs */ +struct msm_v4l2_driver { + struct msm_sync *sync; + int (*open)(struct msm_sync *, const char *apps_id); + int (*release)(struct msm_sync *); + int (*ctrl)(struct msm_sync *, struct msm_ctrl_cmd *); + int (*reg_pmem)(struct msm_sync *, struct msm_pmem_info *); + int (*get_frame) (struct msm_sync *, struct msm_frame *); + int (*put_frame) (struct msm_sync *, struct msm_frame *); + int (*get_pict) (struct msm_sync *, struct msm_ctrl_cmd *); + unsigned int (*drv_poll) (struct msm_sync *, struct file *, + struct poll_table_struct *); +}; + +int msm_v4l2_register(struct msm_v4l2_driver *); +int msm_v4l2_unregister(struct msm_v4l2_driver *); + +void msm_camvfe_init(void); +int msm_camvfe_check(void *); +void msm_camvfe_fn_init(struct msm_camvfe_fn *, void *); +int msm_camera_drv_start(struct platform_device *dev, + int (*sensor_probe)(const struct msm_camera_sensor_info *, + struct msm_sensor_ctrl *)); + +enum msm_camio_clk_type { + CAMIO_VFE_MDC_CLK, + CAMIO_MDC_CLK, + CAMIO_VFE_CLK, + CAMIO_VFE_AXI_CLK, + + CAMIO_MAX_CLK +}; + +enum msm_camio_clk_src_type { + MSM_CAMIO_CLK_SRC_INTERNAL, + MSM_CAMIO_CLK_SRC_EXTERNAL, + MSM_CAMIO_CLK_SRC_MAX +}; + +enum msm_s_test_mode { + S_TEST_OFF, + S_TEST_1, + S_TEST_2, + S_TEST_3 +}; + +enum msm_s_resolution { + S_QTR_SIZE, + S_FULL_SIZE, + S_INVALID_SIZE +}; + +enum msm_s_reg_update { + /* Sensor egisters that need to be updated during initialization */ + S_REG_INIT, + /* Sensor egisters that needs periodic I2C writes */ + S_UPDATE_PERIODIC, + /* All the sensor Registers will be updated */ + S_UPDATE_ALL, + /* Not valid update */ + S_UPDATE_INVALID +}; + +enum msm_s_setting { + S_RES_PREVIEW, + S_RES_CAPTURE +}; + +int msm_camio_enable(struct platform_device *dev); + +int msm_camio_clk_enable(enum msm_camio_clk_type clk); +int msm_camio_clk_disable(enum msm_camio_clk_type clk); +int msm_camio_clk_config(uint32_t freq); +void msm_camio_clk_rate_set(int rate); +void msm_camio_clk_axi_rate_set(int rate); + +void msm_camio_camif_pad_reg_reset(void); +void msm_camio_camif_pad_reg_reset_2(void); + +void msm_camio_vfe_blk_reset(void); + +void msm_camio_clk_sel(enum msm_camio_clk_src_type); +void msm_camio_disable(struct platform_device *); +int msm_camio_probe_on(struct platform_device *); +int msm_camio_probe_off(struct platform_device *); +#endif diff --git a/drivers/staging/dream/include/mach/msm_adsp.h b/drivers/staging/dream/include/mach/msm_adsp.h new file mode 100644 index 000000000000..a081683328a3 --- /dev/null +++ b/drivers/staging/dream/include/mach/msm_adsp.h @@ -0,0 +1,112 @@ +/* include/asm-arm/arch-msm/msm_adsp.h + * + * Copyright (C) 2008 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM__ARCH_MSM_ADSP_H +#define __ASM__ARCH_MSM_ADSP_H + +struct msm_adsp_module; + +struct msm_adsp_ops { + /* event is called from interrupt context when a message + * arrives from the DSP. Use the provided function pointer + * to copy the message into a local buffer. Do NOT call + * it multiple times. + */ + void (*event)(void *driver_data, unsigned id, size_t len, + void (*getevent)(void *ptr, size_t len)); +}; + +/* Get, Put, Enable, and Disable are synchronous and must only + * be called from thread context. Enable and Disable will block + * up to one second in the event of a fatal DSP error but are + * much faster otherwise. + */ +int msm_adsp_get(const char *name, struct msm_adsp_module **module, + struct msm_adsp_ops *ops, void *driver_data); +void msm_adsp_put(struct msm_adsp_module *module); +int msm_adsp_enable(struct msm_adsp_module *module); +int msm_adsp_disable(struct msm_adsp_module *module); +int adsp_set_clkrate(struct msm_adsp_module *module, unsigned long clk_rate); + +/* Write is safe to call from interrupt context. + */ +int msm_adsp_write(struct msm_adsp_module *module, + unsigned queue_id, + void *data, size_t len); + +#if CONFIG_MSM_AMSS_VERSION >= 6350 +/* Command Queue Indexes */ +#define QDSP_lpmCommandQueue 0 +#define QDSP_mpuAfeQueue 1 +#define QDSP_mpuGraphicsCmdQueue 2 +#define QDSP_mpuModmathCmdQueue 3 +#define QDSP_mpuVDecCmdQueue 4 +#define QDSP_mpuVDecPktQueue 5 +#define QDSP_mpuVEncCmdQueue 6 +#define QDSP_rxMpuDecCmdQueue 7 +#define QDSP_rxMpuDecPktQueue 8 +#define QDSP_txMpuEncQueue 9 +#define QDSP_uPAudPPCmd1Queue 10 +#define QDSP_uPAudPPCmd2Queue 11 +#define QDSP_uPAudPPCmd3Queue 12 +#define QDSP_uPAudPlay0BitStreamCtrlQueue 13 +#define QDSP_uPAudPlay1BitStreamCtrlQueue 14 +#define QDSP_uPAudPlay2BitStreamCtrlQueue 15 +#define QDSP_uPAudPlay3BitStreamCtrlQueue 16 +#define QDSP_uPAudPlay4BitStreamCtrlQueue 17 +#define QDSP_uPAudPreProcCmdQueue 18 +#define QDSP_uPAudRecBitStreamQueue 19 +#define QDSP_uPAudRecCmdQueue 20 +#define QDSP_uPDiagQueue 21 +#define QDSP_uPJpegActionCmdQueue 22 +#define QDSP_uPJpegCfgCmdQueue 23 +#define QDSP_uPVocProcQueue 24 +#define QDSP_vfeCommandQueue 25 +#define QDSP_vfeCommandScaleQueue 26 +#define QDSP_vfeCommandTableQueue 27 +#define QDSP_MAX_NUM_QUEUES 28 +#else +/* Command Queue Indexes */ +#define QDSP_lpmCommandQueue 0 +#define QDSP_mpuAfeQueue 1 +#define QDSP_mpuGraphicsCmdQueue 2 +#define QDSP_mpuModmathCmdQueue 3 +#define QDSP_mpuVDecCmdQueue 4 +#define QDSP_mpuVDecPktQueue 5 +#define QDSP_mpuVEncCmdQueue 6 +#define QDSP_rxMpuDecCmdQueue 7 +#define QDSP_rxMpuDecPktQueue 8 +#define QDSP_txMpuEncQueue 9 +#define QDSP_uPAudPPCmd1Queue 10 +#define QDSP_uPAudPPCmd2Queue 11 +#define QDSP_uPAudPPCmd3Queue 12 +#define QDSP_uPAudPlay0BitStreamCtrlQueue 13 +#define QDSP_uPAudPlay1BitStreamCtrlQueue 14 +#define QDSP_uPAudPlay2BitStreamCtrlQueue 15 +#define QDSP_uPAudPlay3BitStreamCtrlQueue 16 +#define QDSP_uPAudPlay4BitStreamCtrlQueue 17 +#define QDSP_uPAudPreProcCmdQueue 18 +#define QDSP_uPAudRecBitStreamQueue 19 +#define QDSP_uPAudRecCmdQueue 20 +#define QDSP_uPJpegActionCmdQueue 21 +#define QDSP_uPJpegCfgCmdQueue 22 +#define QDSP_uPVocProcQueue 23 +#define QDSP_vfeCommandQueue 24 +#define QDSP_vfeCommandScaleQueue 25 +#define QDSP_vfeCommandTableQueue 26 +#define QDSP_QUEUE_MAX 26 +#endif + +#endif diff --git a/drivers/staging/dream/include/mach/msm_rpcrouter.h b/drivers/staging/dream/include/mach/msm_rpcrouter.h new file mode 100644 index 000000000000..9724ece1c97c --- /dev/null +++ b/drivers/staging/dream/include/mach/msm_rpcrouter.h @@ -0,0 +1,179 @@ +/** include/asm-arm/arch-msm/msm_rpcrouter.h + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2007-2009 QUALCOMM Incorporated + * Author: San Mehat + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM__ARCH_MSM_RPCROUTER_H +#define __ASM__ARCH_MSM_RPCROUTER_H + +#include +#include +#include + +#if CONFIG_MSM_AMSS_VERSION >= 6350 +/* RPC API version structure + * Version bit 31 : 1->hashkey versioning, + * 0->major-minor (backward compatible) versioning + * hashkey versioning: + * Version bits 31-0 hashkey + * major-minor (backward compatible) versioning + * Version bits 30-28 reserved (no match) + * Version bits 27-16 major (must match) + * Version bits 15-0 minor (greater or equal) + */ +#define RPC_VERSION_MODE_MASK 0x80000000 +#define RPC_VERSION_MAJOR_MASK 0x0fff0000 +#define RPC_VERSION_MAJOR_OFFSET 16 +#define RPC_VERSION_MINOR_MASK 0x0000ffff + +#define MSM_RPC_VERS(major, minor) \ + ((uint32_t)((((major) << RPC_VERSION_MAJOR_OFFSET) & \ + RPC_VERSION_MAJOR_MASK) | \ + ((minor) & RPC_VERSION_MINOR_MASK))) +#define MSM_RPC_GET_MAJOR(vers) (((vers) & RPC_VERSION_MAJOR_MASK) >> \ + RPC_VERSION_MAJOR_OFFSET) +#define MSM_RPC_GET_MINOR(vers) ((vers) & RPC_VERSION_MINOR_MASK) +#else +#define MSM_RPC_VERS(major, minor) (major) +#define MSM_RPC_GET_MAJOR(vers) (vers) +#define MSM_RPC_GET_MINOR(vers) 0 +#endif + +struct msm_rpc_endpoint; + +struct rpcsvr_platform_device +{ + struct platform_device base; + uint32_t prog; + uint32_t vers; +}; + +#define RPC_DATA_IN 0 +/* + * Structures for sending / receiving direct RPC requests + * XXX: Any cred/verif lengths > 0 not supported + */ + +struct rpc_request_hdr +{ + uint32_t xid; + uint32_t type; /* 0 */ + uint32_t rpc_vers; /* 2 */ + uint32_t prog; + uint32_t vers; + uint32_t procedure; + uint32_t cred_flavor; + uint32_t cred_length; + uint32_t verf_flavor; + uint32_t verf_length; +}; + +typedef struct +{ + uint32_t low; + uint32_t high; +} rpc_reply_progmismatch_data; + +typedef struct +{ +} rpc_denied_reply_hdr; + +typedef struct +{ + uint32_t verf_flavor; + uint32_t verf_length; + uint32_t accept_stat; +#define RPC_ACCEPTSTAT_SUCCESS 0 +#define RPC_ACCEPTSTAT_PROG_UNAVAIL 1 +#define RPC_ACCEPTSTAT_PROG_MISMATCH 2 +#define RPC_ACCEPTSTAT_PROC_UNAVAIL 3 +#define RPC_ACCEPTSTAT_GARBAGE_ARGS 4 +#define RPC_ACCEPTSTAT_SYSTEM_ERR 5 +#define RPC_ACCEPTSTAT_PROG_LOCKED 6 + /* + * Following data is dependant on accept_stat + * If ACCEPTSTAT == PROG_MISMATCH then there is a + * 'rpc_reply_progmismatch_data' structure following the header. + * Otherwise the data is procedure specific + */ +} rpc_accepted_reply_hdr; + +struct rpc_reply_hdr +{ + uint32_t xid; + uint32_t type; + uint32_t reply_stat; +#define RPCMSG_REPLYSTAT_ACCEPTED 0 +#define RPCMSG_REPLYSTAT_DENIED 1 + union { + rpc_accepted_reply_hdr acc_hdr; + rpc_denied_reply_hdr dny_hdr; + } data; +}; + +/* flags for msm_rpc_connect() */ +#define MSM_RPC_UNINTERRUPTIBLE 0x0001 + +/* use IS_ERR() to check for failure */ +struct msm_rpc_endpoint *msm_rpc_open(void); +/* Connect with the specified server version */ +struct msm_rpc_endpoint *msm_rpc_connect(uint32_t prog, uint32_t vers, unsigned flags); +uint32_t msm_rpc_get_vers(struct msm_rpc_endpoint *ept); +/* check if server version can handle client requested version */ +int msm_rpc_is_compatible_version(uint32_t server_version, + uint32_t client_version); + +int msm_rpc_close(struct msm_rpc_endpoint *ept); +int msm_rpc_write(struct msm_rpc_endpoint *ept, + void *data, int len); +int msm_rpc_read(struct msm_rpc_endpoint *ept, + void **data, unsigned len, long timeout); +void msm_rpc_setup_req(struct rpc_request_hdr *hdr, + uint32_t prog, uint32_t vers, uint32_t proc); +int msm_rpc_register_server(struct msm_rpc_endpoint *ept, + uint32_t prog, uint32_t vers); +int msm_rpc_unregister_server(struct msm_rpc_endpoint *ept, + uint32_t prog, uint32_t vers); + +/* simple blocking rpc call + * + * request is mandatory and must have a rpc_request_hdr + * at the start. The header will be filled out for you. + * + * reply provides a buffer for replies of reply_max_size + */ +int msm_rpc_call_reply(struct msm_rpc_endpoint *ept, uint32_t proc, + void *request, int request_size, + void *reply, int reply_max_size, + long timeout); +int msm_rpc_call(struct msm_rpc_endpoint *ept, uint32_t proc, + void *request, int request_size, + long timeout); + +struct msm_rpc_server +{ + struct list_head list; + uint32_t flags; + + uint32_t prog; + uint32_t vers; + + int (*rpc_call)(struct msm_rpc_server *server, + struct rpc_request_hdr *req, unsigned len); +}; + +int msm_rpc_create_server(struct msm_rpc_server *server); + +#endif diff --git a/drivers/staging/dream/include/mach/msm_smd.h b/drivers/staging/dream/include/mach/msm_smd.h new file mode 100644 index 000000000000..bdf7731ab680 --- /dev/null +++ b/drivers/staging/dream/include/mach/msm_smd.h @@ -0,0 +1,107 @@ +/* linux/include/asm-arm/arch-msm/msm_smd.h + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_SMD_H +#define __ASM_ARCH_MSM_SMD_H + +typedef struct smd_channel smd_channel_t; + +/* warning: notify() may be called before open returns */ +int smd_open(const char *name, smd_channel_t **ch, void *priv, + void (*notify)(void *priv, unsigned event)); + +#define SMD_EVENT_DATA 1 +#define SMD_EVENT_OPEN 2 +#define SMD_EVENT_CLOSE 3 + +int smd_close(smd_channel_t *ch); + +/* passing a null pointer for data reads and discards */ +int smd_read(smd_channel_t *ch, void *data, int len); + +/* Write to stream channels may do a partial write and return +** the length actually written. +** Write to packet channels will never do a partial write -- +** it will return the requested length written or an error. +*/ +int smd_write(smd_channel_t *ch, const void *data, int len); + +int smd_write_avail(smd_channel_t *ch); +int smd_read_avail(smd_channel_t *ch); + +/* Returns the total size of the current packet being read. +** Returns 0 if no packets available or a stream channel. +*/ +int smd_cur_packet_size(smd_channel_t *ch); + +/* used for tty unthrottling and the like -- causes the notify() +** callback to be called from the same lock context as is used +** when it is called from channel updates +*/ +void smd_kick(smd_channel_t *ch); + + +#if 0 +/* these are interruptable waits which will block you until the specified +** number of bytes are readable or writable. +*/ +int smd_wait_until_readable(smd_channel_t *ch, int bytes); +int smd_wait_until_writable(smd_channel_t *ch, int bytes); +#endif + +typedef enum +{ + SMD_PORT_DS = 0, + SMD_PORT_DIAG, + SMD_PORT_RPC_CALL, + SMD_PORT_RPC_REPLY, + SMD_PORT_BT, + SMD_PORT_CONTROL, + SMD_PORT_MEMCPY_SPARE1, + SMD_PORT_DATA1, + SMD_PORT_DATA2, + SMD_PORT_DATA3, + SMD_PORT_DATA4, + SMD_PORT_DATA5, + SMD_PORT_DATA6, + SMD_PORT_DATA7, + SMD_PORT_DATA8, + SMD_PORT_DATA9, + SMD_PORT_DATA10, + SMD_PORT_DATA11, + SMD_PORT_DATA12, + SMD_PORT_DATA13, + SMD_PORT_DATA14, + SMD_PORT_DATA15, + SMD_PORT_DATA16, + SMD_PORT_DATA17, + SMD_PORT_DATA18, + SMD_PORT_DATA19, + SMD_PORT_DATA20, + SMD_PORT_GPS_NMEA, + SMD_PORT_BRIDGE_1, + SMD_PORT_BRIDGE_2, + SMD_PORT_BRIDGE_3, + SMD_PORT_BRIDGE_4, + SMD_PORT_BRIDGE_5, + SMD_PORT_LOOPBACK, + SMD_PORT_CS_APPS_MODEM, + SMD_PORT_CS_APPS_DSP, + SMD_PORT_CS_MODEM_DSP, + SMD_NUM_PORTS, +} smd_port_id_type; + +#endif diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5audplaycmdi.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5audplaycmdi.h new file mode 100644 index 000000000000..0b6a31259bb0 --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5audplaycmdi.h @@ -0,0 +1,94 @@ +#ifndef QDSP5AUDPLAYCMDI_H +#define QDSP5AUDPLAYCMDI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + Q D S P 5 A U D I O P L A Y T A S K C O M M A N D S + +GENERAL DESCRIPTION + Command Interface for AUDPLAYTASK on QDSP5 + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + + audplay_cmd_dec_data_avail + Send buffer to AUDPLAY task + + +Copyright(c) 1992 - 2009 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audplaycmdi.h#2 $ + +===========================================================================*/ + +#define AUDPLAY_CMD_BITSTREAM_DATA_AVAIL 0x0000 +#define AUDPLAY_CMD_BITSTREAM_DATA_AVAIL_LEN \ + sizeof(audplay_cmd_bitstream_data_avail) + +/* Type specification of dec_data_avail message sent to AUDPLAYTASK +*/ +typedef struct { + /*command ID*/ + unsigned int cmd_id; + + /* Decoder ID for which message is being sent */ + unsigned int decoder_id; + + /* Start address of data in ARM global memory */ + unsigned int buf_ptr; + + /* Number of 16-bit words of bit-stream data contiguously available at the + * above-mentioned address. */ + unsigned int buf_size; + + /* Partition number used by audPlayTask to communicate with DSP's RTOS + * kernel */ + unsigned int partition_number; +} __attribute__((packed)) audplay_cmd_bitstream_data_avail; + +#define AUDPLAY_CMD_HPCM_BUF_CFG 0x0003 +#define AUDPLAY_CMD_HPCM_BUF_CFG_LEN \ + sizeof(struct audplay_cmd_hpcm_buf_cfg) + +struct audplay_cmd_hpcm_buf_cfg { + unsigned int cmd_id; + unsigned int hostpcm_config; + unsigned int feedback_frequency; + unsigned int byte_swap; + unsigned int max_buffers; + unsigned int partition_number; +} __attribute__((packed)); + +#define AUDPLAY_CMD_BUFFER_REFRESH 0x0004 +#define AUDPLAY_CMD_BUFFER_REFRESH_LEN \ + sizeof(struct audplay_cmd_buffer_update) + +struct audplay_cmd_buffer_refresh { + unsigned int cmd_id; + unsigned int num_buffers; + unsigned int buf_read_count; + unsigned int buf0_address; + unsigned int buf0_length; + unsigned int buf1_address; + unsigned int buf1_length; +} __attribute__((packed)); +#endif /* QDSP5AUDPLAYCMD_H */ diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5audplaymsg.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5audplaymsg.h new file mode 100644 index 000000000000..c63034b8bf13 --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5audplaymsg.h @@ -0,0 +1,70 @@ +#ifndef QDSP5AUDPLAYMSG_H +#define QDSP5AUDPLAYMSG_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + Q D S P 5 A U D I O P L A Y T A S K M S G + +GENERAL DESCRIPTION + Message sent by AUDPLAY task + +REFERENCES + None + + +Copyright(c) 1992 - 2009 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audplaymsg.h#3 $ + +===========================================================================*/ +#define AUDPLAY_MSG_DEC_NEEDS_DATA 0x0001 +#define AUDPLAY_MSG_DEC_NEEDS_DATA_MSG_LEN \ + sizeof(audplay_msg_dec_needs_data) + +typedef struct{ + /* reserved*/ + unsigned int dec_id; + + /* The read pointer offset of external memory until which the + * bitstream has been DMAed in. */ + unsigned int adecDataReadPtrOffset; + + /* The buffer size of external memory. */ + unsigned int adecDataBufSize; + + unsigned int bitstream_free_len; + unsigned int bitstream_write_ptr; + unsigned int bitstarem_buf_start; + unsigned int bitstream_buf_len; +} __attribute__((packed)) audplay_msg_dec_needs_data; + +#define AUDPLAY_MSG_BUFFER_UPDATE 0x0004 +#define AUDPLAY_MSG_BUFFER_UPDATE_LEN \ + sizeof(struct audplay_msg_buffer_update) + +struct audplay_msg_buffer_update { + unsigned int buffer_write_count; + unsigned int num_of_buffer; + unsigned int buf0_address; + unsigned int buf0_length; + unsigned int buf1_address; + unsigned int buf1_length; +} __attribute__((packed)); +#endif /* QDSP5AUDPLAYMSG_H */ diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5audppcmdi.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5audppcmdi.h new file mode 100644 index 000000000000..8bee9c62980b --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5audppcmdi.h @@ -0,0 +1,914 @@ +#ifndef QDSP5AUDPPCMDI_H +#define QDSP5AUDPPCMDI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + A U D I O P O S T P R O C E S S I N G I N T E R N A L C O M M A N D S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of commands + that are accepted by AUDPP Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audppcmdi.h#2 $ + +===========================================================================*/ + +/* + * ARM to AUDPPTASK Commands + * + * ARM uses three command queues to communicate with AUDPPTASK + * 1)uPAudPPCmd1Queue : Used for more frequent and shorter length commands + * Location : MEMA + * Buffer Size : 6 words + * No of buffers in a queue : 20 for gaming audio and 5 for other images + * 2)uPAudPPCmd2Queue : Used for commands which are not much lengthier + * Location : MEMA + * Buffer Size : 23 + * No of buffers in a queue : 2 + * 3)uPAudOOCmd3Queue : Used for lengthier and more frequent commands + * Location : MEMA + * Buffer Size : 145 + * No of buffers in a queue : 3 + */ + +/* + * Commands Related to uPAudPPCmd1Queue + */ + +/* + * Command Structure to enable or disable the active decoders + */ + +#define AUDPP_CMD_CFG_DEC_TYPE 0x0001 +#define AUDPP_CMD_CFG_DEC_TYPE_LEN sizeof(audpp_cmd_cfg_dec_type) + +/* Enable the decoder */ +#define AUDPP_CMD_DEC_TYPE_M 0x000F + +#define AUDPP_CMD_ENA_DEC_V 0x4000 +#define AUDPP_CMD_DIS_DEC_V 0x0000 +#define AUDPP_CMD_DEC_STATE_M 0x4000 + +#define AUDPP_CMD_UPDATDE_CFG_DEC 0x8000 +#define AUDPP_CMD_DONT_UPDATE_CFG_DEC 0x0000 + + +/* Type specification of cmd_cfg_dec */ + +typedef struct { + unsigned short cmd_id; + unsigned short dec0_cfg; + unsigned short dec1_cfg; + unsigned short dec2_cfg; + unsigned short dec3_cfg; + unsigned short dec4_cfg; +} __attribute__((packed)) audpp_cmd_cfg_dec_type; + +/* + * Command Structure to Pause , Resume and flushes the selected audio decoders + */ + +#define AUDPP_CMD_DEC_CTRL 0x0002 +#define AUDPP_CMD_DEC_CTRL_LEN sizeof(audpp_cmd_dec_ctrl) + +/* Decoder control commands for pause, resume and flush */ +#define AUDPP_CMD_FLUSH_V 0x2000 + +#define AUDPP_CMD_PAUSE_V 0x4000 +#define AUDPP_CMD_RESUME_V 0x0000 + +#define AUDPP_CMD_UPDATE_V 0x8000 +#define AUDPP_CMD_IGNORE_V 0x0000 + + +/* Type Spec for decoder control command*/ + +typedef struct { + unsigned short cmd_id; + unsigned short dec0_ctrl; + unsigned short dec1_ctrl; + unsigned short dec2_ctrl; + unsigned short dec3_ctrl; + unsigned short dec4_ctrl; +} __attribute__((packed)) audpp_cmd_dec_ctrl; + +/* + * Command Structure to Configure the AVSync FeedBack Mechanism + */ + +#define AUDPP_CMD_AVSYNC 0x0003 +#define AUDPP_CMD_AVSYNC_LEN sizeof(audpp_cmd_avsync) + +typedef struct { + unsigned short cmd_id; + unsigned short object_number; + unsigned short interrupt_interval_lsw; + unsigned short interrupt_interval_msw; +} __attribute__((packed)) audpp_cmd_avsync; + +/* + * Command Structure to enable or disable(sleep) the AUDPPTASK + */ + +#define AUDPP_CMD_CFG 0x0004 +#define AUDPP_CMD_CFG_LEN sizeof(audpp_cmd_cfg) + +#define AUDPP_CMD_CFG_SLEEP 0x0000 +#define AUDPP_CMD_CFG_ENABLE 0xFFFF + +typedef struct { + unsigned short cmd_id; + unsigned short cfg; +} __attribute__((packed)) audpp_cmd_cfg; + +/* + * Command Structure to Inject or drop the specified no of samples + */ + +#define AUDPP_CMD_ADJUST_SAMP 0x0005 +#define AUDPP_CMD_ADJUST_SAMP_LEN sizeof(audpp_cmd_adjust_samp) + +#define AUDPP_CMD_SAMP_DROP -1 +#define AUDPP_CMD_SAMP_INSERT 0x0001 + +#define AUDPP_CMD_NUM_SAMPLES 0x0001 + +typedef struct { + unsigned short cmd_id; + unsigned short object_no; + signed short sample_insert_or_drop; + unsigned short num_samples; +} __attribute__((packed)) audpp_cmd_adjust_samp; + +/* + * Command Structure to Configure AVSync Feedback Mechanism + */ + +#define AUDPP_CMD_AVSYNC_CMD_2 0x0006 +#define AUDPP_CMD_AVSYNC_CMD_2_LEN sizeof(audpp_cmd_avsync_cmd_2) + +typedef struct { + unsigned short cmd_id; + unsigned short object_number; + unsigned short interrupt_interval_lsw; + unsigned short interrupt_interval_msw; + unsigned short sample_counter_dlsw; + unsigned short sample_counter_dmsw; + unsigned short sample_counter_msw; + unsigned short byte_counter_dlsw; + unsigned short byte_counter_dmsw; + unsigned short byte_counter_msw; +} __attribute__((packed)) audpp_cmd_avsync_cmd_2; + +/* + * Command Structure to Configure AVSync Feedback Mechanism + */ + +#define AUDPP_CMD_AVSYNC_CMD_3 0x0007 +#define AUDPP_CMD_AVSYNC_CMD_3_LEN sizeof(audpp_cmd_avsync_cmd_3) + +typedef struct { + unsigned short cmd_id; + unsigned short object_number; + unsigned short interrupt_interval_lsw; + unsigned short interrupt_interval_msw; + unsigned short sample_counter_dlsw; + unsigned short sample_counter_dmsw; + unsigned short sample_counter_msw; + unsigned short byte_counter_dlsw; + unsigned short byte_counter_dmsw; + unsigned short byte_counter_msw; +} __attribute__((packed)) audpp_cmd_avsync_cmd_3; + +#define AUDPP_CMD_ROUTING_MODE 0x0008 +#define AUDPP_CMD_ROUTING_MODE_LEN \ +sizeof(struct audpp_cmd_routing_mode) + +struct audpp_cmd_routing_mode { + unsigned short cmd_id; + unsigned short object_number; + unsigned short routing_mode; +} __attribute__((packed)); + +/* + * Commands Related to uPAudPPCmd2Queue + */ + +/* + * Command Structure to configure Per decoder Parameters (Common) + */ + +#define AUDPP_CMD_CFG_ADEC_PARAMS 0x0000 +#define AUDPP_CMD_CFG_ADEC_PARAMS_COMMON_LEN \ + sizeof(audpp_cmd_cfg_adec_params_common) + +#define AUDPP_CMD_STATUS_MSG_FLAG_ENA_FCM 0x4000 +#define AUDPP_CMD_STATUS_MSG_FLAG_DIS_FCM 0x0000 + +#define AUDPP_CMD_STATUS_MSG_FLAG_ENA_DCM 0x8000 +#define AUDPP_CMD_STATUS_MSG_FLAG_DIS_DCM 0x0000 + +/* Sampling frequency*/ +#define AUDPP_CMD_SAMP_RATE_96000 0x0000 +#define AUDPP_CMD_SAMP_RATE_88200 0x0001 +#define AUDPP_CMD_SAMP_RATE_64000 0x0002 +#define AUDPP_CMD_SAMP_RATE_48000 0x0003 +#define AUDPP_CMD_SAMP_RATE_44100 0x0004 +#define AUDPP_CMD_SAMP_RATE_32000 0x0005 +#define AUDPP_CMD_SAMP_RATE_24000 0x0006 +#define AUDPP_CMD_SAMP_RATE_22050 0x0007 +#define AUDPP_CMD_SAMP_RATE_16000 0x0008 +#define AUDPP_CMD_SAMP_RATE_12000 0x0009 +#define AUDPP_CMD_SAMP_RATE_11025 0x000A +#define AUDPP_CMD_SAMP_RATE_8000 0x000B + + +/* + * Type specification of cmd_adec_cfg sent to all decoder + */ + +typedef struct { + unsigned short cmd_id; + unsigned short length; + unsigned short dec_id; + unsigned short status_msg_flag; + unsigned short decoder_frame_counter_msg_period; + unsigned short input_sampling_frequency; +} __attribute__((packed)) audpp_cmd_cfg_adec_params_common; + +/* + * Command Structure to configure Per decoder Parameters (Wav) + */ + +#define AUDPP_CMD_CFG_ADEC_PARAMS_WAV_LEN \ + sizeof(audpp_cmd_cfg_adec_params_wav) + + +#define AUDPP_CMD_WAV_STEREO_CFG_MONO 0x0001 +#define AUDPP_CMD_WAV_STEREO_CFG_STEREO 0x0002 + +#define AUDPP_CMD_WAV_PCM_WIDTH_8 0x0000 +#define AUDPP_CMD_WAV_PCM_WIDTH_16 0x0001 +#define AUDPP_CMD_WAV_PCM_WIDTH_32 0x0002 + +typedef struct { + audpp_cmd_cfg_adec_params_common common; + unsigned short stereo_cfg; + unsigned short pcm_width; + unsigned short sign; +} __attribute__((packed)) audpp_cmd_cfg_adec_params_wav; + +/* + * Command Structure to configure Per decoder Parameters (ADPCM) + */ + +#define AUDPP_CMD_CFG_ADEC_PARAMS_ADPCM_LEN \ + sizeof(audpp_cmd_cfg_adec_params_adpcm) + + +#define AUDPP_CMD_ADPCM_STEREO_CFG_MONO 0x0001 +#define AUDPP_CMD_ADPCM_STEREO_CFG_STEREO 0x0002 + +typedef struct { + audpp_cmd_cfg_adec_params_common common; + unsigned short stereo_cfg; + unsigned short block_size; +} __attribute__((packed)) audpp_cmd_cfg_adec_params_adpcm; + +/* + * Command Structure to configure Per decoder Parameters (MP3) + */ + +#define AUDPP_CMD_CFG_ADEC_PARAMS_MP3_LEN \ + sizeof(audpp_cmd_cfg_adec_params_mp3) + +typedef struct { + audpp_cmd_cfg_adec_params_common common; +} __attribute__((packed)) audpp_cmd_cfg_adec_params_mp3; + + +/* + * Command Structure to configure Per decoder Parameters (AAC) + */ + +#define AUDPP_CMD_CFG_ADEC_PARAMS_AAC_LEN \ + sizeof(audpp_cmd_cfg_adec_params_aac) + + +#define AUDPP_CMD_AAC_FORMAT_ADTS -1 +#define AUDPP_CMD_AAC_FORMAT_RAW 0x0000 +#define AUDPP_CMD_AAC_FORMAT_PSUEDO_RAW 0x0001 +#define AUDPP_CMD_AAC_FORMAT_LOAS 0x0002 + +#define AUDPP_CMD_AAC_AUDIO_OBJECT_LC 0x0002 +#define AUDPP_CMD_AAC_AUDIO_OBJECT_LTP 0x0004 +#define AUDPP_CMD_AAC_AUDIO_OBJECT_ERLC 0x0011 + +#define AUDPP_CMD_AAC_SBR_ON_FLAG_ON 0x0001 +#define AUDPP_CMD_AAC_SBR_ON_FLAG_OFF 0x0000 + +#define AUDPP_CMD_AAC_SBR_PS_ON_FLAG_ON 0x0001 +#define AUDPP_CMD_AAC_SBR_PS_ON_FLAG_OFF 0x0000 + +typedef struct { + audpp_cmd_cfg_adec_params_common common; + signed short format; + unsigned short audio_object; + unsigned short ep_config; + unsigned short aac_section_data_resilience_flag; + unsigned short aac_scalefactor_data_resilience_flag; + unsigned short aac_spectral_data_resilience_flag; + unsigned short sbr_on_flag; + unsigned short sbr_ps_on_flag; + unsigned short dual_mono_mode; + unsigned short channel_configuration; +} __attribute__((packed)) audpp_cmd_cfg_adec_params_aac; + +/* + * Command Structure to configure Per decoder Parameters (V13K) + */ + +#define AUDPP_CMD_CFG_ADEC_PARAMS_V13K_LEN \ + sizeof(struct audpp_cmd_cfg_adec_params_v13k) + + +#define AUDPP_CMD_STEREO_CFG_MONO 0x0001 +#define AUDPP_CMD_STEREO_CFG_STEREO 0x0002 + +struct audpp_cmd_cfg_adec_params_v13k { + audpp_cmd_cfg_adec_params_common common; + unsigned short stereo_cfg; +} __attribute__((packed)); + +#define AUDPP_CMD_CFG_ADEC_PARAMS_EVRC_LEN \ + sizeof(struct audpp_cmd_cfg_adec_params_evrc) + +struct audpp_cmd_cfg_adec_params_evrc { + audpp_cmd_cfg_adec_params_common common; + unsigned short stereo_cfg; +} __attribute__ ((packed)); + +/* + * Command Structure to configure the HOST PCM interface + */ + +#define AUDPP_CMD_PCM_INTF 0x0001 +#define AUDPP_CMD_PCM_INTF_2 0x0002 +#define AUDPP_CMD_PCM_INTF_LEN sizeof(audpp_cmd_pcm_intf) + +#define AUDPP_CMD_PCM_INTF_MONO_V 0x0001 +#define AUDPP_CMD_PCM_INTF_STEREO_V 0x0002 + +/* These two values differentiate the two types of commands that could be issued + * Interface configuration command and Buffer update command */ + +#define AUDPP_CMD_PCM_INTF_CONFIG_CMD_V 0x0000 +#define AUDPP_CMD_PCM_INTF_BUFFER_CMD_V -1 + +#define AUDPP_CMD_PCM_INTF_RX_ENA_M 0x000F +#define AUDPP_CMD_PCM_INTF_RX_ENA_ARMTODSP_V 0x0008 +#define AUDPP_CMD_PCM_INTF_RX_ENA_DSPTOARM_V 0x0004 + +/* These flags control the enabling and disabling of the interface together + * with host interface bit mask. */ + +#define AUDPP_CMD_PCM_INTF_ENA_V -1 +#define AUDPP_CMD_PCM_INTF_DIS_V 0x0000 + + +#define AUDPP_CMD_PCM_INTF_FULL_DUPLEX 0x0 +#define AUDPP_CMD_PCM_INTF_HALF_DUPLEX_TODSP 0x1 + + +#define AUDPP_CMD_PCM_INTF_OBJECT_NUM 0x5 +#define AUDPP_CMD_PCM_INTF_COMMON_OBJECT_NUM 0x6 + + +typedef struct { + unsigned short cmd_id; + unsigned short object_num; + signed short config; + unsigned short intf_type; + + /* DSP -> ARM Configuration */ + unsigned short read_buf1LSW; + unsigned short read_buf1MSW; + unsigned short read_buf1_len; + + unsigned short read_buf2LSW; + unsigned short read_buf2MSW; + unsigned short read_buf2_len; + /* 0:HOST_PCM_INTF disable + ** 0xFFFF: HOST_PCM_INTF enable + */ + signed short dsp_to_arm_flag; + unsigned short partition_number; + + /* ARM -> DSP Configuration */ + unsigned short write_buf1LSW; + unsigned short write_buf1MSW; + unsigned short write_buf1_len; + + unsigned short write_buf2LSW; + unsigned short write_buf2MSW; + unsigned short write_buf2_len; + + /* 0:HOST_PCM_INTF disable + ** 0xFFFF: HOST_PCM_INTF enable + */ + signed short arm_to_rx_flag; + unsigned short weight_decoder_to_rx; + unsigned short weight_arm_to_rx; + + unsigned short partition_number_arm_to_dsp; + unsigned short sample_rate; + unsigned short channel_mode; +} __attribute__((packed)) audpp_cmd_pcm_intf; + +/* + ** BUFFER UPDATE COMMAND + */ +#define AUDPP_CMD_PCM_INTF_SEND_BUF_PARAMS_LEN \ + sizeof(audpp_cmd_pcm_intf_send_buffer) + +typedef struct { + unsigned short cmd_id; + unsigned short host_pcm_object; + /* set config = 0xFFFF for configuration*/ + signed short config; + unsigned short intf_type; + unsigned short dsp_to_arm_buf_id; + unsigned short arm_to_dsp_buf_id; + unsigned short arm_to_dsp_buf_len; +} __attribute__((packed)) audpp_cmd_pcm_intf_send_buffer; + + +/* + * Commands Related to uPAudPPCmd3Queue + */ + +/* + * Command Structure to configure post processing params (Commmon) + */ + +#define AUDPP_CMD_CFG_OBJECT_PARAMS 0x0000 +#define AUDPP_CMD_CFG_OBJECT_PARAMS_COMMON_LEN \ + sizeof(audpp_cmd_cfg_object_params_common) + +#define AUDPP_CMD_OBJ0_UPDATE 0x8000 +#define AUDPP_CMD_OBJ0_DONT_UPDATE 0x0000 + +#define AUDPP_CMD_OBJ1_UPDATE 0x8000 +#define AUDPP_CMD_OBJ1_DONT_UPDATE 0x0000 + +#define AUDPP_CMD_OBJ2_UPDATE 0x8000 +#define AUDPP_CMD_OBJ2_DONT_UPDATE 0x0000 + +#define AUDPP_CMD_OBJ3_UPDATE 0x8000 +#define AUDPP_CMD_OBJ3_DONT_UPDATE 0x0000 + +#define AUDPP_CMD_OBJ4_UPDATE 0x8000 +#define AUDPP_CMD_OBJ4_DONT_UPDATE 0x0000 + +#define AUDPP_CMD_HPCM_UPDATE 0x8000 +#define AUDPP_CMD_HPCM_DONT_UPDATE 0x0000 + +#define AUDPP_CMD_COMMON_CFG_UPDATE 0x8000 +#define AUDPP_CMD_COMMON_CFG_DONT_UPDATE 0x0000 + +typedef struct { + unsigned short cmd_id; + unsigned short obj0_cfg; + unsigned short obj1_cfg; + unsigned short obj2_cfg; + unsigned short obj3_cfg; + unsigned short obj4_cfg; + unsigned short host_pcm_obj_cfg; + unsigned short comman_cfg; + unsigned short command_type; +} __attribute__((packed)) audpp_cmd_cfg_object_params_common; + +/* + * Command Structure to configure post processing params (Volume) + */ + +#define AUDPP_CMD_CFG_OBJECT_PARAMS_VOLUME_LEN \ + sizeof(audpp_cmd_cfg_object_params_volume) + +typedef struct { + audpp_cmd_cfg_object_params_common common; + unsigned short volume; + unsigned short pan; +} __attribute__((packed)) audpp_cmd_cfg_object_params_volume; + +/* + * Command Structure to configure post processing params (PCM Filter) --DOUBT + */ + +typedef struct { + unsigned short numerator_b0_filter_lsw; + unsigned short numerator_b0_filter_msw; + unsigned short numerator_b1_filter_lsw; + unsigned short numerator_b1_filter_msw; + unsigned short numerator_b2_filter_lsw; + unsigned short numerator_b2_filter_msw; +} __attribute__((packed)) numerator; + +typedef struct { + unsigned short denominator_a0_filter_lsw; + unsigned short denominator_a0_filter_msw; + unsigned short denominator_a1_filter_lsw; + unsigned short denominator_a1_filter_msw; +} __attribute__((packed)) denominator; + +typedef struct { + unsigned short shift_factor_0; +} __attribute__((packed)) shift_factor; + +typedef struct { + unsigned short pan_filter_0; +} __attribute__((packed)) pan; + +typedef struct { + numerator numerator_filter; + denominator denominator_filter; + shift_factor shift_factor_filter; + pan pan_filter; +} __attribute__((packed)) filter_1; + +typedef struct { + numerator numerator_filter[2]; + denominator denominator_filter[2]; + shift_factor shift_factor_filter[2]; + pan pan_filter[2]; +} __attribute__((packed)) filter_2; + +typedef struct { + numerator numerator_filter[3]; + denominator denominator_filter[3]; + shift_factor shift_factor_filter[3]; + pan pan_filter[3]; +} __attribute__((packed)) filter_3; + +typedef struct { + numerator numerator_filter[4]; + denominator denominator_filter[4]; + shift_factor shift_factor_filter[4]; + pan pan_filter[4]; +} __attribute__((packed)) filter_4; + +#define AUDPP_CMD_CFG_OBJECT_PARAMS_PCM_LEN \ + sizeof(audpp_cmd_cfg_object_params_pcm) + + +typedef struct { + audpp_cmd_cfg_object_params_common common; + unsigned short active_flag; + unsigned short num_bands; + union { + filter_1 filter_1_params; + filter_2 filter_2_params; + filter_3 filter_3_params; + filter_4 filter_4_params; + } __attribute__((packed)) params_filter; +} __attribute__((packed)) audpp_cmd_cfg_object_params_pcm; + + +/* + * Command Structure to configure post processing parameters (equalizer) + */ + +#define AUDPP_CMD_CFG_OBJECT_PARAMS_EQALIZER_LEN \ + sizeof(audpp_cmd_cfg_object_params_eqalizer) + +typedef struct { + unsigned short numerator_coeff_0_lsw; + unsigned short numerator_coeff_0_msw; + unsigned short numerator_coeff_1_lsw; + unsigned short numerator_coeff_1_msw; + unsigned short numerator_coeff_2_lsw; + unsigned short numerator_coeff_2_msw; +} __attribute__((packed)) eq_numerator; + +typedef struct { + unsigned short denominator_coeff_0_lsw; + unsigned short denominator_coeff_0_msw; + unsigned short denominator_coeff_1_lsw; + unsigned short denominator_coeff_1_msw; +} __attribute__((packed)) eq_denominator; + +typedef struct { + unsigned short shift_factor; +} __attribute__((packed)) eq_shiftfactor; + +typedef struct { + eq_numerator numerator; + eq_denominator denominator; + eq_shiftfactor shiftfactor; +} __attribute__((packed)) eq_coeff_1; + +typedef struct { + eq_numerator numerator[2]; + eq_denominator denominator[2]; + eq_shiftfactor shiftfactor[2]; +} __attribute__((packed)) eq_coeff_2; + +typedef struct { + eq_numerator numerator[3]; + eq_denominator denominator[3]; + eq_shiftfactor shiftfactor[3]; +} __attribute__((packed)) eq_coeff_3; + +typedef struct { + eq_numerator numerator[4]; + eq_denominator denominator[4]; + eq_shiftfactor shiftfactor[4]; +} __attribute__((packed)) eq_coeff_4; + +typedef struct { + eq_numerator numerator[5]; + eq_denominator denominator[5]; + eq_shiftfactor shiftfactor[5]; +} __attribute__((packed)) eq_coeff_5; + +typedef struct { + eq_numerator numerator[6]; + eq_denominator denominator[6]; + eq_shiftfactor shiftfactor[6]; +} __attribute__((packed)) eq_coeff_6; + +typedef struct { + eq_numerator numerator[7]; + eq_denominator denominator[7]; + eq_shiftfactor shiftfactor[7]; +} __attribute__((packed)) eq_coeff_7; + +typedef struct { + eq_numerator numerator[8]; + eq_denominator denominator[8]; + eq_shiftfactor shiftfactor[8]; +} __attribute__((packed)) eq_coeff_8; + +typedef struct { + eq_numerator numerator[9]; + eq_denominator denominator[9]; + eq_shiftfactor shiftfactor[9]; +} __attribute__((packed)) eq_coeff_9; + +typedef struct { + eq_numerator numerator[10]; + eq_denominator denominator[10]; + eq_shiftfactor shiftfactor[10]; +} __attribute__((packed)) eq_coeff_10; + +typedef struct { + eq_numerator numerator[11]; + eq_denominator denominator[11]; + eq_shiftfactor shiftfactor[11]; +} __attribute__((packed)) eq_coeff_11; + +typedef struct { + eq_numerator numerator[12]; + eq_denominator denominator[12]; + eq_shiftfactor shiftfactor[12]; +} __attribute__((packed)) eq_coeff_12; + + +typedef struct { + audpp_cmd_cfg_object_params_common common; + unsigned short eq_flag; + unsigned short num_bands; + union { + eq_coeff_1 eq_coeffs_1; + eq_coeff_2 eq_coeffs_2; + eq_coeff_3 eq_coeffs_3; + eq_coeff_4 eq_coeffs_4; + eq_coeff_5 eq_coeffs_5; + eq_coeff_6 eq_coeffs_6; + eq_coeff_7 eq_coeffs_7; + eq_coeff_8 eq_coeffs_8; + eq_coeff_9 eq_coeffs_9; + eq_coeff_10 eq_coeffs_10; + eq_coeff_11 eq_coeffs_11; + eq_coeff_12 eq_coeffs_12; + } __attribute__((packed)) eq_coeff; +} __attribute__((packed)) audpp_cmd_cfg_object_params_eqalizer; + + +/* + * Command Structure to configure post processing parameters (ADRC) + */ + +#define AUDPP_CMD_CFG_OBJECT_PARAMS_ADRC_LEN \ + sizeof(audpp_cmd_cfg_object_params_adrc) + + +#define AUDPP_CMD_ADRC_FLAG_DIS 0x0000 +#define AUDPP_CMD_ADRC_FLAG_ENA -1 + +typedef struct { + audpp_cmd_cfg_object_params_common common; + signed short adrc_flag; + unsigned short compression_th; + unsigned short compression_slope; + unsigned short rms_time; + unsigned short attack_const_lsw; + unsigned short attack_const_msw; + unsigned short release_const_lsw; + unsigned short release_const_msw; + unsigned short adrc_system_delay; +} __attribute__((packed)) audpp_cmd_cfg_object_params_adrc; + +/* + * Command Structure to configure post processing parameters(Spectrum Analizer) + */ + +#define AUDPP_CMD_CFG_OBJECT_PARAMS_SPECTRAM_LEN \ + sizeof(audpp_cmd_cfg_object_params_spectram) + + +typedef struct { + audpp_cmd_cfg_object_params_common common; + unsigned short sample_interval; + unsigned short num_coeff; +} __attribute__((packed)) audpp_cmd_cfg_object_params_spectram; + +/* + * Command Structure to configure post processing parameters (QConcert) + */ + +#define AUDPP_CMD_CFG_OBJECT_PARAMS_QCONCERT_LEN \ + sizeof(audpp_cmd_cfg_object_params_qconcert) + + +#define AUDPP_CMD_QCON_ENA_FLAG_ENA -1 +#define AUDPP_CMD_QCON_ENA_FLAG_DIS 0x0000 + +#define AUDPP_CMD_QCON_OP_MODE_HEADPHONE -1 +#define AUDPP_CMD_QCON_OP_MODE_SPEAKER_FRONT 0x0000 +#define AUDPP_CMD_QCON_OP_MODE_SPEAKER_SIDE 0x0001 +#define AUDPP_CMD_QCON_OP_MODE_SPEAKER_DESKTOP 0x0002 + +#define AUDPP_CMD_QCON_GAIN_UNIT 0x7FFF +#define AUDPP_CMD_QCON_GAIN_SIX_DB 0x4027 + + +#define AUDPP_CMD_QCON_EXPANSION_MAX 0x7FFF + + +typedef struct { + audpp_cmd_cfg_object_params_common common; + signed short enable_flag; + signed short output_mode; + signed short gain; + signed short expansion; + signed short delay; + unsigned short stages_per_mode; +} __attribute__((packed)) audpp_cmd_cfg_object_params_qconcert; + +/* + * Command Structure to configure post processing parameters (Side Chain) + */ + +#define AUDPP_CMD_CFG_OBJECT_PARAMS_SIDECHAIN_LEN \ + sizeof(audpp_cmd_cfg_object_params_sidechain) + + +#define AUDPP_CMD_SIDECHAIN_ACTIVE_FLAG_DIS 0x0000 +#define AUDPP_CMD_SIDECHAIN_ACTIVE_FLAG_ENA -1 + +typedef struct { + audpp_cmd_cfg_object_params_common common; + signed short active_flag; + unsigned short num_bands; + union { + filter_1 filter_1_params; + filter_2 filter_2_params; + filter_3 filter_3_params; + filter_4 filter_4_params; + } __attribute__((packed)) params_filter; +} __attribute__((packed)) audpp_cmd_cfg_object_params_sidechain; + + +/* + * Command Structure to configure post processing parameters (QAFX) + */ + +#define AUDPP_CMD_CFG_OBJECT_PARAMS_QAFX_LEN \ + sizeof(audpp_cmd_cfg_object_params_qafx) + +#define AUDPP_CMD_QAFX_ENA_DISA 0x0000 +#define AUDPP_CMD_QAFX_ENA_ENA_CFG -1 +#define AUDPP_CMD_QAFX_ENA_DIS_CFG 0x0001 + +#define AUDPP_CMD_QAFX_CMD_TYPE_ENV 0x0100 +#define AUDPP_CMD_QAFX_CMD_TYPE_OBJ 0x0010 +#define AUDPP_CMD_QAFX_CMD_TYPE_QUERY 0x1000 + +#define AUDPP_CMD_QAFX_CMDS_ENV_OP_MODE 0x0100 +#define AUDPP_CMD_QAFX_CMDS_ENV_LIS_POS 0x0101 +#define AUDPP_CMD_QAFX_CMDS_ENV_LIS_ORI 0x0102 +#define AUDPP_CMD_QAFX_CMDS_ENV_LIS_VEL 0X0103 +#define AUDPP_CMD_QAFX_CMDS_ENV_ENV_RES 0x0107 + +#define AUDPP_CMD_QAFX_CMDS_OBJ_SAMP_FREQ 0x0010 +#define AUDPP_CMD_QAFX_CMDS_OBJ_VOL 0x0011 +#define AUDPP_CMD_QAFX_CMDS_OBJ_DIST 0x0012 +#define AUDPP_CMD_QAFX_CMDS_OBJ_POS 0x0013 +#define AUDPP_CMD_QAFX_CMDS_OBJ_VEL 0x0014 + + +typedef struct { + audpp_cmd_cfg_object_params_common common; + signed short enable; + unsigned short command_type; + unsigned short num_commands; + unsigned short commands; +} __attribute__((packed)) audpp_cmd_cfg_object_params_qafx; + +/* + * Command Structure to enable , disable or configure the reverberation effect + * (Common) + */ + +#define AUDPP_CMD_REVERB_CONFIG 0x0001 +#define AUDPP_CMD_REVERB_CONFIG_COMMON_LEN \ + sizeof(audpp_cmd_reverb_config_common) + +#define AUDPP_CMD_ENA_ENA 0xFFFF +#define AUDPP_CMD_ENA_DIS 0x0000 +#define AUDPP_CMD_ENA_CFG 0x0001 + +#define AUDPP_CMD_CMD_TYPE_ENV 0x0104 +#define AUDPP_CMD_CMD_TYPE_OBJ 0x0015 +#define AUDPP_CMD_CMD_TYPE_QUERY 0x1000 + + +typedef struct { + unsigned short cmd_id; + unsigned short enable; + unsigned short cmd_type; +} __attribute__((packed)) audpp_cmd_reverb_config_common; + +/* + * Command Structure to enable , disable or configure the reverberation effect + * (ENV-0x0104) + */ + +#define AUDPP_CMD_REVERB_CONFIG_ENV_104_LEN \ + sizeof(audpp_cmd_reverb_config_env_104) + +typedef struct { + audpp_cmd_reverb_config_common common; + unsigned short env_gain; + unsigned short decay_msw; + unsigned short decay_lsw; + unsigned short decay_timeratio_msw; + unsigned short decay_timeratio_lsw; + unsigned short delay_time; + unsigned short reverb_gain; + unsigned short reverb_delay; +} __attribute__((packed)) audpp_cmd_reverb_config_env_104; + +/* + * Command Structure to enable , disable or configure the reverberation effect + * (ENV-0x0015) + */ + +#define AUDPP_CMD_REVERB_CONFIG_ENV_15_LEN \ + sizeof(audpp_cmd_reverb_config_env_15) + +typedef struct { + audpp_cmd_reverb_config_common common; + unsigned short object_num; + unsigned short absolute_gain; +} __attribute__((packed)) audpp_cmd_reverb_config_env_15; + + +#endif /* QDSP5AUDPPCMDI_H */ + diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5audppmsg.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5audppmsg.h new file mode 100644 index 000000000000..44fea224001a --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5audppmsg.h @@ -0,0 +1,318 @@ +#ifndef QDSP5AUDPPMSG_H +#define QDSP5AUDPPMSG_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + Q D S P 5 A U D I O P O S T P R O C E S S I N G M S G + +GENERAL DESCRIPTION + Messages sent by AUDPPTASK to ARM + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2009 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + + $Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audppmsg.h#4 $ + +===========================================================================*/ + +/* + * AUDPPTASK uses audPPuPRlist to send messages to the ARM + * Location : MEMA + * Buffer Size : 45 + * No of Buffers in a queue : 5 for gaming audio and 1 for other images + */ + +/* + * MSG to Informs the ARM os Success/Failure of bringing up the decoder + */ + +#define AUDPP_MSG_STATUS_MSG 0x0001 +#define AUDPP_MSG_STATUS_MSG_LEN \ + sizeof(audpp_msg_status_msg) + +#define AUDPP_MSG_STATUS_SLEEP 0x0000 +#define AUDPP_MSG__STATUS_INIT 0x0001 +#define AUDPP_MSG_MSG_STATUS_CFG 0x0002 +#define AUDPP_MSG_STATUS_PLAY 0x0003 + +#define AUDPP_MSG_REASON_MIPS 0x0000 +#define AUDPP_MSG_REASON_MEM 0x0001 + +typedef struct{ + unsigned short dec_id; + unsigned short status; + unsigned short reason; +} __attribute__((packed)) audpp_msg_status_msg; + +/* + * MSG to communicate the spectrum analyzer output bands to the ARM + */ +#define AUDPP_MSG_SPA_BANDS 0x0002 +#define AUDPP_MSG_SPA_BANDS_LEN \ + sizeof(audpp_msg_spa_bands) + +typedef struct { + unsigned short current_object; + unsigned short spa_band_1; + unsigned short spa_band_2; + unsigned short spa_band_3; + unsigned short spa_band_4; + unsigned short spa_band_5; + unsigned short spa_band_6; + unsigned short spa_band_7; + unsigned short spa_band_8; + unsigned short spa_band_9; + unsigned short spa_band_10; + unsigned short spa_band_11; + unsigned short spa_band_12; + unsigned short spa_band_13; + unsigned short spa_band_14; + unsigned short spa_band_15; + unsigned short spa_band_16; + unsigned short spa_band_17; + unsigned short spa_band_18; + unsigned short spa_band_19; + unsigned short spa_band_20; + unsigned short spa_band_21; + unsigned short spa_band_22; + unsigned short spa_band_23; + unsigned short spa_band_24; + unsigned short spa_band_25; + unsigned short spa_band_26; + unsigned short spa_band_27; + unsigned short spa_band_28; + unsigned short spa_band_29; + unsigned short spa_band_30; + unsigned short spa_band_31; + unsigned short spa_band_32; +} __attribute__((packed)) audpp_msg_spa_bands; + +/* + * MSG to communicate the PCM I/O buffer status to ARM + */ +#define AUDPP_MSG_HOST_PCM_INTF_MSG 0x0003 +#define AUDPP_MSG_HOST_PCM_INTF_MSG_LEN \ + sizeof(audpp_msg_host_pcm_intf_msg) + +#define AUDPP_MSG_HOSTPCM_ID_TX_ARM 0x0000 +#define AUDPP_MSG_HOSTPCM_ID_ARM_TX 0x0001 +#define AUDPP_MSG_HOSTPCM_ID_RX_ARM 0x0002 +#define AUDPP_MSG_HOSTPCM_ID_ARM_RX 0x0003 + +#define AUDPP_MSG_SAMP_FREQ_INDX_96000 0x0000 +#define AUDPP_MSG_SAMP_FREQ_INDX_88200 0x0001 +#define AUDPP_MSG_SAMP_FREQ_INDX_64000 0x0002 +#define AUDPP_MSG_SAMP_FREQ_INDX_48000 0x0003 +#define AUDPP_MSG_SAMP_FREQ_INDX_44100 0x0004 +#define AUDPP_MSG_SAMP_FREQ_INDX_32000 0x0005 +#define AUDPP_MSG_SAMP_FREQ_INDX_24000 0x0006 +#define AUDPP_MSG_SAMP_FREQ_INDX_22050 0x0007 +#define AUDPP_MSG_SAMP_FREQ_INDX_16000 0x0008 +#define AUDPP_MSG_SAMP_FREQ_INDX_12000 0x0009 +#define AUDPP_MSG_SAMP_FREQ_INDX_11025 0x000A +#define AUDPP_MSG_SAMP_FREQ_INDX_8000 0x000B + +#define AUDPP_MSG_CHANNEL_MODE_MONO 0x0001 +#define AUDPP_MSG_CHANNEL_MODE_STEREO 0x0002 + +typedef struct{ + unsigned short obj_num; + unsigned short numbers_of_samples; + unsigned short host_pcm_id; + unsigned short buf_indx; + unsigned short samp_freq_indx; + unsigned short channel_mode; +} __attribute__((packed)) audpp_msg_host_pcm_intf_msg; + + +/* + * MSG to communicate 3D position of the source and listener , source volume + * source rolloff, source orientation + */ + +#define AUDPP_MSG_QAFX_POS 0x0004 +#define AUDPP_MSG_QAFX_POS_LEN \ + sizeof(audpp_msg_qafx_pos) + +typedef struct { + unsigned short current_object; + unsigned short x_pos_lis_msw; + unsigned short x_pos_lis_lsw; + unsigned short y_pos_lis_msw; + unsigned short y_pos_lis_lsw; + unsigned short z_pos_lis_msw; + unsigned short z_pos_lis_lsw; + unsigned short x_fwd_msw; + unsigned short x_fwd_lsw; + unsigned short y_fwd_msw; + unsigned short y_fwd_lsw; + unsigned short z_fwd_msw; + unsigned short z_fwd_lsw; + unsigned short x_up_msw; + unsigned short x_up_lsw; + unsigned short y_up_msw; + unsigned short y_up_lsw; + unsigned short z_up_msw; + unsigned short z_up_lsw; + unsigned short x_vel_lis_msw; + unsigned short x_vel_lis_lsw; + unsigned short y_vel_lis_msw; + unsigned short y_vel_lis_lsw; + unsigned short z_vel_lis_msw; + unsigned short z_vel_lis_lsw; + unsigned short threed_enable_flag; + unsigned short volume; + unsigned short x_pos_source_msw; + unsigned short x_pos_source_lsw; + unsigned short y_pos_source_msw; + unsigned short y_pos_source_lsw; + unsigned short z_pos_source_msw; + unsigned short z_pos_source_lsw; + unsigned short max_dist_0_msw; + unsigned short max_dist_0_lsw; + unsigned short min_dist_0_msw; + unsigned short min_dist_0_lsw; + unsigned short roll_off_factor; + unsigned short mute_after_max_flag; + unsigned short x_vel_source_msw; + unsigned short x_vel_source_lsw; + unsigned short y_vel_source_msw; + unsigned short y_vel_source_lsw; + unsigned short z_vel_source_msw; + unsigned short z_vel_source_lsw; +} __attribute__((packed)) audpp_msg_qafx_pos; + +/* + * MSG to provide AVSYNC feedback from DSP to ARM + */ + +#define AUDPP_MSG_AVSYNC_MSG 0x0005 +#define AUDPP_MSG_AVSYNC_MSG_LEN \ + sizeof(audpp_msg_avsync_msg) + +typedef struct { + unsigned short active_flag; + unsigned short num_samples_counter0_HSW; + unsigned short num_samples_counter0_MSW; + unsigned short num_samples_counter0_LSW; + unsigned short num_bytes_counter0_HSW; + unsigned short num_bytes_counter0_MSW; + unsigned short num_bytes_counter0_LSW; + unsigned short samp_freq_obj_0; + unsigned short samp_freq_obj_1; + unsigned short samp_freq_obj_2; + unsigned short samp_freq_obj_3; + unsigned short samp_freq_obj_4; + unsigned short samp_freq_obj_5; + unsigned short samp_freq_obj_6; + unsigned short samp_freq_obj_7; + unsigned short samp_freq_obj_8; + unsigned short samp_freq_obj_9; + unsigned short samp_freq_obj_10; + unsigned short samp_freq_obj_11; + unsigned short samp_freq_obj_12; + unsigned short samp_freq_obj_13; + unsigned short samp_freq_obj_14; + unsigned short samp_freq_obj_15; + unsigned short num_samples_counter4_HSW; + unsigned short num_samples_counter4_MSW; + unsigned short num_samples_counter4_LSW; + unsigned short num_bytes_counter4_HSW; + unsigned short num_bytes_counter4_MSW; + unsigned short num_bytes_counter4_LSW; +} __attribute__((packed)) audpp_msg_avsync_msg; + +/* + * MSG to provide PCM DMA Missed feedback from the DSP to ARM + */ + +#define AUDPP_MSG_PCMDMAMISSED 0x0006 +#define AUDPP_MSG_PCMDMAMISSED_LEN \ + sizeof(audpp_msg_pcmdmamissed); + +typedef struct{ + /* + ** Bit 0 0 = PCM DMA not missed for object 0 + ** 1 = PCM DMA missed for object0 + ** Bit 1 0 = PCM DMA not missed for object 1 + ** 1 = PCM DMA missed for object1 + ** Bit 2 0 = PCM DMA not missed for object 2 + ** 1 = PCM DMA missed for object2 + ** Bit 3 0 = PCM DMA not missed for object 3 + ** 1 = PCM DMA missed for object3 + ** Bit 4 0 = PCM DMA not missed for object 4 + ** 1 = PCM DMA missed for object4 + */ + unsigned short pcmdmamissed; +} __attribute__((packed)) audpp_msg_pcmdmamissed; + +/* + * MSG to AUDPP enable or disable feedback form DSP to ARM + */ + +#define AUDPP_MSG_CFG_MSG 0x0007 +#define AUDPP_MSG_CFG_MSG_LEN \ + sizeof(audpp_msg_cfg_msg) + +#define AUDPP_MSG_ENA_ENA 0xFFFF +#define AUDPP_MSG_ENA_DIS 0x0000 + +typedef struct{ + /* Enabled - 0xffff + ** Disabled - 0 + */ + unsigned short enabled; +} __attribute__((packed)) audpp_msg_cfg_msg; + +/* + * MSG to communicate the reverb per object volume + */ + +#define AUDPP_MSG_QREVERB_VOLUME 0x0008 +#define AUDPP_MSG_QREVERB_VOLUME_LEN \ + sizeof(audpp_msg_qreverb_volume) + + +typedef struct { + unsigned short obj_0_gain; + unsigned short obj_1_gain; + unsigned short obj_2_gain; + unsigned short obj_3_gain; + unsigned short obj_4_gain; + unsigned short hpcm_obj_volume; +} __attribute__((packed)) audpp_msg_qreverb_volume; + +#define AUDPP_MSG_ROUTING_ACK 0x0009 +#define AUDPP_MSG_ROUTING_ACK_LEN \ + sizeof(struct audpp_msg_routing_ack) + +struct audpp_msg_routing_ack { + unsigned short dec_id; + unsigned short routing_mode; +} __attribute__((packed)); + +#define AUDPP_MSG_FLUSH_ACK 0x000A + +#endif /* QDSP5AUDPPMSG_H */ diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5audpreproccmdi.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5audpreproccmdi.h new file mode 100644 index 000000000000..06d33d571583 --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5audpreproccmdi.h @@ -0,0 +1,256 @@ +#ifndef QDSP5AUDPREPROCCMDI_H +#define QDSP5AUDPREPROCCMDI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + A U D I O P R E P R O C E S S I N G I N T E R N A L C O M M A N D S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of commands + that are accepted by AUDPREPROC Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audpreproccmdi.h#2 $ + +===========================================================================*/ + +/* + * AUDIOPREPROC COMMANDS: + * ARM uses uPAudPreProcCmdQueue to communicate with AUDPREPROCTASK + * Location : MEMB + * Buffer size : 51 + * Number of buffers in a queue : 3 + */ + +/* + * Command to configure the parameters of AGC + */ + +#define AUDPREPROC_CMD_CFG_AGC_PARAMS 0x0000 +#define AUDPREPROC_CMD_CFG_AGC_PARAMS_LEN \ + sizeof(audpreproc_cmd_cfg_agc_params) + +#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_COMP_SLOPE 0x0009 +#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_COMP_TH 0x000A +#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_EXP_SLOPE 0x000B +#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_EXP_TH 0x000C +#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_COMP_AIG_FLAG 0x000D +#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_COMP_STATIC_GAIN 0x000E +#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_TX_AGC_ENA_FLAG 0x000F + +#define AUDPREPROC_CMD_TX_AGC_ENA_FLAG_ENA -1 +#define AUDPREPROC_CMD_TX_AGC_ENA_FLAG_DIS 0x0000 + +#define AUDPREPROC_CMD_ADP_GAIN_FLAG_ENA_ADP_GAIN -1 +#define AUDPREPROC_CMD_ADP_GAIN_FLAG_ENA_STATIC_GAIN 0x0000 + +#define AUDPREPROC_CMD_PARAM_MASK_RMS_TAY 0x0004 +#define AUDPREPROC_CMD_PARAM_MASK_RELEASEK 0x0005 +#define AUDPREPROC_CMD_PARAM_MASK_DELAY 0x0006 +#define AUDPREPROC_CMD_PARAM_MASK_ATTACKK 0x0007 +#define AUDPREPROC_CMD_PARAM_MASK_LEAKRATE_SLOW 0x0008 +#define AUDPREPROC_CMD_PARAM_MASK_LEAKRATE_FAST 0x0009 +#define AUDPREPROC_CMD_PARAM_MASK_AIG_RELEASEK 0x000A +#define AUDPREPROC_CMD_PARAM_MASK_AIG_MIN 0x000B +#define AUDPREPROC_CMD_PARAM_MASK_AIG_MAX 0x000C +#define AUDPREPROC_CMD_PARAM_MASK_LEAK_UP 0x000D +#define AUDPREPROC_CMD_PARAM_MASK_LEAK_DOWN 0x000E +#define AUDPREPROC_CMD_PARAM_MASK_AIG_ATTACKK 0x000F + +typedef struct { + unsigned short cmd_id; + unsigned short tx_agc_param_mask; + unsigned short tx_agc_enable_flag; + unsigned short static_gain; + signed short adaptive_gain_flag; + unsigned short expander_th; + unsigned short expander_slope; + unsigned short compressor_th; + unsigned short compressor_slope; + unsigned short param_mask; + unsigned short aig_attackk; + unsigned short aig_leak_down; + unsigned short aig_leak_up; + unsigned short aig_max; + unsigned short aig_min; + unsigned short aig_releasek; + unsigned short aig_leakrate_fast; + unsigned short aig_leakrate_slow; + unsigned short attackk_msw; + unsigned short attackk_lsw; + unsigned short delay; + unsigned short releasek_msw; + unsigned short releasek_lsw; + unsigned short rms_tav; +} __attribute__((packed)) audpreproc_cmd_cfg_agc_params; + + +/* + * Command to configure the params of Advanved AGC + */ + +#define AUDPREPROC_CMD_CFG_AGC_PARAMS_2 0x0001 +#define AUDPREPROC_CMD_CFG_AGC_PARAMS_2_LEN \ + sizeof(audpreproc_cmd_cfg_agc_params_2) + +#define AUDPREPROC_CMD_2_TX_AGC_ENA_FLAG_ENA -1; +#define AUDPREPROC_CMD_2_TX_AGC_ENA_FLAG_DIS 0x0000; + +typedef struct { + unsigned short cmd_id; + unsigned short agc_param_mask; + signed short tx_agc_enable_flag; + unsigned short comp_static_gain; + unsigned short exp_th; + unsigned short exp_slope; + unsigned short comp_th; + unsigned short comp_slope; + unsigned short comp_rms_tav; + unsigned short comp_samp_mask; + unsigned short comp_attackk_msw; + unsigned short comp_attackk_lsw; + unsigned short comp_releasek_msw; + unsigned short comp_releasek_lsw; + unsigned short comp_delay; + unsigned short comp_makeup_gain; +} __attribute__((packed)) audpreproc_cmd_cfg_agc_params_2; + +/* + * Command to configure params for ns + */ + +#define AUDPREPROC_CMD_CFG_NS_PARAMS 0x0002 +#define AUDPREPROC_CMD_CFG_NS_PARAMS_LEN \ + sizeof(audpreproc_cmd_cfg_ns_params) + +#define AUDPREPROC_CMD_EC_MODE_NEW_NLMS_ENA 0x0001 +#define AUDPREPROC_CMD_EC_MODE_NEW_NLMS_DIS 0x0000 +#define AUDPREPROC_CMD_EC_MODE_NEW_DES_ENA 0x0002 +#define AUDPREPROC_CMD_EC_MODE_NEW_DES_DIS 0x0000 +#define AUDPREPROC_CMD_EC_MODE_NEW_NS_ENA 0x0004 +#define AUDPREPROC_CMD_EC_MODE_NEW_NS_DIS 0x0000 +#define AUDPREPROC_CMD_EC_MODE_NEW_CNI_ENA 0x0008 +#define AUDPREPROC_CMD_EC_MODE_NEW_CNI_DIS 0x0000 + +#define AUDPREPROC_CMD_EC_MODE_NEW_NLES_ENA 0x0010 +#define AUDPREPROC_CMD_EC_MODE_NEW_NLES_DIS 0x0000 +#define AUDPREPROC_CMD_EC_MODE_NEW_HB_ENA 0x0020 +#define AUDPREPROC_CMD_EC_MODE_NEW_HB_DIS 0x0000 +#define AUDPREPROC_CMD_EC_MODE_NEW_VA_ENA 0x0040 +#define AUDPREPROC_CMD_EC_MODE_NEW_VA_DIS 0x0000 +#define AUDPREPROC_CMD_EC_MODE_NEW_PCD_ENA 0x0080 +#define AUDPREPROC_CMD_EC_MODE_NEW_PCD_DIS 0x0000 +#define AUDPREPROC_CMD_EC_MODE_NEW_FEHI_ENA 0x0100 +#define AUDPREPROC_CMD_EC_MODE_NEW_FEHI_DIS 0x0000 +#define AUDPREPROC_CMD_EC_MODE_NEW_NEHI_ENA 0x0200 +#define AUDPREPROC_CMD_EC_MODE_NEW_NEHI_DIS 0x0000 +#define AUDPREPROC_CMD_EC_MODE_NEW_NLPP_ENA 0x0400 +#define AUDPREPROC_CMD_EC_MODE_NEW_NLPP_DIS 0x0000 +#define AUDPREPROC_CMD_EC_MODE_NEW_FNE_ENA 0x0800 +#define AUDPREPROC_CMD_EC_MODE_NEW_FNE_DIS 0x0000 +#define AUDPREPROC_CMD_EC_MODE_NEW_PRENLMS_ENA 0x1000 +#define AUDPREPROC_CMD_EC_MODE_NEW_PRENLMS_DIS 0x0000 + +typedef struct { + unsigned short cmd_id; + unsigned short ec_mode_new; + unsigned short dens_gamma_n; + unsigned short dens_nfe_block_size; + unsigned short dens_limit_ns; + unsigned short dens_limit_ns_d; + unsigned short wb_gamma_e; + unsigned short wb_gamma_n; +} __attribute__((packed)) audpreproc_cmd_cfg_ns_params; + +/* + * Command to configure parameters for IIR tuning filter + */ + +#define AUDPREPROC_CMD_CFG_IIR_TUNING_FILTER_PARAMS 0x0003 +#define AUDPREPROC_CMD_CFG_IIR_TUNING_FILTER_PARAMS_LEN \ + sizeof(audpreproc_cmd_cfg_iir_tuning_filter_params) + +#define AUDPREPROC_CMD_IIR_ACTIVE_FLAG_DIS 0x0000 +#define AUDPREPROC_CMD_IIR_ACTIVE_FLAG_ENA 0x0001 + +typedef struct { + unsigned short cmd_id; + unsigned short active_flag; + unsigned short num_bands; + unsigned short numerator_coeff_b0_filter0_lsw; + unsigned short numerator_coeff_b0_filter0_msw; + unsigned short numerator_coeff_b1_filter0_lsw; + unsigned short numerator_coeff_b1_filter0_msw; + unsigned short numerator_coeff_b2_filter0_lsw; + unsigned short numerator_coeff_b2_filter0_msw; + unsigned short numerator_coeff_b0_filter1_lsw; + unsigned short numerator_coeff_b0_filter1_msw; + unsigned short numerator_coeff_b1_filter1_lsw; + unsigned short numerator_coeff_b1_filter1_msw; + unsigned short numerator_coeff_b2_filter1_lsw; + unsigned short numerator_coeff_b2_filter1_msw; + unsigned short numerator_coeff_b0_filter2_lsw; + unsigned short numerator_coeff_b0_filter2_msw; + unsigned short numerator_coeff_b1_filter2_lsw; + unsigned short numerator_coeff_b1_filter2_msw; + unsigned short numerator_coeff_b2_filter2_lsw; + unsigned short numerator_coeff_b2_filter2_msw; + unsigned short numerator_coeff_b0_filter3_lsw; + unsigned short numerator_coeff_b0_filter3_msw; + unsigned short numerator_coeff_b1_filter3_lsw; + unsigned short numerator_coeff_b1_filter3_msw; + unsigned short numerator_coeff_b2_filter3_lsw; + unsigned short numerator_coeff_b2_filter3_msw; + unsigned short denominator_coeff_a0_filter0_lsw; + unsigned short denominator_coeff_a0_filter0_msw; + unsigned short denominator_coeff_a1_filter0_lsw; + unsigned short denominator_coeff_a1_filter0_msw; + unsigned short denominator_coeff_a0_filter1_lsw; + unsigned short denominator_coeff_a0_filter1_msw; + unsigned short denominator_coeff_a1_filter1_lsw; + unsigned short denominator_coeff_a1_filter1_msw; + unsigned short denominator_coeff_a0_filter2_lsw; + unsigned short denominator_coeff_a0_filter2_msw; + unsigned short denominator_coeff_a1_filter2_lsw; + unsigned short denominator_coeff_a1_filter2_msw; + unsigned short denominator_coeff_a0_filter3_lsw; + unsigned short denominator_coeff_a0_filter3_msw; + unsigned short denominator_coeff_a1_filter3_lsw; + unsigned short denominator_coeff_a1_filter3_msw; + + unsigned short shift_factor_filter0; + unsigned short shift_factor_filter1; + unsigned short shift_factor_filter2; + unsigned short shift_factor_filter3; + + unsigned short channel_selected0; + unsigned short channel_selected1; + unsigned short channel_selected2; + unsigned short channel_selected3; +} __attribute__((packed))audpreproc_cmd_cfg_iir_tuning_filter_params; + +#endif diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5audpreprocmsg.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5audpreprocmsg.h new file mode 100644 index 000000000000..f40e41e76737 --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5audpreprocmsg.h @@ -0,0 +1,85 @@ +#ifndef QDSP5AUDPREPROCMSG_H +#define QDSP5AUDPREPROCMSG_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + A U D I O P R E P R O C E S S I N G M E S S A G E S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of messages + that are rcvd by AUDPREPROC Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + + $Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audpreprocmsg.h#3 $ + +===========================================================================*/ + +/* + * ADSPREPROCTASK Messages + * AUDPREPROCTASK uses audPreProcUpRlist to communicate with ARM + * Location : MEMA + * Message Length : 2 + */ + +/* + * Message to indicate particular feature has been enabled or disabled + */ + + +#define AUDPREPROC_MSG_CMD_CFG_DONE_MSG 0x0000 +#define AUDPREPROC_MSG_CMD_CFG_DONE_MSG_LEN \ + sizeof(audpreproc_msg_cmd_cfg_done_msg) + +#define AUDPREPROC_MSG_TYPE_AGC 0x0000 +#define AUDPREPROC_MSG_TYPE_NOISE_REDUCTION 0x0001 +#define AUDPREPROC_MSG_TYPE_IIR_FILTER 0x0002 + + +#define AUDPREPROC_MSG_STATUS_FLAG_ENA -1 +#define AUDPREPROC_MSG_STATUS_FLAG_DIS 0x0000 + +typedef struct { + unsigned short type; + signed short status_flag; +} __attribute__((packed)) audpreproc_msg_cmd_cfg_done_msg; + + +/* + * Message to indicate particular feature has selected for wrong samp freq + */ + +#define AUDPREPROC_MSG_ERROR_MSG_ID 0x0001 +#define AUDPREPROC_MSG_ERROR_MSG_ID_LEN \ + sizeof(audpreproc_msg_error_msg_id) + +#define AUDPREPROC_MSG_ERR_INDEX_NS 0x0000 + +typedef struct { + unsigned short err_index; +} __attribute__((packed)) audpreproc_msg_error_msg_id; + +#endif diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5audreccmdi.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5audreccmdi.h new file mode 100644 index 000000000000..d03ee024ae91 --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5audreccmdi.h @@ -0,0 +1,176 @@ +#ifndef QDSP5AUDRECCMDI_H +#define QDSP5AUDRECCMDI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + A U D I O R E C O R D I N T E R N A L C O M M A N D S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of commands + that are accepted by AUDREC Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ + +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + + $Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audreccmdi.h#3 $ + +============================================================================*/ + +/* + * AUDRECTASK COMMANDS + * ARM uses 2 queues to communicate with the AUDRECTASK + * 1.uPAudRecCmdQueue + * Location :MEMC + * Buffer Size : 8 + * No of Buffers in a queue : 3 + * 2.audRecUpBitStreamQueue + * Location : MEMC + * Buffer Size : 4 + * No of buffers in a queue : 2 + */ + +/* + * Commands on uPAudRecCmdQueue + */ + +/* + * Command to initiate and terminate the audio recording section + */ + +#define AUDREC_CMD_CFG 0x0000 +#define AUDREC_CMD_CFG_LEN sizeof(audrec_cmd_cfg) + +#define AUDREC_CMD_TYPE_0_INDEX_WAV 0x0000 +#define AUDREC_CMD_TYPE_0_INDEX_AAC 0x0001 + +#define AUDREC_CMD_TYPE_0_ENA 0x4000 +#define AUDREC_CMD_TYPE_0_DIS 0x0000 + +#define AUDREC_CMD_TYPE_0_NOUPDATE 0x0000 +#define AUDREC_CMD_TYPE_0_UPDATE 0x8000 + +#define AUDREC_CMD_TYPE_1_INDEX_SBC 0x0002 + +#define AUDREC_CMD_TYPE_1_ENA 0x4000 +#define AUDREC_CMD_TYPE_1_DIS 0x0000 + +#define AUDREC_CMD_TYPE_1_NOUPDATE 0x0000 +#define AUDREC_CMD_TYPE_1_UPDATE 0x8000 + +typedef struct { + unsigned short cmd_id; + unsigned short type_0; + unsigned short type_1; +} __attribute__((packed)) audrec_cmd_cfg; + + +/* + * Command to configure the recording parameters for RecType0(AAC/WAV) encoder + */ + +#define AUDREC_CMD_AREC0PARAM_CFG 0x0001 +#define AUDREC_CMD_AREC0PARAM_CFG_LEN \ + sizeof(audrec_cmd_arec0param_cfg) + +#define AUDREC_CMD_SAMP_RATE_INDX_8000 0x000B +#define AUDREC_CMD_SAMP_RATE_INDX_11025 0x000A +#define AUDREC_CMD_SAMP_RATE_INDX_12000 0x0009 +#define AUDREC_CMD_SAMP_RATE_INDX_16000 0x0008 +#define AUDREC_CMD_SAMP_RATE_INDX_22050 0x0007 +#define AUDREC_CMD_SAMP_RATE_INDX_24000 0x0006 +#define AUDREC_CMD_SAMP_RATE_INDX_32000 0x0005 +#define AUDREC_CMD_SAMP_RATE_INDX_44100 0x0004 +#define AUDREC_CMD_SAMP_RATE_INDX_48000 0x0003 + +#define AUDREC_CMD_STEREO_MODE_MONO 0x0000 +#define AUDREC_CMD_STEREO_MODE_STEREO 0x0001 + +typedef struct { + unsigned short cmd_id; + unsigned short ptr_to_extpkt_buffer_msw; + unsigned short ptr_to_extpkt_buffer_lsw; + unsigned short buf_len; + unsigned short samp_rate_index; + unsigned short stereo_mode; + unsigned short rec_quality; +} __attribute__((packed)) audrec_cmd_arec0param_cfg; + +/* + * Command to configure the recording parameters for RecType1(SBC) encoder + */ + +#define AUDREC_CMD_AREC1PARAM_CFG 0x0002 +#define AUDREC_CMD_AREC1PARAM_CFG_LEN \ + sizeof(audrec_cmd_arec1param_cfg) + +#define AUDREC_CMD_PARAM_BUF_BLOCKS_4 0x0000 +#define AUDREC_CMD_PARAM_BUF_BLOCKS_8 0x0001 +#define AUDREC_CMD_PARAM_BUF_BLOCKS_12 0x0002 +#define AUDREC_CMD_PARAM_BUF_BLOCKS_16 0x0003 + +#define AUDREC_CMD_PARAM_BUF_SUB_BANDS_8 0x0010 +#define AUDREC_CMD_PARAM_BUF_MODE_MONO 0x0000 +#define AUDREC_CMD_PARAM_BUF_MODE_DUAL 0x0040 +#define AUDREC_CMD_PARAM_BUF_MODE_STEREO 0x0050 +#define AUDREC_CMD_PARAM_BUF_MODE_JSTEREO 0x0060 +#define AUDREC_CMD_PARAM_BUF_LOUDNESS 0x0000 +#define AUDREC_CMD_PARAM_BUF_SNR 0x0100 +#define AUDREC_CMD_PARAM_BUF_BASIC_VER 0x0000 + +typedef struct { + unsigned short cmd_id; + unsigned short ptr_to_extpkt_buffer_msw; + unsigned short ptr_to_extpkt_buffer_lsw; + unsigned short buf_len; + unsigned short param_buf; + unsigned short bit_rate_0; + unsigned short bit_rate_1; +} __attribute__((packed)) audrec_cmd_arec1param_cfg; + + +/* + * Commands on audRecUpBitStreamQueue + */ + +/* + * Command to indicate the current packet read count + */ + +#define AUDREC_CMD_PACKET_EXT_PTR 0x0000 +#define AUDREC_CMD_PACKET_EXT_PTR_LEN \ + sizeof(audrec_cmd_packet_ext_ptr) + +#define AUDREC_CMD_TYPE_0 0x0000 +#define AUDREC_CMD_TYPE_1 0x0001 + +typedef struct { + unsigned short cmd_id; + unsigned short type; + unsigned short curr_rec_count_msw; + unsigned short curr_rec_count_lsw; +} __attribute__((packed)) audrec_cmd_packet_ext_ptr; + +#endif diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5audrecmsg.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5audrecmsg.h new file mode 100644 index 000000000000..bb6eb5093cf5 --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5audrecmsg.h @@ -0,0 +1,127 @@ +#ifndef QDSP5AUDRECMSGI_H +#define QDSP5AUDRECMSGI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + A U D I O R E C O R D M E S S A G E S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of messages + that are sent by AUDREC Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ + +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + + $Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audrecmsg.h#3 $ + +============================================================================*/ + +/* + * AUDRECTASK MESSAGES + * AUDRECTASK uses audRecUpRlist to communicate with ARM + * Location : MEMC + * Buffer size : 4 + * No of buffers in a queue : 2 + */ + +/* + * Message to notify that config command is done + */ + +#define AUDREC_MSG_CMD_CFG_DONE_MSG 0x0002 +#define AUDREC_MSG_CMD_CFG_DONE_MSG_LEN \ + sizeof(audrec_msg_cmd_cfg_done_msg) + + +#define AUDREC_MSG_CFG_DONE_TYPE_0_ENA 0x4000 +#define AUDREC_MSG_CFG_DONE_TYPE_0_DIS 0x0000 + +#define AUDREC_MSG_CFG_DONE_TYPE_0_NO_UPDATE 0x0000 +#define AUDREC_MSG_CFG_DONE_TYPE_0_UPDATE 0x8000 + +#define AUDREC_MSG_CFG_DONE_TYPE_1_ENA 0x4000 +#define AUDREC_MSG_CFG_DONE_TYPE_1_DIS 0x0000 + +#define AUDREC_MSG_CFG_DONE_TYPE_1_NO_UPDATE 0x0000 +#define AUDREC_MSG_CFG_DONE_TYPE_1_UPDATE 0x8000 + +typedef struct { + unsigned short type_0; + unsigned short type_1; +} __attribute__((packed))audrec_msg_cmd_cfg_done_msg; + + +/* + * Message to notify arec0/1 cfg done and recording params revd by task + */ + +#define AUDREC_MSG_CMD_AREC_PARAM_CFG_DONE_MSG 0x0003 +#define AUDREC_MSG_CMD_AREC_PARAM_CFG_DONE_MSG_LEN \ + sizeof(audrec_msg_cmd_arec_param_cfg_done_msg) + +#define AUDREC_MSG_AREC_PARAM_TYPE_0 0x0000 +#define AUDREC_MSG_AREC_PARAM_TYPE_1 0x0001 + +typedef struct { + unsigned short type; +} __attribute__((packed))audrec_msg_cmd_arec_param_cfg_done_msg; + + +/* + * Message to notify no more buffers are available in ext mem to DME + */ + +#define AUDREC_MSG_FATAL_ERR_MSG 0x0004 +#define AUDREC_MSG_FATAL_ERR_MSG_LEN \ + sizeof(audrec_msg_fatal_err_msg) + +#define AUDREC_MSG_FATAL_ERR_TYPE_0 0x0000 +#define AUDREC_MSG_FATAL_ERR_TYPE_1 0x0001 + +typedef struct { + unsigned short type; +} __attribute__((packed))audrec_msg_fatal_err_msg; + +/* + * Message to notify DME deliverd the encoded pkt to ext pkt buffer + */ + +#define AUDREC_MSG_PACKET_READY_MSG 0x0005 +#define AUDREC_MSG_PACKET_READY_MSG_LEN \ + sizeof(audrec_msg_packet_ready_msg) + +#define AUDREC_MSG_PACKET_READY_TYPE_0 0x0000 +#define AUDREC_MSG_PACKET_READY_TYPE_1 0x0001 + +typedef struct { + unsigned short type; + unsigned short pkt_counter_msw; + unsigned short pkt_counter_lsw; + unsigned short pkt_read_cnt_msw; + unsigned short pkt_read_cnt_lsw; +} __attribute__((packed))audrec_msg_packet_ready_msg; + +#endif diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5jpegcmdi.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5jpegcmdi.h new file mode 100644 index 000000000000..574ad6bbcade --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5jpegcmdi.h @@ -0,0 +1,376 @@ +#ifndef QDSP5VIDJPEGCMDI_H +#define QDSP5VIDJPEGCMDI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + J P E G I N T E R N A L C O M M A N D S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of commands + that are accepted by JPEG Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5jpegcmdi.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $ +Revision History: +when who what, where, why +-------- --- ---------------------------------------------------------- +06/09/08 sv initial version +===========================================================================*/ + +/* + * ARM to JPEG configuration commands are passed through the + * uPJpegCfgCmdQueue + */ + +/* + * Command to configure JPEG Encoder + */ + +#define JPEG_CMD_ENC_CFG 0x0000 +#define JPEG_CMD_ENC_CFG_LEN sizeof(jpeg_cmd_enc_cfg) + +#define JPEG_CMD_ENC_PROCESS_CFG_OP_ROTATION_0 0x0000 +#define JPEG_CMD_ENC_PROCESS_CFG_OP_ROTATION_90 0x0100 +#define JPEG_CMD_ENC_PROCESS_CFG_OP_ROTATION_180 0x0200 +#define JPEG_CMD_ENC_PROCESS_CFG_OP_ROTATION_270 0x0300 +#define JPEG_CMD_ENC_PROCESS_CFG_IP_DATA_FORMAT_M 0x0003 +#define JPEG_CMD_ENC_PROCESS_CFG_IP_DATA_FORMAT_H2V2 0x0000 +#define JPEG_CMD_ENC_PROCESS_CFG_IP_DATA_FORMAT_H2V1 0x0001 +#define JPEG_CMD_ENC_PROCESS_CFG_IP_DATA_FORMAT_H1V2 0x0002 + +#define JPEG_CMD_IP_SIZE_CFG_LUMA_HEIGHT_M 0x0000FFFF +#define JPEG_CMD_IP_SIZE_CFG_LUMA_WIDTH_M 0xFFFF0000 +#define JPEG_CMD_ENC_UPSAMP_IP_SIZE_CFG_ENA 0x0001 +#define JPEG_CMD_ENC_UPSAMP_IP_SIZE_CFG_DIS 0x0000 + +#define JPEG_CMD_FRAG_SIZE_LUMA_HEIGHT_M 0xFFFF + +typedef struct { + unsigned int cmd_id; + unsigned int process_cfg; + unsigned int ip_size_cfg; + unsigned int op_size_cfg; + unsigned int frag_cfg; + unsigned int frag_cfg_part[16]; + + unsigned int part_num; + + unsigned int op_buf_0_cfg_part1; + unsigned int op_buf_0_cfg_part2; + unsigned int op_buf_1_cfg_part1; + unsigned int op_buf_1_cfg_part2; + + unsigned int luma_qunt_table[32]; + unsigned int chroma_qunt_table[32]; + + unsigned int upsamp_ip_size_cfg; + unsigned int upsamp_ip_frame_off; + unsigned int upsamp_pp_filter_coeff[64]; +} __attribute__((packed)) jpeg_cmd_enc_cfg; + +/* + * Command to configure JPEG Decoder + */ + +#define JPEG_CMD_DEC_CFG 0x0001 +#define JPEG_CMD_DEC_CFG_LEN sizeof(jpeg_cmd_dec_cfg) + +#define JPEG_CMD_DEC_OP_DATA_FORMAT_M 0x0001 +#define JPEG_CMD_DEC_OP_DATA_FORMAT_H2V2 0x0000 +#define JPEG_CMD_DEC_OP_DATA_FORMAT_H2V1 0x0001 + +#define JPEG_CMD_DEC_OP_DATA_FORMAT_SCALE_FACTOR_8 0x000000 +#define JPEG_CMD_DEC_OP_DATA_FORMAT_SCALE_FACTOR_4 0x010000 +#define JPEG_CMD_DEC_OP_DATA_FORMAT_SCALE_FACTOR_2 0x020000 +#define JPEG_CMD_DEC_OP_DATA_FORMAT_SCALE_FACTOR_1 0x030000 + +#define JPEG_CMD_DEC_IP_STREAM_BUF_CFG_PART3_NOT_FINAL 0x0000 +#define JPEG_CMD_DEC_IP_STREAM_BUF_CFG_PART3_FINAL 0x0001 + + +typedef struct { + unsigned int cmd_id; + unsigned int img_dimension_cfg; + unsigned int op_data_format; + unsigned int restart_interval; + unsigned int ip_buf_partition_num; + unsigned int ip_stream_buf_cfg_part1; + unsigned int ip_stream_buf_cfg_part2; + unsigned int ip_stream_buf_cfg_part3; + unsigned int op_stream_buf_0_cfg_part1; + unsigned int op_stream_buf_0_cfg_part2; + unsigned int op_stream_buf_0_cfg_part3; + unsigned int op_stream_buf_1_cfg_part1; + unsigned int op_stream_buf_1_cfg_part2; + unsigned int op_stream_buf_1_cfg_part3; + unsigned int luma_qunt_table_0_3; + unsigned int luma_qunt_table_4_7; + unsigned int luma_qunt_table_8_11; + unsigned int luma_qunt_table_12_15; + unsigned int luma_qunt_table_16_19; + unsigned int luma_qunt_table_20_23; + unsigned int luma_qunt_table_24_27; + unsigned int luma_qunt_table_28_31; + unsigned int luma_qunt_table_32_35; + unsigned int luma_qunt_table_36_39; + unsigned int luma_qunt_table_40_43; + unsigned int luma_qunt_table_44_47; + unsigned int luma_qunt_table_48_51; + unsigned int luma_qunt_table_52_55; + unsigned int luma_qunt_table_56_59; + unsigned int luma_qunt_table_60_63; + unsigned int chroma_qunt_table_0_3; + unsigned int chroma_qunt_table_4_7; + unsigned int chroma_qunt_table_8_11; + unsigned int chroma_qunt_table_12_15; + unsigned int chroma_qunt_table_16_19; + unsigned int chroma_qunt_table_20_23; + unsigned int chroma_qunt_table_24_27; + unsigned int chroma_qunt_table_28_31; + unsigned int chroma_qunt_table_32_35; + unsigned int chroma_qunt_table_36_39; + unsigned int chroma_qunt_table_40_43; + unsigned int chroma_qunt_table_44_47; + unsigned int chroma_qunt_table_48_51; + unsigned int chroma_qunt_table_52_55; + unsigned int chroma_qunt_table_56_59; + unsigned int chroma_qunt_table_60_63; + unsigned int luma_dc_hm_code_cnt_table_0_3; + unsigned int luma_dc_hm_code_cnt_table_4_7; + unsigned int luma_dc_hm_code_cnt_table_8_11; + unsigned int luma_dc_hm_code_cnt_table_12_15; + unsigned int luma_dc_hm_code_val_table_0_3; + unsigned int luma_dc_hm_code_val_table_4_7; + unsigned int luma_dc_hm_code_val_table_8_11; + unsigned int chroma_dc_hm_code_cnt_table_0_3; + unsigned int chroma_dc_hm_code_cnt_table_4_7; + unsigned int chroma_dc_hm_code_cnt_table_8_11; + unsigned int chroma_dc_hm_code_cnt_table_12_15; + unsigned int chroma_dc_hm_code_val_table_0_3; + unsigned int chroma_dc_hm_code_val_table_4_7; + unsigned int chroma_dc_hm_code_val_table_8_11; + unsigned int luma_ac_hm_code_cnt_table_0_3; + unsigned int luma_ac_hm_code_cnt_table_4_7; + unsigned int luma_ac_hm_code_cnt_table_8_11; + unsigned int luma_ac_hm_code_cnt_table_12_15; + unsigned int luma_ac_hm_code_val_table_0_3; + unsigned int luma_ac_hm_code_val_table_4_7; + unsigned int luma_ac_hm_code_val_table_8_11; + unsigned int luma_ac_hm_code_val_table_12_15; + unsigned int luma_ac_hm_code_val_table_16_19; + unsigned int luma_ac_hm_code_val_table_20_23; + unsigned int luma_ac_hm_code_val_table_24_27; + unsigned int luma_ac_hm_code_val_table_28_31; + unsigned int luma_ac_hm_code_val_table_32_35; + unsigned int luma_ac_hm_code_val_table_36_39; + unsigned int luma_ac_hm_code_val_table_40_43; + unsigned int luma_ac_hm_code_val_table_44_47; + unsigned int luma_ac_hm_code_val_table_48_51; + unsigned int luma_ac_hm_code_val_table_52_55; + unsigned int luma_ac_hm_code_val_table_56_59; + unsigned int luma_ac_hm_code_val_table_60_63; + unsigned int luma_ac_hm_code_val_table_64_67; + unsigned int luma_ac_hm_code_val_table_68_71; + unsigned int luma_ac_hm_code_val_table_72_75; + unsigned int luma_ac_hm_code_val_table_76_79; + unsigned int luma_ac_hm_code_val_table_80_83; + unsigned int luma_ac_hm_code_val_table_84_87; + unsigned int luma_ac_hm_code_val_table_88_91; + unsigned int luma_ac_hm_code_val_table_92_95; + unsigned int luma_ac_hm_code_val_table_96_99; + unsigned int luma_ac_hm_code_val_table_100_103; + unsigned int luma_ac_hm_code_val_table_104_107; + unsigned int luma_ac_hm_code_val_table_108_111; + unsigned int luma_ac_hm_code_val_table_112_115; + unsigned int luma_ac_hm_code_val_table_116_119; + unsigned int luma_ac_hm_code_val_table_120_123; + unsigned int luma_ac_hm_code_val_table_124_127; + unsigned int luma_ac_hm_code_val_table_128_131; + unsigned int luma_ac_hm_code_val_table_132_135; + unsigned int luma_ac_hm_code_val_table_136_139; + unsigned int luma_ac_hm_code_val_table_140_143; + unsigned int luma_ac_hm_code_val_table_144_147; + unsigned int luma_ac_hm_code_val_table_148_151; + unsigned int luma_ac_hm_code_val_table_152_155; + unsigned int luma_ac_hm_code_val_table_156_159; + unsigned int luma_ac_hm_code_val_table_160_161; + unsigned int chroma_ac_hm_code_cnt_table_0_3; + unsigned int chroma_ac_hm_code_cnt_table_4_7; + unsigned int chroma_ac_hm_code_cnt_table_8_11; + unsigned int chroma_ac_hm_code_cnt_table_12_15; + unsigned int chroma_ac_hm_code_val_table_0_3; + unsigned int chroma_ac_hm_code_val_table_4_7; + unsigned int chroma_ac_hm_code_val_table_8_11; + unsigned int chroma_ac_hm_code_val_table_12_15; + unsigned int chroma_ac_hm_code_val_table_16_19; + unsigned int chroma_ac_hm_code_val_table_20_23; + unsigned int chroma_ac_hm_code_val_table_24_27; + unsigned int chroma_ac_hm_code_val_table_28_31; + unsigned int chroma_ac_hm_code_val_table_32_35; + unsigned int chroma_ac_hm_code_val_table_36_39; + unsigned int chroma_ac_hm_code_val_table_40_43; + unsigned int chroma_ac_hm_code_val_table_44_47; + unsigned int chroma_ac_hm_code_val_table_48_51; + unsigned int chroma_ac_hm_code_val_table_52_55; + unsigned int chroma_ac_hm_code_val_table_56_59; + unsigned int chroma_ac_hm_code_val_table_60_63; + unsigned int chroma_ac_hm_code_val_table_64_67; + unsigned int chroma_ac_hm_code_val_table_68_71; + unsigned int chroma_ac_hm_code_val_table_72_75; + unsigned int chroma_ac_hm_code_val_table_76_79; + unsigned int chroma_ac_hm_code_val_table_80_83; + unsigned int chroma_ac_hm_code_val_table_84_87; + unsigned int chroma_ac_hm_code_val_table_88_91; + unsigned int chroma_ac_hm_code_val_table_92_95; + unsigned int chroma_ac_hm_code_val_table_96_99; + unsigned int chroma_ac_hm_code_val_table_100_103; + unsigned int chroma_ac_hm_code_val_table_104_107; + unsigned int chroma_ac_hm_code_val_table_108_111; + unsigned int chroma_ac_hm_code_val_table_112_115; + unsigned int chroma_ac_hm_code_val_table_116_119; + unsigned int chroma_ac_hm_code_val_table_120_123; + unsigned int chroma_ac_hm_code_val_table_124_127; + unsigned int chroma_ac_hm_code_val_table_128_131; + unsigned int chroma_ac_hm_code_val_table_132_135; + unsigned int chroma_ac_hm_code_val_table_136_139; + unsigned int chroma_ac_hm_code_val_table_140_143; + unsigned int chroma_ac_hm_code_val_table_144_147; + unsigned int chroma_ac_hm_code_val_table_148_151; + unsigned int chroma_ac_hm_code_val_table_152_155; + unsigned int chroma_ac_hm_code_val_table_156_159; + unsigned int chroma_ac_hm_code_val_table_160_161; +} __attribute__((packed)) jpeg_cmd_dec_cfg; + + +/* + * ARM to JPEG configuration commands are passed through the + * uPJpegActionCmdQueue + */ + +/* + * Command to start the encode process + */ + +#define JPEG_CMD_ENC_ENCODE 0x0000 +#define JPEG_CMD_ENC_ENCODE_LEN sizeof(jpeg_cmd_enc_encode) + + +typedef struct { + unsigned short cmd_id; +} __attribute__((packed)) jpeg_cmd_enc_encode; + + +/* + * Command to transition from current state of encoder to IDLE state + */ + +#define JPEG_CMD_ENC_IDLE 0x0001 +#define JPEG_CMD_ENC_IDLE_LEN sizeof(jpeg_cmd_enc_idle) + + +typedef struct { + unsigned short cmd_id; +} __attribute__((packed)) jpeg_cmd_enc_idle; + + +/* + * Command to inform the encoder that another buffer is ready + */ + +#define JPEG_CMD_ENC_OP_CONSUMED 0x0002 +#define JPEG_CMD_ENC_OP_CONSUMED_LEN sizeof(jpeg_cmd_enc_op_consumed) + + +typedef struct { + unsigned int cmd_id; + unsigned int op_buf_addr; + unsigned int op_buf_size; +} __attribute__((packed)) jpeg_cmd_enc_op_consumed; + + +/* + * Command to start the decoding process + */ + +#define JPEG_CMD_DEC_DECODE 0x0003 +#define JPEG_CMD_DEC_DECODE_LEN sizeof(jpeg_cmd_dec_decode) + + +typedef struct { + unsigned short cmd_id; +} __attribute__((packed)) jpeg_cmd_dec_decode; + + +/* + * Command to transition from the current state of decoder to IDLE + */ + +#define JPEG_CMD_DEC_IDLE 0x0004 +#define JPEG_CMD_DEC_IDLE_LEN sizeof(jpeg_cmd_dec_idle) + + +typedef struct { + unsigned short cmd_id; +} __attribute__((packed)) jpeg_cmd_dec_idle; + + +/* + * Command to inform that an op buffer is ready for use + */ + +#define JPEG_CMD_DEC_OP_CONSUMED 0x0005 +#define JPEG_CMD_DEC_OP_CONSUMED_LEN sizeof(jpeg_cmd_dec_op_consumed) + + +typedef struct { + unsigned int cmd_id; + unsigned int luma_op_buf_addr; + unsigned int luma_op_buf_size; + unsigned int chroma_op_buf_addr; +} __attribute__((packed)) jpeg_cmd_dec_op_consumed; + + +/* + * Command to pass a new ip buffer to the jpeg decoder + */ + +#define JPEG_CMD_DEC_IP 0x0006 +#define JPEG_CMD_DEC_IP_LEN sizeof(jpeg_cmd_dec_ip_len) + +#define JPEG_CMD_EOI_INDICATOR_NOT_END 0x0000 +#define JPEG_CMD_EOI_INDICATOR_END 0x0001 + +typedef struct { + unsigned int cmd_id; + unsigned int ip_buf_addr; + unsigned int ip_buf_size; + unsigned int eoi_indicator; +} __attribute__((packed)) jpeg_cmd_dec_ip; + + + +#endif diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5jpegmsg.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5jpegmsg.h new file mode 100644 index 000000000000..d11aa3fbccb6 --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5jpegmsg.h @@ -0,0 +1,177 @@ +#ifndef QDSP5VIDJPEGMSGI_H +#define QDSP5VIDJPEGMSGI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + J P E G I N T E R N A L M E S S A G E S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of messages + that are sent by JPEG Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5jpegmsg.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $ +Revision History: + +when who what, where, why +-------- --- ---------------------------------------------------------- +05/10/08 sv initial version +===========================================================================*/ + +/* + * Messages from JPEG task to ARM through jpeguPMsgQueue + */ + +/* + * Message is ACK for CMD_JPEGE_ENCODE cmd + */ + +#define JPEG_MSG_ENC_ENCODE_ACK 0x0000 +#define JPEG_MSG_ENC_ENCODE_ACK_LEN \ + sizeof(jpeg_msg_enc_encode_ack) + +typedef struct { +} __attribute__((packed)) jpeg_msg_enc_encode_ack; + + +/* + * Message informs the up when op buffer is ready for consumption and + * when encoding is complete or errors + */ + +#define JPEG_MSG_ENC_OP_PRODUCED 0x0001 +#define JPEG_MSG_ENC_OP_PRODUCED_LEN \ + sizeof(jpeg_msg_enc_op_produced) + +#define JPEG_MSGOP_OP_BUF_STATUS_ENC_DONE_PROGRESS 0x0000 +#define JPEG_MSGOP_OP_BUF_STATUS_ENC_DONE_COMPLETE 0x0001 +#define JPEG_MSGOP_OP_BUF_STATUS_ENC_ERR 0x10000 + +typedef struct { + unsigned int op_buf_addr; + unsigned int op_buf_size; + unsigned int op_buf_status; +} __attribute__((packed)) jpeg_msg_enc_op_produced; + + +/* + * Message to ack CMD_JPEGE_IDLE + */ + +#define JPEG_MSG_ENC_IDLE_ACK 0x0002 +#define JPEG_MSG_ENC_IDLE_ACK_LEN sizeof(jpeg_msg_enc_idle_ack) + + +typedef struct { +} __attribute__ ((packed)) jpeg_msg_enc_idle_ack; + + +/* + * Message to indicate the illegal command + */ + +#define JPEG_MSG_ENC_ILLEGAL_COMMAND 0x0003 +#define JPEG_MSG_ENC_ILLEGAL_COMMAND_LEN \ + sizeof(jpeg_msg_enc_illegal_command) + +typedef struct { + unsigned int status; +} __attribute__((packed)) jpeg_msg_enc_illegal_command; + + +/* + * Message to ACK CMD_JPEGD_DECODE + */ + +#define JPEG_MSG_DEC_DECODE_ACK 0x0004 +#define JPEG_MSG_DEC_DECODE_ACK_LEN \ + sizeof(jpeg_msg_dec_decode_ack) + + +typedef struct { +} __attribute__((packed)) jpeg_msg_dec_decode_ack; + + +/* + * Message to inform up that an op buffer is ready for consumption and when + * decoding is complete or an error occurs + */ + +#define JPEG_MSG_DEC_OP_PRODUCED 0x0005 +#define JPEG_MSG_DEC_OP_PRODUCED_LEN \ + sizeof(jpeg_msg_dec_op_produced) + +#define JPEG_MSG_DEC_OP_BUF_STATUS_PROGRESS 0x0000 +#define JPEG_MSG_DEC_OP_BUF_STATUS_DONE 0x0001 + +typedef struct { + unsigned int luma_op_buf_addr; + unsigned int chroma_op_buf_addr; + unsigned int num_mcus; + unsigned int op_buf_status; +} __attribute__((packed)) jpeg_msg_dec_op_produced; + +/* + * Message to ack CMD_JPEGD_IDLE cmd + */ + +#define JPEG_MSG_DEC_IDLE_ACK 0x0006 +#define JPEG_MSG_DEC_IDLE_ACK_LEN sizeof(jpeg_msg_dec_idle_ack) + + +typedef struct { +} __attribute__((packed)) jpeg_msg_dec_idle_ack; + + +/* + * Message to indicate illegal cmd was received + */ + +#define JPEG_MSG_DEC_ILLEGAL_COMMAND 0x0007 +#define JPEG_MSG_DEC_ILLEGAL_COMMAND_LEN \ + sizeof(jpeg_msg_dec_illegal_command) + + +typedef struct { + unsigned int status; +} __attribute__((packed)) jpeg_msg_dec_illegal_command; + +/* + * Message to request up for the next segment of ip bit stream + */ + +#define JPEG_MSG_DEC_IP_REQUEST 0x0008 +#define JPEG_MSG_DEC_IP_REQUEST_LEN \ + sizeof(jpeg_msg_dec_ip_request) + + +typedef struct { +} __attribute__((packed)) jpeg_msg_dec_ip_request; + + + +#endif diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5lpmcmdi.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5lpmcmdi.h new file mode 100644 index 000000000000..6c76e2c20cf4 --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5lpmcmdi.h @@ -0,0 +1,82 @@ +#ifndef QDSP5LPMCMDI_H +#define QDSP5LPMCMDI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + L P M I N T E R N A L C O M M A N D S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of commands + that are accepted by LPM Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + + +$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5lpmcmdi.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $ +Revision History: + +when who what, where, why +-------- --- ---------------------------------------------------------- +06/12/08 sv initial version +===========================================================================*/ + + +/* + * Command to start LPM processing based on the config params + */ + +#define LPM_CMD_START 0x0000 +#define LPM_CMD_START_LEN sizeof(lpm_cmd_start) + +#define LPM_CMD_SPATIAL_FILTER_PART_OPMODE_0 0x00000000 +#define LPM_CMD_SPATIAL_FILTER_PART_OPMODE_1 0x00010000 +typedef struct { + unsigned int cmd_id; + unsigned int ip_data_cfg_part1; + unsigned int ip_data_cfg_part2; + unsigned int ip_data_cfg_part3; + unsigned int ip_data_cfg_part4; + unsigned int op_data_cfg_part1; + unsigned int op_data_cfg_part2; + unsigned int op_data_cfg_part3; + unsigned int spatial_filter_part[32]; +} __attribute__((packed)) lpm_cmd_start; + + + +/* + * Command to stop LPM processing + */ + +#define LPM_CMD_IDLE 0x0001 +#define LPM_CMD_IDLE_LEN sizeof(lpm_cmd_idle) + +typedef struct { + unsigned int cmd_id; +} __attribute__((packed)) lpm_cmd_idle; + + +#endif diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5lpmmsg.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5lpmmsg.h new file mode 100644 index 000000000000..3d1039d6ba42 --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5lpmmsg.h @@ -0,0 +1,80 @@ +#ifndef QDSP5LPMMSGI_H +#define QDSP5LPMMSGI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + L P M I N T E R N A L M E S S A G E S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of commands + that are accepted by LPM Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5lpmmsg.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $ +Revision History: + +when who what, where, why +-------- --- ---------------------------------------------------------- +06/12/08 sv initial version +===========================================================================*/ + +/* + * Message to acknowledge CMD_LPM_IDLE command + */ + +#define LPM_MSG_IDLE_ACK 0x0000 +#define LPM_MSG_IDLE_ACK_LEN sizeof(lpm_msg_idle_ack) + +typedef struct { +} __attribute__((packed)) lpm_msg_idle_ack; + + +/* + * Message to acknowledge CMD_LPM_START command + */ + + +#define LPM_MSG_START_ACK 0x0001 +#define LPM_MSG_START_ACK_LEN sizeof(lpm_msg_start_ack) + + +typedef struct { +} __attribute__((packed)) lpm_msg_start_ack; + + +/* + * Message to notify the ARM that LPM processing is complete + */ + +#define LPM_MSG_DONE 0x0002 +#define LPM_MSG_DONE_LEN sizeof(lpm_msg_done) + +typedef struct { +} __attribute__((packed)) lpm_msg_done; + + +#endif diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5vdeccmdi.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5vdeccmdi.h new file mode 100644 index 000000000000..3a32ee99c6e4 --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5vdeccmdi.h @@ -0,0 +1,235 @@ +#ifndef QDSP5VIDDECCMDI_H +#define QDSP5VIDDECCMDI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + V I D E O D E C O D E R I N T E R N A L C O M M A N D S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of commands + that are accepted by VIDDEC Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5vdeccmdi.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $ +Revision History: + +when who what, where, why +-------- --- ---------------------------------------------------------- +05/10/08 ac initial version +===========================================================================*/ + + +/* + * Command to inform VIDDEC that new subframe packet is ready + */ + +#define VIDDEC_CMD_SUBFRAME_PKT 0x0000 +#define VIDDEC_CMD_SUBFRAME_PKT_LEN \ + sizeof(viddec_cmd_subframe_pkt) + +#define VIDDEC_CMD_SF_INFO_1_DM_DMA_STATS_EXCHANGE_FLAG_DM 0x0000 +#define VIDDEC_CMD_SF_INFO_1_DM_DMA_STATS_EXCHANGE_FLAG_DMA 0x0001 + +#define VIDDEC_CMD_SF_INFO_0_SUBFRAME_CONTI 0x0000 +#define VIDDEC_CMD_SF_INFO_0_SUBFRAME_FIRST 0x0001 +#define VIDDEC_CMD_SF_INFO_0_SUBFRAME_LAST 0x0002 +#define VIDDEC_CMD_SF_INFO_0_SUBFRAME_FIRST_AND_LAST 0x0003 + +#define VIDDEC_CMD_CODEC_SELECTION_WORD_MPEG_4 0x0000 +#define VIDDEC_CMD_CODEC_SELECTION_WORD_H_263_P0 0x0001 +#define VIDDEC_CMD_CODEC_SELECTION_WORD_H_264 0x0002 +#define VIDDEC_CMD_CODEC_SELECTION_WORD_H_263_p3 0x0003 +#define VIDDEC_CMD_CODEC_SELECTION_WORD_RV9 0x0004 +#define VIDDEC_CMD_CODEC_SELECTION_WORD_WMV9 0x0005 +#define VIDDEC_CMD_CODEC_SELECTION_WORD_SMCDB 0x0006 +#define VIDDEC_CMD_CODEC_SELECTION_WORD_QFRE 0x0007 +#define VIDDEC_CMD_CODEC_SELECTION_WORD_VLD 0x0008 + +typedef struct { + unsigned short cmd_id; + unsigned short packet_seq_number; + unsigned short codec_instance_id; + unsigned short subframe_packet_size_high; + unsigned short subframe_packet_size_low; + unsigned short subframe_packet_high; + unsigned short subframe_packet_low; + unsigned short subframe_packet_partition; + unsigned short statistics_packet_size_high; + unsigned short statistics_packet_size_low; + unsigned short statistics_packet_high; + unsigned short statistics_packet_low; + unsigned short statistics_partition; + unsigned short subframe_info_1; + unsigned short subframe_info_0; + unsigned short codec_selection_word; + unsigned short num_mbs; +} __attribute__((packed)) viddec_cmd_subframe_pkt; + + +/* + * Command to inform VIDDEC task that post processing is required for the frame + */ + +#define VIDDEC_CMD_PP_ENABLE 0x0001 +#define VIDDEC_CMD_PP_ENABLE_LEN \ + sizeof(viddec_cmd_pp_enable) + +#define VIDDEC_CMD_PP_INFO_0_DM_DMA_LS_EXCHANGE_FLAG_DM 0x0000 +#define VIDDEC_CMD_PP_INFO_0_DM_DMA_LS_EXCHANGE_FLAG_DMA 0x0001 + +typedef struct { + unsigned short cmd_id; + unsigned short packet_seq_num; + unsigned short codec_instance_id; + unsigned short postproc_info_0; + unsigned short codec_selection_word; + unsigned short pp_output_addr_high; + unsigned short pp_output_addr_low; + unsigned short postproc_info_1; + unsigned short load_sharing_packet_size_high; + unsigned short load_sharing_packet_size_low; + unsigned short load_sharing_packet_high; + unsigned short load_sharing_packet_low; + unsigned short load_sharing_partition; + unsigned short pp_param_0; + unsigned short pp_param_1; + unsigned short pp_param_2; + unsigned short pp_param_3; +} __attribute__((packed)) viddec_cmd_pp_enable; + + +/* + * FRAME Header Packet : It is at the start of new frame + */ + +#define VIDDEC_CMD_FRAME_HEADER_PACKET 0x0002 +#define VIDDEC_CMD_FRAME_HEADER_PACKET_LEN \ + sizeof(viddec_cmd_frame_header_packet) + +#define VIDDEC_CMD_FRAME_INFO_0_ERROR_SKIP 0x0000 +#define VIDDEC_CMD_FRAME_INFO_0_ERROR_BLACK 0x0800 + +typedef struct { + unsigned short packet_id; + unsigned short x_dimension; + unsigned short y_dimension; + unsigned short line_width; + unsigned short frame_info_0; + unsigned short frame_buffer_0_high; + unsigned short frame_buffer_0_low; + unsigned short frame_buffer_1_high; + unsigned short frame_buffer_1_low; + unsigned short frame_buffer_2_high; + unsigned short frame_buffer_2_low; + unsigned short frame_buffer_3_high; + unsigned short frame_buffer_3_low; + unsigned short frame_buffer_4_high; + unsigned short frame_buffer_4_low; + unsigned short frame_buffer_5_high; + unsigned short frame_buffer_5_low; + unsigned short frame_buffer_6_high; + unsigned short frame_buffer_6_low; + unsigned short frame_buffer_7_high; + unsigned short frame_buffer_7_low; + unsigned short frame_buffer_8_high; + unsigned short frame_buffer_8_low; + unsigned short frame_buffer_9_high; + unsigned short frame_buffer_9_low; + unsigned short frame_buffer_10_high; + unsigned short frame_buffer_10_low; + unsigned short frame_buffer_11_high; + unsigned short frame_buffer_11_low; + unsigned short frame_buffer_12_high; + unsigned short frame_buffer_12_low; + unsigned short frame_buffer_13_high; + unsigned short frame_buffer_13_low; + unsigned short frame_buffer_14_high; + unsigned short frame_buffer_14_low; + unsigned short frame_buffer_15_high; + unsigned short frame_buffer_15_low; + unsigned short output_frame_buffer_high; + unsigned short output_frame_buffer_low; + unsigned short end_of_packet_marker; +} __attribute__((packed)) viddec_cmd_frame_header_packet; + + +/* + * SLICE HEADER PACKET + * I-Slice and P-Slice + */ + +#define VIDDEC_CMD_SLICE_HEADER_PKT_ISLICE 0x0003 +#define VIDDEC_CMD_SLICE_HEADER_PKT_ISLICE_LEN \ + sizeof(viddec_cmd_slice_header_pkt_islice) + +#define VIDDEC_CMD_ISLICE_INFO_1_MOD_SLICE_TYPE_PSLICE 0x0000 +#define VIDDEC_CMD_ISLICE_INFO_1_MOD_SLICE_TYPE_BSLICE 0x0100 +#define VIDDEC_CMD_ISLICE_INFO_1_MOD_SLICE_TYPE_ISLICE 0x0200 +#define VIDDEC_CMD_ISLICE_INFO_1_MOD_SLICE_TYPE_SPSLICE 0x0300 +#define VIDDEC_CMD_ISLICE_INFO_1_MOD_SLICE_TYPE_SISLICE 0x0400 +#define VIDDEC_CMD_ISLICE_INFO_1_NOPADDING 0x0000 +#define VIDDEC_CMD_ISLICE_INFO_1_PADDING 0x0800 + +#define VIDDEC_CMD_ISLICE_EOP_MARKER 0x7FFF + +typedef struct { + unsigned short cmd_id; + unsigned short packet_id; + unsigned short slice_info_0; + unsigned short slice_info_1; + unsigned short slice_info_2; + unsigned short num_bytes_in_rbsp_high; + unsigned short num_bytes_in_rbsp_low; + unsigned short num_bytes_in_rbsp_consumed; + unsigned short end_of_packet_marker; +} __attribute__((packed)) viddec_cmd_slice_header_pkt_islice; + + +#define VIDDEC_CMD_SLICE_HEADER_PKT_PSLICE 0x0003 +#define VIDDEC_CMD_SLICE_HEADER_PKT_PSLICE_LEN \ + sizeof(viddec_cmd_slice_header_pkt_pslice) + + +typedef struct { + unsigned short cmd_id; + unsigned short packet_id; + unsigned short slice_info_0; + unsigned short slice_info_1; + unsigned short slice_info_2; + unsigned short slice_info_3; + unsigned short refidx_l0_map_tab_info_0; + unsigned short refidx_l0_map_tab_info_1; + unsigned short refidx_l0_map_tab_info_2; + unsigned short refidx_l0_map_tab_info_3; + unsigned short num_bytes_in_rbsp_high; + unsigned short num_bytes_in_rbsp_low; + unsigned short num_bytes_in_rbsp_consumed; + unsigned short end_of_packet_marker; +} __attribute__((packed)) viddec_cmd_slice_header_pkt_pslice; + + +#endif diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5vdecmsg.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5vdecmsg.h new file mode 100644 index 000000000000..c1744c1644dd --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5vdecmsg.h @@ -0,0 +1,107 @@ +#ifndef QDSP5VIDDECMSGI_H +#define QDSP5VIDDECMSGI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + V I D E O D E C O D E R I N T E R N A L M E S S A G E S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of messages + that are sent by VIDDEC Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5vdecmsg.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $ +Revision History: + +when who what, where, why +-------- --- ---------------------------------------------------------- +05/10/08 ac initial version +===========================================================================*/ + +/* + * Message to inform ARM which VDEC_SUBFRAME_PKT_CMD processed by VIDDEC TASK + */ + +#define VIDDEC_MSG_SUBF_DONE 0x0000 +#define VIDDEC_MSG_SUBF_DONE_LEN \ + sizeof(viddec_msg_subf_done) + +typedef struct { + unsigned short packet_seq_number; + unsigned short codec_instance_id; +} __attribute__((packed)) viddec_msg_subf_done; + + +/* + * Message to inform ARM one frame has been decoded + */ + +#define VIDDEC_MSG_FRAME_DONE 0x0001 +#define VIDDEC_MSG_FRAME_DONE_LEN \ + sizeof(viddec_msg_frame_done) + +typedef struct { + unsigned short packet_seq_number; + unsigned short codec_instance_id; +} __attribute__((packed)) viddec_msg_frame_done; + + +/* + * Message to inform ARM that post processing frame has been decoded + */ + +#define VIDDEC_MSG_PP_ENABLE_CMD_DONE 0x0002 +#define VIDDEC_MSG_PP_ENABLE_CMD_DONE_LEN \ + sizeof(viddec_msg_pp_enable_cmd_done) + +typedef struct { + unsigned short packet_seq_number; + unsigned short codec_instance_id; +} __attribute__((packed)) viddec_msg_pp_enable_cmd_done; + + +/* + * Message to inform ARM that one post processing frame has been decoded + */ + + +#define VIDDEC_MSG_PP_FRAME_DONE 0x0003 +#define VIDDEC_MSG_PP_FRAME_DONE_LEN \ + sizeof(viddec_msg_pp_frame_done) + +#define VIDDEC_MSG_DISP_WORTHY_DISP 0x0000 +#define VIDDEC_MSG_DISP_WORTHY_DISP_NONE 0xFFFF + + +typedef struct { + unsigned short packet_seq_number; + unsigned short codec_instance_id; + unsigned short display_worthy; +} __attribute__((packed)) viddec_msg_pp_frame_done; + + +#endif diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5venccmdi.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5venccmdi.h new file mode 100644 index 000000000000..819544d186da --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5venccmdi.h @@ -0,0 +1,212 @@ +#ifndef QDSP5VIDENCCMDI_H +#define QDSP5VIDENCCMDI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + V I D E O E N C O D E R I N T E R N A L C O M M A N D S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of commands + that are accepted by VIDENC Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 2008 by QUALCOMM, Incorporated. +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +Revision History: + +when who what, where, why +-------- --- ---------------------------------------------------------- +09/25/08 umeshp initial version +===========================================================================*/ + + #define VIDENC_CMD_CFG 0x0000 + #define VIDENC_CMD_ACTIVE 0x0001 + #define VIDENC_CMD_IDLE 0x0002 + #define VIDENC_CMD_FRAME_START 0x0003 + #define VIDENC_CMD_STATUS_QUERY 0x0004 + #define VIDENC_CMD_RC_CFG 0x0005 + #define VIDENC_CMD_DIS_CFG 0x0006 + #define VIDENC_CMD_DIS 0x0007 + #define VIDENC_CMD_INTRA_REFRESH 0x0008 + #define VIDENC_CMD_DIGITAL_ZOOM 0x0009 + + +/* + * Command to pass the frame message information to VIDENC + */ + + +#define VIDENC_CMD_FRAME_START_LEN \ + sizeof(videnc_cmd_frame_start) + +typedef struct { + unsigned short cmd_id; + unsigned short frame_info; + unsigned short frame_rho_budget_word_high; + unsigned short frame_rho_budget_word_low; + unsigned short input_luma_addr_high; + unsigned short input_luma_addr_low; + unsigned short input_chroma_addr_high; + unsigned short input_chroma_addr_low; + unsigned short ref_vop_buf_ptr_high; + unsigned short ref_vop_buf_ptr_low; + unsigned short enc_pkt_buf_ptr_high; + unsigned short enc_pkt_buf_ptr_low; + unsigned short enc_pkt_buf_size_high; + unsigned short enc_pkt_buf_size_low; + unsigned short unfilt_recon_vop_buf_ptr_high; + unsigned short unfilt_recon_vop_buf_ptr_low; + unsigned short filt_recon_vop_buf_ptr_high; + unsigned short filt_recon_vop_buf_ptr_low; +} __attribute__((packed)) videnc_cmd_frame_start; + +/* + * Command to pass the frame-level digital stabilization parameters to VIDENC + */ + + +#define VIDENC_CMD_DIS_LEN \ + sizeof(videnc_cmd_dis) + +typedef struct { + unsigned short cmd_id; + unsigned short vfe_out_prev_luma_addr_high; + unsigned short vfe_out_prev_luma_addr_low; + unsigned short stabilization_info; +} __attribute__((packed)) videnc_cmd_dis; + +/* + * Command to pass the codec related parameters to VIDENC + */ + + +#define VIDENC_CMD_CFG_LEN \ + sizeof(videnc_cmd_cfg) + +typedef struct { + unsigned short cmd_id; + unsigned short cfg_info_0; + unsigned short cfg_info_1; + unsigned short four_mv_threshold; + unsigned short ise_fse_mv_cost_fac; + unsigned short venc_frame_dim; + unsigned short venc_DM_partition; +} __attribute__((packed)) videnc_cmd_cfg; + +/* + * Command to start the video encoding + */ + + +#define VIDENC_CMD_ACTIVE_LEN \ + sizeof(videnc_cmd_active) + +typedef struct { + unsigned short cmd_id; +} __attribute__((packed)) videnc_cmd_active; + +/* + * Command to stop the video encoding + */ + + +#define VIDENC_CMD_IDLE_LEN \ + sizeof(videnc_cmd_idle) + +typedef struct { + unsigned short cmd_id; +} __attribute__((packed)) videnc_cmd_idle; + +/* + * Command to query staus of VIDENC + */ + + +#define VIDENC_CMD_STATUS_QUERY_LEN \ + sizeof(videnc_cmd_status_query) + +typedef struct { + unsigned short cmd_id; +} __attribute__((packed)) videnc_cmd_status_query; + +/* + * Command to set rate control for a frame + */ + + +#define VIDENC_CMD_RC_CFG_LEN \ + sizeof(videnc_cmd_rc_cfg) + +typedef struct { + unsigned short cmd_id; + unsigned short max_frame_qp_delta; + unsigned short max_min_frame_qp; +} __attribute__((packed)) videnc_cmd_rc_cfg; + +/* + * Command to set intra-refreshing + */ + + +#define VIDENC_CMD_INTRA_REFRESH_LEN \ + sizeof(videnc_cmd_intra_refresh) + +typedef struct { + unsigned short cmd_id; + unsigned short num_mb_refresh; + unsigned short mb_index[15]; +} __attribute__((packed)) videnc_cmd_intra_refresh; + +/* + * Command to pass digital zoom information to the VIDENC + */ +#define VIDENC_CMD_DIGITAL_ZOOM_LEN \ + sizeof(videnc_cmd_digital_zoom) + +typedef struct { + unsigned short cmd_id; + unsigned short digital_zoom_en; + unsigned short luma_frame_shift_X; + unsigned short luma_frame_shift_Y; + unsigned short up_ip_luma_rows; + unsigned short up_ip_luma_cols; + unsigned short up_ip_chroma_rows; + unsigned short up_ip_chroma_cols; + unsigned short luma_ph_incr_V_low; + unsigned short luma_ph_incr_V_high; + unsigned short luma_ph_incr_H_low; + unsigned short luma_ph_incr_H_high; + unsigned short chroma_ph_incr_V_low; + unsigned short chroma_ph_incr_V_high; + unsigned short chroma_ph_incr_H_low; + unsigned short chroma_ph_incr_H_high; +} __attribute__((packed)) videnc_cmd_digital_zoom; + +/* + * Command to configure digital stabilization parameters + */ + +#define VIDENC_CMD_DIS_CFG_LEN \ + sizeof(videnc_cmd_dis_cfg) + +typedef struct { + unsigned short cmd_id; + unsigned short image_stab_subf_start_row_col; + unsigned short image_stab_subf_dim; + unsigned short image_stab_info_0; +} __attribute__((packed)) videnc_cmd_dis_cfg; + + +#endif diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5vfecmdi.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5vfecmdi.h new file mode 100644 index 000000000000..55e8fc2269f7 --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5vfecmdi.h @@ -0,0 +1,910 @@ +#ifndef QDSP5VFECMDI_H +#define QDSP5VFECMDI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + V F E I N T E R N A L C O M M A N D S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of commands + that are accepted by VFE Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5vfecmdi.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $ +Revision History: + +when who what, where, why +-------- --- ---------------------------------------------------------- +06/12/08 sv initial version +===========================================================================*/ + +/****************************************************************************** + * Commands through vfeCommandScaleQueue + *****************************************************************************/ + +/* + * Command to program scaler for op1 . max op of scaler is VGA + */ + + +#define VFE_CMD_SCALE_OP1_CFG 0x0000 +#define VFE_CMD_SCALE_OP1_CFG_LEN \ + sizeof(vfe_cmd_scale_op1_cfg) + +#define VFE_CMD_SCALE_OP1_SEL_IP_SEL_Y_STANDARD 0x0000 +#define VFE_CMD_SCALE_OP1_SEL_IP_SEL_Y_CASCADED 0x0001 +#define VFE_CMD_SCALE_OP1_SEL_H_Y_SCALER_DIS 0x0000 +#define VFE_CMD_SCALE_OP1_SEL_H_Y_SCALER_ENA 0x0002 +#define VFE_CMD_SCALE_OP1_SEL_H_PP_Y_SCALER_DIS 0x0000 +#define VFE_CMD_SCALE_OP1_SEL_H_PP_Y_SCALER_ENA 0x0004 +#define VFE_CMD_SCALE_OP1_SEL_V_Y_SCALER_DIS 0x0000 +#define VFE_CMD_SCALE_OP1_SEL_V_Y_SCALER_ENA 0x0008 +#define VFE_CMD_SCALE_OP1_SEL_V_PP_Y_SCALER_DIS 0x0000 +#define VFE_CMD_SCALE_OP1_SEL_V_PP_Y_SCALER_ENA 0x0010 +#define VFE_CMD_SCALE_OP1_SEL_IP_SEL_CBCR_STANDARD 0x0000 +#define VFE_CMD_SCALE_OP1_SEL_IP_SEL_CBCR_CASCADED 0x0020 +#define VFE_CMD_SCALE_OP1_SEL_H_CBCR_SCALER_DIS 0x0000 +#define VFE_CMD_SCALE_OP1_SEL_H_CBCR_SCALER_ENA 0x0040 +#define VFE_CMD_SCALE_OP1_SEL_V_CBCR_SCALER_DIS 0x0000 +#define VFE_CMD_SCALE_OP1_SEL_V_CBCR_SCALER_ENA 0x0080 + +#define VFE_CMD_OP1_PP_Y_SCALER_CFG_PART1_DONT_LOAD_COEFFS 0x80000000 +#define VFE_CMD_OP1_PP_Y_SCALER_CFG_PART1_LOAD_COEFFS 0x80000000 + +typedef struct { + unsigned int cmd_id; + unsigned int scale_op1_sel; + unsigned int y_scaler_cfg_part1; + unsigned int y_scaler_cfg_part2; + unsigned int cbcr_scaler_cfg_part1; + unsigned int cbcr_scaler_cfg_part2; + unsigned int cbcr_scaler_cfg_part3; + unsigned int pp_y_scaler_cfg_part1; + unsigned int pp_y_scaler_cfg_part2; + unsigned int y_scaler_v_coeff_bank_part1[16]; + unsigned int y_scaler_v_coeff_bank_part2[16]; + unsigned int y_scaler_h_coeff_bank_part1[16]; + unsigned int y_scaler_h_coeff_bank_part2[16]; +} __attribute__((packed)) vfe_cmd_scale_op1_cfg; + + +/* + * Command to program scaler for op2 + */ + +#define VFE_CMD_SCALE_OP2_CFG 0x0001 +#define VFE_CMD_SCALE_OP2_CFG_LEN \ + sizeof(vfe_cmd_scale_op2_cfg) + +#define VFE_CMD_SCALE_OP2_SEL_IP_SEL_Y_STANDARD 0x0000 +#define VFE_CMD_SCALE_OP2_SEL_IP_SEL_Y_CASCADED 0x0001 +#define VFE_CMD_SCALE_OP2_SEL_H_Y_SCALER_DIS 0x0000 +#define VFE_CMD_SCALE_OP2_SEL_H_Y_SCALER_ENA 0x0002 +#define VFE_CMD_SCALE_OP2_SEL_H_PP_Y_SCALER_DIS 0x0000 +#define VFE_CMD_SCALE_OP2_SEL_H_PP_Y_SCALER_ENA 0x0004 +#define VFE_CMD_SCALE_OP2_SEL_V_Y_SCALER_DIS 0x0000 +#define VFE_CMD_SCALE_OP2_SEL_V_Y_SCALER_ENA 0x0008 +#define VFE_CMD_SCALE_OP2_SEL_V_PP_Y_SCALER_DIS 0x0000 +#define VFE_CMD_SCALE_OP2_SEL_V_PP_Y_SCALER_ENA 0x0010 +#define VFE_CMD_SCALE_OP2_SEL_IP_SEL_CBCR_STANDARD 0x0000 +#define VFE_CMD_SCALE_OP2_SEL_IP_SEL_CBCR_CASCADED 0x0020 +#define VFE_CMD_SCALE_OP2_SEL_H_CBCR_SCALER_DIS 0x0000 +#define VFE_CMD_SCALE_OP2_SEL_H_CBCR_SCALER_ENA 0x0040 +#define VFE_CMD_SCALE_OP2_SEL_V_CBCR_SCALER_DIS 0x0000 +#define VFE_CMD_SCALE_OP2_SEL_V_CBCR_SCALER_ENA 0x0080 + +#define VFE_CMD_OP2_PP_Y_SCALER_CFG_PART1_DONT_LOAD_COEFFS 0x80000000 +#define VFE_CMD_OP2_PP_Y_SCALER_CFG_PART1_LOAD_COEFFS 0x80000000 + +typedef struct { + unsigned int cmd_id; + unsigned int scale_op2_sel; + unsigned int y_scaler_cfg_part1; + unsigned int y_scaler_cfg_part2; + unsigned int cbcr_scaler_cfg_part1; + unsigned int cbcr_scaler_cfg_part2; + unsigned int cbcr_scaler_cfg_part3; + unsigned int pp_y_scaler_cfg_part1; + unsigned int pp_y_scaler_cfg_part2; + unsigned int y_scaler_v_coeff_bank_part1[16]; + unsigned int y_scaler_v_coeff_bank_part2[16]; + unsigned int y_scaler_h_coeff_bank_part1[16]; + unsigned int y_scaler_h_coeff_bank_part2[16]; +} __attribute__((packed)) vfe_cmd_scale_op2_cfg; + + +/****************************************************************************** + * Commands through vfeCommandTableQueue + *****************************************************************************/ + +/* + * Command to program the AXI ip paths + */ + +#define VFE_CMD_AXI_IP_CFG 0x0000 +#define VFE_CMD_AXI_IP_CFG_LEN sizeof(vfe_cmd_axi_ip_cfg) + +#define VFE_CMD_IP_SEL_IP_FORMAT_8 0x0000 +#define VFE_CMD_IP_SEL_IP_FORMAT_10 0x0001 +#define VFE_CMD_IP_SEL_IP_FORMAT_12 0x0002 + +typedef struct { + unsigned int cmd_id; + unsigned int ip_sel; + unsigned int ip_cfg_part1; + unsigned int ip_cfg_part2; + unsigned int ip_unpack_cfg_part[6]; + unsigned int ip_buf_addr[8]; +} __attribute__ ((packed)) vfe_cmd_axi_ip_cfg; + + +/* + * Command to program axi op paths + */ + +#define VFE_CMD_AXI_OP_CFG 0x0001 +#define VFE_CMD_AXI_OP_CFG_LEN sizeof(vfe_cmd_axi_op_cfg) + +#define VFE_CMD_OP_SEL_OP1 0x0000 +#define VFE_CMD_OP_SEL_OP2 0x0001 +#define VFE_CMD_OP_SEL_OP1_OP2 0x0002 +#define VFE_CMD_OP_SEL_CTOA 0x0003 +#define VFE_CMD_OP_SEL_CTOA_OP1 0x0004 +#define VFE_CMD_OP_SEL_CTOA_OP2 0x0005 +#define VFE_CMD_OP_SEL_OP_FORMAT_8 0x0000 +#define VFE_CMD_OP_SEL_OP_FORMAT_10 0x0008 +#define VFE_CMD_OP_SEL_OP_FORMAT_12 0x0010 + + +typedef struct { + unsigned int cmd_id; + unsigned int op_sel; + unsigned int op1_y_cfg_part1; + unsigned int op1_y_cfg_part2; + unsigned int op1_cbcr_cfg_part1; + unsigned int op1_cbcr_cfg_part2; + unsigned int op2_y_cfg_part1; + unsigned int op2_y_cfg_part2; + unsigned int op2_cbcr_cfg_part1; + unsigned int op2_cbcr_cfg_part2; + unsigned int op1_buf1_addr[16]; + unsigned int op2_buf1_addr[16]; +} __attribute__((packed)) vfe_cmd_axi_op_cfg; + + + + +/* + * Command to program the roll off correction module + */ + +#define VFE_CMD_ROLLOFF_CFG 0x0002 +#define VFE_CMD_ROLLOFF_CFG_LEN \ + sizeof(vfe_cmd_rolloff_cfg) + + +typedef struct { + unsigned int cmd_id; + unsigned int correction_opt_center_pos; + unsigned int radius_square_entry[32]; + unsigned int red_table_entry[32]; + unsigned int green_table_entry[32]; + unsigned int blue_table_entry[32]; +} __attribute__((packed)) vfe_cmd_rolloff_cfg; + +/* + * Command to program RGB gamma table + */ + +#define VFE_CMD_RGB_GAMMA_CFG 0x0003 +#define VFE_CMD_RGB_GAMMA_CFG_LEN \ + sizeof(vfe_cmd_rgb_gamma_cfg) + +#define VFE_CMD_RGB_GAMMA_SEL_LINEAR 0x0000 +#define VFE_CMD_RGB_GAMMA_SEL_PW_LINEAR 0x0001 +typedef struct { + unsigned int cmd_id; + unsigned int rgb_gamma_sel; + unsigned int rgb_gamma_entry[256]; +} __attribute__((packed)) vfe_cmd_rgb_gamma_cfg; + + +/* + * Command to program luma gamma table for the noise reduction path + */ + +#define VFE_CMD_Y_GAMMA_CFG 0x0004 +#define VFE_CMD_Y_GAMMA_CFG_LEN \ + sizeof(vfe_cmd_y_gamma_cfg) + +#define VFE_CMD_Y_GAMMA_SEL_LINEAR 0x0000 +#define VFE_CMD_Y_GAMMA_SEL_PW_LINEAR 0x0001 + +typedef struct { + unsigned int cmd_id; + unsigned int y_gamma_sel; + unsigned int y_gamma_entry[256]; +} __attribute__((packed)) vfe_cmd_y_gamma_cfg; + + + +/****************************************************************************** + * Commands through vfeCommandQueue + *****************************************************************************/ + +/* + * Command to reset the VFE to a known good state.All previously programmed + * Params will be lost + */ + + +#define VFE_CMD_RESET 0x0000 +#define VFE_CMD_RESET_LEN sizeof(vfe_cmd_reset) + + +typedef struct { + unsigned short cmd_id; +} __attribute__((packed)) vfe_cmd_reset; + + +/* + * Command to start VFE processing based on the config params + */ + + +#define VFE_CMD_START 0x0001 +#define VFE_CMD_START_LEN sizeof(vfe_cmd_start) + +#define VFE_CMD_STARTUP_PARAMS_SRC_CAMIF 0x0000 +#define VFE_CMD_STARTUP_PARAMS_SRC_AXI 0x0001 +#define VFE_CMD_STARTUP_PARAMS_MODE_CONTINUOUS 0x0000 +#define VFE_CMD_STARTUP_PARAMS_MODE_SNAPSHOT 0x0002 + +#define VFE_CMD_IMAGE_PL_BLACK_LVL_CORR_DIS 0x0000 +#define VFE_CMD_IMAGE_PL_BLACK_LVL_CORR_ENA 0x0001 +#define VFE_CMD_IMAGE_PL_ROLLOFF_CORR_DIS 0x0000 +#define VFE_CMD_IMAGE_PL_ROLLOFF_CORR_ENA 0x0002 +#define VFE_CMD_IMAGE_PL_WHITE_BAL_DIS 0x0000 +#define VFE_CMD_IMAGE_PL_WHITE_BAL_ENA 0x0004 +#define VFE_CMD_IMAGE_PL_RGB_GAMMA_DIS 0x0000 +#define VFE_CMD_IMAGE_PL_RGB_GAMMA_ENA 0x0008 +#define VFE_CMD_IMAGE_PL_LUMA_NOISE_RED_PATH_DIS 0x0000 +#define VFE_CMD_IMAGE_PL_LUMA_NOISE_RED_PATH_ENA 0x0010 +#define VFE_CMD_IMAGE_PL_ADP_FILTER_DIS 0x0000 +#define VFE_CMD_IMAGE_PL_ADP_FILTER_ENA 0x0020 +#define VFE_CMD_IMAGE_PL_CHROMA_SAMP_DIS 0x0000 +#define VFE_CMD_IMAGE_PL_CHROMA_SAMP_ENA 0x0040 + + +typedef struct { + unsigned int cmd_id; + unsigned int startup_params; + unsigned int image_pipeline; + unsigned int frame_dimension; +} __attribute__((packed)) vfe_cmd_start; + + +/* + * Command to halt all processing + */ + +#define VFE_CMD_STOP 0x0002 +#define VFE_CMD_STOP_LEN sizeof(vfe_cmd_stop) + +typedef struct { + unsigned short cmd_id; +} __attribute__((packed)) vfe_cmd_stop; + + +/* + * Command to commit the params that have been programmed to take + * effect on the next frame + */ + +#define VFE_CMD_UPDATE 0x0003 +#define VFE_CMD_UPDATE_LEN sizeof(vfe_cmd_update) + + +typedef struct { + unsigned short cmd_id; +} __attribute__((packed)) vfe_cmd_update; + + +/* + * Command to program CAMIF module + */ + +#define VFE_CMD_CAMIF_CFG 0x0004 +#define VFE_CMD_CAMIF_CFG_LEN sizeof(vfe_cmd_camif_cfg) + +#define VFE_CMD_CFG_VSYNC_SYNC_EDGE_HIGH 0x0000 +#define VFE_CMD_CFG_VSYNC_SYNC_EDGE_LOW 0x0002 +#define VFE_CMD_CFG_HSYNC_SYNC_EDGE_HIGH 0x0000 +#define VFE_CMD_CFG_HSYNC_SYNC_EDGE_LOW 0x0004 +#define VFE_CMD_CFG_SYNC_MODE_APS 0x0000 +#define VFE_CMD_CFG_SYNC_MODE_EFS 0X0008 +#define VFE_CMD_CFG_SYNC_MODE_ELS 0x0010 +#define VFE_CMD_CFG_SYNC_MODE_RVD 0x0018 +#define VFE_CMD_CFG_VFE_SUBSAMP_EN_DIS 0x0000 +#define VFE_CMD_CFG_VFE_SUBSAMP_EN_ENA 0x0020 +#define VFE_CMD_CFG_BUS_SUBSAMP_EN_DIS 0x0000 +#define VFE_CMD_CFG_BUS_SUBSAMP_EN_ENA 0x0080 +#define VFE_CMD_CFG_IRQ_SUBSAMP_EN_DIS 0x0000 +#define VFE_CMD_CFG_IRQ_SUBSAMP_EN_ENA 0x0800 + +#define VFE_CMD_SUBSAMP2_CFG_PIXEL_SKIP_16 0x0000 +#define VFE_CMD_SUBSAMP2_CFG_PIXEL_SKIP_12 0x0010 + +#define VFE_CMD_EPOCH_IRQ_1_DIS 0x0000 +#define VFE_CMD_EPOCH_IRQ_1_ENA 0x4000 +#define VFE_CMD_EPOCH_IRQ_2_DIS 0x0000 +#define VFE_CMD_EPOCH_IRQ_2_ENA 0x8000 + +typedef struct { + unsigned int cmd_id; + unsigned int cfg; + unsigned int efs_cfg; + unsigned int frame_cfg; + unsigned int window_width_cfg; + unsigned int window_height_cfg; + unsigned int subsamp1_cfg; + unsigned int subsamp2_cfg; + unsigned int epoch_irq; +} __attribute__((packed)) vfe_cmd_camif_cfg; + + + +/* + * Command to program the black level module + */ + +#define VFE_CMD_BLACK_LVL_CFG 0x0005 +#define VFE_CMD_BLACK_LVL_CFG_LEN sizeof(vfe_cmd_black_lvl_cfg) + +#define VFE_CMD_BL_SEL_MANUAL 0x0000 +#define VFE_CMD_BL_SEL_AUTO 0x0001 + +typedef struct { + unsigned int cmd_id; + unsigned int black_lvl_sel; + unsigned int cfg_part[3]; +} __attribute__((packed)) vfe_cmd_black_lvl_cfg; + + +/* + * Command to program the active region by cropping the region of interest + */ + +#define VFE_CMD_ACTIVE_REGION_CFG 0x0006 +#define VFE_CMD_ACTIVE_REGION_CFG_LEN \ + sizeof(vfe_cmd_active_region_cfg) + + +typedef struct { + unsigned int cmd_id; + unsigned int cfg_part1; + unsigned int cfg_part2; +} __attribute__((packed)) vfe_cmd_active_region_cfg; + + + +/* + * Command to program the defective pixel correction(DPC) , + * adaptive bayer filter (ABF) and demosaic modules + */ + +#define VFE_CMD_DEMOSAIC_CFG 0x0007 +#define VFE_CMD_DEMOSAIC_CFG_LEN sizeof(vfe_cmd_demosaic_cfg) + +#define VFE_CMD_DEMOSAIC_PART1_ABF_EN_DIS 0x0000 +#define VFE_CMD_DEMOSAIC_PART1_ABF_EN_ENA 0x0001 +#define VFE_CMD_DEMOSAIC_PART1_DPC_EN_DIS 0x0000 +#define VFE_CMD_DEMOSAIC_PART1_DPC_EN_ENA 0x0002 +#define VFE_CMD_DEMOSAIC_PART1_FORCE_ABF_OFF 0x0000 +#define VFE_CMD_DEMOSAIC_PART1_FORCE_ABF_ON 0x0004 +#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_1 0x00000000 +#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_2 0x10000000 +#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_4 0x20000000 +#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_8 0x30000000 +#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_1_2 0x50000000 +#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_1_4 0x60000000 +#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_1_8 0x70000000 + +typedef struct { + unsigned int cmd_id; + unsigned int demosaic_part1; + unsigned int demosaic_part2; + unsigned int demosaic_part3; + unsigned int demosaic_part4; + unsigned int demosaic_part5; +} __attribute__((packed)) vfe_cmd_demosaic_cfg; + + +/* + * Command to program the ip format + */ + +#define VFE_CMD_IP_FORMAT_CFG 0x0008 +#define VFE_CMD_IP_FORMAT_CFG_LEN \ + sizeof(vfe_cmd_ip_format_cfg) + +#define VFE_CMD_IP_FORMAT_SEL_RGRG 0x0000 +#define VFE_CMD_IP_FORMAT_SEL_GRGR 0x0001 +#define VFE_CMD_IP_FORMAT_SEL_BGBG 0x0002 +#define VFE_CMD_IP_FORMAT_SEL_GBGB 0x0003 +#define VFE_CMD_IP_FORMAT_SEL_YCBYCR 0x0004 +#define VFE_CMD_IP_FORMAT_SEL_YCRYCB 0x0005 +#define VFE_CMD_IP_FORMAT_SEL_CBYCRY 0x0006 +#define VFE_CMD_IP_FORMAT_SEL_CRYCBY 0x0007 +#define VFE_CMD_IP_FORMAT_SEL_NO_CHROMA 0x0000 +#define VFE_CMD_IP_FORMAT_SEL_CHROMA 0x0008 + + +typedef struct { + unsigned int cmd_id; + unsigned int ip_format_sel; + unsigned int balance_gains_part1; + unsigned int balance_gains_part2; +} __attribute__((packed)) vfe_cmd_ip_format_cfg; + + + +/* + * Command to program max and min allowed op values + */ + +#define VFE_CMD_OP_CLAMP_CFG 0x0009 +#define VFE_CMD_OP_CLAMP_CFG_LEN \ + sizeof(vfe_cmd_op_clamp_cfg) + +typedef struct { + unsigned int cmd_id; + unsigned int op_clamp_max; + unsigned int op_clamp_min; +} __attribute__((packed)) vfe_cmd_op_clamp_cfg; + + +/* + * Command to program chroma sub sample module + */ + +#define VFE_CMD_CHROMA_SUBSAMPLE_CFG 0x000A +#define VFE_CMD_CHROMA_SUBSAMPLE_CFG_LEN \ + sizeof(vfe_cmd_chroma_subsample_cfg) + +#define VFE_CMD_CHROMA_SUBSAMP_SEL_H_INTERESTIAL_SAMPS 0x0000 +#define VFE_CMD_CHROMA_SUBSAMP_SEL_H_COSITED_SAMPS 0x0001 +#define VFE_CMD_CHROMA_SUBSAMP_SEL_V_INTERESTIAL_SAMPS 0x0000 +#define VFE_CMD_CHROMA_SUBSAMP_SEL_V_COSITED_SAMPS 0x0002 +#define VFE_CMD_CHROMA_SUBSAMP_SEL_H_SUBSAMP_DIS 0x0000 +#define VFE_CMD_CHROMA_SUBSAMP_SEL_H_SUBSAMP_ENA 0x0004 +#define VFE_CMD_CHROMA_SUBSAMP_SEL_V_SUBSAMP_DIS 0x0000 +#define VFE_CMD_CHROMA_SUBSAMP_SEL_V_SUBSAMP_ENA 0x0008 + +typedef struct { + unsigned int cmd_id; + unsigned int chroma_subsamp_sel; +} __attribute__((packed)) vfe_cmd_chroma_subsample_cfg; + + +/* + * Command to program the white balance module + */ + +#define VFE_CMD_WHITE_BALANCE_CFG 0x000B +#define VFE_CMD_WHITE_BALANCE_CFG_LEN \ + sizeof(vfe_cmd_white_balance_cfg) + +typedef struct { + unsigned int cmd_id; + unsigned int white_balance_gains; +} __attribute__((packed)) vfe_cmd_white_balance_cfg; + + +/* + * Command to program the color processing module + */ + +#define VFE_CMD_COLOR_PROCESS_CFG 0x000C +#define VFE_CMD_COLOR_PROCESS_CFG_LEN \ + sizeof(vfe_cmd_color_process_cfg) + +#define VFE_CMD_COLOR_CORRE_PART7_Q7_FACTORS 0x0000 +#define VFE_CMD_COLOR_CORRE_PART7_Q8_FACTORS 0x0001 +#define VFE_CMD_COLOR_CORRE_PART7_Q9_FACTORS 0x0002 +#define VFE_CMD_COLOR_CORRE_PART7_Q10_FACTORS 0x0003 + +typedef struct { + unsigned int cmd_id; + unsigned int color_correction_part1; + unsigned int color_correction_part2; + unsigned int color_correction_part3; + unsigned int color_correction_part4; + unsigned int color_correction_part5; + unsigned int color_correction_part6; + unsigned int color_correction_part7; + unsigned int chroma_enhance_part1; + unsigned int chroma_enhance_part2; + unsigned int chroma_enhance_part3; + unsigned int chroma_enhance_part4; + unsigned int chroma_enhance_part5; + unsigned int luma_calc_part1; + unsigned int luma_calc_part2; +} __attribute__((packed)) vfe_cmd_color_process_cfg; + + +/* + * Command to program adaptive filter module + */ + +#define VFE_CMD_ADP_FILTER_CFG 0x000D +#define VFE_CMD_ADP_FILTER_CFG_LEN \ + sizeof(vfe_cmd_adp_filter_cfg) + +#define VFE_CMD_ASF_CFG_PART_SMOOTH_FILTER_DIS 0x0000 +#define VFE_CMD_ASF_CFG_PART_SMOOTH_FILTER_ENA 0x0001 +#define VFE_CMD_ASF_CFG_PART_NO_SHARP_MODE 0x0000 +#define VFE_CMD_ASF_CFG_PART_SINGLE_FILTER 0x0002 +#define VFE_CMD_ASF_CFG_PART_DUAL_FILTER 0x0004 +#define VFE_CMD_ASF_CFG_PART_SHARP_MODE 0x0007 + +typedef struct { + unsigned int cmd_id; + unsigned int asf_cfg_part[7]; +} __attribute__((packed)) vfe_cmd_adp_filter_cfg; + + +/* + * Command to program for frame skip pattern for op1 and op2 + */ + +#define VFE_CMD_FRAME_SKIP_CFG 0x000E +#define VFE_CMD_FRAME_SKIP_CFG_LEN \ + sizeof(vfe_cmd_frame_skip_cfg) + +typedef struct { + unsigned int cmd_id; + unsigned int frame_skip_pattern_op1; + unsigned int frame_skip_pattern_op2; +} __attribute__((packed)) vfe_cmd_frame_skip_cfg; + + +/* + * Command to program field-of-view crop for digital zoom + */ + +#define VFE_CMD_FOV_CROP 0x000F +#define VFE_CMD_FOV_CROP_LEN sizeof(vfe_cmd_fov_crop) + +typedef struct { + unsigned int cmd_id; + unsigned int fov_crop_part1; + unsigned int fov_crop_part2; +} __attribute__((packed)) vfe_cmd_fov_crop; + + + +/* + * Command to program auto focus(AF) statistics module + */ + +#define VFE_CMD_STATS_AUTOFOCUS_CFG 0x0010 +#define VFE_CMD_STATS_AUTOFOCUS_CFG_LEN \ + sizeof(vfe_cmd_stats_autofocus_cfg) + +#define VFE_CMD_AF_STATS_SEL_STATS_DIS 0x0000 +#define VFE_CMD_AF_STATS_SEL_STATS_ENA 0x0001 +#define VFE_CMD_AF_STATS_SEL_PRI_FIXED 0x0000 +#define VFE_CMD_AF_STATS_SEL_PRI_VAR 0x0002 +#define VFE_CMD_AF_STATS_CFG_PART_METRIC_SUM 0x00000000 +#define VFE_CMD_AF_STATS_CFG_PART_METRIC_MAX 0x00200000 + +typedef struct { + unsigned int cmd_id; + unsigned int af_stats_sel; + unsigned int af_stats_cfg_part[8]; + unsigned int af_stats_op_buf_hdr; + unsigned int af_stats_op_buf[3]; +} __attribute__((packed)) vfe_cmd_stats_autofocus_cfg; + + +/* + * Command to program White balance(wb) and exposure (exp) + * statistics module + */ + +#define VFE_CMD_STATS_WB_EXP_CFG 0x0011 +#define VFE_CMD_STATS_WB_EXP_CFG_LEN \ + sizeof(vfe_cmd_stats_wb_exp_cfg) + +#define VFE_CMD_WB_EXP_STATS_SEL_STATS_DIS 0x0000 +#define VFE_CMD_WB_EXP_STATS_SEL_STATS_ENA 0x0001 +#define VFE_CMD_WB_EXP_STATS_SEL_PRI_FIXED 0x0000 +#define VFE_CMD_WB_EXP_STATS_SEL_PRI_VAR 0x0002 + +#define VFE_CMD_WB_EXP_STATS_CFG_PART1_EXP_REG_8_8 0x0000 +#define VFE_CMD_WB_EXP_STATS_CFG_PART1_EXP_REG_16_16 0x0001 +#define VFE_CMD_WB_EXP_STATS_CFG_PART1_EXP_SREG_8_8 0x0000 +#define VFE_CMD_WB_EXP_STATS_CFG_PART1_EXP_SREG_4_4 0x0002 + +typedef struct { + unsigned int cmd_id; + unsigned int wb_exp_stats_sel; + unsigned int wb_exp_stats_cfg_part1; + unsigned int wb_exp_stats_cfg_part2; + unsigned int wb_exp_stats_cfg_part3; + unsigned int wb_exp_stats_cfg_part4; + unsigned int wb_exp_stats_op_buf_hdr; + unsigned int wb_exp_stats_op_buf[3]; +} __attribute__((packed)) vfe_cmd_stats_wb_exp_cfg; + + +/* + * Command to program histogram(hg) stats module + */ + +#define VFE_CMD_STATS_HG_CFG 0x0012 +#define VFE_CMD_STATS_HG_CFG_LEN \ + sizeof(vfe_cmd_stats_hg_cfg) + +#define VFE_CMD_HG_STATS_SEL_PRI_FIXED 0x0000 +#define VFE_CMD_HG_STATS_SEL_PRI_VAR 0x0002 + +typedef struct { + unsigned int cmd_id; + unsigned int hg_stats_sel; + unsigned int hg_stats_cfg_part1; + unsigned int hg_stats_cfg_part2; + unsigned int hg_stats_op_buf_hdr; + unsigned int hg_stats_op_buf; +} __attribute__((packed)) vfe_cmd_stats_hg_cfg; + + +/* + * Command to acknowledge last MSG_VFE_OP1 message + */ + +#define VFE_CMD_OP1_ACK 0x0013 +#define VFE_CMD_OP1_ACK_LEN sizeof(vfe_cmd_op1_ack) + +typedef struct { + unsigned int cmd_id; + unsigned int op1_buf_y_addr; + unsigned int op1_buf_cbcr_addr; +} __attribute__((packed)) vfe_cmd_op1_ack; + + + +/* + * Command to acknowledge last MSG_VFE_OP2 message + */ + +#define VFE_CMD_OP2_ACK 0x0014 +#define VFE_CMD_OP2_ACK_LEN sizeof(vfe_cmd_op2_ack) + +typedef struct { + unsigned int cmd_id; + unsigned int op2_buf_y_addr; + unsigned int op2_buf_cbcr_addr; +} __attribute__((packed)) vfe_cmd_op2_ack; + + + +/* + * Command to acknowledge MSG_VFE_STATS_AUTOFOCUS msg + */ + +#define VFE_CMD_STATS_AF_ACK 0x0015 +#define VFE_CMD_STATS_AF_ACK_LEN sizeof(vfe_cmd_stats_af_ack) + + +typedef struct { + unsigned int cmd_id; + unsigned int af_stats_op_buf; +} __attribute__((packed)) vfe_cmd_stats_af_ack; + + +/* + * Command to acknowledge MSG_VFE_STATS_WB_EXP msg + */ + +#define VFE_CMD_STATS_WB_EXP_ACK 0x0016 +#define VFE_CMD_STATS_WB_EXP_ACK_LEN sizeof(vfe_cmd_stats_wb_exp_ack) + +typedef struct { + unsigned int cmd_id; + unsigned int wb_exp_stats_op_buf; +} __attribute__((packed)) vfe_cmd_stats_wb_exp_ack; + + +/* + * Command to acknowledge MSG_VFE_EPOCH1 message + */ + +#define VFE_CMD_EPOCH1_ACK 0x0017 +#define VFE_CMD_EPOCH1_ACK_LEN sizeof(vfe_cmd_epoch1_ack) + +typedef struct { + unsigned short cmd_id; +} __attribute__((packed)) vfe_cmd_epoch1_ack; + + +/* + * Command to acknowledge MSG_VFE_EPOCH2 message + */ + +#define VFE_CMD_EPOCH2_ACK 0x0018 +#define VFE_CMD_EPOCH2_ACK_LEN sizeof(vfe_cmd_epoch2_ack) + +typedef struct { + unsigned short cmd_id; +} __attribute__((packed)) vfe_cmd_epoch2_ack; + + + +/* + * Command to configure, enable or disable synchronous timer1 + */ + +#define VFE_CMD_SYNC_TIMER1_CFG 0x0019 +#define VFE_CMD_SYNC_TIMER1_CFG_LEN \ + sizeof(vfe_cmd_sync_timer1_cfg) + +#define VFE_CMD_SYNC_T1_CFG_PART1_TIMER_DIS 0x0000 +#define VFE_CMD_SYNC_T1_CFG_PART1_TIMER_ENA 0x0001 +#define VFE_CMD_SYNC_T1_CFG_PART1_POL_HIGH 0x0000 +#define VFE_CMD_SYNC_T1_CFG_PART1_POL_LOW 0x0002 + +typedef struct { + unsigned int cmd_id; + unsigned int sync_t1_cfg_part1; + unsigned int sync_t1_h_sync_countdown; + unsigned int sync_t1_pclk_countdown; + unsigned int sync_t1_duration; +} __attribute__((packed)) vfe_cmd_sync_timer1_cfg; + + +/* + * Command to configure, enable or disable synchronous timer1 + */ + +#define VFE_CMD_SYNC_TIMER2_CFG 0x001A +#define VFE_CMD_SYNC_TIMER2_CFG_LEN \ + sizeof(vfe_cmd_sync_timer2_cfg) + +#define VFE_CMD_SYNC_T2_CFG_PART1_TIMER_DIS 0x0000 +#define VFE_CMD_SYNC_T2_CFG_PART1_TIMER_ENA 0x0001 +#define VFE_CMD_SYNC_T2_CFG_PART1_POL_HIGH 0x0000 +#define VFE_CMD_SYNC_T2_CFG_PART1_POL_LOW 0x0002 + +typedef struct { + unsigned int cmd_id; + unsigned int sync_t2_cfg_part1; + unsigned int sync_t2_h_sync_countdown; + unsigned int sync_t2_pclk_countdown; + unsigned int sync_t2_duration; +} __attribute__((packed)) vfe_cmd_sync_timer2_cfg; + + +/* + * Command to configure and start asynchronous timer1 + */ + +#define VFE_CMD_ASYNC_TIMER1_START 0x001B +#define VFE_CMD_ASYNC_TIMER1_START_LEN \ + sizeof(vfe_cmd_async_timer1_start) + +#define VFE_CMD_ASYNC_T1_POLARITY_A_HIGH 0x0000 +#define VFE_CMD_ASYNC_T1_POLARITY_A_LOW 0x0001 +#define VFE_CMD_ASYNC_T1_POLARITY_B_HIGH 0x0000 +#define VFE_CMD_ASYNC_T1_POLARITY_B_LOW 0x0002 + +typedef struct { + unsigned int cmd_id; + unsigned int async_t1a_cfg; + unsigned int async_t1b_cfg; + unsigned int async_t1_polarity; +} __attribute__((packed)) vfe_cmd_async_timer1_start; + + +/* + * Command to configure and start asynchronous timer2 + */ + +#define VFE_CMD_ASYNC_TIMER2_START 0x001C +#define VFE_CMD_ASYNC_TIMER2_START_LEN \ + sizeof(vfe_cmd_async_timer2_start) + +#define VFE_CMD_ASYNC_T2_POLARITY_A_HIGH 0x0000 +#define VFE_CMD_ASYNC_T2_POLARITY_A_LOW 0x0001 +#define VFE_CMD_ASYNC_T2_POLARITY_B_HIGH 0x0000 +#define VFE_CMD_ASYNC_T2_POLARITY_B_LOW 0x0002 + +typedef struct { + unsigned int cmd_id; + unsigned int async_t2a_cfg; + unsigned int async_t2b_cfg; + unsigned int async_t2_polarity; +} __attribute__((packed)) vfe_cmd_async_timer2_start; + + +/* + * Command to program partial configurations of auto focus(af) + */ + +#define VFE_CMD_STATS_AF_UPDATE 0x001D +#define VFE_CMD_STATS_AF_UPDATE_LEN \ + sizeof(vfe_cmd_stats_af_update) + +#define VFE_CMD_AF_UPDATE_PART1_WINDOW_ONE 0x00000000 +#define VFE_CMD_AF_UPDATE_PART1_WINDOW_MULTI 0x80000000 + +typedef struct { + unsigned int cmd_id; + unsigned int af_update_part1; + unsigned int af_update_part2; +} __attribute__((packed)) vfe_cmd_stats_af_update; + + +/* + * Command to program partial cfg of wb and exp + */ + +#define VFE_CMD_STATS_WB_EXP_UPDATE 0x001E +#define VFE_CMD_STATS_WB_EXP_UPDATE_LEN \ + sizeof(vfe_cmd_stats_wb_exp_update) + +#define VFE_CMD_WB_EXP_UPDATE_PART1_REGIONS_8_8 0x0000 +#define VFE_CMD_WB_EXP_UPDATE_PART1_REGIONS_16_16 0x0001 +#define VFE_CMD_WB_EXP_UPDATE_PART1_SREGIONS_8_8 0x0000 +#define VFE_CMD_WB_EXP_UPDATE_PART1_SREGIONS_4_4 0x0002 + +typedef struct { + unsigned int cmd_id; + unsigned int wb_exp_update_part1; + unsigned int wb_exp_update_part2; + unsigned int wb_exp_update_part3; + unsigned int wb_exp_update_part4; +} __attribute__((packed)) vfe_cmd_stats_wb_exp_update; + + + +/* + * Command to re program the CAMIF FRAME CONFIG settings + */ + +#define VFE_CMD_UPDATE_CAMIF_FRAME_CFG 0x001F +#define VFE_CMD_UPDATE_CAMIF_FRAME_CFG_LEN \ + sizeof(vfe_cmd_update_camif_frame_cfg) + +typedef struct { + unsigned int cmd_id; + unsigned int camif_frame_cfg; +} __attribute__((packed)) vfe_cmd_update_camif_frame_cfg; + + +#endif diff --git a/drivers/staging/dream/include/mach/qdsp5/qdsp5vfemsg.h b/drivers/staging/dream/include/mach/qdsp5/qdsp5vfemsg.h new file mode 100644 index 000000000000..0053cfb65ba1 --- /dev/null +++ b/drivers/staging/dream/include/mach/qdsp5/qdsp5vfemsg.h @@ -0,0 +1,290 @@ +#ifndef QDSP5VFEMSGI_H +#define QDSP5VFEMSGI_H + +/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====* + + V F E I N T E R N A L M E S S A G E S + +GENERAL DESCRIPTION + This file contains defintions of format blocks of commands + that are sent by VFE Task + +REFERENCES + None + +EXTERNALIZED FUNCTIONS + None + +Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated. + +This software is licensed under the terms of the GNU General Public +License version 2, as published by the Free Software Foundation, and +may be copied, distributed, and modified under those terms. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/ +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5vfemsg.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $ +Revision History: + +when who what, where, why +-------- --- ---------------------------------------------------------- +06/12/08 sv initial version +===========================================================================*/ + + +/* + * Message to acknowledge CMD_VFE_REST command + */ + +#define VFE_MSG_RESET_ACK 0x0000 +#define VFE_MSG_RESET_ACK_LEN sizeof(vfe_msg_reset_ack) + +typedef struct { +} __attribute__((packed)) vfe_msg_reset_ack; + + +/* + * Message to acknowledge CMD_VFE_START command + */ + +#define VFE_MSG_START_ACK 0x0001 +#define VFE_MSG_START_ACK_LEN sizeof(vfe_msg_start_ack) + +typedef struct { +} __attribute__((packed)) vfe_msg_start_ack; + +/* + * Message to acknowledge CMD_VFE_STOP command + */ + +#define VFE_MSG_STOP_ACK 0x0002 +#define VFE_MSG_STOP_ACK_LEN sizeof(vfe_msg_stop_ack) + +typedef struct { +} __attribute__((packed)) vfe_msg_stop_ack; + + +/* + * Message to acknowledge CMD_VFE_UPDATE command + */ + +#define VFE_MSG_UPDATE_ACK 0x0003 +#define VFE_MSG_UPDATE_ACK_LEN sizeof(vfe_msg_update_ack) + +typedef struct { +} __attribute__((packed)) vfe_msg_update_ack; + + +/* + * Message to notify the ARM that snapshot processing is complete + * and that the VFE is now STATE_VFE_IDLE + */ + +#define VFE_MSG_SNAPSHOT_DONE 0x0004 +#define VFE_MSG_SNAPSHOT_DONE_LEN \ + sizeof(vfe_msg_snapshot_done) + +typedef struct { +} __attribute__((packed)) vfe_msg_snapshot_done; + + + +/* + * Message to notify ARM that illegal cmd was received and + * system is in the IDLE state + */ + +#define VFE_MSG_ILLEGAL_CMD 0x0005 +#define VFE_MSG_ILLEGAL_CMD_LEN \ + sizeof(vfe_msg_illegal_cmd) + +typedef struct { + unsigned int status; +} __attribute__((packed)) vfe_msg_illegal_cmd; + + +/* + * Message to notify ARM that op1 buf is full and ready + */ + +#define VFE_MSG_OP1 0x0006 +#define VFE_MSG_OP1_LEN sizeof(vfe_msg_op1) + +typedef struct { + unsigned int op1_buf_y_addr; + unsigned int op1_buf_cbcr_addr; + unsigned int black_level_even_col; + unsigned int black_level_odd_col; + unsigned int defect_pixels_detected; + unsigned int asf_max_edge; +} __attribute__((packed)) vfe_msg_op1; + + +/* + * Message to notify ARM that op2 buf is full and ready + */ + +#define VFE_MSG_OP2 0x0007 +#define VFE_MSG_OP2_LEN sizeof(vfe_msg_op2) + +typedef struct { + unsigned int op2_buf_y_addr; + unsigned int op2_buf_cbcr_addr; + unsigned int black_level_even_col; + unsigned int black_level_odd_col; + unsigned int defect_pixels_detected; + unsigned int asf_max_edge; +} __attribute__((packed)) vfe_msg_op2; + + +/* + * Message to notify ARM that autofocus(af) stats are ready + */ + +#define VFE_MSG_STATS_AF 0x0008 +#define VFE_MSG_STATS_AF_LEN sizeof(vfe_msg_stats_af) + +typedef struct { + unsigned int af_stats_op_buffer; +} __attribute__((packed)) vfe_msg_stats_af; + + +/* + * Message to notify ARM that white balance(wb) and exposure (exp) + * stats are ready + */ + +#define VFE_MSG_STATS_WB_EXP 0x0009 +#define VFE_MSG_STATS_WB_EXP_LEN \ + sizeof(vfe_msg_stats_wb_exp) + +typedef struct { + unsigned int wb_exp_stats_op_buf; +} __attribute__((packed)) vfe_msg_stats_wb_exp; + + +/* + * Message to notify the ARM that histogram(hg) stats are ready + */ + +#define VFE_MSG_STATS_HG 0x000A +#define VFE_MSG_STATS_HG_LEN sizeof(vfe_msg_stats_hg) + +typedef struct { + unsigned int hg_stats_op_buf; +} __attribute__((packed)) vfe_msg_stats_hg; + + +/* + * Message to notify the ARM that epoch1 event occurred in the CAMIF + */ + +#define VFE_MSG_EPOCH1 0x000B +#define VFE_MSG_EPOCH1_LEN sizeof(vfe_msg_epoch1) + +typedef struct { +} __attribute__((packed)) vfe_msg_epoch1; + + +/* + * Message to notify the ARM that epoch2 event occurred in the CAMIF + */ + +#define VFE_MSG_EPOCH2 0x000C +#define VFE_MSG_EPOCH2_LEN sizeof(vfe_msg_epoch2) + +typedef struct { +} __attribute__((packed)) vfe_msg_epoch2; + + +/* + * Message to notify the ARM that sync timer1 op is completed + */ + +#define VFE_MSG_SYNC_T1_DONE 0x000D +#define VFE_MSG_SYNC_T1_DONE_LEN sizeof(vfe_msg_sync_t1_done) + +typedef struct { +} __attribute__((packed)) vfe_msg_sync_t1_done; + + +/* + * Message to notify the ARM that sync timer2 op is completed + */ + +#define VFE_MSG_SYNC_T2_DONE 0x000E +#define VFE_MSG_SYNC_T2_DONE_LEN sizeof(vfe_msg_sync_t2_done) + +typedef struct { +} __attribute__((packed)) vfe_msg_sync_t2_done; + + +/* + * Message to notify the ARM that async t1 operation completed + */ + +#define VFE_MSG_ASYNC_T1_DONE 0x000F +#define VFE_MSG_ASYNC_T1_DONE_LEN sizeof(vfe_msg_async_t1_done) + +typedef struct { +} __attribute__((packed)) vfe_msg_async_t1_done; + + + +/* + * Message to notify the ARM that async t2 operation completed + */ + +#define VFE_MSG_ASYNC_T2_DONE 0x0010 +#define VFE_MSG_ASYNC_T2_DONE_LEN sizeof(vfe_msg_async_t2_done) + +typedef struct { +} __attribute__((packed)) vfe_msg_async_t2_done; + + + +/* + * Message to notify the ARM that an error has occurred + */ + +#define VFE_MSG_ERROR 0x0011 +#define VFE_MSG_ERROR_LEN sizeof(vfe_msg_error) + +#define VFE_MSG_ERR_COND_NO_CAMIF_ERR 0x0000 +#define VFE_MSG_ERR_COND_CAMIF_ERR 0x0001 +#define VFE_MSG_ERR_COND_OP1_Y_NO_BUS_OF 0x0000 +#define VFE_MSG_ERR_COND_OP1_Y_BUS_OF 0x0002 +#define VFE_MSG_ERR_COND_OP1_CBCR_NO_BUS_OF 0x0000 +#define VFE_MSG_ERR_COND_OP1_CBCR_BUS_OF 0x0004 +#define VFE_MSG_ERR_COND_OP2_Y_NO_BUS_OF 0x0000 +#define VFE_MSG_ERR_COND_OP2_Y_BUS_OF 0x0008 +#define VFE_MSG_ERR_COND_OP2_CBCR_NO_BUS_OF 0x0000 +#define VFE_MSG_ERR_COND_OP2_CBCR_BUS_OF 0x0010 +#define VFE_MSG_ERR_COND_AF_NO_BUS_OF 0x0000 +#define VFE_MSG_ERR_COND_AF_BUS_OF 0x0020 +#define VFE_MSG_ERR_COND_WB_EXP_NO_BUS_OF 0x0000 +#define VFE_MSG_ERR_COND_WB_EXP_BUS_OF 0x0040 +#define VFE_MSG_ERR_COND_NO_AXI_ERR 0x0000 +#define VFE_MSG_ERR_COND_AXI_ERR 0x0080 + +#define VFE_MSG_CAMIF_STS_IDLE 0x0000 +#define VFE_MSG_CAMIF_STS_CAPTURE_DATA 0x0001 + +typedef struct { + unsigned int err_cond; + unsigned int camif_sts; +} __attribute__((packed)) vfe_msg_error; + + +#endif diff --git a/drivers/staging/dream/include/media/msm_camera.h b/drivers/staging/dream/include/media/msm_camera.h new file mode 100644 index 000000000000..09812d62cc1e --- /dev/null +++ b/drivers/staging/dream/include/media/msm_camera.h @@ -0,0 +1,388 @@ +/* + * Copyright (C) 2008-2009 QUALCOMM Incorporated. + */ +#ifndef __LINUX_MSM_CAMERA_H +#define __LINUX_MSM_CAMERA_H + +#include +#include +#include + +#define MSM_CAM_IOCTL_MAGIC 'm' + +#define MSM_CAM_IOCTL_GET_SENSOR_INFO \ + _IOR(MSM_CAM_IOCTL_MAGIC, 1, struct msm_camsensor_info *) + +#define MSM_CAM_IOCTL_REGISTER_PMEM \ + _IOW(MSM_CAM_IOCTL_MAGIC, 2, struct msm_pmem_info *) + +#define MSM_CAM_IOCTL_UNREGISTER_PMEM \ + _IOW(MSM_CAM_IOCTL_MAGIC, 3, unsigned) + +#define MSM_CAM_IOCTL_CTRL_COMMAND \ + _IOW(MSM_CAM_IOCTL_MAGIC, 4, struct msm_ctrl_cmd *) + +#define MSM_CAM_IOCTL_CONFIG_VFE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 5, struct msm_camera_vfe_cfg_cmd *) + +#define MSM_CAM_IOCTL_GET_STATS \ + _IOR(MSM_CAM_IOCTL_MAGIC, 6, struct msm_camera_stats_event_ctrl *) + +#define MSM_CAM_IOCTL_GETFRAME \ + _IOR(MSM_CAM_IOCTL_MAGIC, 7, struct msm_camera_get_frame *) + +#define MSM_CAM_IOCTL_ENABLE_VFE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 8, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_CTRL_CMD_DONE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 9, struct camera_cmd *) + +#define MSM_CAM_IOCTL_CONFIG_CMD \ + _IOW(MSM_CAM_IOCTL_MAGIC, 10, struct camera_cmd *) + +#define MSM_CAM_IOCTL_DISABLE_VFE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 11, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_PAD_REG_RESET2 \ + _IOW(MSM_CAM_IOCTL_MAGIC, 12, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_VFE_APPS_RESET \ + _IOW(MSM_CAM_IOCTL_MAGIC, 13, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_RELEASE_FRAME_BUFFER \ + _IOW(MSM_CAM_IOCTL_MAGIC, 14, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_RELEASE_STATS_BUFFER \ + _IOW(MSM_CAM_IOCTL_MAGIC, 15, struct msm_stats_buf *) + +#define MSM_CAM_IOCTL_AXI_CONFIG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 16, struct msm_camera_vfe_cfg_cmd *) + +#define MSM_CAM_IOCTL_GET_PICTURE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 17, struct msm_camera_ctrl_cmd *) + +#define MSM_CAM_IOCTL_SET_CROP \ + _IOW(MSM_CAM_IOCTL_MAGIC, 18, struct crop_info *) + +#define MSM_CAM_IOCTL_PICT_PP \ + _IOW(MSM_CAM_IOCTL_MAGIC, 19, uint8_t *) + +#define MSM_CAM_IOCTL_PICT_PP_DONE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 20, struct msm_snapshot_pp_status *) + +#define MSM_CAM_IOCTL_SENSOR_IO_CFG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 21, struct sensor_cfg_data *) + +#define MSM_CAMERA_LED_OFF 0 +#define MSM_CAMERA_LED_LOW 1 +#define MSM_CAMERA_LED_HIGH 2 + +#define MSM_CAM_IOCTL_FLASH_LED_CFG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 22, unsigned *) + +#define MSM_CAM_IOCTL_UNBLOCK_POLL_FRAME \ + _IO(MSM_CAM_IOCTL_MAGIC, 23) + +#define MSM_CAM_IOCTL_CTRL_COMMAND_2 \ + _IOW(MSM_CAM_IOCTL_MAGIC, 24, struct msm_ctrl_cmd *) + +#define MAX_SENSOR_NUM 3 +#define MAX_SENSOR_NAME 32 + +#define MSM_CAM_CTRL_CMD_DONE 0 +#define MSM_CAM_SENSOR_VFE_CMD 1 + +/***************************************************** + * structure + *****************************************************/ + +/* define five type of structures for userspace <==> kernel + * space communication: + * command 1 - 2 are from userspace ==> kernel + * command 3 - 4 are from kernel ==> userspace + * + * 1. control command: control command(from control thread), + * control status (from config thread); + */ +struct msm_ctrl_cmd { + uint16_t type; + uint16_t length; + void *value; + uint16_t status; + uint32_t timeout_ms; + int resp_fd; /* FIXME: to be used by the kernel, pass-through for now */ +}; + +struct msm_vfe_evt_msg { + unsigned short type; /* 1 == event (RPC), 0 == message (adsp) */ + unsigned short msg_id; + unsigned int len; /* size in, number of bytes out */ + void *data; +}; + +#define MSM_CAM_RESP_CTRL 0 +#define MSM_CAM_RESP_STAT_EVT_MSG 1 +#define MSM_CAM_RESP_V4L2 2 +#define MSM_CAM_RESP_MAX 3 + +/* this one is used to send ctrl/status up to config thread */ +struct msm_stats_event_ctrl { + /* 0 - ctrl_cmd from control thread, + * 1 - stats/event kernel, + * 2 - V4L control or read request */ + int resptype; + int timeout_ms; + struct msm_ctrl_cmd ctrl_cmd; + /* struct vfe_event_t stats_event; */ + struct msm_vfe_evt_msg stats_event; +}; + +/* 2. config command: config command(from config thread); */ +struct msm_camera_cfg_cmd { + /* what to config: + * 1 - sensor config, 2 - vfe config */ + uint16_t cfg_type; + + /* sensor config type */ + uint16_t cmd_type; + uint16_t queue; + uint16_t length; + void *value; +}; + +#define CMD_GENERAL 0 +#define CMD_AXI_CFG_OUT1 1 +#define CMD_AXI_CFG_SNAP_O1_AND_O2 2 +#define CMD_AXI_CFG_OUT2 3 +#define CMD_PICT_T_AXI_CFG 4 +#define CMD_PICT_M_AXI_CFG 5 +#define CMD_RAW_PICT_AXI_CFG 6 +#define CMD_STATS_AXI_CFG 7 +#define CMD_STATS_AF_AXI_CFG 8 +#define CMD_FRAME_BUF_RELEASE 9 +#define CMD_PREV_BUF_CFG 10 +#define CMD_SNAP_BUF_RELEASE 11 +#define CMD_SNAP_BUF_CFG 12 +#define CMD_STATS_DISABLE 13 +#define CMD_STATS_ENABLE 14 +#define CMD_STATS_AF_ENABLE 15 +#define CMD_STATS_BUF_RELEASE 16 +#define CMD_STATS_AF_BUF_RELEASE 17 +#define UPDATE_STATS_INVALID 18 + +/* vfe config command: config command(from config thread)*/ +struct msm_vfe_cfg_cmd { + int cmd_type; + uint16_t length; + void *value; +}; + +#define MAX_CAMERA_ENABLE_NAME_LEN 32 +struct camera_enable_cmd { + char name[MAX_CAMERA_ENABLE_NAME_LEN]; +}; + +#define MSM_PMEM_OUTPUT1 0 +#define MSM_PMEM_OUTPUT2 1 +#define MSM_PMEM_OUTPUT1_OUTPUT2 2 +#define MSM_PMEM_THUMBAIL 3 +#define MSM_PMEM_MAINIMG 4 +#define MSM_PMEM_RAW_MAINIMG 5 +#define MSM_PMEM_AEC_AWB 6 +#define MSM_PMEM_AF 7 +#define MSM_PMEM_MAX 8 + +#define FRAME_PREVIEW_OUTPUT1 0 +#define FRAME_PREVIEW_OUTPUT2 1 +#define FRAME_SNAPSHOT 2 +#define FRAME_THUMBAIL 3 +#define FRAME_RAW_SNAPSHOT 4 +#define FRAME_MAX 5 + +struct msm_pmem_info { + int type; + int fd; + void *vaddr; + uint32_t y_off; + uint32_t cbcr_off; + uint8_t active; +}; + +struct outputCfg { + uint32_t height; + uint32_t width; + + uint32_t window_height_firstline; + uint32_t window_height_lastline; +}; + +#define OUTPUT_1 0 +#define OUTPUT_2 1 +#define OUTPUT_1_AND_2 2 +#define CAMIF_TO_AXI_VIA_OUTPUT_2 3 +#define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 4 +#define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 5 +#define LAST_AXI_OUTPUT_MODE_ENUM = OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 6 + +#define MSM_FRAME_PREV_1 0 +#define MSM_FRAME_PREV_2 1 +#define MSM_FRAME_ENC 2 + +struct msm_frame { + int path; + unsigned long buffer; + uint32_t y_off; + uint32_t cbcr_off; + int fd; + + void *cropinfo; + int croplen; +}; + +#define STAT_AEAW 0 +#define STAT_AF 1 +#define STAT_MAX 2 + +struct msm_stats_buf { + int type; + unsigned long buffer; + int fd; +}; + +#define MSM_V4L2_VID_CAP_TYPE 0 +#define MSM_V4L2_STREAM_ON 1 +#define MSM_V4L2_STREAM_OFF 2 +#define MSM_V4L2_SNAPSHOT 3 +#define MSM_V4L2_QUERY_CTRL 4 +#define MSM_V4L2_GET_CTRL 5 +#define MSM_V4L2_SET_CTRL 6 +#define MSM_V4L2_QUERY 7 +#define MSM_V4L2_MAX 8 + +struct crop_info { + void *info; + int len; +}; + +struct msm_postproc { + int ftnum; + struct msm_frame fthumnail; + int fmnum; + struct msm_frame fmain; +}; + +struct msm_snapshot_pp_status { + void *status; +}; + +#define CFG_SET_MODE 0 +#define CFG_SET_EFFECT 1 +#define CFG_START 2 +#define CFG_PWR_UP 3 +#define CFG_PWR_DOWN 4 +#define CFG_WRITE_EXPOSURE_GAIN 5 +#define CFG_SET_DEFAULT_FOCUS 6 +#define CFG_MOVE_FOCUS 7 +#define CFG_REGISTER_TO_REAL_GAIN 8 +#define CFG_REAL_TO_REGISTER_GAIN 9 +#define CFG_SET_FPS 10 +#define CFG_SET_PICT_FPS 11 +#define CFG_SET_BRIGHTNESS 12 +#define CFG_SET_CONTRAST 13 +#define CFG_SET_ZOOM 14 +#define CFG_SET_EXPOSURE_MODE 15 +#define CFG_SET_WB 16 +#define CFG_SET_ANTIBANDING 17 +#define CFG_SET_EXP_GAIN 18 +#define CFG_SET_PICT_EXP_GAIN 19 +#define CFG_SET_LENS_SHADING 20 +#define CFG_GET_PICT_FPS 21 +#define CFG_GET_PREV_L_PF 22 +#define CFG_GET_PREV_P_PL 23 +#define CFG_GET_PICT_L_PF 24 +#define CFG_GET_PICT_P_PL 25 +#define CFG_GET_AF_MAX_STEPS 26 +#define CFG_GET_PICT_MAX_EXP_LC 27 +#define CFG_MAX 28 + +#define MOVE_NEAR 0 +#define MOVE_FAR 1 + +#define SENSOR_PREVIEW_MODE 0 +#define SENSOR_SNAPSHOT_MODE 1 +#define SENSOR_RAW_SNAPSHOT_MODE 2 + +#define SENSOR_QTR_SIZE 0 +#define SENSOR_FULL_SIZE 1 +#define SENSOR_INVALID_SIZE 2 + +#define CAMERA_EFFECT_OFF 0 +#define CAMERA_EFFECT_MONO 1 +#define CAMERA_EFFECT_NEGATIVE 2 +#define CAMERA_EFFECT_SOLARIZE 3 +#define CAMERA_EFFECT_PASTEL 4 +#define CAMERA_EFFECT_MOSAIC 5 +#define CAMERA_EFFECT_RESIZE 6 +#define CAMERA_EFFECT_SEPIA 7 +#define CAMERA_EFFECT_POSTERIZE 8 +#define CAMERA_EFFECT_WHITEBOARD 9 +#define CAMERA_EFFECT_BLACKBOARD 10 +#define CAMERA_EFFECT_AQUA 11 +#define CAMERA_EFFECT_MAX 12 + +struct sensor_pict_fps { + uint16_t prevfps; + uint16_t pictfps; +}; + +struct exp_gain_cfg { + uint16_t gain; + uint32_t line; +}; + +struct focus_cfg { + int32_t steps; + int dir; +}; + +struct fps_cfg { + uint16_t f_mult; + uint16_t fps_div; + uint32_t pict_fps_div; +}; + +struct sensor_cfg_data { + int cfgtype; + int mode; + int rs; + uint8_t max_steps; + + union { + int8_t effect; + uint8_t lens_shading; + uint16_t prevl_pf; + uint16_t prevp_pl; + uint16_t pictl_pf; + uint16_t pictp_pl; + uint32_t pict_max_exp_lc; + uint16_t p_fps; + struct sensor_pict_fps gfps; + struct exp_gain_cfg exp_gain; + struct focus_cfg focus; + struct fps_cfg fps; + } cfg; +}; + +#define GET_NAME 0 +#define GET_PREVIEW_LINE_PER_FRAME 1 +#define GET_PREVIEW_PIXELS_PER_LINE 2 +#define GET_SNAPSHOT_LINE_PER_FRAME 3 +#define GET_SNAPSHOT_PIXELS_PER_LINE 4 +#define GET_SNAPSHOT_FPS 5 +#define GET_SNAPSHOT_MAX_EP_LINE_CNT 6 + +struct msm_camsensor_info { + char name[MAX_SENSOR_NAME]; + uint8_t flash_enabled; +}; +#endif /* __LINUX_MSM_CAMERA_H */ diff --git a/drivers/staging/dream/qdsp5/Makefile b/drivers/staging/dream/qdsp5/Makefile index 991d4a7e157f..beedaaff5cc5 100644 --- a/drivers/staging/dream/qdsp5/Makefile +++ b/drivers/staging/dream/qdsp5/Makefile @@ -1,3 +1,4 @@ +EXTRA_CFLAGS=-Idrivers/staging/dream/include obj-y += adsp.o ifeq ($(CONFIG_MSM_AMSS_VERSION_6350),y) obj-y += adsp_info.o diff --git a/drivers/staging/dream/smd/Makefile b/drivers/staging/dream/smd/Makefile index 892c7414bbed..1c87618366a7 100644 --- a/drivers/staging/dream/smd/Makefile +++ b/drivers/staging/dream/smd/Makefile @@ -1,3 +1,4 @@ +EXTRA_CFLAGS=-Idrivers/staging/dream/include obj-$(CONFIG_MSM_SMD) += smd.o smd_tty.o smd_qmi.o obj-$(CONFIG_MSM_ONCRPCROUTER) += smd_rpcrouter.o obj-$(CONFIG_MSM_ONCRPCROUTER) += smd_rpcrouter_device.o -- cgit v1.2.3 From ccf972bd6bcb35ebd38e0a530c86088e45102aa4 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Sat, 21 Nov 2009 09:16:47 +0100 Subject: Staging: dream: fix memory leak in camera error path cppcheck found that ctrl_pmsm is leaked if the open operation fails. Signed-off-by: Eric Sesterhenn Signed-off-by: Pavel Machek Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dream/camera/msm_camera.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/dream/camera/msm_camera.c b/drivers/staging/dream/camera/msm_camera.c index 7d938772eacc..87e118d18827 100644 --- a/drivers/staging/dream/camera/msm_camera.c +++ b/drivers/staging/dream/camera/msm_camera.c @@ -1885,8 +1885,10 @@ static int msm_open_control(struct inode *inode, struct file *filep) return -ENOMEM; rc = msm_open_common(inode, filep, 0); - if (rc < 0) + if (rc < 0) { + kfree(ctrl_pmsm); return rc; + } ctrl_pmsm->pmsm = filep->private_data; filep->private_data = ctrl_pmsm; -- cgit v1.2.3 From bb0bfc2a6b3bc0a680b45690e8e427515cf229a7 Mon Sep 17 00:00:00 2001 From: Huang Weiyi Date: Sun, 13 Dec 2009 21:13:54 +0800 Subject: Staging: dream: remove duplicated #include Remove duplicated #include('s) in drivers/staging/dream/smd/smd_rpcrouter.c Signed-off-by: Huang Weiyi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dream/smd/smd_rpcrouter.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dream/smd/smd_rpcrouter.c b/drivers/staging/dream/smd/smd_rpcrouter.c index 5ac2cd4a5978..69911a7bc87a 100644 --- a/drivers/staging/dream/smd/smd_rpcrouter.c +++ b/drivers/staging/dream/smd/smd_rpcrouter.c @@ -38,8 +38,6 @@ #include #include -#include - #include #include "smd_rpcrouter.h" -- cgit v1.2.3 From cb13887657ec7130ff3e4ea7f78cda2e8a943b30 Mon Sep 17 00:00:00 2001 From: Thiago Farina Date: Sun, 22 Nov 2009 17:00:00 -0500 Subject: Staging: otus: fix some sparse warnings *apdbg.c: use NULL pointer instead of 0 interger. Also make two functions private. Signed-off-by: Thiago Farina Signed-off-by: Greg Kroah-Hartman --- drivers/staging/otus/apdbg.c | 53 +++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 28 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/otus/apdbg.c b/drivers/staging/otus/apdbg.c index 0eb93f19958a..b59028e7e33c 100644 --- a/drivers/staging/otus/apdbg.c +++ b/drivers/staging/otus/apdbg.c @@ -90,8 +90,27 @@ struct zdap_ioctl { #endif -char hex(char); -unsigned char asctohex(char *str); +static char hex(char v) +{ + if (isdigit(v)) + return v - '0'; + else if (isxdigit(v)) + return tolower(v) - 'a' + 10; + else + return 0; +} + +static unsigned char asctohex(char *str) +{ + unsigned char value; + + value = hex(*str) & 0x0f; + value = value << 4; + str++; + value |= hex(*str) & 0x0f; + + return value; +} char *prgname; @@ -109,10 +128,10 @@ int set_ioctl(int sock, struct ifreq *req) int read_reg(int sock, struct ifreq *req) { - struct zdap_ioctl *zdreq = 0; + struct zdap_ioctl *zdreq = NULL; if (!set_ioctl(sock, req)) - return -1; + return -1; /* * zdreq = (struct zdap_ioctl *)req->ifr_data; @@ -125,7 +144,7 @@ int read_reg(int sock, struct ifreq *req) int read_mem(int sock, struct ifreq *req) { - struct zdap_ioctl *zdreq = 0; + struct zdap_ioctl *zdreq = NULL; int i; if (!set_ioctl(sock, req)) @@ -368,7 +387,7 @@ int main(int argc, char **argv) zdreq.addr = addr; zdreq.cmd = ZM_IOCTL_SET_PIBSS_MODE; - } else { + } else { fprintf(stderr, "error action\n"); exit(1); } @@ -380,25 +399,3 @@ fail: exit(0); } -unsigned char asctohex(char *str) -{ - unsigned char value; - - value = hex(*str) & 0x0f; - value = value << 4; - str++; - value |= hex(*str) & 0x0f; - - return value; -} - -char hex(char v) -{ - if (isdigit(v)) - return v - '0'; - else if (isxdigit(v)) - return tolower(v) - 'a' + 10; - else - return 0; -} - -- cgit v1.2.3 From 1c47faa0af6f9316e863174f6d30ede60ebf7e36 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Thu, 10 Dec 2009 16:39:44 +0100 Subject: Staging: otus: Fix branch in zfProtRspSim() This semicolon is misplaced. Signed-off-by: Roel Kluin Signed-off-by: Greg Kroah-Hartman --- drivers/staging/otus/80211core/ctxrx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/otus/80211core/ctxrx.c b/drivers/staging/otus/80211core/ctxrx.c index ac54d5a636b0..7fa4f48fc8ca 100644 --- a/drivers/staging/otus/80211core/ctxrx.c +++ b/drivers/staging/otus/80211core/ctxrx.c @@ -536,8 +536,7 @@ void zfProtRspSim(zdev_t* dev, zbuf_t* buf) zm_msg2_rx(ZM_LV_2, "ip1=", dip[1]); //ARP request to 192.168.1.15 - if ((arpOp == 0x0100) && (dip[0] == 0xa8c0) && (dip[1] == 0x0f01)); - { + if ((arpOp == 0x0100) && (dip[0] == 0xa8c0) && (dip[1] == 0x0f01)) { zm_msg0_rx(ZM_LV_2, "ARP"); /* ARP response */ zmw_rx_buf_writeh(dev, buf, 20, 0x0200); -- cgit v1.2.3 From 51616e21066d040988a33effa82d4ef37fd60959 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 15 Dec 2009 08:42:43 +0000 Subject: Staging: vme: Correct vme_user error message typo Correction of erroneous error message in vme_user.c. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/devices/vme_user.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/devices/vme_user.c b/drivers/staging/vme/devices/vme_user.c index e228942ee081..2159540d9383 100644 --- a/drivers/staging/vme/devices/vme_user.c +++ b/drivers/staging/vme/devices/vme_user.c @@ -574,8 +574,8 @@ static int __init vme_user_init(void) * in future revisions if that ever becomes necessary. */ if (bus_num > USER_BUS_MAX) { - printk(KERN_ERR "%s: Driver only able to handle %d PIO2 " - "Cards\n", driver_name, USER_BUS_MAX); + printk(KERN_ERR "%s: Driver only able to handle %d buses\n", + driver_name, USER_BUS_MAX); bus_num = USER_BUS_MAX; } -- cgit v1.2.3 From 638f199db463a8f2b1535c45ab27d04bb1a55baf Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 15 Dec 2009 08:42:49 +0000 Subject: Staging: vme: Allow override of geographical address on tsi148 Geographical addressing only works if the VME backplane supports it. There are a large number of old backplanes which do not support geographical addressing. These boards will generally report a slot ID of zero - which is an invalid ID in the slot numbering scheme. Allow the geographical address to be over-ridden on the tsi148 so that a slot ID can be provided manually in these circumstances. Signed-off-by: Markus Kraemer Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/bridges/vme_tsi148.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/bridges/vme_tsi148.c b/drivers/staging/vme/bridges/vme_tsi148.c index 89a7dccb934f..324cc389586f 100644 --- a/drivers/staging/vme/bridges/vme_tsi148.c +++ b/drivers/staging/vme/bridges/vme_tsi148.c @@ -63,6 +63,7 @@ int tsi148_slot_get(void); /* Modue parameter */ int err_chk = 0; +static int geoid; /* XXX These should all be in a per device structure */ struct vme_bridge *tsi148_bridge; @@ -2145,8 +2146,12 @@ int tsi148_slot_get(void) { u32 slot = 0; - slot = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT); - slot = slot & TSI148_LCSR_VSTAT_GA_M; + if (!geoid) { + slot = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT); + slot = slot & TSI148_LCSR_VSTAT_GA_M; + } else + slot = geoid; + return (int)slot; } @@ -2196,6 +2201,7 @@ static int tsi148_crcsr_init(struct pci_dev *pdev) vstat = tsi148_slot_get(); if (cbar != vstat) { + cbar = vstat; dev_info(&pdev->dev, "Setting CR/CSR offset\n"); iowrite32be(cbar<<3, tsi148_bridge->base + TSI148_CBAR); } @@ -2458,8 +2464,13 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) data = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT); dev_info(&pdev->dev, "Board is%s the VME system controller\n", (data & TSI148_LCSR_VSTAT_SCONS)? "" : " not"); - dev_info(&pdev->dev, "VME geographical address is %d\n", - data & TSI148_LCSR_VSTAT_GA_M); + if (!geoid) { + dev_info(&pdev->dev, "VME geographical address is %d\n", + data & TSI148_LCSR_VSTAT_GA_M); + } else { + dev_info(&pdev->dev, "VME geographical address is set to %d\n", + geoid); + } dev_info(&pdev->dev, "VME Write and flush and error check is %s\n", err_chk ? "enabled" : "disabled"); @@ -2608,7 +2619,8 @@ static void tsi148_remove(struct pci_dev *pdev) /* resources are stored in link list */ list_for_each(pos, &(tsi148_bridge->master_resources)) { - master_image = list_entry(pos, struct vme_master_resource, list); + master_image = list_entry(pos, struct vme_master_resource, + list); list_del(pos); kfree(master_image); } @@ -2634,6 +2646,9 @@ static void __exit tsi148_exit(void) MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes"); module_param(err_chk, bool, 0); +MODULE_PARM_DESC(geoid, "Override geographical addressing"); +module_param(geoid, int, 0); + MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 12b2d5c0895a03e941e7c145d9d23a45908a857b Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 15 Dec 2009 08:42:56 +0000 Subject: Staging: vme: Allow override of geographical address on ca91c142 Geographical addressing only works if the VME backplane supports it. There are a large number of old backplanes which do not support geographical addressing. These boards will generally report a slot ID of zero - which is an invalid ID in the slot numbering scheme. Allow the geographical address to be over-ridden on the ca91c142 so that a slot ID can be provided manually in these circumstances. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/bridges/vme_ca91cx42.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index 1cf3e91db59d..5799b0927686 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c @@ -38,6 +38,9 @@ static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *); static void ca91cx42_remove(struct pci_dev *); static void __exit ca91cx42_exit(void); +/* Module parameters */ +static int geoid; + struct vme_bridge *ca91cx42_bridge; wait_queue_head_t dma_queue; wait_queue_head_t iack_queue; @@ -881,8 +884,12 @@ int ca91cx42_slot_get(void) { u32 slot = 0; - slot = ioread32(ca91cx42_bridge->base + VCSR_BS); - slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27); + if (!geoid) { + slot = ioread32(ca91cx42_bridge->base + VCSR_BS); + slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27); + } else + slot = geoid; + return (int)slot; } @@ -1299,6 +1306,9 @@ static void __exit ca91cx42_exit(void) pci_unregister_driver(&ca91cx42_driver); } +MODULE_PARM_DESC(geoid, "Override geographical addressing"); +module_param(geoid, int, 0); + MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From ead1f3e301e2d886ef89f8d0c82b4d495f2a81c2 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 15 Dec 2009 08:43:02 +0000 Subject: Staging: vme: Fix checkpatch errors on VME core. Running checkpatch on the core VME code highlights many errors. Fix them. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/vme.c | 222 +++++++++++++++++++-------------------- drivers/staging/vme/vme.h | 23 ++-- drivers/staging/vme/vme_bridge.h | 8 +- 3 files changed, 126 insertions(+), 127 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/vme.c b/drivers/staging/vme/vme.c index 994fdb9b2127..c915e9285780 100644 --- a/drivers/staging/vme/vme.c +++ b/drivers/staging/vme/vme.c @@ -37,8 +37,8 @@ static unsigned int vme_bus_numbers; DEFINE_MUTEX(vme_bus_num_mtx); -static void __exit vme_exit (void); -static int __init vme_init (void); +static void __exit vme_exit(void); +static int __init vme_init(void); /* @@ -86,26 +86,26 @@ static struct vme_bridge *find_bridge(struct vme_resource *resource) * XXX VME bridges could be available on buses other than PCI. At the momment * this framework only supports PCI devices. */ -void * vme_alloc_consistent(struct vme_resource *resource, size_t size, +void *vme_alloc_consistent(struct vme_resource *resource, size_t size, dma_addr_t *dma) { struct vme_bridge *bridge; struct pci_dev *pdev; - if(resource == NULL) { - printk("No resource\n"); + if (resource == NULL) { + printk(KERN_ERR "No resource\n"); return NULL; } bridge = find_bridge(resource); - if(bridge == NULL) { - printk("Can't find bridge\n"); + if (bridge == NULL) { + printk(KERN_ERR "Can't find bridge\n"); return NULL; } /* Find pci_dev container of dev */ if (bridge->parent == NULL) { - printk("Dev entry NULL\n"); + printk(KERN_ERR "Dev entry NULL\n"); return NULL; } pdev = container_of(bridge->parent, struct pci_dev, dev); @@ -126,14 +126,14 @@ void vme_free_consistent(struct vme_resource *resource, size_t size, struct vme_bridge *bridge; struct pci_dev *pdev; - if(resource == NULL) { - printk("No resource\n"); + if (resource == NULL) { + printk(KERN_ERR "No resource\n"); return; } bridge = find_bridge(resource); - if(bridge == NULL) { - printk("Can't find bridge\n"); + if (bridge == NULL) { + printk(KERN_ERR "Can't find bridge\n"); return; } @@ -216,7 +216,7 @@ static int vme_check_window(vme_address_t aspace, unsigned long long vme_base, /* User Defined */ break; default: - printk("Invalid address space\n"); + printk(KERN_ERR "Invalid address space\n"); retval = -EINVAL; break; } @@ -228,7 +228,7 @@ static int vme_check_window(vme_address_t aspace, unsigned long long vme_base, * Request a slave image with specific attributes, return some unique * identifier. */ -struct vme_resource * vme_slave_request(struct device *dev, +struct vme_resource *vme_slave_request(struct device *dev, vme_address_t address, vme_cycle_t cycle) { struct vme_bridge *bridge; @@ -249,13 +249,13 @@ struct vme_resource * vme_slave_request(struct device *dev, struct vme_slave_resource, list); if (slave_image == NULL) { - printk("Registered NULL Slave resource\n"); + printk(KERN_ERR "Registered NULL Slave resource\n"); continue; } /* Find an unlocked and compatible image */ mutex_lock(&(slave_image->mtx)); - if(((slave_image->address_attr & address) == address) && + if (((slave_image->address_attr & address) == address) && ((slave_image->cycle_attr & cycle) == cycle) && (slave_image->locked == 0)) { @@ -292,7 +292,7 @@ err_bus: } EXPORT_SYMBOL(vme_slave_request); -int vme_slave_set (struct vme_resource *resource, int enabled, +int vme_slave_set(struct vme_resource *resource, int enabled, unsigned long long vme_base, unsigned long long size, dma_addr_t buf_base, vme_address_t aspace, vme_cycle_t cycle) { @@ -301,25 +301,25 @@ int vme_slave_set (struct vme_resource *resource, int enabled, int retval; if (resource->type != VME_SLAVE) { - printk("Not a slave resource\n"); + printk(KERN_ERR "Not a slave resource\n"); return -EINVAL; } image = list_entry(resource->entry, struct vme_slave_resource, list); if (bridge->slave_set == NULL) { - printk("Function not supported\n"); + printk(KERN_ERR "Function not supported\n"); return -ENOSYS; } - if(!(((image->address_attr & aspace) == aspace) && + if (!(((image->address_attr & aspace) == aspace) && ((image->cycle_attr & cycle) == cycle))) { - printk("Invalid attributes\n"); + printk(KERN_ERR "Invalid attributes\n"); return -EINVAL; } retval = vme_check_window(aspace, vme_base, size); - if(retval) + if (retval) return retval; return bridge->slave_set(image, enabled, vme_base, size, buf_base, @@ -327,7 +327,7 @@ int vme_slave_set (struct vme_resource *resource, int enabled, } EXPORT_SYMBOL(vme_slave_set); -int vme_slave_get (struct vme_resource *resource, int *enabled, +int vme_slave_get(struct vme_resource *resource, int *enabled, unsigned long long *vme_base, unsigned long long *size, dma_addr_t *buf_base, vme_address_t *aspace, vme_cycle_t *cycle) { @@ -335,14 +335,14 @@ int vme_slave_get (struct vme_resource *resource, int *enabled, struct vme_slave_resource *image; if (resource->type != VME_SLAVE) { - printk("Not a slave resource\n"); + printk(KERN_ERR "Not a slave resource\n"); return -EINVAL; } image = list_entry(resource->entry, struct vme_slave_resource, list); if (bridge->slave_get == NULL) { - printk("vme_slave_get not supported\n"); + printk(KERN_ERR "vme_slave_get not supported\n"); return -EINVAL; } @@ -356,14 +356,14 @@ void vme_slave_free(struct vme_resource *resource) struct vme_slave_resource *slave_image; if (resource->type != VME_SLAVE) { - printk("Not a slave resource\n"); + printk(KERN_ERR "Not a slave resource\n"); return; } slave_image = list_entry(resource->entry, struct vme_slave_resource, list); if (slave_image == NULL) { - printk("Can't find slave resource\n"); + printk(KERN_ERR "Can't find slave resource\n"); return; } @@ -384,7 +384,7 @@ EXPORT_SYMBOL(vme_slave_free); * Request a master image with specific attributes, return some unique * identifier. */ -struct vme_resource * vme_master_request(struct device *dev, +struct vme_resource *vme_master_request(struct device *dev, vme_address_t address, vme_cycle_t cycle, vme_width_t dwidth) { struct vme_bridge *bridge; @@ -411,7 +411,7 @@ struct vme_resource * vme_master_request(struct device *dev, /* Find an unlocked and compatible image */ spin_lock(&(master_image->lock)); - if(((master_image->address_attr & address) == address) && + if (((master_image->address_attr & address) == address) && ((master_image->cycle_attr & cycle) == cycle) && ((master_image->width_attr & dwidth) == dwidth) && (master_image->locked == 0)) { @@ -452,7 +452,7 @@ err_bus: } EXPORT_SYMBOL(vme_master_request); -int vme_master_set (struct vme_resource *resource, int enabled, +int vme_master_set(struct vme_resource *resource, int enabled, unsigned long long vme_base, unsigned long long size, vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth) { @@ -461,26 +461,26 @@ int vme_master_set (struct vme_resource *resource, int enabled, int retval; if (resource->type != VME_MASTER) { - printk("Not a master resource\n"); + printk(KERN_ERR "Not a master resource\n"); return -EINVAL; } image = list_entry(resource->entry, struct vme_master_resource, list); if (bridge->master_set == NULL) { - printk("vme_master_set not supported\n"); + printk(KERN_WARNING "vme_master_set not supported\n"); return -EINVAL; } - if(!(((image->address_attr & aspace) == aspace) && + if (!(((image->address_attr & aspace) == aspace) && ((image->cycle_attr & cycle) == cycle) && ((image->width_attr & dwidth) == dwidth))) { - printk("Invalid attributes\n"); + printk(KERN_WARNING "Invalid attributes\n"); return -EINVAL; } retval = vme_check_window(aspace, vme_base, size); - if(retval) + if (retval) return retval; return bridge->master_set(image, enabled, vme_base, size, aspace, @@ -488,7 +488,7 @@ int vme_master_set (struct vme_resource *resource, int enabled, } EXPORT_SYMBOL(vme_master_set); -int vme_master_get (struct vme_resource *resource, int *enabled, +int vme_master_get(struct vme_resource *resource, int *enabled, unsigned long long *vme_base, unsigned long long *size, vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth) { @@ -496,14 +496,14 @@ int vme_master_get (struct vme_resource *resource, int *enabled, struct vme_master_resource *image; if (resource->type != VME_MASTER) { - printk("Not a master resource\n"); + printk(KERN_ERR "Not a master resource\n"); return -EINVAL; } image = list_entry(resource->entry, struct vme_master_resource, list); if (bridge->master_get == NULL) { - printk("vme_master_set not supported\n"); + printk(KERN_WARNING "vme_master_set not supported\n"); return -EINVAL; } @@ -515,7 +515,7 @@ EXPORT_SYMBOL(vme_master_get); /* * Read data out of VME space into a buffer. */ -ssize_t vme_master_read (struct vme_resource *resource, void *buf, size_t count, +ssize_t vme_master_read(struct vme_resource *resource, void *buf, size_t count, loff_t offset) { struct vme_bridge *bridge = find_bridge(resource); @@ -523,12 +523,12 @@ ssize_t vme_master_read (struct vme_resource *resource, void *buf, size_t count, size_t length; if (bridge->master_read == NULL) { - printk("Reading from resource not supported\n"); + printk(KERN_WARNING "Reading from resource not supported\n"); return -EINVAL; } if (resource->type != VME_MASTER) { - printk("Not a master resource\n"); + printk(KERN_ERR "Not a master resource\n"); return -EINVAL; } @@ -537,7 +537,7 @@ ssize_t vme_master_read (struct vme_resource *resource, void *buf, size_t count, length = vme_get_size(resource); if (offset > length) { - printk("Invalid Offset\n"); + printk(KERN_WARNING "Invalid Offset\n"); return -EFAULT; } @@ -552,7 +552,7 @@ EXPORT_SYMBOL(vme_master_read); /* * Write data out to VME space from a buffer. */ -ssize_t vme_master_write (struct vme_resource *resource, void *buf, +ssize_t vme_master_write(struct vme_resource *resource, void *buf, size_t count, loff_t offset) { struct vme_bridge *bridge = find_bridge(resource); @@ -560,12 +560,12 @@ ssize_t vme_master_write (struct vme_resource *resource, void *buf, size_t length; if (bridge->master_write == NULL) { - printk("Writing to resource not supported\n"); + printk(KERN_WARNING "Writing to resource not supported\n"); return -EINVAL; } if (resource->type != VME_MASTER) { - printk("Not a master resource\n"); + printk(KERN_ERR "Not a master resource\n"); return -EINVAL; } @@ -574,7 +574,7 @@ ssize_t vme_master_write (struct vme_resource *resource, void *buf, length = vme_get_size(resource); if (offset > length) { - printk("Invalid Offset\n"); + printk(KERN_WARNING "Invalid Offset\n"); return -EFAULT; } @@ -588,19 +588,19 @@ EXPORT_SYMBOL(vme_master_write); /* * Perform RMW cycle to provided location. */ -unsigned int vme_master_rmw (struct vme_resource *resource, unsigned int mask, +unsigned int vme_master_rmw(struct vme_resource *resource, unsigned int mask, unsigned int compare, unsigned int swap, loff_t offset) { struct vme_bridge *bridge = find_bridge(resource); struct vme_master_resource *image; if (bridge->master_rmw == NULL) { - printk("Writing to resource not supported\n"); + printk(KERN_WARNING "Writing to resource not supported\n"); return -EINVAL; } if (resource->type != VME_MASTER) { - printk("Not a master resource\n"); + printk(KERN_ERR "Not a master resource\n"); return -EINVAL; } @@ -615,14 +615,14 @@ void vme_master_free(struct vme_resource *resource) struct vme_master_resource *master_image; if (resource->type != VME_MASTER) { - printk("Not a master resource\n"); + printk(KERN_ERR "Not a master resource\n"); return; } master_image = list_entry(resource->entry, struct vme_master_resource, list); if (master_image == NULL) { - printk("Can't find master resource\n"); + printk(KERN_ERR "Can't find master resource\n"); return; } @@ -666,13 +666,13 @@ struct vme_resource *vme_dma_request(struct device *dev) struct vme_dma_resource, list); if (dma_ctrlr == NULL) { - printk("Registered NULL DMA resource\n"); + printk(KERN_ERR "Registered NULL DMA resource\n"); continue; } /* Find an unlocked controller */ mutex_lock(&(dma_ctrlr->mtx)); - if(dma_ctrlr->locked == 0) { + if (dma_ctrlr->locked == 0) { dma_ctrlr->locked = 1; mutex_unlock(&(dma_ctrlr->mtx)); allocated_ctrlr = dma_ctrlr; @@ -715,16 +715,15 @@ struct vme_dma_list *vme_new_dma_list(struct vme_resource *resource) struct vme_dma_list *dma_list; if (resource->type != VME_DMA) { - printk("Not a DMA resource\n"); + printk(KERN_ERR "Not a DMA resource\n"); return NULL; } ctrlr = list_entry(resource->entry, struct vme_dma_resource, list); - dma_list = (struct vme_dma_list *)kmalloc( - sizeof(struct vme_dma_list), GFP_KERNEL); - if(dma_list == NULL) { - printk("Unable to allocate memory for new dma list\n"); + dma_list = kmalloc(sizeof(struct vme_dma_list), GFP_KERNEL); + if (dma_list == NULL) { + printk(KERN_ERR "Unable to allocate memory for new dma list\n"); return NULL; } INIT_LIST_HEAD(&(dma_list->entries)); @@ -744,17 +743,17 @@ struct vme_dma_attr *vme_dma_pattern_attribute(u32 pattern, struct vme_dma_attr *attributes; struct vme_dma_pattern *pattern_attr; - attributes = (struct vme_dma_attr *)kmalloc( - sizeof(struct vme_dma_attr), GFP_KERNEL); - if(attributes == NULL) { - printk("Unable to allocate memory for attributes structure\n"); + attributes = kmalloc(sizeof(struct vme_dma_attr), GFP_KERNEL); + if (attributes == NULL) { + printk(KERN_ERR "Unable to allocate memory for attributes " + "structure\n"); goto err_attr; } - pattern_attr = (struct vme_dma_pattern *)kmalloc( - sizeof(struct vme_dma_pattern), GFP_KERNEL); - if(pattern_attr == NULL) { - printk("Unable to allocate memory for pattern attributes\n"); + pattern_attr = kmalloc(sizeof(struct vme_dma_pattern), GFP_KERNEL); + if (pattern_attr == NULL) { + printk(KERN_ERR "Unable to allocate memory for pattern " + "attributes\n"); goto err_pat; } @@ -784,17 +783,17 @@ struct vme_dma_attr *vme_dma_pci_attribute(dma_addr_t address) /* XXX Run some sanity checks here */ - attributes = (struct vme_dma_attr *)kmalloc( - sizeof(struct vme_dma_attr), GFP_KERNEL); - if(attributes == NULL) { - printk("Unable to allocate memory for attributes structure\n"); + attributes = kmalloc(sizeof(struct vme_dma_attr), GFP_KERNEL); + if (attributes == NULL) { + printk(KERN_ERR "Unable to allocate memory for attributes " + "structure\n"); goto err_attr; } - pci_attr = (struct vme_dma_pci *)kmalloc(sizeof(struct vme_dma_pci), - GFP_KERNEL); - if(pci_attr == NULL) { - printk("Unable to allocate memory for pci attributes\n"); + pci_attr = kmalloc(sizeof(struct vme_dma_pci), GFP_KERNEL); + if (pci_attr == NULL) { + printk(KERN_ERR "Unable to allocate memory for pci " + "attributes\n"); goto err_pci; } @@ -826,17 +825,18 @@ struct vme_dma_attr *vme_dma_vme_attribute(unsigned long long address, /* XXX Run some sanity checks here */ - attributes = (struct vme_dma_attr *)kmalloc( + attributes = kmalloc( sizeof(struct vme_dma_attr), GFP_KERNEL); - if(attributes == NULL) { - printk("Unable to allocate memory for attributes structure\n"); + if (attributes == NULL) { + printk(KERN_ERR "Unable to allocate memory for attributes " + "structure\n"); goto err_attr; } - vme_attr = (struct vme_dma_vme *)kmalloc(sizeof(struct vme_dma_vme), - GFP_KERNEL); - if(vme_attr == NULL) { - printk("Unable to allocate memory for vme attributes\n"); + vme_attr = kmalloc(sizeof(struct vme_dma_vme), GFP_KERNEL); + if (vme_attr == NULL) { + printk(KERN_ERR "Unable to allocate memory for vme " + "attributes\n"); goto err_vme; } @@ -875,12 +875,12 @@ int vme_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, int retval; if (bridge->dma_list_add == NULL) { - printk("Link List DMA generation not supported\n"); + printk(KERN_WARNING "Link List DMA generation not supported\n"); return -EINVAL; } if (!mutex_trylock(&(list->mtx))) { - printk("Link List already submitted\n"); + printk(KERN_ERR "Link List already submitted\n"); return -EINVAL; } @@ -898,7 +898,7 @@ int vme_dma_list_exec(struct vme_dma_list *list) int retval; if (bridge->dma_list_exec == NULL) { - printk("Link List DMA execution not supported\n"); + printk(KERN_ERR "Link List DMA execution not supported\n"); return -EINVAL; } @@ -918,12 +918,12 @@ int vme_dma_list_free(struct vme_dma_list *list) int retval; if (bridge->dma_list_empty == NULL) { - printk("Emptying of Link Lists not supported\n"); + printk(KERN_WARNING "Emptying of Link Lists not supported\n"); return -EINVAL; } if (!mutex_trylock(&(list->mtx))) { - printk("Link List in use\n"); + printk(KERN_ERR "Link List in use\n"); return -EINVAL; } @@ -933,7 +933,7 @@ int vme_dma_list_free(struct vme_dma_list *list) */ retval = bridge->dma_list_empty(list); if (retval) { - printk("Unable to empty link-list entries\n"); + printk(KERN_ERR "Unable to empty link-list entries\n"); mutex_unlock(&(list->mtx)); return retval; } @@ -949,19 +949,19 @@ int vme_dma_free(struct vme_resource *resource) struct vme_dma_resource *ctrlr; if (resource->type != VME_DMA) { - printk("Not a DMA resource\n"); + printk(KERN_ERR "Not a DMA resource\n"); return -EINVAL; } ctrlr = list_entry(resource->entry, struct vme_dma_resource, list); if (!mutex_trylock(&(ctrlr->mtx))) { - printk("Resource busy, can't free\n"); + printk(KERN_ERR "Resource busy, can't free\n"); return -EBUSY; } if (!(list_empty(&(ctrlr->pending)) && list_empty(&(ctrlr->running)))) { - printk("Resource still processing transfers\n"); + printk(KERN_WARNING "Resource still processing transfers\n"); mutex_unlock(&(ctrlr->mtx)); return -EBUSY; } @@ -1002,7 +1002,7 @@ int vme_irq_request(struct device *dev, int level, int statid, return -EINVAL; } - if((level < 1) || (level > 7)) { + if ((level < 1) || (level > 7)) { printk(KERN_ERR "Invalid interrupt level\n"); return -EINVAL; } @@ -1043,7 +1043,7 @@ void vme_irq_free(struct device *dev, int level, int statid) return; } - if((level < 1) || (level > 7)) { + if ((level < 1) || (level > 7)) { printk(KERN_ERR "Invalid interrupt level\n"); return; } @@ -1078,13 +1078,13 @@ int vme_irq_generate(struct device *dev, int level, int statid) return -EINVAL; } - if((level < 1) || (level > 7)) { + if ((level < 1) || (level > 7)) { printk(KERN_WARNING "Invalid interrupt level\n"); return -EINVAL; } if (bridge->irq_generate == NULL) { - printk("Interrupt generation not supported\n"); + printk(KERN_WARNING "Interrupt generation not supported\n"); return -EINVAL; } @@ -1297,7 +1297,7 @@ int vme_slot_get(struct device *bus) } if (bridge->slot_get == NULL) { - printk("vme_slot_get not supported\n"); + printk(KERN_WARNING "vme_slot_get not supported\n"); return -EINVAL; } @@ -1331,7 +1331,7 @@ static void vme_free_bus_num(int bus) mutex_unlock(&vme_bus_num_mtx); } -int vme_register_bridge (struct vme_bridge *bridge) +int vme_register_bridge(struct vme_bridge *bridge) { struct device *dev; int retval; @@ -1358,7 +1358,7 @@ int vme_register_bridge (struct vme_bridge *bridge) dev_set_name(dev, "vme-%x.%x", bridge->num, i + 1); retval = device_register(dev); - if(retval) + if (retval) goto err_reg; } @@ -1375,7 +1375,7 @@ err_reg: } EXPORT_SYMBOL(vme_register_bridge); -void vme_unregister_bridge (struct vme_bridge *bridge) +void vme_unregister_bridge(struct vme_bridge *bridge) { int i; struct device *dev; @@ -1392,7 +1392,7 @@ EXPORT_SYMBOL(vme_unregister_bridge); /* - Driver Registration --------------------------------------------------- */ -int vme_register_driver (struct vme_driver *drv) +int vme_register_driver(struct vme_driver *drv) { drv->driver.name = drv->name; drv->driver.bus = &vme_bus_type; @@ -1401,7 +1401,7 @@ int vme_register_driver (struct vme_driver *drv) } EXPORT_SYMBOL(vme_register_driver); -void vme_unregister_driver (struct vme_driver *drv) +void vme_unregister_driver(struct vme_driver *drv) { driver_unregister(&drv->driver); } @@ -1418,10 +1418,10 @@ int vme_calc_slot(struct device *dev) /* Determine slot number */ num = 0; - while(num < VME_SLOTS_MAX) { - if(&(bridge->dev[num]) == dev) { + while (num < VME_SLOTS_MAX) { + if (&(bridge->dev[num]) == dev) break; - } + num++; } if (num == VME_SLOTS_MAX) { @@ -1437,8 +1437,8 @@ err_dev: static struct vme_driver *dev_to_vme_driver(struct device *dev) { - if(dev->driver == NULL) - printk("Bugger dev->driver is NULL\n"); + if (dev->driver == NULL) + printk(KERN_ERR "Bugger dev->driver is NULL\n"); return container_of(dev->driver, struct vme_driver, driver); } @@ -1462,7 +1462,7 @@ static int vme_bus_match(struct device *dev, struct device_driver *drv) } i = 0; - while((driver->bind_table[i].bus != 0) || + while ((driver->bind_table[i].bus != 0) || (driver->bind_table[i].slot != 0)) { if (bridge->num == driver->bind_table[i].bus) { @@ -1493,9 +1493,8 @@ static int vme_bus_probe(struct device *dev) driver = dev_to_vme_driver(dev); bridge = dev_to_bridge(dev); - if(driver->probe != NULL) { + if (driver->probe != NULL) retval = driver->probe(dev, bridge->num, vme_calc_slot(dev)); - } return retval; } @@ -1509,9 +1508,8 @@ static int vme_bus_remove(struct device *dev) driver = dev_to_vme_driver(dev); bridge = dev_to_bridge(dev); - if(driver->remove != NULL) { + if (driver->remove != NULL) retval = driver->remove(dev, bridge->num, vme_calc_slot(dev)); - } return retval; } @@ -1524,12 +1522,12 @@ struct bus_type vme_bus_type = { }; EXPORT_SYMBOL(vme_bus_type); -static int __init vme_init (void) +static int __init vme_init(void) { return bus_register(&vme_bus_type); } -static void __exit vme_exit (void) +static void __exit vme_exit(void) { bus_unregister(&vme_bus_type); } diff --git a/drivers/staging/vme/vme.h b/drivers/staging/vme/vme.h index 97dc22e34caf..5a4d163fae10 100644 --- a/drivers/staging/vme/vme.h +++ b/drivers/staging/vme/vme.h @@ -98,28 +98,29 @@ struct vme_driver { struct device_driver driver; }; -void * vme_alloc_consistent(struct vme_resource *, size_t, dma_addr_t *); +void *vme_alloc_consistent(struct vme_resource *, size_t, dma_addr_t *); void vme_free_consistent(struct vme_resource *, size_t, void *, dma_addr_t); size_t vme_get_size(struct vme_resource *); -struct vme_resource * vme_slave_request(struct device *, vme_address_t, vme_cycle_t); -int vme_slave_set (struct vme_resource *, int, unsigned long long, +struct vme_resource *vme_slave_request(struct device *, vme_address_t, + vme_cycle_t); +int vme_slave_set(struct vme_resource *, int, unsigned long long, unsigned long long, dma_addr_t, vme_address_t, vme_cycle_t); -int vme_slave_get (struct vme_resource *, int *, unsigned long long *, +int vme_slave_get(struct vme_resource *, int *, unsigned long long *, unsigned long long *, dma_addr_t *, vme_address_t *, vme_cycle_t *); void vme_slave_free(struct vme_resource *); -struct vme_resource * vme_master_request(struct device *, vme_address_t, vme_cycle_t, - vme_width_t); -int vme_master_set (struct vme_resource *, int, unsigned long long, +struct vme_resource *vme_master_request(struct device *, vme_address_t, + vme_cycle_t, vme_width_t); +int vme_master_set(struct vme_resource *, int, unsigned long long, unsigned long long, vme_address_t, vme_cycle_t, vme_width_t); -int vme_master_get (struct vme_resource *, int *, unsigned long long *, +int vme_master_get(struct vme_resource *, int *, unsigned long long *, unsigned long long *, vme_address_t *, vme_cycle_t *, vme_width_t *); ssize_t vme_master_read(struct vme_resource *, void *, size_t, loff_t); ssize_t vme_master_write(struct vme_resource *, void *, size_t, loff_t); -unsigned int vme_master_rmw (struct vme_resource *, unsigned int, unsigned int, +unsigned int vme_master_rmw(struct vme_resource *, unsigned int, unsigned int, unsigned int, loff_t); void vme_master_free(struct vme_resource *); @@ -153,8 +154,8 @@ void vme_lm_free(struct vme_resource *); int vme_slot_get(struct device *); -int vme_register_driver (struct vme_driver *); -void vme_unregister_driver (struct vme_driver *); +int vme_register_driver(struct vme_driver *); +void vme_unregister_driver(struct vme_driver *); #endif /* _VME_H_ */ diff --git a/drivers/staging/vme/vme_bridge.h b/drivers/staging/vme/vme_bridge.h index 851fa92559f6..a64677e0a31a 100644 --- a/drivers/staging/vme/vme_bridge.h +++ b/drivers/staging/vme/vme_bridge.h @@ -101,7 +101,7 @@ struct vme_irq { * Currently we assume that all chips are PCI-based */ struct vme_bridge { - char name[VMENAMSIZ]; + char name[VMENAMSIZ]; int num; struct list_head master_resources; struct list_head slave_resources; @@ -112,7 +112,7 @@ struct vme_bridge { /* Bridge Info - XXX Move to private structure? */ struct device *parent; /* Generic device struct (pdev->dev for PCI) */ - void * base; /* Base Address of device registers */ + void *base; /* Base Address of device registers */ struct device dev[VME_SLOTS_MAX]; /* Device registered with * device model on VME bus @@ -178,8 +178,8 @@ struct vme_bridge { void vme_irq_handler(struct vme_bridge *, int, int); -int vme_register_bridge (struct vme_bridge *); -void vme_unregister_bridge (struct vme_bridge *); +int vme_register_bridge(struct vme_bridge *); +void vme_unregister_bridge(struct vme_bridge *); #endif /* _VME_BRIDGE_H_ */ -- cgit v1.2.3 From 3cb1b8a77402df3091ba7ecaede9b22484bf51b9 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 15 Dec 2009 08:43:09 +0000 Subject: Staging: vme: Remove old structures for implemented features Functionality for master RMW and location monitors has been implemented. Remove the commented out structures from the original codebase. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/vme_bridge.h | 32 -------------------------------- 1 file changed, 32 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/vme_bridge.h b/drivers/staging/vme/vme_bridge.h index a64677e0a31a..92e5614ab910 100644 --- a/drivers/staging/vme/vme_bridge.h +++ b/drivers/staging/vme/vme_bridge.h @@ -229,36 +229,4 @@ struct vmeArbiterCfg { }; typedef struct vmeArbiterCfg vmeArbiterCfg_t; - -/* - * VMEbus RMW Configuration Data - */ -struct vmeRmwCfg { - unsigned int targetAddrU; /* VME Address (Upper) to trigger RMW cycle */ - unsigned int targetAddr; /* VME Address (Lower) to trigger RMW cycle */ - vme_address_t addrSpace; /* VME Address Space */ - int enableMask; /* Bit mask defining the bits of interest */ - int compareData; /* Data to be compared with the data read */ - int swapData; /* Data written to the VMEbus on success */ - int maxAttempts; /* Maximum times to try */ - int numAttempts; /* Number of attempts before success */ - int reserved; /* For future use */ - -}; -typedef struct vmeRmwCfg vmeRmwCfg_t; - -/* - * VMEbus Location Monitor Arg Structure - */ -struct vmeLmCfg { - unsigned int addrU; /* Location Monitor Address upper */ - unsigned int addr; /* Location Monitor Address lower */ - vme_address_t addrSpace; /* Address Space */ - int userAccessType; /* User/Supervisor Access Type */ - int dataAccessType; /* Data/Program Access Type */ - int lmWait; /* Time to wait for access */ - int lmEvents; /* Lm event mask */ - int reserved; /* For future use */ -}; -typedef struct vmeLmCfg vmeLmCfg_t; #endif -- cgit v1.2.3 From 42d4eff70f57eb889678d40d46a2c01ffd29d9a6 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 15 Dec 2009 08:43:15 +0000 Subject: Staging: vme: Allow drivers to co-exist Unable to build both drivers at the same time due to classing variables that should be declared static but aren't. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/bridges/vme_ca91cx42.c | 32 ++++++++++++++++-------------- drivers/staging/vme/bridges/vme_tsi148.c | 20 +++++++++---------- 2 files changed, 27 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index 5799b0927686..470479856054 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c @@ -41,21 +41,23 @@ static void __exit ca91cx42_exit(void); /* Module parameters */ static int geoid; -struct vme_bridge *ca91cx42_bridge; -wait_queue_head_t dma_queue; -wait_queue_head_t iack_queue; -wait_queue_head_t lm_queue; -wait_queue_head_t mbox_queue; - -void (*lm_callback[4])(int); /* Called in interrupt handler, be careful! */ -void *crcsr_kernel; -dma_addr_t crcsr_bus; - -struct mutex vme_rmw; /* Only one RMW cycle at a time */ -struct mutex vme_int; /* - * Only one VME interrupt can be - * generated at a time, provide locking - */ +static struct vme_bridge *ca91cx42_bridge; +static wait_queue_head_t dma_queue; +static wait_queue_head_t iack_queue; +#if 0 +static wait_queue_head_t lm_queue; +#endif +static wait_queue_head_t mbox_queue; + +static void (*lm_callback[4])(int); /* Called in interrupt handler */ +static void *crcsr_kernel; +static dma_addr_t crcsr_bus; + +static struct mutex vme_rmw; /* Only one RMW cycle at a time */ +static struct mutex vme_int; /* + * Only one VME interrupt can be + * generated at a time, provide locking + */ static char driver_name[] = "vme_ca91cx42"; diff --git a/drivers/staging/vme/bridges/vme_tsi148.c b/drivers/staging/vme/bridges/vme_tsi148.c index 324cc389586f..4d19a914ec52 100644 --- a/drivers/staging/vme/bridges/vme_tsi148.c +++ b/drivers/staging/vme/bridges/vme_tsi148.c @@ -62,19 +62,19 @@ int tsi148_generate_irq(int, int); int tsi148_slot_get(void); /* Modue parameter */ -int err_chk = 0; +static int err_chk; static int geoid; /* XXX These should all be in a per device structure */ -struct vme_bridge *tsi148_bridge; -wait_queue_head_t dma_queue[2]; -wait_queue_head_t iack_queue; -void (*lm_callback[4])(int); /* Called in interrupt handler, be careful! */ -void *crcsr_kernel; -dma_addr_t crcsr_bus; -struct vme_master_resource *flush_image; -struct mutex vme_rmw; /* Only one RMW cycle at a time */ -struct mutex vme_int; /* +static struct vme_bridge *tsi148_bridge; +static wait_queue_head_t dma_queue[2]; +static wait_queue_head_t iack_queue; +static void (*lm_callback[4])(int); /* Called in interrupt handler */ +static void *crcsr_kernel; +static dma_addr_t crcsr_bus; +static struct vme_master_resource *flush_image; +static struct mutex vme_rmw; /* Only one RMW cycle at a time */ +static struct mutex vme_int; /* * Only one VME interrupt can be * generated at a time, provide locking */ -- cgit v1.2.3 From 203fe0d2e99598eb960baf2cc4b88b6e794e5a20 Mon Sep 17 00:00:00 2001 From: "kirjanov@gmail.com" Date: Fri, 18 Dec 2009 10:51:07 +0300 Subject: staging: slicoss Convert to netdev_tx_t Convert to netdev_tx_t. Signed-off-by: Denis Kirjanov Signed-off-by: Greg Kroah-Hartman --- drivers/staging/slicoss/slicoss.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/slicoss/slicoss.c b/drivers/staging/slicoss/slicoss.c index 5b191afc1442..a18eeb62f4ef 100644 --- a/drivers/staging/slicoss/slicoss.c +++ b/drivers/staging/slicoss/slicoss.c @@ -101,7 +101,7 @@ static struct net_device_stats *slic_get_stats(struct net_device *dev); static int slic_entry_open(struct net_device *dev); static int slic_entry_halt(struct net_device *dev); static int slic_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); -static int slic_xmit_start(struct sk_buff *skb, struct net_device *dev); +static netdev_tx_t slic_xmit_start(struct sk_buff *skb, struct net_device *dev); static void slic_xmit_fail(struct adapter *adapter, struct sk_buff *skb, void *cmd, u32 skbtype, u32 status); static void slic_config_pci(struct pci_dev *pcidev); @@ -784,7 +784,7 @@ static void slic_xmit_build_request(struct adapter *adapter, #define NORMAL_ETHFRAME 0 -static int slic_xmit_start(struct sk_buff *skb, struct net_device *dev) +static netdev_tx_t slic_xmit_start(struct sk_buff *skb, struct net_device *dev) { struct sliccard *card; struct adapter *adapter = (struct adapter *)netdev_priv(dev); -- cgit v1.2.3 From a71b9978819ce25f911af16fc4d7b96fcdf665d4 Mon Sep 17 00:00:00 2001 From: "kirjanov@gmail.com" Date: Fri, 18 Dec 2009 10:52:45 +0300 Subject: staging: slicoss Check for valid hw address Check for valid hw address. Signed-off-by: Denis Kirjanov Signed-off-by: Greg Kroah-Hartman --- drivers/staging/slicoss/slicoss.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/slicoss/slicoss.c b/drivers/staging/slicoss/slicoss.c index a18eeb62f4ef..9c8eb09de1a6 100644 --- a/drivers/staging/slicoss/slicoss.c +++ b/drivers/staging/slicoss/slicoss.c @@ -2531,6 +2531,9 @@ static int slic_mac_set_address(struct net_device *dev, void *ptr) if (!adapter) return -EBUSY; + if (!is_valid_ether_addr(addr->sa_data)) + return -EINVAL; + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); memcpy(adapter->currmacaddr, addr->sa_data, dev->addr_len); -- cgit v1.2.3 From f8771fa67d63c57e9eedf034939261865edc2065 Mon Sep 17 00:00:00 2001 From: "kirjanov@gmail.com" Date: Fri, 18 Dec 2009 10:54:27 +0300 Subject: staging: slicoss No need type casting when using netdev_priv No need type casting when using netdev_priv. Signed-off-by: Denis Kirjanov Signed-off-by: Greg Kroah-Hartman --- drivers/staging/slicoss/slicoss.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/slicoss/slicoss.c b/drivers/staging/slicoss/slicoss.c index 9c8eb09de1a6..41c440d35b8b 100644 --- a/drivers/staging/slicoss/slicoss.c +++ b/drivers/staging/slicoss/slicoss.c @@ -292,7 +292,7 @@ static void slic_init_adapter(struct net_device *netdev, { ushort index; struct slic_handle *pslic_handle; - struct adapter *adapter = (struct adapter *)netdev_priv(netdev); + struct adapter *adapter = netdev_priv(netdev); /* adapter->pcidev = pcidev;*/ adapter->vendid = pci_tbl_entry->vendor; @@ -484,7 +484,7 @@ err_out_disable_pci: static int slic_entry_open(struct net_device *dev) { - struct adapter *adapter = (struct adapter *) netdev_priv(dev); + struct adapter *adapter = netdev_priv(dev); struct sliccard *card = adapter->card; u32 locked = 0; int status; @@ -534,7 +534,7 @@ static void __devexit slic_entry_remove(struct pci_dev *pcidev) struct net_device *dev = pci_get_drvdata(pcidev); u32 mmio_start = 0; uint mmio_len = 0; - struct adapter *adapter = (struct adapter *) netdev_priv(dev); + struct adapter *adapter = netdev_priv(dev); struct sliccard *card; struct mcast_address *mcaddr, *mlist; @@ -581,7 +581,7 @@ static void __devexit slic_entry_remove(struct pci_dev *pcidev) static int slic_entry_halt(struct net_device *dev) { - struct adapter *adapter = (struct adapter *)netdev_priv(dev); + struct adapter *adapter = netdev_priv(dev); struct sliccard *card = adapter->card; __iomem struct slic_regs *slic_regs = adapter->slic_regs; @@ -624,7 +624,7 @@ static int slic_entry_halt(struct net_device *dev) static int slic_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) { - struct adapter *adapter = (struct adapter *)netdev_priv(dev); + struct adapter *adapter = netdev_priv(dev); struct ethtool_cmd edata; struct ethtool_cmd ecmd; u32 data[7]; @@ -787,7 +787,7 @@ static void slic_xmit_build_request(struct adapter *adapter, static netdev_tx_t slic_xmit_start(struct sk_buff *skb, struct net_device *dev) { struct sliccard *card; - struct adapter *adapter = (struct adapter *)netdev_priv(dev); + struct adapter *adapter = netdev_priv(dev); struct slic_hostcmd *hcmd = NULL; u32 status = 0; u32 skbtype = NORMAL_ETHFRAME; @@ -1071,7 +1071,7 @@ static void slic_xmit_complete(struct adapter *adapter) static irqreturn_t slic_interrupt(int irq, void *dev_id) { struct net_device *dev = (struct net_device *)dev_id; - struct adapter *adapter = (struct adapter *)netdev_priv(dev); + struct adapter *adapter = netdev_priv(dev); u32 isr; if ((adapter->pshmem) && (adapter->pshmem->isr)) { @@ -1229,7 +1229,7 @@ static void slic_init_cleanup(struct adapter *adapter) static struct net_device_stats *slic_get_stats(struct net_device *dev) { - struct adapter *adapter = (struct adapter *)netdev_priv(dev); + struct adapter *adapter = netdev_priv(dev); struct net_device_stats *stats; ASSERT(adapter); @@ -1360,7 +1360,7 @@ static void slic_mcast_set_bit(struct adapter *adapter, char *address) static void slic_mcast_set_list(struct net_device *dev) { - struct adapter *adapter = (struct adapter *)netdev_priv(dev); + struct adapter *adapter = netdev_priv(dev); int status = STATUS_SUCCESS; int i; char *addresses; @@ -2523,7 +2523,7 @@ static bool slic_mac_filter(struct adapter *adapter, static int slic_mac_set_address(struct net_device *dev, void *ptr) { - struct adapter *adapter = (struct adapter *)netdev_priv(dev); + struct adapter *adapter = netdev_priv(dev); struct sockaddr *addr = ptr; if (netif_running(dev)) -- cgit v1.2.3 From d9c057ab0b19e4995884f412b7d15b6c08b1b54e Mon Sep 17 00:00:00 2001 From: "kirjanov@gmail.com" Date: Fri, 18 Dec 2009 10:56:21 +0300 Subject: staging: slicoss No need to check pointer in debugfs_remove() No need to check pointer expicitly since it has been done in debugfs_remove() Signed-off-by: Denis Kirjanov Signed-off-by: Greg Kroah-Hartman --- drivers/staging/slicoss/slicoss.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/slicoss/slicoss.c b/drivers/staging/slicoss/slicoss.c index 41c440d35b8b..96108fdb26c5 100644 --- a/drivers/staging/slicoss/slicoss.c +++ b/drivers/staging/slicoss/slicoss.c @@ -3971,10 +3971,8 @@ static void slic_debug_adapter_create(struct adapter *adapter) static void slic_debug_adapter_destroy(struct adapter *adapter) { - if (adapter->debugfs_entry) { - debugfs_remove(adapter->debugfs_entry); - adapter->debugfs_entry = NULL; - } + debugfs_remove(adapter->debugfs_entry); + adapter->debugfs_entry = NULL; } static void slic_debug_card_create(struct sliccard *card) -- cgit v1.2.3 From 6c7aeb654d0d7f6d3b8de864c60868aa61f1e283 Mon Sep 17 00:00:00 2001 From: "kirjanov@gmail.com" Date: Fri, 18 Dec 2009 10:57:45 +0300 Subject: staging: slicoss Use dev->stats rather than adapter->stats. Use dev->stats rather than adapter->stats. Signed-off-by: Denis Kirjanov Signed-off-by: Greg Kroah-Hartman --- drivers/staging/slicoss/slicoss.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/slicoss/slicoss.c b/drivers/staging/slicoss/slicoss.c index 96108fdb26c5..872717024fd0 100644 --- a/drivers/staging/slicoss/slicoss.c +++ b/drivers/staging/slicoss/slicoss.c @@ -1230,21 +1230,20 @@ static void slic_init_cleanup(struct adapter *adapter) static struct net_device_stats *slic_get_stats(struct net_device *dev) { struct adapter *adapter = netdev_priv(dev); - struct net_device_stats *stats; ASSERT(adapter); - stats = &adapter->stats; - stats->collisions = adapter->slic_stats.iface.xmit_collisions; - stats->rx_errors = adapter->slic_stats.iface.rcv_errors; - stats->tx_errors = adapter->slic_stats.iface.xmt_errors; - stats->rx_missed_errors = adapter->slic_stats.iface.rcv_discards; - stats->tx_heartbeat_errors = 0; - stats->tx_aborted_errors = 0; - stats->tx_window_errors = 0; - stats->tx_fifo_errors = 0; - stats->rx_frame_errors = 0; - stats->rx_length_errors = 0; - return &adapter->stats; + dev->stats.collisions = adapter->slic_stats.iface.xmit_collisions; + dev->stats.rx_errors = adapter->slic_stats.iface.rcv_errors; + dev->stats.tx_errors = adapter->slic_stats.iface.xmt_errors; + dev->stats.rx_missed_errors = adapter->slic_stats.iface.rcv_discards; + dev->stats.tx_heartbeat_errors = 0; + dev->stats.tx_aborted_errors = 0; + dev->stats.tx_window_errors = 0; + dev->stats.tx_fifo_errors = 0; + dev->stats.rx_frame_errors = 0; + dev->stats.rx_length_errors = 0; + + return &dev->stats; } /* -- cgit v1.2.3 From 5d372900aa6b14142cc7d7145cc8be1cb6c0d7b6 Mon Sep 17 00:00:00 2001 From: "kirjanov@gmail.com" Date: Fri, 18 Dec 2009 10:59:04 +0300 Subject: staging: slicoss Use PCI_DEVICE_TABLE. Use PCI_DEVICE_TABLE: defines array as const and puts it into the __devinitconst section. Signed-off-by: Denis Kirjanov Signed-off-by: Greg Kroah-Hartman --- drivers/staging/slicoss/slicoss.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/slicoss/slicoss.c b/drivers/staging/slicoss/slicoss.c index 872717024fd0..4dbd5aa2d980 100644 --- a/drivers/staging/slicoss/slicoss.c +++ b/drivers/staging/slicoss/slicoss.c @@ -194,14 +194,10 @@ MODULE_PARM_DESC(dynamic_intagg, "Dynamic Interrupt Aggregation Setting"); module_param(intagg_delay, int, 0); MODULE_PARM_DESC(intagg_delay, "uSec Interrupt Aggregation Delay"); -static struct pci_device_id slic_pci_tbl[] __devinitdata = { - {PCI_VENDOR_ID_ALACRITECH, - SLIC_1GB_DEVICE_ID, - PCI_ANY_ID, PCI_ANY_ID,}, - {PCI_VENDOR_ID_ALACRITECH, - SLIC_2GB_DEVICE_ID, - PCI_ANY_ID, PCI_ANY_ID,}, - {0,} +static DEFINE_PCI_DEVICE_TABLE(slic_pci_tbl) = { + { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH, SLIC_1GB_DEVICE_ID) }, + { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH, SLIC_2GB_DEVICE_ID) }, + { 0 } }; MODULE_DEVICE_TABLE(pci, slic_pci_tbl); -- cgit v1.2.3 From 30ae835f89cac13156fdef84412870f3179f3f22 Mon Sep 17 00:00:00 2001 From: "kirjanov@gmail.com" Date: Fri, 18 Dec 2009 11:00:19 +0300 Subject: staging: slicoss Use compare_ether_addr. Use compare_ether_addr. Signed-off-by: Denis Kirjanov Signed-off-by: Greg Kroah-Hartman --- drivers/staging/slicoss/slic.h | 9 --------- drivers/staging/slicoss/slicoss.c | 11 +++-------- 2 files changed, 3 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/slicoss/slic.h b/drivers/staging/slicoss/slic.h index ccf7625b8bb3..eb3a619c6a94 100644 --- a/drivers/staging/slicoss/slic.h +++ b/drivers/staging/slicoss/slic.h @@ -527,15 +527,6 @@ struct adapter { (largestat) += ((newstat) - (oldstat)); \ } -#define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result) \ -{ \ - _Result = true; \ - if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB)) \ - _Result = false; \ - if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4]))) \ - _Result = false; \ -} - #if defined(CONFIG_X86_64) || defined(CONFIG_IA64) #define SLIC_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & \ 0x00000000FFFFFFFF) diff --git a/drivers/staging/slicoss/slicoss.c b/drivers/staging/slicoss/slicoss.c index 4dbd5aa2d980..aefe3fef7728 100644 --- a/drivers/staging/slicoss/slicoss.c +++ b/drivers/staging/slicoss/slicoss.c @@ -1249,13 +1249,11 @@ static struct net_device_stats *slic_get_stats(struct net_device *dev) static int slic_mcast_add_list(struct adapter *adapter, char *address) { struct mcast_address *mcaddr, *mlist; - bool equaladdr; /* Check to see if it already exists */ mlist = adapter->mcastaddrs; while (mlist) { - ETHER_EQ_ADDR(mlist->address, address, equaladdr); - if (equaladdr) + if (!compare_ether_addr(mlist->address, address)) return STATUS_SUCCESS; mlist = mlist->next; } @@ -2469,7 +2467,6 @@ static bool slic_mac_filter(struct adapter *adapter, u32 opts = adapter->macopts; u32 *dhost4 = (u32 *)ðer_frame->ether_dhost[0]; u16 *dhost2 = (u16 *)ðer_frame->ether_dhost[4]; - bool equaladdr; if (opts & MAC_PROMISC) return true; @@ -2493,10 +2490,8 @@ static bool slic_mac_filter(struct adapter *adapter, struct mcast_address *mcaddr = adapter->mcastaddrs; while (mcaddr) { - ETHER_EQ_ADDR(mcaddr->address, - ether_frame->ether_dhost, - equaladdr); - if (equaladdr) { + if (!compare_ether_addr(mcaddr->address, + ether_frame->ether_dhost)) { adapter->rcv_multicasts++; adapter->stats.multicast++; return true; -- cgit v1.2.3 From a5c252411f16dce1f9586090ffa8210273a4c8fb Mon Sep 17 00:00:00 2001 From: "kirjanov@gmail.com" Date: Fri, 18 Dec 2009 11:02:09 +0300 Subject: staging: slicoss Use pci_set_consistent_dma_mask. Use pci_set_consistent_dma_mask() in the case of 64-bit consistent allocations. Signed-off-by: Denis Kirjanov Signed-off-by: Greg Kroah-Hartman --- drivers/staging/slicoss/slicoss.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/slicoss/slicoss.c b/drivers/staging/slicoss/slicoss.c index aefe3fef7728..09a9d759c612 100644 --- a/drivers/staging/slicoss/slicoss.c +++ b/drivers/staging/slicoss/slicoss.c @@ -366,6 +366,7 @@ static int __devinit slic_entry_probe(struct pci_dev *pcidev, ulong mmio_start = 0; ulong mmio_len = 0; struct sliccard *card = NULL; + int pci_using_dac = 0; slic_global.dynamic_intagg = dynamic_intagg; @@ -379,16 +380,26 @@ static int __devinit slic_entry_probe(struct pci_dev *pcidev, printk(KERN_DEBUG "%s\n", slic_proc_version); } - err = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64)); - if (err) { - err = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32)); - if (err) + if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) { + pci_using_dac = 1; + if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) { + dev_err(&pcidev->dev, "unable to obtain 64-bit DMA for " + "consistent allocations\n"); goto err_out_disable_pci; + } + } else if (pci_set_dma_mask(pcidev, DMA_BIT_MASK(32))) { + pci_using_dac = 0; + pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32)); + } else { + dev_err(&pcidev->dev, "no usable DMA configuration\n"); + goto err_out_disable_pci; } err = pci_request_regions(pcidev, DRV_NAME); - if (err) + if (err) { + dev_err(&pcidev->dev, "can't obtain PCI resources\n"); goto err_out_disable_pci; + } pci_set_master(pcidev); @@ -404,6 +415,8 @@ static int __devinit slic_entry_probe(struct pci_dev *pcidev, adapter = netdev_priv(netdev); adapter->netdev = netdev; adapter->pcidev = pcidev; + if (pci_using_dac) + netdev->features |= NETIF_F_HIGHDMA; mmio_start = pci_resource_start(pcidev, 0); mmio_len = pci_resource_len(pcidev, 0); -- cgit v1.2.3 From 0ee9f67c4028500a4348e8bc87ee7ec1139b8259 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Sun, 6 Dec 2009 11:34:52 -0800 Subject: Staging: rtl8187x: Use %pM for mac address output Uncompiled. Doesn't currently build anyway. Converted MAC_FMT to %pM Converted some %02x%02x%02x%02x%02x%02x to %pm Converted MAC_ARG to direct use Removed MAC_FMT and MAC_ARG macros Signed-off-by: Joe Perches Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8187se/ieee80211/ieee80211.h | 4 -- .../rtl8187se/ieee80211/ieee80211_crypt_ccmp.c | 21 ++++----- .../rtl8187se/ieee80211/ieee80211_crypt_tkip.c | 20 ++++----- drivers/staging/rtl8187se/ieee80211/ieee80211_rx.c | 48 ++++++++++---------- .../rtl8187se/ieee80211/ieee80211_softmac.c | 2 +- drivers/staging/rtl8187se/ieee80211/ieee80211_tx.c | 6 +-- drivers/staging/rtl8187se/ieee80211/ieee80211_wx.c | 4 +- drivers/staging/rtl8192e/ieee80211.h | 3 -- drivers/staging/rtl8192e/ieee80211/ieee80211.h | 3 -- .../rtl8192e/ieee80211/ieee80211_crypt_ccmp.c | 18 ++++---- .../rtl8192e/ieee80211/ieee80211_crypt_tkip.c | 27 +++++------ drivers/staging/rtl8192e/ieee80211/ieee80211_rx.c | 52 +++++++++++----------- .../staging/rtl8192e/ieee80211/ieee80211_softmac.c | 2 +- drivers/staging/rtl8192e/ieee80211/ieee80211_tx.c | 4 +- drivers/staging/rtl8192e/ieee80211/ieee80211_wx.c | 4 +- .../staging/rtl8192e/ieee80211/rtl819x_BAProc.c | 6 +-- .../staging/rtl8192e/ieee80211/rtl819x_TSProc.c | 6 +-- drivers/staging/rtl8192e/r8192E_core.c | 2 +- drivers/staging/rtl8192su/ieee80211/ieee80211.h | 4 -- .../rtl8192su/ieee80211/ieee80211_crypt_ccmp.c | 21 ++++----- .../rtl8192su/ieee80211/ieee80211_crypt_tkip.c | 20 ++++----- drivers/staging/rtl8192su/ieee80211/ieee80211_rx.c | 48 ++++++++++---------- .../rtl8192su/ieee80211/ieee80211_softmac.c | 2 +- drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c | 4 +- drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c | 4 +- .../staging/rtl8192su/ieee80211/rtl819x_BAProc.c | 6 +-- .../staging/rtl8192su/ieee80211/rtl819x_TSProc.c | 6 +-- drivers/staging/rtl8192su/r8192U_core.c | 2 +- drivers/staging/rtl8192su/r8192U_dm.c | 2 +- drivers/staging/rtl8192u/ieee80211.h | 3 -- drivers/staging/rtl8192u/ieee80211/ieee80211.h | 3 -- .../rtl8192u/ieee80211/ieee80211_crypt_ccmp.c | 21 ++++----- .../rtl8192u/ieee80211/ieee80211_crypt_tkip.c | 20 ++++----- drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c | 48 ++++++++++---------- .../staging/rtl8192u/ieee80211/ieee80211_softmac.c | 2 +- drivers/staging/rtl8192u/ieee80211/ieee80211_tx.c | 4 +- drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c | 4 +- .../staging/rtl8192u/ieee80211/rtl819x_BAProc.c | 6 +-- .../staging/rtl8192u/ieee80211/rtl819x_TSProc.c | 6 +-- drivers/staging/rtl8192u/r8192U_core.c | 4 +- 40 files changed, 221 insertions(+), 251 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8187se/ieee80211/ieee80211.h b/drivers/staging/rtl8187se/ieee80211/ieee80211.h index 0d490c164db6..04a48e7e76e6 100644 --- a/drivers/staging/rtl8187se/ieee80211/ieee80211.h +++ b/drivers/staging/rtl8187se/ieee80211/ieee80211.h @@ -161,10 +161,6 @@ do { if (ieee80211_debug_level & (level)) \ #define IEEE80211_DEBUG(level, fmt, args...) do {} while (0) #endif /* CONFIG_IEEE80211_DEBUG */ -#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" -#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], \ - ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5] - /* * To use the debug system; * diff --git a/drivers/staging/rtl8187se/ieee80211/ieee80211_crypt_ccmp.c b/drivers/staging/rtl8187se/ieee80211/ieee80211_crypt_ccmp.c index 172e8f3ae6c1..40f1b99faad2 100644 --- a/drivers/staging/rtl8187se/ieee80211/ieee80211_crypt_ccmp.c +++ b/drivers/staging/rtl8187se/ieee80211/ieee80211_crypt_ccmp.c @@ -285,7 +285,7 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (!(keyidx & (1 << 5))) { if (net_ratelimit()) { printk(KERN_DEBUG "CCMP: received packet without ExtIV" - " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2)); + " flag from %pM\n", hdr->addr2); } key->dot11RSNAStatsCCMPFormatErrors++; return -2; @@ -298,9 +298,9 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) } if (!key->key_set) { if (net_ratelimit()) { - printk(KERN_DEBUG "CCMP: received packet from " MAC_FMT + printk(KERN_DEBUG "CCMP: received packet from %pM" " with keyid=%d that does not have a configured" - " key\n", MAC_ARG(hdr->addr2), keyidx); + " key\n", hdr->addr2, keyidx); } return -3; } @@ -315,11 +315,9 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (memcmp(pn, key->rx_pn, CCMP_PN_LEN) <= 0) { if (net_ratelimit()) { - printk(KERN_DEBUG "CCMP: replay detected: STA=" MAC_FMT - " previous PN %02x%02x%02x%02x%02x%02x " - "received PN %02x%02x%02x%02x%02x%02x\n", - MAC_ARG(hdr->addr2), MAC_ARG(key->rx_pn), - MAC_ARG(pn)); + printk(KERN_DEBUG "CCMP: replay detected: STA=%pM" + " previous PN %pm received PN %pm\n", + hdr->addr2, key->rx_pn, pn); } key->dot11RSNAStatsCCMPReplays++; return -4; @@ -347,7 +345,7 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (memcmp(mic, a, CCMP_MIC_LEN) != 0) { if (net_ratelimit()) { printk(KERN_DEBUG "CCMP: decrypt failed: STA=" - MAC_FMT "\n", MAC_ARG(hdr->addr2)); + "%pM\n", hdr->addr2); } key->dot11RSNAStatsCCMPDecryptErrors++; return -5; @@ -423,11 +421,10 @@ static char * ieee80211_ccmp_print_stats(char *p, void *priv) { struct ieee80211_ccmp_data *ccmp = priv; p += sprintf(p, "key[%d] alg=CCMP key_set=%d " - "tx_pn=%02x%02x%02x%02x%02x%02x " - "rx_pn=%02x%02x%02x%02x%02x%02x " + "tx_pn=%pm rx_pn=%pm " "format_errors=%d replays=%d decrypt_errors=%d\n", ccmp->key_idx, ccmp->key_set, - MAC_ARG(ccmp->tx_pn), MAC_ARG(ccmp->rx_pn), + ccmp->tx_pn, ccmp->rx_pn, ccmp->dot11RSNAStatsCCMPFormatErrors, ccmp->dot11RSNAStatsCCMPReplays, ccmp->dot11RSNAStatsCCMPDecryptErrors); diff --git a/drivers/staging/rtl8187se/ieee80211/ieee80211_crypt_tkip.c b/drivers/staging/rtl8187se/ieee80211/ieee80211_crypt_tkip.c index e6d8385e1d88..a5254111d9a1 100644 --- a/drivers/staging/rtl8187se/ieee80211/ieee80211_crypt_tkip.c +++ b/drivers/staging/rtl8187se/ieee80211/ieee80211_crypt_tkip.c @@ -385,7 +385,7 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (!(keyidx & (1 << 5))) { if (net_ratelimit()) { printk(KERN_DEBUG "TKIP: received packet without ExtIV" - " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2)); + " flag from %pM\n", hdr->addr2); } return -2; } @@ -397,9 +397,9 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) } if (!tkey->key_set) { if (net_ratelimit()) { - printk(KERN_DEBUG "TKIP: received packet from " MAC_FMT + printk(KERN_DEBUG "TKIP: received packet from %pM" " with keyid=%d that does not have a configured" - " key\n", MAC_ARG(hdr->addr2), keyidx); + " key\n", hdr->addr2, keyidx); } return -3; } @@ -410,9 +410,9 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (iv32 < tkey->rx_iv32 || (iv32 == tkey->rx_iv32 && iv16 <= tkey->rx_iv16)) { if (net_ratelimit()) { - printk(KERN_DEBUG "TKIP: replay detected: STA=" MAC_FMT + printk(KERN_DEBUG "TKIP: replay detected: STA=%pM" " previous TSC %08x%04x received TSC " - "%08x%04x\n", MAC_ARG(hdr->addr2), + "%08x%04x\n", hdr->addr2, tkey->rx_iv32, tkey->rx_iv16, iv32, iv16); } tkey->dot11RSNAStatsTKIPReplays++; @@ -431,8 +431,8 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (crypto_blkcipher_decrypt(&desc, &sg, &sg, plen + 4)) { if (net_ratelimit()) { printk(KERN_DEBUG ": TKIP: failed to decrypt " - "received packet from " MAC_FMT "\n", - MAC_ARG(hdr->addr2)); + "received packet from %pM\n", + hdr->addr2); } return -7; } @@ -450,7 +450,7 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) } if (net_ratelimit()) { printk(KERN_DEBUG "TKIP: ICV error detected: STA=" - MAC_FMT "\n", MAC_ARG(hdr->addr2)); + "%pM\n", hdr->addr2); } tkey->dot11RSNAStatsTKIPICVErrors++; return -5; @@ -604,8 +604,8 @@ static int ieee80211_michael_mic_verify(struct sk_buff *skb, int keyidx, struct ieee80211_hdr_4addr *hdr; hdr = (struct ieee80211_hdr_4addr *)skb->data; printk(KERN_DEBUG "%s: Michael MIC verification failed for " - "MSDU from " MAC_FMT " keyidx=%d\n", - skb->dev ? skb->dev->name : "N/A", MAC_ARG(hdr->addr2), + "MSDU from %pM keyidx=%d\n", + skb->dev ? skb->dev->name : "N/A", hdr->addr2, keyidx); if (skb->dev) ieee80211_michael_mic_failure(skb->dev, hdr, keyidx); diff --git a/drivers/staging/rtl8187se/ieee80211/ieee80211_rx.c b/drivers/staging/rtl8187se/ieee80211/ieee80211_rx.c index 9128c181bc7d..2b7080cc2c05 100644 --- a/drivers/staging/rtl8187se/ieee80211/ieee80211_rx.c +++ b/drivers/staging/rtl8187se/ieee80211/ieee80211_rx.c @@ -311,8 +311,8 @@ ieee80211_rx_frame_decrypt(struct ieee80211_device* ieee, struct sk_buff *skb, strcmp(crypt->ops->name, "TKIP") == 0) { if (net_ratelimit()) { printk(KERN_DEBUG "%s: TKIP countermeasures: dropped " - "received packet from " MAC_FMT "\n", - ieee->dev->name, MAC_ARG(hdr->addr2)); + "received packet from %pM\n", + ieee->dev->name, hdr->addr2); } return -1; } @@ -323,8 +323,8 @@ ieee80211_rx_frame_decrypt(struct ieee80211_device* ieee, struct sk_buff *skb, atomic_dec(&crypt->refcnt); if (res < 0) { IEEE80211_DEBUG_DROP( - "decryption failed (SA=" MAC_FMT - ") res=%d\n", MAC_ARG(hdr->addr2), res); + "decryption failed (SA=%pM" + ") res=%d\n", hdr->addr2, res); if (res == -2) IEEE80211_DEBUG_DROP("Decryption failed ICV " "mismatch (key %d)\n", @@ -356,8 +356,8 @@ ieee80211_rx_frame_decrypt_msdu(struct ieee80211_device* ieee, struct sk_buff *s atomic_dec(&crypt->refcnt); if (res < 0) { printk(KERN_DEBUG "%s: MSDU decryption/MIC verification failed" - " (SA=" MAC_FMT " keyidx=%d)\n", - ieee->dev->name, MAC_ARG(hdr->addr2), keyidx); + " (SA=%pM keyidx=%d)\n", + ieee->dev->name, hdr->addr2, keyidx); return -1; } @@ -550,8 +550,8 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, * frames silently instead of filling system log with * these reports. */ IEEE80211_DEBUG_DROP("Decryption failed (not set)" - " (SA=" MAC_FMT ")\n", - MAC_ARG(hdr->addr2)); + " (SA=%pM)\n", + hdr->addr2); ieee->ieee_stats.rx_discards_undecryptable++; goto rx_dropped; } @@ -709,8 +709,8 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, } else { IEEE80211_DEBUG_DROP( "encryption configured, but RX " - "frame not encrypted (SA=" MAC_FMT ")\n", - MAC_ARG(hdr->addr2)); + "frame not encrypted (SA=%pM)\n", + hdr->addr2); goto rx_dropped; } } @@ -729,9 +729,9 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, !ieee80211_is_eapol_frame(ieee, skb, hdrlen)) { IEEE80211_DEBUG_DROP( "dropped unencrypted RX data " - "frame from " MAC_FMT + "frame from %pM" " (drop_unencrypted=1)\n", - MAC_ARG(hdr->addr2)); + hdr->addr2); goto rx_dropped; } /* @@ -1196,11 +1196,11 @@ inline int ieee80211_network_init( } if (network->mode == 0) { - IEEE80211_DEBUG_SCAN("Filtered out '%s (" MAC_FMT ")' " + IEEE80211_DEBUG_SCAN("Filtered out '%s (%pM)' " "network.\n", escape_essid(network->ssid, network->ssid_len), - MAC_ARG(network->bssid)); + network->bssid); return 1; } @@ -1341,9 +1341,9 @@ inline void ieee80211_process_probe_response( memset(&network, 0, sizeof(struct ieee80211_network)); IEEE80211_DEBUG_SCAN( - "'%s' (" MAC_FMT "): %c%c%c%c %c%c%c%c-%c%c%c%c %c%c%c%c\n", + "'%s' (%pM): %c%c%c%c %c%c%c%c-%c%c%c%c %c%c%c%c\n", escape_essid(info_element->data, info_element->len), - MAC_ARG(beacon->header.addr3), + beacon->header.addr3, (beacon->capability & (1<<0xf)) ? '1' : '0', (beacon->capability & (1<<0xe)) ? '1' : '0', (beacon->capability & (1<<0xd)) ? '1' : '0', @@ -1362,10 +1362,10 @@ inline void ieee80211_process_probe_response( (beacon->capability & (1<<0x0)) ? '1' : '0'); if (ieee80211_network_init(ieee, beacon, &network, stats)) { - IEEE80211_DEBUG_SCAN("Dropped '%s' (" MAC_FMT ") via %s.\n", + IEEE80211_DEBUG_SCAN("Dropped '%s' (%pM) via %s.\n", escape_essid(info_element->data, info_element->len), - MAC_ARG(beacon->header.addr3), + beacon->header.addr3, WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP ? "PROBE RESPONSE" : "BEACON"); @@ -1464,11 +1464,11 @@ inline void ieee80211_process_probe_response( /* If there are no more slots, expire the oldest */ list_del(&oldest->list); target = oldest; - IEEE80211_DEBUG_SCAN("Expired '%s' (" MAC_FMT ") from " + IEEE80211_DEBUG_SCAN("Expired '%s' (%pM) from " "network list.\n", escape_essid(target->ssid, target->ssid_len), - MAC_ARG(target->bssid)); + target->bssid); } else { /* Otherwise just pull from the free list */ target = list_entry(ieee->network_free_list.next, @@ -1478,10 +1478,10 @@ inline void ieee80211_process_probe_response( #ifdef CONFIG_IEEE80211_DEBUG - IEEE80211_DEBUG_SCAN("Adding '%s' (" MAC_FMT ") via %s.\n", + IEEE80211_DEBUG_SCAN("Adding '%s' (%pM) via %s.\n", escape_essid(network.ssid, network.ssid_len), - MAC_ARG(network.bssid), + network.bssid, WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP ? "PROBE RESPONSE" : "BEACON"); @@ -1492,10 +1492,10 @@ inline void ieee80211_process_probe_response( if(ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) ieee80211_softmac_new_net(ieee,&network); } else { - IEEE80211_DEBUG_SCAN("Updating '%s' (" MAC_FMT ") via %s.\n", + IEEE80211_DEBUG_SCAN("Updating '%s' (%pM) via %s.\n", escape_essid(target->ssid, target->ssid_len), - MAC_ARG(target->bssid), + target->bssid, WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP ? "PROBE RESPONSE" : "BEACON"); diff --git a/drivers/staging/rtl8187se/ieee80211/ieee80211_softmac.c b/drivers/staging/rtl8187se/ieee80211/ieee80211_softmac.c index c7c645af0ebb..e8cfcb85727e 100644 --- a/drivers/staging/rtl8187se/ieee80211/ieee80211_softmac.c +++ b/drivers/staging/rtl8187se/ieee80211/ieee80211_softmac.c @@ -1573,7 +1573,7 @@ ieee80211_rx_assoc_rq(struct ieee80211_device *ieee, struct sk_buff *skb) ieee80211_resp_to_assoc_rq(ieee, dest); } - printk(KERN_INFO"New client associated: "MAC_FMT"\n", MAC_ARG(dest)); + printk(KERN_INFO"New client associated: %pM\n", dest); } diff --git a/drivers/staging/rtl8187se/ieee80211/ieee80211_tx.c b/drivers/staging/rtl8187se/ieee80211/ieee80211_tx.c index 69bd02164b0c..6cb31e1760ac 100644 --- a/drivers/staging/rtl8187se/ieee80211/ieee80211_tx.c +++ b/drivers/staging/rtl8187se/ieee80211/ieee80211_tx.c @@ -198,8 +198,8 @@ int ieee80211_encrypt_fragment( header = (struct ieee80211_hdr_4addr *)frag->data; if (net_ratelimit()) { printk(KERN_DEBUG "%s: TKIP countermeasures: dropped " - "TX packet to " MAC_FMT "\n", - ieee->dev->name, MAC_ARG(header->addr1)); + "TX packet to %pM\n", + ieee->dev->name, header->addr1); } return -1; } @@ -407,7 +407,7 @@ int ieee80211_rtl_xmit(struct sk_buff *skb, memcpy(&header.addr2, src, ETH_ALEN); memcpy(&header.addr3, ieee->current_network.bssid, ETH_ALEN); } - // printk(KERN_WARNING "essid MAC address is "MAC_FMT, MAC_ARG(&header.addr1)); + // printk(KERN_WARNING "essid MAC address is %pM", &header.addr1); header.frame_ctl = cpu_to_le16(fc); //hdr_len = IEEE80211_3ADDR_LEN; diff --git a/drivers/staging/rtl8187se/ieee80211/ieee80211_wx.c b/drivers/staging/rtl8187se/ieee80211/ieee80211_wx.c index 6aad48fe2e18..acd1077e6396 100644 --- a/drivers/staging/rtl8187se/ieee80211/ieee80211_wx.c +++ b/drivers/staging/rtl8187se/ieee80211/ieee80211_wx.c @@ -234,10 +234,10 @@ int ieee80211_wx_get_scan(struct ieee80211_device *ieee, else IEEE80211_DEBUG_SCAN( "Not showing network '%s (" - MAC_FMT ")' due to age (%lums).\n", + "%pM)' due to age (%lums).\n", escape_essid(network->ssid, network->ssid_len), - MAC_ARG(network->bssid), + network->bssid, (jiffies - network->last_scanned) / (HZ / 100)); } } diff --git a/drivers/staging/rtl8192e/ieee80211.h b/drivers/staging/rtl8192e/ieee80211.h index 3ba9e9e90bda..c39249eb54b5 100644 --- a/drivers/staging/rtl8192e/ieee80211.h +++ b/drivers/staging/rtl8192e/ieee80211.h @@ -547,9 +547,6 @@ do { if (ieee80211_debug_level & (level)) \ /* debug macros not dependent on CONFIG_IEEE80211_DEBUG */ -#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" -#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] - /* * To use the debug system; * diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211.h b/drivers/staging/rtl8192e/ieee80211/ieee80211.h index aa76390487bb..9d91ab9fc04b 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211.h +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211.h @@ -615,9 +615,6 @@ do { if (ieee80211_debug_level & (level)) \ /* debug macros not dependent on CONFIG_IEEE80211_DEBUG */ -#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" -#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] - /* * To use the debug system; * diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c index ab871b360b5d..609c289541d4 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c @@ -331,7 +331,7 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (!(keyidx & (1 << 5))) { if (net_ratelimit()) { printk(KERN_DEBUG "CCMP: received packet without ExtIV" - " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2)); + " flag from %pM\n", hdr->addr2); } key->dot11RSNAStatsCCMPFormatErrors++; return -2; @@ -344,9 +344,9 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) } if (!key->key_set) { if (net_ratelimit()) { - printk(KERN_DEBUG "CCMP: received packet from " MAC_FMT + printk(KERN_DEBUG "CCMP: received packet from %pM" " with keyid=%d that does not have a configured" - " key\n", MAC_ARG(hdr->addr2), keyidx); + " key\n", hdr->addr2, keyidx); } return -3; } @@ -361,11 +361,9 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (memcmp(pn, key->rx_pn, CCMP_PN_LEN) <= 0) { if (net_ratelimit()) { - printk(KERN_DEBUG "CCMP: replay detected: STA=" MAC_FMT - " previous PN %02x%02x%02x%02x%02x%02x " - "received PN %02x%02x%02x%02x%02x%02x\n", - MAC_ARG(hdr->addr2), MAC_ARG(key->rx_pn), - MAC_ARG(pn)); + printk(KERN_DEBUG "CCMP: replay detected: STA=%pM" + " previous PN %pm received PN %pm\n", + hdr->addr2, key->rx_pn, pn); } key->dot11RSNAStatsCCMPReplays++; return -4; @@ -402,7 +400,7 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (memcmp(mic, a, CCMP_MIC_LEN) != 0) { if (net_ratelimit()) { printk(KERN_DEBUG "CCMP: decrypt failed: STA=" - MAC_FMT "\n", MAC_ARG(hdr->addr2)); + "%pM\n", hdr->addr2); } key->dot11RSNAStatsCCMPDecryptErrors++; return -5; @@ -482,7 +480,7 @@ static char * ieee80211_ccmp_print_stats(char *p, void *priv) "rx_pn=%02x%02x%02x%02x%02x%02x " "format_errors=%d replays=%d decrypt_errors=%d\n", ccmp->key_idx, ccmp->key_set, - MAC_ARG(ccmp->tx_pn), MAC_ARG(ccmp->rx_pn), + ccmp->tx_pn, ccmp->rx_pn, ccmp->dot11RSNAStatsCCMPFormatErrors, ccmp->dot11RSNAStatsCCMPReplays, ccmp->dot11RSNAStatsCCMPDecryptErrors); diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_tkip.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_tkip.c index 7a1797e6cbec..7056d932057b 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_tkip.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_tkip.c @@ -520,7 +520,7 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (!(keyidx & (1 << 5))) { if (net_ratelimit()) { printk(KERN_DEBUG "TKIP: received packet without ExtIV" - " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2)); + " flag from %pM\n", hdr->addr2); } return -2; } @@ -532,9 +532,9 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) } if (!tkey->key_set) { if (net_ratelimit()) { - printk(KERN_DEBUG "TKIP: received packet from " MAC_FMT + printk(KERN_DEBUG "TKIP: received packet from %pM" " with keyid=%d that does not have a configured" - " key\n", MAC_ARG(hdr->addr2), keyidx); + " key\n", hdr->addr2, keyidx); } return -3; } @@ -547,9 +547,9 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (iv32 < tkey->rx_iv32 || (iv32 == tkey->rx_iv32 && iv16 <= tkey->rx_iv16)) { if (net_ratelimit()) { - printk(KERN_DEBUG "TKIP: replay detected: STA=" MAC_FMT + printk(KERN_DEBUG "TKIP: replay detected: STA=%pM" " previous TSC %08x%04x received TSC " - "%08x%04x\n", MAC_ARG(hdr->addr2), + "%08x%04x\n", hdr->addr2, tkey->rx_iv32, tkey->rx_iv16, iv32, iv16); } tkey->dot11RSNAStatsTKIPReplays++; @@ -582,8 +582,8 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (crypto_blkcipher_decrypt(&desc, &sg, &sg, plen + 4)) { if (net_ratelimit()) { printk(KERN_DEBUG ": TKIP: failed to decrypt " - "received packet from " MAC_FMT "\n", - MAC_ARG(hdr->addr2)); + "received packet from %pM\n", + hdr->addr2); } return -7; } @@ -606,8 +606,9 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) tkey->rx_phase1_done = 0; } if (net_ratelimit()) { - printk(KERN_DEBUG "TKIP: ICV error detected: STA=" - MAC_FMT "\n", MAC_ARG(hdr->addr2)); + printk(KERN_DEBUG + "TKIP: ICV error detected: STA=%pM\n", + hdr->addr2); } tkey->dot11RSNAStatsTKIPICVErrors++; return -5; @@ -816,8 +817,8 @@ static void ieee80211_michael_mic_failure(struct net_device *dev, /* TODO: needed parameters: count, keyid, key type, TSC */ sprintf(buf, "MLME-MICHAELMICFAILURE.indication(keyid=%d %scast addr=" - MAC_FMT ")", keyidx, hdr->addr1[0] & 0x01 ? "broad" : "uni", - MAC_ARG(hdr->addr2)); + "%pM)", keyidx, hdr->addr1[0] & 0x01 ? "broad" : "uni", + hdr->addr2); memset(&wrqu, 0, sizeof(wrqu)); wrqu.data.length = strlen(buf); wireless_send_event(dev, IWEVCUSTOM, &wrqu, buf); @@ -862,8 +863,8 @@ static int ieee80211_michael_mic_verify(struct sk_buff *skb, int keyidx, struct ieee80211_hdr_4addr *hdr; hdr = (struct ieee80211_hdr_4addr *) skb->data; printk(KERN_DEBUG "%s: Michael MIC verification failed for " - "MSDU from " MAC_FMT " keyidx=%d\n", - skb->dev ? skb->dev->name : "N/A", MAC_ARG(hdr->addr2), + "MSDU from %pM keyidx=%d\n", + skb->dev ? skb->dev->name : "N/A", hdr->addr2, keyidx); if (skb->dev) ieee80211_michael_mic_failure(skb->dev, hdr, keyidx); diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_rx.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_rx.c index 06d91715143c..7a500ac37acb 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_rx.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_rx.c @@ -366,8 +366,8 @@ ieee80211_rx_frame_decrypt(struct ieee80211_device* ieee, struct sk_buff *skb, strcmp(crypt->ops->name, "TKIP") == 0) { if (net_ratelimit()) { printk(KERN_DEBUG "%s: TKIP countermeasures: dropped " - "received packet from " MAC_FMT "\n", - ieee->dev->name, MAC_ARG(hdr->addr2)); + "received packet from %pM\n", + ieee->dev->name, hdr->addr2); } return -1; } @@ -378,8 +378,8 @@ ieee80211_rx_frame_decrypt(struct ieee80211_device* ieee, struct sk_buff *skb, atomic_dec(&crypt->refcnt); if (res < 0) { IEEE80211_DEBUG_DROP( - "decryption failed (SA=" MAC_FMT - ") res=%d\n", MAC_ARG(hdr->addr2), res); + "decryption failed (SA=%pM" + ") res=%d\n", hdr->addr2, res); if (res == -2) IEEE80211_DEBUG_DROP("Decryption failed ICV " "mismatch (key %d)\n", @@ -416,8 +416,8 @@ ieee80211_rx_frame_decrypt_msdu(struct ieee80211_device* ieee, struct sk_buff *s atomic_dec(&crypt->refcnt); if (res < 0) { printk(KERN_DEBUG "%s: MSDU decryption/MIC verification failed" - " (SA=" MAC_FMT " keyidx=%d)\n", - ieee->dev->name, MAC_ARG(hdr->addr2), keyidx); + " (SA=%pM keyidx=%d)\n", + ieee->dev->name, hdr->addr2, keyidx); return -1; } @@ -1045,8 +1045,8 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, * frames silently instead of filling system log with * these reports. */ IEEE80211_DEBUG_DROP("Decryption failed (not set)" - " (SA=" MAC_FMT ")\n", - MAC_ARG(hdr->addr2)); + " (SA=%pM)\n", + hdr->addr2); ieee->ieee_stats.rx_discards_undecryptable++; goto rx_dropped; } @@ -1114,8 +1114,8 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, (keyidx = hostap_rx_frame_decrypt(ieee, skb, crypt)) < 0) { printk(KERN_DEBUG "%s: failed to decrypt mgmt::auth " - "from " MAC_FMT "\n", dev->name, - MAC_ARG(hdr->addr2)); + "from %pM\n", dev->name, + hdr->addr2); /* TODO: could inform hostapd about this so that it * could send auth failure report */ goto rx_dropped; @@ -1311,8 +1311,8 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, } else { IEEE80211_DEBUG_DROP( "encryption configured, but RX " - "frame not encrypted (SA=" MAC_FMT ")\n", - MAC_ARG(hdr->addr2)); + "frame not encrypted (SA=%pM)\n", + hdr->addr2); goto rx_dropped; } } @@ -1331,9 +1331,9 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, !ieee80211_is_eapol_frame(ieee, skb, hdrlen)) { IEEE80211_DEBUG_DROP( "dropped unencrypted RX data " - "frame from " MAC_FMT + "frame from %pM" " (drop_unencrypted=1)\n", - MAC_ARG(hdr->addr2)); + hdr->addr2); goto rx_dropped; } /* @@ -2369,11 +2369,11 @@ static inline int ieee80211_network_init( } if (network->mode == 0) { - IEEE80211_DEBUG_SCAN("Filtered out '%s (" MAC_FMT ")' " + IEEE80211_DEBUG_SCAN("Filtered out '%s (%pM)' " "network.\n", escape_essid(network->ssid, network->ssid_len), - MAC_ARG(network->bssid)); + network->bssid); return 1; } @@ -2557,9 +2557,9 @@ static inline void ieee80211_process_probe_response( memset(&network, 0, sizeof(struct ieee80211_network)); IEEE80211_DEBUG_SCAN( - "'%s' (" MAC_FMT "): %c%c%c%c %c%c%c%c-%c%c%c%c %c%c%c%c\n", + "'%s' (%pM): %c%c%c%c %c%c%c%c-%c%c%c%c %c%c%c%c\n", escape_essid(info_element->data, info_element->len), - MAC_ARG(beacon->header.addr3), + beacon->header.addr3, (beacon->capability & (1<<0xf)) ? '1' : '0', (beacon->capability & (1<<0xe)) ? '1' : '0', (beacon->capability & (1<<0xd)) ? '1' : '0', @@ -2578,10 +2578,10 @@ static inline void ieee80211_process_probe_response( (beacon->capability & (1<<0x0)) ? '1' : '0'); if (ieee80211_network_init(ieee, beacon, &network, stats)) { - IEEE80211_DEBUG_SCAN("Dropped '%s' (" MAC_FMT ") via %s.\n", + IEEE80211_DEBUG_SCAN("Dropped '%s' (%pM) via %s.\n", escape_essid(info_element->data, info_element->len), - MAC_ARG(beacon->header.addr3), + beacon->header.addr3, WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP ? "PROBE RESPONSE" : "BEACON"); @@ -2692,11 +2692,11 @@ static inline void ieee80211_process_probe_response( /* If there are no more slots, expire the oldest */ list_del(&oldest->list); target = oldest; - IEEE80211_DEBUG_SCAN("Expired '%s' (" MAC_FMT ") from " + IEEE80211_DEBUG_SCAN("Expired '%s' (%pM) from " "network list.\n", escape_essid(target->ssid, target->ssid_len), - MAC_ARG(target->bssid)); + target->bssid); } else { /* Otherwise just pull from the free list */ target = list_entry(ieee->network_free_list.next, @@ -2706,10 +2706,10 @@ static inline void ieee80211_process_probe_response( #ifdef CONFIG_IEEE80211_DEBUG - IEEE80211_DEBUG_SCAN("Adding '%s' (" MAC_FMT ") via %s.\n", + IEEE80211_DEBUG_SCAN("Adding '%s' (%pM) via %s.\n", escape_essid(network.ssid, network.ssid_len), - MAC_ARG(network.bssid), + network.bssid, WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP ? "PROBE RESPONSE" : "BEACON"); @@ -2719,10 +2719,10 @@ static inline void ieee80211_process_probe_response( if(ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) ieee80211_softmac_new_net(ieee,&network); } else { - IEEE80211_DEBUG_SCAN("Updating '%s' (" MAC_FMT ") via %s.\n", + IEEE80211_DEBUG_SCAN("Updating '%s' (%pM) via %s.\n", escape_essid(target->ssid, target->ssid_len), - MAC_ARG(target->bssid), + target->bssid, WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP ? "PROBE RESPONSE" : "BEACON"); diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac.c index 6d1ddec39f0e..9e923e29c455 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac.c @@ -1897,7 +1897,7 @@ ieee80211_rx_assoc_rq(struct ieee80211_device *ieee, struct sk_buff *skb) ieee80211_resp_to_assoc_rq(ieee, dest); } - printk(KERN_INFO"New client associated: "MAC_FMT"\n", MAC_ARG(dest)); + printk(KERN_INFO"New client associated: %pM\n", dest); //FIXME #if 0 spin_lock_irqsave(&ieee->lock,flags); diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_tx.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_tx.c index 798fb4154c25..0710d9e30dba 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_tx.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_tx.c @@ -200,8 +200,8 @@ int ieee80211_encrypt_fragment( header = (struct ieee80211_hdr *) frag->data; if (net_ratelimit()) { printk(KERN_DEBUG "%s: TKIP countermeasures: dropped " - "TX packet to " MAC_FMT "\n", - ieee->dev->name, MAC_ARG(header->addr1)); + "TX packet to %pM\n", + ieee->dev->name, header->addr1); } return -1; } diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_wx.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_wx.c index 3441b72dd8fa..efd61bbf06f9 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_wx.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_wx.c @@ -386,10 +386,10 @@ int ieee80211_wx_get_scan(struct ieee80211_device *ieee, else IEEE80211_DEBUG_SCAN( "Not showing network '%s (" - MAC_FMT ")' due to age (%lums).\n", + "%pM)' due to age (%lums).\n", escape_essid(network->ssid, network->ssid_len), - MAC_ARG(network->bssid), + network->bssid, (jiffies - network->last_scanned) / (HZ / 100)); } diff --git a/drivers/staging/rtl8192e/ieee80211/rtl819x_BAProc.c b/drivers/staging/rtl8192e/ieee80211/rtl819x_BAProc.c index e41e8a0c739c..ae0e5b9e2183 100644 --- a/drivers/staging/rtl8192e/ieee80211/rtl819x_BAProc.c +++ b/drivers/staging/rtl8192e/ieee80211/rtl819x_BAProc.c @@ -113,7 +113,7 @@ static struct sk_buff* ieee80211_ADDBA(struct ieee80211_device* ieee, u8* Dst, P u16 tmp = 0; u16 len = ieee->tx_headroom + 9; //category(1) + action field(1) + Dialog Token(1) + BA Parameter Set(2) + BA Timeout Value(2) + BA Start SeqCtrl(2)(or StatusCode(2)) - IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), frame(%d) sentd to:"MAC_FMT", ieee->dev:%p\n", __FUNCTION__, type, MAC_ARG(Dst), ieee->dev); + IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), frame(%d) sentd to:%pM, ieee->dev:%p\n", __FUNCTION__, type, Dst, ieee->dev); if (pBA == NULL||ieee == NULL) { IEEE80211_DEBUG(IEEE80211_DL_ERR, "pBA(%p) is NULL or ieee(%p) is NULL\n", pBA, ieee); @@ -243,7 +243,7 @@ static struct sk_buff* ieee80211_DELBA( u16 len = 6 + ieee->tx_headroom; if (net_ratelimit()) - IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), ReasonCode(%d) sentd to:"MAC_FMT"\n", __FUNCTION__, ReasonCode, MAC_ARG(dst)); + IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), ReasonCode(%d) sentd to:%pM\n", __FUNCTION__, ReasonCode, dst); memset(&DelbaParamSet, 0, 2); @@ -397,7 +397,7 @@ int ieee80211_rx_ADDBAReq( struct ieee80211_device* ieee, struct sk_buff *skb) pBaTimeoutVal = (u16*)(tag + 5); pBaStartSeqCtrl = (PSEQUENCE_CONTROL)(req + 7); - printk("====================>rx ADDBAREQ from :"MAC_FMT"\n", MAC_ARG(dst)); + printk("====================>rx ADDBAREQ from :%pM\n", dst); //some other capability is not ready now. if( (ieee->current_network.qos_data.active == 0) || (ieee->pHTInfo->bCurrentHTSupport == false)) //|| diff --git a/drivers/staging/rtl8192e/ieee80211/rtl819x_TSProc.c b/drivers/staging/rtl8192e/ieee80211/rtl819x_TSProc.c index 2816b60a08a9..e2cbfd3aa00f 100644 --- a/drivers/staging/rtl8192e/ieee80211/rtl819x_TSProc.c +++ b/drivers/staging/rtl8192e/ieee80211/rtl819x_TSProc.c @@ -304,7 +304,7 @@ PTS_COMMON_INFO SearchAdmitTRStream(struct ieee80211_device *ieee, u8* Addr, u8 if(search_dir[dir] ==false ) continue; list_for_each_entry(pRet, psearch_list, List){ - // IEEE80211_DEBUG(IEEE80211_DL_TS, "ADD:"MAC_FMT", TID:%d, dir:%d\n", MAC_ARG(pRet->Addr), pRet->TSpec.f.TSInfo.field.ucTSID, pRet->TSpec.f.TSInfo.field.ucDirection); + // IEEE80211_DEBUG(IEEE80211_DL_TS, "ADD:%pM, TID:%d, dir:%d\n", pRet->Addr, pRet->TSpec.f.TSInfo.field.ucTSID, pRet->TSpec.f.TSInfo.field.ucDirection); if (memcmp(pRet->Addr, Addr, 6) == 0) if (pRet->TSpec.f.TSInfo.field.ucTSID == TID) if(pRet->TSpec.f.TSInfo.field.ucDirection == dir) @@ -466,7 +466,7 @@ bool GetTs( ResetRxTsEntry(tmp); } - IEEE80211_DEBUG(IEEE80211_DL_TS, "to init current TS, UP:%d, Dir:%d, addr:"MAC_FMT"\n", UP, Dir, MAC_ARG(Addr)); + IEEE80211_DEBUG(IEEE80211_DL_TS, "to init current TS, UP:%d, Dir:%d, addr:%pM\n", UP, Dir, Addr); // Prepare TS Info releated field pTSInfo->field.ucTrafficType = 0; // Traffic type: WMM is reserved in this field pTSInfo->field.ucTSID = UP; // TSID @@ -552,7 +552,7 @@ void RemoveTsEntry( void RemovePeerTS(struct ieee80211_device* ieee, u8* Addr) { PTS_COMMON_INFO pTS, pTmpTS; - printk("===========>RemovePeerTS,"MAC_FMT"\n", MAC_ARG(Addr)); + printk("===========>RemovePeerTS,%pM\n", Addr); #if 1 list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Pending_List, List) { diff --git a/drivers/staging/rtl8192e/r8192E_core.c b/drivers/staging/rtl8192e/r8192E_core.c index 0ca5d8b4f746..0f6954863e69 100644 --- a/drivers/staging/rtl8192e/r8192E_core.c +++ b/drivers/staging/rtl8192e/r8192E_core.c @@ -6394,7 +6394,7 @@ void setKey( struct net_device *dev, if (EntryNo >= TOTAL_CAM_ENTRY) RT_TRACE(COMP_ERR, "cam entry exceeds in setKey()\n"); - RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d, KeyType:%d, MacAddr"MAC_FMT"\n", dev,EntryNo, KeyIndex, KeyType, MAC_ARG(MacAddr)); + RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d, KeyType:%d, MacAddr%pM\n", dev,EntryNo, KeyIndex, KeyType, MacAddr); if (DefaultKey) usConfig |= BIT15 | (KeyType<<2); diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211.h b/drivers/staging/rtl8192su/ieee80211/ieee80211.h index 9a4c858b0666..159fddf628e2 100644 --- a/drivers/staging/rtl8192su/ieee80211/ieee80211.h +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211.h @@ -195,10 +195,6 @@ extern u32 ieee80211_debug_level; #define IEEE80211_DEBUG_DATA(level, data, datalen) do {} while(0) #endif /* CONFIG_IEEE80211_DEBUG */ -#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" -#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], \ - ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5] - /* * To use the debug system; * diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_ccmp.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_ccmp.c index 7bc956e1f458..8a93f7d3eb38 100644 --- a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_ccmp.c +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_ccmp.c @@ -288,7 +288,7 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (!(keyidx & (1 << 5))) { if (net_ratelimit()) { printk(KERN_DEBUG "CCMP: received packet without ExtIV" - " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2)); + " flag from %pM\n", hdr->addr2); } key->dot11RSNAStatsCCMPFormatErrors++; return -2; @@ -301,9 +301,9 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) } if (!key->key_set) { if (net_ratelimit()) { - printk(KERN_DEBUG "CCMP: received packet from " MAC_FMT + printk(KERN_DEBUG "CCMP: received packet from %pM" " with keyid=%d that does not have a configured" - " key\n", MAC_ARG(hdr->addr2), keyidx); + " key\n", hdr->addr2, keyidx); } return -3; } @@ -318,11 +318,9 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (memcmp(pn, key->rx_pn, CCMP_PN_LEN) <= 0) { if (net_ratelimit()) { - printk(KERN_DEBUG "CCMP: replay detected: STA=" MAC_FMT - " previous PN %02x%02x%02x%02x%02x%02x " - "received PN %02x%02x%02x%02x%02x%02x\n", - MAC_ARG(hdr->addr2), MAC_ARG(key->rx_pn), - MAC_ARG(pn)); + printk(KERN_DEBUG "CCMP: replay detected: STA=%pM" + " previous PN %pm received PN %pm\n", + hdr->addr2, key->rx_pn, pn); } key->dot11RSNAStatsCCMPReplays++; return -4; @@ -359,7 +357,7 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (memcmp(mic, a, CCMP_MIC_LEN) != 0) { if (net_ratelimit()) { printk(KERN_DEBUG "CCMP: decrypt failed: STA=" - MAC_FMT "\n", MAC_ARG(hdr->addr2)); + "%pM\n", hdr->addr2); } key->dot11RSNAStatsCCMPDecryptErrors++; return -5; @@ -435,11 +433,10 @@ static char * ieee80211_ccmp_print_stats(char *p, void *priv) { struct ieee80211_ccmp_data *ccmp = priv; p += sprintf(p, "key[%d] alg=CCMP key_set=%d " - "tx_pn=%02x%02x%02x%02x%02x%02x " - "rx_pn=%02x%02x%02x%02x%02x%02x " + "tx_pn=%pm rx_pn=%pm " "format_errors=%d replays=%d decrypt_errors=%d\n", ccmp->key_idx, ccmp->key_set, - MAC_ARG(ccmp->tx_pn), MAC_ARG(ccmp->rx_pn), + ccmp->tx_pn, ccmp->rx_pn, ccmp->dot11RSNAStatsCCMPFormatErrors, ccmp->dot11RSNAStatsCCMPReplays, ccmp->dot11RSNAStatsCCMPDecryptErrors); diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_tkip.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_tkip.c index 9b9438fb5f60..7e48748da102 100644 --- a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_tkip.c +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_tkip.c @@ -410,7 +410,7 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (!(keyidx & (1 << 5))) { if (net_ratelimit()) { printk(KERN_DEBUG "TKIP: received packet without ExtIV" - " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2)); + " flag from %pM\n", hdr->addr2); } return -2; } @@ -422,9 +422,9 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) } if (!tkey->key_set) { if (net_ratelimit()) { - printk(KERN_DEBUG "TKIP: received packet from " MAC_FMT + printk(KERN_DEBUG "TKIP: received packet from %pM" " with keyid=%d that does not have a configured" - " key\n", MAC_ARG(hdr->addr2), keyidx); + " key\n", hdr->addr2, keyidx); } return -3; } @@ -437,9 +437,9 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (iv32 < tkey->rx_iv32 || (iv32 == tkey->rx_iv32 && iv16 <= tkey->rx_iv16)) { if (net_ratelimit()) { - printk(KERN_DEBUG "TKIP: replay detected: STA=" MAC_FMT + printk(KERN_DEBUG "TKIP: replay detected: STA=%pM" " previous TSC %08x%04x received TSC " - "%08x%04x\n", MAC_ARG(hdr->addr2), + "%08x%04x\n", hdr->addr2, tkey->rx_iv32, tkey->rx_iv16, iv32, iv16); } tkey->dot11RSNAStatsTKIPReplays++; @@ -460,8 +460,8 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (crypto_blkcipher_decrypt(&desc, &sg, &sg, plen + 4)) { if (net_ratelimit()) { printk(KERN_DEBUG ": TKIP: failed to decrypt " - "received packet from " MAC_FMT "\n", - MAC_ARG(hdr->addr2)); + "received packet from %pM\n", + hdr->addr2); } return -7; } @@ -480,7 +480,7 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) } if (net_ratelimit()) { printk(KERN_DEBUG "TKIP: ICV error detected: STA=" - MAC_FMT "\n", MAC_ARG(hdr->addr2)); + "%pM\n", hdr->addr2); } tkey->dot11RSNAStatsTKIPICVErrors++; return -5; @@ -635,8 +635,8 @@ static int ieee80211_michael_mic_verify(struct sk_buff *skb, int keyidx, struct ieee80211_hdr_4addr *hdr; hdr = (struct ieee80211_hdr_4addr *) skb->data; printk(KERN_DEBUG "%s: Michael MIC verification failed for " - "MSDU from " MAC_FMT " keyidx=%d\n", - skb->dev ? skb->dev->name : "N/A", MAC_ARG(hdr->addr2), + "MSDU from %pM keyidx=%d\n", + skb->dev ? skb->dev->name : "N/A", hdr->addr2, keyidx); if (skb->dev) ieee80211_michael_mic_failure(skb->dev, hdr, keyidx); diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_rx.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_rx.c index fecfa120ff48..67b99ad88475 100644 --- a/drivers/staging/rtl8192su/ieee80211/ieee80211_rx.c +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_rx.c @@ -314,8 +314,8 @@ ieee80211_rx_frame_decrypt(struct ieee80211_device* ieee, struct sk_buff *skb, strcmp(crypt->ops->name, "TKIP") == 0) { if (net_ratelimit()) { printk(KERN_DEBUG "%s: TKIP countermeasures: dropped " - "received packet from " MAC_FMT "\n", - ieee->dev->name, MAC_ARG(hdr->addr2)); + "received packet from %pM\n", + ieee->dev->name, hdr->addr2); } return -1; } @@ -326,8 +326,8 @@ ieee80211_rx_frame_decrypt(struct ieee80211_device* ieee, struct sk_buff *skb, atomic_dec(&crypt->refcnt); if (res < 0) { IEEE80211_DEBUG_DROP( - "decryption failed (SA=" MAC_FMT - ") res=%d\n", MAC_ARG(hdr->addr2), res); + "decryption failed (SA=%pM" + ") res=%d\n", hdr->addr2, res); if (res == -2) IEEE80211_DEBUG_DROP("Decryption failed ICV " "mismatch (key %d)\n", @@ -364,8 +364,8 @@ ieee80211_rx_frame_decrypt_msdu(struct ieee80211_device* ieee, struct sk_buff *s atomic_dec(&crypt->refcnt); if (res < 0) { printk(KERN_DEBUG "%s: MSDU decryption/MIC verification failed" - " (SA=" MAC_FMT " keyidx=%d)\n", - ieee->dev->name, MAC_ARG(hdr->addr2), keyidx); + " (SA=%pM keyidx=%d)\n", + ieee->dev->name, hdr->addr2, keyidx); return -1; } @@ -939,8 +939,8 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, * frames silently instead of filling system log with * these reports. */ IEEE80211_DEBUG_DROP("Decryption failed (not set)" - " (SA=" MAC_FMT ")\n", - MAC_ARG(hdr->addr2)); + " (SA=%pM)\n", + hdr->addr2); ieee->ieee_stats.rx_discards_undecryptable++; goto rx_dropped; } @@ -1143,8 +1143,8 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, } else { IEEE80211_DEBUG_DROP( "encryption configured, but RX " - "frame not encrypted (SA=" MAC_FMT ")\n", - MAC_ARG(hdr->addr2)); + "frame not encrypted (SA=%pM)\n", + hdr->addr2); goto rx_dropped; } } @@ -1163,9 +1163,9 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, !ieee80211_is_eapol_frame(ieee, skb, hdrlen)) { IEEE80211_DEBUG_DROP( "dropped unencrypted RX data " - "frame from " MAC_FMT + "frame from %pM" " (drop_unencrypted=1)\n", - MAC_ARG(hdr->addr2)); + hdr->addr2); goto rx_dropped; } /* @@ -2159,11 +2159,11 @@ static inline int ieee80211_network_init( } if (network->mode == 0) { - IEEE80211_DEBUG_SCAN("Filtered out '%s (" MAC_FMT ")' " + IEEE80211_DEBUG_SCAN("Filtered out '%s (%pM)' " "network.\n", escape_essid(network->ssid, network->ssid_len), - MAC_ARG(network->bssid)); + network->bssid); return 1; } @@ -2345,9 +2345,9 @@ static inline void ieee80211_process_probe_response( memset(&network, 0, sizeof(struct ieee80211_network)); IEEE80211_DEBUG_SCAN( - "'%s' (" MAC_FMT "): %c%c%c%c %c%c%c%c-%c%c%c%c %c%c%c%c\n", + "'%s' (%pM): %c%c%c%c %c%c%c%c-%c%c%c%c %c%c%c%c\n", escape_essid(info_element->data, info_element->len), - MAC_ARG(beacon->header.addr3), + beacon->header.addr3, (beacon->capability & (1<<0xf)) ? '1' : '0', (beacon->capability & (1<<0xe)) ? '1' : '0', (beacon->capability & (1<<0xd)) ? '1' : '0', @@ -2366,10 +2366,10 @@ static inline void ieee80211_process_probe_response( (beacon->capability & (1<<0x0)) ? '1' : '0'); if (ieee80211_network_init(ieee, beacon, &network, stats)) { - IEEE80211_DEBUG_SCAN("Dropped '%s' (" MAC_FMT ") via %s.\n", + IEEE80211_DEBUG_SCAN("Dropped '%s' (%pM) via %s.\n", escape_essid(info_element->data, info_element->len), - MAC_ARG(beacon->header.addr3), + beacon->header.addr3, WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP ? "PROBE RESPONSE" : "BEACON"); @@ -2478,11 +2478,11 @@ static inline void ieee80211_process_probe_response( /* If there are no more slots, expire the oldest */ list_del(&oldest->list); target = oldest; - IEEE80211_DEBUG_SCAN("Expired '%s' (" MAC_FMT ") from " + IEEE80211_DEBUG_SCAN("Expired '%s' (%pM) from " "network list.\n", escape_essid(target->ssid, target->ssid_len), - MAC_ARG(target->bssid)); + target->bssid); } else { /* Otherwise just pull from the free list */ target = list_entry(ieee->network_free_list.next, @@ -2492,10 +2492,10 @@ static inline void ieee80211_process_probe_response( #ifdef CONFIG_IEEE80211_DEBUG - IEEE80211_DEBUG_SCAN("Adding '%s' (" MAC_FMT ") via %s.\n", + IEEE80211_DEBUG_SCAN("Adding '%s' (%pM) via %s.\n", escape_essid(network.ssid, network.ssid_len), - MAC_ARG(network.bssid), + network.bssid, WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP ? "PROBE RESPONSE" : "BEACON"); @@ -2505,10 +2505,10 @@ static inline void ieee80211_process_probe_response( if(ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) ieee80211_softmac_new_net(ieee,&network); } else { - IEEE80211_DEBUG_SCAN("Updating '%s' (" MAC_FMT ") via %s.\n", + IEEE80211_DEBUG_SCAN("Updating '%s' (%pM) via %s.\n", escape_essid(target->ssid, target->ssid_len), - MAC_ARG(target->bssid), + target->bssid, WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP ? "PROBE RESPONSE" : "BEACON"); diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c index 95d4f84dcf3f..e46f3bc6a21a 100644 --- a/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c @@ -1709,7 +1709,7 @@ ieee80211_rx_assoc_rq(struct ieee80211_device *ieee, struct sk_buff *skb) ieee80211_resp_to_assoc_rq(ieee, dest); } - printk(KERN_INFO"New client associated: "MAC_FMT"\n", MAC_ARG(dest)); + printk(KERN_INFO"New client associated: %pM\n", dest); //FIXME } diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c index 4d54e1e62d22..484c3aba5cb3 100644 --- a/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c @@ -199,8 +199,8 @@ int ieee80211_encrypt_fragment( header = (struct rtl_ieee80211_hdr *)frag->data; if (net_ratelimit()) { printk(KERN_DEBUG "%s: TKIP countermeasures: dropped " - "TX packet to " MAC_FMT "\n", - ieee->dev->name, MAC_ARG(header->addr1)); + "TX packet to %pM\n", + ieee->dev->name, header->addr1); } return -1; } diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c index 85c7e96b622d..0f21ccbdeddd 100644 --- a/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c @@ -261,10 +261,10 @@ int ieee80211_wx_get_scan(struct ieee80211_device *ieee, else IEEE80211_DEBUG_SCAN( "Not showing network '%s (" - MAC_FMT ")' due to age (%lums).\n", + "%pM)' due to age (%lums).\n", escape_essid(network->ssid, network->ssid_len), - MAC_ARG(network->bssid), + network->bssid, (jiffies - network->last_scanned) / (HZ / 100)); } diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c b/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c index 8d12ffca18fa..6eb1096866af 100644 --- a/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c +++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c @@ -113,7 +113,7 @@ static struct sk_buff* ieee80211_ADDBA(struct ieee80211_device* ieee, u8* Dst, P u16 tmp = 0; u16 len = ieee->tx_headroom + 9; //category(1) + action field(1) + Dialog Token(1) + BA Parameter Set(2) + BA Timeout Value(2) + BA Start SeqCtrl(2)(or StatusCode(2)) - IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), frame(%d) sentd to:"MAC_FMT", ieee->dev:%p\n", __FUNCTION__, type, MAC_ARG(Dst), ieee->dev); + IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), frame(%d) sentd to:%pM, ieee->dev:%p\n", __FUNCTION__, type, Dst, ieee->dev); if (pBA == NULL||ieee == NULL) { IEEE80211_DEBUG(IEEE80211_DL_ERR, "pBA(%p) is NULL or ieee(%p) is NULL\n", pBA, ieee); @@ -200,7 +200,7 @@ static struct sk_buff* ieee80211_DELBA( u16 len = 6 + ieee->tx_headroom; if (net_ratelimit()) - IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), ReasonCode(%d) sentd to:"MAC_FMT"\n", __FUNCTION__, ReasonCode, MAC_ARG(dst)); + IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), ReasonCode(%d) sentd to:%pM\n", __FUNCTION__, ReasonCode, dst); memset(&DelbaParamSet, 0, 2); @@ -354,7 +354,7 @@ int ieee80211_rx_ADDBAReq( struct ieee80211_device* ieee, struct sk_buff *skb) pBaTimeoutVal = (u16*)(tag + 5); pBaStartSeqCtrl = (PSEQUENCE_CONTROL)(req + 7); - printk("====================>rx ADDBAREQ from :"MAC_FMT"\n", MAC_ARG(dst)); + printk("====================>rx ADDBAREQ from :%pM\n", dst); //some other capability is not ready now. if( (ieee->current_network.qos_data.active == 0) || (ieee->pHTInfo->bCurrentHTSupport == false) || diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_TSProc.c b/drivers/staging/rtl8192su/ieee80211/rtl819x_TSProc.c index ad3bf35d80e6..60cf1f8781ce 100644 --- a/drivers/staging/rtl8192su/ieee80211/rtl819x_TSProc.c +++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_TSProc.c @@ -291,7 +291,7 @@ PTS_COMMON_INFO SearchAdmitTRStream(struct ieee80211_device *ieee, u8* Addr, u8 if(search_dir[dir] ==false ) continue; list_for_each_entry(pRet, psearch_list, List){ - // IEEE80211_DEBUG(IEEE80211_DL_TS, "ADD:"MAC_FMT", TID:%d, dir:%d\n", MAC_ARG(pRet->Addr), pRet->TSpec.f.TSInfo.field.ucTSID, pRet->TSpec.f.TSInfo.field.ucDirection); + // IEEE80211_DEBUG(IEEE80211_DL_TS, "ADD:%pM, TID:%d, dir:%d\n", pRet->Addr, pRet->TSpec.f.TSInfo.field.ucTSID, pRet->TSpec.f.TSInfo.field.ucDirection); if (memcmp(pRet->Addr, Addr, 6) == 0) if (pRet->TSpec.f.TSInfo.field.ucTSID == TID) if(pRet->TSpec.f.TSInfo.field.ucDirection == dir) @@ -447,7 +447,7 @@ bool GetTs( ResetRxTsEntry(tmp); } - IEEE80211_DEBUG(IEEE80211_DL_TS, "to init current TS, UP:%d, Dir:%d, addr:"MAC_FMT"\n", UP, Dir, MAC_ARG(Addr)); + IEEE80211_DEBUG(IEEE80211_DL_TS, "to init current TS, UP:%d, Dir:%d, addr:%pM\n", UP, Dir, Addr); // Prepare TS Info releated field pTSInfo->field.ucTrafficType = 0; // Traffic type: WMM is reserved in this field pTSInfo->field.ucTSID = UP; // TSID @@ -533,7 +533,7 @@ void RemoveTsEntry( void RemovePeerTS(struct ieee80211_device* ieee, u8* Addr) { PTS_COMMON_INFO pTS, pTmpTS; - printk("===========>RemovePeerTS,"MAC_FMT"\n", MAC_ARG(Addr)); + printk("===========>RemovePeerTS,%pM\n", Addr); #if 1 list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Pending_List, List) { diff --git a/drivers/staging/rtl8192su/r8192U_core.c b/drivers/staging/rtl8192su/r8192U_core.c index ccb9d5b8cd44..7fa02ac8e500 100644 --- a/drivers/staging/rtl8192su/r8192U_core.c +++ b/drivers/staging/rtl8192su/r8192U_core.c @@ -7677,7 +7677,7 @@ void setKey( struct net_device *dev, if (EntryNo >= TOTAL_CAM_ENTRY) RT_TRACE(COMP_ERR, "cam entry exceeds in setKey()\n"); - RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d, KeyType:%d, MacAddr"MAC_FMT"\n", dev,EntryNo, KeyIndex, KeyType, MAC_ARG(MacAddr)); + RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d, KeyType:%d, MacAddr%pM\n", dev,EntryNo, KeyIndex, KeyType, MacAddr); if (DefaultKey) usConfig |= BIT15 | (KeyType<<2); diff --git a/drivers/staging/rtl8192su/r8192U_dm.c b/drivers/staging/rtl8192su/r8192U_dm.c index 7891e9640272..fa5e24416dde 100644 --- a/drivers/staging/rtl8192su/r8192U_dm.c +++ b/drivers/staging/rtl8192su/r8192U_dm.c @@ -2697,7 +2697,7 @@ static void dm_check_edca_turbo( u8* peername[11] = {"unknown", "realtek", "realtek_92se", "broadcom", "ralink", "atheros", "cisco", "marvell", "92u_softap", "self_softap"}; static int wb_tmp = 0; if (wb_tmp == 0){ - printk("%s():iot peer is %#x:%s, bssid:"MAC_FMT"\n",__FUNCTION__,pHTInfo->IOTPeer,peername[pHTInfo->IOTPeer], MAC_ARG(priv->ieee80211->current_network.bssid)); + printk("%s():iot peer is %#x:%s, bssid:%pM\n",__FUNCTION__,pHTInfo->IOTPeer,peername[pHTInfo->IOTPeer], priv->ieee80211->current_network.bssid); wb_tmp = 1; } } diff --git a/drivers/staging/rtl8192u/ieee80211.h b/drivers/staging/rtl8192u/ieee80211.h index 3a47f1213e85..9d05ed6791ee 100644 --- a/drivers/staging/rtl8192u/ieee80211.h +++ b/drivers/staging/rtl8192u/ieee80211.h @@ -551,9 +551,6 @@ do { if (ieee80211_debug_level & (level)) \ /* debug macros not dependent on CONFIG_IEEE80211_DEBUG */ -#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" -#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] - /* * To use the debug system; * diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211.h b/drivers/staging/rtl8192u/ieee80211/ieee80211.h index 10908e123b86..3cda38bb6b77 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211.h +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211.h @@ -551,9 +551,6 @@ do { if (ieee80211_debug_level & (level)) \ /* debug macros not dependent on CONFIG_IEEE80211_DEBUG */ -#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" -#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] - /* * To use the debug system; * diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_ccmp.c b/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_ccmp.c index 0b33bf463320..0b57632bcff9 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_ccmp.c +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_ccmp.c @@ -288,7 +288,7 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (!(keyidx & (1 << 5))) { if (net_ratelimit()) { printk(KERN_DEBUG "CCMP: received packet without ExtIV" - " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2)); + " flag from %pM\n", hdr->addr2); } key->dot11RSNAStatsCCMPFormatErrors++; return -2; @@ -301,9 +301,9 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) } if (!key->key_set) { if (net_ratelimit()) { - printk(KERN_DEBUG "CCMP: received packet from " MAC_FMT + printk(KERN_DEBUG "CCMP: received packet from %pM" " with keyid=%d that does not have a configured" - " key\n", MAC_ARG(hdr->addr2), keyidx); + " key\n", hdr->addr2, keyidx); } return -3; } @@ -318,11 +318,9 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (memcmp(pn, key->rx_pn, CCMP_PN_LEN) <= 0) { if (net_ratelimit()) { - printk(KERN_DEBUG "CCMP: replay detected: STA=" MAC_FMT - " previous PN %02x%02x%02x%02x%02x%02x " - "received PN %02x%02x%02x%02x%02x%02x\n", - MAC_ARG(hdr->addr2), MAC_ARG(key->rx_pn), - MAC_ARG(pn)); + printk(KERN_DEBUG "CCMP: replay detected: STA=%pM" + " previous PN %pm received PN %pm\n", + hdr->addr2, key->rx_pn, pn); } key->dot11RSNAStatsCCMPReplays++; return -4; @@ -359,7 +357,7 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (memcmp(mic, a, CCMP_MIC_LEN) != 0) { if (net_ratelimit()) { printk(KERN_DEBUG "CCMP: decrypt failed: STA=" - MAC_FMT "\n", MAC_ARG(hdr->addr2)); + "%pM\n", hdr->addr2); } key->dot11RSNAStatsCCMPDecryptErrors++; return -5; @@ -435,11 +433,10 @@ static char * ieee80211_ccmp_print_stats(char *p, void *priv) { struct ieee80211_ccmp_data *ccmp = priv; p += sprintf(p, "key[%d] alg=CCMP key_set=%d " - "tx_pn=%02x%02x%02x%02x%02x%02x " - "rx_pn=%02x%02x%02x%02x%02x%02x " + "tx_pn=%pm rx_pn=%pm " "format_errors=%d replays=%d decrypt_errors=%d\n", ccmp->key_idx, ccmp->key_set, - MAC_ARG(ccmp->tx_pn), MAC_ARG(ccmp->rx_pn), + ccmp->tx_pn, ccmp->rx_pn, ccmp->dot11RSNAStatsCCMPFormatErrors, ccmp->dot11RSNAStatsCCMPReplays, ccmp->dot11RSNAStatsCCMPDecryptErrors); diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c b/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c index 841b99955b79..9510507d8d05 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c @@ -410,7 +410,7 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (!(keyidx & (1 << 5))) { if (net_ratelimit()) { printk(KERN_DEBUG "TKIP: received packet without ExtIV" - " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2)); + " flag from %pM\n", hdr->addr2); } return -2; } @@ -422,9 +422,9 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) } if (!tkey->key_set) { if (net_ratelimit()) { - printk(KERN_DEBUG "TKIP: received packet from " MAC_FMT + printk(KERN_DEBUG "TKIP: received packet from %pM" " with keyid=%d that does not have a configured" - " key\n", MAC_ARG(hdr->addr2), keyidx); + " key\n", hdr->addr2, keyidx); } return -3; } @@ -437,9 +437,9 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (iv32 < tkey->rx_iv32 || (iv32 == tkey->rx_iv32 && iv16 <= tkey->rx_iv16)) { if (net_ratelimit()) { - printk(KERN_DEBUG "TKIP: replay detected: STA=" MAC_FMT + printk(KERN_DEBUG "TKIP: replay detected: STA=%pM" " previous TSC %08x%04x received TSC " - "%08x%04x\n", MAC_ARG(hdr->addr2), + "%08x%04x\n", hdr->addr2, tkey->rx_iv32, tkey->rx_iv16, iv32, iv16); } tkey->dot11RSNAStatsTKIPReplays++; @@ -460,8 +460,8 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (crypto_blkcipher_decrypt(&desc, &sg, &sg, plen + 4)) { if (net_ratelimit()) { printk(KERN_DEBUG ": TKIP: failed to decrypt " - "received packet from " MAC_FMT "\n", - MAC_ARG(hdr->addr2)); + "received packet from %pM\n", + hdr->addr2); } return -7; } @@ -480,7 +480,7 @@ static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) } if (net_ratelimit()) { printk(KERN_DEBUG "TKIP: ICV error detected: STA=" - MAC_FMT "\n", MAC_ARG(hdr->addr2)); + "%pM\n", hdr->addr2); } tkey->dot11RSNAStatsTKIPICVErrors++; return -5; @@ -635,8 +635,8 @@ static int ieee80211_michael_mic_verify(struct sk_buff *skb, int keyidx, struct ieee80211_hdr_4addr *hdr; hdr = (struct ieee80211_hdr_4addr *) skb->data; printk(KERN_DEBUG "%s: Michael MIC verification failed for " - "MSDU from " MAC_FMT " keyidx=%d\n", - skb->dev ? skb->dev->name : "N/A", MAC_ARG(hdr->addr2), + "MSDU from %pM keyidx=%d\n", + skb->dev ? skb->dev->name : "N/A", hdr->addr2, keyidx); if (skb->dev) ieee80211_michael_mic_failure(skb->dev, hdr, keyidx); diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c b/drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c index 0e003c5bb000..7e9b367594a0 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211_rx.c @@ -360,8 +360,8 @@ ieee80211_rx_frame_decrypt(struct ieee80211_device* ieee, struct sk_buff *skb, strcmp(crypt->ops->name, "TKIP") == 0) { if (net_ratelimit()) { printk(KERN_DEBUG "%s: TKIP countermeasures: dropped " - "received packet from " MAC_FMT "\n", - ieee->dev->name, MAC_ARG(hdr->addr2)); + "received packet from %pM\n", + ieee->dev->name, hdr->addr2); } return -1; } @@ -372,8 +372,8 @@ ieee80211_rx_frame_decrypt(struct ieee80211_device* ieee, struct sk_buff *skb, atomic_dec(&crypt->refcnt); if (res < 0) { IEEE80211_DEBUG_DROP( - "decryption failed (SA=" MAC_FMT - ") res=%d\n", MAC_ARG(hdr->addr2), res); + "decryption failed (SA=%pM" + ") res=%d\n", hdr->addr2, res); if (res == -2) IEEE80211_DEBUG_DROP("Decryption failed ICV " "mismatch (key %d)\n", @@ -410,8 +410,8 @@ ieee80211_rx_frame_decrypt_msdu(struct ieee80211_device* ieee, struct sk_buff *s atomic_dec(&crypt->refcnt); if (res < 0) { printk(KERN_DEBUG "%s: MSDU decryption/MIC verification failed" - " (SA=" MAC_FMT " keyidx=%d)\n", - ieee->dev->name, MAC_ARG(hdr->addr2), keyidx); + " (SA=%pM keyidx=%d)\n", + ieee->dev->name, hdr->addr2, keyidx); return -1; } @@ -1016,8 +1016,8 @@ int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb, * frames silently instead of filling system log with * these reports. */ IEEE80211_DEBUG_DROP("Decryption failed (not set)" - " (SA=" MAC_FMT ")\n", - MAC_ARG(hdr->addr2)); + " (SA=%pM)\n", + hdr->addr2); ieee->ieee_stats.rx_discards_undecryptable++; goto rx_dropped; } @@ -1256,8 +1256,8 @@ int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb, } else { IEEE80211_DEBUG_DROP( "encryption configured, but RX " - "frame not encrypted (SA=" MAC_FMT ")\n", - MAC_ARG(hdr->addr2)); + "frame not encrypted (SA=%pM)\n", + hdr->addr2); goto rx_dropped; } } @@ -1276,9 +1276,9 @@ int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb, !ieee80211_is_eapol_frame(ieee, skb, hdrlen)) { IEEE80211_DEBUG_DROP( "dropped unencrypted RX data " - "frame from " MAC_FMT + "frame from %pM" " (drop_unencrypted=1)\n", - MAC_ARG(hdr->addr2)); + hdr->addr2); goto rx_dropped; } /* @@ -2260,11 +2260,11 @@ static inline int ieee80211_network_init( } if (network->mode == 0) { - IEEE80211_DEBUG_SCAN("Filtered out '%s (" MAC_FMT ")' " + IEEE80211_DEBUG_SCAN("Filtered out '%s (%pM)' " "network.\n", escape_essid(network->ssid, network->ssid_len), - MAC_ARG(network->bssid)); + network->bssid); return 1; } @@ -2439,9 +2439,9 @@ static inline void ieee80211_process_probe_response( memset(&network, 0, sizeof(struct ieee80211_network)); IEEE80211_DEBUG_SCAN( - "'%s' (" MAC_FMT "): %c%c%c%c %c%c%c%c-%c%c%c%c %c%c%c%c\n", + "'%s' (%pM): %c%c%c%c %c%c%c%c-%c%c%c%c %c%c%c%c\n", escape_essid(info_element->data, info_element->len), - MAC_ARG(beacon->header.addr3), + beacon->header.addr3, (beacon->capability & (1<<0xf)) ? '1' : '0', (beacon->capability & (1<<0xe)) ? '1' : '0', (beacon->capability & (1<<0xd)) ? '1' : '0', @@ -2460,10 +2460,10 @@ static inline void ieee80211_process_probe_response( (beacon->capability & (1<<0x0)) ? '1' : '0'); if (ieee80211_network_init(ieee, beacon, &network, stats)) { - IEEE80211_DEBUG_SCAN("Dropped '%s' (" MAC_FMT ") via %s.\n", + IEEE80211_DEBUG_SCAN("Dropped '%s' (%pM) via %s.\n", escape_essid(info_element->data, info_element->len), - MAC_ARG(beacon->header.addr3), + beacon->header.addr3, WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP ? "PROBE RESPONSE" : "BEACON"); @@ -2574,11 +2574,11 @@ static inline void ieee80211_process_probe_response( /* If there are no more slots, expire the oldest */ list_del(&oldest->list); target = oldest; - IEEE80211_DEBUG_SCAN("Expired '%s' (" MAC_FMT ") from " + IEEE80211_DEBUG_SCAN("Expired '%s' (%pM) from " "network list.\n", escape_essid(target->ssid, target->ssid_len), - MAC_ARG(target->bssid)); + target->bssid); } else { /* Otherwise just pull from the free list */ target = list_entry(ieee->network_free_list.next, @@ -2588,10 +2588,10 @@ static inline void ieee80211_process_probe_response( #ifdef CONFIG_IEEE80211_DEBUG - IEEE80211_DEBUG_SCAN("Adding '%s' (" MAC_FMT ") via %s.\n", + IEEE80211_DEBUG_SCAN("Adding '%s' (%pM) via %s.\n", escape_essid(network.ssid, network.ssid_len), - MAC_ARG(network.bssid), + network.bssid, WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP ? "PROBE RESPONSE" : "BEACON"); @@ -2601,10 +2601,10 @@ static inline void ieee80211_process_probe_response( if(ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) ieee80211_softmac_new_net(ieee,&network); } else { - IEEE80211_DEBUG_SCAN("Updating '%s' (" MAC_FMT ") via %s.\n", + IEEE80211_DEBUG_SCAN("Updating '%s' (%pM) via %s.\n", escape_essid(target->ssid, target->ssid_len), - MAC_ARG(target->bssid), + target->bssid, WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP ? "PROBE RESPONSE" : "BEACON"); diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_softmac.c b/drivers/staging/rtl8192u/ieee80211/ieee80211_softmac.c index 8a86e93465c8..27d925712cdd 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211_softmac.c +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211_softmac.c @@ -1731,7 +1731,7 @@ ieee80211_rx_assoc_rq(struct ieee80211_device *ieee, struct sk_buff *skb) ieee80211_resp_to_assoc_rq(ieee, dest); } - printk(KERN_INFO"New client associated: "MAC_FMT"\n", MAC_ARG(dest)); + printk(KERN_INFO"New client associated: %pM\n", dest); //FIXME } diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_tx.c b/drivers/staging/rtl8192u/ieee80211/ieee80211_tx.c index b29c36bac377..48537d948945 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211_tx.c +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211_tx.c @@ -200,8 +200,8 @@ int ieee80211_encrypt_fragment( header = (struct ieee80211_hdr *) frag->data; if (net_ratelimit()) { printk(KERN_DEBUG "%s: TKIP countermeasures: dropped " - "TX packet to " MAC_FMT "\n", - ieee->dev->name, MAC_ARG(header->addr1)); + "TX packet to %pM\n", + ieee->dev->name, header->addr1); } return -1; } diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c b/drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c index 5f12d62658c9..da2449d290cb 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c @@ -289,10 +289,10 @@ int ieee80211_wx_get_scan(struct ieee80211_device *ieee, else IEEE80211_DEBUG_SCAN( "Not showing network '%s (" - MAC_FMT ")' due to age (%lums).\n", + "%pM)' due to age (%lums).\n", escape_essid(network->ssid, network->ssid_len), - MAC_ARG(network->bssid), + network->bssid, (jiffies - network->last_scanned) / (HZ / 100)); } diff --git a/drivers/staging/rtl8192u/ieee80211/rtl819x_BAProc.c b/drivers/staging/rtl8192u/ieee80211/rtl819x_BAProc.c index 512a57aebde3..27d083a70eb2 100644 --- a/drivers/staging/rtl8192u/ieee80211/rtl819x_BAProc.c +++ b/drivers/staging/rtl8192u/ieee80211/rtl819x_BAProc.c @@ -113,7 +113,7 @@ static struct sk_buff* ieee80211_ADDBA(struct ieee80211_device* ieee, u8* Dst, P u16 tmp = 0; u16 len = ieee->tx_headroom + 9; //category(1) + action field(1) + Dialog Token(1) + BA Parameter Set(2) + BA Timeout Value(2) + BA Start SeqCtrl(2)(or StatusCode(2)) - IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), frame(%d) sentd to:"MAC_FMT", ieee->dev:%p\n", __FUNCTION__, type, MAC_ARG(Dst), ieee->dev); + IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), frame(%d) sentd to:%pM, ieee->dev:%p\n", __FUNCTION__, type, Dst, ieee->dev); if (pBA == NULL||ieee == NULL) { IEEE80211_DEBUG(IEEE80211_DL_ERR, "pBA(%p) is NULL or ieee(%p) is NULL\n", pBA, ieee); @@ -201,7 +201,7 @@ static struct sk_buff* ieee80211_DELBA( u16 len = 6 + ieee->tx_headroom; if (net_ratelimit()) - IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), ReasonCode(%d) sentd to:"MAC_FMT"\n", __FUNCTION__, ReasonCode, MAC_ARG(dst)); + IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), ReasonCode(%d) sentd to:%pM\n", __FUNCTION__, ReasonCode, dst); memset(&DelbaParamSet, 0, 2); @@ -355,7 +355,7 @@ int ieee80211_rx_ADDBAReq( struct ieee80211_device* ieee, struct sk_buff *skb) pBaTimeoutVal = (u16*)(tag + 5); pBaStartSeqCtrl = (PSEQUENCE_CONTROL)(req + 7); - printk("====================>rx ADDBAREQ from :"MAC_FMT"\n", MAC_ARG(dst)); + printk("====================>rx ADDBAREQ from :%pM\n", dst); //some other capability is not ready now. if( (ieee->current_network.qos_data.active == 0) || (ieee->pHTInfo->bCurrentHTSupport == false)) //|| diff --git a/drivers/staging/rtl8192u/ieee80211/rtl819x_TSProc.c b/drivers/staging/rtl8192u/ieee80211/rtl819x_TSProc.c index 5373d565af24..d1275e887f0c 100644 --- a/drivers/staging/rtl8192u/ieee80211/rtl819x_TSProc.c +++ b/drivers/staging/rtl8192u/ieee80211/rtl819x_TSProc.c @@ -290,7 +290,7 @@ PTS_COMMON_INFO SearchAdmitTRStream(struct ieee80211_device *ieee, u8* Addr, u8 if(search_dir[dir] ==false ) continue; list_for_each_entry(pRet, psearch_list, List){ - // IEEE80211_DEBUG(IEEE80211_DL_TS, "ADD:"MAC_FMT", TID:%d, dir:%d\n", MAC_ARG(pRet->Addr), pRet->TSpec.f.TSInfo.field.ucTSID, pRet->TSpec.f.TSInfo.field.ucDirection); + // IEEE80211_DEBUG(IEEE80211_DL_TS, "ADD:%pM, TID:%d, dir:%d\n", pRet->Addr, pRet->TSpec.f.TSInfo.field.ucTSID, pRet->TSpec.f.TSInfo.field.ucDirection); if (memcmp(pRet->Addr, Addr, 6) == 0) if (pRet->TSpec.f.TSInfo.field.ucTSID == TID) if(pRet->TSpec.f.TSInfo.field.ucDirection == dir) @@ -445,7 +445,7 @@ bool GetTs( ResetRxTsEntry(tmp); } - IEEE80211_DEBUG(IEEE80211_DL_TS, "to init current TS, UP:%d, Dir:%d, addr:"MAC_FMT"\n", UP, Dir, MAC_ARG(Addr)); + IEEE80211_DEBUG(IEEE80211_DL_TS, "to init current TS, UP:%d, Dir:%d, addr:%pM\n", UP, Dir, Addr); // Prepare TS Info releated field pTSInfo->field.ucTrafficType = 0; // Traffic type: WMM is reserved in this field pTSInfo->field.ucTSID = UP; // TSID @@ -531,7 +531,7 @@ void RemoveTsEntry( void RemovePeerTS(struct ieee80211_device* ieee, u8* Addr) { PTS_COMMON_INFO pTS, pTmpTS; - printk("===========>RemovePeerTS,"MAC_FMT"\n", MAC_ARG(Addr)); + printk("===========>RemovePeerTS,%pM\n", Addr); list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Pending_List, List) { if (memcmp(pTS->Addr, Addr, 6) == 0) diff --git a/drivers/staging/rtl8192u/r8192U_core.c b/drivers/staging/rtl8192u/r8192U_core.c index adade13e1e19..5afc73751043 100644 --- a/drivers/staging/rtl8192u/r8192U_core.c +++ b/drivers/staging/rtl8192u/r8192U_core.c @@ -2976,7 +2976,7 @@ static void rtl8192_read_eeprom_info(struct net_device* dev) memcpy(dev->dev_addr, bMac_Tmp_Addr, 6); //should I set IDR0 here? } - RT_TRACE(COMP_EPROM, "MAC addr:"MAC_FMT"\n", MAC_ARG(dev->dev_addr)); + RT_TRACE(COMP_EPROM, "MAC addr:%pM\n", dev->dev_addr); priv->rf_type = RTL819X_DEFAULT_RF_TYPE; //default 1T2R priv->rf_chip = RF_8256; @@ -6037,7 +6037,7 @@ void setKey( struct net_device *dev, if (EntryNo >= TOTAL_CAM_ENTRY) RT_TRACE(COMP_ERR, "cam entry exceeds in setKey()\n"); - RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d, KeyType:%d, MacAddr"MAC_FMT"\n", dev,EntryNo, KeyIndex, KeyType, MAC_ARG(MacAddr)); + RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d, KeyType:%d, MacAddr%pM\n", dev,EntryNo, KeyIndex, KeyType, MacAddr); if (DefaultKey) usConfig |= BIT15 | (KeyType<<2); -- cgit v1.2.3 From d753fa1df300fe9215a08603f1f8ac18825839eb Mon Sep 17 00:00:00 2001 From: Ameya Palande <2ameya@gmail.com> Date: Fri, 11 Dec 2009 19:10:10 +0200 Subject: Staging: mimio: Fix checkpatch.pl spacing errors Signed-off-by: Ameya Palande <2ameya@gmail.com> Signed-off-by: Greg Kroah-Hartman --- drivers/staging/mimio/mimio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/mimio/mimio.c b/drivers/staging/mimio/mimio.c index 1ba8103f5003..4d7a602a919c 100644 --- a/drivers/staging/mimio/mimio.c +++ b/drivers/staging/mimio/mimio.c @@ -145,7 +145,7 @@ static void mimio_rx_handler(struct mimio *, unsigned char *, unsigned int); static int mimio_tx(struct mimio *, const char *, int); static char mimio_name[] = "VirtualInk mimio-Xi"; -static struct usb_device_id mimio_table [] = { +static struct usb_device_id mimio_table[] = { { USB_DEVICE(MIMIO_VENDOR_ID, MIMIO_PRODUCT_ID) }, { USB_DEVICE(0x0525, 0xa4a0) }, /* gadget zero firmware */ { } @@ -588,7 +588,7 @@ static int handle_mimio_rx_penupdown(struct mimio *mimio, *(mimio->pktbuf.p + 2); if (x != *(mimio->pktbuf.p + 3)) { dev_dbg(&mimio->idev->dev, "EV_PEN%s: bad xsum.\n", - down ? "DOWN":"UP"); + down ? "DOWN" : "UP"); /* skip this event data */ mimio->pktbuf.p += 4; /* decode any remaining events */ -- cgit v1.2.3 From 2c6211606dafaeec51e471cd6aa277fbf45fe80c Mon Sep 17 00:00:00 2001 From: Ameya Palande <2ameya@gmail.com> Date: Fri, 11 Dec 2009 19:10:11 +0200 Subject: Staging: mimio: Remove dead code Signed-off-by: Ameya Palande <2ameya@gmail.com> Signed-off-by: Greg Kroah-Hartman --- drivers/staging/mimio/mimio.c | 24 ------------------------ 1 file changed, 24 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/mimio/mimio.c b/drivers/staging/mimio/mimio.c index 4d7a602a919c..5bdbe02eb793 100644 --- a/drivers/staging/mimio/mimio.c +++ b/drivers/staging/mimio/mimio.c @@ -505,23 +505,6 @@ static int mimio_probe(struct usb_interface *ifc, input_set_abs_params(input_dev, ABS_Y, 0, MIMIO_YRANGE_MAX, 0, 0); input_dev->absbit[BIT_WORD(ABS_MISC)] |= BIT_MASK(ABS_MISC); -#if 0 - input_dev->absmin[ABS_X] = 0; - input_dev->absmin[ABS_Y] = 0; - input_dev->absmax[ABS_X] = 9600; - input_dev->absmax[ABS_Y] = 4800; - input_dev->absfuzz[ABS_X] = 0; - input_dev->absfuzz[ABS_Y] = 0; - input_dev->absflat[ABS_X] = 0; - input_dev->absflat[ABS_Y] = 0; -#endif - -#if 0 - /* this will just reduce the precision */ - input_dev->absfuzz[ABS_X] = 8; /* experimental; may need to change */ - input_dev->absfuzz[ABS_Y] = 8; /* experimental; may need to change */ -#endif - /* * Register the input device. */ @@ -720,13 +703,6 @@ static void mimio_rx_handler(struct mimio *mimio, if (instr_ofst[mimio->pktbuf.instr] >= 0) { int code = BTN_TOOL_PEN + instr_ofst[mimio->last_pen_down]; -#if 0 - /* Utter hack to ensure we get forwarded _AND_ - * so we can identify when a complete signal is - * received */ - mimio->idev->abs[ABS_Y] = -1; - mimio->idev->abs[ABS_X] = -1; -#endif /* input_regs(mimio->idev, regs); */ input_report_abs(mimio->idev, ABS_X, x); input_report_abs(mimio->idev, ABS_Y, y); -- cgit v1.2.3 From 8d4ecdda9870d0999ebb8ed59293f420b5d244fd Mon Sep 17 00:00:00 2001 From: Ameya Palande <2ameya@gmail.com> Date: Fri, 11 Dec 2009 19:10:12 +0200 Subject: Staging: mimio: checkpatch.pl line > 80 chars fixes Rearrange code and cleanup the information to get rid of checkpatch.pl line > 80 chars complaints. Signed-off-by: Ameya Palande <2ameya@gmail.com> Signed-off-by: Greg Kroah-Hartman --- drivers/staging/mimio/mimio.c | 96 +++++++++++++++++++++++-------------------- 1 file changed, 51 insertions(+), 45 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/mimio/mimio.c b/drivers/staging/mimio/mimio.c index 5bdbe02eb793..2cfef4a0851f 100644 --- a/drivers/staging/mimio/mimio.c +++ b/drivers/staging/mimio/mimio.c @@ -1,47 +1,46 @@ /* * Hardware event => input event mapping: * + * BTN_TOOL_PEN 0x140 black + * BTN_TOOL_RUBBER 0x141 blue + * BTN_TOOL_BRUSH 0x142 green + * BTN_TOOL_PENCIL 0x143 red + * BTN_TOOL_AIRBRUSH 0x144 eraser + * BTN_TOOL_FINGER 0x145 small eraser + * BTN_TOOL_MOUSE 0x146 mimio interactive + * BTN_TOOL_LENS 0x147 mimio interactive but1 + * LOCALBTN_TOOL_EXTRA1 0x14a mimio interactive but2 == BTN_TOUCH + * LOCALBTN_TOOL_EXTRA2 0x14b mimio extra pens (orange, brown, yellow, + * purple) == BTN_STYLUS + * LOCALBTN_TOOL_EXTRA3 0x14c unused == BTN_STYLUS2 + * BTN_TOOL_DOUBLETAP 0x14d unused + * BTN_TOOL_TRIPLETAP 0x14e unused * - * - input.h:#define BTN_TOOL_PEN 0x140 black - input.h:#define BTN_TOOL_RUBBER 0x141 blue - input.h:#define BTN_TOOL_BRUSH 0x142 green - input.h:#define BTN_TOOL_PENCIL 0x143 red - input.h:#define BTN_TOOL_AIRBRUSH 0x144 eraser - input.h:#define BTN_TOOL_FINGER 0x145 small eraser - input.h:#define BTN_TOOL_MOUSE 0x146 mimio interactive - input.h:#define BTN_TOOL_LENS 0x147 mimio interactive but1 - input.h:#define LOCALBTN_TOOL_EXTRA1 0x14a mimio interactive but2 == BTN_TOUCH - input.h:#define LOCALBTN_TOOL_EXTRA2 0x14b mimio extra pens (orange, brown, yellow, purple) == BTN_STYLUS - input.h:#define LOCALBTN_TOOL_EXTRA3 0x14c unused == BTN_STYLUS2 - input.h:#define BTN_TOOL_DOUBLETAP 0x14d unused - input.h:#define BTN_TOOL_TRIPLETAP 0x14e unused - * - * MIMIO_EV_PENDOWN(MIMIO_PEN_K) => EV_KEY BIT(BTN_TOOL_PEN) - * MIMIO_EV_PENDOWN(MIMIO_PEN_B) => EV_KEY BIT(BTN_TOOL_RUBBER) - * MIMIO_EV_PENDOWN(MIMIO_PEN_G) => EV_KEY BIT(BTN_TOOL_BRUSH) - * MIMIO_EV_PENDOWN(MIMIO_PEN_R) => EV_KEY BIT(BTN_TOOL_PENCIL) - * MIMIO_EV_PENDOWN(MIMIO_PEN_E) => EV_KEY BIT(BTN_TOOL_AIRBRUSH) - * MIMIO_EV_PENDOWN(MIMIO_PEN_ES) => EV_KEY BIT(BTN_TOOL_FINGER) - * MIMIO_EV_PENDOWN(MIMIO_PEN_I) => EV_KEY BIT(BTN_TOOL_MOUSE) - * MIMIO_EV_PENDOWN(MIMIO_PEN_IL) => EV_KEY BIT(BTN_TOOL_LENS) - * MIMIO_EV_PENDOWN(MIMIO_PEN_IR) => EV_KEY BIT(BTN_TOOL_DOUBLETAP) - * MIMIO_EV_PENDOWN(MIMIO_PEN_EX) => EV_KEY BIT(BTN_TOOL_TRIPLETAP) - * MIMIO_EV_PENDATA => EV_ABS BIT(ABS_X), BIT(ABS_Y) - * MIMIO_EV_MEMRESET => EV_KEY BIT(BTN_0) - * MIMIO_EV_ACC(ACC_NEWPAGE) => EV_KEY BIT(BTN_1) - * MIMIO_EV_ACC(ACC_TAGPAGE) => EV_KEY BIT(BTN_2) - * MIMIO_EV_ACC(ACC_PRINTPAGE) => EV_KEY BIT(BTN_3) - * MIMIO_EV_ACC(ACC_MAXIMIZE) => EV_KEY BIT(BTN_4) - * MIMIO_EV_ACC(ACC_FINDCTLPNL) => EV_KEY BIT(BTN_5) - * + * MIMIO_EV_PENDOWN(MIMIO_PEN_K) => EV_KEY BIT(BTN_TOOL_PEN) + * MIMIO_EV_PENDOWN(MIMIO_PEN_B) => EV_KEY BIT(BTN_TOOL_RUBBER) + * MIMIO_EV_PENDOWN(MIMIO_PEN_G) => EV_KEY BIT(BTN_TOOL_BRUSH) + * MIMIO_EV_PENDOWN(MIMIO_PEN_R) => EV_KEY BIT(BTN_TOOL_PENCIL) + * MIMIO_EV_PENDOWN(MIMIO_PEN_E) => EV_KEY BIT(BTN_TOOL_AIRBRUSH) + * MIMIO_EV_PENDOWN(MIMIO_PEN_ES) => EV_KEY BIT(BTN_TOOL_FINGER) + * MIMIO_EV_PENDOWN(MIMIO_PEN_I) => EV_KEY BIT(BTN_TOOL_MOUSE) + * MIMIO_EV_PENDOWN(MIMIO_PEN_IL) => EV_KEY BIT(BTN_TOOL_LENS) + * MIMIO_EV_PENDOWN(MIMIO_PEN_IR) => EV_KEY BIT(BTN_TOOL_DOUBLETAP) + * MIMIO_EV_PENDOWN(MIMIO_PEN_EX) => EV_KEY BIT(BTN_TOOL_TRIPLETAP) + * MIMIO_EV_PENDATA => EV_ABS BIT(ABS_X), BIT(ABS_Y) + * MIMIO_EV_MEMRESET => EV_KEY BIT(BTN_0) + * MIMIO_EV_ACC(ACC_NEWPAGE) => EV_KEY BIT(BTN_1) + * MIMIO_EV_ACC(ACC_TAGPAGE) => EV_KEY BIT(BTN_2) + * MIMIO_EV_ACC(ACC_PRINTPAGE) => EV_KEY BIT(BTN_3) + * MIMIO_EV_ACC(ACC_MAXIMIZE) => EV_KEY BIT(BTN_4) + * MIMIO_EV_ACC(ACC_FINDCTLPNL) => EV_KEY BIT(BTN_5) * * open issues: - * - cold-load of data captured when mimio in standalone mode not yet - * supported; need to snoop Win32 box to see datastream for this. - * - mimio mouse not yet supported; need to snoop Win32 box to see the - * datastream for this. + * - cold-load of data captured when mimio in standalone mode not yet + * supported; need to snoop Win32 box to see datastream for this. + * - mimio mouse not yet supported; need to snoop Win32 box to see the + * datastream for this. */ + #include #include #include @@ -357,14 +356,21 @@ static int mimio_open(struct input_dev *idev) rslt = usb_submit_urb(mimio->in.urb, GFP_KERNEL); if (rslt) { dev_err(&idev->dev, "usb_submit_urb failure " - "(res = %d: %s). Not greeting.\n", - rslt, - (!urb ? "urb is NULL" : - (urb->hcpriv ? "urb->hcpriv is non-NULL" : - (!urb->complete ? "urb is not complete" : - (urb->number_of_packets <= 0 ? "urb has no packets" : - (urb->interval <= 0 ? "urb interval too small" : - "urb interval too large or some other error")))))); + "(res = %d: ", rslt); + if (!urb) + dev_err(&idev->dev, "urb is NULL"); + else if (urb->hcpriv) + dev_err(&idev->dev, "urb->hcpriv is non-NULL"); + else if (!urb->complete) + dev_err(&idev->dev, "urb is not complete"); + else if (urb->number_of_packets <= 0) + dev_err(&idev->dev, "urb has no packets"); + else if (urb->interval <= 0) + dev_err(&idev->dev, "urb interval too small"); + else + dev_err(&idev->dev, "urb interval too large " \ + "or some other error"); + dev_err(&idev->dev, "). Not greeting.\n"); rslt = -EIO; goto exit; } -- cgit v1.2.3 From e89230ec9154870a165de7e4acc411e1e7eec345 Mon Sep 17 00:00:00 2001 From: Peter Huewe Date: Tue, 15 Dec 2009 05:04:22 +0100 Subject: Staging: asus_oled: Add defines for asus vendor_id and device_id to be consistent with hid-ids.h This almost trivial patch replaces the hardcoded values for the vendor and device ids with defines, as they are used in drivers/hid/hid-ids.h For me this seems to be more consistent, however as drivers/hid/hid-ids.h is not within the default include directory I had to redefine the defines here (maybe move the hid-ids.h to include/linux ?) Signed-off-by: Peter Huewe Signed-off-by: Greg Kroah-Hartman --- drivers/staging/asus_oled/asus_oled.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/asus_oled/asus_oled.c b/drivers/staging/asus_oled/asus_oled.c index 43c57b7688ab..0c1fb0d618a5 100644 --- a/drivers/staging/asus_oled/asus_oled.c +++ b/drivers/staging/asus_oled/asus_oled.c @@ -52,6 +52,10 @@ #define ASUS_OLED_DISP_HEIGHT 32 #define ASUS_OLED_PACKET_BUF_SIZE 256 +#define USB_VENDOR_ID_ASUS 0x0b05 +#define USB_DEVICE_ID_ASUS_LCM 0x1726 +#define USB_DEVICE_ID_ASUS_LCM2 0x175b + MODULE_AUTHOR("Jakub Schmidtke, sjakub@gmail.com"); MODULE_DESCRIPTION("Asus OLED Driver v" ASUS_OLED_VERSION); MODULE_LICENSE("GPL"); @@ -85,16 +89,18 @@ struct oled_dev_desc_str { /* table of devices that work with this driver */ static struct usb_device_id id_table[] = { /* Asus G1/G2 (and variants)*/ - { USB_DEVICE(0x0b05, 0x1726) }, + { USB_DEVICE(USB_VENDOR_ID_ASUS, USB_DEVICE_ID_ASUS_LCM) }, /* Asus G50V (and possibly others - G70? G71?)*/ - { USB_DEVICE(0x0b05, 0x175b) }, + { USB_DEVICE(USB_VENDOR_ID_ASUS, USB_DEVICE_ID_ASUS_LCM2) }, { }, }; /* parameters of specific devices */ static struct oled_dev_desc_str oled_dev_desc_table[] = { - { 0x0b05, 0x1726, 128, PACK_MODE_G1, "G1/G2" }, - { 0x0b05, 0x175b, 256, PACK_MODE_G50, "G50" }, + { USB_VENDOR_ID_ASUS, USB_DEVICE_ID_ASUS_LCM, 128, PACK_MODE_G1, + "G1/G2" }, + { USB_VENDOR_ID_ASUS, USB_DEVICE_ID_ASUS_LCM2, 256, PACK_MODE_G50, + "G50" }, { }, }; -- cgit v1.2.3 From bad2239e87d73fd999a9c5d5efa5024b16046c6c Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 12 Dec 2009 23:39:41 +0100 Subject: Staging: batman-adv: replace internal logging mechanism. batman-adv used its own logging infrastructure. Replace this with standard kernel logging, printk(), with compile time and runtime options to enable/disable different debug levels. Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/Makefile | 2 +- drivers/staging/batman-adv/README | 50 ++++++- drivers/staging/batman-adv/bitarray.c | 15 +-- drivers/staging/batman-adv/device.c | 13 +- drivers/staging/batman-adv/hard-interface.c | 36 +++-- drivers/staging/batman-adv/log.c | 179 ------------------------- drivers/staging/batman-adv/log.h | 32 ----- drivers/staging/batman-adv/main.c | 24 +++- drivers/staging/batman-adv/main.h | 45 ++++--- drivers/staging/batman-adv/proc.c | 171 ++++------------------- drivers/staging/batman-adv/routing.c | 102 +++++++------- drivers/staging/batman-adv/send.c | 56 ++++---- drivers/staging/batman-adv/soft-interface.c | 3 +- drivers/staging/batman-adv/translation-table.c | 22 +-- drivers/staging/batman-adv/vis.c | 12 +- 15 files changed, 242 insertions(+), 520 deletions(-) delete mode 100644 drivers/staging/batman-adv/log.c delete mode 100644 drivers/staging/batman-adv/log.h (limited to 'drivers') diff --git a/drivers/staging/batman-adv/Makefile b/drivers/staging/batman-adv/Makefile index 02da87134fce..64bdb7828e99 100644 --- a/drivers/staging/batman-adv/Makefile +++ b/drivers/staging/batman-adv/Makefile @@ -19,4 +19,4 @@ # obj-m += batman-adv.o -batman-adv-objs := main.o proc.o send.o routing.o soft-interface.o device.o translation-table.o bitarray.o hash.o ring_buffer.o vis.o hard-interface.o aggregation.o log.o +batman-adv-objs := main.o proc.o send.o routing.o soft-interface.o device.o translation-table.o bitarray.o hash.o ring_buffer.o vis.o hard-interface.o aggregation.o diff --git a/drivers/staging/batman-adv/README b/drivers/staging/batman-adv/README index 3aaf393ebaa7..6c624820edd1 100644 --- a/drivers/staging/batman-adv/README +++ b/drivers/staging/batman-adv/README @@ -1,4 +1,4 @@ -[state: 07-11-2009] +[state: 13-11-2009] BATMAN-ADV ---------- @@ -96,6 +96,54 @@ To deactivate batman, do: # echo "" > /proc/net/batman-adv/interfaces +LOGGING/DEBUGGING +----------------- + +All error messages, warnings and information messages are sent to the +kernel log. Depending on your operating system distribution this can be +read in one of a number of ways. Try using the commands: dmesg, +logread, or looking in the files /var/log/kern.log or +/var/log/syslog. All batman-adv messages are prefixed with +"batman-adv:" So to see just these messages try + +dmesg | grep batman-adv + +When investigating problems with your mesh network it is sometimes +necessary to see more detail debug messages. This must be enabled when +compiling the batman-adv module. When building batman-adv as part of +kernel, use "make menuconfig" and enable the option +"B.A.T.M.A.N. debugging". When compiling outside of the kernel tree it +is necessary to edit the file Makefile.kbuild and uncomment the line + +#EXTRA_CFLAGS += -DCONFIG_BATMAN_DEBUG + +The additional debug output is by default disabled. It can be enabled +either at kernel modules load time or during run time. To enable debug +output at module load time, add the module parameter debug=. + can take one of four values. + +0 - All debug output disabled +1 - Enable messages related to routing / flooding / broadcasting +2 - Enable route or hna added / changed / deleted +3 - Enable all messages + +e.g. + +modprobe batman-adv debug=2 + +will load the module and enable debug messages for when routes or HNAs +change. + +The debug output can also be changed at runtime using the file +/sys/module/batman-adv/parameters/debug. e.g. + +echo 2 > /sys/module/batman-adv/parameters/debug + +enables debug messages for when routes or HNAs + +The debug output is sent to the kernel logs. So try dmesg, logread etc +to see the debug messages. + BATCTL ------ diff --git a/drivers/staging/batman-adv/bitarray.c b/drivers/staging/batman-adv/bitarray.c index 3c67f5f42b2b..212eef93afe4 100644 --- a/drivers/staging/batman-adv/bitarray.c +++ b/drivers/staging/batman-adv/bitarray.c @@ -21,7 +21,6 @@ #include "main.h" #include "bitarray.h" -#include "log.h" /* returns true if the corresponding bit in the given seq_bits indicates true * and curr_seqno is within range of last_seqno */ @@ -80,8 +79,8 @@ void bit_shift(TYPE_OF_WORD *seq_bits, int32_t n) * from. * * left is high, right is low: FEDC BA98 7654 3210 - * ^^ ^^ - * vvvv + * ^^ ^^ + * vvvv * ^^^^ = from, vvvvv =to, we'd have word_num==1 and * word_offset==WORD_BIT_SIZE/2 ????? in this example. * (=24 bits) @@ -133,13 +132,13 @@ char bit_get_packet(TYPE_OF_WORD *seq_bits, int16_t seq_num_diff, (seq_num_diff < -TQ_LOCAL_WINDOW_SIZE)) { if (seq_num_diff > TQ_LOCAL_WINDOW_SIZE) - debug_log(LOG_TYPE_BATMAN, - "We missed a lot of packets (%i) !\n", - seq_num_diff-1); + bat_dbg(DBG_BATMAN, + "We missed a lot of packets (%i) !\n", + seq_num_diff-1); if (-seq_num_diff > TQ_LOCAL_WINDOW_SIZE) - debug_log(LOG_TYPE_BATMAN, - "Other host probably restarted !\n"); + bat_dbg(DBG_BATMAN, + "Other host probably restarted !\n"); for (i = 0; i < NUM_WORDS; i++) seq_bits[i] = 0; diff --git a/drivers/staging/batman-adv/device.c b/drivers/staging/batman-adv/device.c index 1e7d1f88674f..12f2de98b3d0 100644 --- a/drivers/staging/batman-adv/device.c +++ b/drivers/staging/batman-adv/device.c @@ -21,7 +21,6 @@ #include "main.h" #include "device.h" -#include "log.h" #include "send.h" #include "types.h" #include "hash.h" @@ -60,7 +59,7 @@ int bat_device_setup(void) /* register our device - kernel assigns a free major number */ tmp_major = register_chrdev(0, DRIVER_DEVICE, &fops); if (tmp_major < 0) { - debug_log(LOG_TYPE_WARN, "Registering the character device failed with %d\n", + printk(KERN_ERR "batman-adv:Registering the character device failed with %d\n", tmp_major); return 0; } @@ -68,7 +67,7 @@ int bat_device_setup(void) batman_class = class_create(THIS_MODULE, "batman-adv"); if (IS_ERR(batman_class)) { - debug_log(LOG_TYPE_WARN, "Could not register class 'batman-adv' \n"); + printk(KERN_ERR "batman-adv:Could not register class 'batman-adv' \n"); return 0; } @@ -111,7 +110,7 @@ int bat_device_open(struct inode *inode, struct file *file) } if (device_client_hash[i] != device_client) { - debug_log(LOG_TYPE_WARN, "Error - can't add another packet client: maximum number of clients reached \n"); + printk(KERN_ERR "batman-adv:Error - can't add another packet client: maximum number of clients reached \n"); kfree(device_client); return -EXFULL; } @@ -208,7 +207,7 @@ ssize_t bat_device_write(struct file *file, const char __user *buff, struct batman_if *batman_if; if (len < sizeof(struct icmp_packet)) { - debug_log(LOG_TYPE_NOTICE, "Error - can't send packet from char device: invalid packet size\n"); + printk(KERN_DEBUG "batman-adv:Error - can't send packet from char device: invalid packet size\n"); return -EINVAL; } @@ -219,12 +218,12 @@ ssize_t bat_device_write(struct file *file, const char __user *buff, return -EFAULT; if (icmp_packet.packet_type != BAT_ICMP) { - debug_log(LOG_TYPE_NOTICE, "Error - can't send packet from char device: got bogus packet type (expected: BAT_ICMP)\n"); + printk(KERN_DEBUG "batman-adv:Error - can't send packet from char device: got bogus packet type (expected: BAT_ICMP)\n"); return -EINVAL; } if (icmp_packet.msg_type != ECHO_REQUEST) { - debug_log(LOG_TYPE_NOTICE, "Error - can't send packet from char device: got bogus message type (expected: ECHO_REQUEST)\n"); + printk(KERN_DEBUG "batman-adv:Error - can't send packet from char device: got bogus message type (expected: ECHO_REQUEST)\n"); return -EINVAL; } diff --git a/drivers/staging/batman-adv/hard-interface.c b/drivers/staging/batman-adv/hard-interface.c index 5ea35da5ee7a..e9cb977d0016 100644 --- a/drivers/staging/batman-adv/hard-interface.c +++ b/drivers/staging/batman-adv/hard-interface.c @@ -21,7 +21,6 @@ #include "main.h" #include "hard-interface.h" -#include "log.h" #include "soft-interface.h" #include "send.h" #include "translation-table.h" @@ -87,9 +86,9 @@ static void check_known_mac_addr(uint8_t *addr) continue; addr_to_string(mac_string, addr); - debug_log(LOG_TYPE_WARN, "The newly added mac address (%s) already exists on: %s\n", - mac_string, batman_if->dev); - debug_log(LOG_TYPE_WARN, "It is strongly recommended to keep mac addresses unique to avoid problems!\n"); + printk(KERN_WARNING "batman-adv:The newly added mac address (%s) already exists on: %s\n", + mac_string, batman_if->dev); + printk(KERN_WARNING "batman-adv:It is strongly recommended to keep mac addresses unique to avoid problems!\n"); } rcu_read_unlock(); } @@ -171,8 +170,8 @@ void hardif_deactivate_interface(struct batman_if *batman_if) batman_if->if_active = IF_INACTIVE; active_ifs--; - debug_log(LOG_TYPE_NOTICE, "Interface deactivated: %s\n", - batman_if->dev); + printk(KERN_INFO "batman-adv:Interface deactivated: %s\n", + batman_if->dev); } /* (re)activate given interface. */ @@ -197,7 +196,7 @@ static void hardif_activate_interface(struct batman_if *batman_if) &batman_if->raw_sock); if (retval < 0) { - debug_log(LOG_TYPE_WARN, "Can't create raw socket: %i\n", + printk(KERN_ERR "batman-adv:Can't create raw socket: %i\n", retval); goto sock_err; } @@ -210,7 +209,7 @@ static void hardif_activate_interface(struct batman_if *batman_if) (struct sockaddr *)&bind_addr, sizeof(bind_addr)); if (retval < 0) { - debug_log(LOG_TYPE_WARN, "Can't create bind raw socket: %i\n", + printk(KERN_ERR "batman-adv:Can't create bind raw socket: %i\n", retval); goto bind_err; } @@ -235,8 +234,8 @@ static void hardif_activate_interface(struct batman_if *batman_if) if (batman_if->if_num == 0) set_main_if_addr(batman_if->net_dev->dev_addr); - debug_log(LOG_TYPE_NOTICE, "Interface activated: %s\n", - batman_if->dev); + printk(KERN_INFO "batman-adv:Interface activated: %s\n", + batman_if->dev); return; @@ -290,7 +289,7 @@ static int resize_orig(struct orig_node *orig_node, int if_num) data_ptr = kmalloc((if_num + 1) * sizeof(TYPE_OF_WORD) * NUM_WORDS, GFP_ATOMIC); if (!data_ptr) { - debug_log(LOG_TYPE_WARN, "Can't resize orig: out of memory\n"); + printk(KERN_ERR "batman-adv:Can't resize orig: out of memory\n"); return -1; } @@ -301,7 +300,7 @@ static int resize_orig(struct orig_node *orig_node, int if_num) data_ptr = kmalloc((if_num + 1) * sizeof(uint8_t), GFP_ATOMIC); if (!data_ptr) { - debug_log(LOG_TYPE_WARN, "Can't resize orig: out of memory\n"); + printk(KERN_ERR "batman-adv:Can't resize orig: out of memory\n"); return -1; } @@ -324,7 +323,7 @@ int hardif_add_interface(char *dev, int if_num) batman_if = kmalloc(sizeof(struct batman_if), GFP_KERNEL); if (!batman_if) { - debug_log(LOG_TYPE_WARN, "Can't add interface (%s): out of memory\n", dev); + printk(KERN_ERR "batman-adv:Can't add interface (%s): out of memory\n", dev); return -1; } @@ -339,7 +338,7 @@ int hardif_add_interface(char *dev, int if_num) batman_if->packet_buff = kmalloc(batman_if->packet_len, GFP_KERNEL); if (!batman_if->packet_buff) { - debug_log(LOG_TYPE_WARN, "Can't add interface packet (%s): out of memory\n", dev); + printk(KERN_ERR "batman-adv:Can't add interface packet (%s): out of memory\n", dev); goto out; } @@ -348,7 +347,7 @@ int hardif_add_interface(char *dev, int if_num) batman_if->if_active = IF_INACTIVE; INIT_RCU_HEAD(&batman_if->rcu); - debug_log(LOG_TYPE_NOTICE, "Adding interface: %s\n", dev); + printk(KERN_INFO "batman-adv:Adding interface: %s\n", dev); avail_ifs++; INIT_LIST_HEAD(&batman_if->list); @@ -389,7 +388,7 @@ int hardif_add_interface(char *dev, int if_num) spin_unlock(&orig_hash_lock); if (!hardif_is_interface_up(batman_if->dev)) - debug_log(LOG_TYPE_WARN, "Not using interface %s (retrying later): interface not active\n", batman_if->dev); + printk(KERN_ERR "batman-adv:Not using interface %s (retrying later): interface not active\n", batman_if->dev); else hardif_activate_interface(batman_if); @@ -413,7 +412,7 @@ char hardif_get_active_if_num(void) } static int hard_if_event(struct notifier_block *this, - unsigned long event, void *ptr) + unsigned long event, void *ptr) { struct net_device *dev = (struct net_device *)ptr; struct batman_if *batman_if = get_batman_if_by_name(dev->name); @@ -436,7 +435,6 @@ static int hard_if_event(struct notifier_block *this, break; /* NETDEV_CHANGEADDR - mac address change - what are we doing here ? */ default: - /* debug_log(LOG_TYPE_CRIT, "hard_if_event: %s %i\n", dev->name, event); */ break; }; @@ -447,5 +445,5 @@ out: } struct notifier_block hard_if_notifier = { - .notifier_call = hard_if_event, + .notifier_call = hard_if_event, }; diff --git a/drivers/staging/batman-adv/log.c b/drivers/staging/batman-adv/log.c deleted file mode 100644 index f37c7f01a9f5..000000000000 --- a/drivers/staging/batman-adv/log.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (C) 2007-2009 B.A.T.M.A.N. contributors: - * - * Marek Lindner, Simon Wunderlich - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of version 2 of the GNU General Public - * License as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * - */ - -#include "main.h" -#include "log.h" - -#define LOG_BUF_MASK (log_buf_len-1) -#define LOG_BUF(idx) (log_buf[(idx) & LOG_BUF_MASK]) - -static char log_buf[LOG_BUF_LEN]; -static int log_buf_len = LOG_BUF_LEN; -static unsigned long log_start; -static unsigned long log_end; -uint8_t log_level; - -static DEFINE_SPINLOCK(logbuf_lock); - -const struct file_operations proc_log_operations = { - .open = log_open, - .release = log_release, - .read = log_read, - .write = log_write, - .poll = log_poll, -}; - -static DECLARE_WAIT_QUEUE_HEAD(log_wait); - -static void emit_log_char(char c) -{ - LOG_BUF(log_end) = c; - log_end++; - - if (log_end - log_start > log_buf_len) - log_start = log_end - log_buf_len; -} - -static int fdebug_log(char *fmt, ...) -{ - int printed_len; - char *p; - va_list args; - static char debug_log_buf[256]; - unsigned long flags; - - spin_lock_irqsave(&logbuf_lock, flags); - va_start(args, fmt); - printed_len = vscnprintf(debug_log_buf, sizeof(debug_log_buf), fmt, - args); - va_end(args); - - for (p = debug_log_buf; *p != 0; p++) - emit_log_char(*p); - - spin_unlock_irqrestore(&logbuf_lock, flags); - - wake_up(&log_wait); - - return 0; -} - -int debug_log(int type, char *fmt, ...) -{ - va_list args; - int retval = 0; - char tmp_log_buf[256]; - - /* only critical information get into the official kernel log */ - if (type == LOG_TYPE_CRIT) { - va_start(args, fmt); - vscnprintf(tmp_log_buf, sizeof(tmp_log_buf), fmt, args); - printk(KERN_ERR "batman-adv: %s", tmp_log_buf); - va_end(args); - } - - if ((type == LOG_TYPE_CRIT) || (log_level & type)) { - va_start(args, fmt); - vscnprintf(tmp_log_buf, sizeof(tmp_log_buf), fmt, args); - fdebug_log("[%10u] %s", (jiffies / HZ), tmp_log_buf); - va_end(args); - } - - return retval; -} - -int log_open(struct inode *inode, struct file *file) -{ - inc_module_count(); - return 0; -} - -int log_release(struct inode *inode, struct file *file) -{ - dec_module_count(); - return 0; -} - -ssize_t log_read(struct file *file, char __user *buf, size_t count, - loff_t *ppos) -{ - int error, i = 0; - char c; - unsigned long flags; - - if ((file->f_flags & O_NONBLOCK) && !(log_end - log_start)) - return -EAGAIN; - - if ((!buf) || (count < 0)) - return -EINVAL; - - if (count == 0) - return 0; - - if (!access_ok(VERIFY_WRITE, buf, count)) - return -EFAULT; - - error = wait_event_interruptible(log_wait, (log_start - log_end)); - - if (error) - return error; - - spin_lock_irqsave(&logbuf_lock, flags); - - while ((!error) && (log_start != log_end) && (i < count)) { - c = LOG_BUF(log_start); - - log_start++; - - spin_unlock_irqrestore(&logbuf_lock, flags); - - error = __put_user(c, buf); - - spin_lock_irqsave(&logbuf_lock, flags); - - buf++; - i++; - - } - - spin_unlock_irqrestore(&logbuf_lock, flags); - - if (!error) - return i; - - return error; -} - -ssize_t log_write(struct file *file, const char __user *buf, size_t count, - loff_t *ppos) -{ - return count; -} - -unsigned int log_poll(struct file *file, poll_table *wait) -{ - poll_wait(file, &log_wait, wait); - - if (log_end - log_start) - return POLLIN | POLLRDNORM; - - return 0; -} diff --git a/drivers/staging/batman-adv/log.h b/drivers/staging/batman-adv/log.h deleted file mode 100644 index 780e3abb48f9..000000000000 --- a/drivers/staging/batman-adv/log.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2007-2009 B.A.T.M.A.N. contributors: - * - * Marek Lindner, Simon Wunderlich - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of version 2 of the GNU General Public - * License as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * - */ - -extern const struct file_operations proc_log_operations; -extern uint8_t log_level; - -int debug_log(int type, char *fmt, ...); -int log_open(struct inode *inode, struct file *file); -int log_release(struct inode *inode, struct file *file); -ssize_t log_read(struct file *file, char __user *buf, size_t count, - loff_t *ppos); -ssize_t log_write(struct file *file, const char __user *buf, size_t count, - loff_t *ppos); -unsigned int log_poll(struct file *file, poll_table *wait); diff --git a/drivers/staging/batman-adv/main.c b/drivers/staging/batman-adv/main.c index bb89bfc5dda6..4b93a5d33cf9 100644 --- a/drivers/staging/batman-adv/main.c +++ b/drivers/staging/batman-adv/main.c @@ -21,7 +21,6 @@ #include "main.h" #include "proc.h" -#include "log.h" #include "routing.h" #include "send.h" #include "soft-interface.h" @@ -57,6 +56,17 @@ atomic_t module_state; struct workqueue_struct *bat_event_workqueue; +#ifdef CONFIG_BATMAN_DEBUG +int debug; + +module_param(debug, int, 0644); + +int bat_debug_type(int type) +{ + return debug & type; +} +#endif + int init_module(void) { int retval; @@ -90,21 +100,21 @@ int init_module(void) interface_setup); if (!soft_device) { - debug_log(LOG_TYPE_CRIT, "Unable to allocate the batman interface\n"); + printk(KERN_ERR "batman-adv:Unable to allocate the batman interface\n"); goto end; } retval = register_netdev(soft_device); if (retval < 0) { - debug_log(LOG_TYPE_CRIT, "Unable to register the batman interface: %i\n", retval); + printk(KERN_ERR "batman-adv:Unable to register the batman interface: %i\n", retval); goto free_soft_device; } register_netdevice_notifier(&hard_if_notifier); - debug_log(LOG_TYPE_CRIT, "B.A.T.M.A.N. advanced %s%s (compatibility version %i) loaded \n", - SOURCE_VERSION, REVISION_VERSION_STR, COMPAT_VERSION); + printk(KERN_INFO "batman-adv:B.A.T.M.A.N. advanced %s%s (compatibility version %i) loaded \n", + SOURCE_VERSION, REVISION_VERSION_STR, COMPAT_VERSION); return 0; @@ -156,7 +166,7 @@ void activate_module(void) kthread_task = kthread_run(packet_recv_thread, NULL, "batman-adv"); if (IS_ERR(kthread_task)) { - debug_log(LOG_TYPE_CRIT, "Unable to start packet receive thread\n"); + printk(KERN_ERR "batman-adv:Unable to start packet receive thread\n"); kthread_task = NULL; } } @@ -166,7 +176,7 @@ void activate_module(void) goto end; err: - debug_log(LOG_TYPE_CRIT, "Unable to allocate memory for mesh information structures: out of mem ?\n"); + printk(KERN_ERR "batman-adv:Unable to allocate memory for mesh information structures: out of mem ?\n"); shutdown_module(); end: return; diff --git a/drivers/staging/batman-adv/main.h b/drivers/staging/batman-adv/main.h index facb6b79ee52..6907cacf8c41 100644 --- a/drivers/staging/batman-adv/main.h +++ b/drivers/staging/batman-adv/main.h @@ -33,16 +33,16 @@ #define TQ_MAX_VALUE 255 #define JITTER 20 -#define TTL 50 /* Time To Live of broadcast messages */ -#define MAX_ADDR 16 /* number of interfaces which can be added to +#define TTL 50 /* Time To Live of broadcast messages */ +#define MAX_ADDR 16 /* number of interfaces which can be added to * batman. */ -#define PURGE_TIMEOUT 200000 /* purge originators after time in ms if no +#define PURGE_TIMEOUT 200000 /* purge originators after time in ms if no * valid packet comes in -> TODO: check * influence on TQ_LOCAL_WINDOW_SIZE */ #define LOCAL_HNA_TIMEOUT 3600000 -#define TQ_LOCAL_WINDOW_SIZE 64 /* sliding packet range of received originator +#define TQ_LOCAL_WINDOW_SIZE 64 /* sliding packet range of received originator * messages in squence numbers (should be a * multiple of our word size) */ #define TQ_GLOBAL_WINDOW_SIZE 5 @@ -69,24 +69,27 @@ /* - * Logging + * Debug Messages */ -#define LOG_TYPE_CRIT 0 /* highest priority for fatal errors such as - * blocked sockets / failed packet delivery / - * programming errors */ -#define LOG_TYPE_WARN 1 /* warnings for small errors like wrong user - * input / damaged packets / etc */ -#define LOG_TYPE_NOTICE 2 /* notice information for new interfaces / - * changed settings / new originators / etc */ -#define LOG_TYPE_BATMAN 4 /* all messages related to routing / flooding / - * broadcasting / etc */ -#define LOG_TYPE_ROUTES 8 /* route or hna added / changed / deleted */ -#define LOG_TYPE_CRIT_NAME "critical" -#define LOG_TYPE_WARN_NAME "warnings" -#define LOG_TYPE_NOTICE_NAME "notices" -#define LOG_TYPE_BATMAN_NAME "batman" -#define LOG_TYPE_ROUTES_NAME "routes" +#define DBG_BATMAN 1 /* all messages related to routing / flooding / + * broadcasting / etc */ +#define DBG_ROUTES 2 /* route or hna added / changed / deleted */ + +#ifdef CONFIG_BATMAN_DEBUG +extern int debug; + +extern int bat_debug_type(int type); +#define bat_dbg(type, fmt, arg...) do { \ + if (bat_debug_type(type)) \ + printk(KERN_DEBUG "batman-adv:" fmt, ## arg); \ + } \ + while (0) +#else /* !CONFIG_BATMAN_DEBUG */ +#define bat_dbg(type, fmt, arg...) do { \ + } \ + while (0) +#endif /* * Vis @@ -147,5 +150,3 @@ int choose_orig(void *data, int32_t size); int is_my_mac(uint8_t *addr); int is_bcast(uint8_t *addr); int is_mcast(uint8_t *addr); - - diff --git a/drivers/staging/batman-adv/proc.c b/drivers/staging/batman-adv/proc.c index aac3df7f13fb..ed4c73484d7d 100644 --- a/drivers/staging/batman-adv/proc.c +++ b/drivers/staging/batman-adv/proc.c @@ -21,7 +21,6 @@ #include "main.h" #include "proc.h" -#include "log.h" #include "routing.h" #include "translation-table.h" #include "hard-interface.h" @@ -34,7 +33,6 @@ static uint8_t vis_format = DOT_DRAW; static struct proc_dir_entry *proc_batman_dir, *proc_interface_file; static struct proc_dir_entry *proc_orig_interval_file, *proc_originators_file; -static struct proc_dir_entry *proc_log_file, *proc_log_level_file; static struct proc_dir_entry *proc_transt_local_file; static struct proc_dir_entry *proc_transt_global_file; static struct proc_dir_entry *proc_vis_file, *proc_vis_format_file; @@ -77,8 +75,7 @@ static ssize_t proc_interfaces_write(struct file *instance, return -ENOMEM; if (count > IFNAMSIZ - 1) { - debug_log(LOG_TYPE_WARN, - "Can't add interface: device name is too long\n"); + printk(KERN_WARNING "batman-adv:Can't add interface: device name is too long\n"); goto end; } @@ -105,7 +102,7 @@ static ssize_t proc_interfaces_write(struct file *instance, rcu_read_lock(); list_for_each_entry_rcu(batman_if, &if_list, list) { if (strncmp(batman_if->dev, if_string, count) == 0) { - debug_log(LOG_TYPE_WARN, "Given interface is already active: %s\n", if_string); + printk(KERN_ERR "batman-adv:Given interface is already active: %s\n", if_string); rcu_read_unlock(); goto end; @@ -162,20 +159,18 @@ static ssize_t proc_orig_interval_write(struct file *file, retval = strict_strtoul(interval_string, 10, &originator_interval_tmp); if (retval) { - debug_log(LOG_TYPE_WARN, "New originator interval invalid\n"); + printk(KERN_ERR "batman-adv:New originator interval invalid\n"); goto end; } if (originator_interval_tmp <= JITTER * 2) { - debug_log(LOG_TYPE_WARN, - "New originator interval too small: %i (min: %i)\n", - originator_interval_tmp, JITTER * 2); + printk(KERN_WARNING "batman-adv:New originator interval too small: %li (min: %i)\n", + originator_interval_tmp, JITTER * 2); goto end; } - debug_log(LOG_TYPE_NOTICE, - "Changing originator interval from: %i to: %i\n", - atomic_read(&originator_interval), originator_interval_tmp); + printk(KERN_INFO "batman-adv:Changing originator interval from: %i to: %li\n", + atomic_read(&originator_interval), originator_interval_tmp); atomic_set(&originator_interval, originator_interval_tmp); @@ -235,7 +230,7 @@ static int proc_originators_read(struct seq_file *seq, void *offset) addr_to_string(orig_str, orig_node->orig); addr_to_string(router_str, orig_node->router->addr); - seq_printf(seq, "%-17s (%3i) %17s [%10s]:", + seq_printf(seq, "%-17s (%3i) %17s [%10s]:", orig_str, orig_node->router->tq_avg, router_str, orig_node->router->if_incoming->dev); @@ -263,84 +258,6 @@ static int proc_originators_open(struct inode *inode, struct file *file) return single_open(file, proc_originators_read, NULL); } -static int proc_log_level_read(struct seq_file *seq, void *offset) -{ - - seq_printf(seq, "[x] %s (%d)\n", LOG_TYPE_CRIT_NAME, LOG_TYPE_CRIT); - seq_printf(seq, "[%c] %s (%d)\n", - (LOG_TYPE_WARN & log_level) ? 'x' : ' ', - LOG_TYPE_WARN_NAME, LOG_TYPE_WARN); - seq_printf(seq, "[%c] %s (%d)\n", - (LOG_TYPE_NOTICE & log_level) ? 'x' : ' ', - LOG_TYPE_NOTICE_NAME, LOG_TYPE_NOTICE); - seq_printf(seq, "[%c] %s (%d)\n", - (LOG_TYPE_BATMAN & log_level) ? 'x' : ' ', - LOG_TYPE_BATMAN_NAME, LOG_TYPE_BATMAN); - seq_printf(seq, "[%c] %s (%d)\n", - (LOG_TYPE_ROUTES & log_level) ? 'x' : ' ', - LOG_TYPE_ROUTES_NAME, LOG_TYPE_ROUTES); - return 0; -} - -static int proc_log_level_open(struct inode *inode, struct file *file) -{ - return single_open(file, proc_log_level_read, NULL); -} - -static ssize_t proc_log_level_write(struct file *instance, - const char __user *userbuffer, - size_t count, loff_t *data) -{ - char *log_level_string, *tokptr, *cp; - int finished, not_copied = 0; - unsigned long log_level_tmp = 0; - - log_level_string = kmalloc(count, GFP_KERNEL); - - if (!log_level_string) - return -ENOMEM; - - not_copied = copy_from_user(log_level_string, userbuffer, count); - log_level_string[count - not_copied - 1] = 0; - - if (strict_strtoul(log_level_string, 10, &log_level_tmp) < 0) { - /* was not a number, doing textual parsing */ - log_level_tmp = 0; - tokptr = log_level_string; - - for (cp = log_level_string, finished = 0; !finished; cp++) { - switch (*cp) { - case 0: - finished = 1; - case ' ': - case '\n': - case '\t': - *cp = 0; - /* compare */ - if (strcmp(tokptr, LOG_TYPE_WARN_NAME) == 0) - log_level_tmp |= LOG_TYPE_WARN; - if (strcmp(tokptr, LOG_TYPE_NOTICE_NAME) == 0) - log_level_tmp |= LOG_TYPE_NOTICE; - if (strcmp(tokptr, LOG_TYPE_BATMAN_NAME) == 0) - log_level_tmp |= LOG_TYPE_BATMAN; - if (strcmp(tokptr, LOG_TYPE_ROUTES_NAME) == 0) - log_level_tmp |= LOG_TYPE_ROUTES; - tokptr = cp + 1; - break; - default: - ; - } - } - } - - debug_log(LOG_TYPE_CRIT, "Changing log_level from: %i to: %i\n", - log_level, log_level_tmp); - log_level = log_level_tmp; - - kfree(log_level_string); - return count; -} - static int proc_transt_local_read(struct seq_file *seq, void *offset) { char *buf; @@ -412,7 +329,7 @@ static void proc_vis_insert_interface(const uint8_t *interface, bool primary) { /* Did we get an empty list? (then insert imediately) */ - if(*if_entry == NULL) { + if (*if_entry == NULL) { *if_entry = kmalloc(sizeof(struct vis_if_list), GFP_KERNEL); if (*if_entry == NULL) return; @@ -585,14 +502,14 @@ static ssize_t proc_vis_write(struct file *file, const char __user * buffer, vis_mode_string[count - not_copied - 1] = 0; if (strcmp(vis_mode_string, "client") == 0) { - debug_log(LOG_TYPE_NOTICE, "Setting VIS mode to client\n"); + printk(KERN_INFO "batman-adv:Setting VIS mode to client\n"); vis_set_mode(VIS_TYPE_CLIENT_UPDATE); } else if (strcmp(vis_mode_string, "server") == 0) { - debug_log(LOG_TYPE_NOTICE, "Setting VIS mode to server\n"); + printk(KERN_INFO "batman-adv:Setting VIS mode to server\n"); vis_set_mode(VIS_TYPE_SERVER_SYNC); } else - debug_log(LOG_TYPE_WARN, "Unknown VIS mode: %s\n", - vis_mode_string); + printk(KERN_ERR "batman-adv:Unknown VIS mode: %s\n", + vis_mode_string); kfree(vis_mode_string); return count; @@ -637,16 +554,16 @@ static ssize_t proc_vis_format_write(struct file *file, vis_format_string[count - not_copied - 1] = 0; if (strcmp(vis_format_string, VIS_FORMAT_DD_NAME) == 0) { - debug_log(LOG_TYPE_NOTICE, "Setting VIS output format to: %s\n", - VIS_FORMAT_DD_NAME); + printk(KERN_INFO "batman-adv:Setting VIS output format to: %s\n", + VIS_FORMAT_DD_NAME); vis_format = DOT_DRAW; } else if (strcmp(vis_format_string, VIS_FORMAT_JSON_NAME) == 0) { - debug_log(LOG_TYPE_NOTICE, "Setting VIS output format to: %s\n", - VIS_FORMAT_JSON_NAME); + printk(KERN_INFO "batman-adv:Setting VIS output format to: %s\n", + VIS_FORMAT_JSON_NAME); vis_format = JSON; } else - debug_log(LOG_TYPE_WARN, "Unknown VIS output format: %s\n", - vis_format_string); + printk(KERN_ERR "batman-adv:Unknown VIS output format: %s\n", + vis_format_string); kfree(vis_format_string); return count; @@ -677,16 +594,16 @@ static ssize_t proc_aggr_write(struct file *file, const char __user *buffer, strict_strtoul(aggr_string, 10, &aggregation_enabled_tmp); if ((aggregation_enabled_tmp != 0) && (aggregation_enabled_tmp != 1)) { - debug_log(LOG_TYPE_WARN, "Aggregation can only be enabled (1) or disabled (0), given value: %li\n", aggregation_enabled_tmp); + printk(KERN_ERR "batman-adv:Aggregation can only be enabled (1) or disabled (0), given value: %li\n", aggregation_enabled_tmp); goto end; } - debug_log(LOG_TYPE_NOTICE, "Changing aggregation from: %s (%i) to: %s (%li)\n", - (atomic_read(&aggregation_enabled) == 1 ? - "enabled" : "disabled"), - atomic_read(&aggregation_enabled), - (aggregation_enabled_tmp == 1 ? "enabled" : "disabled"), - aggregation_enabled_tmp); + printk(KERN_INFO "batman-adv:Changing aggregation from: %s (%i) to: %s (%li)\n", + (atomic_read(&aggregation_enabled) == 1 ? + "enabled" : "disabled"), + atomic_read(&aggregation_enabled), + (aggregation_enabled_tmp == 1 ? "enabled" : "disabled"), + aggregation_enabled_tmp); atomic_set(&aggregation_enabled, (unsigned)aggregation_enabled_tmp); end: @@ -760,15 +677,6 @@ static const struct file_operations proc_transt_global_fops = { .release = single_release, }; -static const struct file_operations proc_log_level_fops = { - .owner = THIS_MODULE, - .open = proc_log_level_open, - .read = seq_read, - .write = proc_log_level_write, - .llseek = seq_lseek, - .release = single_release, -}; - static const struct file_operations proc_interfaces_fops = { .owner = THIS_MODULE, .open = proc_interfaces_open, @@ -795,12 +703,6 @@ void cleanup_procfs(void) if (proc_transt_local_file) remove_proc_entry(PROC_FILE_TRANST_LOCAL, proc_batman_dir); - if (proc_log_file) - remove_proc_entry(PROC_FILE_LOG, proc_batman_dir); - - if (proc_log_level_file) - remove_proc_entry(PROC_FILE_LOG_LEVEL, proc_batman_dir); - if (proc_originators_file) remove_proc_entry(PROC_FILE_ORIGINATORS, proc_batman_dir); @@ -862,17 +764,6 @@ int setup_procfs(void) return -EFAULT; } - proc_log_level_file = create_proc_entry(PROC_FILE_LOG_LEVEL, - S_IWUSR | S_IRUGO, - proc_batman_dir); - if (proc_log_level_file) { - proc_log_level_file->proc_fops = &proc_log_level_fops; - } else { - printk(KERN_ERR "batman-adv: Registering the '/proc/net/%s/%s' file failed\n", PROC_ROOT_DIR, PROC_FILE_LOG_LEVEL); - cleanup_procfs(); - return -EFAULT; - } - proc_originators_file = create_proc_entry(PROC_FILE_ORIGINATORS, S_IRUGO, proc_batman_dir); if (proc_originators_file) { @@ -883,16 +774,6 @@ int setup_procfs(void) return -EFAULT; } - proc_log_file = create_proc_entry(PROC_FILE_LOG, - S_IRUGO, proc_batman_dir); - if (proc_log_file) { - proc_log_file->proc_fops = &proc_log_operations; - } else { - printk(KERN_ERR "batman-adv: Registering the '/proc/net/%s/%s' file failed\n", PROC_FILE_LOG, PROC_FILE_GATEWAYS); - cleanup_procfs(); - return -EFAULT; - } - proc_transt_local_file = create_proc_entry(PROC_FILE_TRANST_LOCAL, S_IRUGO, proc_batman_dir); if (proc_transt_local_file) { diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index 4a14c363ac2b..1f42d4167422 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -25,7 +25,6 @@ #include "main.h" #include "routing.h" -#include "log.h" #include "send.h" #include "soft-interface.h" #include "hard-interface.h" @@ -88,7 +87,7 @@ static struct neigh_node *create_neighbor(struct orig_node *orig_node, struct or { struct neigh_node *neigh_node; - debug_log(LOG_TYPE_BATMAN, "Creating new last-hop neighbour of originator\n"); + bat_dbg(DBG_BATMAN, "Creating new last-hop neighbour of originator\n"); neigh_node = kmalloc(sizeof(struct neigh_node), GFP_ATOMIC); memset(neigh_node, 0, sizeof(struct neigh_node)); @@ -136,7 +135,7 @@ static struct orig_node *get_orig_node(uint8_t *addr) return orig_node; addr_to_string(orig_str, addr); - debug_log(LOG_TYPE_BATMAN, "Creating new originator: %s \n", orig_str); + bat_dbg(DBG_BATMAN, "Creating new originator: %s \n", orig_str); orig_node = kmalloc(sizeof(struct orig_node), GFP_ATOMIC); memset(orig_node, 0, sizeof(struct orig_node)); @@ -159,7 +158,7 @@ static struct orig_node *get_orig_node(uint8_t *addr) swaphash = hash_resize(orig_hash, orig_hash->size * 2); if (swaphash == NULL) - debug_log(LOG_TYPE_CRIT, "Couldn't resize orig hash table \n"); + printk(KERN_ERR "batman-adv:Couldn't resize orig hash table \n"); else orig_hash = swaphash; } @@ -196,15 +195,15 @@ static void update_routes(struct orig_node *orig_node, struct neigh_node *neigh_ /* route deleted */ if ((orig_node->router != NULL) && (neigh_node == NULL)) { - - debug_log(LOG_TYPE_ROUTES, "Deleting route towards: %s\n", orig_str); + bat_dbg(DBG_ROUTES, "Deleting route towards: %s\n", + orig_str); hna_global_del_orig(orig_node, "originator timed out"); /* route added */ } else if ((orig_node->router == NULL) && (neigh_node != NULL)) { addr_to_string(neigh_str, neigh_node->addr); - debug_log(LOG_TYPE_ROUTES, "Adding route towards: %s (via %s)\n", orig_str, neigh_str); + bat_dbg(DBG_ROUTES, "Adding route towards: %s (via %s)\n", orig_str, neigh_str); hna_global_add_orig(orig_node, hna_buff, hna_buff_len); /* route changed */ @@ -212,7 +211,7 @@ static void update_routes(struct orig_node *orig_node, struct neigh_node *neigh_ addr_to_string(neigh_str, neigh_node->addr); addr_to_string(router_str, orig_node->router->addr); - debug_log(LOG_TYPE_ROUTES, "Changing route towards: %s (now via %s - was via %s)\n", orig_str, neigh_str, router_str); + bat_dbg(DBG_ROUTES, "Changing route towards: %s (now via %s - was via %s)\n", orig_str, neigh_str, router_str); } @@ -296,9 +295,9 @@ static int isBidirectionalNeigh(struct orig_node *orig_node, struct orig_node *o (TQ_LOCAL_WINDOW_SIZE - neigh_node->real_packet_count)) / (TQ_LOCAL_WINDOW_SIZE * TQ_LOCAL_WINDOW_SIZE * TQ_LOCAL_WINDOW_SIZE); - batman_packet->tq = ((batman_packet->tq * orig_neigh_node->tq_own * orig_neigh_node->tq_asym_penalty) / (TQ_MAX_VALUE * TQ_MAX_VALUE)); + batman_packet->tq = ((batman_packet->tq * orig_neigh_node->tq_own * orig_neigh_node->tq_asym_penalty) / (TQ_MAX_VALUE * TQ_MAX_VALUE)); - debug_log(LOG_TYPE_BATMAN, "bidirectional: orig = %-15s neigh = %-15s => own_bcast = %2i, real recv = %2i, local tq: %3i, asym_penalty: %3i, total tq: %3i \n", + bat_dbg(DBG_BATMAN, "bidirectional: orig = %-15s neigh = %-15s => own_bcast = %2i, real recv = %2i, local tq: %3i, asym_penalty: %3i, total tq: %3i \n", orig_str, neigh_str, total_count, neigh_node->real_packet_count, orig_neigh_node->tq_own, orig_neigh_node->tq_asym_penalty, batman_packet->tq); /* if link has the minimum required transmission quality consider it bidirectional */ @@ -313,7 +312,7 @@ static void update_orig(struct orig_node *orig_node, struct ethhdr *ethhdr, stru struct neigh_node *neigh_node = NULL, *tmp_neigh_node = NULL; int tmp_hna_buff_len; - debug_log(LOG_TYPE_BATMAN, "update_originator(): Searching and updating originator entry of received packet \n"); + bat_dbg(DBG_BATMAN, "update_originator(): Searching and updating originator entry of received packet \n"); list_for_each_entry(tmp_neigh_node, &orig_node->neigh_list, list) { if (compare_orig(tmp_neigh_node->addr, ethhdr->h_source) && (tmp_neigh_node->if_incoming == if_incoming)) { @@ -331,7 +330,7 @@ static void update_orig(struct orig_node *orig_node, struct ethhdr *ethhdr, stru if (neigh_node == NULL) neigh_node = create_neighbor(orig_node, get_orig_node(ethhdr->h_source), ethhdr->h_source, if_incoming); else - debug_log(LOG_TYPE_BATMAN, "Updating existing last-hop neighbour of originator\n"); + bat_dbg(DBG_BATMAN, "Updating existing last-hop neighbour of originator\n"); orig_node->flags = batman_packet->flags; neigh_node->last_valid = jiffies; @@ -396,7 +395,8 @@ static char count_real_packets(struct ethhdr *ethhdr, struct batman_packet *batm } if (!is_duplicate) { - debug_log(LOG_TYPE_BATMAN, "updating last_seqno: old %d, new %d \n", orig_node->last_real_seqno, batman_packet->seqno); + bat_dbg(DBG_BATMAN, "updating last_seqno: old %d, new %d \n", + orig_node->last_real_seqno, batman_packet->seqno); orig_node->last_real_seqno = batman_packet->seqno; } @@ -436,7 +436,7 @@ void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_pack is_single_hop_neigh = (compare_orig(ethhdr->h_source, batman_packet->orig) ? 1 : 0); - debug_log(LOG_TYPE_BATMAN, "Received BATMAN packet via NB: %s, IF: %s [%s] (from OG: %s, via prev OG: %s, seqno %d, tq %d, TTL %d, V %d, IDF %d) \n", neigh_str, if_incoming->dev, if_incoming->addr_str, orig_str, prev_sender_str, batman_packet->seqno, batman_packet->tq, batman_packet->ttl, batman_packet->version, has_directlink_flag); + bat_dbg(DBG_BATMAN, "Received BATMAN packet via NB: %s, IF: %s [%s] (from OG: %s, via prev OG: %s, seqno %d, tq %d, TTL %d, V %d, IDF %d) \n", neigh_str, if_incoming->dev, if_incoming->addr_str, orig_str, prev_sender_str, batman_packet->seqno, batman_packet->tq, batman_packet->ttl, batman_packet->version, has_directlink_flag); list_for_each_entry_rcu(batman_if, &if_list, list) { if (batman_if->if_active != IF_ACTIVE) @@ -456,17 +456,17 @@ void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_pack } if (batman_packet->version != COMPAT_VERSION) { - debug_log(LOG_TYPE_BATMAN, "Drop packet: incompatible batman version (%i) \n", batman_packet->version); + bat_dbg(DBG_BATMAN, "Drop packet: incompatible batman version (%i) \n", batman_packet->version); return; } if (is_my_addr) { - debug_log(LOG_TYPE_BATMAN, "Drop packet: received my own broadcast (sender: %s) \n", neigh_str); + bat_dbg(DBG_BATMAN, "Drop packet: received my own broadcast (sender: %s) \n", neigh_str); return; } if (is_broadcast) { - debug_log(LOG_TYPE_BATMAN, "Drop packet: ignoring all packets with broadcast source addr (sender: %s) \n", neigh_str); + bat_dbg(DBG_BATMAN, "Drop packet: ignoring all packets with broadcast source addr (sender: %s) \n", neigh_str); return; } @@ -481,19 +481,19 @@ void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_pack orig_neigh_node->bcast_own_sum[if_incoming->if_num] = bit_packet_count((TYPE_OF_WORD *)&(orig_neigh_node->bcast_own[if_incoming->if_num * NUM_WORDS])); } - debug_log(LOG_TYPE_BATMAN, "Drop packet: originator packet from myself (via neighbour) \n"); + bat_dbg(DBG_BATMAN, "Drop packet: originator packet from myself (via neighbour) \n"); return; } if (batman_packet->tq == 0) { count_real_packets(ethhdr, batman_packet, if_incoming); - debug_log(LOG_TYPE_BATMAN, "Drop packet: originator packet with tq equal 0 \n"); + bat_dbg(DBG_BATMAN, "Drop packet: originator packet with tq equal 0 \n"); return; } if (is_my_oldorig) { - debug_log(LOG_TYPE_BATMAN, "Drop packet: ignoring all rebroadcast echos (sender: %s) \n", neigh_str); + bat_dbg(DBG_BATMAN, "Drop packet: ignoring all rebroadcast echos (sender: %s) \n", neigh_str); return; } @@ -508,7 +508,7 @@ void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_pack (compare_orig(orig_node->router->addr, batman_packet->prev_sender)) && !(compare_orig(batman_packet->orig, batman_packet->prev_sender)) && (compare_orig(orig_node->router->addr, orig_node->router->orig_node->router->addr))) { - debug_log(LOG_TYPE_BATMAN, "Drop packet: ignoring all rebroadcast packets that may make me loop (sender: %s) \n", neigh_str); + bat_dbg(DBG_BATMAN, "Drop packet: ignoring all rebroadcast packets that may make me loop (sender: %s) \n", neigh_str); return; } @@ -519,7 +519,7 @@ void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_pack /* drop packet if sender is not a direct neighbor and if we don't route towards it */ if (!is_single_hop_neigh && (orig_neigh_node->router == NULL)) { - debug_log(LOG_TYPE_BATMAN, "Drop packet: OGM via unknown neighbor! \n"); + bat_dbg(DBG_BATMAN, "Drop packet: OGM via unknown neighbor!\n"); return; } @@ -537,22 +537,22 @@ void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_pack /* mark direct link on incoming interface */ schedule_forward_packet(orig_node, ethhdr, batman_packet, 1, hna_buff_len, if_incoming); - debug_log(LOG_TYPE_BATMAN, "Forwarding packet: rebroadcast neighbour packet with direct link flag \n"); + bat_dbg(DBG_BATMAN, "Forwarding packet: rebroadcast neighbour packet with direct link flag\n"); return; } /* multihop originator */ if (!is_bidirectional) { - debug_log(LOG_TYPE_BATMAN, "Drop packet: not received via bidirectional link\n"); + bat_dbg(DBG_BATMAN, "Drop packet: not received via bidirectional link\n"); return; } if (is_duplicate) { - debug_log(LOG_TYPE_BATMAN, "Drop packet: duplicate packet received\n"); + bat_dbg(DBG_BATMAN, "Drop packet: duplicate packet received\n"); return; } - debug_log(LOG_TYPE_BATMAN, "Forwarding packet: rebroadcast originator packet \n"); + bat_dbg(DBG_BATMAN, "Forwarding packet: rebroadcast originator packet\n"); schedule_forward_packet(orig_node, ethhdr, batman_packet, 0, hna_buff_len, if_incoming); } @@ -574,7 +574,7 @@ void purge_orig(struct work_struct *work) if (time_after(jiffies, orig_node->last_valid + ((2 * PURGE_TIMEOUT * HZ) / 1000))) { - debug_log(LOG_TYPE_BATMAN, "Originator timeout: originator %s, last_valid %u \n", orig_str, (orig_node->last_valid / HZ)); + bat_dbg(DBG_BATMAN, "Originator timeout: originator %s, last_valid %lu\n", orig_str, (orig_node->last_valid / HZ)); hash_remove_bucket(orig_hash, hashit); free_orig_node(orig_node); @@ -591,7 +591,7 @@ void purge_orig(struct work_struct *work) if (time_after(jiffies, neigh_node->last_valid + ((PURGE_TIMEOUT * HZ) / 1000))) { addr_to_string(neigh_str, neigh_node->addr); - debug_log(LOG_TYPE_BATMAN, "Neighbour timeout: originator %s, neighbour: %s, last_valid %u \n", orig_str, neigh_str, (neigh_node->last_valid / HZ)); + bat_dbg(DBG_BATMAN, "Neighbour timeout: originator %s, neighbour: %s, last_valid %lu\n", orig_str, neigh_str, (neigh_node->last_valid / HZ)); neigh_purged = 1; list_del(list_pos); @@ -652,7 +652,7 @@ int packet_recv_thread(void *data) atomic_set(&exit_cond, 0); packet_buff = kmalloc(PACKBUFF_SIZE, GFP_KERNEL); if (!packet_buff) { - debug_log(LOG_TYPE_CRIT, "Could allocate memory for the packet buffer. :(\n"); + printk(KERN_ERR "batman-adv:Could allocate memory for the packet buffer. :(\n"); return -1; } @@ -677,9 +677,9 @@ int packet_recv_thread(void *data) while (1) { if (batman_if->if_active != IF_ACTIVE) { if (batman_if->if_active != IF_TO_BE_ACTIVATED) - debug_log(LOG_TYPE_NOTICE, - "Could not read from deactivated interface %s!\n", - batman_if->dev); + printk(KERN_WARNING + "batman-adv:Could not read from deactivated interface %s!\n", + batman_if->dev); if (batman_if->raw_sock) receive_raw_packet(batman_if->raw_sock, packet_buff, PACKBUFF_SIZE); @@ -698,7 +698,7 @@ int packet_recv_thread(void *data) batman_packet = (struct batman_packet *)(packet_buff + sizeof(struct ethhdr)); if (batman_packet->version != COMPAT_VERSION) { - debug_log(LOG_TYPE_BATMAN, "Drop packet: incompatible batman version (%i) \n", batman_packet->version); + bat_dbg(DBG_BATMAN, "Drop packet: incompatible batman version (%i)\n", batman_packet->version); continue; } @@ -719,9 +719,9 @@ int packet_recv_thread(void *data) spin_lock(&orig_hash_lock); receive_aggr_bat_packet(ethhdr, - packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - batman_if); + packet_buff + sizeof(struct ethhdr), + result - sizeof(struct ethhdr), + batman_if); spin_unlock(&orig_hash_lock); break; @@ -768,9 +768,9 @@ int packet_recv_thread(void *data) icmp_packet->ttl = TTL; send_raw_packet(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - orig_node->batman_if, - orig_node->router->addr); + result - sizeof(struct ethhdr), + orig_node->batman_if, + orig_node->router->addr); } @@ -785,7 +785,7 @@ int packet_recv_thread(void *data) addr_to_string(src_str, icmp_packet->orig); addr_to_string(dst_str, icmp_packet->dst); - debug_log(LOG_TYPE_NOTICE, "Error - can't send packet from %s to %s: ttl exceeded\n", src_str, dst_str); + printk(KERN_WARNING "batman-adv:Warning - can't send packet from %s to %s: ttl exceeded\n", src_str, dst_str); /* send TTL exceeded if packet is an echo request (traceroute) */ if (icmp_packet->msg_type != ECHO_REQUEST) @@ -803,9 +803,9 @@ int packet_recv_thread(void *data) icmp_packet->ttl = TTL; send_raw_packet(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - orig_node->batman_if, - orig_node->router->addr); + result - sizeof(struct ethhdr), + orig_node->batman_if, + orig_node->router->addr); } @@ -825,9 +825,9 @@ int packet_recv_thread(void *data) /* route it */ send_raw_packet(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - orig_node->batman_if, - orig_node->router->addr); + result - sizeof(struct ethhdr), + orig_node->batman_if, + orig_node->router->addr); } spin_unlock(&orig_hash_lock); @@ -866,7 +866,7 @@ int packet_recv_thread(void *data) addr_to_string(src_str, ((struct ethhdr *)(unicast_packet + 1))->h_source); addr_to_string(dst_str, unicast_packet->dest); - debug_log(LOG_TYPE_NOTICE, "Error - can't send packet from %s to %s: ttl exceeded\n", src_str, dst_str); + printk(KERN_WARNING "batman-adv:Warning - can't send packet from %s to %s: ttl exceeded\n", src_str, dst_str); continue; } @@ -880,9 +880,9 @@ int packet_recv_thread(void *data) /* route it */ send_raw_packet(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - orig_node->batman_if, - orig_node->router->addr); + result - sizeof(struct ethhdr), + orig_node->batman_if, + orig_node->router->addr); } spin_unlock(&orig_hash_lock); @@ -980,7 +980,7 @@ int packet_recv_thread(void *data) } if ((result < 0) && (result != -EAGAIN)) - debug_log(LOG_TYPE_CRIT, "Could not receive packet from interface %s: %i\n", batman_if->dev, result); + printk(KERN_ERR "batman-adv:Could not receive packet from interface %s: %i\n", batman_if->dev, result); /* lock for the next iteration */ rcu_read_lock(); diff --git a/drivers/staging/batman-adv/send.c b/drivers/staging/batman-adv/send.c index eb617508cca4..fc4953f50dff 100644 --- a/drivers/staging/batman-adv/send.c +++ b/drivers/staging/batman-adv/send.c @@ -21,7 +21,6 @@ #include "main.h" #include "send.h" -#include "log.h" #include "routing.h" #include "translation-table.h" #include "hard-interface.h" @@ -72,9 +71,9 @@ void send_raw_packet(unsigned char *pack_buff, int pack_buff_len, return; if (!(batman_if->net_dev->flags & IFF_UP)) { - debug_log(LOG_TYPE_WARN, - "Interface %s is not up - can't send packet via that interface (IF_TO_BE_DEACTIVATED was here) !\n", - batman_if->dev); + printk(KERN_WARNING + "batman-adv:Interface %s is not up - can't send packet via that interface!\n", + batman_if->dev); return; } @@ -101,9 +100,9 @@ void send_raw_packet(unsigned char *pack_buff, int pack_buff_len, * (which is > 0). This will not be treated as an error. */ retval = dev_queue_xmit(skb); if (retval < 0) - debug_log(LOG_TYPE_CRIT, - "Can't write to raw socket (IF_TO_BE_DEACTIVATED was here): %i\n", - retval); + printk(KERN_WARNING + "batman-adv:Can't write to raw socket: %i\n", + retval); } /* Send a packet to a given interface */ @@ -140,15 +139,15 @@ static void send_packet_to_if(struct forw_packet *forw_packet, fwd_str = (packet_num > 0 ? "Forwarding" : (forw_packet->own ? "Sending own" : "Forwarding")); - debug_log(LOG_TYPE_BATMAN, - "%s %spacket (originator %s, seqno %d, TQ %d, TTL %d, IDF %s) on interface %s [%s]\n", - fwd_str, - (packet_num > 0 ? "aggregated " : ""), - orig_str, ntohs(batman_packet->seqno), - batman_packet->tq, batman_packet->ttl, - (batman_packet->flags & DIRECTLINK ? - "on" : "off"), - batman_if->dev, batman_if->addr_str); + bat_dbg(DBG_BATMAN, + "%s %spacket (originator %s, seqno %d, TQ %d, TTL %d, IDF %s) on interface %s [%s]\n", + fwd_str, + (packet_num > 0 ? "aggregated " : ""), + orig_str, ntohs(batman_packet->seqno), + batman_packet->tq, batman_packet->ttl, + (batman_packet->flags & DIRECTLINK ? + "on" : "off"), + batman_if->dev, batman_if->addr_str); buff_pos += sizeof(struct batman_packet) + (batman_packet->num_hna * ETH_ALEN); @@ -172,8 +171,7 @@ static void send_packet(struct forw_packet *forw_packet) unsigned char directlink = (batman_packet->flags & DIRECTLINK ? 1 : 0); if (!forw_packet->if_incoming) { - debug_log(LOG_TYPE_CRIT, - "Error - can't forward packet: incoming iface not specified\n"); + printk(KERN_ERR "batman-adv: Error - can't forward packet: incoming iface not specified\n"); return; } @@ -188,12 +186,12 @@ static void send_packet(struct forw_packet *forw_packet) (forw_packet->own && (forw_packet->if_incoming->if_num > 0))) { /* FIXME: what about aggregated packets ? */ - debug_log(LOG_TYPE_BATMAN, - "%s packet (originator %s, seqno %d, TTL %d) on interface %s [%s]\n", - (forw_packet->own ? "Sending own" : "Forwarding"), - orig_str, ntohs(batman_packet->seqno), - batman_packet->ttl, forw_packet->if_incoming->dev, - forw_packet->if_incoming->addr_str); + bat_dbg(DBG_BATMAN, + "%s packet (originator %s, seqno %d, TTL %d) on interface %s [%s]\n", + (forw_packet->own ? "Sending own" : "Forwarding"), + orig_str, ntohs(batman_packet->seqno), + batman_packet->ttl, forw_packet->if_incoming->dev, + forw_packet->if_incoming->addr_str); send_raw_packet(forw_packet->packet_buff, forw_packet->packet_len, @@ -286,7 +284,7 @@ void schedule_forward_packet(struct orig_node *orig_node, unsigned long send_time; if (batman_packet->ttl <= 1) { - debug_log(LOG_TYPE_BATMAN, "ttl exceeded \n"); + bat_dbg(DBG_BATMAN, "ttl exceeded \n"); return; } @@ -314,9 +312,9 @@ void schedule_forward_packet(struct orig_node *orig_node, /* apply hop penalty */ batman_packet->tq = hop_penalty(batman_packet->tq); - debug_log(LOG_TYPE_BATMAN, "Forwarding packet: tq_orig: %i, tq_avg: %i, tq_forw: %i, ttl_orig: %i, ttl_forw: %i \n", - in_tq, tq_avg, batman_packet->tq, in_ttl - 1, - batman_packet->ttl); + bat_dbg(DBG_BATMAN, "Forwarding packet: tq_orig: %i, tq_avg: %i, tq_forw: %i, ttl_orig: %i, ttl_forw: %i \n", + in_tq, tq_avg, batman_packet->tq, in_ttl - 1, + batman_packet->ttl); batman_packet->seqno = htons(batman_packet->seqno); @@ -439,7 +437,7 @@ void purge_outstanding_packets(void) struct forw_packet *forw_packet; struct hlist_node *tmp_node, *safe_tmp_node; - debug_log(LOG_TYPE_BATMAN, "purge_outstanding_packets()\n"); + bat_dbg(DBG_BATMAN, "purge_outstanding_packets()\n"); /* free bcast list */ spin_lock(&forw_bcast_list_lock); diff --git a/drivers/staging/batman-adv/soft-interface.c b/drivers/staging/batman-adv/soft-interface.c index d543f50b647f..168a4e195a1c 100644 --- a/drivers/staging/batman-adv/soft-interface.c +++ b/drivers/staging/batman-adv/soft-interface.c @@ -24,7 +24,6 @@ #include "hard-interface.h" #include "send.h" #include "translation-table.h" -#include "log.h" #include "types.h" #include "hash.h" #include @@ -212,7 +211,7 @@ int interface_tx(struct sk_buff *skb, struct net_device *dev) * dropping */ if (!spin_trylock(&orig_hash_lock)) { lock_dropped++; - debug_log(LOG_TYPE_NOTICE, "%d packets dropped because lock was hold\n", lock_dropped); + printk(KERN_WARNING "batman-adv:%d packets dropped because lock was hold\n", lock_dropped); goto dropped; } diff --git a/drivers/staging/batman-adv/translation-table.c b/drivers/staging/batman-adv/translation-table.c index c2190e177c56..c7122da98f1e 100644 --- a/drivers/staging/batman-adv/translation-table.c +++ b/drivers/staging/batman-adv/translation-table.c @@ -21,7 +21,6 @@ #include "main.h" #include "translation-table.h" -#include "log.h" #include "soft-interface.h" #include "types.h" #include "hash.h" @@ -82,12 +81,12 @@ void hna_local_add(uint8_t *addr) MAC-flooding. */ if ((num_hna + 1 > (ETH_DATA_LEN - BAT_PACKET_LEN) / ETH_ALEN) || (num_hna + 1 > 255)) { - debug_log(LOG_TYPE_ROUTES, "Can't add new local hna entry (%s): number of local hna entries exceeds packet size \n", hna_str); + bat_dbg(DBG_ROUTES, "Can't add new local hna entry (%s): number of local hna entries exceeds packet size \n", hna_str); return; } - debug_log(LOG_TYPE_ROUTES, "Creating new local hna entry: %s \n", - hna_str); + bat_dbg(DBG_ROUTES, "Creating new local hna entry: %s \n", + hna_str); hna_local_entry = kmalloc(sizeof(struct hna_local_entry), GFP_ATOMIC); if (!hna_local_entry) @@ -113,7 +112,7 @@ void hna_local_add(uint8_t *addr) hna_local_hash->size * 2); if (swaphash == NULL) - debug_log(LOG_TYPE_CRIT, "Couldn't resize local hna hash table \n"); + printk(KERN_ERR "batman-adv:Couldn't resize local hna hash table \n"); else hna_local_hash = swaphash; } @@ -205,8 +204,8 @@ static void hna_local_del(struct hna_local_entry *hna_local_entry, char hna_str[ETH_STR_LEN]; addr_to_string(hna_str, hna_local_entry->addr); - debug_log(LOG_TYPE_ROUTES, "Deleting local hna entry (%s): %s \n", - hna_str, message); + bat_dbg(DBG_ROUTES, "Deleting local hna entry (%s): %s \n", + hna_str, message); hash_remove(hna_local_hash, hna_local_entry->addr); _hna_local_del(hna_local_entry); @@ -291,7 +290,9 @@ void hna_global_add_orig(struct orig_node *orig_node, memcpy(hna_global_entry->addr, hna_ptr, ETH_ALEN); addr_to_string(hna_str, hna_global_entry->addr); - debug_log(LOG_TYPE_ROUTES, "Creating new global hna entry: %s (via %s)\n", hna_str, orig_str); + bat_dbg(DBG_ROUTES, + "Creating new global hna entry: %s (via %s)\n", + hna_str, orig_str); spin_lock_irqsave(&hna_global_hash_lock, flags); hash_add(hna_global_hash, hna_global_entry); @@ -333,7 +334,7 @@ void hna_global_add_orig(struct orig_node *orig_node, hna_global_hash->size * 2); if (swaphash == NULL) - debug_log(LOG_TYPE_CRIT, "Couldn't resize global hna hash table \n"); + printk(KERN_ERR "batman-adv:Couldn't resize global hna hash table \n"); else hna_global_hash = swaphash; } @@ -386,7 +387,8 @@ void _hna_global_del_orig(struct hna_global_entry *hna_global_entry, addr_to_string(orig_str, hna_global_entry->orig_node->orig); addr_to_string(hna_str, hna_global_entry->addr); - debug_log(LOG_TYPE_ROUTES, "Deleting global hna entry %s (via %s): %s \n", hna_str, orig_str, message); + bat_dbg(DBG_ROUTES, "Deleting global hna entry %s (via %s): %s \n", + hna_str, orig_str, message); hash_remove(hna_global_hash, hna_global_entry->addr); kfree(hna_global_entry); diff --git a/drivers/staging/batman-adv/vis.c b/drivers/staging/batman-adv/vis.c index f6c9acb289ed..cdb8aab146d7 100644 --- a/drivers/staging/batman-adv/vis.c +++ b/drivers/staging/batman-adv/vis.c @@ -23,7 +23,6 @@ #include "send.h" #include "translation-table.h" #include "vis.h" -#include "log.h" #include "soft-interface.h" #include "hard-interface.h" #include "hash.h" @@ -445,8 +444,7 @@ static void send_vis_packet(struct vis_info *info) int packet_length; if (info->packet.ttl < 2) { - debug_log(LOG_TYPE_NOTICE, - "Error - can't send vis packet: ttl exceeded\n"); + printk(KERN_WARNING "batman-adv: Error - can't send vis packet: ttl exceeded\n"); return; } @@ -495,13 +493,13 @@ int vis_init(void) vis_hash = hash_new(256, vis_info_cmp, vis_info_choose); if (!vis_hash) { - debug_log(LOG_TYPE_CRIT, "Can't initialize vis_hash\n"); + printk(KERN_ERR "batman-adv:Can't initialize vis_hash\n"); goto err; } my_vis_info = kmalloc(1000, GFP_ATOMIC); if (!my_vis_info) { - debug_log(LOG_TYPE_CRIT, "Can't initialize vis packet\n"); + printk(KERN_ERR "batman-adv:Can't initialize vis packet\n"); goto err; } @@ -522,8 +520,8 @@ int vis_init(void) memcpy(my_vis_info->packet.sender_orig, mainIfAddr, ETH_ALEN); if (hash_add(vis_hash, my_vis_info) < 0) { - debug_log(LOG_TYPE_CRIT, - "Can't add own vis packet into hash\n"); + printk(KERN_ERR + "batman-adv:Can't add own vis packet into hash\n"); free_info(my_vis_info); /* not in hash, need to remove it * manually. */ goto err; -- cgit v1.2.3 From 4efe0b06559e8cb39c3d6a9bd01cc99604dfd247 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 12 Dec 2009 23:39:42 +0100 Subject: Staging: batman-adv: Refactor routing.c Break up a lot of the big functions up into many smaller ones. This helps with readability and there is now a lot less code squashed against the right hand margin. Signed-off-by: Andrew Lunn Acked-by: Marek Lindner Acked-by: Simon Wunderlich Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/routing.c | 1148 +++++++++++++++++++++------------- 1 file changed, 709 insertions(+), 439 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index 1f42d4167422..1ff2a7aae108 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -19,10 +19,6 @@ * */ - - - - #include "main.h" #include "routing.h" #include "send.h" @@ -37,8 +33,6 @@ #include "aggregation.h" #include "compat.h" - - DECLARE_WAIT_QUEUE_HEAD(thread_wait); static DECLARE_DELAYED_WORK(purge_orig_wq, purge_orig); @@ -83,7 +77,9 @@ void originator_free(void) spin_unlock(&orig_hash_lock); } -static struct neigh_node *create_neighbor(struct orig_node *orig_node, struct orig_node *orig_neigh_node, uint8_t *neigh, struct batman_if *if_incoming) +static struct neigh_node * +create_neighbor(struct orig_node *orig_node, struct orig_node *orig_neigh_node, + uint8_t *neigh, struct batman_if *if_incoming) { struct neigh_node *neigh_node; @@ -122,12 +118,14 @@ void free_orig_node(void *data) kfree(orig_node); } -/* this function finds or creates an originator entry for the given address if it does not exits */ +/* this function finds or creates an originator entry for the given + * address if it does not exits */ static struct orig_node *get_orig_node(uint8_t *addr) { struct orig_node *orig_node; struct hashtable_t *swaphash; char orig_str[ETH_STR_LEN]; + int size; orig_node = ((struct orig_node *)hash_find(orig_hash, addr)); @@ -146,11 +144,14 @@ static struct orig_node *get_orig_node(uint8_t *addr) orig_node->batman_if = NULL; orig_node->hna_buff = NULL; - orig_node->bcast_own = kmalloc(num_ifs * sizeof(TYPE_OF_WORD) * NUM_WORDS, GFP_ATOMIC); - memset(orig_node->bcast_own, 0, num_ifs * sizeof(TYPE_OF_WORD) * NUM_WORDS); + size = num_ifs * sizeof(TYPE_OF_WORD) * NUM_WORDS; + + orig_node->bcast_own = kmalloc(size, GFP_ATOMIC); + memset(orig_node->bcast_own, 0, size); - orig_node->bcast_own_sum = kmalloc(num_ifs * sizeof(uint8_t), GFP_ATOMIC); - memset(orig_node->bcast_own_sum, 0, num_ifs * sizeof(uint8_t)); + size = num_ifs * sizeof(uint8_t); + orig_node->bcast_own_sum = kmalloc(size, GFP_ATOMIC); + memset(orig_node->bcast_own_sum, 0, size); hash_add(orig_hash, orig_node); @@ -158,7 +159,8 @@ static struct orig_node *get_orig_node(uint8_t *addr) swaphash = hash_resize(orig_hash, orig_hash->size * 2); if (swaphash == NULL) - printk(KERN_ERR "batman-adv:Couldn't resize orig hash table \n"); + printk(KERN_ERR + "batman-adv:Couldn't resize orig hash table \n"); else orig_hash = swaphash; } @@ -170,75 +172,99 @@ void slide_own_bcast_window(struct batman_if *batman_if) { struct hash_it_t *hashit = NULL; struct orig_node *orig_node; + TYPE_OF_WORD *word; spin_lock(&orig_hash_lock); while (NULL != (hashit = hash_iterate(orig_hash, hashit))) { orig_node = hashit->bucket->data; + word = &(orig_node->bcast_own[batman_if->if_num * NUM_WORDS]); - bit_get_packet((TYPE_OF_WORD *)&(orig_node->bcast_own[batman_if->if_num * NUM_WORDS]), 1, 0); - orig_node->bcast_own_sum[batman_if->if_num] = bit_packet_count((TYPE_OF_WORD *)&(orig_node->bcast_own[batman_if->if_num * NUM_WORDS])); + bit_get_packet(word, 1, 0); + orig_node->bcast_own_sum[batman_if->if_num] = + bit_packet_count(word); } spin_unlock(&orig_hash_lock); } -static void update_routes(struct orig_node *orig_node, struct neigh_node *neigh_node, unsigned char *hna_buff, int hna_buff_len) +static void update_HNA(struct orig_node *orig_node, + unsigned char *hna_buff, int hna_buff_len) { - char orig_str[ETH_STR_LEN], neigh_str[ETH_STR_LEN], router_str[ETH_STR_LEN]; + if ((hna_buff_len != orig_node->hna_buff_len) || + ((hna_buff_len > 0) && + (orig_node->hna_buff_len > 0) && + (memcmp(orig_node->hna_buff, hna_buff, hna_buff_len) != 0))) { - if (orig_node == NULL) - return; - - if (orig_node->router != neigh_node) { - addr_to_string(orig_str, orig_node->orig); - - /* route deleted */ - if ((orig_node->router != NULL) && (neigh_node == NULL)) { - bat_dbg(DBG_ROUTES, "Deleting route towards: %s\n", - orig_str); - hna_global_del_orig(orig_node, "originator timed out"); + if (orig_node->hna_buff_len > 0) + hna_global_del_orig(orig_node, + "originator changed hna"); - /* route added */ - } else if ((orig_node->router == NULL) && (neigh_node != NULL)) { - - addr_to_string(neigh_str, neigh_node->addr); - bat_dbg(DBG_ROUTES, "Adding route towards: %s (via %s)\n", orig_str, neigh_str); + if ((hna_buff_len > 0) && (hna_buff != NULL)) hna_global_add_orig(orig_node, hna_buff, hna_buff_len); + } +} - /* route changed */ - } else { +static void update_route(struct orig_node *orig_node, + struct neigh_node *neigh_node, + unsigned char *hna_buff, int hna_buff_len) +{ + char orig_str[ETH_STR_LEN], neigh_str[ETH_STR_LEN]; + char router_str[ETH_STR_LEN]; - addr_to_string(neigh_str, neigh_node->addr); - addr_to_string(router_str, orig_node->router->addr); - bat_dbg(DBG_ROUTES, "Changing route towards: %s (now via %s - was via %s)\n", orig_str, neigh_str, router_str); + addr_to_string(orig_str, orig_node->orig); - } + /* route deleted */ + if ((orig_node->router != NULL) && (neigh_node == NULL)) { - if (neigh_node != NULL) - orig_node->batman_if = neigh_node->if_incoming; - else - orig_node->batman_if = NULL; + bat_dbg(DBG_ROUTES, "Deleting route towards: %s\n", + orig_str); + hna_global_del_orig(orig_node, "originator timed out"); - orig_node->router = neigh_node; + /* route added */ + } else if ((orig_node->router == NULL) && (neigh_node != NULL)) { - /* may be just HNA changed */ + addr_to_string(neigh_str, neigh_node->addr); + bat_dbg(DBG_ROUTES, + "Adding route towards: %s (via %s)\n", + orig_str, neigh_str); + hna_global_add_orig(orig_node, hna_buff, hna_buff_len); + + /* route changed */ } else { + addr_to_string(neigh_str, neigh_node->addr); + addr_to_string(router_str, orig_node->router->addr); + bat_dbg(DBG_ROUTES, "Changing route towards: %s (now via %s - was via %s)\n", orig_str, neigh_str, router_str); + } - if ((hna_buff_len != orig_node->hna_buff_len) || ((hna_buff_len > 0) && (orig_node->hna_buff_len > 0) && (memcmp(orig_node->hna_buff, hna_buff, hna_buff_len) != 0))) { + if (neigh_node != NULL) + orig_node->batman_if = neigh_node->if_incoming; + else + orig_node->batman_if = NULL; - if (orig_node->hna_buff_len > 0) - hna_global_del_orig(orig_node, "originator changed hna"); + orig_node->router = neigh_node; +} - if ((hna_buff_len > 0) && (hna_buff != NULL)) - hna_global_add_orig(orig_node, hna_buff, hna_buff_len); - } +static void update_routes(struct orig_node *orig_node, + struct neigh_node *neigh_node, + unsigned char *hna_buff, int hna_buff_len) +{ - } + if (orig_node == NULL) + return; + + if (orig_node->router != neigh_node) + update_route(orig_node, neigh_node, hna_buff, hna_buff_len); + /* may be just HNA changed */ + else + update_HNA(orig_node, hna_buff, hna_buff_len); } -static int isBidirectionalNeigh(struct orig_node *orig_node, struct orig_node *orig_neigh_node, struct batman_packet *batman_packet, struct batman_if *if_incoming) +static int isBidirectionalNeigh(struct orig_node *orig_node, + struct orig_node *orig_neigh_node, + struct batman_packet *batman_packet, + struct batman_if *if_incoming) { struct neigh_node *neigh_node = NULL, *tmp_neigh_node = NULL; char orig_str[ETH_STR_LEN], neigh_str[ETH_STR_LEN]; @@ -248,66 +274,100 @@ static int isBidirectionalNeigh(struct orig_node *orig_node, struct orig_node *o addr_to_string(neigh_str, orig_neigh_node->orig); if (orig_node == orig_neigh_node) { - list_for_each_entry(tmp_neigh_node, &orig_node->neigh_list, list) { + list_for_each_entry(tmp_neigh_node, + &orig_node->neigh_list, + list) { - if (compare_orig(tmp_neigh_node->addr, orig_neigh_node->orig) && (tmp_neigh_node->if_incoming == if_incoming)) + if (compare_orig(tmp_neigh_node->addr, + orig_neigh_node->orig) && + (tmp_neigh_node->if_incoming == if_incoming)) neigh_node = tmp_neigh_node; } if (neigh_node == NULL) - neigh_node = create_neighbor(orig_node, orig_neigh_node, orig_neigh_node->orig, if_incoming); + neigh_node = create_neighbor(orig_node, + orig_neigh_node, + orig_neigh_node->orig, + if_incoming); neigh_node->last_valid = jiffies; } else { /* find packet count of corresponding one hop neighbor */ - list_for_each_entry(tmp_neigh_node, &orig_neigh_node->neigh_list, list) { + list_for_each_entry(tmp_neigh_node, + &orig_neigh_node->neigh_list, list) { - if (compare_orig(tmp_neigh_node->addr, orig_neigh_node->orig) && (tmp_neigh_node->if_incoming == if_incoming)) + if (compare_orig(tmp_neigh_node->addr, + orig_neigh_node->orig) && + (tmp_neigh_node->if_incoming == if_incoming)) neigh_node = tmp_neigh_node; } if (neigh_node == NULL) - neigh_node = create_neighbor(orig_neigh_node, orig_neigh_node, orig_neigh_node->orig, if_incoming); + neigh_node = create_neighbor(orig_neigh_node, + orig_neigh_node, + orig_neigh_node->orig, + if_incoming); } orig_node->last_valid = jiffies; /* pay attention to not get a value bigger than 100 % */ - total_count = (orig_neigh_node->bcast_own_sum[if_incoming->if_num] > neigh_node->real_packet_count ? neigh_node->real_packet_count : orig_neigh_node->bcast_own_sum[if_incoming->if_num]); + total_count = (orig_neigh_node->bcast_own_sum[if_incoming->if_num] > + neigh_node->real_packet_count ? + neigh_node->real_packet_count : + orig_neigh_node->bcast_own_sum[if_incoming->if_num]); /* if we have too few packets (too less data) we set tq_own to zero */ /* if we receive too few packets it is not considered bidirectional */ - if ((total_count < TQ_LOCAL_BIDRECT_SEND_MINIMUM) || (neigh_node->real_packet_count < TQ_LOCAL_BIDRECT_RECV_MINIMUM)) + if ((total_count < TQ_LOCAL_BIDRECT_SEND_MINIMUM) || + (neigh_node->real_packet_count < TQ_LOCAL_BIDRECT_RECV_MINIMUM)) orig_neigh_node->tq_own = 0; else - /* neigh_node->real_packet_count is never zero as we only purge old information when getting new information */ - orig_neigh_node->tq_own = (TQ_MAX_VALUE * total_count) / neigh_node->real_packet_count; + /* neigh_node->real_packet_count is never zero as we + * only purge old information when getting new + * information */ + orig_neigh_node->tq_own = (TQ_MAX_VALUE * total_count) / + neigh_node->real_packet_count; /* - * 1 - ((1-x) ** 3), normalized to TQ_MAX_VALUE - * this does affect the nearly-symmetric links only a little, - * but punishes asymmetric links more. - * this will give a value between 0 and TQ_MAX_VALUE + * 1 - ((1-x) ** 3), normalized to TQ_MAX_VALUE this does + * affect the nearly-symmetric links only a little, but + * punishes asymmetric links more. This will give a value + * between 0 and TQ_MAX_VALUE */ - orig_neigh_node->tq_asym_penalty = TQ_MAX_VALUE - (TQ_MAX_VALUE * - (TQ_LOCAL_WINDOW_SIZE - neigh_node->real_packet_count) * - (TQ_LOCAL_WINDOW_SIZE - neigh_node->real_packet_count) * - (TQ_LOCAL_WINDOW_SIZE - neigh_node->real_packet_count)) / - (TQ_LOCAL_WINDOW_SIZE * TQ_LOCAL_WINDOW_SIZE * TQ_LOCAL_WINDOW_SIZE); - - batman_packet->tq = ((batman_packet->tq * orig_neigh_node->tq_own * orig_neigh_node->tq_asym_penalty) / (TQ_MAX_VALUE * TQ_MAX_VALUE)); + orig_neigh_node->tq_asym_penalty = + TQ_MAX_VALUE - + (TQ_MAX_VALUE * + (TQ_LOCAL_WINDOW_SIZE - neigh_node->real_packet_count) * + (TQ_LOCAL_WINDOW_SIZE - neigh_node->real_packet_count) * + (TQ_LOCAL_WINDOW_SIZE - neigh_node->real_packet_count)) / + (TQ_LOCAL_WINDOW_SIZE * + TQ_LOCAL_WINDOW_SIZE * + TQ_LOCAL_WINDOW_SIZE); + + batman_packet->tq = ((batman_packet->tq * + orig_neigh_node->tq_own * + orig_neigh_node->tq_asym_penalty) / + (TQ_MAX_VALUE * TQ_MAX_VALUE)); bat_dbg(DBG_BATMAN, "bidirectional: orig = %-15s neigh = %-15s => own_bcast = %2i, real recv = %2i, local tq: %3i, asym_penalty: %3i, total tq: %3i \n", - orig_str, neigh_str, total_count, neigh_node->real_packet_count, orig_neigh_node->tq_own, orig_neigh_node->tq_asym_penalty, batman_packet->tq); + orig_str, neigh_str, total_count, + neigh_node->real_packet_count, orig_neigh_node->tq_own, + orig_neigh_node->tq_asym_penalty, batman_packet->tq); - /* if link has the minimum required transmission quality consider it bidirectional */ + /* if link has the minimum required transmission quality + * consider it bidirectional */ if (batman_packet->tq >= TQ_TOTAL_BIDRECT_LIMIT) return 1; return 0; } -static void update_orig(struct orig_node *orig_node, struct ethhdr *ethhdr, struct batman_packet *batman_packet, struct batman_if *if_incoming, unsigned char *hna_buff, int hna_buff_len, char is_duplicate) +static void update_orig(struct orig_node *orig_node, struct ethhdr *ethhdr, + struct batman_packet *batman_packet, + struct batman_if *if_incoming, + unsigned char *hna_buff, int hna_buff_len, + char is_duplicate) { struct neigh_node *neigh_node = NULL, *tmp_neigh_node = NULL; int tmp_hna_buff_len; @@ -315,7 +375,8 @@ static void update_orig(struct orig_node *orig_node, struct ethhdr *ethhdr, stru bat_dbg(DBG_BATMAN, "update_originator(): Searching and updating originator entry of received packet \n"); list_for_each_entry(tmp_neigh_node, &orig_node->neigh_list, list) { - if (compare_orig(tmp_neigh_node->addr, ethhdr->h_source) && (tmp_neigh_node->if_incoming == if_incoming)) { + if (compare_orig(tmp_neigh_node->addr, ethhdr->h_source) && + (tmp_neigh_node->if_incoming == if_incoming)) { neigh_node = tmp_neigh_node; continue; } @@ -323,19 +384,26 @@ static void update_orig(struct orig_node *orig_node, struct ethhdr *ethhdr, stru if (is_duplicate) continue; - ring_buffer_set(tmp_neigh_node->tq_recv, &tmp_neigh_node->tq_index, 0); - tmp_neigh_node->tq_avg = ring_buffer_avg(tmp_neigh_node->tq_recv); + ring_buffer_set(tmp_neigh_node->tq_recv, + &tmp_neigh_node->tq_index, 0); + tmp_neigh_node->tq_avg = + ring_buffer_avg(tmp_neigh_node->tq_recv); } if (neigh_node == NULL) - neigh_node = create_neighbor(orig_node, get_orig_node(ethhdr->h_source), ethhdr->h_source, if_incoming); + neigh_node = create_neighbor(orig_node, + get_orig_node(ethhdr->h_source), + ethhdr->h_source, if_incoming); else - bat_dbg(DBG_BATMAN, "Updating existing last-hop neighbour of originator\n"); + bat_dbg(DBG_BATMAN, + "Updating existing last-hop neighbour of originator\n"); orig_node->flags = batman_packet->flags; neigh_node->last_valid = jiffies; - ring_buffer_set(neigh_node->tq_recv, &neigh_node->tq_index, batman_packet->tq); + ring_buffer_set(neigh_node->tq_recv, + &neigh_node->tq_index, + batman_packet->tq); neigh_node->tq_avg = ring_buffer_avg(neigh_node->tq_recv); if (!is_duplicate) { @@ -343,9 +411,11 @@ static void update_orig(struct orig_node *orig_node, struct ethhdr *ethhdr, stru neigh_node->last_ttl = batman_packet->ttl; } - tmp_hna_buff_len = (hna_buff_len > batman_packet->num_hna * ETH_ALEN ? batman_packet->num_hna * ETH_ALEN : hna_buff_len); + tmp_hna_buff_len = (hna_buff_len > batman_packet->num_hna * ETH_ALEN ? + batman_packet->num_hna * ETH_ALEN : hna_buff_len); - /* if this neighbor already is our next hop there is nothing to change */ + /* if this neighbor already is our next hop there is nothing + * to change */ if (orig_node->router == neigh_node) goto update_hna; @@ -354,11 +424,12 @@ static void update_orig(struct orig_node *orig_node, struct ethhdr *ethhdr, stru (orig_node->router->tq_avg > neigh_node->tq_avg)) goto update_hna; - /* if the TQ is the same and the link not more symetric we won't consider it either */ + /* if the TQ is the same and the link not more symetric we + * won't consider it either */ if ((orig_node->router) && ((neigh_node->tq_avg == orig_node->router->tq_avg) && - (orig_node->router->orig_node->bcast_own_sum[if_incoming->if_num] >= - neigh_node->orig_node->bcast_own_sum[if_incoming->if_num]))) + (orig_node->router->orig_node->bcast_own_sum[if_incoming->if_num] + >= neigh_node->orig_node->bcast_own_sum[if_incoming->if_num]))) goto update_hna; update_routes(orig_node, neigh_node, hna_buff, tmp_hna_buff_len); @@ -369,29 +440,35 @@ update_hna: return; } -static char count_real_packets(struct ethhdr *ethhdr, struct batman_packet *batman_packet, struct batman_if *if_incoming) +static char count_real_packets(struct ethhdr *ethhdr, + struct batman_packet *batman_packet, + struct batman_if *if_incoming) { struct orig_node *orig_node; struct neigh_node *tmp_neigh_node; char is_duplicate = 0; - + uint16_t seq_diff; orig_node = get_orig_node(batman_packet->orig); if (orig_node == NULL) return 0; - list_for_each_entry(tmp_neigh_node, &orig_node->neigh_list, list) { if (!is_duplicate) - is_duplicate = get_bit_status(tmp_neigh_node->real_bits, orig_node->last_real_seqno, batman_packet->seqno); - - if (compare_orig(tmp_neigh_node->addr, ethhdr->h_source) && (tmp_neigh_node->if_incoming == if_incoming)) - bit_get_packet(tmp_neigh_node->real_bits, batman_packet->seqno - orig_node->last_real_seqno, 1); + is_duplicate = + get_bit_status(tmp_neigh_node->real_bits, + orig_node->last_real_seqno, + batman_packet->seqno); + seq_diff = batman_packet->seqno - orig_node->last_real_seqno; + if (compare_orig(tmp_neigh_node->addr, ethhdr->h_source) && + (tmp_neigh_node->if_incoming == if_incoming)) + bit_get_packet(tmp_neigh_node->real_bits, seq_diff, 1); else - bit_get_packet(tmp_neigh_node->real_bits, batman_packet->seqno - orig_node->last_real_seqno, 0); + bit_get_packet(tmp_neigh_node->real_bits, seq_diff, 0); - tmp_neigh_node->real_packet_count = bit_packet_count(tmp_neigh_node->real_bits); + tmp_neigh_node->real_packet_count = + bit_packet_count(tmp_neigh_node->real_bits); } if (!is_duplicate) { @@ -403,24 +480,33 @@ static char count_real_packets(struct ethhdr *ethhdr, struct batman_packet *batm return is_duplicate; } -void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_packet, unsigned char *hna_buff, int hna_buff_len, struct batman_if *if_incoming) +void receive_bat_packet(struct ethhdr *ethhdr, + struct batman_packet *batman_packet, + unsigned char *hna_buff, + int hna_buff_len, + struct batman_if *if_incoming) { struct batman_if *batman_if; struct orig_node *orig_neigh_node, *orig_node; - char orig_str[ETH_STR_LEN], prev_sender_str[ETH_STR_LEN], neigh_str[ETH_STR_LEN]; + char orig_str[ETH_STR_LEN], prev_sender_str[ETH_STR_LEN]; + char neigh_str[ETH_STR_LEN]; char has_directlink_flag; - char is_my_addr = 0, is_my_orig = 0, is_my_oldorig = 0, is_broadcast = 0, is_bidirectional, is_single_hop_neigh, is_duplicate; + char is_my_addr = 0, is_my_orig = 0, is_my_oldorig = 0; + char is_broadcast = 0, is_bidirectional, is_single_hop_neigh; + char is_duplicate; unsigned short if_incoming_seqno; - /* Silently drop when the batman packet is actually not a correct packet. + /* Silently drop when the batman packet is actually not a + * correct packet. * * This might happen if a packet is padded (e.g. Ethernet has a * minimum frame length of 64 byte) and the aggregation interprets * it as an additional length. * - * TODO: A more sane solution would be to have a bit in the batman_packet - * to detect whether the packet is the last packet in an aggregation. - * Here we expect that the padding is always zero (or not 0x01) + * TODO: A more sane solution would be to have a bit in the + * batman_packet to detect whether the packet is the last + * packet in an aggregation. Here we expect that the padding + * is always zero (or not 0x01) */ if (batman_packet->packet_type != BAT_PACKET) return; @@ -434,21 +520,29 @@ void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_pack has_directlink_flag = (batman_packet->flags & DIRECTLINK ? 1 : 0); - is_single_hop_neigh = (compare_orig(ethhdr->h_source, batman_packet->orig) ? 1 : 0); + is_single_hop_neigh = (compare_orig(ethhdr->h_source, + batman_packet->orig) ? 1 : 0); - bat_dbg(DBG_BATMAN, "Received BATMAN packet via NB: %s, IF: %s [%s] (from OG: %s, via prev OG: %s, seqno %d, tq %d, TTL %d, V %d, IDF %d) \n", neigh_str, if_incoming->dev, if_incoming->addr_str, orig_str, prev_sender_str, batman_packet->seqno, batman_packet->tq, batman_packet->ttl, batman_packet->version, has_directlink_flag); + bat_dbg(DBG_BATMAN, "Received BATMAN packet via NB: %s, IF: %s [%s] (from OG: %s, via prev OG: %s, seqno %d, tq %d, TTL %d, V %d, IDF %d) \n", + neigh_str, if_incoming->dev, if_incoming->addr_str, + orig_str, prev_sender_str, batman_packet->seqno, + batman_packet->tq, batman_packet->ttl, batman_packet->version, + has_directlink_flag); list_for_each_entry_rcu(batman_if, &if_list, list) { if (batman_if->if_active != IF_ACTIVE) continue; - if (compare_orig(ethhdr->h_source, batman_if->net_dev->dev_addr)) + if (compare_orig(ethhdr->h_source, + batman_if->net_dev->dev_addr)) is_my_addr = 1; - if (compare_orig(batman_packet->orig, batman_if->net_dev->dev_addr)) + if (compare_orig(batman_packet->orig, + batman_if->net_dev->dev_addr)) is_my_orig = 1; - if (compare_orig(batman_packet->prev_sender, batman_if->net_dev->dev_addr)) + if (compare_orig(batman_packet->prev_sender, + batman_if->net_dev->dev_addr)) is_my_oldorig = 1; if (compare_orig(ethhdr->h_source, broadcastAddr)) @@ -456,12 +550,16 @@ void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_pack } if (batman_packet->version != COMPAT_VERSION) { - bat_dbg(DBG_BATMAN, "Drop packet: incompatible batman version (%i) \n", batman_packet->version); + bat_dbg(DBG_BATMAN, + "Drop packet: incompatible batman version (%i)\n", + batman_packet->version); return; } if (is_my_addr) { - bat_dbg(DBG_BATMAN, "Drop packet: received my own broadcast (sender: %s) \n", neigh_str); + bat_dbg(DBG_BATMAN, + "Drop packet: received my own broadcast (sender: %s)\n", + neigh_str); return; } @@ -471,14 +569,24 @@ void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_pack } if (is_my_orig) { + TYPE_OF_WORD *word; + int offset; + orig_neigh_node = get_orig_node(ethhdr->h_source); - /* neighbour has to indicate direct link and it has to come via the corresponding interface */ - /* if received seqno equals last send seqno save new seqno for bidirectional check */ - if (has_directlink_flag && compare_orig(if_incoming->net_dev->dev_addr, batman_packet->orig) && - (batman_packet->seqno - if_incoming_seqno + 2 == 0)) { - bit_mark((TYPE_OF_WORD *)&(orig_neigh_node->bcast_own[if_incoming->if_num * NUM_WORDS]), 0); - orig_neigh_node->bcast_own_sum[if_incoming->if_num] = bit_packet_count((TYPE_OF_WORD *)&(orig_neigh_node->bcast_own[if_incoming->if_num * NUM_WORDS])); + /* neighbour has to indicate direct link and it has to + * come via the corresponding interface */ + /* if received seqno equals last send seqno save new + * seqno for bidirectional check */ + if (has_directlink_flag && + compare_orig(if_incoming->net_dev->dev_addr, + batman_packet->orig) && + (batman_packet->seqno - if_incoming_seqno + 2 == 0)) { + offset = if_incoming->if_num * NUM_WORDS; + word = &(orig_neigh_node->bcast_own[offset]); + bit_mark(word, 0); + orig_neigh_node->bcast_own_sum[if_incoming->if_num] = + bit_packet_count(word); } bat_dbg(DBG_BATMAN, "Drop packet: originator packet from myself (via neighbour) \n"); @@ -504,38 +612,50 @@ void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_pack return; /* avoid temporary routing loops */ - if ((orig_node->router) && (orig_node->router->orig_node->router) && - (compare_orig(orig_node->router->addr, batman_packet->prev_sender)) && + if ((orig_node->router) && + (orig_node->router->orig_node->router) && + (compare_orig(orig_node->router->addr, + batman_packet->prev_sender)) && !(compare_orig(batman_packet->orig, batman_packet->prev_sender)) && - (compare_orig(orig_node->router->addr, orig_node->router->orig_node->router->addr))) { + (compare_orig(orig_node->router->addr, + orig_node->router->orig_node->router->addr))) { bat_dbg(DBG_BATMAN, "Drop packet: ignoring all rebroadcast packets that may make me loop (sender: %s) \n", neigh_str); return; } - /* if sender is a direct neighbor the sender mac equals originator mac */ - orig_neigh_node = (is_single_hop_neigh ? orig_node : get_orig_node(ethhdr->h_source)); + /* if sender is a direct neighbor the sender mac equals + * originator mac */ + orig_neigh_node = (is_single_hop_neigh ? + orig_node : get_orig_node(ethhdr->h_source)); if (orig_neigh_node == NULL) return; - /* drop packet if sender is not a direct neighbor and if we don't route towards it */ - if (!is_single_hop_neigh && (orig_neigh_node->router == NULL)) { + /* drop packet if sender is not a direct neighbor and if we + * don't route towards it */ + if (!is_single_hop_neigh && + (orig_neigh_node->router == NULL)) { bat_dbg(DBG_BATMAN, "Drop packet: OGM via unknown neighbor!\n"); return; } - is_bidirectional = isBidirectionalNeigh(orig_node, orig_neigh_node, batman_packet, if_incoming); + is_bidirectional = isBidirectionalNeigh(orig_node, orig_neigh_node, + batman_packet, if_incoming); - /* update ranking if it is not a duplicate or has the same seqno and similar ttl as the non-duplicate */ - if (is_bidirectional && (!is_duplicate || - ((orig_node->last_real_seqno == batman_packet->seqno) && - (orig_node->last_ttl - 3 <= batman_packet->ttl)))) - update_orig(orig_node, ethhdr, batman_packet, if_incoming, hna_buff, hna_buff_len, is_duplicate); + /* update ranking if it is not a duplicate or has the same + * seqno and similar ttl as the non-duplicate */ + if (is_bidirectional && + (!is_duplicate || + ((orig_node->last_real_seqno == batman_packet->seqno) && + (orig_node->last_ttl - 3 <= batman_packet->ttl)))) + update_orig(orig_node, ethhdr, batman_packet, + if_incoming, hna_buff, hna_buff_len, is_duplicate); /* is single hop (direct) neighbour */ if (is_single_hop_neigh) { /* mark direct link on incoming interface */ - schedule_forward_packet(orig_node, ethhdr, batman_packet, 1, hna_buff_len, if_incoming); + schedule_forward_packet(orig_node, ethhdr, batman_packet, + 1, hna_buff_len, if_incoming); bat_dbg(DBG_BATMAN, "Forwarding packet: rebroadcast neighbour packet with direct link flag\n"); return; @@ -543,7 +663,8 @@ void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_pack /* multihop originator */ if (!is_bidirectional) { - bat_dbg(DBG_BATMAN, "Drop packet: not received via bidirectional link\n"); + bat_dbg(DBG_BATMAN, + "Drop packet: not received via bidirectional link\n"); return; } @@ -552,65 +673,85 @@ void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_pack return; } - bat_dbg(DBG_BATMAN, "Forwarding packet: rebroadcast originator packet\n"); - schedule_forward_packet(orig_node, ethhdr, batman_packet, 0, hna_buff_len, if_incoming); + bat_dbg(DBG_BATMAN, + "Forwarding packet: rebroadcast originator packet\n"); + schedule_forward_packet(orig_node, ethhdr, batman_packet, + 0, hna_buff_len, if_incoming); } -void purge_orig(struct work_struct *work) +static bool purge_orig_neigbours(struct orig_node *orig_node, + struct neigh_node **best_neigh_node) { struct list_head *list_pos, *list_pos_tmp; - struct hash_it_t *hashit = NULL; - struct orig_node *orig_node; - struct neigh_node *neigh_node, *best_neigh_node; - char orig_str[ETH_STR_LEN], neigh_str[ETH_STR_LEN], neigh_purged; - - spin_lock(&orig_hash_lock); + char neigh_str[ETH_STR_LEN], orig_str[ETH_STR_LEN]; + struct neigh_node *neigh_node; + bool neigh_purged = false; - /* for all origins... */ - while (NULL != (hashit = hash_iterate(orig_hash, hashit))) { + *best_neigh_node = NULL; - orig_node = hashit->bucket->data; - addr_to_string(orig_str, orig_node->orig); - if (time_after(jiffies, orig_node->last_valid + ((2 * PURGE_TIMEOUT * HZ) / 1000))) { + /* for all neighbours towards this originator ... */ + list_for_each_safe(list_pos, list_pos_tmp, &orig_node->neigh_list) { + neigh_node = list_entry(list_pos, struct neigh_node, list); - bat_dbg(DBG_BATMAN, "Originator timeout: originator %s, last_valid %lu\n", orig_str, (orig_node->last_valid / HZ)); + if (time_after(jiffies, + (neigh_node->last_valid + + ((PURGE_TIMEOUT * HZ) / 1000)))) { - hash_remove_bucket(orig_hash, hashit); - free_orig_node(orig_node); + addr_to_string(neigh_str, neigh_node->addr); + bat_dbg(DBG_BATMAN, "Neighbour timeout: originator %s, neighbour: %s, last_valid %lu\n", orig_str, neigh_str, (neigh_node->last_valid / HZ)); + neigh_purged = true; + list_del(list_pos); + kfree(neigh_node); } else { + if ((*best_neigh_node == NULL) || + (neigh_node->tq_avg > (*best_neigh_node)->tq_avg)) + *best_neigh_node = neigh_node; + } + } + return neigh_purged; +} - best_neigh_node = NULL; - neigh_purged = 0; - - /* for all neighbours towards this originator ... */ - list_for_each_safe(list_pos, list_pos_tmp, &orig_node->neigh_list) { - neigh_node = list_entry(list_pos, struct neigh_node, list); - - if (time_after(jiffies, neigh_node->last_valid + ((PURGE_TIMEOUT * HZ) / 1000))) { - - addr_to_string(neigh_str, neigh_node->addr); - bat_dbg(DBG_BATMAN, "Neighbour timeout: originator %s, neighbour: %s, last_valid %lu\n", orig_str, neigh_str, (neigh_node->last_valid / HZ)); +static bool purge_orig_node(struct orig_node *orig_node) +{ + struct neigh_node *best_neigh_node; + char orig_str[ETH_STR_LEN]; - neigh_purged = 1; - list_del(list_pos); - kfree(neigh_node); + addr_to_string(orig_str, orig_node->orig); - } else { + if (time_after(jiffies, + (orig_node->last_valid + + ((2 * PURGE_TIMEOUT * HZ) / 1000)))) { - if ((best_neigh_node == NULL) || (neigh_node->tq_avg > best_neigh_node->tq_avg)) - best_neigh_node = neigh_node; + bat_dbg(DBG_BATMAN, + "Originator timeout: originator %s, last_valid %lu\n", + orig_str, (orig_node->last_valid / HZ)); + return true; + } else { + if (purge_orig_neigbours(orig_node, &best_neigh_node)) + update_routes(orig_node, best_neigh_node, + orig_node->hna_buff, + orig_node->hna_buff_len); + } + return false; +} - } - } +void purge_orig(struct work_struct *work) +{ + struct hash_it_t *hashit = NULL; + struct orig_node *orig_node; - if (neigh_purged) - update_routes(orig_node, best_neigh_node, orig_node->hna_buff, orig_node->hna_buff_len); + spin_lock(&orig_hash_lock); + /* for all origins... */ + while (NULL != (hashit = hash_iterate(orig_hash, hashit))) { + orig_node = hashit->bucket->data; + if (purge_orig_node(orig_node)) { + hash_remove_bucket(orig_hash, hashit); + free_orig_node(orig_node); } - } spin_unlock(&orig_hash_lock); @@ -618,7 +759,8 @@ void purge_orig(struct work_struct *work) start_purge_timer(); } -static int receive_raw_packet(struct socket *raw_sock, unsigned char *packet_buff, int packet_buff_len) +static int receive_raw_packet(struct socket *raw_sock, + unsigned char *packet_buff, int packet_buff_len) { struct kvec iov; struct msghdr msg; @@ -631,367 +773,495 @@ static int receive_raw_packet(struct socket *raw_sock, unsigned char *packet_buf msg.msg_namelen = 0; msg.msg_control = NULL; - return kernel_recvmsg(raw_sock, &msg, &iov, 1, packet_buff_len, MSG_DONTWAIT); + return kernel_recvmsg(raw_sock, &msg, &iov, 1, packet_buff_len, + MSG_DONTWAIT); } -int packet_recv_thread(void *data) +static void recv_bat_packet(struct ethhdr *ethhdr, + unsigned char *packet_buff, + int result, + struct batman_if *batman_if) +{ + /* packet with broadcast indication but unicast recipient */ + if (!is_bcast(ethhdr->h_dest)) + return; + + /* packet with broadcast sender address */ + if (is_bcast(ethhdr->h_source)) + return; + + /* drop packet if it has not at least one batman packet as payload */ + if (result < sizeof(struct ethhdr) + sizeof(struct batman_packet)) + return; + + spin_lock(&orig_hash_lock); + receive_aggr_bat_packet(ethhdr, + packet_buff + sizeof(struct ethhdr), + result - sizeof(struct ethhdr), + batman_if); + spin_unlock(&orig_hash_lock); +} + +static void recv_my_icmp_packet(struct ethhdr *ethhdr, + struct icmp_packet *icmp_packet, + unsigned char *packet_buff, + int result) { - struct batman_if *batman_if; - struct ethhdr *ethhdr; - struct batman_packet *batman_packet; - struct unicast_packet *unicast_packet; - struct bcast_packet *bcast_packet; - struct icmp_packet *icmp_packet; - struct vis_packet *vis_packet; struct orig_node *orig_node; - unsigned char *packet_buff, src_str[ETH_STR_LEN], dst_str[ETH_STR_LEN]; - int vis_info_len; - int result; - atomic_set(&data_ready_cond, 0); - atomic_set(&exit_cond, 0); - packet_buff = kmalloc(PACKBUFF_SIZE, GFP_KERNEL); - if (!packet_buff) { - printk(KERN_ERR "batman-adv:Could allocate memory for the packet buffer. :(\n"); - return -1; + /* add data to device queue */ + if (icmp_packet->msg_type != ECHO_REQUEST) { + bat_device_receive_packet(icmp_packet); + return; } - while ((!kthread_should_stop()) && (!atomic_read(&exit_cond))) { - - wait_event_interruptible(thread_wait, (atomic_read(&data_ready_cond) || atomic_read(&exit_cond))); + /* answer echo request (ping) */ + /* get routing information */ + spin_lock(&orig_hash_lock); + orig_node = ((struct orig_node *)hash_find(orig_hash, + icmp_packet->orig)); + + if ((orig_node != NULL) && + (orig_node->batman_if != NULL) && + (orig_node->router != NULL)) { + memcpy(icmp_packet->dst, icmp_packet->orig, ETH_ALEN); + memcpy(icmp_packet->orig, ethhdr->h_dest, ETH_ALEN); + icmp_packet->msg_type = ECHO_REPLY; + icmp_packet->ttl = TTL; + + send_raw_packet(packet_buff + sizeof(struct ethhdr), + result - sizeof(struct ethhdr), + orig_node->batman_if, + orig_node->router->addr); + } - atomic_set(&data_ready_cond, 0); + spin_unlock(&orig_hash_lock); + return; +} - if (kthread_should_stop() || atomic_read(&exit_cond)) - break; +static void recv_icmp_ttl_exceeded(struct icmp_packet *icmp_packet, + struct ethhdr *ethhdr, + unsigned char *packet_buff, + int result, + struct batman_if *batman_if) +{ + unsigned char src_str[ETH_STR_LEN], dst_str[ETH_STR_LEN]; + struct orig_node *orig_node; - /* we only want to safely traverse the list, hard-interfaces - * won't be deleted anyway as long as this thread runs. */ + addr_to_string(src_str, icmp_packet->orig); + addr_to_string(dst_str, icmp_packet->dst); - rcu_read_lock(); - list_for_each_entry_rcu(batman_if, &if_list, list) { - rcu_read_unlock(); - - result = -1; - - while (1) { - if (batman_if->if_active != IF_ACTIVE) { - if (batman_if->if_active != IF_TO_BE_ACTIVATED) - printk(KERN_WARNING - "batman-adv:Could not read from deactivated interface %s!\n", - batman_if->dev); - - if (batman_if->raw_sock) - receive_raw_packet(batman_if->raw_sock, packet_buff, PACKBUFF_SIZE); - result = 0; - break; - } + printk(KERN_WARNING "batman-adv:Warning - can't send packet from %s to %s: ttl exceeded\n", src_str, dst_str); - result = receive_raw_packet(batman_if->raw_sock, packet_buff, PACKBUFF_SIZE); - if (result <= 0) - break; + /* send TTL exceeded if packet is an echo request (traceroute) */ + if (icmp_packet->msg_type != ECHO_REQUEST) + return; - if (result < sizeof(struct ethhdr) + 2) - continue; + /* get routing information */ + spin_lock(&orig_hash_lock); + orig_node = ((struct orig_node *) + hash_find(orig_hash, icmp_packet->orig)); + + if ((orig_node != NULL) && + (orig_node->batman_if != NULL) && + (orig_node->router != NULL)) { + memcpy(icmp_packet->dst, icmp_packet->orig, ETH_ALEN); + memcpy(icmp_packet->orig, ethhdr->h_dest, ETH_ALEN); + icmp_packet->msg_type = TTL_EXCEEDED; + icmp_packet->ttl = TTL; + + send_raw_packet(packet_buff + sizeof(struct ethhdr), + result - sizeof(struct ethhdr), + orig_node->batman_if, + orig_node->router->addr); - ethhdr = (struct ethhdr *)packet_buff; - batman_packet = (struct batman_packet *)(packet_buff + sizeof(struct ethhdr)); + } - if (batman_packet->version != COMPAT_VERSION) { - bat_dbg(DBG_BATMAN, "Drop packet: incompatible batman version (%i)\n", batman_packet->version); - continue; - } + spin_unlock(&orig_hash_lock); +} - switch (batman_packet->packet_type) { - /* batman originator packet */ - case BAT_PACKET: - /* packet with broadcast indication but unicast recipient */ - if (!is_bcast(ethhdr->h_dest)) - continue; - /* packet with broadcast sender address */ - if (is_bcast(ethhdr->h_source)) - continue; - /* drop packet if it has not at least one batman packet as payload */ - if (result < sizeof(struct ethhdr) + sizeof(struct batman_packet)) - continue; +static void recv_icmp_packet(struct ethhdr *ethhdr, + unsigned char *packet_buff, + int result, + struct batman_if *batman_if) +{ + struct icmp_packet *icmp_packet; + struct orig_node *orig_node; - spin_lock(&orig_hash_lock); - receive_aggr_bat_packet(ethhdr, - packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - batman_if); - spin_unlock(&orig_hash_lock); + /* packet with unicast indication but broadcast recipient */ + if (is_bcast(ethhdr->h_dest)) + return; - break; + /* packet with broadcast sender address */ + if (is_bcast(ethhdr->h_source)) + return; - /* batman icmp packet */ - case BAT_ICMP: - /* packet with unicast indication but broadcast recipient */ - if (is_bcast(ethhdr->h_dest)) - continue; + /* not for me */ + if (!is_my_mac(ethhdr->h_dest)) + return; - /* packet with broadcast sender address */ - if (is_bcast(ethhdr->h_source)) - continue; + /* drop packet if it has not necessary minimum size */ + if (result < sizeof(struct ethhdr) + sizeof(struct icmp_packet)) + return; - /* not for me */ - if (!is_my_mac(ethhdr->h_dest)) - continue; + icmp_packet = (struct icmp_packet *) + (packet_buff + sizeof(struct ethhdr)); - /* drop packet if it has not necessary minimum size */ - if (result < sizeof(struct ethhdr) + sizeof(struct icmp_packet)) - continue; + /* packet for me */ + if (is_my_mac(icmp_packet->dst)) + recv_my_icmp_packet(ethhdr, icmp_packet, packet_buff, result); - icmp_packet = (struct icmp_packet *)(packet_buff + sizeof(struct ethhdr)); + /* TTL exceeded */ + if (icmp_packet->ttl < 2) { + recv_icmp_ttl_exceeded(icmp_packet, ethhdr, packet_buff, result, + batman_if); + return; - /* packet for me */ - if (is_my_mac(icmp_packet->dst)) { + } - /* add data to device queue */ - if (icmp_packet->msg_type != ECHO_REQUEST) { - bat_device_receive_packet(icmp_packet); - continue; - } + /* get routing information */ + spin_lock(&orig_hash_lock); + orig_node = ((struct orig_node *) + hash_find(orig_hash, icmp_packet->dst)); - /* answer echo request (ping) */ - /* get routing information */ - spin_lock(&orig_hash_lock); - orig_node = ((struct orig_node *)hash_find(orig_hash, icmp_packet->orig)); + if ((orig_node != NULL) && + (orig_node->batman_if != NULL) && + (orig_node->router != NULL)) { - if ((orig_node != NULL) && (orig_node->batman_if != NULL) && (orig_node->router != NULL)) { + /* decrement ttl */ + icmp_packet->ttl--; - memcpy(icmp_packet->dst, icmp_packet->orig, ETH_ALEN); - memcpy(icmp_packet->orig, ethhdr->h_dest, ETH_ALEN); - icmp_packet->msg_type = ECHO_REPLY; - icmp_packet->ttl = TTL; + /* route it */ + send_raw_packet(packet_buff + sizeof(struct ethhdr), + result - sizeof(struct ethhdr), + orig_node->batman_if, + orig_node->router->addr); + } + spin_unlock(&orig_hash_lock); +} - send_raw_packet(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - orig_node->batman_if, - orig_node->router->addr); +static void recv_unicast_packet(struct ethhdr *ethhdr, + unsigned char *packet_buff, + int result, + struct batman_if *batman_if) +{ + struct unicast_packet *unicast_packet; + unsigned char src_str[ETH_STR_LEN], dst_str[ETH_STR_LEN]; + struct orig_node *orig_node; + int hdr_size = sizeof(struct ethhdr) + sizeof(struct unicast_packet); - } + /* packet with unicast indication but broadcast recipient */ + if (is_bcast(ethhdr->h_dest)) + return; - spin_unlock(&orig_hash_lock); - continue; + /* packet with broadcast sender address */ + if (is_bcast(ethhdr->h_source)) + return; - } + /* not for me */ + if (!is_my_mac(ethhdr->h_dest)) + return; - /* TTL exceeded */ - if (icmp_packet->ttl < 2) { + /* drop packet if it has not necessary minimum size */ + if (result < hdr_size) + return; - addr_to_string(src_str, icmp_packet->orig); - addr_to_string(dst_str, icmp_packet->dst); + unicast_packet = (struct unicast_packet *) + (packet_buff + sizeof(struct ethhdr)); - printk(KERN_WARNING "batman-adv:Warning - can't send packet from %s to %s: ttl exceeded\n", src_str, dst_str); + /* packet for me */ + if (is_my_mac(unicast_packet->dest)) { + interface_rx(soft_device, packet_buff + hdr_size, + result - hdr_size); + return; - /* send TTL exceeded if packet is an echo request (traceroute) */ - if (icmp_packet->msg_type != ECHO_REQUEST) - continue; + } - /* get routing information */ - spin_lock(&orig_hash_lock); - orig_node = ((struct orig_node *)hash_find(orig_hash, icmp_packet->orig)); + /* TTL exceeded */ + if (unicast_packet->ttl < 2) { + addr_to_string(src_str, ((struct ethhdr *) + (unicast_packet + 1))->h_source); + addr_to_string(dst_str, unicast_packet->dest); - if ((orig_node != NULL) && (orig_node->batman_if != NULL) && (orig_node->router != NULL)) { + printk(KERN_WARNING "batman-adv:Warning - can't send packet from %s to %s: ttl exceeded\n", src_str, dst_str); + return; + } - memcpy(icmp_packet->dst, icmp_packet->orig, ETH_ALEN); - memcpy(icmp_packet->orig, ethhdr->h_dest, ETH_ALEN); - icmp_packet->msg_type = TTL_EXCEEDED; - icmp_packet->ttl = TTL; + /* get routing information */ + spin_lock(&orig_hash_lock); + orig_node = ((struct orig_node *) + hash_find(orig_hash, unicast_packet->dest)); + + if ((orig_node != NULL) && + (orig_node->batman_if != NULL) && + (orig_node->router != NULL)) { + /* decrement ttl */ + unicast_packet->ttl--; + + /* route it */ + send_raw_packet(packet_buff + sizeof(struct ethhdr), + result - sizeof(struct ethhdr), + orig_node->batman_if, + orig_node->router->addr); + } + spin_unlock(&orig_hash_lock); +} - send_raw_packet(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - orig_node->batman_if, - orig_node->router->addr); - } +static void recv_bcast_packet(struct ethhdr *ethhdr, + unsigned char *packet_buff, + int result, + struct batman_if *batman_if) +{ + struct orig_node *orig_node; + struct bcast_packet *bcast_packet; + int hdr_size = sizeof(struct ethhdr) + sizeof(struct bcast_packet); - spin_unlock(&orig_hash_lock); - continue; + /* packet with broadcast indication but unicast recipient */ + if (!is_bcast(ethhdr->h_dest)) + return; - } + /* packet with broadcast sender address */ + if (is_bcast(ethhdr->h_source)) + return; - /* get routing information */ - spin_lock(&orig_hash_lock); - orig_node = ((struct orig_node *)hash_find(orig_hash, icmp_packet->dst)); + /* drop packet if it has not necessary minimum size */ + if (result < hdr_size) + return; - if ((orig_node != NULL) && (orig_node->batman_if != NULL) && (orig_node->router != NULL)) { + /* ignore broadcasts sent by myself */ + if (is_my_mac(ethhdr->h_source)) + return; - /* decrement ttl */ - icmp_packet->ttl--; + bcast_packet = (struct bcast_packet *) + (packet_buff + sizeof(struct ethhdr)); - /* route it */ - send_raw_packet(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - orig_node->batman_if, - orig_node->router->addr); - } + /* ignore broadcasts originated by myself */ + if (is_my_mac(bcast_packet->orig)) + return; - spin_unlock(&orig_hash_lock); - break; + spin_lock(&orig_hash_lock); + orig_node = ((struct orig_node *) + hash_find(orig_hash, bcast_packet->orig)); - /* unicast packet */ - case BAT_UNICAST: - /* packet with unicast indication but broadcast recipient */ - if (is_bcast(ethhdr->h_dest)) - continue; + if (orig_node == NULL) { + spin_unlock(&orig_hash_lock); + return; + } - /* packet with broadcast sender address */ - if (is_bcast(ethhdr->h_source)) - continue; + /* check flood history */ + if (get_bit_status(orig_node->bcast_bits, + orig_node->last_bcast_seqno, + ntohs(bcast_packet->seqno))) { + spin_unlock(&orig_hash_lock); + return; + } - /* not for me */ - if (!is_my_mac(ethhdr->h_dest)) - continue; + /* mark broadcast in flood history */ + if (bit_get_packet(orig_node->bcast_bits, + ntohs(bcast_packet->seqno) - + orig_node->last_bcast_seqno, 1)) + orig_node->last_bcast_seqno = ntohs(bcast_packet->seqno); - /* drop packet if it has not necessary minimum size */ - if (result < sizeof(struct ethhdr) + sizeof(struct unicast_packet)) - continue; + spin_unlock(&orig_hash_lock); - unicast_packet = (struct unicast_packet *)(packet_buff + sizeof(struct ethhdr)); + /* broadcast for me */ + interface_rx(soft_device, packet_buff + hdr_size, result - hdr_size); - /* packet for me */ - if (is_my_mac(unicast_packet->dest)) { + /* rebroadcast packet */ + add_bcast_packet_to_list(packet_buff + sizeof(struct ethhdr), + result - sizeof(struct ethhdr)); +} - interface_rx(soft_device, packet_buff + sizeof(struct ethhdr) + sizeof(struct unicast_packet), result - sizeof(struct ethhdr) - sizeof(struct unicast_packet)); - continue; +static void recv_vis_packet(struct ethhdr *ethhdr, + unsigned char *packet_buff, + int result) +{ + struct vis_packet *vis_packet; + int hdr_size = sizeof(struct ethhdr) + sizeof(struct vis_packet); + int vis_info_len; - } + /* drop if too short. */ + if (result < hdr_size) + return; - /* TTL exceeded */ - if (unicast_packet->ttl < 2) { - addr_to_string(src_str, ((struct ethhdr *)(unicast_packet + 1))->h_source); - addr_to_string(dst_str, unicast_packet->dest); + /* not for me */ + if (!is_my_mac(ethhdr->h_dest)) + return; - printk(KERN_WARNING "batman-adv:Warning - can't send packet from %s to %s: ttl exceeded\n", src_str, dst_str); - continue; - } + vis_packet = (struct vis_packet *)(packet_buff + sizeof(struct ethhdr)); + vis_info_len = result - hdr_size; - /* get routing information */ - spin_lock(&orig_hash_lock); - orig_node = ((struct orig_node *)hash_find(orig_hash, unicast_packet->dest)); + /* ignore own packets */ + if (is_my_mac(vis_packet->vis_orig)) + return; - if ((orig_node != NULL) && (orig_node->batman_if != NULL) && (orig_node->router != NULL)) { - /* decrement ttl */ - unicast_packet->ttl--; + if (is_my_mac(vis_packet->sender_orig)) + return; - /* route it */ - send_raw_packet(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - orig_node->batman_if, - orig_node->router->addr); - } + switch (vis_packet->vis_type) { + case VIS_TYPE_SERVER_SYNC: + receive_server_sync_packet(vis_packet, vis_info_len); + break; - spin_unlock(&orig_hash_lock); - break; + case VIS_TYPE_CLIENT_UPDATE: + receive_client_update_packet(vis_packet, vis_info_len); + break; - /* broadcast packet */ - case BAT_BCAST: - /* packet with broadcast indication but unicast recipient */ - if (!is_bcast(ethhdr->h_dest)) - continue; + default: /* ignore unknown packet */ + break; + } +} - /* packet with broadcast sender address */ - if (is_bcast(ethhdr->h_source)) - continue; +static int recv_one_packet(struct batman_if *batman_if, + unsigned char *packet_buff) +{ + int result; + struct ethhdr *ethhdr; + struct batman_packet *batman_packet; - /* drop packet if it has not necessary minimum size */ - if (result < sizeof(struct ethhdr) + sizeof(struct bcast_packet)) - continue; + result = receive_raw_packet(batman_if->raw_sock, packet_buff, + PACKBUFF_SIZE); + if (result <= 0) + return result; - /* ignore broadcasts sent by myself */ - if (is_my_mac(ethhdr->h_source)) - continue; + if (result < sizeof(struct ethhdr) + 2) + return 0; - bcast_packet = (struct bcast_packet *)(packet_buff + sizeof(struct ethhdr)); + ethhdr = (struct ethhdr *)packet_buff; + batman_packet = (struct batman_packet *) + (packet_buff + sizeof(struct ethhdr)); - /* ignore broadcasts originated by myself */ - if (is_my_mac(bcast_packet->orig)) - continue; + if (batman_packet->version != COMPAT_VERSION) { + bat_dbg(DBG_BATMAN, + "Drop packet: incompatible batman version (%i)\n", + batman_packet->version); + return 0; + } - spin_lock(&orig_hash_lock); - orig_node = ((struct orig_node *)hash_find(orig_hash, bcast_packet->orig)); + switch (batman_packet->packet_type) { + /* batman originator packet */ + case BAT_PACKET: + recv_bat_packet(ethhdr, packet_buff, result, batman_if); + break; + + /* batman icmp packet */ + case BAT_ICMP: + recv_icmp_packet(ethhdr, packet_buff, result, batman_if); + break; + + /* unicast packet */ + case BAT_UNICAST: + recv_unicast_packet(ethhdr, packet_buff, result, batman_if); + break; + + /* broadcast packet */ + case BAT_BCAST: + recv_bcast_packet(ethhdr, + packet_buff, result, batman_if); + break; + + /* vis packet */ + case BAT_VIS: + recv_vis_packet(ethhdr, packet_buff, result); + break; + } + return 0; +} - if (orig_node == NULL) { - spin_unlock(&orig_hash_lock); - continue; - } - /* check flood history */ - if (get_bit_status(orig_node->bcast_bits, orig_node->last_bcast_seqno, ntohs(bcast_packet->seqno))) { - spin_unlock(&orig_hash_lock); - continue; - } +static int discard_one_packet(struct batman_if *batman_if, + unsigned char *packet_buff) +{ + int result = -EAGAIN; - /* mark broadcast in flood history */ - if (bit_get_packet(orig_node->bcast_bits, ntohs(bcast_packet->seqno) - orig_node->last_bcast_seqno, 1)) - orig_node->last_bcast_seqno = ntohs(bcast_packet->seqno); + if (batman_if->if_active != IF_TO_BE_ACTIVATED) { + printk(KERN_WARNING + "batman-adv:Could not read from deactivated interface %s!\n", + batman_if->dev); + } else { + if (batman_if->raw_sock) + result = receive_raw_packet(batman_if->raw_sock, + packet_buff, + PACKBUFF_SIZE); + } + return result; +} - spin_unlock(&orig_hash_lock); - /* broadcast for me */ - interface_rx(soft_device, packet_buff + sizeof(struct ethhdr) + sizeof(struct bcast_packet), result - sizeof(struct ethhdr) - sizeof(struct bcast_packet)); +static bool is_interface_active(struct batman_if *batman_if) +{ + if (batman_if->if_active != IF_ACTIVE) + return false; - /* rebroadcast packet */ - add_bcast_packet_to_list(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr)); + return true; +} - break; +static void service_interface(struct batman_if *batman_if, + unsigned char *packet_buff) - /* vis packet */ - case BAT_VIS: - /* drop if too short. */ - if (result < sizeof(struct ethhdr) + sizeof(struct vis_packet)) - continue; +{ + int result; - /* not for me */ - if (!is_my_mac(ethhdr->h_dest)) - continue; + do { + if (is_interface_active(batman_if)) + result = recv_one_packet(batman_if, packet_buff); + else + result = discard_one_packet(batman_if, packet_buff); + } while (result >= 0); - vis_packet = (struct vis_packet *)(packet_buff + sizeof(struct ethhdr)); - vis_info_len = result - sizeof(struct ethhdr) - sizeof(struct vis_packet); + /* we perform none blocking reads, so EAGAIN indicates there + are no more packets to read. Anything else is a real + error.*/ - /* ignore own packets */ - if (is_my_mac(vis_packet->vis_orig)) - continue; + if ((result < 0) && (result != -EAGAIN)) + printk(KERN_ERR "batman-adv:Could not receive packet from interface %s: %i\n", batman_if->dev, result); +} - if (is_my_mac(vis_packet->sender_orig)) - continue; +static void service_interfaces(unsigned char *packet_buffer) +{ + struct batman_if *batman_if; + rcu_read_lock(); + list_for_each_entry_rcu(batman_if, &if_list, list) { + rcu_read_unlock(); + service_interface(batman_if, packet_buffer); + rcu_read_lock(); + } + rcu_read_unlock(); +} - switch (vis_packet->vis_type) { - case VIS_TYPE_SERVER_SYNC: - receive_server_sync_packet(vis_packet, vis_info_len); - break; - case VIS_TYPE_CLIENT_UPDATE: - receive_client_update_packet(vis_packet, vis_info_len); - break; +int packet_recv_thread(void *data) +{ + unsigned char *packet_buff; - default: /* ignore unknown packet */ - break; - } + atomic_set(&data_ready_cond, 0); + atomic_set(&exit_cond, 0); + packet_buff = kmalloc(PACKBUFF_SIZE, GFP_KERNEL); + if (!packet_buff) { + printk(KERN_ERR"batman-adv:Could allocate memory for the packet buffer. :(\n"); + return -1; + } - break; - } + while ((!kthread_should_stop()) && (!atomic_read(&exit_cond))) { - } + wait_event_interruptible(thread_wait, + (atomic_read(&data_ready_cond) || + atomic_read(&exit_cond))); - if ((result < 0) && (result != -EAGAIN)) - printk(KERN_ERR "batman-adv:Could not receive packet from interface %s: %i\n", batman_if->dev, result); + atomic_set(&data_ready_cond, 0); - /* lock for the next iteration */ - rcu_read_lock(); - } - rcu_read_unlock(); + if (kthread_should_stop() || atomic_read(&exit_cond)) + break; + service_interfaces(packet_buff); } kfree(packet_buff); - /* do not exit until kthread_stop() is actually called, otherwise it will wait for us - * forever. */ + /* do not exit until kthread_stop() is actually called, + * otherwise it will wait for us forever. */ while (!kthread_should_stop()) schedule(); -- cgit v1.2.3 From da6b9ba95f2ce3f923013ce09793ab16f05bac25 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 12 Dec 2009 23:39:43 +0100 Subject: Staging: batman-adv: stop persistent warnings if a device is deactivated. Without this change we spam the kernel log on every packet received on any other interface when an interface has been added, but is not yet active, ie UP. Signed-off-by: Simon Wunderlich Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/routing.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index 1ff2a7aae108..decf67fa944c 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -1177,12 +1177,8 @@ static int discard_one_packet(struct batman_if *batman_if, { int result = -EAGAIN; - if (batman_if->if_active != IF_TO_BE_ACTIVATED) { - printk(KERN_WARNING - "batman-adv:Could not read from deactivated interface %s!\n", - batman_if->dev); - } else { - if (batman_if->raw_sock) + if ((batman_if->if_active == IF_TO_BE_ACTIVATED) + && (batman_if->raw_sock)) { result = receive_raw_packet(batman_if->raw_sock, packet_buff, PACKBUFF_SIZE); -- cgit v1.2.3 From 4088c7ca57b6dbe25683bb16f25233cce373996c Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 12 Dec 2009 23:39:44 +0100 Subject: Staging: batman-adv: Always receive when discarding. It does not matter if the interface is to be activated or not, we must read the packet in order that it be discarded. Signed-off-by: Simon Wunderlich Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/routing.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index decf67fa944c..6a8d73d51357 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -1177,8 +1177,7 @@ static int discard_one_packet(struct batman_if *batman_if, { int result = -EAGAIN; - if ((batman_if->if_active == IF_TO_BE_ACTIVATED) - && (batman_if->raw_sock)) { + if (batman_if->raw_sock) { result = receive_raw_packet(batman_if->raw_sock, packet_buff, PACKBUFF_SIZE); -- cgit v1.2.3 From 8a2e042c2d9b4f1252dbbbb7c31bd3f8af19c8f2 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 12 Dec 2009 23:39:45 +0100 Subject: Staging: batman-adv: Split originator handling parts out of routing.c Bug found and fixed in origional version by Linus Luessing. Signed-off-by: Simon Wunderlich Signed-off-by: Linus Luessing Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/Makefile | 2 +- drivers/staging/batman-adv/main.c | 1 + drivers/staging/batman-adv/originator.c | 243 ++++++++++++++++++++++++++++++++ drivers/staging/batman-adv/originator.h | 31 ++++ drivers/staging/batman-adv/routing.c | 221 +---------------------------- drivers/staging/batman-adv/routing.h | 12 +- 6 files changed, 289 insertions(+), 221 deletions(-) create mode 100644 drivers/staging/batman-adv/originator.c create mode 100644 drivers/staging/batman-adv/originator.h (limited to 'drivers') diff --git a/drivers/staging/batman-adv/Makefile b/drivers/staging/batman-adv/Makefile index 64bdb7828e99..42b4e6370263 100644 --- a/drivers/staging/batman-adv/Makefile +++ b/drivers/staging/batman-adv/Makefile @@ -19,4 +19,4 @@ # obj-m += batman-adv.o -batman-adv-objs := main.o proc.o send.o routing.o soft-interface.o device.o translation-table.o bitarray.o hash.o ring_buffer.o vis.o hard-interface.o aggregation.o +batman-adv-objs := main.o proc.o send.o routing.o soft-interface.o device.o translation-table.o bitarray.o hash.o ring_buffer.o vis.o hard-interface.o aggregation.o originator.o diff --git a/drivers/staging/batman-adv/main.c b/drivers/staging/batman-adv/main.c index 4b93a5d33cf9..a74bfbeba7c4 100644 --- a/drivers/staging/batman-adv/main.c +++ b/drivers/staging/batman-adv/main.c @@ -23,6 +23,7 @@ #include "proc.h" #include "routing.h" #include "send.h" +#include "originator.h" #include "soft-interface.h" #include "device.h" #include "translation-table.h" diff --git a/drivers/staging/batman-adv/originator.c b/drivers/staging/batman-adv/originator.c new file mode 100644 index 000000000000..9962af7ae640 --- /dev/null +++ b/drivers/staging/batman-adv/originator.c @@ -0,0 +1,243 @@ +/* + * Copyright (C) 2009 B.A.T.M.A.N. contributors: + * + * Marek Lindner, Simon Wunderlich + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of version 2 of the GNU General Public + * License as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * + */ + +/* increase the reference counter for this originator */ + +#include "main.h" +#include "originator.h" +#include "hash.h" +#include "translation-table.h" +#include "routing.h" + + +static DECLARE_DELAYED_WORK(purge_orig_wq, purge_orig); + +static void start_purge_timer(void) +{ + queue_delayed_work(bat_event_workqueue, &purge_orig_wq, 1 * HZ); +} + +int originator_init(void) +{ + if (orig_hash) + return 1; + + spin_lock(&orig_hash_lock); + orig_hash = hash_new(128, compare_orig, choose_orig); + + if (!orig_hash) + goto err; + + spin_unlock(&orig_hash_lock); + start_purge_timer(); + return 1; + +err: + spin_unlock(&orig_hash_lock); + return 0; +} + +void originator_free(void) +{ + if (!orig_hash) + return; + + cancel_delayed_work_sync(&purge_orig_wq); + + spin_lock(&orig_hash_lock); + hash_delete(orig_hash, free_orig_node); + orig_hash = NULL; + spin_unlock(&orig_hash_lock); +} + +struct neigh_node * +create_neighbor(struct orig_node *orig_node, struct orig_node *orig_neigh_node, + uint8_t *neigh, struct batman_if *if_incoming) +{ + struct neigh_node *neigh_node; + + bat_dbg(DBG_BATMAN, "Creating new last-hop neighbour of originator\n"); + + neigh_node = kmalloc(sizeof(struct neigh_node), GFP_ATOMIC); + memset(neigh_node, 0, sizeof(struct neigh_node)); + INIT_LIST_HEAD(&neigh_node->list); + + memcpy(neigh_node->addr, neigh, ETH_ALEN); + neigh_node->orig_node = orig_neigh_node; + neigh_node->if_incoming = if_incoming; + + list_add_tail(&neigh_node->list, &orig_node->neigh_list); + return neigh_node; +} + +void free_orig_node(void *data) +{ + struct list_head *list_pos, *list_pos_tmp; + struct neigh_node *neigh_node; + struct orig_node *orig_node = (struct orig_node *)data; + + /* for all neighbours towards this originator ... */ + list_for_each_safe(list_pos, list_pos_tmp, &orig_node->neigh_list) { + neigh_node = list_entry(list_pos, struct neigh_node, list); + + list_del(list_pos); + kfree(neigh_node); + } + + hna_global_del_orig(orig_node, "originator timed out"); + + kfree(orig_node->bcast_own); + kfree(orig_node->bcast_own_sum); + kfree(orig_node); +} + +/* this function finds or creates an originator entry for the given + * address if it does not exits */ +struct orig_node *get_orig_node(uint8_t *addr) +{ + struct orig_node *orig_node; + struct hashtable_t *swaphash; + char orig_str[ETH_STR_LEN]; + int size; + + orig_node = ((struct orig_node *)hash_find(orig_hash, addr)); + + if (orig_node != NULL) + return orig_node; + + addr_to_string(orig_str, addr); + bat_dbg(DBG_BATMAN, "Creating new originator: %s \n", orig_str); + + orig_node = kmalloc(sizeof(struct orig_node), GFP_ATOMIC); + memset(orig_node, 0, sizeof(struct orig_node)); + INIT_LIST_HEAD(&orig_node->neigh_list); + + memcpy(orig_node->orig, addr, ETH_ALEN); + orig_node->router = NULL; + orig_node->batman_if = NULL; + orig_node->hna_buff = NULL; + + size = num_ifs * sizeof(TYPE_OF_WORD) * NUM_WORDS; + + orig_node->bcast_own = kmalloc(size, GFP_ATOMIC); + memset(orig_node->bcast_own, 0, size); + + size = num_ifs * sizeof(uint8_t); + orig_node->bcast_own_sum = kmalloc(size, GFP_ATOMIC); + memset(orig_node->bcast_own_sum, 0, size); + + hash_add(orig_hash, orig_node); + + if (orig_hash->elements * 4 > orig_hash->size) { + swaphash = hash_resize(orig_hash, orig_hash->size * 2); + + if (swaphash == NULL) + printk(KERN_ERR + "batman-adv:Couldn't resize orig hash table \n"); + else + orig_hash = swaphash; + } + + return orig_node; +} + +static bool purge_orig_neigbours(struct orig_node *orig_node, + struct neigh_node **best_neigh_node) +{ + struct list_head *list_pos, *list_pos_tmp; + char neigh_str[ETH_STR_LEN], orig_str[ETH_STR_LEN]; + struct neigh_node *neigh_node; + bool neigh_purged = false; + + *best_neigh_node = NULL; + + + /* for all neighbours towards this originator ... */ + list_for_each_safe(list_pos, list_pos_tmp, &orig_node->neigh_list) { + neigh_node = list_entry(list_pos, struct neigh_node, list); + + if (time_after(jiffies, + (neigh_node->last_valid + + ((PURGE_TIMEOUT * HZ) / 1000)))) { + + addr_to_string(neigh_str, neigh_node->addr); + addr_to_string(orig_str, orig_node->orig); + bat_dbg(DBG_BATMAN, "Neighbour timeout: originator %s, neighbour: %s, last_valid %lu\n", orig_str, neigh_str, (neigh_node->last_valid / HZ)); + + neigh_purged = true; + list_del(list_pos); + kfree(neigh_node); + } else { + if ((*best_neigh_node == NULL) || + (neigh_node->tq_avg > (*best_neigh_node)->tq_avg)) + *best_neigh_node = neigh_node; + } + } + return neigh_purged; +} + + +static bool purge_orig_node(struct orig_node *orig_node) +{ + struct neigh_node *best_neigh_node; + char orig_str[ETH_STR_LEN]; + + addr_to_string(orig_str, orig_node->orig); + + if (time_after(jiffies, + (orig_node->last_valid + + ((2 * PURGE_TIMEOUT * HZ) / 1000)))) { + + bat_dbg(DBG_BATMAN, + "Originator timeout: originator %s, last_valid %lu\n", + orig_str, (orig_node->last_valid / HZ)); + return true; + } else { + if (purge_orig_neigbours(orig_node, &best_neigh_node)) + update_routes(orig_node, best_neigh_node, + orig_node->hna_buff, + orig_node->hna_buff_len); + } + return false; +} + +void purge_orig(struct work_struct *work) +{ + struct hash_it_t *hashit = NULL; + struct orig_node *orig_node; + + spin_lock(&orig_hash_lock); + + /* for all origins... */ + while (NULL != (hashit = hash_iterate(orig_hash, hashit))) { + orig_node = hashit->bucket->data; + if (purge_orig_node(orig_node)) { + hash_remove_bucket(orig_hash, hashit); + free_orig_node(orig_node); + } + } + + spin_unlock(&orig_hash_lock); + + start_purge_timer(); +} + + diff --git a/drivers/staging/batman-adv/originator.h b/drivers/staging/batman-adv/originator.h new file mode 100644 index 000000000000..6ef7a054a0a9 --- /dev/null +++ b/drivers/staging/batman-adv/originator.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2007-2009 B.A.T.M.A.N. contributors: + * + * Marek Lindner, Simon Wunderlich + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of version 2 of the GNU General Public + * License as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * + */ + +int originator_init(void); +void free_orig_node(void *data); +void originator_free(void); +void purge_orig(struct work_struct *work); +struct orig_node *orig_find(char *mac); +struct orig_node *get_orig_node(uint8_t *addr); +struct neigh_node * +create_neighbor(struct orig_node *orig_node, struct orig_node *orig_neigh_node, + uint8_t *neigh, struct batman_if *if_incoming); + diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index 6a8d73d51357..e8d712788dad 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -22,152 +22,22 @@ #include "main.h" #include "routing.h" #include "send.h" +#include "hash.h" #include "soft-interface.h" #include "hard-interface.h" #include "device.h" #include "translation-table.h" +#include "originator.h" #include "types.h" -#include "hash.h" #include "ring_buffer.h" #include "vis.h" #include "aggregation.h" #include "compat.h" DECLARE_WAIT_QUEUE_HEAD(thread_wait); -static DECLARE_DELAYED_WORK(purge_orig_wq, purge_orig); static atomic_t data_ready_cond; atomic_t exit_cond; - -static void start_purge_timer(void) -{ - queue_delayed_work(bat_event_workqueue, &purge_orig_wq, 1 * HZ); -} - -int originator_init(void) -{ - if (orig_hash) - return 1; - - spin_lock(&orig_hash_lock); - orig_hash = hash_new(128, compare_orig, choose_orig); - - if (!orig_hash) - goto err; - - spin_unlock(&orig_hash_lock); - start_purge_timer(); - return 1; - -err: - spin_unlock(&orig_hash_lock); - return 0; -} - -void originator_free(void) -{ - if (!orig_hash) - return; - - cancel_delayed_work_sync(&purge_orig_wq); - - spin_lock(&orig_hash_lock); - hash_delete(orig_hash, free_orig_node); - orig_hash = NULL; - spin_unlock(&orig_hash_lock); -} - -static struct neigh_node * -create_neighbor(struct orig_node *orig_node, struct orig_node *orig_neigh_node, - uint8_t *neigh, struct batman_if *if_incoming) -{ - struct neigh_node *neigh_node; - - bat_dbg(DBG_BATMAN, "Creating new last-hop neighbour of originator\n"); - - neigh_node = kmalloc(sizeof(struct neigh_node), GFP_ATOMIC); - memset(neigh_node, 0, sizeof(struct neigh_node)); - INIT_LIST_HEAD(&neigh_node->list); - - memcpy(neigh_node->addr, neigh, ETH_ALEN); - neigh_node->orig_node = orig_neigh_node; - neigh_node->if_incoming = if_incoming; - - list_add_tail(&neigh_node->list, &orig_node->neigh_list); - return neigh_node; -} - -void free_orig_node(void *data) -{ - struct list_head *list_pos, *list_pos_tmp; - struct neigh_node *neigh_node; - struct orig_node *orig_node = (struct orig_node *)data; - - /* for all neighbours towards this originator ... */ - list_for_each_safe(list_pos, list_pos_tmp, &orig_node->neigh_list) { - neigh_node = list_entry(list_pos, struct neigh_node, list); - - list_del(list_pos); - kfree(neigh_node); - } - - hna_global_del_orig(orig_node, "originator timed out"); - - kfree(orig_node->bcast_own); - kfree(orig_node->bcast_own_sum); - kfree(orig_node); -} - -/* this function finds or creates an originator entry for the given - * address if it does not exits */ -static struct orig_node *get_orig_node(uint8_t *addr) -{ - struct orig_node *orig_node; - struct hashtable_t *swaphash; - char orig_str[ETH_STR_LEN]; - int size; - - orig_node = ((struct orig_node *)hash_find(orig_hash, addr)); - - if (orig_node != NULL) - return orig_node; - - addr_to_string(orig_str, addr); - bat_dbg(DBG_BATMAN, "Creating new originator: %s \n", orig_str); - - orig_node = kmalloc(sizeof(struct orig_node), GFP_ATOMIC); - memset(orig_node, 0, sizeof(struct orig_node)); - INIT_LIST_HEAD(&orig_node->neigh_list); - - memcpy(orig_node->orig, addr, ETH_ALEN); - orig_node->router = NULL; - orig_node->batman_if = NULL; - orig_node->hna_buff = NULL; - - size = num_ifs * sizeof(TYPE_OF_WORD) * NUM_WORDS; - - orig_node->bcast_own = kmalloc(size, GFP_ATOMIC); - memset(orig_node->bcast_own, 0, size); - - size = num_ifs * sizeof(uint8_t); - orig_node->bcast_own_sum = kmalloc(size, GFP_ATOMIC); - memset(orig_node->bcast_own_sum, 0, size); - - hash_add(orig_hash, orig_node); - - if (orig_hash->elements * 4 > orig_hash->size) { - swaphash = hash_resize(orig_hash, orig_hash->size * 2); - - if (swaphash == NULL) - printk(KERN_ERR - "batman-adv:Couldn't resize orig hash table \n"); - else - orig_hash = swaphash; - } - - return orig_node; -} - void slide_own_bcast_window(struct batman_if *batman_if) { struct hash_it_t *hashit = NULL; @@ -246,7 +116,7 @@ static void update_route(struct orig_node *orig_node, } -static void update_routes(struct orig_node *orig_node, +void update_routes(struct orig_node *orig_node, struct neigh_node *neigh_node, unsigned char *hna_buff, int hna_buff_len) { @@ -679,85 +549,6 @@ void receive_bat_packet(struct ethhdr *ethhdr, 0, hna_buff_len, if_incoming); } -static bool purge_orig_neigbours(struct orig_node *orig_node, - struct neigh_node **best_neigh_node) -{ - struct list_head *list_pos, *list_pos_tmp; - char neigh_str[ETH_STR_LEN], orig_str[ETH_STR_LEN]; - struct neigh_node *neigh_node; - bool neigh_purged = false; - - *best_neigh_node = NULL; - - - /* for all neighbours towards this originator ... */ - list_for_each_safe(list_pos, list_pos_tmp, &orig_node->neigh_list) { - neigh_node = list_entry(list_pos, struct neigh_node, list); - - if (time_after(jiffies, - (neigh_node->last_valid + - ((PURGE_TIMEOUT * HZ) / 1000)))) { - - addr_to_string(neigh_str, neigh_node->addr); - bat_dbg(DBG_BATMAN, "Neighbour timeout: originator %s, neighbour: %s, last_valid %lu\n", orig_str, neigh_str, (neigh_node->last_valid / HZ)); - - neigh_purged = true; - list_del(list_pos); - kfree(neigh_node); - } else { - if ((*best_neigh_node == NULL) || - (neigh_node->tq_avg > (*best_neigh_node)->tq_avg)) - *best_neigh_node = neigh_node; - } - } - return neigh_purged; -} - -static bool purge_orig_node(struct orig_node *orig_node) -{ - struct neigh_node *best_neigh_node; - char orig_str[ETH_STR_LEN]; - - addr_to_string(orig_str, orig_node->orig); - - if (time_after(jiffies, - (orig_node->last_valid + - ((2 * PURGE_TIMEOUT * HZ) / 1000)))) { - - bat_dbg(DBG_BATMAN, - "Originator timeout: originator %s, last_valid %lu\n", - orig_str, (orig_node->last_valid / HZ)); - return true; - } else { - if (purge_orig_neigbours(orig_node, &best_neigh_node)) - update_routes(orig_node, best_neigh_node, - orig_node->hna_buff, - orig_node->hna_buff_len); - } - return false; -} - - -void purge_orig(struct work_struct *work) -{ - struct hash_it_t *hashit = NULL; - struct orig_node *orig_node; - - spin_lock(&orig_hash_lock); - - /* for all origins... */ - while (NULL != (hashit = hash_iterate(orig_hash, hashit))) { - orig_node = hashit->bucket->data; - if (purge_orig_node(orig_node)) { - hash_remove_bucket(orig_hash, hashit); - free_orig_node(orig_node); - } - } - - spin_unlock(&orig_hash_lock); - - start_purge_timer(); -} static int receive_raw_packet(struct socket *raw_sock, unsigned char *packet_buff, int packet_buff_len) @@ -1178,9 +969,9 @@ static int discard_one_packet(struct batman_if *batman_if, int result = -EAGAIN; if (batman_if->raw_sock) { - result = receive_raw_packet(batman_if->raw_sock, - packet_buff, - PACKBUFF_SIZE); + result = receive_raw_packet(batman_if->raw_sock, + packet_buff, + PACKBUFF_SIZE); } return result; } diff --git a/drivers/staging/batman-adv/routing.h b/drivers/staging/batman-adv/routing.h index 0123ea86debb..890a4f53b553 100644 --- a/drivers/staging/batman-adv/routing.h +++ b/drivers/staging/batman-adv/routing.h @@ -24,11 +24,13 @@ extern wait_queue_head_t thread_wait; extern atomic_t exit_cond; -int originator_init(void); -void free_orig_node(void *data); -void originator_free(void); void slide_own_bcast_window(struct batman_if *batman_if); void batman_data_ready(struct sock *sk, int len); -void purge_orig(struct work_struct *work); int packet_recv_thread(void *data); -void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_packet, unsigned char *hna_buff, int hna_buff_len, struct batman_if *if_incoming); +void receive_bat_packet(struct ethhdr *ethhdr, + struct batman_packet *batman_packet, + unsigned char *hna_buff, int hna_buff_len, + struct batman_if *if_incoming); +void update_routes(struct orig_node *orig_node, + struct neigh_node *neigh_node, + unsigned char *hna_buff, int hna_buff_len); -- cgit v1.2.3 From 734cc82a65cd5abc1b616fb0699eb2c251de7831 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 12 Dec 2009 23:39:46 +0100 Subject: Staging: batman-adv: Fix the naming of the debug option. So that the configuration hierarchy is correct, set the debug option to have the same base as the main BATMAN option. Signed-off-by: Andrew Lunn Signed-off-by: Marek Lindner Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/Kconfig | 4 ++-- drivers/staging/batman-adv/README | 2 +- drivers/staging/batman-adv/main.c | 2 +- drivers/staging/batman-adv/main.h | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/Kconfig b/drivers/staging/batman-adv/Kconfig index 1d74dabf9511..69e8fb039be0 100644 --- a/drivers/staging/batman-adv/Kconfig +++ b/drivers/staging/batman-adv/Kconfig @@ -14,10 +14,10 @@ config BATMAN_ADV http://www.open-mesh.org/ for more information and user space tools. -config BATMAN_DEBUG +config BATMAN_ADV_DEBUG bool "B.A.T.M.A.N. debugging" depends on BATMAN_ADV != n - help + ---help--- This is an option for use by developers; most people should say N here. This enables compilation of support for diff --git a/drivers/staging/batman-adv/README b/drivers/staging/batman-adv/README index 6c624820edd1..a6a419de0b50 100644 --- a/drivers/staging/batman-adv/README +++ b/drivers/staging/batman-adv/README @@ -115,7 +115,7 @@ kernel, use "make menuconfig" and enable the option "B.A.T.M.A.N. debugging". When compiling outside of the kernel tree it is necessary to edit the file Makefile.kbuild and uncomment the line -#EXTRA_CFLAGS += -DCONFIG_BATMAN_DEBUG +#EXTRA_CFLAGS += -DCONFIG_BATMAN_ADV_DEBUG The additional debug output is by default disabled. It can be enabled either at kernel modules load time or during run time. To enable debug diff --git a/drivers/staging/batman-adv/main.c b/drivers/staging/batman-adv/main.c index a74bfbeba7c4..434c600a6a47 100644 --- a/drivers/staging/batman-adv/main.c +++ b/drivers/staging/batman-adv/main.c @@ -57,7 +57,7 @@ atomic_t module_state; struct workqueue_struct *bat_event_workqueue; -#ifdef CONFIG_BATMAN_DEBUG +#ifdef CONFIG_BATMAN_ADV_DEBUG int debug; module_param(debug, int, 0644); diff --git a/drivers/staging/batman-adv/main.h b/drivers/staging/batman-adv/main.h index 6907cacf8c41..eb6a702c6444 100644 --- a/drivers/staging/batman-adv/main.h +++ b/drivers/staging/batman-adv/main.h @@ -76,7 +76,7 @@ * broadcasting / etc */ #define DBG_ROUTES 2 /* route or hna added / changed / deleted */ -#ifdef CONFIG_BATMAN_DEBUG +#ifdef CONFIG_BATMAN_ADV_DEBUG extern int debug; extern int bat_debug_type(int type); @@ -85,7 +85,7 @@ extern int bat_debug_type(int type); printk(KERN_DEBUG "batman-adv:" fmt, ## arg); \ } \ while (0) -#else /* !CONFIG_BATMAN_DEBUG */ +#else /* !CONFIG_BATMAN_ADV_DEBUG */ #define bat_dbg(type, fmt, arg...) do { \ } \ while (0) -- cgit v1.2.3 From c4ad074f11acc46a4ded25dec4f4c2b8d2d4ebb8 Mon Sep 17 00:00:00 2001 From: Ameya Palande <2ameya@gmail.com> Date: Mon, 14 Dec 2009 13:57:59 +0200 Subject: Staging: iio: checkinclude.pl fix Remove which is included twice Signed-off-by: Ameya Palande <2ameya@gmail.com> Signed-off-by: Greg Kroah-Hartman --- drivers/staging/iio/ring_sw.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/iio/ring_sw.c b/drivers/staging/iio/ring_sw.c index 359ff9208f36..b746cf603225 100644 --- a/drivers/staging/iio/ring_sw.c +++ b/drivers/staging/iio/ring_sw.c @@ -8,7 +8,6 @@ */ #include -#include #include #include #include -- cgit v1.2.3 From 6309017f050af5bb66350ec25a2a1dd0c5643422 Mon Sep 17 00:00:00 2001 From: Huang Weiyi Date: Sun, 13 Dec 2009 21:14:10 +0800 Subject: Staging: wlags49_h2: remove duplicated #include Remove duplicated #include('s) in drivers/staging/wlags49_h2/wl_pci.c Signed-off-by: Huang Weiyi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlags49_h2/wl_pci.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/wlags49_h2/wl_pci.c b/drivers/staging/wlags49_h2/wl_pci.c index a3db111d4a95..01e4bec9fd5b 100644 --- a/drivers/staging/wlags49_h2/wl_pci.c +++ b/drivers/staging/wlags49_h2/wl_pci.c @@ -81,7 +81,6 @@ #include #include #include -#include #include #include -- cgit v1.2.3 From f70615a8f134c4ebe3c2848bb43a68335406a001 Mon Sep 17 00:00:00 2001 From: Huang Weiyi Date: Sun, 13 Dec 2009 22:06:25 +0800 Subject: Staging: ramzswap: remove unused #include Remove unused #include ('s) in drivers/staging/ramzswap/ramzswap_drv.c Signed-off-by: Huang Weiyi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/ramzswap/ramzswap_drv.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/ramzswap/ramzswap_drv.c b/drivers/staging/ramzswap/ramzswap_drv.c index 989fac5b01b3..18196f3852d8 100644 --- a/drivers/staging/ramzswap/ramzswap_drv.c +++ b/drivers/staging/ramzswap/ramzswap_drv.c @@ -29,7 +29,6 @@ #include #include #include -#include #include "ramzswap_drv.h" -- cgit v1.2.3 From 789d9dbdad5cb24fbf0c0e4fa5c5f1b792e4e81e Mon Sep 17 00:00:00 2001 From: Radu Voicilas Date: Fri, 4 Dec 2009 20:42:53 -0800 Subject: Staging: rtl8192e: fix some codingstyle issues dot11d.h needed a good refactoring - I've dropped some of the // comments or transformed them to match the kernel documentation. r8180_93cx6.h - fixed a little bit the copyright section. Signed-off-by: Radu Voicilas Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/dot11d.h | 138 ++++++++++++++++----------------- drivers/staging/rtl8192e/r8180_93cx6.h | 33 ++++---- 2 files changed, 83 insertions(+), 88 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192e/dot11d.h b/drivers/staging/rtl8192e/dot11d.h index 15b7a4ba37b6..5b0e2dbc2bb8 100644 --- a/drivers/staging/rtl8192e/dot11d.h +++ b/drivers/staging/rtl8192e/dot11d.h @@ -1,102 +1,96 @@ -#ifndef __INC_DOT11D_H -#define __INC_DOT11D_H +#ifndef INC_DOT11D_H +#define INC_DOT11D_H #ifdef ENABLE_DOT11D #include "ieee80211.h" -//#define ENABLE_DOT11D - -//#define DOT11D_MAX_CHNL_NUM 83 - typedef struct _CHNL_TXPOWER_TRIPLE { u8 FirstChnl; u8 NumChnls; u8 MaxTxPowerInDbm; -}CHNL_TXPOWER_TRIPLE, *PCHNL_TXPOWER_TRIPLE; +} CHNL_TXPOWER_TRIPLE, *PCHNL_TXPOWER_TRIPLE; typedef enum _DOT11D_STATE { DOT11D_STATE_NONE = 0, DOT11D_STATE_LEARNED, DOT11D_STATE_DONE, -}DOT11D_STATE; +} DOT11D_STATE; + +/** + * struct _RT_DOT11D_INFO + * @CountryIeLen: value greater than 0 if @CountryIeBuf contains + * valid country information element. + * @chanell_map: holds channel values + * 0 - invalid, + * 1 - valid (active scan), + * 2 - valid (passive scan) + * @CountryIeSrcAddr - Source AP of the country IE + */ typedef struct _RT_DOT11D_INFO { - //DECLARE_RT_OBJECT(RT_DOT11D_INFO); + bool bEnabled; - bool bEnabled; // dot11MultiDomainCapabilityEnabled + u16 CountryIeLen; + u8 CountryIeBuf[MAX_IE_LEN]; + u8 CountryIeSrcAddr[6]; + u8 CountryIeWatchdog; - u16 CountryIeLen; // > 0 if CountryIeBuf[] contains valid country information element. - u8 CountryIeBuf[MAX_IE_LEN]; - u8 CountryIeSrcAddr[6]; // Source AP of the country IE. - u8 CountryIeWatchdog; - - u8 channel_map[MAX_CHANNEL_NUMBER+1]; //!!!Value 0: Invalid, 1: Valid (active scan), 2: Valid (passive scan) - //u8 ChnlListLen; // #Bytes valid in ChnlList[]. - //u8 ChnlList[DOT11D_MAX_CHNL_NUM]; - u8 MaxTxPwrDbmList[MAX_CHANNEL_NUMBER+1]; + u8 channel_map[MAX_CHANNEL_NUMBER+1]; + u8 MaxTxPwrDbmList[MAX_CHANNEL_NUMBER+1]; DOT11D_STATE State; -}RT_DOT11D_INFO, *PRT_DOT11D_INFO; -#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 ) -#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5]) -#define GET_DOT11D_INFO(__pIeeeDev) ((PRT_DOT11D_INFO)((__pIeeeDev)->pDot11dInfo)) +} RT_DOT11D_INFO, *PRT_DOT11D_INFO; + +#define eqMacAddr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == \ + (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && \ + (a)[5] == (b)[5]) ? 1 : 0) + +#define cpMacAddr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], \ + (des)[2] = (src)[2], (des)[3] = (src)[3], \ + (des)[4] = (src)[4], (des)[5] = (src)[5]) + +#define GET_DOT11D_INFO(__pIeeeDev) ((PRT_DOT11D_INFO) \ + ((__pIeeeDev)->pDot11dInfo)) #define IS_DOT11D_ENABLE(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->bEnabled -#define IS_COUNTRY_IE_VALID(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen > 0) +#define IS_COUNTRY_IE_VALID(__pIeeeDev) \ + (GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen > 0) -#define IS_EQUAL_CIE_SRC(__pIeeeDev, __pTa) eqMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa) -#define UPDATE_CIE_SRC(__pIeeeDev, __pTa) cpMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa) +#define IS_EQUAL_CIE_SRC(__pIeeeDev, __pTa) \ + eqMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa) + +#define UPDATE_CIE_SRC(__pIeeeDev, __pTa) \ + cpMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa) #define IS_COUNTRY_IE_CHANGED(__pIeeeDev, __Ie) \ - (((__Ie).Length == 0 || (__Ie).Length != GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen) ? \ - FALSE : \ - (!memcmp(GET_DOT11D_INFO(__pIeeeDev)->CountryIeBuf, (__Ie).Octet, (__Ie).Length))) + (((__Ie).Length == 0 || (__Ie).Length != \ + GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen) ? FALSE : \ + (!memcmp(GET_DOT11D_INFO(__pIeeeDev)->CountryIeBuf, \ + (__Ie).Octet, (__Ie).Length))) #define CIE_WATCHDOG_TH 1 #define GET_CIE_WATCHDOG(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->CountryIeWatchdog #define RESET_CIE_WATCHDOG(__pIeeeDev) GET_CIE_WATCHDOG(__pIeeeDev) = 0 #define UPDATE_CIE_WATCHDOG(__pIeeeDev) ++GET_CIE_WATCHDOG(__pIeeeDev) -#define IS_DOT11D_STATE_DONE(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->State == DOT11D_STATE_DONE) - - -void -Dot11d_Init( - struct ieee80211_device *dev - ); - -void -Dot11d_Reset( - struct ieee80211_device *dev - ); - -void -Dot11d_UpdateCountryIe( - struct ieee80211_device *dev, - u8 * pTaddr, - u16 CoutryIeLen, - u8 * pCoutryIe - ); - -u8 -DOT11D_GetMaxTxPwrInDbm( - struct ieee80211_device *dev, - u8 Channel - ); - -void -DOT11D_ScanComplete( - struct ieee80211_device * dev - ); - -int IsLegalChannel( - struct ieee80211_device * dev, - u8 channel -); - -int ToLegalChannel( - struct ieee80211_device * dev, - u8 channel -); -#endif //ENABLE_DOT11D -#endif // #ifndef __INC_DOT11D_H +#define IS_DOT11D_STATE_DONE(__pIeeeDev) \ + (GET_DOT11D_INFO(__pIeeeDev)->State == DOT11D_STATE_DONE) + + +void Dot11d_Init(struct ieee80211_device *dev); + +void Dot11d_Reset(struct ieee80211_device *dev); + +void Dot11d_UpdateCountryIe(struct ieee80211_device *dev, u8 *pTaddr, + u16 CoutryIeLen, u8 *pCoutryIe); + +u8 DOT11D_GetMaxTxPwrInDbm(struct ieee80211_device *dev, u8 channel); + +void DOT11D_ScanComplete(struct ieee80211_device *dev); + +int IsLegalChannel(struct ieee80211_device *dev, u8 channel); + +int ToLegalChannel(struct ieee80211_device *dev, u8 channel); + +#endif /* ENABLE_DOT11D */ +#endif /* INC_DOT11D_H */ diff --git a/drivers/staging/rtl8192e/r8180_93cx6.h b/drivers/staging/rtl8192e/r8180_93cx6.h index 62e14c78e960..4c3f675c6a66 100644 --- a/drivers/staging/rtl8192e/r8180_93cx6.h +++ b/drivers/staging/rtl8192e/r8180_93cx6.h @@ -1,17 +1,18 @@ -/* - This is part of rtl8187 OpenSource driver - Copyright (C) Andrea Merello 2004-2005 - Released under the terms of GPL (General Public Licence) - - Parts of this driver are based on the GPL part of the official realtek driver - Parts of this driver are based on the rtl8180 driver skeleton from Patric Schenke & Andres Salomon - Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver - - We want to tanks the Authors of such projects and the Ndiswrapper project Authors. -*/ - -/*This files contains card eeprom (93c46 or 93c56) programming routines*/ -/*memory is addressed by WORDS*/ +/* r8180_93cx6.h - 93c46 or 93c56 eeprom card programming routines + * + * This is part of rtl8187 OpenSource driver + * Copyright (C) Andrea Merello 2004-2005 + * Released under the terms of GPL (General Public Licence) + * Parts of this driver are based on the GPL part of the official realtek driver + * + * Parts of this driver are based on the rtl8180 driver skeleton from + * Patric Schenke & Andres Salomon. + * + * Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver + * + * We want to thank the authors of the above mentioned projects and to + * the authors of the Ndiswrapper project. + */ #include "r8192E.h" #include "r8192E_hw.h" @@ -36,5 +37,5 @@ #define EPROM_TXPW2 0x1b #define EPROM_TXPW1 0x3d - -u32 eprom_read(struct net_device *dev,u32 addr); //reads a 16 bits word +/* Reads a 16 bits word. */ +u32 eprom_read(struct net_device *dev, u32 addr); -- cgit v1.2.3 From 65a4378471510787e080188f933913315f1afa0c Mon Sep 17 00:00:00 2001 From: david woo Date: Tue, 22 Dec 2009 09:40:36 -0800 Subject: Staging: rtl9192e: fix power usage issues This patch should allow the driver to consume a lot less power. Signed-off-by: david woo Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/Makefile | 9 +- drivers/staging/rtl8192e/ieee80211/ieee80211.h | 156 ++++- .../rtl8192e/ieee80211/ieee80211_crypt_ccmp.c | 6 +- drivers/staging/rtl8192e/ieee80211/ieee80211_rx.c | 96 ++- .../staging/rtl8192e/ieee80211/ieee80211_softmac.c | 244 +++++-- .../rtl8192e/ieee80211/ieee80211_softmac_wx.c | 26 +- drivers/staging/rtl8192e/ieee80211/ieee80211_tx.c | 76 +++ drivers/staging/rtl8192e/ieee80211/rtl819x_HT.h | 4 +- .../staging/rtl8192e/ieee80211/rtl819x_HTProc.c | 63 +- drivers/staging/rtl8192e/r8190_rtl8256.c | 360 +++++----- drivers/staging/rtl8192e/r8192E.h | 23 +- drivers/staging/rtl8192e/r8192E_core.c | 757 ++++++++++++++++++--- drivers/staging/rtl8192e/r8192E_dm.c | 40 +- drivers/staging/rtl8192e/r8192E_hw.h | 8 + drivers/staging/rtl8192e/r8192E_wx.c | 212 ++++-- drivers/staging/rtl8192e/r8192E_wx.h | 1 - drivers/staging/rtl8192e/r819xE_phy.c | 2 +- drivers/staging/rtl8192e/r819xE_phyreg.h | 3 + 18 files changed, 1660 insertions(+), 426 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192e/Makefile b/drivers/staging/rtl8192e/Makefile index 5e4aa9546b51..e032c3e1e864 100644 --- a/drivers/staging/rtl8192e/Makefile +++ b/drivers/staging/rtl8192e/Makefile @@ -1,13 +1,15 @@ NIC_SELECT = RTL8192E - EXTRA_CFLAGS += -DRTL8192E EXTRA_CFLAGS += -std=gnu89 EXTRA_CFLAGS += -O2 EXTRA_CFLAGS += -DTHOMAS_TURBO EXTRA_CFLAGS += -DENABLE_DOT11D -r8192_pci-objs := \ +EXTRA_CFLAGS += -DENABLE_IPS +EXTRA_CFLAGS += -DENABLE_LPS + +r8192e_pci-objs := \ r8192E_core.o \ r8180_93cx6.o \ r8192E_wx.o \ @@ -31,4 +33,5 @@ r8192_pci-objs := \ ieee80211/ieee80211_crypt_ccmp.o \ ieee80211/ieee80211_crypt_wep.o -obj-$(CONFIG_RTL8192E) += r8192_pci.o +obj-$(CONFIG_RTL8192E) += r8192e_pci.o + diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211.h b/drivers/staging/rtl8192e/ieee80211/ieee80211.h index 9d91ab9fc04b..5859f66ff013 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211.h +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211.h @@ -180,6 +180,8 @@ typedef struct cb_desc { u8 DrvAggrNum; u16 pkt_size; u8 reserved12; + + u8 bdhcp; }cb_desc, *pcb_desc; /*--------------------------Define -------------------------------------------*/ @@ -740,6 +742,8 @@ struct ieee80211_snap_hdr { #define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS) #define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE) #define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE) +#define WLAN_FC_MORE_DATA(fc) ((fc) & IEEE80211_FCTL_MOREDATA) + #define WLAN_FC_GET_FRAMETYPE(fc) ((fc) & IEEE80211_FCTL_FRAMETYPE) #define WLAN_GET_SEQ_FRAG(seq) ((seq) & IEEE80211_SCTL_FRAG) @@ -1052,7 +1056,7 @@ struct ieee80211_device; #define SEC_ALG_NONE 0 #define SEC_ALG_WEP 1 #define SEC_ALG_TKIP 2 -#define SEC_ALG_CCMP 3 +#define SEC_ALG_CCMP 4 #define WEP_KEYS 4 #define WEP_KEY_LEN 13 @@ -1121,6 +1125,14 @@ enum ieee80211_mfie { /* Minimal header; can be used for passing 802.11 frames with sufficient * information to determine what type of underlying data type is actually * stored in the data. */ + struct ieee80211_pspoll_hdr { + __le16 frame_ctl; + __le16 aid; + u8 bssid[ETH_ALEN]; + u8 ta[ETH_ALEN]; + //u8 payload[0]; +} __attribute__ ((packed)); + struct ieee80211_hdr { __le16 frame_ctl; __le16 duration_id; @@ -1657,6 +1669,7 @@ struct ieee80211_network { bool ralink_cap_exist; bool atheros_cap_exist; bool cisco_cap_exist; + bool marvell_cap_exist; bool unknown_cap_exist; // u8 berp_info; bool berp_info_valid; @@ -1862,6 +1875,19 @@ typedef struct _RT_POWER_SAVE_CONTROL // Leisre Poswer Save : Disable RF if connected but traffic is not busy // bool bLeisurePs; + u32 PowerProfile; + u8 LpsIdleCount; + u8 RegMaxLPSAwakeIntvl; + u8 LPSAwakeIntvl; + + u32 CurPsLevel; + u32 RegRfPsLevel; + + bool bFwCtrlLPS; + u8 FWCtrlPSMode; + + bool LinkReqInIPSRFOffPgs; + bool BufConnectinfoBefore; }RT_POWER_SAVE_CONTROL,*PRT_POWER_SAVE_CONTROL; @@ -1902,14 +1928,121 @@ typedef struct _RT_LINK_DETECT_T{ u32 NumTxOkInPeriod; u32 NumRxOkInPeriod; + u32 NumRxUnicastOkInPeriod; bool bBusyTraffic; }RT_LINK_DETECT_T, *PRT_LINK_DETECT_T; +//added by amy 090330 +typedef enum _HW_VARIABLES{ + HW_VAR_ETHER_ADDR, + HW_VAR_MULTICAST_REG, + HW_VAR_BASIC_RATE, + HW_VAR_BSSID, + HW_VAR_MEDIA_STATUS, + HW_VAR_SECURITY_CONF, + HW_VAR_BEACON_INTERVAL, + HW_VAR_ATIM_WINDOW, + HW_VAR_LISTEN_INTERVAL, + HW_VAR_CS_COUNTER, + HW_VAR_DEFAULTKEY0, + HW_VAR_DEFAULTKEY1, + HW_VAR_DEFAULTKEY2, + HW_VAR_DEFAULTKEY3, + HW_VAR_SIFS, + HW_VAR_DIFS, + HW_VAR_EIFS, + HW_VAR_SLOT_TIME, + HW_VAR_ACK_PREAMBLE, + HW_VAR_CW_CONFIG, + HW_VAR_CW_VALUES, + HW_VAR_RATE_FALLBACK_CONTROL, + HW_VAR_CONTENTION_WINDOW, + HW_VAR_RETRY_COUNT, + HW_VAR_TR_SWITCH, + HW_VAR_COMMAND, // For Command Register, Annie, 2006-04-07. + HW_VAR_WPA_CONFIG, //2004/08/23, kcwu, for 8187 Security config + HW_VAR_AMPDU_MIN_SPACE, // The spacing between sub-frame. Roger, 2008.07.04. + HW_VAR_SHORTGI_DENSITY, // The density for shortGI. Roger, 2008.07.04. + HW_VAR_AMPDU_FACTOR, + HW_VAR_MCS_RATE_AVAILABLE, + HW_VAR_AC_PARAM, // For AC Parameters, 2005.12.01, by rcnjko. + HW_VAR_ACM_CTRL, // For ACM Control, Annie, 2005-12-13. + HW_VAR_DIS_Req_Qsize, // For DIS_Reg_Qsize, Joseph + HW_VAR_CCX_CHNL_LOAD, // For CCX 2 channel load request, 2006.05.04. + HW_VAR_CCX_NOISE_HISTOGRAM, // For CCX 2 noise histogram request, 2006.05.04. + HW_VAR_CCX_CLM_NHM, // For CCX 2 parallel channel load request and noise histogram request, 2006.05.12. + HW_VAR_TxOPLimit, // For turbo mode related settings, added by Roger, 2006.12.07 + HW_VAR_TURBO_MODE, // For turbo mode related settings, added by Roger, 2006.12.15. + HW_VAR_RF_STATE, // For change or query RF power state, 061214, rcnjko. + HW_VAR_RF_OFF_BY_HW, // For UI to query if external HW signal disable RF, 061229, rcnjko. + HW_VAR_BUS_SPEED, // In unit of bps. 2006.07.03, by rcnjko. + HW_VAR_SET_DEV_POWER, // Set to low power, added by LanHsin, 2007. + + //1!!!!!!!!!!!!!!!!!!!!!!!!!!! + //1Attention Please!!!<11n or 8190 specific code should be put below this line> + //1!!!!!!!!!!!!!!!!!!!!!!!!!!! + HW_VAR_RCR, //for RCR, David 2006,05,11 + HW_VAR_RATR_0, + HW_VAR_RRSR, + HW_VAR_CPU_RST, + HW_VAR_CECHK_BSSID, + HW_VAR_LBK_MODE, // Set lookback mode, 2008.06.11. added by Roger. + // Set HW related setting for 11N AES bug. + HW_VAR_AES_11N_FIX, + // Set Usb Rx Aggregation + HW_VAR_USB_RX_AGGR, + HW_VAR_USER_CONTROL_TURBO_MODE, + HW_VAR_RETRY_LIMIT, +#ifndef _RTL8192_EXT_PATCH_ + HW_VAR_INIT_TX_RATE, //Get Current Tx rate register. 2008.12.10. Added by tynli +#endif + HW_VAR_TX_RATE_REG, //Get Current Tx rate register. 2008.12.10. Added by tynli + HW_VAR_EFUSE_USAGE, //Get current EFUSE utilization. 2008.12.19. Added by Roger. + HW_VAR_EFUSE_BYTES, + HW_VAR_AUTOLOAD_STATUS, //Get current autoload status, 0: autoload success, 1: autoload fail. 2008.12.19. Added by Roger. + HW_VAR_RF_2R_DISABLE, // 2R disable + HW_VAR_SET_RPWM, + HW_VAR_H2C_FW_PWRMODE, // For setting FW related H2C cmd structure. by tynli. 2009.2.18 + HW_VAR_H2C_FW_JOINBSSRPT, // For setting FW related H2C cmd structure. by tynli. 2009.2.18 + HW_VAR_1X1_RECV_COMBINE, // For 1T2R but only 1SS, Add by hpfan 2009.04.16 hpfan + HW_VAR_STOP_SEND_BEACON, + HW_VAR_TSF_TIMER, // Read from TSF register to get the current TSF timer, by Bruce, 2009-07-22. + HW_VAR_IO_CMD, + HW_VAR_HANDLE_FW_C2H, //Added by tynli. For handling FW C2H command. 2009.10.07. + HW_VAR_DL_FW_RSVD_PAGE, //Added by tynli. Download the packets that FW will use to RSVD page. 2009.10.14. + HW_VAR_AID, //Added by tynli. + HW_VAR_HW_SEQ_ENABLE, //Added by tynli. 2009.10.20. + HW_VAR_UPDATE_TSF, //Added by tynli. 2009.10.22. For Hw count TBTT time. + HW_VAR_BCN_VALID, //Added by tynli. + HW_VAR_FWLPS_RF_ON //Added by tynli. 2009.11.09. For checking if Fw finishs RF on sequence. +}HW_VARIABLES; + +#define RT_CHECK_FOR_HANG_PERIOD 2 struct ieee80211_device { struct net_device *dev; struct ieee80211_security sec; + bool need_sw_enc; +#ifdef ENABLE_LPS + bool bAwakePktSent; + u8 LPSDelayCnt; + bool bIsAggregateFrame; + bool polling; + void (*LeisurePSLeave)(struct net_device *dev); +#endif + +#ifdef ENABLE_IPS + bool proto_stoppping; + bool wx_set_enc; + struct semaphore ips_sem; + struct work_struct ips_leave_wq; + void (*ieee80211_ips_leave_wq) (struct net_device *dev); + void (*ieee80211_ips_leave)(struct net_device *dev); +#endif + void (*SetHwRegHandler)(struct net_device *dev,u8 variable,u8* val); + u8 (*rtllib_ap_sec_type)(struct ieee80211_device *ieee); + //hw security related // u8 hwsec_support; //support? u8 hwsec_active; //hw security active. @@ -2316,7 +2449,7 @@ struct ieee80211_device { * stop_send_bacons is NOT guaranteed to be called only * after start_send_beacons. */ - void (*start_send_beacons) (struct net_device *dev,u16 tx_rate); + void (*start_send_beacons) (struct net_device *dev); void (*stop_send_beacons) (struct net_device *dev); /* power save mode related */ @@ -2370,6 +2503,19 @@ struct ieee80211_device { u8 priv[0]; }; +#define RT_RF_OFF_LEVL_ASPM BIT0 // PCI ASPM +#define RT_RF_OFF_LEVL_CLK_REQ BIT1 // PCI clock request +#define RT_RF_OFF_LEVL_PCI_D3 BIT2 // PCI D3 mode +#define RT_RF_OFF_LEVL_HALT_NIC BIT3 // NIC halt, re-initialize hw parameters +#define RT_RF_OFF_LEVL_FREE_FW BIT4 // FW free, re-download the FW +#define RT_RF_OFF_LEVL_FW_32K BIT5 // FW in 32k +#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT6 // Always enable ASPM and Clock Req in initialization. +#define RT_RF_LPS_DISALBE_2R BIT30 // When LPS is on, disable 2R if no packet is received or transmittd. +#define RT_RF_LPS_LEVEL_ASPM BIT31 // LPS with ASPM +#define RT_IN_PS_LEVEL(pPSC, _PS_FLAG) ((pPSC->CurPsLevel & _PS_FLAG) ? true : false) +#define RT_CLEAR_PS_LEVEL(pPSC, _PS_FLAG) (pPSC->CurPsLevel &= (~(_PS_FLAG))) +#define RT_SET_PS_LEVEL(pPSC, _PS_FLAG) (pPSC->CurPsLevel |= _PS_FLAG) + #define IEEE_A (1<<0) #define IEEE_B (1<<1) #define IEEE_G (1<<2) @@ -2606,9 +2752,9 @@ extern void ieee80211_stop_scan(struct ieee80211_device *ieee); extern void ieee80211_start_scan_syncro(struct ieee80211_device *ieee); extern void ieee80211_check_all_nets(struct ieee80211_device *ieee); extern void ieee80211_start_protocol(struct ieee80211_device *ieee); -extern void ieee80211_stop_protocol(struct ieee80211_device *ieee); +extern void ieee80211_stop_protocol(struct ieee80211_device *ieee,u8 shutdown); extern void ieee80211_softmac_start_protocol(struct ieee80211_device *ieee); -extern void ieee80211_softmac_stop_protocol(struct ieee80211_device *ieee); +extern void ieee80211_softmac_stop_protocol(struct ieee80211_device *ieee,u8 shutdown); extern void ieee80211_reset_queue(struct ieee80211_device *ieee); extern void ieee80211_rtl_wake_queue(struct ieee80211_device *ieee); extern void ieee80211_rtl_stop_queue(struct ieee80211_device *ieee); @@ -2795,5 +2941,7 @@ extern int ieee80211_parse_info_param(struct ieee80211_device *ieee, struct ieee80211_rx_stats *stats); void ieee80211_indicate_packets(struct ieee80211_device *ieee, struct ieee80211_rxb** prxbIndicateArray,u8 index); +void ieee80211_sta_ps_send_null_frame(struct ieee80211_device *ieee, short pwr); +void ieee80211_sta_ps_send_pspoll_frame(struct ieee80211_device *ieee); #define RT_ASOC_RETRY_LIMIT 5 #endif /* IEEE80211_H */ diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c index 609c289541d4..70159cf28bce 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c @@ -361,9 +361,9 @@ static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) if (memcmp(pn, key->rx_pn, CCMP_PN_LEN) <= 0) { if (net_ratelimit()) { - printk(KERN_DEBUG "CCMP: replay detected: STA=%pM" - " previous PN %pm received PN %pm\n", - hdr->addr2, key->rx_pn, pn); + //printk(KERN_DEBUG "CCMP: replay detected: STA=%pM" + // " previous PN %pm received PN %pm\n", + // hdr->addr2, key->rx_pn, pn); } key->dot11RSNAStatsCCMPReplays++; return -4; diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_rx.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_rx.c index 7a500ac37acb..ce265ae5fe18 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_rx.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_rx.c @@ -312,6 +312,17 @@ static int ieee80211_is_eapol_frame(struct ieee80211_device *ieee, if (skb->len < 24) return 0; +#if 1 + if (ieee->hwsec_active) + { + cb_desc *tcb_desc = (cb_desc *)(skb->cb+ MAX_DEV_ADDR_SIZE); + tcb_desc->bHwSec = 1; + + if(ieee->need_sw_enc) + tcb_desc->bHwSec = 0; + } +#endif + hdr = (struct ieee80211_hdr_4addr *) skb->data; fc = le16_to_cpu(hdr->frame_ctl); @@ -406,6 +417,10 @@ ieee80211_rx_frame_decrypt_msdu(struct ieee80211_device* ieee, struct sk_buff *s { cb_desc *tcb_desc = (cb_desc *)(skb->cb+ MAX_DEV_ADDR_SIZE); tcb_desc->bHwSec = 1; + + if(ieee->need_sw_enc) + tcb_desc->bHwSec = 0; + } hdr = (struct ieee80211_hdr_4addr *) skb->data; @@ -799,7 +814,7 @@ void RxReorderIndicatePacket( struct ieee80211_device *ieee, #endif } -u8 parse_subframe(struct sk_buff *skb, +u8 parse_subframe(struct ieee80211_device* ieee,struct sk_buff *skb, struct ieee80211_rx_stats *rx_stats, struct ieee80211_rxb *rxb,u8* src,u8* dst) { @@ -839,6 +854,7 @@ u8 parse_subframe(struct sk_buff *skb, } skb_pull(skb, LLCOffset); + ieee->bIsAggregateFrame = bIsAggregateFrame;//added by amy for Leisure PS if(!bIsAggregateFrame) { rxb->nr_subframes = 1; @@ -940,6 +956,7 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, u8 TID = 0; u16 SeqNum = 0; PRX_TS_RECORD pTS = NULL; + bool unicast_packet = false; //bool bIsAggregateFrame = false; //added by amy for reorder #ifdef NOT_YET @@ -1215,6 +1232,24 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, if (memcmp(bssid, ieee->current_network.bssid, ETH_ALEN)) goto rx_dropped; +#ifdef ENABLE_LPS + if ((ieee->iw_mode == IW_MODE_INFRA) && (ieee->sta_sleep == 1) + && (ieee->polling)) { + if (WLAN_FC_MORE_DATA(fc)) { + /* more data bit is set, let's request a new frame from the AP */ + ieee80211_sta_ps_send_pspoll_frame(ieee); + } else { + ieee->polling = false; + } + } +#endif + + ieee->need_sw_enc = 0; + + if((!rx_stats->Decrypted)){ + ieee->need_sw_enc = 1; + } + /* skb: hdr + (possibly fragmented, possibly encrypted) payload */ if (ieee->host_decrypt && (fc & IEEE80211_FCTL_WEP) && @@ -1296,6 +1331,9 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, ieee->LinkDetectInfo.NumRxOkInPeriod++; hdr = (struct ieee80211_hdr_4addr *) skb->data; + if((!is_multicast_ether_addr(hdr->addr1)) && (!is_broadcast_ether_addr(hdr->addr1))) + unicast_packet = true; + if (crypt && !(fc & IEEE80211_FCTL_WEP) && !ieee->open_wep) { if (/*ieee->ieee802_1x &&*/ ieee80211_is_eapol_frame(ieee, skb, hdrlen)) { @@ -1367,7 +1405,7 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, } /* to parse amsdu packets */ /* qos data packets & reserved bit is 1 */ - if(parse_subframe(skb,rx_stats,rxb,src,dst) == 0) { + if(parse_subframe(ieee, skb,rx_stats,rxb,src,dst) == 0) { /* only to free rxb, and not submit the packets to upper layer */ for(i =0; i < rxb->nr_subframes; i++) { dev_kfree_skb(rxb->subframes[i]); @@ -1377,6 +1415,32 @@ int ieee80211_rtl_rx(struct ieee80211_device *ieee, struct sk_buff *skb, goto rx_dropped; } +#ifdef ENABLE_LPS + if(unicast_packet) + { + if (type == IEEE80211_FTYPE_DATA) + { + + if(ieee->bIsAggregateFrame) + ieee->LinkDetectInfo.NumRxUnicastOkInPeriod+=rxb->nr_subframes; + else + ieee->LinkDetectInfo.NumRxUnicastOkInPeriod++; + + // 2009.03.03 Leave DC mode immediately when detect high traffic + // DbgPrint("ending Seq %d\n", Frame_SeqNum(pduOS)); + if((ieee->state == IEEE80211_LINKED) /*&& !MgntInitAdapterInProgress(pMgntInfo)*/) + { + if( ((ieee->LinkDetectInfo.NumRxUnicastOkInPeriod +ieee->LinkDetectInfo.NumTxOkInPeriod) > 8 ) || + (ieee->LinkDetectInfo.NumRxUnicastOkInPeriod > 2) ) + { + if(ieee->LeisurePSLeave) + ieee->LeisurePSLeave(dev); + } + } + } + } +#endif + ieee->last_rx_ps_time = jiffies; //added by amy for reorder if(ieee->pHTInfo->bCurRxReorderEnable == false ||pTS == NULL){ @@ -2013,12 +2077,22 @@ int ieee80211_parse_info_param(struct ieee80211_device *ieee, info_element->data[1] == 0x13 && info_element->data[2] == 0x74)) { - printk("========>%s(): athros AP is exist\n",__FUNCTION__); + //printk("========>%s(): athros AP is exist\n",__FUNCTION__); network->atheros_cap_exist = true; } else network->atheros_cap_exist = false; + if ((info_element->len >= 3 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x50 && + info_element->data[2] == 0x43) ) + { + network->marvell_cap_exist = true; + //printk("========>%s(): marvel AP is exist\n",__FUNCTION__); + } + + if(info_element->len >= 3 && info_element->data[0] == 0x00 && info_element->data[1] == 0x40 && @@ -2219,7 +2293,8 @@ int ieee80211_parse_info_param(struct ieee80211_device *ieee, } if(!network->atheros_cap_exist && !network->broadcom_cap_exist && - !network->cisco_cap_exist && !network->ralink_cap_exist && !network->bssht.bdRT2RTAggregation) + !network->cisco_cap_exist && !network->ralink_cap_exist && !network->bssht.bdRT2RTAggregation && + !network->marvell_cap_exist) { network->unknown_cap_exist = true; } @@ -2333,6 +2408,7 @@ static inline int ieee80211_network_init( network->broadcom_cap_exist = false; network->ralink_cap_exist = false; network->atheros_cap_exist = false; + network->marvell_cap_exist = false; network->cisco_cap_exist = false; network->unknown_cap_exist = false; #ifdef THOMAS_TURBO @@ -2463,6 +2539,7 @@ static inline void update_network(struct ieee80211_network *dst, dst->broadcom_cap_exist = src->broadcom_cap_exist; dst->ralink_cap_exist = src->ralink_cap_exist; dst->atheros_cap_exist = src->atheros_cap_exist; + dst->marvell_cap_exist = src->marvell_cap_exist; dst->cisco_cap_exist = src->cisco_cap_exist; dst->unknown_cap_exist = src->unknown_cap_exist; memcpy(dst->wpa_ie, src->wpa_ie, src->wpa_ie_len); @@ -2761,12 +2838,14 @@ void ieee80211_rx_mgt(struct ieee80211_device *ieee, struct ieee80211_hdr_4addr *header, struct ieee80211_rx_stats *stats) { +#if 0 if(ieee->sta_sleep || (ieee->ps != IEEE80211_PS_DISABLED && ieee->iw_mode == IW_MODE_INFRA && ieee->state == IEEE80211_LINKED)) { tasklet_schedule(&ieee->ps_task); } +#endif if(WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_PROBE_RESP && WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_BEACON) @@ -2780,6 +2859,15 @@ void ieee80211_rx_mgt(struct ieee80211_device *ieee, IEEE80211_DEBUG_SCAN("Beacon\n"); ieee80211_process_probe_response( ieee, (struct ieee80211_probe_response *)header, stats); + + //printk("----------->%s()\n", __func__); + if(ieee->sta_sleep || (ieee->ps != IEEE80211_PS_DISABLED && + ieee->iw_mode == IW_MODE_INFRA && + ieee->state == IEEE80211_LINKED)) + { + tasklet_schedule(&ieee->ps_task); + } + break; case IEEE80211_STYPE_PROBE_RESP: diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac.c index 9e923e29c455..ea96c4956930 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac.c @@ -646,7 +646,7 @@ void ieee80211_stop_send_beacons(struct ieee80211_device *ieee) void ieee80211_start_send_beacons(struct ieee80211_device *ieee) { if(ieee->start_send_beacons) - ieee->start_send_beacons(ieee->dev,ieee->basic_rate); + ieee->start_send_beacons(ieee->dev); if(ieee->softmac_features & IEEE_SOFTMAC_BEACONS) ieee80211_beacons_start(ieee); } @@ -686,6 +686,11 @@ void ieee80211_stop_scan(struct ieee80211_device *ieee) /* called with ieee->lock held */ void ieee80211_rtl_start_scan(struct ieee80211_device *ieee) { +#ifdef ENABLE_IPS + if(ieee->ieee80211_ips_leave_wq != NULL) + ieee->ieee80211_ips_leave_wq(ieee->dev); +#endif + #ifdef ENABLE_DOT11D if(IS_DOT11D_ENABLE(ieee) ) { @@ -1093,6 +1098,40 @@ struct sk_buff* ieee80211_null_func(struct ieee80211_device *ieee,short pwr) } +struct sk_buff* ieee80211_pspoll_func(struct ieee80211_device *ieee) +{ + struct sk_buff *skb; + struct ieee80211_pspoll_hdr* hdr; + +#ifdef USB_USE_ALIGNMENT + u32 Tmpaddr=0; + int alignment=0; + skb = dev_alloc_skb(sizeof(struct ieee80211_pspoll_hdr) + ieee->tx_headroom + USB_512B_ALIGNMENT_SIZE); +#else + skb = dev_alloc_skb(sizeof(struct ieee80211_pspoll_hdr)+ieee->tx_headroom); +#endif + if (!skb) + return NULL; + +#ifdef USB_USE_ALIGNMENT + Tmpaddr = (u32)skb->data; + alignment = Tmpaddr & 0x1ff; + skb_reserve(skb,(USB_512B_ALIGNMENT_SIZE - alignment)); +#endif + skb_reserve(skb, ieee->tx_headroom); + + hdr = (struct ieee80211_pspoll_hdr*)skb_put(skb,sizeof(struct ieee80211_pspoll_hdr)); + + memcpy(hdr->bssid, ieee->current_network.bssid, ETH_ALEN); + memcpy(hdr->ta, ieee->dev->dev_addr, ETH_ALEN); + + hdr->aid = cpu_to_le16(ieee->assoc_id | 0xc000); + hdr->frame_ctl = cpu_to_le16(IEEE80211_FTYPE_CTL |IEEE80211_STYPE_PSPOLL | IEEE80211_FCTL_PM); + + return skb; + +} + void ieee80211_resp_to_assoc_rq(struct ieee80211_device *ieee, u8* dest) { @@ -1582,6 +1621,11 @@ void ieee80211_associate_procedure_wq(struct ieee80211_device *ieee) { #endif ieee->sync_scan_hurryup = 1; +#ifdef ENABLE_IPS + if(ieee->ieee80211_ips_leave != NULL) + ieee->ieee80211_ips_leave(ieee->dev); +#endif + down(&ieee->wx_sem); if (ieee->data_hard_stop) @@ -1592,6 +1636,17 @@ void ieee80211_associate_procedure_wq(struct ieee80211_device *ieee) //ieee->set_chan(ieee->dev, ieee->current_network.channel); HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); +#ifdef ENABLE_IPS + if(ieee->eRFPowerState == eRfOff) + { + if(ieee->ieee80211_ips_leave_wq != NULL) + ieee->ieee80211_ips_leave_wq(ieee->dev); + + up(&ieee->wx_sem); + return; + } +#endif + ieee->associate_seq = 1; ieee80211_associate_step1(ieee); @@ -1918,43 +1973,92 @@ void ieee80211_sta_ps_send_null_frame(struct ieee80211_device *ieee, short pwr) } +void ieee80211_sta_ps_send_pspoll_frame(struct ieee80211_device *ieee) +{ + + struct sk_buff *buf = ieee80211_pspoll_func(ieee); + + if (buf) + softmac_ps_mgmt_xmit(buf, ieee); + +} short ieee80211_sta_ps_sleep(struct ieee80211_device *ieee, u32 *time_h, u32 *time_l) { int timeout = ieee->ps_timeout; u8 dtim; - /*if(ieee->ps == IEEE80211_PS_DISABLED || - ieee->iw_mode != IW_MODE_INFRA || - ieee->state != IEEE80211_LINKED) + PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(ieee->PowerSaveControl)); + if(ieee->LPSDelayCnt) + { + //printk("===============>Delay enter LPS for DHCP and ARP packets...\n"); + ieee->LPSDelayCnt --; return 0; - */ + } + dtim = ieee->current_network.dtim_data; - //printk("DTIM\n"); +// printk("%s():DTIM:%d\n",__FUNCTION__,dtim); if(!(dtim & IEEE80211_DTIM_VALID)) return 0; timeout = ieee->current_network.beacon_interval; //should we use ps_timeout value or beacon_interval //printk("VALID\n"); ieee->current_network.dtim_data = IEEE80211_DTIM_INVALID; - - if(dtim & ((IEEE80211_DTIM_UCAST | IEEE80211_DTIM_MBCAST)& ieee->ps)) + /* there's no need to nofity AP that I find you buffered with broadcast packet */ + if(dtim & (IEEE80211_DTIM_UCAST & ieee->ps)) return 2; - if(!time_after(jiffies, ieee->dev->trans_start + MSECS(timeout))) + if(!time_after(jiffies, ieee->dev->trans_start + MSECS(timeout))){ +// printk("%s():111Oh Oh ,it is not time out return 0\n",__FUNCTION__); return 0; - - if(!time_after(jiffies, ieee->last_rx_ps_time + MSECS(timeout))) + } + if(!time_after(jiffies, ieee->last_rx_ps_time + MSECS(timeout))){ +// printk("%s():222Oh Oh ,it is not time out return 0\n",__FUNCTION__); return 0; - + } if((ieee->softmac_features & IEEE_SOFTMAC_SINGLE_QUEUE ) && (ieee->mgmt_queue_tail != ieee->mgmt_queue_head)) return 0; if(time_l){ + if(ieee->bAwakePktSent == true) { + pPSC->LPSAwakeIntvl = 1;//tx wake one beacon + } else { + u8 MaxPeriod = 1; + + if(pPSC->LPSAwakeIntvl == 0) + pPSC->LPSAwakeIntvl = 1; + //pNdisCommon->RegLPSMaxIntvl /// 0x0 - eFastPs, 0xFF -DTIM, 0xNN - 0xNN * BeaconIntvl + if(pPSC->RegMaxLPSAwakeIntvl == 0) // Default (0x0 - eFastPs, 0xFF -DTIM, 0xNN - 0xNN * BeaconIntvl) + MaxPeriod = 1; // 1 Beacon interval + else if(pPSC->RegMaxLPSAwakeIntvl == 0xFF) // DTIM + MaxPeriod = ieee->current_network.dtim_period; + else + MaxPeriod = pPSC->RegMaxLPSAwakeIntvl; + pPSC->LPSAwakeIntvl = (pPSC->LPSAwakeIntvl >= MaxPeriod) ? MaxPeriod : (pPSC->LPSAwakeIntvl + 1); + } + { + u8 LPSAwakeIntvl_tmp = 0; + u8 period = ieee->current_network.dtim_period; + u8 count = ieee->current_network.tim.tim_count; + if(count == 0 ) { + if(pPSC->LPSAwakeIntvl > period) + LPSAwakeIntvl_tmp = period + (pPSC->LPSAwakeIntvl - period) -((pPSC->LPSAwakeIntvl-period)%period); + else + LPSAwakeIntvl_tmp = pPSC->LPSAwakeIntvl; + + } else { + if(pPSC->LPSAwakeIntvl > ieee->current_network.tim.tim_count) + LPSAwakeIntvl_tmp = count + (pPSC->LPSAwakeIntvl - count) -((pPSC->LPSAwakeIntvl-count)%period); + else + LPSAwakeIntvl_tmp = pPSC->LPSAwakeIntvl;//ieee->current_network.tim.tim_count;//pPSC->LPSAwakeIntvl; + } + //printk("=========>%s()assoc_id:%d(%#x),bAwakePktSent:%d,DTIM:%d, sleep interval:%d, LPSAwakeIntvl_tmp:%d, count:%d\n",__func__,ieee->assoc_id,cpu_to_le16(ieee->assoc_id),ieee->bAwakePktSent,ieee->current_network.dtim_period,pPSC->LPSAwakeIntvl,LPSAwakeIntvl_tmp,count); + *time_l = ieee->current_network.last_dtim_sta_time[0] - + (ieee->current_network.beacon_interval); + + MSECS(ieee->current_network.beacon_interval * LPSAwakeIntvl_tmp); // * ieee->current_network.dtim_period) * 1000; } + } if(time_h){ *time_h = ieee->current_network.last_dtim_sta_time[1]; @@ -1982,6 +2086,8 @@ inline void ieee80211_sta_ps(struct ieee80211_device *ieee) ieee->state != IEEE80211_LINKED)){ // #warning CHECK_LOCK_HERE + printk("=====>%s(): no need to ps,wake up!! ieee->ps is %d,ieee->iw_mode is %d,ieee->state is %d\n", + __FUNCTION__,ieee->ps,ieee->iw_mode,ieee->state); spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2); ieee80211_sta_wakeup(ieee, 1); @@ -1991,27 +2097,27 @@ inline void ieee80211_sta_ps(struct ieee80211_device *ieee) sleep = ieee80211_sta_ps_sleep(ieee,&th, &tl); /* 2 wake, 1 sleep, 0 do nothing */ - if(sleep == 0) + if(sleep == 0)//it is not time out or dtim is not valid + { + //printk("===========>sleep is 0,do nothing\n"); goto out; - + } if(sleep == 1){ - - if(ieee->sta_sleep == 1) + //printk("===========>sleep is 1,to sleep\n"); + if(ieee->sta_sleep == 1){ + //printk("%s(1): sta_sleep = 1, sleep again ++++++++++ \n", __func__); ieee->enter_sleep_state(ieee->dev,th,tl); + } else if(ieee->sta_sleep == 0){ // printk("send null 1\n"); spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2); if(ieee->ps_is_queue_empty(ieee->dev)){ - - ieee->sta_sleep = 2; - ieee->ack_tx_to_ieee = 1; - + //printk("%s(2): sta_sleep = 0, notify AP we will sleeped ++++++++++ SendNullFunctionData\n", __func__); ieee80211_sta_ps_send_null_frame(ieee,1); - ieee->ps_th = th; ieee->ps_tl = tl; } @@ -2019,11 +2125,13 @@ inline void ieee80211_sta_ps(struct ieee80211_device *ieee) } + ieee->bAwakePktSent = false;//after null to power save we set it to false. not listen every beacon. }else if(sleep == 2){ -//#warning CHECK_LOCK_HERE + //printk("==========>sleep is 2,to wakeup\n"); spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2); + //printk("%s(3): pkt buffered in ap will awake ++++++++++ ieee80211_sta_wakeup\n", __func__); ieee80211_sta_wakeup(ieee,1); spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2); @@ -2038,9 +2146,19 @@ void ieee80211_sta_wakeup(struct ieee80211_device *ieee, short nl) { if(ieee->sta_sleep == 0){ if(nl){ - printk("Warning: driver is probably failing to report TX ps error\n"); - ieee->ack_tx_to_ieee = 1; - ieee80211_sta_ps_send_null_frame(ieee, 0); + if(ieee->pHTInfo->IOTAction & HT_IOT_ACT_NULL_DATA_POWER_SAVING) + { + //printk("%s(1): notify AP we are awaked ++++++++++ SendNullFunctionData\n", __func__); + //printk("Warning: driver is probably failing to report TX ps error\n"); + ieee->ack_tx_to_ieee = 1; + ieee80211_sta_ps_send_null_frame(ieee, 0); + } + else + { + ieee->ack_tx_to_ieee = 1; + //printk("%s(2): notify AP we are awaked ++++++++++ Send PS-Poll\n", __func__); + ieee80211_sta_ps_send_pspoll_frame(ieee); + } } return; @@ -2048,12 +2166,27 @@ void ieee80211_sta_wakeup(struct ieee80211_device *ieee, short nl) if(ieee->sta_sleep == 1) ieee->sta_wake_up(ieee->dev); + if(nl){ - ieee->sta_sleep = 0; + if(ieee->pHTInfo->IOTAction & HT_IOT_ACT_NULL_DATA_POWER_SAVING) + { + //printk("%s(3): notify AP we are awaked ++++++++++ SendNullFunctionData\n", __func__); + //printk("Warning: driver is probably failing to report TX ps error\n"); + ieee->ack_tx_to_ieee = 1; + ieee80211_sta_ps_send_null_frame(ieee, 0); + } + else + { + ieee->ack_tx_to_ieee = 1; + ieee->polling = true; + //printk("%s(4): notify AP we are awaked ++++++++++ Send PS-Poll\n", __func__); + //ieee80211_sta_ps_send_null_frame(ieee, 0); + ieee80211_sta_ps_send_pspoll_frame(ieee); + } - if(nl){ - ieee->ack_tx_to_ieee = 1; - ieee80211_sta_ps_send_null_frame(ieee, 0); + } else { + ieee->sta_sleep = 0; + ieee->polling = false; } } @@ -2067,23 +2200,30 @@ void ieee80211_ps_tx_ack(struct ieee80211_device *ieee, short success) /* Null frame with PS bit set */ if(success){ ieee->sta_sleep = 1; + //printk("notify AP we will sleep and send null ok, so sleep now++++++++++ enter_sleep_state\n"); ieee->enter_sleep_state(ieee->dev,ieee->ps_th,ieee->ps_tl); } - /* if the card report not success we can't be sure the AP - * has not RXed so we can't assume the AP believe us awake - */ - } - /* 21112005 - tx again null without PS bit if lost */ - else { + } else {/* 21112005 - tx again null without PS bit if lost */ if((ieee->sta_sleep == 0) && !success){ spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2); - ieee80211_sta_ps_send_null_frame(ieee, 0); + //ieee80211_sta_ps_send_null_frame(ieee, 0); + if(ieee->pHTInfo->IOTAction & HT_IOT_ACT_NULL_DATA_POWER_SAVING) + { + //printk("notify AP we will sleep but send bull failed, so resend++++++++++ SendNullFunctionData\n"); + ieee80211_sta_ps_send_null_frame(ieee, 0); + } + else + { + //printk("notify AP we are awaked but send pspoll failed, so resend++++++++++ Send PS-Poll\n"); + ieee80211_sta_ps_send_pspoll_frame(ieee); + } spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2); } } spin_unlock_irqrestore(&ieee->lock, flags); } + void ieee80211_process_action(struct ieee80211_device* ieee, struct sk_buff* skb) { struct ieee80211_hdr* header = (struct ieee80211_hdr*)skb->data; @@ -2227,7 +2367,7 @@ ieee80211_rx_frame_softmac(struct ieee80211_device *ieee, struct sk_buff *skb, { if (!ieee->GetNmodeSupportBySecCfg(ieee->dev)) { - // WEP or TKIP encryption + // WEP or TKIP encryption if(IsHTHalfNmodeAPs(ieee)) { bSupportNmode = true; @@ -2238,7 +2378,7 @@ ieee80211_rx_frame_softmac(struct ieee80211_device *ieee, struct sk_buff *skb, bSupportNmode = false; bHalfSupportNmode = false; } - printk("==========>to link with AP using SEC(%d, %d)", bSupportNmode, bHalfSupportNmode); + printk("==========>to link with AP using SEC(%d, %d)\n", bSupportNmode, bHalfSupportNmode); } } /* Dummy wirless mode setting to avoid encryption issue */ @@ -2574,6 +2714,7 @@ void ieee80211_start_ibss_wq(struct ieee80211_device *ieee) ieee->ssid_set = 1; } + ieee->state = IEEE80211_NOLINK; /* check if we have this cell in our network list */ ieee80211_softmac_check_all_nets(ieee); @@ -2705,6 +2846,10 @@ void ieee80211_start_bss(struct ieee80211_device *ieee) spin_lock_irqsave(&ieee->lock, flags); if (ieee->state == IEEE80211_NOLINK){ +#ifdef ENABLE_IPS + if(ieee->ieee80211_ips_leave_wq != NULL) + ieee->ieee80211_ips_leave_wq(ieee->dev); +#endif ieee->actscanning = true; ieee80211_rtl_start_scan(ieee); } @@ -2823,21 +2968,23 @@ struct sk_buff *ieee80211_get_beacon(struct ieee80211_device *ieee) return skb; } -void ieee80211_softmac_stop_protocol(struct ieee80211_device *ieee) +void ieee80211_softmac_stop_protocol(struct ieee80211_device *ieee, u8 shutdown) { ieee->sync_scan_hurryup = 1; down(&ieee->wx_sem); - ieee80211_stop_protocol(ieee); + ieee80211_stop_protocol(ieee, shutdown); up(&ieee->wx_sem); } -void ieee80211_stop_protocol(struct ieee80211_device *ieee) +void ieee80211_stop_protocol(struct ieee80211_device *ieee, u8 shutdown) { if (!ieee->proto_started) return; - ieee->proto_started = 0; + if(shutdown) + ieee->proto_started = 0; + ieee->proto_stoppping = 1; ieee80211_stop_send_beacons(ieee); del_timer_sync(&ieee->associate_timer); @@ -2849,6 +2996,8 @@ void ieee80211_stop_protocol(struct ieee80211_device *ieee) ieee80211_disassociate(ieee); RemoveAllTS(ieee); //added as we disconnect from the previous BSS, Remove all TS + + ieee->proto_stoppping = 0; } void ieee80211_softmac_start_protocol(struct ieee80211_device *ieee) @@ -2894,6 +3043,8 @@ void ieee80211_start_protocol(struct ieee80211_device *ieee) ieee->init_wmmparam_flag = 0;//reinitialize AC_xx_PARAM registers. + ieee->state = IEEE80211_NOLINK; + /* if the user set the MAC of the ad-hoc cell and then * switch to managed mode, shall we make sure that association @@ -3013,7 +3164,9 @@ void ieee80211_softmac_init(struct ieee80211_device *ieee) #endif sema_init(&ieee->wx_sem, 1); sema_init(&ieee->scan_sem, 1); - +#ifdef ENABLE_IPS + sema_init(&ieee->ips_sem,1); +#endif spin_lock_init(&ieee->mgmt_tx_lock); spin_lock_init(&ieee->beacon_lock); @@ -3537,5 +3690,6 @@ EXPORT_SYMBOL_NOVERS(ieee80211_stop_scan); EXPORT_SYMBOL_NOVERS(ieee80211_send_probe_requests); EXPORT_SYMBOL_NOVERS(ieee80211_softmac_scan_syncro); EXPORT_SYMBOL_NOVERS(ieee80211_start_scan_syncro); +EXPORT_SYMBOL_NOVERS(ieee80211_sta_ps_send_null_frame); +EXPORT_SYMBOL_NOVERS(ieee80211_sta_ps_send_pspoll_frame); #endif -//EXPORT_SYMBOL(ieee80211_sta_ps_send_null_frame); diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac_wx.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac_wx.c index 7c21aaab9063..1bbd49f1d6f6 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac_wx.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_softmac_wx.c @@ -160,7 +160,7 @@ int ieee80211_wx_set_wap(struct ieee80211_device *ieee, } if (ifup) - ieee80211_stop_protocol(ieee); + ieee80211_stop_protocol(ieee,true); /* just to avoid to give inconsistent infos in the * get wx method. not really needed otherwise @@ -302,7 +302,7 @@ int ieee80211_wx_set_mode(struct ieee80211_device *ieee, struct iw_request_info if (!ieee->proto_started){ ieee->iw_mode = wrqu->mode; }else{ - ieee80211_stop_protocol(ieee); + ieee80211_stop_protocol(ieee,true); ieee->iw_mode = wrqu->mode; ieee80211_start_protocol(ieee); } @@ -326,6 +326,17 @@ void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee) int b40M = 0; static int count = 0; chan = ieee->current_network.channel; + +#ifdef ENABLE_LPS + if (ieee->LeisurePSLeave) { + ieee->LeisurePSLeave(ieee->dev); + } + + /* notify AP to be in PS mode */ + ieee80211_sta_ps_send_null_frame(ieee, 1); + ieee80211_sta_ps_send_null_frame(ieee, 1); +#endif + netif_carrier_off(ieee->dev); if (ieee->data_hard_stop) @@ -360,6 +371,12 @@ void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee) ieee->InitialGainHandler(ieee->dev,IG_Restore); ieee->state = IEEE80211_LINKED; ieee->link_change(ieee->dev); + +#ifdef ENABLE_LPS + /* Notify AP that I wake up again */ + ieee80211_sta_ps_send_null_frame(ieee, 0); +#endif + // To prevent the immediately calling watch_dog after scan. if(ieee->LinkDetectInfo.NumRecvBcnInPeriod==0||ieee->LinkDetectInfo.NumRecvDataInPeriod==0 ) { @@ -429,8 +446,9 @@ int ieee80211_wx_set_essid(struct ieee80211_device *ieee, goto out; } - if(proto_started) - ieee80211_stop_protocol(ieee); + if(proto_started){ + ieee80211_stop_protocol(ieee,true); + } /* this is just to be sure that the GET wx callback diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_tx.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_tx.c index 0710d9e30dba..a75f3668a40a 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_tx.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_tx.c @@ -334,6 +334,13 @@ void ieee80211_tx_query_agg_cap(struct ieee80211_device* ieee, struct sk_buff* s if(!Adapter->HalFunc.GetNmodeSupportBySecCfgHandler(Adapter)) return; #endif + + if(tcb_desc->bdhcp)// || ieee->CntAfterLink<2) + { + return; + } + + #if 1 if(!ieee->GetNmodeSupportBySecCfg(ieee->dev)) { @@ -628,6 +635,7 @@ int ieee80211_rtl_xmit(struct sk_buff *skb, struct net_device *dev) int qos_actived = ieee->current_network.qos_data.active; struct ieee80211_crypt_data* crypt; + bool bdhcp =false; cb_desc *tcb_desc; @@ -672,6 +680,55 @@ int ieee80211_rtl_xmit(struct sk_buff *skb, struct net_device *dev) } #endif + // The following is for DHCP and ARP packet, we use cck1M to tx these packets and let LPS awake some time + // to prevent DHCP protocol fail + if (skb->len > 282){//MINIMUM_DHCP_PACKET_SIZE) { + if (ETH_P_IP == ether_type) {// IP header + const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14); + if (IPPROTO_UDP == ip->protocol) {//FIXME windows is 11 but here UDP in linux kernel is 17. + struct udphdr *udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); + //if(((ntohs(udp->source) == 68) && (ntohs(udp->dest) == 67)) || + /// ((ntohs(udp->source) == 67) && (ntohs(udp->dest) == 68))) { + if(((((u8 *)udp)[1] == 68) && (((u8 *)udp)[3] == 67)) || + ((((u8 *)udp)[1] == 67) && (((u8 *)udp)[3] == 68))) { + // 68 : UDP BOOTP client + // 67 : UDP BOOTP server + printk("DHCP pkt src port:%d, dest port:%d!!\n", ((u8 *)udp)[1],((u8 *)udp)[3]); + // Use low rate to send DHCP packet. + //if(pMgntInfo->IOTAction & HT_IOT_ACT_WA_IOT_Broadcom) + //{ + // tcb_desc->DataRate = MgntQuery_TxRateExcludeCCKRates(ieee);//0xc;//ofdm 6m + // tcb_desc->bTxDisableRateFallBack = false; + //} + //else + //pTcb->DataRate = Adapter->MgntInfo.LowestBasicRate; + //RTPRINT(FDM, WA_IOT, ("DHCP TranslateHeader(), pTcb->DataRate = 0x%x\n", pTcb->DataRate)); + + bdhcp = true; +#ifdef _RTL8192_EXT_PATCH_ + ieee->LPSDelayCnt = 100;//pPSC->LPSAwakeIntvl*2; //AMY,090701 +#else + ieee->LPSDelayCnt = 100;//pPSC->LPSAwakeIntvl*2; +#endif + } + } + }else if(ETH_P_ARP == ether_type){// IP ARP packet + printk("=================>DHCP Protocol start tx ARP pkt!!\n"); + bdhcp = true; + ieee->LPSDelayCnt = ieee->current_network.tim.tim_count; + + //if(pMgntInfo->IOTAction & HT_IOT_ACT_WA_IOT_Broadcom) + //{ + // tcb_desc->DataRate = MgntQuery_TxRateExcludeCCKRates(Adapter->MgntInfo.mBrates);//0xc;//ofdm 6m + // tcb_desc->bTxDisableRateFallBack = FALSE; + //} + //else + // tcb_desc->DataRate = Adapter->MgntInfo.LowestBasicRate; + //RTPRINT(FDM, WA_IOT, ("ARP TranslateHeader(), pTcb->DataRate = 0x%x\n", pTcb->DataRate)); + + } + } + /* Save source and destination addresses */ memcpy(&dest, skb->data, ETH_ALEN); memcpy(&src, skb->data+ETH_ALEN, ETH_ALEN); @@ -895,6 +952,25 @@ int ieee80211_rtl_xmit(struct sk_buff *skb, struct net_device *dev) else //tcb_desc->data_rate = CURRENT_RATE(ieee->current_network.mode, ieee->rate, ieee->HTCurrentOperaRate); tcb_desc->data_rate = CURRENT_RATE(ieee->mode, ieee->rate, ieee->HTCurrentOperaRate); + + if(bdhcp == true){ + // Use low rate to send DHCP packet. + //if(ieee->pHTInfo->IOTAction & HT_IOT_ACT_WA_IOT_Broadcom) { + // tcb_desc->data_rate = MGN_1M;//MgntQuery_TxRateExcludeCCKRates(ieee);//0xc;//ofdm 6m + // tcb_desc->bTxDisableRateFallBack = false; + //} + //else + { + tcb_desc->data_rate = MGN_1M; + tcb_desc->bTxDisableRateFallBack = 1; + } + + tcb_desc->RATRIndex = 7; + tcb_desc->bTxUseDriverAssingedRate = 1; + tcb_desc->bdhcp = 1; + } + + ieee80211_qurey_ShortPreambleMode(ieee, tcb_desc); ieee80211_tx_query_agg_cap(ieee, txb->fragments[0], tcb_desc); ieee80211_query_HTCapShortGI(ieee, tcb_desc); diff --git a/drivers/staging/rtl8192e/ieee80211/rtl819x_HT.h b/drivers/staging/rtl8192e/ieee80211/rtl819x_HT.h index 992b71825a8b..f968817d073c 100644 --- a/drivers/staging/rtl8192e/ieee80211/rtl819x_HT.h +++ b/drivers/staging/rtl8192e/ieee80211/rtl819x_HT.h @@ -458,7 +458,8 @@ typedef enum _HT_IOT_PEER HT_IOT_PEER_RALINK = 3, HT_IOT_PEER_ATHEROS = 4, HT_IOT_PEER_CISCO= 5, - HT_IOT_PEER_MAX = 6 + HT_IOT_PEER_MARVELL=6, + HT_IOT_PEER_MAX = 7 }HT_IOT_PEER_E, *PHTIOT_PEER_E; // @@ -475,6 +476,7 @@ typedef enum _HT_IOT_ACTION{ HT_IOT_ACT_CDD_FSYNC = 0x00000080, HT_IOT_ACT_PURE_N_MODE = 0x00000100, HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200, + HT_IOT_ACT_NULL_DATA_POWER_SAVING = 0x00800000, }HT_IOT_ACTION_E, *PHT_IOT_ACTION_E; #endif //_RTL819XU_HTTYPE_H_ diff --git a/drivers/staging/rtl8192e/ieee80211/rtl819x_HTProc.c b/drivers/staging/rtl8192e/ieee80211/rtl819x_HTProc.c index 1e392141779a..c93247362fe8 100644 --- a/drivers/staging/rtl8192e/ieee80211/rtl819x_HTProc.c +++ b/drivers/staging/rtl8192e/ieee80211/rtl819x_HTProc.c @@ -32,7 +32,7 @@ u16 MCS_DATA_RATE[2][2][77] = static u8 UNKNOWN_BORADCOM[3] = {0x00, 0x14, 0xbf}; static u8 LINKSYSWRT330_LINKSYSWRT300_BROADCOM[3] = {0x00, 0x1a, 0x70}; static u8 LINKSYSWRT350_LINKSYSWRT150_BROADCOM[3] = {0x00, 0x1d, 0x7e}; -static u8 NETGEAR834Bv2_BROADCOM[3] = {0x00, 0x1b, 0x2f}; +//static u8 NETGEAR834Bv2_BROADCOM[3] = {0x00, 0x1b, 0x2f}; static u8 BELKINF5D8233V1_RALINK[3] = {0x00, 0x17, 0x3f}; //cosa 03202008 static u8 BELKINF5D82334V3_RALINK[3] = {0x00, 0x1c, 0xdf}; static u8 PCI_RALINK[3] = {0x00, 0x90, 0xcc}; @@ -40,6 +40,7 @@ static u8 EDIMAX_RALINK[3] = {0x00, 0x0e, 0x2e}; static u8 AIRLINK_RALINK[3] = {0x00, 0x18, 0x02}; static u8 DLINK_ATHEROS[3] = {0x00, 0x1c, 0xf0}; static u8 CISCO_BROADCOM[3] = {0x00, 0x17, 0x94}; +static u8 LINKSYS_MARVELL_4400N[3] = {0x00, 0x14, 0xa4}; // 2008/04/01 MH For Cisco G mode RX TP We need to change FW duration. Shoud we put the // code in other place?? @@ -349,12 +350,12 @@ bool IsHTHalfNmodeAPs(struct ieee80211_device* ieee) bool retValue = false; struct ieee80211_network* net = &ieee->current_network; #if 0 - if(pMgntInfo->bHalfNMode == false) + if(ieee->bHalfNMode == false) retValue = false; else #endif if((memcmp(net->bssid, BELKINF5D8233V1_RALINK, 3)==0) || - (memcmp(net->bssid, BELKINF5D82334V3_RALINK, 3)==0) || + (memcmp(net->bssid, BELKINF5D82334V3_RALINK, 3)==0) || (memcmp(net->bssid, PCI_RALINK, 3)==0) || (memcmp(net->bssid, EDIMAX_RALINK, 3)==0) || (memcmp(net->bssid, AIRLINK_RALINK, 3)==0) || @@ -363,7 +364,7 @@ bool IsHTHalfNmodeAPs(struct ieee80211_device* ieee) else if((memcmp(net->bssid, UNKNOWN_BORADCOM, 3)==0) || (memcmp(net->bssid, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)|| (memcmp(net->bssid, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3)==0)|| - (memcmp(net->bssid, NETGEAR834Bv2_BROADCOM, 3)==0) || + //(memcmp(net->bssid, NETGEAR834Bv2_BROADCOM, 3)==0) || (net->broadcom_cap_exist)) retValue = true; else if(net->bssht.bdRT2RTAggregation) @@ -387,13 +388,15 @@ void HTIOTPeerDetermine(struct ieee80211_device* ieee) struct ieee80211_network* net = &ieee->current_network; if(net->bssht.bdRT2RTAggregation) pHTInfo->IOTPeer = HT_IOT_PEER_REALTEK; - else if(net->broadcom_cap_exist) + else if(net->broadcom_cap_exist){ pHTInfo->IOTPeer = HT_IOT_PEER_BROADCOM; + } else if((memcmp(net->bssid, UNKNOWN_BORADCOM, 3)==0) || (memcmp(net->bssid, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)|| - (memcmp(net->bssid, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3)==0)|| - (memcmp(net->bssid, NETGEAR834Bv2_BROADCOM, 3)==0) ) + (memcmp(net->bssid, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3)==0)){//|| + //(memcmp(net->bssid, NETGEAR834Bv2_BROADCOM, 3)==0) ){ pHTInfo->IOTPeer = HT_IOT_PEER_BROADCOM; + } else if((memcmp(net->bssid, BELKINF5D8233V1_RALINK, 3)==0) || (memcmp(net->bssid, BELKINF5D82334V3_RALINK, 3)==0) || (memcmp(net->bssid, PCI_RALINK, 3)==0) || @@ -405,6 +408,10 @@ void HTIOTPeerDetermine(struct ieee80211_device* ieee) pHTInfo->IOTPeer = HT_IOT_PEER_ATHEROS; else if(memcmp(net->bssid, CISCO_BROADCOM, 3)==0) pHTInfo->IOTPeer = HT_IOT_PEER_CISCO; + else if ((memcmp(net->bssid, LINKSYS_MARVELL_4400N, 3) == 0) || + net->marvell_cap_exist){ + pHTInfo->IOTPeer = HT_IOT_PEER_MARVELL; + } else pHTInfo->IOTPeer = HT_IOT_PEER_UNKNOWN; @@ -442,6 +449,18 @@ u8 HTIOTActIsDisableMCS14(struct ieee80211_device* ieee, u8* PeerMacAddr) return ret; } +u8 HTIOTActIsForcedCTS2Self(struct ieee80211_device *ieee, struct ieee80211_network *network) +{ + u8 retValue = 0; + //if(network->marvell_cap_exist) + if(ieee->pHTInfo->IOTPeer == HT_IOT_PEER_MARVELL) + { + retValue = 1; + } + + return retValue; +} + /** * Function: HTIOTActIsDisableMCS15 @@ -578,6 +597,23 @@ u8 HTIOTActIsCCDFsync(u8* PeerMacAddr) return retValue; } +// +// Send null data for to tell AP that we are awake. +// +bool +HTIOTActIsNullDataPowerSaving(struct ieee80211_device* ieee,struct ieee80211_network *network) +{ + bool retValue = false; + + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + { + if(pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) // ||(pBssDesc->Vender == HT_IOT_PEER_ATHEROS && pBssDesc->SubTypeOfVender == HT_IOT_PEER_ATHEROS_DIR635)) + return true; + + } + return retValue; +} + void HTResetIOTSetting( PRT_HIGH_THROUGHPUT pHTInfo ) @@ -1071,6 +1107,13 @@ void HTOnAssocRsp(struct ieee80211_device *ieee) // Config and configure A-MSDU setting // pHTInfo->bCurrent_AMSDU_Support = pHTInfo->bAMSDU_Support; + if (ieee->rtllib_ap_sec_type && + (ieee->rtllib_ap_sec_type(ieee)&(SEC_ALG_WEP|SEC_ALG_TKIP))){ + if( (pHTInfo->IOTPeer== HT_IOT_PEER_ATHEROS) || + (pHTInfo->IOTPeer == HT_IOT_PEER_UNKNOWN) ) + pHTInfo->bCurrentAMPDUEnable = false; + } + nMaxAMSDUSize = (pPeerHTCap->MaxAMSDUSize==0)?3839:7935; @@ -1515,6 +1558,9 @@ void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80 bIOTAction = HTIOTActIsDisableMCS14(ieee, pNetwork->bssid); if(bIOTAction) pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_MCS14; + bIOTAction = HTIOTActIsForcedCTS2Self(ieee, pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF; bIOTAction = HTIOTActIsDisableMCS15(ieee); if(bIOTAction) @@ -1537,6 +1583,9 @@ void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80 if(bIOTAction) pHTInfo->IOTAction |= HT_IOT_ACT_CDD_FSYNC; + bIOTAction = HTIOTActIsNullDataPowerSaving(ieee, pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_NULL_DATA_POWER_SAVING; } else diff --git a/drivers/staging/rtl8192e/r8190_rtl8256.c b/drivers/staging/rtl8192e/r8190_rtl8256.c index 3d67fbb65b96..1bd054d42f24 100644 --- a/drivers/staging/rtl8192e/r8190_rtl8256.c +++ b/drivers/staging/rtl8192e/r8190_rtl8256.c @@ -429,11 +429,12 @@ SetRFPowerState8190( bool bResult = true; //u8 eRFPath; u8 i = 0, QueueID = 0; - ptx_ring head=NULL,tail=NULL; + //ptx_ring head=NULL,tail=NULL; + struct rtl8192_tx_ring *ring = NULL; if(priv->SetRFPowerStateInProgress == true) return false; - RT_TRACE(COMP_POWER, "===========> SetRFPowerState8190()!\n"); + //RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n"); priv->SetRFPowerStateInProgress = true; switch(priv->rf_chip) @@ -442,11 +443,11 @@ SetRFPowerState8190( switch( eRFPowerState ) { case eRfOn: - RT_TRACE(COMP_POWER, "SetRFPowerState8190() eRfOn !\n"); + //RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn !\n"); //RXTX enable control: On //for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) - // PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x2); - #ifdef RTL8190P + // PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x2); +#ifdef RTL8190P if(priv->rf_type == RF_2T4R) { //enable RF-Chip A/B @@ -479,36 +480,92 @@ SetRFPowerState8190( //analog to digital part2 on rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1800, 0x3); // 0x880[12:11] } - #else - write_nic_byte(dev, ANAPAR, 0x37);//160MHz - write_nic_byte(dev, MacBlkCtrl, 0x17); // 0x403 - mdelay(1); - //enable clock 80/88 MHz - - priv->bHwRfOffAction = 0; - //} - - // Baseband reset 2008.09.30 add - write_nic_byte(dev, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0)); - - //2 AFE - // 2008.09.30 add - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x20000000, 0x1); // 0x884 - //analog to digital part2 on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] - //digital to analog on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x98, 0x13); // 0x880[4:3] - //analog to digital on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf03, 0xf03);// 0x88c[9:8] - //rx antenna on - //PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] - //rx antenna on 2008.09.30 mark - //PHY_SetBBReg(Adapter, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] - - //2 RF - //enable RF-Chip A/B + else if(priv->rf_type == RF_1T1R) //RF-C + { + //enable RF-Chip C/D + rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4] + //analog to digital on + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x400, 0x1);// 0x88c[10] + //digital to analog on + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x80, 0x1); // 0x880[7] + //rx antenna on + rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x4, 0x1);// 0xc04[2] + //rx antenna on + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x4, 0x1);// 0xd04[2] + //analog to digital part2 on + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x800, 0x1); // 0x880[11] + } + +#elif defined RTL8192E + // turn on RF + if((priv->ieee80211->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) + { // The current RF state is OFF and the RF OFF level is halting the NIC, re-initialize the NIC. + bool rtstatus = true; + u32 InitilizeCount = 3; + do + { + InitilizeCount--; + priv->RegRfOff = false; + rtstatus = NicIFEnableNIC(dev); + }while( (rtstatus != true) &&(InitilizeCount >0) ); + + if(rtstatus != true) + { + RT_TRACE(COMP_ERR,"%s():Initialize Adapter fail,return\n",__FUNCTION__); + priv->SetRFPowerStateInProgress = false; + return false; + } + + RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); + } else { + write_nic_byte(dev, ANAPAR, 0x37);//160MHz + //write_nic_byte(dev, MacBlkCtrl, 0x17); // 0x403 + mdelay(1); + //enable clock 80/88 MHz + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2] + priv->bHwRfOffAction = 0; + //} + + //RF-A, RF-B + //enable RF-Chip A/B rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] - rtl8192_setBBreg(dev, rFPGA0_XB_RFInterfaceOE, BIT4, 0x1); // 0x864[4] + //analog to digital on + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] + //digital to analog on + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3] + //rx antenna on + rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] + //rx antenna on + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] + //analog to digital part2 on + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] + + // Baseband reset 2008.09.30 add + //write_nic_byte(dev, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0)); + + //2 AFE + // 2008.09.30 add + //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x20000000, 0x1); // 0x884 + //analog to digital part2 on + //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] + + + //digital to analog on + //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x98, 0x13); // 0x880[4:3] + //analog to digital on + //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf03, 0xf03);// 0x88c[9:8] + //rx antenna on + //PHY_SetBBReg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] + //rx antenna on 2008.09.30 mark + //PHY_SetBBReg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] + + //2 RF + //enable RF-Chip A/B + //rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] + //rtl8192_setBBreg(dev, rFPGA0_XB_RFInterfaceOE, BIT4, 0x1); // 0x864[4] + + } + #endif break; @@ -517,119 +574,137 @@ SetRFPowerState8190( // By Bruce, 2008-01-16. // case eRfSleep: - case eRfOff: - RT_TRACE(COMP_POWER, "SetRFPowerState8190() eRfOff/Sleep !\n"); - if (pPSC->bLeisurePs) + { + // HW setting had been configured with deeper mode. + if(priv->ieee80211->eRFPowerState == eRfOff) + break; + + // Update current RF state variable. + //priv->ieee80211->eRFPowerState = eRFPowerState; + + //if (pPSC->bLeisurePs) { for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { - switch(QueueID) { - case MGNT_QUEUE: - tail=priv->txmapringtail; - head=priv->txmapringhead; + ring = &priv->tx_ring[QueueID]; + + if(skb_queue_len(&ring->queue) == 0) + { + QueueID++; + continue; + } + else + { + RT_TRACE((COMP_POWER|COMP_RF), "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); + udelay(10); + i++; + } + + if(i >= MAX_DOZE_WAITING_TIMES_9x) + { + RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); break; + } + } + } - case BK_QUEUE: - tail=priv->txbkpringtail; - head=priv->txbkpringhead; + //if(Adapter->HardwareType == HARDWARE_TYPE_RTL8190P) +#ifdef RTL8190P + { + PHY_SetRtl8190pRfOff(dev); + } + //else if(Adapter->HardwareType == HARDWARE_TYPE_RTL8192E) +#elif defined RTL8192E + { + PHY_SetRtl8192eRfOff(dev); + } +#endif + } break; - case BE_QUEUE: - tail=priv->txbepringtail; - head=priv->txbepringhead; - break; + case eRfOff: + //RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/Sleep !\n"); - case VI_QUEUE: - tail=priv->txvipringtail; - head=priv->txvipringhead; - break; + // Update current RF state variable. + //priv->ieee80211->eRFPowerState = eRFPowerState; - case VO_QUEUE: - tail=priv->txvopringtail; - head=priv->txvopringhead; - break; + // + // Disconnect with Any AP or STA. + // + for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) + { + ring = &priv->tx_ring[QueueID]; - default: - tail=head=NULL; - break; - } - if(tail == head) + if(skb_queue_len(&ring->queue) == 0) { - //DbgPrint("QueueID = %d", QueueID); QueueID++; continue; } else { - RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times BusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); + RT_TRACE(COMP_POWER, + "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); udelay(10); i++; } if(i >= MAX_DOZE_WAITING_TIMES_9x) { - RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times BusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); + RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); break; } } + + //if(Adapter->HardwareType == HARDWARE_TYPE_RTL8190P) +#if defined RTL8190P + { + PHY_SetRtl8190pRfOff(dev); } - #ifdef RTL8190P - if(priv->rf_type == RF_2T4R) + //else if(Adapter->HardwareType == HARDWARE_TYPE_RTL8192E) +#elif defined RTL8192E { - //disable RF-Chip A/B - rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] + //if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC) && priv->ieee80211->RfOffReason > RF_CHANGE_BY_PS) + if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) + { // Disable all components. + // + // Note: + // NicIFSetLinkStatus is a big problem when we indicate the status to OS, + // the OS(XP) will reset. But now, we cnnot find why the NIC is hard to receive + // packets after RF ON. Just keep this function here and still work to find out the root couse. + // By Bruce, 2009-05-01. + // + //NicIFSetLinkStatus( Adapter, RT_MEDIA_DISCONNECT ); + //if HW radio of , need to indicate scan complete first for not be reset. + //if(MgntScanInProgress(pMgntInfo)) + // MgntResetScanProcess( Adapter ); + + // <1> Disable Interrupt + //rtl8192_irq_disable(dev); + // <2> Stop all timer + //MgntCancelAllTimer(Adapter); + // <3> Disable Adapter + //NicIFHaltAdapter(Adapter, false); + NicIFDisableNIC(dev); + RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); + } + else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC)) + { // Normal case. + // IPS should go to this. + PHY_SetRtl8192eRfOff(dev); + } + } +#else + else + { + RT_TRACE(COMP_DBG,DBG_TRACE,("It is not 8190Pci and 8192PciE \n")); } - //disable RF-Chip C/D - rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x0); // 0x868[4] - //analog to digital off, for power save - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] - //digital to analog off, for power save - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0x0); // 0x880[8:5] - //rx antenna off - rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0] - //rx antenna off - rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0] - //analog to digital part2 off, for power save - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0x0); // 0x880[12:9] -#else //8192E - //2 RF - //disable RF-Chip A/B - rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] - rtl8192_setBBreg(dev, rFPGA0_XB_RFInterfaceOE, BIT4, 0x0); // 0x864[4] - //2 AFE - //analog to digital off, for power save - //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf03, 0x0); // 2008.09.30 Modify - //digital to analog off, for power save - //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3] - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x98, 0x0); // 0x880 2008.09.30 Modify - //rx antenna off 2008.09.30 mark - //PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0] - //rx antenna off 2008.09.30 mark - //PHY_SetBBReg(Adapter, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0] - //analog to digital part2 off, for power save - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5] - // 2008.09.30 add - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x20000000, 0x0); // 0x884 - - - //disable clock 80/88 MHz 2008.09.30 mark - //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, 0x4, 0x0); // 0x880[2] - //2 BB - // Baseband reset 2008.09.30 add - write_nic_byte(dev, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0)); // 0x101 - //MAC: off - write_nic_byte(dev, MacBlkCtrl, 0x0); // 0x403 - //slow down cpu/lbus clock from 160MHz to Lower - write_nic_byte(dev, ANAPAR, 0x07); // 0x 17 40MHz - priv->bHwRfOffAction = 0; - //} #endif + break; default: bResult = false; - RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknown state to set: 0x%X!!!\n", eRFPowerState); + RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState); break; } @@ -644,64 +719,11 @@ SetRFPowerState8190( { // Update current RF state variable. priv->ieee80211->eRFPowerState = eRFPowerState; - - switch(priv->rf_chip ) - { - case RF_8256: - switch(priv->ieee80211->eRFPowerState) - { - case eRfOff: - // - //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015 - // - if(priv->ieee80211->RfOffReason==RF_CHANGE_BY_IPS ) - { - #ifdef TO_DO - Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK); - #endif - } - else - { - // Turn off LED if RF is not ON. - #ifdef TO_DO - Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF); - #endif - } - break; - - case eRfOn: - // Turn on RF we are still linked, which might happen when - // we quickly turn off and on HW RF. 2006.05.12, by rcnjko. - if( priv->ieee80211->state == IEEE80211_LINKED) - { - #ifdef TO_DO - Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK); - #endif - } - else - { - // Turn off LED if RF is not ON. - #ifdef TO_DO - Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); - #endif - } - break; - - default: - // do nothing. - break; - }// Switch RF state - - break; - - default: - RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); - break; - }// Switch RFChipID } + //printk("%s()priv->ieee80211->eRFPowerState:%s\n" ,__func__,priv->ieee80211->eRFPowerState == eRfOn ? "On" : "Off"); priv->SetRFPowerStateInProgress = false; - RT_TRACE(COMP_POWER, "<=========== SetRFPowerState8190() bResult = %d!\n", bResult); + //RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n", bResult); return bResult; } diff --git a/drivers/staging/rtl8192e/r8192E.h b/drivers/staging/rtl8192e/r8192E.h index 61b6f250b917..f4be9cc11005 100644 --- a/drivers/staging/rtl8192e/r8192E.h +++ b/drivers/staging/rtl8192e/r8192E.h @@ -39,7 +39,7 @@ #include #include #include -#include "ieee80211.h" +#include "ieee80211/ieee80211.h" @@ -1003,6 +1003,11 @@ typedef struct r8192_priv int irq; short irq_enabled; struct ieee80211_device *ieee80211; +#ifdef ENABLE_LPS + bool ps_force; + bool force_lps; + bool bdisable_nic; +#endif bool being_init_adapter; u8 Rf_Mode; short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */ @@ -1477,7 +1482,7 @@ void write_nic_word(struct net_device *dev, int x,u16 y); void write_nic_dword(struct net_device *dev, int x,u32 y); void force_pci_posting(struct net_device *dev); -void rtl8192_rtx_disable(struct net_device *); +void rtl8192_halt_adapter(struct net_device *dev, bool reset); void rtl8192_rx_enable(struct net_device *); void rtl8192_tx_enable(struct net_device *); @@ -1512,5 +1517,19 @@ short rtl8192_is_tx_queue_empty(struct net_device *dev); #ifdef ENABLE_IPS void IPSEnter(struct net_device *dev); void IPSLeave(struct net_device *dev); +void InactivePsWorkItemCallback(struct net_device *dev); +void IPSLeave_wq(void *data); +void ieee80211_ips_leave_wq(struct net_device *dev); +void ieee80211_ips_leave(struct net_device *dev); +#endif +#ifdef ENABLE_LPS +void LeisurePSEnter(struct net_device *dev); +void LeisurePSLeave(struct net_device *dev); #endif + +bool NicIFEnableNIC(struct net_device* dev); +bool NicIFDisableNIC(struct net_device* dev); + +void rtl8192_irq_disable(struct net_device *dev); +void PHY_SetRtl8192eRfOff(struct net_device* dev); #endif diff --git a/drivers/staging/rtl8192e/r8192E_core.c b/drivers/staging/rtl8192e/r8192E_core.c index 0f6954863e69..662231968724 100644 --- a/drivers/staging/rtl8192e/r8192E_core.c +++ b/drivers/staging/rtl8192e/r8192E_core.c @@ -66,7 +66,7 @@ #endif #ifdef ENABLE_DOT11D -#include "dot11d.h" +#include "ieee80211/dot11d.h" #endif //set here to open your trace code. //WB @@ -75,7 +75,7 @@ u32 rt_global_debug_component = \ // COMP_EPROM | // COMP_PHY | // COMP_RF | - COMP_FIRMWARE | +// COMP_FIRMWARE | // COMP_TRACE | // COMP_DOWN | // COMP_SWBW | @@ -343,6 +343,141 @@ void write_nic_word(struct net_device *dev, int x,u16 y) #endif /* RTL_IO_MAP */ +u8 rtl8192e_ap_sec_type(struct ieee80211_device *ieee) +{ + //struct r8192_priv* priv = ieee80211_priv(dev); + //struct ieee80211_device *ieee = priv->ieee80211; + + static u8 ccmp_ie[4] = {0x00,0x50,0xf2,0x04}; + static u8 ccmp_rsn_ie[4] = {0x00, 0x0f, 0xac, 0x04}; + int wpa_ie_len= ieee->wpa_ie_len; + struct ieee80211_crypt_data* crypt; + int encrypt; + + crypt = ieee->crypt[ieee->tx_keyidx]; + + encrypt = (ieee->current_network.capability & WLAN_CAPABILITY_PRIVACY) ||\ + (ieee->host_encrypt && crypt && crypt->ops && \ + (0 == strcmp(crypt->ops->name,"WEP"))); + + /* simply judge */ + if(encrypt && (wpa_ie_len == 0)) { + // wep encryption, no N mode setting */ + return SEC_ALG_WEP; + } else if((wpa_ie_len != 0)) { + // parse pairwise key type */ + if (((ieee->wpa_ie[0] == 0xdd) && (!memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) || + ((ieee->wpa_ie[0] == 0x30) && (!memcmp(&ieee->wpa_ie[10],ccmp_rsn_ie, 4)))) + return SEC_ALG_CCMP; + else + return SEC_ALG_TKIP; + } else { + return SEC_ALG_NONE; + } +} + +void +rtl8192e_SetHwReg(struct net_device *dev,u8 variable,u8* val) +{ + struct r8192_priv* priv = ieee80211_priv(dev); + + switch(variable) + { + + case HW_VAR_BSSID: + write_nic_dword(dev, BSSIDR, ((u32*)(val))[0]); + write_nic_word(dev, BSSIDR+2, ((u16*)(val+2))[0]); + break; + + case HW_VAR_MEDIA_STATUS: + { + RT_OP_MODE OpMode = *((RT_OP_MODE *)(val)); + //LED_CTL_MODE LedAction = LED_CTL_NO_LINK; + u8 btMsr = read_nic_byte(dev, MSR); + + btMsr &= 0xfc; + + switch(OpMode) + { + case RT_OP_MODE_INFRASTRUCTURE: + btMsr |= MSR_INFRA; + //LedAction = LED_CTL_LINK; + break; + + case RT_OP_MODE_IBSS: + btMsr |= MSR_ADHOC; + // led link set seperate + break; + + case RT_OP_MODE_AP: + btMsr |= MSR_AP; + //LedAction = LED_CTL_LINK; + break; + + default: + btMsr |= MSR_NOLINK; + break; + } + + write_nic_byte(dev, MSR, btMsr); + + //priv->ieee80211->LedControlHandler(dev, LedAction); + } + break; + + case HW_VAR_CECHK_BSSID: + { + u32 RegRCR, Type; + + Type = ((u8*)(val))[0]; + //priv->ieee80211->GetHwRegHandler(dev, HW_VAR_RCR, (u8*)(&RegRCR)); + RegRCR = read_nic_dword(dev,RCR); + priv->ReceiveConfig = RegRCR; + + if (Type == true) + RegRCR |= (RCR_CBSSID); + else if (Type == false) + RegRCR &= (~RCR_CBSSID); + + //priv->ieee80211->SetHwRegHandler( dev, HW_VAR_RCR, (u8*)(&RegRCR) ); + write_nic_dword(dev, RCR,RegRCR); + priv->ReceiveConfig = RegRCR; + + } + break; + + case HW_VAR_SLOT_TIME: + { + //PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos; + //AC_CODING eACI; + + priv->slot_time = val[0]; + write_nic_byte(dev, SLOT_TIME, val[0]); + + } + break; + + case HW_VAR_ACK_PREAMBLE: + { + u32 regTmp = 0; + priv->short_preamble = (bool)(*(u8*)val ); + regTmp = priv->basic_rate; + if (priv->short_preamble) + regTmp |= BRSR_AckShortPmb; + write_nic_dword(dev, RRSR, regTmp); + } + break; + + case HW_VAR_CPU_RST: + write_nic_dword(dev, CPU_GEN, ((u32*)(val))[0]); + break; + + default: + break; + } + +} + /////////////////////////////////////////////////////////// @@ -365,11 +500,6 @@ void rtl8192_restart(struct work_struct *work); //void rtl8192_rq_tx_ack(struct work_struct *work); void watch_dog_timer_callback(unsigned long data); -#ifdef ENABLE_IPS -void IPSEnter(struct net_device *dev); -void IPSLeave(struct net_device *dev); -void InactivePsWorkItemCallback(struct net_device *dev); -#endif /**************************************************************************** -----------------------------PROCFS STUFF------------------------- *****************************************************************************/ @@ -707,7 +837,7 @@ static void rtl8192_irq_enable(struct net_device *dev) } -static void rtl8192_irq_disable(struct net_device *dev) +void rtl8192_irq_disable(struct net_device *dev) { struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); @@ -717,6 +847,7 @@ static void rtl8192_irq_disable(struct net_device *dev) } +#if 0 static void rtl8192_set_mode(struct net_device *dev,int mode) { u8 ecmd; @@ -727,7 +858,7 @@ static void rtl8192_set_mode(struct net_device *dev,int mode) ecmd=ecmd &~ (1<desc = NULL; } - +#if 0 static void rtl8192_beacon_disable(struct net_device *dev) { struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); @@ -873,38 +1004,116 @@ static void rtl8192_beacon_disable(struct net_device *dev) reg &= ~(IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER); write_nic_dword(priv->ieee80211->dev, INTA_MASK, reg); } +#endif + +void PHY_SetRtl8192eRfOff(struct net_device* dev ) +{ + //struct r8192_priv *priv = ieee80211_priv(dev); + + //disable RF-Chip A/B + rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); + //analog to digital off, for power save + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); + //digital to analog off, for power save + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); + //rx antenna off + rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); + //rx antenna off + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); + //analog to digital part2 off, for power save + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); + // Analog parameter!!Change bias and Lbus control. + write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07); + +} -void rtl8192_rtx_disable(struct net_device *dev) +void rtl8192_halt_adapter(struct net_device *dev, bool reset) { - u8 cmd; + //u8 cmd; struct r8192_priv *priv = ieee80211_priv(dev); - int i; + int i; + u8 OpMode; + u8 u1bTmp; + u32 ulRegRead; + + OpMode = RT_OP_MODE_NO_LINK; + priv->ieee80211->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode); +#if 1 + if(!priv->ieee80211->bSupportRemoteWakeUp) + { + u1bTmp = 0x0; // disable tx/rx. In 8185 we write 0x10 (Reset bit), but here we make reference to WMAC and wirte 0x0. 2006.11.21 Emily + //priv->ieee80211->SetHwRegHandler(dev, HW_VAR_COMMAND, &u1bTmp ); // Using HW_VAR_COMMAND instead of writing CMDR directly. Rewrited by Annie, 2006-04-07. + write_nic_byte(dev, CMDR, u1bTmp); + } +#else cmd=read_nic_byte(dev,CMDR); -// if(!priv->ieee80211->bSupportRemoteWakeUp) { - write_nic_byte(dev, CMDR, cmd &~ \ - (CR_TE|CR_RE)); -// } - force_pci_posting(dev); - mdelay(30); + write_nic_byte(dev, CMDR, cmd &~ (CR_TE|CR_RE)); +#endif - for(i = 0; i < MAX_QUEUE_SIZE; i++) { - skb_queue_purge(&priv->ieee80211->skb_waitQ [i]); - } - for(i = 0; i < MAX_QUEUE_SIZE; i++) { - skb_queue_purge(&priv->ieee80211->skb_aggQ [i]); - } + mdelay(20); + if(!reset) + { + //PlatformStallExecution(150000); + mdelay(150); + +#ifdef RTL8192E + priv->bHwRfOffAction = 2; +#endif + + // + // Call MgntActSet_RF_State instead to prevent RF config race condition. + // By Bruce, 2008-01-17. + // + if(!priv->ieee80211->bSupportRemoteWakeUp) + { + //MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_INIT); + //MgntActSet_RF_State(Adapter, eRfOff, Adapter->MgntInfo.RfOffReason); + //if(Adapter->HardwareType == HARDWARE_TYPE_RTL8190P) + + PHY_SetRtl8192eRfOff(dev); + + // 2006.11.30. System reset bit + //priv->ieee80211->GetHwRegHandler(dev, HW_VAR_CPU_RST, (u32*)(&ulRegRead) ); + ulRegRead = read_nic_dword(dev,CPU_GEN); + ulRegRead|=CPU_GEN_SYSTEM_RESET; + //priv->ieee80211->SetHwRegHandler(dev, HW_VAR_CPU_RST, &ulRegRead); + write_nic_dword(dev,CPU_GEN, ulRegRead); + } + else + { + //2008.06.03 for WOL + write_nic_dword(dev, WFCRC0, 0xffffffff); + write_nic_dword(dev, WFCRC1, 0xffffffff); + write_nic_dword(dev, WFCRC2, 0xffffffff); + + //Write PMR register + write_nic_byte(dev, PMR, 0x5); + //Disable tx, enanble rx + write_nic_byte(dev, MacBlkCtrl, 0xa); + } + } + + for(i = 0; i < MAX_QUEUE_SIZE; i++) { + skb_queue_purge(&priv->ieee80211->skb_waitQ [i]); + } + for(i = 0; i < MAX_QUEUE_SIZE; i++) { + skb_queue_purge(&priv->ieee80211->skb_aggQ [i]); + } skb_queue_purge(&priv->skb_queue); return; } +#if 0 static void rtl8192_reset(struct net_device *dev) { rtl8192_irq_disable(dev); printk("This is RTL819xP Reset procedure\n"); } +#endif static u16 rtl_rate[] = {10,20,55,110,60,90,120,180,240,360,480,540}; inline u16 rtl8192_rate2rate(short rate) @@ -954,6 +1163,12 @@ static void rtl8192_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, /* shall not be referred by command packet */ assert(queue_index != TXCMD_QUEUE); + if((priv->bHwRadioOff == true)||(!priv->up)) + { + kfree_skb(skb); + return; + } + //spin_lock_irqsave(&priv->tx_lock,flags); memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); @@ -996,6 +1211,13 @@ static int rtl8192_hard_start_xmit(struct sk_buff *skb,struct net_device *dev) cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); u8 queue_index = tcb_desc->queue_index; + if(queue_index != TXCMD_QUEUE){ + if((priv->bHwRadioOff == true)||(!priv->up)) + { + kfree_skb(skb); + return 0; + } + } //spin_lock_irqsave(&priv->tx_lock,flags); @@ -1379,6 +1601,15 @@ short rtl8192_tx(struct net_device *dev, struct sk_buff* skb) u8* pda_addr = NULL; int idx; + if(priv->bdisable_nic){ + RT_TRACE(COMP_ERR,"%s: ERR!! Nic is disabled! Can't tx packet len=%d qidx=%d!!!\n", __FUNCTION__, skb->len, tcb_desc->queue_index); + return skb->len; + } + +#ifdef ENABLE_LPS + priv->ieee80211->bAwakePktSent = true; +#endif + mapping = pci_map_single(priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE); /* collect the tx packets statitcs */ pda_addr = ((u8*)skb->data) + sizeof(TX_FWINFO_8190PCI); @@ -1481,6 +1712,7 @@ short rtl8192_tx(struct net_device *dev, struct sk_buff* skb) if((pdesc->OWN == 1) && (tcb_desc->queue_index != BEACON_QUEUE)) { RT_TRACE(COMP_ERR,"No more TX desc@%d, ring->idx = %d,idx = %d,%x", \ tcb_desc->queue_index,ring->idx, idx,skb->len); + spin_unlock_irqrestore(&priv->irq_th_lock,flags); return skb->len; } @@ -1779,7 +2011,7 @@ static void rtl8192_qos_activate(struct work_struct * work) (((u32)(qos_parameters->cw_max[i]))<< AC_PARAM_ECW_MAX_OFFSET)| (((u32)(qos_parameters->cw_min[i]))<< AC_PARAM_ECW_MIN_OFFSET)| ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET)); - printk("===>u4bAcParam:%x, ", u4bAcParam); + //printk("===>u4bAcParam:%x, ", u4bAcParam); write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam); //write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332); } @@ -1964,11 +2196,24 @@ void rtl8192_update_ratr_table(struct net_device* dev) write_nic_byte(dev, UFWP, 1); } +#if 0 static u8 ccmp_ie[4] = {0x00,0x50,0xf2,0x04}; static u8 ccmp_rsn_ie[4] = {0x00, 0x0f, 0xac, 0x04}; +#endif + static bool GetNmodeSupportBySecCfg8190Pci(struct net_device*dev) { #if 1 + + struct r8192_priv *priv = ieee80211_priv(dev); + struct ieee80211_device *ieee = priv->ieee80211; + if (ieee->rtllib_ap_sec_type && + (ieee->rtllib_ap_sec_type(ieee)&(SEC_ALG_WEP|SEC_ALG_TKIP))) { + return false; + } else { + return true; + } +#else struct r8192_priv* priv = ieee80211_priv(dev); struct ieee80211_device* ieee = priv->ieee80211; int wpa_ie_len= ieee->wpa_ie_len; @@ -1995,18 +2240,6 @@ static bool GetNmodeSupportBySecCfg8190Pci(struct net_device*dev) return true; } -#if 0 - //In here we discuss with SD4 David. He think we still can send TKIP in broadcast group key in MCS rate. - //We can't force in G mode if Pairwie key is AES and group key is TKIP - if((pSecInfo->GroupEncAlgorithm == WEP104_Encryption) || (pSecInfo->GroupEncAlgorithm == WEP40_Encryption) || - (pSecInfo->PairwiseEncAlgorithm == WEP104_Encryption) || - (pSecInfo->PairwiseEncAlgorithm == WEP40_Encryption) || (pSecInfo->PairwiseEncAlgorithm == TKIP_Encryption)) - { - return false; - } - else - return true; -#endif return true; #endif } @@ -2127,7 +2360,19 @@ short rtl8192_is_tx_queue_empty(struct net_device *dev) } static void rtl8192_hw_sleep_down(struct net_device *dev) { - RT_TRACE(COMP_POWER, "%s()============>come to sleep down\n", __FUNCTION__); + struct r8192_priv *priv = ieee80211_priv(dev); + unsigned long flags = 0; + + spin_lock_irqsave(&priv->rf_ps_lock,flags); + if (priv->RFChangeInProgress) { + spin_unlock_irqrestore(&priv->rf_ps_lock,flags); + RT_TRACE(COMP_RF, "rtl8192_hw_sleep_down(): RF Change in progress! \n"); + printk("rtl8192_hw_sleep_down(): RF Change in progress!\n"); + return; + } + spin_unlock_irqrestore(&priv->rf_ps_lock,flags); + //RT_TRACE(COMP_PS, "%s()============>come to sleep down\n", __FUNCTION__); + MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS); } static void rtl8192_hw_sleep_wq (struct work_struct *work) @@ -2138,21 +2383,29 @@ static void rtl8192_hw_sleep_wq (struct work_struct *work) struct delayed_work *dwork = container_of(work,struct delayed_work,work); struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_sleep_wq); struct net_device *dev = ieee->dev; - //printk("=========>%s()\n", __FUNCTION__); + rtl8192_hw_sleep_down(dev); } -// printk("dev is %d\n",dev); -// printk("&*&(^*(&(&=========>%s()\n", __FUNCTION__); + static void rtl8192_hw_wakeup(struct net_device* dev) { -// u32 flags = 0; + struct r8192_priv *priv = ieee80211_priv(dev); + unsigned long flags = 0; + + spin_lock_irqsave(&priv->rf_ps_lock,flags); + if (priv->RFChangeInProgress) { + spin_unlock_irqrestore(&priv->rf_ps_lock,flags); + RT_TRACE(COMP_RF, "rtl8192_hw_wakeup(): RF Change in progress! \n"); + printk("rtl8192_hw_wakeup(): RF Change in progress! schedule wake up task again\n"); + queue_delayed_work(priv->ieee80211->wq,&priv->ieee80211->hw_wakeup_wq,MSECS(10));//PowerSave is not supported if kernel version is below 2.6.20 + return; + } + spin_unlock_irqrestore(&priv->rf_ps_lock,flags); -// spin_lock_irqsave(&priv->ps_lock,flags); - RT_TRACE(COMP_POWER, "%s()============>come to wake up\n", __FUNCTION__); + //RT_TRACE(COMP_PS, "%s()============>come to wake up\n", __FUNCTION__); MgntActSet_RF_State(dev, eRfOn, RF_CHANGE_BY_PS); - //FIXME: will we send package stored while nic is sleep? -// spin_unlock_irqrestore(&priv->ps_lock,flags); } + void rtl8192_hw_wakeup_wq (struct work_struct *work) { // struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq); @@ -2169,7 +2422,6 @@ void rtl8192_hw_wakeup_wq (struct work_struct *work) #define MAX_SLEEP_TIME 10000 static void rtl8192_hw_to_sleep(struct net_device *dev, u32 th, u32 tl) { - struct r8192_priv *priv = ieee80211_priv(dev); u32 rb = jiffies; @@ -2177,58 +2429,55 @@ static void rtl8192_hw_to_sleep(struct net_device *dev, u32 th, u32 tl) spin_lock_irqsave(&priv->ps_lock,flags); - /* Writing HW register with 0 equals to disable - * the timer, that is not really what we want - */ - tl -= MSECS(4+16+7); - - //if(tl == 0) tl = 1; - - /* FIXME HACK FIXME HACK */ -// force_pci_posting(dev); - //mdelay(1); - -// rb = read_nic_dword(dev, TSFTR); + // Writing HW register with 0 equals to disable + // the timer, that is not really what we want + // + tl -= MSECS(8+16+7); - /* If the interval in witch we are requested to sleep is too - * short then give up and remain awake - */ + // If the interval in witch we are requested to sleep is too + // short then give up and remain awake + // when we sleep after send null frame, the timer will be too short to sleep. + // if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME)) - ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) { + ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) { spin_unlock_irqrestore(&priv->ps_lock,flags); - printk("too short to sleep\n"); + printk("too short to sleep::%x, %x, %lx\n",tl, rb, MSECS(MIN_SLEEP_TIME)); return; } -// write_nic_dword(dev, TimerInt, tl); -// rb = read_nic_dword(dev, TSFTR); - { - u32 tmp = (tl>rb)?(tl-rb):(rb-tl); - // if (tlieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb - } - /* if we suspect the TimerInt is gone beyond tl - * while setting it, then give up - */ -#if 1 if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))|| - ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) { + ((tl < rb) && (tl>MSECS(69)) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))|| + ((tlMSECS(MAX_SLEEP_TIME)))) { printk("========>too long to sleep:%x, %x, %lx\n", tl, rb, MSECS(MAX_SLEEP_TIME)); spin_unlock_irqrestore(&priv->ps_lock,flags); return; } -#endif -// if(priv->rf_sleep) -// priv->rf_sleep(dev); - - //printk("<=========%s()\n", __FUNCTION__); - queue_delayed_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq,0); + { + u32 tmp = (tl>rb)?(tl-rb):(rb-tl); + queue_delayed_work(priv->ieee80211->wq, + &priv->ieee80211->hw_wakeup_wq,tmp); + //PowerSave not supported when kernel version less 2.6.20 + } + queue_delayed_work(priv->ieee80211->wq, + (void *)&priv->ieee80211->hw_sleep_wq,0); spin_unlock_irqrestore(&priv->ps_lock,flags); + } static void rtl8192_init_priv_variable(struct net_device* dev) { struct r8192_priv *priv = ieee80211_priv(dev); u8 i; + PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl)); + + // Default Halt the NIC if RF is OFF. + pPSC->RegRfPsLevel |= RT_RF_OFF_LEVL_HALT_NIC; + pPSC->RegRfPsLevel |= RT_RF_OFF_LEVL_CLK_REQ; + pPSC->RegRfPsLevel |= RT_RF_OFF_LEVL_ASPM; + pPSC->RegRfPsLevel |= RT_RF_LPS_LEVEL_ASPM; + pPSC->bLeisurePs = true; + pPSC->RegMaxLPSAwakeIntvl = 5; + priv->bHwRadioOff = false; + priv->being_init_adapter = false; priv->txbuffsize = 1600;//1024; priv->txfwbuffersize = 4096; @@ -2328,6 +2577,17 @@ static void rtl8192_init_priv_variable(struct net_device* dev) //added by amy priv->ieee80211->InitialGainHandler = InitialGain819xPci; +#ifdef ENABLE_IPS + priv->ieee80211->ieee80211_ips_leave_wq = ieee80211_ips_leave_wq; + priv->ieee80211->ieee80211_ips_leave = ieee80211_ips_leave; +#endif +#ifdef ENABLE_LPS + priv->ieee80211->LeisurePSLeave = LeisurePSLeave; +#endif//ENABL + + priv->ieee80211->SetHwRegHandler = rtl8192e_SetHwReg; + priv->ieee80211->rtllib_ap_sec_type = rtl8192e_ap_sec_type; + priv->card_type = USB; { priv->ShortRetryLimit = 0x30; @@ -2400,6 +2660,10 @@ static void rtl8192_init_priv_task(struct net_device* dev) priv->priv_wq = create_workqueue(DRV_NAME); #endif +#ifdef ENABLE_IPS + INIT_WORK(&priv->ieee80211->ips_leave_wq, (void*)IPSLeave_wq); +#endif + // INIT_WORK(&priv->reset_wq, (void(*)(void*)) rtl8192_restart); INIT_WORK(&priv->reset_wq, rtl8192_restart); // INIT_DELAYED_WORK(&priv->watch_dog_wq, hal_dm_watchdog); @@ -2926,13 +3190,14 @@ static void rtl8192_read_eeprom_info(struct net_device* dev) #endif break; } -/* - //2008.06.03, for WOL + + if( priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304) - priv->ieee80211->bSupportRemoteWakeUp = TRUE; + priv->ieee80211->bSupportRemoteWakeUp = true; else - priv->ieee80211->bSupportRemoteWakeUp = FALSE; -*/ + priv->ieee80211->bSupportRemoteWakeUp = false; + + RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan); RT_TRACE(COMP_INIT, "ChannelPlan = %d \n", priv->ChannelPlan); RT_TRACE(COMP_INIT, "LedStrategy = %d \n", priv->LedStrategy); @@ -4006,12 +4271,19 @@ static void rtl819x_ifsilentreset(struct net_device *dev) struct ieee80211_device *ieee = priv->ieee80211; + return; + // 2007.07.20. If we need to check CCK stop, please uncomment this line. //bStuck = Adapter->HalFunc.CheckHWStopHandler(Adapter); if(priv->ResetProgress==RESET_TYPE_NORESET) { RESET_START: +#ifdef ENABLE_LPS + //LZM for PS-Poll AID issue. 090429 + if(priv->ieee80211->state == IEEE80211_LINKED) + LeisurePSLeave(dev); +#endif RT_TRACE(COMP_RESET,"=========>Reset progress!! \n"); @@ -4051,9 +4323,9 @@ RESET_START: } else{ printk("ieee->state is NOT LINKED\n"); - ieee80211_softmac_stop_protocol(priv->ieee80211); + ieee80211_softmac_stop_protocol(priv->ieee80211,true); } - rtl8192_rtx_disable(dev); + rtl8192_halt_adapter(dev, true); up(&priv->wx_sem); RT_TRACE(COMP_RESET,"%s():<==========down process is finished\n",__FUNCTION__); RT_TRACE(COMP_RESET,"%s():===========>start to up the driver\n",__FUNCTION__); @@ -4150,6 +4422,128 @@ void InactivePsWorkItemCallback(struct net_device *dev) RT_TRACE(COMP_POWER, "InactivePsWorkItemCallback() <--------- \n"); } +#ifdef ENABLE_LPS +// +// Change current and default preamble mode. +// 2005.01.06, by rcnjko. +// +bool MgntActSet_802_11_PowerSaveMode(struct net_device *dev, u8 rtPsMode) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl)); + //u8 RpwmVal, FwPwrMode; + + // Currently, we do not change power save mode on IBSS mode. + if(priv->ieee80211->iw_mode == IW_MODE_ADHOC) + { + return false; + } + + // + // If we make HW to fill up the PwrMgt bit for us, + // some AP will not response to our mgnt frames with PwrMgt bit set, + // e.g. cannot associate the AP. + // So I commented out it. 2005.02.16, by rcnjko. + // +// // Change device's power save mode. +// Adapter->HalFunc.SetPSModeHandler( Adapter, rtPsMode ); + + // Update power save mode configured. + //RT_TRACE(COMP_LPS,"%s(): set ieee->ps = %x\n",__FUNCTION__,rtPsMode); + if(!priv->ps_force) { + priv->ieee80211->ps = rtPsMode; + } + + // Awake immediately + if(priv->ieee80211->sta_sleep != 0 && rtPsMode == IEEE80211_PS_DISABLED) + { + unsigned long flags; + + //PlatformSetTimer(Adapter, &(pMgntInfo->AwakeTimer), 0); + // Notify the AP we awke. + rtl8192_hw_wakeup(dev); + priv->ieee80211->sta_sleep = 0; + + spin_lock_irqsave(&(priv->ieee80211->mgmt_tx_lock), flags); + printk("LPS leave: notify AP we are awaked ++++++++++ SendNullFunctionData\n"); + ieee80211_sta_ps_send_null_frame(priv->ieee80211, 0); + spin_unlock_irqrestore(&(priv->ieee80211->mgmt_tx_lock), flags); + } + + return true; +} + +//================================================================================ +// Leisure Power Save in linked state. +//================================================================================ + +// +// Description: +// Enter the leisure power save mode. +// +void LeisurePSEnter(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl)); + + //RT_TRACE(COMP_PS, "LeisurePSEnter()...\n"); + //RT_TRACE(COMP_PS, "pPSC->bLeisurePs = %d, ieee->ps = %d,pPSC->LpsIdleCount is %d,RT_CHECK_FOR_HANG_PERIOD is %d\n", + // pPSC->bLeisurePs, priv->ieee80211->ps,pPSC->LpsIdleCount,RT_CHECK_FOR_HANG_PERIOD); + + if(!((priv->ieee80211->iw_mode == IW_MODE_INFRA) && + (priv->ieee80211->state == IEEE80211_LINKED)) || + (priv->ieee80211->iw_mode == IW_MODE_ADHOC) || + (priv->ieee80211->iw_mode == IW_MODE_MASTER)) + return; + + if (pPSC->bLeisurePs) + { + // Idle for a while if we connect to AP a while ago. + if(pPSC->LpsIdleCount >= RT_CHECK_FOR_HANG_PERIOD) // 4 Sec + { + + if(priv->ieee80211->ps == IEEE80211_PS_DISABLED) + { + + //RT_TRACE(COMP_LPS, "LeisurePSEnter(): Enter 802.11 power save mode...\n"); + MgntActSet_802_11_PowerSaveMode(dev, IEEE80211_PS_MBCAST|IEEE80211_PS_UNICAST); + + } + } + else + pPSC->LpsIdleCount++; + } +} + + +// +// Description: +// Leave the leisure power save mode. +// +void LeisurePSLeave(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl)); + + + //RT_TRACE(COMP_PS, "LeisurePSLeave()...\n"); + //RT_TRACE(COMP_PS, "pPSC->bLeisurePs = %d, ieee->ps = %d\n", + // pPSC->bLeisurePs, priv->ieee80211->ps); + + if (pPSC->bLeisurePs) + { + if(priv->ieee80211->ps != IEEE80211_PS_DISABLED) + { + // move to lps_wakecomplete() + //RT_TRACE(COMP_LPS, "LeisurePSLeave(): Busy Traffic , Leave 802.11 power save..\n"); + MgntActSet_802_11_PowerSaveMode(dev, IEEE80211_PS_DISABLED); + + } + } +} +#endif + + // // Description: // Enter the inactive power save mode. RF will be off @@ -4178,6 +4572,7 @@ IPSEnter(struct net_device *dev) && (priv->ieee80211->state != IEEE80211_LINKED) ) { RT_TRACE(COMP_RF,"IPSEnter(): Turn off RF.\n"); + //printk("IPSEnter(): Turn off RF.\n"); pPSC->eInactivePowerState = eRfOff; // queue_work(priv->priv_wq,&(pPSC->InactivePsWorkItem)); InactivePsWorkItemCallback(dev); @@ -4203,12 +4598,53 @@ IPSLeave(struct net_device *dev) if (rtState != eRfOn && !pPSC->bSwRfProcessing && priv->ieee80211->RfOffReason <= RF_CHANGE_BY_IPS) { RT_TRACE(COMP_POWER, "IPSLeave(): Turn on RF.\n"); + //printk("IPSLeave(): Turn on RF.\n"); pPSC->eInactivePowerState = eRfOn; // queue_work(priv->priv_wq,&(pPSC->InactivePsWorkItem)); InactivePsWorkItemCallback(dev); } } } + +void IPSLeave_wq(void *data) +{ + struct ieee80211_device *ieee = container_of(data,struct ieee80211_device,ips_leave_wq); + struct net_device *dev = ieee->dev; + + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + down(&priv->ieee80211->ips_sem); + IPSLeave(dev); + up(&priv->ieee80211->ips_sem); +} + +void ieee80211_ips_leave_wq(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + RT_RF_POWER_STATE rtState; + rtState = priv->ieee80211->eRFPowerState; + + if(priv->ieee80211->PowerSaveControl.bInactivePs){ + if(rtState == eRfOff){ + if(priv->ieee80211->RfOffReason > RF_CHANGE_BY_IPS) + { + RT_TRACE(COMP_ERR, "%s(): RF is OFF.\n",__FUNCTION__); + return; + } + else{ + printk("=========>%s(): IPSLeave\n",__FUNCTION__); + queue_work(priv->ieee80211->wq,&priv->ieee80211->ips_leave_wq); + } + } + } +} +//added by amy 090331 end +void ieee80211_ips_leave(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + down(&priv->ieee80211->ips_sem); + IPSLeave(dev); + up(&priv->ieee80211->ips_sem); +} #endif static void rtl819x_update_rxcounts( @@ -4244,15 +4680,23 @@ void rtl819x_watchdog_wqcallback(struct work_struct *work) unsigned long flags; bool bBusyTraffic = false; static u8 last_time = 0; + bool bEnterPS = false; + + if((!priv->up) || (priv->bHwRadioOff == true)) + return; + if(!priv->up) return; hal_dm_watchdog(dev); #ifdef ENABLE_IPS // printk("watch_dog ENABLE_IPS\n"); if(ieee->actscanning == false){ - if((ieee->iw_mode != IW_MODE_ADHOC) && (ieee->state == IEEE80211_NOLINK) && (ieee->beinretry == false) && (ieee->eRFPowerState == eRfOn) && !ieee->is_set_key){ + //printk("%d,%d,%d,%d\n", ieee->eRFPowerState, ieee->is_set_key, ieee->proto_stoppping, ieee->wx_set_enc); + if((ieee->iw_mode == IW_MODE_INFRA) && (ieee->state == IEEE80211_NOLINK) &&\ + (ieee->eRFPowerState == eRfOn)&&!ieee->is_set_key &&\ + (!ieee->proto_stoppping) && !ieee->wx_set_enc){ if(ieee->PowerSaveControl.ReturnPoint == IPS_CALLBACK_NONE){ - printk("====================>haha:IPSEnter()\n"); + //printk("====================>haha:IPSEnter()\n"); IPSEnter(dev); //ieee80211_stop_scan(priv->ieee80211); } @@ -4262,14 +4706,49 @@ void rtl819x_watchdog_wqcallback(struct work_struct *work) {//to get busy traffic condition if(ieee->state == IEEE80211_LINKED) { - if( ieee->LinkDetectInfo.NumRxOkInPeriod> 666 || - ieee->LinkDetectInfo.NumTxOkInPeriod> 666 ) { + if( ieee->LinkDetectInfo.NumRxOkInPeriod> 100 || + ieee->LinkDetectInfo.NumTxOkInPeriod> 100 ) { bBusyTraffic = true; } +#ifdef ENABLE_LPS + //added by amy for Leisure PS + if( ((ieee->LinkDetectInfo.NumRxUnicastOkInPeriod + ieee->LinkDetectInfo.NumTxOkInPeriod) > 8 ) || + (ieee->LinkDetectInfo.NumRxUnicastOkInPeriod > 2) ) + { + //printk("ieee->LinkDetectInfo.NumRxUnicastOkInPeriod is %d,ieee->LinkDetectInfo.NumTxOkInPeriod is %d\n", + // ieee->LinkDetectInfo.NumRxUnicastOkInPeriod,ieee->LinkDetectInfo.NumTxOkInPeriod); + bEnterPS= false; + } + else + { + bEnterPS= true; + } + + //printk("***bEnterPS = %d\n", bEnterPS); + // LeisurePS only work in infra mode. + if(bEnterPS) + { + LeisurePSEnter(dev); + } + else + { + LeisurePSLeave(dev); + } +#endif + + } + else + { +#ifdef ENABLE_LPS + //RT_TRACE(COMP_LPS,"====>no link LPS leave\n"); + LeisurePSLeave(dev); +#endif } + ieee->LinkDetectInfo.NumRxOkInPeriod = 0; ieee->LinkDetectInfo.NumTxOkInPeriod = 0; + ieee->LinkDetectInfo.NumRxUnicastOkInPeriod = 0; ieee->LinkDetectInfo.bBusyTraffic = bBusyTraffic; } @@ -4288,14 +4767,14 @@ void rtl819x_watchdog_wqcallback(struct work_struct *work) if( ieee->eRFPowerState == eRfOff) RT_TRACE(COMP_ERR,"========>%s()\n",__FUNCTION__); printk("===>%s(): AP is power off,connect another one\n",__FUNCTION__); - // Dot11d_Reset(dev); + // Dot11d_Reset(dev); ieee->state = IEEE80211_ASSOCIATING; notify_wx_assoc_event(priv->ieee80211); - RemovePeerTS(priv->ieee80211,priv->ieee80211->current_network.bssid); + RemovePeerTS(priv->ieee80211,priv->ieee80211->current_network.bssid); ieee->is_roaming = true; ieee->is_set_key = false; - ieee->link_change(dev); - queue_work(ieee->wq, &ieee->associate_procedure_wq); + ieee->link_change(dev); + queue_work(ieee->wq, &ieee->associate_procedure_wq); } } ieee->LinkDetectInfo.NumRecvBcnInPeriod=0; @@ -4348,6 +4827,7 @@ int _rtl8192_up(struct net_device *dev) RT_STATUS init_status = RT_STATUS_SUCCESS; priv->up=1; priv->ieee80211->ieee_up=1; + priv->bdisable_nic = false; //YJ,add,091111 RT_TRACE(COMP_INIT, "Bringing up iface"); init_status = rtl8192_adapter_start(dev); @@ -4422,6 +4902,12 @@ int rtl8192_down(struct net_device *dev) #endif if (priv->up == 0) return -1; +#ifdef ENABLE_LPS + //LZM for PS-Poll AID issue. 090429 + if(priv->ieee80211->state == IEEE80211_LINKED) + LeisurePSLeave(dev); +#endif + priv->up=0; priv->ieee80211->ieee_up = 0; RT_TRACE(COMP_DOWN, "==========>%s()\n", __FUNCTION__); @@ -4459,11 +4945,9 @@ int rtl8192_down(struct net_device *dev) deinit_hal_dm(dev); del_timer_sync(&priv->watch_dog_timer); - ieee80211_softmac_stop_protocol(priv->ieee80211); -#ifdef ENABLE_IPS - MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT); -#endif - rtl8192_rtx_disable(dev); + ieee80211_softmac_stop_protocol(priv->ieee80211,true); + + rtl8192_halt_adapter(dev,false); memset(&priv->ieee80211->current_network, 0 , offsetof(struct ieee80211_network, list)); RT_TRACE(COMP_DOWN, "<==========%s()\n", __FUNCTION__); @@ -4479,10 +4963,10 @@ void rtl8192_commit(struct net_device *dev) if (priv->up == 0) return ; - ieee80211_softmac_stop_protocol(priv->ieee80211); + ieee80211_softmac_stop_protocol(priv->ieee80211,true); rtl8192_irq_disable(dev); - rtl8192_rtx_disable(dev); + rtl8192_halt_adapter(dev,true); _rtl8192_up(dev); } @@ -6381,11 +6865,13 @@ void setKey( struct net_device *dev, if(priv->ieee80211->RfOffReason > RF_CHANGE_BY_IPS) { RT_TRACE(COMP_ERR, "%s(): RF is OFF.\n",__FUNCTION__); - up(&priv->wx_sem); + //up(&priv->wx_sem); return ; } else{ + down(&priv->ieee80211->ips_sem); IPSLeave(dev); + up(&priv->ieee80211->ips_sem); } } } @@ -6455,6 +6941,65 @@ void CamPrintDbgReg(struct net_device* dev) RT_TRACE(COMP_SEC, "WPA_Config=%x \n",ucValue); } +bool NicIFEnableNIC(struct net_device* dev) +{ + RT_STATUS init_status = RT_STATUS_SUCCESS; + struct r8192_priv* priv = ieee80211_priv(dev); + PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl)); + + //YJ,add,091109 + if (priv->up == 0){ + RT_TRACE(COMP_ERR, "ERR!!! %s(): Driver is already down!\n",__FUNCTION__); + priv->bdisable_nic = false; //YJ,add,091111 + return false; + } + // <1> Reset memory: descriptor, buffer,.. + //NicIFResetMemory(Adapter); + + // <2> Enable Adapter + //printk("===========>%s()\n",__FUNCTION__); + //priv->bfirst_init = true; + init_status = rtl8192_adapter_start(dev); + if (init_status != RT_STATUS_SUCCESS) { + RT_TRACE(COMP_ERR,"ERR!!! %s(): initialization is failed!\n",__FUNCTION__); + priv->bdisable_nic = false; //YJ,add,091111 + return -1; + } + //printk("start adapter finished\n"); + RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); + //priv->bfirst_init = false; + + // <3> Enable Interrupt + rtl8192_irq_enable(dev); + priv->bdisable_nic = false; + //RT_TRACE(COMP_PS,"<===========%s()\n",__FUNCTION__); + return (init_status == RT_STATUS_SUCCESS) ? true:false; +} +bool NicIFDisableNIC(struct net_device* dev) +{ + bool status = true; + struct r8192_priv* priv = ieee80211_priv(dev); + u8 tmp_state = 0; + // <1> Disable Interrupt + //RT_TRACE(COMP_PS, "=========>%s()\n",__FUNCTION__); + priv->bdisable_nic = true; //YJ,move,091109 + tmp_state = priv->ieee80211->state; + + ieee80211_softmac_stop_protocol(priv->ieee80211, false); + + priv->ieee80211->state = tmp_state; + rtl8192_cancel_deferred_work(priv); + rtl8192_irq_disable(dev); + // <2> Stop all timer + + // <3> Disable Adapter + rtl8192_halt_adapter(dev, false); +// priv->bdisable_nic = true; + //RT_TRACE(COMP_PS, "<=========%s()\n",__FUNCTION__); + + return status; +} + /*************************************************************************** ------------------- module init / exit stubs ---------------- diff --git a/drivers/staging/rtl8192e/r8192E_dm.c b/drivers/staging/rtl8192e/r8192E_dm.c index 5ffb4f74055b..a249f00da60d 100644 --- a/drivers/staging/rtl8192e/r8192E_dm.c +++ b/drivers/staging/rtl8192e/r8192E_dm.c @@ -19,26 +19,28 @@ Major Change History: #include "r819xE_phy.h" #include "r819xE_phyreg.h" #include "r8190_rtl8256.h" + +#define DRV_NAME "rtl819xE" /*---------------------------Define Local Constant---------------------------*/ // // Indicate different AP vendor for IOT issue. // #ifdef RTL8190P static u32 edca_setting_DL[HT_IOT_PEER_MAX] = -{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322}; +{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322, 0x5e4322}; static u32 edca_setting_UL[HT_IOT_PEER_MAX] = -{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322}; +{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322, 0x5e4322}; #else #ifdef RTL8192E static u32 edca_setting_DL[HT_IOT_PEER_MAX] = -{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322}; +{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322, 0x5e4322}; static u32 edca_setting_UL[HT_IOT_PEER_MAX] = -{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322}; +{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322, 0x5e4322}; #else static u32 edca_setting_DL[HT_IOT_PEER_MAX] = -{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f}; +{ 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f, 0x5e4322}; static u32 edca_setting_UL[HT_IOT_PEER_MAX] = -{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f}; +{ 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f, 0x5e4322}; #endif #endif @@ -275,6 +277,30 @@ void dm_CheckRxAggregation(struct net_device *dev) { #endif +// call the script file to enable +void dm_check_ac_dc_power(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + static char *ac_dc_check_script_path = "/etc/acpi/wireless-rtl-ac-dc-power.sh"; + char *argv[] = {ac_dc_check_script_path,DRV_NAME,NULL}; + static char *envp[] = {"HOME=/", + "TERM=linux", + "PATH=/usr/bin:/bin", + NULL}; + + if(priv->ResetProgress == RESET_TYPE_SILENT) + { + RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF), "GPIOChangeRFWorkItemCallBack(): Silent Reseting!!!!!!!\n"); + return; + } + + if(priv->ieee80211->state != IEEE80211_LINKED) { + return; + } + call_usermodehelper(ac_dc_check_script_path,argv,envp,1); + + return; +}; void hal_dm_watchdog(struct net_device *dev) { @@ -282,6 +308,8 @@ void hal_dm_watchdog(struct net_device *dev) //static u8 previous_bssid[6] ={0}; + dm_check_ac_dc_power(dev); + /*Add by amy 2008/05/15 ,porting from windows code.*/ dm_check_rate_adaptive(dev); dm_dynamic_txpower(dev); diff --git a/drivers/staging/rtl8192e/r8192E_hw.h b/drivers/staging/rtl8192e/r8192E_hw.h index 388908fc8d20..346bfb18e2b0 100644 --- a/drivers/staging/rtl8192e/r8192E_hw.h +++ b/drivers/staging/rtl8192e/r8192E_hw.h @@ -808,4 +808,12 @@ enum _RTL8192Pci_HW { #define GPI 0x108 #define GPO 0x109 #define GPE 0x10a + +#define ANAPAR_FOR_8192PciE 0x17 // Analog parameter register + +#define MSR_NOLINK 0x00 +#define MSR_ADHOC 0x01 +#define MSR_INFRA 0x02 +#define MSR_AP 0x03 + #endif diff --git a/drivers/staging/rtl8192e/r8192E_wx.c b/drivers/staging/rtl8192e/r8192E_wx.c index d1eb89229cdf..0b0f39ce3ced 100644 --- a/drivers/staging/rtl8192e/r8192E_wx.c +++ b/drivers/staging/rtl8192e/r8192E_wx.c @@ -22,7 +22,7 @@ #include "r8192E_hw.h" #include "r8192E_wx.h" #ifdef ENABLE_DOT11D -#include "dot11d.h" +#include "ieee80211/dot11d.h" #endif #define RATE_COUNT 12 @@ -70,6 +70,9 @@ static int r8192_wx_set_rate(struct net_device *dev, int ret; struct r8192_priv *priv = ieee80211_priv(dev); + if(priv->bHwRadioOff == true) + return 0; + down(&priv->wx_sem); ret = ieee80211_wx_set_rate(priv->ieee80211,info,wrqu,extra); @@ -87,6 +90,9 @@ static int r8192_wx_set_rts(struct net_device *dev, int ret; struct r8192_priv *priv = ieee80211_priv(dev); + if(priv->bHwRadioOff == true) + return 0; + down(&priv->wx_sem); ret = ieee80211_wx_set_rts(priv->ieee80211,info,wrqu,extra); @@ -111,6 +117,9 @@ static int r8192_wx_set_power(struct net_device *dev, int ret; struct r8192_priv *priv = ieee80211_priv(dev); + if(priv->bHwRadioOff == true) + return 0; + down(&priv->wx_sem); ret = ieee80211_wx_set_power(priv->ieee80211,info,wrqu,extra); @@ -290,6 +299,9 @@ static int r8192_wx_set_rawtx(struct net_device *dev, struct r8192_priv *priv = ieee80211_priv(dev); int ret; + if(priv->bHwRadioOff == true) + return 0; + down(&priv->wx_sem); ret = ieee80211_wx_set_rawtx(priv->ieee80211, info, wrqu, extra); @@ -325,6 +337,9 @@ static int r8192_wx_set_crcmon(struct net_device *dev, int enable = (parms[0] > 0); short prev = priv->crcmon; + if(priv->bHwRadioOff == true) + return 0; + down(&priv->wx_sem); if(enable) @@ -352,6 +367,9 @@ static int r8192_wx_set_mode(struct net_device *dev, struct iw_request_info *a, RT_RF_POWER_STATE rtState; int ret; + if(priv->bHwRadioOff == true) + return 0; + rtState = priv->ieee80211->eRFPowerState; down(&priv->wx_sem); #ifdef ENABLE_IPS @@ -366,8 +384,10 @@ static int r8192_wx_set_mode(struct net_device *dev, struct iw_request_info *a, return -1; } else{ - printk("=========>%s(): IPSLeave\n",__FUNCTION__); + RT_TRACE(COMP_ERR, "%s(): IPSLeave\n",__FUNCTION__); + down(&priv->ieee80211->ips_sem); IPSLeave(dev); + up(&priv->ieee80211->ips_sem); } } } @@ -425,7 +445,7 @@ static int rtl8180_wx_get_range(struct net_device *dev, */ /* ~5 Mb/s real (802.11b) */ - range->throughput = 5 * 1000 * 1000; + range->throughput = 130 * 1000 * 1000; // TODO: Not used in 802.11b? // range->min_nwid; /* Minimal NWID we are able to set */ @@ -468,7 +488,7 @@ static int rtl8180_wx_get_range(struct net_device *dev, range->pmt_flags = IW_POWER_TIMEOUT; range->pm_capa = IW_POWER_PERIOD | IW_POWER_TIMEOUT | IW_POWER_ALL_R; range->we_version_compiled = WIRELESS_EXT; - range->we_version_source = 16; + range->we_version_source = 18; // range->retry_capa; /* What retry options are supported */ // range->retry_flags; /* How to decode max/min retry limit */ @@ -517,7 +537,12 @@ static int r8192_wx_set_scan(struct net_device *dev, struct iw_request_info *a, struct ieee80211_device* ieee = priv->ieee80211; RT_RF_POWER_STATE rtState; int ret; + + if(priv->bHwRadioOff == true) + return 0; + rtState = priv->ieee80211->eRFPowerState; + if(!priv->up) return -ENETDOWN; if (priv->ieee80211->LinkDetectInfo.bBusyTraffic == true) return -EAGAIN; @@ -547,8 +572,10 @@ static int r8192_wx_set_scan(struct net_device *dev, struct iw_request_info *a, return -1; } else{ - printk("=========>%s(): IPSLeave\n",__FUNCTION__); + //RT_TRACE(COMP_PS, "%s(): IPSLeave\n",__FUNCTION__); + down(&priv->ieee80211->ips_sem); IPSLeave(dev); + up(&priv->ieee80211->ips_sem); } } } @@ -580,6 +607,9 @@ static int r8192_wx_get_scan(struct net_device *dev, struct iw_request_info *a, int ret; struct r8192_priv *priv = ieee80211_priv(dev); + if(priv->bHwRadioOff == true) + return 0; + if(!priv->up) return -ENETDOWN; down(&priv->wx_sem); @@ -599,23 +629,16 @@ static int r8192_wx_set_essid(struct net_device *dev, RT_RF_POWER_STATE rtState; int ret; + if(priv->bHwRadioOff == true) + return 0; + rtState = priv->ieee80211->eRFPowerState; down(&priv->wx_sem); + #ifdef ENABLE_IPS - if(priv->ieee80211->PowerSaveControl.bInactivePs){ - if(rtState == eRfOff){ - if(priv->ieee80211->RfOffReason > RF_CHANGE_BY_IPS) - { - RT_TRACE(COMP_ERR, "%s(): RF is OFF.\n",__FUNCTION__); - up(&priv->wx_sem); - return -1; - } - else{ - printk("=========>%s(): IPSLeave\n",__FUNCTION__); - IPSLeave(dev); - } - } - } + down(&priv->ieee80211->ips_sem); + IPSLeave(dev); + up(&priv->ieee80211->ips_sem); #endif ret = ieee80211_wx_set_essid(priv->ieee80211,a,wrqu,b); @@ -650,6 +673,9 @@ static int r8192_wx_set_freq(struct net_device *dev, struct iw_request_info *a, int ret; struct r8192_priv *priv = ieee80211_priv(dev); + if(priv->bHwRadioOff == true) + return 0; + down(&priv->wx_sem); ret = ieee80211_wx_set_freq(priv->ieee80211, a, wrqu, b); @@ -673,6 +699,9 @@ static int r8192_wx_set_frag(struct net_device *dev, { struct r8192_priv *priv = ieee80211_priv(dev); + if(priv->bHwRadioOff == true) + return 0; + if (wrqu->frag.disabled) priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD; else { @@ -711,8 +740,16 @@ static int r8192_wx_set_wap(struct net_device *dev, struct r8192_priv *priv = ieee80211_priv(dev); // struct sockaddr *temp = (struct sockaddr *)awrq; + if(priv->bHwRadioOff == true) + return 0; + down(&priv->wx_sem); +#ifdef ENABLE_IPS + down(&priv->ieee80211->ips_sem); + IPSLeave(dev); + up(&priv->ieee80211->ips_sem); +#endif ret = ieee80211_wx_set_wap(priv->ieee80211,info,awrq,extra); up(&priv->wx_sem); @@ -753,14 +790,24 @@ static int r8192_wx_set_enc(struct net_device *dev, u32 hwkey[4]={0,0,0,0}; u8 mask=0xff; u32 key_idx=0; - u8 zero_addr[4][6] ={ {0x00,0x00,0x00,0x00,0x00,0x00}, + u8 zero_addr[4][6] ={{0x00,0x00,0x00,0x00,0x00,0x00}, {0x00,0x00,0x00,0x00,0x00,0x01}, {0x00,0x00,0x00,0x00,0x00,0x02}, {0x00,0x00,0x00,0x00,0x00,0x03} }; int i; + if(priv->bHwRadioOff == true) + return 0; + if(!priv->up) return -ENETDOWN; + priv->ieee80211->wx_set_enc = 1; +#ifdef ENABLE_IPS + down(&priv->ieee80211->ips_sem); + IPSLeave(dev); + up(&priv->ieee80211->ips_sem); +#endif + down(&priv->wx_sem); RT_TRACE(COMP_SEC, "Setting SW wep key"); @@ -768,7 +815,6 @@ static int r8192_wx_set_enc(struct net_device *dev, up(&priv->wx_sem); - //sometimes, the length is zero while we do not type key value if(wrqu->encoding.length!=0){ @@ -868,6 +914,8 @@ static int r8192_wx_set_enc(struct net_device *dev, } #endif + priv->ieee80211->wx_set_enc = 0; + return ret; } @@ -893,6 +941,9 @@ static int r8192_wx_set_retry(struct net_device *dev, struct r8192_priv *priv = ieee80211_priv(dev); int err = 0; + if(priv->bHwRadioOff == true) + return 0; + down(&priv->wx_sem); if (wrqu->retry.flags & IW_RETRY_LIFETIME || @@ -985,6 +1036,10 @@ static int r8192_wx_set_sens(struct net_device *dev, struct r8192_priv *priv = ieee80211_priv(dev); short err = 0; + + if(priv->bHwRadioOff == true) + return 0; + down(&priv->wx_sem); //DMESG("attempt to set sensivity to %ddb",wrqu->sens.value); if(priv->rf_set_sens == NULL) { @@ -1011,7 +1066,19 @@ static int r8192_wx_set_enc_ext(struct net_device *dev, struct r8192_priv *priv = ieee80211_priv(dev); struct ieee80211_device* ieee = priv->ieee80211; + if(priv->bHwRadioOff == true) + return 0; + down(&priv->wx_sem); + + priv->ieee80211->wx_set_enc = 1; + +#ifdef ENABLE_IPS + down(&priv->ieee80211->ips_sem); + IPSLeave(dev); + up(&priv->ieee80211->ips_sem); +#endif + ret = ieee80211_wx_set_encode_ext(ieee, info, wrqu, extra); { @@ -1091,6 +1158,7 @@ static int r8192_wx_set_enc_ext(struct net_device *dev, } end_hw_sec: + priv->ieee80211->wx_set_enc = 0; up(&priv->wx_sem); return ret; @@ -1102,6 +1170,10 @@ static int r8192_wx_set_auth(struct net_device *dev, int ret=0; //printk("====>%s()\n", __FUNCTION__); struct r8192_priv *priv = ieee80211_priv(dev); + + if(priv->bHwRadioOff == true) + return 0; + down(&priv->wx_sem); ret = ieee80211_wx_set_auth(priv->ieee80211, info, &(data->param), extra); up(&priv->wx_sem); @@ -1116,6 +1188,10 @@ static int r8192_wx_set_mlme(struct net_device *dev, int ret=0; struct r8192_priv *priv = ieee80211_priv(dev); + + if(priv->bHwRadioOff == true) + return 0; + down(&priv->wx_sem); ret = ieee80211_wx_set_mlme(priv->ieee80211, info, wrqu, extra); up(&priv->wx_sem); @@ -1129,6 +1205,10 @@ static int r8192_wx_set_gen_ie(struct net_device *dev, //printk("====>%s(), len:%d\n", __FUNCTION__, data->length); int ret=0; struct r8192_priv *priv = ieee80211_priv(dev); + + if(priv->bHwRadioOff == true) + return 0; + down(&priv->wx_sem); ret = ieee80211_wx_set_gen_ie(priv->ieee80211, extra, data->data.length); up(&priv->wx_sem); @@ -1142,6 +1222,42 @@ static int dummy(struct net_device *dev, struct iw_request_info *a, return -1; } +// check ac/dc status with the help of user space application */ +static int r8192_wx_adapter_power_status(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +#ifdef ENABLE_LPS + PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl)); + struct ieee80211_device* ieee = priv->ieee80211; +#endif + down(&priv->wx_sem); + +#ifdef ENABLE_LPS + RT_TRACE(COMP_POWER, "%s(): %s\n",__FUNCTION__, (*extra == 6)?"DC power":"AC power"); + // ieee->ps shall not be set under DC mode, otherwise it conflict + // with Leisure power save mode setting. + // + if(*extra || priv->force_lps) { + priv->ps_force = false; + pPSC->bLeisurePs = true; + } else { + //LZM for PS-Poll AID issue. 090429 + if(priv->ieee80211->state == IEEE80211_LINKED) + LeisurePSLeave(dev); + + priv->ps_force = true; + pPSC->bLeisurePs = false; + ieee->ps = *extra; + } + +#endif + up(&priv->wx_sem); + return 0; + +} + static iw_handler r8192_wx_handlers[] = { @@ -1231,72 +1347,28 @@ static const struct iw_priv_args r8192_private_args[] = { SIOCIWFIRSTPRIV + 0x2, IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "rawtx" } -#ifdef JOHN_IOCTL , { SIOCIWFIRSTPRIV + 0x3, - IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "readRF" + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "forcereset" + } , { SIOCIWFIRSTPRIV + 0x4, - IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "writeRF" - } - , - { - SIOCIWFIRSTPRIV + 0x5, - IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "readBB" - } - , - { - SIOCIWFIRSTPRIV + 0x6, - IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "writeBB" - } - , - { - SIOCIWFIRSTPRIV + 0x7, - IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "readnicb" - } - , - { - SIOCIWFIRSTPRIV + 0x8, - IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "writenicb" - } - , - { - SIOCIWFIRSTPRIV + 0x9, - IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "apinfo" - } - -#endif - , - { - SIOCIWFIRSTPRIV + 0x3, - IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "forcereset" - + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED|1, IW_PRIV_TYPE_NONE, + "set_power" } }; static iw_handler r8192_private_handler[] = { -// r8192_wx_set_monitor, /* SIOCIWFIRSTPRIV */ r8192_wx_set_crcmon, /*SIOCIWSECONDPRIV*/ -// r8192_wx_set_forceassociate, -// r8192_wx_set_beaconinterval, -// r8192_wx_set_monitor_type, r8192_wx_set_scan_type, r8192_wx_set_rawtx, -#ifdef JOHN_IOCTL - r8192_wx_read_regs, - r8192_wx_write_regs, - r8192_wx_read_bb, - r8192_wx_write_bb, - r8192_wx_read_nicb, - r8192_wx_write_nicb, - r8192_wx_get_ap_status -#endif r8192_wx_force_reset, + r8192_wx_adapter_power_status, }; //#if WIRELESS_EXT >= 17 diff --git a/drivers/staging/rtl8192e/r8192E_wx.h b/drivers/staging/rtl8192e/r8192E_wx.h index 79ebdb698a41..047030bc051a 100644 --- a/drivers/staging/rtl8192e/r8192E_wx.h +++ b/drivers/staging/rtl8192e/r8192E_wx.h @@ -15,7 +15,6 @@ #ifndef R8180_WX_H #define R8180_WX_H //#include -//#include "ieee80211.h" extern struct iw_handler_def r8192_wx_handlers_def; /* Enable the rtl819x_core.c to share this function, david 2008.9.22 */ extern struct iw_statistics *r8192_get_wireless_stats(struct net_device *dev); diff --git a/drivers/staging/rtl8192e/r819xE_phy.c b/drivers/staging/rtl8192e/r819xE_phy.c index c44059aeacb6..7bd4fae0667e 100644 --- a/drivers/staging/rtl8192e/r819xE_phy.c +++ b/drivers/staging/rtl8192e/r819xE_phy.c @@ -5,7 +5,7 @@ #include "r819xE_phy.h" #include "r8192E_dm.h" #ifdef ENABLE_DOT11D -#include "dot11d.h" +#include "ieee80211/dot11d.h" #endif static u32 RF_CHANNEL_TABLE_ZEBRA[] = { 0, diff --git a/drivers/staging/rtl8192e/r819xE_phyreg.h b/drivers/staging/rtl8192e/r819xE_phyreg.h index 37f0feefaf2c..6a26883d1e9e 100644 --- a/drivers/staging/rtl8192e/r819xE_phyreg.h +++ b/drivers/staging/rtl8192e/r819xE_phyreg.h @@ -38,6 +38,8 @@ #define MCS_TXAGC 0x340 // MCS AGC #define CCK_TXAGC 0x348 // CCK AGC +#define MacBlkCtrl 0x403 // Mac block on/off control register + //page8 #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC #define rFPGA0_TxInfo 0x804 @@ -875,4 +877,5 @@ #define rRTL8256TxBBBW 19 #define bRTL8256TxBBBW 0x18 + #endif //__INC_HAL8190PCIPHYREG_H -- cgit v1.2.3 From 8f2668418f182ac6b50b994851c36bd0a116e4f8 Mon Sep 17 00:00:00 2001 From: Radu Voicilas Date: Fri, 4 Dec 2009 20:43:16 -0800 Subject: Staging: rtl8192e: fix more coding style issues. Fixes to the way code looks. Signed-off-by: Radu Voicilas Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/r8190_rtl8256.h | 49 ++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192e/r8190_rtl8256.h b/drivers/staging/rtl8192e/r8190_rtl8256.h index 7d9095a70aec..ce49c606521a 100644 --- a/drivers/staging/rtl8192e/r8190_rtl8256.h +++ b/drivers/staging/rtl8192e/r8190_rtl8256.h @@ -1,28 +1,33 @@ -/* - This is part of the rtl8180-sa2400 driver - released under the GPL (See file COPYING for details). - Copyright (c) 2005 Andrea Merello +/* r8190_rtl8256.h - rtl8256 radio frontend + * + * This is part of the rtl8180-sa2400 driver + * released under the GPL (See file COPYING for details). + * Copyright (c) 2005 Andrea Merello + * + * Many thanks to Realtek Corp. for their great support! + */ - This files contains programming code for the rtl8256 - radio frontend. - - *Many* thanks to Realtek Corp. for their great support! - -*/ - -#ifndef RTL8225H -#define RTL8225H +#ifndef RTL8225_H +#define RTL8225_H #ifdef RTL8190P -#define RTL819X_TOTAL_RF_PATH 4 +#define RTL819X_TOTAL_RF_PATH 4 #else -#define RTL819X_TOTAL_RF_PATH 2 //for 8192E +#define RTL819X_TOTAL_RF_PATH 2 /* for 8192E */ #endif -extern void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth); -extern RT_STATUS PHY_RF8256_Config(struct net_device* dev); -extern RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev); -extern void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel); -extern void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel); -extern bool MgntActSet_RF_State(struct net_device* dev, RT_RF_POWER_STATE StateToSet, RT_RF_CHANGE_SOURCE ChangeSource); -#endif +extern void PHY_SetRF8256Bandwidth(struct net_device *dev, + HT_CHANNEL_WIDTH Bandwidth); + +extern RT_STATUS PHY_RF8256_Config(struct net_device *dev); + +extern RT_STATUS phy_RF8256_Config_ParaFile(struct net_device *dev); + +extern void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel); +extern void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel); + +extern bool MgntActSet_RF_State(struct net_device *dev, + RT_RF_POWER_STATE StateToSet, + RT_RF_CHANGE_SOURCE ChangeSource); + +#endif /* RTL8225_H */ -- cgit v1.2.3 From 1719e1190a019c65750bc515b3ff2ec694e52bc2 Mon Sep 17 00:00:00 2001 From: Radu Voicilas Date: Mon, 7 Dec 2009 18:20:07 -0800 Subject: Staging: rtl8192e: Code style fix for r819xE_phyreg.h Changed all the comments to conform to the standard, aligned register values. Signed-off-by: Radu Voicilas Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/r819xE_phyreg.h | 1114 +++++++++++++++--------------- 1 file changed, 574 insertions(+), 540 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192e/r819xE_phyreg.h b/drivers/staging/rtl8192e/r819xE_phyreg.h index 6a26883d1e9e..d5de279f6644 100644 --- a/drivers/staging/rtl8192e/r819xE_phyreg.h +++ b/drivers/staging/rtl8192e/r819xE_phyreg.h @@ -81,55 +81,70 @@ #define rFPGA0_XB_LSSIReadBack 0x8a4 #define rFPGA0_XC_LSSIReadBack 0x8a8 #define rFPGA0_XD_LSSIReadBack 0x8ac -#define rFPGA0_PSDReport 0x8b4 +#define rFPGA0_PSDReport 0x8b4 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 -//page 9 -#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC -#define rFPGA1_TxBlock 0x904 -#define rFPGA1_DebugSelect 0x908 -#define rFPGA1_TxInfo 0x90c - -//page a -#define rCCK0_System 0xa00 -#define rCCK0_AFESetting 0xa04 -#define rCCK0_CCA 0xa08 -#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level -#define rCCK0_RxAGC2 0xa10 //AGC & DAGC -#define rCCK0_RxHP 0xa14 -#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold -#define rCCK0_DSPParameter2 0xa1c //SQ threshold -#define rCCK0_TxFilter1 0xa20 -#define rCCK0_TxFilter2 0xa24 -#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 -#define rCCK0_FalseAlarmReport 0xa2c //0xa2d -#define rCCK0_TRSSIReport 0xa50 -#define rCCK0_RxReport 0xa54 //0xa57 -#define rCCK0_FACounterLower 0xa5c //0xa5b -#define rCCK0_FACounterUpper 0xa58 //0xa5c - -//page c -#define rOFDM0_LSTF 0xc00 +/* Page 9 - RF mode & OFDM TxSC */ +#define rFPGA1_RFMOD 0x900 +#define rFPGA1_TxBlock 0x904 +#define rFPGA1_DebugSelect 0x908 +#define rFPGA1_TxInfo 0x90c + +/* Page a */ +#define rCCK0_System 0xa00 +#define rCCK0_AFESetting 0xa04 +#define rCCK0_CCA 0xa08 +/* AGC default value, saturation level */ +#define rCCK0_RxAGC1 0xa0c +/* AGC & DAGC */ +#define rCCK0_RxAGC2 0xa10 +#define rCCK0_RxHP 0xa14 +/* Timing recovery & channel estimation threshold */ +#define rCCK0_DSPParameter1 0xa18 +/* SQ threshold */ +#define rCCK0_DSPParameter2 0xa1c +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +/* Debug port and TX filter 3 */ +#define rCCK0_DebugPort 0xa28 +#define rCCK0_FalseAlarmReport 0xa2c +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 +#define rCCK0_FACounterLower 0xa5c +#define rCCK0_FACounterUpper 0xa58 + +/* Page c */ +#define rOFDM0_LSTF 0xc00 #define rOFDM0_TRxPathEnable 0xc04 -#define rOFDM0_TRMuxPar 0xc08 -#define rOFDM0_TRSWIsolation 0xc0c -#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter -#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix -#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c +/* RxIQ DC offset, Rx digital filter, DC notch filter */ +#define rOFDM0_XARxAFE 0xc10 +/* RxIQ imblance matrix */ +#define rOFDM0_XARxIQImbalance 0xc14 +#define rOFDM0_XBRxAFE 0xc18 #define rOFDM0_XBRxIQImbalance 0xc1c -#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxAFE 0xc20 #define rOFDM0_XCRxIQImbalance 0xc24 -#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxAFE 0xc28 #define rOFDM0_XDRxIQImbalance 0xc2c -#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD -#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. -#define rOFDM0_RxDetector3 0xc38 //Frame Sync. -#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI -#define rOFDM0_RxDSP 0xc40 //Rx Sync Path -#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC -#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold -#define rOFDM0_ECCAThreshold 0xc4c // energy CCA +/* PD, BW & SBD */ +#define rOFDM0_RxDetector1 0xc30 +/* SBD */ +#define rOFDM0_RxDetector2 0xc34 +/* Frame Sync */ +#define rOFDM0_RxDetector3 0xc38 +/* PD, SBD, Frame Sync & Short-GI */ +#define rOFDM0_RxDetector4 0xc3c +/* Rx Sync Path */ +#define rOFDM0_RxDSP 0xc40 +/* CFO & DAGC */ +#define rOFDM0_CFOandDAGC 0xc44 +/* CCA Drop threshold */ +#define rOFDM0_CCADropThreshold 0xc48 +/* Energy CCA */ +#define rOFDM0_ECCAThreshold 0xc4c #define rOFDM0_XAAGCCore1 0xc50 #define rOFDM0_XAAGCCore2 0xc54 #define rOFDM0_XBAGCCore1 0xc58 @@ -141,501 +156,517 @@ #define rOFDM0_AGCParameter1 0xc70 #define rOFDM0_AGCParameter2 0xc74 #define rOFDM0_AGCRSSITable 0xc78 -#define rOFDM0_HTSTFAGC 0xc7c +#define rOFDM0_HTSTFAGC 0xc7c #define rOFDM0_XATxIQImbalance 0xc80 -#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XATxAFE 0xc84 #define rOFDM0_XBTxIQImbalance 0xc88 -#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XBTxAFE 0xc8c #define rOFDM0_XCTxIQImbalance 0xc90 -#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XCTxAFE 0xc94 #define rOFDM0_XDTxIQImbalance 0xc98 -#define rOFDM0_XDTxAFE 0xc9c +#define rOFDM0_XDTxAFE 0xc9c #define rOFDM0_RxHPParameter 0xce0 #define rOFDM0_TxPseudoNoiseWgt 0xce4 -#define rOFDM0_FrameSync 0xcf0 -#define rOFDM0_DFSReport 0xcf4 -#define rOFDM0_TxCoeff1 0xca4 -#define rOFDM0_TxCoeff2 0xca8 -#define rOFDM0_TxCoeff3 0xcac -#define rOFDM0_TxCoeff4 0xcb0 -#define rOFDM0_TxCoeff5 0xcb4 -#define rOFDM0_TxCoeff6 0xcb8 - - -//page d -#define rOFDM1_LSTF 0xd00 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 + + +/* Page d */ +#define rOFDM1_LSTF 0xd00 #define rOFDM1_TRxPathEnable 0xd04 -#define rOFDM1_CFO 0xd08 -#define rOFDM1_CSI1 0xd10 -#define rOFDM1_SBD 0xd14 -#define rOFDM1_CSI2 0xd18 -#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_CFO 0xd08 +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c #define rOFDM1_TRxMesaure1 0xd34 -#define rOFDM1_IntfDet 0xd3c -#define rOFDM1_PseudoNoiseStateAB 0xd50 -#define rOFDM1_PseudoNoiseStateCD 0xd54 -#define rOFDM1_RxPseudoNoiseWgt 0xd58 -#define rOFDM_PHYCounter1 0xda0 //cca, parity fail -#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail -#define rOFDM_PHYCounter3 0xda8 //MCS not support -#define rOFDM_ShortCFOAB 0xdac -#define rOFDM_ShortCFOCD 0xdb0 -#define rOFDM_LongCFOAB 0xdb4 -#define rOFDM_LongCFOCD 0xdb8 -#define rOFDM_TailCFOAB 0xdbc -#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 +/* cca, parity fail */ +#define rOFDM_PHYCounter1 0xda0 +/* rate illegal, crc8 fail */ +#define rOFDM_PHYCounter2 0xda4 +/* MCS not supported */ +#define rOFDM_PHYCounter3 0xda8 +#define rOFDM_ShortCFOAB 0xdac +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 #define rOFDM_PWMeasure1 0xdc4 #define rOFDM_PWMeasure2 0xdc8 -#define rOFDM_BWReport 0xdcc -#define rOFDM_AGCReport 0xdd0 -#define rOFDM_RxSNR 0xdd4 -#define rOFDM_RxEVMCSI 0xdd8 -#define rOFDM_SIGReport 0xddc - -//page e -#define rTxAGC_Rate18_06 0xe00 -#define rTxAGC_Rate54_24 0xe04 -#define rTxAGC_CCK_Mcs32 0xe08 -#define rTxAGC_Mcs03_Mcs00 0xe10 -#define rTxAGC_Mcs07_Mcs04 0xe14 -#define rTxAGC_Mcs11_Mcs08 0xe18 -#define rTxAGC_Mcs15_Mcs12 0xe1c - - -//RF -//Zebra1 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + +/* Page e */ +#define rTxAGC_Rate18_06 0xe00 +#define rTxAGC_Rate54_24 0xe04 +#define rTxAGC_CCK_Mcs32 0xe08 +#define rTxAGC_Mcs03_Mcs00 0xe10 +#define rTxAGC_Mcs07_Mcs04 0xe14 +#define rTxAGC_Mcs11_Mcs08 0xe18 +#define rTxAGC_Mcs15_Mcs12 0xe1c + + +/* RF Zebra 1 */ #define rZebra1_HSSIEnable 0x0 #define rZebra1_TRxEnable1 0x1 #define rZebra1_TRxEnable2 0x2 -#define rZebra1_AGC 0x4 +#define rZebra1_AGC 0x4 #define rZebra1_ChargePump 0x5 -#define rZebra1_Channel 0x7 -#define rZebra1_TxGain 0x8 -#define rZebra1_TxLPF 0x9 -#define rZebra1_RxLPF 0xb +#define rZebra1_Channel 0x7 +#define rZebra1_TxGain 0x8 +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb #define rZebra1_RxHPFCorner 0xc -//Zebra4 -#define rGlobalCtrl 0 -#define rRTL8256_TxLPF 19 -#define rRTL8256_RxLPF 11 +/* Zebra 4 */ +#define rGlobalCtrl 0 +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 -//RTL8258 -#define rRTL8258_TxLPF 0x11 -#define rRTL8258_RxLPF 0x13 +/* RTL8258 */ +#define rRTL8258_TxLPF 0x11 +#define rRTL8258_RxLPF 0x13 #define rRTL8258_RSSILPF 0xa -//Bit Mask -//page-1 -#define bBBResetB 0x100 -#define bGlobalResetB 0x200 -#define bOFDMTxStart 0x4 -#define bCCKTxStart 0x8 -#define bCRC32Debug 0x100 -#define bPMACLoopback 0x10 -#define bTxLSIG 0xffffff -#define bOFDMTxRate 0xf -#define bOFDMTxReserved 0x10 -#define bOFDMTxLength 0x1ffe0 -#define bOFDMTxParity 0x20000 -#define bTxHTSIG1 0xffffff -#define bTxHTMCSRate 0x7f -#define bTxHTBW 0x80 -#define bTxHTLength 0xffff00 -#define bTxHTSIG2 0xffffff -#define bTxHTSmoothing 0x1 -#define bTxHTSounding 0x2 -#define bTxHTReserved 0x4 -#define bTxHTAggreation 0x8 -#define bTxHTSTBC 0x30 -#define bTxHTAdvanceCoding 0x40 -#define bTxHTShortGI 0x80 -#define bTxHTNumberHT_LTF 0x300 -#define bTxHTCRC8 0x3fc00 -#define bCounterReset 0x10000 -#define bNumOfOFDMTx 0xffff -#define bNumOfCCKTx 0xffff0000 -#define bTxIdleInterval 0xffff -#define bOFDMService 0xffff0000 -#define bTxMACHeader 0xffffffff -#define bTxDataInit 0xff -#define bTxHTMode 0x100 -#define bTxDataType 0x30000 -#define bTxRandomSeed 0xffffffff -#define bCCKTxPreamble 0x1 -#define bCCKTxSFD 0xffff0000 -#define bCCKTxSIG 0xff -#define bCCKTxService 0xff00 -#define bCCKLengthExt 0x8000 -#define bCCKTxLength 0xffff0000 -#define bCCKTxCRC16 0xffff -#define bCCKTxStatus 0x1 -#define bOFDMTxStatus 0x2 - -//page-8 -#define bRFMOD 0x1 -#define bJapanMode 0x2 -#define bCCKTxSC 0x30 -#define bCCKEn 0x1000000 -#define bOFDMEn 0x2000000 -#define bOFDMRxADCPhase 0x10000 -#define bOFDMTxDACPhase 0x40000 -#define bXATxAGC 0x3f -#define bXBTxAGC 0xf00 -#define bXCTxAGC 0xf000 -#define bXDTxAGC 0xf0000 -#define bPAStart 0xf0000000 -#define bTRStart 0x00f00000 -#define bRFStart 0x0000f000 -#define bBBStart 0x000000f0 -#define bBBCCKStart 0x0000000f -#define bPAEnd 0xf //Reg0x814 -#define bTREnd 0x0f000000 -#define bRFEnd 0x000f0000 -#define bCCAMask 0x000000f0 //T2R -#define bR2RCCAMask 0x00000f00 -#define bHSSI_R2TDelay 0xf8000000 -#define bHSSI_T2RDelay 0xf80000 -#define bContTxHSSI 0x400 //channel gain at continue Tx -#define bIGFromCCK 0x200 -#define bAGCAddress 0x3f -#define bRxHPTx 0x7000 -#define bRxHPT2R 0x38000 -#define bRxHPCCKIni 0xc0000 -#define bAGCTxCode 0xc00000 -#define bAGCRxCode 0x300000 -#define b3WireDataLength 0x800 -#define b3WireAddressLength 0x400 -#define b3WireRFPowerDown 0x1 -//#define bHWSISelect 0x8 -#define b5GPAPEPolarity 0x40000000 -#define b2GPAPEPolarity 0x80000000 -#define bRFSW_TxDefaultAnt 0x3 -#define bRFSW_TxOptionAnt 0x30 -#define bRFSW_RxDefaultAnt 0x300 -#define bRFSW_RxOptionAnt 0x3000 -#define bRFSI_3WireData 0x1 -#define bRFSI_3WireClock 0x2 -#define bRFSI_3WireLoad 0x4 -#define bRFSI_3WireRW 0x8 -#define bRFSI_3Wire 0xf //3-wire total control -#define bRFSI_RFENV 0x10 -#define bRFSI_TRSW 0x20 -#define bRFSI_TRSWB 0x40 -#define bRFSI_ANTSW 0x100 -#define bRFSI_ANTSWB 0x200 -#define bRFSI_PAPE 0x400 -#define bRFSI_PAPE5G 0x800 -#define bBandSelect 0x1 -#define bHTSIG2_GI 0x80 -#define bHTSIG2_Smoothing 0x01 -#define bHTSIG2_Sounding 0x02 -#define bHTSIG2_Aggreaton 0x08 -#define bHTSIG2_STBC 0x30 -#define bHTSIG2_AdvCoding 0x40 +/* Bit Mask */ +/* Page 1 */ +#define bBBResetB 0x100 +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +/* Page 8 */ +#define bRFMOD 0x1 +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 +#define bOFDMRxADCPhase 0x10000 +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f +#define bXBTxAGC 0xf00 +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 +#define bPAStart 0xf0000000 +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +/* Reg)x814 */ +#define bPAEnd 0xf +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +/* T2R */ +#define bCCAMask 0x000000f0 +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +/* Channel gain at continue TX. */ +#define bContTxHSSI 0x400 +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 +#define b3WireDataLength 0x800 +#define b3WireAddressLength 0x400 +#define b3WireRFPowerDown 0x1 +/*#define bHWSISelect 0x8 */ +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +/* 3-wire total control */ +#define bRFSI_3Wire 0xf +#define bRFSI_RFENV 0x10 +#define bRFSI_TRSW 0x20 +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 #define bHTSIG2_NumOfHTLTF 0x300 -#define bHTSIG2_CRC8 0x3fc -#define bHTSIG1_MCS 0x7f -#define bHTSIG1_BandWidth 0x80 -#define bHTSIG1_HTLength 0xffff -#define bLSIG_Rate 0xf -#define bLSIG_Reserved 0x10 -#define bLSIG_Length 0x1fffe -#define bLSIG_Parity 0x20 -#define bCCKRxPhase 0x4 -#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address -#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal -#define bLSSIReadBackData 0xfff -#define bLSSIReadOKFlag 0x1000 -#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz - -#define bRegulator0Standby 0x1 -#define bRegulatorPLLStandby 0x2 -#define bRegulator1Standby 0x4 -#define bPLLPowerUp 0x8 -#define bDPLLPowerUp 0x10 -#define bDA10PowerUp 0x20 -#define bAD7PowerUp 0x200 -#define bDA6PowerUp 0x2000 -#define bXtalPowerUp 0x4000 -#define b40MDClkPowerUP 0x8000 -#define bDA6DebugMode 0x20000 -#define bDA6Swing 0x380000 -#define bADClkPhase 0x4000000 -#define b80MClkDelay 0x18000000 -#define bAFEWatchDogEnable 0x20000000 -#define bXtalCap 0x0f000000 -#define bXtalCap01 0xc0000000 -#define bXtalCap23 0x3 -#define bXtalCap92x 0x0f000000 -#define bIntDifClkEnable 0x400 -#define bExtSigClkEnable 0x800 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 +/* LSSI "read" address */ +#define bLSSIReadAddress 0x3f000000 +/* LSSI "read" edge signal */ +#define bLSSIReadEdge 0x80000000 +#define bLSSIReadBackData 0xfff +#define bLSSIReadOKFlag 0x1000 +/* 0: 44 MHz, 1: 88MHz */ +#define bCCKSampleRate 0x8 + +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 +#define bADClkPhase 0x4000000 +#define b80MClkDelay 0x18000000 +#define bAFEWatchDogEnable 0x20000000 +#define bXtalCap 0x0f000000 +#define bXtalCap01 0xc0000000 +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 +#define bIntDifClkEnable 0x400 +#define bExtSigClkEnable 0x800 #define bBandgapMbiasPowerUp 0x10000 -#define bAD11SHGain 0xc0000 -#define bAD11InputRange 0x700000 -#define bAD11OPCurrent 0x3800000 -#define bIPathLoopback 0x4000000 -#define bQPathLoopback 0x8000000 -#define bAFELoopback 0x10000000 -#define bDA10Swing 0x7e0 -#define bDA10Reverse 0x800 -#define bDAClkSource 0x1000 -#define bAD7InputRange 0x6000 -#define bAD7Gain 0x38000 -#define bAD7OutputCMMode 0x40000 -#define bAD7InputCMMode 0x380000 -#define bAD7Current 0xc00000 -#define bRegulatorAdjust 0x7000000 -#define bAD11PowerUpAtTx 0x1 -#define bDA10PSAtTx 0x10 -#define bAD11PowerUpAtRx 0x100 -#define bDA10PSAtRx 0x1000 - -#define bCCKRxAGCFormat 0x200 - -#define bPSDFFTSamplepPoint 0xc000 -#define bPSDAverageNum 0x3000 -#define bIQPathControl 0xc00 -#define bPSDFreq 0x3ff -#define bPSDAntennaPath 0x30 -#define bPSDIQSwitch 0x40 -#define bPSDRxTrigger 0x400000 -#define bPSDTxTrigger 0x80000000 -#define bPSDSineToneScale 0x7f000000 -#define bPSDReport 0xffff - -//page-9 -#define bOFDMTxSC 0x30000000 -#define bCCKTxOn 0x1 -#define bOFDMTxOn 0x2 -#define bDebugPage 0xfff //reset debug page and also HWord, LWord -#define bDebugItem 0xff //reset debug page and LWord -#define bAntL 0x10 -#define bAntNonHT 0x100 -#define bAntHT1 0x1000 -#define bAntHT2 0x10000 -#define bAntHT1S1 0x100000 -#define bAntNonHTS1 0x1000000 - -//page-a -#define bCCKBBMode 0x3 -#define bCCKTxPowerSaving 0x80 -#define bCCKRxPowerSaving 0x40 -#define bCCKSideBand 0x10 -#define bCCKScramble 0x8 -#define bCCKAntDiversity 0x8000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 + +#define bCCKRxAGCFormat 0x200 + +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +/* Page 8 */ +#define bOFDMTxSC 0x30000000 +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +/* Reset debug page and also HWord, LWord */ +#define bDebugPage 0xfff +/* Reset debug page and LWord */ +#define bDebugItem 0xff +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +/* Page a */ +#define bCCKBBMode 0x3 +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 +#define bCCKSideBand 0x10 +#define bCCKScramble 0x8 +#define bCCKAntDiversity 0x8000 #define bCCKCarrierRecovery 0x4000 -#define bCCKTxRate 0x3000 -#define bCCKDCCancel 0x0800 -#define bCCKISICancel 0x0400 -#define bCCKMatchFilter 0x0200 -#define bCCKEqualizer 0x0100 -#define bCCKPreambleDetect 0x800000 -#define bCCKFastFalseCCA 0x400000 -#define bCCKChEstStart 0x300000 -#define bCCKCCACount 0x080000 -#define bCCKcs_lim 0x070000 -#define bCCKBistMode 0x80000000 -#define bCCKCCAMask 0x40000000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 #define bCCKTxDACPhase 0x4 -#define bCCKRxADCPhase 0x20000000 //r_rx_clk +/* r_rx_clk */ +#define bCCKRxADCPhase 0x20000000 #define bCCKr_cp_mode0 0x0100 -#define bCCKTxDCOffset 0xf0 -#define bCCKRxDCOffset 0xf -#define bCCKCCAMode 0xc000 -#define bCCKFalseCS_lim 0x3f00 -#define bCCKCS_ratio 0xc00000 -#define bCCKCorgBit_sel 0x300000 -#define bCCKPD_lim 0x0f0000 -#define bCCKNewCCA 0x80000000 -#define bCCKRxHPofIG 0x8000 -#define bCCKRxIG 0x7f00 -#define bCCKLNAPolarity 0x800000 -#define bCCKRx1stGain 0x7f0000 -#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity -#define bCCKRxAGCSatLevel 0x1f000000 -#define bCCKRxAGCSatCount 0xe0 -#define bCCKRxRFSettle 0x1f //AGCsamp_dly -#define bCCKFixedRxAGC 0x8000 -//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 -#define bCCKAntennaPolarity 0x2000 -#define bCCKTxFilterType 0x0c00 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +/* CCK Rx Initial gain polarity */ +#define bCCKRFExtend 0x20000000 +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +/* AGCSAmp_dly */ +#define bCCKRxRFSettle 0x1f +#define bCCKFixedRxAGC 0x8000 +/*#define bCCKRxAGCFormat 0x4000 remove to HSSI register 0x824 */ +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 #define bCCKRxAGCReportType 0x0300 -#define bCCKRxDAGCEn 0x80000000 -#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 #define bCCKRxDAGCSatLevel 0x1f000000 -#define bCCKTimingRecovery 0x800000 -#define bCCKTxC0 0x3f0000 -#define bCCKTxC1 0x3f000000 -#define bCCKTxC2 0x3f -#define bCCKTxC3 0x3f00 -#define bCCKTxC4 0x3f0000 -#define bCCKTxC5 0x3f000000 -#define bCCKTxC6 0x3f -#define bCCKTxC7 0x3f00 -#define bCCKDebugPort 0xff0000 -#define bCCKDACDebug 0x0f000000 -#define bCCKFalseAlarmEnable 0x8000 -#define bCCKFalseAlarmRead 0x4000 -#define bCCKTRSSI 0x7f -#define bCCKRxAGCReport 0xfe -#define bCCKRxReport_AntSel 0x80000000 -#define bCCKRxReport_MFOff 0x40000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 #define bCCKRxRxReport_SQLoss 0x20000000 -#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Pktloss 0x10000000 #define bCCKRxReport_Lockedbit 0x08000000 #define bCCKRxReport_RateError 0x04000000 -#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxReport_RxRate 0x03000000 #define bCCKRxFACounterLower 0xff #define bCCKRxFACounterUpper 0xff000000 -#define bCCKRxHPAGCStart 0xe000 -#define bCCKRxHPAGCFinal 0x1c00 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 #define bCCKRxFalseAlarmEnable 0x8000 -#define bCCKFACounterFreeze 0x4000 - -#define bCCKTxPathSel 0x10000000 -#define bCCKDefaultRxPath 0xc000000 -#define bCCKOptionRxPath 0x3000000 - -//page c -#define bNumOfSTF 0x3 -#define bShift_L 0xc0 -#define bGI_TH 0xc -#define bRxPathA 0x1 -#define bRxPathB 0x2 -#define bRxPathC 0x4 -#define bRxPathD 0x8 -#define bTxPathA 0x1 -#define bTxPathB 0x2 -#define bTxPathC 0x4 -#define bTxPathD 0x8 -#define bTRSSIFreq 0x200 -#define bADCBackoff 0x3000 -#define bDFIRBackoff 0xc000 -#define bTRSSILatchPhase 0x10000 -#define bRxIDCOffset 0xff -#define bRxQDCOffset 0xff00 -#define bRxDFIRMode 0x1800000 -#define bRxDCNFType 0xe000000 -#define bRXIQImb_A 0x3ff -#define bRXIQImb_B 0xfc00 -#define bRXIQImb_C 0x3f0000 -#define bRXIQImb_D 0xffc00000 -#define bDC_dc_Notch 0x60000 -#define bRxNBINotch 0x1f000000 -#define bPD_TH 0xf -#define bPD_TH_Opt2 0xc000 -#define bPWED_TH 0x700 -#define bIfMF_Win_L 0x800 -#define bPD_Option 0x1000 -#define bMF_Win_L 0xe000 -#define bBW_Search_L 0x30000 -#define bwin_enh_L 0xc0000 -#define bBW_TH 0x700000 -#define bED_TH2 0x3800000 -#define bBW_option 0x4000000 -#define bRatio_TH 0x18000000 -#define bWindow_L 0xe0000000 -#define bSBD_Option 0x1 -#define bFrame_TH 0x1c -#define bFS_Option 0x60 -#define bDC_Slope_check 0x80 -#define bFGuard_Counter_DC_L 0xe00 -#define bFrame_Weight_Short 0x7000 -#define bSub_Tune 0xe00000 -#define bFrame_DC_Length 0xe000000 -#define bSBD_start_offset 0x30000000 -#define bFrame_TH_2 0x7 -#define bFrame_GI2_TH 0x38 -#define bGI2_Sync_en 0x40 -#define bSarch_Short_Early 0x300 -#define bSarch_Short_Late 0xc00 -#define bSarch_GI2_Late 0x70000 -#define bCFOAntSum 0x1 -#define bCFOAcc 0x2 -#define bCFOStartOffset 0xc -#define bCFOLookBack 0x70 -#define bCFOSumWeight 0x80 -#define bDAGCEnable 0x10000 -#define bTXIQImb_A 0x3ff -#define bTXIQImb_B 0xfc00 -#define bTXIQImb_C 0x3f0000 -#define bTXIQImb_D 0xffc00000 -#define bTxIDCOffset 0xff -#define bTxQDCOffset 0xff00 -#define bTxDFIRMode 0x10000 -#define bTxPesudoNoiseOn 0x4000000 -#define bTxPesudoNoise_A 0xff -#define bTxPesudoNoise_B 0xff00 -#define bTxPesudoNoise_C 0xff0000 -#define bTxPesudoNoise_D 0xff000000 -#define bCCADropOption 0x20000 -#define bCCADropThres 0xfff00000 -#define bEDCCA_H 0xf -#define bEDCCA_L 0xf0 -#define bLambda_ED 0x300 -#define bRxInitialGain 0x7f -#define bRxAntDivEn 0x80 -#define bRxAGCAddressForLNA 0x7f00 -#define bRxHighPowerFlow 0x8000 -#define bRxAGCFreezeThres 0xc0000 -#define bRxFreezeStep_AGC1 0x300000 -#define bRxFreezeStep_AGC2 0xc00000 -#define bRxFreezeStep_AGC3 0x3000000 -#define bRxFreezeStep_AGC0 0xc000000 -#define bRxRssi_Cmp_En 0x10000000 -#define bRxQuickAGCEn 0x20000000 -#define bRxAGCFreezeThresMode 0x40000000 -#define bRxOverFlowCheckType 0x80000000 -#define bRxAGCShift 0x7f -#define bTRSW_Tri_Only 0x80 -#define bPowerThres 0x300 -#define bRxAGCEn 0x1 -#define bRxAGCTogetherEn 0x2 -#define bRxAGCMin 0x4 -#define bRxHP_Ini 0x7 -#define bRxHP_TRLNA 0x70 -#define bRxHP_RSSI 0x700 -#define bRxHP_BBP1 0x7000 -#define bRxHP_BBP2 0x70000 -#define bRxHP_BBP3 0x700000 -#define bRSSI_H 0x7f0000 //the threshold for high power -#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity -#define bRxSettle_TRSW 0x7 -#define bRxSettle_LNA 0x38 -#define bRxSettle_RSSI 0x1c0 -#define bRxSettle_BBP 0xe00 -#define bRxSettle_RxHP 0x7000 -#define bRxSettle_AntSW_RSSI 0x38000 -#define bRxSettle_AntSW 0xc0000 -#define bRxProcessTime_DAGC 0x300000 -#define bRxSettle_HSSI 0x400000 -#define bRxProcessTime_BBPPW 0x800000 -#define bRxAntennaPowerShift 0x3000000 -#define bRSSITableSelect 0xc000000 -#define bRxHP_Final 0x7000000 -#define bRxHTSettle_BBP 0x7 -#define bRxHTSettle_HSSI 0x8 -#define bRxHTSettle_RxHP 0x70 -#define bRxHTSettle_BBPPW 0x80 -#define bRxHTSettle_Idle 0x300 -#define bRxHTSettle_Reserved 0x1c00 -#define bRxHTRxHPEn 0x8000 -#define bRxHTAGCFreezeThres 0x30000 -#define bRxHTAGCTogetherEn 0x40000 -#define bRxHTAGCMin 0x80000 -#define bRxHTAGCEn 0x100000 -#define bRxHTDAGCEn 0x200000 -#define bRxHTRxHP_BBP 0x1c00000 -#define bRxHTRxHP_Final 0xe0000000 -#define bRxPWRatioTH 0x3 -#define bRxPWRatioEn 0x4 -#define bRxMFHold 0x3800 -#define bRxPD_Delay_TH1 0x38 -#define bRxPD_Delay_TH2 0x1c0 -#define bRxPD_DC_COUNT_MAX 0x600 -//#define bRxMF_Hold 0x3800 +#define bCCKFACounterFreeze 0x4000 + +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +/* Page c */ +#define bNumOfSTF 0x3 +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +/* The threshold for high power */ +#define bRSSI_H 0x7f0000 +/* The threshold for ant diversity */ +#define bRSSI_Gen 0x7f000000 +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +/*#define bRxMF_Hold 0x3800*/ #define bRxPD_Delay_TH 0x8000 #define bRxProcess_Delay 0xf0000 #define bRxSearchrange_GI2_Early 0x700000 @@ -661,7 +692,7 @@ #define bExtLNAGain 0x7c00 -//page d +/* Page d */ #define bSTBCEn 0x4 #define bAntennaMapping 0x10 #define bNss 0x20 @@ -671,12 +702,12 @@ #define bOFDMContinueTx 0x10000000 #define bOFDMSingleCarrier 0x20000000 #define bOFDMSingleTone 0x40000000 -//#define bRxPath1 0x01 -//#define bRxPath2 0x02 -//#define bRxPath3 0x04 -//#define bRxPath4 0x08 -//#define bTxPath1 0x10 -//#define bTxPath2 0x20 +/*#define bRxPath1 0x01 +#define bRxPath2 0x02 +#define bRxPath3 0x04 +#define bRxPath4 0x08 +#define bTxPath1 0x10 +#define bTxPath2 0x20*/ #define bHTDetect 0x100 #define bCFOEn 0x10000 #define bCFOValue 0xfff00000 @@ -689,8 +720,10 @@ #define bCounter_MCSNoSupport 0xffff #define bCounter_FastSync 0xffff #define bShortCFO 0xfff -#define bShortCFOTLength 12 //total -#define bShortCFOFLength 11 //fraction +/* total */ +#define bShortCFOTLength 12 +/* fraction */ +#define bShortCFOFLength 11 #define bLongCFO 0x7ff #define bLongCFOTLength 11 #define bLongCFOFLength 11 @@ -767,18 +800,18 @@ #define bUChCfg 0x7000000 #define bUpdEqz 0x8000000 -//page e -#define bTxAGCRate18_06 0x7f7f7f7f -#define bTxAGCRate54_24 0x7f7f7f7f +/* Page e */ +#define bTxAGCRate18_06 0x7f7f7f7f +#define bTxAGCRate54_24 0x7f7f7f7f #define bTxAGCRateMCS32 0x7f -#define bTxAGCRateCCK 0x7f00 +#define bTxAGCRateCCK 0x7f00 #define bTxAGCRateMCS3_MCS0 0x7f7f7f7f #define bTxAGCRateMCS7_MCS4 0x7f7f7f7f #define bTxAGCRateMCS11_MCS8 0x7f7f7f7f #define bTxAGCRateMCS15_MCS12 0x7f7f7f7f -//Rx Pseduo noise +/* Rx Pseduo noise */ #define bRxPesudoNoiseOn 0x20000000 #define bRxPesudoNoise_A 0xff #define bRxPesudoNoise_B 0xff00 @@ -789,8 +822,7 @@ #define bPesudoNoiseState_C 0xffff #define bPesudoNoiseState_D 0xffff0000 -//RF -//Zebra1 +/* RF Zebra 1 */ #define bZebra1_HSSIEnable 0x8 #define bZebra1_TRxControl 0xc00 #define bZebra1_TRxGainSetting 0x07f @@ -801,7 +833,7 @@ #define bZebra1_TxLPFBW 0x400 #define bZebra1_RxLPFBW 0x600 -//Zebra4 +/* Zebra4 */ #define bRTL8256RegModeCtrl1 0x100 #define bRTL8256RegModeCtrl0 0x40 #define bRTL8256_TxLPFBW 0x18 @@ -812,7 +844,7 @@ #define bRTL8258_RxLPFBW 0xc00 #define bRTL8258_RSSILPFBW 0xc0 -//byte endable for sb_write +/* byte endable for sb_write */ #define bByte0 0x1 #define bByte1 0x2 #define bByte2 0x4 @@ -821,7 +853,7 @@ #define bWord1 0xc #define bDWord 0xf -//for PutRegsetting & GetRegSetting BitMask +/* for PutRegsetting & GetRegSetting BitMask */ #define bMaskByte0 0xff #define bMaskByte1 0xff00 #define bMaskByte2 0xff0000 @@ -830,7 +862,7 @@ #define bMaskLWord 0x0000ffff #define bMaskDWord 0xffffffff -//for PutRFRegsetting & GetRFRegSetting BitMask +/* for PutRFRegsetting & GetRFRegSetting BitMask */ #define bMask12Bits 0xfff #define bEnable 0x1 @@ -839,14 +871,16 @@ #define LeftAntenna 0x0 #define RightAntenna 0x1 -#define tCheckTxStatus 500 //500ms -#define tUpdateRxCounter 100 //100ms +/* 500 ms */ +#define tCheckTxStatus 500 +/* 100 ms */ +#define tUpdateRxCounter 100 #define rateCCK 0 #define rateOFDM 1 #define rateHT 2 -//define Register-End +/* define Register-End */ #define bPMAC_End 0x1ff #define bFPGAPHY0_End 0x8ff #define bFPGAPHY1_End 0x9ff @@ -854,12 +888,12 @@ #define bOFDMPHY0_End 0xcff #define bOFDMPHY1_End 0xdff -//define max debug item in each debug page -//#define bMaxItem_FPGA_PHY0 0x9 -//#define bMaxItem_FPGA_PHY1 0x3 -//#define bMaxItem_PHY_11B 0x16 -//#define bMaxItem_OFDM_PHY0 0x29 -//#define bMaxItem_OFDM_PHY1 0x0 +/*#define max debug item in each debug page +#define bMaxItem_FPGA_PHY0 0x9 +#define bMaxItem_FPGA_PHY1 0x3 +#define bMaxItem_PHY_11B 0x16 +#define bMaxItem_OFDM_PHY0 0x29 +#define bMaxItem_OFDM_PHY1 0x0 */ #define bPMACControl 0x0 #define bWMACControl 0x1 @@ -870,12 +904,12 @@ #define PathC 0x2 #define PathD 0x3 -#define rRTL8256RxMixerPole 0xb -#define bZebraRxMixerPole 0x6 -#define rRTL8256TxBBOPBias 0x9 -#define bRTL8256TxBBOPBias 0x400 -#define rRTL8256TxBBBW 19 -#define bRTL8256TxBBBW 0x18 +#define rRTL8256RxMixerPole 0xb +#define bZebraRxMixerPole 0x6 +#define rRTL8256TxBBOPBias 0x9 +#define bRTL8256TxBBOPBias 0x400 +#define rRTL8256TxBBBW 19 +#define bRTL8256TxBBBW 0x18 -#endif //__INC_HAL8190PCIPHYREG_H +#endif /* __INC_HAL8190PCIPHYREG_H */ -- cgit v1.2.3 From 4db3d5e4e7fce813648215d99fdc5d0fcb73128c Mon Sep 17 00:00:00 2001 From: Radu Voicilas Date: Mon, 7 Dec 2009 18:20:08 -0800 Subject: Staging: rtl8192e: Code style fixes for r819xE_phy.h Signed-off-by: Radu Voicilas Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/r819xE_phy.h | 194 ++++++++++++++++++++-------------- 1 file changed, 116 insertions(+), 78 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192e/r819xE_phy.h b/drivers/staging/rtl8192e/r819xE_phy.h index fa77abe88827..41e0d777eabd 100644 --- a/drivers/staging/rtl8192e/r819xE_phy.h +++ b/drivers/staging/rtl8192e/r819xE_phy.h @@ -1,43 +1,46 @@ #ifndef _R819XU_PHY_H #define _R819XU_PHY_H -/* Channel switch:The size of command tables for switch channel*/ + +/* Channel switch: the size of command tables for switch channel */ #define MAX_PRECMD_CNT 16 #define MAX_RFDEPENDCMD_CNT 16 #define MAX_POSTCMD_CNT 16 #ifdef RTL8190P #define MACPHY_Array_PGLength 21 -#define Rtl819XMACPHY_Array_PG Rtl8190PciMACPHY_Array_PG -#define Rtl819XMACPHY_Array Rtl8190PciMACPHY_Array +#define Rtl819XMACPHY_Array_PG Rtl8190PciMACPHY_Array_PG +#define Rtl819XMACPHY_Array Rtl8190PciMACPHY_Array #define RadioC_ArrayLength 246 #define RadioD_ArrayLength 78 -#define Rtl819XRadioA_Array Rtl8190PciRadioA_Array -#define Rtl819XRadioB_Array Rtl8190PciRadioB_Array -#define Rtl819XRadioC_Array Rtl8190PciRadioC_Array -#define Rtl819XRadioD_Array Rtl8190PciRadioD_Array -#define Rtl819XAGCTAB_Array Rtl8190PciAGCTAB_Array -#define PHY_REGArrayLength 280 -#define Rtl819XPHY_REGArray Rtl8190PciPHY_REGArray -#define PHY_REG_1T2RArrayLength 280 -#define Rtl819XPHY_REG_1T2RArray Rtl8190PciPHY_REG_1T2RArray +#define Rtl819XRadioA_Array Rtl8190PciRadioA_Array +#define Rtl819XRadioB_Array Rtl8190PciRadioB_Array +#define Rtl819XRadioC_Array Rtl8190PciRadioC_Array +#define Rtl819XRadioD_Array Rtl8190PciRadioD_Array +#define Rtl819XAGCTAB_Array Rtl8190PciAGCTAB_Array +#define PHY_REGArrayLength 280 +#define Rtl819XPHY_REGArray Rtl8190PciPHY_REGArray +#define PHY_REG_1T2RArrayLength 280 +#define Rtl819XPHY_REG_1T2RArray Rtl8190PciPHY_REG_1T2RArray +#endif + + +#ifdef RTL8192E +#define MACPHY_Array_PGLength 30 +#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG +#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array +#define RadioC_ArrayLength 1 +#define RadioD_ArrayLength 1 +#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array +#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array +#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array +#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array +#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array +#define PHY_REGArrayLength 1 +#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray +#define PHY_REG_1T2RArrayLength 296 +#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray #endif - #ifdef RTL8192E - #define MACPHY_Array_PGLength 30 - #define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG - #define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array - #define RadioC_ArrayLength 1 - #define RadioD_ArrayLength 1 - #define Rtl819XRadioA_Array Rtl8192PciERadioA_Array - #define Rtl819XRadioB_Array Rtl8192PciERadioB_Array - #define Rtl819XRadioC_Array Rtl8192PciERadioC_Array - #define Rtl819XRadioD_Array Rtl8192PciERadioD_Array - #define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array - #define PHY_REGArrayLength 1 - #define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray - #define PHY_REG_1T2RArrayLength 296 - #define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray - #endif #define AGCTAB_ArrayLength 384 #define MACPHY_ArrayLength 18 @@ -45,7 +48,7 @@ #define RadioB_ArrayLength 78 -typedef enum _SwChnlCmdID{ +typedef enum _SwChnlCmdID { CmdID_End, CmdID_SetTxPowerLevel, CmdID_BBRegWrite10, @@ -53,16 +56,15 @@ typedef enum _SwChnlCmdID{ CmdID_WritePortUshort, CmdID_WritePortUchar, CmdID_RF_WriteReg, -}SwChnlCmdID; +} SwChnlCmdID; -/*--------------------------------Define structure--------------------------------*/ -/* 1. Switch channel related */ -typedef struct _SwChnlCmd{ - SwChnlCmdID CmdID; - u32 Para1; - u32 Para2; - u32 msDelay; -}__attribute__ ((packed)) SwChnlCmd; +/* switch channel data structure */ +typedef struct _SwChnlCmd { + SwChnlCmdID CmdID; + u32 Para1; + u32 Para2; + u32 msDelay; +} __attribute__ ((packed)) SwChnlCmd; extern u32 rtl819XMACPHY_Array_PG[]; extern u32 rtl819XPHY_REG_1T2RArray[]; @@ -72,54 +74,90 @@ extern u32 rtl819XRadioB_Array[]; extern u32 rtl819XRadioC_Array[]; extern u32 rtl819XRadioD_Array[]; -typedef enum _HW90_BLOCK{ +typedef enum _HW90_BLOCK { HW90_BLOCK_MAC = 0, HW90_BLOCK_PHY0 = 1, HW90_BLOCK_PHY1 = 2, HW90_BLOCK_RF = 3, - HW90_BLOCK_MAXIMUM = 4, // Never use this -}HW90_BLOCK_E, *PHW90_BLOCK_E; - -typedef enum _RF90_RADIO_PATH{ - RF90_PATH_A = 0, //Radio Path A - RF90_PATH_B = 1, //Radio Path B - RF90_PATH_C = 2, //Radio Path C - RF90_PATH_D = 3, //Radio Path D - RF90_PATH_MAX //Max RF number 92 support -}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E; - -#define bMaskByte0 0xff -#define bMaskByte1 0xff00 -#define bMaskByte2 0xff0000 -#define bMaskByte3 0xff000000 -#define bMaskHWord 0xffff0000 -#define bMaskLWord 0x0000ffff -#define bMaskDWord 0xffffffff - -//extern u32 rtl8192_CalculateBitShift(u32 dwBitMask); -extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath); -extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData); -extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask); -//extern u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset); -//extern void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); -extern void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data); -extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask); -extern void rtl8192_phy_configmac(struct net_device* dev); -extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType); -//extern void rtl8192_InitBBRFRegDef(struct net_device* dev); -extern RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath); -//extern RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev); -extern RT_STATUS rtl8192_BBConfig(struct net_device* dev); -extern void rtl8192_phy_getTxPower(struct net_device* dev); -extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel); + /* Don't ever use this. */ + HW90_BLOCK_MAXIMUM = 4, +} HW90_BLOCK_E, *PHW90_BLOCK_E; + +typedef enum _RF90_RADIO_PATH { + /* Radio paths */ + RF90_PATH_A = 0, + RF90_PATH_B = 1, + RF90_PATH_C = 2, + RF90_PATH_D = 3, + + /* Max RF number 92 support */ + RF90_PATH_MAX +} RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E; + +#define bMaskByte0 0xff +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff + +/*extern u32 rtl8192_CalculateBitShift(u32 dwBitMask); + +extern u32 rtl8192_phy_RFSerialRead(struct net_device *dev, + RF90_RADIO_PATH_E eRFPath, u32 Offset); + +extern void rtl8192_phy_RFSerialWrite(struct net_device *dev, + RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); + +extern void rtl8192_InitBBRFRegDef(struct net_device *dev); + +extern RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device *dev); */ + +extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath); + +extern void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, + u32 dwBitMask, u32 dwData); + +extern u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, + u32 dwBitMask); + +extern void rtl8192_phy_SetRFReg(struct net_device *dev, + RF90_RADIO_PATH_E eRFPath, u32 RegAddr, + u32 BitMask, u32 Data); + +extern u32 rtl8192_phy_QueryRFReg(struct net_device *dev, + RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask); + +extern void rtl8192_phy_configmac(struct net_device *dev); + +extern void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType); + +extern RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device *dev, + HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath); + +extern RT_STATUS rtl8192_BBConfig(struct net_device *dev); + +extern void rtl8192_phy_getTxPower(struct net_device *dev); + +extern void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel); + extern RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev); + extern void rtl8192_phy_updateInitGain(struct net_device* dev); -extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath); -extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel); -extern void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); +extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, + RF90_RADIO_PATH_E eRFPath); + +extern u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel); + +extern void rtl8192_SetBWMode(struct net_device *dev, + HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); + extern void rtl8192_SwChnl_WorkItem(struct net_device *dev); + extern void rtl8192_SetBWModeWorkItem(struct net_device *dev); + extern void InitialGain819xPci(struct net_device *dev, u8 Operation); -#endif +#endif /* _R819XU_PHY_H */ -- cgit v1.2.3 From da94a755cabe96d2c00af2b1b1aff84307c437fe Mon Sep 17 00:00:00 2001 From: Radu Voicilas Date: Mon, 7 Dec 2009 18:20:09 -0800 Subject: Staging: rtl8192e: Small code fixes for r819xE_firmware.c Signed-off-by: Radu Voicilas Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/r819xE_firmware.c | 81 ++++++++++++++++++------------ 1 file changed, 48 insertions(+), 33 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192e/r819xE_firmware.c b/drivers/staging/rtl8192e/r819xE_firmware.c index 1f9e413bcd49..e05ba1748d30 100644 --- a/drivers/staging/rtl8192e/r819xE_firmware.c +++ b/drivers/staging/rtl8192e/r819xE_firmware.c @@ -1,5 +1,5 @@ /* - * Procedure: Init boot code/firmware code/data session + * Procedure: Init boot code/firmware code/data session * * Description: This routine will intialize firmware. If any error occurs * during the initialization process, the routine shall terminate @@ -7,19 +7,21 @@ * NdisOpenFile only from MiniportInitialize. * * Arguments: The pointer of the adapter - + * * Returns: * NDIS_STATUS_FAILURE - the following initialization process * should be terminated * NDIS_STATUS_SUCCESS - if firmware initialization process * success */ + #include "r8192E.h" #include "r8192E_hw.h" + #include /* It should be double word alignment */ -#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4 * (v / 4) - 8) +#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4 * (v / 4) - 8) enum firmware_init_step { FW_INIT_STEP0_BOOT = 0, @@ -47,17 +49,17 @@ void firmware_init_param(struct net_device *dev) static bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, u32 buffer_len) { - struct r8192_priv *priv = ieee80211_priv(dev); - bool rt_status = true; - u16 frag_threshold; - u16 frag_length, frag_offset = 0; - int i; - - rt_firmware *pfirmware = priv->pFirmware; - struct sk_buff *skb; - unsigned char *seg_ptr; - cb_desc *tcb_desc; - u8 bLastIniPkt; + struct r8192_priv *priv = ieee80211_priv(dev); + bool rt_status = true; + u16 frag_threshold; + u16 frag_length, frag_offset = 0; + int i; + + rt_firmware *pfirmware = priv->pFirmware; + struct sk_buff *skb; + unsigned char *seg_ptr; + cb_desc *tcb_desc; + u8 bLastIniPkt; firmware_init_param(dev); @@ -89,10 +91,17 @@ static bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, * Transform from little endian to big endian and pending zero */ for (i = 0; i < frag_length; i += 4) { - *seg_ptr++ = ((i+0) < frag_length) ? code_virtual_address[i+3] : 0; - *seg_ptr++ = ((i+1) < frag_length) ? code_virtual_address[i+2] : 0; - *seg_ptr++ = ((i+2) < frag_length) ? code_virtual_address[i+1] : 0; - *seg_ptr++ = ((i+3) < frag_length) ? code_virtual_address[i+0] : 0; + *seg_ptr++ = ((i+0) < frag_length) ? \ + code_virtual_address[i+3] : 0; + + *seg_ptr++ = ((i+1) < frag_length) ? \ + code_virtual_address[i+2] : 0; + + *seg_ptr++ = ((i+2) < frag_length) ? \ + code_virtual_address[i+1] : 0; + + *seg_ptr++ = ((i+3) < frag_length) ? \ + code_virtual_address[i+0] : 0; } tcb_desc->txbuf_size = (u16)i; skb_put(skb, i); @@ -204,16 +213,16 @@ CPUCheckFirmwareReady_Fail: bool init_firmware(struct net_device *dev) { - struct r8192_priv *priv = ieee80211_priv(dev); - bool rt_status = TRUE; - u32 file_length = 0; - u8 *mapped_file = NULL; - u32 init_step = 0; - enum opt_rst_type rst_opt = OPT_SYSTEM_RESET; + struct r8192_priv *priv = ieee80211_priv(dev); + bool rt_status = true; + u32 file_length = 0; + u8 *mapped_file = NULL; + u32 init_step = 0; + enum opt_rst_type rst_opt = OPT_SYSTEM_RESET; enum firmware_init_step starting_state = FW_INIT_STEP0_BOOT; - rt_firmware *pfirmware = priv->pFirmware; - const struct firmware *fw_entry; + rt_firmware *pfirmware = priv->pFirmware; + const struct firmware *fw_entry; const char *fw_name[3] = { "RTL8192E/boot.img", "RTL8192E/main.img", "RTL8192E/data.img"}; @@ -240,31 +249,37 @@ bool init_firmware(struct net_device *dev) * Download boot, main, and data image for System reset. * Download data image for firmware reseta */ - for (init_step = starting_state; init_step <= FW_INIT_STEP2_DATA; init_step++) { + for (init_step = starting_state; init_step <= FW_INIT_STEP2_DATA; \ + init_step++) { /* * Open Image file, and map file to contineous memory if open file success. * or read image file from array. Default load from IMG file */ if (rst_opt == OPT_SYSTEM_RESET) { if (pfirmware->firmware_buf_size[init_step] == 0) { - rc = request_firmware(&fw_entry, fw_name[init_step], &priv->pdev->dev); + rc = request_firmware(&fw_entry, + fw_name[init_step], &priv->pdev->dev); + if (rc < 0) { RT_TRACE(COMP_FIRMWARE, "request firmware fail!\n"); goto download_firmware_fail; } if (fw_entry->size > sizeof(pfirmware->firmware_buf[init_step])) { - RT_TRACE(COMP_FIRMWARE, "img file size exceed the container buffer fail!\n"); + RT_TRACE(COMP_FIRMWARE, \ + "img file size exceed the container buffer fail!\n"); goto download_firmware_fail; } if (init_step != FW_INIT_STEP1_MAIN) { - memcpy(pfirmware->firmware_buf[init_step], fw_entry->data, fw_entry->size); + memcpy(pfirmware->firmware_buf[init_step], + fw_entry->data, fw_entry->size); pfirmware->firmware_buf_size[init_step] = fw_entry->size; } else { memset(pfirmware->firmware_buf[init_step], 0, 128); - memcpy(&pfirmware->firmware_buf[init_step][128], fw_entry->data, fw_entry->size); + memcpy(&pfirmware->firmware_buf[init_step][128], fw_entry->data, + fw_entry->size); pfirmware->firmware_buf_size[init_step] = fw_entry->size+128; } @@ -273,6 +288,7 @@ bool init_firmware(struct net_device *dev) } mapped_file = pfirmware->firmware_buf[init_step]; file_length = pfirmware->firmware_buf_size[init_step]; + } else if (rst_opt == OPT_FIRMWARE_RESET) { /* we only need to download data.img here */ mapped_file = pfirmware->firmware_buf[init_step]; @@ -346,7 +362,6 @@ bool init_firmware(struct net_device *dev) download_firmware_fail: RT_TRACE(COMP_ERR, "ERR in %s()\n", __func__); - rt_status = FALSE; + rt_status = false; return rt_status; - } -- cgit v1.2.3 From aa337ef1fbc9650f8b5b9087af1dac33f71eb01c Mon Sep 17 00:00:00 2001 From: Scott Smedley Date: Fri, 18 Dec 2009 10:54:26 -0800 Subject: Staging: add dt3155 driver This is a driver for the DT3155 Digitizer Signed-off-by: Scott Smedley Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dt3155/Makefile | 27 + drivers/staging/dt3155/allocator.README | 98 +++ drivers/staging/dt3155/allocator.c | 296 ++++++++ drivers/staging/dt3155/allocator.h | 28 + drivers/staging/dt3155/dt3155.h | 175 +++++ drivers/staging/dt3155/dt3155.sysvinit | 60 ++ drivers/staging/dt3155/dt3155_drv.c | 1203 +++++++++++++++++++++++++++++++ drivers/staging/dt3155/dt3155_drv.h | 50 ++ drivers/staging/dt3155/dt3155_io.c | 236 ++++++ drivers/staging/dt3155/dt3155_io.h | 400 ++++++++++ drivers/staging/dt3155/dt3155_isr.c | 545 ++++++++++++++ drivers/staging/dt3155/dt3155_isr.h | 77 ++ drivers/staging/dt3155/pci-compat.h | 97 +++ drivers/staging/dt3155/sysdep.h | 820 +++++++++++++++++++++ 14 files changed, 4112 insertions(+) create mode 100644 drivers/staging/dt3155/Makefile create mode 100644 drivers/staging/dt3155/allocator.README create mode 100644 drivers/staging/dt3155/allocator.c create mode 100644 drivers/staging/dt3155/allocator.h create mode 100644 drivers/staging/dt3155/dt3155.h create mode 100644 drivers/staging/dt3155/dt3155.sysvinit create mode 100644 drivers/staging/dt3155/dt3155_drv.c create mode 100644 drivers/staging/dt3155/dt3155_drv.h create mode 100644 drivers/staging/dt3155/dt3155_io.c create mode 100644 drivers/staging/dt3155/dt3155_io.h create mode 100644 drivers/staging/dt3155/dt3155_isr.c create mode 100644 drivers/staging/dt3155/dt3155_isr.h create mode 100644 drivers/staging/dt3155/pci-compat.h create mode 100644 drivers/staging/dt3155/sysdep.h (limited to 'drivers') diff --git a/drivers/staging/dt3155/Makefile b/drivers/staging/dt3155/Makefile new file mode 100644 index 000000000000..1717ffbf682f --- /dev/null +++ b/drivers/staging/dt3155/Makefile @@ -0,0 +1,27 @@ + +ifeq ($(shell [[ `uname -r | cut -f 1,2 -d\.` < 2.6 ]] && echo pre2.6),pre2.6) +# system with a pre 2.6 kernel _don't_ use kbuild. +all: + $(MAKE) -f Makefile.pre-2.6 + +clean: + rm -f *.o + +else +# systems with a 2.6 or later kernel use kbuild. +ifneq ($(KERNELRELEASE),) +obj-m := dt3155.o +dt3155-objs := dt3155_drv.o dt3155_isr.o dt3155_io.o allocator.o + +else +KDIR := /lib/modules/$(shell uname -r)/build +PWD := $(shell pwd) + +all: + $(MAKE) -C $(KDIR) M=$(PWD) modules + +clean: + rm -rf *.o *.mod *.mod.c *.ko .dt3155* .allocator.o.cmd .tmp_versions + +endif +endif diff --git a/drivers/staging/dt3155/allocator.README b/drivers/staging/dt3155/allocator.README new file mode 100644 index 000000000000..05700b6c926c --- /dev/null +++ b/drivers/staging/dt3155/allocator.README @@ -0,0 +1,98 @@ + +The allocator shown here exploits high memory. This document explains +how a user can deal with drivers uses this allocator and how a +programmer can link in the module. + +The module is being used by my pxc and pxdrv device drivers (as well as +other ones), available from ftp.systemy.it/pub/develop and +ftp.linux.it/pub/People/Rubini + + User's manual + ============= + + +One of the most compelling problems with any DMA-capable device is the +allocation of a suitable memory buffer. The "allocator" module tries +to deal with the problem in a clean way. The module is able to use +high memory (above the one used in normal operation) for DMA +allocation. + +To prevent the kernel for using high memory, so that it remains +available for DMA, you should pass a command line argument to the +kernel. Command line arguments can be passed to Lilo, to Loadlin or +to whichever loader you are using (unless it's very poor in design). +For Lilo, either use "append=" in /etc/lilo.conf or add commandline +arguments to the interactive prompt. For example, I have a 32MB box +and reserve two megs for DMA: + +In lilo.conf: + image = /zImage + label = linux + append = "mem=30M" + +Or, interactively: + LILO: linux mem=30M + +Once the kernel is booted with the right command-line argument, any +driver linked with the allocator module will be able to get +DMA-capable memory without much trouble (unless the various drivers +need more memory than available). + +The module implements an alloc/free mechanism, so that it can serve +multiple drivers at the same time. Note however that the allocator +uses all of high memory and assumes to be the only piece of software +using such memory. + + + Programmer's manual + =================== + +The allocator, as released, is designed to be linked to a device +driver. In this case, the driver must call allocator_init() before +using the allocator and must call allocator_cleanup() before +unloading. This is usually done from within init_module() and +cleanup_module(). If the allocator is linked to a driver, it won't be +possible for several drivers to allocate high DMA memory, as explained +above. + +It is possible, on the other hand, to compile the module as a standalone +module, so that several modules can rely on the allocator for they DMA +buffers. To compile the allocator as a standalone module, do the +following in this directory (or provide a suitable Makefile, or edit +the source code): + + make allocator.o CC="gcc -Dallocator_init=init_module -Dallocator_cleanup=cleanup_module -include /usr/include/linux/module.h" + +The previous commandline tells to include in the +first place, and to rename the init and cleanup function to the ones +needed for module loading and unloading. Drivers using a standalone +allocator won't need to call allocator_init() nor allocator_cleanup(). + +The allocator exports the following functions (declared in allocator.h): + + unsigned long allocator_allocate_dma (unsigned long kilobytes, + int priority); + + This function returns a physical address, over high_memory, + which corresponds to an area of at least "kilobytes" kilobytes. + The area will be owned by the module calling the function. + The returned address can be passed to device boards, to instruct + their DMA controllers, via phys_to_bus(). The address can be used + by C code after vremap()/ioremap(). The "priority" argument should + be GFP_KERNEL or GFP_ATOMIC, according to the context of the + caller; it is used to call kmalloc(), as the allocator must keep + track of any region it gives away. In case of error the function + returns 0, and the caller is expected to issue a -ENOMEM error. + + + void allocator_free_dma (unsigned long address); + + This function is the reverse of the previous one. If a driver + doesn't free the DMA memory it allocated, the allocator will + consider such memory as busy. Note, however, that + allocator_cleanup() calls kfree() on every region it reclaimed, + so that a driver with the allocator linked in can avoid calling + allocator_free_dma() at unload time. + + + diff --git a/drivers/staging/dt3155/allocator.c b/drivers/staging/dt3155/allocator.c new file mode 100644 index 000000000000..90429db1c5f7 --- /dev/null +++ b/drivers/staging/dt3155/allocator.c @@ -0,0 +1,296 @@ +/* + * allocator.c -- allocate after high_memory, if available + * + * NOTE: this is different from my previous allocator, the one that + * assembles pages, which revealed itself both slow and unreliable. + * + * Copyright (C) 1998 rubini@linux.it (Alessandro Rubini) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + +-- Changes -- + + Date Programmer Description of changes made + ------------------------------------------------------------------- + 02-Aug-2002 NJC allocator now steps in 1MB increments, rather + than doubling its size each time. + Also, allocator_init(u_int *) now returns + (in the first arg) the size of the free + space. This is no longer consistent with + using the allocator as a module, and some changes + may be necessary for that purpose. This was + designed to work with the DT3155 driver, in + stand alone mode only!!! + 26-Oct-2009 SS Port to 2.6.30 kernel. + */ + + +#ifndef __KERNEL__ +# define __KERNEL__ +#endif +#ifndef MODULE +# define MODULE +#endif + +#include + +#include +#include +#include +#include +#include +#include +#include /* PAGE_ALIGN() */ + +#include + +#include "sysdep.h" + +/*#define ALL_DEBUG*/ +#define ALL_MSG "allocator: " + +#undef PDEBUG /* undef it, just in case */ +#ifdef ALL_DEBUG +# define __static +# define DUMP_LIST() dump_list() +# ifdef __KERNEL__ + /* This one if debugging is on, and kernel space */ +# define PDEBUG(fmt, args...) printk( KERN_DEBUG ALL_MSG fmt, ## args) +# else + /* This one for user space */ +# define PDEBUG(fmt, args...) fprintf(stderr, fmt, ## args) +# endif +#else +# define PDEBUG(fmt, args...) /* not debugging: nothing */ +# define DUMP_LIST() +# define __static static +#endif + +#undef PDEBUGG +#define PDEBUGG(fmt, args...) +/*#define PDEBUGG(fmt, args...) printk( KERN_DEBUG ALL_MSG fmt, ## args)*/ + + +int allocator_himem = 1; /* 0 = probe, pos. = megs, neg. = disable */ +int allocator_step = 1; /* This is the step size in MB */ +int allocator_probe = 1; /* This is a flag -- 1=probe, 0=don't probe */ + +static unsigned long allocator_buffer = 0; /* physical address */ +static unsigned long allocator_buffer_size = 0; /* kilobytes */ + +/* + * The allocator keeps a list of DMA areas, so multiple devices + * can coexist. The list is kept sorted by address + */ + +struct allocator_struct { + unsigned long address; + unsigned long size; + struct allocator_struct *next; +}; + +struct allocator_struct *allocator_list = NULL; + + +#ifdef ALL_DEBUG +static int dump_list(void) +{ + struct allocator_struct *ptr; + + PDEBUG("Current list:\n"); + for (ptr = allocator_list; ptr; ptr = ptr->next) { + PDEBUG("0x%08lx (size %likB)\n",ptr->address,ptr->size>>10); + } + return 0; +} +#endif + +/* ======================================================================== + * This function is the actual allocator. + * + * If space is available in high memory (as detected at load time), that + * one is returned. The return value is a physical address (i.e., it can + * be used straight ahead for DMA, but needs remapping for program use). + */ + +unsigned long allocator_allocate_dma (unsigned long kilobytes, int prio) +{ + struct allocator_struct *ptr = allocator_list, *newptr; + unsigned long bytes = kilobytes << 10; + + /* check if high memory is available */ + if (!allocator_buffer) + return 0; + + /* Round it to a multiple of the pagesize */ + bytes = PAGE_ALIGN(bytes); + PDEBUG("request for %li bytes\n", bytes); + + while (ptr && ptr->next) { + if (ptr->next->address - (ptr->address + ptr->size) >= bytes) + break; /* enough space */ + ptr = ptr->next; + } + if (!ptr->next) { + DUMP_LIST(); + PDEBUG("alloc failed\n"); + return 0; /* end of list */ + } + newptr = kmalloc(sizeof(struct allocator_struct),prio); + if (!newptr) + return 0; + + /* ok, now stick it after ptr */ + newptr->address = ptr->address + ptr->size; + newptr->size = bytes; + newptr->next = ptr->next; + ptr->next = newptr; + + DUMP_LIST(); + PDEBUG("returning 0x%08lx\n",newptr->address); + return newptr->address; +} + +int allocator_free_dma (unsigned long address) +{ + struct allocator_struct *ptr = allocator_list, *prev; + + while (ptr && ptr->next) { + if (ptr->next->address == address) + break; + ptr = ptr->next; + } + /* the one being freed is ptr->next */ + prev = ptr; ptr = ptr->next; + + if (!ptr) { + printk(KERN_ERR ALL_MSG "free_dma(0x%08lx) but add. not allocated\n", + ptr->address); + return -EINVAL; + } + PDEBUGG("freeing: %08lx (%li) next %08lx\n",ptr->address,ptr->size, + ptr->next->address); + prev->next = ptr->next; + kfree(ptr); + + /* dump_list(); */ + return 0; +} + +/* ======================================================================== + * Init and cleanup + * + * On cleanup everything is released. If the list is not empty, that a + * problem of our clients + */ +int allocator_init(u_long *allocator_max) +{ + /* check how much free memory is there */ + + volatile void *remapped; + unsigned long max; + unsigned long trial_size = allocator_himem<<20; + unsigned long last_trial = 0; + unsigned long step = allocator_step<<20; + unsigned long i=0; + struct allocator_struct *head, *tail; + char test_string[]="0123456789abcde"; /* 16 bytes */ + + PDEBUGG("himem = %i\n",allocator_himem); + if (allocator_himem < 0) /* don't even try */ + return -EINVAL; + + if (!trial_size) trial_size = 1<<20; /* not specified: try one meg */ + + while (1) { + remapped = ioremap(__pa(high_memory), trial_size); + if (!remapped) + { + PDEBUGG("%li megs failed!\n",trial_size>>20); + break; + } + PDEBUGG("Trying %li megs (at %p, %p)\n",trial_size>>20, + (void *)__pa(high_memory), remapped); + for (i=last_trial; i>20); + break; + } + if (!allocator_probe) break; + } + PDEBUG("%li megs (%li k, %li b)\n",i>>20,i>>10,i); + allocator_buffer_size = i>>10; /* kilobytes */ + allocator_buffer = __pa(high_memory); + if (!allocator_buffer_size) { + printk(KERN_WARNING ALL_MSG "no free high memory to use\n"); + return -ENOMEM; + } + + /* + * to simplify things, always have two cells in the list: + * the first and the last. This avoids some conditionals and + * extra code when allocating and deallocating: we only play + * in the middle of the list + */ + head = kmalloc(sizeof(struct allocator_struct),GFP_KERNEL); + if (!head) + return -ENOMEM; + tail = kmalloc(sizeof(struct allocator_struct),GFP_KERNEL); + if (!tail) { + kfree(head); + return -ENOMEM; + } + + max = allocator_buffer_size<<10; + + head->size = tail->size = 0; + head->address = allocator_buffer; + tail->address = allocator_buffer + max; + head->next = tail; + tail->next = NULL; + allocator_list = head; + + *allocator_max = allocator_buffer_size; /* Back to the user code, in KB */ + + return 0; /* ok, ready */ +} + +void allocator_cleanup(void) +{ + struct allocator_struct *ptr, *next; + + for (ptr = allocator_list; ptr; ptr = next) { + next = ptr->next; + PDEBUG("freeing list: 0x%08lx\n",ptr->address); + kfree(ptr); + } + + allocator_buffer = 0; + allocator_buffer_size = 0; + allocator_list = NULL; +} + + diff --git a/drivers/staging/dt3155/allocator.h b/drivers/staging/dt3155/allocator.h new file mode 100644 index 000000000000..ecc8680e7d45 --- /dev/null +++ b/drivers/staging/dt3155/allocator.h @@ -0,0 +1,28 @@ +/* + * allocator.h -- prototypes for allocating high memory + * + * NOTE: this is different from my previous allocator, the one that + * assembles pages, which revealed itself both slow and unreliable. + * + * Copyright (C) 1998 rubini@linux.it (Alessandro Rubini) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +void allocator_free_dma(unsigned long address); +unsigned long allocator_allocate_dma (unsigned long kilobytes, int priority); +int allocator_init(u_long *); +void allocator_cleanup(void); diff --git a/drivers/staging/dt3155/dt3155.h b/drivers/staging/dt3155/dt3155.h new file mode 100644 index 000000000000..2e158151a755 --- /dev/null +++ b/drivers/staging/dt3155/dt3155.h @@ -0,0 +1,175 @@ +/* + +Copyright 1996,2002,2005 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, + Jason Lapenta, Scott Smedley + +This file is part of the DT3155 Device Driver. + +The DT3155 Device Driver is free software; you can redistribute it +and/or modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2 of the +License, or (at your option) any later version. + +The DT3155 Device Driver is distributed in the hope that it will be +useful, but WITHOUT ANY WARRANTY; without even the implied warranty +of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with the DT3155 Device Driver; if not, write to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, +MA 02111-1307 USA + + $Id: dt3155.h,v 1.11 2005/08/09 06:08:51 ssmedley Exp $ + +-- Changes -- + + Date Programmer Description of changes made + ------------------------------------------------------------------- + 03-Jul-2000 JML n/a + 10-Oct-2001 SS port to 2.4 kernel. + 24-Jul-2002 SS remove unused code & added GPL licence. + 05-Aug-2005 SS port to 2.6 kernel; make CCIR mode default. + +*/ + +#ifndef _DT3155_INC +#define _DT3155_INC + +#ifdef __KERNEL__ +#include /* u_int etc. */ +#include /* struct timeval */ +#else +#include +#include +#include +#include +#endif + + +#define TRUE 1 +#define FALSE 0 + +/* Uncomment this for 50Hz CCIR */ +#define CCIR 1 + +/* Can be 1 or 2 */ +#define MAXBOARDS 1 + +#define BOARD_MAX_BUFFS 3 +#define MAXBUFFERS BOARD_MAX_BUFFS*MAXBOARDS + +#define PCI_PAGE_SIZE (1 << 12) + +#ifdef CCIR +#define DT3155_MAX_ROWS 576 +#define DT3155_MAX_COLS 768 +#define FORMAT50HZ TRUE +#else +#define DT3155_MAX_ROWS 480 +#define DT3155_MAX_COLS 640 +#define FORMAT50HZ FALSE +#endif + +/* Configuration structure */ +struct dt3155_config_s { + u_int acq_mode; + u_int cols, rows; + u_int continuous; +}; + + +/* hold data for each frame */ +typedef struct +{ + u_long addr; /* address of the buffer with the frame */ + u_long tag; /* unique number for the frame */ + struct timeval time; /* time that capture took place */ +} frame_info_t; + +/* Structure for interrupt and buffer handling. */ +/* This is the setup for 1 card */ +struct dt3155_fbuffer_s { + int nbuffers; + + frame_info_t frame_info[ BOARD_MAX_BUFFS ]; + + int empty_buffers[ BOARD_MAX_BUFFS ]; /* indexes empty frames */ + int empty_len; /* Number of empty buffers */ + /* Zero means empty */ + + int active_buf; /* Where data is currently dma'ing */ + int locked_buf; /* Buffers used by user */ + + int ready_que[ BOARD_MAX_BUFFS ]; + u_long ready_head; /* The most recent buffer located here */ + u_long ready_len; /* The number of ready buffers */ + + int even_happened; + int even_stopped; + + int stop_acquire; /* Flag to stop interrupts */ + u_long frame_count; /* Counter for frames acquired by this card */ + +}; + + + +#define DT3155_MODE_FRAME 1 +#define DT3155_MODE_FIELD 2 + +#define DT3155_SNAP 1 +#define DT3155_ACQ 2 + +/* There is one status structure for each card. */ +typedef struct dt3155_status_s +{ + int fixed_mode; /* if 1, we are in fixed frame mode */ + u_long reg_addr; /* Register address for a single card */ + u_long mem_addr; /* Buffer start addr for this card */ + u_long mem_size; /* This is the amount of mem available */ + u_int irq; /* this card's irq */ + struct dt3155_config_s config; /* configuration struct */ + struct dt3155_fbuffer_s fbuffer;/* frame buffer state struct */ + u_long state; /* this card's state */ + u_int device_installed; /* Flag if installed. 1=installed */ +} dt3155_status_t; + +/* Reference to global status structure */ +extern struct dt3155_status_s dt3155_status[MAXBOARDS]; + +#define DT3155_STATE_IDLE 0x00 +#define DT3155_STATE_FRAME 0x01 +#define DT3155_STATE_FLD 0x02 +#define DT3155_STATE_STOP 0x100 +#define DT3155_STATE_ERROR 0x200 +#define DT3155_STATE_MODE 0x0ff + +#define DT3155_IOC_MAGIC '!' + +#define DT3155_SET_CONFIG _IOW( DT3155_IOC_MAGIC, 1, struct dt3155_config_s ) +#define DT3155_GET_CONFIG _IOR( DT3155_IOC_MAGIC, 2, struct dt3155_status_s ) +#define DT3155_STOP _IO( DT3155_IOC_MAGIC, 3 ) +#define DT3155_START _IO( DT3155_IOC_MAGIC, 4 ) +#define DT3155_FLUSH _IO( DT3155_IOC_MAGIC, 5 ) +#define DT3155_IOC_MAXNR 5 + +/* Error codes */ + +#define DT_ERR_NO_BUFFERS 0x10000 /* not used but it might be one day - SS */ +#define DT_ERR_CORRUPT 0x20000 +#define DT_ERR_OVERRUN 0x30000 +#define DT_ERR_I2C_TIMEOUT 0x40000 +#define DT_ERR_MASK 0xff0000/* not used but it might be one day - SS */ + +/* User code will probably want to declare one of these for each card */ +typedef struct dt3155_read_s +{ + u_long offset; + u_long frame_seq; + u_long state; + + frame_info_t frame_info; +} dt3155_read_t; + +#endif /* _DT3155_inc */ diff --git a/drivers/staging/dt3155/dt3155.sysvinit b/drivers/staging/dt3155/dt3155.sysvinit new file mode 100644 index 000000000000..92ec0939cb7a --- /dev/null +++ b/drivers/staging/dt3155/dt3155.sysvinit @@ -0,0 +1,60 @@ +#! /bin/sh +# +# Module load/unload script for use with SysV-style /etc/init.d/ systems. +# On a Debian system, copy this to /etc/init.d/dt3155 and then run +# /usr/sbin/update-rc.d dt3155 defaults 55 +# to create the appropriate /etc/rc?.d/[SK]55dt3155 start/stop links. +# (The "55" is arbitrary but is what I use to load this rather late.) +# +# Andy Dougherty Feb 22 2000 doughera@lafayette.edu +# Dept. of Physics +# Lafayette College, Easton PA 18042 +# + +PATH=/usr/local/sbin:/usr/local/bin:/sbin:/bin:/usr/sbin:/usr/bin + +# Edit to point to your local copy. +FILE=/usr/local/lib/modules/dt3155/dt3155.o +NAME="dt3155" +DESC="dt3155 Frame Grabber module" +DEV="dt3155" + +if test ! -f $FILE; then + echo "Unable to locate $FILE" + exit 0 +fi + +set -e + +case "$1" in + start) + echo -n "Loading $DESC " + if /sbin/insmod -v -f $FILE; then + major=`grep $DEV /proc/devices | awk "{print \\$1}"` + rm -f /dev/dt3155? + mknod /dev/dt3155a c $major 0 + mknod /dev/dt3155b c $major 1 + chmod go+rw /dev/dt3155? + echo + else + echo "$FILE not loaded." + fi + ;; + stop) + echo -n "Unloading $DESC: " + if /sbin/rmmod $NAME ; then + echo + else + echo "$DEV not removed" + exit 0 + fi + rm -f /dev/dt3155? + ;; + *) + echo "Usage: /etc/init.d/$NAME {start|stop}" + exit 1 + ;; +esac + +exit 0 + diff --git a/drivers/staging/dt3155/dt3155_drv.c b/drivers/staging/dt3155/dt3155_drv.c new file mode 100644 index 000000000000..f3ae8e82d64e --- /dev/null +++ b/drivers/staging/dt3155/dt3155_drv.c @@ -0,0 +1,1203 @@ +/* + +Copyright 1996,2002,2005 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, + Jason Lapenta, Scott Smedley, Greg Sharp + +This file is part of the DT3155 Device Driver. + +The DT3155 Device Driver is free software; you can redistribute it +and/or modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2 of the +License, or (at your option) any later version. + +The DT3155 Device Driver is distributed in the hope that it will be +useful, but WITHOUT ANY WARRANTY; without even the implied warranty +of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with the DT3155 Device Driver; if not, write to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, +MA 02111-1307 USA + +-- Changes -- + + Date Programmer Description of changes made + ------------------------------------------------------------------- + 03-Jul-2000 JML n/a + 10-Oct-2001 SS port to 2.4 kernel + 02-Apr-2002 SS Mods to use allocator as a standalone module; + Merged John Roll's changes (john@cfa.harvard.edu) + to make work with multiple boards. + 02-Jul-2002 SS Merged James Rose's chages (rosejr@purdue.edu) to: + * fix successive interrupt-driven captures + * add select/poll support. + 10-Jul-2002 GCS Add error check when ndevices > MAXBOARDS. + 02-Aug-2002 GCS Fix field mode so that odd (lower) field is stored + in lower half of buffer. + 05-Aug-2005 SS port to 2.6 kernel. + 26-Oct-2009 SS port to 2.6.30 kernel. + +-- Notes -- + +** appended "mem=124" in lilo.conf to allow for 4megs free on my 128meg system. + * using allocator.c and allocator.h from o'reilly book (alessandro rubini) + ftp://ftp.systemy.it/pub/develop (see README.allocator) + + + might want to get rid of MAXboards for allocating initial buffer. + confusing and not necessary + + + in cleanup_module the MOD_IN_USE looks like it is check after it should + + * GFP_DMA should not be set with a PCI system (pg 291) + + - NJC why are only two buffers allowed? (see isr, approx line 358) + +*/ + +extern void printques(int); + +#ifdef MODULE +#include +#include +#include + + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,10) +MODULE_LICENSE("GPL"); +#endif + +#endif + +#ifndef CONFIG_PCI +#error "DT3155 : Kernel PCI support not enabled (DT3155 drive requires PCI)" +#endif + +#include +#include +#include + +#include +#include + +#include "dt3155.h" +#include "dt3155_drv.h" +#include "dt3155_isr.h" +#include "dt3155_io.h" +#include "allocator.h" + +/* Error variable. Zero means no error. */ +int dt3155_errno = 0; + +#ifndef PCI_DEVICE_ID_INTEL_7116 +#define PCI_DEVICE_ID_INTEL_7116 0x1223 +#endif + +#define DT3155_VENDORID PCI_VENDOR_ID_INTEL +#define DT3155_DEVICEID PCI_DEVICE_ID_INTEL_7116 +#define MAXPCI 16 + +#ifdef DT_DEBUG +#define DT_3155_DEBUG_MSG(x,y) printk(x,y) +#else +#define DT_3155_DEBUG_MSG(x,y) +#endif + +/* wait queue for interrupts */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,1) +wait_queue_head_t dt3155_read_wait_queue[ MAXBOARDS ]; +#else +struct wait_queue *dt3155_read_wait_queue[ MAXBOARDS ]; +#endif + +#define DT_3155_SUCCESS 0 +#define DT_3155_FAILURE -EIO + +/* set to dynamicaly allocate, but it is tunable: */ +/* insmod DT_3155 dt3155 dt3155_major=XX */ +int dt3155_major = 0; + +/* The minor numbers are 0 and 1 ... they are not tunable. + * They are used as the indices for the structure vectors, + * and register address vectors + */ + +/* Global structures and variables */ + +/* Status of each device */ +struct dt3155_status_s dt3155_status[ MAXBOARDS ]; + +/* kernel logical address of the board */ +u_char *dt3155_lbase[ MAXBOARDS ] = { NULL +#if MAXBOARDS == 2 + , NULL +#endif +}; +/* DT3155 registers */ +u_char *dt3155_bbase = NULL; /* kernel logical address of the * + * buffer region */ +u_int dt3155_dev_open[ MAXBOARDS ] = {0 +#if MAXBOARDS == 2 + , 0 +#endif +}; + +u_int ndevices = 0; +u_long unique_tag = 0;; + + +/* + * Stops interrupt generation right away and resets the status + * to idle. I don't know why this works and the other way doesn't. + * (James Rose) + */ +static void quick_stop (int minor) +{ + // TODO: scott was here +#if 1 + ReadMReg((dt3155_lbase[ minor ] + INT_CSR), int_csr_r.reg); + /* disable interrupts */ + int_csr_r.fld.FLD_END_EVE_EN = 0; + int_csr_r.fld.FLD_END_ODD_EN = 0; + WriteMReg((dt3155_lbase[ minor ] + INT_CSR), int_csr_r.reg ); + + dt3155_status[ minor ].state &= ~(DT3155_STATE_STOP|0xff); + /* mark the system stopped: */ + dt3155_status[ minor ].state |= DT3155_STATE_IDLE; + dt3155_fbuffer[ minor ]->stop_acquire = 0; + dt3155_fbuffer[ minor ]->even_stopped = 0; +#else + dt3155_status[minor].state |= DT3155_STATE_STOP; + dt3155_status[minor].fbuffer.stop_acquire = 1; +#endif + +} + + +/***************************************************** + * dt3155_isr() Interrupt service routien + * + * - looks like this isr supports IRQ sharing (or could) JML + * - Assumes irq's are disabled, via SA_INTERRUPT flag + * being set in request_irq() call from init_module() + *****************************************************/ +static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) +{ + int minor = -1; + int index; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + unsigned long flags; +#else + int flags; +#endif + u_long buffer_addr; + + /* find out who issued the interrupt */ + for ( index = 0; index < ndevices; index++ ) { + if( dev_id == (void*) &dt3155_status[ index ]) + { + minor = index; + break; + } + } + + /* hopefully we should not get here */ + if ( minor < 0 || minor >= MAXBOARDS ) { + printk(KERN_ERR "dt3155_isr called with invalid dev_id\n"); + return; + } + + /* Check for corruption and set a flag if so */ + ReadMReg( (dt3155_lbase[ minor ] + CSR1), csr1_r.reg ); + + if ( (csr1_r.fld.FLD_CRPT_EVE) || (csr1_r.fld.FLD_CRPT_ODD) ) + { + /* TODO: this should probably stop acquisition */ + /* and set some flags so that dt3155_read */ + /* returns an error next time it is called */ + dt3155_errno = DT_ERR_CORRUPT; + printk("dt3155: corrupt field\n"); + return; + } + + ReadMReg((dt3155_lbase[ minor ] + INT_CSR), int_csr_r.reg); + + /* Handle the even field ... */ + if (int_csr_r.fld.FLD_END_EVE) + { + if ( (dt3155_status[ minor ].state & DT3155_STATE_MODE) == + DT3155_STATE_FLD ) + { + dt3155_fbuffer[ minor ]->frame_count++; + } + + ReadI2C(dt3155_lbase[ minor ], EVEN_CSR, &i2c_even_csr.reg); + + /* Clear the interrupt? */ + int_csr_r.fld.FLD_END_EVE = 1; + + /* disable the interrupt if last field */ + if (dt3155_fbuffer[ minor ]->stop_acquire) + { + printk("dt3155: even stopped.\n"); + dt3155_fbuffer[ minor ]->even_stopped = 1; + if (i2c_even_csr.fld.SNGL_EVE) + { + int_csr_r.fld.FLD_END_EVE_EN = 0; + } + else + { + i2c_even_csr.fld.SNGL_EVE = 1; + } + } + + WriteMReg( (dt3155_lbase[ minor ] + INT_CSR), int_csr_r.reg ); + + /* Set up next DMA if we are doing FIELDS */ + if ( (dt3155_status[ minor ].state & DT3155_STATE_MODE ) == + DT3155_STATE_FLD) + { + /* GCS (Aug 2, 2002) -- In field mode, dma the odd field + into the lower half of the buffer */ + const u_long stride = dt3155_status[ minor ].config.cols; + buffer_addr = dt3155_fbuffer[ minor ]-> + frame_info[ dt3155_fbuffer[ minor ]->active_buf ].addr + + (DT3155_MAX_ROWS / 2) * stride; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + local_save_flags(flags); + local_irq_disable(); +#else + save_flags( flags ); + cli(); +#endif + wake_up_interruptible( &dt3155_read_wait_queue[ minor ] ); + + /* Set up the DMA address for the next field */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + local_irq_restore(flags); +#else + restore_flags( flags ); +#endif + WriteMReg((dt3155_lbase[ minor ] + ODD_DMA_START), buffer_addr); + } + + /* Check for errors. */ + i2c_even_csr.fld.DONE_EVE = 1; + if ( i2c_even_csr.fld.ERROR_EVE ) + dt3155_errno = DT_ERR_OVERRUN; + + WriteI2C( dt3155_lbase[ minor ], EVEN_CSR, i2c_even_csr.reg ); + + /* Note that we actually saw an even field meaning */ + /* that subsequent odd field complete the frame */ + dt3155_fbuffer[ minor ]->even_happened = 1; + + /* recording the time that the even field finished, this should be */ + /* about time in the middle of the frame */ + do_gettimeofday( &(dt3155_fbuffer[ minor ]-> + frame_info[ dt3155_fbuffer[ minor ]-> + active_buf ].time) ); + return; + } + + /* ... now handle the odd field */ + if ( int_csr_r.fld.FLD_END_ODD ) + { + ReadI2C( dt3155_lbase[ minor ], ODD_CSR, &i2c_odd_csr.reg ); + + /* Clear the interrupt? */ + int_csr_r.fld.FLD_END_ODD = 1; + + if (dt3155_fbuffer[ minor ]->even_happened || + (dt3155_status[ minor ].state & DT3155_STATE_MODE) == + DT3155_STATE_FLD) + { + dt3155_fbuffer[ minor ]->frame_count++; + } + + if ( dt3155_fbuffer[ minor ]->stop_acquire && + dt3155_fbuffer[ minor ]->even_stopped ) + { + printk(KERN_DEBUG "dt3155: stopping odd..\n"); + if ( i2c_odd_csr.fld.SNGL_ODD ) + { + /* disable interrupts */ + int_csr_r.fld.FLD_END_ODD_EN = 0; + dt3155_status[ minor ].state &= ~(DT3155_STATE_STOP|0xff); + + /* mark the system stopped: */ + dt3155_status[ minor ].state |= DT3155_STATE_IDLE; + dt3155_fbuffer[ minor ]->stop_acquire = 0; + dt3155_fbuffer[ minor ]->even_stopped = 0; + + printk(KERN_DEBUG "dt3155: state is now %lx\n", + dt3155_status[minor].state); + } + else + { + i2c_odd_csr.fld.SNGL_ODD = 1; + } + } + + WriteMReg( (dt3155_lbase[ minor ] + INT_CSR), int_csr_r.reg ); + + /* if the odd field has been acquired, then */ + /* change the next dma location for both fields */ + /* and wake up the process if sleeping */ + if ( dt3155_fbuffer[ minor ]->even_happened || + (dt3155_status[ minor ].state & DT3155_STATE_MODE) == + DT3155_STATE_FLD ) + { + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + local_save_flags(flags); + local_irq_disable(); +#else + save_flags( flags ); + cli(); +#endif + +#ifdef DEBUG_QUES_B + printques( minor ); +#endif + if ( dt3155_fbuffer[ minor ]->nbuffers > 2 ) + { + if ( !are_empty_buffers( minor ) ) + { + /* The number of active + locked buffers is + * at most 2, and since there are none empty, there + * must be at least nbuffers-2 ready buffers. + * This is where we 'drop frames', oldest first. */ + push_empty( pop_ready( minor ), minor ); + } + + /* The ready_que can't be full, since we know + * there is one active buffer right now, so it's safe + * to push the active buf on the ready_que. */ + push_ready( minor, dt3155_fbuffer[ minor ]->active_buf ); + /* There's at least 1 empty -- make it active */ + dt3155_fbuffer[ minor ]->active_buf = pop_empty( minor ); + dt3155_fbuffer[ minor ]-> + frame_info[ dt3155_fbuffer[ minor ]-> + active_buf ].tag = ++unique_tag; + } + else /* nbuffers == 2, special case */ + { /* There is 1 active buffer. + * If there is a locked buffer, keep the active buffer + * the same -- that means we drop a frame. + */ + if ( dt3155_fbuffer[ minor ]->locked_buf < 0 ) + { + push_ready( minor, + dt3155_fbuffer[ minor ]->active_buf ); + if (are_empty_buffers( minor ) ) + { + dt3155_fbuffer[ minor ]->active_buf = + pop_empty( minor ); + } + else + { /* no empty or locked buffers, so use a readybuf */ + dt3155_fbuffer[ minor ]->active_buf = + pop_ready( minor ); + } + } + } + +#ifdef DEBUG_QUES_B + printques( minor ); +#endif + + dt3155_fbuffer[ minor ]->even_happened = 0; + + wake_up_interruptible( &dt3155_read_wait_queue[ minor ] ); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + local_irq_restore(flags); +#else + restore_flags( flags ); +#endif + } + + + /* Set up the DMA address for the next frame/field */ + buffer_addr = dt3155_fbuffer[ minor ]-> + frame_info[ dt3155_fbuffer[ minor ]->active_buf ].addr; + if ( (dt3155_status[ minor ].state & DT3155_STATE_MODE) == + DT3155_STATE_FLD ) + { + WriteMReg((dt3155_lbase[ minor ] + EVEN_DMA_START), buffer_addr); + } + else + { + WriteMReg((dt3155_lbase[ minor ] + EVEN_DMA_START), buffer_addr); + + WriteMReg((dt3155_lbase[ minor ] + ODD_DMA_START), buffer_addr + + dt3155_status[ minor ].config.cols); + } + + /* Do error checking */ + i2c_odd_csr.fld.DONE_ODD = 1; + if ( i2c_odd_csr.fld.ERROR_ODD ) + dt3155_errno = DT_ERR_OVERRUN; + + WriteI2C(dt3155_lbase[ minor ], ODD_CSR, i2c_odd_csr.reg ); + + return; + } + /* If we get here, the Odd Field wasn't it either... */ + printk( "neither even nor odd. shared perhaps?\n"); +} + +/***************************************************** + * init_isr(int minor) + * turns on interupt generation for the card + * designated by "minor". + * It is called *only* from inside ioctl(). + *****************************************************/ +static void dt3155_init_isr(int minor) +{ + const u_long stride = dt3155_status[ minor ].config.cols; + + switch (dt3155_status[ minor ].state & DT3155_STATE_MODE) + { + case DT3155_STATE_FLD: + { + even_dma_start_r = dt3155_status[ minor ]. + fbuffer.frame_info[ dt3155_status[ minor ].fbuffer.active_buf ].addr; + even_dma_stride_r = 0; + odd_dma_stride_r = 0; + + WriteMReg((dt3155_lbase[ minor ] + EVEN_DMA_START), + even_dma_start_r); + WriteMReg((dt3155_lbase[ minor ] + EVEN_DMA_STRIDE), + even_dma_stride_r); + WriteMReg((dt3155_lbase[ minor ] + ODD_DMA_STRIDE), + odd_dma_stride_r); + break; + } + + case DT3155_STATE_FRAME: + default: + { + even_dma_start_r = dt3155_status[ minor ]. + fbuffer.frame_info[ dt3155_status[ minor ].fbuffer.active_buf ].addr; + odd_dma_start_r = even_dma_start_r + stride; + even_dma_stride_r = stride; + odd_dma_stride_r = stride; + + WriteMReg((dt3155_lbase[ minor ] + EVEN_DMA_START), + even_dma_start_r); + WriteMReg((dt3155_lbase[ minor ] + ODD_DMA_START), + odd_dma_start_r); + WriteMReg((dt3155_lbase[ minor ] + EVEN_DMA_STRIDE), + even_dma_stride_r); + WriteMReg((dt3155_lbase[ minor ] + ODD_DMA_STRIDE), + odd_dma_stride_r); + break; + } + } + + /* 50/60 Hz should be set before this point but let's make sure it is */ + /* right anyway */ + + ReadI2C(dt3155_lbase[ minor ], CONFIG, &i2c_csr2.reg); + i2c_csr2.fld.HZ50 = FORMAT50HZ; + WriteI2C(dt3155_lbase[ minor ], CONFIG, i2c_config.reg); + + /* enable busmaster chip, clear flags */ + + /* + * TODO: + * shouldn't we be concered with continuous values of + * DT3155_SNAP & DT3155_ACQ here? (SS) + */ + + csr1_r.reg = 0; + csr1_r.fld.CAP_CONT_EVE = 1; /* use continuous capture bits to */ + csr1_r.fld.CAP_CONT_ODD = 1; /* enable */ + csr1_r.fld.FLD_DN_EVE = 1; /* writing a 1 clears flags */ + csr1_r.fld.FLD_DN_ODD = 1; + csr1_r.fld.SRST = 1; /* reset - must be 1 */ + csr1_r.fld.FIFO_EN = 1; /* fifo control - must be 1 */ + csr1_r.fld.FLD_CRPT_EVE = 1; /* writing a 1 clears flags */ + csr1_r.fld.FLD_CRPT_ODD = 1; + + WriteMReg((dt3155_lbase[ minor ] + CSR1),csr1_r.reg); + + /* Enable interrupts at the end of each field */ + + int_csr_r.reg = 0; + int_csr_r.fld.FLD_END_EVE_EN = 1; + int_csr_r.fld.FLD_END_ODD_EN = 1; + int_csr_r.fld.FLD_START_EN = 0; + + WriteMReg((dt3155_lbase[ minor ] + INT_CSR), int_csr_r.reg); + + /* start internal BUSY bits */ + + ReadI2C(dt3155_lbase[ minor ], CSR2, &i2c_csr2.reg); + i2c_csr2.fld.BUSY_ODD = 1; + i2c_csr2.fld.BUSY_EVE = 1; + WriteI2C(dt3155_lbase[ minor ], CSR2, i2c_csr2.reg); + + /* Now its up to the interrupt routine!! */ + + return; +} + + +/***************************************************** + * ioctl() + * + *****************************************************/ +static int dt3155_ioctl ( + struct inode *inode, + struct file *file, + u_int cmd, + u_long arg) +{ + int minor = MINOR(inode->i_rdev); /* What device are we ioctl()'ing? */ + + if ( minor >= MAXBOARDS || minor < 0 ) + return -ENODEV; + + /* make sure it is valid command */ + if (_IOC_NR(cmd) > DT3155_IOC_MAXNR) + { + printk("DT3155: invalid IOCTL(0x%x)\n",cmd); + printk("DT3155: Valid commands (0x%x), (0x%x), (0x%x), (0x%x), (0x%x)\n", + DT3155_GET_CONFIG, DT3155_SET_CONFIG, + DT3155_START, DT3155_STOP, DT3155_FLUSH); + return -EINVAL; + } + + switch (cmd) + { + case DT3155_SET_CONFIG: + { + if (dt3155_status[minor].state != DT3155_STATE_IDLE) + return -EBUSY; + + { + struct dt3155_config_s tmp; + if (copy_from_user((void *)&tmp, (void *) arg, sizeof(tmp))) + return -EFAULT; + /* check for valid settings */ + if (tmp.rows > DT3155_MAX_ROWS || + tmp.cols > DT3155_MAX_COLS || + (tmp.acq_mode != DT3155_MODE_FRAME && + tmp.acq_mode != DT3155_MODE_FIELD) || + (tmp.continuous != DT3155_SNAP && + tmp.continuous != DT3155_ACQ)) + { + return -EINVAL; + } + dt3155_status[minor].config = tmp; + } + return 0; + } + case DT3155_GET_CONFIG: + { + if (copy_to_user((void *) arg, (void *) &dt3155_status[minor], + sizeof(dt3155_status_t) )) + return -EFAULT; + return 0; + } + case DT3155_FLUSH: /* Flushes the buffers -- ensures fresh data */ + { + if (dt3155_status[minor].state != DT3155_STATE_IDLE) + return -EBUSY; + return dt3155_flush(minor); + } + case DT3155_STOP: + { + if (dt3155_status[minor].state & DT3155_STATE_STOP || + dt3155_status[minor].fbuffer.stop_acquire) + return -EBUSY; + + if (dt3155_status[minor].state == DT3155_STATE_IDLE) + return 0; + + quick_stop(minor); + if (copy_to_user((void *) arg, (void *) &dt3155_status[minor], + sizeof(dt3155_status_t))) + return -EFAULT; + return 0; + } + case DT3155_START: + { + if (dt3155_status[minor].state != DT3155_STATE_IDLE) + return -EBUSY; + + dt3155_status[minor].fbuffer.stop_acquire = 0; + dt3155_status[minor].fbuffer.frame_count = 0; + + /* Set the MODE in the status -- we default to FRAME */ + if (dt3155_status[minor].config.acq_mode == DT3155_MODE_FIELD) + { + dt3155_status[minor].state = DT3155_STATE_FLD; + } + else + { + dt3155_status[minor].state = DT3155_STATE_FRAME; + } + + dt3155_init_isr(minor); + if (copy_to_user( (void *) arg, (void *) &dt3155_status[minor], + sizeof(dt3155_status_t))) + return -EFAULT; + return 0; + } + default: + { + printk("DT3155: invalid IOCTL(0x%x)\n",cmd); + printk("DT3155: Valid commands (0x%x), (0x%x), (0x%x), (0x%x), (0x%x)\n", + DT3155_GET_CONFIG, DT3155_SET_CONFIG, + DT3155_START, DT3155_STOP, DT3155_FLUSH); + return -ENOSYS; + } + } + return -ENOSYS; +} + +/***************************************************** + * mmap() + * + * only allow the user to mmap the registers and buffer + * It is quite possible that this is broken, since the + * addition of of the capacity for two cards!!!!!!!! + * It *looks* like it should work but since I'm not + * sure how to use it, I'm not actually sure. (NJC? ditto by SS) + *****************************************************/ +static int dt3155_mmap (struct file * file, struct vm_area_struct * vma) +{ + /* which device are we mmapping? */ + int minor = MINOR(file->f_dentry->d_inode->i_rdev); + unsigned long offset; + + /* not actually sure when vm_area_struct changed, + but it was in 2.3 sometime */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,20) + + offset = vma->vm_pgoff << PAGE_SHIFT; + + if (offset >= __pa(high_memory) || (file->f_flags & O_SYNC)) + vma->vm_flags |= VM_IO; + + /* Don't try to swap out physical pages.. */ + vma->vm_flags |= VM_RESERVED; + +#else + + if (vma->vm_offset & ~PAGE_MASK) + return -ENXIO; + + offset = vma->vm_offset; + +#endif + + /* they are mapping the registers or the buffer */ + if ((offset == dt3155_status[minor].reg_addr && + vma->vm_end - vma->vm_start == PCI_PAGE_SIZE) || + (offset == dt3155_status[minor].mem_addr && + vma->vm_end - vma->vm_start == dt3155_status[minor].mem_size)) + { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + if (remap_pfn_range(vma, + vma->vm_start, + offset >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) +#else + if (remap_page_range(vma->vm_start, + offset, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) +#endif + { + printk("DT3155: remap_page_range() failed.\n"); + return -EAGAIN; + } + } + else + { + printk("DT3155: dt3155_mmap() bad call.\n"); + return -ENXIO; + } + + return 0; +} + + +/***************************************************** + * open() + * + * Our special open code. + * MOD_INC_USE_COUNT make sure that the driver memory is not freed + * while the device is in use. + *****************************************************/ +static int dt3155_open( struct inode* inode, struct file* filep) +{ + int minor = MINOR(inode->i_rdev); /* what device are we opening? */ + if (dt3155_dev_open[ minor ]) { + printk ("DT3155: Already opened by another process.\n"); + return -EBUSY; + } + + if (dt3155_status[ minor ].device_installed==0) + { + printk("DT3155 Open Error: No such device dt3155 minor number %d\n", + minor); + return -EIO; + } + + if (dt3155_status[ minor ].state != DT3155_STATE_IDLE) { + printk ("DT3155: Not in idle state (state = %lx)\n", + dt3155_status[ minor ].state); + return -EBUSY; + } + + printk("DT3155: Device opened.\n"); + + dt3155_dev_open[ minor ] = 1 ; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + MOD_INC_USE_COUNT; +#endif + + dt3155_flush( minor ); + + /* Disable ALL interrupts */ + int_csr_r.reg = 0; + WriteMReg( (dt3155_lbase[ minor ] + INT_CSR), int_csr_r.reg ); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,1) + init_waitqueue_head(&(dt3155_read_wait_queue[minor])); +#else + dt3155_read_wait_queue[minor] = NULL; +#endif + + return 0; +} + + +/***************************************************** + * close() + * + * Now decrement the use count. + * + *****************************************************/ +static int dt3155_close( struct inode *inode, struct file *filep) +{ + int minor; + + minor = MINOR(inode->i_rdev); /* which device are we closing */ + if (!dt3155_dev_open[ minor ]) + { + printk("DT3155: attempt to CLOSE a not OPEN device\n"); + } + else + { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + MOD_DEC_USE_COUNT; +#endif + dt3155_dev_open[ minor ] = 0; + + if (dt3155_status[ minor ].state != DT3155_STATE_IDLE) + { + quick_stop(minor); + } + } + return 0; +} + +/***************************************************** + * read() + * + *****************************************************/ +static int dt3155_read ( + struct file *filep, + char *buf, + size_t count, + loff_t *ppos) +{ + /* which device are we reading from? */ + int minor = MINOR(filep->f_dentry->d_inode->i_rdev); + u_long offset; + int frame_index; + frame_info_t *frame_info_p; + + /* TODO: this should check the error flag and */ + /* return an error on hardware failures */ + if (count != sizeof(dt3155_read_t)) + { + printk("DT3155 ERROR (NJC): count is not right\n"); + return -EINVAL; + } + + + /* Hack here -- I'm going to allow reading even when idle. + * this is so that the frames can be read after STOP has + * been called. Leaving it here, commented out, as a reminder + * for a short while to make sure there are no problems. + * Note that if the driver is not opened in non_blocking mode, + * and the device is idle, then it could sit here forever! */ + + /* if (dt3155_status[minor].state == DT3155_STATE_IDLE)*/ + /* return -EBUSY;*/ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,1) + + /* non-blocking reads should return if no data */ + if (filep->f_flags & O_NDELAY) + { + if ((frame_index = dt3155_get_ready_buffer(minor)) < 0) { + /*printk( "dt3155: no buffers available (?)\n");*/ + /* printques(minor); */ + return -EAGAIN; + } + } + else + { + /* + * sleep till data arrives , or we get interrupted. + * Note that wait_event_interruptible() does not actually + * sleep/wait if it's condition evaluates to true upon entry. + */ + wait_event_interruptible(dt3155_read_wait_queue[minor], + (frame_index = dt3155_get_ready_buffer(minor)) + >= 0); + + if (frame_index < 0) + { + printk ("DT3155: read: interrupted\n"); + quick_stop (minor); + printques(minor); + return -EINTR; + } + } + +#else + while ((frame_index = dt3155_get_ready_buffer(minor)) < 0 ) + { + int index; + if (filep->f_flags & O_NDELAY) + return 0; + + /* sleep till data arrives , or we get interrupted */ + interruptible_sleep_on(&dt3155_read_wait_queue[minor]); + for (index = 0; index < _NSIG_WORDS; index++) + { + /* + * Changing the next line of code below to this: + * if (current->pending.signal.sig[index] & + * ~current->blocked.sig[index]) + * would also work on a 2.4 kernel, however, the above + * method is preferred & more portable. + */ + if (current->signal.sig[index] & ~current->blocked.sig[index]) + { + printk ("DT3155: read: interrupted\n"); + return -EINTR; + } + } + } + +#endif + + frame_info_p = &dt3155_status[minor].fbuffer.frame_info[frame_index]; + + /* make this an offset */ + offset = frame_info_p->addr - dt3155_status[minor].mem_addr; + + put_user(offset, (unsigned int *) buf); + buf += sizeof(u_long); + put_user( dt3155_status[minor].fbuffer.frame_count, (unsigned int *) buf); + buf += sizeof(u_long); + put_user(dt3155_status[minor].state, (unsigned int *) buf); + buf += sizeof(u_long); + if (copy_to_user(buf, frame_info_p, sizeof(frame_info_t))) + return -EFAULT; + + return sizeof(dt3155_read_t); +} + +static unsigned int dt3155_poll (struct file * filp, poll_table *wait) +{ + int minor = MINOR(filp->f_dentry->d_inode->i_rdev); + + if (!is_ready_buf_empty(minor)) + return POLLIN | POLLRDNORM; + + poll_wait (filp, &dt3155_read_wait_queue[minor], wait); + + return 0; +} + + +/***************************************************** + * file operations supported by DT3155 driver + * needed by init_module + * register_chrdev + *****************************************************/ +static struct file_operations dt3155_fops = { + read: dt3155_read, + ioctl: dt3155_ioctl, + mmap: dt3155_mmap, + poll: dt3155_poll, + open: dt3155_open, + release: dt3155_close +}; + + +/***************************************************** + * find_PCI(); + * + * PCI has been totally reworked in 2.1.. + *****************************************************/ +static int find_PCI (void) +{ + struct pci_dev *pci_dev = NULL; + int error, pci_index = 0; + unsigned short rev_device; + unsigned long base; + unsigned char irq; + + while ((pci_dev = pci_find_device + (DT3155_VENDORID, DT3155_DEVICEID, pci_dev)) != NULL) + { + pci_index ++; + + /* Is it really there? */ + if ((error = + pci_read_config_word(pci_dev, PCI_CLASS_DEVICE, &rev_device))) + continue; + + /* Found a board */ + DT_3155_DEBUG_MSG("DT3155: Device number %d \n", pci_index); + + /* Make sure the driver was compiled with enough buffers to handle + this many boards */ + if (pci_index > MAXBOARDS) { + printk("DT3155: ERROR - found %d devices, but driver only configured " + "for %d devices\n" + "DT3155: Please change MAXBOARDS in dt3155.h\n", + pci_index, MAXBOARDS); + return DT_3155_FAILURE; + } + + /* Now, just go out and make sure that this/these device(s) is/are + actually mapped into the kernel address space */ + if ((error = pci_read_config_dword( pci_dev, PCI_BASE_ADDRESS_0, + (u_int *) &base))) + { + printk("DT3155: Was not able to find device \n"); + return DT_3155_FAILURE; + } + + DT_3155_DEBUG_MSG("DT3155: Base address 0 for device is %lx \n", base); + dt3155_status[pci_index-1].reg_addr = base; + + /* Remap the base address to a logical address through which we + * can access it. */ + dt3155_lbase[ pci_index - 1 ] = ioremap(base,PCI_PAGE_SIZE); + dt3155_status[ pci_index - 1 ].reg_addr = base; + DT_3155_DEBUG_MSG("DT3155: New logical address is x%x \n", + (u_int)dt3155_lbase[pci_index-1]); + if ( !dt3155_lbase[pci_index-1] ) + { + printk("DT3155: Unable to remap control registers\n"); + return DT_3155_FAILURE; + } + + if ( (error = pci_read_config_byte( pci_dev, PCI_INTERRUPT_LINE, &irq)) ) + { + printk("DT3155: Was not able to find device \n"); + return DT_3155_FAILURE; + } + + DT_3155_DEBUG_MSG("DT3155: IRQ is %d \n",irq); + dt3155_status[ pci_index-1 ].irq = irq; + /* Set flag: kth device found! */ + dt3155_status[ pci_index-1 ].device_installed = 1; + printk("DT3155: Installing device %d w/irq %d and address 0x%x\n", + pci_index, + (u_int)dt3155_status[pci_index-1].irq, + (u_int)dt3155_lbase[pci_index-1]); + + } + ndevices = pci_index; + + return DT_3155_SUCCESS; +} + +u_long allocatorAddr = 0; + +/***************************************************** + * init_module() + *****************************************************/ +int init_module(void) +{ + int index; + int rcode = 0; + char *devname[ MAXBOARDS ]; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,1) +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + SET_MODULE_OWNER(&dt3155_fops); +#endif +#endif + + devname[ 0 ] = "dt3155a"; +#if MAXBOARDS == 2 + devname[ 1 ] = "dt3155b"; +#endif + + printk("DT3155: Loading module...\n"); + + /* Register the device driver */ + rcode = register_chrdev( dt3155_major, "dt3155", &dt3155_fops ); + if( rcode < 0 ) + { + printk( KERN_INFO "DT3155: register_chrdev failed \n"); + return rcode; + } + + if( dt3155_major == 0 ) + dt3155_major = rcode; /* dynamic */ + + + /* init the status variables. */ + /* DMA memory is taken care of in setup_buffers() */ + for ( index = 0; index < MAXBOARDS; index++ ) + { + dt3155_status[ index ].config.acq_mode = DT3155_MODE_FRAME; + dt3155_status[ index ].config.continuous = DT3155_ACQ; + dt3155_status[ index ].config.cols = DT3155_MAX_COLS; + dt3155_status[ index ].config.rows = DT3155_MAX_ROWS; + dt3155_status[ index ].state = DT3155_STATE_IDLE; + + /* find_PCI() will check if devices are installed; */ + /* first assume they're not: */ + dt3155_status[ index ].mem_addr = 0; + dt3155_status[ index ].mem_size = 0; + dt3155_status[ index ].state = DT3155_STATE_IDLE; + dt3155_status[ index ].device_installed = 0; + } + + /* Now let's find the hardware. find_PCI() will set ndevices to the + * number of cards found in this machine. */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + if ( !(pcibios_present()) ) + { + printk("DT3155: Error: No PCI bios on this machine \n"); + if( unregister_chrdev( dt3155_major, "dt3155" ) != 0 ) + printk("DT3155: cleanup_module failed\n"); + + return DT_3155_FAILURE; + } + else +#endif + { + if ( (rcode = find_PCI()) != DT_3155_SUCCESS ) + { + printk("DT3155 error: find_PCI() failed to find dt3155 board(s)\n"); + unregister_chrdev( dt3155_major, "dt3155" ); + return rcode; + } + } + + /* Ok, time to setup the frame buffers */ + if( (rcode = dt3155_setup_buffers(&allocatorAddr)) < 0 ) + { + printk("DT3155: Error: setting up buffer not large enough."); + unregister_chrdev( dt3155_major, "dt3155" ); + return rcode; + } + + /* If we are this far, then there is enough RAM */ + /* for the buffers: Print the configuration. */ + for( index = 0; index < ndevices; index++ ) + { + printk("DT3155: Device = %d; acq_mode = %d; " + "continuous = %d; cols = %d; rows = %d;\n", + index , + dt3155_status[ index ].config.acq_mode, + dt3155_status[ index ].config.continuous, + dt3155_status[ index ].config.cols, + dt3155_status[ index ].config.rows); + printk("DT3155: m_addr = 0x%x; m_size = %ld; " + "state = %ld; device_installed = %d\n", + (u_int)dt3155_status[ index ].mem_addr, + dt3155_status[ index ].mem_size, + dt3155_status[ index ].state, + dt3155_status[ index ].device_installed); + } + + /* Disable ALL interrupts */ + int_csr_r.reg = 0; + for( index = 0; index < ndevices; index++ ) + { + WriteMReg( (dt3155_lbase[ index ] + INT_CSR), int_csr_r.reg ); + if( dt3155_status[ index ].device_installed ) + { + /* + * This driver *looks* like it can handle sharing interrupts, + * but I can't actually test myself. I've had reports that it + * DOES work so I'll enable it for now. This comment will remain + * as a reminder in case any problems arise. (SS) + */ + /* in older kernels flags are: SA_SHIRQ | SA_INTERRUPT */ + rcode = request_irq( dt3155_status[ index ].irq, (void *)dt3155_isr, + IRQF_SHARED | IRQF_DISABLED, devname[ index ], + (void*) &dt3155_status[index]); + if( rcode < 0 ) + { + printk("DT3155: minor %d request_irq failed for IRQ %d\n", + index, dt3155_status[index].irq); + unregister_chrdev( dt3155_major, "dt3155" ); + return rcode; + } + } + } + + printk("DT3155: finished loading\n"); + + return 0; +} + +/***************************************************** + * cleanup_module(void) + * + *****************************************************/ +void cleanup_module(void) +{ + int index; + + printk("DT3155: cleanup_module called\n"); + + /* removed DMA allocated with the allocator */ +#ifdef STANDALONE_ALLOCATOR + if (allocatorAddr != 0) + allocator_free_dma(allocatorAddr); +#else + allocator_cleanup(); +#endif + + unregister_chrdev( dt3155_major, "dt3155" ); + + for( index = 0; index < ndevices; index++ ) + { + if( dt3155_status[ index ].device_installed == 1 ) + { + printk( "DT3155: Freeing irq %d for device %d\n", + dt3155_status[ index ].irq, index ); + free_irq( dt3155_status[ index ].irq, (void*)&dt3155_status[index] ); + } + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + if (MOD_IN_USE) + printk("DT3155: device busy, remove delayed\n"); +#endif +} + diff --git a/drivers/staging/dt3155/dt3155_drv.h b/drivers/staging/dt3155/dt3155_drv.h new file mode 100644 index 000000000000..92a92dc2736c --- /dev/null +++ b/drivers/staging/dt3155/dt3155_drv.h @@ -0,0 +1,50 @@ +/* + +Copyright 1996,2002 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, + Scott Smedley + +This file is part of the DT3155 Device Driver. + +The DT3155 Device Driver is free software; you can redistribute it +and/or modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2 of the +License, or (at your option) any later version. + +The DT3155 Device Driver is distributed in the hope that it will be +useful, but WITHOUT ANY WARRANTY; without even the implied warranty +of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with the DT3155 Device Driver; if not, write to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, +MA 02111-1307 USA +*/ + +#ifndef DT3155_DRV_INC +#define DT3155_DRV_INC + +/* kernel logical address of the frame grabbers */ +extern u_char *dt3155_lbase[ MAXBOARDS ]; + +/* kernel logical address of ram buffer */ +extern u_char *dt3155_bbase; + +#ifdef __KERNEL__ +#include + +#include /* need access to LINUX_VERSION_CODE */ +/* wait queue for reads */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,1) +extern wait_queue_head_t dt3155_read_wait_queue[MAXBOARDS]; +#else +extern struct wait_queue *dt3155_read_wait_queue[MAXBOARDS]; +#endif +#endif + +/* number of devices */ +extern u_int ndevices; + +extern int dt3155_errno; + +#endif diff --git a/drivers/staging/dt3155/dt3155_io.c b/drivers/staging/dt3155/dt3155_io.c new file mode 100644 index 000000000000..6d516863d1ae --- /dev/null +++ b/drivers/staging/dt3155/dt3155_io.c @@ -0,0 +1,236 @@ +/* + +Copyright 1996,2002,2005 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, + Jason Lapenta, Scott Smedley + +This file is part of the DT3155 Device Driver. + +The DT3155 Device Driver is free software; you can redistribute it +and/or modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2 of the +License, or (at your option) any later version. + +The DT3155 Device Driver is distributed in the hope that it will be +useful, but WITHOUT ANY WARRANTY; without even the implied warranty +of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with the DT3155 Device Driver; if not, write to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, +MA 02111-1307 USA + + +-- Changes -- + + Date Programmer Description of changes made + ------------------------------------------------------------------- + 10-Oct-2001 SS port to 2.4 kernel. + 24-Jul-2002 SS GPL licence. + 26-Jul-2002 SS Bug fix: timing logic was wrong. + 08-Aug-2005 SS port to 2.6 kernel. + +*/ + +/* This file provides some basic register io routines. It is modified + from demo code provided by Data Translations. */ + +#ifdef __KERNEL__ +#include +#endif + +#if 0 +#include +#include +#include +#endif + +#include "dt3155.h" +#include "dt3155_io.h" +#include "dt3155_drv.h" + +#ifndef __KERNEL__ +#include +#endif + + +/****** local copies of board's 32 bit registers ******/ +u_long even_dma_start_r; /* bit 0 should always be 0 */ +u_long odd_dma_start_r; /* .. */ +u_long even_dma_stride_r; /* bits 0&1 should always be 0 */ +u_long odd_dma_stride_r; /* .. */ +u_long even_pixel_fmt_r; +u_long odd_pixel_fmt_r; + +FIFO_TRIGGER_R fifo_trigger_r; +XFER_MODE_R xfer_mode_r; +CSR1_R csr1_r; +RETRY_WAIT_CNT_R retry_wait_cnt_r; +INT_CSR_R int_csr_r; + +u_long even_fld_mask_r; +u_long odd_fld_mask_r; + +MASK_LENGTH_R mask_length_r; +FIFO_FLAG_CNT_R fifo_flag_cnt_r; +IIC_CLK_DUR_R iic_clk_dur_r; +IIC_CSR1_R iic_csr1_r; +IIC_CSR2_R iic_csr2_r; +DMA_UPPER_LMT_R even_dma_upper_lmt_r; +DMA_UPPER_LMT_R odd_dma_upper_lmt_r; + + + +/******** local copies of board's 8 bit I2C registers ******/ +I2C_CSR2 i2c_csr2; +I2C_EVEN_CSR i2c_even_csr; +I2C_ODD_CSR i2c_odd_csr; +I2C_CONFIG i2c_config; +u_char i2c_dt_id; +u_char i2c_x_clip_start; +u_char i2c_y_clip_start; +u_char i2c_x_clip_end; +u_char i2c_y_clip_end; +u_char i2c_ad_addr; +u_char i2c_ad_lut; +I2C_AD_CMD i2c_ad_cmd; +u_char i2c_dig_out; +u_char i2c_pm_lut_addr; +u_char i2c_pm_lut_data; + + +// return the time difference (in microseconds) b/w & . +long elapsed2 (const struct timeval *pStart, const struct timeval *pEnd) +{ + long i = (pEnd->tv_sec - pStart->tv_sec) * 1000000; + i += pEnd->tv_usec - pStart->tv_usec; + return i; +} + +/*********************************************************************** + wait_ibsyclr() + + This function handles read/write timing and r/w timeout error + + Returns TRUE if NEW_CYCLE clears + Returns FALSE if NEW_CYCLE doesn't clear in roughly 3 msecs, + otherwise returns 0 + +***********************************************************************/ +int wait_ibsyclr(u_char * lpReg) +{ + /* wait 100 microseconds */ + +#ifdef __KERNEL__ + udelay(100L); + /* __delay(loops_per_sec/10000); */ + if (iic_csr2_r.fld.NEW_CYCLE ) + { /* if NEW_CYCLE didn't clear */ + /* TIMEOUT ERROR */ + dt3155_errno = DT_ERR_I2C_TIMEOUT; + return FALSE; + } + else + return TRUE; /* no error */ +#else + struct timeval StartTime; + struct timeval EndTime; + + const int to_3ms = 3000; /* time out of 3ms = 3000us */ + + gettimeofday( &StartTime, NULL ); + do { + /* get new iic_csr2 value: */ + ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); + gettimeofday( &EndTime, NULL ); + } + while ((elapsed2(&StartTime, &EndTime) < to_3ms) && iic_csr2_r.fld.NEW_CYCLE); + + if (iic_csr2_r.fld.NEW_CYCLE ) + { /* if NEW_CYCLE didn't clear */ + printf("Timed out waiting for NEW_CYCLE to clear!"); + return FALSE; + } + else + return TRUE; /* no error */ +#endif +} + +/*********************************************************************** + WriteI2C() + + This function handles writing to 8-bit DT3155 registers + + 1st parameter is pointer to 32-bit register base address + 2nd parameter is reg. index; + 3rd is value to be written + + Returns TRUE - Successful completion + FALSE - Timeout error - cycle did not complete! +***********************************************************************/ +int WriteI2C (u_char * lpReg, u_short wIregIndex, u_char byVal) +{ + int writestat; /* status for return */ + + /* read 32 bit IIC_CSR2 register data into union */ + + ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); + + iic_csr2_r.fld.DIR_RD = 0; /* for write operation */ + iic_csr2_r.fld.DIR_ADDR = wIregIndex; /* I2C address of I2C register: */ + iic_csr2_r.fld.DIR_WR_DATA = byVal; /* 8 bit data to be written to I2C reg */ + iic_csr2_r.fld.NEW_CYCLE = 1; /* will start a direct I2C cycle: */ + + /* xfer union data into 32 bit IIC_CSR2 register */ + + WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); + + /* wait for IIC cycle to finish */ + + writestat = wait_ibsyclr( lpReg ); + return writestat; /* return with status */ +} + +/*********************************************************************** + ReadI2C() + + This function handles reading from 8-bit DT3155 registers + + 1st parameter is pointer to 32-bit register base address + 2nd parameter is reg. index; + 3rd is adrs of value to be read + + Returns TRUE - Successful completion + FALSE - Timeout error - cycle did not complete! +***********************************************************************/ +int ReadI2C (u_char * lpReg, u_short wIregIndex, u_char * byVal) +{ + int writestat; /* status for return */ + + /* read 32 bit IIC_CSR2 register data into union */ + ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); + + /* for read operation */ + iic_csr2_r.fld.DIR_RD = 1; + + /* I2C address of I2C register: */ + iic_csr2_r.fld.DIR_ADDR = wIregIndex; + + /* will start a direct I2C cycle: */ + iic_csr2_r.fld.NEW_CYCLE = 1; + + /* xfer union's data into 32 bit IIC_CSR2 register */ + WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); + + /* wait for IIC cycle to finish */ + writestat = wait_ibsyclr(lpReg); + + /* Next 2 commands read 32 bit IIC_CSR1 register's data into union */ + /* first read data is in IIC_CSR1 */ + ReadMReg((lpReg + IIC_CSR1), iic_csr1_r.reg); + + /* now get data u_char out of register */ + *byVal = (u_char) iic_csr1_r.fld.RD_DATA; + + return writestat; /* return with status */ +} diff --git a/drivers/staging/dt3155/dt3155_io.h b/drivers/staging/dt3155/dt3155_io.h new file mode 100644 index 000000000000..c1174ab7eac5 --- /dev/null +++ b/drivers/staging/dt3155/dt3155_io.h @@ -0,0 +1,400 @@ +/* + +Copyright 1996,2002 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, + Jason Lapenta, Scott Smedley + +This file is part of the DT3155 Device Driver. + +The DT3155 Device Driver is free software; you can redistribute it +and/or modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2 of the +License, or (at your option) any later version. + +The DT3155 Device Driver is distributed in the hope that it will be +useful, but WITHOUT ANY WARRANTY; without even the implied warranty +of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with the DT3155 Device Driver; if not, write to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, +MA 02111-1307 USA + + +-- Changes -- + + Date Programmer Description of changes made + ------------------------------------------------------------------- + 24-Jul-2002 SS GPL licence. + +*/ + +/* This code is a modified version of examples provided by Data Translations.*/ + +#ifndef DT3155_IO_INC +#define DT3155_IO_INC + +/* macros to access registers */ + +#define WriteMReg(Address, Data) * ((u_long *) (Address)) = Data +#define ReadMReg(Address, Data) Data = * ((u_long *) (Address)) + +/***************** 32 bit register globals **************/ + +/* offsets for 32-bit memory mapped registers */ + +#define EVEN_DMA_START 0x000 +#define ODD_DMA_START 0x00C +#define EVEN_DMA_STRIDE 0x018 +#define ODD_DMA_STRIDE 0x024 +#define EVEN_PIXEL_FMT 0x030 +#define ODD_PIXEL_FMT 0x034 +#define FIFO_TRIGGER 0x038 +#define XFER_MODE 0x03C +#define CSR1 0x040 +#define RETRY_WAIT_CNT 0x044 +#define INT_CSR 0x048 +#define EVEN_FLD_MASK 0x04C +#define ODD_FLD_MASK 0x050 +#define MASK_LENGTH 0x054 +#define FIFO_FLAG_CNT 0x058 +#define IIC_CLK_DUR 0x05C +#define IIC_CSR1 0x060 +#define IIC_CSR2 0x064 +#define EVEN_DMA_UPPR_LMT 0x08C +#define ODD_DMA_UPPR_LMT 0x090 + +#define CLK_DUR_VAL 0x01010101 + + + +/******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/ + +/********************************** + * fifo_trigger_tag + */ +typedef union fifo_trigger_tag { + u_long reg; + struct + { + u_long PACKED : 6; + u_long : 9; + u_long PLANER : 7; + u_long : 9; + } fld; +} FIFO_TRIGGER_R; + +/********************************** + * xfer_mode_tag + */ +typedef union xfer_mode_tag { + u_long reg; + struct + { + u_long : 2; + u_long FIELD_TOGGLE : 1; + u_long : 5; + u_long : 2; + u_long : 22; + } fld; +} XFER_MODE_R; + +/********************************** + * csr1_tag + */ +typedef union csr1_tag { + u_long reg; + struct + { + u_long CAP_CONT_EVE : 1; + u_long CAP_CONT_ODD : 1; + u_long CAP_SNGL_EVE : 1; + u_long CAP_SNGL_ODD : 1; + u_long FLD_DN_EVE : 1; + u_long FLD_DN_ODD : 1; + u_long SRST : 1; + u_long FIFO_EN : 1; + u_long FLD_CRPT_EVE : 1; + u_long FLD_CRPT_ODD : 1; + u_long ADDR_ERR_EVE : 1; + u_long ADDR_ERR_ODD : 1; + u_long CRPT_DIS : 1; + u_long RANGE_EN : 1; + u_long : 16; + } fld; +} CSR1_R; + +/********************************** + * retry_wait_cnt_tag + */ +typedef union retry_wait_cnt_tag { + u_long reg; + struct + { + u_long RTRY_WAIT_CNT : 8; + u_long : 24; + } fld; +} RETRY_WAIT_CNT_R; + +/********************************** + * int_csr_tag + */ +typedef union int_csr_tag { + u_long reg; + struct + { + u_long FLD_END_EVE : 1; + u_long FLD_END_ODD : 1; + u_long FLD_START : 1; + u_long : 5; + u_long FLD_END_EVE_EN : 1; + u_long FLD_END_ODD_EN : 1; + u_long FLD_START_EN : 1; + u_long : 21; + } fld; +} INT_CSR_R; + +/********************************** + * mask_length_tag + */ +typedef union mask_length_tag { + u_long reg; + struct + { + u_long MASK_LEN_EVE : 5; + u_long : 11; + u_long MASK_LEN_ODD : 5; + u_long : 11; + } fld; +} MASK_LENGTH_R; + +/********************************** + * fifo_flag_cnt_tag + */ +typedef union fifo_flag_cnt_tag { + u_long reg; + struct + { + u_long AF_COUNT : 7; + u_long : 9; + u_long AE_COUNT : 7; + u_long : 9; + } fld; +} FIFO_FLAG_CNT_R; + +/********************************** + * iic_clk_dur + */ +typedef union iic_clk_dur { + u_long reg; + struct + { + u_long PHASE_1 : 8; + u_long PHASE_2 : 8; + u_long PHASE_3 : 8; + u_long PHASE_4 : 8; + } fld; +} IIC_CLK_DUR_R; + +/********************************** + * iic_csr1_tag + */ +typedef union iic_csr1_tag { + u_long reg; + struct + { + u_long AUTO_EN : 1; + u_long BYPASS : 1; + u_long SDA_OUT : 1; + u_long SCL_OUT : 1; + u_long : 4; + u_long AUTO_ABORT : 1; + u_long DIRECT_ABORT : 1; + u_long SDA_IN : 1; + u_long SCL_IN : 1; + u_long : 4; + u_long AUTO_ADDR : 8; + u_long RD_DATA : 8; + } fld; +} IIC_CSR1_R; + +/********************************** + * iic_csr2_tag + */ +typedef union iic_csr2_tag { + u_long reg; + struct + { + u_long DIR_WR_DATA : 8; + u_long DIR_SUB_ADDR : 8; + u_long DIR_RD : 1; + u_long DIR_ADDR : 7; + u_long NEW_CYCLE : 1; + u_long : 7; + } fld; +} IIC_CSR2_R; + +/* use for both EVEN and ODD DMA UPPER LIMITS */ + +/********************************** + * dma_upper_lmt_tag + */ +typedef union dma_upper_lmt_tag { + u_long reg; + struct + { + u_long DMA_UPPER_LMT_VAL : 24; + u_long : 8; + } fld; +} DMA_UPPER_LMT_R; + + +/*************************************** + * Global declarations of local copies + * of boards' 32 bit registers + ***************************************/ +extern u_long even_dma_start_r; /* bit 0 should always be 0 */ +extern u_long odd_dma_start_r; /* .. */ +extern u_long even_dma_stride_r; /* bits 0&1 should always be 0 */ +extern u_long odd_dma_stride_r; /* .. */ +extern u_long even_pixel_fmt_r; +extern u_long odd_pixel_fmt_r; + +extern FIFO_TRIGGER_R fifo_trigger_r; +extern XFER_MODE_R xfer_mode_r; +extern CSR1_R csr1_r; +extern RETRY_WAIT_CNT_R retry_wait_cnt_r; +extern INT_CSR_R int_csr_r; + +extern u_long even_fld_mask_r; +extern u_long odd_fld_mask_r; + +extern MASK_LENGTH_R mask_length_r; +extern FIFO_FLAG_CNT_R fifo_flag_cnt_r; +extern IIC_CLK_DUR_R iic_clk_dur_r; +extern IIC_CSR1_R iic_csr1_r; +extern IIC_CSR2_R iic_csr2_r; +extern DMA_UPPER_LMT_R even_dma_upper_lmt_r; +extern DMA_UPPER_LMT_R odd_dma_upper_lmt_r; + + + +/***************** 8 bit I2C register globals ***********/ + +#define CSR2 0x010 /* indices of 8-bit I2C mapped reg's*/ +#define EVEN_CSR 0x011 +#define ODD_CSR 0x012 +#define CONFIG 0x013 +#define DT_ID 0x01F +#define X_CLIP_START 0x020 +#define Y_CLIP_START 0x022 +#define X_CLIP_END 0x024 +#define Y_CLIP_END 0x026 +#define AD_ADDR 0x030 +#define AD_LUT 0x031 +#define AD_CMD 0x032 +#define DIG_OUT 0x040 +#define PM_LUT_ADDR 0x050 +#define PM_LUT_DATA 0x051 + + +/******** Assignments and Typedefs for 8 bit I2C Registers********************/ + +typedef union i2c_csr2_tag { + u_char reg; + struct + { + u_char CHROM_FIL : 1; + u_char SYNC_SNTL : 1; + u_char HZ50 : 1; + u_char SYNC_PRESENT : 1; + u_char BUSY_EVE : 1; + u_char BUSY_ODD : 1; + u_char DISP_PASS : 1; + } fld; +} I2C_CSR2; + +typedef union i2c_even_csr_tag { + u_char reg; + struct + { + u_char DONE_EVE : 1; + u_char SNGL_EVE : 1; + u_char ERROR_EVE : 1; + u_char : 5; + } fld; +} I2C_EVEN_CSR; + +typedef union i2c_odd_csr_tag { + u_char reg; + struct + { + u_char DONE_ODD : 1; + u_char SNGL_ODD : 1; + u_char ERROR_ODD : 1; + u_char : 5; + } fld; +} I2C_ODD_CSR; + +typedef union i2c_config_tag { + u_char reg; + struct + { + u_char ACQ_MODE : 2; + u_char EXT_TRIG_EN : 1; + u_char EXT_TRIG_POL : 1; + u_char H_SCALE : 1; + u_char CLIP : 1; + u_char PM_LUT_SEL : 1; + u_char PM_LUT_PGM : 1; + } fld; +} I2C_CONFIG; + + +typedef union i2c_ad_cmd_tag { /* bits can have 3 different meanings + depending on value of AD_ADDR */ + u_char reg; + struct + { + u_char : 2; + u_char SYNC_LVL_SEL : 2; + u_char SYNC_CNL_SEL : 2; + u_char DIGITIZE_CNL_SEL1 : 2; + } bt252_command; /* Bt252 Command Register */ + struct /* if AD_ADDR = 00h */ + { + u_char IOUT_DATA : 8; + } bt252_iout0; /* Bt252 IOUT0 register */ + struct /* if AD_ADDR = 01h */ + { + u_char IOUT_DATA : 8; + } bt252_iout1; /* BT252 IOUT1 register */ +} I2C_AD_CMD; /* if AD_ADDR = 02h */ + + +/***** Global declarations of local copies of boards' 8 bit I2C registers ***/ + +extern I2C_CSR2 i2c_csr2; +extern I2C_EVEN_CSR i2c_even_csr; +extern I2C_ODD_CSR i2c_odd_csr; +extern I2C_CONFIG i2c_config; +extern u_char i2c_dt_id; +extern u_char i2c_x_clip_start; +extern u_char i2c_y_clip_start; +extern u_char i2c_x_clip_end; +extern u_char i2c_y_clip_end; +extern u_char i2c_ad_addr; +extern u_char i2c_ad_lut; +extern I2C_AD_CMD i2c_ad_cmd; +extern u_char i2c_dig_out; +extern u_char i2c_pm_lut_addr; +extern u_char i2c_pm_lut_data; + +/* Functions for Global use */ + +/* access 8-bit IIC registers */ + +extern int ReadI2C (u_char * lpReg, u_short wIregIndex, u_char * byVal); +extern int WriteI2C (u_char * lpReg, u_short wIregIndex, u_char byVal); + +#endif diff --git a/drivers/staging/dt3155/dt3155_isr.c b/drivers/staging/dt3155/dt3155_isr.c new file mode 100644 index 000000000000..339aee9a0925 --- /dev/null +++ b/drivers/staging/dt3155/dt3155_isr.c @@ -0,0 +1,545 @@ +/* + +Copyright 1996,2002,2005 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, + Jason Lapenta, Scott Smedley, Greg Sharp + +This file is part of the DT3155 Device Driver. + +The DT3155 Device Driver is free software; you can redistribute it +and/or modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2 of the +License, or (at your option) any later version. + +The DT3155 Device Driver is distributed in the hope that it will be +useful, but WITHOUT ANY WARRANTY; without even the implied warranty +of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with the DT3155 Device Driver; if not, write to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, +MA 02111-1307 USA + + File: dt3155_isr.c +Purpose: Buffer management routines, and other routines for the ISR + (the actual isr is in dt3155_drv.c) + +-- Changes -- + + Date Programmer Description of changes made + ------------------------------------------------------------------- + 03-Jul-2000 JML n/a + 02-Apr-2002 SS Mods to make work with separate allocator + module; Merged John Roll's mods to make work with + multiple boards. + 10-Jul-2002 GCS Complete rewrite of setup_buffers to disallow + buffers which span a 4MB boundary. + 24-Jul-2002 SS GPL licence. + 30-Jul-2002 NJC Added support for buffer loop. + 31-Jul-2002 NJC Complete rewrite of buffer management + 02-Aug-2002 NJC Including slab.h instead of malloc.h (no warning). + Also, allocator_init() now returns allocator_max + so cleaned up allocate_buffers() accordingly. + 08-Aug-2005 SS port to 2.6 kernel. + +*/ + +#include +#include +#include +#include + +#include "dt3155.h" +#include "dt3155_drv.h" +#include "dt3155_io.h" +#include "dt3155_isr.h" +#include "allocator.h" + +#define FOUR_MB (0x0400000) /* Can't DMA accross a 4MB boundary!*/ +#define UPPER_10_BITS (0x3FF<<22) /* Can't DMA accross a 4MB boundary!*/ + + +/* Pointer into global structure for handling buffers */ +struct dt3155_fbuffer_s *dt3155_fbuffer[MAXBOARDS] = {NULL +#if MAXBOARDS == 2 + , NULL +#endif +}; + +/****************************************************************************** + * Simple array based que struct + * + * Some handy functions using the buffering structure. + *****************************************************************************/ + + +/*************************** + * are_empty_buffers + * m is minor # of device + ***************************/ +inline bool are_empty_buffers( int m ) +{ + return ( dt3155_fbuffer[ m ]->empty_len ); +} + +/************************** + * push_empty + * m is minor # of device + * + * This is slightly confusing. The number empty_len is the literal # + * of empty buffers. After calling, empty_len-1 is the index into the + * empty buffer stack. So, if empty_len == 1, there is one empty buffer, + * given by dt3155_fbuffer[m]->empty_buffers[0]. + * empty_buffers should never fill up, though this is not checked. + **************************/ +inline void push_empty( int index, int m ) +{ + dt3155_fbuffer[m]->empty_buffers[ dt3155_fbuffer[m]->empty_len ] = index; + dt3155_fbuffer[m]->empty_len++; +} + +/************************** + * pop_empty( m ) + * m is minor # of device + **************************/ +inline int pop_empty( int m ) +{ + dt3155_fbuffer[m]->empty_len--; + return dt3155_fbuffer[m]->empty_buffers[ dt3155_fbuffer[m]->empty_len ]; +} + +/************************* + * is_ready_buf_empty( m ) + * m is minor # of device + *************************/ +inline bool is_ready_buf_empty( int m ) +{ + return ((dt3155_fbuffer[ m ]->ready_len) == 0); +} + +/************************* + * is_ready_buf_full( m ) + * m is minor # of device + * this should *never* be true if there are any active, locked or empty + * buffers, since it corresponds to nbuffers ready buffers!! + * 7/31/02: total rewrite. --NJC + *************************/ +inline bool is_ready_buf_full( int m ) +{ + return ( dt3155_fbuffer[ m ]->ready_len == dt3155_fbuffer[ m ]->nbuffers ); +} + +/***************************************************** + * push_ready( m, buffer ) + * m is minor # of device + * + *****************************************************/ +inline void push_ready( int m, int index ) +{ + int head = dt3155_fbuffer[m]->ready_head; + + dt3155_fbuffer[ m ]->ready_que[ head ] = index; + dt3155_fbuffer[ m ]->ready_head = ( (head + 1) % + (dt3155_fbuffer[ m ]->nbuffers) ); + dt3155_fbuffer[ m ]->ready_len++; + +} + +/***************************************************** + * get_tail() + * m is minor # of device + * + * Simply comptutes the tail given the head and the length. + *****************************************************/ +static inline int get_tail( int m ) +{ + return ((dt3155_fbuffer[ m ]->ready_head - + dt3155_fbuffer[ m ]->ready_len + + dt3155_fbuffer[ m ]->nbuffers)% + (dt3155_fbuffer[ m ]->nbuffers)); +} + + + +/***************************************************** + * pop_ready() + * m is minor # of device + * + * This assumes that there is a ready buffer ready... should + * be checked (e.g. with is_ready_buf_empty() prior to call. + *****************************************************/ +inline int pop_ready( int m ) +{ + int tail; + tail = get_tail(m); + dt3155_fbuffer[ m ]->ready_len--; + return dt3155_fbuffer[ m ]->ready_que[ tail ]; +} + + +/***************************************************** + * printques + * m is minor # of device + *****************************************************/ +inline void printques( int m ) +{ + int head = dt3155_fbuffer[ m ]->ready_head; + int tail; + int num = dt3155_fbuffer[ m ]->nbuffers; + int frame_index; + int index; + + tail = get_tail(m); + + printk("\n R:"); + for ( index = tail; index != head; index++, index = index % (num) ) + { + frame_index = dt3155_fbuffer[ m ]->ready_que[ index ]; + printk(" %d ", frame_index ); + } + + printk("\n E:"); + for ( index = 0; index < dt3155_fbuffer[ m ]->empty_len; index++ ) + { + frame_index = dt3155_fbuffer[ m ]->empty_buffers[ index ]; + printk(" %d ", frame_index ); + } + + frame_index = dt3155_fbuffer[ m ]->active_buf; + printk("\n A: %d", frame_index); + + frame_index = dt3155_fbuffer[ m ]->locked_buf; + printk("\n L: %d \n", frame_index ); + +} + +/***************************************************** + * adjust_4MB + * + * If a buffer intersects the 4MB boundary, push + * the start address up to the beginning of the + * next 4MB chunk (assuming bufsize < 4MB). + *****************************************************/ +u_long adjust_4MB (u_long buf_addr, u_long bufsize) { + if (((buf_addr+bufsize) & UPPER_10_BITS) != (buf_addr & UPPER_10_BITS)) + return (buf_addr+bufsize) & UPPER_10_BITS; + else + return buf_addr; +} + + +/***************************************************** + * allocate_buffers + * + * Try to allocate enough memory for all requested + * buffers. If there is not enough free space + * try for less memory. + *****************************************************/ +void allocate_buffers (u_long *buf_addr, u_long* total_size_kbs, + u_long bufsize) +{ + /* Compute the minimum amount of memory guaranteed to hold all + MAXBUFFERS such that no buffer crosses the 4MB boundary. + Store this value in the variable "full_size" */ + + u_long allocator_max; + u_long bufs_per_chunk = (FOUR_MB / bufsize); + u_long filled_chunks = (MAXBUFFERS-1) / bufs_per_chunk; + u_long leftover_bufs = MAXBUFFERS - filled_chunks * bufs_per_chunk; + + u_long full_size = bufsize /* possibly unusable part of 1st chunk */ + + filled_chunks * FOUR_MB /* max # of completely filled 4mb chunks */ + + leftover_bufs * bufsize; /* these buffs will be in a partly filled + chunk at beginning or end */ + + u_long full_size_kbs = 1 + (full_size-1) / 1024; + u_long min_size_kbs = 2*ndevices*bufsize / 1024; + u_long size_kbs; + + /* Now, try to allocate full_size. If this fails, keep trying for + less & less memory until it succeeds. */ +#ifndef STANDALONE_ALLOCATOR + /* initialize the allocator */ + allocator_init(&allocator_max); +#endif + size_kbs = full_size_kbs; + *buf_addr = 0; + printk ("DT3155: We would like to get: %d KB\n", (u_int)(full_size_kbs)); + printk ("DT3155: ...but need at least: %d KB\n", (u_int)(min_size_kbs)); + printk ("DT3155: ...the allocator has: %d KB\n", (u_int)(allocator_max)); + size_kbs = (full_size_kbs <= allocator_max ? full_size_kbs : allocator_max); + if (size_kbs > min_size_kbs) { + if ((*buf_addr = allocator_allocate_dma (size_kbs, GFP_KERNEL)) != 0) { + printk ("DT3155: Managed to allocate: %d KB\n", (u_int)size_kbs); + *total_size_kbs = size_kbs; + return; + } + } + /* If we got here, the allocation failed */ + printk ("DT3155: Allocator failed!\n"); + *buf_addr = 0; + *total_size_kbs = 0; + return; + +} + + +/***************************************************** + * dt3155_setup_buffers + * + * setup_buffers just puts the buffering system into + * a consistent state before the start of interrupts + * + * JML : it looks like all the buffers need to be + * continuous. So I'm going to try and allocate one + * continuous buffer. + * + * GCS : Fix DMA problems when buffer spans + * 4MB boundary. Also, add error checking. This + * function will return -ENOMEM when not enough memory. + *****************************************************/ +u_long dt3155_setup_buffers(u_long *allocatorAddr) + +{ + u_long index; + u_long rambuff_addr; /* start of allocation */ + u_long rambuff_size; /* total size allocated to driver */ + u_long rambuff_acm; /* accumlator, keep track of how much + is left after being split up*/ + u_long rambuff_end; /* end of rambuff */ + u_long numbufs; /* number of useful buffers allocated (per device) */ + u_long bufsize = DT3155_MAX_ROWS * DT3155_MAX_COLS; + int m; /* minor # of device, looped for all devs */ + + /* zero the fbuffer status and address structure */ + for ( m = 0; m < ndevices; m++) + { + dt3155_fbuffer[ m ] = &(dt3155_status[ m ].fbuffer); + + /* Make sure the buffering variables are consistent */ + { + u_char *ptr = (u_char *) dt3155_fbuffer[ m ]; + for( index = 0; index < sizeof(struct dt3155_fbuffer_s); index++) + *(ptr++)=0; + } + } + + /* allocate a large contiguous chunk of RAM */ + allocate_buffers (&rambuff_addr, &rambuff_size, bufsize); + printk( "DT3155: mem info\n" ); + printk( " - rambuf_addr = 0x%x \n", (u_int)rambuff_addr ); + printk( " - length (kb) = %u \n", (u_int)rambuff_size ); + if( rambuff_addr == 0 ) + { + printk( KERN_INFO + "DT3155: Error setup_buffers() allocator dma failed \n" ); + return -ENOMEM; + } + *allocatorAddr = rambuff_addr; + rambuff_end = rambuff_addr + 1024 * rambuff_size; + + /* after allocation, we need to count how many useful buffers there + are so we can give an equal number to each device */ + rambuff_acm = rambuff_addr; + for ( index = 0; index < MAXBUFFERS; index++) { + rambuff_acm = adjust_4MB (rambuff_acm, bufsize);/*avoid spanning 4MB bdry*/ + if (rambuff_acm + bufsize > rambuff_end) + break; + rambuff_acm += bufsize; + } + /* Following line is OK, will waste buffers if index + * not evenly divisible by ndevices -NJC*/ + numbufs = index / ndevices; + printk (" - numbufs = %u\n", (u_int) numbufs); + if (numbufs < 2) { + printk( KERN_INFO + "DT3155: Error setup_buffers() couldn't allocate 2 bufs/board\n" ); + return -ENOMEM; + } + + /* now that we have board memory we spit it up */ + /* between the boards and the buffers */ + rambuff_acm = rambuff_addr; + for ( m = 0; m < ndevices; m ++) + { + rambuff_acm = adjust_4MB (rambuff_acm, bufsize); + + /* Save the start of this boards buffer space (for mmap). */ + dt3155_status[ m ].mem_addr = rambuff_acm; + + for (index = 0; index < numbufs; index++) + { + rambuff_acm = adjust_4MB (rambuff_acm, bufsize); + if (rambuff_acm + bufsize > rambuff_end) { + /* Should never happen */ + printk ("DT3155 PROGRAM ERROR (GCS)\n" + "Error distributing allocated buffers\n"); + return -ENOMEM; + } + + dt3155_fbuffer[ m ]->frame_info[ index ].addr = rambuff_acm; + push_empty( index, m ); + /* printk(" - Buffer : %lx\n", + * dt3155_fbuffer[ m ]->frame_info[ index ].addr ); + */ + dt3155_fbuffer[ m ]->nbuffers += 1; + rambuff_acm += bufsize; + } + + /* Make sure there is an active buffer there. */ + dt3155_fbuffer[ m ]->active_buf = pop_empty( m ); + dt3155_fbuffer[ m ]->even_happened = 0; + dt3155_fbuffer[ m ]->even_stopped = 0; + + /* make sure there is no locked_buf JML 2/28/00 */ + dt3155_fbuffer[ m ]->locked_buf = -1; + + dt3155_status[ m ].mem_size = + rambuff_acm - dt3155_status[ m ].mem_addr; + + /* setup the ready queue */ + dt3155_fbuffer[ m ]->ready_head = 0; + dt3155_fbuffer[ m ]->ready_len = 0; + printk("Available buffers for device %d: %d\n", + m, dt3155_fbuffer[ m ]->nbuffers); + } + + return 1; +} + +/***************************************************** + * internal_release_locked_buffer + * + * The internal function for releasing a locked buffer. + * It assumes interrupts are turned off. + * + * m is minor number of device + *****************************************************/ +static inline void internal_release_locked_buffer( int m ) +{ + /* Pointer into global structure for handling buffers */ + if ( dt3155_fbuffer[ m ]->locked_buf >= 0 ) + { + push_empty( dt3155_fbuffer[ m ]->locked_buf, m ); + dt3155_fbuffer[ m ]->locked_buf = -1; + } +} + + +/***************************************************** + * dt3155_release_locked_buffer() + * m is minor # of device + * + * The user function of the above. + * + *****************************************************/ +inline void dt3155_release_locked_buffer( int m ) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + unsigned long int flags; + local_save_flags(flags); + local_irq_disable(); + internal_release_locked_buffer(m); + local_irq_restore(flags); +#else + int flags; + + save_flags( flags ); + cli(); + internal_release_locked_buffer( m ); + restore_flags( flags ); +#endif +} + + +/***************************************************** + * dt3155_flush() + * m is minor # of device + * + *****************************************************/ +inline int dt3155_flush( int m ) +{ + int index; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + unsigned long int flags; + local_save_flags(flags); + local_irq_disable(); +#else + int flags; + save_flags( flags ); + cli(); +#endif + + internal_release_locked_buffer( m ); + dt3155_fbuffer[ m ]->empty_len = 0; + + for ( index = 0; index < dt3155_fbuffer[ m ]->nbuffers; index++ ) + push_empty( index, m ); + + /* Make sure there is an active buffer there. */ + dt3155_fbuffer[ m ]->active_buf = pop_empty( m ); + + dt3155_fbuffer[ m ]->even_happened = 0; + dt3155_fbuffer[ m ]->even_stopped = 0; + + /* setup the ready queue */ + dt3155_fbuffer[ m ]->ready_head = 0; + dt3155_fbuffer[ m ]->ready_len = 0; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + local_irq_restore(flags); +#else + restore_flags( flags ); +#endif + + return 0; +} + +/***************************************************** + * dt3155_get_ready_buffer() + * m is minor # of device + * + * get_ready_buffer will grab the next chunk of data + * if it is already there, otherwise it returns 0. + * If the user has a buffer locked it will unlock + * that buffer before returning the new one. + *****************************************************/ +inline int dt3155_get_ready_buffer( int m ) +{ + int frame_index; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + unsigned long int flags; + local_save_flags(flags); + local_irq_disable(); +#else + int flags; + save_flags( flags ); + cli(); +#endif + +#ifdef DEBUG_QUES_A + printques( m ); +#endif + + internal_release_locked_buffer( m ); + + if (is_ready_buf_empty( m )) + frame_index = -1; + else + { + frame_index = pop_ready( m ); + dt3155_fbuffer[ m ]->locked_buf = frame_index; + } + +#ifdef DEBUG_QUES_B + printques( m ); +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + local_irq_restore(flags); +#else + restore_flags( flags ); +#endif + + return frame_index; +} diff --git a/drivers/staging/dt3155/dt3155_isr.h b/drivers/staging/dt3155/dt3155_isr.h new file mode 100644 index 000000000000..b117b504e277 --- /dev/null +++ b/drivers/staging/dt3155/dt3155_isr.h @@ -0,0 +1,77 @@ +/* + +Copyright 1996,2002 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, + Jason Lapenta, Scott Smedley + +This file is part of the DT3155 Device Driver. + +The DT3155 Device Driver is free software; you can redistribute it +and/or modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2 of the +License, or (at your option) any later version. + +The DT3155 Device Driver is distributed in the hope that it will be +useful, but WITHOUT ANY WARRANTY; without even the implied warranty +of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with the DT3155 Device Driver; if not, write to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, +MA 02111-1307 USA + + +-- Changes -- + + Date Programmer Description of changes made + ------------------------------------------------------------------- + 03-Jul-2000 JML n/a + 24-Jul-2002 SS GPL licence. + 26-Oct-2009 SS Porting to 2.6.30 kernel. + +-- notes -- + +*/ + +#ifndef DT3155_ISR_H +#define DT3155_ISR_H + +extern struct dt3155_fbuffer_s *dt3155_fbuffer[MAXBOARDS]; + +/* User functions for buffering */ +/* Initialize the buffering system. This should */ +/* be called prior to enabling interrupts */ + +u_long dt3155_setup_buffers(u_long *allocatorAddr); + +/* Get the next frame of data if it is ready. Returns */ +/* zero if no data is ready. If there is data but */ +/* the user has a locked buffer, it will unlock that */ +/* buffer and return it to the free list. */ + +int dt3155_get_ready_buffer(int minor); + +/* Return a locked buffer to the free list */ + +void dt3155_release_locked_buffer(int minor); + +/* Flush the buffer system */ +int dt3155_flush(int minor); + +/********************************** + * Simple array based que struct + **********************************/ + +bool are_empty_buffers( int minor ); +void push_empty( int index, int minor ); + +int pop_empty( int minor ); + +bool is_ready_buf_empty( int minor ); +bool is_ready_buf_full( int minor ); + +void push_ready( int minor, int index ); +int pop_ready( int minor ); + + +#endif diff --git a/drivers/staging/dt3155/pci-compat.h b/drivers/staging/dt3155/pci-compat.h new file mode 100644 index 000000000000..5f47d5a94d4b --- /dev/null +++ b/drivers/staging/dt3155/pci-compat.h @@ -0,0 +1,97 @@ + +/* This header only makes send when included in a 2.0 compile */ + +#ifndef _PCI_COMPAT_H_ +#define _PCI_COMPAT_H_ + +#ifdef __KERNEL__ + +#include /* pcibios_* */ +#include /* pcibios_* */ +#include /* kmalloc */ + +/* fake the new pci interface based on the old one: encapsulate bus/devfn */ +struct pci_fake_dev { + u8 bus; + u8 devfn; + int index; +}; +#define pci_dev pci_fake_dev /* the other pci_dev is unused by 2.0 drivers */ + +extern inline struct pci_dev *pci_find_device(unsigned int vendorid, + unsigned int devid, + struct pci_dev *from) +{ + struct pci_dev *pptr = kmalloc(sizeof(*pptr), GFP_KERNEL); + int index = 0; + int ret; + + if (!pptr) return NULL; + if (from) index = pptr->index + 1; + ret = pcibios_find_device(vendorid, devid, index, + &pptr->bus, &pptr->devfn); + if (ret) { kfree(pptr); return NULL; } + return pptr; +} + +extern inline struct pci_dev *pci_find_class(unsigned int class, + struct pci_dev *from) +{ + return NULL; /* FIXME */ +} + +extern inline void pci_release_device(struct pci_dev *dev) +{ + kfree(dev); +} + +/* struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn); */ + +#define pci_present pcibios_present + +extern inline int +pci_read_config_byte(struct pci_dev *dev, u8 where, u8 *val) +{ + return pcibios_read_config_byte(dev->bus, dev->devfn, where, val); +} + +extern inline int +pci_read_config_word(struct pci_dev *dev, u8 where, u16 *val) +{ + return pcibios_read_config_word(dev->bus, dev->devfn, where, val); +} + +extern inline int +pci_read_config_dword(struct pci_dev *dev, u8 where, u32 *val) +{ + return pcibios_read_config_dword(dev->bus, dev->devfn, where, val); +} + +extern inline int +pci_write_config_byte(struct pci_dev *dev, u8 where, u8 val) +{ + return pcibios_write_config_byte(dev->bus, dev->devfn, where, val); +} + +extern inline int +pci_write_config_word(struct pci_dev *dev, u8 where, u16 val) +{ + return pcibios_write_config_word(dev->bus, dev->devfn, where, val); +} + +extern inline int +pci_write_config_dword(struct pci_dev *dev, u8 where, u32 val) +{ + return pcibios_write_config_dword(dev->bus, dev->devfn, where, val); +} + +extern inline void pci_set_master(struct pci_dev *dev) +{ + u16 cmd; + pcibios_read_config_word(dev->bus, dev->devfn, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + pcibios_write_config_word(dev->bus, dev->devfn, PCI_COMMAND, cmd); +} + +#endif /* __KERNEL__ */ +#endif /* _PCI_COMPAT_H_ */ diff --git a/drivers/staging/dt3155/sysdep.h b/drivers/staging/dt3155/sysdep.h new file mode 100644 index 000000000000..1d575d4a53ee --- /dev/null +++ b/drivers/staging/dt3155/sysdep.h @@ -0,0 +1,820 @@ +/* + * sysdep.h -- centralizing compatibility issues between 2.0, 2.2, 2.4 + * + * Copyright (C) 2001 Alessandro Rubini and Jonathan Corbet + * Copyright (C) 2001 O'Reilly & Associates + * + * The source code in this file can be freely used, adapted, + * and redistributed in source or binary form, so long as an + * acknowledgment appears in derived source files. The citation + * should list that the code comes from the book "Linux Device + * Drivers" by Alessandro Rubini and Jonathan Corbet, published + * by O'Reilly & Associates. No warranty is attached; + * we cannot take responsibility for errors or fitness for use. + * + * $Id: sysdep.h,v 1.2 2005/08/09 06:08:51 ssmedley Exp $ + */ + + +#ifndef _SYSDEP_H_ +#define _SYSDEP_H_ + +#ifndef LINUX_VERSION_CODE +# include +#endif + +#ifndef KERNEL_VERSION /* pre-2.1.90 didn't have it */ +# define KERNEL_VERSION(vers,rel,seq) ( ((vers)<<16) | ((rel)<<8) | (seq) ) +#endif + +/* only allow 2.0.x 2.2.y and 2.4.z */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,0,0) /* not < 2.0 */ +# error "This kernel is too old: not supported by this file" +#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,7,0) /* not > 2.7, by now */ +# error "This kernel is too recent: not supported by this file" +#endif +#if (LINUX_VERSION_CODE & 0xff00) == 1 /* not 2.1 */ +# error "Please don't use linux-2.1, use 2.2, 2.4 or 2.6 instead" +#endif +#if (LINUX_VERSION_CODE & 0xff00) == 3 /* not 2.3 */ +# error "Please don't use linux-2.3, use 2.4 or 2.6 instead" +#endif + +/* remember about the current version */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0) +# define LINUX_20 +#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0) +# define LINUX_22 +#else +# define LINUX_24 +#endif + +/* we can't support versioning in pre-2.4 because we #define some functions */ +#if !defined(LINUX_24) && defined(CONFIG_MODVERSIONS) +# error "This sysdep.h can't support CONFIG_MODVERSIONS" +# error "and old kernels at the same time." +# error "Either use 2.4 or avoid using versioning" +#endif + +#ifndef LINUX_20 /* include vmalloc.h if this is 2.2/2.4 */ +# ifdef VM_READ /* a typical flag defined by mm.h */ +# include +# endif +#endif + +#include + +/* Modularization issues */ +#ifdef LINUX_20 +# define __USE_OLD_SYMTAB__ +# define EXPORT_NO_SYMBOLS register_symtab(NULL); +# define REGISTER_SYMTAB(tab) register_symtab(tab) +#else +# define REGISTER_SYMTAB(tab) /* nothing */ +#endif + +#ifdef __USE_OLD_SYMTAB__ +# define __MODULE_STRING(s) /* nothing */ +# define MODULE_PARM(v,t) /* nothing */ +# define MODULE_PARM_DESC(v,t) /* nothing */ +# define MODULE_AUTHOR(n) /* nothing */ +# define MODULE_DESCRIPTION(d) /* nothing */ +# define MODULE_SUPPORTED_DEVICE(n) /* nothing */ +#endif + +/* + * In version 2.2 (up to 2.2.19, at least), the macro for request_module() + * when no kmod is there is wrong. It's a "do {} while 0" but it shouldbe int + */ +#ifdef LINUX_22 +# ifndef CONFIG_KMOD +# undef request_module +# define request_module(name) -ENOSYS +# endif +#endif + + +#ifndef LINUX_20 +# include /* module_init/module_exit */ +#endif + +#ifndef module_init +# define module_init(x) int init_module(void) { return x(); } +# define module_exit(x) void cleanup_module(void) { x(); } +#endif + +#ifndef SET_MODULE_OWNER +# define SET_MODULE_OWNER(structure) /* nothing */ +#endif + +/* + * "select" changed in 2.1.23. The implementation is twin, but this + * header is new + * + */ +#ifdef LINUX_20 +# define __USE_OLD_SELECT__ +#else +# include +#endif + +#ifdef LINUX_20 +# define INODE_FROM_F(filp) ((filp)->f_inode) +#else +# define INODE_FROM_F(filp) ((filp)->f_dentry->d_inode) +#endif + +/* Other changes in the fops are solved using wrappers */ + +/* + * Wait queues changed with 2.3 + */ +#ifndef DECLARE_WAIT_QUEUE_HEAD +# define DECLARE_WAIT_QUEUE_HEAD(head) struct wait_queue *head = NULL + typedef struct wait_queue *wait_queue_head_t; +# define init_waitqueue_head(head) (*(head)) = NULL + +/* offer wake_up_sync as an alias for wake_up */ +# define wake_up_sync(head) wake_up(head) +# define wake_up_interruptible_sync(head) wake_up_interruptible(head) + +/* Pretend we have add_wait_queue_exclusive */ +# define add_wait_queue_exclusive(q,entry) add_wait_queue ((q), (entry)) + +#endif /* no DECLARE_WAIT_QUEUE_HEAD */ + +/* + * Define wait_event for 2.0 kernels. (This ripped off directly from + * the 2.2.18 sched.h) + */ +#ifdef LINUX_20 + +#define __wait_event(wq, condition) \ +do { \ + struct wait_queue __wait; \ + \ + __wait.task = current; \ + add_wait_queue(&wq, &__wait); \ + for (;;) { \ + current->state = TASK_UNINTERRUPTIBLE; \ + mb(); \ + if (condition) \ + break; \ + schedule(); \ + } \ + current->state = TASK_RUNNING; \ + remove_wait_queue(&wq, &__wait); \ +} while (0) + +#define wait_event(wq, condition) \ +do { \ + if (condition) \ + break; \ + __wait_event(wq, condition); \ +} while (0) + +#define __wait_event_interruptible(wq, condition, ret) \ +do { \ + struct wait_queue __wait; \ + \ + __wait.task = current; \ + add_wait_queue(&wq, &__wait); \ + for (;;) { \ + current->state = TASK_INTERRUPTIBLE; \ + mb(); \ + if (condition) \ + break; \ + if (!signal_pending(current)) { \ + schedule(); \ + continue; \ + } \ + ret = -ERESTARTSYS; \ + break; \ + } \ + current->state = TASK_RUNNING; \ + remove_wait_queue(&wq, &__wait); \ +} while (0) + +#define wait_event_interruptible(wq, condition) \ +({ \ + int __ret = 0; \ + if (!(condition)) \ + __wait_event_interruptible(wq, condition, __ret); \ + __ret; \ +}) +#endif + + +/* + * 2.3 added tasklets + */ +#ifdef LINUX_24 +# define HAVE_TASKLETS +#endif + + + + +/* FIXME: implement the other versions of wake_up etc */ + + +/* + * access to user space: use the 2.2 functions, + * and implement them as macros for 2.0 + */ + +#ifdef LINUX_20 +# include +# define access_ok(t,a,sz) (verify_area((t),(void *) (a),(sz)) ? 0 : 1) +# define verify_area_20 verify_area +# define copy_to_user(t,f,n) (memcpy_tofs((t), (f), (n)), 0) +# define copy_from_user(t,f,n) (memcpy_fromfs((t), (f), (n)), 0) +# define __copy_to_user(t,f,n) copy_to_user((t), (f), (n)) +# define __copy_from_user(t,f,n) copy_from_user((t), (f), (n)) + +# define PUT_USER(val,add) (put_user((val),(add)), 0) +# define __PUT_USER(val,add) PUT_USER((val),(add)) + +# define GET_USER(dest,add) ((dest)=get_user((add)), 0) +# define __GET_USER(dest,add) GET_USER((dest),(add)) +#else +# include +# include +# define verify_area_20(t,a,sz) (0) /* == success */ +# define PUT_USER put_user +# define __PUT_USER __put_user +# define GET_USER get_user +# define __GET_USER __get_user +#endif + +/* + * Allocation issues + */ +#ifdef GFP_USER /* only if mm.h has been included */ +# ifdef LINUX_20 +# define __GFP_DMA GFP_DMA /* 2.0 didn't have the leading __ */ +# endif +# ifndef LINUX_24 +# define __GFP_HIGHMEM 0 /* was not there */ +# define GFP_HIGHUSER 0 /* idem */ +# endif + +# ifdef LINUX_20 +# define __get_free_pages(a,b) __get_free_pages((a),(b),0) +# endif +# ifndef LINUX_24 +# define get_zeroed_page get_free_page +# endif +#endif + +/* ioremap */ +#if defined(LINUX_20) && defined(_LINUX_MM_H) +# define ioremap_nocache ioremap +# ifndef __i386__ + /* This simple approach works for non-PC platforms. */ +# define ioremap vremap +# define iounmap vfree +# else /* the PC has ISA; 2.2 and 2.4 remap it, 2.0 needs not */ +extern inline void *ioremap(unsigned long phys_addr, unsigned long size) +{ + if (phys_addr >= 0xA0000 && phys_addr + size <= 0x100000) + return (void *)phys_addr; + return vremap(phys_addr, size); +} + +extern inline void iounmap(void *addr) +{ + if ((unsigned long)addr >= 0xA0000 + && (unsigned long)addr < 0x100000) + return; + vfree(addr); +} +# endif +#endif + +/* Also, define check_mem_region etc */ +#ifndef LINUX_24 +# define check_mem_region(a,b) 0 /* success */ +# define request_mem_region(a,b,c) /* nothing */ +# define release_mem_region(a,b) /* nothing */ +#endif + +/* implement capable() for 2.0 */ +#ifdef LINUX_20 +# define capable(anything) suser() +#endif + +/* The use_count of exec_domain and binfmt changed in 2.1.23 */ + +#ifdef LINUX_20 +# define INCRCOUNT(p) ((p)->module ? __MOD_INC_USE_COUNT((p)->module) : 0) +# define DECRCOUNT(p) ((p)->module ? __MOD_DEC_USE_COUNT((p)->module) : 0) +# define CURRCOUNT(p) ((p)->module && (p)->module->usecount) +#else +# define INCRCOUNT(p) ((p)->use_count++) +# define DECRCOUNT(p) ((p)->use_count--) +# define CURRCOUNT(p) ((p)->use_count) +#endif + +/* + * /proc has changed a lot across the versions... + */ +#ifdef LINUX_20 +# define USE_PROC_REGISTER +#endif + + +/* + * 2.2 didn't have create_proc_{read|info}_entry yet. + * And it looks like there are no other "interesting" entry point, as + * the rest is somehow esotique (mknod, symlink, ...) + */ +#ifdef LINUX_22 +# ifdef PROC_SUPER_MAGIC /* Only if procfs is being used */ +extern inline struct proc_dir_entry *create_proc_read_entry(const char *name, + mode_t mode, struct proc_dir_entry *base, + read_proc_t *read_proc, void * data) +{ + struct proc_dir_entry *res=create_proc_entry(name,mode,base); + if (res) { + res->read_proc=read_proc; + res->data=data; + } + return res; +} + +# ifndef create_proc_info_entry /* added in 2.2.18 */ +typedef int (get_info_t)(char *, char **, off_t, int, int); +extern inline struct proc_dir_entry *create_proc_info_entry(const char *name, + mode_t mode, struct proc_dir_entry *base, get_info_t *get_info) +{ + struct proc_dir_entry *res=create_proc_entry(name,mode,base); + if (res) res->get_info=get_info; + return res; +} +# endif /* no create_proc_info_entry */ +# endif +#endif + +#ifdef LINUX_20 +# define test_and_set_bit(nr,addr) test_bit((nr),(addr)) +# define test_and_clear_bit(nr,addr) clear_bit((nr),(addr)) +# define test_and_change_bit(nr,addr) change_bit((nr),(addr)) +#endif + + +/* 2.0 had no read and write memory barriers, and 2.2 lacks the + set_ functions */ +#ifndef LINUX_24 +# ifdef LINUX_20 +# define wmb() mb() /* this is a big penalty on non-reordering platfs */ +# define rmb() mb() /* this is a big penalty on non-reordering platfs */ +# endif /* LINUX_20 */ + +#define set_mb() do { var = value; mb(); } while (0) +#define set_wmb() do { var = value; wmb(); } while (0) +#endif /* ! LINUX_24 */ + + + +/* 2.1.30 removed these functions. Let's define them, just in case */ +#ifndef LINUX_20 +# define queue_task_irq queue_task +# define queue_task_irq_off queue_task +#endif + +/* 2.1.10 and 2.1.43 introduced new functions. They are worth using */ + +#ifdef LINUX_20 + +# include +# ifdef __LITTLE_ENDIAN +# define cpu_to_le16(x) (x) +# define cpu_to_le32(x) (x) +# define cpu_to_be16(x) htons((x)) +# define cpu_to_be32(x) htonl((x)) +# else +# define cpu_to_be16(x) (x) +# define cpu_to_be32(x) (x) + extern inline __u16 cpu_to_le16(__u16 x) { return (x<<8) | (x>>8);} + extern inline __u32 cpu_to_le32(__u32 x) { return (x>>24) | + ((x>>8)&0xff00) | ((x<<8)&0xff0000) | (x<<24);} +# endif + +# define le16_to_cpu(x) cpu_to_le16(x) +# define le32_to_cpu(x) cpu_to_le32(x) +# define be16_to_cpu(x) cpu_to_be16(x) +# define be32_to_cpu(x) cpu_to_be32(x) + +# define cpu_to_le16p(addr) (cpu_to_le16(*(addr))) +# define cpu_to_le32p(addr) (cpu_to_le32(*(addr))) +# define cpu_to_be16p(addr) (cpu_to_be16(*(addr))) +# define cpu_to_be32p(addr) (cpu_to_be32(*(addr))) + + extern inline void cpu_to_le16s(__u16 *a) {*a = cpu_to_le16(*a);} + extern inline void cpu_to_le32s(__u16 *a) {*a = cpu_to_le32(*a);} + extern inline void cpu_to_be16s(__u16 *a) {*a = cpu_to_be16(*a);} + extern inline void cpu_to_be32s(__u16 *a) {*a = cpu_to_be32(*a);} + +# define le16_to_cpup(x) cpu_to_le16p(x) +# define le32_to_cpup(x) cpu_to_le32p(x) +# define be16_to_cpup(x) cpu_to_be16p(x) +# define be32_to_cpup(x) cpu_to_be32p(x) + +# define le16_to_cpus(x) cpu_to_le16s(x) +# define le32_to_cpus(x) cpu_to_le32s(x) +# define be16_to_cpus(x) cpu_to_be16s(x) +# define be32_to_cpus(x) cpu_to_be32s(x) + +#endif + +#ifdef LINUX_20 +# define __USE_OLD_REBUILD_HEADER__ +#endif + +/* + * 2.0 didn't include sema_init, so we make our own - but only if it + * looks like semaphore.h got included. + */ +#ifdef LINUX_20 +# ifdef MUTEX_LOCKED /* Only if semaphore.h included */ + extern inline void sema_init (struct semaphore *sem, int val) + { + sem->count = val; + sem->waking = sem->lock = 0; + sem->wait = NULL; + } +# endif +#endif /* LINUX_20 */ + +/* + * In 2.0, there is no real need for spinlocks, and they weren't really + * implemented anyway. + * + * XXX the _irqsave variant should be defined eventually to do the + * right thing. + */ +#ifdef LINUX_20 +typedef int spinlock_t; +# define spin_lock(lock) +# define spin_unlock(lock) +# define spin_lock_init(lock) + +# define spin_lock_irqsave(lock,flags) do { \ + save_flags(flags); cli(); } while (0); +# define spin_unlock_irqrestore(lock,flags) restore_flags(flags); +#endif + +/* + * 2.1 stuffed the "flush" method into the middle of the file_operations + * structure. The FOP_NO_FLUSH symbol is for drivers that do not implement + * flush (most of them), it can be inserted in initializers for all 2.x + * kernel versions. + */ +#ifdef LINUX_20 +# define FOP_NO_FLUSH /* nothing */ +# define TAG_LLSEEK lseek +# define TAG_POLL select +#else +# define FOP_NO_FLUSH NULL, +# define TAG_LLSEEK llseek +# define TAG_POLL poll +#endif + + + +/* + * fasync changed in 2.2. + */ +#ifdef LINUX_20 +/* typedef struct inode *fasync_file; */ +# define fasync_file struct inode * +#else + typedef int fasync_file; +#endif + +/* kill_fasync had less arguments, and a different indirection in the first */ +#ifndef LINUX_24 +# define kill_fasync(ptrptr,sig,band) kill_fasync(*(ptrptr),(sig)) +#endif + +/* other things that are virtualized: define the new functions for the old k */ +#ifdef LINUX_20 +# define in_interrupt() (intr_count!=0) +# define mdelay(x) udelay((x)*1000) +# define signal_pending(current) ((current)->signal & ~(current)->blocked) +#endif + +#ifdef LINUX_PCI_H /* only if PCI stuff is being used */ +# ifdef LINUX_20 +# include "pci-compat.h" /* a whole set of replacement functions */ +# else +# define pci_release_device(d) /* placeholder, used in 2.0 to free stuff */ +# endif +#endif + + + +/* + * Some task state stuff + */ + +#ifndef set_current_state +# define set_current_state(s) current->state = (s); +#endif + +#ifdef LINUX_20 +extern inline void schedule_timeout(int timeout) +{ + current->timeout = jiffies + timeout; + current->state = TASK_INTERRUPTIBLE; + schedule(); + current->timeout = 0; +} + +extern inline long sleep_on_timeout(wait_queue_head_t *q, signed long timeout) +{ + signed long early = 0; + + current->timeout = jiffies + timeout; + sleep_on (q); + if (current->timeout > 0) { + early = current->timeout - jiffies; + current->timeout = 0; + } + return early; +} + + +extern inline long interruptible_sleep_on_timeout(wait_queue_head_t *q, + signed long timeout) +{ + signed long early = 0; + + current->timeout = jiffies + timeout; + interruptible_sleep_on (q); + if (current->timeout > 0) { + early = current->timeout - jiffies; + current->timeout = 0; + } + return early; +} + +#endif /* LINUX_20 */ + +/* + * Schedule_task was a late 2.4 addition. + */ +#ifndef LINUX_24 +extern inline int schedule_task(struct tq_struct *task) +{ + queue_task(task, &tq_scheduler); + return 1; +} +#endif + + +/* + * Timing issues + */ +#ifdef LINUX_20 +# define get_fast_time do_gettimeofday +#endif + +#ifdef _LINUX_DELAY_H /* only if linux/delay.h is included */ +# ifndef mdelay /* linux-2.0 */ +# ifndef MAX_UDELAY_MS +# define MAX_UDELAY_MS 5 +# endif +# define mdelay(n) (\ + (__builtin_constant_p(n) && (n)<=MAX_UDELAY_MS) ? udelay((n)*1000) : \ + ({unsigned long msec=(n); while (msec--) udelay(1000);})) +# endif /* mdelay */ +#endif /* _LINUX_DELAY_H */ + + +/* + * No del_timer_sync before 2.4 + */ +#ifndef LINUX_24 +# define del_timer_sync(timer) del_timer(timer) /* and hope */ +#endif + +/* + * mod_timer wasn't present in 2.0 + */ +#ifdef LINUX_20 +static inline int mod_timer(struct timer_list *timer, unsigned long expires) +{ + int pending = del_timer(timer); + if (pending) { + timer->expires = expires; + add_timer(timer); + } + return pending; +} +#endif +/* + * Various changes in mmap and friends. + */ + +#ifndef NOPAGE_SIGBUS +# define NOPAGE_SIGBUS NULL /* return value of the nopage memory method */ +# define NOPAGE_OOM NULL /* No real equivalent in older kernels */ +#endif + +#ifndef VM_RESERVED /* Added 2.4.0-test10 */ +# define VM_RESERVED 0 +#endif + +#ifdef LINUX_24 /* use "vm_pgoff" to get an offset */ +#define VMA_OFFSET(vma) ((vma)->vm_pgoff << PAGE_SHIFT) +#else /* use "vm_offset" */ +#define VMA_OFFSET(vma) ((vma)->vm_offset) +#endif + +#ifdef MAP_NR +#define virt_to_page(page) (mem_map + MAP_NR(page)) +#endif + +#ifndef get_page +# define get_page(p) atomic_inc(&(p)->count) +#endif + +/* + * No DMA lock in 2.0. + */ +#ifdef LINUX_20 +static inline unsigned long claim_dma_lock(void) +{ + unsigned long flags; + save_flags(flags); + cli(); + return flags; +} + +static inline void release_dma_lock(unsigned long flags) +{ + restore_flags(flags); +} +#endif + + +/* + * I/O memory was not managed by ealier kernels, define them as success + */ + +#if 0 /* FIXME: what is the right way to do request_mem_region? */ +#ifndef LINUX_24 +# define check_mem_region(start, len) 0 +# define request_mem_region(start, len, name) 0 +# define release_mem_region(start, len) 0 + + /* + * Also, request_ and release_ region used to return void. Return 0 instead + */ +# define request_region(s, l, n) ({request_region((s),(l),(n));0;}) +# define release_region(s, l) ({release_region((s),(l));0;}) + +#endif /* not LINUX_24 */ +#endif + +/* + * Block layer stuff. + */ +#ifndef LINUX_24 + +/* BLK_DEFAULT_QUEUE for use with these macros only!!!! */ +#define BLK_DEFAULT_QUEUE(major) blk_dev[(major)].request_fn +#define blk_init_queue(where,request_fn) where = request_fn; +#define blk_cleanup_queue(where) where = NULL; + +/* No QUEUE_EMPTY in older kernels */ +#ifndef QUEUE_EMPTY /* Driver can redefine it too */ +# define QUEUE_EMPTY (CURRENT != NULL) +#endif + +#ifdef RO_IOCTLS +static inline int blk_ioctl(kdev_t dev, unsigned int cmd, unsigned long arg) +{ + int err; + + switch (cmd) { + case BLKRAGET: /* return the readahead value */ + if (!arg) return -EINVAL; + err = ! access_ok(VERIFY_WRITE, arg, sizeof(long)); + if (err) return -EFAULT; + PUT_USER(read_ahead[MAJOR(dev)],(long *) arg); + return 0; + + case BLKRASET: /* set the readahead value */ + if (!capable(CAP_SYS_ADMIN)) return -EACCES; + if (arg > 0xff) return -EINVAL; /* limit it */ + read_ahead[MAJOR(dev)] = arg; + return 0; + + case BLKFLSBUF: /* flush */ + if (! capable(CAP_SYS_ADMIN)) return -EACCES; /* only root */ + fsync_dev(dev); + invalidate_buffers(dev); + return 0; + + RO_IOCTLS(dev, arg); + } + return -ENOTTY; +} +#endif /* RO_IOCTLS */ + +#ifdef LINUX_EXTENDED_PARTITION /* defined in genhd.h */ +static inline void register_disk(struct gendisk *gdev, kdev_t dev, + unsigned minors, struct file_operations *ops, long size) +{ + if (! gdev) + return; + resetup_one_dev(gdev, MINOR(dev) >> gdev->minor_shift); +} +#endif /* LINUX_EXTENDED_PARTITION */ + + +#else /* it is Linux 2.4 */ +#define HAVE_BLKPG_H +#endif /* LINUX_24 */ + + + +#ifdef LINUX_20 /* physical and virtual addresses had the same value */ +# define __pa(a) (a) +# define __va(a) (a) +#endif + +/* + * Network driver compatibility + */ + +/* + * 2.0 dev_kfree_skb had an extra arg. The following is a little dangerous + * in that it assumes that FREE_WRITE is always wanted. Very few 2.0 drivers + * use FREE_READ, but the number is *not* zero... + * + * Also: implement the non-checking versions of a couple skb functions - + * but they still check in 2.0. + */ +#ifdef LINUX_20 +# define dev_kfree_skb(skb) dev_kfree_skb((skb), FREE_WRITE); + +# define __skb_push(skb, len) skb_push((skb), (len)) +# define __skb_put(skb, len) skb_put((skb), (len)) +#endif + +/* + * Softnet changes in 2.4 + */ +#ifndef LINUX_24 +# ifdef _LINUX_NETDEVICE_H /* only if netdevice.h was included */ +# define netif_start_queue(dev) clear_bit(0, (void *) &(dev)->tbusy); +# define netif_stop_queue(dev) set_bit(0, (void *) &(dev)->tbusy); + +static inline void netif_wake_queue(struct device *dev) +{ + clear_bit(0, (void *) &(dev)->tbusy); + mark_bh(NET_BH); +} + +/* struct device became struct net_device */ +# define net_device device +# endif /* netdevice.h */ +#endif /* ! LINUX_24 */ + +/* + * Memory barrier stuff, define what's missing from older kernel versions + */ +#ifdef switch_to /* this is always a macro, defined in */ + +# ifndef set_mb +# define set_mb(var, value) do {(var) = (value); mb();} while 0 +# endif +# ifndef set_rmb +# define set_rmb(var, value) do {(var) = (value); rmb();} while 0 +# endif +# ifndef set_wmb +# define set_wmb(var, value) do {(var) = (value); wmb();} while 0 +# endif + +/* The hw barriers are defined as sw barriers. A correct thing if this + specific kernel/platform is supported but has no specific instruction */ +# ifndef mb +# define mb barrier +# endif +# ifndef rmb +# define rmb barrier +# endif +# ifndef wmb +# define wmb barrier +# endif + +#endif /* switch to (i.e. ) */ + + +#endif /* _SYSDEP_H_ */ -- cgit v1.2.3 From ae7fd7b818e728fd90e08460dd45ce81e79c99b0 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 18 Dec 2009 11:05:25 -0800 Subject: Staging: dt3155: add needed #include This is needed so the code properly builds Cc: Scott Smedley Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dt3155/dt3155_drv.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/staging/dt3155/dt3155_drv.c b/drivers/staging/dt3155/dt3155_drv.c index f3ae8e82d64e..3efdeb9953ff 100644 --- a/drivers/staging/dt3155/dt3155_drv.c +++ b/drivers/staging/dt3155/dt3155_drv.c @@ -76,6 +76,7 @@ MODULE_LICENSE("GPL"); #include #include #include +#include #include #include -- cgit v1.2.3 From bad9f950c011c50e8302b48244229c0250add9b4 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 18 Dec 2009 11:06:11 -0800 Subject: Staging: dt3155: add TODO file Cc: Scott Smedley Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dt3155/TODO | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 drivers/staging/dt3155/TODO (limited to 'drivers') diff --git a/drivers/staging/dt3155/TODO b/drivers/staging/dt3155/TODO new file mode 100644 index 000000000000..3baa3b6294cc --- /dev/null +++ b/drivers/staging/dt3155/TODO @@ -0,0 +1,10 @@ +TODO: + - fix checkpatch.pl issues + - remove old kernel support, it is not needed + - convert to proper PCI device API + - fix sparse warnings + - audit for correct subsystem interaction + - review review review! + +Please send patches to Greg Kroah-Hartman +and Scott Smedley -- cgit v1.2.3 From 293c0db0dd2a7f1a8074645faa9d3a0294623002 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 18 Dec 2009 11:04:54 -0800 Subject: Staging: dt3155: add it to the build Now it will build with the rest of the kernel Cc: Scott Smedley Signed-off-by: Greg Kroah-Hartman --- drivers/staging/Kconfig | 2 ++ drivers/staging/Makefile | 1 + drivers/staging/dt3155/Kconfig | 4 ++++ drivers/staging/dt3155/Makefile | 33 ++++++--------------------------- 4 files changed, 13 insertions(+), 27 deletions(-) create mode 100644 drivers/staging/dt3155/Kconfig (limited to 'drivers') diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index fc2e963e65e9..02cde3989c5c 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -143,5 +143,7 @@ source "drivers/staging/netwave/Kconfig" source "drivers/staging/sm7xx/Kconfig" +source "drivers/staging/dt3155/Kconfig" + endif # !STAGING_EXCLUDE_BUILD endif # STAGING diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index b5e67b889f60..9d47d42e73ce 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -53,3 +53,4 @@ obj-$(CONFIG_WAVELAN) += wavelan/ obj-$(CONFIG_PCMCIA_WAVELAN) += wavelan/ obj-$(CONFIG_PCMCIA_NETWAVE) += netwave/ obj-$(CONFIG_FB_SM7XX) += sm7xx/ +obj-$(CONFIG_DT3155) += dt3155/ diff --git a/drivers/staging/dt3155/Kconfig b/drivers/staging/dt3155/Kconfig new file mode 100644 index 000000000000..4a3293c721b1 --- /dev/null +++ b/drivers/staging/dt3155/Kconfig @@ -0,0 +1,4 @@ +config DT3155 + tristate "DT3155 Digitizer support" + depends on PCI + diff --git a/drivers/staging/dt3155/Makefile b/drivers/staging/dt3155/Makefile index 1717ffbf682f..136f21fdbbee 100644 --- a/drivers/staging/dt3155/Makefile +++ b/drivers/staging/dt3155/Makefile @@ -1,27 +1,6 @@ - -ifeq ($(shell [[ `uname -r | cut -f 1,2 -d\.` < 2.6 ]] && echo pre2.6),pre2.6) -# system with a pre 2.6 kernel _don't_ use kbuild. -all: - $(MAKE) -f Makefile.pre-2.6 - -clean: - rm -f *.o - -else -# systems with a 2.6 or later kernel use kbuild. -ifneq ($(KERNELRELEASE),) -obj-m := dt3155.o -dt3155-objs := dt3155_drv.o dt3155_isr.o dt3155_io.o allocator.o - -else -KDIR := /lib/modules/$(shell uname -r)/build -PWD := $(shell pwd) - -all: - $(MAKE) -C $(KDIR) M=$(PWD) modules - -clean: - rm -rf *.o *.mod *.mod.c *.ko .dt3155* .allocator.o.cmd .tmp_versions - -endif -endif +obj-$(CONFIG_DT3155) += dt3155.o +dt3155-objs := \ + dt3155_drv.o \ + dt3155_isr.o \ + dt3155_io.o \ + allocator.o -- cgit v1.2.3 From 59277b679f8b5ce594e367759256668eba652d0d Mon Sep 17 00:00:00 2001 From: Bernie Thompson Date: Tue, 24 Nov 2009 15:52:21 -0800 Subject: Staging: udlfb: add dynamic modeset support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add dynamic modeset support udlfb uses EDID to find the monitor’s preferred mode udlfb no longer has fixed mode tables – it’s able to set any mode dynamically, from the standard VESA timing characteristics of the monitor. Draws from probe and setmode code of both displaylink-mod 0.3 branch of Roberto De Ioris, and Jaya Kumar's displaylinkfb. Lays foundation for defio support and making backbuffer optional. With additional changes to minimize diffs and clean for checkpatch.pl style. Does not yet include new ioctls or refcount/mutex code from displaylink-mod. Tested to work with existing xf-video-displaylink X server unmodified. Signed-off-by: Bernie Thompson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/udlfb/udlfb.c | 652 +++++++++++++++++++++++++++++------------- drivers/staging/udlfb/udlfb.h | 156 +--------- 2 files changed, 451 insertions(+), 357 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/udlfb/udlfb.c b/drivers/staging/udlfb/udlfb.c index f5416af1e902..b61a3e58a9ec 100644 --- a/drivers/staging/udlfb/udlfb.c +++ b/drivers/staging/udlfb/udlfb.c @@ -1,17 +1,19 @@ -/***************************************************************************** - * DLFB Kernel Driver * - * Version 0.2 (udlfb) * - * (C) 2009 Roberto De Ioris * - * * - * This file is licensed under the GPLv2. See COPYING in the package. * - * Based on the amazing work of Florian Echtler and libdlo 0.1 * - * * - * * - * 10.06.09 release 0.2.3 (edid ioctl, fallback for unsupported modes) * - * 05.06.09 release 0.2.2 (real screen blanking, rle compression, double buffer) * - * 31.05.09 release 0.2 * - * 22.05.09 First public (ugly) release * - *****************************************************************************/ +/* + * udlfb.c -- Framebuffer driver for DisplayLink USB controller + * + * Copyright (C) 2009 Roberto De Ioris + * Copyright (C) 2009 Jaya Kumar + * + * This file is subject to the terms and conditions of the GNU General Public + * License v2. See the file COPYING in the main directory of this archive for + * more details. + * + * Layout is based on skeletonfb by James Simmons and Geert Uytterhoeven, + * usb-skeleton by GregKH. + * + * Device-specific portions based on information from Displaylink, with work + * from Florian Echtler, Henrik Bjerregaard Pedersen, and others. + */ #include #include @@ -25,45 +27,263 @@ #include "udlfb.h" -#define DRIVER_VERSION "DLFB 0.2" +#define DRIVER_VERSION "DisplayLink Framebuffer Driver 0.4.1" + +static struct fb_fix_screeninfo dlfb_fix = { + .id = "displaylinkfb", + .type = FB_TYPE_PACKED_PIXELS, + .visual = FB_VISUAL_TRUECOLOR, + .xpanstep = 0, + .ypanstep = 0, + .ywrapstep = 0, + .accel = FB_ACCEL_NONE, +}; -/* memory functions taken from vfb */ +#define NR_USB_REQUEST_I2C_SUB_IO 0x02 +#define NR_USB_REQUEST_CHANNEL 0x12 -static void *rvmalloc(unsigned long size) +/* + * Inserts a specific DisplayLink controller command into the provided + * buffer. + */ +static char *insert_command(char *buf, u8 reg, u8 val) { - void *mem; - unsigned long adr; + *buf++ = 0xAF; + *buf++ = 0x20; + *buf++ = reg; + *buf++ = val; + return buf; +} - size = PAGE_ALIGN(size); - mem = vmalloc_32(size); - if (!mem) - return NULL; +static char *insert_vidreg_lock(char *buf) +{ + return insert_command(buf, 0xFF, 0x00); +} - memset(mem, 0, size); /* Clear the ram out, no junk to the user */ - adr = (unsigned long)mem; - while (size > 0) { - SetPageReserved(vmalloc_to_page((void *)adr)); - adr += PAGE_SIZE; - size -= PAGE_SIZE; +static char *insert_vidreg_unlock(char *buf) +{ + return insert_command(buf, 0xFF, 0xFF); +} + +/* + * Once you send this command, the DisplayLink framebuffer gets driven to the + * display. + */ +static char *insert_enable_hvsync(char *buf) +{ + return insert_command(buf, 0x1F, 0x00); +} + +static char *insert_set_color_depth(char *buf, u8 selection) +{ + return insert_command(buf, 0x00, selection); +} + +static char *insert_set_base16bpp(char *wrptr, u32 base) +{ + /* the base pointer is 16 bits wide, 0x20 is hi byte. */ + wrptr = insert_command(wrptr, 0x20, base >> 16); + wrptr = insert_command(wrptr, 0x21, base >> 8); + return insert_command(wrptr, 0x22, base); +} + +static char *insert_set_base8bpp(char *wrptr, u32 base) +{ + wrptr = insert_command(wrptr, 0x26, base >> 16); + wrptr = insert_command(wrptr, 0x27, base >> 8); + return insert_command(wrptr, 0x28, base); +} + +static char *insert_command_16(char *wrptr, u8 reg, u16 value) +{ + wrptr = insert_command(wrptr, reg, value >> 8); + return insert_command(wrptr, reg+1, value); +} + +/* + * This is kind of weird because the controller takes some + * register values in a different byte order than other registers. + */ +static char *insert_command_16be(char *wrptr, u8 reg, u16 value) +{ + wrptr = insert_command(wrptr, reg, value); + return insert_command(wrptr, reg+1, value >> 8); +} + +/* + * LFSR is linear feedback shift register. The reason we have this is + * because the display controller needs to minimize the clock depth of + * various counters used in the display path. So this code reverses the + * provided value into the lfsr16 value by counting backwards to get + * the value that needs to be set in the hardware comparator to get the + * same actual count. This makes sense once you read above a couple of + * times and think about it from a hardware perspective. + */ +static u16 lfsr16(u16 actual_count) +{ + u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */ + + while (actual_count--) { + lv = ((lv << 1) | + (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1)) + & 0xFFFF; } - return mem; + return (u16) lv; +} + +/* + * This does LFSR conversion on the value that is to be written. + * See LFSR explanation above for more detail. + */ +static char *insert_command_lfsr16(char *wrptr, u8 reg, u16 value) +{ + return insert_command_16(wrptr, reg, lfsr16(value)); } -static void rvfree(void *mem, unsigned long size) +/* + * This takes a standard fbdev screeninfo struct and all of its monitor mode + * details and converts them into the DisplayLink equivalent register commands. + */ +static char *insert_set_vid_cmds(char *wrptr, struct fb_var_screeninfo *var) { - unsigned long adr; + u16 xds, yds; + u16 xde, yde; + u16 yec; + + + /* x display start */ + xds = var->left_margin + var->hsync_len; + wrptr = insert_command_lfsr16(wrptr, 0x01, xds); + /* x display end */ + xde = xds + var->xres; + wrptr = insert_command_lfsr16(wrptr, 0x03, xde); + + /* y display start */ + yds = var->upper_margin + var->vsync_len; + wrptr = insert_command_lfsr16(wrptr, 0x05, yds); + /* y display end */ + yde = yds + var->yres; + wrptr = insert_command_lfsr16(wrptr, 0x07, yde); + + /* x end count is active + blanking - 1 */ + wrptr = insert_command_lfsr16(wrptr, 0x09, xde + var->right_margin - 1); + + /* libdlo hardcodes hsync start to 1 */ + wrptr = insert_command_lfsr16(wrptr, 0x0B, 1); + + /* hsync end is width of sync pulse + 1 */ + wrptr = insert_command_lfsr16(wrptr, 0x0D, var->hsync_len + 1); + + /* hpixels is active pixels */ + wrptr = insert_command_16(wrptr, 0x0F, var->xres); - if (!mem) - return; + /* yendcount is vertical active + vertical blanking */ + yec = var->yres + var->upper_margin + var->lower_margin + + var->vsync_len; + wrptr = insert_command_lfsr16(wrptr, 0x11, yec); - adr = (unsigned long)mem; - while ((long)size > 0) { - ClearPageReserved(vmalloc_to_page((void *)adr)); - adr += PAGE_SIZE; - size -= PAGE_SIZE; + /* libdlo hardcodes vsync start to 0 */ + wrptr = insert_command_lfsr16(wrptr, 0x13, 0); + + /* vsync end is width of vsync pulse */ + wrptr = insert_command_lfsr16(wrptr, 0x15, var->vsync_len); + + /* vpixels is active pixels */ + wrptr = insert_command_16(wrptr, 0x17, var->yres); + + /* convert picoseconds to 5kHz multiple for pclk5k = x * 1E12/5k */ + wrptr = insert_command_16be(wrptr, 0x1B, 200*1000*1000/var->pixclock); + + return wrptr; +} + +/* + * This takes a standard fbdev screeninfo struct that was fetched or prepared + * and then generates the appropriate command sequence that then drives the + * display controller. + */ +static int dlfb_set_video_mode(struct dlfb_data *dev, + struct fb_var_screeninfo *var) +{ + char *buf; + char *wrptr; + int retval = 0; + int writesize; + + buf = dev->buf; + + /* + * This first section has to do with setting the base address on the + * controller * associated with the display. There are 2 base + * pointers, currently, we only * use the 16 bpp segment. + */ + wrptr = insert_vidreg_lock(buf); + wrptr = insert_set_color_depth(wrptr, 0x00); + /* set base for 16bpp segment to 0 */ + wrptr = insert_set_base16bpp(wrptr, 0); + /* set base for 8bpp segment to end of fb */ + wrptr = insert_set_base8bpp(wrptr, dev->info->fix.smem_len); + + wrptr = insert_set_vid_cmds(wrptr, var); + wrptr = insert_enable_hvsync(wrptr); + wrptr = insert_vidreg_unlock(wrptr); + + writesize = wrptr - buf; + + mutex_lock(&dev->bulk_mutex); + if (!dev->interface) { /* disconnect() was called */ + mutex_unlock(&dev->bulk_mutex); + retval = -ENODEV; + goto error; } - vfree(mem); + + retval = dlfb_bulk_msg(dev, writesize); + mutex_unlock(&dev->bulk_mutex); + if (retval) { + dev_err(&dev->udev->dev, "Problem %d with submit write bulk.\n", + retval); + goto error; + } + + return 0; + +error: + return retval; +} + +/* + * This is necessary before we can communicate with the display controller. + */ +static int dlfb_select_std_channel(struct dlfb_data *dev) +{ + int ret; + u8 set_def_chn[] = { 0x57, 0xCD, 0xDC, 0xA7, + 0x1C, 0x88, 0x5E, 0x15, + 0x60, 0xFE, 0xC6, 0x97, + 0x16, 0x3D, 0x47, 0xF2 }; + + ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), + NR_USB_REQUEST_CHANNEL, + (USB_DIR_OUT | USB_TYPE_VENDOR), 0, 0, + set_def_chn, sizeof(set_def_chn), USB_CTRL_SET_TIMEOUT); + return ret; +} + + +/* + * Query EDID from the handware, then hand it off to fbdev's edid parse + * routine which should give us back a filled in screeninfo structure. + */ +static int dlfb_get_var_from_edid(struct dlfb_data *dev, + struct fb_var_screeninfo *var) +{ + int ret; + + dlfb_edid(dev); + ret = fb_parse_edid(dev->edid, var); + + return ret; } static int dlfb_mmap(struct fb_info *info, struct vm_area_struct *vma) @@ -106,12 +326,11 @@ struct dloarea { }; /* -static struct usb_device_id id_table [] = { - { USB_DEVICE(0x17e9, 0x023d) }, - { } -}; -*/ - + * There are many DisplayLink-based products, all with unique PIDs. We are able + * to support all volume ones (circa 2009) with a single driver, so we match + * globally on VID. TODO: Probe() needs to detect when we might be running + * "future" chips, and bail on those, so a compatible driver can match. + */ static struct usb_device_id id_table[] = { {.idVendor = 0x17e9, .match_flags = USB_DEVICE_ID_MATCH_VENDOR,}, {}, @@ -205,14 +424,21 @@ image_blit(struct dlfb_data *dev_info, int x, int y, int width, int height, if (thistime > 255) thistime = 255; - // find position of first pixel that has changed - firstdiff = -1; - for (j = 0; j < thistime * 2; j++) { - if (dev_info->backing_buffer - [base - dev_info->base16 + j] != data[j]) { - firstdiff = j / 2; - break; + if (dev_info->backing_buffer) { + /* find first pixel that has changed */ + firstdiff = -1; + for (j = 0; j < thistime * 2; j++) { + if (dev_info->backing_buffer + [base - dev_info->base16 + j] + != data[j]) { + firstdiff = j / 2; + break; + } } + + } else { + firstdiff = 0; + } if (firstdiff >= 0) { @@ -267,8 +493,10 @@ image_blit(struct dlfb_data *dev_info, int x, int y, int width, int height, rem -= thistime; } - memcpy(dev_info->backing_buffer + (base - dev_info->base16) - - (width * 2), data - (width * 2), width * 2); + if (dev_info->backing_buffer) + memcpy(dev_info->backing_buffer + + (base - dev_info->base16) - + (width * 2), data - (width * 2), width * 2); base += (dev_info->info->var.xres * 2) - (width * 2); data += (dev_info->info->var.xres * 2) - (width * 2); @@ -313,12 +541,17 @@ draw_rect(struct dlfb_data *dev_info, int x, int y, int width, int height, for (i = y; i < y + height; i++) { - for (j = 0; j < width * 2; j += 2) { - dev_info->backing_buffer[base - dev_info->base16 + j] = - (char)(col >> 8); - dev_info->backing_buffer[base - dev_info->base16 + j + - 1] = (char)(col); + if (dev_info->backing_buffer) { + for (j = 0; j < width * 2; j += 2) { + dev_info->backing_buffer + [base - dev_info->base16 + j] = + (char)(col >> 8); + dev_info->backing_buffer + [base - dev_info->base16 + j + 1] = + (char)(col); + } } + if (dev_info->bufend - bufptr < BUF_HIGH_WATER_MARK) { ret = dlfb_bulk_msg(dev_info, bufptr - dev_info->buf); bufptr = dev_info->buf; @@ -725,182 +958,196 @@ static struct fb_ops dlfb_ops = { .fb_blank = dlfb_blank, }; -static int -dlfb_probe(struct usb_interface *interface, const struct usb_device_id *id) +static int dlfb_probe(struct usb_interface *interface, + const struct usb_device_id *id) { - struct dlfb_data *dev_info; + struct device *mydev; + struct usb_device *usbdev; + struct dlfb_data *dev; struct fb_info *info; - - int ret; - char rbuf[4]; - - dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); - if (dev_info == NULL) { - printk("cannot allocate dev_info structure.\n"); - return -ENOMEM; - } - - mutex_init(&dev_info->bulk_mutex); - - dev_info->udev = usb_get_dev(interface_to_usbdev(interface)); - dev_info->interface = interface; - - printk("DisplayLink device attached\n"); - - /* add framebuffer info to usb interface */ - usb_set_intfdata(interface, dev_info); - - dev_info->buf = kmalloc(BUF_SIZE, GFP_KERNEL); - /* usb_buffer_alloc(dev_info->udev, BUF_SIZE , GFP_KERNEL, &dev_info->tx_urb->transfer_dma); */ - - if (dev_info->buf == NULL) { - printk("unable to allocate memory for dlfb commands\n"); - goto out; + int videomemorysize; + unsigned char *videomemory; + int retval = -ENOMEM; + struct fb_var_screeninfo *var; + struct fb_bitfield red = { 11, 5, 0 }; + struct fb_bitfield green = { 5, 6, 0 }; + struct fb_bitfield blue = { 0, 5, 0 }; + + usbdev = usb_get_dev(interface_to_usbdev(interface)); + mydev = &usbdev->dev; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (dev == NULL) { + dev_err(mydev, "failed alloc of dev struct\n"); + goto err_devalloc; } - dev_info->bufend = dev_info->buf + BUF_SIZE; - - dev_info->tx_urb = usb_alloc_urb(0, GFP_KERNEL); - usb_fill_bulk_urb(dev_info->tx_urb, dev_info->udev, - usb_sndbulkpipe(dev_info->udev, 1), dev_info->buf, 0, - dlfb_bulk_callback, dev_info); - - ret = - usb_control_msg(dev_info->udev, usb_rcvctrlpipe(dev_info->udev, 0), - (0x06), (0x80 | (0x02 << 5)), 0, 0, rbuf, 4, 0); - printk("ret control msg 0: %d %x%x%x%x\n", ret, rbuf[0], rbuf[1], - rbuf[2], rbuf[3]); - dlfb_edid(dev_info); - - info = framebuffer_alloc(sizeof(u32) * 256, &dev_info->udev->dev); - - if (!info) { - printk("non posso allocare il framebuffer displaylink"); - goto out; + mutex_init(&dev->bulk_mutex); + dev->udev = usbdev; + dev->interface = interface; + usb_set_intfdata(interface, dev); + + dev_info(mydev, "dlfb_probe: setting up DisplayLink device\n"); + + /* + * TODO: replace single 64K buffer with buffer list + * and async dispatch + */ + dev->buf = kmalloc(BUF_SIZE, GFP_KERNEL); + if (dev->buf == NULL) { + dev_err(mydev, "unable to allocate memory for dlfb commands\n"); + goto err_usballoc; } - - fb_parse_edid(dev_info->edid, &info->var); - - printk("EDID XRES %d YRES %d\n", info->var.xres, info->var.yres); - - if (dlfb_set_video_mode(dev_info, info->var.xres, info->var.yres) != 0) { - info->var.xres = 1280; - info->var.yres = 1024; - if (dlfb_set_video_mode - (dev_info, info->var.xres, info->var.yres) != 0) { - goto out; - } + dev->bufend = dev->buf + BUF_SIZE; + + dev->tx_urb = usb_alloc_urb(0, GFP_KERNEL); + usb_fill_bulk_urb(dev->tx_urb, dev->udev, + usb_sndbulkpipe(dev->udev, 1), dev->buf, 0, + dlfb_bulk_callback, dev); + + /* allocates framebuffer driver structure, not framebuffer memory */ + info = framebuffer_alloc(0, mydev); + if (!info) + goto err_fballoc; + + dev->info = info; + info->par = dev; + info->pseudo_palette = dev->pseudo_palette; + + var = &info->var; + retval = dlfb_get_var_from_edid(dev, var); + if (retval) { + /* had a problem getting edid. so fallback to 640x480 */ + dev_err(mydev, "Problem %d with EDID.\n", retval); + var->xres = 640; + var->yres = 480; } - printk("found valid mode...%d\n", info->var.pixclock); - - info->pseudo_palette = info->par; - info->par = dev_info; - - dev_info->info = info; - + /* + * ok, now that we've got the size info, we can alloc our framebuffer. + * We are using 16bpp. + */ + info->var.bits_per_pixel = 16; + info->fix = dlfb_fix; + info->fix.line_length = var->xres * (var->bits_per_pixel / 8); + videomemorysize = info->fix.line_length * var->yres; + + /* + * The big chunk of system memory we use as a virtual framebuffer. + * Pages don't need to be set RESERVED (non-swap) immediately on 2.6 + * remap_pfn_page() syscall in our mmap and/or defio will handle. + */ + videomemory = vmalloc(videomemorysize); + if (!videomemory) + goto err_vidmem; + memset(videomemory, 0, videomemorysize); + + info->screen_base = videomemory; + info->fix.smem_len = PAGE_ALIGN(videomemorysize); + info->fix.smem_start = (unsigned long) videomemory; info->flags = FBINFO_DEFAULT | FBINFO_READS_FAST | FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT; - info->fbops = &dlfb_ops; - info->screen_base = rvmalloc(dev_info->screen_size); - if (info->screen_base == NULL) { - printk - ("cannot allocate framebuffer virtual memory of %d bytes\n", - dev_info->screen_size); - goto out0; - } - - printk("screen base allocated !!!\n"); - - dev_info->backing_buffer = kzalloc(dev_info->screen_size, GFP_KERNEL); - - if (!dev_info->backing_buffer) - printk("non posso allocare il backing buffer\n"); + /* + * Second framebuffer copy, mirroring the state of the framebuffer + * on the physical USB device. We can function without this. + * But with imperfect damage info we may end up sending pixels over USB + * that were, in fact, unchanged -- wasting limited USB bandwidth + */ + dev->backing_buffer = vmalloc(dev->screen_size); + if (!dev->backing_buffer) + dev_info(mydev, "No backing buffer allocated!\n"); - /* info->var = dev_info->si; */ - - info->var.bits_per_pixel = 16; - info->var.activate = FB_ACTIVATE_TEST; - info->var.vmode = FB_VMODE_NONINTERLACED; + info->fbops = &dlfb_ops; - info->var.red.offset = 11; - info->var.red.length = 5; - info->var.red.msb_right = 0; + var->vmode = FB_VMODE_NONINTERLACED; + var->red = red; + var->green = green; + var->blue = blue; - info->var.green.offset = 5; - info->var.green.length = 6; - info->var.green.msb_right = 0; + /* + * TODO: Enable FB_CONFIG_DEFIO support - info->var.blue.offset = 0; - info->var.blue.length = 5; - info->var.blue.msb_right = 0; + info->fbdefio = &dlfb_defio; + fb_deferred_io_init(info); - /* info->var.pixclock = (10000000 / FB_W * 1000 / FB_H)/2 ; */ + */ - info->fix.smem_start = (unsigned long)info->screen_base; - info->fix.smem_len = PAGE_ALIGN(dev_info->screen_size); - if (strlen(dev_info->udev->product) > 15) { - memcpy(info->fix.id, dev_info->udev->product, 15); - } else { - memcpy(info->fix.id, dev_info->udev->product, - strlen(dev_info->udev->product)); + retval = fb_alloc_cmap(&info->cmap, 256, 0); + if (retval < 0) { + dev_err(mydev, "Failed to allocate colormap\n"); + goto err_cmap; } - info->fix.type = FB_TYPE_PACKED_PIXELS; - info->fix.visual = FB_VISUAL_TRUECOLOR; - info->fix.accel = info->flags; - info->fix.line_length = dev_info->line_length; - if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) - goto out1; + dlfb_select_std_channel(dev); + dlfb_set_video_mode(dev, var); + /* TODO: dlfb_dpy_update(dev); */ - printk("colormap allocated\n"); - if (register_framebuffer(info) < 0) - goto out2; + retval = register_framebuffer(info); + if (retval < 0) + goto err_regfb; - draw_rect(dev_info, 0, 0, dev_info->info->var.xres, - dev_info->info->var.yres, 0x30, 0xff, 0x30); + /* paint "successful" green screen */ + draw_rect(dev, 0, 0, dev->info->var.xres, + dev->info->var.yres, 0x30, 0xff, 0x30); + dev_info(mydev, "DisplayLink USB device %d now attached, " + "using %dK of memory\n", info->node, + ((dev->backing_buffer) ? + videomemorysize * 2 : videomemorysize) >> 10); return 0; -out2: +err_regfb: fb_dealloc_cmap(&info->cmap); -out1: - rvfree(info->screen_base, dev_info->screen_size); -out0: +err_cmap: + /* TODO: fb_deferred_io_cleanup(info); */ + vfree(videomemory); +err_vidmem: framebuffer_release(info); -out: +err_fballoc: + kfree(dev->buf); +err_usballoc: usb_set_intfdata(interface, NULL); - usb_put_dev(dev_info->udev); - kfree(dev_info); - return -ENOMEM; - + usb_put_dev(dev->udev); + kfree(dev); +err_devalloc: + return retval; } static void dlfb_disconnect(struct usb_interface *interface) { - struct dlfb_data *dev_info = usb_get_intfdata(interface); - - mutex_unlock(&dev_info->bulk_mutex); + struct dlfb_data *dev; + struct fb_info *info; - usb_kill_urb(dev_info->tx_urb); - usb_free_urb(dev_info->tx_urb); + dev = usb_get_intfdata(interface); usb_set_intfdata(interface, NULL); - usb_put_dev(dev_info->udev); - - if (dev_info->info) { - unregister_framebuffer(dev_info->info); - fb_dealloc_cmap(&dev_info->info->cmap); - rvfree(dev_info->info->screen_base, dev_info->screen_size); - kfree(dev_info->backing_buffer); - framebuffer_release(dev_info->info); - + usb_put_dev(dev->udev); + + /* + * TODO: since, upon usb disconnect(), usb will cancel in-flight urbs + * and error out any new ones, look at eliminating need for mutex + */ + mutex_lock(&dev->bulk_mutex); + dev->interface = NULL; + info = dev->info; + mutex_unlock(&dev->bulk_mutex); + + if (info) { + dev_info(&interface->dev, "Detaching DisplayLink device %d.\n", + info->node); + unregister_framebuffer(info); + fb_dealloc_cmap(&info->cmap); + /* TODO: fb_deferred_io_cleanup(info); */ + fb_dealloc_cmap(&info->cmap); + vfree((void __force *)info->screen_base); + framebuffer_release(info); } - kfree(dev_info); + if (dev->backing_buffer) + vfree(dev->backing_buffer); - printk("DisplayLink device disconnected\n"); + kfree(dev); } static struct usb_driver dlfb_driver = { @@ -914,8 +1161,6 @@ static int __init dlfb_init(void) { int res; - dlfb_init_modes(); - res = usb_register(&dlfb_driver); if (res) err("usb_register failed. Error number %d", res); @@ -933,6 +1178,7 @@ static void __exit dlfb_exit(void) module_init(dlfb_init); module_exit(dlfb_exit); -MODULE_AUTHOR("Roberto De Ioris "); +MODULE_AUTHOR("Roberto De Ioris , " + "Jaya Kumar "); MODULE_DESCRIPTION(DRIVER_VERSION); MODULE_LICENSE("GPL"); diff --git a/drivers/staging/udlfb/udlfb.h b/drivers/staging/udlfb/udlfb.h index 40ad85ea8e67..cdf91d0d4389 100644 --- a/drivers/staging/udlfb/udlfb.h +++ b/drivers/staging/udlfb/udlfb.h @@ -1,12 +1,6 @@ #ifndef UDLFB_H #define UDLFB_H -#define MAX_VMODES 4 -#define FB_BPP 16 - -#define STD_CHANNEL "\x57\xCD\xDC\xA7\x1C\x88\x5E\x15" \ - "\x60\xFE\xC6\x97\x16\x3D\x47\xF2" - /* as libdlo */ #define BUF_HIGH_WATER_MARK 1024 #define BUF_SIZE (64*1024) @@ -29,21 +23,9 @@ struct dlfb_data { int base16d; int base8; int base8d; + u32 pseudo_palette[256]; }; -struct dlfb_video_mode { - uint8_t col; - uint32_t hclock; - uint32_t vclock; - uint8_t unknown1[6]; - uint16_t xres; - uint8_t unknown2[6]; - uint16_t yres; - uint8_t unknown3[4]; -} __attribute__ ((__packed__)); - -static struct dlfb_video_mode dlfb_video_modes[MAX_VMODES]; - static void dlfb_bulk_callback(struct urb *urb) { struct dlfb_data *dev_info = urb->context; @@ -86,140 +68,6 @@ static int dlfb_bulk_msg(struct dlfb_data *dev_info, int len) return dev_info->tx_urb->actual_length; } -static void dlfb_init_modes(void) -{ - dlfb_video_modes[0].col = 0; - memcpy(&dlfb_video_modes[0].hclock, "\x20\x3C\x7A\xC9", 4); - memcpy(&dlfb_video_modes[0].vclock, "\xF2\x6C\x48\xF9", 4); - memcpy(&dlfb_video_modes[0].unknown1, "\x70\x53\xFF\xFF\x21\x27", 6); - dlfb_video_modes[0].xres = 800; - memcpy(&dlfb_video_modes[0].unknown2, "\x91\xF3\xFF\xFF\xFF\xF9", 6); - dlfb_video_modes[0].yres = 480; - memcpy(&dlfb_video_modes[0].unknown3, "\x01\x02\xC8\x19", 4); - - dlfb_video_modes[1].col = 0; - memcpy(&dlfb_video_modes[1].hclock, "\x36\x18\xD5\x10", 4); - memcpy(&dlfb_video_modes[1].vclock, "\x60\xA9\x7B\x33", 4); - memcpy(&dlfb_video_modes[1].unknown1, "\xA1\x2B\x27\x32\xFF\xFF", 6); - dlfb_video_modes[1].xres = 1024; - memcpy(&dlfb_video_modes[1].unknown2, "\xD9\x9A\xFF\xCA\xFF\xFF", 6); - dlfb_video_modes[1].yres = 768; - memcpy(&dlfb_video_modes[1].unknown3, "\x04\x03\xC8\x32", 4); - - dlfb_video_modes[2].col = 0; - memcpy(&dlfb_video_modes[2].hclock, "\x98\xF8\x0D\x57", 4); - memcpy(&dlfb_video_modes[2].vclock, "\x2A\x55\x4D\x54", 4); - memcpy(&dlfb_video_modes[2].unknown1, "\xCA\x0D\xFF\xFF\x94\x43", 6); - dlfb_video_modes[2].xres = 1280; - memcpy(&dlfb_video_modes[2].unknown2, "\x9A\xA8\xFF\xFF\xFF\xF9", 6); - dlfb_video_modes[2].yres = 1024; - memcpy(&dlfb_video_modes[2].unknown3, "\x04\x02\x60\x54", 4); - - dlfb_video_modes[3].col = 0; - memcpy(&dlfb_video_modes[3].hclock, "\x42\x24\x38\x36", 4); - memcpy(&dlfb_video_modes[3].vclock, "\xC1\x52\xD9\x29", 4); - memcpy(&dlfb_video_modes[3].unknown1, "\xEA\xB8\x32\x60\xFF\xFF", 6); - dlfb_video_modes[3].xres = 1400; - memcpy(&dlfb_video_modes[3].unknown2, "\xC9\x4E\xFF\xFF\xFF\xF2", 6); - dlfb_video_modes[3].yres = 1050; - memcpy(&dlfb_video_modes[3].unknown3, "\x04\x02\x1E\x5F", 4); -} - -static char *dlfb_set_register(char *bufptr, uint8_t reg, uint8_t val) -{ - *bufptr++ = 0xAF; - *bufptr++ = 0x20; - *bufptr++ = reg; - *bufptr++ = val; - - return bufptr; -} - -static int dlfb_set_video_mode(struct dlfb_data *dev_info, int width, int height) -{ - int i, ret; - unsigned char j; - char *bufptr = dev_info->buf; - uint8_t *vdata; - - for (i = 0; i < MAX_VMODES; i++) { - printk("INIT VIDEO %d %d %d\n", i, dlfb_video_modes[i].xres, - dlfb_video_modes[i].yres); - if (dlfb_video_modes[i].xres == width - && dlfb_video_modes[i].yres == height) { - - dev_info->base16 = 0; - dev_info->base16d = width * height * (FB_BPP / 8); - - //dev_info->base8 = width * height * (FB_BPP / 8); - - dev_info->base8 = dev_info->base16; - dev_info->base8d = dev_info->base16d; - - /* set encryption key (null) */ - memcpy(dev_info->buf, STD_CHANNEL, 16); - ret = - usb_control_msg(dev_info->udev, - usb_sndctrlpipe(dev_info->udev, 0), - 0x12, (0x02 << 5), 0, 0, - dev_info->buf, 16, 0); - printk("ret control msg 1 (STD_CHANNEL): %d\n", ret); - - /* set registers */ - bufptr = dlfb_set_register(bufptr, 0xFF, 0x00); - - /* set color depth */ - bufptr = dlfb_set_register(bufptr, 0x00, 0x00); - - /* set addresses */ - bufptr = - dlfb_set_register(bufptr, 0x20, - (char)(dev_info->base16 >> 16)); - bufptr = - dlfb_set_register(bufptr, 0x21, - (char)(dev_info->base16 >> 8)); - bufptr = - dlfb_set_register(bufptr, 0x22, - (char)(dev_info->base16)); - - bufptr = - dlfb_set_register(bufptr, 0x26, - (char)(dev_info->base8 >> 16)); - bufptr = - dlfb_set_register(bufptr, 0x27, - (char)(dev_info->base8 >> 8)); - bufptr = - dlfb_set_register(bufptr, 0x28, - (char)(dev_info->base8)); - - /* set video mode */ - vdata = (uint8_t *)&dlfb_video_modes[i]; - for (j = 0; j < 29; j++) - bufptr = dlfb_set_register(bufptr, j, vdata[j]); - - /* blank */ - bufptr = dlfb_set_register(bufptr, 0x1F, 0x00); - - /* end registers */ - bufptr = dlfb_set_register(bufptr, 0xFF, 0xFF); - - /* send */ - ret = dlfb_bulk_msg(dev_info, bufptr - dev_info->buf); - printk("ret bulk 2: %d %td\n", ret, - bufptr - dev_info->buf); - - /* flush */ - ret = dlfb_bulk_msg(dev_info, 0); - printk("ret bulk 3: %d\n", ret); - - dev_info->screen_size = width * height * (FB_BPP / 8); - dev_info->line_length = width * (FB_BPP / 8); - - return 0; - } - } - - return -1; -} +#define dlfb_set_register insert_command #endif -- cgit v1.2.3 From 2ed71d5a14c887b7632aa21579ff7fc5770381d8 Mon Sep 17 00:00:00 2001 From: Adam Buchbinder Date: Fri, 18 Dec 2009 15:43:50 -0500 Subject: staging: Fix misspelling of "successful" and variants. Some comments and one message misspell "successful" or variants of the word; this fixes them. No change in functionality. Signed-off-by: Adam Buchbinder Signed-off-by: Greg Kroah-Hartman --- drivers/staging/altpciechdma/altpciechdma.c | 2 +- drivers/staging/rt2860/sta/connect.c | 4 ++-- drivers/staging/wlags49_h2/wl_netdev.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/altpciechdma/altpciechdma.c b/drivers/staging/altpciechdma/altpciechdma.c index 2f07dd4563ac..2a02f8e625f7 100644 --- a/drivers/staging/altpciechdma/altpciechdma.c +++ b/drivers/staging/altpciechdma/altpciechdma.c @@ -894,7 +894,7 @@ static int __devinit probe(struct pci_dev *dev, const struct pci_device_id *id) } /* remember which irq we allocated */ ape->irq_line = (int)irq_line; - printk(KERN_DEBUG "Succesfully requested IRQ #%d with dev_id 0x%p\n", irq_line, ape); + printk(KERN_DEBUG "Successfully requested IRQ #%d with dev_id 0x%p\n", irq_line, ape); #endif /* show BARs */ scan_bars(ape, dev); diff --git a/drivers/staging/rt2860/sta/connect.c b/drivers/staging/rt2860/sta/connect.c index 17e59ba3d807..55732b10062d 100644 --- a/drivers/staging/rt2860/sta/connect.c +++ b/drivers/staging/rt2860/sta/connect.c @@ -62,8 +62,8 @@ u8 CipherSuiteWpaNoneAes[] = { u8 CipherSuiteWpaNoneAesLen = (sizeof(CipherSuiteWpaNoneAes) / sizeof(u8)); -/* The following MACRO is called after 1. starting an new IBSS, 2. succesfully JOIN an IBSS, */ -/* or 3. succesfully ASSOCIATE to a BSS, 4. successfully RE_ASSOCIATE to a BSS */ +/* The following MACRO is called after 1. starting an new IBSS, 2. successfully JOIN an IBSS, */ +/* or 3. successfully ASSOCIATE to a BSS, 4. successfully RE_ASSOCIATE to a BSS */ /* All settings successfuly negotiated furing MLME state machines become final settings */ /* and are copied to pAd->StaActive */ #define COPY_SETTINGS_FROM_MLME_AUX_TO_ACTIVE_CFG(_pAd) \ diff --git a/drivers/staging/wlags49_h2/wl_netdev.c b/drivers/staging/wlags49_h2/wl_netdev.c index ac3890247965..6d4019160ebe 100644 --- a/drivers/staging/wlags49_h2/wl_netdev.c +++ b/drivers/staging/wlags49_h2/wl_netdev.c @@ -360,7 +360,7 @@ int wl_open(struct net_device *dev) wl_lock( lp, &flags ); if( status != HCF_SUCCESS ) { - // Unsuccesfull, try reset of the card to recover + // Unsuccessful, try reset of the card to recover status = wl_reset( dev ); } -- cgit v1.2.3 From 39cfb97b0d89a99c8e50782b17e65114b89c2e59 Mon Sep 17 00:00:00 2001 From: Adam Buchbinder Date: Fri, 18 Dec 2009 15:43:51 -0500 Subject: staging: Fix misspelling of "should" and "shouldn't" in comments. Some comments misspell "should" or "shouldn't"; this fixes them. No code changes. Signed-off-by: Adam Buchbinder Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/addi-data/APCI1710_Chrono.c | 2 +- drivers/staging/comedi/drivers/addi-data/APCI1710_Dig_io.c | 2 +- drivers/staging/comedi/drivers/addi-data/APCI1710_INCCPT.c | 2 +- drivers/staging/comedi/drivers/addi-data/APCI1710_Inp_cpt.c | 2 +- drivers/staging/comedi/drivers/addi-data/APCI1710_Pwm.c | 2 +- drivers/staging/comedi/drivers/addi-data/APCI1710_Ssi.c | 2 +- drivers/staging/comedi/drivers/addi-data/APCI1710_Tor.c | 2 +- drivers/staging/comedi/drivers/addi-data/APCI1710_Ttl.c | 2 +- drivers/staging/comedi/drivers/addi-data/addi_amcc_S5920.c | 2 +- drivers/staging/comedi/drivers/addi-data/addi_common.c | 2 +- drivers/staging/comedi/drivers/addi-data/addi_eeprom.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_APCI1710.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_apci035.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_apci1032.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_apci1500.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_apci1516.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_apci1564.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_apci16xx.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_apci2016.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_apci2032.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_apci2200.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_apci3200.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_apci3501.c | 2 +- drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c | 2 +- drivers/staging/rtl8192e/ieee80211/rtl819x_HTProc.c | 2 +- drivers/staging/rtl8192e/r8192E_core.c | 4 ++-- drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c | 2 +- drivers/staging/rtl8192su/r8192U_core.c | 2 +- drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c | 2 +- drivers/staging/rtl8192u/r8192U_core.c | 2 +- 31 files changed, 32 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/addi-data/APCI1710_Chrono.c b/drivers/staging/comedi/drivers/addi-data/APCI1710_Chrono.c index 0af12fd2a40a..fbc26a027de4 100644 --- a/drivers/staging/comedi/drivers/addi-data/APCI1710_Chrono.c +++ b/drivers/staging/comedi/drivers/addi-data/APCI1710_Chrono.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/APCI1710_Dig_io.c b/drivers/staging/comedi/drivers/addi-data/APCI1710_Dig_io.c index f3e47e5791db..a6898e4bbb62 100644 --- a/drivers/staging/comedi/drivers/addi-data/APCI1710_Dig_io.c +++ b/drivers/staging/comedi/drivers/addi-data/APCI1710_Dig_io.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/APCI1710_INCCPT.c b/drivers/staging/comedi/drivers/addi-data/APCI1710_INCCPT.c index a15c952c0fab..0e498e9eb080 100644 --- a/drivers/staging/comedi/drivers/addi-data/APCI1710_INCCPT.c +++ b/drivers/staging/comedi/drivers/addi-data/APCI1710_INCCPT.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/APCI1710_Inp_cpt.c b/drivers/staging/comedi/drivers/addi-data/APCI1710_Inp_cpt.c index 0fc2285c9ef8..204d7987700a 100644 --- a/drivers/staging/comedi/drivers/addi-data/APCI1710_Inp_cpt.c +++ b/drivers/staging/comedi/drivers/addi-data/APCI1710_Inp_cpt.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/APCI1710_Pwm.c b/drivers/staging/comedi/drivers/addi-data/APCI1710_Pwm.c index 138a84f572c8..148ce6f67f0d 100644 --- a/drivers/staging/comedi/drivers/addi-data/APCI1710_Pwm.c +++ b/drivers/staging/comedi/drivers/addi-data/APCI1710_Pwm.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/APCI1710_Ssi.c b/drivers/staging/comedi/drivers/addi-data/APCI1710_Ssi.c index a445dab50eac..6360de59e0e9 100644 --- a/drivers/staging/comedi/drivers/addi-data/APCI1710_Ssi.c +++ b/drivers/staging/comedi/drivers/addi-data/APCI1710_Ssi.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/APCI1710_Tor.c b/drivers/staging/comedi/drivers/addi-data/APCI1710_Tor.c index 7e1254475792..344df9462198 100644 --- a/drivers/staging/comedi/drivers/addi-data/APCI1710_Tor.c +++ b/drivers/staging/comedi/drivers/addi-data/APCI1710_Tor.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/APCI1710_Ttl.c b/drivers/staging/comedi/drivers/addi-data/APCI1710_Ttl.c index d3d78d37de5c..de6f77246890 100644 --- a/drivers/staging/comedi/drivers/addi-data/APCI1710_Ttl.c +++ b/drivers/staging/comedi/drivers/addi-data/APCI1710_Ttl.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/addi_amcc_S5920.c b/drivers/staging/comedi/drivers/addi-data/addi_amcc_S5920.c index 6e9e7ed4dba9..bd7e4619b3df 100644 --- a/drivers/staging/comedi/drivers/addi-data/addi_amcc_S5920.c +++ b/drivers/staging/comedi/drivers/addi-data/addi_amcc_S5920.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/addi_common.c b/drivers/staging/comedi/drivers/addi-data/addi_common.c index a56535fbcd3e..8db5ab63e363 100644 --- a/drivers/staging/comedi/drivers/addi-data/addi_common.c +++ b/drivers/staging/comedi/drivers/addi-data/addi_common.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/addi_eeprom.c b/drivers/staging/comedi/drivers/addi-data/addi_eeprom.c index 69b427390e53..bea329f44d80 100644 --- a/drivers/staging/comedi/drivers/addi-data/addi_eeprom.c +++ b/drivers/staging/comedi/drivers/addi-data/addi_eeprom.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_APCI1710.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_APCI1710.c index 47517a938ec5..d7d768ee7c23 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_APCI1710.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_APCI1710.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci035.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci035.c index 016721efdbfb..791297266fc0 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci035.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci035.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1032.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1032.c index 723a97bab44c..27c68aac32d1 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1032.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1032.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1500.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1500.c index 36b929ffecbd..d5e06ad6acc2 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1500.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1500.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1516.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1516.c index 866eb8d75820..7948c41f60f5 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1516.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1516.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1564.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1564.c index 3ae663bc754e..4413279c880b 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1564.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1564.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci16xx.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci16xx.c index 988e3fc2b857..8bc88adfbb59 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci16xx.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci16xx.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci2016.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci2016.c index d348cd5687aa..89783b1eb0bd 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci2016.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci2016.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci2032.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci2032.c index ec817082d170..2d325163c169 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci2032.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci2032.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci2200.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci2200.c index aa159dccc36a..e01889c3c4fc 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci2200.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci2200.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c index 172fba8dbfe5..07123fd766a3 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3200.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3200.c index 98c23872e374..560c848f6258 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3200.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3200.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3501.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3501.c index 7b38d177394b..4ed441a1adc8 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3501.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3501.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c index 1d1e5fc2ea9a..eec71c3efe5e 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c @@ -17,7 +17,7 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -You shoud also find the complete GPL in the COPYING file accompanying this source code. +You should also find the complete GPL in the COPYING file accompanying this source code. @endverbatim */ diff --git a/drivers/staging/rtl8192e/ieee80211/rtl819x_HTProc.c b/drivers/staging/rtl8192e/ieee80211/rtl819x_HTProc.c index c93247362fe8..4c4b1df350ac 100644 --- a/drivers/staging/rtl8192e/ieee80211/rtl819x_HTProc.c +++ b/drivers/staging/rtl8192e/ieee80211/rtl819x_HTProc.c @@ -42,7 +42,7 @@ static u8 DLINK_ATHEROS[3] = {0x00, 0x1c, 0xf0}; static u8 CISCO_BROADCOM[3] = {0x00, 0x17, 0x94}; static u8 LINKSYS_MARVELL_4400N[3] = {0x00, 0x14, 0xa4}; -// 2008/04/01 MH For Cisco G mode RX TP We need to change FW duration. Shoud we put the +// 2008/04/01 MH For Cisco G mode RX TP We need to change FW duration. Should we put the // code in other place?? //static u8 WIFI_CISCO_G_AP[3] = {0x00, 0x40, 0x96}; /******************************************************************************************************************** diff --git a/drivers/staging/rtl8192e/r8192E_core.c b/drivers/staging/rtl8192e/r8192E_core.c index 662231968724..d3105281d31e 100644 --- a/drivers/staging/rtl8192e/r8192E_core.c +++ b/drivers/staging/rtl8192e/r8192E_core.c @@ -2313,7 +2313,7 @@ static void rtl8192_SetWirelessMode(struct net_device* dev, u8 wireless_mode) wireless_mode = WIRELESS_MODE_B; } } -#ifdef TO_DO_LIST //// TODO: this function doesn't work well at this time, we shoud wait for FPGA +#ifdef TO_DO_LIST //// TODO: this function doesn't work well at this time, we should wait for FPGA ActUpdateChannelAccessSetting( pAdapter, pHalData->CurrentWirelessMode, &pAdapter->MgntInfo.Info8185.ChannelAccessSetting ); #endif priv->ieee80211->mode = wireless_mode; @@ -6520,7 +6520,7 @@ void rtl8192_cancel_deferred_work(struct r8192_priv* priv) /* call cancel_work_sync instead of cancel_delayed_work if and only if Linux_version_code * is or is newer than 2.6.20 and work structure is defined to be struct work_struct. * Otherwise call cancel_delayed_work is enough. - * FIXME (2.6.20 shoud 2.6.22, work_struct shoud not cancel) + * FIXME (2.6.20 should 2.6.22, work_struct should not cancel) * */ cancel_delayed_work(&priv->watch_dog_wq); cancel_delayed_work(&priv->update_beacon_wq); diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c b/drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c index 33c7fa7edc8b..01114c5181bb 100644 --- a/drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c +++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c @@ -42,7 +42,7 @@ static u8 DLINK_ATHEROS_1[3] = {0x00, 0x1c, 0xf0}; static u8 DLINK_ATHEROS_2[3] = {0x00, 0x21, 0x91}; static u8 CISCO_BROADCOM[3] = {0x00, 0x17, 0x94}; static u8 LINKSYS_MARVELL_4400N[3] = {0x00, 0x14, 0xa4}; -// 2008/04/01 MH For Cisco G mode RX TP We need to change FW duration. Shoud we put the +// 2008/04/01 MH For Cisco G mode RX TP We need to change FW duration. Should we put the // code in other place?? //static u8 WIFI_CISCO_G_AP[3] = {0x00, 0x40, 0x96}; /******************************************************************************************************************** diff --git a/drivers/staging/rtl8192su/r8192U_core.c b/drivers/staging/rtl8192su/r8192U_core.c index 7fa02ac8e500..ecfa91b56c8d 100644 --- a/drivers/staging/rtl8192su/r8192U_core.c +++ b/drivers/staging/rtl8192su/r8192U_core.c @@ -2952,7 +2952,7 @@ void rtl8192_SetWirelessMode(struct net_device* dev, u8 wireless_mode) wireless_mode = WIRELESS_MODE_B; } } -#ifdef TO_DO_LIST //// TODO: this function doesn't work well at this time, we shoud wait for FPGA +#ifdef TO_DO_LIST //// TODO: this function doesn't work well at this time, we should wait for FPGA ActUpdateChannelAccessSetting( pAdapter, pHalData->CurrentWirelessMode, &pAdapter->MgntInfo.Info8185.ChannelAccessSetting ); #endif //LZM 090306 usb crash here, mark it temp diff --git a/drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c b/drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c index 2c4eb38c89a8..3a5eaa59b21d 100644 --- a/drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c +++ b/drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c @@ -41,7 +41,7 @@ static u8 AIRLINK_RALINK[3] = {0x00, 0x18, 0x02}; //static u8 DLINK_ATHEROS[3] = {0x00, 0x1c, 0xf0}; static u8 CISCO_BROADCOM[3] = {0x00, 0x17, 0x94}; -// 2008/04/01 MH For Cisco G mode RX TP We need to change FW duration. Shoud we put the +// 2008/04/01 MH For Cisco G mode RX TP We need to change FW duration. Should we put the // code in other place?? //static u8 WIFI_CISCO_G_AP[3] = {0x00, 0x40, 0x96}; /******************************************************************************************************************** diff --git a/drivers/staging/rtl8192u/r8192U_core.c b/drivers/staging/rtl8192u/r8192U_core.c index 5afc73751043..7cf7ea703bba 100644 --- a/drivers/staging/rtl8192u/r8192U_core.c +++ b/drivers/staging/rtl8192u/r8192U_core.c @@ -2719,7 +2719,7 @@ void rtl8192_SetWirelessMode(struct net_device* dev, u8 wireless_mode) wireless_mode = WIRELESS_MODE_B; } } -#ifdef TO_DO_LIST //// TODO: this function doesn't work well at this time, we shoud wait for FPGA +#ifdef TO_DO_LIST //// TODO: this function doesn't work well at this time, we should wait for FPGA ActUpdateChannelAccessSetting( pAdapter, pHalData->CurrentWirelessMode, &pAdapter->MgntInfo.Info8185.ChannelAccessSetting ); #endif priv->ieee80211->mode = wireless_mode; -- cgit v1.2.3 From 3fc0d278e3198c8aa9baa71c49a8364d31686ba9 Mon Sep 17 00:00:00 2001 From: Adam Buchbinder Date: Fri, 18 Dec 2009 15:43:52 -0500 Subject: staging: Fix misspelling of "invocation" in comment. A comment misspells "invocation"; this fixes it. No code changes. Signed-off-by: Adam Buchbinder Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlan-ng/hfa384x_usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/wlan-ng/hfa384x_usb.c b/drivers/staging/wlan-ng/hfa384x_usb.c index 925678babd9e..c6a9e17ec79b 100644 --- a/drivers/staging/wlan-ng/hfa384x_usb.c +++ b/drivers/staging/wlan-ng/hfa384x_usb.c @@ -52,7 +52,7 @@ * around the register accesses. The next higher level represents C-callable * prism2 API functions that match the Intersil documentation as closely * as is reasonable. The next higher layer implements common sequences -* of invokations of the API layer (e.g. write to bap, followed by cmd). +* of invocations of the API layer (e.g. write to bap, followed by cmd). * * Common sequences: * hfa384x_drvr_xxx Highest level abstractions provided by the -- cgit v1.2.3 From 1bc5e651295ab35fc7d396d940cf9a1e530c0a7e Mon Sep 17 00:00:00 2001 From: Pekka Enberg Date: Fri, 18 Dec 2009 23:08:15 +0200 Subject: Staging: w35und: Convert typedef LOCAL_PARA to struct wb_local_para Acked-by: Pavel Machek Signed-off-by: Pekka Enberg Signed-off-by: Greg Kroah-Hartman --- drivers/staging/winbond/core.h | 2 +- drivers/staging/winbond/localpara.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/winbond/core.h b/drivers/staging/winbond/core.h index 7d4bd5e8f69b..0a2060bf4f94 100644 --- a/drivers/staging/winbond/core.h +++ b/drivers/staging/winbond/core.h @@ -14,7 +14,7 @@ struct wbsoft_priv { u32 adapterIndex; // 20060703.4 Add for using padapterContext global adapter point - WB_LOCALDESCRIPT sLocalPara; // Myself connected parameters + struct wb_local_para sLocalPara; // Myself connected parameters MLME_FRAME sMlmeFrame; // connect to peerSTA parameters diff --git a/drivers/staging/winbond/localpara.h b/drivers/staging/winbond/localpara.h index 5626a76d69a4..b731875f80f5 100644 --- a/drivers/staging/winbond/localpara.h +++ b/drivers/staging/winbond/localpara.h @@ -136,7 +136,7 @@ typedef struct _RadioOff } RadioOff, *psRadioOff; //=========================================================================== -typedef struct LOCAL_PARA +struct wb_local_para { u8 PermanentAddress[ MAC_ADDR_LENGTH + 2 ]; // read from EPROM, manufacture set for each NetCard u8 ThisMacAddress[ MAC_ADDR_LENGTH + 2 ]; // the driver will use actually. @@ -274,6 +274,6 @@ typedef struct LOCAL_PARA u16 IE_Append_size; u16 reserved_7; -} WB_LOCALDESCRIPT, *PWB_LOCALDESCRIPT; +}; #endif -- cgit v1.2.3 From 92ce4703920dc1bb380c12498a2f6bb825effbc7 Mon Sep 17 00:00:00 2001 From: Pekka Enberg Date: Fri, 18 Dec 2009 23:08:16 +0200 Subject: Staging: w35und: Convert typedef RadioOff to struct radio_off Acked-by: Pavel Machek Signed-off-by: Pekka Enberg Signed-off-by: Greg Kroah-Hartman --- drivers/staging/winbond/localpara.h | 6 +++--- drivers/staging/winbond/sme_api.h | 2 -- 2 files changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/winbond/localpara.h b/drivers/staging/winbond/localpara.h index b731875f80f5..b82d5ce4b1bd 100644 --- a/drivers/staging/winbond/localpara.h +++ b/drivers/staging/winbond/localpara.h @@ -129,11 +129,11 @@ typedef struct _CHAN_LIST ChanInfo Channel[50]; // 100B } CHAN_LIST, *psCHAN_LIST; -typedef struct _RadioOff +struct radio_off { u8 boHwRadioOff; u8 boSwRadioOff; -} RadioOff, *psRadioOff; +}; //=========================================================================== struct wb_local_para @@ -186,7 +186,7 @@ struct wb_local_para u16 ListenInterval; // The listen interval when SME invoking MLME_ // (Re)Associate_Request(). - RadioOff RadioOffStatus; + struct radio_off RadioOffStatus; u8 Reserved0[2]; u8 boMsRadioOff; // Ndis demands to be true when set Disassoc. OID and be false when set SSID OID. diff --git a/drivers/staging/winbond/sme_api.h b/drivers/staging/winbond/sme_api.h index 549878302288..62c256499bc4 100644 --- a/drivers/staging/winbond/sme_api.h +++ b/drivers/staging/winbond/sme_api.h @@ -193,8 +193,6 @@ s8 sme_get_cwmin_value(void *pcore_data, u8 *cwmin); s8 sme_get_cwmax_value(void *pcore_data, u16 *cwmax); s8 sme_get_ms_radio_mode(void *pcore_data, u8 * pMsRadioOff); s8 sme_set_ms_radio_mode(void *pcore_data, u8 boMsRadioOff); -s8 sme_get_radio_mode(void *pcore_data, psRadioOff pRadioOffData); -s8 sme_set_radio_mode(void *pcore_data, RadioOff RadioOffData); void sme_get_tx_power_level(void *pcore_data, u32 *TxPower); u8 sme_set_tx_power_level(void *pcore_data, u32 TxPower); -- cgit v1.2.3 From 395af561825095b2df30ed2ee86c3ed898783e8f Mon Sep 17 00:00:00 2001 From: Pekka Enberg Date: Fri, 18 Dec 2009 23:08:17 +0200 Subject: Staging: w35und: Remove unused typedef _EVENTLOG Acked-by: Pavel Machek Signed-off-by: Pekka Enberg Signed-off-by: Greg Kroah-Hartman --- drivers/staging/winbond/localpara.h | 9 --------- 1 file changed, 9 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/winbond/localpara.h b/drivers/staging/winbond/localpara.h index b82d5ce4b1bd..6b29b56cf5d7 100644 --- a/drivers/staging/winbond/localpara.h +++ b/drivers/staging/winbond/localpara.h @@ -110,13 +110,6 @@ // 20061108 WPS IE buffer #define MAX_IE_APPEND_SIZE 256 + 4 // Due to [E id][Length][OUI][Data] may 257 bytes -typedef struct _EVENTLOG -{ - u16 Count; //Total count from start - u16 index; //Buffer index, 0 ~ 63 - u32 EventValue[64]; //BYTE 3~2 : count, BYTE 1 : Event, BYTE 0 : reason -} Event_Log, *pEvent_Log; - typedef struct _ChanInfo { u8 band; @@ -264,8 +257,6 @@ struct wb_local_para u32 bToSelfPacketReceived; u32 WepKeyDetectTimerCount; - Event_Log EventLog; - u16 SignalLostTh; u16 SignalRoamTh; -- cgit v1.2.3 From 440a233db4c117f34397abd3722d5802fe1b8c30 Mon Sep 17 00:00:00 2001 From: Pekka Enberg Date: Fri, 18 Dec 2009 23:08:18 +0200 Subject: Staging: w35und: Convert typedef ChanInfo to struct chan_info Acked-by: Pavel Machek Signed-off-by: Pekka Enberg Signed-off-by: Greg Kroah-Hartman --- drivers/staging/winbond/localpara.h | 10 +++++----- drivers/staging/winbond/reg.c | 10 +++++----- drivers/staging/winbond/sme_api.h | 2 +- drivers/staging/winbond/wb35reg_f.h | 2 +- drivers/staging/winbond/wbusb.c | 8 ++++---- 5 files changed, 16 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/winbond/localpara.h b/drivers/staging/winbond/localpara.h index 6b29b56cf5d7..7ca58d020578 100644 --- a/drivers/staging/winbond/localpara.h +++ b/drivers/staging/winbond/localpara.h @@ -110,16 +110,16 @@ // 20061108 WPS IE buffer #define MAX_IE_APPEND_SIZE 256 + 4 // Due to [E id][Length][OUI][Data] may 257 bytes -typedef struct _ChanInfo +struct chan_info { u8 band; u8 ChanNo; -} ChanInfo, *pChanInfo; +}; typedef struct _CHAN_LIST { u16 Count; - ChanInfo Channel[50]; // 100B + struct chan_info Channel[50]; // 100B } CHAN_LIST, *psCHAN_LIST; struct radio_off @@ -189,7 +189,7 @@ struct wb_local_para u8 RoamStatus; u8 reserved7[3]; - ChanInfo CurrentChan; //Current channel no. and channel band. It may be changed by scanning. + struct chan_info CurrentChan; //Current channel no. and channel band. It may be changed by scanning. u8 boHandover; // Roaming, Hnadover to other AP. u8 boCCAbusy; @@ -246,7 +246,7 @@ struct wb_local_para u32 _dot11WEPUndecryptableCount; u32 _dot11FrameDuplicateCount; - ChanInfo IbssChanSetting; // 2B. Start IBSS Channel setting by registry or WWU. + struct chan_info IbssChanSetting; // 2B. Start IBSS Channel setting by registry or WWU. u8 reserved_5[2]; //It may not be used after considering RF type, //region and modulation type. diff --git a/drivers/staging/winbond/reg.c b/drivers/staging/winbond/reg.c index d915cbdd38ed..5f5048af26a5 100644 --- a/drivers/staging/winbond/reg.c +++ b/drivers/staging/winbond/reg.c @@ -1823,12 +1823,12 @@ BBProcessor_initial( struct hw_data * pHwData ) reg->SQ3_filter[i] = 0x2f; // half of Bit 0 ~ 6 } -void set_tx_power_per_channel_max2829( struct hw_data * pHwData, ChanInfo Channel) +void set_tx_power_per_channel_max2829( struct hw_data * pHwData, struct chan_info Channel) { RFSynthesizer_SetPowerIndex( pHwData, 100 ); // 20060620.1 Modify } -void set_tx_power_per_channel_al2230( struct hw_data * pHwData, ChanInfo Channel ) +void set_tx_power_per_channel_al2230( struct hw_data * pHwData, struct chan_info Channel ) { u8 index = 100; @@ -1838,7 +1838,7 @@ void set_tx_power_per_channel_al2230( struct hw_data * pHwData, ChanInfo Chann RFSynthesizer_SetPowerIndex( pHwData, index ); } -void set_tx_power_per_channel_al7230( struct hw_data * pHwData, ChanInfo Channel) +void set_tx_power_per_channel_al7230( struct hw_data * pHwData, struct chan_info Channel) { u8 i, index = 100; @@ -1868,7 +1868,7 @@ void set_tx_power_per_channel_al7230( struct hw_data * pHwData, ChanInfo Chann RFSynthesizer_SetPowerIndex( pHwData, index ); } -void set_tx_power_per_channel_wb242( struct hw_data * pHwData, ChanInfo Channel) +void set_tx_power_per_channel_wb242( struct hw_data * pHwData, struct chan_info Channel) { u8 index = 100; @@ -1901,7 +1901,7 @@ void set_tx_power_per_channel_wb242( struct hw_data * pHwData, ChanInfo Channe // None. //============================================================================================================= void -RFSynthesizer_SwitchingChannel( struct hw_data * pHwData, ChanInfo Channel ) +RFSynthesizer_SwitchingChannel( struct hw_data * pHwData, struct chan_info Channel ) { struct wb35_reg *reg = &pHwData->reg; u32 pltmp[16]; // The 16 is the maximum capability of hardware diff --git a/drivers/staging/winbond/sme_api.h b/drivers/staging/winbond/sme_api.h index 62c256499bc4..b5898294eb8a 100644 --- a/drivers/staging/winbond/sme_api.h +++ b/drivers/staging/winbond/sme_api.h @@ -201,7 +201,7 @@ void sme_get_rx_antenna(void *pcore_data, u32 *RxAntenna); u8 sme_set_rx_antenna(void *pcore_data, u32 RxAntenna); void sme_get_tx_antenna(void *pcore_data, u32 *TxAntenna); s8 sme_set_tx_antenna(void *pcore_data, u32 TxAntenna); -s8 sme_set_IBSS_chan(void *pcore_data, ChanInfo chan); +s8 sme_set_IBSS_chan(void *pcore_data, struct chan_info chan); //20061108 WPS s8 sme_set_IE_append(void *pcore_data, u8 *buffer, u16 buf_len); diff --git a/drivers/staging/winbond/wb35reg_f.h b/drivers/staging/winbond/wb35reg_f.h index 30f5b5ad63ad..d352bce5c171 100644 --- a/drivers/staging/winbond/wb35reg_f.h +++ b/drivers/staging/winbond/wb35reg_f.h @@ -14,7 +14,7 @@ void Dxx_initial( struct hw_data * pHwData ); void Mxx_initial( struct hw_data * pHwData ); void RFSynthesizer_initial( struct hw_data * pHwData ); //void RFSynthesizer_SwitchingChannel( struct hw_data * pHwData, s8 Channel ); -void RFSynthesizer_SwitchingChannel( struct hw_data * pHwData, ChanInfo Channel ); +void RFSynthesizer_SwitchingChannel( struct hw_data * pHwData, struct chan_info Channel ); void BBProcessor_initial( struct hw_data * pHwData ); void BBProcessor_RateChanging( struct hw_data * pHwData, u8 rate ); // 20060613.1 //void RF_RateChanging( struct hw_data * pHwData, u8 rate ); // 20060626.5.c Add diff --git a/drivers/staging/winbond/wbusb.c b/drivers/staging/winbond/wbusb.c index 067082a7d759..1c5876359491 100644 --- a/drivers/staging/winbond/wbusb.c +++ b/drivers/staging/winbond/wbusb.c @@ -161,7 +161,7 @@ static void hal_set_radio_mode(struct hw_data *pHwData, unsigned char radio_off) } static void -hal_set_current_channel_ex(struct hw_data *pHwData, ChanInfo channel) +hal_set_current_channel_ex(struct hw_data *pHwData, struct chan_info channel) { struct wb35_reg *reg = &pHwData->reg; @@ -180,10 +180,10 @@ hal_set_current_channel_ex(struct hw_data *pHwData, ChanInfo channel) reg->M28_MacControl &= ~0xff; // Clean channel information field reg->M28_MacControl |= channel.ChanNo; Wb35Reg_WriteWithCallbackValue(pHwData, 0x0828, reg->M28_MacControl, - (s8 *) & channel, sizeof(ChanInfo)); + (s8 *) & channel, sizeof(struct chan_info)); } -static void hal_set_current_channel(struct hw_data *pHwData, ChanInfo channel) +static void hal_set_current_channel(struct hw_data *pHwData, struct chan_info channel) { hal_set_current_channel_ex(pHwData, channel); } @@ -253,7 +253,7 @@ static void hal_set_accept_beacon(struct hw_data *pHwData, u8 enable) static int wbsoft_config(struct ieee80211_hw *dev, u32 changed) { struct wbsoft_priv *priv = dev->priv; - ChanInfo ch; + struct chan_info ch; printk("wbsoft_config called\n"); -- cgit v1.2.3 From 23b0dce239426ff8a7068b8d617d0c6eb4544cf7 Mon Sep 17 00:00:00 2001 From: Pekka Enberg Date: Fri, 18 Dec 2009 23:08:19 +0200 Subject: Staging: w35und: Remove unused typedef CHAN_LIST Acked-by: Pavel Machek Signed-off-by: Pekka Enberg Signed-off-by: Greg Kroah-Hartman --- drivers/staging/winbond/localpara.h | 7 ------- drivers/staging/winbond/scan_s.h | 1 - 2 files changed, 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/winbond/localpara.h b/drivers/staging/winbond/localpara.h index 7ca58d020578..fcf6a0442dc2 100644 --- a/drivers/staging/winbond/localpara.h +++ b/drivers/staging/winbond/localpara.h @@ -116,12 +116,6 @@ struct chan_info u8 ChanNo; }; -typedef struct _CHAN_LIST -{ - u16 Count; - struct chan_info Channel[50]; // 100B -} CHAN_LIST, *psCHAN_LIST; - struct radio_off { u8 boHwRadioOff; @@ -250,7 +244,6 @@ struct wb_local_para u8 reserved_5[2]; //It may not be used after considering RF type, //region and modulation type. - CHAN_LIST sSupportChanList; // 86B. It will be obtained according to RF type and region u8 reserved_6[2]; //two variables are for wep key error detection added by ws 02/02/04 u32 bWepKeyError; diff --git a/drivers/staging/winbond/scan_s.h b/drivers/staging/winbond/scan_s.h index 775bb81f23cc..209717f5d47d 100644 --- a/drivers/staging/winbond/scan_s.h +++ b/drivers/staging/winbond/scan_s.h @@ -35,7 +35,6 @@ typedef struct _SCAN_REQ_PARA //mandatory parameters for SCAN request { u32 ScanType; //passive/active scan - CHAN_LIST sChannelList; // 86B u8 reserved_1[2]; struct SSID_Element sSSID; // 34B. scan only for this SSID -- cgit v1.2.3 From 2b6e6df4d911e5ef1f438b84ee00cfc48865aff3 Mon Sep 17 00:00:00 2001 From: Pekka Enberg Date: Fri, 18 Dec 2009 23:08:20 +0200 Subject: Staging: w35und: Remove unused typedef TXRETRY_REC Acked-by: Pavel Machek Signed-off-by: Pekka Enberg Signed-off-by: Greg Kroah-Hartman --- drivers/staging/winbond/mto.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/winbond/mto.h b/drivers/staging/winbond/mto.h index 4fe24b0f2791..fb4781d5781b 100644 --- a/drivers/staging/winbond/mto.h +++ b/drivers/staging/winbond/mto.h @@ -141,11 +141,6 @@ extern u16 MTO_Frag_Th_Tbl[]; #define MTO_DATA_RATE() MTO_Data_Rate_Tbl[MTO_RATE_LEVEL()] #define MTO_FRAG_TH() MTO_Frag_Th_Tbl[MTO_FRAG_TH_LEVEL()] -typedef struct { - u8 tx_rate; - u8 tx_retry_rate; -} TXRETRY_REC; - extern void MTO_Init(struct wbsoft_priv *); extern void MTO_PeriodicTimerExpired(struct wbsoft_priv *); extern void MTO_SetDTORateRange(struct wbsoft_priv *, u8 *, u8); -- cgit v1.2.3 From 8fab4020fa1aa5ee3ad4e409323be9edfbd6c20e Mon Sep 17 00:00:00 2001 From: Pekka Enberg Date: Fri, 18 Dec 2009 23:08:21 +0200 Subject: Staging: w35und: Remove unused typedef RXLAYER1 Acked-by: Pavel Machek Signed-off-by: Pekka Enberg Signed-off-by: Greg Kroah-Hartman --- drivers/staging/winbond/mds_f.h | 3 --- drivers/staging/winbond/mds_s.h | 28 ---------------------------- 2 files changed, 31 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/winbond/mds_f.h b/drivers/staging/winbond/mds_f.h index ab1ea535f7db..e09dd4b879d4 100644 --- a/drivers/staging/winbond/mds_f.h +++ b/drivers/staging/winbond/mds_f.h @@ -11,9 +11,6 @@ void Mds_SendComplete( struct wbsoft_priv *adapter, PT02_DESCRIPTOR pT02 ); void Mds_MpduProcess( struct wbsoft_priv *adapter, struct wb35_descriptor *pRxDes ); extern void DataDmp(u8 *pdata, u32 len, u32 offset); -// For Asynchronous indicating. The routine collocates with USB. -void Mds_MsduProcess( struct wbsoft_priv *adapter, PRXLAYER1 pRxLayer1, u8 SlotIndex); - // For data frame sending 20060802 u16 MDS_GetPacketSize( struct wbsoft_priv *adapter ); void MDS_GetNextPacket( struct wbsoft_priv *adapter, struct wb35_descriptor *pDes ); diff --git a/drivers/staging/winbond/mds_s.h b/drivers/staging/winbond/mds_s.h index e8e13bde4744..217ff0819a93 100644 --- a/drivers/staging/winbond/mds_s.h +++ b/drivers/staging/winbond/mds_s.h @@ -133,32 +133,4 @@ struct wb35_mds { }; -// -// Reveive Layer 1 Format. -//---------------------------- -typedef struct _RXLAYER1 -{ - u16 SequenceNumber; // The sequence number of the last received packet. - u16 BufferTotalSize; - - u32 InUsed; - u32 DecryptionMethod; // The desired defragment number of the next incoming packet. - - u8 DeFragmentNumber; - u8 FrameType; - u8 TypeEncapsulated; - u8 BufferNumber; - - u32 FirstFrameArrivedTime; - - u8 LastFrameType; // 20061004 for fix intel 3945 's bug - u8 RESERVED[3]; //@@ anson - - ///////////////////////////////////////////////////////////////////////////////////////////// - // For brand-new Rx system - u8 ReservedBuffer[ 2400 ];//If Buffer ID is reserved one, it must copy the data into this area - u8 *ReservedBufferPoint;// Point to the next availabe address of reserved buffer - -}RXLAYER1, * PRXLAYER1; - #endif -- cgit v1.2.3 From 096417e087a391dc78780cc1843369a521635522 Mon Sep 17 00:00:00 2001 From: Pekka Enberg Date: Fri, 18 Dec 2009 23:08:22 +0200 Subject: Staging: w35und: Remove unused typedefs MLME_DEAUTHREQ_PARA and MLME_DISASSOCREQ_PARA Acked-by: Pavel Machek Signed-off-by: Pekka Enberg Signed-off-by: Greg Kroah-Hartman --- drivers/staging/winbond/mlme_s.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/winbond/mlme_s.h b/drivers/staging/winbond/mlme_s.h index ea12684a2b1d..1217a1c025e5 100644 --- a/drivers/staging/winbond/mlme_s.h +++ b/drivers/staging/winbond/mlme_s.h @@ -165,14 +165,6 @@ typedef struct _AUTHREQ { } MLME_AUTHREQ_PARA, *psMLME_AUTHREQ_PARA; -struct _Reason_Code { - - u8 peerMACaddr[MAC_ADDR_LENGTH]; - u16 wReasonCode; -}; -typedef struct _Reason_Code MLME_DEAUTHREQ_PARA, *psMLME_DEAUTHREQ_PARA; -typedef struct _Reason_Code MLME_DISASSOCREQ_PARA, *psMLME_DISASSOCREQ_PARA; - typedef struct _ASSOCREQ { u8 PeerSTAAddr[MAC_ADDR_LENGTH]; u16 CapabilityInfo; -- cgit v1.2.3 From 8c172dde41db666f7a5f3bb62205da017e23c0ec Mon Sep 17 00:00:00 2001 From: Justin Madru Date: Fri, 18 Dec 2009 15:52:53 -0800 Subject: Staging: s5k3e2fx.c: simplify complexity by factoring the code was looping, setting s_move[i] to the following calculations if (actual_step>= 0) s_move[i] = ((((i + 1) * gain + 0x200) - (i * gain + 0x200)) / 0x400); else s_move[i] = ((((i + 1) * gain - 0x200) - (i * gain - 0x200)) / 0x400); but, this code reduces to the expression s_move[i] = gain>> 10; The reason for the complexity was to generate a step function with integer division and rounding to land on specific values. But these calculations can be simplified to the following code: gain = ((actual_step<< 10) / 5)>> 10; for (i = 0; i<= 4; i++) s_move[i] = gain; Signed-off-by: Justin Madru Reviewed-by: Ray Lee Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dream/camera/s5k3e2fx.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dream/camera/s5k3e2fx.c b/drivers/staging/dream/camera/s5k3e2fx.c index edba19889b0f..66582af5a586 100644 --- a/drivers/staging/dream/camera/s5k3e2fx.c +++ b/drivers/staging/dream/camera/s5k3e2fx.c @@ -1093,14 +1093,10 @@ static int32_t s5k3e2fx_move_focus(int direction, int32_t num_steps) actual_step = step_direction * (int16_t)num_steps; pos_offset = init_code + s5k3e2fx_ctrl->curr_lens_pos; - gain = actual_step * 0x400 / 5; + gain = ((actual_step << 10) / 5) >> 10; - for (i = 0; i <= 4; i++) { - if (actual_step >= 0) - s_move[i] = ((((i+1)*gain+0x200) - (i*gain+0x200))/0x400); - else - s_move[i] = ((((i+1)*gain-0x200) - (i*gain-0x200))/0x400); - } + for (i = 0; i <= 4; i++) + s_move[i] = gain; /* Ring Damping Code */ for (i = 0; i <= 4; i++) { -- cgit v1.2.3 From 784d3119475652d34a8d8ec3911e39c5e3d3036f Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 21 Dec 2009 15:07:10 +1100 Subject: Staging: rtl8192su: Build should select WIRELESS_EXT The prevailing idiom is to select WIRELESS_EXT not depend on it. Depending leaves this driver in a situation where it can only be built if another driver that selects WIRELESS_EXT has been enabled. Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192su/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192su/Kconfig b/drivers/staging/rtl8192su/Kconfig index 123fa6d6a93b..b72a96206f58 100644 --- a/drivers/staging/rtl8192su/Kconfig +++ b/drivers/staging/rtl8192su/Kconfig @@ -1,6 +1,7 @@ config RTL8192SU tristate "RealTek RTL8192SU Wireless LAN NIC driver" depends on PCI && WLAN && USB - depends on WIRELESS_EXT + select WIRELESS_EXT + select WEXT_PRIV default N ---help--- -- cgit v1.2.3 From d512a142f0a3d5ce138880fb2a70462542d5f711 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 21 Dec 2009 15:07:50 +1100 Subject: Staging: rtl8192su: Use z format qualifier for output of sizeof() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit $ gcc --version gcc (Debian 4.4.2-5) 4.4.2 Copyright (C) 2009 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ make ... drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c: In function ‘ieee80211_rx_ADDBAReq’: drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c:342: warning: format ‘%ld’ expects type ‘long int’, but argument 3 has type ‘unsigned int’ drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c: In function ‘ieee80211_rx_ADDBARsp’: drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c:443: warning: format ‘%ld’ expects type ‘long int’, but argument 3 has type ‘unsigned int’ drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c: In function ‘ieee80211_rx_DELBA’: drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c:573: warning: format ‘%ld’ expects type ‘long int’, but argument 3 has type ‘unsigned int’ ... Also some style fixes for these lines: + Fix excessively long lines + Remove leading space before struct + Remove unnecessary parentheses Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c b/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c index 6eb1096866af..5a3888450ab3 100644 --- a/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c +++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c @@ -339,7 +339,10 @@ int ieee80211_rx_ADDBAReq( struct ieee80211_device* ieee, struct sk_buff *skb) if (skb->len < sizeof( struct ieee80211_hdr_3addr) + 9) { - IEEE80211_DEBUG(IEEE80211_DL_ERR, " Invalid skb len in BAREQ(%d / %ld)\n", skb->len, (sizeof( struct ieee80211_hdr_3addr) + 9)); + IEEE80211_DEBUG(IEEE80211_DL_ERR, + " Invalid skb len in BAREQ(%d / %zd)\n", + skb->len, + sizeof(struct ieee80211_hdr_3addr) + 9); return -1; } @@ -440,7 +443,10 @@ int ieee80211_rx_ADDBARsp( struct ieee80211_device* ieee, struct sk_buff *skb) if (skb->len < sizeof( struct ieee80211_hdr_3addr) + 9) { - IEEE80211_DEBUG(IEEE80211_DL_ERR, " Invalid skb len in BARSP(%d / %ld)\n", skb->len, (sizeof( struct ieee80211_hdr_3addr) + 9)); + IEEE80211_DEBUG(IEEE80211_DL_ERR, + " Invalid skb len in BARSP(%d / %zd)\n", + skb->len, + sizeof(struct ieee80211_hdr_3addr) + 9); return -1; } rsp = ( struct ieee80211_hdr_3addr*)skb->data; @@ -570,7 +576,10 @@ int ieee80211_rx_DELBA(struct ieee80211_device* ieee,struct sk_buff *skb) if (skb->len < sizeof( struct ieee80211_hdr_3addr) + 6) { - IEEE80211_DEBUG(IEEE80211_DL_ERR, " Invalid skb len in DELBA(%d / %ld)\n", skb->len, (sizeof( struct ieee80211_hdr_3addr) + 6)); + IEEE80211_DEBUG(IEEE80211_DL_ERR, + " Invalid skb len in DELBA(%d / %zd)\n", + skb->len, + sizeof(struct ieee80211_hdr_3addr) + 6); return -1; } -- cgit v1.2.3 From e8ffaa3a06a71a5a02373cfcb5f474f9a181ec68 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 21 Dec 2009 15:08:15 +1100 Subject: Staging: prism2-usb: Build should select WIRELESS_EXT The prevailing idiom is to select WIRELESS_EXT not depend on it. Depending leaves this driver in a situation where it can only be built if another driver that selects WIRELESS_EXT has been enabled. Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlan-ng/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/wlan-ng/Kconfig b/drivers/staging/wlan-ng/Kconfig index f44294b0d8dc..704ebd26e628 100644 --- a/drivers/staging/wlan-ng/Kconfig +++ b/drivers/staging/wlan-ng/Kconfig @@ -1,6 +1,7 @@ config PRISM2_USB tristate "Prism2.5/3 USB driver" - depends on WLAN && USB && WIRELESS_EXT + depends on WLAN && USB + select WIRELESS_EXT default n ---help--- This is the wlan-ng prism 2.5/3 USB driver for a wide range of -- cgit v1.2.3 From 8125e2f66800f9e16e632df20fa3195c07f6aaf9 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 21 Dec 2009 15:09:53 +1100 Subject: Staging: wlan-ng: initialise mibitem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit $ gcc --version gcc (Debian 4.4.2-5) 4.4.2 Copyright (C) 2009 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ make ... drivers/staging/wlan-ng/p80211wext.c: In function ‘p80211wext_dorequest’: drivers/staging/wlan-ng/p80211wext.c:139: warning: ‘mibitem.len’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:139: warning: ‘mibitem.status’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c: In function ‘p80211wext_giwretry’: drivers/staging/wlan-ng/p80211wext.c:967: warning: ‘mibitem.len’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:967: warning: ‘mibitem.status’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:967: warning: ‘mibitem.data’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c: In function ‘p80211wext_siwretry’: drivers/staging/wlan-ng/p80211wext.c:1057: warning: ‘mibitem.len’ may be used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:1057: warning: ‘mibitem.status’ may be used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c: In function ‘p80211wext_giwtxpow’: drivers/staging/wlan-ng/p80211wext.c:1149: warning: ‘mibitem.len’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:1149: warning: ‘mibitem.status’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:1149: warning: ‘mibitem.data’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c: In function ‘p80211wext_siwtxpow’: drivers/staging/wlan-ng/p80211wext.c:1123: warning: ‘mibitem.len’ may be used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:1123: warning: ‘mibitem.status’ may be used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c: In function ‘p80211wext_giwfrag’: drivers/staging/wlan-ng/p80211wext.c:891: warning: ‘mibitem.len’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:891: warning: ‘mibitem.status’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:891: warning: ‘mibitem.data’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c: In function ‘p80211wext_siwfrag’: drivers/staging/wlan-ng/p80211wext.c:933: warning: ‘mibitem.len’ may be used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:933: warning: ‘mibitem.status’ may be used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c: In function ‘p80211wext_giwrts’: drivers/staging/wlan-ng/p80211wext.c:826: warning: ‘mibitem.len’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:826: warning: ‘mibitem.status’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:826: warning: ‘mibitem.data’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c: In function ‘p80211wext_siwrts’: drivers/staging/wlan-ng/p80211wext.c:866: warning: ‘mibitem.len’ may be used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:866: warning: ‘mibitem.status’ may be used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c: In function ‘p80211wext_giwrate’: drivers/staging/wlan-ng/p80211wext.c:775: warning: ‘mibitem.len’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:775: warning: ‘mibitem.status’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:775: warning: ‘mibitem.data’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c: In function ‘p80211wext_giwfreq’: drivers/staging/wlan-ng/p80211wext.c:273: warning: ‘mibitem.len’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:273: warning: ‘mibitem.status’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:273: warning: ‘mibitem.data’ is used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c: In function ‘p80211wext_siwfreq’: drivers/staging/wlan-ng/p80211wext.c:320: warning: ‘mibitem.len’ may be used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c: In function ‘p80211wext_siwmode’: drivers/staging/wlan-ng/p80211wext.c:401: warning: ‘mibitem.len’ may be used uninitialized in this function drivers/staging/wlan-ng/p80211wext.c:401: warning: ‘mibitem.status’ may be used uninitialized in this function ... Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlan-ng/p80211wext.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/wlan-ng/p80211wext.c b/drivers/staging/wlan-ng/p80211wext.c index 74d8022adb24..63bdaaa7a7aa 100644 --- a/drivers/staging/wlan-ng/p80211wext.c +++ b/drivers/staging/wlan-ng/p80211wext.c @@ -134,6 +134,7 @@ static int p80211wext_dorequest(wlandevice_t *wlandev, u32 did, u32 data) int result; msg.msgcode = DIDmsg_dot11req_mibset; + memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = did; mibitem.data = data; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); @@ -269,6 +270,7 @@ static int p80211wext_giwfreq(netdevice_t *dev, int err = 0; msg.msgcode = DIDmsg_dot11req_mibget; + memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_dot11phy_dot11PhyDSSSTable_dot11CurrentChannel; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); result = p80211req_dorequest(wlandev, (u8 *) & msg); @@ -309,6 +311,7 @@ static int p80211wext_siwfreq(netdevice_t *dev, } msg.msgcode = DIDmsg_dot11req_mibset; + memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_dot11phy_dot11PhyDSSSTable_dot11CurrentChannel; mibitem.status = P80211ENUM_msgitem_status_data_ok; @@ -396,6 +399,7 @@ static int p80211wext_siwmode(netdevice_t *dev, /* Set Operation mode to the PORT TYPE RID */ msg.msgcode = DIDmsg_dot11req_mibset; + memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_p2_p2Static_p2CnfPortType; mibitem.data = (*mode == IW_MODE_ADHOC) ? 0 : 1; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); @@ -771,6 +775,7 @@ static int p80211wext_giwrate(netdevice_t *dev, int err = 0; msg.msgcode = DIDmsg_dot11req_mibget; + memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_p2_p2MAC_p2CurrentTxRate; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); result = p80211req_dorequest(wlandev, (u8 *) & msg); @@ -822,6 +827,7 @@ static int p80211wext_giwrts(netdevice_t *dev, int err = 0; msg.msgcode = DIDmsg_dot11req_mibget; + memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_dot11mac_dot11OperationTable_dot11RTSThreshold; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); result = p80211req_dorequest(wlandev, (u8 *) & msg); @@ -857,6 +863,7 @@ static int p80211wext_siwrts(netdevice_t *dev, } msg.msgcode = DIDmsg_dot11req_mibget; + memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_dot11mac_dot11OperationTable_dot11RTSThreshold; if (rts->disabled) mibitem.data = 2347; @@ -886,6 +893,7 @@ static int p80211wext_giwfrag(netdevice_t *dev, int err = 0; msg.msgcode = DIDmsg_dot11req_mibget; + memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_dot11mac_dot11OperationTable_dot11FragmentationThreshold; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); @@ -922,6 +930,7 @@ static int p80211wext_siwfrag(netdevice_t *dev, } msg.msgcode = DIDmsg_dot11req_mibset; + memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_dot11mac_dot11OperationTable_dot11FragmentationThreshold; @@ -962,6 +971,7 @@ static int p80211wext_giwretry(netdevice_t *dev, u16 shortretry, longretry, lifetime; msg.msgcode = DIDmsg_dot11req_mibget; + memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_dot11mac_dot11OperationTable_dot11ShortRetryLimit; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); @@ -1037,6 +1047,8 @@ static int p80211wext_siwretry(netdevice_t *dev, int result; int err = 0; + memset(&mibitem, 0, sizeof(mibitem)); + if (!wlan_wext_write) { err = (-EOPNOTSUPP); goto exit; @@ -1114,6 +1126,7 @@ static int p80211wext_siwtxpow(netdevice_t *dev, } msg.msgcode = DIDmsg_dot11req_mibset; + memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_dot11phy_dot11PhyTxPowerTable_dot11CurrentTxPowerLevel; if (rrq->fixed == 0) @@ -1143,6 +1156,8 @@ static int p80211wext_giwtxpow(netdevice_t *dev, int err = 0; msg.msgcode = DIDmsg_dot11req_mibget; + + memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_dot11phy_dot11PhyTxPowerTable_dot11CurrentTxPowerLevel; -- cgit v1.2.3 From 1769fd86e13eadeca64881fb8494a17afeccbbbf Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 22 Dec 2009 15:18:28 -0800 Subject: Staging: dt3155: coding style cleanups for allocator code This fixes up the worst of the coding style errors for the allocator code. Cc: Scott Smedley Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dt3155/allocator.c | 314 ++++++++++++++++++------------------- drivers/staging/dt3155/allocator.h | 2 +- 2 files changed, 158 insertions(+), 158 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dt3155/allocator.c b/drivers/staging/dt3155/allocator.c index 90429db1c5f7..c1b85447c0e0 100644 --- a/drivers/staging/dt3155/allocator.c +++ b/drivers/staging/dt3155/allocator.c @@ -26,7 +26,7 @@ Date Programmer Description of changes made ------------------------------------------------------------------- 02-Aug-2002 NJC allocator now steps in 1MB increments, rather - than doubling its size each time. + than doubling its size each time. Also, allocator_init(u_int *) now returns (in the first arg) the size of the free space. This is no longer consistent with @@ -68,7 +68,7 @@ # define DUMP_LIST() dump_list() # ifdef __KERNEL__ /* This one if debugging is on, and kernel space */ -# define PDEBUG(fmt, args...) printk( KERN_DEBUG ALL_MSG fmt, ## args) +# define PDEBUG(fmt, args...) printk(KERN_DEBUG ALL_MSG fmt, ## args) # else /* This one for user space */ # define PDEBUG(fmt, args...) fprintf(stderr, fmt, ## args) @@ -88,8 +88,8 @@ int allocator_himem = 1; /* 0 = probe, pos. = megs, neg. = disable */ int allocator_step = 1; /* This is the step size in MB */ int allocator_probe = 1; /* This is a flag -- 1=probe, 0=don't probe */ -static unsigned long allocator_buffer = 0; /* physical address */ -static unsigned long allocator_buffer_size = 0; /* kilobytes */ +static unsigned long allocator_buffer; /* physical address */ +static unsigned long allocator_buffer_size; /* kilobytes */ /* * The allocator keeps a list of DMA areas, so multiple devices @@ -97,24 +97,23 @@ static unsigned long allocator_buffer_size = 0; /* kilobytes */ */ struct allocator_struct { - unsigned long address; - unsigned long size; - struct allocator_struct *next; + unsigned long address; + unsigned long size; + struct allocator_struct *next; }; -struct allocator_struct *allocator_list = NULL; +struct allocator_struct *allocator_list; #ifdef ALL_DEBUG static int dump_list(void) { - struct allocator_struct *ptr; + struct allocator_struct *ptr; - PDEBUG("Current list:\n"); - for (ptr = allocator_list; ptr; ptr = ptr->next) { - PDEBUG("0x%08lx (size %likB)\n",ptr->address,ptr->size>>10); - } - return 0; + PDEBUG("Current list:\n"); + for (ptr = allocator_list; ptr; ptr = ptr->next) + PDEBUG("0x%08lx (size %likB)\n", ptr->address, ptr->size>>10); + return 0; } #endif @@ -126,68 +125,69 @@ static int dump_list(void) * be used straight ahead for DMA, but needs remapping for program use). */ -unsigned long allocator_allocate_dma (unsigned long kilobytes, int prio) +unsigned long allocator_allocate_dma(unsigned long kilobytes, int prio) { - struct allocator_struct *ptr = allocator_list, *newptr; - unsigned long bytes = kilobytes << 10; - - /* check if high memory is available */ - if (!allocator_buffer) - return 0; - - /* Round it to a multiple of the pagesize */ - bytes = PAGE_ALIGN(bytes); - PDEBUG("request for %li bytes\n", bytes); - - while (ptr && ptr->next) { - if (ptr->next->address - (ptr->address + ptr->size) >= bytes) - break; /* enough space */ - ptr = ptr->next; - } - if (!ptr->next) { - DUMP_LIST(); - PDEBUG("alloc failed\n"); - return 0; /* end of list */ - } - newptr = kmalloc(sizeof(struct allocator_struct),prio); - if (!newptr) - return 0; - - /* ok, now stick it after ptr */ - newptr->address = ptr->address + ptr->size; - newptr->size = bytes; - newptr->next = ptr->next; - ptr->next = newptr; - - DUMP_LIST(); - PDEBUG("returning 0x%08lx\n",newptr->address); - return newptr->address; + struct allocator_struct *ptr = allocator_list, *newptr; + unsigned long bytes = kilobytes << 10; + + /* check if high memory is available */ + if (!allocator_buffer) + return 0; + + /* Round it to a multiple of the pagesize */ + bytes = PAGE_ALIGN(bytes); + PDEBUG("request for %li bytes\n", bytes); + + while (ptr && ptr->next) { + if (ptr->next->address - (ptr->address + ptr->size) >= bytes) + break; /* enough space */ + ptr = ptr->next; + } + if (!ptr->next) { + DUMP_LIST(); + PDEBUG("alloc failed\n"); + return 0; /* end of list */ + } + newptr = kmalloc(sizeof(struct allocator_struct), prio); + if (!newptr) + return 0; + + /* ok, now stick it after ptr */ + newptr->address = ptr->address + ptr->size; + newptr->size = bytes; + newptr->next = ptr->next; + ptr->next = newptr; + + DUMP_LIST(); + PDEBUG("returning 0x%08lx\n", newptr->address); + return newptr->address; } -int allocator_free_dma (unsigned long address) +int allocator_free_dma(unsigned long address) { - struct allocator_struct *ptr = allocator_list, *prev; + struct allocator_struct *ptr = allocator_list, *prev; - while (ptr && ptr->next) { - if (ptr->next->address == address) - break; - ptr = ptr->next; + while (ptr && ptr->next) { + if (ptr->next->address == address) + break; + ptr = ptr->next; + } + /* the one being freed is ptr->next */ + prev = ptr; ptr = ptr->next; + + if (!ptr) { + printk(KERN_ERR ALL_MSG + "free_dma(0x%08lx) but add. not allocated\n", + ptr->address); + return -EINVAL; } - /* the one being freed is ptr->next */ - prev = ptr; ptr = ptr->next; - - if (!ptr) { - printk(KERN_ERR ALL_MSG "free_dma(0x%08lx) but add. not allocated\n", - ptr->address); - return -EINVAL; - } - PDEBUGG("freeing: %08lx (%li) next %08lx\n",ptr->address,ptr->size, - ptr->next->address); - prev->next = ptr->next; - kfree(ptr); - - /* dump_list(); */ - return 0; + PDEBUGG("freeing: %08lx (%li) next %08lx\n", ptr->address, ptr->size, + ptr->next->address); + prev->next = ptr->next; + kfree(ptr); + + /* dump_list(); */ + return 0; } /* ======================================================================== @@ -198,99 +198,99 @@ int allocator_free_dma (unsigned long address) */ int allocator_init(u_long *allocator_max) { - /* check how much free memory is there */ - - volatile void *remapped; - unsigned long max; - unsigned long trial_size = allocator_himem<<20; - unsigned long last_trial = 0; - unsigned long step = allocator_step<<20; - unsigned long i=0; - struct allocator_struct *head, *tail; - char test_string[]="0123456789abcde"; /* 16 bytes */ - - PDEBUGG("himem = %i\n",allocator_himem); - if (allocator_himem < 0) /* don't even try */ - return -EINVAL; - - if (!trial_size) trial_size = 1<<20; /* not specified: try one meg */ - - while (1) { - remapped = ioremap(__pa(high_memory), trial_size); - if (!remapped) - { - PDEBUGG("%li megs failed!\n",trial_size>>20); - break; - } - PDEBUGG("Trying %li megs (at %p, %p)\n",trial_size>>20, - (void *)__pa(high_memory), remapped); - for (i=last_trial; i>20); - break; - } - if (!allocator_probe) break; - } - PDEBUG("%li megs (%li k, %li b)\n",i>>20,i>>10,i); - allocator_buffer_size = i>>10; /* kilobytes */ - allocator_buffer = __pa(high_memory); - if (!allocator_buffer_size) { - printk(KERN_WARNING ALL_MSG "no free high memory to use\n"); - return -ENOMEM; - } - - /* - * to simplify things, always have two cells in the list: - * the first and the last. This avoids some conditionals and - * extra code when allocating and deallocating: we only play - * in the middle of the list - */ - head = kmalloc(sizeof(struct allocator_struct),GFP_KERNEL); - if (!head) - return -ENOMEM; - tail = kmalloc(sizeof(struct allocator_struct),GFP_KERNEL); - if (!tail) { - kfree(head); - return -ENOMEM; - } - - max = allocator_buffer_size<<10; - - head->size = tail->size = 0; - head->address = allocator_buffer; - tail->address = allocator_buffer + max; - head->next = tail; - tail->next = NULL; - allocator_list = head; - - *allocator_max = allocator_buffer_size; /* Back to the user code, in KB */ - - return 0; /* ok, ready */ + /* check how much free memory is there */ + void *remapped; + unsigned long max; + unsigned long trial_size = allocator_himem<<20; + unsigned long last_trial = 0; + unsigned long step = allocator_step<<20; + unsigned long i = 0; + struct allocator_struct *head, *tail; + char test_string[] = "0123456789abcde"; /* 16 bytes */ + + PDEBUGG("himem = %i\n", allocator_himem); + if (allocator_himem < 0) /* don't even try */ + return -EINVAL; + + if (!trial_size) + trial_size = 1<<20; /* not specified: try one meg */ + + while (1) { + remapped = ioremap(__pa(high_memory), trial_size); + if (!remapped) { + PDEBUGG("%li megs failed!\n", trial_size>>20); + break; + } + PDEBUGG("Trying %li megs (at %p, %p)\n", trial_size>>20, + (void *)__pa(high_memory), remapped); + for (i = last_trial; i < trial_size; i += 16) { + strcpy((char *)(remapped)+i, test_string); + if (strcmp((char *)(remapped)+i, test_string)) + break; + } + iounmap((void *)remapped); + schedule(); + last_trial = trial_size; + if (i == trial_size) + trial_size += step; /* increment, if all went well */ + else { + PDEBUGG("%li megs copy test failed!\n", trial_size>>20); + break; + } + if (!allocator_probe) + break; + } + PDEBUG("%li megs (%li k, %li b)\n", i>>20, i>>10, i); + allocator_buffer_size = i>>10; /* kilobytes */ + allocator_buffer = __pa(high_memory); + if (!allocator_buffer_size) { + printk(KERN_WARNING ALL_MSG "no free high memory to use\n"); + return -ENOMEM; + } + + /* + * to simplify things, always have two cells in the list: + * the first and the last. This avoids some conditionals and + * extra code when allocating and deallocating: we only play + * in the middle of the list + */ + head = kmalloc(sizeof(struct allocator_struct), GFP_KERNEL); + if (!head) + return -ENOMEM; + tail = kmalloc(sizeof(struct allocator_struct), GFP_KERNEL); + if (!tail) { + kfree(head); + return -ENOMEM; + } + + max = allocator_buffer_size<<10; + + head->size = tail->size = 0; + head->address = allocator_buffer; + tail->address = allocator_buffer + max; + head->next = tail; + tail->next = NULL; + allocator_list = head; + + /* Back to the user code, in KB */ + *allocator_max = allocator_buffer_size; + + return 0; /* ok, ready */ } void allocator_cleanup(void) { - struct allocator_struct *ptr, *next; + struct allocator_struct *ptr, *next; - for (ptr = allocator_list; ptr; ptr = next) { - next = ptr->next; - PDEBUG("freeing list: 0x%08lx\n",ptr->address); - kfree(ptr); - } + for (ptr = allocator_list; ptr; ptr = next) { + next = ptr->next; + PDEBUG("freeing list: 0x%08lx\n", ptr->address); + kfree(ptr); + } - allocator_buffer = 0; - allocator_buffer_size = 0; - allocator_list = NULL; + allocator_buffer = 0; + allocator_buffer_size = 0; + allocator_list = NULL; } diff --git a/drivers/staging/dt3155/allocator.h b/drivers/staging/dt3155/allocator.h index ecc8680e7d45..a2f90ffa3d10 100644 --- a/drivers/staging/dt3155/allocator.h +++ b/drivers/staging/dt3155/allocator.h @@ -23,6 +23,6 @@ */ void allocator_free_dma(unsigned long address); -unsigned long allocator_allocate_dma (unsigned long kilobytes, int priority); +unsigned long allocator_allocate_dma(unsigned long kilobytes, int priority); int allocator_init(u_long *); void allocator_cleanup(void); -- cgit v1.2.3 From 8c6356e2a57044614799de3f1e7f40561724893a Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 22 Dec 2009 15:19:21 -0800 Subject: Staging: dt3155: coding style cleanups for the .h files This cleans up some of the coding style issues in the .h files. More remains to be done. Cc: Scott Smedley Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dt3155/dt3155.h | 148 ++++++++++++++++++------------------ drivers/staging/dt3155/dt3155_drv.h | 6 +- drivers/staging/dt3155/dt3155_io.h | 73 +++++++++--------- drivers/staging/dt3155/dt3155_isr.h | 20 ++--- 4 files changed, 120 insertions(+), 127 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dt3155/dt3155.h b/drivers/staging/dt3155/dt3155.h index 2e158151a755..2a01e017d5fe 100644 --- a/drivers/staging/dt3155/dt3155.h +++ b/drivers/staging/dt3155/dt3155.h @@ -1,7 +1,7 @@ /* Copyright 1996,2002,2005 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, - Jason Lapenta, Scott Smedley + Jason Lapenta, Scott Smedley This file is part of the DT3155 Device Driver. @@ -20,8 +20,6 @@ along with the DT3155 Device Driver; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - $Id: dt3155.h,v 1.11 2005/08/09 06:08:51 ssmedley Exp $ - -- Changes -- Date Programmer Description of changes made @@ -56,120 +54,118 @@ MA 02111-1307 USA /* Can be 1 or 2 */ #define MAXBOARDS 1 -#define BOARD_MAX_BUFFS 3 -#define MAXBUFFERS BOARD_MAX_BUFFS*MAXBOARDS +#define BOARD_MAX_BUFFS 3 +#define MAXBUFFERS (BOARD_MAX_BUFFS*MAXBOARDS) -#define PCI_PAGE_SIZE (1 << 12) +#define PCI_PAGE_SIZE (1 << 12) #ifdef CCIR -#define DT3155_MAX_ROWS 576 -#define DT3155_MAX_COLS 768 -#define FORMAT50HZ TRUE +#define DT3155_MAX_ROWS 576 +#define DT3155_MAX_COLS 768 +#define FORMAT50HZ TRUE #else -#define DT3155_MAX_ROWS 480 -#define DT3155_MAX_COLS 640 -#define FORMAT50HZ FALSE +#define DT3155_MAX_ROWS 480 +#define DT3155_MAX_COLS 640 +#define FORMAT50HZ FALSE #endif /* Configuration structure */ struct dt3155_config_s { - u_int acq_mode; - u_int cols, rows; - u_int continuous; + u_int acq_mode; + u_int cols, rows; + u_int continuous; }; /* hold data for each frame */ -typedef struct -{ - u_long addr; /* address of the buffer with the frame */ - u_long tag; /* unique number for the frame */ - struct timeval time; /* time that capture took place */ +typedef struct { + u_long addr; /* address of the buffer with the frame */ + u_long tag; /* unique number for the frame */ + struct timeval time; /* time that capture took place */ } frame_info_t; -/* Structure for interrupt and buffer handling. */ -/* This is the setup for 1 card */ +/* + * Structure for interrupt and buffer handling. + * This is the setup for 1 card + */ struct dt3155_fbuffer_s { - int nbuffers; - - frame_info_t frame_info[ BOARD_MAX_BUFFS ]; + int nbuffers; - int empty_buffers[ BOARD_MAX_BUFFS ]; /* indexes empty frames */ - int empty_len; /* Number of empty buffers */ - /* Zero means empty */ + frame_info_t frame_info[BOARD_MAX_BUFFS]; - int active_buf; /* Where data is currently dma'ing */ - int locked_buf; /* Buffers used by user */ + int empty_buffers[BOARD_MAX_BUFFS]; /* indexes empty frames */ + int empty_len; /* Number of empty buffers */ + /* Zero means empty */ - int ready_que[ BOARD_MAX_BUFFS ]; - u_long ready_head; /* The most recent buffer located here */ - u_long ready_len; /* The number of ready buffers */ + int active_buf; /* Where data is currently dma'ing */ + int locked_buf; /* Buffers used by user */ - int even_happened; - int even_stopped; + int ready_que[BOARD_MAX_BUFFS]; + u_long ready_head; /* The most recent buffer located here */ + u_long ready_len; /* The number of ready buffers */ - int stop_acquire; /* Flag to stop interrupts */ - u_long frame_count; /* Counter for frames acquired by this card */ + int even_happened; + int even_stopped; + int stop_acquire; /* Flag to stop interrupts */ + u_long frame_count; /* Counter for frames acquired by this card */ }; -#define DT3155_MODE_FRAME 1 -#define DT3155_MODE_FIELD 2 +#define DT3155_MODE_FRAME 1 +#define DT3155_MODE_FIELD 2 -#define DT3155_SNAP 1 -#define DT3155_ACQ 2 +#define DT3155_SNAP 1 +#define DT3155_ACQ 2 /* There is one status structure for each card. */ -typedef struct dt3155_status_s -{ - int fixed_mode; /* if 1, we are in fixed frame mode */ - u_long reg_addr; /* Register address for a single card */ - u_long mem_addr; /* Buffer start addr for this card */ - u_long mem_size; /* This is the amount of mem available */ - u_int irq; /* this card's irq */ - struct dt3155_config_s config; /* configuration struct */ - struct dt3155_fbuffer_s fbuffer;/* frame buffer state struct */ - u_long state; /* this card's state */ - u_int device_installed; /* Flag if installed. 1=installed */ +typedef struct dt3155_status_s { + int fixed_mode; /* if 1, we are in fixed frame mode */ + u_long reg_addr; /* Register address for a single card */ + u_long mem_addr; /* Buffer start addr for this card */ + u_long mem_size; /* This is the amount of mem available */ + u_int irq; /* this card's irq */ + struct dt3155_config_s config; /* configuration struct */ + struct dt3155_fbuffer_s fbuffer; /* frame buffer state struct */ + u_long state; /* this card's state */ + u_int device_installed; /* Flag if installed. 1=installed */ } dt3155_status_t; /* Reference to global status structure */ extern struct dt3155_status_s dt3155_status[MAXBOARDS]; -#define DT3155_STATE_IDLE 0x00 -#define DT3155_STATE_FRAME 0x01 -#define DT3155_STATE_FLD 0x02 -#define DT3155_STATE_STOP 0x100 -#define DT3155_STATE_ERROR 0x200 -#define DT3155_STATE_MODE 0x0ff +#define DT3155_STATE_IDLE 0x00 +#define DT3155_STATE_FRAME 0x01 +#define DT3155_STATE_FLD 0x02 +#define DT3155_STATE_STOP 0x100 +#define DT3155_STATE_ERROR 0x200 +#define DT3155_STATE_MODE 0x0ff -#define DT3155_IOC_MAGIC '!' +#define DT3155_IOC_MAGIC '!' -#define DT3155_SET_CONFIG _IOW( DT3155_IOC_MAGIC, 1, struct dt3155_config_s ) -#define DT3155_GET_CONFIG _IOR( DT3155_IOC_MAGIC, 2, struct dt3155_status_s ) -#define DT3155_STOP _IO( DT3155_IOC_MAGIC, 3 ) -#define DT3155_START _IO( DT3155_IOC_MAGIC, 4 ) -#define DT3155_FLUSH _IO( DT3155_IOC_MAGIC, 5 ) -#define DT3155_IOC_MAXNR 5 +#define DT3155_SET_CONFIG _IOW(DT3155_IOC_MAGIC, 1, struct dt3155_config_s) +#define DT3155_GET_CONFIG _IOR(DT3155_IOC_MAGIC, 2, struct dt3155_status_s) +#define DT3155_STOP _IO(DT3155_IOC_MAGIC, 3) +#define DT3155_START _IO(DT3155_IOC_MAGIC, 4) +#define DT3155_FLUSH _IO(DT3155_IOC_MAGIC, 5) +#define DT3155_IOC_MAXNR 5 /* Error codes */ -#define DT_ERR_NO_BUFFERS 0x10000 /* not used but it might be one day - SS */ -#define DT_ERR_CORRUPT 0x20000 -#define DT_ERR_OVERRUN 0x30000 -#define DT_ERR_I2C_TIMEOUT 0x40000 -#define DT_ERR_MASK 0xff0000/* not used but it might be one day - SS */ +#define DT_ERR_NO_BUFFERS 0x10000 /* not used but it might be one day */ +#define DT_ERR_CORRUPT 0x20000 +#define DT_ERR_OVERRUN 0x30000 +#define DT_ERR_I2C_TIMEOUT 0x40000 +#define DT_ERR_MASK 0xff0000/* not used but it might be one day */ /* User code will probably want to declare one of these for each card */ -typedef struct dt3155_read_s -{ - u_long offset; - u_long frame_seq; - u_long state; +typedef struct dt3155_read_s { + u_long offset; + u_long frame_seq; + u_long state; - frame_info_t frame_info; + frame_info_t frame_info; } dt3155_read_t; #endif /* _DT3155_inc */ diff --git a/drivers/staging/dt3155/dt3155_drv.h b/drivers/staging/dt3155/dt3155_drv.h index 92a92dc2736c..dc110b76e463 100644 --- a/drivers/staging/dt3155/dt3155_drv.h +++ b/drivers/staging/dt3155/dt3155_drv.h @@ -1,7 +1,7 @@ /* Copyright 1996,2002 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, - Scott Smedley + Scott Smedley This file is part of the DT3155 Device Driver. @@ -25,7 +25,7 @@ MA 02111-1307 USA #define DT3155_DRV_INC /* kernel logical address of the frame grabbers */ -extern u_char *dt3155_lbase[ MAXBOARDS ]; +extern u_char *dt3155_lbase[MAXBOARDS]; /* kernel logical address of ram buffer */ extern u_char *dt3155_bbase; @@ -35,7 +35,7 @@ extern u_char *dt3155_bbase; #include /* need access to LINUX_VERSION_CODE */ /* wait queue for reads */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,1) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 3, 1) extern wait_queue_head_t dt3155_read_wait_queue[MAXBOARDS]; #else extern struct wait_queue *dt3155_read_wait_queue[MAXBOARDS]; diff --git a/drivers/staging/dt3155/dt3155_io.h b/drivers/staging/dt3155/dt3155_io.h index c1174ab7eac5..67df27fc6a8a 100644 --- a/drivers/staging/dt3155/dt3155_io.h +++ b/drivers/staging/dt3155/dt3155_io.h @@ -1,7 +1,7 @@ /* Copyright 1996,2002 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, - Jason Lapenta, Scott Smedley + Jason Lapenta, Scott Smedley This file is part of the DT3155 Device Driver. @@ -36,8 +36,8 @@ MA 02111-1307 USA /* macros to access registers */ -#define WriteMReg(Address, Data) * ((u_long *) (Address)) = Data -#define ReadMReg(Address, Data) Data = * ((u_long *) (Address)) +#define WriteMReg(Address, Data) (*((u_long *)(Address)) = Data) +#define ReadMReg(Address, Data) (Data = *((u_long *)(Address))) /***************** 32 bit register globals **************/ @@ -240,12 +240,11 @@ typedef union iic_csr2_tag { * dma_upper_lmt_tag */ typedef union dma_upper_lmt_tag { - u_long reg; - struct - { - u_long DMA_UPPER_LMT_VAL : 24; - u_long : 8; - } fld; + u_long reg; + struct { + u_long DMA_UPPER_LMT_VAL:24; + u_long :8; + } fld; } DMA_UPPER_LMT_R; @@ -253,12 +252,12 @@ typedef union dma_upper_lmt_tag { * Global declarations of local copies * of boards' 32 bit registers ***************************************/ -extern u_long even_dma_start_r; /* bit 0 should always be 0 */ -extern u_long odd_dma_start_r; /* .. */ -extern u_long even_dma_stride_r; /* bits 0&1 should always be 0 */ -extern u_long odd_dma_stride_r; /* .. */ -extern u_long even_pixel_fmt_r; -extern u_long odd_pixel_fmt_r; +extern u_long even_dma_start_r; /* bit 0 should always be 0 */ +extern u_long odd_dma_start_r; /* .. */ +extern u_long even_dma_stride_r; /* bits 0&1 should always be 0 */ +extern u_long odd_dma_stride_r; /* .. */ +extern u_long even_pixel_fmt_r; +extern u_long odd_pixel_fmt_r; extern FIFO_TRIGGER_R fifo_trigger_r; extern XFER_MODE_R xfer_mode_r; @@ -266,8 +265,8 @@ extern CSR1_R csr1_r; extern RETRY_WAIT_CNT_R retry_wait_cnt_r; extern INT_CSR_R int_csr_r; -extern u_long even_fld_mask_r; -extern u_long odd_fld_mask_r; +extern u_long even_fld_mask_r; +extern u_long odd_fld_mask_r; extern MASK_LENGTH_R mask_length_r; extern FIFO_FLAG_CNT_R fifo_flag_cnt_r; @@ -301,28 +300,26 @@ extern DMA_UPPER_LMT_R odd_dma_upper_lmt_r; /******** Assignments and Typedefs for 8 bit I2C Registers********************/ typedef union i2c_csr2_tag { - u_char reg; - struct - { - u_char CHROM_FIL : 1; - u_char SYNC_SNTL : 1; - u_char HZ50 : 1; - u_char SYNC_PRESENT : 1; - u_char BUSY_EVE : 1; - u_char BUSY_ODD : 1; - u_char DISP_PASS : 1; - } fld; + u_char reg; + struct { + u_char CHROM_FIL:1; + u_char SYNC_SNTL:1; + u_char HZ50:1; + u_char SYNC_PRESENT:1; + u_char BUSY_EVE:1; + u_char BUSY_ODD:1; + u_char DISP_PASS:1; + } fld; } I2C_CSR2; typedef union i2c_even_csr_tag { - u_char reg; - struct - { - u_char DONE_EVE : 1; - u_char SNGL_EVE : 1; - u_char ERROR_EVE : 1; - u_char : 5; - } fld; + u_char reg; + struct { + u_char DONE_EVE:1; + u_char SNGL_EVE:1; + u_char ERROR_EVE:1; + u_char :5; + } fld; } I2C_EVEN_CSR; typedef union i2c_odd_csr_tag { @@ -394,7 +391,7 @@ extern u_char i2c_pm_lut_data; /* access 8-bit IIC registers */ -extern int ReadI2C (u_char * lpReg, u_short wIregIndex, u_char * byVal); -extern int WriteI2C (u_char * lpReg, u_short wIregIndex, u_char byVal); +extern int ReadI2C(u_char *lpReg, u_short wIregIndex, u_char *byVal); +extern int WriteI2C(u_char *lpReg, u_short wIregIndex, u_char byVal); #endif diff --git a/drivers/staging/dt3155/dt3155_isr.h b/drivers/staging/dt3155/dt3155_isr.h index b117b504e277..c77a1008c09c 100644 --- a/drivers/staging/dt3155/dt3155_isr.h +++ b/drivers/staging/dt3155/dt3155_isr.h @@ -1,7 +1,7 @@ /* Copyright 1996,2002 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, - Jason Lapenta, Scott Smedley + Jason Lapenta, Scott Smedley This file is part of the DT3155 Device Driver. @@ -33,8 +33,8 @@ MA 02111-1307 USA */ -#ifndef DT3155_ISR_H -#define DT3155_ISR_H +#ifndef DT3155_ISR_H +#define DT3155_ISR_H extern struct dt3155_fbuffer_s *dt3155_fbuffer[MAXBOARDS]; @@ -62,16 +62,16 @@ int dt3155_flush(int minor); * Simple array based que struct **********************************/ -bool are_empty_buffers( int minor ); -void push_empty( int index, int minor ); +bool are_empty_buffers(int minor); +void push_empty(int index, int minor); -int pop_empty( int minor ); +int pop_empty(int minor); -bool is_ready_buf_empty( int minor ); -bool is_ready_buf_full( int minor ); +bool is_ready_buf_empty(int minor); +bool is_ready_buf_full(int minor); -void push_ready( int minor, int index ); -int pop_ready( int minor ); +void push_ready(int minor, int index); +int pop_ready(int minor); #endif -- cgit v1.2.3 From a945db65436a2666927b555d752e67a1bd193a9c Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 22 Dec 2009 16:29:26 -0800 Subject: staging: remove the b3dfg driver It has no users, and no developers to maintain it to get it merged into mainline. So sad. Cc: Daniel Drake Cc: Justin Bronder Cc: Duane Griffin Signed-off-by: Greg Kroah-Hartman --- drivers/staging/Kconfig | 2 - drivers/staging/Makefile | 1 - drivers/staging/b3dfg/Kconfig | 10 - drivers/staging/b3dfg/Makefile | 1 - drivers/staging/b3dfg/TODO | 4 - drivers/staging/b3dfg/b3dfg.c | 1100 ---------------------------------------- 6 files changed, 1118 deletions(-) delete mode 100644 drivers/staging/b3dfg/Kconfig delete mode 100644 drivers/staging/b3dfg/Makefile delete mode 100644 drivers/staging/b3dfg/TODO delete mode 100644 drivers/staging/b3dfg/b3dfg.c (limited to 'drivers') diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 02cde3989c5c..a1dee5c59775 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -89,8 +89,6 @@ source "drivers/staging/dream/Kconfig" source "drivers/staging/pohmelfs/Kconfig" -source "drivers/staging/b3dfg/Kconfig" - source "drivers/staging/phison/Kconfig" source "drivers/staging/p9auth/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index 9d47d42e73ce..f7d34eec6740 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -27,7 +27,6 @@ obj-$(CONFIG_INPUT_MIMIO) += mimio/ obj-$(CONFIG_TRANZPORT) += frontier/ obj-$(CONFIG_DREAM) += dream/ obj-$(CONFIG_POHMELFS) += pohmelfs/ -obj-$(CONFIG_B3DFG) += b3dfg/ obj-$(CONFIG_IDE_PHISON) += phison/ obj-$(CONFIG_PLAN9AUTH) += p9auth/ obj-$(CONFIG_LINE6_USB) += line6/ diff --git a/drivers/staging/b3dfg/Kconfig b/drivers/staging/b3dfg/Kconfig deleted file mode 100644 index 9e6573cf97d3..000000000000 --- a/drivers/staging/b3dfg/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -config B3DFG - tristate "Brontes 3d Frame Framegrabber" - depends on PCI - default n - ---help--- - This driver provides support for the Brontes 3d Framegrabber - PCI card. - - To compile this driver as a module, choose M here. The module - will be called b3dfg. diff --git a/drivers/staging/b3dfg/Makefile b/drivers/staging/b3dfg/Makefile deleted file mode 100644 index 91f439ffc174..000000000000 --- a/drivers/staging/b3dfg/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-$(CONFIG_B3DFG) += b3dfg.o diff --git a/drivers/staging/b3dfg/TODO b/drivers/staging/b3dfg/TODO deleted file mode 100644 index f5a9298b9ac1..000000000000 --- a/drivers/staging/b3dfg/TODO +++ /dev/null @@ -1,4 +0,0 @@ - - - queue/wait buffer presents filltime results for each frame? - - counting of dropped frames - - review endianness diff --git a/drivers/staging/b3dfg/b3dfg.c b/drivers/staging/b3dfg/b3dfg.c deleted file mode 100644 index 4a43c51c172a..000000000000 --- a/drivers/staging/b3dfg/b3dfg.c +++ /dev/null @@ -1,1100 +0,0 @@ - /* - * Brontes PCI frame grabber driver - * - * Copyright (C) 2008 3M Company - * Contact: Justin Bronder - * Original Authors: Daniel Drake - * Duane Griffin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static unsigned int b3dfg_nbuf = 2; - -module_param_named(buffer_count, b3dfg_nbuf, uint, 0444); - -MODULE_PARM_DESC(buffer_count, "Number of buffers (min 2, default 2)"); - -MODULE_AUTHOR("Daniel Drake "); -MODULE_DESCRIPTION("Brontes frame grabber driver"); -MODULE_LICENSE("GPL"); - -#define DRIVER_NAME "b3dfg" -#define B3DFG_MAX_DEVS 4 -#define B3DFG_FRAMES_PER_BUFFER 3 - -#define B3DFG_BAR_REGS 0 -#define B3DFG_REGS_LENGTH 0x10000 - -#define B3DFG_IOC_MAGIC 0xb3 /* dfg :-) */ -#define B3DFG_IOCGFRMSZ _IOR(B3DFG_IOC_MAGIC, 1, int) -#define B3DFG_IOCTNUMBUFS _IO(B3DFG_IOC_MAGIC, 2) -#define B3DFG_IOCTTRANS _IO(B3DFG_IOC_MAGIC, 3) -#define B3DFG_IOCTQUEUEBUF _IO(B3DFG_IOC_MAGIC, 4) -#define B3DFG_IOCTPOLLBUF _IOWR(B3DFG_IOC_MAGIC, 5, struct b3dfg_poll) -#define B3DFG_IOCTWAITBUF _IOWR(B3DFG_IOC_MAGIC, 6, struct b3dfg_wait) -#define B3DFG_IOCGWANDSTAT _IOR(B3DFG_IOC_MAGIC, 7, int) - -enum { - /* number of 4kb pages per frame */ - B3D_REG_FRM_SIZE = 0x0, - - /* bit 0: set to enable interrupts - * bit 1: set to enable cable status change interrupts */ - B3D_REG_HW_CTRL = 0x4, - - /* bit 0-1 - 1-based ID of next pending frame transfer (0 = none) - * bit 2 indicates the previous DMA transfer has completed - * bit 3 indicates wand cable status change - * bit 8:15 - counter of number of discarded triplets */ - B3D_REG_DMA_STS = 0x8, - - /* bit 0: wand status (1 = present, 0 = disconnected) */ - B3D_REG_WAND_STS = 0xc, - - /* bus address for DMA transfers. lower 2 bits must be zero because DMA - * works with 32 bit word size. */ - B3D_REG_EC220_DMA_ADDR = 0x8000, - - /* bit 20:0 - number of 32 bit words to be transferred - * bit 21:31 - reserved */ - B3D_REG_EC220_TRF_SIZE = 0x8004, - - /* bit 0 - error bit - * bit 1 - interrupt bit (set to generate interrupt at end of transfer) - * bit 2 - start bit (set to start transfer) - * bit 3 - direction (0 = DMA_TO_DEVICE, 1 = DMA_FROM_DEVICE - * bit 4:31 - reserved */ - B3D_REG_EC220_DMA_STS = 0x8008, -}; - -enum b3dfg_buffer_state { - B3DFG_BUFFER_POLLED = 0, - B3DFG_BUFFER_PENDING, - B3DFG_BUFFER_POPULATED, -}; - -struct b3dfg_buffer { - unsigned char *frame[B3DFG_FRAMES_PER_BUFFER]; - struct list_head list; - u8 state; -}; - -struct b3dfg_dev { - - /* no protection needed: all finalized at initialization time */ - struct pci_dev *pdev; - struct cdev chardev; - struct device *dev; - void __iomem *regs; - unsigned int frame_size; - - /* - * Protects buffer state, including buffer_queue, triplet_ready, - * cur_dma_frame_idx & cur_dma_frame_addr. - */ - spinlock_t buffer_lock; - struct b3dfg_buffer *buffers; - struct list_head buffer_queue; - - /* Last frame in triplet transferred (-1 if none). */ - int cur_dma_frame_idx; - - /* Current frame's address for DMA. */ - dma_addr_t cur_dma_frame_addr; - - /* - * Protects cstate_tstamp. - * Nests inside buffer_lock. - */ - spinlock_t cstate_lock; - unsigned long cstate_tstamp; - - /* - * Protects triplets_dropped. - * Nests inside buffers_lock. - */ - spinlock_t triplets_dropped_lock; - unsigned int triplets_dropped; - - wait_queue_head_t buffer_waitqueue; - - unsigned int transmission_enabled:1; - unsigned int triplet_ready:1; -}; - -static u8 b3dfg_devices[B3DFG_MAX_DEVS]; - -static struct class *b3dfg_class; -static dev_t b3dfg_devt; - -static const struct pci_device_id b3dfg_ids[] __devinitdata = { - { PCI_DEVICE(0x0b3d, 0x0001) }, - { }, -}; - -MODULE_DEVICE_TABLE(pci, b3dfg_ids); - -/***** user-visible types *****/ - -struct b3dfg_poll { - int buffer_idx; - unsigned int triplets_dropped; -}; - -struct b3dfg_wait { - int buffer_idx; - unsigned int timeout; - unsigned int triplets_dropped; -}; - -/**** register I/O ****/ - -static u32 b3dfg_read32(struct b3dfg_dev *fgdev, u16 reg) -{ - return ioread32(fgdev->regs + reg); -} - -static void b3dfg_write32(struct b3dfg_dev *fgdev, u16 reg, u32 value) -{ - iowrite32(value, fgdev->regs + reg); -} - -/**** buffer management ****/ - -/* - * Program EC220 for transfer of a specific frame. - * Called with buffer_lock held. - */ -static int setup_frame_transfer(struct b3dfg_dev *fgdev, - struct b3dfg_buffer *buf, int frame) -{ - unsigned char *frm_addr; - dma_addr_t frm_addr_dma; - unsigned int frm_size = fgdev->frame_size; - - frm_addr = buf->frame[frame]; - frm_addr_dma = pci_map_single(fgdev->pdev, frm_addr, - frm_size, PCI_DMA_FROMDEVICE); - if (pci_dma_mapping_error(fgdev->pdev, frm_addr_dma)) - return -ENOMEM; - - fgdev->cur_dma_frame_addr = frm_addr_dma; - fgdev->cur_dma_frame_idx = frame; - - b3dfg_write32(fgdev, B3D_REG_EC220_DMA_ADDR, - cpu_to_le32(frm_addr_dma)); - b3dfg_write32(fgdev, B3D_REG_EC220_TRF_SIZE, - cpu_to_le32(frm_size >> 2)); - b3dfg_write32(fgdev, B3D_REG_EC220_DMA_STS, 0xf); - - return 0; -} - -/* Caller should hold buffer lock */ -static void dequeue_all_buffers(struct b3dfg_dev *fgdev) -{ - int i; - for (i = 0; i < b3dfg_nbuf; i++) { - struct b3dfg_buffer *buf = &fgdev->buffers[i]; - buf->state = B3DFG_BUFFER_POLLED; - list_del_init(&buf->list); - } -} - -/* queue a buffer to receive data */ -static int queue_buffer(struct b3dfg_dev *fgdev, int bufidx) -{ - struct device *dev = &fgdev->pdev->dev; - struct b3dfg_buffer *buf; - unsigned long flags; - int r = 0; - - spin_lock_irqsave(&fgdev->buffer_lock, flags); - if (bufidx < 0 || bufidx >= b3dfg_nbuf) { - dev_dbg(dev, "Invalid buffer index, %d\n", bufidx); - r = -ENOENT; - goto out; - } - buf = &fgdev->buffers[bufidx]; - - if (unlikely(buf->state == B3DFG_BUFFER_PENDING)) { - dev_dbg(dev, "buffer %d is already queued\n", bufidx); - r = -EINVAL; - goto out; - } - - buf->state = B3DFG_BUFFER_PENDING; - list_add_tail(&buf->list, &fgdev->buffer_queue); - - if (fgdev->transmission_enabled && fgdev->triplet_ready) { - dev_dbg(dev, "triplet is ready, pushing immediately\n"); - fgdev->triplet_ready = 0; - r = setup_frame_transfer(fgdev, buf, 0); - if (r) - dev_err(dev, "unable to map DMA buffer\n"); - } - -out: - spin_unlock_irqrestore(&fgdev->buffer_lock, flags); - return r; -} - -/* non-blocking buffer poll. returns 1 if data is present in the buffer, - * 0 otherwise */ -static int poll_buffer(struct b3dfg_dev *fgdev, void __user *arg) -{ - struct device *dev = &fgdev->pdev->dev; - struct b3dfg_poll p; - struct b3dfg_buffer *buf; - unsigned long flags; - int r = 1; - int arg_out = 0; - - if (copy_from_user(&p, arg, sizeof(p))) - return -EFAULT; - - if (unlikely(!fgdev->transmission_enabled)) { - dev_dbg(dev, "cannot poll, transmission disabled\n"); - return -EINVAL; - } - - if (p.buffer_idx < 0 || p.buffer_idx >= b3dfg_nbuf) - return -ENOENT; - - buf = &fgdev->buffers[p.buffer_idx]; - - spin_lock_irqsave(&fgdev->buffer_lock, flags); - - if (likely(buf->state == B3DFG_BUFFER_POPULATED)) { - arg_out = 1; - buf->state = B3DFG_BUFFER_POLLED; - - /* IRQs already disabled by spin_lock_irqsave above. */ - spin_lock(&fgdev->triplets_dropped_lock); - p.triplets_dropped = fgdev->triplets_dropped; - fgdev->triplets_dropped = 0; - spin_unlock(&fgdev->triplets_dropped_lock); - } else { - r = 0; - } - - spin_unlock_irqrestore(&fgdev->buffer_lock, flags); - - if (arg_out && copy_to_user(arg, &p, sizeof(p))) - r = -EFAULT; - - return r; -} - -static unsigned long get_cstate_change(struct b3dfg_dev *fgdev) -{ - unsigned long flags, when; - - spin_lock_irqsave(&fgdev->cstate_lock, flags); - when = fgdev->cstate_tstamp; - spin_unlock_irqrestore(&fgdev->cstate_lock, flags); - return when; -} - -static int is_event_ready(struct b3dfg_dev *fgdev, struct b3dfg_buffer *buf, - unsigned long when) -{ - int result; - unsigned long flags; - - spin_lock_irqsave(&fgdev->buffer_lock, flags); - spin_lock(&fgdev->cstate_lock); - result = (!fgdev->transmission_enabled || - buf->state == B3DFG_BUFFER_POPULATED || - when != fgdev->cstate_tstamp); - spin_unlock(&fgdev->cstate_lock); - spin_unlock_irqrestore(&fgdev->buffer_lock, flags); - - return result; -} - -/* sleep until a specific buffer becomes populated */ -static int wait_buffer(struct b3dfg_dev *fgdev, void __user *arg) -{ - struct device *dev = &fgdev->pdev->dev; - struct b3dfg_wait w; - struct b3dfg_buffer *buf; - unsigned long flags, when; - int r; - - if (copy_from_user(&w, arg, sizeof(w))) - return -EFAULT; - - if (!fgdev->transmission_enabled) { - dev_dbg(dev, "cannot wait, transmission disabled\n"); - return -EINVAL; - } - - if (w.buffer_idx < 0 || w.buffer_idx >= b3dfg_nbuf) - return -ENOENT; - - buf = &fgdev->buffers[w.buffer_idx]; - - spin_lock_irqsave(&fgdev->buffer_lock, flags); - - if (buf->state == B3DFG_BUFFER_POPULATED) { - r = w.timeout; - goto out_triplets_dropped; - } - - spin_unlock_irqrestore(&fgdev->buffer_lock, flags); - - when = get_cstate_change(fgdev); - if (w.timeout > 0) { - r = wait_event_interruptible_timeout(fgdev->buffer_waitqueue, - is_event_ready(fgdev, buf, when), - (w.timeout * HZ) / 1000); - - if (unlikely(r < 0)) - goto out; - - w.timeout = r * 1000 / HZ; - } else { - r = wait_event_interruptible(fgdev->buffer_waitqueue, - is_event_ready(fgdev, buf, when)); - - if (unlikely(r)) { - r = -ERESTARTSYS; - goto out; - } - } - - /* TODO: Inform the user via field(s) in w? */ - if (!fgdev->transmission_enabled || when != get_cstate_change(fgdev)) { - r = -EINVAL; - goto out; - } - - spin_lock_irqsave(&fgdev->buffer_lock, flags); - - if (buf->state != B3DFG_BUFFER_POPULATED) { - r = -ETIMEDOUT; - goto out_unlock; - } - - buf->state = B3DFG_BUFFER_POLLED; - -out_triplets_dropped: - - /* IRQs already disabled by spin_lock_irqsave above. */ - spin_lock(&fgdev->triplets_dropped_lock); - w.triplets_dropped = fgdev->triplets_dropped; - fgdev->triplets_dropped = 0; - spin_unlock(&fgdev->triplets_dropped_lock); - -out_unlock: - spin_unlock_irqrestore(&fgdev->buffer_lock, flags); - if (copy_to_user(arg, &w, sizeof(w))) - r = -EFAULT; -out: - return r; -} - -/* mmap page fault handler */ -static int b3dfg_vma_fault(struct vm_area_struct *vma, - struct vm_fault *vmf) -{ - struct b3dfg_dev *fgdev = vma->vm_file->private_data; - unsigned long off = vmf->pgoff << PAGE_SHIFT; - unsigned int frame_size = fgdev->frame_size; - unsigned int buf_size = frame_size * B3DFG_FRAMES_PER_BUFFER; - unsigned char *addr; - - /* determine which buffer the offset lies within */ - unsigned int buf_idx = off / buf_size; - /* and the offset into the buffer */ - unsigned int buf_off = off % buf_size; - - /* determine which frame inside the buffer the offset lies in */ - unsigned int frm_idx = buf_off / frame_size; - /* and the offset into the frame */ - unsigned int frm_off = buf_off % frame_size; - - if (unlikely(buf_idx >= b3dfg_nbuf)) - return VM_FAULT_SIGBUS; - - addr = fgdev->buffers[buf_idx].frame[frm_idx] + frm_off; - vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, - virt_to_phys(addr) >> PAGE_SHIFT); - - return VM_FAULT_NOPAGE; -} - -static struct vm_operations_struct b3dfg_vm_ops = { - .fault = b3dfg_vma_fault, -}; - -static int get_wand_status(struct b3dfg_dev *fgdev, int __user *arg) -{ - u32 wndstat = b3dfg_read32(fgdev, B3D_REG_WAND_STS); - dev_dbg(&fgdev->pdev->dev, "wand status %x\n", wndstat); - return __put_user(wndstat & 0x1, arg); -} - -static int enable_transmission(struct b3dfg_dev *fgdev) -{ - unsigned long flags; - struct device *dev = &fgdev->pdev->dev; - - dev_dbg(dev, "enable transmission\n"); - - /* check the cable is plugged in. */ - if (!b3dfg_read32(fgdev, B3D_REG_WAND_STS)) { - dev_dbg(dev, "cannot start transmission without wand\n"); - return -EINVAL; - } - - spin_lock_irqsave(&fgdev->buffer_lock, flags); - - /* Handle racing enable_transmission calls. */ - if (fgdev->transmission_enabled) { - spin_unlock_irqrestore(&fgdev->buffer_lock, flags); - goto out; - } - - spin_lock(&fgdev->triplets_dropped_lock); - fgdev->triplets_dropped = 0; - spin_unlock(&fgdev->triplets_dropped_lock); - - fgdev->triplet_ready = 0; - fgdev->cur_dma_frame_idx = -1; - fgdev->transmission_enabled = 1; - - spin_unlock_irqrestore(&fgdev->buffer_lock, flags); - - /* Enable DMA and cable status interrupts. */ - b3dfg_write32(fgdev, B3D_REG_HW_CTRL, 0x03); - -out: - return 0; -} - -static void disable_transmission(struct b3dfg_dev *fgdev) -{ - struct device *dev = &fgdev->pdev->dev; - unsigned long flags; - u32 tmp; - - dev_dbg(dev, "disable transmission\n"); - - /* guarantee that no more interrupts will be serviced */ - spin_lock_irqsave(&fgdev->buffer_lock, flags); - fgdev->transmission_enabled = 0; - - b3dfg_write32(fgdev, B3D_REG_HW_CTRL, 0); - - /* FIXME: temporary debugging only. if the board stops transmitting, - * hitting ctrl+c and seeing this message is useful for determining - * the state of the board. */ - tmp = b3dfg_read32(fgdev, B3D_REG_DMA_STS); - dev_dbg(dev, "DMA_STS reads %x after TX stopped\n", tmp); - - dequeue_all_buffers(fgdev); - spin_unlock_irqrestore(&fgdev->buffer_lock, flags); - - wake_up_interruptible(&fgdev->buffer_waitqueue); -} - -static int set_transmission(struct b3dfg_dev *fgdev, int enabled) -{ - int res = 0; - - if (enabled && !fgdev->transmission_enabled) - res = enable_transmission(fgdev); - else if (!enabled && fgdev->transmission_enabled) - disable_transmission(fgdev); - - return res; -} - -/* Called in interrupt context. */ -static void handle_cstate_unplug(struct b3dfg_dev *fgdev) -{ - /* Disable all interrupts. */ - b3dfg_write32(fgdev, B3D_REG_HW_CTRL, 0); - - /* Stop transmission. */ - spin_lock(&fgdev->buffer_lock); - fgdev->transmission_enabled = 0; - - fgdev->cur_dma_frame_idx = -1; - fgdev->triplet_ready = 0; - if (fgdev->cur_dma_frame_addr) { - pci_unmap_single(fgdev->pdev, fgdev->cur_dma_frame_addr, - fgdev->frame_size, PCI_DMA_FROMDEVICE); - fgdev->cur_dma_frame_addr = 0; - } - dequeue_all_buffers(fgdev); - spin_unlock(&fgdev->buffer_lock); -} - -/* Called in interrupt context. */ -static void handle_cstate_change(struct b3dfg_dev *fgdev) -{ - u32 cstate = b3dfg_read32(fgdev, B3D_REG_WAND_STS); - unsigned long when; - struct device *dev = &fgdev->pdev->dev; - - dev_dbg(dev, "cable state change: %u\n", cstate); - - /* - * When the wand is unplugged we reset our state. The hardware will - * have done the same internally. - * - * Note we should never see a cable *plugged* event, as interrupts - * should only be enabled when transmitting, which requires the cable - * to be plugged. If we do see one it probably means the cable has been - * unplugged and re-plugged very rapidly. Possibly because it has a - * broken wire and is momentarily losing contact. - * - * TODO: At the moment if you plug in the cable then enable transmission - * the hardware will raise a couple of spurious interrupts, so - * just ignore them for now. - * - * Once the hardware is fixed we should complain and treat it as an - * unplug. Or at least track how frequently it is happening and do - * so if too many come in. - */ - if (cstate) { - dev_warn(dev, "ignoring unexpected plug event\n"); - return; - } - handle_cstate_unplug(fgdev); - - /* - * Record cable state change timestamp & wake anyone waiting - * on a cable state change. Be paranoid about ensuring events - * are not missed if we somehow get two interrupts in a jiffy. - */ - spin_lock(&fgdev->cstate_lock); - when = jiffies_64; - if (when <= fgdev->cstate_tstamp) - when = fgdev->cstate_tstamp + 1; - fgdev->cstate_tstamp = when; - wake_up_interruptible(&fgdev->buffer_waitqueue); - spin_unlock(&fgdev->cstate_lock); -} - -/* Called with buffer_lock held. */ -static void transfer_complete(struct b3dfg_dev *fgdev) -{ - struct b3dfg_buffer *buf; - struct device *dev = &fgdev->pdev->dev; - - pci_unmap_single(fgdev->pdev, fgdev->cur_dma_frame_addr, - fgdev->frame_size, PCI_DMA_FROMDEVICE); - fgdev->cur_dma_frame_addr = 0; - - buf = list_entry(fgdev->buffer_queue.next, struct b3dfg_buffer, list); - - dev_dbg(dev, "handle frame completion\n"); - if (fgdev->cur_dma_frame_idx == B3DFG_FRAMES_PER_BUFFER - 1) { - - /* last frame of that triplet completed */ - dev_dbg(dev, "triplet completed\n"); - buf->state = B3DFG_BUFFER_POPULATED; - list_del_init(&buf->list); - wake_up_interruptible(&fgdev->buffer_waitqueue); - } -} - -/* - * Called with buffer_lock held. - * - * Note that idx is the (1-based) *next* frame to be transferred, while - * cur_dma_frame_idx is the (0-based) *last* frame to have been transferred (or - * -1 if none). Thus there should be a difference of 2 between them. - */ -static bool setup_next_frame_transfer(struct b3dfg_dev *fgdev, int idx) -{ - struct b3dfg_buffer *buf; - struct device *dev = &fgdev->pdev->dev; - bool need_ack = 1; - - dev_dbg(dev, "program DMA transfer for next frame: %d\n", idx); - - buf = list_entry(fgdev->buffer_queue.next, struct b3dfg_buffer, list); - if (idx == fgdev->cur_dma_frame_idx + 2) { - if (setup_frame_transfer(fgdev, buf, idx - 1)) - dev_err(dev, "unable to map DMA buffer\n"); - need_ack = 0; - } else { - dev_err(dev, "frame mismatch, got %d, expected %d\n", - idx, fgdev->cur_dma_frame_idx + 2); - - /* FIXME: handle dropped triplets here */ - } - - return need_ack; -} - -static irqreturn_t b3dfg_intr(int irq, void *dev_id) -{ - struct b3dfg_dev *fgdev = dev_id; - struct device *dev = &fgdev->pdev->dev; - u32 sts; - u8 dropped; - bool need_ack = 1; - irqreturn_t res = IRQ_HANDLED; - - sts = b3dfg_read32(fgdev, B3D_REG_DMA_STS); - if (unlikely(sts == 0)) { - dev_warn(dev, "ignore interrupt, DMA status is 0\n"); - res = IRQ_NONE; - goto out; - } - - if (unlikely(!fgdev->transmission_enabled)) { - dev_warn(dev, "ignore interrupt, TX disabled\n"); - res = IRQ_HANDLED; - goto out; - } - - /* Handle dropped frames, as reported by the hardware. */ - dropped = (sts >> 8) & 0xff; - dev_dbg(dev, "intr: DMA_STS=%08x (drop=%d comp=%d next=%d)\n", - sts, dropped, !!(sts & 0x4), sts & 0x3); - if (unlikely(dropped > 0)) { - spin_lock(&fgdev->triplets_dropped_lock); - fgdev->triplets_dropped += dropped; - spin_unlock(&fgdev->triplets_dropped_lock); - } - - /* Handle a cable state change (i.e. the wand being unplugged). */ - if (sts & 0x08) { - handle_cstate_change(fgdev); - goto out; - } - - spin_lock(&fgdev->buffer_lock); - if (unlikely(list_empty(&fgdev->buffer_queue))) { - - /* FIXME need more sanity checking here */ - dev_info(dev, "buffer not ready for next transfer\n"); - fgdev->triplet_ready = 1; - goto out_unlock; - } - - /* Has a frame transfer been completed? */ - if (sts & 0x4) { - u32 dma_status = b3dfg_read32(fgdev, B3D_REG_EC220_DMA_STS); - - /* Check for DMA errors reported by the hardware. */ - if (unlikely(dma_status & 0x1)) { - dev_err(dev, "EC220 error: %08x\n", dma_status); - - /* FIXME flesh out error handling */ - goto out_unlock; - } - - /* Sanity check, we should have a frame index at this point. */ - if (unlikely(fgdev->cur_dma_frame_idx == -1)) { - dev_err(dev, "completed but no last idx?\n"); - - /* FIXME flesh out error handling */ - goto out_unlock; - } - - transfer_complete(fgdev); - } - - /* Is there another frame transfer pending? */ - if (sts & 0x3) - need_ack = setup_next_frame_transfer(fgdev, sts & 0x3); - else - fgdev->cur_dma_frame_idx = -1; - -out_unlock: - spin_unlock(&fgdev->buffer_lock); -out: - if (need_ack) { - dev_dbg(dev, "acknowledging interrupt\n"); - b3dfg_write32(fgdev, B3D_REG_EC220_DMA_STS, 0x0b); - } - return res; -} - -static int b3dfg_open(struct inode *inode, struct file *filp) -{ - struct b3dfg_dev *fgdev = - container_of(inode->i_cdev, struct b3dfg_dev, chardev); - - dev_dbg(&fgdev->pdev->dev, "open\n"); - filp->private_data = fgdev; - return 0; -} - -static int b3dfg_release(struct inode *inode, struct file *filp) -{ - struct b3dfg_dev *fgdev = filp->private_data; - dev_dbg(&fgdev->pdev->dev, "release\n"); - disable_transmission(fgdev); - return 0; -} - -static long b3dfg_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) -{ - struct b3dfg_dev *fgdev = filp->private_data; - - switch (cmd) { - case B3DFG_IOCGFRMSZ: - return __put_user(fgdev->frame_size, (int __user *) arg); - case B3DFG_IOCGWANDSTAT: - return get_wand_status(fgdev, (int __user *) arg); - case B3DFG_IOCTTRANS: - return set_transmission(fgdev, (int) arg); - case B3DFG_IOCTQUEUEBUF: - return queue_buffer(fgdev, (int) arg); - case B3DFG_IOCTPOLLBUF: - return poll_buffer(fgdev, (void __user *) arg); - case B3DFG_IOCTWAITBUF: - return wait_buffer(fgdev, (void __user *) arg); - default: - dev_dbg(&fgdev->pdev->dev, "unrecognised ioctl %x\n", cmd); - return -EINVAL; - } -} - -static unsigned int b3dfg_poll(struct file *filp, poll_table *poll_table) -{ - struct b3dfg_dev *fgdev = filp->private_data; - unsigned long flags, when; - int i; - int r = 0; - - when = get_cstate_change(fgdev); - poll_wait(filp, &fgdev->buffer_waitqueue, poll_table); - - spin_lock_irqsave(&fgdev->buffer_lock, flags); - for (i = 0; i < b3dfg_nbuf; i++) { - if (fgdev->buffers[i].state == B3DFG_BUFFER_POPULATED) { - r = POLLIN | POLLRDNORM; - break; - } - } - spin_unlock_irqrestore(&fgdev->buffer_lock, flags); - - /* TODO: Confirm this is how we want to communicate the change. */ - if (!fgdev->transmission_enabled || when != get_cstate_change(fgdev)) - r = POLLERR; - - return r; -} - -static int b3dfg_mmap(struct file *filp, struct vm_area_struct *vma) -{ - struct b3dfg_dev *fgdev = filp->private_data; - unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; - unsigned long vsize = vma->vm_end - vma->vm_start; - unsigned long bufdatalen = b3dfg_nbuf * fgdev->frame_size * 3; - unsigned long psize = bufdatalen - offset; - int r = 0; - - if (vsize <= psize) { - vma->vm_flags |= VM_IO | VM_RESERVED | VM_CAN_NONLINEAR | - VM_PFNMAP; - vma->vm_ops = &b3dfg_vm_ops; - } else { - r = -EINVAL; - } - - return r; -} - -static struct file_operations b3dfg_fops = { - .owner = THIS_MODULE, - .open = b3dfg_open, - .release = b3dfg_release, - .unlocked_ioctl = b3dfg_ioctl, - .poll = b3dfg_poll, - .mmap = b3dfg_mmap, -}; - -static void free_all_frame_buffers(struct b3dfg_dev *fgdev) -{ - int i, j; - for (i = 0; i < b3dfg_nbuf; i++) - for (j = 0; j < B3DFG_FRAMES_PER_BUFFER; j++) - kfree(fgdev->buffers[i].frame[j]); - kfree(fgdev->buffers); -} - -/* initialize device and any data structures. called before any interrupts - * are enabled. */ -static int b3dfg_init_dev(struct b3dfg_dev *fgdev) -{ - int i, j; - u32 frm_size = b3dfg_read32(fgdev, B3D_REG_FRM_SIZE); - - /* Disable interrupts. In abnormal circumstances (e.g. after a crash) - * the board may still be transmitting from the previous session. If we - * ensure that interrupts are disabled before we later enable them, we - * are sure to capture a triplet from the start, rather than starting - * from frame 2 or 3. Disabling interrupts causes the FG to throw away - * all buffered data and stop buffering more until interrupts are - * enabled again. - */ - b3dfg_write32(fgdev, B3D_REG_HW_CTRL, 0); - - fgdev->frame_size = frm_size * 4096; - fgdev->buffers = kzalloc(sizeof(struct b3dfg_buffer) * b3dfg_nbuf, - GFP_KERNEL); - if (!fgdev->buffers) - goto err_no_buf; - for (i = 0; i < b3dfg_nbuf; i++) { - struct b3dfg_buffer *buf = &fgdev->buffers[i]; - for (j = 0; j < B3DFG_FRAMES_PER_BUFFER; j++) { - buf->frame[j] = kmalloc(fgdev->frame_size, GFP_KERNEL); - if (!buf->frame[j]) - goto err_no_mem; - } - INIT_LIST_HEAD(&buf->list); - } - - INIT_LIST_HEAD(&fgdev->buffer_queue); - init_waitqueue_head(&fgdev->buffer_waitqueue); - spin_lock_init(&fgdev->buffer_lock); - spin_lock_init(&fgdev->cstate_lock); - spin_lock_init(&fgdev->triplets_dropped_lock); - return 0; - -err_no_mem: - free_all_frame_buffers(fgdev); -err_no_buf: - return -ENOMEM; -} - -/* find next free minor number, returns -1 if none are availabile */ -static int get_free_minor(void) -{ - int i; - for (i = 0; i < B3DFG_MAX_DEVS; i++) { - if (b3dfg_devices[i] == 0) - return i; - } - return -1; -} - -static int __devinit b3dfg_probe(struct pci_dev *pdev, - const struct pci_device_id *id) -{ - struct b3dfg_dev *fgdev = kzalloc(sizeof(*fgdev), GFP_KERNEL); - int r = 0; - int minor = get_free_minor(); - dev_t devno = MKDEV(MAJOR(b3dfg_devt), minor); - unsigned long res_len; - resource_size_t res_base; - - if (fgdev == NULL) - return -ENOMEM; - - if (minor < 0) { - dev_err(&pdev->dev, "too many devices found!\n"); - r = -EIO; - goto err_free; - } - - b3dfg_devices[minor] = 1; - dev_info(&pdev->dev, "probe device with IRQ %d\n", pdev->irq); - - cdev_init(&fgdev->chardev, &b3dfg_fops); - fgdev->chardev.owner = THIS_MODULE; - - r = cdev_add(&fgdev->chardev, devno, 1); - if (r) { - dev_err(&pdev->dev, "cannot add char device\n"); - goto err_release_minor; - } - - fgdev->dev = device_create( - b3dfg_class, - &pdev->dev, - devno, - dev_get_drvdata(&pdev->dev), - DRIVER_NAME "%d", minor); - - if (IS_ERR(fgdev->dev)) { - dev_err(&pdev->dev, "cannot create device\n"); - r = PTR_ERR(fgdev->dev); - goto err_del_cdev; - } - - r = pci_enable_device(pdev); - if (r) { - dev_err(&pdev->dev, "cannot enable PCI device\n"); - goto err_dev_unreg; - } - - res_len = pci_resource_len(pdev, B3DFG_BAR_REGS); - if (res_len != B3DFG_REGS_LENGTH) { - dev_err(&pdev->dev, "invalid register resource size\n"); - r = -EIO; - goto err_disable; - } - - if (pci_resource_flags(pdev, B3DFG_BAR_REGS) - != (IORESOURCE_MEM | IORESOURCE_SIZEALIGN)) { - dev_err(&pdev->dev, "invalid resource flags\n"); - r = -EIO; - goto err_disable; - } - r = pci_request_regions(pdev, DRIVER_NAME); - if (r) { - dev_err(&pdev->dev, "cannot obtain PCI resources\n"); - goto err_disable; - } - - pci_set_master(pdev); - - r = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); - if (r) { - dev_err(&pdev->dev, "no usable DMA configuration\n"); - goto err_free_res; - } - - res_base = pci_resource_start(pdev, B3DFG_BAR_REGS); - fgdev->regs = ioremap_nocache(res_base, res_len); - if (!fgdev->regs) { - dev_err(&pdev->dev, "regs ioremap failed\n"); - r = -EIO; - goto err_free_res; - } - - fgdev->pdev = pdev; - pci_set_drvdata(pdev, fgdev); - r = b3dfg_init_dev(fgdev); - if (r < 0) { - dev_err(&pdev->dev, "failed to initalize device\n"); - goto err_unmap; - } - - r = request_irq(pdev->irq, b3dfg_intr, IRQF_SHARED, DRIVER_NAME, fgdev); - if (r) { - dev_err(&pdev->dev, "couldn't request irq %d\n", pdev->irq); - goto err_free_bufs; - } - - return 0; - -err_free_bufs: - free_all_frame_buffers(fgdev); -err_unmap: - iounmap(fgdev->regs); -err_free_res: - pci_release_regions(pdev); -err_disable: - pci_disable_device(pdev); -err_dev_unreg: - device_destroy(b3dfg_class, devno); -err_del_cdev: - cdev_del(&fgdev->chardev); -err_release_minor: - b3dfg_devices[minor] = 0; -err_free: - kfree(fgdev); - return r; -} - -static void __devexit b3dfg_remove(struct pci_dev *pdev) -{ - struct b3dfg_dev *fgdev = pci_get_drvdata(pdev); - unsigned int minor = MINOR(fgdev->chardev.dev); - - dev_dbg(&pdev->dev, "remove\n"); - - free_irq(pdev->irq, fgdev); - iounmap(fgdev->regs); - pci_release_regions(pdev); - pci_disable_device(pdev); - device_destroy(b3dfg_class, MKDEV(MAJOR(b3dfg_devt), minor)); - cdev_del(&fgdev->chardev); - free_all_frame_buffers(fgdev); - kfree(fgdev); - b3dfg_devices[minor] = 0; -} - -static struct pci_driver b3dfg_driver = { - .name = DRIVER_NAME, - .id_table = b3dfg_ids, - .probe = b3dfg_probe, - .remove = __devexit_p(b3dfg_remove), -}; - -static int __init b3dfg_module_init(void) -{ - int r; - - if (b3dfg_nbuf < 2) { - printk(KERN_ERR DRIVER_NAME - ": buffer_count is out of range (must be >= 2)"); - return -EINVAL; - } - - printk(KERN_INFO DRIVER_NAME ": loaded\n"); - - b3dfg_class = class_create(THIS_MODULE, DRIVER_NAME); - if (IS_ERR(b3dfg_class)) - return PTR_ERR(b3dfg_class); - - r = alloc_chrdev_region(&b3dfg_devt, 0, B3DFG_MAX_DEVS, DRIVER_NAME); - if (r) - goto err1; - - r = pci_register_driver(&b3dfg_driver); - if (r) - goto err2; - - return r; - -err2: - unregister_chrdev_region(b3dfg_devt, B3DFG_MAX_DEVS); -err1: - class_destroy(b3dfg_class); - return r; -} - -static void __exit b3dfg_module_exit(void) -{ - printk(KERN_INFO DRIVER_NAME ": unloaded\n"); - pci_unregister_driver(&b3dfg_driver); - unregister_chrdev_region(b3dfg_devt, B3DFG_MAX_DEVS); - class_destroy(b3dfg_class); -} - -module_init(b3dfg_module_init); -module_exit(b3dfg_module_exit); -- cgit v1.2.3 From 2d629030ca649bd4a7356befedbe7bbefa840b21 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 22 Dec 2009 16:35:21 -0800 Subject: Staging: p9auth: remove driver from tree No one seems to be maintaining this anymore, and it is not on any track to be merged to mainline. Cc: Ashwin Ganti Signed-off-by: Greg Kroah-Hartman --- drivers/staging/Kconfig | 2 - drivers/staging/Makefile | 1 - drivers/staging/p9auth/Kconfig | 9 - drivers/staging/p9auth/Makefile | 1 - drivers/staging/p9auth/p9auth.c | 408 ---------------------------------------- 5 files changed, 421 deletions(-) delete mode 100644 drivers/staging/p9auth/Kconfig delete mode 100644 drivers/staging/p9auth/Makefile delete mode 100644 drivers/staging/p9auth/p9auth.c (limited to 'drivers') diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index a1dee5c59775..e43cab46e2cb 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -91,8 +91,6 @@ source "drivers/staging/pohmelfs/Kconfig" source "drivers/staging/phison/Kconfig" -source "drivers/staging/p9auth/Kconfig" - source "drivers/staging/line6/Kconfig" source "drivers/gpu/drm/vmwgfx/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index f7d34eec6740..c2f0ca9a7a15 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -28,7 +28,6 @@ obj-$(CONFIG_TRANZPORT) += frontier/ obj-$(CONFIG_DREAM) += dream/ obj-$(CONFIG_POHMELFS) += pohmelfs/ obj-$(CONFIG_IDE_PHISON) += phison/ -obj-$(CONFIG_PLAN9AUTH) += p9auth/ obj-$(CONFIG_LINE6_USB) += line6/ obj-$(CONFIG_USB_SERIAL_QUATECH2) += serqt_usb2/ obj-$(CONFIG_USB_SERIAL_QUATECH_USB2) += quatech_usb2/ diff --git a/drivers/staging/p9auth/Kconfig b/drivers/staging/p9auth/Kconfig deleted file mode 100644 index d1c66d262020..000000000000 --- a/drivers/staging/p9auth/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -config PLAN9AUTH - tristate "Plan 9 style capability device implementation" - default n - depends on CRYPTO - help - This module implements the Plan 9 style capability device. - - To compile this driver as a module, choose - M here: the module will be called p9auth. diff --git a/drivers/staging/p9auth/Makefile b/drivers/staging/p9auth/Makefile deleted file mode 100644 index 3ebf6ff0eef2..000000000000 --- a/drivers/staging/p9auth/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-$(CONFIG_PLAN9AUTH) += p9auth.o diff --git a/drivers/staging/p9auth/p9auth.c b/drivers/staging/p9auth/p9auth.c deleted file mode 100644 index db7962621210..000000000000 --- a/drivers/staging/p9auth/p9auth.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * Plan 9 style capability device implementation for the Linux Kernel - * - * Copyright 2008, 2009 Ashwin Ganti - * - * Released under the GPLv2 - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef CAP_MAJOR -#define CAP_MAJOR 0 -#endif - -#ifndef CAP_NR_DEVS -#define CAP_NR_DEVS 2 /* caphash and capuse */ -#endif - -#ifndef CAP_NODE_SIZE -#define CAP_NODE_SIZE 20 -#endif - -#define MAX_DIGEST_SIZE 20 - -struct cap_node { - char data[CAP_NODE_SIZE]; - struct list_head list; -}; - -struct cap_dev { - struct cap_node *head; - int node_size; - unsigned long size; - struct semaphore sem; - struct cdev cdev; -}; - -static int cap_major = CAP_MAJOR; -static int cap_minor; -static int cap_nr_devs = CAP_NR_DEVS; -static int cap_node_size = CAP_NODE_SIZE; - -module_param(cap_major, int, S_IRUGO); -module_param(cap_minor, int, S_IRUGO); -module_param(cap_nr_devs, int, S_IRUGO); - -MODULE_AUTHOR("Ashwin Ganti"); -MODULE_LICENSE("GPL"); - -static struct cap_dev *cap_devices; - -static void hexdump(unsigned char *buf, unsigned int len) -{ - while (len--) - printk("%02x", *buf++); - printk("\n"); -} - -static char *cap_hash(char *plain_text, unsigned int plain_text_size, - char *key, unsigned int key_size) -{ - struct scatterlist sg; - char *result; - struct crypto_hash *tfm; - struct hash_desc desc; - int ret; - - tfm = crypto_alloc_hash("hmac(sha1)", 0, CRYPTO_ALG_ASYNC); - if (IS_ERR(tfm)) { - printk(KERN_ERR - "failed to load transform for hmac(sha1): %ld\n", - PTR_ERR(tfm)); - return NULL; - } - - desc.tfm = tfm; - desc.flags = 0; - - result = kzalloc(MAX_DIGEST_SIZE, GFP_KERNEL); - if (!result) { - printk(KERN_ERR "out of memory!\n"); - goto out; - } - - sg_set_buf(&sg, plain_text, plain_text_size); - - ret = crypto_hash_setkey(tfm, key, key_size); - if (ret) { - printk(KERN_ERR "setkey() failed ret=%d\n", ret); - kfree(result); - result = NULL; - goto out; - } - - ret = crypto_hash_digest(&desc, &sg, plain_text_size, result); - if (ret) { - printk(KERN_ERR "digest () failed ret=%d\n", ret); - kfree(result); - result = NULL; - goto out; - } - - printk(KERN_DEBUG "crypto hash digest size %d\n", - crypto_hash_digestsize(tfm)); - hexdump(result, MAX_DIGEST_SIZE); - -out: - crypto_free_hash(tfm); - return result; -} - -static int cap_trim(struct cap_dev *dev) -{ - struct cap_node *tmp; - struct list_head *pos, *q; - if (dev->head != NULL) { - list_for_each_safe(pos, q, &(dev->head->list)) { - tmp = list_entry(pos, struct cap_node, list); - list_del(pos); - kfree(tmp); - } - } - return 0; -} - -static int cap_open(struct inode *inode, struct file *filp) -{ - struct cap_dev *dev; - dev = container_of(inode->i_cdev, struct cap_dev, cdev); - filp->private_data = dev; - - /* trim to 0 the length of the device if open was write-only */ - if ((filp->f_flags & O_ACCMODE) == O_WRONLY) { - if (down_interruptible(&dev->sem)) - return -ERESTARTSYS; - cap_trim(dev); - up(&dev->sem); - } - /* initialise the head if it is NULL */ - if (dev->head == NULL) { - dev->head = kmalloc(sizeof(struct cap_node), GFP_KERNEL); - INIT_LIST_HEAD(&(dev->head->list)); - } - return 0; -} - -static int cap_release(struct inode *inode, struct file *filp) -{ - return 0; -} - -static ssize_t cap_write(struct file *filp, const char __user *buf, - size_t count, loff_t *f_pos) -{ - struct cap_node *node_ptr, *tmp; - struct list_head *pos; - struct cap_dev *dev = filp->private_data; - ssize_t retval = -ENOMEM; - struct cred *new; - int len, target_int, source_int, flag = 0; - char *user_buf, *user_buf_running, *source_user, *target_user, - *rand_str, *hash_str, *result; - - if (down_interruptible(&dev->sem)) - return -ERESTARTSYS; - - user_buf_running = NULL; - hash_str = NULL; - node_ptr = kmalloc(sizeof(struct cap_node), GFP_KERNEL); - user_buf = kzalloc(count+1, GFP_KERNEL); - if (!node_ptr || !user_buf) - goto out; - - if (copy_from_user(user_buf, buf, count)) { - retval = -EFAULT; - goto out; - } - - /* - * If the minor number is 0 ( /dev/caphash ) then simply add the - * hashed capability supplied by the user to the list of hashes - */ - if (0 == iminor(filp->f_dentry->d_inode)) { - if (count > CAP_NODE_SIZE) { - retval = -EINVAL; - goto out; - } - printk(KERN_INFO "Capability being written to /dev/caphash : \n"); - hexdump(user_buf, count); - memcpy(node_ptr->data, user_buf, count); - list_add(&(node_ptr->list), &(dev->head->list)); - node_ptr = NULL; - } else { - char *tmpu; - if (!cap_devices[0].head || - list_empty(&(cap_devices[0].head->list))) { - retval = -EINVAL; - goto out; - } - /* - * break the supplied string into tokens with @ as the - * delimiter If the string is "user1@user2@randomstring" we - * need to split it and hash 'user1@user2' using 'randomstring' - * as the key. - */ - tmpu = user_buf_running = kstrdup(user_buf, GFP_KERNEL); - source_user = strsep(&tmpu, "@"); - target_user = strsep(&tmpu, "@"); - rand_str = tmpu; - if (!source_user || !target_user || !rand_str) { - retval = -EINVAL; - goto out; - } - - /* hash the string user1@user2 with rand_str as the key */ - len = strlen(source_user) + strlen(target_user) + 1; - /* src, @, len, \0 */ - hash_str = kzalloc(len+1, GFP_KERNEL); - strcat(hash_str, source_user); - strcat(hash_str, "@"); - strcat(hash_str, target_user); - - printk(KERN_ALERT "the source user is %s \n", source_user); - printk(KERN_ALERT "the target user is %s \n", target_user); - - result = cap_hash(hash_str, len, rand_str, strlen(rand_str)); - if (NULL == result) { - retval = -EFAULT; - goto out; - } - memcpy(node_ptr->data, result, CAP_NODE_SIZE); /* why? */ - /* Change the process's uid if the hash is present in the - * list of hashes - */ - list_for_each(pos, &(cap_devices->head->list)) { - /* - * Change the user id of the process if the hashes - * match - */ - if (0 == - memcmp(result, - list_entry(pos, struct cap_node, - list)->data, - CAP_NODE_SIZE)) { - target_int = (unsigned int) - simple_strtol(target_user, NULL, 0); - source_int = (unsigned int) - simple_strtol(source_user, NULL, 0); - flag = 1; - - /* - * Check whether the process writing to capuse - * is actually owned by the source owner - */ - if (source_int != current_uid()) { - printk(KERN_ALERT - "Process is not owned by the source user of the capability.\n"); - retval = -EFAULT; - goto out; - } - /* - * What all id's need to be changed here? uid, - * euid, fsid, savedids ?? Currently I am - * changing the effective user id since most of - * the authorisation decisions are based on it - */ - new = prepare_creds(); - if (!new) { - retval = -ENOMEM; - goto out; - } - new->uid = (uid_t) target_int; - new->euid = (uid_t) target_int; - retval = commit_creds(new); - if (retval) - goto out; - - /* - * Remove the capability from the list and - * break - */ - tmp = list_entry(pos, struct cap_node, list); - list_del(pos); - kfree(tmp); - break; - } - } - if (0 == flag) { - /* - * The capability is not present in the list of the - * hashes stored, hence return failure - */ - printk(KERN_ALERT - "Invalid capabiliy written to /dev/capuse \n"); - retval = -EFAULT; - goto out; - } - } - *f_pos += count; - retval = count; - /* update the size */ - if (dev->size < *f_pos) - dev->size = *f_pos; - -out: - kfree(node_ptr); - kfree(user_buf); - kfree(user_buf_running); - kfree(hash_str); - up(&dev->sem); - return retval; -} - -static const struct file_operations cap_fops = { - .owner = THIS_MODULE, - .write = cap_write, - .open = cap_open, - .release = cap_release, -}; - -/* no __exit here because it can be called by the init function */ -static void cap_cleanup_module(void) -{ - int i; - dev_t devno = MKDEV(cap_major, cap_minor); - if (cap_devices) { - for (i = 0; i < cap_nr_devs; i++) { - cap_trim(cap_devices + i); - cdev_del(&cap_devices[i].cdev); - } - kfree(cap_devices); - } - unregister_chrdev_region(devno, cap_nr_devs); - -} - -static void cap_setup_cdev(struct cap_dev *dev, int index) -{ - int err, devno = MKDEV(cap_major, cap_minor + index); - cdev_init(&dev->cdev, &cap_fops); - dev->cdev.owner = THIS_MODULE; - dev->cdev.ops = &cap_fops; - err = cdev_add(&dev->cdev, devno, 1); - if (err) - printk(KERN_NOTICE "Error %d adding cap%d", err, index); -} - -static int __init cap_init_module(void) -{ - int result, i; - dev_t dev = 0; - - if (cap_major) { - dev = MKDEV(cap_major, cap_minor); - result = register_chrdev_region(dev, cap_nr_devs, "cap"); - } else { - result = alloc_chrdev_region(&dev, cap_minor, cap_nr_devs, - "cap"); - cap_major = MAJOR(dev); - } - - if (result < 0) { - printk(KERN_WARNING "cap: can't get major %d\n", - cap_major); - return result; - } - - cap_devices = kzalloc(cap_nr_devs * sizeof(struct cap_dev), - GFP_KERNEL); - if (!cap_devices) { - result = -ENOMEM; - goto fail; - } - - /* Initialize each device. */ - for (i = 0; i < cap_nr_devs; i++) { - cap_devices[i].node_size = cap_node_size; - init_MUTEX(&cap_devices[i].sem); - cap_setup_cdev(&cap_devices[i], i); - } - - return 0; - -fail: - cap_cleanup_module(); - return result; -} - -module_init(cap_init_module); -module_exit(cap_cleanup_module); - - -- cgit v1.2.3 From ca1f29c01aaa37d522dc6ce311769731f5f1919e Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 22 Dec 2009 16:38:10 -0800 Subject: Staging: altpciechdma: remove driver No one seems to be able to maintain this, or merge it into mainline, so remove it. Acked-by: Leon Woestenberg Signed-off-by: Greg Kroah-Hartman --- drivers/staging/Kconfig | 2 - drivers/staging/Makefile | 1 - drivers/staging/altpciechdma/Kconfig | 10 - drivers/staging/altpciechdma/Makefile | 2 - drivers/staging/altpciechdma/TODO | 15 - drivers/staging/altpciechdma/altpciechdma.c | 1182 --------------------------- 6 files changed, 1212 deletions(-) delete mode 100644 drivers/staging/altpciechdma/Kconfig delete mode 100644 drivers/staging/altpciechdma/Makefile delete mode 100644 drivers/staging/altpciechdma/TODO delete mode 100644 drivers/staging/altpciechdma/altpciechdma.c (limited to 'drivers') diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index e43cab46e2cb..9543174360bf 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -71,8 +71,6 @@ source "drivers/staging/asus_oled/Kconfig" source "drivers/staging/panel/Kconfig" -source "drivers/staging/altpciechdma/Kconfig" - source "drivers/staging/rtl8187se/Kconfig" source "drivers/staging/rtl8192su/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index c2f0ca9a7a15..394327a1f789 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -18,7 +18,6 @@ obj-$(CONFIG_RT2870) += rt2870/ obj-$(CONFIG_COMEDI) += comedi/ obj-$(CONFIG_ASUS_OLED) += asus_oled/ obj-$(CONFIG_PANEL) += panel/ -obj-$(CONFIG_ALTERA_PCIE_CHDMA) += altpciechdma/ obj-$(CONFIG_R8187SE) += rtl8187se/ obj-$(CONFIG_RTL8192SU) += rtl8192su/ obj-$(CONFIG_RTL8192U) += rtl8192u/ diff --git a/drivers/staging/altpciechdma/Kconfig b/drivers/staging/altpciechdma/Kconfig deleted file mode 100644 index 0f4bf92cbbfb..000000000000 --- a/drivers/staging/altpciechdma/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -config ALTERA_PCIE_CHDMA - tristate "Altera PCI Express Chaining DMA driver" - depends on PCI - default N - ---help--- - A reference driver that exercises the Chaining DMA logic reference - design generated along the Altera FPGA PCI Express soft or hard core, - only if instantiated using the MegaWizard, not the SOPC builder, of - Quartus 8.1. - diff --git a/drivers/staging/altpciechdma/Makefile b/drivers/staging/altpciechdma/Makefile deleted file mode 100644 index c08c8437f4db..000000000000 --- a/drivers/staging/altpciechdma/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-$(CONFIG_ALTERA_PCIE_CHDMA) += altpciechdma.o - diff --git a/drivers/staging/altpciechdma/TODO b/drivers/staging/altpciechdma/TODO deleted file mode 100644 index 12c945fd61e1..000000000000 --- a/drivers/staging/altpciechdma/TODO +++ /dev/null @@ -1,15 +0,0 @@ -DONE: - - functionality similar to logic testbench - -TODO: - - checkpatch.pl cleanups. - - keep state of DMA engines. - - keep data structure that keeps state of each transfer. - - interrupt handler should iterate over outstanding descriptor tables. - - complete userspace cdev to read/write using the DMA engines. - - split off the DMA support functions in a module, re-usable by custom - drivers. - -Please coordinate work with, and send patches to -Leon Woestenberg - diff --git a/drivers/staging/altpciechdma/altpciechdma.c b/drivers/staging/altpciechdma/altpciechdma.c deleted file mode 100644 index 2a02f8e625f7..000000000000 --- a/drivers/staging/altpciechdma/altpciechdma.c +++ /dev/null @@ -1,1182 +0,0 @@ -/** - * Driver for Altera PCIe core chaining DMA reference design. - * - * Copyright (C) 2008 Leon Woestenberg - * Copyright (C) 2008 Nickolas Heppermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * - * Rationale: This driver exercises the chaining DMA read and write engine - * in the reference design. It is meant as a complementary reference - * driver that can be used for testing early designs as well as a basis to - * write your custom driver. - * - * Status: Test results from Leon Woestenberg : - * - * Sendero Board w/ Cyclone II EP2C35F672C6N, PX1011A PCIe x1 PHY on a - * Dell Precision 370 PC, x86, kernel 2.6.20 from Ubuntu 7.04. - * - * Sendero Board w/ Cyclone II EP2C35F672C6N, PX1011A PCIe x1 PHY on a - * Freescale MPC8313E-RDB board, PowerPC, 2.6.24 w/ Freescale patches. - * - * Driver tests passed with PCIe Compiler 8.1. With PCIe 8.0 the DMA - * loopback test had reproducable compare errors. I assume a change - * in the compiler or reference design, but could not find evidence nor - * documentation on a change or fix in that direction. - * - * The reference design does not have readable locations and thus a - * dummy read, used to flush PCI posted writes, cannot be performed. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -/* by default do not build the character device interface */ -/* XXX It is non-functional yet */ -#ifndef ALTPCIECHDMA_CDEV -# define ALTPCIECHDMA_CDEV 0 -#endif - -/* build the character device interface? */ -#if ALTPCIECHDMA_CDEV -# define MAX_CHDMA_SIZE (8 * 1024 * 1024) -# include "mapper_user_to_sg.h" -#endif - -/** driver name, mimicks Altera naming of the reference design */ -#define DRV_NAME "altpciechdma" -/** number of BARs on the device */ -#define APE_BAR_NUM (6) -/** BAR number where the RCSLAVE memory sits */ -#define APE_BAR_RCSLAVE (0) -/** BAR number where the Descriptor Header sits */ -#define APE_BAR_HEADER (2) - -/** maximum size in bytes of the descriptor table, chdma logic limit */ -#define APE_CHDMA_TABLE_SIZE (4096) -/* single transfer must not exceed 255 table entries. worst case this can be - * achieved by 255 scattered pages, with only a single byte in the head and - * tail pages. 253 * PAGE_SIZE is a safe upper bound for the transfer size. - */ -#define APE_CHDMA_MAX_TRANSFER_LEN (253 * PAGE_SIZE) - -/** - * Specifies those BARs to be mapped and the length of each mapping. - * - * Zero (0) means do not map, otherwise specifies the BAR lengths to be mapped. - * If the actual BAR length is less, this is considered an error; then - * reconfigure your PCIe core. - * - * @see ug_pci_express 8.0, table 7-2 at page 7-13. - */ -static const unsigned long bar_min_len[APE_BAR_NUM] = - { 32768, 0, 256, 0, 32768, 0 }; - -/** - * Descriptor Header, controls the DMA read engine or write engine. - * - * The descriptor header is the main data structure for starting DMA transfers. - * - * It sits in End Point (FPGA) memory BAR[2] for 32-bit or BAR[3:2] for 64-bit. - * It references a descriptor table which exists in Root Complex (PC) memory. - * Writing the rclast field starts the DMA operation, thus all other structures - * and fields must be setup before doing so. - * - * @see ug_pci_express 8.0, tables 7-3, 7-4 and 7-5 at page 7-14. - * @note This header must be written in four 32-bit (PCI DWORD) writes. - */ -struct ape_chdma_header { - /** - * w0 consists of two 16-bit fields: - * lsb u16 number; number of descriptors in ape_chdma_table - * msb u16 control; global control flags - */ - u32 w0; - /* bus address to ape_chdma_table in Root Complex memory */ - u32 bdt_addr_h; - u32 bdt_addr_l; - /** - * w3 consists of two 16-bit fields: - * - lsb u16 rclast; last descriptor number available in Root Complex - * - zero (0) means the first descriptor is ready, - * - one (1) means two descriptors are ready, etc. - * - msb u16 reserved; - * - * @note writing to this memory location starts the DMA operation! - */ - u32 w3; -} __attribute__ ((packed)); - -/** - * Descriptor Entry, describing a (non-scattered) single memory block transfer. - * - * There is one descriptor for each memory block involved in the transfer, a - * block being a contiguous address range on the bus. - * - * Multiple descriptors are chained by means of the ape_chdma_table data - * structure. - * - * @see ug_pci_express 8.0, tables 7-6, 7-7 and 7-8 at page 7-14 and page 7-15. - */ -struct ape_chdma_desc { - /** - * w0 consists of two 16-bit fields: - * number of DWORDS to transfer - * - lsb u16 length; - * global control - * - msb u16 control; - */ - u32 w0; - /* address of memory in the End Point */ - u32 ep_addr; - /* bus address of source or destination memory in the Root Complex */ - u32 rc_addr_h; - u32 rc_addr_l; -} __attribute__ ((packed)); - -/** - * Descriptor Table, an array of descriptors describing a chained transfer. - * - * An array of descriptors, preceded by workspace for the End Point. - * It exists in Root Complex memory. - * - * The End Point can update its last completed descriptor number in the - * eplast field if requested by setting the EPLAST_ENA bit either - * globally in the header's or locally in any descriptor's control field. - * - * @note this structure may not exceed 4096 bytes. This results in a - * maximum of 4096 / (4 * 4) - 1 = 255 descriptors per chained transfer. - * - * @see ug_pci_express 8.0, tables 7-9, 7-10 and 7-11 at page 7-17 and page 7-18. - */ -struct ape_chdma_table { - /* workspace 0x00-0x0b, reserved */ - u32 reserved1[3]; - /* workspace 0x0c-0x0f, last descriptor handled by End Point */ - u32 w3; - /* the actual array of descriptors - * 0x10-0x1f, 0x20-0x2f, ... 0xff0-0xfff (255 entries) - */ - struct ape_chdma_desc desc[255]; -} __attribute__ ((packed)); - -/** - * Altera PCI Express ('ape') board specific book keeping data - * - * Keeps state of the PCIe core and the Chaining DMA controller - * application. - */ -struct ape_dev { - /** the kernel pci device data structure provided by probe() */ - struct pci_dev *pci_dev; - /** - * kernel virtual address of the mapped BAR memory and IO regions of - * the End Point. Used by map_bars()/unmap_bars(). - */ - void * __iomem bar[APE_BAR_NUM]; - /** kernel virtual address for Descriptor Table in Root Complex memory */ - struct ape_chdma_table *table_virt; - /** - * bus address for the Descriptor Table in Root Complex memory, in - * CPU-native endianess - */ - dma_addr_t table_bus; - /* if the device regions could not be allocated, assume and remember it - * is in use by another driver; this driver must not disable the device. - */ - int in_use; - /* whether this driver enabled msi for the device */ - int msi_enabled; - /* whether this driver could obtain the regions */ - int got_regions; - /* irq line successfully requested by this driver, -1 otherwise */ - int irq_line; - /* board revision */ - u8 revision; - /* interrupt count, incremented by the interrupt handler */ - int irq_count; -#if ALTPCIECHDMA_CDEV - /* character device */ - dev_t cdevno; - struct cdev cdev; - /* user space scatter gather mapper */ - struct sg_mapping_t *sgm; -#endif -}; - -/** - * Using the subsystem vendor id and subsystem id, it is possible to - * distinguish between different cards bases around the same - * (third-party) logic core. - * - * Default Altera vendor and device ID's, and some (non-reserved) - * ID's are now used here that are used amongst the testers/developers. - */ -static const struct pci_device_id ids[] = { - { PCI_DEVICE(0x1172, 0xE001), }, - { PCI_DEVICE(0x2071, 0x2071), }, - { 0, } -}; -MODULE_DEVICE_TABLE(pci, ids); - -#if ALTPCIECHDMA_CDEV -/* prototypes for character device */ -static int sg_init(struct ape_dev *ape); -static void sg_exit(struct ape_dev *ape); -#endif - -/** - * altpciechdma_isr() - Interrupt handler - * - */ -static irqreturn_t altpciechdma_isr(int irq, void *dev_id) -{ - struct ape_dev *ape = (struct ape_dev *)dev_id; - if (!ape) - return IRQ_NONE; - ape->irq_count++; - return IRQ_HANDLED; -} - -static int __devinit scan_bars(struct ape_dev *ape, struct pci_dev *dev) -{ - int i; - for (i = 0; i < APE_BAR_NUM; i++) { - unsigned long bar_start = pci_resource_start(dev, i); - if (bar_start) { - unsigned long bar_end = pci_resource_end(dev, i); - unsigned long bar_flags = pci_resource_flags(dev, i); - printk(KERN_DEBUG "BAR%d 0x%08lx-0x%08lx flags 0x%08lx\n", - i, bar_start, bar_end, bar_flags); - } - } - return 0; -} - -/** - * Unmap the BAR regions that had been mapped earlier using map_bars() - */ -static void unmap_bars(struct ape_dev *ape, struct pci_dev *dev) -{ - int i; - for (i = 0; i < APE_BAR_NUM; i++) { - /* is this BAR mapped? */ - if (ape->bar[i]) { - /* unmap BAR */ - pci_iounmap(dev, ape->bar[i]); - ape->bar[i] = NULL; - } - } -} - -/** - * Map the device memory regions into kernel virtual address space after - * verifying their sizes respect the minimum sizes needed, given by the - * bar_min_len[] array. - */ -static int __devinit map_bars(struct ape_dev *ape, struct pci_dev *dev) -{ - int rc; - int i; - /* iterate through all the BARs */ - for (i = 0; i < APE_BAR_NUM; i++) { - unsigned long bar_start = pci_resource_start(dev, i); - unsigned long bar_end = pci_resource_end(dev, i); - unsigned long bar_length = bar_end - bar_start + 1; - ape->bar[i] = NULL; - /* do not map, and skip, BARs with length 0 */ - if (!bar_min_len[i]) - continue; - /* do not map BARs with address 0 */ - if (!bar_start || !bar_end) { - printk(KERN_DEBUG "BAR #%d is not present?!\n", i); - rc = -1; - goto fail; - } - bar_length = bar_end - bar_start + 1; - /* BAR length is less than driver requires? */ - if (bar_length < bar_min_len[i]) { - printk(KERN_DEBUG "BAR #%d length = %lu bytes but driver " - "requires at least %lu bytes\n", - i, bar_length, bar_min_len[i]); - rc = -1; - goto fail; - } - /* map the device memory or IO region into kernel virtual - * address space */ - ape->bar[i] = pci_iomap(dev, i, bar_min_len[i]); - if (!ape->bar[i]) { - printk(KERN_DEBUG "Could not map BAR #%d.\n", i); - rc = -1; - goto fail; - } - printk(KERN_DEBUG "BAR[%d] mapped at 0x%p with length %lu(/%lu).\n", i, - ape->bar[i], bar_min_len[i], bar_length); - } - /* successfully mapped all required BAR regions */ - rc = 0; - goto success; -fail: - /* unmap any BARs that we did map */ - unmap_bars(ape, dev); -success: - return rc; -} - -#if 0 /* not yet implemented fully FIXME add opcode */ -static void __devinit rcslave_test(struct ape_dev *ape, struct pci_dev *dev) -{ - u32 *rcslave_mem = (u32 *)ape->bar[APE_BAR_RCSLAVE]; - u32 result = 0; - /** this number is assumed to be different each time this test runs */ - u32 seed = (u32)jiffies; - u32 value = seed; - int i; - - /* write loop */ - value = seed; - for (i = 1024; i < 32768 / 4 ; i++) { - printk(KERN_DEBUG "Writing 0x%08x to 0x%p.\n", - (u32)value, (void *)rcslave_mem + i); - iowrite32(value, rcslave_mem + i); - value++; - } - /* read-back loop */ - value = seed; - for (i = 1024; i < 32768 / 4; i++) { - result = ioread32(rcslave_mem + i); - if (result != value) { - printk(KERN_DEBUG "Wrote 0x%08x to 0x%p, but read back 0x%08x.\n", - (u32)value, (void *)rcslave_mem + i, (u32)result); - break; - } - value++; - } -} -#endif - -/* obtain the 32 most significant (high) bits of a 32-bit or 64-bit address */ -#define pci_dma_h(addr) ((addr >> 16) >> 16) -/* obtain the 32 least significant (low) bits of a 32-bit or 64-bit address */ -#define pci_dma_l(addr) (addr & 0xffffffffUL) - -/* ape_fill_chdma_desc() - Fill a Altera PCI Express Chaining DMA descriptor - * - * @desc pointer to descriptor to be filled - * @addr root complex address - * @ep_addr end point address - * @len number of bytes, must be a multiple of 4. - */ -static inline void ape_chdma_desc_set(struct ape_chdma_desc *desc, dma_addr_t addr, u32 ep_addr, int len) -{ - BUG_ON(len & 3); - desc->w0 = cpu_to_le32(len / 4); - desc->ep_addr = cpu_to_le32(ep_addr); - desc->rc_addr_h = cpu_to_le32(pci_dma_h(addr)); - desc->rc_addr_l = cpu_to_le32(pci_dma_l(addr)); -} - -#if ALTPCIECHDMA_CDEV -/* - * ape_sg_to_chdma_table() - Create a device descriptor table from a scatterlist. - * - * The scatterlist must have been mapped by pci_map_sg(sgm->sgl). - * - * @sgl scatterlist. - * @nents Number of entries in the scatterlist. - * @first Start index in the scatterlist sgm->sgl. - * @ep_addr End Point address for the scatter/gather transfer. - * @desc pointer to first descriptor - * - * Returns Number of entries in the table on success, -1 on error. - */ -static int ape_sg_to_chdma_table(struct scatterlist *sgl, int nents, int first, struct ape_chdma_desc *desc, u32 ep_addr) -{ - int i = first, j = 0; - /* inspect first entry */ - dma_addr_t addr = sg_dma_address(&sgl[i]); - unsigned int len = sg_dma_len(&sgl[i]); - /* contiguous block */ - dma_addr_t cont_addr = addr; - unsigned int cont_len = len; - /* iterate over remaining entries */ - for (; j < 25 && i < nents - 1; i++) { - /* bus address of next entry i + 1 */ - dma_addr_t next = sg_dma_address(&sgl[i + 1]); - /* length of this entry i */ - len = sg_dma_len(&sgl[i]); - printk(KERN_DEBUG "%04d: addr=0x%Lx length=0x%08x\n", i, - (unsigned long long)addr, len); - /* entry i + 1 is non-contiguous with entry i? */ - if (next != addr + len) { - /* TODO create entry here (we could overwrite i) */ - printk(KERN_DEBUG "%4d: cont_addr=0x%Lx cont_len=0x%08x\n", j, - (unsigned long long)cont_addr, cont_len); - /* set descriptor for contiguous transfer */ - ape_chdma_desc_set(&desc[j], cont_addr, ep_addr, cont_len); - /* next end point memory address */ - ep_addr += cont_len; - /* start new contiguous block */ - cont_addr = next; - cont_len = 0; - j++; - } - /* add entry i + 1 to current contiguous block */ - cont_len += len; - /* goto entry i + 1 */ - addr = next; - } - /* TODO create entry here (we could overwrite i) */ - printk(KERN_DEBUG "%04d: addr=0x%Lx length=0x%08x\n", i, - (unsigned long long)addr, len); - printk(KERN_DEBUG "%4d: cont_addr=0x%Lx length=0x%08x\n", j, - (unsigned long long)cont_addr, cont_len); - j++; - return j; -} -#endif - -/* compare buffers */ -static inline int compare(u32 *p, u32 *q, int len) -{ - int result = -1; - int fail = 0; - int i; - for (i = 0; i < len / 4; i++) { - if (*p == *q) { - /* every so many u32 words, show equals */ - if ((i & 255) == 0) - printk(KERN_DEBUG "[%p] = 0x%08x [%p] = 0x%08x\n", p, *p, q, *q); - } else { - fail++; - /* show the first few miscompares */ - if (fail < 10) - printk(KERN_DEBUG "[%p] = 0x%08x != [%p] = 0x%08x ?!\n", p, *p, q, *q); - /* but stop after a while */ - else if (fail == 10) - printk(KERN_DEBUG "---more errors follow! not printed---\n"); - else - /* stop compare after this many errors */ - break; - } - p++; - q++; - } - if (!fail) - result = 0; - return result; -} - -/* dma_test() - Perform DMA loop back test to end point and back to root complex. - * - * Allocate a cache-coherent buffer in host memory, consisting of four pages. - * - * Fill the four memory pages such that each 32-bit word contains its own address. - * - * Now perform a loop back test, have the end point device copy the first buffer - * half to end point memory, then have it copy back into the second half. - * - * Create a descriptor table to copy the first buffer half into End Point - * memory. Instruct the End Point to do a DMA read using that table. - * - * Create a descriptor table to copy End Point memory to the second buffer - * half. Instruct the End Point to do a DMA write using that table. - * - * Compare results, fail or pass. - * - */ -static int __devinit dma_test(struct ape_dev *ape, struct pci_dev *dev) -{ - /* test result; guilty until proven innocent */ - int result = -1; - /* the DMA read header sits at address 0x00 of the DMA engine BAR */ - struct ape_chdma_header *write_header = (struct ape_chdma_header *)ape->bar[APE_BAR_HEADER]; - /* the write DMA header sits after the read header at address 0x10 */ - struct ape_chdma_header *read_header = write_header + 1; - /* virtual address of the allocated buffer */ - u8 *buffer_virt = 0; - /* bus address of the allocated buffer */ - dma_addr_t buffer_bus = 0; - int i, n = 0, irq_count; - - /* temporary value used to construct 32-bit data words */ - u32 w; - - printk(KERN_DEBUG "bar_tests(), PAGE_SIZE = 0x%0x\n", (int)PAGE_SIZE); - printk(KERN_DEBUG "write_header = 0x%p.\n", write_header); - printk(KERN_DEBUG "read_header = 0x%p.\n", read_header); - printk(KERN_DEBUG "&write_header->w3 = 0x%p\n", &write_header->w3); - printk(KERN_DEBUG "&read_header->w3 = 0x%p\n", &read_header->w3); - printk(KERN_DEBUG "ape->table_virt = 0x%p.\n", ape->table_virt); - - if (!write_header || !read_header || !ape->table_virt) - goto fail; - - /* allocate and map coherently-cached memory for a DMA-able buffer */ - /* @see Documentation/PCI/PCI-DMA-mapping.txt, near line 318 */ - buffer_virt = (u8 *)pci_alloc_consistent(dev, PAGE_SIZE * 4, &buffer_bus); - if (!buffer_virt) { - printk(KERN_DEBUG "Could not allocate coherent DMA buffer.\n"); - goto fail; - } - printk(KERN_DEBUG "Allocated cache-coherent DMA buffer (virtual address = %p, bus address = 0x%016llx).\n", - buffer_virt, (u64)buffer_bus); - - /* fill first half of buffer with its virtual address as data */ - for (i = 0; i < 4 * PAGE_SIZE; i += 4) -#if 0 - *(u32 *)(buffer_virt + i) = i / PAGE_SIZE + 1; -#else - *(u32 *)(buffer_virt + i) = (u32)(unsigned long)(buffer_virt + i); -#endif -#if 0 - compare((u32 *)buffer_virt, (u32 *)(buffer_virt + 2 * PAGE_SIZE), 8192); -#endif - -#if 0 - /* fill second half of buffer with zeroes */ - for (i = 2 * PAGE_SIZE; i < 4 * PAGE_SIZE; i += 4) - *(u32 *)(buffer_virt + i) = 0; -#endif - - /* invalidate EPLAST, outside 0-255, 0xFADE is from the testbench */ - ape->table_virt->w3 = cpu_to_le32(0x0000FADE); - - /* fill in first descriptor */ - n = 0; - /* read 8192 bytes from RC buffer to EP address 4096 */ - ape_chdma_desc_set(&ape->table_virt->desc[n], buffer_bus, 4096, 2 * PAGE_SIZE); -#if 1 - for (i = 0; i < 255; i++) - ape_chdma_desc_set(&ape->table_virt->desc[i], buffer_bus, 4096, 2 * PAGE_SIZE); - /* index of last descriptor */ - n = i - 1; -#endif -#if 0 - /* fill in next descriptor */ - n++; - /* read 1024 bytes from RC buffer to EP address 4096 + 1024 */ - ape_chdma_desc_set(&ape->table_virt->desc[n], buffer_bus + 1024, 4096 + 1024, 1024); -#endif - -#if 1 - /* enable MSI after the last descriptor is completed */ - if (ape->msi_enabled) - ape->table_virt->desc[n].w0 |= cpu_to_le32(1UL << 16)/*local MSI*/; -#endif -#if 0 - /* dump descriptor table for debugging */ - printk(KERN_DEBUG "Descriptor Table (Read, in Root Complex Memory, # = %d)\n", n + 1); - for (i = 0; i < 4 + (n + 1) * 4; i += 4) { - u32 *p = (u32 *)ape->table_virt; - p += i; - printk(KERN_DEBUG "0x%08x/0x%02x: 0x%08x (LEN=0x%x)\n", (u32)p, (u32)p & 15, *p, 4 * le32_to_cpu(*p)); - p++; - printk(KERN_DEBUG "0x%08x/0x%02x: 0x%08x (EPA=0x%x)\n", (u32)p, (u32)p & 15, *p, le32_to_cpu(*p)); - p++; - printk(KERN_DEBUG "0x%08x/0x%02x: 0x%08x (RCH=0x%x)\n", (u32)p, (u32)p & 15, *p, le32_to_cpu(*p)); - p++; - printk(KERN_DEBUG "0x%08x/0x%02x: 0x%08x (RCL=0x%x)\n", (u32)p, (u32)p & 15, *p, le32_to_cpu(*p)); - } -#endif - /* set available number of descriptors in table */ - w = (u32)(n + 1); - w |= (1UL << 18)/*global EPLAST_EN*/; -#if 0 - if (ape->msi_enabled) - w |= (1UL << 17)/*global MSI*/; -#endif - printk(KERN_DEBUG "writing 0x%08x to 0x%p\n", w, (void *)&read_header->w0); - iowrite32(w, &read_header->w0); - - /* write table address (higher 32-bits) */ - printk(KERN_DEBUG "writing 0x%08x to 0x%p\n", (u32)((ape->table_bus >> 16) >> 16), (void *)&read_header->bdt_addr_h); - iowrite32(pci_dma_h(ape->table_bus), &read_header->bdt_addr_h); - - /* write table address (lower 32-bits) */ - printk(KERN_DEBUG "writing 0x%08x to 0x%p\n", (u32)(ape->table_bus & 0xffffffffUL), (void *)&read_header->bdt_addr_l); - iowrite32(pci_dma_l(ape->table_bus), &read_header->bdt_addr_l); - - /* memory write barrier */ - wmb(); - printk(KERN_DEBUG "Flush posted writes\n"); - /** FIXME Add dummy read to flush posted writes but need a readable location! */ -#if 0 - (void)ioread32(); -#endif - - /* remember IRQ count before the transfer */ - irq_count = ape->irq_count; - /* write number of descriptors - this starts the DMA */ - printk(KERN_DEBUG "\nStart DMA read\n"); - printk(KERN_DEBUG "writing 0x%08x to 0x%p\n", (u32)n, (void *)&read_header->w3); - iowrite32(n, &read_header->w3); - printk(KERN_DEBUG "EPLAST = %lu\n", le32_to_cpu(*(u32 *)&ape->table_virt->w3) & 0xffffUL); - - /** memory write barrier */ - wmb(); - /* dummy read to flush posted writes */ - /* FIXME Need a readable location! */ -#if 0 - (void)ioread32(); -#endif - printk(KERN_DEBUG "POLL FOR READ:\n"); - /* poll for chain completion, 1000 times 1 millisecond */ - for (i = 0; i < 100; i++) { - volatile u32 *p = &ape->table_virt->w3; - u32 eplast = le32_to_cpu(*p) & 0xffffUL; - printk(KERN_DEBUG "EPLAST = %u, n = %d\n", eplast, n); - if (eplast == n) { - printk(KERN_DEBUG "DONE\n"); - /* print IRQ count before the transfer */ - printk(KERN_DEBUG "#IRQs during transfer: %d\n", ape->irq_count - irq_count); - break; - } - udelay(100); - } - - /* invalidate EPLAST, outside 0-255, 0xFADE is from the testbench */ - ape->table_virt->w3 = cpu_to_le32(0x0000FADE); - - /* setup first descriptor */ - n = 0; - ape_chdma_desc_set(&ape->table_virt->desc[n], buffer_bus + 8192, 4096, 2 * PAGE_SIZE); -#if 1 - for (i = 0; i < 255; i++) - ape_chdma_desc_set(&ape->table_virt->desc[i], buffer_bus + 8192, 4096, 2 * PAGE_SIZE); - - /* index of last descriptor */ - n = i - 1; -#endif -#if 1 /* test variable, make a module option later */ - if (ape->msi_enabled) - ape->table_virt->desc[n].w0 |= cpu_to_le32(1UL << 16)/*local MSI*/; -#endif -#if 0 - /* dump descriptor table for debugging */ - printk(KERN_DEBUG "Descriptor Table (Write, in Root Complex Memory, # = %d)\n", n + 1); - for (i = 0; i < 4 + (n + 1) * 4; i += 4) { - u32 *p = (u32 *)ape->table_virt; - p += i; - printk(KERN_DEBUG "0x%08x/0x%02x: 0x%08x (LEN=0x%x)\n", (u32)p, (u32)p & 15, *p, 4 * le32_to_cpu(*p)); - p++; - printk(KERN_DEBUG "0x%08x/0x%02x: 0x%08x (EPA=0x%x)\n", (u32)p, (u32)p & 15, *p, le32_to_cpu(*p)); - p++; - printk(KERN_DEBUG "0x%08x/0x%02x: 0x%08x (RCH=0x%x)\n", (u32)p, (u32)p & 15, *p, le32_to_cpu(*p)); - p++; - printk(KERN_DEBUG "0x%08x/0x%02x: 0x%08x (RCL=0x%x)\n", (u32)p, (u32)p & 15, *p, le32_to_cpu(*p)); - } -#endif - - /* set number of available descriptors in the table */ - w = (u32)(n + 1); - /* enable updates of eplast for each descriptor completion */ - w |= (u32)(1UL << 18)/*global EPLAST_EN*/; -#if 0 /* test variable, make a module option later */ - /* enable MSI for each descriptor completion */ - if (ape->msi_enabled) - w |= (1UL << 17)/*global MSI*/; -#endif - iowrite32(w, &write_header->w0); - iowrite32(pci_dma_h(ape->table_bus), &write_header->bdt_addr_h); - iowrite32(pci_dma_l(ape->table_bus), &write_header->bdt_addr_l); - - /** memory write barrier and flush posted writes */ - wmb(); - /* dummy read to flush posted writes */ - /* FIXME Need a readable location! */ -#if 0 - (void)ioread32(); -#endif - irq_count = ape->irq_count; - - printk(KERN_DEBUG "\nStart DMA write\n"); - iowrite32(n, &write_header->w3); - - /** memory write barrier */ - wmb(); - /** dummy read to flush posted writes */ - /* (void) ioread32(); */ - - printk(KERN_DEBUG "POLL FOR WRITE:\n"); - /* poll for completion, 1000 times 1 millisecond */ - for (i = 0; i < 100; i++) { - volatile u32 *p = &ape->table_virt->w3; - u32 eplast = le32_to_cpu(*p) & 0xffffUL; - printk(KERN_DEBUG "EPLAST = %u, n = %d\n", eplast, n); - if (eplast == n) { - printk(KERN_DEBUG "DONE\n"); - /* print IRQ count before the transfer */ - printk(KERN_DEBUG "#IRQs during transfer: %d\n", ape->irq_count - irq_count); - break; - } - udelay(100); - } - /* soft-reset DMA write engine */ - iowrite32(0x0000ffffUL, &write_header->w0); - /* soft-reset DMA read engine */ - iowrite32(0x0000ffffUL, &read_header->w0); - - /** memory write barrier */ - wmb(); - /* dummy read to flush posted writes */ - /* FIXME Need a readable location! */ -#if 0 - (void)ioread32(); -#endif - /* compare first half of buffer with second half, should be identical */ - result = compare((u32 *)buffer_virt, (u32 *)(buffer_virt + 2 * PAGE_SIZE), 8192); - printk(KERN_DEBUG "DMA loop back test %s.\n", result ? "FAILED" : "PASSED"); - - pci_free_consistent(dev, 4 * PAGE_SIZE, buffer_virt, buffer_bus); -fail: - printk(KERN_DEBUG "bar_tests() end, result %d\n", result); - return result; -} - -/* Called when the PCI sub system thinks we can control the given device. - * Inspect if we can support the device and if so take control of it. - * - * Return 0 when we have taken control of the given device. - * - * - allocate board specific bookkeeping - * - allocate coherently-mapped memory for the descriptor table - * - enable the board - * - verify board revision - * - request regions - * - query DMA mask - * - obtain and request irq - * - map regions into kernel address space - */ -static int __devinit probe(struct pci_dev *dev, const struct pci_device_id *id) -{ - int rc = 0; - struct ape_dev *ape = NULL; - u8 irq_pin, irq_line; - printk(KERN_DEBUG "probe(dev = 0x%p, pciid = 0x%p)\n", dev, id); - - /* allocate memory for per-board book keeping */ - ape = kzalloc(sizeof(struct ape_dev), GFP_KERNEL); - if (!ape) { - printk(KERN_DEBUG "Could not kzalloc()ate memory.\n"); - goto err_ape; - } - ape->pci_dev = dev; - dev_set_drvdata(&dev->dev, ape); - printk(KERN_DEBUG "probe() ape = 0x%p\n", ape); - - printk(KERN_DEBUG "sizeof(struct ape_chdma_table) = %d.\n", - (int)sizeof(struct ape_chdma_table)); - /* the reference design has a size restriction on the table size */ - BUG_ON(sizeof(struct ape_chdma_table) > APE_CHDMA_TABLE_SIZE); - - /* allocate and map coherently-cached memory for a descriptor table */ - /* @see LDD3 page 446 */ - ape->table_virt = (struct ape_chdma_table *)pci_alloc_consistent(dev, - APE_CHDMA_TABLE_SIZE, &ape->table_bus); - /* could not allocate table? */ - if (!ape->table_virt) { - printk(KERN_DEBUG "Could not dma_alloc()ate_coherent memory.\n"); - goto err_table; - } - - printk(KERN_DEBUG "table_virt = %p, table_bus = 0x%16llx.\n", - ape->table_virt, (u64)ape->table_bus); - - /* enable device */ - rc = pci_enable_device(dev); - if (rc) { - printk(KERN_DEBUG "pci_enable_device() failed\n"); - goto err_enable; - } - - /* enable bus master capability on device */ - pci_set_master(dev); - /* enable message signaled interrupts */ - rc = pci_enable_msi(dev); - /* could not use MSI? */ - if (rc) { - /* resort to legacy interrupts */ - printk(KERN_DEBUG "Could not enable MSI interrupting.\n"); - ape->msi_enabled = 0; - /* MSI enabled, remember for cleanup */ - } else { - printk(KERN_DEBUG "Enabled MSI interrupting.\n"); - ape->msi_enabled = 1; - } - - pci_read_config_byte(dev, PCI_REVISION_ID, &ape->revision); -#if 0 /* example */ - /* (for example) this driver does not support revision 0x42 */ - if (ape->revision == 0x42) { - printk(KERN_DEBUG "Revision 0x42 is not supported by this driver.\n"); - rc = -ENODEV; - goto err_rev; - } -#endif - /** XXX check for native or legacy PCIe endpoint? */ - - rc = pci_request_regions(dev, DRV_NAME); - /* could not request all regions? */ - if (rc) { - /* assume device is in use (and do not disable it later!) */ - ape->in_use = 1; - goto err_regions; - } - ape->got_regions = 1; - -#if 1 /* @todo For now, disable 64-bit, because I do not understand the implications (DAC!) */ - /* query for DMA transfer */ - /* @see Documentation/PCI/PCI-DMA-mapping.txt */ - if (!pci_set_dma_mask(dev, DMA_BIT_MASK(64))) { - pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64)); - /* use 64-bit DMA */ - printk(KERN_DEBUG "Using a 64-bit DMA mask.\n"); - } else -#endif - if (!pci_set_dma_mask(dev, DMA_BIT_MASK(32))) { - printk(KERN_DEBUG "Could not set 64-bit DMA mask.\n"); - pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(32)); - /* use 32-bit DMA */ - printk(KERN_DEBUG "Using a 32-bit DMA mask.\n"); - } else { - printk(KERN_DEBUG "No suitable DMA possible.\n"); - /** @todo Choose proper error return code */ - rc = -1; - goto err_mask; - } - - rc = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq_pin); - /* could not read? */ - if (rc) - goto err_irq; - printk(KERN_DEBUG "IRQ pin #%d (0=none, 1=INTA#...4=INTD#).\n", irq_pin); - - /* @see LDD3, page 318 */ - rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq_line); - /* could not read? */ - if (rc) { - printk(KERN_DEBUG "Could not query PCI_INTERRUPT_LINE, error %d\n", rc); - goto err_irq; - } - printk(KERN_DEBUG "IRQ line #%d.\n", irq_line); -#if 1 - irq_line = dev->irq; - /* @see LDD3, page 259 */ - rc = request_irq(irq_line, altpciechdma_isr, IRQF_SHARED, DRV_NAME, (void *)ape); - if (rc) { - printk(KERN_DEBUG "Could not request IRQ #%d, error %d\n", irq_line, rc); - ape->irq_line = -1; - goto err_irq; - } - /* remember which irq we allocated */ - ape->irq_line = (int)irq_line; - printk(KERN_DEBUG "Successfully requested IRQ #%d with dev_id 0x%p\n", irq_line, ape); -#endif - /* show BARs */ - scan_bars(ape, dev); - /* map BARs */ - rc = map_bars(ape, dev); - if (rc) - goto err_map; -#if ALTPCIECHDMA_CDEV - /* initialize character device */ - rc = sg_init(ape); - if (rc) - goto err_cdev; -#endif - /* perform DMA engines loop back test */ - rc = dma_test(ape, dev); - (void)rc; - /* successfully took the device */ - rc = 0; - printk(KERN_DEBUG "probe() successful.\n"); - goto end; -#if ALTPCIECHDMA_CDEV -err_cdev: - /* unmap the BARs */ - unmap_bars(ape, dev); -#endif -err_map: - /* free allocated irq */ - if (ape->irq_line >= 0) - free_irq(ape->irq_line, (void *)ape); -err_irq: - if (ape->msi_enabled) - pci_disable_msi(dev); - /* disable the device iff it is not in use */ - if (!ape->in_use) - pci_disable_device(dev); - if (ape->got_regions) - pci_release_regions(dev); -err_mask: -err_regions: -/*err_rev:*/ -/* clean up everything before device enable() */ -err_enable: - if (ape->table_virt) - pci_free_consistent(dev, APE_CHDMA_TABLE_SIZE, ape->table_virt, ape->table_bus); -/* clean up everything before allocating descriptor table */ -err_table: - if (ape) - kfree(ape); -err_ape: -end: - return rc; -} - -static void __devexit remove(struct pci_dev *dev) -{ - struct ape_dev *ape = dev_get_drvdata(&dev->dev); - - printk(KERN_DEBUG "remove(0x%p)\n", dev); - printk(KERN_DEBUG "remove(dev = 0x%p) where ape = 0x%p\n", dev, ape); - - /* remove character device */ -#if ALTPCIECHDMA_CDEV - sg_exit(ape); -#endif - - if (ape->table_virt) - pci_free_consistent(dev, APE_CHDMA_TABLE_SIZE, ape->table_virt, ape->table_bus); - - /* free IRQ - * @see LDD3 page 279 - */ - if (ape->irq_line >= 0) { - printk(KERN_DEBUG "Freeing IRQ #%d for dev_id 0x%08lx.\n", - ape->irq_line, (unsigned long)ape); - free_irq(ape->irq_line, (void *)ape); - } - /* MSI was enabled? */ - if (ape->msi_enabled) { - /* Disable MSI @see Documentation/MSI-HOWTO.txt */ - pci_disable_msi(dev); - ape->msi_enabled = 0; - } - /* unmap the BARs */ - unmap_bars(ape, dev); - if (!ape->in_use) - pci_disable_device(dev); - if (ape->got_regions) - /* to be called after device disable */ - pci_release_regions(dev); -} - -#if ALTPCIECHDMA_CDEV - -/* - * Called when the device goes from unused to used. - */ -static int sg_open(struct inode *inode, struct file *file) -{ - struct ape_dev *ape; - printk(KERN_DEBUG DRV_NAME "_open()\n"); - /* pointer to containing data structure of the character device inode */ - ape = container_of(inode->i_cdev, struct ape_dev, cdev); - /* create a reference to our device state in the opened file */ - file->private_data = ape; - /* create virtual memory mapper */ - ape->sgm = sg_create_mapper(MAX_CHDMA_SIZE); - return 0; -} - -/* - * Called when the device goes from used to unused. - */ -static int sg_close(struct inode *inode, struct file *file) -{ - /* fetch device specific data stored earlier during open */ - struct ape_dev *ape = (struct ape_dev *)file->private_data; - printk(KERN_DEBUG DRV_NAME "_close()\n"); - /* destroy virtual memory mapper */ - sg_destroy_mapper(ape->sgm); - return 0; -} - -static ssize_t sg_read(struct file *file, char __user *buf, size_t count, loff_t *pos) -{ - /* fetch device specific data stored earlier during open */ - struct ape_dev *ape = (struct ape_dev *)file->private_data; - (void)ape; - printk(KERN_DEBUG DRV_NAME "_read(buf=0x%p, count=%lld, pos=%llu)\n", buf, (s64)count, (u64)*pos); - return count; -} - -/* sg_write() - Write to the device - * - * @buf userspace buffer - * @count number of bytes in the userspace buffer - * - * Iterate over the userspace buffer, taking at most 255 * PAGE_SIZE bytes for - * each DMA transfer. - * For each transfer, get the user pages, build a sglist, map, build a - * descriptor table. submit the transfer. wait for the interrupt handler - * to wake us on completion. - */ -static ssize_t sg_write(struct file *file, const char __user *buf, size_t count, loff_t *pos) -{ - int hwnents, tents; - size_t transfer_len, remaining = count, done = 0; - u64 transfer_addr = (u64)buf; - /* fetch device specific data stored earlier during open */ - struct ape_dev *ape = (struct ape_dev *)file->private_data; - printk(KERN_DEBUG DRV_NAME "_write(buf=0x%p, count=%lld, pos=%llu)\n", - buf, (s64)count, (u64)*pos); - /* TODO transfer boundaries at PAGE_SIZE granularity */ - while (remaining > 0) { - /* limit DMA transfer size */ - transfer_len = (remaining < APE_CHDMA_MAX_TRANSFER_LEN) ? remaining : - APE_CHDMA_MAX_TRANSFER_LEN; - /* get all user space buffer pages and create a scattergather list */ - sgm_map_user_pages(ape->sgm, transfer_addr, transfer_len, 0/*read from userspace*/); - printk(KERN_DEBUG DRV_NAME "mapped_pages=%d\n", ape->sgm->mapped_pages); - /* map all entries in the scattergather list */ - hwnents = pci_map_sg(ape->pci_dev, ape->sgm->sgl, ape->sgm->mapped_pages, DMA_TO_DEVICE); - printk(KERN_DEBUG DRV_NAME "hwnents=%d\n", hwnents); - /* build device descriptor tables and submit them to the DMA engine */ - tents = ape_sg_to_chdma_table(ape->sgm->sgl, hwnents, 0, &ape->table_virt->desc[0], 4096); - printk(KERN_DEBUG DRV_NAME "tents=%d\n", hwnents); -#if 0 - while (tables) { - /* TODO build table */ - /* TODO submit table to the device */ - /* if engine stopped and unfinished work then start engine */ - } - put ourselves on wait queue -#endif - - dma_unmap_sg(NULL, ape->sgm->sgl, ape->sgm->mapped_pages, DMA_TO_DEVICE); - /* dirty and free the pages */ - sgm_unmap_user_pages(ape->sgm, 1/*dirtied*/); - /* book keeping */ - transfer_addr += transfer_len; - remaining -= transfer_len; - done += transfer_len; - } - return done; -} - -/* - * character device file operations - */ -static const struct file_operations sg_fops = { - .owner = THIS_MODULE, - .open = sg_open, - .release = sg_close, - .read = sg_read, - .write = sg_write, -}; - -/* sg_init() - Initialize character device - * - * XXX Should ideally be tied to the device, on device probe, not module init. - */ -static int sg_init(struct ape_dev *ape) -{ - int rc; - printk(KERN_DEBUG DRV_NAME " sg_init()\n"); - /* allocate a dynamically allocated character device node */ - rc = alloc_chrdev_region(&ape->cdevno, 0/*requested minor*/, 1/*count*/, DRV_NAME); - /* allocation failed? */ - if (rc < 0) { - printk("alloc_chrdev_region() = %d\n", rc); - goto fail_alloc; - } - /* couple the device file operations to the character device */ - cdev_init(&ape->cdev, &sg_fops); - ape->cdev.owner = THIS_MODULE; - /* bring character device live */ - rc = cdev_add(&ape->cdev, ape->cdevno, 1/*count*/); - if (rc < 0) { - printk("cdev_add() = %d\n", rc); - goto fail_add; - } - printk(KERN_DEBUG "altpciechdma = %d:%d\n", MAJOR(ape->cdevno), MINOR(ape->cdevno)); - return 0; -fail_add: - /* free the dynamically allocated character device node */ - unregister_chrdev_region(ape->cdevno, 1/*count*/); -fail_alloc: - return -1; -} - -/* sg_exit() - Cleanup character device - * - * XXX Should ideally be tied to the device, on device remove, not module exit. - */ - -static void sg_exit(struct ape_dev *ape) -{ - printk(KERN_DEBUG DRV_NAME " sg_exit()\n"); - /* remove the character device */ - cdev_del(&ape->cdev); - /* free the dynamically allocated character device node */ - unregister_chrdev_region(ape->cdevno, 1/*count*/); -} - -#endif /* ALTPCIECHDMA_CDEV */ - -/* used to register the driver with the PCI kernel sub system - * @see LDD3 page 311 - */ -static struct pci_driver pci_driver = { - .name = DRV_NAME, - .id_table = ids, - .probe = probe, - .remove = __devexit_p(remove), - /* resume, suspend are optional */ -}; - -/** - * alterapciechdma_init() - Module initialization, registers devices. - */ -static int __init alterapciechdma_init(void) -{ - int rc = 0; - printk(KERN_DEBUG DRV_NAME " init(), built at " __DATE__ " " __TIME__ "\n"); - /* register this driver with the PCI bus driver */ - rc = pci_register_driver(&pci_driver); - if (rc < 0) - return rc; - return 0; -} - -/** - * alterapciechdma_init() - Module cleanup, unregisters devices. - */ -static void __exit alterapciechdma_exit(void) -{ - printk(KERN_DEBUG DRV_NAME " exit(), built at " __DATE__ " " __TIME__ "\n"); - /* unregister this driver from the PCI bus driver */ - pci_unregister_driver(&pci_driver); -} - -MODULE_LICENSE("GPL"); - -module_init(alterapciechdma_init); -module_exit(alterapciechdma_exit); - -- cgit v1.2.3 From 7963eb432be2ebbf7e740bcdf6b385cc68fb7627 Mon Sep 17 00:00:00 2001 From: Jarod Wilson Date: Mon, 4 Jan 2010 18:02:27 -0500 Subject: staging: add Broadcom Crystal HD driver This patch supersedes the earlier ones sent by Manu Abraham to add the Broadcom Crystal HD driver to the staging tree, per discussion with him about it. I've been working with Broadcom's Naren Sankar on this driver for a number of months, and had already talked Naren about submitting this on Broadcom's behalf, didn't expect anyone else to jump on submitting it as quickly as Manu did. ;) This version is a one-shot deal, incorporating the original driver, Manu's coding style clean-ups, udev device creation support from Edgar 'gimli' Hucek, and a number of other small tweaks from myself and Scott Davilla, the other individual who has been working closely on this code with Naren and I. I've tested this iteration of the code lightly on a mini pci-e board in a ThinkPad T61p running x86_64 Fedora 12, with the expected results, and will test further on other systems with other variants of the card (I have three varieties of this device currently in hand). Scott has also tested on assorted primarily i686 varieties of Ubuntu, and Naren has tested with both Fedora and Ubuntu, iirc. Note: only the 70012 is currently supported by this driver, 70015 support will follow later. Also note that Blu-Ray support isn't enabled (at the firmware level), due to misc fun related to the BD encryption scheme, DRM, etc. :\ I *do* have a git tree containing the driver, lib, gst plugin and firmware that I'm working from at the moment[*], as there are inter- dependencies between the driver and lib, and the driver can be used with kernels going a ways back (I've only tested back to 2.6.18 as it exists in Red Hat Enterprise Linux 5). I'm exporting from there, into a linux-next tree, then generating patches from there. The goal is to feed everything upstream as quickly as possible, but there are users who want this code for earlier kernels too... The firmware will be submitted for inclusion in dwmw2's linux-firmware tree once there is a suitable redistribution-no-modification type of license on it (I believe Naren is working with Broadcom legal to get that in place). Changelog from initial Broadcom release to here: commit d20475d444610c5683d09e63f707f5bb22359062 Author: Jarod Wilson Date: Mon Jan 4 13:55:16 2010 -0500 include: lib doesn't build w/o the removed stdint include So add it back... Signed-off-by: Jarod Wilson commit c181070a330530b792d2b80e3ec6ab12a5a57394 Author: Scott Davilla Date: Mon Jan 4 13:38:37 2010 -0500 include: don't define VOID if its already defined Signed-off-by: Scott Davilla Signed-off-by: Jarod Wilson commit 33d8a2b691e81212e398f53770578d79650bf0bc Author: Jarod Wilson Date: Mon Jan 4 13:12:10 2010 -0500 driver: create crystalhd device using udev Based on: http://sourceforge.net/apps/trac/archvdr/browser/trunk/archvdr/crystalhd/use_udev.patch Signed-off-by: Edgar ( gimli ) Hucek Formatting tweaks, error-handling path fixups and any bugs added by Jarod. Signed-off-by: Jarod Wilson commit c44c64dea5537814796fcbe2d9db0209383c78b9 Author: Manu Abraham Date: Mon Jan 4 10:32:47 2010 -0500 crystalhd: coding style cleanups Signed-off-by: Manu Abraham Signed-off-by: Jarod Wilson commit cffa6da7467ff697a656d1dfff54bb0513a053dc Author: Jarod Wilson Date: Mon Jan 4 10:17:27 2010 -0500 crystalhd: run dos2unix over everything, this is linux source... Signed-off-by: Jarod Wilson commit 7fa38a282db7af5a5746055f7c6cef8a9b8ee138 Author: Jarod Wilson Date: Mon Jan 4 10:02:33 2010 -0500 crystalhd: initial import of released Broadcom code Straight import of: http://www.broadcom.com/docs/support/crystalhd/crystalhd_linux_20091229.zip Unfortunately, we're unable to publicly publish all the history that got us from the initial internal code to what was released here, but such is life, we can just be happy we've got this open-sourced now. :) Signed-off-by: Jarod Wilson Signed-off-by: Naren Sankar Signed-off-by: Scott Davilla Signed-off-by: Manu Abraham Signed-off-by: Jarod Wilson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/Kconfig | 2 + drivers/staging/Makefile | 1 + drivers/staging/crystalhd/Kconfig | 6 + drivers/staging/crystalhd/Makefile | 6 + drivers/staging/crystalhd/TODO | 16 + drivers/staging/crystalhd/bc_dts_defs.h | 498 ++ drivers/staging/crystalhd/bc_dts_glob_lnx.h | 299 + drivers/staging/crystalhd/bc_dts_types.h | 115 + drivers/staging/crystalhd/bcm_70012_regs.h | 12299 ++++++++++++++++++++++++++ drivers/staging/crystalhd/crystalhd_cmds.c | 1058 +++ drivers/staging/crystalhd/crystalhd_cmds.h | 88 + drivers/staging/crystalhd/crystalhd_fw_if.h | 369 + drivers/staging/crystalhd/crystalhd_hw.c | 2395 +++++ drivers/staging/crystalhd/crystalhd_hw.h | 398 + drivers/staging/crystalhd/crystalhd_lnx.c | 780 ++ drivers/staging/crystalhd/crystalhd_lnx.h | 95 + drivers/staging/crystalhd/crystalhd_misc.c | 1029 +++ drivers/staging/crystalhd/crystalhd_misc.h | 229 + 18 files changed, 19683 insertions(+) create mode 100644 drivers/staging/crystalhd/Kconfig create mode 100644 drivers/staging/crystalhd/Makefile create mode 100644 drivers/staging/crystalhd/TODO create mode 100644 drivers/staging/crystalhd/bc_dts_defs.h create mode 100644 drivers/staging/crystalhd/bc_dts_glob_lnx.h create mode 100644 drivers/staging/crystalhd/bc_dts_types.h create mode 100644 drivers/staging/crystalhd/bcm_70012_regs.h create mode 100644 drivers/staging/crystalhd/crystalhd_cmds.c create mode 100644 drivers/staging/crystalhd/crystalhd_cmds.h create mode 100644 drivers/staging/crystalhd/crystalhd_fw_if.h create mode 100644 drivers/staging/crystalhd/crystalhd_hw.c create mode 100644 drivers/staging/crystalhd/crystalhd_hw.h create mode 100644 drivers/staging/crystalhd/crystalhd_lnx.c create mode 100644 drivers/staging/crystalhd/crystalhd_lnx.h create mode 100644 drivers/staging/crystalhd/crystalhd_misc.c create mode 100644 drivers/staging/crystalhd/crystalhd_misc.h (limited to 'drivers') diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 9543174360bf..4a2afe7d0078 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -139,5 +139,7 @@ source "drivers/staging/sm7xx/Kconfig" source "drivers/staging/dt3155/Kconfig" +source "drivers/staging/crystalhd/Kconfig" + endif # !STAGING_EXCLUDE_BUILD endif # STAGING diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index 394327a1f789..dc404936a862 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_PCMCIA_WAVELAN) += wavelan/ obj-$(CONFIG_PCMCIA_NETWAVE) += netwave/ obj-$(CONFIG_FB_SM7XX) += sm7xx/ obj-$(CONFIG_DT3155) += dt3155/ +obj-$(CONFIG_CRYSTALHD) += crystalhd/ diff --git a/drivers/staging/crystalhd/Kconfig b/drivers/staging/crystalhd/Kconfig new file mode 100644 index 000000000000..56b414bca1a1 --- /dev/null +++ b/drivers/staging/crystalhd/Kconfig @@ -0,0 +1,6 @@ +config CRYSTALHD + tristate "Broadcom Crystal HD video decoder support" + depends on PCI + default n + help + Support for the Broadcom Crystal HD video decoder chipset diff --git a/drivers/staging/crystalhd/Makefile b/drivers/staging/crystalhd/Makefile new file mode 100644 index 000000000000..e2af0ce2e792 --- /dev/null +++ b/drivers/staging/crystalhd/Makefile @@ -0,0 +1,6 @@ +obj-$(CONFIG_CRYSTALHD) += crystalhd.o + +crystalhd-objs := crystalhd_cmds.o \ + crystalhd_hw.o \ + crystalhd_lnx.o \ + crystalhd_misc.o diff --git a/drivers/staging/crystalhd/TODO b/drivers/staging/crystalhd/TODO new file mode 100644 index 000000000000..69be5d0cb80c --- /dev/null +++ b/drivers/staging/crystalhd/TODO @@ -0,0 +1,16 @@ +- Testing +- Cleanup return codes +- Cleanup typedefs +- Cleanup all WIN* references +- Allocate an Accelerator device class specific Major number, + since we don't have any other open sourced accelerators, it is the only + one in that category for now. + A somewhat similar device is the DXR2/3 + +Please send patches to: +Greg Kroah-Hartman +Naren Sankar +Jarod Wilson +Scott Davilla +Manu Abraham + diff --git a/drivers/staging/crystalhd/bc_dts_defs.h b/drivers/staging/crystalhd/bc_dts_defs.h new file mode 100644 index 000000000000..c34cc07127b8 --- /dev/null +++ b/drivers/staging/crystalhd/bc_dts_defs.h @@ -0,0 +1,498 @@ +/******************************************************************** + * Copyright(c) 2006-2009 Broadcom Corporation. + * + * Name: bc_dts_defs.h + * + * Description: Common definitions for all components. Only types + * is allowed to be included from this file. + * + * AU + * + * HISTORY: + * + ******************************************************************** + * This header is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation, either version 2.1 of the License. + * + * This header is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * You should have received a copy of the GNU Lesser General Public License + * along with this header. If not, see . + *******************************************************************/ + +#ifndef _BC_DTS_DEFS_H_ +#define _BC_DTS_DEFS_H_ + +#include "bc_dts_types.h" + +/* BIT Mask */ +#define BC_BIT(_x) (1 << (_x)) + +typedef enum _BC_STATUS { + BC_STS_SUCCESS = 0, + BC_STS_INV_ARG = 1, + BC_STS_BUSY = 2, + BC_STS_NOT_IMPL = 3, + BC_STS_PGM_QUIT = 4, + BC_STS_NO_ACCESS = 5, + BC_STS_INSUFF_RES = 6, + BC_STS_IO_ERROR = 7, + BC_STS_NO_DATA = 8, + BC_STS_VER_MISMATCH = 9, + BC_STS_TIMEOUT = 10, + BC_STS_FW_CMD_ERR = 11, + BC_STS_DEC_NOT_OPEN = 12, + BC_STS_ERR_USAGE = 13, + BC_STS_IO_USER_ABORT = 14, + BC_STS_IO_XFR_ERROR = 15, + BC_STS_DEC_NOT_STARTED = 16, + BC_STS_FWHEX_NOT_FOUND = 17, + BC_STS_FMT_CHANGE = 18, + BC_STS_HIF_ACCESS = 19, + BC_STS_CMD_CANCELLED = 20, + BC_STS_FW_AUTH_FAILED = 21, + BC_STS_BOOTLOADER_FAILED = 22, + BC_STS_CERT_VERIFY_ERROR = 23, + BC_STS_DEC_EXIST_OPEN = 24, + BC_STS_PENDING = 25, + BC_STS_CLK_NOCHG = 26, + + /* Must be the last one.*/ + BC_STS_ERROR = -1 +} BC_STATUS; + +/*------------------------------------------------------* + * Registry Key Definitions * + *------------------------------------------------------*/ +#define BC_REG_KEY_MAIN_PATH "Software\\Broadcom\\MediaPC\\70010" +#define BC_REG_KEY_FWPATH "FirmwareFilePath" +#define BC_REG_KEY_SEC_OPT "DbgOptions" + +/* + * Options: + * + * b[5] = Enable RSA KEY in EEPROM Support + * b[6] = Enable Old PIB scheme. (0 = Use PIB with video scheme) + * + * b[12] = Enable send message to NotifyIcon + * + */ + +typedef enum _BC_SW_OPTIONS { + BC_OPT_DOSER_OUT_ENCRYPT = BC_BIT(3), + BC_OPT_LINK_OUT_ENCRYPT = BC_BIT(29), +} BC_SW_OPTIONS; + +typedef struct _BC_REG_CONFIG{ + uint32_t DbgOptions; +} BC_REG_CONFIG; + +#if defined(__KERNEL__) || defined(__LINUX_USER__) +#else +/* Align data structures */ +#define ALIGN(x) __declspec(align(x)) +#endif + +/* mode + * b[0]..b[7] = _DtsDeviceOpenMode + * b[8] = Load new FW + * b[9] = Load file play back FW + * b[10] = Disk format (0 for HD DVD and 1 for BLU ray) + * b[11]-b[15] = default output resolution + * b[16] = Skip TX CPB Buffer Check + * b[17] = Adaptive Output Encrypt/Scramble Scheme + * b[18]-b[31] = reserved for future use + */ + +/* To allow multiple apps to open the device. */ +enum _DtsDeviceOpenMode { + DTS_PLAYBACK_MODE = 0, + DTS_DIAG_MODE, + DTS_MONITOR_MODE, + DTS_HWINIT_MODE +}; + +/* To enable the filter to selectively enable/disable fixes or erratas */ +enum _DtsDeviceFixMode { + DTS_LOAD_NEW_FW = BC_BIT(8), + DTS_LOAD_FILE_PLAY_FW = BC_BIT(9), + DTS_DISK_FMT_BD = BC_BIT(10), + /* b[11]-b[15] : Default output resolution */ + DTS_SKIP_TX_CHK_CPB = BC_BIT(16), + DTS_ADAPTIVE_OUTPUT_PER = BC_BIT(17), + DTS_INTELLIMAP = BC_BIT(18), + /* b[19]-b[21] : select clock frequency */ + DTS_PLAYBACK_DROP_RPT_MODE = BC_BIT(22) +}; + +#define DTS_DFLT_RESOLUTION(x) (x<<11) + +#define DTS_DFLT_CLOCK(x) (x<<19) + +/* F/W File Version corresponding to S/W Releases */ +enum _FW_FILE_VER { + /* S/W release: 02.04.02 F/W release 2.12.2.0 */ + BC_FW_VER_020402 = ((12<<16) | (2<<8) | (0)) +}; + +/*------------------------------------------------------* + * Stream Types for DtsOpenDecoder() * + *------------------------------------------------------*/ +enum _DtsOpenDecStreamTypes { + BC_STREAM_TYPE_ES = 0, + BC_STREAM_TYPE_PES = 1, + BC_STREAM_TYPE_TS = 2, + BC_STREAM_TYPE_ES_TSTAMP = 6, +}; + +/*------------------------------------------------------* + * Video Algorithms for DtsSetVideoParams() * + *------------------------------------------------------*/ +enum _DtsSetVideoParamsAlgo { + BC_VID_ALGO_H264 = 0, + BC_VID_ALGO_MPEG2 = 1, + BC_VID_ALGO_VC1 = 4, + BC_VID_ALGO_VC1MP = 7, +}; + +/*------------------------------------------------------* + * MPEG Extension to the PPB * + *------------------------------------------------------*/ +#define BC_MPEG_VALID_PANSCAN (1) + +typedef struct _BC_PIB_EXT_MPEG { + uint32_t valid; + /* Always valid, defaults to picture size if no + * sequence display extension in the stream. */ + uint32_t display_horizontal_size; + uint32_t display_vertical_size; + + /* MPEG_VALID_PANSCAN + * Offsets are a copy values from the MPEG stream. */ + uint32_t offset_count; + int32_t horizontal_offset[3]; + int32_t vertical_offset[3]; + +} BC_PIB_EXT_MPEG; + +/*------------------------------------------------------* + * H.264 Extension to the PPB * + *------------------------------------------------------*/ +/* Bit definitions for 'other.h264.valid' field */ +#define H264_VALID_PANSCAN (1) +#define H264_VALID_SPS_CROP (2) +#define H264_VALID_VUI (4) + +typedef struct _BC_PIB_EXT_H264 { + /* 'valid' specifies which fields (or sets of + * fields) below are valid. If the corresponding + * bit in 'valid' is NOT set then that field(s) + * is (are) not initialized. */ + uint32_t valid; + + /* H264_VALID_PANSCAN */ + uint32_t pan_scan_count; + int32_t pan_scan_left[3]; + int32_t pan_scan_right[3]; + int32_t pan_scan_top[3]; + int32_t pan_scan_bottom[3]; + + /* H264_VALID_SPS_CROP */ + int32_t sps_crop_left; + int32_t sps_crop_right; + int32_t sps_crop_top; + int32_t sps_crop_bottom; + + /* H264_VALID_VUI */ + uint32_t chroma_top; + uint32_t chroma_bottom; + +} BC_PIB_EXT_H264; + +/*------------------------------------------------------* + * VC1 Extension to the PPB * + *------------------------------------------------------*/ +#define VC1_VALID_PANSCAN (1) + +typedef struct _BC_PIB_EXT_VC1 { + uint32_t valid; + + /* Always valid, defaults to picture size if no + * sequence display extension in the stream. */ + uint32_t display_horizontal_size; + uint32_t display_vertical_size; + + /* VC1 pan scan windows */ + uint32_t num_panscan_windows; + int32_t ps_horiz_offset[4]; + int32_t ps_vert_offset[4]; + int32_t ps_width[4]; + int32_t ps_height[4]; + +} BC_PIB_EXT_VC1; + + +/*------------------------------------------------------* + * Picture Information Block * + *------------------------------------------------------*/ +#if defined(_WIN32) || defined(_WIN64) || defined(__LINUX_USER__) +/* Values for 'pulldown' field. '0' means no pulldown information + * was present for this picture. */ +enum { + vdecNoPulldownInfo = 0, + vdecTop = 1, + vdecBottom = 2, + vdecTopBottom = 3, + vdecBottomTop = 4, + vdecTopBottomTop = 5, + vdecBottomTopBottom = 6, + vdecFrame_X2 = 7, + vdecFrame_X3 = 8, + vdecFrame_X1 = 9, + vdecFrame_X4 = 10, +}; + +/* Values for the 'frame_rate' field. */ +enum { + vdecFrameRateUnknown = 0, + vdecFrameRate23_97, + vdecFrameRate24, + vdecFrameRate25, + vdecFrameRate29_97, + vdecFrameRate30, + vdecFrameRate50, + vdecFrameRate59_94, + vdecFrameRate60, +}; + +/* Values for the 'aspect_ratio' field. */ +enum { + vdecAspectRatioUnknown = 0, + vdecAspectRatioSquare, + vdecAspectRatio12_11, + vdecAspectRatio10_11, + vdecAspectRatio16_11, + vdecAspectRatio40_33, + vdecAspectRatio24_11, + vdecAspectRatio20_11, + vdecAspectRatio32_11, + vdecAspectRatio80_33, + vdecAspectRatio18_11, + vdecAspectRatio15_11, + vdecAspectRatio64_33, + vdecAspectRatio160_99, + vdecAspectRatio4_3, + vdecAspectRatio16_9, + vdecAspectRatio221_1, + vdecAspectRatioOther = 255, +}; + +/* Values for the 'colour_primaries' field. */ +enum { + vdecColourPrimariesUnknown = 0, + vdecColourPrimariesBT709, + vdecColourPrimariesUnspecified, + vdecColourPrimariesReserved, + vdecColourPrimariesBT470_2M = 4, + vdecColourPrimariesBT470_2BG, + vdecColourPrimariesSMPTE170M, + vdecColourPrimariesSMPTE240M, + vdecColourPrimariesGenericFilm, +}; + +enum { + vdecRESOLUTION_CUSTOM = 0x00000000, /* custom */ + vdecRESOLUTION_480i = 0x00000001, /* 480i */ + vdecRESOLUTION_1080i = 0x00000002, /* 1080i (1920x1080, 60i) */ + vdecRESOLUTION_NTSC = 0x00000003, /* NTSC (720x483, 60i) */ + vdecRESOLUTION_480p = 0x00000004, /* 480p (720x480, 60p) */ + vdecRESOLUTION_720p = 0x00000005, /* 720p (1280x720, 60p) */ + vdecRESOLUTION_PAL1 = 0x00000006, /* PAL_1 (720x576, 50i) */ + vdecRESOLUTION_1080i25 = 0x00000007, /* 1080i25 (1920x1080, 50i) */ + vdecRESOLUTION_720p50 = 0x00000008, /* 720p50 (1280x720, 50p) */ + vdecRESOLUTION_576p = 0x00000009, /* 576p (720x576, 50p) */ + vdecRESOLUTION_1080i29_97 = 0x0000000A, /* 1080i (1920x1080, 59.94i) */ + vdecRESOLUTION_720p59_94 = 0x0000000B, /* 720p (1280x720, 59.94p) */ + vdecRESOLUTION_SD_DVD = 0x0000000C, /* SD DVD (720x483, 60i) */ + vdecRESOLUTION_480p656 = 0x0000000D, /* 480p (720x480, 60p), output bus width 8 bit, clock 74.25MHz */ + vdecRESOLUTION_1080p23_976 = 0x0000000E, /* 1080p23_976 (1920x1080, 23.976p) */ + vdecRESOLUTION_720p23_976 = 0x0000000F, /* 720p23_976 (1280x720p, 23.976p) */ + vdecRESOLUTION_240p29_97 = 0x00000010, /* 240p (1440x240, 29.97p ) */ + vdecRESOLUTION_240p30 = 0x00000011, /* 240p (1440x240, 30p) */ + vdecRESOLUTION_288p25 = 0x00000012, /* 288p (1440x288p, 25p) */ + vdecRESOLUTION_1080p29_97 = 0x00000013, /* 1080p29_97 (1920x1080, 29.97p) */ + vdecRESOLUTION_1080p30 = 0x00000014, /* 1080p30 (1920x1080, 30p) */ + vdecRESOLUTION_1080p24 = 0x00000015, /* 1080p24 (1920x1080, 24p) */ + vdecRESOLUTION_1080p25 = 0x00000016, /* 1080p25 (1920x1080, 25p) */ + vdecRESOLUTION_720p24 = 0x00000017, /* 720p24 (1280x720, 25p) */ + vdecRESOLUTION_720p29_97 = 0x00000018, /* 720p29.97 (1280x720, 29.97p) */ + vdecRESOLUTION_480p23_976 = 0x00000019, /* 480p23.976 (720*480, 23.976) */ + vdecRESOLUTION_480p29_97 = 0x0000001A, /* 480p29.976 (720*480, 29.97p) */ + vdecRESOLUTION_576p25 = 0x0000001B, /* 576p25 (720*576, 25p) */ + /* For Zero Frame Rate */ + vdecRESOLUTION_480p0 = 0x0000001C, /* 480p (720x480, 0p) */ + vdecRESOLUTION_480i0 = 0x0000001D, /* 480i (720x480, 0i) */ + vdecRESOLUTION_576p0 = 0x0000001E, /* 576p (720x576, 0p) */ + vdecRESOLUTION_720p0 = 0x0000001F, /* 720p (1280x720, 0p) */ + vdecRESOLUTION_1080p0 = 0x00000020, /* 1080p (1920x1080, 0p) */ + vdecRESOLUTION_1080i0 = 0x00000021, /* 1080i (1920x1080, 0i) */ +}; + +/* Bit definitions for 'flags' field */ +#define VDEC_FLAG_EOS (0x0004) + +#define VDEC_FLAG_FRAME (0x0000) +#define VDEC_FLAG_FIELDPAIR (0x0008) +#define VDEC_FLAG_TOPFIELD (0x0010) +#define VDEC_FLAG_BOTTOMFIELD (0x0018) + +#define VDEC_FLAG_PROGRESSIVE_SRC (0x0000) +#define VDEC_FLAG_INTERLACED_SRC (0x0020) +#define VDEC_FLAG_UNKNOWN_SRC (0x0040) + +#define VDEC_FLAG_BOTTOM_FIRST (0x0080) +#define VDEC_FLAG_LAST_PICTURE (0x0100) + +#define VDEC_FLAG_PICTURE_META_DATA_PRESENT (0x40000) + +#endif /* _WIN32 || _WIN64 */ + +enum _BC_OUTPUT_FORMAT { + MODE420 = 0x0, + MODE422_YUY2 = 0x1, + MODE422_UYVY = 0x2, +}; + +typedef struct _BC_PIC_INFO_BLOCK { + /* Common fields. */ + uint64_t timeStamp; /* Timestamp */ + uint32_t picture_number; /* Ordinal display number */ + uint32_t width; /* pixels */ + uint32_t height; /* pixels */ + uint32_t chroma_format; /* 0x420, 0x422 or 0x444 */ + uint32_t pulldown; + uint32_t flags; + uint32_t frame_rate; + uint32_t aspect_ratio; + uint32_t colour_primaries; + uint32_t picture_meta_payload; + uint32_t sess_num; + uint32_t ycom; + uint32_t custom_aspect_ratio_width_height; + uint32_t n_drop; /* number of non-reference frames remaining to be dropped */ + + /* Protocol-specific extensions. */ + union { + BC_PIB_EXT_H264 h264; + BC_PIB_EXT_MPEG mpeg; + BC_PIB_EXT_VC1 vc1; + } other; + +} BC_PIC_INFO_BLOCK, *PBC_PIC_INFO_BLOCK; + +/*------------------------------------------------------* + * ProcOut Info * + *------------------------------------------------------*/ +/* Optional flags for ProcOut Interface.*/ +enum _POUT_OPTIONAL_IN_FLAGS_{ + /* Flags from App to Device */ + BC_POUT_FLAGS_YV12 = 0x01, /* Copy Data in YV12 format */ + BC_POUT_FLAGS_STRIDE = 0x02, /* Stride size is valid. */ + BC_POUT_FLAGS_SIZE = 0x04, /* Take size information from Application */ + BC_POUT_FLAGS_INTERLACED = 0x08, /* copy only half the bytes */ + BC_POUT_FLAGS_INTERLEAVED = 0x10, /* interleaved frame */ + + /* Flags from Device to APP */ + BC_POUT_FLAGS_FMT_CHANGE = 0x10000, /* Data is not VALID when this flag is set */ + BC_POUT_FLAGS_PIB_VALID = 0x20000, /* PIB Information valid */ + BC_POUT_FLAGS_ENCRYPTED = 0x40000, /* Data is encrypted. */ + BC_POUT_FLAGS_FLD_BOT = 0x80000, /* Bottom Field data */ +}; + +#if defined(__KERNEL__) || defined(__LINUX_USER__) +typedef BC_STATUS(*dts_pout_callback)(void *shnd, uint32_t width, uint32_t height, uint32_t stride, void *pOut); +#else +typedef BC_STATUS(*dts_pout_callback)(void *shnd, uint32_t width, uint32_t height, uint32_t stride, struct _BC_DTS_PROC_OUT *pOut); +#endif + +/* Line 21 Closed Caption */ +/* User Data */ +#define MAX_UD_SIZE 1792 /* 1920 - 128 */ + +typedef struct _BC_DTS_PROC_OUT { + uint8_t *Ybuff; /* Caller Supplied buffer for Y data */ + uint32_t YbuffSz; /* Caller Supplied Y buffer size */ + uint32_t YBuffDoneSz; /* Transferred Y datasize */ + + uint8_t *UVbuff; /* Caller Supplied buffer for UV data */ + uint32_t UVbuffSz; /* Caller Supplied UV buffer size */ + uint32_t UVBuffDoneSz; /* Transferred UV data size */ + + uint32_t StrideSz; /* Caller supplied Stride Size */ + uint32_t PoutFlags; /* Call IN Flags */ + + uint32_t discCnt; /* Picture discontinuity count */ + + BC_PIC_INFO_BLOCK PicInfo; /* Picture Information Block Data */ + + /* Line 21 Closed Caption */ + /* User Data */ + uint32_t UserDataSz; + uint8_t UserData[MAX_UD_SIZE]; + + void *hnd; + dts_pout_callback AppCallBack; + uint8_t DropFrames; + uint8_t b422Mode; /* Picture output Mode */ + uint8_t bPibEnc; /* PIB encrypted */ + uint8_t bRevertScramble; + +} BC_DTS_PROC_OUT; + +typedef struct _BC_DTS_STATUS { + uint8_t ReadyListCount; /* Number of frames in ready list (reported by driver) */ + uint8_t FreeListCount; /* Number of frame buffers free. (reported by driver) */ + uint8_t PowerStateChange; /* Number of active state power transitions (reported by driver) */ + uint8_t reserved_[1]; + + uint32_t FramesDropped; /* Number of frames dropped. (reported by DIL) */ + uint32_t FramesCaptured; /* Number of frames captured. (reported by DIL) */ + uint32_t FramesRepeated; /* Number of frames repeated. (reported by DIL) */ + + uint32_t InputCount; /* Times compressed video has been sent to the HW. + * i.e. Successful DtsProcInput() calls (reported by DIL) */ + uint64_t InputTotalSize; /* Amount of compressed video that has been sent to the HW. + * (reported by DIL) */ + uint32_t InputBusyCount; /* Times compressed video has attempted to be sent to the HW + * but the input FIFO was full. (reported by DIL) */ + + uint32_t PIBMissCount; /* Amount of times a PIB is invalid. (reported by DIL) */ + + uint32_t cpbEmptySize; /* supported only for H.264, specifically changed for + * Adobe. Report size of CPB buffer available. + * Reported by DIL */ + uint64_t NextTimeStamp; /* TimeStamp of the next picture that will be returned + * by a call to ProcOutput. Added for Adobe. Reported + * back from the driver */ + uint8_t reserved__[16]; + +} BC_DTS_STATUS; + +#define BC_SWAP32(_v) \ + ((((_v) & 0xFF000000)>>24)| \ + (((_v) & 0x00FF0000)>>8)| \ + (((_v) & 0x0000FF00)<<8)| \ + (((_v) & 0x000000FF)<<24)) + +#define WM_AGENT_TRAYICON_DECODER_OPEN 10001 +#define WM_AGENT_TRAYICON_DECODER_CLOSE 10002 +#define WM_AGENT_TRAYICON_DECODER_START 10003 +#define WM_AGENT_TRAYICON_DECODER_STOP 10004 +#define WM_AGENT_TRAYICON_DECODER_RUN 10005 +#define WM_AGENT_TRAYICON_DECODER_PAUSE 10006 + + +#endif /* _BC_DTS_DEFS_H_ */ diff --git a/drivers/staging/crystalhd/bc_dts_glob_lnx.h b/drivers/staging/crystalhd/bc_dts_glob_lnx.h new file mode 100644 index 000000000000..b3125e3e0372 --- /dev/null +++ b/drivers/staging/crystalhd/bc_dts_glob_lnx.h @@ -0,0 +1,299 @@ +/******************************************************************** + * Copyright(c) 2006-2009 Broadcom Corporation. + * + * Name: bc_dts_glob_lnx.h + * + * Description: Wrapper to Windows dts_glob.h for Link-Linux usage. + * The idea is to define additional Linux related defs + * in this file to avoid changes to existing Windows + * glob file. + * + * AU + * + * HISTORY: + * + ******************************************************************** + * This header is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation, either version 2.1 of the License. + * + * This header is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * You should have received a copy of the GNU Lesser General Public License + * along with this header. If not, see . + *******************************************************************/ + +#ifndef _BC_DTS_GLOB_LNX_H_ +#define _BC_DTS_GLOB_LNX_H_ + +#ifdef __LINUX_USER__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRVIFLIB_INT_API + +#endif + +#include "bc_dts_defs.h" +#include "bcm_70012_regs.h" /* Link Register defs */ + +#define CRYSTALHD_API_NAME "crystalhd" +#define CRYSTALHD_API_DEV_NAME "/dev/crystalhd" + +/* + * These are SW stack tunable parameters shared + * between the driver and the application. + */ +enum _BC_DTS_GLOBALS { + BC_MAX_FW_CMD_BUFF_SZ = 0x40, /* FW passthrough cmd/rsp buffer size */ + PCI_CFG_SIZE = 256, /* PCI config size buffer */ + BC_IOCTL_DATA_POOL_SIZE = 8, /* BC_IOCTL_DATA Pool size */ + BC_LINK_MAX_OPENS = 3, /* Maximum simultaneous opens*/ + BC_LINK_MAX_SGLS = 1024, /* Maximum SG elements 4M/4K */ + BC_TX_LIST_CNT = 2, /* Max Tx DMA Rings */ + BC_RX_LIST_CNT = 8, /* Max Rx DMA Rings*/ + BC_PROC_OUTPUT_TIMEOUT = 3000, /* Milliseconds */ + BC_INFIFO_THRESHOLD = 0x10000, +}; + +typedef struct _BC_CMD_REG_ACC { + uint32_t Offset; + uint32_t Value; +} BC_CMD_REG_ACC; + +typedef struct _BC_CMD_DEV_MEM { + uint32_t StartOff; + uint32_t NumDwords; + uint32_t Rsrd; +} BC_CMD_DEV_MEM; + +/* FW Passthrough command structure */ +enum _bc_fw_cmd_flags { + BC_FW_CMD_FLAGS_NONE = 0, + BC_FW_CMD_PIB_QS = 0x01, +}; + +typedef struct _BC_FW_CMD { + uint32_t cmd[BC_MAX_FW_CMD_BUFF_SZ]; + uint32_t rsp[BC_MAX_FW_CMD_BUFF_SZ]; + uint32_t flags; + uint32_t add_data; +} BC_FW_CMD, *PBC_FW_CMD; + +typedef struct _BC_HW_TYPE { + uint16_t PciDevId; + uint16_t PciVenId; + uint8_t HwRev; + uint8_t Align[3]; +} BC_HW_TYPE; + +typedef struct _BC_PCI_CFG { + uint32_t Size; + uint32_t Offset; + uint8_t pci_cfg_space[PCI_CFG_SIZE]; +} BC_PCI_CFG; + +typedef struct _BC_VERSION_INFO_ { + uint8_t DriverMajor; + uint8_t DriverMinor; + uint16_t DriverRevision; +} BC_VERSION_INFO; + +typedef struct _BC_START_RX_CAP_ { + uint32_t Rsrd; + uint32_t StartDeliveryThsh; + uint32_t PauseThsh; + uint32_t ResumeThsh; +} BC_START_RX_CAP; + +typedef struct _BC_FLUSH_RX_CAP_ { + uint32_t Rsrd; + uint32_t bDiscardOnly; +} BC_FLUSH_RX_CAP; + +typedef struct _BC_DTS_STATS { + uint8_t drvRLL; + uint8_t drvFLL; + uint8_t eosDetected; + uint8_t pwr_state_change; + + /* Stats from App */ + uint32_t opFrameDropped; + uint32_t opFrameCaptured; + uint32_t ipSampleCnt; + uint64_t ipTotalSize; + uint32_t reptdFrames; + uint32_t pauseCount; + uint32_t pibMisses; + uint32_t discCounter; + + /* Stats from Driver */ + uint32_t TxFifoBsyCnt; + uint32_t intCount; + uint32_t DrvIgnIntrCnt; + uint32_t DrvTotalFrmDropped; + uint32_t DrvTotalHWErrs; + uint32_t DrvTotalPIBFlushCnt; + uint32_t DrvTotalFrmCaptured; + uint32_t DrvPIBMisses; + uint32_t DrvPauseTime; + uint32_t DrvRepeatedFrms; + uint32_t res1[13]; + +} BC_DTS_STATS; + +typedef struct _BC_PROC_INPUT_ { + uint8_t *pDmaBuff; + uint32_t BuffSz; + uint8_t Mapped; + uint8_t Encrypted; + uint8_t Rsrd[2]; + uint32_t DramOffset; /* For debug use only */ +} BC_PROC_INPUT, *PBC_PROC_INPUT; + +typedef struct _BC_DEC_YUV_BUFFS { + uint32_t b422Mode; + uint8_t *YuvBuff; + uint32_t YuvBuffSz; + uint32_t UVbuffOffset; + uint32_t YBuffDoneSz; + uint32_t UVBuffDoneSz; + uint32_t RefCnt; +} BC_DEC_YUV_BUFFS; + +enum _DECOUT_COMPLETION_FLAGS{ + COMP_FLAG_NO_INFO = 0x00, + COMP_FLAG_FMT_CHANGE = 0x01, + COMP_FLAG_PIB_VALID = 0x02, + COMP_FLAG_DATA_VALID = 0x04, + COMP_FLAG_DATA_ENC = 0x08, + COMP_FLAG_DATA_BOT = 0x10, +}; + +typedef struct _BC_DEC_OUT_BUFF{ + BC_DEC_YUV_BUFFS OutPutBuffs; + BC_PIC_INFO_BLOCK PibInfo; + uint32_t Flags; + uint32_t BadFrCnt; +} BC_DEC_OUT_BUFF; + +typedef struct _BC_NOTIFY_MODE { + uint32_t Mode; + uint32_t Rsvr[3]; +} BC_NOTIFY_MODE; + +typedef struct _BC_CLOCK { + uint32_t clk; + uint32_t Rsvr[3]; +} BC_CLOCK; + +typedef struct _BC_IOCTL_DATA { + BC_STATUS RetSts; + uint32_t IoctlDataSz; + uint32_t Timeout; + union { + BC_CMD_REG_ACC regAcc; + BC_CMD_DEV_MEM devMem; + BC_FW_CMD fwCmd; + BC_HW_TYPE hwType; + BC_PCI_CFG pciCfg; + BC_VERSION_INFO VerInfo; + BC_PROC_INPUT ProcInput; + BC_DEC_YUV_BUFFS RxBuffs; + BC_DEC_OUT_BUFF DecOutData; + BC_START_RX_CAP RxCap; + BC_FLUSH_RX_CAP FlushRxCap; + BC_DTS_STATS drvStat; + BC_NOTIFY_MODE NotifyMode; + BC_CLOCK clockValue; + } u; + struct _BC_IOCTL_DATA *next; +} BC_IOCTL_DATA; + +typedef enum _BC_DRV_CMD{ + DRV_CMD_VERSION = 0, /* Get SW version */ + DRV_CMD_GET_HWTYPE, /* Get HW version and type Dozer/Tank */ + DRV_CMD_REG_RD, /* Read Device Register */ + DRV_CMD_REG_WR, /* Write Device Register */ + DRV_CMD_FPGA_RD, /* Read FPGA Register */ + DRV_CMD_FPGA_WR, /* Wrtie FPGA Reister */ + DRV_CMD_MEM_RD, /* Read Device Memory */ + DRV_CMD_MEM_WR, /* Write Device Memory */ + DRV_CMD_RD_PCI_CFG, /* Read PCI Config Space */ + DRV_CMD_WR_PCI_CFG, /* Write the PCI Configuration Space*/ + DRV_CMD_FW_DOWNLOAD, /* Download Firmware */ + DRV_ISSUE_FW_CMD, /* Issue FW Cmd (pass through mode) */ + DRV_CMD_PROC_INPUT, /* Process Input Sample */ + DRV_CMD_ADD_RXBUFFS, /* Add Rx side buffers to driver pool */ + DRV_CMD_FETCH_RXBUFF, /* Get Rx DMAed buffer */ + DRV_CMD_START_RX_CAP, /* Start Rx Buffer Capture */ + DRV_CMD_FLUSH_RX_CAP, /* Stop the capture for now...we will enhance this later*/ + DRV_CMD_GET_DRV_STAT, /* Get Driver Internal Statistics */ + DRV_CMD_RST_DRV_STAT, /* Reset Driver Internal Statistics */ + DRV_CMD_NOTIFY_MODE, /* Notify the Mode to driver in which the application is Operating*/ + DRV_CMD_CHANGE_CLOCK, /* Change the core clock to either save power or improve performance */ + + /* MUST be the last one.. */ + DRV_CMD_END, /* End of the List.. */ +} BC_DRV_CMD; + +#define BC_IOC_BASE 'b' +#define BC_IOC_VOID _IOC_NONE +#define BC_IOC_IOWR(nr, type) _IOWR(BC_IOC_BASE, nr, type) +#define BC_IOCTL_MB BC_IOCTL_DATA + +#define BCM_IOC_GET_VERSION BC_IOC_IOWR(DRV_CMD_VERSION, BC_IOCTL_MB) +#define BCM_IOC_GET_HWTYPE BC_IOC_IOWR(DRV_CMD_GET_HWTYPE, BC_IOCTL_MB) +#define BCM_IOC_REG_RD BC_IOC_IOWR(DRV_CMD_REG_RD, BC_IOCTL_MB) +#define BCM_IOC_REG_WR BC_IOC_IOWR(DRV_CMD_REG_WR, BC_IOCTL_MB) +#define BCM_IOC_MEM_RD BC_IOC_IOWR(DRV_CMD_MEM_RD, BC_IOCTL_MB) +#define BCM_IOC_MEM_WR BC_IOC_IOWR(DRV_CMD_MEM_WR, BC_IOCTL_MB) +#define BCM_IOC_FPGA_RD BC_IOC_IOWR(DRV_CMD_FPGA_RD, BC_IOCTL_MB) +#define BCM_IOC_FPGA_WR BC_IOC_IOWR(DRV_CMD_FPGA_WR, BC_IOCTL_MB) +#define BCM_IOC_RD_PCI_CFG BC_IOC_IOWR(DRV_CMD_RD_PCI_CFG, BC_IOCTL_MB) +#define BCM_IOC_WR_PCI_CFG BC_IOC_IOWR(DRV_CMD_WR_PCI_CFG, BC_IOCTL_MB) +#define BCM_IOC_PROC_INPUT BC_IOC_IOWR(DRV_CMD_PROC_INPUT, BC_IOCTL_MB) +#define BCM_IOC_ADD_RXBUFFS BC_IOC_IOWR(DRV_CMD_ADD_RXBUFFS, BC_IOCTL_MB) +#define BCM_IOC_FETCH_RXBUFF BC_IOC_IOWR(DRV_CMD_FETCH_RXBUFF, BC_IOCTL_MB) +#define BCM_IOC_FW_CMD BC_IOC_IOWR(DRV_ISSUE_FW_CMD, BC_IOCTL_MB) +#define BCM_IOC_START_RX_CAP BC_IOC_IOWR(DRV_CMD_START_RX_CAP, BC_IOCTL_MB) +#define BCM_IOC_FLUSH_RX_CAP BC_IOC_IOWR(DRV_CMD_FLUSH_RX_CAP, BC_IOCTL_MB) +#define BCM_IOC_GET_DRV_STAT BC_IOC_IOWR(DRV_CMD_GET_DRV_STAT, BC_IOCTL_MB) +#define BCM_IOC_RST_DRV_STAT BC_IOC_IOWR(DRV_CMD_RST_DRV_STAT, BC_IOCTL_MB) +#define BCM_IOC_NOTIFY_MODE BC_IOC_IOWR(DRV_CMD_NOTIFY_MODE, BC_IOCTL_MB) +#define BCM_IOC_FW_DOWNLOAD BC_IOC_IOWR(DRV_CMD_FW_DOWNLOAD, BC_IOCTL_MB) +#define BCM_IOC_CHG_CLK BC_IOC_IOWR(DRV_CMD_CHANGE_CLOCK, BC_IOCTL_MB) +#define BCM_IOC_END BC_IOC_VOID + +/* Wrapper for main IOCTL data */ +typedef struct _crystalhd_ioctl_data { + BC_IOCTL_DATA udata; /* IOCTL from App..*/ + uint32_t u_id; /* Driver specific user ID */ + uint32_t cmd; /* Cmd ID for driver's use. */ + void *add_cdata; /* Additional command specific data..*/ + uint32_t add_cdata_sz; /* Additional command specific data size */ + struct _crystalhd_ioctl_data *next; /* List/Fifo management */ +} crystalhd_ioctl_data; + + +enum _crystalhd_kmod_ver{ + crystalhd_kmod_major = 0, + crystalhd_kmod_minor = 9, + crystalhd_kmod_rev = 27, +}; + +#endif diff --git a/drivers/staging/crystalhd/bc_dts_types.h b/drivers/staging/crystalhd/bc_dts_types.h new file mode 100644 index 000000000000..e073d7450c16 --- /dev/null +++ b/drivers/staging/crystalhd/bc_dts_types.h @@ -0,0 +1,115 @@ +/******************************************************************** + * Copyright(c) 2006-2009 Broadcom Corporation. + * + * Name: bc_dts_types.h + * + * Description: Data types + * + * AU + * + * HISTORY: + * + ******************************************************************** + * This header is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation, either version 2.1 of the License. + * + * This header is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * You should have received a copy of the GNU Lesser General Public License + * along with this header. If not, see . + *******************************************************************/ + +#ifndef _BC_DTS_TYPES_H_ +#define _BC_DTS_TYPES_H_ + +#if defined(_WIN64) || defined(_WIN32) +typedef uint32_t U32; +typedef int32_t S32; +typedef uint16_t U16; +typedef int16_t S16; +typedef unsigned char U8; +typedef char S8; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif + +#ifndef BOOL +typedef int BOOL; +#endif + +#ifdef WIN32 + typedef unsigned __int64 U64; +#elif defined(_WIN64) + typedef uint64_t U64; +#endif + +#ifdef _WIN64 +#if !(defined(POINTER_32)) +#define POINTER_32 __ptr32 +#endif +#else /* _WIN32 */ +#define POINTER_32 +#endif + +#if defined(__KERNEL__) || defined(__LINUX_USER__) + +#ifdef __LINUX_USER__ /* Don't include these for KERNEL */ +typedef uint32_t ULONG; +typedef int32_t LONG; +typedef void *HANDLE; +typedef void VOID; +typedef void *LPVOID; +typedef uint32_t DWORD; +typedef uint32_t UINT32; +typedef uint32_t *LPDWORD; +typedef unsigned char *PUCHAR; + +#ifndef TRUE + #define TRUE 1 +#endif + +#ifndef FALSE + #define FALSE 0 +#endif + +#define TEXT + +#else + +/* For Kernel usage.. */ +typedef bool bc_bool_t; +#endif + +#else + +#ifndef uint64_t +typedef struct _uint64_t { + uint32_t low_dw; + uint32_t hi_dw; +} uint64_t; +#endif + +#ifndef int32_t +typedef signed long int32_t; +#endif + +#ifndef uint32_t +typedef unsigned long uint32_t; +#endif + +#ifndef uint16_t +typedef unsigned short uint16_t; +#endif + +#ifndef uint8_t +typedef unsigned char uint8_t; +#endif +#endif + +#endif + diff --git a/drivers/staging/crystalhd/bcm_70012_regs.h b/drivers/staging/crystalhd/bcm_70012_regs.h new file mode 100644 index 000000000000..b3b255769641 --- /dev/null +++ b/drivers/staging/crystalhd/bcm_70012_regs.h @@ -0,0 +1,12299 @@ +/*************************************************************************** + * Copyright (c) 1999-2009, Broadcom Corporation. + * + * Name: bcm_70012_regs.h + * + * Description: BCM70012 registers + * + ******************************************************************** + * This header is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation, either version 2.1 of the License. + * + * This header is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * You should have received a copy of the GNU Lesser General Public License + * along with this header. If not, see . + ***************************************************************************/ + +#ifndef MACFILE_H__ +#define MACFILE_H__ + +/** + * m = memory, c = core, r = register, f = field, d = data. + */ +#if !defined(GET_FIELD) && !defined(SET_FIELD) +#define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN +#define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS +#define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK +#define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT + +#define GET_FIELD(m,c,r,f) \ + ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) + +#define SET_FIELD(m,c,r,f,d) \ + ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ + BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ + ) + +#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) +#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) +#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) + +#endif /* GET & SET */ + +/**************************************************************************** + * Core Enums. + ***************************************************************************/ +/**************************************************************************** + * Enums: AES_RGR_BRIDGE_RESET_CTRL + ***************************************************************************/ +#define AES_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 +#define AES_RGR_BRIDGE_RESET_CTRL_ASSERT 1 + +/**************************************************************************** + * Enums: CCE_RGR_BRIDGE_RESET_CTRL + ***************************************************************************/ +#define CCE_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 +#define CCE_RGR_BRIDGE_RESET_CTRL_ASSERT 1 + +/**************************************************************************** + * Enums: DBU_RGR_BRIDGE_RESET_CTRL + ***************************************************************************/ +#define DBU_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 +#define DBU_RGR_BRIDGE_RESET_CTRL_ASSERT 1 + +/**************************************************************************** + * Enums: DCI_RGR_BRIDGE_RESET_CTRL + ***************************************************************************/ +#define DCI_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 +#define DCI_RGR_BRIDGE_RESET_CTRL_ASSERT 1 + +/**************************************************************************** + * Enums: GISB_ARBITER_DEASSERT_ASSERT + ***************************************************************************/ +#define GISB_ARBITER_DEASSERT_ASSERT_DEASSERT 0 +#define GISB_ARBITER_DEASSERT_ASSERT_ASSERT 1 + +/**************************************************************************** + * Enums: GISB_ARBITER_UNMASK_MASK + ***************************************************************************/ +#define GISB_ARBITER_UNMASK_MASK_UNMASK 0 +#define GISB_ARBITER_UNMASK_MASK_MASK 1 + +/**************************************************************************** + * Enums: GISB_ARBITER_DISABLE_ENABLE + ***************************************************************************/ +#define GISB_ARBITER_DISABLE_ENABLE_DISABLE 0 +#define GISB_ARBITER_DISABLE_ENABLE_ENABLE 1 + +/**************************************************************************** + * Enums: I2C_GR_BRIDGE_RESET_CTRL + ***************************************************************************/ +#define I2C_GR_BRIDGE_RESET_CTRL_DEASSERT 0 +#define I2C_GR_BRIDGE_RESET_CTRL_ASSERT 1 + +/**************************************************************************** + * Enums: MISC_GR_BRIDGE_RESET_CTRL + ***************************************************************************/ +#define MISC_GR_BRIDGE_RESET_CTRL_DEASSERT 0 +#define MISC_GR_BRIDGE_RESET_CTRL_ASSERT 1 + +/**************************************************************************** + * Enums: OTP_GR_BRIDGE_RESET_CTRL + ***************************************************************************/ +#define OTP_GR_BRIDGE_RESET_CTRL_DEASSERT 0 +#define OTP_GR_BRIDGE_RESET_CTRL_ASSERT 1 + +/**************************************************************************** + * BCM70012_TGT_TOP_PCIE_CFG + ***************************************************************************/ +#define PCIE_CFG_DEVICE_VENDOR_ID 0x00000000 /* DEVICE_VENDOR_ID Register */ +#define PCIE_CFG_STATUS_COMMAND 0x00000004 /* STATUS_COMMAND Register */ +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID 0x00000008 /* PCI_CLASSCODE_AND_REVISION_ID Register */ +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE 0x0000000c /* BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE Register */ +#define PCIE_CFG_BASE_ADDRESS_1 0x00000010 /* BASE_ADDRESS_1 Register */ +#define PCIE_CFG_BASE_ADDRESS_2 0x00000014 /* BASE_ADDRESS_2 Register */ +#define PCIE_CFG_BASE_ADDRESS_3 0x00000018 /* BASE_ADDRESS_3 Register */ +#define PCIE_CFG_BASE_ADDRESS_4 0x0000001c /* BASE_ADDRESS_4 Register */ +#define PCIE_CFG_CARDBUS_CIS_POINTER 0x00000028 /* CARDBUS_CIS_POINTER Register */ +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID 0x0000002c /* SUBSYSTEM_DEVICE_VENDOR_ID Register */ +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS 0x00000030 /* EXPANSION_ROM_BASE_ADDRESS Register */ +#define PCIE_CFG_CAPABILITIES_POINTER 0x00000034 /* CAPABILITIES_POINTER Register */ +#define PCIE_CFG_INTERRUPT 0x0000003c /* INTERRUPT Register */ +#define PCIE_CFG_VPD_CAPABILITIES 0x00000040 /* VPD_CAPABILITIES Register */ +#define PCIE_CFG_VPD_DATA 0x00000044 /* VPD_DATA Register */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY 0x00000048 /* POWER_MANAGEMENT_CAPABILITY Register */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS 0x0000004c /* POWER_MANAGEMENT_CONTROL_STATUS Register */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER 0x00000050 /* MSI_CAPABILITY_HEADER Register */ +#define PCIE_CFG_MSI_LOWER_ADDRESS 0x00000054 /* MSI_LOWER_ADDRESS Register */ +#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER 0x00000058 /* MSI_UPPER_ADDRESS_REGISTER Register */ +#define PCIE_CFG_MSI_DATA 0x0000005c /* MSI_DATA Register */ +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER 0x00000060 /* BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER Register */ +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES 0x00000064 /* RESET_COUNTERS_INITIAL_VALUES Register */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL 0x00000068 /* MISCELLANEOUS_HOST_CONTROL Register */ +#define PCIE_CFG_SPARE 0x0000006c /* SPARE Register */ +#define PCIE_CFG_PCI_STATE 0x00000070 /* PCI_STATE Register */ +#define PCIE_CFG_CLOCK_CONTROL 0x00000074 /* CLOCK_CONTROL Register */ +#define PCIE_CFG_REGISTER_BASE 0x00000078 /* REGISTER_BASE Register */ +#define PCIE_CFG_MEMORY_BASE 0x0000007c /* MEMORY_BASE Register */ +#define PCIE_CFG_REGISTER_DATA 0x00000080 /* REGISTER_DATA Register */ +#define PCIE_CFG_MEMORY_DATA 0x00000084 /* MEMORY_DATA Register */ +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE 0x00000088 /* EXPANSION_ROM_BAR_SIZE Register */ +#define PCIE_CFG_EXPANSION_ROM_ADDRESS 0x0000008c /* EXPANSION_ROM_ADDRESS Register */ +#define PCIE_CFG_EXPANSION_ROM_DATA 0x00000090 /* EXPANSION_ROM_DATA Register */ +#define PCIE_CFG_VPD_INTERFACE 0x00000094 /* VPD_INTERFACE Register */ +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER 0x00000098 /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER Register */ +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER 0x0000009c /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER Register */ +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER 0x000000a0 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER Register */ +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER 0x000000a4 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER Register */ +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER 0x000000a8 /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER Register */ +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER 0x000000ac /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER Register */ +#define PCIE_CFG_INT_MAILBOX_UPPER 0x000000b0 /* INT_MAILBOX_UPPER Register */ +#define PCIE_CFG_INT_MAILBOX_LOWER 0x000000b4 /* INT_MAILBOX_LOWER Register */ +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION 0x000000bc /* PRODUCT_ID_AND_ASIC_REVISION Register */ +#define PCIE_CFG_FUNCTION_EVENT 0x000000c0 /* FUNCTION_EVENT Register */ +#define PCIE_CFG_FUNCTION_EVENT_MASK 0x000000c4 /* FUNCTION_EVENT_MASK Register */ +#define PCIE_CFG_FUNCTION_PRESENT 0x000000c8 /* FUNCTION_PRESENT Register */ +#define PCIE_CFG_PCIE_CAPABILITIES 0x000000cc /* PCIE_CAPABILITIES Register */ +#define PCIE_CFG_DEVICE_CAPABILITIES 0x000000d0 /* DEVICE_CAPABILITIES Register */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL 0x000000d4 /* DEVICE_STATUS_CONTROL Register */ +#define PCIE_CFG_LINK_CAPABILITY 0x000000d8 /* LINK_CAPABILITY Register */ +#define PCIE_CFG_LINK_STATUS_CONTROL 0x000000dc /* LINK_STATUS_CONTROL Register */ +#define PCIE_CFG_DEVICE_CAPABILITIES_2 0x000000f0 /* DEVICE_CAPABILITIES_2 Register */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2 0x000000f4 /* DEVICE_STATUS_CONTROL_2 Register */ +#define PCIE_CFG_LINK_CAPABILITIES_2 0x000000f8 /* LINK_CAPABILITIES_2 Register */ +#define PCIE_CFG_LINK_STATUS_CONTROL_2 0x000000fc /* LINK_STATUS_CONTROL_2 Register */ +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER 0x00000100 /* ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER Register */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS 0x00000104 /* UNCORRECTABLE_ERROR_STATUS Register */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK 0x00000108 /* UNCORRECTABLE_ERROR_MASK Register */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY 0x0000010c /* UNCORRECTABLE_ERROR_SEVERITY Register */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS 0x00000110 /* CORRECTABLE_ERROR_STATUS Register */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK 0x00000114 /* CORRECTABLE_ERROR_MASK Register */ +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL 0x00000118 /* ADVANCED_ERROR_CAPABILITIES_AND_CONTROL Register */ +#define PCIE_CFG_HEADER_LOG_1 0x0000011c /* HEADER_LOG_1 Register */ +#define PCIE_CFG_HEADER_LOG_2 0x00000120 /* HEADER_LOG_2 Register */ +#define PCIE_CFG_HEADER_LOG_3 0x00000124 /* HEADER_LOG_3 Register */ +#define PCIE_CFG_HEADER_LOG_4 0x00000128 /* HEADER_LOG_4 Register */ +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER 0x0000013c /* VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER Register */ +#define PCIE_CFG_PORT_VC_CAPABILITY 0x00000140 /* PORT_VC_CAPABILITY Register */ +#define PCIE_CFG_PORT_VC_CAPABILITY_2 0x00000144 /* PORT_VC_CAPABILITY_2 Register */ +#define PCIE_CFG_PORT_VC_STATUS_CONTROL 0x00000148 /* PORT_VC_STATUS_CONTROL Register */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY 0x0000014c /* VC_RESOURCE_CAPABILITY Register */ +#define PCIE_CFG_VC_RESOURCE_CONTROL 0x00000150 /* VC_RESOURCE_CONTROL Register */ +#define PCIE_CFG_VC_RESOURCE_STATUS 0x00000154 /* VC_RESOURCE_STATUS Register */ +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER 0x00000160 /* DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER Register */ +#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW 0x00000164 /* DEVICE_SERIAL_NO_LOWER_DW Register */ +#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW 0x00000168 /* DEVICE_SERIAL_NO_UPPER_DW Register */ +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER 0x0000016c /* POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER Register */ +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT 0x00000170 /* POWER_BUDGETING_DATA_SELECT Register */ +#define PCIE_CFG_POWER_BUDGETING_DATA 0x00000174 /* POWER_BUDGETING_DATA Register */ +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY 0x00000178 /* POWER_BUDGETING_CAPABILITY Register */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1 0x0000017c /* FIRMWARE_POWER_BUDGETING_2_1 Register */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3 0x00000180 /* FIRMWARE_POWER_BUDGETING_4_3 Register */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5 0x00000184 /* FIRMWARE_POWER_BUDGETING_6_5 Register */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7 0x00000188 /* FIRMWARE_POWER_BUDGETING_8_7 Register */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING 0x0000018c /* PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING Register */ + + +/**************************************************************************** + * BCM70012_TGT_TOP_PCIE_TL + ***************************************************************************/ +#define PCIE_TL_TL_CONTROL 0x00000400 /* TL_CONTROL Register */ +#define PCIE_TL_TRANSACTION_CONFIGURATION 0x00000404 /* TRANSACTION_CONFIGURATION Register */ +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00000408 /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 0x0000040c /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 Register */ +#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00000410 /* DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ +#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 0x00000414 /* DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 Register */ +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC 0x00000418 /* DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC Register */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC 0x0000041c /* DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC Register */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC 0x00000420 /* READ_DMA_SPLIT_IDS_DIAGNOSTIC Register */ +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC 0x00000424 /* READ_DMA_SPLIT_LENGTH_DIAGNOSTIC Register */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC 0x0000043c /* XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC Register */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC 0x00000458 /* DMA_COMPLETION_MISC__DIAGNOSTIC Register */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC 0x0000045c /* SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC Register */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC 0x00000460 /* SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC Register */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC 0x00000464 /* SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC Register */ +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO 0x00000468 /* TL_BUS_NO_DEV__NO__FUNC__NO Register */ +#define PCIE_TL_TL_DEBUG 0x0000046c /* TL_DEBUG Register */ + + +/**************************************************************************** + * BCM70012_TGT_TOP_PCIE_DLL + ***************************************************************************/ +#define PCIE_DLL_DATA_LINK_CONTROL 0x00000500 /* DATA_LINK_CONTROL Register */ +#define PCIE_DLL_DATA_LINK_STATUS 0x00000504 /* DATA_LINK_STATUS Register */ +#define PCIE_DLL_DATA_LINK_ATTENTION 0x00000508 /* DATA_LINK_ATTENTION Register */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK 0x0000050c /* DATA_LINK_ATTENTION_MASK Register */ +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000510 /* NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000514 /* ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000518 /* PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG 0x0000051c /* RECEIVE_SEQUENCE_NUMBER_DEBUG Register */ +#define PCIE_DLL_DATA_LINK_REPLAY 0x00000520 /* DATA_LINK_REPLAY Register */ +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT 0x00000524 /* DATA_LINK_ACK_TIMEOUT Register */ +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD 0x00000528 /* POWER_MANAGEMENT_THRESHOLD Register */ +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG 0x0000052c /* RETRY_BUFFER_WRITE_POINTER_DEBUG Register */ +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG 0x00000530 /* RETRY_BUFFER_READ_POINTER_DEBUG Register */ +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG 0x00000534 /* RETRY_BUFFER_PURGED_POINTER_DEBUG Register */ +#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT 0x00000538 /* RETRY_BUFFER_READ_WRITE_DEBUG_PORT Register */ +#define PCIE_DLL_ERROR_COUNT_THRESHOLD 0x0000053c /* ERROR_COUNT_THRESHOLD Register */ +#define PCIE_DLL_TL_ERROR_COUNTER 0x00000540 /* TL_ERROR_COUNTER Register */ +#define PCIE_DLL_DLLP_ERROR_COUNTER 0x00000544 /* DLLP_ERROR_COUNTER Register */ +#define PCIE_DLL_NAK_RECEIVED_COUNTER 0x00000548 /* NAK_RECEIVED_COUNTER Register */ +#define PCIE_DLL_DATA_LINK_TEST 0x0000054c /* DATA_LINK_TEST Register */ +#define PCIE_DLL_PACKET_BIST 0x00000550 /* PACKET_BIST Register */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL 0x00000554 /* LINK_PCIE_1_1_CONTROL Register */ + + +/**************************************************************************** + * BCM70012_TGT_TOP_PCIE_PHY + ***************************************************************************/ +#define PCIE_PHY_PHY_MODE 0x00000600 /* TYPE_PHY_MODE Register */ +#define PCIE_PHY_PHY_LINK_STATUS 0x00000604 /* TYPE_PHY_LINK_STATUS Register */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL 0x00000608 /* TYPE_PHY_LINK_LTSSM_CONTROL Register */ +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER 0x0000060c /* TYPE_PHY_LINK_TRAINING_LINK_NUMBER Register */ +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER 0x00000610 /* TYPE_PHY_LINK_TRAINING_LANE_NUMBER Register */ +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS 0x00000614 /* TYPE_PHY_LINK_TRAINING_N_FTS Register */ +#define PCIE_PHY_PHY_ATTENTION 0x00000618 /* TYPE_PHY_ATTENTION Register */ +#define PCIE_PHY_PHY_ATTENTION_MASK 0x0000061c /* TYPE_PHY_ATTENTION_MASK Register */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER 0x00000620 /* TYPE_PHY_RECEIVE_ERROR_COUNTER Register */ +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER 0x00000624 /* TYPE_PHY_RECEIVE_FRAMING_ERROR_COUNTER Register */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD 0x00000628 /* TYPE_PHY_RECEIVE_ERROR_THRESHOLD Register */ +#define PCIE_PHY_PHY_TEST_CONTROL 0x0000062c /* TYPE_PHY_TEST_CONTROL Register */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE 0x00000630 /* TYPE_PHY_SERDES_CONTROL_OVERRIDE Register */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE 0x00000634 /* TYPE_PHY_TIMING_PARAMETER_OVERRIDE Register */ +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES 0x00000638 /* TYPE_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES Register */ +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES 0x0000063c /* TYPE_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES Register */ + + +/**************************************************************************** + * BCM70012_TGT_TOP_INTR + ***************************************************************************/ +#define INTR_INTR_STATUS 0x00000700 /* Interrupt Status Register */ +#define INTR_INTR_SET 0x00000704 /* Interrupt Set Register */ +#define INTR_INTR_CLR_REG 0x00000708 /* Interrupt Clear Register */ +#define INTR_INTR_MSK_STS_REG 0x0000070c /* Interrupt Mask Status Register */ +#define INTR_INTR_MSK_SET_REG 0x00000710 /* Interrupt Mask Set Register */ +#define INTR_INTR_MSK_CLR_REG 0x00000714 /* Interrupt Mask Clear Register */ +#define INTR_EOI_CTRL 0x00000720 /* End of interrupt control register */ + + +/**************************************************************************** + * BCM70012_TGT_TOP_MDIO + ***************************************************************************/ +#define MDIO_CTRL0 0x00000730 /* PCIE Serdes MDIO Control Register 0 */ +#define MDIO_CTRL1 0x00000734 /* PCIE Serdes MDIO Control Register 1 */ +#define MDIO_CTRL2 0x00000738 /* PCIE Serdes MDIO Control Register 2 */ + + +/**************************************************************************** + * BCM70012_TGT_TOP_TGT_RGR_BRIDGE + ***************************************************************************/ +#define TGT_RGR_BRIDGE_REVISION 0x00000740 /* PCIE RGR Bridge Revision Register */ +#define TGT_RGR_BRIDGE_CTRL 0x00000744 /* RGR Bridge Control Register */ +#define TGT_RGR_BRIDGE_RBUS_TIMER 0x00000748 /* RGR Bridge RBUS Timer Register */ +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0 0x0000074c /* RGR Bridge Spare Software Reset 0 Register */ +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1 0x00000750 /* RGR Bridge Spare Software Reset 1 Register */ + + +/**************************************************************************** + * BCM70012_I2C_TOP_I2C + ***************************************************************************/ +#define I2C_CHIP_ADDRESS 0x00000800 /* I2C Chip Address And Read/Write Control */ +#define I2C_DATA_IN0 0x00000804 /* I2C Write Data Byte 0 */ +#define I2C_DATA_IN1 0x00000808 /* I2C Write Data Byte 1 */ +#define I2C_DATA_IN2 0x0000080c /* I2C Write Data Byte 2 */ +#define I2C_DATA_IN3 0x00000810 /* I2C Write Data Byte 3 */ +#define I2C_DATA_IN4 0x00000814 /* I2C Write Data Byte 4 */ +#define I2C_DATA_IN5 0x00000818 /* I2C Write Data Byte 5 */ +#define I2C_DATA_IN6 0x0000081c /* I2C Write Data Byte 6 */ +#define I2C_DATA_IN7 0x00000820 /* I2C Write Data Byte 7 */ +#define I2C_CNT_REG 0x00000824 /* I2C Transfer Count Register */ +#define I2C_CTL_REG 0x00000828 /* I2C Control Register */ +#define I2C_IIC_ENABLE 0x0000082c /* I2C Read/Write Enable And Interrupt */ +#define I2C_DATA_OUT0 0x00000830 /* I2C Read Data Byte 0 */ +#define I2C_DATA_OUT1 0x00000834 /* I2C Read Data Byte 1 */ +#define I2C_DATA_OUT2 0x00000838 /* I2C Read Data Byte 2 */ +#define I2C_DATA_OUT3 0x0000083c /* I2C Read Data Byte 3 */ +#define I2C_DATA_OUT4 0x00000840 /* I2C Read Data Byte 4 */ +#define I2C_DATA_OUT5 0x00000844 /* I2C Read Data Byte 5 */ +#define I2C_DATA_OUT6 0x00000848 /* I2C Read Data Byte 6 */ +#define I2C_DATA_OUT7 0x0000084c /* I2C Read Data Byte 7 */ +#define I2C_CTLHI_REG 0x00000850 /* I2C Control Register */ +#define I2C_SCL_PARAM 0x00000854 /* I2C SCL Parameter Register */ + + +/**************************************************************************** + * BCM70012_I2C_TOP_I2C_GR_BRIDGE + ***************************************************************************/ +#define I2C_GR_BRIDGE_REVISION 0x00000be0 /* GR Bridge Revision */ +#define I2C_GR_BRIDGE_CTRL 0x00000be4 /* GR Bridge Control Register */ +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0 0x00000be8 /* GR Bridge Software Reset 0 Register */ +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1 0x00000bec /* GR Bridge Software Reset 1 Register */ + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC1 + ***************************************************************************/ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0 0x00000c00 /* Tx DMA Descriptor List0 First Descriptor lower Address */ +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0 0x00000c04 /* Tx DMA Descriptor List0 First Descriptor Upper Address */ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1 0x00000c08 /* Tx DMA Descriptor List1 First Descriptor Lower Address */ +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1 0x00000c0c /* Tx DMA Descriptor List1 First Descriptor Upper Address */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS 0x00000c10 /* Tx DMA Software Descriptor List Control and Status */ +#define MISC1_TX_DMA_ERROR_STATUS 0x00000c18 /* Tx DMA Engine Error Status */ +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR 0x00000c1c /* Tx DMA List0 Current Descriptor Lower Address */ +#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR 0x00000c20 /* Tx DMA List0 Current Descriptor Upper Address */ +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM 0x00000c24 /* Tx DMA List0 Current Descriptor Upper Address */ +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR 0x00000c28 /* Tx DMA List1 Current Descriptor Lower Address */ +#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR 0x00000c2c /* Tx DMA List1 Current Descriptor Upper Address */ +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM 0x00000c30 /* Tx DMA List1 Current Descriptor Upper Address */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0 0x00000c34 /* Y Rx Descriptor List0 First Descriptor Lower Address */ +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0 0x00000c38 /* Y Rx Descriptor List0 First Descriptor Upper Address */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1 0x00000c3c /* Y Rx Descriptor List1 First Descriptor Lower Address */ +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1 0x00000c40 /* Y Rx Descriptor List1 First Descriptor Upper Address */ +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS 0x00000c44 /* Y Rx Software Descriptor List Control and Status */ +#define MISC1_Y_RX_ERROR_STATUS 0x00000c4c /* Y Rx Engine Error Status */ +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR 0x00000c50 /* Y Rx List0 Current Descriptor Lower Address */ +#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR 0x00000c54 /* Y Rx List0 Current Descriptor Upper Address */ +#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT 0x00000c58 /* Y Rx List0 Current Descriptor Byte Count */ +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR 0x00000c5c /* Y Rx List1 Current Descriptor Lower address */ +#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR 0x00000c60 /* Y Rx List1 Current Descriptor Upper address */ +#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT 0x00000c64 /* Y Rx List1 Current Descriptor Byte Count */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0 0x00000c68 /* UV Rx Descriptor List0 First Descriptor lower Address */ +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0 0x00000c6c /* UV Rx Descriptor List0 First Descriptor Upper Address */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1 0x00000c70 /* UV Rx Descriptor List1 First Descriptor Lower Address */ +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1 0x00000c74 /* UV Rx Descriptor List1 First Descriptor Upper Address */ +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS 0x00000c78 /* UV Rx Software Descriptor List Control and Status */ +#define MISC1_UV_RX_ERROR_STATUS 0x00000c7c /* UV Rx Engine Error Status */ +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR 0x00000c80 /* UV Rx List0 Current Descriptor Lower Address */ +#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR 0x00000c84 /* UV Rx List0 Current Descriptor Upper Address */ +#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT 0x00000c88 /* UV Rx List0 Current Descriptor Byte Count */ +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR 0x00000c8c /* UV Rx List1 Current Descriptor Lower Address */ +#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR 0x00000c90 /* UV Rx List1 Current Descriptor Upper Address */ +#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT 0x00000c94 /* UV Rx List1 Current Descriptor Byte Count */ +#define MISC1_DMA_DEBUG_OPTIONS_REG 0x00000c98 /* DMA Debug Options Register */ +#define MISC1_READ_CHANNEL_ERROR_STATUS 0x00000c9c /* Read Channel Error Status */ +#define MISC1_PCIE_DMA_CTRL 0x00000ca0 /* PCIE DMA Control Register */ + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC2 + ***************************************************************************/ +#define MISC2_GLOBAL_CTRL 0x00000d00 /* Global Control Register */ +#define MISC2_INTERNAL_STATUS 0x00000d04 /* Internal Status Register */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL 0x00000d08 /* Internal Debug Mux Control */ +#define MISC2_DEBUG_FIFO_LENGTH 0x00000d0c /* Debug FIFO Length */ + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC3 + ***************************************************************************/ +#define MISC3_RESET_CTRL 0x00000e00 /* Reset Control Register */ +#define MISC3_BIST_CTRL 0x00000e04 /* BIST Control Register */ +#define MISC3_BIST_STATUS 0x00000e08 /* BIST Status Register */ +#define MISC3_RX_CHECKSUM 0x00000e0c /* Receive Checksum */ +#define MISC3_TX_CHECKSUM 0x00000e10 /* Transmit Checksum */ +#define MISC3_ECO_CTRL_CORE 0x00000e14 /* ECO Core Reset Control Register */ +#define MISC3_CSI_TEST_CTRL 0x00000e18 /* CSI Test Control Register */ +#define MISC3_HD_DVI_TEST_CTRL 0x00000e1c /* HD DVI Test Control Register */ + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC_PERST + ***************************************************************************/ +#define MISC_PERST_ECO_CTRL_PERST 0x00000e80 /* ECO PCIE Reset Control Register */ +#define MISC_PERST_DECODER_CTRL 0x00000e84 /* Decoder Control Register */ +#define MISC_PERST_CCE_STATUS 0x00000e88 /* Config Copy Engine Status */ +#define MISC_PERST_PCIE_DEBUG 0x00000e8c /* PCIE Debug Control Register */ +#define MISC_PERST_PCIE_DEBUG_STATUS 0x00000e90 /* PCIE Debug Status Register */ +#define MISC_PERST_VREG_CTRL 0x00000e94 /* Voltage Regulator Control Register */ +#define MISC_PERST_MEM_CTRL 0x00000e98 /* Memory Control Register */ +#define MISC_PERST_CLOCK_CTRL 0x00000e9c /* Clock Control Register */ + + +/**************************************************************************** + * BCM70012_MISC_TOP_GISB_ARBITER + ***************************************************************************/ +#define GISB_ARBITER_REVISION 0x00000f00 /* GISB ARBITER REVISION */ +#define GISB_ARBITER_SCRATCH 0x00000f04 /* GISB ARBITER Scratch Register */ +#define GISB_ARBITER_REQ_MASK 0x00000f08 /* GISB ARBITER Master Request Mask Register */ +#define GISB_ARBITER_TIMER 0x00000f0c /* GISB ARBITER Timer Value Register */ +#define GISB_ARBITER_BP_CTRL 0x00000f10 /* GISB ARBITER Breakpoint Control Register */ +#define GISB_ARBITER_BP_CAP_CLR 0x00000f14 /* GISB ARBITER Breakpoint Capture Clear Register */ +#define GISB_ARBITER_BP_START_ADDR_0 0x00000f18 /* GISB ARBITER Breakpoint Start Address 0 Register */ +#define GISB_ARBITER_BP_END_ADDR_0 0x00000f1c /* GISB ARBITER Breakpoint End Address 0 Register */ +#define GISB_ARBITER_BP_READ_0 0x00000f20 /* GISB ARBITER Breakpoint Master Read Control 0 Register */ +#define GISB_ARBITER_BP_WRITE_0 0x00000f24 /* GISB ARBITER Breakpoint Master Write Control 0 Register */ +#define GISB_ARBITER_BP_ENABLE_0 0x00000f28 /* GISB ARBITER Breakpoint Enable 0 Register */ +#define GISB_ARBITER_BP_START_ADDR_1 0x00000f2c /* GISB ARBITER Breakpoint Start Address 1 Register */ +#define GISB_ARBITER_BP_END_ADDR_1 0x00000f30 /* GISB ARBITER Breakpoint End Address 1 Register */ +#define GISB_ARBITER_BP_READ_1 0x00000f34 /* GISB ARBITER Breakpoint Master Read Control 1 Register */ +#define GISB_ARBITER_BP_WRITE_1 0x00000f38 /* GISB ARBITER Breakpoint Master Write Control 1 Register */ +#define GISB_ARBITER_BP_ENABLE_1 0x00000f3c /* GISB ARBITER Breakpoint Enable 1 Register */ +#define GISB_ARBITER_BP_START_ADDR_2 0x00000f40 /* GISB ARBITER Breakpoint Start Address 2 Register */ +#define GISB_ARBITER_BP_END_ADDR_2 0x00000f44 /* GISB ARBITER Breakpoint End Address 2 Register */ +#define GISB_ARBITER_BP_READ_2 0x00000f48 /* GISB ARBITER Breakpoint Master Read Control 2 Register */ +#define GISB_ARBITER_BP_WRITE_2 0x00000f4c /* GISB ARBITER Breakpoint Master Write Control 2 Register */ +#define GISB_ARBITER_BP_ENABLE_2 0x00000f50 /* GISB ARBITER Breakpoint Enable 2 Register */ +#define GISB_ARBITER_BP_START_ADDR_3 0x00000f54 /* GISB ARBITER Breakpoint Start Address 3 Register */ +#define GISB_ARBITER_BP_END_ADDR_3 0x00000f58 /* GISB ARBITER Breakpoint End Address 3 Register */ +#define GISB_ARBITER_BP_READ_3 0x00000f5c /* GISB ARBITER Breakpoint Master Read Control 3 Register */ +#define GISB_ARBITER_BP_WRITE_3 0x00000f60 /* GISB ARBITER Breakpoint Master Write Control 3 Register */ +#define GISB_ARBITER_BP_ENABLE_3 0x00000f64 /* GISB ARBITER Breakpoint Enable 3 Register */ +#define GISB_ARBITER_BP_START_ADDR_4 0x00000f68 /* GISB ARBITER Breakpoint Start Address 4 Register */ +#define GISB_ARBITER_BP_END_ADDR_4 0x00000f6c /* GISB ARBITER Breakpoint End Address 4 Register */ +#define GISB_ARBITER_BP_READ_4 0x00000f70 /* GISB ARBITER Breakpoint Master Read Control 4 Register */ +#define GISB_ARBITER_BP_WRITE_4 0x00000f74 /* GISB ARBITER Breakpoint Master Write Control 4 Register */ +#define GISB_ARBITER_BP_ENABLE_4 0x00000f78 /* GISB ARBITER Breakpoint Enable 4 Register */ +#define GISB_ARBITER_BP_START_ADDR_5 0x00000f7c /* GISB ARBITER Breakpoint Start Address 5 Register */ +#define GISB_ARBITER_BP_END_ADDR_5 0x00000f80 /* GISB ARBITER Breakpoint End Address 5 Register */ +#define GISB_ARBITER_BP_READ_5 0x00000f84 /* GISB ARBITER Breakpoint Master Read Control 5 Register */ +#define GISB_ARBITER_BP_WRITE_5 0x00000f88 /* GISB ARBITER Breakpoint Master Write Control 5 Register */ +#define GISB_ARBITER_BP_ENABLE_5 0x00000f8c /* GISB ARBITER Breakpoint Enable 5 Register */ +#define GISB_ARBITER_BP_START_ADDR_6 0x00000f90 /* GISB ARBITER Breakpoint Start Address 6 Register */ +#define GISB_ARBITER_BP_END_ADDR_6 0x00000f94 /* GISB ARBITER Breakpoint End Address 6 Register */ +#define GISB_ARBITER_BP_READ_6 0x00000f98 /* GISB ARBITER Breakpoint Master Read Control 6 Register */ +#define GISB_ARBITER_BP_WRITE_6 0x00000f9c /* GISB ARBITER Breakpoint Master Write Control 6 Register */ +#define GISB_ARBITER_BP_ENABLE_6 0x00000fa0 /* GISB ARBITER Breakpoint Enable 6 Register */ +#define GISB_ARBITER_BP_START_ADDR_7 0x00000fa4 /* GISB ARBITER Breakpoint Start Address 7 Register */ +#define GISB_ARBITER_BP_END_ADDR_7 0x00000fa8 /* GISB ARBITER Breakpoint End Address 7 Register */ +#define GISB_ARBITER_BP_READ_7 0x00000fac /* GISB ARBITER Breakpoint Master Read Control 7 Register */ +#define GISB_ARBITER_BP_WRITE_7 0x00000fb0 /* GISB ARBITER Breakpoint Master Write Control 7 Register */ +#define GISB_ARBITER_BP_ENABLE_7 0x00000fb4 /* GISB ARBITER Breakpoint Enable 7 Register */ +#define GISB_ARBITER_BP_CAP_ADDR 0x00000fb8 /* GISB ARBITER Breakpoint Capture Address Register */ +#define GISB_ARBITER_BP_CAP_DATA 0x00000fbc /* GISB ARBITER Breakpoint Capture Data Register */ +#define GISB_ARBITER_BP_CAP_STATUS 0x00000fc0 /* GISB ARBITER Breakpoint Capture Status Register */ +#define GISB_ARBITER_BP_CAP_MASTER 0x00000fc4 /* GISB ARBITER Breakpoint Capture GISB MASTER Register */ +#define GISB_ARBITER_ERR_CAP_CLR 0x00000fc8 /* GISB ARBITER Error Capture Clear Register */ +#define GISB_ARBITER_ERR_CAP_ADDR 0x00000fcc /* GISB ARBITER Error Capture Address Register */ +#define GISB_ARBITER_ERR_CAP_DATA 0x00000fd0 /* GISB ARBITER Error Capture Data Register */ +#define GISB_ARBITER_ERR_CAP_STATUS 0x00000fd4 /* GISB ARBITER Error Capture Status Register */ +#define GISB_ARBITER_ERR_CAP_MASTER 0x00000fd8 /* GISB ARBITER Error Capture GISB MASTER Register */ + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC_GR_BRIDGE + ***************************************************************************/ +#define MISC_GR_BRIDGE_REVISION 0x00000fe0 /* GR Bridge Revision */ +#define MISC_GR_BRIDGE_CTRL 0x00000fe4 /* GR Bridge Control Register */ +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0 0x00000fe8 /* GR Bridge Software Reset 0 Register */ +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1 0x00000fec /* GR Bridge Software Reset 1 Register */ + + +/**************************************************************************** + * BCM70012_DBU_TOP_DBU + ***************************************************************************/ +#define DBU_DBU_CMD 0x00001000 /* DBU (Debug UART) command register */ +#define DBU_DBU_STATUS 0x00001004 /* DBU (Debug UART) status register */ +#define DBU_DBU_CONFIG 0x00001008 /* DBU (Debug UART) configuration register */ +#define DBU_DBU_TIMING 0x0000100c /* DBU (Debug UART) timing register */ +#define DBU_DBU_RXDATA 0x00001010 /* DBU (Debug UART) recieve data register */ +#define DBU_DBU_TXDATA 0x00001014 /* DBU (Debug UART) transmit data register */ + + +/**************************************************************************** + * BCM70012_DBU_TOP_DBU_RGR_BRIDGE + ***************************************************************************/ +#define DBU_RGR_BRIDGE_REVISION 0x000013e0 /* RGR Bridge Revision */ +#define DBU_RGR_BRIDGE_CTRL 0x000013e4 /* RGR Bridge Control Register */ +#define DBU_RGR_BRIDGE_RBUS_TIMER 0x000013e8 /* RGR Bridge RBUS Timer Register */ +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0 0x000013ec /* RGR Bridge Software Reset 0 Register */ +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1 0x000013f0 /* RGR Bridge Software Reset 1 Register */ + + +/**************************************************************************** + * BCM70012_OTP_TOP_OTP + ***************************************************************************/ +#define OTP_CONFIG_INFO 0x00001400 /* OTP Configuration Register */ +#define OTP_CMD 0x00001404 /* OTP Command Register */ +#define OTP_STATUS 0x00001408 /* OTP Status Register */ +#define OTP_CONTENT_MISC 0x0000140c /* Content : Miscellaneous Register */ +#define OTP_CONTENT_AES_0 0x00001410 /* Content : AES Key 0 Register */ +#define OTP_CONTENT_AES_1 0x00001414 /* Content : AES Key 1 Register */ +#define OTP_CONTENT_AES_2 0x00001418 /* Content : AES Key 2 Register */ +#define OTP_CONTENT_AES_3 0x0000141c /* Content : AES Key 3 Register */ +#define OTP_CONTENT_SHA_0 0x00001420 /* Content : SHA Key 0 Register */ +#define OTP_CONTENT_SHA_1 0x00001424 /* Content : SHA Key 1 Register */ +#define OTP_CONTENT_SHA_2 0x00001428 /* Content : SHA Key 2 Register */ +#define OTP_CONTENT_SHA_3 0x0000142c /* Content : SHA Key 3 Register */ +#define OTP_CONTENT_SHA_4 0x00001430 /* Content : SHA Key 4 Register */ +#define OTP_CONTENT_SHA_5 0x00001434 /* Content : SHA Key 5 Register */ +#define OTP_CONTENT_SHA_6 0x00001438 /* Content : SHA Key 6 Register */ +#define OTP_CONTENT_SHA_7 0x0000143c /* Content : SHA Key 7 Register */ +#define OTP_CONTENT_CHECKSUM 0x00001440 /* Content : Checksum Register */ +#define OTP_PROG_CTRL 0x00001444 /* Programming Control Register */ +#define OTP_PROG_STATUS 0x00001448 /* Programming Status Register */ +#define OTP_PROG_PULSE 0x0000144c /* Program Pulse Width Register */ +#define OTP_VERIFY_PULSE 0x00001450 /* Verify Pulse Width Register */ +#define OTP_PROG_MASK 0x00001454 /* Program Mask Register */ +#define OTP_DATA_INPUT 0x00001458 /* Data Input Register */ +#define OTP_DATA_OUTPUT 0x0000145c /* Data Output Register */ + + +/**************************************************************************** + * BCM70012_OTP_TOP_OTP_GR_BRIDGE + ***************************************************************************/ +#define OTP_GR_BRIDGE_REVISION 0x000017e0 /* GR Bridge Revision */ +#define OTP_GR_BRIDGE_CTRL 0x000017e4 /* GR Bridge Control Register */ +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0 0x000017e8 /* GR Bridge Software Reset 0 Register */ +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1 0x000017ec /* GR Bridge Software Reset 1 Register */ + + +/**************************************************************************** + * BCM70012_AES_TOP_AES + ***************************************************************************/ +#define AES_CONFIG_INFO 0x00001800 /* AES Configuration Information Register */ +#define AES_CMD 0x00001804 /* AES Command Register */ +#define AES_STATUS 0x00001808 /* AES Status Register */ +#define AES_EEPROM_CONFIG 0x0000180c /* AES EEPROM Configuration Register */ +#define AES_EEPROM_DATA_0 0x00001810 /* AES EEPROM Data Register 0 */ +#define AES_EEPROM_DATA_1 0x00001814 /* AES EEPROM Data Register 1 */ +#define AES_EEPROM_DATA_2 0x00001818 /* AES EEPROM Data Register 2 */ +#define AES_EEPROM_DATA_3 0x0000181c /* AES EEPROM Data Register 3 */ + + +/**************************************************************************** + * BCM70012_AES_TOP_AES_RGR_BRIDGE + ***************************************************************************/ +#define AES_RGR_BRIDGE_REVISION 0x00001be0 /* RGR Bridge Revision */ +#define AES_RGR_BRIDGE_CTRL 0x00001be4 /* RGR Bridge Control Register */ +#define AES_RGR_BRIDGE_RBUS_TIMER 0x00001be8 /* RGR Bridge RBUS Timer Register */ +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0 0x00001bec /* RGR Bridge Software Reset 0 Register */ +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1 0x00001bf0 /* RGR Bridge Software Reset 1 Register */ + + +/**************************************************************************** + * BCM70012_DCI_TOP_DCI + ***************************************************************************/ +#define DCI_CMD 0x00001c00 /* DCI Command Register */ +#define DCI_STATUS 0x00001c04 /* DCI Status Register */ +#define DCI_DRAM_BASE_ADDR 0x00001c08 /* DRAM Base Address Register */ +#define DCI_FIRMWARE_ADDR 0x00001c0c /* Firmware Address Register */ +#define DCI_FIRMWARE_DATA 0x00001c10 /* Firmware Data Register */ +#define DCI_SIGNATURE_DATA_0 0x00001c14 /* Signature Data Register 0 */ +#define DCI_SIGNATURE_DATA_1 0x00001c18 /* Signature Data Register 1 */ +#define DCI_SIGNATURE_DATA_2 0x00001c1c /* Signature Data Register 2 */ +#define DCI_SIGNATURE_DATA_3 0x00001c20 /* Signature Data Register 3 */ +#define DCI_SIGNATURE_DATA_4 0x00001c24 /* Signature Data Register 4 */ +#define DCI_SIGNATURE_DATA_5 0x00001c28 /* Signature Data Register 5 */ +#define DCI_SIGNATURE_DATA_6 0x00001c2c /* Signature Data Register 6 */ +#define DCI_SIGNATURE_DATA_7 0x00001c30 /* Signature Data Register 7 */ + + +/**************************************************************************** + * BCM70012_DCI_TOP_DCI_RGR_BRIDGE + ***************************************************************************/ +#define DCI_RGR_BRIDGE_REVISION 0x00001fe0 /* RGR Bridge Revision */ +#define DCI_RGR_BRIDGE_CTRL 0x00001fe4 /* RGR Bridge Control Register */ +#define DCI_RGR_BRIDGE_RBUS_TIMER 0x00001fe8 /* RGR Bridge RBUS Timer Register */ +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0 0x00001fec /* RGR Bridge Software Reset 0 Register */ +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1 0x00001ff0 /* RGR Bridge Software Reset 1 Register */ + + +/**************************************************************************** + * BCM70012_CCE_TOP_CCE_RGR_BRIDGE + ***************************************************************************/ +#define CCE_RGR_BRIDGE_REVISION 0x000023e0 /* RGR Bridge Revision */ +#define CCE_RGR_BRIDGE_CTRL 0x000023e4 /* RGR Bridge Control Register */ +#define CCE_RGR_BRIDGE_RBUS_TIMER 0x000023e8 /* RGR Bridge RBUS Timer Register */ +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0 0x000023ec /* RGR Bridge Software Reset 0 Register */ +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1 0x000023f0 /* RGR Bridge Software Reset 1 Register */ + + +/**************************************************************************** + * BCM70012_TGT_TOP_PCIE_CFG + ***************************************************************************/ +/**************************************************************************** + * PCIE_CFG :: DEVICE_VENDOR_ID + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_VENDOR_ID :: DEVICE_ID [31:16] */ +#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_MASK 0xffff0000 +#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_ALIGN 0 +#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_BITS 16 +#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT 16 + +/* PCIE_CFG :: DEVICE_VENDOR_ID :: VENDOR_ID [15:00] */ +#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_MASK 0x0000ffff +#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_ALIGN 0 +#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_BITS 16 +#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: STATUS_COMMAND + ***************************************************************************/ +/* PCIE_CFG :: STATUS_COMMAND :: DETECTED_PARITY_ERROR [31:31] */ +#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_MASK 0x80000000 +#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_SHIFT 31 + +/* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_SYSTEM_ERROR [30:30] */ +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_MASK 0x40000000 +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_SHIFT 30 + +/* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_MASTER_ABORT [29:29] */ +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_SHIFT 29 + +/* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_TARGET_ABORT [28:28] */ +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_SHIFT 28 + +/* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_TARGET_ABORT [27:27] */ +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_MASK 0x08000000 +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_SHIFT 27 + +/* PCIE_CFG :: STATUS_COMMAND :: DEVSEL_TIMING [26:25] */ +#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_MASK 0x06000000 +#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_BITS 2 +#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_SHIFT 25 + +/* PCIE_CFG :: STATUS_COMMAND :: MASTER_DATA_PARITY_ERROR [24:24] */ +#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_MASK 0x01000000 +#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_SHIFT 24 + +/* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_CAPABLE [23:23] */ +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_MASK 0x00800000 +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_SHIFT 23 + +/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_0 [22:22] */ +#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_MASK 0x00400000 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_SHIFT 22 + +/* PCIE_CFG :: STATUS_COMMAND :: CAPABLE_66MHZ [21:21] */ +#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_MASK 0x00200000 +#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_SHIFT 21 + +/* PCIE_CFG :: STATUS_COMMAND :: CAPABILITIES_LIST [20:20] */ +#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_MASK 0x00100000 +#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_SHIFT 20 + +/* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_STATUS [19:19] */ +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_MASK 0x00080000 +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_SHIFT 19 + +/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_1 [18:16] */ +#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_MASK 0x00070000 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_BITS 3 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_SHIFT 16 + +/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_2 [15:11] */ +#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_MASK 0x0000f800 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_BITS 5 +#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_SHIFT 11 + +/* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_DISABLE [10:10] */ +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_MASK 0x00000400 +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_SHIFT 10 + +/* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_ENABLE [09:09] */ +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_MASK 0x00000200 +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_SHIFT 9 + +/* PCIE_CFG :: STATUS_COMMAND :: SYSTEM_ERROR_ENABLE [08:08] */ +#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_MASK 0x00000100 +#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_SHIFT 8 + +/* PCIE_CFG :: STATUS_COMMAND :: STEPPING_CONTROL [07:07] */ +#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_MASK 0x00000080 +#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_SHIFT 7 + +/* PCIE_CFG :: STATUS_COMMAND :: PARITY_ERROR_ENABLE [06:06] */ +#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_MASK 0x00000040 +#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_SHIFT 6 + +/* PCIE_CFG :: STATUS_COMMAND :: VGA_PALETTE_SNOOP [05:05] */ +#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_MASK 0x00000020 +#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_SHIFT 5 + +/* PCIE_CFG :: STATUS_COMMAND :: MEMORY_WRITE_AND_INVALIDATE [04:04] */ +#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_MASK 0x00000010 +#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_SHIFT 4 + +/* PCIE_CFG :: STATUS_COMMAND :: SPECIAL_CYCLES [03:03] */ +#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_MASK 0x00000008 +#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT 3 + +/* PCIE_CFG :: STATUS_COMMAND :: BUS_MASTER [02:02] */ +#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_MASK 0x00000004 +#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_SHIFT 2 + +/* PCIE_CFG :: STATUS_COMMAND :: MEMORY_SPACE [01:01] */ +#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_MASK 0x00000002 +#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_SHIFT 1 + +/* PCIE_CFG :: STATUS_COMMAND :: I_O_SPACE [00:00] */ +#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_MASK 0x00000001 +#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_ALIGN 0 +#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_BITS 1 +#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID + ***************************************************************************/ +/* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: PCI_CLASSCODE [31:08] */ +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_MASK 0xffffff00 +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_ALIGN 0 +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_BITS 24 +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_SHIFT 8 + +/* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: REVISION_ID [07:00] */ +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_MASK 0x000000ff +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_ALIGN 0 +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_BITS 8 +#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE + ***************************************************************************/ +/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: BIST [31:24] */ +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_MASK 0xff000000 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_ALIGN 0 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_BITS 8 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_SHIFT 24 + +/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: HEADER_TYPE [23:16] */ +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_MASK 0x00ff0000 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_ALIGN 0 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_BITS 8 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_SHIFT 16 + +/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: LATENCY_TIMER [15:08] */ +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_MASK 0x0000ff00 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_ALIGN 0 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_BITS 8 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_SHIFT 8 + +/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: CACHE_LINE_SIZE [07:00] */ +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_MASK 0x000000ff +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_ALIGN 0 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_BITS 8 +#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: BASE_ADDRESS_1 + ***************************************************************************/ +/* PCIE_CFG :: BASE_ADDRESS_1 :: BASE_ADDRESS [31:16] */ +#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_MASK 0xffff0000 +#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_BITS 16 +#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_SHIFT 16 + +/* PCIE_CFG :: BASE_ADDRESS_1 :: RESERVED_0 [15:04] */ +#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_MASK 0x0000fff0 +#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_BITS 12 +#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_SHIFT 4 + +/* PCIE_CFG :: BASE_ADDRESS_1 :: PREFETCHABLE [03:03] */ +#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_MASK 0x00000008 +#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_BITS 1 +#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_SHIFT 3 + +/* PCIE_CFG :: BASE_ADDRESS_1 :: TYPE [02:01] */ +#define PCIE_CFG_BASE_ADDRESS_1_TYPE_MASK 0x00000006 +#define PCIE_CFG_BASE_ADDRESS_1_TYPE_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_1_TYPE_BITS 2 +#define PCIE_CFG_BASE_ADDRESS_1_TYPE_SHIFT 1 + +/* PCIE_CFG :: BASE_ADDRESS_1 :: MEMORY_SPACE_INDICATOR [00:00] */ +#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_MASK 0x00000001 +#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_BITS 1 +#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: BASE_ADDRESS_2 + ***************************************************************************/ +/* PCIE_CFG :: BASE_ADDRESS_2 :: EXTENDED_BASE_ADDRESS [31:00] */ +#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_MASK 0xffffffff +#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_BITS 32 +#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: BASE_ADDRESS_3 + ***************************************************************************/ +/* PCIE_CFG :: BASE_ADDRESS_3 :: BASE_ADDRESS_2 [31:22] */ +#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_MASK 0xffc00000 +#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_BITS 10 +#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_SHIFT 22 + +/* PCIE_CFG :: BASE_ADDRESS_3 :: RESERVED_0 [21:04] */ +#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_MASK 0x003ffff0 +#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_BITS 18 +#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_SHIFT 4 + +/* PCIE_CFG :: BASE_ADDRESS_3 :: PREFETCHABLE [03:03] */ +#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_MASK 0x00000008 +#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_BITS 1 +#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_SHIFT 3 + +/* PCIE_CFG :: BASE_ADDRESS_3 :: TYPE [02:01] */ +#define PCIE_CFG_BASE_ADDRESS_3_TYPE_MASK 0x00000006 +#define PCIE_CFG_BASE_ADDRESS_3_TYPE_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_3_TYPE_BITS 2 +#define PCIE_CFG_BASE_ADDRESS_3_TYPE_SHIFT 1 + +/* PCIE_CFG :: BASE_ADDRESS_3 :: MEMORY_SPACE_INDICATOR [00:00] */ +#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_MASK 0x00000001 +#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_BITS 1 +#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: BASE_ADDRESS_4 + ***************************************************************************/ +/* PCIE_CFG :: BASE_ADDRESS_4 :: EXTENDED_BASE_ADDRESS_2 [31:00] */ +#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_MASK 0xffffffff +#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_ALIGN 0 +#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_BITS 32 +#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: CARDBUS_CIS_POINTER + ***************************************************************************/ +/* PCIE_CFG :: CARDBUS_CIS_POINTER :: CARDBUS_CIS_POINTER [31:00] */ +#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_MASK 0xffffffff +#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_ALIGN 0 +#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_BITS 32 +#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID + ***************************************************************************/ +/* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_DEVICE_ID [31:16] */ +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_MASK 0xffff0000 +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_ALIGN 0 +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_BITS 16 +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_SHIFT 16 + +/* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_VENDOR_ID [15:00] */ +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_MASK 0x0000ffff +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_ALIGN 0 +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_BITS 16 +#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS + ***************************************************************************/ +/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_BASE_ADDRESS [31:16] */ +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_MASK 0xffff0000 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_BITS 16 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_SHIFT 16 + +/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_SIZE_INDICATION [15:11] */ +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_MASK 0x0000f800 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_BITS 5 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_SHIFT 11 + +/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: RESERVED_0 [10:01] */ +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_MASK 0x000007fe +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_BITS 10 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_SHIFT 1 + +/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: EXPANSION_ROM_ENABLE [00:00] */ +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_MASK 0x00000001 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_BITS 1 +#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: CAPABILITIES_POINTER + ***************************************************************************/ +/* PCIE_CFG :: CAPABILITIES_POINTER :: CAPABILITIES_POINTER [31:00] */ +#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_MASK 0xffffffff +#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_ALIGN 0 +#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_BITS 32 +#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: INTERRUPT + ***************************************************************************/ +/* PCIE_CFG :: INTERRUPT :: RESERVED_0 [31:16] */ +#define PCIE_CFG_INTERRUPT_RESERVED_0_MASK 0xffff0000 +#define PCIE_CFG_INTERRUPT_RESERVED_0_ALIGN 0 +#define PCIE_CFG_INTERRUPT_RESERVED_0_BITS 16 +#define PCIE_CFG_INTERRUPT_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: INTERRUPT :: INTERRUPT_PIN [15:08] */ +#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_MASK 0x0000ff00 +#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_ALIGN 0 +#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_BITS 8 +#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_SHIFT 8 + +/* PCIE_CFG :: INTERRUPT :: INTERRUPT_LINE [07:00] */ +#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_MASK 0x000000ff +#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_ALIGN 0 +#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_BITS 8 +#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: VPD_CAPABILITIES + ***************************************************************************/ +/* PCIE_CFG :: VPD_CAPABILITIES :: RESERVED_0 [31:00] */ +#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_MASK 0xffffffff +#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_ALIGN 0 +#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_BITS 32 +#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: VPD_DATA + ***************************************************************************/ +/* PCIE_CFG :: VPD_DATA :: RESERVED_0 [31:00] */ +#define PCIE_CFG_VPD_DATA_RESERVED_0_MASK 0xffffffff +#define PCIE_CFG_VPD_DATA_RESERVED_0_ALIGN 0 +#define PCIE_CFG_VPD_DATA_RESERVED_0_BITS 32 +#define PCIE_CFG_VPD_DATA_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY + ***************************************************************************/ +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_SUPPORT [31:27] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_MASK 0xf8000000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_BITS 5 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_SHIFT 27 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D2_SUPPORT [26:26] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_MASK 0x04000000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_SHIFT 26 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D1_SUPPORT [25:25] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_MASK 0x02000000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_SHIFT 25 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: AUX_CURRENT [24:22] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_MASK 0x01c00000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_BITS 3 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_SHIFT 22 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: DSI [21:21] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_MASK 0x00200000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_SHIFT 21 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: RESERVED_0 [20:20] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_MASK 0x00100000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_SHIFT 20 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_CLOCK [19:19] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_MASK 0x00080000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_SHIFT 19 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: VERSION [18:16] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_MASK 0x00070000 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_BITS 3 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_SHIFT 16 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: NEXT_POINTER [15:08] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_MASK 0x0000ff00 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_BITS 8 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_SHIFT 8 + +/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: CAPABILITY_ID [07:00] */ +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_MASK 0x000000ff +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_BITS 8 +#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS + ***************************************************************************/ +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PM_DATA [31:24] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_MASK 0xff000000 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_BITS 8 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_SHIFT 24 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_0 [23:16] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_MASK 0x00ff0000 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_BITS 8 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_STATUS [15:15] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_MASK 0x00008000 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_SHIFT 15 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SCALE [14:13] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_MASK 0x00006000 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_BITS 2 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_SHIFT 13 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SELECT [12:09] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_MASK 0x00001e00 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_BITS 4 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_SHIFT 9 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_ENABLE [08:08] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_MASK 0x00000100 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_SHIFT 8 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_1 [07:04] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_MASK 0x000000f0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_BITS 4 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_SHIFT 4 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: NO_SOFT_RESET [03:03] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_MASK 0x00000008 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_SHIFT 3 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_2 [02:02] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_MASK 0x00000004 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_BITS 1 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_SHIFT 2 + +/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: POWER_STATE [01:00] */ +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_MASK 0x00000003 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_ALIGN 0 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_BITS 2 +#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: MSI_CAPABILITY_HEADER + ***************************************************************************/ +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_CONTROL [31:24] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_MASK 0xff000000 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_BITS 8 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_SHIFT 24 + +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: ADDRESS_CAPABLE_64_BIT [23:23] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_MASK 0x00800000 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_BITS 1 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_SHIFT 23 + +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_ENABLE [22:20] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_MASK 0x00700000 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_BITS 3 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_SHIFT 20 + +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_CAPABLE [19:17] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_MASK 0x000e0000 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_BITS 3 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_SHIFT 17 + +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_ENABLE [16:16] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_MASK 0x00010000 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_BITS 1 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_SHIFT 16 + +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_BITS 8 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 + +/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ +#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff +#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_BITS 8 +#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: MSI_LOWER_ADDRESS + ***************************************************************************/ +/* PCIE_CFG :: MSI_LOWER_ADDRESS :: MSI_LOWER_ADDRESS [31:02] */ +#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_MASK 0xfffffffc +#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_ALIGN 0 +#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_BITS 30 +#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_SHIFT 2 + +/* PCIE_CFG :: MSI_LOWER_ADDRESS :: RESERVED_0 [01:00] */ +#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_MASK 0x00000003 +#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_ALIGN 0 +#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_BITS 2 +#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER + ***************************************************************************/ +/* PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER :: MSI_UPPER_ADDRESS [31:00] */ +#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_MASK 0xffffffff +#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_ALIGN 0 +#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_BITS 32 +#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: MSI_DATA + ***************************************************************************/ +/* PCIE_CFG :: MSI_DATA :: RESERVED_0 [31:16] */ +#define PCIE_CFG_MSI_DATA_RESERVED_0_MASK 0xffff0000 +#define PCIE_CFG_MSI_DATA_RESERVED_0_ALIGN 0 +#define PCIE_CFG_MSI_DATA_RESERVED_0_BITS 16 +#define PCIE_CFG_MSI_DATA_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: MSI_DATA :: MSI_DATA [15:00] */ +#define PCIE_CFG_MSI_DATA_MSI_DATA_MASK 0x0000ffff +#define PCIE_CFG_MSI_DATA_MSI_DATA_ALIGN 0 +#define PCIE_CFG_MSI_DATA_MSI_DATA_BITS 16 +#define PCIE_CFG_MSI_DATA_MSI_DATA_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER + ***************************************************************************/ +/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: RESERVED_0 [31:24] */ +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_MASK 0xff000000 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_ALIGN 0 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_BITS 8 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_SHIFT 24 + +/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: VENDOR_SPECIFIC_CAPABILITY_LENGTH [23:16] */ +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_MASK 0x00ff0000 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_ALIGN 0 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_BITS 8 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_SHIFT 16 + +/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_ALIGN 0 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_BITS 8 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 + +/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_BITS 8 +#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES + ***************************************************************************/ +/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: POR_RESET_COUNTER [31:28] */ +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_MASK 0xf0000000 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_ALIGN 0 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_BITS 4 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_SHIFT 28 + +/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: HOT_RESET_COUNTER [27:24] */ +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_MASK 0x0f000000 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_ALIGN 0 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_BITS 4 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_SHIFT 24 + +/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: GRC_RESET_COUNTER [23:16] */ +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_MASK 0x00ff0000 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_ALIGN 0 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_BITS 8 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_SHIFT 16 + +/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: PERST_RESET_COUNTER [15:08] */ +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_MASK 0x0000ff00 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_ALIGN 0 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_BITS 8 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_SHIFT 8 + +/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: LINKDOWN_RESET_COUNTER [07:00] */ +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_MASK 0x000000ff +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_ALIGN 0 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_BITS 8 +#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: PRODUCT_ID [31:24] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xff000000 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_BITS 8 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 24 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ASIC_REVISION_ID [23:16] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_MASK 0x00ff0000 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_BITS 8 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_SHIFT 16 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TLP_MINOR_ERROR_TOLERANCE [15:15] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x00008000 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: LOG_HEADER_OVERFLOW [14:14] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x00004000 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BOUNDARY_CHECK [13:13] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x00002000 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BYTE_ENABLE_RULE_CHECK [12:12] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x00001000 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: INTERRUPT_CHECK [11:11] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x00000800 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: RCB_CHECK [10:10] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x00000400 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TAGGED_STATUS_MODE [09:09] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x00000200 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT_MODE [08:08] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x00000100 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_INDIRECT_ACCESS [07:07] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x00000080 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_REGISTER_WORD_SWAP [06:06] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x00000040 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY [05:05] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000020 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_SHIFT 5 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY [04:04] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000010 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_SHIFT 4 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_WORD_SWAP [03:03] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x00000008 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_BYTE_SWAP [02:02] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x00000004 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT [01:01] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x00000002 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1 + +/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: CLEAR_INTERRUPT [00:00] */ +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x00000001 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_ALIGN 0 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_BITS 1 +#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: SPARE + ***************************************************************************/ +/* PCIE_CFG :: SPARE :: UNUSED_0 [31:16] */ +#define PCIE_CFG_SPARE_UNUSED_0_MASK 0xffff0000 +#define PCIE_CFG_SPARE_UNUSED_0_ALIGN 0 +#define PCIE_CFG_SPARE_UNUSED_0_BITS 16 +#define PCIE_CFG_SPARE_UNUSED_0_SHIFT 16 + +/* PCIE_CFG :: SPARE :: RESERVED_0 [15:15] */ +#define PCIE_CFG_SPARE_RESERVED_0_MASK 0x00008000 +#define PCIE_CFG_SPARE_RESERVED_0_ALIGN 0 +#define PCIE_CFG_SPARE_RESERVED_0_BITS 1 +#define PCIE_CFG_SPARE_RESERVED_0_SHIFT 15 + +/* PCIE_CFG :: SPARE :: UNUSED_1 [14:02] */ +#define PCIE_CFG_SPARE_UNUSED_1_MASK 0x00007ffc +#define PCIE_CFG_SPARE_UNUSED_1_ALIGN 0 +#define PCIE_CFG_SPARE_UNUSED_1_BITS 13 +#define PCIE_CFG_SPARE_UNUSED_1_SHIFT 2 + +/* PCIE_CFG :: SPARE :: BAR2_TARGET_WORD_SWAP [01:01] */ +#define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_MASK 0x00000002 +#define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_ALIGN 0 +#define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_BITS 1 +#define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_SHIFT 1 + +/* PCIE_CFG :: SPARE :: BAR2_TARGET_BYTE_SWAP [00:00] */ +#define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_MASK 0x00000001 +#define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_ALIGN 0 +#define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_BITS 1 +#define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PCI_STATE + ***************************************************************************/ +/* PCIE_CFG :: PCI_STATE :: RESERVED_0 [31:16] */ +#define PCIE_CFG_PCI_STATE_RESERVED_0_MASK 0xffff0000 +#define PCIE_CFG_PCI_STATE_RESERVED_0_ALIGN 0 +#define PCIE_CFG_PCI_STATE_RESERVED_0_BITS 16 +#define PCIE_CFG_PCI_STATE_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: PCI_STATE :: CONFIG_RETRY [15:15] */ +#define PCIE_CFG_PCI_STATE_CONFIG_RETRY_MASK 0x00008000 +#define PCIE_CFG_PCI_STATE_CONFIG_RETRY_ALIGN 0 +#define PCIE_CFG_PCI_STATE_CONFIG_RETRY_BITS 1 +#define PCIE_CFG_PCI_STATE_CONFIG_RETRY_SHIFT 15 + +/* PCIE_CFG :: PCI_STATE :: RESERVED_1 [14:12] */ +#define PCIE_CFG_PCI_STATE_RESERVED_1_MASK 0x00007000 +#define PCIE_CFG_PCI_STATE_RESERVED_1_ALIGN 0 +#define PCIE_CFG_PCI_STATE_RESERVED_1_BITS 3 +#define PCIE_CFG_PCI_STATE_RESERVED_1_SHIFT 12 + +/* PCIE_CFG :: PCI_STATE :: MAX_PCI_TARGET_RETRY [11:09] */ +#define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0x00000e00 +#define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_ALIGN 0 +#define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_BITS 3 +#define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9 + +/* PCIE_CFG :: PCI_STATE :: FLAT_VIEW [08:08] */ +#define PCIE_CFG_PCI_STATE_FLAT_VIEW_MASK 0x00000100 +#define PCIE_CFG_PCI_STATE_FLAT_VIEW_ALIGN 0 +#define PCIE_CFG_PCI_STATE_FLAT_VIEW_BITS 1 +#define PCIE_CFG_PCI_STATE_FLAT_VIEW_SHIFT 8 + +/* PCIE_CFG :: PCI_STATE :: VPD_AVAILABLE [07:07] */ +#define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_MASK 0x00000080 +#define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_ALIGN 0 +#define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_BITS 1 +#define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_SHIFT 7 + +/* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_RETRY [06:06] */ +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x00000040 +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_ALIGN 0 +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_BITS 1 +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6 + +/* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_DESIRED [05:05] */ +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x00000020 +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_ALIGN 0 +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_BITS 1 +#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5 + +/* PCIE_CFG :: PCI_STATE :: RESERVED_2 [04:00] */ +#define PCIE_CFG_PCI_STATE_RESERVED_2_MASK 0x0000001f +#define PCIE_CFG_PCI_STATE_RESERVED_2_ALIGN 0 +#define PCIE_CFG_PCI_STATE_RESERVED_2_BITS 5 +#define PCIE_CFG_PCI_STATE_RESERVED_2_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: CLOCK_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: CLOCK_CONTROL :: PL_CLOCK_DISABLE [31:31] */ +#define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_MASK 0x80000000 +#define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_BITS 1 +#define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_SHIFT 31 + +/* PCIE_CFG :: CLOCK_CONTROL :: DLL_CLOCK_DISABLE [30:30] */ +#define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_MASK 0x40000000 +#define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_BITS 1 +#define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_SHIFT 30 + +/* PCIE_CFG :: CLOCK_CONTROL :: TL_CLOCK_DISABLE [29:29] */ +#define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_MASK 0x20000000 +#define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_BITS 1 +#define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_SHIFT 29 + +/* PCIE_CFG :: CLOCK_CONTROL :: PCI_EXPRESS_CLOCK_TO_CORE_CLOCK [28:28] */ +#define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_MASK 0x10000000 +#define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_BITS 1 +#define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_SHIFT 28 + +/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_0 [27:21] */ +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_MASK 0x0fe00000 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_BITS 7 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_SHIFT 21 + +/* PCIE_CFG :: CLOCK_CONTROL :: SELECT_FINAL_ALT_CLOCK_SOURCE [20:20] */ +#define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_MASK 0x00100000 +#define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_BITS 1 +#define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_SHIFT 20 + +/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_1 [19:13] */ +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_MASK 0x000fe000 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_BITS 7 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_SHIFT 13 + +/* PCIE_CFG :: CLOCK_CONTROL :: SELECT_ALT_CLOCK [12:12] */ +#define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_MASK 0x00001000 +#define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_BITS 1 +#define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_SHIFT 12 + +/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_2 [11:08] */ +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_MASK 0x00000f00 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_BITS 4 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_SHIFT 8 + +/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_3 [07:00] */ +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_MASK 0x000000ff +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_ALIGN 0 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_BITS 8 +#define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: REGISTER_BASE + ***************************************************************************/ +/* PCIE_CFG :: REGISTER_BASE :: RESERVED_0 [31:18] */ +#define PCIE_CFG_REGISTER_BASE_RESERVED_0_MASK 0xfffc0000 +#define PCIE_CFG_REGISTER_BASE_RESERVED_0_ALIGN 0 +#define PCIE_CFG_REGISTER_BASE_RESERVED_0_BITS 14 +#define PCIE_CFG_REGISTER_BASE_RESERVED_0_SHIFT 18 + +/* PCIE_CFG :: REGISTER_BASE :: REGISTER_BASE_REGISTER [17:02] */ +#define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_MASK 0x0003fffc +#define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_ALIGN 0 +#define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_BITS 16 +#define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_SHIFT 2 + +/* PCIE_CFG :: REGISTER_BASE :: RESERVED_1 [01:00] */ +#define PCIE_CFG_REGISTER_BASE_RESERVED_1_MASK 0x00000003 +#define PCIE_CFG_REGISTER_BASE_RESERVED_1_ALIGN 0 +#define PCIE_CFG_REGISTER_BASE_RESERVED_1_BITS 2 +#define PCIE_CFG_REGISTER_BASE_RESERVED_1_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: MEMORY_BASE + ***************************************************************************/ +/* PCIE_CFG :: MEMORY_BASE :: RESERVED_0 [31:24] */ +#define PCIE_CFG_MEMORY_BASE_RESERVED_0_MASK 0xff000000 +#define PCIE_CFG_MEMORY_BASE_RESERVED_0_ALIGN 0 +#define PCIE_CFG_MEMORY_BASE_RESERVED_0_BITS 8 +#define PCIE_CFG_MEMORY_BASE_RESERVED_0_SHIFT 24 + +/* PCIE_CFG :: MEMORY_BASE :: MEMORY_BASE_REGISTER [23:02] */ +#define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_MASK 0x00fffffc +#define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_ALIGN 0 +#define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_BITS 22 +#define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_SHIFT 2 + +/* PCIE_CFG :: MEMORY_BASE :: RESERVED_1 [01:00] */ +#define PCIE_CFG_MEMORY_BASE_RESERVED_1_MASK 0x00000003 +#define PCIE_CFG_MEMORY_BASE_RESERVED_1_ALIGN 0 +#define PCIE_CFG_MEMORY_BASE_RESERVED_1_BITS 2 +#define PCIE_CFG_MEMORY_BASE_RESERVED_1_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: REGISTER_DATA + ***************************************************************************/ +/* PCIE_CFG :: REGISTER_DATA :: REGISTER_DATA_REGISTER [31:00] */ +#define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_MASK 0xffffffff +#define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_ALIGN 0 +#define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_BITS 32 +#define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: MEMORY_DATA + ***************************************************************************/ +/* PCIE_CFG :: MEMORY_DATA :: MEMORY_DATA_REGISTER [31:00] */ +#define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_MASK 0xffffffff +#define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_ALIGN 0 +#define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_BITS 32 +#define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: EXPANSION_ROM_BAR_SIZE + ***************************************************************************/ +/* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: RESERVED_0 [31:04] */ +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_MASK 0xfffffff0 +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_BITS 28 +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_SHIFT 4 + +/* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: BAR_SIZE [03:00] */ +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_MASK 0x0000000f +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_BITS 4 +#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: EXPANSION_ROM_ADDRESS + ***************************************************************************/ +/* PCIE_CFG :: EXPANSION_ROM_ADDRESS :: ROM_CTL_ADDR [31:00] */ +#define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_MASK 0xffffffff +#define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_BITS 32 +#define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: EXPANSION_ROM_DATA + ***************************************************************************/ +/* PCIE_CFG :: EXPANSION_ROM_DATA :: ROM_DATA [31:00] */ +#define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_MASK 0xffffffff +#define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_ALIGN 0 +#define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_BITS 32 +#define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: VPD_INTERFACE + ***************************************************************************/ +/* PCIE_CFG :: VPD_INTERFACE :: RESERVED_0 [31:01] */ +#define PCIE_CFG_VPD_INTERFACE_RESERVED_0_MASK 0xfffffffe +#define PCIE_CFG_VPD_INTERFACE_RESERVED_0_ALIGN 0 +#define PCIE_CFG_VPD_INTERFACE_RESERVED_0_BITS 31 +#define PCIE_CFG_VPD_INTERFACE_RESERVED_0_SHIFT 1 + +/* PCIE_CFG :: VPD_INTERFACE :: VPD_REQUEST [00:00] */ +#define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_MASK 0x00000001 +#define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_ALIGN 0 +#define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_BITS 1 +#define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER + ***************************************************************************/ +/* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_ALIGN 0 +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_BITS 32 +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER + ***************************************************************************/ +/* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_ALIGN 0 +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_BITS 32 +#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER + ***************************************************************************/ +/* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_ALIGN 0 +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_BITS 32 +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER + ***************************************************************************/ +/* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_ALIGN 0 +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_BITS 32 +#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER + ***************************************************************************/ +/* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_ALIGN 0 +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_BITS 32 +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER + ***************************************************************************/ +/* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_ALIGN 0 +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_BITS 32 +#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: INT_MAILBOX_UPPER + ***************************************************************************/ +/* PCIE_CFG :: INT_MAILBOX_UPPER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ +#define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff +#define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_ALIGN 0 +#define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_BITS 32 +#define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: INT_MAILBOX_LOWER + ***************************************************************************/ +/* PCIE_CFG :: INT_MAILBOX_LOWER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ +#define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff +#define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_ALIGN 0 +#define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_BITS 32 +#define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION + ***************************************************************************/ +/* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: RESERVED_0 [31:28] */ +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_MASK 0xf0000000 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_ALIGN 0 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_BITS 4 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_SHIFT 28 + +/* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: PRODUCT_ID [27:08] */ +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_MASK 0x0fffff00 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_ALIGN 0 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_BITS 20 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_SHIFT 8 + +/* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: ASIC_REVISION_ID [07:00] */ +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_MASK 0x000000ff +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_ALIGN 0 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_BITS 8 +#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FUNCTION_EVENT + ***************************************************************************/ +/* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_0 [31:16] */ +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_MASK 0xffff0000 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_BITS 16 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: FUNCTION_EVENT :: INTA_EVENT [15:15] */ +#define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_MASK 0x00008000 +#define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_BITS 1 +#define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_SHIFT 15 + +/* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_1 [14:05] */ +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_MASK 0x00007fe0 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_BITS 10 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_SHIFT 5 + +/* PCIE_CFG :: FUNCTION_EVENT :: GWAKE_EVENT [04:04] */ +#define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_MASK 0x00000010 +#define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_BITS 1 +#define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_SHIFT 4 + +/* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_2 [03:00] */ +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_MASK 0x0000000f +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_BITS 4 +#define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FUNCTION_EVENT_MASK + ***************************************************************************/ +/* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_0 [31:16] */ +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_MASK 0xffff0000 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_BITS 16 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: FUNCTION_EVENT_MASK :: INTA_MASK [15:15] */ +#define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_MASK 0x00008000 +#define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_BITS 1 +#define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_SHIFT 15 + +/* PCIE_CFG :: FUNCTION_EVENT_MASK :: WAKE_UP_MASK [14:14] */ +#define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_MASK 0x00004000 +#define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_BITS 1 +#define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_SHIFT 14 + +/* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_1 [13:05] */ +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_MASK 0x00003fe0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_BITS 9 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_SHIFT 5 + +/* PCIE_CFG :: FUNCTION_EVENT_MASK :: GWAKE_MASK [04:04] */ +#define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_MASK 0x00000010 +#define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_BITS 1 +#define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_SHIFT 4 + +/* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_2 [03:00] */ +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_MASK 0x0000000f +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_ALIGN 0 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_BITS 4 +#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FUNCTION_PRESENT + ***************************************************************************/ +/* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_0 [31:16] */ +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_MASK 0xffff0000 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_ALIGN 0 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_BITS 16 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_SHIFT 16 + +/* PCIE_CFG :: FUNCTION_PRESENT :: INTA_STATUS [15:15] */ +#define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_MASK 0x00008000 +#define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_ALIGN 0 +#define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_BITS 1 +#define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_SHIFT 15 + +/* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_1 [14:05] */ +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_MASK 0x00007fe0 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_ALIGN 0 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_BITS 10 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_SHIFT 5 + +/* PCIE_CFG :: FUNCTION_PRESENT :: PME_STATUS [04:04] */ +#define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_MASK 0x00000010 +#define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_ALIGN 0 +#define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_BITS 1 +#define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_SHIFT 4 + +/* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_2 [03:00] */ +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_MASK 0x0000000f +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_ALIGN 0 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_BITS 4 +#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PCIE_CAPABILITIES + ***************************************************************************/ +/* PCIE_CFG :: PCIE_CAPABILITIES :: RESERVED_0 [31:30] */ +#define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_MASK 0xc0000000 +#define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_BITS 2 +#define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_SHIFT 30 + +/* PCIE_CFG :: PCIE_CAPABILITIES :: INTERRUPT_MESSAGE_NUMBER [29:25] */ +#define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_MASK 0x3e000000 +#define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_BITS 5 +#define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_SHIFT 25 + +/* PCIE_CFG :: PCIE_CAPABILITIES :: SLOT_IMPLEMENTED [24:24] */ +#define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_MASK 0x01000000 +#define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_BITS 1 +#define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_SHIFT 24 + +/* PCIE_CFG :: PCIE_CAPABILITIES :: DEVICE_PORT_TYPE [23:20] */ +#define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_MASK 0x00f00000 +#define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_BITS 4 +#define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_SHIFT 20 + +/* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_VERSION [19:16] */ +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_MASK 0x000f0000 +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_BITS 4 +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_SHIFT 16 + +/* PCIE_CFG :: PCIE_CAPABILITIES :: NEXT_POINTER [15:08] */ +#define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_MASK 0x0000ff00 +#define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_BITS 8 +#define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_SHIFT 8 + +/* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_ID [07:00] */ +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_MASK 0x000000ff +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_BITS 8 +#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_CAPABILITIES + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_0 [31:28] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_MASK 0xf0000000 +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_BITS 4 +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_SHIFT 28 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_SCALE [27:26] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_MASK 0x0c000000 +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_BITS 2 +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_SHIFT 26 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_VALUE [25:18] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_MASK 0x03fc0000 +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_BITS 8 +#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_SHIFT 18 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_1 [17:16] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_MASK 0x00030000 +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_BITS 2 +#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_SHIFT 16 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: ROLE_BASED_ERROR_SUPPORT [15:15] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_MASK 0x00008000 +#define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_BITS 1 +#define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_SHIFT 15 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: POWER_INDICATOR_PRESENT [14:14] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_MASK 0x00004000 +#define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_BITS 1 +#define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_SHIFT 14 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_INDICATOR_PRESENT [13:13] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_MASK 0x00002000 +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_BITS 1 +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_SHIFT 13 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_BUTTON_PRESENT [12:12] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_MASK 0x00001000 +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_BITS 1 +#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_SHIFT 12 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L1_ACCEPTABLE_LATENCY [11:09] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_MASK 0x00000e00 +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_BITS 3 +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_SHIFT 9 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L0S_ACCEPTABLE_LATENCY [08:06] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0 +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_BITS 3 +#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_SHIFT 6 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: EXTENDED_TAG_FIELD_SUPPORTED [05:05] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_MASK 0x00000020 +#define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_BITS 1 +#define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_SHIFT 5 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: PHANTOM_FUNCTIONS_SUPPORTED [04:03] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_MASK 0x00000018 +#define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_BITS 2 +#define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_SHIFT 3 + +/* PCIE_CFG :: DEVICE_CAPABILITIES :: MAX_PAYLOAD_SIZE_SUPPORTED [02:00] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_MASK 0x00000007 +#define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_BITS 3 +#define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_STATUS_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_0 [31:22] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_MASK 0xffc00000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_BITS 10 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_SHIFT 22 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: TRANSACTION_PENDING [21:21] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_MASK 0x00200000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_SHIFT 21 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_DETECTED [20:20] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_MASK 0x00100000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_SHIFT 20 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_DETECTED [19:19] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_MASK 0x00080000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_SHIFT 19 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_DETECTED [18:18] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_MASK 0x00040000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_SHIFT 18 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_DETECTED [17:17] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_MASK 0x00020000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_SHIFT 17 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_DETECTED [16:16] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_MASK 0x00010000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_SHIFT 16 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_1 [15:15] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_MASK 0x00008000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_SHIFT 15 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_READ_REQUEST_SIZE [14:12] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_MASK 0x00007000 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_BITS 3 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_SHIFT 12 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLE_NO_SNOOP [11:11] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_MASK 0x00000800 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_SHIFT 11 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_PM_ENABLE [10:10] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_MASK 0x00000400 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_SHIFT 10 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: PHANTOM_FUNCTIONS_ENABLE [09:09] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_MASK 0x00000200 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_SHIFT 9 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: EXTENDED_TAG_FIELD_ENABLE [08:08] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_MASK 0x00000100 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_SHIFT 8 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_PAYLOAD_SIZE [07:05] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_MASK 0x000000e0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_BITS 3 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_SHIFT 5 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLED_RELAXED_ORDERING [04:04] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_MASK 0x00000010 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_SHIFT 4 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_REPORTING_ENABLE [03:03] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_MASK 0x00000008 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_SHIFT 3 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_REPORTING_ENABLED [02:02] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000004 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_SHIFT 2 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_REPORTING_ENABLED [01:01] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000002 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_SHIFT 1 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_REPORTING_ENABLED [00:00] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_MASK 0x00000001 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: LINK_CAPABILITY + ***************************************************************************/ +/* PCIE_CFG :: LINK_CAPABILITY :: PORT_NUMBER [31:24] */ +#define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_MASK 0xff000000 +#define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_BITS 8 +#define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_SHIFT 24 + +/* PCIE_CFG :: LINK_CAPABILITY :: RESERVED_0 [23:19] */ +#define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_MASK 0x00f80000 +#define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_BITS 5 +#define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_SHIFT 19 + +/* PCIE_CFG :: LINK_CAPABILITY :: CLOCK_POWER_MANAGEMENT [18:18] */ +#define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_MASK 0x00040000 +#define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_BITS 1 +#define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_SHIFT 18 + +/* PCIE_CFG :: LINK_CAPABILITY :: L1_EXIT_LATENCY [17:15] */ +#define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_MASK 0x00038000 +#define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_BITS 3 +#define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_SHIFT 15 + +/* PCIE_CFG :: LINK_CAPABILITY :: L0S_EXIT_LATENCY [14:12] */ +#define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_MASK 0x00007000 +#define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_BITS 3 +#define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_SHIFT 12 + +/* PCIE_CFG :: LINK_CAPABILITY :: ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT [11:10] */ +#define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_MASK 0x00000c00 +#define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_BITS 2 +#define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_SHIFT 10 + +/* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_WIDTH [09:04] */ +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_MASK 0x000003f0 +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_BITS 6 +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_SHIFT 4 + +/* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_SPEED [03:00] */ +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_MASK 0x0000000f +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_BITS 4 +#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: LINK_STATUS_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_0 [31:29] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_MASK 0xe0000000 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_BITS 3 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_SHIFT 29 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: SLOT_CLOCK_CONFIGURATION [28:28] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_MASK 0x10000000 +#define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_SHIFT 28 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_1 [27:26] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_MASK 0x0c000000 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_BITS 2 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_SHIFT 26 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: NEGOTIATED_LINK_WIDTH [25:20] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x03f00000 +#define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_BITS 6 +#define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: LINK_SPEED [19:16] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_MASK 0x000f0000 +#define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_BITS 4 +#define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_SHIFT 16 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_2 [15:09] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_MASK 0x0000fe00 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_BITS 7 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_SHIFT 9 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: CLOCK_REQUEST_ENABLE [08:08] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_MASK 0x00000100 +#define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_SHIFT 8 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: EXTENDED_SYNCH [07:07] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_MASK 0x00000080 +#define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_SHIFT 7 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: COMMON_CLOCK_CONFIGURATION [06:06] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_MASK 0x00000040 +#define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_SHIFT 6 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_3 [05:05] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_MASK 0x00000020 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_SHIFT 5 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_4 [04:04] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_MASK 0x00000010 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_SHIFT 4 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: READ_COMPLETION_BOUNDARY [03:03] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_MASK 0x00000008 +#define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_SHIFT 3 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_5 [02:02] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_MASK 0x00000004 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_BITS 1 +#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_SHIFT 2 + +/* PCIE_CFG :: LINK_STATUS_CONTROL :: ACTIVE_STATE_POWER_MANAGEMENT_CONTROL [01:00] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_MASK 0x00000003 +#define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_BITS 2 +#define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_CAPABILITIES_2 + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: RESERVED_0 [31:05] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_MASK 0xffffffe0 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_BITS 27 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_SHIFT 5 + +/* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_DISABLE_SUPPORTED [04:04] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_MASK 0x00000010 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_BITS 1 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_SHIFT 4 + +/* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_TIMEOUT_RANGE_SUPPORTED [03:00] */ +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000f +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_ALIGN 0 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_BITS 4 +#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_STATUS_CONTROL_2 + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: RESERVED_0 [31:05] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffe0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_BITS 27 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_SHIFT 5 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_DISABLE [04:04] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_MASK 0x00000010 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_BITS 1 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_SHIFT 4 + +/* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_VALUE [03:00] */ +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_MASK 0x0000000f +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_ALIGN 0 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_BITS 4 +#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: LINK_CAPABILITIES_2 + ***************************************************************************/ +/* PCIE_CFG :: LINK_CAPABILITIES_2 :: RESERVED_0 [31:00] */ +#define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_MASK 0xffffffff +#define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_ALIGN 0 +#define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_BITS 32 +#define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: LINK_STATUS_CONTROL_2 + ***************************************************************************/ +/* PCIE_CFG :: LINK_STATUS_CONTROL_2 :: RESERVED_0 [31:00] */ +#define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffff +#define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_ALIGN 0 +#define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_BITS 32 +#define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER + ***************************************************************************/ +/* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 + +/* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 + +/* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 +#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS + ***************************************************************************/ +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:21] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffe00000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_BITS 11 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 21 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNSUPPORTED_REQUEST_ERROR_STATUS [20:20] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_MASK 0x00100000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_SHIFT 20 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: ECRC_ERROR_STATUS [19:19] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_MASK 0x00080000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_SHIFT 19 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: MALFORMED_TLP_STATUS [18:18] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_MASK 0x00040000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_SHIFT 18 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RECEIVER_OVERFLOW_STATUS [17:17] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_MASK 0x00020000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_SHIFT 17 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNEXPECTED_COMPLETION_STATUS [16:16] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_MASK 0x00010000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_SHIFT 16 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETER_ABORT_STATUS [15:15] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_MASK 0x00008000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_SHIFT 15 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETION_TIMEOUT_STATUS [14:14] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_MASK 0x00004000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_SHIFT 14 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR_STATUS [13:13] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_MASK 0x00002000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_SHIFT 13 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: POISONED_TLP_STATUS [12:12] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_MASK 0x00001000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_SHIFT 12 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:05] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000fe0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_BITS 7 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 5 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: DATA_LINK_PROTOCOL_ERROR_STATUS [04:04] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_MASK 0x00000010 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_SHIFT 4 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_2 [03:01] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000000e +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_BITS 3 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: TRAINING_ERROR_STATUS [00:00] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_MASK 0x00000001 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNCORRECTABLE_ERROR_MASK + ***************************************************************************/ +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_0 [31:21] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffe00000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_BITS 11 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 21 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNSUPPORTED_REQUEST_ERROR_MASK [20:20] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_MASK 0x00100000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_SHIFT 20 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: ECRC_ERROR_MASK [19:19] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_MASK 0x00080000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_SHIFT 19 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: MALFORMED_TLP_MASK [18:18] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_MASK 0x00040000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_SHIFT 18 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RECEIVER_OVERFLOW_MASK [17:17] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_MASK 0x00020000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_SHIFT 17 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNEXPECTED_COMPLETION_MASK [16:16] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_MASK 0x00010000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_SHIFT 16 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETER_ABORT_MASK [15:15] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_MASK 0x00008000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_SHIFT 15 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETION_TIMEOUT_MASK [14:14] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_MASK 0x00004000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_SHIFT 14 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: FLOW_CONTROL_PROTOCOL_ERROR_MASK [13:13] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_MASK 0x00002000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_SHIFT 13 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: POISONED_TLP_MASK [12:12] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_MASK 0x00001000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_SHIFT 12 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_1 [11:05] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000fe0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_BITS 7 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 5 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: DATA_LINK_PROTOCOL_ERROR_MASK [04:04] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_MASK 0x00000010 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_SHIFT 4 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_2 [03:01] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000000e +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_BITS 3 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: TRAINING_ERROR_MASK [00:00] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_MASK 0x00000001 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY + ***************************************************************************/ +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_0 [31:21] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_MASK 0xffe00000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_BITS 11 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_SHIFT 21 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNSUPPORTED_REQUEST_ERROR_SEVERITY [20:20] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_MASK 0x00100000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_SHIFT 20 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: ECRC_ERROR_SEVERITY [19:19] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_MASK 0x00080000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_SHIFT 19 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: MALFORMED_TLP_SEVERITY [18:18] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_MASK 0x00040000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_SHIFT 18 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RECEIVER_OVERFLOW_ERROR_SEVERITY [17:17] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_MASK 0x00020000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_SHIFT 17 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNEXPECTED_COMPLETION_ERROR_SEVERITY [16:16] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_MASK 0x00010000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_SHIFT 16 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETER_ABORT_ERROR_SEVERITY [15:15] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_MASK 0x00008000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_SHIFT 15 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETION_TIMEOUT_ERROR_SEVERITY [14:14] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_MASK 0x00004000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_SHIFT 14 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY [13:13] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_MASK 0x00002000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_SHIFT 13 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: POISONED_TLP_SEVERITY [12:12] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_MASK 0x00001000 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_SHIFT 12 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_1 [11:05] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_MASK 0x00000fe0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_BITS 7 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_SHIFT 5 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: DATA_LINK_PROTOCOL_ERROR_SEVERITY [04:04] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_MASK 0x00000010 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_SHIFT 4 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_2 [03:01] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_MASK 0x0000000e +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_BITS 3 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_SHIFT 1 + +/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: TRAINING_ERROR_SEVERITY [00:00] */ +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_MASK 0x00000001 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_ALIGN 0 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_BITS 1 +#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: CORRECTABLE_ERROR_STATUS + ***************************************************************************/ +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:14] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffffc000 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_BITS 18 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 14 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: ADVISORY_NON_FATAL_ERROR_STATUS [13:13] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_MASK 0x00002000 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_SHIFT 13 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_TIMER_TIMEOUT_STATUS [12:12] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_SHIFT 12 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:09] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000e00 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_BITS 3 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 9 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_NUM_ROLLOVER_STATUS [08:08] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_SHIFT 8 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_DLLP_STATUS [07:07] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_MASK 0x00000080 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_SHIFT 7 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_TLP_STATUS [06:06] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_MASK 0x00000040 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_SHIFT 6 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_2 [05:01] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000003e +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_BITS 5 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 + +/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RECEIVER_ERROR_STATUS [00:00] */ +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_MASK 0x00000001 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: CORRECTABLE_ERROR_MASK + ***************************************************************************/ +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_0 [31:14] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffffc000 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_BITS 18 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 14 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: ADVISORY_NON_FATAL_ERROR_MASK [13:13] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_MASK 0x00002000 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_SHIFT 13 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_TIMER_TIMEOUT_MASK [12:12] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_SHIFT 12 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_1 [11:09] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000e00 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_BITS 3 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 9 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_NUM_ROLLOVER_MASK [08:08] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_SHIFT 8 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_DLLP_MASK [07:07] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_MASK 0x00000080 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_SHIFT 7 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_TLP_MASK [06:06] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_MASK 0x00000040 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_SHIFT 6 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_2 [05:01] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000003e +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_BITS 5 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 + +/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RECEIVER_ERROR_MASK [00:00] */ +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_MASK 0x00000001 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_ALIGN 0 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_BITS 1 +#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: RESERVED_0 [31:09] */ +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_MASK 0xfffffe00 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_BITS 23 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_SHIFT 9 + +/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_ENABLE [08:08] */ +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_MASK 0x00000100 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_BITS 1 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_SHIFT 8 + +/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_CAPABLE [07:07] */ +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_MASK 0x00000080 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_BITS 1 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_SHIFT 7 + +/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_ENABLE [06:06] */ +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_MASK 0x00000040 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_BITS 1 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_SHIFT 6 + +/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_CAPABLE [05:05] */ +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_MASK 0x00000020 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_BITS 1 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_SHIFT 5 + +/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: FIRST_ERROR_POINTER [04:00] */ +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_MASK 0x0000001f +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_ALIGN 0 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_BITS 5 +#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: HEADER_LOG_1 + ***************************************************************************/ +/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_0 [31:24] */ +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_MASK 0xff000000 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_BITS 8 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_SHIFT 24 + +/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_1 [23:16] */ +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_MASK 0x00ff0000 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_BITS 8 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_SHIFT 16 + +/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_2 [15:08] */ +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_MASK 0x0000ff00 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_BITS 8 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_SHIFT 8 + +/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_3 [07:00] */ +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_MASK 0x000000ff +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_BITS 8 +#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: HEADER_LOG_2 + ***************************************************************************/ +/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_4 [31:24] */ +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_MASK 0xff000000 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_BITS 8 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_SHIFT 24 + +/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_5 [23:16] */ +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_MASK 0x00ff0000 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_BITS 8 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_SHIFT 16 + +/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_6 [15:08] */ +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_MASK 0x0000ff00 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_BITS 8 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_SHIFT 8 + +/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_7 [07:00] */ +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_MASK 0x000000ff +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_BITS 8 +#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: HEADER_LOG_3 + ***************************************************************************/ +/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_8 [31:24] */ +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_MASK 0xff000000 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_BITS 8 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_SHIFT 24 + +/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_9 [23:16] */ +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_MASK 0x00ff0000 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_BITS 8 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_SHIFT 16 + +/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_10 [15:08] */ +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_MASK 0x0000ff00 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_BITS 8 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_SHIFT 8 + +/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_11 [07:00] */ +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_MASK 0x000000ff +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_BITS 8 +#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: HEADER_LOG_4 + ***************************************************************************/ +/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_12 [31:24] */ +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_MASK 0xff000000 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_BITS 8 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_SHIFT 24 + +/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_13 [23:16] */ +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_MASK 0x00ff0000 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_BITS 8 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_SHIFT 16 + +/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_14 [15:08] */ +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_MASK 0x0000ff00 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_BITS 8 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_SHIFT 8 + +/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_15 [07:00] */ +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_MASK 0x000000ff +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_ALIGN 0 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_BITS 8 +#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER + ***************************************************************************/ +/* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 + +/* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 + +/* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 +#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PORT_VC_CAPABILITY + ***************************************************************************/ +/* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_0 [31:12] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_MASK 0xfffff000 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_BITS 20 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_SHIFT 12 + +/* PCIE_CFG :: PORT_VC_CAPABILITY :: PORT_ARBITRATION_TABLE_ENTRY_SIZE [11:10] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_MASK 0x00000c00 +#define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_BITS 2 +#define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_SHIFT 10 + +/* PCIE_CFG :: PORT_VC_CAPABILITY :: REFERENCE_CLOCK [09:08] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_MASK 0x00000300 +#define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_BITS 2 +#define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_SHIFT 8 + +/* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_1 [07:07] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_MASK 0x00000080 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_BITS 1 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_SHIFT 7 + +/* PCIE_CFG :: PORT_VC_CAPABILITY :: LOW_PRIORITY_EXTENDED_VC_COUNT [06:04] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_MASK 0x00000070 +#define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_BITS 3 +#define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_SHIFT 4 + +/* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_2 [03:03] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_MASK 0x00000008 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_BITS 1 +#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_SHIFT 3 + +/* PCIE_CFG :: PORT_VC_CAPABILITY :: EXTENDED_VC_COUNT [02:00] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_MASK 0x00000007 +#define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_BITS 3 +#define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PORT_VC_CAPABILITY_2 + ***************************************************************************/ +/* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_TABLE_OFFSET [31:24] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_BITS 8 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_SHIFT 24 + +/* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: RESERVED_0 [23:08] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_MASK 0x00ffff00 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_BITS 16 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_SHIFT 8 + +/* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_CAPABILITY [07:00] */ +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_MASK 0x000000ff +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_ALIGN 0 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_BITS 8 +#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PORT_VC_STATUS_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_0 [31:17] */ +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_MASK 0xfffe0000 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_BITS 15 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_SHIFT 17 + +/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_TABLE_STATUS [16:16] */ +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_MASK 0x00010000 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_ALIGN 0 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_BITS 1 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_SHIFT 16 + +/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_1 [15:04] */ +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_MASK 0x0000fff0 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_ALIGN 0 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_BITS 12 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_SHIFT 4 + +/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_SELECT [03:01] */ +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_MASK 0x0000000e +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_ALIGN 0 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_BITS 3 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_SHIFT 1 + +/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: LOAD_VC_ARBITRATION_TABLE [00:00] */ +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_MASK 0x00000001 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_ALIGN 0 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_BITS 1 +#define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: VC_RESOURCE_CAPABILITY + ***************************************************************************/ +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_TABLE_OFFSET [31:24] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_BITS 8 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_SHIFT 24 + +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_0 [23:23] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_MASK 0x00800000 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_BITS 1 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_SHIFT 23 + +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: MAXIMUM_TIME_SLOTS [22:16] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_MASK 0x007f0000 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_BITS 7 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_SHIFT 16 + +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: REJECT_SNOOP_TRANSACTIONS [15:15] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_MASK 0x00008000 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_BITS 1 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_SHIFT 15 + +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: ADVANCED_PACKET_SWITCHING [14:14] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_MASK 0x00004000 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_BITS 1 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_SHIFT 14 + +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_1 [13:08] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_MASK 0x00003f00 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_BITS 6 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_SHIFT 8 + +/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_CAPABILITY [07:00] */ +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_MASK 0x000000ff +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_BITS 8 +#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: VC_RESOURCE_CONTROL + ***************************************************************************/ +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ENABLE [31:31] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_MASK 0x80000000 +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_BITS 1 +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_SHIFT 31 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_0 [30:27] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_MASK 0x78000000 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_BITS 4 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_SHIFT 27 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ID [26:24] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_MASK 0x07000000 +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_BITS 3 +#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_SHIFT 24 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_1 [23:20] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_MASK 0x00f00000 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_BITS 4 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_SHIFT 20 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: PORT_ARBITRATION_SELECT [19:17] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_MASK 0x000e0000 +#define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_BITS 3 +#define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_SHIFT 17 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: LOAD_PORT_ARBITRATION_TABLE [16:16] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_MASK 0x00010000 +#define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_BITS 1 +#define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_SHIFT 16 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_2 [15:08] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_MASK 0x0000ff00 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_BITS 8 +#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_SHIFT 8 + +/* PCIE_CFG :: VC_RESOURCE_CONTROL :: TC_VC_MAP [07:00] */ +#define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_MASK 0x000000ff +#define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_BITS 8 +#define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: VC_RESOURCE_STATUS + ***************************************************************************/ +/* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_0 [31:18] */ +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_MASK 0xfffc0000 +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_BITS 14 +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_SHIFT 18 + +/* PCIE_CFG :: VC_RESOURCE_STATUS :: VC_NEGOTIATION_PENDING [17:17] */ +#define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_MASK 0x00020000 +#define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_BITS 1 +#define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_SHIFT 17 + +/* PCIE_CFG :: VC_RESOURCE_STATUS :: PORT_ARBITRATION_TABLE_STATUS [16:16] */ +#define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_MASK 0x00010000 +#define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_BITS 1 +#define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_SHIFT 16 + +/* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_1 [15:00] */ +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_MASK 0x0000ffff +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_ALIGN 0 +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_BITS 16 +#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 + +/* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 + +/* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 +#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_SERIAL_NO_LOWER_DW + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_SERIAL_NO_LOWER_DW :: SERIAL_NO_LOWER [31:00] */ +#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_MASK 0xffffffff +#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_ALIGN 0 +#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_BITS 32 +#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: DEVICE_SERIAL_NO_UPPER_DW + ***************************************************************************/ +/* PCIE_CFG :: DEVICE_SERIAL_NO_UPPER_DW :: SERIAL_NO_UPPER [31:00] */ +#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_MASK 0xffffffff +#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_ALIGN 0 +#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_BITS 32 +#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER + ***************************************************************************/ +/* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 + +/* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 + +/* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 +#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: POWER_BUDGETING_DATA_SELECT + ***************************************************************************/ +/* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: RESERVED_0 [31:08] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_MASK 0xffffff00 +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_BITS 24 +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_SHIFT 8 + +/* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: DATA_SELECT [07:00] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_MASK 0x000000ff +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_BITS 8 +#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: POWER_BUDGETING_DATA + ***************************************************************************/ +/* PCIE_CFG :: POWER_BUDGETING_DATA :: RESERVED_0 [31:21] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_MASK 0xffe00000 +#define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_BITS 11 +#define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_SHIFT 21 + +/* PCIE_CFG :: POWER_BUDGETING_DATA :: POWER_RAIL [20:18] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_MASK 0x001c0000 +#define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_BITS 3 +#define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_SHIFT 18 + +/* PCIE_CFG :: POWER_BUDGETING_DATA :: TYPE [17:15] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_MASK 0x00038000 +#define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_BITS 3 +#define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_SHIFT 15 + +/* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_STATE [14:13] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_MASK 0x00006000 +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_BITS 2 +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_SHIFT 13 + +/* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_SUB_STATE [12:10] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_MASK 0x00001c00 +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_BITS 3 +#define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_SHIFT 10 + +/* PCIE_CFG :: POWER_BUDGETING_DATA :: DATA_SCALE [09:08] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_MASK 0x00000300 +#define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_BITS 2 +#define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_SHIFT 8 + +/* PCIE_CFG :: POWER_BUDGETING_DATA :: BASE_POWER [07:00] */ +#define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_MASK 0x000000ff +#define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_BITS 8 +#define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: POWER_BUDGETING_CAPABILITY + ***************************************************************************/ +/* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: RESERVED_0 [31:01] */ +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_MASK 0xfffffffe +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_BITS 31 +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_SHIFT 1 + +/* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: LOM_CONFIGURATION [00:00] */ +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_MASK 0x00000001 +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_ALIGN 0 +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_BITS 1 +#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 + ***************************************************************************/ +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_2 [31:29] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_MASK 0xe0000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_SHIFT 29 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_2 [28:26] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_MASK 0x1c000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_SHIFT 26 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_2 [25:24] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_MASK 0x03000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_SHIFT 24 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_2 [23:16] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_MASK 0x00ff0000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_SHIFT 16 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_1 [15:13] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_MASK 0x0000e000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_SHIFT 13 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_1 [12:10] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_MASK 0x00001c00 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_SHIFT 10 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_1 [09:08] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_MASK 0x00000300 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_SHIFT 8 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_1 [07:00] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_MASK 0x000000ff +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 + ***************************************************************************/ +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_4 [31:29] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_MASK 0xe0000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_SHIFT 29 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_4 [28:26] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_MASK 0x1c000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_SHIFT 26 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_4 [25:24] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_MASK 0x03000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_SHIFT 24 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_4 [23:16] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_MASK 0x00ff0000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_SHIFT 16 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_3 [15:13] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_MASK 0x0000e000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_SHIFT 13 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_3 [12:10] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_MASK 0x00001c00 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_SHIFT 10 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_3 [09:08] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_MASK 0x00000300 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_SHIFT 8 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_3 [07:00] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_MASK 0x000000ff +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 + ***************************************************************************/ +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_6 [31:29] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_MASK 0xe0000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_SHIFT 29 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_6 [28:26] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_MASK 0x1c000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_SHIFT 26 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_6 [25:24] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_MASK 0x03000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_SHIFT 24 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_6 [23:16] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_MASK 0x00ff0000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_SHIFT 16 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_5 [15:13] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_MASK 0x0000e000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_SHIFT 13 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_5 [12:10] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_MASK 0x00001c00 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_SHIFT 10 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_5 [09:08] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_MASK 0x00000300 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_SHIFT 8 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_5 [07:00] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_MASK 0x000000ff +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 + ***************************************************************************/ +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_8 [31:29] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_MASK 0xe0000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_SHIFT 29 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_8 [28:26] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_MASK 0x1c000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_SHIFT 26 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_8 [25:24] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_MASK 0x03000000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_SHIFT 24 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_8 [23:16] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_MASK 0x00ff0000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_SHIFT 16 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_7 [15:13] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_MASK 0x0000e000 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_SHIFT 13 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_7 [12:10] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_MASK 0x00001c00 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_BITS 3 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_SHIFT 10 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_7 [09:08] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_MASK 0x00000300 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_BITS 2 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_SHIFT 8 + +/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_7 [07:00] */ +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_MASK 0x000000ff +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_ALIGN 0 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_BITS 8 +#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_SHIFT 0 + + +/**************************************************************************** + * PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING + ***************************************************************************/ +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNUSED_0 [31:07] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_MASK 0xffffff80 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_BITS 25 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_SHIFT 7 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: D3HOT_MEMORY_READ_ADVISORY_NON_FATAL [06:06] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_MASK 0x00000040 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_SHIFT 6 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: RETRY_POISON_ENABLE [05:05] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_MASK 0x00000020 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_SHIFT 5 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: POISON_ADVISORY_NON_FATAL_ENABLE [04:04] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000010 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_SHIFT 4 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNEXPECTED_ADVISORY_NON_FATAL_ENABLE [03:03] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000008 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_SHIFT 3 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE [02:02] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000004 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_SHIFT 2 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [01:01] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000002 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 1 + +/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [00:00] */ +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000001 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_BITS 1 +#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 0 + + +/**************************************************************************** + * BCM70012_TGT_TOP_PCIE_TL + ***************************************************************************/ +/**************************************************************************** + * PCIE_TL :: TL_CONTROL + ***************************************************************************/ +/* PCIE_TL :: TL_CONTROL :: RESERVED_0 [31:31] */ +#define PCIE_TL_TL_CONTROL_RESERVED_0_MASK 0x80000000 +#define PCIE_TL_TL_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_0_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_0_SHIFT 31 + +/* PCIE_TL :: TL_CONTROL :: CQ14298_FIX_ENA_N [30:30] */ +#define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_MASK 0x40000000 +#define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_ALIGN 0 +#define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_BITS 1 +#define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_SHIFT 30 + +/* PCIE_TL :: TL_CONTROL :: RESERVED_1 [29:29] */ +#define PCIE_TL_TL_CONTROL_RESERVED_1_MASK 0x20000000 +#define PCIE_TL_TL_CONTROL_RESERVED_1_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_1_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_1_SHIFT 29 + +/* PCIE_TL :: TL_CONTROL :: INTA_WAKEUP_LINK_CLKREQ_DA [28:28] */ +#define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_MASK 0x10000000 +#define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_ALIGN 0 +#define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_BITS 1 +#define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_SHIFT 28 + +/* PCIE_TL :: TL_CONTROL :: RESERVED_2 [27:27] */ +#define PCIE_TL_TL_CONTROL_RESERVED_2_MASK 0x08000000 +#define PCIE_TL_TL_CONTROL_RESERVED_2_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_2_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_2_SHIFT 27 + +/* PCIE_TL :: TL_CONTROL :: CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX [26:26] */ +#define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_MASK 0x04000000 +#define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_ALIGN 0 +#define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_BITS 1 +#define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_SHIFT 26 + +/* PCIE_TL :: TL_CONTROL :: RESERVED_3 [25:25] */ +#define PCIE_TL_TL_CONTROL_RESERVED_3_MASK 0x02000000 +#define PCIE_TL_TL_CONTROL_RESERVED_3_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_3_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_3_SHIFT 25 + +/* PCIE_TL :: TL_CONTROL :: RESERVED_4 [24:24] */ +#define PCIE_TL_TL_CONTROL_RESERVED_4_MASK 0x01000000 +#define PCIE_TL_TL_CONTROL_RESERVED_4_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_4_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_4_SHIFT 24 + +/* PCIE_TL :: TL_CONTROL :: RESERVED_5 [23:23] */ +#define PCIE_TL_TL_CONTROL_RESERVED_5_MASK 0x00800000 +#define PCIE_TL_TL_CONTROL_RESERVED_5_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_5_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_5_SHIFT 23 + +/* PCIE_TL :: TL_CONTROL :: CRC_SWAP [22:22] */ +#define PCIE_TL_TL_CONTROL_CRC_SWAP_MASK 0x00400000 +#define PCIE_TL_TL_CONTROL_CRC_SWAP_ALIGN 0 +#define PCIE_TL_TL_CONTROL_CRC_SWAP_BITS 1 +#define PCIE_TL_TL_CONTROL_CRC_SWAP_SHIFT 22 + +/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_CA_ERROR [21:21] */ +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_MASK 0x00200000 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_ALIGN 0 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_BITS 1 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_SHIFT 21 + +/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_UR_ERROR [20:20] */ +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_MASK 0x00100000 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_ALIGN 0 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_BITS 1 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_SHIFT 20 + +/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_RSV_ERROR [19:19] */ +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_MASK 0x00080000 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_ALIGN 0 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_BITS 1 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_SHIFT 19 + +/* PCIE_TL :: TL_CONTROL :: RESERVED_6 [18:18] */ +#define PCIE_TL_TL_CONTROL_RESERVED_6_MASK 0x00040000 +#define PCIE_TL_TL_CONTROL_RESERVED_6_ALIGN 0 +#define PCIE_TL_TL_CONTROL_RESERVED_6_BITS 1 +#define PCIE_TL_TL_CONTROL_RESERVED_6_SHIFT 18 + +/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_EP_ERROR [17:17] */ +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_MASK 0x00020000 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_ALIGN 0 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_BITS 1 +#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_SHIFT 17 + +/* PCIE_TL :: TL_CONTROL :: ENABLE_BYTECOUNT_CHECK [16:16] */ +#define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_MASK 0x00010000 +#define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_ALIGN 0 +#define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_BITS 1 +#define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_SHIFT 16 + +/* PCIE_TL :: TL_CONTROL :: NOT_USED [15:14] */ +#define PCIE_TL_TL_CONTROL_NOT_USED_MASK 0x0000c000 +#define PCIE_TL_TL_CONTROL_NOT_USED_ALIGN 0 +#define PCIE_TL_TL_CONTROL_NOT_USED_BITS 2 +#define PCIE_TL_TL_CONTROL_NOT_USED_SHIFT 14 + +/* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DR [13:11] */ +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_MASK 0x00003800 +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_ALIGN 0 +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_BITS 3 +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_SHIFT 11 + +/* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DW [10:08] */ +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_MASK 0x00000700 +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_ALIGN 0 +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_BITS 3 +#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_SHIFT 8 + +/* PCIE_TL :: TL_CONTROL :: NOT_USED_0 [07:06] */ +#define PCIE_TL_TL_CONTROL_NOT_USED_0_MASK 0x000000c0 +#define PCIE_TL_TL_CONTROL_NOT_USED_0_ALIGN 0 +#define PCIE_TL_TL_CONTROL_NOT_USED_0_BITS 2 +#define PCIE_TL_TL_CONTROL_NOT_USED_0_SHIFT 6 + +/* PCIE_TL :: TL_CONTROL :: NOT_USED_1 [05:00] */ +#define PCIE_TL_TL_CONTROL_NOT_USED_1_MASK 0x0000003f +#define PCIE_TL_TL_CONTROL_NOT_USED_1_ALIGN 0 +#define PCIE_TL_TL_CONTROL_NOT_USED_1_BITS 6 +#define PCIE_TL_TL_CONTROL_NOT_USED_1_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: TRANSACTION_CONFIGURATION + ***************************************************************************/ +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_RETRY_BUFFER_TIMING_MOD [31:31] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_MASK 0x80000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_SHIFT 31 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_0 [30:30] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_MASK 0x40000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_SHIFT 30 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_SINGLE_SHOT_ENABLE [29:29] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_MASK 0x20000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_SHIFT 29 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_1 [28:28] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_MASK 0x10000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_SHIFT 28 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: SELECT_CORE_CLOCK_OVERRIDE [27:27] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_MASK 0x08000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_SHIFT 27 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: CQ9139_FIX_ENABLE [26:26] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_MASK 0x04000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_SHIFT 26 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CMPT_PWR_CHECK [25:25] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_MASK 0x02000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_SHIFT 25 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12696_FIX [24:24] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_MASK 0x01000000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_SHIFT 24 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: DEVICE_SERIAL_NO_OVERRIDE [23:23] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_MASK 0x00800000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_SHIFT 23 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12455_FIX [22:22] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_MASK 0x00400000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_SHIFT 22 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_TC_VC_FILTERING_CHECK [21:21] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_MASK 0x00200000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_SHIFT 21 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: DONT_GEN_HOT_PLUG_MSG [20:20] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_MASK 0x00100000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_SHIFT 20 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: IGNORE_HOTPLUG_MSG [19:19] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_MASK 0x00080000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_SHIFT 19 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_MULTMSG_CAPABLE [18:16] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_MASK 0x00070000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_BITS 3 +#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_SHIFT 16 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: DATA_SELECT_LIMIT [15:12] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_MASK 0x0000f000 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_BITS 4 +#define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_SHIFT 12 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_PL [11:11] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_MASK 0x00000800 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_SHIFT 11 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_DL [10:10] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_MASK 0x00000400 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_SHIFT 10 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_TL [09:09] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_MASK 0x00000200 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_SHIFT 9 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_2 [08:07] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_MASK 0x00000180 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_BITS 2 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_SHIFT 7 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: PCIE_POWER_BUDGET_CAP_ENABLE [06:06] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_MASK 0x00000040 +#define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_SHIFT 6 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: LOM_CONFIGURATION [05:05] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_MASK 0x00000020 +#define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_SHIFT 5 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: CONCATE_SELECT [04:04] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_MASK 0x00000010 +#define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_SHIFT 4 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_3 [03:03] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_MASK 0x00000008 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_SHIFT 3 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9468_FIX [02:02] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_MASK 0x00000004 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_SHIFT 2 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: POWER_STATE_WRITE_MEM_ENABLE [01:01] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_MASK 0x00000002 +#define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_SHIFT 1 + +/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9709_ENABLE [00:00] */ +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_MASK 0x00000001 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_ALIGN 0 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_BITS 1 +#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: RESERVED_0 [31:00] */ +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_MASK 0xffffffff +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_BITS 32 +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 + ***************************************************************************/ +/* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 :: RESERVED_0 [31:00] */ +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_MASK 0xffffffff +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_ALIGN 0 +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_BITS 32 +#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: REG_MADDR_UPR [31:00] */ +#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_MASK 0xffffffff +#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_BITS 32 +#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 + ***************************************************************************/ +/* PCIE_TL :: DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 :: REG_MADDR_LWR [31:00] */ +#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_MASK 0xffffffff +#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_BITS 32 +#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: REG_MLEN_BE [31:24] */ +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_MASK 0xff000000 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_BITS 8 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_SHIFT 24 + +/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_FIRST_DW_BYTE_ENABLES [23:20] */ +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_MASK 0x00f00000 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_BITS 4 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_SHIFT 20 + +/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_LAST_DW_BYTE_ENABLES [19:16] */ +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_MASK 0x000f0000 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_BITS 4 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_SHIFT 16 + +/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: RESERVED_0 [15:11] */ +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_MASK 0x0000f800 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_BITS 5 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_SHIFT 11 + +/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_DW_LENGTH [10:00] */ +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_MASK 0x000007ff +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_BITS 11 +#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: REG_MTAG_ATTR [31:19] */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_MASK 0xfff80000 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_BITS 13 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_SHIFT 19 + +/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_FUNCTION [18:16] */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_MASK 0x00070000 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_BITS 3 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_SHIFT 16 + +/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_0 [15:13] */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_BITS 3 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_SHIFT 13 + +/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_ATTRIBUTES [12:08] */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_MASK 0x00001f00 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_BITS 5 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_SHIFT 8 + +/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_1 [07:05] */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_BITS 3 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_SHIFT 5 + +/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_TAG [04:00] */ +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_MASK 0x0000001f +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_ALIGN 0 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_BITS 5 +#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: REG_SPLIT_ID [31:16] */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_MASK 0xffff0000 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_BITS 16 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_SHIFT 16 + +/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_0 [15:13] */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_BITS 3 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_SHIFT 13 + +/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_ATTRIBUTES [12:11] */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_MASK 0x00001800 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_BITS 2 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_SHIFT 11 + +/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TC [10:08] */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_MASK 0x00000700 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_BITS 3 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_SHIFT 8 + +/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_1 [07:05] */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_BITS 3 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_SHIFT 5 + +/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TAG [04:00] */ +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_MASK 0x0000001f +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_BITS 5 +#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: REG_SPLIT_LEN [31:13] */ +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_MASK 0xffffe000 +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_BITS 19 +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_SHIFT 13 + +/* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: READ_DMA_SPLIT_INITIAL_BYTE_COUNT [12:00] */ +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_MASK 0x00001fff +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_ALIGN 0 +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_BITS 13 +#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: REG_SM_R0_R3 [31:31] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_MASK 0x80000000 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_SHIFT 31 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_DATA_STATE_MACHINE [30:28] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_MASK 0x70000000 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_BITS 3 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_SHIFT 28 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE [27:23] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_MASK 0x0f800000 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_BITS 5 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_SHIFT 23 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: RESERVED_0 [22:07] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_MASK 0x007fff80 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_BITS 16 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_SHIFT 7 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_RAW_REQUEST [06:06] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_MASK 0x00000040 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_SHIFT 6 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_RAW_REQUEST [05:05] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_MASK 0x00000020 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_SHIFT 5 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: INTERRUPT_MSG_GATED_REQUEST [04:04] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_MASK 0x00000010 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_SHIFT 4 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: MSI_DMA_GATED_REQUEST [03:03] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_MASK 0x00000008 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_SHIFT 3 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TARGET_COMPLETION_OR_MSG_GATED_REQUEST [02:02] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_MASK 0x00000004 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_SHIFT 2 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_GATED_REQUEST [01:01] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_MASK 0x00000002 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_SHIFT 1 + +/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_GATED_REQUEST [00:00] */ +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_MASK 0x00000001 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_ALIGN 0 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_BITS 1 +#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: REG_DMA_CMPT_MISC2 [31:29] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_MASK 0xe0000000 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_BITS 3 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_SHIFT 29 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_BYTE_LENGTH_REMAINING [28:16] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_MASK 0x1fff0000 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_BITS 13 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_SHIFT 16 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: NOT_USED [15:15] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_MASK 0x00008000 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_SHIFT 15 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED [14:14] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_MASK 0x00004000 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_SHIFT 14 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED [13:13] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_MASK 0x00002000 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_SHIFT 13 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1 [12:12] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_MASK 0x00001000 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_SHIFT 12 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST [11:11] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_MASK 0x00000800 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_SHIFT 11 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS [10:10] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_MASK 0x00000400 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_SHIFT 10 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_FULLY [09:09] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_MASK 0x00000200 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_SHIFT 9 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_DW_DATA_VALID_ADDRESS_ACK [08:08] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_MASK 0x00000100 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_BITS 1 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_SHIFT 8 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER [07:04] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_MASK 0x000000f0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_BITS 4 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_SHIFT 4 + +/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: FRAME_DEAD_TIME_ERROR_COUNTER [03:00] */ +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_MASK 0x0000000f +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_ALIGN 0 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_BITS 4 +#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: REG_SPLITCTL_MISC0 [31:29] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_MASK 0xe0000000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_BITS 3 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_SHIFT 29 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING [28:16] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_MASK 0x1fff0000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_BITS 13 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_SHIFT 16 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID [15:00] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_MASK 0x0000ffff +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_BITS 16 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: REG_SPLITCTL_MISC1 [31:16] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_MASK 0xffff0000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_BITS 16 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_SHIFT 16 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_0 [15:15] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_MASK 0x00008000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_BITS 1 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_SHIFT 15 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS [14:08] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_MASK 0x00007f00 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_BITS 7 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_SHIFT 8 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_1 [07:07] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_MASK 0x00000080 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_BITS 1 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_SHIFT 7 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE [06:05] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_MASK 0x00000060 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_BITS 2 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_SHIFT 5 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_TAG [04:00] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_MASK 0x0000001f +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_BITS 5 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC + ***************************************************************************/ +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: REG_SPLITCTL_MISC2 [31:31] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_MASK 0x80000000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_BITS 1 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_SHIFT 31 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS [30:30] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_MASK 0x40000000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_BITS 1 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_SHIFT 30 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_VALID_TAG [29:29] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_MASK 0x20000000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_BITS 1 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_SHIFT 29 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: UPDATED_BYTE_COUNT [28:16] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_MASK 0x1fff0000 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_BITS 13 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_SHIFT 16 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: RESERVED_0 [15:08] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_MASK 0x0000ff00 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_BITS 8 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_SHIFT 8 + +/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: SPLIT_TABLE_VALID_ARRAY [07:00] */ +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_MASK 0x000000ff +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_ALIGN 0 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_BITS 8 +#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO + ***************************************************************************/ +/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: RESERVED_0 [31:17] */ +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_MASK 0xfffe0000 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_ALIGN 0 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_BITS 15 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_SHIFT 17 + +/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: CONFIG_WRITE_INDICATER [16:16] */ +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_MASK 0x00010000 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_ALIGN 0 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_BITS 1 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_SHIFT 16 + +/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: BUS_NUMBER [15:08] */ +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_MASK 0x0000ff00 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_ALIGN 0 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_BITS 8 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_SHIFT 8 + +/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: DEVICE_NUMBER [07:03] */ +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_MASK 0x000000f8 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_ALIGN 0 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_BITS 5 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_SHIFT 3 + +/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: FUNCTION_NUMBER [02:00] */ +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_MASK 0x00000007 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_ALIGN 0 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_BITS 3 +#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_TL :: TL_DEBUG + ***************************************************************************/ +/* PCIE_TL :: TL_DEBUG :: A4_DEVICE_INDICATION_BIT [31:31] */ +#define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_MASK 0x80000000 +#define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_ALIGN 0 +#define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_BITS 1 +#define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_SHIFT 31 + +/* PCIE_TL :: TL_DEBUG :: B1_DEVICE_INDICATION_BIT [30:30] */ +#define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_MASK 0x40000000 +#define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_ALIGN 0 +#define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_BITS 1 +#define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_SHIFT 30 + +/* PCIE_TL :: TL_DEBUG :: RESERVED_0 [29:00] */ +#define PCIE_TL_TL_DEBUG_RESERVED_0_MASK 0x3fffffff +#define PCIE_TL_TL_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_TL_TL_DEBUG_RESERVED_0_BITS 30 +#define PCIE_TL_TL_DEBUG_RESERVED_0_SHIFT 0 + + +/**************************************************************************** + * BCM70012_TGT_TOP_PCIE_DLL + ***************************************************************************/ +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_CONTROL + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_0 [31:30] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_MASK 0xc0000000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_BITS 2 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_SHIFT 30 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: CQ28001_FIX_ENABLE [29:29] */ +#define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_MASK 0x20000000 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_SHIFT 29 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: CQ27820_FIX_ENABLE [28:28] */ +#define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_MASK 0x10000000 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_SHIFT 28 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: ASPM_L1_ENABLE [27:27] */ +#define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_MASK 0x08000000 +#define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_SHIFT 27 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_1 [26:25] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_MASK 0x06000000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_BITS 2 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_SHIFT 25 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: CQ11211 [24:24] */ +#define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_MASK 0x01000000 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_SHIFT 24 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_2 [23:23] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_MASK 0x00800000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_SHIFT 23 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_3 [22:22] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_MASK 0x00400000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_SHIFT 22 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_4 [21:21] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_MASK 0x00200000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_SHIFT 21 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_5 [20:20] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_MASK 0x00100000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_SHIFT 20 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_6 [19:19] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_MASK 0x00080000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_SHIFT 19 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: PLL_REFSEL_SWITCH_CONTROL_CQ11011 [18:18] */ +#define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_MASK 0x00040000 +#define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_SHIFT 18 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_7 [17:17] */ +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_MASK 0x00020000 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_SHIFT 17 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL [16:16] */ +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_MASK 0x00010000 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_SHIFT 16 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_TRANSMITTER [15:15] */ +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_MASK 0x00008000 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_SHIFT 15 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_PLL [14:14] */ +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_MASK 0x00004000 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_SHIFT 14 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_RECEIVER [13:13] */ +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_MASK 0x00002000 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_SHIFT 13 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_BEACON [12:12] */ +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_MASK 0x00001000 +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_SHIFT 12 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: AUTOMATIC_TIMER_THRESHOLD_ENABLE [11:11] */ +#define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_MASK 0x00000800 +#define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_SHIFT 11 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_DLLP_TIMEOUT_MECHANISM [10:10] */ +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_MASK 0x00000400 +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_SHIFT 10 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: CHECK_RECEIVE_FLOW_CONTROL_CREDITS [09:09] */ +#define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_MASK 0x00000200 +#define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_SHIFT 9 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: LINK_ENABLE [08:08] */ +#define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_MASK 0x00000100 +#define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_BITS 1 +#define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_SHIFT 8 + +/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL_2 [07:00] */ +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_MASK 0x000000ff +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_ALIGN 0 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_BITS 8 +#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_STATUS + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_0 [31:26] */ +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_MASK 0xfc000000 +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_BITS 6 +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_SHIFT 26 + +/* PCIE_DLL :: DATA_LINK_STATUS :: PHY_LINK_STATE [25:23] */ +#define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_MASK 0x03800000 +#define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_BITS 3 +#define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_SHIFT 23 + +/* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_STATE [22:19] */ +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_MASK 0x00780000 +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_BITS 4 +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_SHIFT 19 + +/* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_SUB_STATE [18:17] */ +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_MASK 0x00060000 +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_BITS 2 +#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_SHIFT 17 + +/* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_UP [16:16] */ +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_MASK 0x00010000 +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_SHIFT 16 + +/* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_1 [15:11] */ +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_MASK 0x0000f800 +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_BITS 5 +#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_SHIFT 11 + +/* PCIE_DLL :: DATA_LINK_STATUS :: PME_TURN_OFF_STATUS_IN_D0 [10:10] */ +#define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_MASK 0x00000400 +#define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_SHIFT 10 + +/* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_UPDATE_TIMEOUT [09:09] */ +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_MASK 0x00000200 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_SHIFT 9 + +/* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_RECEIVE_OVERFLOW [08:08] */ +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_MASK 0x00000100 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_SHIFT 8 + +/* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR [07:07] */ +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_MASK 0x00000080 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_SHIFT 7 + +/* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_PROTOCOL_ERROR [06:06] */ +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_MASK 0x00000040 +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_SHIFT 6 + +/* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_ROLLOVER [05:05] */ +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_MASK 0x00000020 +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_SHIFT 5 + +/* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_TIMEOUT [04:04] */ +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_MASK 0x00000010 +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_SHIFT 4 + +/* PCIE_DLL :: DATA_LINK_STATUS :: NAK_RECEIVED [03:03] */ +#define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_MASK 0x00000008 +#define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_SHIFT 3 + +/* PCIE_DLL :: DATA_LINK_STATUS :: DLLP_ERROR [02:02] */ +#define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_MASK 0x00000004 +#define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_SHIFT 2 + +/* PCIE_DLL :: DATA_LINK_STATUS :: BAD_TLP_SEQUENCE_NUMBER [01:01] */ +#define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_MASK 0x00000002 +#define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_SHIFT 1 + +/* PCIE_DLL :: DATA_LINK_STATUS :: TLP_ERROR [00:00] */ +#define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_MASK 0x00000001 +#define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_BITS 1 +#define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_ATTENTION + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_ATTENTION :: RESERVED_0 [31:06] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_MASK 0xffffffc0 +#define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_BITS 26 +#define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_SHIFT 6 + +/* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_PACKET_TEST_INDICATOR [05:05] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_MASK 0x00000020 +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_SHIFT 5 + +/* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR [04:04] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_MASK 0x00000010 +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_SHIFT 4 + +/* PCIE_DLL :: DATA_LINK_ATTENTION :: NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR [03:03] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_MASK 0x00000008 +#define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_SHIFT 3 + +/* PCIE_DLL :: DATA_LINK_ATTENTION :: DLLP_ERROR_COUNTER_ATTENTION_INDICATOR [02:02] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000004 +#define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 2 + +/* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR [01:01] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_MASK 0x00000002 +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_SHIFT 1 + +/* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_ERROR_COUNTER_ATTENTION_INDICATOR [00:00] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000001 +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_ATTENTION_MASK + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: RESERVED_0 [31:08] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_BITS 24 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_SHIFT 8 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: UNUSED_0 [07:06] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_MASK 0x000000c0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_BITS 2 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_SHIFT 6 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK [05:05] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_MASK 0x00000020 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_SHIFT 5 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_ERROR_ATTENTION_MASK [04:04] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_MASK 0x00000010 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_SHIFT 4 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: NAK_RECEIVED_COUNTER_ATTENTION_MASK [03:03] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_MASK 0x00000008 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_SHIFT 3 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DLLP_ERROR_COUNTER_ATTENTION_MASK [02:02] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000004 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 2 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK [01:01] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_MASK 0x00000002 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_SHIFT 1 + +/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_ERROR_COUNTER_ATTENTION_MASK [00:00] */ +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000001 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_BITS 1 +#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 + +/* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: NEXT_TRANSMIT_SEQUENCE_NUMBER [11:00] */ +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_BITS 12 +#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 + +/* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_BITS 12 +#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 + +/* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: PURGED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_BITS 12 +#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 + +/* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RECEIVE_SEQUENCE_NUMBER [11:00] */ +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_MASK 0x00000fff +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_ALIGN 0 +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_BITS 12 +#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_REPLAY + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_REPLAY :: RESERVED_0 [31:23] */ +#define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_MASK 0xff800000 +#define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_BITS 9 +#define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_SHIFT 23 + +/* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_TIMEOUT_VALUE [22:10] */ +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_MASK 0x007ffc00 +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_BITS 13 +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_SHIFT 10 + +/* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_BUFFER_SIZE [09:00] */ +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_MASK 0x000003ff +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_BITS 10 +#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_ACK_TIMEOUT + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: RESERVED_0 [31:11] */ +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_MASK 0xfffff800 +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_BITS 21 +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_SHIFT 11 + +/* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: ACK_LATENCY_TIMEOUT_VALUE [10:00] */ +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_MASK 0x000007ff +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_BITS 11 +#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD + ***************************************************************************/ +/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: RESERVED_0 [31:24] */ +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_MASK 0xff000000 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_ALIGN 0 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_BITS 8 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_SHIFT 24 + +/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0_STAY_TIME [23:20] */ +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_MASK 0x00f00000 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_ALIGN 0 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_BITS 4 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_SHIFT 20 + +/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_STAY_TIME [19:16] */ +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_MASK 0x000f0000 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_ALIGN 0 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_BITS 4 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_SHIFT 16 + +/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_THRESHOLD [15:08] */ +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_MASK 0x0000ff00 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_ALIGN 0 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_BITS 8 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_SHIFT 8 + +/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0S_THRESHOLD [07:00] */ +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_MASK 0x000000ff +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_ALIGN 0 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_BITS 8 +#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RESERVED_0 [31:11] */ +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_BITS 21 +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_SHIFT 11 + +/* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RETRY_BUFFER_WRITE_POINTER [10:00] */ +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_MASK 0x000007ff +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_BITS 11 +#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RESERVED_0 [31:11] */ +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_BITS 21 +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_SHIFT 11 + +/* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RETRY_BUFFER_READ_POINTER [10:00] */ +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_MASK 0x000007ff +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_BITS 11 +#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG + ***************************************************************************/ +/* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RESERVED_0 [31:11] */ +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_BITS 21 +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_SHIFT 11 + +/* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RETRY_BUFFER_PURGED_POINTER [10:00] */ +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_MASK 0x000007ff +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_BITS 11 +#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: RETRY_BUFFER_READ_WRITE_DEBUG_PORT + ***************************************************************************/ +/* PCIE_DLL :: RETRY_BUFFER_READ_WRITE_DEBUG_PORT :: RETRY_BUFFER_DATA [31:00] */ +#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_MASK 0xffffffff +#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_ALIGN 0 +#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_BITS 32 +#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: ERROR_COUNT_THRESHOLD + ***************************************************************************/ +/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: RESERVED_0 [31:15] */ +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_MASK 0xffff8000 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_ALIGN 0 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_BITS 17 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_SHIFT 15 + +/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD [14:12] */ +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_MASK 0x00007000 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_ALIGN 0 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_BITS 3 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_SHIFT 12 + +/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: NAK_RECEIVED_COUNT_THRESHOLD [11:08] */ +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_MASK 0x00000f00 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_ALIGN 0 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_BITS 4 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_SHIFT 8 + +/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: DLLP_ERROR_COUNT_THRESHOLD [07:04] */ +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_MASK 0x000000f0 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_ALIGN 0 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_BITS 4 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_SHIFT 4 + +/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: TLP_ERROR_COUNT_THRESHOLD [03:00] */ +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_MASK 0x0000000f +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_ALIGN 0 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_BITS 4 +#define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: TL_ERROR_COUNTER + ***************************************************************************/ +/* PCIE_DLL :: TL_ERROR_COUNTER :: RESERVED_0 [31:24] */ +#define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_MASK 0xff000000 +#define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_ALIGN 0 +#define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_BITS 8 +#define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_SHIFT 24 + +/* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_BAD_SEQUENCE_NUMBER_COUNTER [23:16] */ +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_MASK 0x00ff0000 +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_ALIGN 0 +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_BITS 8 +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_SHIFT 16 + +/* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_ERROR_COUNTER [15:00] */ +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_MASK 0x0000ffff +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_ALIGN 0 +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_BITS 16 +#define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DLLP_ERROR_COUNTER + ***************************************************************************/ +/* PCIE_DLL :: DLLP_ERROR_COUNTER :: RESERVED_0 [31:16] */ +#define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 +#define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_BITS 16 +#define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_SHIFT 16 + +/* PCIE_DLL :: DLLP_ERROR_COUNTER :: DLLP_ERROR_COUNTER [15:00] */ +#define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_MASK 0x0000ffff +#define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_ALIGN 0 +#define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_BITS 16 +#define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: NAK_RECEIVED_COUNTER + ***************************************************************************/ +/* PCIE_DLL :: NAK_RECEIVED_COUNTER :: RESERVED_0 [31:16] */ +#define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_MASK 0xffff0000 +#define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_ALIGN 0 +#define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_BITS 16 +#define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_SHIFT 16 + +/* PCIE_DLL :: NAK_RECEIVED_COUNTER :: NAK_RECEIVED_COUNTER [15:00] */ +#define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_MASK 0x0000ffff +#define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_ALIGN 0 +#define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_BITS 16 +#define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: DATA_LINK_TEST + ***************************************************************************/ +/* PCIE_DLL :: DATA_LINK_TEST :: RESERVED_0 [31:16] */ +#define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_MASK 0xffff0000 +#define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_BITS 16 +#define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_SHIFT 16 + +/* PCIE_DLL :: DATA_LINK_TEST :: STORE_RECEIVE_TLPS [15:15] */ +#define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_MASK 0x00008000 +#define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_SHIFT 15 + +/* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_TLPS [14:14] */ +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_MASK 0x00004000 +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_SHIFT 14 + +/* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_DLLPS [13:13] */ +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_MASK 0x00002000 +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_SHIFT 13 + +/* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PHY_LINK_UP [12:12] */ +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_MASK 0x00001000 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_SHIFT 12 + +/* PCIE_DLL :: DATA_LINK_TEST :: BYPASS_FLOW_CONTROL [11:11] */ +#define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_MASK 0x00000800 +#define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_SHIFT 11 + +/* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE [10:10] */ +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_MASK 0x00000400 +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_SHIFT 10 + +/* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_OVERSTRESS_TEST_MODE [09:09] */ +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_MASK 0x00000200 +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_SHIFT 9 + +/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_SLOW_CLOCK [08:08] */ +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_MASK 0x00000100 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_SHIFT 8 + +/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_COMPLETION_TIMER [07:07] */ +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_MASK 0x00000080 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_SHIFT 7 + +/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_REPLAY_TIMER [06:06] */ +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_MASK 0x00000040 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_SHIFT 6 + +/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_ACK_LATENCY_TIMER [05:05] */ +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_MASK 0x00000020 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_SHIFT 5 + +/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_PME_SERVICE_TIMER [04:04] */ +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_MASK 0x00000010 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_SHIFT 4 + +/* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PURGE [03:03] */ +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_MASK 0x00000008 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_SHIFT 3 + +/* PCIE_DLL :: DATA_LINK_TEST :: FORCE_RETRY [02:02] */ +#define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_MASK 0x00000004 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_SHIFT 2 + +/* PCIE_DLL :: DATA_LINK_TEST :: INVERT_CRC [01:01] */ +#define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_MASK 0x00000002 +#define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_SHIFT 1 + +/* PCIE_DLL :: DATA_LINK_TEST :: SEND_BAD_CRC_BIT [00:00] */ +#define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_MASK 0x00000001 +#define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_ALIGN 0 +#define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_BITS 1 +#define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: PACKET_BIST + ***************************************************************************/ +/* PCIE_DLL :: PACKET_BIST :: RESERVED_0 [31:24] */ +#define PCIE_DLL_PACKET_BIST_RESERVED_0_MASK 0xff000000 +#define PCIE_DLL_PACKET_BIST_RESERVED_0_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_RESERVED_0_BITS 8 +#define PCIE_DLL_PACKET_BIST_RESERVED_0_SHIFT 24 + +/* PCIE_DLL :: PACKET_BIST :: PACKET_CHECKER_LOCKED [23:23] */ +#define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_MASK 0x00800000 +#define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_BITS 1 +#define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_SHIFT 23 + +/* PCIE_DLL :: PACKET_BIST :: RECEIVE_MISMATCH [22:22] */ +#define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_MASK 0x00400000 +#define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_BITS 1 +#define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_SHIFT 22 + +/* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_TLP_LENGTH [21:21] */ +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_MASK 0x00200000 +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_BITS 1 +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_SHIFT 21 + +/* PCIE_DLL :: PACKET_BIST :: TLP_LENGTH [20:10] */ +#define PCIE_DLL_PACKET_BIST_TLP_LENGTH_MASK 0x001ffc00 +#define PCIE_DLL_PACKET_BIST_TLP_LENGTH_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_TLP_LENGTH_BITS 11 +#define PCIE_DLL_PACKET_BIST_TLP_LENGTH_SHIFT 10 + +/* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_IPG_LENGTH [09:09] */ +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_MASK 0x00000200 +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_BITS 1 +#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_SHIFT 9 + +/* PCIE_DLL :: PACKET_BIST :: IPG_LENGTH [08:02] */ +#define PCIE_DLL_PACKET_BIST_IPG_LENGTH_MASK 0x000001fc +#define PCIE_DLL_PACKET_BIST_IPG_LENGTH_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_IPG_LENGTH_BITS 7 +#define PCIE_DLL_PACKET_BIST_IPG_LENGTH_SHIFT 2 + +/* PCIE_DLL :: PACKET_BIST :: TRANSMIT_START [01:01] */ +#define PCIE_DLL_PACKET_BIST_TRANSMIT_START_MASK 0x00000002 +#define PCIE_DLL_PACKET_BIST_TRANSMIT_START_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_TRANSMIT_START_BITS 1 +#define PCIE_DLL_PACKET_BIST_TRANSMIT_START_SHIFT 1 + +/* PCIE_DLL :: PACKET_BIST :: ENABLE_PACKET_GENERATOR_TEST_MODE [00:00] */ +#define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_MASK 0x00000001 +#define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_ALIGN 0 +#define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_BITS 1 +#define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_SHIFT 0 + + +/**************************************************************************** + * PCIE_DLL :: LINK_PCIE_1_1_CONTROL + ***************************************************************************/ +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_CT_2_0 [31:29] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_MASK 0xe0000000 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_BITS 3 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_SHIFT 29 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_SAM_1_0 [28:27] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_MASK 0x18000000 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_BITS 2 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_SHIFT 27 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: UNUSED_0 [26:10] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_MASK 0x07fffc00 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_BITS 17 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_SHIFT 10 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: SELOCALXTAL [09:09] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_MASK 0x00000200 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_SHIFT 9 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_PLL_POWERDOWN_DISABLE [08:08] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_MASK 0x00000100 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_SHIFT 8 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_POWERDOWN_DISABLE [07:07] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_MASK 0x00000080 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_SHIFT 7 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_D3PM_CLKREQ_DISABLE [06:06] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_MASK 0x00000040 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_SHIFT 6 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_D3PM_CLKREQ_DISABLE [05:05] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_MASK 0x00000020 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_SHIFT 5 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_ASPM_CLKREQ_DISABLE [04:04] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_MASK 0x00000010 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_SHIFT 4 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_PD_W_O_CLKREQ [03:03] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_MASK 0x00000008 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_SHIFT 3 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DASPM10USTIMER [02:02] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_MASK 0x00000004 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_SHIFT 2 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFFU_EL1 [01:01] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_MASK 0x00000002 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_SHIFT 1 + +/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFLOWCTLUPDATE1_1 [00:00] */ +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_MASK 0x00000001 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_ALIGN 0 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_BITS 1 +#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_SHIFT 0 + + +/**************************************************************************** + * BCM70012_TGT_TOP_PCIE_PHY + ***************************************************************************/ +/**************************************************************************** + * PCIE_PHY :: PHY_MODE + ***************************************************************************/ +/* PCIE_PHY :: PHY_MODE :: RESERVED_0 [31:04] */ +#define PCIE_PHY_PHY_MODE_RESERVED_0_MASK 0xfffffff0 +#define PCIE_PHY_PHY_MODE_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_MODE_RESERVED_0_BITS 28 +#define PCIE_PHY_PHY_MODE_RESERVED_0_SHIFT 4 + +/* PCIE_PHY :: PHY_MODE :: UPSTREAM_DEV [03:03] */ +#define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_MASK 0x00000008 +#define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_ALIGN 0 +#define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_BITS 1 +#define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_SHIFT 3 + +/* PCIE_PHY :: PHY_MODE :: SERDES_SA_MODE [02:02] */ +#define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_MASK 0x00000004 +#define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_ALIGN 0 +#define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_BITS 1 +#define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_SHIFT 2 + +/* PCIE_PHY :: PHY_MODE :: LINK_DISABLE [01:01] */ +#define PCIE_PHY_PHY_MODE_LINK_DISABLE_MASK 0x00000002 +#define PCIE_PHY_PHY_MODE_LINK_DISABLE_ALIGN 0 +#define PCIE_PHY_PHY_MODE_LINK_DISABLE_BITS 1 +#define PCIE_PHY_PHY_MODE_LINK_DISABLE_SHIFT 1 + +/* PCIE_PHY :: PHY_MODE :: SOFT_RESET [00:00] */ +#define PCIE_PHY_PHY_MODE_SOFT_RESET_MASK 0x00000001 +#define PCIE_PHY_PHY_MODE_SOFT_RESET_ALIGN 0 +#define PCIE_PHY_PHY_MODE_SOFT_RESET_BITS 1 +#define PCIE_PHY_PHY_MODE_SOFT_RESET_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_LINK_STATUS + ***************************************************************************/ +/* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_0 [31:10] */ +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_MASK 0xfffffc00 +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_BITS 22 +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_SHIFT 10 + +/* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_OVERRUN [09:09] */ +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_MASK 0x00000200 +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_SHIFT 9 + +/* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_UNDERRUN [08:08] */ +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_MASK 0x00000100 +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_SHIFT 8 + +/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_REQUEST_LOOPBACK [07:07] */ +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_MASK 0x00000080 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_SHIFT 7 + +/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_DISABLE_SCRAMBLER [06:06] */ +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_MASK 0x00000040 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_SHIFT 6 + +/* PCIE_PHY :: PHY_LINK_STATUS :: EXTENDED_SYNCH [05:05] */ +#define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_MASK 0x00000020 +#define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_SHIFT 5 + +/* PCIE_PHY :: PHY_LINK_STATUS :: POLARITY_INVERTED [04:04] */ +#define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_MASK 0x00000010 +#define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_SHIFT 4 + +/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_UP [03:03] */ +#define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_MASK 0x00000008 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_SHIFT 3 + +/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_TRAINING [02:02] */ +#define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_MASK 0x00000004 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_SHIFT 2 + +/* PCIE_PHY :: PHY_LINK_STATUS :: RECEIVE_DATA_VALID [01:01] */ +#define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_MASK 0x00000002 +#define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_SHIFT 1 + +/* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_1 [00:00] */ +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_MASK 0x00000001 +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_ALIGN 0 +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_BITS 1 +#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_LINK_LTSSM_CONTROL + ***************************************************************************/ +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESERVED_0 [31:08] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_MASK 0xffffff00 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_BITS 24 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_SHIFT 8 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESCRAMBLE [07:07] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_MASK 0x00000080 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_SHIFT 7 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DETECTSTATE [06:06] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_MASK 0x00000040 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_SHIFT 6 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: POLLINGSTATE [05:05] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_MASK 0x00000020 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_SHIFT 5 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: CONFIGSTATE [04:04] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_MASK 0x00000010 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_SHIFT 4 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RECOVSTATE [03:03] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_MASK 0x00000008 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_SHIFT 3 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: EXTLBSTATE [02:02] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_MASK 0x00000004 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_SHIFT 2 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESETSTATE [01:01] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_MASK 0x00000002 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_SHIFT 1 + +/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESTATE [00:00] */ +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_MASK 0x00000001 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_BITS 1 +#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER + ***************************************************************************/ +/* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: RESERVED_0 [31:08] */ +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_MASK 0xffffff00 +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_BITS 24 +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_SHIFT 8 + +/* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: LANE_NUMBER [07:00] */ +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_MASK 0x000000ff +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_BITS 8 +#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER + ***************************************************************************/ +/* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: RESERVED_0 [31:08] */ +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_MASK 0xffffff00 +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_BITS 24 +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_SHIFT 8 + +/* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: LANE_NUMBER [07:00] */ +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_MASK 0x000000ff +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_BITS 8 +#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_LINK_TRAINING_N_FTS + ***************************************************************************/ +/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RESERVED_0 [31:25] */ +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_MASK 0xfe000000 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_BITS 7 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_SHIFT 25 + +/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE [24:24] */ +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_MASK 0x01000000 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_BITS 1 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_SHIFT 24 + +/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE_VALUE [23:16] */ +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_MASK 0x00ff0000 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_BITS 8 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_SHIFT 16 + +/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS [15:08] */ +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_MASK 0x0000ff00 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_BITS 8 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_SHIFT 8 + +/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RECEIVER_N_FTS [07:00] */ +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_MASK 0x000000ff +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_ALIGN 0 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_BITS 8 +#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_ATTENTION + ***************************************************************************/ +/* PCIE_PHY :: PHY_ATTENTION :: RESERVED_0 [31:08] */ +#define PCIE_PHY_PHY_ATTENTION_RESERVED_0_MASK 0xffffff00 +#define PCIE_PHY_PHY_ATTENTION_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_RESERVED_0_BITS 24 +#define PCIE_PHY_PHY_ATTENTION_RESERVED_0_SHIFT 8 + +/* PCIE_PHY :: PHY_ATTENTION :: HOT_RESET [07:07] */ +#define PCIE_PHY_PHY_ATTENTION_HOT_RESET_MASK 0x00000080 +#define PCIE_PHY_PHY_ATTENTION_HOT_RESET_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_HOT_RESET_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_HOT_RESET_SHIFT 7 + +/* PCIE_PHY :: PHY_ATTENTION :: LINK_DOWN [06:06] */ +#define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_MASK 0x00000040 +#define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_SHIFT 6 + +/* PCIE_PHY :: PHY_ATTENTION :: TRAINING_ERROR [05:05] */ +#define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_MASK 0x00000020 +#define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_SHIFT 5 + +/* PCIE_PHY :: PHY_ATTENTION :: BUFFER_OVERRUN [04:04] */ +#define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_MASK 0x00000010 +#define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_SHIFT 4 + +/* PCIE_PHY :: PHY_ATTENTION :: BUFFER_UNDERRUN [03:03] */ +#define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_MASK 0x00000008 +#define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_SHIFT 3 + +/* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_FRAMING_ERROR [02:02] */ +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_MASK 0x00000004 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_SHIFT 2 + +/* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_DISPARITY_ERROR [01:01] */ +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_MASK 0x00000002 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_SHIFT 1 + +/* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_CODE_ERROR [00:00] */ +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_MASK 0x00000001 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_ATTENTION_MASK + ***************************************************************************/ +/* PCIE_PHY :: PHY_ATTENTION_MASK :: RESERVED_0 [31:08] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 +#define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_BITS 24 +#define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_SHIFT 8 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: HOT_RESET_MASK [07:07] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_MASK 0x00000080 +#define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_SHIFT 7 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: LINK_DOWN_MASK [06:06] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_MASK 0x00000040 +#define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_SHIFT 6 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: TRAINING_ERROR_MASK [05:05] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_MASK 0x00000020 +#define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_SHIFT 5 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_OVERRUN_MASK [04:04] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_MASK 0x00000010 +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_SHIFT 4 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_UNDERRUN_MASK [03:03] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_MASK 0x00000008 +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_SHIFT 3 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_FRAME_ERROR_MASK [02:02] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_MASK 0x00000004 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_SHIFT 2 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_DISPARITY_ERROR_MASK [01:01] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_MASK 0x00000002 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_SHIFT 1 + +/* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_CODE_ERROR_MASK [00:00] */ +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_MASK 0x00000001 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_ALIGN 0 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_BITS 1 +#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER + ***************************************************************************/ +/* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: DISPARITY_ERROR_COUNT [31:16] */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_MASK 0xffff0000 +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_BITS 16 +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_SHIFT 16 + +/* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: CODE_ERROR_COUNT [15:00] */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_MASK 0x0000ffff +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_BITS 16 +#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER + ***************************************************************************/ +/* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: RESERVED_0 [31:16] */ +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_BITS 16 +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_SHIFT 16 + +/* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: FRAMING_ERROR_COUNT [15:00] */ +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_MASK 0x0000ffff +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_BITS 16 +#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD + ***************************************************************************/ +/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: RESERVED_0 [31:12] */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_MASK 0xfffff000 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_BITS 20 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_SHIFT 12 + +/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: FRAME_ERROR_THRESHOLD [11:08] */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_MASK 0x00000f00 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_BITS 4 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_SHIFT 8 + +/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: DISPARITY_ERROR_THRESHOLD [07:04] */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_MASK 0x000000f0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_BITS 4 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_SHIFT 4 + +/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: CODE_ERROR_THRESHOLD [03:00] */ +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_MASK 0x0000000f +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_ALIGN 0 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_BITS 4 +#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_TEST_CONTROL + ***************************************************************************/ +/* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_0 [31:31] */ +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_MASK 0x80000000 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_SHIFT 31 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DELAY_HOTRESET_ENABLE [30:30] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_MASK 0x40000000 +#define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_SHIFT 30 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_TSX_MAJORITY_CHECK [29:29] */ +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_MASK 0x20000000 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_SHIFT 29 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_MASK_OFF_BOGUS [28:28] */ +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_MASK 0x10000000 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_SHIFT 28 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_POLARITY_CHECK [27:27] */ +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_MASK 0x08000000 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_SHIFT 27 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_STICKY_POLARITY_CHECK [26:26] */ +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_MASK 0x04000000 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_SHIFT 26 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_1 [25:23] */ +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_MASK 0x03800000 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_BITS 3 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_SHIFT 23 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: TWO_OS_RULE_RELAXING [22:22] */ +#define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_MASK 0x00400000 +#define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_SHIFT 22 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_HOT_RESET [21:21] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_MASK 0x00200000 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_SHIFT 21 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_LINK_DOWN_RESET [20:20] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_MASK 0x00100000 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_SHIFT 20 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE [19:19] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_MASK 0x00080000 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_SHIFT 19 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_EXIT [18:18] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_MASK 0x00040000 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_SHIFT 18 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_MASK [17:17] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_MASK 0x00020000 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_SHIFT 17 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_RECOVERY [16:16] */ +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_MASK 0x00010000 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_SHIFT 16 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: RESERVED_0 [15:08] */ +#define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_MASK 0x0000ff00 +#define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_BITS 8 +#define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_SHIFT 8 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_2 [07:04] */ +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_MASK 0x000000f0 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_BITS 4 +#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_SHIFT 4 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ22100_FIX_DISABLE [03:03] */ +#define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_MASK 0x00000008 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_SHIFT 3 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: TRAINING_BYPASS [02:02] */ +#define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_MASK 0x00000004 +#define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_SHIFT 2 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: EXTERNAL_LOOPBACK [01:01] */ +#define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_MASK 0x00000002 +#define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_SHIFT 1 + +/* PCIE_PHY :: PHY_TEST_CONTROL :: INTERNAL_LOOPBACK [00:00] */ +#define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_MASK 0x00000001 +#define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_ALIGN 0 +#define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_BITS 1 +#define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE + ***************************************************************************/ +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RESERVED_0 [31:18] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_MASK 0xfffc0000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_BITS 14 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_SHIFT 18 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEVALUE [17:17] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_MASK 0x00020000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_BITS 1 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_SHIFT 17 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEOVERRIDE [16:16] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_MASK 0x00010000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_BITS 1 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_SHIFT 16 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPVALUE [15:15] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_MASK 0x00008000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_BITS 1 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_SHIFT 15 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPOVERRIDE [14:14] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_MASK 0x00004000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_BITS 1 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_SHIFT 14 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETVALUE [13:13] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_MASK 0x00002000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_BITS 1 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_SHIFT 13 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETOVERRIDE [12:12] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_MASK 0x00001000 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_BITS 1 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_SHIFT 12 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETTIMECONTROL [11:10] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_MASK 0x00000c00 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_BITS 2 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_SHIFT 10 + +/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETECTIONTIME [09:00] */ +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_MASK 0x000003ff +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_ALIGN 0 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_BITS 10 +#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE + ***************************************************************************/ +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TS1NUMOVERRIDE [31:31] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_MASK 0x80000000 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_BITS 1 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_SHIFT 31 + +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINOVERRIDE [30:30] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_MASK 0x40000000 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_BITS 1 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_SHIFT 30 + +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLE2IDLEOVERRIDE [29:29] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_MASK 0x20000000 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_BITS 1 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_SHIFT 29 + +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: UNUSED_0 [28:28] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_MASK 0x10000000 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_BITS 1 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_SHIFT 28 + +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: N_TS1INPOLLINGACTIVE [27:16] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_MASK 0x0fff0000 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_BITS 12 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_SHIFT 16 + +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINTIME [15:08] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_MASK 0x0000ff00 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_BITS 8 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_SHIFT 8 + +/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLESETTOIDLETIME [07:00] */ +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_MASK 0x000000ff +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_ALIGN 0 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_BITS 8 +#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES + ***************************************************************************/ +/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RESERVED_0 [31:10] */ +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_MASK 0xfffffc00 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_ALIGN 0 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_BITS 22 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_SHIFT 10 + +/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: TRANSMIT_STATE_MACHINE_STATE [09:04] */ +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_MASK 0x000003f0 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_ALIGN 0 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_BITS 6 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_SHIFT 4 + +/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RECEIVE_STATE_MACHINE_STATE [03:00] */ +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_MASK 0x0000000f +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_ALIGN 0 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_BITS 4 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_SHIFT 0 + + +/**************************************************************************** + * PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES + ***************************************************************************/ +/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES :: LTSSM_STATE_MACHINE_STATE [31:00] */ +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_MASK 0xffffffff +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_ALIGN 0 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_BITS 32 +#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_SHIFT 0 + + +/**************************************************************************** + * BCM70012_TGT_TOP_INTR + ***************************************************************************/ +/**************************************************************************** + * INTR :: INTR_STATUS + ***************************************************************************/ +/* INTR :: INTR_STATUS :: reserved0 [31:26] */ +#define INTR_INTR_STATUS_reserved0_MASK 0xfc000000 +#define INTR_INTR_STATUS_reserved0_ALIGN 0 +#define INTR_INTR_STATUS_reserved0_BITS 6 +#define INTR_INTR_STATUS_reserved0_SHIFT 26 + +/* INTR :: INTR_STATUS :: PCIE_TGT_CA_ATTN [25:25] */ +#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK 0x02000000 +#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_ALIGN 0 +#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_BITS 1 +#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT 25 + +/* INTR :: INTR_STATUS :: PCIE_TGT_UR_ATTN [24:24] */ +#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK 0x01000000 +#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_ALIGN 0 +#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_BITS 1 +#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT 24 + +/* INTR :: INTR_STATUS :: reserved1 [23:14] */ +#define INTR_INTR_STATUS_reserved1_MASK 0x00ffc000 +#define INTR_INTR_STATUS_reserved1_ALIGN 0 +#define INTR_INTR_STATUS_reserved1_BITS 10 +#define INTR_INTR_STATUS_reserved1_SHIFT 14 + +/* INTR :: INTR_STATUS :: L1_UV_RX_DMA_ERR_INTR [13:13] */ +#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK 0x00002000 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_SHIFT 13 + +/* INTR :: INTR_STATUS :: L1_UV_RX_DMA_DONE_INTR [12:12] */ +#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK 0x00001000 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_SHIFT 12 + +/* INTR :: INTR_STATUS :: L1_Y_RX_DMA_ERR_INTR [11:11] */ +#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK 0x00000800 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT 11 + +/* INTR :: INTR_STATUS :: L1_Y_RX_DMA_DONE_INTR [10:10] */ +#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK 0x00000400 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT 10 + +/* INTR :: INTR_STATUS :: L1_TX_DMA_ERR_INTR [09:09] */ +#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000200 +#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 9 + +/* INTR :: INTR_STATUS :: L1_TX_DMA_DONE_INTR [08:08] */ +#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000100 +#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 8 + +/* INTR :: INTR_STATUS :: reserved2 [07:06] */ +#define INTR_INTR_STATUS_reserved2_MASK 0x000000c0 +#define INTR_INTR_STATUS_reserved2_ALIGN 0 +#define INTR_INTR_STATUS_reserved2_BITS 2 +#define INTR_INTR_STATUS_reserved2_SHIFT 6 + +/* INTR :: INTR_STATUS :: L0_UV_RX_DMA_ERR_INTR [05:05] */ +#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK 0x00000020 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_SHIFT 5 + +/* INTR :: INTR_STATUS :: L0_UV_RX_DMA_DONE_INTR [04:04] */ +#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK 0x00000010 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_SHIFT 4 + +/* INTR :: INTR_STATUS :: L0_Y_RX_DMA_ERR_INTR [03:03] */ +#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK 0x00000008 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT 3 + +/* INTR :: INTR_STATUS :: L0_Y_RX_DMA_DONE_INTR [02:02] */ +#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK 0x00000004 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT 2 + +/* INTR :: INTR_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */ +#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002 +#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1 + +/* INTR :: INTR_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */ +#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001 +#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0 + + +/**************************************************************************** + * INTR :: INTR_SET + ***************************************************************************/ +/* INTR :: INTR_SET :: reserved0 [31:26] */ +#define INTR_INTR_SET_reserved0_MASK 0xfc000000 +#define INTR_INTR_SET_reserved0_ALIGN 0 +#define INTR_INTR_SET_reserved0_BITS 6 +#define INTR_INTR_SET_reserved0_SHIFT 26 + +/* INTR :: INTR_SET :: PCIE_TGT_CA_ATTN [25:25] */ +#define INTR_INTR_SET_PCIE_TGT_CA_ATTN_MASK 0x02000000 +#define INTR_INTR_SET_PCIE_TGT_CA_ATTN_ALIGN 0 +#define INTR_INTR_SET_PCIE_TGT_CA_ATTN_BITS 1 +#define INTR_INTR_SET_PCIE_TGT_CA_ATTN_SHIFT 25 + +/* INTR :: INTR_SET :: PCIE_TGT_UR_ATTN [24:24] */ +#define INTR_INTR_SET_PCIE_TGT_UR_ATTN_MASK 0x01000000 +#define INTR_INTR_SET_PCIE_TGT_UR_ATTN_ALIGN 0 +#define INTR_INTR_SET_PCIE_TGT_UR_ATTN_BITS 1 +#define INTR_INTR_SET_PCIE_TGT_UR_ATTN_SHIFT 24 + +/* INTR :: INTR_SET :: reserved1 [23:14] */ +#define INTR_INTR_SET_reserved1_MASK 0x00ffc000 +#define INTR_INTR_SET_reserved1_ALIGN 0 +#define INTR_INTR_SET_reserved1_BITS 10 +#define INTR_INTR_SET_reserved1_SHIFT 14 + +/* INTR :: INTR_SET :: UV_RX_DMA_L1_ERR_INTR [13:13] */ +#define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_MASK 0x00002000 +#define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_ALIGN 0 +#define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_BITS 1 +#define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_SHIFT 13 + +/* INTR :: INTR_SET :: UV_RX_DMA_L1_DONE_INTR [12:12] */ +#define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_MASK 0x00001000 +#define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_ALIGN 0 +#define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_BITS 1 +#define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_SHIFT 12 + +/* INTR :: INTR_SET :: Y_RX_DMA_L1_ERR_INTR [11:11] */ +#define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_MASK 0x00000800 +#define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_ALIGN 0 +#define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_BITS 1 +#define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_SHIFT 11 + +/* INTR :: INTR_SET :: Y_RX_DMA_L1_DONE_INTR [10:10] */ +#define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_MASK 0x00000400 +#define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_ALIGN 0 +#define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_BITS 1 +#define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_SHIFT 10 + +/* INTR :: INTR_SET :: TX_DMA_L1_ERR_INTR [09:09] */ +#define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_MASK 0x00000200 +#define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_ALIGN 0 +#define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_BITS 1 +#define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_SHIFT 9 + +/* INTR :: INTR_SET :: TX_DMA_L1_DONE_INTR [08:08] */ +#define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_MASK 0x00000100 +#define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_ALIGN 0 +#define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_BITS 1 +#define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_SHIFT 8 + +/* INTR :: INTR_SET :: reserved2 [07:06] */ +#define INTR_INTR_SET_reserved2_MASK 0x000000c0 +#define INTR_INTR_SET_reserved2_ALIGN 0 +#define INTR_INTR_SET_reserved2_BITS 2 +#define INTR_INTR_SET_reserved2_SHIFT 6 + +/* INTR :: INTR_SET :: UV_RX_DMA_L0_ERR_INTR [05:05] */ +#define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_MASK 0x00000020 +#define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_ALIGN 0 +#define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_BITS 1 +#define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_SHIFT 5 + +/* INTR :: INTR_SET :: UV_RX_DMA_L0_DONE_INTR [04:04] */ +#define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_MASK 0x00000010 +#define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_ALIGN 0 +#define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_BITS 1 +#define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_SHIFT 4 + +/* INTR :: INTR_SET :: Y_RX_DMA_L0_ERR_INTR [03:03] */ +#define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_MASK 0x00000008 +#define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_ALIGN 0 +#define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_BITS 1 +#define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_SHIFT 3 + +/* INTR :: INTR_SET :: Y_RX_DMA_L0_DONE_INTR [02:02] */ +#define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_MASK 0x00000004 +#define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_ALIGN 0 +#define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_BITS 1 +#define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_SHIFT 2 + +/* INTR :: INTR_SET :: TX_DMA_L0_ERR_INTR [01:01] */ +#define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_MASK 0x00000002 +#define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_ALIGN 0 +#define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_BITS 1 +#define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_SHIFT 1 + +/* INTR :: INTR_SET :: TX_DMA_L0_DONE_INTR [00:00] */ +#define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_MASK 0x00000001 +#define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_ALIGN 0 +#define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_BITS 1 +#define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_SHIFT 0 + + +/**************************************************************************** + * INTR :: INTR_CLR_REG + ***************************************************************************/ +/* INTR :: INTR_CLR_REG :: reserved0 [31:26] */ +#define INTR_INTR_CLR_REG_reserved0_MASK 0xfc000000 +#define INTR_INTR_CLR_REG_reserved0_ALIGN 0 +#define INTR_INTR_CLR_REG_reserved0_BITS 6 +#define INTR_INTR_CLR_REG_reserved0_SHIFT 26 + +/* INTR :: INTR_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ +#define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 +#define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_ALIGN 0 +#define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_BITS 1 +#define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 + +/* INTR :: INTR_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ +#define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 +#define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_ALIGN 0 +#define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_BITS 1 +#define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 + +/* INTR :: INTR_CLR_REG :: reserved1 [23:14] */ +#define INTR_INTR_CLR_REG_reserved1_MASK 0x00ffc000 +#define INTR_INTR_CLR_REG_reserved1_ALIGN 0 +#define INTR_INTR_CLR_REG_reserved1_BITS 10 +#define INTR_INTR_CLR_REG_reserved1_SHIFT 14 + +/* INTR :: INTR_CLR_REG :: L1_UV_RX_DMA_ERR_INTR_CLR [13:13] */ +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_MASK 0x00002000 +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_SHIFT 13 + +/* INTR :: INTR_CLR_REG :: L1_UV_RX_DMA_DONE_INTR_CLR [12:12] */ +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_MASK 0x00001000 +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_SHIFT 12 + +/* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_CLR [11:11] */ +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000800 +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_SHIFT 11 + +/* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_CLR [10:10] */ +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000400 +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_SHIFT 10 + +/* INTR :: INTR_CLR_REG :: L1_TX_DMA_ERR_INTR_CLR [09:09] */ +#define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_MASK 0x00000200 +#define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_SHIFT 9 + +/* INTR :: INTR_CLR_REG :: L1_TX_DMA_DONE_INTR_CLR [08:08] */ +#define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_MASK 0x00000100 +#define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_SHIFT 8 + +/* INTR :: INTR_CLR_REG :: reserved2 [07:06] */ +#define INTR_INTR_CLR_REG_reserved2_MASK 0x000000c0 +#define INTR_INTR_CLR_REG_reserved2_ALIGN 0 +#define INTR_INTR_CLR_REG_reserved2_BITS 2 +#define INTR_INTR_CLR_REG_reserved2_SHIFT 6 + +/* INTR :: INTR_CLR_REG :: L0_UV_RX_DMA_ERR_INTR_CLR [05:05] */ +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_MASK 0x00000020 +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_SHIFT 5 + +/* INTR :: INTR_CLR_REG :: L0_UV_RX_DMA_DONE_INTR_CLR [04:04] */ +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_MASK 0x00000010 +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_SHIFT 4 + +/* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_CLR [03:03] */ +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000008 +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_SHIFT 3 + +/* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_CLR [02:02] */ +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000004 +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_SHIFT 2 + +/* INTR :: INTR_CLR_REG :: L0_TX_DMA_ERR_INTR_CLR [01:01] */ +#define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_MASK 0x00000002 +#define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_SHIFT 1 + +/* INTR :: INTR_CLR_REG :: L0_TX_DMA_DONE_INTR_CLR [00:00] */ +#define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_MASK 0x00000001 +#define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_ALIGN 0 +#define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_BITS 1 +#define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_SHIFT 0 + + +/**************************************************************************** + * INTR :: INTR_MSK_STS_REG + ***************************************************************************/ +/* INTR :: INTR_MSK_STS_REG :: reserved0 [31:26] */ +#define INTR_INTR_MSK_STS_REG_reserved0_MASK 0xfc000000 +#define INTR_INTR_MSK_STS_REG_reserved0_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_reserved0_BITS 6 +#define INTR_INTR_MSK_STS_REG_reserved0_SHIFT 26 + +/* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_CA_ATTN [25:25] */ +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_BITS 1 +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_SHIFT 25 + +/* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_UR_ATTN [24:24] */ +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_BITS 1 +#define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_SHIFT 24 + +/* INTR :: INTR_MSK_STS_REG :: reserved1 [23:14] */ +#define INTR_INTR_MSK_STS_REG_reserved1_MASK 0x00ffc000 +#define INTR_INTR_MSK_STS_REG_reserved1_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_reserved1_BITS 10 +#define INTR_INTR_MSK_STS_REG_reserved1_SHIFT 14 + +/* INTR :: INTR_MSK_STS_REG :: L1_UV_RX_DMA_ERR_INTR_MSK [13:13] */ +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_MASK 0x00002000 +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SHIFT 13 + +/* INTR :: INTR_MSK_STS_REG :: L1_UV_RX_DMA_DONE_INTR_MSK [12:12] */ +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_MASK 0x00001000 +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SHIFT 12 + +/* INTR :: INTR_MSK_STS_REG :: LIST1_Y_RX_DMA_ERR_INTR_MSK [11:11] */ +#define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000800 +#define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_SHIFT 11 + +/* INTR :: INTR_MSK_STS_REG :: L1_Y_RX_DMA_DONE_INTR_MSK [10:10] */ +#define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000400 +#define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SHIFT 10 + +/* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_ERR_INTR_MSK [09:09] */ +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_MASK 0x00000200 +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_SHIFT 9 + +/* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_DONE_INTR_MSK [08:08] */ +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_MASK 0x00000100 +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_SHIFT 8 + +/* INTR :: INTR_MSK_STS_REG :: reserved2 [07:06] */ +#define INTR_INTR_MSK_STS_REG_reserved2_MASK 0x000000c0 +#define INTR_INTR_MSK_STS_REG_reserved2_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_reserved2_BITS 2 +#define INTR_INTR_MSK_STS_REG_reserved2_SHIFT 6 + +/* INTR :: INTR_MSK_STS_REG :: L0_UV_RX_DMA_ERR_INTR_MSK [05:05] */ +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_MASK 0x00000020 +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SHIFT 5 + +/* INTR :: INTR_MSK_STS_REG :: L0_UV_RX_DMA_DONE_INTR_MSK [04:04] */ +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_MASK 0x00000010 +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SHIFT 4 + +/* INTR :: INTR_MSK_STS_REG :: LIST0_Y_RX_DMA_ERR_INTR_MSK [03:03] */ +#define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000008 +#define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_SHIFT 3 + +/* INTR :: INTR_MSK_STS_REG :: L0_Y_RX_DMA_DONE_INTR_MSK [02:02] */ +#define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000004 +#define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SHIFT 2 + +/* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_ERR_INTR_MSK [01:01] */ +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_MASK 0x00000002 +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_SHIFT 1 + +/* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_DONE_INTR_MSK [00:00] */ +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_MASK 0x00000001 +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_ALIGN 0 +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_BITS 1 +#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_SHIFT 0 + + +/**************************************************************************** + * INTR :: INTR_MSK_SET_REG + ***************************************************************************/ +/* INTR :: INTR_MSK_SET_REG :: reserved0 [31:26] */ +#define INTR_INTR_MSK_SET_REG_reserved0_MASK 0xfc000000 +#define INTR_INTR_MSK_SET_REG_reserved0_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_reserved0_BITS 6 +#define INTR_INTR_MSK_SET_REG_reserved0_SHIFT 26 + +/* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_CA_ATTN [25:25] */ +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_BITS 1 +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_SHIFT 25 + +/* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_UR_ATTN [24:24] */ +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_BITS 1 +#define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_SHIFT 24 + +/* INTR :: INTR_MSK_SET_REG :: reserved1 [23:14] */ +#define INTR_INTR_MSK_SET_REG_reserved1_MASK 0x00ffc000 +#define INTR_INTR_MSK_SET_REG_reserved1_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_reserved1_BITS 10 +#define INTR_INTR_MSK_SET_REG_reserved1_SHIFT 14 + +/* INTR :: INTR_MSK_SET_REG :: L1_UV_RX_DMA_ERR_INTR_MSK_SET [13:13] */ +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00002000 +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_SHIFT 13 + +/* INTR :: INTR_MSK_SET_REG :: L1_UV_RX_DMA_DONE_INTR_MSK_SET [12:12] */ +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00001000 +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_SHIFT 12 + +/* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_SET [11:11] */ +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000800 +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 11 + +/* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_SET [10:10] */ +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000400 +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 10 + +/* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_ERR_INTR_MSK_SET [09:09] */ +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000200 +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_SHIFT 9 + +/* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_DONE_INTR_MSK_SET [08:08] */ +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000100 +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_SHIFT 8 + +/* INTR :: INTR_MSK_SET_REG :: reserved2 [07:06] */ +#define INTR_INTR_MSK_SET_REG_reserved2_MASK 0x000000c0 +#define INTR_INTR_MSK_SET_REG_reserved2_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_reserved2_BITS 2 +#define INTR_INTR_MSK_SET_REG_reserved2_SHIFT 6 + +/* INTR :: INTR_MSK_SET_REG :: L0_UV_RX_DMA_ERR_INTR_MSK_SET [05:05] */ +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000020 +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_SHIFT 5 + +/* INTR :: INTR_MSK_SET_REG :: L0_UV_RX_DMA_DONE_INTR_MSK_SET [04:04] */ +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000010 +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_SHIFT 4 + +/* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_SET [03:03] */ +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000008 +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 3 + +/* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_SET [02:02] */ +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000004 +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 2 + +/* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_ERR_INTR_MSK_SET [01:01] */ +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000002 +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_SHIFT 1 + +/* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_DONE_INTR_MSK_SET [00:00] */ +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000001 +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_ALIGN 0 +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_BITS 1 +#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_SHIFT 0 + + +/**************************************************************************** + * INTR :: INTR_MSK_CLR_REG + ***************************************************************************/ +/* INTR :: INTR_MSK_CLR_REG :: reserved0 [31:26] */ +#define INTR_INTR_MSK_CLR_REG_reserved0_MASK 0xfc000000 +#define INTR_INTR_MSK_CLR_REG_reserved0_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_reserved0_BITS 6 +#define INTR_INTR_MSK_CLR_REG_reserved0_SHIFT 26 + +/* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_BITS 1 +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 + +/* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_BITS 1 +#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 + +/* INTR :: INTR_MSK_CLR_REG :: reserved1 [23:14] */ +#define INTR_INTR_MSK_CLR_REG_reserved1_MASK 0x00ffc000 +#define INTR_INTR_MSK_CLR_REG_reserved1_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_reserved1_BITS 10 +#define INTR_INTR_MSK_CLR_REG_reserved1_SHIFT 14 + +/* INTR :: INTR_MSK_CLR_REG :: L1_UV_RX_DMA_ERR_INTR_MSK_CLR [13:13] */ +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00002000 +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 13 + +/* INTR :: INTR_MSK_CLR_REG :: L1_UV_RX_DMA_DONE_INTR_MSK_CLR [12:12] */ +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00001000 +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 12 + +/* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_CLR [11:11] */ +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000800 +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 11 + +/* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_CLR [10:10] */ +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000400 +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 10 + +/* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_ERR_INTR_MSK_CLR [09:09] */ +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000200 +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 9 + +/* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_DONE_INTR_MSK_CLR [08:08] */ +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000100 +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 8 + +/* INTR :: INTR_MSK_CLR_REG :: reserved2 [07:06] */ +#define INTR_INTR_MSK_CLR_REG_reserved2_MASK 0x000000c0 +#define INTR_INTR_MSK_CLR_REG_reserved2_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_reserved2_BITS 2 +#define INTR_INTR_MSK_CLR_REG_reserved2_SHIFT 6 + +/* INTR :: INTR_MSK_CLR_REG :: L0_UV_RX_DMA_ERR_INTR_MSK_CLR [05:05] */ +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000020 +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 5 + +/* INTR :: INTR_MSK_CLR_REG :: L0_UV_RX_DMA_DONE_INTR_MSK_CLR [04:04] */ +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000010 +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 4 + +/* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_CLR [03:03] */ +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000008 +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 3 + +/* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_CLR [02:02] */ +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000004 +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 2 + +/* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_ERR_INTR_MSK_CLR [01:01] */ +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000002 +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 1 + +/* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_DONE_INTR_MSK_CLR [00:00] */ +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000001 +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_BITS 1 +#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 0 + + +/**************************************************************************** + * INTR :: EOI_CTRL + ***************************************************************************/ +/* INTR :: EOI_CTRL :: reserved0 [31:01] */ +#define INTR_EOI_CTRL_reserved0_MASK 0xfffffffe +#define INTR_EOI_CTRL_reserved0_ALIGN 0 +#define INTR_EOI_CTRL_reserved0_BITS 31 +#define INTR_EOI_CTRL_reserved0_SHIFT 1 + +/* INTR :: EOI_CTRL :: EOI [00:00] */ +#define INTR_EOI_CTRL_EOI_MASK 0x00000001 +#define INTR_EOI_CTRL_EOI_ALIGN 0 +#define INTR_EOI_CTRL_EOI_BITS 1 +#define INTR_EOI_CTRL_EOI_SHIFT 0 + + +/**************************************************************************** + * BCM70012_TGT_TOP_MDIO + ***************************************************************************/ +/**************************************************************************** + * MDIO :: CTRL0 + ***************************************************************************/ +/* MDIO :: CTRL0 :: reserved0 [31:22] */ +#define MDIO_CTRL0_reserved0_MASK 0xffc00000 +#define MDIO_CTRL0_reserved0_ALIGN 0 +#define MDIO_CTRL0_reserved0_BITS 10 +#define MDIO_CTRL0_reserved0_SHIFT 22 + +/* MDIO :: CTRL0 :: WRITE_READ_COMMAND [21:21] */ +#define MDIO_CTRL0_WRITE_READ_COMMAND_MASK 0x00200000 +#define MDIO_CTRL0_WRITE_READ_COMMAND_ALIGN 0 +#define MDIO_CTRL0_WRITE_READ_COMMAND_BITS 1 +#define MDIO_CTRL0_WRITE_READ_COMMAND_SHIFT 21 + +/* MDIO :: CTRL0 :: PHYAD [20:16] */ +#define MDIO_CTRL0_PHYAD_MASK 0x001f0000 +#define MDIO_CTRL0_PHYAD_ALIGN 0 +#define MDIO_CTRL0_PHYAD_BITS 5 +#define MDIO_CTRL0_PHYAD_SHIFT 16 + +/* MDIO :: CTRL0 :: reserved1 [15:05] */ +#define MDIO_CTRL0_reserved1_MASK 0x0000ffe0 +#define MDIO_CTRL0_reserved1_ALIGN 0 +#define MDIO_CTRL0_reserved1_BITS 11 +#define MDIO_CTRL0_reserved1_SHIFT 5 + +/* MDIO :: CTRL0 :: REGAD [04:00] */ +#define MDIO_CTRL0_REGAD_MASK 0x0000001f +#define MDIO_CTRL0_REGAD_ALIGN 0 +#define MDIO_CTRL0_REGAD_BITS 5 +#define MDIO_CTRL0_REGAD_SHIFT 0 + + +/**************************************************************************** + * MDIO :: CTRL1 + ***************************************************************************/ +/* MDIO :: CTRL1 :: WR_STATUS [31:31] */ +#define MDIO_CTRL1_WR_STATUS_MASK 0x80000000 +#define MDIO_CTRL1_WR_STATUS_ALIGN 0 +#define MDIO_CTRL1_WR_STATUS_BITS 1 +#define MDIO_CTRL1_WR_STATUS_SHIFT 31 + +/* MDIO :: CTRL1 :: reserved0 [30:16] */ +#define MDIO_CTRL1_reserved0_MASK 0x7fff0000 +#define MDIO_CTRL1_reserved0_ALIGN 0 +#define MDIO_CTRL1_reserved0_BITS 15 +#define MDIO_CTRL1_reserved0_SHIFT 16 + +/* MDIO :: CTRL1 :: Write_Data [15:00] */ +#define MDIO_CTRL1_Write_Data_MASK 0x0000ffff +#define MDIO_CTRL1_Write_Data_ALIGN 0 +#define MDIO_CTRL1_Write_Data_BITS 16 +#define MDIO_CTRL1_Write_Data_SHIFT 0 + + +/**************************************************************************** + * MDIO :: CTRL2 + ***************************************************************************/ +/* MDIO :: CTRL2 :: RD_STATUS [31:31] */ +#define MDIO_CTRL2_RD_STATUS_MASK 0x80000000 +#define MDIO_CTRL2_RD_STATUS_ALIGN 0 +#define MDIO_CTRL2_RD_STATUS_BITS 1 +#define MDIO_CTRL2_RD_STATUS_SHIFT 31 + +/* MDIO :: CTRL2 :: reserved0 [30:16] */ +#define MDIO_CTRL2_reserved0_MASK 0x7fff0000 +#define MDIO_CTRL2_reserved0_ALIGN 0 +#define MDIO_CTRL2_reserved0_BITS 15 +#define MDIO_CTRL2_reserved0_SHIFT 16 + +/* MDIO :: CTRL2 :: Read_Data [15:00] */ +#define MDIO_CTRL2_Read_Data_MASK 0x0000ffff +#define MDIO_CTRL2_Read_Data_ALIGN 0 +#define MDIO_CTRL2_Read_Data_BITS 16 +#define MDIO_CTRL2_Read_Data_SHIFT 0 + + +/**************************************************************************** + * BCM70012_TGT_TOP_TGT_RGR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * TGT_RGR_BRIDGE :: REVISION + ***************************************************************************/ +/* TGT_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define TGT_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define TGT_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define TGT_RGR_BRIDGE_REVISION_reserved0_BITS 16 +#define TGT_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* TGT_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define TGT_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define TGT_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define TGT_RGR_BRIDGE_REVISION_MAJOR_BITS 8 +#define TGT_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* TGT_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define TGT_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define TGT_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define TGT_RGR_BRIDGE_REVISION_MINOR_BITS 8 +#define TGT_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * TGT_RGR_BRIDGE :: CTRL + ***************************************************************************/ +/* TGT_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ +#define TGT_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc +#define TGT_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define TGT_RGR_BRIDGE_CTRL_reserved0_BITS 30 +#define TGT_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 + +/* TGT_RGR_BRIDGE :: CTRL :: RBUS_ERROR_INTR [01:01] */ +#define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_MASK 0x00000002 +#define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_ALIGN 0 +#define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_BITS 1 +#define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_SHIFT 1 + +/* TGT_RGR_BRIDGE :: CTRL :: GISB_ERROR_INTR [00:00] */ +#define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_MASK 0x00000001 +#define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_ALIGN 0 +#define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_BITS 1 +#define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_SHIFT 0 + + +/**************************************************************************** + * TGT_RGR_BRIDGE :: RBUS_TIMER + ***************************************************************************/ +/* TGT_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ +#define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 +#define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 +#define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 +#define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 + +/* TGT_RGR_BRIDGE :: RBUS_TIMER :: RBUS_TO_RBUS_TRANS_TIMER_CNT [15:00] */ +#define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_MASK 0x0000ffff +#define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_ALIGN 0 +#define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_BITS 16 +#define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_SHIFT 0 + + +/**************************************************************************** + * TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 + + +/**************************************************************************** + * TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 + + +/**************************************************************************** + * BCM70012_I2C_TOP_I2C + ***************************************************************************/ +/**************************************************************************** + * I2C :: CHIP_ADDRESS + ***************************************************************************/ +/* I2C :: CHIP_ADDRESS :: reserved0 [31:08] */ +#define I2C_CHIP_ADDRESS_reserved0_MASK 0xffffff00 +#define I2C_CHIP_ADDRESS_reserved0_ALIGN 0 +#define I2C_CHIP_ADDRESS_reserved0_BITS 24 +#define I2C_CHIP_ADDRESS_reserved0_SHIFT 8 + +/* I2C :: CHIP_ADDRESS :: CHIP_ADDRESS [07:01] */ +#define I2C_CHIP_ADDRESS_CHIP_ADDRESS_MASK 0x000000fe +#define I2C_CHIP_ADDRESS_CHIP_ADDRESS_ALIGN 0 +#define I2C_CHIP_ADDRESS_CHIP_ADDRESS_BITS 7 +#define I2C_CHIP_ADDRESS_CHIP_ADDRESS_SHIFT 1 + +/* I2C :: CHIP_ADDRESS :: RESERVED [00:00] */ +#define I2C_CHIP_ADDRESS_RESERVED_MASK 0x00000001 +#define I2C_CHIP_ADDRESS_RESERVED_ALIGN 0 +#define I2C_CHIP_ADDRESS_RESERVED_BITS 1 +#define I2C_CHIP_ADDRESS_RESERVED_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN0 + ***************************************************************************/ +/* I2C :: DATA_IN0 :: reserved0 [31:08] */ +#define I2C_DATA_IN0_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN0_reserved0_ALIGN 0 +#define I2C_DATA_IN0_reserved0_BITS 24 +#define I2C_DATA_IN0_reserved0_SHIFT 8 + +/* I2C :: DATA_IN0 :: DATA_IN0 [07:00] */ +#define I2C_DATA_IN0_DATA_IN0_MASK 0x000000ff +#define I2C_DATA_IN0_DATA_IN0_ALIGN 0 +#define I2C_DATA_IN0_DATA_IN0_BITS 8 +#define I2C_DATA_IN0_DATA_IN0_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN1 + ***************************************************************************/ +/* I2C :: DATA_IN1 :: reserved0 [31:08] */ +#define I2C_DATA_IN1_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN1_reserved0_ALIGN 0 +#define I2C_DATA_IN1_reserved0_BITS 24 +#define I2C_DATA_IN1_reserved0_SHIFT 8 + +/* I2C :: DATA_IN1 :: DATA_IN1 [07:00] */ +#define I2C_DATA_IN1_DATA_IN1_MASK 0x000000ff +#define I2C_DATA_IN1_DATA_IN1_ALIGN 0 +#define I2C_DATA_IN1_DATA_IN1_BITS 8 +#define I2C_DATA_IN1_DATA_IN1_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN2 + ***************************************************************************/ +/* I2C :: DATA_IN2 :: reserved0 [31:08] */ +#define I2C_DATA_IN2_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN2_reserved0_ALIGN 0 +#define I2C_DATA_IN2_reserved0_BITS 24 +#define I2C_DATA_IN2_reserved0_SHIFT 8 + +/* I2C :: DATA_IN2 :: DATA_IN2 [07:00] */ +#define I2C_DATA_IN2_DATA_IN2_MASK 0x000000ff +#define I2C_DATA_IN2_DATA_IN2_ALIGN 0 +#define I2C_DATA_IN2_DATA_IN2_BITS 8 +#define I2C_DATA_IN2_DATA_IN2_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN3 + ***************************************************************************/ +/* I2C :: DATA_IN3 :: reserved0 [31:08] */ +#define I2C_DATA_IN3_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN3_reserved0_ALIGN 0 +#define I2C_DATA_IN3_reserved0_BITS 24 +#define I2C_DATA_IN3_reserved0_SHIFT 8 + +/* I2C :: DATA_IN3 :: DATA_IN3 [07:00] */ +#define I2C_DATA_IN3_DATA_IN3_MASK 0x000000ff +#define I2C_DATA_IN3_DATA_IN3_ALIGN 0 +#define I2C_DATA_IN3_DATA_IN3_BITS 8 +#define I2C_DATA_IN3_DATA_IN3_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN4 + ***************************************************************************/ +/* I2C :: DATA_IN4 :: reserved0 [31:08] */ +#define I2C_DATA_IN4_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN4_reserved0_ALIGN 0 +#define I2C_DATA_IN4_reserved0_BITS 24 +#define I2C_DATA_IN4_reserved0_SHIFT 8 + +/* I2C :: DATA_IN4 :: DATA_IN4 [07:00] */ +#define I2C_DATA_IN4_DATA_IN4_MASK 0x000000ff +#define I2C_DATA_IN4_DATA_IN4_ALIGN 0 +#define I2C_DATA_IN4_DATA_IN4_BITS 8 +#define I2C_DATA_IN4_DATA_IN4_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN5 + ***************************************************************************/ +/* I2C :: DATA_IN5 :: reserved0 [31:08] */ +#define I2C_DATA_IN5_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN5_reserved0_ALIGN 0 +#define I2C_DATA_IN5_reserved0_BITS 24 +#define I2C_DATA_IN5_reserved0_SHIFT 8 + +/* I2C :: DATA_IN5 :: DATA_IN5 [07:00] */ +#define I2C_DATA_IN5_DATA_IN5_MASK 0x000000ff +#define I2C_DATA_IN5_DATA_IN5_ALIGN 0 +#define I2C_DATA_IN5_DATA_IN5_BITS 8 +#define I2C_DATA_IN5_DATA_IN5_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN6 + ***************************************************************************/ +/* I2C :: DATA_IN6 :: reserved0 [31:08] */ +#define I2C_DATA_IN6_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN6_reserved0_ALIGN 0 +#define I2C_DATA_IN6_reserved0_BITS 24 +#define I2C_DATA_IN6_reserved0_SHIFT 8 + +/* I2C :: DATA_IN6 :: DATA_IN6 [07:00] */ +#define I2C_DATA_IN6_DATA_IN6_MASK 0x000000ff +#define I2C_DATA_IN6_DATA_IN6_ALIGN 0 +#define I2C_DATA_IN6_DATA_IN6_BITS 8 +#define I2C_DATA_IN6_DATA_IN6_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_IN7 + ***************************************************************************/ +/* I2C :: DATA_IN7 :: reserved0 [31:08] */ +#define I2C_DATA_IN7_reserved0_MASK 0xffffff00 +#define I2C_DATA_IN7_reserved0_ALIGN 0 +#define I2C_DATA_IN7_reserved0_BITS 24 +#define I2C_DATA_IN7_reserved0_SHIFT 8 + +/* I2C :: DATA_IN7 :: DATA_IN7 [07:00] */ +#define I2C_DATA_IN7_DATA_IN7_MASK 0x000000ff +#define I2C_DATA_IN7_DATA_IN7_ALIGN 0 +#define I2C_DATA_IN7_DATA_IN7_BITS 8 +#define I2C_DATA_IN7_DATA_IN7_SHIFT 0 + + +/**************************************************************************** + * I2C :: CNT_REG + ***************************************************************************/ +/* I2C :: CNT_REG :: reserved0 [31:08] */ +#define I2C_CNT_REG_reserved0_MASK 0xffffff00 +#define I2C_CNT_REG_reserved0_ALIGN 0 +#define I2C_CNT_REG_reserved0_BITS 24 +#define I2C_CNT_REG_reserved0_SHIFT 8 + +/* I2C :: CNT_REG :: CNT_REG2 [07:04] */ +#define I2C_CNT_REG_CNT_REG2_MASK 0x000000f0 +#define I2C_CNT_REG_CNT_REG2_ALIGN 0 +#define I2C_CNT_REG_CNT_REG2_BITS 4 +#define I2C_CNT_REG_CNT_REG2_SHIFT 4 + +/* I2C :: CNT_REG :: CNT_REG1 [03:00] */ +#define I2C_CNT_REG_CNT_REG1_MASK 0x0000000f +#define I2C_CNT_REG_CNT_REG1_ALIGN 0 +#define I2C_CNT_REG_CNT_REG1_BITS 4 +#define I2C_CNT_REG_CNT_REG1_SHIFT 0 + + +/**************************************************************************** + * I2C :: CTL_REG + ***************************************************************************/ +/* I2C :: CTL_REG :: reserved0 [31:08] */ +#define I2C_CTL_REG_reserved0_MASK 0xffffff00 +#define I2C_CTL_REG_reserved0_ALIGN 0 +#define I2C_CTL_REG_reserved0_BITS 24 +#define I2C_CTL_REG_reserved0_SHIFT 8 + +/* I2C :: CTL_REG :: DIV_CLK [07:07] */ +#define I2C_CTL_REG_DIV_CLK_MASK 0x00000080 +#define I2C_CTL_REG_DIV_CLK_ALIGN 0 +#define I2C_CTL_REG_DIV_CLK_BITS 1 +#define I2C_CTL_REG_DIV_CLK_SHIFT 7 + +/* I2C :: CTL_REG :: INT_EN [06:06] */ +#define I2C_CTL_REG_INT_EN_MASK 0x00000040 +#define I2C_CTL_REG_INT_EN_ALIGN 0 +#define I2C_CTL_REG_INT_EN_BITS 1 +#define I2C_CTL_REG_INT_EN_SHIFT 6 + +/* I2C :: CTL_REG :: SCL_SEL [05:04] */ +#define I2C_CTL_REG_SCL_SEL_MASK 0x00000030 +#define I2C_CTL_REG_SCL_SEL_ALIGN 0 +#define I2C_CTL_REG_SCL_SEL_BITS 2 +#define I2C_CTL_REG_SCL_SEL_SHIFT 4 + +/* I2C :: CTL_REG :: DELAY_DIS [03:03] */ +#define I2C_CTL_REG_DELAY_DIS_MASK 0x00000008 +#define I2C_CTL_REG_DELAY_DIS_ALIGN 0 +#define I2C_CTL_REG_DELAY_DIS_BITS 1 +#define I2C_CTL_REG_DELAY_DIS_SHIFT 3 + +/* I2C :: CTL_REG :: DEGLITCH_DIS [02:02] */ +#define I2C_CTL_REG_DEGLITCH_DIS_MASK 0x00000004 +#define I2C_CTL_REG_DEGLITCH_DIS_ALIGN 0 +#define I2C_CTL_REG_DEGLITCH_DIS_BITS 1 +#define I2C_CTL_REG_DEGLITCH_DIS_SHIFT 2 + +/* I2C :: CTL_REG :: DTF [01:00] */ +#define I2C_CTL_REG_DTF_MASK 0x00000003 +#define I2C_CTL_REG_DTF_ALIGN 0 +#define I2C_CTL_REG_DTF_BITS 2 +#define I2C_CTL_REG_DTF_SHIFT 0 + + +/**************************************************************************** + * I2C :: IIC_ENABLE + ***************************************************************************/ +/* I2C :: IIC_ENABLE :: reserved0 [31:07] */ +#define I2C_IIC_ENABLE_reserved0_MASK 0xffffff80 +#define I2C_IIC_ENABLE_reserved0_ALIGN 0 +#define I2C_IIC_ENABLE_reserved0_BITS 25 +#define I2C_IIC_ENABLE_reserved0_SHIFT 7 + +/* I2C :: IIC_ENABLE :: RESTART [06:06] */ +#define I2C_IIC_ENABLE_RESTART_MASK 0x00000040 +#define I2C_IIC_ENABLE_RESTART_ALIGN 0 +#define I2C_IIC_ENABLE_RESTART_BITS 1 +#define I2C_IIC_ENABLE_RESTART_SHIFT 6 + +/* I2C :: IIC_ENABLE :: NO_START [05:05] */ +#define I2C_IIC_ENABLE_NO_START_MASK 0x00000020 +#define I2C_IIC_ENABLE_NO_START_ALIGN 0 +#define I2C_IIC_ENABLE_NO_START_BITS 1 +#define I2C_IIC_ENABLE_NO_START_SHIFT 5 + +/* I2C :: IIC_ENABLE :: NO_STOP [04:04] */ +#define I2C_IIC_ENABLE_NO_STOP_MASK 0x00000010 +#define I2C_IIC_ENABLE_NO_STOP_ALIGN 0 +#define I2C_IIC_ENABLE_NO_STOP_BITS 1 +#define I2C_IIC_ENABLE_NO_STOP_SHIFT 4 + +/* I2C :: IIC_ENABLE :: reserved1 [03:03] */ +#define I2C_IIC_ENABLE_reserved1_MASK 0x00000008 +#define I2C_IIC_ENABLE_reserved1_ALIGN 0 +#define I2C_IIC_ENABLE_reserved1_BITS 1 +#define I2C_IIC_ENABLE_reserved1_SHIFT 3 + +/* I2C :: IIC_ENABLE :: NO_ACK [02:02] */ +#define I2C_IIC_ENABLE_NO_ACK_MASK 0x00000004 +#define I2C_IIC_ENABLE_NO_ACK_ALIGN 0 +#define I2C_IIC_ENABLE_NO_ACK_BITS 1 +#define I2C_IIC_ENABLE_NO_ACK_SHIFT 2 + +/* I2C :: IIC_ENABLE :: INTRP [01:01] */ +#define I2C_IIC_ENABLE_INTRP_MASK 0x00000002 +#define I2C_IIC_ENABLE_INTRP_ALIGN 0 +#define I2C_IIC_ENABLE_INTRP_BITS 1 +#define I2C_IIC_ENABLE_INTRP_SHIFT 1 + +/* I2C :: IIC_ENABLE :: ENABLE [00:00] */ +#define I2C_IIC_ENABLE_ENABLE_MASK 0x00000001 +#define I2C_IIC_ENABLE_ENABLE_ALIGN 0 +#define I2C_IIC_ENABLE_ENABLE_BITS 1 +#define I2C_IIC_ENABLE_ENABLE_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT0 + ***************************************************************************/ +/* I2C :: DATA_OUT0 :: reserved0 [31:08] */ +#define I2C_DATA_OUT0_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT0_reserved0_ALIGN 0 +#define I2C_DATA_OUT0_reserved0_BITS 24 +#define I2C_DATA_OUT0_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT0 :: DATA_OUT0 [07:00] */ +#define I2C_DATA_OUT0_DATA_OUT0_MASK 0x000000ff +#define I2C_DATA_OUT0_DATA_OUT0_ALIGN 0 +#define I2C_DATA_OUT0_DATA_OUT0_BITS 8 +#define I2C_DATA_OUT0_DATA_OUT0_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT1 + ***************************************************************************/ +/* I2C :: DATA_OUT1 :: reserved0 [31:08] */ +#define I2C_DATA_OUT1_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT1_reserved0_ALIGN 0 +#define I2C_DATA_OUT1_reserved0_BITS 24 +#define I2C_DATA_OUT1_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT1 :: DATA_OUT1 [07:00] */ +#define I2C_DATA_OUT1_DATA_OUT1_MASK 0x000000ff +#define I2C_DATA_OUT1_DATA_OUT1_ALIGN 0 +#define I2C_DATA_OUT1_DATA_OUT1_BITS 8 +#define I2C_DATA_OUT1_DATA_OUT1_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT2 + ***************************************************************************/ +/* I2C :: DATA_OUT2 :: reserved0 [31:08] */ +#define I2C_DATA_OUT2_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT2_reserved0_ALIGN 0 +#define I2C_DATA_OUT2_reserved0_BITS 24 +#define I2C_DATA_OUT2_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT2 :: DATA_OUT2 [07:00] */ +#define I2C_DATA_OUT2_DATA_OUT2_MASK 0x000000ff +#define I2C_DATA_OUT2_DATA_OUT2_ALIGN 0 +#define I2C_DATA_OUT2_DATA_OUT2_BITS 8 +#define I2C_DATA_OUT2_DATA_OUT2_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT3 + ***************************************************************************/ +/* I2C :: DATA_OUT3 :: reserved0 [31:08] */ +#define I2C_DATA_OUT3_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT3_reserved0_ALIGN 0 +#define I2C_DATA_OUT3_reserved0_BITS 24 +#define I2C_DATA_OUT3_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT3 :: DATA_OUT3 [07:00] */ +#define I2C_DATA_OUT3_DATA_OUT3_MASK 0x000000ff +#define I2C_DATA_OUT3_DATA_OUT3_ALIGN 0 +#define I2C_DATA_OUT3_DATA_OUT3_BITS 8 +#define I2C_DATA_OUT3_DATA_OUT3_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT4 + ***************************************************************************/ +/* I2C :: DATA_OUT4 :: reserved0 [31:08] */ +#define I2C_DATA_OUT4_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT4_reserved0_ALIGN 0 +#define I2C_DATA_OUT4_reserved0_BITS 24 +#define I2C_DATA_OUT4_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT4 :: DATA_OUT4 [07:00] */ +#define I2C_DATA_OUT4_DATA_OUT4_MASK 0x000000ff +#define I2C_DATA_OUT4_DATA_OUT4_ALIGN 0 +#define I2C_DATA_OUT4_DATA_OUT4_BITS 8 +#define I2C_DATA_OUT4_DATA_OUT4_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT5 + ***************************************************************************/ +/* I2C :: DATA_OUT5 :: reserved0 [31:08] */ +#define I2C_DATA_OUT5_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT5_reserved0_ALIGN 0 +#define I2C_DATA_OUT5_reserved0_BITS 24 +#define I2C_DATA_OUT5_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT5 :: DATA_OUT5 [07:00] */ +#define I2C_DATA_OUT5_DATA_OUT5_MASK 0x000000ff +#define I2C_DATA_OUT5_DATA_OUT5_ALIGN 0 +#define I2C_DATA_OUT5_DATA_OUT5_BITS 8 +#define I2C_DATA_OUT5_DATA_OUT5_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT6 + ***************************************************************************/ +/* I2C :: DATA_OUT6 :: reserved0 [31:08] */ +#define I2C_DATA_OUT6_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT6_reserved0_ALIGN 0 +#define I2C_DATA_OUT6_reserved0_BITS 24 +#define I2C_DATA_OUT6_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT6 :: DATA_OUT6 [07:00] */ +#define I2C_DATA_OUT6_DATA_OUT6_MASK 0x000000ff +#define I2C_DATA_OUT6_DATA_OUT6_ALIGN 0 +#define I2C_DATA_OUT6_DATA_OUT6_BITS 8 +#define I2C_DATA_OUT6_DATA_OUT6_SHIFT 0 + + +/**************************************************************************** + * I2C :: DATA_OUT7 + ***************************************************************************/ +/* I2C :: DATA_OUT7 :: reserved0 [31:08] */ +#define I2C_DATA_OUT7_reserved0_MASK 0xffffff00 +#define I2C_DATA_OUT7_reserved0_ALIGN 0 +#define I2C_DATA_OUT7_reserved0_BITS 24 +#define I2C_DATA_OUT7_reserved0_SHIFT 8 + +/* I2C :: DATA_OUT7 :: DATA_OUT7 [07:00] */ +#define I2C_DATA_OUT7_DATA_OUT7_MASK 0x000000ff +#define I2C_DATA_OUT7_DATA_OUT7_ALIGN 0 +#define I2C_DATA_OUT7_DATA_OUT7_BITS 8 +#define I2C_DATA_OUT7_DATA_OUT7_SHIFT 0 + + +/**************************************************************************** + * I2C :: CTLHI_REG + ***************************************************************************/ +/* I2C :: CTLHI_REG :: reserved0 [31:02] */ +#define I2C_CTLHI_REG_reserved0_MASK 0xfffffffc +#define I2C_CTLHI_REG_reserved0_ALIGN 0 +#define I2C_CTLHI_REG_reserved0_BITS 30 +#define I2C_CTLHI_REG_reserved0_SHIFT 2 + +/* I2C :: CTLHI_REG :: IGNORE_ACK [01:01] */ +#define I2C_CTLHI_REG_IGNORE_ACK_MASK 0x00000002 +#define I2C_CTLHI_REG_IGNORE_ACK_ALIGN 0 +#define I2C_CTLHI_REG_IGNORE_ACK_BITS 1 +#define I2C_CTLHI_REG_IGNORE_ACK_SHIFT 1 + +/* I2C :: CTLHI_REG :: WAIT_DIS [00:00] */ +#define I2C_CTLHI_REG_WAIT_DIS_MASK 0x00000001 +#define I2C_CTLHI_REG_WAIT_DIS_ALIGN 0 +#define I2C_CTLHI_REG_WAIT_DIS_BITS 1 +#define I2C_CTLHI_REG_WAIT_DIS_SHIFT 0 + + +/**************************************************************************** + * I2C :: SCL_PARAM + ***************************************************************************/ +/* I2C :: SCL_PARAM :: reserved0 [31:00] */ +#define I2C_SCL_PARAM_reserved0_MASK 0xffffffff +#define I2C_SCL_PARAM_reserved0_ALIGN 0 +#define I2C_SCL_PARAM_reserved0_BITS 32 +#define I2C_SCL_PARAM_reserved0_SHIFT 0 + + +/**************************************************************************** + * BCM70012_I2C_TOP_I2C_GR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * I2C_GR_BRIDGE :: REVISION + ***************************************************************************/ +/* I2C_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define I2C_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define I2C_GR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define I2C_GR_BRIDGE_REVISION_reserved0_BITS 16 +#define I2C_GR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* I2C_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define I2C_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define I2C_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define I2C_GR_BRIDGE_REVISION_MAJOR_BITS 8 +#define I2C_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* I2C_GR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define I2C_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define I2C_GR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define I2C_GR_BRIDGE_REVISION_MINOR_BITS 8 +#define I2C_GR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * I2C_GR_BRIDGE :: CTRL + ***************************************************************************/ +/* I2C_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ +#define I2C_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe +#define I2C_GR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define I2C_GR_BRIDGE_CTRL_reserved0_BITS 31 +#define I2C_GR_BRIDGE_CTRL_reserved0_SHIFT 1 + +/* I2C_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + + +/**************************************************************************** + * I2C_GR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * I2C_GR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 +#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC1 + ***************************************************************************/ +/**************************************************************************** + * MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 + ***************************************************************************/ +/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 + +/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 + +/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: TX_DESC_LIST0_VALID [00:00] */ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_MASK 0x00000001 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_ALIGN 0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_BITS 1 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_FIRST_DESC_U_ADDR_LIST0 + ***************************************************************************/ +/* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 + ***************************************************************************/ +/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 + +/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 + +/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: TX_DESC_LIST1_VALID [00:00] */ +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_MASK 0x00000001 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_ALIGN 0 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_BITS 1 +#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_FIRST_DESC_U_ADDR_LIST1 + ***************************************************************************/ +/* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 +#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_SW_DESC_LIST_CTRL_STS + ***************************************************************************/ +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 + +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 + +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 + +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_HALT_ON_ERROR [01:01] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_MASK 0x00000002 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_BITS 1 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_SHIFT 1 + +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_BITS 1 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_ERROR_STATUS + ***************************************************************************/ +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved0 [31:10] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved0_MASK 0xfffffc00 +#define MISC1_TX_DMA_ERROR_STATUS_reserved0_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved0_BITS 22 +#define MISC1_TX_DMA_ERROR_STATUS_reserved0_SHIFT 10 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved1 [08:08] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved1_MASK 0x00000100 +#define MISC1_TX_DMA_ERROR_STATUS_reserved1_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved1_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_reserved1_SHIFT 8 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved2 [06:06] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved2_MASK 0x00000040 +#define MISC1_TX_DMA_ERROR_STATUS_reserved2_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved2_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_reserved2_SHIFT 6 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DMA_DATA_TX_ABORT_ERRORS [05:05] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000020 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_SHIFT 5 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_FIFO_FULL_ERRORS [04:04] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_SHIFT 4 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved3 [03:03] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved3_MASK 0x00000008 +#define MISC1_TX_DMA_ERROR_STATUS_reserved3_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved3_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_reserved3_SHIFT 3 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DMA_DATA_TX_ABORT_ERRORS [02:02] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000004 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_SHIFT 2 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_FIFO_FULL_ERRORS [01:01] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_SHIFT 1 + +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved4 [00:00] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved4_MASK 0x00000001 +#define MISC1_TX_DMA_ERROR_STATUS_reserved4_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved4_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_reserved4_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR + ***************************************************************************/ +/* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: TX_DMA_L0_CUR_DESC_L_ADDR [31:05] */ +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_ALIGN 0 +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_BITS 27 +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_SHIFT 5 + +/* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 +#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_LIST0_CUR_DESC_U_ADDR + ***************************************************************************/ +/* MISC1 :: TX_DMA_LIST0_CUR_DESC_U_ADDR :: TX_DMA_L0_CUR_DESC_U_ADDR [31:00] */ +#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_MASK 0xffffffff +#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_ALIGN 0 +#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_BITS 32 +#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM + ***************************************************************************/ +/* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_ALIGN 0 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_BITS 8 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 + +/* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: TX_DMA_L0_CUR_BYTE_CNT_REM [23:02] */ +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_MASK 0x00fffffc +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_ALIGN 0 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_BITS 22 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_SHIFT 2 + +/* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_ALIGN 0 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_BITS 2 +#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR + ***************************************************************************/ +/* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: TX_DMA_L1_CUR_DESC_L_ADDR [31:05] */ +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_ALIGN 0 +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_BITS 27 +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_SHIFT 5 + +/* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 +#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_LIST1_CUR_DESC_U_ADDR + ***************************************************************************/ +/* MISC1 :: TX_DMA_LIST1_CUR_DESC_U_ADDR :: TX_DMA_L1_CUR_DESC_U_ADDR [31:00] */ +#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_MASK 0xffffffff +#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_ALIGN 0 +#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_BITS 32 +#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM + ***************************************************************************/ +/* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_ALIGN 0 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_BITS 8 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 + +/* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: TX_DMA_L1_CUR_BYTE_CNT_REM [23:02] */ +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_MASK 0x00fffffc +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_ALIGN 0 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_BITS 22 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_SHIFT 2 + +/* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_ALIGN 0 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_BITS 2 +#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 + ***************************************************************************/ +/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 + +/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 + +/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_BITS 1 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST0 + ***************************************************************************/ +/* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 + ***************************************************************************/ +/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 + +/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 + +/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_BITS 1 +#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST1 + ***************************************************************************/ +/* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 +#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS + ***************************************************************************/ +/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 + +/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 + +/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 + +/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_ALIGN 0 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_BITS 1 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 + +/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_ALIGN 0 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_BITS 1 +#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_ERROR_STATUS + ***************************************************************************/ +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved0 [31:14] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 +#define MISC1_Y_RX_ERROR_STATUS_reserved0_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved0_BITS 18 +#define MISC1_Y_RX_ERROR_STATUS_reserved0_SHIFT 14 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 + +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved1 [08:08] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved1_MASK 0x00000100 +#define MISC1_Y_RX_ERROR_STATUS_reserved1_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved1_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_reserved1_SHIFT 8 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 + +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved2 [06:05] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved2_MASK 0x00000060 +#define MISC1_Y_RX_ERROR_STATUS_reserved2_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved2_BITS 2 +#define MISC1_Y_RX_ERROR_STATUS_reserved2_SHIFT 5 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 + +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved3 [03:02] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved3_MASK 0x0000000c +#define MISC1_Y_RX_ERROR_STATUS_reserved3_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved3_BITS 2 +#define MISC1_Y_RX_ERROR_STATUS_reserved3_SHIFT 2 + +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 + +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved4 [00:00] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved4_MASK 0x00000001 +#define MISC1_Y_RX_ERROR_STATUS_reserved4_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved4_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_reserved4_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR + ***************************************************************************/ +/* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_ALIGN 0 +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_BITS 27 +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 + +/* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 +#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_LIST0_CUR_DESC_U_ADDR + ***************************************************************************/ +/* MISC1 :: Y_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ +#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff +#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_ALIGN 0 +#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_BITS 32 +#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_LIST0_CUR_BYTE_CNT + ***************************************************************************/ +/* MISC1 :: Y_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ +#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff +#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_ALIGN 0 +#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_BITS 32 +#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR + ***************************************************************************/ +/* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_ALIGN 0 +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_BITS 27 +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 + +/* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 +#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_LIST1_CUR_DESC_U_ADDR + ***************************************************************************/ +/* MISC1 :: Y_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ +#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff +#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_ALIGN 0 +#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_BITS 32 +#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: Y_RX_LIST1_CUR_BYTE_CNT + ***************************************************************************/ +/* MISC1 :: Y_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ +#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff +#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_ALIGN 0 +#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_BITS 32 +#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 + ***************************************************************************/ +/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 + +/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 + +/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_BITS 1 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST0 + ***************************************************************************/ +/* MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 + ***************************************************************************/ +/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 + +/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 + +/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_BITS 1 +#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST1 + ***************************************************************************/ +/* MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 +#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS + ***************************************************************************/ +/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 + +/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 + +/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 + +/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_ALIGN 0 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_BITS 1 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 + +/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_ALIGN 0 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_BITS 1 +#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_ERROR_STATUS + ***************************************************************************/ +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved0 [31:14] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 +#define MISC1_UV_RX_ERROR_STATUS_reserved0_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved0_BITS 18 +#define MISC1_UV_RX_ERROR_STATUS_reserved0_SHIFT 14 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 + +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved1 [08:08] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved1_MASK 0x00000100 +#define MISC1_UV_RX_ERROR_STATUS_reserved1_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved1_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_reserved1_SHIFT 8 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 + +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved2 [06:05] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved2_MASK 0x00000060 +#define MISC1_UV_RX_ERROR_STATUS_reserved2_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved2_BITS 2 +#define MISC1_UV_RX_ERROR_STATUS_reserved2_SHIFT 5 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 + +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved3 [03:02] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved3_MASK 0x0000000c +#define MISC1_UV_RX_ERROR_STATUS_reserved3_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved3_BITS 2 +#define MISC1_UV_RX_ERROR_STATUS_reserved3_SHIFT 2 + +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 + +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved4 [00:00] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved4_MASK 0x00000001 +#define MISC1_UV_RX_ERROR_STATUS_reserved4_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved4_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_reserved4_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR + ***************************************************************************/ +/* MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_ALIGN 0 +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_BITS 27 +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 + +/* MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 +#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_LIST0_CUR_DESC_U_ADDR + ***************************************************************************/ +/* MISC1 :: UV_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ +#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff +#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_ALIGN 0 +#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_BITS 32 +#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_LIST0_CUR_BYTE_CNT + ***************************************************************************/ +/* MISC1 :: UV_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ +#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff +#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_ALIGN 0 +#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_BITS 32 +#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR + ***************************************************************************/ +/* MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_ALIGN 0 +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_BITS 27 +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 + +/* MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 +#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_LIST1_CUR_DESC_U_ADDR + ***************************************************************************/ +/* MISC1 :: UV_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ +#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff +#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_ALIGN 0 +#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_BITS 32 +#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: UV_RX_LIST1_CUR_BYTE_CNT + ***************************************************************************/ +/* MISC1 :: UV_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ +#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff +#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_ALIGN 0 +#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_BITS 32 +#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: DMA_DEBUG_OPTIONS_REG + ***************************************************************************/ +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_SOFT_RST [31:31] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_MASK 0x80000000 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_SHIFT 31 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_SOFT_RST [30:30] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_MASK 0x40000000 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_SHIFT 30 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST [29:29] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_MASK 0x20000000 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_SHIFT 29 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST [28:28] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_MASK 0x10000000 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_SHIFT 28 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_0 [27:05] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_MASK 0x0fffffe0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_BITS 23 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_SHIFT 5 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_EN_RX_DMA_XFER_CNT [04:04] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_MASK 0x00000010 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_SHIFT 4 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_1 [03:03] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_MASK 0x00000008 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_SHIFT 3 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_RD_Q [02:02] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_MASK 0x00000004 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_SHIFT 2 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_WR_Q [01:01] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_MASK 0x00000002 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_SHIFT 1 + +/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_2 [00:00] */ +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_MASK 0x00000001 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_ALIGN 0 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_BITS 1 +#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: READ_CHANNEL_ERROR_STATUS + ***************************************************************************/ +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_7 [31:28] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_MASK 0xf0000000 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_SHIFT 28 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_6 [27:24] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_MASK 0x0f000000 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_SHIFT 24 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_5 [23:20] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_MASK 0x00f00000 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_SHIFT 20 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_4 [19:16] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_MASK 0x000f0000 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_SHIFT 16 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_3 [15:12] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_MASK 0x0000f000 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_SHIFT 12 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_2 [11:08] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_MASK 0x00000f00 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_SHIFT 8 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_1 [07:04] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_MASK 0x000000f0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_SHIFT 4 + +/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_0 [03:00] */ +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_MASK 0x0000000f +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_ALIGN 0 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_BITS 4 +#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_SHIFT 0 + + +/**************************************************************************** + * MISC1 :: PCIE_DMA_CTRL + ***************************************************************************/ +/* MISC1 :: PCIE_DMA_CTRL :: reserved0 [31:18] */ +#define MISC1_PCIE_DMA_CTRL_reserved0_MASK 0xfffc0000 +#define MISC1_PCIE_DMA_CTRL_reserved0_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_reserved0_BITS 14 +#define MISC1_PCIE_DMA_CTRL_reserved0_SHIFT 18 + +/* MISC1 :: PCIE_DMA_CTRL :: DESC_ENDIAN_MODE [17:16] */ +#define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_MASK 0x00030000 +#define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_BITS 2 +#define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_SHIFT 16 + +/* MISC1 :: PCIE_DMA_CTRL :: reserved1 [15:10] */ +#define MISC1_PCIE_DMA_CTRL_reserved1_MASK 0x0000fc00 +#define MISC1_PCIE_DMA_CTRL_reserved1_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_reserved1_BITS 6 +#define MISC1_PCIE_DMA_CTRL_reserved1_SHIFT 10 + +/* MISC1 :: PCIE_DMA_CTRL :: EN_WEIGHTED_RR [09:09] */ +#define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_MASK 0x00000200 +#define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_BITS 1 +#define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_SHIFT 9 + +/* MISC1 :: PCIE_DMA_CTRL :: EN_ROUND_ROBIN [08:08] */ +#define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_MASK 0x00000100 +#define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_BITS 1 +#define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_SHIFT 8 + +/* MISC1 :: PCIE_DMA_CTRL :: reserved2 [07:05] */ +#define MISC1_PCIE_DMA_CTRL_reserved2_MASK 0x000000e0 +#define MISC1_PCIE_DMA_CTRL_reserved2_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_reserved2_BITS 3 +#define MISC1_PCIE_DMA_CTRL_reserved2_SHIFT 5 + +/* MISC1 :: PCIE_DMA_CTRL :: RELAXED_ORDERING [04:04] */ +#define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_MASK 0x00000010 +#define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_BITS 1 +#define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_SHIFT 4 + +/* MISC1 :: PCIE_DMA_CTRL :: NO_SNOOP [03:03] */ +#define MISC1_PCIE_DMA_CTRL_NO_SNOOP_MASK 0x00000008 +#define MISC1_PCIE_DMA_CTRL_NO_SNOOP_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_NO_SNOOP_BITS 1 +#define MISC1_PCIE_DMA_CTRL_NO_SNOOP_SHIFT 3 + +/* MISC1 :: PCIE_DMA_CTRL :: TRAFFIC_CLASS [02:00] */ +#define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_MASK 0x00000007 +#define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_ALIGN 0 +#define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_BITS 3 +#define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_SHIFT 0 + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC2 + ***************************************************************************/ +/**************************************************************************** + * MISC2 :: GLOBAL_CTRL + ***************************************************************************/ +/* MISC2 :: GLOBAL_CTRL :: reserved0 [31:21] */ +#define MISC2_GLOBAL_CTRL_reserved0_MASK 0xffe00000 +#define MISC2_GLOBAL_CTRL_reserved0_ALIGN 0 +#define MISC2_GLOBAL_CTRL_reserved0_BITS 11 +#define MISC2_GLOBAL_CTRL_reserved0_SHIFT 21 + +/* MISC2 :: GLOBAL_CTRL :: EN_WRITE_ALL [20:20] */ +#define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_MASK 0x00100000 +#define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_ALIGN 0 +#define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_BITS 1 +#define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_SHIFT 20 + +/* MISC2 :: GLOBAL_CTRL :: reserved1 [19:17] */ +#define MISC2_GLOBAL_CTRL_reserved1_MASK 0x000e0000 +#define MISC2_GLOBAL_CTRL_reserved1_ALIGN 0 +#define MISC2_GLOBAL_CTRL_reserved1_BITS 3 +#define MISC2_GLOBAL_CTRL_reserved1_SHIFT 17 + +/* MISC2 :: GLOBAL_CTRL :: EN_SINGLE_DMA [16:16] */ +#define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_MASK 0x00010000 +#define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_ALIGN 0 +#define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_BITS 1 +#define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_SHIFT 16 + +/* MISC2 :: GLOBAL_CTRL :: reserved2 [15:11] */ +#define MISC2_GLOBAL_CTRL_reserved2_MASK 0x0000f800 +#define MISC2_GLOBAL_CTRL_reserved2_ALIGN 0 +#define MISC2_GLOBAL_CTRL_reserved2_BITS 5 +#define MISC2_GLOBAL_CTRL_reserved2_SHIFT 11 + +/* MISC2 :: GLOBAL_CTRL :: Y_UV_FIFO_LEN_SEL [10:10] */ +#define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_MASK 0x00000400 +#define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_ALIGN 0 +#define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_BITS 1 +#define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_SHIFT 10 + +/* MISC2 :: GLOBAL_CTRL :: ODD_DE_EOFRST_DIS [09:09] */ +#define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_MASK 0x00000200 +#define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_ALIGN 0 +#define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_BITS 1 +#define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_SHIFT 9 + +/* MISC2 :: GLOBAL_CTRL :: DIS_BIT_STUFFING [08:08] */ +#define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_MASK 0x00000100 +#define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_ALIGN 0 +#define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_BITS 1 +#define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_SHIFT 8 + +/* MISC2 :: GLOBAL_CTRL :: reserved3 [07:05] */ +#define MISC2_GLOBAL_CTRL_reserved3_MASK 0x000000e0 +#define MISC2_GLOBAL_CTRL_reserved3_ALIGN 0 +#define MISC2_GLOBAL_CTRL_reserved3_BITS 3 +#define MISC2_GLOBAL_CTRL_reserved3_SHIFT 5 + +/* MISC2 :: GLOBAL_CTRL :: EN_PROG_MODE [04:04] */ +#define MISC2_GLOBAL_CTRL_EN_PROG_MODE_MASK 0x00000010 +#define MISC2_GLOBAL_CTRL_EN_PROG_MODE_ALIGN 0 +#define MISC2_GLOBAL_CTRL_EN_PROG_MODE_BITS 1 +#define MISC2_GLOBAL_CTRL_EN_PROG_MODE_SHIFT 4 + +/* MISC2 :: GLOBAL_CTRL :: reserved4 [03:01] */ +#define MISC2_GLOBAL_CTRL_reserved4_MASK 0x0000000e +#define MISC2_GLOBAL_CTRL_reserved4_ALIGN 0 +#define MISC2_GLOBAL_CTRL_reserved4_BITS 3 +#define MISC2_GLOBAL_CTRL_reserved4_SHIFT 1 + +/* MISC2 :: GLOBAL_CTRL :: EN_188B [00:00] */ +#define MISC2_GLOBAL_CTRL_EN_188B_MASK 0x00000001 +#define MISC2_GLOBAL_CTRL_EN_188B_ALIGN 0 +#define MISC2_GLOBAL_CTRL_EN_188B_BITS 1 +#define MISC2_GLOBAL_CTRL_EN_188B_SHIFT 0 + + +/**************************************************************************** + * MISC2 :: INTERNAL_STATUS + ***************************************************************************/ +/* MISC2 :: INTERNAL_STATUS :: reserved0 [31:12] */ +#define MISC2_INTERNAL_STATUS_reserved0_MASK 0xfffff000 +#define MISC2_INTERNAL_STATUS_reserved0_ALIGN 0 +#define MISC2_INTERNAL_STATUS_reserved0_BITS 20 +#define MISC2_INTERNAL_STATUS_reserved0_SHIFT 12 + +/* MISC2 :: INTERNAL_STATUS :: UV_BYTE_COUNT_FIFO_FULL [11:11] */ +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_MASK 0x00000800 +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_BITS 1 +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_SHIFT 11 + +/* MISC2 :: INTERNAL_STATUS :: UV_DATA_FIFO_FULL [10:10] */ +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_MASK 0x00000400 +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_BITS 1 +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_SHIFT 10 + +/* MISC2 :: INTERNAL_STATUS :: Y_BYTE_COUNT_FIFO_FULL [09:09] */ +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_MASK 0x00000200 +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_BITS 1 +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_SHIFT 9 + +/* MISC2 :: INTERNAL_STATUS :: Y_DATA_FIFO_FULL [08:08] */ +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_MASK 0x00000100 +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_BITS 1 +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_SHIFT 8 + +/* MISC2 :: INTERNAL_STATUS :: UV_BYTE_COUNT_FIFO_EMPTY [07:07] */ +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_MASK 0x00000080 +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_ALIGN 0 +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_BITS 1 +#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_SHIFT 7 + +/* MISC2 :: INTERNAL_STATUS :: UV_DATA_FIFO_EMPTY [06:06] */ +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_MASK 0x00000040 +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_ALIGN 0 +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_BITS 1 +#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_SHIFT 6 + +/* MISC2 :: INTERNAL_STATUS :: Y_BYTE_COUNT_FIFO_EMPTY [05:05] */ +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_MASK 0x00000020 +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_ALIGN 0 +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_BITS 1 +#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_SHIFT 5 + +/* MISC2 :: INTERNAL_STATUS :: Y_DATA_FIFO_EMPTY [04:04] */ +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_MASK 0x00000010 +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_ALIGN 0 +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_BITS 1 +#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_SHIFT 4 + +/* MISC2 :: INTERNAL_STATUS :: reserved1 [03:00] */ +#define MISC2_INTERNAL_STATUS_reserved1_MASK 0x0000000f +#define MISC2_INTERNAL_STATUS_reserved1_ALIGN 0 +#define MISC2_INTERNAL_STATUS_reserved1_BITS 4 +#define MISC2_INTERNAL_STATUS_reserved1_SHIFT 0 + + +/**************************************************************************** + * MISC2 :: INTERNAL_STATUS_MUX_CTRL + ***************************************************************************/ +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved0 [31:16] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_MASK 0xffff0000 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_BITS 16 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_SHIFT 16 + +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: CLK_OUT_ALT_SRC [15:15] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_MASK 0x00008000 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_BITS 1 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_SHIFT 15 + +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CLK_SEL [14:12] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_MASK 0x00007000 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_BITS 3 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_SHIFT 12 + +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved1 [11:09] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_MASK 0x00000e00 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_BITS 3 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_SHIFT 9 + +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_TOP_CORE_SEL [08:08] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_MASK 0x00000100 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_BITS 1 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_SHIFT 8 + +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CORE_BLK_SEL [07:04] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_MASK 0x000000f0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_BITS 4 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_SHIFT 4 + +/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_VECTOR_SEL [03:00] */ +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_MASK 0x0000000f +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_ALIGN 0 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_BITS 4 +#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_SHIFT 0 + + +/**************************************************************************** + * MISC2 :: DEBUG_FIFO_LENGTH + ***************************************************************************/ +/* MISC2 :: DEBUG_FIFO_LENGTH :: reserved0 [31:21] */ +#define MISC2_DEBUG_FIFO_LENGTH_reserved0_MASK 0xffe00000 +#define MISC2_DEBUG_FIFO_LENGTH_reserved0_ALIGN 0 +#define MISC2_DEBUG_FIFO_LENGTH_reserved0_BITS 11 +#define MISC2_DEBUG_FIFO_LENGTH_reserved0_SHIFT 21 + +/* MISC2 :: DEBUG_FIFO_LENGTH :: FIFO_LENGTH [20:00] */ +#define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_MASK 0x001fffff +#define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_ALIGN 0 +#define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_BITS 21 +#define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_SHIFT 0 + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC3 + ***************************************************************************/ +/**************************************************************************** + * MISC3 :: RESET_CTRL + ***************************************************************************/ +/* MISC3 :: RESET_CTRL :: reserved0 [31:09] */ +#define MISC3_RESET_CTRL_reserved0_MASK 0xfffffe00 +#define MISC3_RESET_CTRL_reserved0_ALIGN 0 +#define MISC3_RESET_CTRL_reserved0_BITS 23 +#define MISC3_RESET_CTRL_reserved0_SHIFT 9 + +/* MISC3 :: RESET_CTRL :: PLL_RESET [08:08] */ +#define MISC3_RESET_CTRL_PLL_RESET_MASK 0x00000100 +#define MISC3_RESET_CTRL_PLL_RESET_ALIGN 0 +#define MISC3_RESET_CTRL_PLL_RESET_BITS 1 +#define MISC3_RESET_CTRL_PLL_RESET_SHIFT 8 + +/* MISC3 :: RESET_CTRL :: reserved1 [07:02] */ +#define MISC3_RESET_CTRL_reserved1_MASK 0x000000fc +#define MISC3_RESET_CTRL_reserved1_ALIGN 0 +#define MISC3_RESET_CTRL_reserved1_BITS 6 +#define MISC3_RESET_CTRL_reserved1_SHIFT 2 + +/* MISC3 :: RESET_CTRL :: POR_RESET [01:01] */ +#define MISC3_RESET_CTRL_POR_RESET_MASK 0x00000002 +#define MISC3_RESET_CTRL_POR_RESET_ALIGN 0 +#define MISC3_RESET_CTRL_POR_RESET_BITS 1 +#define MISC3_RESET_CTRL_POR_RESET_SHIFT 1 + +/* MISC3 :: RESET_CTRL :: CORE_RESET [00:00] */ +#define MISC3_RESET_CTRL_CORE_RESET_MASK 0x00000001 +#define MISC3_RESET_CTRL_CORE_RESET_ALIGN 0 +#define MISC3_RESET_CTRL_CORE_RESET_BITS 1 +#define MISC3_RESET_CTRL_CORE_RESET_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: BIST_CTRL + ***************************************************************************/ +/* MISC3 :: BIST_CTRL :: MBIST_OVERRIDE [31:31] */ +#define MISC3_BIST_CTRL_MBIST_OVERRIDE_MASK 0x80000000 +#define MISC3_BIST_CTRL_MBIST_OVERRIDE_ALIGN 0 +#define MISC3_BIST_CTRL_MBIST_OVERRIDE_BITS 1 +#define MISC3_BIST_CTRL_MBIST_OVERRIDE_SHIFT 31 + +/* MISC3 :: BIST_CTRL :: reserved0 [30:15] */ +#define MISC3_BIST_CTRL_reserved0_MASK 0x7fff8000 +#define MISC3_BIST_CTRL_reserved0_ALIGN 0 +#define MISC3_BIST_CTRL_reserved0_BITS 16 +#define MISC3_BIST_CTRL_reserved0_SHIFT 15 + +/* MISC3 :: BIST_CTRL :: MBIST_EN_2 [14:14] */ +#define MISC3_BIST_CTRL_MBIST_EN_2_MASK 0x00004000 +#define MISC3_BIST_CTRL_MBIST_EN_2_ALIGN 0 +#define MISC3_BIST_CTRL_MBIST_EN_2_BITS 1 +#define MISC3_BIST_CTRL_MBIST_EN_2_SHIFT 14 + +/* MISC3 :: BIST_CTRL :: MBIST_EN_1 [13:13] */ +#define MISC3_BIST_CTRL_MBIST_EN_1_MASK 0x00002000 +#define MISC3_BIST_CTRL_MBIST_EN_1_ALIGN 0 +#define MISC3_BIST_CTRL_MBIST_EN_1_BITS 1 +#define MISC3_BIST_CTRL_MBIST_EN_1_SHIFT 13 + +/* MISC3 :: BIST_CTRL :: MBIST_EN_0 [12:12] */ +#define MISC3_BIST_CTRL_MBIST_EN_0_MASK 0x00001000 +#define MISC3_BIST_CTRL_MBIST_EN_0_ALIGN 0 +#define MISC3_BIST_CTRL_MBIST_EN_0_BITS 1 +#define MISC3_BIST_CTRL_MBIST_EN_0_SHIFT 12 + +/* MISC3 :: BIST_CTRL :: reserved1 [11:06] */ +#define MISC3_BIST_CTRL_reserved1_MASK 0x00000fc0 +#define MISC3_BIST_CTRL_reserved1_ALIGN 0 +#define MISC3_BIST_CTRL_reserved1_BITS 6 +#define MISC3_BIST_CTRL_reserved1_SHIFT 6 + +/* MISC3 :: BIST_CTRL :: MBIST_SETUP [05:04] */ +#define MISC3_BIST_CTRL_MBIST_SETUP_MASK 0x00000030 +#define MISC3_BIST_CTRL_MBIST_SETUP_ALIGN 0 +#define MISC3_BIST_CTRL_MBIST_SETUP_BITS 2 +#define MISC3_BIST_CTRL_MBIST_SETUP_SHIFT 4 + +/* MISC3 :: BIST_CTRL :: reserved2 [03:01] */ +#define MISC3_BIST_CTRL_reserved2_MASK 0x0000000e +#define MISC3_BIST_CTRL_reserved2_ALIGN 0 +#define MISC3_BIST_CTRL_reserved2_BITS 3 +#define MISC3_BIST_CTRL_reserved2_SHIFT 1 + +/* MISC3 :: BIST_CTRL :: MBIST_ASYNC_RESET [00:00] */ +#define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_MASK 0x00000001 +#define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_ALIGN 0 +#define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_BITS 1 +#define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: BIST_STATUS + ***************************************************************************/ +/* MISC3 :: BIST_STATUS :: reserved0 [31:31] */ +#define MISC3_BIST_STATUS_reserved0_MASK 0x80000000 +#define MISC3_BIST_STATUS_reserved0_ALIGN 0 +#define MISC3_BIST_STATUS_reserved0_BITS 1 +#define MISC3_BIST_STATUS_reserved0_SHIFT 31 + +/* MISC3 :: BIST_STATUS :: MBIST_GO_2 [30:30] */ +#define MISC3_BIST_STATUS_MBIST_GO_2_MASK 0x40000000 +#define MISC3_BIST_STATUS_MBIST_GO_2_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_GO_2_BITS 1 +#define MISC3_BIST_STATUS_MBIST_GO_2_SHIFT 30 + +/* MISC3 :: BIST_STATUS :: MBIST_GO_1 [29:29] */ +#define MISC3_BIST_STATUS_MBIST_GO_1_MASK 0x20000000 +#define MISC3_BIST_STATUS_MBIST_GO_1_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_GO_1_BITS 1 +#define MISC3_BIST_STATUS_MBIST_GO_1_SHIFT 29 + +/* MISC3 :: BIST_STATUS :: MBIST_GO_0 [28:28] */ +#define MISC3_BIST_STATUS_MBIST_GO_0_MASK 0x10000000 +#define MISC3_BIST_STATUS_MBIST_GO_0_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_GO_0_BITS 1 +#define MISC3_BIST_STATUS_MBIST_GO_0_SHIFT 28 + +/* MISC3 :: BIST_STATUS :: reserved1 [27:27] */ +#define MISC3_BIST_STATUS_reserved1_MASK 0x08000000 +#define MISC3_BIST_STATUS_reserved1_ALIGN 0 +#define MISC3_BIST_STATUS_reserved1_BITS 1 +#define MISC3_BIST_STATUS_reserved1_SHIFT 27 + +/* MISC3 :: BIST_STATUS :: MBIST_DONE_2 [26:26] */ +#define MISC3_BIST_STATUS_MBIST_DONE_2_MASK 0x04000000 +#define MISC3_BIST_STATUS_MBIST_DONE_2_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_DONE_2_BITS 1 +#define MISC3_BIST_STATUS_MBIST_DONE_2_SHIFT 26 + +/* MISC3 :: BIST_STATUS :: MBIST_DONE_1 [25:25] */ +#define MISC3_BIST_STATUS_MBIST_DONE_1_MASK 0x02000000 +#define MISC3_BIST_STATUS_MBIST_DONE_1_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_DONE_1_BITS 1 +#define MISC3_BIST_STATUS_MBIST_DONE_1_SHIFT 25 + +/* MISC3 :: BIST_STATUS :: MBIST_DONE_0 [24:24] */ +#define MISC3_BIST_STATUS_MBIST_DONE_0_MASK 0x01000000 +#define MISC3_BIST_STATUS_MBIST_DONE_0_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_DONE_0_BITS 1 +#define MISC3_BIST_STATUS_MBIST_DONE_0_SHIFT 24 + +/* MISC3 :: BIST_STATUS :: reserved2 [23:06] */ +#define MISC3_BIST_STATUS_reserved2_MASK 0x00ffffc0 +#define MISC3_BIST_STATUS_reserved2_ALIGN 0 +#define MISC3_BIST_STATUS_reserved2_BITS 18 +#define MISC3_BIST_STATUS_reserved2_SHIFT 6 + +/* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_2 [05:04] */ +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_MASK 0x00000030 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_BITS 2 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_SHIFT 4 + +/* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_1 [03:02] */ +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_MASK 0x0000000c +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_BITS 2 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_SHIFT 2 + +/* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_0 [01:00] */ +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_MASK 0x00000003 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_ALIGN 0 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_BITS 2 +#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: RX_CHECKSUM + ***************************************************************************/ +/* MISC3 :: RX_CHECKSUM :: RX_CHECKSUM [31:00] */ +#define MISC3_RX_CHECKSUM_RX_CHECKSUM_MASK 0xffffffff +#define MISC3_RX_CHECKSUM_RX_CHECKSUM_ALIGN 0 +#define MISC3_RX_CHECKSUM_RX_CHECKSUM_BITS 32 +#define MISC3_RX_CHECKSUM_RX_CHECKSUM_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: TX_CHECKSUM + ***************************************************************************/ +/* MISC3 :: TX_CHECKSUM :: TX_CHECKSUM [31:00] */ +#define MISC3_TX_CHECKSUM_TX_CHECKSUM_MASK 0xffffffff +#define MISC3_TX_CHECKSUM_TX_CHECKSUM_ALIGN 0 +#define MISC3_TX_CHECKSUM_TX_CHECKSUM_BITS 32 +#define MISC3_TX_CHECKSUM_TX_CHECKSUM_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: ECO_CTRL_CORE + ***************************************************************************/ +/* MISC3 :: ECO_CTRL_CORE :: reserved0 [31:16] */ +#define MISC3_ECO_CTRL_CORE_reserved0_MASK 0xffff0000 +#define MISC3_ECO_CTRL_CORE_reserved0_ALIGN 0 +#define MISC3_ECO_CTRL_CORE_reserved0_BITS 16 +#define MISC3_ECO_CTRL_CORE_reserved0_SHIFT 16 + +/* MISC3 :: ECO_CTRL_CORE :: ECO_CORE_RST_N [15:00] */ +#define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_MASK 0x0000ffff +#define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_ALIGN 0 +#define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_BITS 16 +#define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: CSI_TEST_CTRL + ***************************************************************************/ +/* MISC3 :: CSI_TEST_CTRL :: ENABLE_CSI_TEST [31:31] */ +#define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_MASK 0x80000000 +#define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_ALIGN 0 +#define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_BITS 1 +#define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_SHIFT 31 + +/* MISC3 :: CSI_TEST_CTRL :: reserved0 [30:24] */ +#define MISC3_CSI_TEST_CTRL_reserved0_MASK 0x7f000000 +#define MISC3_CSI_TEST_CTRL_reserved0_ALIGN 0 +#define MISC3_CSI_TEST_CTRL_reserved0_BITS 7 +#define MISC3_CSI_TEST_CTRL_reserved0_SHIFT 24 + +/* MISC3 :: CSI_TEST_CTRL :: CSI_CLOCK_ENABLE [23:16] */ +#define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_MASK 0x00ff0000 +#define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_ALIGN 0 +#define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_BITS 8 +#define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_SHIFT 16 + +/* MISC3 :: CSI_TEST_CTRL :: CSI_SYNC [15:08] */ +#define MISC3_CSI_TEST_CTRL_CSI_SYNC_MASK 0x0000ff00 +#define MISC3_CSI_TEST_CTRL_CSI_SYNC_ALIGN 0 +#define MISC3_CSI_TEST_CTRL_CSI_SYNC_BITS 8 +#define MISC3_CSI_TEST_CTRL_CSI_SYNC_SHIFT 8 + +/* MISC3 :: CSI_TEST_CTRL :: CSI_DATA [07:00] */ +#define MISC3_CSI_TEST_CTRL_CSI_DATA_MASK 0x000000ff +#define MISC3_CSI_TEST_CTRL_CSI_DATA_ALIGN 0 +#define MISC3_CSI_TEST_CTRL_CSI_DATA_BITS 8 +#define MISC3_CSI_TEST_CTRL_CSI_DATA_SHIFT 0 + + +/**************************************************************************** + * MISC3 :: HD_DVI_TEST_CTRL + ***************************************************************************/ +/* MISC3 :: HD_DVI_TEST_CTRL :: reserved0 [31:25] */ +#define MISC3_HD_DVI_TEST_CTRL_reserved0_MASK 0xfe000000 +#define MISC3_HD_DVI_TEST_CTRL_reserved0_ALIGN 0 +#define MISC3_HD_DVI_TEST_CTRL_reserved0_BITS 7 +#define MISC3_HD_DVI_TEST_CTRL_reserved0_SHIFT 25 + +/* MISC3 :: HD_DVI_TEST_CTRL :: POS_VIDO_VBLANK_N [24:24] */ +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_MASK 0x01000000 +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_ALIGN 0 +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_BITS 1 +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_SHIFT 24 + +/* MISC3 :: HD_DVI_TEST_CTRL :: NEG_VIDO_DVI_DATA [23:12] */ +#define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_MASK 0x00fff000 +#define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_ALIGN 0 +#define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_BITS 12 +#define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_SHIFT 12 + +/* MISC3 :: HD_DVI_TEST_CTRL :: POS_VIDO_DVI_DATA [11:00] */ +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_MASK 0x00000fff +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_ALIGN 0 +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_BITS 12 +#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_SHIFT 0 + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC_PERST + ***************************************************************************/ +/**************************************************************************** + * MISC_PERST :: ECO_CTRL_PERST + ***************************************************************************/ +/* MISC_PERST :: ECO_CTRL_PERST :: reserved0 [31:16] */ +#define MISC_PERST_ECO_CTRL_PERST_reserved0_MASK 0xffff0000 +#define MISC_PERST_ECO_CTRL_PERST_reserved0_ALIGN 0 +#define MISC_PERST_ECO_CTRL_PERST_reserved0_BITS 16 +#define MISC_PERST_ECO_CTRL_PERST_reserved0_SHIFT 16 + +/* MISC_PERST :: ECO_CTRL_PERST :: ECO_PERST_N [15:00] */ +#define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_MASK 0x0000ffff +#define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_ALIGN 0 +#define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_BITS 16 +#define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: DECODER_CTRL + ***************************************************************************/ +/* MISC_PERST :: DECODER_CTRL :: reserved0 [31:05] */ +#define MISC_PERST_DECODER_CTRL_reserved0_MASK 0xffffffe0 +#define MISC_PERST_DECODER_CTRL_reserved0_ALIGN 0 +#define MISC_PERST_DECODER_CTRL_reserved0_BITS 27 +#define MISC_PERST_DECODER_CTRL_reserved0_SHIFT 5 + +/* MISC_PERST :: DECODER_CTRL :: STOP_BCM7412_CLK [04:04] */ +#define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_MASK 0x00000010 +#define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_ALIGN 0 +#define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_BITS 1 +#define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_SHIFT 4 + +/* MISC_PERST :: DECODER_CTRL :: reserved1 [03:01] */ +#define MISC_PERST_DECODER_CTRL_reserved1_MASK 0x0000000e +#define MISC_PERST_DECODER_CTRL_reserved1_ALIGN 0 +#define MISC_PERST_DECODER_CTRL_reserved1_BITS 3 +#define MISC_PERST_DECODER_CTRL_reserved1_SHIFT 1 + +/* MISC_PERST :: DECODER_CTRL :: BCM7412_RESET [00:00] */ +#define MISC_PERST_DECODER_CTRL_BCM7412_RESET_MASK 0x00000001 +#define MISC_PERST_DECODER_CTRL_BCM7412_RESET_ALIGN 0 +#define MISC_PERST_DECODER_CTRL_BCM7412_RESET_BITS 1 +#define MISC_PERST_DECODER_CTRL_BCM7412_RESET_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: CCE_STATUS + ***************************************************************************/ +/* MISC_PERST :: CCE_STATUS :: CCE_DONE [31:31] */ +#define MISC_PERST_CCE_STATUS_CCE_DONE_MASK 0x80000000 +#define MISC_PERST_CCE_STATUS_CCE_DONE_ALIGN 0 +#define MISC_PERST_CCE_STATUS_CCE_DONE_BITS 1 +#define MISC_PERST_CCE_STATUS_CCE_DONE_SHIFT 31 + +/* MISC_PERST :: CCE_STATUS :: reserved0 [30:03] */ +#define MISC_PERST_CCE_STATUS_reserved0_MASK 0x7ffffff8 +#define MISC_PERST_CCE_STATUS_reserved0_ALIGN 0 +#define MISC_PERST_CCE_STATUS_reserved0_BITS 28 +#define MISC_PERST_CCE_STATUS_reserved0_SHIFT 3 + +/* MISC_PERST :: CCE_STATUS :: CCE_BAD_GISB_ACCESS [02:02] */ +#define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_MASK 0x00000004 +#define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_ALIGN 0 +#define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_BITS 1 +#define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_SHIFT 2 + +/* MISC_PERST :: CCE_STATUS :: CCE_BAD_I2C_ACCESS [01:01] */ +#define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_MASK 0x00000002 +#define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_ALIGN 0 +#define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_BITS 1 +#define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_SHIFT 1 + +/* MISC_PERST :: CCE_STATUS :: CCE_BAD_SECTION_ID [00:00] */ +#define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_MASK 0x00000001 +#define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_ALIGN 0 +#define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_BITS 1 +#define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: PCIE_DEBUG + ***************************************************************************/ +/* MISC_PERST :: PCIE_DEBUG :: SERDES_TERM_CNT [31:16] */ +#define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_MASK 0xffff0000 +#define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_BITS 16 +#define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_SHIFT 16 + +/* MISC_PERST :: PCIE_DEBUG :: reserved0 [15:11] */ +#define MISC_PERST_PCIE_DEBUG_reserved0_MASK 0x0000f800 +#define MISC_PERST_PCIE_DEBUG_reserved0_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_reserved0_BITS 5 +#define MISC_PERST_PCIE_DEBUG_reserved0_SHIFT 11 + +/* MISC_PERST :: PCIE_DEBUG :: PLL_VCO_RESCUE [10:10] */ +#define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_MASK 0x00000400 +#define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_BITS 1 +#define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_SHIFT 10 + +/* MISC_PERST :: PCIE_DEBUG :: PLL_PDN_OVERRIDE [09:09] */ +#define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_MASK 0x00000200 +#define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_BITS 1 +#define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_SHIFT 9 + +/* MISC_PERST :: PCIE_DEBUG :: CORE_CLOCK_OVR [08:08] */ +#define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_MASK 0x00000100 +#define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_BITS 1 +#define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_SHIFT 8 + +/* MISC_PERST :: PCIE_DEBUG :: reserved1 [07:04] */ +#define MISC_PERST_PCIE_DEBUG_reserved1_MASK 0x000000f0 +#define MISC_PERST_PCIE_DEBUG_reserved1_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_reserved1_BITS 4 +#define MISC_PERST_PCIE_DEBUG_reserved1_SHIFT 4 + +/* MISC_PERST :: PCIE_DEBUG :: PCIE_TMUX_SEL [03:00] */ +#define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_MASK 0x0000000f +#define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_BITS 4 +#define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: PCIE_DEBUG_STATUS + ***************************************************************************/ +/* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved0 [31:06] */ +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_MASK 0xffffffc0 +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_BITS 26 +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_SHIFT 6 + +/* MISC_PERST :: PCIE_DEBUG_STATUS :: DATALINKATTN [05:05] */ +#define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_MASK 0x00000020 +#define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_BITS 1 +#define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_SHIFT 5 + +/* MISC_PERST :: PCIE_DEBUG_STATUS :: PHYLINKATTN [04:04] */ +#define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_MASK 0x00000010 +#define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_BITS 1 +#define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_SHIFT 4 + +/* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved1 [03:02] */ +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_MASK 0x0000000c +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_BITS 2 +#define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_SHIFT 2 + +/* MISC_PERST :: PCIE_DEBUG_STATUS :: DATA_LINKUP [01:01] */ +#define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_MASK 0x00000002 +#define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_BITS 1 +#define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_SHIFT 1 + +/* MISC_PERST :: PCIE_DEBUG_STATUS :: PHY_LINKUP [00:00] */ +#define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_MASK 0x00000001 +#define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_ALIGN 0 +#define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_BITS 1 +#define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: VREG_CTRL + ***************************************************************************/ +/* MISC_PERST :: VREG_CTRL :: reserved0 [31:08] */ +#define MISC_PERST_VREG_CTRL_reserved0_MASK 0xffffff00 +#define MISC_PERST_VREG_CTRL_reserved0_ALIGN 0 +#define MISC_PERST_VREG_CTRL_reserved0_BITS 24 +#define MISC_PERST_VREG_CTRL_reserved0_SHIFT 8 + +/* MISC_PERST :: VREG_CTRL :: VREG1P2_SEL [07:04] */ +#define MISC_PERST_VREG_CTRL_VREG1P2_SEL_MASK 0x000000f0 +#define MISC_PERST_VREG_CTRL_VREG1P2_SEL_ALIGN 0 +#define MISC_PERST_VREG_CTRL_VREG1P2_SEL_BITS 4 +#define MISC_PERST_VREG_CTRL_VREG1P2_SEL_SHIFT 4 + +/* MISC_PERST :: VREG_CTRL :: VREG2P5_SEL [03:00] */ +#define MISC_PERST_VREG_CTRL_VREG2P5_SEL_MASK 0x0000000f +#define MISC_PERST_VREG_CTRL_VREG2P5_SEL_ALIGN 0 +#define MISC_PERST_VREG_CTRL_VREG2P5_SEL_BITS 4 +#define MISC_PERST_VREG_CTRL_VREG2P5_SEL_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: MEM_CTRL + ***************************************************************************/ +/* MISC_PERST :: MEM_CTRL :: reserved0 [31:04] */ +#define MISC_PERST_MEM_CTRL_reserved0_MASK 0xfffffff0 +#define MISC_PERST_MEM_CTRL_reserved0_ALIGN 0 +#define MISC_PERST_MEM_CTRL_reserved0_BITS 28 +#define MISC_PERST_MEM_CTRL_reserved0_SHIFT 4 + +/* MISC_PERST :: MEM_CTRL :: Y_RM [03:03] */ +#define MISC_PERST_MEM_CTRL_Y_RM_MASK 0x00000008 +#define MISC_PERST_MEM_CTRL_Y_RM_ALIGN 0 +#define MISC_PERST_MEM_CTRL_Y_RM_BITS 1 +#define MISC_PERST_MEM_CTRL_Y_RM_SHIFT 3 + +/* MISC_PERST :: MEM_CTRL :: Y_CCM [02:02] */ +#define MISC_PERST_MEM_CTRL_Y_CCM_MASK 0x00000004 +#define MISC_PERST_MEM_CTRL_Y_CCM_ALIGN 0 +#define MISC_PERST_MEM_CTRL_Y_CCM_BITS 1 +#define MISC_PERST_MEM_CTRL_Y_CCM_SHIFT 2 + +/* MISC_PERST :: MEM_CTRL :: UV_RM [01:01] */ +#define MISC_PERST_MEM_CTRL_UV_RM_MASK 0x00000002 +#define MISC_PERST_MEM_CTRL_UV_RM_ALIGN 0 +#define MISC_PERST_MEM_CTRL_UV_RM_BITS 1 +#define MISC_PERST_MEM_CTRL_UV_RM_SHIFT 1 + +/* MISC_PERST :: MEM_CTRL :: UV_CCM [00:00] */ +#define MISC_PERST_MEM_CTRL_UV_CCM_MASK 0x00000001 +#define MISC_PERST_MEM_CTRL_UV_CCM_ALIGN 0 +#define MISC_PERST_MEM_CTRL_UV_CCM_BITS 1 +#define MISC_PERST_MEM_CTRL_UV_CCM_SHIFT 0 + + +/**************************************************************************** + * MISC_PERST :: CLOCK_CTRL + ***************************************************************************/ +/* MISC_PERST :: CLOCK_CTRL :: reserved0 [31:20] */ +#define MISC_PERST_CLOCK_CTRL_reserved0_MASK 0xfff00000 +#define MISC_PERST_CLOCK_CTRL_reserved0_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_reserved0_BITS 12 +#define MISC_PERST_CLOCK_CTRL_reserved0_SHIFT 20 + +/* MISC_PERST :: CLOCK_CTRL :: PLL_DIV [19:16] */ +#define MISC_PERST_CLOCK_CTRL_PLL_DIV_MASK 0x000f0000 +#define MISC_PERST_CLOCK_CTRL_PLL_DIV_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_PLL_DIV_BITS 4 +#define MISC_PERST_CLOCK_CTRL_PLL_DIV_SHIFT 16 + +/* MISC_PERST :: CLOCK_CTRL :: PLL_MULT [15:08] */ +#define MISC_PERST_CLOCK_CTRL_PLL_MULT_MASK 0x0000ff00 +#define MISC_PERST_CLOCK_CTRL_PLL_MULT_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_PLL_MULT_BITS 8 +#define MISC_PERST_CLOCK_CTRL_PLL_MULT_SHIFT 8 + +/* MISC_PERST :: CLOCK_CTRL :: reserved1 [07:03] */ +#define MISC_PERST_CLOCK_CTRL_reserved1_MASK 0x000000f8 +#define MISC_PERST_CLOCK_CTRL_reserved1_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_reserved1_BITS 5 +#define MISC_PERST_CLOCK_CTRL_reserved1_SHIFT 3 + +/* MISC_PERST :: CLOCK_CTRL :: PLL_PWRDOWN [02:02] */ +#define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_MASK 0x00000004 +#define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_BITS 1 +#define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_SHIFT 2 + +/* MISC_PERST :: CLOCK_CTRL :: STOP_CORE_CLK [01:01] */ +#define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_MASK 0x00000002 +#define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_BITS 1 +#define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_SHIFT 1 + +/* MISC_PERST :: CLOCK_CTRL :: SEL_ALT_CLK [00:00] */ +#define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_MASK 0x00000001 +#define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_ALIGN 0 +#define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_BITS 1 +#define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_SHIFT 0 + + +/**************************************************************************** + * BCM70012_MISC_TOP_GISB_ARBITER + ***************************************************************************/ +/**************************************************************************** + * GISB_ARBITER :: REVISION + ***************************************************************************/ +/* GISB_ARBITER :: REVISION :: reserved0 [31:16] */ +#define GISB_ARBITER_REVISION_reserved0_MASK 0xffff0000 +#define GISB_ARBITER_REVISION_reserved0_ALIGN 0 +#define GISB_ARBITER_REVISION_reserved0_BITS 16 +#define GISB_ARBITER_REVISION_reserved0_SHIFT 16 + +/* GISB_ARBITER :: REVISION :: MAJOR [15:08] */ +#define GISB_ARBITER_REVISION_MAJOR_MASK 0x0000ff00 +#define GISB_ARBITER_REVISION_MAJOR_ALIGN 0 +#define GISB_ARBITER_REVISION_MAJOR_BITS 8 +#define GISB_ARBITER_REVISION_MAJOR_SHIFT 8 + +/* GISB_ARBITER :: REVISION :: MINOR [07:00] */ +#define GISB_ARBITER_REVISION_MINOR_MASK 0x000000ff +#define GISB_ARBITER_REVISION_MINOR_ALIGN 0 +#define GISB_ARBITER_REVISION_MINOR_BITS 8 +#define GISB_ARBITER_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: SCRATCH + ***************************************************************************/ +/* GISB_ARBITER :: SCRATCH :: scratch_bit [31:00] */ +#define GISB_ARBITER_SCRATCH_scratch_bit_MASK 0xffffffff +#define GISB_ARBITER_SCRATCH_scratch_bit_ALIGN 0 +#define GISB_ARBITER_SCRATCH_scratch_bit_BITS 32 +#define GISB_ARBITER_SCRATCH_scratch_bit_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: REQ_MASK + ***************************************************************************/ +/* GISB_ARBITER :: REQ_MASK :: reserved0 [31:06] */ +#define GISB_ARBITER_REQ_MASK_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_REQ_MASK_reserved0_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_reserved0_BITS 26 +#define GISB_ARBITER_REQ_MASK_reserved0_SHIFT 6 + +/* GISB_ARBITER :: REQ_MASK :: bsp [05:05] */ +#define GISB_ARBITER_REQ_MASK_bsp_MASK 0x00000020 +#define GISB_ARBITER_REQ_MASK_bsp_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_bsp_BITS 1 +#define GISB_ARBITER_REQ_MASK_bsp_SHIFT 5 +#define GISB_ARBITER_REQ_MASK_bsp_UNMASK 0 + +/* GISB_ARBITER :: REQ_MASK :: tgt [04:04] */ +#define GISB_ARBITER_REQ_MASK_tgt_MASK 0x00000010 +#define GISB_ARBITER_REQ_MASK_tgt_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_tgt_BITS 1 +#define GISB_ARBITER_REQ_MASK_tgt_SHIFT 4 +#define GISB_ARBITER_REQ_MASK_tgt_UNMASK 0 + +/* GISB_ARBITER :: REQ_MASK :: aes [03:03] */ +#define GISB_ARBITER_REQ_MASK_aes_MASK 0x00000008 +#define GISB_ARBITER_REQ_MASK_aes_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_aes_BITS 1 +#define GISB_ARBITER_REQ_MASK_aes_SHIFT 3 +#define GISB_ARBITER_REQ_MASK_aes_UNMASK 0 + +/* GISB_ARBITER :: REQ_MASK :: dci [02:02] */ +#define GISB_ARBITER_REQ_MASK_dci_MASK 0x00000004 +#define GISB_ARBITER_REQ_MASK_dci_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_dci_BITS 1 +#define GISB_ARBITER_REQ_MASK_dci_SHIFT 2 +#define GISB_ARBITER_REQ_MASK_dci_UNMASK 0 + +/* GISB_ARBITER :: REQ_MASK :: cce [01:01] */ +#define GISB_ARBITER_REQ_MASK_cce_MASK 0x00000002 +#define GISB_ARBITER_REQ_MASK_cce_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_cce_BITS 1 +#define GISB_ARBITER_REQ_MASK_cce_SHIFT 1 +#define GISB_ARBITER_REQ_MASK_cce_UNMASK 0 + +/* GISB_ARBITER :: REQ_MASK :: dbu [00:00] */ +#define GISB_ARBITER_REQ_MASK_dbu_MASK 0x00000001 +#define GISB_ARBITER_REQ_MASK_dbu_ALIGN 0 +#define GISB_ARBITER_REQ_MASK_dbu_BITS 1 +#define GISB_ARBITER_REQ_MASK_dbu_SHIFT 0 +#define GISB_ARBITER_REQ_MASK_dbu_UNMASK 0 + + +/**************************************************************************** + * GISB_ARBITER :: TIMER + ***************************************************************************/ +/* GISB_ARBITER :: TIMER :: hi_count [31:16] */ +#define GISB_ARBITER_TIMER_hi_count_MASK 0xffff0000 +#define GISB_ARBITER_TIMER_hi_count_ALIGN 0 +#define GISB_ARBITER_TIMER_hi_count_BITS 16 +#define GISB_ARBITER_TIMER_hi_count_SHIFT 16 + +/* GISB_ARBITER :: TIMER :: lo_count [15:00] */ +#define GISB_ARBITER_TIMER_lo_count_MASK 0x0000ffff +#define GISB_ARBITER_TIMER_lo_count_ALIGN 0 +#define GISB_ARBITER_TIMER_lo_count_BITS 16 +#define GISB_ARBITER_TIMER_lo_count_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_CTRL + ***************************************************************************/ +/* GISB_ARBITER :: BP_CTRL :: reserved0 [31:02] */ +#define GISB_ARBITER_BP_CTRL_reserved0_MASK 0xfffffffc +#define GISB_ARBITER_BP_CTRL_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_CTRL_reserved0_BITS 30 +#define GISB_ARBITER_BP_CTRL_reserved0_SHIFT 2 + +/* GISB_ARBITER :: BP_CTRL :: breakpoint_tea [01:01] */ +#define GISB_ARBITER_BP_CTRL_breakpoint_tea_MASK 0x00000002 +#define GISB_ARBITER_BP_CTRL_breakpoint_tea_ALIGN 0 +#define GISB_ARBITER_BP_CTRL_breakpoint_tea_BITS 1 +#define GISB_ARBITER_BP_CTRL_breakpoint_tea_SHIFT 1 +#define GISB_ARBITER_BP_CTRL_breakpoint_tea_DISABLE 0 +#define GISB_ARBITER_BP_CTRL_breakpoint_tea_ENABLE 1 + +/* GISB_ARBITER :: BP_CTRL :: repeat_capture [00:00] */ +#define GISB_ARBITER_BP_CTRL_repeat_capture_MASK 0x00000001 +#define GISB_ARBITER_BP_CTRL_repeat_capture_ALIGN 0 +#define GISB_ARBITER_BP_CTRL_repeat_capture_BITS 1 +#define GISB_ARBITER_BP_CTRL_repeat_capture_SHIFT 0 +#define GISB_ARBITER_BP_CTRL_repeat_capture_DISABLE 0 +#define GISB_ARBITER_BP_CTRL_repeat_capture_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_CAP_CLR + ***************************************************************************/ +/* GISB_ARBITER :: BP_CAP_CLR :: reserved0 [31:01] */ +#define GISB_ARBITER_BP_CAP_CLR_reserved0_MASK 0xfffffffe +#define GISB_ARBITER_BP_CAP_CLR_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_CAP_CLR_reserved0_BITS 31 +#define GISB_ARBITER_BP_CAP_CLR_reserved0_SHIFT 1 + +/* GISB_ARBITER :: BP_CAP_CLR :: clear [00:00] */ +#define GISB_ARBITER_BP_CAP_CLR_clear_MASK 0x00000001 +#define GISB_ARBITER_BP_CAP_CLR_clear_ALIGN 0 +#define GISB_ARBITER_BP_CAP_CLR_clear_BITS 1 +#define GISB_ARBITER_BP_CAP_CLR_clear_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_0 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_0 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_0_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_0_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_0_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_0_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_0 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_0 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_0_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_0_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_0_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_0_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_0 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_0 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_0_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_0_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_0_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_0 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_0_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_0_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_0_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_0_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_0_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_0 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_0_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_0_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_aes_BITS 1 +#define GISB_ARBITER_BP_READ_0_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_0_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_0_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_0 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_0_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_0_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_fve_BITS 1 +#define GISB_ARBITER_BP_READ_0_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_0_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_0_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_0 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_0_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_0_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_0_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_0_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_0_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_0 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_0_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_0_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_0_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_0_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_0_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_0 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_0_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_0_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_0_cce_BITS 1 +#define GISB_ARBITER_BP_READ_0_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_0_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_0_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_0 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_0 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_0_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_0_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_0_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_0 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_0_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_0_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_0_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_0_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_0_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_0 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_0_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_0_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_0_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_0_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_0_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_0 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_0_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_0_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_0_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_0_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_0_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_0 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_0_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_0_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_0_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_0_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_0_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_0 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_0_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_0_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_0_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_0_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_0_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_0 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_0_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_0_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_0_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_0_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_0_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_0_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_0 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_0 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_0_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_0_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_0_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_0_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_0 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_0_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_0_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_0_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_0_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_0_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_0_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_0 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_0_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_0_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_0_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_0_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_0_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_0_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_0 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_0_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_0_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_0_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_0_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_0_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_0_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_1 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_1 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_1_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_1_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_1_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_1_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_1 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_1 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_1_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_1_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_1_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_1_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_1 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_1 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_1_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_1_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_1_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_1 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_1_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_1_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_1_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_1_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_1_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_1 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_1_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_1_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_aes_BITS 1 +#define GISB_ARBITER_BP_READ_1_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_1_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_1_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_1 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_1_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_1_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_fve_BITS 1 +#define GISB_ARBITER_BP_READ_1_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_1_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_1_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_1 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_1_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_1_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_1_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_1_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_1_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_1 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_1_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_1_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_1_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_1_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_1_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_1 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_1_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_1_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_1_cce_BITS 1 +#define GISB_ARBITER_BP_READ_1_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_1_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_1_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_1 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_1 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_1_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_1_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_1_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_1 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_1_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_1_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_1_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_1_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_1_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_1 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_1_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_1_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_1_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_1_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_1_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_1 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_1_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_1_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_1_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_1_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_1_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_1 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_1_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_1_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_1_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_1_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_1_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_1 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_1_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_1_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_1_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_1_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_1_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_1 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_1_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_1_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_1_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_1_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_1_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_1_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_1 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_1 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_1_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_1_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_1_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_1_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_1 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_1_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_1_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_1_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_1_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_1_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_1_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_1 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_1_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_1_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_1_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_1_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_1_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_1_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_1 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_1_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_1_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_1_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_1_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_1_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_1_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_2 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_2 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_2_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_2_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_2_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_2_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_2 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_2 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_2_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_2_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_2_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_2_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_2 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_2 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_2_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_2_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_2_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_2 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_2_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_2_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_2_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_2_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_2_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_2 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_2_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_2_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_aes_BITS 1 +#define GISB_ARBITER_BP_READ_2_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_2_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_2_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_2 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_2_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_2_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_fve_BITS 1 +#define GISB_ARBITER_BP_READ_2_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_2_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_2_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_2 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_2_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_2_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_2_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_2_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_2_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_2 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_2_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_2_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_2_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_2_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_2_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_2 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_2_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_2_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_2_cce_BITS 1 +#define GISB_ARBITER_BP_READ_2_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_2_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_2_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_2 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_2 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_2_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_2_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_2_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_2 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_2_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_2_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_2_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_2_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_2_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_2 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_2_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_2_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_2_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_2_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_2_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_2 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_2_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_2_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_2_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_2_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_2_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_2 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_2_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_2_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_2_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_2_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_2_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_2 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_2_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_2_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_2_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_2_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_2_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_2 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_2_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_2_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_2_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_2_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_2_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_2_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_2 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_2 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_2_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_2_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_2_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_2_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_2 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_2_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_2_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_2_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_2_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_2_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_2_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_2 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_2_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_2_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_2_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_2_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_2_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_2_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_2 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_2_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_2_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_2_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_2_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_2_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_2_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_3 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_3 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_3_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_3_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_3_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_3_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_3 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_3 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_3_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_3_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_3_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_3_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_3 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_3 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_3_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_3_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_3_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_3 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_3_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_3_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_3_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_3_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_3_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_3 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_3_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_3_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_aes_BITS 1 +#define GISB_ARBITER_BP_READ_3_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_3_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_3_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_3 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_3_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_3_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_fve_BITS 1 +#define GISB_ARBITER_BP_READ_3_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_3_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_3_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_3 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_3_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_3_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_3_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_3_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_3_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_3 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_3_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_3_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_3_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_3_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_3_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_3 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_3_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_3_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_3_cce_BITS 1 +#define GISB_ARBITER_BP_READ_3_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_3_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_3_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_3 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_3 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_3_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_3_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_3_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_3 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_3_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_3_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_3_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_3_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_3_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_3 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_3_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_3_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_3_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_3_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_3_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_3 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_3_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_3_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_3_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_3_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_3_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_3 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_3_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_3_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_3_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_3_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_3_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_3 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_3_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_3_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_3_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_3_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_3_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_3 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_3_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_3_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_3_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_3_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_3_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_3_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_3 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_3 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_3_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_3_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_3_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_3_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_3 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_3_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_3_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_3_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_3_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_3_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_3_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_3 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_3_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_3_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_3_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_3_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_3_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_3_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_3 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_3_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_3_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_3_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_3_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_3_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_3_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_4 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_4 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_4_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_4_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_4_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_4_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_4 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_4 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_4_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_4_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_4_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_4_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_4 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_4 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_4_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_4_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_4_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_4 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_4_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_4_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_4_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_4_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_4_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_4 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_4_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_4_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_aes_BITS 1 +#define GISB_ARBITER_BP_READ_4_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_4_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_4_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_4 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_4_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_4_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_fve_BITS 1 +#define GISB_ARBITER_BP_READ_4_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_4_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_4_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_4 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_4_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_4_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_4_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_4_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_4_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_4 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_4_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_4_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_4_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_4_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_4_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_4 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_4_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_4_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_4_cce_BITS 1 +#define GISB_ARBITER_BP_READ_4_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_4_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_4_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_4 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_4 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_4_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_4_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_4_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_4 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_4_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_4_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_4_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_4_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_4_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_4 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_4_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_4_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_4_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_4_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_4_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_4 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_4_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_4_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_4_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_4_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_4_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_4 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_4_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_4_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_4_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_4_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_4_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_4 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_4_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_4_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_4_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_4_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_4_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_4 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_4_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_4_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_4_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_4_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_4_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_4_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_4 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_4 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_4_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_4_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_4_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_4_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_4 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_4_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_4_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_4_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_4_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_4_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_4_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_4 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_4_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_4_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_4_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_4_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_4_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_4_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_4 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_4_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_4_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_4_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_4_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_4_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_4_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_5 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_5 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_5_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_5_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_5_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_5_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_5 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_5 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_5_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_5_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_5_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_5_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_5 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_5 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_5_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_5_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_5_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_5 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_5_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_5_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_5_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_5_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_5_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_5 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_5_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_5_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_aes_BITS 1 +#define GISB_ARBITER_BP_READ_5_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_5_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_5_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_5 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_5_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_5_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_fve_BITS 1 +#define GISB_ARBITER_BP_READ_5_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_5_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_5_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_5 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_5_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_5_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_5_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_5_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_5_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_5 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_5_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_5_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_5_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_5_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_5_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_5 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_5_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_5_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_5_cce_BITS 1 +#define GISB_ARBITER_BP_READ_5_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_5_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_5_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_5 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_5 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_5_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_5_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_5_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_5 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_5_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_5_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_5_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_5_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_5_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_5 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_5_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_5_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_5_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_5_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_5_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_5 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_5_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_5_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_5_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_5_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_5_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_5 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_5_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_5_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_5_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_5_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_5_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_5 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_5_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_5_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_5_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_5_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_5_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_5 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_5_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_5_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_5_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_5_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_5_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_5_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_5 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_5 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_5_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_5_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_5_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_5_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_5 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_5_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_5_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_5_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_5_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_5_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_5_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_5 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_5_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_5_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_5_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_5_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_5_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_5_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_5 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_5_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_5_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_5_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_5_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_5_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_5_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_6 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_6 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_6_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_6_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_6_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_6_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_6 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_6 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_6_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_6_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_6_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_6_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_6 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_6 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_6_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_6_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_6_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_6 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_6_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_6_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_6_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_6_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_6_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_6 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_6_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_6_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_aes_BITS 1 +#define GISB_ARBITER_BP_READ_6_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_6_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_6_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_6 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_6_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_6_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_fve_BITS 1 +#define GISB_ARBITER_BP_READ_6_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_6_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_6_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_6 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_6_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_6_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_6_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_6_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_6_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_6 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_6_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_6_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_6_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_6_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_6_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_6 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_6_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_6_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_6_cce_BITS 1 +#define GISB_ARBITER_BP_READ_6_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_6_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_6_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_6 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_6 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_6_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_6_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_6_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_6 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_6_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_6_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_6_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_6_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_6_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_6 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_6_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_6_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_6_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_6_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_6_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_6 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_6_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_6_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_6_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_6_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_6_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_6 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_6_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_6_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_6_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_6_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_6_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_6 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_6_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_6_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_6_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_6_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_6_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_6 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_6_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_6_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_6_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_6_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_6_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_6_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_6 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_6 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_6_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_6_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_6_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_6_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_6 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_6_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_6_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_6_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_6_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_6_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_6_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_6 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_6_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_6_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_6_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_6_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_6_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_6_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_6 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_6_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_6_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_6_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_6_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_6_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_6_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_START_ADDR_7 + ***************************************************************************/ +/* GISB_ARBITER :: BP_START_ADDR_7 :: start [31:00] */ +#define GISB_ARBITER_BP_START_ADDR_7_start_MASK 0xffffffff +#define GISB_ARBITER_BP_START_ADDR_7_start_ALIGN 0 +#define GISB_ARBITER_BP_START_ADDR_7_start_BITS 32 +#define GISB_ARBITER_BP_START_ADDR_7_start_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_END_ADDR_7 + ***************************************************************************/ +/* GISB_ARBITER :: BP_END_ADDR_7 :: end [31:00] */ +#define GISB_ARBITER_BP_END_ADDR_7_end_MASK 0xffffffff +#define GISB_ARBITER_BP_END_ADDR_7_end_ALIGN 0 +#define GISB_ARBITER_BP_END_ADDR_7_end_BITS 32 +#define GISB_ARBITER_BP_END_ADDR_7_end_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_READ_7 + ***************************************************************************/ +/* GISB_ARBITER :: BP_READ_7 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_READ_7_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_READ_7_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_reserved0_BITS 26 +#define GISB_ARBITER_BP_READ_7_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_READ_7 :: bsp [05:05] */ +#define GISB_ARBITER_BP_READ_7_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_READ_7_bsp_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_bsp_BITS 1 +#define GISB_ARBITER_BP_READ_7_bsp_SHIFT 5 +#define GISB_ARBITER_BP_READ_7_bsp_DISABLE 0 +#define GISB_ARBITER_BP_READ_7_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_7 :: aes [04:04] */ +#define GISB_ARBITER_BP_READ_7_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_READ_7_aes_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_aes_BITS 1 +#define GISB_ARBITER_BP_READ_7_aes_SHIFT 4 +#define GISB_ARBITER_BP_READ_7_aes_DISABLE 0 +#define GISB_ARBITER_BP_READ_7_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_7 :: fve [03:03] */ +#define GISB_ARBITER_BP_READ_7_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_READ_7_fve_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_fve_BITS 1 +#define GISB_ARBITER_BP_READ_7_fve_SHIFT 3 +#define GISB_ARBITER_BP_READ_7_fve_DISABLE 0 +#define GISB_ARBITER_BP_READ_7_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_7 :: tgt [02:02] */ +#define GISB_ARBITER_BP_READ_7_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_READ_7_tgt_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_tgt_BITS 1 +#define GISB_ARBITER_BP_READ_7_tgt_SHIFT 2 +#define GISB_ARBITER_BP_READ_7_tgt_DISABLE 0 +#define GISB_ARBITER_BP_READ_7_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_7 :: dbu [01:01] */ +#define GISB_ARBITER_BP_READ_7_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_READ_7_dbu_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_dbu_BITS 1 +#define GISB_ARBITER_BP_READ_7_dbu_SHIFT 1 +#define GISB_ARBITER_BP_READ_7_dbu_DISABLE 0 +#define GISB_ARBITER_BP_READ_7_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_READ_7 :: cce [00:00] */ +#define GISB_ARBITER_BP_READ_7_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_READ_7_cce_ALIGN 0 +#define GISB_ARBITER_BP_READ_7_cce_BITS 1 +#define GISB_ARBITER_BP_READ_7_cce_SHIFT 0 +#define GISB_ARBITER_BP_READ_7_cce_DISABLE 0 +#define GISB_ARBITER_BP_READ_7_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_WRITE_7 + ***************************************************************************/ +/* GISB_ARBITER :: BP_WRITE_7 :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_WRITE_7_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_WRITE_7_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_reserved0_BITS 26 +#define GISB_ARBITER_BP_WRITE_7_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_WRITE_7 :: bsp [05:05] */ +#define GISB_ARBITER_BP_WRITE_7_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_WRITE_7_bsp_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_bsp_BITS 1 +#define GISB_ARBITER_BP_WRITE_7_bsp_SHIFT 5 +#define GISB_ARBITER_BP_WRITE_7_bsp_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_7_bsp_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_7 :: aes [04:04] */ +#define GISB_ARBITER_BP_WRITE_7_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_WRITE_7_aes_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_aes_BITS 1 +#define GISB_ARBITER_BP_WRITE_7_aes_SHIFT 4 +#define GISB_ARBITER_BP_WRITE_7_aes_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_7_aes_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_7 :: fve [03:03] */ +#define GISB_ARBITER_BP_WRITE_7_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_WRITE_7_fve_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_fve_BITS 1 +#define GISB_ARBITER_BP_WRITE_7_fve_SHIFT 3 +#define GISB_ARBITER_BP_WRITE_7_fve_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_7_fve_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_7 :: tgt [02:02] */ +#define GISB_ARBITER_BP_WRITE_7_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_WRITE_7_tgt_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_tgt_BITS 1 +#define GISB_ARBITER_BP_WRITE_7_tgt_SHIFT 2 +#define GISB_ARBITER_BP_WRITE_7_tgt_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_7_tgt_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_7 :: dbu [01:01] */ +#define GISB_ARBITER_BP_WRITE_7_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_WRITE_7_dbu_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_dbu_BITS 1 +#define GISB_ARBITER_BP_WRITE_7_dbu_SHIFT 1 +#define GISB_ARBITER_BP_WRITE_7_dbu_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_7_dbu_ENABLE 1 + +/* GISB_ARBITER :: BP_WRITE_7 :: cce [00:00] */ +#define GISB_ARBITER_BP_WRITE_7_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_WRITE_7_cce_ALIGN 0 +#define GISB_ARBITER_BP_WRITE_7_cce_BITS 1 +#define GISB_ARBITER_BP_WRITE_7_cce_SHIFT 0 +#define GISB_ARBITER_BP_WRITE_7_cce_DISABLE 0 +#define GISB_ARBITER_BP_WRITE_7_cce_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_ENABLE_7 + ***************************************************************************/ +/* GISB_ARBITER :: BP_ENABLE_7 :: reserved0 [31:03] */ +#define GISB_ARBITER_BP_ENABLE_7_reserved0_MASK 0xfffffff8 +#define GISB_ARBITER_BP_ENABLE_7_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_7_reserved0_BITS 29 +#define GISB_ARBITER_BP_ENABLE_7_reserved0_SHIFT 3 + +/* GISB_ARBITER :: BP_ENABLE_7 :: block [02:02] */ +#define GISB_ARBITER_BP_ENABLE_7_block_MASK 0x00000004 +#define GISB_ARBITER_BP_ENABLE_7_block_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_7_block_BITS 1 +#define GISB_ARBITER_BP_ENABLE_7_block_SHIFT 2 +#define GISB_ARBITER_BP_ENABLE_7_block_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_7_block_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_7 :: address [01:01] */ +#define GISB_ARBITER_BP_ENABLE_7_address_MASK 0x00000002 +#define GISB_ARBITER_BP_ENABLE_7_address_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_7_address_BITS 1 +#define GISB_ARBITER_BP_ENABLE_7_address_SHIFT 1 +#define GISB_ARBITER_BP_ENABLE_7_address_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_7_address_ENABLE 1 + +/* GISB_ARBITER :: BP_ENABLE_7 :: access [00:00] */ +#define GISB_ARBITER_BP_ENABLE_7_access_MASK 0x00000001 +#define GISB_ARBITER_BP_ENABLE_7_access_ALIGN 0 +#define GISB_ARBITER_BP_ENABLE_7_access_BITS 1 +#define GISB_ARBITER_BP_ENABLE_7_access_SHIFT 0 +#define GISB_ARBITER_BP_ENABLE_7_access_DISABLE 0 +#define GISB_ARBITER_BP_ENABLE_7_access_ENABLE 1 + + +/**************************************************************************** + * GISB_ARBITER :: BP_CAP_ADDR + ***************************************************************************/ +/* GISB_ARBITER :: BP_CAP_ADDR :: address [31:00] */ +#define GISB_ARBITER_BP_CAP_ADDR_address_MASK 0xffffffff +#define GISB_ARBITER_BP_CAP_ADDR_address_ALIGN 0 +#define GISB_ARBITER_BP_CAP_ADDR_address_BITS 32 +#define GISB_ARBITER_BP_CAP_ADDR_address_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_CAP_DATA + ***************************************************************************/ +/* GISB_ARBITER :: BP_CAP_DATA :: data [31:00] */ +#define GISB_ARBITER_BP_CAP_DATA_data_MASK 0xffffffff +#define GISB_ARBITER_BP_CAP_DATA_data_ALIGN 0 +#define GISB_ARBITER_BP_CAP_DATA_data_BITS 32 +#define GISB_ARBITER_BP_CAP_DATA_data_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_CAP_STATUS + ***************************************************************************/ +/* GISB_ARBITER :: BP_CAP_STATUS :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_CAP_STATUS_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_CAP_STATUS_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_CAP_STATUS_reserved0_BITS 26 +#define GISB_ARBITER_BP_CAP_STATUS_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_CAP_STATUS :: bs_b [05:02] */ +#define GISB_ARBITER_BP_CAP_STATUS_bs_b_MASK 0x0000003c +#define GISB_ARBITER_BP_CAP_STATUS_bs_b_ALIGN 0 +#define GISB_ARBITER_BP_CAP_STATUS_bs_b_BITS 4 +#define GISB_ARBITER_BP_CAP_STATUS_bs_b_SHIFT 2 + +/* GISB_ARBITER :: BP_CAP_STATUS :: write [01:01] */ +#define GISB_ARBITER_BP_CAP_STATUS_write_MASK 0x00000002 +#define GISB_ARBITER_BP_CAP_STATUS_write_ALIGN 0 +#define GISB_ARBITER_BP_CAP_STATUS_write_BITS 1 +#define GISB_ARBITER_BP_CAP_STATUS_write_SHIFT 1 + +/* GISB_ARBITER :: BP_CAP_STATUS :: valid [00:00] */ +#define GISB_ARBITER_BP_CAP_STATUS_valid_MASK 0x00000001 +#define GISB_ARBITER_BP_CAP_STATUS_valid_ALIGN 0 +#define GISB_ARBITER_BP_CAP_STATUS_valid_BITS 1 +#define GISB_ARBITER_BP_CAP_STATUS_valid_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: BP_CAP_MASTER + ***************************************************************************/ +/* GISB_ARBITER :: BP_CAP_MASTER :: reserved0 [31:06] */ +#define GISB_ARBITER_BP_CAP_MASTER_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_BP_CAP_MASTER_reserved0_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_reserved0_BITS 26 +#define GISB_ARBITER_BP_CAP_MASTER_reserved0_SHIFT 6 + +/* GISB_ARBITER :: BP_CAP_MASTER :: bsp [05:05] */ +#define GISB_ARBITER_BP_CAP_MASTER_bsp_MASK 0x00000020 +#define GISB_ARBITER_BP_CAP_MASTER_bsp_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_bsp_BITS 1 +#define GISB_ARBITER_BP_CAP_MASTER_bsp_SHIFT 5 + +/* GISB_ARBITER :: BP_CAP_MASTER :: aes [04:04] */ +#define GISB_ARBITER_BP_CAP_MASTER_aes_MASK 0x00000010 +#define GISB_ARBITER_BP_CAP_MASTER_aes_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_aes_BITS 1 +#define GISB_ARBITER_BP_CAP_MASTER_aes_SHIFT 4 + +/* GISB_ARBITER :: BP_CAP_MASTER :: fve [03:03] */ +#define GISB_ARBITER_BP_CAP_MASTER_fve_MASK 0x00000008 +#define GISB_ARBITER_BP_CAP_MASTER_fve_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_fve_BITS 1 +#define GISB_ARBITER_BP_CAP_MASTER_fve_SHIFT 3 + +/* GISB_ARBITER :: BP_CAP_MASTER :: tgt [02:02] */ +#define GISB_ARBITER_BP_CAP_MASTER_tgt_MASK 0x00000004 +#define GISB_ARBITER_BP_CAP_MASTER_tgt_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_tgt_BITS 1 +#define GISB_ARBITER_BP_CAP_MASTER_tgt_SHIFT 2 + +/* GISB_ARBITER :: BP_CAP_MASTER :: dbu [01:01] */ +#define GISB_ARBITER_BP_CAP_MASTER_dbu_MASK 0x00000002 +#define GISB_ARBITER_BP_CAP_MASTER_dbu_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_dbu_BITS 1 +#define GISB_ARBITER_BP_CAP_MASTER_dbu_SHIFT 1 + +/* GISB_ARBITER :: BP_CAP_MASTER :: cce [00:00] */ +#define GISB_ARBITER_BP_CAP_MASTER_cce_MASK 0x00000001 +#define GISB_ARBITER_BP_CAP_MASTER_cce_ALIGN 0 +#define GISB_ARBITER_BP_CAP_MASTER_cce_BITS 1 +#define GISB_ARBITER_BP_CAP_MASTER_cce_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: ERR_CAP_CLR + ***************************************************************************/ +/* GISB_ARBITER :: ERR_CAP_CLR :: reserved0 [31:01] */ +#define GISB_ARBITER_ERR_CAP_CLR_reserved0_MASK 0xfffffffe +#define GISB_ARBITER_ERR_CAP_CLR_reserved0_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_CLR_reserved0_BITS 31 +#define GISB_ARBITER_ERR_CAP_CLR_reserved0_SHIFT 1 + +/* GISB_ARBITER :: ERR_CAP_CLR :: clear [00:00] */ +#define GISB_ARBITER_ERR_CAP_CLR_clear_MASK 0x00000001 +#define GISB_ARBITER_ERR_CAP_CLR_clear_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_CLR_clear_BITS 1 +#define GISB_ARBITER_ERR_CAP_CLR_clear_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: ERR_CAP_ADDR + ***************************************************************************/ +/* GISB_ARBITER :: ERR_CAP_ADDR :: address [31:00] */ +#define GISB_ARBITER_ERR_CAP_ADDR_address_MASK 0xffffffff +#define GISB_ARBITER_ERR_CAP_ADDR_address_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_ADDR_address_BITS 32 +#define GISB_ARBITER_ERR_CAP_ADDR_address_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: ERR_CAP_DATA + ***************************************************************************/ +/* GISB_ARBITER :: ERR_CAP_DATA :: data [31:00] */ +#define GISB_ARBITER_ERR_CAP_DATA_data_MASK 0xffffffff +#define GISB_ARBITER_ERR_CAP_DATA_data_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_DATA_data_BITS 32 +#define GISB_ARBITER_ERR_CAP_DATA_data_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: ERR_CAP_STATUS + ***************************************************************************/ +/* GISB_ARBITER :: ERR_CAP_STATUS :: reserved0 [31:13] */ +#define GISB_ARBITER_ERR_CAP_STATUS_reserved0_MASK 0xffffe000 +#define GISB_ARBITER_ERR_CAP_STATUS_reserved0_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_reserved0_BITS 19 +#define GISB_ARBITER_ERR_CAP_STATUS_reserved0_SHIFT 13 + +/* GISB_ARBITER :: ERR_CAP_STATUS :: timeout [12:12] */ +#define GISB_ARBITER_ERR_CAP_STATUS_timeout_MASK 0x00001000 +#define GISB_ARBITER_ERR_CAP_STATUS_timeout_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_timeout_BITS 1 +#define GISB_ARBITER_ERR_CAP_STATUS_timeout_SHIFT 12 + +/* GISB_ARBITER :: ERR_CAP_STATUS :: tea [11:11] */ +#define GISB_ARBITER_ERR_CAP_STATUS_tea_MASK 0x00000800 +#define GISB_ARBITER_ERR_CAP_STATUS_tea_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_tea_BITS 1 +#define GISB_ARBITER_ERR_CAP_STATUS_tea_SHIFT 11 + +/* GISB_ARBITER :: ERR_CAP_STATUS :: reserved1 [10:06] */ +#define GISB_ARBITER_ERR_CAP_STATUS_reserved1_MASK 0x000007c0 +#define GISB_ARBITER_ERR_CAP_STATUS_reserved1_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_reserved1_BITS 5 +#define GISB_ARBITER_ERR_CAP_STATUS_reserved1_SHIFT 6 + +/* GISB_ARBITER :: ERR_CAP_STATUS :: bs_b [05:02] */ +#define GISB_ARBITER_ERR_CAP_STATUS_bs_b_MASK 0x0000003c +#define GISB_ARBITER_ERR_CAP_STATUS_bs_b_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_bs_b_BITS 4 +#define GISB_ARBITER_ERR_CAP_STATUS_bs_b_SHIFT 2 + +/* GISB_ARBITER :: ERR_CAP_STATUS :: write [01:01] */ +#define GISB_ARBITER_ERR_CAP_STATUS_write_MASK 0x00000002 +#define GISB_ARBITER_ERR_CAP_STATUS_write_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_write_BITS 1 +#define GISB_ARBITER_ERR_CAP_STATUS_write_SHIFT 1 + +/* GISB_ARBITER :: ERR_CAP_STATUS :: valid [00:00] */ +#define GISB_ARBITER_ERR_CAP_STATUS_valid_MASK 0x00000001 +#define GISB_ARBITER_ERR_CAP_STATUS_valid_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_STATUS_valid_BITS 1 +#define GISB_ARBITER_ERR_CAP_STATUS_valid_SHIFT 0 + + +/**************************************************************************** + * GISB_ARBITER :: ERR_CAP_MASTER + ***************************************************************************/ +/* GISB_ARBITER :: ERR_CAP_MASTER :: reserved0 [31:06] */ +#define GISB_ARBITER_ERR_CAP_MASTER_reserved0_MASK 0xffffffc0 +#define GISB_ARBITER_ERR_CAP_MASTER_reserved0_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_reserved0_BITS 26 +#define GISB_ARBITER_ERR_CAP_MASTER_reserved0_SHIFT 6 + +/* GISB_ARBITER :: ERR_CAP_MASTER :: bsp [05:05] */ +#define GISB_ARBITER_ERR_CAP_MASTER_bsp_MASK 0x00000020 +#define GISB_ARBITER_ERR_CAP_MASTER_bsp_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_bsp_BITS 1 +#define GISB_ARBITER_ERR_CAP_MASTER_bsp_SHIFT 5 + +/* GISB_ARBITER :: ERR_CAP_MASTER :: aes [04:04] */ +#define GISB_ARBITER_ERR_CAP_MASTER_aes_MASK 0x00000010 +#define GISB_ARBITER_ERR_CAP_MASTER_aes_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_aes_BITS 1 +#define GISB_ARBITER_ERR_CAP_MASTER_aes_SHIFT 4 + +/* GISB_ARBITER :: ERR_CAP_MASTER :: fve [03:03] */ +#define GISB_ARBITER_ERR_CAP_MASTER_fve_MASK 0x00000008 +#define GISB_ARBITER_ERR_CAP_MASTER_fve_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_fve_BITS 1 +#define GISB_ARBITER_ERR_CAP_MASTER_fve_SHIFT 3 + +/* GISB_ARBITER :: ERR_CAP_MASTER :: tgt [02:02] */ +#define GISB_ARBITER_ERR_CAP_MASTER_tgt_MASK 0x00000004 +#define GISB_ARBITER_ERR_CAP_MASTER_tgt_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_tgt_BITS 1 +#define GISB_ARBITER_ERR_CAP_MASTER_tgt_SHIFT 2 + +/* GISB_ARBITER :: ERR_CAP_MASTER :: dbu [01:01] */ +#define GISB_ARBITER_ERR_CAP_MASTER_dbu_MASK 0x00000002 +#define GISB_ARBITER_ERR_CAP_MASTER_dbu_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_dbu_BITS 1 +#define GISB_ARBITER_ERR_CAP_MASTER_dbu_SHIFT 1 + +/* GISB_ARBITER :: ERR_CAP_MASTER :: cce [00:00] */ +#define GISB_ARBITER_ERR_CAP_MASTER_cce_MASK 0x00000001 +#define GISB_ARBITER_ERR_CAP_MASTER_cce_ALIGN 0 +#define GISB_ARBITER_ERR_CAP_MASTER_cce_BITS 1 +#define GISB_ARBITER_ERR_CAP_MASTER_cce_SHIFT 0 + + +/**************************************************************************** + * BCM70012_MISC_TOP_MISC_GR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * MISC_GR_BRIDGE :: REVISION + ***************************************************************************/ +/* MISC_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define MISC_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define MISC_GR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define MISC_GR_BRIDGE_REVISION_reserved0_BITS 16 +#define MISC_GR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* MISC_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define MISC_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define MISC_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define MISC_GR_BRIDGE_REVISION_MAJOR_BITS 8 +#define MISC_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* MISC_GR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define MISC_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define MISC_GR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define MISC_GR_BRIDGE_REVISION_MINOR_BITS 8 +#define MISC_GR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * MISC_GR_BRIDGE :: CTRL + ***************************************************************************/ +/* MISC_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ +#define MISC_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe +#define MISC_GR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define MISC_GR_BRIDGE_CTRL_reserved0_BITS 31 +#define MISC_GR_BRIDGE_CTRL_reserved0_SHIFT 1 + +/* MISC_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + + +/**************************************************************************** + * MISC_GR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * MISC_GR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 +#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * BCM70012_DBU_TOP_DBU + ***************************************************************************/ +/**************************************************************************** + * DBU :: DBU_CMD + ***************************************************************************/ +/* DBU :: DBU_CMD :: reserved0 [31:03] */ +#define DBU_DBU_CMD_reserved0_MASK 0xfffffff8 +#define DBU_DBU_CMD_reserved0_ALIGN 0 +#define DBU_DBU_CMD_reserved0_BITS 29 +#define DBU_DBU_CMD_reserved0_SHIFT 3 + +/* DBU :: DBU_CMD :: RX_OVERFLOW [02:02] */ +#define DBU_DBU_CMD_RX_OVERFLOW_MASK 0x00000004 +#define DBU_DBU_CMD_RX_OVERFLOW_ALIGN 0 +#define DBU_DBU_CMD_RX_OVERFLOW_BITS 1 +#define DBU_DBU_CMD_RX_OVERFLOW_SHIFT 2 + +/* DBU :: DBU_CMD :: RX_ERROR [01:01] */ +#define DBU_DBU_CMD_RX_ERROR_MASK 0x00000002 +#define DBU_DBU_CMD_RX_ERROR_ALIGN 0 +#define DBU_DBU_CMD_RX_ERROR_BITS 1 +#define DBU_DBU_CMD_RX_ERROR_SHIFT 1 + +/* DBU :: DBU_CMD :: ENABLE [00:00] */ +#define DBU_DBU_CMD_ENABLE_MASK 0x00000001 +#define DBU_DBU_CMD_ENABLE_ALIGN 0 +#define DBU_DBU_CMD_ENABLE_BITS 1 +#define DBU_DBU_CMD_ENABLE_SHIFT 0 + + +/**************************************************************************** + * DBU :: DBU_STATUS + ***************************************************************************/ +/* DBU :: DBU_STATUS :: reserved0 [31:02] */ +#define DBU_DBU_STATUS_reserved0_MASK 0xfffffffc +#define DBU_DBU_STATUS_reserved0_ALIGN 0 +#define DBU_DBU_STATUS_reserved0_BITS 30 +#define DBU_DBU_STATUS_reserved0_SHIFT 2 + +/* DBU :: DBU_STATUS :: TXDATA_OCCUPIED [01:01] */ +#define DBU_DBU_STATUS_TXDATA_OCCUPIED_MASK 0x00000002 +#define DBU_DBU_STATUS_TXDATA_OCCUPIED_ALIGN 0 +#define DBU_DBU_STATUS_TXDATA_OCCUPIED_BITS 1 +#define DBU_DBU_STATUS_TXDATA_OCCUPIED_SHIFT 1 + +/* DBU :: DBU_STATUS :: RXDATA_VALID [00:00] */ +#define DBU_DBU_STATUS_RXDATA_VALID_MASK 0x00000001 +#define DBU_DBU_STATUS_RXDATA_VALID_ALIGN 0 +#define DBU_DBU_STATUS_RXDATA_VALID_BITS 1 +#define DBU_DBU_STATUS_RXDATA_VALID_SHIFT 0 + + +/**************************************************************************** + * DBU :: DBU_CONFIG + ***************************************************************************/ +/* DBU :: DBU_CONFIG :: reserved0 [31:03] */ +#define DBU_DBU_CONFIG_reserved0_MASK 0xfffffff8 +#define DBU_DBU_CONFIG_reserved0_ALIGN 0 +#define DBU_DBU_CONFIG_reserved0_BITS 29 +#define DBU_DBU_CONFIG_reserved0_SHIFT 3 + +/* DBU :: DBU_CONFIG :: CRLF_ENABLE [02:02] */ +#define DBU_DBU_CONFIG_CRLF_ENABLE_MASK 0x00000004 +#define DBU_DBU_CONFIG_CRLF_ENABLE_ALIGN 0 +#define DBU_DBU_CONFIG_CRLF_ENABLE_BITS 1 +#define DBU_DBU_CONFIG_CRLF_ENABLE_SHIFT 2 + +/* DBU :: DBU_CONFIG :: DEBUGSM_ENABLE [01:01] */ +#define DBU_DBU_CONFIG_DEBUGSM_ENABLE_MASK 0x00000002 +#define DBU_DBU_CONFIG_DEBUGSM_ENABLE_ALIGN 0 +#define DBU_DBU_CONFIG_DEBUGSM_ENABLE_BITS 1 +#define DBU_DBU_CONFIG_DEBUGSM_ENABLE_SHIFT 1 + +/* DBU :: DBU_CONFIG :: TIMING_OVERRIDE [00:00] */ +#define DBU_DBU_CONFIG_TIMING_OVERRIDE_MASK 0x00000001 +#define DBU_DBU_CONFIG_TIMING_OVERRIDE_ALIGN 0 +#define DBU_DBU_CONFIG_TIMING_OVERRIDE_BITS 1 +#define DBU_DBU_CONFIG_TIMING_OVERRIDE_SHIFT 0 + + +/**************************************************************************** + * DBU :: DBU_TIMING + ***************************************************************************/ +/* DBU :: DBU_TIMING :: BIT_INTERVAL [31:16] */ +#define DBU_DBU_TIMING_BIT_INTERVAL_MASK 0xffff0000 +#define DBU_DBU_TIMING_BIT_INTERVAL_ALIGN 0 +#define DBU_DBU_TIMING_BIT_INTERVAL_BITS 16 +#define DBU_DBU_TIMING_BIT_INTERVAL_SHIFT 16 + +/* DBU :: DBU_TIMING :: FB_SMPL_OFFSET [15:00] */ +#define DBU_DBU_TIMING_FB_SMPL_OFFSET_MASK 0x0000ffff +#define DBU_DBU_TIMING_FB_SMPL_OFFSET_ALIGN 0 +#define DBU_DBU_TIMING_FB_SMPL_OFFSET_BITS 16 +#define DBU_DBU_TIMING_FB_SMPL_OFFSET_SHIFT 0 + + +/**************************************************************************** + * DBU :: DBU_RXDATA + ***************************************************************************/ +/* DBU :: DBU_RXDATA :: reserved0 [31:09] */ +#define DBU_DBU_RXDATA_reserved0_MASK 0xfffffe00 +#define DBU_DBU_RXDATA_reserved0_ALIGN 0 +#define DBU_DBU_RXDATA_reserved0_BITS 23 +#define DBU_DBU_RXDATA_reserved0_SHIFT 9 + +/* DBU :: DBU_RXDATA :: ERROR [08:08] */ +#define DBU_DBU_RXDATA_ERROR_MASK 0x00000100 +#define DBU_DBU_RXDATA_ERROR_ALIGN 0 +#define DBU_DBU_RXDATA_ERROR_BITS 1 +#define DBU_DBU_RXDATA_ERROR_SHIFT 8 + +/* DBU :: DBU_RXDATA :: VALUE [07:00] */ +#define DBU_DBU_RXDATA_VALUE_MASK 0x000000ff +#define DBU_DBU_RXDATA_VALUE_ALIGN 0 +#define DBU_DBU_RXDATA_VALUE_BITS 8 +#define DBU_DBU_RXDATA_VALUE_SHIFT 0 + + +/**************************************************************************** + * DBU :: DBU_TXDATA + ***************************************************************************/ +/* DBU :: DBU_TXDATA :: reserved0 [31:08] */ +#define DBU_DBU_TXDATA_reserved0_MASK 0xffffff00 +#define DBU_DBU_TXDATA_reserved0_ALIGN 0 +#define DBU_DBU_TXDATA_reserved0_BITS 24 +#define DBU_DBU_TXDATA_reserved0_SHIFT 8 + +/* DBU :: DBU_TXDATA :: VALUE [07:00] */ +#define DBU_DBU_TXDATA_VALUE_MASK 0x000000ff +#define DBU_DBU_TXDATA_VALUE_ALIGN 0 +#define DBU_DBU_TXDATA_VALUE_BITS 8 +#define DBU_DBU_TXDATA_VALUE_SHIFT 0 + + +/**************************************************************************** + * BCM70012_DBU_TOP_DBU_RGR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * DBU_RGR_BRIDGE :: REVISION + ***************************************************************************/ +/* DBU_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define DBU_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define DBU_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define DBU_RGR_BRIDGE_REVISION_reserved0_BITS 16 +#define DBU_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* DBU_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define DBU_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define DBU_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define DBU_RGR_BRIDGE_REVISION_MAJOR_BITS 8 +#define DBU_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* DBU_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define DBU_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define DBU_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define DBU_RGR_BRIDGE_REVISION_MINOR_BITS 8 +#define DBU_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * DBU_RGR_BRIDGE :: CTRL + ***************************************************************************/ +/* DBU_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ +#define DBU_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc +#define DBU_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define DBU_RGR_BRIDGE_CTRL_reserved0_BITS 30 +#define DBU_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 + +/* DBU_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ +#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 +#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 +#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 +#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 +#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 +#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 + +/* DBU_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + + +/**************************************************************************** + * DBU_RGR_BRIDGE :: RBUS_TIMER + ***************************************************************************/ +/* DBU_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ +#define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 +#define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 +#define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 +#define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 + +/* DBU_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ +#define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff +#define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 +#define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 +#define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 + + +/**************************************************************************** + * DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 +#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * BCM70012_OTP_TOP_OTP + ***************************************************************************/ +/**************************************************************************** + * OTP :: CONFIG_INFO + ***************************************************************************/ +/* OTP :: CONFIG_INFO :: reserved0 [31:22] */ +#define OTP_CONFIG_INFO_reserved0_MASK 0xffc00000 +#define OTP_CONFIG_INFO_reserved0_ALIGN 0 +#define OTP_CONFIG_INFO_reserved0_BITS 10 +#define OTP_CONFIG_INFO_reserved0_SHIFT 22 + +/* OTP :: CONFIG_INFO :: SELVL [21:20] */ +#define OTP_CONFIG_INFO_SELVL_MASK 0x00300000 +#define OTP_CONFIG_INFO_SELVL_ALIGN 0 +#define OTP_CONFIG_INFO_SELVL_BITS 2 +#define OTP_CONFIG_INFO_SELVL_SHIFT 20 + +/* OTP :: CONFIG_INFO :: reserved1 [19:17] */ +#define OTP_CONFIG_INFO_reserved1_MASK 0x000e0000 +#define OTP_CONFIG_INFO_reserved1_ALIGN 0 +#define OTP_CONFIG_INFO_reserved1_BITS 3 +#define OTP_CONFIG_INFO_reserved1_SHIFT 17 + +/* OTP :: CONFIG_INFO :: PTEST [16:16] */ +#define OTP_CONFIG_INFO_PTEST_MASK 0x00010000 +#define OTP_CONFIG_INFO_PTEST_ALIGN 0 +#define OTP_CONFIG_INFO_PTEST_BITS 1 +#define OTP_CONFIG_INFO_PTEST_SHIFT 16 + +/* OTP :: CONFIG_INFO :: reserved2 [15:13] */ +#define OTP_CONFIG_INFO_reserved2_MASK 0x0000e000 +#define OTP_CONFIG_INFO_reserved2_ALIGN 0 +#define OTP_CONFIG_INFO_reserved2_BITS 3 +#define OTP_CONFIG_INFO_reserved2_SHIFT 13 + +/* OTP :: CONFIG_INFO :: MAX_REDUNDANT_ROWS [12:08] */ +#define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_MASK 0x00001f00 +#define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_ALIGN 0 +#define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_BITS 5 +#define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_SHIFT 8 + +/* OTP :: CONFIG_INFO :: MAX_RETRY [07:04] */ +#define OTP_CONFIG_INFO_MAX_RETRY_MASK 0x000000f0 +#define OTP_CONFIG_INFO_MAX_RETRY_ALIGN 0 +#define OTP_CONFIG_INFO_MAX_RETRY_BITS 4 +#define OTP_CONFIG_INFO_MAX_RETRY_SHIFT 4 + +/* OTP :: CONFIG_INFO :: reserved3 [03:01] */ +#define OTP_CONFIG_INFO_reserved3_MASK 0x0000000e +#define OTP_CONFIG_INFO_reserved3_ALIGN 0 +#define OTP_CONFIG_INFO_reserved3_BITS 3 +#define OTP_CONFIG_INFO_reserved3_SHIFT 1 + +/* OTP :: CONFIG_INFO :: PROG_MODE [00:00] */ +#define OTP_CONFIG_INFO_PROG_MODE_MASK 0x00000001 +#define OTP_CONFIG_INFO_PROG_MODE_ALIGN 0 +#define OTP_CONFIG_INFO_PROG_MODE_BITS 1 +#define OTP_CONFIG_INFO_PROG_MODE_SHIFT 0 + + +/**************************************************************************** + * OTP :: CMD + ***************************************************************************/ +/* OTP :: CMD :: reserved0 [31:02] */ +#define OTP_CMD_reserved0_MASK 0xfffffffc +#define OTP_CMD_reserved0_ALIGN 0 +#define OTP_CMD_reserved0_BITS 30 +#define OTP_CMD_reserved0_SHIFT 2 + +/* OTP :: CMD :: KEYS_AVAIL [01:01] */ +#define OTP_CMD_KEYS_AVAIL_MASK 0x00000002 +#define OTP_CMD_KEYS_AVAIL_ALIGN 0 +#define OTP_CMD_KEYS_AVAIL_BITS 1 +#define OTP_CMD_KEYS_AVAIL_SHIFT 1 + +/* OTP :: CMD :: PROGRAM_OTP [00:00] */ +#define OTP_CMD_PROGRAM_OTP_MASK 0x00000001 +#define OTP_CMD_PROGRAM_OTP_ALIGN 0 +#define OTP_CMD_PROGRAM_OTP_BITS 1 +#define OTP_CMD_PROGRAM_OTP_SHIFT 0 + + +/**************************************************************************** + * OTP :: STATUS + ***************************************************************************/ +/* OTP :: STATUS :: reserved0 [31:30] */ +#define OTP_STATUS_reserved0_MASK 0xc0000000 +#define OTP_STATUS_reserved0_ALIGN 0 +#define OTP_STATUS_reserved0_BITS 2 +#define OTP_STATUS_reserved0_SHIFT 30 + +/* OTP :: STATUS :: TOTAL_RETRIES [29:17] */ +#define OTP_STATUS_TOTAL_RETRIES_MASK 0x3ffe0000 +#define OTP_STATUS_TOTAL_RETRIES_ALIGN 0 +#define OTP_STATUS_TOTAL_RETRIES_BITS 13 +#define OTP_STATUS_TOTAL_RETRIES_SHIFT 17 + +/* OTP :: STATUS :: ROWS_USED [16:12] */ +#define OTP_STATUS_ROWS_USED_MASK 0x0001f000 +#define OTP_STATUS_ROWS_USED_ALIGN 0 +#define OTP_STATUS_ROWS_USED_BITS 5 +#define OTP_STATUS_ROWS_USED_SHIFT 12 + +/* OTP :: STATUS :: MAX_RETRIES [11:08] */ +#define OTP_STATUS_MAX_RETRIES_MASK 0x00000f00 +#define OTP_STATUS_MAX_RETRIES_ALIGN 0 +#define OTP_STATUS_MAX_RETRIES_BITS 4 +#define OTP_STATUS_MAX_RETRIES_SHIFT 8 + +/* OTP :: STATUS :: PROG_STATUS [07:04] */ +#define OTP_STATUS_PROG_STATUS_MASK 0x000000f0 +#define OTP_STATUS_PROG_STATUS_ALIGN 0 +#define OTP_STATUS_PROG_STATUS_BITS 4 +#define OTP_STATUS_PROG_STATUS_SHIFT 4 + +/* OTP :: STATUS :: reserved1 [03:03] */ +#define OTP_STATUS_reserved1_MASK 0x00000008 +#define OTP_STATUS_reserved1_ALIGN 0 +#define OTP_STATUS_reserved1_BITS 1 +#define OTP_STATUS_reserved1_SHIFT 3 + +/* OTP :: STATUS :: CHECKSUM_MISMATCH [02:02] */ +#define OTP_STATUS_CHECKSUM_MISMATCH_MASK 0x00000004 +#define OTP_STATUS_CHECKSUM_MISMATCH_ALIGN 0 +#define OTP_STATUS_CHECKSUM_MISMATCH_BITS 1 +#define OTP_STATUS_CHECKSUM_MISMATCH_SHIFT 2 + +/* OTP :: STATUS :: INSUFFICIENT_ROWS [01:01] */ +#define OTP_STATUS_INSUFFICIENT_ROWS_MASK 0x00000002 +#define OTP_STATUS_INSUFFICIENT_ROWS_ALIGN 0 +#define OTP_STATUS_INSUFFICIENT_ROWS_BITS 1 +#define OTP_STATUS_INSUFFICIENT_ROWS_SHIFT 1 + +/* OTP :: STATUS :: PROGRAMMED [00:00] */ +#define OTP_STATUS_PROGRAMMED_MASK 0x00000001 +#define OTP_STATUS_PROGRAMMED_ALIGN 0 +#define OTP_STATUS_PROGRAMMED_BITS 1 +#define OTP_STATUS_PROGRAMMED_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_MISC + ***************************************************************************/ +/* OTP :: CONTENT_MISC :: reserved0 [31:06] */ +#define OTP_CONTENT_MISC_reserved0_MASK 0xffffffc0 +#define OTP_CONTENT_MISC_reserved0_ALIGN 0 +#define OTP_CONTENT_MISC_reserved0_BITS 26 +#define OTP_CONTENT_MISC_reserved0_SHIFT 6 + +/* OTP :: CONTENT_MISC :: DCI_SECURITY_ENABLE [05:05] */ +#define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_MASK 0x00000020 +#define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_ALIGN 0 +#define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_BITS 1 +#define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_SHIFT 5 + +/* OTP :: CONTENT_MISC :: AES_SECURITY_ENABLE [04:04] */ +#define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_MASK 0x00000010 +#define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_ALIGN 0 +#define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_BITS 1 +#define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_SHIFT 4 + +/* OTP :: CONTENT_MISC :: DISABLE_JTAG [03:03] */ +#define OTP_CONTENT_MISC_DISABLE_JTAG_MASK 0x00000008 +#define OTP_CONTENT_MISC_DISABLE_JTAG_ALIGN 0 +#define OTP_CONTENT_MISC_DISABLE_JTAG_BITS 1 +#define OTP_CONTENT_MISC_DISABLE_JTAG_SHIFT 3 + +/* OTP :: CONTENT_MISC :: DISABLE_UART [02:02] */ +#define OTP_CONTENT_MISC_DISABLE_UART_MASK 0x00000004 +#define OTP_CONTENT_MISC_DISABLE_UART_ALIGN 0 +#define OTP_CONTENT_MISC_DISABLE_UART_BITS 1 +#define OTP_CONTENT_MISC_DISABLE_UART_SHIFT 2 + +/* OTP :: CONTENT_MISC :: ENABLE_RANDOMIZATION [01:01] */ +#define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_MASK 0x00000002 +#define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_ALIGN 0 +#define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_BITS 1 +#define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_SHIFT 1 + +/* OTP :: CONTENT_MISC :: OTP_SECURITY_ENABLE [00:00] */ +#define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_MASK 0x00000001 +#define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_ALIGN 0 +#define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_BITS 1 +#define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_AES_0 + ***************************************************************************/ +/* OTP :: CONTENT_AES_0 :: AES_KEY_0 [31:00] */ +#define OTP_CONTENT_AES_0_AES_KEY_0_MASK 0xffffffff +#define OTP_CONTENT_AES_0_AES_KEY_0_ALIGN 0 +#define OTP_CONTENT_AES_0_AES_KEY_0_BITS 32 +#define OTP_CONTENT_AES_0_AES_KEY_0_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_AES_1 + ***************************************************************************/ +/* OTP :: CONTENT_AES_1 :: AES_KEY_1 [31:00] */ +#define OTP_CONTENT_AES_1_AES_KEY_1_MASK 0xffffffff +#define OTP_CONTENT_AES_1_AES_KEY_1_ALIGN 0 +#define OTP_CONTENT_AES_1_AES_KEY_1_BITS 32 +#define OTP_CONTENT_AES_1_AES_KEY_1_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_AES_2 + ***************************************************************************/ +/* OTP :: CONTENT_AES_2 :: AES_KEY_2 [31:00] */ +#define OTP_CONTENT_AES_2_AES_KEY_2_MASK 0xffffffff +#define OTP_CONTENT_AES_2_AES_KEY_2_ALIGN 0 +#define OTP_CONTENT_AES_2_AES_KEY_2_BITS 32 +#define OTP_CONTENT_AES_2_AES_KEY_2_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_AES_3 + ***************************************************************************/ +/* OTP :: CONTENT_AES_3 :: AES_KEY_3 [31:00] */ +#define OTP_CONTENT_AES_3_AES_KEY_3_MASK 0xffffffff +#define OTP_CONTENT_AES_3_AES_KEY_3_ALIGN 0 +#define OTP_CONTENT_AES_3_AES_KEY_3_BITS 32 +#define OTP_CONTENT_AES_3_AES_KEY_3_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_0 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_0 :: SHA_KEY_0 [31:00] */ +#define OTP_CONTENT_SHA_0_SHA_KEY_0_MASK 0xffffffff +#define OTP_CONTENT_SHA_0_SHA_KEY_0_ALIGN 0 +#define OTP_CONTENT_SHA_0_SHA_KEY_0_BITS 32 +#define OTP_CONTENT_SHA_0_SHA_KEY_0_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_1 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_1 :: SHA_KEY_1 [31:00] */ +#define OTP_CONTENT_SHA_1_SHA_KEY_1_MASK 0xffffffff +#define OTP_CONTENT_SHA_1_SHA_KEY_1_ALIGN 0 +#define OTP_CONTENT_SHA_1_SHA_KEY_1_BITS 32 +#define OTP_CONTENT_SHA_1_SHA_KEY_1_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_2 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_2 :: SHA_KEY_2 [31:00] */ +#define OTP_CONTENT_SHA_2_SHA_KEY_2_MASK 0xffffffff +#define OTP_CONTENT_SHA_2_SHA_KEY_2_ALIGN 0 +#define OTP_CONTENT_SHA_2_SHA_KEY_2_BITS 32 +#define OTP_CONTENT_SHA_2_SHA_KEY_2_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_3 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_3 :: SHA_KEY_3 [31:00] */ +#define OTP_CONTENT_SHA_3_SHA_KEY_3_MASK 0xffffffff +#define OTP_CONTENT_SHA_3_SHA_KEY_3_ALIGN 0 +#define OTP_CONTENT_SHA_3_SHA_KEY_3_BITS 32 +#define OTP_CONTENT_SHA_3_SHA_KEY_3_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_4 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_4 :: SHA_KEY_4 [31:00] */ +#define OTP_CONTENT_SHA_4_SHA_KEY_4_MASK 0xffffffff +#define OTP_CONTENT_SHA_4_SHA_KEY_4_ALIGN 0 +#define OTP_CONTENT_SHA_4_SHA_KEY_4_BITS 32 +#define OTP_CONTENT_SHA_4_SHA_KEY_4_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_5 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_5 :: SHA_KEY_5 [31:00] */ +#define OTP_CONTENT_SHA_5_SHA_KEY_5_MASK 0xffffffff +#define OTP_CONTENT_SHA_5_SHA_KEY_5_ALIGN 0 +#define OTP_CONTENT_SHA_5_SHA_KEY_5_BITS 32 +#define OTP_CONTENT_SHA_5_SHA_KEY_5_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_6 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_6 :: SHA_KEY_6 [31:00] */ +#define OTP_CONTENT_SHA_6_SHA_KEY_6_MASK 0xffffffff +#define OTP_CONTENT_SHA_6_SHA_KEY_6_ALIGN 0 +#define OTP_CONTENT_SHA_6_SHA_KEY_6_BITS 32 +#define OTP_CONTENT_SHA_6_SHA_KEY_6_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_SHA_7 + ***************************************************************************/ +/* OTP :: CONTENT_SHA_7 :: SHA_KEY_7 [31:00] */ +#define OTP_CONTENT_SHA_7_SHA_KEY_7_MASK 0xffffffff +#define OTP_CONTENT_SHA_7_SHA_KEY_7_ALIGN 0 +#define OTP_CONTENT_SHA_7_SHA_KEY_7_BITS 32 +#define OTP_CONTENT_SHA_7_SHA_KEY_7_SHIFT 0 + + +/**************************************************************************** + * OTP :: CONTENT_CHECKSUM + ***************************************************************************/ +/* OTP :: CONTENT_CHECKSUM :: reserved0 [31:16] */ +#define OTP_CONTENT_CHECKSUM_reserved0_MASK 0xffff0000 +#define OTP_CONTENT_CHECKSUM_reserved0_ALIGN 0 +#define OTP_CONTENT_CHECKSUM_reserved0_BITS 16 +#define OTP_CONTENT_CHECKSUM_reserved0_SHIFT 16 + +/* OTP :: CONTENT_CHECKSUM :: CHECKSUM [15:00] */ +#define OTP_CONTENT_CHECKSUM_CHECKSUM_MASK 0x0000ffff +#define OTP_CONTENT_CHECKSUM_CHECKSUM_ALIGN 0 +#define OTP_CONTENT_CHECKSUM_CHECKSUM_BITS 16 +#define OTP_CONTENT_CHECKSUM_CHECKSUM_SHIFT 0 + + +/**************************************************************************** + * OTP :: PROG_CTRL + ***************************************************************************/ +/* OTP :: PROG_CTRL :: reserved0 [31:02] */ +#define OTP_PROG_CTRL_reserved0_MASK 0xfffffffc +#define OTP_PROG_CTRL_reserved0_ALIGN 0 +#define OTP_PROG_CTRL_reserved0_BITS 30 +#define OTP_PROG_CTRL_reserved0_SHIFT 2 + +/* OTP :: PROG_CTRL :: ENABLE [01:01] */ +#define OTP_PROG_CTRL_ENABLE_MASK 0x00000002 +#define OTP_PROG_CTRL_ENABLE_ALIGN 0 +#define OTP_PROG_CTRL_ENABLE_BITS 1 +#define OTP_PROG_CTRL_ENABLE_SHIFT 1 + +/* OTP :: PROG_CTRL :: RST [00:00] */ +#define OTP_PROG_CTRL_RST_MASK 0x00000001 +#define OTP_PROG_CTRL_RST_ALIGN 0 +#define OTP_PROG_CTRL_RST_BITS 1 +#define OTP_PROG_CTRL_RST_SHIFT 0 + + +/**************************************************************************** + * OTP :: PROG_STATUS + ***************************************************************************/ +/* OTP :: PROG_STATUS :: reserved0 [31:02] */ +#define OTP_PROG_STATUS_reserved0_MASK 0xfffffffc +#define OTP_PROG_STATUS_reserved0_ALIGN 0 +#define OTP_PROG_STATUS_reserved0_BITS 30 +#define OTP_PROG_STATUS_reserved0_SHIFT 2 + +/* OTP :: PROG_STATUS :: ORDY [01:01] */ +#define OTP_PROG_STATUS_ORDY_MASK 0x00000002 +#define OTP_PROG_STATUS_ORDY_ALIGN 0 +#define OTP_PROG_STATUS_ORDY_BITS 1 +#define OTP_PROG_STATUS_ORDY_SHIFT 1 + +/* OTP :: PROG_STATUS :: IRDY [00:00] */ +#define OTP_PROG_STATUS_IRDY_MASK 0x00000001 +#define OTP_PROG_STATUS_IRDY_ALIGN 0 +#define OTP_PROG_STATUS_IRDY_BITS 1 +#define OTP_PROG_STATUS_IRDY_SHIFT 0 + + +/**************************************************************************** + * OTP :: PROG_PULSE + ***************************************************************************/ +/* OTP :: PROG_PULSE :: PROG_HI [31:00] */ +#define OTP_PROG_PULSE_PROG_HI_MASK 0xffffffff +#define OTP_PROG_PULSE_PROG_HI_ALIGN 0 +#define OTP_PROG_PULSE_PROG_HI_BITS 32 +#define OTP_PROG_PULSE_PROG_HI_SHIFT 0 + + +/**************************************************************************** + * OTP :: VERIFY_PULSE + ***************************************************************************/ +/* OTP :: VERIFY_PULSE :: PROG_LOW [31:16] */ +#define OTP_VERIFY_PULSE_PROG_LOW_MASK 0xffff0000 +#define OTP_VERIFY_PULSE_PROG_LOW_ALIGN 0 +#define OTP_VERIFY_PULSE_PROG_LOW_BITS 16 +#define OTP_VERIFY_PULSE_PROG_LOW_SHIFT 16 + +/* OTP :: VERIFY_PULSE :: VERIFY [15:00] */ +#define OTP_VERIFY_PULSE_VERIFY_MASK 0x0000ffff +#define OTP_VERIFY_PULSE_VERIFY_ALIGN 0 +#define OTP_VERIFY_PULSE_VERIFY_BITS 16 +#define OTP_VERIFY_PULSE_VERIFY_SHIFT 0 + + +/**************************************************************************** + * OTP :: PROG_MASK + ***************************************************************************/ +/* OTP :: PROG_MASK :: reserved0 [31:17] */ +#define OTP_PROG_MASK_reserved0_MASK 0xfffe0000 +#define OTP_PROG_MASK_reserved0_ALIGN 0 +#define OTP_PROG_MASK_reserved0_BITS 15 +#define OTP_PROG_MASK_reserved0_SHIFT 17 + +/* OTP :: PROG_MASK :: PROG_MASK [16:00] */ +#define OTP_PROG_MASK_PROG_MASK_MASK 0x0001ffff +#define OTP_PROG_MASK_PROG_MASK_ALIGN 0 +#define OTP_PROG_MASK_PROG_MASK_BITS 17 +#define OTP_PROG_MASK_PROG_MASK_SHIFT 0 + + +/**************************************************************************** + * OTP :: DATA_INPUT + ***************************************************************************/ +/* OTP :: DATA_INPUT :: reserved0 [31:31] */ +#define OTP_DATA_INPUT_reserved0_MASK 0x80000000 +#define OTP_DATA_INPUT_reserved0_ALIGN 0 +#define OTP_DATA_INPUT_reserved0_BITS 1 +#define OTP_DATA_INPUT_reserved0_SHIFT 31 + +/* OTP :: DATA_INPUT :: CMD [30:28] */ +#define OTP_DATA_INPUT_CMD_MASK 0x70000000 +#define OTP_DATA_INPUT_CMD_ALIGN 0 +#define OTP_DATA_INPUT_CMD_BITS 3 +#define OTP_DATA_INPUT_CMD_SHIFT 28 + +/* OTP :: DATA_INPUT :: reserved1 [27:26] */ +#define OTP_DATA_INPUT_reserved1_MASK 0x0c000000 +#define OTP_DATA_INPUT_reserved1_ALIGN 0 +#define OTP_DATA_INPUT_reserved1_BITS 2 +#define OTP_DATA_INPUT_reserved1_SHIFT 26 + +/* OTP :: DATA_INPUT :: ADDR [25:20] */ +#define OTP_DATA_INPUT_ADDR_MASK 0x03f00000 +#define OTP_DATA_INPUT_ADDR_ALIGN 0 +#define OTP_DATA_INPUT_ADDR_BITS 6 +#define OTP_DATA_INPUT_ADDR_SHIFT 20 + +/* OTP :: DATA_INPUT :: reserved2 [19:18] */ +#define OTP_DATA_INPUT_reserved2_MASK 0x000c0000 +#define OTP_DATA_INPUT_reserved2_ALIGN 0 +#define OTP_DATA_INPUT_reserved2_BITS 2 +#define OTP_DATA_INPUT_reserved2_SHIFT 18 + +/* OTP :: DATA_INPUT :: WRCOL [17:17] */ +#define OTP_DATA_INPUT_WRCOL_MASK 0x00020000 +#define OTP_DATA_INPUT_WRCOL_ALIGN 0 +#define OTP_DATA_INPUT_WRCOL_BITS 1 +#define OTP_DATA_INPUT_WRCOL_SHIFT 17 + +/* OTP :: DATA_INPUT :: DIN [16:00] */ +#define OTP_DATA_INPUT_DIN_MASK 0x0001ffff +#define OTP_DATA_INPUT_DIN_ALIGN 0 +#define OTP_DATA_INPUT_DIN_BITS 17 +#define OTP_DATA_INPUT_DIN_SHIFT 0 + + +/**************************************************************************** + * OTP :: DATA_OUTPUT + ***************************************************************************/ +/* OTP :: DATA_OUTPUT :: reserved0 [31:17] */ +#define OTP_DATA_OUTPUT_reserved0_MASK 0xfffe0000 +#define OTP_DATA_OUTPUT_reserved0_ALIGN 0 +#define OTP_DATA_OUTPUT_reserved0_BITS 15 +#define OTP_DATA_OUTPUT_reserved0_SHIFT 17 + +/* OTP :: DATA_OUTPUT :: DOUT [16:00] */ +#define OTP_DATA_OUTPUT_DOUT_MASK 0x0001ffff +#define OTP_DATA_OUTPUT_DOUT_ALIGN 0 +#define OTP_DATA_OUTPUT_DOUT_BITS 17 +#define OTP_DATA_OUTPUT_DOUT_SHIFT 0 + + +/**************************************************************************** + * BCM70012_OTP_TOP_OTP_GR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * OTP_GR_BRIDGE :: REVISION + ***************************************************************************/ +/* OTP_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define OTP_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define OTP_GR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define OTP_GR_BRIDGE_REVISION_reserved0_BITS 16 +#define OTP_GR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* OTP_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define OTP_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define OTP_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define OTP_GR_BRIDGE_REVISION_MAJOR_BITS 8 +#define OTP_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* OTP_GR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define OTP_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define OTP_GR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define OTP_GR_BRIDGE_REVISION_MINOR_BITS 8 +#define OTP_GR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * OTP_GR_BRIDGE :: CTRL + ***************************************************************************/ +/* OTP_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ +#define OTP_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe +#define OTP_GR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define OTP_GR_BRIDGE_CTRL_reserved0_BITS 31 +#define OTP_GR_BRIDGE_CTRL_reserved0_SHIFT 1 + +/* OTP_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + + +/**************************************************************************** + * OTP_GR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* OTP_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* OTP_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * OTP_GR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* OTP_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* OTP_GR_BRIDGE :: SPARE_SW_RESET_1 :: OTP_00_SW_RESET [00:00] */ +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_MASK 0x00000001 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_ALIGN 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_BITS 1 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_SHIFT 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_DEASSERT 0 +#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * BCM70012_AES_TOP_AES + ***************************************************************************/ +/**************************************************************************** + * AES :: CONFIG_INFO + ***************************************************************************/ +/* AES :: CONFIG_INFO :: SWAP [31:31] */ +#define AES_CONFIG_INFO_SWAP_MASK 0x80000000 +#define AES_CONFIG_INFO_SWAP_ALIGN 0 +#define AES_CONFIG_INFO_SWAP_BITS 1 +#define AES_CONFIG_INFO_SWAP_SHIFT 31 + +/* AES :: CONFIG_INFO :: reserved0 [30:19] */ +#define AES_CONFIG_INFO_reserved0_MASK 0x7ff80000 +#define AES_CONFIG_INFO_reserved0_ALIGN 0 +#define AES_CONFIG_INFO_reserved0_BITS 12 +#define AES_CONFIG_INFO_reserved0_SHIFT 19 + +/* AES :: CONFIG_INFO :: OFFSET [18:02] */ +#define AES_CONFIG_INFO_OFFSET_MASK 0x0007fffc +#define AES_CONFIG_INFO_OFFSET_ALIGN 0 +#define AES_CONFIG_INFO_OFFSET_BITS 17 +#define AES_CONFIG_INFO_OFFSET_SHIFT 2 + +/* AES :: CONFIG_INFO :: reserved1 [01:00] */ +#define AES_CONFIG_INFO_reserved1_MASK 0x00000003 +#define AES_CONFIG_INFO_reserved1_ALIGN 0 +#define AES_CONFIG_INFO_reserved1_BITS 2 +#define AES_CONFIG_INFO_reserved1_SHIFT 0 + + +/**************************************************************************** + * AES :: CMD + ***************************************************************************/ +/* AES :: CMD :: reserved0 [31:13] */ +#define AES_CMD_reserved0_MASK 0xffffe000 +#define AES_CMD_reserved0_ALIGN 0 +#define AES_CMD_reserved0_BITS 19 +#define AES_CMD_reserved0_SHIFT 13 + +/* AES :: CMD :: WRITE_EEPROM [12:12] */ +#define AES_CMD_WRITE_EEPROM_MASK 0x00001000 +#define AES_CMD_WRITE_EEPROM_ALIGN 0 +#define AES_CMD_WRITE_EEPROM_BITS 1 +#define AES_CMD_WRITE_EEPROM_SHIFT 12 + +/* AES :: CMD :: reserved1 [11:09] */ +#define AES_CMD_reserved1_MASK 0x00000e00 +#define AES_CMD_reserved1_ALIGN 0 +#define AES_CMD_reserved1_BITS 3 +#define AES_CMD_reserved1_SHIFT 9 + +/* AES :: CMD :: START_EEPROM_COPY [08:08] */ +#define AES_CMD_START_EEPROM_COPY_MASK 0x00000100 +#define AES_CMD_START_EEPROM_COPY_ALIGN 0 +#define AES_CMD_START_EEPROM_COPY_BITS 1 +#define AES_CMD_START_EEPROM_COPY_SHIFT 8 + +/* AES :: CMD :: reserved2 [07:05] */ +#define AES_CMD_reserved2_MASK 0x000000e0 +#define AES_CMD_reserved2_ALIGN 0 +#define AES_CMD_reserved2_BITS 3 +#define AES_CMD_reserved2_SHIFT 5 + +/* AES :: CMD :: PREPARE_ENCRYPTION [04:04] */ +#define AES_CMD_PREPARE_ENCRYPTION_MASK 0x00000010 +#define AES_CMD_PREPARE_ENCRYPTION_ALIGN 0 +#define AES_CMD_PREPARE_ENCRYPTION_BITS 1 +#define AES_CMD_PREPARE_ENCRYPTION_SHIFT 4 + +/* AES :: CMD :: reserved3 [03:01] */ +#define AES_CMD_reserved3_MASK 0x0000000e +#define AES_CMD_reserved3_ALIGN 0 +#define AES_CMD_reserved3_BITS 3 +#define AES_CMD_reserved3_SHIFT 1 + +/* AES :: CMD :: START_KEY_LOAD [00:00] */ +#define AES_CMD_START_KEY_LOAD_MASK 0x00000001 +#define AES_CMD_START_KEY_LOAD_ALIGN 0 +#define AES_CMD_START_KEY_LOAD_BITS 1 +#define AES_CMD_START_KEY_LOAD_SHIFT 0 + + +/**************************************************************************** + * AES :: STATUS + ***************************************************************************/ +/* AES :: STATUS :: reserved0 [31:23] */ +#define AES_STATUS_reserved0_MASK 0xff800000 +#define AES_STATUS_reserved0_ALIGN 0 +#define AES_STATUS_reserved0_BITS 9 +#define AES_STATUS_reserved0_SHIFT 23 + +/* AES :: STATUS :: STUCK_AT_ZERO [22:22] */ +#define AES_STATUS_STUCK_AT_ZERO_MASK 0x00400000 +#define AES_STATUS_STUCK_AT_ZERO_ALIGN 0 +#define AES_STATUS_STUCK_AT_ZERO_BITS 1 +#define AES_STATUS_STUCK_AT_ZERO_SHIFT 22 + +/* AES :: STATUS :: STUCK_AT_ONE [21:21] */ +#define AES_STATUS_STUCK_AT_ONE_MASK 0x00200000 +#define AES_STATUS_STUCK_AT_ONE_ALIGN 0 +#define AES_STATUS_STUCK_AT_ONE_BITS 1 +#define AES_STATUS_STUCK_AT_ONE_SHIFT 21 + +/* AES :: STATUS :: RANDOM_READY [20:20] */ +#define AES_STATUS_RANDOM_READY_MASK 0x00100000 +#define AES_STATUS_RANDOM_READY_ALIGN 0 +#define AES_STATUS_RANDOM_READY_BITS 1 +#define AES_STATUS_RANDOM_READY_SHIFT 20 + +/* AES :: STATUS :: reserved1 [19:16] */ +#define AES_STATUS_reserved1_MASK 0x000f0000 +#define AES_STATUS_reserved1_ALIGN 0 +#define AES_STATUS_reserved1_BITS 4 +#define AES_STATUS_reserved1_SHIFT 16 + +/* AES :: STATUS :: WRITE_EEPROM_TIMEOUT [15:15] */ +#define AES_STATUS_WRITE_EEPROM_TIMEOUT_MASK 0x00008000 +#define AES_STATUS_WRITE_EEPROM_TIMEOUT_ALIGN 0 +#define AES_STATUS_WRITE_EEPROM_TIMEOUT_BITS 1 +#define AES_STATUS_WRITE_EEPROM_TIMEOUT_SHIFT 15 + +/* AES :: STATUS :: WRITE_DATA_MISMATCH [14:14] */ +#define AES_STATUS_WRITE_DATA_MISMATCH_MASK 0x00004000 +#define AES_STATUS_WRITE_DATA_MISMATCH_ALIGN 0 +#define AES_STATUS_WRITE_DATA_MISMATCH_BITS 1 +#define AES_STATUS_WRITE_DATA_MISMATCH_SHIFT 14 + +/* AES :: STATUS :: WRITE_GISB_ERROR [13:13] */ +#define AES_STATUS_WRITE_GISB_ERROR_MASK 0x00002000 +#define AES_STATUS_WRITE_GISB_ERROR_ALIGN 0 +#define AES_STATUS_WRITE_GISB_ERROR_BITS 1 +#define AES_STATUS_WRITE_GISB_ERROR_SHIFT 13 + +/* AES :: STATUS :: WRITE_DONE [12:12] */ +#define AES_STATUS_WRITE_DONE_MASK 0x00001000 +#define AES_STATUS_WRITE_DONE_ALIGN 0 +#define AES_STATUS_WRITE_DONE_BITS 1 +#define AES_STATUS_WRITE_DONE_SHIFT 12 + +/* AES :: STATUS :: reserved2 [11:11] */ +#define AES_STATUS_reserved2_MASK 0x00000800 +#define AES_STATUS_reserved2_ALIGN 0 +#define AES_STATUS_reserved2_BITS 1 +#define AES_STATUS_reserved2_SHIFT 11 + +/* AES :: STATUS :: COPY_EEPROM_ERROR [10:10] */ +#define AES_STATUS_COPY_EEPROM_ERROR_MASK 0x00000400 +#define AES_STATUS_COPY_EEPROM_ERROR_ALIGN 0 +#define AES_STATUS_COPY_EEPROM_ERROR_BITS 1 +#define AES_STATUS_COPY_EEPROM_ERROR_SHIFT 10 + +/* AES :: STATUS :: COPY_GISB_ERROR [09:09] */ +#define AES_STATUS_COPY_GISB_ERROR_MASK 0x00000200 +#define AES_STATUS_COPY_GISB_ERROR_ALIGN 0 +#define AES_STATUS_COPY_GISB_ERROR_BITS 1 +#define AES_STATUS_COPY_GISB_ERROR_SHIFT 9 + +/* AES :: STATUS :: COPY_DONE [08:08] */ +#define AES_STATUS_COPY_DONE_MASK 0x00000100 +#define AES_STATUS_COPY_DONE_ALIGN 0 +#define AES_STATUS_COPY_DONE_BITS 1 +#define AES_STATUS_COPY_DONE_SHIFT 8 + +/* AES :: STATUS :: PREPARE_EEPROM_TIMEOUT [07:07] */ +#define AES_STATUS_PREPARE_EEPROM_TIMEOUT_MASK 0x00000080 +#define AES_STATUS_PREPARE_EEPROM_TIMEOUT_ALIGN 0 +#define AES_STATUS_PREPARE_EEPROM_TIMEOUT_BITS 1 +#define AES_STATUS_PREPARE_EEPROM_TIMEOUT_SHIFT 7 + +/* AES :: STATUS :: PREPARE_DATA_MISMATCH [06:06] */ +#define AES_STATUS_PREPARE_DATA_MISMATCH_MASK 0x00000040 +#define AES_STATUS_PREPARE_DATA_MISMATCH_ALIGN 0 +#define AES_STATUS_PREPARE_DATA_MISMATCH_BITS 1 +#define AES_STATUS_PREPARE_DATA_MISMATCH_SHIFT 6 + +/* AES :: STATUS :: PREPARE_GISB_ERROR [05:05] */ +#define AES_STATUS_PREPARE_GISB_ERROR_MASK 0x00000020 +#define AES_STATUS_PREPARE_GISB_ERROR_ALIGN 0 +#define AES_STATUS_PREPARE_GISB_ERROR_BITS 1 +#define AES_STATUS_PREPARE_GISB_ERROR_SHIFT 5 + +/* AES :: STATUS :: PREPARE_DONE [04:04] */ +#define AES_STATUS_PREPARE_DONE_MASK 0x00000010 +#define AES_STATUS_PREPARE_DONE_ALIGN 0 +#define AES_STATUS_PREPARE_DONE_BITS 1 +#define AES_STATUS_PREPARE_DONE_SHIFT 4 + +/* AES :: STATUS :: reserved3 [03:02] */ +#define AES_STATUS_reserved3_MASK 0x0000000c +#define AES_STATUS_reserved3_ALIGN 0 +#define AES_STATUS_reserved3_BITS 2 +#define AES_STATUS_reserved3_SHIFT 2 + +/* AES :: STATUS :: KEY_LOAD_GISB_ERROR [01:01] */ +#define AES_STATUS_KEY_LOAD_GISB_ERROR_MASK 0x00000002 +#define AES_STATUS_KEY_LOAD_GISB_ERROR_ALIGN 0 +#define AES_STATUS_KEY_LOAD_GISB_ERROR_BITS 1 +#define AES_STATUS_KEY_LOAD_GISB_ERROR_SHIFT 1 + +/* AES :: STATUS :: KEY_LOAD_DONE [00:00] */ +#define AES_STATUS_KEY_LOAD_DONE_MASK 0x00000001 +#define AES_STATUS_KEY_LOAD_DONE_ALIGN 0 +#define AES_STATUS_KEY_LOAD_DONE_BITS 1 +#define AES_STATUS_KEY_LOAD_DONE_SHIFT 0 + + +/**************************************************************************** + * AES :: EEPROM_CONFIG + ***************************************************************************/ +/* AES :: EEPROM_CONFIG :: LENGTH [31:20] */ +#define AES_EEPROM_CONFIG_LENGTH_MASK 0xfff00000 +#define AES_EEPROM_CONFIG_LENGTH_ALIGN 0 +#define AES_EEPROM_CONFIG_LENGTH_BITS 12 +#define AES_EEPROM_CONFIG_LENGTH_SHIFT 20 + +/* AES :: EEPROM_CONFIG :: reserved0 [19:16] */ +#define AES_EEPROM_CONFIG_reserved0_MASK 0x000f0000 +#define AES_EEPROM_CONFIG_reserved0_ALIGN 0 +#define AES_EEPROM_CONFIG_reserved0_BITS 4 +#define AES_EEPROM_CONFIG_reserved0_SHIFT 16 + +/* AES :: EEPROM_CONFIG :: START_ADDR [15:02] */ +#define AES_EEPROM_CONFIG_START_ADDR_MASK 0x0000fffc +#define AES_EEPROM_CONFIG_START_ADDR_ALIGN 0 +#define AES_EEPROM_CONFIG_START_ADDR_BITS 14 +#define AES_EEPROM_CONFIG_START_ADDR_SHIFT 2 + +/* AES :: EEPROM_CONFIG :: reserved1 [01:00] */ +#define AES_EEPROM_CONFIG_reserved1_MASK 0x00000003 +#define AES_EEPROM_CONFIG_reserved1_ALIGN 0 +#define AES_EEPROM_CONFIG_reserved1_BITS 2 +#define AES_EEPROM_CONFIG_reserved1_SHIFT 0 + + +/**************************************************************************** + * AES :: EEPROM_DATA_0 + ***************************************************************************/ +/* AES :: EEPROM_DATA_0 :: DATA [31:00] */ +#define AES_EEPROM_DATA_0_DATA_MASK 0xffffffff +#define AES_EEPROM_DATA_0_DATA_ALIGN 0 +#define AES_EEPROM_DATA_0_DATA_BITS 32 +#define AES_EEPROM_DATA_0_DATA_SHIFT 0 + + +/**************************************************************************** + * AES :: EEPROM_DATA_1 + ***************************************************************************/ +/* AES :: EEPROM_DATA_1 :: DATA [31:00] */ +#define AES_EEPROM_DATA_1_DATA_MASK 0xffffffff +#define AES_EEPROM_DATA_1_DATA_ALIGN 0 +#define AES_EEPROM_DATA_1_DATA_BITS 32 +#define AES_EEPROM_DATA_1_DATA_SHIFT 0 + + +/**************************************************************************** + * AES :: EEPROM_DATA_2 + ***************************************************************************/ +/* AES :: EEPROM_DATA_2 :: DATA [31:00] */ +#define AES_EEPROM_DATA_2_DATA_MASK 0xffffffff +#define AES_EEPROM_DATA_2_DATA_ALIGN 0 +#define AES_EEPROM_DATA_2_DATA_BITS 32 +#define AES_EEPROM_DATA_2_DATA_SHIFT 0 + + +/**************************************************************************** + * AES :: EEPROM_DATA_3 + ***************************************************************************/ +/* AES :: EEPROM_DATA_3 :: DATA [31:00] */ +#define AES_EEPROM_DATA_3_DATA_MASK 0xffffffff +#define AES_EEPROM_DATA_3_DATA_ALIGN 0 +#define AES_EEPROM_DATA_3_DATA_BITS 32 +#define AES_EEPROM_DATA_3_DATA_SHIFT 0 + + +/**************************************************************************** + * BCM70012_AES_TOP_AES_RGR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * AES_RGR_BRIDGE :: REVISION + ***************************************************************************/ +/* AES_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define AES_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define AES_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define AES_RGR_BRIDGE_REVISION_reserved0_BITS 16 +#define AES_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* AES_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define AES_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define AES_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define AES_RGR_BRIDGE_REVISION_MAJOR_BITS 8 +#define AES_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* AES_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define AES_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define AES_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define AES_RGR_BRIDGE_REVISION_MINOR_BITS 8 +#define AES_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * AES_RGR_BRIDGE :: CTRL + ***************************************************************************/ +/* AES_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ +#define AES_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc +#define AES_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define AES_RGR_BRIDGE_CTRL_reserved0_BITS 30 +#define AES_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 + +/* AES_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ +#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 +#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 +#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 +#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 +#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 +#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 + +/* AES_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + + +/**************************************************************************** + * AES_RGR_BRIDGE :: RBUS_TIMER + ***************************************************************************/ +/* AES_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ +#define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 +#define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 +#define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 +#define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 + +/* AES_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ +#define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff +#define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 +#define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 +#define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 + + +/**************************************************************************** + * AES_RGR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* AES_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* AES_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * AES_RGR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* AES_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* AES_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 +#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * BCM70012_DCI_TOP_DCI + ***************************************************************************/ +/**************************************************************************** + * DCI :: CMD + ***************************************************************************/ +/* DCI :: CMD :: reserved0 [31:09] */ +#define DCI_CMD_reserved0_MASK 0xfffffe00 +#define DCI_CMD_reserved0_ALIGN 0 +#define DCI_CMD_reserved0_BITS 23 +#define DCI_CMD_reserved0_SHIFT 9 + +/* DCI :: CMD :: FORCE_FW_VALIDATED [08:08] */ +#define DCI_CMD_FORCE_FW_VALIDATED_MASK 0x00000100 +#define DCI_CMD_FORCE_FW_VALIDATED_ALIGN 0 +#define DCI_CMD_FORCE_FW_VALIDATED_BITS 1 +#define DCI_CMD_FORCE_FW_VALIDATED_SHIFT 8 + +/* DCI :: CMD :: reserved1 [07:05] */ +#define DCI_CMD_reserved1_MASK 0x000000e0 +#define DCI_CMD_reserved1_ALIGN 0 +#define DCI_CMD_reserved1_BITS 3 +#define DCI_CMD_reserved1_SHIFT 5 + +/* DCI :: CMD :: START_PROCESSOR [04:04] */ +#define DCI_CMD_START_PROCESSOR_MASK 0x00000010 +#define DCI_CMD_START_PROCESSOR_ALIGN 0 +#define DCI_CMD_START_PROCESSOR_BITS 1 +#define DCI_CMD_START_PROCESSOR_SHIFT 4 + +/* DCI :: CMD :: reserved2 [03:02] */ +#define DCI_CMD_reserved2_MASK 0x0000000c +#define DCI_CMD_reserved2_ALIGN 0 +#define DCI_CMD_reserved2_BITS 2 +#define DCI_CMD_reserved2_SHIFT 2 + +/* DCI :: CMD :: DOWNLOAD_COMPLETE [01:01] */ +#define DCI_CMD_DOWNLOAD_COMPLETE_MASK 0x00000002 +#define DCI_CMD_DOWNLOAD_COMPLETE_ALIGN 0 +#define DCI_CMD_DOWNLOAD_COMPLETE_BITS 1 +#define DCI_CMD_DOWNLOAD_COMPLETE_SHIFT 1 + +/* DCI :: CMD :: INITIATE_FW_DOWNLOAD [00:00] */ +#define DCI_CMD_INITIATE_FW_DOWNLOAD_MASK 0x00000001 +#define DCI_CMD_INITIATE_FW_DOWNLOAD_ALIGN 0 +#define DCI_CMD_INITIATE_FW_DOWNLOAD_BITS 1 +#define DCI_CMD_INITIATE_FW_DOWNLOAD_SHIFT 0 + + +/**************************************************************************** + * DCI :: STATUS + ***************************************************************************/ +/* DCI :: STATUS :: reserved0 [31:10] */ +#define DCI_STATUS_reserved0_MASK 0xfffffc00 +#define DCI_STATUS_reserved0_ALIGN 0 +#define DCI_STATUS_reserved0_BITS 22 +#define DCI_STATUS_reserved0_SHIFT 10 + +/* DCI :: STATUS :: SIGNATURE_MATCHED [09:09] */ +#define DCI_STATUS_SIGNATURE_MATCHED_MASK 0x00000200 +#define DCI_STATUS_SIGNATURE_MATCHED_ALIGN 0 +#define DCI_STATUS_SIGNATURE_MATCHED_BITS 1 +#define DCI_STATUS_SIGNATURE_MATCHED_SHIFT 9 + +/* DCI :: STATUS :: SIGNATURE_MISMATCH [08:08] */ +#define DCI_STATUS_SIGNATURE_MISMATCH_MASK 0x00000100 +#define DCI_STATUS_SIGNATURE_MISMATCH_ALIGN 0 +#define DCI_STATUS_SIGNATURE_MISMATCH_BITS 1 +#define DCI_STATUS_SIGNATURE_MISMATCH_SHIFT 8 + +/* DCI :: STATUS :: reserved1 [07:06] */ +#define DCI_STATUS_reserved1_MASK 0x000000c0 +#define DCI_STATUS_reserved1_ALIGN 0 +#define DCI_STATUS_reserved1_BITS 2 +#define DCI_STATUS_reserved1_SHIFT 6 + +/* DCI :: STATUS :: GISB_ERROR [05:05] */ +#define DCI_STATUS_GISB_ERROR_MASK 0x00000020 +#define DCI_STATUS_GISB_ERROR_ALIGN 0 +#define DCI_STATUS_GISB_ERROR_BITS 1 +#define DCI_STATUS_GISB_ERROR_SHIFT 5 + +/* DCI :: STATUS :: DOWNLOAD_READY [04:04] */ +#define DCI_STATUS_DOWNLOAD_READY_MASK 0x00000010 +#define DCI_STATUS_DOWNLOAD_READY_ALIGN 0 +#define DCI_STATUS_DOWNLOAD_READY_BITS 1 +#define DCI_STATUS_DOWNLOAD_READY_SHIFT 4 + +/* DCI :: STATUS :: reserved2 [03:01] */ +#define DCI_STATUS_reserved2_MASK 0x0000000e +#define DCI_STATUS_reserved2_ALIGN 0 +#define DCI_STATUS_reserved2_BITS 3 +#define DCI_STATUS_reserved2_SHIFT 1 + +/* DCI :: STATUS :: FIRMWARE_VALIDATED [00:00] */ +#define DCI_STATUS_FIRMWARE_VALIDATED_MASK 0x00000001 +#define DCI_STATUS_FIRMWARE_VALIDATED_ALIGN 0 +#define DCI_STATUS_FIRMWARE_VALIDATED_BITS 1 +#define DCI_STATUS_FIRMWARE_VALIDATED_SHIFT 0 + + +/**************************************************************************** + * DCI :: DRAM_BASE_ADDR + ***************************************************************************/ +/* DCI :: DRAM_BASE_ADDR :: reserved0 [31:13] */ +#define DCI_DRAM_BASE_ADDR_reserved0_MASK 0xffffe000 +#define DCI_DRAM_BASE_ADDR_reserved0_ALIGN 0 +#define DCI_DRAM_BASE_ADDR_reserved0_BITS 19 +#define DCI_DRAM_BASE_ADDR_reserved0_SHIFT 13 + +/* DCI :: DRAM_BASE_ADDR :: BASE_ADDR [12:00] */ +#define DCI_DRAM_BASE_ADDR_BASE_ADDR_MASK 0x00001fff +#define DCI_DRAM_BASE_ADDR_BASE_ADDR_ALIGN 0 +#define DCI_DRAM_BASE_ADDR_BASE_ADDR_BITS 13 +#define DCI_DRAM_BASE_ADDR_BASE_ADDR_SHIFT 0 + + +/**************************************************************************** + * DCI :: FIRMWARE_ADDR + ***************************************************************************/ +/* DCI :: FIRMWARE_ADDR :: reserved0 [31:19] */ +#define DCI_FIRMWARE_ADDR_reserved0_MASK 0xfff80000 +#define DCI_FIRMWARE_ADDR_reserved0_ALIGN 0 +#define DCI_FIRMWARE_ADDR_reserved0_BITS 13 +#define DCI_FIRMWARE_ADDR_reserved0_SHIFT 19 + +/* DCI :: FIRMWARE_ADDR :: FW_ADDR [18:02] */ +#define DCI_FIRMWARE_ADDR_FW_ADDR_MASK 0x0007fffc +#define DCI_FIRMWARE_ADDR_FW_ADDR_ALIGN 0 +#define DCI_FIRMWARE_ADDR_FW_ADDR_BITS 17 +#define DCI_FIRMWARE_ADDR_FW_ADDR_SHIFT 2 + +/* DCI :: FIRMWARE_ADDR :: reserved1 [01:00] */ +#define DCI_FIRMWARE_ADDR_reserved1_MASK 0x00000003 +#define DCI_FIRMWARE_ADDR_reserved1_ALIGN 0 +#define DCI_FIRMWARE_ADDR_reserved1_BITS 2 +#define DCI_FIRMWARE_ADDR_reserved1_SHIFT 0 + + +/**************************************************************************** + * DCI :: FIRMWARE_DATA + ***************************************************************************/ +/* DCI :: FIRMWARE_DATA :: FW_DATA [31:00] */ +#define DCI_FIRMWARE_DATA_FW_DATA_MASK 0xffffffff +#define DCI_FIRMWARE_DATA_FW_DATA_ALIGN 0 +#define DCI_FIRMWARE_DATA_FW_DATA_BITS 32 +#define DCI_FIRMWARE_DATA_FW_DATA_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_0 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_0 :: SIG_DATA_0 [31:00] */ +#define DCI_SIGNATURE_DATA_0_SIG_DATA_0_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_0_SIG_DATA_0_ALIGN 0 +#define DCI_SIGNATURE_DATA_0_SIG_DATA_0_BITS 32 +#define DCI_SIGNATURE_DATA_0_SIG_DATA_0_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_1 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_1 :: SIG_DATA_1 [31:00] */ +#define DCI_SIGNATURE_DATA_1_SIG_DATA_1_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_1_SIG_DATA_1_ALIGN 0 +#define DCI_SIGNATURE_DATA_1_SIG_DATA_1_BITS 32 +#define DCI_SIGNATURE_DATA_1_SIG_DATA_1_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_2 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_2 :: SIG_DATA_2 [31:00] */ +#define DCI_SIGNATURE_DATA_2_SIG_DATA_2_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_2_SIG_DATA_2_ALIGN 0 +#define DCI_SIGNATURE_DATA_2_SIG_DATA_2_BITS 32 +#define DCI_SIGNATURE_DATA_2_SIG_DATA_2_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_3 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_3 :: SIG_DATA_3 [31:00] */ +#define DCI_SIGNATURE_DATA_3_SIG_DATA_3_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_3_SIG_DATA_3_ALIGN 0 +#define DCI_SIGNATURE_DATA_3_SIG_DATA_3_BITS 32 +#define DCI_SIGNATURE_DATA_3_SIG_DATA_3_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_4 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_4 :: SIG_DATA_4 [31:00] */ +#define DCI_SIGNATURE_DATA_4_SIG_DATA_4_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_4_SIG_DATA_4_ALIGN 0 +#define DCI_SIGNATURE_DATA_4_SIG_DATA_4_BITS 32 +#define DCI_SIGNATURE_DATA_4_SIG_DATA_4_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_5 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_5 :: SIG_DATA_5 [31:00] */ +#define DCI_SIGNATURE_DATA_5_SIG_DATA_5_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_5_SIG_DATA_5_ALIGN 0 +#define DCI_SIGNATURE_DATA_5_SIG_DATA_5_BITS 32 +#define DCI_SIGNATURE_DATA_5_SIG_DATA_5_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_6 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_6 :: SIG_DATA_6 [31:00] */ +#define DCI_SIGNATURE_DATA_6_SIG_DATA_6_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_6_SIG_DATA_6_ALIGN 0 +#define DCI_SIGNATURE_DATA_6_SIG_DATA_6_BITS 32 +#define DCI_SIGNATURE_DATA_6_SIG_DATA_6_SHIFT 0 + + +/**************************************************************************** + * DCI :: SIGNATURE_DATA_7 + ***************************************************************************/ +/* DCI :: SIGNATURE_DATA_7 :: SIG_DATA_7 [31:00] */ +#define DCI_SIGNATURE_DATA_7_SIG_DATA_7_MASK 0xffffffff +#define DCI_SIGNATURE_DATA_7_SIG_DATA_7_ALIGN 0 +#define DCI_SIGNATURE_DATA_7_SIG_DATA_7_BITS 32 +#define DCI_SIGNATURE_DATA_7_SIG_DATA_7_SHIFT 0 + + +/**************************************************************************** + * BCM70012_DCI_TOP_DCI_RGR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * DCI_RGR_BRIDGE :: REVISION + ***************************************************************************/ +/* DCI_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define DCI_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define DCI_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define DCI_RGR_BRIDGE_REVISION_reserved0_BITS 16 +#define DCI_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* DCI_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define DCI_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define DCI_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define DCI_RGR_BRIDGE_REVISION_MAJOR_BITS 8 +#define DCI_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* DCI_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define DCI_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define DCI_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define DCI_RGR_BRIDGE_REVISION_MINOR_BITS 8 +#define DCI_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * DCI_RGR_BRIDGE :: CTRL + ***************************************************************************/ +/* DCI_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ +#define DCI_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc +#define DCI_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define DCI_RGR_BRIDGE_CTRL_reserved0_BITS 30 +#define DCI_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 + +/* DCI_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ +#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 +#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 +#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 +#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 +#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 +#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 + +/* DCI_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + + +/**************************************************************************** + * DCI_RGR_BRIDGE :: RBUS_TIMER + ***************************************************************************/ +/* DCI_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ +#define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 +#define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 +#define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 +#define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 + +/* DCI_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ +#define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff +#define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 +#define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 +#define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 + + +/**************************************************************************** + * DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 +#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * BCM70012_CCE_TOP_CCE_RGR_BRIDGE + ***************************************************************************/ +/**************************************************************************** + * CCE_RGR_BRIDGE :: REVISION + ***************************************************************************/ +/* CCE_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ +#define CCE_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 +#define CCE_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 +#define CCE_RGR_BRIDGE_REVISION_reserved0_BITS 16 +#define CCE_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 + +/* CCE_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ +#define CCE_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 +#define CCE_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 +#define CCE_RGR_BRIDGE_REVISION_MAJOR_BITS 8 +#define CCE_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 + +/* CCE_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ +#define CCE_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff +#define CCE_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 +#define CCE_RGR_BRIDGE_REVISION_MINOR_BITS 8 +#define CCE_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 + + +/**************************************************************************** + * CCE_RGR_BRIDGE :: CTRL + ***************************************************************************/ +/* CCE_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ +#define CCE_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc +#define CCE_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 +#define CCE_RGR_BRIDGE_CTRL_reserved0_BITS 30 +#define CCE_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 + +/* CCE_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ +#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 +#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 +#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 +#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 +#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 +#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 + +/* CCE_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ +#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 +#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 +#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 +#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 +#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 +#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 + + +/**************************************************************************** + * CCE_RGR_BRIDGE :: RBUS_TIMER + ***************************************************************************/ +/* CCE_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ +#define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 +#define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 +#define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 +#define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 + +/* CCE_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ +#define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff +#define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 +#define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 +#define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 + + +/**************************************************************************** + * CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 + ***************************************************************************/ +/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 + +/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 + ***************************************************************************/ +/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 + +/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 +#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 + + +/**************************************************************************** + * Datatype Definitions. + ***************************************************************************/ +#endif /* #ifndef MACFILE_H__ */ + +/* End of File */ + diff --git a/drivers/staging/crystalhd/crystalhd_cmds.c b/drivers/staging/crystalhd/crystalhd_cmds.c new file mode 100644 index 000000000000..39c641d6b672 --- /dev/null +++ b/drivers/staging/crystalhd/crystalhd_cmds.c @@ -0,0 +1,1058 @@ +/*************************************************************************** + * Copyright (c) 2005-2009, Broadcom Corporation. + * + * Name: crystalhd_cmds . c + * + * Description: + * BCM70010 Linux driver user command interfaces. + * + * HISTORY: + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#include "crystalhd_cmds.h" +#include "crystalhd_hw.h" + +static struct crystalhd_user *bc_cproc_get_uid(struct crystalhd_cmd *ctx) +{ + struct crystalhd_user *user = NULL; + int i; + + for (i = 0; i < BC_LINK_MAX_OPENS; i++) { + if (!ctx->user[i].in_use) { + user = &ctx->user[i]; + break; + } + } + + return user; +} + +static int bc_cproc_get_user_count(struct crystalhd_cmd *ctx) +{ + int i, count = 0; + + for (i = 0; i < BC_LINK_MAX_OPENS; i++) { + if (ctx->user[i].in_use) + count++; + } + + return count; +} + +static void bc_cproc_mark_pwr_state(struct crystalhd_cmd *ctx) +{ + int i; + + for (i = 0; i < BC_LINK_MAX_OPENS; i++) { + if (!ctx->user[i].in_use) + continue; + if (ctx->user[i].mode == DTS_DIAG_MODE || + ctx->user[i].mode == DTS_PLAYBACK_MODE) { + ctx->pwr_state_change = 1; + break; + } + } +} + +static BC_STATUS bc_cproc_notify_mode(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + int rc = 0, i = 0; + + if (!ctx || !idata) { + BCMLOG_ERR("Invalid Arg!!\n"); + return BC_STS_INV_ARG; + } + + if (ctx->user[idata->u_id].mode != DTS_MODE_INV) { + BCMLOG_ERR("Close the handle first..\n"); + return BC_STS_ERR_USAGE; + } + if (idata->udata.u.NotifyMode.Mode == DTS_MONITOR_MODE) { + ctx->user[idata->u_id].mode = idata->udata.u.NotifyMode.Mode; + return BC_STS_SUCCESS; + } + if (ctx->state != BC_LINK_INVALID) { + BCMLOG_ERR("Link invalid state %d \n", ctx->state); + return BC_STS_ERR_USAGE; + } + /* Check for duplicate playback sessions..*/ + for (i = 0; i < BC_LINK_MAX_OPENS; i++) { + if (ctx->user[i].mode == DTS_DIAG_MODE || + ctx->user[i].mode == DTS_PLAYBACK_MODE) { + BCMLOG_ERR("multiple playback sessions are not " + "supported..\n"); + return BC_STS_ERR_USAGE; + } + } + ctx->cin_wait_exit = 0; + ctx->user[idata->u_id].mode = idata->udata.u.NotifyMode.Mode; + /* Setup mmap pool for uaddr sgl mapping..*/ + rc = crystalhd_create_dio_pool(ctx->adp, BC_LINK_MAX_SGLS); + if (rc) + return BC_STS_ERROR; + + /* Setup Hardware DMA rings */ + return crystalhd_hw_setup_dma_rings(&ctx->hw_ctx); +} + +static BC_STATUS bc_cproc_get_version(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + + if (!ctx || !idata) { + BCMLOG_ERR("Invalid Arg!!\n"); + return BC_STS_INV_ARG; + } + idata->udata.u.VerInfo.DriverMajor = crystalhd_kmod_major; + idata->udata.u.VerInfo.DriverMinor = crystalhd_kmod_minor; + idata->udata.u.VerInfo.DriverRevision = crystalhd_kmod_rev; + return BC_STS_SUCCESS; +} + + +static BC_STATUS bc_cproc_get_hwtype(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) +{ + if (!ctx || !idata) { + BCMLOG_ERR("Invalid Arg!!\n"); + return BC_STS_INV_ARG; + } + + crystalhd_pci_cfg_rd(ctx->adp, 0, 2, + (uint32_t *)&idata->udata.u.hwType.PciVenId); + crystalhd_pci_cfg_rd(ctx->adp, 2, 2, + (uint32_t *)&idata->udata.u.hwType.PciDevId); + crystalhd_pci_cfg_rd(ctx->adp, 8, 1, + (uint32_t *)&idata->udata.u.hwType.HwRev); + + return BC_STS_SUCCESS; +} + +static BC_STATUS bc_cproc_reg_rd(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + if (!ctx || !idata) + return BC_STS_INV_ARG; + idata->udata.u.regAcc.Value = bc_dec_reg_rd(ctx->adp, + idata->udata.u.regAcc.Offset); + return BC_STS_SUCCESS; +} + +static BC_STATUS bc_cproc_reg_wr(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + if (!ctx || !idata) + return BC_STS_INV_ARG; + + bc_dec_reg_wr(ctx->adp, idata->udata.u.regAcc.Offset, + idata->udata.u.regAcc.Value); + + return BC_STS_SUCCESS; +} + +static BC_STATUS bc_cproc_link_reg_rd(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + if (!ctx || !idata) + return BC_STS_INV_ARG; + + idata->udata.u.regAcc.Value = crystalhd_reg_rd(ctx->adp, + idata->udata.u.regAcc.Offset); + return BC_STS_SUCCESS; +} + +static BC_STATUS bc_cproc_link_reg_wr(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + if (!ctx || !idata) + return BC_STS_INV_ARG; + + crystalhd_reg_wr(ctx->adp, idata->udata.u.regAcc.Offset, + idata->udata.u.regAcc.Value); + + return BC_STS_SUCCESS; +} + +static BC_STATUS bc_cproc_mem_rd(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + BC_STATUS sts = BC_STS_SUCCESS; + + if (!ctx || !idata || !idata->add_cdata) + return BC_STS_INV_ARG; + + if (idata->udata.u.devMem.NumDwords > (idata->add_cdata_sz / 4)) { + BCMLOG_ERR("insufficient buffer\n"); + return BC_STS_INV_ARG; + } + sts = crystalhd_mem_rd(ctx->adp, idata->udata.u.devMem.StartOff, + idata->udata.u.devMem.NumDwords, + (uint32_t *)idata->add_cdata); + return sts; + +} + +static BC_STATUS bc_cproc_mem_wr(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + BC_STATUS sts = BC_STS_SUCCESS; + + if (!ctx || !idata || !idata->add_cdata) + return BC_STS_INV_ARG; + + if (idata->udata.u.devMem.NumDwords > (idata->add_cdata_sz / 4)) { + BCMLOG_ERR("insufficient buffer\n"); + return BC_STS_INV_ARG; + } + + sts = crystalhd_mem_wr(ctx->adp, idata->udata.u.devMem.StartOff, + idata->udata.u.devMem.NumDwords, + (uint32_t *)idata->add_cdata); + return sts; +} + +static BC_STATUS bc_cproc_cfg_rd(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + uint32_t ix, cnt, off, len; + BC_STATUS sts = BC_STS_SUCCESS; + uint32_t *temp; + + if (!ctx || !idata) + return BC_STS_INV_ARG; + + temp = (uint32_t *) idata->udata.u.pciCfg.pci_cfg_space; + off = idata->udata.u.pciCfg.Offset; + len = idata->udata.u.pciCfg.Size; + + if (len <= 4) + return crystalhd_pci_cfg_rd(ctx->adp, off, len, temp); + + /* Truncate to dword alignment..*/ + len = 4; + cnt = idata->udata.u.pciCfg.Size / len; + for (ix = 0; ix < cnt; ix++) { + sts = crystalhd_pci_cfg_rd(ctx->adp, off, len, &temp[ix]); + if (sts != BC_STS_SUCCESS) { + BCMLOG_ERR("config read : %d\n", sts); + return sts; + } + off += len; + } + + return sts; +} + +static BC_STATUS bc_cproc_cfg_wr(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + uint32_t ix, cnt, off, len; + BC_STATUS sts = BC_STS_SUCCESS; + uint32_t *temp; + + if (!ctx || !idata) + return BC_STS_INV_ARG; + + temp = (uint32_t *) idata->udata.u.pciCfg.pci_cfg_space; + off = idata->udata.u.pciCfg.Offset; + len = idata->udata.u.pciCfg.Size; + + if (len <= 4) + return crystalhd_pci_cfg_wr(ctx->adp, off, len, temp[0]); + + /* Truncate to dword alignment..*/ + len = 4; + cnt = idata->udata.u.pciCfg.Size / len; + for (ix = 0; ix < cnt; ix++) { + sts = crystalhd_pci_cfg_wr(ctx->adp, off, len, temp[ix]); + if (sts != BC_STS_SUCCESS) { + BCMLOG_ERR("config write : %d\n", sts); + return sts; + } + off += len; + } + + return sts; +} + +static BC_STATUS bc_cproc_download_fw(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + BC_STATUS sts = BC_STS_SUCCESS; + + if (!ctx || !idata || !idata->add_cdata || !idata->add_cdata_sz) { + BCMLOG_ERR("Invalid Arg!!\n"); + return BC_STS_INV_ARG; + } + + if (ctx->state != BC_LINK_INVALID) { + BCMLOG_ERR("Link invalid state %d \n", ctx->state); + return BC_STS_ERR_USAGE; + } + + sts = crystalhd_download_fw(ctx->adp, (uint8_t *)idata->add_cdata, + idata->add_cdata_sz); + + if (sts != BC_STS_SUCCESS) { + BCMLOG_ERR("Firmware Download Failure!! - %d\n", sts); + } else + ctx->state |= BC_LINK_INIT; + + return sts; +} + +/* + * We use the FW_CMD interface to sync up playback state with application + * and firmware. This function will perform the required pre and post + * processing of the Firmware commands. + * + * Pause - + * Disable capture after decoder pause. + * Resume - + * First enable capture and issue decoder resume command. + * Flush - + * Abort pending input transfers and issue decoder flush command. + * + */ +static BC_STATUS bc_cproc_do_fw_cmd(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) +{ + BC_STATUS sts; + uint32_t *cmd; + + if (!(ctx->state & BC_LINK_INIT)) { + BCMLOG_ERR("Link invalid state %d \n", ctx->state); + return BC_STS_ERR_USAGE; + } + + cmd = idata->udata.u.fwCmd.cmd; + + /* Pre-Process */ + if (cmd[0] == eCMD_C011_DEC_CHAN_PAUSE) { + if (!cmd[3]) { + ctx->state &= ~BC_LINK_PAUSED; + crystalhd_hw_unpause(&ctx->hw_ctx); + } + } else if (cmd[0] == eCMD_C011_DEC_CHAN_FLUSH) { + BCMLOG(BCMLOG_INFO, "Flush issued\n"); + if (cmd[3]) + ctx->cin_wait_exit = 1; + } + + sts = crystalhd_do_fw_cmd(&ctx->hw_ctx, &idata->udata.u.fwCmd); + + if (sts != BC_STS_SUCCESS) { + BCMLOG(BCMLOG_INFO, "fw cmd %x failed\n", cmd[0]); + return sts; + } + + /* Post-Process */ + if (cmd[0] == eCMD_C011_DEC_CHAN_PAUSE) { + if (cmd[3]) { + ctx->state |= BC_LINK_PAUSED; + crystalhd_hw_pause(&ctx->hw_ctx); + } + } + + return sts; +} + +static void bc_proc_in_completion(crystalhd_dio_req *dio_hnd, + wait_queue_head_t *event, BC_STATUS sts) +{ + if (!dio_hnd || !event) { + BCMLOG_ERR("Invalid Arg!!\n"); + return; + } + if (sts == BC_STS_IO_USER_ABORT) + return; + + dio_hnd->uinfo.comp_sts = sts; + dio_hnd->uinfo.ev_sts = 1; + crystalhd_set_event(event); +} + +static BC_STATUS bc_cproc_codein_sleep(struct crystalhd_cmd *ctx) +{ + wait_queue_head_t sleep_ev; + int rc = 0; + + if (ctx->state & BC_LINK_SUSPEND) + return BC_STS_IO_USER_ABORT; + + if (ctx->cin_wait_exit) { + ctx->cin_wait_exit = 0; + return BC_STS_CMD_CANCELLED; + } + crystalhd_create_event(&sleep_ev); + crystalhd_wait_on_event(&sleep_ev, 0, 100, rc, 0); + if (rc == -EINTR) + return BC_STS_IO_USER_ABORT; + + return BC_STS_SUCCESS; +} + +static BC_STATUS bc_cproc_hw_txdma(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata, + crystalhd_dio_req *dio) +{ + uint32_t tx_listid = 0; + BC_STATUS sts = BC_STS_SUCCESS; + wait_queue_head_t event; + int rc = 0; + + if (!ctx || !idata || !dio) { + BCMLOG_ERR("Invalid Arg!!\n"); + return BC_STS_INV_ARG; + } + + crystalhd_create_event(&event); + + ctx->tx_list_id = 0; + /* msleep_interruptible(2000); */ + sts = crystalhd_hw_post_tx(&ctx->hw_ctx, dio, bc_proc_in_completion, + &event, &tx_listid, + idata->udata.u.ProcInput.Encrypted); + + while (sts == BC_STS_BUSY) { + sts = bc_cproc_codein_sleep(ctx); + if (sts != BC_STS_SUCCESS) + break; + sts = crystalhd_hw_post_tx(&ctx->hw_ctx, dio, + bc_proc_in_completion, + &event, &tx_listid, + idata->udata.u.ProcInput.Encrypted); + } + if (sts != BC_STS_SUCCESS) { + BCMLOG(BCMLOG_DBG, "_hw_txdma returning sts:%d\n", sts); + return sts; + } + if (ctx->cin_wait_exit) + ctx->cin_wait_exit = 0; + + ctx->tx_list_id = tx_listid; + + /* _post() succeeded.. wait for the completion. */ + crystalhd_wait_on_event(&event, (dio->uinfo.ev_sts), 3000, rc, 0); + ctx->tx_list_id = 0; + if (!rc) { + return dio->uinfo.comp_sts; + } else if (rc == -EBUSY) { + BCMLOG(BCMLOG_DBG, "_tx_post() T/O \n"); + sts = BC_STS_TIMEOUT; + } else if (rc == -EINTR) { + BCMLOG(BCMLOG_DBG, "Tx Wait Signal int.\n"); + sts = BC_STS_IO_USER_ABORT; + } else { + sts = BC_STS_IO_ERROR; + } + + /* We are cancelling the IO from the same context as the _post(). + * so no need to wait on the event again.. the return itself + * ensures the release of our resources. + */ + crystalhd_hw_cancel_tx(&ctx->hw_ctx, tx_listid); + + return sts; +} + +/* Helper function to check on user buffers */ +static BC_STATUS bc_cproc_check_inbuffs(bool pin, void *ubuff, uint32_t ub_sz, + uint32_t uv_off, bool en_422) +{ + if (!ubuff || !ub_sz) { + BCMLOG_ERR("%s->Invalid Arg %p %x\n", + ((pin) ? "TX" : "RX"), ubuff, ub_sz); + return BC_STS_INV_ARG; + } + + /* Check for alignment */ + if (((uintptr_t)ubuff) & 0x03) { + BCMLOG_ERR("%s-->Un-aligned address not implemented yet.. %p \n", + ((pin) ? "TX" : "RX"), ubuff); + return BC_STS_NOT_IMPL; + } + if (pin) + return BC_STS_SUCCESS; + + if (!en_422 && !uv_off) { + BCMLOG_ERR("Need UV offset for 420 mode.\n"); + return BC_STS_INV_ARG; + } + + if (en_422 && uv_off) { + BCMLOG_ERR("UV offset in 422 mode ??\n"); + return BC_STS_INV_ARG; + } + + return BC_STS_SUCCESS; +} + +static BC_STATUS bc_cproc_proc_input(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) +{ + void *ubuff; + uint32_t ub_sz; + crystalhd_dio_req *dio_hnd = NULL; + BC_STATUS sts = BC_STS_SUCCESS; + + if (!ctx || !idata) { + BCMLOG_ERR("Invalid Arg!!\n"); + return BC_STS_INV_ARG; + } + + ubuff = idata->udata.u.ProcInput.pDmaBuff; + ub_sz = idata->udata.u.ProcInput.BuffSz; + + sts = bc_cproc_check_inbuffs(1, ubuff, ub_sz, 0, 0); + if (sts != BC_STS_SUCCESS) + return sts; + + sts = crystalhd_map_dio(ctx->adp, ubuff, ub_sz, 0, 0, 1, &dio_hnd); + if (sts != BC_STS_SUCCESS) { + BCMLOG_ERR("dio map - %d \n", sts); + return sts; + } + + if (!dio_hnd) + return BC_STS_ERROR; + + sts = bc_cproc_hw_txdma(ctx, idata, dio_hnd); + + crystalhd_unmap_dio(ctx->adp, dio_hnd); + + return sts; +} + +static BC_STATUS bc_cproc_add_cap_buff(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + void *ubuff; + uint32_t ub_sz, uv_off; + bool en_422; + crystalhd_dio_req *dio_hnd = NULL; + BC_STATUS sts = BC_STS_SUCCESS; + + if (!ctx || !idata) { + BCMLOG_ERR("Invalid Arg!!\n"); + return BC_STS_INV_ARG; + } + + ubuff = idata->udata.u.RxBuffs.YuvBuff; + ub_sz = idata->udata.u.RxBuffs.YuvBuffSz; + uv_off = idata->udata.u.RxBuffs.UVbuffOffset; + en_422 = idata->udata.u.RxBuffs.b422Mode; + + sts = bc_cproc_check_inbuffs(0, ubuff, ub_sz, uv_off, en_422); + if (sts != BC_STS_SUCCESS) + return sts; + + sts = crystalhd_map_dio(ctx->adp, ubuff, ub_sz, uv_off, + en_422, 0, &dio_hnd); + if (sts != BC_STS_SUCCESS) { + BCMLOG_ERR("dio map - %d \n", sts); + return sts; + } + + if (!dio_hnd) + return BC_STS_ERROR; + + sts = crystalhd_hw_add_cap_buffer(&ctx->hw_ctx, dio_hnd, (ctx->state == BC_LINK_READY)); + if ((sts != BC_STS_SUCCESS) && (sts != BC_STS_BUSY)) { + crystalhd_unmap_dio(ctx->adp, dio_hnd); + return sts; + } + + return BC_STS_SUCCESS; +} + +static BC_STATUS bc_cproc_fmt_change(struct crystalhd_cmd *ctx, + crystalhd_dio_req *dio) +{ + BC_STATUS sts = BC_STS_SUCCESS; + + sts = crystalhd_hw_add_cap_buffer(&ctx->hw_ctx, dio, 0); + if (sts != BC_STS_SUCCESS) + return sts; + + ctx->state |= BC_LINK_FMT_CHG; + if (ctx->state == BC_LINK_READY) + sts = crystalhd_hw_start_capture(&ctx->hw_ctx); + + return sts; +} + +static BC_STATUS bc_cproc_fetch_frame(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + crystalhd_dio_req *dio = NULL; + BC_STATUS sts = BC_STS_SUCCESS; + BC_DEC_OUT_BUFF *frame; + + if (!ctx || !idata) { + BCMLOG_ERR("Invalid Arg!!\n"); + return BC_STS_INV_ARG; + } + + if (!(ctx->state & BC_LINK_CAP_EN)) { + BCMLOG(BCMLOG_DBG, "Capture not enabled..%x\n", ctx->state); + return BC_STS_ERR_USAGE; + } + + frame = &idata->udata.u.DecOutData; + + sts = crystalhd_hw_get_cap_buffer(&ctx->hw_ctx, &frame->PibInfo, &dio); + if (sts != BC_STS_SUCCESS) + return (ctx->state & BC_LINK_SUSPEND) ? BC_STS_IO_USER_ABORT : sts; + + frame->Flags = dio->uinfo.comp_flags; + + if (frame->Flags & COMP_FLAG_FMT_CHANGE) + return bc_cproc_fmt_change(ctx, dio); + + frame->OutPutBuffs.YuvBuff = dio->uinfo.xfr_buff; + frame->OutPutBuffs.YuvBuffSz = dio->uinfo.xfr_len; + frame->OutPutBuffs.UVbuffOffset = dio->uinfo.uv_offset; + frame->OutPutBuffs.b422Mode = dio->uinfo.b422mode; + + frame->OutPutBuffs.YBuffDoneSz = dio->uinfo.y_done_sz; + frame->OutPutBuffs.UVBuffDoneSz = dio->uinfo.uv_done_sz; + + crystalhd_unmap_dio(ctx->adp, dio); + + return BC_STS_SUCCESS; +} + +static BC_STATUS bc_cproc_start_capture(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + ctx->state |= BC_LINK_CAP_EN; + if (ctx->state == BC_LINK_READY) + return crystalhd_hw_start_capture(&ctx->hw_ctx); + + return BC_STS_SUCCESS; +} + +static BC_STATUS bc_cproc_flush_cap_buffs(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + crystalhd_dio_req *dio = NULL; + BC_STATUS sts = BC_STS_SUCCESS; + BC_DEC_OUT_BUFF *frame; + uint32_t count; + + if (!ctx || !idata) { + BCMLOG_ERR("Invalid Arg!!\n"); + return BC_STS_INV_ARG; + } + + if (!(ctx->state & BC_LINK_CAP_EN)) + return BC_STS_ERR_USAGE; + + /* We should ack flush even when we are in paused/suspend state */ + if (!(ctx->state & BC_LINK_READY)) + return crystalhd_hw_stop_capture(&ctx->hw_ctx); + + ctx->state &= ~(BC_LINK_CAP_EN|BC_LINK_FMT_CHG); + + frame = &idata->udata.u.DecOutData; + for (count = 0; count < BC_RX_LIST_CNT; count++) { + + sts = crystalhd_hw_get_cap_buffer(&ctx->hw_ctx, &frame->PibInfo, &dio); + if (sts != BC_STS_SUCCESS) + break; + + crystalhd_unmap_dio(ctx->adp, dio); + } + + return crystalhd_hw_stop_capture(&ctx->hw_ctx); +} + +static BC_STATUS bc_cproc_get_stats(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + BC_DTS_STATS *stats; + struct crystalhd_hw_stats hw_stats; + + if (!ctx || !idata) { + BCMLOG_ERR("Invalid Arg!!\n"); + return BC_STS_INV_ARG; + } + + crystalhd_hw_stats(&ctx->hw_ctx, &hw_stats); + + stats = &idata->udata.u.drvStat; + stats->drvRLL = hw_stats.rdyq_count; + stats->drvFLL = hw_stats.freeq_count; + stats->DrvTotalFrmDropped = hw_stats.rx_errors; + stats->DrvTotalHWErrs = hw_stats.rx_errors + hw_stats.tx_errors; + stats->intCount = hw_stats.num_interrupts; + stats->DrvIgnIntrCnt = hw_stats.num_interrupts - + hw_stats.dev_interrupts; + stats->TxFifoBsyCnt = hw_stats.cin_busy; + stats->pauseCount = hw_stats.pause_cnt; + + if (ctx->pwr_state_change) + stats->pwr_state_change = 1; + if (ctx->state & BC_LINK_PAUSED) + stats->DrvPauseTime = 1; + + return BC_STS_SUCCESS; +} + +static BC_STATUS bc_cproc_reset_stats(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + crystalhd_hw_stats(&ctx->hw_ctx, NULL); + + return BC_STS_SUCCESS; +} + +static BC_STATUS bc_cproc_chg_clk(struct crystalhd_cmd *ctx, + crystalhd_ioctl_data *idata) +{ + BC_CLOCK *clock; + uint32_t oldClk; + BC_STATUS sts = BC_STS_SUCCESS; + + if (!ctx || !idata) { + BCMLOG_ERR("Invalid Arg!!\n"); + return BC_STS_INV_ARG; + } + + clock = &idata->udata.u.clockValue; + oldClk = ctx->hw_ctx.core_clock_mhz; + ctx->hw_ctx.core_clock_mhz = clock->clk; + + if (ctx->state & BC_LINK_READY) { + sts = crystalhd_hw_set_core_clock(&ctx->hw_ctx); + if (sts == BC_STS_CLK_NOCHG) + ctx->hw_ctx.core_clock_mhz = oldClk; + } + + clock->clk = ctx->hw_ctx.core_clock_mhz; + + return sts; +} + +/*=============== Cmd Proc Table.. ======================================*/ +static const crystalhd_cmd_tbl_t g_crystalhd_cproc_tbl[] = { + { BCM_IOC_GET_VERSION, bc_cproc_get_version, 0}, + { BCM_IOC_GET_HWTYPE, bc_cproc_get_hwtype, 0}, + { BCM_IOC_REG_RD, bc_cproc_reg_rd, 0}, + { BCM_IOC_REG_WR, bc_cproc_reg_wr, 0}, + { BCM_IOC_FPGA_RD, bc_cproc_link_reg_rd, 0}, + { BCM_IOC_FPGA_WR, bc_cproc_link_reg_wr, 0}, + { BCM_IOC_MEM_RD, bc_cproc_mem_rd, 0}, + { BCM_IOC_MEM_WR, bc_cproc_mem_wr, 0}, + { BCM_IOC_RD_PCI_CFG, bc_cproc_cfg_rd, 0}, + { BCM_IOC_WR_PCI_CFG, bc_cproc_cfg_wr, 1}, + { BCM_IOC_FW_DOWNLOAD, bc_cproc_download_fw, 1}, + { BCM_IOC_FW_CMD, bc_cproc_do_fw_cmd, 1}, + { BCM_IOC_PROC_INPUT, bc_cproc_proc_input, 1}, + { BCM_IOC_ADD_RXBUFFS, bc_cproc_add_cap_buff, 1}, + { BCM_IOC_FETCH_RXBUFF, bc_cproc_fetch_frame, 1}, + { BCM_IOC_START_RX_CAP, bc_cproc_start_capture, 1}, + { BCM_IOC_FLUSH_RX_CAP, bc_cproc_flush_cap_buffs, 1}, + { BCM_IOC_GET_DRV_STAT, bc_cproc_get_stats, 0}, + { BCM_IOC_RST_DRV_STAT, bc_cproc_reset_stats, 0}, + { BCM_IOC_NOTIFY_MODE, bc_cproc_notify_mode, 0}, + { BCM_IOC_CHG_CLK, bc_cproc_chg_clk, 0}, + { BCM_IOC_END, NULL}, +}; + +/*=============== Cmd Proc Functions.. ===================================*/ + +/** + * crystalhd_suspend - Power management suspend request. + * @ctx: Command layer context. + * @idata: Iodata - required for internal use. + * + * Return: + * status + * + * 1. Set the state to Suspend. + * 2. Flush the Rx Buffers it will unmap all the buffers and + * stop the RxDMA engine. + * 3. Cancel The TX Io and Stop Dma Engine. + * 4. Put the DDR in to deep sleep. + * 5. Stop the hardware putting it in to Reset State. + * + * Current gstreamer frame work does not provide any power management + * related notification to user mode decoder plug-in. As a work-around + * we pass on the power mangement notification to our plug-in by completing + * all outstanding requests with BC_STS_IO_USER_ABORT return code. + */ +BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) +{ + BC_STATUS sts = BC_STS_SUCCESS; + + if (!ctx || !idata) { + BCMLOG_ERR("Invalid Parameters\n"); + return BC_STS_ERROR; + } + + if (ctx->state & BC_LINK_SUSPEND) + return BC_STS_SUCCESS; + + if (ctx->state == BC_LINK_INVALID) { + BCMLOG(BCMLOG_DBG, "Nothing To Do Suspend Success\n"); + return BC_STS_SUCCESS; + } + + ctx->state |= BC_LINK_SUSPEND; + + bc_cproc_mark_pwr_state(ctx); + + if (ctx->state & BC_LINK_CAP_EN) { + sts = bc_cproc_flush_cap_buffs(ctx, idata); + if (sts != BC_STS_SUCCESS) + return sts; + } + + if (ctx->tx_list_id) { + sts = crystalhd_hw_cancel_tx(&ctx->hw_ctx, ctx->tx_list_id); + if (sts != BC_STS_SUCCESS) + return sts; + } + + sts = crystalhd_hw_suspend(&ctx->hw_ctx); + if (sts != BC_STS_SUCCESS) + return sts; + + BCMLOG(BCMLOG_DBG, "BCM70012 suspend success\n"); + + return BC_STS_SUCCESS; +} + +/** + * crystalhd_resume - Resume frame capture. + * @ctx: Command layer contextx. + * + * Return: + * status + * + * + * Resume frame capture. + * + * PM_Resume can't resume the playback state back to pre-suspend state + * because we don't keep video clip related information within driver. + * To get back to the pre-suspend state App will re-open the device and + * start a new playback session from the pre-suspend clip position. + * + */ +BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx) +{ + BCMLOG(BCMLOG_DBG, "crystalhd_resume Success %x\n", ctx->state); + + bc_cproc_mark_pwr_state(ctx); + + return BC_STS_SUCCESS; +} + +/** + * crystalhd_user_open - Create application handle. + * @ctx: Command layer contextx. + * @user_ctx: User ID context. + * + * Return: + * status + * + * Creates an application specific UID and allocates + * application specific resources. HW layer initialization + * is done for the first open request. + */ +BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, + struct crystalhd_user **user_ctx) +{ + struct crystalhd_user *uc; + + if (!ctx || !user_ctx) { + BCMLOG_ERR("Invalid arg..\n"); + return BC_STS_INV_ARG; + } + + uc = bc_cproc_get_uid(ctx); + if (!uc) { + BCMLOG(BCMLOG_INFO, "No free user context...\n"); + return BC_STS_BUSY; + } + + BCMLOG(BCMLOG_INFO, "Opening new user[%x] handle\n", uc->uid); + + crystalhd_hw_open(&ctx->hw_ctx, ctx->adp); + + uc->in_use = 1; + + *user_ctx = uc; + + return BC_STS_SUCCESS; +} + +/** + * crystalhd_user_close - Close application handle. + * @ctx: Command layer contextx. + * @uc: User ID context. + * + * Return: + * status + * + * Closer aplication handle and release app specific + * resources. + */ +BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx, struct crystalhd_user *uc) +{ + uint32_t mode = uc->mode; + + ctx->user[uc->uid].mode = DTS_MODE_INV; + ctx->user[uc->uid].in_use = 0; + ctx->cin_wait_exit = 1; + ctx->pwr_state_change = 0; + + BCMLOG(BCMLOG_INFO, "Closing user[%x] handle\n", uc->uid); + + if ((mode == DTS_DIAG_MODE) || (mode == DTS_PLAYBACK_MODE)) { + crystalhd_hw_free_dma_rings(&ctx->hw_ctx); + crystalhd_destroy_dio_pool(ctx->adp); + } else if (bc_cproc_get_user_count(ctx)) { + return BC_STS_SUCCESS; + } + + crystalhd_hw_close(&ctx->hw_ctx); + + ctx->state = BC_LINK_INVALID; + + return BC_STS_SUCCESS; +} + +/** + * crystalhd_setup_cmd_context - Setup Command layer resources. + * @ctx: Command layer contextx. + * @adp: Adapter context + * + * Return: + * status + * + * Called at the time of driver load. + */ +BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, + struct crystalhd_adp *adp) +{ + int i = 0; + + if (!ctx || !adp) { + BCMLOG_ERR("Invalid arg!!\n"); + return BC_STS_INV_ARG; + } + + if (ctx->adp) + BCMLOG(BCMLOG_DBG, "Resetting Cmd context delete missing..\n"); + + ctx->adp = adp; + for (i = 0; i < BC_LINK_MAX_OPENS; i++) { + ctx->user[i].uid = i; + ctx->user[i].in_use = 0; + ctx->user[i].mode = DTS_MODE_INV; + } + + /*Open and Close the Hardware to put it in to sleep state*/ + crystalhd_hw_open(&ctx->hw_ctx, ctx->adp); + crystalhd_hw_close(&ctx->hw_ctx); + return BC_STS_SUCCESS; +} + +/** + * crystalhd_delete_cmd_context - Release Command layer resources. + * @ctx: Command layer contextx. + * + * Return: + * status + * + * Called at the time of driver un-load. + */ +BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx) +{ + BCMLOG(BCMLOG_DBG, "Deleting Command context..\n"); + + ctx->adp = NULL; + + return BC_STS_SUCCESS; +} + +/** + * crystalhd_get_cmd_proc - Cproc table lookup. + * @ctx: Command layer contextx. + * @cmd: IOCTL command code. + * @uc: User ID context. + * + * Return: + * command proc function pointer + * + * This function checks the process context, application's + * mode of operation and returns the function pointer + * from the cproc table. + */ +crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, uint32_t cmd, + struct crystalhd_user *uc) +{ + crystalhd_cmd_proc cproc = NULL; + unsigned int i, tbl_sz; + + if (!ctx) { + BCMLOG_ERR("Invalid arg.. Cmd[%d]\n", cmd); + return NULL; + } + + if ((cmd != BCM_IOC_GET_DRV_STAT) && (ctx->state & BC_LINK_SUSPEND)) { + BCMLOG_ERR("Invalid State [suspend Set].. Cmd[%d]\n", cmd); + return NULL; + } + + tbl_sz = sizeof(g_crystalhd_cproc_tbl) / sizeof(crystalhd_cmd_tbl_t); + for (i = 0; i < tbl_sz; i++) { + if (g_crystalhd_cproc_tbl[i].cmd_id == cmd) { + if ((uc->mode == DTS_MONITOR_MODE) && + (g_crystalhd_cproc_tbl[i].block_mon)) { + BCMLOG(BCMLOG_INFO, "Blocking cmd %d \n", cmd); + break; + } + cproc = g_crystalhd_cproc_tbl[i].cmd_proc; + break; + } + } + + return cproc; +} + +/** + * crystalhd_cmd_interrupt - ISR entry point + * @ctx: Command layer contextx. + * + * Return: + * TRUE: If interrupt from bcm70012 device. + * + * + * ISR entry point from OS layer. + */ +bool crystalhd_cmd_interrupt(struct crystalhd_cmd *ctx) +{ + if (!ctx) { + BCMLOG_ERR("Invalid arg..\n"); + return 0; + } + + return crystalhd_hw_interrupt(ctx->adp, &ctx->hw_ctx); +} diff --git a/drivers/staging/crystalhd/crystalhd_cmds.h b/drivers/staging/crystalhd/crystalhd_cmds.h new file mode 100644 index 000000000000..6b290aed8e0b --- /dev/null +++ b/drivers/staging/crystalhd/crystalhd_cmds.h @@ -0,0 +1,88 @@ +/*************************************************************************** + * Copyright (c) 2005-2009, Broadcom Corporation. + * + * Name: crystalhd_cmds . h + * + * Description: + * BCM70010 Linux driver user command interfaces. + * + * HISTORY: + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#ifndef _CRYSTALHD_CMDS_H_ +#define _CRYSTALHD_CMDS_H_ + +/* + * NOTE:: This is the main interface file between the Linux layer + * and the harware layer. This file will use the definitions + * from _dts_glob and dts_defs etc.. which are defined for + * windows. + */ +#include "crystalhd_misc.h" +#include "crystalhd_hw.h" + +enum _crystalhd_state{ + BC_LINK_INVALID = 0x00, + BC_LINK_INIT = 0x01, + BC_LINK_CAP_EN = 0x02, + BC_LINK_FMT_CHG = 0x04, + BC_LINK_SUSPEND = 0x10, + BC_LINK_PAUSED = 0x20, + BC_LINK_READY = (BC_LINK_INIT | BC_LINK_CAP_EN | BC_LINK_FMT_CHG), +}; + +struct crystalhd_user { + uint32_t uid; + uint32_t in_use; + uint32_t mode; +}; + +#define DTS_MODE_INV (-1) + +struct crystalhd_cmd { + uint32_t state; + struct crystalhd_adp *adp; + struct crystalhd_user user[BC_LINK_MAX_OPENS]; + + spinlock_t ctx_lock; + uint32_t tx_list_id; + uint32_t cin_wait_exit; + uint32_t pwr_state_change; + struct crystalhd_hw hw_ctx; +}; + +typedef BC_STATUS (*crystalhd_cmd_proc)(struct crystalhd_cmd *, crystalhd_ioctl_data *); + +typedef struct _crystalhd_cmd_tbl { + uint32_t cmd_id; + const crystalhd_cmd_proc cmd_proc; + uint32_t block_mon; +} crystalhd_cmd_tbl_t; + + +BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata); +BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx); +crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, uint32_t cmd, + struct crystalhd_user *uc); +BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, struct crystalhd_user **user_ctx); +BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx, struct crystalhd_user *uc); +BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, struct crystalhd_adp *adp); +BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx); +bool crystalhd_cmd_interrupt(struct crystalhd_cmd *ctx); + +#endif diff --git a/drivers/staging/crystalhd/crystalhd_fw_if.h b/drivers/staging/crystalhd/crystalhd_fw_if.h new file mode 100644 index 000000000000..261cd19a0ee7 --- /dev/null +++ b/drivers/staging/crystalhd/crystalhd_fw_if.h @@ -0,0 +1,369 @@ +/*************************************************************************** + * Copyright (c) 2005-2009, Broadcom Corporation. + * + * Name: crystalhd_fw_if . h + * + * Description: + * BCM70012 Firmware interface definitions. + * + * HISTORY: + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#ifndef _CRYSTALHD_FW_IF_H_ +#define _CRYSTALHD_FW_IF_H_ + +/* TBD: Pull in only required defs into this file.. */ + + + +/* User Data Header */ +typedef struct user_data { + struct user_data *next; + uint32_t type; + uint32_t size; +} UD_HDR; + + + +/*------------------------------------------------------* + * MPEG Extension to the PPB * + *------------------------------------------------------*/ +typedef struct { + uint32_t to_be_defined; + uint32_t valid; + + /* Always valid, defaults to picture size if no + sequence display extension in the stream. */ + uint32_t display_horizontal_size; + uint32_t display_vertical_size; + + /* MPEG_VALID_PANSCAN + Offsets are a copy values from the MPEG stream. */ + uint32_t offset_count; + int32_t horizontal_offset[3]; + int32_t vertical_offset[3]; + + /* MPEG_VALID_USERDATA + User data is in the form of a linked list. */ + int32_t userDataSize; + UD_HDR *userData; + +} PPB_MPEG; + + +/*------------------------------------------------------* + * VC1 Extension to the PPB * + *------------------------------------------------------*/ +typedef struct { + uint32_t to_be_defined; + uint32_t valid; + + /* Always valid, defaults to picture size if no + sequence display extension in the stream. */ + uint32_t display_horizontal_size; + uint32_t display_vertical_size; + + /* VC1 pan scan windows */ + uint32_t num_panscan_windows; + int32_t ps_horiz_offset[4]; + int32_t ps_vert_offset[4]; + int32_t ps_width[4]; + int32_t ps_height[4]; + + /* VC1_VALID_USERDATA + User data is in the form of a linked list. */ + int32_t userDataSize; + UD_HDR *userData; + +} PPB_VC1; + +/*------------------------------------------------------* + * H.264 Extension to the PPB * + *------------------------------------------------------*/ + +/** + * @brief Film grain SEI message. + * + * Content of the film grain SEI message. + */ + +/* maximum number of model-values as for Thomson spec(standard says 5) */ +#define MAX_FGT_MODEL_VALUE (3) + +/* maximum number of intervals(as many as 256 intervals?) */ +#define MAX_FGT_VALUE_INTERVAL (256) + +typedef struct FGT_SEI { + struct FGT_SEI *next; + unsigned char model_values[3][MAX_FGT_VALUE_INTERVAL][MAX_FGT_MODEL_VALUE]; + unsigned char upper_bound[3][MAX_FGT_VALUE_INTERVAL]; + unsigned char lower_bound[3][MAX_FGT_VALUE_INTERVAL]; + + unsigned char cancel_flag; /* Cancel flag: 1 no film grain. */ + unsigned char model_id; /* Model id. */ + + /* +unused SE based on Thomson spec */ + unsigned char color_desc_flag; /* Separate color descrition flag. */ + unsigned char bit_depth_luma; /* Bit depth luma minus 8. */ + unsigned char bit_depth_chroma; /* Bit depth chroma minus 8. */ + unsigned char full_range_flag; /* Full range flag. */ + unsigned char color_primaries; /* Color primaries. */ + unsigned char transfer_charact; /* Transfer characteristics. */ + unsigned char matrix_coeff; /*< Matrix coefficients. */ + /* -unused SE based on Thomson spec */ + + unsigned char blending_mode_id; /* Blending mode. */ + unsigned char log2_scale_factor; /* Log2 scale factor (2-7). */ + unsigned char comp_flag[3]; /* Components [0,2] parameters present flag. */ + unsigned char num_intervals_minus1[3]; /* Number of intensity level intervals. */ + unsigned char num_model_values[3]; /* Number of model values. */ + uint16_t repetition_period; /* Repetition period (0-16384) */ + +} FGT_SEI; + +typedef struct { + /* 'valid' specifies which fields (or sets of + * fields) below are valid. If the corresponding + * bit in 'valid' is NOT set then that field(s) + * is (are) not initialized. */ + uint32_t valid; + + int32_t poc_top; /* POC for Top Field/Frame */ + int32_t poc_bottom; /* POC for Bottom Field */ + uint32_t idr_pic_id; + + /* H264_VALID_PANSCAN */ + uint32_t pan_scan_count; + int32_t pan_scan_left[3]; + int32_t pan_scan_right[3]; + int32_t pan_scan_top[3]; + int32_t pan_scan_bottom[3]; + + /* H264_VALID_CT_TYPE */ + uint32_t ct_type_count; + uint32_t ct_type[3]; + + /* H264_VALID_SPS_CROP */ + int32_t sps_crop_left; + int32_t sps_crop_right; + int32_t sps_crop_top; + int32_t sps_crop_bottom; + + /* H264_VALID_VUI */ + uint32_t chroma_top; + uint32_t chroma_bottom; + + /* H264_VALID_USER */ + uint32_t user_data_size; + UD_HDR *user_data; + + /* H264 VALID FGT */ + FGT_SEI *pfgt; + +} PPB_H264; + +typedef struct { + /* Common fields. */ + uint32_t picture_number; /* Ordinal display number */ + uint32_t video_buffer; /* Video (picbuf) number */ + uint32_t video_address; /* Address of picbuf Y */ + uint32_t video_address_uv; /* Address of picbuf UV */ + uint32_t video_stripe; /* Picbuf stripe */ + uint32_t video_width; /* Picbuf width */ + uint32_t video_height; /* Picbuf height */ + + uint32_t channel_id; /* Decoder channel ID */ + uint32_t status; /* reserved */ + uint32_t width; /* pixels */ + uint32_t height; /* pixels */ + uint32_t chroma_format; /* see above */ + uint32_t pulldown; /* see above */ + uint32_t flags; /* see above */ + uint32_t pts; /* 32 LSBs of PTS */ + uint32_t protocol; /* protocolXXX (above) */ + + uint32_t frame_rate; /* see above */ + uint32_t matrix_coeff; /* see above */ + uint32_t aspect_ratio; /* see above */ + uint32_t colour_primaries; /* see above */ + uint32_t transfer_char; /* see above */ + uint32_t pcr_offset; /* 45kHz if PCR type; else 27MHz */ + uint32_t n_drop; /* Number of pictures to be dropped */ + + uint32_t custom_aspect_ratio_width_height; + /* upper 16-bits is Y and lower 16-bits is X */ + + uint32_t picture_tag; /* Indexing tag from BUD packets */ + uint32_t picture_done_payload; + uint32_t picture_meta_payload; + uint32_t reserved[1]; + + /* Protocol-specific extensions. */ + union { + PPB_H264 h264; + PPB_MPEG mpeg; + PPB_VC1 vc1; + } other; + +} PPB; + +typedef struct { + uint32_t bFormatChange; + uint32_t resolution; + uint32_t channelId; + uint32_t ppbPtr; + int32_t ptsStcOffset; + uint32_t zeroPanscanValid; + uint32_t dramOutBufAddr; + uint32_t yComponent; + PPB ppb; + +} C011_PIB; + + + +typedef struct { + uint32_t command; + uint32_t sequence; + uint32_t status; + uint32_t picBuf; + uint32_t picRelBuf; + uint32_t picInfoDeliveryQ; + uint32_t picInfoReleaseQ; + uint32_t channelStatus; + uint32_t userDataDeliveryQ; + uint32_t userDataReleaseQ; + uint32_t transportStreamCaptureAddr; + uint32_t asyncEventQ; + +} DecRspChannelStartVideo; + +#define eCMD_C011_CMD_BASE (0x73763000) + +/* host commands */ +typedef enum { + eCMD_TS_GET_NEXT_PIC = 0x7376F100, /* debug get next picture */ + eCMD_TS_GET_LAST_PIC = 0x7376F102, /* debug get last pic status */ + eCMD_TS_READ_WRITE_MEM = 0x7376F104, /* debug read write memory */ + + /* New API commands */ + /* General commands */ + eCMD_C011_INIT = eCMD_C011_CMD_BASE + 0x01, + eCMD_C011_RESET = eCMD_C011_CMD_BASE + 0x02, + eCMD_C011_SELF_TEST = eCMD_C011_CMD_BASE + 0x03, + eCMD_C011_GET_VERSION = eCMD_C011_CMD_BASE + 0x04, + eCMD_C011_GPIO = eCMD_C011_CMD_BASE + 0x05, + eCMD_C011_DEBUG_SETUP = eCMD_C011_CMD_BASE + 0x06, + + /* Decoding commands */ + eCMD_C011_DEC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x100, + eCMD_C011_DEC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x101, + eCMD_C011_DEC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x102, + eCMD_C011_DEC_CHAN_STATUS = eCMD_C011_CMD_BASE + 0x103, + eCMD_C011_DEC_CHAN_FLUSH = eCMD_C011_CMD_BASE + 0x104, + eCMD_C011_DEC_CHAN_TRICK_PLAY = eCMD_C011_CMD_BASE + 0x105, + eCMD_C011_DEC_CHAN_TS_PIDS = eCMD_C011_CMD_BASE + 0x106, + eCMD_C011_DEC_CHAN_PS_STREAM_ID = eCMD_C011_CMD_BASE + 0x107, + eCMD_C011_DEC_CHAN_INPUT_PARAMS = eCMD_C011_CMD_BASE + 0x108, + eCMD_C011_DEC_CHAN_VIDEO_OUTPUT = eCMD_C011_CMD_BASE + 0x109, + eCMD_C011_DEC_CHAN_OUTPUT_FORMAT = eCMD_C011_CMD_BASE + 0x10A, + eCMD_C011_DEC_CHAN_SCALING_FILTERS = eCMD_C011_CMD_BASE + 0x10B, + eCMD_C011_DEC_CHAN_OSD_MODE = eCMD_C011_CMD_BASE + 0x10D, + eCMD_C011_DEC_CHAN_DROP = eCMD_C011_CMD_BASE + 0x10E, + eCMD_C011_DEC_CHAN_RELEASE = eCMD_C011_CMD_BASE + 0x10F, + eCMD_C011_DEC_CHAN_STREAM_SETTINGS = eCMD_C011_CMD_BASE + 0x110, + eCMD_C011_DEC_CHAN_PAUSE_OUTPUT = eCMD_C011_CMD_BASE + 0x111, + eCMD_C011_DEC_CHAN_CHANGE = eCMD_C011_CMD_BASE + 0x112, + eCMD_C011_DEC_CHAN_SET_STC = eCMD_C011_CMD_BASE + 0x113, + eCMD_C011_DEC_CHAN_SET_PTS = eCMD_C011_CMD_BASE + 0x114, + eCMD_C011_DEC_CHAN_CC_MODE = eCMD_C011_CMD_BASE + 0x115, + eCMD_C011_DEC_CREATE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x116, + eCMD_C011_DEC_COPY_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x117, + eCMD_C011_DEC_DELETE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x118, + eCMD_C011_DEC_CHAN_SET_DECYPTION = eCMD_C011_CMD_BASE + 0x119, + eCMD_C011_DEC_CHAN_START_VIDEO = eCMD_C011_CMD_BASE + 0x11A, + eCMD_C011_DEC_CHAN_STOP_VIDEO = eCMD_C011_CMD_BASE + 0x11B, + eCMD_C011_DEC_CHAN_PIC_CAPTURE = eCMD_C011_CMD_BASE + 0x11C, + eCMD_C011_DEC_CHAN_PAUSE = eCMD_C011_CMD_BASE + 0x11D, + eCMD_C011_DEC_CHAN_PAUSE_STATE = eCMD_C011_CMD_BASE + 0x11E, + eCMD_C011_DEC_CHAN_SET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x11F, + eCMD_C011_DEC_CHAN_GET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x120, + eCMD_C011_DEC_CHAN_SET_FF_RATE = eCMD_C011_CMD_BASE + 0x121, + eCMD_C011_DEC_CHAN_GET_FF_RATE = eCMD_C011_CMD_BASE + 0x122, + eCMD_C011_DEC_CHAN_FRAME_ADVANCE = eCMD_C011_CMD_BASE + 0x123, + eCMD_C011_DEC_CHAN_SET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x124, + eCMD_C011_DEC_CHAN_GET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x125, + eCMD_C011_DEC_CHAN_FILL_PIC_BUF = eCMD_C011_CMD_BASE + 0x126, + eCMD_C011_DEC_CHAN_SET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x127, + eCMD_C011_DEC_CHAN_GET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x128, + eCMD_C011_DEC_CHAN_SET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x129, + eCMD_C011_DEC_CHAN_GET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x12A, + eCMD_C011_DEC_CHAN_REVERSE_FIELD_STATUS = eCMD_C011_CMD_BASE + 0x12B, + eCMD_C011_DEC_CHAN_I_PICTURE_FOUND = eCMD_C011_CMD_BASE + 0x12C, + eCMD_C011_DEC_CHAN_SET_PARAMETER = eCMD_C011_CMD_BASE + 0x12D, + eCMD_C011_DEC_CHAN_SET_USER_DATA_MODE = eCMD_C011_CMD_BASE + 0x12E, + eCMD_C011_DEC_CHAN_SET_PAUSE_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x12F, + eCMD_C011_DEC_CHAN_SET_SLOW_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x130, + eCMD_C011_DEC_CHAN_SET_FF_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x131, + eCMD_C011_DEC_CHAN_SET_DISPLAY_TIMING_MODE = eCMD_C011_CMD_BASE + 0x132, + eCMD_C011_DEC_CHAN_SET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x133, + eCMD_C011_DEC_CHAN_GET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x134, + eCMD_C011_DEC_CHAN_SET_REVERSE_FIELD = eCMD_C011_CMD_BASE + 0x135, + eCMD_C011_DEC_CHAN_STREAM_OPEN = eCMD_C011_CMD_BASE + 0x136, + eCMD_C011_DEC_CHAN_SET_PCR_PID = eCMD_C011_CMD_BASE + 0x137, + eCMD_C011_DEC_CHAN_SET_VID_PID = eCMD_C011_CMD_BASE + 0x138, + eCMD_C011_DEC_CHAN_SET_PAN_SCAN_MODE = eCMD_C011_CMD_BASE + 0x139, + eCMD_C011_DEC_CHAN_START_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x140, + eCMD_C011_DEC_CHAN_STOP_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x141, + eCMD_C011_DEC_CHAN_SET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x142, + eCMD_C011_DEC_CHAN_GET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x143, + eCMD_C011_DEC_CHAN_SET_HOST_TRICK_MODE = eCMD_C011_CMD_BASE + 0x144, + eCMD_C011_DEC_CHAN_SET_OPERATION_MODE = eCMD_C011_CMD_BASE + 0x145, + eCMD_C011_DEC_CHAN_DISPLAY_PAUSE_UNTO_PTS = eCMD_C011_CMD_BASE + 0x146, + eCMD_C011_DEC_CHAN_SET_PTS_STC_DIFF_THRESHOLD = eCMD_C011_CMD_BASE + 0x147, + eCMD_C011_DEC_CHAN_SEND_COMPRESSED_BUF = eCMD_C011_CMD_BASE + 0x148, + eCMD_C011_DEC_CHAN_SET_CLIPPING = eCMD_C011_CMD_BASE + 0x149, + eCMD_C011_DEC_CHAN_SET_PARAMETERS_FOR_HARD_RESET_INTERRUPT_TO_HOST + = eCMD_C011_CMD_BASE + 0x150, + + /* Decoder RevD commands */ + eCMD_C011_DEC_CHAN_SET_CSC = eCMD_C011_CMD_BASE + 0x180, /* color space conversion */ + eCMD_C011_DEC_CHAN_SET_RANGE_REMAP = eCMD_C011_CMD_BASE + 0x181, + eCMD_C011_DEC_CHAN_SET_FGT = eCMD_C011_CMD_BASE + 0x182, + /* Note: 0x183 not implemented yet in Rev D main */ + eCMD_C011_DEC_CHAN_SET_LASTPICTURE_PADDING = eCMD_C011_CMD_BASE + 0x183, + + /* Decoder 7412 commands (7412-only) */ + eCMD_C011_DEC_CHAN_SET_CONTENT_KEY = eCMD_C011_CMD_BASE + 0x190, + eCMD_C011_DEC_CHAN_SET_SESSION_KEY = eCMD_C011_CMD_BASE + 0x191, + eCMD_C011_DEC_CHAN_FMT_CHANGE_ACK = eCMD_C011_CMD_BASE + 0x192, + + eCMD_C011_DEC_CHAN_CUSTOM_VIDOUT = eCMD_C011_CMD_BASE + 0x1FF, + + /* Encoding commands */ + eCMD_C011_ENC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x200, + eCMD_C011_ENC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x201, + eCMD_C011_ENC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x202, + eCMD_C011_ENC_CHAN_CONTROL = eCMD_C011_CMD_BASE + 0x203, + eCMD_C011_ENC_CHAN_STATISTICS = eCMD_C011_CMD_BASE + 0x204, + + eNOTIFY_C011_ENC_CHAN_EVENT = eCMD_C011_CMD_BASE + 0x210, + +} eC011_TS_CMD; + +#endif diff --git a/drivers/staging/crystalhd/crystalhd_hw.c b/drivers/staging/crystalhd/crystalhd_hw.c new file mode 100644 index 000000000000..01819d34201a --- /dev/null +++ b/drivers/staging/crystalhd/crystalhd_hw.c @@ -0,0 +1,2395 @@ +/*************************************************************************** + * Copyright (c) 2005-2009, Broadcom Corporation. + * + * Name: crystalhd_hw . c + * + * Description: + * BCM70010 Linux driver HW layer. + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#include +#include +#include "crystalhd_hw.h" + +/* Functions internal to this file */ + +static void crystalhd_enable_uarts(struct crystalhd_adp *adp) +{ + bc_dec_reg_wr(adp, UartSelectA, BSVS_UART_STREAM); + bc_dec_reg_wr(adp, UartSelectB, BSVS_UART_DEC_OUTER); +} + + +static void crystalhd_start_dram(struct crystalhd_adp *adp) +{ + bc_dec_reg_wr(adp, SDRAM_PARAM, ((40 / 5 - 1) << 0) | + /* tras (40ns tras)/(5ns period) -1 ((15/5 - 1) << 4) | // trcd */ + ((15 / 5 - 1) << 7) | /* trp */ + ((10 / 5 - 1) << 10) | /* trrd */ + ((15 / 5 + 1) << 12) | /* twr */ + ((2 + 1) << 16) | /* twtr */ + ((70 / 5 - 2) << 19) | /* trfc */ + (0 << 23)); + + bc_dec_reg_wr(adp, SDRAM_PRECHARGE, 0); + bc_dec_reg_wr(adp, SDRAM_EXT_MODE, 2); + bc_dec_reg_wr(adp, SDRAM_MODE, 0x132); + bc_dec_reg_wr(adp, SDRAM_PRECHARGE, 0); + bc_dec_reg_wr(adp, SDRAM_REFRESH, 0); + bc_dec_reg_wr(adp, SDRAM_REFRESH, 0); + bc_dec_reg_wr(adp, SDRAM_MODE, 0x32); + /* setting the refresh rate here */ + bc_dec_reg_wr(adp, SDRAM_REF_PARAM, ((1 << 12) | 96)); +} + + +static bool crystalhd_bring_out_of_rst(struct crystalhd_adp *adp) +{ + link_misc_perst_deco_ctrl rst_deco_cntrl; + link_misc_perst_clk_ctrl rst_clk_cntrl; + uint32_t temp; + + /* + * Link clocks: MISC_PERST_CLOCK_CTRL Clear PLL power down bit, + * delay to allow PLL to lock Clear alternate clock, stop clock bits + */ + rst_clk_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_CLOCK_CTRL); + rst_clk_cntrl.pll_pwr_dn = 0; + crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); + msleep_interruptible(50); + + rst_clk_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_CLOCK_CTRL); + rst_clk_cntrl.stop_core_clk = 0; + rst_clk_cntrl.sel_alt_clk = 0; + + crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); + msleep_interruptible(50); + + /* + * Bus Arbiter Timeout: GISB_ARBITER_TIMER + * Set internal bus arbiter timeout to 40us based on core clock speed + * (63MHz * 40us = 0x9D8) + */ + crystalhd_reg_wr(adp, GISB_ARBITER_TIMER, 0x9D8); + + /* + * Decoder clocks: MISC_PERST_DECODER_CTRL + * Enable clocks while 7412 reset is asserted, delay + * De-assert 7412 reset + */ + rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_DECODER_CTRL); + rst_deco_cntrl.stop_bcm_7412_clk = 0; + rst_deco_cntrl.bcm7412_rst = 1; + crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); + msleep_interruptible(10); + + rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_DECODER_CTRL); + rst_deco_cntrl.bcm7412_rst = 0; + crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); + msleep_interruptible(50); + + /* Disable OTP_CONTENT_MISC to 0 to disable all secure modes */ + crystalhd_reg_wr(adp, OTP_CONTENT_MISC, 0); + + /* Clear bit 29 of 0x404 */ + temp = crystalhd_reg_rd(adp, PCIE_TL_TRANSACTION_CONFIGURATION); + temp &= ~BC_BIT(29); + crystalhd_reg_wr(adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp); + + /* 2.5V regulator must be set to 2.6 volts (+6%) */ + /* FIXME: jarod: what's the point of this reg read? */ + temp = crystalhd_reg_rd(adp, MISC_PERST_VREG_CTRL); + crystalhd_reg_wr(adp, MISC_PERST_VREG_CTRL, 0xF3); + + return true; +} + +static bool crystalhd_put_in_reset(struct crystalhd_adp *adp) +{ + link_misc_perst_deco_ctrl rst_deco_cntrl; + link_misc_perst_clk_ctrl rst_clk_cntrl; + uint32_t temp; + + /* + * Decoder clocks: MISC_PERST_DECODER_CTRL + * Assert 7412 reset, delay + * Assert 7412 stop clock + */ + rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_DECODER_CTRL); + rst_deco_cntrl.stop_bcm_7412_clk = 1; + crystalhd_reg_wr(adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); + msleep_interruptible(50); + + /* Bus Arbiter Timeout: GISB_ARBITER_TIMER + * Set internal bus arbiter timeout to 40us based on core clock speed + * (6.75MHZ * 40us = 0x10E) + */ + crystalhd_reg_wr(adp, GISB_ARBITER_TIMER, 0x10E); + + /* Link clocks: MISC_PERST_CLOCK_CTRL + * Stop core clk, delay + * Set alternate clk, delay, set PLL power down + */ + rst_clk_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_CLOCK_CTRL); + rst_clk_cntrl.stop_core_clk = 1; + rst_clk_cntrl.sel_alt_clk = 1; + crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); + msleep_interruptible(50); + + rst_clk_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC_PERST_CLOCK_CTRL); + rst_clk_cntrl.pll_pwr_dn = 1; + crystalhd_reg_wr(adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); + + /* + * Read and restore the Transaction Configuration Register + * after core reset + */ + temp = crystalhd_reg_rd(adp, PCIE_TL_TRANSACTION_CONFIGURATION); + + /* + * Link core soft reset: MISC3_RESET_CTRL + * - Write BIT[0]=1 and read it back for core reset to take place + */ + crystalhd_reg_wr(adp, MISC3_RESET_CTRL, 1); + rst_deco_cntrl.whole_reg = crystalhd_reg_rd(adp, MISC3_RESET_CTRL); + msleep_interruptible(50); + + /* restore the transaction configuration register */ + crystalhd_reg_wr(adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp); + + return true; +} + +static void crystalhd_disable_interrupts(struct crystalhd_adp *adp) +{ + intr_mask_reg intr_mask; + intr_mask.whole_reg = crystalhd_reg_rd(adp, INTR_INTR_MSK_STS_REG); + intr_mask.mask_pcie_err = 1; + intr_mask.mask_pcie_rbusmast_err = 1; + intr_mask.mask_pcie_rgr_bridge = 1; + intr_mask.mask_rx_done = 1; + intr_mask.mask_rx_err = 1; + intr_mask.mask_tx_done = 1; + intr_mask.mask_tx_err = 1; + crystalhd_reg_wr(adp, INTR_INTR_MSK_SET_REG, intr_mask.whole_reg); + + return; +} + +static void crystalhd_enable_interrupts(struct crystalhd_adp *adp) +{ + intr_mask_reg intr_mask; + intr_mask.whole_reg = crystalhd_reg_rd(adp, INTR_INTR_MSK_STS_REG); + intr_mask.mask_pcie_err = 1; + intr_mask.mask_pcie_rbusmast_err = 1; + intr_mask.mask_pcie_rgr_bridge = 1; + intr_mask.mask_rx_done = 1; + intr_mask.mask_rx_err = 1; + intr_mask.mask_tx_done = 1; + intr_mask.mask_tx_err = 1; + crystalhd_reg_wr(adp, INTR_INTR_MSK_CLR_REG, intr_mask.whole_reg); + + return; +} + +static void crystalhd_clear_errors(struct crystalhd_adp *adp) +{ + uint32_t reg; + + /* FIXME: jarod: wouldn't we want to write a 0 to the reg? Or does the write clear the bits specified? */ + reg = crystalhd_reg_rd(adp, MISC1_Y_RX_ERROR_STATUS); + if (reg) + crystalhd_reg_wr(adp, MISC1_Y_RX_ERROR_STATUS, reg); + + reg = crystalhd_reg_rd(adp, MISC1_UV_RX_ERROR_STATUS); + if (reg) + crystalhd_reg_wr(adp, MISC1_UV_RX_ERROR_STATUS, reg); + + reg = crystalhd_reg_rd(adp, MISC1_TX_DMA_ERROR_STATUS); + if (reg) + crystalhd_reg_wr(adp, MISC1_TX_DMA_ERROR_STATUS, reg); +} + +static void crystalhd_clear_interrupts(struct crystalhd_adp *adp) +{ + uint32_t intr_sts = crystalhd_reg_rd(adp, INTR_INTR_STATUS); + + if (intr_sts) { + crystalhd_reg_wr(adp, INTR_INTR_CLR_REG, intr_sts); + + /* Write End Of Interrupt for PCIE */ + crystalhd_reg_wr(adp, INTR_EOI_CTRL, 1); + } +} + +static void crystalhd_soft_rst(struct crystalhd_adp *adp) +{ + uint32_t val; + + /* Assert c011 soft reset*/ + bc_dec_reg_wr(adp, DecHt_HostSwReset, 0x00000001); + msleep_interruptible(50); + + /* Release c011 soft reset*/ + bc_dec_reg_wr(adp, DecHt_HostSwReset, 0x00000000); + + /* Disable Stuffing..*/ + val = crystalhd_reg_rd(adp, MISC2_GLOBAL_CTRL); + val |= BC_BIT(8); + crystalhd_reg_wr(adp, MISC2_GLOBAL_CTRL, val); +} + +static bool crystalhd_load_firmware_config(struct crystalhd_adp *adp) +{ + uint32_t i = 0, reg; + + crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (BC_DRAM_FW_CFG_ADDR >> 19)); + + crystalhd_reg_wr(adp, AES_CMD, 0); + crystalhd_reg_wr(adp, AES_CONFIG_INFO, (BC_DRAM_FW_CFG_ADDR & 0x7FFFF)); + crystalhd_reg_wr(adp, AES_CMD, 0x1); + + /* FIXME: jarod: I've seen this fail, and introducing extra delays helps... */ + for (i = 0; i < 100; ++i) { + reg = crystalhd_reg_rd(adp, AES_STATUS); + if (reg & 0x1) + return true; + msleep_interruptible(10); + } + + return false; +} + + +static bool crystalhd_start_device(struct crystalhd_adp *adp) +{ + uint32_t dbg_options, glb_cntrl = 0, reg_pwrmgmt = 0; + + BCMLOG(BCMLOG_INFO, "Starting BCM70012 Device\n"); + + reg_pwrmgmt = crystalhd_reg_rd(adp, PCIE_DLL_DATA_LINK_CONTROL); + reg_pwrmgmt &= ~ASPM_L1_ENABLE; + + crystalhd_reg_wr(adp, PCIE_DLL_DATA_LINK_CONTROL, reg_pwrmgmt); + + if (!crystalhd_bring_out_of_rst(adp)) { + BCMLOG_ERR("Failed To Bring Link Out Of Reset\n"); + return false; + } + + crystalhd_disable_interrupts(adp); + + crystalhd_clear_errors(adp); + + crystalhd_clear_interrupts(adp); + + crystalhd_enable_interrupts(adp); + + /* Enable the option for getting the total no. of DWORDS + * that have been transfered by the RXDMA engine + */ + dbg_options = crystalhd_reg_rd(adp, MISC1_DMA_DEBUG_OPTIONS_REG); + dbg_options |= 0x10; + crystalhd_reg_wr(adp, MISC1_DMA_DEBUG_OPTIONS_REG, dbg_options); + + /* Enable PCI Global Control options */ + glb_cntrl = crystalhd_reg_rd(adp, MISC2_GLOBAL_CTRL); + glb_cntrl |= 0x100; + glb_cntrl |= 0x8000; + crystalhd_reg_wr(adp, MISC2_GLOBAL_CTRL, glb_cntrl); + + crystalhd_enable_interrupts(adp); + + crystalhd_soft_rst(adp); + crystalhd_start_dram(adp); + crystalhd_enable_uarts(adp); + + return true; +} + +static bool crystalhd_stop_device(struct crystalhd_adp *adp) +{ + uint32_t reg; + + BCMLOG(BCMLOG_INFO, "Stopping BCM70012 Device\n"); + /* Clear and disable interrupts */ + crystalhd_disable_interrupts(adp); + crystalhd_clear_errors(adp); + crystalhd_clear_interrupts(adp); + + if (!crystalhd_put_in_reset(adp)) + BCMLOG_ERR("Failed to Put Link To Reset State\n"); + + reg = crystalhd_reg_rd(adp, PCIE_DLL_DATA_LINK_CONTROL); + reg |= ASPM_L1_ENABLE; + crystalhd_reg_wr(adp, PCIE_DLL_DATA_LINK_CONTROL, reg); + + /* Set PCI Clk Req */ + reg = crystalhd_reg_rd(adp, PCIE_CLK_REQ_REG); + reg |= PCI_CLK_REQ_ENABLE; + crystalhd_reg_wr(adp, PCIE_CLK_REQ_REG, reg); + + return true; +} + +static crystalhd_rx_dma_pkt *crystalhd_hw_alloc_rx_pkt(struct crystalhd_hw *hw) +{ + unsigned long flags = 0; + crystalhd_rx_dma_pkt *temp = NULL; + + if (!hw) + return NULL; + + spin_lock_irqsave(&hw->lock, flags); + temp = hw->rx_pkt_pool_head; + if (temp) { + hw->rx_pkt_pool_head = hw->rx_pkt_pool_head->next; + temp->dio_req = NULL; + temp->pkt_tag = 0; + temp->flags = 0; + } + spin_unlock_irqrestore(&hw->lock, flags); + + return temp; +} + +static void crystalhd_hw_free_rx_pkt(struct crystalhd_hw *hw, + crystalhd_rx_dma_pkt *pkt) +{ + unsigned long flags = 0; + + if (!hw || !pkt) + return; + + spin_lock_irqsave(&hw->lock, flags); + pkt->next = hw->rx_pkt_pool_head; + hw->rx_pkt_pool_head = pkt; + spin_unlock_irqrestore(&hw->lock, flags); +} + +/* + * Call back from TX - IOQ deletion. + * + * This routine will release the TX DMA rings allocated + * druing setup_dma rings interface. + * + * Memory is allocated per DMA ring basis. This is just + * a place holder to be able to create the dio queues. + */ +static void crystalhd_tx_desc_rel_call_back(void *context, void *data) +{ +} + +/* + * Rx Packet release callback.. + * + * Release All user mapped capture buffers and Our DMA packets + * back to our free pool. The actual cleanup of the DMA + * ring descriptors happen during dma ring release. + */ +static void crystalhd_rx_pkt_rel_call_back(void *context, void *data) +{ + struct crystalhd_hw *hw = (struct crystalhd_hw *)context; + crystalhd_rx_dma_pkt *pkt = (crystalhd_rx_dma_pkt *)data; + + if (!pkt || !hw) { + BCMLOG_ERR("Invalid arg - %p %p\n", hw, pkt); + return; + } + + if (pkt->dio_req) + crystalhd_unmap_dio(hw->adp, pkt->dio_req); + else + BCMLOG_ERR("Missing dio_req: 0x%x\n", pkt->pkt_tag); + + crystalhd_hw_free_rx_pkt(hw, pkt); +} + +#define crystalhd_hw_delete_ioq(adp, q) \ + if (q) { \ + crystalhd_delete_dioq(adp, q); \ + q = NULL; \ + } + +static void crystalhd_hw_delete_ioqs(struct crystalhd_hw *hw) +{ + if (!hw) + return; + + BCMLOG(BCMLOG_DBG, "Deleting IOQs \n"); + crystalhd_hw_delete_ioq(hw->adp, hw->tx_actq); + crystalhd_hw_delete_ioq(hw->adp, hw->tx_freeq); + crystalhd_hw_delete_ioq(hw->adp, hw->rx_actq); + crystalhd_hw_delete_ioq(hw->adp, hw->rx_freeq); + crystalhd_hw_delete_ioq(hw->adp, hw->rx_rdyq); +} + +#define crystalhd_hw_create_ioq(sts, hw, q, cb) \ +do { \ + sts = crystalhd_create_dioq(hw->adp, &q, cb, hw); \ + if (sts != BC_STS_SUCCESS) \ + goto hw_create_ioq_err; \ +} while (0) + +/* + * Create IOQs.. + * + * TX - Active & Free + * RX - Active, Ready and Free. + */ +static BC_STATUS crystalhd_hw_create_ioqs(struct crystalhd_hw *hw) +{ + BC_STATUS sts = BC_STS_SUCCESS; + + if (!hw) { + BCMLOG_ERR("Invalid Arg!!\n"); + return BC_STS_INV_ARG; + } + + crystalhd_hw_create_ioq(sts, hw, hw->tx_freeq, + crystalhd_tx_desc_rel_call_back); + crystalhd_hw_create_ioq(sts, hw, hw->tx_actq, + crystalhd_tx_desc_rel_call_back); + + crystalhd_hw_create_ioq(sts, hw, hw->rx_freeq, + crystalhd_rx_pkt_rel_call_back); + crystalhd_hw_create_ioq(sts, hw, hw->rx_rdyq, + crystalhd_rx_pkt_rel_call_back); + crystalhd_hw_create_ioq(sts, hw, hw->rx_actq, + crystalhd_rx_pkt_rel_call_back); + + return sts; + +hw_create_ioq_err: + crystalhd_hw_delete_ioqs(hw); + + return sts; +} + + +static bool crystalhd_code_in_full(struct crystalhd_adp *adp, uint32_t needed_sz, + bool b_188_byte_pkts, uint8_t flags) +{ + uint32_t base, end, writep, readp; + uint32_t cpbSize, cpbFullness, fifoSize; + + if (flags & 0x02) { /* ASF Bit is set */ + base = bc_dec_reg_rd(adp, REG_Dec_TsAudCDB2Base); + end = bc_dec_reg_rd(adp, REG_Dec_TsAudCDB2End); + writep = bc_dec_reg_rd(adp, REG_Dec_TsAudCDB2Wrptr); + readp = bc_dec_reg_rd(adp, REG_Dec_TsAudCDB2Rdptr); + } else if (b_188_byte_pkts) { /*Encrypted 188 byte packets*/ + base = bc_dec_reg_rd(adp, REG_Dec_TsUser0Base); + end = bc_dec_reg_rd(adp, REG_Dec_TsUser0End); + writep = bc_dec_reg_rd(adp, REG_Dec_TsUser0Wrptr); + readp = bc_dec_reg_rd(adp, REG_Dec_TsUser0Rdptr); + } else { + base = bc_dec_reg_rd(adp, REG_DecCA_RegCinBase); + end = bc_dec_reg_rd(adp, REG_DecCA_RegCinEnd); + writep = bc_dec_reg_rd(adp, REG_DecCA_RegCinWrPtr); + readp = bc_dec_reg_rd(adp, REG_DecCA_RegCinRdPtr); + } + + cpbSize = end - base; + if (writep >= readp) + cpbFullness = writep - readp; + else + cpbFullness = (end - base) - (readp - writep); + + fifoSize = cpbSize - cpbFullness; + + if (fifoSize < BC_INFIFO_THRESHOLD) + return true; + + if (needed_sz > (fifoSize - BC_INFIFO_THRESHOLD)) + return true; + + return false; +} + +static BC_STATUS crystalhd_hw_tx_req_complete(struct crystalhd_hw *hw, + uint32_t list_id, BC_STATUS cs) +{ + tx_dma_pkt *tx_req; + + if (!hw || !list_id) { + BCMLOG_ERR("Invalid Arg..\n"); + return BC_STS_INV_ARG; + } + + hw->pwr_lock--; + + tx_req = (tx_dma_pkt *)crystalhd_dioq_find_and_fetch(hw->tx_actq, list_id); + if (!tx_req) { + if (cs != BC_STS_IO_USER_ABORT) + BCMLOG_ERR("Find and Fetch Did not find req\n"); + return BC_STS_NO_DATA; + } + + if (tx_req->call_back) { + tx_req->call_back(tx_req->dio_req, tx_req->cb_event, cs); + tx_req->dio_req = NULL; + tx_req->cb_event = NULL; + tx_req->call_back = NULL; + } else { + BCMLOG(BCMLOG_DBG, "Missing Tx Callback - %X\n", + tx_req->list_tag); + } + + /* Now put back the tx_list back in FreeQ */ + tx_req->list_tag = 0; + + return crystalhd_dioq_add(hw->tx_freeq, tx_req, false, 0); +} + +static bool crystalhd_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts) +{ + uint32_t err_mask, tmp; + unsigned long flags = 0; + + err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK | + MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK | + MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; + + if (!(err_sts & err_mask)) + return false; + + BCMLOG_ERR("Error on Tx-L0 %x \n", err_sts); + + tmp = err_mask; + + if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK) + tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; + + if (tmp) { + spin_lock_irqsave(&hw->lock, flags); + /* reset list index.*/ + hw->tx_list_post_index = 0; + spin_unlock_irqrestore(&hw->lock, flags); + } + + tmp = err_sts & err_mask; + crystalhd_reg_wr(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp); + + return true; +} + +static bool crystalhd_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts) +{ + uint32_t err_mask, tmp; + unsigned long flags = 0; + + err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK | + MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK | + MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; + + if (!(err_sts & err_mask)) + return false; + + BCMLOG_ERR("Error on Tx-L1 %x \n", err_sts); + + tmp = err_mask; + + if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK) + tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; + + if (tmp) { + spin_lock_irqsave(&hw->lock, flags); + /* reset list index.*/ + hw->tx_list_post_index = 0; + spin_unlock_irqrestore(&hw->lock, flags); + } + + tmp = err_sts & err_mask; + crystalhd_reg_wr(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp); + + return true; +} + +static void crystalhd_tx_isr(struct crystalhd_hw *hw, uint32_t int_sts) +{ + uint32_t err_sts; + + if (int_sts & INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK) + crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, + BC_STS_SUCCESS); + + if (int_sts & INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK) + crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, + BC_STS_SUCCESS); + + if (!(int_sts & (INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK | + INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK))) { + /* No error mask set.. */ + return; + } + + /* Handle Tx errors. */ + err_sts = crystalhd_reg_rd(hw->adp, MISC1_TX_DMA_ERROR_STATUS); + + if (crystalhd_tx_list0_handler(hw, err_sts)) + crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, + BC_STS_ERROR); + + if (crystalhd_tx_list1_handler(hw, err_sts)) + crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, + BC_STS_ERROR); + + hw->stats.tx_errors++; +} + +static void crystalhd_hw_dump_desc(pdma_descriptor p_dma_desc, + uint32_t ul_desc_index, uint32_t cnt) +{ + uint32_t ix, ll = 0; + + if (!p_dma_desc || !cnt) + return; + + /* FIXME: jarod: perhaps a modparam desc_debug to enable this, rather than + * setting ll (log level, I presume) to non-zero? */ + if (!ll) + return; + + for (ix = ul_desc_index; ix < (ul_desc_index + cnt); ix++) { + BCMLOG(ll, "%s[%d] Buff[%x:%x] Next:[%x:%x] XferSz:%x Intr:%x,Last:%x\n", + ((p_dma_desc[ul_desc_index].dma_dir) ? "TDesc" : "RDesc"), + ul_desc_index, + p_dma_desc[ul_desc_index].buff_addr_high, + p_dma_desc[ul_desc_index].buff_addr_low, + p_dma_desc[ul_desc_index].next_desc_addr_high, + p_dma_desc[ul_desc_index].next_desc_addr_low, + p_dma_desc[ul_desc_index].xfer_size, + p_dma_desc[ul_desc_index].intr_enable, + p_dma_desc[ul_desc_index].last_rec_indicator); + } + +} + +static BC_STATUS crystalhd_hw_fill_desc(crystalhd_dio_req *ioreq, + dma_descriptor *desc, + dma_addr_t desc_paddr_base, + uint32_t sg_cnt, uint32_t sg_st_ix, + uint32_t sg_st_off, uint32_t xfr_sz) +{ + uint32_t count = 0, ix = 0, sg_ix = 0, len = 0, last_desc_ix = 0; + dma_addr_t desc_phy_addr = desc_paddr_base; + addr_64 addr_temp; + + if (!ioreq || !desc || !desc_paddr_base || !xfr_sz || + (!sg_cnt && !ioreq->uinfo.dir_tx)) { + BCMLOG_ERR("Invalid Args\n"); + return BC_STS_INV_ARG; + } + + for (ix = 0; ix < sg_cnt; ix++) { + + /* Setup SGLE index. */ + sg_ix = ix + sg_st_ix; + + /* Get SGLE length */ + len = crystalhd_get_sgle_len(ioreq, sg_ix); + if (len % 4) { + BCMLOG_ERR(" len in sg %d %d %d\n", len, sg_ix, sg_cnt); + return BC_STS_NOT_IMPL; + } + /* Setup DMA desc with Phy addr & Length at current index. */ + addr_temp.full_addr = crystalhd_get_sgle_paddr(ioreq, sg_ix); + if (sg_ix == sg_st_ix) { + addr_temp.full_addr += sg_st_off; + len -= sg_st_off; + } + memset(&desc[ix], 0, sizeof(desc[ix])); + desc[ix].buff_addr_low = addr_temp.low_part; + desc[ix].buff_addr_high = addr_temp.high_part; + desc[ix].dma_dir = ioreq->uinfo.dir_tx; + + /* Chain DMA descriptor. */ + addr_temp.full_addr = desc_phy_addr + sizeof(dma_descriptor); + desc[ix].next_desc_addr_low = addr_temp.low_part; + desc[ix].next_desc_addr_high = addr_temp.high_part; + + if ((count + len) > xfr_sz) + len = xfr_sz - count; + + /* Debug.. */ + if ((!len) || (len > crystalhd_get_sgle_len(ioreq, sg_ix))) { + BCMLOG_ERR("inv-len(%x) Ix(%d) count:%x xfr_sz:%x sg_cnt:%d\n", + len, ix, count, xfr_sz, sg_cnt); + return BC_STS_ERROR; + } + /* Length expects Multiple of 4 */ + desc[ix].xfer_size = (len / 4); + + crystalhd_hw_dump_desc(desc, ix, 1); + + count += len; + desc_phy_addr += sizeof(dma_descriptor); + } + + last_desc_ix = ix - 1; + + if (ioreq->fb_size) { + memset(&desc[ix], 0, sizeof(desc[ix])); + addr_temp.full_addr = ioreq->fb_pa; + desc[ix].buff_addr_low = addr_temp.low_part; + desc[ix].buff_addr_high = addr_temp.high_part; + desc[ix].dma_dir = ioreq->uinfo.dir_tx; + desc[ix].xfer_size = 1; + desc[ix].fill_bytes = 4 - ioreq->fb_size; + count += ioreq->fb_size; + last_desc_ix++; + } + + /* setup last descriptor..*/ + desc[last_desc_ix].last_rec_indicator = 1; + desc[last_desc_ix].next_desc_addr_low = 0; + desc[last_desc_ix].next_desc_addr_high = 0; + desc[last_desc_ix].intr_enable = 1; + + crystalhd_hw_dump_desc(desc, last_desc_ix, 1); + + if (count != xfr_sz) { + BCMLOG_ERR("interal error sz curr:%x exp:%x\n", count, xfr_sz); + return BC_STS_ERROR; + } + + return BC_STS_SUCCESS; +} + +static BC_STATUS crystalhd_xlat_sgl_to_dma_desc(crystalhd_dio_req *ioreq, + pdma_desc_mem pdesc_mem, + uint32_t *uv_desc_index) +{ + dma_descriptor *desc = NULL; + dma_addr_t desc_paddr_base = 0; + uint32_t sg_cnt = 0, sg_st_ix = 0, sg_st_off = 0; + uint32_t xfr_sz = 0; + BC_STATUS sts = BC_STS_SUCCESS; + + /* Check params.. */ + if (!ioreq || !pdesc_mem || !uv_desc_index) { + BCMLOG_ERR("Invalid Args\n"); + return BC_STS_INV_ARG; + } + + if (!pdesc_mem->sz || !pdesc_mem->pdma_desc_start || + !ioreq->sg || (!ioreq->sg_cnt && !ioreq->uinfo.dir_tx)) { + BCMLOG_ERR("Invalid Args\n"); + return BC_STS_INV_ARG; + } + + if ((ioreq->uinfo.dir_tx) && (ioreq->uinfo.uv_offset)) { + BCMLOG_ERR("UV offset for TX??\n"); + return BC_STS_INV_ARG; + + } + + desc = pdesc_mem->pdma_desc_start; + desc_paddr_base = pdesc_mem->phy_addr; + + if (ioreq->uinfo.dir_tx || (ioreq->uinfo.uv_offset == 0)) { + sg_cnt = ioreq->sg_cnt; + xfr_sz = ioreq->uinfo.xfr_len; + } else { + sg_cnt = ioreq->uinfo.uv_sg_ix + 1; + xfr_sz = ioreq->uinfo.uv_offset; + } + + sts = crystalhd_hw_fill_desc(ioreq, desc, desc_paddr_base, sg_cnt, + sg_st_ix, sg_st_off, xfr_sz); + + if ((sts != BC_STS_SUCCESS) || !ioreq->uinfo.uv_offset) + return sts; + + /* Prepare for UV mapping.. */ + desc = &pdesc_mem->pdma_desc_start[sg_cnt]; + desc_paddr_base = pdesc_mem->phy_addr + + (sg_cnt * sizeof(dma_descriptor)); + + /* Done with desc addr.. now update sg stuff.*/ + sg_cnt = ioreq->sg_cnt - ioreq->uinfo.uv_sg_ix; + xfr_sz = ioreq->uinfo.xfr_len - ioreq->uinfo.uv_offset; + sg_st_ix = ioreq->uinfo.uv_sg_ix; + sg_st_off = ioreq->uinfo.uv_sg_off; + + sts = crystalhd_hw_fill_desc(ioreq, desc, desc_paddr_base, sg_cnt, + sg_st_ix, sg_st_off, xfr_sz); + if (sts != BC_STS_SUCCESS) + return sts; + + *uv_desc_index = sg_st_ix; + + return sts; +} + +static void crystalhd_start_tx_dma_engine(struct crystalhd_hw *hw) +{ + uint32_t dma_cntrl; + + dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS); + if (!(dma_cntrl & DMA_START_BIT)) { + dma_cntrl |= DMA_START_BIT; + crystalhd_reg_wr(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, + dma_cntrl); + } + + return; +} + +/* _CHECK_THIS_ + * + * Verify if the Stop generates a completion interrupt or not. + * if it does not generate an interrupt, then add polling here. + */ +static BC_STATUS crystalhd_stop_tx_dma_engine(struct crystalhd_hw *hw) +{ + uint32_t dma_cntrl, cnt = 30; + uint32_t l1 = 1, l2 = 1; + unsigned long flags = 0; + + dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS); + + BCMLOG(BCMLOG_DBG, "Stopping TX DMA Engine..\n"); + + /* FIXME: jarod: invert dma_ctrl and check bit? or are there missing parens? */ + if (!dma_cntrl & DMA_START_BIT) { + BCMLOG(BCMLOG_DBG, "Already Stopped\n"); + return BC_STS_SUCCESS; + } + + crystalhd_disable_interrupts(hw->adp); + + /* Issue stop to HW */ + /* This bit when set gave problems. Please check*/ + dma_cntrl &= ~DMA_START_BIT; + crystalhd_reg_wr(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + + BCMLOG(BCMLOG_DBG, "Cleared the DMA Start bit\n"); + + /* Poll for 3seconds (30 * 100ms) on both the lists..*/ + while ((l1 || l2) && cnt) { + + if (l1) { + l1 = crystalhd_reg_rd(hw->adp, MISC1_TX_FIRST_DESC_L_ADDR_LIST0); + l1 &= DMA_START_BIT; + } + + if (l2) { + l2 = crystalhd_reg_rd(hw->adp, MISC1_TX_FIRST_DESC_L_ADDR_LIST1); + l2 &= DMA_START_BIT; + } + + msleep_interruptible(100); + + cnt--; + } + + if (!cnt) { + BCMLOG_ERR("Failed to stop TX DMA.. l1 %d, l2 %d\n", l1, l2); + crystalhd_enable_interrupts(hw->adp); + return BC_STS_ERROR; + } + + spin_lock_irqsave(&hw->lock, flags); + hw->tx_list_post_index = 0; + spin_unlock_irqrestore(&hw->lock, flags); + BCMLOG(BCMLOG_DBG, "stopped TX DMA..\n"); + crystalhd_enable_interrupts(hw->adp); + + return BC_STS_SUCCESS; +} + +static uint32_t crystalhd_get_pib_avail_cnt(struct crystalhd_hw *hw) +{ + /* + * Position of the PIB Entries can be found at + * 0th and the 1st location of the Circular list. + */ + uint32_t Q_addr; + uint32_t pib_cnt, r_offset, w_offset; + + Q_addr = hw->pib_del_Q_addr; + + /* Get the Read Pointer */ + crystalhd_mem_rd(hw->adp, Q_addr, 1, &r_offset); + + /* Get the Write Pointer */ + crystalhd_mem_rd(hw->adp, Q_addr + sizeof(uint32_t), 1, &w_offset); + + if (r_offset == w_offset) + return 0; /* Queue is empty */ + + if (w_offset > r_offset) + pib_cnt = w_offset - r_offset; + else + pib_cnt = (w_offset + MAX_PIB_Q_DEPTH) - + (r_offset + MIN_PIB_Q_DEPTH); + + if (pib_cnt > MAX_PIB_Q_DEPTH) { + BCMLOG_ERR("Invalid PIB Count (%u)\n", pib_cnt); + return 0; + } + + return pib_cnt; +} + +static uint32_t crystalhd_get_addr_from_pib_Q(struct crystalhd_hw *hw) +{ + uint32_t Q_addr; + uint32_t addr_entry, r_offset, w_offset; + + Q_addr = hw->pib_del_Q_addr; + + /* Get the Read Pointer 0Th Location is Read Pointer */ + crystalhd_mem_rd(hw->adp, Q_addr, 1, &r_offset); + + /* Get the Write Pointer 1st Location is Write pointer */ + crystalhd_mem_rd(hw->adp, Q_addr + sizeof(uint32_t), 1, &w_offset); + + /* Queue is empty */ + if (r_offset == w_offset) + return 0; + + if ((r_offset < MIN_PIB_Q_DEPTH) || (r_offset >= MAX_PIB_Q_DEPTH)) + return 0; + + /* Get the Actual Address of the PIB */ + crystalhd_mem_rd(hw->adp, Q_addr + (r_offset * sizeof(uint32_t)), + 1, &addr_entry); + + /* Increment the Read Pointer */ + r_offset++; + + if (MAX_PIB_Q_DEPTH == r_offset) + r_offset = MIN_PIB_Q_DEPTH; + + /* Write back the read pointer to It's Location */ + crystalhd_mem_wr(hw->adp, Q_addr, 1, &r_offset); + + return addr_entry; +} + +static bool crystalhd_rel_addr_to_pib_Q(struct crystalhd_hw *hw, uint32_t addr_to_rel) +{ + uint32_t Q_addr; + uint32_t r_offset, w_offset, n_offset; + + Q_addr = hw->pib_rel_Q_addr; + + /* Get the Read Pointer */ + crystalhd_mem_rd(hw->adp, Q_addr, 1, &r_offset); + + /* Get the Write Pointer */ + crystalhd_mem_rd(hw->adp, Q_addr + sizeof(uint32_t), 1, &w_offset); + + if ((r_offset < MIN_PIB_Q_DEPTH) || + (r_offset >= MAX_PIB_Q_DEPTH)) + return false; + + n_offset = w_offset + 1; + + if (MAX_PIB_Q_DEPTH == n_offset) + n_offset = MIN_PIB_Q_DEPTH; + + if (r_offset == n_offset) + return false; /* should never happen */ + + /* Write the DRAM ADDR to the Queue at Next Offset */ + crystalhd_mem_wr(hw->adp, Q_addr + (w_offset * sizeof(uint32_t)), + 1, &addr_to_rel); + + /* Put the New value of the write pointer in Queue */ + crystalhd_mem_wr(hw->adp, Q_addr + sizeof(uint32_t), 1, &n_offset); + + return true; +} + +static void cpy_pib_to_app(C011_PIB *src_pib, BC_PIC_INFO_BLOCK *dst_pib) +{ + if (!src_pib || !dst_pib) { + BCMLOG_ERR("Invalid Arguments\n"); + return; + } + + dst_pib->timeStamp = 0; + dst_pib->picture_number = src_pib->ppb.picture_number; + dst_pib->width = src_pib->ppb.width; + dst_pib->height = src_pib->ppb.height; + dst_pib->chroma_format = src_pib->ppb.chroma_format; + dst_pib->pulldown = src_pib->ppb.pulldown; + dst_pib->flags = src_pib->ppb.flags; + dst_pib->sess_num = src_pib->ptsStcOffset; + dst_pib->aspect_ratio = src_pib->ppb.aspect_ratio; + dst_pib->colour_primaries = src_pib->ppb.colour_primaries; + dst_pib->picture_meta_payload = src_pib->ppb.picture_meta_payload; + dst_pib->frame_rate = src_pib->resolution ; + return; +} + +static void crystalhd_hw_proc_pib(struct crystalhd_hw *hw) +{ + unsigned int cnt; + C011_PIB src_pib; + uint32_t pib_addr, pib_cnt; + BC_PIC_INFO_BLOCK *AppPib; + crystalhd_rx_dma_pkt *rx_pkt = NULL; + + pib_cnt = crystalhd_get_pib_avail_cnt(hw); + + if (!pib_cnt) + return; + + for (cnt = 0; cnt < pib_cnt; cnt++) { + + pib_addr = crystalhd_get_addr_from_pib_Q(hw); + crystalhd_mem_rd(hw->adp, pib_addr, sizeof(C011_PIB) / 4, + (uint32_t *)&src_pib); + + if (src_pib.bFormatChange) { + rx_pkt = (crystalhd_rx_dma_pkt *)crystalhd_dioq_fetch(hw->rx_freeq); + if (!rx_pkt) + return; + rx_pkt->flags = 0; + rx_pkt->flags |= COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE; + AppPib = &rx_pkt->pib; + cpy_pib_to_app(&src_pib, AppPib); + + BCMLOG(BCMLOG_DBG, + "App PIB:%x %x %x %x %x %x %x %x %x %x\n", + rx_pkt->pib.picture_number, + rx_pkt->pib.aspect_ratio, + rx_pkt->pib.chroma_format, + rx_pkt->pib.colour_primaries, + rx_pkt->pib.frame_rate, + rx_pkt->pib.height, + rx_pkt->pib.height, + rx_pkt->pib.n_drop, + rx_pkt->pib.pulldown, + rx_pkt->pib.ycom); + + crystalhd_dioq_add(hw->rx_rdyq, (void *)rx_pkt, true, rx_pkt->pkt_tag); + + } + + crystalhd_rel_addr_to_pib_Q(hw, pib_addr); + } +} + +static void crystalhd_start_rx_dma_engine(struct crystalhd_hw *hw) +{ + uint32_t dma_cntrl; + + dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); + if (!(dma_cntrl & DMA_START_BIT)) { + dma_cntrl |= DMA_START_BIT; + crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + } + + dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); + if (!(dma_cntrl & DMA_START_BIT)) { + dma_cntrl |= DMA_START_BIT; + crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + } + + return; +} + +static void crystalhd_stop_rx_dma_engine(struct crystalhd_hw *hw) +{ + uint32_t dma_cntrl = 0, count = 30; + uint32_t l0y = 1, l0uv = 1, l1y = 1, l1uv = 1; + + dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); + if ((dma_cntrl & DMA_START_BIT)) { + dma_cntrl &= ~DMA_START_BIT; + crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + } + + dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); + if ((dma_cntrl & DMA_START_BIT)) { + dma_cntrl &= ~DMA_START_BIT; + crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + } + + /* Poll for 3seconds (30 * 100ms) on both the lists..*/ + while ((l0y || l0uv || l1y || l1uv) && count) { + + if (l0y) { + l0y = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0); + l0y &= DMA_START_BIT; + if (!l0y) { + hw->rx_list_sts[0] &= ~rx_waiting_y_intr; + } + } + + if (l1y) { + l1y = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1); + l1y &= DMA_START_BIT; + if (!l1y) { + hw->rx_list_sts[1] &= ~rx_waiting_y_intr; + } + } + + if (l0uv) { + l0uv = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0); + l0uv &= DMA_START_BIT; + if (!l0uv) { + hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; + } + } + + if (l1uv) { + l1uv = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1); + l1uv &= DMA_START_BIT; + if (!l1uv) { + hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; + } + } + msleep_interruptible(100); + count--; + } + + hw->rx_list_post_index = 0; + + BCMLOG(BCMLOG_SSTEP, "Capture Stop: %d List0:Sts:%x List1:Sts:%x\n", + count, hw->rx_list_sts[0], hw->rx_list_sts[1]); +} + +static BC_STATUS crystalhd_hw_prog_rxdma(struct crystalhd_hw *hw, crystalhd_rx_dma_pkt *rx_pkt) +{ + uint32_t y_low_addr_reg, y_high_addr_reg; + uint32_t uv_low_addr_reg, uv_high_addr_reg; + addr_64 desc_addr; + unsigned long flags; + + if (!hw || !rx_pkt) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + if (hw->rx_list_post_index >= DMA_ENGINE_CNT) { + BCMLOG_ERR("List Out Of bounds %x\n", hw->rx_list_post_index); + return BC_STS_INV_ARG; + } + + spin_lock_irqsave(&hw->rx_lock, flags); + /* FIXME: jarod: sts_free is an enum for 0, in crystalhd_hw.h... yuk... */ + if (sts_free != hw->rx_list_sts[hw->rx_list_post_index]) { + spin_unlock_irqrestore(&hw->rx_lock, flags); + return BC_STS_BUSY; + } + + if (!hw->rx_list_post_index) { + y_low_addr_reg = MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0; + y_high_addr_reg = MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0; + uv_low_addr_reg = MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0; + uv_high_addr_reg = MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0; + } else { + y_low_addr_reg = MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1; + y_high_addr_reg = MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1; + uv_low_addr_reg = MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1; + uv_high_addr_reg = MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1; + } + rx_pkt->pkt_tag = hw->rx_pkt_tag_seed + hw->rx_list_post_index; + hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_y_intr; + if (rx_pkt->uv_phy_addr) + hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_uv_intr; + hw->rx_list_post_index = (hw->rx_list_post_index + 1) % DMA_ENGINE_CNT; + spin_unlock_irqrestore(&hw->rx_lock, flags); + + crystalhd_dioq_add(hw->rx_actq, (void *)rx_pkt, false, rx_pkt->pkt_tag); + + crystalhd_start_rx_dma_engine(hw); + /* Program the Y descriptor */ + desc_addr.full_addr = rx_pkt->desc_mem.phy_addr; + crystalhd_reg_wr(hw->adp, y_high_addr_reg, desc_addr.high_part); + crystalhd_reg_wr(hw->adp, y_low_addr_reg, desc_addr.low_part | 0x01); + + if (rx_pkt->uv_phy_addr) { + /* Program the UV descriptor */ + desc_addr.full_addr = rx_pkt->uv_phy_addr; + crystalhd_reg_wr(hw->adp, uv_high_addr_reg, desc_addr.high_part); + crystalhd_reg_wr(hw->adp, uv_low_addr_reg, desc_addr.low_part | 0x01); + } + + return BC_STS_SUCCESS; +} + +static BC_STATUS crystalhd_hw_post_cap_buff(struct crystalhd_hw *hw, + crystalhd_rx_dma_pkt *rx_pkt) +{ + BC_STATUS sts = crystalhd_hw_prog_rxdma(hw, rx_pkt); + + if (sts == BC_STS_BUSY) + crystalhd_dioq_add(hw->rx_freeq, (void *)rx_pkt, + false, rx_pkt->pkt_tag); + + return sts; +} + +static void crystalhd_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, + uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz) +{ + uint32_t y_dn_sz_reg, uv_dn_sz_reg; + + if (!list_index) { + y_dn_sz_reg = MISC1_Y_RX_LIST0_CUR_BYTE_CNT; + uv_dn_sz_reg = MISC1_UV_RX_LIST0_CUR_BYTE_CNT; + } else { + y_dn_sz_reg = MISC1_Y_RX_LIST1_CUR_BYTE_CNT; + uv_dn_sz_reg = MISC1_UV_RX_LIST1_CUR_BYTE_CNT; + } + + *y_dw_dnsz = crystalhd_reg_rd(hw->adp, y_dn_sz_reg); + *uv_dw_dnsz = crystalhd_reg_rd(hw->adp, uv_dn_sz_reg); +} + +/* + * This function should be called only after making sure that the two DMA + * lists are free. This function does not check if DMA's are active, before + * turning off the DMA. + */ +static void crystalhd_hw_finalize_pause(struct crystalhd_hw *hw) +{ + uint32_t dma_cntrl, aspm; + + hw->stop_pending = 0; + + dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); + if (dma_cntrl & DMA_START_BIT) { + dma_cntrl &= ~DMA_START_BIT; + crystalhd_reg_wr(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + } + + dma_cntrl = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); + if (dma_cntrl & DMA_START_BIT) { + dma_cntrl &= ~DMA_START_BIT; + crystalhd_reg_wr(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); + } + hw->rx_list_post_index = 0; + + aspm = crystalhd_reg_rd(hw->adp, PCIE_DLL_DATA_LINK_CONTROL); + aspm |= ASPM_L1_ENABLE; + /* NAREN BCMLOG(BCMLOG_INFO, "aspm on\n"); */ + crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm); +} + +static BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, uint32_t list_index, + BC_STATUS comp_sts) +{ + crystalhd_rx_dma_pkt *rx_pkt = NULL; + uint32_t y_dw_dnsz, uv_dw_dnsz; + BC_STATUS sts = BC_STS_SUCCESS; + + if (!hw || list_index >= DMA_ENGINE_CNT) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + rx_pkt = crystalhd_dioq_find_and_fetch(hw->rx_actq, + hw->rx_pkt_tag_seed + list_index); + if (!rx_pkt) { + BCMLOG_ERR("Act-Q:PostIx:%x L0Sts:%x L1Sts:%x current L:%x tag:%x comp:%x\n", + hw->rx_list_post_index, hw->rx_list_sts[0], + hw->rx_list_sts[1], list_index, + hw->rx_pkt_tag_seed + list_index, comp_sts); + return BC_STS_INV_ARG; + } + + if (comp_sts == BC_STS_SUCCESS) { + crystalhd_get_dnsz(hw, list_index, &y_dw_dnsz, &uv_dw_dnsz); + rx_pkt->dio_req->uinfo.y_done_sz = y_dw_dnsz; + rx_pkt->flags = COMP_FLAG_DATA_VALID; + if (rx_pkt->uv_phy_addr) + rx_pkt->dio_req->uinfo.uv_done_sz = uv_dw_dnsz; + crystalhd_dioq_add(hw->rx_rdyq, rx_pkt, true, + hw->rx_pkt_tag_seed + list_index); + return sts; + } + + /* Check if we can post this DIO again. */ + return crystalhd_hw_post_cap_buff(hw, rx_pkt); +} + +static bool crystalhd_rx_list0_handler(struct crystalhd_hw *hw, uint32_t int_sts, + uint32_t y_err_sts, uint32_t uv_err_sts) +{ + uint32_t tmp; + list_sts tmp_lsts; + + if (!(y_err_sts & GET_Y0_ERR_MSK) && !(uv_err_sts & GET_UV0_ERR_MSK)) + return false; + + tmp_lsts = hw->rx_list_sts[0]; + + /* Y0 - DMA */ + tmp = y_err_sts & GET_Y0_ERR_MSK; + if (int_sts & INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) + hw->rx_list_sts[0] &= ~rx_waiting_y_intr; + + if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { + hw->rx_list_sts[0] &= ~rx_waiting_y_intr; + tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; + } + + if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { + hw->rx_list_sts[0] &= ~rx_y_mask; + hw->rx_list_sts[0] |= rx_y_error; + tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; + } + + if (tmp) { + hw->rx_list_sts[0] &= ~rx_y_mask; + hw->rx_list_sts[0] |= rx_y_error; + hw->rx_list_post_index = 0; + } + + /* UV0 - DMA */ + tmp = uv_err_sts & GET_UV0_ERR_MSK; + if (int_sts & INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK) + hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; + + if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { + hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; + tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; + } + + if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { + hw->rx_list_sts[0] &= ~rx_uv_mask; + hw->rx_list_sts[0] |= rx_uv_error; + tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; + } + + if (tmp) { + hw->rx_list_sts[0] &= ~rx_uv_mask; + hw->rx_list_sts[0] |= rx_uv_error; + hw->rx_list_post_index = 0; + } + + if (y_err_sts & GET_Y0_ERR_MSK) { + tmp = y_err_sts & GET_Y0_ERR_MSK; + crystalhd_reg_wr(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp); + } + + if (uv_err_sts & GET_UV0_ERR_MSK) { + tmp = uv_err_sts & GET_UV0_ERR_MSK; + crystalhd_reg_wr(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp); + } + + return (tmp_lsts != hw->rx_list_sts[0]); +} + +static bool crystalhd_rx_list1_handler(struct crystalhd_hw *hw, uint32_t int_sts, + uint32_t y_err_sts, uint32_t uv_err_sts) +{ + uint32_t tmp; + list_sts tmp_lsts; + + if (!(y_err_sts & GET_Y1_ERR_MSK) && !(uv_err_sts & GET_UV1_ERR_MSK)) + return false; + + tmp_lsts = hw->rx_list_sts[1]; + + /* Y1 - DMA */ + tmp = y_err_sts & GET_Y1_ERR_MSK; + if (int_sts & INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK) + hw->rx_list_sts[1] &= ~rx_waiting_y_intr; + + if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { + hw->rx_list_sts[1] &= ~rx_waiting_y_intr; + tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; + } + + if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { + /* Add retry-support..*/ + hw->rx_list_sts[1] &= ~rx_y_mask; + hw->rx_list_sts[1] |= rx_y_error; + tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; + } + + if (tmp) { + hw->rx_list_sts[1] &= ~rx_y_mask; + hw->rx_list_sts[1] |= rx_y_error; + hw->rx_list_post_index = 0; + } + + /* UV1 - DMA */ + tmp = uv_err_sts & GET_UV1_ERR_MSK; + if (int_sts & INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK) { + hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; + } + + if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { + hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; + tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; + } + + if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { + /* Add retry-support*/ + hw->rx_list_sts[1] &= ~rx_uv_mask; + hw->rx_list_sts[1] |= rx_uv_error; + tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; + } + + if (tmp) { + hw->rx_list_sts[1] &= ~rx_uv_mask; + hw->rx_list_sts[1] |= rx_uv_error; + hw->rx_list_post_index = 0; + } + + if (y_err_sts & GET_Y1_ERR_MSK) { + tmp = y_err_sts & GET_Y1_ERR_MSK; + crystalhd_reg_wr(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp); + } + + if (uv_err_sts & GET_UV1_ERR_MSK) { + tmp = uv_err_sts & GET_UV1_ERR_MSK; + crystalhd_reg_wr(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp); + } + + return (tmp_lsts != hw->rx_list_sts[1]); +} + + +static void crystalhd_rx_isr(struct crystalhd_hw *hw, uint32_t intr_sts) +{ + unsigned long flags; + uint32_t i, list_avail = 0; + BC_STATUS comp_sts = BC_STS_NO_DATA; + uint32_t y_err_sts, uv_err_sts, y_dn_sz = 0, uv_dn_sz = 0; + bool ret = 0; + + if (!hw) { + BCMLOG_ERR("Invalid Arguments\n"); + return; + } + + if (!(intr_sts & GET_RX_INTR_MASK)) + return; + + y_err_sts = crystalhd_reg_rd(hw->adp, MISC1_Y_RX_ERROR_STATUS); + uv_err_sts = crystalhd_reg_rd(hw->adp, MISC1_UV_RX_ERROR_STATUS); + + for (i = 0; i < DMA_ENGINE_CNT; i++) { + /* Update States..*/ + spin_lock_irqsave(&hw->rx_lock, flags); + if (i == 0) + ret = crystalhd_rx_list0_handler(hw, intr_sts, y_err_sts, uv_err_sts); + else + ret = crystalhd_rx_list1_handler(hw, intr_sts, y_err_sts, uv_err_sts); + if (ret) { + switch (hw->rx_list_sts[i]) { + case sts_free: + comp_sts = BC_STS_SUCCESS; + list_avail = 1; + break; + case rx_y_error: + case rx_uv_error: + case rx_sts_error: + /* We got error on both or Y or uv. */ + hw->stats.rx_errors++; + crystalhd_get_dnsz(hw, i, &y_dn_sz, &uv_dn_sz); + /* FIXME: jarod: this is where my mini pci-e card is tripping up */ + BCMLOG(BCMLOG_DBG, "list_index:%x rx[%d] Y:%x " + "UV:%x Int:%x YDnSz:%x UVDnSz:%x\n", + i, hw->stats.rx_errors, y_err_sts, + uv_err_sts, intr_sts, y_dn_sz, uv_dn_sz); + hw->rx_list_sts[i] = sts_free; + comp_sts = BC_STS_ERROR; + break; + default: + /* Wait for completion..*/ + comp_sts = BC_STS_NO_DATA; + break; + } + } + spin_unlock_irqrestore(&hw->rx_lock, flags); + + /* handle completion...*/ + if (comp_sts != BC_STS_NO_DATA) { + crystalhd_rx_pkt_done(hw, i, comp_sts); + comp_sts = BC_STS_NO_DATA; + } + } + + if (list_avail) { + if (hw->stop_pending) { + if ((hw->rx_list_sts[0] == sts_free) && + (hw->rx_list_sts[1] == sts_free)) + crystalhd_hw_finalize_pause(hw); + } else { + crystalhd_hw_start_capture(hw); + } + } +} + +static BC_STATUS crystalhd_fw_cmd_post_proc(struct crystalhd_hw *hw, + BC_FW_CMD *fw_cmd) +{ + BC_STATUS sts = BC_STS_SUCCESS; + DecRspChannelStartVideo *st_rsp = NULL; + + switch (fw_cmd->cmd[0]) { + case eCMD_C011_DEC_CHAN_START_VIDEO: + st_rsp = (DecRspChannelStartVideo *)fw_cmd->rsp; + hw->pib_del_Q_addr = st_rsp->picInfoDeliveryQ; + hw->pib_rel_Q_addr = st_rsp->picInfoReleaseQ; + BCMLOG(BCMLOG_DBG, "DelQAddr:%x RelQAddr:%x\n", + hw->pib_del_Q_addr, hw->pib_rel_Q_addr); + break; + case eCMD_C011_INIT: + if (!(crystalhd_load_firmware_config(hw->adp))) { + BCMLOG_ERR("Invalid Params.\n"); + sts = BC_STS_FW_AUTH_FAILED; + } + break; + default: + break; + } + return sts; +} + +static BC_STATUS crystalhd_put_ddr2sleep(struct crystalhd_hw *hw) +{ + uint32_t reg; + link_misc_perst_decoder_ctrl rst_cntrl_reg; + + /* Pulse reset pin of 7412 (MISC_PERST_DECODER_CTRL) */ + rst_cntrl_reg.whole_reg = crystalhd_reg_rd(hw->adp, MISC_PERST_DECODER_CTRL); + + rst_cntrl_reg.bcm_7412_rst = 1; + crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg); + msleep_interruptible(50); + + rst_cntrl_reg.bcm_7412_rst = 0; + crystalhd_reg_wr(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg); + + /* Close all banks, put DDR in idle */ + bc_dec_reg_wr(hw->adp, SDRAM_PRECHARGE, 0); + + /* Set bit 25 (drop CKE pin of DDR) */ + reg = bc_dec_reg_rd(hw->adp, SDRAM_PARAM); + reg |= 0x02000000; + bc_dec_reg_wr(hw->adp, SDRAM_PARAM, reg); + + /* Reset the audio block */ + bc_dec_reg_wr(hw->adp, AUD_DSP_MISC_SOFT_RESET, 0x1); + + /* Power down Raptor PLL */ + reg = bc_dec_reg_rd(hw->adp, DecHt_PllCCtl); + reg |= 0x00008000; + bc_dec_reg_wr(hw->adp, DecHt_PllCCtl, reg); + + /* Power down all Audio PLL */ + bc_dec_reg_wr(hw->adp, AIO_MISC_PLL_RESET, 0x1); + + /* Power down video clock (75MHz) */ + reg = bc_dec_reg_rd(hw->adp, DecHt_PllECtl); + reg |= 0x00008000; + bc_dec_reg_wr(hw->adp, DecHt_PllECtl, reg); + + /* Power down video clock (75MHz) */ + reg = bc_dec_reg_rd(hw->adp, DecHt_PllDCtl); + reg |= 0x00008000; + bc_dec_reg_wr(hw->adp, DecHt_PllDCtl, reg); + + /* Power down core clock (200MHz) */ + reg = bc_dec_reg_rd(hw->adp, DecHt_PllACtl); + reg |= 0x00008000; + bc_dec_reg_wr(hw->adp, DecHt_PllACtl, reg); + + /* Power down core clock (200MHz) */ + reg = bc_dec_reg_rd(hw->adp, DecHt_PllBCtl); + reg |= 0x00008000; + bc_dec_reg_wr(hw->adp, DecHt_PllBCtl, reg); + + return BC_STS_SUCCESS; +} + +/************************************************ +** +*************************************************/ + +BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp, void *buffer, uint32_t sz) +{ + uint32_t reg_data, cnt, *temp_buff; + uint32_t fw_sig_len = 36; + uint32_t dram_offset = BC_FWIMG_ST_ADDR, sig_reg; + + BCMLOG_ENTER; + + if (!adp || !buffer || !sz) { + BCMLOG_ERR("Invalid Params.\n"); + return BC_STS_INV_ARG; + } + + reg_data = crystalhd_reg_rd(adp, OTP_CMD); + if (!(reg_data & 0x02)) { + BCMLOG_ERR("Invalid hw config.. otp not programmed\n"); + return BC_STS_ERROR; + } + + reg_data = 0; + crystalhd_reg_wr(adp, DCI_CMD, 0); + reg_data |= BC_BIT(0); + crystalhd_reg_wr(adp, DCI_CMD, reg_data); + + reg_data = 0; + cnt = 1000; + msleep_interruptible(10); + + while (reg_data != BC_BIT(4)) { + reg_data = crystalhd_reg_rd(adp, DCI_STATUS); + reg_data &= BC_BIT(4); + if (--cnt == 0) { + BCMLOG_ERR("Firmware Download RDY Timeout.\n"); + return BC_STS_TIMEOUT; + } + } + + msleep_interruptible(10); + /* Load the FW to the FW_ADDR field in the DCI_FIRMWARE_ADDR */ + crystalhd_reg_wr(adp, DCI_FIRMWARE_ADDR, dram_offset); + temp_buff = (uint32_t *)buffer; + for (cnt = 0; cnt < (sz - fw_sig_len); cnt += 4) { + crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (dram_offset >> 19)); + crystalhd_reg_wr(adp, DCI_FIRMWARE_DATA, *temp_buff); + dram_offset += 4; + temp_buff++; + } + msleep_interruptible(10); + + temp_buff++; + + sig_reg = (uint32_t)DCI_SIGNATURE_DATA_7; + for (cnt = 0; cnt < 8; cnt++) { + uint32_t swapped_data = *temp_buff; + swapped_data = bswap_32_1(swapped_data); + crystalhd_reg_wr(adp, sig_reg, swapped_data); + sig_reg -= 4; + temp_buff++; + } + msleep_interruptible(10); + + reg_data = 0; + reg_data |= BC_BIT(1); + crystalhd_reg_wr(adp, DCI_CMD, reg_data); + msleep_interruptible(10); + + reg_data = 0; + reg_data = crystalhd_reg_rd(adp, DCI_STATUS); + + if ((reg_data & BC_BIT(9)) == BC_BIT(9)) { + cnt = 1000; + while ((reg_data & BC_BIT(0)) != BC_BIT(0)) { + reg_data = crystalhd_reg_rd(adp, DCI_STATUS); + reg_data &= BC_BIT(0); + if (!(--cnt)) + break; + msleep_interruptible(10); + } + reg_data = 0; + reg_data = crystalhd_reg_rd(adp, DCI_CMD); + reg_data |= BC_BIT(4); + crystalhd_reg_wr(adp, DCI_CMD, reg_data); + + } else { + BCMLOG_ERR("F/w Signature mismatch\n"); + return BC_STS_FW_AUTH_FAILED; + } + + BCMLOG(BCMLOG_INFO, "Firmware Downloaded Successfully\n"); + return BC_STS_SUCCESS;; +} + +BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd) +{ + uint32_t cnt = 0, cmd_res_addr; + uint32_t *cmd_buff, *res_buff; + wait_queue_head_t fw_cmd_event; + int rc = 0; + BC_STATUS sts; + + crystalhd_create_event(&fw_cmd_event); + + BCMLOG_ENTER; + + if (!hw || !fw_cmd) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + cmd_buff = fw_cmd->cmd; + res_buff = fw_cmd->rsp; + + if (!cmd_buff || !res_buff) { + BCMLOG_ERR("Invalid Parameters for F/W Command \n"); + return BC_STS_INV_ARG; + } + + hw->pwr_lock++; + + hw->fwcmd_evt_sts = 0; + hw->pfw_cmd_event = &fw_cmd_event; + + /*Write the command to the memory*/ + crystalhd_mem_wr(hw->adp, TS_Host2CpuSnd, FW_CMD_BUFF_SZ, cmd_buff); + + /*Memory Read for memory arbitrator flush*/ + crystalhd_mem_rd(hw->adp, TS_Host2CpuSnd, 1, &cnt); + + /* Write the command address to mailbox */ + bc_dec_reg_wr(hw->adp, Hst2CpuMbx1, TS_Host2CpuSnd); + msleep_interruptible(50); + + crystalhd_wait_on_event(&fw_cmd_event, hw->fwcmd_evt_sts, 20000, rc, 0); + + if (!rc) { + sts = BC_STS_SUCCESS; + } else if (rc == -EBUSY) { + BCMLOG_ERR("Firmware command T/O\n"); + sts = BC_STS_TIMEOUT; + } else if (rc == -EINTR) { + BCMLOG(BCMLOG_DBG, "FwCmd Wait Signal int.\n"); + sts = BC_STS_IO_USER_ABORT; + } else { + BCMLOG_ERR("FwCmd IO Error.\n"); + sts = BC_STS_IO_ERROR; + } + + if (sts != BC_STS_SUCCESS) { + BCMLOG_ERR("FwCmd Failed.\n"); + hw->pwr_lock--; + return sts; + } + + /*Get the Responce Address*/ + cmd_res_addr = bc_dec_reg_rd(hw->adp, Cpu2HstMbx1); + + /*Read the Response*/ + crystalhd_mem_rd(hw->adp, cmd_res_addr, FW_CMD_BUFF_SZ, res_buff); + + hw->pwr_lock--; + + if (res_buff[2] != C011_RET_SUCCESS) { + BCMLOG_ERR("res_buff[2] != C011_RET_SUCCESS\n"); + return BC_STS_FW_CMD_ERR; + } + + sts = crystalhd_fw_cmd_post_proc(hw, fw_cmd); + if (sts != BC_STS_SUCCESS) + BCMLOG_ERR("crystalhd_fw_cmd_post_proc Failed.\n"); + + return sts; +} + +bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, struct crystalhd_hw *hw) +{ + uint32_t intr_sts = 0; + uint32_t deco_intr = 0; + bool rc = 0; + + if (!adp || !hw->dev_started) + return rc; + + hw->stats.num_interrupts++; + hw->pwr_lock++; + + deco_intr = bc_dec_reg_rd(adp, Stream2Host_Intr_Sts); + intr_sts = crystalhd_reg_rd(adp, INTR_INTR_STATUS); + + if (intr_sts) { + /* let system know we processed interrupt..*/ + rc = 1; + hw->stats.dev_interrupts++; + } + + if (deco_intr && (deco_intr != 0xdeaddead)) { + + if (deco_intr & 0x80000000) { + /*Set the Event and the status flag*/ + if (hw->pfw_cmd_event) { + hw->fwcmd_evt_sts = 1; + crystalhd_set_event(hw->pfw_cmd_event); + } + } + + if (deco_intr & BC_BIT(1)) + crystalhd_hw_proc_pib(hw); + + bc_dec_reg_wr(adp, Stream2Host_Intr_Sts, deco_intr); + /* FIXME: jarod: No udelay? might this be the real reason mini pci-e cards were stalling out? */ + bc_dec_reg_wr(adp, Stream2Host_Intr_Sts, 0); + rc = 1; + } + + /* Rx interrupts */ + crystalhd_rx_isr(hw, intr_sts); + + /* Tx interrupts*/ + crystalhd_tx_isr(hw, intr_sts); + + /* Clear interrupts */ + if (rc) { + if (intr_sts) + crystalhd_reg_wr(adp, INTR_INTR_CLR_REG, intr_sts); + + crystalhd_reg_wr(adp, INTR_EOI_CTRL, 1); + } + + hw->pwr_lock--; + + return rc; +} + +BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw, struct crystalhd_adp *adp) +{ + if (!hw || !adp) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + if (hw->dev_started) + return BC_STS_SUCCESS; + + memset(hw, 0, sizeof(struct crystalhd_hw)); + + hw->adp = adp; + spin_lock_init(&hw->lock); + spin_lock_init(&hw->rx_lock); + /* FIXME: jarod: what are these magic numbers?!? */ + hw->tx_ioq_tag_seed = 0x70023070; + hw->rx_pkt_tag_seed = 0x70029070; + + hw->stop_pending = 0; + crystalhd_start_device(hw->adp); + hw->dev_started = true; + + /* set initial core clock */ + hw->core_clock_mhz = CLOCK_PRESET; + hw->prev_n = 0; + hw->pwr_lock = 0; + crystalhd_hw_set_core_clock(hw); + + return BC_STS_SUCCESS; +} + +BC_STATUS crystalhd_hw_close(struct crystalhd_hw *hw) +{ + if (!hw) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + if (!hw->dev_started) + return BC_STS_SUCCESS; + + /* Stop and DDR sleep will happen in here */ + crystalhd_hw_suspend(hw); + hw->dev_started = false; + + return BC_STS_SUCCESS; +} + +BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *hw) +{ + unsigned int i; + void *mem; + size_t mem_len; + dma_addr_t phy_addr; + BC_STATUS sts = BC_STS_SUCCESS; + crystalhd_rx_dma_pkt *rpkt; + + if (!hw || !hw->adp) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + sts = crystalhd_hw_create_ioqs(hw); + if (sts != BC_STS_SUCCESS) { + BCMLOG_ERR("Failed to create IOQs..\n"); + return sts; + } + + mem_len = BC_LINK_MAX_SGLS * sizeof(dma_descriptor); + + for (i = 0; i < BC_TX_LIST_CNT; i++) { + mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr); + if (mem) { + memset(mem, 0, mem_len); + } else { + BCMLOG_ERR("Insufficient Memory For TX\n"); + crystalhd_hw_free_dma_rings(hw); + return BC_STS_INSUFF_RES; + } + /* rx_pkt_pool -- static memory allocation */ + hw->tx_pkt_pool[i].desc_mem.pdma_desc_start = mem; + hw->tx_pkt_pool[i].desc_mem.phy_addr = phy_addr; + hw->tx_pkt_pool[i].desc_mem.sz = BC_LINK_MAX_SGLS * + sizeof(dma_descriptor); + hw->tx_pkt_pool[i].list_tag = 0; + + /* Add TX dma requests to Free Queue..*/ + sts = crystalhd_dioq_add(hw->tx_freeq, + &hw->tx_pkt_pool[i], false, 0); + if (sts != BC_STS_SUCCESS) { + crystalhd_hw_free_dma_rings(hw); + return sts; + } + } + + for (i = 0; i < BC_RX_LIST_CNT; i++) { + rpkt = kzalloc(sizeof(*rpkt), GFP_KERNEL); + if (!rpkt) { + BCMLOG_ERR("Insufficient Memory For RX\n"); + crystalhd_hw_free_dma_rings(hw); + return BC_STS_INSUFF_RES; + } + + mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr); + if (mem) { + memset(mem, 0, mem_len); + } else { + BCMLOG_ERR("Insufficient Memory For RX\n"); + crystalhd_hw_free_dma_rings(hw); + return BC_STS_INSUFF_RES; + } + rpkt->desc_mem.pdma_desc_start = mem; + rpkt->desc_mem.phy_addr = phy_addr; + rpkt->desc_mem.sz = BC_LINK_MAX_SGLS * sizeof(dma_descriptor); + rpkt->pkt_tag = hw->rx_pkt_tag_seed + i; + crystalhd_hw_free_rx_pkt(hw, rpkt); + } + + return BC_STS_SUCCESS; +} + +BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *hw) +{ + unsigned int i; + crystalhd_rx_dma_pkt *rpkt = NULL; + + if (!hw || !hw->adp) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + /* Delete all IOQs.. */ + crystalhd_hw_delete_ioqs(hw); + + for (i = 0; i < BC_TX_LIST_CNT; i++) { + if (hw->tx_pkt_pool[i].desc_mem.pdma_desc_start) { + bc_kern_dma_free(hw->adp, + hw->tx_pkt_pool[i].desc_mem.sz, + hw->tx_pkt_pool[i].desc_mem.pdma_desc_start, + hw->tx_pkt_pool[i].desc_mem.phy_addr); + + hw->tx_pkt_pool[i].desc_mem.pdma_desc_start = NULL; + } + } + + BCMLOG(BCMLOG_DBG, "Releasing RX Pkt pool\n"); + do { + rpkt = crystalhd_hw_alloc_rx_pkt(hw); + if (!rpkt) + break; + bc_kern_dma_free(hw->adp, rpkt->desc_mem.sz, + rpkt->desc_mem.pdma_desc_start, + rpkt->desc_mem.phy_addr); + kfree(rpkt); + } while (rpkt); + + return BC_STS_SUCCESS; +} + +BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, crystalhd_dio_req *ioreq, + hw_comp_callback call_back, + wait_queue_head_t *cb_event, uint32_t *list_id, + uint8_t data_flags) +{ + tx_dma_pkt *tx_dma_packet = NULL; + uint32_t first_desc_u_addr, first_desc_l_addr; + uint32_t low_addr, high_addr; + addr_64 desc_addr; + BC_STATUS sts, add_sts; + uint32_t dummy_index = 0; + unsigned long flags; + bool rc; + + if (!hw || !ioreq || !call_back || !cb_event || !list_id) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + /* + * Since we hit code in busy condition very frequently, + * we will check the code in status first before + * checking the availability of free elem. + * + * This will avoid the Q fetch/add in normal condition. + */ + rc = crystalhd_code_in_full(hw->adp, ioreq->uinfo.xfr_len, + false, data_flags); + if (rc) { + hw->stats.cin_busy++; + return BC_STS_BUSY; + } + + /* Get a list from TxFreeQ */ + tx_dma_packet = (tx_dma_pkt *)crystalhd_dioq_fetch(hw->tx_freeq); + if (!tx_dma_packet) { + BCMLOG_ERR("No empty elements..\n"); + return BC_STS_ERR_USAGE; + } + + sts = crystalhd_xlat_sgl_to_dma_desc(ioreq, + &tx_dma_packet->desc_mem, + &dummy_index); + if (sts != BC_STS_SUCCESS) { + add_sts = crystalhd_dioq_add(hw->tx_freeq, tx_dma_packet, + false, 0); + if (add_sts != BC_STS_SUCCESS) + BCMLOG_ERR("double fault..\n"); + + return sts; + } + + hw->pwr_lock++; + + desc_addr.full_addr = tx_dma_packet->desc_mem.phy_addr; + low_addr = desc_addr.low_part; + high_addr = desc_addr.high_part; + + tx_dma_packet->call_back = call_back; + tx_dma_packet->cb_event = cb_event; + tx_dma_packet->dio_req = ioreq; + + spin_lock_irqsave(&hw->lock, flags); + + if (hw->tx_list_post_index == 0) { + first_desc_u_addr = MISC1_TX_FIRST_DESC_U_ADDR_LIST0; + first_desc_l_addr = MISC1_TX_FIRST_DESC_L_ADDR_LIST0; + } else { + first_desc_u_addr = MISC1_TX_FIRST_DESC_U_ADDR_LIST1; + first_desc_l_addr = MISC1_TX_FIRST_DESC_L_ADDR_LIST1; + } + + *list_id = tx_dma_packet->list_tag = hw->tx_ioq_tag_seed + + hw->tx_list_post_index; + + hw->tx_list_post_index = (hw->tx_list_post_index + 1) % DMA_ENGINE_CNT; + + spin_unlock_irqrestore(&hw->lock, flags); + + + /* Insert in Active Q..*/ + crystalhd_dioq_add(hw->tx_actq, tx_dma_packet, false, + tx_dma_packet->list_tag); + + /* + * Interrupt will come as soon as you write + * the valid bit. So be ready for that. All + * the initialization should happen before that. + */ + crystalhd_start_tx_dma_engine(hw); + crystalhd_reg_wr(hw->adp, first_desc_u_addr, desc_addr.high_part); + + crystalhd_reg_wr(hw->adp, first_desc_l_addr, desc_addr.low_part | 0x01); + /* Be sure we set the valid bit ^^^^ */ + + return BC_STS_SUCCESS; +} + +/* + * This is a force cancel and we are racing with ISR. + * + * Will try to remove the req from ActQ before ISR gets it. + * If ISR gets it first then the completion happens in the + * normal path and we will return _STS_NO_DATA from here. + * + * FIX_ME: Not Tested the actual condition.. + */ +BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id) +{ + if (!hw || !list_id) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + crystalhd_stop_tx_dma_engine(hw); + crystalhd_hw_tx_req_complete(hw, list_id, BC_STS_IO_USER_ABORT); + + return BC_STS_SUCCESS; +} + +BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw, + crystalhd_dio_req *ioreq, bool en_post) +{ + crystalhd_rx_dma_pkt *rpkt; + uint32_t tag, uv_desc_ix = 0; + BC_STATUS sts; + + if (!hw || !ioreq) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + rpkt = crystalhd_hw_alloc_rx_pkt(hw); + if (!rpkt) { + BCMLOG_ERR("Insufficient resources\n"); + return BC_STS_INSUFF_RES; + } + + rpkt->dio_req = ioreq; + tag = rpkt->pkt_tag; + + sts = crystalhd_xlat_sgl_to_dma_desc(ioreq, &rpkt->desc_mem, &uv_desc_ix); + if (sts != BC_STS_SUCCESS) + return sts; + + rpkt->uv_phy_addr = 0; + + /* Store the address of UV in the rx packet for post*/ + if (uv_desc_ix) + rpkt->uv_phy_addr = rpkt->desc_mem.phy_addr + + (sizeof(dma_descriptor) * (uv_desc_ix + 1)); + + if (en_post) + sts = crystalhd_hw_post_cap_buff(hw, rpkt); + else + sts = crystalhd_dioq_add(hw->rx_freeq, rpkt, false, tag); + + return sts; +} + +BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw, + BC_PIC_INFO_BLOCK *pib, + crystalhd_dio_req **ioreq) +{ + crystalhd_rx_dma_pkt *rpkt; + uint32_t timeout = BC_PROC_OUTPUT_TIMEOUT / 1000; + uint32_t sig_pending = 0; + + + if (!hw || !ioreq || !pib) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + rpkt = crystalhd_dioq_fetch_wait(hw->rx_rdyq, timeout, &sig_pending); + if (!rpkt) { + if (sig_pending) { + BCMLOG(BCMLOG_INFO, "wait on frame time out %d\n", sig_pending); + return BC_STS_IO_USER_ABORT; + } else { + return BC_STS_TIMEOUT; + } + } + + rpkt->dio_req->uinfo.comp_flags = rpkt->flags; + + if (rpkt->flags & COMP_FLAG_PIB_VALID) + memcpy(pib, &rpkt->pib, sizeof(*pib)); + + *ioreq = rpkt->dio_req; + + crystalhd_hw_free_rx_pkt(hw, rpkt); + + return BC_STS_SUCCESS; +} + +BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw) +{ + crystalhd_rx_dma_pkt *rx_pkt; + BC_STATUS sts; + uint32_t i; + + if (!hw) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + /* This is start of capture.. Post to both the lists.. */ + for (i = 0; i < DMA_ENGINE_CNT; i++) { + rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); + if (!rx_pkt) + return BC_STS_NO_DATA; + sts = crystalhd_hw_post_cap_buff(hw, rx_pkt); + if (BC_STS_SUCCESS != sts) + break; + + } + + return BC_STS_SUCCESS; +} + +BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw) +{ + void *temp = NULL; + + if (!hw) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + crystalhd_stop_rx_dma_engine(hw); + + do { + temp = crystalhd_dioq_fetch(hw->rx_freeq); + if (temp) + crystalhd_rx_pkt_rel_call_back(hw, temp); + } while (temp); + + return BC_STS_SUCCESS; +} + +BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw) +{ + hw->stats.pause_cnt++; + hw->stop_pending = 1; + + if ((hw->rx_list_sts[0] == sts_free) && + (hw->rx_list_sts[1] == sts_free)) + crystalhd_hw_finalize_pause(hw); + + return BC_STS_SUCCESS; +} + +BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw) +{ + BC_STATUS sts; + uint32_t aspm; + + hw->stop_pending = 0; + + aspm = crystalhd_reg_rd(hw->adp, PCIE_DLL_DATA_LINK_CONTROL); + aspm &= ~ASPM_L1_ENABLE; +/* NAREN BCMLOG(BCMLOG_INFO, "aspm off\n"); */ + crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm); + + sts = crystalhd_hw_start_capture(hw); + return sts; +} + +BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw) +{ + BC_STATUS sts; + + if (!hw) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + sts = crystalhd_put_ddr2sleep(hw); + if (sts != BC_STS_SUCCESS) { + BCMLOG_ERR("Failed to Put DDR To Sleep!!\n"); + return BC_STS_ERROR; + } + + if (!crystalhd_stop_device(hw->adp)) { + BCMLOG_ERR("Failed to Stop Device!!\n"); + return BC_STS_ERROR; + } + + return BC_STS_SUCCESS; +} + +void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats) +{ + if (!hw) { + BCMLOG_ERR("Invalid Arguments\n"); + return; + } + + /* if called w/NULL stats, its a req to zero out the stats */ + if (!stats) { + memset(&hw->stats, 0, sizeof(hw->stats)); + return; + } + + hw->stats.freeq_count = crystalhd_dioq_count(hw->rx_freeq); + hw->stats.rdyq_count = crystalhd_dioq_count(hw->rx_rdyq); + memcpy(stats, &hw->stats, sizeof(*stats)); +} + +BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *hw) +{ + uint32_t reg, n, i; + uint32_t vco_mg, refresh_reg; + + if (!hw) { + BCMLOG_ERR("Invalid Arguments\n"); + return BC_STS_INV_ARG; + } + + /* FIXME: jarod: wha? */ + /*n = (hw->core_clock_mhz * 3) / 20 + 1; */ + n = hw->core_clock_mhz/5; + + if (n == hw->prev_n) + return BC_STS_CLK_NOCHG; + + if (hw->pwr_lock > 0) { + /* BCMLOG(BCMLOG_INFO,"pwr_lock is %u\n", hw->pwr_lock) */ + return BC_STS_CLK_NOCHG; + } + + i = n * 27; + if (i < 560) + vco_mg = 0; + else if (i < 900) + vco_mg = 1; + else if (i < 1030) + vco_mg = 2; + else + vco_mg = 3; + + reg = bc_dec_reg_rd(hw->adp, DecHt_PllACtl); + + reg &= 0xFFFFCFC0; + reg |= n; + reg |= vco_mg << 12; + + BCMLOG(BCMLOG_INFO, "clock is moving to %d with n %d with vco_mg %d\n", + hw->core_clock_mhz, n, vco_mg); + + /* Change the DRAM refresh rate to accomodate the new frequency */ + /* refresh reg = ((refresh_rate * clock_rate)/16) - 1; rounding up*/ + refresh_reg = (7 * hw->core_clock_mhz / 16); + bc_dec_reg_wr(hw->adp, SDRAM_REF_PARAM, ((1 << 12) | refresh_reg)); + + bc_dec_reg_wr(hw->adp, DecHt_PllACtl, reg); + + i = 0; + + for (i = 0; i < 10; i++) { + reg = bc_dec_reg_rd(hw->adp, DecHt_PllACtl); + + if (reg & 0x00020000) { + hw->prev_n = n; + /* FIXME: jarod: outputting a random "C" is... confusing... */ + BCMLOG(BCMLOG_INFO, "C"); + return BC_STS_SUCCESS; + } else { + msleep_interruptible(10); + } + } + BCMLOG(BCMLOG_INFO, "clk change failed\n"); + return BC_STS_CLK_NOCHG; +} diff --git a/drivers/staging/crystalhd/crystalhd_hw.h b/drivers/staging/crystalhd/crystalhd_hw.h new file mode 100644 index 000000000000..1c6318e912ac --- /dev/null +++ b/drivers/staging/crystalhd/crystalhd_hw.h @@ -0,0 +1,398 @@ +/*************************************************************************** + * Copyright (c) 2005-2009, Broadcom Corporation. + * + * Name: crystalhd_hw . h + * + * Description: + * BCM70012 Linux driver hardware layer. + * + * HISTORY: + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#ifndef _CRYSTALHD_HW_H_ +#define _CRYSTALHD_HW_H_ + +#include "crystalhd_misc.h" +#include "crystalhd_fw_if.h" + +/* HW constants..*/ +#define DMA_ENGINE_CNT 2 +#define MAX_PIB_Q_DEPTH 64 +#define MIN_PIB_Q_DEPTH 2 +#define WR_POINTER_OFF 4 + +#define ASPM_L1_ENABLE (BC_BIT(27)) + +/************************************************* + 7412 Decoder Registers. +**************************************************/ +#define FW_CMD_BUFF_SZ 64 +#define TS_Host2CpuSnd 0x00000100 +#define Hst2CpuMbx1 0x00100F00 +#define Cpu2HstMbx1 0x00100F04 +#define MbxStat1 0x00100F08 +#define Stream2Host_Intr_Sts 0x00100F24 +#define C011_RET_SUCCESS 0x0 /* Reutrn status of firmware command. */ + +/* TS input status register */ +#define TS_StreamAFIFOStatus 0x0010044C +#define TS_StreamBFIFOStatus 0x0010084C + +/*UART Selection definitions*/ +#define UartSelectA 0x00100300 +#define UartSelectB 0x00100304 + +#define BSVS_UART_DEC_NONE 0x00 +#define BSVS_UART_DEC_OUTER 0x01 +#define BSVS_UART_DEC_INNER 0x02 +#define BSVS_UART_STREAM 0x03 + +/* Code-In fifo */ +#define REG_DecCA_RegCinCTL 0xa00 +#define REG_DecCA_RegCinBase 0xa0c +#define REG_DecCA_RegCinEnd 0xa10 +#define REG_DecCA_RegCinWrPtr 0xa04 +#define REG_DecCA_RegCinRdPtr 0xa08 + +#define REG_Dec_TsUser0Base 0x100864 +#define REG_Dec_TsUser0Rdptr 0x100868 +#define REG_Dec_TsUser0Wrptr 0x10086C +#define REG_Dec_TsUser0End 0x100874 + +/* ASF Case ...*/ +#define REG_Dec_TsAudCDB2Base 0x10036c +#define REG_Dec_TsAudCDB2Rdptr 0x100378 +#define REG_Dec_TsAudCDB2Wrptr 0x100374 +#define REG_Dec_TsAudCDB2End 0x100370 + +/* DRAM bringup Registers */ +#define SDRAM_PARAM 0x00040804 +#define SDRAM_PRECHARGE 0x000408B0 +#define SDRAM_EXT_MODE 0x000408A4 +#define SDRAM_MODE 0x000408A0 +#define SDRAM_REFRESH 0x00040890 +#define SDRAM_REF_PARAM 0x00040808 + +#define DecHt_PllACtl 0x34000C +#define DecHt_PllBCtl 0x340010 +#define DecHt_PllCCtl 0x340014 +#define DecHt_PllDCtl 0x340034 +#define DecHt_PllECtl 0x340038 +#define AUD_DSP_MISC_SOFT_RESET 0x00240104 +#define AIO_MISC_PLL_RESET 0x0026000C +#define PCIE_CLK_REQ_REG 0xDC +#define PCI_CLK_REQ_ENABLE (BC_BIT(8)) + +/************************************************* + F/W Copy engine definitions.. +**************************************************/ +#define BC_FWIMG_ST_ADDR 0x00000000 +/* FIXME: jarod: there's a kernel function that'll do this for us... */ +#define rotr32_1(x, n) (((x) >> n) | ((x) << (32 - n))) +#define bswap_32_1(x) ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00)) + +#define DecHt_HostSwReset 0x340000 +#define BC_DRAM_FW_CFG_ADDR 0x001c2000 + +typedef union _addr_64_ { + struct { + uint32_t low_part; + uint32_t high_part; + }; + + uint64_t full_addr; + +} addr_64; + +typedef union _intr_mask_reg_ { + struct { + uint32_t mask_tx_done:1; + uint32_t mask_tx_err:1; + uint32_t mask_rx_done:1; + uint32_t mask_rx_err:1; + uint32_t mask_pcie_err:1; + uint32_t mask_pcie_rbusmast_err:1; + uint32_t mask_pcie_rgr_bridge:1; + uint32_t reserved:25; + }; + + uint32_t whole_reg; + +} intr_mask_reg; + +typedef union _link_misc_perst_deco_ctrl_ { + struct { + uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ + uint32_t reserved0:3; /* Reserved.No Effect*/ + uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ + uint32_t reserved1:27; /* Reseved. No Effect*/ + }; + + uint32_t whole_reg; + +} link_misc_perst_deco_ctrl; + +typedef union _link_misc_perst_clk_ctrl_ { + struct { + uint32_t sel_alt_clk:1; /* When set, selects a 6.75MHz clock as the source of core_clk */ + uint32_t stop_core_clk:1; /* When set, stops the branch of core_clk that is not needed for low power operation */ + uint32_t pll_pwr_dn:1; /* When set, powers down the main PLL. The alternate clock bit should be set + to select an alternate clock before setting this bit.*/ + uint32_t reserved0:5; /* Reserved */ + uint32_t pll_mult:8; /* This setting controls the multiplier for the PLL. */ + uint32_t pll_div:4; /* This setting controls the divider for the PLL. */ + uint32_t reserved1:12; /* Reserved */ + }; + + uint32_t whole_reg; + +} link_misc_perst_clk_ctrl; + + +typedef union _link_misc_perst_decoder_ctrl_ { + struct { + uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ + uint32_t res0:3; /* Reserved.No Effect*/ + uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ + uint32_t res1:27; /* Reseved. No Effect */ + }; + + uint32_t whole_reg; + +} link_misc_perst_decoder_ctrl; + + +typedef union _desc_low_addr_reg_ { + struct { + uint32_t list_valid:1; + uint32_t reserved:4; + uint32_t low_addr:27; + }; + + uint32_t whole_reg; + +} desc_low_addr_reg; + +typedef struct _dma_descriptor_ { /* 8 32-bit values */ + /* 0th u32 */ + uint32_t sdram_buff_addr:28; /* bits 0-27: SDRAM Address */ + uint32_t res0:4; /* bits 28-31: Reserved */ + + /* 1st u32 */ + uint32_t buff_addr_low; /* 1 buffer address low */ + uint32_t buff_addr_high; /* 2 buffer address high */ + + /* 3rd u32 */ + uint32_t res2:2; /* 0-1 - Reserved */ + uint32_t xfer_size:23; /* 2-24 = Xfer size in words */ + uint32_t res3:6; /* 25-30 reserved */ + uint32_t intr_enable:1; /* 31 - Interrupt After this desc */ + + /* 4th u32 */ + uint32_t endian_xlat_align:2; /* 0-1 Endian Translation */ + uint32_t next_desc_cont:1; /* 2 - Next desc is in contig memory */ + uint32_t res4:25; /* 3 - 27 Reserved bits */ + uint32_t fill_bytes:2; /* 28-29 Bits Fill Bytes */ + uint32_t dma_dir:1; /* 30 bit DMA Direction */ + uint32_t last_rec_indicator:1; /* 31 bit Last Record Indicator */ + + /* 5th u32 */ + uint32_t next_desc_addr_low; /* 32-bits Next Desc Addr lower */ + + /* 6th u32 */ + uint32_t next_desc_addr_high; /* 32-bits Next Desc Addr Higher */ + + /* 7th u32 */ + uint32_t res8; /* Last 32bits reserved */ + +} dma_descriptor, *pdma_descriptor; + +/* + * We will allocate the memory in 4K pages + * the linked list will be a list of 32 byte descriptors. + * The virtual address will determine what should be freed. + */ +typedef struct _dma_desc_mem_ { + pdma_descriptor pdma_desc_start; /* 32-bytes for dma descriptor. should be first element */ + dma_addr_t phy_addr; /* physical address of each DMA desc */ + uint32_t sz; + struct _dma_desc_mem_ *Next; /* points to Next Descriptor in chain */ + +} dma_desc_mem, *pdma_desc_mem; + + + +typedef enum _list_sts_ { + sts_free = 0, + + /* RX-Y Bits 0:7 */ + rx_waiting_y_intr = 0x00000001, + rx_y_error = 0x00000004, + + /* RX-UV Bits 8:16 */ + rx_waiting_uv_intr = 0x0000100, + rx_uv_error = 0x0000400, + + rx_sts_waiting = (rx_waiting_y_intr|rx_waiting_uv_intr), + rx_sts_error = (rx_y_error|rx_uv_error), + + rx_y_mask = 0x000000FF, + rx_uv_mask = 0x0000FF00, + +} list_sts; + +typedef struct _tx_dma_pkt_ { + dma_desc_mem desc_mem; + hw_comp_callback call_back; + crystalhd_dio_req *dio_req; + wait_queue_head_t *cb_event; + uint32_t list_tag; + +} tx_dma_pkt; + +typedef struct _crystalhd_rx_dma_pkt { + dma_desc_mem desc_mem; + crystalhd_dio_req *dio_req; + uint32_t pkt_tag; + uint32_t flags; + BC_PIC_INFO_BLOCK pib; + dma_addr_t uv_phy_addr; + struct _crystalhd_rx_dma_pkt *next; + +} crystalhd_rx_dma_pkt; + +struct crystalhd_hw_stats{ + uint32_t rx_errors; + uint32_t tx_errors; + uint32_t freeq_count; + uint32_t rdyq_count; + uint32_t num_interrupts; + uint32_t dev_interrupts; + uint32_t cin_busy; + uint32_t pause_cnt; +}; + +struct crystalhd_hw { + tx_dma_pkt tx_pkt_pool[DMA_ENGINE_CNT]; + spinlock_t lock; + + uint32_t tx_ioq_tag_seed; + uint32_t tx_list_post_index; + + crystalhd_rx_dma_pkt *rx_pkt_pool_head; + uint32_t rx_pkt_tag_seed; + + bool dev_started; + void *adp; + + wait_queue_head_t *pfw_cmd_event; + int fwcmd_evt_sts; + + uint32_t pib_del_Q_addr; + uint32_t pib_rel_Q_addr; + + crystalhd_dioq_t *tx_freeq; + crystalhd_dioq_t *tx_actq; + + /* Rx DMA Engine Specific Locks */ + spinlock_t rx_lock; + uint32_t rx_list_post_index; + list_sts rx_list_sts[DMA_ENGINE_CNT]; + crystalhd_dioq_t *rx_rdyq; + crystalhd_dioq_t *rx_freeq; + crystalhd_dioq_t *rx_actq; + uint32_t stop_pending; + + /* HW counters.. */ + struct crystalhd_hw_stats stats; + + /* Core clock in MHz */ + uint32_t core_clock_mhz; + uint32_t prev_n; + uint32_t pwr_lock; +}; + +/* Clock defines for power control */ +#define CLOCK_PRESET 175 + +/* DMA engine register BIT mask wrappers.. */ +#define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK + +#define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \ + INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \ + INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \ + INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \ + INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \ + INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \ + INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \ + INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) + +#define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) + +#define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) + +#define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ + MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) + +#define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ + MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) + + +/**** API Exposed to the other layers ****/ +BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp, + void *buffer, uint32_t sz); +BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd); +bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, struct crystalhd_hw *hw); +BC_STATUS crystalhd_hw_open(struct crystalhd_hw *, struct crystalhd_adp *); +BC_STATUS crystalhd_hw_close(struct crystalhd_hw *); +BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *); +BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *); + + +BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, crystalhd_dio_req *ioreq, + hw_comp_callback call_back, + wait_queue_head_t *cb_event, + uint32_t *list_id, uint8_t data_flags); + +BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw); +BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw); +BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw); +BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id); +BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw, + crystalhd_dio_req *ioreq, bool en_post); +BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw, + BC_PIC_INFO_BLOCK *pib, + crystalhd_dio_req **ioreq); +BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw); +BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw); +void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats); + +/* API to program the core clock on the decoder */ +BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *); + +#endif diff --git a/drivers/staging/crystalhd/crystalhd_lnx.c b/drivers/staging/crystalhd/crystalhd_lnx.c new file mode 100644 index 000000000000..1f36b4db6fce --- /dev/null +++ b/drivers/staging/crystalhd/crystalhd_lnx.c @@ -0,0 +1,780 @@ +/*************************************************************************** + * Copyright (c) 2005-2009, Broadcom Corporation. + * + * Name: crystalhd_lnx . c + * + * Description: + * BCM70010 Linux driver + * + * HISTORY: + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#include + +#include "crystalhd_lnx.h" + +static struct class *crystalhd_class; + +static struct crystalhd_adp *g_adp_info; + +static irqreturn_t chd_dec_isr(int irq, void *arg) +{ + struct crystalhd_adp *adp = (struct crystalhd_adp *) arg; + int rc = 0; + if (adp) + rc = crystalhd_cmd_interrupt(&adp->cmds); + + return IRQ_RETVAL(rc); +} + +static int chd_dec_enable_int(struct crystalhd_adp *adp) +{ + int rc = 0; + + if (!adp || !adp->pdev) { + BCMLOG_ERR("Invalid arg!!\n"); + return -EINVAL; + } + + if (adp->pdev->msi_enabled) + adp->msi = 1; + else + adp->msi = pci_enable_msi(adp->pdev); + + rc = request_irq(adp->pdev->irq, chd_dec_isr, IRQF_SHARED, + adp->name, (void *)adp); + if (rc) { + BCMLOG_ERR("Interrupt request failed.. \n"); + pci_disable_msi(adp->pdev); + } + + return rc; +} + +static int chd_dec_disable_int(struct crystalhd_adp *adp) +{ + if (!adp || !adp->pdev) { + BCMLOG_ERR("Invalid arg!!\n"); + return -EINVAL; + } + + free_irq(adp->pdev->irq, adp); + + if (adp->msi) + pci_disable_msi(adp->pdev); + + return 0; +} + +crystalhd_ioctl_data *chd_dec_alloc_iodata(struct crystalhd_adp *adp, bool isr) +{ + unsigned long flags = 0; + crystalhd_ioctl_data *temp; + + if (!adp) + return NULL; + + spin_lock_irqsave(&adp->lock, flags); + + temp = adp->idata_free_head; + if (temp) { + adp->idata_free_head = adp->idata_free_head->next; + memset(temp, 0, sizeof(*temp)); + } + + spin_unlock_irqrestore(&adp->lock, flags); + return temp; +} + +void chd_dec_free_iodata(struct crystalhd_adp *adp, crystalhd_ioctl_data *iodata, + bool isr) +{ + unsigned long flags = 0; + + if (!adp || !iodata) + return; + + spin_lock_irqsave(&adp->lock, flags); + iodata->next = adp->idata_free_head; + adp->idata_free_head = iodata; + spin_unlock_irqrestore(&adp->lock, flags); +} + +static inline int crystalhd_user_data(unsigned long ud, void *dr, int size, int set) +{ + int rc; + + if (!ud || !dr) { + BCMLOG_ERR("Invalid arg \n"); + return -EINVAL; + } + + if (set) + rc = copy_to_user((void *)ud, dr, size); + else + rc = copy_from_user(dr, (void *)ud, size); + + if (rc) { + BCMLOG_ERR("Invalid args for command \n"); + rc = -EFAULT; + } + + return rc; +} + +static int chd_dec_fetch_cdata(struct crystalhd_adp *adp, crystalhd_ioctl_data *io, + uint32_t m_sz, unsigned long ua) +{ + unsigned long ua_off; + int rc = 0; + + if (!adp || !io || !ua || !m_sz) { + BCMLOG_ERR("Invalid Arg!!\n"); + return -EINVAL; + } + + io->add_cdata = vmalloc(m_sz); + if (!io->add_cdata) { + BCMLOG_ERR("kalloc fail for sz:%x\n", m_sz); + return -ENOMEM; + } + + io->add_cdata_sz = m_sz; + ua_off = ua + sizeof(io->udata); + rc = crystalhd_user_data(ua_off, io->add_cdata, io->add_cdata_sz, 0); + if (rc) { + BCMLOG_ERR("failed to pull add_cdata sz:%x ua_off:%x\n", + io->add_cdata_sz, (unsigned int)ua_off); + if (io->add_cdata) { + kfree(io->add_cdata); + io->add_cdata = NULL; + } + return -ENODATA; + } + + return rc; +} + +static int chd_dec_release_cdata(struct crystalhd_adp *adp, + crystalhd_ioctl_data *io, unsigned long ua) +{ + unsigned long ua_off; + int rc; + + if (!adp || !io || !ua) { + BCMLOG_ERR("Invalid Arg!!\n"); + return -EINVAL; + } + + if (io->cmd != BCM_IOC_FW_DOWNLOAD) { + ua_off = ua + sizeof(io->udata); + rc = crystalhd_user_data(ua_off, io->add_cdata, + io->add_cdata_sz, 1); + if (rc) { + BCMLOG_ERR("failed to push add_cdata sz:%x ua_off:%x\n", + io->add_cdata_sz, (unsigned int)ua_off); + return -ENODATA; + } + } + + if (io->add_cdata) { + vfree(io->add_cdata); + io->add_cdata = NULL; + } + + return 0; +} + +static int chd_dec_proc_user_data(struct crystalhd_adp *adp, + crystalhd_ioctl_data *io, + unsigned long ua, int set) +{ + int rc; + uint32_t m_sz = 0; + + if (!adp || !io || !ua) { + BCMLOG_ERR("Invalid Arg!!\n"); + return -EINVAL; + } + + rc = crystalhd_user_data(ua, &io->udata, sizeof(io->udata), set); + if (rc) { + BCMLOG_ERR("failed to %s iodata \n", (set ? "set" : "get")); + return rc; + } + + switch (io->cmd) { + case BCM_IOC_MEM_RD: + case BCM_IOC_MEM_WR: + case BCM_IOC_FW_DOWNLOAD: + m_sz = io->udata.u.devMem.NumDwords * 4; + if (set) + rc = chd_dec_release_cdata(adp, io, ua); + else + rc = chd_dec_fetch_cdata(adp, io, m_sz, ua); + break; + default: + break; + } + + return rc; +} + +static int chd_dec_api_cmd(struct crystalhd_adp *adp, unsigned long ua, + uint32_t uid, uint32_t cmd, crystalhd_cmd_proc func) +{ + int rc; + crystalhd_ioctl_data *temp; + BC_STATUS sts = BC_STS_SUCCESS; + + temp = chd_dec_alloc_iodata(adp, 0); + if (!temp) { + BCMLOG_ERR("Failed to get iodata..\n"); + return -EINVAL; + } + + temp->u_id = uid; + temp->cmd = cmd; + + rc = chd_dec_proc_user_data(adp, temp, ua, 0); + if (!rc) { + sts = func(&adp->cmds, temp); + if (sts == BC_STS_PENDING) + sts = BC_STS_NOT_IMPL; + temp->udata.RetSts = sts; + rc = chd_dec_proc_user_data(adp, temp, ua, 1); + } + + if (temp) { + chd_dec_free_iodata(adp, temp, 0); + temp = NULL; + } + + return rc; +} + +/* ========================= API interfaces =================================*/ +static int chd_dec_ioctl(struct inode *in, struct file *fd, + unsigned int cmd, unsigned long ua) +{ + struct crystalhd_adp *adp = chd_get_adp(); + crystalhd_cmd_proc cproc; + struct crystalhd_user *uc; + + if (!adp || !fd) { + BCMLOG_ERR("Invalid adp\n"); + return -EINVAL; + } + + uc = (struct crystalhd_user *)fd->private_data; + if (!uc) { + BCMLOG_ERR("Failed to get uc\n"); + return -ENODATA; + } + + cproc = crystalhd_get_cmd_proc(&adp->cmds, cmd, uc); + if (!cproc) { + BCMLOG_ERR("Unhandled command: %d\n", cmd); + return -EINVAL; + } + + return chd_dec_api_cmd(adp, ua, uc->uid, cmd, cproc); +} + +static int chd_dec_open(struct inode *in, struct file *fd) +{ + struct crystalhd_adp *adp = chd_get_adp(); + int rc = 0; + BC_STATUS sts = BC_STS_SUCCESS; + struct crystalhd_user *uc = NULL; + + BCMLOG_ENTER; + if (!adp) { + BCMLOG_ERR("Invalid adp\n"); + return -EINVAL; + } + + if (adp->cfg_users >= BC_LINK_MAX_OPENS) { + BCMLOG(BCMLOG_INFO, "Already in use.%d\n", adp->cfg_users); + return -EBUSY; + } + + sts = crystalhd_user_open(&adp->cmds, &uc); + if (sts != BC_STS_SUCCESS) { + BCMLOG_ERR("cmd_user_open - %d \n", sts); + rc = -EBUSY; + } + + adp->cfg_users++; + + fd->private_data = uc; + + return rc; +} + +static int chd_dec_close(struct inode *in, struct file *fd) +{ + struct crystalhd_adp *adp = chd_get_adp(); + struct crystalhd_user *uc; + + BCMLOG_ENTER; + if (!adp) { + BCMLOG_ERR("Invalid adp \n"); + return -EINVAL; + } + + uc = (struct crystalhd_user *)fd->private_data; + if (!uc) { + BCMLOG_ERR("Failed to get uc\n"); + return -ENODATA; + } + + crystalhd_user_close(&adp->cmds, uc); + + adp->cfg_users--; + + return 0; +} + +static const struct file_operations chd_dec_fops = { + .owner = THIS_MODULE, + .ioctl = chd_dec_ioctl, + .open = chd_dec_open, + .release = chd_dec_close, +}; + +static int chd_dec_init_chdev(struct crystalhd_adp *adp) +{ + crystalhd_ioctl_data *temp; + struct device *dev; + int rc = -ENODEV, i = 0; + + if (!adp) + goto fail; + + adp->chd_dec_major = register_chrdev(0, CRYSTALHD_API_NAME, + &chd_dec_fops); + if (adp->chd_dec_major < 0) { + BCMLOG_ERR("Failed to create config dev\n"); + rc = adp->chd_dec_major; + goto fail; + } + + /* register crystalhd class */ + crystalhd_class = class_create(THIS_MODULE, "crystalhd"); + if (IS_ERR(crystalhd_class)) { + BCMLOG_ERR("failed to create class\n"); + goto fail; + } + + dev = device_create(crystalhd_class, NULL, MKDEV(adp->chd_dec_major, 0), + NULL, "crystalhd"); + if (!dev) { + BCMLOG_ERR("failed to create device\n"); + goto device_create_fail; + } + + rc = crystalhd_create_elem_pool(adp, BC_LINK_ELEM_POOL_SZ); + if (rc) { + BCMLOG_ERR("failed to create device\n"); + goto elem_pool_fail; + } + + /* Allocate general purpose ioctl pool. */ + for (i = 0; i < CHD_IODATA_POOL_SZ; i++) { + /* FIXME: jarod: why atomic? */ + temp = kzalloc(sizeof(crystalhd_ioctl_data), GFP_ATOMIC); + if (!temp) { + BCMLOG_ERR("ioctl data pool kzalloc failed\n"); + rc = -ENOMEM; + goto kzalloc_fail; + } + /* Add to global pool.. */ + chd_dec_free_iodata(adp, temp, 0); + } + + return 0; + +kzalloc_fail: + crystalhd_delete_elem_pool(adp); +elem_pool_fail: + device_destroy(crystalhd_class, MKDEV(adp->chd_dec_major, 0)); +device_create_fail: + class_destroy(crystalhd_class); +fail: + return rc; +} + +static void chd_dec_release_chdev(struct crystalhd_adp *adp) +{ + crystalhd_ioctl_data *temp = NULL; + if (!adp) + return; + + if (adp->chd_dec_major > 0) { + /* unregister crystalhd class */ + device_destroy(crystalhd_class, MKDEV(adp->chd_dec_major, 0)); + unregister_chrdev(adp->chd_dec_major, CRYSTALHD_API_NAME); + BCMLOG(BCMLOG_INFO, "released api device - %d\n", + adp->chd_dec_major); + class_destroy(crystalhd_class); + } + adp->chd_dec_major = 0; + + /* Clear iodata pool.. */ + do { + temp = chd_dec_alloc_iodata(adp, 0); + if (temp) + kfree(temp); + } while (temp); + + crystalhd_delete_elem_pool(adp); +} + +static int chd_pci_reserve_mem(struct crystalhd_adp *pinfo) +{ + int rc; + unsigned long bar2 = pci_resource_start(pinfo->pdev, 2); + uint32_t mem_len = pci_resource_len(pinfo->pdev, 2); + unsigned long bar0 = pci_resource_start(pinfo->pdev, 0); + uint32_t i2o_len = pci_resource_len(pinfo->pdev, 0); + + BCMLOG(BCMLOG_SSTEP, "bar2:0x%lx-0x%08x bar0:0x%lx-0x%08x\n", + bar2, mem_len, bar0, i2o_len); + + rc = check_mem_region(bar2, mem_len); + if (rc) { + BCMLOG_ERR("No valid mem region...\n"); + return -ENOMEM; + } + + pinfo->addr = ioremap_nocache(bar2, mem_len); + if (!pinfo->addr) { + BCMLOG_ERR("Failed to remap mem region...\n"); + return -ENOMEM; + } + + pinfo->pci_mem_start = bar2; + pinfo->pci_mem_len = mem_len; + + rc = check_mem_region(bar0, i2o_len); + if (rc) { + BCMLOG_ERR("No valid mem region...\n"); + return -ENOMEM; + } + + pinfo->i2o_addr = ioremap_nocache(bar0, i2o_len); + if (!pinfo->i2o_addr) { + BCMLOG_ERR("Failed to remap mem region...\n"); + return -ENOMEM; + } + + pinfo->pci_i2o_start = bar0; + pinfo->pci_i2o_len = i2o_len; + + rc = pci_request_regions(pinfo->pdev, pinfo->name); + if (rc < 0) { + BCMLOG_ERR("Region request failed: %d\n", rc); + return rc; + } + + BCMLOG(BCMLOG_SSTEP, "Mapped addr:0x%08lx i2o_addr:0x%08lx\n", + (unsigned long)pinfo->addr, (unsigned long)pinfo->i2o_addr); + + return 0; +} + +static void chd_pci_release_mem(struct crystalhd_adp *pinfo) +{ + if (!pinfo) + return; + + if (pinfo->addr) + iounmap(pinfo->addr); + + if (pinfo->i2o_addr) + iounmap(pinfo->i2o_addr); + + pci_release_regions(pinfo->pdev); +} + + +static void chd_dec_pci_remove(struct pci_dev *pdev) +{ + struct crystalhd_adp *pinfo; + BC_STATUS sts = BC_STS_SUCCESS; + + BCMLOG_ENTER; + + pinfo = (struct crystalhd_adp *) pci_get_drvdata(pdev); + if (!pinfo) { + BCMLOG_ERR("could not get adp\n"); + return; + } + + sts = crystalhd_delete_cmd_context(&pinfo->cmds); + if (sts != BC_STS_SUCCESS) + BCMLOG_ERR("cmd delete :%d \n", sts); + + chd_dec_release_chdev(pinfo); + + chd_dec_disable_int(pinfo); + + chd_pci_release_mem(pinfo); + pci_disable_device(pinfo->pdev); + + kfree(pinfo); + g_adp_info = NULL; +} + +static int chd_dec_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *entry) +{ + struct crystalhd_adp *pinfo; + int rc; + BC_STATUS sts = BC_STS_SUCCESS; + + BCMLOG(BCMLOG_DBG, "PCI_INFO: Vendor:0x%04x Device:0x%04x " + "s_vendor:0x%04x s_device: 0x%04x\n", + pdev->vendor, pdev->device, pdev->subsystem_vendor, + pdev->subsystem_device); + + /* FIXME: jarod: why atomic? */ + pinfo = kzalloc(sizeof(struct crystalhd_adp), GFP_ATOMIC); + if (!pinfo) { + BCMLOG_ERR("Failed to allocate memory\n"); + return -ENOMEM; + } + + pinfo->pdev = pdev; + + rc = pci_enable_device(pdev); + if (rc) { + BCMLOG_ERR("Failed to enable PCI device\n"); + return rc; + } + + snprintf(pinfo->name, 31, "crystalhd_pci_e:%d:%d:%d", + pdev->bus->number, PCI_SLOT(pdev->devfn), + PCI_FUNC(pdev->devfn)); + + rc = chd_pci_reserve_mem(pinfo); + if (rc) { + BCMLOG_ERR("Failed to setup memory regions.\n"); + return -ENOMEM; + } + + pinfo->present = 1; + pinfo->drv_data = entry->driver_data; + + /* Setup adapter level lock.. */ + spin_lock_init(&pinfo->lock); + + /* setup api stuff.. */ + chd_dec_init_chdev(pinfo); + rc = chd_dec_enable_int(pinfo); + if (rc) { + BCMLOG_ERR("_enable_int err:%d \n", rc); + pci_disable_device(pdev); + return -ENODEV; + } + + /* Set dma mask... */ + if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { + pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); + pinfo->dmabits = 64; + } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { + pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + pinfo->dmabits = 32; + } else { + BCMLOG_ERR("Unabled to setup DMA %d\n", rc); + pci_disable_device(pdev); + return -ENODEV; + } + + sts = crystalhd_setup_cmd_context(&pinfo->cmds, pinfo); + if (sts != BC_STS_SUCCESS) { + BCMLOG_ERR("cmd setup :%d \n", sts); + pci_disable_device(pdev); + return -ENODEV; + } + + pci_set_master(pdev); + + pci_set_drvdata(pdev, pinfo); + + g_adp_info = pinfo; + + return 0; + +} + +#ifdef CONFIG_PM +int chd_dec_pci_suspend(struct pci_dev *pdev, pm_message_t state) +{ + struct crystalhd_adp *adp; + crystalhd_ioctl_data *temp; + BC_STATUS sts = BC_STS_SUCCESS; + + adp = (struct crystalhd_adp *)pci_get_drvdata(pdev); + if (!adp) { + BCMLOG_ERR("could not get adp\n"); + return -ENODEV; + } + + temp = chd_dec_alloc_iodata(adp, false); + if (!temp) { + BCMLOG_ERR("could not get ioctl data\n"); + return -ENODEV; + } + + sts = crystalhd_suspend(&adp->cmds, temp); + if (sts != BC_STS_SUCCESS) { + BCMLOG_ERR("BCM70012 Suspend %d\n", sts); + return -ENODEV; + } + + chd_dec_free_iodata(adp, temp, false); + chd_dec_disable_int(adp); + pci_save_state(pdev); + + /* Disable IO/bus master/irq router */ + pci_disable_device(pdev); + pci_set_power_state(pdev, pci_choose_state(pdev, state)); + return 0; +} + +int chd_dec_pci_resume(struct pci_dev *pdev) +{ + struct crystalhd_adp *adp; + BC_STATUS sts = BC_STS_SUCCESS; + int rc; + + adp = (struct crystalhd_adp *)pci_get_drvdata(pdev); + if (!adp) { + BCMLOG_ERR("could not get adp\n"); + return -ENODEV; + } + + pci_set_power_state(pdev, PCI_D0); + pci_restore_state(pdev); + + /* device's irq possibly is changed, driver should take care */ + if (pci_enable_device(pdev)) { + BCMLOG_ERR("Failed to enable PCI device\n"); + return 1; + } + + pci_set_master(pdev); + + rc = chd_dec_enable_int(adp); + if (rc) { + BCMLOG_ERR("_enable_int err:%d \n", rc); + pci_disable_device(pdev); + return -ENODEV; + } + + sts = crystalhd_resume(&adp->cmds); + if (sts != BC_STS_SUCCESS) { + BCMLOG_ERR("BCM70012 Resume %d\n", sts); + pci_disable_device(pdev); + return -ENODEV; + } + + return 0; +} +#endif + +static struct pci_device_id chd_dec_pci_id_table[] = { +/* vendor, device, subvendor, subdevice, class, classmask, driver_data */ + { 0x14e4, 0x1612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 }, + { 0, }, +}; + +struct pci_driver bc_chd_70012_driver = { + .name = "Broadcom 70012 Decoder", + .probe = chd_dec_pci_probe, + .remove = chd_dec_pci_remove, + .id_table = chd_dec_pci_id_table, +#ifdef CONFIG_PM + .suspend = chd_dec_pci_suspend, + .resume = chd_dec_pci_resume +#endif +}; +MODULE_DEVICE_TABLE(pci, chd_dec_pci_id_table); + + +void chd_set_log_level(struct crystalhd_adp *adp, char *arg) +{ + if ((!arg) || (strlen(arg) < 3)) + g_linklog_level = BCMLOG_ERROR | BCMLOG_DATA; + else if (!strncmp(arg, "sstep", 5)) + g_linklog_level = BCMLOG_INFO | BCMLOG_DATA | BCMLOG_DBG | + BCMLOG_SSTEP | BCMLOG_ERROR; + else if (!strncmp(arg, "info", 4)) + g_linklog_level = BCMLOG_ERROR | BCMLOG_DATA | BCMLOG_INFO; + else if (!strncmp(arg, "debug", 5)) + g_linklog_level = BCMLOG_ERROR | BCMLOG_DATA | BCMLOG_INFO | + BCMLOG_DBG; + else if (!strncmp(arg, "pball", 5)) + g_linklog_level = 0xFFFFFFFF & ~(BCMLOG_SPINLOCK); + else if (!strncmp(arg, "silent", 6)) + g_linklog_level = 0; + else + g_linklog_level = 0; +} + +struct crystalhd_adp *chd_get_adp(void) +{ + return g_adp_info; +} + +int __init chd_dec_module_init(void) +{ + int rc; + + chd_set_log_level(NULL, "debug"); + BCMLOG(BCMLOG_DATA, "Loading crystalhd %d.%d.%d \n", + crystalhd_kmod_major, crystalhd_kmod_minor, crystalhd_kmod_rev); + + rc = pci_register_driver(&bc_chd_70012_driver); + + if (rc < 0) + BCMLOG_ERR("Could not find any devices. err:%d \n", rc); + + return rc; +} + +void __exit chd_dec_module_cleanup(void) +{ + BCMLOG(BCMLOG_DATA, "unloading crystalhd %d.%d.%d \n", + crystalhd_kmod_major, crystalhd_kmod_minor, crystalhd_kmod_rev); + + pci_unregister_driver(&bc_chd_70012_driver); +} + + +MODULE_AUTHOR("Naren Sankar "); +MODULE_AUTHOR("Prasad Bolisetty "); +MODULE_DESCRIPTION(CRYSTAL_HD_NAME); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("bcm70012"); + +module_init(chd_dec_module_init); +module_exit(chd_dec_module_cleanup); + diff --git a/drivers/staging/crystalhd/crystalhd_lnx.h b/drivers/staging/crystalhd/crystalhd_lnx.h new file mode 100644 index 000000000000..d3f9fc43d2d4 --- /dev/null +++ b/drivers/staging/crystalhd/crystalhd_lnx.h @@ -0,0 +1,95 @@ +/*************************************************************************** + * Copyright (c) 2005-2009, Broadcom Corporation. + * + * Name: crystalhd_lnx . c + * + * Description: + * BCM70012 Linux driver + * + * HISTORY: + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#ifndef _CRYSTALHD_LNX_H_ +#define _CRYSTALHD_LNX_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "crystalhd_cmds.h" + +#define CRYSTAL_HD_NAME "Broadcom Crystal HD Decoder (BCM70012) Driver" + + +/* OS specific PCI information structure and adapter information. */ +struct crystalhd_adp { + /* Hardware borad/PCI specifics */ + char name[32]; + struct pci_dev *pdev; + + unsigned long pci_mem_start; + uint32_t pci_mem_len; + void *addr; + + unsigned long pci_i2o_start; + uint32_t pci_i2o_len; + void *i2o_addr; + + unsigned int drv_data; + unsigned int dmabits; /* 32 | 64 */ + unsigned int registered; + unsigned int present; + unsigned int msi; + + spinlock_t lock; + + /* API Related */ + unsigned int chd_dec_major; + unsigned int cfg_users; + + crystalhd_ioctl_data *idata_free_head; /* ioctl data pool */ + crystalhd_elem_t *elem_pool_head; /* Queue element pool */ + + struct crystalhd_cmd cmds; + + crystalhd_dio_req *ua_map_free_head; + struct pci_pool *fill_byte_pool; +}; + + +struct crystalhd_adp *chd_get_adp(void); +void chd_set_log_level(struct crystalhd_adp *adp, char *arg); + +#endif + diff --git a/drivers/staging/crystalhd/crystalhd_misc.c b/drivers/staging/crystalhd/crystalhd_misc.c new file mode 100644 index 000000000000..32e632c2ab3e --- /dev/null +++ b/drivers/staging/crystalhd/crystalhd_misc.c @@ -0,0 +1,1029 @@ +/*************************************************************************** + * Copyright (c) 2005-2009, Broadcom Corporation. + * + * Name: crystalhd_misc . c + * + * Description: + * BCM70012 Linux driver misc routines. + * + * HISTORY: + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#include "crystalhd_misc.h" +#include "crystalhd_lnx.h" + +uint32_t g_linklog_level; + +static inline uint32_t crystalhd_dram_rd(struct crystalhd_adp *adp, uint32_t mem_off) +{ + crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (mem_off >> 19)); + return bc_dec_reg_rd(adp, (0x00380000 | (mem_off & 0x0007FFFF))); +} + +static inline void crystalhd_dram_wr(struct crystalhd_adp *adp, uint32_t mem_off, uint32_t val) +{ + crystalhd_reg_wr(adp, DCI_DRAM_BASE_ADDR, (mem_off >> 19)); + bc_dec_reg_wr(adp, (0x00380000 | (mem_off & 0x0007FFFF)), val); +} + +static inline BC_STATUS bc_chk_dram_range(struct crystalhd_adp *adp, uint32_t start_off, uint32_t cnt) +{ + return BC_STS_SUCCESS; +} + +static crystalhd_dio_req *crystalhd_alloc_dio(struct crystalhd_adp *adp) +{ + unsigned long flags = 0; + crystalhd_dio_req *temp = NULL; + + if (!adp) { + BCMLOG_ERR("Invalid Arg!!\n"); + return temp; + } + + spin_lock_irqsave(&adp->lock, flags); + temp = adp->ua_map_free_head; + if (temp) + adp->ua_map_free_head = adp->ua_map_free_head->next; + spin_unlock_irqrestore(&adp->lock, flags); + + return temp; +} + +static void crystalhd_free_dio(struct crystalhd_adp *adp, crystalhd_dio_req *dio) +{ + unsigned long flags = 0; + + if (!adp || !dio) + return; + spin_lock_irqsave(&adp->lock, flags); + dio->sig = crystalhd_dio_inv; + dio->page_cnt = 0; + dio->fb_size = 0; + memset(&dio->uinfo, 0, sizeof(dio->uinfo)); + dio->next = adp->ua_map_free_head; + adp->ua_map_free_head = dio; + spin_unlock_irqrestore(&adp->lock, flags); +} + +static crystalhd_elem_t *crystalhd_alloc_elem(struct crystalhd_adp *adp) +{ + unsigned long flags = 0; + crystalhd_elem_t *temp = NULL; + + if (!adp) + return temp; + spin_lock_irqsave(&adp->lock, flags); + temp = adp->elem_pool_head; + if (temp) { + adp->elem_pool_head = adp->elem_pool_head->flink; + memset(temp, 0, sizeof(*temp)); + } + spin_unlock_irqrestore(&adp->lock, flags); + + return temp; +} +static void crystalhd_free_elem(struct crystalhd_adp *adp, crystalhd_elem_t *elem) +{ + unsigned long flags = 0; + + if (!adp || !elem) + return; + spin_lock_irqsave(&adp->lock, flags); + elem->flink = adp->elem_pool_head; + adp->elem_pool_head = elem; + spin_unlock_irqrestore(&adp->lock, flags); +} + +static inline void crystalhd_set_sg(struct scatterlist *sg, struct page *page, + unsigned int len, unsigned int offset) +{ + sg_set_page(sg, page, len, offset); +#ifdef CONFIG_X86_64 + sg->dma_length = len; +#endif +} + +static inline void crystalhd_init_sg(struct scatterlist *sg, unsigned int entries) +{ + /* http://lkml.org/lkml/2007/11/27/68 */ + sg_init_table(sg, entries); +} + +/*========================== Extern ========================================*/ +/** + * bc_dec_reg_rd - Read 7412's device register. + * @adp: Adapter instance + * @reg_off: Register offset. + * + * Return: + * 32bit value read + * + * 7412's device register read routine. This interface use + * 7412's device access range mapped from BAR-2 (4M) of PCIe + * configuration space. + */ +uint32_t bc_dec_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) +{ + if (!adp || (reg_off > adp->pci_mem_len)) { + BCMLOG_ERR("dec_rd_reg_off outof range: 0x%08x\n", reg_off); + return 0; + } + + return readl(adp->addr + reg_off); +} + +/** + * bc_dec_reg_wr - Write 7412's device register + * @adp: Adapter instance + * @reg_off: Register offset. + * @val: Dword value to be written. + * + * Return: + * none. + * + * 7412's device register write routine. This interface use + * 7412's device access range mapped from BAR-2 (4M) of PCIe + * configuration space. + */ +void bc_dec_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val) +{ + if (!adp || (reg_off > adp->pci_mem_len)) { + BCMLOG_ERR("dec_wr_reg_off outof range: 0x%08x\n", reg_off); + return; + } + writel(val, adp->addr + reg_off); + udelay(8); +} + +/** + * crystalhd_reg_rd - Read Link's device register. + * @adp: Adapter instance + * @reg_off: Register offset. + * + * Return: + * 32bit value read + * + * Link device register read routine. This interface use + * Link's device access range mapped from BAR-1 (64K) of PCIe + * configuration space. + * + */ +uint32_t crystalhd_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) +{ + if (!adp || (reg_off > adp->pci_i2o_len)) { + BCMLOG_ERR("link_rd_reg_off outof range: 0x%08x\n", reg_off); + return 0; + } + return readl(adp->i2o_addr + reg_off); +} + +/** + * crystalhd_reg_wr - Write Link's device register + * @adp: Adapter instance + * @reg_off: Register offset. + * @val: Dword value to be written. + * + * Return: + * none. + * + * Link device register write routine. This interface use + * Link's device access range mapped from BAR-1 (64K) of PCIe + * configuration space. + * + */ +void crystalhd_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val) +{ + if (!adp || (reg_off > adp->pci_i2o_len)) { + BCMLOG_ERR("link_wr_reg_off outof range: 0x%08x\n", reg_off); + return; + } + writel(val, adp->i2o_addr + reg_off); +} + +/** + * crystalhd_mem_rd - Read data from 7412's DRAM area. + * @adp: Adapter instance + * @start_off: Start offset. + * @dw_cnt: Count in dwords. + * @rd_buff: Buffer to copy the data from dram. + * + * Return: + * Status. + * + * 7412's Dram read routine. + */ +BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *adp, uint32_t start_off, + uint32_t dw_cnt, uint32_t *rd_buff) +{ + uint32_t ix = 0; + + if (!adp || !rd_buff || + (bc_chk_dram_range(adp, start_off, dw_cnt) != BC_STS_SUCCESS)) { + BCMLOG_ERR("Invalid arg \n"); + return BC_STS_INV_ARG; + } + for (ix = 0; ix < dw_cnt; ix++) + rd_buff[ix] = crystalhd_dram_rd(adp, (start_off + (ix * 4))); + + return BC_STS_SUCCESS; +} + +/** + * crystalhd_mem_wr - Write data to 7412's DRAM area. + * @adp: Adapter instance + * @start_off: Start offset. + * @dw_cnt: Count in dwords. + * @wr_buff: Data Buffer to be written. + * + * Return: + * Status. + * + * 7412's Dram write routine. + */ +BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *adp, uint32_t start_off, + uint32_t dw_cnt, uint32_t *wr_buff) +{ + uint32_t ix = 0; + + if (!adp || !wr_buff || + (bc_chk_dram_range(adp, start_off, dw_cnt) != BC_STS_SUCCESS)) { + BCMLOG_ERR("Invalid arg \n"); + return BC_STS_INV_ARG; + } + + for (ix = 0; ix < dw_cnt; ix++) + crystalhd_dram_wr(adp, (start_off + (ix * 4)), wr_buff[ix]); + + return BC_STS_SUCCESS; +} +/** + * crystalhd_pci_cfg_rd - PCIe config read + * @adp: Adapter instance + * @off: PCI config space offset. + * @len: Size -- Byte, Word & dword. + * @val: Value read + * + * Return: + * Status. + * + * Get value from Link's PCIe config space. + */ +BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *adp, uint32_t off, + uint32_t len, uint32_t *val) +{ + BC_STATUS sts = BC_STS_SUCCESS; + int rc = 0; + + if (!adp || !val) { + BCMLOG_ERR("Invalid arg \n"); + return BC_STS_INV_ARG; + } + + switch (len) { + case 1: + rc = pci_read_config_byte(adp->pdev, off, (u8 *)val); + break; + case 2: + rc = pci_read_config_word(adp->pdev, off, (u16 *)val); + break; + case 4: + rc = pci_read_config_dword(adp->pdev, off, (u32 *)val); + break; + default: + rc = -EINVAL; + sts = BC_STS_INV_ARG; + BCMLOG_ERR("Invalid len:%d\n", len); + }; + + if (rc && (sts == BC_STS_SUCCESS)) + sts = BC_STS_ERROR; + + return sts; +} + +/** + * crystalhd_pci_cfg_wr - PCIe config write + * @adp: Adapter instance + * @off: PCI config space offset. + * @len: Size -- Byte, Word & dword. + * @val: Value to be written + * + * Return: + * Status. + * + * Set value to Link's PCIe config space. + */ +BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *adp, uint32_t off, + uint32_t len, uint32_t val) +{ + BC_STATUS sts = BC_STS_SUCCESS; + int rc = 0; + + if (!adp || !val) { + BCMLOG_ERR("Invalid arg \n"); + return BC_STS_INV_ARG; + } + + switch (len) { + case 1: + rc = pci_write_config_byte(adp->pdev, off, (u8)val); + break; + case 2: + rc = pci_write_config_word(adp->pdev, off, (u16)val); + break; + case 4: + rc = pci_write_config_dword(adp->pdev, off, val); + break; + default: + rc = -EINVAL; + sts = BC_STS_INV_ARG; + BCMLOG_ERR("Invalid len:%d\n", len); + }; + + if (rc && (sts == BC_STS_SUCCESS)) + sts = BC_STS_ERROR; + + return sts; +} + +/** + * bc_kern_dma_alloc - Allocate memory for Dma rings + * @adp: Adapter instance + * @sz: Size of the memory to allocate. + * @phy_addr: Physical address of the memory allocated. + * Typedef to system's dma_addr_t (u64) + * + * Return: + * Pointer to allocated memory.. + * + * Wrapper to Linux kernel interface. + * + */ +void *bc_kern_dma_alloc(struct crystalhd_adp *adp, uint32_t sz, + dma_addr_t *phy_addr) +{ + void *temp = NULL; + + if (!adp || !sz || !phy_addr) { + BCMLOG_ERR("Invalide Arg..\n"); + return temp; + } + + temp = pci_alloc_consistent(adp->pdev, sz, phy_addr); + if (temp) + memset(temp, 0, sz); + + return temp; +} + +/** + * bc_kern_dma_free - Release Dma ring memory. + * @adp: Adapter instance + * @sz: Size of the memory to allocate. + * @ka: Kernel virtual address returned during _dio_alloc() + * @phy_addr: Physical address of the memory allocated. + * Typedef to system's dma_addr_t (u64) + * + * Return: + * none. + */ +void bc_kern_dma_free(struct crystalhd_adp *adp, uint32_t sz, void *ka, + dma_addr_t phy_addr) +{ + if (!adp || !ka || !sz || !phy_addr) { + BCMLOG_ERR("Invalide Arg..\n"); + return; + } + + pci_free_consistent(adp->pdev, sz, ka, phy_addr); +} + +/** + * crystalhd_create_dioq - Create Generic DIO queue + * @adp: Adapter instance + * @dioq_hnd: Handle to the dio queue created + * @cb : Optional - Call back To free the element. + * @cbctx: Context to pass to callback. + * + * Return: + * status + * + * Initialize Generic DIO queue to hold any data. Callback + * will be used to free elements while deleting the queue. + */ +BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *adp, + crystalhd_dioq_t **dioq_hnd, + crystalhd_data_free_cb cb, void *cbctx) +{ + crystalhd_dioq_t *dioq = NULL; + + if (!adp || !dioq_hnd) { + BCMLOG_ERR("Invalid arg!!\n"); + return BC_STS_INV_ARG; + } + + dioq = kzalloc(sizeof(*dioq), GFP_KERNEL); + if (!dioq) + return BC_STS_INSUFF_RES; + + spin_lock_init(&dioq->lock); + dioq->sig = BC_LINK_DIOQ_SIG; + dioq->head = (crystalhd_elem_t *)&dioq->head; + dioq->tail = (crystalhd_elem_t *)&dioq->head; + crystalhd_create_event(&dioq->event); + dioq->adp = adp; + dioq->data_rel_cb = cb; + dioq->cb_context = cbctx; + *dioq_hnd = dioq; + + return BC_STS_SUCCESS; +} + +/** + * crystalhd_delete_dioq - Delete Generic DIO queue + * @adp: Adapter instance + * @dioq: DIOQ instance.. + * + * Return: + * None. + * + * Release Generic DIO queue. This function will remove + * all the entries from the Queue and will release data + * by calling the call back provided during creation. + * + */ +void crystalhd_delete_dioq(struct crystalhd_adp *adp, crystalhd_dioq_t *dioq) +{ + void *temp; + + if (!dioq || (dioq->sig != BC_LINK_DIOQ_SIG)) + return; + + do { + temp = crystalhd_dioq_fetch(dioq); + if (temp && dioq->data_rel_cb) + dioq->data_rel_cb(dioq->cb_context, temp); + } while (temp); + dioq->sig = 0; + kfree(dioq); +} + +/** + * crystalhd_dioq_add - Add new DIO request element. + * @ioq: DIO queue instance + * @t: DIO request to be added. + * @wake: True - Wake up suspended process. + * @tag: Special tag to assign - For search and get. + * + * Return: + * Status. + * + * Insert new element to Q tail. + */ +BC_STATUS crystalhd_dioq_add(crystalhd_dioq_t *ioq, void *data, + bool wake, uint32_t tag) +{ + unsigned long flags = 0; + crystalhd_elem_t *tmp; + + if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG) || !data) { + BCMLOG_ERR("Invalid arg!!\n"); + return BC_STS_INV_ARG; + } + + tmp = crystalhd_alloc_elem(ioq->adp); + if (!tmp) { + BCMLOG_ERR("No free elements.\n"); + return BC_STS_INSUFF_RES; + } + + tmp->data = data; + tmp->tag = tag; + spin_lock_irqsave(&ioq->lock, flags); + tmp->flink = (crystalhd_elem_t *)&ioq->head; + tmp->blink = ioq->tail; + tmp->flink->blink = tmp; + tmp->blink->flink = tmp; + ioq->count++; + spin_unlock_irqrestore(&ioq->lock, flags); + + if (wake) + crystalhd_set_event(&ioq->event); + + return BC_STS_SUCCESS; +} + +/** + * crystalhd_dioq_fetch - Fetch element from head. + * @ioq: DIO queue instance + * + * Return: + * data element from the head.. + * + * Remove an element from Queue. + */ +void *crystalhd_dioq_fetch(crystalhd_dioq_t *ioq) +{ + unsigned long flags = 0; + crystalhd_elem_t *tmp; + crystalhd_elem_t *ret = NULL; + void *data = NULL; + + if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG)) { + BCMLOG_ERR("Invalid arg!!\n"); + return data; + } + + spin_lock_irqsave(&ioq->lock, flags); + tmp = ioq->head; + if (tmp != (crystalhd_elem_t *)&ioq->head) { + ret = tmp; + tmp->flink->blink = tmp->blink; + tmp->blink->flink = tmp->flink; + ioq->count--; + } + spin_unlock_irqrestore(&ioq->lock, flags); + if (ret) { + data = ret->data; + crystalhd_free_elem(ioq->adp, ret); + } + + return data; +} +/** + * crystalhd_dioq_find_and_fetch - Search the tag and Fetch element + * @ioq: DIO queue instance + * @tag: Tag to search for. + * + * Return: + * element from the head.. + * + * Search TAG and remove the element. + */ +void *crystalhd_dioq_find_and_fetch(crystalhd_dioq_t *ioq, uint32_t tag) +{ + unsigned long flags = 0; + crystalhd_elem_t *tmp; + crystalhd_elem_t *ret = NULL; + void *data = NULL; + + if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG)) { + BCMLOG_ERR("Invalid arg!!\n"); + return data; + } + + spin_lock_irqsave(&ioq->lock, flags); + tmp = ioq->head; + while (tmp != (crystalhd_elem_t *)&ioq->head) { + if (tmp->tag == tag) { + ret = tmp; + tmp->flink->blink = tmp->blink; + tmp->blink->flink = tmp->flink; + ioq->count--; + break; + } + tmp = tmp->flink; + } + spin_unlock_irqrestore(&ioq->lock, flags); + + if (ret) { + data = ret->data; + crystalhd_free_elem(ioq->adp, ret); + } + + return data; +} + +/** + * crystalhd_dioq_fetch_wait - Fetch element from Head. + * @ioq: DIO queue instance + * @to_secs: Wait timeout in seconds.. + * + * Return: + * element from the head.. + * + * Return element from head if Q is not empty. Wait for new element + * if Q is empty for Timeout seconds. + */ +void *crystalhd_dioq_fetch_wait(crystalhd_dioq_t *ioq, uint32_t to_secs, + uint32_t *sig_pend) +{ + unsigned long flags = 0; + int rc = 0, count; + void *tmp = NULL; + + if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG) || !to_secs || !sig_pend) { + BCMLOG_ERR("Invalid arg!!\n"); + return tmp; + } + + count = to_secs; + spin_lock_irqsave(&ioq->lock, flags); + while ((ioq->count == 0) && count) { + spin_unlock_irqrestore(&ioq->lock, flags); + + crystalhd_wait_on_event(&ioq->event, (ioq->count > 0), 1000, rc, 0); + if (rc == 0) { + goto out; + } else if (rc == -EINTR) { + BCMLOG(BCMLOG_INFO, "Cancelling fetch wait\n"); + *sig_pend = 1; + return tmp; + } + spin_lock_irqsave(&ioq->lock, flags); + count--; + } + spin_unlock_irqrestore(&ioq->lock, flags); + +out: + return crystalhd_dioq_fetch(ioq); +} + +/** + * crystalhd_map_dio - Map user address for DMA + * @adp: Adapter instance + * @ubuff: User buffer to map. + * @ubuff_sz: User buffer size. + * @uv_offset: UV buffer offset. + * @en_422mode: TRUE:422 FALSE:420 Capture mode. + * @dir_tx: TRUE for Tx (To device from host) + * @dio_hnd: Handle to mapped DIO request. + * + * Return: + * Status. + * + * This routine maps user address and lock pages for DMA. + * + */ +BC_STATUS crystalhd_map_dio(struct crystalhd_adp *adp, void *ubuff, + uint32_t ubuff_sz, uint32_t uv_offset, + bool en_422mode, bool dir_tx, + crystalhd_dio_req **dio_hnd) +{ + crystalhd_dio_req *dio; + /* FIXME: jarod: should some of these unsigned longs be uint32_t or uintptr_t? */ + unsigned long start = 0, end = 0, uaddr = 0, count = 0; + unsigned long spsz = 0, uv_start = 0; + int i = 0, rw = 0, res = 0, nr_pages = 0, skip_fb_sg = 0; + + if (!adp || !ubuff || !ubuff_sz || !dio_hnd) { + BCMLOG_ERR("Invalid arg \n"); + return BC_STS_INV_ARG; + } + /* Compute pages */ + uaddr = (unsigned long)ubuff; + count = (unsigned long)ubuff_sz; + end = (uaddr + count + PAGE_SIZE - 1) >> PAGE_SHIFT; + start = uaddr >> PAGE_SHIFT; + nr_pages = end - start; + + if (!count || ((uaddr + count) < uaddr)) { + BCMLOG_ERR("User addr overflow!!\n"); + return BC_STS_INV_ARG; + } + + dio = crystalhd_alloc_dio(adp); + if (!dio) { + BCMLOG_ERR("dio pool empty..\n"); + return BC_STS_INSUFF_RES; + } + + if (dir_tx) { + rw = WRITE; + dio->direction = DMA_TO_DEVICE; + } else { + rw = READ; + dio->direction = DMA_FROM_DEVICE; + } + + if (nr_pages > dio->max_pages) { + BCMLOG_ERR("max_pages(%d) exceeded(%d)!!\n", + dio->max_pages, nr_pages); + crystalhd_unmap_dio(adp, dio); + return BC_STS_INSUFF_RES; + } + + if (uv_offset) { + uv_start = (uaddr + (unsigned long)uv_offset) >> PAGE_SHIFT; + dio->uinfo.uv_sg_ix = uv_start - start; + dio->uinfo.uv_sg_off = ((uaddr + (unsigned long)uv_offset) & ~PAGE_MASK); + } + + dio->fb_size = ubuff_sz & 0x03; + if (dio->fb_size) { + res = copy_from_user(dio->fb_va, + (void *)(uaddr + count - dio->fb_size), + dio->fb_size); + if (res) { + BCMLOG_ERR("failed %d to copy %u fill bytes from %p\n", + res, dio->fb_size, + (void *)(uaddr + count-dio->fb_size)); + crystalhd_unmap_dio(adp, dio); + return BC_STS_INSUFF_RES; + } + } + + down_read(¤t->mm->mmap_sem); + res = get_user_pages(current, current->mm, uaddr, nr_pages, rw == READ, + 0, dio->pages, NULL); + up_read(¤t->mm->mmap_sem); + + /* Save for release..*/ + dio->sig = crystalhd_dio_locked; + if (res < nr_pages) { + BCMLOG_ERR("get pages failed: %d-%d\n", nr_pages, res); + dio->page_cnt = res; + crystalhd_unmap_dio(adp, dio); + return BC_STS_ERROR; + } + + dio->page_cnt = nr_pages; + /* Get scatter/gather */ + crystalhd_init_sg(dio->sg, dio->page_cnt); + crystalhd_set_sg(&dio->sg[0], dio->pages[0], 0, uaddr & ~PAGE_MASK); + if (nr_pages > 1) { + dio->sg[0].length = PAGE_SIZE - dio->sg[0].offset; + +#ifdef CONFIG_X86_64 + dio->sg[0].dma_length = dio->sg[0].length; +#endif + count -= dio->sg[0].length; + for (i = 1; i < nr_pages; i++) { + if (count < 4) { + spsz = count; + skip_fb_sg = 1; + } else { + spsz = (count < PAGE_SIZE) ? + (count & ~0x03) : PAGE_SIZE; + } + crystalhd_set_sg(&dio->sg[i], dio->pages[i], spsz, 0); + count -= spsz; + } + } else { + if (count < 4) { + dio->sg[0].length = count; + skip_fb_sg = 1; + } else { + dio->sg[0].length = count - dio->fb_size; + } +#ifdef CONFIG_X86_64 + dio->sg[0].dma_length = dio->sg[0].length; +#endif + } + dio->sg_cnt = pci_map_sg(adp->pdev, dio->sg, + dio->page_cnt, dio->direction); + if (dio->sg_cnt <= 0) { + BCMLOG_ERR("sg map %d-%d \n", dio->sg_cnt, dio->page_cnt); + crystalhd_unmap_dio(adp, dio); + return BC_STS_ERROR; + } + if (dio->sg_cnt && skip_fb_sg) + dio->sg_cnt -= 1; + dio->sig = crystalhd_dio_sg_mapped; + /* Fill in User info.. */ + dio->uinfo.xfr_len = ubuff_sz; + dio->uinfo.xfr_buff = ubuff; + dio->uinfo.uv_offset = uv_offset; + dio->uinfo.b422mode = en_422mode; + dio->uinfo.dir_tx = dir_tx; + + *dio_hnd = dio; + + return BC_STS_SUCCESS; +} + +/** + * crystalhd_unmap_sgl - Release mapped resources + * @adp: Adapter instance + * @dio: DIO request instance + * + * Return: + * Status. + * + * This routine is to unmap the user buffer pages. + */ +BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *adp, crystalhd_dio_req *dio) +{ + struct page *page = NULL; + int j = 0; + + if (!adp || !dio) { + BCMLOG_ERR("Invalid arg \n"); + return BC_STS_INV_ARG; + } + + if ((dio->page_cnt > 0) && (dio->sig != crystalhd_dio_inv)) { + for (j = 0; j < dio->page_cnt; j++) { + page = dio->pages[j]; + if (page) { + if (!PageReserved(page) && + (dio->direction == DMA_FROM_DEVICE)) + SetPageDirty(page); + page_cache_release(page); + } + } + } + if (dio->sig == crystalhd_dio_sg_mapped) + pci_unmap_sg(adp->pdev, dio->sg, dio->page_cnt, dio->direction); + + crystalhd_free_dio(adp, dio); + + return BC_STS_SUCCESS; +} + +/** + * crystalhd_create_dio_pool - Allocate mem pool for DIO management. + * @adp: Adapter instance + * @max_pages: Max pages for size calculation. + * + * Return: + * system error. + * + * This routine creates a memory pool to hold dio context for + * for HW Direct IO operation. + */ +int crystalhd_create_dio_pool(struct crystalhd_adp *adp, uint32_t max_pages) +{ + uint32_t asz = 0, i = 0; + uint8_t *temp; + crystalhd_dio_req *dio; + + if (!adp || !max_pages) { + BCMLOG_ERR("Invalid Arg!!\n"); + return -EINVAL; + } + + /* Get dma memory for fill byte handling..*/ + adp->fill_byte_pool = pci_pool_create("crystalhd_fbyte", + adp->pdev, 8, 8, 0); + if (!adp->fill_byte_pool) { + BCMLOG_ERR("failed to create fill byte pool\n"); + return -ENOMEM; + } + + /* Get the max size from user based on 420/422 modes */ + asz = (sizeof(*dio->pages) * max_pages) + + (sizeof(*dio->sg) * max_pages) + sizeof(*dio); + + BCMLOG(BCMLOG_DBG, "Initializing Dio pool %d %d %x %p\n", + BC_LINK_SG_POOL_SZ, max_pages, asz, adp->fill_byte_pool); + + for (i = 0; i < BC_LINK_SG_POOL_SZ; i++) { + temp = (uint8_t *)kzalloc(asz, GFP_KERNEL); + if ((temp) == NULL) { + BCMLOG_ERR("Failed to alloc %d mem\n", asz); + return -ENOMEM; + } + + dio = (crystalhd_dio_req *)temp; + temp += sizeof(*dio); + dio->pages = (struct page **)temp; + temp += (sizeof(*dio->pages) * max_pages); + dio->sg = (struct scatterlist *)temp; + dio->max_pages = max_pages; + dio->fb_va = pci_pool_alloc(adp->fill_byte_pool, GFP_KERNEL, + &dio->fb_pa); + if (!dio->fb_va) { + BCMLOG_ERR("fill byte alloc failed.\n"); + return -ENOMEM; + } + + crystalhd_free_dio(adp, dio); + } + + return 0; +} + +/** + * crystalhd_destroy_dio_pool - Release DIO mem pool. + * @adp: Adapter instance + * + * Return: + * none. + * + * This routine releases dio memory pool during close. + */ +void crystalhd_destroy_dio_pool(struct crystalhd_adp *adp) +{ + crystalhd_dio_req *dio; + int count = 0; + + if (!adp) { + BCMLOG_ERR("Invalid Arg!!\n"); + return; + } + + do { + dio = crystalhd_alloc_dio(adp); + if (dio) { + if (dio->fb_va) + pci_pool_free(adp->fill_byte_pool, + dio->fb_va, dio->fb_pa); + count++; + kfree(dio); + } + } while (dio); + + if (adp->fill_byte_pool) { + pci_pool_destroy(adp->fill_byte_pool); + adp->fill_byte_pool = NULL; + } + + BCMLOG(BCMLOG_DBG, "Released dio pool %d \n", count); +} + +/** + * crystalhd_create_elem_pool - List element pool creation. + * @adp: Adapter instance + * @pool_size: Number of elements in the pool. + * + * Return: + * 0 - success, <0 error + * + * Create general purpose list element pool to hold pending, + * and active requests. + */ +int crystalhd_create_elem_pool(struct crystalhd_adp *adp, uint32_t pool_size) +{ + uint32_t i; + crystalhd_elem_t *temp; + + if (!adp || !pool_size) + return -EINVAL; + + for (i = 0; i < pool_size; i++) { + temp = kzalloc(sizeof(*temp), GFP_KERNEL); + if (!temp) { + BCMLOG_ERR("kalloc failed \n"); + return -ENOMEM; + } + crystalhd_free_elem(adp, temp); + } + BCMLOG(BCMLOG_DBG, "allocated %d elem\n", pool_size); + return 0; +} + +/** + * crystalhd_delete_elem_pool - List element pool deletion. + * @adp: Adapter instance + * + * Return: + * none + * + * Delete general purpose list element pool. + */ +void crystalhd_delete_elem_pool(struct crystalhd_adp *adp) +{ + crystalhd_elem_t *temp; + int dbg_cnt = 0; + + if (!adp) + return; + + do { + temp = crystalhd_alloc_elem(adp); + if (temp) { + kfree(temp); + dbg_cnt++; + } + } while (temp); + + BCMLOG(BCMLOG_DBG, "released %d elem\n", dbg_cnt); +} + +/*================ Debug support routines.. ================================*/ +void crystalhd_show_buffer(uint32_t off, uint8_t *buff, uint32_t dwcount) +{ + uint32_t i, k = 1; + + for (i = 0; i < dwcount; i++) { + if (k == 1) + BCMLOG(BCMLOG_DATA, "0x%08X : ", off); + + BCMLOG(BCMLOG_DATA, " 0x%08X ", *((uint32_t *)buff)); + + buff += sizeof(uint32_t); + off += sizeof(uint32_t); + k++; + if ((i == dwcount - 1) || (k > 4)) { + BCMLOG(BCMLOG_DATA, "\n"); + k = 1; + } + } +} diff --git a/drivers/staging/crystalhd/crystalhd_misc.h b/drivers/staging/crystalhd/crystalhd_misc.h new file mode 100644 index 000000000000..a2aa6ad7fc81 --- /dev/null +++ b/drivers/staging/crystalhd/crystalhd_misc.h @@ -0,0 +1,229 @@ +/*************************************************************************** + * Copyright (c) 2005-2009, Broadcom Corporation. + * + * Name: crystalhd_misc . h + * + * Description: + * BCM70012 Linux driver general purpose routines. + * Includes reg/mem read and write routines. + * + * HISTORY: + * + ********************************************************************** + * This file is part of the crystalhd device driver. + * + * This driver is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this driver. If not, see . + **********************************************************************/ + +#ifndef _CRYSTALHD_MISC_H_ +#define _CRYSTALHD_MISC_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "bc_dts_glob_lnx.h" + +/* Global log level variable defined in crystal_misc.c file */ +extern uint32_t g_linklog_level; + +/* Global element pool for all Queue management. + * TX: Active = BC_TX_LIST_CNT, Free = BC_TX_LIST_CNT. + * RX: Free = BC_RX_LIST_CNT, Active = 2 + * FW-CMD: 4 + */ +#define BC_LINK_ELEM_POOL_SZ ((BC_TX_LIST_CNT * 2) + BC_RX_LIST_CNT + 2 + 4) + +/* Driver's IODATA pool count */ +#define CHD_IODATA_POOL_SZ (BC_IOCTL_DATA_POOL_SIZE * BC_LINK_MAX_OPENS) + +/* Scatter Gather memory pool size for Tx and Rx */ +#define BC_LINK_SG_POOL_SZ (BC_TX_LIST_CNT + BC_RX_LIST_CNT) + +enum _crystalhd_dio_sig { + crystalhd_dio_inv = 0, + crystalhd_dio_locked, + crystalhd_dio_sg_mapped, +}; + +struct crystalhd_dio_user_info { + void *xfr_buff; + uint32_t xfr_len; + uint32_t uv_offset; + bool dir_tx; + + uint32_t uv_sg_ix; + uint32_t uv_sg_off; + int comp_sts; + int ev_sts; + uint32_t y_done_sz; + uint32_t uv_done_sz; + uint32_t comp_flags; + bool b422mode; +}; + +typedef struct _crystalhd_dio_req { + uint32_t sig; + uint32_t max_pages; + struct page **pages; + struct scatterlist *sg; + int sg_cnt; + int page_cnt; + int direction; + struct crystalhd_dio_user_info uinfo; + void *fb_va; + uint32_t fb_size; + dma_addr_t fb_pa; + struct _crystalhd_dio_req *next; +} crystalhd_dio_req; + +#define BC_LINK_DIOQ_SIG (0x09223280) + +typedef struct _crystalhd_elem_s { + struct _crystalhd_elem_s *flink; + struct _crystalhd_elem_s *blink; + void *data; + uint32_t tag; +} crystalhd_elem_t; + +typedef void (*crystalhd_data_free_cb)(void *context, void *data); + +typedef struct _crystalhd_dioq_s { + uint32_t sig; + struct crystalhd_adp *adp; + crystalhd_elem_t *head; + crystalhd_elem_t *tail; + uint32_t count; + spinlock_t lock; + wait_queue_head_t event; + crystalhd_data_free_cb data_rel_cb; + void *cb_context; +} crystalhd_dioq_t; + +typedef void (*hw_comp_callback)(crystalhd_dio_req *, + wait_queue_head_t *event, BC_STATUS sts); + +/*========= Decoder (7412) register access routines.================= */ +uint32_t bc_dec_reg_rd(struct crystalhd_adp *, uint32_t); +void bc_dec_reg_wr(struct crystalhd_adp *, uint32_t, uint32_t); + +/*========= Link (70012) register access routines.. =================*/ +uint32_t crystalhd_reg_rd(struct crystalhd_adp *, uint32_t); +void crystalhd_reg_wr(struct crystalhd_adp *, uint32_t, uint32_t); + +/*========= Decoder (7412) memory access routines..=================*/ +BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *); +BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *); + +/*==========Link (70012) PCIe Config access routines.================*/ +BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *); +BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t); + +/*========= Linux Kernel Interface routines. ======================= */ +void *bc_kern_dma_alloc(struct crystalhd_adp *, uint32_t, dma_addr_t *); +void bc_kern_dma_free(struct crystalhd_adp *, uint32_t, + void *, dma_addr_t); +#define crystalhd_create_event(_ev) init_waitqueue_head(_ev) +#define crystalhd_set_event(_ev) wake_up_interruptible(_ev) +#define crystalhd_wait_on_event(ev, condition, timeout, ret, nosig) \ +do { \ + DECLARE_WAITQUEUE(entry, current); \ + unsigned long end = jiffies + ((timeout * HZ) / 1000); \ + ret = 0; \ + add_wait_queue(ev, &entry); \ + for (;;) { \ + __set_current_state(TASK_INTERRUPTIBLE); \ + if (condition) { \ + break; \ + } \ + if (time_after_eq(jiffies, end)) { \ + ret = -EBUSY; \ + break; \ + } \ + schedule_timeout((HZ / 100 > 1) ? HZ / 100 : 1); \ + if (!nosig && signal_pending(current)) { \ + ret = -EINTR; \ + break; \ + } \ + } \ + __set_current_state(TASK_RUNNING); \ + remove_wait_queue(ev, &entry); \ +} while (0) + +/*================ Direct IO mapping routines ==================*/ +extern int crystalhd_create_dio_pool(struct crystalhd_adp *, uint32_t); +extern void crystalhd_destroy_dio_pool(struct crystalhd_adp *); +extern BC_STATUS crystalhd_map_dio(struct crystalhd_adp *, void *, uint32_t, + uint32_t, bool, bool, crystalhd_dio_req**); + +extern BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *, crystalhd_dio_req*); +#define crystalhd_get_sgle_paddr(_dio, _ix) (cpu_to_le64(sg_dma_address(&_dio->sg[_ix]))) +#define crystalhd_get_sgle_len(_dio, _ix) (cpu_to_le32(sg_dma_len(&_dio->sg[_ix]))) + +/*================ General Purpose Queues ==================*/ +extern BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *, crystalhd_dioq_t **, crystalhd_data_free_cb , void *); +extern void crystalhd_delete_dioq(struct crystalhd_adp *, crystalhd_dioq_t *); +extern BC_STATUS crystalhd_dioq_add(crystalhd_dioq_t *ioq, void *data, bool wake, uint32_t tag); +extern void *crystalhd_dioq_fetch(crystalhd_dioq_t *ioq); +extern void *crystalhd_dioq_find_and_fetch(crystalhd_dioq_t *ioq, uint32_t tag); +extern void *crystalhd_dioq_fetch_wait(crystalhd_dioq_t *ioq, uint32_t to_secs, uint32_t *sig_pend); + +#define crystalhd_dioq_count(_ioq) ((_ioq) ? _ioq->count : 0) + +extern int crystalhd_create_elem_pool(struct crystalhd_adp *, uint32_t); +extern void crystalhd_delete_elem_pool(struct crystalhd_adp *); + + +/*================ Debug routines/macros .. ================================*/ +extern void crystalhd_show_buffer(uint32_t off, uint8_t *buff, uint32_t dwcount); + +enum _chd_log_levels { + BCMLOG_ERROR = 0x80000000, /* Don't disable this option */ + BCMLOG_DATA = 0x40000000, /* Data, enable by default */ + BCMLOG_SPINLOCK = 0x20000000, /* Spcial case for Spin locks*/ + + /* Following are allowed only in debug mode */ + BCMLOG_INFO = 0x00000001, /* Generic informational */ + BCMLOG_DBG = 0x00000002, /* First level Debug info */ + BCMLOG_SSTEP = 0x00000004, /* Stepping information */ + BCMLOG_ENTER_LEAVE = 0x00000008, /* stack tracking */ +}; + +#define BCMLOG_ENTER \ +if (g_linklog_level & BCMLOG_ENTER_LEAVE) { \ + printk("Entered %s\n", __func__); \ +} + +#define BCMLOG_LEAVE \ +if (g_linklog_level & BCMLOG_ENTER_LEAVE) { \ + printk("Leaving %s\n", __func__); \ +} + +#define BCMLOG(trace, fmt, args...) \ +if (g_linklog_level & trace) { \ + printk(fmt, ##args); \ +} + +#define BCMLOG_ERR(fmt, args...) \ +do { \ + if (g_linklog_level & BCMLOG_ERROR) { \ + printk("*ERR*:%s:%d: "fmt, __FILE__, __LINE__, ##args); \ + } \ +} while (0); + +#endif -- cgit v1.2.3 From 716323c09319ae5e6c9e413a6378d61a77b26996 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Wed, 23 Dec 2009 02:36:43 +0100 Subject: Staging: rtl8192u: ieee80211: add missing parentheses not(!) has a higher precedence than bit and(&). Signed-off-by: Roel Kluin Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c b/drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c index da2449d290cb..c0b2c02b0ac4 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c @@ -718,7 +718,7 @@ int ieee80211_wx_get_encode_ext(struct ieee80211_device *ieee, } else idx = ieee->tx_keyidx; - if (!ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY && + if (!(ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) && ext->alg != IW_ENCODE_ALG_WEP) if (idx != 0 || ieee->iw_mode != IW_MODE_INFRA) return -EINVAL; -- cgit v1.2.3 From 23a51a8061567a47347ade59edf2a0bde0eece30 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Sat, 26 Dec 2009 20:00:47 +0100 Subject: Staging: rt2860: test off by one in RtmpAsicSendCommandToMcu() `i' reaches 101 after the loop, so if it was 100 then it succeeded in the last iteration. This is probably unlikely to cause problems. Signed-off-by: Roel Kluin Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rt2860/common/rtmp_mcu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/rt2860/common/rtmp_mcu.c b/drivers/staging/rt2860/common/rtmp_mcu.c index 9f03901433bb..e80f587cff1a 100644 --- a/drivers/staging/rt2860/common/rtmp_mcu.c +++ b/drivers/staging/rt2860/common/rtmp_mcu.c @@ -221,7 +221,7 @@ int RtmpAsicSendCommandToMcu(struct rt_rtmp_adapter *pAd, ("AsicSendCommanToMcu::Mail box is busy\n")); } while (i++ < 100); - if (i >= 100) { + if (i > 100) { DBGPRINT_ERR(("H2M_MAILBOX still hold by MCU. command fail\n")); return FALSE; } -- cgit v1.2.3 From acdfd0e088502dc225f594b5a5598cab53ffd375 Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Sat, 2 Jan 2010 11:30:36 +0100 Subject: Staging: batman-adv: Remove NULL pointer check It is safe to call kfree(NULL) which makes this extra check unneeded. It was found using checkpatch.pl from linux-2.6 Signed-off-by: Sven Eckelmann Acked-by: Simon Wunderlich Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/hard-interface.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/hard-interface.c b/drivers/staging/batman-adv/hard-interface.c index e9cb977d0016..28d02f68a3f8 100644 --- a/drivers/staging/batman-adv/hard-interface.c +++ b/drivers/staging/batman-adv/hard-interface.c @@ -399,8 +399,7 @@ int hardif_add_interface(char *dev, int if_num) return 1; out: - if (batman_if->packet_buff) - kfree(batman_if->packet_buff); + kfree(batman_if->packet_buff); kfree(batman_if); kfree(dev); return -1; -- cgit v1.2.3 From 183cd9ee543c9364fa42be8d30265fd47a914b59 Mon Sep 17 00:00:00 2001 From: Simon Wunderlich Date: Sat, 2 Jan 2010 11:30:37 +0100 Subject: Staging: batman-adv: update README for latest kernel state in the README that we also (compile) support 2.6.32 Signed-off-by: Simon Wunderlich Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/README b/drivers/staging/batman-adv/README index a6a419de0b50..2bedcbedb6af 100644 --- a/drivers/staging/batman-adv/README +++ b/drivers/staging/batman-adv/README @@ -1,4 +1,4 @@ -[state: 13-11-2009] +[state: 13-12-2009] BATMAN-ADV ---------- @@ -15,7 +15,7 @@ above B.A.T.M.A.N. Advanced, prominent examples are: IPv4, IPv6, DHCP, IPX. This is batman-advanced implemented as Linux kernel driver. It does not depend on any network (other) driver, and can be used on wifi as well as ethernet, vpn, etc ... (anything with ethernet-style layer 2). -It compiles against and should work with Linux 2.6.20 - 2.6.31. Supporting older +It compiles against and should work with Linux 2.6.20 - 2.6.32. Supporting older versions is not planned, but it's probably easy to backport it. If you work on a backport, feel free to contact us. :-) -- cgit v1.2.3 From 4ce21a7faf320bdb750a2e1639f8f2dbb27bdb89 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 2 Jan 2010 11:30:38 +0100 Subject: Staging: batman-adv: Replace KERN_DEBUG with bat_dbg Ameya Palande requested we replace printk(KERN_DEBUG "") by pr_debug() I decided it was better to use our debug macro. Signed-off-by: Andrew Lunn Acked-by: Marek Lindner Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/TODO | 6 ------ drivers/staging/batman-adv/device.c | 6 +++--- 2 files changed, 3 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/TODO b/drivers/staging/batman-adv/TODO index ea6dcf94d661..8c2b89e82ad7 100644 --- a/drivers/staging/batman-adv/TODO +++ b/drivers/staging/batman-adv/TODO @@ -29,12 +29,6 @@ -> PRIMARY) => logging -* the log level LOG_TYPE_CRIT, LOG_TYPE_WARN & LOG_TYPE_NOTICE will be -* unified to use printk -* LOG_TYPE_BATMAN & LOG_TYPE_ROUTES will also use printk but only after the -* internal debug level has been raised -* the internal debug level can be modified using a module parameter (debug) -* or at run time via /sys/module/batman-adv/parameters/debug * make use of printk %pM support instead of converting mac addresses * manually diff --git a/drivers/staging/batman-adv/device.c b/drivers/staging/batman-adv/device.c index 12f2de98b3d0..92cf8d56a5f2 100644 --- a/drivers/staging/batman-adv/device.c +++ b/drivers/staging/batman-adv/device.c @@ -207,7 +207,7 @@ ssize_t bat_device_write(struct file *file, const char __user *buff, struct batman_if *batman_if; if (len < sizeof(struct icmp_packet)) { - printk(KERN_DEBUG "batman-adv:Error - can't send packet from char device: invalid packet size\n"); + bat_dbg(DBG_BATMAN, "batman-adv:Error - can't send packet from char device: invalid packet size\n"); return -EINVAL; } @@ -218,12 +218,12 @@ ssize_t bat_device_write(struct file *file, const char __user *buff, return -EFAULT; if (icmp_packet.packet_type != BAT_ICMP) { - printk(KERN_DEBUG "batman-adv:Error - can't send packet from char device: got bogus packet type (expected: BAT_ICMP)\n"); + bat_dbg(DBG_BATMAN, "batman-adv:Error - can't send packet from char device: got bogus packet type (expected: BAT_ICMP)\n"); return -EINVAL; } if (icmp_packet.msg_type != ECHO_REQUEST) { - printk(KERN_DEBUG "batman-adv:Error - can't send packet from char device: got bogus message type (expected: ECHO_REQUEST)\n"); + bat_dbg(DBG_BATMAN, "batman-adv:Error - can't send packet from char device: got bogus message type (expected: ECHO_REQUEST)\n"); return -EINVAL; } -- cgit v1.2.3 From b6c359767bc743a7b6830660daa8f7e5c4273ad8 Mon Sep 17 00:00:00 2001 From: Simon Wunderlich Date: Sat, 2 Jan 2010 11:30:39 +0100 Subject: Staging: batman-adv: initialize static hash iterators instead of dynamically registering hash iterators, calling functions are changed to register the iterator objects statically. The two advantages are: * no memory leaks when aborting from hash_iterate() * no calls to kmalloc/kfree, therefore a little faster/safer Tested with 9 QEMU instances, no obvious regression found. Signed-off-by: Simon Wunderlich Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/hard-interface.c | 6 ++--- drivers/staging/batman-adv/hash.c | 23 +++++++----------- drivers/staging/batman-adv/hash.h | 5 ++++ drivers/staging/batman-adv/originator.c | 8 +++---- drivers/staging/batman-adv/proc.c | 12 +++++----- drivers/staging/batman-adv/routing.c | 6 ++--- drivers/staging/batman-adv/translation-table.c | 24 +++++++++---------- drivers/staging/batman-adv/vis.c | 33 +++++++++++++------------- 8 files changed, 57 insertions(+), 60 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/hard-interface.c b/drivers/staging/batman-adv/hard-interface.c index 28d02f68a3f8..7c885926b167 100644 --- a/drivers/staging/batman-adv/hard-interface.c +++ b/drivers/staging/batman-adv/hard-interface.c @@ -318,7 +318,7 @@ int hardif_add_interface(char *dev, int if_num) struct batman_if *batman_if; struct batman_packet *batman_packet; struct orig_node *orig_node; - struct hash_it_t *hashit = NULL; + HASHIT(hashit); batman_if = kmalloc(sizeof(struct batman_if), GFP_KERNEL); @@ -377,8 +377,8 @@ int hardif_add_interface(char *dev, int if_num) * if_num */ spin_lock(&orig_hash_lock); - while (NULL != (hashit = hash_iterate(orig_hash, hashit))) { - orig_node = hashit->bucket->data; + while (hash_iterate(orig_hash, &hashit)) { + orig_node = hashit.bucket->data; if (resize_orig(orig_node, if_num) == -1) { spin_unlock(&orig_hash_lock); goto out; diff --git a/drivers/staging/batman-adv/hash.c b/drivers/staging/batman-adv/hash.c index 61cb4a20ebca..5a2018de3ff2 100644 --- a/drivers/staging/batman-adv/hash.c +++ b/drivers/staging/batman-adv/hash.c @@ -64,24 +64,18 @@ void hash_destroy(struct hashtable_t *hash) kfree(hash); } -/* iterate though the hash. first element is selected with iter_in NULL. use - * the returned iterator to access the elements until hash_it_t returns NULL. */ +/* iterate though the hash. First element is selected if an iterator + * initialized with HASHIT() is supplied as iter. Use the returned + * (or supplied) iterator to access the elements until hash_iterate returns + * NULL. */ + struct hash_it_t *hash_iterate(struct hashtable_t *hash, - struct hash_it_t *iter_in) + struct hash_it_t *iter) { - struct hash_it_t *iter; - if (!hash) return NULL; - - if (iter_in == NULL) { - iter = kmalloc(sizeof(struct hash_it_t), GFP_ATOMIC); - iter->index = -1; - iter->bucket = NULL; - iter->prev_bucket = NULL; - } else { - iter = iter_in; - } + if (!iter) + return NULL; /* sanity checks first (if our bucket got deleted in the last * iteration): */ @@ -139,7 +133,6 @@ struct hash_it_t *hash_iterate(struct hashtable_t *hash, } /* nothing to iterate over anymore */ - kfree(iter); return NULL; } diff --git a/drivers/staging/batman-adv/hash.h b/drivers/staging/batman-adv/hash.h index bb60f082be6a..a70d6d6e1c7a 100644 --- a/drivers/staging/batman-adv/hash.h +++ b/drivers/staging/batman-adv/hash.h @@ -21,6 +21,11 @@ #ifndef _BATMAN_HASH_H #define _BATMAN_HASH_H +#define HASHIT(name) struct hash_it_t name = { \ + .index = -1, .bucket = NULL, \ + .prev_bucket = NULL, \ + .first_bucket = NULL } + typedef int (*hashdata_compare_cb)(void *, void *); typedef int (*hashdata_choose_cb)(void *, int); diff --git a/drivers/staging/batman-adv/originator.c b/drivers/staging/batman-adv/originator.c index 9962af7ae640..b1049826b51a 100644 --- a/drivers/staging/batman-adv/originator.c +++ b/drivers/staging/batman-adv/originator.c @@ -221,16 +221,16 @@ static bool purge_orig_node(struct orig_node *orig_node) void purge_orig(struct work_struct *work) { - struct hash_it_t *hashit = NULL; + HASHIT(hashit); struct orig_node *orig_node; spin_lock(&orig_hash_lock); /* for all origins... */ - while (NULL != (hashit = hash_iterate(orig_hash, hashit))) { - orig_node = hashit->bucket->data; + while (hash_iterate(orig_hash, &hashit)) { + orig_node = hashit.bucket->data; if (purge_orig_node(orig_node)) { - hash_remove_bucket(orig_hash, hashit); + hash_remove_bucket(orig_hash, &hashit); free_orig_node(orig_node); } } diff --git a/drivers/staging/batman-adv/proc.c b/drivers/staging/batman-adv/proc.c index ed4c73484d7d..9f7136b3be3e 100644 --- a/drivers/staging/batman-adv/proc.c +++ b/drivers/staging/batman-adv/proc.c @@ -186,7 +186,7 @@ static int proc_orig_interval_open(struct inode *inode, struct file *file) static int proc_originators_read(struct seq_file *seq, void *offset) { - struct hash_it_t *hashit = NULL; + HASHIT(hashit); struct orig_node *orig_node; struct neigh_node *neigh_node; int batman_count = 0; @@ -215,9 +215,9 @@ static int proc_originators_read(struct seq_file *seq, void *offset) rcu_read_unlock(); spin_lock(&orig_hash_lock); - while (NULL != (hashit = hash_iterate(orig_hash, hashit))) { + while (hash_iterate(orig_hash, &hashit)) { - orig_node = hashit->bucket->data; + orig_node = hashit.bucket->data; if (!orig_node->router) continue; @@ -413,7 +413,7 @@ static void proc_vis_read_entry(struct seq_file *seq, static int proc_vis_read(struct seq_file *seq, void *offset) { - struct hash_it_t *hashit = NULL; + HASHIT(hashit); struct vis_info *info; struct vis_info_entry *entries; struct vis_if_list *if_entries = NULL; @@ -440,8 +440,8 @@ static int proc_vis_read(struct seq_file *seq, void *offset) seq_printf(seq, "digraph {\n"); spin_lock(&vis_hash_lock); - while (NULL != (hashit = hash_iterate(vis_hash, hashit))) { - info = hashit->bucket->data; + while (hash_iterate(vis_hash, &hashit)) { + info = hashit.bucket->data; entries = (struct vis_info_entry *) ((char *)info + sizeof(struct vis_info)); diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index e8d712788dad..68dea76b0cab 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -40,14 +40,14 @@ static atomic_t data_ready_cond; atomic_t exit_cond; void slide_own_bcast_window(struct batman_if *batman_if) { - struct hash_it_t *hashit = NULL; + HASHIT(hashit); struct orig_node *orig_node; TYPE_OF_WORD *word; spin_lock(&orig_hash_lock); - while (NULL != (hashit = hash_iterate(orig_hash, hashit))) { - orig_node = hashit->bucket->data; + while (hash_iterate(orig_hash, &hashit)) { + orig_node = hashit.bucket->data; word = &(orig_node->bcast_own[batman_if->if_num * NUM_WORDS]); bit_get_packet(word, 1, 0); diff --git a/drivers/staging/batman-adv/translation-table.c b/drivers/staging/batman-adv/translation-table.c index c7122da98f1e..088715ba8dbd 100644 --- a/drivers/staging/batman-adv/translation-table.c +++ b/drivers/staging/batman-adv/translation-table.c @@ -134,18 +134,18 @@ void hna_local_add(uint8_t *addr) int hna_local_fill_buffer(unsigned char *buff, int buff_len) { struct hna_local_entry *hna_local_entry; - struct hash_it_t *hashit = NULL; + HASHIT(hashit); int i = 0; unsigned long flags; spin_lock_irqsave(&hna_local_hash_lock, flags); - while (NULL != (hashit = hash_iterate(hna_local_hash, hashit))) { + while (hash_iterate(hna_local_hash, &hashit)) { if (buff_len < (i + 1) * ETH_ALEN) break; - hna_local_entry = hashit->bucket->data; + hna_local_entry = hashit.bucket->data; memcpy(buff + (i * ETH_ALEN), hna_local_entry->addr, ETH_ALEN); i++; @@ -163,18 +163,18 @@ int hna_local_fill_buffer(unsigned char *buff, int buff_len) int hna_local_fill_buffer_text(unsigned char *buff, int buff_len) { struct hna_local_entry *hna_local_entry; - struct hash_it_t *hashit = NULL; + HASHIT(hashit); int bytes_written = 0; unsigned long flags; spin_lock_irqsave(&hna_local_hash_lock, flags); - while (NULL != (hashit = hash_iterate(hna_local_hash, hashit))) { + while (hash_iterate(hna_local_hash, &hashit)) { if (buff_len < bytes_written + ETH_STR_LEN + 4) break; - hna_local_entry = hashit->bucket->data; + hna_local_entry = hashit.bucket->data; bytes_written += snprintf(buff + bytes_written, ETH_STR_LEN + 4, " * %02x:%02x:%02x:%02x:%02x:%02x\n", @@ -214,14 +214,14 @@ static void hna_local_del(struct hna_local_entry *hna_local_entry, void hna_local_purge(struct work_struct *work) { struct hna_local_entry *hna_local_entry; - struct hash_it_t *hashit = NULL; + HASHIT(hashit); unsigned long flags; unsigned long timeout; spin_lock_irqsave(&hna_local_hash_lock, flags); - while (NULL != (hashit = hash_iterate(hna_local_hash, hashit))) { - hna_local_entry = hashit->bucket->data; + while (hash_iterate(hna_local_hash, &hashit)) { + hna_local_entry = hashit.bucket->data; timeout = hna_local_entry->last_seen + ((LOCAL_HNA_TIMEOUT / 1000) * HZ); @@ -345,17 +345,17 @@ void hna_global_add_orig(struct orig_node *orig_node, int hna_global_fill_buffer_text(unsigned char *buff, int buff_len) { struct hna_global_entry *hna_global_entry; - struct hash_it_t *hashit = NULL; + HASHIT(hashit); int bytes_written = 0; unsigned long flags; spin_lock_irqsave(&hna_global_hash_lock, flags); - while (NULL != (hashit = hash_iterate(hna_global_hash, hashit))) { + while (hash_iterate(hna_global_hash, &hashit)) { if (buff_len < bytes_written + (2 * ETH_STR_LEN) + 10) break; - hna_global_entry = hashit->bucket->data; + hna_global_entry = hashit.bucket->data; bytes_written += snprintf(buff + bytes_written, (2 * ETH_STR_LEN) + 10, diff --git a/drivers/staging/batman-adv/vis.c b/drivers/staging/batman-adv/vis.c index cdb8aab146d7..086da871cd59 100644 --- a/drivers/staging/batman-adv/vis.c +++ b/drivers/staging/batman-adv/vis.c @@ -266,12 +266,12 @@ end: * Must be called with the originator hash locked */ static int find_best_vis_server(struct vis_info *info) { - struct hash_it_t *hashit = NULL; + HASHIT(hashit); struct orig_node *orig_node; int best_tq = -1; - while (NULL != (hashit = hash_iterate(orig_hash, hashit))) { - orig_node = hashit->bucket->data; + while (hash_iterate(orig_hash, &hashit)) { + orig_node = hashit.bucket->data; if ((orig_node != NULL) && (orig_node->router != NULL) && (orig_node->flags & VIS_SERVER) && @@ -297,7 +297,8 @@ static bool vis_packet_full(struct vis_info *info) * returns 0 on success, -1 if no packet could be generated */ static int generate_vis_packet(void) { - struct hash_it_t *hashit = NULL; + HASHIT(hashit_local); + HASHIT(hashit_global); struct orig_node *orig_node; struct vis_info *info = (struct vis_info *)my_vis_info; struct vis_info_entry *entry, *entry_array; @@ -320,13 +321,12 @@ static int generate_vis_packet(void) return -1; } } - hashit = NULL; entry_array = (struct vis_info_entry *) ((char *)info + sizeof(struct vis_info)); - while (NULL != (hashit = hash_iterate(orig_hash, hashit))) { - orig_node = hashit->bucket->data; + while (hash_iterate(orig_hash, &hashit_global)) { + orig_node = hashit_global.bucket->data; if (orig_node->router != NULL && compare_orig(orig_node->router->addr, orig_node->orig) && orig_node->batman_if @@ -349,10 +349,9 @@ static int generate_vis_packet(void) spin_unlock(&orig_hash_lock); - hashit = NULL; spin_lock_irqsave(&hna_local_hash_lock, flags); - while (NULL != (hashit = hash_iterate(hna_local_hash, hashit))) { - hna_local_entry = hashit->bucket->data; + while (hash_iterate(hna_local_hash, &hashit_local)) { + hna_local_entry = hashit_local.bucket->data; entry = &entry_array[info->packet.entries]; memset(entry->src, 0, ETH_ALEN); memcpy(entry->dest, hna_local_entry->addr, ETH_ALEN); @@ -370,16 +369,16 @@ static int generate_vis_packet(void) static void purge_vis_packets(void) { - struct hash_it_t *hashit = NULL; + HASHIT(hashit); struct vis_info *info; - while (NULL != (hashit = hash_iterate(vis_hash, hashit))) { - info = hashit->bucket->data; + while (hash_iterate(vis_hash, &hashit)) { + info = hashit.bucket->data; if (info == my_vis_info) /* never purge own data. */ continue; if (time_after(jiffies, info->first_seen + (VIS_TIMEOUT/1000)*HZ)) { - hash_remove_bucket(vis_hash, hashit); + hash_remove_bucket(vis_hash, &hashit); free_info(info); } } @@ -387,14 +386,14 @@ static void purge_vis_packets(void) static void broadcast_vis_packet(struct vis_info *info, int packet_length) { - struct hash_it_t *hashit = NULL; + HASHIT(hashit); struct orig_node *orig_node; spin_lock(&orig_hash_lock); /* send to all routers in range. */ - while (NULL != (hashit = hash_iterate(orig_hash, hashit))) { - orig_node = hashit->bucket->data; + while (hash_iterate(orig_hash, &hashit)) { + orig_node = hashit.bucket->data; /* if it's a vis server and reachable, send it. */ if (orig_node && -- cgit v1.2.3 From 5ea84fa369baa3d36fa8a78e9af3dc71bbcbca51 Mon Sep 17 00:00:00 2001 From: Simon Wunderlich Date: Sat, 2 Jan 2010 11:30:40 +0100 Subject: Staging: batman-adv: consistent spelling of "neighbors" we have written "neighbors", "neighbours" and bad spelled versions of this word, this patch should make it consistent. Signed-off-by: Simon Wunderlich Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/originator.c | 12 ++++++------ drivers/staging/batman-adv/packet.h | 2 +- drivers/staging/batman-adv/proc.c | 2 +- drivers/staging/batman-adv/routing.c | 10 +++++----- drivers/staging/batman-adv/types.h | 2 +- 5 files changed, 14 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/originator.c b/drivers/staging/batman-adv/originator.c index b1049826b51a..6a1fdf2b702b 100644 --- a/drivers/staging/batman-adv/originator.c +++ b/drivers/staging/batman-adv/originator.c @@ -74,7 +74,7 @@ create_neighbor(struct orig_node *orig_node, struct orig_node *orig_neigh_node, { struct neigh_node *neigh_node; - bat_dbg(DBG_BATMAN, "Creating new last-hop neighbour of originator\n"); + bat_dbg(DBG_BATMAN, "Creating new last-hop neighbor of originator\n"); neigh_node = kmalloc(sizeof(struct neigh_node), GFP_ATOMIC); memset(neigh_node, 0, sizeof(struct neigh_node)); @@ -94,7 +94,7 @@ void free_orig_node(void *data) struct neigh_node *neigh_node; struct orig_node *orig_node = (struct orig_node *)data; - /* for all neighbours towards this originator ... */ + /* for all neighbors towards this originator ... */ list_for_each_safe(list_pos, list_pos_tmp, &orig_node->neigh_list) { neigh_node = list_entry(list_pos, struct neigh_node, list); @@ -159,7 +159,7 @@ struct orig_node *get_orig_node(uint8_t *addr) return orig_node; } -static bool purge_orig_neigbours(struct orig_node *orig_node, +static bool purge_orig_neighbors(struct orig_node *orig_node, struct neigh_node **best_neigh_node) { struct list_head *list_pos, *list_pos_tmp; @@ -170,7 +170,7 @@ static bool purge_orig_neigbours(struct orig_node *orig_node, *best_neigh_node = NULL; - /* for all neighbours towards this originator ... */ + /* for all neighbors towards this originator ... */ list_for_each_safe(list_pos, list_pos_tmp, &orig_node->neigh_list) { neigh_node = list_entry(list_pos, struct neigh_node, list); @@ -180,7 +180,7 @@ static bool purge_orig_neigbours(struct orig_node *orig_node, addr_to_string(neigh_str, neigh_node->addr); addr_to_string(orig_str, orig_node->orig); - bat_dbg(DBG_BATMAN, "Neighbour timeout: originator %s, neighbour: %s, last_valid %lu\n", orig_str, neigh_str, (neigh_node->last_valid / HZ)); + bat_dbg(DBG_BATMAN, "neighbor timeout: originator %s, neighbor: %s, last_valid %lu\n", orig_str, neigh_str, (neigh_node->last_valid / HZ)); neigh_purged = true; list_del(list_pos); @@ -211,7 +211,7 @@ static bool purge_orig_node(struct orig_node *orig_node) orig_str, (orig_node->last_valid / HZ)); return true; } else { - if (purge_orig_neigbours(orig_node, &best_neigh_node)) + if (purge_orig_neighbors(orig_node, &best_neigh_node)) update_routes(orig_node, best_neigh_node, orig_node->hna_buff, orig_node->hna_buff_len); diff --git a/drivers/staging/batman-adv/packet.h b/drivers/staging/batman-adv/packet.h index 5627ca326018..ad006ce8b131 100644 --- a/drivers/staging/batman-adv/packet.h +++ b/drivers/staging/batman-adv/packet.h @@ -90,7 +90,7 @@ struct vis_packet { uint8_t entries; /* number of entries behind this struct */ uint8_t ttl; /* TTL */ uint8_t vis_orig[6]; /* originator that informs about its - * neighbours */ + * neighbors */ uint8_t target_orig[6]; /* who should receive this packet */ uint8_t sender_orig[6]; /* who sent or rebroadcasted this packet */ } __attribute__((packed)); diff --git a/drivers/staging/batman-adv/proc.c b/drivers/staging/batman-adv/proc.c index 9f7136b3be3e..71668cfbdbf9 100644 --- a/drivers/staging/batman-adv/proc.c +++ b/drivers/staging/batman-adv/proc.c @@ -404,7 +404,7 @@ static void proc_vis_read_entry(struct seq_file *seq, from, to, int_part, frac_part); } else { seq_printf(seq, - "%s\t{ router : \"%s\", neighbour : \"%s\", label : %d.%d }", + "%s\t{ router : \"%s\", neighbor : \"%s\", label : %d.%d }", (first_line ? "" : ",\n"), from, to, int_part, frac_part); } } diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index 68dea76b0cab..37c53822e9c9 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -266,7 +266,7 @@ static void update_orig(struct orig_node *orig_node, struct ethhdr *ethhdr, ethhdr->h_source, if_incoming); else bat_dbg(DBG_BATMAN, - "Updating existing last-hop neighbour of originator\n"); + "Updating existing last-hop neighbor of originator\n"); orig_node->flags = batman_packet->flags; neigh_node->last_valid = jiffies; @@ -444,7 +444,7 @@ void receive_bat_packet(struct ethhdr *ethhdr, orig_neigh_node = get_orig_node(ethhdr->h_source); - /* neighbour has to indicate direct link and it has to + /* neighbor has to indicate direct link and it has to * come via the corresponding interface */ /* if received seqno equals last send seqno save new * seqno for bidirectional check */ @@ -459,7 +459,7 @@ void receive_bat_packet(struct ethhdr *ethhdr, bit_packet_count(word); } - bat_dbg(DBG_BATMAN, "Drop packet: originator packet from myself (via neighbour) \n"); + bat_dbg(DBG_BATMAN, "Drop packet: originator packet from myself (via neighbor) \n"); return; } @@ -520,14 +520,14 @@ void receive_bat_packet(struct ethhdr *ethhdr, update_orig(orig_node, ethhdr, batman_packet, if_incoming, hna_buff, hna_buff_len, is_duplicate); - /* is single hop (direct) neighbour */ + /* is single hop (direct) neighbor */ if (is_single_hop_neigh) { /* mark direct link on incoming interface */ schedule_forward_packet(orig_node, ethhdr, batman_packet, 1, hna_buff_len, if_incoming); - bat_dbg(DBG_BATMAN, "Forwarding packet: rebroadcast neighbour packet with direct link flag\n"); + bat_dbg(DBG_BATMAN, "Forwarding packet: rebroadcast neighbor packet with direct link flag\n"); return; } diff --git a/drivers/staging/batman-adv/types.h b/drivers/staging/batman-adv/types.h index 3a0ef0c38c93..9739358caca3 100644 --- a/drivers/staging/batman-adv/types.h +++ b/drivers/staging/batman-adv/types.h @@ -75,7 +75,7 @@ struct neigh_node { uint8_t tq_index; uint8_t tq_avg; uint8_t last_ttl; - unsigned long last_valid; /* when last packet via this neighbour was received */ + unsigned long last_valid; /* when last packet via this neighbor was received */ TYPE_OF_WORD real_bits[NUM_WORDS]; struct orig_node *orig_node; struct batman_if *if_incoming; -- cgit v1.2.3 From cec4a69cfc2bc780b4107193cb9bd621b67ab2b6 Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Sat, 2 Jan 2010 11:30:41 +0100 Subject: Staging: batman-adv: Use forw_bcast_list_lock always with disabled interrupts forw_bcast_list_lock is spin_locked in both process and softirq context. SoftIRQ calls the spinlock with disabled IRQ and normal process context with enabled IRQs. When process context is inside an spin_locked area protected by forw_bcast_list_lock and gets interrupted by an IRQ, it could happen that something tries to lock forw_bcast_list_lock again in SoftIRQ context. It cannot proceed further since the lock is already taken somewhere else, but no reschedule will happen inside the SoftIRQ context. This leads to an complete kernel hang without any chance of resurrection. All functions called in process context must disable IRQs when they try to get get that lock to to prevent any reschedule due to IRQs. Signed-off-by: Sven Eckelmann Acked-by: Marek Lindner Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/send.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/send.c b/drivers/staging/batman-adv/send.c index fc4953f50dff..49b1534b8f77 100644 --- a/drivers/staging/batman-adv/send.c +++ b/drivers/staging/batman-adv/send.c @@ -338,12 +338,13 @@ static void forw_packet_free(struct forw_packet *forw_packet) static void _add_bcast_packet_to_list(struct forw_packet *forw_packet, unsigned long send_time) { + unsigned long flags; INIT_HLIST_NODE(&forw_packet->list); /* add new packet to packet list */ - spin_lock(&forw_bcast_list_lock); + spin_lock_irqsave(&forw_bcast_list_lock, flags); hlist_add_head(&forw_packet->list, &forw_bcast_list); - spin_unlock(&forw_bcast_list_lock); + spin_unlock_irqrestore(&forw_bcast_list_lock, flags); /* start timer for this packet */ INIT_DELAYED_WORK(&forw_packet->delayed_work, @@ -382,10 +383,11 @@ void send_outstanding_bcast_packet(struct work_struct *work) container_of(work, struct delayed_work, work); struct forw_packet *forw_packet = container_of(delayed_work, struct forw_packet, delayed_work); + unsigned long flags; - spin_lock(&forw_bcast_list_lock); + spin_lock_irqsave(&forw_bcast_list_lock, flags); hlist_del(&forw_packet->list); - spin_unlock(&forw_bcast_list_lock); + spin_unlock_irqrestore(&forw_bcast_list_lock, flags); /* rebroadcast packet */ rcu_read_lock(); @@ -436,24 +438,25 @@ void purge_outstanding_packets(void) { struct forw_packet *forw_packet; struct hlist_node *tmp_node, *safe_tmp_node; + unsigned long flags; bat_dbg(DBG_BATMAN, "purge_outstanding_packets()\n"); /* free bcast list */ - spin_lock(&forw_bcast_list_lock); + spin_lock_irqsave(&forw_bcast_list_lock, flags); hlist_for_each_entry_safe(forw_packet, tmp_node, safe_tmp_node, &forw_bcast_list, list) { - spin_unlock(&forw_bcast_list_lock); + spin_unlock_irqrestore(&forw_bcast_list_lock, flags); /** * send_outstanding_bcast_packet() will lock the list to * delete the item from the list */ cancel_delayed_work_sync(&forw_packet->delayed_work); - spin_lock(&forw_bcast_list_lock); + spin_lock_irqsave(&forw_bcast_list_lock, flags); } - spin_unlock(&forw_bcast_list_lock); + spin_unlock_irqrestore(&forw_bcast_list_lock, flags); /* free batman packet list */ spin_lock(&forw_bat_list_lock); -- cgit v1.2.3 From 9bbf1ecdb36e2395eecbf04229eaaedce3589db5 Mon Sep 17 00:00:00 2001 From: Linus Lüssing Date: Sat, 2 Jan 2010 11:30:42 +0100 Subject: Staging: batman-adv: Fixes rounding issues in vis.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patches fixes two rounding issues in vis.c for sending and purging vis packets. Before, the timers and timeouts always got rounded down to seconds, though we want a precision in milliseconds. This also fixes a kernel panic that occures when lowering the timer for sending vis packets (vis_interval) to less than 1000ms in main.c manually. Signed-off-by: Linus Lüssing Acked-by: Marek Lindner Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/vis.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/vis.c b/drivers/staging/batman-adv/vis.c index 086da871cd59..054631012138 100644 --- a/drivers/staging/batman-adv/vis.c +++ b/drivers/staging/batman-adv/vis.c @@ -377,7 +377,7 @@ static void purge_vis_packets(void) if (info == my_vis_info) /* never purge own data. */ continue; if (time_after(jiffies, - info->first_seen + (VIS_TIMEOUT/1000)*HZ)) { + info->first_seen + (VIS_TIMEOUT*HZ)/1000)) { hash_remove_bucket(vis_hash, &hashit); free_info(info); } @@ -556,6 +556,6 @@ void vis_quit(void) static void start_vis_timer(void) { queue_delayed_work(bat_event_workqueue, &vis_timer_wq, - (atomic_read(&vis_interval)/1000) * HZ); + (atomic_read(&vis_interval) * HZ) / 1000); } -- cgit v1.2.3 From b665aac8a7b44bbffc32dfff8543227704136ed5 Mon Sep 17 00:00:00 2001 From: Marek Lindner Date: Sat, 2 Jan 2010 11:30:43 +0100 Subject: Staging: batman-adv: fix minor orig table layout bug The originator table contained a TAB instead of a space which broke the layout as well as the batctl parser. Signed-off-by: Marek Lindner Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/proc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/proc.c b/drivers/staging/batman-adv/proc.c index 71668cfbdbf9..4afabad3abef 100644 --- a/drivers/staging/batman-adv/proc.c +++ b/drivers/staging/batman-adv/proc.c @@ -230,7 +230,7 @@ static int proc_originators_read(struct seq_file *seq, void *offset) addr_to_string(orig_str, orig_node->orig); addr_to_string(router_str, orig_node->router->addr); - seq_printf(seq, "%-17s (%3i) %17s [%10s]:", + seq_printf(seq, "%-17s (%3i) %17s [%10s]:", orig_str, orig_node->router->tq_avg, router_str, orig_node->router->if_incoming->dev); -- cgit v1.2.3 From b801fede6bd94a4b3b0bd4ba1f35f69a6b34158b Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 2 Jan 2010 11:30:44 +0100 Subject: Staging: batman-adv: moving vis output formats out of the kernel The batman-adv kernel module is able to output visualization data using the dot draw or JSON format. This patch transforms the output into a generic format (called vis raw). User space tool may convert the raw data to support a variety of formats without the need of modifying the kernel module. Signed-off-by: Andrew Lunn Signed-off-by: Marek Lindner Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/TODO | 11 --- drivers/staging/batman-adv/proc.c | 169 ++++++++++++++------------------------ drivers/staging/batman-adv/proc.h | 9 -- 3 files changed, 60 insertions(+), 129 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/TODO b/drivers/staging/batman-adv/TODO index 8c2b89e82ad7..b1e369cf9870 100644 --- a/drivers/staging/batman-adv/TODO +++ b/drivers/staging/batman-adv/TODO @@ -17,17 +17,6 @@ -> transtable_global (read-only) [outputs the global translation table] -> transtable_local (read-only) [outputs the local translation table] -=> vis "raw" data output -* the raw format shall replace dot draw / json to offer a neutral that can -* be converted -* the format (comma seperated entries): --> "mac" -> mac address of an originator (each line begins with it) --> "TQ mac value" -> src mac's link quality towards mac address --> "HNA mac" -> HNA announced by source mac --> "PRIMARY" -> this is a primary interface --> "SEC mac" -> secondary mac address of source (requires preceeding --> PRIMARY) - => logging * make use of printk %pM support instead of converting mac addresses * manually diff --git a/drivers/staging/batman-adv/proc.c b/drivers/staging/batman-adv/proc.c index 4afabad3abef..3ecf8e7684a5 100644 --- a/drivers/staging/batman-adv/proc.c +++ b/drivers/staging/batman-adv/proc.c @@ -322,166 +322,117 @@ static int proc_transt_global_open(struct inode *inode, struct file *file) return single_open(file, proc_transt_global_read, NULL); } -/* insert interface to the list of interfaces of one originator */ +/* While scanning for vis-entries of a particular vis-originator + * this list collects its interfaces to create a subgraph/cluster + * out of them later + */ +struct if_list_entry { + uint8_t addr[ETH_ALEN]; + bool primary; + struct hlist_node list; +}; +/* insert interface to the list of interfaces of one originator, if it + * does not already exist in the list */ static void proc_vis_insert_interface(const uint8_t *interface, - struct vis_if_list **if_entry, + struct hlist_head *if_list, bool primary) { - /* Did we get an empty list? (then insert imediately) */ - if (*if_entry == NULL) { - *if_entry = kmalloc(sizeof(struct vis_if_list), GFP_KERNEL); - if (*if_entry == NULL) + struct if_list_entry *entry; + struct hlist_node *pos; + + hlist_for_each_entry(entry, pos, if_list, list) { + if (compare_orig(entry->addr, (void *)interface)) return; + } - (*if_entry)->primary = primary; - (*if_entry)->next = NULL; - memcpy((*if_entry)->addr, interface, ETH_ALEN); - } else { - struct vis_if_list *head_if_entry = *if_entry; - /* Do we already have this interface in our list? */ - while (!compare_orig((*if_entry)->addr, (void *)interface)) { - - /* Or did we reach the end (then append the interface) */ - if ((*if_entry)->next == NULL) { - (*if_entry)->next = kmalloc(sizeof(struct vis_if_list), GFP_KERNEL); - if ((*if_entry)->next == NULL) - return; - - memcpy((*if_entry)->next->addr, interface, ETH_ALEN); - (*if_entry)->next->primary = primary; - (*if_entry)->next->next = NULL; - break; - } - *if_entry = (*if_entry)->next; + /* its a new address, add it to the list */ + entry = kmalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) + return; + memcpy(entry->addr, interface, ETH_ALEN); + entry->primary = primary; + hlist_add_head(&entry->list, if_list); +} + +static void proc_vis_read_prim_sec(struct seq_file *seq, + struct hlist_head *if_list) +{ + struct if_list_entry *entry; + struct hlist_node *pos, *n; + char tmp_addr_str[ETH_STR_LEN]; + + hlist_for_each_entry_safe(entry, pos, n, if_list, list) { + if (entry->primary) { + seq_printf(seq, "PRIMARY, "); + } else { + addr_to_string(tmp_addr_str, entry->addr); + seq_printf(seq, "SEC %s, ", tmp_addr_str); } - /* Rewind the list to its head */ - *if_entry = head_if_entry; + + hlist_del(&entry->list); + kfree(entry); } } -/* read an entry */ +/* read an entry */ static void proc_vis_read_entry(struct seq_file *seq, struct vis_info_entry *entry, - struct vis_if_list **if_entry, - uint8_t *vis_orig, - uint8_t current_format, - uint8_t first_line) + struct hlist_head *if_list, + uint8_t *vis_orig) { - char from[40]; char to[40]; - int int_part, frac_part; addr_to_string(to, entry->dest); if (entry->quality == 0) { -#ifndef VIS_SUBCLUSTERS_DISABLED - proc_vis_insert_interface(vis_orig, if_entry, true); -#endif /* VIS_SUBCLUSTERS_DISABLED */ - addr_to_string(from, vis_orig); - if (current_format == DOT_DRAW) { - seq_printf(seq, "\t\"%s\" -> \"%s\" [label=\"HNA\"]\n", - from, to); - } else { - seq_printf(seq, - "%s\t{ router : \"%s\", gateway : \"%s\", label : \"HNA\" }", - (first_line ? "" : ",\n"), from, to); - } + proc_vis_insert_interface(vis_orig, if_list, true); + seq_printf(seq, "HNA %s, ", to); } else { -#ifndef VIS_SUBCLUSTERS_DISABLED - proc_vis_insert_interface(entry->src, if_entry, compare_orig(entry->src, vis_orig)); -#endif /* VIS_SUBCLUSTERS_DISABLED */ - addr_to_string(from, entry->src); - - /* kernel has no printf-support for %f? it'd be better to return - * this in float. */ - - int_part = TQ_MAX_VALUE / entry->quality; - frac_part = 1000 * TQ_MAX_VALUE / entry->quality - int_part * 1000; - - if (current_format == DOT_DRAW) { - seq_printf(seq, - "\t\"%s\" -> \"%s\" [label=\"%d.%d\"]\n", - from, to, int_part, frac_part); - } else { - seq_printf(seq, - "%s\t{ router : \"%s\", neighbor : \"%s\", label : %d.%d }", - (first_line ? "" : ",\n"), from, to, int_part, frac_part); - } + proc_vis_insert_interface(entry->src, if_list, + compare_orig(entry->src, vis_orig)); + seq_printf(seq, "TQ %s %d, ", to, entry->quality); } } - static int proc_vis_read(struct seq_file *seq, void *offset) { HASHIT(hashit); struct vis_info *info; struct vis_info_entry *entries; - struct vis_if_list *if_entries = NULL; + HLIST_HEAD(vis_if_list); int i; - uint8_t current_format, first_line = 1; -#ifndef VIS_SUBCLUSTERS_DISABLED + uint8_t current_format; char tmp_addr_str[ETH_STR_LEN]; - struct vis_if_list *tmp_if_next; -#endif /* VIS_SUBCLUSTERS_DISABLED */ current_format = vis_format; rcu_read_lock(); if (list_empty(&if_list) || (!is_vis_server())) { rcu_read_unlock(); - if (current_format == DOT_DRAW) - seq_printf(seq, "digraph {\n}\n"); goto end; } rcu_read_unlock(); - if (current_format == DOT_DRAW) - seq_printf(seq, "digraph {\n"); - spin_lock(&vis_hash_lock); while (hash_iterate(vis_hash, &hashit)) { info = hashit.bucket->data; entries = (struct vis_info_entry *) ((char *)info + sizeof(struct vis_info)); + addr_to_string(tmp_addr_str, info->packet.vis_orig); + seq_printf(seq, "%s,", tmp_addr_str); for (i = 0; i < info->packet.entries; i++) { - proc_vis_read_entry(seq, &entries[i], &if_entries, - info->packet.vis_orig, - current_format, first_line); - if (first_line) - first_line = 0; + proc_vis_read_entry(seq, &entries[i], &vis_if_list, + info->packet.vis_orig); } -#ifndef VIS_SUBCLUSTERS_DISABLED - /* Generate subgraphs from the collected items */ - if (current_format == DOT_DRAW) { - - addr_to_string(tmp_addr_str, info->packet.vis_orig); - seq_printf(seq, "\tsubgraph \"cluster_%s\" {\n", tmp_addr_str); - while (if_entries != NULL) { - - addr_to_string(tmp_addr_str, if_entries->addr); - if (if_entries->primary) - seq_printf(seq, "\t\t\"%s\" [peripheries=2]\n", tmp_addr_str); - else - seq_printf(seq, "\t\t\"%s\"\n", tmp_addr_str); - - /* ... and empty the list while doing this */ - tmp_if_next = if_entries->next; - kfree(if_entries); - if_entries = tmp_if_next; - } - seq_printf(seq, "\t}\n"); - } -#endif /* VIS_SUBCLUSTERS_DISABLED */ + /* add primary/secondary records */ + proc_vis_read_prim_sec(seq, &vis_if_list); + seq_printf(seq, "\n"); } spin_unlock(&vis_hash_lock); - if (current_format == DOT_DRAW) - seq_printf(seq, "}\n"); - else - seq_printf(seq, "\n"); end: return 0; } diff --git a/drivers/staging/batman-adv/proc.h b/drivers/staging/batman-adv/proc.h index 16d3efdebe52..761c5f8f95f6 100644 --- a/drivers/staging/batman-adv/proc.h +++ b/drivers/staging/batman-adv/proc.h @@ -38,12 +38,3 @@ void cleanup_procfs(void); int setup_procfs(void); -/* While scanning for vis-entries of a particular vis-originator - * this list collects its interfaces to create a subgraph/cluster - * out of them later - */ -struct vis_if_list { - uint8_t addr[ETH_ALEN]; - bool primary; - struct vis_if_list *next; -}; -- cgit v1.2.3 From 6051d44cb1210e79b39143921b9e162983a03005 Mon Sep 17 00:00:00 2001 From: Linus Luessing Date: Sat, 2 Jan 2010 11:30:45 +0100 Subject: Staging: batman-adv: remove obsoleted vis_format /proc file batman-adv used to export the vis data using different formats that were switchable via /proc/net/batman-adv/vis_format. The various formats moved to user space and rendered this configuration switch useless. Signed-off-by: Linus Luessing Signed-off-by: Marek Lindner Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/proc.c | 79 +-------------------------------------- drivers/staging/batman-adv/vis.h | 5 --- 2 files changed, 1 insertion(+), 83 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/proc.c b/drivers/staging/batman-adv/proc.c index 3ecf8e7684a5..d0da0eae50f7 100644 --- a/drivers/staging/batman-adv/proc.c +++ b/drivers/staging/batman-adv/proc.c @@ -29,13 +29,11 @@ #include "vis.h" #include "compat.h" -static uint8_t vis_format = DOT_DRAW; - static struct proc_dir_entry *proc_batman_dir, *proc_interface_file; static struct proc_dir_entry *proc_orig_interval_file, *proc_originators_file; static struct proc_dir_entry *proc_transt_local_file; static struct proc_dir_entry *proc_transt_global_file; -static struct proc_dir_entry *proc_vis_file, *proc_vis_format_file; +static struct proc_dir_entry *proc_vis_file; static struct proc_dir_entry *proc_aggr_file; static int proc_interfaces_read(struct seq_file *seq, void *offset) @@ -401,11 +399,8 @@ static int proc_vis_read(struct seq_file *seq, void *offset) struct vis_info_entry *entries; HLIST_HEAD(vis_if_list); int i; - uint8_t current_format; char tmp_addr_str[ETH_STR_LEN]; - current_format = vis_format; - rcu_read_lock(); if (list_empty(&if_list) || (!is_vis_server())) { rcu_read_unlock(); @@ -471,55 +466,6 @@ static int proc_vis_open(struct inode *inode, struct file *file) return single_open(file, proc_vis_read, NULL); } -static int proc_vis_format_read(struct seq_file *seq, void *offset) -{ - uint8_t current_format = vis_format; - - seq_printf(seq, "[%c] %s\n", - (current_format == DOT_DRAW) ? 'x' : ' ', - VIS_FORMAT_DD_NAME); - seq_printf(seq, "[%c] %s\n", - (current_format == JSON) ? 'x' : ' ', - VIS_FORMAT_JSON_NAME); - return 0; -} - -static int proc_vis_format_open(struct inode *inode, struct file *file) -{ - return single_open(file, proc_vis_format_read, NULL); -} - -static ssize_t proc_vis_format_write(struct file *file, - const char __user *buffer, - size_t count, loff_t *ppos) -{ - char *vis_format_string; - int not_copied = 0; - - vis_format_string = kmalloc(count, GFP_KERNEL); - - if (!vis_format_string) - return -ENOMEM; - - not_copied = copy_from_user(vis_format_string, buffer, count); - vis_format_string[count - not_copied - 1] = 0; - - if (strcmp(vis_format_string, VIS_FORMAT_DD_NAME) == 0) { - printk(KERN_INFO "batman-adv:Setting VIS output format to: %s\n", - VIS_FORMAT_DD_NAME); - vis_format = DOT_DRAW; - } else if (strcmp(vis_format_string, VIS_FORMAT_JSON_NAME) == 0) { - printk(KERN_INFO "batman-adv:Setting VIS output format to: %s\n", - VIS_FORMAT_JSON_NAME); - vis_format = JSON; - } else - printk(KERN_ERR "batman-adv:Unknown VIS output format: %s\n", - vis_format_string); - - kfree(vis_format_string); - return count; -} - static int proc_aggr_read(struct seq_file *seq, void *offset) { seq_printf(seq, "%i\n", atomic_read(&aggregation_enabled)); @@ -583,15 +529,6 @@ static const struct file_operations proc_aggr_fops = { .release = single_release, }; -static const struct file_operations proc_vis_format_fops = { - .owner = THIS_MODULE, - .open = proc_vis_format_open, - .read = seq_read, - .write = proc_vis_format_write, - .llseek = seq_lseek, - .release = single_release, -}; - static const struct file_operations proc_vis_fops = { .owner = THIS_MODULE, .open = proc_vis_open, @@ -666,9 +603,6 @@ void cleanup_procfs(void) if (proc_vis_file) remove_proc_entry(PROC_FILE_VIS, proc_batman_dir); - if (proc_vis_format_file) - remove_proc_entry(PROC_FILE_VIS_FORMAT, proc_batman_dir); - if (proc_aggr_file) remove_proc_entry(PROC_FILE_AGGR, proc_batman_dir); @@ -755,17 +689,6 @@ int setup_procfs(void) return -EFAULT; } - proc_vis_format_file = create_proc_entry(PROC_FILE_VIS_FORMAT, - S_IWUSR | S_IRUGO, - proc_batman_dir); - if (proc_vis_format_file) { - proc_vis_format_file->proc_fops = &proc_vis_format_fops; - } else { - printk(KERN_ERR "batman-adv: Registering the '/proc/net/%s/%s' file failed\n", PROC_ROOT_DIR, PROC_FILE_VIS_FORMAT); - cleanup_procfs(); - return -EFAULT; - } - proc_aggr_file = create_proc_entry(PROC_FILE_AGGR, S_IWUSR | S_IRUGO, proc_batman_dir); if (proc_aggr_file) { diff --git a/drivers/staging/batman-adv/vis.h b/drivers/staging/batman-adv/vis.h index 276fabab4e88..ff88a43fc674 100644 --- a/drivers/staging/batman-adv/vis.h +++ b/drivers/staging/batman-adv/vis.h @@ -45,11 +45,6 @@ struct recvlist_node { uint8_t mac[ETH_ALEN]; }; -enum vis_formats { - DOT_DRAW, - JSON, -}; - extern struct hashtable_t *vis_hash; extern spinlock_t vis_hash_lock; -- cgit v1.2.3 From e9b764506aeb06ada6a7d0a24eda3e6eb70bade1 Mon Sep 17 00:00:00 2001 From: Marek Lindner Date: Sat, 2 Jan 2010 11:30:46 +0100 Subject: Staging: batman-adv: splitting /proc vis file into vis_server and vis_data The /proc vis file was used to enable/disable the vis server and to output the vis data at the same time. This behaviour was confusing and lacked a proper method to display the current vis server status. This patch seperates the 2 functionalities: * use vis_server to enable/disable the vis server and to retrieve its status * use vis_data to retrieve the vis raw data (if the server is enabled) Signed-off-by: Marek Lindner Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/proc.c | 172 +++++++++++++++---------------------- drivers/staging/batman-adv/proc.h | 4 +- drivers/staging/batman-adv/types.h | 10 +++ drivers/staging/batman-adv/vis.c | 62 +++++++++++++ drivers/staging/batman-adv/vis.h | 6 ++ 5 files changed, 151 insertions(+), 103 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/proc.c b/drivers/staging/batman-adv/proc.c index d0da0eae50f7..a4f19e1dfc7b 100644 --- a/drivers/staging/batman-adv/proc.c +++ b/drivers/staging/batman-adv/proc.c @@ -33,7 +33,7 @@ static struct proc_dir_entry *proc_batman_dir, *proc_interface_file; static struct proc_dir_entry *proc_orig_interval_file, *proc_originators_file; static struct proc_dir_entry *proc_transt_local_file; static struct proc_dir_entry *proc_transt_global_file; -static struct proc_dir_entry *proc_vis_file; +static struct proc_dir_entry *proc_vis_srv_file, *proc_vis_data_file; static struct proc_dir_entry *proc_aggr_file; static int proc_interfaces_read(struct seq_file *seq, void *offset) @@ -320,79 +320,55 @@ static int proc_transt_global_open(struct inode *inode, struct file *file) return single_open(file, proc_transt_global_read, NULL); } -/* While scanning for vis-entries of a particular vis-originator - * this list collects its interfaces to create a subgraph/cluster - * out of them later - */ -struct if_list_entry { - uint8_t addr[ETH_ALEN]; - bool primary; - struct hlist_node list; -}; - -/* insert interface to the list of interfaces of one originator, if it - * does not already exist in the list */ -static void proc_vis_insert_interface(const uint8_t *interface, - struct hlist_head *if_list, - bool primary) +/* setting the mode of the vis server by the user */ +static ssize_t proc_vis_srv_write(struct file *file, const char __user * buffer, + size_t count, loff_t *ppos) { - struct if_list_entry *entry; - struct hlist_node *pos; + char *vis_mode_string; + int not_copied = 0; - hlist_for_each_entry(entry, pos, if_list, list) { - if (compare_orig(entry->addr, (void *)interface)) - return; - } + vis_mode_string = kmalloc(count, GFP_KERNEL); - /* its a new address, add it to the list */ - entry = kmalloc(sizeof(*entry), GFP_KERNEL); - if (!entry) - return; - memcpy(entry->addr, interface, ETH_ALEN); - entry->primary = primary; - hlist_add_head(&entry->list, if_list); + if (!vis_mode_string) + return -ENOMEM; + + not_copied = copy_from_user(vis_mode_string, buffer, count); + vis_mode_string[count - not_copied - 1] = 0; + + if ((strcmp(vis_mode_string, "client") == 0) || + (strcmp(vis_mode_string, "disabled") == 0)) { + printk(KERN_INFO "batman-adv:Setting VIS mode to client (disabling vis server)\n"); + vis_set_mode(VIS_TYPE_CLIENT_UPDATE); + } else if ((strcmp(vis_mode_string, "server") == 0) || + (strcmp(vis_mode_string, "enabled") == 0)) { + printk(KERN_INFO "batman-adv:Setting VIS mode to server (enabling vis server)\n"); + vis_set_mode(VIS_TYPE_SERVER_SYNC); + } else + printk(KERN_ERR "batman-adv:Unknown VIS mode: %s\n", + vis_mode_string); + + kfree(vis_mode_string); + return count; } -static void proc_vis_read_prim_sec(struct seq_file *seq, - struct hlist_head *if_list) +static int proc_vis_srv_read(struct seq_file *seq, void *offset) { - struct if_list_entry *entry; - struct hlist_node *pos, *n; - char tmp_addr_str[ETH_STR_LEN]; + int vis_server = is_vis_server(); - hlist_for_each_entry_safe(entry, pos, n, if_list, list) { - if (entry->primary) { - seq_printf(seq, "PRIMARY, "); - } else { - addr_to_string(tmp_addr_str, entry->addr); - seq_printf(seq, "SEC %s, ", tmp_addr_str); - } + seq_printf(seq, "[%c] client mode (server disabled) \n", + (!vis_server) ? 'x' : ' '); + seq_printf(seq, "[%c] server mode (server enabled) \n", + (vis_server) ? 'x' : ' '); - hlist_del(&entry->list); - kfree(entry); - } + return 0; } -/* read an entry */ -static void proc_vis_read_entry(struct seq_file *seq, - struct vis_info_entry *entry, - struct hlist_head *if_list, - uint8_t *vis_orig) +static int proc_vis_srv_open(struct inode *inode, struct file *file) { - char to[40]; - - addr_to_string(to, entry->dest); - if (entry->quality == 0) { - proc_vis_insert_interface(vis_orig, if_list, true); - seq_printf(seq, "HNA %s, ", to); - } else { - proc_vis_insert_interface(entry->src, if_list, - compare_orig(entry->src, vis_orig)); - seq_printf(seq, "TQ %s %d, ", to, entry->quality); - } + return single_open(file, proc_vis_srv_read, NULL); } -static int proc_vis_read(struct seq_file *seq, void *offset) +static int proc_vis_data_read(struct seq_file *seq, void *offset) { HASHIT(hashit); struct vis_info *info; @@ -432,38 +408,9 @@ end: return 0; } -/* setting the mode of the vis server by the user */ -static ssize_t proc_vis_write(struct file *file, const char __user * buffer, - size_t count, loff_t *ppos) +static int proc_vis_data_open(struct inode *inode, struct file *file) { - char *vis_mode_string; - int not_copied = 0; - - vis_mode_string = kmalloc(count, GFP_KERNEL); - - if (!vis_mode_string) - return -ENOMEM; - - not_copied = copy_from_user(vis_mode_string, buffer, count); - vis_mode_string[count - not_copied - 1] = 0; - - if (strcmp(vis_mode_string, "client") == 0) { - printk(KERN_INFO "batman-adv:Setting VIS mode to client\n"); - vis_set_mode(VIS_TYPE_CLIENT_UPDATE); - } else if (strcmp(vis_mode_string, "server") == 0) { - printk(KERN_INFO "batman-adv:Setting VIS mode to server\n"); - vis_set_mode(VIS_TYPE_SERVER_SYNC); - } else - printk(KERN_ERR "batman-adv:Unknown VIS mode: %s\n", - vis_mode_string); - - kfree(vis_mode_string); - return count; -} - -static int proc_vis_open(struct inode *inode, struct file *file) -{ - return single_open(file, proc_vis_read, NULL); + return single_open(file, proc_vis_data_read, NULL); } static int proc_aggr_read(struct seq_file *seq, void *offset) @@ -529,11 +476,20 @@ static const struct file_operations proc_aggr_fops = { .release = single_release, }; -static const struct file_operations proc_vis_fops = { +static const struct file_operations proc_vis_srv_fops = { .owner = THIS_MODULE, - .open = proc_vis_open, + .open = proc_vis_srv_open, .read = seq_read, - .write = proc_vis_write, + .write = proc_vis_srv_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static const struct file_operations proc_vis_data_fops = { + .owner = THIS_MODULE, + .open = proc_vis_data_open, + .read = seq_read, + .write = proc_dummy_write, .llseek = seq_lseek, .release = single_release, }; @@ -600,8 +556,11 @@ void cleanup_procfs(void) if (proc_interface_file) remove_proc_entry(PROC_FILE_INTERFACES, proc_batman_dir); - if (proc_vis_file) - remove_proc_entry(PROC_FILE_VIS, proc_batman_dir); + if (proc_vis_data_file) + remove_proc_entry(PROC_FILE_VIS_DATA, proc_batman_dir); + + if (proc_vis_srv_file) + remove_proc_entry(PROC_FILE_VIS_SRV, proc_batman_dir); if (proc_aggr_file) remove_proc_entry(PROC_FILE_AGGR, proc_batman_dir); @@ -679,12 +638,23 @@ int setup_procfs(void) return -EFAULT; } - proc_vis_file = create_proc_entry(PROC_FILE_VIS, S_IWUSR | S_IRUGO, + proc_vis_srv_file = create_proc_entry(PROC_FILE_VIS_SRV, + S_IWUSR | S_IRUGO, + proc_batman_dir); + if (proc_vis_srv_file) { + proc_vis_srv_file->proc_fops = &proc_vis_srv_fops; + } else { + printk(KERN_ERR "batman-adv: Registering the '/proc/net/%s/%s' file failed\n", PROC_ROOT_DIR, PROC_FILE_VIS_SRV); + cleanup_procfs(); + return -EFAULT; + } + + proc_vis_data_file = create_proc_entry(PROC_FILE_VIS_DATA, S_IRUGO, proc_batman_dir); - if (proc_vis_file) { - proc_vis_file->proc_fops = &proc_vis_fops; + if (proc_vis_data_file) { + proc_vis_data_file->proc_fops = &proc_vis_data_fops; } else { - printk(KERN_ERR "batman-adv: Registering the '/proc/net/%s/%s' file failed\n", PROC_ROOT_DIR, PROC_FILE_VIS); + printk(KERN_ERR "batman-adv: Registering the '/proc/net/%s/%s' file failed\n", PROC_ROOT_DIR, PROC_FILE_VIS_DATA); cleanup_procfs(); return -EFAULT; } diff --git a/drivers/staging/batman-adv/proc.h b/drivers/staging/batman-adv/proc.h index 761c5f8f95f6..cd690e0f3e44 100644 --- a/drivers/staging/batman-adv/proc.h +++ b/drivers/staging/batman-adv/proc.h @@ -31,8 +31,8 @@ #define PROC_FILE_LOG_LEVEL "log_level" #define PROC_FILE_TRANST_LOCAL "transtable_local" #define PROC_FILE_TRANST_GLOBAL "transtable_global" -#define PROC_FILE_VIS "vis" -#define PROC_FILE_VIS_FORMAT "vis_format" +#define PROC_FILE_VIS_SRV "vis_server" +#define PROC_FILE_VIS_DATA "vis_data" #define PROC_FILE_AGGR "aggregate_ogm" void cleanup_procfs(void); diff --git a/drivers/staging/batman-adv/types.h b/drivers/staging/batman-adv/types.h index 9739358caca3..d708e6f15b37 100644 --- a/drivers/staging/batman-adv/types.h +++ b/drivers/staging/batman-adv/types.h @@ -121,4 +121,14 @@ struct forw_packet { /* structure for forw_list maintaining packet struct batman_if *if_incoming; }; +/* While scanning for vis-entries of a particular vis-originator + * this list collects its interfaces to create a subgraph/cluster + * out of them later + */ +struct if_list_entry { + uint8_t addr[ETH_ALEN]; + bool primary; + struct hlist_node list; +}; + #endif diff --git a/drivers/staging/batman-adv/vis.c b/drivers/staging/batman-adv/vis.c index 054631012138..62ee77396418 100644 --- a/drivers/staging/batman-adv/vis.c +++ b/drivers/staging/batman-adv/vis.c @@ -114,6 +114,68 @@ static int vis_info_choose(void *data, int size) return hash % size; } +/* insert interface to the list of interfaces of one originator, if it + * does not already exist in the list */ +static void proc_vis_insert_interface(const uint8_t *interface, + struct hlist_head *if_list, + bool primary) +{ + struct if_list_entry *entry; + struct hlist_node *pos; + + hlist_for_each_entry(entry, pos, if_list, list) { + if (compare_orig(entry->addr, (void *)interface)) + return; + } + + /* its a new address, add it to the list */ + entry = kmalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) + return; + memcpy(entry->addr, interface, ETH_ALEN); + entry->primary = primary; + hlist_add_head(&entry->list, if_list); +} + +void proc_vis_read_prim_sec(struct seq_file *seq, + struct hlist_head *if_list) +{ + struct if_list_entry *entry; + struct hlist_node *pos, *n; + char tmp_addr_str[ETH_STR_LEN]; + + hlist_for_each_entry_safe(entry, pos, n, if_list, list) { + if (entry->primary) { + seq_printf(seq, "PRIMARY, "); + } else { + addr_to_string(tmp_addr_str, entry->addr); + seq_printf(seq, "SEC %s, ", tmp_addr_str); + } + + hlist_del(&entry->list); + kfree(entry); + } +} + +/* read an entry */ +void proc_vis_read_entry(struct seq_file *seq, + struct vis_info_entry *entry, + struct hlist_head *if_list, + uint8_t *vis_orig) +{ + char to[40]; + + addr_to_string(to, entry->dest); + if (entry->quality == 0) { + proc_vis_insert_interface(vis_orig, if_list, true); + seq_printf(seq, "HNA %s, ", to); + } else { + proc_vis_insert_interface(entry->src, if_list, + compare_orig(entry->src, vis_orig)); + seq_printf(seq, "TQ %s %d, ", to, entry->quality); + } +} + /* tries to add one entry to the receive list. */ static void recv_list_add(struct list_head *recv_list, char *mac) { diff --git a/drivers/staging/batman-adv/vis.h b/drivers/staging/batman-adv/vis.h index ff88a43fc674..2e24258e69a4 100644 --- a/drivers/staging/batman-adv/vis.h +++ b/drivers/staging/batman-adv/vis.h @@ -50,6 +50,12 @@ extern spinlock_t vis_hash_lock; void vis_set_mode(int mode); int is_vis_server(void); +void proc_vis_read_entry(struct seq_file *seq, + struct vis_info_entry *entry, + struct hlist_head *if_list, + uint8_t *vis_orig); +void proc_vis_read_prim_sec(struct seq_file *seq, + struct hlist_head *if_list); void receive_server_sync_packet(struct vis_packet *vis_packet, int vis_info_len); void receive_client_update_packet(struct vis_packet *vis_packet, -- cgit v1.2.3 From c4bf05d3960981a4291bcc9580f3d73eb4dcbe84 Mon Sep 17 00:00:00 2001 From: Simon Wunderlich Date: Sat, 2 Jan 2010 11:30:47 +0100 Subject: Staging: batman-adv: check all kmalloc()s there are some kmallocs left which are not checked whether they succeeds or not, which might lead to corrupted data structures if the system memory is full. This patch should clean up the remaining unchecked kmalloc()s. Signed-off-by: Simon Wunderlich Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/originator.c | 22 ++++++++++++++++++++- drivers/staging/batman-adv/routing.c | 27 +++++++++++++++++++++----- drivers/staging/batman-adv/translation-table.c | 18 +++++++++-------- 3 files changed, 53 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/originator.c b/drivers/staging/batman-adv/originator.c index 6a1fdf2b702b..71bd2cf421c4 100644 --- a/drivers/staging/batman-adv/originator.c +++ b/drivers/staging/batman-adv/originator.c @@ -77,6 +77,9 @@ create_neighbor(struct orig_node *orig_node, struct orig_node *orig_neigh_node, bat_dbg(DBG_BATMAN, "Creating new last-hop neighbor of originator\n"); neigh_node = kmalloc(sizeof(struct neigh_node), GFP_ATOMIC); + if (!neigh_node) + return NULL; + memset(neigh_node, 0, sizeof(struct neigh_node)); INIT_LIST_HEAD(&neigh_node->list); @@ -127,6 +130,9 @@ struct orig_node *get_orig_node(uint8_t *addr) bat_dbg(DBG_BATMAN, "Creating new originator: %s \n", orig_str); orig_node = kmalloc(sizeof(struct orig_node), GFP_ATOMIC); + if (!orig_node) + return NULL; + memset(orig_node, 0, sizeof(struct orig_node)); INIT_LIST_HEAD(&orig_node->neigh_list); @@ -138,13 +144,20 @@ struct orig_node *get_orig_node(uint8_t *addr) size = num_ifs * sizeof(TYPE_OF_WORD) * NUM_WORDS; orig_node->bcast_own = kmalloc(size, GFP_ATOMIC); + if (!orig_node->bcast_own) + goto free_orig_node; + memset(orig_node->bcast_own, 0, size); size = num_ifs * sizeof(uint8_t); orig_node->bcast_own_sum = kmalloc(size, GFP_ATOMIC); + if (!orig_node->bcast_own_sum) + goto free_bcast_own; + memset(orig_node->bcast_own_sum, 0, size); - hash_add(orig_hash, orig_node); + if (hash_add(orig_hash, orig_node) < 0) + goto free_bcast_own_sum; if (orig_hash->elements * 4 > orig_hash->size) { swaphash = hash_resize(orig_hash, orig_hash->size * 2); @@ -157,6 +170,13 @@ struct orig_node *get_orig_node(uint8_t *addr) } return orig_node; +free_bcast_own_sum: + kfree(orig_node->bcast_own_sum); +free_bcast_own: + kfree(orig_node->bcast_own); +free_orig_node: + kfree(orig_node); + return NULL; } static bool purge_orig_neighbors(struct orig_node *orig_node, diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index 37c53822e9c9..f8464cad30b7 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -154,11 +154,14 @@ static int isBidirectionalNeigh(struct orig_node *orig_node, neigh_node = tmp_neigh_node; } - if (neigh_node == NULL) + if (!neigh_node) neigh_node = create_neighbor(orig_node, orig_neigh_node, orig_neigh_node->orig, if_incoming); + /* create_neighbor failed, return 0 */ + if (!neigh_node) + return 0; neigh_node->last_valid = jiffies; } else { @@ -172,11 +175,14 @@ static int isBidirectionalNeigh(struct orig_node *orig_node, neigh_node = tmp_neigh_node; } - if (neigh_node == NULL) + if (!neigh_node) neigh_node = create_neighbor(orig_neigh_node, orig_neigh_node, orig_neigh_node->orig, if_incoming); + /* create_neighbor failed, return 0 */ + if (!neigh_node) + return 0; } orig_node->last_valid = jiffies; @@ -260,11 +266,19 @@ static void update_orig(struct orig_node *orig_node, struct ethhdr *ethhdr, ring_buffer_avg(tmp_neigh_node->tq_recv); } - if (neigh_node == NULL) + if (!neigh_node) { + struct orig_node *orig_tmp; + + orig_tmp = get_orig_node(ethhdr->h_source); + if (!orig_tmp) + return; + neigh_node = create_neighbor(orig_node, - get_orig_node(ethhdr->h_source), + orig_tmp, ethhdr->h_source, if_incoming); - else + if (!neigh_node) + return; + } else bat_dbg(DBG_BATMAN, "Updating existing last-hop neighbor of originator\n"); @@ -444,6 +458,9 @@ void receive_bat_packet(struct ethhdr *ethhdr, orig_neigh_node = get_orig_node(ethhdr->h_source); + if (!orig_neigh_node) + return; + /* neighbor has to indicate direct link and it has to * come via the corresponding interface */ /* if received seqno equals last send seqno save new diff --git a/drivers/staging/batman-adv/translation-table.c b/drivers/staging/batman-adv/translation-table.c index 088715ba8dbd..8c8136b71628 100644 --- a/drivers/staging/batman-adv/translation-table.c +++ b/drivers/staging/batman-adv/translation-table.c @@ -317,14 +317,16 @@ void hna_global_add_orig(struct orig_node *orig_node, hna_buff_count++; } - orig_node->hna_buff_len = hna_buff_len; - - if (orig_node->hna_buff_len > 0) { - orig_node->hna_buff = kmalloc(orig_node->hna_buff_len, - GFP_ATOMIC); - memcpy(orig_node->hna_buff, hna_buff, orig_node->hna_buff_len); - } else { - orig_node->hna_buff = NULL; + /* initialize, and overwrite if malloc succeeds */ + orig_node->hna_buff = NULL; + orig_node->hna_buff_len = 0; + + if (hna_buff_len > 0) { + orig_node->hna_buff = kmalloc(hna_buff_len, GFP_ATOMIC); + if (orig_node->hna_buff) { + memcpy(orig_node->hna_buff, hna_buff, hna_buff_len); + orig_node->hna_buff_len = hna_buff_len; + } } spin_lock_irqsave(&hna_global_hash_lock, flags); -- cgit v1.2.3 From e70171957a3ac67fd62af0c66efe7b7749121899 Mon Sep 17 00:00:00 2001 From: Simon Wunderlich Date: Sat, 2 Jan 2010 11:30:48 +0100 Subject: Staging: batman-adv: receive packets directly using skbs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch removes the (ugly and racy) packet receiving thread and the kernel socket usage. Instead, packets are received directly by registering the ethernet type and handling skbs instead of self-allocated buffers. Some consequences and comments: * we don't copy the payload data when forwarding/sending/receiving data anymore. This should boost performance. * packets from/to different interfaces can be (theoretically) processed simultaneously. Only the big originator hash lock might be in the way. * no more polling or sleeping/wakeup/scheduling issues when receiving packets * this might introduce new race conditions. * aggregation and vis code still use packet buffers and are not (yet) converted. * all spinlocks were converted to irqsave/restore versions to solve some lifelock issues when preempted. This might be overkill, some of these locks might be reverted later. * skb copies are only done if neccesary to avoid overhead performance differences: * we made some "benchmarks" with intel laptops. * bandwidth on Gigabit Ethernet increased from ~500 MBit/s to ~920 MBit/s * ping latency decresed from ~2ms to ~0.2 ms I did some tests on my 9 node qemu environment and could confirm that usual sending/receiving, forwarding, vis, batctl ping etc works. Signed-off-by: Simon Wunderlich Acked-by: Sven Eckelmann Acked-by: Marek Lindner Acked-by: Linus Lüssing Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/aggregation.c | 13 +- drivers/staging/batman-adv/device.c | 24 +- drivers/staging/batman-adv/hard-interface.c | 154 +++++--- drivers/staging/batman-adv/hard-interface.h | 4 + drivers/staging/batman-adv/main.c | 29 +- drivers/staging/batman-adv/originator.c | 18 +- drivers/staging/batman-adv/proc.c | 10 +- drivers/staging/batman-adv/routing.c | 563 ++++++++++++---------------- drivers/staging/batman-adv/routing.h | 8 +- drivers/staging/batman-adv/send.c | 93 +++-- drivers/staging/batman-adv/send.h | 5 +- drivers/staging/batman-adv/soft-interface.c | 76 ++-- drivers/staging/batman-adv/soft-interface.h | 3 +- drivers/staging/batman-adv/types.h | 2 +- drivers/staging/batman-adv/vis.c | 55 +-- 15 files changed, 548 insertions(+), 509 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/aggregation.c b/drivers/staging/batman-adv/aggregation.c index 9c6e681f6fb6..7917322a7e2a 100644 --- a/drivers/staging/batman-adv/aggregation.c +++ b/drivers/staging/batman-adv/aggregation.c @@ -96,6 +96,7 @@ static void new_aggregated_packet(unsigned char *packet_buff, int own_packet) { struct forw_packet *forw_packet_aggr; + unsigned long flags; forw_packet_aggr = kmalloc(sizeof(struct forw_packet), GFP_ATOMIC); if (!forw_packet_aggr) @@ -115,6 +116,7 @@ static void new_aggregated_packet(unsigned char *packet_buff, packet_buff, forw_packet_aggr->packet_len); + forw_packet_aggr->skb = NULL; forw_packet_aggr->own = own_packet; forw_packet_aggr->if_incoming = if_incoming; forw_packet_aggr->num_packets = 0; @@ -126,9 +128,9 @@ static void new_aggregated_packet(unsigned char *packet_buff, forw_packet_aggr->direct_link_flags |= 1; /* add new packet to packet list */ - spin_lock(&forw_bat_list_lock); + spin_lock_irqsave(&forw_bat_list_lock, flags); hlist_add_head(&forw_packet_aggr->list, &forw_bat_list); - spin_unlock(&forw_bat_list_lock); + spin_unlock_irqrestore(&forw_bat_list_lock, flags); /* start timer for this packet */ INIT_DELAYED_WORK(&forw_packet_aggr->delayed_work, @@ -168,9 +170,10 @@ void add_bat_packet_to_list(unsigned char *packet_buff, int packet_len, struct batman_packet *batman_packet = (struct batman_packet *)packet_buff; bool direct_link = batman_packet->flags & DIRECTLINK ? 1 : 0; + unsigned long flags; /* find position for the packet in the forward queue */ - spin_lock(&forw_bat_list_lock); + spin_lock_irqsave(&forw_bat_list_lock, flags); /* own packets are not to be aggregated */ if ((atomic_read(&aggregation_enabled)) && (!own_packet)) { hlist_for_each_entry(forw_packet_pos, tmp_node, &forw_bat_list, @@ -191,7 +194,7 @@ void add_bat_packet_to_list(unsigned char *packet_buff, int packet_len, * suitable aggregation packet found */ if (forw_packet_aggr == NULL) { /* the following section can run without the lock */ - spin_unlock(&forw_bat_list_lock); + spin_unlock_irqrestore(&forw_bat_list_lock, flags); new_aggregated_packet(packet_buff, packet_len, send_time, direct_link, if_incoming, own_packet); @@ -199,7 +202,7 @@ void add_bat_packet_to_list(unsigned char *packet_buff, int packet_len, aggregate(forw_packet_aggr, packet_buff, packet_len, direct_link); - spin_unlock(&forw_bat_list_lock); + spin_unlock_irqrestore(&forw_bat_list_lock, flags); } } diff --git a/drivers/staging/batman-adv/device.c b/drivers/staging/batman-adv/device.c index 92cf8d56a5f2..ab2b0b17d9ea 100644 --- a/drivers/staging/batman-adv/device.c +++ b/drivers/staging/batman-adv/device.c @@ -133,8 +133,9 @@ int bat_device_release(struct inode *inode, struct file *file) (struct device_client *)file->private_data; struct device_packet *device_packet; struct list_head *list_pos, *list_pos_tmp; + unsigned long flags; - spin_lock(&device_client->lock); + spin_lock_irqsave(&device_client->lock, flags); /* for all packets in the queue ... */ list_for_each_safe(list_pos, list_pos_tmp, &device_client->queue_list) { @@ -146,7 +147,7 @@ int bat_device_release(struct inode *inode, struct file *file) } device_client_hash[device_client->index] = NULL; - spin_unlock(&device_client->lock); + spin_unlock_irqrestore(&device_client->lock, flags); kfree(device_client); dec_module_count(); @@ -161,6 +162,7 @@ ssize_t bat_device_read(struct file *file, char __user *buf, size_t count, (struct device_client *)file->private_data; struct device_packet *device_packet; int error; + unsigned long flags; if ((file->f_flags & O_NONBLOCK) && (device_client->queue_len == 0)) return -EAGAIN; @@ -177,14 +179,14 @@ ssize_t bat_device_read(struct file *file, char __user *buf, size_t count, if (error) return error; - spin_lock(&device_client->lock); + spin_lock_irqsave(&device_client->lock, flags); device_packet = list_first_entry(&device_client->queue_list, struct device_packet, list); list_del(&device_packet->list); device_client->queue_len--; - spin_unlock(&device_client->lock); + spin_unlock_irqrestore(&device_client->lock, flags); error = __copy_to_user(buf, &device_packet->icmp_packet, sizeof(struct icmp_packet)); @@ -205,6 +207,7 @@ ssize_t bat_device_write(struct file *file, const char __user *buff, struct icmp_packet icmp_packet; struct orig_node *orig_node; struct batman_if *batman_if; + unsigned long flags; if (len < sizeof(struct icmp_packet)) { bat_dbg(DBG_BATMAN, "batman-adv:Error - can't send packet from char device: invalid packet size\n"); @@ -239,7 +242,7 @@ ssize_t bat_device_write(struct file *file, const char __user *buff, if (atomic_read(&module_state) != MODULE_ACTIVE) goto dst_unreach; - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); orig_node = ((struct orig_node *)hash_find(orig_hash, icmp_packet.dst)); if (!orig_node) @@ -261,11 +264,11 @@ ssize_t bat_device_write(struct file *file, const char __user *buff, sizeof(struct icmp_packet), batman_if, orig_node->router->addr); - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); goto out; unlock: - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); dst_unreach: icmp_packet.msg_type = DESTINATION_UNREACHABLE; bat_device_add_packet(device_client, &icmp_packet); @@ -290,6 +293,7 @@ void bat_device_add_packet(struct device_client *device_client, struct icmp_packet *icmp_packet) { struct device_packet *device_packet; + unsigned long flags; device_packet = kmalloc(sizeof(struct device_packet), GFP_KERNEL); @@ -300,12 +304,12 @@ void bat_device_add_packet(struct device_client *device_client, memcpy(&device_packet->icmp_packet, icmp_packet, sizeof(struct icmp_packet)); - spin_lock(&device_client->lock); + spin_lock_irqsave(&device_client->lock, flags); /* while waiting for the lock the device_client could have been * deleted */ if (!device_client_hash[icmp_packet->uid]) { - spin_unlock(&device_client->lock); + spin_unlock_irqrestore(&device_client->lock, flags); kfree(device_packet); return; } @@ -322,7 +326,7 @@ void bat_device_add_packet(struct device_client *device_client, device_client->queue_len--; } - spin_unlock(&device_client->lock); + spin_unlock_irqrestore(&device_client->lock, flags); wake_up(&device_client->queue_wait); } diff --git a/drivers/staging/batman-adv/hard-interface.c b/drivers/staging/batman-adv/hard-interface.c index 7c885926b167..cc59c307a420 100644 --- a/drivers/staging/batman-adv/hard-interface.c +++ b/drivers/staging/batman-adv/hard-interface.c @@ -153,9 +153,6 @@ void hardif_deactivate_interface(struct batman_if *batman_if) if (batman_if->if_active != IF_ACTIVE) return; - if (batman_if->raw_sock) - sock_release(batman_if->raw_sock); - /** * batman_if->net_dev has been acquired by dev_get_by_name() in * proc_interfaces_write() and has to be unreferenced. @@ -164,9 +161,6 @@ void hardif_deactivate_interface(struct batman_if *batman_if) if (batman_if->net_dev) dev_put(batman_if->net_dev); - batman_if->raw_sock = NULL; - batman_if->net_dev = NULL; - batman_if->if_active = IF_INACTIVE; active_ifs--; @@ -177,9 +171,6 @@ void hardif_deactivate_interface(struct batman_if *batman_if) /* (re)activate given interface. */ static void hardif_activate_interface(struct batman_if *batman_if) { - struct sockaddr_ll bind_addr; - int retval; - if (batman_if->if_active != IF_INACTIVE) return; @@ -191,35 +182,8 @@ static void hardif_activate_interface(struct batman_if *batman_if) if (!batman_if->net_dev) goto dev_err; - retval = sock_create_kern(PF_PACKET, SOCK_RAW, - __constant_htons(ETH_P_BATMAN), - &batman_if->raw_sock); - - if (retval < 0) { - printk(KERN_ERR "batman-adv:Can't create raw socket: %i\n", - retval); - goto sock_err; - } - - bind_addr.sll_family = AF_PACKET; - bind_addr.sll_ifindex = batman_if->net_dev->ifindex; - bind_addr.sll_protocol = 0; /* is set by the kernel */ - - retval = kernel_bind(batman_if->raw_sock, - (struct sockaddr *)&bind_addr, sizeof(bind_addr)); - - if (retval < 0) { - printk(KERN_ERR "batman-adv:Can't create bind raw socket: %i\n", - retval); - goto bind_err; - } - check_known_mac_addr(batman_if->net_dev->dev_addr); - batman_if->raw_sock->sk->sk_user_data = - batman_if->raw_sock->sk->sk_data_ready; - batman_if->raw_sock->sk->sk_data_ready = batman_data_ready; - addr_to_string(batman_if->addr_str, batman_if->net_dev->dev_addr); memcpy(((struct batman_packet *)(batman_if->packet_buff))->orig, @@ -239,12 +203,7 @@ static void hardif_activate_interface(struct batman_if *batman_if) return; -bind_err: - sock_release(batman_if->raw_sock); -sock_err: - dev_put(batman_if->net_dev); dev_err: - batman_if->raw_sock = NULL; batman_if->net_dev = NULL; } @@ -318,6 +277,7 @@ int hardif_add_interface(char *dev, int if_num) struct batman_if *batman_if; struct batman_packet *batman_packet; struct orig_node *orig_node; + unsigned long flags; HASHIT(hashit); batman_if = kmalloc(sizeof(struct batman_if), GFP_KERNEL); @@ -327,7 +287,6 @@ int hardif_add_interface(char *dev, int if_num) return -1; } - batman_if->raw_sock = NULL; batman_if->net_dev = NULL; if ((if_num == 0) && (num_hna > 0)) @@ -375,17 +334,17 @@ int hardif_add_interface(char *dev, int if_num) /* resize all orig nodes because orig_node->bcast_own(_sum) depend on * if_num */ - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); while (hash_iterate(orig_hash, &hashit)) { orig_node = hashit.bucket->data; if (resize_orig(orig_node, if_num) == -1) { - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); goto out; } } - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); if (!hardif_is_interface_up(batman_if->dev)) printk(KERN_ERR "batman-adv:Not using interface %s (retrying later): interface not active\n", batman_if->dev); @@ -443,6 +402,111 @@ out: return NOTIFY_DONE; } +/* find batman interface by netdev. assumes rcu_read_lock on */ +static struct batman_if *find_batman_if(struct net_device *dev) +{ + struct batman_if *batman_if; + + rcu_read_lock(); + list_for_each_entry_rcu(batman_if, &if_list, list) { + if (batman_if->net_dev == dev) { + rcu_read_unlock(); + return batman_if; + } + } + rcu_read_unlock(); + return NULL; +} + + +/* receive a packet with the batman ethertype coming on a hard + * interface */ +int batman_skb_recv(struct sk_buff *skb, struct net_device *dev, + struct packet_type *ptype, struct net_device *orig_dev) +{ + struct batman_packet *batman_packet; + struct batman_if *batman_if; + struct net_device_stats *stats; + int ret; + + skb = skb_share_check(skb, GFP_ATOMIC); + + if (skb == NULL) + goto err_free; + + /* packet should hold at least type and version */ + if (unlikely(skb_headlen(skb) < 2)) + goto err_free; + + /* expect a valid ethernet header here. */ + if (unlikely(skb->mac_len != sizeof(struct ethhdr) + || !skb_mac_header(skb))) + goto err_free; + + batman_if = find_batman_if(skb->dev); + if (!batman_if) + goto err_free; + + stats = &skb->dev->stats; + stats->rx_packets++; + stats->rx_bytes += skb->len; + + batman_packet = (struct batman_packet *)skb->data; + + if (batman_packet->version != COMPAT_VERSION) { + bat_dbg(DBG_BATMAN, + "Drop packet: incompatible batman version (%i)\n", + batman_packet->version); + goto err_free; + } + + /* all receive handlers return whether they received or reused + * the supplied skb. if not, we have to free the skb. */ + + switch (batman_packet->packet_type) { + /* batman originator packet */ + case BAT_PACKET: + ret = recv_bat_packet(skb, batman_if); + break; + + /* batman icmp packet */ + case BAT_ICMP: + ret = recv_icmp_packet(skb); + break; + + /* unicast packet */ + case BAT_UNICAST: + ret = recv_unicast_packet(skb); + break; + + /* broadcast packet */ + case BAT_BCAST: + ret = recv_bcast_packet(skb); + break; + + /* vis packet */ + case BAT_VIS: + ret = recv_vis_packet(skb); + break; + default: + ret = NET_RX_DROP; + } + if (ret == NET_RX_DROP) + kfree_skb(skb); + + /* return NET_RX_SUCCESS in any case as we + * most probably dropped the packet for + * routing-logical reasons. */ + + return NET_RX_SUCCESS; + +err_free: + kfree_skb(skb); + return NET_RX_DROP; + +} + + struct notifier_block hard_if_notifier = { .notifier_call = hard_if_event, }; diff --git a/drivers/staging/batman-adv/hard-interface.h b/drivers/staging/batman-adv/hard-interface.h index 742358c00c0e..97c6ecb9e087 100644 --- a/drivers/staging/batman-adv/hard-interface.h +++ b/drivers/staging/batman-adv/hard-interface.h @@ -32,5 +32,9 @@ void hardif_deactivate_interface(struct batman_if *batman_if); char hardif_get_active_if_num(void); void hardif_check_interfaces_status(void); void hardif_check_interfaces_status_wq(struct work_struct *work); +int batman_skb_recv(struct sk_buff *skb, + struct net_device *dev, + struct packet_type *ptype, + struct net_device *orig_dev); int hardif_min_mtu(void); void update_min_mtu(void); diff --git a/drivers/staging/batman-adv/main.c b/drivers/staging/batman-adv/main.c index 434c600a6a47..c73350415697 100644 --- a/drivers/staging/batman-adv/main.c +++ b/drivers/staging/batman-adv/main.c @@ -50,11 +50,14 @@ int16_t num_ifs; struct net_device *soft_device; -static struct task_struct *kthread_task; - unsigned char broadcastAddr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; atomic_t module_state; +static struct packet_type batman_adv_packet_type __read_mostly = { + .type = cpu_to_be16(ETH_P_BATMAN), + .func = batman_skb_recv, +}; + struct workqueue_struct *bat_event_workqueue; #ifdef CONFIG_BATMAN_ADV_DEBUG @@ -113,6 +116,7 @@ int init_module(void) } register_netdevice_notifier(&hard_if_notifier); + dev_add_pack(&batman_adv_packet_type); printk(KERN_INFO "batman-adv:B.A.T.M.A.N. advanced %s%s (compatibility version %i) loaded \n", SOURCE_VERSION, REVISION_VERSION_STR, COMPAT_VERSION); @@ -135,6 +139,8 @@ void cleanup_module(void) soft_device = NULL; } + dev_remove_pack(&batman_adv_packet_type); + unregister_netdevice_notifier(&hard_if_notifier); cleanup_procfs(); @@ -162,16 +168,6 @@ void activate_module(void) if (vis_init() < 1) goto err; - /* (re)start kernel thread for packet processing */ - if (!kthread_task) { - kthread_task = kthread_run(packet_recv_thread, NULL, "batman-adv"); - - if (IS_ERR(kthread_task)) { - printk(KERN_ERR "batman-adv:Unable to start packet receive thread\n"); - kthread_task = NULL; - } - } - update_min_mtu(); atomic_set(&module_state, MODULE_ACTIVE); goto end; @@ -193,14 +189,7 @@ void shutdown_module(void) vis_quit(); - /* deactivate kernel thread for packet processing (if running) */ - if (kthread_task) { - atomic_set(&exit_cond, 1); - wake_up_interruptible(&thread_wait); - kthread_stop(kthread_task); - - kthread_task = NULL; - } + /* TODO: unregister BATMAN pack */ originator_free(); diff --git a/drivers/staging/batman-adv/originator.c b/drivers/staging/batman-adv/originator.c index 71bd2cf421c4..1c0a3cec8466 100644 --- a/drivers/staging/batman-adv/originator.c +++ b/drivers/staging/batman-adv/originator.c @@ -37,35 +37,38 @@ static void start_purge_timer(void) int originator_init(void) { + unsigned long flags; if (orig_hash) return 1; - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); orig_hash = hash_new(128, compare_orig, choose_orig); if (!orig_hash) goto err; - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); start_purge_timer(); return 1; err: - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); return 0; } void originator_free(void) { + unsigned long flags; + if (!orig_hash) return; cancel_delayed_work_sync(&purge_orig_wq); - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); hash_delete(orig_hash, free_orig_node); orig_hash = NULL; - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); } struct neigh_node * @@ -243,8 +246,9 @@ void purge_orig(struct work_struct *work) { HASHIT(hashit); struct orig_node *orig_node; + unsigned long flags; - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); /* for all origins... */ while (hash_iterate(orig_hash, &hashit)) { @@ -255,7 +259,7 @@ void purge_orig(struct work_struct *work) } } - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); start_purge_timer(); } diff --git a/drivers/staging/batman-adv/proc.c b/drivers/staging/batman-adv/proc.c index a4f19e1dfc7b..33dae941a5c9 100644 --- a/drivers/staging/batman-adv/proc.c +++ b/drivers/staging/batman-adv/proc.c @@ -189,6 +189,7 @@ static int proc_originators_read(struct seq_file *seq, void *offset) struct neigh_node *neigh_node; int batman_count = 0; char orig_str[ETH_STR_LEN], router_str[ETH_STR_LEN]; + unsigned long flags; rcu_read_lock(); if (list_empty(&if_list)) { @@ -211,7 +212,7 @@ static int proc_originators_read(struct seq_file *seq, void *offset) ((struct batman_if *)if_list.next)->addr_str); rcu_read_unlock(); - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); while (hash_iterate(orig_hash, &hashit)) { @@ -242,7 +243,7 @@ static int proc_originators_read(struct seq_file *seq, void *offset) } - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); if (batman_count == 0) seq_printf(seq, "No batman nodes in range ... \n"); @@ -376,6 +377,7 @@ static int proc_vis_data_read(struct seq_file *seq, void *offset) HLIST_HEAD(vis_if_list); int i; char tmp_addr_str[ETH_STR_LEN]; + unsigned long flags; rcu_read_lock(); if (list_empty(&if_list) || (!is_vis_server())) { @@ -385,7 +387,7 @@ static int proc_vis_data_read(struct seq_file *seq, void *offset) rcu_read_unlock(); - spin_lock(&vis_hash_lock); + spin_lock_irqsave(&vis_hash_lock, flags); while (hash_iterate(vis_hash, &hashit)) { info = hashit.bucket->data; entries = (struct vis_info_entry *) @@ -402,7 +404,7 @@ static int proc_vis_data_read(struct seq_file *seq, void *offset) proc_vis_read_prim_sec(seq, &vis_if_list); seq_printf(seq, "\n"); } - spin_unlock(&vis_hash_lock); + spin_unlock_irqrestore(&vis_hash_lock, flags); end: return 0; diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index f8464cad30b7..e0d093f5d524 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -36,15 +36,16 @@ DECLARE_WAIT_QUEUE_HEAD(thread_wait); -static atomic_t data_ready_cond; atomic_t exit_cond; + void slide_own_bcast_window(struct batman_if *batman_if) { HASHIT(hashit); struct orig_node *orig_node; TYPE_OF_WORD *word; + unsigned long flags; - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); while (hash_iterate(orig_hash, &hashit)) { orig_node = hashit.bucket->data; @@ -55,7 +56,7 @@ void slide_own_bcast_window(struct batman_if *batman_if) bit_packet_count(word); } - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); } static void update_HNA(struct orig_node *orig_node, @@ -365,10 +366,9 @@ static char count_real_packets(struct ethhdr *ethhdr, } void receive_bat_packet(struct ethhdr *ethhdr, - struct batman_packet *batman_packet, - unsigned char *hna_buff, - int hna_buff_len, - struct batman_if *if_incoming) + struct batman_packet *batman_packet, + unsigned char *hna_buff, int hna_buff_len, + struct batman_if *if_incoming) { struct batman_if *batman_if; struct orig_node *orig_neigh_node, *orig_node; @@ -566,95 +566,118 @@ void receive_bat_packet(struct ethhdr *ethhdr, 0, hna_buff_len, if_incoming); } - -static int receive_raw_packet(struct socket *raw_sock, - unsigned char *packet_buff, int packet_buff_len) +int recv_bat_packet(struct sk_buff *skb, + struct batman_if *batman_if) { - struct kvec iov; - struct msghdr msg; + struct ethhdr *ethhdr; + unsigned long flags; - iov.iov_base = packet_buff; - iov.iov_len = packet_buff_len; + /* drop packet if it has not necessary minimum size */ + if (skb_headlen(skb) < sizeof(struct batman_packet)) + return NET_RX_DROP; - msg.msg_flags = MSG_DONTWAIT; /* non-blocking */ - msg.msg_name = NULL; - msg.msg_namelen = 0; - msg.msg_control = NULL; + ethhdr = (struct ethhdr *)skb_mac_header(skb); - return kernel_recvmsg(raw_sock, &msg, &iov, 1, packet_buff_len, - MSG_DONTWAIT); -} - -static void recv_bat_packet(struct ethhdr *ethhdr, - unsigned char *packet_buff, - int result, - struct batman_if *batman_if) -{ /* packet with broadcast indication but unicast recipient */ if (!is_bcast(ethhdr->h_dest)) - return; + return NET_RX_DROP; /* packet with broadcast sender address */ if (is_bcast(ethhdr->h_source)) - return; - - /* drop packet if it has not at least one batman packet as payload */ - if (result < sizeof(struct ethhdr) + sizeof(struct batman_packet)) - return; - - spin_lock(&orig_hash_lock); + return NET_RX_DROP; + + spin_lock_irqsave(&orig_hash_lock, flags); + /* TODO: we use headlen instead of "length", because + * only this data is paged in. */ + /* TODO: is another skb_copy needed here? there will be + * written on the data, but nobody (?) should further use + * this data */ receive_aggr_bat_packet(ethhdr, - packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), + skb->data, + skb_headlen(skb), batman_if); - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); + + kfree_skb(skb); + return NET_RX_SUCCESS; } -static void recv_my_icmp_packet(struct ethhdr *ethhdr, - struct icmp_packet *icmp_packet, - unsigned char *packet_buff, - int result) +static int recv_my_icmp_packet(struct sk_buff *skb) { struct orig_node *orig_node; + struct icmp_packet *icmp_packet; + struct ethhdr *ethhdr; + struct sk_buff *skb_old; + struct batman_if *batman_if; + int ret; + unsigned long flags; + uint8_t dstaddr[ETH_ALEN]; + + icmp_packet = (struct icmp_packet *) skb->data; + ethhdr = (struct ethhdr *) skb_mac_header(skb); /* add data to device queue */ if (icmp_packet->msg_type != ECHO_REQUEST) { bat_device_receive_packet(icmp_packet); - return; + return NET_RX_DROP; } /* answer echo request (ping) */ /* get routing information */ - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); orig_node = ((struct orig_node *)hash_find(orig_hash, icmp_packet->orig)); + ret = NET_RX_DROP; if ((orig_node != NULL) && (orig_node->batman_if != NULL) && (orig_node->router != NULL)) { + + /* don't lock while sending the packets ... we therefore + * copy the required data before sending */ + batman_if = orig_node->batman_if; + memcpy(dstaddr, orig_node->router->addr, ETH_ALEN); + spin_unlock_irqrestore(&orig_hash_lock, flags); + + /* create a copy of the skb, if needed, to modify it. */ + skb_old = NULL; + if (!skb_clone_writable(skb, sizeof(struct icmp_packet))) { + skb_old = skb; + skb = skb_copy(skb, GFP_ATOMIC); + if (!skb) + return NET_RX_DROP; + icmp_packet = (struct icmp_packet *) skb->data; + kfree_skb(skb_old); + } + memcpy(icmp_packet->dst, icmp_packet->orig, ETH_ALEN); memcpy(icmp_packet->orig, ethhdr->h_dest, ETH_ALEN); icmp_packet->msg_type = ECHO_REPLY; icmp_packet->ttl = TTL; - send_raw_packet(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - orig_node->batman_if, - orig_node->router->addr); - } + send_skb_packet(skb, batman_if, dstaddr); + ret = NET_RX_SUCCESS; - spin_unlock(&orig_hash_lock); - return; + } else + spin_unlock_irqrestore(&orig_hash_lock, flags); + + return ret; } -static void recv_icmp_ttl_exceeded(struct icmp_packet *icmp_packet, - struct ethhdr *ethhdr, - unsigned char *packet_buff, - int result, - struct batman_if *batman_if) +static int recv_icmp_ttl_exceeded(struct sk_buff *skb) { unsigned char src_str[ETH_STR_LEN], dst_str[ETH_STR_LEN]; struct orig_node *orig_node; + struct icmp_packet *icmp_packet; + struct ethhdr *ethhdr; + struct sk_buff *skb_old; + struct batman_if *batman_if; + int ret; + unsigned long flags; + uint8_t dstaddr[ETH_ALEN]; + + icmp_packet = (struct icmp_packet *) skb->data; + ethhdr = (struct ethhdr *) skb_mac_header(skb); addr_to_string(src_str, icmp_packet->orig); addr_to_string(dst_str, icmp_packet->dst); @@ -663,74 +686,93 @@ static void recv_icmp_ttl_exceeded(struct icmp_packet *icmp_packet, /* send TTL exceeded if packet is an echo request (traceroute) */ if (icmp_packet->msg_type != ECHO_REQUEST) - return; + return NET_RX_DROP; /* get routing information */ - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); orig_node = ((struct orig_node *) hash_find(orig_hash, icmp_packet->orig)); + ret = NET_RX_DROP; if ((orig_node != NULL) && (orig_node->batman_if != NULL) && (orig_node->router != NULL)) { + + /* don't lock while sending the packets ... we therefore + * copy the required data before sending */ + batman_if = orig_node->batman_if; + memcpy(dstaddr, orig_node->router->addr, ETH_ALEN); + spin_unlock_irqrestore(&orig_hash_lock, flags); + + /* create a copy of the skb, if needed, to modify it. */ + if (!skb_clone_writable(skb, sizeof(struct icmp_packet))) { + skb_old = skb; + skb = skb_copy(skb, GFP_ATOMIC); + if (!skb) + return NET_RX_DROP; + icmp_packet = (struct icmp_packet *) skb->data; + kfree_skb(skb_old); + } + memcpy(icmp_packet->dst, icmp_packet->orig, ETH_ALEN); memcpy(icmp_packet->orig, ethhdr->h_dest, ETH_ALEN); icmp_packet->msg_type = TTL_EXCEEDED; icmp_packet->ttl = TTL; - send_raw_packet(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - orig_node->batman_if, - orig_node->router->addr); + send_skb_packet(skb, batman_if, dstaddr); + ret = NET_RX_SUCCESS; - } + } else + spin_unlock_irqrestore(&orig_hash_lock, flags); - spin_unlock(&orig_hash_lock); + return ret; } - -static void recv_icmp_packet(struct ethhdr *ethhdr, - unsigned char *packet_buff, - int result, - struct batman_if *batman_if) +int recv_icmp_packet(struct sk_buff *skb) { struct icmp_packet *icmp_packet; + struct ethhdr *ethhdr; struct orig_node *orig_node; + struct sk_buff *skb_old; + struct batman_if *batman_if; + int hdr_size = sizeof(struct icmp_packet); + int ret; + unsigned long flags; + uint8_t dstaddr[ETH_ALEN]; + + /* drop packet if it has not necessary minimum size */ + if (skb_headlen(skb) < hdr_size) + return NET_RX_DROP; + + ethhdr = (struct ethhdr *)skb_mac_header(skb); /* packet with unicast indication but broadcast recipient */ if (is_bcast(ethhdr->h_dest)) - return; + return NET_RX_DROP; /* packet with broadcast sender address */ if (is_bcast(ethhdr->h_source)) - return; + return NET_RX_DROP; /* not for me */ if (!is_my_mac(ethhdr->h_dest)) - return; + return NET_RX_DROP; - /* drop packet if it has not necessary minimum size */ - if (result < sizeof(struct ethhdr) + sizeof(struct icmp_packet)) - return; - - icmp_packet = (struct icmp_packet *) - (packet_buff + sizeof(struct ethhdr)); + icmp_packet = (struct icmp_packet *) skb->data; /* packet for me */ if (is_my_mac(icmp_packet->dst)) - recv_my_icmp_packet(ethhdr, icmp_packet, packet_buff, result); + return recv_my_icmp_packet(skb); /* TTL exceeded */ - if (icmp_packet->ttl < 2) { - recv_icmp_ttl_exceeded(icmp_packet, ethhdr, packet_buff, result, - batman_if); - return; + if (icmp_packet->ttl < 2) + return recv_icmp_ttl_exceeded(skb); - } + ret = NET_RX_DROP; /* get routing information */ - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); orig_node = ((struct orig_node *) hash_find(orig_hash, icmp_packet->dst)); @@ -738,133 +780,169 @@ static void recv_icmp_packet(struct ethhdr *ethhdr, (orig_node->batman_if != NULL) && (orig_node->router != NULL)) { + /* don't lock while sending the packets ... we therefore + * copy the required data before sending */ + batman_if = orig_node->batman_if; + memcpy(dstaddr, orig_node->router->addr, ETH_ALEN); + spin_unlock_irqrestore(&orig_hash_lock, flags); + + /* create a copy of the skb, if needed, to modify it. */ + if (!skb_clone_writable(skb, sizeof(struct icmp_packet))) { + skb_old = skb; + skb = skb_copy(skb, GFP_ATOMIC); + if (!skb) + return NET_RX_DROP; + icmp_packet = (struct icmp_packet *) skb->data; + kfree_skb(skb_old); + } + /* decrement ttl */ icmp_packet->ttl--; /* route it */ - send_raw_packet(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - orig_node->batman_if, - orig_node->router->addr); - } - spin_unlock(&orig_hash_lock); + send_skb_packet(skb, batman_if, dstaddr); + ret = NET_RX_SUCCESS; + + } else + spin_unlock_irqrestore(&orig_hash_lock, flags); + + return ret; } -static void recv_unicast_packet(struct ethhdr *ethhdr, - unsigned char *packet_buff, - int result, - struct batman_if *batman_if) +int recv_unicast_packet(struct sk_buff *skb) { struct unicast_packet *unicast_packet; unsigned char src_str[ETH_STR_LEN], dst_str[ETH_STR_LEN]; struct orig_node *orig_node; - int hdr_size = sizeof(struct ethhdr) + sizeof(struct unicast_packet); + struct ethhdr *ethhdr; + struct batman_if *batman_if; + struct sk_buff *skb_old; + uint8_t dstaddr[ETH_ALEN]; + int hdr_size = sizeof(struct unicast_packet); + int ret; + unsigned long flags; + + /* drop packet if it has not necessary minimum size */ + if (skb_headlen(skb) < hdr_size) + return NET_RX_DROP; + + ethhdr = (struct ethhdr *) skb_mac_header(skb); /* packet with unicast indication but broadcast recipient */ if (is_bcast(ethhdr->h_dest)) - return; + return NET_RX_DROP; /* packet with broadcast sender address */ if (is_bcast(ethhdr->h_source)) - return; + return NET_RX_DROP; /* not for me */ if (!is_my_mac(ethhdr->h_dest)) - return; - - /* drop packet if it has not necessary minimum size */ - if (result < hdr_size) - return; + return NET_RX_DROP; - unicast_packet = (struct unicast_packet *) - (packet_buff + sizeof(struct ethhdr)); + unicast_packet = (struct unicast_packet *) skb->data; /* packet for me */ if (is_my_mac(unicast_packet->dest)) { - interface_rx(soft_device, packet_buff + hdr_size, - result - hdr_size); - return; - + interface_rx(skb, hdr_size); + return NET_RX_SUCCESS; } /* TTL exceeded */ if (unicast_packet->ttl < 2) { - addr_to_string(src_str, ((struct ethhdr *) - (unicast_packet + 1))->h_source); - addr_to_string(dst_str, unicast_packet->dest); + addr_to_string(src_str, ethhdr->h_source); + addr_to_string(dst_str, ethhdr->h_dest); printk(KERN_WARNING "batman-adv:Warning - can't send packet from %s to %s: ttl exceeded\n", src_str, dst_str); - return; + return NET_RX_DROP; } + ret = NET_RX_DROP; /* get routing information */ - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); orig_node = ((struct orig_node *) hash_find(orig_hash, unicast_packet->dest)); if ((orig_node != NULL) && (orig_node->batman_if != NULL) && (orig_node->router != NULL)) { + + /* don't lock while sending the packets ... we therefore + * copy the required data before sending */ + batman_if = orig_node->batman_if; + memcpy(dstaddr, orig_node->router->addr, ETH_ALEN); + spin_unlock_irqrestore(&orig_hash_lock, flags); + + /* create a copy of the skb, if needed, to modify it. */ + if (!skb_clone_writable(skb, sizeof(struct unicast_packet))) { + skb_old = skb; + skb = skb_copy(skb, GFP_ATOMIC); + if (!skb) + return NET_RX_DROP; + unicast_packet = (struct unicast_packet *) skb->data; + kfree_skb(skb_old); + } /* decrement ttl */ unicast_packet->ttl--; /* route it */ - send_raw_packet(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr), - orig_node->batman_if, - orig_node->router->addr); - } - spin_unlock(&orig_hash_lock); + send_skb_packet(skb, batman_if, dstaddr); + ret = NET_RX_SUCCESS; + + } else + spin_unlock_irqrestore(&orig_hash_lock, flags); + + return ret; } -static void recv_bcast_packet(struct ethhdr *ethhdr, - unsigned char *packet_buff, - int result, - struct batman_if *batman_if) +int recv_bcast_packet(struct sk_buff *skb) { struct orig_node *orig_node; struct bcast_packet *bcast_packet; - int hdr_size = sizeof(struct ethhdr) + sizeof(struct bcast_packet); + struct ethhdr *ethhdr; + int hdr_size = sizeof(struct bcast_packet); + unsigned long flags; + + /* drop packet if it has not necessary minimum size */ + if (skb_headlen(skb) < hdr_size) + return NET_RX_DROP; + + ethhdr = (struct ethhdr *)skb_mac_header(skb); /* packet with broadcast indication but unicast recipient */ if (!is_bcast(ethhdr->h_dest)) - return; + return NET_RX_DROP; /* packet with broadcast sender address */ if (is_bcast(ethhdr->h_source)) - return; - - /* drop packet if it has not necessary minimum size */ - if (result < hdr_size) - return; + return NET_RX_DROP; /* ignore broadcasts sent by myself */ if (is_my_mac(ethhdr->h_source)) - return; + return NET_RX_DROP; - bcast_packet = (struct bcast_packet *) - (packet_buff + sizeof(struct ethhdr)); + bcast_packet = (struct bcast_packet *) skb->data; /* ignore broadcasts originated by myself */ if (is_my_mac(bcast_packet->orig)) - return; + return NET_RX_DROP; - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); orig_node = ((struct orig_node *) hash_find(orig_hash, bcast_packet->orig)); if (orig_node == NULL) { - spin_unlock(&orig_hash_lock); - return; + spin_unlock_irqrestore(&orig_hash_lock, flags); + return NET_RX_DROP; } /* check flood history */ if (get_bit_status(orig_node->bcast_bits, orig_node->last_bcast_seqno, ntohs(bcast_packet->seqno))) { - spin_unlock(&orig_hash_lock); - return; + spin_unlock_irqrestore(&orig_hash_lock, flags); + return NET_RX_DROP; } /* mark broadcast in flood history */ @@ -873,211 +951,58 @@ static void recv_bcast_packet(struct ethhdr *ethhdr, orig_node->last_bcast_seqno, 1)) orig_node->last_bcast_seqno = ntohs(bcast_packet->seqno); - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); + + /* rebroadcast packet */ + add_bcast_packet_to_list(skb); /* broadcast for me */ - interface_rx(soft_device, packet_buff + hdr_size, result - hdr_size); + interface_rx(skb, hdr_size); - /* rebroadcast packet */ - add_bcast_packet_to_list(packet_buff + sizeof(struct ethhdr), - result - sizeof(struct ethhdr)); + return NET_RX_SUCCESS; } -static void recv_vis_packet(struct ethhdr *ethhdr, - unsigned char *packet_buff, - int result) +int recv_vis_packet(struct sk_buff *skb) { struct vis_packet *vis_packet; - int hdr_size = sizeof(struct ethhdr) + sizeof(struct vis_packet); - int vis_info_len; + struct ethhdr *ethhdr; + int hdr_size = sizeof(struct vis_packet); + int ret; - /* drop if too short. */ - if (result < hdr_size) - return; + if (skb_headlen(skb) < hdr_size) + return NET_RX_DROP; + + vis_packet = (struct vis_packet *) skb->data; + ethhdr = (struct ethhdr *)skb_mac_header(skb); /* not for me */ if (!is_my_mac(ethhdr->h_dest)) - return; - - vis_packet = (struct vis_packet *)(packet_buff + sizeof(struct ethhdr)); - vis_info_len = result - hdr_size; + return NET_RX_DROP; /* ignore own packets */ if (is_my_mac(vis_packet->vis_orig)) - return; + return NET_RX_DROP; if (is_my_mac(vis_packet->sender_orig)) - return; + return NET_RX_DROP; switch (vis_packet->vis_type) { case VIS_TYPE_SERVER_SYNC: - receive_server_sync_packet(vis_packet, vis_info_len); + /* TODO: handle fragmented skbs properly */ + receive_server_sync_packet(vis_packet, skb_headlen(skb)); + ret = NET_RX_SUCCESS; break; case VIS_TYPE_CLIENT_UPDATE: - receive_client_update_packet(vis_packet, vis_info_len); + /* TODO: handle fragmented skbs properly */ + receive_client_update_packet(vis_packet, skb_headlen(skb)); + ret = NET_RX_SUCCESS; break; default: /* ignore unknown packet */ + ret = NET_RX_DROP; break; } -} - -static int recv_one_packet(struct batman_if *batman_if, - unsigned char *packet_buff) -{ - int result; - struct ethhdr *ethhdr; - struct batman_packet *batman_packet; - - result = receive_raw_packet(batman_if->raw_sock, packet_buff, - PACKBUFF_SIZE); - if (result <= 0) - return result; - - if (result < sizeof(struct ethhdr) + 2) - return 0; - - ethhdr = (struct ethhdr *)packet_buff; - batman_packet = (struct batman_packet *) - (packet_buff + sizeof(struct ethhdr)); - - if (batman_packet->version != COMPAT_VERSION) { - bat_dbg(DBG_BATMAN, - "Drop packet: incompatible batman version (%i)\n", - batman_packet->version); - return 0; - } - - switch (batman_packet->packet_type) { - /* batman originator packet */ - case BAT_PACKET: - recv_bat_packet(ethhdr, packet_buff, result, batman_if); - break; - - /* batman icmp packet */ - case BAT_ICMP: - recv_icmp_packet(ethhdr, packet_buff, result, batman_if); - break; - - /* unicast packet */ - case BAT_UNICAST: - recv_unicast_packet(ethhdr, packet_buff, result, batman_if); - break; - - /* broadcast packet */ - case BAT_BCAST: - recv_bcast_packet(ethhdr, - packet_buff, result, batman_if); - break; - - /* vis packet */ - case BAT_VIS: - recv_vis_packet(ethhdr, packet_buff, result); - break; - } - return 0; -} - - -static int discard_one_packet(struct batman_if *batman_if, - unsigned char *packet_buff) -{ - int result = -EAGAIN; - - if (batman_if->raw_sock) { - result = receive_raw_packet(batman_if->raw_sock, - packet_buff, - PACKBUFF_SIZE); - } - return result; -} - - -static bool is_interface_active(struct batman_if *batman_if) -{ - if (batman_if->if_active != IF_ACTIVE) - return false; - - return true; -} - -static void service_interface(struct batman_if *batman_if, - unsigned char *packet_buff) - -{ - int result; - - do { - if (is_interface_active(batman_if)) - result = recv_one_packet(batman_if, packet_buff); - else - result = discard_one_packet(batman_if, packet_buff); - } while (result >= 0); - - /* we perform none blocking reads, so EAGAIN indicates there - are no more packets to read. Anything else is a real - error.*/ - - if ((result < 0) && (result != -EAGAIN)) - printk(KERN_ERR "batman-adv:Could not receive packet from interface %s: %i\n", batman_if->dev, result); -} - -static void service_interfaces(unsigned char *packet_buffer) -{ - struct batman_if *batman_if; - rcu_read_lock(); - list_for_each_entry_rcu(batman_if, &if_list, list) { - rcu_read_unlock(); - service_interface(batman_if, packet_buffer); - rcu_read_lock(); - } - rcu_read_unlock(); -} - - -int packet_recv_thread(void *data) -{ - unsigned char *packet_buff; - - atomic_set(&data_ready_cond, 0); - atomic_set(&exit_cond, 0); - packet_buff = kmalloc(PACKBUFF_SIZE, GFP_KERNEL); - if (!packet_buff) { - printk(KERN_ERR"batman-adv:Could allocate memory for the packet buffer. :(\n"); - return -1; - } - - while ((!kthread_should_stop()) && (!atomic_read(&exit_cond))) { - - wait_event_interruptible(thread_wait, - (atomic_read(&data_ready_cond) || - atomic_read(&exit_cond))); - - atomic_set(&data_ready_cond, 0); - - if (kthread_should_stop() || atomic_read(&exit_cond)) - break; - - service_interfaces(packet_buff); - } - kfree(packet_buff); - - /* do not exit until kthread_stop() is actually called, - * otherwise it will wait for us forever. */ - while (!kthread_should_stop()) - schedule(); - - return 0; -} - -void batman_data_ready(struct sock *sk, int len) -{ - void (*data_ready)(struct sock *, int) = sk->sk_user_data; - - data_ready(sk, len); - - atomic_set(&data_ready_cond, 1); - wake_up_interruptible(&thread_wait); + return ret; } diff --git a/drivers/staging/batman-adv/routing.h b/drivers/staging/batman-adv/routing.h index 890a4f53b553..c217241d0efd 100644 --- a/drivers/staging/batman-adv/routing.h +++ b/drivers/staging/batman-adv/routing.h @@ -25,8 +25,6 @@ extern wait_queue_head_t thread_wait; extern atomic_t exit_cond; void slide_own_bcast_window(struct batman_if *batman_if); -void batman_data_ready(struct sock *sk, int len); -int packet_recv_thread(void *data); void receive_bat_packet(struct ethhdr *ethhdr, struct batman_packet *batman_packet, unsigned char *hna_buff, int hna_buff_len, @@ -34,3 +32,9 @@ void receive_bat_packet(struct ethhdr *ethhdr, void update_routes(struct orig_node *orig_node, struct neigh_node *neigh_node, unsigned char *hna_buff, int hna_buff_len); +int recv_icmp_packet(struct sk_buff *skb); +int recv_unicast_packet(struct sk_buff *skb); +int recv_bcast_packet(struct sk_buff *skb); +int recv_vis_packet(struct sk_buff *skb); +int recv_bat_packet(struct sk_buff *skb, + struct batman_if *batman_if); diff --git a/drivers/staging/batman-adv/send.c b/drivers/staging/batman-adv/send.c index 49b1534b8f77..fd48f3fa2d88 100644 --- a/drivers/staging/batman-adv/send.c +++ b/drivers/staging/batman-adv/send.c @@ -23,6 +23,7 @@ #include "send.h" #include "routing.h" #include "translation-table.h" +#include "soft-interface.h" #include "hard-interface.h" #include "types.h" #include "vis.h" @@ -58,51 +59,69 @@ static unsigned long forward_send_time(void) return send_time; } -/* sends a raw packet. */ -void send_raw_packet(unsigned char *pack_buff, int pack_buff_len, - struct batman_if *batman_if, uint8_t *dst_addr) +/* send out an already prepared packet to the given address via the + * specified batman interface */ +int send_skb_packet(struct sk_buff *skb, + struct batman_if *batman_if, + uint8_t *dst_addr) { struct ethhdr *ethhdr; - struct sk_buff *skb; - int retval; - char *data; if (batman_if->if_active != IF_ACTIVE) - return; + goto send_skb_err; + + if (unlikely(!batman_if->net_dev)) + goto send_skb_err; if (!(batman_if->net_dev->flags & IFF_UP)) { printk(KERN_WARNING "batman-adv:Interface %s is not up - can't send packet via that interface!\n", batman_if->dev); - return; + goto send_skb_err; } - skb = dev_alloc_skb(pack_buff_len + sizeof(struct ethhdr)); - if (!skb) - return; - data = skb_put(skb, pack_buff_len + sizeof(struct ethhdr)); + /* push to the ethernet header. */ + if (my_skb_push(skb, sizeof(struct ethhdr)) < 0) + goto send_skb_err; - memcpy(data + sizeof(struct ethhdr), pack_buff, pack_buff_len); + skb_reset_mac_header(skb); - ethhdr = (struct ethhdr *) data; + ethhdr = (struct ethhdr *) skb_mac_header(skb); memcpy(ethhdr->h_source, batman_if->net_dev->dev_addr, ETH_ALEN); memcpy(ethhdr->h_dest, dst_addr, ETH_ALEN); ethhdr->h_proto = __constant_htons(ETH_P_BATMAN); - skb_reset_mac_header(skb); skb_set_network_header(skb, ETH_HLEN); skb->priority = TC_PRIO_CONTROL; skb->protocol = __constant_htons(ETH_P_BATMAN); + skb->dev = batman_if->net_dev; /* dev_queue_xmit() returns a negative result on error. However on * congestion and traffic shaping, it drops and returns NET_XMIT_DROP * (which is > 0). This will not be treated as an error. */ - retval = dev_queue_xmit(skb); - if (retval < 0) - printk(KERN_WARNING - "batman-adv:Can't write to raw socket: %i\n", - retval); + + return dev_queue_xmit(skb); +send_skb_err: + kfree_skb(skb); + return NET_XMIT_DROP; +} + +/* sends a raw packet. */ +void send_raw_packet(unsigned char *pack_buff, int pack_buff_len, + struct batman_if *batman_if, uint8_t *dst_addr) +{ + struct sk_buff *skb; + char *data; + + skb = dev_alloc_skb(pack_buff_len + sizeof(struct ethhdr)); + if (!skb) + return; + data = skb_put(skb, pack_buff_len + sizeof(struct ethhdr)); + memcpy(data + sizeof(struct ethhdr), pack_buff, pack_buff_len); + /* pull back to the batman "network header" */ + skb_pull(skb, sizeof(struct ethhdr)); + send_skb_packet(skb, batman_if, dst_addr); } /* Send a packet to a given interface */ @@ -331,6 +350,8 @@ void schedule_forward_packet(struct orig_node *orig_node, static void forw_packet_free(struct forw_packet *forw_packet) { + if (forw_packet->skb) + kfree_skb(forw_packet->skb); kfree(forw_packet->packet_buff); kfree(forw_packet); } @@ -353,7 +374,7 @@ static void _add_bcast_packet_to_list(struct forw_packet *forw_packet, send_time); } -void add_bcast_packet_to_list(unsigned char *packet_buff, int packet_len) +void add_bcast_packet_to_list(struct sk_buff *skb) { struct forw_packet *forw_packet; @@ -361,14 +382,16 @@ void add_bcast_packet_to_list(unsigned char *packet_buff, int packet_len) if (!forw_packet) return; - forw_packet->packet_buff = kmalloc(packet_len, GFP_ATOMIC); - if (!forw_packet->packet_buff) { + skb = skb_copy(skb, GFP_ATOMIC); + if (!skb) { kfree(forw_packet); return; } - forw_packet->packet_len = packet_len; - memcpy(forw_packet->packet_buff, packet_buff, forw_packet->packet_len); + skb_reset_mac_header(skb); + + forw_packet->skb = skb; + forw_packet->packet_buff = NULL; /* how often did we send the bcast packet ? */ forw_packet->num_packets = 0; @@ -384,6 +407,7 @@ void send_outstanding_bcast_packet(struct work_struct *work) struct forw_packet *forw_packet = container_of(delayed_work, struct forw_packet, delayed_work); unsigned long flags; + struct sk_buff *skb1; spin_lock_irqsave(&forw_bcast_list_lock, flags); hlist_del(&forw_packet->list); @@ -392,8 +416,10 @@ void send_outstanding_bcast_packet(struct work_struct *work) /* rebroadcast packet */ rcu_read_lock(); list_for_each_entry_rcu(batman_if, &if_list, list) { - send_raw_packet(forw_packet->packet_buff, - forw_packet->packet_len, + /* send a copy of the saved skb */ + skb1 = skb_copy(forw_packet->skb, GFP_ATOMIC); + if (skb1) + send_skb_packet(skb1, batman_if, broadcastAddr); } rcu_read_unlock(); @@ -415,10 +441,11 @@ void send_outstanding_bat_packet(struct work_struct *work) container_of(work, struct delayed_work, work); struct forw_packet *forw_packet = container_of(delayed_work, struct forw_packet, delayed_work); + unsigned long flags; - spin_lock(&forw_bat_list_lock); + spin_lock_irqsave(&forw_bat_list_lock, flags); hlist_del(&forw_packet->list); - spin_unlock(&forw_bat_list_lock); + spin_unlock_irqrestore(&forw_bat_list_lock, flags); send_packet(forw_packet); @@ -459,18 +486,18 @@ void purge_outstanding_packets(void) spin_unlock_irqrestore(&forw_bcast_list_lock, flags); /* free batman packet list */ - spin_lock(&forw_bat_list_lock); + spin_lock_irqsave(&forw_bat_list_lock, flags); hlist_for_each_entry_safe(forw_packet, tmp_node, safe_tmp_node, &forw_bat_list, list) { - spin_unlock(&forw_bat_list_lock); + spin_unlock_irqrestore(&forw_bat_list_lock, flags); /** * send_outstanding_bat_packet() will lock the list to * delete the item from the list */ cancel_delayed_work_sync(&forw_packet->delayed_work); - spin_lock(&forw_bat_list_lock); + spin_lock_irqsave(&forw_bat_list_lock, flags); } - spin_unlock(&forw_bat_list_lock); + spin_unlock_irqrestore(&forw_bat_list_lock, flags); } diff --git a/drivers/staging/batman-adv/send.h b/drivers/staging/batman-adv/send.h index 59d500917a35..5fc6f3417cb6 100644 --- a/drivers/staging/batman-adv/send.h +++ b/drivers/staging/batman-adv/send.h @@ -22,6 +22,9 @@ #include "types.h" void send_own_packet_work(struct work_struct *work); +int send_skb_packet(struct sk_buff *skb, + struct batman_if *batman_if, + uint8_t *dst_addr); void send_raw_packet(unsigned char *pack_buff, int pack_buff_len, struct batman_if *batman_if, uint8_t *dst_addr); void schedule_own_packet(struct batman_if *batman_if); @@ -30,7 +33,7 @@ void schedule_forward_packet(struct orig_node *orig_node, struct batman_packet *batman_packet, uint8_t directlink, int hna_buff_len, struct batman_if *if_outgoing); -void add_bcast_packet_to_list(unsigned char *packet_buff, int packet_len); +void add_bcast_packet_to_list(struct sk_buff *skb); void send_outstanding_bcast_packet(struct work_struct *work); void send_outstanding_bat_packet(struct work_struct *work); void purge_outstanding_packets(void); diff --git a/drivers/staging/batman-adv/soft-interface.c b/drivers/staging/batman-adv/soft-interface.c index 168a4e195a1c..8ae3483a6259 100644 --- a/drivers/staging/batman-adv/soft-interface.c +++ b/drivers/staging/batman-adv/soft-interface.c @@ -34,7 +34,6 @@ static uint16_t bcast_seqno = 1; /* give own bcast messages seq numbers to avoid * broadcast storms */ static int32_t skb_packets; static int32_t skb_bad_packets; -static int32_t lock_dropped; unsigned char mainIfAddr[ETH_ALEN]; static unsigned char mainIfAddr_default[ETH_ALEN]; @@ -67,12 +66,12 @@ int main_if_was_up(void) return (memcmp(mainIfAddr, mainIfAddr_default, ETH_ALEN) != 0 ? 1 : 0); } -static int my_skb_push(struct sk_buff *skb, unsigned int len) +int my_skb_push(struct sk_buff *skb, unsigned int len) { int result = 0; skb_packets++; - if (skb->data - len < skb->head) { + if (skb_headroom(skb) < len) { skb_bad_packets++; result = pskb_expand_head(skb, len, 0, GFP_ATOMIC); @@ -169,7 +168,10 @@ int interface_tx(struct sk_buff *skb, struct net_device *dev) struct orig_node *orig_node; struct ethhdr *ethhdr = (struct ethhdr *)skb->data; struct bat_priv *priv = netdev_priv(dev); + struct batman_if *batman_if; + uint8_t dstaddr[6]; int data_len = skb->len; + unsigned long flags; if (atomic_read(&module_state) != MODULE_ACTIVE) goto dropped; @@ -185,7 +187,6 @@ int interface_tx(struct sk_buff *skb, struct net_device *dev) goto dropped; bcast_packet = (struct bcast_packet *)skb->data; - bcast_packet->version = COMPAT_VERSION; /* batman packet type: broadcast */ @@ -194,27 +195,21 @@ int interface_tx(struct sk_buff *skb, struct net_device *dev) /* hw address of first interface is the orig mac because only * this mac is known throughout the mesh */ memcpy(bcast_packet->orig, mainIfAddr, ETH_ALEN); + /* set broadcast sequence number */ bcast_packet->seqno = htons(bcast_seqno); bcast_seqno++; /* broadcast packet */ - add_bcast_packet_to_list(skb->data, skb->len); + add_bcast_packet_to_list(skb); + /* a copy is stored in the bcast list, therefore removing + * the original skb. */ + kfree_skb(skb); /* unicast packet */ } else { - - /* simply spin_lock()ing can deadlock when the lock is already - * hold. */ - /* TODO: defer the work in a working queue instead of - * dropping */ - if (!spin_trylock(&orig_hash_lock)) { - lock_dropped++; - printk(KERN_WARNING "batman-adv:%d packets dropped because lock was hold\n", lock_dropped); - goto dropped; - } - + spin_lock_irqsave(&orig_hash_lock, flags); /* get routing information */ orig_node = ((struct orig_node *)hash_find(orig_hash, ethhdr->h_dest)); @@ -243,14 +238,17 @@ int interface_tx(struct sk_buff *skb, struct net_device *dev) if (orig_node->batman_if->if_active != IF_ACTIVE) goto unlock; - send_raw_packet(skb->data, skb->len, - orig_node->batman_if, - orig_node->router->addr); + /* don't lock while sending the packets ... we therefore + * copy the required data before sending */ + + batman_if = orig_node->batman_if; + memcpy(dstaddr, orig_node->router->addr, ETH_ALEN); + spin_unlock_irqrestore(&orig_hash_lock, flags); + + send_skb_packet(skb, batman_if, dstaddr); } else { goto unlock; } - - spin_unlock(&orig_hash_lock); } priv->stats.tx_packets++; @@ -258,42 +256,44 @@ int interface_tx(struct sk_buff *skb, struct net_device *dev) goto end; unlock: - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); dropped: priv->stats.tx_dropped++; end: - kfree_skb(skb); return 0; } -void interface_rx(struct net_device *dev, void *packet, int packet_len) +void interface_rx(struct sk_buff *skb, int hdr_size) { - struct sk_buff *skb; + struct net_device *dev = soft_device; struct bat_priv *priv = netdev_priv(dev); - skb = dev_alloc_skb(packet_len); - - if (!skb) { - priv->stats.rx_dropped++; - goto out; + /* check if enough space is available for pulling, and pull */ + if (!pskb_may_pull(skb, hdr_size)) { + kfree_skb(skb); + return; } + skb_pull_rcsum(skb, hdr_size); +/* skb_set_mac_header(skb, -sizeof(struct ethhdr));*/ - memcpy(skb_put(skb, packet_len), packet, packet_len); - - /* Write metadata, and then pass to the receive level */ skb->dev = dev; skb->protocol = eth_type_trans(skb, dev); - skb->ip_summed = CHECKSUM_UNNECESSARY; + + /* should not be neccesary anymore as we use skb_pull_rcsum() + * TODO: please verify this and remove this TODO + * -- Dec 21st 2009, Simon Wunderlich */ + +/* skb->ip_summed = CHECKSUM_UNNECESSARY;*/ + + /* TODO: set skb->pkt_type to PACKET_BROADCAST, PACKET_MULTICAST, + * PACKET_OTHERHOST or PACKET_HOST */ priv->stats.rx_packets++; - priv->stats.rx_bytes += packet_len; + priv->stats.rx_bytes += skb->len; dev->last_rx = jiffies; netif_rx(skb); - -out: - return; } /* ethtool */ diff --git a/drivers/staging/batman-adv/soft-interface.h b/drivers/staging/batman-adv/soft-interface.h index 515e276ef53d..c0cad8134b2b 100644 --- a/drivers/staging/batman-adv/soft-interface.h +++ b/drivers/staging/batman-adv/soft-interface.h @@ -28,6 +28,7 @@ struct net_device_stats *interface_stats(struct net_device *dev); int interface_set_mac_addr(struct net_device *dev, void *addr); int interface_change_mtu(struct net_device *dev, int new_mtu); int interface_tx(struct sk_buff *skb, struct net_device *dev); -void interface_rx(struct net_device *dev, void *packet, int packet_len); +void interface_rx(struct sk_buff *skb, int hdr_size); +int my_skb_push(struct sk_buff *skb, unsigned int len); extern unsigned char mainIfAddr[]; diff --git a/drivers/staging/batman-adv/types.h b/drivers/staging/batman-adv/types.h index d708e6f15b37..dec1b54031b6 100644 --- a/drivers/staging/batman-adv/types.h +++ b/drivers/staging/batman-adv/types.h @@ -39,7 +39,6 @@ struct batman_if { char if_active; char addr_str[ETH_STR_LEN]; struct net_device *net_dev; - struct socket *raw_sock; atomic_t seqno; unsigned char *packet_buff; int packet_len; @@ -113,6 +112,7 @@ struct forw_packet { /* structure for forw_list maintaining packet struct hlist_node list; unsigned long send_time; uint8_t own; + struct sk_buff *skb; unsigned char *packet_buff; uint16_t packet_len; uint32_t direct_link_flags; diff --git a/drivers/staging/batman-adv/vis.c b/drivers/staging/batman-adv/vis.c index 62ee77396418..191297926b3f 100644 --- a/drivers/staging/batman-adv/vis.c +++ b/drivers/staging/batman-adv/vis.c @@ -52,12 +52,13 @@ static void free_info(void *data) /* set the mode of the visualization to client or server */ void vis_set_mode(int mode) { - spin_lock(&vis_hash_lock); + unsigned long flags; + spin_lock_irqsave(&vis_hash_lock, flags); if (my_vis_info != NULL) my_vis_info->packet.vis_type = mode; - spin_unlock(&vis_hash_lock); + spin_unlock_irqrestore(&vis_hash_lock, flags); } /* is_vis_server(), locked outside */ @@ -74,10 +75,11 @@ static int is_vis_server_locked(void) int is_vis_server(void) { int ret = 0; + unsigned long flags; - spin_lock(&vis_hash_lock); + spin_lock_irqsave(&vis_hash_lock, flags); ret = is_vis_server_locked(); - spin_unlock(&vis_hash_lock); + spin_unlock_irqrestore(&vis_hash_lock, flags); return ret; } @@ -269,8 +271,9 @@ void receive_server_sync_packet(struct vis_packet *vis_packet, int vis_info_len) { struct vis_info *info; int is_new; + unsigned long flags; - spin_lock(&vis_hash_lock); + spin_lock_irqsave(&vis_hash_lock, flags); info = add_packet(vis_packet, vis_info_len, &is_new); if (info == NULL) goto end; @@ -283,7 +286,7 @@ void receive_server_sync_packet(struct vis_packet *vis_packet, int vis_info_len) list_add_tail(&info->send_list, &send_list); } end: - spin_unlock(&vis_hash_lock); + spin_unlock_irqrestore(&vis_hash_lock, flags); } /* handle an incoming client update packet and schedule forward if needed. */ @@ -292,12 +295,13 @@ void receive_client_update_packet(struct vis_packet *vis_packet, { struct vis_info *info; int is_new; + unsigned long flags; /* clients shall not broadcast. */ if (is_bcast(vis_packet->target_orig)) return; - spin_lock(&vis_hash_lock); + spin_lock_irqsave(&vis_hash_lock, flags); info = add_packet(vis_packet, vis_info_len, &is_new); if (info == NULL) goto end; @@ -319,7 +323,7 @@ void receive_client_update_packet(struct vis_packet *vis_packet, list_add_tail(&info->send_list, &send_list); } end: - spin_unlock(&vis_hash_lock); + spin_unlock_irqrestore(&vis_hash_lock, flags); } /* Walk the originators and find the VIS server with the best tq. Set the packet @@ -370,7 +374,7 @@ static int generate_vis_packet(void) info->first_seen = jiffies; - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); memcpy(info->packet.target_orig, broadcastAddr, ETH_ALEN); info->packet.ttl = TTL; info->packet.seqno++; @@ -379,7 +383,7 @@ static int generate_vis_packet(void) if (!is_vis_server_locked()) { best_tq = find_best_vis_server(info); if (best_tq < 0) { - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); return -1; } } @@ -403,13 +407,13 @@ static int generate_vis_packet(void) info->packet.entries++; if (vis_packet_full(info)) { - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); return 0; } } } - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); spin_lock_irqsave(&hna_local_hash_lock, flags); while (hash_iterate(hna_local_hash, &hashit_local)) { @@ -450,8 +454,9 @@ static void broadcast_vis_packet(struct vis_info *info, int packet_length) { HASHIT(hashit); struct orig_node *orig_node; + unsigned long flags; - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); /* send to all routers in range. */ while (hash_iterate(orig_hash, &hashit)) { @@ -478,14 +483,15 @@ static void broadcast_vis_packet(struct vis_info *info, int packet_length) } } memcpy(info->packet.target_orig, broadcastAddr, ETH_ALEN); - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); } static void unicast_vis_packet(struct vis_info *info, int packet_length) { struct orig_node *orig_node; + unsigned long flags; - spin_lock(&orig_hash_lock); + spin_lock_irqsave(&orig_hash_lock, flags); orig_node = ((struct orig_node *) hash_find(orig_hash, info->packet.target_orig)); @@ -496,7 +502,7 @@ static void unicast_vis_packet(struct vis_info *info, int packet_length) orig_node->batman_if, orig_node->router->addr); } - spin_unlock(&orig_hash_lock); + spin_unlock_irqrestore(&orig_hash_lock, flags); } /* only send one vis packet. called from send_vis_packets() */ @@ -526,8 +532,9 @@ static void send_vis_packet(struct vis_info *info) static void send_vis_packets(struct work_struct *work) { struct vis_info *info, *temp; + unsigned long flags; - spin_lock(&vis_hash_lock); + spin_lock_irqsave(&vis_hash_lock, flags); purge_vis_packets(); if (generate_vis_packet() == 0) @@ -538,7 +545,7 @@ static void send_vis_packets(struct work_struct *work) list_del_init(&info->send_list); send_vis_packet(info); } - spin_unlock(&vis_hash_lock); + spin_unlock_irqrestore(&vis_hash_lock, flags); start_vis_timer(); } static DECLARE_DELAYED_WORK(vis_timer_wq, send_vis_packets); @@ -547,10 +554,11 @@ static DECLARE_DELAYED_WORK(vis_timer_wq, send_vis_packets); * initialized (e.g. bat0 is initialized, interfaces have been added) */ int vis_init(void) { + unsigned long flags; if (vis_hash) return 1; - spin_lock(&vis_hash_lock); + spin_lock_irqsave(&vis_hash_lock, flags); vis_hash = hash_new(256, vis_info_cmp, vis_info_choose); if (!vis_hash) { @@ -588,12 +596,12 @@ int vis_init(void) goto err; } - spin_unlock(&vis_hash_lock); + spin_unlock_irqrestore(&vis_hash_lock, flags); start_vis_timer(); return 1; err: - spin_unlock(&vis_hash_lock); + spin_unlock_irqrestore(&vis_hash_lock, flags); vis_quit(); return 0; } @@ -601,17 +609,18 @@ err: /* shutdown vis-server */ void vis_quit(void) { + unsigned long flags; if (!vis_hash) return; cancel_delayed_work_sync(&vis_timer_wq); - spin_lock(&vis_hash_lock); + spin_lock_irqsave(&vis_hash_lock, flags); /* properly remove, kill timers ... */ hash_delete(vis_hash, free_info); vis_hash = NULL; my_vis_info = NULL; - spin_unlock(&vis_hash_lock); + spin_unlock_irqrestore(&vis_hash_lock, flags); } /* schedule packets for (re)transmission */ -- cgit v1.2.3 From a9c2910aa15c5b2559e80d1406176f8456d3e34e Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 2 Jan 2010 11:30:49 +0100 Subject: Staging: batman-adv: Allow the MAC address to be set Some embedded devices have very limited sources of entropy for the random number generator. It has been observed that the random MAC address on the interface bat0 is not always random. When testing with a collection of identical hardware, sometimes the bat0 device the same MAC address on multiple devices, causing mayhem. This patch allows the MAC address to be set by the user. Signed-off-by: Andrew Lunn Signed-off-by: Simon Wunderlich Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/soft-interface.c | 13 +++++++++++-- drivers/staging/batman-adv/translation-table.c | 15 +++++++++++++++ drivers/staging/batman-adv/translation-table.h | 1 + 3 files changed, 27 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/soft-interface.c b/drivers/staging/batman-adv/soft-interface.c index 8ae3483a6259..bc0217b1aeb1 100644 --- a/drivers/staging/batman-adv/soft-interface.c +++ b/drivers/staging/batman-adv/soft-interface.c @@ -145,9 +145,18 @@ struct net_device_stats *interface_stats(struct net_device *dev) return &priv->stats; } -int interface_set_mac_addr(struct net_device *dev, void *addr) +int interface_set_mac_addr(struct net_device *dev, void *p) { - return -EBUSY; + struct sockaddr *addr = p; + + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + + hna_local_remove(dev->dev_addr, "mac address changed"); + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); + hna_local_add(dev->dev_addr); + + return 0; } int interface_change_mtu(struct net_device *dev, int new_mtu) diff --git a/drivers/staging/batman-adv/translation-table.c b/drivers/staging/batman-adv/translation-table.c index 8c8136b71628..53a054e413d7 100644 --- a/drivers/staging/batman-adv/translation-table.c +++ b/drivers/staging/batman-adv/translation-table.c @@ -211,6 +211,21 @@ static void hna_local_del(struct hna_local_entry *hna_local_entry, _hna_local_del(hna_local_entry); } +void hna_local_remove(uint8_t *addr, char *message) +{ + struct hna_local_entry *hna_local_entry; + unsigned long flags; + + spin_lock_irqsave(&hna_local_hash_lock, flags); + + hna_local_entry = (struct hna_local_entry *) + hash_find(hna_local_hash, addr); + if (hna_local_entry) + hna_local_del(hna_local_entry, message); + + spin_unlock_irqrestore(&hna_local_hash_lock, flags); +} + void hna_local_purge(struct work_struct *work) { struct hna_local_entry *hna_local_entry; diff --git a/drivers/staging/batman-adv/translation-table.h b/drivers/staging/batman-adv/translation-table.h index f7da81129318..281125b729fb 100644 --- a/drivers/staging/batman-adv/translation-table.h +++ b/drivers/staging/batman-adv/translation-table.h @@ -23,6 +23,7 @@ int hna_local_init(void); void hna_local_add(uint8_t *addr); +void hna_local_remove(uint8_t *addr, char *message); int hna_local_fill_buffer(unsigned char *buff, int buff_len); int hna_local_fill_buffer_text(unsigned char *buff, int buff_len); void hna_local_purge(struct work_struct *work); -- cgit v1.2.3 From b9b27e4ef6313449a6b40a21e0e9a1bdd9a1d8ce Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 2 Jan 2010 11:30:50 +0100 Subject: Staging: batman-adv: Use printk(%pM) for MAC addresses printk() since kernel version 2.6.29 has supported printing MAC addresses directly, as an extension to the %p processing. This patch makes use of this for printk() and bat_dbg(). This will remove the overhead of using addr_to_string() which is normally never actually output. Fixed a typo found by Gus Wirth. Signed-off-by: Andrew Lunn Signed-off-by: Simon Wunderlich Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/TODO | 4 -- drivers/staging/batman-adv/compat.h | 82 ++++++++++++++++++++------ drivers/staging/batman-adv/device.c | 1 + drivers/staging/batman-adv/hard-interface.c | 14 ++--- drivers/staging/batman-adv/main.c | 2 +- drivers/staging/batman-adv/originator.c | 17 ++---- drivers/staging/batman-adv/routing.c | 65 ++++++-------------- drivers/staging/batman-adv/send.c | 13 ++-- drivers/staging/batman-adv/translation-table.c | 34 ++++------- 9 files changed, 111 insertions(+), 121 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/TODO b/drivers/staging/batman-adv/TODO index b1e369cf9870..2122adc6aa84 100644 --- a/drivers/staging/batman-adv/TODO +++ b/drivers/staging/batman-adv/TODO @@ -17,10 +17,6 @@ -> transtable_global (read-only) [outputs the global translation table] -> transtable_local (read-only) [outputs the local translation table] -=> logging -* make use of printk %pM support instead of converting mac addresses -* manually - => strip out all backward compatibility support to older kernels (only found in compat.h) diff --git a/drivers/staging/batman-adv/compat.h b/drivers/staging/batman-adv/compat.h index f4e0a4564ba7..ded1e6e15240 100644 --- a/drivers/staging/batman-adv/compat.h +++ b/drivers/staging/batman-adv/compat.h @@ -35,41 +35,87 @@ #define list_first_entry(ptr, type, member) \ list_entry((ptr)->next, type, member) -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22) */ +#define skb_mac_header(_skb) \ + ((_skb)->mac.raw) +#define skb_network_header(_skb) \ + ((_skb)->nh.raw) + +#define skb_mac_header(_skb) \ + ((_skb)->mac.raw) + +#endif /* < KERNEL_VERSION(2,6,22) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 23) + +static inline int skb_clone_writable(struct sk_buff *skb, unsigned int len) +{ + /* skb->hdr_len not available, just "not writable" to enforce a copy */ + return 0; +} + +#define cancel_delayed_work_sync(wq) cancel_rearming_delayed_work(wq) + +#endif /* < KERNEL_VERSION(2, 6, 23) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25) + +#define strict_strtoul(cp, base, res) \ + ({ \ + int ret = 0; \ + char *endp; \ + *res = simple_strtoul(cp, &endp, base); \ + if (cp == endp) \ + ret = -EINVAL; \ + ret; \ +}) + +#endif /* < KERNEL_VERSION(2, 6, 25) */ #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26) +static const char hex_asc[] = "0123456789abcdef"; +#define hex_asc_lo(x) hex_asc[((x) & 0x0f)] +#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4] +static inline char *pack_hex_byte(char *buf, u8 byte) +{ + *buf++ = hex_asc_hi(byte); + *buf++ = hex_asc_lo(byte); + return buf; +} + #define device_create(_cls, _parent, _devt, _device, _fmt) \ class_device_create(_cls, _parent, _devt, _device, _fmt) #define device_destroy(_cls, _device) \ class_device_destroy(_cls, _device) -#else +#endif /* < KERNEL_VERSION(2, 6, 26) */ #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27) +#ifndef dereference_function_descriptor +#define dereference_function_descriptor(p) (p) +#endif + +#ifndef device_create #define device_create(_cls, _parent, _devt, _device, _fmt) \ device_create_drvdata(_cls, _parent, _devt, _device, _fmt) +#endif -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27) */ +#endif /* < KERNEL_VERSION(2, 6, 27) */ -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26) */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29) -#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 23) +asmlinkage int bat_printk(const char *fmt, ...); +#define printk bat_printk -#define cancel_delayed_work_sync(wq) cancel_rearming_delayed_work(wq) +static inline struct net_device_stats *dev_get_stats(struct net_device *dev) +{ + if (dev->get_stats) + return dev->get_stats(dev); + else + return NULL; +} -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 23) */ -#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25) -#define strict_strtoul(cp, base, res) \ - ({ \ - int ret = 0; \ - char *endp; \ - *res = simple_strtoul(cp, &endp, base); \ - if (cp == endp) \ - ret = -EINVAL; \ - ret; \ -}) -#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25) */ +#endif /* < KERNEL_VERSION(2, 6, 29) */ diff --git a/drivers/staging/batman-adv/device.c b/drivers/staging/batman-adv/device.c index ab2b0b17d9ea..72306acec5e6 100644 --- a/drivers/staging/batman-adv/device.c +++ b/drivers/staging/batman-adv/device.c @@ -19,6 +19,7 @@ * */ +#include #include "main.h" #include "device.h" #include "send.h" diff --git a/drivers/staging/batman-adv/hard-interface.c b/drivers/staging/batman-adv/hard-interface.c index cc59c307a420..db264bd0bf9d 100644 --- a/drivers/staging/batman-adv/hard-interface.c +++ b/drivers/staging/batman-adv/hard-interface.c @@ -74,7 +74,6 @@ int hardif_min_mtu(void) static void check_known_mac_addr(uint8_t *addr) { struct batman_if *batman_if; - char mac_string[ETH_STR_LEN]; rcu_read_lock(); list_for_each_entry_rcu(batman_if, &if_list, list) { @@ -85,9 +84,8 @@ static void check_known_mac_addr(uint8_t *addr) if (!compare_orig(batman_if->net_dev->dev_addr, addr)) continue; - addr_to_string(mac_string, addr); - printk(KERN_WARNING "batman-adv:The newly added mac address (%s) already exists on: %s\n", - mac_string, batman_if->dev); + printk(KERN_WARNING "batman-adv:The newly added mac address (%pM) already exists on: %s\n", + addr, batman_if->dev); printk(KERN_WARNING "batman-adv:It is strongly recommended to keep mac addresses unique to avoid problems!\n"); } rcu_read_unlock(); @@ -447,9 +445,11 @@ int batman_skb_recv(struct sk_buff *skb, struct net_device *dev, if (!batman_if) goto err_free; - stats = &skb->dev->stats; - stats->rx_packets++; - stats->rx_bytes += skb->len; + stats = (struct net_device_stats *) dev_get_stats(skb->dev); + if (stats) { + stats->rx_packets++; + stats->rx_bytes += skb->len; + } batman_packet = (struct batman_packet *)skb->data; diff --git a/drivers/staging/batman-adv/main.c b/drivers/staging/batman-adv/main.c index c73350415697..1d80ea366be3 100644 --- a/drivers/staging/batman-adv/main.c +++ b/drivers/staging/batman-adv/main.c @@ -54,7 +54,7 @@ unsigned char broadcastAddr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; atomic_t module_state; static struct packet_type batman_adv_packet_type __read_mostly = { - .type = cpu_to_be16(ETH_P_BATMAN), + .type = __constant_htons(ETH_P_BATMAN), .func = batman_skb_recv, }; diff --git a/drivers/staging/batman-adv/originator.c b/drivers/staging/batman-adv/originator.c index 1c0a3cec8466..a60dbe1cf6bf 100644 --- a/drivers/staging/batman-adv/originator.c +++ b/drivers/staging/batman-adv/originator.c @@ -26,6 +26,7 @@ #include "hash.h" #include "translation-table.h" #include "routing.h" +#include "compat.h" static DECLARE_DELAYED_WORK(purge_orig_wq, purge_orig); @@ -121,7 +122,6 @@ struct orig_node *get_orig_node(uint8_t *addr) { struct orig_node *orig_node; struct hashtable_t *swaphash; - char orig_str[ETH_STR_LEN]; int size; orig_node = ((struct orig_node *)hash_find(orig_hash, addr)); @@ -129,8 +129,7 @@ struct orig_node *get_orig_node(uint8_t *addr) if (orig_node != NULL) return orig_node; - addr_to_string(orig_str, addr); - bat_dbg(DBG_BATMAN, "Creating new originator: %s \n", orig_str); + bat_dbg(DBG_BATMAN, "Creating new originator: %pM \n", addr); orig_node = kmalloc(sizeof(struct orig_node), GFP_ATOMIC); if (!orig_node) @@ -186,7 +185,6 @@ static bool purge_orig_neighbors(struct orig_node *orig_node, struct neigh_node **best_neigh_node) { struct list_head *list_pos, *list_pos_tmp; - char neigh_str[ETH_STR_LEN], orig_str[ETH_STR_LEN]; struct neigh_node *neigh_node; bool neigh_purged = false; @@ -201,9 +199,7 @@ static bool purge_orig_neighbors(struct orig_node *orig_node, (neigh_node->last_valid + ((PURGE_TIMEOUT * HZ) / 1000)))) { - addr_to_string(neigh_str, neigh_node->addr); - addr_to_string(orig_str, orig_node->orig); - bat_dbg(DBG_BATMAN, "neighbor timeout: originator %s, neighbor: %s, last_valid %lu\n", orig_str, neigh_str, (neigh_node->last_valid / HZ)); + bat_dbg(DBG_BATMAN, "neighbor timeout: originator %pM, neighbor: %pM, last_valid %lu\n", orig_node->orig, neigh_node->addr, (neigh_node->last_valid / HZ)); neigh_purged = true; list_del(list_pos); @@ -221,17 +217,14 @@ static bool purge_orig_neighbors(struct orig_node *orig_node, static bool purge_orig_node(struct orig_node *orig_node) { struct neigh_node *best_neigh_node; - char orig_str[ETH_STR_LEN]; - - addr_to_string(orig_str, orig_node->orig); if (time_after(jiffies, (orig_node->last_valid + ((2 * PURGE_TIMEOUT * HZ) / 1000)))) { bat_dbg(DBG_BATMAN, - "Originator timeout: originator %s, last_valid %lu\n", - orig_str, (orig_node->last_valid / HZ)); + "Originator timeout: originator %pM, last_valid %lu\n", + orig_node->orig, (orig_node->last_valid / HZ)); return true; } else { if (purge_orig_neighbors(orig_node, &best_neigh_node)) diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index e0d093f5d524..bab7a73e17a5 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -80,32 +80,24 @@ static void update_route(struct orig_node *orig_node, struct neigh_node *neigh_node, unsigned char *hna_buff, int hna_buff_len) { - char orig_str[ETH_STR_LEN], neigh_str[ETH_STR_LEN]; - char router_str[ETH_STR_LEN]; - - addr_to_string(orig_str, orig_node->orig); - /* route deleted */ if ((orig_node->router != NULL) && (neigh_node == NULL)) { - bat_dbg(DBG_ROUTES, "Deleting route towards: %s\n", - orig_str); + bat_dbg(DBG_ROUTES, "Deleting route towards: %pM\n", + orig_node->orig); hna_global_del_orig(orig_node, "originator timed out"); /* route added */ } else if ((orig_node->router == NULL) && (neigh_node != NULL)) { - addr_to_string(neigh_str, neigh_node->addr); bat_dbg(DBG_ROUTES, - "Adding route towards: %s (via %s)\n", - orig_str, neigh_str); + "Adding route towards: %pM (via %pM)\n", + orig_node->orig, neigh_node->addr); hna_global_add_orig(orig_node, hna_buff, hna_buff_len); /* route changed */ } else { - addr_to_string(neigh_str, neigh_node->addr); - addr_to_string(router_str, orig_node->router->addr); - bat_dbg(DBG_ROUTES, "Changing route towards: %s (now via %s - was via %s)\n", orig_str, neigh_str, router_str); + bat_dbg(DBG_ROUTES, "Changing route towards: %pM (now via %pM - was via %pM)\n", orig_node->orig, neigh_node->addr, orig_node->router->addr); } if (neigh_node != NULL) @@ -138,12 +130,8 @@ static int isBidirectionalNeigh(struct orig_node *orig_node, struct batman_if *if_incoming) { struct neigh_node *neigh_node = NULL, *tmp_neigh_node = NULL; - char orig_str[ETH_STR_LEN], neigh_str[ETH_STR_LEN]; unsigned char total_count; - addr_to_string(orig_str, orig_node->orig); - addr_to_string(neigh_str, orig_neigh_node->orig); - if (orig_node == orig_neigh_node) { list_for_each_entry(tmp_neigh_node, &orig_node->neigh_list, @@ -227,8 +215,8 @@ static int isBidirectionalNeigh(struct orig_node *orig_node, orig_neigh_node->tq_asym_penalty) / (TQ_MAX_VALUE * TQ_MAX_VALUE)); - bat_dbg(DBG_BATMAN, "bidirectional: orig = %-15s neigh = %-15s => own_bcast = %2i, real recv = %2i, local tq: %3i, asym_penalty: %3i, total tq: %3i \n", - orig_str, neigh_str, total_count, + bat_dbg(DBG_BATMAN, "bidirectional: orig = %-15pM neigh = %-15pM => own_bcast = %2i, real recv = %2i, local tq: %3i, asym_penalty: %3i, total tq: %3i \n", + orig_node->orig, orig_neigh_node->orig, total_count, neigh_node->real_packet_count, orig_neigh_node->tq_own, orig_neigh_node->tq_asym_penalty, batman_packet->tq); @@ -372,8 +360,6 @@ void receive_bat_packet(struct ethhdr *ethhdr, { struct batman_if *batman_if; struct orig_node *orig_neigh_node, *orig_node; - char orig_str[ETH_STR_LEN], prev_sender_str[ETH_STR_LEN]; - char neigh_str[ETH_STR_LEN]; char has_directlink_flag; char is_my_addr = 0, is_my_orig = 0, is_my_oldorig = 0; char is_broadcast = 0, is_bidirectional, is_single_hop_neigh; @@ -398,20 +384,16 @@ void receive_bat_packet(struct ethhdr *ethhdr, /* could be changed by schedule_own_packet() */ if_incoming_seqno = atomic_read(&if_incoming->seqno); - addr_to_string(orig_str, batman_packet->orig); - addr_to_string(prev_sender_str, batman_packet->prev_sender); - addr_to_string(neigh_str, ethhdr->h_source); - has_directlink_flag = (batman_packet->flags & DIRECTLINK ? 1 : 0); is_single_hop_neigh = (compare_orig(ethhdr->h_source, batman_packet->orig) ? 1 : 0); - bat_dbg(DBG_BATMAN, "Received BATMAN packet via NB: %s, IF: %s [%s] (from OG: %s, via prev OG: %s, seqno %d, tq %d, TTL %d, V %d, IDF %d) \n", - neigh_str, if_incoming->dev, if_incoming->addr_str, - orig_str, prev_sender_str, batman_packet->seqno, - batman_packet->tq, batman_packet->ttl, batman_packet->version, - has_directlink_flag); + bat_dbg(DBG_BATMAN, "Received BATMAN packet via NB: %pM, IF: %s [%s] (from OG: %pM, via prev OG: %pM, seqno %d, tq %d, TTL %d, V %d, IDF %d) \n", + ethhdr->h_source, if_incoming->dev, if_incoming->addr_str, + batman_packet->orig, batman_packet->prev_sender, + batman_packet->seqno, batman_packet->tq, batman_packet->ttl, + batman_packet->version, has_directlink_flag); list_for_each_entry_rcu(batman_if, &if_list, list) { if (batman_if->if_active != IF_ACTIVE) @@ -442,13 +424,13 @@ void receive_bat_packet(struct ethhdr *ethhdr, if (is_my_addr) { bat_dbg(DBG_BATMAN, - "Drop packet: received my own broadcast (sender: %s)\n", - neigh_str); + "Drop packet: received my own broadcast (sender: %pM)\n", + ethhdr->h_source); return; } if (is_broadcast) { - bat_dbg(DBG_BATMAN, "Drop packet: ignoring all packets with broadcast source addr (sender: %s) \n", neigh_str); + bat_dbg(DBG_BATMAN, "Drop packet: ignoring all packets with broadcast source addr (sender: %pM) \n", ethhdr->h_source); return; } @@ -488,7 +470,7 @@ void receive_bat_packet(struct ethhdr *ethhdr, } if (is_my_oldorig) { - bat_dbg(DBG_BATMAN, "Drop packet: ignoring all rebroadcast echos (sender: %s) \n", neigh_str); + bat_dbg(DBG_BATMAN, "Drop packet: ignoring all rebroadcast echos (sender: %pM) \n", ethhdr->h_source); return; } @@ -506,7 +488,7 @@ void receive_bat_packet(struct ethhdr *ethhdr, !(compare_orig(batman_packet->orig, batman_packet->prev_sender)) && (compare_orig(orig_node->router->addr, orig_node->router->orig_node->router->addr))) { - bat_dbg(DBG_BATMAN, "Drop packet: ignoring all rebroadcast packets that may make me loop (sender: %s) \n", neigh_str); + bat_dbg(DBG_BATMAN, "Drop packet: ignoring all rebroadcast packets that may make me loop (sender: %pM) \n", ethhdr->h_source); return; } @@ -666,7 +648,6 @@ static int recv_my_icmp_packet(struct sk_buff *skb) static int recv_icmp_ttl_exceeded(struct sk_buff *skb) { - unsigned char src_str[ETH_STR_LEN], dst_str[ETH_STR_LEN]; struct orig_node *orig_node; struct icmp_packet *icmp_packet; struct ethhdr *ethhdr; @@ -679,10 +660,7 @@ static int recv_icmp_ttl_exceeded(struct sk_buff *skb) icmp_packet = (struct icmp_packet *) skb->data; ethhdr = (struct ethhdr *) skb_mac_header(skb); - addr_to_string(src_str, icmp_packet->orig); - addr_to_string(dst_str, icmp_packet->dst); - - printk(KERN_WARNING "batman-adv:Warning - can't send packet from %s to %s: ttl exceeded\n", src_str, dst_str); + printk(KERN_WARNING "batman-adv:Warning - can't send packet from %pM to %pM: ttl exceeded\n", icmp_packet->orig, icmp_packet->dst); /* send TTL exceeded if packet is an echo request (traceroute) */ if (icmp_packet->msg_type != ECHO_REQUEST) @@ -812,7 +790,6 @@ int recv_icmp_packet(struct sk_buff *skb) int recv_unicast_packet(struct sk_buff *skb) { struct unicast_packet *unicast_packet; - unsigned char src_str[ETH_STR_LEN], dst_str[ETH_STR_LEN]; struct orig_node *orig_node; struct ethhdr *ethhdr; struct batman_if *batman_if; @@ -850,10 +827,7 @@ int recv_unicast_packet(struct sk_buff *skb) /* TTL exceeded */ if (unicast_packet->ttl < 2) { - addr_to_string(src_str, ethhdr->h_source); - addr_to_string(dst_str, ethhdr->h_dest); - - printk(KERN_WARNING "batman-adv:Warning - can't send packet from %s to %s: ttl exceeded\n", src_str, dst_str); + printk(KERN_WARNING "batman-adv:Warning - can't send packet from %pM to %pM: ttl exceeded\n", ethhdr->h_source, unicast_packet->dest); return NET_RX_DROP; } @@ -1005,4 +979,3 @@ int recv_vis_packet(struct sk_buff *skb) } return ret; } - diff --git a/drivers/staging/batman-adv/send.c b/drivers/staging/batman-adv/send.c index fd48f3fa2d88..edfdd5d9279b 100644 --- a/drivers/staging/batman-adv/send.c +++ b/drivers/staging/batman-adv/send.c @@ -132,7 +132,6 @@ static void send_packet_to_if(struct forw_packet *forw_packet, uint8_t packet_num; int16_t buff_pos; struct batman_packet *batman_packet; - char orig_str[ETH_STR_LEN]; if (batman_if->if_active != IF_ACTIVE) return; @@ -154,15 +153,14 @@ static void send_packet_to_if(struct forw_packet *forw_packet, else batman_packet->flags &= ~DIRECTLINK; - addr_to_string(orig_str, batman_packet->orig); fwd_str = (packet_num > 0 ? "Forwarding" : (forw_packet->own ? "Sending own" : "Forwarding")); bat_dbg(DBG_BATMAN, - "%s %spacket (originator %s, seqno %d, TQ %d, TTL %d, IDF %s) on interface %s [%s]\n", + "%s %spacket (originator %pM, seqno %d, TQ %d, TTL %d, IDF %s) on interface %s [%s]\n", fwd_str, (packet_num > 0 ? "aggregated " : ""), - orig_str, ntohs(batman_packet->seqno), + batman_packet->orig, ntohs(batman_packet->seqno), batman_packet->tq, batman_packet->ttl, (batman_packet->flags & DIRECTLINK ? "on" : "off"), @@ -186,7 +184,6 @@ static void send_packet(struct forw_packet *forw_packet) struct batman_if *batman_if; struct batman_packet *batman_packet = (struct batman_packet *)(forw_packet->packet_buff); - char orig_str[ETH_STR_LEN]; unsigned char directlink = (batman_packet->flags & DIRECTLINK ? 1 : 0); if (!forw_packet->if_incoming) { @@ -197,8 +194,6 @@ static void send_packet(struct forw_packet *forw_packet) if (forw_packet->if_incoming->if_active != IF_ACTIVE) return; - addr_to_string(orig_str, batman_packet->orig); - /* multihomed peer assumed */ /* non-primary OGMs are only broadcasted on their interface */ if ((directlink && (batman_packet->ttl == 1)) || @@ -206,9 +201,9 @@ static void send_packet(struct forw_packet *forw_packet) /* FIXME: what about aggregated packets ? */ bat_dbg(DBG_BATMAN, - "%s packet (originator %s, seqno %d, TTL %d) on interface %s [%s]\n", + "%s packet (originator %pM, seqno %d, TTL %d) on interface %s [%s]\n", (forw_packet->own ? "Sending own" : "Forwarding"), - orig_str, ntohs(batman_packet->seqno), + batman_packet->orig, ntohs(batman_packet->seqno), batman_packet->ttl, forw_packet->if_incoming->dev, forw_packet->if_incoming->addr_str); diff --git a/drivers/staging/batman-adv/translation-table.c b/drivers/staging/batman-adv/translation-table.c index 53a054e413d7..398a8084660a 100644 --- a/drivers/staging/batman-adv/translation-table.c +++ b/drivers/staging/batman-adv/translation-table.c @@ -61,7 +61,6 @@ void hna_local_add(uint8_t *addr) struct hna_local_entry *hna_local_entry; struct hna_global_entry *hna_global_entry; struct hashtable_t *swaphash; - char hna_str[ETH_STR_LEN]; unsigned long flags; spin_lock_irqsave(&hna_local_hash_lock, flags); @@ -74,19 +73,17 @@ void hna_local_add(uint8_t *addr) return; } - addr_to_string(hna_str, addr); - /* only announce as many hosts as possible in the batman-packet and space in batman_packet->num_hna That also should give a limit to MAC-flooding. */ if ((num_hna + 1 > (ETH_DATA_LEN - BAT_PACKET_LEN) / ETH_ALEN) || (num_hna + 1 > 255)) { - bat_dbg(DBG_ROUTES, "Can't add new local hna entry (%s): number of local hna entries exceeds packet size \n", hna_str); + bat_dbg(DBG_ROUTES, "Can't add new local hna entry (%pM): number of local hna entries exceeds packet size \n", addr); return; } - bat_dbg(DBG_ROUTES, "Creating new local hna entry: %s \n", - hna_str); + bat_dbg(DBG_ROUTES, "Creating new local hna entry: %pM \n", + addr); hna_local_entry = kmalloc(sizeof(struct hna_local_entry), GFP_ATOMIC); if (!hna_local_entry) @@ -201,11 +198,8 @@ static void _hna_local_del(void *data) static void hna_local_del(struct hna_local_entry *hna_local_entry, char *message) { - char hna_str[ETH_STR_LEN]; - - addr_to_string(hna_str, hna_local_entry->addr); - bat_dbg(DBG_ROUTES, "Deleting local hna entry (%s): %s \n", - hna_str, message); + bat_dbg(DBG_ROUTES, "Deleting local hna entry (%pM): %s \n", + hna_local_entry->addr, message); hash_remove(hna_local_hash, hna_local_entry->addr); _hna_local_del(hna_local_entry); @@ -278,13 +272,10 @@ void hna_global_add_orig(struct orig_node *orig_node, struct hna_global_entry *hna_global_entry; struct hna_local_entry *hna_local_entry; struct hashtable_t *swaphash; - char hna_str[ETH_STR_LEN], orig_str[ETH_STR_LEN]; int hna_buff_count = 0; unsigned long flags; unsigned char *hna_ptr; - addr_to_string(orig_str, orig_node->orig); - while ((hna_buff_count + 1) * ETH_ALEN <= hna_buff_len) { spin_lock_irqsave(&hna_global_hash_lock, flags); @@ -304,10 +295,9 @@ void hna_global_add_orig(struct orig_node *orig_node, memcpy(hna_global_entry->addr, hna_ptr, ETH_ALEN); - addr_to_string(hna_str, hna_global_entry->addr); bat_dbg(DBG_ROUTES, - "Creating new global hna entry: %s (via %s)\n", - hna_str, orig_str); + "Creating new global hna entry: %pM (via %pM)\n", + hna_global_entry->addr, orig_node->orig); spin_lock_irqsave(&hna_global_hash_lock, flags); hash_add(hna_global_hash, hna_global_entry); @@ -399,13 +389,9 @@ int hna_global_fill_buffer_text(unsigned char *buff, int buff_len) void _hna_global_del_orig(struct hna_global_entry *hna_global_entry, char *message) { - char hna_str[ETH_STR_LEN], orig_str[ETH_STR_LEN]; - - addr_to_string(orig_str, hna_global_entry->orig_node->orig); - addr_to_string(hna_str, hna_global_entry->addr); - - bat_dbg(DBG_ROUTES, "Deleting global hna entry %s (via %s): %s \n", - hna_str, orig_str, message); + bat_dbg(DBG_ROUTES, "Deleting global hna entry %pM (via %pM): %s \n", + hna_global_entry->addr, hna_global_entry->orig_node->orig, + message); hash_remove(hna_global_hash, hna_global_entry->addr); kfree(hna_global_entry); -- cgit v1.2.3 From abad5446585b0b9519fad00c05156f373ea114ad Mon Sep 17 00:00:00 2001 From: Simon Wunderlich Date: Sat, 2 Jan 2010 11:30:51 +0100 Subject: Staging: batman-adv: Remove compat.h Since we are now part of mainline, we don't need compat.h to allow building of the module with old versions of the kernel. Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/TODO | 3 - drivers/staging/batman-adv/compat.h | 121 ------------------------- drivers/staging/batman-adv/device.c | 2 - drivers/staging/batman-adv/hard-interface.c | 1 - drivers/staging/batman-adv/main.c | 1 - drivers/staging/batman-adv/originator.c | 16 +--- drivers/staging/batman-adv/proc.c | 1 - drivers/staging/batman-adv/routing.c | 2 - drivers/staging/batman-adv/send.c | 2 - drivers/staging/batman-adv/soft-interface.c | 6 +- drivers/staging/batman-adv/translation-table.c | 1 - drivers/staging/batman-adv/vis.c | 1 - 12 files changed, 6 insertions(+), 151 deletions(-) delete mode 100644 drivers/staging/batman-adv/compat.h (limited to 'drivers') diff --git a/drivers/staging/batman-adv/TODO b/drivers/staging/batman-adv/TODO index 2122adc6aa84..2f15136b18e7 100644 --- a/drivers/staging/batman-adv/TODO +++ b/drivers/staging/batman-adv/TODO @@ -17,9 +17,6 @@ -> transtable_global (read-only) [outputs the global translation table] -> transtable_local (read-only) [outputs the local translation table] -=> strip out all backward compatibility support to older kernels - (only found in compat.h) - => fix checkpatch.pl errors Please send all patches to: diff --git a/drivers/staging/batman-adv/compat.h b/drivers/staging/batman-adv/compat.h deleted file mode 100644 index ded1e6e15240..000000000000 --- a/drivers/staging/batman-adv/compat.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (C) 2007-2009 B.A.T.M.A.N. contributors: - * - * Marek Lindner, Simon Wunderlich - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of version 2 of the GNU General Public - * License as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA - * - * - * This file contains macros for maintaining compatibility with older versions - * of the Linux kernel. - */ - -#include /* LINUX_VERSION_CODE */ - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22) - -#define skb_set_network_header(_skb, _offset) \ - do { (_skb)->nh.raw = (_skb)->data + (_offset); } while (0) - -#define skb_reset_mac_header(_skb) \ - do { (_skb)->mac.raw = (_skb)->data; } while (0) - -#define list_first_entry(ptr, type, member) \ - list_entry((ptr)->next, type, member) - -#define skb_mac_header(_skb) \ - ((_skb)->mac.raw) - -#define skb_network_header(_skb) \ - ((_skb)->nh.raw) - -#define skb_mac_header(_skb) \ - ((_skb)->mac.raw) - -#endif /* < KERNEL_VERSION(2,6,22) */ - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 23) - -static inline int skb_clone_writable(struct sk_buff *skb, unsigned int len) -{ - /* skb->hdr_len not available, just "not writable" to enforce a copy */ - return 0; -} - -#define cancel_delayed_work_sync(wq) cancel_rearming_delayed_work(wq) - -#endif /* < KERNEL_VERSION(2, 6, 23) */ - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25) - -#define strict_strtoul(cp, base, res) \ - ({ \ - int ret = 0; \ - char *endp; \ - *res = simple_strtoul(cp, &endp, base); \ - if (cp == endp) \ - ret = -EINVAL; \ - ret; \ -}) - -#endif /* < KERNEL_VERSION(2, 6, 25) */ - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26) - -static const char hex_asc[] = "0123456789abcdef"; -#define hex_asc_lo(x) hex_asc[((x) & 0x0f)] -#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4] -static inline char *pack_hex_byte(char *buf, u8 byte) -{ - *buf++ = hex_asc_hi(byte); - *buf++ = hex_asc_lo(byte); - return buf; -} - -#define device_create(_cls, _parent, _devt, _device, _fmt) \ - class_device_create(_cls, _parent, _devt, _device, _fmt) - -#define device_destroy(_cls, _device) \ - class_device_destroy(_cls, _device) - -#endif /* < KERNEL_VERSION(2, 6, 26) */ - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27) - -#ifndef dereference_function_descriptor -#define dereference_function_descriptor(p) (p) -#endif - -#ifndef device_create -#define device_create(_cls, _parent, _devt, _device, _fmt) \ - device_create_drvdata(_cls, _parent, _devt, _device, _fmt) -#endif - -#endif /* < KERNEL_VERSION(2, 6, 27) */ - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29) - -asmlinkage int bat_printk(const char *fmt, ...); -#define printk bat_printk - -static inline struct net_device_stats *dev_get_stats(struct net_device *dev) -{ - if (dev->get_stats) - return dev->get_stats(dev); - else - return NULL; -} - -#endif /* < KERNEL_VERSION(2, 6, 29) */ diff --git a/drivers/staging/batman-adv/device.c b/drivers/staging/batman-adv/device.c index 72306acec5e6..a3e74296abfd 100644 --- a/drivers/staging/batman-adv/device.c +++ b/drivers/staging/batman-adv/device.c @@ -26,8 +26,6 @@ #include "types.h" #include "hash.h" -#include "compat.h" - static struct class *batman_class; static int Major; /* Major number assigned to our device driver */ diff --git a/drivers/staging/batman-adv/hard-interface.c b/drivers/staging/batman-adv/hard-interface.c index db264bd0bf9d..f8b1ba3910ad 100644 --- a/drivers/staging/batman-adv/hard-interface.c +++ b/drivers/staging/batman-adv/hard-interface.c @@ -26,7 +26,6 @@ #include "translation-table.h" #include "routing.h" #include "hash.h" -#include "compat.h" #define MIN(x, y) ((x) < (y) ? (x) : (y)) diff --git a/drivers/staging/batman-adv/main.c b/drivers/staging/batman-adv/main.c index 1d80ea366be3..3f780753a2bf 100644 --- a/drivers/staging/batman-adv/main.c +++ b/drivers/staging/batman-adv/main.c @@ -31,7 +31,6 @@ #include "types.h" #include "vis.h" #include "hash.h" -#include "compat.h" struct list_head if_list; struct hlist_head forw_bat_list; diff --git a/drivers/staging/batman-adv/originator.c b/drivers/staging/batman-adv/originator.c index a60dbe1cf6bf..29c241119a3b 100644 --- a/drivers/staging/batman-adv/originator.c +++ b/drivers/staging/batman-adv/originator.c @@ -26,8 +26,6 @@ #include "hash.h" #include "translation-table.h" #include "routing.h" -#include "compat.h" - static DECLARE_DELAYED_WORK(purge_orig_wq, purge_orig); @@ -80,11 +78,10 @@ create_neighbor(struct orig_node *orig_node, struct orig_node *orig_neigh_node, bat_dbg(DBG_BATMAN, "Creating new last-hop neighbor of originator\n"); - neigh_node = kmalloc(sizeof(struct neigh_node), GFP_ATOMIC); + neigh_node = kzalloc(sizeof(struct neigh_node), GFP_ATOMIC); if (!neigh_node) return NULL; - memset(neigh_node, 0, sizeof(struct neigh_node)); INIT_LIST_HEAD(&neigh_node->list); memcpy(neigh_node->addr, neigh, ETH_ALEN); @@ -131,11 +128,10 @@ struct orig_node *get_orig_node(uint8_t *addr) bat_dbg(DBG_BATMAN, "Creating new originator: %pM \n", addr); - orig_node = kmalloc(sizeof(struct orig_node), GFP_ATOMIC); + orig_node = kzalloc(sizeof(struct orig_node), GFP_ATOMIC); if (!orig_node) return NULL; - memset(orig_node, 0, sizeof(struct orig_node)); INIT_LIST_HEAD(&orig_node->neigh_list); memcpy(orig_node->orig, addr, ETH_ALEN); @@ -145,19 +141,15 @@ struct orig_node *get_orig_node(uint8_t *addr) size = num_ifs * sizeof(TYPE_OF_WORD) * NUM_WORDS; - orig_node->bcast_own = kmalloc(size, GFP_ATOMIC); + orig_node->bcast_own = kzalloc(size, GFP_ATOMIC); if (!orig_node->bcast_own) goto free_orig_node; - memset(orig_node->bcast_own, 0, size); - size = num_ifs * sizeof(uint8_t); - orig_node->bcast_own_sum = kmalloc(size, GFP_ATOMIC); + orig_node->bcast_own_sum = kzalloc(size, GFP_ATOMIC); if (!orig_node->bcast_own_sum) goto free_bcast_own; - memset(orig_node->bcast_own_sum, 0, size); - if (hash_add(orig_hash, orig_node) < 0) goto free_bcast_own_sum; diff --git a/drivers/staging/batman-adv/proc.c b/drivers/staging/batman-adv/proc.c index 33dae941a5c9..4d199351c2b4 100644 --- a/drivers/staging/batman-adv/proc.c +++ b/drivers/staging/batman-adv/proc.c @@ -27,7 +27,6 @@ #include "types.h" #include "hash.h" #include "vis.h" -#include "compat.h" static struct proc_dir_entry *proc_batman_dir, *proc_interface_file; static struct proc_dir_entry *proc_orig_interval_file, *proc_originators_file; diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index bab7a73e17a5..09917e57b41c 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -32,7 +32,6 @@ #include "ring_buffer.h" #include "vis.h" #include "aggregation.h" -#include "compat.h" DECLARE_WAIT_QUEUE_HEAD(thread_wait); @@ -310,7 +309,6 @@ static void update_orig(struct orig_node *orig_node, struct ethhdr *ethhdr, update_hna: update_routes(orig_node, orig_node->router, hna_buff, tmp_hna_buff_len); - return; } static char count_real_packets(struct ethhdr *ethhdr, diff --git a/drivers/staging/batman-adv/send.c b/drivers/staging/batman-adv/send.c index edfdd5d9279b..944b2cdbdff8 100644 --- a/drivers/staging/batman-adv/send.c +++ b/drivers/staging/batman-adv/send.c @@ -29,8 +29,6 @@ #include "vis.h" #include "aggregation.h" -#include "compat.h" - /* apply hop penalty for a normal link */ static uint8_t hop_penalty(const uint8_t tq) { diff --git a/drivers/staging/batman-adv/soft-interface.c b/drivers/staging/batman-adv/soft-interface.c index bc0217b1aeb1..c9b35d9f7991 100644 --- a/drivers/staging/batman-adv/soft-interface.c +++ b/drivers/staging/batman-adv/soft-interface.c @@ -28,7 +28,6 @@ #include "hash.h" #include #include -#include "compat.h" static uint16_t bcast_seqno = 1; /* give own bcast messages seq numbers to avoid * broadcast storms */ @@ -120,7 +119,7 @@ void interface_setup(struct net_device *dev) /* generate random address */ random_ether_addr(dev_addr); - memcpy(dev->dev_addr, dev_addr, sizeof(dev->dev_addr)); + memcpy(dev->dev_addr, dev_addr, ETH_ALEN); SET_ETHTOOL_OPS(dev, &bat_ethtool_ops); @@ -269,7 +268,7 @@ unlock: dropped: priv->stats.tx_dropped++; end: - return 0; + return NETDEV_TX_OK; } void interface_rx(struct sk_buff *skb, int hdr_size) @@ -338,7 +337,6 @@ static u32 bat_get_msglevel(struct net_device *dev) static void bat_set_msglevel(struct net_device *dev, u32 value) { - return; } static u32 bat_get_link(struct net_device *dev) diff --git a/drivers/staging/batman-adv/translation-table.c b/drivers/staging/batman-adv/translation-table.c index 398a8084660a..d56f6654de0d 100644 --- a/drivers/staging/batman-adv/translation-table.c +++ b/drivers/staging/batman-adv/translation-table.c @@ -24,7 +24,6 @@ #include "soft-interface.h" #include "types.h" #include "hash.h" -#include "compat.h" struct hashtable_t *hna_local_hash; static struct hashtable_t *hna_global_hash; diff --git a/drivers/staging/batman-adv/vis.c b/drivers/staging/batman-adv/vis.c index 191297926b3f..ec8bb3f382c6 100644 --- a/drivers/staging/batman-adv/vis.c +++ b/drivers/staging/batman-adv/vis.c @@ -26,7 +26,6 @@ #include "soft-interface.h" #include "hard-interface.h" #include "hash.h" -#include "compat.h" struct hashtable_t *vis_hash; DEFINE_SPINLOCK(vis_hash_lock); -- cgit v1.2.3 From 4230020c42457e51c98636a328c60e9f3744152c Mon Sep 17 00:00:00 2001 From: Linus Lüssing Date: Sat, 2 Jan 2010 11:30:52 +0100 Subject: Staging: batman-adv: Dont deactivate aggregation on wrong input MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A non-integer changes the aggregation mode. Therefore this patch changes the behaviour to explicitly check strict_strtoul()'s return code. Signed-off-by: Linus Lüssing Acked-by: Simon Wunderlich Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/proc.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/proc.c b/drivers/staging/batman-adv/proc.c index 4d199351c2b4..68c36b097a07 100644 --- a/drivers/staging/batman-adv/proc.c +++ b/drivers/staging/batman-adv/proc.c @@ -427,6 +427,7 @@ static ssize_t proc_aggr_write(struct file *file, const char __user *buffer, char *aggr_string; int not_copied = 0; unsigned long aggregation_enabled_tmp; + int retval; aggr_string = kmalloc(count, GFP_KERNEL); @@ -436,22 +437,21 @@ static ssize_t proc_aggr_write(struct file *file, const char __user *buffer, not_copied = copy_from_user(aggr_string, buffer, count); aggr_string[count - not_copied - 1] = 0; - strict_strtoul(aggr_string, 10, &aggregation_enabled_tmp); + retval = strict_strtoul(aggr_string, 10, &aggregation_enabled_tmp); - if ((aggregation_enabled_tmp != 0) && (aggregation_enabled_tmp != 1)) { + if (retval || aggregation_enabled_tmp > 1) { printk(KERN_ERR "batman-adv:Aggregation can only be enabled (1) or disabled (0), given value: %li\n", aggregation_enabled_tmp); - goto end; + } else { + printk(KERN_INFO "batman-adv:Changing aggregation from: %s (%i) to: %s (%li)\n", + (atomic_read(&aggregation_enabled) == 1 ? + "enabled" : "disabled"), + atomic_read(&aggregation_enabled), + (aggregation_enabled_tmp == 1 ? "enabled" : "disabled"), + aggregation_enabled_tmp); + atomic_set(&aggregation_enabled, + (unsigned)aggregation_enabled_tmp); } - printk(KERN_INFO "batman-adv:Changing aggregation from: %s (%i) to: %s (%li)\n", - (atomic_read(&aggregation_enabled) == 1 ? - "enabled" : "disabled"), - atomic_read(&aggregation_enabled), - (aggregation_enabled_tmp == 1 ? "enabled" : "disabled"), - aggregation_enabled_tmp); - - atomic_set(&aggregation_enabled, (unsigned)aggregation_enabled_tmp); -end: kfree(aggr_string); return count; } -- cgit v1.2.3 From 65e65a3e73b31c097e59c6e8d4a9ed1eebbe9d8d Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 8 Jan 2010 10:20:27 -0800 Subject: Staging: hv: remove unneeded OnHostRescan callback This callback was never called, so delete the thing. Cc: Hank Janssen Cc: Haiyang Zhang . Signed-off-by: Greg Kroah-Hartman --- drivers/staging/hv/StorVscApi.h | 3 --- drivers/staging/hv/storvsc_drv.c | 1 - 2 files changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/hv/StorVscApi.h b/drivers/staging/hv/StorVscApi.h index 69c14066c479..1aca24e65035 100644 --- a/drivers/staging/hv/StorVscApi.h +++ b/drivers/staging/hv/StorVscApi.h @@ -91,9 +91,6 @@ struct storvsc_driver_object { /* Maximum # of requests in flight per channel/device */ u32 MaxOutstandingRequestsPerChannel; - /* Set by the caller to allow us to re-enumerate the bus on the host */ - void (*OnHostRescan)(struct hv_device *Device); - /* Specific to this driver */ int (*OnIORequest)(struct hv_device *Device, struct hv_storvsc_request *Request); diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c index d49dc21d4cb4..c3839626aeda 100644 --- a/drivers/staging/hv/storvsc_drv.c +++ b/drivers/staging/hv/storvsc_drv.c @@ -148,7 +148,6 @@ static int storvsc_drv_init(int (*drv_init)(struct hv_driver *drv)) vmbus_get_interface(&storvsc_drv_obj->Base.VmbusChannelInterface); storvsc_drv_obj->RingBufferSize = storvsc_ringbuffer_size; - storvsc_drv_obj->OnHostRescan = storvsc_host_rescan; /* Callback to client driver to complete the initialization */ drv_init(&storvsc_drv_obj->Base); -- cgit v1.2.3 From 99358ca725513de0a97971eb019d4a5544d83760 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 8 Jan 2010 10:21:58 -0800 Subject: Staging: hv: storvsc_drv: move unused functions Now that the callback pointer was removed, we can remove the code itself, as it is never used. Cc: Hank Janssen Cc: Haiyang Zhang . Signed-off-by: Greg Kroah-Hartman --- drivers/staging/hv/storvsc_drv.c | 204 --------------------------------------- 1 file changed, 204 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c index c3839626aeda..56c911e7ade5 100644 --- a/drivers/staging/hv/storvsc_drv.c +++ b/drivers/staging/hv/storvsc_drv.c @@ -39,8 +39,6 @@ struct host_device_context { /* must be 1st field * FIXME this is a bug */ - struct work_struct host_rescan_work; - /* point back to our device context */ struct device_context *device_ctx; struct kmem_cache *request_pool; @@ -77,8 +75,6 @@ static int storvsc_queuecommand(struct scsi_cmnd *scmnd, static int storvsc_device_alloc(struct scsi_device *); static int storvsc_device_configure(struct scsi_device *); static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd); -static void storvsc_host_rescan_callback(struct work_struct *work); -static void storvsc_host_rescan(struct hv_device *device_obj); static int storvsc_remove(struct device *dev); static struct scatterlist *create_bounce_buffer(struct scatterlist *sgl, @@ -94,8 +90,6 @@ static unsigned int copy_to_bounce_buffer(struct scatterlist *orig_sgl, struct scatterlist *bounce_sgl, unsigned int orig_sgl_count); -static int storvsc_report_luns(struct scsi_device *sdev, unsigned int luns[], - unsigned int *lun_count); static int storvsc_get_chs(struct scsi_device *sdev, struct block_device *bdev, sector_t capacity, int *info); @@ -265,9 +259,6 @@ static int storvsc_probe(struct device *device) host_device_ctx->port = host->host_no; host_device_ctx->device_ctx = device_ctx; - INIT_WORK(&host_device_ctx->host_rescan_work, - storvsc_host_rescan_callback); - host_device_ctx->request_pool = kmem_cache_create(dev_name(&device_ctx->device), sizeof(struct storvsc_cmd_request) + @@ -908,201 +899,6 @@ static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd) return ret; } -/** - * storvsc_host_rescan - Rescan the scsi HBA - */ -static void storvsc_host_rescan_callback(struct work_struct *work) -{ - struct hv_device *device_obj = - &((struct host_device_context *)work)->device_ctx->device_obj; - struct device_context *device_ctx = to_device_context(device_obj); - struct Scsi_Host *host = dev_get_drvdata(&device_ctx->device); - struct scsi_device *sdev; - struct host_device_context *host_device_ctx; - struct scsi_device **sdevs_remove_list; - unsigned int sdevs_count = 0; - unsigned int found; - unsigned int i; - unsigned int lun_count = 0; - unsigned int *lun_list; - - DPRINT_ENTER(STORVSC_DRV); - - host_device_ctx = (struct host_device_context *)host->hostdata; - lun_list = kcalloc(STORVSC_MAX_LUNS_PER_TARGET, sizeof(unsigned int), - GFP_ATOMIC); - if (!lun_list) { - DPRINT_ERR(STORVSC_DRV, "unable to allocate lun list"); - return; - } - - sdevs_remove_list = kcalloc(STORVSC_MAX_LUNS_PER_TARGET, - sizeof(void *), GFP_ATOMIC); - if (!sdevs_remove_list) { - kfree(lun_list); - DPRINT_ERR(STORVSC_DRV, "unable to allocate lun remove list"); - return; - } - - DPRINT_INFO(STORVSC_DRV, "rescanning host for new scsi devices..."); - - /* Rescan for new device */ - scsi_scan_target(&host->shost_gendev, host_device_ctx->path, - host_device_ctx->target, SCAN_WILD_CARD, 1); - - DPRINT_INFO(STORVSC_DRV, "rescanning host for removed scsi device..."); - - /* Use the 1st device to send the report luns cmd */ - shost_for_each_device(sdev, host) { - lun_count = STORVSC_MAX_LUNS_PER_TARGET; - storvsc_report_luns(sdev, lun_list, &lun_count); - - DPRINT_INFO(STORVSC_DRV, - "report luns on scsi device (%p) found %u luns ", - sdev, lun_count); - DPRINT_INFO(STORVSC_DRV, - "existing luns on scsi device (%p) host (%d)", - sdev, host->host_no); - - scsi_device_put(sdev); - break; - } - - for (i = 0; i < lun_count; i++) - DPRINT_INFO(STORVSC_DRV, "%d) lun %u", i, lun_list[i]); - - /* Rescan for devices that may have been removed. - * We do not have to worry that new devices may have been added since - * this callback is serialized by the workqueue ie add/remove are done - * here. - */ - shost_for_each_device(sdev, host) { - /* See if this device is still here */ - found = 0; - for (i = 0; i < lun_count; i++) { - if (sdev->lun == lun_list[i]) { - found = 1; - break; - } - } - if (!found) { - DPRINT_INFO(STORVSC_DRV, "lun (%u) does not exists", - sdev->lun); - sdevs_remove_list[sdevs_count++] = sdev; - } - } - - /* Now remove the devices */ - for (i = 0; i < sdevs_count; i++) { - DPRINT_INFO(STORVSC_DRV, - "removing scsi device (%p) lun (%u)...", - sdevs_remove_list[i], sdevs_remove_list[i]->lun); - - /* make sure it is not removed from underneath us */ - if (!scsi_device_get(sdevs_remove_list[i])) { - scsi_remove_device(sdevs_remove_list[i]); - scsi_device_put(sdevs_remove_list[i]); - } - } - - DPRINT_INFO(STORVSC_DRV, "rescan completed on dev obj (%p) " - "target (%u) bus (%u)", device_obj, - host_device_ctx->target, host_device_ctx->path); - - kfree(lun_list); - kfree(sdevs_remove_list); - - DPRINT_EXIT(STORVSC_DRV); -} - -static int storvsc_report_luns(struct scsi_device *sdev, unsigned int luns[], - unsigned int *lun_count) -{ - int i, j; - unsigned int lun = 0; - unsigned int num_luns; - int result; - unsigned char *data; - struct scsi_sense_hdr sshdr; - unsigned char cmd[16] = {0}; - /* Add 1 to cover the report_lun header */ - unsigned int report_len = 8 * (STORVSC_MAX_LUNS_PER_TARGET+1); - unsigned long long *report_luns; - const unsigned int in_lun_count = *lun_count; - - *lun_count = 0; - - report_luns = kzalloc(report_len, GFP_ATOMIC); - if (!report_luns) - return -ENOMEM; - - cmd[0] = REPORT_LUNS; - - /* cmd length */ - *(unsigned int *)&cmd[6] = cpu_to_be32(report_len); - - result = scsi_execute_req(sdev, cmd, DMA_FROM_DEVICE, - (unsigned char *)report_luns, report_len, - &sshdr, 30 * HZ, 3, NULL); - if (result != 0) { - kfree(report_luns); - return -EBUSY; - } - - /* get the length from the first four bytes */ - report_len = be32_to_cpu(*(unsigned int *)&report_luns[0]); - - num_luns = (report_len / sizeof(unsigned long long)); - if (num_luns > in_lun_count) { - kfree(report_luns); - return -EINVAL; - } - - *lun_count = num_luns; - - DPRINT_DBG(STORVSC_DRV, - "report luns on scsi device (%p) found %u luns ", - sdev, num_luns); - - /* lun id starts at 1 */ - for (i = 1; i < num_luns + 1; i++) { - lun = 0; - data = (unsigned char *)&report_luns[i]; - for (j = 0; j < sizeof(lun); j += 2) { - lun = lun | (((data[j] << 8) | data[j + 1]) << - (j * 8)); - } - - luns[i-1] = lun; - } - - kfree(report_luns); - return 0; -} - -static void storvsc_host_rescan(struct hv_device *device_obj) -{ - struct device_context *device_ctx = to_device_context(device_obj); - struct Scsi_Host *host = dev_get_drvdata(&device_ctx->device); - struct host_device_context *host_device_ctx; - - DPRINT_ENTER(STORVSC_DRV); - - host_device_ctx = (struct host_device_context *)host->hostdata; - - DPRINT_INFO(STORVSC_DRV, "initiating rescan on dev obj (%p) " - "target (%u) bus (%u)...", device_obj, - host_device_ctx->target, host_device_ctx->path); - - /* - * We need to queue this since the scanning may block and the caller - * may be in an intr context - */ - /* scsi_queue_work(host, &host_device_ctx->host_rescan_work); */ - schedule_work(&host_device_ctx->host_rescan_work); - DPRINT_EXIT(STORVSC_DRV); -} - static int storvsc_get_chs(struct scsi_device *sdev, struct block_device * bdev, sector_t capacity, int *info) { -- cgit v1.2.3 From 354b0a643e89dd3163278c9a0ac9cbcb9ef5c298 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 8 Jan 2010 10:24:26 -0800 Subject: Staging: hv: remove unneeded OnHostReset callback This callback only calls one function, so just call the function instead, no need for indirection at all. Cc: Hank Janssen Cc: Haiyang Zhang . Signed-off-by: Greg Kroah-Hartman --- drivers/staging/hv/StorVsc.c | 3 +-- drivers/staging/hv/StorVscApi.h | 2 +- drivers/staging/hv/storvsc_drv.c | 10 +--------- 3 files changed, 3 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/hv/StorVsc.c b/drivers/staging/hv/StorVsc.c index 2f7c425896f7..38ea1407f222 100644 --- a/drivers/staging/hv/StorVsc.c +++ b/drivers/staging/hv/StorVsc.c @@ -625,7 +625,7 @@ static int StorVscOnDeviceRemove(struct hv_device *Device) return 0; } -static int StorVscOnHostReset(struct hv_device *Device) +int StorVscOnHostReset(struct hv_device *Device) { struct storvsc_device *storDevice; struct storvsc_request_extension *request; @@ -842,7 +842,6 @@ int StorVscInitialize(struct hv_driver *Driver) storDriver->Base.OnCleanup = StorVscOnCleanup; storDriver->OnIORequest = StorVscOnIORequest; - storDriver->OnHostReset = StorVscOnHostReset; DPRINT_EXIT(STORVSC); diff --git a/drivers/staging/hv/StorVscApi.h b/drivers/staging/hv/StorVscApi.h index 1aca24e65035..126a8588edb1 100644 --- a/drivers/staging/hv/StorVscApi.h +++ b/drivers/staging/hv/StorVscApi.h @@ -94,7 +94,6 @@ struct storvsc_driver_object { /* Specific to this driver */ int (*OnIORequest)(struct hv_device *Device, struct hv_storvsc_request *Request); - int (*OnHostReset)(struct hv_device *Device); }; struct storvsc_device_info { @@ -105,6 +104,7 @@ struct storvsc_device_info { /* Interface */ int StorVscInitialize(struct hv_driver *driver); +int StorVscOnHostReset(struct hv_device *Device); int BlkVscInitialize(struct hv_driver *driver); #endif /* _STORVSC_API_H_ */ diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c index 56c911e7ade5..12f8f3f64c61 100644 --- a/drivers/staging/hv/storvsc_drv.c +++ b/drivers/staging/hv/storvsc_drv.c @@ -870,13 +870,6 @@ static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd) struct host_device_context *host_device_ctx = (struct host_device_context *)scmnd->device->host->hostdata; struct device_context *device_ctx = host_device_ctx->device_ctx; - struct driver_context *driver_ctx = - driver_to_driver_context(device_ctx->device.driver); - struct storvsc_driver_context *storvsc_drv_ctx = - (struct storvsc_driver_context *)driver_ctx; - - struct storvsc_driver_object *storvsc_drv_obj = - &storvsc_drv_ctx->drv_obj; DPRINT_ENTER(STORVSC_DRV); @@ -884,8 +877,7 @@ static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd) scmnd->device, &device_ctx->device_obj); /* Invokes the vsc to reset the host/bus */ - ASSERT(storvsc_drv_obj->OnHostReset); - ret = storvsc_drv_obj->OnHostReset(&device_ctx->device_obj); + ret = StorVscOnHostReset(&device_ctx->device_obj); if (ret != 0) { DPRINT_EXIT(STORVSC_DRV); return ret; -- cgit v1.2.3 From 2d0753464b497287565c2e54d3ae67666852ef57 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 8 Jan 2010 10:24:42 -0800 Subject: Staging: hv: remove unneeded OnOpen callback This callback only calls one function, so just call the function instead, no need for indirection at all. Cc: Hank Janssen Cc: Haiyang Zhang . Signed-off-by: Greg Kroah-Hartman --- drivers/staging/hv/NetVscApi.h | 2 +- drivers/staging/hv/RndisFilter.c | 5 +---- drivers/staging/hv/netvsc_drv.c | 7 +------ 3 files changed, 3 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/hv/NetVscApi.h b/drivers/staging/hv/NetVscApi.h index 1ce2b74a34a7..93b9226ff3b5 100644 --- a/drivers/staging/hv/NetVscApi.h +++ b/drivers/staging/hv/NetVscApi.h @@ -105,7 +105,6 @@ struct netvsc_driver { void (*OnLinkStatusChanged)(struct hv_device *dev, u32 Status); /* Specific to this driver */ - int (*OnOpen)(struct hv_device *dev); int (*OnClose)(struct hv_device *dev); int (*OnSend)(struct hv_device *dev, struct hv_netvsc_packet *packet); @@ -119,5 +118,6 @@ struct netvsc_device_info { /* Interface */ int NetVscInitialize(struct hv_driver *drv); +int RndisFilterOnOpen(struct hv_device *Device); #endif /* _NETVSC_API_H_ */ diff --git a/drivers/staging/hv/RndisFilter.c b/drivers/staging/hv/RndisFilter.c index 26d79975387c..74f741eb1296 100644 --- a/drivers/staging/hv/RndisFilter.c +++ b/drivers/staging/hv/RndisFilter.c @@ -85,8 +85,6 @@ static int RndisFilterOnDeviceRemove(struct hv_device *Device); static void RndisFilterOnCleanup(struct hv_driver *Driver); -static int RndisFilterOnOpen(struct hv_device *Device); - static int RndisFilterOnClose(struct hv_device *Device); static int RndisFilterOnSend(struct hv_device *Device, @@ -654,7 +652,6 @@ int RndisFilterInit(struct netvsc_driver *Driver) Driver->Base.OnDeviceRemove = RndisFilterOnDeviceRemove; Driver->Base.OnCleanup = RndisFilterOnCleanup; Driver->OnSend = RndisFilterOnSend; - Driver->OnOpen = RndisFilterOnOpen; Driver->OnClose = RndisFilterOnClose; /* Driver->QueryLinkStatus = RndisFilterQueryDeviceLinkStatus; */ Driver->OnReceiveCallback = RndisFilterOnReceive; @@ -888,7 +885,7 @@ static void RndisFilterOnCleanup(struct hv_driver *Driver) DPRINT_EXIT(NETVSC); } -static int RndisFilterOnOpen(struct hv_device *Device) +int RndisFilterOnOpen(struct hv_device *Device) { int ret; struct netvsc_device *netDevice = Device->Extension; diff --git a/drivers/staging/hv/netvsc_drv.c b/drivers/staging/hv/netvsc_drv.c index 0d7459e2d036..515cd2361bf2 100644 --- a/drivers/staging/hv/netvsc_drv.c +++ b/drivers/staging/hv/netvsc_drv.c @@ -72,11 +72,6 @@ static void netvsc_set_multicast_list(struct net_device *net) static int netvsc_open(struct net_device *net) { struct net_device_context *net_device_ctx = netdev_priv(net); - struct driver_context *driver_ctx = - driver_to_driver_context(net_device_ctx->device_ctx->device.driver); - struct netvsc_driver_context *net_drv_ctx = - (struct netvsc_driver_context *)driver_ctx; - struct netvsc_driver *net_drv_obj = &net_drv_ctx->drv_obj; struct hv_device *device_obj = &net_device_ctx->device_ctx->device_obj; int ret = 0; @@ -87,7 +82,7 @@ static int netvsc_open(struct net_device *net) sizeof(struct net_device_stats)); /* Open up the device */ - ret = net_drv_obj->OnOpen(device_obj); + ret = RndisFilterOnOpen(device_obj); if (ret != 0) { DPRINT_ERR(NETVSC_DRV, "unable to open device (ret %d).", ret); -- cgit v1.2.3 From 4f28900bcf9bb5e6fb0c18fc7ee325df66fe8bbd Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 8 Jan 2010 10:25:01 -0800 Subject: Staging: hv: remove unneeded OnClose callback This callback only calls one function, so just call the function instead, no need for indirection at all. Cc: Hank Janssen Cc: Haiyang Zhang . Signed-off-by: Greg Kroah-Hartman --- drivers/staging/hv/NetVscApi.h | 2 +- drivers/staging/hv/RndisFilter.c | 5 +---- drivers/staging/hv/netvsc_drv.c | 7 +------ 3 files changed, 3 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/hv/NetVscApi.h b/drivers/staging/hv/NetVscApi.h index 93b9226ff3b5..95d7a32b12f2 100644 --- a/drivers/staging/hv/NetVscApi.h +++ b/drivers/staging/hv/NetVscApi.h @@ -105,7 +105,6 @@ struct netvsc_driver { void (*OnLinkStatusChanged)(struct hv_device *dev, u32 Status); /* Specific to this driver */ - int (*OnClose)(struct hv_device *dev); int (*OnSend)(struct hv_device *dev, struct hv_netvsc_packet *packet); void *Context; @@ -119,5 +118,6 @@ struct netvsc_device_info { /* Interface */ int NetVscInitialize(struct hv_driver *drv); int RndisFilterOnOpen(struct hv_device *Device); +int RndisFilterOnClose(struct hv_device *Device); #endif /* _NETVSC_API_H_ */ diff --git a/drivers/staging/hv/RndisFilter.c b/drivers/staging/hv/RndisFilter.c index 74f741eb1296..1ab7fa97d373 100644 --- a/drivers/staging/hv/RndisFilter.c +++ b/drivers/staging/hv/RndisFilter.c @@ -85,8 +85,6 @@ static int RndisFilterOnDeviceRemove(struct hv_device *Device); static void RndisFilterOnCleanup(struct hv_driver *Driver); -static int RndisFilterOnClose(struct hv_device *Device); - static int RndisFilterOnSend(struct hv_device *Device, struct hv_netvsc_packet *Packet); @@ -652,7 +650,6 @@ int RndisFilterInit(struct netvsc_driver *Driver) Driver->Base.OnDeviceRemove = RndisFilterOnDeviceRemove; Driver->Base.OnCleanup = RndisFilterOnCleanup; Driver->OnSend = RndisFilterOnSend; - Driver->OnClose = RndisFilterOnClose; /* Driver->QueryLinkStatus = RndisFilterQueryDeviceLinkStatus; */ Driver->OnReceiveCallback = RndisFilterOnReceive; @@ -900,7 +897,7 @@ int RndisFilterOnOpen(struct hv_device *Device) return ret; } -static int RndisFilterOnClose(struct hv_device *Device) +int RndisFilterOnClose(struct hv_device *Device) { int ret; struct netvsc_device *netDevice = Device->Extension; diff --git a/drivers/staging/hv/netvsc_drv.c b/drivers/staging/hv/netvsc_drv.c index 515cd2361bf2..3234a7c4a429 100644 --- a/drivers/staging/hv/netvsc_drv.c +++ b/drivers/staging/hv/netvsc_drv.c @@ -101,11 +101,6 @@ static int netvsc_open(struct net_device *net) static int netvsc_close(struct net_device *net) { struct net_device_context *net_device_ctx = netdev_priv(net); - struct driver_context *driver_ctx = - driver_to_driver_context(net_device_ctx->device_ctx->device.driver); - struct netvsc_driver_context *net_drv_ctx = - (struct netvsc_driver_context *)driver_ctx; - struct netvsc_driver *net_drv_obj = &net_drv_ctx->drv_obj; struct hv_device *device_obj = &net_device_ctx->device_ctx->device_obj; int ret; @@ -113,7 +108,7 @@ static int netvsc_close(struct net_device *net) netif_stop_queue(net); - ret = net_drv_obj->OnClose(device_obj); + ret = RndisFilterOnClose(device_obj); if (ret != 0) DPRINT_ERR(NETVSC_DRV, "unable to close device (ret %d).", ret); -- cgit v1.2.3 From a73e6b7c508f610eeb315c443d9ac79041124af0 Mon Sep 17 00:00:00 2001 From: Hank Janssen Date: Fri, 22 Jan 2010 19:17:50 +0000 Subject: Staging: hv: Remove xen legacy code and check for Hyper-V Removed legacy XEN layer from hypervisor setup, and made sure only Hyper-V is Is a valid hypervisor to run on. Signed-off-by: Hank Janssen Cc: Haiyang Zhang . Signed-off-by: Greg Kroah-Hartman --- drivers/staging/hv/Hv.c | 205 +++++++++++++++++++----------------------------- drivers/staging/hv/Hv.h | 10 +-- 2 files changed, 84 insertions(+), 131 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/hv/Hv.c b/drivers/staging/hv/Hv.c index c2809f2a2ce0..51149e69f3e8 100644 --- a/drivers/staging/hv/Hv.c +++ b/drivers/staging/hv/Hv.c @@ -208,50 +208,51 @@ int HvInit(void) /* HvQueryHypervisorFeatures(maxLeaf); */ /* - * Determine if we are running on xenlinux (ie x2v shim) or native - * linux + * We only support running on top of Hyper-V */ rdmsrl(HV_X64_MSR_GUEST_OS_ID, gHvContext.GuestId); - if (gHvContext.GuestId == 0) { - /* Write our OS info */ - wrmsrl(HV_X64_MSR_GUEST_OS_ID, HV_LINUX_GUEST_ID); - gHvContext.GuestId = HV_LINUX_GUEST_ID; + + if (gHvContext.GuestId != 0) { + DPRINT_ERR(VMBUS, "Unknown guest id (0x%llx)!!", + gHvContext.GuestId); + goto Cleanup; } + /* Write our OS info */ + wrmsrl(HV_X64_MSR_GUEST_OS_ID, HV_LINUX_GUEST_ID); + gHvContext.GuestId = HV_LINUX_GUEST_ID; + /* See if the hypercall page is already set */ rdmsrl(HV_X64_MSR_HYPERCALL, hypercallMsr.AsUINT64); - if (gHvContext.GuestId == HV_LINUX_GUEST_ID) { - /* Allocate the hypercall page memory */ - /* virtAddr = osd_PageAlloc(1); */ - virtAddr = osd_VirtualAllocExec(PAGE_SIZE); - - if (!virtAddr) { - DPRINT_ERR(VMBUS, - "unable to allocate hypercall page!!"); - goto Cleanup; - } - hypercallMsr.Enable = 1; - /* hypercallMsr.GuestPhysicalAddress = - * virt_to_phys(virtAddr) >> PAGE_SHIFT; */ - hypercallMsr.GuestPhysicalAddress = vmalloc_to_pfn(virtAddr); - wrmsrl(HV_X64_MSR_HYPERCALL, hypercallMsr.AsUINT64); + /* + * Allocate the hypercall page memory + * virtAddr = osd_PageAlloc(1); + */ + virtAddr = osd_VirtualAllocExec(PAGE_SIZE); - /* Confirm that hypercall page did get setup. */ - hypercallMsr.AsUINT64 = 0; - rdmsrl(HV_X64_MSR_HYPERCALL, hypercallMsr.AsUINT64); - if (!hypercallMsr.Enable) { - DPRINT_ERR(VMBUS, "unable to set hypercall page!!"); - goto Cleanup; - } + if (!virtAddr) { + DPRINT_ERR(VMBUS, + "unable to allocate hypercall page!!"); + goto Cleanup; + } - gHvContext.HypercallPage = virtAddr; - } else { - DPRINT_ERR(VMBUS, "Unknown guest id (0x%llx)!!", - gHvContext.GuestId); + hypercallMsr.Enable = 1; + + hypercallMsr.GuestPhysicalAddress = vmalloc_to_pfn(virtAddr); + wrmsrl(HV_X64_MSR_HYPERCALL, hypercallMsr.AsUINT64); + + /* Confirm that hypercall page did get setup. */ + hypercallMsr.AsUINT64 = 0; + rdmsrl(HV_X64_MSR_HYPERCALL, hypercallMsr.AsUINT64); + + if (!hypercallMsr.Enable) { + DPRINT_ERR(VMBUS, "unable to set hypercall page!!"); goto Cleanup; } + gHvContext.HypercallPage = virtAddr; + DPRINT_INFO(VMBUS, "Hypercall page VA=%p, PA=0x%0llx", gHvContext.HypercallPage, (u64)hypercallMsr.GuestPhysicalAddress << PAGE_SHIFT); @@ -273,8 +274,6 @@ int HvInit(void) gHvContext.SignalEventParam->FlagNumber = 0; gHvContext.SignalEventParam->RsvdZ = 0; - /* DPRINT_DBG(VMBUS, "My id %llu", HvGetCurrentPartitionId()); */ - DPRINT_EXIT(VMBUS); return ret; @@ -311,17 +310,14 @@ void HvCleanup(void) kfree(gHvContext.SignalEventBuffer); } - if (gHvContext.GuestId == HV_LINUX_GUEST_ID) { - if (gHvContext.HypercallPage) { - hypercallMsr.AsUINT64 = 0; - wrmsrl(HV_X64_MSR_HYPERCALL, hypercallMsr.AsUINT64); - vfree(gHvContext.HypercallPage); - gHvContext.HypercallPage = NULL; - } + if (gHvContext.HypercallPage) { + hypercallMsr.AsUINT64 = 0; + wrmsrl(HV_X64_MSR_HYPERCALL, hypercallMsr.AsUINT64); + vfree(gHvContext.HypercallPage); + gHvContext.HypercallPage = NULL; } DPRINT_EXIT(VMBUS); - } /** @@ -393,7 +389,7 @@ void HvSynicInit(void *irqarg) union hv_synic_siefp siefp; union hv_synic_sint sharedSint; union hv_synic_scontrol sctrl; - u64 guestID; + u32 irqVector = *((u32 *)(irqarg)); int cpu = smp_processor_id(); @@ -409,71 +405,41 @@ void HvSynicInit(void *irqarg) DPRINT_INFO(VMBUS, "SynIC version: %llx", version); - /* TODO: Handle SMP */ - if (gHvContext.GuestId == HV_XENLINUX_GUEST_ID) { - DPRINT_INFO(VMBUS, "Skipping SIMP and SIEFP setup since " - "it is already set."); - - rdmsrl(HV_X64_MSR_SIMP, simp.AsUINT64); - rdmsrl(HV_X64_MSR_SIEFP, siefp.AsUINT64); - - DPRINT_DBG(VMBUS, "Simp: %llx, Sifep: %llx", - simp.AsUINT64, siefp.AsUINT64); - - /* - * Determine if we are running on xenlinux (ie x2v shim) or - * native linux - */ - rdmsrl(HV_X64_MSR_GUEST_OS_ID, guestID); - if (guestID == HV_LINUX_GUEST_ID) { - gHvContext.synICMessagePage[cpu] = - phys_to_virt(simp.BaseSimpGpa << PAGE_SHIFT); - gHvContext.synICEventPage[cpu] = - phys_to_virt(siefp.BaseSiefpGpa << PAGE_SHIFT); - } else { - DPRINT_ERR(VMBUS, "unknown guest id!!"); - goto Cleanup; - } - DPRINT_DBG(VMBUS, "MAPPED: Simp: %p, Sifep: %p", - gHvContext.synICMessagePage[cpu], - gHvContext.synICEventPage[cpu]); - } else { - gHvContext.synICMessagePage[cpu] = (void *)get_zeroed_page(GFP_ATOMIC); - if (gHvContext.synICMessagePage[cpu] == NULL) { - DPRINT_ERR(VMBUS, - "unable to allocate SYNIC message page!!"); - goto Cleanup; - } + gHvContext.synICMessagePage[cpu] = (void *)get_zeroed_page(GFP_ATOMIC); - gHvContext.synICEventPage[cpu] = (void *)get_zeroed_page(GFP_ATOMIC); - if (gHvContext.synICEventPage[cpu] == NULL) { - DPRINT_ERR(VMBUS, - "unable to allocate SYNIC event page!!"); - goto Cleanup; - } + if (gHvContext.synICMessagePage[cpu] == NULL) { + DPRINT_ERR(VMBUS, + "unable to allocate SYNIC message page!!"); + goto Cleanup; + } - /* Setup the Synic's message page */ - rdmsrl(HV_X64_MSR_SIMP, simp.AsUINT64); - simp.SimpEnabled = 1; - simp.BaseSimpGpa = virt_to_phys(gHvContext.synICMessagePage[cpu]) - >> PAGE_SHIFT; + gHvContext.synICEventPage[cpu] = (void *)get_zeroed_page(GFP_ATOMIC); - DPRINT_DBG(VMBUS, "HV_X64_MSR_SIMP msr set to: %llx", - simp.AsUINT64); + if (gHvContext.synICEventPage[cpu] == NULL) { + DPRINT_ERR(VMBUS, + "unable to allocate SYNIC event page!!"); + goto Cleanup; + } - wrmsrl(HV_X64_MSR_SIMP, simp.AsUINT64); + /* Setup the Synic's message page */ + rdmsrl(HV_X64_MSR_SIMP, simp.AsUINT64); + simp.SimpEnabled = 1; + simp.BaseSimpGpa = virt_to_phys(gHvContext.synICMessagePage[cpu]) + >> PAGE_SHIFT; - /* Setup the Synic's event page */ - rdmsrl(HV_X64_MSR_SIEFP, siefp.AsUINT64); - siefp.SiefpEnabled = 1; - siefp.BaseSiefpGpa = virt_to_phys(gHvContext.synICEventPage[cpu]) - >> PAGE_SHIFT; + DPRINT_DBG(VMBUS, "HV_X64_MSR_SIMP msr set to: %llx", simp.AsUINT64); - DPRINT_DBG(VMBUS, "HV_X64_MSR_SIEFP msr set to: %llx", - siefp.AsUINT64); + wrmsrl(HV_X64_MSR_SIMP, simp.AsUINT64); - wrmsrl(HV_X64_MSR_SIEFP, siefp.AsUINT64); - } + /* Setup the Synic's event page */ + rdmsrl(HV_X64_MSR_SIEFP, siefp.AsUINT64); + siefp.SiefpEnabled = 1; + siefp.BaseSiefpGpa = virt_to_phys(gHvContext.synICEventPage[cpu]) + >> PAGE_SHIFT; + + DPRINT_DBG(VMBUS, "HV_X64_MSR_SIEFP msr set to: %llx", siefp.AsUINT64); + + wrmsrl(HV_X64_MSR_SIEFP, siefp.AsUINT64); /* Setup the interception SINT. */ /* wrmsrl((HV_X64_MSR_SINT0 + HV_SYNIC_INTERCEPTION_SINT_INDEX), */ @@ -505,13 +471,11 @@ void HvSynicInit(void *irqarg) return; Cleanup: - if (gHvContext.GuestId == HV_LINUX_GUEST_ID) { - if (gHvContext.synICEventPage[cpu]) - osd_PageFree(gHvContext.synICEventPage[cpu], 1); + if (gHvContext.synICEventPage[cpu]) + osd_PageFree(gHvContext.synICEventPage[cpu], 1); - if (gHvContext.synICMessagePage[cpu]) - osd_PageFree(gHvContext.synICMessagePage[cpu], 1); - } + if (gHvContext.synICMessagePage[cpu]) + osd_PageFree(gHvContext.synICMessagePage[cpu], 1); DPRINT_EXIT(VMBUS); return; @@ -542,27 +506,20 @@ void HvSynicCleanup(void *arg) /* Disable the interrupt */ wrmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, sharedSint.AsUINT64); - /* - * Disable and free the resources only if we are running as - * native linux since in xenlinux, we are sharing the - * resources with the x2v shim - */ - if (gHvContext.GuestId == HV_LINUX_GUEST_ID) { - rdmsrl(HV_X64_MSR_SIMP, simp.AsUINT64); - simp.SimpEnabled = 0; - simp.BaseSimpGpa = 0; + rdmsrl(HV_X64_MSR_SIMP, simp.AsUINT64); + simp.SimpEnabled = 0; + simp.BaseSimpGpa = 0; - wrmsrl(HV_X64_MSR_SIMP, simp.AsUINT64); + wrmsrl(HV_X64_MSR_SIMP, simp.AsUINT64); - rdmsrl(HV_X64_MSR_SIEFP, siefp.AsUINT64); - siefp.SiefpEnabled = 0; - siefp.BaseSiefpGpa = 0; + rdmsrl(HV_X64_MSR_SIEFP, siefp.AsUINT64); + siefp.SiefpEnabled = 0; + siefp.BaseSiefpGpa = 0; - wrmsrl(HV_X64_MSR_SIEFP, siefp.AsUINT64); + wrmsrl(HV_X64_MSR_SIEFP, siefp.AsUINT64); - osd_PageFree(gHvContext.synICMessagePage[cpu], 1); - osd_PageFree(gHvContext.synICEventPage[cpu], 1); - } + osd_PageFree(gHvContext.synICMessagePage[cpu], 1); + osd_PageFree(gHvContext.synICEventPage[cpu], 1); DPRINT_EXIT(VMBUS); } diff --git a/drivers/staging/hv/Hv.h b/drivers/staging/hv/Hv.h index fce4b5cdac30..41f5ebb86e17 100644 --- a/drivers/staging/hv/Hv.h +++ b/drivers/staging/hv/Hv.h @@ -41,11 +41,6 @@ enum { #define HV_PRESENT_BIT 0x80000000 -#define HV_XENLINUX_GUEST_ID_LO 0x00000000 -#define HV_XENLINUX_GUEST_ID_HI 0x0B00B135 -#define HV_XENLINUX_GUEST_ID (((u64)HV_XENLINUX_GUEST_ID_HI << 32) \ - | HV_XENLINUX_GUEST_ID_LO) - #define HV_LINUX_GUEST_ID_LO 0x00000000 #define HV_LINUX_GUEST_ID_HI 0xB16B00B5 #define HV_LINUX_GUEST_ID (((u64)HV_LINUX_GUEST_ID_HI << 32) | \ @@ -102,8 +97,9 @@ struct hv_input_signal_event_buffer { }; struct hv_context { - /* XenLinux or native Linux. If XenLinux, the hypercall and synic pages - * has already been initialized */ + /* We only support running on top of Hyper-V + * So at this point this really can only contain the Hyper-V ID + */ u64 GuestId; void *HypercallPage; -- cgit v1.2.3 From 4408f5319b6c8784120e0784df315b87e8a5dfef Mon Sep 17 00:00:00 2001 From: "C. Bartlett" Date: Wed, 3 Feb 2010 15:34:27 +0000 Subject: Staging: hv: fix various coding style issues in RingBuffer.c This is a patch to the RingBuffer.c file that corrects various coding style warnings and errors found by checkpatch.pl [ The real solution here is to get rid of this file entirely, and use the kernel's internal ring buffer api, but until then, make these changes so as to make checkpatch.pl happy, and keep others from continuously sending this type of patch. - gkh] Signed-off-by: Craig Bartlett Cc: Bill Pemberton Cc: Nicolas Palix Cc: Hank Janssen Cc: Haiyang Zhang Signed-off-by: Greg Kroah-Hartman --- drivers/staging/hv/RingBuffer.c | 153 ++++++++++++++++++++++------------------ 1 file changed, 86 insertions(+), 67 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/hv/RingBuffer.c b/drivers/staging/hv/RingBuffer.c index f69ae33a91e3..80b8a2c7784f 100644 --- a/drivers/staging/hv/RingBuffer.c +++ b/drivers/staging/hv/RingBuffer.c @@ -48,7 +48,7 @@ Description: static inline void GetRingBufferAvailBytes(RING_BUFFER_INFO *rbi, u32 *read, u32 *write) { - u32 read_loc,write_loc; + u32 read_loc, write_loc; /* Capture the read/write indices before they changed */ read_loc = rbi->RingBuffer->ReadIndex; @@ -68,7 +68,7 @@ Description: --*/ static inline u32 -GetNextWriteLocation(RING_BUFFER_INFO* RingInfo) +GetNextWriteLocation(RING_BUFFER_INFO *RingInfo) { u32 next = RingInfo->RingBuffer->WriteIndex; @@ -87,7 +87,7 @@ Description: --*/ static inline void -SetNextWriteLocation(RING_BUFFER_INFO* RingInfo, u32 NextWriteLocation) +SetNextWriteLocation(RING_BUFFER_INFO *RingInfo, u32 NextWriteLocation) { RingInfo->RingBuffer->WriteIndex = NextWriteLocation; } @@ -102,7 +102,7 @@ Description: --*/ static inline u32 -GetNextReadLocation(RING_BUFFER_INFO* RingInfo) +GetNextReadLocation(RING_BUFFER_INFO *RingInfo) { u32 next = RingInfo->RingBuffer->ReadIndex; @@ -122,7 +122,7 @@ Description: --*/ static inline u32 -GetNextReadLocationWithOffset(RING_BUFFER_INFO* RingInfo, u32 Offset) +GetNextReadLocationWithOffset(RING_BUFFER_INFO *RingInfo, u32 Offset) { u32 next = RingInfo->RingBuffer->ReadIndex; @@ -143,7 +143,7 @@ Description: --*/ static inline void -SetNextReadLocation(RING_BUFFER_INFO* RingInfo, u32 NextReadLocation) +SetNextReadLocation(RING_BUFFER_INFO *RingInfo, u32 NextReadLocation) { RingInfo->RingBuffer->ReadIndex = NextReadLocation; } @@ -159,7 +159,7 @@ Description: --*/ static inline void * -GetRingBuffer(RING_BUFFER_INFO* RingInfo) +GetRingBuffer(RING_BUFFER_INFO *RingInfo) { return (void *)RingInfo->RingBuffer->Buffer; } @@ -175,7 +175,7 @@ Description: --*/ static inline u32 -GetRingBufferSize(RING_BUFFER_INFO* RingInfo) +GetRingBufferSize(RING_BUFFER_INFO *RingInfo) { return RingInfo->RingDataSize; } @@ -190,9 +190,10 @@ Description: --*/ static inline u64 -GetRingBufferIndices(RING_BUFFER_INFO* RingInfo) +GetRingBufferIndices(RING_BUFFER_INFO *RingInfo) { - return ((u64)RingInfo->RingBuffer->WriteIndex << 32) || RingInfo->RingBuffer->ReadIndex; + return ((u64)RingInfo->RingBuffer->WriteIndex << 32) + || RingInfo->RingBuffer->ReadIndex; } @@ -210,9 +211,14 @@ void DumpRingInfo(RING_BUFFER_INFO *RingInfo, char *Prefix) u32 bytesAvailToWrite; u32 bytesAvailToRead; - GetRingBufferAvailBytes(RingInfo, &bytesAvailToRead, &bytesAvailToWrite); + GetRingBufferAvailBytes(RingInfo, + &bytesAvailToRead, + &bytesAvailToWrite); - DPRINT(VMBUS, DEBUG_RING_LVL, "%s <>", + DPRINT(VMBUS, + DEBUG_RING_LVL, + "%s <>", Prefix, RingInfo, RingInfo->RingBuffer->Buffer, @@ -229,13 +235,13 @@ static u32 CopyToRingBuffer( RING_BUFFER_INFO *RingInfo, u32 StartWriteOffset, - void * Src, + void *Src, u32 SrcLen); static u32 CopyFromRingBuffer( RING_BUFFER_INFO *RingInfo, - void * Dest, + void *Dest, u32 DestLen, u32 StartReadOffset); @@ -256,15 +262,15 @@ void RingBufferGetDebugInfo(RING_BUFFER_INFO *RingInfo, u32 bytesAvailToWrite; u32 bytesAvailToRead; - if (RingInfo->RingBuffer) - { - GetRingBufferAvailBytes(RingInfo, &bytesAvailToRead, &bytesAvailToWrite); + if (RingInfo->RingBuffer) { + GetRingBufferAvailBytes(RingInfo, + &bytesAvailToRead, + &bytesAvailToWrite); DebugInfo->BytesAvailToRead = bytesAvailToRead; DebugInfo->BytesAvailToWrite = bytesAvailToWrite; DebugInfo->CurrentReadIndex = RingInfo->RingBuffer->ReadIndex; DebugInfo->CurrentWriteIndex = RingInfo->RingBuffer->WriteIndex; - DebugInfo->CurrentInterruptMask = RingInfo->RingBuffer->InterruptMask; } } @@ -299,7 +305,7 @@ int RingBufferInit(RING_BUFFER_INFO *RingInfo, void *Buffer, u32 BufferLen) memset(RingInfo, 0, sizeof(RING_BUFFER_INFO)); - RingInfo->RingBuffer = (RING_BUFFER*)Buffer; + RingInfo->RingBuffer = (RING_BUFFER *)Buffer; RingInfo->RingBuffer->ReadIndex = RingInfo->RingBuffer->WriteIndex = 0; RingInfo->RingSize = BufferLen; @@ -319,7 +325,7 @@ Description: Cleanup the ring buffer --*/ -void RingBufferCleanup(RING_BUFFER_INFO* RingInfo) +void RingBufferCleanup(RING_BUFFER_INFO *RingInfo) { } @@ -335,14 +341,14 @@ Description: int RingBufferWrite(RING_BUFFER_INFO *OutRingInfo, struct scatterlist *sglist, u32 sgcount) { - int i=0; + int i = 0; u32 byteAvailToWrite; u32 byteAvailToRead; - u32 totalBytesToWrite=0; + u32 totalBytesToWrite = 0; struct scatterlist *sg; volatile u32 nextWriteLocation; - u64 prevIndices=0; + u64 prevIndices = 0; unsigned long flags; DPRINT_ENTER(VMBUS); @@ -356,17 +362,23 @@ int RingBufferWrite(RING_BUFFER_INFO *OutRingInfo, spin_lock_irqsave(&OutRingInfo->ring_lock, flags); - GetRingBufferAvailBytes(OutRingInfo, &byteAvailToRead, &byteAvailToWrite); + GetRingBufferAvailBytes(OutRingInfo, + &byteAvailToRead, + &byteAvailToWrite); DPRINT_DBG(VMBUS, "Writing %u bytes...", totalBytesToWrite); /* DumpRingInfo(OutRingInfo, "BEFORE "); */ - /* If there is only room for the packet, assume it is full. Otherwise, the next time around, we think the ring buffer */ + /* If there is only room for the packet, assume it is full. */ + /* Otherwise, the next time around, we think the ring buffer */ /* is empty since the read index == write index */ - if (byteAvailToWrite <= totalBytesToWrite) - { - DPRINT_DBG(VMBUS, "No more space left on outbound ring buffer (needed %u, avail %u)", totalBytesToWrite, byteAvailToWrite); + if (byteAvailToWrite <= totalBytesToWrite) { + DPRINT_DBG(VMBUS, + "No more space left on outbound ring buffer " + "(needed %u, avail %u)", + totalBytesToWrite, + byteAvailToWrite); spin_unlock_irqrestore(&OutRingInfo->ring_lock, flags); @@ -423,17 +435,22 @@ int RingBufferPeek(RING_BUFFER_INFO *InRingInfo, void *Buffer, u32 BufferLen) { u32 bytesAvailToWrite; u32 bytesAvailToRead; - u32 nextReadLocation=0; + u32 nextReadLocation = 0; unsigned long flags; spin_lock_irqsave(&InRingInfo->ring_lock, flags); - GetRingBufferAvailBytes(InRingInfo, &bytesAvailToRead, &bytesAvailToWrite); + GetRingBufferAvailBytes(InRingInfo, + &bytesAvailToRead, + &bytesAvailToWrite); /* Make sure there is something to read */ - if (bytesAvailToRead < BufferLen ) - { - /* DPRINT_DBG(VMBUS, "got callback but not enough to read !!", bytesAvailToRead, BufferLen); */ + if (bytesAvailToRead < BufferLen) { + /* DPRINT_DBG(VMBUS, + "got callback but not enough to read " + "!!", + bytesAvailToRead, + BufferLen); */ spin_unlock_irqrestore(&InRingInfo->ring_lock, flags); @@ -444,9 +461,9 @@ int RingBufferPeek(RING_BUFFER_INFO *InRingInfo, void *Buffer, u32 BufferLen) nextReadLocation = GetNextReadLocation(InRingInfo); nextReadLocation = CopyFromRingBuffer(InRingInfo, - Buffer, - BufferLen, - nextReadLocation); + Buffer, + BufferLen, + nextReadLocation); spin_unlock_irqrestore(&InRingInfo->ring_lock, flags); @@ -468,24 +485,29 @@ int RingBufferRead(RING_BUFFER_INFO *InRingInfo, void *Buffer, { u32 bytesAvailToWrite; u32 bytesAvailToRead; - u32 nextReadLocation=0; - u64 prevIndices=0; + u32 nextReadLocation = 0; + u64 prevIndices = 0; unsigned long flags; ASSERT(BufferLen > 0); spin_lock_irqsave(&InRingInfo->ring_lock, flags); - GetRingBufferAvailBytes(InRingInfo, &bytesAvailToRead, &bytesAvailToWrite); + GetRingBufferAvailBytes(InRingInfo, + &bytesAvailToRead, + &bytesAvailToWrite); DPRINT_DBG(VMBUS, "Reading %u bytes...", BufferLen); /* DumpRingInfo(InRingInfo, "BEFORE "); */ /* Make sure there is something to read */ - if (bytesAvailToRead < BufferLen ) - { - DPRINT_DBG(VMBUS, "got callback but not enough to read !!", bytesAvailToRead, BufferLen); + if (bytesAvailToRead < BufferLen) { + DPRINT_DBG(VMBUS, + "got callback but not enough to read " + "!!", + bytesAvailToRead, + BufferLen); spin_unlock_irqrestore(&InRingInfo->ring_lock, flags); @@ -495,17 +517,18 @@ int RingBufferRead(RING_BUFFER_INFO *InRingInfo, void *Buffer, nextReadLocation = GetNextReadLocationWithOffset(InRingInfo, Offset); nextReadLocation = CopyFromRingBuffer(InRingInfo, - Buffer, - BufferLen, - nextReadLocation); + Buffer, + BufferLen, + nextReadLocation); nextReadLocation = CopyFromRingBuffer(InRingInfo, - &prevIndices, - sizeof(u64), - nextReadLocation); + &prevIndices, + sizeof(u64), + nextReadLocation); /* Make sure all reads are done before we update the read index since */ - /* the writer may start writing to the read area once the read index is updated */ + /* the writer may start writing to the read area once the read index */ + /*is updated */ mb(); /* Update the read index */ @@ -533,25 +556,22 @@ static u32 CopyToRingBuffer( RING_BUFFER_INFO *RingInfo, u32 StartWriteOffset, - void * Src, + void *Src, u32 SrcLen) { - void * ringBuffer=GetRingBuffer(RingInfo); - u32 ringBufferSize=GetRingBufferSize(RingInfo); + void *ringBuffer = GetRingBuffer(RingInfo); + u32 ringBufferSize = GetRingBufferSize(RingInfo); u32 fragLen; - if (SrcLen > ringBufferSize - StartWriteOffset) /* wrap-around detected! */ - { + /* wrap-around detected! */ + if (SrcLen > ringBufferSize - StartWriteOffset) { DPRINT_DBG(VMBUS, "wrap-around detected!"); fragLen = ringBufferSize - StartWriteOffset; memcpy(ringBuffer + StartWriteOffset, Src, fragLen); memcpy(ringBuffer, Src + fragLen, SrcLen - fragLen); - } - else - { + } else memcpy(ringBuffer + StartWriteOffset, Src, SrcLen); - } StartWriteOffset += SrcLen; StartWriteOffset %= ringBufferSize; @@ -573,28 +593,27 @@ Description: static u32 CopyFromRingBuffer( RING_BUFFER_INFO *RingInfo, - void * Dest, + void *Dest, u32 DestLen, u32 StartReadOffset) { - void * ringBuffer=GetRingBuffer(RingInfo); - u32 ringBufferSize=GetRingBufferSize(RingInfo); + void *ringBuffer = GetRingBuffer(RingInfo); + u32 ringBufferSize = GetRingBufferSize(RingInfo); u32 fragLen; - if (DestLen > ringBufferSize - StartReadOffset) /* wrap-around detected at the src */ - { + /* wrap-around detected at the src */ + if (DestLen > ringBufferSize - StartReadOffset) { DPRINT_DBG(VMBUS, "src wrap-around detected!"); fragLen = ringBufferSize - StartReadOffset; memcpy(Dest, ringBuffer + StartReadOffset, fragLen); memcpy(Dest + fragLen, ringBuffer, DestLen - fragLen); - } - else - { + } else + memcpy(Dest, ringBuffer + StartReadOffset, DestLen); - } + StartReadOffset += DestLen; StartReadOffset %= ringBufferSize; -- cgit v1.2.3 From 26c14cc119204adc218259251919c5198d07dafe Mon Sep 17 00:00:00 2001 From: Hank Janssen Date: Thu, 11 Feb 2010 23:02:42 +0000 Subject: Staging: hv: Add proper versioning to HV drivers Provide proper versioning information for all HV drivers. With removal of build time/date/and Minor number as requested by Greg KH Signed-off-by: Hank Janssen Signed-off-by: Haiyang Zhang Signed-off-by: Greg Kroah-Hartman --- drivers/staging/hv/VersionInfo.h | 22 +++++++++++++++++++--- drivers/staging/hv/Vmbus.c | 6 ++---- drivers/staging/hv/blkvsc_drv.c | 2 ++ drivers/staging/hv/netvsc_drv.c | 5 +++-- drivers/staging/hv/storvsc_drv.c | 2 ++ drivers/staging/hv/vmbus_drv.c | 2 ++ 6 files changed, 30 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/hv/VersionInfo.h b/drivers/staging/hv/VersionInfo.h index 9c3641d99ed8..10d7b19a485f 100644 --- a/drivers/staging/hv/VersionInfo.h +++ b/drivers/staging/hv/VersionInfo.h @@ -24,8 +24,24 @@ #ifndef __HV_VERSION_INFO #define __HV_VERSION_INFO -static const char VersionDate[] = __DATE__; -static const char VersionTime[] = __TIME__; -static const char VersionDesc[] = "Version 2.0"; +/* + * We use the same version numbering for all Hyper-V modules. + * + * Definition of versioning is as follows; + * + * Major Number Changes for these scenarios; + * 1. When a new version of Windows Hyper-V + * is released. + * 2. A Major change has occurred in the + * Linux IC's. + * (For example the merge for the first time + * into the kernel) Every time the Major Number + * changes, the Revision number is reset to 0. + * Minor Number Changes when new functionality is added + * to the Linux IC's that is not a bug fix. + * + */ +#define HV_DRV_VERSION "3.0" + #endif diff --git a/drivers/staging/hv/Vmbus.c b/drivers/staging/hv/Vmbus.c index 35a023e9f9d1..3d0a240ed664 100644 --- a/drivers/staging/hv/Vmbus.c +++ b/drivers/staging/hv/Vmbus.c @@ -273,10 +273,8 @@ int VmbusInitialize(struct hv_driver *drv) DPRINT_ENTER(VMBUS); - DPRINT_INFO(VMBUS, "+++++++ Build Date=%s %s +++++++", - VersionDate, VersionTime); - DPRINT_INFO(VMBUS, "+++++++ Build Description=%s +++++++", - VersionDesc); + DPRINT_INFO(VMBUS, "+++++++ HV Driver version = %s +++++++", + HV_DRV_VERSION); DPRINT_INFO(VMBUS, "+++++++ Vmbus supported version = %d +++++++", VMBUS_REVISION_NUMBER); DPRINT_INFO(VMBUS, "+++++++ Vmbus using SINT %d +++++++", diff --git a/drivers/staging/hv/blkvsc_drv.c b/drivers/staging/hv/blkvsc_drv.c index 62b282844a53..635692d59954 100644 --- a/drivers/staging/hv/blkvsc_drv.c +++ b/drivers/staging/hv/blkvsc_drv.c @@ -31,6 +31,7 @@ #include #include "osd.h" #include "logging.h" +#include "VersionInfo.h" #include "vmbus.h" #include "StorVscApi.h" @@ -1507,6 +1508,7 @@ static void __exit blkvsc_exit(void) } MODULE_LICENSE("GPL"); +MODULE_VERSION(HV_DRV_VERSION); module_param(blkvsc_ringbuffer_size, int, S_IRUGO); module_init(blkvsc_init); module_exit(blkvsc_exit); diff --git a/drivers/staging/hv/netvsc_drv.c b/drivers/staging/hv/netvsc_drv.c index 3234a7c4a429..0a780671cefe 100644 --- a/drivers/staging/hv/netvsc_drv.c +++ b/drivers/staging/hv/netvsc_drv.c @@ -35,11 +35,10 @@ #include #include "osd.h" #include "logging.h" +#include "VersionInfo.h" #include "vmbus.h" #include "NetVscApi.h" -MODULE_LICENSE("GPL"); - struct net_device_context { /* point back to our device context */ struct device_context *device_ctx; @@ -603,6 +602,8 @@ static void __exit netvsc_exit(void) DPRINT_EXIT(NETVSC_DRV); } +MODULE_LICENSE("GPL"); +MODULE_VERSION(HV_DRV_VERSION); module_param(netvsc_ringbuffer_size, int, S_IRUGO); module_init(netvsc_init); diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c index 12f8f3f64c61..a10fa0ea98e5 100644 --- a/drivers/staging/hv/storvsc_drv.c +++ b/drivers/staging/hv/storvsc_drv.c @@ -32,6 +32,7 @@ #include #include "osd.h" #include "logging.h" +#include "VersionInfo.h" #include "vmbus.h" #include "StorVscApi.h" @@ -990,6 +991,7 @@ static void __exit storvsc_exit(void) } MODULE_LICENSE("GPL"); +MODULE_VERSION(HV_DRV_VERSION); module_param(storvsc_ringbuffer_size, int, S_IRUGO); module_init(storvsc_init); module_exit(storvsc_exit); diff --git a/drivers/staging/hv/vmbus_drv.c b/drivers/staging/hv/vmbus_drv.c index 894eecfc63ca..92d70cd881ba 100644 --- a/drivers/staging/hv/vmbus_drv.c +++ b/drivers/staging/hv/vmbus_drv.c @@ -24,6 +24,7 @@ #include #include #include +#include "VersionInfo.h" #include "osd.h" #include "logging.h" #include "vmbus.h" @@ -974,6 +975,7 @@ static void __exit vmbus_exit(void) } MODULE_LICENSE("GPL"); +MODULE_VERSION(HV_DRV_VERSION); module_param(vmbus_irq, int, S_IRUGO); module_param(vmbus_loglevel, int, S_IRUGO); -- cgit v1.2.3 From f916a34dc066c13ff2c8986657634cef06c07719 Mon Sep 17 00:00:00 2001 From: Haiyang Zhang Date: Wed, 17 Feb 2010 20:58:47 +0000 Subject: Staging: hv: Rename struct device_context and re-arrange the fields inside Rename struct device_context and re-arrange the fields inside. Rename struct device_context to struct vm_device, and move struct device field to the end according to Document/driver-model standard. Signed-off-by: Hank Janssen Signed-off-by: Haiyang Zhang Signed-off-by: Greg Kroah-Hartman --- drivers/staging/hv/blkvsc_drv.c | 8 ++++---- drivers/staging/hv/netvsc_drv.c | 10 +++++----- drivers/staging/hv/storvsc_drv.c | 10 +++++----- drivers/staging/hv/vmbus.h | 12 ++++++------ drivers/staging/hv/vmbus_drv.c | 36 ++++++++++++++++++------------------ 5 files changed, 38 insertions(+), 38 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/hv/blkvsc_drv.c b/drivers/staging/hv/blkvsc_drv.c index 635692d59954..1d1a46f524d2 100644 --- a/drivers/staging/hv/blkvsc_drv.c +++ b/drivers/staging/hv/blkvsc_drv.c @@ -93,7 +93,7 @@ struct blkvsc_request { /* Per device structure */ struct block_device_context { /* point back to our device context */ - struct device_context *device_ctx; + struct vm_device *device_ctx; struct kmem_cache *request_pool; spinlock_t lock; struct gendisk *gd; @@ -255,7 +255,7 @@ static int blkvsc_probe(struct device *device) (struct blkvsc_driver_context *)driver_ctx; struct storvsc_driver_object *storvsc_drv_obj = &blkvsc_drv_ctx->drv_obj; - struct device_context *device_ctx = device_to_device_context(device); + struct vm_device *device_ctx = device_to_vm_device(device); struct hv_device *device_obj = &device_ctx->device_obj; struct block_device_context *blkdev = NULL; @@ -746,7 +746,7 @@ static int blkvsc_remove(struct device *device) (struct blkvsc_driver_context *)driver_ctx; struct storvsc_driver_object *storvsc_drv_obj = &blkvsc_drv_ctx->drv_obj; - struct device_context *device_ctx = device_to_device_context(device); + struct vm_device *device_ctx = device_to_vm_device(device); struct hv_device *device_obj = &device_ctx->device_obj; struct block_device_context *blkdev = dev_get_drvdata(device); unsigned long flags; @@ -866,7 +866,7 @@ static int blkvsc_submit_request(struct blkvsc_request *blkvsc_req, void (*request_completion)(struct hv_storvsc_request *)) { struct block_device_context *blkdev = blkvsc_req->dev; - struct device_context *device_ctx = blkdev->device_ctx; + struct vm_device *device_ctx = blkdev->device_ctx; struct driver_context *driver_ctx = driver_to_driver_context(device_ctx->device.driver); struct blkvsc_driver_context *blkvsc_drv_ctx = diff --git a/drivers/staging/hv/netvsc_drv.c b/drivers/staging/hv/netvsc_drv.c index 0a780671cefe..1af3dcbafd65 100644 --- a/drivers/staging/hv/netvsc_drv.c +++ b/drivers/staging/hv/netvsc_drv.c @@ -41,7 +41,7 @@ struct net_device_context { /* point back to our device context */ - struct device_context *device_ctx; + struct vm_device *device_ctx; struct net_device_stats stats; }; @@ -271,7 +271,7 @@ retry_send: static void netvsc_linkstatus_callback(struct hv_device *device_obj, unsigned int status) { - struct device_context *device_ctx = to_device_context(device_obj); + struct vm_device *device_ctx = to_vm_device(device_obj); struct net_device *net = dev_get_drvdata(&device_ctx->device); DPRINT_ENTER(NETVSC_DRV); @@ -298,7 +298,7 @@ static void netvsc_linkstatus_callback(struct hv_device *device_obj, static int netvsc_recv_callback(struct hv_device *device_obj, struct hv_netvsc_packet *packet) { - struct device_context *device_ctx = to_device_context(device_obj); + struct vm_device *device_ctx = to_vm_device(device_obj); struct net_device *net = dev_get_drvdata(&device_ctx->device); struct net_device_context *net_device_ctx; struct sk_buff *skb; @@ -390,7 +390,7 @@ static int netvsc_probe(struct device *device) struct netvsc_driver_context *net_drv_ctx = (struct netvsc_driver_context *)driver_ctx; struct netvsc_driver *net_drv_obj = &net_drv_ctx->drv_obj; - struct device_context *device_ctx = device_to_device_context(device); + struct vm_device *device_ctx = device_to_vm_device(device); struct hv_device *device_obj = &device_ctx->device_obj; struct net_device *net = NULL; struct net_device_context *net_device_ctx; @@ -462,7 +462,7 @@ static int netvsc_remove(struct device *device) struct netvsc_driver_context *net_drv_ctx = (struct netvsc_driver_context *)driver_ctx; struct netvsc_driver *net_drv_obj = &net_drv_ctx->drv_obj; - struct device_context *device_ctx = device_to_device_context(device); + struct vm_device *device_ctx = device_to_vm_device(device); struct net_device *net = dev_get_drvdata(&device_ctx->device); struct hv_device *device_obj = &device_ctx->device_obj; int ret; diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c index a10fa0ea98e5..3988f4bec1ce 100644 --- a/drivers/staging/hv/storvsc_drv.c +++ b/drivers/staging/hv/storvsc_drv.c @@ -41,7 +41,7 @@ struct host_device_context { /* must be 1st field * FIXME this is a bug */ /* point back to our device context */ - struct device_context *device_ctx; + struct vm_device *device_ctx; struct kmem_cache *request_pool; unsigned int port; unsigned char path; @@ -234,7 +234,7 @@ static int storvsc_probe(struct device *device) (struct storvsc_driver_context *)driver_ctx; struct storvsc_driver_object *storvsc_drv_obj = &storvsc_drv_ctx->drv_obj; - struct device_context *device_ctx = device_to_device_context(device); + struct vm_device *device_ctx = device_to_vm_device(device); struct hv_device *device_obj = &device_ctx->device_obj; struct Scsi_Host *host; struct host_device_context *host_device_ctx; @@ -330,7 +330,7 @@ static int storvsc_remove(struct device *device) (struct storvsc_driver_context *)driver_ctx; struct storvsc_driver_object *storvsc_drv_obj = &storvsc_drv_ctx->drv_obj; - struct device_context *device_ctx = device_to_device_context(device); + struct vm_device *device_ctx = device_to_vm_device(device); struct hv_device *device_obj = &device_ctx->device_obj; struct Scsi_Host *host = dev_get_drvdata(device); struct host_device_context *host_device_ctx = @@ -631,7 +631,7 @@ static int storvsc_queuecommand(struct scsi_cmnd *scmnd, int ret; struct host_device_context *host_device_ctx = (struct host_device_context *)scmnd->device->host->hostdata; - struct device_context *device_ctx = host_device_ctx->device_ctx; + struct vm_device *device_ctx = host_device_ctx->device_ctx; struct driver_context *driver_ctx = driver_to_driver_context(device_ctx->device.driver); struct storvsc_driver_context *storvsc_drv_ctx = @@ -870,7 +870,7 @@ static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd) int ret; struct host_device_context *host_device_ctx = (struct host_device_context *)scmnd->device->host->hostdata; - struct device_context *device_ctx = host_device_ctx->device_ctx; + struct vm_device *device_ctx = host_device_ctx->device_ctx; DPRINT_ENTER(STORVSC_DRV); diff --git a/drivers/staging/hv/vmbus.h b/drivers/staging/hv/vmbus.h index ae0a896eb392..6404b8424bef 100644 --- a/drivers/staging/hv/vmbus.h +++ b/drivers/staging/hv/vmbus.h @@ -43,23 +43,23 @@ struct driver_context { void (*shutdown)(struct device *); }; -struct device_context { +struct vm_device { struct work_struct probe_failed_work_item; struct hv_guid class_id; struct hv_guid device_id; int probe_error; - struct device device; struct hv_device device_obj; + struct device device; }; -static inline struct device_context *to_device_context(struct hv_device *d) +static inline struct vm_device *to_vm_device(struct hv_device *d) { - return container_of(d, struct device_context, device_obj); + return container_of(d, struct vm_device, device_obj); } -static inline struct device_context *device_to_device_context(struct device *d) +static inline struct vm_device *device_to_vm_device(struct device *d) { - return container_of(d, struct device_context, device); + return container_of(d, struct vm_device, device); } static inline struct driver_context *driver_to_driver_context(struct device_driver *d) diff --git a/drivers/staging/hv/vmbus_drv.c b/drivers/staging/hv/vmbus_drv.c index 92d70cd881ba..de8729d6820c 100644 --- a/drivers/staging/hv/vmbus_drv.c +++ b/drivers/staging/hv/vmbus_drv.c @@ -48,7 +48,7 @@ struct vmbus_driver_context { struct tasklet_struct event_dpc; /* The bus root device */ - struct device_context device_ctx; + struct vm_device device_ctx; }; static int vmbus_match(struct device *device, struct device_driver *driver); @@ -136,7 +136,7 @@ static ssize_t vmbus_show_device_attr(struct device *dev, struct device_attribute *dev_attr, char *buf) { - struct device_context *device_ctx = device_to_device_context(dev); + struct vm_device *device_ctx = device_to_vm_device(dev); struct hv_device_info device_info; memset(&device_info, 0, sizeof(struct hv_device_info)); @@ -246,7 +246,7 @@ static int vmbus_bus_init(int (*drv_init)(struct hv_driver *drv)) { struct vmbus_driver_context *vmbus_drv_ctx = &g_vmbus_drv; struct vmbus_driver *vmbus_drv_obj = &g_vmbus_drv.drv_obj; - struct device_context *dev_ctx = &g_vmbus_drv.device_ctx; + struct vm_device *dev_ctx = &g_vmbus_drv.device_ctx; int ret; unsigned int vector; @@ -308,7 +308,7 @@ static int vmbus_bus_init(int (*drv_init)(struct hv_driver *drv)) DPRINT_INFO(VMBUS_DRV, "irq 0x%x vector 0x%x", vmbus_irq, vector); /* Call to bus driver to add the root device */ - memset(dev_ctx, 0, sizeof(struct device_context)); + memset(dev_ctx, 0, sizeof(struct vm_device)); ret = vmbus_drv_obj->Base.OnDeviceAdd(&dev_ctx->device_obj, &vector); if (ret != 0) { @@ -369,7 +369,7 @@ static void vmbus_bus_exit(void) struct vmbus_driver *vmbus_drv_obj = &g_vmbus_drv.drv_obj; struct vmbus_driver_context *vmbus_drv_ctx = &g_vmbus_drv; - struct device_context *dev_ctx = &g_vmbus_drv.device_ctx; + struct vm_device *dev_ctx = &g_vmbus_drv.device_ctx; DPRINT_ENTER(VMBUS_DRV); @@ -472,13 +472,13 @@ static struct hv_device *vmbus_child_device_create(struct hv_guid *type, struct hv_guid *instance, void *context) { - struct device_context *child_device_ctx; + struct vm_device *child_device_ctx; struct hv_device *child_device_obj; DPRINT_ENTER(VMBUS_DRV); /* Allocate the new child device */ - child_device_ctx = kzalloc(sizeof(struct device_context), GFP_KERNEL); + child_device_ctx = kzalloc(sizeof(struct vm_device), GFP_KERNEL); if (!child_device_ctx) { DPRINT_ERR(VMBUS_DRV, "unable to allocate device_context for child device"); @@ -527,10 +527,10 @@ static int vmbus_child_device_register(struct hv_device *root_device_obj, struct hv_device *child_device_obj) { int ret = 0; - struct device_context *root_device_ctx = - to_device_context(root_device_obj); - struct device_context *child_device_ctx = - to_device_context(child_device_obj); + struct vm_device *root_device_ctx = + to_vm_device(root_device_obj); + struct vm_device *child_device_ctx = + to_vm_device(child_device_obj); static atomic_t device_num = ATOMIC_INIT(0); DPRINT_ENTER(VMBUS_DRV); @@ -573,7 +573,7 @@ static int vmbus_child_device_register(struct hv_device *root_device_obj, */ static void vmbus_child_device_unregister(struct hv_device *device_obj) { - struct device_context *device_ctx = to_device_context(device_obj); + struct vm_device *device_ctx = to_vm_device(device_obj); DPRINT_ENTER(VMBUS_DRV); @@ -611,7 +611,7 @@ static void vmbus_child_device_destroy(struct hv_device *device_obj) */ static int vmbus_uevent(struct device *device, struct kobj_uevent_env *env) { - struct device_context *device_ctx = device_to_device_context(device); + struct vm_device *device_ctx = device_to_vm_device(device); int ret; DPRINT_ENTER(VMBUS_DRV); @@ -688,7 +688,7 @@ static int vmbus_match(struct device *device, struct device_driver *driver) { int match = 0; struct driver_context *driver_ctx = driver_to_driver_context(driver); - struct device_context *device_ctx = device_to_device_context(device); + struct vm_device *device_ctx = device_to_vm_device(device); DPRINT_ENTER(VMBUS_DRV); @@ -725,7 +725,7 @@ static int vmbus_match(struct device *device, struct device_driver *driver) */ static void vmbus_probe_failed_cb(struct work_struct *context) { - struct device_context *device_ctx = (struct device_context *)context; + struct vm_device *device_ctx = (struct vm_device *)context; DPRINT_ENTER(VMBUS_DRV); @@ -747,8 +747,8 @@ static int vmbus_probe(struct device *child_device) int ret = 0; struct driver_context *driver_ctx = driver_to_driver_context(child_device->driver); - struct device_context *device_ctx = - device_to_device_context(child_device); + struct vm_device *device_ctx = + device_to_vm_device(child_device); DPRINT_ENTER(VMBUS_DRV); @@ -872,7 +872,7 @@ static void vmbus_bus_release(struct device *device) */ static void vmbus_device_release(struct device *device) { - struct device_context *device_ctx = device_to_device_context(device); + struct vm_device *device_ctx = device_to_vm_device(device); DPRINT_ENTER(VMBUS_DRV); -- cgit v1.2.3 From 0fa37b1ee936811c8aa8fcb72d189d02cf1575b9 Mon Sep 17 00:00:00 2001 From: Chris Nicholson Date: Sat, 20 Feb 2010 20:36:23 +0000 Subject: Staging: hv: fix brace coding style issue in Channel.c This is a patch to the Channel.c file that fixes up a brace warning found by checkpatch.pl Signed-off-by: Chris Nicholson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/hv/Channel.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/hv/Channel.c b/drivers/staging/hv/Channel.c index 746370e82115..d46eb145484f 100644 --- a/drivers/staging/hv/Channel.c +++ b/drivers/staging/hv/Channel.c @@ -991,9 +991,8 @@ void VmbusChannelOnTimer(unsigned long data) { struct vmbus_channel *channel = (struct vmbus_channel *)data; - if (channel->OnChannelCallback) { + if (channel->OnChannelCallback) channel->OnChannelCallback(channel->ChannelCallbackContext); - } } /** -- cgit v1.2.3 From 9a775dbd4e8c87b7d35549183145321c7205404e Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 25 Feb 2010 16:42:10 -0800 Subject: Staging: hv: add a pci device table This allows the HV core to be properly found and autoloaded by the system tools. It uses the Microsoft virtual VGA device to trigger this. Cc: Haiyang Zhang Cc: Hank Janssen Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/staging/hv/vmbus_drv.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/hv/vmbus_drv.c b/drivers/staging/hv/vmbus_drv.c index de8729d6820c..186cbe6983a9 100644 --- a/drivers/staging/hv/vmbus_drv.c +++ b/drivers/staging/hv/vmbus_drv.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "VersionInfo.h" #include "osd.h" #include "logging.h" @@ -974,6 +975,22 @@ static void __exit vmbus_exit(void) return; } +/* + * We use a PCI table to determine if we should autoload this driver This is + * needed by distro tools to determine if the hyperv drivers should be + * installed and/or configured. We don't do anything else with the table, but + * it needs to be present. + * + * We might consider triggering off of DMI table info as well, as that does + * decribe the virtual machine being run on, but not all configuration tools + * seem to be able to handle DMI device ids properly. + */ +const static struct pci_device_id microsoft_hv_pci_table[] = { + { PCI_DEVICE(0x1414, 0x5353) }, /* VGA compatible controller */ + { 0 } +}; +MODULE_DEVICE_TABLE(pci, microsoft_hv_pci_table); + MODULE_LICENSE("GPL"); MODULE_VERSION(HV_DRV_VERSION); module_param(vmbus_irq, int, S_IRUGO); -- cgit v1.2.3 From c22090facd354749cfe99a46e903449c7ac07788 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 25 Feb 2010 16:43:15 -0800 Subject: Staging: hv: match on DMI values to know if we should run. The HV core mucks around with specific irqs and other low-level stuff and takes forever to determine that it really shouldn't be running on a machine. So instead, trigger off of the DMI system information and error out much sooner. This also allows the module loading tools to recognize that this code should be loaded on this type of system. Cc: Haiyang Zhang Cc: Hank Janssen Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/staging/hv/vmbus_drv.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/hv/vmbus_drv.c b/drivers/staging/hv/vmbus_drv.c index 186cbe6983a9..2c906195b9c8 100644 --- a/drivers/staging/hv/vmbus_drv.c +++ b/drivers/staging/hv/vmbus_drv.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "VersionInfo.h" #include "osd.h" #include "logging.h" @@ -948,6 +949,19 @@ static irqreturn_t vmbus_isr(int irq, void *dev_id) } } +static struct dmi_system_id __initdata microsoft_hv_dmi_table[] = { + { + .ident = "Hyper-V", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"), + DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"), + DMI_MATCH(DMI_BOARD_NAME, "Virtual Machine"), + }, + }, + { }, +}; +MODULE_DEVICE_TABLE(dmi, microsoft_hv_dmi_table); + static int __init vmbus_init(void) { int ret = 0; @@ -959,6 +973,9 @@ static int __init vmbus_init(void) vmbus_loglevel, HIWORD(vmbus_loglevel), LOWORD(vmbus_loglevel)); /* Todo: it is used for loglevel, to be ported to new kernel. */ + if (!dmi_check_system(microsoft_hv_dmi_table)) + return -ENODEV; + ret = vmbus_bus_init(VmbusInitialize); DPRINT_EXIT(VMBUS_DRV); @@ -980,10 +997,6 @@ static void __exit vmbus_exit(void) * needed by distro tools to determine if the hyperv drivers should be * installed and/or configured. We don't do anything else with the table, but * it needs to be present. - * - * We might consider triggering off of DMI table info as well, as that does - * decribe the virtual machine being run on, but not all configuration tools - * seem to be able to handle DMI device ids properly. */ const static struct pci_device_id microsoft_hv_pci_table[] = { { PCI_DEVICE(0x1414, 0x5353) }, /* VGA compatible controller */ -- cgit v1.2.3 From 6910dadf3f11254bc0af79f578c7228b4e1334ac Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 24 Dec 2009 22:41:13 +1100 Subject: Staging: DT3155: Use pci_get_device() The use of pci_find_device() is deprecated. Signed-off-by: Simon Horman Cc: Scott Smedley Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dt3155/dt3155_drv.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dt3155/dt3155_drv.c b/drivers/staging/dt3155/dt3155_drv.c index 3efdeb9953ff..950956c08eda 100644 --- a/drivers/staging/dt3155/dt3155_drv.c +++ b/drivers/staging/dt3155/dt3155_drv.c @@ -963,7 +963,7 @@ static int find_PCI (void) unsigned long base; unsigned char irq; - while ((pci_dev = pci_find_device + while ((pci_dev = pci_get_device (DT3155_VENDORID, DT3155_DEVICEID, pci_dev)) != NULL) { pci_index ++; @@ -983,7 +983,7 @@ static int find_PCI (void) "for %d devices\n" "DT3155: Please change MAXBOARDS in dt3155.h\n", pci_index, MAXBOARDS); - return DT_3155_FAILURE; + goto err; } /* Now, just go out and make sure that this/these device(s) is/are @@ -992,7 +992,7 @@ static int find_PCI (void) (u_int *) &base))) { printk("DT3155: Was not able to find device \n"); - return DT_3155_FAILURE; + goto err; } DT_3155_DEBUG_MSG("DT3155: Base address 0 for device is %lx \n", base); @@ -1007,13 +1007,13 @@ static int find_PCI (void) if ( !dt3155_lbase[pci_index-1] ) { printk("DT3155: Unable to remap control registers\n"); - return DT_3155_FAILURE; + goto err; } if ( (error = pci_read_config_byte( pci_dev, PCI_INTERRUPT_LINE, &irq)) ) { printk("DT3155: Was not able to find device \n"); - return DT_3155_FAILURE; + goto err; } DT_3155_DEBUG_MSG("DT3155: IRQ is %d \n",irq); @@ -1029,6 +1029,10 @@ static int find_PCI (void) ndevices = pci_index; return DT_3155_SUCCESS; + +err: + pci_dev_put(pci_dev); + return DT_3155_FAILURE; } u_long allocatorAddr = 0; -- cgit v1.2.3 From c33c2065fc4d424e23547b58900ded5eb4444e9d Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 23 Dec 2009 19:54:50 +1100 Subject: Staging: rt2870: rtusb_probe() should be in section __devinit $ make CONFIG_DEBUG_SECTION_MISMATCH=y WARNING: drivers/staging/rt2870/rt2870sta.o(.text+0x2f4c5): Section mismatch in reference from the function rtusb_probe() to the function .devinit.text:rt2870_probe() The function rtusb_probe() references the function __devinit rt2870_probe(). This is often because rtusb_probe lacks a __devinit annotation or the annotation of rt2870_probe is wrong. Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rt2860/usb_main_dev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/rt2860/usb_main_dev.c b/drivers/staging/rt2860/usb_main_dev.c index 925a236e1044..1e6e8a3b61ac 100644 --- a/drivers/staging/rt2860/usb_main_dev.c +++ b/drivers/staging/rt2860/usb_main_dev.c @@ -296,7 +296,7 @@ static BOOLEAN USBDevConfigInit(IN struct usb_device *dev, } -static int rtusb_probe(struct usb_interface *intf, +static int __devinit rtusb_probe(struct usb_interface *intf, const struct usb_device_id *id) { struct rt_rtmp_adapter *pAd; -- cgit v1.2.3 From db15438cd5be7380cdf27c8adb8fc71a72da0210 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 23 Dec 2009 19:54:51 +1100 Subject: Staging: rt2870: Remove unnecessary forward declarations Remove unnecessary forward declaration of rtusb_probe() and rtusb_disconnect() Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rt2860/usb_main_dev.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rt2860/usb_main_dev.c b/drivers/staging/rt2860/usb_main_dev.c index 1e6e8a3b61ac..1873a79bb033 100644 --- a/drivers/staging/rt2860/usb_main_dev.c +++ b/drivers/staging/rt2860/usb_main_dev.c @@ -216,10 +216,6 @@ static int rt2870_suspend(struct usb_interface *intf, pm_message_t state); static int rt2870_resume(struct usb_interface *intf); #endif /* CONFIG_PM // */ -static int rtusb_probe(struct usb_interface *intf, - const struct usb_device_id *id); -static void rtusb_disconnect(struct usb_interface *intf); - static BOOLEAN USBDevConfigInit(IN struct usb_device *dev, IN struct usb_interface *intf, struct rt_rtmp_adapter *pAd) -- cgit v1.2.3 From 9bfafe825d0af5f4cbb2aaaecad0cf9a459cf6b1 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 23 Dec 2009 19:54:52 +1100 Subject: Staging: rtl8192e: print the elements of tx_pn and rx_pn not the arrays themselves Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- .../staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c index 70159cf28bce..d5fe94d74b52 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c @@ -475,12 +475,19 @@ static int ieee80211_ccmp_get_key(void *key, int len, u8 *seq, void *priv) static char * ieee80211_ccmp_print_stats(char *p, void *priv) { struct ieee80211_ccmp_data *ccmp = priv; - p += sprintf(p, "key[%d] alg=CCMP key_set=%d " - "tx_pn=%02x%02x%02x%02x%02x%02x " - "rx_pn=%02x%02x%02x%02x%02x%02x " - "format_errors=%d replays=%d decrypt_errors=%d\n", - ccmp->key_idx, ccmp->key_set, - ccmp->tx_pn, ccmp->rx_pn, + int i; + + p += sprintf(p, "key[%d] alg=CCMP key_set=%d tx_pn=", + ccmp->key_idx, ccmp->key_set); + + for (i = 0; i < ARRAY_SIZE(ccmp->tx_pn); i++) + p += sprintf(p, "%02x", ccmp->tx_pn[i]); + + sprintf(p, " rx_pn="); + for (i = 0; i < ARRAY_SIZE(ccmp->rx_pn); i++) + p += sprintf(p, "%02x", ccmp->tx_pn[i]); + + p += sprintf(p, " format_errors=%d replays=%d decrypt_errors=%d\n", ccmp->dot11RSNAStatsCCMPFormatErrors, ccmp->dot11RSNAStatsCCMPReplays, ccmp->dot11RSNAStatsCCMPDecryptErrors); -- cgit v1.2.3 From 27b93f80e47a49a0584a4c8fb58bc44f9e026256 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 23 Dec 2009 19:54:53 +1100 Subject: Staging: rtl8192e: remove some functions from the __exit section ieee80211_crypto_tkip_exit(), ieee80211_crypto_deinit() and ieee80211_crypto_ccmp_exit() are called by ieee80211_rtl_init() which are in section __init, so they can't be in section __exit. Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/ieee80211/ieee80211_crypt.c | 2 +- drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c | 2 +- drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_tkip.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt.c index b1c54932da3e..b3c9bf4b4ea6 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt.c @@ -225,7 +225,7 @@ out: } -void __exit ieee80211_crypto_deinit(void) +void ieee80211_crypto_deinit(void) { struct list_head *ptr, *n; diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c index d5fe94d74b52..1776f7e69bfe 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_ccmp.c @@ -524,7 +524,7 @@ int __init ieee80211_crypto_ccmp_init(void) } -void __exit ieee80211_crypto_ccmp_exit(void) +void ieee80211_crypto_ccmp_exit(void) { ieee80211_unregister_crypto_ops(&ieee80211_crypt_ccmp); } diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_tkip.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_tkip.c index 7056d932057b..03cb21eb0658 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_tkip.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_crypt_tkip.c @@ -1012,7 +1012,7 @@ int __init ieee80211_crypto_tkip_init(void) } -void __exit ieee80211_crypto_tkip_exit(void) +void ieee80211_crypto_tkip_exit(void) { ieee80211_unregister_crypto_ops(&ieee80211_crypt_tkip); } -- cgit v1.2.3 From cf137d5c49379c5f05fba40baf1535b611410ec0 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 23 Dec 2009 19:54:54 +1100 Subject: Staging: rtl8192su, rtl8192u: use min_t() in store_debug_level() sizeof() returns a size_t but the other types involved are unsigned long, so using min() results in a warning. As sizeof() is called on an 11 character buffer defined immediately above unsigned long is obviously wide enough for the result. Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192su/ieee80211/ieee80211_module.c | 2 +- drivers/staging/rtl8192u/ieee80211/ieee80211_module.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_module.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_module.c index e8c67d5dfb76..c024fa600729 100644 --- a/drivers/staging/rtl8192su/ieee80211/ieee80211_module.c +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_module.c @@ -262,7 +262,7 @@ static int store_debug_level(struct file *file, const char *buffer, unsigned long count, void *data) { char buf[] = "0x00000000"; - unsigned long len = min(sizeof(buf) - 1, count); + unsigned long len = min_t(unsigned long, sizeof(buf) - 1, count); char *p = (char *)buf; unsigned long val; diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_module.c b/drivers/staging/rtl8192u/ieee80211/ieee80211_module.c index 7a8690f449b4..b752017a4d18 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211_module.c +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211_module.c @@ -260,7 +260,7 @@ static int store_debug_level(struct file *file, const char *buffer, unsigned long count, void *data) { char buf[] = "0x00000000"; - unsigned long len = min(sizeof(buf) - 1, count); + unsigned long len = min_t(unsigned long, sizeof(buf) - 1, count); char *p = (char *)buf; unsigned long val; -- cgit v1.2.3 From 2141ec629c9c9a70c905cfebcc8fa69373dd982a Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 24 Dec 2009 22:42:31 +1100 Subject: Staging: dt3155: remove compat code Remove compatibility code as this is not an older version of the kernel. Signed-off-by: Simon Horman Cc: Scott Smedley Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dt3155/allocator.c | 3 +- drivers/staging/dt3155/dt3155_drv.c | 115 +---- drivers/staging/dt3155/dt3155_drv.h | 5 - drivers/staging/dt3155/dt3155_isr.c | 41 +- drivers/staging/dt3155/pci-compat.h | 97 ----- drivers/staging/dt3155/sysdep.h | 820 ------------------------------------ 6 files changed, 8 insertions(+), 1073 deletions(-) delete mode 100644 drivers/staging/dt3155/pci-compat.h delete mode 100644 drivers/staging/dt3155/sysdep.h (limited to 'drivers') diff --git a/drivers/staging/dt3155/allocator.c b/drivers/staging/dt3155/allocator.c index c1b85447c0e0..4983c9379e57 100644 --- a/drivers/staging/dt3155/allocator.c +++ b/drivers/staging/dt3155/allocator.c @@ -54,11 +54,10 @@ #include #include #include /* PAGE_ALIGN() */ +#include #include -#include "sysdep.h" - /*#define ALL_DEBUG*/ #define ALL_MSG "allocator: " diff --git a/drivers/staging/dt3155/dt3155_drv.c b/drivers/staging/dt3155/dt3155_drv.c index 950956c08eda..6b40d422ad0c 100644 --- a/drivers/staging/dt3155/dt3155_drv.c +++ b/drivers/staging/dt3155/dt3155_drv.c @@ -59,13 +59,10 @@ extern void printques(int); #ifdef MODULE #include -#include #include -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,10) MODULE_LICENSE("GPL"); -#endif #endif @@ -105,11 +102,7 @@ int dt3155_errno = 0; #endif /* wait queue for interrupts */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,1) wait_queue_head_t dt3155_read_wait_queue[ MAXBOARDS ]; -#else -struct wait_queue *dt3155_read_wait_queue[ MAXBOARDS ]; -#endif #define DT_3155_SUCCESS 0 #define DT_3155_FAILURE -EIO @@ -186,11 +179,7 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) { int minor = -1; int index; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) unsigned long flags; -#else - int flags; -#endif u_long buffer_addr; /* find out who issued the interrupt */ @@ -264,21 +253,12 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) buffer_addr = dt3155_fbuffer[ minor ]-> frame_info[ dt3155_fbuffer[ minor ]->active_buf ].addr + (DT3155_MAX_ROWS / 2) * stride; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) local_save_flags(flags); local_irq_disable(); -#else - save_flags( flags ); - cli(); -#endif wake_up_interruptible( &dt3155_read_wait_queue[ minor ] ); /* Set up the DMA address for the next field */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) local_irq_restore(flags); -#else - restore_flags( flags ); -#endif WriteMReg((dt3155_lbase[ minor ] + ODD_DMA_START), buffer_addr); } @@ -350,13 +330,8 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) DT3155_STATE_FLD ) { -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) local_save_flags(flags); local_irq_disable(); -#else - save_flags( flags ); - cli(); -#endif #ifdef DEBUG_QUES_B printques( minor ); @@ -412,11 +387,7 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) wake_up_interruptible( &dt3155_read_wait_queue[ minor ] ); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) local_irq_restore(flags); -#else - restore_flags( flags ); -#endif } @@ -675,11 +646,6 @@ static int dt3155_mmap (struct file * file, struct vm_area_struct * vma) /* which device are we mmapping? */ int minor = MINOR(file->f_dentry->d_inode->i_rdev); unsigned long offset; - - /* not actually sure when vm_area_struct changed, - but it was in 2.3 sometime */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,20) - offset = vma->vm_pgoff << PAGE_SHIFT; if (offset >= __pa(high_memory) || (file->f_flags & O_SYNC)) @@ -688,34 +654,17 @@ static int dt3155_mmap (struct file * file, struct vm_area_struct * vma) /* Don't try to swap out physical pages.. */ vma->vm_flags |= VM_RESERVED; -#else - - if (vma->vm_offset & ~PAGE_MASK) - return -ENXIO; - - offset = vma->vm_offset; - -#endif - /* they are mapping the registers or the buffer */ if ((offset == dt3155_status[minor].reg_addr && vma->vm_end - vma->vm_start == PCI_PAGE_SIZE) || (offset == dt3155_status[minor].mem_addr && vma->vm_end - vma->vm_start == dt3155_status[minor].mem_size)) { -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) if (remap_pfn_range(vma, vma->vm_start, offset >> PAGE_SHIFT, vma->vm_end - vma->vm_start, - vma->vm_page_prot)) -#else - if (remap_page_range(vma->vm_start, - offset, - vma->vm_end - vma->vm_start, - vma->vm_page_prot)) -#endif - { + vma->vm_page_prot)) { printk("DT3155: remap_page_range() failed.\n"); return -EAGAIN; } @@ -761,9 +710,6 @@ static int dt3155_open( struct inode* inode, struct file* filep) printk("DT3155: Device opened.\n"); dt3155_dev_open[ minor ] = 1 ; -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) - MOD_INC_USE_COUNT; -#endif dt3155_flush( minor ); @@ -771,11 +717,7 @@ static int dt3155_open( struct inode* inode, struct file* filep) int_csr_r.reg = 0; WriteMReg( (dt3155_lbase[ minor ] + INT_CSR), int_csr_r.reg ); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,1) init_waitqueue_head(&(dt3155_read_wait_queue[minor])); -#else - dt3155_read_wait_queue[minor] = NULL; -#endif return 0; } @@ -798,9 +740,6 @@ static int dt3155_close( struct inode *inode, struct file *filep) } else { -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) - MOD_DEC_USE_COUNT; -#endif dt3155_dev_open[ minor ] = 0; if (dt3155_status[ minor ].state != DT3155_STATE_IDLE) @@ -846,8 +785,6 @@ static int dt3155_read ( /* if (dt3155_status[minor].state == DT3155_STATE_IDLE)*/ /* return -EBUSY;*/ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,1) - /* non-blocking reads should return if no data */ if (filep->f_flags & O_NDELAY) { @@ -877,34 +814,6 @@ static int dt3155_read ( } } -#else - while ((frame_index = dt3155_get_ready_buffer(minor)) < 0 ) - { - int index; - if (filep->f_flags & O_NDELAY) - return 0; - - /* sleep till data arrives , or we get interrupted */ - interruptible_sleep_on(&dt3155_read_wait_queue[minor]); - for (index = 0; index < _NSIG_WORDS; index++) - { - /* - * Changing the next line of code below to this: - * if (current->pending.signal.sig[index] & - * ~current->blocked.sig[index]) - * would also work on a 2.4 kernel, however, the above - * method is preferred & more portable. - */ - if (current->signal.sig[index] & ~current->blocked.sig[index]) - { - printk ("DT3155: read: interrupted\n"); - return -EINTR; - } - } - } - -#endif - frame_info_p = &dt3155_status[minor].fbuffer.frame_info[frame_index]; /* make this an offset */ @@ -1046,12 +955,6 @@ int init_module(void) int rcode = 0; char *devname[ MAXBOARDS ]; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,1) -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) - SET_MODULE_OWNER(&dt3155_fops); -#endif -#endif - devname[ 0 ] = "dt3155a"; #if MAXBOARDS == 2 devname[ 1 ] = "dt3155b"; @@ -1091,17 +994,6 @@ int init_module(void) /* Now let's find the hardware. find_PCI() will set ndevices to the * number of cards found in this machine. */ -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) - if ( !(pcibios_present()) ) - { - printk("DT3155: Error: No PCI bios on this machine \n"); - if( unregister_chrdev( dt3155_major, "dt3155" ) != 0 ) - printk("DT3155: cleanup_module failed\n"); - - return DT_3155_FAILURE; - } - else -#endif { if ( (rcode = find_PCI()) != DT_3155_SUCCESS ) { @@ -1199,10 +1091,5 @@ void cleanup_module(void) free_irq( dt3155_status[ index ].irq, (void*)&dt3155_status[index] ); } } - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) - if (MOD_IN_USE) - printk("DT3155: device busy, remove delayed\n"); -#endif } diff --git a/drivers/staging/dt3155/dt3155_drv.h b/drivers/staging/dt3155/dt3155_drv.h index dc110b76e463..215399a3d26a 100644 --- a/drivers/staging/dt3155/dt3155_drv.h +++ b/drivers/staging/dt3155/dt3155_drv.h @@ -33,13 +33,8 @@ extern u_char *dt3155_bbase; #ifdef __KERNEL__ #include -#include /* need access to LINUX_VERSION_CODE */ /* wait queue for reads */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 3, 1) extern wait_queue_head_t dt3155_read_wait_queue[MAXBOARDS]; -#else -extern struct wait_queue *dt3155_read_wait_queue[MAXBOARDS]; -#endif #endif /* number of devices */ diff --git a/drivers/staging/dt3155/dt3155_isr.c b/drivers/staging/dt3155/dt3155_isr.c index 339aee9a0925..54460dbb867a 100644 --- a/drivers/staging/dt3155/dt3155_isr.c +++ b/drivers/staging/dt3155/dt3155_isr.c @@ -435,20 +435,11 @@ static inline void internal_release_locked_buffer( int m ) *****************************************************/ inline void dt3155_release_locked_buffer( int m ) { -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) unsigned long int flags; local_save_flags(flags); local_irq_disable(); internal_release_locked_buffer(m); local_irq_restore(flags); -#else - int flags; - - save_flags( flags ); - cli(); - internal_release_locked_buffer( m ); - restore_flags( flags ); -#endif } @@ -460,15 +451,9 @@ inline void dt3155_release_locked_buffer( int m ) inline int dt3155_flush( int m ) { int index; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) - unsigned long int flags; - local_save_flags(flags); - local_irq_disable(); -#else - int flags; - save_flags( flags ); - cli(); -#endif + unsigned long int flags; + local_save_flags(flags); + local_irq_disable(); internal_release_locked_buffer( m ); dt3155_fbuffer[ m ]->empty_len = 0; @@ -486,11 +471,7 @@ inline int dt3155_flush( int m ) dt3155_fbuffer[ m ]->ready_head = 0; dt3155_fbuffer[ m ]->ready_len = 0; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) local_irq_restore(flags); -#else - restore_flags( flags ); -#endif return 0; } @@ -507,15 +488,9 @@ inline int dt3155_flush( int m ) inline int dt3155_get_ready_buffer( int m ) { int frame_index; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) - unsigned long int flags; - local_save_flags(flags); - local_irq_disable(); -#else - int flags; - save_flags( flags ); - cli(); -#endif + unsigned long int flags; + local_save_flags(flags); + local_irq_disable(); #ifdef DEBUG_QUES_A printques( m ); @@ -535,11 +510,7 @@ inline int dt3155_get_ready_buffer( int m ) printques( m ); #endif -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) local_irq_restore(flags); -#else - restore_flags( flags ); -#endif return frame_index; } diff --git a/drivers/staging/dt3155/pci-compat.h b/drivers/staging/dt3155/pci-compat.h deleted file mode 100644 index 5f47d5a94d4b..000000000000 --- a/drivers/staging/dt3155/pci-compat.h +++ /dev/null @@ -1,97 +0,0 @@ - -/* This header only makes send when included in a 2.0 compile */ - -#ifndef _PCI_COMPAT_H_ -#define _PCI_COMPAT_H_ - -#ifdef __KERNEL__ - -#include /* pcibios_* */ -#include /* pcibios_* */ -#include /* kmalloc */ - -/* fake the new pci interface based on the old one: encapsulate bus/devfn */ -struct pci_fake_dev { - u8 bus; - u8 devfn; - int index; -}; -#define pci_dev pci_fake_dev /* the other pci_dev is unused by 2.0 drivers */ - -extern inline struct pci_dev *pci_find_device(unsigned int vendorid, - unsigned int devid, - struct pci_dev *from) -{ - struct pci_dev *pptr = kmalloc(sizeof(*pptr), GFP_KERNEL); - int index = 0; - int ret; - - if (!pptr) return NULL; - if (from) index = pptr->index + 1; - ret = pcibios_find_device(vendorid, devid, index, - &pptr->bus, &pptr->devfn); - if (ret) { kfree(pptr); return NULL; } - return pptr; -} - -extern inline struct pci_dev *pci_find_class(unsigned int class, - struct pci_dev *from) -{ - return NULL; /* FIXME */ -} - -extern inline void pci_release_device(struct pci_dev *dev) -{ - kfree(dev); -} - -/* struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn); */ - -#define pci_present pcibios_present - -extern inline int -pci_read_config_byte(struct pci_dev *dev, u8 where, u8 *val) -{ - return pcibios_read_config_byte(dev->bus, dev->devfn, where, val); -} - -extern inline int -pci_read_config_word(struct pci_dev *dev, u8 where, u16 *val) -{ - return pcibios_read_config_word(dev->bus, dev->devfn, where, val); -} - -extern inline int -pci_read_config_dword(struct pci_dev *dev, u8 where, u32 *val) -{ - return pcibios_read_config_dword(dev->bus, dev->devfn, where, val); -} - -extern inline int -pci_write_config_byte(struct pci_dev *dev, u8 where, u8 val) -{ - return pcibios_write_config_byte(dev->bus, dev->devfn, where, val); -} - -extern inline int -pci_write_config_word(struct pci_dev *dev, u8 where, u16 val) -{ - return pcibios_write_config_word(dev->bus, dev->devfn, where, val); -} - -extern inline int -pci_write_config_dword(struct pci_dev *dev, u8 where, u32 val) -{ - return pcibios_write_config_dword(dev->bus, dev->devfn, where, val); -} - -extern inline void pci_set_master(struct pci_dev *dev) -{ - u16 cmd; - pcibios_read_config_word(dev->bus, dev->devfn, PCI_COMMAND, &cmd); - cmd |= PCI_COMMAND_MASTER; - pcibios_write_config_word(dev->bus, dev->devfn, PCI_COMMAND, cmd); -} - -#endif /* __KERNEL__ */ -#endif /* _PCI_COMPAT_H_ */ diff --git a/drivers/staging/dt3155/sysdep.h b/drivers/staging/dt3155/sysdep.h deleted file mode 100644 index 1d575d4a53ee..000000000000 --- a/drivers/staging/dt3155/sysdep.h +++ /dev/null @@ -1,820 +0,0 @@ -/* - * sysdep.h -- centralizing compatibility issues between 2.0, 2.2, 2.4 - * - * Copyright (C) 2001 Alessandro Rubini and Jonathan Corbet - * Copyright (C) 2001 O'Reilly & Associates - * - * The source code in this file can be freely used, adapted, - * and redistributed in source or binary form, so long as an - * acknowledgment appears in derived source files. The citation - * should list that the code comes from the book "Linux Device - * Drivers" by Alessandro Rubini and Jonathan Corbet, published - * by O'Reilly & Associates. No warranty is attached; - * we cannot take responsibility for errors or fitness for use. - * - * $Id: sysdep.h,v 1.2 2005/08/09 06:08:51 ssmedley Exp $ - */ - - -#ifndef _SYSDEP_H_ -#define _SYSDEP_H_ - -#ifndef LINUX_VERSION_CODE -# include -#endif - -#ifndef KERNEL_VERSION /* pre-2.1.90 didn't have it */ -# define KERNEL_VERSION(vers,rel,seq) ( ((vers)<<16) | ((rel)<<8) | (seq) ) -#endif - -/* only allow 2.0.x 2.2.y and 2.4.z */ - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,0,0) /* not < 2.0 */ -# error "This kernel is too old: not supported by this file" -#endif -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,7,0) /* not > 2.7, by now */ -# error "This kernel is too recent: not supported by this file" -#endif -#if (LINUX_VERSION_CODE & 0xff00) == 1 /* not 2.1 */ -# error "Please don't use linux-2.1, use 2.2, 2.4 or 2.6 instead" -#endif -#if (LINUX_VERSION_CODE & 0xff00) == 3 /* not 2.3 */ -# error "Please don't use linux-2.3, use 2.4 or 2.6 instead" -#endif - -/* remember about the current version */ -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0) -# define LINUX_20 -#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0) -# define LINUX_22 -#else -# define LINUX_24 -#endif - -/* we can't support versioning in pre-2.4 because we #define some functions */ -#if !defined(LINUX_24) && defined(CONFIG_MODVERSIONS) -# error "This sysdep.h can't support CONFIG_MODVERSIONS" -# error "and old kernels at the same time." -# error "Either use 2.4 or avoid using versioning" -#endif - -#ifndef LINUX_20 /* include vmalloc.h if this is 2.2/2.4 */ -# ifdef VM_READ /* a typical flag defined by mm.h */ -# include -# endif -#endif - -#include - -/* Modularization issues */ -#ifdef LINUX_20 -# define __USE_OLD_SYMTAB__ -# define EXPORT_NO_SYMBOLS register_symtab(NULL); -# define REGISTER_SYMTAB(tab) register_symtab(tab) -#else -# define REGISTER_SYMTAB(tab) /* nothing */ -#endif - -#ifdef __USE_OLD_SYMTAB__ -# define __MODULE_STRING(s) /* nothing */ -# define MODULE_PARM(v,t) /* nothing */ -# define MODULE_PARM_DESC(v,t) /* nothing */ -# define MODULE_AUTHOR(n) /* nothing */ -# define MODULE_DESCRIPTION(d) /* nothing */ -# define MODULE_SUPPORTED_DEVICE(n) /* nothing */ -#endif - -/* - * In version 2.2 (up to 2.2.19, at least), the macro for request_module() - * when no kmod is there is wrong. It's a "do {} while 0" but it shouldbe int - */ -#ifdef LINUX_22 -# ifndef CONFIG_KMOD -# undef request_module -# define request_module(name) -ENOSYS -# endif -#endif - - -#ifndef LINUX_20 -# include /* module_init/module_exit */ -#endif - -#ifndef module_init -# define module_init(x) int init_module(void) { return x(); } -# define module_exit(x) void cleanup_module(void) { x(); } -#endif - -#ifndef SET_MODULE_OWNER -# define SET_MODULE_OWNER(structure) /* nothing */ -#endif - -/* - * "select" changed in 2.1.23. The implementation is twin, but this - * header is new - * - */ -#ifdef LINUX_20 -# define __USE_OLD_SELECT__ -#else -# include -#endif - -#ifdef LINUX_20 -# define INODE_FROM_F(filp) ((filp)->f_inode) -#else -# define INODE_FROM_F(filp) ((filp)->f_dentry->d_inode) -#endif - -/* Other changes in the fops are solved using wrappers */ - -/* - * Wait queues changed with 2.3 - */ -#ifndef DECLARE_WAIT_QUEUE_HEAD -# define DECLARE_WAIT_QUEUE_HEAD(head) struct wait_queue *head = NULL - typedef struct wait_queue *wait_queue_head_t; -# define init_waitqueue_head(head) (*(head)) = NULL - -/* offer wake_up_sync as an alias for wake_up */ -# define wake_up_sync(head) wake_up(head) -# define wake_up_interruptible_sync(head) wake_up_interruptible(head) - -/* Pretend we have add_wait_queue_exclusive */ -# define add_wait_queue_exclusive(q,entry) add_wait_queue ((q), (entry)) - -#endif /* no DECLARE_WAIT_QUEUE_HEAD */ - -/* - * Define wait_event for 2.0 kernels. (This ripped off directly from - * the 2.2.18 sched.h) - */ -#ifdef LINUX_20 - -#define __wait_event(wq, condition) \ -do { \ - struct wait_queue __wait; \ - \ - __wait.task = current; \ - add_wait_queue(&wq, &__wait); \ - for (;;) { \ - current->state = TASK_UNINTERRUPTIBLE; \ - mb(); \ - if (condition) \ - break; \ - schedule(); \ - } \ - current->state = TASK_RUNNING; \ - remove_wait_queue(&wq, &__wait); \ -} while (0) - -#define wait_event(wq, condition) \ -do { \ - if (condition) \ - break; \ - __wait_event(wq, condition); \ -} while (0) - -#define __wait_event_interruptible(wq, condition, ret) \ -do { \ - struct wait_queue __wait; \ - \ - __wait.task = current; \ - add_wait_queue(&wq, &__wait); \ - for (;;) { \ - current->state = TASK_INTERRUPTIBLE; \ - mb(); \ - if (condition) \ - break; \ - if (!signal_pending(current)) { \ - schedule(); \ - continue; \ - } \ - ret = -ERESTARTSYS; \ - break; \ - } \ - current->state = TASK_RUNNING; \ - remove_wait_queue(&wq, &__wait); \ -} while (0) - -#define wait_event_interruptible(wq, condition) \ -({ \ - int __ret = 0; \ - if (!(condition)) \ - __wait_event_interruptible(wq, condition, __ret); \ - __ret; \ -}) -#endif - - -/* - * 2.3 added tasklets - */ -#ifdef LINUX_24 -# define HAVE_TASKLETS -#endif - - - - -/* FIXME: implement the other versions of wake_up etc */ - - -/* - * access to user space: use the 2.2 functions, - * and implement them as macros for 2.0 - */ - -#ifdef LINUX_20 -# include -# define access_ok(t,a,sz) (verify_area((t),(void *) (a),(sz)) ? 0 : 1) -# define verify_area_20 verify_area -# define copy_to_user(t,f,n) (memcpy_tofs((t), (f), (n)), 0) -# define copy_from_user(t,f,n) (memcpy_fromfs((t), (f), (n)), 0) -# define __copy_to_user(t,f,n) copy_to_user((t), (f), (n)) -# define __copy_from_user(t,f,n) copy_from_user((t), (f), (n)) - -# define PUT_USER(val,add) (put_user((val),(add)), 0) -# define __PUT_USER(val,add) PUT_USER((val),(add)) - -# define GET_USER(dest,add) ((dest)=get_user((add)), 0) -# define __GET_USER(dest,add) GET_USER((dest),(add)) -#else -# include -# include -# define verify_area_20(t,a,sz) (0) /* == success */ -# define PUT_USER put_user -# define __PUT_USER __put_user -# define GET_USER get_user -# define __GET_USER __get_user -#endif - -/* - * Allocation issues - */ -#ifdef GFP_USER /* only if mm.h has been included */ -# ifdef LINUX_20 -# define __GFP_DMA GFP_DMA /* 2.0 didn't have the leading __ */ -# endif -# ifndef LINUX_24 -# define __GFP_HIGHMEM 0 /* was not there */ -# define GFP_HIGHUSER 0 /* idem */ -# endif - -# ifdef LINUX_20 -# define __get_free_pages(a,b) __get_free_pages((a),(b),0) -# endif -# ifndef LINUX_24 -# define get_zeroed_page get_free_page -# endif -#endif - -/* ioremap */ -#if defined(LINUX_20) && defined(_LINUX_MM_H) -# define ioremap_nocache ioremap -# ifndef __i386__ - /* This simple approach works for non-PC platforms. */ -# define ioremap vremap -# define iounmap vfree -# else /* the PC has ISA; 2.2 and 2.4 remap it, 2.0 needs not */ -extern inline void *ioremap(unsigned long phys_addr, unsigned long size) -{ - if (phys_addr >= 0xA0000 && phys_addr + size <= 0x100000) - return (void *)phys_addr; - return vremap(phys_addr, size); -} - -extern inline void iounmap(void *addr) -{ - if ((unsigned long)addr >= 0xA0000 - && (unsigned long)addr < 0x100000) - return; - vfree(addr); -} -# endif -#endif - -/* Also, define check_mem_region etc */ -#ifndef LINUX_24 -# define check_mem_region(a,b) 0 /* success */ -# define request_mem_region(a,b,c) /* nothing */ -# define release_mem_region(a,b) /* nothing */ -#endif - -/* implement capable() for 2.0 */ -#ifdef LINUX_20 -# define capable(anything) suser() -#endif - -/* The use_count of exec_domain and binfmt changed in 2.1.23 */ - -#ifdef LINUX_20 -# define INCRCOUNT(p) ((p)->module ? __MOD_INC_USE_COUNT((p)->module) : 0) -# define DECRCOUNT(p) ((p)->module ? __MOD_DEC_USE_COUNT((p)->module) : 0) -# define CURRCOUNT(p) ((p)->module && (p)->module->usecount) -#else -# define INCRCOUNT(p) ((p)->use_count++) -# define DECRCOUNT(p) ((p)->use_count--) -# define CURRCOUNT(p) ((p)->use_count) -#endif - -/* - * /proc has changed a lot across the versions... - */ -#ifdef LINUX_20 -# define USE_PROC_REGISTER -#endif - - -/* - * 2.2 didn't have create_proc_{read|info}_entry yet. - * And it looks like there are no other "interesting" entry point, as - * the rest is somehow esotique (mknod, symlink, ...) - */ -#ifdef LINUX_22 -# ifdef PROC_SUPER_MAGIC /* Only if procfs is being used */ -extern inline struct proc_dir_entry *create_proc_read_entry(const char *name, - mode_t mode, struct proc_dir_entry *base, - read_proc_t *read_proc, void * data) -{ - struct proc_dir_entry *res=create_proc_entry(name,mode,base); - if (res) { - res->read_proc=read_proc; - res->data=data; - } - return res; -} - -# ifndef create_proc_info_entry /* added in 2.2.18 */ -typedef int (get_info_t)(char *, char **, off_t, int, int); -extern inline struct proc_dir_entry *create_proc_info_entry(const char *name, - mode_t mode, struct proc_dir_entry *base, get_info_t *get_info) -{ - struct proc_dir_entry *res=create_proc_entry(name,mode,base); - if (res) res->get_info=get_info; - return res; -} -# endif /* no create_proc_info_entry */ -# endif -#endif - -#ifdef LINUX_20 -# define test_and_set_bit(nr,addr) test_bit((nr),(addr)) -# define test_and_clear_bit(nr,addr) clear_bit((nr),(addr)) -# define test_and_change_bit(nr,addr) change_bit((nr),(addr)) -#endif - - -/* 2.0 had no read and write memory barriers, and 2.2 lacks the - set_ functions */ -#ifndef LINUX_24 -# ifdef LINUX_20 -# define wmb() mb() /* this is a big penalty on non-reordering platfs */ -# define rmb() mb() /* this is a big penalty on non-reordering platfs */ -# endif /* LINUX_20 */ - -#define set_mb() do { var = value; mb(); } while (0) -#define set_wmb() do { var = value; wmb(); } while (0) -#endif /* ! LINUX_24 */ - - - -/* 2.1.30 removed these functions. Let's define them, just in case */ -#ifndef LINUX_20 -# define queue_task_irq queue_task -# define queue_task_irq_off queue_task -#endif - -/* 2.1.10 and 2.1.43 introduced new functions. They are worth using */ - -#ifdef LINUX_20 - -# include -# ifdef __LITTLE_ENDIAN -# define cpu_to_le16(x) (x) -# define cpu_to_le32(x) (x) -# define cpu_to_be16(x) htons((x)) -# define cpu_to_be32(x) htonl((x)) -# else -# define cpu_to_be16(x) (x) -# define cpu_to_be32(x) (x) - extern inline __u16 cpu_to_le16(__u16 x) { return (x<<8) | (x>>8);} - extern inline __u32 cpu_to_le32(__u32 x) { return (x>>24) | - ((x>>8)&0xff00) | ((x<<8)&0xff0000) | (x<<24);} -# endif - -# define le16_to_cpu(x) cpu_to_le16(x) -# define le32_to_cpu(x) cpu_to_le32(x) -# define be16_to_cpu(x) cpu_to_be16(x) -# define be32_to_cpu(x) cpu_to_be32(x) - -# define cpu_to_le16p(addr) (cpu_to_le16(*(addr))) -# define cpu_to_le32p(addr) (cpu_to_le32(*(addr))) -# define cpu_to_be16p(addr) (cpu_to_be16(*(addr))) -# define cpu_to_be32p(addr) (cpu_to_be32(*(addr))) - - extern inline void cpu_to_le16s(__u16 *a) {*a = cpu_to_le16(*a);} - extern inline void cpu_to_le32s(__u16 *a) {*a = cpu_to_le32(*a);} - extern inline void cpu_to_be16s(__u16 *a) {*a = cpu_to_be16(*a);} - extern inline void cpu_to_be32s(__u16 *a) {*a = cpu_to_be32(*a);} - -# define le16_to_cpup(x) cpu_to_le16p(x) -# define le32_to_cpup(x) cpu_to_le32p(x) -# define be16_to_cpup(x) cpu_to_be16p(x) -# define be32_to_cpup(x) cpu_to_be32p(x) - -# define le16_to_cpus(x) cpu_to_le16s(x) -# define le32_to_cpus(x) cpu_to_le32s(x) -# define be16_to_cpus(x) cpu_to_be16s(x) -# define be32_to_cpus(x) cpu_to_be32s(x) - -#endif - -#ifdef LINUX_20 -# define __USE_OLD_REBUILD_HEADER__ -#endif - -/* - * 2.0 didn't include sema_init, so we make our own - but only if it - * looks like semaphore.h got included. - */ -#ifdef LINUX_20 -# ifdef MUTEX_LOCKED /* Only if semaphore.h included */ - extern inline void sema_init (struct semaphore *sem, int val) - { - sem->count = val; - sem->waking = sem->lock = 0; - sem->wait = NULL; - } -# endif -#endif /* LINUX_20 */ - -/* - * In 2.0, there is no real need for spinlocks, and they weren't really - * implemented anyway. - * - * XXX the _irqsave variant should be defined eventually to do the - * right thing. - */ -#ifdef LINUX_20 -typedef int spinlock_t; -# define spin_lock(lock) -# define spin_unlock(lock) -# define spin_lock_init(lock) - -# define spin_lock_irqsave(lock,flags) do { \ - save_flags(flags); cli(); } while (0); -# define spin_unlock_irqrestore(lock,flags) restore_flags(flags); -#endif - -/* - * 2.1 stuffed the "flush" method into the middle of the file_operations - * structure. The FOP_NO_FLUSH symbol is for drivers that do not implement - * flush (most of them), it can be inserted in initializers for all 2.x - * kernel versions. - */ -#ifdef LINUX_20 -# define FOP_NO_FLUSH /* nothing */ -# define TAG_LLSEEK lseek -# define TAG_POLL select -#else -# define FOP_NO_FLUSH NULL, -# define TAG_LLSEEK llseek -# define TAG_POLL poll -#endif - - - -/* - * fasync changed in 2.2. - */ -#ifdef LINUX_20 -/* typedef struct inode *fasync_file; */ -# define fasync_file struct inode * -#else - typedef int fasync_file; -#endif - -/* kill_fasync had less arguments, and a different indirection in the first */ -#ifndef LINUX_24 -# define kill_fasync(ptrptr,sig,band) kill_fasync(*(ptrptr),(sig)) -#endif - -/* other things that are virtualized: define the new functions for the old k */ -#ifdef LINUX_20 -# define in_interrupt() (intr_count!=0) -# define mdelay(x) udelay((x)*1000) -# define signal_pending(current) ((current)->signal & ~(current)->blocked) -#endif - -#ifdef LINUX_PCI_H /* only if PCI stuff is being used */ -# ifdef LINUX_20 -# include "pci-compat.h" /* a whole set of replacement functions */ -# else -# define pci_release_device(d) /* placeholder, used in 2.0 to free stuff */ -# endif -#endif - - - -/* - * Some task state stuff - */ - -#ifndef set_current_state -# define set_current_state(s) current->state = (s); -#endif - -#ifdef LINUX_20 -extern inline void schedule_timeout(int timeout) -{ - current->timeout = jiffies + timeout; - current->state = TASK_INTERRUPTIBLE; - schedule(); - current->timeout = 0; -} - -extern inline long sleep_on_timeout(wait_queue_head_t *q, signed long timeout) -{ - signed long early = 0; - - current->timeout = jiffies + timeout; - sleep_on (q); - if (current->timeout > 0) { - early = current->timeout - jiffies; - current->timeout = 0; - } - return early; -} - - -extern inline long interruptible_sleep_on_timeout(wait_queue_head_t *q, - signed long timeout) -{ - signed long early = 0; - - current->timeout = jiffies + timeout; - interruptible_sleep_on (q); - if (current->timeout > 0) { - early = current->timeout - jiffies; - current->timeout = 0; - } - return early; -} - -#endif /* LINUX_20 */ - -/* - * Schedule_task was a late 2.4 addition. - */ -#ifndef LINUX_24 -extern inline int schedule_task(struct tq_struct *task) -{ - queue_task(task, &tq_scheduler); - return 1; -} -#endif - - -/* - * Timing issues - */ -#ifdef LINUX_20 -# define get_fast_time do_gettimeofday -#endif - -#ifdef _LINUX_DELAY_H /* only if linux/delay.h is included */ -# ifndef mdelay /* linux-2.0 */ -# ifndef MAX_UDELAY_MS -# define MAX_UDELAY_MS 5 -# endif -# define mdelay(n) (\ - (__builtin_constant_p(n) && (n)<=MAX_UDELAY_MS) ? udelay((n)*1000) : \ - ({unsigned long msec=(n); while (msec--) udelay(1000);})) -# endif /* mdelay */ -#endif /* _LINUX_DELAY_H */ - - -/* - * No del_timer_sync before 2.4 - */ -#ifndef LINUX_24 -# define del_timer_sync(timer) del_timer(timer) /* and hope */ -#endif - -/* - * mod_timer wasn't present in 2.0 - */ -#ifdef LINUX_20 -static inline int mod_timer(struct timer_list *timer, unsigned long expires) -{ - int pending = del_timer(timer); - if (pending) { - timer->expires = expires; - add_timer(timer); - } - return pending; -} -#endif -/* - * Various changes in mmap and friends. - */ - -#ifndef NOPAGE_SIGBUS -# define NOPAGE_SIGBUS NULL /* return value of the nopage memory method */ -# define NOPAGE_OOM NULL /* No real equivalent in older kernels */ -#endif - -#ifndef VM_RESERVED /* Added 2.4.0-test10 */ -# define VM_RESERVED 0 -#endif - -#ifdef LINUX_24 /* use "vm_pgoff" to get an offset */ -#define VMA_OFFSET(vma) ((vma)->vm_pgoff << PAGE_SHIFT) -#else /* use "vm_offset" */ -#define VMA_OFFSET(vma) ((vma)->vm_offset) -#endif - -#ifdef MAP_NR -#define virt_to_page(page) (mem_map + MAP_NR(page)) -#endif - -#ifndef get_page -# define get_page(p) atomic_inc(&(p)->count) -#endif - -/* - * No DMA lock in 2.0. - */ -#ifdef LINUX_20 -static inline unsigned long claim_dma_lock(void) -{ - unsigned long flags; - save_flags(flags); - cli(); - return flags; -} - -static inline void release_dma_lock(unsigned long flags) -{ - restore_flags(flags); -} -#endif - - -/* - * I/O memory was not managed by ealier kernels, define them as success - */ - -#if 0 /* FIXME: what is the right way to do request_mem_region? */ -#ifndef LINUX_24 -# define check_mem_region(start, len) 0 -# define request_mem_region(start, len, name) 0 -# define release_mem_region(start, len) 0 - - /* - * Also, request_ and release_ region used to return void. Return 0 instead - */ -# define request_region(s, l, n) ({request_region((s),(l),(n));0;}) -# define release_region(s, l) ({release_region((s),(l));0;}) - -#endif /* not LINUX_24 */ -#endif - -/* - * Block layer stuff. - */ -#ifndef LINUX_24 - -/* BLK_DEFAULT_QUEUE for use with these macros only!!!! */ -#define BLK_DEFAULT_QUEUE(major) blk_dev[(major)].request_fn -#define blk_init_queue(where,request_fn) where = request_fn; -#define blk_cleanup_queue(where) where = NULL; - -/* No QUEUE_EMPTY in older kernels */ -#ifndef QUEUE_EMPTY /* Driver can redefine it too */ -# define QUEUE_EMPTY (CURRENT != NULL) -#endif - -#ifdef RO_IOCTLS -static inline int blk_ioctl(kdev_t dev, unsigned int cmd, unsigned long arg) -{ - int err; - - switch (cmd) { - case BLKRAGET: /* return the readahead value */ - if (!arg) return -EINVAL; - err = ! access_ok(VERIFY_WRITE, arg, sizeof(long)); - if (err) return -EFAULT; - PUT_USER(read_ahead[MAJOR(dev)],(long *) arg); - return 0; - - case BLKRASET: /* set the readahead value */ - if (!capable(CAP_SYS_ADMIN)) return -EACCES; - if (arg > 0xff) return -EINVAL; /* limit it */ - read_ahead[MAJOR(dev)] = arg; - return 0; - - case BLKFLSBUF: /* flush */ - if (! capable(CAP_SYS_ADMIN)) return -EACCES; /* only root */ - fsync_dev(dev); - invalidate_buffers(dev); - return 0; - - RO_IOCTLS(dev, arg); - } - return -ENOTTY; -} -#endif /* RO_IOCTLS */ - -#ifdef LINUX_EXTENDED_PARTITION /* defined in genhd.h */ -static inline void register_disk(struct gendisk *gdev, kdev_t dev, - unsigned minors, struct file_operations *ops, long size) -{ - if (! gdev) - return; - resetup_one_dev(gdev, MINOR(dev) >> gdev->minor_shift); -} -#endif /* LINUX_EXTENDED_PARTITION */ - - -#else /* it is Linux 2.4 */ -#define HAVE_BLKPG_H -#endif /* LINUX_24 */ - - - -#ifdef LINUX_20 /* physical and virtual addresses had the same value */ -# define __pa(a) (a) -# define __va(a) (a) -#endif - -/* - * Network driver compatibility - */ - -/* - * 2.0 dev_kfree_skb had an extra arg. The following is a little dangerous - * in that it assumes that FREE_WRITE is always wanted. Very few 2.0 drivers - * use FREE_READ, but the number is *not* zero... - * - * Also: implement the non-checking versions of a couple skb functions - - * but they still check in 2.0. - */ -#ifdef LINUX_20 -# define dev_kfree_skb(skb) dev_kfree_skb((skb), FREE_WRITE); - -# define __skb_push(skb, len) skb_push((skb), (len)) -# define __skb_put(skb, len) skb_put((skb), (len)) -#endif - -/* - * Softnet changes in 2.4 - */ -#ifndef LINUX_24 -# ifdef _LINUX_NETDEVICE_H /* only if netdevice.h was included */ -# define netif_start_queue(dev) clear_bit(0, (void *) &(dev)->tbusy); -# define netif_stop_queue(dev) set_bit(0, (void *) &(dev)->tbusy); - -static inline void netif_wake_queue(struct device *dev) -{ - clear_bit(0, (void *) &(dev)->tbusy); - mark_bh(NET_BH); -} - -/* struct device became struct net_device */ -# define net_device device -# endif /* netdevice.h */ -#endif /* ! LINUX_24 */ - -/* - * Memory barrier stuff, define what's missing from older kernel versions - */ -#ifdef switch_to /* this is always a macro, defined in */ - -# ifndef set_mb -# define set_mb(var, value) do {(var) = (value); mb();} while 0 -# endif -# ifndef set_rmb -# define set_rmb(var, value) do {(var) = (value); rmb();} while 0 -# endif -# ifndef set_wmb -# define set_wmb(var, value) do {(var) = (value); wmb();} while 0 -# endif - -/* The hw barriers are defined as sw barriers. A correct thing if this - specific kernel/platform is supported but has no specific instruction */ -# ifndef mb -# define mb barrier -# endif -# ifndef rmb -# define rmb barrier -# endif -# ifndef wmb -# define wmb barrier -# endif - -#endif /* switch to (i.e. ) */ - - -#endif /* _SYSDEP_H_ */ -- cgit v1.2.3 From ef4ffb7ade54f7669172cf5cead69695e588c06a Mon Sep 17 00:00:00 2001 From: C yp Date: Wed, 6 Jan 2010 13:42:00 +0100 Subject: Staging: ramzswap: Minor spelling fixes Also removed an extra semicolon. Signed-off-by: Cyp Cc: Nitin Gupta Signed-off-by: Greg Kroah-Hartman --- drivers/staging/ramzswap/Kconfig | 2 +- drivers/staging/ramzswap/ramzswap.txt | 6 +++--- drivers/staging/ramzswap/ramzswap_drv.c | 4 ++-- drivers/staging/ramzswap/ramzswap_drv.h | 6 +++--- drivers/staging/ramzswap/ramzswap_ioctl.h | 4 ++-- drivers/staging/ramzswap/xvmalloc.c | 2 +- drivers/staging/ramzswap/xvmalloc_int.h | 2 +- 7 files changed, 13 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/ramzswap/Kconfig b/drivers/staging/ramzswap/Kconfig index 24e25691fae2..127b3c6c9596 100644 --- a/drivers/staging/ramzswap/Kconfig +++ b/drivers/staging/ramzswap/Kconfig @@ -5,7 +5,7 @@ config RAMZSWAP select LZO_DECOMPRESS default n help - Creates virtual block devices which can be used (only) as a swap + Creates virtual block devices which can (only) be used as swap disks. Pages swapped to these disks are compressed and stored in memory itself. diff --git a/drivers/staging/ramzswap/ramzswap.txt b/drivers/staging/ramzswap/ramzswap.txt index e9f1619505a0..9694acfeb43f 100644 --- a/drivers/staging/ramzswap/ramzswap.txt +++ b/drivers/staging/ramzswap/ramzswap.txt @@ -5,9 +5,9 @@ Project home: http://compcache.googlecode.com/ * Introduction -It creates RAM based block devices which can be used (only) as swap disks. -Pages swapped to these devices are compressed and stored in memory itself. -See project home for use cases, performance numbers and a lot more. +The ramzswap module creates RAM based block devices which can (only) be used as +swap disks. Pages swapped to these devices are compressed and stored in memory +itself. See project home for use cases, performance numbers and a lot more. Individual ramzswap devices are configured and initialized using rzscontrol userspace utility as shown in examples below. See rzscontrol man page for more diff --git a/drivers/staging/ramzswap/ramzswap_drv.c b/drivers/staging/ramzswap/ramzswap_drv.c index 18196f3852d8..7a7ead4e6c87 100644 --- a/drivers/staging/ramzswap/ramzswap_drv.c +++ b/drivers/staging/ramzswap/ramzswap_drv.c @@ -730,7 +730,7 @@ static int ramzswap_read(struct ramzswap *rzs, struct bio *bio) if (!rzs->table[index].page) return handle_ramzswap_fault(rzs, bio); - /* Page is stored uncompressed since its incompressible */ + /* Page is stored uncompressed since it's incompressible */ if (unlikely(rzs_test_flag(rzs, index, RZS_UNCOMPRESSED))) return handle_uncompressed_page(rzs, bio); @@ -792,7 +792,7 @@ static int ramzswap_write(struct ramzswap *rzs, struct bio *bio) ramzswap_free_page(rzs, index); /* - * No memory ia allocated for zero filled pages. + * No memory is allocated for zero filled pages. * Simply clear zero page flag. */ if (rzs_test_flag(rzs, index, RZS_ZERO)) { diff --git a/drivers/staging/ramzswap/ramzswap_drv.h b/drivers/staging/ramzswap/ramzswap_drv.h index a6ea240935b6..7ba98bfee2d6 100644 --- a/drivers/staging/ramzswap/ramzswap_drv.h +++ b/drivers/staging/ramzswap/ramzswap_drv.h @@ -102,7 +102,7 @@ struct table { u16 offset; u8 count; /* object ref count (not yet used) */ u8 flags; -} __attribute__((aligned(4)));; +} __attribute__((aligned(4))); /* * Swap extent information in case backing swap is a regular @@ -121,8 +121,8 @@ struct ramzswap_stats { #if defined(CONFIG_RAMZSWAP_STATS) u64 num_reads; /* failed + successful */ u64 num_writes; /* --do-- */ - u64 failed_reads; /* can happen when memory is too low */ - u64 failed_writes; /* should NEVER! happen */ + u64 failed_reads; /* should NEVER! happen */ + u64 failed_writes; /* can happen when memory is too low */ u64 invalid_io; /* non-swap I/O requests */ u32 pages_zero; /* no. of zero filled pages */ u32 pages_stored; /* no. of pages currently stored */ diff --git a/drivers/staging/ramzswap/ramzswap_ioctl.h b/drivers/staging/ramzswap/ramzswap_ioctl.h index c713a09af580..1bc54e22c915 100644 --- a/drivers/staging/ramzswap/ramzswap_ioctl.h +++ b/drivers/staging/ramzswap/ramzswap_ioctl.h @@ -24,8 +24,8 @@ struct ramzswap_ioctl_stats { * size (if present) */ u64 num_reads; /* failed + successful */ u64 num_writes; /* --do-- */ - u64 failed_reads; /* can happen when memory is too low */ - u64 failed_writes; /* should NEVER! happen */ + u64 failed_reads; /* should NEVER! happen */ + u64 failed_writes; /* can happen when memory is too low */ u64 invalid_io; /* non-swap I/O requests */ u32 pages_zero; /* no. of zero filled pages */ u32 good_compress_pct; /* no. of pages with compression ratio<=50% */ diff --git a/drivers/staging/ramzswap/xvmalloc.c b/drivers/staging/ramzswap/xvmalloc.c index b3e986c33141..dabd266a427b 100644 --- a/drivers/staging/ramzswap/xvmalloc.c +++ b/drivers/staging/ramzswap/xvmalloc.c @@ -273,7 +273,7 @@ static void remove_block(struct xv_pool *pool, struct page *page, u32 offset, } /* - * Allocate a page and add it freelist of given pool. + * Allocate a page and add it to freelist of given pool. */ static int grow_pool(struct xv_pool *pool, gfp_t flags) { diff --git a/drivers/staging/ramzswap/xvmalloc_int.h b/drivers/staging/ramzswap/xvmalloc_int.h index 03c1a652a3aa..263c72d1fb3d 100644 --- a/drivers/staging/ramzswap/xvmalloc_int.h +++ b/drivers/staging/ramzswap/xvmalloc_int.h @@ -62,7 +62,7 @@ struct link_free { struct block_header { union { - /* This common header must be ALIGN bytes */ + /* This common header must be XV_ALIGN bytes */ u8 common[XV_ALIGN]; struct { u16 size; -- cgit v1.2.3 From 5d3aed742498ffe5692e3f974f3f7ea0e99a93bb Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 28 Dec 2009 18:57:51 +0200 Subject: Staging: comedi: off by one in doDevConfig() Changed > to >= to avoid array overflow. Signed-off-by: Dan Carpenter Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/comedi_bond.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/comedi_bond.c b/drivers/staging/comedi/drivers/comedi_bond.c index cf39a24ddd4c..d7260cc86985 100644 --- a/drivers/staging/comedi/drivers/comedi_bond.c +++ b/drivers/staging/comedi/drivers/comedi_bond.c @@ -417,7 +417,7 @@ static int doDevConfig(struct comedi_device *dev, struct comedi_devconfig *it) int sdev = -1, nchans, tmp; struct BondedDevice *bdev = NULL; - if (minor < 0 || minor > COMEDI_NUM_BOARD_MINORS) { + if (minor < 0 || minor >= COMEDI_NUM_BOARD_MINORS) { ERROR("Minor %d is invalid!\n", minor); return 0; } -- cgit v1.2.3 From 4b2ba24399cfcd7c80a20cd3bbedc5df0ebd4345 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 28 Dec 2009 18:59:01 +0200 Subject: Staging: comedi: reorder check in pcmmio_attach() The check for dio_num_asics is used to determine if there is more than 1 irq. If it is false then irq[1] is past the end of the array. Signed-off-by: Dan Carpenter Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcmmio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcmmio.c b/drivers/staging/comedi/drivers/pcmmio.c index 35ba93989a36..6ca4105610c1 100644 --- a/drivers/staging/comedi/drivers/pcmmio.c +++ b/drivers/staging/comedi/drivers/pcmmio.c @@ -550,7 +550,7 @@ static int pcmmio_attach(struct comedi_device *dev, struct comedi_devconfig *it) if (irq[0]) { printk("irq: %u ", irq[0]); - if (irq[1] && thisboard->dio_num_asics == 2) + if (thisboard->dio_num_asics == 2 && irq[1]) printk("second ASIC irq: %u ", irq[1]); } else { printk("(IRQ mode disabled) "); -- cgit v1.2.3 From 7a02f549fcc30fe6be0c0024beae9a3db22e1af6 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 28 Dec 2009 18:59:46 +0200 Subject: Staging: cx25821: fix double unlock in medusa_video_init() medusa_set_videostandard() takes the lock but it always drops it before returning. This was found with a static checker and compile tested only. :/ Signed-off-by: Dan Carpenter Signed-off-by: Greg Kroah-Hartman --- drivers/staging/cx25821/cx25821-medusa-video.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/cx25821/cx25821-medusa-video.c b/drivers/staging/cx25821/cx25821-medusa-video.c index 1eb079b3d429..d6016200d699 100644 --- a/drivers/staging/cx25821/cx25821-medusa-video.c +++ b/drivers/staging/cx25821/cx25821-medusa-video.c @@ -795,10 +795,8 @@ int medusa_video_init(struct cx25821_dev *dev) value &= 0xFFFFFFDF; ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value); - if (ret_val < 0) { - mutex_unlock(&dev->lock); + if (ret_val < 0) return -EINVAL; - } mutex_unlock(&dev->lock); -- cgit v1.2.3 From ed30013207ef3e36da4f39db1298ae53f799e29c Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 28 Dec 2009 19:00:24 +0200 Subject: Staging: cx25821: off by one in cx25821_enum_input() The INPUT(n) macro indexes an array of size 2. Signed-off-by: Dan Carpenter Signed-off-by: Greg Kroah-Hartman --- drivers/staging/cx25821/cx25821-video.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/cx25821/cx25821-video.c b/drivers/staging/cx25821/cx25821-video.c index c7c14c7698a7..6e710ae067ad 100644 --- a/drivers/staging/cx25821/cx25821-video.c +++ b/drivers/staging/cx25821/cx25821-video.c @@ -876,7 +876,7 @@ int cx25821_enum_input(struct cx25821_dev *dev, struct v4l2_input *i) dprintk(1, "%s()\n", __func__); n = i->index; - if (n > 2) + if (n >= 2) return -EINVAL; if (0 == INPUT(n)->type) -- cgit v1.2.3 From 1c7e4a7c326c916918b5a29051db4f93973e775a Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 28 Dec 2009 19:01:34 +0200 Subject: Staging: otus: off by one in usbdrvwext_siwessid() A 33 char ESSID is too long and it could cause a buffer overflow a couple lines below when we put a NULL terminator on the end. Signed-off-by: Dan Carpenter Signed-off-by: Greg Kroah-Hartman --- drivers/staging/otus/ioctl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/otus/ioctl.c b/drivers/staging/otus/ioctl.c index 6808e69fb354..86d93330acad 100644 --- a/drivers/staging/otus/ioctl.c +++ b/drivers/staging/otus/ioctl.c @@ -930,7 +930,7 @@ int usbdrvwext_siwessid(struct net_device *dev, return -EINVAL; if (essid->flags == 1) { - if (essid->length > (IW_ESSID_MAX_SIZE + 1)) + if (essid->length > IW_ESSID_MAX_SIZE) return -E2BIG; if (copy_from_user(&EssidBuf, essid->pointer, essid->length)) -- cgit v1.2.3 From 28a2333413b2fbb74b35d55e1dd8c349dc825a16 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Mon, 28 Dec 2009 19:21:34 -0500 Subject: Staging: et131x_netdev.c: use %pM to shown MAC address Trivial, use the %pM kernel extension to display the MAC address. Signed-off-by: H Hartley Sweeten Cc: Olaf Hartmann Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et131x_netdev.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et131x_netdev.c b/drivers/staging/et131x/et131x_netdev.c index 24d97b4fa6fb..c63032fa88c5 100644 --- a/drivers/staging/et131x/et131x_netdev.c +++ b/drivers/staging/et131x/et131x_netdev.c @@ -674,12 +674,8 @@ int et131x_set_mac_addr(struct net_device *netdev, void *new_mac) memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len); - printk(KERN_INFO - "%s: Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n", - netdev->name, - netdev->dev_addr[0], netdev->dev_addr[1], - netdev->dev_addr[2], netdev->dev_addr[3], - netdev->dev_addr[4], netdev->dev_addr[5]); + printk(KERN_INFO "%s: Setting MAC address to %pM\n", + netdev->name, netdev->dev_addr); /* Free Rx DMA memory */ et131x_adapter_memory_free(adapter); -- cgit v1.2.3 From 820793c396846e5885b0d28c68512d08b5cb77cf Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Mon, 28 Dec 2009 19:28:11 -0500 Subject: Staging: r8192E_core.c: use %pM to shown MAC address Trivial, use the %pM kernel extension to display the MAC address. Signed-off-by: H Hartley Sweeten Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/r8192E_core.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192e/r8192E_core.c b/drivers/staging/rtl8192e/r8192E_core.c index d3105281d31e..50c760284df4 100644 --- a/drivers/staging/rtl8192e/r8192E_core.c +++ b/drivers/staging/rtl8192e/r8192E_core.c @@ -2814,10 +2814,7 @@ static void rtl8192_read_eeprom_info(struct net_device* dev) memcpy(dev->dev_addr, bMac_Tmp_Addr, 6); } - RT_TRACE(COMP_INIT, "Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", - dev->dev_addr[0], dev->dev_addr[1], - dev->dev_addr[2], dev->dev_addr[3], - dev->dev_addr[4], dev->dev_addr[5]); + RT_TRACE(COMP_INIT, "Permanent Address = %pM\n", dev->dev_addr); //2 TX Power Check EEPROM Fail or not if(priv->card_8192_version > VERSION_8190_BD) { -- cgit v1.2.3 From 6756993bafb436af088dacdef92b756f5f96134e Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Mon, 28 Dec 2009 19:33:17 -0500 Subject: r8192U_core.c: use %pM to shown MAC address Trivial, use the %pM kernel extension to display the MAC address. Signed-off-by: H Hartley Sweeten Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192su/r8192U_core.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192su/r8192U_core.c b/drivers/staging/rtl8192su/r8192U_core.c index ecfa91b56c8d..27c45fbbcca5 100644 --- a/drivers/staging/rtl8192su/r8192U_core.c +++ b/drivers/staging/rtl8192su/r8192U_core.c @@ -3426,10 +3426,9 @@ rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(struct net_device* dev) write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]); write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]); - RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", - dev->dev_addr[0], dev->dev_addr[1], - dev->dev_addr[2], dev->dev_addr[3], - dev->dev_addr[4], dev->dev_addr[5]); + RT_TRACE(COMP_INIT, + "ReadAdapterInfo8192SEFuse(), Permanent Address = %pM\n", + dev->dev_addr); priv->EEPROMBoardType = EEPROM_Default_BoardType; priv->rf_type = RF_1T2R; //RF_2T2R @@ -3767,10 +3766,9 @@ rtl8192SU_ReadAdapterInfo8192SUsb(struct net_device* dev) write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]); write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]); - RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", - dev->dev_addr[0], dev->dev_addr[1], - dev->dev_addr[2], dev->dev_addr[3], - dev->dev_addr[4], dev->dev_addr[5]); + RT_TRACE(COMP_INIT, + "ReadAdapterInfo8192SEFuse(), Permanent Address = %pM\n", + dev->dev_addr); // // Get CustomerID(Boad Type) -- cgit v1.2.3 From 00367a6d7caae9c6b077e177aeebad5b0a91ea62 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Mon, 28 Dec 2009 19:38:22 -0500 Subject: Staging: vt6655/device_main.c: use %pM to shown MAC address Trivial, use the %pM kernel extension to display the MAC address. Signed-off-by: H Hartley Sweeten Cc: Forest Bond Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vt6655/device_main.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vt6655/device_main.c b/drivers/staging/vt6655/device_main.c index 0db8d7b6e79c..ddf3aa04db09 100644 --- a/drivers/staging/vt6655/device_main.c +++ b/drivers/staging/vt6655/device_main.c @@ -1105,10 +1105,7 @@ static void device_print_info(PSDevice pDevice) struct net_device* dev=pDevice->dev; DBG_PRT(MSG_LEVEL_INFO, KERN_INFO "%s: %s\n",dev->name, get_chip_name(pDevice->chip_id)); - DBG_PRT(MSG_LEVEL_INFO, KERN_INFO "%s: MAC=%2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X", - dev->name, - dev->dev_addr[0],dev->dev_addr[1],dev->dev_addr[2], - dev->dev_addr[3],dev->dev_addr[4],dev->dev_addr[5]); + DBG_PRT(MSG_LEVEL_INFO, KERN_INFO "%s: MAC=%pM", dev->name, dev->dev_addr); #ifdef IO_MAP DBG_PRT(MSG_LEVEL_INFO, KERN_INFO" IO=0x%lx ",(ULONG) pDevice->ioaddr); DBG_PRT(MSG_LEVEL_INFO, KERN_INFO" IRQ=%d \n", pDevice->dev->irq); -- cgit v1.2.3 From 88e05d854cbbd583d528be9295a74586f920492b Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 30 Dec 2009 18:10:18 +0200 Subject: Staging: rtl8192su: buffer overflow in r8192U_core.c There was a buffer overflow in the original code. rf_path was 2 and it should have been only 0 or 1. I don't have the hardware for this, so I can't test it. Looking at the code, there are two almost identical sections for updating the hal variables. The first one was clearly wrong and had the array overflow as well. The second one looked correct. I decided to use the second section as is except for whitespace changes. The differences between the two original sections: 1) The second one had more debug output. 2) The second one looped over rf_path instead of corrupting data. 3) The second one had these additional assigments. if (rf_path == 0) { priv->TxPowerLevelOFDM24G[i] = priv->RfTxPwrLevelOfdm1T[rf_path][i] ; priv->TxPowerLevelCCK[i] = priv->RfTxPwrLevelCck[rf_path][i]; } Signed-off-by: Dan Carpenter Cc: Jerry chuang Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192su/r8192U_core.c | 127 +++++++++++--------------------- 1 file changed, 43 insertions(+), 84 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192su/r8192U_core.c b/drivers/staging/rtl8192su/r8192U_core.c index 27c45fbbcca5..f15be1eca324 100644 --- a/drivers/staging/rtl8192su/r8192U_core.c +++ b/drivers/staging/rtl8192su/r8192U_core.c @@ -3359,6 +3359,46 @@ u8 rtl8192SU_BoardTypeToRFtype(struct net_device* dev, u8 Boardtype) return RFtype; } +void update_hal_variables(struct r8192_priv *priv) +{ + int rf_path; + int i; + u8 index; + + for (rf_path = 0; rf_path < 2; rf_path++) { + for (i = 0; i < 3; i++) { + RT_TRACE((COMP_INIT), "CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, priv->RfCckChnlAreaTxPwr[rf_path][i]); + RT_TRACE((COMP_INIT), "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]); + RT_TRACE((COMP_INIT), "OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]); + } + /* Assign dedicated channel tx power */ + for(i = 0; i < 14; i++) { + /* channel 1-3 use the same Tx Power Level. */ + if (i < 3) /* Channel 1-3 */ + index = 0; + else if (i < 9) /* Channel 4-9 */ + index = 1; + else /* Channel 10-14 */ + index = 2; + /* Record A & B CCK /OFDM - 1T/2T Channel area tx power */ + priv->RfTxPwrLevelCck[rf_path][i] = priv->RfCckChnlAreaTxPwr[rf_path][index]; + priv->RfTxPwrLevelOfdm1T[rf_path][i] = priv->RfOfdmChnlAreaTxPwr1T[rf_path][index]; + priv->RfTxPwrLevelOfdm2T[rf_path][i] = priv->RfOfdmChnlAreaTxPwr2T[rf_path][index]; + if (rf_path == 0) { + priv->TxPowerLevelOFDM24G[i] = priv->RfTxPwrLevelOfdm1T[rf_path][i] ; + priv->TxPowerLevelCCK[i] = priv->RfTxPwrLevelCck[rf_path][i]; + } + } + for(i = 0; i < 14; i++) { + RT_TRACE((COMP_INIT), + "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n", + rf_path, i, priv->RfTxPwrLevelCck[rf_path][i], + priv->RfTxPwrLevelOfdm1T[rf_path][i] , + priv->RfTxPwrLevelOfdm2T[rf_path][i] ); + } + } +} + // // Description: // Config HW adapter information into initial value. @@ -3374,7 +3414,7 @@ rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(struct net_device* dev) struct r8192_priv *priv = ieee80211_priv(dev); //u16 i,usValue; //u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00}; - u8 rf_path, index; // For EEPROM/EFUSE After V0.6_1117 + u8 rf_path; // For EEPROM/EFUSE After V0.6_1117 int i; RT_TRACE(COMP_INIT, "====> ConfigAdapterInfo8192SForAutoLoadFail\n"); @@ -3454,42 +3494,7 @@ rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(struct net_device* dev) } } - for (i = 0; i < 3; i++) - { - //RT_TRACE((COMP_EFUSE), "CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, - //priv->RfCckChnlAreaTxPwr[rf_path][i]); - //RT_TRACE((COMP_EFUSE), "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, - //priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]); - //RT_TRACE((COMP_EFUSE), "OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, - //priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]); - } - - // Assign dedicated channel tx power - for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level. - { - if (i < 3) // Cjanel 1-3 - index = 0; - else if (i < 9) // Channel 4-9 - index = 1; - else // Channel 10-14 - index = 2; - - // Record A & B CCK /OFDM - 1T/2T Channel area tx power - priv->RfTxPwrLevelCck[rf_path][i] = - priv->RfCckChnlAreaTxPwr[rf_path][index]; - priv->RfTxPwrLevelOfdm1T[rf_path][i] = - priv->RfOfdmChnlAreaTxPwr1T[rf_path][index]; - priv->RfTxPwrLevelOfdm2T[rf_path][i] = - priv->RfOfdmChnlAreaTxPwr2T[rf_path][index]; - } - - for(i=0; i<14; i++) - { - //RT_TRACE((COMP_EFUSE), "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n", - //rf_path, i, priv->RfTxPwrLevelCck[0][i], - //priv->RfTxPwrLevelOfdm1T[0][i] , - //priv->RfTxPwrLevelOfdm2T[0][i] ); - } + update_hal_variables(priv); // // Update remained HAL variables. @@ -3899,53 +3904,7 @@ rtl8192SU_ReadAdapterInfo8192SUsb(struct net_device* dev) } } -// - // Update Tx Power HAL variables. -// - for (rf_path = 0; rf_path < 2; rf_path++) - { - for (i = 0; i < 3; i++) - { - RT_TRACE((COMP_INIT), "CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, - priv->RfCckChnlAreaTxPwr[rf_path][i]); - RT_TRACE((COMP_INIT), "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, - priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]); - RT_TRACE((COMP_INIT), "OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]); - } - - // Assign dedicated channel tx power - for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level. - { - if (i < 3) // Cjanel 1-3 - index = 0; - else if (i < 9) // Channel 4-9 - index = 1; - else // Channel 10-14 - index = 2; - - // Record A & B CCK /OFDM - 1T/2T Channel area tx power - priv->RfTxPwrLevelCck[rf_path][i] = - priv->RfCckChnlAreaTxPwr[rf_path][index]; - priv->RfTxPwrLevelOfdm1T[rf_path][i] = - priv->RfOfdmChnlAreaTxPwr1T[rf_path][index]; - priv->RfTxPwrLevelOfdm2T[rf_path][i] = - priv->RfOfdmChnlAreaTxPwr2T[rf_path][index]; - if (rf_path == 0) - { - priv->TxPowerLevelOFDM24G[i] = priv->RfTxPwrLevelOfdm1T[rf_path][i] ; - priv->TxPowerLevelCCK[i] = priv->RfTxPwrLevelCck[rf_path][i]; - } - } - - for(i=0; i<14; i++) - { - RT_TRACE((COMP_INIT), - "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n", - rf_path, i, priv->RfTxPwrLevelCck[rf_path][i], - priv->RfTxPwrLevelOfdm1T[rf_path][i] , - priv->RfTxPwrLevelOfdm2T[rf_path][i] ); - } - } + update_hal_variables(priv); } // -- cgit v1.2.3 From f3557cc180b73308048867b591111df6436987ff Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Thu, 31 Dec 2009 21:54:46 +1300 Subject: Staging: rar: Fix all coding style issues. This fixes all coding style issues and some spelling mistakes. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rar/rar_driver.c | 132 +++++++++++++++++++-------------------- drivers/staging/rar/rar_driver.h | 68 +++++++++----------- 2 files changed, 93 insertions(+), 107 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rar/rar_driver.c b/drivers/staging/rar/rar_driver.c index d85d1890e81e..b91a90f4ce9e 100644 --- a/drivers/staging/rar/rar_driver.c +++ b/drivers/staging/rar/rar_driver.c @@ -68,7 +68,8 @@ static void __exit rar_exit_handler(void); /* function that is activated on the successfull probe of the RAR device */ -static int __devinit rar_probe(struct pci_dev *pdev, const struct pci_device_id *ent); +static int __devinit rar_probe(struct pci_dev *pdev, + const struct pci_device_id *ent); static struct pci_device_id rar_pci_id_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4110) }, @@ -86,9 +87,9 @@ static struct pci_driver rar_pci_driver = { /* This function is used to retrieved RAR info using the IPC message bus interface */ -static int memrar_get_rar_addr(struct pci_dev* pdev, - int offset, - u32 *addr) +static int memrar_get_rar_addr(struct pci_dev *pdev, + int offset, + u32 *addr) { /* * ======== The Lincroft Message Bus Interface ======== @@ -140,29 +141,29 @@ static int memrar_get_rar_addr(struct pci_dev* pdev, | (offset << 8) | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); - printk(KERN_WARNING "rar- offset to LNC MSG is %x\n",offset); + printk(KERN_WARNING "rar- offset to LNC MSG is %x\n", offset); if (addr == 0) return -EINVAL; /* Send the control message */ result = pci_write_config_dword(pdev, - LNC_MCR_OFFSET, - message); + LNC_MCR_OFFSET, + message); - printk(KERN_WARNING "rar- result from send ctl register is %x\n" - ,result); + printk(KERN_WARNING "rar- result from send ctl register is %x\n", + result); if (!result) result = pci_read_config_dword(pdev, - LNC_MDR_OFFSET, - addr); + LNC_MDR_OFFSET, + addr); printk(KERN_WARNING "rar- result from read data register is %x\n", - result); + result); printk(KERN_WARNING "rar- value read from data register is %x\n", - *addr); + *addr); if (result) return -1; @@ -170,9 +171,9 @@ static int memrar_get_rar_addr(struct pci_dev* pdev, return 0; } -static int memrar_set_rar_addr(struct pci_dev* pdev, - int offset, - u32 addr) +static int memrar_set_rar_addr(struct pci_dev *pdev, + int offset, + u32 addr) { /* * ======== The Lincroft Message Bus Interface ======== @@ -225,29 +226,29 @@ static int memrar_set_rar_addr(struct pci_dev* pdev, | (offset << 8) | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); - printk(KERN_WARNING "rar- offset to LNC MSG is %x\n",offset); + printk(KERN_WARNING "rar- offset to LNC MSG is %x\n", offset); if (addr == 0) return -EINVAL; /* Send the control message */ result = pci_write_config_dword(pdev, - LNC_MDR_OFFSET, - addr); + LNC_MDR_OFFSET, + addr); - printk(KERN_WARNING "rar- result from send ctl register is %x\n" - ,result); + printk(KERN_WARNING "rar- result from send ctl register is %x\n", + result); if (!result) result = pci_write_config_dword(pdev, - LNC_MCR_OFFSET, - message); + LNC_MCR_OFFSET, + message); printk(KERN_WARNING "rar- result from write data register is %x\n", - result); + result); printk(KERN_WARNING "rar- value read to data register is %x\n", - addr); + addr); if (result) return -1; @@ -284,35 +285,36 @@ static int memrar_init_rar_params(struct pci_dev *pdev) /* struct pci_dev *pdev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); */ if (pdev == NULL) - return -ENODEV; + return -ENODEV; for (i = offsets; i != end; ++i, ++n) { - if (memrar_get_rar_addr (pdev, - (*i).low, - &(rar_addr[n].low)) != 0 - || memrar_get_rar_addr (pdev, - (*i).high, - &(rar_addr[n].high)) != 0) { - result = -1; - break; - } + if (memrar_get_rar_addr(pdev, + (*i).low, + &(rar_addr[n].low)) != 0 + || memrar_get_rar_addr(pdev, + (*i).high, + &(rar_addr[n].high)) != 0) { + result = -1; + break; + } } /* Done accessing the device. */ /* pci_dev_put(pdev); */ if (result == 0) { - if(1) { - size_t z; - for (z = 0; z != MRST_NUM_RAR; ++z) { - printk(KERN_WARNING "rar - BRAR[%Zd] physical address low\n" - "\tlow: 0x%08x\n" - "\thigh: 0x%08x\n", - z, - rar_addr[z].low, - rar_addr[z].high); + if (1) { + size_t z; + for (z = 0; z != MRST_NUM_RAR; ++z) { + printk(KERN_WARNING + "rar - BRAR[%Zd] physical address low\n" + "\tlow: 0x%08x\n" + "\thigh: 0x%08x\n", + z, + rar_addr[z].low, + rar_addr[z].high); } - } + } } return result; @@ -321,7 +323,8 @@ static int memrar_init_rar_params(struct pci_dev *pdev) /* function that is activated on the successfull probe of the RAR device */ -static int __devinit rar_probe(struct pci_dev *pdev, const struct pci_device_id *ent) +static int __devinit rar_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) { /* error */ int error; @@ -347,7 +350,7 @@ static int __devinit rar_probe(struct pci_dev *pdev, const struct pci_device_id /* Initialize the RAR parameters, which have to be retrieved */ /* via the message bus service */ - error=memrar_init_rar_params(rar_dev); + error = memrar_init_rar_params(rar_dev); if (error) { DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, @@ -362,8 +365,8 @@ end_function: } /* - this function registers th driver to - the device subsystem( either PCI, USB, etc) + this function registers the driver to + the device subsystem (either PCI, USB, etc) */ static int __init rar_init_handler(void) { @@ -396,25 +399,20 @@ MODULE_LICENSE("GPL"); * The function returns a 0 upon success or a -1 if there is no RAR * facility on this system. */ -int get_rar_address(int rar_index,struct RAR_address_struct *addresses) +int get_rar_address(int rar_index, struct RAR_address_struct *addresses) { if (registered && (rar_index < 3) && (rar_index >= 0)) { - *addresses=rar_addr[rar_index]; + *addresses = rar_addr[rar_index]; /* strip off lock bit information */ addresses->low = addresses->low & 0xfffffff0; addresses->high = addresses->high & 0xfffffff0; return 0; - } - - else { + } else return -ENODEV; - } } - - EXPORT_SYMBOL(get_rar_address); -/* The lock_rar function is ued by other device drivers to lock an RAR. +/* The lock_rar function is used by other device drivers to lock an RAR. * once an RAR is locked, it stays locked until the next system reboot. * The function takes one parameter: * @@ -429,16 +427,14 @@ int lock_rar(int rar_index) { u32 working_addr; int result; -if (registered && (rar_index < 3) && (rar_index >= 0)) { - /* first make sure that lock bits are clear (this does lock) */ - working_addr=rar_addr[rar_index].low & 0xfffffff0; - /* now send that value to the register using the IPC */ - result=memrar_set_rar_addr(rar_dev,rar_index,working_addr); - return result; - } + if (registered && (rar_index < 3) && (rar_index >= 0)) { + /* first make sure that lock bits are clear (this does lock) */ + working_addr = rar_addr[rar_index].low & 0xfffffff0; -else { - return -ENODEV; - } + /* now send that value to the register using the IPC */ + result = memrar_set_rar_addr(rar_dev, rar_index, working_addr); + return result; + } else + return -ENODEV; } diff --git a/drivers/staging/rar/rar_driver.h b/drivers/staging/rar/rar_driver.h index 3690f984ff55..4172fbf36327 100644 --- a/drivers/staging/rar/rar_driver.h +++ b/drivers/staging/rar/rar_driver.h @@ -1,7 +1,7 @@ /* === RAR Physical Addresses === */ struct RAR_address_struct { - u32 low; - u32 high; + u32 low; + u32 high; }; /* The get_rar_address function is used by other device drivers @@ -19,10 +19,10 @@ struct RAR_address_struct { * The function returns a 0 upon success or a -1 if there is no RAR * facility on this system. */ -int get_rar_address(int rar_index,struct RAR_address_struct *addresses); +int get_rar_address(int rar_index, struct RAR_address_struct *addresses); -/* The lock_rar function is ued by other device drivers to lock an RAR. +/* The lock_rar function is used by other device drivers to lock an RAR. * once an RAR is locked, it stays locked until the next system reboot. * The function takes one parameter: * @@ -49,51 +49,41 @@ int lock_rar(int rar_index); /* debug macro without paramaters */ #define DEBUG_PRINT_0(DEBUG_LEVEL , info) \ -do \ -{ \ - if(DEBUG_LEVEL) \ - { \ - printk(KERN_WARNING info); \ - } \ -}while(0) +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info); \ + } \ +} while (0) /* debug macro with 1 paramater */ #define DEBUG_PRINT_1(DEBUG_LEVEL , info , param1) \ -do \ -{ \ - if(DEBUG_LEVEL) \ - { \ - printk(KERN_WARNING info , param1); \ - } \ -}while(0) +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info , param1); \ + } \ +} while (0) /* debug macro with 2 paramaters */ #define DEBUG_PRINT_2(DEBUG_LEVEL , info , param1, param2) \ -do \ -{ \ - if(DEBUG_LEVEL) \ - { \ - printk(KERN_WARNING info , param1, param2); \ - } \ -}while(0) +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info , param1, param2); \ + } \ +} while (0) /* debug macro with 3 paramaters */ #define DEBUG_PRINT_3(DEBUG_LEVEL , info , param1, param2 , param3) \ -do \ -{ \ - if(DEBUG_LEVEL) \ - { \ - printk(KERN_WARNING info , param1, param2 , param3); \ - } \ -}while(0) +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info , param1, param2 , param3); \ + } \ +} while (0) /* debug macro with 4 paramaters */ #define DEBUG_PRINT_4(DEBUG_LEVEL , info , param1, param2 , param3 , param4) \ -do \ -{ \ - if(DEBUG_LEVEL) \ - { \ - printk(KERN_WARNING info , param1, param2 , param3 , param4); \ - } \ -}while(0) +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info , param1, param2 , param3 , param4); \ + } \ +} while (0) -- cgit v1.2.3 From 274350fe401474d0c30cd10bbad74b5dbf34f4fe Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Thu, 31 Dec 2009 13:28:32 +0100 Subject: Staging: otus: 80211core: Fix &&/|| confusion This always evaluates to true. Signed-off-by: Roel Kluin Signed-off-by: Greg Kroah-Hartman --- drivers/staging/otus/80211core/cmmsta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/otus/80211core/cmmsta.c b/drivers/staging/otus/80211core/cmmsta.c index a11d559167b1..5c0dea7a3433 100644 --- a/drivers/staging/otus/80211core/cmmsta.c +++ b/drivers/staging/otus/80211core/cmmsta.c @@ -2808,7 +2808,7 @@ void zfStaProcessProbeReq(zdev_t* dev, zbuf_t* buf, u16_t* src) zmw_get_wlan_dev(dev); /* check mode : AP/IBSS */ - if ((wd->wlanMode != ZM_MODE_AP) || (wd->wlanMode != ZM_MODE_IBSS)) + if ((wd->wlanMode != ZM_MODE_AP) && (wd->wlanMode != ZM_MODE_IBSS)) { zm_msg0_mm(ZM_LV_3, "Ignore probe req"); return; -- cgit v1.2.3 From db376005ab4abe4a57fd96c8e007cf5d3b2e22bf Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 4 Jan 2010 16:24:47 +0000 Subject: Staging: sep: Fix build problems from header changes Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/sep/sep_driver.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/sep/sep_driver.c b/drivers/staging/sep/sep_driver.c index e7bc9ec63a8c..a5d65b9afaab 100644 --- a/drivers/staging/sep/sep_driver.c +++ b/drivers/staging/sep/sep_driver.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -273,8 +274,8 @@ static dma_addr_t sep_shared_virt_to_bus(struct sep_device *sep, void *virt_address) { dma_addr_t pa = sep->shared_bus + (virt_address - sep->shared_addr); - edbg("sep: virt to bus b %08llx v %p\n", - (unsigned long long)pa, virt_address); + edbg("sep: virt to bus b %08llx v %p\n", (unsigned long long) pa, + virt_address); return pa; } @@ -1771,7 +1772,7 @@ static struct sep_flow_context_t *sep_find_flow_context(struct sep_device *sep, static int sep_create_flow_dma_tables_handler(struct sep_device *sep, unsigned long arg) { - int error; + int error = -ENOENT; struct sep_driver_build_flow_table_t command_args; /* first table - output */ struct sep_lli_entry_t first_table_data; -- cgit v1.2.3 From 74e1cd4555c7b8d2fe9de657658f92f859427025 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 4 Jan 2010 16:25:02 +0000 Subject: Staging: sep: Fix use of legacy ioctl fop SEP doesn't need lock_kernel. Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/sep/sep_driver.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/sep/sep_driver.c b/drivers/staging/sep/sep_driver.c index a5d65b9afaab..92fa18655f87 100644 --- a/drivers/staging/sep/sep_driver.c +++ b/drivers/staging/sep/sep_driver.c @@ -2233,7 +2233,7 @@ static int sep_set_flow_id_handler(struct sep_device *sep, return error; } -static int sep_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) +static long sep_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { int error = 0; struct sep_device *sep = filp->private_data; @@ -2608,7 +2608,7 @@ static dev_t sep_devno; /* the files operations structure of the driver */ static struct file_operations sep_file_operations = { .owner = THIS_MODULE, - .ioctl = sep_ioctl, + .unlocked_ioctl = sep_ioctl, .poll = sep_poll, .open = sep_open, .release = sep_release, -- cgit v1.2.3 From 0c14c06cc18bc0d7f968d0bf1e531bcb8ced387d Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Tue, 5 Jan 2010 17:20:14 -0800 Subject: Staging: pohmelfs: Remove uses of NIPQUAD, use %pI4 Signed-off-by: Joe Perches Signed-off-by: Greg Kroah-Hartman --- drivers/staging/pohmelfs/inode.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/pohmelfs/inode.c b/drivers/staging/pohmelfs/inode.c index f69b7783027f..e286fd16fedc 100644 --- a/drivers/staging/pohmelfs/inode.c +++ b/drivers/staging/pohmelfs/inode.c @@ -1767,8 +1767,7 @@ static int pohmelfs_show_stats(struct seq_file *m, struct vfsmount *mnt) seq_printf(m, "%u ", ctl->idx); if (ctl->addr.sa_family == AF_INET) { struct sockaddr_in *sin = (struct sockaddr_in *)&st->ctl.addr; - /* seq_printf(m, "%pi4:%u", &sin->sin_addr.s_addr, ntohs(sin->sin_port)); */ - seq_printf(m, "%u.%u.%u.%u:%u", NIPQUAD(sin->sin_addr.s_addr), ntohs(sin->sin_port)); + seq_printf(m, "%pI4:%u", &sin->sin_addr.s_addr, ntohs(sin->sin_port)); } else if (ctl->addr.sa_family == AF_INET6) { struct sockaddr_in6 *sin = (struct sockaddr_in6 *)&st->ctl.addr; seq_printf(m, "%pi6:%u", &sin->sin6_addr, ntohs(sin->sin6_port)); -- cgit v1.2.3 From e3c0acf44d837d3095ab8222d3271f9ba0d3db44 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 8 Jan 2010 14:51:50 +0300 Subject: Staging: pohmelfs: avoid null dereference err_out_put is for when the netfs_trans_alloc() succeeded. Signed-off-by: Dan Carpenter Acked-by: Evgeniy Polyakov Signed-off-by: Greg Kroah-Hartman --- drivers/staging/pohmelfs/inode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/pohmelfs/inode.c b/drivers/staging/pohmelfs/inode.c index e286fd16fedc..6a978c8dd5d1 100644 --- a/drivers/staging/pohmelfs/inode.c +++ b/drivers/staging/pohmelfs/inode.c @@ -322,7 +322,7 @@ int pohmelfs_write_create_inode(struct pohmelfs_inode *pi) t = netfs_trans_alloc(psb, err + 1, 0, 0); if (!t) { err = -ENOMEM; - goto err_out_put; + goto err_out_exit; } t->complete = pohmelfs_write_inode_complete; t->private = igrab(inode); -- cgit v1.2.3 From 182374a0bddeef46769d2f8ab56fcccc433b96f3 Mon Sep 17 00:00:00 2001 From: Evgeniy Polyakov Date: Wed, 3 Feb 2010 01:04:30 +0300 Subject: Staging: Fixed pohmelfs regression because of per-bdi writeback. Since pohmelfs isn't tied to a single block device, it needs to setup a backing dev like nfs/btrfs/etc do. Signed-off-by: Jens Axboe Signed-off-by: Evgeniy Polyakov Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/staging/pohmelfs/inode.c | 20 ++++++++++++++++++-- drivers/staging/pohmelfs/netfs.h | 3 +++ 2 files changed, 21 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/pohmelfs/inode.c b/drivers/staging/pohmelfs/inode.c index 6a978c8dd5d1..eec3798eaf25 100644 --- a/drivers/staging/pohmelfs/inode.c +++ b/drivers/staging/pohmelfs/inode.c @@ -36,6 +36,7 @@ #define POHMELFS_MAGIC_NUM 0x504f482e static struct kmem_cache *pohmelfs_inode_cache; +static atomic_t psb_bdi_num = ATOMIC_INIT(0); /* * Removes inode from all trees, drops local name cache and removes all queued @@ -1331,6 +1332,8 @@ static void pohmelfs_put_super(struct super_block *sb) pohmelfs_crypto_exit(psb); pohmelfs_state_exit(psb); + bdi_destroy(&psb->bdi); + kfree(psb); sb->s_fs_info = NULL; } @@ -1814,11 +1817,22 @@ static int pohmelfs_fill_super(struct super_block *sb, void *data, int silent) if (!psb) goto err_out_exit; + err = bdi_init(&psb->bdi); + if (err) + goto err_out_free_sb; + + err = bdi_register(&psb->bdi, NULL, "pfs-%d", atomic_inc_return(&psb_bdi_num)); + if (err) { + bdi_destroy(&psb->bdi); + goto err_out_free_sb; + } + sb->s_fs_info = psb; sb->s_op = &pohmelfs_sb_ops; sb->s_magic = POHMELFS_MAGIC_NUM; sb->s_maxbytes = MAX_LFS_FILESIZE; sb->s_blocksize = PAGE_SIZE; + sb->s_bdi = &psb->bdi; psb->sb = sb; @@ -1862,11 +1876,11 @@ static int pohmelfs_fill_super(struct super_block *sb, void *data, int silent) err = pohmelfs_parse_options((char *) data, psb, 0); if (err) - goto err_out_free_sb; + goto err_out_free_bdi; err = pohmelfs_copy_crypto(psb); if (err) - goto err_out_free_sb; + goto err_out_free_bdi; err = pohmelfs_state_init(psb); if (err) @@ -1915,6 +1929,8 @@ err_out_state_exit: err_out_free_strings: kfree(psb->cipher_string); kfree(psb->hash_string); +err_out_free_bdi: + bdi_destroy(&psb->bdi); err_out_free_sb: kfree(psb); err_out_exit: diff --git a/drivers/staging/pohmelfs/netfs.h b/drivers/staging/pohmelfs/netfs.h index 623a07d29dea..01cba006e07a 100644 --- a/drivers/staging/pohmelfs/netfs.h +++ b/drivers/staging/pohmelfs/netfs.h @@ -18,6 +18,7 @@ #include #include +#include #define POHMELFS_CN_IDX 5 #define POHMELFS_CN_VAL 0 @@ -624,6 +625,8 @@ struct pohmelfs_sb { struct super_block *sb; + struct backing_dev_info bdi; + /* * Algorithm strings. */ -- cgit v1.2.3 From 9d4682d070e1f90f75cb27dd44d9cc7ab79577f1 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Wed, 6 Jan 2010 07:30:48 +0100 Subject: Staging: batman-adv: Update the README for mainline usage. The module now only compiles inside mainline, so remove the comments about different versions of the kernel it can be used with. Also update comments about building with debug enabled and how to use the VIS data now that it no longer natively outputs dot or JSON. Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/README | 50 ++++++++++----------------------------- 1 file changed, 13 insertions(+), 37 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/README b/drivers/staging/batman-adv/README index 2bedcbedb6af..7d666ad04359 100644 --- a/drivers/staging/batman-adv/README +++ b/drivers/staging/batman-adv/README @@ -1,4 +1,4 @@ -[state: 13-12-2009] +[state: 06-01-2010] BATMAN-ADV ---------- @@ -15,19 +15,6 @@ above B.A.T.M.A.N. Advanced, prominent examples are: IPv4, IPv6, DHCP, IPX. This is batman-advanced implemented as Linux kernel driver. It does not depend on any network (other) driver, and can be used on wifi as well as ethernet, vpn, etc ... (anything with ethernet-style layer 2). -It compiles against and should work with Linux 2.6.20 - 2.6.32. Supporting older -versions is not planned, but it's probably easy to backport it. If you work on a -backport, feel free to contact us. :-) - -COMPILE -------- -To compile against your currently installed kernel, just type: - -# make - -if you want to compile against some other kernel, use: - -# make KERNELPATH=/path/to/kernel USAGE ----- @@ -73,16 +60,9 @@ When configured as server, you can get a topology snapshot of your mesh: # cat /proc/net/batman-adv/vis -This output format is a graphviz formatted text file which can be -processed with graphviz-tools like dot. -The labels are similar/compatible to the ETX metric, 1.0 means perfect -connection (100%), 2.0 means 50%, 3.0 means 33% and so on. - -Alternatively, a JSON output format is available. The format can be set -using by writing either "dot_draw" or "json" into the vis_format file. -"dot_draw" is selected by default. - -echo "json" > /proc/net/batman-adv/vis_format +The output is in a generic raw format. Use the batctl tool (See below) +to convert this to other formats more suitable for graphing, eg +graphviz dot, or JSON data-interchange format. In very mobile scenarios, you might want to adjust the originator interval to a lower value. This will make the mesh more responsive to @@ -110,15 +90,11 @@ dmesg | grep batman-adv When investigating problems with your mesh network it is sometimes necessary to see more detail debug messages. This must be enabled when -compiling the batman-adv module. When building batman-adv as part of -kernel, use "make menuconfig" and enable the option -"B.A.T.M.A.N. debugging". When compiling outside of the kernel tree it -is necessary to edit the file Makefile.kbuild and uncomment the line - -#EXTRA_CFLAGS += -DCONFIG_BATMAN_ADV_DEBUG +compiling the batman-adv module. Use "make menuconfig" and enable the +option "B.A.T.M.A.N. debugging". The additional debug output is by default disabled. It can be enabled -either at kernel modules load time or during run time. To enable debug +either at kernel module load time or during run time. To enable debug output at module load time, add the module parameter debug=. can take one of four values. @@ -147,12 +123,12 @@ to see the debug messages. BATCTL ------ -B.A.T.M.A.N. advanced operates on layer 2 and thus all hosts partici- -pating in the virtual switch are completely transparent for all proto- -cols above layer 2. Therefore the common diagnosis tools do not work as -expected. To overcome these problems batctl was created. At the moment -the batctl contains ping, traceroute, tcpdump and interfaces to the -kernel module settings. +B.A.T.M.A.N. advanced operates on layer 2 and thus all hosts +participating in the virtual switch are completely transparent for all +protocols above layer 2. Therefore the common diagnosis tools do not +work as expected. To overcome these problems batctl was created. At +the moment the batctl contains ping, traceroute, tcpdump and +interfaces to the kernel module settings. For more information, please see the manpage (man batctl). -- cgit v1.2.3 From 267c39c918cd0c239148a281d51693f47d2e1e54 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Wed, 6 Jan 2010 23:27:47 +0100 Subject: Staging: v56655: add missing parentheses (in comment) `!' has a higher precedence than `&' so parentheses are required. Signed-off-by: Roel Kluin Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vt6655/iwctl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/vt6655/iwctl.c b/drivers/staging/vt6655/iwctl.c index 108830ff3b32..78b49830a255 100644 --- a/drivers/staging/vt6655/iwctl.c +++ b/drivers/staging/vt6655/iwctl.c @@ -1472,7 +1472,7 @@ if((wrq->flags & IW_ENCODE_DISABLED)==0){ if ( index < 4 ) { pDevice->byKeyIndex = index; } - else if(!wrq->flags & IW_ENCODE_MODE) { + else if(!(wrq->flags & IW_ENCODE_MODE)) { rc = -EINVAL; return rc; } -- cgit v1.2.3 From c424d46fdc79df201707fe815aa8480751918025 Mon Sep 17 00:00:00 2001 From: Alexander Beregalov Date: Thu, 7 Jan 2010 03:21:48 +0300 Subject: staging: cx25821: avoid NULL pointer dereference Assign dev only if fh is not NULL. Signed-off-by: Alexander Beregalov Signed-off-by: Greg Kroah-Hartman --- drivers/staging/cx25821/cx25821-audups11.c | 3 ++- drivers/staging/cx25821/cx25821-video.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/cx25821/cx25821-audups11.c b/drivers/staging/cx25821/cx25821-audups11.c index 89c8fe2997fa..46c7f78bb972 100644 --- a/drivers/staging/cx25821/cx25821-audups11.c +++ b/drivers/staging/cx25821/cx25821-audups11.c @@ -343,10 +343,11 @@ static int vidioc_s_ctrl(struct file *file, void *priv, struct v4l2_control *ctl) { struct cx25821_fh *fh = priv; - struct cx25821_dev *dev = fh->dev; + struct cx25821_dev *dev; int err; if (fh) { + dev = fh->dev; err = v4l2_prio_check(&dev->prio, &fh->prio); if (0 != err) return err; diff --git a/drivers/staging/cx25821/cx25821-video.c b/drivers/staging/cx25821/cx25821-video.c index 6e710ae067ad..8cd3986d2e5c 100644 --- a/drivers/staging/cx25821/cx25821-video.c +++ b/drivers/staging/cx25821/cx25821-video.c @@ -963,10 +963,11 @@ int cx25821_set_freq(struct cx25821_dev *dev, struct v4l2_frequency *f) int vidioc_s_frequency(struct file *file, void *priv, struct v4l2_frequency *f) { struct cx25821_fh *fh = priv; - struct cx25821_dev *dev = fh->dev; + struct cx25821_dev *dev; int err; if (fh) { + dev = fh->dev; err = v4l2_prio_check(&dev->prio, &fh->prio); if (0 != err) return err; -- cgit v1.2.3 From 0df28be06e08b9a53c26a53974bf3afea4928b3e Mon Sep 17 00:00:00 2001 From: Peter Huewe Date: Thu, 7 Jan 2010 19:57:36 +0100 Subject: Staging: asus_oled: Add NULL test for kmalloc This patch adds a NULL test to check wether kmalloc was successful or not. Signed-off-by: Peter Huewe Signed-off-by: Greg Kroah-Hartman --- drivers/staging/asus_oled/asus_oled.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/asus_oled/asus_oled.c b/drivers/staging/asus_oled/asus_oled.c index 0c1fb0d618a5..c597fb27bd53 100644 --- a/drivers/staging/asus_oled/asus_oled.c +++ b/drivers/staging/asus_oled/asus_oled.c @@ -430,6 +430,11 @@ static ssize_t odev_set_picture(struct asus_oled_dev *odev, kfree(odev->buf); odev->buf = kmalloc(odev->buf_size, GFP_KERNEL); + if (odev->buf == NULL) { + odev->buf_size = 0; + printk(ASUS_OLED_ERROR "Out of memory!\n"); + return -ENOMEM; + } memset(odev->buf, 0xff, odev->buf_size); -- cgit v1.2.3 From 95702ef05b9b6554c2669bdb9a6121af9f034171 Mon Sep 17 00:00:00 2001 From: Peter Huewe Date: Fri, 8 Jan 2010 09:09:12 +0100 Subject: Staging: otus: Add select WEXT_PRIV to Kconfig to prevent build failure Without WEXT_PRIV set the driver fails to build due to unknown fields in the iw_handler_def struct. Those fields are enclosed in WEXT_PRIV conditionals in the prototype of iw_handler_def in include/net/iw_handler.h Signed-off-by: Peter Huewe Acked-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/otus/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/otus/Kconfig b/drivers/staging/otus/Kconfig index f6cc2625e341..e9181340bef1 100644 --- a/drivers/staging/otus/Kconfig +++ b/drivers/staging/otus/Kconfig @@ -1,6 +1,8 @@ config OTUS tristate "Atheros OTUS 802.11n USB wireless support" depends on USB && WLAN && MAC80211 + select WIRELESS_EXT + select WEXT_PRIV default N ---help--- Enable support for Atheros 802.11n USB hardware: -- cgit v1.2.3 From 733acf902fbafb6571fce45ee77b1516aaae1bc6 Mon Sep 17 00:00:00 2001 From: Peter Huewe Date: Fri, 8 Jan 2010 09:10:13 +0100 Subject: Staging: rtl8192u: Add select WEXT_PRIV to Kconfig to prevent build failure Without WEXT_PRIV set the driver fails to build due to unknown fields in the iw_handler_def struct. Those fields are enclosed in WEXT_PRIV conditionals in the prototype of iw_handler_def in include/net/iw_handler.h Signed-off-by: Peter Huewe Acked-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192u/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192u/Kconfig b/drivers/staging/rtl8192u/Kconfig index 9913ab8fb359..0439c90b4163 100644 --- a/drivers/staging/rtl8192u/Kconfig +++ b/drivers/staging/rtl8192u/Kconfig @@ -1,6 +1,7 @@ config RTL8192U tristate "RealTek RTL8192U Wireless LAN NIC driver" depends on PCI && WLAN && USB - depends on WIRELESS_EXT + select WIRELESS_EXT + select WEXT_PRIV default N ---help--- -- cgit v1.2.3 From 8a8e29752dfdba014b866d3c587d3409e57263dd Mon Sep 17 00:00:00 2001 From: Peter Huewe Date: Thu, 7 Jan 2010 21:21:35 +0100 Subject: Staging: wlan-ng: Add select WEXT_PRIV to Kconfig to prevent build failure Without WEXT_PRIV set the p80211wext.c fails to build due to unknown fields in the iw_handler_def struct. Those fields are enclosed in WEXT_PRIV conditionals in the prototype of iw_handler_def in include/net/iw_handler.h Signed-off-by: Peter Huewe Acked-by: Simon Horman Cc: stable [2.6.33 only] Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlan-ng/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/staging/wlan-ng/Kconfig b/drivers/staging/wlan-ng/Kconfig index 704ebd26e628..82fcc1665e92 100644 --- a/drivers/staging/wlan-ng/Kconfig +++ b/drivers/staging/wlan-ng/Kconfig @@ -2,6 +2,7 @@ config PRISM2_USB tristate "Prism2.5/3 USB driver" depends on WLAN && USB select WIRELESS_EXT + select WEXT_PRIV default n ---help--- This is the wlan-ng prism 2.5/3 USB driver for a wide range of -- cgit v1.2.3 From 88d43000098017d93d9bb2f88d33950e6c7a6bf4 Mon Sep 17 00:00:00 2001 From: Jarod Wilson Date: Thu, 7 Jan 2010 18:35:58 -0500 Subject: staging: crystalhd: add missing fixes for userspace lib build I somehow managed to not actually include these two fixes in the submission that was committed to the staging tree. libcrystalhd should eventually be built against the kernel-provided header, and needs the stdint.h include. The VOID bit is to keep things in sync with the Mac OS X driver and library that Scott Davilla is also working on. Signed-off-by: Scott Davilla Signed-off-by: Jarod Wilson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/crystalhd/bc_dts_types.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/crystalhd/bc_dts_types.h b/drivers/staging/crystalhd/bc_dts_types.h index e073d7450c16..ac0c81717385 100644 --- a/drivers/staging/crystalhd/bc_dts_types.h +++ b/drivers/staging/crystalhd/bc_dts_types.h @@ -25,6 +25,10 @@ #ifndef _BC_DTS_TYPES_H_ #define _BC_DTS_TYPES_H_ +#ifdef __LINUX_USER__ // Don't include these for KERNEL.. +#include +#endif + #if defined(_WIN64) || defined(_WIN32) typedef uint32_t U32; typedef int32_t S32; @@ -62,7 +66,9 @@ typedef int BOOL; typedef uint32_t ULONG; typedef int32_t LONG; typedef void *HANDLE; +#ifndef VOID typedef void VOID; +#endif typedef void *LPVOID; typedef uint32_t DWORD; typedef uint32_t UINT32; -- cgit v1.2.3 From 90d49b4f32c243215c0620162e6cae6af980047c Mon Sep 17 00:00:00 2001 From: Jarod Wilson Date: Thu, 7 Jan 2010 18:37:36 -0500 Subject: staging: crystalhd: trim register defines We don't actually need most of the register defines to build, and most of the ones we don't need aren't currently interesting. We'll leave a full copy of all of them in libcrystalhd's source, and only include what we need and/or think might be interesting in the driver. Signed-off-by: Jarod Wilson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/crystalhd/bcm_70012_regs.h | 12144 +-------------------------- 1 file changed, 301 insertions(+), 11843 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/crystalhd/bcm_70012_regs.h b/drivers/staging/crystalhd/bcm_70012_regs.h index b3b255769641..6922f54e432f 100644 --- a/drivers/staging/crystalhd/bcm_70012_regs.h +++ b/drivers/staging/crystalhd/bcm_70012_regs.h @@ -203,21 +203,6 @@ ***************************************************************************/ #define PCIE_TL_TL_CONTROL 0x00000400 /* TL_CONTROL Register */ #define PCIE_TL_TRANSACTION_CONFIGURATION 0x00000404 /* TRANSACTION_CONFIGURATION Register */ -#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00000408 /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ -#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 0x0000040c /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 Register */ -#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00000410 /* DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ -#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 0x00000414 /* DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 Register */ -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC 0x00000418 /* DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC Register */ -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC 0x0000041c /* DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC Register */ -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC 0x00000420 /* READ_DMA_SPLIT_IDS_DIAGNOSTIC Register */ -#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC 0x00000424 /* READ_DMA_SPLIT_LENGTH_DIAGNOSTIC Register */ -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC 0x0000043c /* XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC Register */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC 0x00000458 /* DMA_COMPLETION_MISC__DIAGNOSTIC Register */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC 0x0000045c /* SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC Register */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC 0x00000460 /* SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC Register */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC 0x00000464 /* SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC Register */ -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO 0x00000468 /* TL_BUS_NO_DEV__NO__FUNC__NO Register */ -#define PCIE_TL_TL_DEBUG 0x0000046c /* TL_DEBUG Register */ /**************************************************************************** @@ -225,47 +210,6 @@ ***************************************************************************/ #define PCIE_DLL_DATA_LINK_CONTROL 0x00000500 /* DATA_LINK_CONTROL Register */ #define PCIE_DLL_DATA_LINK_STATUS 0x00000504 /* DATA_LINK_STATUS Register */ -#define PCIE_DLL_DATA_LINK_ATTENTION 0x00000508 /* DATA_LINK_ATTENTION Register */ -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK 0x0000050c /* DATA_LINK_ATTENTION_MASK Register */ -#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000510 /* NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ -#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000514 /* ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ -#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000518 /* PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ -#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG 0x0000051c /* RECEIVE_SEQUENCE_NUMBER_DEBUG Register */ -#define PCIE_DLL_DATA_LINK_REPLAY 0x00000520 /* DATA_LINK_REPLAY Register */ -#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT 0x00000524 /* DATA_LINK_ACK_TIMEOUT Register */ -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD 0x00000528 /* POWER_MANAGEMENT_THRESHOLD Register */ -#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG 0x0000052c /* RETRY_BUFFER_WRITE_POINTER_DEBUG Register */ -#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG 0x00000530 /* RETRY_BUFFER_READ_POINTER_DEBUG Register */ -#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG 0x00000534 /* RETRY_BUFFER_PURGED_POINTER_DEBUG Register */ -#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT 0x00000538 /* RETRY_BUFFER_READ_WRITE_DEBUG_PORT Register */ -#define PCIE_DLL_ERROR_COUNT_THRESHOLD 0x0000053c /* ERROR_COUNT_THRESHOLD Register */ -#define PCIE_DLL_TL_ERROR_COUNTER 0x00000540 /* TL_ERROR_COUNTER Register */ -#define PCIE_DLL_DLLP_ERROR_COUNTER 0x00000544 /* DLLP_ERROR_COUNTER Register */ -#define PCIE_DLL_NAK_RECEIVED_COUNTER 0x00000548 /* NAK_RECEIVED_COUNTER Register */ -#define PCIE_DLL_DATA_LINK_TEST 0x0000054c /* DATA_LINK_TEST Register */ -#define PCIE_DLL_PACKET_BIST 0x00000550 /* PACKET_BIST Register */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL 0x00000554 /* LINK_PCIE_1_1_CONTROL Register */ - - -/**************************************************************************** - * BCM70012_TGT_TOP_PCIE_PHY - ***************************************************************************/ -#define PCIE_PHY_PHY_MODE 0x00000600 /* TYPE_PHY_MODE Register */ -#define PCIE_PHY_PHY_LINK_STATUS 0x00000604 /* TYPE_PHY_LINK_STATUS Register */ -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL 0x00000608 /* TYPE_PHY_LINK_LTSSM_CONTROL Register */ -#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER 0x0000060c /* TYPE_PHY_LINK_TRAINING_LINK_NUMBER Register */ -#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER 0x00000610 /* TYPE_PHY_LINK_TRAINING_LANE_NUMBER Register */ -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS 0x00000614 /* TYPE_PHY_LINK_TRAINING_N_FTS Register */ -#define PCIE_PHY_PHY_ATTENTION 0x00000618 /* TYPE_PHY_ATTENTION Register */ -#define PCIE_PHY_PHY_ATTENTION_MASK 0x0000061c /* TYPE_PHY_ATTENTION_MASK Register */ -#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER 0x00000620 /* TYPE_PHY_RECEIVE_ERROR_COUNTER Register */ -#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER 0x00000624 /* TYPE_PHY_RECEIVE_FRAMING_ERROR_COUNTER Register */ -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD 0x00000628 /* TYPE_PHY_RECEIVE_ERROR_THRESHOLD Register */ -#define PCIE_PHY_PHY_TEST_CONTROL 0x0000062c /* TYPE_PHY_TEST_CONTROL Register */ -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE 0x00000630 /* TYPE_PHY_SERDES_CONTROL_OVERRIDE Register */ -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE 0x00000634 /* TYPE_PHY_TIMING_PARAMETER_OVERRIDE Register */ -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES 0x00000638 /* TYPE_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES Register */ -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES 0x0000063c /* TYPE_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES Register */ /**************************************************************************** @@ -280,60 +224,6 @@ #define INTR_EOI_CTRL 0x00000720 /* End of interrupt control register */ -/**************************************************************************** - * BCM70012_TGT_TOP_MDIO - ***************************************************************************/ -#define MDIO_CTRL0 0x00000730 /* PCIE Serdes MDIO Control Register 0 */ -#define MDIO_CTRL1 0x00000734 /* PCIE Serdes MDIO Control Register 1 */ -#define MDIO_CTRL2 0x00000738 /* PCIE Serdes MDIO Control Register 2 */ - - -/**************************************************************************** - * BCM70012_TGT_TOP_TGT_RGR_BRIDGE - ***************************************************************************/ -#define TGT_RGR_BRIDGE_REVISION 0x00000740 /* PCIE RGR Bridge Revision Register */ -#define TGT_RGR_BRIDGE_CTRL 0x00000744 /* RGR Bridge Control Register */ -#define TGT_RGR_BRIDGE_RBUS_TIMER 0x00000748 /* RGR Bridge RBUS Timer Register */ -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0 0x0000074c /* RGR Bridge Spare Software Reset 0 Register */ -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1 0x00000750 /* RGR Bridge Spare Software Reset 1 Register */ - - -/**************************************************************************** - * BCM70012_I2C_TOP_I2C - ***************************************************************************/ -#define I2C_CHIP_ADDRESS 0x00000800 /* I2C Chip Address And Read/Write Control */ -#define I2C_DATA_IN0 0x00000804 /* I2C Write Data Byte 0 */ -#define I2C_DATA_IN1 0x00000808 /* I2C Write Data Byte 1 */ -#define I2C_DATA_IN2 0x0000080c /* I2C Write Data Byte 2 */ -#define I2C_DATA_IN3 0x00000810 /* I2C Write Data Byte 3 */ -#define I2C_DATA_IN4 0x00000814 /* I2C Write Data Byte 4 */ -#define I2C_DATA_IN5 0x00000818 /* I2C Write Data Byte 5 */ -#define I2C_DATA_IN6 0x0000081c /* I2C Write Data Byte 6 */ -#define I2C_DATA_IN7 0x00000820 /* I2C Write Data Byte 7 */ -#define I2C_CNT_REG 0x00000824 /* I2C Transfer Count Register */ -#define I2C_CTL_REG 0x00000828 /* I2C Control Register */ -#define I2C_IIC_ENABLE 0x0000082c /* I2C Read/Write Enable And Interrupt */ -#define I2C_DATA_OUT0 0x00000830 /* I2C Read Data Byte 0 */ -#define I2C_DATA_OUT1 0x00000834 /* I2C Read Data Byte 1 */ -#define I2C_DATA_OUT2 0x00000838 /* I2C Read Data Byte 2 */ -#define I2C_DATA_OUT3 0x0000083c /* I2C Read Data Byte 3 */ -#define I2C_DATA_OUT4 0x00000840 /* I2C Read Data Byte 4 */ -#define I2C_DATA_OUT5 0x00000844 /* I2C Read Data Byte 5 */ -#define I2C_DATA_OUT6 0x00000848 /* I2C Read Data Byte 6 */ -#define I2C_DATA_OUT7 0x0000084c /* I2C Read Data Byte 7 */ -#define I2C_CTLHI_REG 0x00000850 /* I2C Control Register */ -#define I2C_SCL_PARAM 0x00000854 /* I2C SCL Parameter Register */ - - -/**************************************************************************** - * BCM70012_I2C_TOP_I2C_GR_BRIDGE - ***************************************************************************/ -#define I2C_GR_BRIDGE_REVISION 0x00000be0 /* GR Bridge Revision */ -#define I2C_GR_BRIDGE_CTRL 0x00000be4 /* GR Bridge Control Register */ -#define I2C_GR_BRIDGE_SPARE_SW_RESET_0 0x00000be8 /* GR Bridge Software Reset 0 Register */ -#define I2C_GR_BRIDGE_SPARE_SW_RESET_1 0x00000bec /* GR Bridge Software Reset 1 Register */ - - /**************************************************************************** * BCM70012_MISC_TOP_MISC1 ***************************************************************************/ @@ -420,87 +310,6 @@ #define GISB_ARBITER_SCRATCH 0x00000f04 /* GISB ARBITER Scratch Register */ #define GISB_ARBITER_REQ_MASK 0x00000f08 /* GISB ARBITER Master Request Mask Register */ #define GISB_ARBITER_TIMER 0x00000f0c /* GISB ARBITER Timer Value Register */ -#define GISB_ARBITER_BP_CTRL 0x00000f10 /* GISB ARBITER Breakpoint Control Register */ -#define GISB_ARBITER_BP_CAP_CLR 0x00000f14 /* GISB ARBITER Breakpoint Capture Clear Register */ -#define GISB_ARBITER_BP_START_ADDR_0 0x00000f18 /* GISB ARBITER Breakpoint Start Address 0 Register */ -#define GISB_ARBITER_BP_END_ADDR_0 0x00000f1c /* GISB ARBITER Breakpoint End Address 0 Register */ -#define GISB_ARBITER_BP_READ_0 0x00000f20 /* GISB ARBITER Breakpoint Master Read Control 0 Register */ -#define GISB_ARBITER_BP_WRITE_0 0x00000f24 /* GISB ARBITER Breakpoint Master Write Control 0 Register */ -#define GISB_ARBITER_BP_ENABLE_0 0x00000f28 /* GISB ARBITER Breakpoint Enable 0 Register */ -#define GISB_ARBITER_BP_START_ADDR_1 0x00000f2c /* GISB ARBITER Breakpoint Start Address 1 Register */ -#define GISB_ARBITER_BP_END_ADDR_1 0x00000f30 /* GISB ARBITER Breakpoint End Address 1 Register */ -#define GISB_ARBITER_BP_READ_1 0x00000f34 /* GISB ARBITER Breakpoint Master Read Control 1 Register */ -#define GISB_ARBITER_BP_WRITE_1 0x00000f38 /* GISB ARBITER Breakpoint Master Write Control 1 Register */ -#define GISB_ARBITER_BP_ENABLE_1 0x00000f3c /* GISB ARBITER Breakpoint Enable 1 Register */ -#define GISB_ARBITER_BP_START_ADDR_2 0x00000f40 /* GISB ARBITER Breakpoint Start Address 2 Register */ -#define GISB_ARBITER_BP_END_ADDR_2 0x00000f44 /* GISB ARBITER Breakpoint End Address 2 Register */ -#define GISB_ARBITER_BP_READ_2 0x00000f48 /* GISB ARBITER Breakpoint Master Read Control 2 Register */ -#define GISB_ARBITER_BP_WRITE_2 0x00000f4c /* GISB ARBITER Breakpoint Master Write Control 2 Register */ -#define GISB_ARBITER_BP_ENABLE_2 0x00000f50 /* GISB ARBITER Breakpoint Enable 2 Register */ -#define GISB_ARBITER_BP_START_ADDR_3 0x00000f54 /* GISB ARBITER Breakpoint Start Address 3 Register */ -#define GISB_ARBITER_BP_END_ADDR_3 0x00000f58 /* GISB ARBITER Breakpoint End Address 3 Register */ -#define GISB_ARBITER_BP_READ_3 0x00000f5c /* GISB ARBITER Breakpoint Master Read Control 3 Register */ -#define GISB_ARBITER_BP_WRITE_3 0x00000f60 /* GISB ARBITER Breakpoint Master Write Control 3 Register */ -#define GISB_ARBITER_BP_ENABLE_3 0x00000f64 /* GISB ARBITER Breakpoint Enable 3 Register */ -#define GISB_ARBITER_BP_START_ADDR_4 0x00000f68 /* GISB ARBITER Breakpoint Start Address 4 Register */ -#define GISB_ARBITER_BP_END_ADDR_4 0x00000f6c /* GISB ARBITER Breakpoint End Address 4 Register */ -#define GISB_ARBITER_BP_READ_4 0x00000f70 /* GISB ARBITER Breakpoint Master Read Control 4 Register */ -#define GISB_ARBITER_BP_WRITE_4 0x00000f74 /* GISB ARBITER Breakpoint Master Write Control 4 Register */ -#define GISB_ARBITER_BP_ENABLE_4 0x00000f78 /* GISB ARBITER Breakpoint Enable 4 Register */ -#define GISB_ARBITER_BP_START_ADDR_5 0x00000f7c /* GISB ARBITER Breakpoint Start Address 5 Register */ -#define GISB_ARBITER_BP_END_ADDR_5 0x00000f80 /* GISB ARBITER Breakpoint End Address 5 Register */ -#define GISB_ARBITER_BP_READ_5 0x00000f84 /* GISB ARBITER Breakpoint Master Read Control 5 Register */ -#define GISB_ARBITER_BP_WRITE_5 0x00000f88 /* GISB ARBITER Breakpoint Master Write Control 5 Register */ -#define GISB_ARBITER_BP_ENABLE_5 0x00000f8c /* GISB ARBITER Breakpoint Enable 5 Register */ -#define GISB_ARBITER_BP_START_ADDR_6 0x00000f90 /* GISB ARBITER Breakpoint Start Address 6 Register */ -#define GISB_ARBITER_BP_END_ADDR_6 0x00000f94 /* GISB ARBITER Breakpoint End Address 6 Register */ -#define GISB_ARBITER_BP_READ_6 0x00000f98 /* GISB ARBITER Breakpoint Master Read Control 6 Register */ -#define GISB_ARBITER_BP_WRITE_6 0x00000f9c /* GISB ARBITER Breakpoint Master Write Control 6 Register */ -#define GISB_ARBITER_BP_ENABLE_6 0x00000fa0 /* GISB ARBITER Breakpoint Enable 6 Register */ -#define GISB_ARBITER_BP_START_ADDR_7 0x00000fa4 /* GISB ARBITER Breakpoint Start Address 7 Register */ -#define GISB_ARBITER_BP_END_ADDR_7 0x00000fa8 /* GISB ARBITER Breakpoint End Address 7 Register */ -#define GISB_ARBITER_BP_READ_7 0x00000fac /* GISB ARBITER Breakpoint Master Read Control 7 Register */ -#define GISB_ARBITER_BP_WRITE_7 0x00000fb0 /* GISB ARBITER Breakpoint Master Write Control 7 Register */ -#define GISB_ARBITER_BP_ENABLE_7 0x00000fb4 /* GISB ARBITER Breakpoint Enable 7 Register */ -#define GISB_ARBITER_BP_CAP_ADDR 0x00000fb8 /* GISB ARBITER Breakpoint Capture Address Register */ -#define GISB_ARBITER_BP_CAP_DATA 0x00000fbc /* GISB ARBITER Breakpoint Capture Data Register */ -#define GISB_ARBITER_BP_CAP_STATUS 0x00000fc0 /* GISB ARBITER Breakpoint Capture Status Register */ -#define GISB_ARBITER_BP_CAP_MASTER 0x00000fc4 /* GISB ARBITER Breakpoint Capture GISB MASTER Register */ -#define GISB_ARBITER_ERR_CAP_CLR 0x00000fc8 /* GISB ARBITER Error Capture Clear Register */ -#define GISB_ARBITER_ERR_CAP_ADDR 0x00000fcc /* GISB ARBITER Error Capture Address Register */ -#define GISB_ARBITER_ERR_CAP_DATA 0x00000fd0 /* GISB ARBITER Error Capture Data Register */ -#define GISB_ARBITER_ERR_CAP_STATUS 0x00000fd4 /* GISB ARBITER Error Capture Status Register */ -#define GISB_ARBITER_ERR_CAP_MASTER 0x00000fd8 /* GISB ARBITER Error Capture GISB MASTER Register */ - - -/**************************************************************************** - * BCM70012_MISC_TOP_MISC_GR_BRIDGE - ***************************************************************************/ -#define MISC_GR_BRIDGE_REVISION 0x00000fe0 /* GR Bridge Revision */ -#define MISC_GR_BRIDGE_CTRL 0x00000fe4 /* GR Bridge Control Register */ -#define MISC_GR_BRIDGE_SPARE_SW_RESET_0 0x00000fe8 /* GR Bridge Software Reset 0 Register */ -#define MISC_GR_BRIDGE_SPARE_SW_RESET_1 0x00000fec /* GR Bridge Software Reset 1 Register */ - - -/**************************************************************************** - * BCM70012_DBU_TOP_DBU - ***************************************************************************/ -#define DBU_DBU_CMD 0x00001000 /* DBU (Debug UART) command register */ -#define DBU_DBU_STATUS 0x00001004 /* DBU (Debug UART) status register */ -#define DBU_DBU_CONFIG 0x00001008 /* DBU (Debug UART) configuration register */ -#define DBU_DBU_TIMING 0x0000100c /* DBU (Debug UART) timing register */ -#define DBU_DBU_RXDATA 0x00001010 /* DBU (Debug UART) recieve data register */ -#define DBU_DBU_TXDATA 0x00001014 /* DBU (Debug UART) transmit data register */ - - -/**************************************************************************** - * BCM70012_DBU_TOP_DBU_RGR_BRIDGE - ***************************************************************************/ -#define DBU_RGR_BRIDGE_REVISION 0x000013e0 /* RGR Bridge Revision */ -#define DBU_RGR_BRIDGE_CTRL 0x000013e4 /* RGR Bridge Control Register */ -#define DBU_RGR_BRIDGE_RBUS_TIMER 0x000013e8 /* RGR Bridge RBUS Timer Register */ -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0 0x000013ec /* RGR Bridge Software Reset 0 Register */ -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1 0x000013f0 /* RGR Bridge Software Reset 1 Register */ /**************************************************************************** @@ -532,15 +341,6 @@ #define OTP_DATA_OUTPUT 0x0000145c /* Data Output Register */ -/**************************************************************************** - * BCM70012_OTP_TOP_OTP_GR_BRIDGE - ***************************************************************************/ -#define OTP_GR_BRIDGE_REVISION 0x000017e0 /* GR Bridge Revision */ -#define OTP_GR_BRIDGE_CTRL 0x000017e4 /* GR Bridge Control Register */ -#define OTP_GR_BRIDGE_SPARE_SW_RESET_0 0x000017e8 /* GR Bridge Software Reset 0 Register */ -#define OTP_GR_BRIDGE_SPARE_SW_RESET_1 0x000017ec /* GR Bridge Software Reset 1 Register */ - - /**************************************************************************** * BCM70012_AES_TOP_AES ***************************************************************************/ @@ -554,16 +354,6 @@ #define AES_EEPROM_DATA_3 0x0000181c /* AES EEPROM Data Register 3 */ -/**************************************************************************** - * BCM70012_AES_TOP_AES_RGR_BRIDGE - ***************************************************************************/ -#define AES_RGR_BRIDGE_REVISION 0x00001be0 /* RGR Bridge Revision */ -#define AES_RGR_BRIDGE_CTRL 0x00001be4 /* RGR Bridge Control Register */ -#define AES_RGR_BRIDGE_RBUS_TIMER 0x00001be8 /* RGR Bridge RBUS Timer Register */ -#define AES_RGR_BRIDGE_SPARE_SW_RESET_0 0x00001bec /* RGR Bridge Software Reset 0 Register */ -#define AES_RGR_BRIDGE_SPARE_SW_RESET_1 0x00001bf0 /* RGR Bridge Software Reset 1 Register */ - - /**************************************************************************** * BCM70012_DCI_TOP_DCI ***************************************************************************/ @@ -583,11712 +373,380 @@ /**************************************************************************** - * BCM70012_DCI_TOP_DCI_RGR_BRIDGE - ***************************************************************************/ -#define DCI_RGR_BRIDGE_REVISION 0x00001fe0 /* RGR Bridge Revision */ -#define DCI_RGR_BRIDGE_CTRL 0x00001fe4 /* RGR Bridge Control Register */ -#define DCI_RGR_BRIDGE_RBUS_TIMER 0x00001fe8 /* RGR Bridge RBUS Timer Register */ -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0 0x00001fec /* RGR Bridge Software Reset 0 Register */ -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1 0x00001ff0 /* RGR Bridge Software Reset 1 Register */ - - -/**************************************************************************** - * BCM70012_CCE_TOP_CCE_RGR_BRIDGE - ***************************************************************************/ -#define CCE_RGR_BRIDGE_REVISION 0x000023e0 /* RGR Bridge Revision */ -#define CCE_RGR_BRIDGE_CTRL 0x000023e4 /* RGR Bridge Control Register */ -#define CCE_RGR_BRIDGE_RBUS_TIMER 0x000023e8 /* RGR Bridge RBUS Timer Register */ -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0 0x000023ec /* RGR Bridge Software Reset 0 Register */ -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1 0x000023f0 /* RGR Bridge Software Reset 1 Register */ - - -/**************************************************************************** - * BCM70012_TGT_TOP_PCIE_CFG - ***************************************************************************/ -/**************************************************************************** - * PCIE_CFG :: DEVICE_VENDOR_ID + * BCM70012_TGT_TOP_INTR ***************************************************************************/ -/* PCIE_CFG :: DEVICE_VENDOR_ID :: DEVICE_ID [31:16] */ -#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_MASK 0xffff0000 -#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_ALIGN 0 -#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_BITS 16 -#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT 16 - -/* PCIE_CFG :: DEVICE_VENDOR_ID :: VENDOR_ID [15:00] */ -#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_MASK 0x0000ffff -#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_ALIGN 0 -#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_BITS 16 -#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT 0 - - /**************************************************************************** - * PCIE_CFG :: STATUS_COMMAND + * INTR :: INTR_STATUS ***************************************************************************/ -/* PCIE_CFG :: STATUS_COMMAND :: DETECTED_PARITY_ERROR [31:31] */ -#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_MASK 0x80000000 -#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_SHIFT 31 - -/* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_SYSTEM_ERROR [30:30] */ -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_MASK 0x40000000 -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_SHIFT 30 - -/* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_MASTER_ABORT [29:29] */ -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_MASK 0x20000000 -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_SHIFT 29 - -/* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_TARGET_ABORT [28:28] */ -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_MASK 0x10000000 -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_SHIFT 28 - -/* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_TARGET_ABORT [27:27] */ -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_MASK 0x08000000 -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_SHIFT 27 - -/* PCIE_CFG :: STATUS_COMMAND :: DEVSEL_TIMING [26:25] */ -#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_MASK 0x06000000 -#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_BITS 2 -#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_SHIFT 25 - -/* PCIE_CFG :: STATUS_COMMAND :: MASTER_DATA_PARITY_ERROR [24:24] */ -#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_MASK 0x01000000 -#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_SHIFT 24 - -/* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_CAPABLE [23:23] */ -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_MASK 0x00800000 -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_SHIFT 23 - -/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_0 [22:22] */ -#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_MASK 0x00400000 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_SHIFT 22 +/* INTR :: INTR_STATUS :: reserved0 [31:26] */ +#define INTR_INTR_STATUS_reserved0_MASK 0xfc000000 +#define INTR_INTR_STATUS_reserved0_ALIGN 0 +#define INTR_INTR_STATUS_reserved0_BITS 6 +#define INTR_INTR_STATUS_reserved0_SHIFT 26 -/* PCIE_CFG :: STATUS_COMMAND :: CAPABLE_66MHZ [21:21] */ -#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_MASK 0x00200000 -#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_SHIFT 21 +/* INTR :: INTR_STATUS :: PCIE_TGT_CA_ATTN [25:25] */ +#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK 0x02000000 +#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_ALIGN 0 +#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_BITS 1 +#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT 25 -/* PCIE_CFG :: STATUS_COMMAND :: CAPABILITIES_LIST [20:20] */ -#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_MASK 0x00100000 -#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_SHIFT 20 +/* INTR :: INTR_STATUS :: PCIE_TGT_UR_ATTN [24:24] */ +#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK 0x01000000 +#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_ALIGN 0 +#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_BITS 1 +#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT 24 -/* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_STATUS [19:19] */ -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_MASK 0x00080000 -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_SHIFT 19 +/* INTR :: INTR_STATUS :: reserved1 [23:14] */ +#define INTR_INTR_STATUS_reserved1_MASK 0x00ffc000 +#define INTR_INTR_STATUS_reserved1_ALIGN 0 +#define INTR_INTR_STATUS_reserved1_BITS 10 +#define INTR_INTR_STATUS_reserved1_SHIFT 14 -/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_1 [18:16] */ -#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_MASK 0x00070000 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_BITS 3 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_SHIFT 16 +/* INTR :: INTR_STATUS :: L1_UV_RX_DMA_ERR_INTR [13:13] */ +#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK 0x00002000 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_SHIFT 13 -/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_2 [15:11] */ -#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_MASK 0x0000f800 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_BITS 5 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_SHIFT 11 +/* INTR :: INTR_STATUS :: L1_UV_RX_DMA_DONE_INTR [12:12] */ +#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK 0x00001000 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_SHIFT 12 -/* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_DISABLE [10:10] */ -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_MASK 0x00000400 -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_SHIFT 10 +/* INTR :: INTR_STATUS :: L1_Y_RX_DMA_ERR_INTR [11:11] */ +#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK 0x00000800 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT 11 -/* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_ENABLE [09:09] */ -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_MASK 0x00000200 -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_SHIFT 9 +/* INTR :: INTR_STATUS :: L1_Y_RX_DMA_DONE_INTR [10:10] */ +#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK 0x00000400 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT 10 -/* PCIE_CFG :: STATUS_COMMAND :: SYSTEM_ERROR_ENABLE [08:08] */ -#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_MASK 0x00000100 -#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_SHIFT 8 +/* INTR :: INTR_STATUS :: L1_TX_DMA_ERR_INTR [09:09] */ +#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000200 +#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 9 -/* PCIE_CFG :: STATUS_COMMAND :: STEPPING_CONTROL [07:07] */ -#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_MASK 0x00000080 -#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_SHIFT 7 +/* INTR :: INTR_STATUS :: L1_TX_DMA_DONE_INTR [08:08] */ +#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000100 +#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 8 -/* PCIE_CFG :: STATUS_COMMAND :: PARITY_ERROR_ENABLE [06:06] */ -#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_MASK 0x00000040 -#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_SHIFT 6 +/* INTR :: INTR_STATUS :: reserved2 [07:06] */ +#define INTR_INTR_STATUS_reserved2_MASK 0x000000c0 +#define INTR_INTR_STATUS_reserved2_ALIGN 0 +#define INTR_INTR_STATUS_reserved2_BITS 2 +#define INTR_INTR_STATUS_reserved2_SHIFT 6 -/* PCIE_CFG :: STATUS_COMMAND :: VGA_PALETTE_SNOOP [05:05] */ -#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_MASK 0x00000020 -#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_SHIFT 5 +/* INTR :: INTR_STATUS :: L0_UV_RX_DMA_ERR_INTR [05:05] */ +#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK 0x00000020 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_SHIFT 5 -/* PCIE_CFG :: STATUS_COMMAND :: MEMORY_WRITE_AND_INVALIDATE [04:04] */ -#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_MASK 0x00000010 -#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_SHIFT 4 +/* INTR :: INTR_STATUS :: L0_UV_RX_DMA_DONE_INTR [04:04] */ +#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK 0x00000010 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_SHIFT 4 -/* PCIE_CFG :: STATUS_COMMAND :: SPECIAL_CYCLES [03:03] */ -#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_MASK 0x00000008 -#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT 3 +/* INTR :: INTR_STATUS :: L0_Y_RX_DMA_ERR_INTR [03:03] */ +#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK 0x00000008 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT 3 -/* PCIE_CFG :: STATUS_COMMAND :: BUS_MASTER [02:02] */ -#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_MASK 0x00000004 -#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_SHIFT 2 +/* INTR :: INTR_STATUS :: L0_Y_RX_DMA_DONE_INTR [02:02] */ +#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK 0x00000004 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT 2 -/* PCIE_CFG :: STATUS_COMMAND :: MEMORY_SPACE [01:01] */ -#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_MASK 0x00000002 -#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_SHIFT 1 +/* INTR :: INTR_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */ +#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002 +#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1 -/* PCIE_CFG :: STATUS_COMMAND :: I_O_SPACE [00:00] */ -#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_MASK 0x00000001 -#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_SHIFT 0 +/* INTR :: INTR_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */ +#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001 +#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_ALIGN 0 +#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_BITS 1 +#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0 /**************************************************************************** - * PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID + * MISC1 :: TX_SW_DESC_LIST_CTRL_STS ***************************************************************************/ -/* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: PCI_CLASSCODE [31:08] */ -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_MASK 0xffffff00 -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_ALIGN 0 -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_BITS 24 -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_SHIFT 8 - -/* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: REVISION_ID [07:00] */ -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_MASK 0x000000ff -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_ALIGN 0 -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_BITS 8 -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_SHIFT 0 - +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 -/**************************************************************************** - * PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE - ***************************************************************************/ -/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: BIST [31:24] */ -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_MASK 0xff000000 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_ALIGN 0 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_BITS 8 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_SHIFT 24 +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 -/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: HEADER_TYPE [23:16] */ -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_MASK 0x00ff0000 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_ALIGN 0 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_BITS 8 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_SHIFT 16 +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 -/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: LATENCY_TIMER [15:08] */ -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_MASK 0x0000ff00 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_ALIGN 0 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_BITS 8 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_SHIFT 8 +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_HALT_ON_ERROR [01:01] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_MASK 0x00000002 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_BITS 1 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_SHIFT 1 -/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: CACHE_LINE_SIZE [07:00] */ -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_MASK 0x000000ff -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_ALIGN 0 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_BITS 8 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_SHIFT 0 +/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */ +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_ALIGN 0 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_BITS 1 +#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0 /**************************************************************************** - * PCIE_CFG :: BASE_ADDRESS_1 + * MISC1 :: TX_DMA_ERROR_STATUS ***************************************************************************/ -/* PCIE_CFG :: BASE_ADDRESS_1 :: BASE_ADDRESS [31:16] */ -#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_MASK 0xffff0000 -#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_BITS 16 -#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_SHIFT 16 - -/* PCIE_CFG :: BASE_ADDRESS_1 :: RESERVED_0 [15:04] */ -#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_MASK 0x0000fff0 -#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_BITS 12 -#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_SHIFT 4 - -/* PCIE_CFG :: BASE_ADDRESS_1 :: PREFETCHABLE [03:03] */ -#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_MASK 0x00000008 -#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_BITS 1 -#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_SHIFT 3 - -/* PCIE_CFG :: BASE_ADDRESS_1 :: TYPE [02:01] */ -#define PCIE_CFG_BASE_ADDRESS_1_TYPE_MASK 0x00000006 -#define PCIE_CFG_BASE_ADDRESS_1_TYPE_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_1_TYPE_BITS 2 -#define PCIE_CFG_BASE_ADDRESS_1_TYPE_SHIFT 1 - -/* PCIE_CFG :: BASE_ADDRESS_1 :: MEMORY_SPACE_INDICATOR [00:00] */ -#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_MASK 0x00000001 -#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_BITS 1 -#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_SHIFT 0 +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved0 [31:10] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved0_MASK 0xfffffc00 +#define MISC1_TX_DMA_ERROR_STATUS_reserved0_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved0_BITS 22 +#define MISC1_TX_DMA_ERROR_STATUS_reserved0_SHIFT 10 +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 -/**************************************************************************** - * PCIE_CFG :: BASE_ADDRESS_2 - ***************************************************************************/ -/* PCIE_CFG :: BASE_ADDRESS_2 :: EXTENDED_BASE_ADDRESS [31:00] */ -#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_MASK 0xffffffff -#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_BITS 32 -#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_SHIFT 0 +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved1 [08:08] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved1_MASK 0x00000100 +#define MISC1_TX_DMA_ERROR_STATUS_reserved1_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved1_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_reserved1_SHIFT 8 +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 -/**************************************************************************** - * PCIE_CFG :: BASE_ADDRESS_3 - ***************************************************************************/ -/* PCIE_CFG :: BASE_ADDRESS_3 :: BASE_ADDRESS_2 [31:22] */ -#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_MASK 0xffc00000 -#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_BITS 10 -#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_SHIFT 22 +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved2 [06:06] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved2_MASK 0x00000040 +#define MISC1_TX_DMA_ERROR_STATUS_reserved2_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved2_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_reserved2_SHIFT 6 -/* PCIE_CFG :: BASE_ADDRESS_3 :: RESERVED_0 [21:04] */ -#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_MASK 0x003ffff0 -#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_BITS 18 -#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_SHIFT 4 +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DMA_DATA_TX_ABORT_ERRORS [05:05] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000020 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_SHIFT 5 -/* PCIE_CFG :: BASE_ADDRESS_3 :: PREFETCHABLE [03:03] */ -#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_MASK 0x00000008 -#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_BITS 1 -#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_SHIFT 3 +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_FIFO_FULL_ERRORS [04:04] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_SHIFT 4 -/* PCIE_CFG :: BASE_ADDRESS_3 :: TYPE [02:01] */ -#define PCIE_CFG_BASE_ADDRESS_3_TYPE_MASK 0x00000006 -#define PCIE_CFG_BASE_ADDRESS_3_TYPE_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_3_TYPE_BITS 2 -#define PCIE_CFG_BASE_ADDRESS_3_TYPE_SHIFT 1 +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved3 [03:03] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved3_MASK 0x00000008 +#define MISC1_TX_DMA_ERROR_STATUS_reserved3_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved3_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_reserved3_SHIFT 3 -/* PCIE_CFG :: BASE_ADDRESS_3 :: MEMORY_SPACE_INDICATOR [00:00] */ -#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_MASK 0x00000001 -#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_BITS 1 -#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_SHIFT 0 +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DMA_DATA_TX_ABORT_ERRORS [02:02] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000004 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_SHIFT 2 +/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_FIFO_FULL_ERRORS [01:01] */ +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_SHIFT 1 -/**************************************************************************** - * PCIE_CFG :: BASE_ADDRESS_4 - ***************************************************************************/ -/* PCIE_CFG :: BASE_ADDRESS_4 :: EXTENDED_BASE_ADDRESS_2 [31:00] */ -#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_MASK 0xffffffff -#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_BITS 32 -#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_SHIFT 0 +/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved4 [00:00] */ +#define MISC1_TX_DMA_ERROR_STATUS_reserved4_MASK 0x00000001 +#define MISC1_TX_DMA_ERROR_STATUS_reserved4_ALIGN 0 +#define MISC1_TX_DMA_ERROR_STATUS_reserved4_BITS 1 +#define MISC1_TX_DMA_ERROR_STATUS_reserved4_SHIFT 0 /**************************************************************************** - * PCIE_CFG :: CARDBUS_CIS_POINTER + * MISC1 :: Y_RX_ERROR_STATUS ***************************************************************************/ -/* PCIE_CFG :: CARDBUS_CIS_POINTER :: CARDBUS_CIS_POINTER [31:00] */ -#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_MASK 0xffffffff -#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_ALIGN 0 -#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_BITS 32 -#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_SHIFT 0 +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved0 [31:14] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 +#define MISC1_Y_RX_ERROR_STATUS_reserved0_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved0_BITS 18 +#define MISC1_Y_RX_ERROR_STATUS_reserved0_SHIFT 14 +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 -/**************************************************************************** - * PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID - ***************************************************************************/ -/* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_DEVICE_ID [31:16] */ -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_MASK 0xffff0000 -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_ALIGN 0 -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_BITS 16 -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_SHIFT 16 - -/* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_VENDOR_ID [15:00] */ -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_MASK 0x0000ffff -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_ALIGN 0 -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_BITS 16 -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS - ***************************************************************************/ -/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_BASE_ADDRESS [31:16] */ -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_MASK 0xffff0000 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_ALIGN 0 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_BITS 16 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_SHIFT 16 - -/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_SIZE_INDICATION [15:11] */ -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_MASK 0x0000f800 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_ALIGN 0 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_BITS 5 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_SHIFT 11 - -/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: RESERVED_0 [10:01] */ -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_MASK 0x000007fe -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_ALIGN 0 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_BITS 10 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_SHIFT 1 - -/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: EXPANSION_ROM_ENABLE [00:00] */ -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_MASK 0x00000001 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_ALIGN 0 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_BITS 1 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: CAPABILITIES_POINTER - ***************************************************************************/ -/* PCIE_CFG :: CAPABILITIES_POINTER :: CAPABILITIES_POINTER [31:00] */ -#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_MASK 0xffffffff -#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_ALIGN 0 -#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_BITS 32 -#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: INTERRUPT - ***************************************************************************/ -/* PCIE_CFG :: INTERRUPT :: RESERVED_0 [31:16] */ -#define PCIE_CFG_INTERRUPT_RESERVED_0_MASK 0xffff0000 -#define PCIE_CFG_INTERRUPT_RESERVED_0_ALIGN 0 -#define PCIE_CFG_INTERRUPT_RESERVED_0_BITS 16 -#define PCIE_CFG_INTERRUPT_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: INTERRUPT :: INTERRUPT_PIN [15:08] */ -#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_MASK 0x0000ff00 -#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_ALIGN 0 -#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_BITS 8 -#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_SHIFT 8 - -/* PCIE_CFG :: INTERRUPT :: INTERRUPT_LINE [07:00] */ -#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_MASK 0x000000ff -#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_ALIGN 0 -#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_BITS 8 -#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: VPD_CAPABILITIES - ***************************************************************************/ -/* PCIE_CFG :: VPD_CAPABILITIES :: RESERVED_0 [31:00] */ -#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_MASK 0xffffffff -#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_ALIGN 0 -#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_BITS 32 -#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: VPD_DATA - ***************************************************************************/ -/* PCIE_CFG :: VPD_DATA :: RESERVED_0 [31:00] */ -#define PCIE_CFG_VPD_DATA_RESERVED_0_MASK 0xffffffff -#define PCIE_CFG_VPD_DATA_RESERVED_0_ALIGN 0 -#define PCIE_CFG_VPD_DATA_RESERVED_0_BITS 32 -#define PCIE_CFG_VPD_DATA_RESERVED_0_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY - ***************************************************************************/ -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_SUPPORT [31:27] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_MASK 0xf8000000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_BITS 5 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_SHIFT 27 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D2_SUPPORT [26:26] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_MASK 0x04000000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_SHIFT 26 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D1_SUPPORT [25:25] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_MASK 0x02000000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_SHIFT 25 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: AUX_CURRENT [24:22] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_MASK 0x01c00000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_BITS 3 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_SHIFT 22 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: DSI [21:21] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_MASK 0x00200000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_SHIFT 21 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: RESERVED_0 [20:20] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_MASK 0x00100000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_SHIFT 20 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_CLOCK [19:19] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_MASK 0x00080000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_SHIFT 19 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: VERSION [18:16] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_MASK 0x00070000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_BITS 3 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_SHIFT 16 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: NEXT_POINTER [15:08] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_MASK 0x0000ff00 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_BITS 8 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_SHIFT 8 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: CAPABILITY_ID [07:00] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_MASK 0x000000ff -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_BITS 8 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS - ***************************************************************************/ -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PM_DATA [31:24] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_MASK 0xff000000 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_BITS 8 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_SHIFT 24 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_0 [23:16] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_MASK 0x00ff0000 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_BITS 8 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_STATUS [15:15] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_MASK 0x00008000 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_SHIFT 15 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SCALE [14:13] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_MASK 0x00006000 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_BITS 2 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_SHIFT 13 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SELECT [12:09] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_MASK 0x00001e00 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_BITS 4 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_SHIFT 9 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_ENABLE [08:08] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_MASK 0x00000100 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_SHIFT 8 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_1 [07:04] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_MASK 0x000000f0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_BITS 4 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_SHIFT 4 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: NO_SOFT_RESET [03:03] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_MASK 0x00000008 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_SHIFT 3 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_2 [02:02] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_MASK 0x00000004 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_SHIFT 2 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: POWER_STATE [01:00] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_MASK 0x00000003 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_BITS 2 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: MSI_CAPABILITY_HEADER - ***************************************************************************/ -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_CONTROL [31:24] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_MASK 0xff000000 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_BITS 8 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_SHIFT 24 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: ADDRESS_CAPABLE_64_BIT [23:23] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_MASK 0x00800000 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_BITS 1 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_SHIFT 23 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_ENABLE [22:20] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_MASK 0x00700000 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_BITS 3 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_SHIFT 20 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_CAPABLE [19:17] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_MASK 0x000e0000 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_BITS 3 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_SHIFT 17 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_ENABLE [16:16] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_MASK 0x00010000 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_BITS 1 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_SHIFT 16 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_BITS 8 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff -#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_BITS 8 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: MSI_LOWER_ADDRESS - ***************************************************************************/ -/* PCIE_CFG :: MSI_LOWER_ADDRESS :: MSI_LOWER_ADDRESS [31:02] */ -#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_MASK 0xfffffffc -#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_ALIGN 0 -#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_BITS 30 -#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_SHIFT 2 - -/* PCIE_CFG :: MSI_LOWER_ADDRESS :: RESERVED_0 [01:00] */ -#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_MASK 0x00000003 -#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_ALIGN 0 -#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_BITS 2 -#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER - ***************************************************************************/ -/* PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER :: MSI_UPPER_ADDRESS [31:00] */ -#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_MASK 0xffffffff -#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_ALIGN 0 -#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_BITS 32 -#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: MSI_DATA - ***************************************************************************/ -/* PCIE_CFG :: MSI_DATA :: RESERVED_0 [31:16] */ -#define PCIE_CFG_MSI_DATA_RESERVED_0_MASK 0xffff0000 -#define PCIE_CFG_MSI_DATA_RESERVED_0_ALIGN 0 -#define PCIE_CFG_MSI_DATA_RESERVED_0_BITS 16 -#define PCIE_CFG_MSI_DATA_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: MSI_DATA :: MSI_DATA [15:00] */ -#define PCIE_CFG_MSI_DATA_MSI_DATA_MASK 0x0000ffff -#define PCIE_CFG_MSI_DATA_MSI_DATA_ALIGN 0 -#define PCIE_CFG_MSI_DATA_MSI_DATA_BITS 16 -#define PCIE_CFG_MSI_DATA_MSI_DATA_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER - ***************************************************************************/ -/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: RESERVED_0 [31:24] */ -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_MASK 0xff000000 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_ALIGN 0 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_BITS 8 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_SHIFT 24 - -/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: VENDOR_SPECIFIC_CAPABILITY_LENGTH [23:16] */ -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_MASK 0x00ff0000 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_ALIGN 0 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_BITS 8 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_SHIFT 16 - -/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_ALIGN 0 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_BITS 8 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 - -/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_ALIGN 0 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_BITS 8 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES - ***************************************************************************/ -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: POR_RESET_COUNTER [31:28] */ -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_MASK 0xf0000000 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_ALIGN 0 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_BITS 4 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_SHIFT 28 - -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: HOT_RESET_COUNTER [27:24] */ -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_MASK 0x0f000000 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_ALIGN 0 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_BITS 4 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_SHIFT 24 - -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: GRC_RESET_COUNTER [23:16] */ -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_MASK 0x00ff0000 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_ALIGN 0 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_BITS 8 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_SHIFT 16 - -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: PERST_RESET_COUNTER [15:08] */ -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_MASK 0x0000ff00 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_ALIGN 0 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_BITS 8 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_SHIFT 8 - -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: LINKDOWN_RESET_COUNTER [07:00] */ -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_MASK 0x000000ff -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_ALIGN 0 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_BITS 8 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL - ***************************************************************************/ -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: PRODUCT_ID [31:24] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xff000000 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_BITS 8 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 24 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ASIC_REVISION_ID [23:16] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_MASK 0x00ff0000 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_BITS 8 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_SHIFT 16 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TLP_MINOR_ERROR_TOLERANCE [15:15] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x00008000 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: LOG_HEADER_OVERFLOW [14:14] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x00004000 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BOUNDARY_CHECK [13:13] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x00002000 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BYTE_ENABLE_RULE_CHECK [12:12] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x00001000 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: INTERRUPT_CHECK [11:11] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x00000800 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: RCB_CHECK [10:10] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x00000400 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TAGGED_STATUS_MODE [09:09] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x00000200 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT_MODE [08:08] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x00000100 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_INDIRECT_ACCESS [07:07] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x00000080 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_REGISTER_WORD_SWAP [06:06] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x00000040 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY [05:05] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000020 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_SHIFT 5 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY [04:04] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000010 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_SHIFT 4 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_WORD_SWAP [03:03] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x00000008 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_BYTE_SWAP [02:02] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x00000004 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT [01:01] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x00000002 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: CLEAR_INTERRUPT [00:00] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x00000001 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: SPARE - ***************************************************************************/ -/* PCIE_CFG :: SPARE :: UNUSED_0 [31:16] */ -#define PCIE_CFG_SPARE_UNUSED_0_MASK 0xffff0000 -#define PCIE_CFG_SPARE_UNUSED_0_ALIGN 0 -#define PCIE_CFG_SPARE_UNUSED_0_BITS 16 -#define PCIE_CFG_SPARE_UNUSED_0_SHIFT 16 - -/* PCIE_CFG :: SPARE :: RESERVED_0 [15:15] */ -#define PCIE_CFG_SPARE_RESERVED_0_MASK 0x00008000 -#define PCIE_CFG_SPARE_RESERVED_0_ALIGN 0 -#define PCIE_CFG_SPARE_RESERVED_0_BITS 1 -#define PCIE_CFG_SPARE_RESERVED_0_SHIFT 15 - -/* PCIE_CFG :: SPARE :: UNUSED_1 [14:02] */ -#define PCIE_CFG_SPARE_UNUSED_1_MASK 0x00007ffc -#define PCIE_CFG_SPARE_UNUSED_1_ALIGN 0 -#define PCIE_CFG_SPARE_UNUSED_1_BITS 13 -#define PCIE_CFG_SPARE_UNUSED_1_SHIFT 2 - -/* PCIE_CFG :: SPARE :: BAR2_TARGET_WORD_SWAP [01:01] */ -#define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_MASK 0x00000002 -#define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_ALIGN 0 -#define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_BITS 1 -#define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_SHIFT 1 - -/* PCIE_CFG :: SPARE :: BAR2_TARGET_BYTE_SWAP [00:00] */ -#define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_MASK 0x00000001 -#define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_ALIGN 0 -#define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_BITS 1 -#define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: PCI_STATE - ***************************************************************************/ -/* PCIE_CFG :: PCI_STATE :: RESERVED_0 [31:16] */ -#define PCIE_CFG_PCI_STATE_RESERVED_0_MASK 0xffff0000 -#define PCIE_CFG_PCI_STATE_RESERVED_0_ALIGN 0 -#define PCIE_CFG_PCI_STATE_RESERVED_0_BITS 16 -#define PCIE_CFG_PCI_STATE_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: PCI_STATE :: CONFIG_RETRY [15:15] */ -#define PCIE_CFG_PCI_STATE_CONFIG_RETRY_MASK 0x00008000 -#define PCIE_CFG_PCI_STATE_CONFIG_RETRY_ALIGN 0 -#define PCIE_CFG_PCI_STATE_CONFIG_RETRY_BITS 1 -#define PCIE_CFG_PCI_STATE_CONFIG_RETRY_SHIFT 15 - -/* PCIE_CFG :: PCI_STATE :: RESERVED_1 [14:12] */ -#define PCIE_CFG_PCI_STATE_RESERVED_1_MASK 0x00007000 -#define PCIE_CFG_PCI_STATE_RESERVED_1_ALIGN 0 -#define PCIE_CFG_PCI_STATE_RESERVED_1_BITS 3 -#define PCIE_CFG_PCI_STATE_RESERVED_1_SHIFT 12 - -/* PCIE_CFG :: PCI_STATE :: MAX_PCI_TARGET_RETRY [11:09] */ -#define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0x00000e00 -#define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_ALIGN 0 -#define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_BITS 3 -#define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9 - -/* PCIE_CFG :: PCI_STATE :: FLAT_VIEW [08:08] */ -#define PCIE_CFG_PCI_STATE_FLAT_VIEW_MASK 0x00000100 -#define PCIE_CFG_PCI_STATE_FLAT_VIEW_ALIGN 0 -#define PCIE_CFG_PCI_STATE_FLAT_VIEW_BITS 1 -#define PCIE_CFG_PCI_STATE_FLAT_VIEW_SHIFT 8 - -/* PCIE_CFG :: PCI_STATE :: VPD_AVAILABLE [07:07] */ -#define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_MASK 0x00000080 -#define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_ALIGN 0 -#define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_BITS 1 -#define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_SHIFT 7 - -/* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_RETRY [06:06] */ -#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x00000040 -#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_ALIGN 0 -#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_BITS 1 -#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6 - -/* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_DESIRED [05:05] */ -#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x00000020 -#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_ALIGN 0 -#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_BITS 1 -#define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5 - -/* PCIE_CFG :: PCI_STATE :: RESERVED_2 [04:00] */ -#define PCIE_CFG_PCI_STATE_RESERVED_2_MASK 0x0000001f -#define PCIE_CFG_PCI_STATE_RESERVED_2_ALIGN 0 -#define PCIE_CFG_PCI_STATE_RESERVED_2_BITS 5 -#define PCIE_CFG_PCI_STATE_RESERVED_2_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: CLOCK_CONTROL - ***************************************************************************/ -/* PCIE_CFG :: CLOCK_CONTROL :: PL_CLOCK_DISABLE [31:31] */ -#define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_MASK 0x80000000 -#define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_ALIGN 0 -#define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_BITS 1 -#define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_SHIFT 31 - -/* PCIE_CFG :: CLOCK_CONTROL :: DLL_CLOCK_DISABLE [30:30] */ -#define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_MASK 0x40000000 -#define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_ALIGN 0 -#define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_BITS 1 -#define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_SHIFT 30 - -/* PCIE_CFG :: CLOCK_CONTROL :: TL_CLOCK_DISABLE [29:29] */ -#define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_MASK 0x20000000 -#define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_ALIGN 0 -#define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_BITS 1 -#define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_SHIFT 29 - -/* PCIE_CFG :: CLOCK_CONTROL :: PCI_EXPRESS_CLOCK_TO_CORE_CLOCK [28:28] */ -#define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_MASK 0x10000000 -#define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_ALIGN 0 -#define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_BITS 1 -#define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_SHIFT 28 - -/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_0 [27:21] */ -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_MASK 0x0fe00000 -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_ALIGN 0 -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_BITS 7 -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_SHIFT 21 - -/* PCIE_CFG :: CLOCK_CONTROL :: SELECT_FINAL_ALT_CLOCK_SOURCE [20:20] */ -#define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_MASK 0x00100000 -#define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_ALIGN 0 -#define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_BITS 1 -#define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_SHIFT 20 - -/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_1 [19:13] */ -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_MASK 0x000fe000 -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_ALIGN 0 -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_BITS 7 -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_SHIFT 13 - -/* PCIE_CFG :: CLOCK_CONTROL :: SELECT_ALT_CLOCK [12:12] */ -#define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_MASK 0x00001000 -#define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_ALIGN 0 -#define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_BITS 1 -#define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_SHIFT 12 - -/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_2 [11:08] */ -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_MASK 0x00000f00 -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_ALIGN 0 -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_BITS 4 -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_SHIFT 8 - -/* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_3 [07:00] */ -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_MASK 0x000000ff -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_ALIGN 0 -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_BITS 8 -#define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: REGISTER_BASE - ***************************************************************************/ -/* PCIE_CFG :: REGISTER_BASE :: RESERVED_0 [31:18] */ -#define PCIE_CFG_REGISTER_BASE_RESERVED_0_MASK 0xfffc0000 -#define PCIE_CFG_REGISTER_BASE_RESERVED_0_ALIGN 0 -#define PCIE_CFG_REGISTER_BASE_RESERVED_0_BITS 14 -#define PCIE_CFG_REGISTER_BASE_RESERVED_0_SHIFT 18 - -/* PCIE_CFG :: REGISTER_BASE :: REGISTER_BASE_REGISTER [17:02] */ -#define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_MASK 0x0003fffc -#define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_ALIGN 0 -#define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_BITS 16 -#define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_SHIFT 2 - -/* PCIE_CFG :: REGISTER_BASE :: RESERVED_1 [01:00] */ -#define PCIE_CFG_REGISTER_BASE_RESERVED_1_MASK 0x00000003 -#define PCIE_CFG_REGISTER_BASE_RESERVED_1_ALIGN 0 -#define PCIE_CFG_REGISTER_BASE_RESERVED_1_BITS 2 -#define PCIE_CFG_REGISTER_BASE_RESERVED_1_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: MEMORY_BASE - ***************************************************************************/ -/* PCIE_CFG :: MEMORY_BASE :: RESERVED_0 [31:24] */ -#define PCIE_CFG_MEMORY_BASE_RESERVED_0_MASK 0xff000000 -#define PCIE_CFG_MEMORY_BASE_RESERVED_0_ALIGN 0 -#define PCIE_CFG_MEMORY_BASE_RESERVED_0_BITS 8 -#define PCIE_CFG_MEMORY_BASE_RESERVED_0_SHIFT 24 - -/* PCIE_CFG :: MEMORY_BASE :: MEMORY_BASE_REGISTER [23:02] */ -#define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_MASK 0x00fffffc -#define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_ALIGN 0 -#define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_BITS 22 -#define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_SHIFT 2 - -/* PCIE_CFG :: MEMORY_BASE :: RESERVED_1 [01:00] */ -#define PCIE_CFG_MEMORY_BASE_RESERVED_1_MASK 0x00000003 -#define PCIE_CFG_MEMORY_BASE_RESERVED_1_ALIGN 0 -#define PCIE_CFG_MEMORY_BASE_RESERVED_1_BITS 2 -#define PCIE_CFG_MEMORY_BASE_RESERVED_1_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: REGISTER_DATA - ***************************************************************************/ -/* PCIE_CFG :: REGISTER_DATA :: REGISTER_DATA_REGISTER [31:00] */ -#define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_MASK 0xffffffff -#define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_ALIGN 0 -#define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_BITS 32 -#define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: MEMORY_DATA - ***************************************************************************/ -/* PCIE_CFG :: MEMORY_DATA :: MEMORY_DATA_REGISTER [31:00] */ -#define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_MASK 0xffffffff -#define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_ALIGN 0 -#define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_BITS 32 -#define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: EXPANSION_ROM_BAR_SIZE - ***************************************************************************/ -/* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: RESERVED_0 [31:04] */ -#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_MASK 0xfffffff0 -#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_ALIGN 0 -#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_BITS 28 -#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_SHIFT 4 - -/* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: BAR_SIZE [03:00] */ -#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_MASK 0x0000000f -#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_ALIGN 0 -#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_BITS 4 -#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: EXPANSION_ROM_ADDRESS - ***************************************************************************/ -/* PCIE_CFG :: EXPANSION_ROM_ADDRESS :: ROM_CTL_ADDR [31:00] */ -#define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_MASK 0xffffffff -#define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_ALIGN 0 -#define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_BITS 32 -#define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: EXPANSION_ROM_DATA - ***************************************************************************/ -/* PCIE_CFG :: EXPANSION_ROM_DATA :: ROM_DATA [31:00] */ -#define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_MASK 0xffffffff -#define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_ALIGN 0 -#define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_BITS 32 -#define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: VPD_INTERFACE - ***************************************************************************/ -/* PCIE_CFG :: VPD_INTERFACE :: RESERVED_0 [31:01] */ -#define PCIE_CFG_VPD_INTERFACE_RESERVED_0_MASK 0xfffffffe -#define PCIE_CFG_VPD_INTERFACE_RESERVED_0_ALIGN 0 -#define PCIE_CFG_VPD_INTERFACE_RESERVED_0_BITS 31 -#define PCIE_CFG_VPD_INTERFACE_RESERVED_0_SHIFT 1 - -/* PCIE_CFG :: VPD_INTERFACE :: VPD_REQUEST [00:00] */ -#define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_MASK 0x00000001 -#define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_ALIGN 0 -#define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_BITS 1 -#define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER - ***************************************************************************/ -/* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ -#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff -#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_ALIGN 0 -#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_BITS 32 -#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER - ***************************************************************************/ -/* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ -#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff -#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_ALIGN 0 -#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_BITS 32 -#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER - ***************************************************************************/ -/* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ -#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff -#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_ALIGN 0 -#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_BITS 32 -#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER - ***************************************************************************/ -/* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ -#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff -#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_ALIGN 0 -#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_BITS 32 -#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER - ***************************************************************************/ -/* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ -#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff -#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_ALIGN 0 -#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_BITS 32 -#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER - ***************************************************************************/ -/* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ -#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff -#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_ALIGN 0 -#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_BITS 32 -#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: INT_MAILBOX_UPPER - ***************************************************************************/ -/* PCIE_CFG :: INT_MAILBOX_UPPER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ -#define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff -#define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_ALIGN 0 -#define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_BITS 32 -#define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: INT_MAILBOX_LOWER - ***************************************************************************/ -/* PCIE_CFG :: INT_MAILBOX_LOWER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ -#define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff -#define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_ALIGN 0 -#define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_BITS 32 -#define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION - ***************************************************************************/ -/* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: RESERVED_0 [31:28] */ -#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_MASK 0xf0000000 -#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_ALIGN 0 -#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_BITS 4 -#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_SHIFT 28 - -/* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: PRODUCT_ID [27:08] */ -#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_MASK 0x0fffff00 -#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_ALIGN 0 -#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_BITS 20 -#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_SHIFT 8 - -/* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: ASIC_REVISION_ID [07:00] */ -#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_MASK 0x000000ff -#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_ALIGN 0 -#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_BITS 8 -#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: FUNCTION_EVENT - ***************************************************************************/ -/* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_0 [31:16] */ -#define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_MASK 0xffff0000 -#define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_ALIGN 0 -#define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_BITS 16 -#define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: FUNCTION_EVENT :: INTA_EVENT [15:15] */ -#define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_MASK 0x00008000 -#define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_ALIGN 0 -#define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_BITS 1 -#define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_SHIFT 15 - -/* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_1 [14:05] */ -#define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_MASK 0x00007fe0 -#define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_ALIGN 0 -#define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_BITS 10 -#define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_SHIFT 5 - -/* PCIE_CFG :: FUNCTION_EVENT :: GWAKE_EVENT [04:04] */ -#define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_MASK 0x00000010 -#define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_ALIGN 0 -#define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_BITS 1 -#define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_SHIFT 4 - -/* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_2 [03:00] */ -#define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_MASK 0x0000000f -#define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_ALIGN 0 -#define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_BITS 4 -#define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: FUNCTION_EVENT_MASK - ***************************************************************************/ -/* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_0 [31:16] */ -#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_MASK 0xffff0000 -#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_ALIGN 0 -#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_BITS 16 -#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: FUNCTION_EVENT_MASK :: INTA_MASK [15:15] */ -#define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_MASK 0x00008000 -#define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_ALIGN 0 -#define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_BITS 1 -#define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_SHIFT 15 - -/* PCIE_CFG :: FUNCTION_EVENT_MASK :: WAKE_UP_MASK [14:14] */ -#define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_MASK 0x00004000 -#define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_ALIGN 0 -#define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_BITS 1 -#define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_SHIFT 14 - -/* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_1 [13:05] */ -#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_MASK 0x00003fe0 -#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_ALIGN 0 -#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_BITS 9 -#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_SHIFT 5 - -/* PCIE_CFG :: FUNCTION_EVENT_MASK :: GWAKE_MASK [04:04] */ -#define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_MASK 0x00000010 -#define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_ALIGN 0 -#define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_BITS 1 -#define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_SHIFT 4 - -/* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_2 [03:00] */ -#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_MASK 0x0000000f -#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_ALIGN 0 -#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_BITS 4 -#define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: FUNCTION_PRESENT - ***************************************************************************/ -/* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_0 [31:16] */ -#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_MASK 0xffff0000 -#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_ALIGN 0 -#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_BITS 16 -#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: FUNCTION_PRESENT :: INTA_STATUS [15:15] */ -#define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_MASK 0x00008000 -#define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_ALIGN 0 -#define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_BITS 1 -#define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_SHIFT 15 - -/* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_1 [14:05] */ -#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_MASK 0x00007fe0 -#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_ALIGN 0 -#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_BITS 10 -#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_SHIFT 5 - -/* PCIE_CFG :: FUNCTION_PRESENT :: PME_STATUS [04:04] */ -#define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_MASK 0x00000010 -#define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_ALIGN 0 -#define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_BITS 1 -#define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_SHIFT 4 - -/* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_2 [03:00] */ -#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_MASK 0x0000000f -#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_ALIGN 0 -#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_BITS 4 -#define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: PCIE_CAPABILITIES - ***************************************************************************/ -/* PCIE_CFG :: PCIE_CAPABILITIES :: RESERVED_0 [31:30] */ -#define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_MASK 0xc0000000 -#define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_ALIGN 0 -#define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_BITS 2 -#define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_SHIFT 30 - -/* PCIE_CFG :: PCIE_CAPABILITIES :: INTERRUPT_MESSAGE_NUMBER [29:25] */ -#define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_MASK 0x3e000000 -#define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_ALIGN 0 -#define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_BITS 5 -#define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_SHIFT 25 - -/* PCIE_CFG :: PCIE_CAPABILITIES :: SLOT_IMPLEMENTED [24:24] */ -#define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_MASK 0x01000000 -#define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_ALIGN 0 -#define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_BITS 1 -#define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_SHIFT 24 - -/* PCIE_CFG :: PCIE_CAPABILITIES :: DEVICE_PORT_TYPE [23:20] */ -#define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_MASK 0x00f00000 -#define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_ALIGN 0 -#define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_BITS 4 -#define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_SHIFT 20 - -/* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_VERSION [19:16] */ -#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_MASK 0x000f0000 -#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_ALIGN 0 -#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_BITS 4 -#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_SHIFT 16 - -/* PCIE_CFG :: PCIE_CAPABILITIES :: NEXT_POINTER [15:08] */ -#define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_MASK 0x0000ff00 -#define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_ALIGN 0 -#define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_BITS 8 -#define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_SHIFT 8 - -/* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_ID [07:00] */ -#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_MASK 0x000000ff -#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_ALIGN 0 -#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_BITS 8 -#define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: DEVICE_CAPABILITIES - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_0 [31:28] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_MASK 0xf0000000 -#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_BITS 4 -#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_SHIFT 28 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_SCALE [27:26] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_MASK 0x0c000000 -#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_BITS 2 -#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_SHIFT 26 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_VALUE [25:18] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_MASK 0x03fc0000 -#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_BITS 8 -#define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_SHIFT 18 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_1 [17:16] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_MASK 0x00030000 -#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_BITS 2 -#define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_SHIFT 16 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: ROLE_BASED_ERROR_SUPPORT [15:15] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_MASK 0x00008000 -#define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_BITS 1 -#define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_SHIFT 15 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: POWER_INDICATOR_PRESENT [14:14] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_MASK 0x00004000 -#define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_BITS 1 -#define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_SHIFT 14 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_INDICATOR_PRESENT [13:13] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_MASK 0x00002000 -#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_BITS 1 -#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_SHIFT 13 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_BUTTON_PRESENT [12:12] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_MASK 0x00001000 -#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_BITS 1 -#define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_SHIFT 12 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L1_ACCEPTABLE_LATENCY [11:09] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_MASK 0x00000e00 -#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_BITS 3 -#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_SHIFT 9 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L0S_ACCEPTABLE_LATENCY [08:06] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0 -#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_BITS 3 -#define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_SHIFT 6 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: EXTENDED_TAG_FIELD_SUPPORTED [05:05] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_MASK 0x00000020 -#define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_BITS 1 -#define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_SHIFT 5 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: PHANTOM_FUNCTIONS_SUPPORTED [04:03] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_MASK 0x00000018 -#define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_BITS 2 -#define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_SHIFT 3 - -/* PCIE_CFG :: DEVICE_CAPABILITIES :: MAX_PAYLOAD_SIZE_SUPPORTED [02:00] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_MASK 0x00000007 -#define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_BITS 3 -#define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: DEVICE_STATUS_CONTROL - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_0 [31:22] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_MASK 0xffc00000 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_BITS 10 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_SHIFT 22 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: TRANSACTION_PENDING [21:21] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_MASK 0x00200000 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_SHIFT 21 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_DETECTED [20:20] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_MASK 0x00100000 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_SHIFT 20 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_DETECTED [19:19] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_MASK 0x00080000 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_SHIFT 19 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_DETECTED [18:18] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_MASK 0x00040000 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_SHIFT 18 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_DETECTED [17:17] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_MASK 0x00020000 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_SHIFT 17 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_DETECTED [16:16] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_MASK 0x00010000 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_SHIFT 16 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_1 [15:15] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_MASK 0x00008000 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_SHIFT 15 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_READ_REQUEST_SIZE [14:12] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_MASK 0x00007000 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_BITS 3 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_SHIFT 12 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLE_NO_SNOOP [11:11] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_MASK 0x00000800 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_SHIFT 11 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_PM_ENABLE [10:10] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_MASK 0x00000400 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_SHIFT 10 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: PHANTOM_FUNCTIONS_ENABLE [09:09] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_MASK 0x00000200 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_SHIFT 9 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: EXTENDED_TAG_FIELD_ENABLE [08:08] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_MASK 0x00000100 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_SHIFT 8 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_PAYLOAD_SIZE [07:05] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_MASK 0x000000e0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_BITS 3 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_SHIFT 5 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLED_RELAXED_ORDERING [04:04] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_MASK 0x00000010 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_SHIFT 4 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_REPORTING_ENABLE [03:03] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_MASK 0x00000008 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_SHIFT 3 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_REPORTING_ENABLED [02:02] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000004 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_SHIFT 2 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_REPORTING_ENABLED [01:01] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000002 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_SHIFT 1 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_REPORTING_ENABLED [00:00] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_MASK 0x00000001 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: LINK_CAPABILITY - ***************************************************************************/ -/* PCIE_CFG :: LINK_CAPABILITY :: PORT_NUMBER [31:24] */ -#define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_MASK 0xff000000 -#define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_ALIGN 0 -#define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_BITS 8 -#define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_SHIFT 24 - -/* PCIE_CFG :: LINK_CAPABILITY :: RESERVED_0 [23:19] */ -#define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_MASK 0x00f80000 -#define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_ALIGN 0 -#define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_BITS 5 -#define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_SHIFT 19 - -/* PCIE_CFG :: LINK_CAPABILITY :: CLOCK_POWER_MANAGEMENT [18:18] */ -#define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_MASK 0x00040000 -#define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_ALIGN 0 -#define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_BITS 1 -#define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_SHIFT 18 - -/* PCIE_CFG :: LINK_CAPABILITY :: L1_EXIT_LATENCY [17:15] */ -#define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_MASK 0x00038000 -#define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_ALIGN 0 -#define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_BITS 3 -#define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_SHIFT 15 - -/* PCIE_CFG :: LINK_CAPABILITY :: L0S_EXIT_LATENCY [14:12] */ -#define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_MASK 0x00007000 -#define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_ALIGN 0 -#define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_BITS 3 -#define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_SHIFT 12 - -/* PCIE_CFG :: LINK_CAPABILITY :: ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT [11:10] */ -#define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_MASK 0x00000c00 -#define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_ALIGN 0 -#define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_BITS 2 -#define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_SHIFT 10 - -/* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_WIDTH [09:04] */ -#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_MASK 0x000003f0 -#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_ALIGN 0 -#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_BITS 6 -#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_SHIFT 4 - -/* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_SPEED [03:00] */ -#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_MASK 0x0000000f -#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_ALIGN 0 -#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_BITS 4 -#define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: LINK_STATUS_CONTROL - ***************************************************************************/ -/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_0 [31:29] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_MASK 0xe0000000 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_BITS 3 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_SHIFT 29 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: SLOT_CLOCK_CONFIGURATION [28:28] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_MASK 0x10000000 -#define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_BITS 1 -#define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_SHIFT 28 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_1 [27:26] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_MASK 0x0c000000 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_BITS 2 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_SHIFT 26 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: NEGOTIATED_LINK_WIDTH [25:20] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x03f00000 -#define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_BITS 6 -#define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: LINK_SPEED [19:16] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_MASK 0x000f0000 -#define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_BITS 4 -#define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_SHIFT 16 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_2 [15:09] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_MASK 0x0000fe00 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_BITS 7 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_SHIFT 9 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: CLOCK_REQUEST_ENABLE [08:08] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_MASK 0x00000100 -#define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_BITS 1 -#define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_SHIFT 8 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: EXTENDED_SYNCH [07:07] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_MASK 0x00000080 -#define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_BITS 1 -#define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_SHIFT 7 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: COMMON_CLOCK_CONFIGURATION [06:06] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_MASK 0x00000040 -#define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_BITS 1 -#define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_SHIFT 6 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_3 [05:05] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_MASK 0x00000020 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_BITS 1 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_SHIFT 5 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_4 [04:04] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_MASK 0x00000010 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_BITS 1 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_SHIFT 4 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: READ_COMPLETION_BOUNDARY [03:03] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_MASK 0x00000008 -#define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_BITS 1 -#define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_SHIFT 3 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_5 [02:02] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_MASK 0x00000004 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_BITS 1 -#define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_SHIFT 2 - -/* PCIE_CFG :: LINK_STATUS_CONTROL :: ACTIVE_STATE_POWER_MANAGEMENT_CONTROL [01:00] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_MASK 0x00000003 -#define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_BITS 2 -#define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: DEVICE_CAPABILITIES_2 - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: RESERVED_0 [31:05] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_MASK 0xffffffe0 -#define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_BITS 27 -#define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_SHIFT 5 - -/* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_DISABLE_SUPPORTED [04:04] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_MASK 0x00000010 -#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_BITS 1 -#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_SHIFT 4 - -/* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_TIMEOUT_RANGE_SUPPORTED [03:00] */ -#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000f -#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_ALIGN 0 -#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_BITS 4 -#define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: DEVICE_STATUS_CONTROL_2 - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: RESERVED_0 [31:05] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffe0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_BITS 27 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_SHIFT 5 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_DISABLE [04:04] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_MASK 0x00000010 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_BITS 1 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_SHIFT 4 - -/* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_VALUE [03:00] */ -#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_MASK 0x0000000f -#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_ALIGN 0 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_BITS 4 -#define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: LINK_CAPABILITIES_2 - ***************************************************************************/ -/* PCIE_CFG :: LINK_CAPABILITIES_2 :: RESERVED_0 [31:00] */ -#define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_MASK 0xffffffff -#define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_ALIGN 0 -#define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_BITS 32 -#define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: LINK_STATUS_CONTROL_2 - ***************************************************************************/ -/* PCIE_CFG :: LINK_STATUS_CONTROL_2 :: RESERVED_0 [31:00] */ -#define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffff -#define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_ALIGN 0 -#define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_BITS 32 -#define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER - ***************************************************************************/ -/* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ -#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 -#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 -#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 -#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 - -/* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ -#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 -#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 -#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 -#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 - -/* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ -#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff -#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 -#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 -#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS - ***************************************************************************/ -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:21] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffe00000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_BITS 11 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 21 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNSUPPORTED_REQUEST_ERROR_STATUS [20:20] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_MASK 0x00100000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_SHIFT 20 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: ECRC_ERROR_STATUS [19:19] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_MASK 0x00080000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_SHIFT 19 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: MALFORMED_TLP_STATUS [18:18] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_MASK 0x00040000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_SHIFT 18 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RECEIVER_OVERFLOW_STATUS [17:17] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_MASK 0x00020000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_SHIFT 17 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNEXPECTED_COMPLETION_STATUS [16:16] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_MASK 0x00010000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_SHIFT 16 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETER_ABORT_STATUS [15:15] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_MASK 0x00008000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_SHIFT 15 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETION_TIMEOUT_STATUS [14:14] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_MASK 0x00004000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_SHIFT 14 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR_STATUS [13:13] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_MASK 0x00002000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_SHIFT 13 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: POISONED_TLP_STATUS [12:12] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_MASK 0x00001000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_SHIFT 12 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:05] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000fe0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_BITS 7 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 5 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: DATA_LINK_PROTOCOL_ERROR_STATUS [04:04] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_MASK 0x00000010 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_SHIFT 4 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_2 [03:01] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000000e -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_BITS 3 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: TRAINING_ERROR_STATUS [00:00] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_MASK 0x00000001 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: UNCORRECTABLE_ERROR_MASK - ***************************************************************************/ -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_0 [31:21] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffe00000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_BITS 11 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 21 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNSUPPORTED_REQUEST_ERROR_MASK [20:20] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_MASK 0x00100000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_SHIFT 20 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: ECRC_ERROR_MASK [19:19] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_MASK 0x00080000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_SHIFT 19 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: MALFORMED_TLP_MASK [18:18] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_MASK 0x00040000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_SHIFT 18 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RECEIVER_OVERFLOW_MASK [17:17] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_MASK 0x00020000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_SHIFT 17 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNEXPECTED_COMPLETION_MASK [16:16] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_MASK 0x00010000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_SHIFT 16 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETER_ABORT_MASK [15:15] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_MASK 0x00008000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_SHIFT 15 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETION_TIMEOUT_MASK [14:14] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_MASK 0x00004000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_SHIFT 14 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: FLOW_CONTROL_PROTOCOL_ERROR_MASK [13:13] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_MASK 0x00002000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_SHIFT 13 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: POISONED_TLP_MASK [12:12] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_MASK 0x00001000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_SHIFT 12 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_1 [11:05] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000fe0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_BITS 7 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 5 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: DATA_LINK_PROTOCOL_ERROR_MASK [04:04] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_MASK 0x00000010 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_SHIFT 4 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_2 [03:01] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000000e -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_BITS 3 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: TRAINING_ERROR_MASK [00:00] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_MASK 0x00000001 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY - ***************************************************************************/ -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_0 [31:21] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_MASK 0xffe00000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_BITS 11 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_SHIFT 21 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNSUPPORTED_REQUEST_ERROR_SEVERITY [20:20] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_MASK 0x00100000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_SHIFT 20 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: ECRC_ERROR_SEVERITY [19:19] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_MASK 0x00080000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_SHIFT 19 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: MALFORMED_TLP_SEVERITY [18:18] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_MASK 0x00040000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_SHIFT 18 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RECEIVER_OVERFLOW_ERROR_SEVERITY [17:17] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_MASK 0x00020000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_SHIFT 17 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNEXPECTED_COMPLETION_ERROR_SEVERITY [16:16] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_MASK 0x00010000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_SHIFT 16 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETER_ABORT_ERROR_SEVERITY [15:15] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_MASK 0x00008000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_SHIFT 15 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETION_TIMEOUT_ERROR_SEVERITY [14:14] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_MASK 0x00004000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_SHIFT 14 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY [13:13] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_MASK 0x00002000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_SHIFT 13 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: POISONED_TLP_SEVERITY [12:12] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_MASK 0x00001000 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_SHIFT 12 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_1 [11:05] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_MASK 0x00000fe0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_BITS 7 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_SHIFT 5 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: DATA_LINK_PROTOCOL_ERROR_SEVERITY [04:04] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_MASK 0x00000010 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_SHIFT 4 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_2 [03:01] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_MASK 0x0000000e -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_BITS 3 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_SHIFT 1 - -/* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: TRAINING_ERROR_SEVERITY [00:00] */ -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_MASK 0x00000001 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_ALIGN 0 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_BITS 1 -#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: CORRECTABLE_ERROR_STATUS - ***************************************************************************/ -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:14] */ -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffffc000 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_BITS 18 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 14 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: ADVISORY_NON_FATAL_ERROR_STATUS [13:13] */ -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_MASK 0x00002000 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_BITS 1 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_SHIFT 13 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_TIMER_TIMEOUT_STATUS [12:12] */ -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_BITS 1 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_SHIFT 12 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:09] */ -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000e00 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_BITS 3 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 9 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_NUM_ROLLOVER_STATUS [08:08] */ -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_BITS 1 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_SHIFT 8 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_DLLP_STATUS [07:07] */ -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_MASK 0x00000080 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_BITS 1 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_SHIFT 7 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_TLP_STATUS [06:06] */ -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_MASK 0x00000040 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_BITS 1 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_SHIFT 6 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_2 [05:01] */ -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000003e -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_BITS 5 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 - -/* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RECEIVER_ERROR_STATUS [00:00] */ -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_MASK 0x00000001 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_BITS 1 -#define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: CORRECTABLE_ERROR_MASK - ***************************************************************************/ -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_0 [31:14] */ -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffffc000 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_BITS 18 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 14 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: ADVISORY_NON_FATAL_ERROR_MASK [13:13] */ -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_MASK 0x00002000 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_BITS 1 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_SHIFT 13 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_TIMER_TIMEOUT_MASK [12:12] */ -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_BITS 1 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_SHIFT 12 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_1 [11:09] */ -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000e00 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_BITS 3 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 9 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_NUM_ROLLOVER_MASK [08:08] */ -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_BITS 1 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_SHIFT 8 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_DLLP_MASK [07:07] */ -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_MASK 0x00000080 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_BITS 1 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_SHIFT 7 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_TLP_MASK [06:06] */ -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_MASK 0x00000040 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_BITS 1 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_SHIFT 6 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_2 [05:01] */ -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000003e -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_BITS 5 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 - -/* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RECEIVER_ERROR_MASK [00:00] */ -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_MASK 0x00000001 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_ALIGN 0 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_BITS 1 -#define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL - ***************************************************************************/ -/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: RESERVED_0 [31:09] */ -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_MASK 0xfffffe00 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_ALIGN 0 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_BITS 23 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_SHIFT 9 - -/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_ENABLE [08:08] */ -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_MASK 0x00000100 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_ALIGN 0 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_BITS 1 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_SHIFT 8 - -/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_CAPABLE [07:07] */ -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_MASK 0x00000080 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_ALIGN 0 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_BITS 1 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_SHIFT 7 - -/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_ENABLE [06:06] */ -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_MASK 0x00000040 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_ALIGN 0 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_BITS 1 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_SHIFT 6 - -/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_CAPABLE [05:05] */ -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_MASK 0x00000020 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_ALIGN 0 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_BITS 1 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_SHIFT 5 - -/* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: FIRST_ERROR_POINTER [04:00] */ -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_MASK 0x0000001f -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_ALIGN 0 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_BITS 5 -#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: HEADER_LOG_1 - ***************************************************************************/ -/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_0 [31:24] */ -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_MASK 0xff000000 -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_BITS 8 -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_SHIFT 24 - -/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_1 [23:16] */ -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_MASK 0x00ff0000 -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_BITS 8 -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_SHIFT 16 - -/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_2 [15:08] */ -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_MASK 0x0000ff00 -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_BITS 8 -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_SHIFT 8 - -/* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_3 [07:00] */ -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_MASK 0x000000ff -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_BITS 8 -#define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: HEADER_LOG_2 - ***************************************************************************/ -/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_4 [31:24] */ -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_MASK 0xff000000 -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_BITS 8 -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_SHIFT 24 - -/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_5 [23:16] */ -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_MASK 0x00ff0000 -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_BITS 8 -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_SHIFT 16 - -/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_6 [15:08] */ -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_MASK 0x0000ff00 -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_BITS 8 -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_SHIFT 8 - -/* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_7 [07:00] */ -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_MASK 0x000000ff -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_BITS 8 -#define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: HEADER_LOG_3 - ***************************************************************************/ -/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_8 [31:24] */ -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_MASK 0xff000000 -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_BITS 8 -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_SHIFT 24 - -/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_9 [23:16] */ -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_MASK 0x00ff0000 -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_BITS 8 -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_SHIFT 16 - -/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_10 [15:08] */ -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_MASK 0x0000ff00 -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_BITS 8 -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_SHIFT 8 - -/* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_11 [07:00] */ -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_MASK 0x000000ff -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_BITS 8 -#define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: HEADER_LOG_4 - ***************************************************************************/ -/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_12 [31:24] */ -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_MASK 0xff000000 -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_BITS 8 -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_SHIFT 24 - -/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_13 [23:16] */ -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_MASK 0x00ff0000 -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_BITS 8 -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_SHIFT 16 - -/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_14 [15:08] */ -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_MASK 0x0000ff00 -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_BITS 8 -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_SHIFT 8 - -/* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_15 [07:00] */ -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_MASK 0x000000ff -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_ALIGN 0 -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_BITS 8 -#define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER - ***************************************************************************/ -/* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ -#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 -#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 -#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 -#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 - -/* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ -#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 -#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 -#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 -#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 - -/* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ -#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff -#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 -#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 -#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: PORT_VC_CAPABILITY - ***************************************************************************/ -/* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_0 [31:12] */ -#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_MASK 0xfffff000 -#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_ALIGN 0 -#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_BITS 20 -#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_SHIFT 12 - -/* PCIE_CFG :: PORT_VC_CAPABILITY :: PORT_ARBITRATION_TABLE_ENTRY_SIZE [11:10] */ -#define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_MASK 0x00000c00 -#define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_ALIGN 0 -#define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_BITS 2 -#define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_SHIFT 10 - -/* PCIE_CFG :: PORT_VC_CAPABILITY :: REFERENCE_CLOCK [09:08] */ -#define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_MASK 0x00000300 -#define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_ALIGN 0 -#define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_BITS 2 -#define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_SHIFT 8 - -/* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_1 [07:07] */ -#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_MASK 0x00000080 -#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_ALIGN 0 -#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_BITS 1 -#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_SHIFT 7 - -/* PCIE_CFG :: PORT_VC_CAPABILITY :: LOW_PRIORITY_EXTENDED_VC_COUNT [06:04] */ -#define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_MASK 0x00000070 -#define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_ALIGN 0 -#define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_BITS 3 -#define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_SHIFT 4 - -/* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_2 [03:03] */ -#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_MASK 0x00000008 -#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_ALIGN 0 -#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_BITS 1 -#define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_SHIFT 3 - -/* PCIE_CFG :: PORT_VC_CAPABILITY :: EXTENDED_VC_COUNT [02:00] */ -#define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_MASK 0x00000007 -#define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_ALIGN 0 -#define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_BITS 3 -#define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: PORT_VC_CAPABILITY_2 - ***************************************************************************/ -/* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_TABLE_OFFSET [31:24] */ -#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 -#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_ALIGN 0 -#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_BITS 8 -#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_SHIFT 24 - -/* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: RESERVED_0 [23:08] */ -#define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_MASK 0x00ffff00 -#define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_ALIGN 0 -#define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_BITS 16 -#define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_SHIFT 8 - -/* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_CAPABILITY [07:00] */ -#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_MASK 0x000000ff -#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_ALIGN 0 -#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_BITS 8 -#define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: PORT_VC_STATUS_CONTROL - ***************************************************************************/ -/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_0 [31:17] */ -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_MASK 0xfffe0000 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_ALIGN 0 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_BITS 15 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_SHIFT 17 - -/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_TABLE_STATUS [16:16] */ -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_MASK 0x00010000 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_ALIGN 0 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_BITS 1 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_SHIFT 16 - -/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_1 [15:04] */ -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_MASK 0x0000fff0 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_ALIGN 0 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_BITS 12 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_SHIFT 4 - -/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_SELECT [03:01] */ -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_MASK 0x0000000e -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_ALIGN 0 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_BITS 3 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_SHIFT 1 - -/* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: LOAD_VC_ARBITRATION_TABLE [00:00] */ -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_MASK 0x00000001 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_ALIGN 0 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_BITS 1 -#define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: VC_RESOURCE_CAPABILITY - ***************************************************************************/ -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_TABLE_OFFSET [31:24] */ -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_BITS 8 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_SHIFT 24 - -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_0 [23:23] */ -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_MASK 0x00800000 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_BITS 1 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_SHIFT 23 - -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: MAXIMUM_TIME_SLOTS [22:16] */ -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_MASK 0x007f0000 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_BITS 7 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_SHIFT 16 - -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: REJECT_SNOOP_TRANSACTIONS [15:15] */ -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_MASK 0x00008000 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_BITS 1 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_SHIFT 15 - -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: ADVANCED_PACKET_SWITCHING [14:14] */ -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_MASK 0x00004000 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_BITS 1 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_SHIFT 14 - -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_1 [13:08] */ -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_MASK 0x00003f00 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_BITS 6 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_SHIFT 8 - -/* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_CAPABILITY [07:00] */ -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_MASK 0x000000ff -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_BITS 8 -#define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: VC_RESOURCE_CONTROL - ***************************************************************************/ -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ENABLE [31:31] */ -#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_MASK 0x80000000 -#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_BITS 1 -#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_SHIFT 31 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_0 [30:27] */ -#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_MASK 0x78000000 -#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_BITS 4 -#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_SHIFT 27 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ID [26:24] */ -#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_MASK 0x07000000 -#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_BITS 3 -#define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_SHIFT 24 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_1 [23:20] */ -#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_MASK 0x00f00000 -#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_BITS 4 -#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_SHIFT 20 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: PORT_ARBITRATION_SELECT [19:17] */ -#define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_MASK 0x000e0000 -#define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_BITS 3 -#define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_SHIFT 17 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: LOAD_PORT_ARBITRATION_TABLE [16:16] */ -#define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_MASK 0x00010000 -#define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_BITS 1 -#define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_SHIFT 16 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_2 [15:08] */ -#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_MASK 0x0000ff00 -#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_BITS 8 -#define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_SHIFT 8 - -/* PCIE_CFG :: VC_RESOURCE_CONTROL :: TC_VC_MAP [07:00] */ -#define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_MASK 0x000000ff -#define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_BITS 8 -#define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: VC_RESOURCE_STATUS - ***************************************************************************/ -/* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_0 [31:18] */ -#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_MASK 0xfffc0000 -#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_BITS 14 -#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_SHIFT 18 - -/* PCIE_CFG :: VC_RESOURCE_STATUS :: VC_NEGOTIATION_PENDING [17:17] */ -#define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_MASK 0x00020000 -#define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_BITS 1 -#define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_SHIFT 17 - -/* PCIE_CFG :: VC_RESOURCE_STATUS :: PORT_ARBITRATION_TABLE_STATUS [16:16] */ -#define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_MASK 0x00010000 -#define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_BITS 1 -#define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_SHIFT 16 - -/* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_1 [15:00] */ -#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_MASK 0x0000ffff -#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_ALIGN 0 -#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_BITS 16 -#define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ -#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 -#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 -#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 -#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 - -/* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ -#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 -#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 -#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 -#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 - -/* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ -#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff -#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 -#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 -#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: DEVICE_SERIAL_NO_LOWER_DW - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_SERIAL_NO_LOWER_DW :: SERIAL_NO_LOWER [31:00] */ -#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_MASK 0xffffffff -#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_ALIGN 0 -#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_BITS 32 -#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: DEVICE_SERIAL_NO_UPPER_DW - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_SERIAL_NO_UPPER_DW :: SERIAL_NO_UPPER [31:00] */ -#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_MASK 0xffffffff -#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_ALIGN 0 -#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_BITS 32 -#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER - ***************************************************************************/ -/* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ -#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 -#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 -#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 - -/* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ -#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 -#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 -#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 - -/* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ -#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff -#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 -#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: POWER_BUDGETING_DATA_SELECT - ***************************************************************************/ -/* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: RESERVED_0 [31:08] */ -#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_MASK 0xffffff00 -#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_BITS 24 -#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_SHIFT 8 - -/* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: DATA_SELECT [07:00] */ -#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_MASK 0x000000ff -#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_BITS 8 -#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: POWER_BUDGETING_DATA - ***************************************************************************/ -/* PCIE_CFG :: POWER_BUDGETING_DATA :: RESERVED_0 [31:21] */ -#define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_MASK 0xffe00000 -#define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_BITS 11 -#define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_SHIFT 21 - -/* PCIE_CFG :: POWER_BUDGETING_DATA :: POWER_RAIL [20:18] */ -#define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_MASK 0x001c0000 -#define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_BITS 3 -#define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_SHIFT 18 - -/* PCIE_CFG :: POWER_BUDGETING_DATA :: TYPE [17:15] */ -#define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_MASK 0x00038000 -#define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_BITS 3 -#define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_SHIFT 15 - -/* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_STATE [14:13] */ -#define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_MASK 0x00006000 -#define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_BITS 2 -#define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_SHIFT 13 - -/* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_SUB_STATE [12:10] */ -#define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_MASK 0x00001c00 -#define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_BITS 3 -#define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_SHIFT 10 - -/* PCIE_CFG :: POWER_BUDGETING_DATA :: DATA_SCALE [09:08] */ -#define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_MASK 0x00000300 -#define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_BITS 2 -#define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_SHIFT 8 - -/* PCIE_CFG :: POWER_BUDGETING_DATA :: BASE_POWER [07:00] */ -#define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_MASK 0x000000ff -#define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_BITS 8 -#define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: POWER_BUDGETING_CAPABILITY - ***************************************************************************/ -/* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: RESERVED_0 [31:01] */ -#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_MASK 0xfffffffe -#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_BITS 31 -#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_SHIFT 1 - -/* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: LOM_CONFIGURATION [00:00] */ -#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_MASK 0x00000001 -#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_ALIGN 0 -#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_BITS 1 -#define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 - ***************************************************************************/ -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_2 [31:29] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_MASK 0xe0000000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_SHIFT 29 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_2 [28:26] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_MASK 0x1c000000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_SHIFT 26 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_2 [25:24] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_MASK 0x03000000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_BITS 2 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_SHIFT 24 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_2 [23:16] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_MASK 0x00ff0000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_BITS 8 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_SHIFT 16 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_1 [15:13] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_MASK 0x0000e000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_SHIFT 13 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_1 [12:10] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_MASK 0x00001c00 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_SHIFT 10 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_1 [09:08] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_MASK 0x00000300 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_BITS 2 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_SHIFT 8 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_1 [07:00] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_MASK 0x000000ff -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_BITS 8 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 - ***************************************************************************/ -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_4 [31:29] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_MASK 0xe0000000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_SHIFT 29 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_4 [28:26] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_MASK 0x1c000000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_SHIFT 26 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_4 [25:24] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_MASK 0x03000000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_BITS 2 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_SHIFT 24 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_4 [23:16] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_MASK 0x00ff0000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_BITS 8 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_SHIFT 16 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_3 [15:13] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_MASK 0x0000e000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_SHIFT 13 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_3 [12:10] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_MASK 0x00001c00 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_SHIFT 10 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_3 [09:08] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_MASK 0x00000300 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_BITS 2 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_SHIFT 8 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_3 [07:00] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_MASK 0x000000ff -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_BITS 8 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 - ***************************************************************************/ -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_6 [31:29] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_MASK 0xe0000000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_SHIFT 29 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_6 [28:26] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_MASK 0x1c000000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_SHIFT 26 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_6 [25:24] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_MASK 0x03000000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_BITS 2 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_SHIFT 24 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_6 [23:16] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_MASK 0x00ff0000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_BITS 8 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_SHIFT 16 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_5 [15:13] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_MASK 0x0000e000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_SHIFT 13 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_5 [12:10] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_MASK 0x00001c00 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_SHIFT 10 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_5 [09:08] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_MASK 0x00000300 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_BITS 2 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_SHIFT 8 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_5 [07:00] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_MASK 0x000000ff -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_BITS 8 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 - ***************************************************************************/ -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_8 [31:29] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_MASK 0xe0000000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_SHIFT 29 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_8 [28:26] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_MASK 0x1c000000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_SHIFT 26 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_8 [25:24] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_MASK 0x03000000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_BITS 2 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_SHIFT 24 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_8 [23:16] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_MASK 0x00ff0000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_BITS 8 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_SHIFT 16 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_7 [15:13] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_MASK 0x0000e000 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_SHIFT 13 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_7 [12:10] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_MASK 0x00001c00 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_BITS 3 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_SHIFT 10 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_7 [09:08] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_MASK 0x00000300 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_BITS 2 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_SHIFT 8 - -/* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_7 [07:00] */ -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_MASK 0x000000ff -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_ALIGN 0 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_BITS 8 -#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING - ***************************************************************************/ -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNUSED_0 [31:07] */ -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_MASK 0xffffff80 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_ALIGN 0 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_BITS 25 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_SHIFT 7 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: D3HOT_MEMORY_READ_ADVISORY_NON_FATAL [06:06] */ -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_MASK 0x00000040 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_ALIGN 0 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_BITS 1 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_SHIFT 6 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: RETRY_POISON_ENABLE [05:05] */ -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_MASK 0x00000020 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_ALIGN 0 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_BITS 1 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_SHIFT 5 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: POISON_ADVISORY_NON_FATAL_ENABLE [04:04] */ -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000010 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_BITS 1 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_SHIFT 4 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNEXPECTED_ADVISORY_NON_FATAL_ENABLE [03:03] */ -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000008 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_BITS 1 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_SHIFT 3 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE [02:02] */ -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000004 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_BITS 1 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_SHIFT 2 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [01:01] */ -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000002 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_BITS 1 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 1 - -/* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [00:00] */ -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000001 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_BITS 1 -#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 0 - - -/**************************************************************************** - * BCM70012_TGT_TOP_PCIE_TL - ***************************************************************************/ -/**************************************************************************** - * PCIE_TL :: TL_CONTROL - ***************************************************************************/ -/* PCIE_TL :: TL_CONTROL :: RESERVED_0 [31:31] */ -#define PCIE_TL_TL_CONTROL_RESERVED_0_MASK 0x80000000 -#define PCIE_TL_TL_CONTROL_RESERVED_0_ALIGN 0 -#define PCIE_TL_TL_CONTROL_RESERVED_0_BITS 1 -#define PCIE_TL_TL_CONTROL_RESERVED_0_SHIFT 31 - -/* PCIE_TL :: TL_CONTROL :: CQ14298_FIX_ENA_N [30:30] */ -#define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_MASK 0x40000000 -#define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_ALIGN 0 -#define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_BITS 1 -#define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_SHIFT 30 - -/* PCIE_TL :: TL_CONTROL :: RESERVED_1 [29:29] */ -#define PCIE_TL_TL_CONTROL_RESERVED_1_MASK 0x20000000 -#define PCIE_TL_TL_CONTROL_RESERVED_1_ALIGN 0 -#define PCIE_TL_TL_CONTROL_RESERVED_1_BITS 1 -#define PCIE_TL_TL_CONTROL_RESERVED_1_SHIFT 29 - -/* PCIE_TL :: TL_CONTROL :: INTA_WAKEUP_LINK_CLKREQ_DA [28:28] */ -#define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_MASK 0x10000000 -#define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_ALIGN 0 -#define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_BITS 1 -#define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_SHIFT 28 - -/* PCIE_TL :: TL_CONTROL :: RESERVED_2 [27:27] */ -#define PCIE_TL_TL_CONTROL_RESERVED_2_MASK 0x08000000 -#define PCIE_TL_TL_CONTROL_RESERVED_2_ALIGN 0 -#define PCIE_TL_TL_CONTROL_RESERVED_2_BITS 1 -#define PCIE_TL_TL_CONTROL_RESERVED_2_SHIFT 27 - -/* PCIE_TL :: TL_CONTROL :: CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX [26:26] */ -#define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_MASK 0x04000000 -#define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_ALIGN 0 -#define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_BITS 1 -#define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_SHIFT 26 - -/* PCIE_TL :: TL_CONTROL :: RESERVED_3 [25:25] */ -#define PCIE_TL_TL_CONTROL_RESERVED_3_MASK 0x02000000 -#define PCIE_TL_TL_CONTROL_RESERVED_3_ALIGN 0 -#define PCIE_TL_TL_CONTROL_RESERVED_3_BITS 1 -#define PCIE_TL_TL_CONTROL_RESERVED_3_SHIFT 25 - -/* PCIE_TL :: TL_CONTROL :: RESERVED_4 [24:24] */ -#define PCIE_TL_TL_CONTROL_RESERVED_4_MASK 0x01000000 -#define PCIE_TL_TL_CONTROL_RESERVED_4_ALIGN 0 -#define PCIE_TL_TL_CONTROL_RESERVED_4_BITS 1 -#define PCIE_TL_TL_CONTROL_RESERVED_4_SHIFT 24 - -/* PCIE_TL :: TL_CONTROL :: RESERVED_5 [23:23] */ -#define PCIE_TL_TL_CONTROL_RESERVED_5_MASK 0x00800000 -#define PCIE_TL_TL_CONTROL_RESERVED_5_ALIGN 0 -#define PCIE_TL_TL_CONTROL_RESERVED_5_BITS 1 -#define PCIE_TL_TL_CONTROL_RESERVED_5_SHIFT 23 - -/* PCIE_TL :: TL_CONTROL :: CRC_SWAP [22:22] */ -#define PCIE_TL_TL_CONTROL_CRC_SWAP_MASK 0x00400000 -#define PCIE_TL_TL_CONTROL_CRC_SWAP_ALIGN 0 -#define PCIE_TL_TL_CONTROL_CRC_SWAP_BITS 1 -#define PCIE_TL_TL_CONTROL_CRC_SWAP_SHIFT 22 - -/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_CA_ERROR [21:21] */ -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_MASK 0x00200000 -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_ALIGN 0 -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_BITS 1 -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_SHIFT 21 - -/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_UR_ERROR [20:20] */ -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_MASK 0x00100000 -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_ALIGN 0 -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_BITS 1 -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_SHIFT 20 - -/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_RSV_ERROR [19:19] */ -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_MASK 0x00080000 -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_ALIGN 0 -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_BITS 1 -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_SHIFT 19 - -/* PCIE_TL :: TL_CONTROL :: RESERVED_6 [18:18] */ -#define PCIE_TL_TL_CONTROL_RESERVED_6_MASK 0x00040000 -#define PCIE_TL_TL_CONTROL_RESERVED_6_ALIGN 0 -#define PCIE_TL_TL_CONTROL_RESERVED_6_BITS 1 -#define PCIE_TL_TL_CONTROL_RESERVED_6_SHIFT 18 - -/* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_EP_ERROR [17:17] */ -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_MASK 0x00020000 -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_ALIGN 0 -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_BITS 1 -#define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_SHIFT 17 - -/* PCIE_TL :: TL_CONTROL :: ENABLE_BYTECOUNT_CHECK [16:16] */ -#define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_MASK 0x00010000 -#define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_ALIGN 0 -#define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_BITS 1 -#define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_SHIFT 16 - -/* PCIE_TL :: TL_CONTROL :: NOT_USED [15:14] */ -#define PCIE_TL_TL_CONTROL_NOT_USED_MASK 0x0000c000 -#define PCIE_TL_TL_CONTROL_NOT_USED_ALIGN 0 -#define PCIE_TL_TL_CONTROL_NOT_USED_BITS 2 -#define PCIE_TL_TL_CONTROL_NOT_USED_SHIFT 14 - -/* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DR [13:11] */ -#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_MASK 0x00003800 -#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_ALIGN 0 -#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_BITS 3 -#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_SHIFT 11 - -/* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DW [10:08] */ -#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_MASK 0x00000700 -#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_ALIGN 0 -#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_BITS 3 -#define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_SHIFT 8 - -/* PCIE_TL :: TL_CONTROL :: NOT_USED_0 [07:06] */ -#define PCIE_TL_TL_CONTROL_NOT_USED_0_MASK 0x000000c0 -#define PCIE_TL_TL_CONTROL_NOT_USED_0_ALIGN 0 -#define PCIE_TL_TL_CONTROL_NOT_USED_0_BITS 2 -#define PCIE_TL_TL_CONTROL_NOT_USED_0_SHIFT 6 - -/* PCIE_TL :: TL_CONTROL :: NOT_USED_1 [05:00] */ -#define PCIE_TL_TL_CONTROL_NOT_USED_1_MASK 0x0000003f -#define PCIE_TL_TL_CONTROL_NOT_USED_1_ALIGN 0 -#define PCIE_TL_TL_CONTROL_NOT_USED_1_BITS 6 -#define PCIE_TL_TL_CONTROL_NOT_USED_1_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: TRANSACTION_CONFIGURATION - ***************************************************************************/ -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_RETRY_BUFFER_TIMING_MOD [31:31] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_MASK 0x80000000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_SHIFT 31 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_0 [30:30] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_MASK 0x40000000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_SHIFT 30 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_SINGLE_SHOT_ENABLE [29:29] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_MASK 0x20000000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_SHIFT 29 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_1 [28:28] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_MASK 0x10000000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_SHIFT 28 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: SELECT_CORE_CLOCK_OVERRIDE [27:27] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_MASK 0x08000000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_SHIFT 27 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: CQ9139_FIX_ENABLE [26:26] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_MASK 0x04000000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_SHIFT 26 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CMPT_PWR_CHECK [25:25] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_MASK 0x02000000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_SHIFT 25 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12696_FIX [24:24] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_MASK 0x01000000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_SHIFT 24 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: DEVICE_SERIAL_NO_OVERRIDE [23:23] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_MASK 0x00800000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_SHIFT 23 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12455_FIX [22:22] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_MASK 0x00400000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_SHIFT 22 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_TC_VC_FILTERING_CHECK [21:21] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_MASK 0x00200000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_SHIFT 21 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: DONT_GEN_HOT_PLUG_MSG [20:20] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_MASK 0x00100000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_SHIFT 20 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: IGNORE_HOTPLUG_MSG [19:19] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_MASK 0x00080000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_SHIFT 19 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_MULTMSG_CAPABLE [18:16] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_MASK 0x00070000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_BITS 3 -#define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_SHIFT 16 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: DATA_SELECT_LIMIT [15:12] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_MASK 0x0000f000 -#define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_BITS 4 -#define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_SHIFT 12 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_PL [11:11] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_MASK 0x00000800 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_SHIFT 11 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_DL [10:10] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_MASK 0x00000400 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_SHIFT 10 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_TL [09:09] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_MASK 0x00000200 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_SHIFT 9 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_2 [08:07] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_MASK 0x00000180 -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_BITS 2 -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_SHIFT 7 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: PCIE_POWER_BUDGET_CAP_ENABLE [06:06] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_MASK 0x00000040 -#define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_SHIFT 6 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: LOM_CONFIGURATION [05:05] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_MASK 0x00000020 -#define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_SHIFT 5 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: CONCATE_SELECT [04:04] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_MASK 0x00000010 -#define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_SHIFT 4 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_3 [03:03] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_MASK 0x00000008 -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_SHIFT 3 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9468_FIX [02:02] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_MASK 0x00000004 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_SHIFT 2 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: POWER_STATE_WRITE_MEM_ENABLE [01:01] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_MASK 0x00000002 -#define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_SHIFT 1 - -/* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9709_ENABLE [00:00] */ -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_MASK 0x00000001 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_ALIGN 0 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_BITS 1 -#define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC - ***************************************************************************/ -/* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: RESERVED_0 [31:00] */ -#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_MASK 0xffffffff -#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_ALIGN 0 -#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_BITS 32 -#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 - ***************************************************************************/ -/* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 :: RESERVED_0 [31:00] */ -#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_MASK 0xffffffff -#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_ALIGN 0 -#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_BITS 32 -#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC - ***************************************************************************/ -/* PCIE_TL :: DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: REG_MADDR_UPR [31:00] */ -#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_MASK 0xffffffff -#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_ALIGN 0 -#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_BITS 32 -#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 - ***************************************************************************/ -/* PCIE_TL :: DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 :: REG_MADDR_LWR [31:00] */ -#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_MASK 0xffffffff -#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_ALIGN 0 -#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_BITS 32 -#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC - ***************************************************************************/ -/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: REG_MLEN_BE [31:24] */ -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_MASK 0xff000000 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_ALIGN 0 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_BITS 8 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_SHIFT 24 - -/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_FIRST_DW_BYTE_ENABLES [23:20] */ -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_MASK 0x00f00000 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_ALIGN 0 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_BITS 4 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_SHIFT 20 - -/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_LAST_DW_BYTE_ENABLES [19:16] */ -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_MASK 0x000f0000 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_ALIGN 0 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_BITS 4 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_SHIFT 16 - -/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: RESERVED_0 [15:11] */ -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_MASK 0x0000f800 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_ALIGN 0 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_BITS 5 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_SHIFT 11 - -/* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_DW_LENGTH [10:00] */ -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_MASK 0x000007ff -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_ALIGN 0 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_BITS 11 -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC - ***************************************************************************/ -/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: REG_MTAG_ATTR [31:19] */ -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_MASK 0xfff80000 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_ALIGN 0 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_BITS 13 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_SHIFT 19 - -/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_FUNCTION [18:16] */ -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_MASK 0x00070000 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_ALIGN 0 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_BITS 3 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_SHIFT 16 - -/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_0 [15:13] */ -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_ALIGN 0 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_BITS 3 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_SHIFT 13 - -/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_ATTRIBUTES [12:08] */ -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_MASK 0x00001f00 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_ALIGN 0 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_BITS 5 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_SHIFT 8 - -/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_1 [07:05] */ -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_ALIGN 0 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_BITS 3 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_SHIFT 5 - -/* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_TAG [04:00] */ -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_MASK 0x0000001f -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_ALIGN 0 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_BITS 5 -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC - ***************************************************************************/ -/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: REG_SPLIT_ID [31:16] */ -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_MASK 0xffff0000 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_ALIGN 0 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_BITS 16 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_SHIFT 16 - -/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_0 [15:13] */ -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_ALIGN 0 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_BITS 3 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_SHIFT 13 - -/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_ATTRIBUTES [12:11] */ -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_MASK 0x00001800 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_ALIGN 0 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_BITS 2 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_SHIFT 11 - -/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TC [10:08] */ -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_MASK 0x00000700 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_ALIGN 0 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_BITS 3 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_SHIFT 8 - -/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_1 [07:05] */ -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_ALIGN 0 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_BITS 3 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_SHIFT 5 - -/* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TAG [04:00] */ -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_MASK 0x0000001f -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_ALIGN 0 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_BITS 5 -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC - ***************************************************************************/ -/* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: REG_SPLIT_LEN [31:13] */ -#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_MASK 0xffffe000 -#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_ALIGN 0 -#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_BITS 19 -#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_SHIFT 13 - -/* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: READ_DMA_SPLIT_INITIAL_BYTE_COUNT [12:00] */ -#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_MASK 0x00001fff -#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_ALIGN 0 -#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_BITS 13 -#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC - ***************************************************************************/ -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: REG_SM_R0_R3 [31:31] */ -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_MASK 0x80000000 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_ALIGN 0 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_BITS 1 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_SHIFT 31 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_DATA_STATE_MACHINE [30:28] */ -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_MASK 0x70000000 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_ALIGN 0 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_BITS 3 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_SHIFT 28 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE [27:23] */ -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_MASK 0x0f800000 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_ALIGN 0 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_BITS 5 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_SHIFT 23 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: RESERVED_0 [22:07] */ -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_MASK 0x007fff80 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_ALIGN 0 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_BITS 16 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_SHIFT 7 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_RAW_REQUEST [06:06] */ -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_MASK 0x00000040 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_ALIGN 0 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_BITS 1 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_SHIFT 6 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_RAW_REQUEST [05:05] */ -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_MASK 0x00000020 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_ALIGN 0 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_BITS 1 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_SHIFT 5 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: INTERRUPT_MSG_GATED_REQUEST [04:04] */ -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_MASK 0x00000010 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_ALIGN 0 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_BITS 1 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_SHIFT 4 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: MSI_DMA_GATED_REQUEST [03:03] */ -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_MASK 0x00000008 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_ALIGN 0 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_BITS 1 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_SHIFT 3 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TARGET_COMPLETION_OR_MSG_GATED_REQUEST [02:02] */ -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_MASK 0x00000004 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_ALIGN 0 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_BITS 1 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_SHIFT 2 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_GATED_REQUEST [01:01] */ -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_MASK 0x00000002 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_ALIGN 0 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_BITS 1 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_SHIFT 1 - -/* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_GATED_REQUEST [00:00] */ -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_MASK 0x00000001 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_ALIGN 0 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_BITS 1 -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC - ***************************************************************************/ -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: REG_DMA_CMPT_MISC2 [31:29] */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_MASK 0xe0000000 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_ALIGN 0 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_BITS 3 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_SHIFT 29 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_BYTE_LENGTH_REMAINING [28:16] */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_MASK 0x1fff0000 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_ALIGN 0 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_BITS 13 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_SHIFT 16 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: NOT_USED [15:15] */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_MASK 0x00008000 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_ALIGN 0 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_BITS 1 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_SHIFT 15 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED [14:14] */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_MASK 0x00004000 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_ALIGN 0 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_BITS 1 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_SHIFT 14 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED [13:13] */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_MASK 0x00002000 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_ALIGN 0 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_BITS 1 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_SHIFT 13 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1 [12:12] */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_MASK 0x00001000 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_ALIGN 0 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_BITS 1 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_SHIFT 12 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST [11:11] */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_MASK 0x00000800 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_ALIGN 0 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_BITS 1 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_SHIFT 11 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS [10:10] */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_MASK 0x00000400 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_ALIGN 0 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_BITS 1 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_SHIFT 10 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_FULLY [09:09] */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_MASK 0x00000200 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_ALIGN 0 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_BITS 1 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_SHIFT 9 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_DW_DATA_VALID_ADDRESS_ACK [08:08] */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_MASK 0x00000100 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_ALIGN 0 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_BITS 1 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_SHIFT 8 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER [07:04] */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_MASK 0x000000f0 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_ALIGN 0 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_BITS 4 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_SHIFT 4 - -/* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: FRAME_DEAD_TIME_ERROR_COUNTER [03:00] */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_MASK 0x0000000f -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_ALIGN 0 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_BITS 4 -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC - ***************************************************************************/ -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: REG_SPLITCTL_MISC0 [31:29] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_MASK 0xe0000000 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_BITS 3 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_SHIFT 29 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING [28:16] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_MASK 0x1fff0000 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_BITS 13 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_SHIFT 16 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID [15:00] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_MASK 0x0000ffff -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_BITS 16 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC - ***************************************************************************/ -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: REG_SPLITCTL_MISC1 [31:16] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_MASK 0xffff0000 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_BITS 16 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_SHIFT 16 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_0 [15:15] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_MASK 0x00008000 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_BITS 1 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_SHIFT 15 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS [14:08] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_MASK 0x00007f00 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_BITS 7 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_SHIFT 8 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_1 [07:07] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_MASK 0x00000080 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_BITS 1 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_SHIFT 7 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE [06:05] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_MASK 0x00000060 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_BITS 2 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_SHIFT 5 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_TAG [04:00] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_MASK 0x0000001f -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_BITS 5 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC - ***************************************************************************/ -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: REG_SPLITCTL_MISC2 [31:31] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_MASK 0x80000000 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_BITS 1 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_SHIFT 31 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS [30:30] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_MASK 0x40000000 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_BITS 1 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_SHIFT 30 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_VALID_TAG [29:29] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_MASK 0x20000000 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_BITS 1 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_SHIFT 29 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: UPDATED_BYTE_COUNT [28:16] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_MASK 0x1fff0000 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_BITS 13 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_SHIFT 16 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: RESERVED_0 [15:08] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_MASK 0x0000ff00 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_BITS 8 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_SHIFT 8 - -/* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: SPLIT_TABLE_VALID_ARRAY [07:00] */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_MASK 0x000000ff -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_ALIGN 0 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_BITS 8 -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO - ***************************************************************************/ -/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: RESERVED_0 [31:17] */ -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_MASK 0xfffe0000 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_ALIGN 0 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_BITS 15 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_SHIFT 17 - -/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: CONFIG_WRITE_INDICATER [16:16] */ -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_MASK 0x00010000 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_ALIGN 0 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_BITS 1 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_SHIFT 16 - -/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: BUS_NUMBER [15:08] */ -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_MASK 0x0000ff00 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_ALIGN 0 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_BITS 8 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_SHIFT 8 - -/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: DEVICE_NUMBER [07:03] */ -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_MASK 0x000000f8 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_ALIGN 0 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_BITS 5 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_SHIFT 3 - -/* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: FUNCTION_NUMBER [02:00] */ -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_MASK 0x00000007 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_ALIGN 0 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_BITS 3 -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_SHIFT 0 - - -/**************************************************************************** - * PCIE_TL :: TL_DEBUG - ***************************************************************************/ -/* PCIE_TL :: TL_DEBUG :: A4_DEVICE_INDICATION_BIT [31:31] */ -#define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_MASK 0x80000000 -#define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_ALIGN 0 -#define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_BITS 1 -#define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_SHIFT 31 - -/* PCIE_TL :: TL_DEBUG :: B1_DEVICE_INDICATION_BIT [30:30] */ -#define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_MASK 0x40000000 -#define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_ALIGN 0 -#define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_BITS 1 -#define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_SHIFT 30 - -/* PCIE_TL :: TL_DEBUG :: RESERVED_0 [29:00] */ -#define PCIE_TL_TL_DEBUG_RESERVED_0_MASK 0x3fffffff -#define PCIE_TL_TL_DEBUG_RESERVED_0_ALIGN 0 -#define PCIE_TL_TL_DEBUG_RESERVED_0_BITS 30 -#define PCIE_TL_TL_DEBUG_RESERVED_0_SHIFT 0 - - -/**************************************************************************** - * BCM70012_TGT_TOP_PCIE_DLL - ***************************************************************************/ -/**************************************************************************** - * PCIE_DLL :: DATA_LINK_CONTROL - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_0 [31:30] */ -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_MASK 0xc0000000 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_BITS 2 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_SHIFT 30 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: CQ28001_FIX_ENABLE [29:29] */ -#define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_MASK 0x20000000 -#define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_SHIFT 29 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: CQ27820_FIX_ENABLE [28:28] */ -#define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_MASK 0x10000000 -#define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_SHIFT 28 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: ASPM_L1_ENABLE [27:27] */ -#define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_MASK 0x08000000 -#define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_SHIFT 27 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_1 [26:25] */ -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_MASK 0x06000000 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_BITS 2 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_SHIFT 25 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: CQ11211 [24:24] */ -#define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_MASK 0x01000000 -#define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_SHIFT 24 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_2 [23:23] */ -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_MASK 0x00800000 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_SHIFT 23 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_3 [22:22] */ -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_MASK 0x00400000 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_SHIFT 22 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_4 [21:21] */ -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_MASK 0x00200000 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_SHIFT 21 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_5 [20:20] */ -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_MASK 0x00100000 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_SHIFT 20 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_6 [19:19] */ -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_MASK 0x00080000 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_SHIFT 19 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: PLL_REFSEL_SWITCH_CONTROL_CQ11011 [18:18] */ -#define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_MASK 0x00040000 -#define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_SHIFT 18 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_7 [17:17] */ -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_MASK 0x00020000 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_SHIFT 17 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL [16:16] */ -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_MASK 0x00010000 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_SHIFT 16 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_TRANSMITTER [15:15] */ -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_MASK 0x00008000 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_SHIFT 15 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_PLL [14:14] */ -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_MASK 0x00004000 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_SHIFT 14 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_RECEIVER [13:13] */ -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_MASK 0x00002000 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_SHIFT 13 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_BEACON [12:12] */ -#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_MASK 0x00001000 -#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_SHIFT 12 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: AUTOMATIC_TIMER_THRESHOLD_ENABLE [11:11] */ -#define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_MASK 0x00000800 -#define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_SHIFT 11 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_DLLP_TIMEOUT_MECHANISM [10:10] */ -#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_MASK 0x00000400 -#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_SHIFT 10 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: CHECK_RECEIVE_FLOW_CONTROL_CREDITS [09:09] */ -#define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_MASK 0x00000200 -#define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_SHIFT 9 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: LINK_ENABLE [08:08] */ -#define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_MASK 0x00000100 -#define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_BITS 1 -#define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_SHIFT 8 - -/* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL_2 [07:00] */ -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_MASK 0x000000ff -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_ALIGN 0 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_BITS 8 -#define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: DATA_LINK_STATUS - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_0 [31:26] */ -#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_MASK 0xfc000000 -#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_BITS 6 -#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_SHIFT 26 - -/* PCIE_DLL :: DATA_LINK_STATUS :: PHY_LINK_STATE [25:23] */ -#define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_MASK 0x03800000 -#define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_BITS 3 -#define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_SHIFT 23 - -/* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_STATE [22:19] */ -#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_MASK 0x00780000 -#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_BITS 4 -#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_SHIFT 19 - -/* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_SUB_STATE [18:17] */ -#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_MASK 0x00060000 -#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_BITS 2 -#define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_SHIFT 17 - -/* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_UP [16:16] */ -#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_MASK 0x00010000 -#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_BITS 1 -#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_SHIFT 16 - -/* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_1 [15:11] */ -#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_MASK 0x0000f800 -#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_BITS 5 -#define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_SHIFT 11 - -/* PCIE_DLL :: DATA_LINK_STATUS :: PME_TURN_OFF_STATUS_IN_D0 [10:10] */ -#define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_MASK 0x00000400 -#define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_BITS 1 -#define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_SHIFT 10 - -/* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_UPDATE_TIMEOUT [09:09] */ -#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_MASK 0x00000200 -#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_BITS 1 -#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_SHIFT 9 - -/* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_RECEIVE_OVERFLOW [08:08] */ -#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_MASK 0x00000100 -#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_BITS 1 -#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_SHIFT 8 - -/* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR [07:07] */ -#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_MASK 0x00000080 -#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_BITS 1 -#define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_SHIFT 7 - -/* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_PROTOCOL_ERROR [06:06] */ -#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_MASK 0x00000040 -#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_BITS 1 -#define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_SHIFT 6 - -/* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_ROLLOVER [05:05] */ -#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_MASK 0x00000020 -#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_BITS 1 -#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_SHIFT 5 - -/* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_TIMEOUT [04:04] */ -#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_MASK 0x00000010 -#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_BITS 1 -#define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_SHIFT 4 - -/* PCIE_DLL :: DATA_LINK_STATUS :: NAK_RECEIVED [03:03] */ -#define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_MASK 0x00000008 -#define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_BITS 1 -#define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_SHIFT 3 - -/* PCIE_DLL :: DATA_LINK_STATUS :: DLLP_ERROR [02:02] */ -#define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_MASK 0x00000004 -#define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_BITS 1 -#define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_SHIFT 2 - -/* PCIE_DLL :: DATA_LINK_STATUS :: BAD_TLP_SEQUENCE_NUMBER [01:01] */ -#define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_MASK 0x00000002 -#define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_BITS 1 -#define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_SHIFT 1 - -/* PCIE_DLL :: DATA_LINK_STATUS :: TLP_ERROR [00:00] */ -#define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_MASK 0x00000001 -#define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_ALIGN 0 -#define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_BITS 1 -#define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: DATA_LINK_ATTENTION - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_ATTENTION :: RESERVED_0 [31:06] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_MASK 0xffffffc0 -#define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_BITS 26 -#define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_SHIFT 6 - -/* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_PACKET_TEST_INDICATOR [05:05] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_MASK 0x00000020 -#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_BITS 1 -#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_SHIFT 5 - -/* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR [04:04] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_MASK 0x00000010 -#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_BITS 1 -#define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_SHIFT 4 - -/* PCIE_DLL :: DATA_LINK_ATTENTION :: NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR [03:03] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_MASK 0x00000008 -#define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_BITS 1 -#define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_SHIFT 3 - -/* PCIE_DLL :: DATA_LINK_ATTENTION :: DLLP_ERROR_COUNTER_ATTENTION_INDICATOR [02:02] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000004 -#define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_BITS 1 -#define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 2 - -/* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR [01:01] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_MASK 0x00000002 -#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_BITS 1 -#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_SHIFT 1 - -/* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_ERROR_COUNTER_ATTENTION_INDICATOR [00:00] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000001 -#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_BITS 1 -#define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: DATA_LINK_ATTENTION_MASK - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: RESERVED_0 [31:08] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_BITS 24 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_SHIFT 8 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: UNUSED_0 [07:06] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_MASK 0x000000c0 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_BITS 2 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_SHIFT 6 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK [05:05] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_MASK 0x00000020 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_BITS 1 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_SHIFT 5 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_ERROR_ATTENTION_MASK [04:04] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_MASK 0x00000010 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_BITS 1 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_SHIFT 4 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: NAK_RECEIVED_COUNTER_ATTENTION_MASK [03:03] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_MASK 0x00000008 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_BITS 1 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_SHIFT 3 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DLLP_ERROR_COUNTER_ATTENTION_MASK [02:02] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000004 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_BITS 1 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 2 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK [01:01] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_MASK 0x00000002 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_BITS 1 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_SHIFT 1 - -/* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_ERROR_COUNTER_ATTENTION_MASK [00:00] */ -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000001 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_BITS 1 -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG - ***************************************************************************/ -/* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ -#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 -#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 -#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 -#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 - -/* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: NEXT_TRANSMIT_SEQUENCE_NUMBER [11:00] */ -#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff -#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 -#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_BITS 12 -#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG - ***************************************************************************/ -/* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ -#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 -#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 -#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 -#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 - -/* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ -#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff -#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 -#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_BITS 12 -#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG - ***************************************************************************/ -/* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ -#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 -#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 -#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 -#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 - -/* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: PURGED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ -#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff -#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 -#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_BITS 12 -#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG - ***************************************************************************/ -/* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ -#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 -#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 -#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 -#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 - -/* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RECEIVE_SEQUENCE_NUMBER [11:00] */ -#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_MASK 0x00000fff -#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_ALIGN 0 -#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_BITS 12 -#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: DATA_LINK_REPLAY - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_REPLAY :: RESERVED_0 [31:23] */ -#define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_MASK 0xff800000 -#define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_ALIGN 0 -#define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_BITS 9 -#define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_SHIFT 23 - -/* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_TIMEOUT_VALUE [22:10] */ -#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_MASK 0x007ffc00 -#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_BITS 13 -#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_SHIFT 10 - -/* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_BUFFER_SIZE [09:00] */ -#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_MASK 0x000003ff -#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_BITS 10 -#define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: DATA_LINK_ACK_TIMEOUT - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: RESERVED_0 [31:11] */ -#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_MASK 0xfffff800 -#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_BITS 21 -#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_SHIFT 11 - -/* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: ACK_LATENCY_TIMEOUT_VALUE [10:00] */ -#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_MASK 0x000007ff -#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_BITS 11 -#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD - ***************************************************************************/ -/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: RESERVED_0 [31:24] */ -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_MASK 0xff000000 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_ALIGN 0 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_BITS 8 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_SHIFT 24 - -/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0_STAY_TIME [23:20] */ -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_MASK 0x00f00000 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_ALIGN 0 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_BITS 4 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_SHIFT 20 - -/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_STAY_TIME [19:16] */ -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_MASK 0x000f0000 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_ALIGN 0 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_BITS 4 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_SHIFT 16 - -/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_THRESHOLD [15:08] */ -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_MASK 0x0000ff00 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_ALIGN 0 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_BITS 8 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_SHIFT 8 - -/* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0S_THRESHOLD [07:00] */ -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_MASK 0x000000ff -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_ALIGN 0 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_BITS 8 -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG - ***************************************************************************/ -/* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RESERVED_0 [31:11] */ -#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 -#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_ALIGN 0 -#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_BITS 21 -#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_SHIFT 11 - -/* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RETRY_BUFFER_WRITE_POINTER [10:00] */ -#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_MASK 0x000007ff -#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_ALIGN 0 -#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_BITS 11 -#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG - ***************************************************************************/ -/* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RESERVED_0 [31:11] */ -#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 -#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_ALIGN 0 -#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_BITS 21 -#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_SHIFT 11 - -/* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RETRY_BUFFER_READ_POINTER [10:00] */ -#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_MASK 0x000007ff -#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_ALIGN 0 -#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_BITS 11 -#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG - ***************************************************************************/ -/* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RESERVED_0 [31:11] */ -#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 -#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_ALIGN 0 -#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_BITS 21 -#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_SHIFT 11 - -/* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RETRY_BUFFER_PURGED_POINTER [10:00] */ -#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_MASK 0x000007ff -#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_ALIGN 0 -#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_BITS 11 -#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: RETRY_BUFFER_READ_WRITE_DEBUG_PORT - ***************************************************************************/ -/* PCIE_DLL :: RETRY_BUFFER_READ_WRITE_DEBUG_PORT :: RETRY_BUFFER_DATA [31:00] */ -#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_MASK 0xffffffff -#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_ALIGN 0 -#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_BITS 32 -#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: ERROR_COUNT_THRESHOLD - ***************************************************************************/ -/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: RESERVED_0 [31:15] */ -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_MASK 0xffff8000 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_ALIGN 0 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_BITS 17 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_SHIFT 15 - -/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD [14:12] */ -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_MASK 0x00007000 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_ALIGN 0 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_BITS 3 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_SHIFT 12 - -/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: NAK_RECEIVED_COUNT_THRESHOLD [11:08] */ -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_MASK 0x00000f00 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_ALIGN 0 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_BITS 4 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_SHIFT 8 - -/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: DLLP_ERROR_COUNT_THRESHOLD [07:04] */ -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_MASK 0x000000f0 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_ALIGN 0 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_BITS 4 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_SHIFT 4 - -/* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: TLP_ERROR_COUNT_THRESHOLD [03:00] */ -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_MASK 0x0000000f -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_ALIGN 0 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_BITS 4 -#define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: TL_ERROR_COUNTER - ***************************************************************************/ -/* PCIE_DLL :: TL_ERROR_COUNTER :: RESERVED_0 [31:24] */ -#define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_MASK 0xff000000 -#define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_ALIGN 0 -#define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_BITS 8 -#define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_SHIFT 24 - -/* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_BAD_SEQUENCE_NUMBER_COUNTER [23:16] */ -#define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_MASK 0x00ff0000 -#define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_ALIGN 0 -#define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_BITS 8 -#define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_SHIFT 16 - -/* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_ERROR_COUNTER [15:00] */ -#define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_MASK 0x0000ffff -#define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_ALIGN 0 -#define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_BITS 16 -#define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: DLLP_ERROR_COUNTER - ***************************************************************************/ -/* PCIE_DLL :: DLLP_ERROR_COUNTER :: RESERVED_0 [31:16] */ -#define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 -#define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_ALIGN 0 -#define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_BITS 16 -#define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_SHIFT 16 - -/* PCIE_DLL :: DLLP_ERROR_COUNTER :: DLLP_ERROR_COUNTER [15:00] */ -#define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_MASK 0x0000ffff -#define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_ALIGN 0 -#define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_BITS 16 -#define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: NAK_RECEIVED_COUNTER - ***************************************************************************/ -/* PCIE_DLL :: NAK_RECEIVED_COUNTER :: RESERVED_0 [31:16] */ -#define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_MASK 0xffff0000 -#define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_ALIGN 0 -#define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_BITS 16 -#define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_SHIFT 16 - -/* PCIE_DLL :: NAK_RECEIVED_COUNTER :: NAK_RECEIVED_COUNTER [15:00] */ -#define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_MASK 0x0000ffff -#define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_ALIGN 0 -#define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_BITS 16 -#define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: DATA_LINK_TEST - ***************************************************************************/ -/* PCIE_DLL :: DATA_LINK_TEST :: RESERVED_0 [31:16] */ -#define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_MASK 0xffff0000 -#define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_BITS 16 -#define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_SHIFT 16 - -/* PCIE_DLL :: DATA_LINK_TEST :: STORE_RECEIVE_TLPS [15:15] */ -#define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_MASK 0x00008000 -#define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_SHIFT 15 - -/* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_TLPS [14:14] */ -#define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_MASK 0x00004000 -#define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_SHIFT 14 - -/* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_DLLPS [13:13] */ -#define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_MASK 0x00002000 -#define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_SHIFT 13 - -/* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PHY_LINK_UP [12:12] */ -#define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_MASK 0x00001000 -#define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_SHIFT 12 - -/* PCIE_DLL :: DATA_LINK_TEST :: BYPASS_FLOW_CONTROL [11:11] */ -#define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_MASK 0x00000800 -#define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_SHIFT 11 - -/* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE [10:10] */ -#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_MASK 0x00000400 -#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_SHIFT 10 - -/* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_OVERSTRESS_TEST_MODE [09:09] */ -#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_MASK 0x00000200 -#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_SHIFT 9 - -/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_SLOW_CLOCK [08:08] */ -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_MASK 0x00000100 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_SHIFT 8 - -/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_COMPLETION_TIMER [07:07] */ -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_MASK 0x00000080 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_SHIFT 7 - -/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_REPLAY_TIMER [06:06] */ -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_MASK 0x00000040 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_SHIFT 6 - -/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_ACK_LATENCY_TIMER [05:05] */ -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_MASK 0x00000020 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_SHIFT 5 - -/* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_PME_SERVICE_TIMER [04:04] */ -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_MASK 0x00000010 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_SHIFT 4 - -/* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PURGE [03:03] */ -#define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_MASK 0x00000008 -#define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_SHIFT 3 - -/* PCIE_DLL :: DATA_LINK_TEST :: FORCE_RETRY [02:02] */ -#define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_MASK 0x00000004 -#define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_SHIFT 2 - -/* PCIE_DLL :: DATA_LINK_TEST :: INVERT_CRC [01:01] */ -#define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_MASK 0x00000002 -#define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_SHIFT 1 - -/* PCIE_DLL :: DATA_LINK_TEST :: SEND_BAD_CRC_BIT [00:00] */ -#define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_MASK 0x00000001 -#define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_ALIGN 0 -#define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_BITS 1 -#define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: PACKET_BIST - ***************************************************************************/ -/* PCIE_DLL :: PACKET_BIST :: RESERVED_0 [31:24] */ -#define PCIE_DLL_PACKET_BIST_RESERVED_0_MASK 0xff000000 -#define PCIE_DLL_PACKET_BIST_RESERVED_0_ALIGN 0 -#define PCIE_DLL_PACKET_BIST_RESERVED_0_BITS 8 -#define PCIE_DLL_PACKET_BIST_RESERVED_0_SHIFT 24 - -/* PCIE_DLL :: PACKET_BIST :: PACKET_CHECKER_LOCKED [23:23] */ -#define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_MASK 0x00800000 -#define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_ALIGN 0 -#define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_BITS 1 -#define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_SHIFT 23 - -/* PCIE_DLL :: PACKET_BIST :: RECEIVE_MISMATCH [22:22] */ -#define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_MASK 0x00400000 -#define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_ALIGN 0 -#define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_BITS 1 -#define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_SHIFT 22 - -/* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_TLP_LENGTH [21:21] */ -#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_MASK 0x00200000 -#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_ALIGN 0 -#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_BITS 1 -#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_SHIFT 21 - -/* PCIE_DLL :: PACKET_BIST :: TLP_LENGTH [20:10] */ -#define PCIE_DLL_PACKET_BIST_TLP_LENGTH_MASK 0x001ffc00 -#define PCIE_DLL_PACKET_BIST_TLP_LENGTH_ALIGN 0 -#define PCIE_DLL_PACKET_BIST_TLP_LENGTH_BITS 11 -#define PCIE_DLL_PACKET_BIST_TLP_LENGTH_SHIFT 10 - -/* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_IPG_LENGTH [09:09] */ -#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_MASK 0x00000200 -#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_ALIGN 0 -#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_BITS 1 -#define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_SHIFT 9 - -/* PCIE_DLL :: PACKET_BIST :: IPG_LENGTH [08:02] */ -#define PCIE_DLL_PACKET_BIST_IPG_LENGTH_MASK 0x000001fc -#define PCIE_DLL_PACKET_BIST_IPG_LENGTH_ALIGN 0 -#define PCIE_DLL_PACKET_BIST_IPG_LENGTH_BITS 7 -#define PCIE_DLL_PACKET_BIST_IPG_LENGTH_SHIFT 2 - -/* PCIE_DLL :: PACKET_BIST :: TRANSMIT_START [01:01] */ -#define PCIE_DLL_PACKET_BIST_TRANSMIT_START_MASK 0x00000002 -#define PCIE_DLL_PACKET_BIST_TRANSMIT_START_ALIGN 0 -#define PCIE_DLL_PACKET_BIST_TRANSMIT_START_BITS 1 -#define PCIE_DLL_PACKET_BIST_TRANSMIT_START_SHIFT 1 - -/* PCIE_DLL :: PACKET_BIST :: ENABLE_PACKET_GENERATOR_TEST_MODE [00:00] */ -#define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_MASK 0x00000001 -#define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_ALIGN 0 -#define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_BITS 1 -#define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_SHIFT 0 - - -/**************************************************************************** - * PCIE_DLL :: LINK_PCIE_1_1_CONTROL - ***************************************************************************/ -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_CT_2_0 [31:29] */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_MASK 0xe0000000 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_ALIGN 0 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_BITS 3 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_SHIFT 29 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_SAM_1_0 [28:27] */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_MASK 0x18000000 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_ALIGN 0 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_BITS 2 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_SHIFT 27 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: UNUSED_0 [26:10] */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_MASK 0x07fffc00 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_ALIGN 0 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_BITS 17 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_SHIFT 10 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: SELOCALXTAL [09:09] */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_MASK 0x00000200 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_ALIGN 0 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_BITS 1 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_SHIFT 9 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_PLL_POWERDOWN_DISABLE [08:08] */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_MASK 0x00000100 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_ALIGN 0 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_BITS 1 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_SHIFT 8 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_POWERDOWN_DISABLE [07:07] */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_MASK 0x00000080 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_ALIGN 0 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_BITS 1 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_SHIFT 7 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_D3PM_CLKREQ_DISABLE [06:06] */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_MASK 0x00000040 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_ALIGN 0 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_BITS 1 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_SHIFT 6 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_D3PM_CLKREQ_DISABLE [05:05] */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_MASK 0x00000020 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_ALIGN 0 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_BITS 1 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_SHIFT 5 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_ASPM_CLKREQ_DISABLE [04:04] */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_MASK 0x00000010 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_ALIGN 0 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_BITS 1 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_SHIFT 4 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_PD_W_O_CLKREQ [03:03] */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_MASK 0x00000008 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_ALIGN 0 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_BITS 1 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_SHIFT 3 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DASPM10USTIMER [02:02] */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_MASK 0x00000004 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_ALIGN 0 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_BITS 1 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_SHIFT 2 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFFU_EL1 [01:01] */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_MASK 0x00000002 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_ALIGN 0 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_BITS 1 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_SHIFT 1 - -/* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFLOWCTLUPDATE1_1 [00:00] */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_MASK 0x00000001 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_ALIGN 0 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_BITS 1 -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_SHIFT 0 - - -/**************************************************************************** - * BCM70012_TGT_TOP_PCIE_PHY - ***************************************************************************/ -/**************************************************************************** - * PCIE_PHY :: PHY_MODE - ***************************************************************************/ -/* PCIE_PHY :: PHY_MODE :: RESERVED_0 [31:04] */ -#define PCIE_PHY_PHY_MODE_RESERVED_0_MASK 0xfffffff0 -#define PCIE_PHY_PHY_MODE_RESERVED_0_ALIGN 0 -#define PCIE_PHY_PHY_MODE_RESERVED_0_BITS 28 -#define PCIE_PHY_PHY_MODE_RESERVED_0_SHIFT 4 - -/* PCIE_PHY :: PHY_MODE :: UPSTREAM_DEV [03:03] */ -#define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_MASK 0x00000008 -#define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_ALIGN 0 -#define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_BITS 1 -#define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_SHIFT 3 - -/* PCIE_PHY :: PHY_MODE :: SERDES_SA_MODE [02:02] */ -#define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_MASK 0x00000004 -#define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_ALIGN 0 -#define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_BITS 1 -#define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_SHIFT 2 - -/* PCIE_PHY :: PHY_MODE :: LINK_DISABLE [01:01] */ -#define PCIE_PHY_PHY_MODE_LINK_DISABLE_MASK 0x00000002 -#define PCIE_PHY_PHY_MODE_LINK_DISABLE_ALIGN 0 -#define PCIE_PHY_PHY_MODE_LINK_DISABLE_BITS 1 -#define PCIE_PHY_PHY_MODE_LINK_DISABLE_SHIFT 1 - -/* PCIE_PHY :: PHY_MODE :: SOFT_RESET [00:00] */ -#define PCIE_PHY_PHY_MODE_SOFT_RESET_MASK 0x00000001 -#define PCIE_PHY_PHY_MODE_SOFT_RESET_ALIGN 0 -#define PCIE_PHY_PHY_MODE_SOFT_RESET_BITS 1 -#define PCIE_PHY_PHY_MODE_SOFT_RESET_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_LINK_STATUS - ***************************************************************************/ -/* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_0 [31:10] */ -#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_MASK 0xfffffc00 -#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_ALIGN 0 -#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_BITS 22 -#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_SHIFT 10 - -/* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_OVERRUN [09:09] */ -#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_MASK 0x00000200 -#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_ALIGN 0 -#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_BITS 1 -#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_SHIFT 9 - -/* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_UNDERRUN [08:08] */ -#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_MASK 0x00000100 -#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_ALIGN 0 -#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_BITS 1 -#define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_SHIFT 8 - -/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_REQUEST_LOOPBACK [07:07] */ -#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_MASK 0x00000080 -#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_ALIGN 0 -#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_BITS 1 -#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_SHIFT 7 - -/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_DISABLE_SCRAMBLER [06:06] */ -#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_MASK 0x00000040 -#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_ALIGN 0 -#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_BITS 1 -#define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_SHIFT 6 - -/* PCIE_PHY :: PHY_LINK_STATUS :: EXTENDED_SYNCH [05:05] */ -#define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_MASK 0x00000020 -#define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_ALIGN 0 -#define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_BITS 1 -#define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_SHIFT 5 - -/* PCIE_PHY :: PHY_LINK_STATUS :: POLARITY_INVERTED [04:04] */ -#define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_MASK 0x00000010 -#define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_ALIGN 0 -#define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_BITS 1 -#define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_SHIFT 4 - -/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_UP [03:03] */ -#define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_MASK 0x00000008 -#define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_ALIGN 0 -#define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_BITS 1 -#define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_SHIFT 3 - -/* PCIE_PHY :: PHY_LINK_STATUS :: LINK_TRAINING [02:02] */ -#define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_MASK 0x00000004 -#define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_ALIGN 0 -#define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_BITS 1 -#define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_SHIFT 2 - -/* PCIE_PHY :: PHY_LINK_STATUS :: RECEIVE_DATA_VALID [01:01] */ -#define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_MASK 0x00000002 -#define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_ALIGN 0 -#define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_BITS 1 -#define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_SHIFT 1 - -/* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_1 [00:00] */ -#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_MASK 0x00000001 -#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_ALIGN 0 -#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_BITS 1 -#define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_LINK_LTSSM_CONTROL - ***************************************************************************/ -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESERVED_0 [31:08] */ -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_MASK 0xffffff00 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_ALIGN 0 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_BITS 24 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_SHIFT 8 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESCRAMBLE [07:07] */ -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_MASK 0x00000080 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_ALIGN 0 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_BITS 1 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_SHIFT 7 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DETECTSTATE [06:06] */ -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_MASK 0x00000040 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_ALIGN 0 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_BITS 1 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_SHIFT 6 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: POLLINGSTATE [05:05] */ -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_MASK 0x00000020 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_ALIGN 0 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_BITS 1 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_SHIFT 5 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: CONFIGSTATE [04:04] */ -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_MASK 0x00000010 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_ALIGN 0 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_BITS 1 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_SHIFT 4 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RECOVSTATE [03:03] */ -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_MASK 0x00000008 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_ALIGN 0 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_BITS 1 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_SHIFT 3 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: EXTLBSTATE [02:02] */ -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_MASK 0x00000004 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_ALIGN 0 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_BITS 1 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_SHIFT 2 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESETSTATE [01:01] */ -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_MASK 0x00000002 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_ALIGN 0 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_BITS 1 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_SHIFT 1 - -/* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESTATE [00:00] */ -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_MASK 0x00000001 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_ALIGN 0 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_BITS 1 -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER - ***************************************************************************/ -/* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: RESERVED_0 [31:08] */ -#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_MASK 0xffffff00 -#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_ALIGN 0 -#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_BITS 24 -#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_SHIFT 8 - -/* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: LANE_NUMBER [07:00] */ -#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_MASK 0x000000ff -#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_ALIGN 0 -#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_BITS 8 -#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER - ***************************************************************************/ -/* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: RESERVED_0 [31:08] */ -#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_MASK 0xffffff00 -#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_ALIGN 0 -#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_BITS 24 -#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_SHIFT 8 - -/* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: LANE_NUMBER [07:00] */ -#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_MASK 0x000000ff -#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_ALIGN 0 -#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_BITS 8 -#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_LINK_TRAINING_N_FTS - ***************************************************************************/ -/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RESERVED_0 [31:25] */ -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_MASK 0xfe000000 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_ALIGN 0 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_BITS 7 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_SHIFT 25 - -/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE [24:24] */ -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_MASK 0x01000000 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_ALIGN 0 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_BITS 1 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_SHIFT 24 - -/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE_VALUE [23:16] */ -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_MASK 0x00ff0000 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_ALIGN 0 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_BITS 8 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_SHIFT 16 - -/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS [15:08] */ -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_MASK 0x0000ff00 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_ALIGN 0 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_BITS 8 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_SHIFT 8 - -/* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RECEIVER_N_FTS [07:00] */ -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_MASK 0x000000ff -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_ALIGN 0 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_BITS 8 -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_ATTENTION - ***************************************************************************/ -/* PCIE_PHY :: PHY_ATTENTION :: RESERVED_0 [31:08] */ -#define PCIE_PHY_PHY_ATTENTION_RESERVED_0_MASK 0xffffff00 -#define PCIE_PHY_PHY_ATTENTION_RESERVED_0_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_RESERVED_0_BITS 24 -#define PCIE_PHY_PHY_ATTENTION_RESERVED_0_SHIFT 8 - -/* PCIE_PHY :: PHY_ATTENTION :: HOT_RESET [07:07] */ -#define PCIE_PHY_PHY_ATTENTION_HOT_RESET_MASK 0x00000080 -#define PCIE_PHY_PHY_ATTENTION_HOT_RESET_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_HOT_RESET_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_HOT_RESET_SHIFT 7 - -/* PCIE_PHY :: PHY_ATTENTION :: LINK_DOWN [06:06] */ -#define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_MASK 0x00000040 -#define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_SHIFT 6 - -/* PCIE_PHY :: PHY_ATTENTION :: TRAINING_ERROR [05:05] */ -#define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_MASK 0x00000020 -#define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_SHIFT 5 - -/* PCIE_PHY :: PHY_ATTENTION :: BUFFER_OVERRUN [04:04] */ -#define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_MASK 0x00000010 -#define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_SHIFT 4 - -/* PCIE_PHY :: PHY_ATTENTION :: BUFFER_UNDERRUN [03:03] */ -#define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_MASK 0x00000008 -#define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_SHIFT 3 - -/* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_FRAMING_ERROR [02:02] */ -#define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_MASK 0x00000004 -#define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_SHIFT 2 - -/* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_DISPARITY_ERROR [01:01] */ -#define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_MASK 0x00000002 -#define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_SHIFT 1 - -/* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_CODE_ERROR [00:00] */ -#define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_MASK 0x00000001 -#define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_ATTENTION_MASK - ***************************************************************************/ -/* PCIE_PHY :: PHY_ATTENTION_MASK :: RESERVED_0 [31:08] */ -#define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 -#define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_BITS 24 -#define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_SHIFT 8 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: HOT_RESET_MASK [07:07] */ -#define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_MASK 0x00000080 -#define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_SHIFT 7 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: LINK_DOWN_MASK [06:06] */ -#define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_MASK 0x00000040 -#define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_SHIFT 6 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: TRAINING_ERROR_MASK [05:05] */ -#define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_MASK 0x00000020 -#define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_SHIFT 5 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_OVERRUN_MASK [04:04] */ -#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_MASK 0x00000010 -#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_SHIFT 4 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_UNDERRUN_MASK [03:03] */ -#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_MASK 0x00000008 -#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_SHIFT 3 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_FRAME_ERROR_MASK [02:02] */ -#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_MASK 0x00000004 -#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_SHIFT 2 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_DISPARITY_ERROR_MASK [01:01] */ -#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_MASK 0x00000002 -#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_SHIFT 1 - -/* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_CODE_ERROR_MASK [00:00] */ -#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_MASK 0x00000001 -#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_ALIGN 0 -#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_BITS 1 -#define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER - ***************************************************************************/ -/* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: DISPARITY_ERROR_COUNT [31:16] */ -#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_MASK 0xffff0000 -#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_ALIGN 0 -#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_BITS 16 -#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_SHIFT 16 - -/* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: CODE_ERROR_COUNT [15:00] */ -#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_MASK 0x0000ffff -#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_ALIGN 0 -#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_BITS 16 -#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER - ***************************************************************************/ -/* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: RESERVED_0 [31:16] */ -#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 -#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_ALIGN 0 -#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_BITS 16 -#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_SHIFT 16 - -/* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: FRAMING_ERROR_COUNT [15:00] */ -#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_MASK 0x0000ffff -#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_ALIGN 0 -#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_BITS 16 -#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD - ***************************************************************************/ -/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: RESERVED_0 [31:12] */ -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_MASK 0xfffff000 -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_ALIGN 0 -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_BITS 20 -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_SHIFT 12 - -/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: FRAME_ERROR_THRESHOLD [11:08] */ -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_MASK 0x00000f00 -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_ALIGN 0 -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_BITS 4 -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_SHIFT 8 - -/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: DISPARITY_ERROR_THRESHOLD [07:04] */ -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_MASK 0x000000f0 -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_ALIGN 0 -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_BITS 4 -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_SHIFT 4 - -/* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: CODE_ERROR_THRESHOLD [03:00] */ -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_MASK 0x0000000f -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_ALIGN 0 -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_BITS 4 -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_TEST_CONTROL - ***************************************************************************/ -/* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_0 [31:31] */ -#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_MASK 0x80000000 -#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_SHIFT 31 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DELAY_HOTRESET_ENABLE [30:30] */ -#define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_MASK 0x40000000 -#define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_SHIFT 30 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_TSX_MAJORITY_CHECK [29:29] */ -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_MASK 0x20000000 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_SHIFT 29 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_MASK_OFF_BOGUS [28:28] */ -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_MASK 0x10000000 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_SHIFT 28 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_POLARITY_CHECK [27:27] */ -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_MASK 0x08000000 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_SHIFT 27 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_STICKY_POLARITY_CHECK [26:26] */ -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_MASK 0x04000000 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_SHIFT 26 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_1 [25:23] */ -#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_MASK 0x03800000 -#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_BITS 3 -#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_SHIFT 23 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: TWO_OS_RULE_RELAXING [22:22] */ -#define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_MASK 0x00400000 -#define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_SHIFT 22 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_HOT_RESET [21:21] */ -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_MASK 0x00200000 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_SHIFT 21 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_LINK_DOWN_RESET [20:20] */ -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_MASK 0x00100000 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_SHIFT 20 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE [19:19] */ -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_MASK 0x00080000 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_SHIFT 19 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_EXIT [18:18] */ -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_MASK 0x00040000 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_SHIFT 18 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_MASK [17:17] */ -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_MASK 0x00020000 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_SHIFT 17 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_RECOVERY [16:16] */ -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_MASK 0x00010000 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_SHIFT 16 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: RESERVED_0 [15:08] */ -#define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_MASK 0x0000ff00 -#define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_BITS 8 -#define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_SHIFT 8 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_2 [07:04] */ -#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_MASK 0x000000f0 -#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_BITS 4 -#define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_SHIFT 4 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: CQ22100_FIX_DISABLE [03:03] */ -#define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_MASK 0x00000008 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_SHIFT 3 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: TRAINING_BYPASS [02:02] */ -#define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_MASK 0x00000004 -#define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_SHIFT 2 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: EXTERNAL_LOOPBACK [01:01] */ -#define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_MASK 0x00000002 -#define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_SHIFT 1 - -/* PCIE_PHY :: PHY_TEST_CONTROL :: INTERNAL_LOOPBACK [00:00] */ -#define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_MASK 0x00000001 -#define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_ALIGN 0 -#define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_BITS 1 -#define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE - ***************************************************************************/ -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RESERVED_0 [31:18] */ -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_MASK 0xfffc0000 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_ALIGN 0 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_BITS 14 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_SHIFT 18 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEVALUE [17:17] */ -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_MASK 0x00020000 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_ALIGN 0 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_BITS 1 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_SHIFT 17 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEOVERRIDE [16:16] */ -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_MASK 0x00010000 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_ALIGN 0 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_BITS 1 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_SHIFT 16 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPVALUE [15:15] */ -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_MASK 0x00008000 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_ALIGN 0 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_BITS 1 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_SHIFT 15 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPOVERRIDE [14:14] */ -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_MASK 0x00004000 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_ALIGN 0 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_BITS 1 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_SHIFT 14 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETVALUE [13:13] */ -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_MASK 0x00002000 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_ALIGN 0 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_BITS 1 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_SHIFT 13 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETOVERRIDE [12:12] */ -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_MASK 0x00001000 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_ALIGN 0 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_BITS 1 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_SHIFT 12 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETTIMECONTROL [11:10] */ -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_MASK 0x00000c00 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_ALIGN 0 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_BITS 2 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_SHIFT 10 - -/* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETECTIONTIME [09:00] */ -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_MASK 0x000003ff -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_ALIGN 0 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_BITS 10 -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE - ***************************************************************************/ -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TS1NUMOVERRIDE [31:31] */ -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_MASK 0x80000000 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_ALIGN 0 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_BITS 1 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_SHIFT 31 - -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINOVERRIDE [30:30] */ -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_MASK 0x40000000 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_ALIGN 0 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_BITS 1 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_SHIFT 30 - -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLE2IDLEOVERRIDE [29:29] */ -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_MASK 0x20000000 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_ALIGN 0 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_BITS 1 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_SHIFT 29 - -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: UNUSED_0 [28:28] */ -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_MASK 0x10000000 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_ALIGN 0 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_BITS 1 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_SHIFT 28 - -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: N_TS1INPOLLINGACTIVE [27:16] */ -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_MASK 0x0fff0000 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_ALIGN 0 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_BITS 12 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_SHIFT 16 - -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINTIME [15:08] */ -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_MASK 0x0000ff00 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_ALIGN 0 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_BITS 8 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_SHIFT 8 - -/* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLESETTOIDLETIME [07:00] */ -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_MASK 0x000000ff -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_ALIGN 0 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_BITS 8 -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES - ***************************************************************************/ -/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RESERVED_0 [31:10] */ -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_MASK 0xfffffc00 -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_ALIGN 0 -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_BITS 22 -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_SHIFT 10 - -/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: TRANSMIT_STATE_MACHINE_STATE [09:04] */ -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_MASK 0x000003f0 -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_ALIGN 0 -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_BITS 6 -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_SHIFT 4 - -/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RECEIVE_STATE_MACHINE_STATE [03:00] */ -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_MASK 0x0000000f -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_ALIGN 0 -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_BITS 4 -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_SHIFT 0 - - -/**************************************************************************** - * PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES - ***************************************************************************/ -/* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES :: LTSSM_STATE_MACHINE_STATE [31:00] */ -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_MASK 0xffffffff -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_ALIGN 0 -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_BITS 32 -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_SHIFT 0 - - -/**************************************************************************** - * BCM70012_TGT_TOP_INTR - ***************************************************************************/ -/**************************************************************************** - * INTR :: INTR_STATUS - ***************************************************************************/ -/* INTR :: INTR_STATUS :: reserved0 [31:26] */ -#define INTR_INTR_STATUS_reserved0_MASK 0xfc000000 -#define INTR_INTR_STATUS_reserved0_ALIGN 0 -#define INTR_INTR_STATUS_reserved0_BITS 6 -#define INTR_INTR_STATUS_reserved0_SHIFT 26 - -/* INTR :: INTR_STATUS :: PCIE_TGT_CA_ATTN [25:25] */ -#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_ALIGN 0 -#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_BITS 1 -#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: INTR_STATUS :: PCIE_TGT_UR_ATTN [24:24] */ -#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_ALIGN 0 -#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_BITS 1 -#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: INTR_STATUS :: reserved1 [23:14] */ -#define INTR_INTR_STATUS_reserved1_MASK 0x00ffc000 -#define INTR_INTR_STATUS_reserved1_ALIGN 0 -#define INTR_INTR_STATUS_reserved1_BITS 10 -#define INTR_INTR_STATUS_reserved1_SHIFT 14 - -/* INTR :: INTR_STATUS :: L1_UV_RX_DMA_ERR_INTR [13:13] */ -#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK 0x00002000 -#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_BITS 1 -#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_SHIFT 13 - -/* INTR :: INTR_STATUS :: L1_UV_RX_DMA_DONE_INTR [12:12] */ -#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK 0x00001000 -#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_BITS 1 -#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_SHIFT 12 - -/* INTR :: INTR_STATUS :: L1_Y_RX_DMA_ERR_INTR [11:11] */ -#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK 0x00000800 -#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_BITS 1 -#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT 11 - -/* INTR :: INTR_STATUS :: L1_Y_RX_DMA_DONE_INTR [10:10] */ -#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK 0x00000400 -#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_BITS 1 -#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT 10 - -/* INTR :: INTR_STATUS :: L1_TX_DMA_ERR_INTR [09:09] */ -#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000200 -#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_BITS 1 -#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 9 - -/* INTR :: INTR_STATUS :: L1_TX_DMA_DONE_INTR [08:08] */ -#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000100 -#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_BITS 1 -#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 8 - -/* INTR :: INTR_STATUS :: reserved2 [07:06] */ -#define INTR_INTR_STATUS_reserved2_MASK 0x000000c0 -#define INTR_INTR_STATUS_reserved2_ALIGN 0 -#define INTR_INTR_STATUS_reserved2_BITS 2 -#define INTR_INTR_STATUS_reserved2_SHIFT 6 - -/* INTR :: INTR_STATUS :: L0_UV_RX_DMA_ERR_INTR [05:05] */ -#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK 0x00000020 -#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_BITS 1 -#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_SHIFT 5 - -/* INTR :: INTR_STATUS :: L0_UV_RX_DMA_DONE_INTR [04:04] */ -#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK 0x00000010 -#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_BITS 1 -#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_SHIFT 4 - -/* INTR :: INTR_STATUS :: L0_Y_RX_DMA_ERR_INTR [03:03] */ -#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK 0x00000008 -#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_BITS 1 -#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT 3 - -/* INTR :: INTR_STATUS :: L0_Y_RX_DMA_DONE_INTR [02:02] */ -#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK 0x00000004 -#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_BITS 1 -#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT 2 - -/* INTR :: INTR_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */ -#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002 -#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_BITS 1 -#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1 - -/* INTR :: INTR_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */ -#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001 -#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_ALIGN 0 -#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_BITS 1 -#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0 - - -/**************************************************************************** - * INTR :: INTR_SET - ***************************************************************************/ -/* INTR :: INTR_SET :: reserved0 [31:26] */ -#define INTR_INTR_SET_reserved0_MASK 0xfc000000 -#define INTR_INTR_SET_reserved0_ALIGN 0 -#define INTR_INTR_SET_reserved0_BITS 6 -#define INTR_INTR_SET_reserved0_SHIFT 26 - -/* INTR :: INTR_SET :: PCIE_TGT_CA_ATTN [25:25] */ -#define INTR_INTR_SET_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define INTR_INTR_SET_PCIE_TGT_CA_ATTN_ALIGN 0 -#define INTR_INTR_SET_PCIE_TGT_CA_ATTN_BITS 1 -#define INTR_INTR_SET_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: INTR_SET :: PCIE_TGT_UR_ATTN [24:24] */ -#define INTR_INTR_SET_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define INTR_INTR_SET_PCIE_TGT_UR_ATTN_ALIGN 0 -#define INTR_INTR_SET_PCIE_TGT_UR_ATTN_BITS 1 -#define INTR_INTR_SET_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: INTR_SET :: reserved1 [23:14] */ -#define INTR_INTR_SET_reserved1_MASK 0x00ffc000 -#define INTR_INTR_SET_reserved1_ALIGN 0 -#define INTR_INTR_SET_reserved1_BITS 10 -#define INTR_INTR_SET_reserved1_SHIFT 14 - -/* INTR :: INTR_SET :: UV_RX_DMA_L1_ERR_INTR [13:13] */ -#define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_MASK 0x00002000 -#define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_ALIGN 0 -#define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_BITS 1 -#define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_SHIFT 13 - -/* INTR :: INTR_SET :: UV_RX_DMA_L1_DONE_INTR [12:12] */ -#define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_MASK 0x00001000 -#define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_ALIGN 0 -#define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_BITS 1 -#define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_SHIFT 12 - -/* INTR :: INTR_SET :: Y_RX_DMA_L1_ERR_INTR [11:11] */ -#define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_MASK 0x00000800 -#define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_ALIGN 0 -#define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_BITS 1 -#define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_SHIFT 11 - -/* INTR :: INTR_SET :: Y_RX_DMA_L1_DONE_INTR [10:10] */ -#define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_MASK 0x00000400 -#define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_ALIGN 0 -#define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_BITS 1 -#define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_SHIFT 10 - -/* INTR :: INTR_SET :: TX_DMA_L1_ERR_INTR [09:09] */ -#define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_MASK 0x00000200 -#define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_ALIGN 0 -#define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_BITS 1 -#define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_SHIFT 9 - -/* INTR :: INTR_SET :: TX_DMA_L1_DONE_INTR [08:08] */ -#define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_MASK 0x00000100 -#define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_ALIGN 0 -#define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_BITS 1 -#define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_SHIFT 8 - -/* INTR :: INTR_SET :: reserved2 [07:06] */ -#define INTR_INTR_SET_reserved2_MASK 0x000000c0 -#define INTR_INTR_SET_reserved2_ALIGN 0 -#define INTR_INTR_SET_reserved2_BITS 2 -#define INTR_INTR_SET_reserved2_SHIFT 6 - -/* INTR :: INTR_SET :: UV_RX_DMA_L0_ERR_INTR [05:05] */ -#define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_MASK 0x00000020 -#define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_ALIGN 0 -#define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_BITS 1 -#define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_SHIFT 5 - -/* INTR :: INTR_SET :: UV_RX_DMA_L0_DONE_INTR [04:04] */ -#define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_MASK 0x00000010 -#define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_ALIGN 0 -#define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_BITS 1 -#define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_SHIFT 4 - -/* INTR :: INTR_SET :: Y_RX_DMA_L0_ERR_INTR [03:03] */ -#define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_MASK 0x00000008 -#define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_ALIGN 0 -#define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_BITS 1 -#define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_SHIFT 3 - -/* INTR :: INTR_SET :: Y_RX_DMA_L0_DONE_INTR [02:02] */ -#define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_MASK 0x00000004 -#define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_ALIGN 0 -#define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_BITS 1 -#define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_SHIFT 2 - -/* INTR :: INTR_SET :: TX_DMA_L0_ERR_INTR [01:01] */ -#define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_MASK 0x00000002 -#define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_ALIGN 0 -#define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_BITS 1 -#define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_SHIFT 1 - -/* INTR :: INTR_SET :: TX_DMA_L0_DONE_INTR [00:00] */ -#define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_MASK 0x00000001 -#define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_ALIGN 0 -#define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_BITS 1 -#define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_SHIFT 0 - - -/**************************************************************************** - * INTR :: INTR_CLR_REG - ***************************************************************************/ -/* INTR :: INTR_CLR_REG :: reserved0 [31:26] */ -#define INTR_INTR_CLR_REG_reserved0_MASK 0xfc000000 -#define INTR_INTR_CLR_REG_reserved0_ALIGN 0 -#define INTR_INTR_CLR_REG_reserved0_BITS 6 -#define INTR_INTR_CLR_REG_reserved0_SHIFT 26 - -/* INTR :: INTR_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ -#define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_ALIGN 0 -#define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_BITS 1 -#define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: INTR_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ -#define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_ALIGN 0 -#define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_BITS 1 -#define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: INTR_CLR_REG :: reserved1 [23:14] */ -#define INTR_INTR_CLR_REG_reserved1_MASK 0x00ffc000 -#define INTR_INTR_CLR_REG_reserved1_ALIGN 0 -#define INTR_INTR_CLR_REG_reserved1_BITS 10 -#define INTR_INTR_CLR_REG_reserved1_SHIFT 14 - -/* INTR :: INTR_CLR_REG :: L1_UV_RX_DMA_ERR_INTR_CLR [13:13] */ -#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_MASK 0x00002000 -#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_ALIGN 0 -#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_BITS 1 -#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_SHIFT 13 - -/* INTR :: INTR_CLR_REG :: L1_UV_RX_DMA_DONE_INTR_CLR [12:12] */ -#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_MASK 0x00001000 -#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_ALIGN 0 -#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_BITS 1 -#define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_SHIFT 12 - -/* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_CLR [11:11] */ -#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000800 -#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_ALIGN 0 -#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_BITS 1 -#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_SHIFT 11 - -/* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_CLR [10:10] */ -#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000400 -#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_ALIGN 0 -#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_BITS 1 -#define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_SHIFT 10 - -/* INTR :: INTR_CLR_REG :: L1_TX_DMA_ERR_INTR_CLR [09:09] */ -#define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_MASK 0x00000200 -#define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_ALIGN 0 -#define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_BITS 1 -#define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_SHIFT 9 - -/* INTR :: INTR_CLR_REG :: L1_TX_DMA_DONE_INTR_CLR [08:08] */ -#define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_MASK 0x00000100 -#define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_ALIGN 0 -#define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_BITS 1 -#define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_SHIFT 8 - -/* INTR :: INTR_CLR_REG :: reserved2 [07:06] */ -#define INTR_INTR_CLR_REG_reserved2_MASK 0x000000c0 -#define INTR_INTR_CLR_REG_reserved2_ALIGN 0 -#define INTR_INTR_CLR_REG_reserved2_BITS 2 -#define INTR_INTR_CLR_REG_reserved2_SHIFT 6 - -/* INTR :: INTR_CLR_REG :: L0_UV_RX_DMA_ERR_INTR_CLR [05:05] */ -#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_MASK 0x00000020 -#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_ALIGN 0 -#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_BITS 1 -#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_SHIFT 5 - -/* INTR :: INTR_CLR_REG :: L0_UV_RX_DMA_DONE_INTR_CLR [04:04] */ -#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_MASK 0x00000010 -#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_ALIGN 0 -#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_BITS 1 -#define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_SHIFT 4 - -/* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_CLR [03:03] */ -#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000008 -#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_ALIGN 0 -#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_BITS 1 -#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_SHIFT 3 - -/* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_CLR [02:02] */ -#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000004 -#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_ALIGN 0 -#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_BITS 1 -#define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_SHIFT 2 - -/* INTR :: INTR_CLR_REG :: L0_TX_DMA_ERR_INTR_CLR [01:01] */ -#define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_MASK 0x00000002 -#define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_ALIGN 0 -#define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_BITS 1 -#define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_SHIFT 1 - -/* INTR :: INTR_CLR_REG :: L0_TX_DMA_DONE_INTR_CLR [00:00] */ -#define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_MASK 0x00000001 -#define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_ALIGN 0 -#define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_BITS 1 -#define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_SHIFT 0 - - -/**************************************************************************** - * INTR :: INTR_MSK_STS_REG - ***************************************************************************/ -/* INTR :: INTR_MSK_STS_REG :: reserved0 [31:26] */ -#define INTR_INTR_MSK_STS_REG_reserved0_MASK 0xfc000000 -#define INTR_INTR_MSK_STS_REG_reserved0_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_reserved0_BITS 6 -#define INTR_INTR_MSK_STS_REG_reserved0_SHIFT 26 - -/* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_CA_ATTN [25:25] */ -#define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_BITS 1 -#define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_UR_ATTN [24:24] */ -#define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_BITS 1 -#define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: INTR_MSK_STS_REG :: reserved1 [23:14] */ -#define INTR_INTR_MSK_STS_REG_reserved1_MASK 0x00ffc000 -#define INTR_INTR_MSK_STS_REG_reserved1_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_reserved1_BITS 10 -#define INTR_INTR_MSK_STS_REG_reserved1_SHIFT 14 - -/* INTR :: INTR_MSK_STS_REG :: L1_UV_RX_DMA_ERR_INTR_MSK [13:13] */ -#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_MASK 0x00002000 -#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_BITS 1 -#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SHIFT 13 - -/* INTR :: INTR_MSK_STS_REG :: L1_UV_RX_DMA_DONE_INTR_MSK [12:12] */ -#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_MASK 0x00001000 -#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_BITS 1 -#define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SHIFT 12 - -/* INTR :: INTR_MSK_STS_REG :: LIST1_Y_RX_DMA_ERR_INTR_MSK [11:11] */ -#define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000800 -#define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_BITS 1 -#define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_SHIFT 11 - -/* INTR :: INTR_MSK_STS_REG :: L1_Y_RX_DMA_DONE_INTR_MSK [10:10] */ -#define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000400 -#define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_BITS 1 -#define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SHIFT 10 - -/* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_ERR_INTR_MSK [09:09] */ -#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_MASK 0x00000200 -#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_BITS 1 -#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_SHIFT 9 - -/* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_DONE_INTR_MSK [08:08] */ -#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_MASK 0x00000100 -#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_BITS 1 -#define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_SHIFT 8 - -/* INTR :: INTR_MSK_STS_REG :: reserved2 [07:06] */ -#define INTR_INTR_MSK_STS_REG_reserved2_MASK 0x000000c0 -#define INTR_INTR_MSK_STS_REG_reserved2_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_reserved2_BITS 2 -#define INTR_INTR_MSK_STS_REG_reserved2_SHIFT 6 - -/* INTR :: INTR_MSK_STS_REG :: L0_UV_RX_DMA_ERR_INTR_MSK [05:05] */ -#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_MASK 0x00000020 -#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_BITS 1 -#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SHIFT 5 - -/* INTR :: INTR_MSK_STS_REG :: L0_UV_RX_DMA_DONE_INTR_MSK [04:04] */ -#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_MASK 0x00000010 -#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_BITS 1 -#define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SHIFT 4 - -/* INTR :: INTR_MSK_STS_REG :: LIST0_Y_RX_DMA_ERR_INTR_MSK [03:03] */ -#define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000008 -#define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_BITS 1 -#define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_SHIFT 3 - -/* INTR :: INTR_MSK_STS_REG :: L0_Y_RX_DMA_DONE_INTR_MSK [02:02] */ -#define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000004 -#define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_BITS 1 -#define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SHIFT 2 - -/* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_ERR_INTR_MSK [01:01] */ -#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_MASK 0x00000002 -#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_BITS 1 -#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_SHIFT 1 - -/* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_DONE_INTR_MSK [00:00] */ -#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_MASK 0x00000001 -#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_ALIGN 0 -#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_BITS 1 -#define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_SHIFT 0 - - -/**************************************************************************** - * INTR :: INTR_MSK_SET_REG - ***************************************************************************/ -/* INTR :: INTR_MSK_SET_REG :: reserved0 [31:26] */ -#define INTR_INTR_MSK_SET_REG_reserved0_MASK 0xfc000000 -#define INTR_INTR_MSK_SET_REG_reserved0_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_reserved0_BITS 6 -#define INTR_INTR_MSK_SET_REG_reserved0_SHIFT 26 - -/* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_CA_ATTN [25:25] */ -#define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_BITS 1 -#define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_UR_ATTN [24:24] */ -#define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_BITS 1 -#define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: INTR_MSK_SET_REG :: reserved1 [23:14] */ -#define INTR_INTR_MSK_SET_REG_reserved1_MASK 0x00ffc000 -#define INTR_INTR_MSK_SET_REG_reserved1_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_reserved1_BITS 10 -#define INTR_INTR_MSK_SET_REG_reserved1_SHIFT 14 - -/* INTR :: INTR_MSK_SET_REG :: L1_UV_RX_DMA_ERR_INTR_MSK_SET [13:13] */ -#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00002000 -#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_BITS 1 -#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_SHIFT 13 - -/* INTR :: INTR_MSK_SET_REG :: L1_UV_RX_DMA_DONE_INTR_MSK_SET [12:12] */ -#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00001000 -#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_BITS 1 -#define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_SHIFT 12 - -/* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_SET [11:11] */ -#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000800 -#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_BITS 1 -#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 11 - -/* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_SET [10:10] */ -#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000400 -#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_BITS 1 -#define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 10 - -/* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_ERR_INTR_MSK_SET [09:09] */ -#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000200 -#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_BITS 1 -#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_SHIFT 9 - -/* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_DONE_INTR_MSK_SET [08:08] */ -#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000100 -#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_BITS 1 -#define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_SHIFT 8 - -/* INTR :: INTR_MSK_SET_REG :: reserved2 [07:06] */ -#define INTR_INTR_MSK_SET_REG_reserved2_MASK 0x000000c0 -#define INTR_INTR_MSK_SET_REG_reserved2_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_reserved2_BITS 2 -#define INTR_INTR_MSK_SET_REG_reserved2_SHIFT 6 - -/* INTR :: INTR_MSK_SET_REG :: L0_UV_RX_DMA_ERR_INTR_MSK_SET [05:05] */ -#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000020 -#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_BITS 1 -#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_SHIFT 5 - -/* INTR :: INTR_MSK_SET_REG :: L0_UV_RX_DMA_DONE_INTR_MSK_SET [04:04] */ -#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000010 -#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_BITS 1 -#define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_SHIFT 4 - -/* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_SET [03:03] */ -#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000008 -#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_BITS 1 -#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 3 - -/* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_SET [02:02] */ -#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000004 -#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_BITS 1 -#define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 2 - -/* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_ERR_INTR_MSK_SET [01:01] */ -#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000002 -#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_BITS 1 -#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_SHIFT 1 - -/* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_DONE_INTR_MSK_SET [00:00] */ -#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000001 -#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_ALIGN 0 -#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_BITS 1 -#define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_SHIFT 0 - - -/**************************************************************************** - * INTR :: INTR_MSK_CLR_REG - ***************************************************************************/ -/* INTR :: INTR_MSK_CLR_REG :: reserved0 [31:26] */ -#define INTR_INTR_MSK_CLR_REG_reserved0_MASK 0xfc000000 -#define INTR_INTR_MSK_CLR_REG_reserved0_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_reserved0_BITS 6 -#define INTR_INTR_MSK_CLR_REG_reserved0_SHIFT 26 - -/* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ -#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 -#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_BITS 1 -#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 - -/* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ -#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 -#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_BITS 1 -#define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 - -/* INTR :: INTR_MSK_CLR_REG :: reserved1 [23:14] */ -#define INTR_INTR_MSK_CLR_REG_reserved1_MASK 0x00ffc000 -#define INTR_INTR_MSK_CLR_REG_reserved1_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_reserved1_BITS 10 -#define INTR_INTR_MSK_CLR_REG_reserved1_SHIFT 14 - -/* INTR :: INTR_MSK_CLR_REG :: L1_UV_RX_DMA_ERR_INTR_MSK_CLR [13:13] */ -#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00002000 -#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 -#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 13 - -/* INTR :: INTR_MSK_CLR_REG :: L1_UV_RX_DMA_DONE_INTR_MSK_CLR [12:12] */ -#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00001000 -#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 -#define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 12 - -/* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_CLR [11:11] */ -#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000800 -#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 -#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 11 - -/* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_CLR [10:10] */ -#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000400 -#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 -#define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 10 - -/* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_ERR_INTR_MSK_CLR [09:09] */ -#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000200 -#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_BITS 1 -#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 9 - -/* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_DONE_INTR_MSK_CLR [08:08] */ -#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000100 -#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_BITS 1 -#define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 8 - -/* INTR :: INTR_MSK_CLR_REG :: reserved2 [07:06] */ -#define INTR_INTR_MSK_CLR_REG_reserved2_MASK 0x000000c0 -#define INTR_INTR_MSK_CLR_REG_reserved2_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_reserved2_BITS 2 -#define INTR_INTR_MSK_CLR_REG_reserved2_SHIFT 6 - -/* INTR :: INTR_MSK_CLR_REG :: L0_UV_RX_DMA_ERR_INTR_MSK_CLR [05:05] */ -#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000020 -#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 -#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 5 - -/* INTR :: INTR_MSK_CLR_REG :: L0_UV_RX_DMA_DONE_INTR_MSK_CLR [04:04] */ -#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000010 -#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 -#define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 4 - -/* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_CLR [03:03] */ -#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000008 -#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 -#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 3 - -/* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_CLR [02:02] */ -#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000004 -#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 -#define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 2 - -/* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_ERR_INTR_MSK_CLR [01:01] */ -#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000002 -#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_BITS 1 -#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 1 - -/* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_DONE_INTR_MSK_CLR [00:00] */ -#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000001 -#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 -#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_BITS 1 -#define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 0 - - -/**************************************************************************** - * INTR :: EOI_CTRL - ***************************************************************************/ -/* INTR :: EOI_CTRL :: reserved0 [31:01] */ -#define INTR_EOI_CTRL_reserved0_MASK 0xfffffffe -#define INTR_EOI_CTRL_reserved0_ALIGN 0 -#define INTR_EOI_CTRL_reserved0_BITS 31 -#define INTR_EOI_CTRL_reserved0_SHIFT 1 - -/* INTR :: EOI_CTRL :: EOI [00:00] */ -#define INTR_EOI_CTRL_EOI_MASK 0x00000001 -#define INTR_EOI_CTRL_EOI_ALIGN 0 -#define INTR_EOI_CTRL_EOI_BITS 1 -#define INTR_EOI_CTRL_EOI_SHIFT 0 - - -/**************************************************************************** - * BCM70012_TGT_TOP_MDIO - ***************************************************************************/ -/**************************************************************************** - * MDIO :: CTRL0 - ***************************************************************************/ -/* MDIO :: CTRL0 :: reserved0 [31:22] */ -#define MDIO_CTRL0_reserved0_MASK 0xffc00000 -#define MDIO_CTRL0_reserved0_ALIGN 0 -#define MDIO_CTRL0_reserved0_BITS 10 -#define MDIO_CTRL0_reserved0_SHIFT 22 - -/* MDIO :: CTRL0 :: WRITE_READ_COMMAND [21:21] */ -#define MDIO_CTRL0_WRITE_READ_COMMAND_MASK 0x00200000 -#define MDIO_CTRL0_WRITE_READ_COMMAND_ALIGN 0 -#define MDIO_CTRL0_WRITE_READ_COMMAND_BITS 1 -#define MDIO_CTRL0_WRITE_READ_COMMAND_SHIFT 21 - -/* MDIO :: CTRL0 :: PHYAD [20:16] */ -#define MDIO_CTRL0_PHYAD_MASK 0x001f0000 -#define MDIO_CTRL0_PHYAD_ALIGN 0 -#define MDIO_CTRL0_PHYAD_BITS 5 -#define MDIO_CTRL0_PHYAD_SHIFT 16 - -/* MDIO :: CTRL0 :: reserved1 [15:05] */ -#define MDIO_CTRL0_reserved1_MASK 0x0000ffe0 -#define MDIO_CTRL0_reserved1_ALIGN 0 -#define MDIO_CTRL0_reserved1_BITS 11 -#define MDIO_CTRL0_reserved1_SHIFT 5 - -/* MDIO :: CTRL0 :: REGAD [04:00] */ -#define MDIO_CTRL0_REGAD_MASK 0x0000001f -#define MDIO_CTRL0_REGAD_ALIGN 0 -#define MDIO_CTRL0_REGAD_BITS 5 -#define MDIO_CTRL0_REGAD_SHIFT 0 - - -/**************************************************************************** - * MDIO :: CTRL1 - ***************************************************************************/ -/* MDIO :: CTRL1 :: WR_STATUS [31:31] */ -#define MDIO_CTRL1_WR_STATUS_MASK 0x80000000 -#define MDIO_CTRL1_WR_STATUS_ALIGN 0 -#define MDIO_CTRL1_WR_STATUS_BITS 1 -#define MDIO_CTRL1_WR_STATUS_SHIFT 31 - -/* MDIO :: CTRL1 :: reserved0 [30:16] */ -#define MDIO_CTRL1_reserved0_MASK 0x7fff0000 -#define MDIO_CTRL1_reserved0_ALIGN 0 -#define MDIO_CTRL1_reserved0_BITS 15 -#define MDIO_CTRL1_reserved0_SHIFT 16 - -/* MDIO :: CTRL1 :: Write_Data [15:00] */ -#define MDIO_CTRL1_Write_Data_MASK 0x0000ffff -#define MDIO_CTRL1_Write_Data_ALIGN 0 -#define MDIO_CTRL1_Write_Data_BITS 16 -#define MDIO_CTRL1_Write_Data_SHIFT 0 - - -/**************************************************************************** - * MDIO :: CTRL2 - ***************************************************************************/ -/* MDIO :: CTRL2 :: RD_STATUS [31:31] */ -#define MDIO_CTRL2_RD_STATUS_MASK 0x80000000 -#define MDIO_CTRL2_RD_STATUS_ALIGN 0 -#define MDIO_CTRL2_RD_STATUS_BITS 1 -#define MDIO_CTRL2_RD_STATUS_SHIFT 31 - -/* MDIO :: CTRL2 :: reserved0 [30:16] */ -#define MDIO_CTRL2_reserved0_MASK 0x7fff0000 -#define MDIO_CTRL2_reserved0_ALIGN 0 -#define MDIO_CTRL2_reserved0_BITS 15 -#define MDIO_CTRL2_reserved0_SHIFT 16 - -/* MDIO :: CTRL2 :: Read_Data [15:00] */ -#define MDIO_CTRL2_Read_Data_MASK 0x0000ffff -#define MDIO_CTRL2_Read_Data_ALIGN 0 -#define MDIO_CTRL2_Read_Data_BITS 16 -#define MDIO_CTRL2_Read_Data_SHIFT 0 - - -/**************************************************************************** - * BCM70012_TGT_TOP_TGT_RGR_BRIDGE - ***************************************************************************/ -/**************************************************************************** - * TGT_RGR_BRIDGE :: REVISION - ***************************************************************************/ -/* TGT_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define TGT_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define TGT_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 -#define TGT_RGR_BRIDGE_REVISION_reserved0_BITS 16 -#define TGT_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* TGT_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define TGT_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define TGT_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 -#define TGT_RGR_BRIDGE_REVISION_MAJOR_BITS 8 -#define TGT_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* TGT_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define TGT_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define TGT_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 -#define TGT_RGR_BRIDGE_REVISION_MINOR_BITS 8 -#define TGT_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 - - -/**************************************************************************** - * TGT_RGR_BRIDGE :: CTRL - ***************************************************************************/ -/* TGT_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ -#define TGT_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc -#define TGT_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 -#define TGT_RGR_BRIDGE_CTRL_reserved0_BITS 30 -#define TGT_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 - -/* TGT_RGR_BRIDGE :: CTRL :: RBUS_ERROR_INTR [01:01] */ -#define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_MASK 0x00000002 -#define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_ALIGN 0 -#define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_BITS 1 -#define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_SHIFT 1 - -/* TGT_RGR_BRIDGE :: CTRL :: GISB_ERROR_INTR [00:00] */ -#define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_MASK 0x00000001 -#define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_ALIGN 0 -#define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_BITS 1 -#define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_SHIFT 0 - - -/**************************************************************************** - * TGT_RGR_BRIDGE :: RBUS_TIMER - ***************************************************************************/ -/* TGT_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ -#define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 -#define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 -#define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 -#define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 - -/* TGT_RGR_BRIDGE :: RBUS_TIMER :: RBUS_TO_RBUS_TRANS_TIMER_CNT [15:00] */ -#define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_MASK 0x0000ffff -#define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_ALIGN 0 -#define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_BITS 16 -#define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_SHIFT 0 - - -/**************************************************************************** - * TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 - ***************************************************************************/ -/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 - -/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 - - -/**************************************************************************** - * TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 - ***************************************************************************/ -/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 - -/* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 - - -/**************************************************************************** - * BCM70012_I2C_TOP_I2C - ***************************************************************************/ -/**************************************************************************** - * I2C :: CHIP_ADDRESS - ***************************************************************************/ -/* I2C :: CHIP_ADDRESS :: reserved0 [31:08] */ -#define I2C_CHIP_ADDRESS_reserved0_MASK 0xffffff00 -#define I2C_CHIP_ADDRESS_reserved0_ALIGN 0 -#define I2C_CHIP_ADDRESS_reserved0_BITS 24 -#define I2C_CHIP_ADDRESS_reserved0_SHIFT 8 - -/* I2C :: CHIP_ADDRESS :: CHIP_ADDRESS [07:01] */ -#define I2C_CHIP_ADDRESS_CHIP_ADDRESS_MASK 0x000000fe -#define I2C_CHIP_ADDRESS_CHIP_ADDRESS_ALIGN 0 -#define I2C_CHIP_ADDRESS_CHIP_ADDRESS_BITS 7 -#define I2C_CHIP_ADDRESS_CHIP_ADDRESS_SHIFT 1 - -/* I2C :: CHIP_ADDRESS :: RESERVED [00:00] */ -#define I2C_CHIP_ADDRESS_RESERVED_MASK 0x00000001 -#define I2C_CHIP_ADDRESS_RESERVED_ALIGN 0 -#define I2C_CHIP_ADDRESS_RESERVED_BITS 1 -#define I2C_CHIP_ADDRESS_RESERVED_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_IN0 - ***************************************************************************/ -/* I2C :: DATA_IN0 :: reserved0 [31:08] */ -#define I2C_DATA_IN0_reserved0_MASK 0xffffff00 -#define I2C_DATA_IN0_reserved0_ALIGN 0 -#define I2C_DATA_IN0_reserved0_BITS 24 -#define I2C_DATA_IN0_reserved0_SHIFT 8 - -/* I2C :: DATA_IN0 :: DATA_IN0 [07:00] */ -#define I2C_DATA_IN0_DATA_IN0_MASK 0x000000ff -#define I2C_DATA_IN0_DATA_IN0_ALIGN 0 -#define I2C_DATA_IN0_DATA_IN0_BITS 8 -#define I2C_DATA_IN0_DATA_IN0_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_IN1 - ***************************************************************************/ -/* I2C :: DATA_IN1 :: reserved0 [31:08] */ -#define I2C_DATA_IN1_reserved0_MASK 0xffffff00 -#define I2C_DATA_IN1_reserved0_ALIGN 0 -#define I2C_DATA_IN1_reserved0_BITS 24 -#define I2C_DATA_IN1_reserved0_SHIFT 8 - -/* I2C :: DATA_IN1 :: DATA_IN1 [07:00] */ -#define I2C_DATA_IN1_DATA_IN1_MASK 0x000000ff -#define I2C_DATA_IN1_DATA_IN1_ALIGN 0 -#define I2C_DATA_IN1_DATA_IN1_BITS 8 -#define I2C_DATA_IN1_DATA_IN1_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_IN2 - ***************************************************************************/ -/* I2C :: DATA_IN2 :: reserved0 [31:08] */ -#define I2C_DATA_IN2_reserved0_MASK 0xffffff00 -#define I2C_DATA_IN2_reserved0_ALIGN 0 -#define I2C_DATA_IN2_reserved0_BITS 24 -#define I2C_DATA_IN2_reserved0_SHIFT 8 - -/* I2C :: DATA_IN2 :: DATA_IN2 [07:00] */ -#define I2C_DATA_IN2_DATA_IN2_MASK 0x000000ff -#define I2C_DATA_IN2_DATA_IN2_ALIGN 0 -#define I2C_DATA_IN2_DATA_IN2_BITS 8 -#define I2C_DATA_IN2_DATA_IN2_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_IN3 - ***************************************************************************/ -/* I2C :: DATA_IN3 :: reserved0 [31:08] */ -#define I2C_DATA_IN3_reserved0_MASK 0xffffff00 -#define I2C_DATA_IN3_reserved0_ALIGN 0 -#define I2C_DATA_IN3_reserved0_BITS 24 -#define I2C_DATA_IN3_reserved0_SHIFT 8 - -/* I2C :: DATA_IN3 :: DATA_IN3 [07:00] */ -#define I2C_DATA_IN3_DATA_IN3_MASK 0x000000ff -#define I2C_DATA_IN3_DATA_IN3_ALIGN 0 -#define I2C_DATA_IN3_DATA_IN3_BITS 8 -#define I2C_DATA_IN3_DATA_IN3_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_IN4 - ***************************************************************************/ -/* I2C :: DATA_IN4 :: reserved0 [31:08] */ -#define I2C_DATA_IN4_reserved0_MASK 0xffffff00 -#define I2C_DATA_IN4_reserved0_ALIGN 0 -#define I2C_DATA_IN4_reserved0_BITS 24 -#define I2C_DATA_IN4_reserved0_SHIFT 8 - -/* I2C :: DATA_IN4 :: DATA_IN4 [07:00] */ -#define I2C_DATA_IN4_DATA_IN4_MASK 0x000000ff -#define I2C_DATA_IN4_DATA_IN4_ALIGN 0 -#define I2C_DATA_IN4_DATA_IN4_BITS 8 -#define I2C_DATA_IN4_DATA_IN4_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_IN5 - ***************************************************************************/ -/* I2C :: DATA_IN5 :: reserved0 [31:08] */ -#define I2C_DATA_IN5_reserved0_MASK 0xffffff00 -#define I2C_DATA_IN5_reserved0_ALIGN 0 -#define I2C_DATA_IN5_reserved0_BITS 24 -#define I2C_DATA_IN5_reserved0_SHIFT 8 - -/* I2C :: DATA_IN5 :: DATA_IN5 [07:00] */ -#define I2C_DATA_IN5_DATA_IN5_MASK 0x000000ff -#define I2C_DATA_IN5_DATA_IN5_ALIGN 0 -#define I2C_DATA_IN5_DATA_IN5_BITS 8 -#define I2C_DATA_IN5_DATA_IN5_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_IN6 - ***************************************************************************/ -/* I2C :: DATA_IN6 :: reserved0 [31:08] */ -#define I2C_DATA_IN6_reserved0_MASK 0xffffff00 -#define I2C_DATA_IN6_reserved0_ALIGN 0 -#define I2C_DATA_IN6_reserved0_BITS 24 -#define I2C_DATA_IN6_reserved0_SHIFT 8 - -/* I2C :: DATA_IN6 :: DATA_IN6 [07:00] */ -#define I2C_DATA_IN6_DATA_IN6_MASK 0x000000ff -#define I2C_DATA_IN6_DATA_IN6_ALIGN 0 -#define I2C_DATA_IN6_DATA_IN6_BITS 8 -#define I2C_DATA_IN6_DATA_IN6_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_IN7 - ***************************************************************************/ -/* I2C :: DATA_IN7 :: reserved0 [31:08] */ -#define I2C_DATA_IN7_reserved0_MASK 0xffffff00 -#define I2C_DATA_IN7_reserved0_ALIGN 0 -#define I2C_DATA_IN7_reserved0_BITS 24 -#define I2C_DATA_IN7_reserved0_SHIFT 8 - -/* I2C :: DATA_IN7 :: DATA_IN7 [07:00] */ -#define I2C_DATA_IN7_DATA_IN7_MASK 0x000000ff -#define I2C_DATA_IN7_DATA_IN7_ALIGN 0 -#define I2C_DATA_IN7_DATA_IN7_BITS 8 -#define I2C_DATA_IN7_DATA_IN7_SHIFT 0 - - -/**************************************************************************** - * I2C :: CNT_REG - ***************************************************************************/ -/* I2C :: CNT_REG :: reserved0 [31:08] */ -#define I2C_CNT_REG_reserved0_MASK 0xffffff00 -#define I2C_CNT_REG_reserved0_ALIGN 0 -#define I2C_CNT_REG_reserved0_BITS 24 -#define I2C_CNT_REG_reserved0_SHIFT 8 - -/* I2C :: CNT_REG :: CNT_REG2 [07:04] */ -#define I2C_CNT_REG_CNT_REG2_MASK 0x000000f0 -#define I2C_CNT_REG_CNT_REG2_ALIGN 0 -#define I2C_CNT_REG_CNT_REG2_BITS 4 -#define I2C_CNT_REG_CNT_REG2_SHIFT 4 - -/* I2C :: CNT_REG :: CNT_REG1 [03:00] */ -#define I2C_CNT_REG_CNT_REG1_MASK 0x0000000f -#define I2C_CNT_REG_CNT_REG1_ALIGN 0 -#define I2C_CNT_REG_CNT_REG1_BITS 4 -#define I2C_CNT_REG_CNT_REG1_SHIFT 0 - - -/**************************************************************************** - * I2C :: CTL_REG - ***************************************************************************/ -/* I2C :: CTL_REG :: reserved0 [31:08] */ -#define I2C_CTL_REG_reserved0_MASK 0xffffff00 -#define I2C_CTL_REG_reserved0_ALIGN 0 -#define I2C_CTL_REG_reserved0_BITS 24 -#define I2C_CTL_REG_reserved0_SHIFT 8 - -/* I2C :: CTL_REG :: DIV_CLK [07:07] */ -#define I2C_CTL_REG_DIV_CLK_MASK 0x00000080 -#define I2C_CTL_REG_DIV_CLK_ALIGN 0 -#define I2C_CTL_REG_DIV_CLK_BITS 1 -#define I2C_CTL_REG_DIV_CLK_SHIFT 7 - -/* I2C :: CTL_REG :: INT_EN [06:06] */ -#define I2C_CTL_REG_INT_EN_MASK 0x00000040 -#define I2C_CTL_REG_INT_EN_ALIGN 0 -#define I2C_CTL_REG_INT_EN_BITS 1 -#define I2C_CTL_REG_INT_EN_SHIFT 6 - -/* I2C :: CTL_REG :: SCL_SEL [05:04] */ -#define I2C_CTL_REG_SCL_SEL_MASK 0x00000030 -#define I2C_CTL_REG_SCL_SEL_ALIGN 0 -#define I2C_CTL_REG_SCL_SEL_BITS 2 -#define I2C_CTL_REG_SCL_SEL_SHIFT 4 - -/* I2C :: CTL_REG :: DELAY_DIS [03:03] */ -#define I2C_CTL_REG_DELAY_DIS_MASK 0x00000008 -#define I2C_CTL_REG_DELAY_DIS_ALIGN 0 -#define I2C_CTL_REG_DELAY_DIS_BITS 1 -#define I2C_CTL_REG_DELAY_DIS_SHIFT 3 - -/* I2C :: CTL_REG :: DEGLITCH_DIS [02:02] */ -#define I2C_CTL_REG_DEGLITCH_DIS_MASK 0x00000004 -#define I2C_CTL_REG_DEGLITCH_DIS_ALIGN 0 -#define I2C_CTL_REG_DEGLITCH_DIS_BITS 1 -#define I2C_CTL_REG_DEGLITCH_DIS_SHIFT 2 - -/* I2C :: CTL_REG :: DTF [01:00] */ -#define I2C_CTL_REG_DTF_MASK 0x00000003 -#define I2C_CTL_REG_DTF_ALIGN 0 -#define I2C_CTL_REG_DTF_BITS 2 -#define I2C_CTL_REG_DTF_SHIFT 0 - - -/**************************************************************************** - * I2C :: IIC_ENABLE - ***************************************************************************/ -/* I2C :: IIC_ENABLE :: reserved0 [31:07] */ -#define I2C_IIC_ENABLE_reserved0_MASK 0xffffff80 -#define I2C_IIC_ENABLE_reserved0_ALIGN 0 -#define I2C_IIC_ENABLE_reserved0_BITS 25 -#define I2C_IIC_ENABLE_reserved0_SHIFT 7 - -/* I2C :: IIC_ENABLE :: RESTART [06:06] */ -#define I2C_IIC_ENABLE_RESTART_MASK 0x00000040 -#define I2C_IIC_ENABLE_RESTART_ALIGN 0 -#define I2C_IIC_ENABLE_RESTART_BITS 1 -#define I2C_IIC_ENABLE_RESTART_SHIFT 6 - -/* I2C :: IIC_ENABLE :: NO_START [05:05] */ -#define I2C_IIC_ENABLE_NO_START_MASK 0x00000020 -#define I2C_IIC_ENABLE_NO_START_ALIGN 0 -#define I2C_IIC_ENABLE_NO_START_BITS 1 -#define I2C_IIC_ENABLE_NO_START_SHIFT 5 - -/* I2C :: IIC_ENABLE :: NO_STOP [04:04] */ -#define I2C_IIC_ENABLE_NO_STOP_MASK 0x00000010 -#define I2C_IIC_ENABLE_NO_STOP_ALIGN 0 -#define I2C_IIC_ENABLE_NO_STOP_BITS 1 -#define I2C_IIC_ENABLE_NO_STOP_SHIFT 4 - -/* I2C :: IIC_ENABLE :: reserved1 [03:03] */ -#define I2C_IIC_ENABLE_reserved1_MASK 0x00000008 -#define I2C_IIC_ENABLE_reserved1_ALIGN 0 -#define I2C_IIC_ENABLE_reserved1_BITS 1 -#define I2C_IIC_ENABLE_reserved1_SHIFT 3 - -/* I2C :: IIC_ENABLE :: NO_ACK [02:02] */ -#define I2C_IIC_ENABLE_NO_ACK_MASK 0x00000004 -#define I2C_IIC_ENABLE_NO_ACK_ALIGN 0 -#define I2C_IIC_ENABLE_NO_ACK_BITS 1 -#define I2C_IIC_ENABLE_NO_ACK_SHIFT 2 - -/* I2C :: IIC_ENABLE :: INTRP [01:01] */ -#define I2C_IIC_ENABLE_INTRP_MASK 0x00000002 -#define I2C_IIC_ENABLE_INTRP_ALIGN 0 -#define I2C_IIC_ENABLE_INTRP_BITS 1 -#define I2C_IIC_ENABLE_INTRP_SHIFT 1 - -/* I2C :: IIC_ENABLE :: ENABLE [00:00] */ -#define I2C_IIC_ENABLE_ENABLE_MASK 0x00000001 -#define I2C_IIC_ENABLE_ENABLE_ALIGN 0 -#define I2C_IIC_ENABLE_ENABLE_BITS 1 -#define I2C_IIC_ENABLE_ENABLE_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_OUT0 - ***************************************************************************/ -/* I2C :: DATA_OUT0 :: reserved0 [31:08] */ -#define I2C_DATA_OUT0_reserved0_MASK 0xffffff00 -#define I2C_DATA_OUT0_reserved0_ALIGN 0 -#define I2C_DATA_OUT0_reserved0_BITS 24 -#define I2C_DATA_OUT0_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT0 :: DATA_OUT0 [07:00] */ -#define I2C_DATA_OUT0_DATA_OUT0_MASK 0x000000ff -#define I2C_DATA_OUT0_DATA_OUT0_ALIGN 0 -#define I2C_DATA_OUT0_DATA_OUT0_BITS 8 -#define I2C_DATA_OUT0_DATA_OUT0_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_OUT1 - ***************************************************************************/ -/* I2C :: DATA_OUT1 :: reserved0 [31:08] */ -#define I2C_DATA_OUT1_reserved0_MASK 0xffffff00 -#define I2C_DATA_OUT1_reserved0_ALIGN 0 -#define I2C_DATA_OUT1_reserved0_BITS 24 -#define I2C_DATA_OUT1_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT1 :: DATA_OUT1 [07:00] */ -#define I2C_DATA_OUT1_DATA_OUT1_MASK 0x000000ff -#define I2C_DATA_OUT1_DATA_OUT1_ALIGN 0 -#define I2C_DATA_OUT1_DATA_OUT1_BITS 8 -#define I2C_DATA_OUT1_DATA_OUT1_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_OUT2 - ***************************************************************************/ -/* I2C :: DATA_OUT2 :: reserved0 [31:08] */ -#define I2C_DATA_OUT2_reserved0_MASK 0xffffff00 -#define I2C_DATA_OUT2_reserved0_ALIGN 0 -#define I2C_DATA_OUT2_reserved0_BITS 24 -#define I2C_DATA_OUT2_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT2 :: DATA_OUT2 [07:00] */ -#define I2C_DATA_OUT2_DATA_OUT2_MASK 0x000000ff -#define I2C_DATA_OUT2_DATA_OUT2_ALIGN 0 -#define I2C_DATA_OUT2_DATA_OUT2_BITS 8 -#define I2C_DATA_OUT2_DATA_OUT2_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_OUT3 - ***************************************************************************/ -/* I2C :: DATA_OUT3 :: reserved0 [31:08] */ -#define I2C_DATA_OUT3_reserved0_MASK 0xffffff00 -#define I2C_DATA_OUT3_reserved0_ALIGN 0 -#define I2C_DATA_OUT3_reserved0_BITS 24 -#define I2C_DATA_OUT3_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT3 :: DATA_OUT3 [07:00] */ -#define I2C_DATA_OUT3_DATA_OUT3_MASK 0x000000ff -#define I2C_DATA_OUT3_DATA_OUT3_ALIGN 0 -#define I2C_DATA_OUT3_DATA_OUT3_BITS 8 -#define I2C_DATA_OUT3_DATA_OUT3_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_OUT4 - ***************************************************************************/ -/* I2C :: DATA_OUT4 :: reserved0 [31:08] */ -#define I2C_DATA_OUT4_reserved0_MASK 0xffffff00 -#define I2C_DATA_OUT4_reserved0_ALIGN 0 -#define I2C_DATA_OUT4_reserved0_BITS 24 -#define I2C_DATA_OUT4_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT4 :: DATA_OUT4 [07:00] */ -#define I2C_DATA_OUT4_DATA_OUT4_MASK 0x000000ff -#define I2C_DATA_OUT4_DATA_OUT4_ALIGN 0 -#define I2C_DATA_OUT4_DATA_OUT4_BITS 8 -#define I2C_DATA_OUT4_DATA_OUT4_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_OUT5 - ***************************************************************************/ -/* I2C :: DATA_OUT5 :: reserved0 [31:08] */ -#define I2C_DATA_OUT5_reserved0_MASK 0xffffff00 -#define I2C_DATA_OUT5_reserved0_ALIGN 0 -#define I2C_DATA_OUT5_reserved0_BITS 24 -#define I2C_DATA_OUT5_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT5 :: DATA_OUT5 [07:00] */ -#define I2C_DATA_OUT5_DATA_OUT5_MASK 0x000000ff -#define I2C_DATA_OUT5_DATA_OUT5_ALIGN 0 -#define I2C_DATA_OUT5_DATA_OUT5_BITS 8 -#define I2C_DATA_OUT5_DATA_OUT5_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_OUT6 - ***************************************************************************/ -/* I2C :: DATA_OUT6 :: reserved0 [31:08] */ -#define I2C_DATA_OUT6_reserved0_MASK 0xffffff00 -#define I2C_DATA_OUT6_reserved0_ALIGN 0 -#define I2C_DATA_OUT6_reserved0_BITS 24 -#define I2C_DATA_OUT6_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT6 :: DATA_OUT6 [07:00] */ -#define I2C_DATA_OUT6_DATA_OUT6_MASK 0x000000ff -#define I2C_DATA_OUT6_DATA_OUT6_ALIGN 0 -#define I2C_DATA_OUT6_DATA_OUT6_BITS 8 -#define I2C_DATA_OUT6_DATA_OUT6_SHIFT 0 - - -/**************************************************************************** - * I2C :: DATA_OUT7 - ***************************************************************************/ -/* I2C :: DATA_OUT7 :: reserved0 [31:08] */ -#define I2C_DATA_OUT7_reserved0_MASK 0xffffff00 -#define I2C_DATA_OUT7_reserved0_ALIGN 0 -#define I2C_DATA_OUT7_reserved0_BITS 24 -#define I2C_DATA_OUT7_reserved0_SHIFT 8 - -/* I2C :: DATA_OUT7 :: DATA_OUT7 [07:00] */ -#define I2C_DATA_OUT7_DATA_OUT7_MASK 0x000000ff -#define I2C_DATA_OUT7_DATA_OUT7_ALIGN 0 -#define I2C_DATA_OUT7_DATA_OUT7_BITS 8 -#define I2C_DATA_OUT7_DATA_OUT7_SHIFT 0 - - -/**************************************************************************** - * I2C :: CTLHI_REG - ***************************************************************************/ -/* I2C :: CTLHI_REG :: reserved0 [31:02] */ -#define I2C_CTLHI_REG_reserved0_MASK 0xfffffffc -#define I2C_CTLHI_REG_reserved0_ALIGN 0 -#define I2C_CTLHI_REG_reserved0_BITS 30 -#define I2C_CTLHI_REG_reserved0_SHIFT 2 - -/* I2C :: CTLHI_REG :: IGNORE_ACK [01:01] */ -#define I2C_CTLHI_REG_IGNORE_ACK_MASK 0x00000002 -#define I2C_CTLHI_REG_IGNORE_ACK_ALIGN 0 -#define I2C_CTLHI_REG_IGNORE_ACK_BITS 1 -#define I2C_CTLHI_REG_IGNORE_ACK_SHIFT 1 - -/* I2C :: CTLHI_REG :: WAIT_DIS [00:00] */ -#define I2C_CTLHI_REG_WAIT_DIS_MASK 0x00000001 -#define I2C_CTLHI_REG_WAIT_DIS_ALIGN 0 -#define I2C_CTLHI_REG_WAIT_DIS_BITS 1 -#define I2C_CTLHI_REG_WAIT_DIS_SHIFT 0 - - -/**************************************************************************** - * I2C :: SCL_PARAM - ***************************************************************************/ -/* I2C :: SCL_PARAM :: reserved0 [31:00] */ -#define I2C_SCL_PARAM_reserved0_MASK 0xffffffff -#define I2C_SCL_PARAM_reserved0_ALIGN 0 -#define I2C_SCL_PARAM_reserved0_BITS 32 -#define I2C_SCL_PARAM_reserved0_SHIFT 0 - - -/**************************************************************************** - * BCM70012_I2C_TOP_I2C_GR_BRIDGE - ***************************************************************************/ -/**************************************************************************** - * I2C_GR_BRIDGE :: REVISION - ***************************************************************************/ -/* I2C_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define I2C_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define I2C_GR_BRIDGE_REVISION_reserved0_ALIGN 0 -#define I2C_GR_BRIDGE_REVISION_reserved0_BITS 16 -#define I2C_GR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* I2C_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define I2C_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define I2C_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 -#define I2C_GR_BRIDGE_REVISION_MAJOR_BITS 8 -#define I2C_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* I2C_GR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define I2C_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define I2C_GR_BRIDGE_REVISION_MINOR_ALIGN 0 -#define I2C_GR_BRIDGE_REVISION_MINOR_BITS 8 -#define I2C_GR_BRIDGE_REVISION_MINOR_SHIFT 0 - - -/**************************************************************************** - * I2C_GR_BRIDGE :: CTRL - ***************************************************************************/ -/* I2C_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ -#define I2C_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe -#define I2C_GR_BRIDGE_CTRL_reserved0_ALIGN 0 -#define I2C_GR_BRIDGE_CTRL_reserved0_BITS 31 -#define I2C_GR_BRIDGE_CTRL_reserved0_SHIFT 1 - -/* I2C_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ -#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 -#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 -#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 -#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 -#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 - - -/**************************************************************************** - * I2C_GR_BRIDGE :: SPARE_SW_RESET_0 - ***************************************************************************/ -/* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 - -/* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 - - -/**************************************************************************** - * I2C_GR_BRIDGE :: SPARE_SW_RESET_1 - ***************************************************************************/ -/* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 - -/* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 -#define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 - - -/**************************************************************************** - * BCM70012_MISC_TOP_MISC1 - ***************************************************************************/ -/**************************************************************************** - * MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 - ***************************************************************************/ -/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 - -/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 - -/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: TX_DESC_LIST0_VALID [00:00] */ -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_MASK 0x00000001 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_ALIGN 0 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_BITS 1 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: TX_FIRST_DESC_U_ADDR_LIST0 - ***************************************************************************/ -/* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ -#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff -#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 -#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 -#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 - ***************************************************************************/ -/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 - -/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 - -/* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: TX_DESC_LIST1_VALID [00:00] */ -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_MASK 0x00000001 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_ALIGN 0 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_BITS 1 -#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: TX_FIRST_DESC_U_ADDR_LIST1 - ***************************************************************************/ -/* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ -#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff -#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 -#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 -#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: TX_SW_DESC_LIST_CTRL_STS - ***************************************************************************/ -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 - -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 - -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 - -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_HALT_ON_ERROR [01:01] */ -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_MASK 0x00000002 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_ALIGN 0 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_BITS 1 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_SHIFT 1 - -/* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */ -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_ALIGN 0 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_BITS 1 -#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: TX_DMA_ERROR_STATUS - ***************************************************************************/ -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved0 [31:10] */ -#define MISC1_TX_DMA_ERROR_STATUS_reserved0_MASK 0xfffffc00 -#define MISC1_TX_DMA_ERROR_STATUS_reserved0_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_reserved0_BITS 22 -#define MISC1_TX_DMA_ERROR_STATUS_reserved0_SHIFT 10 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */ -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved1 [08:08] */ -#define MISC1_TX_DMA_ERROR_STATUS_reserved1_MASK 0x00000100 -#define MISC1_TX_DMA_ERROR_STATUS_reserved1_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_reserved1_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_reserved1_SHIFT 8 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */ -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved2 [06:06] */ -#define MISC1_TX_DMA_ERROR_STATUS_reserved2_MASK 0x00000040 -#define MISC1_TX_DMA_ERROR_STATUS_reserved2_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_reserved2_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_reserved2_SHIFT 6 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DMA_DATA_TX_ABORT_ERRORS [05:05] */ -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000020 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_SHIFT 5 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_FIFO_FULL_ERRORS [04:04] */ -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_SHIFT 4 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved3 [03:03] */ -#define MISC1_TX_DMA_ERROR_STATUS_reserved3_MASK 0x00000008 -#define MISC1_TX_DMA_ERROR_STATUS_reserved3_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_reserved3_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_reserved3_SHIFT 3 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DMA_DATA_TX_ABORT_ERRORS [02:02] */ -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000004 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_SHIFT 2 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_FIFO_FULL_ERRORS [01:01] */ -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_SHIFT 1 - -/* MISC1 :: TX_DMA_ERROR_STATUS :: reserved4 [00:00] */ -#define MISC1_TX_DMA_ERROR_STATUS_reserved4_MASK 0x00000001 -#define MISC1_TX_DMA_ERROR_STATUS_reserved4_ALIGN 0 -#define MISC1_TX_DMA_ERROR_STATUS_reserved4_BITS 1 -#define MISC1_TX_DMA_ERROR_STATUS_reserved4_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR - ***************************************************************************/ -/* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: TX_DMA_L0_CUR_DESC_L_ADDR [31:05] */ -#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 -#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_ALIGN 0 -#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_BITS 27 -#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_SHIFT 5 - -/* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ -#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f -#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 -#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 -#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: TX_DMA_LIST0_CUR_DESC_U_ADDR - ***************************************************************************/ -/* MISC1 :: TX_DMA_LIST0_CUR_DESC_U_ADDR :: TX_DMA_L0_CUR_DESC_U_ADDR [31:00] */ -#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_MASK 0xffffffff -#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_ALIGN 0 -#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_BITS 32 -#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM - ***************************************************************************/ -/* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ -#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 -#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_ALIGN 0 -#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_BITS 8 -#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 - -/* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: TX_DMA_L0_CUR_BYTE_CNT_REM [23:02] */ -#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_MASK 0x00fffffc -#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_ALIGN 0 -#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_BITS 22 -#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_SHIFT 2 - -/* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ -#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 -#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_ALIGN 0 -#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_BITS 2 -#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR - ***************************************************************************/ -/* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: TX_DMA_L1_CUR_DESC_L_ADDR [31:05] */ -#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 -#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_ALIGN 0 -#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_BITS 27 -#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_SHIFT 5 - -/* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ -#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f -#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 -#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 -#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: TX_DMA_LIST1_CUR_DESC_U_ADDR - ***************************************************************************/ -/* MISC1 :: TX_DMA_LIST1_CUR_DESC_U_ADDR :: TX_DMA_L1_CUR_DESC_U_ADDR [31:00] */ -#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_MASK 0xffffffff -#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_ALIGN 0 -#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_BITS 32 -#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM - ***************************************************************************/ -/* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ -#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 -#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_ALIGN 0 -#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_BITS 8 -#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 - -/* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: TX_DMA_L1_CUR_BYTE_CNT_REM [23:02] */ -#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_MASK 0x00fffffc -#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_ALIGN 0 -#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_BITS 22 -#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_SHIFT 2 - -/* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ -#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 -#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_ALIGN 0 -#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_BITS 2 -#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 - ***************************************************************************/ -/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 - -/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 - -/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_ALIGN 0 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_BITS 1 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST0 - ***************************************************************************/ -/* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ -#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff -#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 -#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 -#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 - ***************************************************************************/ -/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 - -/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 - -/* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_ALIGN 0 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_BITS 1 -#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST1 - ***************************************************************************/ -/* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ -#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff -#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 -#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 -#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS - ***************************************************************************/ -/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 - -/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 - -/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 - -/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_ALIGN 0 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_BITS 1 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 - -/* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_ALIGN 0 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_BITS 1 -#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: Y_RX_ERROR_STATUS - ***************************************************************************/ -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved0 [31:14] */ -#define MISC1_Y_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 -#define MISC1_Y_RX_ERROR_STATUS_reserved0_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_reserved0_BITS 18 -#define MISC1_Y_RX_ERROR_STATUS_reserved0_SHIFT 14 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 - -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved1 [08:08] */ -#define MISC1_Y_RX_ERROR_STATUS_reserved1_MASK 0x00000100 -#define MISC1_Y_RX_ERROR_STATUS_reserved1_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_reserved1_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_reserved1_SHIFT 8 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 - -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved2 [06:05] */ -#define MISC1_Y_RX_ERROR_STATUS_reserved2_MASK 0x00000060 -#define MISC1_Y_RX_ERROR_STATUS_reserved2_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_reserved2_BITS 2 -#define MISC1_Y_RX_ERROR_STATUS_reserved2_SHIFT 5 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 - -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved3 [03:02] */ -#define MISC1_Y_RX_ERROR_STATUS_reserved3_MASK 0x0000000c -#define MISC1_Y_RX_ERROR_STATUS_reserved3_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_reserved3_BITS 2 -#define MISC1_Y_RX_ERROR_STATUS_reserved3_SHIFT 2 - -/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 - -/* MISC1 :: Y_RX_ERROR_STATUS :: reserved4 [00:00] */ -#define MISC1_Y_RX_ERROR_STATUS_reserved4_MASK 0x00000001 -#define MISC1_Y_RX_ERROR_STATUS_reserved4_ALIGN 0 -#define MISC1_Y_RX_ERROR_STATUS_reserved4_BITS 1 -#define MISC1_Y_RX_ERROR_STATUS_reserved4_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR - ***************************************************************************/ -/* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ -#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 -#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_ALIGN 0 -#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_BITS 27 -#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 - -/* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ -#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f -#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 -#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 -#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: Y_RX_LIST0_CUR_DESC_U_ADDR - ***************************************************************************/ -/* MISC1 :: Y_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ -#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff -#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_ALIGN 0 -#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_BITS 32 -#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: Y_RX_LIST0_CUR_BYTE_CNT - ***************************************************************************/ -/* MISC1 :: Y_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ -#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff -#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_ALIGN 0 -#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_BITS 32 -#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR - ***************************************************************************/ -/* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ -#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 -#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_ALIGN 0 -#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_BITS 27 -#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 - -/* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ -#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f -#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 -#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 -#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: Y_RX_LIST1_CUR_DESC_U_ADDR - ***************************************************************************/ -/* MISC1 :: Y_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ -#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff -#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_ALIGN 0 -#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_BITS 32 -#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: Y_RX_LIST1_CUR_BYTE_CNT - ***************************************************************************/ -/* MISC1 :: Y_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ -#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff -#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_ALIGN 0 -#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_BITS 32 -#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 - ***************************************************************************/ -/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 - -/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 - -/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_ALIGN 0 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_BITS 1 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST0 - ***************************************************************************/ -/* MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ -#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff -#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 -#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 -#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 - ***************************************************************************/ -/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 - -/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 - -/* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_ALIGN 0 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_BITS 1 -#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST1 - ***************************************************************************/ -/* MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ -#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff -#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 -#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 -#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS - ***************************************************************************/ -/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 - -/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 - -/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 - -/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_ALIGN 0 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_BITS 1 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 - -/* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_ALIGN 0 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_BITS 1 -#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: UV_RX_ERROR_STATUS - ***************************************************************************/ -/* MISC1 :: UV_RX_ERROR_STATUS :: reserved0 [31:14] */ -#define MISC1_UV_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 -#define MISC1_UV_RX_ERROR_STATUS_reserved0_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_reserved0_BITS 18 -#define MISC1_UV_RX_ERROR_STATUS_reserved0_SHIFT 14 - -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 - -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 - -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 - -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 - -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 - -/* MISC1 :: UV_RX_ERROR_STATUS :: reserved1 [08:08] */ -#define MISC1_UV_RX_ERROR_STATUS_reserved1_MASK 0x00000100 -#define MISC1_UV_RX_ERROR_STATUS_reserved1_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_reserved1_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_reserved1_SHIFT 8 - -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 - -/* MISC1 :: UV_RX_ERROR_STATUS :: reserved2 [06:05] */ -#define MISC1_UV_RX_ERROR_STATUS_reserved2_MASK 0x00000060 -#define MISC1_UV_RX_ERROR_STATUS_reserved2_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_reserved2_BITS 2 -#define MISC1_UV_RX_ERROR_STATUS_reserved2_SHIFT 5 - -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 - -/* MISC1 :: UV_RX_ERROR_STATUS :: reserved3 [03:02] */ -#define MISC1_UV_RX_ERROR_STATUS_reserved3_MASK 0x0000000c -#define MISC1_UV_RX_ERROR_STATUS_reserved3_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_reserved3_BITS 2 -#define MISC1_UV_RX_ERROR_STATUS_reserved3_SHIFT 2 - -/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 - -/* MISC1 :: UV_RX_ERROR_STATUS :: reserved4 [00:00] */ -#define MISC1_UV_RX_ERROR_STATUS_reserved4_MASK 0x00000001 -#define MISC1_UV_RX_ERROR_STATUS_reserved4_ALIGN 0 -#define MISC1_UV_RX_ERROR_STATUS_reserved4_BITS 1 -#define MISC1_UV_RX_ERROR_STATUS_reserved4_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR - ***************************************************************************/ -/* MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ -#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 -#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_ALIGN 0 -#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_BITS 27 -#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 - -/* MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ -#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f -#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 -#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 -#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: UV_RX_LIST0_CUR_DESC_U_ADDR - ***************************************************************************/ -/* MISC1 :: UV_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ -#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff -#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_ALIGN 0 -#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_BITS 32 -#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: UV_RX_LIST0_CUR_BYTE_CNT - ***************************************************************************/ -/* MISC1 :: UV_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ -#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff -#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_ALIGN 0 -#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_BITS 32 -#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR - ***************************************************************************/ -/* MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ -#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 -#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_ALIGN 0 -#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_BITS 27 -#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 - -/* MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ -#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f -#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 -#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 -#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: UV_RX_LIST1_CUR_DESC_U_ADDR - ***************************************************************************/ -/* MISC1 :: UV_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ -#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff -#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_ALIGN 0 -#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_BITS 32 -#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: UV_RX_LIST1_CUR_BYTE_CNT - ***************************************************************************/ -/* MISC1 :: UV_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ -#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff -#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_ALIGN 0 -#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_BITS 32 -#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: DMA_DEBUG_OPTIONS_REG - ***************************************************************************/ -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_SOFT_RST [31:31] */ -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_MASK 0x80000000 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_ALIGN 0 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_BITS 1 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_SHIFT 31 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_SOFT_RST [30:30] */ -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_MASK 0x40000000 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_ALIGN 0 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_BITS 1 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_SHIFT 30 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST [29:29] */ -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_MASK 0x20000000 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_ALIGN 0 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_BITS 1 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_SHIFT 29 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST [28:28] */ -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_MASK 0x10000000 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_ALIGN 0 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_BITS 1 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_SHIFT 28 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_0 [27:05] */ -#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_MASK 0x0fffffe0 -#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_ALIGN 0 -#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_BITS 23 -#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_SHIFT 5 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_EN_RX_DMA_XFER_CNT [04:04] */ -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_MASK 0x00000010 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_ALIGN 0 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_BITS 1 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_SHIFT 4 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_1 [03:03] */ -#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_MASK 0x00000008 -#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_ALIGN 0 -#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_BITS 1 -#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_SHIFT 3 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_RD_Q [02:02] */ -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_MASK 0x00000004 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_ALIGN 0 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_BITS 1 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_SHIFT 2 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_WR_Q [01:01] */ -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_MASK 0x00000002 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_ALIGN 0 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_BITS 1 -#define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_SHIFT 1 - -/* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_2 [00:00] */ -#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_MASK 0x00000001 -#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_ALIGN 0 -#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_BITS 1 -#define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: READ_CHANNEL_ERROR_STATUS - ***************************************************************************/ -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_7 [31:28] */ -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_MASK 0xf0000000 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_ALIGN 0 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_BITS 4 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_SHIFT 28 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_6 [27:24] */ -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_MASK 0x0f000000 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_ALIGN 0 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_BITS 4 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_SHIFT 24 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_5 [23:20] */ -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_MASK 0x00f00000 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_ALIGN 0 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_BITS 4 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_SHIFT 20 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_4 [19:16] */ -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_MASK 0x000f0000 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_ALIGN 0 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_BITS 4 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_SHIFT 16 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_3 [15:12] */ -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_MASK 0x0000f000 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_ALIGN 0 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_BITS 4 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_SHIFT 12 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_2 [11:08] */ -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_MASK 0x00000f00 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_ALIGN 0 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_BITS 4 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_SHIFT 8 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_1 [07:04] */ -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_MASK 0x000000f0 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_ALIGN 0 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_BITS 4 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_SHIFT 4 - -/* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_0 [03:00] */ -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_MASK 0x0000000f -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_ALIGN 0 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_BITS 4 -#define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_SHIFT 0 - - -/**************************************************************************** - * MISC1 :: PCIE_DMA_CTRL - ***************************************************************************/ -/* MISC1 :: PCIE_DMA_CTRL :: reserved0 [31:18] */ -#define MISC1_PCIE_DMA_CTRL_reserved0_MASK 0xfffc0000 -#define MISC1_PCIE_DMA_CTRL_reserved0_ALIGN 0 -#define MISC1_PCIE_DMA_CTRL_reserved0_BITS 14 -#define MISC1_PCIE_DMA_CTRL_reserved0_SHIFT 18 - -/* MISC1 :: PCIE_DMA_CTRL :: DESC_ENDIAN_MODE [17:16] */ -#define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_MASK 0x00030000 -#define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_ALIGN 0 -#define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_BITS 2 -#define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_SHIFT 16 - -/* MISC1 :: PCIE_DMA_CTRL :: reserved1 [15:10] */ -#define MISC1_PCIE_DMA_CTRL_reserved1_MASK 0x0000fc00 -#define MISC1_PCIE_DMA_CTRL_reserved1_ALIGN 0 -#define MISC1_PCIE_DMA_CTRL_reserved1_BITS 6 -#define MISC1_PCIE_DMA_CTRL_reserved1_SHIFT 10 - -/* MISC1 :: PCIE_DMA_CTRL :: EN_WEIGHTED_RR [09:09] */ -#define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_MASK 0x00000200 -#define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_ALIGN 0 -#define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_BITS 1 -#define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_SHIFT 9 - -/* MISC1 :: PCIE_DMA_CTRL :: EN_ROUND_ROBIN [08:08] */ -#define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_MASK 0x00000100 -#define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_ALIGN 0 -#define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_BITS 1 -#define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_SHIFT 8 - -/* MISC1 :: PCIE_DMA_CTRL :: reserved2 [07:05] */ -#define MISC1_PCIE_DMA_CTRL_reserved2_MASK 0x000000e0 -#define MISC1_PCIE_DMA_CTRL_reserved2_ALIGN 0 -#define MISC1_PCIE_DMA_CTRL_reserved2_BITS 3 -#define MISC1_PCIE_DMA_CTRL_reserved2_SHIFT 5 - -/* MISC1 :: PCIE_DMA_CTRL :: RELAXED_ORDERING [04:04] */ -#define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_MASK 0x00000010 -#define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_ALIGN 0 -#define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_BITS 1 -#define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_SHIFT 4 - -/* MISC1 :: PCIE_DMA_CTRL :: NO_SNOOP [03:03] */ -#define MISC1_PCIE_DMA_CTRL_NO_SNOOP_MASK 0x00000008 -#define MISC1_PCIE_DMA_CTRL_NO_SNOOP_ALIGN 0 -#define MISC1_PCIE_DMA_CTRL_NO_SNOOP_BITS 1 -#define MISC1_PCIE_DMA_CTRL_NO_SNOOP_SHIFT 3 - -/* MISC1 :: PCIE_DMA_CTRL :: TRAFFIC_CLASS [02:00] */ -#define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_MASK 0x00000007 -#define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_ALIGN 0 -#define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_BITS 3 -#define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_SHIFT 0 - - -/**************************************************************************** - * BCM70012_MISC_TOP_MISC2 - ***************************************************************************/ -/**************************************************************************** - * MISC2 :: GLOBAL_CTRL - ***************************************************************************/ -/* MISC2 :: GLOBAL_CTRL :: reserved0 [31:21] */ -#define MISC2_GLOBAL_CTRL_reserved0_MASK 0xffe00000 -#define MISC2_GLOBAL_CTRL_reserved0_ALIGN 0 -#define MISC2_GLOBAL_CTRL_reserved0_BITS 11 -#define MISC2_GLOBAL_CTRL_reserved0_SHIFT 21 - -/* MISC2 :: GLOBAL_CTRL :: EN_WRITE_ALL [20:20] */ -#define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_MASK 0x00100000 -#define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_ALIGN 0 -#define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_BITS 1 -#define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_SHIFT 20 - -/* MISC2 :: GLOBAL_CTRL :: reserved1 [19:17] */ -#define MISC2_GLOBAL_CTRL_reserved1_MASK 0x000e0000 -#define MISC2_GLOBAL_CTRL_reserved1_ALIGN 0 -#define MISC2_GLOBAL_CTRL_reserved1_BITS 3 -#define MISC2_GLOBAL_CTRL_reserved1_SHIFT 17 - -/* MISC2 :: GLOBAL_CTRL :: EN_SINGLE_DMA [16:16] */ -#define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_MASK 0x00010000 -#define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_ALIGN 0 -#define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_BITS 1 -#define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_SHIFT 16 - -/* MISC2 :: GLOBAL_CTRL :: reserved2 [15:11] */ -#define MISC2_GLOBAL_CTRL_reserved2_MASK 0x0000f800 -#define MISC2_GLOBAL_CTRL_reserved2_ALIGN 0 -#define MISC2_GLOBAL_CTRL_reserved2_BITS 5 -#define MISC2_GLOBAL_CTRL_reserved2_SHIFT 11 - -/* MISC2 :: GLOBAL_CTRL :: Y_UV_FIFO_LEN_SEL [10:10] */ -#define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_MASK 0x00000400 -#define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_ALIGN 0 -#define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_BITS 1 -#define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_SHIFT 10 - -/* MISC2 :: GLOBAL_CTRL :: ODD_DE_EOFRST_DIS [09:09] */ -#define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_MASK 0x00000200 -#define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_ALIGN 0 -#define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_BITS 1 -#define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_SHIFT 9 - -/* MISC2 :: GLOBAL_CTRL :: DIS_BIT_STUFFING [08:08] */ -#define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_MASK 0x00000100 -#define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_ALIGN 0 -#define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_BITS 1 -#define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_SHIFT 8 - -/* MISC2 :: GLOBAL_CTRL :: reserved3 [07:05] */ -#define MISC2_GLOBAL_CTRL_reserved3_MASK 0x000000e0 -#define MISC2_GLOBAL_CTRL_reserved3_ALIGN 0 -#define MISC2_GLOBAL_CTRL_reserved3_BITS 3 -#define MISC2_GLOBAL_CTRL_reserved3_SHIFT 5 - -/* MISC2 :: GLOBAL_CTRL :: EN_PROG_MODE [04:04] */ -#define MISC2_GLOBAL_CTRL_EN_PROG_MODE_MASK 0x00000010 -#define MISC2_GLOBAL_CTRL_EN_PROG_MODE_ALIGN 0 -#define MISC2_GLOBAL_CTRL_EN_PROG_MODE_BITS 1 -#define MISC2_GLOBAL_CTRL_EN_PROG_MODE_SHIFT 4 - -/* MISC2 :: GLOBAL_CTRL :: reserved4 [03:01] */ -#define MISC2_GLOBAL_CTRL_reserved4_MASK 0x0000000e -#define MISC2_GLOBAL_CTRL_reserved4_ALIGN 0 -#define MISC2_GLOBAL_CTRL_reserved4_BITS 3 -#define MISC2_GLOBAL_CTRL_reserved4_SHIFT 1 - -/* MISC2 :: GLOBAL_CTRL :: EN_188B [00:00] */ -#define MISC2_GLOBAL_CTRL_EN_188B_MASK 0x00000001 -#define MISC2_GLOBAL_CTRL_EN_188B_ALIGN 0 -#define MISC2_GLOBAL_CTRL_EN_188B_BITS 1 -#define MISC2_GLOBAL_CTRL_EN_188B_SHIFT 0 - - -/**************************************************************************** - * MISC2 :: INTERNAL_STATUS - ***************************************************************************/ -/* MISC2 :: INTERNAL_STATUS :: reserved0 [31:12] */ -#define MISC2_INTERNAL_STATUS_reserved0_MASK 0xfffff000 -#define MISC2_INTERNAL_STATUS_reserved0_ALIGN 0 -#define MISC2_INTERNAL_STATUS_reserved0_BITS 20 -#define MISC2_INTERNAL_STATUS_reserved0_SHIFT 12 - -/* MISC2 :: INTERNAL_STATUS :: UV_BYTE_COUNT_FIFO_FULL [11:11] */ -#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_MASK 0x00000800 -#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_ALIGN 0 -#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_BITS 1 -#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_SHIFT 11 - -/* MISC2 :: INTERNAL_STATUS :: UV_DATA_FIFO_FULL [10:10] */ -#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_MASK 0x00000400 -#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_ALIGN 0 -#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_BITS 1 -#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_SHIFT 10 - -/* MISC2 :: INTERNAL_STATUS :: Y_BYTE_COUNT_FIFO_FULL [09:09] */ -#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_MASK 0x00000200 -#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_ALIGN 0 -#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_BITS 1 -#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_SHIFT 9 - -/* MISC2 :: INTERNAL_STATUS :: Y_DATA_FIFO_FULL [08:08] */ -#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_MASK 0x00000100 -#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_ALIGN 0 -#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_BITS 1 -#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_SHIFT 8 - -/* MISC2 :: INTERNAL_STATUS :: UV_BYTE_COUNT_FIFO_EMPTY [07:07] */ -#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_MASK 0x00000080 -#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_ALIGN 0 -#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_BITS 1 -#define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_SHIFT 7 - -/* MISC2 :: INTERNAL_STATUS :: UV_DATA_FIFO_EMPTY [06:06] */ -#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_MASK 0x00000040 -#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_ALIGN 0 -#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_BITS 1 -#define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_SHIFT 6 - -/* MISC2 :: INTERNAL_STATUS :: Y_BYTE_COUNT_FIFO_EMPTY [05:05] */ -#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_MASK 0x00000020 -#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_ALIGN 0 -#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_BITS 1 -#define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_SHIFT 5 - -/* MISC2 :: INTERNAL_STATUS :: Y_DATA_FIFO_EMPTY [04:04] */ -#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_MASK 0x00000010 -#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_ALIGN 0 -#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_BITS 1 -#define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_SHIFT 4 - -/* MISC2 :: INTERNAL_STATUS :: reserved1 [03:00] */ -#define MISC2_INTERNAL_STATUS_reserved1_MASK 0x0000000f -#define MISC2_INTERNAL_STATUS_reserved1_ALIGN 0 -#define MISC2_INTERNAL_STATUS_reserved1_BITS 4 -#define MISC2_INTERNAL_STATUS_reserved1_SHIFT 0 - - -/**************************************************************************** - * MISC2 :: INTERNAL_STATUS_MUX_CTRL - ***************************************************************************/ -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved0 [31:16] */ -#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_MASK 0xffff0000 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_ALIGN 0 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_BITS 16 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_SHIFT 16 - -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: CLK_OUT_ALT_SRC [15:15] */ -#define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_MASK 0x00008000 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_ALIGN 0 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_BITS 1 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_SHIFT 15 - -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CLK_SEL [14:12] */ -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_MASK 0x00007000 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_ALIGN 0 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_BITS 3 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_SHIFT 12 - -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved1 [11:09] */ -#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_MASK 0x00000e00 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_ALIGN 0 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_BITS 3 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_SHIFT 9 - -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_TOP_CORE_SEL [08:08] */ -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_MASK 0x00000100 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_ALIGN 0 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_BITS 1 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_SHIFT 8 - -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CORE_BLK_SEL [07:04] */ -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_MASK 0x000000f0 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_ALIGN 0 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_BITS 4 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_SHIFT 4 - -/* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_VECTOR_SEL [03:00] */ -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_MASK 0x0000000f -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_ALIGN 0 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_BITS 4 -#define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_SHIFT 0 - - -/**************************************************************************** - * MISC2 :: DEBUG_FIFO_LENGTH - ***************************************************************************/ -/* MISC2 :: DEBUG_FIFO_LENGTH :: reserved0 [31:21] */ -#define MISC2_DEBUG_FIFO_LENGTH_reserved0_MASK 0xffe00000 -#define MISC2_DEBUG_FIFO_LENGTH_reserved0_ALIGN 0 -#define MISC2_DEBUG_FIFO_LENGTH_reserved0_BITS 11 -#define MISC2_DEBUG_FIFO_LENGTH_reserved0_SHIFT 21 - -/* MISC2 :: DEBUG_FIFO_LENGTH :: FIFO_LENGTH [20:00] */ -#define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_MASK 0x001fffff -#define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_ALIGN 0 -#define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_BITS 21 -#define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_SHIFT 0 - - -/**************************************************************************** - * BCM70012_MISC_TOP_MISC3 - ***************************************************************************/ -/**************************************************************************** - * MISC3 :: RESET_CTRL - ***************************************************************************/ -/* MISC3 :: RESET_CTRL :: reserved0 [31:09] */ -#define MISC3_RESET_CTRL_reserved0_MASK 0xfffffe00 -#define MISC3_RESET_CTRL_reserved0_ALIGN 0 -#define MISC3_RESET_CTRL_reserved0_BITS 23 -#define MISC3_RESET_CTRL_reserved0_SHIFT 9 - -/* MISC3 :: RESET_CTRL :: PLL_RESET [08:08] */ -#define MISC3_RESET_CTRL_PLL_RESET_MASK 0x00000100 -#define MISC3_RESET_CTRL_PLL_RESET_ALIGN 0 -#define MISC3_RESET_CTRL_PLL_RESET_BITS 1 -#define MISC3_RESET_CTRL_PLL_RESET_SHIFT 8 - -/* MISC3 :: RESET_CTRL :: reserved1 [07:02] */ -#define MISC3_RESET_CTRL_reserved1_MASK 0x000000fc -#define MISC3_RESET_CTRL_reserved1_ALIGN 0 -#define MISC3_RESET_CTRL_reserved1_BITS 6 -#define MISC3_RESET_CTRL_reserved1_SHIFT 2 - -/* MISC3 :: RESET_CTRL :: POR_RESET [01:01] */ -#define MISC3_RESET_CTRL_POR_RESET_MASK 0x00000002 -#define MISC3_RESET_CTRL_POR_RESET_ALIGN 0 -#define MISC3_RESET_CTRL_POR_RESET_BITS 1 -#define MISC3_RESET_CTRL_POR_RESET_SHIFT 1 - -/* MISC3 :: RESET_CTRL :: CORE_RESET [00:00] */ -#define MISC3_RESET_CTRL_CORE_RESET_MASK 0x00000001 -#define MISC3_RESET_CTRL_CORE_RESET_ALIGN 0 -#define MISC3_RESET_CTRL_CORE_RESET_BITS 1 -#define MISC3_RESET_CTRL_CORE_RESET_SHIFT 0 - - -/**************************************************************************** - * MISC3 :: BIST_CTRL - ***************************************************************************/ -/* MISC3 :: BIST_CTRL :: MBIST_OVERRIDE [31:31] */ -#define MISC3_BIST_CTRL_MBIST_OVERRIDE_MASK 0x80000000 -#define MISC3_BIST_CTRL_MBIST_OVERRIDE_ALIGN 0 -#define MISC3_BIST_CTRL_MBIST_OVERRIDE_BITS 1 -#define MISC3_BIST_CTRL_MBIST_OVERRIDE_SHIFT 31 - -/* MISC3 :: BIST_CTRL :: reserved0 [30:15] */ -#define MISC3_BIST_CTRL_reserved0_MASK 0x7fff8000 -#define MISC3_BIST_CTRL_reserved0_ALIGN 0 -#define MISC3_BIST_CTRL_reserved0_BITS 16 -#define MISC3_BIST_CTRL_reserved0_SHIFT 15 - -/* MISC3 :: BIST_CTRL :: MBIST_EN_2 [14:14] */ -#define MISC3_BIST_CTRL_MBIST_EN_2_MASK 0x00004000 -#define MISC3_BIST_CTRL_MBIST_EN_2_ALIGN 0 -#define MISC3_BIST_CTRL_MBIST_EN_2_BITS 1 -#define MISC3_BIST_CTRL_MBIST_EN_2_SHIFT 14 - -/* MISC3 :: BIST_CTRL :: MBIST_EN_1 [13:13] */ -#define MISC3_BIST_CTRL_MBIST_EN_1_MASK 0x00002000 -#define MISC3_BIST_CTRL_MBIST_EN_1_ALIGN 0 -#define MISC3_BIST_CTRL_MBIST_EN_1_BITS 1 -#define MISC3_BIST_CTRL_MBIST_EN_1_SHIFT 13 - -/* MISC3 :: BIST_CTRL :: MBIST_EN_0 [12:12] */ -#define MISC3_BIST_CTRL_MBIST_EN_0_MASK 0x00001000 -#define MISC3_BIST_CTRL_MBIST_EN_0_ALIGN 0 -#define MISC3_BIST_CTRL_MBIST_EN_0_BITS 1 -#define MISC3_BIST_CTRL_MBIST_EN_0_SHIFT 12 - -/* MISC3 :: BIST_CTRL :: reserved1 [11:06] */ -#define MISC3_BIST_CTRL_reserved1_MASK 0x00000fc0 -#define MISC3_BIST_CTRL_reserved1_ALIGN 0 -#define MISC3_BIST_CTRL_reserved1_BITS 6 -#define MISC3_BIST_CTRL_reserved1_SHIFT 6 - -/* MISC3 :: BIST_CTRL :: MBIST_SETUP [05:04] */ -#define MISC3_BIST_CTRL_MBIST_SETUP_MASK 0x00000030 -#define MISC3_BIST_CTRL_MBIST_SETUP_ALIGN 0 -#define MISC3_BIST_CTRL_MBIST_SETUP_BITS 2 -#define MISC3_BIST_CTRL_MBIST_SETUP_SHIFT 4 - -/* MISC3 :: BIST_CTRL :: reserved2 [03:01] */ -#define MISC3_BIST_CTRL_reserved2_MASK 0x0000000e -#define MISC3_BIST_CTRL_reserved2_ALIGN 0 -#define MISC3_BIST_CTRL_reserved2_BITS 3 -#define MISC3_BIST_CTRL_reserved2_SHIFT 1 - -/* MISC3 :: BIST_CTRL :: MBIST_ASYNC_RESET [00:00] */ -#define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_MASK 0x00000001 -#define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_ALIGN 0 -#define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_BITS 1 -#define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_SHIFT 0 - - -/**************************************************************************** - * MISC3 :: BIST_STATUS - ***************************************************************************/ -/* MISC3 :: BIST_STATUS :: reserved0 [31:31] */ -#define MISC3_BIST_STATUS_reserved0_MASK 0x80000000 -#define MISC3_BIST_STATUS_reserved0_ALIGN 0 -#define MISC3_BIST_STATUS_reserved0_BITS 1 -#define MISC3_BIST_STATUS_reserved0_SHIFT 31 - -/* MISC3 :: BIST_STATUS :: MBIST_GO_2 [30:30] */ -#define MISC3_BIST_STATUS_MBIST_GO_2_MASK 0x40000000 -#define MISC3_BIST_STATUS_MBIST_GO_2_ALIGN 0 -#define MISC3_BIST_STATUS_MBIST_GO_2_BITS 1 -#define MISC3_BIST_STATUS_MBIST_GO_2_SHIFT 30 - -/* MISC3 :: BIST_STATUS :: MBIST_GO_1 [29:29] */ -#define MISC3_BIST_STATUS_MBIST_GO_1_MASK 0x20000000 -#define MISC3_BIST_STATUS_MBIST_GO_1_ALIGN 0 -#define MISC3_BIST_STATUS_MBIST_GO_1_BITS 1 -#define MISC3_BIST_STATUS_MBIST_GO_1_SHIFT 29 - -/* MISC3 :: BIST_STATUS :: MBIST_GO_0 [28:28] */ -#define MISC3_BIST_STATUS_MBIST_GO_0_MASK 0x10000000 -#define MISC3_BIST_STATUS_MBIST_GO_0_ALIGN 0 -#define MISC3_BIST_STATUS_MBIST_GO_0_BITS 1 -#define MISC3_BIST_STATUS_MBIST_GO_0_SHIFT 28 - -/* MISC3 :: BIST_STATUS :: reserved1 [27:27] */ -#define MISC3_BIST_STATUS_reserved1_MASK 0x08000000 -#define MISC3_BIST_STATUS_reserved1_ALIGN 0 -#define MISC3_BIST_STATUS_reserved1_BITS 1 -#define MISC3_BIST_STATUS_reserved1_SHIFT 27 - -/* MISC3 :: BIST_STATUS :: MBIST_DONE_2 [26:26] */ -#define MISC3_BIST_STATUS_MBIST_DONE_2_MASK 0x04000000 -#define MISC3_BIST_STATUS_MBIST_DONE_2_ALIGN 0 -#define MISC3_BIST_STATUS_MBIST_DONE_2_BITS 1 -#define MISC3_BIST_STATUS_MBIST_DONE_2_SHIFT 26 - -/* MISC3 :: BIST_STATUS :: MBIST_DONE_1 [25:25] */ -#define MISC3_BIST_STATUS_MBIST_DONE_1_MASK 0x02000000 -#define MISC3_BIST_STATUS_MBIST_DONE_1_ALIGN 0 -#define MISC3_BIST_STATUS_MBIST_DONE_1_BITS 1 -#define MISC3_BIST_STATUS_MBIST_DONE_1_SHIFT 25 - -/* MISC3 :: BIST_STATUS :: MBIST_DONE_0 [24:24] */ -#define MISC3_BIST_STATUS_MBIST_DONE_0_MASK 0x01000000 -#define MISC3_BIST_STATUS_MBIST_DONE_0_ALIGN 0 -#define MISC3_BIST_STATUS_MBIST_DONE_0_BITS 1 -#define MISC3_BIST_STATUS_MBIST_DONE_0_SHIFT 24 - -/* MISC3 :: BIST_STATUS :: reserved2 [23:06] */ -#define MISC3_BIST_STATUS_reserved2_MASK 0x00ffffc0 -#define MISC3_BIST_STATUS_reserved2_ALIGN 0 -#define MISC3_BIST_STATUS_reserved2_BITS 18 -#define MISC3_BIST_STATUS_reserved2_SHIFT 6 - -/* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_2 [05:04] */ -#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_MASK 0x00000030 -#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_ALIGN 0 -#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_BITS 2 -#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_SHIFT 4 - -/* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_1 [03:02] */ -#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_MASK 0x0000000c -#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_ALIGN 0 -#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_BITS 2 -#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_SHIFT 2 - -/* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_0 [01:00] */ -#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_MASK 0x00000003 -#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_ALIGN 0 -#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_BITS 2 -#define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_SHIFT 0 - - -/**************************************************************************** - * MISC3 :: RX_CHECKSUM - ***************************************************************************/ -/* MISC3 :: RX_CHECKSUM :: RX_CHECKSUM [31:00] */ -#define MISC3_RX_CHECKSUM_RX_CHECKSUM_MASK 0xffffffff -#define MISC3_RX_CHECKSUM_RX_CHECKSUM_ALIGN 0 -#define MISC3_RX_CHECKSUM_RX_CHECKSUM_BITS 32 -#define MISC3_RX_CHECKSUM_RX_CHECKSUM_SHIFT 0 - - -/**************************************************************************** - * MISC3 :: TX_CHECKSUM - ***************************************************************************/ -/* MISC3 :: TX_CHECKSUM :: TX_CHECKSUM [31:00] */ -#define MISC3_TX_CHECKSUM_TX_CHECKSUM_MASK 0xffffffff -#define MISC3_TX_CHECKSUM_TX_CHECKSUM_ALIGN 0 -#define MISC3_TX_CHECKSUM_TX_CHECKSUM_BITS 32 -#define MISC3_TX_CHECKSUM_TX_CHECKSUM_SHIFT 0 - - -/**************************************************************************** - * MISC3 :: ECO_CTRL_CORE - ***************************************************************************/ -/* MISC3 :: ECO_CTRL_CORE :: reserved0 [31:16] */ -#define MISC3_ECO_CTRL_CORE_reserved0_MASK 0xffff0000 -#define MISC3_ECO_CTRL_CORE_reserved0_ALIGN 0 -#define MISC3_ECO_CTRL_CORE_reserved0_BITS 16 -#define MISC3_ECO_CTRL_CORE_reserved0_SHIFT 16 - -/* MISC3 :: ECO_CTRL_CORE :: ECO_CORE_RST_N [15:00] */ -#define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_MASK 0x0000ffff -#define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_ALIGN 0 -#define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_BITS 16 -#define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_SHIFT 0 - - -/**************************************************************************** - * MISC3 :: CSI_TEST_CTRL - ***************************************************************************/ -/* MISC3 :: CSI_TEST_CTRL :: ENABLE_CSI_TEST [31:31] */ -#define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_MASK 0x80000000 -#define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_ALIGN 0 -#define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_BITS 1 -#define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_SHIFT 31 - -/* MISC3 :: CSI_TEST_CTRL :: reserved0 [30:24] */ -#define MISC3_CSI_TEST_CTRL_reserved0_MASK 0x7f000000 -#define MISC3_CSI_TEST_CTRL_reserved0_ALIGN 0 -#define MISC3_CSI_TEST_CTRL_reserved0_BITS 7 -#define MISC3_CSI_TEST_CTRL_reserved0_SHIFT 24 - -/* MISC3 :: CSI_TEST_CTRL :: CSI_CLOCK_ENABLE [23:16] */ -#define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_MASK 0x00ff0000 -#define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_ALIGN 0 -#define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_BITS 8 -#define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_SHIFT 16 - -/* MISC3 :: CSI_TEST_CTRL :: CSI_SYNC [15:08] */ -#define MISC3_CSI_TEST_CTRL_CSI_SYNC_MASK 0x0000ff00 -#define MISC3_CSI_TEST_CTRL_CSI_SYNC_ALIGN 0 -#define MISC3_CSI_TEST_CTRL_CSI_SYNC_BITS 8 -#define MISC3_CSI_TEST_CTRL_CSI_SYNC_SHIFT 8 - -/* MISC3 :: CSI_TEST_CTRL :: CSI_DATA [07:00] */ -#define MISC3_CSI_TEST_CTRL_CSI_DATA_MASK 0x000000ff -#define MISC3_CSI_TEST_CTRL_CSI_DATA_ALIGN 0 -#define MISC3_CSI_TEST_CTRL_CSI_DATA_BITS 8 -#define MISC3_CSI_TEST_CTRL_CSI_DATA_SHIFT 0 - - -/**************************************************************************** - * MISC3 :: HD_DVI_TEST_CTRL - ***************************************************************************/ -/* MISC3 :: HD_DVI_TEST_CTRL :: reserved0 [31:25] */ -#define MISC3_HD_DVI_TEST_CTRL_reserved0_MASK 0xfe000000 -#define MISC3_HD_DVI_TEST_CTRL_reserved0_ALIGN 0 -#define MISC3_HD_DVI_TEST_CTRL_reserved0_BITS 7 -#define MISC3_HD_DVI_TEST_CTRL_reserved0_SHIFT 25 - -/* MISC3 :: HD_DVI_TEST_CTRL :: POS_VIDO_VBLANK_N [24:24] */ -#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_MASK 0x01000000 -#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_ALIGN 0 -#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_BITS 1 -#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_SHIFT 24 - -/* MISC3 :: HD_DVI_TEST_CTRL :: NEG_VIDO_DVI_DATA [23:12] */ -#define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_MASK 0x00fff000 -#define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_ALIGN 0 -#define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_BITS 12 -#define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_SHIFT 12 - -/* MISC3 :: HD_DVI_TEST_CTRL :: POS_VIDO_DVI_DATA [11:00] */ -#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_MASK 0x00000fff -#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_ALIGN 0 -#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_BITS 12 -#define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_SHIFT 0 - - -/**************************************************************************** - * BCM70012_MISC_TOP_MISC_PERST - ***************************************************************************/ -/**************************************************************************** - * MISC_PERST :: ECO_CTRL_PERST - ***************************************************************************/ -/* MISC_PERST :: ECO_CTRL_PERST :: reserved0 [31:16] */ -#define MISC_PERST_ECO_CTRL_PERST_reserved0_MASK 0xffff0000 -#define MISC_PERST_ECO_CTRL_PERST_reserved0_ALIGN 0 -#define MISC_PERST_ECO_CTRL_PERST_reserved0_BITS 16 -#define MISC_PERST_ECO_CTRL_PERST_reserved0_SHIFT 16 - -/* MISC_PERST :: ECO_CTRL_PERST :: ECO_PERST_N [15:00] */ -#define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_MASK 0x0000ffff -#define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_ALIGN 0 -#define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_BITS 16 -#define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_SHIFT 0 - - -/**************************************************************************** - * MISC_PERST :: DECODER_CTRL - ***************************************************************************/ -/* MISC_PERST :: DECODER_CTRL :: reserved0 [31:05] */ -#define MISC_PERST_DECODER_CTRL_reserved0_MASK 0xffffffe0 -#define MISC_PERST_DECODER_CTRL_reserved0_ALIGN 0 -#define MISC_PERST_DECODER_CTRL_reserved0_BITS 27 -#define MISC_PERST_DECODER_CTRL_reserved0_SHIFT 5 - -/* MISC_PERST :: DECODER_CTRL :: STOP_BCM7412_CLK [04:04] */ -#define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_MASK 0x00000010 -#define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_ALIGN 0 -#define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_BITS 1 -#define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_SHIFT 4 - -/* MISC_PERST :: DECODER_CTRL :: reserved1 [03:01] */ -#define MISC_PERST_DECODER_CTRL_reserved1_MASK 0x0000000e -#define MISC_PERST_DECODER_CTRL_reserved1_ALIGN 0 -#define MISC_PERST_DECODER_CTRL_reserved1_BITS 3 -#define MISC_PERST_DECODER_CTRL_reserved1_SHIFT 1 - -/* MISC_PERST :: DECODER_CTRL :: BCM7412_RESET [00:00] */ -#define MISC_PERST_DECODER_CTRL_BCM7412_RESET_MASK 0x00000001 -#define MISC_PERST_DECODER_CTRL_BCM7412_RESET_ALIGN 0 -#define MISC_PERST_DECODER_CTRL_BCM7412_RESET_BITS 1 -#define MISC_PERST_DECODER_CTRL_BCM7412_RESET_SHIFT 0 - - -/**************************************************************************** - * MISC_PERST :: CCE_STATUS - ***************************************************************************/ -/* MISC_PERST :: CCE_STATUS :: CCE_DONE [31:31] */ -#define MISC_PERST_CCE_STATUS_CCE_DONE_MASK 0x80000000 -#define MISC_PERST_CCE_STATUS_CCE_DONE_ALIGN 0 -#define MISC_PERST_CCE_STATUS_CCE_DONE_BITS 1 -#define MISC_PERST_CCE_STATUS_CCE_DONE_SHIFT 31 - -/* MISC_PERST :: CCE_STATUS :: reserved0 [30:03] */ -#define MISC_PERST_CCE_STATUS_reserved0_MASK 0x7ffffff8 -#define MISC_PERST_CCE_STATUS_reserved0_ALIGN 0 -#define MISC_PERST_CCE_STATUS_reserved0_BITS 28 -#define MISC_PERST_CCE_STATUS_reserved0_SHIFT 3 - -/* MISC_PERST :: CCE_STATUS :: CCE_BAD_GISB_ACCESS [02:02] */ -#define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_MASK 0x00000004 -#define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_ALIGN 0 -#define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_BITS 1 -#define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_SHIFT 2 - -/* MISC_PERST :: CCE_STATUS :: CCE_BAD_I2C_ACCESS [01:01] */ -#define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_MASK 0x00000002 -#define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_ALIGN 0 -#define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_BITS 1 -#define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_SHIFT 1 - -/* MISC_PERST :: CCE_STATUS :: CCE_BAD_SECTION_ID [00:00] */ -#define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_MASK 0x00000001 -#define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_ALIGN 0 -#define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_BITS 1 -#define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_SHIFT 0 - - -/**************************************************************************** - * MISC_PERST :: PCIE_DEBUG - ***************************************************************************/ -/* MISC_PERST :: PCIE_DEBUG :: SERDES_TERM_CNT [31:16] */ -#define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_MASK 0xffff0000 -#define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_ALIGN 0 -#define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_BITS 16 -#define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_SHIFT 16 - -/* MISC_PERST :: PCIE_DEBUG :: reserved0 [15:11] */ -#define MISC_PERST_PCIE_DEBUG_reserved0_MASK 0x0000f800 -#define MISC_PERST_PCIE_DEBUG_reserved0_ALIGN 0 -#define MISC_PERST_PCIE_DEBUG_reserved0_BITS 5 -#define MISC_PERST_PCIE_DEBUG_reserved0_SHIFT 11 - -/* MISC_PERST :: PCIE_DEBUG :: PLL_VCO_RESCUE [10:10] */ -#define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_MASK 0x00000400 -#define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_ALIGN 0 -#define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_BITS 1 -#define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_SHIFT 10 - -/* MISC_PERST :: PCIE_DEBUG :: PLL_PDN_OVERRIDE [09:09] */ -#define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_MASK 0x00000200 -#define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_ALIGN 0 -#define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_BITS 1 -#define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_SHIFT 9 - -/* MISC_PERST :: PCIE_DEBUG :: CORE_CLOCK_OVR [08:08] */ -#define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_MASK 0x00000100 -#define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_ALIGN 0 -#define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_BITS 1 -#define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_SHIFT 8 - -/* MISC_PERST :: PCIE_DEBUG :: reserved1 [07:04] */ -#define MISC_PERST_PCIE_DEBUG_reserved1_MASK 0x000000f0 -#define MISC_PERST_PCIE_DEBUG_reserved1_ALIGN 0 -#define MISC_PERST_PCIE_DEBUG_reserved1_BITS 4 -#define MISC_PERST_PCIE_DEBUG_reserved1_SHIFT 4 - -/* MISC_PERST :: PCIE_DEBUG :: PCIE_TMUX_SEL [03:00] */ -#define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_MASK 0x0000000f -#define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_ALIGN 0 -#define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_BITS 4 -#define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_SHIFT 0 - - -/**************************************************************************** - * MISC_PERST :: PCIE_DEBUG_STATUS - ***************************************************************************/ -/* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved0 [31:06] */ -#define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_MASK 0xffffffc0 -#define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_ALIGN 0 -#define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_BITS 26 -#define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_SHIFT 6 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: DATALINKATTN [05:05] */ -#define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_MASK 0x00000020 -#define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_ALIGN 0 -#define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_BITS 1 -#define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_SHIFT 5 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: PHYLINKATTN [04:04] */ -#define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_MASK 0x00000010 -#define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_ALIGN 0 -#define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_BITS 1 -#define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_SHIFT 4 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved1 [03:02] */ -#define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_MASK 0x0000000c -#define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_ALIGN 0 -#define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_BITS 2 -#define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_SHIFT 2 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: DATA_LINKUP [01:01] */ -#define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_MASK 0x00000002 -#define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_ALIGN 0 -#define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_BITS 1 -#define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_SHIFT 1 - -/* MISC_PERST :: PCIE_DEBUG_STATUS :: PHY_LINKUP [00:00] */ -#define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_MASK 0x00000001 -#define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_ALIGN 0 -#define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_BITS 1 -#define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_SHIFT 0 - - -/**************************************************************************** - * MISC_PERST :: VREG_CTRL - ***************************************************************************/ -/* MISC_PERST :: VREG_CTRL :: reserved0 [31:08] */ -#define MISC_PERST_VREG_CTRL_reserved0_MASK 0xffffff00 -#define MISC_PERST_VREG_CTRL_reserved0_ALIGN 0 -#define MISC_PERST_VREG_CTRL_reserved0_BITS 24 -#define MISC_PERST_VREG_CTRL_reserved0_SHIFT 8 - -/* MISC_PERST :: VREG_CTRL :: VREG1P2_SEL [07:04] */ -#define MISC_PERST_VREG_CTRL_VREG1P2_SEL_MASK 0x000000f0 -#define MISC_PERST_VREG_CTRL_VREG1P2_SEL_ALIGN 0 -#define MISC_PERST_VREG_CTRL_VREG1P2_SEL_BITS 4 -#define MISC_PERST_VREG_CTRL_VREG1P2_SEL_SHIFT 4 - -/* MISC_PERST :: VREG_CTRL :: VREG2P5_SEL [03:00] */ -#define MISC_PERST_VREG_CTRL_VREG2P5_SEL_MASK 0x0000000f -#define MISC_PERST_VREG_CTRL_VREG2P5_SEL_ALIGN 0 -#define MISC_PERST_VREG_CTRL_VREG2P5_SEL_BITS 4 -#define MISC_PERST_VREG_CTRL_VREG2P5_SEL_SHIFT 0 - - -/**************************************************************************** - * MISC_PERST :: MEM_CTRL - ***************************************************************************/ -/* MISC_PERST :: MEM_CTRL :: reserved0 [31:04] */ -#define MISC_PERST_MEM_CTRL_reserved0_MASK 0xfffffff0 -#define MISC_PERST_MEM_CTRL_reserved0_ALIGN 0 -#define MISC_PERST_MEM_CTRL_reserved0_BITS 28 -#define MISC_PERST_MEM_CTRL_reserved0_SHIFT 4 - -/* MISC_PERST :: MEM_CTRL :: Y_RM [03:03] */ -#define MISC_PERST_MEM_CTRL_Y_RM_MASK 0x00000008 -#define MISC_PERST_MEM_CTRL_Y_RM_ALIGN 0 -#define MISC_PERST_MEM_CTRL_Y_RM_BITS 1 -#define MISC_PERST_MEM_CTRL_Y_RM_SHIFT 3 - -/* MISC_PERST :: MEM_CTRL :: Y_CCM [02:02] */ -#define MISC_PERST_MEM_CTRL_Y_CCM_MASK 0x00000004 -#define MISC_PERST_MEM_CTRL_Y_CCM_ALIGN 0 -#define MISC_PERST_MEM_CTRL_Y_CCM_BITS 1 -#define MISC_PERST_MEM_CTRL_Y_CCM_SHIFT 2 - -/* MISC_PERST :: MEM_CTRL :: UV_RM [01:01] */ -#define MISC_PERST_MEM_CTRL_UV_RM_MASK 0x00000002 -#define MISC_PERST_MEM_CTRL_UV_RM_ALIGN 0 -#define MISC_PERST_MEM_CTRL_UV_RM_BITS 1 -#define MISC_PERST_MEM_CTRL_UV_RM_SHIFT 1 - -/* MISC_PERST :: MEM_CTRL :: UV_CCM [00:00] */ -#define MISC_PERST_MEM_CTRL_UV_CCM_MASK 0x00000001 -#define MISC_PERST_MEM_CTRL_UV_CCM_ALIGN 0 -#define MISC_PERST_MEM_CTRL_UV_CCM_BITS 1 -#define MISC_PERST_MEM_CTRL_UV_CCM_SHIFT 0 - - -/**************************************************************************** - * MISC_PERST :: CLOCK_CTRL - ***************************************************************************/ -/* MISC_PERST :: CLOCK_CTRL :: reserved0 [31:20] */ -#define MISC_PERST_CLOCK_CTRL_reserved0_MASK 0xfff00000 -#define MISC_PERST_CLOCK_CTRL_reserved0_ALIGN 0 -#define MISC_PERST_CLOCK_CTRL_reserved0_BITS 12 -#define MISC_PERST_CLOCK_CTRL_reserved0_SHIFT 20 - -/* MISC_PERST :: CLOCK_CTRL :: PLL_DIV [19:16] */ -#define MISC_PERST_CLOCK_CTRL_PLL_DIV_MASK 0x000f0000 -#define MISC_PERST_CLOCK_CTRL_PLL_DIV_ALIGN 0 -#define MISC_PERST_CLOCK_CTRL_PLL_DIV_BITS 4 -#define MISC_PERST_CLOCK_CTRL_PLL_DIV_SHIFT 16 - -/* MISC_PERST :: CLOCK_CTRL :: PLL_MULT [15:08] */ -#define MISC_PERST_CLOCK_CTRL_PLL_MULT_MASK 0x0000ff00 -#define MISC_PERST_CLOCK_CTRL_PLL_MULT_ALIGN 0 -#define MISC_PERST_CLOCK_CTRL_PLL_MULT_BITS 8 -#define MISC_PERST_CLOCK_CTRL_PLL_MULT_SHIFT 8 - -/* MISC_PERST :: CLOCK_CTRL :: reserved1 [07:03] */ -#define MISC_PERST_CLOCK_CTRL_reserved1_MASK 0x000000f8 -#define MISC_PERST_CLOCK_CTRL_reserved1_ALIGN 0 -#define MISC_PERST_CLOCK_CTRL_reserved1_BITS 5 -#define MISC_PERST_CLOCK_CTRL_reserved1_SHIFT 3 - -/* MISC_PERST :: CLOCK_CTRL :: PLL_PWRDOWN [02:02] */ -#define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_MASK 0x00000004 -#define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_ALIGN 0 -#define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_BITS 1 -#define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_SHIFT 2 - -/* MISC_PERST :: CLOCK_CTRL :: STOP_CORE_CLK [01:01] */ -#define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_MASK 0x00000002 -#define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_ALIGN 0 -#define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_BITS 1 -#define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_SHIFT 1 - -/* MISC_PERST :: CLOCK_CTRL :: SEL_ALT_CLK [00:00] */ -#define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_MASK 0x00000001 -#define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_ALIGN 0 -#define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_BITS 1 -#define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_SHIFT 0 - - -/**************************************************************************** - * BCM70012_MISC_TOP_GISB_ARBITER - ***************************************************************************/ -/**************************************************************************** - * GISB_ARBITER :: REVISION - ***************************************************************************/ -/* GISB_ARBITER :: REVISION :: reserved0 [31:16] */ -#define GISB_ARBITER_REVISION_reserved0_MASK 0xffff0000 -#define GISB_ARBITER_REVISION_reserved0_ALIGN 0 -#define GISB_ARBITER_REVISION_reserved0_BITS 16 -#define GISB_ARBITER_REVISION_reserved0_SHIFT 16 - -/* GISB_ARBITER :: REVISION :: MAJOR [15:08] */ -#define GISB_ARBITER_REVISION_MAJOR_MASK 0x0000ff00 -#define GISB_ARBITER_REVISION_MAJOR_ALIGN 0 -#define GISB_ARBITER_REVISION_MAJOR_BITS 8 -#define GISB_ARBITER_REVISION_MAJOR_SHIFT 8 - -/* GISB_ARBITER :: REVISION :: MINOR [07:00] */ -#define GISB_ARBITER_REVISION_MINOR_MASK 0x000000ff -#define GISB_ARBITER_REVISION_MINOR_ALIGN 0 -#define GISB_ARBITER_REVISION_MINOR_BITS 8 -#define GISB_ARBITER_REVISION_MINOR_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: SCRATCH - ***************************************************************************/ -/* GISB_ARBITER :: SCRATCH :: scratch_bit [31:00] */ -#define GISB_ARBITER_SCRATCH_scratch_bit_MASK 0xffffffff -#define GISB_ARBITER_SCRATCH_scratch_bit_ALIGN 0 -#define GISB_ARBITER_SCRATCH_scratch_bit_BITS 32 -#define GISB_ARBITER_SCRATCH_scratch_bit_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: REQ_MASK - ***************************************************************************/ -/* GISB_ARBITER :: REQ_MASK :: reserved0 [31:06] */ -#define GISB_ARBITER_REQ_MASK_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_REQ_MASK_reserved0_ALIGN 0 -#define GISB_ARBITER_REQ_MASK_reserved0_BITS 26 -#define GISB_ARBITER_REQ_MASK_reserved0_SHIFT 6 - -/* GISB_ARBITER :: REQ_MASK :: bsp [05:05] */ -#define GISB_ARBITER_REQ_MASK_bsp_MASK 0x00000020 -#define GISB_ARBITER_REQ_MASK_bsp_ALIGN 0 -#define GISB_ARBITER_REQ_MASK_bsp_BITS 1 -#define GISB_ARBITER_REQ_MASK_bsp_SHIFT 5 -#define GISB_ARBITER_REQ_MASK_bsp_UNMASK 0 - -/* GISB_ARBITER :: REQ_MASK :: tgt [04:04] */ -#define GISB_ARBITER_REQ_MASK_tgt_MASK 0x00000010 -#define GISB_ARBITER_REQ_MASK_tgt_ALIGN 0 -#define GISB_ARBITER_REQ_MASK_tgt_BITS 1 -#define GISB_ARBITER_REQ_MASK_tgt_SHIFT 4 -#define GISB_ARBITER_REQ_MASK_tgt_UNMASK 0 - -/* GISB_ARBITER :: REQ_MASK :: aes [03:03] */ -#define GISB_ARBITER_REQ_MASK_aes_MASK 0x00000008 -#define GISB_ARBITER_REQ_MASK_aes_ALIGN 0 -#define GISB_ARBITER_REQ_MASK_aes_BITS 1 -#define GISB_ARBITER_REQ_MASK_aes_SHIFT 3 -#define GISB_ARBITER_REQ_MASK_aes_UNMASK 0 - -/* GISB_ARBITER :: REQ_MASK :: dci [02:02] */ -#define GISB_ARBITER_REQ_MASK_dci_MASK 0x00000004 -#define GISB_ARBITER_REQ_MASK_dci_ALIGN 0 -#define GISB_ARBITER_REQ_MASK_dci_BITS 1 -#define GISB_ARBITER_REQ_MASK_dci_SHIFT 2 -#define GISB_ARBITER_REQ_MASK_dci_UNMASK 0 - -/* GISB_ARBITER :: REQ_MASK :: cce [01:01] */ -#define GISB_ARBITER_REQ_MASK_cce_MASK 0x00000002 -#define GISB_ARBITER_REQ_MASK_cce_ALIGN 0 -#define GISB_ARBITER_REQ_MASK_cce_BITS 1 -#define GISB_ARBITER_REQ_MASK_cce_SHIFT 1 -#define GISB_ARBITER_REQ_MASK_cce_UNMASK 0 - -/* GISB_ARBITER :: REQ_MASK :: dbu [00:00] */ -#define GISB_ARBITER_REQ_MASK_dbu_MASK 0x00000001 -#define GISB_ARBITER_REQ_MASK_dbu_ALIGN 0 -#define GISB_ARBITER_REQ_MASK_dbu_BITS 1 -#define GISB_ARBITER_REQ_MASK_dbu_SHIFT 0 -#define GISB_ARBITER_REQ_MASK_dbu_UNMASK 0 - - -/**************************************************************************** - * GISB_ARBITER :: TIMER - ***************************************************************************/ -/* GISB_ARBITER :: TIMER :: hi_count [31:16] */ -#define GISB_ARBITER_TIMER_hi_count_MASK 0xffff0000 -#define GISB_ARBITER_TIMER_hi_count_ALIGN 0 -#define GISB_ARBITER_TIMER_hi_count_BITS 16 -#define GISB_ARBITER_TIMER_hi_count_SHIFT 16 - -/* GISB_ARBITER :: TIMER :: lo_count [15:00] */ -#define GISB_ARBITER_TIMER_lo_count_MASK 0x0000ffff -#define GISB_ARBITER_TIMER_lo_count_ALIGN 0 -#define GISB_ARBITER_TIMER_lo_count_BITS 16 -#define GISB_ARBITER_TIMER_lo_count_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_CTRL - ***************************************************************************/ -/* GISB_ARBITER :: BP_CTRL :: reserved0 [31:02] */ -#define GISB_ARBITER_BP_CTRL_reserved0_MASK 0xfffffffc -#define GISB_ARBITER_BP_CTRL_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_CTRL_reserved0_BITS 30 -#define GISB_ARBITER_BP_CTRL_reserved0_SHIFT 2 - -/* GISB_ARBITER :: BP_CTRL :: breakpoint_tea [01:01] */ -#define GISB_ARBITER_BP_CTRL_breakpoint_tea_MASK 0x00000002 -#define GISB_ARBITER_BP_CTRL_breakpoint_tea_ALIGN 0 -#define GISB_ARBITER_BP_CTRL_breakpoint_tea_BITS 1 -#define GISB_ARBITER_BP_CTRL_breakpoint_tea_SHIFT 1 -#define GISB_ARBITER_BP_CTRL_breakpoint_tea_DISABLE 0 -#define GISB_ARBITER_BP_CTRL_breakpoint_tea_ENABLE 1 - -/* GISB_ARBITER :: BP_CTRL :: repeat_capture [00:00] */ -#define GISB_ARBITER_BP_CTRL_repeat_capture_MASK 0x00000001 -#define GISB_ARBITER_BP_CTRL_repeat_capture_ALIGN 0 -#define GISB_ARBITER_BP_CTRL_repeat_capture_BITS 1 -#define GISB_ARBITER_BP_CTRL_repeat_capture_SHIFT 0 -#define GISB_ARBITER_BP_CTRL_repeat_capture_DISABLE 0 -#define GISB_ARBITER_BP_CTRL_repeat_capture_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_CAP_CLR - ***************************************************************************/ -/* GISB_ARBITER :: BP_CAP_CLR :: reserved0 [31:01] */ -#define GISB_ARBITER_BP_CAP_CLR_reserved0_MASK 0xfffffffe -#define GISB_ARBITER_BP_CAP_CLR_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_CAP_CLR_reserved0_BITS 31 -#define GISB_ARBITER_BP_CAP_CLR_reserved0_SHIFT 1 - -/* GISB_ARBITER :: BP_CAP_CLR :: clear [00:00] */ -#define GISB_ARBITER_BP_CAP_CLR_clear_MASK 0x00000001 -#define GISB_ARBITER_BP_CAP_CLR_clear_ALIGN 0 -#define GISB_ARBITER_BP_CAP_CLR_clear_BITS 1 -#define GISB_ARBITER_BP_CAP_CLR_clear_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_START_ADDR_0 - ***************************************************************************/ -/* GISB_ARBITER :: BP_START_ADDR_0 :: start [31:00] */ -#define GISB_ARBITER_BP_START_ADDR_0_start_MASK 0xffffffff -#define GISB_ARBITER_BP_START_ADDR_0_start_ALIGN 0 -#define GISB_ARBITER_BP_START_ADDR_0_start_BITS 32 -#define GISB_ARBITER_BP_START_ADDR_0_start_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_END_ADDR_0 - ***************************************************************************/ -/* GISB_ARBITER :: BP_END_ADDR_0 :: end [31:00] */ -#define GISB_ARBITER_BP_END_ADDR_0_end_MASK 0xffffffff -#define GISB_ARBITER_BP_END_ADDR_0_end_ALIGN 0 -#define GISB_ARBITER_BP_END_ADDR_0_end_BITS 32 -#define GISB_ARBITER_BP_END_ADDR_0_end_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_READ_0 - ***************************************************************************/ -/* GISB_ARBITER :: BP_READ_0 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_READ_0_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_READ_0_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_READ_0_reserved0_BITS 26 -#define GISB_ARBITER_BP_READ_0_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_READ_0 :: bsp [05:05] */ -#define GISB_ARBITER_BP_READ_0_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_READ_0_bsp_ALIGN 0 -#define GISB_ARBITER_BP_READ_0_bsp_BITS 1 -#define GISB_ARBITER_BP_READ_0_bsp_SHIFT 5 -#define GISB_ARBITER_BP_READ_0_bsp_DISABLE 0 -#define GISB_ARBITER_BP_READ_0_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_0 :: aes [04:04] */ -#define GISB_ARBITER_BP_READ_0_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_READ_0_aes_ALIGN 0 -#define GISB_ARBITER_BP_READ_0_aes_BITS 1 -#define GISB_ARBITER_BP_READ_0_aes_SHIFT 4 -#define GISB_ARBITER_BP_READ_0_aes_DISABLE 0 -#define GISB_ARBITER_BP_READ_0_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_0 :: fve [03:03] */ -#define GISB_ARBITER_BP_READ_0_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_READ_0_fve_ALIGN 0 -#define GISB_ARBITER_BP_READ_0_fve_BITS 1 -#define GISB_ARBITER_BP_READ_0_fve_SHIFT 3 -#define GISB_ARBITER_BP_READ_0_fve_DISABLE 0 -#define GISB_ARBITER_BP_READ_0_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_0 :: tgt [02:02] */ -#define GISB_ARBITER_BP_READ_0_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_READ_0_tgt_ALIGN 0 -#define GISB_ARBITER_BP_READ_0_tgt_BITS 1 -#define GISB_ARBITER_BP_READ_0_tgt_SHIFT 2 -#define GISB_ARBITER_BP_READ_0_tgt_DISABLE 0 -#define GISB_ARBITER_BP_READ_0_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_0 :: dbu [01:01] */ -#define GISB_ARBITER_BP_READ_0_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_READ_0_dbu_ALIGN 0 -#define GISB_ARBITER_BP_READ_0_dbu_BITS 1 -#define GISB_ARBITER_BP_READ_0_dbu_SHIFT 1 -#define GISB_ARBITER_BP_READ_0_dbu_DISABLE 0 -#define GISB_ARBITER_BP_READ_0_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_0 :: cce [00:00] */ -#define GISB_ARBITER_BP_READ_0_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_READ_0_cce_ALIGN 0 -#define GISB_ARBITER_BP_READ_0_cce_BITS 1 -#define GISB_ARBITER_BP_READ_0_cce_SHIFT 0 -#define GISB_ARBITER_BP_READ_0_cce_DISABLE 0 -#define GISB_ARBITER_BP_READ_0_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_WRITE_0 - ***************************************************************************/ -/* GISB_ARBITER :: BP_WRITE_0 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_WRITE_0_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_WRITE_0_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_0_reserved0_BITS 26 -#define GISB_ARBITER_BP_WRITE_0_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_WRITE_0 :: bsp [05:05] */ -#define GISB_ARBITER_BP_WRITE_0_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_WRITE_0_bsp_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_0_bsp_BITS 1 -#define GISB_ARBITER_BP_WRITE_0_bsp_SHIFT 5 -#define GISB_ARBITER_BP_WRITE_0_bsp_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_0_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_0 :: aes [04:04] */ -#define GISB_ARBITER_BP_WRITE_0_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_WRITE_0_aes_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_0_aes_BITS 1 -#define GISB_ARBITER_BP_WRITE_0_aes_SHIFT 4 -#define GISB_ARBITER_BP_WRITE_0_aes_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_0_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_0 :: fve [03:03] */ -#define GISB_ARBITER_BP_WRITE_0_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_WRITE_0_fve_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_0_fve_BITS 1 -#define GISB_ARBITER_BP_WRITE_0_fve_SHIFT 3 -#define GISB_ARBITER_BP_WRITE_0_fve_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_0_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_0 :: tgt [02:02] */ -#define GISB_ARBITER_BP_WRITE_0_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_WRITE_0_tgt_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_0_tgt_BITS 1 -#define GISB_ARBITER_BP_WRITE_0_tgt_SHIFT 2 -#define GISB_ARBITER_BP_WRITE_0_tgt_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_0_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_0 :: dbu [01:01] */ -#define GISB_ARBITER_BP_WRITE_0_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_WRITE_0_dbu_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_0_dbu_BITS 1 -#define GISB_ARBITER_BP_WRITE_0_dbu_SHIFT 1 -#define GISB_ARBITER_BP_WRITE_0_dbu_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_0_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_0 :: cce [00:00] */ -#define GISB_ARBITER_BP_WRITE_0_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_WRITE_0_cce_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_0_cce_BITS 1 -#define GISB_ARBITER_BP_WRITE_0_cce_SHIFT 0 -#define GISB_ARBITER_BP_WRITE_0_cce_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_0_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_ENABLE_0 - ***************************************************************************/ -/* GISB_ARBITER :: BP_ENABLE_0 :: reserved0 [31:03] */ -#define GISB_ARBITER_BP_ENABLE_0_reserved0_MASK 0xfffffff8 -#define GISB_ARBITER_BP_ENABLE_0_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_0_reserved0_BITS 29 -#define GISB_ARBITER_BP_ENABLE_0_reserved0_SHIFT 3 - -/* GISB_ARBITER :: BP_ENABLE_0 :: block [02:02] */ -#define GISB_ARBITER_BP_ENABLE_0_block_MASK 0x00000004 -#define GISB_ARBITER_BP_ENABLE_0_block_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_0_block_BITS 1 -#define GISB_ARBITER_BP_ENABLE_0_block_SHIFT 2 -#define GISB_ARBITER_BP_ENABLE_0_block_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_0_block_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_0 :: address [01:01] */ -#define GISB_ARBITER_BP_ENABLE_0_address_MASK 0x00000002 -#define GISB_ARBITER_BP_ENABLE_0_address_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_0_address_BITS 1 -#define GISB_ARBITER_BP_ENABLE_0_address_SHIFT 1 -#define GISB_ARBITER_BP_ENABLE_0_address_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_0_address_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_0 :: access [00:00] */ -#define GISB_ARBITER_BP_ENABLE_0_access_MASK 0x00000001 -#define GISB_ARBITER_BP_ENABLE_0_access_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_0_access_BITS 1 -#define GISB_ARBITER_BP_ENABLE_0_access_SHIFT 0 -#define GISB_ARBITER_BP_ENABLE_0_access_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_0_access_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_START_ADDR_1 - ***************************************************************************/ -/* GISB_ARBITER :: BP_START_ADDR_1 :: start [31:00] */ -#define GISB_ARBITER_BP_START_ADDR_1_start_MASK 0xffffffff -#define GISB_ARBITER_BP_START_ADDR_1_start_ALIGN 0 -#define GISB_ARBITER_BP_START_ADDR_1_start_BITS 32 -#define GISB_ARBITER_BP_START_ADDR_1_start_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_END_ADDR_1 - ***************************************************************************/ -/* GISB_ARBITER :: BP_END_ADDR_1 :: end [31:00] */ -#define GISB_ARBITER_BP_END_ADDR_1_end_MASK 0xffffffff -#define GISB_ARBITER_BP_END_ADDR_1_end_ALIGN 0 -#define GISB_ARBITER_BP_END_ADDR_1_end_BITS 32 -#define GISB_ARBITER_BP_END_ADDR_1_end_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_READ_1 - ***************************************************************************/ -/* GISB_ARBITER :: BP_READ_1 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_READ_1_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_READ_1_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_READ_1_reserved0_BITS 26 -#define GISB_ARBITER_BP_READ_1_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_READ_1 :: bsp [05:05] */ -#define GISB_ARBITER_BP_READ_1_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_READ_1_bsp_ALIGN 0 -#define GISB_ARBITER_BP_READ_1_bsp_BITS 1 -#define GISB_ARBITER_BP_READ_1_bsp_SHIFT 5 -#define GISB_ARBITER_BP_READ_1_bsp_DISABLE 0 -#define GISB_ARBITER_BP_READ_1_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_1 :: aes [04:04] */ -#define GISB_ARBITER_BP_READ_1_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_READ_1_aes_ALIGN 0 -#define GISB_ARBITER_BP_READ_1_aes_BITS 1 -#define GISB_ARBITER_BP_READ_1_aes_SHIFT 4 -#define GISB_ARBITER_BP_READ_1_aes_DISABLE 0 -#define GISB_ARBITER_BP_READ_1_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_1 :: fve [03:03] */ -#define GISB_ARBITER_BP_READ_1_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_READ_1_fve_ALIGN 0 -#define GISB_ARBITER_BP_READ_1_fve_BITS 1 -#define GISB_ARBITER_BP_READ_1_fve_SHIFT 3 -#define GISB_ARBITER_BP_READ_1_fve_DISABLE 0 -#define GISB_ARBITER_BP_READ_1_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_1 :: tgt [02:02] */ -#define GISB_ARBITER_BP_READ_1_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_READ_1_tgt_ALIGN 0 -#define GISB_ARBITER_BP_READ_1_tgt_BITS 1 -#define GISB_ARBITER_BP_READ_1_tgt_SHIFT 2 -#define GISB_ARBITER_BP_READ_1_tgt_DISABLE 0 -#define GISB_ARBITER_BP_READ_1_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_1 :: dbu [01:01] */ -#define GISB_ARBITER_BP_READ_1_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_READ_1_dbu_ALIGN 0 -#define GISB_ARBITER_BP_READ_1_dbu_BITS 1 -#define GISB_ARBITER_BP_READ_1_dbu_SHIFT 1 -#define GISB_ARBITER_BP_READ_1_dbu_DISABLE 0 -#define GISB_ARBITER_BP_READ_1_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_1 :: cce [00:00] */ -#define GISB_ARBITER_BP_READ_1_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_READ_1_cce_ALIGN 0 -#define GISB_ARBITER_BP_READ_1_cce_BITS 1 -#define GISB_ARBITER_BP_READ_1_cce_SHIFT 0 -#define GISB_ARBITER_BP_READ_1_cce_DISABLE 0 -#define GISB_ARBITER_BP_READ_1_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_WRITE_1 - ***************************************************************************/ -/* GISB_ARBITER :: BP_WRITE_1 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_WRITE_1_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_WRITE_1_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_1_reserved0_BITS 26 -#define GISB_ARBITER_BP_WRITE_1_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_WRITE_1 :: bsp [05:05] */ -#define GISB_ARBITER_BP_WRITE_1_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_WRITE_1_bsp_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_1_bsp_BITS 1 -#define GISB_ARBITER_BP_WRITE_1_bsp_SHIFT 5 -#define GISB_ARBITER_BP_WRITE_1_bsp_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_1_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_1 :: aes [04:04] */ -#define GISB_ARBITER_BP_WRITE_1_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_WRITE_1_aes_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_1_aes_BITS 1 -#define GISB_ARBITER_BP_WRITE_1_aes_SHIFT 4 -#define GISB_ARBITER_BP_WRITE_1_aes_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_1_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_1 :: fve [03:03] */ -#define GISB_ARBITER_BP_WRITE_1_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_WRITE_1_fve_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_1_fve_BITS 1 -#define GISB_ARBITER_BP_WRITE_1_fve_SHIFT 3 -#define GISB_ARBITER_BP_WRITE_1_fve_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_1_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_1 :: tgt [02:02] */ -#define GISB_ARBITER_BP_WRITE_1_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_WRITE_1_tgt_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_1_tgt_BITS 1 -#define GISB_ARBITER_BP_WRITE_1_tgt_SHIFT 2 -#define GISB_ARBITER_BP_WRITE_1_tgt_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_1_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_1 :: dbu [01:01] */ -#define GISB_ARBITER_BP_WRITE_1_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_WRITE_1_dbu_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_1_dbu_BITS 1 -#define GISB_ARBITER_BP_WRITE_1_dbu_SHIFT 1 -#define GISB_ARBITER_BP_WRITE_1_dbu_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_1_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_1 :: cce [00:00] */ -#define GISB_ARBITER_BP_WRITE_1_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_WRITE_1_cce_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_1_cce_BITS 1 -#define GISB_ARBITER_BP_WRITE_1_cce_SHIFT 0 -#define GISB_ARBITER_BP_WRITE_1_cce_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_1_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_ENABLE_1 - ***************************************************************************/ -/* GISB_ARBITER :: BP_ENABLE_1 :: reserved0 [31:03] */ -#define GISB_ARBITER_BP_ENABLE_1_reserved0_MASK 0xfffffff8 -#define GISB_ARBITER_BP_ENABLE_1_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_1_reserved0_BITS 29 -#define GISB_ARBITER_BP_ENABLE_1_reserved0_SHIFT 3 - -/* GISB_ARBITER :: BP_ENABLE_1 :: block [02:02] */ -#define GISB_ARBITER_BP_ENABLE_1_block_MASK 0x00000004 -#define GISB_ARBITER_BP_ENABLE_1_block_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_1_block_BITS 1 -#define GISB_ARBITER_BP_ENABLE_1_block_SHIFT 2 -#define GISB_ARBITER_BP_ENABLE_1_block_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_1_block_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_1 :: address [01:01] */ -#define GISB_ARBITER_BP_ENABLE_1_address_MASK 0x00000002 -#define GISB_ARBITER_BP_ENABLE_1_address_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_1_address_BITS 1 -#define GISB_ARBITER_BP_ENABLE_1_address_SHIFT 1 -#define GISB_ARBITER_BP_ENABLE_1_address_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_1_address_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_1 :: access [00:00] */ -#define GISB_ARBITER_BP_ENABLE_1_access_MASK 0x00000001 -#define GISB_ARBITER_BP_ENABLE_1_access_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_1_access_BITS 1 -#define GISB_ARBITER_BP_ENABLE_1_access_SHIFT 0 -#define GISB_ARBITER_BP_ENABLE_1_access_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_1_access_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_START_ADDR_2 - ***************************************************************************/ -/* GISB_ARBITER :: BP_START_ADDR_2 :: start [31:00] */ -#define GISB_ARBITER_BP_START_ADDR_2_start_MASK 0xffffffff -#define GISB_ARBITER_BP_START_ADDR_2_start_ALIGN 0 -#define GISB_ARBITER_BP_START_ADDR_2_start_BITS 32 -#define GISB_ARBITER_BP_START_ADDR_2_start_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_END_ADDR_2 - ***************************************************************************/ -/* GISB_ARBITER :: BP_END_ADDR_2 :: end [31:00] */ -#define GISB_ARBITER_BP_END_ADDR_2_end_MASK 0xffffffff -#define GISB_ARBITER_BP_END_ADDR_2_end_ALIGN 0 -#define GISB_ARBITER_BP_END_ADDR_2_end_BITS 32 -#define GISB_ARBITER_BP_END_ADDR_2_end_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_READ_2 - ***************************************************************************/ -/* GISB_ARBITER :: BP_READ_2 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_READ_2_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_READ_2_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_READ_2_reserved0_BITS 26 -#define GISB_ARBITER_BP_READ_2_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_READ_2 :: bsp [05:05] */ -#define GISB_ARBITER_BP_READ_2_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_READ_2_bsp_ALIGN 0 -#define GISB_ARBITER_BP_READ_2_bsp_BITS 1 -#define GISB_ARBITER_BP_READ_2_bsp_SHIFT 5 -#define GISB_ARBITER_BP_READ_2_bsp_DISABLE 0 -#define GISB_ARBITER_BP_READ_2_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_2 :: aes [04:04] */ -#define GISB_ARBITER_BP_READ_2_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_READ_2_aes_ALIGN 0 -#define GISB_ARBITER_BP_READ_2_aes_BITS 1 -#define GISB_ARBITER_BP_READ_2_aes_SHIFT 4 -#define GISB_ARBITER_BP_READ_2_aes_DISABLE 0 -#define GISB_ARBITER_BP_READ_2_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_2 :: fve [03:03] */ -#define GISB_ARBITER_BP_READ_2_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_READ_2_fve_ALIGN 0 -#define GISB_ARBITER_BP_READ_2_fve_BITS 1 -#define GISB_ARBITER_BP_READ_2_fve_SHIFT 3 -#define GISB_ARBITER_BP_READ_2_fve_DISABLE 0 -#define GISB_ARBITER_BP_READ_2_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_2 :: tgt [02:02] */ -#define GISB_ARBITER_BP_READ_2_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_READ_2_tgt_ALIGN 0 -#define GISB_ARBITER_BP_READ_2_tgt_BITS 1 -#define GISB_ARBITER_BP_READ_2_tgt_SHIFT 2 -#define GISB_ARBITER_BP_READ_2_tgt_DISABLE 0 -#define GISB_ARBITER_BP_READ_2_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_2 :: dbu [01:01] */ -#define GISB_ARBITER_BP_READ_2_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_READ_2_dbu_ALIGN 0 -#define GISB_ARBITER_BP_READ_2_dbu_BITS 1 -#define GISB_ARBITER_BP_READ_2_dbu_SHIFT 1 -#define GISB_ARBITER_BP_READ_2_dbu_DISABLE 0 -#define GISB_ARBITER_BP_READ_2_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_2 :: cce [00:00] */ -#define GISB_ARBITER_BP_READ_2_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_READ_2_cce_ALIGN 0 -#define GISB_ARBITER_BP_READ_2_cce_BITS 1 -#define GISB_ARBITER_BP_READ_2_cce_SHIFT 0 -#define GISB_ARBITER_BP_READ_2_cce_DISABLE 0 -#define GISB_ARBITER_BP_READ_2_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_WRITE_2 - ***************************************************************************/ -/* GISB_ARBITER :: BP_WRITE_2 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_WRITE_2_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_WRITE_2_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_2_reserved0_BITS 26 -#define GISB_ARBITER_BP_WRITE_2_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_WRITE_2 :: bsp [05:05] */ -#define GISB_ARBITER_BP_WRITE_2_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_WRITE_2_bsp_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_2_bsp_BITS 1 -#define GISB_ARBITER_BP_WRITE_2_bsp_SHIFT 5 -#define GISB_ARBITER_BP_WRITE_2_bsp_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_2_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_2 :: aes [04:04] */ -#define GISB_ARBITER_BP_WRITE_2_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_WRITE_2_aes_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_2_aes_BITS 1 -#define GISB_ARBITER_BP_WRITE_2_aes_SHIFT 4 -#define GISB_ARBITER_BP_WRITE_2_aes_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_2_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_2 :: fve [03:03] */ -#define GISB_ARBITER_BP_WRITE_2_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_WRITE_2_fve_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_2_fve_BITS 1 -#define GISB_ARBITER_BP_WRITE_2_fve_SHIFT 3 -#define GISB_ARBITER_BP_WRITE_2_fve_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_2_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_2 :: tgt [02:02] */ -#define GISB_ARBITER_BP_WRITE_2_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_WRITE_2_tgt_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_2_tgt_BITS 1 -#define GISB_ARBITER_BP_WRITE_2_tgt_SHIFT 2 -#define GISB_ARBITER_BP_WRITE_2_tgt_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_2_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_2 :: dbu [01:01] */ -#define GISB_ARBITER_BP_WRITE_2_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_WRITE_2_dbu_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_2_dbu_BITS 1 -#define GISB_ARBITER_BP_WRITE_2_dbu_SHIFT 1 -#define GISB_ARBITER_BP_WRITE_2_dbu_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_2_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_2 :: cce [00:00] */ -#define GISB_ARBITER_BP_WRITE_2_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_WRITE_2_cce_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_2_cce_BITS 1 -#define GISB_ARBITER_BP_WRITE_2_cce_SHIFT 0 -#define GISB_ARBITER_BP_WRITE_2_cce_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_2_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_ENABLE_2 - ***************************************************************************/ -/* GISB_ARBITER :: BP_ENABLE_2 :: reserved0 [31:03] */ -#define GISB_ARBITER_BP_ENABLE_2_reserved0_MASK 0xfffffff8 -#define GISB_ARBITER_BP_ENABLE_2_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_2_reserved0_BITS 29 -#define GISB_ARBITER_BP_ENABLE_2_reserved0_SHIFT 3 - -/* GISB_ARBITER :: BP_ENABLE_2 :: block [02:02] */ -#define GISB_ARBITER_BP_ENABLE_2_block_MASK 0x00000004 -#define GISB_ARBITER_BP_ENABLE_2_block_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_2_block_BITS 1 -#define GISB_ARBITER_BP_ENABLE_2_block_SHIFT 2 -#define GISB_ARBITER_BP_ENABLE_2_block_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_2_block_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_2 :: address [01:01] */ -#define GISB_ARBITER_BP_ENABLE_2_address_MASK 0x00000002 -#define GISB_ARBITER_BP_ENABLE_2_address_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_2_address_BITS 1 -#define GISB_ARBITER_BP_ENABLE_2_address_SHIFT 1 -#define GISB_ARBITER_BP_ENABLE_2_address_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_2_address_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_2 :: access [00:00] */ -#define GISB_ARBITER_BP_ENABLE_2_access_MASK 0x00000001 -#define GISB_ARBITER_BP_ENABLE_2_access_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_2_access_BITS 1 -#define GISB_ARBITER_BP_ENABLE_2_access_SHIFT 0 -#define GISB_ARBITER_BP_ENABLE_2_access_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_2_access_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_START_ADDR_3 - ***************************************************************************/ -/* GISB_ARBITER :: BP_START_ADDR_3 :: start [31:00] */ -#define GISB_ARBITER_BP_START_ADDR_3_start_MASK 0xffffffff -#define GISB_ARBITER_BP_START_ADDR_3_start_ALIGN 0 -#define GISB_ARBITER_BP_START_ADDR_3_start_BITS 32 -#define GISB_ARBITER_BP_START_ADDR_3_start_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_END_ADDR_3 - ***************************************************************************/ -/* GISB_ARBITER :: BP_END_ADDR_3 :: end [31:00] */ -#define GISB_ARBITER_BP_END_ADDR_3_end_MASK 0xffffffff -#define GISB_ARBITER_BP_END_ADDR_3_end_ALIGN 0 -#define GISB_ARBITER_BP_END_ADDR_3_end_BITS 32 -#define GISB_ARBITER_BP_END_ADDR_3_end_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_READ_3 - ***************************************************************************/ -/* GISB_ARBITER :: BP_READ_3 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_READ_3_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_READ_3_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_READ_3_reserved0_BITS 26 -#define GISB_ARBITER_BP_READ_3_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_READ_3 :: bsp [05:05] */ -#define GISB_ARBITER_BP_READ_3_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_READ_3_bsp_ALIGN 0 -#define GISB_ARBITER_BP_READ_3_bsp_BITS 1 -#define GISB_ARBITER_BP_READ_3_bsp_SHIFT 5 -#define GISB_ARBITER_BP_READ_3_bsp_DISABLE 0 -#define GISB_ARBITER_BP_READ_3_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_3 :: aes [04:04] */ -#define GISB_ARBITER_BP_READ_3_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_READ_3_aes_ALIGN 0 -#define GISB_ARBITER_BP_READ_3_aes_BITS 1 -#define GISB_ARBITER_BP_READ_3_aes_SHIFT 4 -#define GISB_ARBITER_BP_READ_3_aes_DISABLE 0 -#define GISB_ARBITER_BP_READ_3_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_3 :: fve [03:03] */ -#define GISB_ARBITER_BP_READ_3_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_READ_3_fve_ALIGN 0 -#define GISB_ARBITER_BP_READ_3_fve_BITS 1 -#define GISB_ARBITER_BP_READ_3_fve_SHIFT 3 -#define GISB_ARBITER_BP_READ_3_fve_DISABLE 0 -#define GISB_ARBITER_BP_READ_3_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_3 :: tgt [02:02] */ -#define GISB_ARBITER_BP_READ_3_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_READ_3_tgt_ALIGN 0 -#define GISB_ARBITER_BP_READ_3_tgt_BITS 1 -#define GISB_ARBITER_BP_READ_3_tgt_SHIFT 2 -#define GISB_ARBITER_BP_READ_3_tgt_DISABLE 0 -#define GISB_ARBITER_BP_READ_3_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_3 :: dbu [01:01] */ -#define GISB_ARBITER_BP_READ_3_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_READ_3_dbu_ALIGN 0 -#define GISB_ARBITER_BP_READ_3_dbu_BITS 1 -#define GISB_ARBITER_BP_READ_3_dbu_SHIFT 1 -#define GISB_ARBITER_BP_READ_3_dbu_DISABLE 0 -#define GISB_ARBITER_BP_READ_3_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_3 :: cce [00:00] */ -#define GISB_ARBITER_BP_READ_3_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_READ_3_cce_ALIGN 0 -#define GISB_ARBITER_BP_READ_3_cce_BITS 1 -#define GISB_ARBITER_BP_READ_3_cce_SHIFT 0 -#define GISB_ARBITER_BP_READ_3_cce_DISABLE 0 -#define GISB_ARBITER_BP_READ_3_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_WRITE_3 - ***************************************************************************/ -/* GISB_ARBITER :: BP_WRITE_3 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_WRITE_3_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_WRITE_3_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_3_reserved0_BITS 26 -#define GISB_ARBITER_BP_WRITE_3_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_WRITE_3 :: bsp [05:05] */ -#define GISB_ARBITER_BP_WRITE_3_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_WRITE_3_bsp_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_3_bsp_BITS 1 -#define GISB_ARBITER_BP_WRITE_3_bsp_SHIFT 5 -#define GISB_ARBITER_BP_WRITE_3_bsp_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_3_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_3 :: aes [04:04] */ -#define GISB_ARBITER_BP_WRITE_3_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_WRITE_3_aes_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_3_aes_BITS 1 -#define GISB_ARBITER_BP_WRITE_3_aes_SHIFT 4 -#define GISB_ARBITER_BP_WRITE_3_aes_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_3_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_3 :: fve [03:03] */ -#define GISB_ARBITER_BP_WRITE_3_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_WRITE_3_fve_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_3_fve_BITS 1 -#define GISB_ARBITER_BP_WRITE_3_fve_SHIFT 3 -#define GISB_ARBITER_BP_WRITE_3_fve_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_3_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_3 :: tgt [02:02] */ -#define GISB_ARBITER_BP_WRITE_3_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_WRITE_3_tgt_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_3_tgt_BITS 1 -#define GISB_ARBITER_BP_WRITE_3_tgt_SHIFT 2 -#define GISB_ARBITER_BP_WRITE_3_tgt_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_3_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_3 :: dbu [01:01] */ -#define GISB_ARBITER_BP_WRITE_3_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_WRITE_3_dbu_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_3_dbu_BITS 1 -#define GISB_ARBITER_BP_WRITE_3_dbu_SHIFT 1 -#define GISB_ARBITER_BP_WRITE_3_dbu_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_3_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_3 :: cce [00:00] */ -#define GISB_ARBITER_BP_WRITE_3_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_WRITE_3_cce_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_3_cce_BITS 1 -#define GISB_ARBITER_BP_WRITE_3_cce_SHIFT 0 -#define GISB_ARBITER_BP_WRITE_3_cce_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_3_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_ENABLE_3 - ***************************************************************************/ -/* GISB_ARBITER :: BP_ENABLE_3 :: reserved0 [31:03] */ -#define GISB_ARBITER_BP_ENABLE_3_reserved0_MASK 0xfffffff8 -#define GISB_ARBITER_BP_ENABLE_3_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_3_reserved0_BITS 29 -#define GISB_ARBITER_BP_ENABLE_3_reserved0_SHIFT 3 - -/* GISB_ARBITER :: BP_ENABLE_3 :: block [02:02] */ -#define GISB_ARBITER_BP_ENABLE_3_block_MASK 0x00000004 -#define GISB_ARBITER_BP_ENABLE_3_block_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_3_block_BITS 1 -#define GISB_ARBITER_BP_ENABLE_3_block_SHIFT 2 -#define GISB_ARBITER_BP_ENABLE_3_block_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_3_block_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_3 :: address [01:01] */ -#define GISB_ARBITER_BP_ENABLE_3_address_MASK 0x00000002 -#define GISB_ARBITER_BP_ENABLE_3_address_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_3_address_BITS 1 -#define GISB_ARBITER_BP_ENABLE_3_address_SHIFT 1 -#define GISB_ARBITER_BP_ENABLE_3_address_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_3_address_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_3 :: access [00:00] */ -#define GISB_ARBITER_BP_ENABLE_3_access_MASK 0x00000001 -#define GISB_ARBITER_BP_ENABLE_3_access_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_3_access_BITS 1 -#define GISB_ARBITER_BP_ENABLE_3_access_SHIFT 0 -#define GISB_ARBITER_BP_ENABLE_3_access_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_3_access_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_START_ADDR_4 - ***************************************************************************/ -/* GISB_ARBITER :: BP_START_ADDR_4 :: start [31:00] */ -#define GISB_ARBITER_BP_START_ADDR_4_start_MASK 0xffffffff -#define GISB_ARBITER_BP_START_ADDR_4_start_ALIGN 0 -#define GISB_ARBITER_BP_START_ADDR_4_start_BITS 32 -#define GISB_ARBITER_BP_START_ADDR_4_start_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_END_ADDR_4 - ***************************************************************************/ -/* GISB_ARBITER :: BP_END_ADDR_4 :: end [31:00] */ -#define GISB_ARBITER_BP_END_ADDR_4_end_MASK 0xffffffff -#define GISB_ARBITER_BP_END_ADDR_4_end_ALIGN 0 -#define GISB_ARBITER_BP_END_ADDR_4_end_BITS 32 -#define GISB_ARBITER_BP_END_ADDR_4_end_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_READ_4 - ***************************************************************************/ -/* GISB_ARBITER :: BP_READ_4 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_READ_4_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_READ_4_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_READ_4_reserved0_BITS 26 -#define GISB_ARBITER_BP_READ_4_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_READ_4 :: bsp [05:05] */ -#define GISB_ARBITER_BP_READ_4_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_READ_4_bsp_ALIGN 0 -#define GISB_ARBITER_BP_READ_4_bsp_BITS 1 -#define GISB_ARBITER_BP_READ_4_bsp_SHIFT 5 -#define GISB_ARBITER_BP_READ_4_bsp_DISABLE 0 -#define GISB_ARBITER_BP_READ_4_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_4 :: aes [04:04] */ -#define GISB_ARBITER_BP_READ_4_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_READ_4_aes_ALIGN 0 -#define GISB_ARBITER_BP_READ_4_aes_BITS 1 -#define GISB_ARBITER_BP_READ_4_aes_SHIFT 4 -#define GISB_ARBITER_BP_READ_4_aes_DISABLE 0 -#define GISB_ARBITER_BP_READ_4_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_4 :: fve [03:03] */ -#define GISB_ARBITER_BP_READ_4_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_READ_4_fve_ALIGN 0 -#define GISB_ARBITER_BP_READ_4_fve_BITS 1 -#define GISB_ARBITER_BP_READ_4_fve_SHIFT 3 -#define GISB_ARBITER_BP_READ_4_fve_DISABLE 0 -#define GISB_ARBITER_BP_READ_4_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_4 :: tgt [02:02] */ -#define GISB_ARBITER_BP_READ_4_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_READ_4_tgt_ALIGN 0 -#define GISB_ARBITER_BP_READ_4_tgt_BITS 1 -#define GISB_ARBITER_BP_READ_4_tgt_SHIFT 2 -#define GISB_ARBITER_BP_READ_4_tgt_DISABLE 0 -#define GISB_ARBITER_BP_READ_4_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_4 :: dbu [01:01] */ -#define GISB_ARBITER_BP_READ_4_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_READ_4_dbu_ALIGN 0 -#define GISB_ARBITER_BP_READ_4_dbu_BITS 1 -#define GISB_ARBITER_BP_READ_4_dbu_SHIFT 1 -#define GISB_ARBITER_BP_READ_4_dbu_DISABLE 0 -#define GISB_ARBITER_BP_READ_4_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_4 :: cce [00:00] */ -#define GISB_ARBITER_BP_READ_4_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_READ_4_cce_ALIGN 0 -#define GISB_ARBITER_BP_READ_4_cce_BITS 1 -#define GISB_ARBITER_BP_READ_4_cce_SHIFT 0 -#define GISB_ARBITER_BP_READ_4_cce_DISABLE 0 -#define GISB_ARBITER_BP_READ_4_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_WRITE_4 - ***************************************************************************/ -/* GISB_ARBITER :: BP_WRITE_4 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_WRITE_4_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_WRITE_4_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_4_reserved0_BITS 26 -#define GISB_ARBITER_BP_WRITE_4_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_WRITE_4 :: bsp [05:05] */ -#define GISB_ARBITER_BP_WRITE_4_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_WRITE_4_bsp_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_4_bsp_BITS 1 -#define GISB_ARBITER_BP_WRITE_4_bsp_SHIFT 5 -#define GISB_ARBITER_BP_WRITE_4_bsp_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_4_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_4 :: aes [04:04] */ -#define GISB_ARBITER_BP_WRITE_4_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_WRITE_4_aes_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_4_aes_BITS 1 -#define GISB_ARBITER_BP_WRITE_4_aes_SHIFT 4 -#define GISB_ARBITER_BP_WRITE_4_aes_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_4_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_4 :: fve [03:03] */ -#define GISB_ARBITER_BP_WRITE_4_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_WRITE_4_fve_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_4_fve_BITS 1 -#define GISB_ARBITER_BP_WRITE_4_fve_SHIFT 3 -#define GISB_ARBITER_BP_WRITE_4_fve_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_4_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_4 :: tgt [02:02] */ -#define GISB_ARBITER_BP_WRITE_4_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_WRITE_4_tgt_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_4_tgt_BITS 1 -#define GISB_ARBITER_BP_WRITE_4_tgt_SHIFT 2 -#define GISB_ARBITER_BP_WRITE_4_tgt_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_4_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_4 :: dbu [01:01] */ -#define GISB_ARBITER_BP_WRITE_4_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_WRITE_4_dbu_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_4_dbu_BITS 1 -#define GISB_ARBITER_BP_WRITE_4_dbu_SHIFT 1 -#define GISB_ARBITER_BP_WRITE_4_dbu_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_4_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_4 :: cce [00:00] */ -#define GISB_ARBITER_BP_WRITE_4_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_WRITE_4_cce_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_4_cce_BITS 1 -#define GISB_ARBITER_BP_WRITE_4_cce_SHIFT 0 -#define GISB_ARBITER_BP_WRITE_4_cce_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_4_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_ENABLE_4 - ***************************************************************************/ -/* GISB_ARBITER :: BP_ENABLE_4 :: reserved0 [31:03] */ -#define GISB_ARBITER_BP_ENABLE_4_reserved0_MASK 0xfffffff8 -#define GISB_ARBITER_BP_ENABLE_4_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_4_reserved0_BITS 29 -#define GISB_ARBITER_BP_ENABLE_4_reserved0_SHIFT 3 - -/* GISB_ARBITER :: BP_ENABLE_4 :: block [02:02] */ -#define GISB_ARBITER_BP_ENABLE_4_block_MASK 0x00000004 -#define GISB_ARBITER_BP_ENABLE_4_block_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_4_block_BITS 1 -#define GISB_ARBITER_BP_ENABLE_4_block_SHIFT 2 -#define GISB_ARBITER_BP_ENABLE_4_block_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_4_block_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_4 :: address [01:01] */ -#define GISB_ARBITER_BP_ENABLE_4_address_MASK 0x00000002 -#define GISB_ARBITER_BP_ENABLE_4_address_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_4_address_BITS 1 -#define GISB_ARBITER_BP_ENABLE_4_address_SHIFT 1 -#define GISB_ARBITER_BP_ENABLE_4_address_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_4_address_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_4 :: access [00:00] */ -#define GISB_ARBITER_BP_ENABLE_4_access_MASK 0x00000001 -#define GISB_ARBITER_BP_ENABLE_4_access_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_4_access_BITS 1 -#define GISB_ARBITER_BP_ENABLE_4_access_SHIFT 0 -#define GISB_ARBITER_BP_ENABLE_4_access_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_4_access_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_START_ADDR_5 - ***************************************************************************/ -/* GISB_ARBITER :: BP_START_ADDR_5 :: start [31:00] */ -#define GISB_ARBITER_BP_START_ADDR_5_start_MASK 0xffffffff -#define GISB_ARBITER_BP_START_ADDR_5_start_ALIGN 0 -#define GISB_ARBITER_BP_START_ADDR_5_start_BITS 32 -#define GISB_ARBITER_BP_START_ADDR_5_start_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_END_ADDR_5 - ***************************************************************************/ -/* GISB_ARBITER :: BP_END_ADDR_5 :: end [31:00] */ -#define GISB_ARBITER_BP_END_ADDR_5_end_MASK 0xffffffff -#define GISB_ARBITER_BP_END_ADDR_5_end_ALIGN 0 -#define GISB_ARBITER_BP_END_ADDR_5_end_BITS 32 -#define GISB_ARBITER_BP_END_ADDR_5_end_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_READ_5 - ***************************************************************************/ -/* GISB_ARBITER :: BP_READ_5 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_READ_5_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_READ_5_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_READ_5_reserved0_BITS 26 -#define GISB_ARBITER_BP_READ_5_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_READ_5 :: bsp [05:05] */ -#define GISB_ARBITER_BP_READ_5_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_READ_5_bsp_ALIGN 0 -#define GISB_ARBITER_BP_READ_5_bsp_BITS 1 -#define GISB_ARBITER_BP_READ_5_bsp_SHIFT 5 -#define GISB_ARBITER_BP_READ_5_bsp_DISABLE 0 -#define GISB_ARBITER_BP_READ_5_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_5 :: aes [04:04] */ -#define GISB_ARBITER_BP_READ_5_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_READ_5_aes_ALIGN 0 -#define GISB_ARBITER_BP_READ_5_aes_BITS 1 -#define GISB_ARBITER_BP_READ_5_aes_SHIFT 4 -#define GISB_ARBITER_BP_READ_5_aes_DISABLE 0 -#define GISB_ARBITER_BP_READ_5_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_5 :: fve [03:03] */ -#define GISB_ARBITER_BP_READ_5_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_READ_5_fve_ALIGN 0 -#define GISB_ARBITER_BP_READ_5_fve_BITS 1 -#define GISB_ARBITER_BP_READ_5_fve_SHIFT 3 -#define GISB_ARBITER_BP_READ_5_fve_DISABLE 0 -#define GISB_ARBITER_BP_READ_5_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_5 :: tgt [02:02] */ -#define GISB_ARBITER_BP_READ_5_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_READ_5_tgt_ALIGN 0 -#define GISB_ARBITER_BP_READ_5_tgt_BITS 1 -#define GISB_ARBITER_BP_READ_5_tgt_SHIFT 2 -#define GISB_ARBITER_BP_READ_5_tgt_DISABLE 0 -#define GISB_ARBITER_BP_READ_5_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_5 :: dbu [01:01] */ -#define GISB_ARBITER_BP_READ_5_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_READ_5_dbu_ALIGN 0 -#define GISB_ARBITER_BP_READ_5_dbu_BITS 1 -#define GISB_ARBITER_BP_READ_5_dbu_SHIFT 1 -#define GISB_ARBITER_BP_READ_5_dbu_DISABLE 0 -#define GISB_ARBITER_BP_READ_5_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_5 :: cce [00:00] */ -#define GISB_ARBITER_BP_READ_5_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_READ_5_cce_ALIGN 0 -#define GISB_ARBITER_BP_READ_5_cce_BITS 1 -#define GISB_ARBITER_BP_READ_5_cce_SHIFT 0 -#define GISB_ARBITER_BP_READ_5_cce_DISABLE 0 -#define GISB_ARBITER_BP_READ_5_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_WRITE_5 - ***************************************************************************/ -/* GISB_ARBITER :: BP_WRITE_5 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_WRITE_5_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_WRITE_5_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_5_reserved0_BITS 26 -#define GISB_ARBITER_BP_WRITE_5_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_WRITE_5 :: bsp [05:05] */ -#define GISB_ARBITER_BP_WRITE_5_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_WRITE_5_bsp_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_5_bsp_BITS 1 -#define GISB_ARBITER_BP_WRITE_5_bsp_SHIFT 5 -#define GISB_ARBITER_BP_WRITE_5_bsp_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_5_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_5 :: aes [04:04] */ -#define GISB_ARBITER_BP_WRITE_5_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_WRITE_5_aes_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_5_aes_BITS 1 -#define GISB_ARBITER_BP_WRITE_5_aes_SHIFT 4 -#define GISB_ARBITER_BP_WRITE_5_aes_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_5_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_5 :: fve [03:03] */ -#define GISB_ARBITER_BP_WRITE_5_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_WRITE_5_fve_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_5_fve_BITS 1 -#define GISB_ARBITER_BP_WRITE_5_fve_SHIFT 3 -#define GISB_ARBITER_BP_WRITE_5_fve_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_5_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_5 :: tgt [02:02] */ -#define GISB_ARBITER_BP_WRITE_5_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_WRITE_5_tgt_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_5_tgt_BITS 1 -#define GISB_ARBITER_BP_WRITE_5_tgt_SHIFT 2 -#define GISB_ARBITER_BP_WRITE_5_tgt_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_5_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_5 :: dbu [01:01] */ -#define GISB_ARBITER_BP_WRITE_5_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_WRITE_5_dbu_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_5_dbu_BITS 1 -#define GISB_ARBITER_BP_WRITE_5_dbu_SHIFT 1 -#define GISB_ARBITER_BP_WRITE_5_dbu_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_5_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_5 :: cce [00:00] */ -#define GISB_ARBITER_BP_WRITE_5_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_WRITE_5_cce_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_5_cce_BITS 1 -#define GISB_ARBITER_BP_WRITE_5_cce_SHIFT 0 -#define GISB_ARBITER_BP_WRITE_5_cce_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_5_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_ENABLE_5 - ***************************************************************************/ -/* GISB_ARBITER :: BP_ENABLE_5 :: reserved0 [31:03] */ -#define GISB_ARBITER_BP_ENABLE_5_reserved0_MASK 0xfffffff8 -#define GISB_ARBITER_BP_ENABLE_5_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_5_reserved0_BITS 29 -#define GISB_ARBITER_BP_ENABLE_5_reserved0_SHIFT 3 - -/* GISB_ARBITER :: BP_ENABLE_5 :: block [02:02] */ -#define GISB_ARBITER_BP_ENABLE_5_block_MASK 0x00000004 -#define GISB_ARBITER_BP_ENABLE_5_block_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_5_block_BITS 1 -#define GISB_ARBITER_BP_ENABLE_5_block_SHIFT 2 -#define GISB_ARBITER_BP_ENABLE_5_block_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_5_block_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_5 :: address [01:01] */ -#define GISB_ARBITER_BP_ENABLE_5_address_MASK 0x00000002 -#define GISB_ARBITER_BP_ENABLE_5_address_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_5_address_BITS 1 -#define GISB_ARBITER_BP_ENABLE_5_address_SHIFT 1 -#define GISB_ARBITER_BP_ENABLE_5_address_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_5_address_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_5 :: access [00:00] */ -#define GISB_ARBITER_BP_ENABLE_5_access_MASK 0x00000001 -#define GISB_ARBITER_BP_ENABLE_5_access_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_5_access_BITS 1 -#define GISB_ARBITER_BP_ENABLE_5_access_SHIFT 0 -#define GISB_ARBITER_BP_ENABLE_5_access_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_5_access_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_START_ADDR_6 - ***************************************************************************/ -/* GISB_ARBITER :: BP_START_ADDR_6 :: start [31:00] */ -#define GISB_ARBITER_BP_START_ADDR_6_start_MASK 0xffffffff -#define GISB_ARBITER_BP_START_ADDR_6_start_ALIGN 0 -#define GISB_ARBITER_BP_START_ADDR_6_start_BITS 32 -#define GISB_ARBITER_BP_START_ADDR_6_start_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_END_ADDR_6 - ***************************************************************************/ -/* GISB_ARBITER :: BP_END_ADDR_6 :: end [31:00] */ -#define GISB_ARBITER_BP_END_ADDR_6_end_MASK 0xffffffff -#define GISB_ARBITER_BP_END_ADDR_6_end_ALIGN 0 -#define GISB_ARBITER_BP_END_ADDR_6_end_BITS 32 -#define GISB_ARBITER_BP_END_ADDR_6_end_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_READ_6 - ***************************************************************************/ -/* GISB_ARBITER :: BP_READ_6 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_READ_6_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_READ_6_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_READ_6_reserved0_BITS 26 -#define GISB_ARBITER_BP_READ_6_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_READ_6 :: bsp [05:05] */ -#define GISB_ARBITER_BP_READ_6_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_READ_6_bsp_ALIGN 0 -#define GISB_ARBITER_BP_READ_6_bsp_BITS 1 -#define GISB_ARBITER_BP_READ_6_bsp_SHIFT 5 -#define GISB_ARBITER_BP_READ_6_bsp_DISABLE 0 -#define GISB_ARBITER_BP_READ_6_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_6 :: aes [04:04] */ -#define GISB_ARBITER_BP_READ_6_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_READ_6_aes_ALIGN 0 -#define GISB_ARBITER_BP_READ_6_aes_BITS 1 -#define GISB_ARBITER_BP_READ_6_aes_SHIFT 4 -#define GISB_ARBITER_BP_READ_6_aes_DISABLE 0 -#define GISB_ARBITER_BP_READ_6_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_6 :: fve [03:03] */ -#define GISB_ARBITER_BP_READ_6_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_READ_6_fve_ALIGN 0 -#define GISB_ARBITER_BP_READ_6_fve_BITS 1 -#define GISB_ARBITER_BP_READ_6_fve_SHIFT 3 -#define GISB_ARBITER_BP_READ_6_fve_DISABLE 0 -#define GISB_ARBITER_BP_READ_6_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_6 :: tgt [02:02] */ -#define GISB_ARBITER_BP_READ_6_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_READ_6_tgt_ALIGN 0 -#define GISB_ARBITER_BP_READ_6_tgt_BITS 1 -#define GISB_ARBITER_BP_READ_6_tgt_SHIFT 2 -#define GISB_ARBITER_BP_READ_6_tgt_DISABLE 0 -#define GISB_ARBITER_BP_READ_6_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_6 :: dbu [01:01] */ -#define GISB_ARBITER_BP_READ_6_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_READ_6_dbu_ALIGN 0 -#define GISB_ARBITER_BP_READ_6_dbu_BITS 1 -#define GISB_ARBITER_BP_READ_6_dbu_SHIFT 1 -#define GISB_ARBITER_BP_READ_6_dbu_DISABLE 0 -#define GISB_ARBITER_BP_READ_6_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_6 :: cce [00:00] */ -#define GISB_ARBITER_BP_READ_6_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_READ_6_cce_ALIGN 0 -#define GISB_ARBITER_BP_READ_6_cce_BITS 1 -#define GISB_ARBITER_BP_READ_6_cce_SHIFT 0 -#define GISB_ARBITER_BP_READ_6_cce_DISABLE 0 -#define GISB_ARBITER_BP_READ_6_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_WRITE_6 - ***************************************************************************/ -/* GISB_ARBITER :: BP_WRITE_6 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_WRITE_6_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_WRITE_6_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_6_reserved0_BITS 26 -#define GISB_ARBITER_BP_WRITE_6_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_WRITE_6 :: bsp [05:05] */ -#define GISB_ARBITER_BP_WRITE_6_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_WRITE_6_bsp_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_6_bsp_BITS 1 -#define GISB_ARBITER_BP_WRITE_6_bsp_SHIFT 5 -#define GISB_ARBITER_BP_WRITE_6_bsp_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_6_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_6 :: aes [04:04] */ -#define GISB_ARBITER_BP_WRITE_6_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_WRITE_6_aes_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_6_aes_BITS 1 -#define GISB_ARBITER_BP_WRITE_6_aes_SHIFT 4 -#define GISB_ARBITER_BP_WRITE_6_aes_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_6_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_6 :: fve [03:03] */ -#define GISB_ARBITER_BP_WRITE_6_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_WRITE_6_fve_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_6_fve_BITS 1 -#define GISB_ARBITER_BP_WRITE_6_fve_SHIFT 3 -#define GISB_ARBITER_BP_WRITE_6_fve_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_6_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_6 :: tgt [02:02] */ -#define GISB_ARBITER_BP_WRITE_6_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_WRITE_6_tgt_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_6_tgt_BITS 1 -#define GISB_ARBITER_BP_WRITE_6_tgt_SHIFT 2 -#define GISB_ARBITER_BP_WRITE_6_tgt_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_6_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_6 :: dbu [01:01] */ -#define GISB_ARBITER_BP_WRITE_6_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_WRITE_6_dbu_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_6_dbu_BITS 1 -#define GISB_ARBITER_BP_WRITE_6_dbu_SHIFT 1 -#define GISB_ARBITER_BP_WRITE_6_dbu_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_6_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_6 :: cce [00:00] */ -#define GISB_ARBITER_BP_WRITE_6_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_WRITE_6_cce_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_6_cce_BITS 1 -#define GISB_ARBITER_BP_WRITE_6_cce_SHIFT 0 -#define GISB_ARBITER_BP_WRITE_6_cce_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_6_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_ENABLE_6 - ***************************************************************************/ -/* GISB_ARBITER :: BP_ENABLE_6 :: reserved0 [31:03] */ -#define GISB_ARBITER_BP_ENABLE_6_reserved0_MASK 0xfffffff8 -#define GISB_ARBITER_BP_ENABLE_6_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_6_reserved0_BITS 29 -#define GISB_ARBITER_BP_ENABLE_6_reserved0_SHIFT 3 - -/* GISB_ARBITER :: BP_ENABLE_6 :: block [02:02] */ -#define GISB_ARBITER_BP_ENABLE_6_block_MASK 0x00000004 -#define GISB_ARBITER_BP_ENABLE_6_block_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_6_block_BITS 1 -#define GISB_ARBITER_BP_ENABLE_6_block_SHIFT 2 -#define GISB_ARBITER_BP_ENABLE_6_block_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_6_block_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_6 :: address [01:01] */ -#define GISB_ARBITER_BP_ENABLE_6_address_MASK 0x00000002 -#define GISB_ARBITER_BP_ENABLE_6_address_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_6_address_BITS 1 -#define GISB_ARBITER_BP_ENABLE_6_address_SHIFT 1 -#define GISB_ARBITER_BP_ENABLE_6_address_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_6_address_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_6 :: access [00:00] */ -#define GISB_ARBITER_BP_ENABLE_6_access_MASK 0x00000001 -#define GISB_ARBITER_BP_ENABLE_6_access_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_6_access_BITS 1 -#define GISB_ARBITER_BP_ENABLE_6_access_SHIFT 0 -#define GISB_ARBITER_BP_ENABLE_6_access_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_6_access_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_START_ADDR_7 - ***************************************************************************/ -/* GISB_ARBITER :: BP_START_ADDR_7 :: start [31:00] */ -#define GISB_ARBITER_BP_START_ADDR_7_start_MASK 0xffffffff -#define GISB_ARBITER_BP_START_ADDR_7_start_ALIGN 0 -#define GISB_ARBITER_BP_START_ADDR_7_start_BITS 32 -#define GISB_ARBITER_BP_START_ADDR_7_start_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_END_ADDR_7 - ***************************************************************************/ -/* GISB_ARBITER :: BP_END_ADDR_7 :: end [31:00] */ -#define GISB_ARBITER_BP_END_ADDR_7_end_MASK 0xffffffff -#define GISB_ARBITER_BP_END_ADDR_7_end_ALIGN 0 -#define GISB_ARBITER_BP_END_ADDR_7_end_BITS 32 -#define GISB_ARBITER_BP_END_ADDR_7_end_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_READ_7 - ***************************************************************************/ -/* GISB_ARBITER :: BP_READ_7 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_READ_7_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_READ_7_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_READ_7_reserved0_BITS 26 -#define GISB_ARBITER_BP_READ_7_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_READ_7 :: bsp [05:05] */ -#define GISB_ARBITER_BP_READ_7_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_READ_7_bsp_ALIGN 0 -#define GISB_ARBITER_BP_READ_7_bsp_BITS 1 -#define GISB_ARBITER_BP_READ_7_bsp_SHIFT 5 -#define GISB_ARBITER_BP_READ_7_bsp_DISABLE 0 -#define GISB_ARBITER_BP_READ_7_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_7 :: aes [04:04] */ -#define GISB_ARBITER_BP_READ_7_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_READ_7_aes_ALIGN 0 -#define GISB_ARBITER_BP_READ_7_aes_BITS 1 -#define GISB_ARBITER_BP_READ_7_aes_SHIFT 4 -#define GISB_ARBITER_BP_READ_7_aes_DISABLE 0 -#define GISB_ARBITER_BP_READ_7_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_7 :: fve [03:03] */ -#define GISB_ARBITER_BP_READ_7_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_READ_7_fve_ALIGN 0 -#define GISB_ARBITER_BP_READ_7_fve_BITS 1 -#define GISB_ARBITER_BP_READ_7_fve_SHIFT 3 -#define GISB_ARBITER_BP_READ_7_fve_DISABLE 0 -#define GISB_ARBITER_BP_READ_7_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_7 :: tgt [02:02] */ -#define GISB_ARBITER_BP_READ_7_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_READ_7_tgt_ALIGN 0 -#define GISB_ARBITER_BP_READ_7_tgt_BITS 1 -#define GISB_ARBITER_BP_READ_7_tgt_SHIFT 2 -#define GISB_ARBITER_BP_READ_7_tgt_DISABLE 0 -#define GISB_ARBITER_BP_READ_7_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_7 :: dbu [01:01] */ -#define GISB_ARBITER_BP_READ_7_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_READ_7_dbu_ALIGN 0 -#define GISB_ARBITER_BP_READ_7_dbu_BITS 1 -#define GISB_ARBITER_BP_READ_7_dbu_SHIFT 1 -#define GISB_ARBITER_BP_READ_7_dbu_DISABLE 0 -#define GISB_ARBITER_BP_READ_7_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_READ_7 :: cce [00:00] */ -#define GISB_ARBITER_BP_READ_7_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_READ_7_cce_ALIGN 0 -#define GISB_ARBITER_BP_READ_7_cce_BITS 1 -#define GISB_ARBITER_BP_READ_7_cce_SHIFT 0 -#define GISB_ARBITER_BP_READ_7_cce_DISABLE 0 -#define GISB_ARBITER_BP_READ_7_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_WRITE_7 - ***************************************************************************/ -/* GISB_ARBITER :: BP_WRITE_7 :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_WRITE_7_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_WRITE_7_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_7_reserved0_BITS 26 -#define GISB_ARBITER_BP_WRITE_7_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_WRITE_7 :: bsp [05:05] */ -#define GISB_ARBITER_BP_WRITE_7_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_WRITE_7_bsp_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_7_bsp_BITS 1 -#define GISB_ARBITER_BP_WRITE_7_bsp_SHIFT 5 -#define GISB_ARBITER_BP_WRITE_7_bsp_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_7_bsp_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_7 :: aes [04:04] */ -#define GISB_ARBITER_BP_WRITE_7_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_WRITE_7_aes_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_7_aes_BITS 1 -#define GISB_ARBITER_BP_WRITE_7_aes_SHIFT 4 -#define GISB_ARBITER_BP_WRITE_7_aes_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_7_aes_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_7 :: fve [03:03] */ -#define GISB_ARBITER_BP_WRITE_7_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_WRITE_7_fve_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_7_fve_BITS 1 -#define GISB_ARBITER_BP_WRITE_7_fve_SHIFT 3 -#define GISB_ARBITER_BP_WRITE_7_fve_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_7_fve_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_7 :: tgt [02:02] */ -#define GISB_ARBITER_BP_WRITE_7_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_WRITE_7_tgt_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_7_tgt_BITS 1 -#define GISB_ARBITER_BP_WRITE_7_tgt_SHIFT 2 -#define GISB_ARBITER_BP_WRITE_7_tgt_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_7_tgt_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_7 :: dbu [01:01] */ -#define GISB_ARBITER_BP_WRITE_7_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_WRITE_7_dbu_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_7_dbu_BITS 1 -#define GISB_ARBITER_BP_WRITE_7_dbu_SHIFT 1 -#define GISB_ARBITER_BP_WRITE_7_dbu_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_7_dbu_ENABLE 1 - -/* GISB_ARBITER :: BP_WRITE_7 :: cce [00:00] */ -#define GISB_ARBITER_BP_WRITE_7_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_WRITE_7_cce_ALIGN 0 -#define GISB_ARBITER_BP_WRITE_7_cce_BITS 1 -#define GISB_ARBITER_BP_WRITE_7_cce_SHIFT 0 -#define GISB_ARBITER_BP_WRITE_7_cce_DISABLE 0 -#define GISB_ARBITER_BP_WRITE_7_cce_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_ENABLE_7 - ***************************************************************************/ -/* GISB_ARBITER :: BP_ENABLE_7 :: reserved0 [31:03] */ -#define GISB_ARBITER_BP_ENABLE_7_reserved0_MASK 0xfffffff8 -#define GISB_ARBITER_BP_ENABLE_7_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_7_reserved0_BITS 29 -#define GISB_ARBITER_BP_ENABLE_7_reserved0_SHIFT 3 - -/* GISB_ARBITER :: BP_ENABLE_7 :: block [02:02] */ -#define GISB_ARBITER_BP_ENABLE_7_block_MASK 0x00000004 -#define GISB_ARBITER_BP_ENABLE_7_block_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_7_block_BITS 1 -#define GISB_ARBITER_BP_ENABLE_7_block_SHIFT 2 -#define GISB_ARBITER_BP_ENABLE_7_block_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_7_block_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_7 :: address [01:01] */ -#define GISB_ARBITER_BP_ENABLE_7_address_MASK 0x00000002 -#define GISB_ARBITER_BP_ENABLE_7_address_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_7_address_BITS 1 -#define GISB_ARBITER_BP_ENABLE_7_address_SHIFT 1 -#define GISB_ARBITER_BP_ENABLE_7_address_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_7_address_ENABLE 1 - -/* GISB_ARBITER :: BP_ENABLE_7 :: access [00:00] */ -#define GISB_ARBITER_BP_ENABLE_7_access_MASK 0x00000001 -#define GISB_ARBITER_BP_ENABLE_7_access_ALIGN 0 -#define GISB_ARBITER_BP_ENABLE_7_access_BITS 1 -#define GISB_ARBITER_BP_ENABLE_7_access_SHIFT 0 -#define GISB_ARBITER_BP_ENABLE_7_access_DISABLE 0 -#define GISB_ARBITER_BP_ENABLE_7_access_ENABLE 1 - - -/**************************************************************************** - * GISB_ARBITER :: BP_CAP_ADDR - ***************************************************************************/ -/* GISB_ARBITER :: BP_CAP_ADDR :: address [31:00] */ -#define GISB_ARBITER_BP_CAP_ADDR_address_MASK 0xffffffff -#define GISB_ARBITER_BP_CAP_ADDR_address_ALIGN 0 -#define GISB_ARBITER_BP_CAP_ADDR_address_BITS 32 -#define GISB_ARBITER_BP_CAP_ADDR_address_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_CAP_DATA - ***************************************************************************/ -/* GISB_ARBITER :: BP_CAP_DATA :: data [31:00] */ -#define GISB_ARBITER_BP_CAP_DATA_data_MASK 0xffffffff -#define GISB_ARBITER_BP_CAP_DATA_data_ALIGN 0 -#define GISB_ARBITER_BP_CAP_DATA_data_BITS 32 -#define GISB_ARBITER_BP_CAP_DATA_data_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_CAP_STATUS - ***************************************************************************/ -/* GISB_ARBITER :: BP_CAP_STATUS :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_CAP_STATUS_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_CAP_STATUS_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_CAP_STATUS_reserved0_BITS 26 -#define GISB_ARBITER_BP_CAP_STATUS_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_CAP_STATUS :: bs_b [05:02] */ -#define GISB_ARBITER_BP_CAP_STATUS_bs_b_MASK 0x0000003c -#define GISB_ARBITER_BP_CAP_STATUS_bs_b_ALIGN 0 -#define GISB_ARBITER_BP_CAP_STATUS_bs_b_BITS 4 -#define GISB_ARBITER_BP_CAP_STATUS_bs_b_SHIFT 2 - -/* GISB_ARBITER :: BP_CAP_STATUS :: write [01:01] */ -#define GISB_ARBITER_BP_CAP_STATUS_write_MASK 0x00000002 -#define GISB_ARBITER_BP_CAP_STATUS_write_ALIGN 0 -#define GISB_ARBITER_BP_CAP_STATUS_write_BITS 1 -#define GISB_ARBITER_BP_CAP_STATUS_write_SHIFT 1 - -/* GISB_ARBITER :: BP_CAP_STATUS :: valid [00:00] */ -#define GISB_ARBITER_BP_CAP_STATUS_valid_MASK 0x00000001 -#define GISB_ARBITER_BP_CAP_STATUS_valid_ALIGN 0 -#define GISB_ARBITER_BP_CAP_STATUS_valid_BITS 1 -#define GISB_ARBITER_BP_CAP_STATUS_valid_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: BP_CAP_MASTER - ***************************************************************************/ -/* GISB_ARBITER :: BP_CAP_MASTER :: reserved0 [31:06] */ -#define GISB_ARBITER_BP_CAP_MASTER_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_BP_CAP_MASTER_reserved0_ALIGN 0 -#define GISB_ARBITER_BP_CAP_MASTER_reserved0_BITS 26 -#define GISB_ARBITER_BP_CAP_MASTER_reserved0_SHIFT 6 - -/* GISB_ARBITER :: BP_CAP_MASTER :: bsp [05:05] */ -#define GISB_ARBITER_BP_CAP_MASTER_bsp_MASK 0x00000020 -#define GISB_ARBITER_BP_CAP_MASTER_bsp_ALIGN 0 -#define GISB_ARBITER_BP_CAP_MASTER_bsp_BITS 1 -#define GISB_ARBITER_BP_CAP_MASTER_bsp_SHIFT 5 - -/* GISB_ARBITER :: BP_CAP_MASTER :: aes [04:04] */ -#define GISB_ARBITER_BP_CAP_MASTER_aes_MASK 0x00000010 -#define GISB_ARBITER_BP_CAP_MASTER_aes_ALIGN 0 -#define GISB_ARBITER_BP_CAP_MASTER_aes_BITS 1 -#define GISB_ARBITER_BP_CAP_MASTER_aes_SHIFT 4 - -/* GISB_ARBITER :: BP_CAP_MASTER :: fve [03:03] */ -#define GISB_ARBITER_BP_CAP_MASTER_fve_MASK 0x00000008 -#define GISB_ARBITER_BP_CAP_MASTER_fve_ALIGN 0 -#define GISB_ARBITER_BP_CAP_MASTER_fve_BITS 1 -#define GISB_ARBITER_BP_CAP_MASTER_fve_SHIFT 3 - -/* GISB_ARBITER :: BP_CAP_MASTER :: tgt [02:02] */ -#define GISB_ARBITER_BP_CAP_MASTER_tgt_MASK 0x00000004 -#define GISB_ARBITER_BP_CAP_MASTER_tgt_ALIGN 0 -#define GISB_ARBITER_BP_CAP_MASTER_tgt_BITS 1 -#define GISB_ARBITER_BP_CAP_MASTER_tgt_SHIFT 2 - -/* GISB_ARBITER :: BP_CAP_MASTER :: dbu [01:01] */ -#define GISB_ARBITER_BP_CAP_MASTER_dbu_MASK 0x00000002 -#define GISB_ARBITER_BP_CAP_MASTER_dbu_ALIGN 0 -#define GISB_ARBITER_BP_CAP_MASTER_dbu_BITS 1 -#define GISB_ARBITER_BP_CAP_MASTER_dbu_SHIFT 1 - -/* GISB_ARBITER :: BP_CAP_MASTER :: cce [00:00] */ -#define GISB_ARBITER_BP_CAP_MASTER_cce_MASK 0x00000001 -#define GISB_ARBITER_BP_CAP_MASTER_cce_ALIGN 0 -#define GISB_ARBITER_BP_CAP_MASTER_cce_BITS 1 -#define GISB_ARBITER_BP_CAP_MASTER_cce_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: ERR_CAP_CLR - ***************************************************************************/ -/* GISB_ARBITER :: ERR_CAP_CLR :: reserved0 [31:01] */ -#define GISB_ARBITER_ERR_CAP_CLR_reserved0_MASK 0xfffffffe -#define GISB_ARBITER_ERR_CAP_CLR_reserved0_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_CLR_reserved0_BITS 31 -#define GISB_ARBITER_ERR_CAP_CLR_reserved0_SHIFT 1 - -/* GISB_ARBITER :: ERR_CAP_CLR :: clear [00:00] */ -#define GISB_ARBITER_ERR_CAP_CLR_clear_MASK 0x00000001 -#define GISB_ARBITER_ERR_CAP_CLR_clear_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_CLR_clear_BITS 1 -#define GISB_ARBITER_ERR_CAP_CLR_clear_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: ERR_CAP_ADDR - ***************************************************************************/ -/* GISB_ARBITER :: ERR_CAP_ADDR :: address [31:00] */ -#define GISB_ARBITER_ERR_CAP_ADDR_address_MASK 0xffffffff -#define GISB_ARBITER_ERR_CAP_ADDR_address_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_ADDR_address_BITS 32 -#define GISB_ARBITER_ERR_CAP_ADDR_address_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: ERR_CAP_DATA - ***************************************************************************/ -/* GISB_ARBITER :: ERR_CAP_DATA :: data [31:00] */ -#define GISB_ARBITER_ERR_CAP_DATA_data_MASK 0xffffffff -#define GISB_ARBITER_ERR_CAP_DATA_data_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_DATA_data_BITS 32 -#define GISB_ARBITER_ERR_CAP_DATA_data_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: ERR_CAP_STATUS - ***************************************************************************/ -/* GISB_ARBITER :: ERR_CAP_STATUS :: reserved0 [31:13] */ -#define GISB_ARBITER_ERR_CAP_STATUS_reserved0_MASK 0xffffe000 -#define GISB_ARBITER_ERR_CAP_STATUS_reserved0_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_STATUS_reserved0_BITS 19 -#define GISB_ARBITER_ERR_CAP_STATUS_reserved0_SHIFT 13 - -/* GISB_ARBITER :: ERR_CAP_STATUS :: timeout [12:12] */ -#define GISB_ARBITER_ERR_CAP_STATUS_timeout_MASK 0x00001000 -#define GISB_ARBITER_ERR_CAP_STATUS_timeout_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_STATUS_timeout_BITS 1 -#define GISB_ARBITER_ERR_CAP_STATUS_timeout_SHIFT 12 - -/* GISB_ARBITER :: ERR_CAP_STATUS :: tea [11:11] */ -#define GISB_ARBITER_ERR_CAP_STATUS_tea_MASK 0x00000800 -#define GISB_ARBITER_ERR_CAP_STATUS_tea_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_STATUS_tea_BITS 1 -#define GISB_ARBITER_ERR_CAP_STATUS_tea_SHIFT 11 - -/* GISB_ARBITER :: ERR_CAP_STATUS :: reserved1 [10:06] */ -#define GISB_ARBITER_ERR_CAP_STATUS_reserved1_MASK 0x000007c0 -#define GISB_ARBITER_ERR_CAP_STATUS_reserved1_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_STATUS_reserved1_BITS 5 -#define GISB_ARBITER_ERR_CAP_STATUS_reserved1_SHIFT 6 - -/* GISB_ARBITER :: ERR_CAP_STATUS :: bs_b [05:02] */ -#define GISB_ARBITER_ERR_CAP_STATUS_bs_b_MASK 0x0000003c -#define GISB_ARBITER_ERR_CAP_STATUS_bs_b_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_STATUS_bs_b_BITS 4 -#define GISB_ARBITER_ERR_CAP_STATUS_bs_b_SHIFT 2 - -/* GISB_ARBITER :: ERR_CAP_STATUS :: write [01:01] */ -#define GISB_ARBITER_ERR_CAP_STATUS_write_MASK 0x00000002 -#define GISB_ARBITER_ERR_CAP_STATUS_write_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_STATUS_write_BITS 1 -#define GISB_ARBITER_ERR_CAP_STATUS_write_SHIFT 1 - -/* GISB_ARBITER :: ERR_CAP_STATUS :: valid [00:00] */ -#define GISB_ARBITER_ERR_CAP_STATUS_valid_MASK 0x00000001 -#define GISB_ARBITER_ERR_CAP_STATUS_valid_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_STATUS_valid_BITS 1 -#define GISB_ARBITER_ERR_CAP_STATUS_valid_SHIFT 0 - - -/**************************************************************************** - * GISB_ARBITER :: ERR_CAP_MASTER - ***************************************************************************/ -/* GISB_ARBITER :: ERR_CAP_MASTER :: reserved0 [31:06] */ -#define GISB_ARBITER_ERR_CAP_MASTER_reserved0_MASK 0xffffffc0 -#define GISB_ARBITER_ERR_CAP_MASTER_reserved0_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_MASTER_reserved0_BITS 26 -#define GISB_ARBITER_ERR_CAP_MASTER_reserved0_SHIFT 6 - -/* GISB_ARBITER :: ERR_CAP_MASTER :: bsp [05:05] */ -#define GISB_ARBITER_ERR_CAP_MASTER_bsp_MASK 0x00000020 -#define GISB_ARBITER_ERR_CAP_MASTER_bsp_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_MASTER_bsp_BITS 1 -#define GISB_ARBITER_ERR_CAP_MASTER_bsp_SHIFT 5 - -/* GISB_ARBITER :: ERR_CAP_MASTER :: aes [04:04] */ -#define GISB_ARBITER_ERR_CAP_MASTER_aes_MASK 0x00000010 -#define GISB_ARBITER_ERR_CAP_MASTER_aes_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_MASTER_aes_BITS 1 -#define GISB_ARBITER_ERR_CAP_MASTER_aes_SHIFT 4 - -/* GISB_ARBITER :: ERR_CAP_MASTER :: fve [03:03] */ -#define GISB_ARBITER_ERR_CAP_MASTER_fve_MASK 0x00000008 -#define GISB_ARBITER_ERR_CAP_MASTER_fve_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_MASTER_fve_BITS 1 -#define GISB_ARBITER_ERR_CAP_MASTER_fve_SHIFT 3 - -/* GISB_ARBITER :: ERR_CAP_MASTER :: tgt [02:02] */ -#define GISB_ARBITER_ERR_CAP_MASTER_tgt_MASK 0x00000004 -#define GISB_ARBITER_ERR_CAP_MASTER_tgt_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_MASTER_tgt_BITS 1 -#define GISB_ARBITER_ERR_CAP_MASTER_tgt_SHIFT 2 - -/* GISB_ARBITER :: ERR_CAP_MASTER :: dbu [01:01] */ -#define GISB_ARBITER_ERR_CAP_MASTER_dbu_MASK 0x00000002 -#define GISB_ARBITER_ERR_CAP_MASTER_dbu_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_MASTER_dbu_BITS 1 -#define GISB_ARBITER_ERR_CAP_MASTER_dbu_SHIFT 1 - -/* GISB_ARBITER :: ERR_CAP_MASTER :: cce [00:00] */ -#define GISB_ARBITER_ERR_CAP_MASTER_cce_MASK 0x00000001 -#define GISB_ARBITER_ERR_CAP_MASTER_cce_ALIGN 0 -#define GISB_ARBITER_ERR_CAP_MASTER_cce_BITS 1 -#define GISB_ARBITER_ERR_CAP_MASTER_cce_SHIFT 0 - - -/**************************************************************************** - * BCM70012_MISC_TOP_MISC_GR_BRIDGE - ***************************************************************************/ -/**************************************************************************** - * MISC_GR_BRIDGE :: REVISION - ***************************************************************************/ -/* MISC_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define MISC_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define MISC_GR_BRIDGE_REVISION_reserved0_ALIGN 0 -#define MISC_GR_BRIDGE_REVISION_reserved0_BITS 16 -#define MISC_GR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* MISC_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define MISC_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define MISC_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 -#define MISC_GR_BRIDGE_REVISION_MAJOR_BITS 8 -#define MISC_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* MISC_GR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define MISC_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define MISC_GR_BRIDGE_REVISION_MINOR_ALIGN 0 -#define MISC_GR_BRIDGE_REVISION_MINOR_BITS 8 -#define MISC_GR_BRIDGE_REVISION_MINOR_SHIFT 0 - - -/**************************************************************************** - * MISC_GR_BRIDGE :: CTRL - ***************************************************************************/ -/* MISC_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ -#define MISC_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe -#define MISC_GR_BRIDGE_CTRL_reserved0_ALIGN 0 -#define MISC_GR_BRIDGE_CTRL_reserved0_BITS 31 -#define MISC_GR_BRIDGE_CTRL_reserved0_SHIFT 1 - -/* MISC_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ -#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 -#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 -#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 -#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 -#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 - - -/**************************************************************************** - * MISC_GR_BRIDGE :: SPARE_SW_RESET_0 - ***************************************************************************/ -/* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 - -/* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 - - -/**************************************************************************** - * MISC_GR_BRIDGE :: SPARE_SW_RESET_1 - ***************************************************************************/ -/* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 - -/* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 -#define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 - - -/**************************************************************************** - * BCM70012_DBU_TOP_DBU - ***************************************************************************/ -/**************************************************************************** - * DBU :: DBU_CMD - ***************************************************************************/ -/* DBU :: DBU_CMD :: reserved0 [31:03] */ -#define DBU_DBU_CMD_reserved0_MASK 0xfffffff8 -#define DBU_DBU_CMD_reserved0_ALIGN 0 -#define DBU_DBU_CMD_reserved0_BITS 29 -#define DBU_DBU_CMD_reserved0_SHIFT 3 - -/* DBU :: DBU_CMD :: RX_OVERFLOW [02:02] */ -#define DBU_DBU_CMD_RX_OVERFLOW_MASK 0x00000004 -#define DBU_DBU_CMD_RX_OVERFLOW_ALIGN 0 -#define DBU_DBU_CMD_RX_OVERFLOW_BITS 1 -#define DBU_DBU_CMD_RX_OVERFLOW_SHIFT 2 - -/* DBU :: DBU_CMD :: RX_ERROR [01:01] */ -#define DBU_DBU_CMD_RX_ERROR_MASK 0x00000002 -#define DBU_DBU_CMD_RX_ERROR_ALIGN 0 -#define DBU_DBU_CMD_RX_ERROR_BITS 1 -#define DBU_DBU_CMD_RX_ERROR_SHIFT 1 - -/* DBU :: DBU_CMD :: ENABLE [00:00] */ -#define DBU_DBU_CMD_ENABLE_MASK 0x00000001 -#define DBU_DBU_CMD_ENABLE_ALIGN 0 -#define DBU_DBU_CMD_ENABLE_BITS 1 -#define DBU_DBU_CMD_ENABLE_SHIFT 0 - - -/**************************************************************************** - * DBU :: DBU_STATUS - ***************************************************************************/ -/* DBU :: DBU_STATUS :: reserved0 [31:02] */ -#define DBU_DBU_STATUS_reserved0_MASK 0xfffffffc -#define DBU_DBU_STATUS_reserved0_ALIGN 0 -#define DBU_DBU_STATUS_reserved0_BITS 30 -#define DBU_DBU_STATUS_reserved0_SHIFT 2 - -/* DBU :: DBU_STATUS :: TXDATA_OCCUPIED [01:01] */ -#define DBU_DBU_STATUS_TXDATA_OCCUPIED_MASK 0x00000002 -#define DBU_DBU_STATUS_TXDATA_OCCUPIED_ALIGN 0 -#define DBU_DBU_STATUS_TXDATA_OCCUPIED_BITS 1 -#define DBU_DBU_STATUS_TXDATA_OCCUPIED_SHIFT 1 - -/* DBU :: DBU_STATUS :: RXDATA_VALID [00:00] */ -#define DBU_DBU_STATUS_RXDATA_VALID_MASK 0x00000001 -#define DBU_DBU_STATUS_RXDATA_VALID_ALIGN 0 -#define DBU_DBU_STATUS_RXDATA_VALID_BITS 1 -#define DBU_DBU_STATUS_RXDATA_VALID_SHIFT 0 - - -/**************************************************************************** - * DBU :: DBU_CONFIG - ***************************************************************************/ -/* DBU :: DBU_CONFIG :: reserved0 [31:03] */ -#define DBU_DBU_CONFIG_reserved0_MASK 0xfffffff8 -#define DBU_DBU_CONFIG_reserved0_ALIGN 0 -#define DBU_DBU_CONFIG_reserved0_BITS 29 -#define DBU_DBU_CONFIG_reserved0_SHIFT 3 - -/* DBU :: DBU_CONFIG :: CRLF_ENABLE [02:02] */ -#define DBU_DBU_CONFIG_CRLF_ENABLE_MASK 0x00000004 -#define DBU_DBU_CONFIG_CRLF_ENABLE_ALIGN 0 -#define DBU_DBU_CONFIG_CRLF_ENABLE_BITS 1 -#define DBU_DBU_CONFIG_CRLF_ENABLE_SHIFT 2 - -/* DBU :: DBU_CONFIG :: DEBUGSM_ENABLE [01:01] */ -#define DBU_DBU_CONFIG_DEBUGSM_ENABLE_MASK 0x00000002 -#define DBU_DBU_CONFIG_DEBUGSM_ENABLE_ALIGN 0 -#define DBU_DBU_CONFIG_DEBUGSM_ENABLE_BITS 1 -#define DBU_DBU_CONFIG_DEBUGSM_ENABLE_SHIFT 1 - -/* DBU :: DBU_CONFIG :: TIMING_OVERRIDE [00:00] */ -#define DBU_DBU_CONFIG_TIMING_OVERRIDE_MASK 0x00000001 -#define DBU_DBU_CONFIG_TIMING_OVERRIDE_ALIGN 0 -#define DBU_DBU_CONFIG_TIMING_OVERRIDE_BITS 1 -#define DBU_DBU_CONFIG_TIMING_OVERRIDE_SHIFT 0 - - -/**************************************************************************** - * DBU :: DBU_TIMING - ***************************************************************************/ -/* DBU :: DBU_TIMING :: BIT_INTERVAL [31:16] */ -#define DBU_DBU_TIMING_BIT_INTERVAL_MASK 0xffff0000 -#define DBU_DBU_TIMING_BIT_INTERVAL_ALIGN 0 -#define DBU_DBU_TIMING_BIT_INTERVAL_BITS 16 -#define DBU_DBU_TIMING_BIT_INTERVAL_SHIFT 16 - -/* DBU :: DBU_TIMING :: FB_SMPL_OFFSET [15:00] */ -#define DBU_DBU_TIMING_FB_SMPL_OFFSET_MASK 0x0000ffff -#define DBU_DBU_TIMING_FB_SMPL_OFFSET_ALIGN 0 -#define DBU_DBU_TIMING_FB_SMPL_OFFSET_BITS 16 -#define DBU_DBU_TIMING_FB_SMPL_OFFSET_SHIFT 0 - - -/**************************************************************************** - * DBU :: DBU_RXDATA - ***************************************************************************/ -/* DBU :: DBU_RXDATA :: reserved0 [31:09] */ -#define DBU_DBU_RXDATA_reserved0_MASK 0xfffffe00 -#define DBU_DBU_RXDATA_reserved0_ALIGN 0 -#define DBU_DBU_RXDATA_reserved0_BITS 23 -#define DBU_DBU_RXDATA_reserved0_SHIFT 9 - -/* DBU :: DBU_RXDATA :: ERROR [08:08] */ -#define DBU_DBU_RXDATA_ERROR_MASK 0x00000100 -#define DBU_DBU_RXDATA_ERROR_ALIGN 0 -#define DBU_DBU_RXDATA_ERROR_BITS 1 -#define DBU_DBU_RXDATA_ERROR_SHIFT 8 - -/* DBU :: DBU_RXDATA :: VALUE [07:00] */ -#define DBU_DBU_RXDATA_VALUE_MASK 0x000000ff -#define DBU_DBU_RXDATA_VALUE_ALIGN 0 -#define DBU_DBU_RXDATA_VALUE_BITS 8 -#define DBU_DBU_RXDATA_VALUE_SHIFT 0 - - -/**************************************************************************** - * DBU :: DBU_TXDATA - ***************************************************************************/ -/* DBU :: DBU_TXDATA :: reserved0 [31:08] */ -#define DBU_DBU_TXDATA_reserved0_MASK 0xffffff00 -#define DBU_DBU_TXDATA_reserved0_ALIGN 0 -#define DBU_DBU_TXDATA_reserved0_BITS 24 -#define DBU_DBU_TXDATA_reserved0_SHIFT 8 - -/* DBU :: DBU_TXDATA :: VALUE [07:00] */ -#define DBU_DBU_TXDATA_VALUE_MASK 0x000000ff -#define DBU_DBU_TXDATA_VALUE_ALIGN 0 -#define DBU_DBU_TXDATA_VALUE_BITS 8 -#define DBU_DBU_TXDATA_VALUE_SHIFT 0 - - -/**************************************************************************** - * BCM70012_DBU_TOP_DBU_RGR_BRIDGE - ***************************************************************************/ -/**************************************************************************** - * DBU_RGR_BRIDGE :: REVISION - ***************************************************************************/ -/* DBU_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define DBU_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define DBU_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 -#define DBU_RGR_BRIDGE_REVISION_reserved0_BITS 16 -#define DBU_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* DBU_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define DBU_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define DBU_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 -#define DBU_RGR_BRIDGE_REVISION_MAJOR_BITS 8 -#define DBU_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* DBU_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define DBU_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define DBU_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 -#define DBU_RGR_BRIDGE_REVISION_MINOR_BITS 8 -#define DBU_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 - - -/**************************************************************************** - * DBU_RGR_BRIDGE :: CTRL - ***************************************************************************/ -/* DBU_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ -#define DBU_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc -#define DBU_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 -#define DBU_RGR_BRIDGE_CTRL_reserved0_BITS 30 -#define DBU_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 - -/* DBU_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ -#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 -#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 -#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 -#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 -#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 -#define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 - -/* DBU_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ -#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 -#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 -#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 -#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 -#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 - - -/**************************************************************************** - * DBU_RGR_BRIDGE :: RBUS_TIMER - ***************************************************************************/ -/* DBU_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ -#define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 -#define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 -#define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 -#define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 - -/* DBU_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ -#define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff -#define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 -#define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 -#define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 - - -/**************************************************************************** - * DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 - ***************************************************************************/ -/* DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 - -/* DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 - - -/**************************************************************************** - * DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 - ***************************************************************************/ -/* DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 - -/* DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 - - -/**************************************************************************** - * BCM70012_OTP_TOP_OTP - ***************************************************************************/ -/**************************************************************************** - * OTP :: CONFIG_INFO - ***************************************************************************/ -/* OTP :: CONFIG_INFO :: reserved0 [31:22] */ -#define OTP_CONFIG_INFO_reserved0_MASK 0xffc00000 -#define OTP_CONFIG_INFO_reserved0_ALIGN 0 -#define OTP_CONFIG_INFO_reserved0_BITS 10 -#define OTP_CONFIG_INFO_reserved0_SHIFT 22 - -/* OTP :: CONFIG_INFO :: SELVL [21:20] */ -#define OTP_CONFIG_INFO_SELVL_MASK 0x00300000 -#define OTP_CONFIG_INFO_SELVL_ALIGN 0 -#define OTP_CONFIG_INFO_SELVL_BITS 2 -#define OTP_CONFIG_INFO_SELVL_SHIFT 20 - -/* OTP :: CONFIG_INFO :: reserved1 [19:17] */ -#define OTP_CONFIG_INFO_reserved1_MASK 0x000e0000 -#define OTP_CONFIG_INFO_reserved1_ALIGN 0 -#define OTP_CONFIG_INFO_reserved1_BITS 3 -#define OTP_CONFIG_INFO_reserved1_SHIFT 17 - -/* OTP :: CONFIG_INFO :: PTEST [16:16] */ -#define OTP_CONFIG_INFO_PTEST_MASK 0x00010000 -#define OTP_CONFIG_INFO_PTEST_ALIGN 0 -#define OTP_CONFIG_INFO_PTEST_BITS 1 -#define OTP_CONFIG_INFO_PTEST_SHIFT 16 - -/* OTP :: CONFIG_INFO :: reserved2 [15:13] */ -#define OTP_CONFIG_INFO_reserved2_MASK 0x0000e000 -#define OTP_CONFIG_INFO_reserved2_ALIGN 0 -#define OTP_CONFIG_INFO_reserved2_BITS 3 -#define OTP_CONFIG_INFO_reserved2_SHIFT 13 - -/* OTP :: CONFIG_INFO :: MAX_REDUNDANT_ROWS [12:08] */ -#define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_MASK 0x00001f00 -#define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_ALIGN 0 -#define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_BITS 5 -#define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_SHIFT 8 - -/* OTP :: CONFIG_INFO :: MAX_RETRY [07:04] */ -#define OTP_CONFIG_INFO_MAX_RETRY_MASK 0x000000f0 -#define OTP_CONFIG_INFO_MAX_RETRY_ALIGN 0 -#define OTP_CONFIG_INFO_MAX_RETRY_BITS 4 -#define OTP_CONFIG_INFO_MAX_RETRY_SHIFT 4 - -/* OTP :: CONFIG_INFO :: reserved3 [03:01] */ -#define OTP_CONFIG_INFO_reserved3_MASK 0x0000000e -#define OTP_CONFIG_INFO_reserved3_ALIGN 0 -#define OTP_CONFIG_INFO_reserved3_BITS 3 -#define OTP_CONFIG_INFO_reserved3_SHIFT 1 - -/* OTP :: CONFIG_INFO :: PROG_MODE [00:00] */ -#define OTP_CONFIG_INFO_PROG_MODE_MASK 0x00000001 -#define OTP_CONFIG_INFO_PROG_MODE_ALIGN 0 -#define OTP_CONFIG_INFO_PROG_MODE_BITS 1 -#define OTP_CONFIG_INFO_PROG_MODE_SHIFT 0 - - -/**************************************************************************** - * OTP :: CMD - ***************************************************************************/ -/* OTP :: CMD :: reserved0 [31:02] */ -#define OTP_CMD_reserved0_MASK 0xfffffffc -#define OTP_CMD_reserved0_ALIGN 0 -#define OTP_CMD_reserved0_BITS 30 -#define OTP_CMD_reserved0_SHIFT 2 - -/* OTP :: CMD :: KEYS_AVAIL [01:01] */ -#define OTP_CMD_KEYS_AVAIL_MASK 0x00000002 -#define OTP_CMD_KEYS_AVAIL_ALIGN 0 -#define OTP_CMD_KEYS_AVAIL_BITS 1 -#define OTP_CMD_KEYS_AVAIL_SHIFT 1 - -/* OTP :: CMD :: PROGRAM_OTP [00:00] */ -#define OTP_CMD_PROGRAM_OTP_MASK 0x00000001 -#define OTP_CMD_PROGRAM_OTP_ALIGN 0 -#define OTP_CMD_PROGRAM_OTP_BITS 1 -#define OTP_CMD_PROGRAM_OTP_SHIFT 0 - - -/**************************************************************************** - * OTP :: STATUS - ***************************************************************************/ -/* OTP :: STATUS :: reserved0 [31:30] */ -#define OTP_STATUS_reserved0_MASK 0xc0000000 -#define OTP_STATUS_reserved0_ALIGN 0 -#define OTP_STATUS_reserved0_BITS 2 -#define OTP_STATUS_reserved0_SHIFT 30 - -/* OTP :: STATUS :: TOTAL_RETRIES [29:17] */ -#define OTP_STATUS_TOTAL_RETRIES_MASK 0x3ffe0000 -#define OTP_STATUS_TOTAL_RETRIES_ALIGN 0 -#define OTP_STATUS_TOTAL_RETRIES_BITS 13 -#define OTP_STATUS_TOTAL_RETRIES_SHIFT 17 - -/* OTP :: STATUS :: ROWS_USED [16:12] */ -#define OTP_STATUS_ROWS_USED_MASK 0x0001f000 -#define OTP_STATUS_ROWS_USED_ALIGN 0 -#define OTP_STATUS_ROWS_USED_BITS 5 -#define OTP_STATUS_ROWS_USED_SHIFT 12 - -/* OTP :: STATUS :: MAX_RETRIES [11:08] */ -#define OTP_STATUS_MAX_RETRIES_MASK 0x00000f00 -#define OTP_STATUS_MAX_RETRIES_ALIGN 0 -#define OTP_STATUS_MAX_RETRIES_BITS 4 -#define OTP_STATUS_MAX_RETRIES_SHIFT 8 - -/* OTP :: STATUS :: PROG_STATUS [07:04] */ -#define OTP_STATUS_PROG_STATUS_MASK 0x000000f0 -#define OTP_STATUS_PROG_STATUS_ALIGN 0 -#define OTP_STATUS_PROG_STATUS_BITS 4 -#define OTP_STATUS_PROG_STATUS_SHIFT 4 - -/* OTP :: STATUS :: reserved1 [03:03] */ -#define OTP_STATUS_reserved1_MASK 0x00000008 -#define OTP_STATUS_reserved1_ALIGN 0 -#define OTP_STATUS_reserved1_BITS 1 -#define OTP_STATUS_reserved1_SHIFT 3 - -/* OTP :: STATUS :: CHECKSUM_MISMATCH [02:02] */ -#define OTP_STATUS_CHECKSUM_MISMATCH_MASK 0x00000004 -#define OTP_STATUS_CHECKSUM_MISMATCH_ALIGN 0 -#define OTP_STATUS_CHECKSUM_MISMATCH_BITS 1 -#define OTP_STATUS_CHECKSUM_MISMATCH_SHIFT 2 - -/* OTP :: STATUS :: INSUFFICIENT_ROWS [01:01] */ -#define OTP_STATUS_INSUFFICIENT_ROWS_MASK 0x00000002 -#define OTP_STATUS_INSUFFICIENT_ROWS_ALIGN 0 -#define OTP_STATUS_INSUFFICIENT_ROWS_BITS 1 -#define OTP_STATUS_INSUFFICIENT_ROWS_SHIFT 1 - -/* OTP :: STATUS :: PROGRAMMED [00:00] */ -#define OTP_STATUS_PROGRAMMED_MASK 0x00000001 -#define OTP_STATUS_PROGRAMMED_ALIGN 0 -#define OTP_STATUS_PROGRAMMED_BITS 1 -#define OTP_STATUS_PROGRAMMED_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_MISC - ***************************************************************************/ -/* OTP :: CONTENT_MISC :: reserved0 [31:06] */ -#define OTP_CONTENT_MISC_reserved0_MASK 0xffffffc0 -#define OTP_CONTENT_MISC_reserved0_ALIGN 0 -#define OTP_CONTENT_MISC_reserved0_BITS 26 -#define OTP_CONTENT_MISC_reserved0_SHIFT 6 - -/* OTP :: CONTENT_MISC :: DCI_SECURITY_ENABLE [05:05] */ -#define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_MASK 0x00000020 -#define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_ALIGN 0 -#define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_BITS 1 -#define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_SHIFT 5 - -/* OTP :: CONTENT_MISC :: AES_SECURITY_ENABLE [04:04] */ -#define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_MASK 0x00000010 -#define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_ALIGN 0 -#define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_BITS 1 -#define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_SHIFT 4 - -/* OTP :: CONTENT_MISC :: DISABLE_JTAG [03:03] */ -#define OTP_CONTENT_MISC_DISABLE_JTAG_MASK 0x00000008 -#define OTP_CONTENT_MISC_DISABLE_JTAG_ALIGN 0 -#define OTP_CONTENT_MISC_DISABLE_JTAG_BITS 1 -#define OTP_CONTENT_MISC_DISABLE_JTAG_SHIFT 3 - -/* OTP :: CONTENT_MISC :: DISABLE_UART [02:02] */ -#define OTP_CONTENT_MISC_DISABLE_UART_MASK 0x00000004 -#define OTP_CONTENT_MISC_DISABLE_UART_ALIGN 0 -#define OTP_CONTENT_MISC_DISABLE_UART_BITS 1 -#define OTP_CONTENT_MISC_DISABLE_UART_SHIFT 2 - -/* OTP :: CONTENT_MISC :: ENABLE_RANDOMIZATION [01:01] */ -#define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_MASK 0x00000002 -#define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_ALIGN 0 -#define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_BITS 1 -#define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_SHIFT 1 - -/* OTP :: CONTENT_MISC :: OTP_SECURITY_ENABLE [00:00] */ -#define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_MASK 0x00000001 -#define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_ALIGN 0 -#define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_BITS 1 -#define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_AES_0 - ***************************************************************************/ -/* OTP :: CONTENT_AES_0 :: AES_KEY_0 [31:00] */ -#define OTP_CONTENT_AES_0_AES_KEY_0_MASK 0xffffffff -#define OTP_CONTENT_AES_0_AES_KEY_0_ALIGN 0 -#define OTP_CONTENT_AES_0_AES_KEY_0_BITS 32 -#define OTP_CONTENT_AES_0_AES_KEY_0_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_AES_1 - ***************************************************************************/ -/* OTP :: CONTENT_AES_1 :: AES_KEY_1 [31:00] */ -#define OTP_CONTENT_AES_1_AES_KEY_1_MASK 0xffffffff -#define OTP_CONTENT_AES_1_AES_KEY_1_ALIGN 0 -#define OTP_CONTENT_AES_1_AES_KEY_1_BITS 32 -#define OTP_CONTENT_AES_1_AES_KEY_1_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_AES_2 - ***************************************************************************/ -/* OTP :: CONTENT_AES_2 :: AES_KEY_2 [31:00] */ -#define OTP_CONTENT_AES_2_AES_KEY_2_MASK 0xffffffff -#define OTP_CONTENT_AES_2_AES_KEY_2_ALIGN 0 -#define OTP_CONTENT_AES_2_AES_KEY_2_BITS 32 -#define OTP_CONTENT_AES_2_AES_KEY_2_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_AES_3 - ***************************************************************************/ -/* OTP :: CONTENT_AES_3 :: AES_KEY_3 [31:00] */ -#define OTP_CONTENT_AES_3_AES_KEY_3_MASK 0xffffffff -#define OTP_CONTENT_AES_3_AES_KEY_3_ALIGN 0 -#define OTP_CONTENT_AES_3_AES_KEY_3_BITS 32 -#define OTP_CONTENT_AES_3_AES_KEY_3_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_SHA_0 - ***************************************************************************/ -/* OTP :: CONTENT_SHA_0 :: SHA_KEY_0 [31:00] */ -#define OTP_CONTENT_SHA_0_SHA_KEY_0_MASK 0xffffffff -#define OTP_CONTENT_SHA_0_SHA_KEY_0_ALIGN 0 -#define OTP_CONTENT_SHA_0_SHA_KEY_0_BITS 32 -#define OTP_CONTENT_SHA_0_SHA_KEY_0_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_SHA_1 - ***************************************************************************/ -/* OTP :: CONTENT_SHA_1 :: SHA_KEY_1 [31:00] */ -#define OTP_CONTENT_SHA_1_SHA_KEY_1_MASK 0xffffffff -#define OTP_CONTENT_SHA_1_SHA_KEY_1_ALIGN 0 -#define OTP_CONTENT_SHA_1_SHA_KEY_1_BITS 32 -#define OTP_CONTENT_SHA_1_SHA_KEY_1_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_SHA_2 - ***************************************************************************/ -/* OTP :: CONTENT_SHA_2 :: SHA_KEY_2 [31:00] */ -#define OTP_CONTENT_SHA_2_SHA_KEY_2_MASK 0xffffffff -#define OTP_CONTENT_SHA_2_SHA_KEY_2_ALIGN 0 -#define OTP_CONTENT_SHA_2_SHA_KEY_2_BITS 32 -#define OTP_CONTENT_SHA_2_SHA_KEY_2_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_SHA_3 - ***************************************************************************/ -/* OTP :: CONTENT_SHA_3 :: SHA_KEY_3 [31:00] */ -#define OTP_CONTENT_SHA_3_SHA_KEY_3_MASK 0xffffffff -#define OTP_CONTENT_SHA_3_SHA_KEY_3_ALIGN 0 -#define OTP_CONTENT_SHA_3_SHA_KEY_3_BITS 32 -#define OTP_CONTENT_SHA_3_SHA_KEY_3_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_SHA_4 - ***************************************************************************/ -/* OTP :: CONTENT_SHA_4 :: SHA_KEY_4 [31:00] */ -#define OTP_CONTENT_SHA_4_SHA_KEY_4_MASK 0xffffffff -#define OTP_CONTENT_SHA_4_SHA_KEY_4_ALIGN 0 -#define OTP_CONTENT_SHA_4_SHA_KEY_4_BITS 32 -#define OTP_CONTENT_SHA_4_SHA_KEY_4_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_SHA_5 - ***************************************************************************/ -/* OTP :: CONTENT_SHA_5 :: SHA_KEY_5 [31:00] */ -#define OTP_CONTENT_SHA_5_SHA_KEY_5_MASK 0xffffffff -#define OTP_CONTENT_SHA_5_SHA_KEY_5_ALIGN 0 -#define OTP_CONTENT_SHA_5_SHA_KEY_5_BITS 32 -#define OTP_CONTENT_SHA_5_SHA_KEY_5_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_SHA_6 - ***************************************************************************/ -/* OTP :: CONTENT_SHA_6 :: SHA_KEY_6 [31:00] */ -#define OTP_CONTENT_SHA_6_SHA_KEY_6_MASK 0xffffffff -#define OTP_CONTENT_SHA_6_SHA_KEY_6_ALIGN 0 -#define OTP_CONTENT_SHA_6_SHA_KEY_6_BITS 32 -#define OTP_CONTENT_SHA_6_SHA_KEY_6_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_SHA_7 - ***************************************************************************/ -/* OTP :: CONTENT_SHA_7 :: SHA_KEY_7 [31:00] */ -#define OTP_CONTENT_SHA_7_SHA_KEY_7_MASK 0xffffffff -#define OTP_CONTENT_SHA_7_SHA_KEY_7_ALIGN 0 -#define OTP_CONTENT_SHA_7_SHA_KEY_7_BITS 32 -#define OTP_CONTENT_SHA_7_SHA_KEY_7_SHIFT 0 - - -/**************************************************************************** - * OTP :: CONTENT_CHECKSUM - ***************************************************************************/ -/* OTP :: CONTENT_CHECKSUM :: reserved0 [31:16] */ -#define OTP_CONTENT_CHECKSUM_reserved0_MASK 0xffff0000 -#define OTP_CONTENT_CHECKSUM_reserved0_ALIGN 0 -#define OTP_CONTENT_CHECKSUM_reserved0_BITS 16 -#define OTP_CONTENT_CHECKSUM_reserved0_SHIFT 16 - -/* OTP :: CONTENT_CHECKSUM :: CHECKSUM [15:00] */ -#define OTP_CONTENT_CHECKSUM_CHECKSUM_MASK 0x0000ffff -#define OTP_CONTENT_CHECKSUM_CHECKSUM_ALIGN 0 -#define OTP_CONTENT_CHECKSUM_CHECKSUM_BITS 16 -#define OTP_CONTENT_CHECKSUM_CHECKSUM_SHIFT 0 - - -/**************************************************************************** - * OTP :: PROG_CTRL - ***************************************************************************/ -/* OTP :: PROG_CTRL :: reserved0 [31:02] */ -#define OTP_PROG_CTRL_reserved0_MASK 0xfffffffc -#define OTP_PROG_CTRL_reserved0_ALIGN 0 -#define OTP_PROG_CTRL_reserved0_BITS 30 -#define OTP_PROG_CTRL_reserved0_SHIFT 2 - -/* OTP :: PROG_CTRL :: ENABLE [01:01] */ -#define OTP_PROG_CTRL_ENABLE_MASK 0x00000002 -#define OTP_PROG_CTRL_ENABLE_ALIGN 0 -#define OTP_PROG_CTRL_ENABLE_BITS 1 -#define OTP_PROG_CTRL_ENABLE_SHIFT 1 - -/* OTP :: PROG_CTRL :: RST [00:00] */ -#define OTP_PROG_CTRL_RST_MASK 0x00000001 -#define OTP_PROG_CTRL_RST_ALIGN 0 -#define OTP_PROG_CTRL_RST_BITS 1 -#define OTP_PROG_CTRL_RST_SHIFT 0 - - -/**************************************************************************** - * OTP :: PROG_STATUS - ***************************************************************************/ -/* OTP :: PROG_STATUS :: reserved0 [31:02] */ -#define OTP_PROG_STATUS_reserved0_MASK 0xfffffffc -#define OTP_PROG_STATUS_reserved0_ALIGN 0 -#define OTP_PROG_STATUS_reserved0_BITS 30 -#define OTP_PROG_STATUS_reserved0_SHIFT 2 - -/* OTP :: PROG_STATUS :: ORDY [01:01] */ -#define OTP_PROG_STATUS_ORDY_MASK 0x00000002 -#define OTP_PROG_STATUS_ORDY_ALIGN 0 -#define OTP_PROG_STATUS_ORDY_BITS 1 -#define OTP_PROG_STATUS_ORDY_SHIFT 1 - -/* OTP :: PROG_STATUS :: IRDY [00:00] */ -#define OTP_PROG_STATUS_IRDY_MASK 0x00000001 -#define OTP_PROG_STATUS_IRDY_ALIGN 0 -#define OTP_PROG_STATUS_IRDY_BITS 1 -#define OTP_PROG_STATUS_IRDY_SHIFT 0 - - -/**************************************************************************** - * OTP :: PROG_PULSE - ***************************************************************************/ -/* OTP :: PROG_PULSE :: PROG_HI [31:00] */ -#define OTP_PROG_PULSE_PROG_HI_MASK 0xffffffff -#define OTP_PROG_PULSE_PROG_HI_ALIGN 0 -#define OTP_PROG_PULSE_PROG_HI_BITS 32 -#define OTP_PROG_PULSE_PROG_HI_SHIFT 0 - - -/**************************************************************************** - * OTP :: VERIFY_PULSE - ***************************************************************************/ -/* OTP :: VERIFY_PULSE :: PROG_LOW [31:16] */ -#define OTP_VERIFY_PULSE_PROG_LOW_MASK 0xffff0000 -#define OTP_VERIFY_PULSE_PROG_LOW_ALIGN 0 -#define OTP_VERIFY_PULSE_PROG_LOW_BITS 16 -#define OTP_VERIFY_PULSE_PROG_LOW_SHIFT 16 - -/* OTP :: VERIFY_PULSE :: VERIFY [15:00] */ -#define OTP_VERIFY_PULSE_VERIFY_MASK 0x0000ffff -#define OTP_VERIFY_PULSE_VERIFY_ALIGN 0 -#define OTP_VERIFY_PULSE_VERIFY_BITS 16 -#define OTP_VERIFY_PULSE_VERIFY_SHIFT 0 - - -/**************************************************************************** - * OTP :: PROG_MASK - ***************************************************************************/ -/* OTP :: PROG_MASK :: reserved0 [31:17] */ -#define OTP_PROG_MASK_reserved0_MASK 0xfffe0000 -#define OTP_PROG_MASK_reserved0_ALIGN 0 -#define OTP_PROG_MASK_reserved0_BITS 15 -#define OTP_PROG_MASK_reserved0_SHIFT 17 - -/* OTP :: PROG_MASK :: PROG_MASK [16:00] */ -#define OTP_PROG_MASK_PROG_MASK_MASK 0x0001ffff -#define OTP_PROG_MASK_PROG_MASK_ALIGN 0 -#define OTP_PROG_MASK_PROG_MASK_BITS 17 -#define OTP_PROG_MASK_PROG_MASK_SHIFT 0 - - -/**************************************************************************** - * OTP :: DATA_INPUT - ***************************************************************************/ -/* OTP :: DATA_INPUT :: reserved0 [31:31] */ -#define OTP_DATA_INPUT_reserved0_MASK 0x80000000 -#define OTP_DATA_INPUT_reserved0_ALIGN 0 -#define OTP_DATA_INPUT_reserved0_BITS 1 -#define OTP_DATA_INPUT_reserved0_SHIFT 31 - -/* OTP :: DATA_INPUT :: CMD [30:28] */ -#define OTP_DATA_INPUT_CMD_MASK 0x70000000 -#define OTP_DATA_INPUT_CMD_ALIGN 0 -#define OTP_DATA_INPUT_CMD_BITS 3 -#define OTP_DATA_INPUT_CMD_SHIFT 28 - -/* OTP :: DATA_INPUT :: reserved1 [27:26] */ -#define OTP_DATA_INPUT_reserved1_MASK 0x0c000000 -#define OTP_DATA_INPUT_reserved1_ALIGN 0 -#define OTP_DATA_INPUT_reserved1_BITS 2 -#define OTP_DATA_INPUT_reserved1_SHIFT 26 - -/* OTP :: DATA_INPUT :: ADDR [25:20] */ -#define OTP_DATA_INPUT_ADDR_MASK 0x03f00000 -#define OTP_DATA_INPUT_ADDR_ALIGN 0 -#define OTP_DATA_INPUT_ADDR_BITS 6 -#define OTP_DATA_INPUT_ADDR_SHIFT 20 - -/* OTP :: DATA_INPUT :: reserved2 [19:18] */ -#define OTP_DATA_INPUT_reserved2_MASK 0x000c0000 -#define OTP_DATA_INPUT_reserved2_ALIGN 0 -#define OTP_DATA_INPUT_reserved2_BITS 2 -#define OTP_DATA_INPUT_reserved2_SHIFT 18 - -/* OTP :: DATA_INPUT :: WRCOL [17:17] */ -#define OTP_DATA_INPUT_WRCOL_MASK 0x00020000 -#define OTP_DATA_INPUT_WRCOL_ALIGN 0 -#define OTP_DATA_INPUT_WRCOL_BITS 1 -#define OTP_DATA_INPUT_WRCOL_SHIFT 17 - -/* OTP :: DATA_INPUT :: DIN [16:00] */ -#define OTP_DATA_INPUT_DIN_MASK 0x0001ffff -#define OTP_DATA_INPUT_DIN_ALIGN 0 -#define OTP_DATA_INPUT_DIN_BITS 17 -#define OTP_DATA_INPUT_DIN_SHIFT 0 - - -/**************************************************************************** - * OTP :: DATA_OUTPUT - ***************************************************************************/ -/* OTP :: DATA_OUTPUT :: reserved0 [31:17] */ -#define OTP_DATA_OUTPUT_reserved0_MASK 0xfffe0000 -#define OTP_DATA_OUTPUT_reserved0_ALIGN 0 -#define OTP_DATA_OUTPUT_reserved0_BITS 15 -#define OTP_DATA_OUTPUT_reserved0_SHIFT 17 - -/* OTP :: DATA_OUTPUT :: DOUT [16:00] */ -#define OTP_DATA_OUTPUT_DOUT_MASK 0x0001ffff -#define OTP_DATA_OUTPUT_DOUT_ALIGN 0 -#define OTP_DATA_OUTPUT_DOUT_BITS 17 -#define OTP_DATA_OUTPUT_DOUT_SHIFT 0 - - -/**************************************************************************** - * BCM70012_OTP_TOP_OTP_GR_BRIDGE - ***************************************************************************/ -/**************************************************************************** - * OTP_GR_BRIDGE :: REVISION - ***************************************************************************/ -/* OTP_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define OTP_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define OTP_GR_BRIDGE_REVISION_reserved0_ALIGN 0 -#define OTP_GR_BRIDGE_REVISION_reserved0_BITS 16 -#define OTP_GR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* OTP_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define OTP_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define OTP_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 -#define OTP_GR_BRIDGE_REVISION_MAJOR_BITS 8 -#define OTP_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* OTP_GR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define OTP_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define OTP_GR_BRIDGE_REVISION_MINOR_ALIGN 0 -#define OTP_GR_BRIDGE_REVISION_MINOR_BITS 8 -#define OTP_GR_BRIDGE_REVISION_MINOR_SHIFT 0 - - -/**************************************************************************** - * OTP_GR_BRIDGE :: CTRL - ***************************************************************************/ -/* OTP_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ -#define OTP_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe -#define OTP_GR_BRIDGE_CTRL_reserved0_ALIGN 0 -#define OTP_GR_BRIDGE_CTRL_reserved0_BITS 31 -#define OTP_GR_BRIDGE_CTRL_reserved0_SHIFT 1 - -/* OTP_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ -#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 -#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 -#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 -#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 -#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define OTP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 - - -/**************************************************************************** - * OTP_GR_BRIDGE :: SPARE_SW_RESET_0 - ***************************************************************************/ -/* OTP_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 - -/* OTP_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 - - -/**************************************************************************** - * OTP_GR_BRIDGE :: SPARE_SW_RESET_1 - ***************************************************************************/ -/* OTP_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 - -/* OTP_GR_BRIDGE :: SPARE_SW_RESET_1 :: OTP_00_SW_RESET [00:00] */ -#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_MASK 0x00000001 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_ALIGN 0 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_BITS 1 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_SHIFT 0 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_DEASSERT 0 -#define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_ASSERT 1 - - -/**************************************************************************** - * BCM70012_AES_TOP_AES - ***************************************************************************/ -/**************************************************************************** - * AES :: CONFIG_INFO - ***************************************************************************/ -/* AES :: CONFIG_INFO :: SWAP [31:31] */ -#define AES_CONFIG_INFO_SWAP_MASK 0x80000000 -#define AES_CONFIG_INFO_SWAP_ALIGN 0 -#define AES_CONFIG_INFO_SWAP_BITS 1 -#define AES_CONFIG_INFO_SWAP_SHIFT 31 - -/* AES :: CONFIG_INFO :: reserved0 [30:19] */ -#define AES_CONFIG_INFO_reserved0_MASK 0x7ff80000 -#define AES_CONFIG_INFO_reserved0_ALIGN 0 -#define AES_CONFIG_INFO_reserved0_BITS 12 -#define AES_CONFIG_INFO_reserved0_SHIFT 19 - -/* AES :: CONFIG_INFO :: OFFSET [18:02] */ -#define AES_CONFIG_INFO_OFFSET_MASK 0x0007fffc -#define AES_CONFIG_INFO_OFFSET_ALIGN 0 -#define AES_CONFIG_INFO_OFFSET_BITS 17 -#define AES_CONFIG_INFO_OFFSET_SHIFT 2 - -/* AES :: CONFIG_INFO :: reserved1 [01:00] */ -#define AES_CONFIG_INFO_reserved1_MASK 0x00000003 -#define AES_CONFIG_INFO_reserved1_ALIGN 0 -#define AES_CONFIG_INFO_reserved1_BITS 2 -#define AES_CONFIG_INFO_reserved1_SHIFT 0 - - -/**************************************************************************** - * AES :: CMD - ***************************************************************************/ -/* AES :: CMD :: reserved0 [31:13] */ -#define AES_CMD_reserved0_MASK 0xffffe000 -#define AES_CMD_reserved0_ALIGN 0 -#define AES_CMD_reserved0_BITS 19 -#define AES_CMD_reserved0_SHIFT 13 - -/* AES :: CMD :: WRITE_EEPROM [12:12] */ -#define AES_CMD_WRITE_EEPROM_MASK 0x00001000 -#define AES_CMD_WRITE_EEPROM_ALIGN 0 -#define AES_CMD_WRITE_EEPROM_BITS 1 -#define AES_CMD_WRITE_EEPROM_SHIFT 12 - -/* AES :: CMD :: reserved1 [11:09] */ -#define AES_CMD_reserved1_MASK 0x00000e00 -#define AES_CMD_reserved1_ALIGN 0 -#define AES_CMD_reserved1_BITS 3 -#define AES_CMD_reserved1_SHIFT 9 - -/* AES :: CMD :: START_EEPROM_COPY [08:08] */ -#define AES_CMD_START_EEPROM_COPY_MASK 0x00000100 -#define AES_CMD_START_EEPROM_COPY_ALIGN 0 -#define AES_CMD_START_EEPROM_COPY_BITS 1 -#define AES_CMD_START_EEPROM_COPY_SHIFT 8 - -/* AES :: CMD :: reserved2 [07:05] */ -#define AES_CMD_reserved2_MASK 0x000000e0 -#define AES_CMD_reserved2_ALIGN 0 -#define AES_CMD_reserved2_BITS 3 -#define AES_CMD_reserved2_SHIFT 5 - -/* AES :: CMD :: PREPARE_ENCRYPTION [04:04] */ -#define AES_CMD_PREPARE_ENCRYPTION_MASK 0x00000010 -#define AES_CMD_PREPARE_ENCRYPTION_ALIGN 0 -#define AES_CMD_PREPARE_ENCRYPTION_BITS 1 -#define AES_CMD_PREPARE_ENCRYPTION_SHIFT 4 - -/* AES :: CMD :: reserved3 [03:01] */ -#define AES_CMD_reserved3_MASK 0x0000000e -#define AES_CMD_reserved3_ALIGN 0 -#define AES_CMD_reserved3_BITS 3 -#define AES_CMD_reserved3_SHIFT 1 - -/* AES :: CMD :: START_KEY_LOAD [00:00] */ -#define AES_CMD_START_KEY_LOAD_MASK 0x00000001 -#define AES_CMD_START_KEY_LOAD_ALIGN 0 -#define AES_CMD_START_KEY_LOAD_BITS 1 -#define AES_CMD_START_KEY_LOAD_SHIFT 0 - - -/**************************************************************************** - * AES :: STATUS - ***************************************************************************/ -/* AES :: STATUS :: reserved0 [31:23] */ -#define AES_STATUS_reserved0_MASK 0xff800000 -#define AES_STATUS_reserved0_ALIGN 0 -#define AES_STATUS_reserved0_BITS 9 -#define AES_STATUS_reserved0_SHIFT 23 - -/* AES :: STATUS :: STUCK_AT_ZERO [22:22] */ -#define AES_STATUS_STUCK_AT_ZERO_MASK 0x00400000 -#define AES_STATUS_STUCK_AT_ZERO_ALIGN 0 -#define AES_STATUS_STUCK_AT_ZERO_BITS 1 -#define AES_STATUS_STUCK_AT_ZERO_SHIFT 22 - -/* AES :: STATUS :: STUCK_AT_ONE [21:21] */ -#define AES_STATUS_STUCK_AT_ONE_MASK 0x00200000 -#define AES_STATUS_STUCK_AT_ONE_ALIGN 0 -#define AES_STATUS_STUCK_AT_ONE_BITS 1 -#define AES_STATUS_STUCK_AT_ONE_SHIFT 21 - -/* AES :: STATUS :: RANDOM_READY [20:20] */ -#define AES_STATUS_RANDOM_READY_MASK 0x00100000 -#define AES_STATUS_RANDOM_READY_ALIGN 0 -#define AES_STATUS_RANDOM_READY_BITS 1 -#define AES_STATUS_RANDOM_READY_SHIFT 20 - -/* AES :: STATUS :: reserved1 [19:16] */ -#define AES_STATUS_reserved1_MASK 0x000f0000 -#define AES_STATUS_reserved1_ALIGN 0 -#define AES_STATUS_reserved1_BITS 4 -#define AES_STATUS_reserved1_SHIFT 16 - -/* AES :: STATUS :: WRITE_EEPROM_TIMEOUT [15:15] */ -#define AES_STATUS_WRITE_EEPROM_TIMEOUT_MASK 0x00008000 -#define AES_STATUS_WRITE_EEPROM_TIMEOUT_ALIGN 0 -#define AES_STATUS_WRITE_EEPROM_TIMEOUT_BITS 1 -#define AES_STATUS_WRITE_EEPROM_TIMEOUT_SHIFT 15 - -/* AES :: STATUS :: WRITE_DATA_MISMATCH [14:14] */ -#define AES_STATUS_WRITE_DATA_MISMATCH_MASK 0x00004000 -#define AES_STATUS_WRITE_DATA_MISMATCH_ALIGN 0 -#define AES_STATUS_WRITE_DATA_MISMATCH_BITS 1 -#define AES_STATUS_WRITE_DATA_MISMATCH_SHIFT 14 - -/* AES :: STATUS :: WRITE_GISB_ERROR [13:13] */ -#define AES_STATUS_WRITE_GISB_ERROR_MASK 0x00002000 -#define AES_STATUS_WRITE_GISB_ERROR_ALIGN 0 -#define AES_STATUS_WRITE_GISB_ERROR_BITS 1 -#define AES_STATUS_WRITE_GISB_ERROR_SHIFT 13 - -/* AES :: STATUS :: WRITE_DONE [12:12] */ -#define AES_STATUS_WRITE_DONE_MASK 0x00001000 -#define AES_STATUS_WRITE_DONE_ALIGN 0 -#define AES_STATUS_WRITE_DONE_BITS 1 -#define AES_STATUS_WRITE_DONE_SHIFT 12 - -/* AES :: STATUS :: reserved2 [11:11] */ -#define AES_STATUS_reserved2_MASK 0x00000800 -#define AES_STATUS_reserved2_ALIGN 0 -#define AES_STATUS_reserved2_BITS 1 -#define AES_STATUS_reserved2_SHIFT 11 - -/* AES :: STATUS :: COPY_EEPROM_ERROR [10:10] */ -#define AES_STATUS_COPY_EEPROM_ERROR_MASK 0x00000400 -#define AES_STATUS_COPY_EEPROM_ERROR_ALIGN 0 -#define AES_STATUS_COPY_EEPROM_ERROR_BITS 1 -#define AES_STATUS_COPY_EEPROM_ERROR_SHIFT 10 - -/* AES :: STATUS :: COPY_GISB_ERROR [09:09] */ -#define AES_STATUS_COPY_GISB_ERROR_MASK 0x00000200 -#define AES_STATUS_COPY_GISB_ERROR_ALIGN 0 -#define AES_STATUS_COPY_GISB_ERROR_BITS 1 -#define AES_STATUS_COPY_GISB_ERROR_SHIFT 9 - -/* AES :: STATUS :: COPY_DONE [08:08] */ -#define AES_STATUS_COPY_DONE_MASK 0x00000100 -#define AES_STATUS_COPY_DONE_ALIGN 0 -#define AES_STATUS_COPY_DONE_BITS 1 -#define AES_STATUS_COPY_DONE_SHIFT 8 - -/* AES :: STATUS :: PREPARE_EEPROM_TIMEOUT [07:07] */ -#define AES_STATUS_PREPARE_EEPROM_TIMEOUT_MASK 0x00000080 -#define AES_STATUS_PREPARE_EEPROM_TIMEOUT_ALIGN 0 -#define AES_STATUS_PREPARE_EEPROM_TIMEOUT_BITS 1 -#define AES_STATUS_PREPARE_EEPROM_TIMEOUT_SHIFT 7 - -/* AES :: STATUS :: PREPARE_DATA_MISMATCH [06:06] */ -#define AES_STATUS_PREPARE_DATA_MISMATCH_MASK 0x00000040 -#define AES_STATUS_PREPARE_DATA_MISMATCH_ALIGN 0 -#define AES_STATUS_PREPARE_DATA_MISMATCH_BITS 1 -#define AES_STATUS_PREPARE_DATA_MISMATCH_SHIFT 6 - -/* AES :: STATUS :: PREPARE_GISB_ERROR [05:05] */ -#define AES_STATUS_PREPARE_GISB_ERROR_MASK 0x00000020 -#define AES_STATUS_PREPARE_GISB_ERROR_ALIGN 0 -#define AES_STATUS_PREPARE_GISB_ERROR_BITS 1 -#define AES_STATUS_PREPARE_GISB_ERROR_SHIFT 5 - -/* AES :: STATUS :: PREPARE_DONE [04:04] */ -#define AES_STATUS_PREPARE_DONE_MASK 0x00000010 -#define AES_STATUS_PREPARE_DONE_ALIGN 0 -#define AES_STATUS_PREPARE_DONE_BITS 1 -#define AES_STATUS_PREPARE_DONE_SHIFT 4 - -/* AES :: STATUS :: reserved3 [03:02] */ -#define AES_STATUS_reserved3_MASK 0x0000000c -#define AES_STATUS_reserved3_ALIGN 0 -#define AES_STATUS_reserved3_BITS 2 -#define AES_STATUS_reserved3_SHIFT 2 - -/* AES :: STATUS :: KEY_LOAD_GISB_ERROR [01:01] */ -#define AES_STATUS_KEY_LOAD_GISB_ERROR_MASK 0x00000002 -#define AES_STATUS_KEY_LOAD_GISB_ERROR_ALIGN 0 -#define AES_STATUS_KEY_LOAD_GISB_ERROR_BITS 1 -#define AES_STATUS_KEY_LOAD_GISB_ERROR_SHIFT 1 - -/* AES :: STATUS :: KEY_LOAD_DONE [00:00] */ -#define AES_STATUS_KEY_LOAD_DONE_MASK 0x00000001 -#define AES_STATUS_KEY_LOAD_DONE_ALIGN 0 -#define AES_STATUS_KEY_LOAD_DONE_BITS 1 -#define AES_STATUS_KEY_LOAD_DONE_SHIFT 0 - - -/**************************************************************************** - * AES :: EEPROM_CONFIG - ***************************************************************************/ -/* AES :: EEPROM_CONFIG :: LENGTH [31:20] */ -#define AES_EEPROM_CONFIG_LENGTH_MASK 0xfff00000 -#define AES_EEPROM_CONFIG_LENGTH_ALIGN 0 -#define AES_EEPROM_CONFIG_LENGTH_BITS 12 -#define AES_EEPROM_CONFIG_LENGTH_SHIFT 20 - -/* AES :: EEPROM_CONFIG :: reserved0 [19:16] */ -#define AES_EEPROM_CONFIG_reserved0_MASK 0x000f0000 -#define AES_EEPROM_CONFIG_reserved0_ALIGN 0 -#define AES_EEPROM_CONFIG_reserved0_BITS 4 -#define AES_EEPROM_CONFIG_reserved0_SHIFT 16 - -/* AES :: EEPROM_CONFIG :: START_ADDR [15:02] */ -#define AES_EEPROM_CONFIG_START_ADDR_MASK 0x0000fffc -#define AES_EEPROM_CONFIG_START_ADDR_ALIGN 0 -#define AES_EEPROM_CONFIG_START_ADDR_BITS 14 -#define AES_EEPROM_CONFIG_START_ADDR_SHIFT 2 - -/* AES :: EEPROM_CONFIG :: reserved1 [01:00] */ -#define AES_EEPROM_CONFIG_reserved1_MASK 0x00000003 -#define AES_EEPROM_CONFIG_reserved1_ALIGN 0 -#define AES_EEPROM_CONFIG_reserved1_BITS 2 -#define AES_EEPROM_CONFIG_reserved1_SHIFT 0 - - -/**************************************************************************** - * AES :: EEPROM_DATA_0 - ***************************************************************************/ -/* AES :: EEPROM_DATA_0 :: DATA [31:00] */ -#define AES_EEPROM_DATA_0_DATA_MASK 0xffffffff -#define AES_EEPROM_DATA_0_DATA_ALIGN 0 -#define AES_EEPROM_DATA_0_DATA_BITS 32 -#define AES_EEPROM_DATA_0_DATA_SHIFT 0 - - -/**************************************************************************** - * AES :: EEPROM_DATA_1 - ***************************************************************************/ -/* AES :: EEPROM_DATA_1 :: DATA [31:00] */ -#define AES_EEPROM_DATA_1_DATA_MASK 0xffffffff -#define AES_EEPROM_DATA_1_DATA_ALIGN 0 -#define AES_EEPROM_DATA_1_DATA_BITS 32 -#define AES_EEPROM_DATA_1_DATA_SHIFT 0 - - -/**************************************************************************** - * AES :: EEPROM_DATA_2 - ***************************************************************************/ -/* AES :: EEPROM_DATA_2 :: DATA [31:00] */ -#define AES_EEPROM_DATA_2_DATA_MASK 0xffffffff -#define AES_EEPROM_DATA_2_DATA_ALIGN 0 -#define AES_EEPROM_DATA_2_DATA_BITS 32 -#define AES_EEPROM_DATA_2_DATA_SHIFT 0 - - -/**************************************************************************** - * AES :: EEPROM_DATA_3 - ***************************************************************************/ -/* AES :: EEPROM_DATA_3 :: DATA [31:00] */ -#define AES_EEPROM_DATA_3_DATA_MASK 0xffffffff -#define AES_EEPROM_DATA_3_DATA_ALIGN 0 -#define AES_EEPROM_DATA_3_DATA_BITS 32 -#define AES_EEPROM_DATA_3_DATA_SHIFT 0 - - -/**************************************************************************** - * BCM70012_AES_TOP_AES_RGR_BRIDGE - ***************************************************************************/ -/**************************************************************************** - * AES_RGR_BRIDGE :: REVISION - ***************************************************************************/ -/* AES_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define AES_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define AES_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 -#define AES_RGR_BRIDGE_REVISION_reserved0_BITS 16 -#define AES_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* AES_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define AES_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define AES_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 -#define AES_RGR_BRIDGE_REVISION_MAJOR_BITS 8 -#define AES_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* AES_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define AES_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define AES_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 -#define AES_RGR_BRIDGE_REVISION_MINOR_BITS 8 -#define AES_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 - - -/**************************************************************************** - * AES_RGR_BRIDGE :: CTRL - ***************************************************************************/ -/* AES_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ -#define AES_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc -#define AES_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 -#define AES_RGR_BRIDGE_CTRL_reserved0_BITS 30 -#define AES_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 - -/* AES_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ -#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 -#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 -#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 -#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 -#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 -#define AES_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 - -/* AES_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ -#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 -#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 -#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 -#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 -#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define AES_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 - - -/**************************************************************************** - * AES_RGR_BRIDGE :: RBUS_TIMER - ***************************************************************************/ -/* AES_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ -#define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 -#define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 -#define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 -#define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 - -/* AES_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ -#define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff -#define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 -#define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 -#define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 - - -/**************************************************************************** - * AES_RGR_BRIDGE :: SPARE_SW_RESET_0 - ***************************************************************************/ -/* AES_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 - -/* AES_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 - - -/**************************************************************************** - * AES_RGR_BRIDGE :: SPARE_SW_RESET_1 - ***************************************************************************/ -/* AES_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 - -/* AES_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 -#define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 - - -/**************************************************************************** - * BCM70012_DCI_TOP_DCI - ***************************************************************************/ -/**************************************************************************** - * DCI :: CMD - ***************************************************************************/ -/* DCI :: CMD :: reserved0 [31:09] */ -#define DCI_CMD_reserved0_MASK 0xfffffe00 -#define DCI_CMD_reserved0_ALIGN 0 -#define DCI_CMD_reserved0_BITS 23 -#define DCI_CMD_reserved0_SHIFT 9 - -/* DCI :: CMD :: FORCE_FW_VALIDATED [08:08] */ -#define DCI_CMD_FORCE_FW_VALIDATED_MASK 0x00000100 -#define DCI_CMD_FORCE_FW_VALIDATED_ALIGN 0 -#define DCI_CMD_FORCE_FW_VALIDATED_BITS 1 -#define DCI_CMD_FORCE_FW_VALIDATED_SHIFT 8 - -/* DCI :: CMD :: reserved1 [07:05] */ -#define DCI_CMD_reserved1_MASK 0x000000e0 -#define DCI_CMD_reserved1_ALIGN 0 -#define DCI_CMD_reserved1_BITS 3 -#define DCI_CMD_reserved1_SHIFT 5 - -/* DCI :: CMD :: START_PROCESSOR [04:04] */ -#define DCI_CMD_START_PROCESSOR_MASK 0x00000010 -#define DCI_CMD_START_PROCESSOR_ALIGN 0 -#define DCI_CMD_START_PROCESSOR_BITS 1 -#define DCI_CMD_START_PROCESSOR_SHIFT 4 - -/* DCI :: CMD :: reserved2 [03:02] */ -#define DCI_CMD_reserved2_MASK 0x0000000c -#define DCI_CMD_reserved2_ALIGN 0 -#define DCI_CMD_reserved2_BITS 2 -#define DCI_CMD_reserved2_SHIFT 2 - -/* DCI :: CMD :: DOWNLOAD_COMPLETE [01:01] */ -#define DCI_CMD_DOWNLOAD_COMPLETE_MASK 0x00000002 -#define DCI_CMD_DOWNLOAD_COMPLETE_ALIGN 0 -#define DCI_CMD_DOWNLOAD_COMPLETE_BITS 1 -#define DCI_CMD_DOWNLOAD_COMPLETE_SHIFT 1 - -/* DCI :: CMD :: INITIATE_FW_DOWNLOAD [00:00] */ -#define DCI_CMD_INITIATE_FW_DOWNLOAD_MASK 0x00000001 -#define DCI_CMD_INITIATE_FW_DOWNLOAD_ALIGN 0 -#define DCI_CMD_INITIATE_FW_DOWNLOAD_BITS 1 -#define DCI_CMD_INITIATE_FW_DOWNLOAD_SHIFT 0 - - -/**************************************************************************** - * DCI :: STATUS - ***************************************************************************/ -/* DCI :: STATUS :: reserved0 [31:10] */ -#define DCI_STATUS_reserved0_MASK 0xfffffc00 -#define DCI_STATUS_reserved0_ALIGN 0 -#define DCI_STATUS_reserved0_BITS 22 -#define DCI_STATUS_reserved0_SHIFT 10 - -/* DCI :: STATUS :: SIGNATURE_MATCHED [09:09] */ -#define DCI_STATUS_SIGNATURE_MATCHED_MASK 0x00000200 -#define DCI_STATUS_SIGNATURE_MATCHED_ALIGN 0 -#define DCI_STATUS_SIGNATURE_MATCHED_BITS 1 -#define DCI_STATUS_SIGNATURE_MATCHED_SHIFT 9 - -/* DCI :: STATUS :: SIGNATURE_MISMATCH [08:08] */ -#define DCI_STATUS_SIGNATURE_MISMATCH_MASK 0x00000100 -#define DCI_STATUS_SIGNATURE_MISMATCH_ALIGN 0 -#define DCI_STATUS_SIGNATURE_MISMATCH_BITS 1 -#define DCI_STATUS_SIGNATURE_MISMATCH_SHIFT 8 - -/* DCI :: STATUS :: reserved1 [07:06] */ -#define DCI_STATUS_reserved1_MASK 0x000000c0 -#define DCI_STATUS_reserved1_ALIGN 0 -#define DCI_STATUS_reserved1_BITS 2 -#define DCI_STATUS_reserved1_SHIFT 6 - -/* DCI :: STATUS :: GISB_ERROR [05:05] */ -#define DCI_STATUS_GISB_ERROR_MASK 0x00000020 -#define DCI_STATUS_GISB_ERROR_ALIGN 0 -#define DCI_STATUS_GISB_ERROR_BITS 1 -#define DCI_STATUS_GISB_ERROR_SHIFT 5 - -/* DCI :: STATUS :: DOWNLOAD_READY [04:04] */ -#define DCI_STATUS_DOWNLOAD_READY_MASK 0x00000010 -#define DCI_STATUS_DOWNLOAD_READY_ALIGN 0 -#define DCI_STATUS_DOWNLOAD_READY_BITS 1 -#define DCI_STATUS_DOWNLOAD_READY_SHIFT 4 - -/* DCI :: STATUS :: reserved2 [03:01] */ -#define DCI_STATUS_reserved2_MASK 0x0000000e -#define DCI_STATUS_reserved2_ALIGN 0 -#define DCI_STATUS_reserved2_BITS 3 -#define DCI_STATUS_reserved2_SHIFT 1 - -/* DCI :: STATUS :: FIRMWARE_VALIDATED [00:00] */ -#define DCI_STATUS_FIRMWARE_VALIDATED_MASK 0x00000001 -#define DCI_STATUS_FIRMWARE_VALIDATED_ALIGN 0 -#define DCI_STATUS_FIRMWARE_VALIDATED_BITS 1 -#define DCI_STATUS_FIRMWARE_VALIDATED_SHIFT 0 - - -/**************************************************************************** - * DCI :: DRAM_BASE_ADDR - ***************************************************************************/ -/* DCI :: DRAM_BASE_ADDR :: reserved0 [31:13] */ -#define DCI_DRAM_BASE_ADDR_reserved0_MASK 0xffffe000 -#define DCI_DRAM_BASE_ADDR_reserved0_ALIGN 0 -#define DCI_DRAM_BASE_ADDR_reserved0_BITS 19 -#define DCI_DRAM_BASE_ADDR_reserved0_SHIFT 13 - -/* DCI :: DRAM_BASE_ADDR :: BASE_ADDR [12:00] */ -#define DCI_DRAM_BASE_ADDR_BASE_ADDR_MASK 0x00001fff -#define DCI_DRAM_BASE_ADDR_BASE_ADDR_ALIGN 0 -#define DCI_DRAM_BASE_ADDR_BASE_ADDR_BITS 13 -#define DCI_DRAM_BASE_ADDR_BASE_ADDR_SHIFT 0 - - -/**************************************************************************** - * DCI :: FIRMWARE_ADDR - ***************************************************************************/ -/* DCI :: FIRMWARE_ADDR :: reserved0 [31:19] */ -#define DCI_FIRMWARE_ADDR_reserved0_MASK 0xfff80000 -#define DCI_FIRMWARE_ADDR_reserved0_ALIGN 0 -#define DCI_FIRMWARE_ADDR_reserved0_BITS 13 -#define DCI_FIRMWARE_ADDR_reserved0_SHIFT 19 - -/* DCI :: FIRMWARE_ADDR :: FW_ADDR [18:02] */ -#define DCI_FIRMWARE_ADDR_FW_ADDR_MASK 0x0007fffc -#define DCI_FIRMWARE_ADDR_FW_ADDR_ALIGN 0 -#define DCI_FIRMWARE_ADDR_FW_ADDR_BITS 17 -#define DCI_FIRMWARE_ADDR_FW_ADDR_SHIFT 2 - -/* DCI :: FIRMWARE_ADDR :: reserved1 [01:00] */ -#define DCI_FIRMWARE_ADDR_reserved1_MASK 0x00000003 -#define DCI_FIRMWARE_ADDR_reserved1_ALIGN 0 -#define DCI_FIRMWARE_ADDR_reserved1_BITS 2 -#define DCI_FIRMWARE_ADDR_reserved1_SHIFT 0 - - -/**************************************************************************** - * DCI :: FIRMWARE_DATA - ***************************************************************************/ -/* DCI :: FIRMWARE_DATA :: FW_DATA [31:00] */ -#define DCI_FIRMWARE_DATA_FW_DATA_MASK 0xffffffff -#define DCI_FIRMWARE_DATA_FW_DATA_ALIGN 0 -#define DCI_FIRMWARE_DATA_FW_DATA_BITS 32 -#define DCI_FIRMWARE_DATA_FW_DATA_SHIFT 0 - - -/**************************************************************************** - * DCI :: SIGNATURE_DATA_0 - ***************************************************************************/ -/* DCI :: SIGNATURE_DATA_0 :: SIG_DATA_0 [31:00] */ -#define DCI_SIGNATURE_DATA_0_SIG_DATA_0_MASK 0xffffffff -#define DCI_SIGNATURE_DATA_0_SIG_DATA_0_ALIGN 0 -#define DCI_SIGNATURE_DATA_0_SIG_DATA_0_BITS 32 -#define DCI_SIGNATURE_DATA_0_SIG_DATA_0_SHIFT 0 - - -/**************************************************************************** - * DCI :: SIGNATURE_DATA_1 - ***************************************************************************/ -/* DCI :: SIGNATURE_DATA_1 :: SIG_DATA_1 [31:00] */ -#define DCI_SIGNATURE_DATA_1_SIG_DATA_1_MASK 0xffffffff -#define DCI_SIGNATURE_DATA_1_SIG_DATA_1_ALIGN 0 -#define DCI_SIGNATURE_DATA_1_SIG_DATA_1_BITS 32 -#define DCI_SIGNATURE_DATA_1_SIG_DATA_1_SHIFT 0 - - -/**************************************************************************** - * DCI :: SIGNATURE_DATA_2 - ***************************************************************************/ -/* DCI :: SIGNATURE_DATA_2 :: SIG_DATA_2 [31:00] */ -#define DCI_SIGNATURE_DATA_2_SIG_DATA_2_MASK 0xffffffff -#define DCI_SIGNATURE_DATA_2_SIG_DATA_2_ALIGN 0 -#define DCI_SIGNATURE_DATA_2_SIG_DATA_2_BITS 32 -#define DCI_SIGNATURE_DATA_2_SIG_DATA_2_SHIFT 0 - - -/**************************************************************************** - * DCI :: SIGNATURE_DATA_3 - ***************************************************************************/ -/* DCI :: SIGNATURE_DATA_3 :: SIG_DATA_3 [31:00] */ -#define DCI_SIGNATURE_DATA_3_SIG_DATA_3_MASK 0xffffffff -#define DCI_SIGNATURE_DATA_3_SIG_DATA_3_ALIGN 0 -#define DCI_SIGNATURE_DATA_3_SIG_DATA_3_BITS 32 -#define DCI_SIGNATURE_DATA_3_SIG_DATA_3_SHIFT 0 - - -/**************************************************************************** - * DCI :: SIGNATURE_DATA_4 - ***************************************************************************/ -/* DCI :: SIGNATURE_DATA_4 :: SIG_DATA_4 [31:00] */ -#define DCI_SIGNATURE_DATA_4_SIG_DATA_4_MASK 0xffffffff -#define DCI_SIGNATURE_DATA_4_SIG_DATA_4_ALIGN 0 -#define DCI_SIGNATURE_DATA_4_SIG_DATA_4_BITS 32 -#define DCI_SIGNATURE_DATA_4_SIG_DATA_4_SHIFT 0 - - -/**************************************************************************** - * DCI :: SIGNATURE_DATA_5 - ***************************************************************************/ -/* DCI :: SIGNATURE_DATA_5 :: SIG_DATA_5 [31:00] */ -#define DCI_SIGNATURE_DATA_5_SIG_DATA_5_MASK 0xffffffff -#define DCI_SIGNATURE_DATA_5_SIG_DATA_5_ALIGN 0 -#define DCI_SIGNATURE_DATA_5_SIG_DATA_5_BITS 32 -#define DCI_SIGNATURE_DATA_5_SIG_DATA_5_SHIFT 0 - - -/**************************************************************************** - * DCI :: SIGNATURE_DATA_6 - ***************************************************************************/ -/* DCI :: SIGNATURE_DATA_6 :: SIG_DATA_6 [31:00] */ -#define DCI_SIGNATURE_DATA_6_SIG_DATA_6_MASK 0xffffffff -#define DCI_SIGNATURE_DATA_6_SIG_DATA_6_ALIGN 0 -#define DCI_SIGNATURE_DATA_6_SIG_DATA_6_BITS 32 -#define DCI_SIGNATURE_DATA_6_SIG_DATA_6_SHIFT 0 - - -/**************************************************************************** - * DCI :: SIGNATURE_DATA_7 - ***************************************************************************/ -/* DCI :: SIGNATURE_DATA_7 :: SIG_DATA_7 [31:00] */ -#define DCI_SIGNATURE_DATA_7_SIG_DATA_7_MASK 0xffffffff -#define DCI_SIGNATURE_DATA_7_SIG_DATA_7_ALIGN 0 -#define DCI_SIGNATURE_DATA_7_SIG_DATA_7_BITS 32 -#define DCI_SIGNATURE_DATA_7_SIG_DATA_7_SHIFT 0 - - -/**************************************************************************** - * BCM70012_DCI_TOP_DCI_RGR_BRIDGE - ***************************************************************************/ -/**************************************************************************** - * DCI_RGR_BRIDGE :: REVISION - ***************************************************************************/ -/* DCI_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define DCI_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define DCI_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 -#define DCI_RGR_BRIDGE_REVISION_reserved0_BITS 16 -#define DCI_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 - -/* DCI_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define DCI_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define DCI_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 -#define DCI_RGR_BRIDGE_REVISION_MAJOR_BITS 8 -#define DCI_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 - -/* DCI_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define DCI_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define DCI_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 -#define DCI_RGR_BRIDGE_REVISION_MINOR_BITS 8 -#define DCI_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 - - -/**************************************************************************** - * DCI_RGR_BRIDGE :: CTRL - ***************************************************************************/ -/* DCI_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ -#define DCI_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc -#define DCI_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 -#define DCI_RGR_BRIDGE_CTRL_reserved0_BITS 30 -#define DCI_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 - -/* DCI_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ -#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 -#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 -#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 -#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 -#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 -#define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 - -/* DCI_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ -#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 -#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 -#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 -#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 -#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 - - -/**************************************************************************** - * DCI_RGR_BRIDGE :: RBUS_TIMER - ***************************************************************************/ -/* DCI_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ -#define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 -#define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 -#define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 -#define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 - -/* DCI_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ -#define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff -#define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 -#define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 -#define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 -/**************************************************************************** - * DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 - ***************************************************************************/ -/* DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 -/* DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved1 [08:08] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved1_MASK 0x00000100 +#define MISC1_Y_RX_ERROR_STATUS_reserved1_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved1_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_reserved1_SHIFT 8 -/**************************************************************************** - * DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 - ***************************************************************************/ -/* DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 -/* DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved2 [06:05] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved2_MASK 0x00000060 +#define MISC1_Y_RX_ERROR_STATUS_reserved2_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved2_BITS 2 +#define MISC1_Y_RX_ERROR_STATUS_reserved2_SHIFT 5 +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 -/**************************************************************************** - * BCM70012_CCE_TOP_CCE_RGR_BRIDGE - ***************************************************************************/ -/**************************************************************************** - * CCE_RGR_BRIDGE :: REVISION - ***************************************************************************/ -/* CCE_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ -#define CCE_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 -#define CCE_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 -#define CCE_RGR_BRIDGE_REVISION_reserved0_BITS 16 -#define CCE_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved3 [03:02] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved3_MASK 0x0000000c +#define MISC1_Y_RX_ERROR_STATUS_reserved3_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved3_BITS 2 +#define MISC1_Y_RX_ERROR_STATUS_reserved3_SHIFT 2 -/* CCE_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ -#define CCE_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 -#define CCE_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 -#define CCE_RGR_BRIDGE_REVISION_MAJOR_BITS 8 -#define CCE_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 +/* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 -/* CCE_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ -#define CCE_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff -#define CCE_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 -#define CCE_RGR_BRIDGE_REVISION_MINOR_BITS 8 -#define CCE_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 +/* MISC1 :: Y_RX_ERROR_STATUS :: reserved4 [00:00] */ +#define MISC1_Y_RX_ERROR_STATUS_reserved4_MASK 0x00000001 +#define MISC1_Y_RX_ERROR_STATUS_reserved4_ALIGN 0 +#define MISC1_Y_RX_ERROR_STATUS_reserved4_BITS 1 +#define MISC1_Y_RX_ERROR_STATUS_reserved4_SHIFT 0 /**************************************************************************** - * CCE_RGR_BRIDGE :: CTRL + * MISC1 :: UV_RX_ERROR_STATUS ***************************************************************************/ -/* CCE_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ -#define CCE_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc -#define CCE_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 -#define CCE_RGR_BRIDGE_CTRL_reserved0_BITS 30 -#define CCE_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved0 [31:14] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 +#define MISC1_UV_RX_ERROR_STATUS_reserved0_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved0_BITS 18 +#define MISC1_UV_RX_ERROR_STATUS_reserved0_SHIFT 14 -/* CCE_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ -#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 -#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 -#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 -#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 -#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 -#define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 -/* CCE_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ -#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 -#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 -#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 -#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 -#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 -#define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 -/**************************************************************************** - * CCE_RGR_BRIDGE :: RBUS_TIMER - ***************************************************************************/ -/* CCE_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ -#define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 -#define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 -#define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 -#define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 -/* CCE_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ -#define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff -#define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 -#define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 -#define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved1 [08:08] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved1_MASK 0x00000100 +#define MISC1_UV_RX_ERROR_STATUS_reserved1_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved1_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_reserved1_SHIFT 8 -/**************************************************************************** - * CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 - ***************************************************************************/ -/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 -/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved2 [06:05] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved2_MASK 0x00000060 +#define MISC1_UV_RX_ERROR_STATUS_reserved2_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved2_BITS 2 +#define MISC1_UV_RX_ERROR_STATUS_reserved2_SHIFT 5 +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 -/**************************************************************************** - * CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 - ***************************************************************************/ -/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved3 [03:02] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved3_MASK 0x0000000c +#define MISC1_UV_RX_ERROR_STATUS_reserved3_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved3_BITS 2 +#define MISC1_UV_RX_ERROR_STATUS_reserved3_SHIFT 2 -/* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 +/* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 +/* MISC1 :: UV_RX_ERROR_STATUS :: reserved4 [00:00] */ +#define MISC1_UV_RX_ERROR_STATUS_reserved4_MASK 0x00000001 +#define MISC1_UV_RX_ERROR_STATUS_reserved4_ALIGN 0 +#define MISC1_UV_RX_ERROR_STATUS_reserved4_BITS 1 +#define MISC1_UV_RX_ERROR_STATUS_reserved4_SHIFT 0 /**************************************************************************** * Datatype Definitions. -- cgit v1.2.3 From d027936949b839a858cd822975491e19ec316621 Mon Sep 17 00:00:00 2001 From: "horms@vergenet.net" Date: Fri, 8 Jan 2010 18:57:49 +1100 Subject: Staging: otus: dont mix declarations and code $ gcc (Debian 4.4.2-8) 4.4.2 Copyright (C) 2009 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ make ... drivers/staging/otus/ioctl.c: In function 'usbdrv_wpa_ioctl': drivers/staging/otus/ioctl.c:2253: warning: ISO C90 forbids mixed declarations and code ... Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/otus/ioctl.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/otus/ioctl.c b/drivers/staging/otus/ioctl.c index 86d93330acad..ebaedb7b1688 100644 --- a/drivers/staging/otus/ioctl.c +++ b/drivers/staging/otus/ioctl.c @@ -2227,7 +2227,8 @@ int usbdrv_wpa_ioctl(struct net_device *dev, struct athr_wlan_param *zdparm) case ZD_CMD_SCAN_REQ: printk(KERN_ERR "usbdrv_wpa_ioctl: ZD_CMD_SCAN_REQ\n"); break; - case ZD_CMD_SET_GENERIC_ELEMENT: + case ZD_CMD_SET_GENERIC_ELEMENT: { + u8_t len, *wpaie; printk(KERN_ERR "usbdrv_wpa_ioctl:" " ZD_CMD_SET_GENERIC_ELEMENT\n"); @@ -2250,8 +2251,8 @@ int usbdrv_wpa_ioctl(struct net_device *dev, struct athr_wlan_param *zdparm) /* zfiWlanSetWpaIe(dev, zdparm->u.generic_elem.data, * zdparm->u.generic_elem.len); */ - u8_t len = zdparm->u.generic_elem.len; - u8_t *wpaie = (u8_t *)zdparm->u.generic_elem.data; + len = zdparm->u.generic_elem.len; + wpaie = zdparm->u.generic_elem.data; printk(KERN_ERR "wd->ap.wpaLen : % d\n", len); @@ -2273,6 +2274,7 @@ int usbdrv_wpa_ioctl(struct net_device *dev, struct athr_wlan_param *zdparm) * #endif */ break; + } /* #ifdef ZM_HOSTAPD_SUPPORT */ case ZD_CMD_GET_TSC: -- cgit v1.2.3 From d74385fd9c81d2168aa3a556abcc55f5e1558626 Mon Sep 17 00:00:00 2001 From: "horms@vergenet.net" Date: Fri, 8 Jan 2010 18:57:50 +1100 Subject: Staging: otus: remove unused variables Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/otus/80211core/cagg.c | 3 +-- drivers/staging/otus/80211core/cfunc.c | 2 -- drivers/staging/otus/80211core/cmm.c | 4 ---- drivers/staging/otus/80211core/cmmsta.c | 5 ----- drivers/staging/otus/80211core/cpsmgr.c | 2 -- drivers/staging/otus/80211core/cscanmgr.c | 2 -- drivers/staging/otus/80211core/ctxrx.c | 5 ----- drivers/staging/otus/80211core/ledmgr.c | 1 - drivers/staging/otus/hal/hpmain.c | 4 ---- drivers/staging/otus/hal/hprw.c | 1 - 10 files changed, 1 insertion(+), 28 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/otus/80211core/cagg.c b/drivers/staging/otus/80211core/cagg.c index dbd0a5f0fcdf..d11661c3b884 100644 --- a/drivers/staging/otus/80211core/cagg.c +++ b/drivers/staging/otus/80211core/cagg.c @@ -1832,8 +1832,7 @@ u16_t zfAggRxClear(zdev_t* dev, u32_t time) struct agg_tid_rx* zfAggRxEnabled(zdev_t* dev, zbuf_t* buf) { - u16_t dst0, src[3], ac, aid, fragOff; - u8_t up; + u16_t dst0, src[3], aid; u16_t offset = 0; u16_t seq_no; u16_t frameType; diff --git a/drivers/staging/otus/80211core/cfunc.c b/drivers/staging/otus/80211core/cfunc.c index d7c49d7523df..e0a9f383c755 100644 --- a/drivers/staging/otus/80211core/cfunc.c +++ b/drivers/staging/otus/80211core/cfunc.c @@ -1194,8 +1194,6 @@ u16_t zfFindMinimumUtilizationChannelIndex(zdev_t* dev, u16_t* array, u16_t coun u8_t i; u16_t tempMinIndex, tempMinValue; - zmw_get_wlan_dev(dev); - i = 1; tempMinIndex = 0; tempMinValue = array[tempMinIndex]; diff --git a/drivers/staging/otus/80211core/cmm.c b/drivers/staging/otus/80211core/cmm.c index a6c1b41ba848..484e753df358 100644 --- a/drivers/staging/otus/80211core/cmm.c +++ b/drivers/staging/otus/80211core/cmm.c @@ -346,8 +346,6 @@ u16_t zfFindSuperGElement(zdev_t* dev, zbuf_t* buf, u8_t type) u8_t super_feature; u8_t ouiSuperG[6] = {0x00,0x03,0x7f,0x01, 0x01, 0x00}; - zmw_get_wlan_dev(dev); - /* Get offset of first element */ subType = (zmw_rx_buf_readb(dev, buf, 0) >> 4); if ((offset = zgElementOffsetTable[subType]) == 0xff) @@ -411,8 +409,6 @@ u16_t zfFindXRElement(zdev_t* dev, zbuf_t* buf, u8_t type) u8_t id; u8_t ouixr[6] = {0x00,0x03,0x7f,0x03, 0x01, 0x00}; - zmw_get_wlan_dev(dev); - /* Get offset of first element */ subType = (zmw_rx_buf_readb(dev, buf, 0) >> 4); if ((offset = zgElementOffsetTable[subType]) == 0xff) diff --git a/drivers/staging/otus/80211core/cmmsta.c b/drivers/staging/otus/80211core/cmmsta.c index 5c0dea7a3433..c3fd47529c14 100644 --- a/drivers/staging/otus/80211core/cmmsta.c +++ b/drivers/staging/otus/80211core/cmmsta.c @@ -4848,8 +4848,6 @@ u16_t zfStaAddIePowerCap(zdev_t* dev, zbuf_t* buf, u16_t offset) u8_t MaxTxPower; u8_t MinTxPower; - zmw_get_wlan_dev(dev); - /* Element ID */ zmw_tx_buf_writeb(dev, buf, offset++, ZM_WLAN_EID_POWER_CAPABILITY); @@ -5276,7 +5274,6 @@ u16_t zfStaRxValidateFrame(zdev_t* dev, zbuf_t* buf) u8_t da0; //u16_t sa[3]; u16_t ret; - u16_t i; //u8_t sa0; zmw_get_wlan_dev(dev); @@ -5738,8 +5735,6 @@ u16_t zfComputeBssInfoWeightValue(zdev_t *dev, u8_t isBMode, u8_t isHT, u8_t isH u8_t weightOfN40BelowThr = 16; u8_t weightOfN40UpThr = 32; - zmw_get_wlan_dev(dev); - if( isBMode == 0 ) return (signalStrength + weightOfB); // pure b mode , do not add the weight value for this AP ! else diff --git a/drivers/staging/otus/80211core/cpsmgr.c b/drivers/staging/otus/80211core/cpsmgr.c index cf73caca8e52..98e1f0cc0727 100644 --- a/drivers/staging/otus/80211core/cpsmgr.c +++ b/drivers/staging/otus/80211core/cpsmgr.c @@ -381,8 +381,6 @@ static void zfPowerSavingMgrSleepIfIdle(zdev_t *dev) static void zfPowerSavingMgrDisconnectMain(zdev_t* dev) { - zmw_get_wlan_dev(dev); - #ifdef ZM_ENABLE_DISCONNECT_PS switch(wd->sta.psMgr.state) { diff --git a/drivers/staging/otus/80211core/cscanmgr.c b/drivers/staging/otus/80211core/cscanmgr.c index b32835c87590..be7d8ebe82ba 100644 --- a/drivers/staging/otus/80211core/cscanmgr.c +++ b/drivers/staging/otus/80211core/cscanmgr.c @@ -289,8 +289,6 @@ static void zfScanMgrEventSetFreqCompleteCb(zdev_t* dev) static void zfScanMgrEventScanCompleteCb(zdev_t* dev) { - zmw_get_wlan_dev(dev); - if ((zfStaIsConnected(dev)) && (!zfPowerSavingMgrIsSleeping(dev))) { zfSendNullData(dev, 0); diff --git a/drivers/staging/otus/80211core/ctxrx.c b/drivers/staging/otus/80211core/ctxrx.c index 7fa4f48fc8ca..4e7f4bd86f47 100644 --- a/drivers/staging/otus/80211core/ctxrx.c +++ b/drivers/staging/otus/80211core/ctxrx.c @@ -882,7 +882,6 @@ zlError: /************************************************************************/ u16_t zfTxSendEth(zdev_t* dev, zbuf_t* buf, u16_t port, u16_t bufType, u16_t flag) { - u16_t err; //u16_t addrTblSize; //struct zsAddrTbl addrTbl; u16_t removeLen; @@ -904,7 +903,6 @@ u16_t zfTxSendEth(zdev_t* dev, zbuf_t* buf, u16_t port, u16_t bufType, u16_t fla u8_t qosType, keyIdx = 0; u16_t fragOff; u16_t newFlag; - struct zsMicVar* pMicKey; u8_t tkipFrameOffset = 0; zmw_get_wlan_dev(dev); @@ -1692,8 +1690,6 @@ void zfShowTxEAPOL(zdev_t* dev, zbuf_t* buf, u16_t offset) u16_t packetLen, keyInfo, keyLen, keyDataLen, length, Op_Code; u32_t replayCounterH, replayCounterL, vendorId, VendorType; - zmw_get_wlan_dev(dev); - zm_debug_msg1("EAPOL Packet size = ", zfwBufGetSize(dev, buf)); /* EAPOL packet type */ @@ -2436,7 +2432,6 @@ void zfiRecv80211(zdev_t* dev, zbuf_t* buf, struct zsAdditionInfo* addInfo) u16_t IvOffset; u8_t keyLen = 5; u8_t iv[3]; - u8_t *wepKey; u8_t keyIdx; IvOffset = offset + ZM_SIZE_OF_WLAN_DATA_HEADER; diff --git a/drivers/staging/otus/80211core/ledmgr.c b/drivers/staging/otus/80211core/ledmgr.c index 1e104a928ca4..eafce0b1204f 100644 --- a/drivers/staging/otus/80211core/ledmgr.c +++ b/drivers/staging/otus/80211core/ledmgr.c @@ -187,7 +187,6 @@ void zfLedCtrlType2_scan(zdev_t* dev); void zfLedCtrlType2(zdev_t* dev) { - u32_t ton, toff, tmp, period; u16_t OperateLED; zmw_get_wlan_dev(dev); diff --git a/drivers/staging/otus/hal/hpmain.c b/drivers/staging/otus/hal/hpmain.c index 94f9cbbbdefc..8dff5b97dfe3 100644 --- a/drivers/staging/otus/hal/hpmain.c +++ b/drivers/staging/otus/hal/hpmain.c @@ -1316,7 +1316,6 @@ void zfHpSetFrequencyEx(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset, u8_t initRF) { u32_t cmd[9]; - u32_t cmdB[3]; u16_t ret; u8_t old_band; u8_t new_band; @@ -3434,7 +3433,6 @@ void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset) /* Write PHY regs 672-703 */ for (i=0; i<128; i+=4) { - u32_t regAddr = 0x9800 + (672 * 4); u32_t val; val = ((u32_t)vpd_chain1[i+3]<<24) | @@ -3485,7 +3483,6 @@ void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset) /* Write PHY regs 672-703 + 0x1000 */ for (i=0; i<128; i+=4) { - u32_t regAddr = 0x9800 + (672 * 4) + 0x1000; u32_t val; val = ((u32_t)vpd_chain3[i+3]<<24) | @@ -4584,7 +4581,6 @@ void zfHpSetRollCallTable(zdev_t* dev) void zfHpSetTTSIFSTime(zdev_t* dev, u8_t sifs_time) { u32_t reg_value = 0; - zmw_get_wlan_dev(dev); sifs_time &= 0x3f; reg_value = 0x14400b | (((u32_t)sifs_time)<<24); diff --git a/drivers/staging/otus/hal/hprw.c b/drivers/staging/otus/hal/hprw.c index d9fad47d5d59..4dbd5fb44b0a 100644 --- a/drivers/staging/otus/hal/hprw.c +++ b/drivers/staging/otus/hal/hprw.c @@ -282,7 +282,6 @@ void zfIdlRsp(zdev_t* dev, u32_t* rsp, u16_t rspLen) else if (src == ZM_OID_FLASH_READ) { u32_t datalen; - u16_t i; datalen = (rsp[0] & 255); -- cgit v1.2.3 From 3db96cd871e7cfea6e671b262a8ef661b27dadf1 Mon Sep 17 00:00:00 2001 From: "horms@vergenet.net" Date: Fri, 8 Jan 2010 18:57:51 +1100 Subject: Staging: otus: remove unused constants Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/otus/hal/hpreg.c | 133 --------------------------------------- 1 file changed, 133 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/otus/hal/hpreg.c b/drivers/staging/otus/hal/hpreg.c index d9894fe5f4ec..178777c09dbd 100644 --- a/drivers/staging/otus/hal/hpreg.c +++ b/drivers/staging/otus/hal/hpreg.c @@ -786,45 +786,6 @@ enum { WT1_5760_5800, }; -static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = { - { 5130, 5210, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5130_5210 */ - { 5250, 5330, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 0}, /* T1_5250_5330 */ - { 5370, 5490, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5370_5490 */ - { 5530, 5650, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 0}, /* T1_5530_5650 */ - - { 5150, 5190, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5150_5190 */ - { 5230, 5310, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 0}, /* T1_5230_5310 */ - { 5350, 5470, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5350_5470 */ - { 5510, 5670, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 0}, /* T1_5510_5670 */ - - { 5200, 5240, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5200_5240 */ - { 5200, 5240, 23, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T2_5200_5240 */ - { 5210, 5210, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5210_5210 */ - { 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T2_5210_5210 */ - - { 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5280_5280 */ - { 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T2_5280_5280 */ - { 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5250_5250 */ - { 5290, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5290_5290 */ - { 5250, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5250_5290 */ - { 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T2_5250_5290 */ - - { 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5540_5660 */ - { 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5760_5800 */ - { 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T2_5760_5800 */ - - { 5765, 5805, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5765_5805 */ - - /* - * Below are the WWR frequencies - */ - - { 5210, 5250, 15, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0}, /* WT1_5210_5250 */ - { 5290, 5290, 18, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0}, /* WT1_5290_5290 */ - { 5540, 5660, 20, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0}, /* WT1_5540_5660 */ - { 5760, 5800, 20, 0, 40, 40, NO_DFS, PSCAN_WWR, 0, 0}, /* WT1_5760_5800 */ -}; - /* * 2GHz 11b channel tags */ @@ -864,45 +825,6 @@ enum { W2_2484_2484, }; -static REG_DMN_FREQ_BAND regDmn2GhzFreq[] = { - { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2312_2372 */ - { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F2_2312_2372 */ - - { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2412_2472 */ - { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0, 0}, /* F2_2412_2472 */ - { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F3_2412_2472 */ - - { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2412_2462 */ - { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0, 0}, /* F2_2412_2462 */ - { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2432_2442 */ - - { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2457_2472 */ - - { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0, 0}, /* F1_2467_2472 */ - - { 2484, 2484, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2484_2484 */ - { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2, 0, 0}, /* F2_2484_2484 */ - - { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2512_2732 */ - - /* - * WWR have powers opened up to 20dBm. Limits should often come from CTL/Max powers - */ - - { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2312_2372 */ - { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2412_2412 */ - { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2417_2432 */ - { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2437_2442 */ - { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2447_2457 */ - { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2462_2462 */ - { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* W1_2467_2467 */ - { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* W2_2467_2467 */ - { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* W1_2472_2472 */ - { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* W2_2472_2472 */ - { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* W1_2484_2484 */ - { 2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* W2_2484_2484 */ -}; - /* * 2GHz 11g channel tags @@ -984,16 +906,6 @@ enum { T1_2512_2732 }; -static REG_DMN_FREQ_BAND regDmn2Ghz11gTurboFreq[] = { - { 2312, 2372, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_2312_2372 */ - { 2437, 2437, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_2437_2437 */ - { 2437, 2437, 20, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T2_2437_2437 */ - { 2437, 2437, 18, 6, 40, 40, NO_DFS, PSCAN_WWR, 0, 0}, /* T3_2437_2437 */ - { 2512, 2732, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_2512_2732 */ -}; - - - /* * 2GHz 11n frequency tags */ @@ -1005,15 +917,6 @@ enum { NG_DEMO_ALL_CHANNELS, }; -static REG_DMN_FREQ_BAND regDmn2Ghz11ngFreq[] = { - { 2422, 2452, 20, 0, 40, 5, NO_DFS, NO_PSCAN, 0, 0}, /* NG1_2422_2452 */ - { 2422, 2452, 27, 0, 40, 5, NO_DFS, NO_PSCAN, 0, 0}, /* NG2_2422_2452 */ - { 2422, 2452, 30, 0, 40, 5, NO_DFS, NO_PSCAN, 0, 0}, /* NG3_2422_2452 */ - - { 2312, 2732, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* NG_DEMO_ALL_CHANNELS */ -}; - - /* * 5GHz 11n frequency tags */ @@ -1050,42 +953,6 @@ enum { NA_DEMO_ALL_CHANNELS, }; -static REG_DMN_FREQ_BAND regDmn5Ghz11naFreq[] = { - /* - * ToDo: This table needs to be completely populated with 5GHz 11n properties - */ - { 5190, 5230, 15, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA1_5190_5230 */ - { 5190, 5230, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA2_5190_5230 */ - { 5190, 5230, 18, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA3_5190_5230 */ - { 5190, 5230, 20, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA4_5190_5230 */ - { 5190, 5230, 23, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA5_5190_5230 */ - - { 5270, 5270, 23, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA1_5270_5270 */ - - { 5270, 5310, 18, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA1_5270_5310 */ - { 5270, 5310, 20, 0, 40, 40, DFS_FCC3|DFS_ETSI|DFS_MKK4, NO_PSCAN, 0, 1}, /* NA2_5270_5310 */ - { 5270, 5310, 23, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA3_5270_5310 */ - { 5270, 5310, 30, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA4_5270_5310 */ - - { 5310, 5310, 17, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA1_5310_5310 */ - - { 5510, 5630, 30, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA1_5510_5630 */ - - { 5510, 5670, 20, 6, 40, 40, DFS_FCC3|DFS_ETSI|DFS_MKK4, NO_PSCAN, 0, 1}, /* NA1_5510_5670 */ - { 5510, 5670, 27, 0, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA2_5510_5670 */ - { 5510, 5670, 30, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 1}, /* NA3_5510_5670 */ - - { 5755, 5795, 17, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA1_5755_5795 */ - { 5755, 5795, 20, 6, 40, 40, DFS_ETSI, NO_PSCAN, 0, 0}, /* NA2_5755_5795 */ - { 5755, 5795, 23, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA3_5755_5795 */ - { 5755, 5795, 30, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA4_5755_5795 */ - { 5755, 5795, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA5_5755_5795 */ - - { 5795, 5795, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA1_5795_5795 */ - - { 4920, 6100, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA_DEMO_ALL_CHANNELS */ -}; - typedef struct regDomain { u16_t regDmnEnum; /* value from EnumRd table */ u8_t conformanceTestLimit; -- cgit v1.2.3 From e36e8c0add960eb523a8a1bc93c7efa744339415 Mon Sep 17 00:00:00 2001 From: "horms@vergenet.net" Date: Fri, 8 Jan 2010 18:57:52 +1100 Subject: Staging: otus: Fix ZM_SEQ_DEBUG macro for no-debug case tcp_seq is only initialised in case where ZM_ENABLE_PERFORMANCE_EVALUATION is defined. So move the call to ZM_SEQ_DEBUG() and the decleration of tcp_seq in there too. This allows ZM_SEQ_DEBUG() to be removed from the non-ZM_ENABLE_PERFORMANCE_EVALUATION case in the header file. This resolves several compile warnings for the non-ZM_ENABLE_PERFORMANCE_EVALUATION case. However, the ZM_ENABLE_PERFORMANCE_EVALUATION case seems to be completely broken. $ gcc (Debian 4.4.2-8) 4.4.2 Copyright (C) 2009 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ make ... drivers/staging/otus/80211core/cagg.c: In function 'zfAggRxEnabled': drivers/staging/otus/80211core/cagg.c:1872: warning: left-hand operand of comma expression has no effect drivers/staging/otus/80211core/cagg.c:1872: warning: left-hand operand of comma expression has no effect drivers/staging/otus/80211core/cagg.c:1872: warning: statement with no effect ... Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/otus/80211core/cagg.c | 15 +++++++++------ drivers/staging/otus/80211core/pub_zfi.h | 1 - 2 files changed, 9 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/otus/80211core/cagg.c b/drivers/staging/otus/80211core/cagg.c index d11661c3b884..f9514c06c14c 100644 --- a/drivers/staging/otus/80211core/cagg.c +++ b/drivers/staging/otus/80211core/cagg.c @@ -1838,7 +1838,6 @@ struct agg_tid_rx* zfAggRxEnabled(zdev_t* dev, zbuf_t* buf) u16_t frameType; u16_t frameCtrl; u16_t frameSubtype; - u32_t tcp_seq; //struct aggSta *agg_sta; #if ZM_AGG_FPGA_REORDERING struct agg_tid_rx *tid_rx; @@ -1863,13 +1862,17 @@ struct agg_tid_rx* zfAggRxEnabled(zdev_t* dev, zbuf_t* buf) return NULL; } #ifdef ZM_ENABLE_PERFORMANCE_EVALUATION - tcp_seq = zmw_rx_buf_readb(dev, buf, 22+36) << 24; - tcp_seq += zmw_rx_buf_readb(dev, buf, 22+37) << 16; - tcp_seq += zmw_rx_buf_readb(dev, buf, 22+38) << 8; - tcp_seq += zmw_rx_buf_readb(dev, buf, 22+39); + { + u32_t tcp_seq; + + tcp_seq = zmw_rx_buf_readb(dev, buf, 22+36) << 24; + tcp_seq += zmw_rx_buf_readb(dev, buf, 22+37) << 16; + tcp_seq += zmw_rx_buf_readb(dev, buf, 22+38) << 8; + tcp_seq += zmw_rx_buf_readb(dev, buf, 22+39); + ZM_SEQ_DEBUG("In %5d, %12u\n", seq_no, tcp_seq); + } #endif - ZM_SEQ_DEBUG("In %5d, %12u\n", seq_no, tcp_seq); dst0 = zmw_rx_buf_readh(dev, buf, offset+4); src[0] = zmw_rx_buf_readh(dev, buf, offset+10); diff --git a/drivers/staging/otus/80211core/pub_zfi.h b/drivers/staging/otus/80211core/pub_zfi.h index b7b7f455f357..5202e5a645d5 100644 --- a/drivers/staging/otus/80211core/pub_zfi.h +++ b/drivers/staging/otus/80211core/pub_zfi.h @@ -814,7 +814,6 @@ extern void zfiRxPerformanceReg(zdev_t* dev, u32_t reg, u32_t rsp); #define ZM_PERFORMANCE_RX_AMSDU(dev, buf, len) #define ZM_PERFORMANCE_RX_FLUSH(dev) #define ZM_PERFORMANCE_RX_CLEAR(dev) -#define ZM_SEQ_DEBUG #define ZM_PERFORMANCE_RX_REORDER(dev) #endif /***** End of section 3 *****/ -- cgit v1.2.3 From 0daa04a586f03de8f9022e29fb41c9dc0de28c4a Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 12 Jan 2010 11:50:09 +1100 Subject: Staging: otus: zfTkipInit(): increment another pointer Increment the pointer rather than its value. These appear to be logic errors. Thanks to Dan Carpenter for the first hunk of this change. Cc: Dan Carpenter Signed-off-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/otus/80211core/ctkip.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/otus/80211core/ctkip.c b/drivers/staging/otus/80211core/ctkip.c index be42f7aaa37d..ca0740227be4 100644 --- a/drivers/staging/otus/80211core/ctkip.c +++ b/drivers/staging/otus/80211core/ctkip.c @@ -255,7 +255,8 @@ void zfTkipInit(u8_t* key, u8_t* ta, struct zsTkipSeed* pSeed, u8_t* initIv) zfMemoryCopy(pSeed->ta, ta, 6); zfMemoryCopy(pSeed->tk, key, 16); - iv16 = *initIv++; + iv16 = *initIv; + initIv++; iv16 += *initIv<<8; initIv++; @@ -264,7 +265,7 @@ void zfTkipInit(u8_t* key, u8_t* ta, struct zsTkipSeed* pSeed, u8_t* initIv) for(i=0; i<4; i++) // initiv is little endian { iv32 += *initIv<<(i*8); - *initIv++; + initIv++; } pSeed->iv32 = iv32+1; // Force Recalculating on Tkip Phase1 -- cgit v1.2.3 From 75c8075394906b4bda4b056328bd9b401277d9b8 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sat, 9 Jan 2010 16:57:34 +0000 Subject: staging: iio: Ensure mutex is correctly unlocked in __iio_push_event This error was picked up by running the smatch static checker over all the IIO subsytem. Signed-off-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/staging/iio/industrialio-core.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/iio/industrialio-core.c b/drivers/staging/iio/industrialio-core.c index 768f44894d08..87799b2a9262 100644 --- a/drivers/staging/iio/industrialio-core.c +++ b/drivers/staging/iio/industrialio-core.c @@ -79,11 +79,14 @@ EXPORT_SYMBOL(__iio_change_event); /* Does anyone care? */ mutex_lock(&ev_int->event_list_lock); if (test_bit(IIO_BUSY_BIT_POS, &ev_int->handler.flags)) { - if (ev_int->current_events == ev_int->max_events) + if (ev_int->current_events == ev_int->max_events) { + mutex_unlock(&ev_int->event_list_lock); return 0; + } ev = kmalloc(sizeof(*ev), GFP_KERNEL); if (ev == NULL) { ret = -ENOMEM; + mutex_unlock(&ev_int->event_list_lock); goto error_ret; } ev->ev.id = ev_code; -- cgit v1.2.3 From 75b16013e29f6058e5bd648e6f4a9c03d262cf4f Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sat, 9 Jan 2010 17:01:33 +0000 Subject: staging: iio: Fix incorrect existence check for a shared event pointer. A second smatch detected error. First part fixes in a typo in the comment directly above that I noticed whilst trying to remember what this code actually does. Second part is the actual fix. I'm fairly amazed this one never caused trouble in testing as it is in one of the most common paths. Signed-off-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/staging/iio/industrialio-core.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/iio/industrialio-core.c b/drivers/staging/iio/industrialio-core.c index 87799b2a9262..4ff683a3df31 100644 --- a/drivers/staging/iio/industrialio-core.c +++ b/drivers/staging/iio/industrialio-core.c @@ -292,16 +292,16 @@ ssize_t iio_event_chrdev_read(struct file *filep, mutex_unlock(&ev_int->event_list_lock); /* * Possible concurency issue if an update of this event is on its way - * through. May lead to new even being removed whilst the reported event - * was the unescalated event. In typical use case this is not a problem - * as userspace will say read half the buffer due to a 50% full event - * which would make the correct 100% full incorrect anyway. + * through. May lead to new event being removed whilst the reported + * event was the unescalated event. In typical use case this is not a + * problem as userspace will say read half the buffer due to a 50% + * full event which would make the correct 100% full incorrect anyway. */ - spin_lock(&el->shared_pointer->lock); - if (el->shared_pointer) + if (el->shared_pointer) { + spin_lock(&el->shared_pointer->lock); (el->shared_pointer->ev_p) = NULL; - spin_unlock(&el->shared_pointer->lock); - + spin_unlock(&el->shared_pointer->lock); + } kfree(el); return len; -- cgit v1.2.3 From 13ac58dac0c6b1edeb060102049b07ebceea9a40 Mon Sep 17 00:00:00 2001 From: Németh Márton Date: Sun, 10 Jan 2010 00:18:26 +0100 Subject: staging: make PCI device id constant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The id_table field of the struct pci_driver is constant in so it is worth to make the initialization data also constant. The semantic match that finds this kind of pattern is as follows: (http://coccinelle.lip6.fr/) // @r@ disable decl_init,const_decl_init; identifier I1, I2, x; @@ struct I1 { ... const struct I2 *x; ... }; @s@ identifier r.I1, y; identifier r.x, E; @@ struct I1 y = { .x = E, }; @c@ identifier r.I2; identifier s.E; @@ const struct I2 E[] = ... ; @depends on !c@ identifier r.I2; identifier s.E; @@ + const struct I2 E[] = ...; // Signed-off-by: Németh Márton Cc: Julia Lawall Cc: cocci@diku.dk Signed-off-by: Greg Kroah-Hartman --- drivers/staging/phison/phison.c | 2 +- drivers/staging/rar/rar_driver.c | 2 +- drivers/staging/sep/sep_driver.c | 2 +- drivers/staging/sm7xx/smtcfb.c | 2 +- drivers/staging/vme/bridges/vme_ca91cx42.c | 2 +- drivers/staging/vme/bridges/vme_tsi148.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/phison/phison.c b/drivers/staging/phison/phison.c index 3817d7497049..ff30cb0321b9 100644 --- a/drivers/staging/phison/phison.c +++ b/drivers/staging/phison/phison.c @@ -69,7 +69,7 @@ static int phison_init_one(struct pci_dev *pdev, const struct pci_device_id *id) return ret; } -static struct pci_device_id phison_pci_tbl[] = { +static const struct pci_device_id phison_pci_tbl[] = { { PCI_VENDOR_ID_PHISON, PCI_DEVICE_ID_PS5000, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE << 8, 0xffff00, 0 }, { 0, }, diff --git a/drivers/staging/rar/rar_driver.c b/drivers/staging/rar/rar_driver.c index b91a90f4ce9e..a85a7da6df40 100644 --- a/drivers/staging/rar/rar_driver.c +++ b/drivers/staging/rar/rar_driver.c @@ -71,7 +71,7 @@ static void __exit rar_exit_handler(void); static int __devinit rar_probe(struct pci_dev *pdev, const struct pci_device_id *ent); -static struct pci_device_id rar_pci_id_tbl[] = { +static const struct pci_device_id rar_pci_id_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4110) }, { 0 } }; diff --git a/drivers/staging/sep/sep_driver.c b/drivers/staging/sep/sep_driver.c index 92fa18655f87..09346c92e94d 100644 --- a/drivers/staging/sep/sep_driver.c +++ b/drivers/staging/sep/sep_driver.c @@ -2587,7 +2587,7 @@ end_function: return error; } -static struct pci_device_id sep_pci_id_tbl[] = { +static const struct pci_device_id sep_pci_id_tbl[] = { {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080c)}, {0} }; diff --git a/drivers/staging/sm7xx/smtcfb.c b/drivers/staging/sm7xx/smtcfb.c index 161dbc9c1397..080b51a6e553 100644 --- a/drivers/staging/sm7xx/smtcfb.c +++ b/drivers/staging/sm7xx/smtcfb.c @@ -1103,7 +1103,7 @@ static int __init smtcfb_pci_probe(struct pci_dev *pdev, /* Jason (08/11/2009) PCI_DRV wrapper essential structs */ -static struct pci_device_id smtcfb_pci_table[] = { +static const struct pci_device_id smtcfb_pci_table[] = { {0x126f, 0x710, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {0x126f, 0x712, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {0x126f, 0x720, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index 470479856054..807278485bbf 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c @@ -61,7 +61,7 @@ static struct mutex vme_int; /* static char driver_name[] = "vme_ca91cx42"; -static struct pci_device_id ca91cx42_ids[] = { +static const struct pci_device_id ca91cx42_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) }, { }, }; diff --git a/drivers/staging/vme/bridges/vme_tsi148.c b/drivers/staging/vme/bridges/vme_tsi148.c index 4d19a914ec52..ed8297daf9ee 100644 --- a/drivers/staging/vme/bridges/vme_tsi148.c +++ b/drivers/staging/vme/bridges/vme_tsi148.c @@ -81,7 +81,7 @@ static struct mutex vme_int; /* static char driver_name[] = "vme_tsi148"; -static struct pci_device_id tsi148_ids[] = { +static const struct pci_device_id tsi148_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) }, { }, }; -- cgit v1.2.3 From a457732b836b970c82c7ba35b4cfc938c9c543f9 Mon Sep 17 00:00:00 2001 From: Németh Márton Date: Sun, 10 Jan 2010 00:18:34 +0100 Subject: staging: make USB device id constant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The id_table field of the struct usb_device_id is constant in so it is worth to make the initialization data also constant. The semantic match that finds this kind of pattern is as follows: (http://coccinelle.lip6.fr/) // @r@ disable decl_init,const_decl_init; identifier I1, I2, x; @@ struct I1 { ... const struct I2 *x; ... }; @s@ identifier r.I1, y; identifier r.x, E; @@ struct I1 y = { .x = E, }; @c@ identifier r.I2; identifier s.E; @@ const struct I2 E[] = ... ; @depends on !c@ identifier r.I2; identifier s.E; @@ + const struct I2 E[] = ...; // Signed-off-by: Németh Márton Cc: Julia Lawall Cc: cocci@diku.dk Signed-off-by: Greg Kroah-Hartman --- drivers/staging/asus_oled/asus_oled.c | 2 +- drivers/staging/comedi/drivers/dt9812.c | 2 +- drivers/staging/comedi/drivers/usbdux.c | 2 +- drivers/staging/comedi/drivers/usbduxfast.c | 2 +- drivers/staging/comedi/drivers/vmk80xx.c | 2 +- drivers/staging/frontier/alphatrack.c | 2 +- drivers/staging/frontier/tranzport.c | 2 +- drivers/staging/go7007/go7007-usb.c | 2 +- drivers/staging/go7007/s2250-loader.c | 2 +- drivers/staging/line6/driver.c | 2 +- drivers/staging/otus/zdusb.c | 2 +- drivers/staging/quatech_usb2/quatech_usb2.c | 2 +- drivers/staging/rtl8192su/r8192U_core.c | 2 +- drivers/staging/rtl8192u/r8192U_core.c | 2 +- drivers/staging/serqt_usb2/serqt_usb2.c | 2 +- drivers/staging/winbond/wbusb.c | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/asus_oled/asus_oled.c b/drivers/staging/asus_oled/asus_oled.c index c597fb27bd53..cadb6f7321ad 100644 --- a/drivers/staging/asus_oled/asus_oled.c +++ b/drivers/staging/asus_oled/asus_oled.c @@ -87,7 +87,7 @@ struct oled_dev_desc_str { }; /* table of devices that work with this driver */ -static struct usb_device_id id_table[] = { +static const struct usb_device_id id_table[] = { /* Asus G1/G2 (and variants)*/ { USB_DEVICE(USB_VENDOR_ID_ASUS, USB_DEVICE_ID_ASUS_LCM) }, /* Asus G50V (and possibly others - G70? G71?)*/ diff --git a/drivers/staging/comedi/drivers/dt9812.c b/drivers/staging/comedi/drivers/dt9812.c index 312f4f282bd7..96caae36279c 100644 --- a/drivers/staging/comedi/drivers/dt9812.c +++ b/drivers/staging/comedi/drivers/dt9812.c @@ -264,7 +264,7 @@ struct dt9812_usb_cmd { static DECLARE_MUTEX(dt9812_mutex); -static struct usb_device_id dt9812_table[] = { +static const struct usb_device_id dt9812_table[] = { {USB_DEVICE(0x0867, 0x9812)}, {} /* Terminating entry */ }; diff --git a/drivers/staging/comedi/drivers/usbdux.c b/drivers/staging/comedi/drivers/usbdux.c index 9a1b559c4b0d..0c854a6f1ca6 100644 --- a/drivers/staging/comedi/drivers/usbdux.c +++ b/drivers/staging/comedi/drivers/usbdux.c @@ -2833,7 +2833,7 @@ static struct comedi_driver driver_usbdux = { }; /* Table with the USB-devices: just now only testing IDs */ -static struct usb_device_id usbduxsub_table[] = { +static const struct usb_device_id usbduxsub_table[] = { {USB_DEVICE(0x13d8, 0x0001)}, {USB_DEVICE(0x13d8, 0x0002)}, {} /* Terminating entry */ diff --git a/drivers/staging/comedi/drivers/usbduxfast.c b/drivers/staging/comedi/drivers/usbduxfast.c index 2e675cce7dbf..4ff48860fc57 100644 --- a/drivers/staging/comedi/drivers/usbduxfast.c +++ b/drivers/staging/comedi/drivers/usbduxfast.c @@ -1769,7 +1769,7 @@ static struct comedi_driver driver_usbduxfast = { /* * Table with the USB-devices: just now only testing IDs */ -static struct usb_device_id usbduxfastsub_table[] = { +static const struct usb_device_id usbduxfastsub_table[] = { /* { USB_DEVICE(0x4b4, 0x8613) }, testing */ {USB_DEVICE(0x13d8, 0x0010)}, /* real ID */ {USB_DEVICE(0x13d8, 0x0011)}, /* real ID */ diff --git a/drivers/staging/comedi/drivers/vmk80xx.c b/drivers/staging/comedi/drivers/vmk80xx.c index c34a0b9141e2..6479c38d0278 100644 --- a/drivers/staging/comedi/drivers/vmk80xx.c +++ b/drivers/staging/comedi/drivers/vmk80xx.c @@ -75,7 +75,7 @@ enum { DEVICE_VMK8061 }; -static struct usb_device_id vmk80xx_id_table[] = { +static const struct usb_device_id vmk80xx_id_table[] = { {USB_DEVICE(0x10cf, 0x5500), .driver_info = DEVICE_VMK8055}, {USB_DEVICE(0x10cf, 0x5501), .driver_info = DEVICE_VMK8055}, {USB_DEVICE(0x10cf, 0x5502), .driver_info = DEVICE_VMK8055}, diff --git a/drivers/staging/frontier/alphatrack.c b/drivers/staging/frontier/alphatrack.c index 15aed87fe1bb..a50a21518a8e 100644 --- a/drivers/staging/frontier/alphatrack.c +++ b/drivers/staging/frontier/alphatrack.c @@ -58,7 +58,7 @@ #endif /* table of devices that work with this driver */ -static struct usb_device_id usb_alphatrack_table[] = { +static const struct usb_device_id usb_alphatrack_table[] = { {USB_DEVICE(VENDOR_ID, PRODUCT_ID)}, {} /* Terminating entry */ }; diff --git a/drivers/staging/frontier/tranzport.c b/drivers/staging/frontier/tranzport.c index ef8fcc8c67bd..2f03f43f3a2e 100644 --- a/drivers/staging/frontier/tranzport.c +++ b/drivers/staging/frontier/tranzport.c @@ -55,7 +55,7 @@ #endif /* table of devices that work with this driver */ -static struct usb_device_id usb_tranzport_table[] = { +static const struct usb_device_id usb_tranzport_table[] = { {USB_DEVICE(VENDOR_ID, PRODUCT_ID)}, {} /* Terminating entry */ }; diff --git a/drivers/staging/go7007/go7007-usb.c b/drivers/staging/go7007/go7007-usb.c index 1e89dc04ec23..baace8367cb0 100644 --- a/drivers/staging/go7007/go7007-usb.c +++ b/drivers/staging/go7007/go7007-usb.c @@ -444,7 +444,7 @@ static struct go7007_usb_board board_sensoray_2250 = { }, }; -static struct usb_device_id go7007_usb_id_table[] = { +static const struct usb_device_id go7007_usb_id_table[] = { { .match_flags = USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION | USB_DEVICE_ID_MATCH_INT_INFO, diff --git a/drivers/staging/go7007/s2250-loader.c b/drivers/staging/go7007/s2250-loader.c index c152ab9be2fb..ef833e0d63ae 100644 --- a/drivers/staging/go7007/s2250-loader.c +++ b/drivers/staging/go7007/s2250-loader.c @@ -148,7 +148,7 @@ static void s2250loader_disconnect(struct usb_interface *interface) unlock_kernel(); } -static struct usb_device_id s2250loader_ids[] = { +static const struct usb_device_id s2250loader_ids[] = { {USB_DEVICE(0x1943, 0xa250)}, {} /* Terminating entry */ }; diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c index e4078a92d399..0392a4bc8cc8 100644 --- a/drivers/staging/line6/driver.c +++ b/drivers/staging/line6/driver.c @@ -33,7 +33,7 @@ /* table of devices that work with this driver */ -static struct usb_device_id line6_id_table[] = { +static const struct usb_device_id line6_id_table[] = { { USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_BASSPODXT) }, { USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_BASSPODXTLIVE) }, { USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_BASSPODXTPRO) }, diff --git a/drivers/staging/otus/zdusb.c b/drivers/staging/otus/zdusb.c index 2a6d937ba5e8..4cd9b7f5a887 100644 --- a/drivers/staging/otus/zdusb.c +++ b/drivers/staging/otus/zdusb.c @@ -45,7 +45,7 @@ MODULE_LICENSE("Dual BSD/GPL"); static const char driver_name[] = "Otus"; /* table of devices that work with this driver */ -static struct usb_device_id zd1221_ids [] = { +static const struct usb_device_id zd1221_ids[] = { { USB_DEVICE(VENDOR_ATHR, PRODUCT_AR9170) }, { USB_DEVICE(VENDOR_DLINK, PRODUCT_DWA160A) }, { USB_DEVICE(VENDOR_NETGEAR, PRODUCT_WNDA3100) }, diff --git a/drivers/staging/quatech_usb2/quatech_usb2.c b/drivers/staging/quatech_usb2/quatech_usb2.c index f7726f1d3641..1561f74a413b 100644 --- a/drivers/staging/quatech_usb2/quatech_usb2.c +++ b/drivers/staging/quatech_usb2/quatech_usb2.c @@ -116,7 +116,7 @@ static int debug; #define FOURTHCHAR ((unsigned char *)(urb->transfer_buffer))[i + 3] #define FIFTHCHAR ((unsigned char *)(urb->transfer_buffer))[i + 4] -static struct usb_device_id quausb2_id_table[] = { +static const struct usb_device_id quausb2_id_table[] = { {USB_DEVICE(USB_VENDOR_ID_QUATECH, QUATECH_SSU2_100)}, {USB_DEVICE(USB_VENDOR_ID_QUATECH, QUATECH_DSU2_100)}, {USB_DEVICE(USB_VENDOR_ID_QUATECH, QUATECH_DSU2_400)}, diff --git a/drivers/staging/rtl8192su/r8192U_core.c b/drivers/staging/rtl8192su/r8192U_core.c index f15be1eca324..23d1d35be7ed 100644 --- a/drivers/staging/rtl8192su/r8192U_core.c +++ b/drivers/staging/rtl8192su/r8192U_core.c @@ -110,7 +110,7 @@ u32 rt_global_debug_component = \ #define TOTAL_CAM_ENTRY 32 #define CAM_CONTENT_COUNT 8 -static struct usb_device_id rtl8192_usb_id_tbl[] = { +static const struct usb_device_id rtl8192_usb_id_tbl[] = { /* Realtek */ {USB_DEVICE(0x0bda, 0x8192)}, {USB_DEVICE(0x0bda, 0x8709)}, diff --git a/drivers/staging/rtl8192u/r8192U_core.c b/drivers/staging/rtl8192u/r8192U_core.c index 7cf7ea703bba..f1e085ba1cf1 100644 --- a/drivers/staging/rtl8192u/r8192U_core.c +++ b/drivers/staging/rtl8192u/r8192U_core.c @@ -104,7 +104,7 @@ u32 rt_global_debug_component = \ #define TOTAL_CAM_ENTRY 32 #define CAM_CONTENT_COUNT 8 -static struct usb_device_id rtl8192_usb_id_tbl[] = { +static const struct usb_device_id rtl8192_usb_id_tbl[] = { /* Realtek */ {USB_DEVICE(0x0bda, 0x8192)}, {USB_DEVICE(0x0bda, 0x8709)}, diff --git a/drivers/staging/serqt_usb2/serqt_usb2.c b/drivers/staging/serqt_usb2/serqt_usb2.c index 060e9de3b065..375a50580a28 100644 --- a/drivers/staging/serqt_usb2/serqt_usb2.c +++ b/drivers/staging/serqt_usb2/serqt_usb2.c @@ -126,7 +126,7 @@ static int debug; #define MODEM_CTRL 0x40 #define RS232_MODE 0x00 -static struct usb_device_id serqt_id_table[] = { +static const struct usb_device_id serqt_id_table[] = { {USB_DEVICE(USB_VENDOR_ID_QUATECH, QUATECH_SSU100)}, {USB_DEVICE(USB_VENDOR_ID_QUATECH, QUATECH_SSU200)}, {USB_DEVICE(USB_VENDOR_ID_QUATECH, QUATECH_DSU100)}, diff --git a/drivers/staging/winbond/wbusb.c b/drivers/staging/winbond/wbusb.c index 1c5876359491..ecf418dcefd9 100644 --- a/drivers/staging/winbond/wbusb.c +++ b/drivers/staging/winbond/wbusb.c @@ -23,7 +23,7 @@ MODULE_DESCRIPTION("IS89C35 802.11bg WLAN USB Driver"); MODULE_LICENSE("GPL"); MODULE_VERSION("0.1"); -static struct usb_device_id wb35_table[] __devinitdata = { +static const struct usb_device_id wb35_table[] __devinitconst = { { USB_DEVICE(0x0416, 0x0035) }, { USB_DEVICE(0x18E8, 0x6201) }, { USB_DEVICE(0x18E8, 0x6206) }, -- cgit v1.2.3 From b76a32638d9d7d6b421fccce02e667007509bd7b Mon Sep 17 00:00:00 2001 From: Németh Márton Date: Sun, 10 Jan 2010 00:18:41 +0100 Subject: staging: make i2c device id constant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The id_table field of the struct i2c_driver is constant in so it is worth to make the initialization data also constant. The semantic match that finds this kind of pattern is as follows: (http://coccinelle.lip6.fr/) // @r@ disable decl_init,const_decl_init; identifier I1, I2, x; @@ struct I1 { ... const struct I2 *x; ... }; @s@ identifier r.I1, y; identifier r.x, E; @@ struct I1 y = { .x = E, }; @c@ identifier r.I2; identifier s.E; @@ const struct I2 E[] = ... ; @depends on !c@ identifier r.I2; identifier s.E; @@ + const struct I2 E[] = ...; // Signed-off-by: Németh Márton Cc: Julia Lawall Cc: cocci@diku.dk Signed-off-by: Greg Kroah-Hartman --- drivers/staging/go7007/s2250-board.c | 2 +- drivers/staging/go7007/wis-ov7640.c | 2 +- drivers/staging/go7007/wis-saa7113.c | 2 +- drivers/staging/go7007/wis-saa7115.c | 2 +- drivers/staging/go7007/wis-sony-tuner.c | 2 +- drivers/staging/go7007/wis-tw2804.c | 2 +- drivers/staging/go7007/wis-tw9903.c | 2 +- drivers/staging/go7007/wis-uda1342.c | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/go7007/s2250-board.c b/drivers/staging/go7007/s2250-board.c index 8cf7f2750b3f..977df137a0cc 100644 --- a/drivers/staging/go7007/s2250-board.c +++ b/drivers/staging/go7007/s2250-board.c @@ -667,7 +667,7 @@ static int s2250_remove(struct i2c_client *client) return 0; } -static struct i2c_device_id s2250_id[] = { +static const struct i2c_device_id s2250_id[] = { { "s2250", 0 }, { } }; diff --git a/drivers/staging/go7007/wis-ov7640.c b/drivers/staging/go7007/wis-ov7640.c index 04d6d3a498a3..4f0cbdde2765 100644 --- a/drivers/staging/go7007/wis-ov7640.c +++ b/drivers/staging/go7007/wis-ov7640.c @@ -77,7 +77,7 @@ static int wis_ov7640_remove(struct i2c_client *client) return 0; } -static struct i2c_device_id wis_ov7640_id[] = { +static const struct i2c_device_id wis_ov7640_id[] = { { "wis_ov7640", 0 }, { } }; diff --git a/drivers/staging/go7007/wis-saa7113.c b/drivers/staging/go7007/wis-saa7113.c index 9ab893bd204e..d196e16fe72b 100644 --- a/drivers/staging/go7007/wis-saa7113.c +++ b/drivers/staging/go7007/wis-saa7113.c @@ -304,7 +304,7 @@ static int wis_saa7113_remove(struct i2c_client *client) return 0; } -static struct i2c_device_id wis_saa7113_id[] = { +static const struct i2c_device_id wis_saa7113_id[] = { { "wis_saa7113", 0 }, { } }; diff --git a/drivers/staging/go7007/wis-saa7115.c b/drivers/staging/go7007/wis-saa7115.c index 8687ad2de761..0f2b4a0ceccf 100644 --- a/drivers/staging/go7007/wis-saa7115.c +++ b/drivers/staging/go7007/wis-saa7115.c @@ -437,7 +437,7 @@ static int wis_saa7115_remove(struct i2c_client *client) return 0; } -static struct i2c_device_id wis_saa7115_id[] = { +static const struct i2c_device_id wis_saa7115_id[] = { { "wis_saa7115", 0 }, { } }; diff --git a/drivers/staging/go7007/wis-sony-tuner.c b/drivers/staging/go7007/wis-sony-tuner.c index 086896cec49b..c723e4aa7147 100644 --- a/drivers/staging/go7007/wis-sony-tuner.c +++ b/drivers/staging/go7007/wis-sony-tuner.c @@ -688,7 +688,7 @@ static int wis_sony_tuner_remove(struct i2c_client *client) return 0; } -static struct i2c_device_id wis_sony_tuner_id[] = { +static const struct i2c_device_id wis_sony_tuner_id[] = { { "wis_sony_tuner", 0 }, { } }; diff --git a/drivers/staging/go7007/wis-tw2804.c b/drivers/staging/go7007/wis-tw2804.c index e15794a2a0ae..1983839f554d 100644 --- a/drivers/staging/go7007/wis-tw2804.c +++ b/drivers/staging/go7007/wis-tw2804.c @@ -327,7 +327,7 @@ static int wis_tw2804_remove(struct i2c_client *client) return 0; } -static struct i2c_device_id wis_tw2804_id[] = { +static const struct i2c_device_id wis_tw2804_id[] = { { "wis_tw2804", 0 }, { } }; diff --git a/drivers/staging/go7007/wis-tw9903.c b/drivers/staging/go7007/wis-tw9903.c index 506dca6e942e..f97e2be3c0b5 100644 --- a/drivers/staging/go7007/wis-tw9903.c +++ b/drivers/staging/go7007/wis-tw9903.c @@ -309,7 +309,7 @@ static int wis_tw9903_remove(struct i2c_client *client) return 0; } -static struct i2c_device_id wis_tw9903_id[] = { +static const struct i2c_device_id wis_tw9903_id[] = { { "wis_tw9903", 0 }, { } }; diff --git a/drivers/staging/go7007/wis-uda1342.c b/drivers/staging/go7007/wis-uda1342.c index 739c7ae8913f..5c4eb49d7357 100644 --- a/drivers/staging/go7007/wis-uda1342.c +++ b/drivers/staging/go7007/wis-uda1342.c @@ -82,7 +82,7 @@ static int wis_uda1342_remove(struct i2c_client *client) return 0; } -static struct i2c_device_id wis_uda1342_id[] = { +static const struct i2c_device_id wis_uda1342_id[] = { { "wis_uda1342", 0 }, { } }; -- cgit v1.2.3 From 3bf040c75294ad9470b11902477e2c07af2031bd Mon Sep 17 00:00:00 2001 From: Minchan Kim Date: Mon, 11 Jan 2010 16:15:53 +0900 Subject: Staging: ramzswap: Free memory when create_device is failed If create_device is failed, it can't free gendisk and request_queue of preceding devices. It cause memory leak. This patch fixes it. Signed-off-by: Minchan Kim Acked-by: Nitin Gupta Signed-off-by: Greg Kroah-Hartman --- drivers/staging/ramzswap/ramzswap_drv.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/ramzswap/ramzswap_drv.c b/drivers/staging/ramzswap/ramzswap_drv.c index 7a7ead4e6c87..baf757259d0b 100644 --- a/drivers/staging/ramzswap/ramzswap_drv.c +++ b/drivers/staging/ramzswap/ramzswap_drv.c @@ -1292,7 +1292,7 @@ static struct block_device_operations ramzswap_devops = { .owner = THIS_MODULE, }; -static void create_device(struct ramzswap *rzs, int device_id) +static int create_device(struct ramzswap *rzs, int device_id) { mutex_init(&rzs->lock); INIT_LIST_HEAD(&rzs->backing_swap_extent_list); @@ -1301,7 +1301,7 @@ static void create_device(struct ramzswap *rzs, int device_id) if (!rzs->queue) { pr_err("Error allocating disk queue for device %d\n", device_id); - return; + return 0; } blk_queue_make_request(rzs->queue, ramzswap_make_request); @@ -1313,7 +1313,7 @@ static void create_device(struct ramzswap *rzs, int device_id) blk_cleanup_queue(rzs->queue); pr_warning("Error allocating disk structure for device %d\n", device_id); - return; + return 0; } rzs->disk->major = ramzswap_major; @@ -1331,6 +1331,7 @@ static void create_device(struct ramzswap *rzs, int device_id) add_disk(rzs->disk); rzs->init_done = 0; + return 1; } static void destroy_device(struct ramzswap *rzs) @@ -1368,16 +1369,20 @@ static int __init ramzswap_init(void) /* Allocate the device array and initialize each one */ pr_info("Creating %u devices ...\n", num_devices); devices = kzalloc(num_devices * sizeof(struct ramzswap), GFP_KERNEL); - if (!devices) { - ret = -ENOMEM; + if (!devices) goto out; - } for (i = 0; i < num_devices; i++) - create_device(&devices[i], i); - + if (!create_device(&devices[i], i)) { + ret = i; + goto free_devices; + } return 0; +free_devices: + for (i = 0; i < ret; i++) + destroy_device(&devices[i]); out: + ret = -ENOMEM; unregister_blkdev(ramzswap_major, "ramzswap"); return ret; } -- cgit v1.2.3 From 53cf8743d227283e78c27ada407b506014c9223d Mon Sep 17 00:00:00 2001 From: Jeff Mahoney Date: Mon, 11 Jan 2010 10:54:25 -0500 Subject: Staging: rt2860: Use skb_tail_pointer rt2860 uses skb->tail directly. This patch uses the tail pointer macros instead. Signed-off-by: Jeff Mahoney Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rt2860/rt_linux.c | 10 +++++----- drivers/staging/rt2860/rt_linux.h | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rt2860/rt_linux.c b/drivers/staging/rt2860/rt_linux.c index 9357fb26cc2a..9d763b4f2261 100644 --- a/drivers/staging/rt2860/rt_linux.c +++ b/drivers/staging/rt2860/rt_linux.c @@ -462,9 +462,9 @@ void *duplicate_pkt(struct rt_rtmp_adapter *pAd, if ((skb = __dev_alloc_skb(HdrLen + DataSize + 2, MEM_ALLOC_FLAG)) != NULL) { skb_reserve(skb, 2); - NdisMoveMemory(skb->tail, pHeader802_3, HdrLen); + NdisMoveMemory(skb_tail_pointer(skb), pHeader802_3, HdrLen); skb_put(skb, HdrLen); - NdisMoveMemory(skb->tail, pData, DataSize); + NdisMoveMemory(skb_tail_pointer(skb), pData, DataSize); skb_put(skb, DataSize); skb->dev = get_netdev_from_bssid(pAd, FromWhichBSSID); pPacket = OSPKT_TO_RTPKT(skb); @@ -515,7 +515,7 @@ void *ClonePacket(struct rt_rtmp_adapter *pAd, pClonedPkt->dev = pRxPkt->dev; pClonedPkt->data = pData; pClonedPkt->len = DataSize; - pClonedPkt->tail = pClonedPkt->data + pClonedPkt->len; + skb_set_tail_pointer(pClonedPkt, DataSize) ASSERT(DataSize < 1530); } return pClonedPkt; @@ -535,7 +535,7 @@ void update_os_packet_info(struct rt_rtmp_adapter *pAd, pOSPkt->dev = get_netdev_from_bssid(pAd, FromWhichBSSID); pOSPkt->data = pRxBlk->pData; pOSPkt->len = pRxBlk->DataSize; - pOSPkt->tail = pOSPkt->data + pOSPkt->len; + skb_set_tail_pointer(pOSPkt, pOSPkt->len); } void wlan_802_11_to_802_3_packet(struct rt_rtmp_adapter *pAd, @@ -553,7 +553,7 @@ void wlan_802_11_to_802_3_packet(struct rt_rtmp_adapter *pAd, pOSPkt->dev = get_netdev_from_bssid(pAd, FromWhichBSSID); pOSPkt->data = pRxBlk->pData; pOSPkt->len = pRxBlk->DataSize; - pOSPkt->tail = pOSPkt->data + pOSPkt->len; + skb_set_tail_pointer(pOSPkt, pOSPkt->len); /* */ /* copy 802.3 header */ diff --git a/drivers/staging/rt2860/rt_linux.h b/drivers/staging/rt2860/rt_linux.h index f85508d9d5a9..a7c540f8e3e3 100644 --- a/drivers/staging/rt2860/rt_linux.h +++ b/drivers/staging/rt2860/rt_linux.h @@ -658,9 +658,9 @@ void linux_pci_unmap_single(void *handle, dma_addr_t dma_addr, size_t size, (RTPKT_TO_OSPKT(_pkt)->len) = (_len) #define GET_OS_PKT_DATATAIL(_pkt) \ - (RTPKT_TO_OSPKT(_pkt)->tail) + (skb_tail_pointer(RTPKT_TO_OSPKT(_pkt)) #define SET_OS_PKT_DATATAIL(_pkt, _start, _len) \ - ((RTPKT_TO_OSPKT(_pkt))->tail) = (u8 *)((_start) + (_len)) + (skb_set_tail_pointer(RTPKT_TO_OSPKT(_pkt), _len)) #define GET_OS_PKT_HEAD(_pkt) \ (RTPKT_TO_OSPKT(_pkt)->head) -- cgit v1.2.3 From 1c7ec2e8e0fb6e8acda4f6b9a682cf7f8e650e2f Mon Sep 17 00:00:00 2001 From: Jeff Mahoney Date: Mon, 11 Jan 2010 10:54:27 -0500 Subject: Staging: rtl8192e: Use skb_tail_pointer rtl8192e uses skb->tail directly. This patch uses the tail pointer macros instead. Signed-off-by: Jeff Mahoney Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/r8192E_core.c | 5 ++--- drivers/staging/rtl8192e/r819xE_cmdpkt.c | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192e/r8192E_core.c b/drivers/staging/rtl8192e/r8192E_core.c index 50c760284df4..886105db8b7c 100644 --- a/drivers/staging/rtl8192e/r8192E_core.c +++ b/drivers/staging/rtl8192e/r8192E_core.c @@ -1807,7 +1807,7 @@ static short rtl8192_alloc_rx_desc_ring(struct net_device *dev) return 0; priv->rx_buf[i] = skb; mapping = (dma_addr_t *)skb->cb; - *mapping = pci_map_single(priv->pdev, skb->tail,//skb_tail_pointer(skb), + *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb), priv->rxbuffersize, PCI_DMA_FROMDEVICE); entry->BufferAddress = cpu_to_le32(*mapping); @@ -6287,8 +6287,7 @@ static void rtl8192_rx(struct net_device *dev) skb = new_skb; priv->rx_buf[priv->rx_idx] = skb; - *((dma_addr_t *) skb->cb) = pci_map_single(priv->pdev, skb->tail, priv->rxbuffersize, PCI_DMA_FROMDEVICE); -// *((dma_addr_t *) skb->cb) = pci_map_single(priv->pdev, skb_tail_pointer(skb), priv->rxbuffersize, PCI_DMA_FROMDEVICE); + *((dma_addr_t *) skb->cb) = pci_map_single(priv->pdev, skb_tail_pointer(skb), priv->rxbuffersize, PCI_DMA_FROMDEVICE); } } diff --git a/drivers/staging/rtl8192e/r819xE_cmdpkt.c b/drivers/staging/rtl8192e/r819xE_cmdpkt.c index 2aaa4e1bb375..87c334fb7333 100644 --- a/drivers/staging/rtl8192e/r819xE_cmdpkt.c +++ b/drivers/staging/rtl8192e/r819xE_cmdpkt.c @@ -135,7 +135,7 @@ RT_STATUS cmpk_message_handle_tx( * Transform from little endian to big endian * and pending zero */ - seg_ptr = skb->tail; + seg_ptr = skb_tail_pointer(skb); for(i=0 ; i < frag_length; i+=4) { *seg_ptr++ = ((i+0) Date: Mon, 11 Jan 2010 10:54:29 -0500 Subject: Staging: rtl8192u: dont use -mhard-float rtl8192u uses -mhard-float, which doesn't exist on ia64. Since in-kernel floating-point isn't allowed, this is implied anyway. Signed-off-by: Jeff Mahoney Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192u/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192u/Makefile b/drivers/staging/rtl8192u/Makefile index 2d59c4ef6c5b..738f4a80ec67 100644 --- a/drivers/staging/rtl8192u/Makefile +++ b/drivers/staging/rtl8192u/Makefile @@ -3,7 +3,7 @@ NIC_SELECT = RTL8192U EXTRA_CFLAGS += -std=gnu89 EXTRA_CFLAGS += -O2 -EXTRA_CFLAGS += -mhard-float -DCONFIG_FORCE_HARD_FLOAT=y +EXTRA_CFLAGS += -DCONFIG_FORCE_HARD_FLOAT=y EXTRA_CFLAGS += -DJACKSON_NEW_8187 -DJACKSON_NEW_RX EXTRA_CFLAGS += -DTHOMAS_BEACON -DTHOMAS_TASKLET -DTHOMAS_SKB -DTHOMAS_TURBO #EXTRA_CFLAGS += -DUSB_TX_DRIVER_AGGREGATION_ENABLE -- cgit v1.2.3 From 23639126523b274e094515b609c987e927284920 Mon Sep 17 00:00:00 2001 From: Jeff Mahoney Date: Mon, 11 Jan 2010 10:54:30 -0500 Subject: Staging: otus: fix assignment makes integer from pointer without a cast warnings This patch fixes some %x pointer printing to %p. It also uses the skb_tail_pointer and skb_mac_header macros for accessing thos members. Signed-off-by: Jeff Mahoney Signed-off-by: Greg Kroah-Hartman --- drivers/staging/otus/usbdrv.c | 4 ++-- drivers/staging/otus/wrap_pkt.c | 10 ++-------- 2 files changed, 4 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/otus/usbdrv.c b/drivers/staging/otus/usbdrv.c index b0adbc8b2dc2..5e6a12037b12 100644 --- a/drivers/staging/otus/usbdrv.c +++ b/drivers/staging/otus/usbdrv.c @@ -829,7 +829,7 @@ int zfLnxRegisterVapDev(struct net_device* parentDev, u16_t vapId) { /* Allocate net device structure */ vap[vapId].dev = alloc_etherdev(0); - printk("Register vap dev=%x\n", (u32_t)vap[vapId].dev); + printk("Register vap dev=%p\n", vap[vapId].dev); if(vap[vapId].dev == NULL) { printk("alloc_etherdev fail\n"); @@ -883,7 +883,7 @@ int zfLnxUnregisterVapDev(struct net_device* parentDev, u16_t vapId) printk("Unregister VAP dev : %s\n", vap[vapId].dev->name); if(vap[vapId].dev != NULL) { - printk("Unregister vap dev=%x\n", (u32_t)vap[vapId].dev); + printk("Unregister vap dev=%p\n", vap[vapId].dev); // //unregister_netdevice(wds[wdsId].dev); unregister_netdev(vap[vapId].dev); diff --git a/drivers/staging/otus/wrap_pkt.c b/drivers/staging/otus/wrap_pkt.c index 75bb952fd0a5..a2f5cb1f5298 100644 --- a/drivers/staging/otus/wrap_pkt.c +++ b/drivers/staging/otus/wrap_pkt.c @@ -58,7 +58,7 @@ void zfLnxRecv80211(zdev_t *dev, zbuf_t *buf, struct zsAdditionInfo *addInfo) skb1 = skb_copy(buf, GFP_ATOMIC); if (skb1 != NULL) { skb1->dev = dev; - skb1->mac_header = skb1->data; + skb_reset_mac_header(skb1); skb1->ip_summed = CHECKSUM_NONE; skb1->pkt_type = PACKET_OTHERHOST; /* ETH_P_80211_RAW */ @@ -85,13 +85,7 @@ void zfLnxRecvEth(zdev_t *dev, zbuf_t *buf, u16_t port) /* new_buf = dev_alloc_skb(2048); */ new_buf = dev_alloc_skb(buf->len); -#ifdef NET_SKBUFF_DATA_USES_OFFSET - new_buf->tail = 0; - new_buf->len = 0; -#else - new_buf->tail = new_buf->data; - new_buf->len = 0; -#endif + skb_reset_tail_pointer(new_buf); skb_put(new_buf, buf->len); memcpy(new_buf->data, buf->data, buf->len); -- cgit v1.2.3 From 362f46e3ab6ee4fc771da55067921c39dd13877d Mon Sep 17 00:00:00 2001 From: Jeff Mahoney Date: Mon, 11 Jan 2010 10:54:31 -0500 Subject: Staging: vme/tsi148: Depend on VIRT_TO_BUS This driver depends on virt_to_bus working correctly, but it doesn't exist on ppc64 (and probably other arches). Signed-off-by: Jeff Mahoney Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/bridges/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/staging/vme/bridges/Kconfig b/drivers/staging/vme/bridges/Kconfig index 023cceba0c59..66c49f5d8db8 100644 --- a/drivers/staging/vme/bridges/Kconfig +++ b/drivers/staging/vme/bridges/Kconfig @@ -8,6 +8,7 @@ config VME_CA91CX42 config VME_TSI148 tristate "Tempe" + depends on VIRT_TO_BUS help If you say Y here you get support for the Tundra TSI148 VME bridge chip. -- cgit v1.2.3 From 32dbb67138fdb8cefa348d29850eb9a9ce964e09 Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Mon, 11 Jan 2010 21:08:02 +0300 Subject: Staging: dream: HTC Dream camera, not need sizeof http://bugzilla.kernel.org/show_bug.cgi?id=14825 sizeof(extlen), always will be sizeof( unit32_t) or 4 It seems that something is wrong?!?! Signed-off-by: Pavel Vasilyev Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dream/camera/msm_vfe7x.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dream/camera/msm_vfe7x.c b/drivers/staging/dream/camera/msm_vfe7x.c index 33ab3ac6ac57..62fd24d632d5 100644 --- a/drivers/staging/dream/camera/msm_vfe7x.c +++ b/drivers/staging/dream/camera/msm_vfe7x.c @@ -255,8 +255,7 @@ static int vfe_7x_init(struct msm_vfe_callback *presp, extlen = sizeof(struct vfe_frame_extra); - extdata = - kmalloc(sizeof(extlen), GFP_ATOMIC); + extdata = kmalloc(extlen, GFP_ATOMIC); if (!extdata) { rc = -ENOMEM; goto init_fail; -- cgit v1.2.3 From 5d929a71908968905331cda0d52c44570d402110 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Wed, 13 Jan 2010 23:36:09 +0000 Subject: staging: declare MODULE_FIRMWARE in various drivers Signed-off-by: Ben Hutchings Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/jr3_pci.c | 2 ++ drivers/staging/go7007/go7007-driver.c | 2 ++ drivers/staging/go7007/go7007-usb.c | 2 ++ drivers/staging/go7007/saa7134-go7007.c | 1 + drivers/staging/rtl8192e/r819xE_firmware.c | 4 ++++ drivers/staging/rtl8192su/r8192S_firmware.c | 1 + drivers/staging/slicoss/slicoss.c | 6 ++++++ drivers/staging/wlan-ng/prism2fw.c | 1 + 8 files changed, 19 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/jr3_pci.c b/drivers/staging/comedi/drivers/jr3_pci.c index bd397840dcba..fe5b4953f7ec 100644 --- a/drivers/staging/comedi/drivers/jr3_pci.c +++ b/drivers/staging/comedi/drivers/jr3_pci.c @@ -954,6 +954,8 @@ out: return result; } +MODULE_FIRMWARE("comedi/jr3pci.idm"); + static int jr3_pci_detach(struct comedi_device *dev) { int i; diff --git a/drivers/staging/go7007/go7007-driver.c b/drivers/staging/go7007/go7007-driver.c index fb1345ffb858..d42ba1696999 100644 --- a/drivers/staging/go7007/go7007-driver.c +++ b/drivers/staging/go7007/go7007-driver.c @@ -128,6 +128,8 @@ static int go7007_load_encoder(struct go7007 *go) return rv; } +MODULE_FIRMWARE("go7007fw.bin"); + /* * Boot the encoder and register the I2C adapter if requested. Do the * minimum initialization necessary, since the board-specific code may diff --git a/drivers/staging/go7007/go7007-usb.c b/drivers/staging/go7007/go7007-usb.c index baace8367cb0..ee278f64a16b 100644 --- a/drivers/staging/go7007/go7007-usb.c +++ b/drivers/staging/go7007/go7007-usb.c @@ -444,6 +444,8 @@ static struct go7007_usb_board board_sensoray_2250 = { }, }; +MODULE_FIRMWARE("go7007tv.bin"); + static const struct usb_device_id go7007_usb_id_table[] = { { .match_flags = USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION | diff --git a/drivers/staging/go7007/saa7134-go7007.c b/drivers/staging/go7007/saa7134-go7007.c index 665bbf59d026..b25d7d2090e1 100644 --- a/drivers/staging/go7007/saa7134-go7007.c +++ b/drivers/staging/go7007/saa7134-go7007.c @@ -84,6 +84,7 @@ static struct go7007_board_info board_voyager = { }, }, }; +MODULE_FIRMWARE("go7007tv.bin"); /********************* Driver for GPIO HPI interface *********************/ diff --git a/drivers/staging/rtl8192e/r819xE_firmware.c b/drivers/staging/rtl8192e/r819xE_firmware.c index e05ba1748d30..793a17545554 100644 --- a/drivers/staging/rtl8192e/r819xE_firmware.c +++ b/drivers/staging/rtl8192e/r819xE_firmware.c @@ -365,3 +365,7 @@ download_firmware_fail: rt_status = false; return rt_status; } + +MODULE_FIRMWARE("RTL8192E/boot.img"); +MODULE_FIRMWARE("RTL8192E/main.img"); +MODULE_FIRMWARE("RTL8192E/data.img"); diff --git a/drivers/staging/rtl8192su/r8192S_firmware.c b/drivers/staging/rtl8192su/r8192S_firmware.c index 3561adf0468a..ff65bd125afc 100644 --- a/drivers/staging/rtl8192su/r8192S_firmware.c +++ b/drivers/staging/rtl8192su/r8192S_firmware.c @@ -538,3 +538,4 @@ bool FirmwareDownload92S(struct net_device *dev) return rtStatus; } +MODULE_FIRMWARE("RTL8192SU/rtl8192sfw.bin"); diff --git a/drivers/staging/slicoss/slicoss.c b/drivers/staging/slicoss/slicoss.c index 09a9d759c612..87d98e38d3b5 100644 --- a/drivers/staging/slicoss/slicoss.c +++ b/drivers/staging/slicoss/slicoss.c @@ -1866,6 +1866,9 @@ static int slic_card_download_gbrcv(struct adapter *adapter) return 0; } +MODULE_FIRMWARE("slicoss/oasisrcvucode.sys"); +MODULE_FIRMWARE("slicoss/gbrcvucode.sys"); + static int slic_card_download(struct adapter *adapter) { const struct firmware *fw; @@ -1977,6 +1980,9 @@ static int slic_card_download(struct adapter *adapter) return STATUS_SUCCESS; } +MODULE_FIRMWARE("slicoss/oasisdownload.sys"); +MODULE_FIRMWARE("slicoss/gbdownload.sys"); + static void slic_adapter_set_hwaddr(struct adapter *adapter) { struct sliccard *card = adapter->card; diff --git a/drivers/staging/wlan-ng/prism2fw.c b/drivers/staging/wlan-ng/prism2fw.c index aaa70ed57710..5e95c482fb7b 100644 --- a/drivers/staging/wlan-ng/prism2fw.c +++ b/drivers/staging/wlan-ng/prism2fw.c @@ -53,6 +53,7 @@ /* Local Constants */ #define PRISM2_USB_FWFILE "prism2_ru.fw" +MODULE_FIRMWARE(PRISM2_USB_FWFILE); #define S3DATA_MAX 5000 #define S3PLUG_MAX 200 -- cgit v1.2.3 From 4401e8243d2e02a991a475eea11885a56f854f69 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Wed, 13 Jan 2010 23:36:27 +0000 Subject: Staging: sep: include driver name in firmware filenames The current names "cache.image.bin" and "resident.image.bin" are far too generic. Signed-off-by: Ben Hutchings Signed-off-by: Greg Kroah-Hartman --- drivers/staging/sep/sep_driver.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/sep/sep_driver.c b/drivers/staging/sep/sep_driver.c index 09346c92e94d..96453cb4f16a 100644 --- a/drivers/staging/sep/sep_driver.c +++ b/drivers/staging/sep/sep_driver.c @@ -183,8 +183,8 @@ static DECLARE_WAIT_QUEUE_HEAD(sep_event); static int sep_load_firmware(struct sep_device *sep) { const struct firmware *fw; - char *cache_name = "cache.image.bin"; - char *res_name = "resident.image.bin"; + char *cache_name = "sep/cache.image.bin"; + char *res_name = "sep/resident.image.bin"; int error; edbg("SEP Driver:rar_virtual is %p\n", sep->rar_addr); -- cgit v1.2.3 From e4c3a24dc5c318e57e5295a54f03eb8ae54d9ffa Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Wed, 13 Jan 2010 23:36:46 +0000 Subject: Staging: sep: declare MODULE_FIRMWARE Signed-off-by: Ben Hutchings Signed-off-by: Greg Kroah-Hartman --- drivers/staging/sep/sep_driver.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/sep/sep_driver.c b/drivers/staging/sep/sep_driver.c index 96453cb4f16a..8ab3be684098 100644 --- a/drivers/staging/sep/sep_driver.c +++ b/drivers/staging/sep/sep_driver.c @@ -223,6 +223,9 @@ static int sep_load_firmware(struct sep_device *sep) return 0; } +MODULE_FIRMWARE("sep/cache.image.bin"); +MODULE_FIRMWARE("sep/resident.image.bin"); + /** * sep_map_and_alloc_shared_area - allocate shared block * @sep: security processor -- cgit v1.2.3 From 9f64859208f3a56f33f2e893e11df585768f1705 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 14 Jan 2010 15:07:23 +0200 Subject: staging: wlags49: don't use custom implementation of atoi() Kernel has its own method called simple_strtoul() to do such things. Here we are using simple_strtoul(value, NULL, 0) because in original function the recognized base is 10 or 16 and input data is assumed to be unsigned. Signed-off-by: Andy Shevchenko Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlags49_h2/wl_main.c | 2 +- drivers/staging/wlags49_h2/wl_profile.c | 76 ++++++++++++++++----------------- drivers/staging/wlags49_h2/wl_util.c | 49 --------------------- drivers/staging/wlags49_h2/wl_util.h | 2 - 4 files changed, 39 insertions(+), 90 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/wlags49_h2/wl_main.c b/drivers/staging/wlags49_h2/wl_main.c index 16764a000942..cf0c38468b20 100644 --- a/drivers/staging/wlags49_h2/wl_main.c +++ b/drivers/staging/wlags49_h2/wl_main.c @@ -3792,7 +3792,7 @@ static int write_int(struct file *file, const char *buffer, unsigned long count, } if (count > 0 ) { proc_number[count] = 0; - nr = wl_atoi( proc_number ); + nr = simple_strtoul(proc_number , NULL, 0); *(unsigned int *)data = nr; if ( nr & 0x8000 ) { //;?kludgy but it is unclear to me were else to place this #if DBG diff --git a/drivers/staging/wlags49_h2/wl_profile.c b/drivers/staging/wlags49_h2/wl_profile.c index 715f027a923f..1e0c75f28557 100644 --- a/drivers/staging/wlags49_h2/wl_profile.c +++ b/drivers/staging/wlags49_h2/wl_profile.c @@ -383,15 +383,15 @@ void translate_option( char *buffer, struct wl_private *lp ) DbgInfo->DebugFlag |= DBG_DEFAULTS; } } else { - DbgInfo->DebugFlag = wl_atoi( value ); //;?DebugFlag; + DbgInfo->DebugFlag = simple_strtoul(value, NULL, 0); //;?DebugFlag; } - DbgInfo->DebugFlag = wl_atoi( value ); //;?Delete ASAP + DbgInfo->DebugFlag = simple_strtoul(value, NULL, 0); //;?Delete ASAP } #endif /* DBG */ if ( strcmp( key, PARM_NAME_AUTH_KEY_MGMT_SUITE ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_AUTH_KEY_MGMT_SUITE, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_AUTH_KEY_MGMT_SUITE ) || ( value_convert <= PARM_MAX_AUTH_KEY_MGMT_SUITE )) { lp->AuthKeyMgmtSuite = value_convert; } else { @@ -401,7 +401,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_BRSC_2GHZ ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_BRSC_2GHZ, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_BRSC ) || ( value_convert <= PARM_MAX_BRSC )) { lp->brsc[0] = value_convert; } else { @@ -411,7 +411,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_BRSC_5GHZ ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_BRSC_5GHZ, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_BRSC ) || ( value_convert <= PARM_MAX_BRSC )) { lp->brsc[1] = value_convert; } else { @@ -448,7 +448,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_ENABLE_ENCRYPTION ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_ENABLE_ENCRYPTION, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_ENABLE_ENCRYPTION ) && ( value_convert <= PARM_MAX_ENABLE_ENCRYPTION )) { lp->EnableEncryption = value_convert; } else { @@ -529,7 +529,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_MULTICAST_RATE ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_MULTICAST_RATE, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_MULTICAST_RATE ) && ( value_convert <= PARM_MAX_MULTICAST_RATE )) { lp->MulticastRate[0] = value_convert; @@ -540,7 +540,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_OWN_CHANNEL ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_OWN_CHANNEL, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if ( wl_is_a_valid_chan( value_convert )) { if ( value_convert > 14 ) { value_convert = value_convert | 0x100; @@ -567,7 +567,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_RTS_THRESHOLD ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_RTS_THRESHOLD, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_RTS_THRESHOLD ) && ( value_convert <= PARM_MAX_RTS_THRESHOLD )) { lp->RTSThreshold = value_convert; } else { @@ -577,7 +577,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_SRSC_2GHZ ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_SRSC_2GHZ, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_SRSC ) || ( value_convert <= PARM_MAX_SRSC )) { lp->srsc[0] = value_convert; } else { @@ -587,7 +587,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_SRSC_5GHZ ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_SRSC_5GHZ, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_SRSC ) || ( value_convert <= PARM_MAX_SRSC )) { lp->srsc[1] = value_convert; } else { @@ -597,7 +597,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_SYSTEM_SCALE ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_SYSTEM_SCALE, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_SYSTEM_SCALE ) && ( value_convert <= PARM_MAX_SYSTEM_SCALE )) { lp->DistanceBetweenAPs = value_convert; } else { @@ -607,9 +607,9 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_TX_KEY ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_TX_KEY, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_TX_KEY ) && ( value_convert <= PARM_MAX_TX_KEY )) { - lp->TransmitKeyID = wl_atoi( value ); + lp->TransmitKeyID = simple_strtoul(value, NULL, 0); } else { DBG_WARNING( DbgInfo, "%s invalid; will be ignored\n", PARM_NAME_TX_KEY ); } @@ -617,7 +617,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_TX_RATE ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_TX_RATE, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_TX_RATE ) && ( value_convert <= PARM_MAX_TX_RATE )) { lp->TxRateControl[0] = value_convert; } else { @@ -627,7 +627,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_TX_POW_LEVEL ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_TX_POW_LEVEL, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_TX_POW_LEVEL ) || ( value_convert <= PARM_MAX_TX_POW_LEVEL )) { lp->txPowLevel = value_convert; } else { @@ -645,7 +645,7 @@ void translate_option( char *buffer, struct wl_private *lp ) if ( strcmp( key, PARM_NAME_PORT_TYPE ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_PORT_TYPE, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert == PARM_MIN_PORT_TYPE ) || ( value_convert == PARM_MAX_PORT_TYPE )) { lp->PortType = value_convert; } else { @@ -654,7 +654,7 @@ void translate_option( char *buffer, struct wl_private *lp ) } else if ( strcmp( key, PARM_NAME_PM_ENABLED ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_PM_ENABLED, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); /* ;? how about wl_main.c containing * VALID_PARAM( PARM_PM_ENABLED <= WVLAN_PM_STATE_STANDARD || * ( PARM_PM_ENABLED & 0x7FFF ) <= WVLAN_PM_STATE_STANDARD ); @@ -677,7 +677,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_MAX_SLEEP ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_MAX_SLEEP, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= 0 ) && ( value_convert <= 65535 )) { lp->MaxSleepDuration = value_convert; } else { @@ -696,7 +696,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_AUTHENTICATION ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_AUTHENTICATION, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_AUTHENTICATION ) && ( value_convert <= PARM_MAX_AUTHENTICATION )) { lp->authentication = value_convert; } else { @@ -706,7 +706,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_OWN_ATIM_WINDOW ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_OWN_ATIM_WINDOW, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_OWN_ATIM_WINDOW ) && ( value_convert <= PARM_MAX_OWN_ATIM_WINDOW )) { lp->atimWindow = value_convert; } else { @@ -716,7 +716,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_PM_HOLDOVER_DURATION ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_PM_HOLDOVER_DURATION, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_PM_HOLDOVER_DURATION ) && ( value_convert <= PARM_MAX_PM_HOLDOVER_DURATION )) { lp->holdoverDuration = value_convert; } else { @@ -730,7 +730,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_CONNECTION_CONTROL ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_CONNECTION_CONTROL, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_CONNECTION_CONTROL ) && ( value_convert <= PARM_MAX_CONNECTION_CONTROL )) { lp->connectionControl = value_convert; } else { @@ -749,7 +749,7 @@ void translate_option( char *buffer, struct wl_private *lp ) if ( strcmp( key, PARM_NAME_OWN_DTIM_PERIOD ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_OWN_DTIM_PERIOD, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if ( value_convert >= PARM_MIN_OWN_DTIM_PERIOD ) { lp->DTIMPeriod = value_convert; } else { @@ -775,7 +775,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_OWN_BEACON_INTERVAL ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_OWN_BEACON_INTERVAL, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if ( value_convert >= PARM_MIN_OWN_BEACON_INTERVAL ) { lp->ownBeaconInterval = value_convert; } else { @@ -785,7 +785,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_COEXISTENCE ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_COEXISTENCE, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if ( value_convert >= PARM_MIN_COEXISTENCE ) { lp->coexistence = value_convert; } else { @@ -797,7 +797,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_RTS_THRESHOLD1 ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_RTS_THRESHOLD1, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_RTS_THRESHOLD ) && ( value_convert <= PARM_MAX_RTS_THRESHOLD )) { lp->wds_port[0].rtsThreshold = value_convert; } else { @@ -807,7 +807,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_RTS_THRESHOLD2 ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_RTS_THRESHOLD2, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_RTS_THRESHOLD ) && ( value_convert <= PARM_MAX_RTS_THRESHOLD )) { lp->wds_port[1].rtsThreshold = value_convert; } else { @@ -817,7 +817,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_RTS_THRESHOLD3 ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_RTS_THRESHOLD3, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_RTS_THRESHOLD ) && ( value_convert <= PARM_MAX_RTS_THRESHOLD )) { lp->wds_port[2].rtsThreshold = value_convert; } else { @@ -827,7 +827,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_RTS_THRESHOLD4 ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_RTS_THRESHOLD4, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_RTS_THRESHOLD ) && ( value_convert <= PARM_MAX_RTS_THRESHOLD )) { lp->wds_port[3].rtsThreshold = value_convert; } else { @@ -837,7 +837,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_RTS_THRESHOLD5 ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_RTS_THRESHOLD5, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_RTS_THRESHOLD ) && ( value_convert <= PARM_MAX_RTS_THRESHOLD )) { lp->wds_port[4].rtsThreshold = value_convert; } else { @@ -847,7 +847,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_RTS_THRESHOLD6 ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_RTS_THRESHOLD6, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_RTS_THRESHOLD ) && ( value_convert <= PARM_MAX_RTS_THRESHOLD )) { lp->wds_port[5].rtsThreshold = value_convert; } else { @@ -857,7 +857,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_TX_RATE1 ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_TX_RATE1, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_TX_RATE ) && ( value_convert <= PARM_MAX_TX_RATE )) { lp->wds_port[0].txRateCntl = value_convert; } else { @@ -867,7 +867,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_TX_RATE2 ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_TX_RATE2, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_TX_RATE ) && ( value_convert <= PARM_MAX_TX_RATE )) { lp->wds_port[1].txRateCntl = value_convert; } else { @@ -877,7 +877,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_TX_RATE3 ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_TX_RATE3, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_TX_RATE ) && ( value_convert <= PARM_MAX_TX_RATE )) { lp->wds_port[2].txRateCntl = value_convert; } else { @@ -887,7 +887,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_TX_RATE4 ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_TX_RATE4, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_TX_RATE ) && ( value_convert <= PARM_MAX_TX_RATE )) { lp->wds_port[3].txRateCntl = value_convert; } else { @@ -897,7 +897,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_TX_RATE5 ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_TX_RATE5, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_TX_RATE ) && ( value_convert <= PARM_MAX_TX_RATE )) { lp->wds_port[4].txRateCntl = value_convert; } else { @@ -907,7 +907,7 @@ void translate_option( char *buffer, struct wl_private *lp ) else if ( strcmp( key, PARM_NAME_TX_RATE6 ) == 0 ) { DBG_TRACE( DbgInfo, "%s, value: %s\n", PARM_NAME_TX_RATE6, value ); - value_convert = wl_atoi( value ); + value_convert = simple_strtoul(value, NULL, 0); if (( value_convert >= PARM_MIN_TX_RATE ) && ( value_convert <= PARM_MAX_TX_RATE )) { lp->wds_port[5].txRateCntl = value_convert; } else { diff --git a/drivers/staging/wlags49_h2/wl_util.c b/drivers/staging/wlags49_h2/wl_util.c index ac1e7f38f982..bbdb9973d1e5 100644 --- a/drivers/staging/wlags49_h2/wl_util.c +++ b/drivers/staging/wlags49_h2/wl_util.c @@ -1536,52 +1536,3 @@ int wl_get_tallies(struct wl_private *lp, return ret; } -/******************************************************************************* - * wl_atoi() - ******************************************************************************* - * - * DESCRIPTION: - * - * Believe it or not, we need our own implementation of atoi in the kernel. - * - * PARAMETERS: - * - * string - the ASCII string to convert to an integer - * - * RETURNS: - * - * unsigned integer - * - ******************************************************************************/ -unsigned int wl_atoi( char *string ) -{ -unsigned int base = 10; //default to decimal -unsigned int value = 0; -unsigned int c; -int i = strlen( string ); - - if ( i > 2 && string[0] == '0' && ( string[1] | ('X'^'x') ) == 'x' ) { - base = 16; - string +=2; - } - while ( ( c = *string++ ) != '\0' ) { - if ( value > UINT_MAX / base ) { //test for overrun - DBG_FUNC( "wl_atoi" ); //don't overload the log file with good messages - DBG_ENTER( DbgInfo ); - DBG_ERROR( DbgInfo, "string \"%s\", lenght exceeds expectations\n", string ); - printk( "<1>string \"%s\", lenght exceeds expectations\n", string ); - DBG_LEAVE( DbgInfo ); - break; - } - c -= '0'; - if ( 0 <= c && c <= 9 ) value = base * value + c; - else if ( base == 16 ) { - c += '0'; - c |= 'A'^'a'; - c = c - 'a'+ 10; - if ( 10 <= c && c <= 15 ) value = base * value + c; - } - } - return value; -} // wl_atoi - diff --git a/drivers/staging/wlags49_h2/wl_util.h b/drivers/staging/wlags49_h2/wl_util.h index 16cd6c578adb..561e85b5c9b2 100644 --- a/drivers/staging/wlags49_h2/wl_util.h +++ b/drivers/staging/wlags49_h2/wl_util.h @@ -100,6 +100,4 @@ void wl_process_updated_record( struct wl_private *lp ); void wl_process_assoc_status( struct wl_private *lp ); void wl_process_security_status( struct wl_private *lp ); -unsigned int wl_atoi( char *string ); - #endif // __WL_UTIL_H__ -- cgit v1.2.3 From 1832664ae124df0c58dc26985e4963b2c39b6b05 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 12 Jan 2010 15:57:56 +0100 Subject: staging: fix typos "enalbe" -> "enable" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch was generated by git grep -E -l 'enalbe' drivers/staging | xargs -r perl -p -i -e 's/enalbe/enable/g' Signed-off-by: Uwe Kleine-König Signed-off-by: Greg Kroah-Hartman --- drivers/staging/otus/80211core/ccmd.c | 2 +- drivers/staging/rtl8187se/ieee80211/ieee80211_wx.c | 2 +- drivers/staging/rtl8192e/ieee80211/ieee80211_wx.c | 2 +- drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/otus/80211core/ccmd.c b/drivers/staging/otus/80211core/ccmd.c index 8da28eee7fb0..3e3d9b500f65 100644 --- a/drivers/staging/otus/80211core/ccmd.c +++ b/drivers/staging/otus/80211core/ccmd.c @@ -1659,7 +1659,7 @@ void zfiWlanSetPacketTypePromiscuous(zdev_t *dev, u32_t setValue) if (setValue) { /* write register for sniffer mode */ zfHpSetSnifferMode(dev, 1); - zm_msg0_mm(ZM_LV_1, "enalbe sniffer mode"); + zm_msg0_mm(ZM_LV_1, "enable sniffer mode"); } else { zfHpSetSnifferMode(dev, 0); zm_msg0_mm(ZM_LV_0, "disalbe sniffer mode"); diff --git a/drivers/staging/rtl8187se/ieee80211/ieee80211_wx.c b/drivers/staging/rtl8187se/ieee80211/ieee80211_wx.c index acd1077e6396..bd5e77bf7162 100644 --- a/drivers/staging/rtl8187se/ieee80211/ieee80211_wx.c +++ b/drivers/staging/rtl8187se/ieee80211/ieee80211_wx.c @@ -694,7 +694,7 @@ int ieee80211_wx_set_auth(struct ieee80211_device *ieee, #if 1 case IW_AUTH_WPA_ENABLED: ieee->wpa_enabled = (data->value)?1:0; - //printk("enalbe wpa:%d\n", ieee->wpa_enabled); + //printk("enable wpa:%d\n", ieee->wpa_enabled); break; #endif diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211_wx.c b/drivers/staging/rtl8192e/ieee80211/ieee80211_wx.c index efd61bbf06f9..a3302d5e01ab 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211_wx.c +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211_wx.c @@ -933,7 +933,7 @@ int ieee80211_wx_set_auth(struct ieee80211_device *ieee, #if 1 case IW_AUTH_WPA_ENABLED: ieee->wpa_enabled = (data->value)?1:0; - //printk("enalbe wpa:%d\n", ieee->wpa_enabled); + //printk("enable wpa:%d\n", ieee->wpa_enabled); break; #endif diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c index 0f21ccbdeddd..122f8004904b 100644 --- a/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c @@ -731,7 +731,7 @@ int ieee80211_wx_set_auth(struct ieee80211_device *ieee, #if 1 case IW_AUTH_WPA_ENABLED: ieee->wpa_enabled = (data->value)?1:0; - //printk("enalbe wpa:%d\n", ieee->wpa_enabled); + //printk("enable wpa:%d\n", ieee->wpa_enabled); break; #endif -- cgit v1.2.3 From a82fd70197e1e59d2127e5536d6a1d502699528d Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 12 Jan 2010 15:57:57 +0100 Subject: staging: fix typos "selct" -> "select" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch was generated by git grep -E -i -l 's(le|el)ct' drivers/staging | xargs -r perl -p -i -e 's/([Ss])(le|el)ct/$1elect/' Signed-off-by: Uwe Kleine-König Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c index eec71c3efe5e..3692326d474a 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c @@ -1206,7 +1206,7 @@ int i_APCI3XXX_InsnWriteTTLIO(struct comedi_device *dev, if (b_Channel < 8) { /*****************************************************************************/ - /* Read port 0 (first digital output port) and set/reset the selcted channel */ + /* Read port 0 (first digital output port) and set/reset the selected channel */ /*****************************************************************************/ dw_Status = inl(devpriv->iobase + 80); @@ -1228,7 +1228,7 @@ int i_APCI3XXX_InsnWriteTTLIO(struct comedi_device *dev, if ((devpriv->ul_TTLPortConfiguration[0] & 0xFF) == 0xFF) { /*****************************************************************************/ - /* Read port 2 (first digital output port) and set/reset the selcted channel */ + /* Read port 2 (first digital output port) and set/reset the selected channel */ /*****************************************************************************/ dw_Status = inl(devpriv->iobase + 112); -- cgit v1.2.3 From 9d220c6b54f3d0b141846321814ec1c4e4fbdc67 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 12 Jan 2010 15:57:58 +0100 Subject: staging: fix typos "aquire" -> "acquire" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch was generated by git grep -E -i -l '[Aa]quire' drivers/staging | xargs -r perl -p -i -e 's/([Aa])quire/$1cquire/' Signed-off-by: Uwe Kleine-König Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/mpc624.c | 2 +- drivers/staging/comedi/drivers/ni_labpc.c | 2 +- drivers/staging/comedi/drivers/s626.c | 2 +- drivers/staging/comedi/drivers/usbdux.c | 2 +- drivers/staging/comedi/drivers/usbduxfast.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/mpc624.c b/drivers/staging/comedi/drivers/mpc624.c index cb4da2ae8429..12e72c828157 100644 --- a/drivers/staging/comedi/drivers/mpc624.c +++ b/drivers/staging/comedi/drivers/mpc624.c @@ -284,7 +284,7 @@ static int mpc624_ai_rinsn(struct comedi_device *dev, outb(insn->chanspec, dev->iobase + MPC624_GNMUXCH); /* printk("Channel %d: \n", insn->chanspec); */ if (!insn->n) { - printk("MPC624: Warning, no data to aquire\n"); + printk("MPC624: Warning, no data to acquire\n"); return 0; } diff --git a/drivers/staging/comedi/drivers/ni_labpc.c b/drivers/staging/comedi/drivers/ni_labpc.c index dc3f398cb3ed..647c9b72b551 100644 --- a/drivers/staging/comedi/drivers/ni_labpc.c +++ b/drivers/staging/comedi/drivers/ni_labpc.c @@ -1503,7 +1503,7 @@ static void handle_isa_dma(struct comedi_device *dev) devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); } -/* makes sure all data aquired by board is transfered to comedi (used +/* makes sure all data acquired by board is transfered to comedi (used * when aquisition is terminated by stop_src == TRIG_EXT). */ static void labpc_drain_dregs(struct comedi_device *dev) { diff --git a/drivers/staging/comedi/drivers/s626.c b/drivers/staging/comedi/drivers/s626.c index fdd7ab954d8c..a3cc93362ec2 100644 --- a/drivers/staging/comedi/drivers/s626.c +++ b/drivers/staging/comedi/drivers/s626.c @@ -140,7 +140,7 @@ struct s626_private { short allocatedBuf; uint8_t ai_cmd_running; /* ai_cmd is running */ uint8_t ai_continous; /* continous aquisition */ - int ai_sample_count; /* number of samples to aquire */ + int ai_sample_count; /* number of samples to acquire */ unsigned int ai_sample_timer; /* time between samples in units of the timer */ int ai_convert_count; /* conversion counter */ diff --git a/drivers/staging/comedi/drivers/usbdux.c b/drivers/staging/comedi/drivers/usbdux.c index 0c854a6f1ca6..bcf46dab2052 100644 --- a/drivers/staging/comedi/drivers/usbdux.c +++ b/drivers/staging/comedi/drivers/usbdux.c @@ -289,7 +289,7 @@ struct usbduxsub { /* continous aquisition */ short int ai_continous; short int ao_continous; - /* number of samples to aquire */ + /* number of samples to acquire */ int ai_sample_count; int ao_sample_count; /* time between samples in units of the timer */ diff --git a/drivers/staging/comedi/drivers/usbduxfast.c b/drivers/staging/comedi/drivers/usbduxfast.c index 4ff48860fc57..b96cf3b96fd3 100644 --- a/drivers/staging/comedi/drivers/usbduxfast.c +++ b/drivers/staging/comedi/drivers/usbduxfast.c @@ -182,7 +182,7 @@ struct usbduxfastsub_s { context */ short int ai_cmd_running; /* asynchronous command is running */ short int ai_continous; /* continous aquisition */ - long int ai_sample_count; /* number of samples to aquire */ + long int ai_sample_count; /* number of samples to acquire */ uint8_t *dux_commands; /* commands */ int ignore; /* counter which ignores the first buffers */ -- cgit v1.2.3 From d5a2ffd8e8d602293339f69180aff8914c454d83 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 12 Jan 2010 15:57:59 +0100 Subject: staging: fix typos "couter" -> "counter" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch was generated by git grep -l 'couter' drivers/staging | xargs -r perl -p -i -e 's/couter/counter/' Signed-off-by: Uwe Kleine-König Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/adl_pci9118.c | 6 +++--- drivers/staging/comedi/drivers/adv_pci1710.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/adl_pci9118.c b/drivers/staging/comedi/drivers/adl_pci9118.c index 791ea8334e1e..9934a3cf2548 100644 --- a/drivers/staging/comedi/drivers/adl_pci9118.c +++ b/drivers/staging/comedi/drivers/adl_pci9118.c @@ -88,9 +88,9 @@ Configuration options: #define IORANGE_9118 64 /* I hope */ #define PCI9118_CHANLEN 255 /* len of chanlist, some source say 256, but reality looks like 255 :-( */ -#define PCI9118_CNT0 0x00 /* R/W: 8254 couter 0 */ -#define PCI9118_CNT1 0x04 /* R/W: 8254 couter 0 */ -#define PCI9118_CNT2 0x08 /* R/W: 8254 couter 0 */ +#define PCI9118_CNT0 0x00 /* R/W: 8254 counter 0 */ +#define PCI9118_CNT1 0x04 /* R/W: 8254 counter 0 */ +#define PCI9118_CNT2 0x08 /* R/W: 8254 counter 0 */ #define PCI9118_CNTCTRL 0x0c /* W: 8254 counter control */ #define PCI9118_AD_DATA 0x10 /* R: A/D data */ #define PCI9118_DA1 0x10 /* W: D/A registers */ diff --git a/drivers/staging/comedi/drivers/adv_pci1710.c b/drivers/staging/comedi/drivers/adv_pci1710.c index 951e57949f7f..03c73a889048 100644 --- a/drivers/staging/comedi/drivers/adv_pci1710.c +++ b/drivers/staging/comedi/drivers/adv_pci1710.c @@ -84,9 +84,9 @@ Configuration options: #define PCI171x_DAREF 14 /* W: D/A reference control */ #define PCI171x_DI 16 /* R: digi inputs */ #define PCI171x_DO 16 /* R: digi inputs */ -#define PCI171x_CNT0 24 /* R/W: 8254 couter 0 */ -#define PCI171x_CNT1 26 /* R/W: 8254 couter 1 */ -#define PCI171x_CNT2 28 /* R/W: 8254 couter 2 */ +#define PCI171x_CNT0 24 /* R/W: 8254 counter 0 */ +#define PCI171x_CNT1 26 /* R/W: 8254 counter 1 */ +#define PCI171x_CNT2 28 /* R/W: 8254 counter 2 */ #define PCI171x_CNTCTRL 30 /* W: 8254 counter control */ /* upper bits from status register (PCI171x_STATUS) (lower is same woth control reg) */ -- cgit v1.2.3 From 3af805735a2538c38ec16014f19d19030544aaef Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Wed, 6 Jan 2010 16:33:10 +0800 Subject: staging: sm7xx: remove the buggy 2D acceleration support When scrolling the screen on the console with the 2D acceleration support, the whole system may hang. for example, when copying some files from another machine to YeeLoong netbook with the sm7xx video driver via scp and when the screen output is enabled, the system may hang. Before the bug is fixed, remove the 2D acceleration! Signed-off-by: Wu Zhangjin Cc: Teddy Wang Signed-off-by: Greg Kroah-Hartman --- drivers/staging/sm7xx/Kconfig | 7 - drivers/staging/sm7xx/TODO | 1 + drivers/staging/sm7xx/smtc2d.c | 979 ----------------------------------------- drivers/staging/sm7xx/smtc2d.h | 530 ---------------------- drivers/staging/sm7xx/smtcfb.c | 129 +----- 5 files changed, 11 insertions(+), 1635 deletions(-) delete mode 100644 drivers/staging/sm7xx/smtc2d.c delete mode 100644 drivers/staging/sm7xx/smtc2d.h (limited to 'drivers') diff --git a/drivers/staging/sm7xx/Kconfig b/drivers/staging/sm7xx/Kconfig index 204dbfc3c38b..315102c7fed1 100644 --- a/drivers/staging/sm7xx/Kconfig +++ b/drivers/staging/sm7xx/Kconfig @@ -6,10 +6,3 @@ config FB_SM7XX select FB_CFB_IMAGEBLIT help Frame Buffer driver for the Silicon Motion SM7XX serial graphic card. - -config FB_SM7XX_ACCEL - bool "Siliconmotion Acceleration functions (EXPERIMENTAL)" - depends on FB_SM7XX && EXPERIMENTAL - help - This will compile the Trident frame buffer device with - acceleration functions. diff --git a/drivers/staging/sm7xx/TODO b/drivers/staging/sm7xx/TODO index 1f61f5e11cf5..a66d9e406497 100644 --- a/drivers/staging/sm7xx/TODO +++ b/drivers/staging/sm7xx/TODO @@ -1,5 +1,6 @@ TODO: - Dual head support +- 2D acceleration support - use kernel coding style - checkpatch.pl clean - refine the code and remove unused code diff --git a/drivers/staging/sm7xx/smtc2d.c b/drivers/staging/sm7xx/smtc2d.c deleted file mode 100644 index 133b86c6a678..000000000000 --- a/drivers/staging/sm7xx/smtc2d.c +++ /dev/null @@ -1,979 +0,0 @@ -/* - * Silicon Motion SM7XX 2D drawing engine functions. - * - * Copyright (C) 2006 Silicon Motion Technology Corp. - * Author: Boyod boyod.yang@siliconmotion.com.cn - * - * Copyright (C) 2009 Lemote, Inc. - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - * - * Version 0.10.26192.21.01 - * - Add PowerPC support - * - Add 2D support for Lynx - - * Verified on 2.6.19.2 - * Boyod.yang - */ - -unsigned char smtc_de_busy; - -void SMTC_write2Dreg(unsigned long nOffset, unsigned long nData) -{ - writel(nData, smtc_2DBaseAddress + nOffset); -} - -unsigned long SMTC_read2Dreg(unsigned long nOffset) -{ - return readl(smtc_2DBaseAddress + nOffset); -} - -void SMTC_write2Ddataport(unsigned long nOffset, unsigned long nData) -{ - writel(nData, smtc_2Ddataport + nOffset); -} - -/********************************************************************** - * - * deInit - * - * Purpose - * Drawing engine initialization. - * - **********************************************************************/ - -void deInit(unsigned int nModeWidth, unsigned int nModeHeight, - unsigned int bpp) -{ - /* Get current power configuration. */ - unsigned char clock; - clock = smtc_seqr(0x21); - - /* initialize global 'mutex lock' variable */ - smtc_de_busy = 0; - - /* Enable 2D Drawing Engine */ - smtc_seqw(0x21, clock & 0xF8); - - SMTC_write2Dreg(DE_CLIP_TL, - FIELD_VALUE(0, DE_CLIP_TL, TOP, 0) | - FIELD_SET(0, DE_CLIP_TL, STATUS, DISABLE) | - FIELD_SET(0, DE_CLIP_TL, INHIBIT, OUTSIDE) | - FIELD_VALUE(0, DE_CLIP_TL, LEFT, 0)); - - if (bpp >= 24) { - SMTC_write2Dreg(DE_PITCH, - FIELD_VALUE(0, DE_PITCH, DESTINATION, - nModeWidth * 3) | FIELD_VALUE(0, - DE_PITCH, - SOURCE, - nModeWidth - * 3)); - } else { - SMTC_write2Dreg(DE_PITCH, - FIELD_VALUE(0, DE_PITCH, DESTINATION, - nModeWidth) | FIELD_VALUE(0, - DE_PITCH, - SOURCE, - nModeWidth)); - } - - SMTC_write2Dreg(DE_WINDOW_WIDTH, - FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, - nModeWidth) | FIELD_VALUE(0, - DE_WINDOW_WIDTH, - SOURCE, - nModeWidth)); - - switch (bpp) { - case 8: - SMTC_write2Dreg(DE_STRETCH_FORMAT, - FIELD_SET(0, DE_STRETCH_FORMAT, PATTERN_XY, - NORMAL) | FIELD_VALUE(0, - DE_STRETCH_FORMAT, - PATTERN_Y, - 0) | - FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_X, - 0) | FIELD_SET(0, DE_STRETCH_FORMAT, - PIXEL_FORMAT, - 8) | FIELD_SET(0, - DE_STRETCH_FORMAT, - ADDRESSING, - XY) | - FIELD_VALUE(0, DE_STRETCH_FORMAT, - SOURCE_HEIGHT, 3)); - break; - case 24: - SMTC_write2Dreg(DE_STRETCH_FORMAT, - FIELD_SET(0, DE_STRETCH_FORMAT, PATTERN_XY, - NORMAL) | FIELD_VALUE(0, - DE_STRETCH_FORMAT, - PATTERN_Y, - 0) | - FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_X, - 0) | FIELD_SET(0, DE_STRETCH_FORMAT, - PIXEL_FORMAT, - 24) | FIELD_SET(0, - DE_STRETCH_FORMAT, - ADDRESSING, - XY) | - FIELD_VALUE(0, DE_STRETCH_FORMAT, - SOURCE_HEIGHT, 3)); - break; - case 16: - default: - SMTC_write2Dreg(DE_STRETCH_FORMAT, - FIELD_SET(0, DE_STRETCH_FORMAT, PATTERN_XY, - NORMAL) | FIELD_VALUE(0, - DE_STRETCH_FORMAT, - PATTERN_Y, - 0) | - FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_X, - 0) | FIELD_SET(0, DE_STRETCH_FORMAT, - PIXEL_FORMAT, - 16) | FIELD_SET(0, - DE_STRETCH_FORMAT, - ADDRESSING, - XY) | - FIELD_VALUE(0, DE_STRETCH_FORMAT, - SOURCE_HEIGHT, 3)); - break; - } - - SMTC_write2Dreg(DE_MASKS, - FIELD_VALUE(0, DE_MASKS, BYTE_MASK, 0xFFFF) | - FIELD_VALUE(0, DE_MASKS, BIT_MASK, 0xFFFF)); - SMTC_write2Dreg(DE_COLOR_COMPARE_MASK, - FIELD_VALUE(0, DE_COLOR_COMPARE_MASK, MASKS, \ - 0xFFFFFF)); - SMTC_write2Dreg(DE_COLOR_COMPARE, - FIELD_VALUE(0, DE_COLOR_COMPARE, COLOR, 0xFFFFFF)); -} - -void deVerticalLine(unsigned long dst_base, - unsigned long dst_pitch, - unsigned long nX, - unsigned long nY, - unsigned long dst_height, unsigned long nColor) -{ - deWaitForNotBusy(); - - SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, - FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, - dst_base)); - - SMTC_write2Dreg(DE_PITCH, - FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) | - FIELD_VALUE(0, DE_PITCH, SOURCE, dst_pitch)); - - SMTC_write2Dreg(DE_WINDOW_WIDTH, - FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, - dst_pitch) | FIELD_VALUE(0, DE_WINDOW_WIDTH, - SOURCE, - dst_pitch)); - - SMTC_write2Dreg(DE_FOREGROUND, - FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor)); - - SMTC_write2Dreg(DE_DESTINATION, - FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | - FIELD_VALUE(0, DE_DESTINATION, X, nX) | - FIELD_VALUE(0, DE_DESTINATION, Y, nY)); - - SMTC_write2Dreg(DE_DIMENSION, - FIELD_VALUE(0, DE_DIMENSION, X, 1) | - FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height)); - - SMTC_write2Dreg(DE_CONTROL, - FIELD_SET(0, DE_CONTROL, STATUS, START) | - FIELD_SET(0, DE_CONTROL, DIRECTION, LEFT_TO_RIGHT) | - FIELD_SET(0, DE_CONTROL, MAJOR, Y) | - FIELD_SET(0, DE_CONTROL, STEP_X, NEGATIVE) | - FIELD_SET(0, DE_CONTROL, STEP_Y, POSITIVE) | - FIELD_SET(0, DE_CONTROL, LAST_PIXEL, OFF) | - FIELD_SET(0, DE_CONTROL, COMMAND, SHORT_STROKE) | - FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) | - FIELD_VALUE(0, DE_CONTROL, ROP, 0x0C)); - - smtc_de_busy = 1; -} - -void deHorizontalLine(unsigned long dst_base, - unsigned long dst_pitch, - unsigned long nX, - unsigned long nY, - unsigned long dst_width, unsigned long nColor) -{ - deWaitForNotBusy(); - - SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, - FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, - dst_base)); - - SMTC_write2Dreg(DE_PITCH, - FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) | - FIELD_VALUE(0, DE_PITCH, SOURCE, dst_pitch)); - - SMTC_write2Dreg(DE_WINDOW_WIDTH, - FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, - dst_pitch) | FIELD_VALUE(0, DE_WINDOW_WIDTH, - SOURCE, - dst_pitch)); - SMTC_write2Dreg(DE_FOREGROUND, - FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor)); - SMTC_write2Dreg(DE_DESTINATION, - FIELD_SET(0, DE_DESTINATION, WRAP, - DISABLE) | FIELD_VALUE(0, DE_DESTINATION, X, - nX) | FIELD_VALUE(0, - DE_DESTINATION, - Y, - nY)); - SMTC_write2Dreg(DE_DIMENSION, - FIELD_VALUE(0, DE_DIMENSION, X, - dst_width) | FIELD_VALUE(0, DE_DIMENSION, - Y_ET, 1)); - SMTC_write2Dreg(DE_CONTROL, - FIELD_SET(0, DE_CONTROL, STATUS, START) | FIELD_SET(0, - DE_CONTROL, - DIRECTION, - RIGHT_TO_LEFT) - | FIELD_SET(0, DE_CONTROL, MAJOR, X) | FIELD_SET(0, - DE_CONTROL, - STEP_X, - POSITIVE) - | FIELD_SET(0, DE_CONTROL, STEP_Y, - NEGATIVE) | FIELD_SET(0, DE_CONTROL, - LAST_PIXEL, - OFF) | FIELD_SET(0, - DE_CONTROL, - COMMAND, - SHORT_STROKE) - | FIELD_SET(0, DE_CONTROL, ROP_SELECT, - ROP2) | FIELD_VALUE(0, DE_CONTROL, ROP, - 0x0C)); - - smtc_de_busy = 1; -} - -void deLine(unsigned long dst_base, - unsigned long dst_pitch, - unsigned long nX1, - unsigned long nY1, - unsigned long nX2, unsigned long nY2, unsigned long nColor) -{ - unsigned long nCommand = - FIELD_SET(0, DE_CONTROL, STATUS, START) | - FIELD_SET(0, DE_CONTROL, DIRECTION, LEFT_TO_RIGHT) | - FIELD_SET(0, DE_CONTROL, MAJOR, X) | - FIELD_SET(0, DE_CONTROL, STEP_X, POSITIVE) | - FIELD_SET(0, DE_CONTROL, STEP_Y, POSITIVE) | - FIELD_SET(0, DE_CONTROL, LAST_PIXEL, OFF) | - FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) | - FIELD_VALUE(0, DE_CONTROL, ROP, 0x0C); - unsigned long DeltaX; - unsigned long DeltaY; - - /* Calculate delta X */ - if (nX1 <= nX2) - DeltaX = nX2 - nX1; - else { - DeltaX = nX1 - nX2; - nCommand = FIELD_SET(nCommand, DE_CONTROL, STEP_X, NEGATIVE); - } - - /* Calculate delta Y */ - if (nY1 <= nY2) - DeltaY = nY2 - nY1; - else { - DeltaY = nY1 - nY2; - nCommand = FIELD_SET(nCommand, DE_CONTROL, STEP_Y, NEGATIVE); - } - - /* Determine the major axis */ - if (DeltaX < DeltaY) - nCommand = FIELD_SET(nCommand, DE_CONTROL, MAJOR, Y); - - /* Vertical line? */ - if (nX1 == nX2) - deVerticalLine(dst_base, dst_pitch, nX1, nY1, DeltaY, nColor); - - /* Horizontal line? */ - else if (nY1 == nY2) - deHorizontalLine(dst_base, dst_pitch, nX1, nY1, \ - DeltaX, nColor); - - /* Diagonal line? */ - else if (DeltaX == DeltaY) { - deWaitForNotBusy(); - - SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, - FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, - ADDRESS, dst_base)); - - SMTC_write2Dreg(DE_PITCH, - FIELD_VALUE(0, DE_PITCH, DESTINATION, - dst_pitch) | FIELD_VALUE(0, - DE_PITCH, - SOURCE, - dst_pitch)); - - SMTC_write2Dreg(DE_WINDOW_WIDTH, - FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, - dst_pitch) | FIELD_VALUE(0, - DE_WINDOW_WIDTH, - SOURCE, - dst_pitch)); - - SMTC_write2Dreg(DE_FOREGROUND, - FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor)); - - SMTC_write2Dreg(DE_DESTINATION, - FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | - FIELD_VALUE(0, DE_DESTINATION, X, 1) | - FIELD_VALUE(0, DE_DESTINATION, Y, nY1)); - - SMTC_write2Dreg(DE_DIMENSION, - FIELD_VALUE(0, DE_DIMENSION, X, 1) | - FIELD_VALUE(0, DE_DIMENSION, Y_ET, DeltaX)); - - SMTC_write2Dreg(DE_CONTROL, - FIELD_SET(nCommand, DE_CONTROL, COMMAND, - SHORT_STROKE)); - } - - /* Generic line */ - else { - unsigned int k1, k2, et, w; - if (DeltaX < DeltaY) { - k1 = 2 * DeltaX; - et = k1 - DeltaY; - k2 = et - DeltaY; - w = DeltaY + 1; - } else { - k1 = 2 * DeltaY; - et = k1 - DeltaX; - k2 = et - DeltaX; - w = DeltaX + 1; - } - - deWaitForNotBusy(); - - SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, - FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, - ADDRESS, dst_base)); - - SMTC_write2Dreg(DE_PITCH, - FIELD_VALUE(0, DE_PITCH, DESTINATION, - dst_pitch) | FIELD_VALUE(0, - DE_PITCH, - SOURCE, - dst_pitch)); - - SMTC_write2Dreg(DE_WINDOW_WIDTH, - FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, - dst_pitch) | FIELD_VALUE(0, - DE_WINDOW_WIDTH, - SOURCE, - dst_pitch)); - - SMTC_write2Dreg(DE_FOREGROUND, - FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor)); - - SMTC_write2Dreg(DE_SOURCE, - FIELD_SET(0, DE_SOURCE, WRAP, DISABLE) | - FIELD_VALUE(0, DE_SOURCE, X_K1, k1) | - FIELD_VALUE(0, DE_SOURCE, Y_K2, k2)); - - SMTC_write2Dreg(DE_DESTINATION, - FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | - FIELD_VALUE(0, DE_DESTINATION, X, nX1) | - FIELD_VALUE(0, DE_DESTINATION, Y, nY1)); - - SMTC_write2Dreg(DE_DIMENSION, - FIELD_VALUE(0, DE_DIMENSION, X, w) | - FIELD_VALUE(0, DE_DIMENSION, Y_ET, et)); - - SMTC_write2Dreg(DE_CONTROL, - FIELD_SET(nCommand, DE_CONTROL, COMMAND, - LINE_DRAW)); - } - - smtc_de_busy = 1; -} - -void deFillRect(unsigned long dst_base, - unsigned long dst_pitch, - unsigned long dst_X, - unsigned long dst_Y, - unsigned long dst_width, - unsigned long dst_height, unsigned long nColor) -{ - deWaitForNotBusy(); - - SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, - FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, - dst_base)); - - if (dst_pitch) { - SMTC_write2Dreg(DE_PITCH, - FIELD_VALUE(0, DE_PITCH, DESTINATION, - dst_pitch) | FIELD_VALUE(0, - DE_PITCH, - SOURCE, - dst_pitch)); - - SMTC_write2Dreg(DE_WINDOW_WIDTH, - FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, - dst_pitch) | FIELD_VALUE(0, - DE_WINDOW_WIDTH, - SOURCE, - dst_pitch)); - } - - SMTC_write2Dreg(DE_FOREGROUND, - FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor)); - - SMTC_write2Dreg(DE_DESTINATION, - FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | - FIELD_VALUE(0, DE_DESTINATION, X, dst_X) | - FIELD_VALUE(0, DE_DESTINATION, Y, dst_Y)); - - SMTC_write2Dreg(DE_DIMENSION, - FIELD_VALUE(0, DE_DIMENSION, X, dst_width) | - FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height)); - - SMTC_write2Dreg(DE_CONTROL, - FIELD_SET(0, DE_CONTROL, STATUS, START) | - FIELD_SET(0, DE_CONTROL, DIRECTION, LEFT_TO_RIGHT) | - FIELD_SET(0, DE_CONTROL, LAST_PIXEL, OFF) | - FIELD_SET(0, DE_CONTROL, COMMAND, RECTANGLE_FILL) | - FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) | - FIELD_VALUE(0, DE_CONTROL, ROP, 0x0C)); - - smtc_de_busy = 1; -} - -/********************************************************************** - * - * deRotatePattern - * - * Purpose - * Rotate the given pattern if necessary - * - * Parameters - * [in] - * pPattern - Pointer to DE_SURFACE structure containing - * pattern attributes - * patternX - X position (0-7) of pattern origin - * patternY - Y position (0-7) of pattern origin - * - * [out] - * pattern_dstaddr - Pointer to pre-allocated buffer containing - * rotated pattern - * - **********************************************************************/ -void deRotatePattern(unsigned char *pattern_dstaddr, - unsigned long pattern_src_addr, - unsigned long pattern_BPP, - unsigned long pattern_stride, int patternX, int patternY) -{ - unsigned int i; - unsigned long pattern[PATTERN_WIDTH * PATTERN_HEIGHT]; - unsigned int x, y; - unsigned char *pjPatByte; - - if (pattern_dstaddr != NULL) { - deWaitForNotBusy(); - - if (patternX || patternY) { - /* Rotate pattern */ - pjPatByte = (unsigned char *)pattern; - - switch (pattern_BPP) { - case 8: - { - for (y = 0; y < 8; y++) { - unsigned char *pjBuffer = - pattern_dstaddr + - ((patternY + y) & 7) * 8; - for (x = 0; x < 8; x++) { - pjBuffer[(patternX + - x) & 7] = - pjPatByte[x]; - } - pjPatByte += pattern_stride; - } - break; - } - - case 16: - { - for (y = 0; y < 8; y++) { - unsigned short *pjBuffer = - (unsigned short *) - pattern_dstaddr + - ((patternY + y) & 7) * 8; - for (x = 0; x < 8; x++) { - pjBuffer[(patternX + - x) & 7] = - ((unsigned short *) - pjPatByte)[x]; - } - pjPatByte += pattern_stride; - } - break; - } - - case 32: - { - for (y = 0; y < 8; y++) { - unsigned long *pjBuffer = - (unsigned long *) - pattern_dstaddr + - ((patternY + y) & 7) * 8; - for (x = 0; x < 8; x++) { - pjBuffer[(patternX + - x) & 7] = - ((unsigned long *) - pjPatByte)[x]; - } - pjPatByte += pattern_stride; - } - break; - } - } - } else { - /*Don't rotate,just copy pattern into pattern_dstaddr*/ - for (i = 0; i < (pattern_BPP * 2); i++) { - ((unsigned long *)pattern_dstaddr)[i] = - pattern[i]; - } - } - - } -} - -/********************************************************************** - * - * deCopy - * - * Purpose - * Copy a rectangular area of the source surface to a destination surface - * - * Remarks - * Source bitmap must have the same color depth (BPP) as the destination - * bitmap. - * -**********************************************************************/ -void deCopy(unsigned long dst_base, - unsigned long dst_pitch, - unsigned long dst_BPP, - unsigned long dst_X, - unsigned long dst_Y, - unsigned long dst_width, - unsigned long dst_height, - unsigned long src_base, - unsigned long src_pitch, - unsigned long src_X, - unsigned long src_Y, pTransparent pTransp, unsigned char nROP2) -{ - unsigned long nDirection = 0; - unsigned long nTransparent = 0; - /* Direction of ROP2 operation: - * 1 = Left to Right, - * (-1) = Right to Left - */ - unsigned long opSign = 1; - /* xWidth is in pixels */ - unsigned long xWidth = 192 / (dst_BPP / 8); - unsigned long de_ctrl = 0; - - deWaitForNotBusy(); - - SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, - FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, - dst_base)); - - SMTC_write2Dreg(DE_WINDOW_SOURCE_BASE, - FIELD_VALUE(0, DE_WINDOW_SOURCE_BASE, ADDRESS, - src_base)); - - if (dst_pitch && src_pitch) { - SMTC_write2Dreg(DE_PITCH, - FIELD_VALUE(0, DE_PITCH, DESTINATION, - dst_pitch) | FIELD_VALUE(0, - DE_PITCH, - SOURCE, - src_pitch)); - - SMTC_write2Dreg(DE_WINDOW_WIDTH, - FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, - dst_pitch) | FIELD_VALUE(0, - DE_WINDOW_WIDTH, - SOURCE, - src_pitch)); - } - - /* Set transparent bits if necessary */ - if (pTransp != NULL) { - nTransparent = - pTransp->match | pTransp->select | pTransp->control; - - /* Set color compare register */ - SMTC_write2Dreg(DE_COLOR_COMPARE, - FIELD_VALUE(0, DE_COLOR_COMPARE, COLOR, - pTransp->color)); - } - - /* Determine direction of operation */ - if (src_Y < dst_Y) { - /* +----------+ - |S | - | +----------+ - | | | | - | | | | - +---|------+ | - | D | - +----------+ */ - - nDirection = BOTTOM_TO_TOP; - } else if (src_Y > dst_Y) { - /* +----------+ - |D | - | +----------+ - | | | | - | | | | - +---|------+ | - | S | - +----------+ */ - - nDirection = TOP_TO_BOTTOM; - } else { - /* src_Y == dst_Y */ - - if (src_X <= dst_X) { - /* +------+---+------+ - |S | | D| - | | | | - | | | | - | | | | - +------+---+------+ */ - - nDirection = RIGHT_TO_LEFT; - } else { - /* src_X > dst_X */ - - /* +------+---+------+ - |D | | S| - | | | | - | | | | - | | | | - +------+---+------+ */ - - nDirection = LEFT_TO_RIGHT; - } - } - - if ((nDirection == BOTTOM_TO_TOP) || (nDirection == RIGHT_TO_LEFT)) { - src_X += dst_width - 1; - src_Y += dst_height - 1; - dst_X += dst_width - 1; - dst_Y += dst_height - 1; - opSign = (-1); - } - - if (dst_BPP >= 24) { - src_X *= 3; - src_Y *= 3; - dst_X *= 3; - dst_Y *= 3; - dst_width *= 3; - if ((nDirection == BOTTOM_TO_TOP) - || (nDirection == RIGHT_TO_LEFT)) { - src_X += 2; - dst_X += 2; - } - } - - /* Workaround for 192 byte hw bug */ - if ((nROP2 != 0x0C) && ((dst_width * (dst_BPP / 8)) >= 192)) { - /* - * Perform the ROP2 operation in chunks of (xWidth * - * dst_height) - */ - while (1) { - deWaitForNotBusy(); - - SMTC_write2Dreg(DE_SOURCE, - FIELD_SET(0, DE_SOURCE, WRAP, DISABLE) | - FIELD_VALUE(0, DE_SOURCE, X_K1, src_X) | - FIELD_VALUE(0, DE_SOURCE, Y_K2, src_Y)); - - SMTC_write2Dreg(DE_DESTINATION, - FIELD_SET(0, DE_DESTINATION, WRAP, - DISABLE) | FIELD_VALUE(0, - DE_DESTINATION, - X, - dst_X) - | FIELD_VALUE(0, DE_DESTINATION, Y, - dst_Y)); - - SMTC_write2Dreg(DE_DIMENSION, - FIELD_VALUE(0, DE_DIMENSION, X, - xWidth) | FIELD_VALUE(0, - DE_DIMENSION, - Y_ET, - dst_height)); - - de_ctrl = - FIELD_VALUE(0, DE_CONTROL, ROP, - nROP2) | nTransparent | FIELD_SET(0, - DE_CONTROL, - ROP_SELECT, - ROP2) - | FIELD_SET(0, DE_CONTROL, COMMAND, - BITBLT) | ((nDirection == - 1) ? FIELD_SET(0, - DE_CONTROL, - DIRECTION, - RIGHT_TO_LEFT) - : FIELD_SET(0, DE_CONTROL, - DIRECTION, - LEFT_TO_RIGHT)) | - FIELD_SET(0, DE_CONTROL, STATUS, START); - - SMTC_write2Dreg(DE_CONTROL, de_ctrl); - - src_X += (opSign * xWidth); - dst_X += (opSign * xWidth); - dst_width -= xWidth; - - if (dst_width <= 0) { - /* ROP2 operation is complete */ - break; - } - - if (xWidth > dst_width) - xWidth = dst_width; - } - } else { - deWaitForNotBusy(); - SMTC_write2Dreg(DE_SOURCE, - FIELD_SET(0, DE_SOURCE, WRAP, DISABLE) | - FIELD_VALUE(0, DE_SOURCE, X_K1, src_X) | - FIELD_VALUE(0, DE_SOURCE, Y_K2, src_Y)); - - SMTC_write2Dreg(DE_DESTINATION, - FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | - FIELD_VALUE(0, DE_DESTINATION, X, dst_X) | - FIELD_VALUE(0, DE_DESTINATION, Y, dst_Y)); - - SMTC_write2Dreg(DE_DIMENSION, - FIELD_VALUE(0, DE_DIMENSION, X, dst_width) | - FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height)); - - de_ctrl = FIELD_VALUE(0, DE_CONTROL, ROP, nROP2) | - nTransparent | - FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) | - FIELD_SET(0, DE_CONTROL, COMMAND, BITBLT) | - ((nDirection == 1) ? FIELD_SET(0, DE_CONTROL, DIRECTION, - RIGHT_TO_LEFT) - : FIELD_SET(0, DE_CONTROL, DIRECTION, - LEFT_TO_RIGHT)) | FIELD_SET(0, DE_CONTROL, - STATUS, START); - SMTC_write2Dreg(DE_CONTROL, de_ctrl); - } - - smtc_de_busy = 1; -} - -/* - * This function sets the pixel format that will apply to the 2D Engine. - */ -void deSetPixelFormat(unsigned long bpp) -{ - unsigned long de_format; - - de_format = SMTC_read2Dreg(DE_STRETCH_FORMAT); - - switch (bpp) { - case 8: - de_format = - FIELD_SET(de_format, DE_STRETCH_FORMAT, PIXEL_FORMAT, 8); - break; - default: - case 16: - de_format = - FIELD_SET(de_format, DE_STRETCH_FORMAT, PIXEL_FORMAT, 16); - break; - case 32: - de_format = - FIELD_SET(de_format, DE_STRETCH_FORMAT, PIXEL_FORMAT, 32); - break; - } - - SMTC_write2Dreg(DE_STRETCH_FORMAT, de_format); -} - -/* - * System memory to Video memory monochrome expansion. - * - * Source is monochrome image in system memory. This function expands the - * monochrome data to color image in video memory. - */ - -long deSystemMem2VideoMemMonoBlt(const char *pSrcbuf, - long srcDelta, - unsigned long startBit, - unsigned long dBase, - unsigned long dPitch, - unsigned long bpp, - unsigned long dx, unsigned long dy, - unsigned long width, unsigned long height, - unsigned long fColor, - unsigned long bColor, - unsigned long rop2) { - unsigned long bytePerPixel; - unsigned long ulBytesPerScan; - unsigned long ul4BytesPerScan; - unsigned long ulBytesRemain; - unsigned long de_ctrl = 0; - unsigned char ajRemain[4]; - long i, j; - - bytePerPixel = bpp / 8; - - /* Just make sure the start bit is within legal range */ - startBit &= 7; - - ulBytesPerScan = (width + startBit + 7) / 8; - ul4BytesPerScan = ulBytesPerScan & ~3; - ulBytesRemain = ulBytesPerScan & 3; - - if (smtc_de_busy) - deWaitForNotBusy(); - - /* - * 2D Source Base. Use 0 for HOST Blt. - */ - - SMTC_write2Dreg(DE_WINDOW_SOURCE_BASE, 0); - - /* - * 2D Destination Base. - * - * It is an address offset (128 bit aligned) from the beginning of - * frame buffer. - */ - - SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, dBase); - - if (dPitch) { - - /* - * Program pitch (distance between the 1st points of two - * adjacent lines). - * - * Note that input pitch is BYTE value, but the 2D Pitch - * register uses pixel values. Need Byte to pixel convertion. - */ - - SMTC_write2Dreg(DE_PITCH, - FIELD_VALUE(0, DE_PITCH, DESTINATION, - dPitch / - bytePerPixel) | FIELD_VALUE(0, - DE_PITCH, - SOURCE, - dPitch / - bytePerPixel)); - - /* Screen Window width in Pixels. - * - * 2D engine uses this value to calculate the linear address in - * frame buffer for a given point. - */ - - SMTC_write2Dreg(DE_WINDOW_WIDTH, - FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, - (dPitch / - bytePerPixel)) | FIELD_VALUE(0, - DE_WINDOW_WIDTH, - SOURCE, - (dPitch - / - bytePerPixel))); - } - /* Note: For 2D Source in Host Write, only X_K1 field is needed, and - * Y_K2 field is not used. For mono bitmap, use startBit for X_K1. - */ - - SMTC_write2Dreg(DE_SOURCE, - FIELD_SET(0, DE_SOURCE, WRAP, DISABLE) | - FIELD_VALUE(0, DE_SOURCE, X_K1, startBit) | - FIELD_VALUE(0, DE_SOURCE, Y_K2, 0)); - - SMTC_write2Dreg(DE_DESTINATION, - FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | - FIELD_VALUE(0, DE_DESTINATION, X, dx) | - FIELD_VALUE(0, DE_DESTINATION, Y, dy)); - - SMTC_write2Dreg(DE_DIMENSION, - FIELD_VALUE(0, DE_DIMENSION, X, width) | - FIELD_VALUE(0, DE_DIMENSION, Y_ET, height)); - - SMTC_write2Dreg(DE_FOREGROUND, fColor); - SMTC_write2Dreg(DE_BACKGROUND, bColor); - - if (bpp) - deSetPixelFormat(bpp); - /* Set the pixel format of the destination */ - - de_ctrl = FIELD_VALUE(0, DE_CONTROL, ROP, rop2) | - FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) | - FIELD_SET(0, DE_CONTROL, COMMAND, HOST_WRITE) | - FIELD_SET(0, DE_CONTROL, HOST, MONO) | - FIELD_SET(0, DE_CONTROL, STATUS, START); - - SMTC_write2Dreg(DE_CONTROL, de_ctrl | deGetTransparency()); - - /* Write MONO data (line by line) to 2D Engine data port */ - for (i = 0; i < height; i++) { - /* For each line, send the data in chunks of 4 bytes */ - for (j = 0; j < (ul4BytesPerScan / 4); j++) - SMTC_write2Ddataport(0, - *(unsigned long *)(pSrcbuf + - (j * 4))); - - if (ulBytesRemain) { - memcpy(ajRemain, pSrcbuf + ul4BytesPerScan, - ulBytesRemain); - SMTC_write2Ddataport(0, *(unsigned long *)ajRemain); - } - - pSrcbuf += srcDelta; - } - smtc_de_busy = 1; - - return 0; -} - -/* - * This function gets the transparency status from DE_CONTROL register. - * It returns a double word with the transparent fields properly set, - * while other fields are 0. - */ -unsigned long deGetTransparency(void) -{ - unsigned long de_ctrl; - - de_ctrl = SMTC_read2Dreg(DE_CONTROL); - - de_ctrl &= - FIELD_MASK(DE_CONTROL_TRANSPARENCY_MATCH) | - FIELD_MASK(DE_CONTROL_TRANSPARENCY_SELECT) | - FIELD_MASK(DE_CONTROL_TRANSPARENCY); - - return de_ctrl; -} diff --git a/drivers/staging/sm7xx/smtc2d.h b/drivers/staging/sm7xx/smtc2d.h deleted file mode 100644 index 38d0c335322b..000000000000 --- a/drivers/staging/sm7xx/smtc2d.h +++ /dev/null @@ -1,530 +0,0 @@ -/* - * Silicon Motion SM712 2D drawing engine functions. - * - * Copyright (C) 2006 Silicon Motion Technology Corp. - * Author: Ge Wang, gewang@siliconmotion.com - * - * Copyright (C) 2009 Lemote, Inc. - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#ifndef NULL -#define NULL 0 -#endif - -/* Internal macros */ - -#define _F_START(f) (0 ? f) -#define _F_END(f) (1 ? f) -#define _F_SIZE(f) (1 + _F_END(f) - _F_START(f)) -#define _F_MASK(f) (((1ULL << _F_SIZE(f)) - 1) << _F_START(f)) -#define _F_NORMALIZE(v, f) (((v) & _F_MASK(f)) >> _F_START(f)) -#define _F_DENORMALIZE(v, f) (((v) << _F_START(f)) & _F_MASK(f)) - -/* Global macros */ - -#define FIELD_GET(x, reg, field) \ -( \ - _F_NORMALIZE((x), reg ## _ ## field) \ -) - -#define FIELD_SET(x, reg, field, value) \ -( \ - (x & ~_F_MASK(reg ## _ ## field)) \ - | _F_DENORMALIZE(reg ## _ ## field ## _ ## value, reg ## _ ## field) \ -) - -#define FIELD_VALUE(x, reg, field, value) \ -( \ - (x & ~_F_MASK(reg ## _ ## field)) \ - | _F_DENORMALIZE(value, reg ## _ ## field) \ -) - -#define FIELD_CLEAR(reg, field) \ -( \ - ~_F_MASK(reg ## _ ## field) \ -) - -/* Field Macros */ - -#define FIELD_START(field) (0 ? field) -#define FIELD_END(field) (1 ? field) -#define FIELD_SIZE(field) \ - (1 + FIELD_END(field) - FIELD_START(field)) - -#define FIELD_MASK(field) \ - (((1 << (FIELD_SIZE(field)-1)) \ - | ((1 << (FIELD_SIZE(field)-1)) - 1)) \ - << FIELD_START(field)) - -#define FIELD_NORMALIZE(reg, field) \ - (((reg) & FIELD_MASK(field)) >> FIELD_START(field)) - -#define FIELD_DENORMALIZE(field, value) \ - (((value) << FIELD_START(field)) & FIELD_MASK(field)) - -#define FIELD_INIT(reg, field, value) \ - FIELD_DENORMALIZE(reg ## _ ## field, \ - reg ## _ ## field ## _ ## value) - -#define FIELD_INIT_VAL(reg, field, value) \ - (FIELD_DENORMALIZE(reg ## _ ## field, value)) - -#define FIELD_VAL_SET(x, r, f, v) ({ \ - x = (x & ~FIELD_MASK(r ## _ ## f)) \ - | FIELD_DENORMALIZE(r ## _ ## f, r ## _ ## f ## _ ## v) \ -}) - -#define RGB(r, g, b) ((unsigned long)(((r) << 16) | ((g) << 8) | (b))) - -/* Transparent info definition */ -typedef struct { - unsigned long match; /* Matching pixel is OPAQUE/TRANSPARENT */ - unsigned long select; /* Transparency controlled by SRC/DST */ - unsigned long control; /* ENABLE/DISABLE transparency */ - unsigned long color; /* Transparent color */ -} Transparent, *pTransparent; - -#define PIXEL_DEPTH_1_BP 0 /* 1 bit per pixel */ -#define PIXEL_DEPTH_8_BPP 1 /* 8 bits per pixel */ -#define PIXEL_DEPTH_16_BPP 2 /* 16 bits per pixel */ -#define PIXEL_DEPTH_32_BPP 3 /* 32 bits per pixel */ -#define PIXEL_DEPTH_YUV422 8 /* 16 bits per pixel YUV422 */ -#define PIXEL_DEPTH_YUV420 9 /* 16 bits per pixel YUV420 */ - -#define PATTERN_WIDTH 8 -#define PATTERN_HEIGHT 8 - -#define TOP_TO_BOTTOM 0 -#define BOTTOM_TO_TOP 1 -#define RIGHT_TO_LEFT BOTTOM_TO_TOP -#define LEFT_TO_RIGHT TOP_TO_BOTTOM - -/* Constants used in Transparent structure */ -#define MATCH_OPAQUE 0x00000000 -#define MATCH_TRANSPARENT 0x00000400 -#define SOURCE 0x00000000 -#define DESTINATION 0x00000200 - -/* 2D registers. */ - -#define DE_SOURCE 0x000000 -#define DE_SOURCE_WRAP 31 : 31 -#define DE_SOURCE_WRAP_DISABLE 0 -#define DE_SOURCE_WRAP_ENABLE 1 -#define DE_SOURCE_X_K1 29 : 16 -#define DE_SOURCE_Y_K2 15 : 0 - -#define DE_DESTINATION 0x000004 -#define DE_DESTINATION_WRAP 31 : 31 -#define DE_DESTINATION_WRAP_DISABLE 0 -#define DE_DESTINATION_WRAP_ENABLE 1 -#define DE_DESTINATION_X 28 : 16 -#define DE_DESTINATION_Y 15 : 0 - -#define DE_DIMENSION 0x000008 -#define DE_DIMENSION_X 28 : 16 -#define DE_DIMENSION_Y_ET 15 : 0 - -#define DE_CONTROL 0x00000C -#define DE_CONTROL_STATUS 31 : 31 -#define DE_CONTROL_STATUS_STOP 0 -#define DE_CONTROL_STATUS_START 1 -#define DE_CONTROL_PATTERN 30 : 30 -#define DE_CONTROL_PATTERN_MONO 0 -#define DE_CONTROL_PATTERN_COLOR 1 -#define DE_CONTROL_UPDATE_DESTINATION_X 29 : 29 -#define DE_CONTROL_UPDATE_DESTINATION_X_DISABLE 0 -#define DE_CONTROL_UPDATE_DESTINATION_X_ENABLE 1 -#define DE_CONTROL_QUICK_START 28 : 28 -#define DE_CONTROL_QUICK_START_DISABLE 0 -#define DE_CONTROL_QUICK_START_ENABLE 1 -#define DE_CONTROL_DIRECTION 27 : 27 -#define DE_CONTROL_DIRECTION_LEFT_TO_RIGHT 0 -#define DE_CONTROL_DIRECTION_RIGHT_TO_LEFT 1 -#define DE_CONTROL_MAJOR 26 : 26 -#define DE_CONTROL_MAJOR_X 0 -#define DE_CONTROL_MAJOR_Y 1 -#define DE_CONTROL_STEP_X 25 : 25 -#define DE_CONTROL_STEP_X_POSITIVE 1 -#define DE_CONTROL_STEP_X_NEGATIVE 0 -#define DE_CONTROL_STEP_Y 24 : 24 -#define DE_CONTROL_STEP_Y_POSITIVE 1 -#define DE_CONTROL_STEP_Y_NEGATIVE 0 -#define DE_CONTROL_STRETCH 23 : 23 -#define DE_CONTROL_STRETCH_DISABLE 0 -#define DE_CONTROL_STRETCH_ENABLE 1 -#define DE_CONTROL_HOST 22 : 22 -#define DE_CONTROL_HOST_COLOR 0 -#define DE_CONTROL_HOST_MONO 1 -#define DE_CONTROL_LAST_PIXEL 21 : 21 -#define DE_CONTROL_LAST_PIXEL_OFF 0 -#define DE_CONTROL_LAST_PIXEL_ON 1 -#define DE_CONTROL_COMMAND 20 : 16 -#define DE_CONTROL_COMMAND_BITBLT 0 -#define DE_CONTROL_COMMAND_RECTANGLE_FILL 1 -#define DE_CONTROL_COMMAND_DE_TILE 2 -#define DE_CONTROL_COMMAND_TRAPEZOID_FILL 3 -#define DE_CONTROL_COMMAND_ALPHA_BLEND 4 -#define DE_CONTROL_COMMAND_RLE_STRIP 5 -#define DE_CONTROL_COMMAND_SHORT_STROKE 6 -#define DE_CONTROL_COMMAND_LINE_DRAW 7 -#define DE_CONTROL_COMMAND_HOST_WRITE 8 -#define DE_CONTROL_COMMAND_HOST_READ 9 -#define DE_CONTROL_COMMAND_HOST_WRITE_BOTTOM_UP 10 -#define DE_CONTROL_COMMAND_ROTATE 11 -#define DE_CONTROL_COMMAND_FONT 12 -#define DE_CONTROL_COMMAND_TEXTURE_LOAD 15 -#define DE_CONTROL_ROP_SELECT 15 : 15 -#define DE_CONTROL_ROP_SELECT_ROP3 0 -#define DE_CONTROL_ROP_SELECT_ROP2 1 -#define DE_CONTROL_ROP2_SOURCE 14 : 14 -#define DE_CONTROL_ROP2_SOURCE_BITMAP 0 -#define DE_CONTROL_ROP2_SOURCE_PATTERN 1 -#define DE_CONTROL_MONO_DATA 13 : 12 -#define DE_CONTROL_MONO_DATA_NOT_PACKED 0 -#define DE_CONTROL_MONO_DATA_8_PACKED 1 -#define DE_CONTROL_MONO_DATA_16_PACKED 2 -#define DE_CONTROL_MONO_DATA_32_PACKED 3 -#define DE_CONTROL_REPEAT_ROTATE 11 : 11 -#define DE_CONTROL_REPEAT_ROTATE_DISABLE 0 -#define DE_CONTROL_REPEAT_ROTATE_ENABLE 1 -#define DE_CONTROL_TRANSPARENCY_MATCH 10 : 10 -#define DE_CONTROL_TRANSPARENCY_MATCH_OPAQUE 0 -#define DE_CONTROL_TRANSPARENCY_MATCH_TRANSPARENT 1 -#define DE_CONTROL_TRANSPARENCY_SELECT 9 : 9 -#define DE_CONTROL_TRANSPARENCY_SELECT_SOURCE 0 -#define DE_CONTROL_TRANSPARENCY_SELECT_DESTINATION 1 -#define DE_CONTROL_TRANSPARENCY 8 : 8 -#define DE_CONTROL_TRANSPARENCY_DISABLE 0 -#define DE_CONTROL_TRANSPARENCY_ENABLE 1 -#define DE_CONTROL_ROP 7 : 0 - -/* Pseudo fields. */ - -#define DE_CONTROL_SHORT_STROKE_DIR 27 : 24 -#define DE_CONTROL_SHORT_STROKE_DIR_225 0 -#define DE_CONTROL_SHORT_STROKE_DIR_135 1 -#define DE_CONTROL_SHORT_STROKE_DIR_315 2 -#define DE_CONTROL_SHORT_STROKE_DIR_45 3 -#define DE_CONTROL_SHORT_STROKE_DIR_270 4 -#define DE_CONTROL_SHORT_STROKE_DIR_90 5 -#define DE_CONTROL_SHORT_STROKE_DIR_180 8 -#define DE_CONTROL_SHORT_STROKE_DIR_0 10 -#define DE_CONTROL_ROTATION 25 : 24 -#define DE_CONTROL_ROTATION_0 0 -#define DE_CONTROL_ROTATION_270 1 -#define DE_CONTROL_ROTATION_90 2 -#define DE_CONTROL_ROTATION_180 3 - -#define DE_PITCH 0x000010 -#define DE_PITCH_DESTINATION 28 : 16 -#define DE_PITCH_SOURCE 12 : 0 - -#define DE_FOREGROUND 0x000014 -#define DE_FOREGROUND_COLOR 31 : 0 - -#define DE_BACKGROUND 0x000018 -#define DE_BACKGROUND_COLOR 31 : 0 - -#define DE_STRETCH_FORMAT 0x00001C -#define DE_STRETCH_FORMAT_PATTERN_XY 30 : 30 -#define DE_STRETCH_FORMAT_PATTERN_XY_NORMAL 0 -#define DE_STRETCH_FORMAT_PATTERN_XY_OVERWRITE 1 -#define DE_STRETCH_FORMAT_PATTERN_Y 29 : 27 -#define DE_STRETCH_FORMAT_PATTERN_X 25 : 23 -#define DE_STRETCH_FORMAT_PIXEL_FORMAT 21 : 20 -#define DE_STRETCH_FORMAT_PIXEL_FORMAT_8 0 -#define DE_STRETCH_FORMAT_PIXEL_FORMAT_16 1 -#define DE_STRETCH_FORMAT_PIXEL_FORMAT_24 3 -#define DE_STRETCH_FORMAT_PIXEL_FORMAT_32 2 -#define DE_STRETCH_FORMAT_ADDRESSING 19 : 16 -#define DE_STRETCH_FORMAT_ADDRESSING_XY 0 -#define DE_STRETCH_FORMAT_ADDRESSING_LINEAR 15 -#define DE_STRETCH_FORMAT_SOURCE_HEIGHT 11 : 0 - -#define DE_COLOR_COMPARE 0x000020 -#define DE_COLOR_COMPARE_COLOR 23 : 0 - -#define DE_COLOR_COMPARE_MASK 0x000024 -#define DE_COLOR_COMPARE_MASK_MASKS 23 : 0 - -#define DE_MASKS 0x000028 -#define DE_MASKS_BYTE_MASK 31 : 16 -#define DE_MASKS_BIT_MASK 15 : 0 - -#define DE_CLIP_TL 0x00002C -#define DE_CLIP_TL_TOP 31 : 16 -#define DE_CLIP_TL_STATUS 13 : 13 -#define DE_CLIP_TL_STATUS_DISABLE 0 -#define DE_CLIP_TL_STATUS_ENABLE 1 -#define DE_CLIP_TL_INHIBIT 12 : 12 -#define DE_CLIP_TL_INHIBIT_OUTSIDE 0 -#define DE_CLIP_TL_INHIBIT_INSIDE 1 -#define DE_CLIP_TL_LEFT 11 : 0 - -#define DE_CLIP_BR 0x000030 -#define DE_CLIP_BR_BOTTOM 31 : 16 -#define DE_CLIP_BR_RIGHT 12 : 0 - -#define DE_MONO_PATTERN_LOW 0x000034 -#define DE_MONO_PATTERN_LOW_PATTERN 31 : 0 - -#define DE_MONO_PATTERN_HIGH 0x000038 -#define DE_MONO_PATTERN_HIGH_PATTERN 31 : 0 - -#define DE_WINDOW_WIDTH 0x00003C -#define DE_WINDOW_WIDTH_DESTINATION 28 : 16 -#define DE_WINDOW_WIDTH_SOURCE 12 : 0 - -#define DE_WINDOW_SOURCE_BASE 0x000040 -#define DE_WINDOW_SOURCE_BASE_EXT 27 : 27 -#define DE_WINDOW_SOURCE_BASE_EXT_LOCAL 0 -#define DE_WINDOW_SOURCE_BASE_EXT_EXTERNAL 1 -#define DE_WINDOW_SOURCE_BASE_CS 26 : 26 -#define DE_WINDOW_SOURCE_BASE_CS_0 0 -#define DE_WINDOW_SOURCE_BASE_CS_1 1 -#define DE_WINDOW_SOURCE_BASE_ADDRESS 25 : 0 - -#define DE_WINDOW_DESTINATION_BASE 0x000044 -#define DE_WINDOW_DESTINATION_BASE_EXT 27 : 27 -#define DE_WINDOW_DESTINATION_BASE_EXT_LOCAL 0 -#define DE_WINDOW_DESTINATION_BASE_EXT_EXTERNAL 1 -#define DE_WINDOW_DESTINATION_BASE_CS 26 : 26 -#define DE_WINDOW_DESTINATION_BASE_CS_0 0 -#define DE_WINDOW_DESTINATION_BASE_CS_1 1 -#define DE_WINDOW_DESTINATION_BASE_ADDRESS 25 : 0 - -#define DE_ALPHA 0x000048 -#define DE_ALPHA_VALUE 7 : 0 - -#define DE_WRAP 0x00004C -#define DE_WRAP_X 31 : 16 -#define DE_WRAP_Y 15 : 0 - -#define DE_STATUS 0x000050 -#define DE_STATUS_CSC 1 : 1 -#define DE_STATUS_CSC_CLEAR 0 -#define DE_STATUS_CSC_NOT_ACTIVE 0 -#define DE_STATUS_CSC_ACTIVE 1 -#define DE_STATUS_2D 0 : 0 -#define DE_STATUS_2D_CLEAR 0 -#define DE_STATUS_2D_NOT_ACTIVE 0 -#define DE_STATUS_2D_ACTIVE 1 - -/* Color Space Conversion registers. */ - -#define CSC_Y_SOURCE_BASE 0x0000C8 -#define CSC_Y_SOURCE_BASE_EXT 27 : 27 -#define CSC_Y_SOURCE_BASE_EXT_LOCAL 0 -#define CSC_Y_SOURCE_BASE_EXT_EXTERNAL 1 -#define CSC_Y_SOURCE_BASE_CS 26 : 26 -#define CSC_Y_SOURCE_BASE_CS_0 0 -#define CSC_Y_SOURCE_BASE_CS_1 1 -#define CSC_Y_SOURCE_BASE_ADDRESS 25 : 0 - -#define CSC_CONSTANTS 0x0000CC -#define CSC_CONSTANTS_Y 31 : 24 -#define CSC_CONSTANTS_R 23 : 16 -#define CSC_CONSTANTS_G 15 : 8 -#define CSC_CONSTANTS_B 7 : 0 - -#define CSC_Y_SOURCE_X 0x0000D0 -#define CSC_Y_SOURCE_X_INTEGER 26 : 16 -#define CSC_Y_SOURCE_X_FRACTION 15 : 3 - -#define CSC_Y_SOURCE_Y 0x0000D4 -#define CSC_Y_SOURCE_Y_INTEGER 27 : 16 -#define CSC_Y_SOURCE_Y_FRACTION 15 : 3 - -#define CSC_U_SOURCE_BASE 0x0000D8 -#define CSC_U_SOURCE_BASE_EXT 27 : 27 -#define CSC_U_SOURCE_BASE_EXT_LOCAL 0 -#define CSC_U_SOURCE_BASE_EXT_EXTERNAL 1 -#define CSC_U_SOURCE_BASE_CS 26 : 26 -#define CSC_U_SOURCE_BASE_CS_0 0 -#define CSC_U_SOURCE_BASE_CS_1 1 -#define CSC_U_SOURCE_BASE_ADDRESS 25 : 0 - -#define CSC_V_SOURCE_BASE 0x0000DC -#define CSC_V_SOURCE_BASE_EXT 27 : 27 -#define CSC_V_SOURCE_BASE_EXT_LOCAL 0 -#define CSC_V_SOURCE_BASE_EXT_EXTERNAL 1 -#define CSC_V_SOURCE_BASE_CS 26 : 26 -#define CSC_V_SOURCE_BASE_CS_0 0 -#define CSC_V_SOURCE_BASE_CS_1 1 -#define CSC_V_SOURCE_BASE_ADDRESS 25 : 0 - -#define CSC_SOURCE_DIMENSION 0x0000E0 -#define CSC_SOURCE_DIMENSION_X 31 : 16 -#define CSC_SOURCE_DIMENSION_Y 15 : 0 - -#define CSC_SOURCE_PITCH 0x0000E4 -#define CSC_SOURCE_PITCH_Y 31 : 16 -#define CSC_SOURCE_PITCH_UV 15 : 0 - -#define CSC_DESTINATION 0x0000E8 -#define CSC_DESTINATION_WRAP 31 : 31 -#define CSC_DESTINATION_WRAP_DISABLE 0 -#define CSC_DESTINATION_WRAP_ENABLE 1 -#define CSC_DESTINATION_X 27 : 16 -#define CSC_DESTINATION_Y 11 : 0 - -#define CSC_DESTINATION_DIMENSION 0x0000EC -#define CSC_DESTINATION_DIMENSION_X 31 : 16 -#define CSC_DESTINATION_DIMENSION_Y 15 : 0 - -#define CSC_DESTINATION_PITCH 0x0000F0 -#define CSC_DESTINATION_PITCH_X 31 : 16 -#define CSC_DESTINATION_PITCH_Y 15 : 0 - -#define CSC_SCALE_FACTOR 0x0000F4 -#define CSC_SCALE_FACTOR_HORIZONTAL 31 : 16 -#define CSC_SCALE_FACTOR_VERTICAL 15 : 0 - -#define CSC_DESTINATION_BASE 0x0000F8 -#define CSC_DESTINATION_BASE_EXT 27 : 27 -#define CSC_DESTINATION_BASE_EXT_LOCAL 0 -#define CSC_DESTINATION_BASE_EXT_EXTERNAL 1 -#define CSC_DESTINATION_BASE_CS 26 : 26 -#define CSC_DESTINATION_BASE_CS_0 0 -#define CSC_DESTINATION_BASE_CS_1 1 -#define CSC_DESTINATION_BASE_ADDRESS 25 : 0 - -#define CSC_CONTROL 0x0000FC -#define CSC_CONTROL_STATUS 31 : 31 -#define CSC_CONTROL_STATUS_STOP 0 -#define CSC_CONTROL_STATUS_START 1 -#define CSC_CONTROL_SOURCE_FORMAT 30 : 28 -#define CSC_CONTROL_SOURCE_FORMAT_YUV422 0 -#define CSC_CONTROL_SOURCE_FORMAT_YUV420I 1 -#define CSC_CONTROL_SOURCE_FORMAT_YUV420 2 -#define CSC_CONTROL_SOURCE_FORMAT_YVU9 3 -#define CSC_CONTROL_SOURCE_FORMAT_IYU1 4 -#define CSC_CONTROL_SOURCE_FORMAT_IYU2 5 -#define CSC_CONTROL_SOURCE_FORMAT_RGB565 6 -#define CSC_CONTROL_SOURCE_FORMAT_RGB8888 7 -#define CSC_CONTROL_DESTINATION_FORMAT 27 : 26 -#define CSC_CONTROL_DESTINATION_FORMAT_RGB565 0 -#define CSC_CONTROL_DESTINATION_FORMAT_RGB8888 1 -#define CSC_CONTROL_HORIZONTAL_FILTER 25 : 25 -#define CSC_CONTROL_HORIZONTAL_FILTER_DISABLE 0 -#define CSC_CONTROL_HORIZONTAL_FILTER_ENABLE 1 -#define CSC_CONTROL_VERTICAL_FILTER 24 : 24 -#define CSC_CONTROL_VERTICAL_FILTER_DISABLE 0 -#define CSC_CONTROL_VERTICAL_FILTER_ENABLE 1 -#define CSC_CONTROL_BYTE_ORDER 23 : 23 -#define CSC_CONTROL_BYTE_ORDER_YUYV 0 -#define CSC_CONTROL_BYTE_ORDER_UYVY 1 - -#define DE_DATA_PORT_501 0x110000 -#define DE_DATA_PORT_712 0x400000 -#define DE_DATA_PORT_722 0x6000 - -/* point to virtual Memory Map IO starting address */ -extern char *smtc_RegBaseAddress; -/* point to virtual video memory starting address */ -extern char *smtc_VRAMBaseAddress; -extern unsigned char smtc_de_busy; - -extern unsigned long memRead32(unsigned long nOffset); -extern void memWrite32(unsigned long nOffset, unsigned long nData); -extern unsigned long SMTC_read2Dreg(unsigned long nOffset); - -/* 2D functions */ -extern void deInit(unsigned int nModeWidth, unsigned int nModeHeight, - unsigned int bpp); - -extern void deWaitForNotBusy(void); - -extern void deVerticalLine(unsigned long dst_base, - unsigned long dst_pitch, - unsigned long nX, - unsigned long nY, - unsigned long dst_height, - unsigned long nColor); - -extern void deHorizontalLine(unsigned long dst_base, - unsigned long dst_pitch, - unsigned long nX, - unsigned long nY, - unsigned long dst_width, - unsigned long nColor); - -extern void deLine(unsigned long dst_base, - unsigned long dst_pitch, - unsigned long nX1, - unsigned long nY1, - unsigned long nX2, - unsigned long nY2, - unsigned long nColor); - -extern void deFillRect(unsigned long dst_base, - unsigned long dst_pitch, - unsigned long dst_X, - unsigned long dst_Y, - unsigned long dst_width, - unsigned long dst_height, - unsigned long nColor); - -extern void deRotatePattern(unsigned char *pattern_dstaddr, - unsigned long pattern_src_addr, - unsigned long pattern_BPP, - unsigned long pattern_stride, - int patternX, - int patternY); - -extern void deCopy(unsigned long dst_base, - unsigned long dst_pitch, - unsigned long dst_BPP, - unsigned long dst_X, - unsigned long dst_Y, - unsigned long dst_width, - unsigned long dst_height, - unsigned long src_base, - unsigned long src_pitch, - unsigned long src_X, - unsigned long src_Y, - pTransparent pTransp, - unsigned char nROP2); - -/* - * System memory to Video memory monochrome expansion. - * - * Source is monochrome image in system memory. This function expands the - * monochrome data to color image in video memory. - * - * @pSrcbuf: pointer to start of source buffer in system memory - * @srcDelta: Pitch value (in bytes) of the source buffer, +ive means top - * down and -ive mean button up - * @startBit: Mono data can start at any bit in a byte, this value should - * be 0 to 7 - * @dBase: Address of destination : offset in frame buffer - * @dPitch: Pitch value of destination surface in BYTE - * @bpp: Color depth of destination surface - * @dx, dy: Starting coordinate of destination surface - * @width, height: width and height of rectange in pixel value - * @fColor,bColor: Foreground, Background color (corresponding to a 1, 0 in - * the monochrome data) - * @rop2: ROP value - */ - -extern long deSystemMem2VideoMemMonoBlt( - const char *pSrcbuf, - long srcDelta, - unsigned long startBit, - unsigned long dBase, - unsigned long dPitch, - unsigned long bpp, - unsigned long dx, unsigned long dy, - unsigned long width, unsigned long height, - unsigned long fColor, - unsigned long bColor, - unsigned long rop2); - -extern unsigned long deGetTransparency(void); -extern void deSetPixelFormat(unsigned long bpp); diff --git a/drivers/staging/sm7xx/smtcfb.c b/drivers/staging/sm7xx/smtcfb.c index 080b51a6e553..863df038f0d6 100644 --- a/drivers/staging/sm7xx/smtcfb.c +++ b/drivers/staging/sm7xx/smtcfb.c @@ -45,7 +45,6 @@ struct screen_info smtc_screen_info; #include "smtcfb.h" -#include "smtc2d.h" #ifdef DEBUG #define smdbg(format, arg...) printk(KERN_DEBUG format , ## arg) @@ -120,10 +119,6 @@ static struct vesa_mode_table vesa_mode[] = { char __iomem *smtc_RegBaseAddress; /* Memory Map IO starting address */ char __iomem *smtc_VRAMBaseAddress; /* video memory starting address */ -char *smtc_2DBaseAddress; /* 2D engine starting address */ -char *smtc_2Ddataport; /* 2D data port offset */ -short smtc_2Dacceleration; - static u32 colreg[17]; static struct par_info hw; /* hardware information */ @@ -135,16 +130,6 @@ u16 smtc_ChipIDs[] = { #define numSMTCchipIDs (sizeof(smtc_ChipIDs) / sizeof(u16)) -void deWaitForNotBusy(void) -{ - unsigned long i = 0x1000000; - while (i--) { - if ((smtc_seqr(0x16) & 0x18) == 0x10) - break; - } - smtc_de_busy = 0; -} - static void sm712_set_timing(struct smtcfb_info *sfb, struct par_info *ppar_info) { @@ -324,7 +309,7 @@ static inline unsigned int chan_to_field(unsigned int chan, return chan << bf->offset; } -static int smtcfb_blank(int blank_mode, struct fb_info *info) +static int cfb_blank(int blank_mode, struct fb_info *info) { /* clear DPMS setting */ switch (blank_mode) { @@ -622,93 +607,13 @@ smtcfb_write(struct fb_info *info, const char __user *buf, size_t count, } #endif /* ! __BIG_ENDIAN */ -#include "smtc2d.c" - -void smtcfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) -{ - struct par_info *p = (struct par_info *)info->par; - - if (smtc_2Dacceleration) { - if (!area->width || !area->height) - return; - - deCopy(p->BaseAddressInVRAM, 0, info->var.bits_per_pixel, - area->dx, area->dy, area->width, area->height, - p->BaseAddressInVRAM, 0, area->sx, area->sy, 0, 0xC); - - } else - cfb_copyarea(info, area); -} - -void smtcfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) -{ - struct par_info *p = (struct par_info *)info->par; - - if (smtc_2Dacceleration) { - if (!rect->width || !rect->height) - return; - if (info->var.bits_per_pixel >= 24) - deFillRect(p->BaseAddressInVRAM, 0, rect->dx * 3, - rect->dy * 3, rect->width * 3, rect->height, - rect->color); - else - deFillRect(p->BaseAddressInVRAM, 0, rect->dx, rect->dy, - rect->width, rect->height, rect->color); - } else - cfb_fillrect(info, rect); -} - -void smtcfb_imageblit(struct fb_info *info, const struct fb_image *image) -{ - struct par_info *p = (struct par_info *)info->par; - u32 bg_col = 0, fg_col = 0; - - if ((smtc_2Dacceleration) && (image->depth == 1)) { - if (smtc_de_busy) - deWaitForNotBusy(); - - switch (info->var.bits_per_pixel) { - case 8: - bg_col = image->bg_color; - fg_col = image->fg_color; - break; - case 16: - bg_col = - ((u32 *) (info->pseudo_palette))[image->bg_color]; - fg_col = - ((u32 *) (info->pseudo_palette))[image->fg_color]; - break; - case 32: - bg_col = - ((u32 *) (info->pseudo_palette))[image->bg_color]; - fg_col = - ((u32 *) (info->pseudo_palette))[image->fg_color]; - break; - } - - deSystemMem2VideoMemMonoBlt( - image->data, - image->width / 8, - 0, - p->BaseAddressInVRAM, - 0, - 0, - image->dx, image->dy, - image->width, image->height, - fg_col, bg_col, - 0x0C); - - } else - cfb_imageblit(info, image); -} - static struct fb_ops smtcfb_ops = { .owner = THIS_MODULE, .fb_setcolreg = smtc_setcolreg, - .fb_blank = smtcfb_blank, - .fb_fillrect = smtcfb_fillrect, - .fb_imageblit = smtcfb_imageblit, - .fb_copyarea = smtcfb_copyarea, + .fb_blank = cfb_blank, + .fb_fillrect = cfb_fillrect, + .fb_imageblit = cfb_imageblit, + .fb_copyarea = cfb_copyarea, #ifdef __BIG_ENDIAN .fb_read = smtcfb_read, .fb_write = smtcfb_write, @@ -772,12 +677,6 @@ void smtcfb_setmode(struct smtcfb_info *sfb) hw.height = sfb->fb.var.yres; hw.hz = 60; smtc_set_timing(sfb, &hw); - if (smtc_2Dacceleration) { - printk("2D acceleration enabled!\n"); - /* Init smtc drawing engine */ - deInit(sfb->fb.var.xres, sfb->fb.var.yres, - sfb->fb.var.bits_per_pixel); - } } /* @@ -1004,9 +903,7 @@ static int __init smtcfb_pci_probe(struct pci_dev *pdev, #endif hw.m_pMMIO = (smtc_RegBaseAddress = smtc_VRAMBaseAddress + 0x00700000); - smtc_2DBaseAddress = (hw.m_pDPR = - smtc_VRAMBaseAddress + 0x00408000); - smtc_2Ddataport = smtc_VRAMBaseAddress + DE_DATA_PORT_712; + hw.m_pDPR = smtc_VRAMBaseAddress + 0x00408000; hw.m_pVPR = hw.m_pLFB + 0x0040c000; #ifdef __BIG_ENDIAN if (sfb->fb.var.bits_per_pixel == 32) { @@ -1034,28 +931,22 @@ static int __init smtcfb_pci_probe(struct pci_dev *pdev, #ifdef __BIG_ENDIAN if (sfb->fb.var.bits_per_pixel == 32) smtc_seqw(0x17, 0x30); -#endif -#ifdef CONFIG_FB_SM7XX_ACCEL - smtc_2Dacceleration = 1; #endif break; case 0x720: sfb->fb.fix.mmio_start = pFramebufferPhysical; sfb->fb.fix.mmio_len = 0x00200000; smem_size = SM722_VIDEOMEMORYSIZE; - smtc_2DBaseAddress = (hw.m_pDPR = - ioremap(pFramebufferPhysical, 0x00a00000)); + hw.m_pDPR = ioremap(pFramebufferPhysical, 0x00a00000); hw.m_pLFB = (smtc_VRAMBaseAddress = - smtc_2DBaseAddress + 0x00200000); + hw.m_pDPR + 0x00200000); hw.m_pMMIO = (smtc_RegBaseAddress = - smtc_2DBaseAddress + 0x000c0000); - smtc_2Ddataport = smtc_2DBaseAddress + DE_DATA_PORT_722; - hw.m_pVPR = smtc_2DBaseAddress + 0x800; + hw.m_pDPR + 0x000c0000); + hw.m_pVPR = hw.m_pDPR + 0x800; smtc_seqw(0x62, 0xff); smtc_seqw(0x6a, 0x0d); smtc_seqw(0x6b, 0x02); - smtc_2Dacceleration = 0; break; default: printk(KERN_INFO -- cgit v1.2.3 From 0289bb5d18ad57e23a7be681857f070980c66790 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Thu, 14 Jan 2010 21:25:56 +0100 Subject: Staging: rtl8192u: ieee80211: CurrentMPDUDensity assigned to itself in HTUseDefaultSetting() CurrentMPDUDensity was designed to itself. Signed-off-by: Roel Kluin Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c b/drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c index 3a5eaa59b21d..50f4f5943e75 100644 --- a/drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c +++ b/drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c @@ -1342,7 +1342,7 @@ void HTUseDefaultSetting(struct ieee80211_device* ieee) pHTInfo->CurrentAMPDUFactor = pHTInfo->AMPDU_Factor; - pHTInfo->CurrentMPDUDensity = pHTInfo->CurrentMPDUDensity; + pHTInfo->CurrentMPDUDensity = pHTInfo->MPDU_Density; // Set BWOpMode register -- cgit v1.2.3 From d2e01434fd9c01687a7cace957f182594cccc829 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Fri, 15 Jan 2010 12:08:01 +0100 Subject: Staging: comedi: adq12b: Checkpatch cleanups This fixes some checkpatch issues in the adq12b comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/adq12b.c | 48 ++++++++++++++++----------------- 1 file changed, 24 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/adq12b.c b/drivers/staging/comedi/drivers/adq12b.c index c5ed8bb97602..4590cac612d4 100644 --- a/drivers/staging/comedi/drivers/adq12b.c +++ b/drivers/staging/comedi/drivers/adq12b.c @@ -42,23 +42,23 @@ If you do not specify any options, they will default to option 1: I/O base address. The following table is provided as a help of the hardware jumpers. - address jumper JADR - 0x300 1 (factory default) - 0x320 2 - 0x340 3 - 0x360 4 - 0x380 5 - 0x3A0 6 + address jumper JADR + 0x300 1 (factory default) + 0x320 2 + 0x340 3 + 0x360 4 + 0x380 5 + 0x3A0 6 option 2: unipolar/bipolar ADC selection: 0 -> bipolar, 1 -> unipolar - selection comedi_config option JUB - bipolar 0 2-3 (factory default) - unipolar 1 1-2 + selection comedi_config option JUB + bipolar 0 2-3 (factory default) + unipolar 1 1-2 option 3: single-ended/differential AI selection: 0 -> SE, 1 -> differential - selection comedi_config option JCHA JCHB + selection comedi_config option JCHA JCHB single-ended 0 1-2 1-2 (factory default) differential 1 2-3 2-3 @@ -140,7 +140,7 @@ static const struct adq12b_board adq12b_boards[] = { .ai_bits = 12, .di_chans = 8, .do_chans = 5 - }*/ + }*/ }; #define thisboard ((const struct adq12b_board *)dev->board_ptr) @@ -164,14 +164,15 @@ struct adq12b_private { static int adq12b_attach(struct comedi_device *dev, struct comedi_devconfig *it); static int adq12b_detach(struct comedi_device *dev); + static struct comedi_driver driver_adq12b = { -driver_name:"adq12b", -module:THIS_MODULE, -attach:adq12b_attach, -detach:adq12b_detach, -board_name:&adq12b_boards[0].name, -offset:sizeof(struct adq12b_board), -num_names:ARRAY_SIZE(adq12b_boards), + .driver_name = "adq12b", + .module = THIS_MODULE, + .attach = adq12b_attach, + .detach = adq12b_detach, + .board_name = &adq12b_boards[0].name, + .offset = sizeof(struct adq12b_board), + .num_names = ARRAY_SIZE(adq12b_boards), }; static int adq12b_ai_rinsn(struct comedi_device *dev, @@ -259,11 +260,10 @@ static int adq12b_attach(struct comedi_device *dev, struct comedi_devconfig *it) s->n_chan = thisboard->ai_se_chans; } - if (unipolar) { + if (unipolar) s->range_table = &range_adq12b_ai_unipolar; - } else { + else s->range_table = &range_adq12b_ai_bipolar; - } s->maxdata = (1 << thisboard->ai_bits) - 1; @@ -344,11 +344,11 @@ static int adq12b_ai_rinsn(struct comedi_device *dev, /* wait for end of convertion */ i = 0; do { -/* udelay(1); */ + /* udelay(1); */ status = inb(dev->iobase + ADQ12B_STINR); status = status & ADQ12B_EOC; } while (status == 0 && ++i < TIMEOUT); -/* } while (++i < 10); */ + /* } while (++i < 10); */ /* read data */ hi = inb(dev->iobase + ADQ12B_ADHIG); -- cgit v1.2.3 From 23d53b1768f9396d0e259a9b4e62bfcc03122bab Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Fri, 15 Jan 2010 17:37:47 +0100 Subject: Staging: comedi: c6xdigio: Checkpatch cleanups This fixes some checkpatch issues and some spelling mistakes in the c6xdigio comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/c6xdigio.c | 57 +++++++++++++++---------------- 1 file changed, 28 insertions(+), 29 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/c6xdigio.c b/drivers/staging/comedi/drivers/c6xdigio.c index abb0532182ba..fb0d5fa71765 100644 --- a/drivers/staging/comedi/drivers/c6xdigio.c +++ b/drivers/staging/comedi/drivers/c6xdigio.c @@ -45,7 +45,7 @@ http://robot0.ge.uiuc.edu/~spong/mecha/ #include #include #include -#include +#include #include #include "../comedidev.h" @@ -220,11 +220,11 @@ static int C6X_encInput(unsigned long baseAddr, unsigned channel) /* printk("Inside C6X_encInput\n"); */ enc.value = 0; - if (channel == 0) { + if (channel == 0) ppcmd = 0x48; - } else { + else ppcmd = 0x50; - } + WriteByteToHwPort(baseAddr, ppcmd); tmp = ReadByteFromHwPort(baseAddr + 1); while (((tmp & 0x80) == 0) && (timeout < C6XDIGIO_TIME_OUT)) { @@ -391,9 +391,8 @@ static int c6xdigio_ei_insn_read(struct comedi_device *dev, int n; int chan = CR_CHAN(insn->chanspec); - for (n = 0; n < insn->n; n++) { + for (n = 0; n < insn->n; n++) data[n] = (C6X_encInput(dev->iobase, chan) & 0xffffff); - } return n; } @@ -420,9 +419,9 @@ static void board_init(struct comedi_device *dev) static const struct pnp_device_id c6xdigio_pnp_tbl[] = { /* Standard LPT Printer Port */ - {.id = "PNP0400",.driver_data = 0}, + {.id = "PNP0400", .driver_data = 0}, /* ECP Printer Port */ - {.id = "PNP0401",.driver_data = 0}, + {.id = "PNP0401", .driver_data = 0}, {} }; @@ -452,15 +451,14 @@ static int c6xdigio_attach(struct comedi_device *dev, if (result < 0) return result; - /* Make sure that PnP ports gets activated */ + /* Make sure that PnP ports get activated */ pnp_register_driver(&c6xdigio_pnp_driver); irq = it->options[1]; - if (irq > 0) { + if (irq > 0) printk("comedi%d: irq = %u ignored\n", dev->minor, irq); - } else if (irq == 0) { + else if (irq == 0) printk("comedi%d: no irq\n", dev->minor); - } s = dev->subdevices + 0; /* pwm output subdevice */ @@ -483,19 +481,19 @@ static int c6xdigio_attach(struct comedi_device *dev, s->maxdata = 0xffffff; s->range_table = &range_unknown; - /* s = dev->subdevices + 2; */ + /* s = dev->subdevices + 2; */ /* pwm output subdevice */ - /* s->type = COMEDI_SUBD_COUNTER; // Not sure what to put here */ - /* s->subdev_flags = SDF_WRITEABLE; */ - /* s->n_chan = 1; */ - /* s->trig[0] = c6xdigio_ei_init; */ - /* s->insn_read = c6xdigio_ei_init_insn_read; */ - /* s->insn_write = c6xdigio_ei_init_insn_write; */ - /* s->maxdata = 0xFFFF; // Really just a don't care */ - /* s->range_table = &range_unknown; // Not sure what to put here */ - - /* I will call this init anyway but more than likely the DSP board will not be connect */ - /* when device driver is loaded. */ + /* s->type = COMEDI_SUBD_COUNTER; // Not sure what to put here */ + /* s->subdev_flags = SDF_WRITEABLE; */ + /* s->n_chan = 1; */ + /* s->trig[0] = c6xdigio_ei_init; */ + /* s->insn_read = c6xdigio_ei_init_insn_read; */ + /* s->insn_write = c6xdigio_ei_init_insn_write; */ + /* s->maxdata = 0xFFFF; // Really just a don't care */ + /* s->range_table = &range_unknown; // Not sure what to put here */ + + /* I will call this init anyway but more than likely the DSP board */ + /* will not be connected when device driver is loaded. */ board_init(dev); return 0; @@ -503,16 +501,17 @@ static int c6xdigio_attach(struct comedi_device *dev, static int c6xdigio_detach(struct comedi_device *dev) { -/* board_halt(dev); may not need this */ + /* board_halt(dev); may not need this */ printk("comedi%d: c6xdigio: remove\n", dev->minor); - if (dev->iobase) { + if (dev->iobase) release_region(dev->iobase, C6XDIGIO_SIZE); - } - if (dev->irq) { + + /* Not using IRQ so I am not sure if I need this */ + if (dev->irq) free_irq(dev->irq, dev); - } /* Not using IRQ so I am not sure if I need this */ + pnp_unregister_driver(&c6xdigio_pnp_driver); return 0; -- cgit v1.2.3 From 79a22d5c264f5ddfc8573aa7eb234fe62dd1ee32 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Fri, 15 Jan 2010 18:03:35 +0100 Subject: Staging: comedi: rti800: Checkpatch cleanups This fixes some checkpatch issues in the rti800 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/rti800.c | 41 ++++++++++++++++----------------- 1 file changed, 20 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/rti800.c b/drivers/staging/comedi/drivers/rti800.c index 2c9d05bd288c..f2ee5289dbf1 100644 --- a/drivers/staging/comedi/drivers/rti800.c +++ b/drivers/staging/comedi/drivers/rti800.c @@ -32,22 +32,22 @@ Configuration options: [0] - I/O port base address [1] - IRQ [2] - A/D reference - 0 = differential - 1 = pseudodifferential (common) - 2 = single-ended + 0 = differential + 1 = pseudodifferential (common) + 2 = single-ended [3] - A/D range - 0 = [-10,10] - 1 = [-5,5] - 2 = [0,10] + 0 = [-10,10] + 1 = [-5,5] + 2 = [0,10] [4] - A/D encoding - 0 = two's complement - 1 = straight binary + 0 = two's complement + 1 = straight binary [5] - DAC 0 range - 0 = [-10,10] - 1 = [0,10] + 0 = [-10,10] + 1 = [0,10] [6] - DAC 0 encoding - 0 = two's complement - 1 = straight binary + 0 = two's complement + 1 = straight binary [7] - DAC 1 range (same as DAC 0) [8] - DAC 1 encoding (same as DAC 0) */ @@ -240,9 +240,8 @@ static int rti800_ai_insn_read(struct comedi_device *dev, data[i] = inb(dev->iobase + RTI800_ADCLO); data[i] |= (0xf & inb(dev->iobase + RTI800_ADCHI)) << 8; - if (devpriv->adc_coding == adc_2comp) { + if (devpriv->adc_coding == adc_2comp) data[i] ^= 0x800; - } } return i; @@ -271,9 +270,9 @@ static int rti800_ao_insn_write(struct comedi_device *dev, for (i = 0; i < insn->n; i++) { devpriv->ao_readback[chan] = d = data[i]; - if (devpriv->dac0_coding == dac_2comp) { + if (devpriv->dac0_coding == dac_2comp) d ^= 0x800; - } + outb(d & 0xff, dev->iobase + (chan ? RTI800_DAC1LO : RTI800_DAC0LO)); outb(d >> 8, @@ -315,15 +314,15 @@ static int rti800_do_insn_bits(struct comedi_device *dev, options[0] - I/O port options[1] - irq options[2] - a/d mux - 0=differential, 1=pseudodiff, 2=single + 0=differential, 1=pseudodiff, 2=single options[3] - a/d range - 0=bipolar10, 1=bipolar5, 2=unipolar10 + 0=bipolar10, 1=bipolar5, 2=unipolar10 options[4] - a/d coding - 0=2's comp, 1=straight binary + 0=2's comp, 1=straight binary options[5] - dac0 range - 0=bipolar10, 1=unipolar10 + 0=bipolar10, 1=unipolar10 options[6] - dac0 coding - 0=2's comp, 1=straight binary + 0=2's comp, 1=straight binary options[7] - dac1 range options[8] - dac1 coding */ -- cgit v1.2.3 From f51f90300010937bc9a2455cef88366448a6e718 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Sat, 16 Jan 2010 16:59:22 +0100 Subject: Staging: go7007: Eliminate useless code The variable s is initialized twice to the same (side effect-free) expression. Drop one initialization. A simplified version of the semantic match that finds this problem is: (http://coccinelle.lip6.fr/) // @forall@ idexpression *x; identifier f!=ERR_PTR; @@ x = f(...) ... when != x ( x = f(...,<+...x...+>,...) | * x = f(...) ) // Signed-off-by: Julia Lawall Signed-off-by: Greg Kroah-Hartman --- drivers/staging/go7007/s2250-loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/go7007/s2250-loader.c b/drivers/staging/go7007/s2250-loader.c index ef833e0d63ae..1de2dfb16d3f 100644 --- a/drivers/staging/go7007/s2250-loader.c +++ b/drivers/staging/go7007/s2250-loader.c @@ -139,7 +139,7 @@ failed2: static void s2250loader_disconnect(struct usb_interface *interface) { - pdevice_extension_t s = usb_get_intfdata(interface); + pdevice_extension_t s; printk(KERN_INFO "s2250: disconnect\n"); lock_kernel(); s = usb_get_intfdata(interface); -- cgit v1.2.3 From 266bfbdd3eb7f080612977f22055c82b951b179e Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Sat, 16 Jan 2010 18:58:58 +0100 Subject: Staging: comedi: pcl711: Checkpatch cleanups This fixes some checkpatch issues in the pcl711 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcl711.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcl711.c b/drivers/staging/comedi/drivers/pcl711.c index 4914784f6995..a499f7070f72 100644 --- a/drivers/staging/comedi/drivers/pcl711.c +++ b/drivers/staging/comedi/drivers/pcl711.c @@ -207,11 +207,10 @@ static irqreturn_t pcl711_interrupt(int irq, void *d) /* FIXME! Nothing else sets ntrig! */ if (!(--devpriv->ntrig)) { - if (this_board->is_8112) { + if (this_board->is_8112) outb(1, dev->iobase + PCL711_MODE); - } else { + else outb(0, dev->iobase + PCL711_MODE); - } s->async->events |= COMEDI_CB_EOA; } @@ -232,15 +231,15 @@ static void pcl711_set_changain(struct comedi_device *dev, int chan) /* * Set the correct channel. The two channel banks are switched * using the mask value. - * NB: To use differential channels, you should use mask = 0x30, - * but I haven't written the support for this yet. /JJ + * NB: To use differential channels, you should use + * mask = 0x30, but I haven't written the support for this + * yet. /JJ */ - if (chan_register >= 8) { + if (chan_register >= 8) chan_register = 0x20 | (chan_register & 0x7); - } else { + else chan_register |= 0x10; - } } else { outb(chan_register, dev->iobase + PCL711_MUX); } @@ -256,15 +255,13 @@ static int pcl711_ai_insn(struct comedi_device *dev, struct comedi_subdevice *s, for (n = 0; n < insn->n; n++) { /* - * Write the correct mode (software polling) and start polling by writing - * to the trigger register + * Write the correct mode (software polling) and start polling + * by writing to the trigger register */ outb(1, dev->iobase + PCL711_MODE); - if (this_board->is_8112) { - } else { + if (!this_board->is_8112) outb(0, dev->iobase + PCL711_SOFTTRIG); - } i = PCL711_TIMEOUT; while (--i) { @@ -462,9 +459,8 @@ static int pcl711_ao_insn_read(struct comedi_device *dev, int n; int chan = CR_CHAN(insn->chanspec); - for (n = 0; n < insn->n; n++) { + for (n = 0; n < insn->n; n++) data[n] = devpriv->ao_readback[chan]; - } return n; @@ -619,9 +615,8 @@ static int pcl711_attach(struct comedi_device *dev, struct comedi_devconfig *it) this is the "base value" for the mode register, which is used for the irq on the PCL711 */ - if (this_board->is_pcl711b) { + if (this_board->is_pcl711b) devpriv->mode = (dev->irq << 4); - } /* clear DAC */ outb(0, dev->iobase + PCL711_DA0_LO); -- cgit v1.2.3 From 186539192c37c0ebe95ddac341cf7e037b096966 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Mon, 18 Jan 2010 12:48:16 +0100 Subject: Staging: comedi: pcl724: Checkpatch cleanups This fixes all checkpatch issues in the pcl724 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcl724.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcl724.c b/drivers/staging/comedi/drivers/pcl724.c index df1f4ef14616..0f103c328064 100644 --- a/drivers/staging/comedi/drivers/pcl724.c +++ b/drivers/staging/comedi/drivers/pcl724.c @@ -17,7 +17,7 @@ [0] - IO Base [1] - IRQ (0=disable IRQ) IRQ isn't supported at this time! [2] -number of DIO: - 0, 144: 144 DIO configuration + 0, 144: 144 DIO configuration 1, 96: 96 DIO configuration */ /* @@ -137,8 +137,8 @@ static int pcl724_attach(struct comedi_device *dev, struct comedi_devconfig *it) iorange = this_board->io_range; if ((this_board->can_have96) && ((it->options[1] == 1) || (it->options[1] == 96))) - iorange = PCL722_96_SIZE; /* PCL-724 in 96 DIO configuration */ - printk("comedi%d: pcl724: board=%s, 0x%03lx ", dev->minor, + iorange = PCL722_96_SIZE; /* PCL-724 in 96 DIO configuration */ + printk(KERN_INFO "comedi%d: pcl724: board=%s, 0x%03lx ", dev->minor, this_board->name, iobase); if (!request_region(iobase, iorange, "pcl724")) { printk("I/O port conflict\n"); @@ -155,16 +155,16 @@ static int pcl724_attach(struct comedi_device *dev, struct comedi_devconfig *it) irq = it->options[1]; if (irq) { /* we want to use IRQ */ if (((1 << irq) & this_board->IRQbits) == 0) { - printk - (", IRQ %u is out of allowed range, DISABLING IT", - irq); + printk(KERN_WARNING + ", IRQ %u is out of allowed range, " + "DISABLING IT", irq); irq = 0; /* Bad IRQ */ } else { if (request_irq (irq, interrupt_pcl724, 0, "pcl724", dev)) { - printk - (", unable to allocate IRQ %u, DISABLING IT", - irq); + printk(KERN_WARNING + ", unable to allocate IRQ %u, " + "DISABLING IT", irq); irq = 0; /* Can't use IRQ */ } else { printk(", irq=%u", irq); @@ -207,16 +207,14 @@ static int pcl724_detach(struct comedi_device *dev) { int i; -/* printk("comedi%d: pcl724: remove\n",dev->minor); */ + /* printk("comedi%d: pcl724: remove\n",dev->minor); */ - for (i = 0; i < dev->n_subdevices; i++) { + for (i = 0; i < dev->n_subdevices; i++) subdev_8255_cleanup(dev, dev->subdevices + i); - } #ifdef PCL724_IRQ - if (dev->irq) { + if (dev->irq) free_irq(dev->irq, dev); - } #endif release_region(dev->iobase, this_board->io_range); -- cgit v1.2.3 From acb60e915a68c44757e12c45a8cede11339b6172 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Mon, 18 Jan 2010 12:57:42 +0100 Subject: Staging: comedi: pcl725: Checkpatch cleanups This fixes all checkpatch issues in the pcl725 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcl725.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcl725.c b/drivers/staging/comedi/drivers/pcl725.c index 1da4941fce49..60261f4ba5b4 100644 --- a/drivers/staging/comedi/drivers/pcl725.c +++ b/drivers/staging/comedi/drivers/pcl725.c @@ -66,7 +66,7 @@ static int pcl725_attach(struct comedi_device *dev, struct comedi_devconfig *it) unsigned long iobase; iobase = it->options[0]; - printk("comedi%d: pcl725: 0x%04lx ", dev->minor, iobase); + printk(KERN_INFO "comedi%d: pcl725: 0x%04lx ", dev->minor, iobase); if (!request_region(iobase, PCL725_SIZE, "pcl725")) { printk("I/O port conflict\n"); return -EIO; @@ -96,14 +96,14 @@ static int pcl725_attach(struct comedi_device *dev, struct comedi_devconfig *it) s->insn_bits = pcl725_di_insn; s->range_table = &range_digital; - printk("\n"); + printk(KERN_INFO "\n"); return 0; } static int pcl725_detach(struct comedi_device *dev) { - printk("comedi%d: pcl725: remove\n", dev->minor); + printk(KERN_INFO "comedi%d: pcl725: remove\n", dev->minor); if (dev->iobase) release_region(dev->iobase, PCL725_SIZE); -- cgit v1.2.3 From 615d5b6c56ff6bfd6ae223e99df26cf28d55f566 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Mon, 18 Jan 2010 22:32:07 +0100 Subject: Staging: comedi: pcl730: Checkpatch cleanups This fixes all checkpatch issues in the pcl730 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcl730.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcl730.c b/drivers/staging/comedi/drivers/pcl730.c index c9859c90c152..e5e7bed21de0 100644 --- a/drivers/staging/comedi/drivers/pcl730.c +++ b/drivers/staging/comedi/drivers/pcl730.c @@ -99,7 +99,7 @@ static int pcl730_attach(struct comedi_device *dev, struct comedi_devconfig *it) iobase = it->options[0]; iorange = this_board->io_range; - printk("comedi%d: pcl730: board=%s 0x%04lx ", dev->minor, + printk(KERN_INFO "comedi%d: pcl730: board=%s 0x%04lx ", dev->minor, this_board->name, iobase); if (!request_region(iobase, iorange, "pcl730")) { printk("I/O port conflict\n"); @@ -152,14 +152,14 @@ static int pcl730_attach(struct comedi_device *dev, struct comedi_devconfig *it) s->range_table = &range_digital; s->private = (void *)PCL730_DIO_LO; - printk("\n"); + printk(KERN_INFO "\n"); return 0; } static int pcl730_detach(struct comedi_device *dev) { - printk("comedi%d: pcl730: remove\n", dev->minor); + printk(KERN_INFO "comedi%d: pcl730: remove\n", dev->minor); if (dev->iobase) release_region(dev->iobase, this_board->io_range); -- cgit v1.2.3 From 6c381c5775ea5eb799bdc790dd6d6d43fe966134 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Tue, 19 Jan 2010 21:46:48 +0100 Subject: Staging: Comedi: G1-3 status registers not read in ni_gpct_to_660x_register() Read from the right status register Signed-off-by: Roel Kluin Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_660x.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_660x.c b/drivers/staging/comedi/drivers/ni_660x.c index 404d3c516ed1..1e2041447667 100644 --- a/drivers/staging/comedi/drivers/ni_660x.c +++ b/drivers/staging/comedi/drivers/ni_660x.c @@ -691,13 +691,13 @@ static enum NI_660x_Register ni_gpct_to_660x_register(enum ni_gpct_register reg) ni_660x_register = G0StatusRegister; break; case NITIO_G1_Status_Reg: - ni_660x_register = G0StatusRegister; + ni_660x_register = G1StatusRegister; break; case NITIO_G2_Status_Reg: - ni_660x_register = G0StatusRegister; + ni_660x_register = G2StatusRegister; break; case NITIO_G3_Status_Reg: - ni_660x_register = G0StatusRegister; + ni_660x_register = G3StatusRegister; break; case NITIO_G0_Interrupt_Enable_Reg: ni_660x_register = G0InterruptEnable; -- cgit v1.2.3 From 7edfa10689615255e65909bb893fd8f8620cff92 Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Wed, 20 Jan 2010 13:04:44 +0000 Subject: Staging: comedi: pcl812: Correct AI scan counting The AI scan counter should be updated after every completed scan, not after every channel. Keep track of current channel. Signed-off-by: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcl812.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcl812.c b/drivers/staging/comedi/drivers/pcl812.c index 0a5bc3d6da8c..aa912735ddba 100644 --- a/drivers/staging/comedi/drivers/pcl812.c +++ b/drivers/staging/comedi/drivers/pcl812.c @@ -995,7 +995,9 @@ static irqreturn_t interrupt_pcl812_ai_int(int irq, void *d) outb(0, dev->iobase + PCL812_CLRINT); /* clear INT request */ - if (s->async->cur_chan == 0) { /* one scan done */ + s->async->cur_chan++; + if (s->async->cur_chan >= devpriv->ai_n_chan) { /* one scan done */ + s->async->cur_chan = 0; devpriv->ai_act_scan++; if (!(devpriv->ai_neverending)) if (devpriv->ai_act_scan >= devpriv->ai_scans) { /* all data sampled */ @@ -1021,7 +1023,9 @@ static void transfer_from_dma_buf(struct comedi_device *dev, for (i = len; i; i--) { comedi_buf_put(s->async, ptr[bufptr++]); /* get one sample */ - if (s->async->cur_chan == 0) { + s->async->cur_chan++; + if (s->async->cur_chan >= devpriv->ai_n_chan) { + s->async->cur_chan = 0; devpriv->ai_act_scan++; if (!devpriv->ai_neverending) if (devpriv->ai_act_scan >= devpriv->ai_scans) { /* all data sampled */ -- cgit v1.2.3 From 13de4f000ec491b16a820e4ed59de2c98b7807be Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Wed, 20 Jan 2010 13:04:45 +0000 Subject: Staging: comedi: pcl816: Correct AI scan counting For AI commands, the scan counter should be updated after every scan. In DMA mode, it was being updated after every repeated segment of the channel list. In non-DMA mode, it was being updated after every sample. Signed-off-by: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcl816.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcl816.c b/drivers/staging/comedi/drivers/pcl816.c index 852fe2458fdc..5c88ddc1fc05 100644 --- a/drivers/staging/comedi/drivers/pcl816.c +++ b/drivers/staging/comedi/drivers/pcl816.c @@ -202,6 +202,7 @@ struct pcl816_private { unsigned int ai_act_chanlist[16]; /* MUX setting for actual AI operations */ unsigned int ai_act_chanlist_len; /* how long is actual MUX list */ unsigned int ai_act_chanlist_pos; /* actual position in MUX list */ + unsigned int ai_n_chan; /* how many channels per scan */ unsigned int ai_poll_ptr; /* how many sampes transfer poll */ struct comedi_subdevice *sub_ai; /* ptr to AI subdevice */ #ifdef unused @@ -320,7 +321,9 @@ static irqreturn_t interrupt_pcl816_ai_mode13_int(int irq, void *d) if (++devpriv->ai_act_chanlist_pos >= devpriv->ai_act_chanlist_len) devpriv->ai_act_chanlist_pos = 0; - if (s->async->cur_chan == 0) { + s->async->cur_chan++; + if (s->async->cur_chan >= devpriv->ai_n_chan) { + s->async->cur_chan = 0; devpriv->ai_act_scan++; } @@ -353,6 +356,11 @@ static void transfer_from_dma_buf(struct comedi_device *dev, if (++devpriv->ai_act_chanlist_pos >= devpriv->ai_act_chanlist_len) { devpriv->ai_act_chanlist_pos = 0; + } + + s->async->cur_chan++; + if (s->async->cur_chan >= devpriv->ai_n_chan) { + s->async->cur_chan = 0; devpriv->ai_act_scan++; } @@ -647,6 +655,7 @@ static int pcl816_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) return -EINVAL; udelay(1); + devpriv->ai_n_chan = cmd->chanlist_len; devpriv->ai_act_scan = 0; s->async->cur_chan = 0; devpriv->irq_blocked = 1; -- cgit v1.2.3 From b3559cb1aa5f863e1ce9b94b518be7ddf6680e45 Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Wed, 20 Jan 2010 13:04:46 +0000 Subject: Staging: comedi: pcl818: Correct AI scan counting and channel checks For AI commands, the scan counter should be updated after every scan. It was being updated after every sample except for DMA mode where it was being updated after every repeated segment of the channel list. Also AI commands with multiple channels were being terminated with an error prematurely except in DMA mode. This was because the driver was comparing channel numbers received from the hardware (combined with the sample value) with the expected channel numbers to check for a "channel dropout". This test was failing incorrectly because the driver was not keeping the current position within the (repeated segment of the) channel list up to date. Signed-off-by: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcl818.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcl818.c b/drivers/staging/comedi/drivers/pcl818.c index d0481013a837..40ac293ad89d 100644 --- a/drivers/staging/comedi/drivers/pcl818.c +++ b/drivers/staging/comedi/drivers/pcl818.c @@ -557,8 +557,14 @@ conv_finish: comedi_event(dev, s); return IRQ_HANDLED; } - if (s->async->cur_chan == 0) { + devpriv->act_chanlist_pos++; + if (devpriv->act_chanlist_pos >= devpriv->act_chanlist_len) { + devpriv->act_chanlist_pos = 0; + } + s->async->cur_chan++; + if (s->async->cur_chan >= devpriv->ai_n_chan) { /* printk("E"); */ + s->async->cur_chan = 0; devpriv->ai_act_scan--; } @@ -627,9 +633,13 @@ static irqreturn_t interrupt_pcl818_ai_mode13_dma(int irq, void *d) devpriv->act_chanlist_pos++; if (devpriv->act_chanlist_pos >= devpriv->act_chanlist_len) { - devpriv->ai_act_scan--; devpriv->act_chanlist_pos = 0; } + s->async->cur_chan++; + if (s->async->cur_chan >= devpriv->ai_n_chan) { + s->async->cur_chan = 0; + devpriv->ai_act_scan--; + } if (!devpriv->neverending_ai) if (devpriv->ai_act_scan == 0) { /* all data sampled */ @@ -717,7 +727,14 @@ static irqreturn_t interrupt_pcl818_ai_mode13_dma_rtc(int irq, void *d) comedi_buf_put(s->async, dmabuf[bufptr++] >> 4); /* get one sample */ bufptr &= (devpriv->dmasamplsize - 1); - if (s->async->cur_chan == 0) { + devpriv->act_chanlist_pos++; + if (devpriv->act_chanlist_pos >= + devpriv->act_chanlist_len) { + devpriv->act_chanlist_pos = 0; + } + s->async->cur_chan++; + if (s->async->cur_chan >= devpriv->ai_n_chan) { + s->async->cur_chan = 0; devpriv->ai_act_scan--; } @@ -796,7 +813,13 @@ static irqreturn_t interrupt_pcl818_ai_mode13_fifo(int irq, void *d) comedi_buf_put(s->async, (lo >> 4) | (inb(dev->iobase + PCL818_FI_DATAHI) << 4)); /* get one sample */ - if (s->async->cur_chan == 0) { + devpriv->act_chanlist_pos++; + if (devpriv->act_chanlist_pos >= devpriv->act_chanlist_len) { + devpriv->act_chanlist_pos = 0; + } + s->async->cur_chan++; + if (s->async->cur_chan >= devpriv->ai_n_chan) { + s->async->cur_chan = 0; devpriv->ai_act_scan--; } -- cgit v1.2.3 From 61283d227c6b39e30afc6346db099521b0b64fa1 Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Wed, 20 Jan 2010 13:04:47 +0000 Subject: Staging: comedi: adv_pci1710: Correct AI scan count and channel checks For AI commands, the internal channel list used to check incoming data was only set up partially if the channel list contained repeats. Set it up fully. Also the current scan position was not updated properly when moving a block of data from the FIFO unless a whole number of scans was moved. Signed-off-by: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/adv_pci1710.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/adv_pci1710.c b/drivers/staging/comedi/drivers/adv_pci1710.c index 03c73a889048..82433864094f 100644 --- a/drivers/staging/comedi/drivers/adv_pci1710.c +++ b/drivers/staging/comedi/drivers/adv_pci1710.c @@ -724,6 +724,7 @@ static int move_block_from_fifo(struct comedi_device *dev, devpriv->ai_act_scan++; } } + s->async->cur_chan = j; DPRINTK("adv_pci1710 EDBG: END: move_block_from_fifo(...)\n"); return 0; } @@ -1230,6 +1231,12 @@ static void setup_channel_list(struct comedi_device *dev, DPRINTK("GS: %2d. [%4x]=%4x %4x\n", i, chanprog, range, devpriv->act_chanlist[i]); } +#ifdef PCI171x_PARANOIDCHECK + for ( ; i < n_chan; i++) { /* store remainder of channel list */ + devpriv->act_chanlist[i] = + (CR_CHAN(chanlist[i]) << 12) & 0xf000; + } +#endif devpriv->ai_et_MuxVal = CR_CHAN(chanlist[0]) | (CR_CHAN(chanlist[seglen - 1]) << 8); -- cgit v1.2.3 From 8f87b832dea11dd00f6a30aaaf934c5c93556cfe Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Wed, 20 Jan 2010 13:04:48 +0000 Subject: Staging: comedi: adv_pci1710: Remove unneeded chanlist_len check For AI command testing, the driver does not need to range-check the length of the channel list as the comedi core has already checked it. Signed-off-by: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/adv_pci1710.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/adv_pci1710.c b/drivers/staging/comedi/drivers/adv_pci1710.c index 82433864094f..394d2ea19c2e 100644 --- a/drivers/staging/comedi/drivers/adv_pci1710.c +++ b/drivers/staging/comedi/drivers/adv_pci1710.c @@ -1035,14 +1035,6 @@ static int pci171x_ai_cmdtest(struct comedi_device *dev, } } - if (!cmd->chanlist_len) { - cmd->chanlist_len = 1; - err++; - } - if (cmd->chanlist_len > this_board->n_aichan) { - cmd->chanlist_len = this_board->n_aichan; - err++; - } if (cmd->scan_end_arg != cmd->chanlist_len) { cmd->scan_end_arg = cmd->chanlist_len; err++; -- cgit v1.2.3 From c203b521e64e062d94f1ced1510206c0a55d5b55 Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Wed, 20 Jan 2010 13:04:49 +0000 Subject: Staging: comedi: pcl812: Update MUX for multi-channel AI command For multi-channel AI commands, the interrupt handler is missing code to switch to the next channel. Add some (untested) code to handle this. Signed-off-by: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcl812.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcl812.c b/drivers/staging/comedi/drivers/pcl812.c index aa912735ddba..d4634c4f02dc 100644 --- a/drivers/staging/comedi/drivers/pcl812.c +++ b/drivers/staging/comedi/drivers/pcl812.c @@ -955,6 +955,7 @@ static irqreturn_t interrupt_pcl812_ai_int(int irq, void *d) unsigned int mask, timeout; struct comedi_device *dev = d; struct comedi_subdevice *s = dev->subdevices + 0; + unsigned int next_chan; s->async->events = 0; @@ -993,11 +994,18 @@ static irqreturn_t interrupt_pcl812_ai_int(int irq, void *d) ((inb(dev->iobase + PCL812_AD_HI) << 8) | inb(dev->iobase + PCL812_AD_LO)) & mask); + /* Set up next channel. Added by abbotti 2010-01-20, but untested. */ + next_chan = s->async->cur_chan + 1; + if (next_chan >= devpriv->ai_n_chan) + next_chan = 0; + if (devpriv->ai_chanlist[s->async->cur_chan] != + devpriv->ai_chanlist[next_chan]) + setup_range_channel(dev, s, devpriv->ai_chanlist[next_chan], 0); + outb(0, dev->iobase + PCL812_CLRINT); /* clear INT request */ - s->async->cur_chan++; - if (s->async->cur_chan >= devpriv->ai_n_chan) { /* one scan done */ - s->async->cur_chan = 0; + s->async->cur_chan = next_chan; + if (next_chan == 0) { /* one scan done */ devpriv->ai_act_scan++; if (!(devpriv->ai_neverending)) if (devpriv->ai_act_scan >= devpriv->ai_scans) { /* all data sampled */ -- cgit v1.2.3 From 64a1f7bd56e0f26bd4dd621805facffde9fbb0a3 Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Wed, 20 Jan 2010 13:04:50 +0000 Subject: Staging: comedi: pcl816: Check channel list in AI command test Check the channel list is valid in step 5 of the AI command test. Split function check_and_setup_channel_list() in two. Also, remove unnecessary chanlist_len tests in step 3 of the AI command test as the comedi core has already checked it. Signed-off-by: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcl816.c | 55 +++++++++++++++++++++------------ 1 file changed, 36 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcl816.c b/drivers/staging/comedi/drivers/pcl816.c index 5c88ddc1fc05..9820759ec54f 100644 --- a/drivers/staging/comedi/drivers/pcl816.c +++ b/drivers/staging/comedi/drivers/pcl816.c @@ -214,9 +214,12 @@ struct pcl816_private { /* ============================================================================== */ -static int check_and_setup_channel_list(struct comedi_device *dev, - struct comedi_subdevice *s, - unsigned int *chanlist, int chanlen); +static int check_channel_list(struct comedi_device *dev, + struct comedi_subdevice *s, + unsigned int *chanlist, unsigned int chanlen); +static void setup_channel_list(struct comedi_device *dev, + struct comedi_subdevice *s, + unsigned int *chanlist, unsigned int seglen); static int pcl816_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s); static void start_pacer(struct comedi_device *dev, int mode, @@ -566,14 +569,6 @@ static int pcl816_ai_cmdtest(struct comedi_device *dev, } } - if (!cmd->chanlist_len) { - cmd->chanlist_len = 1; - err++; - } - if (cmd->chanlist_len > this_board->n_aichan) { - cmd->chanlist_len = this_board->n_aichan; - err++; - } if (cmd->scan_end_arg != cmd->chanlist_len) { cmd->scan_end_arg = cmd->chanlist_len; err++; @@ -611,6 +606,14 @@ static int pcl816_ai_cmdtest(struct comedi_device *dev, return 4; } + /* step 5: complain about special chanlist considerations */ + + if (cmd->chanlist) { + if (!check_channel_list(dev, s, cmd->chanlist, + cmd->chanlist_len)) + return 5; /* incorrect channels list */ + } + return 0; } @@ -618,6 +621,7 @@ static int pcl816_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) { unsigned int divisor1 = 0, divisor2 = 0, dma_flags, bytes, dmairq; struct comedi_cmd *cmd = &s->async->cmd; + unsigned int seglen; if (cmd->start_src != TRIG_NOW) return -EINVAL; @@ -650,9 +654,10 @@ static int pcl816_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) start_pacer(dev, -1, 0, 0); /* stop pacer */ - if (!check_and_setup_channel_list(dev, s, cmd->chanlist, - cmd->chanlist_len)) + seglen = check_channel_list(dev, s, cmd->chanlist, cmd->chanlist_len); + if (seglen < 1) return -EINVAL; + setup_channel_list(dev, s, cmd->chanlist, seglen); udelay(1); devpriv->ai_n_chan = cmd->chanlist_len; @@ -880,12 +885,12 @@ start_pacer(struct comedi_device *dev, int mode, unsigned int divisor1, /* ============================================================================== Check if channel list from user is builded correctly - If it's ok, then program scan/gain logic + If it's ok, then return non-zero length of repeated segment of channel list */ static int -check_and_setup_channel_list(struct comedi_device *dev, - struct comedi_subdevice *s, unsigned int *chanlist, - int chanlen) +check_channel_list(struct comedi_device *dev, + struct comedi_subdevice *s, unsigned int *chanlist, + unsigned int chanlen) { unsigned int chansegment[16]; unsigned int i, nowmustbechan, seglen, segpos; @@ -939,6 +944,20 @@ check_and_setup_channel_list(struct comedi_device *dev, seglen = 1; } + return seglen; /* we can serve this with MUX logic */ +} + +/* +============================================================================== + Program scan/gain logic with channel list. +*/ +static void +setup_channel_list(struct comedi_device *dev, + struct comedi_subdevice *s, unsigned int *chanlist, + unsigned int seglen) +{ + unsigned int i; + devpriv->ai_act_chanlist_len = seglen; devpriv->ai_act_chanlist_pos = 0; @@ -951,8 +970,6 @@ check_and_setup_channel_list(struct comedi_device *dev, udelay(1); outb(devpriv->ai_act_chanlist[0] | (devpriv->ai_act_chanlist[seglen - 1] << 4), dev->iobase + PCL816_MUX); /* select channel interval to scan */ - - return 1; /* we can serve this with MUX logic */ } #ifdef unused -- cgit v1.2.3 From 57ac827c9b17f2cc2f0f86c4fd43c3597c40253c Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Wed, 20 Jan 2010 13:04:51 +0000 Subject: Staging: comedi: pcl818: Remove unneeded chanlist_len check For AI command testing, the driver does not need to range-check the length of the channel list as the comedi core has already checked it. Signed-off-by: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcl818.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcl818.c b/drivers/staging/comedi/drivers/pcl818.c index 40ac293ad89d..c9d75385755d 100644 --- a/drivers/staging/comedi/drivers/pcl818.c +++ b/drivers/staging/comedi/drivers/pcl818.c @@ -1392,14 +1392,6 @@ static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, } } - if (!cmd->chanlist_len) { - cmd->chanlist_len = 1; - err++; - } - if (cmd->chanlist_len > s->n_chan) { - cmd->chanlist_len = s->n_chan; - err++; - } if (cmd->scan_end_arg != cmd->chanlist_len) { cmd->scan_end_arg = cmd->chanlist_len; err++; -- cgit v1.2.3 From a2c3fdb996a926a45622428405a042f011eb03ba Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Sun, 17 Jan 2010 16:44:37 +0100 Subject: Staging: rt2860/sta_ioctl.c: Two branches the same in rt_ioctl_giwscan() Regardless of the condition, the branches execute the same code Signed-off-by: Roel Kluin Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rt2860/sta_ioctl.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rt2860/sta_ioctl.c b/drivers/staging/rt2860/sta_ioctl.c index d8fbe6cc6941..de4b6277baee 100644 --- a/drivers/staging/rt2860/sta_ioctl.c +++ b/drivers/staging/rt2860/sta_ioctl.c @@ -975,10 +975,7 @@ int rt_ioctl_giwscan(struct net_device *dev, /*================================ */ memset(&iwe, 0, sizeof(iwe)); iwe.cmd = SIOCGIWFREQ; - if (INFRA_ON(pAdapter) || ADHOC_ON(pAdapter)) - iwe.u.freq.m = pAdapter->ScanTab.BssEntry[i].Channel; - else - iwe.u.freq.m = pAdapter->ScanTab.BssEntry[i].Channel; + iwe.u.freq.m = pAdapter->ScanTab.BssEntry[i].Channel; iwe.u.freq.e = 0; iwe.u.freq.i = 0; -- cgit v1.2.3 From 35f077dca73132dcac2cac1706417229a68f38c3 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Sun, 17 Jan 2010 16:50:10 +0100 Subject: Staging: serqt_usb2: Two branches the same in qt_set_termios() Regardless of the condition, the branches executed the same code Signed-off-by: Roel Kluin Signed-off-by: Greg Kroah-Hartman --- drivers/staging/serqt_usb2/serqt_usb2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/serqt_usb2/serqt_usb2.c b/drivers/staging/serqt_usb2/serqt_usb2.c index 375a50580a28..44f2d4eaf84b 100644 --- a/drivers/staging/serqt_usb2/serqt_usb2.c +++ b/drivers/staging/serqt_usb2/serqt_usb2.c @@ -1277,7 +1277,7 @@ static void qt_set_termios(struct tty_struct *tty, if (cflag & CSTOPB) new_LCR |= SERIAL_TWO_STOPB; else - new_LCR |= SERIAL_TWO_STOPB; + new_LCR |= SERIAL_ONE_STOPB; dbg("%s - 4\n", __func__); -- cgit v1.2.3 From 8838d2560a8ccbc5e03688d55bf075793b36a04e Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Mon, 18 Jan 2010 02:50:24 +0000 Subject: Staging: rt2870sta: constify RTUSBMultiWrite(), RTUSBFirmwareWrite() These functions do not modify the data they are passed. Signed-off-by: Ben Hutchings Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rt2860/rtmp.h | 6 +++--- drivers/staging/rt2870/common/rtusb_io.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rt2860/rtmp.h b/drivers/staging/rt2860/rtmp.h index c50abf4b8068..6c6503d2438f 100644 --- a/drivers/staging/rt2860/rtmp.h +++ b/drivers/staging/rt2860/rtmp.h @@ -4043,10 +4043,10 @@ int RTUSBMultiRead(struct rt_rtmp_adapter *pAd, u16 Offset, u8 *pData, u16 length); int RTUSBMultiWrite(struct rt_rtmp_adapter *pAd, - u16 Offset, u8 *pData, u16 length); + u16 Offset, const u8 *pData, u16 length); int RTUSBMultiWrite_OneByte(struct rt_rtmp_adapter *pAd, - u16 Offset, u8 *pData); + u16 Offset, const u8 *pData); int RTUSBReadBBPRegister(struct rt_rtmp_adapter *pAd, u8 Id, u8 *pValue); @@ -4112,7 +4112,7 @@ int RTUSBSingleWrite(struct rt_rtmp_adapter *pAd, u16 Offset, u16 Value); int RTUSBFirmwareWrite(struct rt_rtmp_adapter *pAd, - u8 *pFwImage, unsigned long FwLen); + const u8 *pFwImage, unsigned long FwLen); int RTUSBVenderReset(struct rt_rtmp_adapter *pAd); diff --git a/drivers/staging/rt2870/common/rtusb_io.c b/drivers/staging/rt2870/common/rtusb_io.c index 34443f2243f1..cf0d2f5dbc6c 100644 --- a/drivers/staging/rt2870/common/rtusb_io.c +++ b/drivers/staging/rt2870/common/rtusb_io.c @@ -84,7 +84,7 @@ static int RTUSBFirmwareRun(struct rt_rtmp_adapter *pAd) ======================================================================== */ int RTUSBFirmwareWrite(struct rt_rtmp_adapter *pAd, - u8 *pFwImage, unsigned long FwLen) + const u8 *pFwImage, unsigned long FwLen) { u32 MacReg; int Status; @@ -167,7 +167,7 @@ int RTUSBMultiRead(struct rt_rtmp_adapter *pAd, ======================================================================== */ int RTUSBMultiWrite_OneByte(struct rt_rtmp_adapter *pAd, - u16 Offset, u8 *pData) + u16 Offset, const u8 *pData) { int Status; @@ -175,18 +175,18 @@ int RTUSBMultiWrite_OneByte(struct rt_rtmp_adapter *pAd, Status = RTUSB_VendorRequest(pAd, USBD_TRANSFER_DIRECTION_OUT, DEVICE_VENDOR_REQUEST_OUT, - 0x6, 0, Offset, pData, 1); + 0x6, 0, Offset, (u8 *)pData, 1); return Status; } int RTUSBMultiWrite(struct rt_rtmp_adapter *pAd, - u16 Offset, u8 *pData, u16 length) + u16 Offset, const u8 *pData, u16 length) { int Status; u16 index = 0, Value; - u8 *pSrc = pData; + const u8 *pSrc = pData; u16 resude = 0; resude = length % 2; -- cgit v1.2.3 From c22202faade08b6b45f14fd86bfb57f79d73464c Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Mon, 18 Jan 2010 03:25:56 +0000 Subject: Staging: rt{2860,2870}sta: Use request_firmware() to load firmware When originally introduced into staging, these drivers had custom firmware-loading code which checked a version number and CRC at the end of each blob. This reintroduces those checks, using crc-ccitt instead of custom code. The removed firmware will be added to the linux-firmware.git repository. Based on work by Darren Salt . Signed-off-by: Ben Hutchings Tested-By: Darren Salt Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rt2860/Kconfig | 2 + drivers/staging/rt2860/common/firmware.h | 558 -------------------------- drivers/staging/rt2860/common/firmware_3070.h | 517 ------------------------ drivers/staging/rt2860/common/rtmp_mcu.c | 165 +++++--- drivers/staging/rt2860/rt_linux.c | 3 + drivers/staging/rt2860/rtmp.h | 1 + drivers/staging/rt2870/Kconfig | 2 + drivers/staging/rt3070/firmware.h | 558 -------------------------- drivers/staging/rt3090/firmware.h | 517 ------------------------ 9 files changed, 113 insertions(+), 2210 deletions(-) delete mode 100644 drivers/staging/rt2860/common/firmware.h delete mode 100644 drivers/staging/rt2860/common/firmware_3070.h delete mode 100644 drivers/staging/rt3070/firmware.h delete mode 100644 drivers/staging/rt3090/firmware.h (limited to 'drivers') diff --git a/drivers/staging/rt2860/Kconfig b/drivers/staging/rt2860/Kconfig index f9962b693128..f3a7e47df5e9 100644 --- a/drivers/staging/rt2860/Kconfig +++ b/drivers/staging/rt2860/Kconfig @@ -3,6 +3,8 @@ config RT2860 depends on PCI && X86 && WLAN select WIRELESS_EXT select WEXT_PRIV + select CRC_CCITT + select FW_LOADER ---help--- This is an experimental driver for the Ralink 2860 and 3090 wireless chips. diff --git a/drivers/staging/rt2860/common/firmware.h b/drivers/staging/rt2860/common/firmware.h deleted file mode 100644 index 2fecd32f7600..000000000000 --- a/drivers/staging/rt2860/common/firmware.h +++ /dev/null @@ -1,558 +0,0 @@ -/* - Copyright (c) 2007, Ralink Technology Corporation - All rights reserved. - - Redistribution. Redistribution and use in binary form, without - modification, are permitted provided that the following conditions are - met: - - * Redistributions must reproduce the above copyright notice and the - following disclaimer in the documentation and/or other materials - provided with the distribution. - * Neither the name of Ralink Technology Corporation nor the names of its - suppliers may be used to endorse or promote products derived from this - software without specific prior written permission. - * No reverse engineering, decompilation, or disassembly of this software - is permitted. - - Limited patent license. Ralink Technology Corporation grants a world-wide, - royalty-free, non-exclusive license under patents it now or hereafter - owns or controls to make, have made, use, import, offer to sell and - sell ("Utilize") this software, but solely to the extent that any - such patent is necessary to Utilize the software alone, or in - combination with an operating system licensed under an approved Open - Source license as listed by the Open Source Initiative at - http://opensource.org/licenses. The patent license shall not apply to - any other combinations which include this software. No hardware per - se is licensed hereunder. - - DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, - BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - DAMAGE. -*/ -/* AUTO GEN PLEASE DO NOT MODIFY IT */ -/* AUTO GEN PLEASE DO NOT MODIFY IT */ - - -u8 FirmwareImage_2860 [] = { -0x02, 0x03, 0x5e, 0x02, 0x02, 0xb1, 0x22, 0x22, 0xff, 0xff, 0xff, 0x02, 0x01, 0x82, 0xff, 0xff, -0xff, 0xff, 0xff, 0x02, 0x00, 0x1e, 0xff, 0xff, 0xff, 0xff, 0xff, 0x02, 0x01, 0x33, 0xc0, 0xe0, -0xc0, 0xf0, 0xc0, 0x83, 0xc0, 0x82, 0xc0, 0xd0, 0x75, 0xd0, 0x18, 0xc2, 0xaf, 0x30, 0x45, 0x03, -0x12, 0x10, 0x09, 0x90, 0x04, 0x16, 0xe0, 0x30, 0xe3, 0x03, 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0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x65, 0xd3, } ; diff --git a/drivers/staging/rt2860/common/rtmp_mcu.c b/drivers/staging/rt2860/common/rtmp_mcu.c index e80f587cff1a..844d4b987b78 100644 --- a/drivers/staging/rt2860/common/rtmp_mcu.c +++ b/drivers/staging/rt2860/common/rtmp_mcu.c @@ -37,35 +37,38 @@ #include "../rt_config.h" -#if defined(RT2860) || defined(RT3090) -#include "firmware.h" -#include "../../rt3090/firmware.h" -#endif -#ifdef RT2870 -#include "../../rt3070/firmware.h" -#include "firmware_3070.h" -#endif - -#include +#include +#include #ifdef RTMP_MAC_USB -/* */ -/* RT2870 Firmware Spec only used 1 oct for version expression */ -/* */ -#define FIRMWARE_MINOR_VERSION 7 -#endif /* RTMP_MAC_USB // */ -/* New 8k byte firmware size for RT3071/RT3072 */ -#define FIRMWAREIMAGE_MAX_LENGTH 0x2000 -#define FIRMWAREIMAGE_LENGTH (sizeof (FirmwareImage) / sizeof(u8)) -#define FIRMWARE_MAJOR_VERSION 0 +#define FIRMWAREIMAGE_LENGTH 0x1000 -#define FIRMWAREIMAGEV1_LENGTH 0x1000 -#define FIRMWAREIMAGEV2_LENGTH 0x1000 +#define FIRMWARE_2870_MIN_VERSION 12 +#define FIRMWARE_2870_FILENAME "rt2870.bin" +MODULE_FIRMWARE(FIRMWARE_2870_FILENAME); -#ifdef RTMP_MAC_PCI -#define FIRMWARE_MINOR_VERSION 2 -#endif /* RTMP_MAC_PCI // */ +#define FIRMWARE_3070_MIN_VERSION 17 +#define FIRMWARE_3070_FILENAME "rt3070.bin" +MODULE_FIRMWARE(FIRMWARE_3070_FILENAME); + +#define FIRMWARE_3071_MIN_VERSION 17 +#define FIRMWARE_3071_FILENAME "rt3071.bin" /* for RT3071/RT3072 */ +MODULE_FIRMWARE(FIRMWARE_3071_FILENAME); + +#else /* RTMP_MAC_PCI */ + +#define FIRMWAREIMAGE_LENGTH 0x2000 + +#define FIRMWARE_2860_MIN_VERSION 11 +#define FIRMWARE_2860_FILENAME "rt2860.bin" +MODULE_FIRMWARE(FIRMWARE_2860_FILENAME); + +#define FIRMWARE_3090_MIN_VERSION 19 +#define FIRMWARE_3090_FILENAME "rt3090.bin" /* for RT3090/RT3390 */ +MODULE_FIRMWARE(FIRMWARE_3090_FILENAME); + +#endif /* ======================================================================== @@ -90,6 +93,78 @@ int RtmpAsicEraseFirmware(struct rt_rtmp_adapter *pAd) return 0; } +static const struct firmware *rtmp_get_firmware(struct rt_rtmp_adapter *adapter) +{ + const char *name; + const struct firmware *fw = NULL; + u8 min_version; + struct device *dev; + int err; + + if (adapter->firmware) + return adapter->firmware; + +#ifdef RTMP_MAC_USB + if (IS_RT3071(adapter)) { + name = FIRMWARE_3071_FILENAME; + min_version = FIRMWARE_3071_MIN_VERSION; + } else if (IS_RT3070(adapter)) { + name = FIRMWARE_3070_FILENAME; + min_version = FIRMWARE_3070_MIN_VERSION; + } else { + name = FIRMWARE_2870_FILENAME; + min_version = FIRMWARE_2870_MIN_VERSION; + } + dev = &((struct os_cookie *)adapter->OS_Cookie)->pUsb_Dev->dev; +#else /* RTMP_MAC_PCI */ + if (IS_RT3090(adapter) || IS_RT3390(adapter)) { + name = FIRMWARE_3090_FILENAME; + min_version = FIRMWARE_3090_MIN_VERSION; + } else { + name = FIRMWARE_2860_FILENAME; + min_version = FIRMWARE_2860_MIN_VERSION; + } + dev = &((struct os_cookie *)adapter->OS_Cookie)->pci_dev->dev; +#endif + + err = request_firmware(&fw, name, dev); + if (err) { + dev_err(dev, "firmware file %s request failed (%d)\n", + name, err); + return NULL; + } + + if (fw->size < FIRMWAREIMAGE_LENGTH) { + dev_err(dev, "firmware file %s size is invalid\n", name); + goto invalid; + } + + /* is it new enough? */ + adapter->FirmwareVersion = fw->data[FIRMWAREIMAGE_LENGTH - 3]; + if (adapter->FirmwareVersion < min_version) { + dev_err(dev, + "firmware file %s is too old;" + " driver requires v%d or later\n", + name, min_version); + goto invalid; + } + + /* is the internal CRC correct? */ + if (crc_ccitt(0xffff, fw->data, FIRMWAREIMAGE_LENGTH - 2) != + (fw->data[FIRMWAREIMAGE_LENGTH - 2] | + (fw->data[FIRMWAREIMAGE_LENGTH - 1] << 8))) { + dev_err(dev, "firmware file %s failed internal CRC\n", name); + goto invalid; + } + + adapter->firmware = fw; + return fw; + +invalid: + release_firmware(fw); + return NULL; +} + /* ======================================================================== @@ -109,46 +184,16 @@ int RtmpAsicEraseFirmware(struct rt_rtmp_adapter *pAd) */ int RtmpAsicLoadFirmware(struct rt_rtmp_adapter *pAd) { - + const struct firmware *fw; int Status = NDIS_STATUS_SUCCESS; - u8 *pFirmwareImage = NULL; - unsigned long FileLength, Index; + unsigned long Index; u32 MacReg = 0; -#ifdef RTMP_MAC_USB - u32 Version = (pAd->MACVersion >> 16); -#endif - /* New 8k byte firmware size for RT3071/RT3072 */ - { -#ifdef RTMP_MAC_PCI - if (IS_RT3090(pAd) || IS_RT3390(pAd)) { - pFirmwareImage = FirmwareImage_3090; - FileLength = FIRMWAREIMAGE_MAX_LENGTH; - } else { - pFirmwareImage = FirmwareImage_2860; - FileLength = FIRMWAREIMAGE_MAX_LENGTH; - } -#endif /* RTMP_MAC_PCI // */ -#ifdef RTMP_MAC_USB - /* the firmware image consists of two parts */ - if ((Version != 0x2860) && (Version != 0x2872) && (Version != 0x3070)) { /* use the second part */ - /*printk("KH:Use New Version,part2\n"); */ - pFirmwareImage = - (u8 *)& - FirmwareImage_3070[FIRMWAREIMAGEV1_LENGTH]; - FileLength = FIRMWAREIMAGEV2_LENGTH; - } else { - /*printk("KH:Use New Version,part1\n"); */ - if (Version == 0x3070) - pFirmwareImage = FirmwareImage_3070; - else - pFirmwareImage = FirmwareImage_2870; - FileLength = FIRMWAREIMAGEV1_LENGTH; - } -#endif /* RTMP_MAC_USB // */ - } + fw = rtmp_get_firmware(pAd); + if (!fw) + return NDIS_STATUS_FAILURE; - RTMP_WRITE_FIRMWARE(pAd, pFirmwareImage, FileLength); + RTMP_WRITE_FIRMWARE(pAd, fw->data, FIRMWAREIMAGE_LENGTH); /* check if MCU is ready */ Index = 0; diff --git a/drivers/staging/rt2860/rt_linux.c b/drivers/staging/rt2860/rt_linux.c index 9d763b4f2261..b5c78aecf5e3 100644 --- a/drivers/staging/rt2860/rt_linux.c +++ b/drivers/staging/rt2860/rt_linux.c @@ -25,6 +25,7 @@ ************************************************************************* */ +#include #include #include "rt_config.h" @@ -260,6 +261,8 @@ void RTMPFreeAdapter(struct rt_rtmp_adapter *pAd) NdisFreeSpinLock(&pAd->irq_lock); + release_firmware(pAd->firmware); + vfree(pAd); /* pci_free_consistent(os_cookie->pci_dev,sizeof(struct rt_rtmp_adapter),pAd,os_cookie->pAd_pa); */ if (os_cookie) kfree(os_cookie); diff --git a/drivers/staging/rt2860/rtmp.h b/drivers/staging/rt2860/rtmp.h index 6c6503d2438f..4401a55bda67 100644 --- a/drivers/staging/rt2860/rtmp.h +++ b/drivers/staging/rt2860/rtmp.h @@ -1719,6 +1719,7 @@ struct rt_rtmp_adapter { void *OS_Cookie; /* save specific structure relative to OS */ struct net_device *net_dev; unsigned long VirtualIfCnt; + const struct firmware *firmware; struct rt_rtmp_chip_op chipOps; u16 ThisTbttNumToNextWakeUp; diff --git a/drivers/staging/rt2870/Kconfig b/drivers/staging/rt2870/Kconfig index fd3ba3a3b127..6ea172b433e9 100644 --- a/drivers/staging/rt2870/Kconfig +++ b/drivers/staging/rt2870/Kconfig @@ -3,5 +3,7 @@ config RT2870 depends on USB && X86 && WLAN select WIRELESS_EXT select WEXT_PRIV + select CRC_CCITT + select FW_LOADER ---help--- This is an experimental driver for the Ralink xx70 wireless chips. diff --git a/drivers/staging/rt3070/firmware.h b/drivers/staging/rt3070/firmware.h deleted file mode 100644 index 5cf9cbcf4ab6..000000000000 --- a/drivers/staging/rt3070/firmware.h +++ /dev/null @@ -1,558 +0,0 @@ -/* - Copyright (c) 2007, Ralink Technology Corporation - All rights reserved. - - Redistribution. Redistribution and use in binary form, without - modification, are permitted provided that the following conditions are - met: - - * Redistributions must reproduce the above copyright notice and the - following disclaimer in the documentation and/or other materials - provided with the distribution. - * Neither the name of Ralink Technology Corporation nor the names of its - suppliers may be used to endorse or promote products derived from this - software without specific prior written permission. - * No reverse engineering, decompilation, or disassembly of this software - is permitted. - - Limited patent license. Ralink Technology Corporation grants a world-wide, - royalty-free, non-exclusive license under patents it now or hereafter - owns or controls to make, have made, use, import, offer to sell and - sell ("Utilize") this software, but solely to the extent that any - such patent is necessary to Utilize the software alone, or in - combination with an operating system licensed under an approved Open - Source license as listed by the Open Source Initiative at - http://opensource.org/licenses. The patent license shall not apply to - any other combinations which include this software. No hardware per - se is licensed hereunder. - - DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, - BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - DAMAGE. -*/ -/* AUTO GEN PLEASE DO NOT MODIFY IT */ -/* AUTO GEN PLEASE DO NOT MODIFY IT */ - - -u8 FirmwareImage_2870 [] = { -0xff, 0xff, 0xff, 0x02, 0x10, 0x28, 0x02, 0x10, 0x32, 0x02, 0x10, 0x78, 0x02, 0x12, 0x67, 0x02, -0x12, 0x68, 0x02, 0x12, 0x87, 0x02, 0x12, 0x8c, 0x12, 0x12, 0x88, 0x22, 0x02, 0x16, 0x49, 0x02, -0x17, 0x1f, 0x02, 0x13, 0x77, 0x02, 0x12, 0x8d, 0x30, 0x05, 0x06, 0x20, 0x0d, 0x03, 0x12, 0x17, -0xc1, 0x22, 0x90, 0x01, 0x8c, 0xe0, 0x30, 0xe3, 0x1b, 0xe5, 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0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0xe3, 0x34, } ; -- cgit v1.2.3 From cffd4e16cd6e5893148c31f86d1b48db10b64baa Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 18 Jan 2010 14:23:20 +0300 Subject: Staging: rtl8187se: fix if statement I removed a misplace semicolon. It is clear from the indentation that TxPwrTracking87SE() was only supposed to be called if CheckTxPwrTracking() returned true. Signed-off-by: Dan Carpenter Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8187se/r8180_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8187se/r8180_core.c b/drivers/staging/rtl8187se/r8180_core.c index e0f13efdb15a..1fb9e1141df8 100644 --- a/drivers/staging/rtl8187se/r8180_core.c +++ b/drivers/staging/rtl8187se/r8180_core.c @@ -2566,7 +2566,7 @@ void watch_dog_adaptive(unsigned long data) // Tx Power Tracking on 87SE. #ifdef TX_TRACK //if( priv->bTxPowerTrack ) //lzm mod 080826 - if( CheckTxPwrTracking((struct net_device *)data)); + if (CheckTxPwrTracking((struct net_device *)data)) TxPwrTracking87SE((struct net_device *)data); #endif -- cgit v1.2.3 From 5fe68019c600ac0b92475654cbee66208dddb800 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 20 Jan 2010 17:29:10 -0500 Subject: Staging: crystalhd: fix build on powerpc Add necessary include to fix build on PowerPC Signed-off-by: Dave Airlie Signed-off-by: Jarod Wilson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/crystalhd/crystalhd_lnx.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/staging/crystalhd/crystalhd_lnx.h b/drivers/staging/crystalhd/crystalhd_lnx.h index d3f9fc43d2d4..d338ae97a4cf 100644 --- a/drivers/staging/crystalhd/crystalhd_lnx.h +++ b/drivers/staging/crystalhd/crystalhd_lnx.h @@ -40,6 +40,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3 From 09b25c6fa36ea3c961e75cede0f86f1fed5c33b5 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:32:39 +0000 Subject: Staging: et131x: kill off the FBR_NUM_DES type This is another 10 bit value with the high bits clear, and where the type doesn't get used anywhere properly anyway Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index e715e4dcb523..fcd968132263 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -451,18 +451,6 @@ typedef union _RXDMA_CSR_t { * 31-10: unused * 9-0: fbr ndesc */ -typedef union _RXDMA_FBR_NUM_DES_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused:22; /* bits 10-31 */ - u32 fbr_ndesc:10; /* bits 0-9 */ -#else - u32 fbr_ndesc:10; /* bits 0-9 */ - u32 unused:22; /* bits 10-31 */ -#endif - } bits; -} RXDMA_FBR_NUM_DES_t, *PRXDMA_FBR_NUM_DES_t; /* * structure for free buffer ring 0 available offset reg in rxdma address map -- cgit v1.2.3 From 7d9e15eb31debad09ef055290d04e162998b766f Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:32:44 +0000 Subject: Staging: et131x: kill of FBR_WORD2 This is only used meaningfully as a definition, we never mask and fetch the bits apart Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_rx.c | 8 ++++---- drivers/staging/et131x/et1310_rx.h | 15 +-------------- 2 files changed, 5 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c index 81c1a7478ad6..2600b2f7a623 100644 --- a/drivers/staging/et131x/et1310_rx.c +++ b/drivers/staging/et131x/et1310_rx.c @@ -640,7 +640,7 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev) for (entry = 0; entry < rx_local->Fbr1NumEntries; entry++) { fbr_entry->addr_hi = rx_local->Fbr[1]->PAHigh[entry]; fbr_entry->addr_lo = rx_local->Fbr[1]->PALow[entry]; - fbr_entry->word2.bits.bi = entry; + fbr_entry->word2 = entry; fbr_entry++; } @@ -665,7 +665,7 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev) for (entry = 0; entry < rx_local->Fbr0NumEntries; entry++) { fbr_entry->addr_hi = rx_local->Fbr[0]->PAHigh[entry]; fbr_entry->addr_lo = rx_local->Fbr[0]->PALow[entry]; - fbr_entry->word2.bits.bi = entry; + fbr_entry->word2 = entry; fbr_entry++; } @@ -1126,7 +1126,7 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd) */ next->addr_hi = rx_local->Fbr[1]->PAHigh[bi]; next->addr_lo = rx_local->Fbr[1]->PALow[bi]; - next->word2.value = bi; + next->word2 = bi; writel(bump_fbr(&rx_local->local_Fbr1_full, rx_local->Fbr1NumEntries - 1), @@ -1144,7 +1144,7 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd) */ next->addr_hi = rx_local->Fbr[0]->PAHigh[bi]; next->addr_lo = rx_local->Fbr[0]->PALow[bi]; - next->word2.value = bi; + next->word2 = bi; writel(bump_fbr(&rx_local->local_Fbr0_full, rx_local->Fbr0NumEntries - 1), diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h index 69514593612c..db252cafa94a 100644 --- a/drivers/staging/et131x/et1310_rx.h +++ b/drivers/staging/et131x/et1310_rx.h @@ -91,23 +91,10 @@ #define ALCATEL_BROADCAST_PKT 0x02000000 /* typedefs for Free Buffer Descriptors */ -typedef union _FBR_WORD2_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved:22; /* bits 10-31 */ - u32 bi:10; /* bits 0-9(Buffer Index) */ -#else - u32 bi:10; /* bits 0-9(Buffer Index) */ - u32 reserved:22; /* bit 10-31 */ -#endif - } bits; -} FBR_WORD2_t, *PFBR_WORD2_t; - typedef struct _FBR_DESC_t { u32 addr_lo; u32 addr_hi; - FBR_WORD2_t word2; + u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */ } FBR_DESC_t, *PFBR_DESC_t; /* Typedefs for Packet Status Ring Descriptors */ -- cgit v1.2.3 From 13a79c697f737c19b5dd2f642374d9f289f9b830 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:32:50 +0000 Subject: Staging: et131x: fbr_desc is now only sane types Clean up the typdef for fbr_desc itself so we know it is done Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_rx.c | 35 +++++++++++++++++------------------ drivers/staging/et131x/et1310_rx.h | 5 +++-- 2 files changed, 20 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c index 2600b2f7a623..6ae8f119d78e 100644 --- a/drivers/staging/et131x/et1310_rx.c +++ b/drivers/staging/et131x/et1310_rx.c @@ -170,7 +170,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) #endif /* Allocate an area of memory for Free Buffer Ring 1 */ - bufsize = (sizeof(FBR_DESC_t) * rx_ring->Fbr1NumEntries) + 0xfff; + bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr1NumEntries) + 0xfff; rx_ring->pFbr1RingVa = pci_alloc_consistent(adapter->pdev, bufsize, &rx_ring->pFbr1RingPa); @@ -199,7 +199,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) #ifdef USE_FBR0 /* Allocate an area of memory for Free Buffer Ring 0 */ - bufsize = (sizeof(FBR_DESC_t) * rx_ring->Fbr0NumEntries) + 0xfff; + bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr0NumEntries) + 0xfff; rx_ring->pFbr0RingVa = pci_alloc_consistent(adapter->pdev, bufsize, &rx_ring->pFbr0RingPa); @@ -450,12 +450,11 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) rx_ring->pFbr1RingVa = (void *)((uint8_t *) rx_ring->pFbr1RingVa - rx_ring->Fbr1offset); - bufsize = - (sizeof(FBR_DESC_t) * rx_ring->Fbr1NumEntries) + 0xfff; + bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr1NumEntries) + + 0xfff; - pci_free_consistent(adapter->pdev, - bufsize, - rx_ring->pFbr1RingVa, rx_ring->pFbr1RingPa); + pci_free_consistent(adapter->pdev, bufsize, + rx_ring->pFbr1RingVa, rx_ring->pFbr1RingPa); rx_ring->pFbr1RingVa = NULL; } @@ -484,8 +483,8 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) rx_ring->pFbr0RingVa = (void *)((uint8_t *) rx_ring->pFbr0RingVa - rx_ring->Fbr0offset); - bufsize = - (sizeof(FBR_DESC_t) * rx_ring->Fbr0NumEntries) + 0xfff; + bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr0NumEntries) + + 0xfff; pci_free_consistent(adapter->pdev, bufsize, @@ -596,7 +595,7 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev) { struct _RXDMA_t __iomem *rx_dma = &etdev->regs->rxdma; struct _rx_ring_t *rx_local = &etdev->RxRing; - PFBR_DESC_t fbr_entry; + struct fbr_desc *fbr_entry; u32 entry; u32 psr_num_des; unsigned long flags; @@ -636,7 +635,7 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev) rx_local->local_psr_full = 0; /* Now's the best time to initialize FBR1 contents */ - fbr_entry = (PFBR_DESC_t) rx_local->pFbr1RingVa; + fbr_entry = (struct fbr_desc *) rx_local->pFbr1RingVa; for (entry = 0; entry < rx_local->Fbr1NumEntries; entry++) { fbr_entry->addr_hi = rx_local->Fbr[1]->PAHigh[entry]; fbr_entry->addr_lo = rx_local->Fbr[1]->PALow[entry]; @@ -661,7 +660,7 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev) #ifdef USE_FBR0 /* Now's the best time to initialize FBR0 contents */ - fbr_entry = (PFBR_DESC_t) rx_local->pFbr0RingVa; + fbr_entry = (struct fbr_desc *) rx_local->pFbr0RingVa; for (entry = 0; entry < rx_local->Fbr0NumEntries; entry++) { fbr_entry->addr_hi = rx_local->Fbr[0]->PAHigh[entry]; fbr_entry->addr_lo = rx_local->Fbr[0]->PALow[entry]; @@ -1116,9 +1115,9 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd) spin_lock_irqsave(&etdev->FbrLock, flags); if (ri == 1) { - PFBR_DESC_t next = - (PFBR_DESC_t) (rx_local->pFbr1RingVa) + - INDEX10(rx_local->local_Fbr1_full); + struct fbr_desc *next = + (struct fbr_desc *) (rx_local->pFbr1RingVa) + + INDEX10(rx_local->local_Fbr1_full); /* Handle the Free Buffer Ring advancement here. Write * the PA / Buffer Index for the returned buffer into @@ -1134,9 +1133,9 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd) } #ifdef USE_FBR0 else { - PFBR_DESC_t next = - (PFBR_DESC_t) rx_local->pFbr0RingVa + - INDEX10(rx_local->local_Fbr0_full); + struct fbr_desc *next = (struct fbr_desc *) + rx_local->pFbr0RingVa + + INDEX10(rx_local->local_Fbr0_full); /* Handle the Free Buffer Ring advancement here. Write * the PA / Buffer Index for the returned buffer into diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h index db252cafa94a..afa670e57179 100644 --- a/drivers/staging/et131x/et1310_rx.h +++ b/drivers/staging/et131x/et1310_rx.h @@ -91,11 +91,12 @@ #define ALCATEL_BROADCAST_PKT 0x02000000 /* typedefs for Free Buffer Descriptors */ -typedef struct _FBR_DESC_t { +struct fbr_desc +{ u32 addr_lo; u32 addr_hi; u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */ -} FBR_DESC_t, *PFBR_DESC_t; +}; /* Typedefs for Packet Status Ring Descriptors */ typedef union _PKT_STAT_DESC_WORD0_t { -- cgit v1.2.3 From 1bd751c1abc1029e8a0ae63ef4f19357c735a2a3 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:32:55 +0000 Subject: Staging: et131x: Clean up rxdma_csr This is another set of flags as typedef that can be cleaned up. Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 58 ++++++++++------------------- drivers/staging/et131x/et1310_rx.c | 46 +++++++++++------------ 2 files changed, 41 insertions(+), 63 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index fcd968132263..e39fd5608c98 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -292,45 +292,25 @@ typedef struct _TXDMA_t { /* Location: */ /* * structure for control status reg in rxdma address map * Located at address 0x2000 + * + * CSR + * 0: halt + * 1-3: tc + * 4: fbr_big_endian + * 5: psr_big_endian + * 6: pkt_big_endian + * 7: dma_big_endian + * 8-9: fbr0_size + * 10: fbr0_enable + * 11-12: fbr1_size + * 13: fbr1_enable + * 14: unused + * 15: pkt_drop_disable + * 16: pkt_done_flush + * 17: halt_status + * 18-31: unused */ -typedef union _RXDMA_CSR_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused2:14; /* bits 18-31 */ - u32 halt_status:1; /* bit 17 */ - u32 pkt_done_flush:1; /* bit 16 */ - u32 pkt_drop_disable:1; /* bit 15 */ - u32 unused1:1; /* bit 14 */ - u32 fbr1_enable:1; /* bit 13 */ - u32 fbr1_size:2; /* bits 11-12 */ - u32 fbr0_enable:1; /* bit 10 */ - u32 fbr0_size:2; /* bits 8-9 */ - u32 dma_big_endian:1; /* bit 7 */ - u32 pkt_big_endian:1; /* bit 6 */ - u32 psr_big_endian:1; /* bit 5 */ - u32 fbr_big_endian:1; /* bit 4 */ - u32 tc:3; /* bits 1-3 */ - u32 halt:1; /* bit 0 */ -#else - u32 halt:1; /* bit 0 */ - u32 tc:3; /* bits 1-3 */ - u32 fbr_big_endian:1; /* bit 4 */ - u32 psr_big_endian:1; /* bit 5 */ - u32 pkt_big_endian:1; /* bit 6 */ - u32 dma_big_endian:1; /* bit 7 */ - u32 fbr0_size:2; /* bits 8-9 */ - u32 fbr0_enable:1; /* bit 10 */ - u32 fbr1_size:2; /* bits 11-12 */ - u32 fbr1_enable:1; /* bit 13 */ - u32 unused1:1; /* bit 14 */ - u32 pkt_drop_disable:1; /* bit 15 */ - u32 pkt_done_flush:1; /* bit 16 */ - u32 halt_status:1; /* bit 17 */ - u32 unused2:14; /* bits 18-31 */ -#endif - } bits; -} RXDMA_CSR_t, *PRXDMA_CSR_t; + /* * structure for dma writeback lo reg in rxdma address map @@ -521,7 +501,7 @@ typedef union _RXDMA_CSR_t { * Located at address 0x2000 */ typedef struct _RXDMA_t { /* Location: */ - RXDMA_CSR_t csr; /* 0x2000 */ + u32 csr; /* 0x2000 */ u32 dma_wb_base_lo; /* 0x2004 */ u32 dma_wb_base_hi; /* 0x2008 */ u32 num_pkt_done; /* 0x200C */ diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c index 6ae8f119d78e..e593ad654449 100644 --- a/drivers/staging/et131x/et1310_rx.c +++ b/drivers/staging/et131x/et1310_rx.c @@ -720,18 +720,17 @@ void SetRxDmaTimer(struct et131x_adapter *etdev) */ void et131x_rx_dma_disable(struct et131x_adapter *etdev) { - RXDMA_CSR_t csr; - + u32 csr; /* Setup the receive dma configuration register */ - writel(0x00002001, &etdev->regs->rxdma.csr.value); - csr.value = readl(&etdev->regs->rxdma.csr.value); - if (csr.bits.halt_status != 1) { + writel(0x00002001, &etdev->regs->rxdma.csr); + csr = readl(&etdev->regs->rxdma.csr); + if ((csr & 0x00020000) != 1) { /* Check halt status (bit 17) */ udelay(5); - csr.value = readl(&etdev->regs->rxdma.csr.value); - if (csr.bits.halt_status != 1) + csr = readl(&etdev->regs->rxdma.csr); + if ((csr & 0x00020000) != 1) dev_err(&etdev->pdev->dev, - "RX Dma failed to enter halt state. CSR 0x%08x\n", - csr.value); + "RX Dma failed to enter halt state. CSR 0x%08x\n", + csr); } } @@ -742,34 +741,33 @@ void et131x_rx_dma_disable(struct et131x_adapter *etdev) void et131x_rx_dma_enable(struct et131x_adapter *etdev) { /* Setup the receive dma configuration register for normal operation */ - RXDMA_CSR_t csr = { 0 }; + u32 csr = 0x2000; /* FBR1 enable */ - csr.bits.fbr1_enable = 1; if (etdev->RxRing.Fbr1BufferSize == 4096) - csr.bits.fbr1_size = 1; + csr |= 0x0800; else if (etdev->RxRing.Fbr1BufferSize == 8192) - csr.bits.fbr1_size = 2; + csr |= 0x1000; else if (etdev->RxRing.Fbr1BufferSize == 16384) - csr.bits.fbr1_size = 3; + csr |= 0x1800; #ifdef USE_FBR0 - csr.bits.fbr0_enable = 1; + csr |= 0x0400; /* FBR0 enable */ if (etdev->RxRing.Fbr0BufferSize == 256) - csr.bits.fbr0_size = 1; + csr |= 0x0100; else if (etdev->RxRing.Fbr0BufferSize == 512) - csr.bits.fbr0_size = 2; + csr |= 0x0200; else if (etdev->RxRing.Fbr0BufferSize == 1024) - csr.bits.fbr0_size = 3; + csr |= 0x0300; #endif - writel(csr.value, &etdev->regs->rxdma.csr.value); + writel(csr, &etdev->regs->rxdma.csr); - csr.value = readl(&etdev->regs->rxdma.csr.value); - if (csr.bits.halt_status != 0) { + csr = readl(&etdev->regs->rxdma.csr); + if ((csr & 0x00020000) != 0) { udelay(5); - csr.value = readl(&etdev->regs->rxdma.csr.value); - if (csr.bits.halt_status != 0) { + csr = readl(&etdev->regs->rxdma.csr); + if ((csr & 0x00020000) != 0) { dev_err(&etdev->pdev->dev, "RX Dma failed to exit halt state. CSR 0x%08x\n", - csr.value); + csr); } } } -- cgit v1.2.3 From 61d5ed8c62fcceba08812f176de233ea7c78f5da Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:33:01 +0000 Subject: Staging: et131x: Kill off the rxdma type We have a clean struct of this now so turn the top level typedefs into a struct Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 8 ++++---- drivers/staging/et131x/et1310_rx.c | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index e39fd5608c98..9a7a4d256b46 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -500,7 +500,7 @@ typedef struct _TXDMA_t { /* Location: */ * Rx DMA Module of JAGCore Address Mapping * Located at address 0x2000 */ -typedef struct _RXDMA_t { /* Location: */ +struct rxdma_regs { /* Location: */ u32 csr; /* 0x2000 */ u32 dma_wb_base_lo; /* 0x2004 */ u32 dma_wb_base_hi; /* 0x2008 */ @@ -530,7 +530,7 @@ typedef struct _RXDMA_t { /* Location: */ u32 fbr1_full_offset; /* 0x2068 */ u32 fbr1_rd_index; /* 0x206C */ u32 fbr1_min_des; /* 0x2070 */ -} RXDMA_t, *PRXDMA_t; +}; /* END OF RXDMA REGISTER ADDRESS MAP */ @@ -1688,9 +1688,9 @@ typedef struct _ADDRESS_MAP_t { TXDMA_t txdma; /* unused section of txdma address map */ u8 unused_txdma[4096 - sizeof(TXDMA_t)]; - RXDMA_t rxdma; + struct rxdma_regs rxdma; /* unused section of rxdma address map */ - u8 unused_rxdma[4096 - sizeof(RXDMA_t)]; + u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)]; TXMAC_t txmac; /* unused section of txmac address map */ u8 unused_txmac[4096 - sizeof(TXMAC_t)]; diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c index e593ad654449..ee6436a3475b 100644 --- a/drivers/staging/et131x/et1310_rx.c +++ b/drivers/staging/et131x/et1310_rx.c @@ -593,7 +593,7 @@ int et131x_init_recv(struct et131x_adapter *adapter) */ void ConfigRxDmaRegs(struct et131x_adapter *etdev) { - struct _RXDMA_t __iomem *rx_dma = &etdev->regs->rxdma; + struct rxdma_regs __iomem *rx_dma = &etdev->regs->rxdma; struct _rx_ring_t *rx_local = &etdev->RxRing; struct fbr_desc *fbr_entry; u32 entry; @@ -1097,7 +1097,7 @@ static inline u32 bump_fbr(u32 *fbr, u32 limit) void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd) { struct _rx_ring_t *rx_local = &etdev->RxRing; - struct _RXDMA_t __iomem *rx_dma = &etdev->regs->rxdma; + struct rxdma_regs __iomem *rx_dma = &etdev->regs->rxdma; uint16_t bi = rfd->bufferindex; uint8_t ri = rfd->ringindex; unsigned long flags; -- cgit v1.2.3 From 254472ac59e2298fe3af9edafe291439e7756645 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:33:07 +0000 Subject: Staging: et131x: kill EXP_ROM This is another unused type for the bin Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 21 --------------------- 1 file changed, 21 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index 9a7a4d256b46..f121961339c1 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -1662,22 +1662,6 @@ typedef struct _MMC_t { /* Location: */ /* END OF MMC REGISTER ADDRESS MAP */ -/* START OF EXP ROM REGISTER ADDRESS MAP */ - -/* - * Expansion ROM Module of JAGCore Address Mapping - */ - -/* Take this out until it is not empty */ -#if 0 -typedef struct _EXP_ROM_t { - -} EXP_ROM_t, *PEXP_ROM_t; -#endif - -/* END OF EXP ROM REGISTER ADDRESS MAP */ - - /* * JAGCore Address Mapping */ @@ -1709,11 +1693,6 @@ typedef struct _ADDRESS_MAP_t { /* unused section of address map */ u8 unused_[1015808]; -/* Take this out until it is not empty */ -#if 0 - EXP_ROM_t exp_rom; -#endif - u8 unused_exp_rom[4096]; /* MGS-size TBD */ u8 unused__[524288]; /* unused section of address map */ } ADDRESS_MAP_t, *PADDRESS_MAP_t; -- cgit v1.2.3 From 2b903327d34a48250da3f559a8906f3a55db9901 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:33:12 +0000 Subject: Staging: et131x: GLOBAL_t is now sane so kill the GLOBAL_t itself Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 10 ++++------ drivers/staging/et131x/et131x_initpci.c | 2 +- 2 files changed, 5 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index f121961339c1..16254b7603a1 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -149,7 +149,7 @@ * GLOBAL Module of JAGCore Address Mapping * Located at address 0x0000 */ -typedef struct _GLOBAL_t { /* Location: */ +struct global_regs { /* Location: */ u32 txq_start_addr; /* 0x0000 */ u32 txq_end_addr; /* 0x0004 */ u32 rxq_start_addr; /* 0x0008 */ @@ -165,9 +165,7 @@ typedef struct _GLOBAL_t { /* Location: */ u32 msi_config; /* 0x0030 */ u32 loopback; /* 0x0034 */ u32 watchdog_timer; /* 0x0038 */ -} GLOBAL_t, *PGLOBAL_t; - -/* END OF GLOBAL REGISTER ADDRESS MAP */ +}; /* START OF TXDMA REGISTER ADDRESS MAP */ @@ -1666,9 +1664,9 @@ typedef struct _MMC_t { /* Location: */ * JAGCore Address Mapping */ typedef struct _ADDRESS_MAP_t { - GLOBAL_t global; + struct global_regs global; /* unused section of global address map */ - u8 unused_global[4096 - sizeof(GLOBAL_t)]; + u8 unused_global[4096 - sizeof(struct global_regs)]; TXDMA_t txdma; /* unused section of txdma address map */ u8 unused_txdma[4096 - sizeof(TXDMA_t)]; diff --git a/drivers/staging/et131x/et131x_initpci.c b/drivers/staging/et131x/et131x_initpci.c index 0892b6a538db..e02b1cd98f55 100644 --- a/drivers/staging/et131x/et131x_initpci.c +++ b/drivers/staging/et131x/et131x_initpci.c @@ -327,7 +327,7 @@ void et131x_link_detection_handler(unsigned long data) */ void ConfigGlobalRegs(struct et131x_adapter *etdev) { - struct _GLOBAL_t __iomem *regs = &etdev->regs->global; + struct global_regs __iomem *regs = &etdev->regs->global; writel(0, ®s->rxq_start_addr); writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr); -- cgit v1.2.3 From 060a78a07a06d78e64a00a25f4a4a7d5fe7402d1 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:33:18 +0000 Subject: Staging: et131x: Kill off TXDMA_t All the contents are clean so kill off the top level typedefs Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 8 ++++---- drivers/staging/et131x/et1310_tx.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index 16254b7603a1..43bd3034d495 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -253,7 +253,7 @@ extern inline void add_12bit(u32 *v, int n) * Tx DMA Module of JAGCore Address Mapping * Located at address 0x1000 */ -typedef struct _TXDMA_t { /* Location: */ +struct txdma_regs { /* Location: */ u32 csr; /* 0x1000 */ u32 pr_base_hi; /* 0x1004 */ u32 pr_base_lo; /* 0x1008 */ @@ -280,7 +280,7 @@ typedef struct _TXDMA_t { /* Location: */ u32 DroppedTLPCount; /* 0x105c */ u32 NewServiceComplete; /* 0x1060 */ u32 EthernetPacketCount; /* 0x1064 */ -} TXDMA_t, *PTXDMA_t; +}; /* END OF TXDMA REGISTER ADDRESS MAP */ @@ -1667,9 +1667,9 @@ typedef struct _ADDRESS_MAP_t { struct global_regs global; /* unused section of global address map */ u8 unused_global[4096 - sizeof(struct global_regs)]; - TXDMA_t txdma; + struct txdma_regs txdma; /* unused section of txdma address map */ - u8 unused_txdma[4096 - sizeof(TXDMA_t)]; + u8 unused_txdma[4096 - sizeof(struct txdma_regs)]; struct rxdma_regs rxdma; /* unused section of rxdma address map */ u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)]; diff --git a/drivers/staging/et131x/et1310_tx.c b/drivers/staging/et131x/et1310_tx.c index 977e8b34e7a6..b0cb0579026e 100644 --- a/drivers/staging/et131x/et1310_tx.c +++ b/drivers/staging/et131x/et1310_tx.c @@ -200,7 +200,7 @@ void et131x_tx_dma_memory_free(struct et131x_adapter *adapter) */ void ConfigTxDmaRegs(struct et131x_adapter *etdev) { - struct _TXDMA_t __iomem *txdma = &etdev->regs->txdma; + struct txdma_regs __iomem *txdma = &etdev->regs->txdma; /* Load the hardware with the start of the transmit descriptor ring. */ writel((u32) ((u64)etdev->tx_ring.tx_desc_ring_pa >> 32), -- cgit v1.2.3 From 461e0e8b15864b2f8d7b13a5bf86acf40d7a6fd6 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:33:23 +0000 Subject: Staging: et131x: Kill off MMC_t The contents of MMC_t are clean so kill off the MMC_t typedef Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index 43bd3034d495..446b2acf2d98 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -1648,14 +1648,14 @@ typedef struct _MAC_STAT_t { /* Location: */ /* * Memory Control Module of JAGCore Address Mapping */ -typedef struct _MMC_t { /* Location: */ +struct mmc_regs { /* Location: */ u32 mmc_ctrl; /* 0x7000 */ u32 sram_access; /* 0x7004 */ u32 sram_word1; /* 0x7008 */ u32 sram_word2; /* 0x700C */ u32 sram_word3; /* 0x7010 */ u32 sram_word4; /* 0x7014 */ -} MMC_t, *PMMC_t; +}; /* END OF MMC REGISTER ADDRESS MAP */ @@ -1685,9 +1685,9 @@ typedef struct _ADDRESS_MAP_t { MAC_STAT_t macStat; /* unused section of mac stat address map */ u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)]; - MMC_t mmc; + struct mmc_regs mmc; /* unused section of mmc address map */ - u8 unused_mmc[4096 - sizeof(MMC_t)]; + u8 unused_mmc[4096 - sizeof(struct mmc_regs)]; /* unused section of address map */ u8 unused_[1015808]; -- cgit v1.2.3 From dc26ffc7729e5a35c7019a6fb7d306005fdae518 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:33:29 +0000 Subject: Staging: et131x: Kill MAC_STAT_t All the contents of this type are now clean, so kill the top level type as well Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 11 ++++++----- drivers/staging/et131x/et1310_mac.c | 16 ++++++++-------- 2 files changed, 14 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index 446b2acf2d98..11e7b656d45c 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -1464,8 +1464,9 @@ typedef struct _MAC_t { /* Location: */ /* * MAC STATS Module of JAGCore Address Mapping */ -typedef struct _MAC_STAT_t { /* Location: */ - u32 pad[32]; /* 0x6000 - 607C */ +struct macstat_regs +{ /* Location: */ + u32 pad[32]; /* 0x6000 - 607C */ /* Tx/Rx 0-64 Byte Frame Counter */ u32 TR64; /* 0x6080 */ @@ -1610,7 +1611,7 @@ typedef struct _MAC_STAT_t { /* Location: */ /* Carry Register Two Mask Register */ u32 Carry2M; /* 0x613C */ -} MAC_STAT_t, *PMAC_STAT_t; +}; /* END OF MAC STAT REGISTER ADDRESS MAP */ @@ -1682,9 +1683,9 @@ typedef struct _ADDRESS_MAP_t { MAC_t mac; /* unused section of mac address map */ u8 unused_mac[4096 - sizeof(MAC_t)]; - MAC_STAT_t macStat; + struct macstat_regs macstat; /* unused section of mac stat address map */ - u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)]; + u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)]; struct mmc_regs mmc; /* unused section of mmc address map */ u8 unused_mmc[4096 - sizeof(struct mmc_regs)]; diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c index b8a1f2037314..a02bce0c2807 100644 --- a/drivers/staging/et131x/et1310_mac.c +++ b/drivers/staging/et131x/et1310_mac.c @@ -384,8 +384,8 @@ void ConfigTxMacRegs(struct et131x_adapter *etdev) void ConfigMacStatRegs(struct et131x_adapter *etdev) { - struct _MAC_STAT_t __iomem *macstat = - &etdev->regs->macStat; + struct macstat_regs __iomem *macstat = + &etdev->regs->macstat; /* Next we need to initialize all the MAC_STAT registers to zero on * the device. @@ -456,8 +456,8 @@ void ConfigFlowControl(struct et131x_adapter *etdev) void UpdateMacStatHostCounters(struct et131x_adapter *etdev) { struct _ce_stats_t *stats = &etdev->Stats; - struct _MAC_STAT_t __iomem *macstat = - &etdev->regs->macStat; + struct macstat_regs __iomem *macstat = + &etdev->regs->macstat; stats->collisions += readl(&macstat->TNcl); stats->first_collision += readl(&macstat->TScl); @@ -493,11 +493,11 @@ void HandleMacStatInterrupt(struct et131x_adapter *etdev) /* Read the interrupt bits from the register(s). These are Clear On * Write. */ - Carry1 = readl(&etdev->regs->macStat.Carry1); - Carry2 = readl(&etdev->regs->macStat.Carry2); + Carry1 = readl(&etdev->regs->macstat.Carry1); + Carry2 = readl(&etdev->regs->macstat.Carry2); - writel(Carry1, &etdev->regs->macStat.Carry1); - writel(Carry2, &etdev->regs->macStat.Carry2); + writel(Carry1, &etdev->regs->macstat.Carry1); + writel(Carry2, &etdev->regs->macstat.Carry2); /* We need to do update the host copy of all the MAC_STAT counters. * For each counter, check it's overflow bit. If the overflow bit is -- cgit v1.2.3 From 61aa21f208314496c4fa6c28c4a96c610831ed5e Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:33:34 +0000 Subject: Staging: et131x: Clean up the rx status word types Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_rx.c | 10 ++++------ drivers/staging/et131x/et1310_rx.h | 28 ++++++---------------------- 2 files changed, 10 insertions(+), 28 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c index ee6436a3475b..0e12709ad762 100644 --- a/drivers/staging/et131x/et1310_rx.c +++ b/drivers/staging/et131x/et1310_rx.c @@ -797,21 +797,19 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) uint16_t bindex; u32 len; PKT_STAT_DESC_WORD0_t Word0; + u32 word1; /* RX Status block is written by the DMA engine prior to every * interrupt. It contains the next to be used entry in the Packet * Status Ring, and also the two Free Buffer rings. */ status = (PRX_STATUS_BLOCK_t) rx_local->pRxStatusVa; + word1 = status->Word1 >> 16; /* Get the useful bits */ - /* FIXME: tidy later when conversions complete */ - if (status->Word1.bits.PSRoffset == - (rx_local->local_psr_full & 0xFFF) && - status->Word1.bits.PSRwrap == - ((rx_local->local_psr_full >> 12) & 1)) { + /* Check the PSR and wrap bits do not match */ + if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF)) /* Looks like this ring is not updated yet */ return NULL; - } /* The packet status ring indicates that data is available. */ psr = (PPKT_STAT_DESC_t) (rx_local->pPSRingVa) + diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h index afa670e57179..a46788d564ec 100644 --- a/drivers/staging/et131x/et1310_rx.h +++ b/drivers/staging/et131x/et1310_rx.h @@ -211,36 +211,20 @@ typedef struct _PKT_STAT_DESC_t { * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word * which contains the Packet Status Ring available offset. + * + * bit 0-15 reserved + * bit 16-27 PSRoffset + * bit 28 PSRwrap + * bit 29-31 unused */ -#define RXSTAT1_OFFSET 16 -#define RXSTAT1_MASK 0xFFF -#define RXSTAT1_WRAP 0x10000000 - -typedef union _rxstat_word1_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 PSRunused:3; /* bits 29-31 */ - u32 PSRwrap:1; /* bit 28 */ - u32 PSRoffset:12; /* bits 16-27 */ - u32 reserved:16; /* bits 0-15 */ -#else - u32 reserved:16; /* bits 0-15 */ - u32 PSRoffset:12; /* bits 16-27 */ - u32 PSRwrap:1; /* bit 28 */ - u32 PSRunused:3; /* bits 29-31 */ -#endif - } bits; -} RXSTAT_WORD1_t, *PRXSTAT_WORD1_t; - /* * RX_STATUS_BLOCK_t is sructure representing the status of the Rx DMA engine * it sits in free memory, and is pointed to by 0x101c / 0x1020 */ typedef struct _rx_status_block_t { u32 Word0; - RXSTAT_WORD1_t Word1; + u32 Word1; } RX_STATUS_BLOCK_t, *PRX_STATUS_BLOCK_t; /* -- cgit v1.2.3 From c9a8ad187a67da5892ff1155960cd14912c49efb Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:33:40 +0000 Subject: Staging: et131x: kill off the rx interrupt state enum Another verbose enum we don't need Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_rx.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h index a46788d564ec..2ba74b5c664b 100644 --- a/drivers/staging/et131x/et1310_rx.h +++ b/drivers/staging/et131x/et1310_rx.h @@ -238,11 +238,6 @@ typedef struct _FbrLookupTable { u32 PALow[MAX_DESC_PER_RING_RX]; } FBRLOOKUPTABLE, *PFBRLOOKUPTABLE; -typedef enum { - ONE_PACKET_INTERRUPT, - FOUR_PACKET_INTERRUPT -} eRX_INTERRUPT_STATE_t, *PeRX_INTERRUPT_STATE_t; - /* * RX_RING_t is sructure representing the adaptor's local reference(s) to the * rings -- cgit v1.2.3 From f926d216502c55e3d1089e5845045d0c16004428 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:33:45 +0000 Subject: Staging: et131x: rx_status_block_t is now clean So kill off the top level type and turn it into a struct Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_rx.c | 12 ++++++------ drivers/staging/et131x/et1310_rx.h | 8 ++++---- 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c index 0e12709ad762..7a4134687100 100644 --- a/drivers/staging/et131x/et1310_rx.c +++ b/drivers/staging/et131x/et1310_rx.c @@ -361,8 +361,8 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) /* Allocate an area of memory for writeback of status information */ rx_ring->pRxStatusVa = pci_alloc_consistent(adapter->pdev, - sizeof(RX_STATUS_BLOCK_t), - &rx_ring->pRxStatusPa); + sizeof(struct rx_status_block), + &rx_ring->pRxStatusPa); if (!rx_ring->pRxStatusVa) { dev_err(&adapter->pdev->dev, "Cannot alloc memory for Status Block\n"); @@ -508,7 +508,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) /* Free area of memory for the writeback of status information */ if (rx_ring->pRxStatusVa) { pci_free_consistent(adapter->pdev, - sizeof(RX_STATUS_BLOCK_t), + sizeof(struct rx_status_block), rx_ring->pRxStatusVa, rx_ring->pRxStatusPa); rx_ring->pRxStatusVa = NULL; @@ -614,7 +614,7 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev) &rx_dma->dma_wb_base_hi); writel((u32) rx_local->pRxStatusPa, &rx_dma->dma_wb_base_lo); - memset(rx_local->pRxStatusVa, 0, sizeof(RX_STATUS_BLOCK_t)); + memset(rx_local->pRxStatusVa, 0, sizeof(struct rx_status_block)); /* Set the address and parameters of the packet status ring into the * 1310's registers @@ -786,7 +786,7 @@ void et131x_rx_dma_enable(struct et131x_adapter *etdev) PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) { struct _rx_ring_t *rx_local = &etdev->RxRing; - PRX_STATUS_BLOCK_t status; + struct rx_status_block *status; PPKT_STAT_DESC_t psr; PMP_RFD rfd; u32 i; @@ -803,7 +803,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) * interrupt. It contains the next to be used entry in the Packet * Status Ring, and also the two Free Buffer rings. */ - status = (PRX_STATUS_BLOCK_t) rx_local->pRxStatusVa; + status = (struct rx_status_block *)rx_local->pRxStatusVa; word1 = status->Word1 >> 16; /* Get the useful bits */ /* Check the PSR and wrap bits do not match */ diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h index 2ba74b5c664b..53ecddb36e84 100644 --- a/drivers/staging/et131x/et1310_rx.h +++ b/drivers/staging/et131x/et1310_rx.h @@ -219,13 +219,13 @@ typedef struct _PKT_STAT_DESC_t { */ /* - * RX_STATUS_BLOCK_t is sructure representing the status of the Rx DMA engine - * it sits in free memory, and is pointed to by 0x101c / 0x1020 + * struct rx_status_block is a structure representing the status of the Rx + * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020 */ -typedef struct _rx_status_block_t { +struct rx_status_block { u32 Word0; u32 Word1; -} RX_STATUS_BLOCK_t, *PRX_STATUS_BLOCK_t; +}; /* * Structure for look-up table holding free buffer ring pointers -- cgit v1.2.3 From 07563ac691c284a5b9402556a270b8cc14164ff8 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:33:51 +0000 Subject: Staging: et131x: Fix rx_status typing Use the proper pointer types for the higher level pointers to the rx_status object and kill casts Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_rx.c | 21 ++++++++++----------- drivers/staging/et131x/et1310_rx.h | 4 ++-- 2 files changed, 12 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c index 7a4134687100..6719c4ee6a72 100644 --- a/drivers/staging/et131x/et1310_rx.c +++ b/drivers/staging/et131x/et1310_rx.c @@ -360,16 +360,16 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) */ /* Allocate an area of memory for writeback of status information */ - rx_ring->pRxStatusVa = pci_alloc_consistent(adapter->pdev, + rx_ring->rx_status_block = pci_alloc_consistent(adapter->pdev, sizeof(struct rx_status_block), - &rx_ring->pRxStatusPa); - if (!rx_ring->pRxStatusVa) { + &rx_ring->rx_status_bus); + if (!rx_ring->rx_status_block) { dev_err(&adapter->pdev->dev, "Cannot alloc memory for Status Block\n"); return -ENOMEM; } rx_ring->NumRfd = NIC_DEFAULT_NUM_RFD; - printk("PRS %lx\n", (unsigned long)rx_ring->pRxStatusPa); + printk("PRS %lx\n", (unsigned long)rx_ring->rx_status_bus); /* Recv * pci_pool_create initializes a lookaside list. After successful @@ -506,12 +506,11 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) } /* Free area of memory for the writeback of status information */ - if (rx_ring->pRxStatusVa) { + if (rx_ring->rx_status_block) { pci_free_consistent(adapter->pdev, - sizeof(struct rx_status_block), - rx_ring->pRxStatusVa, rx_ring->pRxStatusPa); - - rx_ring->pRxStatusVa = NULL; + sizeof(struct rx_status_block), + rx_ring->rx_status_block, rx_ring->rx_status_bus); + rx_ring->rx_status_block = NULL; } /* Free receive buffer pool */ @@ -614,7 +613,7 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev) &rx_dma->dma_wb_base_hi); writel((u32) rx_local->pRxStatusPa, &rx_dma->dma_wb_base_lo); - memset(rx_local->pRxStatusVa, 0, sizeof(struct rx_status_block)); + memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block)); /* Set the address and parameters of the packet status ring into the * 1310's registers @@ -803,7 +802,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) * interrupt. It contains the next to be used entry in the Packet * Status Ring, and also the two Free Buffer rings. */ - status = (struct rx_status_block *)rx_local->pRxStatusVa; + status = rx_local->rx_status_block; word1 = status->Word1 >> 16; /* Get the useful bits */ /* Check the PSR and wrap bits do not match */ diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h index 53ecddb36e84..b84d811e2912 100644 --- a/drivers/staging/et131x/et1310_rx.h +++ b/drivers/staging/et131x/et1310_rx.h @@ -270,8 +270,8 @@ typedef struct _rx_ring_t { u32 local_psr_full; u32 PsrNumEntries; - void *pRxStatusVa; - dma_addr_t pRxStatusPa; + struct rx_status_block *rx_status_block; + dma_addr_t rx_status_bus; struct list_head RecvBufferPool; -- cgit v1.2.3 From 8a66278cf91c9b0bfedd70865954d5fccba02237 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:33:56 +0000 Subject: Staging: et131x: Clean up the fbr lookup table All the subtypes are sane so just turn it into something struct and linux like Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_rx.c | 65 +++++++++++++++++++------------------- drivers/staging/et131x/et1310_rx.h | 16 +++++----- 2 files changed, 40 insertions(+), 41 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c index 6719c4ee6a72..cdc9105d553f 100644 --- a/drivers/staging/et131x/et1310_rx.c +++ b/drivers/staging/et131x/et1310_rx.c @@ -116,10 +116,9 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) /* Alloc memory for the lookup table */ #ifdef USE_FBR0 - rx_ring->Fbr[0] = kmalloc(sizeof(FBRLOOKUPTABLE), GFP_KERNEL); + rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL); #endif - - rx_ring->Fbr[1] = kmalloc(sizeof(FBRLOOKUPTABLE), GFP_KERNEL); + rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL); /* The first thing we will do is configure the sizes of the buffer * rings. These will change based on jumbo packet support. Larger @@ -270,23 +269,23 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) /* Save the Virtual address of this index for quick * access later */ - rx_ring->Fbr[1]->Va[index] = + rx_ring->fbr[1]->virt[index] = (uint8_t *) rx_ring->Fbr1MemVa[i] + (j * rx_ring->Fbr1BufferSize) + Fbr1Offset; /* now store the physical address in the descriptor * so the device can access it */ - rx_ring->Fbr[1]->PAHigh[index] = + rx_ring->fbr[1]->bus_high[index] = (u32) (Fbr1TempPa >> 32); - rx_ring->Fbr[1]->PALow[index] = (u32) Fbr1TempPa; + rx_ring->fbr[1]->bus_low[index] = (u32) Fbr1TempPa; Fbr1TempPa += rx_ring->Fbr1BufferSize; - rx_ring->Fbr[1]->Buffer1[index] = - rx_ring->Fbr[1]->Va[index]; - rx_ring->Fbr[1]->Buffer2[index] = - rx_ring->Fbr[1]->Va[index] - 4; + rx_ring->fbr[1]->buffer1[index] = + rx_ring->fbr[1]->virt[index]; + rx_ring->fbr[1]->buffer2[index] = + rx_ring->fbr[1]->virt[index] - 4; } } @@ -319,20 +318,20 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) for (j = 0; j < FBR_CHUNKS; j++) { u32 index = (i * FBR_CHUNKS) + j; - rx_ring->Fbr[0]->Va[index] = + rx_ring->fbr[0]->virt[index] = (uint8_t *) rx_ring->Fbr0MemVa[i] + (j * rx_ring->Fbr0BufferSize) + Fbr0Offset; - rx_ring->Fbr[0]->PAHigh[index] = + rx_ring->fbr[0]->bus_high[index] = (u32) (Fbr0TempPa >> 32); - rx_ring->Fbr[0]->PALow[index] = (u32) Fbr0TempPa; + rx_ring->fbr[0]->bus_low[index] = (u32) Fbr0TempPa; Fbr0TempPa += rx_ring->Fbr0BufferSize; - rx_ring->Fbr[0]->Buffer1[index] = - rx_ring->Fbr[0]->Va[index]; - rx_ring->Fbr[0]->Buffer2[index] = - rx_ring->Fbr[0]->Va[index] - 4; + rx_ring->fbr[0]->buffer1[index] = + rx_ring->fbr[0]->virt[index]; + rx_ring->fbr[0]->buffer2[index] = + rx_ring->fbr[0]->virt[index] - 4; } } #endif @@ -525,10 +524,10 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) /* Free the FBR Lookup Table */ #ifdef USE_FBR0 - kfree(rx_ring->Fbr[0]); + kfree(rx_ring->fbr[0]); #endif - kfree(rx_ring->Fbr[1]); + kfree(rx_ring->fbr[1]); /* Reset Counters */ rx_ring->nReadyRecv = 0; @@ -609,9 +608,9 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev) * are ever returned, make sure the high part is retrieved here * before storing the adjusted address. */ - writel((u32) ((u64)rx_local->pRxStatusPa >> 32), + writel((u32) ((u64)rx_local->rx_status_bus >> 32), &rx_dma->dma_wb_base_hi); - writel((u32) rx_local->pRxStatusPa, &rx_dma->dma_wb_base_lo); + writel((u32) rx_local->rx_status_bus, &rx_dma->dma_wb_base_lo); memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block)); @@ -636,8 +635,8 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev) /* Now's the best time to initialize FBR1 contents */ fbr_entry = (struct fbr_desc *) rx_local->pFbr1RingVa; for (entry = 0; entry < rx_local->Fbr1NumEntries; entry++) { - fbr_entry->addr_hi = rx_local->Fbr[1]->PAHigh[entry]; - fbr_entry->addr_lo = rx_local->Fbr[1]->PALow[entry]; + fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry]; + fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry]; fbr_entry->word2 = entry; fbr_entry++; } @@ -661,8 +660,8 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev) /* Now's the best time to initialize FBR0 contents */ fbr_entry = (struct fbr_desc *) rx_local->pFbr0RingVa; for (entry = 0; entry < rx_local->Fbr0NumEntries; entry++) { - fbr_entry->addr_hi = rx_local->Fbr[0]->PAHigh[entry]; - fbr_entry->addr_lo = rx_local->Fbr[0]->PALow[entry]; + fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry]; + fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry]; fbr_entry->word2 = entry; fbr_entry++; } @@ -893,7 +892,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) if (len) { if (etdev->ReplicaPhyLoopbk == 1) { - buf = rx_local->Fbr[rindex]->Va[bindex]; + buf = rx_local->fbr[rindex]->virt[bindex]; if (memcmp(&buf[6], &etdev->CurrentAddress[0], ETH_ALEN) == 0) { @@ -917,8 +916,8 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) if ((etdev->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) && !(etdev->PacketFilter & ET131X_PACKET_TYPE_PROMISCUOUS) && !(etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST)) { - buf = rx_local->Fbr[rindex]-> - Va[bindex]; + buf = rx_local->fbr[rindex]-> + virt[bindex]; /* Loop through our list to see if the * destination address of this packet @@ -984,7 +983,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) etdev->net_stats.rx_bytes += rfd->PacketSize; memcpy(skb_put(skb, rfd->PacketSize), - rx_local->Fbr[rindex]->Va[bindex], + rx_local->fbr[rindex]->virt[bindex], rfd->PacketSize); skb->dev = etdev->netdev; @@ -1118,8 +1117,8 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd) * the PA / Buffer Index for the returned buffer into * the oldest (next to be freed)FBR entry */ - next->addr_hi = rx_local->Fbr[1]->PAHigh[bi]; - next->addr_lo = rx_local->Fbr[1]->PALow[bi]; + next->addr_hi = rx_local->fbr[1]->bus_high[bi]; + next->addr_lo = rx_local->fbr[1]->bus_low[bi]; next->word2 = bi; writel(bump_fbr(&rx_local->local_Fbr1_full, @@ -1136,8 +1135,8 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd) * the PA / Buffer Index for the returned buffer into * the oldest (next to be freed) FBR entry */ - next->addr_hi = rx_local->Fbr[0]->PAHigh[bi]; - next->addr_lo = rx_local->Fbr[0]->PALow[bi]; + next->addr_hi = rx_local->fbr[0]->bus_high[bi]; + next->addr_lo = rx_local->fbr[0]->bus_low[bi]; next->word2 = bi; writel(bump_fbr(&rx_local->local_Fbr0_full, diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h index b84d811e2912..a8915e6e59f0 100644 --- a/drivers/staging/et131x/et1310_rx.h +++ b/drivers/staging/et131x/et1310_rx.h @@ -230,13 +230,13 @@ struct rx_status_block { /* * Structure for look-up table holding free buffer ring pointers */ -typedef struct _FbrLookupTable { - void *Va[MAX_DESC_PER_RING_RX]; - void *Buffer1[MAX_DESC_PER_RING_RX]; - void *Buffer2[MAX_DESC_PER_RING_RX]; - u32 PAHigh[MAX_DESC_PER_RING_RX]; - u32 PALow[MAX_DESC_PER_RING_RX]; -} FBRLOOKUPTABLE, *PFBRLOOKUPTABLE; +struct fbr_lookup { + void *virt[MAX_DESC_PER_RING_RX]; + void *buffer1[MAX_DESC_PER_RING_RX]; + void *buffer2[MAX_DESC_PER_RING_RX]; + u32 bus_high[MAX_DESC_PER_RING_RX]; + u32 bus_low[MAX_DESC_PER_RING_RX]; +}; /* * RX_RING_t is sructure representing the adaptor's local reference(s) to the @@ -260,7 +260,7 @@ typedef struct _rx_ring_t { dma_addr_t Fbr1MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS]; uint64_t Fbr1Realpa; uint64_t Fbr1offset; - FBRLOOKUPTABLE *Fbr[2]; + struct fbr_lookup *fbr[2]; /* One per ring */ u32 local_Fbr1_full; u32 Fbr1NumEntries; u32 Fbr1BufferSize; -- cgit v1.2.3 From 4ba64c1ba5f26a445255dd7684c175e298d84d07 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:34:02 +0000 Subject: Staging: et131x: clean up the pkt_desc_stat_t types Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_rx.c | 49 +++++++------ drivers/staging/et131x/et1310_rx.h | 140 ++++++++++++------------------------- 2 files changed, 70 insertions(+), 119 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c index cdc9105d553f..a95e6c6705da 100644 --- a/drivers/staging/et131x/et1310_rx.c +++ b/drivers/staging/et131x/et1310_rx.c @@ -193,7 +193,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) &rx_ring->Fbr1Realpa, &rx_ring->Fbr1offset, 0x0FFF); - rx_ring->pFbr1RingVa = (void *)((uint8_t *) rx_ring->pFbr1RingVa + + rx_ring->pFbr1RingVa = (void *)((u8 *) rx_ring->pFbr1RingVa + rx_ring->Fbr1offset); #ifdef USE_FBR0 @@ -222,7 +222,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) &rx_ring->Fbr0Realpa, &rx_ring->Fbr0offset, 0x0FFF); - rx_ring->pFbr0RingVa = (void *)((uint8_t *) rx_ring->pFbr0RingVa + + rx_ring->pFbr0RingVa = (void *)((u8 *) rx_ring->pFbr0RingVa + rx_ring->Fbr0offset); #endif @@ -270,7 +270,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) * access later */ rx_ring->fbr[1]->virt[index] = - (uint8_t *) rx_ring->Fbr1MemVa[i] + + (u8 *) rx_ring->Fbr1MemVa[i] + (j * rx_ring->Fbr1BufferSize) + Fbr1Offset; /* now store the physical address in the descriptor @@ -319,7 +319,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) u32 index = (i * FBR_CHUNKS) + j; rx_ring->fbr[0]->virt[index] = - (uint8_t *) rx_ring->Fbr0MemVa[i] + + (u8 *) rx_ring->Fbr0MemVa[i] + (j * rx_ring->Fbr0BufferSize) + Fbr0Offset; rx_ring->fbr[0]->bus_high[index] = @@ -338,7 +338,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) /* Allocate an area of memory for FIFO of Packet Status ring entries */ pktStatRingSize = - sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries; + sizeof(struct pkt_stat_desc) * adapter->RxRing.PsrNumEntries; rx_ring->pPSRingVa = pci_alloc_consistent(adapter->pdev, pktStatRingSize, @@ -446,7 +446,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) } /* Now the FIFO itself */ - rx_ring->pFbr1RingVa = (void *)((uint8_t *) + rx_ring->pFbr1RingVa = (void *)((u8 *) rx_ring->pFbr1RingVa - rx_ring->Fbr1offset); bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr1NumEntries) @@ -479,7 +479,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) } /* Now the FIFO itself */ - rx_ring->pFbr0RingVa = (void *)((uint8_t *) + rx_ring->pFbr0RingVa = (void *)((u8 *) rx_ring->pFbr0RingVa - rx_ring->Fbr0offset); bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr0NumEntries) @@ -496,7 +496,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) /* Free Packet Status Ring */ if (rx_ring->pPSRingVa) { pktStatRingSize = - sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries; + sizeof(struct pkt_stat_desc) * adapter->RxRing.PsrNumEntries; pci_free_consistent(adapter->pdev, pktStatRingSize, rx_ring->pPSRingVa, rx_ring->pPSRingPa); @@ -785,16 +785,16 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) { struct _rx_ring_t *rx_local = &etdev->RxRing; struct rx_status_block *status; - PPKT_STAT_DESC_t psr; + struct pkt_stat_desc *psr; PMP_RFD rfd; u32 i; - uint8_t *buf; + u8 *buf; unsigned long flags; struct list_head *element; - uint8_t rindex; - uint16_t bindex; + u8 rindex; + u16 bindex; u32 len; - PKT_STAT_DESC_WORD0_t Word0; + u32 word0; u32 word1; /* RX Status block is written by the DMA engine prior to every @@ -810,17 +810,17 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) return NULL; /* The packet status ring indicates that data is available. */ - psr = (PPKT_STAT_DESC_t) (rx_local->pPSRingVa) + + psr = (struct pkt_stat_desc *) (rx_local->pPSRingVa) + (rx_local->local_psr_full & 0xFFF); /* Grab any information that is required once the PSR is * advanced, since we can no longer rely on the memory being * accurate */ - len = psr->word1.bits.length; - rindex = (uint8_t) psr->word1.bits.ri; - bindex = (uint16_t) psr->word1.bits.bi; - Word0 = psr->word0; + len = psr->word1 & 0xFFFF; + rindex = (psr->word1 >> 26) & 0x03; + bindex = (psr->word1 >> 16) & 0x3FF; + word0 = psr->word0; /* Indicate that we have used this PSR entry. */ /* FIXME wrap 12 */ @@ -835,9 +835,8 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) &etdev->regs->rxdma.psr_full_offset); #ifndef USE_FBR0 - if (rindex != 1) { + if (rindex != 1) return NULL; - } #endif #ifdef USE_FBR0 @@ -904,8 +903,8 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) } /* Determine if this is a multicast packet coming in */ - if ((Word0.value & ALCATEL_MULTICAST_PKT) && - !(Word0.value & ALCATEL_BROADCAST_PKT)) { + if ((word0 & ALCATEL_MULTICAST_PKT) && + !(word0 & ALCATEL_BROADCAST_PKT)) { /* Promiscuous mode and Multicast mode are * not mutually exclusive as was first * thought. I guess Promiscuous is just @@ -956,7 +955,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) if (len > 0) etdev->Stats.multircv++; - } else if (Word0.value & ALCATEL_BROADCAST_PKT) + } else if (word0 & ALCATEL_BROADCAST_PKT) etdev->Stats.brdcstrcv++; else /* Not sure what this counter measures in @@ -1094,8 +1093,8 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd) { struct _rx_ring_t *rx_local = &etdev->RxRing; struct rxdma_regs __iomem *rx_dma = &etdev->regs->rxdma; - uint16_t bi = rfd->bufferindex; - uint8_t ri = rfd->ringindex; + u16 bi = rfd->bufferindex; + u8 ri = rfd->ringindex; unsigned long flags; /* We don't use any of the OOB data besides status. Otherwise, we diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h index a8915e6e59f0..28e7665f46d4 100644 --- a/drivers/staging/et131x/et1310_rx.h +++ b/drivers/staging/et131x/et1310_rx.h @@ -98,101 +98,53 @@ struct fbr_desc u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */ }; -/* Typedefs for Packet Status Ring Descriptors */ -typedef union _PKT_STAT_DESC_WORD0_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - /* top 16 bits are from the Alcatel Status Word as enumerated in */ - /* PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2) */ -#if 0 - u32 asw_trunc:1; /* bit 31(Rx frame truncated) */ -#endif - u32 asw_long_evt:1; /* bit 31(Rx long event) */ - u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */ - u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */ - u32 asw_pause_frame:1; /* bit 28(is a pause frame) */ - u32 asw_control_frame:1; /* bit 27(is a control frame) */ - u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */ - u32 asw_broadcast:1; /* bit 25(has a broadcast address) */ - u32 asw_multicast:1; /* bit 24(has a multicast address) */ - u32 asw_OK:1; /* bit 23(valid CRC + no code error) */ - u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */ - u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */ - u32 asw_CRC_err:1; /* bit 20(CRC error) */ - u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */ - u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */ - u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */ - u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */ - u32 unused:5; /* bits 11-15 */ - u32 vp:1; /* bit 10(VLAN Packet) */ - u32 jp:1; /* bit 9(Jumbo Packet) */ - u32 ft:1; /* bit 8(Frame Truncated) */ - u32 drop:1; /* bit 7(Drop packet) */ - u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */ - u32 wol:1; /* bit 5(WOL Event) */ - u32 tcpp:1; /* bit 4(TCP checksum pass) */ - u32 tcpa:1; /* bit 3(TCP checksum assist) */ - u32 ipp:1; /* bit 2(IP checksum pass) */ - u32 ipa:1; /* bit 1(IP checksum assist) */ - u32 hp:1; /* bit 0(hash pass) */ -#else - u32 hp:1; /* bit 0(hash pass) */ - u32 ipa:1; /* bit 1(IP checksum assist) */ - u32 ipp:1; /* bit 2(IP checksum pass) */ - u32 tcpa:1; /* bit 3(TCP checksum assist) */ - u32 tcpp:1; /* bit 4(TCP checksum pass) */ - u32 wol:1; /* bit 5(WOL Event) */ - u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */ - u32 drop:1; /* bit 7(Drop packet) */ - u32 ft:1; /* bit 8(Frame Truncated) */ - u32 jp:1; /* bit 9(Jumbo Packet) */ - u32 vp:1; /* bit 10(VLAN Packet) */ - u32 unused:5; /* bits 11-15 */ - u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */ - u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */ - u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */ - u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */ - u32 asw_CRC_err:1; /* bit 20(CRC error) */ - u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */ - u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */ - u32 asw_OK:1; /* bit 23(valid CRC + no code error) */ - u32 asw_multicast:1; /* bit 24(has a multicast address) */ - u32 asw_broadcast:1; /* bit 25(has a broadcast address) */ - u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */ - u32 asw_control_frame:1; /* bit 27(is a control frame) */ - u32 asw_pause_frame:1; /* bit 28(is a pause frame) */ - u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */ - u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */ - u32 asw_long_evt:1; /* bit 31(Rx long event) */ -#if 0 - u32 asw_trunc:1; /* bit 31(Rx frame truncated) */ -#endif -#endif - } bits; -} PKT_STAT_DESC_WORD0_t, *PPKT_STAT_WORD0_t; - -typedef union _PKT_STAT_DESC_WORD1_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused:4; /* bits 28-31 */ - u32 ri:2; /* bits 26-27(Ring Index) */ - u32 bi:10; /* bits 16-25(Buffer Index) */ - u32 length:16; /* bit 0-15(length in bytes) */ -#else - u32 length:16; /* bit 0-15(length in bytes) */ - u32 bi:10; /* bits 16-25(Buffer Index) */ - u32 ri:2; /* bits 26-27(Ring Index) */ - u32 unused:4; /* bits 28-31 */ -#endif - } bits; -} PKT_STAT_DESC_WORD1_t, *PPKT_STAT_WORD1_t; +/* Packet Status Ring Descriptors + * + * Word 0: + * + * top 16 bits are from the Alcatel Status Word as enumerated in + * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2) + * + * 0: hp hash pass + * 1: ipa IP checksum assist + * 2: ipp IP checksum pass + * 3: tcpa TCP checksum assist + * 4: tcpp TCP checksum pass + * 5: wol WOL Event + * 6: rxmac_error RXMAC Error Indicator + * 7: drop Drop packet + * 8: ft Frame Truncated + * 9: jp Jumbo Packet + * 10: vp VLAN Packet + * 11-15: unused + * 16: asw_prev_pkt_dropped e.g. IFG too small on previous + * 17: asw_RX_DV_event short receive event detected + * 18: asw_false_carrier_event bad carrier since last good packet + * 19: asw_code_err one or more nibbles signalled as errors + * 20: asw_CRC_err CRC error + * 21: asw_len_chk_err frame length field incorrect + * 22: asw_too_long frame length > 1518 bytes + * 23: asw_OK valid CRC + no code error + * 24: asw_multicast has a multicast address + * 25: asw_broadcast has a broadcast address + * 26: asw_dribble_nibble spurious bits after EOP + * 27: asw_control_frame is a control frame + * 28: asw_pause_frame is a pause frame + * 29: asw_unsupported_op unsupported OP code + * 30: asw_VLAN_tag VLAN tag detected + * 31: asw_long_evt Rx long event + * + * Word 1: + * 0-15: length length in bytes + * 16-25: bi Buffer Index + * 26-27: ri Ring Index + * 28-31: reserved + */ -typedef struct _PKT_STAT_DESC_t { - PKT_STAT_DESC_WORD0_t word0; - PKT_STAT_DESC_WORD1_t word1; -} PKT_STAT_DESC_t, *PPKT_STAT_DESC_t; +struct pkt_stat_desc { + u32 word0; + u32 word1; +}; /* Typedefs for the RX DMA status word */ -- cgit v1.2.3 From 8f12785dd008f4ad94e3c9aad00517e082563935 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:34:07 +0000 Subject: Staging: et131x: Kill off RX_RING_t This completes the typedef clean up of the rx specific structures, although there is plenty do on field names and the like Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_rx.c | 54 ++++++++++++++++----------------- drivers/staging/et131x/et1310_rx.h | 8 ++--- drivers/staging/et131x/et131x_adapter.h | 2 +- drivers/staging/et131x/et131x_isr.c | 2 +- 4 files changed, 33 insertions(+), 33 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c index a95e6c6705da..232ceb603391 100644 --- a/drivers/staging/et131x/et1310_rx.c +++ b/drivers/staging/et131x/et1310_rx.c @@ -109,10 +109,10 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) u32 i, j; u32 bufsize; u32 pktStatRingSize, FBRChunkSize; - RX_RING_t *rx_ring; + struct rx_ring *rx_ring; /* Setup some convenience pointers */ - rx_ring = (RX_RING_t *) &adapter->RxRing; + rx_ring = &adapter->rx_ring; /* Alloc memory for the lookup table */ #ifdef USE_FBR0 @@ -162,10 +162,10 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) } #ifdef USE_FBR0 - adapter->RxRing.PsrNumEntries = adapter->RxRing.Fbr0NumEntries + - adapter->RxRing.Fbr1NumEntries; + adapter->rx_ring.PsrNumEntries = adapter->rx_ring.Fbr0NumEntries + + adapter->rx_ring.Fbr1NumEntries; #else - adapter->RxRing.PsrNumEntries = adapter->RxRing.Fbr1NumEntries; + adapter->rx_ring.PsrNumEntries = adapter->rx_ring.Fbr1NumEntries; #endif /* Allocate an area of memory for Free Buffer Ring 1 */ @@ -338,7 +338,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) /* Allocate an area of memory for FIFO of Packet Status ring entries */ pktStatRingSize = - sizeof(struct pkt_stat_desc) * adapter->RxRing.PsrNumEntries; + sizeof(struct pkt_stat_desc) * adapter->rx_ring.PsrNumEntries; rx_ring->pPSRingVa = pci_alloc_consistent(adapter->pdev, pktStatRingSize, @@ -402,10 +402,10 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) u32 bufsize; u32 pktStatRingSize; PMP_RFD rfd; - RX_RING_t *rx_ring; + struct rx_ring *rx_ring; /* Setup some convenience pointers */ - rx_ring = (RX_RING_t *) &adapter->RxRing; + rx_ring = &adapter->rx_ring; /* Free RFDs and associated packet descriptors */ WARN_ON(rx_ring->nReadyRecv != rx_ring->NumRfd); @@ -416,7 +416,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) list_del(&rfd->list_node); rfd->Packet = NULL; - kmem_cache_free(adapter->RxRing.RecvLookaside, rfd); + kmem_cache_free(adapter->rx_ring.RecvLookaside, rfd); } /* Free Free Buffer Ring 1 */ @@ -496,7 +496,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) /* Free Packet Status Ring */ if (rx_ring->pPSRingVa) { pktStatRingSize = - sizeof(struct pkt_stat_desc) * adapter->RxRing.PsrNumEntries; + sizeof(struct pkt_stat_desc) * adapter->rx_ring.PsrNumEntries; pci_free_consistent(adapter->pdev, pktStatRingSize, rx_ring->pPSRingVa, rx_ring->pPSRingPa); @@ -545,10 +545,10 @@ int et131x_init_recv(struct et131x_adapter *adapter) PMP_RFD rfd = NULL; u32 rfdct; u32 numrfd = 0; - RX_RING_t *rx_ring = NULL; + struct rx_ring *rx_ring; /* Setup some convenience pointers */ - rx_ring = (RX_RING_t *) &adapter->RxRing; + rx_ring = &adapter->rx_ring; /* Setup each RFD */ for (rfdct = 0; rfdct < rx_ring->NumRfd; rfdct++) { @@ -592,7 +592,7 @@ int et131x_init_recv(struct et131x_adapter *adapter) void ConfigRxDmaRegs(struct et131x_adapter *etdev) { struct rxdma_regs __iomem *rx_dma = &etdev->regs->rxdma; - struct _rx_ring_t *rx_local = &etdev->RxRing; + struct rx_ring *rx_local = &etdev->rx_ring; struct fbr_desc *fbr_entry; u32 entry; u32 psr_num_des; @@ -741,19 +741,19 @@ void et131x_rx_dma_enable(struct et131x_adapter *etdev) /* Setup the receive dma configuration register for normal operation */ u32 csr = 0x2000; /* FBR1 enable */ - if (etdev->RxRing.Fbr1BufferSize == 4096) + if (etdev->rx_ring.Fbr1BufferSize == 4096) csr |= 0x0800; - else if (etdev->RxRing.Fbr1BufferSize == 8192) + else if (etdev->rx_ring.Fbr1BufferSize == 8192) csr |= 0x1000; - else if (etdev->RxRing.Fbr1BufferSize == 16384) + else if (etdev->rx_ring.Fbr1BufferSize == 16384) csr |= 0x1800; #ifdef USE_FBR0 csr |= 0x0400; /* FBR0 enable */ - if (etdev->RxRing.Fbr0BufferSize == 256) + if (etdev->rx_ring.Fbr0BufferSize == 256) csr |= 0x0100; - else if (etdev->RxRing.Fbr0BufferSize == 512) + else if (etdev->rx_ring.Fbr0BufferSize == 512) csr |= 0x0200; - else if (etdev->RxRing.Fbr0BufferSize == 1024) + else if (etdev->rx_ring.Fbr0BufferSize == 1024) csr |= 0x0300; #endif writel(csr, &etdev->regs->rxdma.csr); @@ -783,7 +783,7 @@ void et131x_rx_dma_enable(struct et131x_adapter *etdev) */ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) { - struct _rx_ring_t *rx_local = &etdev->RxRing; + struct rx_ring *rx_local = &etdev->rx_ring; struct rx_status_block *status; struct pkt_stat_desc *psr; PMP_RFD rfd; @@ -1006,7 +1006,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) */ void et131x_reset_recv(struct et131x_adapter *etdev) { - WARN_ON(list_empty(&etdev->RxRing.RecvList)); + WARN_ON(list_empty(&etdev->rx_ring.RecvList)); } @@ -1024,8 +1024,8 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev) /* Process up to available RFD's */ while (count < NUM_PACKETS_HANDLED) { - if (list_empty(&etdev->RxRing.RecvList)) { - WARN_ON(etdev->RxRing.nReadyRecv != 0); + if (list_empty(&etdev->rx_ring.RecvList)) { + WARN_ON(etdev->rx_ring.nReadyRecv != 0); done = false; break; } @@ -1050,7 +1050,7 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev) etdev->Stats.ipackets++; /* Set the status on the packet, either resources or success */ - if (etdev->RxRing.nReadyRecv < RFD_LOW_WATER_MARK) { + if (etdev->rx_ring.nReadyRecv < RFD_LOW_WATER_MARK) { dev_warn(&etdev->pdev->dev, "RFD's are running out\n"); } @@ -1058,12 +1058,12 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev) } if (count == NUM_PACKETS_HANDLED || !done) { - etdev->RxRing.UnfinishedReceives = true; + etdev->rx_ring.UnfinishedReceives = true; writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO, &etdev->regs->global.watchdog_timer); } else /* Watchdog timer will disable itself if appropriate. */ - etdev->RxRing.UnfinishedReceives = false; + etdev->rx_ring.UnfinishedReceives = false; } static inline u32 bump_fbr(u32 *fbr, u32 limit) @@ -1091,7 +1091,7 @@ static inline u32 bump_fbr(u32 *fbr, u32 limit) */ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd) { - struct _rx_ring_t *rx_local = &etdev->RxRing; + struct rx_ring *rx_local = &etdev->rx_ring; struct rxdma_regs __iomem *rx_dma = &etdev->regs->rxdma; u16 bi = rfd->bufferindex; u8 ri = rfd->ringindex; diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h index 28e7665f46d4..de5487ecedd3 100644 --- a/drivers/staging/et131x/et1310_rx.h +++ b/drivers/staging/et131x/et1310_rx.h @@ -191,10 +191,10 @@ struct fbr_lookup { }; /* - * RX_RING_t is sructure representing the adaptor's local reference(s) to the - * rings + * struct rx_ring is the ssructure representing the adaptor's local + * reference(s) to the rings */ -typedef struct _rx_ring_t { +struct rx_ring { #ifdef USE_FBR0 void *pFbr0RingVa; dma_addr_t pFbr0RingPa; @@ -239,7 +239,7 @@ typedef struct _rx_ring_t { /* lookaside lists */ struct kmem_cache *RecvLookaside; -} RX_RING_t, *PRX_RING_t; +}; /* Forward reference of RFD */ struct _MP_RFD; diff --git a/drivers/staging/et131x/et131x_adapter.h b/drivers/staging/et131x/et131x_adapter.h index 3f7f37a56b6c..e4e3185932eb 100644 --- a/drivers/staging/et131x/et131x_adapter.h +++ b/drivers/staging/et131x/et131x_adapter.h @@ -248,7 +248,7 @@ struct et131x_adapter { struct tx_ring tx_ring; /* Rx Memory Variables */ - RX_RING_t RxRing; + struct rx_ring rx_ring; /* Loopback specifics */ u8 ReplicaPhyLoopbk; /* Replica Enable */ diff --git a/drivers/staging/et131x/et131x_isr.c b/drivers/staging/et131x/et131x_isr.c index f6d452dd14e2..e297739fb868 100644 --- a/drivers/staging/et131x/et131x_isr.c +++ b/drivers/staging/et131x/et131x_isr.c @@ -185,7 +185,7 @@ irqreturn_t et131x_isr(int irq, void *dev_id) if (++tcb->stale > 1) status |= ET_INTR_TXDMA_ISR; - if (adapter->RxRing.UnfinishedReceives) + if (adapter->rx_ring.UnfinishedReceives) status |= ET_INTR_RXDMA_XFR_DONE; else if (tcb == NULL) writel(0, &adapter->regs->global.watchdog_timer); -- cgit v1.2.3 From f1471660df8e88fa7840459e3ea28ac1f3187296 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:34:13 +0000 Subject: Staging: et131x: kill MP_ERR_COUNTERS which is unused Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et131x_adapter.h | 9 --------- 1 file changed, 9 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et131x_adapter.h b/drivers/staging/et131x/et131x_adapter.h index e4e3185932eb..8b525b040cab 100644 --- a/drivers/staging/et131x/et131x_adapter.h +++ b/drivers/staging/et131x/et131x_adapter.h @@ -100,15 +100,6 @@ #define LO_MARK_PERCENT_FOR_PSR 15 #define LO_MARK_PERCENT_FOR_RX 15 -/* Counters for error rate monitoring */ -typedef struct _MP_ERR_COUNTERS { - u32 PktCountTxPackets; - u32 PktCountTxErrors; - u32 TimerBasedTxErrors; - u32 PktCountLastError; - u32 ErredConsecPackets; -} MP_ERR_COUNTERS, *PMP_ERR_COUNTERS; - /* RFD (Receive Frame Descriptor) */ typedef struct _MP_RFD { struct list_head list_node; -- cgit v1.2.3 From ec7d9f61012b9ab902810d63c4b5a7c796e4ceed Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:34:18 +0000 Subject: Staging: et131x: Kill unused error defines Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et131x_adapter.h | 18 ------------------ 1 file changed, 18 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et131x_adapter.h b/drivers/staging/et131x/et131x_adapter.h index 8b525b040cab..6f7bb2dff5a0 100644 --- a/drivers/staging/et131x/et131x_adapter.h +++ b/drivers/staging/et131x/et131x_adapter.h @@ -77,25 +77,7 @@ */ #define NUM_TRAFFIC_CLASSES 1 -/* - * There are three ways of counting errors - if there are more than X errors - * in Y packets (represented by the "SAMPLE" macros), if there are more than - * N errors in a S mSec time period (the "PERIOD" macros), or if there are - * consecutive packets with errors (CONSEC_ERRORED_THRESH). This last covers - * for "Bursty" errors, and the errored packets may well not be contiguous, - * but several errors where the packet counter has changed by less than a - * small amount will cause this count to increment. - */ -#define TX_PACKETS_IN_SAMPLE 10000 -#define TX_MAX_ERRORS_IN_SAMPLE 50 - #define TX_ERROR_PERIOD 1000 -#define TX_MAX_ERRORS_IN_PERIOD 10 - -#define LINK_DETECTION_TIMER 5000 - -#define TX_CONSEC_RANGE 5 -#define TX_CONSEC_ERRORED_THRESH 10 #define LO_MARK_PERCENT_FOR_PSR 15 #define LO_MARK_PERCENT_FOR_RX 15 -- cgit v1.2.3 From 69ea5fcb5e33b785f3f554db0ab0c2694da3f22f Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:34:24 +0000 Subject: Staging: et131x: Collapse all the function definitions into one place We have lots of tiny files right now that could be one Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_eeprom.c | 41 +++++++-- drivers/staging/et131x/et1310_eeprom.h | 103 --------------------- drivers/staging/et131x/et1310_jagcore.h | 94 -------------------- drivers/staging/et131x/et1310_mac.c | 17 ++-- drivers/staging/et131x/et1310_mac.h | 93 ------------------- drivers/staging/et131x/et1310_phy.c | 7 +- drivers/staging/et131x/et1310_phy.h | 34 ------- drivers/staging/et131x/et1310_pm.c | 6 +- drivers/staging/et131x/et1310_pm.h | 85 ------------------ drivers/staging/et131x/et1310_rx.c | 7 +- drivers/staging/et131x/et1310_rx.h | 24 ----- drivers/staging/et131x/et1310_tx.c | 8 +- drivers/staging/et131x/et1310_tx.h | 14 --- drivers/staging/et131x/et131x.h | 153 ++++++++++++++++++++++++++++++++ drivers/staging/et131x/et131x_adapter.h | 14 +++ drivers/staging/et131x/et131x_config.h | 67 -------------- drivers/staging/et131x/et131x_initpci.c | 10 +-- drivers/staging/et131x/et131x_initpci.h | 73 --------------- drivers/staging/et131x/et131x_isr.c | 24 ++++- drivers/staging/et131x/et131x_isr.h | 65 -------------- drivers/staging/et131x/et131x_netdev.c | 7 +- drivers/staging/et131x/et131x_netdev.h | 64 ------------- drivers/staging/et131x/et131x_version.h | 9 +- 23 files changed, 242 insertions(+), 777 deletions(-) delete mode 100644 drivers/staging/et131x/et1310_eeprom.h delete mode 100644 drivers/staging/et131x/et1310_jagcore.h delete mode 100644 drivers/staging/et131x/et1310_mac.h delete mode 100644 drivers/staging/et131x/et1310_pm.h create mode 100644 drivers/staging/et131x/et131x.h delete mode 100644 drivers/staging/et131x/et131x_config.h delete mode 100644 drivers/staging/et131x/et131x_initpci.h delete mode 100644 drivers/staging/et131x/et131x_isr.h delete mode 100644 drivers/staging/et131x/et131x_netdev.h (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_eeprom.c b/drivers/staging/et131x/et1310_eeprom.c index bcca1f86f516..3ca253672ba1 100644 --- a/drivers/staging/et131x/et1310_eeprom.c +++ b/drivers/staging/et131x/et1310_eeprom.c @@ -84,17 +84,42 @@ #include #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" -#include "et1310_eeprom.h" - #include "et131x_adapter.h" -#include "et131x_initpci.h" -#include "et131x_isr.h" - -#include "et1310_tx.h" +#include "et131x.h" +/* + * EEPROM Defines + */ +/* LBCIF Register Groups (addressed via 32-bit offsets) */ +#define LBCIF_DWORD0_GROUP 0xAC +#define LBCIF_DWORD1_GROUP 0xB0 + +/* LBCIF Registers (addressed via 8-bit offsets) */ +#define LBCIF_ADDRESS_REGISTER 0xAC +#define LBCIF_DATA_REGISTER 0xB0 +#define LBCIF_CONTROL_REGISTER 0xB1 +#define LBCIF_STATUS_REGISTER 0xB2 + +/* LBCIF Control Register Bits */ +#define LBCIF_CONTROL_SEQUENTIAL_READ 0x01 +#define LBCIF_CONTROL_PAGE_WRITE 0x02 +#define LBCIF_CONTROL_EEPROM_RELOAD 0x08 +#define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20 +#define LBCIF_CONTROL_I2C_WRITE 0x40 +#define LBCIF_CONTROL_LBCIF_ENABLE 0x80 + +/* LBCIF Status Register Bits */ +#define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01 +#define LBCIF_STATUS_I2C_IDLE 0x02 +#define LBCIF_STATUS_ACK_ERROR 0x04 +#define LBCIF_STATUS_GENERAL_ERROR 0x08 +#define LBCIF_STATUS_CHECKSUM_ERROR 0x40 +#define LBCIF_STATUS_EEPROM_PRESENT 0x80 + +/* Miscellaneous Constraints */ +#define MAX_NUM_REGISTER_POLLS 1000 +#define MAX_NUM_WRITE_RETRIES 2 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status) { diff --git a/drivers/staging/et131x/et1310_eeprom.h b/drivers/staging/et131x/et1310_eeprom.h deleted file mode 100644 index 6a6c6a632a8f..000000000000 --- a/drivers/staging/et131x/et1310_eeprom.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et1310_eeprom.h - Defines, structs, enums, prototypes, etc. used for EEPROM - * access routines - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef __ET1310_EEPROM_H__ -#define __ET1310_EEPROM_H__ - -#include "et1310_address_map.h" - -/* - * EEPROM Defines - */ - -/* LBCIF Register Groups (addressed via 32-bit offsets) */ -#define LBCIF_DWORD0_GROUP 0xAC -#define LBCIF_DWORD1_GROUP 0xB0 - -/* LBCIF Registers (addressed via 8-bit offsets) */ -#define LBCIF_ADDRESS_REGISTER 0xAC -#define LBCIF_DATA_REGISTER 0xB0 -#define LBCIF_CONTROL_REGISTER 0xB1 -#define LBCIF_STATUS_REGISTER 0xB2 - -/* LBCIF Control Register Bits */ -#define LBCIF_CONTROL_SEQUENTIAL_READ 0x01 -#define LBCIF_CONTROL_PAGE_WRITE 0x02 -#define LBCIF_CONTROL_EEPROM_RELOAD 0x08 -#define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20 -#define LBCIF_CONTROL_I2C_WRITE 0x40 -#define LBCIF_CONTROL_LBCIF_ENABLE 0x80 - -/* LBCIF Status Register Bits */ -#define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01 -#define LBCIF_STATUS_I2C_IDLE 0x02 -#define LBCIF_STATUS_ACK_ERROR 0x04 -#define LBCIF_STATUS_GENERAL_ERROR 0x08 -#define LBCIF_STATUS_CHECKSUM_ERROR 0x40 -#define LBCIF_STATUS_EEPROM_PRESENT 0x80 - -/* Miscellaneous Constraints */ -#define MAX_NUM_REGISTER_POLLS 1000 -#define MAX_NUM_WRITE_RETRIES 2 - -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; - -int et131x_init_eeprom(struct et131x_adapter *etdev); - -#endif /* _ET1310_EEPROM_H_ */ diff --git a/drivers/staging/et131x/et1310_jagcore.h b/drivers/staging/et131x/et1310_jagcore.h deleted file mode 100644 index 0807a01d88ae..000000000000 --- a/drivers/staging/et131x/et1310_jagcore.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et1310_jagcore.h - Defines, structs, enums, prototypes, etc. pertaining to - * the JAGCore - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef __ET1310_JAGCORE_H__ -#define __ET1310_JAGCORE_H__ - -#include "et1310_address_map.h" - - -#define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */ -#define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */ - -/* - * For interrupts, normal running is: - * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt, - * watchdog_interrupt & txdma_xfer_done - * - * In both cases, when flow control is enabled for either Tx or bi-direction, - * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the - * buffer rings are running low. - */ -#define INT_MASK_DISABLE 0xffffffff - -/* NOTE: Masking out MAC_STAT Interrupt for now... - * #define INT_MASK_ENABLE 0xfff6bf17 - * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7 - */ -#define INT_MASK_ENABLE 0xfffebf17 -#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7 - -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; - -void ConfigGlobalRegs(struct et131x_adapter *pAdapter); -void ConfigMMCRegs(struct et131x_adapter *pAdapter); -void et131x_enable_interrupts(struct et131x_adapter *adapter); -void et131x_disable_interrupts(struct et131x_adapter *adapter); - -#endif /* __ET1310_JAGCORE_H__ */ diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c index a02bce0c2807..6515f50a95d8 100644 --- a/drivers/staging/et131x/et1310_mac.c +++ b/drivers/staging/et131x/et1310_mac.c @@ -85,12 +85,19 @@ #include #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" -#include "et1310_mac.h" - #include "et131x_adapter.h" -#include "et131x_initpci.h" +#include "et131x.h" + + +#define COUNTER_WRAP_28_BIT 0x10000000 +#define COUNTER_WRAP_22_BIT 0x400000 +#define COUNTER_WRAP_16_BIT 0x10000 +#define COUNTER_WRAP_12_BIT 0x1000 + +#define COUNTER_MASK_28_BIT (COUNTER_WRAP_28_BIT - 1) +#define COUNTER_MASK_22_BIT (COUNTER_WRAP_22_BIT - 1) +#define COUNTER_MASK_16_BIT (COUNTER_WRAP_16_BIT - 1) +#define COUNTER_MASK_12_BIT (COUNTER_WRAP_12_BIT - 1) /** * ConfigMacRegs1 - Initialize the first part of MAC regs diff --git a/drivers/staging/et131x/et1310_mac.h b/drivers/staging/et131x/et1310_mac.h deleted file mode 100644 index 2c3859594538..000000000000 --- a/drivers/staging/et131x/et1310_mac.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et1310_mac.h - Defines, structs, enums, prototypes, etc. pertaining to the - * MAC. - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef _ET1310_MAC_H_ -#define _ET1310_MAC_H_ - - -#include "et1310_address_map.h" - - -#define COUNTER_WRAP_28_BIT 0x10000000 -#define COUNTER_WRAP_22_BIT 0x400000 -#define COUNTER_WRAP_16_BIT 0x10000 -#define COUNTER_WRAP_12_BIT 0x1000 - -#define COUNTER_MASK_28_BIT (COUNTER_WRAP_28_BIT - 1) -#define COUNTER_MASK_22_BIT (COUNTER_WRAP_22_BIT - 1) -#define COUNTER_MASK_16_BIT (COUNTER_WRAP_16_BIT - 1) -#define COUNTER_MASK_12_BIT (COUNTER_WRAP_12_BIT - 1) - -#define UPDATE_COUNTER(HostCnt, DevCnt) \ - HostCnt = HostCnt + DevCnt; - -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; - -void ConfigMACRegs1(struct et131x_adapter *adapter); -void ConfigMACRegs2(struct et131x_adapter *adapter); -void ConfigRxMacRegs(struct et131x_adapter *adapter); -void ConfigTxMacRegs(struct et131x_adapter *adapter); -void ConfigMacStatRegs(struct et131x_adapter *adapter); -void ConfigFlowControl(struct et131x_adapter *adapter); -void UpdateMacStatHostCounters(struct et131x_adapter *adapter); -void HandleMacStatInterrupt(struct et131x_adapter *adapter); -void SetupDeviceForMulticast(struct et131x_adapter *adapter); -void SetupDeviceForUnicast(struct et131x_adapter *adapter); - -#endif /* _ET1310_MAC_H_ */ diff --git a/drivers/staging/et131x/et1310_phy.c b/drivers/staging/et131x/et1310_phy.c index 6ecad619f779..4a55fbfbd59d 100644 --- a/drivers/staging/et131x/et1310_phy.c +++ b/drivers/staging/et131x/et1310_phy.c @@ -85,17 +85,14 @@ #include #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" #include "et131x_adapter.h" -#include "et131x_netdev.h" -#include "et131x_initpci.h" #include "et1310_address_map.h" #include "et1310_tx.h" #include "et1310_rx.h" -#include "et1310_mac.h" + +#include "et131x.h" /* Prototypes for functions with local scope */ static void et131x_xcvr_init(struct et131x_adapter *etdev); diff --git a/drivers/staging/et131x/et1310_phy.h b/drivers/staging/et131x/et1310_phy.h index 758b9b251715..47907ba76012 100644 --- a/drivers/staging/et131x/et1310_phy.h +++ b/drivers/staging/et131x/et1310_phy.h @@ -736,32 +736,8 @@ typedef union _MI_LCR2_t { /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */ -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; /* Prototypes for ET1310_phy.c */ -int et131x_xcvr_find(struct et131x_adapter *adapter); -void et131x_setphy_normal(struct et131x_adapter *adapter); - -/* static inline function does not work because et131x_adapter is not always - * defined - */ -int PhyMiRead(struct et131x_adapter *adapter, u8 xcvrAddr, - u8 xcvrReg, u16 *value); -#define MiRead(adapter, xcvrReg, value) \ - PhyMiRead((adapter), (adapter)->Stats.xcvr_addr, (xcvrReg), (value)) - -int32_t MiWrite(struct et131x_adapter *adapter, - u8 xcvReg, u16 value); -void et131x_Mii_check(struct et131x_adapter *pAdapter, - MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints); - -/* This last is not strictly required (the driver could call the TPAL - * version instead), but this sets the adapter up correctly, and calls the - * access routine indirectly. This protects the driver from changes in TPAL. - */ -void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter); - /* Defines for PHY access routines */ /* Define bit operation flags */ @@ -843,14 +819,4 @@ void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter); /* #define TRU_VMI_LINK_CONTROL_REGISTER 29 */ /* #define TRU_VMI_TIMING_CONTROL_REGISTER */ -/* Prototypes for PHY access routines */ -void ET1310_PhyInit(struct et131x_adapter *adapter); -void ET1310_PhyReset(struct et131x_adapter *adapter); -void ET1310_PhyPowerDown(struct et131x_adapter *adapter, bool down); -void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *adapter, - u16 duplex); -void ET1310_PhyAccessMiBit(struct et131x_adapter *adapter, - u16 action, - u16 regnum, u16 bitnum, u8 *value); - #endif /* _ET1310_PHY_H_ */ diff --git a/drivers/staging/et131x/et1310_pm.c b/drivers/staging/et131x/et1310_pm.c index 7d0772359291..41019e390af5 100644 --- a/drivers/staging/et131x/et1310_pm.c +++ b/drivers/staging/et131x/et1310_pm.c @@ -83,13 +83,9 @@ #include #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" -#include "et1310_mac.h" #include "et1310_rx.h" - #include "et131x_adapter.h" -#include "et131x_initpci.h" +#include "et131x.h" /** * EnablePhyComa - called when network cable is unplugged diff --git a/drivers/staging/et131x/et1310_pm.h b/drivers/staging/et131x/et1310_pm.h deleted file mode 100644 index 295f3ab132fb..000000000000 --- a/drivers/staging/et131x/et1310_pm.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et1310_pm.h - Defines, structs, enums, prototypes, etc. pertaining to power - * management. - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef _ET1310_PM_H_ -#define _ET1310_PM_H_ - -#include "et1310_address_map.h" - -typedef struct _MP_POWER_MGMT { - /* variable putting the phy into coma mode when boot up with no cable - * plugged in after 5 seconds - */ - u8 TransPhyComaModeOnBoot; - - /* Next two used to save power information at power down. This - * information will be used during power up to set up parts of Power - * Management in JAGCore - */ - u16 PowerDownSpeed; - u8 PowerDownDuplex; -} MP_POWER_MGMT, *PMP_POWER_MGMT; - -/* Forward declaration of the private adapter structure - */ -struct et131x_adapter; - -void EnablePhyComa(struct et131x_adapter *adapter); -void DisablePhyComa(struct et131x_adapter *adapter); - -#endif /* _ET1310_PM_H_ */ diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c index 232ceb603391..54686e2ace69 100644 --- a/drivers/staging/et131x/et1310_rx.c +++ b/drivers/staging/et131x/et1310_rx.c @@ -84,14 +84,9 @@ #include #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" - #include "et131x_adapter.h" -#include "et131x_initpci.h" - #include "et1310_rx.h" - +#include "et131x.h" void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd); diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h index de5487ecedd3..ca84a9146d69 100644 --- a/drivers/staging/et131x/et1310_rx.h +++ b/drivers/staging/et131x/et1310_rx.h @@ -241,28 +241,4 @@ struct rx_ring { struct kmem_cache *RecvLookaside; }; -/* Forward reference of RFD */ -struct _MP_RFD; - -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; - -/* PROTOTYPES for Initialization */ -int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter); -void et131x_rx_dma_memory_free(struct et131x_adapter *adapter); -int et131x_rfd_resources_alloc(struct et131x_adapter *adapter, - struct _MP_RFD *pMpRfd); -void et131x_rfd_resources_free(struct et131x_adapter *adapter, - struct _MP_RFD *pMpRfd); -int et131x_init_recv(struct et131x_adapter *adapter); - -void ConfigRxDmaRegs(struct et131x_adapter *adapter); -void SetRxDmaTimer(struct et131x_adapter *adapter); -void et131x_rx_dma_disable(struct et131x_adapter *adapter); -void et131x_rx_dma_enable(struct et131x_adapter *adapter); - -void et131x_reset_recv(struct et131x_adapter *adapter); - -void et131x_handle_recv_interrupt(struct et131x_adapter *adapter); - #endif /* __ET1310_RX_H__ */ diff --git a/drivers/staging/et131x/et1310_tx.c b/drivers/staging/et131x/et1310_tx.c index b0cb0579026e..b6ff20f47de4 100644 --- a/drivers/staging/et131x/et1310_tx.c +++ b/drivers/staging/et131x/et1310_tx.c @@ -84,15 +84,9 @@ #include #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" - #include "et131x_adapter.h" -#include "et131x_initpci.h" -#include "et131x_isr.h" - #include "et1310_tx.h" - +#include "et131x.h" static inline void et131x_free_send_packet(struct et131x_adapter *etdev, struct tcb *tcb); diff --git a/drivers/staging/et131x/et1310_tx.h b/drivers/staging/et131x/et1310_tx.h index 4f0ea81978f5..82d06e9870de 100644 --- a/drivers/staging/et131x/et1310_tx.h +++ b/drivers/staging/et131x/et1310_tx.h @@ -147,18 +147,4 @@ struct tx_ring { int since_irq; }; -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; - -/* PROTOTYPES for et1310_tx.c */ -int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter); -void et131x_tx_dma_memory_free(struct et131x_adapter *adapter); -void ConfigTxDmaRegs(struct et131x_adapter *adapter); -void et131x_init_send(struct et131x_adapter *adapter); -void et131x_tx_dma_disable(struct et131x_adapter *adapter); -void et131x_tx_dma_enable(struct et131x_adapter *adapter); -void et131x_handle_send_interrupt(struct et131x_adapter *adapter); -void et131x_free_busy_send_packets(struct et131x_adapter *adapter); -int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev); - #endif /* __ET1310_TX_H__ */ diff --git a/drivers/staging/et131x/et131x.h b/drivers/staging/et131x/et131x.h new file mode 100644 index 000000000000..a8abfe6ca81f --- /dev/null +++ b/drivers/staging/et131x/et131x.h @@ -0,0 +1,153 @@ +/* + * Merged from files + * + * Copyright © 2005 Agere Systems Inc. + * All rights reserved. + * http://www.agere.com + * + * SOFTWARE LICENSE + * + * This software is provided subject to the following terms and conditions, + * which you should read carefully before using the software. Using this + * software indicates your acceptance of these terms and conditions. If you do + * not agree with these terms and conditions, do not use the software. + * + * Copyright © 2005 Agere Systems Inc. + * All rights reserved. + * + * Redistribution and use in source or binary forms, with or without + * modifications, are permitted provided that the following conditions are met: + * + * . Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following Disclaimer as comments in the code as + * well as in the documentation and/or other materials provided with the + * distribution. + * + * . Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following Disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * . Neither the name of Agere Systems Inc. nor the names of the contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * Disclaimer + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * + */ + +/* et131x_eeprom.c */ +int et131x_init_eeprom(struct et131x_adapter *etdev); + +/* et131x_initpci.c */ +void ConfigGlobalRegs(struct et131x_adapter *pAdapter); +void ConfigMMCRegs(struct et131x_adapter *pAdapter); +void et131x_enable_interrupts(struct et131x_adapter *adapter); +void et131x_disable_interrupts(struct et131x_adapter *adapter); +void et131x_align_allocated_memory(struct et131x_adapter *adapter, + u64 *phys_addr, + u64 *offset, u64 mask); + +int et131x_adapter_setup(struct et131x_adapter *adapter); +int et131x_adapter_memory_alloc(struct et131x_adapter *adapter); +void et131x_adapter_memory_free(struct et131x_adapter *adapter); +void et131x_hwaddr_init(struct et131x_adapter *adapter); +void et131x_soft_reset(struct et131x_adapter *adapter); + +/* et131x_isr.c */ +irqreturn_t et131x_isr(int irq, void *dev_id); +void et131x_isr_handler(struct work_struct *work); + +/* et1310_mac.c */ +void ConfigMACRegs1(struct et131x_adapter *adapter); +void ConfigMACRegs2(struct et131x_adapter *adapter); +void ConfigRxMacRegs(struct et131x_adapter *adapter); +void ConfigTxMacRegs(struct et131x_adapter *adapter); +void ConfigMacStatRegs(struct et131x_adapter *adapter); +void ConfigFlowControl(struct et131x_adapter *adapter); +void UpdateMacStatHostCounters(struct et131x_adapter *adapter); +void HandleMacStatInterrupt(struct et131x_adapter *adapter); +void SetupDeviceForMulticast(struct et131x_adapter *adapter); +void SetupDeviceForUnicast(struct et131x_adapter *adapter); + +/* et131x_netdev.c */ +struct net_device *et131x_device_alloc(void); + +/* et131x_pm.c */ +void EnablePhyComa(struct et131x_adapter *adapter); +void DisablePhyComa(struct et131x_adapter *adapter); + +/* et131x_phy.c */ +void ET1310_PhyInit(struct et131x_adapter *adapter); +void ET1310_PhyReset(struct et131x_adapter *adapter); +void ET1310_PhyPowerDown(struct et131x_adapter *adapter, bool down); +void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *adapter, + u16 duplex); +void ET1310_PhyAccessMiBit(struct et131x_adapter *adapter, + u16 action, + u16 regnum, u16 bitnum, u8 *value); + +int et131x_xcvr_find(struct et131x_adapter *adapter); +void et131x_setphy_normal(struct et131x_adapter *adapter); + +/* static inline function does not work because et131x_adapter is not always + * defined + */ +int PhyMiRead(struct et131x_adapter *adapter, u8 xcvrAddr, + u8 xcvrReg, u16 *value); +#define MiRead(adapter, xcvrReg, value) \ + PhyMiRead((adapter), (adapter)->Stats.xcvr_addr, (xcvrReg), (value)) + +int32_t MiWrite(struct et131x_adapter *adapter, + u8 xcvReg, u16 value); +void et131x_Mii_check(struct et131x_adapter *pAdapter, + MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints); + +/* This last is not strictly required (the driver could call the TPAL + * version instead), but this sets the adapter up correctly, and calls the + * access routine indirectly. This protects the driver from changes in TPAL. + */ +void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter); + + +/* et1310_rx.c */ +int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter); +void et131x_rx_dma_memory_free(struct et131x_adapter *adapter); +int et131x_rfd_resources_alloc(struct et131x_adapter *adapter, + struct _MP_RFD *pMpRfd); +void et131x_rfd_resources_free(struct et131x_adapter *adapter, + struct _MP_RFD *pMpRfd); +int et131x_init_recv(struct et131x_adapter *adapter); + +void ConfigRxDmaRegs(struct et131x_adapter *adapter); +void SetRxDmaTimer(struct et131x_adapter *adapter); +void et131x_rx_dma_disable(struct et131x_adapter *adapter); +void et131x_rx_dma_enable(struct et131x_adapter *adapter); + +void et131x_reset_recv(struct et131x_adapter *adapter); + +void et131x_handle_recv_interrupt(struct et131x_adapter *adapter); + +/* et131x_tx.c */ +int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter); +void et131x_tx_dma_memory_free(struct et131x_adapter *adapter); +void ConfigTxDmaRegs(struct et131x_adapter *adapter); +void et131x_init_send(struct et131x_adapter *adapter); +void et131x_tx_dma_disable(struct et131x_adapter *adapter); +void et131x_tx_dma_enable(struct et131x_adapter *adapter); +void et131x_handle_send_interrupt(struct et131x_adapter *adapter); +void et131x_free_busy_send_packets(struct et131x_adapter *adapter); +int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev); + diff --git a/drivers/staging/et131x/et131x_adapter.h b/drivers/staging/et131x/et131x_adapter.h index 6f7bb2dff5a0..64a678fcb60a 100644 --- a/drivers/staging/et131x/et131x_adapter.h +++ b/drivers/staging/et131x/et131x_adapter.h @@ -147,6 +147,20 @@ typedef struct _ce_stats_t { u32 InterruptStatus; } CE_STATS_t, *PCE_STATS_t; +typedef struct _MP_POWER_MGMT { + /* variable putting the phy into coma mode when boot up with no cable + * plugged in after 5 seconds + */ + u8 TransPhyComaModeOnBoot; + + /* Next two used to save power information at power down. This + * information will be used during power up to set up parts of Power + * Management in JAGCore + */ + u16 PowerDownSpeed; + u8 PowerDownDuplex; +} MP_POWER_MGMT, *PMP_POWER_MGMT; + /* The private adapter structure */ struct et131x_adapter { struct net_device *netdev; diff --git a/drivers/staging/et131x/et131x_config.h b/drivers/staging/et131x/et131x_config.h deleted file mode 100644 index 642c0f6dd6f3..000000000000 --- a/drivers/staging/et131x/et131x_config.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et131x_config.h - Defines, structs, enums, prototypes, etc. to support - * et131x_config.c - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef __ET131X_CONFIG_H__ -#define __ET131X_CONFIG_H__ - -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; - -void et131x_config_parse(struct et131x_adapter *adapter); - -#endif /* __ET131X_CONFIG_H__ */ diff --git a/drivers/staging/et131x/et131x_initpci.c b/drivers/staging/et131x/et131x_initpci.c index e02b1cd98f55..5ad7e5a6f631 100644 --- a/drivers/staging/et131x/et131x_initpci.c +++ b/drivers/staging/et131x/et131x_initpci.c @@ -87,20 +87,16 @@ #include #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" #include "et131x_adapter.h" -#include "et131x_netdev.h" -#include "et131x_config.h" -#include "et131x_isr.h" #include "et1310_address_map.h" #include "et1310_tx.h" #include "et1310_rx.h" -#include "et1310_mac.h" -#include "et1310_eeprom.h" +#include "et131x.h" +#define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */ +#define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */ /* Defines for Parameter Default/Min/Max vaules */ #define PARM_SPEED_DUPLEX_MIN 0 diff --git a/drivers/staging/et131x/et131x_initpci.h b/drivers/staging/et131x/et131x_initpci.h deleted file mode 100644 index 7269569a874b..000000000000 --- a/drivers/staging/et131x/et131x_initpci.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et131x_initpci.h - Header which includes common data and function prototypes - * related to the driver's PCI (and PCI Express) information. - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef __ET131X_INITPCI_H__ -#define __ET131X_INITPCI_H__ - -/* Function Prototypes */ -void et131x_align_allocated_memory(struct et131x_adapter *adapter, - u64 *phys_addr, - u64 *offset, u64 mask); - -int et131x_adapter_setup(struct et131x_adapter *adapter); -int et131x_adapter_memory_alloc(struct et131x_adapter *adapter); -void et131x_adapter_memory_free(struct et131x_adapter *adapter); -void et131x_hwaddr_init(struct et131x_adapter *adapter); -void et131x_soft_reset(struct et131x_adapter *adapter); - -#endif /* __ET131X_INITPCI_H__ */ diff --git a/drivers/staging/et131x/et131x_isr.c b/drivers/staging/et131x/et131x_isr.c index e297739fb868..c35a564de3c8 100644 --- a/drivers/staging/et131x/et131x_isr.c +++ b/drivers/staging/et131x/et131x_isr.c @@ -85,11 +85,27 @@ #include #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" -#include "et1310_mac.h" - #include "et131x_adapter.h" +#include "et131x.h" + +/* + * For interrupts, normal running is: + * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt, + * watchdog_interrupt & txdma_xfer_done + * + * In both cases, when flow control is enabled for either Tx or bi-direction, + * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the + * buffer rings are running low. + */ +#define INT_MASK_DISABLE 0xffffffff + +/* NOTE: Masking out MAC_STAT Interrupt for now... + * #define INT_MASK_ENABLE 0xfff6bf17 + * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7 + */ +#define INT_MASK_ENABLE 0xfffebf17 +#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7 + /** * et131x_enable_interrupts - enable interrupt diff --git a/drivers/staging/et131x/et131x_isr.h b/drivers/staging/et131x/et131x_isr.h deleted file mode 100644 index 906d57727e20..000000000000 --- a/drivers/staging/et131x/et131x_isr.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et131x_isr.h - Defines, structs, enums, prototypes, etc. pertaining to the - * ISR processing code. - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef __ET131X_ISR_H__ -#define __ET131X_ISR_H__ - -irqreturn_t et131x_isr(int irq, void *dev_id); -void et131x_isr_handler(struct work_struct *work); - -#endif /* __ET131X_ISR_H__ */ diff --git a/drivers/staging/et131x/et131x_netdev.c b/drivers/staging/et131x/et131x_netdev.c index c63032fa88c5..6d9f9be7a844 100644 --- a/drivers/staging/et131x/et131x_netdev.c +++ b/drivers/staging/et131x/et131x_netdev.c @@ -85,14 +85,9 @@ #include #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" -#include "et1310_mac.h" #include "et1310_tx.h" - #include "et131x_adapter.h" -#include "et131x_isr.h" -#include "et131x_initpci.h" +#include "et131x.h" struct net_device_stats *et131x_stats(struct net_device *netdev); int et131x_open(struct net_device *netdev); diff --git a/drivers/staging/et131x/et131x_netdev.h b/drivers/staging/et131x/et131x_netdev.h deleted file mode 100644 index 1eb4a922c01d..000000000000 --- a/drivers/staging/et131x/et131x_netdev.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et131x_netdev.h - Defines, structs, enums, prototypes, etc. related to the - * driver's net_device support. - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef __ET131X_NETDEV_H__ -#define __ET131X_NETDEV_H__ - -struct net_device *et131x_device_alloc(void); - -#endif /* __ET131X_NETDEV_H__ */ diff --git a/drivers/staging/et131x/et131x_version.h b/drivers/staging/et131x/et131x_version.h index 568f6c8c34f5..2aa9bda44ac0 100644 --- a/drivers/staging/et131x/et131x_version.h +++ b/drivers/staging/et131x/et131x_version.h @@ -62,20 +62,13 @@ #define DRIVER_LICENSE "Dual BSD/GPL" #define DRIVER_DEVICE_STRING "ET1310" #define DRIVER_NAME "et131x" -#define DRIVER_MAJOR_VERSION 1 -#define DRIVER_MINOR_VERSION 2 -#define DRIVER_PATCH_VERSION 3 -#define DRIVER_VERSION_STRING "1.2.3" +#define DRIVER_VERSION_STRING "1.2.3-lk" #define DRIVER_VENDOR "Agere Systems, http://www.agere.com" #define DRIVER_DESC "10/100/1000 Base-T Ethernet Driver" -#define STRUCT_MODULE "net" /* blux: missed by the kernel */ - #define DRIVER_INFO DRIVER_DESC " for the "\ DRIVER_DEVICE_STRING ", v" \ DRIVER_VERSION_STRING " by " \ DRIVER_VENDOR -#define DRIVER_NAME_EXT "et131x.ko" - #endif /* __ET131X_VERSION_H__ */ -- cgit v1.2.3 From 6720949d55623cb8c4cb6b06f218d8be68780a6f Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:34:29 +0000 Subject: Staging: et131x: Kil the txmac type Only used for one trivial thing so turn that into something trivial instead Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 39 +++++++++-------------------- drivers/staging/et131x/et1310_mac.c | 9 +++---- 2 files changed, 16 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index 11e7b656d45c..5fcb48334590 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -538,33 +538,18 @@ struct rxdma_regs { /* Location: */ /* * structure for control reg in txmac address map * located at address 0x3000 + * + * bits + * 31-8: unused + * 7: cklseg_disable + * 6: ckbcnt_disable + * 5: cksegnum + * 4: async_disable + * 3: fc_disable + * 2: mcif_disable + * 1: mif_disable + * 0: txmac_en */ -typedef union _TXMAC_CTL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused:24; /* bits 8-31 */ - u32 cklseg_diable:1; /* bit 7 */ - u32 ckbcnt_disable:1; /* bit 6 */ - u32 cksegnum:1; /* bit 5 */ - u32 async_disable:1; /* bit 4 */ - u32 fc_disable:1; /* bit 3 */ - u32 mcif_disable:1; /* bit 2 */ - u32 mif_disable:1; /* bit 1 */ - u32 txmac_en:1; /* bit 0 */ -#else - u32 txmac_en:1; /* bit 0 */ - u32 mif_disable:1; /* bit 1 mac interface */ - u32 mcif_disable:1; /* bit 2 mem. contr. interface */ - u32 fc_disable:1; /* bit 3 */ - u32 async_disable:1; /* bit 4 */ - u32 cksegnum:1; /* bit 5 */ - u32 ckbcnt_disable:1; /* bit 6 */ - u32 cklseg_diable:1; /* bit 7 */ - u32 unused:24; /* bits 8-31 */ -#endif - } bits; -} TXMAC_CTL_t, *PTXMAC_CTL_t; /* * structure for shadow pointer reg in txmac address map @@ -695,7 +680,7 @@ typedef union _TXMAC_ERR_INT_t { * Tx MAC Module of JAGCore Address Mapping */ typedef struct _TXMAC_t { /* Location: */ - TXMAC_CTL_t ctl; /* 0x3000 */ + u32 ctl; /* 0x3000 */ u32 shadow_ptr; /* 0x3004 */ TXMAC_ERR_CNT_t err_cnt; /* 0x3008 */ u32 max_fill; /* 0x300C */ diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c index 6515f50a95d8..dc9cb297a848 100644 --- a/drivers/staging/et131x/et1310_mac.c +++ b/drivers/staging/et131x/et1310_mac.c @@ -170,9 +170,9 @@ void ConfigMACRegs2(struct et131x_adapter *etdev) u32 cfg1; u32 cfg2; u32 ifctrl; - TXMAC_CTL_t ctl; + u32 ctl; - ctl.value = readl(&etdev->regs->txmac.ctl.value); + ctl = readl(&etdev->regs->txmac.ctl); cfg1 = readl(&pMac->cfg1); cfg2 = readl(&pMac->cfg2); ifctrl = readl(&pMac->if_ctrl); @@ -226,9 +226,8 @@ void ConfigMACRegs2(struct et131x_adapter *etdev) } /* Enable TXMAC */ - ctl.bits.txmac_en = 0x1; - ctl.bits.fc_disable = 0x1; - writel(ctl.value, &etdev->regs->txmac.ctl.value); + ctl |= 0x05; /* TX mac enable, FC disable */ + writel(ctl, &etdev->regs->txmac.ctl); /* Ready to start the RXDMA/TXDMA engine */ if (etdev->Flags & fMP_ADAPTER_LOWER_POWER) { -- cgit v1.2.3 From 1cb180dc9dadf7739fe5bf9a8f159097abb67590 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:34:35 +0000 Subject: Staging: et131x: kill txmac err count typedef Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index 5fcb48334590..c8b22ba120fc 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -563,23 +563,12 @@ struct rxdma_regs { /* Location: */ /* * structure for error count reg in txmac address map * located at address 0x3008 + * + * 31-12: unused + * 11-8: reserved + * 7-4: txq_underrun + * 3-0: fifo_underrun */ -typedef union _TXMAC_ERR_CNT_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused:20; /* bits 12-31 */ - u32 reserved:4; /* bits 8-11 */ - u32 txq_underrun:4; /* bits 4-7 */ - u32 fifo_underrun:4; /* bits 0-3 */ -#else - u32 fifo_underrun:4; /* bits 0-3 */ - u32 txq_underrun:4; /* bits 4-7 */ - u32 reserved:4; /* bits 8-11 */ - u32 unused:20; /* bits 12-31 */ -#endif - } bits; -} TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t; /* * structure for max fill reg in txmac address map @@ -682,7 +671,7 @@ typedef union _TXMAC_ERR_INT_t { typedef struct _TXMAC_t { /* Location: */ u32 ctl; /* 0x3000 */ u32 shadow_ptr; /* 0x3004 */ - TXMAC_ERR_CNT_t err_cnt; /* 0x3008 */ + u32 err_cnt; /* 0x3008 */ u32 max_fill; /* 0x300C */ u32 cf_param; /* 0x3010 */ u32 tx_test; /* 0x3014 */ -- cgit v1.2.3 From 003e52e85b1cf04c0bccc70c124d67aea3036fda Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:34:40 +0000 Subject: Staging: et131x: Kill off the TXMAC_ERR_t type This is another one we don't really need to do much to get rid of Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 38 +++++++++-------------------- drivers/staging/et131x/et131x_isr.c | 2 +- 2 files changed, 12 insertions(+), 28 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index c8b22ba120fc..4c1e73574ecd 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -597,33 +597,17 @@ struct rxdma_regs { /* Location: */ /* * structure for error reg in txmac address map * located at address 0x3018 + * + * 31-9: unused + * 8: fifo_underrun + * 7-6: unused + * 5: ctrl2_err + * 4: txq_underrun + * 3: bcnt_err + * 2: lseg_err + * 1: segnum_err + * 0: seg0_err */ -typedef union _TXMAC_ERR_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused2:23; /* bits 9-31 */ - u32 fifo_underrun:1; /* bit 8 */ - u32 unused1:2; /* bits 6-7 */ - u32 ctrl2_err:1; /* bit 5 */ - u32 txq_underrun:1; /* bit 4 */ - u32 bcnt_err:1; /* bit 3 */ - u32 lseg_err:1; /* bit 2 */ - u32 segnum_err:1; /* bit 1 */ - u32 seg0_err:1; /* bit 0 */ -#else - u32 seg0_err:1; /* bit 0 */ - u32 segnum_err:1; /* bit 1 */ - u32 lseg_err:1; /* bit 2 */ - u32 bcnt_err:1; /* bit 3 */ - u32 txq_underrun:1; /* bit 4 */ - u32 ctrl2_err:1; /* bit 5 */ - u32 unused1:2; /* bits 6-7 */ - u32 fifo_underrun:1; /* bit 8 */ - u32 unused2:23; /* bits 9-31 */ -#endif - } bits; -} TXMAC_ERR_t, *PTXMAC_ERR_t; /* * structure for error interrupt reg in txmac address map @@ -675,7 +659,7 @@ typedef struct _TXMAC_t { /* Location: */ u32 max_fill; /* 0x300C */ u32 cf_param; /* 0x3010 */ u32 tx_test; /* 0x3014 */ - TXMAC_ERR_t err; /* 0x3018 */ + u32 err; /* 0x3018 */ TXMAC_ERR_INT_t err_int; /* 0x301C */ u32 bp_ctrl; /* 0x3020 */ } TXMAC_t, *PTXMAC_t; diff --git a/drivers/staging/et131x/et131x_isr.c b/drivers/staging/et131x/et131x_isr.c index c35a564de3c8..aa36e40ec248 100644 --- a/drivers/staging/et131x/et131x_isr.c +++ b/drivers/staging/et131x/et131x_isr.c @@ -406,7 +406,7 @@ void et131x_isr_handler(struct work_struct *work) /* Let's move on to the TxMac */ if (status & ET_INTR_TXMAC) { - u32 err = readl(&iomem->txmac.err.value); + u32 err = readl(&iomem->txmac.err); /* * When any of the errors occur and TXMAC generates -- cgit v1.2.3 From afa7e5ec93b4e9e991fd3feb0bda2589f785e357 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:34:46 +0000 Subject: Staging: et13x: kill off TXMAC_ERR_INT_t This completes the structures within the txmac block so we can now propogate a name change and type removal up a layer and clean up TXMAC as well Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 48 ++++++++++------------------- drivers/staging/et131x/et1310_mac.c | 6 ++-- 2 files changed, 19 insertions(+), 35 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index 4c1e73574ecd..d599f312963e 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -612,33 +612,17 @@ struct rxdma_regs { /* Location: */ /* * structure for error interrupt reg in txmac address map * located at address 0x301C + * + * 31-9: unused + * 8: fifo_underrun + * 7-6: unused + * 5: ctrl2_err + * 4: txq_underrun + * 3: bcnt_err + * 2: lseg_err + * 1: segnum_err + * 0: seg0_err */ -typedef union _TXMAC_ERR_INT_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused2:23; /* bits 9-31 */ - u32 fifo_underrun:1; /* bit 8 */ - u32 unused1:2; /* bits 6-7 */ - u32 ctrl2_err:1; /* bit 5 */ - u32 txq_underrun:1; /* bit 4 */ - u32 bcnt_err:1; /* bit 3 */ - u32 lseg_err:1; /* bit 2 */ - u32 segnum_err:1; /* bit 1 */ - u32 seg0_err:1; /* bit 0 */ -#else - u32 seg0_err:1; /* bit 0 */ - u32 segnum_err:1; /* bit 1 */ - u32 lseg_err:1; /* bit 2 */ - u32 bcnt_err:1; /* bit 3 */ - u32 txq_underrun:1; /* bit 4 */ - u32 ctrl2_err:1; /* bit 5 */ - u32 unused1:2; /* bits 6-7 */ - u32 fifo_underrun:1; /* bit 8 */ - u32 unused2:23; /* bits 9-31 */ -#endif - } bits; -} TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t; /* * structure for error interrupt reg in txmac address map @@ -652,7 +636,7 @@ typedef union _TXMAC_ERR_INT_t { /* * Tx MAC Module of JAGCore Address Mapping */ -typedef struct _TXMAC_t { /* Location: */ +struct txmac_regs { /* Location: */ u32 ctl; /* 0x3000 */ u32 shadow_ptr; /* 0x3004 */ u32 err_cnt; /* 0x3008 */ @@ -660,9 +644,9 @@ typedef struct _TXMAC_t { /* Location: */ u32 cf_param; /* 0x3010 */ u32 tx_test; /* 0x3014 */ u32 err; /* 0x3018 */ - TXMAC_ERR_INT_t err_int; /* 0x301C */ + u32 err_int; /* 0x301C */ u32 bp_ctrl; /* 0x3020 */ -} TXMAC_t, *PTXMAC_t; +}; /* END OF TXMAC REGISTER ADDRESS MAP */ @@ -1087,7 +1071,7 @@ typedef struct _RXMAC_t { /* Location: */ RXMAC_ERROR_REG_t err_reg; /* 0x409C */ } RXMAC_t, *PRXMAC_t; -/* END OF TXMAC REGISTER ADDRESS MAP */ +/* END OF RXMAC REGISTER ADDRESS MAP */ /* START OF MAC REGISTER ADDRESS MAP */ @@ -1632,9 +1616,9 @@ typedef struct _ADDRESS_MAP_t { struct rxdma_regs rxdma; /* unused section of rxdma address map */ u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)]; - TXMAC_t txmac; + struct txmac_regs txmac; /* unused section of txmac address map */ - u8 unused_txmac[4096 - sizeof(TXMAC_t)]; + u8 unused_txmac[4096 - sizeof(struct txmac_regs)]; RXMAC_t rxmac; /* unused section of rxmac address map */ u8 unused_rxmac[4096 - sizeof(RXMAC_t)]; diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c index dc9cb297a848..99aeb331c0e4 100644 --- a/drivers/staging/et131x/et1310_mac.c +++ b/drivers/staging/et131x/et1310_mac.c @@ -376,16 +376,16 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) void ConfigTxMacRegs(struct et131x_adapter *etdev) { - struct _TXMAC_t __iomem *pTxMac = &etdev->regs->txmac; + struct txmac_regs *txmac = &etdev->regs->txmac; /* We need to update the Control Frame Parameters * cfpt - control frame pause timer set to 64 (0x40) * cfep - control frame extended pause timer set to 0x0 */ if (etdev->FlowControl == None) - writel(0, &pTxMac->cf_param); + writel(0, &txmac->cf_param); else - writel(0x40, &pTxMac->cf_param); + writel(0x40, &txmac->cf_param); } void ConfigMacStatRegs(struct et131x_adapter *etdev) -- cgit v1.2.3 From 70a29a24088211369169b6285f33795be4d3a616 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:34:51 +0000 Subject: Staging: et131x: Kill rxmac crc fields More we don't need Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 82 +++++++---------------------- drivers/staging/et131x/et1310_mac.c | 6 +-- 2 files changed, 22 insertions(+), 66 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index d599f312963e..67aef73b3ce0 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -684,77 +684,33 @@ typedef union _RXMAC_CTRL_t { /* * structure for Wake On Lan Control and CRC 0 reg in rxmac address map * located at address 0x4004 + * 31-16: crc + * 15-12: reserved + * 11: ignore_pp + * 10: ignore_mp + * 9: clr_intr + * 8: ignore_link_chg + * 7: ignore_uni + * 6: ignore_multi + * 5: ignore_broad + * 4-0: valid_crc 4-0 */ -typedef union _RXMAC_WOL_CTL_CRC0_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 crc0:16; /* bits 16-31 */ - u32 reserve:4; /* bits 12-15 */ - u32 ignore_pp:1; /* bit 11 */ - u32 ignore_mp:1; /* bit 10 */ - u32 clr_intr:1; /* bit 9 */ - u32 ignore_link_chg:1; /* bit 8 */ - u32 ignore_uni:1; /* bit 7 */ - u32 ignore_multi:1; /* bit 6 */ - u32 ignore_broad:1; /* bit 5 */ - u32 valid_crc4:1; /* bit 4 */ - u32 valid_crc3:1; /* bit 3 */ - u32 valid_crc2:1; /* bit 2 */ - u32 valid_crc1:1; /* bit 1 */ - u32 valid_crc0:1; /* bit 0 */ -#else - u32 valid_crc0:1; /* bit 0 */ - u32 valid_crc1:1; /* bit 1 */ - u32 valid_crc2:1; /* bit 2 */ - u32 valid_crc3:1; /* bit 3 */ - u32 valid_crc4:1; /* bit 4 */ - u32 ignore_broad:1; /* bit 5 */ - u32 ignore_multi:1; /* bit 6 */ - u32 ignore_uni:1; /* bit 7 */ - u32 ignore_link_chg:1; /* bit 8 */ - u32 clr_intr:1; /* bit 9 */ - u32 ignore_mp:1; /* bit 10 */ - u32 ignore_pp:1; /* bit 11 */ - u32 reserve:4; /* bits 12-15 */ - u32 crc0:16; /* bits 16-31 */ -#endif - } bits; -} RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t; /* * structure for CRC 1 and CRC 2 reg in rxmac address map * located at address 0x4008 + * + * 31-16: crc2 + * 15-0: crc1 */ -typedef union _RXMAC_WOL_CRC12_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 crc2:16; /* bits 16-31 */ - u32 crc1:16; /* bits 0-15 */ -#else - u32 crc1:16; /* bits 0-15 */ - u32 crc2:16; /* bits 16-31 */ -#endif - } bits; -} RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t; /* * structure for CRC 3 and CRC 4 reg in rxmac address map * located at address 0x400C + * + * 31-16: crc4 + * 15-0: crc3 */ -typedef union _RXMAC_WOL_CRC34_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 crc4:16; /* bits 16-31 */ - u32 crc3:16; /* bits 0-15 */ -#else - u32 crc3:16; /* bits 0-15 */ - u32 crc4:16; /* bits 16-31 */ -#endif - } bits; -} RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t; /* * structure for Wake On Lan Source Address Lo reg in rxmac address map @@ -1029,9 +985,9 @@ typedef union _RXMAC_ERROR_REG_t { */ typedef struct _RXMAC_t { /* Location: */ RXMAC_CTRL_t ctrl; /* 0x4000 */ - RXMAC_WOL_CTL_CRC0_t crc0; /* 0x4004 */ - RXMAC_WOL_CRC12_t crc12; /* 0x4008 */ - RXMAC_WOL_CRC34_t crc34; /* 0x400C */ + u32 crc0; /* 0x4004 */ + u32 crc12; /* 0x4008 */ + u32 crc34; /* 0x400C */ RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */ RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */ u32 mask0_word0; /* 0x4018 */ diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c index 99aeb331c0e4..d42407c05457 100644 --- a/drivers/staging/et131x/et1310_mac.c +++ b/drivers/staging/et131x/et1310_mac.c @@ -247,9 +247,9 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) writel(0x8, &pRxMac->ctrl.value); /* Initialize WOL to disabled. */ - writel(0, &pRxMac->crc0.value); - writel(0, &pRxMac->crc12.value); - writel(0, &pRxMac->crc34.value); + writel(0, &pRxMac->crc0); + writel(0, &pRxMac->crc12); + writel(0, &pRxMac->crc34); /* We need to set the WOL mask0 - mask4 next. We initialize it to * its default Values of 0x00000000 because there are not WOL masks -- cgit v1.2.3 From b186f33137a124b3d10bcd7b9b35d76247b82014 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:34:57 +0000 Subject: Staging: et131x: kill off RXMAC_PF_CTRL_t Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 32 ++++++++------------------- drivers/staging/et131x/et1310_mac.c | 18 +++++++-------- drivers/staging/et131x/et131x_netdev.c | 34 ++++++++++++++--------------- 3 files changed, 33 insertions(+), 51 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index 67aef73b3ce0..ebbbc1a7bccc 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -830,29 +830,15 @@ typedef union _RXMAC_UNI_PF_ADDR3_t { /* * structure for Packet Filter Control reg in rxmac address map * located at address 0x4084 + * + * 31-23: unused + * 22-16: min_pkt_size + * 15-4: unused + * 3: filter_frag_en + * 2: filter_uni_en + * 1: filter_multi_en + * 0: filter_broad_en */ -typedef union _RXMAC_PF_CTRL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused2:9; /* bits 23-31 */ - u32 min_pkt_size:7; /* bits 16-22 */ - u32 unused1:12; /* bits 4-15 */ - u32 filter_frag_en:1; /* bit 3 */ - u32 filter_uni_en:1; /* bit 2 */ - u32 filter_multi_en:1; /* bit 1 */ - u32 filter_broad_en:1; /* bit 0 */ -#else - u32 filter_broad_en:1; /* bit 0 */ - u32 filter_multi_en:1; /* bit 1 */ - u32 filter_uni_en:1; /* bit 2 */ - u32 filter_frag_en:1; /* bit 3 */ - u32 unused1:12; /* bits 4-15 */ - u32 min_pkt_size:7; /* bits 16-22 */ - u32 unused2:9; /* bits 23-31 */ -#endif - } bits; -} RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t; /* * structure for Memory Controller Interface Control Max Segment reg in rxmac @@ -1017,7 +1003,7 @@ typedef struct _RXMAC_t { /* Location: */ u32 multi_hash2; /* 0x4078 */ u32 multi_hash3; /* 0x407C */ u32 multi_hash4; /* 0x4080 */ - RXMAC_PF_CTRL_t pf_ctrl; /* 0x4084 */ + u32 pf_ctrl; /* 0x4084 */ RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; /* 0x4088 */ RXMAC_MCIF_WATER_MARK_t mcif_water_mark; /* 0x408C */ RXMAC_RXQ_DIAG_t rxq_diag; /* 0x4090 */ diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c index d42407c05457..c1184abec916 100644 --- a/drivers/staging/et131x/et1310_mac.c +++ b/drivers/staging/et131x/et1310_mac.c @@ -241,7 +241,7 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) struct _RXMAC_t __iomem *pRxMac = &etdev->regs->rxmac; RXMAC_WOL_SA_LO_t sa_lo; RXMAC_WOL_SA_HI_t sa_hi; - RXMAC_PF_CTRL_t pf_ctrl = { 0 }; + u32 pf_ctrl = 0; /* Disable the MAC while it is being configured (also disable WOL) */ writel(0x8, &pRxMac->ctrl.value); @@ -292,12 +292,12 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) writel(sa_hi.value, &pRxMac->sa_hi.value); /* Disable all Packet Filtering */ - writel(0, &pRxMac->pf_ctrl.value); + writel(0, &pRxMac->pf_ctrl); /* Let's initialize the Unicast Packet filtering address */ if (etdev->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) { SetupDeviceForUnicast(etdev); - pf_ctrl.bits.filter_uni_en = 1; + pf_ctrl |= 4; /* Unicast filter */ } else { writel(0, &pRxMac->uni_pf_addr1.value); writel(0, &pRxMac->uni_pf_addr2.value); @@ -305,16 +305,14 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) } /* Let's initialize the Multicast hash */ - if (etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST) { - pf_ctrl.bits.filter_multi_en = 0; - } else { - pf_ctrl.bits.filter_multi_en = 1; + if (!(etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST)) { + pf_ctrl |= 2; /* Multicast filter */ SetupDeviceForMulticast(etdev); } /* Runt packet filtering. Didn't work in version A silicon. */ - pf_ctrl.bits.min_pkt_size = NIC_MIN_PACKET_SIZE + 4; - pf_ctrl.bits.filter_frag_en = 1; + pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << 16; + pf_ctrl |= 8; /* Fragment filter */ if (etdev->RegistryJumboPacket > 8192) { RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; @@ -370,7 +368,7 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) * dropping doesn't work, so it is disabled in the pf_ctrl register, * but we still leave the packet filter on. */ - writel(pf_ctrl.value, &pRxMac->pf_ctrl.value); + writel(pf_ctrl, &pRxMac->pf_ctrl); writel(0x9, &pRxMac->ctrl.value); } diff --git a/drivers/staging/et131x/et131x_netdev.c b/drivers/staging/et131x/et131x_netdev.c index 6d9f9be7a844..5cfebf0a2181 100644 --- a/drivers/staging/et131x/et131x_netdev.c +++ b/drivers/staging/et131x/et131x_netdev.c @@ -334,6 +334,8 @@ int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf, int cmd) * et131x_set_packet_filter - Configures the Rx Packet filtering on the device * @adapter: pointer to our private adapter structure * + * FIXME: lot of dups with MAC code + * * Returns 0 on success, errno on failure */ int et131x_set_packet_filter(struct et131x_adapter *adapter) @@ -341,10 +343,10 @@ int et131x_set_packet_filter(struct et131x_adapter *adapter) int status = 0; uint32_t filter = adapter->PacketFilter; RXMAC_CTRL_t ctrl; - RXMAC_PF_CTRL_t pf_ctrl; + u32 pf_ctrl; ctrl.value = readl(&adapter->regs->rxmac.ctrl.value); - pf_ctrl.value = readl(&adapter->regs->rxmac.pf_ctrl.value); + pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl); /* Default to disabled packet filtering. Enable it in the individual * case statements that require the device to filter something @@ -354,45 +356,41 @@ int et131x_set_packet_filter(struct et131x_adapter *adapter) /* Set us to be in promiscuous mode so we receive everything, this * is also true when we get a packet filter of 0 */ - if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0) { - pf_ctrl.bits.filter_broad_en = 0; - pf_ctrl.bits.filter_multi_en = 0; - pf_ctrl.bits.filter_uni_en = 0; - } else { + if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0) + pf_ctrl &= ~7; /* Clear filter bits */ + else { /* * Set us up with Multicast packet filtering. Three cases are * possible - (1) we have a multi-cast list, (2) we receive ALL * multicast entries or (3) we receive none. */ - if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST) { - pf_ctrl.bits.filter_multi_en = 0; - } else { + if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST) + pf_ctrl &= ~2; /* Multicast filter bit */ + else { SetupDeviceForMulticast(adapter); - pf_ctrl.bits.filter_multi_en = 1; + pf_ctrl |= 2; ctrl.bits.pkt_filter_disable = 0; } /* Set us up with Unicast packet filtering */ if (filter & ET131X_PACKET_TYPE_DIRECTED) { SetupDeviceForUnicast(adapter); - pf_ctrl.bits.filter_uni_en = 1; + pf_ctrl |= 4; ctrl.bits.pkt_filter_disable = 0; } /* Set us up with Broadcast packet filtering */ if (filter & ET131X_PACKET_TYPE_BROADCAST) { - pf_ctrl.bits.filter_broad_en = 1; + pf_ctrl |= 1; /* Broadcast filter bit */ ctrl.bits.pkt_filter_disable = 0; - } else { - pf_ctrl.bits.filter_broad_en = 0; - } + } else + pf_ctrl &= ~1; /* Setup the receive mac configuration registers - Packet * Filter control + the enable / disable for packet filter * in the control reg. */ - writel(pf_ctrl.value, - &adapter->regs->rxmac.pf_ctrl.value); + writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl); writel(ctrl.value, &adapter->regs->rxmac.ctrl.value); } return status; -- cgit v1.2.3 From 287acb63a593c9872005824d6866937617624668 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:35:02 +0000 Subject: Staging: et131x: Kill of the MCIF types Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 46 ++++++++--------------------- drivers/staging/et131x/et1310_mac.c | 20 +++++-------- 2 files changed, 19 insertions(+), 47 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index ebbbc1a7bccc..9441fe664d51 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -843,44 +843,22 @@ typedef union _RXMAC_UNI_PF_ADDR3_t { /* * structure for Memory Controller Interface Control Max Segment reg in rxmac * address map. Located at address 0x4088 + * + * 31-10: reserved + * 9-2: max_size + * 1: fc_en + * 0: seg_en */ -typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved:22; /* bits 10-31 */ - u32 max_size:8; /* bits 2-9 */ - u32 fc_en:1; /* bit 1 */ - u32 seg_en:1; /* bit 0 */ -#else - u32 seg_en:1; /* bit 0 */ - u32 fc_en:1; /* bit 1 */ - u32 max_size:8; /* bits 2-9 */ - u32 reserved:22; /* bits 10-31 */ -#endif - } bits; -} RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t; /* * structure for Memory Controller Interface Water Mark reg in rxmac address * map. Located at address 0x408C + * + * 31-26: unused + * 25-16: mark_hi + * 15-10: unused + * 9-0: mark_lo */ -typedef union _RXMAC_MCIF_WATER_MARK_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved2:6; /* bits 26-31 */ - u32 mark_hi:10; /* bits 16-25 */ - u32 reserved1:6; /* bits 10-15 */ - u32 mark_lo:10; /* bits 0-9 */ -#else - u32 mark_lo:10; /* bits 0-9 */ - u32 reserved1:6; /* bits 10-15 */ - u32 mark_hi:10; /* bits 16-25 */ - u32 reserved2:6; /* bits 26-31 */ -#endif - } bits; -} RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t; /* * structure for Rx Queue Dialog reg in rxmac address map. @@ -1004,8 +982,8 @@ typedef struct _RXMAC_t { /* Location: */ u32 multi_hash3; /* 0x407C */ u32 multi_hash4; /* 0x4080 */ u32 pf_ctrl; /* 0x4084 */ - RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; /* 0x4088 */ - RXMAC_MCIF_WATER_MARK_t mcif_water_mark; /* 0x408C */ + u32 mcif_ctrl_max_seg; /* 0x4088 */ + u32 mcif_water_mark; /* 0x408C */ RXMAC_RXQ_DIAG_t rxq_diag; /* 0x4090 */ RXMAC_SPACE_AVAIL_t space_avail; /* 0x4094 */ diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c index c1184abec916..8302098976ef 100644 --- a/drivers/staging/et131x/et1310_mac.c +++ b/drivers/staging/et131x/et1310_mac.c @@ -314,9 +314,7 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << 16; pf_ctrl |= 8; /* Fragment filter */ - if (etdev->RegistryJumboPacket > 8192) { - RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; - + if (etdev->RegistryJumboPacket > 8192) /* In order to transmit jumbo packets greater than 8k, the * FIFO between RxMAC and RxDMA needs to be reduced in size * to (16k - Jumbo packet size). In order to implement this, @@ -324,19 +322,15 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) * packets down into segments which are (max_size * 16). In * this case we selected 256 bytes, since this is the size of * the PCI-Express TLP's that the 1310 uses. + * + * seg_en on, fc_en off, size 0x10 */ - mcif_ctrl_max_seg.bits.seg_en = 0x1; - mcif_ctrl_max_seg.bits.fc_en = 0x0; - mcif_ctrl_max_seg.bits.max_size = 0x10; - - writel(mcif_ctrl_max_seg.value, - &pRxMac->mcif_ctrl_max_seg.value); - } else { - writel(0, &pRxMac->mcif_ctrl_max_seg.value); - } + writel(0x41, &pRxMac->mcif_ctrl_max_seg); + else + writel(0, &pRxMac->mcif_ctrl_max_seg); /* Initialize the MCIF water marks */ - writel(0, &pRxMac->mcif_water_mark.value); + writel(0, &pRxMac->mcif_water_mark); /* Initialize the MIF control */ writel(0, &pRxMac->mif_ctrl.value); -- cgit v1.2.3 From f7ae1957cac1388e7bbe070b13a5f5f5a98107d2 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:35:08 +0000 Subject: Staging: et131x: Kill off the rxq_diag types Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 23 ++++++----------------- drivers/staging/et131x/et131x_isr.c | 2 +- 2 files changed, 7 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index 9441fe664d51..f8a918928183 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -863,23 +863,12 @@ typedef union _RXMAC_UNI_PF_ADDR3_t { /* * structure for Rx Queue Dialog reg in rxmac address map. * located at address 0x4090 + * + * 31-26: reserved + * 25-16: rd_ptr + * 15-10: reserved + * 9-0: wr_ptr */ -typedef union _RXMAC_RXQ_DIAG_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved2:6; /* bits 26-31 */ - u32 rd_ptr:10; /* bits 16-25 */ - u32 reserved1:6; /* bits 10-15 */ - u32 wr_ptr:10; /* bits 0-9 */ -#else - u32 wr_ptr:10; /* bits 0-9 */ - u32 reserved1:6; /* bits 10-15 */ - u32 rd_ptr:10; /* bits 16-25 */ - u32 reserved2:6; /* bits 26-31 */ -#endif - } bits; -} RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t; /* * structure for space availiable reg in rxmac address map. @@ -984,7 +973,7 @@ typedef struct _RXMAC_t { /* Location: */ u32 pf_ctrl; /* 0x4084 */ u32 mcif_ctrl_max_seg; /* 0x4088 */ u32 mcif_water_mark; /* 0x408C */ - RXMAC_RXQ_DIAG_t rxq_diag; /* 0x4090 */ + u32 rxq_diag; /* 0x4090 */ RXMAC_SPACE_AVAIL_t space_avail; /* 0x4094 */ RXMAC_MIF_CTL_t mif_ctrl; /* 0x4098 */ diff --git a/drivers/staging/et131x/et131x_isr.c b/drivers/staging/et131x/et131x_isr.c index aa36e40ec248..5ff8665e687b 100644 --- a/drivers/staging/et131x/et131x_isr.c +++ b/drivers/staging/et131x/et131x_isr.c @@ -446,7 +446,7 @@ void et131x_isr_handler(struct work_struct *work) dev_warn(&etdev->pdev->dev, "Enable 0x%08x, Diag 0x%08x\n", readl(&iomem->rxmac.ctrl.value), - readl(&iomem->rxmac.rxq_diag.value)); + readl(&iomem->rxmac.rxq_diag)); /* * If we are debugging, we want to see this error, -- cgit v1.2.3 From 370d52acf7f2a8f4fccbf9fa49defd6e364ae1f3 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:35:13 +0000 Subject: Staging: et131x: Kill the SPACE_AVAIL type Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 23 ++++++----------------- drivers/staging/et131x/et1310_mac.c | 2 +- 2 files changed, 7 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index f8a918928183..f434b8660356 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -873,23 +873,12 @@ typedef union _RXMAC_UNI_PF_ADDR3_t { /* * structure for space availiable reg in rxmac address map. * located at address 0x4094 + * + * 31-17: reserved + * 16: space_avail_en + * 15-10: reserved + * 9-0: space_avail */ -typedef union _RXMAC_SPACE_AVAIL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved2:15; /* bits 17-31 */ - u32 space_avail_en:1; /* bit 16 */ - u32 reserved1:6; /* bits 10-15 */ - u32 space_avail:10; /* bits 0-9 */ -#else - u32 space_avail:10; /* bits 0-9 */ - u32 reserved1:6; /* bits 10-15 */ - u32 space_avail_en:1; /* bit 16 */ - u32 reserved2:15; /* bits 17-31 */ -#endif - } bits; -} RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t; /* * structure for management interface reg in rxmac address map. @@ -974,7 +963,7 @@ typedef struct _RXMAC_t { /* Location: */ u32 mcif_ctrl_max_seg; /* 0x4088 */ u32 mcif_water_mark; /* 0x408C */ u32 rxq_diag; /* 0x4090 */ - RXMAC_SPACE_AVAIL_t space_avail; /* 0x4094 */ + u32 space_avail; /* 0x4094 */ RXMAC_MIF_CTL_t mif_ctrl; /* 0x4098 */ RXMAC_ERROR_REG_t err_reg; /* 0x409C */ diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c index 8302098976ef..1b4c0e6d6765 100644 --- a/drivers/staging/et131x/et1310_mac.c +++ b/drivers/staging/et131x/et1310_mac.c @@ -336,7 +336,7 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) writel(0, &pRxMac->mif_ctrl.value); /* Initialize the Space Available Register */ - writel(0, &pRxMac->space_avail.value); + writel(0, &pRxMac->space_avail); /* Initialize the the mif_ctrl register * bit 3: Receive code error. One or more nibbles were signaled as -- cgit v1.2.3 From dcb0789bb344b76fdeb32876f1e498a5cd19ecc1 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:35:19 +0000 Subject: Staging: et131x: Kill MIF_CTL_t Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 20 +++++--------------- drivers/staging/et131x/et1310_mac.c | 6 +++--- 2 files changed, 8 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index f434b8660356..e57109345d16 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -883,21 +883,11 @@ typedef union _RXMAC_UNI_PF_ADDR3_t { /* * structure for management interface reg in rxmac address map. * located at address 0x4098 + * + * 31-18: reserved + * 17: drop_pkt_en + * 16-0: drop_pkt_mask */ -typedef union _RXMAC_MIF_CTL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserve:14; /* bits 18-31 */ - u32 drop_pkt_en:1; /* bit 17 */ - u32 drop_pkt_mask:17; /* bits 0-16 */ -#else - u32 drop_pkt_mask:17; /* bits 0-16 */ - u32 drop_pkt_en:1; /* bit 17 */ - u32 reserve:14; /* bits 18-31 */ -#endif - } bits; -} RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t; /* * structure for Error reg in rxmac address map. @@ -965,7 +955,7 @@ typedef struct _RXMAC_t { /* Location: */ u32 rxq_diag; /* 0x4090 */ u32 space_avail; /* 0x4094 */ - RXMAC_MIF_CTL_t mif_ctrl; /* 0x4098 */ + u32 mif_ctrl; /* 0x4098 */ RXMAC_ERROR_REG_t err_reg; /* 0x409C */ } RXMAC_t, *PRXMAC_t; diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c index 1b4c0e6d6765..a9f924dd6b0e 100644 --- a/drivers/staging/et131x/et1310_mac.c +++ b/drivers/staging/et131x/et1310_mac.c @@ -333,7 +333,7 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) writel(0, &pRxMac->mcif_water_mark); /* Initialize the MIF control */ - writel(0, &pRxMac->mif_ctrl.value); + writel(0, &pRxMac->mif_ctrl); /* Initialize the Space Available Register */ writel(0, &pRxMac->space_avail); @@ -352,9 +352,9 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) * bit 17: Drop packet enable */ if (etdev->linkspeed == TRUEPHY_SPEED_100MBPS) - writel(0x30038, &pRxMac->mif_ctrl.value); + writel(0x30038, &pRxMac->mif_ctrl); else - writel(0x30030, &pRxMac->mif_ctrl.value); + writel(0x30030, &pRxMac->mif_ctrl); /* Finally we initialize RxMac to be enabled & WOL disabled. Packet * filter is always enabled since it is where the runt packets are -- cgit v1.2.3 From fef5ba3ae9760fdc2688b7160fa056e7ef2700bb Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:35:24 +0000 Subject: Staging: et131x: kill the rxmac ERROR_REG_t Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 26 +++++++------------------- drivers/staging/et131x/et131x_isr.c | 2 +- 2 files changed, 8 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index e57109345d16..5f6a7b549677 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -892,25 +892,13 @@ typedef union _RXMAC_UNI_PF_ADDR3_t { /* * structure for Error reg in rxmac address map. * located at address 0x409C + * + * 31-4: unused + * 3: mif + * 2: async + * 1: pkt_filter + * 0: mcif */ -typedef union _RXMAC_ERROR_REG_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserve:28; /* bits 4-31 */ - u32 mif:1; /* bit 3 */ - u32 async:1; /* bit 2 */ - u32 pkt_filter:1; /* bit 1 */ - u32 mcif:1; /* bit 0 */ -#else - u32 mcif:1; /* bit 0 */ - u32 pkt_filter:1; /* bit 1 */ - u32 async:1; /* bit 2 */ - u32 mif:1; /* bit 3 */ - u32 reserve:28; /* bits 4-31 */ -#endif - } bits; -} RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t; /* * Rx MAC Module of JAGCore Address Mapping @@ -956,7 +944,7 @@ typedef struct _RXMAC_t { /* Location: */ u32 space_avail; /* 0x4094 */ u32 mif_ctrl; /* 0x4098 */ - RXMAC_ERROR_REG_t err_reg; /* 0x409C */ + u32 err_reg; /* 0x409C */ } RXMAC_t, *PRXMAC_t; /* END OF RXMAC REGISTER ADDRESS MAP */ diff --git a/drivers/staging/et131x/et131x_isr.c b/drivers/staging/et131x/et131x_isr.c index 5ff8665e687b..87c8de636711 100644 --- a/drivers/staging/et131x/et131x_isr.c +++ b/drivers/staging/et131x/et131x_isr.c @@ -441,7 +441,7 @@ void et131x_isr_handler(struct work_struct *work) dev_warn(&etdev->pdev->dev, "RXMAC interrupt, error 0x%08x. Requesting reset\n", - readl(&iomem->rxmac.err_reg.value)); + readl(&iomem->rxmac.err_reg)); dev_warn(&etdev->pdev->dev, "Enable 0x%08x, Diag 0x%08x\n", -- cgit v1.2.3 From bd03d0d5bc253533a6d169a82f56626d552d9471 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:35:30 +0000 Subject: Staging: et131x: kill off the rxmac ctrl type Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 35 +++++++++-------------------- drivers/staging/et131x/et1310_mac.c | 4 ++-- drivers/staging/et131x/et131x_isr.c | 2 +- drivers/staging/et131x/et131x_netdev.c | 14 ++++++------ 4 files changed, 20 insertions(+), 35 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index 5f6a7b549677..1e0ffcd17886 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -655,31 +655,16 @@ struct txmac_regs { /* Location: */ /* * structure for rxmac control reg in rxmac address map * located at address 0x4000 + * + * 31-7: reserved + * 6: rxmac_int_disable + * 5: async_disable + * 4: mif_disable + * 3: wol_disable + * 2: pkt_filter_disable + * 1: mcif_disable + * 0: rxmac_en */ -typedef union _RXMAC_CTRL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved:25; /* bits 7-31 */ - u32 rxmac_int_disable:1; /* bit 6 */ - u32 async_disable:1; /* bit 5 */ - u32 mif_disable:1; /* bit 4 */ - u32 wol_disable:1; /* bit 3 */ - u32 pkt_filter_disable:1; /* bit 2 */ - u32 mcif_disable:1; /* bit 1 */ - u32 rxmac_en:1; /* bit 0 */ -#else - u32 rxmac_en:1; /* bit 0 */ - u32 mcif_disable:1; /* bit 1 */ - u32 pkt_filter_disable:1; /* bit 2 */ - u32 wol_disable:1; /* bit 3 */ - u32 mif_disable:1; /* bit 4 */ - u32 async_disable:1; /* bit 5 */ - u32 rxmac_int_disable:1; /* bit 6 */ - u32 reserved:25; /* bits 7-31 */ -#endif - } bits; -} RXMAC_CTRL_t, *PRXMAC_CTRL_t; /* * structure for Wake On Lan Control and CRC 0 reg in rxmac address map @@ -904,7 +889,7 @@ typedef union _RXMAC_UNI_PF_ADDR3_t { * Rx MAC Module of JAGCore Address Mapping */ typedef struct _RXMAC_t { /* Location: */ - RXMAC_CTRL_t ctrl; /* 0x4000 */ + u32 ctrl; /* 0x4000 */ u32 crc0; /* 0x4004 */ u32 crc12; /* 0x4008 */ u32 crc34; /* 0x400C */ diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c index a9f924dd6b0e..a292b1edc414 100644 --- a/drivers/staging/et131x/et1310_mac.c +++ b/drivers/staging/et131x/et1310_mac.c @@ -244,7 +244,7 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) u32 pf_ctrl = 0; /* Disable the MAC while it is being configured (also disable WOL) */ - writel(0x8, &pRxMac->ctrl.value); + writel(0x8, &pRxMac->ctrl); /* Initialize WOL to disabled. */ writel(0, &pRxMac->crc0); @@ -363,7 +363,7 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) * but we still leave the packet filter on. */ writel(pf_ctrl, &pRxMac->pf_ctrl); - writel(0x9, &pRxMac->ctrl.value); + writel(0x9, &pRxMac->ctrl); } void ConfigTxMacRegs(struct et131x_adapter *etdev) diff --git a/drivers/staging/et131x/et131x_isr.c b/drivers/staging/et131x/et131x_isr.c index 87c8de636711..8b6e0b7ec568 100644 --- a/drivers/staging/et131x/et131x_isr.c +++ b/drivers/staging/et131x/et131x_isr.c @@ -445,7 +445,7 @@ void et131x_isr_handler(struct work_struct *work) dev_warn(&etdev->pdev->dev, "Enable 0x%08x, Diag 0x%08x\n", - readl(&iomem->rxmac.ctrl.value), + readl(&iomem->rxmac.ctrl), readl(&iomem->rxmac.rxq_diag)); /* diff --git a/drivers/staging/et131x/et131x_netdev.c b/drivers/staging/et131x/et131x_netdev.c index 5cfebf0a2181..226641acd954 100644 --- a/drivers/staging/et131x/et131x_netdev.c +++ b/drivers/staging/et131x/et131x_netdev.c @@ -342,16 +342,16 @@ int et131x_set_packet_filter(struct et131x_adapter *adapter) { int status = 0; uint32_t filter = adapter->PacketFilter; - RXMAC_CTRL_t ctrl; + u32 ctrl; u32 pf_ctrl; - ctrl.value = readl(&adapter->regs->rxmac.ctrl.value); + ctrl = readl(&adapter->regs->rxmac.ctrl); pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl); /* Default to disabled packet filtering. Enable it in the individual * case statements that require the device to filter something */ - ctrl.bits.pkt_filter_disable = 1; + ctrl |= 0x04; /* Set us to be in promiscuous mode so we receive everything, this * is also true when we get a packet filter of 0 @@ -369,20 +369,20 @@ int et131x_set_packet_filter(struct et131x_adapter *adapter) else { SetupDeviceForMulticast(adapter); pf_ctrl |= 2; - ctrl.bits.pkt_filter_disable = 0; + ctrl &= ~0x04; } /* Set us up with Unicast packet filtering */ if (filter & ET131X_PACKET_TYPE_DIRECTED) { SetupDeviceForUnicast(adapter); pf_ctrl |= 4; - ctrl.bits.pkt_filter_disable = 0; + ctrl &= ~0x04; } /* Set us up with Broadcast packet filtering */ if (filter & ET131X_PACKET_TYPE_BROADCAST) { pf_ctrl |= 1; /* Broadcast filter bit */ - ctrl.bits.pkt_filter_disable = 0; + ctrl &= ~0x04; } else pf_ctrl &= ~1; @@ -391,7 +391,7 @@ int et131x_set_packet_filter(struct et131x_adapter *adapter) * in the control reg. */ writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl); - writel(ctrl.value, &adapter->regs->rxmac.ctrl.value); + writel(ctrl, &adapter->regs->rxmac.ctrl); } return status; } -- cgit v1.2.3 From 22e0967f72494564e416b157568ed5876666ad26 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 18 Jan 2010 15:35:35 +0000 Subject: Staging: et131x_kill MAC_STAT_t Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_address_map.h | 44 +++++++++-------------------- 1 file changed, 13 insertions(+), 31 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index 1e0ffcd17886..ea746ba41faf 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -1106,37 +1106,19 @@ typedef struct _RXMAC_t { /* Location: */ /* * structure for Interface Status reg in mac address map. * located at address 0x503C + * + * 31-10: reserved + * 9: excess_defer + * 8: clash + * 7: phy_jabber + * 6: phy_link_ok + * 5: phy_full_duplex + * 4: phy_speed + * 3: pe100x_link_fail + * 2: pe10t_loss_carrier + * 1: pe10t_sqe_error + * 0: pe10t_jabber */ -typedef union _MAC_IF_STAT_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved:22; /* bits 10-31 */ - u32 excess_defer:1; /* bit 9 */ - u32 clash:1; /* bit 8 */ - u32 phy_jabber:1; /* bit 7 */ - u32 phy_link_ok:1; /* bit 6 */ - u32 phy_full_duplex:1; /* bit 5 */ - u32 phy_speed:1; /* bit 4 */ - u32 pe100x_link_fail:1; /* bit 3 */ - u32 pe10t_loss_carrie:1; /* bit 2 */ - u32 pe10t_sqe_error:1; /* bit 1 */ - u32 pe10t_jabber:1; /* bit 0 */ -#else - u32 pe10t_jabber:1; /* bit 0 */ - u32 pe10t_sqe_error:1; /* bit 1 */ - u32 pe10t_loss_carrie:1; /* bit 2 */ - u32 pe100x_link_fail:1; /* bit 3 */ - u32 phy_speed:1; /* bit 4 */ - u32 phy_full_duplex:1; /* bit 5 */ - u32 phy_link_ok:1; /* bit 6 */ - u32 phy_jabber:1; /* bit 7 */ - u32 clash:1; /* bit 8 */ - u32 excess_defer:1; /* bit 9 */ - u32 reserved:22; /* bits 10-31 */ -#endif - } bits; -} MAC_IF_STAT_t, *PMAC_IF_STAT_t; /* * structure for Mac Station Address, Part 1 reg in mac address map. @@ -1197,7 +1179,7 @@ typedef struct _MAC_t { /* Location: */ u32 mii_mgmt_stat; /* 0x5030 */ u32 mii_mgmt_indicator; /* 0x5034 */ u32 if_ctrl; /* 0x5038 */ - MAC_IF_STAT_t if_stat; /* 0x503C */ + u32 if_stat; /* 0x503C */ MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */ MAC_STATION_ADDR2_t station_addr_2; /* 0x5044 */ } MAC_t, *PMAC_t; -- cgit v1.2.3 From 1e5065dbd6fe53b46d8281db7b4286751dcf607a Mon Sep 17 00:00:00 2001 From: Himanshu Chauhan Date: Sat, 23 Jan 2010 01:51:57 +0530 Subject: Staging: usbip: minor code cleanup Signed-off-by: Himanshu Chauhan Signed-off-by: Greg Kroah-Hartman --- drivers/staging/usbip/usbip_common.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/usbip/usbip_common.c b/drivers/staging/usbip/usbip_common.c index ddb6f5fd04d5..57c0ff5ab9a5 100644 --- a/drivers/staging/usbip/usbip_common.c +++ b/drivers/staging/usbip/usbip_common.c @@ -55,10 +55,7 @@ static ssize_t show_flag(struct device *dev, struct device_attribute *attr, static ssize_t store_flag(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - unsigned long flag; - - sscanf(buf, "%lx", &flag); - usbip_debug_flag = flag; + sscanf(buf, "%lx", &usbip_debug_flag); return count; } -- cgit v1.2.3 From aad86577b829be29048e0a692e1c28c3ffeda6ca Mon Sep 17 00:00:00 2001 From: Himanshu Chauhan Date: Sat, 23 Jan 2010 02:52:41 +0530 Subject: Staging: usbip: use print_hex_dump() instead of open coding it. Signed-off-by: Himanshu Chauhan Signed-off-by: Greg Kroah-Hartman --- drivers/staging/usbip/usbip_common.c | 29 ++--------------------------- 1 file changed, 2 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/usbip/usbip_common.c b/drivers/staging/usbip/usbip_common.c index 57c0ff5ab9a5..3367a5217694 100644 --- a/drivers/staging/usbip/usbip_common.c +++ b/drivers/staging/usbip/usbip_common.c @@ -63,33 +63,8 @@ DEVICE_ATTR(usbip_debug, (S_IRUGO | S_IWUSR), show_flag, store_flag); static void usbip_dump_buffer(char *buff, int bufflen) { - int i; - - if (bufflen > 128) { - for (i = 0; i < 128; i++) { - if (i%24 == 0) - printk(KERN_DEBUG " "); - printk(KERN_DEBUG "%02x ", (unsigned char) buff[i]); - if (i%4 == 3) - printk(KERN_DEBUG "| "); - if (i%24 == 23) - printk(KERN_DEBUG "\n"); - } - printk(KERN_DEBUG "... (%d byte)\n", bufflen); - return; - } - - for (i = 0; i < bufflen; i++) { - if (i%24 == 0) - printk(KERN_DEBUG " "); - printk(KERN_DEBUG "%02x ", (unsigned char) buff[i]); - if (i%4 == 3) - printk(KERN_DEBUG "| "); - if (i%24 == 23) - printk(KERN_DEBUG "\n"); - } - printk(KERN_DEBUG "\n"); - + print_hex_dump(KERN_DEBUG, "usb-ip", DUMP_PREFIX_OFFSET, 16, 4, + buff, bufflen, false); } static void usbip_dump_pipe(unsigned int p) -- cgit v1.2.3 From a439f5bff51d3e0c93d61ee6886b9dbf29a03da9 Mon Sep 17 00:00:00 2001 From: Himanshu Chauhan Date: Sat, 23 Jan 2010 10:36:56 +0530 Subject: Staging: usbip: Remove dead code This patch removes the dead uncompiled code in usbip_common.c Signed-off-by: Himanshu Chauhan Signed-off-by: Greg Kroah-Hartman --- drivers/staging/usbip/usbip_common.c | 54 ------------------------------------ 1 file changed, 54 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/usbip/usbip_common.c b/drivers/staging/usbip/usbip_common.c index 3367a5217694..d8197028f20a 100644 --- a/drivers/staging/usbip/usbip_common.c +++ b/drivers/staging/usbip/usbip_common.c @@ -530,60 +530,6 @@ err: } EXPORT_SYMBOL_GPL(usbip_xmit); - -/* now a usrland utility should set options. */ -#if 0 -int setquickack(struct socket *socket) -{ - mm_segment_t oldfs; - int val = 1; - int ret; - - oldfs = get_fs(); - set_fs(get_ds()); - ret = socket->ops->setsockopt(socket, SOL_TCP, TCP_QUICKACK, - (char __user *) &val, sizeof(ret)); - set_fs(oldfs); - - return ret; -} - -int setnodelay(struct socket *socket) -{ - mm_segment_t oldfs; - int val = 1; - int ret; - - oldfs = get_fs(); - set_fs(get_ds()); - ret = socket->ops->setsockopt(socket, SOL_TCP, TCP_NODELAY, - (char __user *) &val, sizeof(ret)); - set_fs(oldfs); - - return ret; -} - -int setkeepalive(struct socket *socket) -{ - mm_segment_t oldfs; - int val = 1; - int ret; - - oldfs = get_fs(); - set_fs(get_ds()); - ret = socket->ops->setsockopt(socket, SOL_SOCKET, SO_KEEPALIVE, - (char __user *) &val, sizeof(ret)); - set_fs(oldfs); - - return ret; -} - -void setreuse(struct socket *socket) -{ - socket->sk->sk_reuse = 1; -} -#endif - struct socket *sockfd_to_socket(unsigned int sockfd) { struct socket *socket; -- cgit v1.2.3 From 411a861fc4f92cf0f5039928b448dcc7ca31d423 Mon Sep 17 00:00:00 2001 From: Himanshu Date: Sat, 23 Jan 2010 17:52:02 +0530 Subject: Staging: usbip: Seperate usbip config debug from CONFIG_USB_DEBUG Signed-off-by: Himanshu Signed-off-by: Greg Kroah-Hartman --- drivers/staging/usbip/Kconfig | 7 +++++++ drivers/staging/usbip/Makefile | 2 +- drivers/staging/usbip/usbip_common.c | 2 +- drivers/staging/usbip/usbip_common.h | 8 ++++---- 4 files changed, 13 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/usbip/Kconfig b/drivers/staging/usbip/Kconfig index 350d5d65ccf3..2c1d10acb8b5 100644 --- a/drivers/staging/usbip/Kconfig +++ b/drivers/staging/usbip/Kconfig @@ -34,3 +34,10 @@ config USB_IP_HOST To compile this driver as a module, choose M here: the module will be called usbip. + +config USB_IP_DEBUG_ENABLE + bool "USB-IP Debug Enable" + depends on USB_IP_COMMON + default N + ---help--- + This enables the debug messages from the USB-IP drivers. diff --git a/drivers/staging/usbip/Makefile b/drivers/staging/usbip/Makefile index 179f4211f96b..6f2916b1807a 100644 --- a/drivers/staging/usbip/Makefile +++ b/drivers/staging/usbip/Makefile @@ -7,6 +7,6 @@ vhci-hcd-objs := vhci_sysfs.o vhci_tx.o vhci_rx.o vhci_hcd.o obj-$(CONFIG_USB_IP_HOST) += usbip.o usbip-objs := stub_dev.o stub_main.o stub_rx.o stub_tx.o -ifeq ($(CONFIG_USB_DEBUG),y) +ifeq ($(CONFIG_USB_IP_DEBUG_ENABLE),y) EXTRA_CFLAGS += -DDEBUG endif diff --git a/drivers/staging/usbip/usbip_common.c b/drivers/staging/usbip/usbip_common.c index d8197028f20a..7a45da8f9565 100644 --- a/drivers/staging/usbip/usbip_common.c +++ b/drivers/staging/usbip/usbip_common.c @@ -33,7 +33,7 @@ /*-------------------------------------------------------------------------*/ /* debug routines */ -#ifdef CONFIG_USB_DEBUG +#ifdef CONFIG_USB_IP_DEBUG_ENABLE unsigned long usbip_debug_flag = 0xffffffff; #else unsigned long usbip_debug_flag; diff --git a/drivers/staging/usbip/usbip_common.h b/drivers/staging/usbip/usbip_common.h index 1ca3eab8af18..6f1dcb197d13 100644 --- a/drivers/staging/usbip/usbip_common.h +++ b/drivers/staging/usbip/usbip_common.h @@ -33,12 +33,12 @@ */ /** - * usbip_udbg - print debug messages if CONFIG_USB_DEBUG is defined + * usbip_udbg - print debug messages if CONFIG_USB_IP_DEBUG_ENABLE is defined * @fmt: * @args: */ -#ifdef CONFIG_USB_DEBUG +#ifdef CONFIG_USB_IP_DEBUG_ENABLE #define usbip_udbg(fmt, args...) \ do { \ @@ -47,11 +47,11 @@ __FILE__, __LINE__, __func__, ##args); \ } while (0) -#else /* CONFIG_USB_DEBUG */ +#else /* CONFIG_USB_IP_DEBUG_ENABLE */ #define usbip_udbg(fmt, args...) do { } while (0) -#endif /* CONFIG_USB_DEBUG */ +#endif /* CONFIG_USB_IP_DEBUG_ENABLE */ enum { -- cgit v1.2.3 From e501b36bdf85212d537b30babf60dfedf3fdcebd Mon Sep 17 00:00:00 2001 From: d binderman Date: Tue, 26 Jan 2010 10:00:25 +0000 Subject: Staging: otus: fix memory leak Fix memory leak in drivers/staging/otus Signed-off-by: David Binderman --- drivers/staging/otus/ioctl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/otus/ioctl.c b/drivers/staging/otus/ioctl.c index ebaedb7b1688..8c47b1a68627 100644 --- a/drivers/staging/otus/ioctl.c +++ b/drivers/staging/otus/ioctl.c @@ -866,15 +866,15 @@ int usbdrvwext_giwscan(struct net_device *dev, char *current_ev = extra; char *end_buf; int i; - /* struct zsBssList BssList; */ - struct zsBssListV1 *pBssList = kmalloc(sizeof(struct zsBssListV1), - GFP_KERNEL); /* BssList = wd->sta.pBssList; */ /* zmw_get_wlan_dev(dev); */ if (macp->DeviceOpened != 1) return 0; + /* struct zsBssList BssList; */ + struct zsBssListV1 *pBssList = kmalloc(sizeof(struct zsBssListV1), + GFP_KERNEL); if (data->length == 0) end_buf = extra + IW_SCAN_MAX_DATA; else -- cgit v1.2.3 From 1994130e4f881696aad562429fbbafeb73418e5a Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Mon, 25 Jan 2010 13:11:49 -0600 Subject: Staging: r8187se: Fix a faulty if and do additional cleanups Cleanup the driver and fix a faulty if statement. Signed-off-by: Larry Finger Tested by: Bernhard Schiffner Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8187se/r8180_core.c | 305 +++++++++++++-------------------- 1 file changed, 122 insertions(+), 183 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8187se/r8180_core.c b/drivers/staging/rtl8187se/r8180_core.c index 1fb9e1141df8..9c2f4d3b58c7 100644 --- a/drivers/staging/rtl8187se/r8180_core.c +++ b/drivers/staging/rtl8187se/r8180_core.c @@ -41,13 +41,6 @@ #include "ieee80211/dot11d.h" -#ifndef PCI_VENDOR_ID_BELKIN - #define PCI_VENDOR_ID_BELKIN 0x1799 -#endif -#ifndef PCI_VENDOR_ID_DLINK - #define PCI_VENDOR_ID_DLINK 0x1186 -#endif - static struct pci_device_id rtl8180_pci_id_tbl[] __devinitdata = { { .vendor = PCI_VENDOR_ID_REALTEK, @@ -1421,11 +1414,9 @@ u16 N_DBPSOfRate(u16 DataRate) return N_DBPS; } -//{by amy 080312 // // Description: // For Netgear case, they want good-looking singal strength. -// 2004.12.05, by rcnjko. // long NetgearSignalStrengthTranslate(long LastSS, long CurrSS) { @@ -1481,7 +1472,6 @@ long TranslateToDbm8185(u8 SignalStrengthIndex) // This is different with PerformSignalSmoothing8185 in smoothing fomula. // No dramatic adjustion is apply because dynamic mechanism need some degree // of correctness. Ported from 8187B. -// 2007-02-26, by Bruce. // void PerformUndecoratedSignalSmoothing8185(struct r8180_priv *priv, bool bCckRate) @@ -1502,7 +1492,6 @@ void PerformUndecoratedSignalSmoothing8185(struct r8180_priv *priv, priv->CurCCKRSSI = 0; } -//by amy 080312} /* This is rough RX isr handling routine*/ void rtl8180_rx(struct net_device *dev) @@ -1638,7 +1627,7 @@ void rtl8180_rx(struct net_device *dev) } signal=(unsigned char)(((*(priv->rxringtail+3))& (0x00ff0000))>>16); - signal=(signal&0xfe)>>1; // Modify by hikaru 6.6 + signal = (signal & 0xfe) >> 1; quality=(unsigned char)((*(priv->rxringtail+3)) & (0xff)); @@ -1652,7 +1641,6 @@ void rtl8180_rx(struct net_device *dev) stats.rate = rtl8180_rate2rate(rate); Antenna = (((*(priv->rxringtail +3))& (0x00008000)) == 0 )? 0:1 ; -//by amy for antenna if(!rtl8180_IsWirelessBMode(stats.rate)) { // OFDM rate. @@ -1691,11 +1679,10 @@ void rtl8180_rx(struct net_device *dev) RXAGC=(95-RXAGC)*100/65; } priv->SignalStrength = (u8)RXAGC; - priv->RecvSignalPower = RxAGC_dBm ; // It can use directly by SD3 CMLin + priv->RecvSignalPower = RxAGC_dBm; priv->RxPower = rxpower; priv->RSSI = RSSI; -//{by amy 080312 - // SQ translation formular is provided by SD3 DZ. 2006.06.27, by rcnjko. + /* SQ translation formula is provided by SD3 DZ. 2006.06.27 */ if(quality >= 127) quality = 1;//0; //0 will cause epc to show signal zero , walk aroud now; else if(quality < 27) @@ -1712,7 +1699,6 @@ void rtl8180_rx(struct net_device *dev) // printk("==========================>rx : RXAGC is %d,signalstrength is %d\n",RXAGC,stats.signalstrength); stats.rssi = priv->wstats.qual.qual = priv->SignalQuality; stats.noise = priv->wstats.qual.noise = 100 - priv ->wstats.qual.qual; -//by amy 080312} bHwError = (((*(priv->rxringtail))& (0x00000fff)) == 4080)| (((*(priv->rxringtail))& (0x04000000)) != 0 ) | (((*(priv->rxringtail))& (0x08000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x10000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x20000000)) != 0 ); bCRC = ((*(priv->rxringtail)) & (0x00002000)) >> 13; @@ -1725,11 +1711,12 @@ void rtl8180_rx(struct net_device *dev) (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3)) && (!bHwError) && (!bCRC)&& (!bICV)) { -//by amy 080312 - // Perform signal smoothing for dynamic mechanism on demand. - // This is different with PerformSignalSmoothing8185 in smoothing fomula. - // No dramatic adjustion is apply because dynamic mechanism need some degree - // of correctness. 2007.01.23, by shien chang. + /* Perform signal smoothing for dynamic + * mechanism on demand. This is different + * with PerformSignalSmoothing8185 in smoothing + * fomula. No dramatic adjustion is apply + * because dynamic mechanism need some degree + * of correctness. */ PerformUndecoratedSignalSmoothing8185(priv,bCckRate); // // For good-looking singal strength. @@ -1749,12 +1736,9 @@ void rtl8180_rx(struct net_device *dev) // Figure out which antenna that received the lasted packet. priv->LastRxPktAntenna = Antenna ? 1 : 0; // 0: aux, 1: main. -//by amy 080312 SwAntennaDiversityRxOk8185(dev, priv->SignalStrength); } -//by amy for antenna -#ifndef DUMMY_RX if(first){ if(!priv->rx_skb_complete){ /* seems that HW sometimes fails to reiceve and @@ -1810,19 +1794,12 @@ void rtl8180_rx(struct net_device *dev) if(last && !priv->rx_skb_complete){ if(priv->rx_skb->len > 4) skb_trim(priv->rx_skb,priv->rx_skb->len-4); -#ifndef RX_DONT_PASS_UL if(!ieee80211_rtl_rx(priv->ieee80211, - priv->rx_skb, &stats)){ -#endif // RX_DONT_PASS_UL - + priv->rx_skb, &stats)) dev_kfree_skb_any(priv->rx_skb); -#ifndef RX_DONT_PASS_UL - } -#endif priv->rx_skb_complete=1; } -#endif //DUMMY_RX pci_dma_sync_single_for_device(priv->pdev, priv->rxbuffer->dma, priv->rxbuffersize * \ @@ -2056,7 +2033,7 @@ short rtl8180_tx(struct net_device *dev, u8* txbuf, int len, int priority, u16 RtsDur = 0; u16 ThisFrameTime = 0; u16 TxDescDuration = 0; - u8 ownbit_flag = false; //added by david woo for sync Tx, 2007.12.14 + u8 ownbit_flag = false; switch(priority) { case MANAGE_PRIORITY: @@ -2123,7 +2100,8 @@ short rtl8180_tx(struct net_device *dev, u8* txbuf, int len, int priority, //YJ,add,080828,for Keep alive priv->NumTxUnicast++; - // Figure out ACK rate according to BSS basic rate and Tx rate, 2006.03.08 by rcnjko. + /* Figure out ACK rate according to BSS basic rate + * and Tx rate. */ AckTime = ComputeTxTime(14, 10,0, 0); // AckCTSLng = 14 use 1M bps send if ( ((len + sCrcLng) > priv->rts) && priv->rts ) @@ -2206,7 +2184,7 @@ short rtl8180_tx(struct net_device *dev, u8* txbuf, int len, int priority, *tail |= (1<<15); /* no encrypt */ if(remain==len && !descfrag) { - ownbit_flag = false; //added by david woo,2007.12.14 + ownbit_flag = false; *tail = *tail| (1<<29) ; //fist segment of the packet *tail = *tail |(len); } else { @@ -2556,27 +2534,16 @@ void watch_dog_adaptive(unsigned long data) } // Tx High Power Mechanism. -#ifdef HIGH_POWER if(CheckHighPower((struct net_device *)data)) - { queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->tx_pw_wq); - } -#endif // Tx Power Tracking on 87SE. -#ifdef TX_TRACK - //if( priv->bTxPowerTrack ) //lzm mod 080826 if (CheckTxPwrTracking((struct net_device *)data)) TxPwrTracking87SE((struct net_device *)data); -#endif // Perform DIG immediately. -#ifdef SW_DIG if(CheckDig((struct net_device *)data) == true) - { queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_dig_wq); - } -#endif rtl8180_watch_dog((struct net_device *)data); queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->GPIOChangeRFWorkItem); @@ -2747,10 +2714,8 @@ short rtl8180_init(struct net_device *dev) priv->TxPollingTimes = 0;//lzm add 080826 priv->bLeisurePs = true; priv->dot11PowerSaveMode = eActive; -//by amy for antenna priv->AdMinCheckPeriod = 5; priv->AdMaxCheckPeriod = 10; -// Lower signal strength threshold to fit the HW participation in antenna diversity. +by amy 080312 priv->AdMaxRxSsThreshold = 30;//60->30 priv->AdRxSsThreshold = 20;//50->20 priv->AdCheckPeriod = priv->AdMinCheckPeriod; @@ -2765,8 +2730,6 @@ short rtl8180_init(struct net_device *dev) init_timer(&priv->SwAntennaDiversityTimer); priv->SwAntennaDiversityTimer.data = (unsigned long)dev; priv->SwAntennaDiversityTimer.function = (void *)SwAntennaDiversityTimerCallback; -//by amy for antenna -//{by amy 080312 priv->bDigMechanism = 1; priv->InitialGain = 6; priv->bXtalCalibration = false; @@ -2803,58 +2766,63 @@ short rtl8180_init(struct net_device *dev) priv->NumTxUnicast = 0; priv->keepAliveLevel = DEFAULT_KEEP_ALIVE_LEVEL; priv->PowerProfile = POWER_PROFILE_AC; - priv->CurrRetryCnt=0; - priv->LastRetryCnt=0; - priv->LastTxokCnt=0; - priv->LastRxokCnt=0; - priv->LastRetryRate=0; - priv->bTryuping=0; - priv->CurrTxRate=0; - priv->CurrRetryRate=0; - priv->TryupingCount=0; - priv->TryupingCountNoData=0; - priv->TryDownCountLowData=0; - priv->LastTxOKBytes=0; - priv->LastFailTxRate=0; - priv->LastFailTxRateSS=0; - priv->FailTxRateCount=0; - priv->LastTxThroughput=0; - priv->NumTxOkBytesTotal=0; + priv->CurrRetryCnt = 0; + priv->LastRetryCnt = 0; + priv->LastTxokCnt = 0; + priv->LastRxokCnt = 0; + priv->LastRetryRate = 0; + priv->bTryuping = 0; + priv->CurrTxRate = 0; + priv->CurrRetryRate = 0; + priv->TryupingCount = 0; + priv->TryupingCountNoData = 0; + priv->TryDownCountLowData = 0; + priv->LastTxOKBytes = 0; + priv->LastFailTxRate = 0; + priv->LastFailTxRateSS = 0; + priv->FailTxRateCount = 0; + priv->LastTxThroughput = 0; + priv->NumTxOkBytesTotal = 0; priv->ForcedDataRate = 0; priv->RegBModeGainStage = 1; - priv->promisc = (dev->flags & IFF_PROMISC) ? 1:0; + priv->promisc = (dev->flags & IFF_PROMISC) ? 1 : 0; spin_lock_init(&priv->irq_lock); spin_lock_init(&priv->irq_th_lock); spin_lock_init(&priv->tx_lock); spin_lock_init(&priv->ps_lock); spin_lock_init(&priv->rf_ps_lock); - sema_init(&priv->wx_sem,1); - sema_init(&priv->rf_state,1); - INIT_WORK(&priv->reset_wq,(void*) rtl8180_restart_wq); - INIT_WORK(&priv->tx_irq_wq,(void*) rtl8180_tx_irq_wq); - INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8180_hw_wakeup_wq); - INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq,(void*) rtl8180_hw_sleep_wq); - INIT_WORK(&priv->ieee80211->wmm_param_update_wq,(void*) rtl8180_wmm_param_update); - INIT_DELAYED_WORK(&priv->ieee80211->rate_adapter_wq,(void*)rtl8180_rate_adapter);//+by amy 080312 - INIT_DELAYED_WORK(&priv->ieee80211->hw_dig_wq,(void*)rtl8180_hw_dig_wq);//+by amy 080312 - INIT_DELAYED_WORK(&priv->ieee80211->tx_pw_wq,(void*)rtl8180_tx_pw_wq);//+by amy 080312 - - INIT_DELAYED_WORK(&priv->ieee80211->GPIOChangeRFWorkItem,(void*) GPIOChangeRFWorkItemCallBack); - + sema_init(&priv->wx_sem, 1); + sema_init(&priv->rf_state, 1); + INIT_WORK(&priv->reset_wq, (void *)rtl8180_restart_wq); + INIT_WORK(&priv->tx_irq_wq, (void *)rtl8180_tx_irq_wq); + INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq, + (void *)rtl8180_hw_wakeup_wq); + INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq, + (void *)rtl8180_hw_sleep_wq); + INIT_WORK(&priv->ieee80211->wmm_param_update_wq, + (void *)rtl8180_wmm_param_update); + INIT_DELAYED_WORK(&priv->ieee80211->rate_adapter_wq, + (void *)rtl8180_rate_adapter); + INIT_DELAYED_WORK(&priv->ieee80211->hw_dig_wq, + (void *)rtl8180_hw_dig_wq); + INIT_DELAYED_WORK(&priv->ieee80211->tx_pw_wq, + (void *)rtl8180_tx_pw_wq); + INIT_DELAYED_WORK(&priv->ieee80211->GPIOChangeRFWorkItem, + (void *) GPIOChangeRFWorkItemCallBack); tasklet_init(&priv->irq_rx_tasklet, (void(*)(unsigned long)) rtl8180_irq_rx_tasklet, (unsigned long)priv); - init_timer(&priv->watch_dog_timer); + init_timer(&priv->watch_dog_timer); priv->watch_dog_timer.data = (unsigned long)dev; priv->watch_dog_timer.function = watch_dog_adaptive; - init_timer(&priv->rateadapter_timer); - priv->rateadapter_timer.data = (unsigned long)dev; - priv->rateadapter_timer.function = timer_rate_adaptive; - priv->RateAdaptivePeriod= RATE_ADAPTIVE_TIMER_PERIOD; - priv->bEnhanceTxPwr=false; + init_timer(&priv->rateadapter_timer); + priv->rateadapter_timer.data = (unsigned long)dev; + priv->rateadapter_timer.function = timer_rate_adaptive; + priv->RateAdaptivePeriod = RATE_ADAPTIVE_TIMER_PERIOD; + priv->bEnhanceTxPwr = false; priv->ieee80211->softmac_hard_start_xmit = rtl8180_hard_start_xmit; priv->ieee80211->set_chan = rtl8180_set_chan; @@ -2877,30 +2845,28 @@ short rtl8180_init(struct net_device *dev) priv->CSMethod = (0x01 << 29); - priv->TransmitConfig = - 1<ShortRetryLimit<LongRetryLimit<ReceiveConfig = - RCR_AMF | RCR_ADF | //accept management/data - RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko. - RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC - (7<EarlyRxThreshold<EarlyRxThreshold == 7 ? RCR_ONLYERLPKT:0); + priv->TransmitConfig = TCR_DurProcMode_OFFSET | + (7<ShortRetryLimit<LongRetryLimit<ReceiveConfig = RCR_AMF | RCR_ADF | RCR_ACF | + RCR_AB | RCR_AM | RCR_APM | + (7<EarlyRxThreshold<EarlyRxThreshold == 7 ? + RCR_ONLYERLPKT : 0); priv->IntrMask = IMR_TMGDOK | IMR_TBDER | IMR_THPDER | - IMR_THPDER | IMR_THPDOK | - IMR_TVODER | IMR_TVODOK | - IMR_TVIDER | IMR_TVIDOK | - IMR_TBEDER | IMR_TBEDOK | - IMR_TBKDER | IMR_TBKDOK | - IMR_RDU | // To handle the defragmentation not enough Rx descriptors case. Annie, 2006-03-27. - IMR_RER | IMR_ROK | - IMR_RQoSOK; // ROK and RQoSOK are mutually exclusive, so, we must handle RQoSOK interrupt to receive QoS frames, 2005.12.09, by rcnjko. + IMR_THPDER | IMR_THPDOK | + IMR_TVODER | IMR_TVODOK | + IMR_TVIDER | IMR_TVIDOK | + IMR_TBEDER | IMR_TBEDOK | + IMR_TBKDER | IMR_TBKDOK | + IMR_RDU | + IMR_RER | IMR_ROK | + IMR_RQoSOK; priv->InitialGain = 6; @@ -2968,25 +2934,22 @@ short rtl8180_init(struct net_device *dev) for (i = 1, j = 0; i < 14; i += 2, j++) { word = eprom_read(dev, EPROM_TXPW_OFDM_CH1_2 + j); priv->chtxpwr_ofdm[i] = word & 0xff; - priv->chtxpwr_ofdm[i+1] = (word & 0xff00)>>8; + priv->chtxpwr_ofdm[i+1] = (word & 0xff00) >> 8; } - //3Read crystal calibtration and thermal meter indication on 87SE. - - // By SD3 SY's request. Added by Roger, 2007.12.11. + /* 3Read crystal calibtration and thermal meter indication on 87SE. */ - tmpu16 = eprom_read(dev, EEPROM_RSV>>1); + tmpu16 = eprom_read(dev, EEPROM_RSV >> 1); + /* Crystal calibration for Xin and Xout resp. */ + priv->XtalCal_Xout = tmpu16 & EEPROM_XTAL_CAL_XOUT_MASK; + priv->XtalCal_Xin = (tmpu16 & EEPROM_XTAL_CAL_XIN_MASK) >> 4; + if ((tmpu16 & EEPROM_XTAL_CAL_ENABLE) >> 12) + priv->bXtalCalibration = true; - // Crystal calibration for Xin and Xout resp. - priv->XtalCal_Xout = tmpu16 & EEPROM_XTAL_CAL_XOUT_MASK; // 0~7.5pF - priv->XtalCal_Xin = (tmpu16 & EEPROM_XTAL_CAL_XIN_MASK)>>4; // 0~7.5pF - if((tmpu16 & EEPROM_XTAL_CAL_ENABLE)>>12) - priv->bXtalCalibration = true; - - // Thermal meter reference indication. - priv->ThermalMeter = (u8)((tmpu16 & EEPROM_THERMAL_METER_MASK)>>8); - if((tmpu16 & EEPROM_THERMAL_METER_ENABLE)>>13) - priv->bTxPowerTrack = true; + /* Thermal meter reference indication. */ + priv->ThermalMeter = (u8)((tmpu16 & EEPROM_THERMAL_METER_MASK) >> 8); + if ((tmpu16 & EEPROM_THERMAL_METER_ENABLE) >> 13) + priv->bTxPowerTrack = true; word = eprom_read(dev,EPROM_TXPW_BASE); priv->cck_txpwr_base = word & 0xf; @@ -3010,7 +2973,6 @@ short rtl8180_init(struct net_device *dev) priv->rf_set_chan = rtl8225z2_rf_set_chan; priv->rf_set_sens = NULL; - if (0!=alloc_rx_desc_ring(dev, priv->rxbuffersize, priv->rxringcount)) return -ENOMEM; @@ -3042,11 +3004,7 @@ short rtl8180_init(struct net_device *dev) TX_BEACON_RING_ADDR)) return -ENOMEM; -#if !defined(SA_SHIRQ) if(request_irq(dev->irq, (void *)rtl8180_interrupt, IRQF_SHARED, dev->name, dev)){ -#else - if(request_irq(dev->irq, (void *)rtl8180_interrupt, SA_SHIRQ, dev->name, dev)){ -#endif DMESGE("Error allocating IRQ %d",dev->irq); return -1; }else{ @@ -3335,7 +3293,6 @@ static struct net_device_stats *rtl8180_stats(struct net_device *dev) } // // Change current and default preamble mode. -// 2005.01.06, by rcnjko. // bool MgntActSet_802_11_PowerSaveMode( @@ -3454,7 +3411,6 @@ void rtl8180_watch_dog(struct net_device *dev) MgntLinkKeepAlive(priv); //YJ,add,080828,for LPS -#ifdef ENABLE_LPS if (priv->PowerProfile == POWER_PROFILE_BATTERY) priv->bLeisurePs = true; else if (priv->PowerProfile == POWER_PROFILE_AC) { @@ -3464,7 +3420,6 @@ void rtl8180_watch_dog(struct net_device *dev) if(priv->ieee80211->state == IEEE80211_LINKED){ priv->link_detect.NumRxOkInPeriod = priv->ieee80211->NumRxDataInPeriod; - //printk("TxOk=%d RxOk=%d\n", priv->link_detect.NumTxOkInPeriod, priv->link_detect.NumRxOkInPeriod); if( priv->link_detect.NumRxOkInPeriod> 666 || priv->link_detect.NumTxOkInPeriod> 666 ) { bBusyTraffic = true; @@ -3481,7 +3436,6 @@ void rtl8180_watch_dog(struct net_device *dev) LeisurePSLeave(priv); } else LeisurePSLeave(priv); -#endif priv->link_detect.bBusyTraffic = bBusyTraffic; priv->link_detect.NumRxOkInPeriod = 0; priv->link_detect.NumTxOkInPeriod = 0; @@ -3503,16 +3457,11 @@ int _rtl8180_up(struct net_device *dev) if(priv->ieee80211->iw_mode == IW_MODE_ADHOC) IPSLeave(dev); } -#ifdef RATE_ADAPT timer_rate_adaptive((unsigned long)dev); -#endif watch_dog_adaptive((unsigned long)dev); -#ifdef SW_ANTE if(priv->bSwAntennaDiverity) SwAntennaDiversityTimerCallback(dev); -#endif ieee80211_softmac_start_protocol(priv->ieee80211); - return 0; } @@ -3748,7 +3697,7 @@ static int __devinit rtl8180_pci_probe(struct pci_dev *pdev, dev->wireless_handlers = &r8180_wx_handlers_def; dev->type=ARPHRD_ETHER; - dev->watchdog_timeo = HZ*3; //added by david woo, 2007.12.13 + dev->watchdog_timeo = HZ*3; if (dev_alloc_name(dev, ifname) < 0){ DMESG("Oops: devname already taken! Trying wlan%%d...\n"); @@ -4236,60 +4185,50 @@ void GPIOChangeRFWorkItemCallBack(struct work_struct *work) static char *envp[] = {"HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL}; static int readf_count = 0; -#ifdef ENABLE_LPS if(readf_count % 10 == 0) priv->PowerProfile = read_acadapter_file("/proc/acpi/ac_adapter/AC0/state"); readf_count = (readf_count+1)%0xffff; -#endif - { - // We should turn off LED before polling FF51[4]. + /* We should turn off LED before polling FF51[4]. */ - //Turn off LED. - btPSR = read_nic_byte(dev, PSR); - write_nic_byte(dev, PSR, (btPSR & ~BIT3)); + /* Turn off LED. */ + btPSR = read_nic_byte(dev, PSR); + write_nic_byte(dev, PSR, (btPSR & ~BIT3)); - //It need to delay 4us suggested by Jong, 2008-01-16 - udelay(4); + /* It need to delay 4us suggested by Jong, 2008-01-16 */ + udelay(4); - //HW radio On/Off according to the value of FF51[4](config0) - btConfig0 = btPSR = read_nic_byte(dev, CONFIG0); + /* HW radio On/Off according to the value of FF51[4](config0) */ + btConfig0 = btPSR = read_nic_byte(dev, CONFIG0); - //Turn on LED. - write_nic_byte(dev, PSR, btPSR| BIT3); + /* Turn on LED. */ + write_nic_byte(dev, PSR, btPSR | BIT3); - eRfPowerStateToSet = (btConfig0 & BIT4) ? eRfOn : eRfOff; + eRfPowerStateToSet = (btConfig0 & BIT4) ? eRfOn : eRfOff; - if((priv->ieee80211->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn)) - { - priv->ieee80211->bHwRadioOff = false; - bActuallySet = true; - } - else if((priv->ieee80211->bHwRadioOff == false) && (eRfPowerStateToSet == eRfOff)) - { - priv->ieee80211->bHwRadioOff = true; - bActuallySet = true; - } + if ((priv->ieee80211->bHwRadioOff == true) && + (eRfPowerStateToSet == eRfOn)) { + priv->ieee80211->bHwRadioOff = false; + bActuallySet = true; + } else if ((priv->ieee80211->bHwRadioOff == false) && + (eRfPowerStateToSet == eRfOff)) { + priv->ieee80211->bHwRadioOff = true; + bActuallySet = true; + } - if(bActuallySet) - { - MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW); - - /* To update the UI status for Power status changed */ - if(priv->ieee80211->bHwRadioOff == true) - argv[1] = "RFOFF"; - else{ - //if(!priv->RfOffReason) - argv[1] = "RFON"; - //else - // argv[1] = "RFOFF"; - } - argv[0] = RadioPowerPath; - argv[2] = NULL; - - call_usermodehelper(RadioPowerPath,argv,envp,1); - } - } + if (bActuallySet) { + MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW); + + /* To update the UI status for Power status changed */ + if (priv->ieee80211->bHwRadioOff == true) + argv[1] = "RFOFF"; + else + argv[1] = "RFON"; + argv[0] = RadioPowerPath; + argv[2] = NULL; + + call_usermodehelper(RadioPowerPath, argv, envp, 1); + } } static u8 read_acadapter_file(char *filename) -- cgit v1.2.3 From 6a90772886d5d6812f9b2775d3caa0dc002754e0 Mon Sep 17 00:00:00 2001 From: Nitin Gupta Date: Thu, 28 Jan 2010 21:13:37 +0530 Subject: Staging: ramzswap: Use lock for 64-bit stats 64-bit stats corruption was observed when ramzswap was used on SMP systems. To prevent this, use separate spinlock to protect these stats. Also, replace stat_*() with rzs_stat*() to avoid possible conflict with core kernel code. Eventually, these will be converted to per-cpu counters if this driver finds use on large scale systems and this locking is found to affect scalability. Signed-off-by: Nitin Gupta Signed-off-by: Greg Kroah-Hartman --- drivers/staging/ramzswap/ramzswap_drv.c | 58 +++++++++++++++--------------- drivers/staging/ramzswap/ramzswap_drv.h | 59 +++++++++++++++++++++++++------ drivers/staging/ramzswap/ramzswap_ioctl.h | 1 + 3 files changed, 80 insertions(+), 38 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/ramzswap/ramzswap_drv.c b/drivers/staging/ramzswap/ramzswap_drv.c index baf757259d0b..05273c0588c6 100644 --- a/drivers/staging/ramzswap/ramzswap_drv.c +++ b/drivers/staging/ramzswap/ramzswap_drv.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -239,7 +238,8 @@ void ramzswap_ioctl_get_stats(struct ramzswap *rzs, mem_used = xv_get_total_size_bytes(rzs->mem_pool) + (rs->pages_expand << PAGE_SHIFT); - succ_writes = rs->num_writes - rs->failed_writes; + succ_writes = rzs_stat64_read(rzs, &rs->num_writes) - + rzs_stat64_read(rzs, &rs->failed_writes); if (succ_writes && rs->pages_stored) { good_compress_perc = rs->good_compress * 100 @@ -248,11 +248,12 @@ void ramzswap_ioctl_get_stats(struct ramzswap *rzs, / rs->pages_stored; } - s->num_reads = rs->num_reads; - s->num_writes = rs->num_writes; - s->failed_reads = rs->failed_reads; - s->failed_writes = rs->failed_writes; - s->invalid_io = rs->invalid_io; + s->num_reads = rzs_stat64_read(rzs, &rs->num_reads); + s->num_writes = rzs_stat64_read(rzs, &rs->num_writes); + s->failed_reads = rzs_stat64_read(rzs, &rs->failed_reads); + s->failed_writes = rzs_stat64_read(rzs, &rs->failed_writes); + s->invalid_io = rzs_stat64_read(rzs, &rs->invalid_io); + s->notify_free = rzs_stat64_read(rzs, &rs->notify_free); s->pages_zero = rs->pages_zero; s->good_compress_pct = good_compress_perc; @@ -264,8 +265,8 @@ void ramzswap_ioctl_get_stats(struct ramzswap *rzs, s->compr_data_size = rs->compr_size; s->mem_used_total = mem_used; - s->bdev_num_reads = rs->bdev_num_reads; - s->bdev_num_writes = rs->bdev_num_writes; + s->bdev_num_reads = rzs_stat64_read(rzs, &rs->bdev_num_reads); + s->bdev_num_writes = rzs_stat64_read(rzs, &rs->bdev_num_writes); } #endif /* CONFIG_RAMZSWAP_STATS */ } @@ -594,7 +595,7 @@ static void ramzswap_free_page(struct ramzswap *rzs, size_t index) if (unlikely(!page)) { if (rzs_test_flag(rzs, index, RZS_ZERO)) { rzs_clear_flag(rzs, index, RZS_ZERO); - stat_dec(rzs->stats.pages_zero); + rzs_stat_dec(&rzs->stats.pages_zero); } return; } @@ -603,7 +604,7 @@ static void ramzswap_free_page(struct ramzswap *rzs, size_t index) clen = PAGE_SIZE; __free_page(page); rzs_clear_flag(rzs, index, RZS_UNCOMPRESSED); - stat_dec(rzs->stats.pages_expand); + rzs_stat_dec(&rzs->stats.pages_expand); goto out; } @@ -613,11 +614,11 @@ static void ramzswap_free_page(struct ramzswap *rzs, size_t index) xv_free(rzs->mem_pool, page, offset); if (clen <= PAGE_SIZE / 2) - stat_dec(rzs->stats.good_compress); + rzs_stat_dec(&rzs->stats.good_compress); out: rzs->stats.compr_size -= clen; - stat_dec(rzs->stats.pages_stored); + rzs_stat_dec(&rzs->stats.pages_stored); rzs->table[index].page = NULL; rzs->table[index].offset = 0; @@ -679,8 +680,8 @@ static int handle_ramzswap_fault(struct ramzswap *rzs, struct bio *bio) */ if (rzs->backing_swap) { u32 pagenum; - stat_dec(rzs->stats.num_reads); - stat_inc(rzs->stats.bdev_num_reads); + rzs_stat64_dec(rzs, &rzs->stats.num_reads); + rzs_stat64_inc(rzs, &rzs->stats.bdev_num_reads); bio->bi_bdev = rzs->backing_swap; /* @@ -718,7 +719,7 @@ static int ramzswap_read(struct ramzswap *rzs, struct bio *bio) struct zobj_header *zheader; unsigned char *user_mem, *cmem; - stat_inc(rzs->stats.num_reads); + rzs_stat64_inc(rzs, &rzs->stats.num_reads); page = bio->bi_io_vec[0].bv_page; index = bio->bi_sector >> SECTORS_PER_PAGE_SHIFT; @@ -752,7 +753,7 @@ static int ramzswap_read(struct ramzswap *rzs, struct bio *bio) if (unlikely(ret != LZO_E_OK)) { pr_err("Decompression failed! err=%d, page=%u\n", ret, index); - stat_inc(rzs->stats.failed_reads); + rzs_stat64_inc(rzs, &rzs->stats.failed_reads); goto out; } @@ -776,7 +777,7 @@ static int ramzswap_write(struct ramzswap *rzs, struct bio *bio) struct page *page, *page_store; unsigned char *user_mem, *cmem, *src; - stat_inc(rzs->stats.num_writes); + rzs_stat64_inc(rzs, &rzs->stats.num_writes); page = bio->bi_io_vec[0].bv_page; index = bio->bi_sector >> SECTORS_PER_PAGE_SHIFT; @@ -796,7 +797,7 @@ static int ramzswap_write(struct ramzswap *rzs, struct bio *bio) * Simply clear zero page flag. */ if (rzs_test_flag(rzs, index, RZS_ZERO)) { - stat_dec(rzs->stats.pages_zero); + rzs_stat_dec(&rzs->stats.pages_zero); rzs_clear_flag(rzs, index, RZS_ZERO); } @@ -806,7 +807,7 @@ static int ramzswap_write(struct ramzswap *rzs, struct bio *bio) if (page_zero_filled(user_mem)) { kunmap_atomic(user_mem, KM_USER0); mutex_unlock(&rzs->lock); - stat_inc(rzs->stats.pages_zero); + rzs_stat_inc(&rzs->stats.pages_zero); rzs_set_flag(rzs, index, RZS_ZERO); set_bit(BIO_UPTODATE, &bio->bi_flags); @@ -830,7 +831,7 @@ static int ramzswap_write(struct ramzswap *rzs, struct bio *bio) if (unlikely(ret != LZO_E_OK)) { mutex_unlock(&rzs->lock); pr_err("Compression failed! err=%d\n", ret); - stat_inc(rzs->stats.failed_writes); + rzs_stat64_inc(rzs, &rzs->stats.failed_writes); goto out; } @@ -853,13 +854,13 @@ static int ramzswap_write(struct ramzswap *rzs, struct bio *bio) mutex_unlock(&rzs->lock); pr_info("Error allocating memory for incompressible " "page: %u\n", index); - stat_inc(rzs->stats.failed_writes); + rzs_stat64_inc(rzs, &rzs->stats.failed_writes); goto out; } offset = 0; rzs_set_flag(rzs, index, RZS_UNCOMPRESSED); - stat_inc(rzs->stats.pages_expand); + rzs_stat_inc(&rzs->stats.pages_expand); rzs->table[index].page = page_store; src = kmap_atomic(page, KM_USER0); goto memstore; @@ -871,7 +872,7 @@ static int ramzswap_write(struct ramzswap *rzs, struct bio *bio) mutex_unlock(&rzs->lock); pr_info("Error allocating memory for compressed " "page: %u, size=%zu\n", index, clen); - stat_inc(rzs->stats.failed_writes); + rzs_stat64_inc(rzs, &rzs->stats.failed_writes); if (rzs->backing_swap) fwd_write_request = 1; goto out; @@ -900,9 +901,9 @@ memstore: /* Update stats */ rzs->stats.compr_size += clen; - stat_inc(rzs->stats.pages_stored); + rzs_stat_inc(&rzs->stats.pages_stored); if (clen <= PAGE_SIZE / 2) - stat_inc(rzs->stats.good_compress); + rzs_stat_inc(&rzs->stats.good_compress); mutex_unlock(&rzs->lock); @@ -912,7 +913,7 @@ memstore: out: if (fwd_write_request) { - stat_inc(rzs->stats.bdev_num_writes); + rzs_stat64_inc(rzs, &rzs->stats.bdev_num_writes); bio->bi_bdev = rzs->backing_swap; #if 0 /* @@ -974,7 +975,7 @@ static int ramzswap_make_request(struct request_queue *queue, struct bio *bio) } if (!valid_swap_request(rzs, bio)) { - stat_inc(rzs->stats.invalid_io); + rzs_stat64_inc(rzs, &rzs->stats.invalid_io); bio_io_error(bio); return 0; } @@ -1295,6 +1296,7 @@ static struct block_device_operations ramzswap_devops = { static int create_device(struct ramzswap *rzs, int device_id) { mutex_init(&rzs->lock); + spin_lock_init(&rzs->stat64_lock); INIT_LIST_HEAD(&rzs->backing_swap_extent_list); rzs->queue = blk_alloc_queue(GFP_KERNEL); diff --git a/drivers/staging/ramzswap/ramzswap_drv.h b/drivers/staging/ramzswap/ramzswap_drv.h index 7ba98bfee2d6..5b672225e174 100644 --- a/drivers/staging/ramzswap/ramzswap_drv.h +++ b/drivers/staging/ramzswap/ramzswap_drv.h @@ -15,6 +15,9 @@ #ifndef _RAMZSWAP_DRV_H_ #define _RAMZSWAP_DRV_H_ +#include +#include + #include "ramzswap_ioctl.h" #include "xvmalloc.h" @@ -71,15 +74,6 @@ static const unsigned max_zpage_size_nobdev = PAGE_SIZE / 4 * 3; #define SECTORS_PER_PAGE_SHIFT (PAGE_SHIFT - SECTOR_SHIFT) #define SECTORS_PER_PAGE (1 << SECTORS_PER_PAGE_SHIFT) -/* Debugging and Stats */ -#if defined(CONFIG_RAMZSWAP_STATS) -#define stat_inc(stat) ((stat)++) -#define stat_dec(stat) ((stat)--) -#else -#define stat_inc(x) -#define stat_dec(x) -#endif - /* Flags for ramzswap pages (table[page_no].flags) */ enum rzs_pageflags { /* Page is stored uncompressed */ @@ -124,6 +118,7 @@ struct ramzswap_stats { u64 failed_reads; /* should NEVER! happen */ u64 failed_writes; /* can happen when memory is too low */ u64 invalid_io; /* non-swap I/O requests */ + u64 notify_free; /* no. of swap slot free notifications */ u32 pages_zero; /* no. of zero filled pages */ u32 pages_stored; /* no. of pages currently stored */ u32 good_compress; /* % of pages with compression ratio<=50% */ @@ -138,6 +133,7 @@ struct ramzswap { void *compress_workmem; void *compress_buffer; struct table *table; + spinlock_t stat64_lock; /* protect 64-bit stats */ struct mutex lock; struct request_queue *queue; struct gendisk *disk; @@ -167,5 +163,48 @@ struct ramzswap { /*-- */ -#endif +/* Debugging and Stats */ +#if defined(CONFIG_RAMZSWAP_STATS) +static void rzs_stat_inc(u32 *v) +{ + *v = *v + 1; +} + +static void rzs_stat_dec(u32 *v) +{ + *v = *v - 1; +} + +static void rzs_stat64_inc(struct ramzswap *rzs, u64 *v) +{ + spin_lock(&rzs->stat64_lock); + *v = *v + 1; + spin_unlock(&rzs->stat64_lock); +} + +static void rzs_stat64_dec(struct ramzswap *rzs, u64 *v) +{ + spin_lock(&rzs->stat64_lock); + *v = *v - 1; + spin_unlock(&rzs->stat64_lock); +} + +static u64 rzs_stat64_read(struct ramzswap *rzs, u64 *v) +{ + u64 val; + + spin_lock(&rzs->stat64_lock); + val = *v; + spin_unlock(&rzs->stat64_lock); + + return val; +} +#else +#define rzs_stat_inc(v) +#define rzs_stat_dec(v) +#define rzs_stat64_inc(r, v) +#define rzs_stat64_dec(r, v) +#define rzs_stat64_read(r, v) +#endif /* CONFIG_RAMZSWAP_STATS */ +#endif diff --git a/drivers/staging/ramzswap/ramzswap_ioctl.h b/drivers/staging/ramzswap/ramzswap_ioctl.h index 1bc54e22c915..1edaebaaf81d 100644 --- a/drivers/staging/ramzswap/ramzswap_ioctl.h +++ b/drivers/staging/ramzswap/ramzswap_ioctl.h @@ -27,6 +27,7 @@ struct ramzswap_ioctl_stats { u64 failed_reads; /* should NEVER! happen */ u64 failed_writes; /* can happen when memory is too low */ u64 invalid_io; /* non-swap I/O requests */ + u64 notify_free; /* no. of swap slot free notifications */ u32 pages_zero; /* no. of zero filled pages */ u32 good_compress_pct; /* no. of pages with compression ratio<=50% */ u32 pages_expand_pct; /* no. of incompressible pages */ -- cgit v1.2.3 From 7eef7533909f3ea50e8b375777242f778e8da11e Mon Sep 17 00:00:00 2001 From: Nitin Gupta Date: Thu, 28 Jan 2010 21:13:38 +0530 Subject: Staging: ramzswap: Flush block device before reset Make sure we flush block device before freeing all metadata during reset ioctl. Signed-off-by: Nitin Gupta Signed-off-by: Greg Kroah-Hartman --- drivers/staging/ramzswap/ramzswap_drv.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/ramzswap/ramzswap_drv.c b/drivers/staging/ramzswap/ramzswap_drv.c index 05273c0588c6..3567ee3991bd 100644 --- a/drivers/staging/ramzswap/ramzswap_drv.c +++ b/drivers/staging/ramzswap/ramzswap_drv.c @@ -1000,6 +1000,9 @@ static void reset_device(struct ramzswap *rzs) unsigned entries_per_page; unsigned long num_table_pages, entry = 0; + /* Do not accept any new I/O request */ + rzs->init_done = 0; + if (rzs->backing_swap && !rzs->num_extents) is_backing_blkdev = 1; @@ -1073,9 +1076,6 @@ static void reset_device(struct ramzswap *rzs) rzs->disksize = 0; rzs->memlimit = 0; - - /* Back to uninitialized state */ - rzs->init_done = 0; } static int ramzswap_ioctl_init_device(struct ramzswap *rzs) @@ -1276,6 +1276,11 @@ static int ramzswap_ioctl(struct block_device *bdev, fmode_t mode, ret = -EBUSY; goto out; } + + /* Make sure all pending I/O is finished */ + if (bdev) + fsync_bdev(bdev); + ret = ramzswap_ioctl_reset_device(rzs); break; -- cgit v1.2.3 From 5d83d5a0b5ee332b724978d657c0af17f14e807e Mon Sep 17 00:00:00 2001 From: Nitin Gupta Date: Thu, 28 Jan 2010 21:13:39 +0530 Subject: Staging: ramzswap: Set block size to PAGE_SIZE ramzswap block size needs to be set equal to PAGE_SIZE to avoid receiving any unaligned block I/O requests (happens due to readahead logic during swapon). These unaligned accesses produce unnecessary I/O errors, scaring users. Signed-off-by: Nitin Gupta Signed-off-by: Greg Kroah-Hartman --- drivers/staging/ramzswap/ramzswap_drv.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/ramzswap/ramzswap_drv.c b/drivers/staging/ramzswap/ramzswap_drv.c index 3567ee3991bd..2021ad6fb013 100644 --- a/drivers/staging/ramzswap/ramzswap_drv.c +++ b/drivers/staging/ramzswap/ramzswap_drv.c @@ -1335,6 +1335,10 @@ static int create_device(struct ramzswap *rzs, int device_id) * or set equal to backing swap device (if provided) */ set_capacity(rzs->disk, 0); + + blk_queue_physical_block_size(rzs->disk->queue, PAGE_SIZE); + blk_queue_logical_block_size(rzs->disk->queue, PAGE_SIZE); + add_disk(rzs->disk); rzs->init_done = 0; -- cgit v1.2.3 From de1a21a0f1f614dac0d8cacc13f41e32a15bba98 Mon Sep 17 00:00:00 2001 From: Nitin Gupta Date: Thu, 28 Jan 2010 21:13:40 +0530 Subject: Staging: ramzswap: Return proper error code on device create failure Currently, we return 0 if create_device() fails and 1 otherwise. Now, proper error code is returned from create_device() and the same is propagated as module error code from ramzswap_init(). Also added some cleanups for ramzswap_init(), improving function structure. Signed-off-by: Nitin Gupta Signed-off-by: Greg Kroah-Hartman --- drivers/staging/ramzswap/ramzswap_drv.c | 44 +++++++++++++++++++++------------ 1 file changed, 28 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/ramzswap/ramzswap_drv.c b/drivers/staging/ramzswap/ramzswap_drv.c index 2021ad6fb013..3035addfaedd 100644 --- a/drivers/staging/ramzswap/ramzswap_drv.c +++ b/drivers/staging/ramzswap/ramzswap_drv.c @@ -1300,6 +1300,8 @@ static struct block_device_operations ramzswap_devops = { static int create_device(struct ramzswap *rzs, int device_id) { + int ret = 0; + mutex_init(&rzs->lock); spin_lock_init(&rzs->stat64_lock); INIT_LIST_HEAD(&rzs->backing_swap_extent_list); @@ -1308,7 +1310,8 @@ static int create_device(struct ramzswap *rzs, int device_id) if (!rzs->queue) { pr_err("Error allocating disk queue for device %d\n", device_id); - return 0; + ret = -ENOMEM; + goto out; } blk_queue_make_request(rzs->queue, ramzswap_make_request); @@ -1320,7 +1323,8 @@ static int create_device(struct ramzswap *rzs, int device_id) blk_cleanup_queue(rzs->queue); pr_warning("Error allocating disk structure for device %d\n", device_id); - return 0; + ret = -ENOMEM; + goto out; } rzs->disk->major = ramzswap_major; @@ -1342,7 +1346,9 @@ static int create_device(struct ramzswap *rzs, int device_id) add_disk(rzs->disk); rzs->init_done = 0; - return 1; + +out: + return ret; } static void destroy_device(struct ramzswap *rzs) @@ -1358,18 +1364,20 @@ static void destroy_device(struct ramzswap *rzs) static int __init ramzswap_init(void) { - int i, ret; + int ret, dev_id; if (num_devices > max_num_devices) { pr_warning("Invalid value for num_devices: %u\n", num_devices); - return -EINVAL; + ret = -EINVAL; + goto out; } ramzswap_major = register_blkdev(0, "ramzswap"); if (ramzswap_major <= 0) { pr_warning("Unable to get major number\n"); - return -EBUSY; + ret = -EBUSY; + goto out; } if (!num_devices) { @@ -1380,21 +1388,25 @@ static int __init ramzswap_init(void) /* Allocate the device array and initialize each one */ pr_info("Creating %u devices ...\n", num_devices); devices = kzalloc(num_devices * sizeof(struct ramzswap), GFP_KERNEL); - if (!devices) - goto out; + if (!devices) { + ret = -ENOMEM; + goto unregister; + } - for (i = 0; i < num_devices; i++) - if (!create_device(&devices[i], i)) { - ret = i; + for (dev_id = 0; dev_id < num_devices; dev_id++) { + ret = create_device(&devices[dev_id], dev_id); + if (ret) goto free_devices; - } + } + return 0; + free_devices: - for (i = 0; i < ret; i++) - destroy_device(&devices[i]); -out: - ret = -ENOMEM; + while (dev_id) + destroy_device(&devices[--dev_id]); +unregister: unregister_blkdev(ramzswap_major, "ramzswap"); +out: return ret; } -- cgit v1.2.3 From 2e882281742f7e483e751bbbaf6c0946b5f8513f Mon Sep 17 00:00:00 2001 From: Nitin Gupta Date: Thu, 28 Jan 2010 21:13:41 +0530 Subject: Staging: ramzswap: Remove redundant check for zero page ramzswap_free_page() already handles the case for zero filled pages. So, remove redundant logic for the same in ramzswap_write(). Signed-off-by: Nitin Gupta Signed-off-by: Greg Kroah-Hartman --- drivers/staging/ramzswap/ramzswap_drv.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/ramzswap/ramzswap_drv.c b/drivers/staging/ramzswap/ramzswap_drv.c index 3035addfaedd..7e0a3fab9cd4 100644 --- a/drivers/staging/ramzswap/ramzswap_drv.c +++ b/drivers/staging/ramzswap/ramzswap_drv.c @@ -593,6 +593,10 @@ static void ramzswap_free_page(struct ramzswap *rzs, size_t index) u32 offset = rzs->table[index].offset; if (unlikely(!page)) { + /* + * No memory is allocated for zero filled pages. + * Simply clear zero page flag. + */ if (rzs_test_flag(rzs, index, RZS_ZERO)) { rzs_clear_flag(rzs, index, RZS_ZERO); rzs_stat_dec(&rzs->stats.pages_zero); @@ -789,18 +793,9 @@ static int ramzswap_write(struct ramzswap *rzs, struct bio *bio) * is no longer referenced by any process. So, its now safe * to free the memory that was allocated for this page. */ - if (rzs->table[index].page) + if (rzs->table[index].page || rzs_test_flag(rzs, index, RZS_ZERO)) ramzswap_free_page(rzs, index); - /* - * No memory is allocated for zero filled pages. - * Simply clear zero page flag. - */ - if (rzs_test_flag(rzs, index, RZS_ZERO)) { - rzs_stat_dec(&rzs->stats.pages_zero); - rzs_clear_flag(rzs, index, RZS_ZERO); - } - mutex_lock(&rzs->lock); user_mem = kmap_atomic(page, KM_USER0); -- cgit v1.2.3 From c25d75a234df36446dc0d9bb3365ab8b83374d50 Mon Sep 17 00:00:00 2001 From: Nitin Gupta Date: Thu, 28 Jan 2010 21:19:59 +0530 Subject: Staging: ramzswap: Handle case for invalid backing swap Currently, we crash (issue BUG_ON) if backing swap disk size is zero. This can happen is user specified an extended partition or simply a bad disk as backing swap. A crash is really an unpleasant surprise to user for such trivial problems. Now, we check for this condition and simply fail device initialization if this is the case. Additional cleanups: * use static for all functions * remove extra newline between functions * memset backing_swap_name to NULL on device reset Signed-off-by: Nitin Gupta Signed-off-by: Greg Kroah-Hartman --- drivers/staging/ramzswap/ramzswap_drv.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/ramzswap/ramzswap_drv.c b/drivers/staging/ramzswap/ramzswap_drv.c index 7e0a3fab9cd4..1bca069211a8 100644 --- a/drivers/staging/ramzswap/ramzswap_drv.c +++ b/drivers/staging/ramzswap/ramzswap_drv.c @@ -220,7 +220,7 @@ out: return ret; } -void ramzswap_ioctl_get_stats(struct ramzswap *rzs, +static void ramzswap_ioctl_get_stats(struct ramzswap *rzs, struct ramzswap_ioctl_stats *s) { strncpy(s->backing_swap_name, rzs->backing_swap_name, @@ -502,6 +502,14 @@ static int setup_backing_swap(struct ramzswap *rzs) goto bad_param; } disksize = i_size_read(inode); + /* + * Can happen if user gives an extended partition as + * backing swap or simply a bad disk. + */ + if (!disksize) { + pr_err("Error reading backing swap size.\n"); + goto bad_param; + } } else if (S_ISREG(inode->i_mode)) { bdev = inode->i_sb->s_bdev; if (IS_SWAPFILE(inode)) { @@ -519,7 +527,6 @@ static int setup_backing_swap(struct ramzswap *rzs) rzs->swap_file = swap_file; rzs->backing_swap = bdev; rzs->disksize = disksize; - BUG_ON(!rzs->disksize); return 0; @@ -537,7 +544,7 @@ out: * Map logical page number 'pagenum' to physical page number * on backing swap device. For block device, this is a nop. */ -u32 map_backing_swap_page(struct ramzswap *rzs, u32 pagenum) +static u32 map_backing_swap_page(struct ramzswap *rzs, u32 pagenum) { u32 skip_pages, entries_per_page; size_t delta, se_offset, skipped; @@ -668,7 +675,6 @@ static int handle_uncompressed_page(struct ramzswap *rzs, struct bio *bio) return 0; } - /* * Called when request page is not present in ramzswap. * Its either in backing swap device (if present) or @@ -936,7 +942,6 @@ out: return 0; } - /* * Check if request is within bounds and page aligned. */ @@ -1064,6 +1069,7 @@ static void reset_device(struct ramzswap *rzs) bd_release(rzs->backing_swap); filp_close(rzs->swap_file, NULL); rzs->backing_swap = NULL; + memset(rzs->backing_swap_name, 0, MAX_SWAP_NAME_LEN); } /* Reset stats */ -- cgit v1.2.3 From 1130ebbaae8ed0dcf8be707449601f8d7dbb7538 Mon Sep 17 00:00:00 2001 From: Nitin Gupta Date: Thu, 28 Jan 2010 21:21:35 +0530 Subject: Staging: ramzswap: Update copyright notice Update copyright notice. Signed-off-by: Nitin Gupta Signed-off-by: Greg Kroah-Hartman --- drivers/staging/ramzswap/ramzswap_drv.c | 2 +- drivers/staging/ramzswap/ramzswap_drv.h | 2 +- drivers/staging/ramzswap/ramzswap_ioctl.h | 2 +- drivers/staging/ramzswap/xvmalloc.c | 2 +- drivers/staging/ramzswap/xvmalloc.h | 2 +- drivers/staging/ramzswap/xvmalloc_int.h | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/ramzswap/ramzswap_drv.c b/drivers/staging/ramzswap/ramzswap_drv.c index 1bca069211a8..5e422e254ee8 100644 --- a/drivers/staging/ramzswap/ramzswap_drv.c +++ b/drivers/staging/ramzswap/ramzswap_drv.c @@ -1,7 +1,7 @@ /* * Compressed RAM based swap device * - * Copyright (C) 2008, 2009 Nitin Gupta + * Copyright (C) 2008, 2009, 2010 Nitin Gupta * * This code is released using a dual license strategy: BSD/GPL * You can choose the licence that better fits your requirements. diff --git a/drivers/staging/ramzswap/ramzswap_drv.h b/drivers/staging/ramzswap/ramzswap_drv.h index 5b672225e174..c7e0e767c223 100644 --- a/drivers/staging/ramzswap/ramzswap_drv.h +++ b/drivers/staging/ramzswap/ramzswap_drv.h @@ -1,7 +1,7 @@ /* * Compressed RAM based swap device * - * Copyright (C) 2008, 2009 Nitin Gupta + * Copyright (C) 2008, 2009, 2010 Nitin Gupta * * This code is released using a dual license strategy: BSD/GPL * You can choose the licence that better fits your requirements. diff --git a/drivers/staging/ramzswap/ramzswap_ioctl.h b/drivers/staging/ramzswap/ramzswap_ioctl.h index 1edaebaaf81d..d26076d41bde 100644 --- a/drivers/staging/ramzswap/ramzswap_ioctl.h +++ b/drivers/staging/ramzswap/ramzswap_ioctl.h @@ -1,7 +1,7 @@ /* * Compressed RAM based swap device * - * Copyright (C) 2008, 2009 Nitin Gupta + * Copyright (C) 2008, 2009, 2010 Nitin Gupta * * This code is released using a dual license strategy: BSD/GPL * You can choose the licence that better fits your requirements. diff --git a/drivers/staging/ramzswap/xvmalloc.c b/drivers/staging/ramzswap/xvmalloc.c index dabd266a427b..3fdbb8ada827 100644 --- a/drivers/staging/ramzswap/xvmalloc.c +++ b/drivers/staging/ramzswap/xvmalloc.c @@ -1,7 +1,7 @@ /* * xvmalloc memory allocator * - * Copyright (C) 2008, 2009 Nitin Gupta + * Copyright (C) 2008, 2009, 2010 Nitin Gupta * * This code is released using a dual license strategy: BSD/GPL * You can choose the licence that better fits your requirements. diff --git a/drivers/staging/ramzswap/xvmalloc.h b/drivers/staging/ramzswap/xvmalloc.h index 010c6fe5e173..5b1a81aa5faf 100644 --- a/drivers/staging/ramzswap/xvmalloc.h +++ b/drivers/staging/ramzswap/xvmalloc.h @@ -1,7 +1,7 @@ /* * xvmalloc memory allocator * - * Copyright (C) 2008, 2009 Nitin Gupta + * Copyright (C) 2008, 2009, 2010 Nitin Gupta * * This code is released using a dual license strategy: BSD/GPL * You can choose the licence that better fits your requirements. diff --git a/drivers/staging/ramzswap/xvmalloc_int.h b/drivers/staging/ramzswap/xvmalloc_int.h index 263c72d1fb3d..e23ed5c8b8e4 100644 --- a/drivers/staging/ramzswap/xvmalloc_int.h +++ b/drivers/staging/ramzswap/xvmalloc_int.h @@ -1,7 +1,7 @@ /* * xvmalloc memory allocator * - * Copyright (C) 2008, 2009 Nitin Gupta + * Copyright (C) 2008, 2009, 2010 Nitin Gupta * * This code is released using a dual license strategy: BSD/GPL * You can choose the licence that better fits your requirements. -- cgit v1.2.3 From 50ae2a521f60a62dce3fedfc3046064a680a6d5e Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Fri, 29 Jan 2010 00:16:19 +0100 Subject: Staging: comedi: pcm3724: Checkpatch cleanups This fixes all checkpatch issues in the pcm3724 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcm3724.c | 85 +++++++++++++++----------------- 1 file changed, 40 insertions(+), 45 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcm3724.c b/drivers/staging/comedi/drivers/pcm3724.c index 52811824b05a..ed6103079232 100644 --- a/drivers/staging/comedi/drivers/pcm3724.c +++ b/drivers/staging/comedi/drivers/pcm3724.c @@ -121,25 +121,22 @@ static int compute_buffer(int config, int devno, struct comedi_subdevice *s) { /* 1 in io_bits indicates output */ if (s->io_bits & 0x0000ff) { - if (devno == 0) { + if (devno == 0) config |= BUF_A0; - } else { + else config |= BUF_A1; - } } if (s->io_bits & 0x00ff00) { - if (devno == 0) { + if (devno == 0) config |= BUF_B0; - } else { + else config |= BUF_B1; - } } if (s->io_bits & 0xff0000) { - if (devno == 0) { + if (devno == 0) config |= BUF_C0; - } else { + else config |= BUF_C1; - } } return config; } @@ -155,26 +152,27 @@ static void do_3724_config(struct comedi_device *dev, buffer_config = 0; /* 1 in io_bits indicates output, 1 in config indicates input */ - if (!(s->io_bits & 0x0000ff)) { + if (!(s->io_bits & 0x0000ff)) config |= CR_A_IO; - } - if (!(s->io_bits & 0x00ff00)) { + + if (!(s->io_bits & 0x00ff00)) config |= CR_B_IO; - } - if (!(s->io_bits & 0xff0000)) { + + if (!(s->io_bits & 0xff0000)) config |= CR_C_IO; - } buffer_config = compute_buffer(0, 0, dev->subdevices); buffer_config = compute_buffer(buffer_config, 1, (dev->subdevices) + 1); - if (s == dev->subdevices) { + if (s == dev->subdevices) port_8255_cfg = dev->iobase + _8255_CR; - } else { + else port_8255_cfg = dev->iobase + SIZE_8255 + _8255_CR; - } + outb(buffer_config, dev->iobase + 8); /* update buffer register */ - /* printk("pcm3724 buffer_config (%lx) %d, %x\n", dev->iobase + _8255_CR, chanspec, buffer_config); */ + /* printk("pcm3724 buffer_config (%lx) %d, %x\n", + dev->iobase + _8255_CR, chanspec, buffer_config); */ + outb(config, port_8255_cfg); } @@ -189,29 +187,29 @@ static void enable_chan(struct comedi_device *dev, struct comedi_subdevice *s, priv = (struct priv_pcm3724 *)(dev->private); mask = 1 << CR_CHAN(chanspec); - if (s == dev->subdevices) { /* subdev 0 */ + if (s == dev->subdevices) /* subdev 0 */ priv->dio_1 |= mask; - } else { /* subdev 1 */ + else /* subdev 1 */ priv->dio_2 |= mask; - } - if (priv->dio_1 & 0xff0000) { + + if (priv->dio_1 & 0xff0000) gatecfg |= GATE_C0; - } - if (priv->dio_1 & 0xff00) { + + if (priv->dio_1 & 0xff00) gatecfg |= GATE_B0; - } - if (priv->dio_1 & 0xff) { + + if (priv->dio_1 & 0xff) gatecfg |= GATE_A0; - } - if (priv->dio_2 & 0xff0000) { + + if (priv->dio_2 & 0xff0000) gatecfg |= GATE_C1; - } - if (priv->dio_2 & 0xff00) { + + if (priv->dio_2 & 0xff00) gatecfg |= GATE_B1; - } - if (priv->dio_2 & 0xff) { + + if (priv->dio_2 & 0xff) gatecfg |= GATE_A1; - } + /* printk("gate control %x\n", gatecfg); */ outb(gatecfg, dev->iobase + 9); } @@ -225,15 +223,14 @@ static int subdev_3724_insn_config(struct comedi_device *dev, unsigned int bits; mask = 1 << CR_CHAN(insn->chanspec); - if (mask & 0x0000ff) { + if (mask & 0x0000ff) bits = 0x0000ff; - } else if (mask & 0x00ff00) { + else if (mask & 0x00ff00) bits = 0x00ff00; - } else if (mask & 0x0f0000) { + else if (mask & 0x0f0000) bits = 0x0f0000; - } else { + else bits = 0xf00000; - } switch (data[0]) { case INSN_CONFIG_DIO_INPUT: @@ -272,7 +269,7 @@ static int pcm3724_attach(struct comedi_device *dev, ((struct priv_pcm3724 *)(dev->private))->dio_1 = 0; ((struct priv_pcm3724 *)(dev->private))->dio_2 = 0; - printk("comedi%d: pcm3724: board=%s, 0x%03lx ", dev->minor, + printk(KERN_INFO "comedi%d: pcm3724: board=%s, 0x%03lx ", dev->minor, this_board->name, iobase); if (!iobase || !request_region(iobase, iorange, "pcm3724")) { printk("I/O port conflict\n"); @@ -281,7 +278,7 @@ static int pcm3724_attach(struct comedi_device *dev, dev->iobase = iobase; dev->board_name = this_board->name; - printk("\n"); + printk(KERN_INFO "\n"); n_subdevices = this_board->numofports; @@ -302,13 +299,11 @@ static int pcm3724_detach(struct comedi_device *dev) int i; if (dev->subdevices) { - for (i = 0; i < dev->n_subdevices; i++) { + for (i = 0; i < dev->n_subdevices; i++) subdev_8255_cleanup(dev, dev->subdevices + i); - } } - if (dev->iobase) { + if (dev->iobase) release_region(dev->iobase, this_board->io_range); - } return 0; } -- cgit v1.2.3 From b1e68ea5e1b0829037a1dc97e8a2ef4bb6e9c91d Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Fri, 29 Jan 2010 00:17:06 +0100 Subject: Staging: comedi: pcm3730: Checkpatch cleanups This fixes all checkpatch issues in the pcm3730 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcm3730.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcm3730.c b/drivers/staging/comedi/drivers/pcm3730.c index 9e4adbd89dda..22b7aae63add 100644 --- a/drivers/staging/comedi/drivers/pcm3730.c +++ b/drivers/staging/comedi/drivers/pcm3730.c @@ -73,7 +73,7 @@ static int pcm3730_attach(struct comedi_device *dev, unsigned long iobase; iobase = it->options[0]; - printk("comedi%d: pcm3730: 0x%04lx ", dev->minor, iobase); + printk(KERN_INFO "comedi%d: pcm3730: 0x%04lx ", dev->minor, iobase); if (!request_region(iobase, PCM3730_SIZE, "pcm3730")) { printk("I/O port conflict\n"); return -EIO; @@ -140,14 +140,14 @@ static int pcm3730_attach(struct comedi_device *dev, s->range_table = &range_digital; s->private = (void *)PCM3730_DIC; - printk("\n"); + printk(KERN_INFO "\n"); return 0; } static int pcm3730_detach(struct comedi_device *dev) { - printk("comedi%d: pcm3730: remove\n", dev->minor); + printk(KERN_INFO "comedi%d: pcm3730: remove\n", dev->minor); if (dev->iobase) release_region(dev->iobase, PCM3730_SIZE); -- cgit v1.2.3 From 94941bc805d2b77e6b548b83529b3fa5e98a3636 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Fri, 29 Jan 2010 00:28:46 +0100 Subject: Staging: comedi: poc: Checkpatch cleanups This fixes all checkpatch issues in the poc comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/poc.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/poc.c b/drivers/staging/comedi/drivers/poc.c index d23e588d0632..8990bf2fc186 100644 --- a/drivers/staging/comedi/drivers/poc.c +++ b/drivers/staging/comedi/drivers/poc.c @@ -122,22 +122,21 @@ static int poc_attach(struct comedi_device *dev, struct comedi_devconfig *it) unsigned int iosize; iobase = it->options[0]; - printk("comedi%d: poc: using %s iobase 0x%lx\n", dev->minor, + printk(KERN_INFO "comedi%d: poc: using %s iobase 0x%lx\n", dev->minor, this_board->name, iobase); dev->board_name = this_board->name; if (iobase == 0) { - printk("io base address required\n"); + printk(KERN_WARNING "io base address required\n"); return -EINVAL; } iosize = this_board->iosize; /* check if io addresses are available */ if (!request_region(iobase, iosize, "dac02")) { - printk - ("I/O port conflict: failed to allocate ports 0x%lx to 0x%lx\n", - iobase, iobase + iosize - 1); + printk(KERN_WARNING "I/O port conflict: failed to allocate " + "ports 0x%lx to 0x%lx\n", iobase, iobase + iosize - 1); return -EIO; } dev->iobase = iobase; @@ -156,9 +155,8 @@ static int poc_attach(struct comedi_device *dev, struct comedi_devconfig *it) s->insn_write = this_board->winsn; s->insn_read = this_board->rinsn; s->insn_bits = this_board->insnbits; - if (s->type == COMEDI_SUBD_AO || s->type == COMEDI_SUBD_DO) { + if (s->type == COMEDI_SUBD_AO || s->type == COMEDI_SUBD_DO) s->subdev_flags = SDF_WRITABLE; - } return 0; } @@ -169,7 +167,7 @@ static int poc_detach(struct comedi_device *dev) if (dev->iobase) release_region(dev->iobase, this_board->iosize); - printk("comedi%d: dac02: remove\n", dev->minor); + printk(KERN_INFO "comedi%d: dac02: remove\n", dev->minor); return 0; } -- cgit v1.2.3 From 900b78088567d2033c58d4e2433c3d2558f56b76 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Fri, 29 Jan 2010 00:42:30 +0100 Subject: Staging: comedi: ni_660x: Checkpatch cleanups This fixes all checkpatch issues in the ni_660x comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_660x.c | 71 ++++++++++++++++---------------- 1 file changed, 36 insertions(+), 35 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_660x.c b/drivers/staging/comedi/drivers/ni_660x.c index 1e2041447667..f74fc5e6ba20 100644 --- a/drivers/staging/comedi/drivers/ni_660x.c +++ b/drivers/staging/comedi/drivers/ni_660x.c @@ -52,7 +52,9 @@ enum ni_660x_constants { }; #define NUM_PFI_CHANNELS 40 -/* really there are only up to 3 dma channels, but the register layout allows for 4 */ +/* really there are only up to 3 dma channels, but the register layout allows +for 4 */ + #define MAX_DMA_CHANNEL 4 /* See Register-Level Programmer Manual page 3.1 */ @@ -198,7 +200,7 @@ struct NI_660xRegisterData { const char *name; /* Register Name */ int offset; /* Offset from base address from GPCT chip */ enum ni_660x_register_direction direction; - enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */ + enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */ }; static const struct NI_660xRegisterData registerData[NumRegisters] = { @@ -382,8 +384,8 @@ enum global_interrupt_config_register_bits { }; /* Offset of the GPCT chips from the base-adress of the card */ -static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 }; /* First chip is at base-address + - 0x00, etc. */ +/* First chip is at base-address + 0x00, etc. */ +static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 }; /* Board description*/ struct ni_660x_board { @@ -712,7 +714,7 @@ static enum NI_660x_Register ni_gpct_to_660x_register(enum ni_gpct_register reg) ni_660x_register = G3InterruptEnable; break; default: - printk("%s: unhandled register 0x%x in switch.\n", + printk(KERN_WARNING "%s: unhandled register 0x%x in switch.\n", __func__, reg); BUG(); return 0; @@ -737,7 +739,7 @@ static inline void ni_660x_write_register(struct comedi_device *dev, writel(bits, write_address); break; default: - printk("%s: %s: bug! unhandled case (reg=0x%x) in switch.\n", + printk(KERN_WARNING "%s: %s: bug! unhandled case (reg=0x%x) in switch.\n", __FILE__, __func__, reg); BUG(); break; @@ -760,7 +762,7 @@ static inline unsigned ni_660x_read_register(struct comedi_device *dev, return readl(read_address); break; default: - printk("%s: %s: bug! unhandled case (reg=0x%x) in switch.\n", + printk(KERN_WARNING "%s: %s: bug! unhandled case (reg=0x%x) in switch.\n", __FILE__, __func__, reg); BUG(); break; @@ -993,9 +995,9 @@ static int ni_660x_allocate_private(struct comedi_device *dev) spin_lock_init(&private(dev)->mite_channel_lock); spin_lock_init(&private(dev)->interrupt_lock); spin_lock_init(&private(dev)->soft_reg_copy_lock); - for (i = 0; i < NUM_PFI_CHANNELS; ++i) { + for (i = 0; i < NUM_PFI_CHANNELS; ++i) private(dev)->pfi_output_selects[i] = pfi_output_select_counter; - } + return 0; } @@ -1008,9 +1010,8 @@ static int ni_660x_alloc_mite_rings(struct comedi_device *dev) for (j = 0; j < counters_per_chip; ++j) { private(dev)->mite_rings[i][j] = mite_alloc_ring(private(dev)->mite); - if (private(dev)->mite_rings[i][j] == NULL) { + if (private(dev)->mite_rings[i][j] == NULL) return -ENOMEM; - } } } return 0; @@ -1022,9 +1023,8 @@ static void ni_660x_free_mite_rings(struct comedi_device *dev) unsigned j; for (i = 0; i < board(dev)->n_chips; ++i) { - for (j = 0; j < counters_per_chip; ++j) { + for (j = 0; j < counters_per_chip; ++j) mite_free_ring(private(dev)->mite_rings[i][j]); - } } } @@ -1036,7 +1036,7 @@ static int ni_660x_attach(struct comedi_device *dev, unsigned i; unsigned global_interrupt_config_bits; - printk("comedi%d: ni_660x: ", dev->minor); + printk(KERN_INFO "comedi%d: ni_660x: ", dev->minor); ret = ni_660x_allocate_private(dev); if (ret < 0) @@ -1049,7 +1049,7 @@ static int ni_660x_attach(struct comedi_device *dev, ret = mite_setup2(private(dev)->mite, 1); if (ret < 0) { - printk("error setting up mite\n"); + printk(KERN_WARNING "error setting up mite\n"); return ret; } comedi_set_hw_dev(dev, &private(dev)->mite->pcidev->dev); @@ -1057,7 +1057,7 @@ static int ni_660x_attach(struct comedi_device *dev, if (ret < 0) return ret; - printk(" %s ", dev->board_name); + printk(KERN_INFO " %s ", dev->board_name); dev->n_subdevices = 2 + NI_660X_MAX_NUM_COUNTERS; @@ -1078,15 +1078,17 @@ static int ni_660x_attach(struct comedi_device *dev, s->insn_bits = ni_660x_dio_insn_bits; s->insn_config = ni_660x_dio_insn_config; s->io_bits = 0; /* all bits default to input */ - /* we use the ioconfig registers to control dio direction, so zero output enables in stc dio control reg */ + /* we use the ioconfig registers to control dio direction, so zero + output enables in stc dio control reg */ ni_660x_write_register(dev, 0, 0, STCDIOControl); - private(dev)->counter_dev = ni_gpct_device_construct(dev, - &ni_gpct_write_register, - &ni_gpct_read_register, - ni_gpct_variant_660x, - ni_660x_num_counters - (dev)); + private(dev)->counter_dev + = ni_gpct_device_construct(dev, + &ni_gpct_write_register, + &ni_gpct_read_register, + ni_gpct_variant_660x, + ni_660x_num_counters + (dev)); if (private(dev)->counter_dev == NULL) return -ENOMEM; for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) { @@ -1118,12 +1120,12 @@ static int ni_660x_attach(struct comedi_device *dev, s->type = COMEDI_SUBD_UNUSED; } } - for (i = 0; i < board(dev)->n_chips; ++i) { + for (i = 0; i < board(dev)->n_chips; ++i) init_tio_chip(dev, i); - } - for (i = 0; i < ni_660x_num_counters(dev); ++i) { + + for (i = 0; i < ni_660x_num_counters(dev); ++i) ni_tio_init_counter(&private(dev)->counter_dev->counters[i]); - } + for (i = 0; i < NUM_PFI_CHANNELS; ++i) { if (i < min_counter_pfi_chan) ni_660x_set_pfi_routing(dev, i, pfi_output_select_do); @@ -1134,13 +1136,13 @@ static int ni_660x_attach(struct comedi_device *dev, } /* to be safe, set counterswap bits on tio chips after all the counter outputs have been set to high impedance mode */ - for (i = 0; i < board(dev)->n_chips; ++i) { + for (i = 0; i < board(dev)->n_chips; ++i) set_tio_counterswap(dev, i); - } + ret = request_irq(mite_irq(private(dev)->mite), ni_660x_interrupt, IRQF_SHARED, "ni_660x", dev); if (ret < 0) { - printk(" irq not available\n"); + printk(KERN_WARNING " irq not available\n"); return ret; } dev->irq = mite_irq(private(dev)->mite); @@ -1149,13 +1151,13 @@ static int ni_660x_attach(struct comedi_device *dev, global_interrupt_config_bits |= Cascade_Int_Enable_Bit; ni_660x_write_register(dev, 0, global_interrupt_config_bits, GlobalInterruptConfigRegister); - printk("attached\n"); + printk(KERN_INFO "attached\n"); return 0; } static int ni_660x_detach(struct comedi_device *dev) { - printk("comedi%d: ni_660x: remove\n", dev->minor); + printk(KERN_INFO "comedi%d: ni_660x: remove\n", dev->minor); /* Free irq */ if (dev->irq) @@ -1193,9 +1195,8 @@ static void init_tio_chip(struct comedi_device *dev, int chipset) private(dev)-> dma_configuration_soft_copies[chipset], DMAConfigRegister); - for (i = 0; i < NUM_PFI_CHANNELS; ++i) { + for (i = 0; i < NUM_PFI_CHANNELS; ++i) ni_660x_write_register(dev, chipset, 0, IOConfigReg(i)); - } } static int @@ -1234,7 +1235,7 @@ static int ni_660x_find_device(struct comedi_device *dev, int bus, int slot) } } } - printk("no device found\n"); + printk(KERN_WARNING "no device found\n"); mite_list_devices(); return -EIO; } -- cgit v1.2.3 From c733110ae3c49a69907b89f37ff1721a157df0f3 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Sat, 30 Jan 2010 12:40:29 +0100 Subject: Staging: comedi: ni_670x: Checkpatch cleanups This fixes all checkpatch issues in the ni_670x comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_670x.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_670x.c b/drivers/staging/comedi/drivers/ni_670x.c index 9b43547e80a1..1e792d592f73 100644 --- a/drivers/staging/comedi/drivers/ni_670x.c +++ b/drivers/staging/comedi/drivers/ni_670x.c @@ -93,7 +93,7 @@ static DEFINE_PCI_DEVICE_TABLE(ni_670x_pci_table) = { { PCI_VENDOR_ID_NATINST, 0x2c90, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { PCI_VENDOR_ID_NATINST, 0x1920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, - /* { PCI_VENDOR_ID_NATINST, 0x0000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, */ + /*{ PCI_VENDOR_ID_NATINST, 0x0000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },*/ { 0} }; @@ -151,7 +151,7 @@ static int ni_670x_attach(struct comedi_device *dev, int ret; int i; - printk("comedi%d: ni_670x: ", dev->minor); + printk(KERN_INFO "comedi%d: ni_670x: ", dev->minor); ret = alloc_private(dev, sizeof(struct ni_670x_private)); if (ret < 0) @@ -163,12 +163,12 @@ static int ni_670x_attach(struct comedi_device *dev, ret = mite_setup(devpriv->mite); if (ret < 0) { - printk("error setting up mite\n"); + printk(KERN_WARNING "error setting up mite\n"); return ret; } dev->board_name = thisboard->name; dev->irq = mite_irq(devpriv->mite); - printk(" %s", dev->board_name); + printk(KERN_INFO " %s", dev->board_name); if (alloc_subdevices(dev, 2) < 0) return -ENOMEM; @@ -207,21 +207,22 @@ static int ni_670x_attach(struct comedi_device *dev, s->insn_bits = ni_670x_dio_insn_bits; s->insn_config = ni_670x_dio_insn_config; - writel(0x10, devpriv->mite->daq_io_addr + MISC_CONTROL_OFFSET); /* Config of misc registers */ - writel(0x00, devpriv->mite->daq_io_addr + AO_CONTROL_OFFSET); /* Config of ao registers */ + /* Config of misc registers */ + writel(0x10, devpriv->mite->daq_io_addr + MISC_CONTROL_OFFSET); + /* Config of ao registers */ + writel(0x00, devpriv->mite->daq_io_addr + AO_CONTROL_OFFSET); - printk("attached\n"); + printk(KERN_INFO "attached\n"); return 1; } static int ni_670x_detach(struct comedi_device *dev) { - printk("comedi%d: ni_670x: remove\n", dev->minor); + printk(KERN_INFO "comedi%d: ni_670x: remove\n", dev->minor); + + kfree(dev->subdevices[0].range_table_list); - if (dev->subdevices[0].range_table_list) { - kfree(dev->subdevices[0].range_table_list); - } if (dev->private && devpriv->mite) mite_unsetup(devpriv->mite); @@ -250,8 +251,11 @@ static int ni_670x_ao_winsn(struct comedi_device *dev, vch(15) : 30 | ich(31) : 31 */ for (i = 0; i < insn->n; i++) { - writel(((chan & 15) << 1) | ((chan & 16) >> 4), devpriv->mite->daq_io_addr + AO_CHAN_OFFSET); /* First write in channel register which channel to use */ - writel(data[i], devpriv->mite->daq_io_addr + AO_VALUE_OFFSET); /* write channel value */ + /* First write in channel register which channel to use */ + writel(((chan & 15) << 1) | ((chan & 16) >> 4), + devpriv->mite->daq_io_addr + AO_CHAN_OFFSET); + /* write channel value */ + writel(data[i], devpriv->mite->daq_io_addr + AO_VALUE_OFFSET); devpriv->ao_readback[chan] = data[i]; } @@ -344,7 +348,7 @@ static int ni_670x_find_device(struct comedi_device *dev, int bus, int slot) } } } - printk("no device found\n"); + printk(KERN_INFO "no device found\n"); mite_list_devices(); return -EIO; } -- cgit v1.2.3 From d8dfb3882e12539f34c6eeb01dee6f425e92e892 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Sat, 30 Jan 2010 13:03:20 +0100 Subject: Staging: comedi: ni_65xx: Checkpatch cleanups This fixes all checkpatch issues in the ni_65xx comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_65xx.c | 49 ++++++++++++++++---------------- 1 file changed, 24 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_65xx.c b/drivers/staging/comedi/drivers/ni_65xx.c index bbf75eb6d7f2..c223f76031f6 100644 --- a/drivers/staging/comedi/drivers/ni_65xx.c +++ b/drivers/staging/comedi/drivers/ni_65xx.c @@ -26,12 +26,13 @@ /* Driver: ni_65xx Description: National Instruments 65xx static dio boards -Author: Jon Grierson , Frank Mori Hess +Author: Jon Grierson , + Frank Mori Hess Status: testing -Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510, PCI-6511, - PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514, PXI-6514, PCI-6515, - PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519, PCI-6520, PCI-6521, PXI-6521, - PCI-6528, PXI-6528 +Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510, + PCI-6511, PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514, + PXI-6514, PCI-6515, PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519, + PCI-6520, PCI-6521, PXI-6521, PCI-6528, PXI-6528 Updated: Wed Oct 18 08:59:11 EDT 2006 Based on the PCI-6527 driver by ds. @@ -418,9 +419,10 @@ static int ni_65xx_dio_insn_bits(struct comedi_device *dev, return -EINVAL; base_bitfield_channel = CR_CHAN(insn->chanspec); for (j = 0; j < max_ports_per_bitfield; ++j) { - const unsigned port_offset = ni_65xx_port_by_channel(base_bitfield_channel) + j; + const unsigned port_offset = + ni_65xx_port_by_channel(base_bitfield_channel) + j; const unsigned port = - sprivate(s)->base_port + port_offset; + sprivate(s)->base_port + port_offset; unsigned base_port_channel; unsigned port_mask, port_data, port_read_bits; int bitshift; @@ -463,11 +465,11 @@ static int ni_65xx_dio_insn_bits(struct comedi_device *dev, * subdevice.) */ port_read_bits ^= 0xFF; } - if (bitshift > 0) { + if (bitshift > 0) port_read_bits <<= bitshift; - } else { + else port_read_bits >>= -bitshift; - } + read_bits |= port_read_bits; } data[1] = read_bits; @@ -532,7 +534,8 @@ static int ni_65xx_intr_cmdtest(struct comedi_device *dev, if (err) return 1; - /* step 2: make sure trigger sources are unique and mutually compatible */ + /* step 2: make sure trigger sources are unique and mutually + compatible */ if (err) return 2; @@ -652,7 +655,7 @@ static int ni_65xx_attach(struct comedi_device *dev, unsigned i; int ret; - printk("comedi%d: ni_65xx:", dev->minor); + printk(KERN_INFO "comedi%d: ni_65xx:", dev->minor); ret = alloc_private(dev, sizeof(struct ni_65xx_private)); if (ret < 0) @@ -664,15 +667,15 @@ static int ni_65xx_attach(struct comedi_device *dev, ret = mite_setup(private(dev)->mite); if (ret < 0) { - printk("error setting up mite\n"); + printk(KERN_WARNING "error setting up mite\n"); return ret; } dev->board_name = board(dev)->name; dev->irq = mite_irq(private(dev)->mite); - printk(" %s", dev->board_name); + printk(KERN_INFO " %s", dev->board_name); - printk(" ID=0x%02x", + printk(KERN_INFO " ID=0x%02x", readb(private(dev)->mite->daq_io_addr + ID_Register)); ret = alloc_subdevices(dev, 4); @@ -773,7 +776,7 @@ static int ni_65xx_attach(struct comedi_device *dev, "ni_65xx", dev); if (ret < 0) { dev->irq = 0; - printk(" irq not available"); + printk(KERN_WARNING " irq not available"); } printk("\n"); @@ -790,21 +793,17 @@ static int ni_65xx_detach(struct comedi_device *dev) Master_Interrupt_Control); } - if (dev->irq) { + if (dev->irq) free_irq(dev->irq, dev); - } if (private(dev)) { unsigned i; for (i = 0; i < dev->n_subdevices; ++i) { - if (dev->subdevices[i].private) { - kfree(dev->subdevices[i].private); - dev->subdevices[i].private = NULL; - } + kfree(dev->subdevices[i].private); + dev->subdevices[i].private = NULL; } - if (private(dev)->mite) { + if (private(dev)->mite) mite_unsetup(private(dev)->mite); - } } return 0; } @@ -830,7 +829,7 @@ static int ni_65xx_find_device(struct comedi_device *dev, int bus, int slot) } } } - printk("no device found\n"); + printk(KERN_WARNING "no device found\n"); mite_list_devices(); return -EIO; } -- cgit v1.2.3 From 27aa7320972a130ba3cd2d4004c2568e7c40f01e Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Sun, 31 Jan 2010 23:29:28 +0100 Subject: Staging: comedi: fl512: Checkpatch cleanups This fixes all checkpatch issues in the fl512 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/fl512.c | 72 +++++++++++++++++++++------------- 1 file changed, 44 insertions(+), 28 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/fl512.c b/drivers/staging/comedi/drivers/fl512.c index 8fca18043357..a10a2b070a24 100644 --- a/drivers/staging/comedi/drivers/fl512.c +++ b/drivers/staging/comedi/drivers/fl512.c @@ -76,14 +76,14 @@ static int fl512_ai_insn(struct comedi_device *dev, unsigned long iobase = dev->iobase; for (n = 0; n < insn->n; n++) { /* sample n times on selected channel */ - /* XXX probably can move next step out of for() loop -- will make - * AI a little bit faster. */ + /* XXX probably can move next step out of for() loop -- will + * make AI a little bit faster. */ outb(chan, iobase + 2); /* select chan */ outb(0, iobase + 3); /* start conversion */ /* XXX should test "done" flag instead of delay */ udelay(30); /* sleep 30 usec */ lo_byte = inb(iobase + 2); /* low 8 byte */ - hi_byte = inb(iobase + 3) & 0xf; /* high 4 bit and mask */ + hi_byte = inb(iobase + 3) & 0xf; /* high 4 bit and mask */ data[n] = lo_byte + (hi_byte << 8); } return n; @@ -101,8 +101,10 @@ static int fl512_ao_insn(struct comedi_device *dev, unsigned long iobase = dev->iobase; /* get base address */ for (n = 0; n < insn->n; n++) { /* write n data set */ - outb(data[n] & 0x0ff, iobase + 4 + 2 * chan); /* write low byte */ - outb((data[n] & 0xf00) >> 8, iobase + 4 + 2 * chan); /* write high byte */ + /* write low byte */ + outb(data[n] & 0x0ff, iobase + 4 + 2 * chan); + /* write high byte */ + outb((data[n] & 0xf00) >> 8, iobase + 4 + 2 * chan); inb(iobase + 4 + 2 * chan); /* trig */ devpriv->ao_readback[chan] = data[n]; @@ -121,9 +123,8 @@ static int fl512_ao_insn_readback(struct comedi_device *dev, int n; int chan = CR_CHAN(insn->chanspec); - for (n = 0; n < insn->n; n++) { + for (n = 0; n < insn->n; n++) data[n] = devpriv->ao_readback[chan]; - } return n; } @@ -134,13 +135,15 @@ static int fl512_ao_insn_readback(struct comedi_device *dev, static int fl512_attach(struct comedi_device *dev, struct comedi_devconfig *it) { unsigned long iobase; - struct comedi_subdevice *s; /* pointer to the subdevice: - Analog in, Analog out, ( not made ->and Digital IO) */ + + /* pointer to the subdevice: Analog in, Analog out, + (not made ->and Digital IO) */ + struct comedi_subdevice *s; iobase = it->options[0]; - printk("comedi:%d fl512: 0x%04lx", dev->minor, iobase); + printk(KERN_INFO "comedi:%d fl512: 0x%04lx", dev->minor, iobase); if (!request_region(iobase, FL512_SIZE, "fl512")) { - printk(" I/O port conflict\n"); + printk(KERN_WARNING " I/O port conflict\n"); return -EIO; } dev->iobase = iobase; @@ -149,7 +152,7 @@ static int fl512_attach(struct comedi_device *dev, struct comedi_devconfig *it) return -ENOMEM; #if DEBUG - printk("malloc ok\n"); + printk(KERN_DEBUG "malloc ok\n"); #endif if (alloc_subdevices(dev, 2) < 0) @@ -160,24 +163,37 @@ static int fl512_attach(struct comedi_device *dev, struct comedi_devconfig *it) */ /* Analog indput */ s = dev->subdevices + 0; - s->type = COMEDI_SUBD_AI; /* define subdevice as Analog In */ - s->subdev_flags = SDF_READABLE | SDF_GROUND; /* you can read it from userspace */ - s->n_chan = 16; /* Number of Analog input channels */ - s->maxdata = 0x0fff; /* accept only 12 bits of data */ - s->range_table = &range_fl512; /* device use one of the ranges */ - s->insn_read = fl512_ai_insn; /* function to call when read AD */ - printk("comedi: fl512: subdevice 0 initialized\n"); + /* define subdevice as Analog In */ + s->type = COMEDI_SUBD_AI; + /* you can read it from userspace */ + s->subdev_flags = SDF_READABLE | SDF_GROUND; + /* Number of Analog input channels */ + s->n_chan = 16; + /* accept only 12 bits of data */ + s->maxdata = 0x0fff; + /* device use one of the ranges */ + s->range_table = &range_fl512; + /* function to call when read AD */ + s->insn_read = fl512_ai_insn; + printk(KERN_INFO "comedi: fl512: subdevice 0 initialized\n"); /* Analog output */ s = dev->subdevices + 1; - s->type = COMEDI_SUBD_AO; /* define subdevice as Analog OUT */ - s->subdev_flags = SDF_WRITABLE; /* you can write it from userspace */ - s->n_chan = 2; /* Number of Analog output channels */ - s->maxdata = 0x0fff; /* accept only 12 bits of data */ - s->range_table = &range_fl512; /* device use one of the ranges */ - s->insn_write = fl512_ao_insn; /* function to call when write DA */ - s->insn_read = fl512_ao_insn_readback; /* function to call when reading DA */ - printk("comedi: fl512: subdevice 1 initialized\n"); + /* define subdevice as Analog OUT */ + s->type = COMEDI_SUBD_AO; + /* you can write it from userspace */ + s->subdev_flags = SDF_WRITABLE; + /* Number of Analog output channels */ + s->n_chan = 2; + /* accept only 12 bits of data */ + s->maxdata = 0x0fff; + /* device use one of the ranges */ + s->range_table = &range_fl512; + /* function to call when write DA */ + s->insn_write = fl512_ao_insn; + /* function to call when reading DA */ + s->insn_read = fl512_ao_insn_readback; + printk(KERN_INFO "comedi: fl512: subdevice 1 initialized\n"); return 1; } @@ -186,6 +202,6 @@ static int fl512_detach(struct comedi_device *dev) { if (dev->iobase) release_region(dev->iobase, FL512_SIZE); - printk("comedi%d: fl512: dummy i detach\n", dev->minor); + printk(KERN_INFO "comedi%d: fl512: dummy i detach\n", dev->minor); return 0; } -- cgit v1.2.3 From 7df1735bebee6d1f3492c79ab110f3a6e67e0244 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Mon, 1 Feb 2010 00:04:14 +0100 Subject: Staging: comedi: adq12b: Checkpatch cleanups 2 This fixes all checkpatch issues in the adq12b comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/adq12b.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/adq12b.c b/drivers/staging/comedi/drivers/adq12b.c index 4590cac612d4..f3ba645bf63b 100644 --- a/drivers/staging/comedi/drivers/adq12b.c +++ b/drivers/staging/comedi/drivers/adq12b.c @@ -201,15 +201,16 @@ static int adq12b_attach(struct comedi_device *dev, struct comedi_devconfig *it) unipolar = it->options[1]; differential = it->options[2]; - printk("comedi%d: adq12b called with options base=0x%03lx, %s and %s\n", - dev->minor, iobase, (unipolar == 1) ? "unipolar" : "bipolar", + printk(KERN_INFO "comedi%d: adq12b called with options base=0x%03lx, " + "%s and %s\n", dev->minor, iobase, + (unipolar == 1) ? "unipolar" : "bipolar", (differential == 1) ? "differential" : "single-ended"); /* if no address was specified, try the default 0x300 */ if (iobase == 0) { - printk - ("comedi%d: adq12b warning: I/O base address not specified. Trying the default 0x300.\n", - dev->minor); + printk(KERN_WARNING "comedi%d: adq12b warning: I/O base " + "address not specified. Trying the default 0x300.\n", + dev->minor); iobase = 0x300; } @@ -289,7 +290,7 @@ static int adq12b_attach(struct comedi_device *dev, struct comedi_devconfig *it) s->range_table = &range_digital; s->insn_bits = adq12b_do_insn_bits; - printk("attached\n"); + printk(KERN_INFO "attached\n"); return 0; } @@ -309,7 +310,7 @@ static int adq12b_detach(struct comedi_device *dev) kfree(devpriv); - printk("comedi%d: adq12b: removed\n", dev->minor); + printk(KERN_INFO "comedi%d: adq12b: removed\n", dev->minor); return 0; } @@ -354,7 +355,8 @@ static int adq12b_ai_rinsn(struct comedi_device *dev, hi = inb(dev->iobase + ADQ12B_ADHIG); lo = inb(dev->iobase + ADQ12B_ADLOW); - /* printk("debug: chan=%d range=%d status=%d hi=%d lo=%d\n", channel, range, status, hi, lo); */ + /* printk("debug: chan=%d range=%d status=%d hi=%d lo=%d\n", + channel, range, status, hi, lo); */ data[n] = (hi << 8) | lo; } -- cgit v1.2.3 From bc56894234e55ad53419cfda1bbfc401a8be3e46 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Sun, 31 Jan 2010 12:02:08 -0800 Subject: Staging: Fix continuation line formats String constants that are continued on subsequent lines with \ are not good. Fixed a "is tryied" / tried typo Signed-off-by: Joe Perches Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dream/qdsp5/audio_mp3.c | 3 +-- drivers/staging/rtl8187se/ieee80211/ieee80211_softmac_wx.c | 3 +-- drivers/staging/rtl8187se/r8180_core.c | 3 +-- drivers/staging/sep/sep_driver.c | 3 +-- 4 files changed, 4 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dream/qdsp5/audio_mp3.c b/drivers/staging/dream/qdsp5/audio_mp3.c index b95574f699ff..7ed6e261d6c9 100644 --- a/drivers/staging/dream/qdsp5/audio_mp3.c +++ b/drivers/staging/dream/qdsp5/audio_mp3.c @@ -650,8 +650,7 @@ static long audio_ioctl(struct file *file, unsigned int cmd, unsigned long arg) &audio->read_phys, GFP_KERNEL); if (!audio->read_data) { - pr_err("audio_mp3: malloc pcm \ - buf failed\n"); + pr_err("audio_mp3: malloc pcm buf failed\n"); rc = -1; } else { uint8_t index; diff --git a/drivers/staging/rtl8187se/ieee80211/ieee80211_softmac_wx.c b/drivers/staging/rtl8187se/ieee80211/ieee80211_softmac_wx.c index f1d6cb452563..ad42bcdc9374 100644 --- a/drivers/staging/rtl8187se/ieee80211/ieee80211_softmac_wx.c +++ b/drivers/staging/rtl8187se/ieee80211/ieee80211_softmac_wx.c @@ -482,8 +482,7 @@ int ieee80211_wx_set_power(struct ieee80211_device *ieee, (!ieee->enter_sleep_state) || (!ieee->ps_is_queue_empty)){ - printk("ERROR. PS mode is tryied to be use but\ -driver missed a callback\n\n"); + printk("ERROR. PS mode tried to be use but driver missed a callback\n\n"); return -1; } diff --git a/drivers/staging/rtl8187se/r8180_core.c b/drivers/staging/rtl8187se/r8180_core.c index 9c2f4d3b58c7..33363c47c265 100644 --- a/drivers/staging/rtl8187se/r8180_core.c +++ b/drivers/staging/rtl8187se/r8180_core.c @@ -3813,8 +3813,7 @@ static int __init rtl8180_pci_module_init(void) return ret; } - printk(KERN_INFO "\nLinux kernel driver for RTL8180 \ -/ RTL8185 based WLAN cards\n"); + printk(KERN_INFO "\nLinux kernel driver for RTL8180 / RTL8185 based WLAN cards\n"); printk(KERN_INFO "Copyright (c) 2004-2005, Andrea Merello\n"); DMESG("Initializing module"); DMESG("Wireless extensions version %d", WIRELESS_EXT); diff --git a/drivers/staging/sep/sep_driver.c b/drivers/staging/sep/sep_driver.c index 8ab3be684098..f9a492a8cef4 100644 --- a/drivers/staging/sep/sep_driver.c +++ b/drivers/staging/sep/sep_driver.c @@ -384,8 +384,7 @@ static int sep_mmap(struct file *filp, struct vm_area_struct *vma) shared area */ if ((vma->vm_end - vma->vm_start) > SEP_DRIVER_MMMAP_AREA_SIZE) { edbg("SEP Driver mmap requested size is more than allowed\n"); - printk(KERN_WARNING "SEP Driver mmap requested size is more \ - than allowed\n"); + printk(KERN_WARNING "SEP Driver mmap requested size is more than allowed\n"); printk(KERN_WARNING "SEP Driver vma->vm_end is %08lx\n", vma->vm_end); printk(KERN_WARNING "SEP Driver vma->vm_end is %08lx\n", vma->vm_start); return -EAGAIN; -- cgit v1.2.3 From 8455cd1bdba3331e07291c455ca70be33ff39860 Mon Sep 17 00:00:00 2001 From: Richard Kennedy Date: Thu, 4 Feb 2010 11:33:49 +0000 Subject: Staging: wlan-ng: minor cleanups Remove iw_handle_def private initialisations as they are no longer need these. Signed-off-by: Richard Kennedy Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlan-ng/p80211wext.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/wlan-ng/p80211wext.c b/drivers/staging/wlan-ng/p80211wext.c index 63bdaaa7a7aa..cc4b1ca80d6f 100644 --- a/drivers/staging/wlan-ng/p80211wext.c +++ b/drivers/staging/wlan-ng/p80211wext.c @@ -1744,11 +1744,7 @@ static iw_handler p80211wext_handlers[] = { struct iw_handler_def p80211wext_handler_def = { .num_standard = ARRAY_SIZE(p80211wext_handlers), - .num_private = 0, - .num_private_args = 0, .standard = p80211wext_handlers, - .private = NULL, - .private_args = NULL, .get_wireless_stats = p80211wext_get_wireless_stats }; -- cgit v1.2.3 From c7e10c99565d7a4d2f4bcc37e7bccd6c8120a0a3 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Mon, 1 Feb 2010 23:22:14 -0800 Subject: Staging: Fix continuation line formats String constants that are continued on subsequent lines with \ are not good. Signed-off-by: Joe Perches Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192su/r8192S_phy.c | 16 ++++++++-------- drivers/staging/sep/sep_driver.c | 5 +++-- drivers/staging/slicoss/slicoss.c | 6 ++---- 3 files changed, 13 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192su/r8192S_phy.c b/drivers/staging/rtl8192su/r8192S_phy.c index 77ab026288d3..63d4e5fd7b18 100644 --- a/drivers/staging/rtl8192su/r8192S_phy.c +++ b/drivers/staging/rtl8192su/r8192S_phy.c @@ -2407,8 +2407,8 @@ void PHY_SetBWModeCallback8192S(struct net_device *dev) break; default: - RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci():\ - unknown Bandwidth: %#X\n",priv->CurrentChannelBW); + RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n", + priv->CurrentChannelBW); break; } @@ -3398,8 +3398,8 @@ void SwChnlCallback8192SUsb(struct net_device *dev) u32 delay; // bool ret; - RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel\ - %d\n", priv->chan); + RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel %d\n", + priv->chan); if(!priv->up) @@ -3525,8 +3525,8 @@ void SetBWModeCallback8192SUsb(struct net_device *dev) break; default: - RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():\ - unknown Bandwidth: %#X\n",priv->CurrentChannelBW); + RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n", + priv->CurrentChannelBW); break; } @@ -3660,8 +3660,8 @@ void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev) break; default: - RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem():\ - unknown Bandwidth: %#X\n",priv->CurrentChannelBW); + RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem(): unknown Bandwidth: %#X\n", + priv->CurrentChannelBW); break; } diff --git a/drivers/staging/sep/sep_driver.c b/drivers/staging/sep/sep_driver.c index f9a492a8cef4..265de7949a78 100644 --- a/drivers/staging/sep/sep_driver.c +++ b/drivers/staging/sep/sep_driver.c @@ -944,8 +944,9 @@ static int sep_lock_user_pages(struct sep_device *sep, dbg("data_size is %lu\n", data_size); while (1); } - edbg("lli_array[%lu].physical_address is %08lx, \ - lli_array[%lu].block_size is %lu\n", count, lli_array[count].physical_address, count, lli_array[count].block_size); + edbg("lli_array[%lu].physical_address is %08lx, lli_array[%lu].block_size is %lu\n", + count, lli_array[count].physical_address, + count, lli_array[count].block_size); } /* set output params */ diff --git a/drivers/staging/slicoss/slicoss.c b/drivers/staging/slicoss/slicoss.c index 87d98e38d3b5..37e518656afa 100644 --- a/drivers/staging/slicoss/slicoss.c +++ b/drivers/staging/slicoss/slicoss.c @@ -658,8 +658,7 @@ static int slic_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) if (copy_from_user(data, rq->ifr_data, 28)) { PRINT_ERROR - ("slic: copy_from_user FAILED getting \ - initial simba param\n"); + ("slic: copy_from_user FAILED getting initial simba param\n"); return -EFAULT; } @@ -674,8 +673,7 @@ static int slic_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) (tracemon_request == SLIC_DUMP_IN_PROGRESS)) { PRINT_ERROR - ("ATK Diagnostic Trace Dump Requested but \ - already in progress... ignore\n"); + ("ATK Diagnostic Trace Dump Requested but already in progress... ignore\n"); } else { PRINT_ERROR ("ATK Diagnostic Trace Dump Requested\n"); -- cgit v1.2.3 From 412bd046b0a1726f8b168d5056d21213932f9d84 Mon Sep 17 00:00:00 2001 From: tony burrows Date: Tue, 2 Feb 2010 16:52:49 +0000 Subject: Staging: comedi: fix brace coding style issues in ni_labpc.c This patch fixes all of the brace style warnings found by the checkpatch.pl tool Signed-off-by: Tony Burrows Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_labpc.c | 36 +++++++++++++------------------ 1 file changed, 15 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_labpc.c b/drivers/staging/comedi/drivers/ni_labpc.c index 647c9b72b551..566b791e00c7 100644 --- a/drivers/staging/comedi/drivers/ni_labpc.c +++ b/drivers/staging/comedi/drivers/ni_labpc.c @@ -483,12 +483,10 @@ int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, printk("comedi%d: ni_labpc: %s, io 0x%lx", dev->minor, thisboard->name, iobase); - if (irq) { + if (irq) printk(", irq %u", irq); - } - if (dma_chan) { + if (dma_chan) printk(", dma %u", dma_chan); - } printk("\n"); if (iobase == 0) { @@ -585,8 +583,9 @@ int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, /* analog output */ s = dev->subdevices + 1; if (thisboard->has_ao) { -/* Could provide command support, except it only has a one sample - * hardware buffer for analog output and no underrun flag. */ + /* Could provide command support, except it only has a + * one sample hardware buffer for analog output and no + * underrun flag. */ s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; s->n_chan = NUM_AO_CHAN; @@ -608,7 +607,8 @@ int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, /* 8255 dio */ s = dev->subdevices + 2; - /* if board uses io memory we have to give a custom callback function to the 8255 driver */ + /* if board uses io memory we have to give a custom callback + * function to the 8255 driver */ if (thisboard->memory_mapped_io) subdev_8255_init(dev, s, labpc_dio_mem_callback, (unsigned long)(dev->iobase + DIO_BASE_REG)); @@ -640,14 +640,12 @@ int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, s->insn_read = labpc_eeprom_read_insn; s->insn_write = labpc_eeprom_write_insn; - for (i = 0; i < EEPROM_SIZE; i++) { + for (i = 0; i < EEPROM_SIZE; i++) devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); - } #ifdef LABPC_DEBUG printk(" eeprom:"); - for (i = 0; i < EEPROM_SIZE; i++) { + for (i = 0; i < EEPROM_SIZE; i++) printk(" %i:0x%x ", i, devpriv->eeprom_data[i]); - } printk("\n"); #endif } else @@ -679,9 +677,8 @@ static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) case pci_bustype: #ifdef CONFIG_COMEDI_PCI retval = labpc_find_device(dev, it->options[0], it->options[1]); - if (retval < 0) { + if (retval < 0) return retval; - } retval = mite_setup(devpriv->mite); if (retval < 0) return retval; @@ -1008,9 +1005,9 @@ static int labpc_ai_cmdtest(struct comedi_device *dev, err++; } - if (!cmd->chanlist_len) { + if (!cmd->chanlist_len) err++; - } + if (cmd->scan_end_arg != cmd->chanlist_len) { cmd->scan_end_arg = cmd->chanlist_len; err++; @@ -1105,9 +1102,8 @@ static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); /* initialize software conversion count */ - if (cmd->stop_src == TRIG_COUNT) { + if (cmd->stop_src == TRIG_COUNT) devpriv->count = cmd->stop_arg * cmd->chanlist_len; - } /* setup hardware conversion counter */ if (cmd->stop_src == TRIG_EXT) { /* load counter a1 with count of 3 (pc+ manual says this is minimum allowed) using mode 0 */ @@ -1479,9 +1475,8 @@ static void labpc_drain_dma(struct comedi_device *dev) } /* write data to comedi buffer */ - for (i = 0; i < num_points; i++) { + for (i = 0; i < num_points; i++) cfc_write_to_buffer(s, devpriv->dma_buffer[i]); - } if (async->cmd.stop_src == TRIG_COUNT) devpriv->count -= num_points; @@ -1864,9 +1859,8 @@ static unsigned int labpc_serial_in(struct comedi_device *dev) udelay(1); devpriv->status2_bits = devpriv->read_byte(dev->iobase + STATUS2_REG); - if (devpriv->status2_bits & EEPROM_OUT_BIT) { + if (devpriv->status2_bits & EEPROM_OUT_BIT) value |= 1 << (value_width - i); - } } return value; -- cgit v1.2.3 From f4098b4f8ac65e0e44bbe579ac7d32b6e05ffa3b Mon Sep 17 00:00:00 2001 From: Paul Elms Date: Thu, 4 Feb 2010 08:24:28 +0000 Subject: Staging: comedi: fix brace coding style in comedi_fops.c This patch to the comedi_fops.c file fixes a brace warning found by the checkpatch.pl tool Signed-off-by: Paul Elms Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/comedi_fops.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/comedi_fops.c b/drivers/staging/comedi/comedi_fops.c index 8117748ad5a5..79653e868c12 100644 --- a/drivers/staging/comedi/comedi_fops.c +++ b/drivers/staging/comedi/comedi_fops.c @@ -2004,12 +2004,10 @@ void comedi_event(struct comedi_device *dev, struct comedi_subdevice *s) if (async->cb_mask & s->async->events) { if (comedi_get_subdevice_runflags(s) & SRF_USER) { wake_up_interruptible(&async->wait_head); - if (s->subdev_flags & SDF_CMD_READ) { + if (s->subdev_flags & SDF_CMD_READ) kill_fasync(&dev->async_queue, SIGIO, POLL_IN); - } - if (s->subdev_flags & SDF_CMD_WRITE) { + if (s->subdev_flags & SDF_CMD_WRITE) kill_fasync(&dev->async_queue, SIGIO, POLL_OUT); - } } else { if (async->cb_func) async->cb_func(s->async->events, async->cb_arg); -- cgit v1.2.3 From 01823a13dca4de28ddb55b63c3334ff928b3abbc Mon Sep 17 00:00:00 2001 From: Tim Schofield Date: Thu, 4 Feb 2010 19:57:09 +0000 Subject: Staging: rtl8192e: fix spacing style issues in r8180_93cx6.c This is a patch to the r8180_93cx6.c file that fixes up spacing issue warnings found by the checkpatch.pl tool Signed-off-by: Tim Schofield Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/r8180_93cx6.c | 63 +++++++++++++++++----------------- 1 file changed, 32 insertions(+), 31 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192e/r8180_93cx6.c b/drivers/staging/rtl8192e/r8180_93cx6.c index 79f7a0f39623..262ed5fd086a 100644 --- a/drivers/staging/rtl8192e/r8180_93cx6.c +++ b/drivers/staging/rtl8192e/r8180_93cx6.c @@ -22,7 +22,7 @@ static void eprom_cs(struct net_device *dev, short bit) { - if(bit) + if (bit) write_nic_byte(dev, EPROM_CMD, (1<epromtype==EPROM_93c56){ - addr_str[7]=addr & 1; - addr_str[6]=addr & (1<<1); - addr_str[5]=addr & (1<<2); - addr_str[4]=addr & (1<<3); - addr_str[3]=addr & (1<<4); - addr_str[2]=addr & (1<<5); - addr_str[1]=addr & (1<<6); - addr_str[0]=addr & (1<<7); - addr_len=8; - }else{ - addr_str[5]=addr & 1; - addr_str[4]=addr & (1<<1); - addr_str[3]=addr & (1<<2); - addr_str[2]=addr & (1<<3); - addr_str[1]=addr & (1<<4); - addr_str[0]=addr & (1<<5); - addr_len=6; + if (priv->epromtype == EPROM_93c56) { + addr_str[7] = addr & 1; + addr_str[6] = addr & (1<<1); + addr_str[5] = addr & (1<<2); + addr_str[4] = addr & (1<<3); + addr_str[3] = addr & (1<<4); + addr_str[2] = addr & (1<<5); + addr_str[1] = addr & (1<<6); + addr_str[0] = addr & (1<<7); + addr_len = 8; + } else { + addr_str[5] = addr & 1; + addr_str[4] = addr & (1<<1); + addr_str[3] = addr & (1<<2); + addr_str[2] = addr & (1<<3); + addr_str[1] = addr & (1<<4); + addr_str[0] = addr & (1<<5); + addr_len = 6; } eprom_cs(dev, 1); eprom_ck_cycle(dev); @@ -129,7 +130,7 @@ u32 eprom_read(struct net_device *dev, u32 addr) //I'm unsure if it is necessary, but anyway shouldn't hurt eprom_w(dev, 0); - for(i=0;i<16;i++){ + for (i = 0; i < 16; i++) { //eeprom needs a clk cycle between writing opcode&adr //and reading data. (eeprom outs a dummy 0) eprom_ck_cycle(dev); -- cgit v1.2.3 From e41e5d601e1c035fde488f9543c978b8ae86e1be Mon Sep 17 00:00:00 2001 From: Yong Zhang Date: Fri, 5 Feb 2010 21:52:40 +0800 Subject: Staging: rt2860: correct onstack wait_queue_head declaration Use DECLARE_WAIT_QUEUE_HEAD_ONSTACK to make lockdep happy Signed-off-by: Yong Zhang Cc: Greg Kroah-Hartman Cc: Bartlomiej Zolnierkiewicz Cc: Alexander Beregalov Cc: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rt2860/rt_main_dev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/rt2860/rt_main_dev.c b/drivers/staging/rt2860/rt_main_dev.c index c3d92802d0c9..fbddb00cfedd 100644 --- a/drivers/staging/rt2860/rt_main_dev.c +++ b/drivers/staging/rt2860/rt_main_dev.c @@ -216,7 +216,7 @@ int rt28xx_close(struct net_device *dev) u32 i = 0; #ifdef RTMP_MAC_USB - DECLARE_WAIT_QUEUE_HEAD(unlink_wakeup); + DECLARE_WAIT_QUEUE_HEAD_ONSTACK(unlink_wakeup); DECLARE_WAITQUEUE(wait, current); #endif /* RTMP_MAC_USB // */ -- cgit v1.2.3 From d3c796fd57f33a20b2ca968e0e449382397c8dba Mon Sep 17 00:00:00 2001 From: Chihau Chau Date: Fri, 5 Feb 2010 15:23:48 -0300 Subject: Staging: samsung-laptop: fix coding style issues This fixes some lines over 80 characters coding style issues. Signed-off-by: Chihau Chau Signed-off-by: Greg Kroah-Hartman --- drivers/staging/samsung-laptop/samsung-laptop.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/samsung-laptop/samsung-laptop.c b/drivers/staging/samsung-laptop/samsung-laptop.c index 4877138a9f96..dd7ea4c075db 100644 --- a/drivers/staging/samsung-laptop/samsung-laptop.c +++ b/drivers/staging/samsung-laptop/samsung-laptop.c @@ -99,7 +99,8 @@ static struct rfkill *rfk; static int force; module_param(force, bool, 0); -MODULE_PARM_DESC(force, "Disable the DMI check and forces the driver to be loaded"); +MODULE_PARM_DESC(force, + "Disable the DMI check and forces the driver to be loaded"); static int debug; module_param(debug, bool, S_IRUGO | S_IWUSR); @@ -370,7 +371,8 @@ static struct dmi_system_id __initdata samsung_dmi_table[] = { { .ident = "N128", .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."), + DMI_MATCH(DMI_SYS_VENDOR, + "SAMSUNG ELECTRONICS CO., LTD."), DMI_MATCH(DMI_PRODUCT_NAME, "N128"), DMI_MATCH(DMI_BOARD_NAME, "N128"), }, @@ -379,7 +381,8 @@ static struct dmi_system_id __initdata samsung_dmi_table[] = { { .ident = "N130", .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."), + DMI_MATCH(DMI_SYS_VENDOR, + "SAMSUNG ELECTRONICS CO., LTD."), DMI_MATCH(DMI_PRODUCT_NAME, "N130"), DMI_MATCH(DMI_BOARD_NAME, "N130"), }, -- cgit v1.2.3 From 0acc516aee7b1527ad125a53deff328ef29be9e6 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Sat, 6 Feb 2010 15:02:50 +0100 Subject: Staging: comedi: dt2815: Checkpatch cleanups This fixes all checkpatch issues in the dt2815 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/dt2815.c | 89 +++++++++++++++------------------ 1 file changed, 39 insertions(+), 50 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/dt2815.c b/drivers/staging/comedi/drivers/dt2815.c index d1db93c043a8..d1a4f7822433 100644 --- a/drivers/staging/comedi/drivers/dt2815.c +++ b/drivers/staging/comedi/drivers/dt2815.c @@ -34,19 +34,19 @@ Configuration options: [0] - I/O port base base address [1] - IRQ (unused) [2] - Voltage unipolar/bipolar configuration - 0 == unipolar 5V (0V -- +5V) - 1 == bipolar 5V (-5V -- +5V) + 0 == unipolar 5V (0V -- +5V) + 1 == bipolar 5V (-5V -- +5V) [3] - Current offset configuration - 0 == disabled (0mA -- +32mAV) - 1 == enabled (+4mA -- +20mAV) + 0 == disabled (0mA -- +32mAV) + 1 == enabled (+4mA -- +20mAV) [4] - Firmware program configuration - 0 == program 1 (see manual table 5-4) - 1 == program 2 (see manual table 5-4) - 2 == program 3 (see manual table 5-4) - 3 == program 4 (see manual table 5-4) + 0 == program 1 (see manual table 5-4) + 1 == program 2 (see manual table 5-4) + 2 == program 3 (see manual table 5-4) + 3 == program 4 (see manual table 5-4) [5] - Analog output 0 range configuration - 0 == voltage - 1 == current + 0 == voltage + 1 == current [6] - Analog output 1 range configuration (same options) [7] - Analog output 2 range configuration (same options) [8] - Analog output 3 range configuration (same options) @@ -61,17 +61,11 @@ Configuration options: #include #include -static const struct comedi_lrange range_dt2815_ao_32_current = { 1, { - RANGE_mA(0, - 32) - } -}; +static const struct comedi_lrange + range_dt2815_ao_32_current = {1, {RANGE_mA(0, 32)} }; -static const struct comedi_lrange range_dt2815_ao_20_current = { 1, { - RANGE_mA(4, - 20) - } -}; +static const struct comedi_lrange + range_dt2815_ao_20_current = {1, {RANGE_mA(4, 20)} }; #define DT2815_SIZE 2 @@ -118,9 +112,8 @@ static int dt2815_ao_insn_read(struct comedi_device *dev, int i; int chan = CR_CHAN(insn->chanspec); - for (i = 0; i < insn->n; i++) { + for (i = 0; i < insn->n; i++) data[i] = devpriv->ao_readback[chan]; - } return i; } @@ -139,9 +132,8 @@ static int dt2815_ao_insn(struct comedi_device *dev, struct comedi_subdevice *s, status = dt2815_wait_for_status(dev, 0x00); if (status != 0) { - printk - ("dt2815: failed to write low byte on %d reason %x\n", - chan, status); + printk(KERN_WARNING "dt2815: failed to write low byte " + "on %d reason %x\n", chan, status); return -EBUSY; } @@ -149,9 +141,8 @@ static int dt2815_ao_insn(struct comedi_device *dev, struct comedi_subdevice *s, status = dt2815_wait_for_status(dev, 0x10); if (status != 0x10) { - printk - ("dt2815: failed to write high byte on %d reason %x\n", - chan, status); + printk(KERN_WARNING "dt2815: failed to write high byte " + "on %d reason %x\n", chan, status); return -EBUSY; } devpriv->ao_readback[chan] = data[i]; @@ -163,24 +154,24 @@ static int dt2815_ao_insn(struct comedi_device *dev, struct comedi_subdevice *s, options[0] Board base address options[1] IRQ (not applicable) options[2] Voltage unipolar/bipolar configuration - 0 == unipolar 5V (0V -- +5V) - 1 == bipolar 5V (-5V -- +5V) + 0 == unipolar 5V (0V -- +5V) + 1 == bipolar 5V (-5V -- +5V) options[3] Current offset configuration - 0 == disabled (0mA -- +32mAV) - 1 == enabled (+4mA -- +20mAV) + 0 == disabled (0mA -- +32mAV) + 1 == enabled (+4mA -- +20mAV) options[4] Firmware program configuration - 0 == program 1 (see manual table 5-4) - 1 == program 2 (see manual table 5-4) - 2 == program 3 (see manual table 5-4) - 3 == program 4 (see manual table 5-4) + 0 == program 1 (see manual table 5-4) + 1 == program 2 (see manual table 5-4) + 2 == program 3 (see manual table 5-4) + 3 == program 4 (see manual table 5-4) options[5] Analog output 0 range configuration - 0 == voltage - 1 == current + 0 == voltage + 1 == current options[6] Analog output 1 range configuration ... options[12] Analog output 7 range configuration - 0 == voltage - 1 == current + 0 == voltage + 1 == current */ static int dt2815_attach(struct comedi_device *dev, struct comedi_devconfig *it) @@ -191,9 +182,9 @@ static int dt2815_attach(struct comedi_device *dev, struct comedi_devconfig *it) unsigned long iobase; iobase = it->options[0]; - printk("comedi%d: dt2815: 0x%04lx ", dev->minor, iobase); + printk(KERN_INFO "comedi%d: dt2815: 0x%04lx ", dev->minor, iobase); if (!request_region(iobase, DT2815_SIZE, "dt2815")) { - printk("I/O port conflict\n"); + printk(KERN_WARNING "I/O port conflict\n"); return -EIO; } @@ -236,19 +227,17 @@ static int dt2815_attach(struct comedi_device *dev, struct comedi_devconfig *it) unsigned int program; program = (it->options[4] & 0x3) << 3 | 0x7; outb(program, dev->iobase + DT2815_DATA); - printk(", program: 0x%x (@t=%d)\n", program, i); + printk(KERN_INFO ", program: 0x%x (@t=%d)\n", + program, i); break; } else if (status != 0x00) { - printk("dt2815: unexpected status 0x%x (@t=%d)\n", - status, i); - if (status & 0x60) { + printk(KERN_WARNING "dt2815: unexpected status 0x%x " + "(@t=%d)\n", status, i); + if (status & 0x60) outb(0x00, dev->iobase + DT2815_STATUS); - } } } - printk("\n"); - return 0; } @@ -260,7 +249,7 @@ static void dt2815_free_resources(struct comedi_device *dev) static int dt2815_detach(struct comedi_device *dev) { - printk("comedi%d: dt2815: remove\n", dev->minor); + printk(KERN_INFO "comedi%d: dt2815: remove\n", dev->minor); dt2815_free_resources(dev); -- cgit v1.2.3 From 83c41dabcca05eacc5917928a3e6a3bdfefad652 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Sat, 6 Feb 2010 15:08:46 +0100 Subject: Staging: comedi: rti802: Checkpatch cleanups This fixes all checkpatch issues in the rti802 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/rti802.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/rti802.c b/drivers/staging/comedi/drivers/rti802.c index 2f75c737ea15..2157edcf7997 100644 --- a/drivers/staging/comedi/drivers/rti802.c +++ b/drivers/staging/comedi/drivers/rti802.c @@ -106,9 +106,9 @@ static int rti802_attach(struct comedi_device *dev, struct comedi_devconfig *it) unsigned long iobase; iobase = it->options[0]; - printk("comedi%d: rti802: 0x%04lx ", dev->minor, iobase); + printk(KERN_INFO "comedi%d: rti802: 0x%04lx ", dev->minor, iobase); if (!request_region(iobase, RTI802_SIZE, "rti802")) { - printk("I/O port conflict\n"); + printk(KERN_WARNING "I/O port conflict\n"); return -EIO; } dev->iobase = iobase; @@ -138,14 +138,12 @@ static int rti802_attach(struct comedi_device *dev, struct comedi_devconfig *it) ? &range_unipolar10 : &range_bipolar10; } - printk("\n"); - return 0; } static int rti802_detach(struct comedi_device *dev) { - printk("comedi%d: rti802: remove\n", dev->minor); + printk(KERN_INFO "comedi%d: rti802: remove\n", dev->minor); if (dev->iobase) release_region(dev->iobase, RTI802_SIZE); -- cgit v1.2.3 From 2d2facda0b71609be294aa1fd5f56d2cdbcbb794 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Sat, 6 Feb 2010 16:17:06 +0100 Subject: Staging: comedi: ni_pcidio: Checkpatch cleanups This fixes almost all checkpatch issues in the ni_pcidio comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_pcidio.c | 83 ++++++++++++++++-------------- 1 file changed, 44 insertions(+), 39 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_pcidio.c b/drivers/staging/comedi/drivers/ni_pcidio.c index 2d88a5be65ff..9d337516409d 100644 --- a/drivers/staging/comedi/drivers/ni_pcidio.c +++ b/drivers/staging/comedi/drivers/ni_pcidio.c @@ -1,8 +1,8 @@ /* comedi/drivers/ni_pcidio.c driver for National Instruments PCI-DIO-96/PCI-6508 - National Instruments PCI-DIO-32HS - National Instruments PCI-6503 + National Instruments PCI-DIO-32HS + National Instruments PCI-6503 COMEDI - Linux Control and Measurement Device Interface Copyright (C) 1999,2002 David A. Schleef @@ -518,7 +518,8 @@ static irqreturn_t nidio_interrupt(int irq, void *d) ni_pcidio_print_status(status); /* printk("buf[0]=%08x\n",*(unsigned int *)async->prealloc_buf); */ - /* printk("buf[4096]=%08x\n",*(unsigned int *)(async->prealloc_buf+4096)); */ + /* printk("buf[4096]=%08x\n", + *(unsigned int *)(async->prealloc_buf+4096)); */ spin_lock_irqsave(&devpriv->mite_channel_lock, irq_flags); if (devpriv->di_mite_chan) @@ -526,7 +527,9 @@ static irqreturn_t nidio_interrupt(int irq, void *d) #ifdef MITE_DEBUG mite_print_chsr(m_status); #endif - /* printk("mite_bytes_transferred: %d\n",mite_bytes_transferred(mite,DI_DMA_CHAN)); */ + /* printk("mite_bytes_transferred: %d\n", + mite_bytes_transferred(mite,DI_DMA_CHAN)); */ + /* mite_dump_regs(mite); */ if (m_status & CHSR_INT) { if (m_status & CHSR_LINKC) { @@ -565,7 +568,8 @@ static irqreturn_t nidio_interrupt(int irq, void *d) DPRINTK("too much work in interrupt\n"); writeb(0x00, devpriv->mite->daq_io_addr + - Master_DMA_And_Interrupt_Control); + Master_DMA_And_Interrupt_Control + ); goto out; } AuxData = @@ -579,8 +583,10 @@ static irqreturn_t nidio_interrupt(int irq, void *d) flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags); } - /* DPRINTK("buf_int_count: %d\n",async->buf_int_count); */ - /* DPRINTK("1) IntEn=%d,flags=%d,status=%d\n",IntEn,flags,status); */ + /* DPRINTK("buf_int_count: %d\n", + async->buf_int_count); */ + /* DPRINTK("1) IntEn=%d,flags=%d,status=%d\n", + IntEn,flags,status); */ /* ni_pcidio_print_flags(flags); */ /* ni_pcidio_print_status(status); */ async->events |= COMEDI_CB_BLOCK; @@ -627,8 +633,8 @@ static irqreturn_t nidio_interrupt(int irq, void *d) flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags); status = readb(devpriv->mite->daq_io_addr + Interrupt_And_Window_Status); - /* DPRINTK("loop end: IntEn=0x%02x,flags=0x%02x,status=0x%02x\n", */ - /* IntEn,flags,status); */ + /* DPRINTK("loop end: IntEn=0x%02x,flags=0x%02x," + "status=0x%02x\n", IntEn, flags, status); */ /* ni_pcidio_print_flags(flags); */ /* ni_pcidio_print_status(status); */ } @@ -655,11 +661,10 @@ static void ni_pcidio_print_flags(unsigned int flags) { int i; - printk("group_1_flags:"); + printk(KERN_INFO "group_1_flags:"); for (i = 7; i >= 0; i--) { - if (flags & (1 << i)) { + if (flags & (1 << i)) printk(" %s", flags_strings[i]); - } } printk("\n"); } @@ -673,11 +678,10 @@ static void ni_pcidio_print_status(unsigned int flags) { int i; - printk("group_status:"); + printk(KERN_INFO "group_status:"); for (i = 7; i >= 0; i--) { - if (flags & (1 << i)) { + if (flags & (1 << i)) printk(" %s", status_strings[i]); - } } printk("\n"); } @@ -793,7 +797,8 @@ static int ni_pcidio_cmdtest(struct comedi_device *dev, if (err) return 1; - /* step 2: make sure trigger sources are unique and mutually compatible */ + /* step 2: make sure trigger sources are unique and mutually + compatible */ /* note that mutual compatibility is not an issue here */ if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_INT) @@ -974,7 +979,8 @@ static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) /* clear and enable interrupts */ writeb(0xff, devpriv->mite->daq_io_addr + Group_1_First_Clear); - /* writeb(ClearExpired,devpriv->mite->daq_io_addr+Group_1_Second_Clear); */ + /* writeb(ClearExpired, + devpriv->mite->daq_io_addr+Group_1_Second_Clear); */ writeb(IntEn, devpriv->mite->daq_io_addr + Interrupt_Control); writeb(0x03, @@ -1052,7 +1058,7 @@ static int ni_pcidio_change(struct comedi_device *dev, } static int pci_6534_load_fpga(struct comedi_device *dev, int fpga_index, - u8 * data, int data_len) + u8 *data, int data_len) { static const int timeout = 1000; int i, j; @@ -1066,9 +1072,8 @@ static int pci_6534_load_fpga(struct comedi_device *dev, int fpga_index, udelay(1); } if (i == timeout) { - printk - ("ni_pcidio: failed to load fpga %i, waiting for status 0x2\n", - fpga_index); + printk(KERN_WARNING "ni_pcidio: failed to load fpga %i, " + "waiting for status 0x2\n", fpga_index); return -EIO; } writew(0x80 | fpga_index, @@ -1079,9 +1084,8 @@ static int pci_6534_load_fpga(struct comedi_device *dev, int fpga_index, udelay(1); } if (i == timeout) { - printk - ("ni_pcidio: failed to load fpga %i, waiting for status 0x3\n", - fpga_index); + printk(KERN_WARNING "ni_pcidio: failed to load fpga %i, " + "waiting for status 0x3\n", fpga_index); return -EIO; } for (j = 0; j + 1 < data_len;) { @@ -1174,9 +1178,10 @@ static int nidio_attach(struct comedi_device *dev, struct comedi_devconfig *it) int n_subdevices; unsigned int irq; - printk("comedi%d: nidio:", dev->minor); + printk(KERN_INFO "comedi%d: nidio:", dev->minor); - if ((ret = alloc_private(dev, sizeof(struct nidio96_private))) < 0) + ret = alloc_private(dev, sizeof(struct nidio96_private)); + if (ret < 0) return ret; spin_lock_init(&devpriv->mite_channel_lock); @@ -1186,7 +1191,7 @@ static int nidio_attach(struct comedi_device *dev, struct comedi_devconfig *it) ret = mite_setup(devpriv->mite); if (ret < 0) { - printk("error setting up mite\n"); + printk(KERN_WARNING "error setting up mite\n"); return ret; } comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev); @@ -1196,18 +1201,19 @@ static int nidio_attach(struct comedi_device *dev, struct comedi_devconfig *it) dev->board_name = this_board->name; irq = mite_irq(devpriv->mite); - printk(" %s", dev->board_name); + printk(KERN_INFO " %s", dev->board_name); if (this_board->uses_firmware) { ret = pci_6534_upload_firmware(dev, it->options); if (ret < 0) return ret; } - if (!this_board->is_diodaq) { + if (!this_board->is_diodaq) n_subdevices = this_board->n_8255; - } else { + else n_subdevices = 1; - } - if ((ret = alloc_subdevices(dev, n_subdevices)) < 0) + + ret = alloc_subdevices(dev, n_subdevices); + if (ret < 0) return ret; if (!this_board->is_diodaq) { @@ -1220,7 +1226,7 @@ static int nidio_attach(struct comedi_device *dev, struct comedi_devconfig *it) } } else { - printk(" rev=%d", + printk(KERN_INFO " rev=%d", readb(devpriv->mite->daq_io_addr + Chip_Version)); s = dev->subdevices + 0; @@ -1253,9 +1259,9 @@ static int nidio_attach(struct comedi_device *dev, struct comedi_devconfig *it) ret = request_irq(irq, nidio_interrupt, IRQF_SHARED, "ni_pcidio", dev); - if (ret < 0) { - printk(" irq not available"); - } + if (ret < 0) + printk(KERN_WARNING " irq not available"); + dev->irq = irq; } @@ -1269,9 +1275,8 @@ static int nidio_detach(struct comedi_device *dev) int i; if (this_board && !this_board->is_diodaq) { - for (i = 0; i < this_board->n_8255; i++) { + for (i = 0; i < this_board->n_8255; i++) subdev_8255_cleanup(dev, dev->subdevices + i); - } } if (dev->irq) @@ -1310,7 +1315,7 @@ static int nidio_find_device(struct comedi_device *dev, int bus, int slot) } } } - printk("no device found\n"); + printk(KERN_WARNING "no device found\n"); mite_list_devices(); return -EIO; } -- cgit v1.2.3 From dee86e8c9279110d787da64cbca5d4bda63d93c6 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sun, 7 Feb 2010 08:51:51 -0800 Subject: Staging: comedi: ssc_dnp: fixed a brace coding style issue Fixed a coding style issue. Created during the keynote presentation at FOSDEM 2010 Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ssv_dnp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ssv_dnp.c b/drivers/staging/comedi/drivers/ssv_dnp.c index 4918fbfab5e8..17c92a57b0dd 100644 --- a/drivers/staging/comedi/drivers/ssv_dnp.c +++ b/drivers/staging/comedi/drivers/ssv_dnp.c @@ -300,11 +300,11 @@ static int dnp_dio_insn_config(struct comedi_device *dev, /* read 'old' direction of the port and set bits (out=1, in=0) */ register_buffer = inb(CSCDR); - if (data[0] == COMEDI_OUTPUT) { + if (data[0] == COMEDI_OUTPUT) register_buffer |= (1 << chan); - } else { + else register_buffer &= ~(1 << chan); - } + outb(register_buffer, CSCDR); return 1; -- cgit v1.2.3 From f721ad7a9c4cec5b151134b2ace164861aca0df9 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 9 Feb 2010 12:37:25 -0800 Subject: Staging: dt3155: fix build warnings This fixes the build warnings in the dt3155 driver Cc: Scott Smedley Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dt3155/dt3155_drv.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dt3155/dt3155_drv.c b/drivers/staging/dt3155/dt3155_drv.c index 6b40d422ad0c..716814ed42bb 100644 --- a/drivers/staging/dt3155/dt3155_drv.c +++ b/drivers/staging/dt3155/dt3155_drv.c @@ -538,8 +538,11 @@ static int dt3155_ioctl ( { printk("DT3155: invalid IOCTL(0x%x)\n",cmd); printk("DT3155: Valid commands (0x%x), (0x%x), (0x%x), (0x%x), (0x%x)\n", - DT3155_GET_CONFIG, DT3155_SET_CONFIG, - DT3155_START, DT3155_STOP, DT3155_FLUSH); + (unsigned int)DT3155_GET_CONFIG, + (unsigned int)DT3155_SET_CONFIG, + (unsigned int)DT3155_START, + (unsigned int)DT3155_STOP, + (unsigned int)DT3155_FLUSH); return -EINVAL; } @@ -624,7 +627,8 @@ static int dt3155_ioctl ( { printk("DT3155: invalid IOCTL(0x%x)\n",cmd); printk("DT3155: Valid commands (0x%x), (0x%x), (0x%x), (0x%x), (0x%x)\n", - DT3155_GET_CONFIG, DT3155_SET_CONFIG, + (unsigned int)DT3155_GET_CONFIG, + (unsigned int)DT3155_SET_CONFIG, DT3155_START, DT3155_STOP, DT3155_FLUSH); return -ENOSYS; } @@ -754,11 +758,8 @@ static int dt3155_close( struct inode *inode, struct file *filep) * read() * *****************************************************/ -static int dt3155_read ( - struct file *filep, - char *buf, - size_t count, - loff_t *ppos) +static ssize_t dt3155_read(struct file *filep, char __user *buf, + size_t count, loff_t *ppos) { /* which device are we reading from? */ int minor = MINOR(filep->f_dentry->d_inode->i_rdev); @@ -911,8 +912,8 @@ static int find_PCI (void) * can access it. */ dt3155_lbase[ pci_index - 1 ] = ioremap(base,PCI_PAGE_SIZE); dt3155_status[ pci_index - 1 ].reg_addr = base; - DT_3155_DEBUG_MSG("DT3155: New logical address is x%x \n", - (u_int)dt3155_lbase[pci_index-1]); + DT_3155_DEBUG_MSG("DT3155: New logical address is %p \n", + dt3155_lbase[pci_index-1]); if ( !dt3155_lbase[pci_index-1] ) { printk("DT3155: Unable to remap control registers\n"); @@ -929,10 +930,10 @@ static int find_PCI (void) dt3155_status[ pci_index-1 ].irq = irq; /* Set flag: kth device found! */ dt3155_status[ pci_index-1 ].device_installed = 1; - printk("DT3155: Installing device %d w/irq %d and address 0x%x\n", + printk("DT3155: Installing device %d w/irq %d and address %p\n", pci_index, (u_int)dt3155_status[pci_index-1].irq, - (u_int)dt3155_lbase[pci_index-1]); + dt3155_lbase[pci_index-1]); } ndevices = pci_index; -- cgit v1.2.3 From 062d164719fcbffae6e2fe5e7ba5ab68da12ce33 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 9 Feb 2010 12:38:13 -0800 Subject: Staging: dt3155: coding cleanups for dt3155_io.h This fixes up some coding style issues in the dt3155_io.h file Cc: Scott Smedley Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dt3155/dt3155_io.h | 463 +++++++++++++++++-------------------- 1 file changed, 212 insertions(+), 251 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dt3155/dt3155_io.h b/drivers/staging/dt3155/dt3155_io.h index 67df27fc6a8a..72d655dae5a2 100644 --- a/drivers/staging/dt3155/dt3155_io.h +++ b/drivers/staging/dt3155/dt3155_io.h @@ -43,258 +43,219 @@ MA 02111-1307 USA /* offsets for 32-bit memory mapped registers */ -#define EVEN_DMA_START 0x000 -#define ODD_DMA_START 0x00C -#define EVEN_DMA_STRIDE 0x018 -#define ODD_DMA_STRIDE 0x024 -#define EVEN_PIXEL_FMT 0x030 -#define ODD_PIXEL_FMT 0x034 -#define FIFO_TRIGGER 0x038 -#define XFER_MODE 0x03C -#define CSR1 0x040 -#define RETRY_WAIT_CNT 0x044 -#define INT_CSR 0x048 -#define EVEN_FLD_MASK 0x04C -#define ODD_FLD_MASK 0x050 -#define MASK_LENGTH 0x054 -#define FIFO_FLAG_CNT 0x058 -#define IIC_CLK_DUR 0x05C -#define IIC_CSR1 0x060 -#define IIC_CSR2 0x064 -#define EVEN_DMA_UPPR_LMT 0x08C -#define ODD_DMA_UPPR_LMT 0x090 - -#define CLK_DUR_VAL 0x01010101 +#define EVEN_DMA_START 0x000 +#define ODD_DMA_START 0x00C +#define EVEN_DMA_STRIDE 0x018 +#define ODD_DMA_STRIDE 0x024 +#define EVEN_PIXEL_FMT 0x030 +#define ODD_PIXEL_FMT 0x034 +#define FIFO_TRIGGER 0x038 +#define XFER_MODE 0x03C +#define CSR1 0x040 +#define RETRY_WAIT_CNT 0x044 +#define INT_CSR 0x048 +#define EVEN_FLD_MASK 0x04C +#define ODD_FLD_MASK 0x050 +#define MASK_LENGTH 0x054 +#define FIFO_FLAG_CNT 0x058 +#define IIC_CLK_DUR 0x05C +#define IIC_CSR1 0x060 +#define IIC_CSR2 0x064 +#define EVEN_DMA_UPPR_LMT 0x08C +#define ODD_DMA_UPPR_LMT 0x090 + +#define CLK_DUR_VAL 0x01010101 /******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/ -/********************************** - * fifo_trigger_tag - */ typedef union fifo_trigger_tag { - u_long reg; - struct - { - u_long PACKED : 6; - u_long : 9; - u_long PLANER : 7; - u_long : 9; - } fld; + u_long reg; + struct { + u_long PACKED:6; + u_long :9; + u_long PLANER:7; + u_long :9; + } fld; } FIFO_TRIGGER_R; -/********************************** - * xfer_mode_tag - */ typedef union xfer_mode_tag { - u_long reg; - struct - { - u_long : 2; - u_long FIELD_TOGGLE : 1; - u_long : 5; - u_long : 2; - u_long : 22; - } fld; + u_long reg; + struct { + u_long :2; + u_long FIELD_TOGGLE:1; + u_long :5; + u_long :2; + u_long :22; + } fld; } XFER_MODE_R; -/********************************** - * csr1_tag - */ typedef union csr1_tag { - u_long reg; - struct - { - u_long CAP_CONT_EVE : 1; - u_long CAP_CONT_ODD : 1; - u_long CAP_SNGL_EVE : 1; - u_long CAP_SNGL_ODD : 1; - u_long FLD_DN_EVE : 1; - u_long FLD_DN_ODD : 1; - u_long SRST : 1; - u_long FIFO_EN : 1; - u_long FLD_CRPT_EVE : 1; - u_long FLD_CRPT_ODD : 1; - u_long ADDR_ERR_EVE : 1; - u_long ADDR_ERR_ODD : 1; - u_long CRPT_DIS : 1; - u_long RANGE_EN : 1; - u_long : 16; - } fld; + u_long reg; + struct { + u_long CAP_CONT_EVE:1; + u_long CAP_CONT_ODD:1; + u_long CAP_SNGL_EVE:1; + u_long CAP_SNGL_ODD:1; + u_long FLD_DN_EVE :1; + u_long FLD_DN_ODD :1; + u_long SRST :1; + u_long FIFO_EN :1; + u_long FLD_CRPT_EVE:1; + u_long FLD_CRPT_ODD:1; + u_long ADDR_ERR_EVE:1; + u_long ADDR_ERR_ODD:1; + u_long CRPT_DIS :1; + u_long RANGE_EN :1; + u_long :16; + } fld; } CSR1_R; -/********************************** - * retry_wait_cnt_tag - */ typedef union retry_wait_cnt_tag { - u_long reg; - struct - { - u_long RTRY_WAIT_CNT : 8; - u_long : 24; - } fld; + u_long reg; + struct { + u_long RTRY_WAIT_CNT:8; + u_long :24; + } fld; } RETRY_WAIT_CNT_R; -/********************************** - * int_csr_tag - */ typedef union int_csr_tag { - u_long reg; - struct - { - u_long FLD_END_EVE : 1; - u_long FLD_END_ODD : 1; - u_long FLD_START : 1; - u_long : 5; - u_long FLD_END_EVE_EN : 1; - u_long FLD_END_ODD_EN : 1; - u_long FLD_START_EN : 1; - u_long : 21; - } fld; + u_long reg; + struct { + u_long FLD_END_EVE :1; + u_long FLD_END_ODD :1; + u_long FLD_START :1; + u_long :5; + u_long FLD_END_EVE_EN:1; + u_long FLD_END_ODD_EN:1; + u_long FLD_START_EN :1; + u_long :21; + } fld; } INT_CSR_R; -/********************************** - * mask_length_tag - */ typedef union mask_length_tag { - u_long reg; - struct - { - u_long MASK_LEN_EVE : 5; - u_long : 11; - u_long MASK_LEN_ODD : 5; - u_long : 11; - } fld; + u_long reg; + struct { + u_long MASK_LEN_EVE:5; + u_long :11; + u_long MASK_LEN_ODD:5; + u_long :11; + } fld; } MASK_LENGTH_R; -/********************************** - * fifo_flag_cnt_tag - */ typedef union fifo_flag_cnt_tag { - u_long reg; - struct - { - u_long AF_COUNT : 7; - u_long : 9; - u_long AE_COUNT : 7; - u_long : 9; - } fld; + u_long reg; + struct { + u_long AF_COUNT:7; + u_long :9; + u_long AE_COUNT:7; + u_long :9; + } fld; } FIFO_FLAG_CNT_R; -/********************************** - * iic_clk_dur - */ typedef union iic_clk_dur { - u_long reg; - struct - { - u_long PHASE_1 : 8; - u_long PHASE_2 : 8; - u_long PHASE_3 : 8; - u_long PHASE_4 : 8; - } fld; + u_long reg; + struct { + u_long PHASE_1:8; + u_long PHASE_2:8; + u_long PHASE_3:8; + u_long PHASE_4:8; + } fld; } IIC_CLK_DUR_R; -/********************************** - * iic_csr1_tag - */ typedef union iic_csr1_tag { - u_long reg; - struct - { - u_long AUTO_EN : 1; - u_long BYPASS : 1; - u_long SDA_OUT : 1; - u_long SCL_OUT : 1; - u_long : 4; - u_long AUTO_ABORT : 1; - u_long DIRECT_ABORT : 1; - u_long SDA_IN : 1; - u_long SCL_IN : 1; - u_long : 4; - u_long AUTO_ADDR : 8; - u_long RD_DATA : 8; - } fld; + u_long reg; + struct { + u_long AUTO_EN :1; + u_long BYPASS :1; + u_long SDA_OUT :1; + u_long SCL_OUT :1; + u_long :4; + u_long AUTO_ABORT :1; + u_long DIRECT_ABORT:1; + u_long SDA_IN :1; + u_long SCL_IN :1; + u_long :4; + u_long AUTO_ADDR :8; + u_long RD_DATA :8; + } fld; } IIC_CSR1_R; /********************************** * iic_csr2_tag */ typedef union iic_csr2_tag { - u_long reg; - struct - { - u_long DIR_WR_DATA : 8; - u_long DIR_SUB_ADDR : 8; - u_long DIR_RD : 1; - u_long DIR_ADDR : 7; - u_long NEW_CYCLE : 1; - u_long : 7; - } fld; + u_long reg; + struct { + u_long DIR_WR_DATA :8; + u_long DIR_SUB_ADDR:8; + u_long DIR_RD :1; + u_long DIR_ADDR :7; + u_long NEW_CYCLE :1; + u_long :7; + } fld; } IIC_CSR2_R; -/* use for both EVEN and ODD DMA UPPER LIMITS */ +/* use for both EVEN and ODD DMA UPPER LIMITS */ -/********************************** +/* * dma_upper_lmt_tag */ typedef union dma_upper_lmt_tag { u_long reg; struct { u_long DMA_UPPER_LMT_VAL:24; - u_long :8; + u_long :8; } fld; } DMA_UPPER_LMT_R; -/*************************************** - * Global declarations of local copies - * of boards' 32 bit registers - ***************************************/ -extern u_long even_dma_start_r; /* bit 0 should always be 0 */ -extern u_long odd_dma_start_r; /* .. */ -extern u_long even_dma_stride_r; /* bits 0&1 should always be 0 */ -extern u_long odd_dma_stride_r; /* .. */ +/* + * Global declarations of local copies of boards' 32 bit registers + */ +extern u_long even_dma_start_r; /* bit 0 should always be 0 */ +extern u_long odd_dma_start_r; /* .. */ +extern u_long even_dma_stride_r; /* bits 0&1 should always be 0 */ +extern u_long odd_dma_stride_r; /* .. */ extern u_long even_pixel_fmt_r; extern u_long odd_pixel_fmt_r; -extern FIFO_TRIGGER_R fifo_trigger_r; -extern XFER_MODE_R xfer_mode_r; -extern CSR1_R csr1_r; -extern RETRY_WAIT_CNT_R retry_wait_cnt_r; -extern INT_CSR_R int_csr_r; +extern FIFO_TRIGGER_R fifo_trigger_r; +extern XFER_MODE_R xfer_mode_r; +extern CSR1_R csr1_r; +extern RETRY_WAIT_CNT_R retry_wait_cnt_r; +extern INT_CSR_R int_csr_r; extern u_long even_fld_mask_r; extern u_long odd_fld_mask_r; -extern MASK_LENGTH_R mask_length_r; -extern FIFO_FLAG_CNT_R fifo_flag_cnt_r; -extern IIC_CLK_DUR_R iic_clk_dur_r; -extern IIC_CSR1_R iic_csr1_r; -extern IIC_CSR2_R iic_csr2_r; -extern DMA_UPPER_LMT_R even_dma_upper_lmt_r; -extern DMA_UPPER_LMT_R odd_dma_upper_lmt_r; +extern MASK_LENGTH_R mask_length_r; +extern FIFO_FLAG_CNT_R fifo_flag_cnt_r; +extern IIC_CLK_DUR_R iic_clk_dur_r; +extern IIC_CSR1_R iic_csr1_r; +extern IIC_CSR2_R iic_csr2_r; +extern DMA_UPPER_LMT_R even_dma_upper_lmt_r; +extern DMA_UPPER_LMT_R odd_dma_upper_lmt_r; /***************** 8 bit I2C register globals ***********/ - -#define CSR2 0x010 /* indices of 8-bit I2C mapped reg's*/ -#define EVEN_CSR 0x011 -#define ODD_CSR 0x012 -#define CONFIG 0x013 -#define DT_ID 0x01F -#define X_CLIP_START 0x020 -#define Y_CLIP_START 0x022 -#define X_CLIP_END 0x024 -#define Y_CLIP_END 0x026 -#define AD_ADDR 0x030 -#define AD_LUT 0x031 -#define AD_CMD 0x032 -#define DIG_OUT 0x040 -#define PM_LUT_ADDR 0x050 -#define PM_LUT_DATA 0x051 +#define CSR2 0x010 /* indices of 8-bit I2C mapped reg's*/ +#define EVEN_CSR 0x011 +#define ODD_CSR 0x012 +#define CONFIG 0x013 +#define DT_ID 0x01F +#define X_CLIP_START 0x020 +#define Y_CLIP_START 0x022 +#define X_CLIP_END 0x024 +#define Y_CLIP_END 0x026 +#define AD_ADDR 0x030 +#define AD_LUT 0x031 +#define AD_CMD 0x032 +#define DIG_OUT 0x040 +#define PM_LUT_ADDR 0x050 +#define PM_LUT_DATA 0x051 /******** Assignments and Typedefs for 8 bit I2C Registers********************/ @@ -315,77 +276,77 @@ typedef union i2c_csr2_tag { typedef union i2c_even_csr_tag { u_char reg; struct { - u_char DONE_EVE:1; - u_char SNGL_EVE:1; + u_char DONE_EVE :1; + u_char SNGL_EVE :1; u_char ERROR_EVE:1; - u_char :5; + u_char :5; } fld; } I2C_EVEN_CSR; typedef union i2c_odd_csr_tag { - u_char reg; - struct - { - u_char DONE_ODD : 1; - u_char SNGL_ODD : 1; - u_char ERROR_ODD : 1; - u_char : 5; - } fld; + u_char reg; + struct { + u_char DONE_ODD:1; + u_char SNGL_ODD:1; + u_char ERROR_ODD:1; + u_char :5; + } fld; } I2C_ODD_CSR; typedef union i2c_config_tag { - u_char reg; - struct - { - u_char ACQ_MODE : 2; - u_char EXT_TRIG_EN : 1; - u_char EXT_TRIG_POL : 1; - u_char H_SCALE : 1; - u_char CLIP : 1; - u_char PM_LUT_SEL : 1; - u_char PM_LUT_PGM : 1; - } fld; -} I2C_CONFIG; - - -typedef union i2c_ad_cmd_tag { /* bits can have 3 different meanings - depending on value of AD_ADDR */ - u_char reg; - struct - { - u_char : 2; - u_char SYNC_LVL_SEL : 2; - u_char SYNC_CNL_SEL : 2; - u_char DIGITIZE_CNL_SEL1 : 2; - } bt252_command; /* Bt252 Command Register */ - struct /* if AD_ADDR = 00h */ - { - u_char IOUT_DATA : 8; - } bt252_iout0; /* Bt252 IOUT0 register */ - struct /* if AD_ADDR = 01h */ - { - u_char IOUT_DATA : 8; - } bt252_iout1; /* BT252 IOUT1 register */ -} I2C_AD_CMD; /* if AD_ADDR = 02h */ + u_char reg; + struct { + u_char ACQ_MODE:2; + u_char EXT_TRIG_EN:1; + u_char EXT_TRIG_POL:1; + u_char H_SCALE:1; + u_char CLIP:1; + u_char PM_LUT_SEL:1; + u_char PM_LUT_PGM:1; + } fld; +} I2C_CONFIG; + + +typedef union i2c_ad_cmd_tag { + /* bits can have 3 different meanings depending on value of AD_ADDR */ + u_char reg; + /* Bt252 Command Register if AD_ADDR = 00h */ + struct { + u_char :2; + u_char SYNC_LVL_SEL:2; + u_char SYNC_CNL_SEL:2; + u_char DIGITIZE_CNL_SEL1:2; + } bt252_command; + + /* Bt252 IOUT0 register if AD_ADDR = 01h */ + struct { + u_char IOUT_DATA:8; + } bt252_iout0; + + /* BT252 IOUT1 register if AD_ADDR = 02h */ + struct { + u_char IOUT_DATA:8; + } bt252_iout1; +} I2C_AD_CMD; /***** Global declarations of local copies of boards' 8 bit I2C registers ***/ -extern I2C_CSR2 i2c_csr2; -extern I2C_EVEN_CSR i2c_even_csr; -extern I2C_ODD_CSR i2c_odd_csr; -extern I2C_CONFIG i2c_config; -extern u_char i2c_dt_id; -extern u_char i2c_x_clip_start; -extern u_char i2c_y_clip_start; -extern u_char i2c_x_clip_end; -extern u_char i2c_y_clip_end; -extern u_char i2c_ad_addr; -extern u_char i2c_ad_lut; -extern I2C_AD_CMD i2c_ad_cmd; -extern u_char i2c_dig_out; -extern u_char i2c_pm_lut_addr; -extern u_char i2c_pm_lut_data; +extern I2C_CSR2 i2c_csr2; +extern I2C_EVEN_CSR i2c_even_csr; +extern I2C_ODD_CSR i2c_odd_csr; +extern I2C_CONFIG i2c_config; +extern u_char i2c_dt_id; +extern u_char i2c_x_clip_start; +extern u_char i2c_y_clip_start; +extern u_char i2c_x_clip_end; +extern u_char i2c_y_clip_end; +extern u_char i2c_ad_addr; +extern u_char i2c_ad_lut; +extern I2C_AD_CMD i2c_ad_cmd; +extern u_char i2c_dig_out; +extern u_char i2c_pm_lut_addr; +extern u_char i2c_pm_lut_data; /* Functions for Global use */ -- cgit v1.2.3 From 5d3921117d7c3bfec5a5877ba0be0430e2aec491 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 9 Feb 2010 12:41:38 -0800 Subject: Staging: dt3155: replace u_char usage Use u8 instead, that's the proper thing to do. Cc: Scott Smedley Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dt3155/dt3155_drv.c | 4 +- drivers/staging/dt3155/dt3155_drv.h | 4 +- drivers/staging/dt3155/dt3155_io.c | 30 ++++++------- drivers/staging/dt3155/dt3155_io.h | 90 ++++++++++++++++++------------------- drivers/staging/dt3155/dt3155_isr.c | 2 +- 5 files changed, 65 insertions(+), 65 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dt3155/dt3155_drv.c b/drivers/staging/dt3155/dt3155_drv.c index 716814ed42bb..76f8a78c01e7 100644 --- a/drivers/staging/dt3155/dt3155_drv.c +++ b/drivers/staging/dt3155/dt3155_drv.c @@ -122,13 +122,13 @@ int dt3155_major = 0; struct dt3155_status_s dt3155_status[ MAXBOARDS ]; /* kernel logical address of the board */ -u_char *dt3155_lbase[ MAXBOARDS ] = { NULL +u8 *dt3155_lbase[ MAXBOARDS ] = { NULL #if MAXBOARDS == 2 , NULL #endif }; /* DT3155 registers */ -u_char *dt3155_bbase = NULL; /* kernel logical address of the * +u8 *dt3155_bbase = NULL; /* kernel logical address of the * * buffer region */ u_int dt3155_dev_open[ MAXBOARDS ] = {0 #if MAXBOARDS == 2 diff --git a/drivers/staging/dt3155/dt3155_drv.h b/drivers/staging/dt3155/dt3155_drv.h index 215399a3d26a..1006cf5410da 100644 --- a/drivers/staging/dt3155/dt3155_drv.h +++ b/drivers/staging/dt3155/dt3155_drv.h @@ -25,10 +25,10 @@ MA 02111-1307 USA #define DT3155_DRV_INC /* kernel logical address of the frame grabbers */ -extern u_char *dt3155_lbase[MAXBOARDS]; +extern u8 *dt3155_lbase[MAXBOARDS]; /* kernel logical address of ram buffer */ -extern u_char *dt3155_bbase; +extern u8 *dt3155_bbase; #ifdef __KERNEL__ #include diff --git a/drivers/staging/dt3155/dt3155_io.c b/drivers/staging/dt3155/dt3155_io.c index 6d516863d1ae..b0f1a78074a1 100644 --- a/drivers/staging/dt3155/dt3155_io.c +++ b/drivers/staging/dt3155/dt3155_io.c @@ -86,17 +86,17 @@ I2C_CSR2 i2c_csr2; I2C_EVEN_CSR i2c_even_csr; I2C_ODD_CSR i2c_odd_csr; I2C_CONFIG i2c_config; -u_char i2c_dt_id; -u_char i2c_x_clip_start; -u_char i2c_y_clip_start; -u_char i2c_x_clip_end; -u_char i2c_y_clip_end; -u_char i2c_ad_addr; -u_char i2c_ad_lut; +u8 i2c_dt_id; +u8 i2c_x_clip_start; +u8 i2c_y_clip_start; +u8 i2c_x_clip_end; +u8 i2c_y_clip_end; +u8 i2c_ad_addr; +u8 i2c_ad_lut; I2C_AD_CMD i2c_ad_cmd; -u_char i2c_dig_out; -u_char i2c_pm_lut_addr; -u_char i2c_pm_lut_data; +u8 i2c_dig_out; +u8 i2c_pm_lut_addr; +u8 i2c_pm_lut_data; // return the time difference (in microseconds) b/w & . @@ -117,7 +117,7 @@ long elapsed2 (const struct timeval *pStart, const struct timeval *pEnd) otherwise returns 0 ***********************************************************************/ -int wait_ibsyclr(u_char * lpReg) +int wait_ibsyclr(u8 * lpReg) { /* wait 100 microseconds */ @@ -168,7 +168,7 @@ int wait_ibsyclr(u_char * lpReg) Returns TRUE - Successful completion FALSE - Timeout error - cycle did not complete! ***********************************************************************/ -int WriteI2C (u_char * lpReg, u_short wIregIndex, u_char byVal) +int WriteI2C (u8 * lpReg, u_short wIregIndex, u8 byVal) { int writestat; /* status for return */ @@ -203,7 +203,7 @@ int WriteI2C (u_char * lpReg, u_short wIregIndex, u_char byVal) Returns TRUE - Successful completion FALSE - Timeout error - cycle did not complete! ***********************************************************************/ -int ReadI2C (u_char * lpReg, u_short wIregIndex, u_char * byVal) +int ReadI2C (u8 * lpReg, u_short wIregIndex, u8 * byVal) { int writestat; /* status for return */ @@ -229,8 +229,8 @@ int ReadI2C (u_char * lpReg, u_short wIregIndex, u_char * byVal) /* first read data is in IIC_CSR1 */ ReadMReg((lpReg + IIC_CSR1), iic_csr1_r.reg); - /* now get data u_char out of register */ - *byVal = (u_char) iic_csr1_r.fld.RD_DATA; + /* now get data u8 out of register */ + *byVal = (u8) iic_csr1_r.fld.RD_DATA; return writestat; /* return with status */ } diff --git a/drivers/staging/dt3155/dt3155_io.h b/drivers/staging/dt3155/dt3155_io.h index 72d655dae5a2..dd25a79bdee9 100644 --- a/drivers/staging/dt3155/dt3155_io.h +++ b/drivers/staging/dt3155/dt3155_io.h @@ -261,71 +261,71 @@ extern DMA_UPPER_LMT_R odd_dma_upper_lmt_r; /******** Assignments and Typedefs for 8 bit I2C Registers********************/ typedef union i2c_csr2_tag { - u_char reg; + u8 reg; struct { - u_char CHROM_FIL:1; - u_char SYNC_SNTL:1; - u_char HZ50:1; - u_char SYNC_PRESENT:1; - u_char BUSY_EVE:1; - u_char BUSY_ODD:1; - u_char DISP_PASS:1; + u8 CHROM_FIL:1; + u8 SYNC_SNTL:1; + u8 HZ50:1; + u8 SYNC_PRESENT:1; + u8 BUSY_EVE:1; + u8 BUSY_ODD:1; + u8 DISP_PASS:1; } fld; } I2C_CSR2; typedef union i2c_even_csr_tag { - u_char reg; + u8 reg; struct { - u_char DONE_EVE :1; - u_char SNGL_EVE :1; - u_char ERROR_EVE:1; - u_char :5; + u8 DONE_EVE :1; + u8 SNGL_EVE :1; + u8 ERROR_EVE:1; + u8 :5; } fld; } I2C_EVEN_CSR; typedef union i2c_odd_csr_tag { - u_char reg; + u8 reg; struct { - u_char DONE_ODD:1; - u_char SNGL_ODD:1; - u_char ERROR_ODD:1; - u_char :5; + u8 DONE_ODD:1; + u8 SNGL_ODD:1; + u8 ERROR_ODD:1; + u8 :5; } fld; } I2C_ODD_CSR; typedef union i2c_config_tag { - u_char reg; + u8 reg; struct { - u_char ACQ_MODE:2; - u_char EXT_TRIG_EN:1; - u_char EXT_TRIG_POL:1; - u_char H_SCALE:1; - u_char CLIP:1; - u_char PM_LUT_SEL:1; - u_char PM_LUT_PGM:1; + u8 ACQ_MODE:2; + u8 EXT_TRIG_EN:1; + u8 EXT_TRIG_POL:1; + u8 H_SCALE:1; + u8 CLIP:1; + u8 PM_LUT_SEL:1; + u8 PM_LUT_PGM:1; } fld; } I2C_CONFIG; typedef union i2c_ad_cmd_tag { /* bits can have 3 different meanings depending on value of AD_ADDR */ - u_char reg; + u8 reg; /* Bt252 Command Register if AD_ADDR = 00h */ struct { - u_char :2; - u_char SYNC_LVL_SEL:2; - u_char SYNC_CNL_SEL:2; - u_char DIGITIZE_CNL_SEL1:2; + u8 :2; + u8 SYNC_LVL_SEL:2; + u8 SYNC_CNL_SEL:2; + u8 DIGITIZE_CNL_SEL1:2; } bt252_command; /* Bt252 IOUT0 register if AD_ADDR = 01h */ struct { - u_char IOUT_DATA:8; + u8 IOUT_DATA:8; } bt252_iout0; /* BT252 IOUT1 register if AD_ADDR = 02h */ struct { - u_char IOUT_DATA:8; + u8 IOUT_DATA:8; } bt252_iout1; } I2C_AD_CMD; @@ -336,23 +336,23 @@ extern I2C_CSR2 i2c_csr2; extern I2C_EVEN_CSR i2c_even_csr; extern I2C_ODD_CSR i2c_odd_csr; extern I2C_CONFIG i2c_config; -extern u_char i2c_dt_id; -extern u_char i2c_x_clip_start; -extern u_char i2c_y_clip_start; -extern u_char i2c_x_clip_end; -extern u_char i2c_y_clip_end; -extern u_char i2c_ad_addr; -extern u_char i2c_ad_lut; +extern u8 i2c_dt_id; +extern u8 i2c_x_clip_start; +extern u8 i2c_y_clip_start; +extern u8 i2c_x_clip_end; +extern u8 i2c_y_clip_end; +extern u8 i2c_ad_addr; +extern u8 i2c_ad_lut; extern I2C_AD_CMD i2c_ad_cmd; -extern u_char i2c_dig_out; -extern u_char i2c_pm_lut_addr; -extern u_char i2c_pm_lut_data; +extern u8 i2c_dig_out; +extern u8 i2c_pm_lut_addr; +extern u8 i2c_pm_lut_data; /* Functions for Global use */ /* access 8-bit IIC registers */ -extern int ReadI2C(u_char *lpReg, u_short wIregIndex, u_char *byVal); -extern int WriteI2C(u_char *lpReg, u_short wIregIndex, u_char byVal); +extern int ReadI2C(u8 *lpReg, u_short wIregIndex, u8 *byVal); +extern int WriteI2C(u8 *lpReg, u_short wIregIndex, u8 byVal); #endif diff --git a/drivers/staging/dt3155/dt3155_isr.c b/drivers/staging/dt3155/dt3155_isr.c index 54460dbb867a..faed085d4fc7 100644 --- a/drivers/staging/dt3155/dt3155_isr.c +++ b/drivers/staging/dt3155/dt3155_isr.c @@ -318,7 +318,7 @@ u_long dt3155_setup_buffers(u_long *allocatorAddr) /* Make sure the buffering variables are consistent */ { - u_char *ptr = (u_char *) dt3155_fbuffer[ m ]; + u8 *ptr = (u8 *) dt3155_fbuffer[ m ]; for( index = 0; index < sizeof(struct dt3155_fbuffer_s); index++) *(ptr++)=0; } -- cgit v1.2.3 From dcff74ce8b458792c1628ad9f3803fc648f94e11 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 9 Feb 2010 12:41:38 -0800 Subject: Staging: dt3155: replace u_int and u_long usage Use u32 and u64 instead, that's the proper thing to do. Cc: Scott Smedley Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dt3155/allocator.c | 4 +- drivers/staging/dt3155/allocator.h | 2 +- drivers/staging/dt3155/dt3155.h | 36 ++++---- drivers/staging/dt3155/dt3155_drv.c | 51 ++++++----- drivers/staging/dt3155/dt3155_drv.h | 2 +- drivers/staging/dt3155/dt3155_io.c | 16 ++-- drivers/staging/dt3155/dt3155_io.h | 174 ++++++++++++++++++------------------ drivers/staging/dt3155/dt3155_isr.c | 52 +++++------ drivers/staging/dt3155/dt3155_isr.h | 2 +- 9 files changed, 169 insertions(+), 170 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dt3155/allocator.c b/drivers/staging/dt3155/allocator.c index 4983c9379e57..114e2a86fefa 100644 --- a/drivers/staging/dt3155/allocator.c +++ b/drivers/staging/dt3155/allocator.c @@ -27,7 +27,7 @@ ------------------------------------------------------------------- 02-Aug-2002 NJC allocator now steps in 1MB increments, rather than doubling its size each time. - Also, allocator_init(u_int *) now returns + Also, allocator_init(u32 *) now returns (in the first arg) the size of the free space. This is no longer consistent with using the allocator as a module, and some changes @@ -195,7 +195,7 @@ int allocator_free_dma(unsigned long address) * On cleanup everything is released. If the list is not empty, that a * problem of our clients */ -int allocator_init(u_long *allocator_max) +int allocator_init(u64 *allocator_max) { /* check how much free memory is there */ void *remapped; diff --git a/drivers/staging/dt3155/allocator.h b/drivers/staging/dt3155/allocator.h index a2f90ffa3d10..4cd81bdb3faa 100644 --- a/drivers/staging/dt3155/allocator.h +++ b/drivers/staging/dt3155/allocator.h @@ -24,5 +24,5 @@ void allocator_free_dma(unsigned long address); unsigned long allocator_allocate_dma(unsigned long kilobytes, int priority); -int allocator_init(u_long *); +int allocator_init(u64 *); void allocator_cleanup(void); diff --git a/drivers/staging/dt3155/dt3155.h b/drivers/staging/dt3155/dt3155.h index 2a01e017d5fe..22292b102a33 100644 --- a/drivers/staging/dt3155/dt3155.h +++ b/drivers/staging/dt3155/dt3155.h @@ -35,7 +35,7 @@ MA 02111-1307 USA #define _DT3155_INC #ifdef __KERNEL__ -#include /* u_int etc. */ +#include #include /* struct timeval */ #else #include @@ -71,16 +71,16 @@ MA 02111-1307 USA /* Configuration structure */ struct dt3155_config_s { - u_int acq_mode; - u_int cols, rows; - u_int continuous; + u32 acq_mode; + u32 cols, rows; + u32 continuous; }; /* hold data for each frame */ typedef struct { - u_long addr; /* address of the buffer with the frame */ - u_long tag; /* unique number for the frame */ + u64 addr; /* address of the buffer with the frame */ + u64 tag; /* unique number for the frame */ struct timeval time; /* time that capture took place */ } frame_info_t; @@ -101,14 +101,14 @@ struct dt3155_fbuffer_s { int locked_buf; /* Buffers used by user */ int ready_que[BOARD_MAX_BUFFS]; - u_long ready_head; /* The most recent buffer located here */ - u_long ready_len; /* The number of ready buffers */ + u64 ready_head; /* The most recent buffer located here */ + u64 ready_len; /* The number of ready buffers */ int even_happened; int even_stopped; int stop_acquire; /* Flag to stop interrupts */ - u_long frame_count; /* Counter for frames acquired by this card */ + u64 frame_count; /* Counter for frames acquired by this card */ }; @@ -122,14 +122,14 @@ struct dt3155_fbuffer_s { /* There is one status structure for each card. */ typedef struct dt3155_status_s { int fixed_mode; /* if 1, we are in fixed frame mode */ - u_long reg_addr; /* Register address for a single card */ - u_long mem_addr; /* Buffer start addr for this card */ - u_long mem_size; /* This is the amount of mem available */ - u_int irq; /* this card's irq */ + u64 reg_addr; /* Register address for a single card */ + u64 mem_addr; /* Buffer start addr for this card */ + u64 mem_size; /* This is the amount of mem available */ + u32 irq; /* this card's irq */ struct dt3155_config_s config; /* configuration struct */ struct dt3155_fbuffer_s fbuffer; /* frame buffer state struct */ - u_long state; /* this card's state */ - u_int device_installed; /* Flag if installed. 1=installed */ + u64 state; /* this card's state */ + u32 device_installed; /* Flag if installed. 1=installed */ } dt3155_status_t; /* Reference to global status structure */ @@ -161,9 +161,9 @@ extern struct dt3155_status_s dt3155_status[MAXBOARDS]; /* User code will probably want to declare one of these for each card */ typedef struct dt3155_read_s { - u_long offset; - u_long frame_seq; - u_long state; + u64 offset; + u64 frame_seq; + u64 state; frame_info_t frame_info; } dt3155_read_t; diff --git a/drivers/staging/dt3155/dt3155_drv.c b/drivers/staging/dt3155/dt3155_drv.c index 76f8a78c01e7..930a3e666c0a 100644 --- a/drivers/staging/dt3155/dt3155_drv.c +++ b/drivers/staging/dt3155/dt3155_drv.c @@ -130,14 +130,14 @@ u8 *dt3155_lbase[ MAXBOARDS ] = { NULL /* DT3155 registers */ u8 *dt3155_bbase = NULL; /* kernel logical address of the * * buffer region */ -u_int dt3155_dev_open[ MAXBOARDS ] = {0 +u32 dt3155_dev_open[ MAXBOARDS ] = {0 #if MAXBOARDS == 2 , 0 #endif }; -u_int ndevices = 0; -u_long unique_tag = 0;; +u32 ndevices = 0; +u64 unique_tag = 0;; /* @@ -180,7 +180,7 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) int minor = -1; int index; unsigned long flags; - u_long buffer_addr; + u64 buffer_addr; /* find out who issued the interrupt */ for ( index = 0; index < ndevices; index++ ) { @@ -249,7 +249,7 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) { /* GCS (Aug 2, 2002) -- In field mode, dma the odd field into the lower half of the buffer */ - const u_long stride = dt3155_status[ minor ].config.cols; + const u64 stride = dt3155_status[ minor ].config.cols; buffer_addr = dt3155_fbuffer[ minor ]-> frame_info[ dt3155_fbuffer[ minor ]->active_buf ].addr + (DT3155_MAX_ROWS / 2) * stride; @@ -311,8 +311,8 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) dt3155_fbuffer[ minor ]->stop_acquire = 0; dt3155_fbuffer[ minor ]->even_stopped = 0; - printk(KERN_DEBUG "dt3155: state is now %lx\n", - dt3155_status[minor].state); + printk(KERN_DEBUG "dt3155: state is now %x\n", + (u32)dt3155_status[minor].state); } else { @@ -428,7 +428,7 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) *****************************************************/ static void dt3155_init_isr(int minor) { - const u_long stride = dt3155_status[ minor ].config.cols; + const u64 stride = dt3155_status[ minor ].config.cols; switch (dt3155_status[ minor ].state & DT3155_STATE_MODE) { @@ -522,11 +522,10 @@ static void dt3155_init_isr(int minor) * ioctl() * *****************************************************/ -static int dt3155_ioctl ( - struct inode *inode, - struct file *file, - u_int cmd, - u_long arg) +static int dt3155_ioctl(struct inode *inode, + struct file *file, + unsigned int cmd, + unsigned long arg) { int minor = MINOR(inode->i_rdev); /* What device are we ioctl()'ing? */ @@ -706,8 +705,8 @@ static int dt3155_open( struct inode* inode, struct file* filep) } if (dt3155_status[ minor ].state != DT3155_STATE_IDLE) { - printk ("DT3155: Not in idle state (state = %lx)\n", - dt3155_status[ minor ].state); + printk ("DT3155: Not in idle state (state = %x)\n", + (u32)dt3155_status[ minor ].state); return -EBUSY; } @@ -763,7 +762,7 @@ static ssize_t dt3155_read(struct file *filep, char __user *buf, { /* which device are we reading from? */ int minor = MINOR(filep->f_dentry->d_inode->i_rdev); - u_long offset; + u64 offset; int frame_index; frame_info_t *frame_info_p; @@ -821,11 +820,11 @@ static ssize_t dt3155_read(struct file *filep, char __user *buf, offset = frame_info_p->addr - dt3155_status[minor].mem_addr; put_user(offset, (unsigned int *) buf); - buf += sizeof(u_long); + buf += sizeof(u64); put_user( dt3155_status[minor].fbuffer.frame_count, (unsigned int *) buf); - buf += sizeof(u_long); + buf += sizeof(u64); put_user(dt3155_status[minor].state, (unsigned int *) buf); - buf += sizeof(u_long); + buf += sizeof(u64); if (copy_to_user(buf, frame_info_p, sizeof(frame_info_t))) return -EFAULT; @@ -899,7 +898,7 @@ static int find_PCI (void) /* Now, just go out and make sure that this/these device(s) is/are actually mapped into the kernel address space */ if ((error = pci_read_config_dword( pci_dev, PCI_BASE_ADDRESS_0, - (u_int *) &base))) + (u32 *) &base))) { printk("DT3155: Was not able to find device \n"); goto err; @@ -932,7 +931,7 @@ static int find_PCI (void) dt3155_status[ pci_index-1 ].device_installed = 1; printk("DT3155: Installing device %d w/irq %d and address %p\n", pci_index, - (u_int)dt3155_status[pci_index-1].irq, + (u32)dt3155_status[pci_index-1].irq, dt3155_lbase[pci_index-1]); } @@ -945,7 +944,7 @@ err: return DT_3155_FAILURE; } -u_long allocatorAddr = 0; +u64 allocatorAddr = 0; /***************************************************** * init_module() @@ -1024,10 +1023,10 @@ int init_module(void) dt3155_status[ index ].config.cols, dt3155_status[ index ].config.rows); printk("DT3155: m_addr = 0x%x; m_size = %ld; " - "state = %ld; device_installed = %d\n", - (u_int)dt3155_status[ index ].mem_addr, - dt3155_status[ index ].mem_size, - dt3155_status[ index ].state, + "state = %d; device_installed = %d\n", + (u32)dt3155_status[ index ].mem_addr, + (long int)dt3155_status[ index ].mem_size, + (u32)dt3155_status[ index ].state, dt3155_status[ index ].device_installed); } diff --git a/drivers/staging/dt3155/dt3155_drv.h b/drivers/staging/dt3155/dt3155_drv.h index 1006cf5410da..95e68c3388a4 100644 --- a/drivers/staging/dt3155/dt3155_drv.h +++ b/drivers/staging/dt3155/dt3155_drv.h @@ -38,7 +38,7 @@ extern wait_queue_head_t dt3155_read_wait_queue[MAXBOARDS]; #endif /* number of devices */ -extern u_int ndevices; +extern u32 ndevices; extern int dt3155_errno; diff --git a/drivers/staging/dt3155/dt3155_io.c b/drivers/staging/dt3155/dt3155_io.c index b0f1a78074a1..236d3ea0f9fb 100644 --- a/drivers/staging/dt3155/dt3155_io.c +++ b/drivers/staging/dt3155/dt3155_io.c @@ -55,12 +55,12 @@ MA 02111-1307 USA /****** local copies of board's 32 bit registers ******/ -u_long even_dma_start_r; /* bit 0 should always be 0 */ -u_long odd_dma_start_r; /* .. */ -u_long even_dma_stride_r; /* bits 0&1 should always be 0 */ -u_long odd_dma_stride_r; /* .. */ -u_long even_pixel_fmt_r; -u_long odd_pixel_fmt_r; +u64 even_dma_start_r; /* bit 0 should always be 0 */ +u64 odd_dma_start_r; /* .. */ +u64 even_dma_stride_r; /* bits 0&1 should always be 0 */ +u64 odd_dma_stride_r; /* .. */ +u64 even_pixel_fmt_r; +u64 odd_pixel_fmt_r; FIFO_TRIGGER_R fifo_trigger_r; XFER_MODE_R xfer_mode_r; @@ -68,8 +68,8 @@ CSR1_R csr1_r; RETRY_WAIT_CNT_R retry_wait_cnt_r; INT_CSR_R int_csr_r; -u_long even_fld_mask_r; -u_long odd_fld_mask_r; +u64 even_fld_mask_r; +u64 odd_fld_mask_r; MASK_LENGTH_R mask_length_r; FIFO_FLAG_CNT_R fifo_flag_cnt_r; diff --git a/drivers/staging/dt3155/dt3155_io.h b/drivers/staging/dt3155/dt3155_io.h index dd25a79bdee9..a135aada5902 100644 --- a/drivers/staging/dt3155/dt3155_io.h +++ b/drivers/staging/dt3155/dt3155_io.h @@ -36,8 +36,8 @@ MA 02111-1307 USA /* macros to access registers */ -#define WriteMReg(Address, Data) (*((u_long *)(Address)) = Data) -#define ReadMReg(Address, Data) (Data = *((u_long *)(Address))) +#define WriteMReg(Address, Data) (*((u64 *)(Address)) = Data) +#define ReadMReg(Address, Data) (Data = *((u64 *)(Address))) /***************** 32 bit register globals **************/ @@ -71,114 +71,114 @@ MA 02111-1307 USA /******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/ typedef union fifo_trigger_tag { - u_long reg; + u64 reg; struct { - u_long PACKED:6; - u_long :9; - u_long PLANER:7; - u_long :9; + u64 PACKED:6; + u64 :9; + u64 PLANER:7; + u64 :9; } fld; } FIFO_TRIGGER_R; typedef union xfer_mode_tag { - u_long reg; + u64 reg; struct { - u_long :2; - u_long FIELD_TOGGLE:1; - u_long :5; - u_long :2; - u_long :22; + u64 :2; + u64 FIELD_TOGGLE:1; + u64 :5; + u64 :2; + u64 :22; } fld; } XFER_MODE_R; typedef union csr1_tag { - u_long reg; + u64 reg; struct { - u_long CAP_CONT_EVE:1; - u_long CAP_CONT_ODD:1; - u_long CAP_SNGL_EVE:1; - u_long CAP_SNGL_ODD:1; - u_long FLD_DN_EVE :1; - u_long FLD_DN_ODD :1; - u_long SRST :1; - u_long FIFO_EN :1; - u_long FLD_CRPT_EVE:1; - u_long FLD_CRPT_ODD:1; - u_long ADDR_ERR_EVE:1; - u_long ADDR_ERR_ODD:1; - u_long CRPT_DIS :1; - u_long RANGE_EN :1; - u_long :16; + u64 CAP_CONT_EVE:1; + u64 CAP_CONT_ODD:1; + u64 CAP_SNGL_EVE:1; + u64 CAP_SNGL_ODD:1; + u64 FLD_DN_EVE :1; + u64 FLD_DN_ODD :1; + u64 SRST :1; + u64 FIFO_EN :1; + u64 FLD_CRPT_EVE:1; + u64 FLD_CRPT_ODD:1; + u64 ADDR_ERR_EVE:1; + u64 ADDR_ERR_ODD:1; + u64 CRPT_DIS :1; + u64 RANGE_EN :1; + u64 :16; } fld; } CSR1_R; typedef union retry_wait_cnt_tag { - u_long reg; + u64 reg; struct { - u_long RTRY_WAIT_CNT:8; - u_long :24; + u64 RTRY_WAIT_CNT:8; + u64 :24; } fld; } RETRY_WAIT_CNT_R; typedef union int_csr_tag { - u_long reg; + u64 reg; struct { - u_long FLD_END_EVE :1; - u_long FLD_END_ODD :1; - u_long FLD_START :1; - u_long :5; - u_long FLD_END_EVE_EN:1; - u_long FLD_END_ODD_EN:1; - u_long FLD_START_EN :1; - u_long :21; + u64 FLD_END_EVE :1; + u64 FLD_END_ODD :1; + u64 FLD_START :1; + u64 :5; + u64 FLD_END_EVE_EN:1; + u64 FLD_END_ODD_EN:1; + u64 FLD_START_EN :1; + u64 :21; } fld; } INT_CSR_R; typedef union mask_length_tag { - u_long reg; + u64 reg; struct { - u_long MASK_LEN_EVE:5; - u_long :11; - u_long MASK_LEN_ODD:5; - u_long :11; + u64 MASK_LEN_EVE:5; + u64 :11; + u64 MASK_LEN_ODD:5; + u64 :11; } fld; } MASK_LENGTH_R; typedef union fifo_flag_cnt_tag { - u_long reg; + u64 reg; struct { - u_long AF_COUNT:7; - u_long :9; - u_long AE_COUNT:7; - u_long :9; + u64 AF_COUNT:7; + u64 :9; + u64 AE_COUNT:7; + u64 :9; } fld; } FIFO_FLAG_CNT_R; typedef union iic_clk_dur { - u_long reg; + u64 reg; struct { - u_long PHASE_1:8; - u_long PHASE_2:8; - u_long PHASE_3:8; - u_long PHASE_4:8; + u64 PHASE_1:8; + u64 PHASE_2:8; + u64 PHASE_3:8; + u64 PHASE_4:8; } fld; } IIC_CLK_DUR_R; typedef union iic_csr1_tag { - u_long reg; + u64 reg; struct { - u_long AUTO_EN :1; - u_long BYPASS :1; - u_long SDA_OUT :1; - u_long SCL_OUT :1; - u_long :4; - u_long AUTO_ABORT :1; - u_long DIRECT_ABORT:1; - u_long SDA_IN :1; - u_long SCL_IN :1; - u_long :4; - u_long AUTO_ADDR :8; - u_long RD_DATA :8; + u64 AUTO_EN :1; + u64 BYPASS :1; + u64 SDA_OUT :1; + u64 SCL_OUT :1; + u64 :4; + u64 AUTO_ABORT :1; + u64 DIRECT_ABORT:1; + u64 SDA_IN :1; + u64 SCL_IN :1; + u64 :4; + u64 AUTO_ADDR :8; + u64 RD_DATA :8; } fld; } IIC_CSR1_R; @@ -186,14 +186,14 @@ typedef union iic_csr1_tag { * iic_csr2_tag */ typedef union iic_csr2_tag { - u_long reg; + u64 reg; struct { - u_long DIR_WR_DATA :8; - u_long DIR_SUB_ADDR:8; - u_long DIR_RD :1; - u_long DIR_ADDR :7; - u_long NEW_CYCLE :1; - u_long :7; + u64 DIR_WR_DATA :8; + u64 DIR_SUB_ADDR:8; + u64 DIR_RD :1; + u64 DIR_ADDR :7; + u64 NEW_CYCLE :1; + u64 :7; } fld; } IIC_CSR2_R; @@ -203,10 +203,10 @@ typedef union iic_csr2_tag { * dma_upper_lmt_tag */ typedef union dma_upper_lmt_tag { - u_long reg; + u64 reg; struct { - u_long DMA_UPPER_LMT_VAL:24; - u_long :8; + u64 DMA_UPPER_LMT_VAL:24; + u64 :8; } fld; } DMA_UPPER_LMT_R; @@ -214,12 +214,12 @@ typedef union dma_upper_lmt_tag { /* * Global declarations of local copies of boards' 32 bit registers */ -extern u_long even_dma_start_r; /* bit 0 should always be 0 */ -extern u_long odd_dma_start_r; /* .. */ -extern u_long even_dma_stride_r; /* bits 0&1 should always be 0 */ -extern u_long odd_dma_stride_r; /* .. */ -extern u_long even_pixel_fmt_r; -extern u_long odd_pixel_fmt_r; +extern u64 even_dma_start_r; /* bit 0 should always be 0 */ +extern u64 odd_dma_start_r; /* .. */ +extern u64 even_dma_stride_r; /* bits 0&1 should always be 0 */ +extern u64 odd_dma_stride_r; /* .. */ +extern u64 even_pixel_fmt_r; +extern u64 odd_pixel_fmt_r; extern FIFO_TRIGGER_R fifo_trigger_r; extern XFER_MODE_R xfer_mode_r; @@ -227,8 +227,8 @@ extern CSR1_R csr1_r; extern RETRY_WAIT_CNT_R retry_wait_cnt_r; extern INT_CSR_R int_csr_r; -extern u_long even_fld_mask_r; -extern u_long odd_fld_mask_r; +extern u64 even_fld_mask_r; +extern u64 odd_fld_mask_r; extern MASK_LENGTH_R mask_length_r; extern FIFO_FLAG_CNT_R fifo_flag_cnt_r; diff --git a/drivers/staging/dt3155/dt3155_isr.c b/drivers/staging/dt3155/dt3155_isr.c index faed085d4fc7..5b790867c292 100644 --- a/drivers/staging/dt3155/dt3155_isr.c +++ b/drivers/staging/dt3155/dt3155_isr.c @@ -220,7 +220,7 @@ inline void printques( int m ) * the start address up to the beginning of the * next 4MB chunk (assuming bufsize < 4MB). *****************************************************/ -u_long adjust_4MB (u_long buf_addr, u_long bufsize) { +u64 adjust_4MB (u64 buf_addr, u64 bufsize) { if (((buf_addr+bufsize) & UPPER_10_BITS) != (buf_addr & UPPER_10_BITS)) return (buf_addr+bufsize) & UPPER_10_BITS; else @@ -235,26 +235,26 @@ u_long adjust_4MB (u_long buf_addr, u_long bufsize) { * buffers. If there is not enough free space * try for less memory. *****************************************************/ -void allocate_buffers (u_long *buf_addr, u_long* total_size_kbs, - u_long bufsize) +void allocate_buffers (u64 *buf_addr, u64* total_size_kbs, + u64 bufsize) { /* Compute the minimum amount of memory guaranteed to hold all MAXBUFFERS such that no buffer crosses the 4MB boundary. Store this value in the variable "full_size" */ - u_long allocator_max; - u_long bufs_per_chunk = (FOUR_MB / bufsize); - u_long filled_chunks = (MAXBUFFERS-1) / bufs_per_chunk; - u_long leftover_bufs = MAXBUFFERS - filled_chunks * bufs_per_chunk; + u64 allocator_max; + u64 bufs_per_chunk = (FOUR_MB / bufsize); + u64 filled_chunks = (MAXBUFFERS-1) / bufs_per_chunk; + u64 leftover_bufs = MAXBUFFERS - filled_chunks * bufs_per_chunk; - u_long full_size = bufsize /* possibly unusable part of 1st chunk */ + u64 full_size = bufsize /* possibly unusable part of 1st chunk */ + filled_chunks * FOUR_MB /* max # of completely filled 4mb chunks */ + leftover_bufs * bufsize; /* these buffs will be in a partly filled chunk at beginning or end */ - u_long full_size_kbs = 1 + (full_size-1) / 1024; - u_long min_size_kbs = 2*ndevices*bufsize / 1024; - u_long size_kbs; + u64 full_size_kbs = 1 + (full_size-1) / 1024; + u64 min_size_kbs = 2*ndevices*bufsize / 1024; + u64 size_kbs; /* Now, try to allocate full_size. If this fails, keep trying for less & less memory until it succeeds. */ @@ -264,13 +264,13 @@ void allocate_buffers (u_long *buf_addr, u_long* total_size_kbs, #endif size_kbs = full_size_kbs; *buf_addr = 0; - printk ("DT3155: We would like to get: %d KB\n", (u_int)(full_size_kbs)); - printk ("DT3155: ...but need at least: %d KB\n", (u_int)(min_size_kbs)); - printk ("DT3155: ...the allocator has: %d KB\n", (u_int)(allocator_max)); + printk ("DT3155: We would like to get: %d KB\n", (u32)(full_size_kbs)); + printk ("DT3155: ...but need at least: %d KB\n", (u32)(min_size_kbs)); + printk ("DT3155: ...the allocator has: %d KB\n", (u32)(allocator_max)); size_kbs = (full_size_kbs <= allocator_max ? full_size_kbs : allocator_max); if (size_kbs > min_size_kbs) { if ((*buf_addr = allocator_allocate_dma (size_kbs, GFP_KERNEL)) != 0) { - printk ("DT3155: Managed to allocate: %d KB\n", (u_int)size_kbs); + printk ("DT3155: Managed to allocate: %d KB\n", (u32)size_kbs); *total_size_kbs = size_kbs; return; } @@ -298,17 +298,17 @@ void allocate_buffers (u_long *buf_addr, u_long* total_size_kbs, * 4MB boundary. Also, add error checking. This * function will return -ENOMEM when not enough memory. *****************************************************/ -u_long dt3155_setup_buffers(u_long *allocatorAddr) +u64 dt3155_setup_buffers(u64 *allocatorAddr) { - u_long index; - u_long rambuff_addr; /* start of allocation */ - u_long rambuff_size; /* total size allocated to driver */ - u_long rambuff_acm; /* accumlator, keep track of how much + u64 index; + u64 rambuff_addr; /* start of allocation */ + u64 rambuff_size; /* total size allocated to driver */ + u64 rambuff_acm; /* accumlator, keep track of how much is left after being split up*/ - u_long rambuff_end; /* end of rambuff */ - u_long numbufs; /* number of useful buffers allocated (per device) */ - u_long bufsize = DT3155_MAX_ROWS * DT3155_MAX_COLS; + u64 rambuff_end; /* end of rambuff */ + u64 numbufs; /* number of useful buffers allocated (per device) */ + u64 bufsize = DT3155_MAX_ROWS * DT3155_MAX_COLS; int m; /* minor # of device, looped for all devs */ /* zero the fbuffer status and address structure */ @@ -327,8 +327,8 @@ u_long dt3155_setup_buffers(u_long *allocatorAddr) /* allocate a large contiguous chunk of RAM */ allocate_buffers (&rambuff_addr, &rambuff_size, bufsize); printk( "DT3155: mem info\n" ); - printk( " - rambuf_addr = 0x%x \n", (u_int)rambuff_addr ); - printk( " - length (kb) = %u \n", (u_int)rambuff_size ); + printk( " - rambuf_addr = 0x%x \n", (u32)rambuff_addr ); + printk( " - length (kb) = %u \n", (u32)rambuff_size ); if( rambuff_addr == 0 ) { printk( KERN_INFO @@ -350,7 +350,7 @@ u_long dt3155_setup_buffers(u_long *allocatorAddr) /* Following line is OK, will waste buffers if index * not evenly divisible by ndevices -NJC*/ numbufs = index / ndevices; - printk (" - numbufs = %u\n", (u_int) numbufs); + printk (" - numbufs = %u\n", (u32) numbufs); if (numbufs < 2) { printk( KERN_INFO "DT3155: Error setup_buffers() couldn't allocate 2 bufs/board\n" ); diff --git a/drivers/staging/dt3155/dt3155_isr.h b/drivers/staging/dt3155/dt3155_isr.h index c77a1008c09c..7f27910eb941 100644 --- a/drivers/staging/dt3155/dt3155_isr.h +++ b/drivers/staging/dt3155/dt3155_isr.h @@ -42,7 +42,7 @@ extern struct dt3155_fbuffer_s *dt3155_fbuffer[MAXBOARDS]; /* Initialize the buffering system. This should */ /* be called prior to enabling interrupts */ -u_long dt3155_setup_buffers(u_long *allocatorAddr); +u64 dt3155_setup_buffers(u64 *allocatorAddr); /* Get the next frame of data if it is ready. Returns */ /* zero if no data is ready. If there is data but */ -- cgit v1.2.3 From ef97e4ef156500eb1c26de57354ad685f0b6127b Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 9 Feb 2010 12:41:38 -0800 Subject: Staging: dt3155: fix coding style issues in dt3155_io.c This fixes up the sparse and coding style issues found in the dt3155_io.c file. No code is changed, only formatting and removing unused code. Cc: Scott Smedley Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dt3155/dt3155_io.c | 333 +++++++++++++++---------------------- 1 file changed, 136 insertions(+), 197 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dt3155/dt3155_io.c b/drivers/staging/dt3155/dt3155_io.c index 236d3ea0f9fb..1c15604f4313 100644 --- a/drivers/staging/dt3155/dt3155_io.c +++ b/drivers/staging/dt3155/dt3155_io.c @@ -1,236 +1,175 @@ /* + * Copyright 1996,2002,2005 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, + * Jason Lapenta, Scott Smedley + * + * This file is part of the DT3155 Device Driver. + * + * The DT3155 Device Driver is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * The DT3155 Device Driver is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + */ -Copyright 1996,2002,2005 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan, - Jason Lapenta, Scott Smedley - -This file is part of the DT3155 Device Driver. - -The DT3155 Device Driver is free software; you can redistribute it -and/or modify it under the terms of the GNU General Public License as -published by the Free Software Foundation; either version 2 of the -License, or (at your option) any later version. - -The DT3155 Device Driver is distributed in the hope that it will be -useful, but WITHOUT ANY WARRANTY; without even the implied warranty -of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with the DT3155 Device Driver; if not, write to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, -MA 02111-1307 USA - - --- Changes -- - - Date Programmer Description of changes made - ------------------------------------------------------------------- - 10-Oct-2001 SS port to 2.4 kernel. - 24-Jul-2002 SS GPL licence. - 26-Jul-2002 SS Bug fix: timing logic was wrong. - 08-Aug-2005 SS port to 2.6 kernel. - -*/ - -/* This file provides some basic register io routines. It is modified - from demo code provided by Data Translations. */ - -#ifdef __KERNEL__ -#include -#endif - -#if 0 -#include -#include -#include -#endif +/* + * This file provides some basic register io routines. It is modified from + * demo code provided by Data Translations. + */ +#include #include "dt3155.h" #include "dt3155_io.h" #include "dt3155_drv.h" -#ifndef __KERNEL__ -#include -#endif - /****** local copies of board's 32 bit registers ******/ -u64 even_dma_start_r; /* bit 0 should always be 0 */ -u64 odd_dma_start_r; /* .. */ -u64 even_dma_stride_r; /* bits 0&1 should always be 0 */ -u64 odd_dma_stride_r; /* .. */ -u64 even_pixel_fmt_r; -u64 odd_pixel_fmt_r; +u64 even_dma_start_r; /* bit 0 should always be 0 */ +u64 odd_dma_start_r; /* .. */ +u64 even_dma_stride_r; /* bits 0&1 should always be 0 */ +u64 odd_dma_stride_r; /* .. */ +u64 even_pixel_fmt_r; +u64 odd_pixel_fmt_r; -FIFO_TRIGGER_R fifo_trigger_r; -XFER_MODE_R xfer_mode_r; -CSR1_R csr1_r; -RETRY_WAIT_CNT_R retry_wait_cnt_r; -INT_CSR_R int_csr_r; +FIFO_TRIGGER_R fifo_trigger_r; +XFER_MODE_R xfer_mode_r; +CSR1_R csr1_r; +RETRY_WAIT_CNT_R retry_wait_cnt_r; +INT_CSR_R int_csr_r; -u64 even_fld_mask_r; -u64 odd_fld_mask_r; +u64 even_fld_mask_r; +u64 odd_fld_mask_r; -MASK_LENGTH_R mask_length_r; -FIFO_FLAG_CNT_R fifo_flag_cnt_r; -IIC_CLK_DUR_R iic_clk_dur_r; -IIC_CSR1_R iic_csr1_r; -IIC_CSR2_R iic_csr2_r; -DMA_UPPER_LMT_R even_dma_upper_lmt_r; -DMA_UPPER_LMT_R odd_dma_upper_lmt_r; +MASK_LENGTH_R mask_length_r; +FIFO_FLAG_CNT_R fifo_flag_cnt_r; +IIC_CLK_DUR_R iic_clk_dur_r; +IIC_CSR1_R iic_csr1_r; +IIC_CSR2_R iic_csr2_r; +DMA_UPPER_LMT_R even_dma_upper_lmt_r; +DMA_UPPER_LMT_R odd_dma_upper_lmt_r; /******** local copies of board's 8 bit I2C registers ******/ -I2C_CSR2 i2c_csr2; -I2C_EVEN_CSR i2c_even_csr; -I2C_ODD_CSR i2c_odd_csr; -I2C_CONFIG i2c_config; -u8 i2c_dt_id; -u8 i2c_x_clip_start; -u8 i2c_y_clip_start; -u8 i2c_x_clip_end; -u8 i2c_y_clip_end; -u8 i2c_ad_addr; -u8 i2c_ad_lut; -I2C_AD_CMD i2c_ad_cmd; -u8 i2c_dig_out; -u8 i2c_pm_lut_addr; -u8 i2c_pm_lut_data; - - -// return the time difference (in microseconds) b/w & . -long elapsed2 (const struct timeval *pStart, const struct timeval *pEnd) -{ - long i = (pEnd->tv_sec - pStart->tv_sec) * 1000000; - i += pEnd->tv_usec - pStart->tv_usec; - return i; -} +I2C_CSR2 i2c_csr2; +I2C_EVEN_CSR i2c_even_csr; +I2C_ODD_CSR i2c_odd_csr; +I2C_CONFIG i2c_config; +u8 i2c_dt_id; +u8 i2c_x_clip_start; +u8 i2c_y_clip_start; +u8 i2c_x_clip_end; +u8 i2c_y_clip_end; +u8 i2c_ad_addr; +u8 i2c_ad_lut; +I2C_AD_CMD i2c_ad_cmd; +u8 i2c_dig_out; +u8 i2c_pm_lut_addr; +u8 i2c_pm_lut_data; -/*********************************************************************** - wait_ibsyclr() - - This function handles read/write timing and r/w timeout error - - Returns TRUE if NEW_CYCLE clears - Returns FALSE if NEW_CYCLE doesn't clear in roughly 3 msecs, - otherwise returns 0 - -***********************************************************************/ -int wait_ibsyclr(u8 * lpReg) +/* + * wait_ibsyclr() + * + * This function handles read/write timing and r/w timeout error + * + * Returns TRUE if NEW_CYCLE clears + * Returns FALSE if NEW_CYCLE doesn't clear in roughly 3 msecs, otherwise + * returns 0 + */ +static int wait_ibsyclr(u8 *lpReg) { - /* wait 100 microseconds */ - -#ifdef __KERNEL__ - udelay(100L); - /* __delay(loops_per_sec/10000); */ - if (iic_csr2_r.fld.NEW_CYCLE ) - { /* if NEW_CYCLE didn't clear */ - /* TIMEOUT ERROR */ - dt3155_errno = DT_ERR_I2C_TIMEOUT; - return FALSE; - } - else - return TRUE; /* no error */ -#else - struct timeval StartTime; - struct timeval EndTime; - - const int to_3ms = 3000; /* time out of 3ms = 3000us */ - - gettimeofday( &StartTime, NULL ); - do { - /* get new iic_csr2 value: */ - ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); - gettimeofday( &EndTime, NULL ); - } - while ((elapsed2(&StartTime, &EndTime) < to_3ms) && iic_csr2_r.fld.NEW_CYCLE); - - if (iic_csr2_r.fld.NEW_CYCLE ) - { /* if NEW_CYCLE didn't clear */ - printf("Timed out waiting for NEW_CYCLE to clear!"); - return FALSE; - } - else - return TRUE; /* no error */ -#endif + /* wait 100 microseconds */ + udelay(100L); + /* __delay(loops_per_sec/10000); */ + if (iic_csr2_r.fld.NEW_CYCLE) { + /* if NEW_CYCLE didn't clear */ + /* TIMEOUT ERROR */ + dt3155_errno = DT_ERR_I2C_TIMEOUT; + return FALSE; + } else + return TRUE; /* no error */ } -/*********************************************************************** - WriteI2C() - - This function handles writing to 8-bit DT3155 registers - - 1st parameter is pointer to 32-bit register base address - 2nd parameter is reg. index; - 3rd is value to be written - - Returns TRUE - Successful completion - FALSE - Timeout error - cycle did not complete! -***********************************************************************/ -int WriteI2C (u8 * lpReg, u_short wIregIndex, u8 byVal) +/* + * WriteI2C() + * + * This function handles writing to 8-bit DT3155 registers + * + * 1st parameter is pointer to 32-bit register base address + * 2nd parameter is reg. index; + * 3rd is value to be written + * + * Returns TRUE - Successful completion + * FALSE - Timeout error - cycle did not complete! + */ +int WriteI2C(u8 *lpReg, u_short wIregIndex, u8 byVal) { - int writestat; /* status for return */ - - /* read 32 bit IIC_CSR2 register data into union */ + int writestat; /* status for return */ - ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); + /* read 32 bit IIC_CSR2 register data into union */ - iic_csr2_r.fld.DIR_RD = 0; /* for write operation */ - iic_csr2_r.fld.DIR_ADDR = wIregIndex; /* I2C address of I2C register: */ - iic_csr2_r.fld.DIR_WR_DATA = byVal; /* 8 bit data to be written to I2C reg */ - iic_csr2_r.fld.NEW_CYCLE = 1; /* will start a direct I2C cycle: */ + ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); - /* xfer union data into 32 bit IIC_CSR2 register */ + /* for write operation */ + iic_csr2_r.fld.DIR_RD = 0; + /* I2C address of I2C register: */ + iic_csr2_r.fld.DIR_ADDR = wIregIndex; + /* 8 bit data to be written to I2C reg */ + iic_csr2_r.fld.DIR_WR_DATA = byVal; + /* will start a direct I2C cycle: */ + iic_csr2_r.fld.NEW_CYCLE = 1; - WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); + /* xfer union data into 32 bit IIC_CSR2 register */ + WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); - /* wait for IIC cycle to finish */ - - writestat = wait_ibsyclr( lpReg ); - return writestat; /* return with status */ + /* wait for IIC cycle to finish */ + writestat = wait_ibsyclr(lpReg); + return writestat; } -/*********************************************************************** - ReadI2C() - - This function handles reading from 8-bit DT3155 registers - - 1st parameter is pointer to 32-bit register base address - 2nd parameter is reg. index; - 3rd is adrs of value to be read - - Returns TRUE - Successful completion - FALSE - Timeout error - cycle did not complete! -***********************************************************************/ -int ReadI2C (u8 * lpReg, u_short wIregIndex, u8 * byVal) +/* + * ReadI2C() + * + * This function handles reading from 8-bit DT3155 registers + * + * 1st parameter is pointer to 32-bit register base address + * 2nd parameter is reg. index; + * 3rd is adrs of value to be read + * + * Returns TRUE - Successful completion + * FALSE - Timeout error - cycle did not complete! + */ +int ReadI2C(u8 *lpReg, u_short wIregIndex, u8 *byVal) { - int writestat; /* status for return */ + int writestat; /* status for return */ - /* read 32 bit IIC_CSR2 register data into union */ - ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); + /* read 32 bit IIC_CSR2 register data into union */ + ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); - /* for read operation */ - iic_csr2_r.fld.DIR_RD = 1; + /* for read operation */ + iic_csr2_r.fld.DIR_RD = 1; - /* I2C address of I2C register: */ - iic_csr2_r.fld.DIR_ADDR = wIregIndex; + /* I2C address of I2C register: */ + iic_csr2_r.fld.DIR_ADDR = wIregIndex; - /* will start a direct I2C cycle: */ - iic_csr2_r.fld.NEW_CYCLE = 1; + /* will start a direct I2C cycle: */ + iic_csr2_r.fld.NEW_CYCLE = 1; - /* xfer union's data into 32 bit IIC_CSR2 register */ - WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); + /* xfer union's data into 32 bit IIC_CSR2 register */ + WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg); - /* wait for IIC cycle to finish */ - writestat = wait_ibsyclr(lpReg); + /* wait for IIC cycle to finish */ + writestat = wait_ibsyclr(lpReg); - /* Next 2 commands read 32 bit IIC_CSR1 register's data into union */ - /* first read data is in IIC_CSR1 */ - ReadMReg((lpReg + IIC_CSR1), iic_csr1_r.reg); + /* Next 2 commands read 32 bit IIC_CSR1 register's data into union */ + /* first read data is in IIC_CSR1 */ + ReadMReg((lpReg + IIC_CSR1), iic_csr1_r.reg); - /* now get data u8 out of register */ - *byVal = (u8) iic_csr1_r.fld.RD_DATA; + /* now get data u8 out of register */ + *byVal = (u8) iic_csr1_r.fld.RD_DATA; - return writestat; /* return with status */ + return writestat; } -- cgit v1.2.3 From e37bcc0de040127281de13a84a608570355c20eb Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 11 Feb 2010 17:15:14 -0800 Subject: Staging: mimio: remove the mimio driver It turns out that Mimio has a userspace solution for this product using libusb, and the in-kernel driver is just getting in the way now and causing problems. So they have asked that the in-kernel driver be removed. As the staging driver wasn't quite working anyway, and Mimio supports their libusb solution for all distros, I am removing the in-kernel driver. The libusb solution can be downloaded from: http://www.mimio.com/downloads/mimio_studio_software/linux.asp Cc: Cc: Phil Hannent Cc: Marc Rousseau Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/staging/Kconfig | 2 - drivers/staging/Makefile | 1 - drivers/staging/mimio/Kconfig | 10 - drivers/staging/mimio/Makefile | 1 - drivers/staging/mimio/mimio.c | 896 ----------------------------------------- 5 files changed, 910 deletions(-) delete mode 100644 drivers/staging/mimio/Kconfig delete mode 100644 drivers/staging/mimio/Makefile delete mode 100644 drivers/staging/mimio/mimio.c (limited to 'drivers') diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 4a2afe7d0078..9b396bdbeeb5 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -79,8 +79,6 @@ source "drivers/staging/rtl8192u/Kconfig" source "drivers/staging/rtl8192e/Kconfig" -source "drivers/staging/mimio/Kconfig" - source "drivers/staging/frontier/Kconfig" source "drivers/staging/dream/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index dc404936a862..95ef22081a4c 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -22,7 +22,6 @@ obj-$(CONFIG_R8187SE) += rtl8187se/ obj-$(CONFIG_RTL8192SU) += rtl8192su/ obj-$(CONFIG_RTL8192U) += rtl8192u/ obj-$(CONFIG_RTL8192E) += rtl8192e/ -obj-$(CONFIG_INPUT_MIMIO) += mimio/ obj-$(CONFIG_TRANZPORT) += frontier/ obj-$(CONFIG_DREAM) += dream/ obj-$(CONFIG_POHMELFS) += pohmelfs/ diff --git a/drivers/staging/mimio/Kconfig b/drivers/staging/mimio/Kconfig deleted file mode 100644 index 505dcb275796..000000000000 --- a/drivers/staging/mimio/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -config INPUT_MIMIO - tristate "Mimio Xi interactive whiteboard support" - depends on USB && INPUT - default N - help - Say Y here if you want to use a Mimio Xi interactive - whiteboard device. - - To compile this driver as a module, choose M here: the - module will be called mimio. diff --git a/drivers/staging/mimio/Makefile b/drivers/staging/mimio/Makefile deleted file mode 100644 index 77807ee0450e..000000000000 --- a/drivers/staging/mimio/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-$(CONFIG_INPUT_MIMIO) += mimio.o diff --git a/drivers/staging/mimio/mimio.c b/drivers/staging/mimio/mimio.c deleted file mode 100644 index 2cfef4a0851f..000000000000 --- a/drivers/staging/mimio/mimio.c +++ /dev/null @@ -1,896 +0,0 @@ -/* - * Hardware event => input event mapping: - * - * BTN_TOOL_PEN 0x140 black - * BTN_TOOL_RUBBER 0x141 blue - * BTN_TOOL_BRUSH 0x142 green - * BTN_TOOL_PENCIL 0x143 red - * BTN_TOOL_AIRBRUSH 0x144 eraser - * BTN_TOOL_FINGER 0x145 small eraser - * BTN_TOOL_MOUSE 0x146 mimio interactive - * BTN_TOOL_LENS 0x147 mimio interactive but1 - * LOCALBTN_TOOL_EXTRA1 0x14a mimio interactive but2 == BTN_TOUCH - * LOCALBTN_TOOL_EXTRA2 0x14b mimio extra pens (orange, brown, yellow, - * purple) == BTN_STYLUS - * LOCALBTN_TOOL_EXTRA3 0x14c unused == BTN_STYLUS2 - * BTN_TOOL_DOUBLETAP 0x14d unused - * BTN_TOOL_TRIPLETAP 0x14e unused - * - * MIMIO_EV_PENDOWN(MIMIO_PEN_K) => EV_KEY BIT(BTN_TOOL_PEN) - * MIMIO_EV_PENDOWN(MIMIO_PEN_B) => EV_KEY BIT(BTN_TOOL_RUBBER) - * MIMIO_EV_PENDOWN(MIMIO_PEN_G) => EV_KEY BIT(BTN_TOOL_BRUSH) - * MIMIO_EV_PENDOWN(MIMIO_PEN_R) => EV_KEY BIT(BTN_TOOL_PENCIL) - * MIMIO_EV_PENDOWN(MIMIO_PEN_E) => EV_KEY BIT(BTN_TOOL_AIRBRUSH) - * MIMIO_EV_PENDOWN(MIMIO_PEN_ES) => EV_KEY BIT(BTN_TOOL_FINGER) - * MIMIO_EV_PENDOWN(MIMIO_PEN_I) => EV_KEY BIT(BTN_TOOL_MOUSE) - * MIMIO_EV_PENDOWN(MIMIO_PEN_IL) => EV_KEY BIT(BTN_TOOL_LENS) - * MIMIO_EV_PENDOWN(MIMIO_PEN_IR) => EV_KEY BIT(BTN_TOOL_DOUBLETAP) - * MIMIO_EV_PENDOWN(MIMIO_PEN_EX) => EV_KEY BIT(BTN_TOOL_TRIPLETAP) - * MIMIO_EV_PENDATA => EV_ABS BIT(ABS_X), BIT(ABS_Y) - * MIMIO_EV_MEMRESET => EV_KEY BIT(BTN_0) - * MIMIO_EV_ACC(ACC_NEWPAGE) => EV_KEY BIT(BTN_1) - * MIMIO_EV_ACC(ACC_TAGPAGE) => EV_KEY BIT(BTN_2) - * MIMIO_EV_ACC(ACC_PRINTPAGE) => EV_KEY BIT(BTN_3) - * MIMIO_EV_ACC(ACC_MAXIMIZE) => EV_KEY BIT(BTN_4) - * MIMIO_EV_ACC(ACC_FINDCTLPNL) => EV_KEY BIT(BTN_5) - * - * open issues: - * - cold-load of data captured when mimio in standalone mode not yet - * supported; need to snoop Win32 box to see datastream for this. - * - mimio mouse not yet supported; need to snoop Win32 box to see the - * datastream for this. - */ - -#include -#include -#include -#include -#include -#include - -#define DRIVER_VERSION "v0.031" -#define DRIVER_AUTHOR "mwilder@cs.nmsu.edu" -#define DRIVER_DESC "USB mimio-xi driver" - -enum {UPVALUE, DOWNVALUE, MOVEVALUE}; - -#define MIMIO_XRANGE_MAX 9600 -#define MIMIO_YRANGE_MAX 4800 - -#define LOCALBTN_TOOL_EXTRA1 BTN_TOUCH -#define LOCALBTN_TOOL_EXTRA2 BTN_STYLUS -#define LOCALBTN_TOOL_EXTRA3 BTN_STYLUS2 - -#define MIMIO_VENDOR_ID 0x08d3 -#define MIMIO_PRODUCT_ID 0x0001 -#define MIMIO_MAXPAYLOAD (8) -#define MIMIO_MAXNAMELEN (64) -#define MIMIO_TXWAIT (1) -#define MIMIO_TXDONE (2) - -#define MIMIO_EV_PENDOWN (0x22) -#define MIMIO_EV_PENDATA (0x24) -#define MIMIO_EV_PENUP (0x51) -#define MIMIO_EV_MEMRESET (0x45) -#define MIMIO_EV_ACC (0xb2) - -#define MIMIO_PEN_K (1) /* black pen */ -#define MIMIO_PEN_B (2) /* blue pen */ -#define MIMIO_PEN_G (3) /* green pen */ -#define MIMIO_PEN_R (4) /* red pen */ -/* 5, 6, 7, 8 are extra pens */ -#define MIMIO_PEN_E (9) /* big eraser */ -#define MIMIO_PEN_ES (10) /* lil eraser */ -#define MIMIO_PENJUMP_START (10) -#define MIMIO_PENJUMP (6) -#define MIMIO_PEN_I (17) /* mimio interactive */ -#define MIMIO_PEN_IL (18) /* mimio interactive button 1 */ -#define MIMIO_PEN_IR (19) /* mimio interactive button 2 */ - -#define MIMIO_PEN_MAX (MIMIO_PEN_IR) - -#define ACC_DONE (0) -#define ACC_NEWPAGE (1) -#define ACC_TAGPAGE (2) -#define ACC_PRINTPAGE (4) -#define ACC_MAXIMIZE (8) -#define ACC_FINDCTLPNL (16) - -#define isvalidtxsize(n) ((n) > 0 && (n) <= MIMIO_MAXPAYLOAD) - - -struct pktbuf { - unsigned char instr; - unsigned char buf[16]; - unsigned char *p; - unsigned char *q; -}; - -struct usbintendpt { - dma_addr_t dma; - struct urb *urb; - unsigned char *buf; - struct usb_endpoint_descriptor *desc; -}; - -struct mimio { - struct input_dev *idev; - struct usb_device *udev; - struct usb_interface *uifc; - int open; - int present; - int greeted; - int txflags; - char phys[MIMIO_MAXNAMELEN]; - struct usbintendpt in; - struct usbintendpt out; - struct pktbuf pktbuf; - unsigned char minor; - wait_queue_head_t waitq; - spinlock_t txlock; - void (*rxhandler)(struct mimio *, unsigned char *, unsigned int); - int last_pen_down; -}; - -static void mimio_close(struct input_dev *); -static void mimio_dealloc(struct mimio *); -static void mimio_disconnect(struct usb_interface *); -static int mimio_greet(struct mimio *); -static void mimio_irq_in(struct urb *); -static void mimio_irq_out(struct urb *); -static int mimio_open(struct input_dev *); -static int mimio_probe(struct usb_interface *, const struct usb_device_id *); -static void mimio_rx_handler(struct mimio *, unsigned char *, unsigned int); -static int mimio_tx(struct mimio *, const char *, int); - -static char mimio_name[] = "VirtualInk mimio-Xi"; -static struct usb_device_id mimio_table[] = { - { USB_DEVICE(MIMIO_VENDOR_ID, MIMIO_PRODUCT_ID) }, - { USB_DEVICE(0x0525, 0xa4a0) }, /* gadget zero firmware */ - { } -}; - -MODULE_DEVICE_TABLE(usb, mimio_table); - -static struct usb_driver mimio_driver = { - .name = "mimio", - .probe = mimio_probe, - .disconnect = mimio_disconnect, - .id_table = mimio_table, -}; - -static DECLARE_MUTEX(disconnect_sem); - -static void mimio_close(struct input_dev *idev) -{ - struct mimio *mimio; - - mimio = input_get_drvdata(idev); - if (!mimio) { - dev_err(&idev->dev, "null mimio attached to input device\n"); - return; - } - - if (mimio->open <= 0) - dev_err(&idev->dev, "mimio not open.\n"); - else - mimio->open--; - - if (mimio->present == 0 && mimio->open == 0) - mimio_dealloc(mimio); -} - -static void mimio_dealloc(struct mimio *mimio) -{ - if (mimio == NULL) - return; - - usb_kill_urb(mimio->in.urb); - - usb_kill_urb(mimio->out.urb); - - if (mimio->idev) { - input_unregister_device(mimio->idev); - if (mimio->idev->grab) - input_close_device(mimio->idev->grab); - else - dev_dbg(&mimio->idev->dev, "mimio->idev->grab == NULL" - " -- didn't call input_close_device\n"); - } - - usb_free_urb(mimio->in.urb); - - usb_free_urb(mimio->out.urb); - - if (mimio->in.buf) { - usb_buffer_free(mimio->udev, MIMIO_MAXPAYLOAD, mimio->in.buf, - mimio->in.dma); - } - - if (mimio->out.buf) - usb_buffer_free(mimio->udev, MIMIO_MAXPAYLOAD, mimio->out.buf, - mimio->out.dma); - - if (mimio->idev) - input_free_device(mimio->idev); - - kfree(mimio); -} - -static void mimio_disconnect(struct usb_interface *ifc) -{ - struct mimio *mimio; - - down(&disconnect_sem); - - mimio = usb_get_intfdata(ifc); - usb_set_intfdata(ifc, NULL); - dev_dbg(&mimio->idev->dev, "disconnect\n"); - - if (mimio) { - mimio->present = 0; - - if (mimio->open <= 0) - mimio_dealloc(mimio); - } - - up(&disconnect_sem); -} - -static int mimio_greet(struct mimio *mimio) -{ - const struct grtpkt { - int nbytes; - unsigned delay; - char data[8]; - } grtpkts[] = { - { 3, 0, { 0x11, 0x55, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00 } }, - { 5, 0, { 0x53, 0x55, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00 } }, - { 5, 0, { 0x43, 0x55, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00 } }, - { 5, 0, { 0x33, 0x55, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00 } }, - { 5, 0, { 0x13, 0x00, 0x5e, 0x02, 0x4f, 0x00, 0x00, 0x00 } }, - { 5, 0, { 0x13, 0x00, 0x04, 0x03, 0x14, 0x00, 0x00, 0x00 } }, - { 5, 2, { 0x13, 0x00, 0x00, 0x04, 0x17, 0x00, 0x00, 0x00 } }, - { 5, 0, { 0x13, 0x00, 0x0d, 0x08, 0x16, 0x00, 0x00, 0x00 } }, - { 5, 0, { 0x13, 0x00, 0x4d, 0x01, 0x5f, 0x00, 0x00, 0x00 } }, - { 3, 0, { 0xf1, 0x55, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00 } }, - { 7, 2, { 0x52, 0x55, 0x00, 0x07, 0x31, 0x55, 0x64, 0x00 } }, - { 0, 0, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, - }; - int rslt; - const struct grtpkt *pkt; - - for (pkt = grtpkts; pkt->nbytes; pkt++) { - rslt = mimio_tx(mimio, pkt->data, pkt->nbytes); - if (rslt) - return rslt; - if (pkt->delay) - msleep(pkt->delay); - } - - return 0; -} - -static void mimio_irq_in(struct urb *urb) -{ - int rslt; - char *data; - const char *reason = "going down"; - struct mimio *mimio; - - mimio = urb->context; - - if (mimio == NULL) - /* paranoia */ - return; - - switch (urb->status) { - case 0: - /* success */ - break; - case -ETIMEDOUT: - reason = "timeout -- unplugged?"; - case -ECONNRESET: - case -ENOENT: - case -ESHUTDOWN: - dev_dbg(&mimio->idev->dev, "%s.\n", reason); - return; - default: - dev_dbg(&mimio->idev->dev, "unknown urb-status: %d.\n", - urb->status); - goto exit; - } - data = mimio->in.buf; - - if (mimio->rxhandler) - mimio->rxhandler(mimio, data, urb->actual_length); -exit: - /* - * Keep listening to device on same urb. - */ - rslt = usb_submit_urb(urb, GFP_ATOMIC); - if (rslt) - dev_err(&mimio->idev->dev, "usb_submit_urb failure: %d.\n", - rslt); -} - -static void mimio_irq_out(struct urb *urb) -{ - unsigned long flags; - struct mimio *mimio; - - mimio = urb->context; - - if (urb->status) - dev_dbg(&mimio->idev->dev, "urb-status: %d.\n", urb->status); - - spin_lock_irqsave(&mimio->txlock, flags); - mimio->txflags |= MIMIO_TXDONE; - spin_unlock_irqrestore(&mimio->txlock, flags); - wmb(); - wake_up(&mimio->waitq); -} - -static int mimio_open(struct input_dev *idev) -{ - int rslt; - struct mimio *mimio; - - rslt = 0; - down(&disconnect_sem); - mimio = input_get_drvdata(idev); - dev_dbg(&idev->dev, "mimio_open\n"); - - if (mimio == NULL) { - dev_err(&idev->dev, "null mimio.\n"); - rslt = -ENODEV; - goto exit; - } - - if (mimio->open++) - goto exit; - - if (mimio->present && !mimio->greeted) { - struct urb *urb = mimio->in.urb; - mimio->in.urb->dev = mimio->udev; - rslt = usb_submit_urb(mimio->in.urb, GFP_KERNEL); - if (rslt) { - dev_err(&idev->dev, "usb_submit_urb failure " - "(res = %d: ", rslt); - if (!urb) - dev_err(&idev->dev, "urb is NULL"); - else if (urb->hcpriv) - dev_err(&idev->dev, "urb->hcpriv is non-NULL"); - else if (!urb->complete) - dev_err(&idev->dev, "urb is not complete"); - else if (urb->number_of_packets <= 0) - dev_err(&idev->dev, "urb has no packets"); - else if (urb->interval <= 0) - dev_err(&idev->dev, "urb interval too small"); - else - dev_err(&idev->dev, "urb interval too large " \ - "or some other error"); - dev_err(&idev->dev, "). Not greeting.\n"); - rslt = -EIO; - goto exit; - } - rslt = mimio_greet(mimio); - if (rslt == 0) { - dev_dbg(&idev->dev, "Mimio greeted OK.\n"); - mimio->greeted = 1; - } else { - dev_dbg(&idev->dev, "Mimio greet Failure (%d)\n", - rslt); - } - } - -exit: - up(&disconnect_sem); - return rslt; -} - -static int mimio_probe(struct usb_interface *ifc, - const struct usb_device_id *id) -{ - char path[64]; - int pipe, maxp; - struct mimio *mimio; - struct usb_device *udev; - struct usb_host_interface *hostifc; - struct input_dev *input_dev; - int res = 0; - int i; - - udev = interface_to_usbdev(ifc); - - mimio = kzalloc(sizeof(struct mimio), GFP_KERNEL); - if (!mimio) - return -ENOMEM; - - input_dev = input_allocate_device(); - if (!input_dev) { - mimio_dealloc(mimio); - return -ENOMEM; - } - - mimio->uifc = ifc; - mimio->udev = udev; - mimio->pktbuf.p = mimio->pktbuf.buf; - mimio->pktbuf.q = mimio->pktbuf.buf; - /* init_input_dev(mimio->idev); */ - mimio->idev = input_dev; - init_waitqueue_head(&mimio->waitq); - spin_lock_init(&mimio->txlock); - hostifc = ifc->cur_altsetting; - - if (hostifc->desc.bNumEndpoints != 2) { - dev_err(&udev->dev, "Unexpected endpoint count: %d.\n", - hostifc->desc.bNumEndpoints); - mimio_dealloc(mimio); - return -ENODEV; - } - - mimio->in.desc = &(hostifc->endpoint[0].desc); - mimio->out.desc = &(hostifc->endpoint[1].desc); - - mimio->in.buf = usb_buffer_alloc(udev, MIMIO_MAXPAYLOAD, GFP_KERNEL, - &mimio->in.dma); - mimio->out.buf = usb_buffer_alloc(udev, MIMIO_MAXPAYLOAD, GFP_KERNEL, - &mimio->out.dma); - - if (mimio->in.buf == NULL || mimio->out.buf == NULL) { - dev_err(&udev->dev, "usb_buffer_alloc failure.\n"); - mimio_dealloc(mimio); - return -ENOMEM; - } - - mimio->in.urb = usb_alloc_urb(0, GFP_KERNEL); - mimio->out.urb = usb_alloc_urb(0, GFP_KERNEL); - - if (mimio->in.urb == NULL || mimio->out.urb == NULL) { - dev_err(&udev->dev, "usb_alloc_urb failure.\n"); - mimio_dealloc(mimio); - return -ENOMEM; - } - - /* - * Build the input urb. - */ - pipe = usb_rcvintpipe(udev, mimio->in.desc->bEndpointAddress); - maxp = usb_maxpacket(udev, pipe, usb_pipeout(pipe)); - if (maxp > MIMIO_MAXPAYLOAD) - maxp = MIMIO_MAXPAYLOAD; - usb_fill_int_urb(mimio->in.urb, udev, pipe, mimio->in.buf, maxp, - mimio_irq_in, mimio, mimio->in.desc->bInterval); - mimio->in.urb->transfer_dma = mimio->in.dma; - mimio->in.urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; - - /* - * Build the output urb. - */ - pipe = usb_sndintpipe(udev, mimio->out.desc->bEndpointAddress); - maxp = usb_maxpacket(udev, pipe, usb_pipeout(pipe)); - if (maxp > MIMIO_MAXPAYLOAD) - maxp = MIMIO_MAXPAYLOAD; - usb_fill_int_urb(mimio->out.urb, udev, pipe, mimio->out.buf, maxp, - mimio_irq_out, mimio, mimio->out.desc->bInterval); - mimio->out.urb->transfer_dma = mimio->out.dma; - mimio->out.urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; - - /* - * Build input device info - */ - usb_make_path(udev, path, 64); - snprintf(mimio->phys, MIMIO_MAXNAMELEN, "%s/input0", path); - input_set_drvdata(input_dev, mimio); - /* input_dev->dev = &ifc->dev; */ - input_dev->open = mimio_open; - input_dev->close = mimio_close; - input_dev->name = mimio_name; - input_dev->phys = mimio->phys; - input_dev->dev.parent = &ifc->dev; - - input_dev->id.bustype = BUS_USB; - input_dev->id.vendor = le16_to_cpu(udev->descriptor.idVendor); - input_dev->id.product = le16_to_cpu(udev->descriptor.idProduct); - input_dev->id.version = le16_to_cpu(udev->descriptor.bcdDevice); - - input_dev->evbit[0] |= BIT(EV_KEY) | BIT(EV_ABS); - for (i = BTN_TOOL_PEN; i <= LOCALBTN_TOOL_EXTRA2; ++i) - set_bit(i, input_dev->keybit); - - input_dev->keybit[BIT_WORD(BTN_MISC)] |= BIT_MASK(BTN_0) | - BIT_MASK(BTN_1) | - BIT_MASK(BTN_2) | - BIT_MASK(BTN_3) | - BIT_MASK(BTN_4) | - BIT_MASK(BTN_5); - /* input_dev->keybit[BTN_MOUSE] |= BIT(BTN_LEFT); */ - input_dev->absbit[0] |= BIT_MASK(ABS_X) | BIT_MASK(ABS_Y); - input_set_abs_params(input_dev, ABS_X, 0, MIMIO_XRANGE_MAX, 0, 0); - input_set_abs_params(input_dev, ABS_Y, 0, MIMIO_YRANGE_MAX, 0, 0); - input_dev->absbit[BIT_WORD(ABS_MISC)] |= BIT_MASK(ABS_MISC); - - /* - * Register the input device. - */ - res = input_register_device(mimio->idev); - if (res) { - dev_err(&udev->dev, "input_register_device failure (%d)\n", - res); - mimio_dealloc(mimio); - return -EIO; - } - dev_dbg(&mimio->idev->dev, "input: %s on %s (res = %d).\n", - input_dev->name, input_dev->phys, res); - - usb_set_intfdata(ifc, mimio); - mimio->present = 1; - - /* - * Submit the input urb to the usb subsystem. - */ - mimio->in.urb->dev = mimio->udev; - res = usb_submit_urb(mimio->in.urb, GFP_KERNEL); - if (res) { - dev_err(&mimio->idev->dev, "usb_submit_urb failure (%d)\n", - res); - mimio_dealloc(mimio); - return -EIO; - } - - /* - * Attempt to greet the mimio after giving - * it some post-init settling time. - * - * note: sometimes this sleep interval isn't - * long enough to permit the device to re-init - * after a hot-swap; maybe need to bump it up. - * - * As it is, this probably breaks module unloading support! - */ - msleep(1024); - - res = mimio_greet(mimio); - if (res == 0) { - dev_dbg(&mimio->idev->dev, "Mimio greeted OK.\n"); - mimio->greeted = 1; - mimio->rxhandler = mimio_rx_handler; - } else { - dev_dbg(&mimio->idev->dev, "Mimio greet Failure (%d)\n", res); - } - - return 0; -} - -static int handle_mimio_rx_penupdown(struct mimio *mimio, - int down, - const char *const instr[], - const int instr_ofst[]) -{ - int penid, x; - if (mimio->pktbuf.q - mimio->pktbuf.p < (down ? 4 : 3)) - return 1; /* partial pkt */ - - if (down) { - x = *mimio->pktbuf.p ^ *(mimio->pktbuf.p + 1) ^ - *(mimio->pktbuf.p + 2); - if (x != *(mimio->pktbuf.p + 3)) { - dev_dbg(&mimio->idev->dev, "EV_PEN%s: bad xsum.\n", - down ? "DOWN" : "UP"); - /* skip this event data */ - mimio->pktbuf.p += 4; - /* decode any remaining events */ - return 0; - } - penid = mimio->pktbuf.instr = *(mimio->pktbuf.p + 2); - if (penid > MIMIO_PEN_MAX) { - dev_dbg(&mimio->idev->dev, - "Unmapped penID (not in [0, %d]): %d\n", - MIMIO_PEN_MAX, (int)mimio->pktbuf.instr); - penid = mimio->pktbuf.instr = 0; - } - mimio->last_pen_down = penid; - } else { - penid = mimio->last_pen_down; - } - dev_dbg(&mimio->idev->dev, "%s (id %d, code %d) %s.\n", instr[penid], - instr_ofst[penid], penid, down ? "down" : "up"); - - if (instr_ofst[penid] >= 0) { - int code = BTN_TOOL_PEN + instr_ofst[penid]; - int value = down ? DOWNVALUE : UPVALUE; - if (code > KEY_MAX) - dev_dbg(&mimio->idev->dev, "input_event will ignore " - "-- code (%d) > KEY_MAX\n", code); - if (!test_bit(code, mimio->idev->keybit)) - dev_dbg(&mimio->idev->dev, "input_event will ignore " - "-- bit for code (%d) not enabled\n", code); - if (!!test_bit(code, mimio->idev->key) == value) - dev_dbg(&mimio->idev->dev, "input_event will ignore " - "-- bit for code (%d) already set to %d\n", - code, value); - if (value != DOWNVALUE) { - /* input_regs(mimio->idev, regs); */ - input_report_key(mimio->idev, code, value); - input_sync(mimio->idev); - } else { - /* wait until we get some coordinates */ - } - } else { - dev_dbg(&mimio->idev->dev, "penID offset[%d] == %d is < 0 " - "- not sending\n", penid, instr_ofst[penid]); - } - mimio->pktbuf.p += down ? 4 : 3; /* 3 for up, 4 for down */ - return 0; -} - -/* - * Stay tuned for partial-packet excitement. - * - * This routine buffers data packets received from the mimio device - * in the mimio's data space. This buffering is necessary because - * the mimio's in endpoint can serve us partial packets of data, and - * we want the driver to support the servicing of multiple mimios. - * Empirical evidence gathered so far suggests that the method of - * buffering packet data in the mimio's data space works. Previous - * versions of this driver did not buffer packet data in each mimio's - * data-space, and were therefore not able to service multiple mimios. - * Note that since the caller of this routine is running in interrupt - * context, care needs to be taken to ensure that this routine does not - * become bloated, and it may be that another spinlock is needed in each - * mimio to guard the buffered packet data properly. - */ -static void mimio_rx_handler(struct mimio *mimio, - unsigned char *data, - unsigned int nbytes) -{ - struct device *dev = &mimio->idev->dev; - unsigned int x; - unsigned int y; - static const char * const instr[] = { - "?0", - "black pen", "blue pen", "green pen", "red pen", - "brown pen", "orange pen", "purple pen", "yellow pen", - "big eraser", "lil eraser", - "?11", "?12", "?13", "?14", "?15", "?16", - "mimio interactive", "interactive button1", - "interactive button2" - }; - - /* Mimio Interactive gives: - * down: [0x22 0x01 0x11 0x32 0x24] - * b1 : [0x22 0x01 0x12 0x31 0x24] - * b2 : [0x22 0x01 0x13 0x30 0x24] - */ - static const int instr_ofst[] = { - -1, - 0, 1, 2, 3, - 9, 9, 9, 9, - 4, 5, - -1, -1, -1, -1, -1, -1, - 6, 7, 8, - }; - - memcpy(mimio->pktbuf.q, data, nbytes); - mimio->pktbuf.q += nbytes; - - while (mimio->pktbuf.p < mimio->pktbuf.q) { - int t = *mimio->pktbuf.p; - switch (t) { - case MIMIO_EV_PENUP: - case MIMIO_EV_PENDOWN: - if (handle_mimio_rx_penupdown(mimio, - t == MIMIO_EV_PENDOWN, - instr, instr_ofst)) - return; /* partial packet */ - break; - - case MIMIO_EV_PENDATA: - if (mimio->pktbuf.q - mimio->pktbuf.p < 6) - /* partial pkt */ - return; - x = *mimio->pktbuf.p ^ *(mimio->pktbuf.p + 1) ^ - *(mimio->pktbuf.p + 2) ^ - *(mimio->pktbuf.p + 3) ^ - *(mimio->pktbuf.p + 4); - if (x != *(mimio->pktbuf.p + 5)) { - dev_dbg(dev, "EV_PENDATA: bad xsum.\n"); - mimio->pktbuf.p += 6; /* skip this event data */ - break; /* decode any remaining events */ - } - x = *(mimio->pktbuf.p + 1); - x <<= 8; - x |= *(mimio->pktbuf.p + 2); - y = *(mimio->pktbuf.p + 3); - y <<= 8; - y |= *(mimio->pktbuf.p + 4); - dev_dbg(dev, "coord: (%d, %d)\n", x, y); - if (instr_ofst[mimio->pktbuf.instr] >= 0) { - int code = BTN_TOOL_PEN + - instr_ofst[mimio->last_pen_down]; - /* input_regs(mimio->idev, regs); */ - input_report_abs(mimio->idev, ABS_X, x); - input_report_abs(mimio->idev, ABS_Y, y); - /* fake a penup */ - change_bit(code, mimio->idev->key); - input_report_key(mimio->idev, - code, - DOWNVALUE); - /* always sync here */ - mimio->idev->sync = 0; - input_sync(mimio->idev); - } - mimio->pktbuf.p += 6; - break; - case MIMIO_EV_MEMRESET: - if (mimio->pktbuf.q - mimio->pktbuf.p < 7) - /* partial pkt */ - return; - dev_dbg(dev, "mem-reset.\n"); - /* input_regs(mimio->idev, regs); */ - input_event(mimio->idev, EV_KEY, BTN_0, 1); - input_event(mimio->idev, EV_KEY, BTN_0, 0); - input_sync(mimio->idev); - mimio->pktbuf.p += 7; - break; - case MIMIO_EV_ACC: - if (mimio->pktbuf.q - mimio->pktbuf.p < 4) - /* partial pkt */ - return; - x = *mimio->pktbuf.p ^ *(mimio->pktbuf.p + 1) ^ - *(mimio->pktbuf.p + 2); - if (x != *(mimio->pktbuf.p + 3)) { - dev_dbg(dev, "EV_ACC: bad xsum.\n"); - mimio->pktbuf.p += 4; /* skip this event data */ - break; /* decode any remaining events */ - } - switch (*(mimio->pktbuf.p + 2)) { - case ACC_NEWPAGE: - dev_dbg(&mimio->idev->dev, "new-page.\n"); - /* input_regs(mimio->idev, regs); */ - input_event(mimio->idev, EV_KEY, BTN_1, 1); - input_event(mimio->idev, EV_KEY, BTN_1, 0); - input_sync(mimio->idev); - break; - case ACC_TAGPAGE: - dev_dbg(&mimio->idev->dev, "tag-page.\n"); - /* input_regs(mimio->idev, regs); */ - input_event(mimio->idev, EV_KEY, BTN_2, 1); - input_event(mimio->idev, EV_KEY, BTN_2, 0); - input_sync(mimio->idev); - break; - case ACC_PRINTPAGE: - dev_dbg(&mimio->idev->dev, "print-page.\n"); - /* input_regs(mimio->idev, regs);*/ - input_event(mimio->idev, EV_KEY, BTN_3, 1); - input_event(mimio->idev, EV_KEY, BTN_3, 0); - input_sync(mimio->idev); - break; - case ACC_MAXIMIZE: - dev_dbg(&mimio->idev->dev, - "maximize-window.\n"); - /* input_regs(mimio->idev, regs); */ - input_event(mimio->idev, EV_KEY, BTN_4, 1); - input_event(mimio->idev, EV_KEY, BTN_4, 0); - input_sync(mimio->idev); - break; - case ACC_FINDCTLPNL: - dev_dbg(&mimio->idev->dev, "find-ctl-panel.\n"); - /* input_regs(mimio->idev, regs); */ - input_event(mimio->idev, EV_KEY, BTN_5, 1); - input_event(mimio->idev, EV_KEY, BTN_5, 0); - input_sync(mimio->idev); - break; - case ACC_DONE: - dev_dbg(&mimio->idev->dev, "acc-done.\n"); - /* no event is dispatched to the input - * subsystem for this device event. - */ - break; - default: - dev_dbg(dev, "unknown acc event.\n"); - break; - } - mimio->pktbuf.p += 4; - break; - default: - mimio->pktbuf.p++; - break; - } - } - - /* - * No partial event was received, so reset mimio's pktbuf ptrs. - */ - mimio->pktbuf.p = mimio->pktbuf.q = mimio->pktbuf.buf; -} - -static int mimio_tx(struct mimio *mimio, const char *buf, int nbytes) -{ - int rslt; - int timeout; - unsigned long flags; - DECLARE_WAITQUEUE(wait, current); - - if (!(isvalidtxsize(nbytes))) { - dev_err(&mimio->idev->dev, "invalid arg: nbytes: %d.\n", - nbytes); - return -EINVAL; - } - - /* - * Init the out urb and copy the data to send. - */ - mimio->out.urb->dev = mimio->udev; - mimio->out.urb->transfer_buffer_length = nbytes; - memcpy(mimio->out.urb->transfer_buffer, buf, nbytes); - - /* - * Send the data. - */ - spin_lock_irqsave(&mimio->txlock, flags); - mimio->txflags = MIMIO_TXWAIT; - rslt = usb_submit_urb(mimio->out.urb, GFP_ATOMIC); - spin_unlock_irqrestore(&mimio->txlock, flags); - dev_dbg(&mimio->idev->dev, "rslt: %d.\n", rslt); - - if (rslt) { - dev_err(&mimio->idev->dev, "usb_submit_urb failure: %d.\n", - rslt); - return rslt; - } - - /* - * Wait for completion to be signalled (the mimio_irq_out - * completion routine will or MIMIO_TXDONE in with txflags). - */ - timeout = HZ; - set_current_state(TASK_INTERRUPTIBLE); - add_wait_queue(&mimio->waitq, &wait); - - while (timeout && ((mimio->txflags & MIMIO_TXDONE) == 0)) { - timeout = schedule_timeout(timeout); - rmb(); - } - - if ((mimio->txflags & MIMIO_TXDONE) == 0) - dev_dbg(&mimio->idev->dev, "tx timed out.\n"); - - /* - * Now that completion has been signalled, - * unlink the urb so that it can be recycled. - */ - set_current_state(TASK_RUNNING); - remove_wait_queue(&mimio->waitq, &wait); - usb_unlink_urb(mimio->out.urb); - - return rslt; -} - -static int __init mimio_init(void) -{ - int rslt; - - rslt = usb_register(&mimio_driver); - if (rslt != 0) { - err("%s: usb_register failure: %d", __func__, rslt); - return rslt; - } - - printk(KERN_INFO KBUILD_MODNAME ":" - DRIVER_DESC " " DRIVER_VERSION "\n"); - return rslt; -} - -static void __exit mimio_exit(void) -{ - usb_deregister(&mimio_driver); -} - -module_init(mimio_init); -module_exit(mimio_exit); - -MODULE_AUTHOR(DRIVER_AUTHOR); -MODULE_DESCRIPTION(DRIVER_DESC); -MODULE_LICENSE("GPL"); -- cgit v1.2.3 From ee7dfb7e245e92c011c335e7bac2474967eda192 Mon Sep 17 00:00:00 2001 From: Mark Allyn Date: Fri, 5 Feb 2010 10:52:09 -0800 Subject: staging: rar_register: renaming driver to rar_register Patch renames rar_driver to rar_register to clarifiy and differentiate from rar_handler that will be submitted later Signed-off-by: Mark Allyn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rar/Makefile | 2 +- drivers/staging/rar/rar_driver.c | 440 ------------------------------------- drivers/staging/rar/rar_driver.h | 89 -------- drivers/staging/rar/rar_register.c | 440 +++++++++++++++++++++++++++++++++++++ drivers/staging/rar/rar_register.h | 89 ++++++++ 5 files changed, 530 insertions(+), 530 deletions(-) delete mode 100644 drivers/staging/rar/rar_driver.c delete mode 100644 drivers/staging/rar/rar_driver.h create mode 100644 drivers/staging/rar/rar_register.c create mode 100644 drivers/staging/rar/rar_register.h (limited to 'drivers') diff --git a/drivers/staging/rar/Makefile b/drivers/staging/rar/Makefile index 5422ed04ccf1..d5954ccc16c9 100644 --- a/drivers/staging/rar/Makefile +++ b/drivers/staging/rar/Makefile @@ -1,2 +1,2 @@ EXTRA_CFLAGS += -DLITTLE__ENDIAN -obj-$(CONFIG_RAR_REGISTER) += rar_driver.o +obj-$(CONFIG_RAR_REGISTER) += rar_register.o diff --git a/drivers/staging/rar/rar_driver.c b/drivers/staging/rar/rar_driver.c deleted file mode 100644 index a85a7da6df40..000000000000 --- a/drivers/staging/rar/rar_driver.c +++ /dev/null @@ -1,440 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rar_driver.h" - -/* The following defines are for the IPC process to retrieve RAR in */ - -/* === Lincroft Message Bus Interface === */ -/* Message Control Register */ -#define LNC_MCR_OFFSET 0xD0 - -/* Message Data Register */ -#define LNC_MDR_OFFSET 0xD4 - -/* Message Opcodes */ -#define LNC_MESSAGE_READ_OPCODE 0xD0 -#define LNC_MESSAGE_WRITE_OPCODE 0xE0 - -/* Message Write Byte Enables */ -#define LNC_MESSAGE_BYTE_WRITE_ENABLES 0xF - -/* B-unit Port */ -#define LNC_BUNIT_PORT 0x3 - -/* === Lincroft B-Unit Registers - Programmed by IA32 firmware === */ -#define LNC_BRAR0L 0x10 -#define LNC_BRAR0H 0x11 -#define LNC_BRAR1L 0x12 -#define LNC_BRAR1H 0x13 - -/* Reserved for SeP */ -#define LNC_BRAR2L 0x14 -#define LNC_BRAR2H 0x15 - - -/* This structure is only used during module initialization. */ -struct RAR_offsets { - int low; /* Register offset for low RAR physical address. */ - int high; /* Register offset for high RAR physical address. */ -}; - -struct pci_dev *rar_dev; -static uint32_t registered; - -/* Moorestown supports three restricted access regions. */ -#define MRST_NUM_RAR 3 - -struct RAR_address_struct rar_addr[MRST_NUM_RAR]; - -/* prototype for init */ -static int __init rar_init_handler(void); -static void __exit rar_exit_handler(void); - -/* - function that is activated on the successfull probe of the RAR device -*/ -static int __devinit rar_probe(struct pci_dev *pdev, - const struct pci_device_id *ent); - -static const struct pci_device_id rar_pci_id_tbl[] = { - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4110) }, - { 0 } -}; - -MODULE_DEVICE_TABLE(pci, rar_pci_id_tbl); - -/* field for registering driver to PCI device */ -static struct pci_driver rar_pci_driver = { - .name = "rar_driver", - .id_table = rar_pci_id_tbl, - .probe = rar_probe -}; - -/* This function is used to retrieved RAR info using the IPC message - bus interface */ -static int memrar_get_rar_addr(struct pci_dev *pdev, - int offset, - u32 *addr) -{ - /* - * ======== The Lincroft Message Bus Interface ======== - * Lincroft registers may be obtained from the PCI - * (the Host Bridge) using the Lincroft Message Bus - * Interface. That message bus interface is generally - * comprised of two registers: a control register (MCR, 0xDO) - * and a data register (MDR, 0xD4). - * - * The MCR (message control register) format is the following: - * 1. [31:24]: Opcode - * 2. [23:16]: Port - * 3. [15:8]: Register Offset - * 4. [7:4]: Byte Enables (use 0xF to set all of these bits - * to 1) - * 5. [3:0]: reserved - * - * Read (0xD0) and write (0xE0) opcodes are written to the - * control register when reading and writing to Lincroft - * registers, respectively. - * - * We're interested in registers found in the Lincroft - * B-unit. The B-unit port is 0x3. - * - * The six B-unit RAR register offsets we use are listed - * earlier in this file. - * - * Lastly writing to the MCR register requires the "Byte - * enables" bits to be set to 1. This may be achieved by - * writing 0xF at bit 4. - * - * The MDR (message data register) format is the following: - * 1. [31:0]: Read/Write Data - * - * Data being read from this register is only available after - * writing the appropriate control message to the MCR - * register. - * - * Data being written to this register must be written before - * writing the appropriate control message to the MCR - * register. - */ - - int result = 0; /* result */ - /* Construct control message */ - u32 const message = - (LNC_MESSAGE_READ_OPCODE << 24) - | (LNC_BUNIT_PORT << 16) - | (offset << 8) - | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); - - printk(KERN_WARNING "rar- offset to LNC MSG is %x\n", offset); - - if (addr == 0) - return -EINVAL; - - /* Send the control message */ - result = pci_write_config_dword(pdev, - LNC_MCR_OFFSET, - message); - - printk(KERN_WARNING "rar- result from send ctl register is %x\n", - result); - - if (!result) - result = pci_read_config_dword(pdev, - LNC_MDR_OFFSET, - addr); - - printk(KERN_WARNING "rar- result from read data register is %x\n", - result); - - printk(KERN_WARNING "rar- value read from data register is %x\n", - *addr); - - if (result) - return -1; - else - return 0; -} - -static int memrar_set_rar_addr(struct pci_dev *pdev, - int offset, - u32 addr) -{ - /* - * ======== The Lincroft Message Bus Interface ======== - * Lincroft registers may be obtained from the PCI - * (the Host Bridge) using the Lincroft Message Bus - * Interface. That message bus interface is generally - * comprised of two registers: a control register (MCR, 0xDO) - * and a data register (MDR, 0xD4). - * - * The MCR (message control register) format is the following: - * 1. [31:24]: Opcode - * 2. [23:16]: Port - * 3. [15:8]: Register Offset - * 4. [7:4]: Byte Enables (use 0xF to set all of these bits - * to 1) - * 5. [3:0]: reserved - * - * Read (0xD0) and write (0xE0) opcodes are written to the - * control register when reading and writing to Lincroft - * registers, respectively. - * - * We're interested in registers found in the Lincroft - * B-unit. The B-unit port is 0x3. - * - * The six B-unit RAR register offsets we use are listed - * earlier in this file. - * - * Lastly writing to the MCR register requires the "Byte - * enables" bits to be set to 1. This may be achieved by - * writing 0xF at bit 4. - * - * The MDR (message data register) format is the following: - * 1. [31:0]: Read/Write Data - * - * Data being read from this register is only available after - * writing the appropriate control message to the MCR - * register. - * - * Data being written to this register must be written before - * writing the appropriate control message to the MCR - * register. - */ - - int result = 0; /* result */ - - /* Construct control message */ - u32 const message = - (LNC_MESSAGE_WRITE_OPCODE << 24) - | (LNC_BUNIT_PORT << 16) - | (offset << 8) - | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); - - printk(KERN_WARNING "rar- offset to LNC MSG is %x\n", offset); - - if (addr == 0) - return -EINVAL; - - /* Send the control message */ - result = pci_write_config_dword(pdev, - LNC_MDR_OFFSET, - addr); - - printk(KERN_WARNING "rar- result from send ctl register is %x\n", - result); - - if (!result) - result = pci_write_config_dword(pdev, - LNC_MCR_OFFSET, - message); - - printk(KERN_WARNING "rar- result from write data register is %x\n", - result); - - printk(KERN_WARNING "rar- value read to data register is %x\n", - addr); - - if (result) - return -1; - else - return 0; -} - -/* - - * Initialize RAR parameters, such as physical addresses, etc. - - */ -static int memrar_init_rar_params(struct pci_dev *pdev) -{ - struct RAR_offsets const offsets[] = { - { LNC_BRAR0L, LNC_BRAR0H }, - { LNC_BRAR1L, LNC_BRAR1H }, - { LNC_BRAR2L, LNC_BRAR2H } - }; - - size_t const num_offsets = sizeof(offsets) / sizeof(offsets[0]); - struct RAR_offsets const *end = offsets + num_offsets; - struct RAR_offsets const *i; - unsigned int n = 0; - int result = 0; - - /* Retrieve RAR start and end physical addresses. */ - - /* - * Access the RAR registers through the Lincroft Message Bus - * Interface on PCI device: 00:00.0 Host bridge. - */ - - /* struct pci_dev *pdev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); */ - - if (pdev == NULL) - return -ENODEV; - - for (i = offsets; i != end; ++i, ++n) { - if (memrar_get_rar_addr(pdev, - (*i).low, - &(rar_addr[n].low)) != 0 - || memrar_get_rar_addr(pdev, - (*i).high, - &(rar_addr[n].high)) != 0) { - result = -1; - break; - } - } - - /* Done accessing the device. */ - /* pci_dev_put(pdev); */ - - if (result == 0) { - if (1) { - size_t z; - for (z = 0; z != MRST_NUM_RAR; ++z) { - printk(KERN_WARNING - "rar - BRAR[%Zd] physical address low\n" - "\tlow: 0x%08x\n" - "\thigh: 0x%08x\n", - z, - rar_addr[z].low, - rar_addr[z].high); - } - } - } - - return result; -} - -/* - function that is activated on the successfull probe of the RAR device -*/ -static int __devinit rar_probe(struct pci_dev *pdev, - const struct pci_device_id *ent) -{ - /* error */ - int error; - - /*------------------------ - CODE - ---------------------------*/ - - DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, - "Rar pci probe starting\n"); - error = 0; - - /* enable the device */ - error = pci_enable_device(pdev); - if (error) { - DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, - "error enabling pci device\n"); - goto end_function; - } - - rar_dev = pdev; - registered = 1; - - /* Initialize the RAR parameters, which have to be retrieved */ - /* via the message bus service */ - error = memrar_init_rar_params(rar_dev); - - if (error) { - DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, - "error getting RAR addresses device\n"); - registered = 0; - goto end_function; - } - -end_function: - - return error; -} - -/* - this function registers the driver to - the device subsystem (either PCI, USB, etc) -*/ -static int __init rar_init_handler(void) -{ - return pci_register_driver(&rar_pci_driver); -} - -static void __exit rar_exit_handler(void) -{ - pci_unregister_driver(&rar_pci_driver); -} - -module_init(rar_init_handler); -module_exit(rar_exit_handler); - -MODULE_LICENSE("GPL"); - - -/* The get_rar_address function is used by other device drivers - * to obtain RAR address information on a RAR. It takes two - * parameter: - * - * int rar_index - * The rar_index is an index to the rar for which you wish to retrieve - * the address information. - * Values can be 0,1, or 2. - * - * struct RAR_address_struct is a pointer to a place to which the function - * can return the address structure for the RAR. - * - * The function returns a 0 upon success or a -1 if there is no RAR - * facility on this system. - */ -int get_rar_address(int rar_index, struct RAR_address_struct *addresses) -{ - if (registered && (rar_index < 3) && (rar_index >= 0)) { - *addresses = rar_addr[rar_index]; - /* strip off lock bit information */ - addresses->low = addresses->low & 0xfffffff0; - addresses->high = addresses->high & 0xfffffff0; - return 0; - } else - return -ENODEV; -} -EXPORT_SYMBOL(get_rar_address); - -/* The lock_rar function is used by other device drivers to lock an RAR. - * once an RAR is locked, it stays locked until the next system reboot. - * The function takes one parameter: - * - * int rar_index - * The rar_index is an index to the rar that you want to lock. - * Values can be 0,1, or 2. - * - * The function returns a 0 upon success or a -1 if there is no RAR - * facility on this system. - */ -int lock_rar(int rar_index) -{ - u32 working_addr; - int result; - - if (registered && (rar_index < 3) && (rar_index >= 0)) { - /* first make sure that lock bits are clear (this does lock) */ - working_addr = rar_addr[rar_index].low & 0xfffffff0; - - /* now send that value to the register using the IPC */ - result = memrar_set_rar_addr(rar_dev, rar_index, working_addr); - return result; - } else - return -ENODEV; -} diff --git a/drivers/staging/rar/rar_driver.h b/drivers/staging/rar/rar_driver.h deleted file mode 100644 index 4172fbf36327..000000000000 --- a/drivers/staging/rar/rar_driver.h +++ /dev/null @@ -1,89 +0,0 @@ -/* === RAR Physical Addresses === */ -struct RAR_address_struct { - u32 low; - u32 high; -}; - -/* The get_rar_address function is used by other device drivers - * to obtain RAR address information on a RAR. It takes two - * parameter: - * - * int rar_index - * The rar_index is an index to the rar for which you wish to retrieve - * the address information. - * Values can be 0,1, or 2. - * - * struct RAR_address_struct is a pointer to a place to which the function - * can return the address structure for the RAR. - * - * The function returns a 0 upon success or a -1 if there is no RAR - * facility on this system. - */ -int get_rar_address(int rar_index, struct RAR_address_struct *addresses); - - -/* The lock_rar function is used by other device drivers to lock an RAR. - * once an RAR is locked, it stays locked until the next system reboot. - * The function takes one parameter: - * - * int rar_index - * The rar_index is an index to the rar that you want to lock. - * Values can be 0,1, or 2. - * - * The function returns a 0 upon success or a -1 if there is no RAR - * facility on this system. - */ -int lock_rar(int rar_index); - - -/* DEBUG LEVEL MASKS */ -#define RAR_DEBUG_LEVEL_BASIC 0x1 - -#define RAR_DEBUG_LEVEL_REGISTERS 0x2 - -#define RAR_DEBUG_LEVEL_EXTENDED 0x4 - -#define DEBUG_LEVEL 0x7 - -/* FUNCTIONAL MACROS */ - -/* debug macro without paramaters */ -#define DEBUG_PRINT_0(DEBUG_LEVEL , info) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info); \ - } \ -} while (0) - -/* debug macro with 1 paramater */ -#define DEBUG_PRINT_1(DEBUG_LEVEL , info , param1) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info , param1); \ - } \ -} while (0) - -/* debug macro with 2 paramaters */ -#define DEBUG_PRINT_2(DEBUG_LEVEL , info , param1, param2) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info , param1, param2); \ - } \ -} while (0) - -/* debug macro with 3 paramaters */ -#define DEBUG_PRINT_3(DEBUG_LEVEL , info , param1, param2 , param3) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info , param1, param2 , param3); \ - } \ -} while (0) - -/* debug macro with 4 paramaters */ -#define DEBUG_PRINT_4(DEBUG_LEVEL , info , param1, param2 , param3 , param4) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info , param1, param2 , param3 , param4); \ - } \ -} while (0) - diff --git a/drivers/staging/rar/rar_register.c b/drivers/staging/rar/rar_register.c new file mode 100644 index 000000000000..51eb5a360f1c --- /dev/null +++ b/drivers/staging/rar/rar_register.c @@ -0,0 +1,440 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rar_register.h" + +/* The following defines are for the IPC process to retrieve RAR in */ + +/* === Lincroft Message Bus Interface === */ +/* Message Control Register */ +#define LNC_MCR_OFFSET 0xD0 + +/* Message Data Register */ +#define LNC_MDR_OFFSET 0xD4 + +/* Message Opcodes */ +#define LNC_MESSAGE_READ_OPCODE 0xD0 +#define LNC_MESSAGE_WRITE_OPCODE 0xE0 + +/* Message Write Byte Enables */ +#define LNC_MESSAGE_BYTE_WRITE_ENABLES 0xF + +/* B-unit Port */ +#define LNC_BUNIT_PORT 0x3 + +/* === Lincroft B-Unit Registers - Programmed by IA32 firmware === */ +#define LNC_BRAR0L 0x10 +#define LNC_BRAR0H 0x11 +#define LNC_BRAR1L 0x12 +#define LNC_BRAR1H 0x13 + +/* Reserved for SeP */ +#define LNC_BRAR2L 0x14 +#define LNC_BRAR2H 0x15 + + +/* This structure is only used during module initialization. */ +struct RAR_offsets { + int low; /* Register offset for low RAR physical address. */ + int high; /* Register offset for high RAR physical address. */ +}; + +struct pci_dev *rar_dev; +static uint32_t registered; + +/* Moorestown supports three restricted access regions. */ +#define MRST_NUM_RAR 3 + +struct RAR_address_struct rar_addr[MRST_NUM_RAR]; + +/* prototype for init */ +static int __init rar_init_handler(void); +static void __exit rar_exit_handler(void); + +/* + function that is activated on the successfull probe of the RAR device +*/ +static int __devinit rar_probe(struct pci_dev *pdev, + const struct pci_device_id *ent); + +static const struct pci_device_id rar_pci_id_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4110) }, + { 0 } +}; + +MODULE_DEVICE_TABLE(pci, rar_pci_id_tbl); + +/* field for registering driver to PCI device */ +static struct pci_driver rar_pci_driver = { + .name = "rar_driver", + .id_table = rar_pci_id_tbl, + .probe = rar_probe +}; + +/* This function is used to retrieved RAR info using the IPC message + bus interface */ +static int memrar_get_rar_addr(struct pci_dev *pdev, + int offset, + u32 *addr) +{ + /* + * ======== The Lincroft Message Bus Interface ======== + * Lincroft registers may be obtained from the PCI + * (the Host Bridge) using the Lincroft Message Bus + * Interface. That message bus interface is generally + * comprised of two registers: a control register (MCR, 0xDO) + * and a data register (MDR, 0xD4). + * + * The MCR (message control register) format is the following: + * 1. [31:24]: Opcode + * 2. [23:16]: Port + * 3. [15:8]: Register Offset + * 4. [7:4]: Byte Enables (use 0xF to set all of these bits + * to 1) + * 5. [3:0]: reserved + * + * Read (0xD0) and write (0xE0) opcodes are written to the + * control register when reading and writing to Lincroft + * registers, respectively. + * + * We're interested in registers found in the Lincroft + * B-unit. The B-unit port is 0x3. + * + * The six B-unit RAR register offsets we use are listed + * earlier in this file. + * + * Lastly writing to the MCR register requires the "Byte + * enables" bits to be set to 1. This may be achieved by + * writing 0xF at bit 4. + * + * The MDR (message data register) format is the following: + * 1. [31:0]: Read/Write Data + * + * Data being read from this register is only available after + * writing the appropriate control message to the MCR + * register. + * + * Data being written to this register must be written before + * writing the appropriate control message to the MCR + * register. + */ + + int result = 0; /* result */ + /* Construct control message */ + u32 const message = + (LNC_MESSAGE_READ_OPCODE << 24) + | (LNC_BUNIT_PORT << 16) + | (offset << 8) + | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); + + printk(KERN_WARNING "rar- offset to LNC MSG is %x\n", offset); + + if (addr == 0) + return -EINVAL; + + /* Send the control message */ + result = pci_write_config_dword(pdev, + LNC_MCR_OFFSET, + message); + + printk(KERN_WARNING "rar- result from send ctl register is %x\n", + result); + + if (!result) + result = pci_read_config_dword(pdev, + LNC_MDR_OFFSET, + addr); + + printk(KERN_WARNING "rar- result from read data register is %x\n", + result); + + printk(KERN_WARNING "rar- value read from data register is %x\n", + *addr); + + if (result) + return -1; + else + return 0; +} + +static int memrar_set_rar_addr(struct pci_dev *pdev, + int offset, + u32 addr) +{ + /* + * ======== The Lincroft Message Bus Interface ======== + * Lincroft registers may be obtained from the PCI + * (the Host Bridge) using the Lincroft Message Bus + * Interface. That message bus interface is generally + * comprised of two registers: a control register (MCR, 0xDO) + * and a data register (MDR, 0xD4). + * + * The MCR (message control register) format is the following: + * 1. [31:24]: Opcode + * 2. [23:16]: Port + * 3. [15:8]: Register Offset + * 4. [7:4]: Byte Enables (use 0xF to set all of these bits + * to 1) + * 5. [3:0]: reserved + * + * Read (0xD0) and write (0xE0) opcodes are written to the + * control register when reading and writing to Lincroft + * registers, respectively. + * + * We're interested in registers found in the Lincroft + * B-unit. The B-unit port is 0x3. + * + * The six B-unit RAR register offsets we use are listed + * earlier in this file. + * + * Lastly writing to the MCR register requires the "Byte + * enables" bits to be set to 1. This may be achieved by + * writing 0xF at bit 4. + * + * The MDR (message data register) format is the following: + * 1. [31:0]: Read/Write Data + * + * Data being read from this register is only available after + * writing the appropriate control message to the MCR + * register. + * + * Data being written to this register must be written before + * writing the appropriate control message to the MCR + * register. + */ + + int result = 0; /* result */ + + /* Construct control message */ + u32 const message = + (LNC_MESSAGE_WRITE_OPCODE << 24) + | (LNC_BUNIT_PORT << 16) + | (offset << 8) + | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); + + printk(KERN_WARNING "rar- offset to LNC MSG is %x\n", offset); + + if (addr == 0) + return -EINVAL; + + /* Send the control message */ + result = pci_write_config_dword(pdev, + LNC_MDR_OFFSET, + addr); + + printk(KERN_WARNING "rar- result from send ctl register is %x\n", + result); + + if (!result) + result = pci_write_config_dword(pdev, + LNC_MCR_OFFSET, + message); + + printk(KERN_WARNING "rar- result from write data register is %x\n", + result); + + printk(KERN_WARNING "rar- value read to data register is %x\n", + addr); + + if (result) + return -1; + else + return 0; +} + +/* + + * Initialize RAR parameters, such as physical addresses, etc. + + */ +static int memrar_init_rar_params(struct pci_dev *pdev) +{ + struct RAR_offsets const offsets[] = { + { LNC_BRAR0L, LNC_BRAR0H }, + { LNC_BRAR1L, LNC_BRAR1H }, + { LNC_BRAR2L, LNC_BRAR2H } + }; + + size_t const num_offsets = sizeof(offsets) / sizeof(offsets[0]); + struct RAR_offsets const *end = offsets + num_offsets; + struct RAR_offsets const *i; + unsigned int n = 0; + int result = 0; + + /* Retrieve RAR start and end physical addresses. */ + + /* + * Access the RAR registers through the Lincroft Message Bus + * Interface on PCI device: 00:00.0 Host bridge. + */ + + /* struct pci_dev *pdev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); */ + + if (pdev == NULL) + return -ENODEV; + + for (i = offsets; i != end; ++i, ++n) { + if (memrar_get_rar_addr(pdev, + (*i).low, + &(rar_addr[n].low)) != 0 + || memrar_get_rar_addr(pdev, + (*i).high, + &(rar_addr[n].high)) != 0) { + result = -1; + break; + } + } + + /* Done accessing the device. */ + /* pci_dev_put(pdev); */ + + if (result == 0) { + if (1) { + size_t z; + for (z = 0; z != MRST_NUM_RAR; ++z) { + printk(KERN_WARNING + "rar - BRAR[%Zd] physical address low\n" + "\tlow: 0x%08x\n" + "\thigh: 0x%08x\n", + z, + rar_addr[z].low, + rar_addr[z].high); + } + } + } + + return result; +} + +/* + function that is activated on the successfull probe of the RAR device +*/ +static int __devinit rar_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + /* error */ + int error; + + /*------------------------ + CODE + ---------------------------*/ + + DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, + "Rar pci probe starting\n"); + error = 0; + + /* enable the device */ + error = pci_enable_device(pdev); + if (error) { + DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, + "error enabling pci device\n"); + goto end_function; + } + + rar_dev = pdev; + registered = 1; + + /* Initialize the RAR parameters, which have to be retrieved */ + /* via the message bus service */ + error = memrar_init_rar_params(rar_dev); + + if (error) { + DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, + "error getting RAR addresses device\n"); + registered = 0; + goto end_function; + } + +end_function: + + return error; +} + +/* + this function registers the driver to + the device subsystem (either PCI, USB, etc) +*/ +static int __init rar_init_handler(void) +{ + return pci_register_driver(&rar_pci_driver); +} + +static void __exit rar_exit_handler(void) +{ + pci_unregister_driver(&rar_pci_driver); +} + +module_init(rar_init_handler); +module_exit(rar_exit_handler); + +MODULE_LICENSE("GPL"); + + +/* The get_rar_address function is used by other device drivers + * to obtain RAR address information on a RAR. It takes two + * parameter: + * + * int rar_index + * The rar_index is an index to the rar for which you wish to retrieve + * the address information. + * Values can be 0,1, or 2. + * + * struct RAR_address_struct is a pointer to a place to which the function + * can return the address structure for the RAR. + * + * The function returns a 0 upon success or a -1 if there is no RAR + * facility on this system. + */ +int get_rar_address(int rar_index, struct RAR_address_struct *addresses) +{ + if (registered && (rar_index < 3) && (rar_index >= 0)) { + *addresses = rar_addr[rar_index]; + /* strip off lock bit information */ + addresses->low = addresses->low & 0xfffffff0; + addresses->high = addresses->high & 0xfffffff0; + return 0; + } else + return -ENODEV; +} +EXPORT_SYMBOL(get_rar_address); + +/* The lock_rar function is used by other device drivers to lock an RAR. + * once an RAR is locked, it stays locked until the next system reboot. + * The function takes one parameter: + * + * int rar_index + * The rar_index is an index to the rar that you want to lock. + * Values can be 0,1, or 2. + * + * The function returns a 0 upon success or a -1 if there is no RAR + * facility on this system. + */ +int lock_rar(int rar_index) +{ + u32 working_addr; + int result; + + if (registered && (rar_index < 3) && (rar_index >= 0)) { + /* first make sure that lock bits are clear (this does lock) */ + working_addr = rar_addr[rar_index].low & 0xfffffff0; + + /* now send that value to the register using the IPC */ + result = memrar_set_rar_addr(rar_dev, rar_index, working_addr); + return result; + } else + return -ENODEV; +} diff --git a/drivers/staging/rar/rar_register.h b/drivers/staging/rar/rar_register.h new file mode 100644 index 000000000000..4172fbf36327 --- /dev/null +++ b/drivers/staging/rar/rar_register.h @@ -0,0 +1,89 @@ +/* === RAR Physical Addresses === */ +struct RAR_address_struct { + u32 low; + u32 high; +}; + +/* The get_rar_address function is used by other device drivers + * to obtain RAR address information on a RAR. It takes two + * parameter: + * + * int rar_index + * The rar_index is an index to the rar for which you wish to retrieve + * the address information. + * Values can be 0,1, or 2. + * + * struct RAR_address_struct is a pointer to a place to which the function + * can return the address structure for the RAR. + * + * The function returns a 0 upon success or a -1 if there is no RAR + * facility on this system. + */ +int get_rar_address(int rar_index, struct RAR_address_struct *addresses); + + +/* The lock_rar function is used by other device drivers to lock an RAR. + * once an RAR is locked, it stays locked until the next system reboot. + * The function takes one parameter: + * + * int rar_index + * The rar_index is an index to the rar that you want to lock. + * Values can be 0,1, or 2. + * + * The function returns a 0 upon success or a -1 if there is no RAR + * facility on this system. + */ +int lock_rar(int rar_index); + + +/* DEBUG LEVEL MASKS */ +#define RAR_DEBUG_LEVEL_BASIC 0x1 + +#define RAR_DEBUG_LEVEL_REGISTERS 0x2 + +#define RAR_DEBUG_LEVEL_EXTENDED 0x4 + +#define DEBUG_LEVEL 0x7 + +/* FUNCTIONAL MACROS */ + +/* debug macro without paramaters */ +#define DEBUG_PRINT_0(DEBUG_LEVEL , info) \ +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info); \ + } \ +} while (0) + +/* debug macro with 1 paramater */ +#define DEBUG_PRINT_1(DEBUG_LEVEL , info , param1) \ +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info , param1); \ + } \ +} while (0) + +/* debug macro with 2 paramaters */ +#define DEBUG_PRINT_2(DEBUG_LEVEL , info , param1, param2) \ +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info , param1, param2); \ + } \ +} while (0) + +/* debug macro with 3 paramaters */ +#define DEBUG_PRINT_3(DEBUG_LEVEL , info , param1, param2 , param3) \ +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info , param1, param2 , param3); \ + } \ +} while (0) + +/* debug macro with 4 paramaters */ +#define DEBUG_PRINT_4(DEBUG_LEVEL , info , param1, param2 , param3 , param4) \ +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info , param1, param2 , param3 , param4); \ + } \ +} while (0) + -- cgit v1.2.3 From e33cc5cec039ac6aef68568c06998707bceb0953 Mon Sep 17 00:00:00 2001 From: Mark Allyn Date: Fri, 5 Feb 2010 10:52:26 -0800 Subject: Staging: rar_register: renaming directory to rar_register Renames the directory in which the driver files are located; again for clarity. Signed-off-by: Mark Allyn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/Kconfig | 2 +- drivers/staging/Makefile | 2 +- drivers/staging/rar/Kconfig | 17 -- drivers/staging/rar/Makefile | 2 - drivers/staging/rar/rar_register.c | 440 ---------------------------- drivers/staging/rar/rar_register.h | 89 ------ drivers/staging/rar_register/Kconfig | 17 ++ drivers/staging/rar_register/Makefile | 2 + drivers/staging/rar_register/rar_register.c | 440 ++++++++++++++++++++++++++++ drivers/staging/rar_register/rar_register.h | 89 ++++++ 10 files changed, 550 insertions(+), 550 deletions(-) delete mode 100644 drivers/staging/rar/Kconfig delete mode 100644 drivers/staging/rar/Makefile delete mode 100644 drivers/staging/rar/rar_register.c delete mode 100644 drivers/staging/rar/rar_register.h create mode 100644 drivers/staging/rar_register/Kconfig create mode 100644 drivers/staging/rar_register/Makefile create mode 100644 drivers/staging/rar_register/rar_register.c create mode 100644 drivers/staging/rar_register/rar_register.h (limited to 'drivers') diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 9b396bdbeeb5..7696a664f8a5 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -109,7 +109,7 @@ source "drivers/staging/hv/Kconfig" source "drivers/staging/vme/Kconfig" -source "drivers/staging/rar/Kconfig" +source "drivers/staging/rar_register/Kconfig" source "drivers/staging/sep/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index 95ef22081a4c..ea2e70e2fed4 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -35,7 +35,7 @@ obj-$(CONFIG_VT6656) += vt6656/ obj-$(CONFIG_FB_UDL) += udlfb/ obj-$(CONFIG_HYPERV) += hv/ obj-$(CONFIG_VME_BUS) += vme/ -obj-$(CONFIG_RAR_REGISTER) += rar/ +obj-$(CONFIG_RAR_REGISTER) += rar_register/ obj-$(CONFIG_DX_SEP) += sep/ obj-$(CONFIG_IIO) += iio/ obj-$(CONFIG_RAMZSWAP) += ramzswap/ diff --git a/drivers/staging/rar/Kconfig b/drivers/staging/rar/Kconfig deleted file mode 100644 index 17f8bf3bb41a..000000000000 --- a/drivers/staging/rar/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# RAR device configuration -# - -menu "RAR Register Driver" -# -# Restricted Access Register Manager -# -config RAR_REGISTER - tristate "Restricted Access Region Register Driver" - default n - ---help--- - This driver allows other kernel drivers access to the - contents of the restricted access region control - registers. - -endmenu diff --git a/drivers/staging/rar/Makefile b/drivers/staging/rar/Makefile deleted file mode 100644 index d5954ccc16c9..000000000000 --- a/drivers/staging/rar/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -EXTRA_CFLAGS += -DLITTLE__ENDIAN -obj-$(CONFIG_RAR_REGISTER) += rar_register.o diff --git a/drivers/staging/rar/rar_register.c b/drivers/staging/rar/rar_register.c deleted file mode 100644 index 51eb5a360f1c..000000000000 --- a/drivers/staging/rar/rar_register.c +++ /dev/null @@ -1,440 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rar_register.h" - -/* The following defines are for the IPC process to retrieve RAR in */ - -/* === Lincroft Message Bus Interface === */ -/* Message Control Register */ -#define LNC_MCR_OFFSET 0xD0 - -/* Message Data Register */ -#define LNC_MDR_OFFSET 0xD4 - -/* Message Opcodes */ -#define LNC_MESSAGE_READ_OPCODE 0xD0 -#define LNC_MESSAGE_WRITE_OPCODE 0xE0 - -/* Message Write Byte Enables */ -#define LNC_MESSAGE_BYTE_WRITE_ENABLES 0xF - -/* B-unit Port */ -#define LNC_BUNIT_PORT 0x3 - -/* === Lincroft B-Unit Registers - Programmed by IA32 firmware === */ -#define LNC_BRAR0L 0x10 -#define LNC_BRAR0H 0x11 -#define LNC_BRAR1L 0x12 -#define LNC_BRAR1H 0x13 - -/* Reserved for SeP */ -#define LNC_BRAR2L 0x14 -#define LNC_BRAR2H 0x15 - - -/* This structure is only used during module initialization. */ -struct RAR_offsets { - int low; /* Register offset for low RAR physical address. */ - int high; /* Register offset for high RAR physical address. */ -}; - -struct pci_dev *rar_dev; -static uint32_t registered; - -/* Moorestown supports three restricted access regions. */ -#define MRST_NUM_RAR 3 - -struct RAR_address_struct rar_addr[MRST_NUM_RAR]; - -/* prototype for init */ -static int __init rar_init_handler(void); -static void __exit rar_exit_handler(void); - -/* - function that is activated on the successfull probe of the RAR device -*/ -static int __devinit rar_probe(struct pci_dev *pdev, - const struct pci_device_id *ent); - -static const struct pci_device_id rar_pci_id_tbl[] = { - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4110) }, - { 0 } -}; - -MODULE_DEVICE_TABLE(pci, rar_pci_id_tbl); - -/* field for registering driver to PCI device */ -static struct pci_driver rar_pci_driver = { - .name = "rar_driver", - .id_table = rar_pci_id_tbl, - .probe = rar_probe -}; - -/* This function is used to retrieved RAR info using the IPC message - bus interface */ -static int memrar_get_rar_addr(struct pci_dev *pdev, - int offset, - u32 *addr) -{ - /* - * ======== The Lincroft Message Bus Interface ======== - * Lincroft registers may be obtained from the PCI - * (the Host Bridge) using the Lincroft Message Bus - * Interface. That message bus interface is generally - * comprised of two registers: a control register (MCR, 0xDO) - * and a data register (MDR, 0xD4). - * - * The MCR (message control register) format is the following: - * 1. [31:24]: Opcode - * 2. [23:16]: Port - * 3. [15:8]: Register Offset - * 4. [7:4]: Byte Enables (use 0xF to set all of these bits - * to 1) - * 5. [3:0]: reserved - * - * Read (0xD0) and write (0xE0) opcodes are written to the - * control register when reading and writing to Lincroft - * registers, respectively. - * - * We're interested in registers found in the Lincroft - * B-unit. The B-unit port is 0x3. - * - * The six B-unit RAR register offsets we use are listed - * earlier in this file. - * - * Lastly writing to the MCR register requires the "Byte - * enables" bits to be set to 1. This may be achieved by - * writing 0xF at bit 4. - * - * The MDR (message data register) format is the following: - * 1. [31:0]: Read/Write Data - * - * Data being read from this register is only available after - * writing the appropriate control message to the MCR - * register. - * - * Data being written to this register must be written before - * writing the appropriate control message to the MCR - * register. - */ - - int result = 0; /* result */ - /* Construct control message */ - u32 const message = - (LNC_MESSAGE_READ_OPCODE << 24) - | (LNC_BUNIT_PORT << 16) - | (offset << 8) - | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); - - printk(KERN_WARNING "rar- offset to LNC MSG is %x\n", offset); - - if (addr == 0) - return -EINVAL; - - /* Send the control message */ - result = pci_write_config_dword(pdev, - LNC_MCR_OFFSET, - message); - - printk(KERN_WARNING "rar- result from send ctl register is %x\n", - result); - - if (!result) - result = pci_read_config_dword(pdev, - LNC_MDR_OFFSET, - addr); - - printk(KERN_WARNING "rar- result from read data register is %x\n", - result); - - printk(KERN_WARNING "rar- value read from data register is %x\n", - *addr); - - if (result) - return -1; - else - return 0; -} - -static int memrar_set_rar_addr(struct pci_dev *pdev, - int offset, - u32 addr) -{ - /* - * ======== The Lincroft Message Bus Interface ======== - * Lincroft registers may be obtained from the PCI - * (the Host Bridge) using the Lincroft Message Bus - * Interface. That message bus interface is generally - * comprised of two registers: a control register (MCR, 0xDO) - * and a data register (MDR, 0xD4). - * - * The MCR (message control register) format is the following: - * 1. [31:24]: Opcode - * 2. [23:16]: Port - * 3. [15:8]: Register Offset - * 4. [7:4]: Byte Enables (use 0xF to set all of these bits - * to 1) - * 5. [3:0]: reserved - * - * Read (0xD0) and write (0xE0) opcodes are written to the - * control register when reading and writing to Lincroft - * registers, respectively. - * - * We're interested in registers found in the Lincroft - * B-unit. The B-unit port is 0x3. - * - * The six B-unit RAR register offsets we use are listed - * earlier in this file. - * - * Lastly writing to the MCR register requires the "Byte - * enables" bits to be set to 1. This may be achieved by - * writing 0xF at bit 4. - * - * The MDR (message data register) format is the following: - * 1. [31:0]: Read/Write Data - * - * Data being read from this register is only available after - * writing the appropriate control message to the MCR - * register. - * - * Data being written to this register must be written before - * writing the appropriate control message to the MCR - * register. - */ - - int result = 0; /* result */ - - /* Construct control message */ - u32 const message = - (LNC_MESSAGE_WRITE_OPCODE << 24) - | (LNC_BUNIT_PORT << 16) - | (offset << 8) - | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); - - printk(KERN_WARNING "rar- offset to LNC MSG is %x\n", offset); - - if (addr == 0) - return -EINVAL; - - /* Send the control message */ - result = pci_write_config_dword(pdev, - LNC_MDR_OFFSET, - addr); - - printk(KERN_WARNING "rar- result from send ctl register is %x\n", - result); - - if (!result) - result = pci_write_config_dword(pdev, - LNC_MCR_OFFSET, - message); - - printk(KERN_WARNING "rar- result from write data register is %x\n", - result); - - printk(KERN_WARNING "rar- value read to data register is %x\n", - addr); - - if (result) - return -1; - else - return 0; -} - -/* - - * Initialize RAR parameters, such as physical addresses, etc. - - */ -static int memrar_init_rar_params(struct pci_dev *pdev) -{ - struct RAR_offsets const offsets[] = { - { LNC_BRAR0L, LNC_BRAR0H }, - { LNC_BRAR1L, LNC_BRAR1H }, - { LNC_BRAR2L, LNC_BRAR2H } - }; - - size_t const num_offsets = sizeof(offsets) / sizeof(offsets[0]); - struct RAR_offsets const *end = offsets + num_offsets; - struct RAR_offsets const *i; - unsigned int n = 0; - int result = 0; - - /* Retrieve RAR start and end physical addresses. */ - - /* - * Access the RAR registers through the Lincroft Message Bus - * Interface on PCI device: 00:00.0 Host bridge. - */ - - /* struct pci_dev *pdev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); */ - - if (pdev == NULL) - return -ENODEV; - - for (i = offsets; i != end; ++i, ++n) { - if (memrar_get_rar_addr(pdev, - (*i).low, - &(rar_addr[n].low)) != 0 - || memrar_get_rar_addr(pdev, - (*i).high, - &(rar_addr[n].high)) != 0) { - result = -1; - break; - } - } - - /* Done accessing the device. */ - /* pci_dev_put(pdev); */ - - if (result == 0) { - if (1) { - size_t z; - for (z = 0; z != MRST_NUM_RAR; ++z) { - printk(KERN_WARNING - "rar - BRAR[%Zd] physical address low\n" - "\tlow: 0x%08x\n" - "\thigh: 0x%08x\n", - z, - rar_addr[z].low, - rar_addr[z].high); - } - } - } - - return result; -} - -/* - function that is activated on the successfull probe of the RAR device -*/ -static int __devinit rar_probe(struct pci_dev *pdev, - const struct pci_device_id *ent) -{ - /* error */ - int error; - - /*------------------------ - CODE - ---------------------------*/ - - DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, - "Rar pci probe starting\n"); - error = 0; - - /* enable the device */ - error = pci_enable_device(pdev); - if (error) { - DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, - "error enabling pci device\n"); - goto end_function; - } - - rar_dev = pdev; - registered = 1; - - /* Initialize the RAR parameters, which have to be retrieved */ - /* via the message bus service */ - error = memrar_init_rar_params(rar_dev); - - if (error) { - DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, - "error getting RAR addresses device\n"); - registered = 0; - goto end_function; - } - -end_function: - - return error; -} - -/* - this function registers the driver to - the device subsystem (either PCI, USB, etc) -*/ -static int __init rar_init_handler(void) -{ - return pci_register_driver(&rar_pci_driver); -} - -static void __exit rar_exit_handler(void) -{ - pci_unregister_driver(&rar_pci_driver); -} - -module_init(rar_init_handler); -module_exit(rar_exit_handler); - -MODULE_LICENSE("GPL"); - - -/* The get_rar_address function is used by other device drivers - * to obtain RAR address information on a RAR. It takes two - * parameter: - * - * int rar_index - * The rar_index is an index to the rar for which you wish to retrieve - * the address information. - * Values can be 0,1, or 2. - * - * struct RAR_address_struct is a pointer to a place to which the function - * can return the address structure for the RAR. - * - * The function returns a 0 upon success or a -1 if there is no RAR - * facility on this system. - */ -int get_rar_address(int rar_index, struct RAR_address_struct *addresses) -{ - if (registered && (rar_index < 3) && (rar_index >= 0)) { - *addresses = rar_addr[rar_index]; - /* strip off lock bit information */ - addresses->low = addresses->low & 0xfffffff0; - addresses->high = addresses->high & 0xfffffff0; - return 0; - } else - return -ENODEV; -} -EXPORT_SYMBOL(get_rar_address); - -/* The lock_rar function is used by other device drivers to lock an RAR. - * once an RAR is locked, it stays locked until the next system reboot. - * The function takes one parameter: - * - * int rar_index - * The rar_index is an index to the rar that you want to lock. - * Values can be 0,1, or 2. - * - * The function returns a 0 upon success or a -1 if there is no RAR - * facility on this system. - */ -int lock_rar(int rar_index) -{ - u32 working_addr; - int result; - - if (registered && (rar_index < 3) && (rar_index >= 0)) { - /* first make sure that lock bits are clear (this does lock) */ - working_addr = rar_addr[rar_index].low & 0xfffffff0; - - /* now send that value to the register using the IPC */ - result = memrar_set_rar_addr(rar_dev, rar_index, working_addr); - return result; - } else - return -ENODEV; -} diff --git a/drivers/staging/rar/rar_register.h b/drivers/staging/rar/rar_register.h deleted file mode 100644 index 4172fbf36327..000000000000 --- a/drivers/staging/rar/rar_register.h +++ /dev/null @@ -1,89 +0,0 @@ -/* === RAR Physical Addresses === */ -struct RAR_address_struct { - u32 low; - u32 high; -}; - -/* The get_rar_address function is used by other device drivers - * to obtain RAR address information on a RAR. It takes two - * parameter: - * - * int rar_index - * The rar_index is an index to the rar for which you wish to retrieve - * the address information. - * Values can be 0,1, or 2. - * - * struct RAR_address_struct is a pointer to a place to which the function - * can return the address structure for the RAR. - * - * The function returns a 0 upon success or a -1 if there is no RAR - * facility on this system. - */ -int get_rar_address(int rar_index, struct RAR_address_struct *addresses); - - -/* The lock_rar function is used by other device drivers to lock an RAR. - * once an RAR is locked, it stays locked until the next system reboot. - * The function takes one parameter: - * - * int rar_index - * The rar_index is an index to the rar that you want to lock. - * Values can be 0,1, or 2. - * - * The function returns a 0 upon success or a -1 if there is no RAR - * facility on this system. - */ -int lock_rar(int rar_index); - - -/* DEBUG LEVEL MASKS */ -#define RAR_DEBUG_LEVEL_BASIC 0x1 - -#define RAR_DEBUG_LEVEL_REGISTERS 0x2 - -#define RAR_DEBUG_LEVEL_EXTENDED 0x4 - -#define DEBUG_LEVEL 0x7 - -/* FUNCTIONAL MACROS */ - -/* debug macro without paramaters */ -#define DEBUG_PRINT_0(DEBUG_LEVEL , info) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info); \ - } \ -} while (0) - -/* debug macro with 1 paramater */ -#define DEBUG_PRINT_1(DEBUG_LEVEL , info , param1) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info , param1); \ - } \ -} while (0) - -/* debug macro with 2 paramaters */ -#define DEBUG_PRINT_2(DEBUG_LEVEL , info , param1, param2) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info , param1, param2); \ - } \ -} while (0) - -/* debug macro with 3 paramaters */ -#define DEBUG_PRINT_3(DEBUG_LEVEL , info , param1, param2 , param3) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info , param1, param2 , param3); \ - } \ -} while (0) - -/* debug macro with 4 paramaters */ -#define DEBUG_PRINT_4(DEBUG_LEVEL , info , param1, param2 , param3 , param4) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info , param1, param2 , param3 , param4); \ - } \ -} while (0) - diff --git a/drivers/staging/rar_register/Kconfig b/drivers/staging/rar_register/Kconfig new file mode 100644 index 000000000000..17f8bf3bb41a --- /dev/null +++ b/drivers/staging/rar_register/Kconfig @@ -0,0 +1,17 @@ +# +# RAR device configuration +# + +menu "RAR Register Driver" +# +# Restricted Access Register Manager +# +config RAR_REGISTER + tristate "Restricted Access Region Register Driver" + default n + ---help--- + This driver allows other kernel drivers access to the + contents of the restricted access region control + registers. + +endmenu diff --git a/drivers/staging/rar_register/Makefile b/drivers/staging/rar_register/Makefile new file mode 100644 index 000000000000..d5954ccc16c9 --- /dev/null +++ b/drivers/staging/rar_register/Makefile @@ -0,0 +1,2 @@ +EXTRA_CFLAGS += -DLITTLE__ENDIAN +obj-$(CONFIG_RAR_REGISTER) += rar_register.o diff --git a/drivers/staging/rar_register/rar_register.c b/drivers/staging/rar_register/rar_register.c new file mode 100644 index 000000000000..51eb5a360f1c --- /dev/null +++ b/drivers/staging/rar_register/rar_register.c @@ -0,0 +1,440 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rar_register.h" + +/* The following defines are for the IPC process to retrieve RAR in */ + +/* === Lincroft Message Bus Interface === */ +/* Message Control Register */ +#define LNC_MCR_OFFSET 0xD0 + +/* Message Data Register */ +#define LNC_MDR_OFFSET 0xD4 + +/* Message Opcodes */ +#define LNC_MESSAGE_READ_OPCODE 0xD0 +#define LNC_MESSAGE_WRITE_OPCODE 0xE0 + +/* Message Write Byte Enables */ +#define LNC_MESSAGE_BYTE_WRITE_ENABLES 0xF + +/* B-unit Port */ +#define LNC_BUNIT_PORT 0x3 + +/* === Lincroft B-Unit Registers - Programmed by IA32 firmware === */ +#define LNC_BRAR0L 0x10 +#define LNC_BRAR0H 0x11 +#define LNC_BRAR1L 0x12 +#define LNC_BRAR1H 0x13 + +/* Reserved for SeP */ +#define LNC_BRAR2L 0x14 +#define LNC_BRAR2H 0x15 + + +/* This structure is only used during module initialization. */ +struct RAR_offsets { + int low; /* Register offset for low RAR physical address. */ + int high; /* Register offset for high RAR physical address. */ +}; + +struct pci_dev *rar_dev; +static uint32_t registered; + +/* Moorestown supports three restricted access regions. */ +#define MRST_NUM_RAR 3 + +struct RAR_address_struct rar_addr[MRST_NUM_RAR]; + +/* prototype for init */ +static int __init rar_init_handler(void); +static void __exit rar_exit_handler(void); + +/* + function that is activated on the successfull probe of the RAR device +*/ +static int __devinit rar_probe(struct pci_dev *pdev, + const struct pci_device_id *ent); + +static const struct pci_device_id rar_pci_id_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4110) }, + { 0 } +}; + +MODULE_DEVICE_TABLE(pci, rar_pci_id_tbl); + +/* field for registering driver to PCI device */ +static struct pci_driver rar_pci_driver = { + .name = "rar_driver", + .id_table = rar_pci_id_tbl, + .probe = rar_probe +}; + +/* This function is used to retrieved RAR info using the IPC message + bus interface */ +static int memrar_get_rar_addr(struct pci_dev *pdev, + int offset, + u32 *addr) +{ + /* + * ======== The Lincroft Message Bus Interface ======== + * Lincroft registers may be obtained from the PCI + * (the Host Bridge) using the Lincroft Message Bus + * Interface. That message bus interface is generally + * comprised of two registers: a control register (MCR, 0xDO) + * and a data register (MDR, 0xD4). + * + * The MCR (message control register) format is the following: + * 1. [31:24]: Opcode + * 2. [23:16]: Port + * 3. [15:8]: Register Offset + * 4. [7:4]: Byte Enables (use 0xF to set all of these bits + * to 1) + * 5. [3:0]: reserved + * + * Read (0xD0) and write (0xE0) opcodes are written to the + * control register when reading and writing to Lincroft + * registers, respectively. + * + * We're interested in registers found in the Lincroft + * B-unit. The B-unit port is 0x3. + * + * The six B-unit RAR register offsets we use are listed + * earlier in this file. + * + * Lastly writing to the MCR register requires the "Byte + * enables" bits to be set to 1. This may be achieved by + * writing 0xF at bit 4. + * + * The MDR (message data register) format is the following: + * 1. [31:0]: Read/Write Data + * + * Data being read from this register is only available after + * writing the appropriate control message to the MCR + * register. + * + * Data being written to this register must be written before + * writing the appropriate control message to the MCR + * register. + */ + + int result = 0; /* result */ + /* Construct control message */ + u32 const message = + (LNC_MESSAGE_READ_OPCODE << 24) + | (LNC_BUNIT_PORT << 16) + | (offset << 8) + | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); + + printk(KERN_WARNING "rar- offset to LNC MSG is %x\n", offset); + + if (addr == 0) + return -EINVAL; + + /* Send the control message */ + result = pci_write_config_dword(pdev, + LNC_MCR_OFFSET, + message); + + printk(KERN_WARNING "rar- result from send ctl register is %x\n", + result); + + if (!result) + result = pci_read_config_dword(pdev, + LNC_MDR_OFFSET, + addr); + + printk(KERN_WARNING "rar- result from read data register is %x\n", + result); + + printk(KERN_WARNING "rar- value read from data register is %x\n", + *addr); + + if (result) + return -1; + else + return 0; +} + +static int memrar_set_rar_addr(struct pci_dev *pdev, + int offset, + u32 addr) +{ + /* + * ======== The Lincroft Message Bus Interface ======== + * Lincroft registers may be obtained from the PCI + * (the Host Bridge) using the Lincroft Message Bus + * Interface. That message bus interface is generally + * comprised of two registers: a control register (MCR, 0xDO) + * and a data register (MDR, 0xD4). + * + * The MCR (message control register) format is the following: + * 1. [31:24]: Opcode + * 2. [23:16]: Port + * 3. [15:8]: Register Offset + * 4. [7:4]: Byte Enables (use 0xF to set all of these bits + * to 1) + * 5. [3:0]: reserved + * + * Read (0xD0) and write (0xE0) opcodes are written to the + * control register when reading and writing to Lincroft + * registers, respectively. + * + * We're interested in registers found in the Lincroft + * B-unit. The B-unit port is 0x3. + * + * The six B-unit RAR register offsets we use are listed + * earlier in this file. + * + * Lastly writing to the MCR register requires the "Byte + * enables" bits to be set to 1. This may be achieved by + * writing 0xF at bit 4. + * + * The MDR (message data register) format is the following: + * 1. [31:0]: Read/Write Data + * + * Data being read from this register is only available after + * writing the appropriate control message to the MCR + * register. + * + * Data being written to this register must be written before + * writing the appropriate control message to the MCR + * register. + */ + + int result = 0; /* result */ + + /* Construct control message */ + u32 const message = + (LNC_MESSAGE_WRITE_OPCODE << 24) + | (LNC_BUNIT_PORT << 16) + | (offset << 8) + | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); + + printk(KERN_WARNING "rar- offset to LNC MSG is %x\n", offset); + + if (addr == 0) + return -EINVAL; + + /* Send the control message */ + result = pci_write_config_dword(pdev, + LNC_MDR_OFFSET, + addr); + + printk(KERN_WARNING "rar- result from send ctl register is %x\n", + result); + + if (!result) + result = pci_write_config_dword(pdev, + LNC_MCR_OFFSET, + message); + + printk(KERN_WARNING "rar- result from write data register is %x\n", + result); + + printk(KERN_WARNING "rar- value read to data register is %x\n", + addr); + + if (result) + return -1; + else + return 0; +} + +/* + + * Initialize RAR parameters, such as physical addresses, etc. + + */ +static int memrar_init_rar_params(struct pci_dev *pdev) +{ + struct RAR_offsets const offsets[] = { + { LNC_BRAR0L, LNC_BRAR0H }, + { LNC_BRAR1L, LNC_BRAR1H }, + { LNC_BRAR2L, LNC_BRAR2H } + }; + + size_t const num_offsets = sizeof(offsets) / sizeof(offsets[0]); + struct RAR_offsets const *end = offsets + num_offsets; + struct RAR_offsets const *i; + unsigned int n = 0; + int result = 0; + + /* Retrieve RAR start and end physical addresses. */ + + /* + * Access the RAR registers through the Lincroft Message Bus + * Interface on PCI device: 00:00.0 Host bridge. + */ + + /* struct pci_dev *pdev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); */ + + if (pdev == NULL) + return -ENODEV; + + for (i = offsets; i != end; ++i, ++n) { + if (memrar_get_rar_addr(pdev, + (*i).low, + &(rar_addr[n].low)) != 0 + || memrar_get_rar_addr(pdev, + (*i).high, + &(rar_addr[n].high)) != 0) { + result = -1; + break; + } + } + + /* Done accessing the device. */ + /* pci_dev_put(pdev); */ + + if (result == 0) { + if (1) { + size_t z; + for (z = 0; z != MRST_NUM_RAR; ++z) { + printk(KERN_WARNING + "rar - BRAR[%Zd] physical address low\n" + "\tlow: 0x%08x\n" + "\thigh: 0x%08x\n", + z, + rar_addr[z].low, + rar_addr[z].high); + } + } + } + + return result; +} + +/* + function that is activated on the successfull probe of the RAR device +*/ +static int __devinit rar_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + /* error */ + int error; + + /*------------------------ + CODE + ---------------------------*/ + + DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, + "Rar pci probe starting\n"); + error = 0; + + /* enable the device */ + error = pci_enable_device(pdev); + if (error) { + DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, + "error enabling pci device\n"); + goto end_function; + } + + rar_dev = pdev; + registered = 1; + + /* Initialize the RAR parameters, which have to be retrieved */ + /* via the message bus service */ + error = memrar_init_rar_params(rar_dev); + + if (error) { + DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, + "error getting RAR addresses device\n"); + registered = 0; + goto end_function; + } + +end_function: + + return error; +} + +/* + this function registers the driver to + the device subsystem (either PCI, USB, etc) +*/ +static int __init rar_init_handler(void) +{ + return pci_register_driver(&rar_pci_driver); +} + +static void __exit rar_exit_handler(void) +{ + pci_unregister_driver(&rar_pci_driver); +} + +module_init(rar_init_handler); +module_exit(rar_exit_handler); + +MODULE_LICENSE("GPL"); + + +/* The get_rar_address function is used by other device drivers + * to obtain RAR address information on a RAR. It takes two + * parameter: + * + * int rar_index + * The rar_index is an index to the rar for which you wish to retrieve + * the address information. + * Values can be 0,1, or 2. + * + * struct RAR_address_struct is a pointer to a place to which the function + * can return the address structure for the RAR. + * + * The function returns a 0 upon success or a -1 if there is no RAR + * facility on this system. + */ +int get_rar_address(int rar_index, struct RAR_address_struct *addresses) +{ + if (registered && (rar_index < 3) && (rar_index >= 0)) { + *addresses = rar_addr[rar_index]; + /* strip off lock bit information */ + addresses->low = addresses->low & 0xfffffff0; + addresses->high = addresses->high & 0xfffffff0; + return 0; + } else + return -ENODEV; +} +EXPORT_SYMBOL(get_rar_address); + +/* The lock_rar function is used by other device drivers to lock an RAR. + * once an RAR is locked, it stays locked until the next system reboot. + * The function takes one parameter: + * + * int rar_index + * The rar_index is an index to the rar that you want to lock. + * Values can be 0,1, or 2. + * + * The function returns a 0 upon success or a -1 if there is no RAR + * facility on this system. + */ +int lock_rar(int rar_index) +{ + u32 working_addr; + int result; + + if (registered && (rar_index < 3) && (rar_index >= 0)) { + /* first make sure that lock bits are clear (this does lock) */ + working_addr = rar_addr[rar_index].low & 0xfffffff0; + + /* now send that value to the register using the IPC */ + result = memrar_set_rar_addr(rar_dev, rar_index, working_addr); + return result; + } else + return -ENODEV; +} diff --git a/drivers/staging/rar_register/rar_register.h b/drivers/staging/rar_register/rar_register.h new file mode 100644 index 000000000000..4172fbf36327 --- /dev/null +++ b/drivers/staging/rar_register/rar_register.h @@ -0,0 +1,89 @@ +/* === RAR Physical Addresses === */ +struct RAR_address_struct { + u32 low; + u32 high; +}; + +/* The get_rar_address function is used by other device drivers + * to obtain RAR address information on a RAR. It takes two + * parameter: + * + * int rar_index + * The rar_index is an index to the rar for which you wish to retrieve + * the address information. + * Values can be 0,1, or 2. + * + * struct RAR_address_struct is a pointer to a place to which the function + * can return the address structure for the RAR. + * + * The function returns a 0 upon success or a -1 if there is no RAR + * facility on this system. + */ +int get_rar_address(int rar_index, struct RAR_address_struct *addresses); + + +/* The lock_rar function is used by other device drivers to lock an RAR. + * once an RAR is locked, it stays locked until the next system reboot. + * The function takes one parameter: + * + * int rar_index + * The rar_index is an index to the rar that you want to lock. + * Values can be 0,1, or 2. + * + * The function returns a 0 upon success or a -1 if there is no RAR + * facility on this system. + */ +int lock_rar(int rar_index); + + +/* DEBUG LEVEL MASKS */ +#define RAR_DEBUG_LEVEL_BASIC 0x1 + +#define RAR_DEBUG_LEVEL_REGISTERS 0x2 + +#define RAR_DEBUG_LEVEL_EXTENDED 0x4 + +#define DEBUG_LEVEL 0x7 + +/* FUNCTIONAL MACROS */ + +/* debug macro without paramaters */ +#define DEBUG_PRINT_0(DEBUG_LEVEL , info) \ +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info); \ + } \ +} while (0) + +/* debug macro with 1 paramater */ +#define DEBUG_PRINT_1(DEBUG_LEVEL , info , param1) \ +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info , param1); \ + } \ +} while (0) + +/* debug macro with 2 paramaters */ +#define DEBUG_PRINT_2(DEBUG_LEVEL , info , param1, param2) \ +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info , param1, param2); \ + } \ +} while (0) + +/* debug macro with 3 paramaters */ +#define DEBUG_PRINT_3(DEBUG_LEVEL , info , param1, param2 , param3) \ +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info , param1, param2 , param3); \ + } \ +} while (0) + +/* debug macro with 4 paramaters */ +#define DEBUG_PRINT_4(DEBUG_LEVEL , info , param1, param2 , param3 , param4) \ +do { \ + if (DEBUG_LEVEL) { \ + printk(KERN_WARNING info , param1, param2 , param3 , param4); \ + } \ +} while (0) + -- cgit v1.2.3 From bafb6f63af819269c23871ba9ca8d9eb3f6893cc Mon Sep 17 00:00:00 2001 From: Mark Allyn Date: Fri, 5 Feb 2010 10:52:46 -0800 Subject: Staging: rar_register: provide better explanation in Kconfig Provides a better explanation of what this driver is for in the Kconfig file Signed-off-by: Mark Allyn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rar_register/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/rar_register/Kconfig b/drivers/staging/rar_register/Kconfig index 17f8bf3bb41a..3f73839643e9 100644 --- a/drivers/staging/rar_register/Kconfig +++ b/drivers/staging/rar_register/Kconfig @@ -14,4 +14,17 @@ config RAR_REGISTER contents of the restricted access region control registers. + The restricted access region control registers + (rar_registers) are used to pass address and + locking information on restricted access regions + to other drivers that use restricted access regions + + The restricted access regions are regions of memory + on the Intel MID Platform that are not accessible to + the x86 processor, but are accessible to dedicated + processors on board peripheral devices. + + The purpose of the restricted access regions is to + protect sensitive data from compromise by unauthorized + programs running on the x86 processor. endmenu -- cgit v1.2.3 From 9cedb3924bfa3f70d0c562c65e26ce824c686fc4 Mon Sep 17 00:00:00 2001 From: Mark Allyn Date: Fri, 5 Feb 2010 10:53:00 -0800 Subject: Staging: rar_register: fix checkpatch errors and debug header file Signed-off-by: Mark Allyn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rar_register/rar_register.h | 115 +++++++++++++--------------- 1 file changed, 55 insertions(+), 60 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rar_register/rar_register.h b/drivers/staging/rar_register/rar_register.h index 4172fbf36327..29ade0f361d2 100644 --- a/drivers/staging/rar_register/rar_register.h +++ b/drivers/staging/rar_register/rar_register.h @@ -1,9 +1,53 @@ -/* === RAR Physical Addresses === */ -struct RAR_address_struct { - u32 low; - u32 high; +/* + * Copyright (C) 2010 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of version 2 of the GNU General + * Public License as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + * PURPOSE. See the GNU General Public License for more details. + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + * The full GNU General Public License is included in this + * distribution in the file called COPYING. + */ + + +#ifndef _RAR_REGISTER_H +#define _RAR_REGISTER_H + +# include + +/* following are used both in drivers as well as user space apps */ +enum RAR_type { + RAR_TYPE_VIDEO = 0, + RAR_TYPE_AUDIO, + RAR_TYPE_IMAGE, + RAR_TYPE_DATA }; +#ifdef __KERNEL__ + +/* PCI device id for controller */ +#define PCI_RAR_DEVICE_ID 0x4110 + +/* The register_rar function is to used by other device drivers + * to ensure that this driver is ready. As we cannot be sure of + * the compile/execute order of dirvers in ther kernel, it is + * best to give this driver a callback function to call when + * it is ready to give out addresses. The callback function + * would have those steps that continue the initialization of + * a driver that do require a valid RAR address. One of those + * steps would be to call get_rar_address() + * This function return 0 on success an -1 on failure. + */ +int register_rar(int (*callback)(void *yourparameter), void *yourparameter); + /* The get_rar_address function is used by other device drivers * to obtain RAR address information on a RAR. It takes two * parameter: @@ -19,10 +63,11 @@ struct RAR_address_struct { * The function returns a 0 upon success or a -1 if there is no RAR * facility on this system. */ -int get_rar_address(int rar_index, struct RAR_address_struct *addresses); - +int rar_get_address(int rar_index, + dma_addr_t *start_address, + dma_addr_t *end_address); -/* The lock_rar function is used by other device drivers to lock an RAR. +/* The lock_rar function is ued by other device drivers to lock an RAR. * once an RAR is locked, it stays locked until the next system reboot. * The function takes one parameter: * @@ -33,57 +78,7 @@ int get_rar_address(int rar_index, struct RAR_address_struct *addresses); * The function returns a 0 upon success or a -1 if there is no RAR * facility on this system. */ -int lock_rar(int rar_index); - - -/* DEBUG LEVEL MASKS */ -#define RAR_DEBUG_LEVEL_BASIC 0x1 - -#define RAR_DEBUG_LEVEL_REGISTERS 0x2 - -#define RAR_DEBUG_LEVEL_EXTENDED 0x4 - -#define DEBUG_LEVEL 0x7 - -/* FUNCTIONAL MACROS */ - -/* debug macro without paramaters */ -#define DEBUG_PRINT_0(DEBUG_LEVEL , info) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info); \ - } \ -} while (0) - -/* debug macro with 1 paramater */ -#define DEBUG_PRINT_1(DEBUG_LEVEL , info , param1) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info , param1); \ - } \ -} while (0) - -/* debug macro with 2 paramaters */ -#define DEBUG_PRINT_2(DEBUG_LEVEL , info , param1, param2) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info , param1, param2); \ - } \ -} while (0) - -/* debug macro with 3 paramaters */ -#define DEBUG_PRINT_3(DEBUG_LEVEL , info , param1, param2 , param3) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info , param1, param2 , param3); \ - } \ -} while (0) - -/* debug macro with 4 paramaters */ -#define DEBUG_PRINT_4(DEBUG_LEVEL , info , param1, param2 , param3 , param4) \ -do { \ - if (DEBUG_LEVEL) { \ - printk(KERN_WARNING info , param1, param2 , param3 , param4); \ - } \ -} while (0) +int rar_lock(int rar_index); +#endif /* __KERNEL__ */ +#endif /* _RAR_REGISTER_H */ -- cgit v1.2.3 From 433e63c63eee9fd8ac3735ce5b41797f30d5ce58 Mon Sep 17 00:00:00 2001 From: Mark Allyn Date: Fri, 5 Feb 2010 10:53:18 -0800 Subject: Staging: rar_register: fix checkpatch errors and debug program file Signed-off-by: Mark Allyn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rar_register/rar_register.c | 728 +++++++++++++++++----------- 1 file changed, 445 insertions(+), 283 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rar_register/rar_register.c b/drivers/staging/rar_register/rar_register.c index 51eb5a360f1c..c9dcc9916b70 100644 --- a/drivers/staging/rar_register/rar_register.c +++ b/drivers/staging/rar_register/rar_register.c @@ -1,33 +1,67 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +/* + * rar_register.c - An Intel Restricted Access Region register driver + * + * Copyright(c) 2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + * 02111-1307, USA. + * + * ------------------------------------------------------------------- + * 20091204 Mark Allyn + * Ossama Othman + * Cleanup per feedback from Alan Cox and Arjan Van De Ven + * + * 20090806 Ossama Othman + * Return zero high address if upper 22 bits is zero. + * Cleaned up checkpatch errors. + * Clarified that driver is dealing with bus addresses. + * + * 20090702 Ossama Othman + * Removed unnecessary include directives + * Cleaned up spinlocks. + * Cleaned up logging. + * Improved invalid parameter checks. + * Fixed and simplified RAR address retrieval and RAR locking + * code. + * + * 20090626 Mark Allyn + * Initial publish + */ + +#define DEBUG 1 + #include "rar_register.h" -/* The following defines are for the IPC process to retrieve RAR in */ +#include +#include +#include +#include +#include /* === Lincroft Message Bus Interface === */ /* Message Control Register */ #define LNC_MCR_OFFSET 0xD0 +/* Maximum number of clients (other drivers using this driver) */ +#define MAX_RAR_CLIENTS 10 + /* Message Data Register */ #define LNC_MDR_OFFSET 0xD4 /* Message Opcodes */ -#define LNC_MESSAGE_READ_OPCODE 0xD0 +#define LNC_MESSAGE_READ_OPCODE 0xD0 #define LNC_MESSAGE_WRITE_OPCODE 0xE0 /* Message Write Byte Enables */ @@ -37,59 +71,73 @@ #define LNC_BUNIT_PORT 0x3 /* === Lincroft B-Unit Registers - Programmed by IA32 firmware === */ -#define LNC_BRAR0L 0x10 -#define LNC_BRAR0H 0x11 -#define LNC_BRAR1L 0x12 -#define LNC_BRAR1H 0x13 +#define LNC_BRAR0L 0x10 +#define LNC_BRAR0H 0x11 +#define LNC_BRAR1L 0x12 +#define LNC_BRAR1H 0x13 /* Reserved for SeP */ -#define LNC_BRAR2L 0x14 -#define LNC_BRAR2H 0x15 +#define LNC_BRAR2L 0x14 +#define LNC_BRAR2H 0x15 +/* Moorestown supports three restricted access regions. */ +#define MRST_NUM_RAR 3 -/* This structure is only used during module initialization. */ -struct RAR_offsets { - int low; /* Register offset for low RAR physical address. */ - int high; /* Register offset for high RAR physical address. */ -}; -struct pci_dev *rar_dev; -static uint32_t registered; +/* RAR Bus Address Range */ +struct RAR_address_range { + dma_addr_t low; + dma_addr_t high; +}; -/* Moorestown supports three restricted access regions. */ -#define MRST_NUM_RAR 3 +/* Structure containing low and high RAR register offsets. */ +struct RAR_offsets { + u32 low; /* Register offset for low RAR bus address. */ + u32 high; /* Register offset for high RAR bus address. */ +}; -struct RAR_address_struct rar_addr[MRST_NUM_RAR]; +struct client { + int (*client_callback)(void *client_data); + void *customer_data; + int client_called; + }; -/* prototype for init */ -static int __init rar_init_handler(void); -static void __exit rar_exit_handler(void); +static DEFINE_MUTEX(rar_mutex); +static DEFINE_MUTEX(lnc_reg_mutex); -/* - function that is activated on the successfull probe of the RAR device -*/ -static int __devinit rar_probe(struct pci_dev *pdev, - const struct pci_device_id *ent); +struct RAR_device { + struct RAR_offsets const rar_offsets[MRST_NUM_RAR]; + struct RAR_address_range rar_addr[MRST_NUM_RAR]; + struct pci_dev *rar_dev; + bool registered; + }; -static const struct pci_device_id rar_pci_id_tbl[] = { - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4110) }, - { 0 } +/* this platform has only one rar_device for 3 rar regions */ +static struct RAR_device my_rar_device = { + .rar_offsets = { + [0].low = LNC_BRAR0L, + [0].high = LNC_BRAR0H, + [1].low = LNC_BRAR1L, + [1].high = LNC_BRAR1H, + [2].low = LNC_BRAR2L, + [2].high = LNC_BRAR2H + } }; -MODULE_DEVICE_TABLE(pci, rar_pci_id_tbl); +/* this data is for handling requests from other drivers which arrive + * prior to this driver initializing + */ -/* field for registering driver to PCI device */ -static struct pci_driver rar_pci_driver = { - .name = "rar_driver", - .id_table = rar_pci_id_tbl, - .probe = rar_probe -}; +static struct client clients[MAX_RAR_CLIENTS]; +static int num_clients; -/* This function is used to retrieved RAR info using the IPC message - bus interface */ -static int memrar_get_rar_addr(struct pci_dev *pdev, - int offset, - u32 *addr) +/* + * This function is used to retrieved RAR info using the Lincroft + * message bus interface. + */ +static int retrieve_rar_addr(struct pci_dev *pdev, + int offset, + dma_addr_t *addr) { /* * ======== The Lincroft Message Bus Interface ======== @@ -131,243 +179,412 @@ static int memrar_get_rar_addr(struct pci_dev *pdev, * Data being written to this register must be written before * writing the appropriate control message to the MCR * register. - */ + */ + + int result; - int result = 0; /* result */ /* Construct control message */ u32 const message = - (LNC_MESSAGE_READ_OPCODE << 24) - | (LNC_BUNIT_PORT << 16) - | (offset << 8) - | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); + (LNC_MESSAGE_READ_OPCODE << 24) + | (LNC_BUNIT_PORT << 16) + | (offset << 8) + | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); - printk(KERN_WARNING "rar- offset to LNC MSG is %x\n", offset); + dev_dbg(&pdev->dev, "Offset for 'get' LNC MSG is %x\n", offset); - if (addr == 0) + if (addr == 0) { + WARN_ON(1); return -EINVAL; + } + + /* + * We synchronize access to the Lincroft MCR and MDR registers + * until BOTH the command is issued through the MCR register + * and the corresponding data is read from the MDR register. + * Otherwise a race condition would exist between accesses to + * both registers. + */ + + mutex_lock(&lnc_reg_mutex); /* Send the control message */ - result = pci_write_config_dword(pdev, - LNC_MCR_OFFSET, - message); + result = pci_write_config_dword(pdev, LNC_MCR_OFFSET, message); - printk(KERN_WARNING "rar- result from send ctl register is %x\n", - result); + dev_dbg(&pdev->dev, "Result from send ctl register is %x\n", result); - if (!result) - result = pci_read_config_dword(pdev, - LNC_MDR_OFFSET, - addr); + if (!result) { + result = pci_read_config_dword(pdev, LNC_MDR_OFFSET, + (u32 *)addr); + dev_dbg(&pdev->dev, + "Result from read data register is %x\n", result); - printk(KERN_WARNING "rar- result from read data register is %x\n", - result); + dev_dbg(&pdev->dev, + "Value read from data register is %lx\n", + (unsigned long)*addr); + } - printk(KERN_WARNING "rar- value read from data register is %x\n", - *addr); + mutex_unlock(&lnc_reg_mutex); - if (result) - return -1; - else - return 0; + return result; } -static int memrar_set_rar_addr(struct pci_dev *pdev, - int offset, - u32 addr) +static int set_rar_address(struct pci_dev *pdev, + int offset, + dma_addr_t addr) { /* - * ======== The Lincroft Message Bus Interface ======== - * Lincroft registers may be obtained from the PCI - * (the Host Bridge) using the Lincroft Message Bus - * Interface. That message bus interface is generally - * comprised of two registers: a control register (MCR, 0xDO) - * and a data register (MDR, 0xD4). - * - * The MCR (message control register) format is the following: - * 1. [31:24]: Opcode - * 2. [23:16]: Port - * 3. [15:8]: Register Offset - * 4. [7:4]: Byte Enables (use 0xF to set all of these bits - * to 1) - * 5. [3:0]: reserved - * - * Read (0xD0) and write (0xE0) opcodes are written to the - * control register when reading and writing to Lincroft - * registers, respectively. - * - * We're interested in registers found in the Lincroft - * B-unit. The B-unit port is 0x3. - * - * The six B-unit RAR register offsets we use are listed - * earlier in this file. - * - * Lastly writing to the MCR register requires the "Byte - * enables" bits to be set to 1. This may be achieved by - * writing 0xF at bit 4. - * - * The MDR (message data register) format is the following: - * 1. [31:0]: Read/Write Data - * - * Data being read from this register is only available after - * writing the appropriate control message to the MCR - * register. - * - * Data being written to this register must be written before - * writing the appropriate control message to the MCR - * register. - */ + * Data being written to this register must be written before + * writing the appropriate control message to the MCR + * register. + * @note See rar_get_address() for a description of the + * message bus interface being used here. + */ - int result = 0; /* result */ + int result = 0; /* Construct control message */ - u32 const message = - (LNC_MESSAGE_WRITE_OPCODE << 24) - | (LNC_BUNIT_PORT << 16) - | (offset << 8) - | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); - - printk(KERN_WARNING "rar- offset to LNC MSG is %x\n", offset); + u32 const message = (LNC_MESSAGE_WRITE_OPCODE << 24) + | (LNC_BUNIT_PORT << 16) + | (offset << 8) + | (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4); - if (addr == 0) + if (addr == 0) { + WARN_ON(1); return -EINVAL; + } + + dev_dbg(&pdev->dev, "Offset for 'set' LNC MSG is %x\n", offset); + + /* + * We synchronize access to the Lincroft MCR and MDR registers + * until BOTH the command is issued through the MCR register + * and the corresponding data is read from the MDR register. + * Otherwise a race condition would exist between accesses to + * both registers. + */ + + mutex_lock(&lnc_reg_mutex); /* Send the control message */ - result = pci_write_config_dword(pdev, - LNC_MDR_OFFSET, - addr); + result = pci_write_config_dword(pdev, LNC_MDR_OFFSET, addr); - printk(KERN_WARNING "rar- result from send ctl register is %x\n", - result); + dev_dbg(&pdev->dev, "Result from write data register is %x\n", result); - if (!result) - result = pci_write_config_dword(pdev, - LNC_MCR_OFFSET, - message); + if (!result) { + dev_dbg(&pdev->dev, + "Value written to data register is %lx\n", + (unsigned long)addr); - printk(KERN_WARNING "rar- result from write data register is %x\n", - result); + result = pci_write_config_dword(pdev, LNC_MCR_OFFSET, message); + + dev_dbg(&pdev->dev, "Result from send ctl register is %x\n", + result); + } - printk(KERN_WARNING "rar- value read to data register is %x\n", - addr); + mutex_unlock(&lnc_reg_mutex); - if (result) - return -1; - else - return 0; + return result; } /* - - * Initialize RAR parameters, such as physical addresses, etc. - - */ -static int memrar_init_rar_params(struct pci_dev *pdev) +* Initialize RAR parameters, such as bus addresses, etc. +*/ +static int init_rar_params(struct pci_dev *pdev) { - struct RAR_offsets const offsets[] = { - { LNC_BRAR0L, LNC_BRAR0H }, - { LNC_BRAR1L, LNC_BRAR1H }, - { LNC_BRAR2L, LNC_BRAR2H } - }; - - size_t const num_offsets = sizeof(offsets) / sizeof(offsets[0]); - struct RAR_offsets const *end = offsets + num_offsets; - struct RAR_offsets const *i; - unsigned int n = 0; + unsigned int i; int result = 0; - /* Retrieve RAR start and end physical addresses. */ + /* Retrieve RAR start and end bus addresses. + * Access the RAR registers through the Lincroft Message Bus + * Interface on PCI device: 00:00.0 Host bridge. + */ - /* - * Access the RAR registers through the Lincroft Message Bus - * Interface on PCI device: 00:00.0 Host bridge. - */ - - /* struct pci_dev *pdev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); */ - - if (pdev == NULL) - return -ENODEV; - - for (i = offsets; i != end; ++i, ++n) { - if (memrar_get_rar_addr(pdev, - (*i).low, - &(rar_addr[n].low)) != 0 - || memrar_get_rar_addr(pdev, - (*i).high, - &(rar_addr[n].high)) != 0) { - result = -1; - break; + for (i = 0; i < MRST_NUM_RAR; ++i) { + struct RAR_offsets const *offset = + &my_rar_device.rar_offsets[i]; + struct RAR_address_range *addr = &my_rar_device.rar_addr[i]; + + if ((retrieve_rar_addr(pdev, offset->low, &addr->low) != 0) + || (retrieve_rar_addr(pdev, offset->high, &addr->high) != 0)) { + result = -1; + break; } - } + /* + * Only the upper 22 bits of the RAR addresses are + * stored in their corresponding RAR registers so we + * must set the lower 10 bits accordingly. + + * The low address has its lower 10 bits cleared, and + * the high address has all its lower 10 bits set, + * e.g.: + * low = 0x2ffffc00 + */ + + addr->low &= (dma_addr_t)0xfffffc00u; + + /* + * Set bits 9:0 on uppser address if bits 31:10 are non + * zero; otherwize clear all bits + */ + + if ((addr->high & 0xfffffc00u) == 0) + addr->high = 0; + else + addr->high |= 0x3ffu; + } /* Done accessing the device. */ - /* pci_dev_put(pdev); */ if (result == 0) { - if (1) { - size_t z; - for (z = 0; z != MRST_NUM_RAR; ++z) { - printk(KERN_WARNING - "rar - BRAR[%Zd] physical address low\n" - "\tlow: 0x%08x\n" - "\thigh: 0x%08x\n", - z, - rar_addr[z].low, - rar_addr[z].high); - } + int z; + for (z = 0; z != MRST_NUM_RAR; ++z) { + /* + * "BRAR" refers to the RAR registers in the + * Lincroft B-unit. + */ + dev_info(&pdev->dev, "BRAR[%u] bus address range = " + "[%lx, %lx]\n", z, + (unsigned long)my_rar_device.rar_addr[z].low, + (unsigned long)my_rar_device.rar_addr[z].high); + } + } + + return result; +} + +/* + * The rar_get_address function is used by other device drivers + * to obtain RAR address information on a RAR. It takes three + * parameters: + * + * int rar_index + * The rar_index is an index to the rar for which you wish to retrieve + * the address information. + * Values can be 0,1, or 2. + * + * The function returns a 0 upon success or a -1 if there is no RAR + * facility on this system. + */ +int rar_get_address(int rar_index, + dma_addr_t *start_address, + dma_addr_t *end_address) +{ + int result = -ENODEV; + + if (my_rar_device.registered) { + if (start_address == 0 || end_address == 0 + || rar_index >= MRST_NUM_RAR || rar_index < 0) { + result = -EINVAL; + } else { + *start_address = + my_rar_device.rar_addr[rar_index].low; + *end_address = + my_rar_device.rar_addr[rar_index].high; + + result = 0; } } return result; } +EXPORT_SYMBOL(rar_get_address); /* - function that is activated on the successfull probe of the RAR device + * The rar_lock function is ued by other device drivers to lock an RAR. + * once an RAR is locked, it stays locked until the next system reboot. + * The function takes one parameter: + * + * int rar_index + * The rar_index is an index to the rar that you want to lock. + * Values can be 0,1, or 2. + * + * The function returns a 0 upon success or a -1 if there is no RAR + * facility on this system. + */ +int rar_lock(int rar_index) +{ + int result = -ENODEV; + + if (rar_index >= MRST_NUM_RAR || rar_index < 0) { + result = -EINVAL; + return result; + } + + dev_dbg(&my_rar_device.rar_dev->dev, "rar_lock mutex locking\n"); + mutex_lock(&rar_mutex); + + if (my_rar_device.registered) { + + dma_addr_t low = my_rar_device.rar_addr[rar_index].low & + 0xfffffc00u; + + dma_addr_t high = my_rar_device.rar_addr[rar_index].high & + 0xfffffc00u; + + /* + * Only allow I/O from the graphics and Langwell; + * Not from the x96 processor + */ + if (rar_index == (int)RAR_TYPE_VIDEO) { + low |= 0x00000009; + high |= 0x00000015; + } + + else if (rar_index == (int)RAR_TYPE_AUDIO) { + /* Only allow I/O from Langwell; nothing from x86 */ + low |= 0x00000008; + high |= 0x00000018; + } + + else + /* Read-only from all agents */ + high |= 0x00000018; + + /* + * Now program the register using the Lincroft message + * bus interface. + */ + result = set_rar_address(my_rar_device.rar_dev, + my_rar_device.rar_offsets[rar_index].low, + low); + + if (result == 0) + result = set_rar_address( + my_rar_device.rar_dev, + my_rar_device.rar_offsets[rar_index].high, + high); + } + + dev_dbg(&my_rar_device.rar_dev->dev, "rar_lock mutex unlocking\n"); + mutex_unlock(&rar_mutex); + return result; +} +EXPORT_SYMBOL(rar_lock); + +/* The register_rar function is to used by other device drivers + * to ensure that this driver is ready. As we cannot be sure of + * the compile/execute order of dirvers in ther kernel, it is + * best to give this driver a callback function to call when + * it is ready to give out addresses. The callback function + * would have those steps that continue the initialization of + * a driver that do require a valid RAR address. One of those + * steps would be to call rar_get_address() + * This function return 0 on success an -1 on failure. */ -static int __devinit rar_probe(struct pci_dev *pdev, - const struct pci_device_id *ent) +int register_rar(int (*callback)(void *yourparameter), void *yourparameter) { - /* error */ - int error; - /*------------------------ - CODE - ---------------------------*/ + int result = -ENODEV; - DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, - "Rar pci probe starting\n"); - error = 0; + if (callback == NULL) + return -EINVAL; + + mutex_lock(&rar_mutex); + + if (my_rar_device.registered) { + + mutex_unlock(&rar_mutex); + /* + * if the driver already registered, then we can simply + * call the callback right now + */ + + return (*callback)(yourparameter); + } + + if (num_clients < MRST_NUM_RAR) { + + clients[num_clients].client_callback = callback; + clients[num_clients].customer_data = yourparameter; + num_clients += 1; + result = 0; + } + + mutex_unlock(&rar_mutex); + return result; + +} +EXPORT_SYMBOL(register_rar); + +/* + * This function registers the driver with the device subsystem ( + * either PCI, USB, etc). + * Function that is activaed on the succesful probe of the RAR device + * (Moorestown host controller). + */ +static int rar_probe(struct pci_dev *dev, const struct pci_device_id *id) +{ + int error; + int counter; + + dev_dbg(&dev->dev, "PCI probe starting\n"); /* enable the device */ - error = pci_enable_device(pdev); + error = pci_enable_device(dev); if (error) { - DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, - "error enabling pci device\n"); + dev_err(&dev->dev, + "Error enabling RAR register PCI device\n"); goto end_function; } - rar_dev = pdev; - registered = 1; - - /* Initialize the RAR parameters, which have to be retrieved */ - /* via the message bus service */ - error = memrar_init_rar_params(rar_dev); + /* we have only one device; fill in the rar_device structure */ + my_rar_device.rar_dev = dev; + /* + * Initialize the RAR parameters, which have to be retrieved + * via the message bus interface. + */ + error = init_rar_params(dev); if (error) { - DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED, - "error getting RAR addresses device\n"); - registered = 0; + pci_disable_device(dev); + + dev_err(&dev->dev, + "Error retrieving RAR addresses\n"); + goto end_function; + } + + dev_dbg(&dev->dev, "PCI probe locking\n"); + mutex_lock(&rar_mutex); + my_rar_device.registered = 1; + + /* now call anyone who has registered (using callbacks) */ + for (counter = 0; counter < num_clients; counter += 1) { + if (clients[counter].client_callback) { + error = (*clients[counter].client_callback)( + clients[counter].customer_data); + /* set callback to NULL to indicate it has been done */ + clients[counter].client_callback = NULL; + dev_dbg(&my_rar_device.rar_dev->dev, + "Callback called for %d\n", + counter); } + } + + dev_dbg(&dev->dev, "PCI probe unlocking\n"); + mutex_unlock(&rar_mutex); end_function: return error; } -/* - this function registers the driver to - the device subsystem (either PCI, USB, etc) -*/ +const struct pci_device_id rar_pci_id_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_RAR_DEVICE_ID) }, + { 0 } +}; + +MODULE_DEVICE_TABLE(pci, rar_pci_id_tbl); + +const struct pci_device_id *my_id_table = rar_pci_id_tbl; + +/* field for registering driver to PCI device */ +static struct pci_driver rar_pci_driver = { + .name = "rar_register_driver", + .id_table = rar_pci_id_tbl, + .probe = rar_probe +}; + static int __init rar_init_handler(void) { return pci_register_driver(&rar_pci_driver); @@ -382,59 +599,4 @@ module_init(rar_init_handler); module_exit(rar_exit_handler); MODULE_LICENSE("GPL"); - - -/* The get_rar_address function is used by other device drivers - * to obtain RAR address information on a RAR. It takes two - * parameter: - * - * int rar_index - * The rar_index is an index to the rar for which you wish to retrieve - * the address information. - * Values can be 0,1, or 2. - * - * struct RAR_address_struct is a pointer to a place to which the function - * can return the address structure for the RAR. - * - * The function returns a 0 upon success or a -1 if there is no RAR - * facility on this system. - */ -int get_rar_address(int rar_index, struct RAR_address_struct *addresses) -{ - if (registered && (rar_index < 3) && (rar_index >= 0)) { - *addresses = rar_addr[rar_index]; - /* strip off lock bit information */ - addresses->low = addresses->low & 0xfffffff0; - addresses->high = addresses->high & 0xfffffff0; - return 0; - } else - return -ENODEV; -} -EXPORT_SYMBOL(get_rar_address); - -/* The lock_rar function is used by other device drivers to lock an RAR. - * once an RAR is locked, it stays locked until the next system reboot. - * The function takes one parameter: - * - * int rar_index - * The rar_index is an index to the rar that you want to lock. - * Values can be 0,1, or 2. - * - * The function returns a 0 upon success or a -1 if there is no RAR - * facility on this system. - */ -int lock_rar(int rar_index) -{ - u32 working_addr; - int result; - - if (registered && (rar_index < 3) && (rar_index >= 0)) { - /* first make sure that lock bits are clear (this does lock) */ - working_addr = rar_addr[rar_index].low & 0xfffffff0; - - /* now send that value to the register using the IPC */ - result = memrar_set_rar_addr(rar_dev, rar_index, working_addr); - return result; - } else - return -ENODEV; -} +MODULE_DESCRIPTION("Intel Restricted Access Region Register Driver"); -- cgit v1.2.3 From 3913add413ab95b1e33738b44e9a2118afb11346 Mon Sep 17 00:00:00 2001 From: Mark Allyn Date: Fri, 5 Feb 2010 10:53:34 -0800 Subject: Staging: rar_register: add suspend and resume functions Add suspend and resume functions (which are currently stubs returning -ENOSYS) Signed-off-by: Mark Allyn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rar_register/rar_register.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/rar_register/rar_register.c b/drivers/staging/rar_register/rar_register.c index c9dcc9916b70..bfc0e31f1a6f 100644 --- a/drivers/staging/rar_register/rar_register.c +++ b/drivers/staging/rar_register/rar_register.c @@ -506,6 +506,17 @@ int register_rar(int (*callback)(void *yourparameter), void *yourparameter) } EXPORT_SYMBOL(register_rar); +/* Suspend - returns -ENOSYS */ +static int rar_suspend(struct pci_dev *dev, pm_message_t state) +{ + return -ENOSYS; +} + +static int rar_resume(struct pci_dev *dev) +{ + return -ENOSYS; +} + /* * This function registers the driver with the device subsystem ( * either PCI, USB, etc). @@ -582,7 +593,9 @@ const struct pci_device_id *my_id_table = rar_pci_id_tbl; static struct pci_driver rar_pci_driver = { .name = "rar_register_driver", .id_table = rar_pci_id_tbl, - .probe = rar_probe + .probe = rar_probe, + .suspend = rar_suspend, + .resume = rar_resume }; static int __init rar_init_handler(void) -- cgit v1.2.3 From 326bdc6537d3f18d894745a344c44c9c34777014 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Sat, 6 Feb 2010 15:12:32 +0100 Subject: Staging: comedi: rti800: more Checkpatch cleanups This fixes all checkpatch issues in the rti800 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/rti800.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/rti800.c b/drivers/staging/comedi/drivers/rti800.c index f2ee5289dbf1..028ed6f89c4c 100644 --- a/drivers/staging/comedi/drivers/rti800.c +++ b/drivers/staging/comedi/drivers/rti800.c @@ -225,7 +225,7 @@ static int rti800_ai_insn_read(struct comedi_device *dev, for (t = RTI800_TIMEOUT; t; t--) { status = inb(dev->iobase + RTI800_CSR); if (status & RTI800_OVERRUN) { - printk("rti800: a/d overrun\n"); + printk(KERN_WARNING "rti800: a/d overrun\n"); outb(0, dev->iobase + RTI800_CLRFLAGS); return -EIO; } @@ -234,7 +234,7 @@ static int rti800_ai_insn_read(struct comedi_device *dev, udelay(1); } if (t == 0) { - printk("rti800: timeout\n"); + printk(KERN_WARNING "rti800: timeout\n"); return -ETIME; } data[i] = inb(dev->iobase + RTI800_ADCLO); @@ -335,15 +335,15 @@ static int rti800_attach(struct comedi_device *dev, struct comedi_devconfig *it) struct comedi_subdevice *s; iobase = it->options[0]; - printk("comedi%d: rti800: 0x%04lx ", dev->minor, iobase); + printk(KERN_INFO "comedi%d: rti800: 0x%04lx\n", dev->minor, iobase); if (!request_region(iobase, RTI800_SIZE, "rti800")) { - printk("I/O port conflict\n"); + printk(KERN_WARNING "I/O port conflict\n"); return -EIO; } dev->iobase = iobase; #ifdef DEBUG - printk("fingerprint=%x,%x,%x,%x,%x ", + printk(KERN_DEBUG "fingerprint=%x,%x,%x,%x,%x ", inb(dev->iobase + 0), inb(dev->iobase + 1), inb(dev->iobase + 2), @@ -356,15 +356,15 @@ static int rti800_attach(struct comedi_device *dev, struct comedi_devconfig *it) irq = it->options[1]; if (irq) { - printk("( irq = %u )", irq); + printk(KERN_INFO "( irq = %u )\n", irq); ret = request_irq(irq, rti800_interrupt, 0, "rti800", dev); if (ret < 0) { - printk(" Failed to allocate IRQ\n"); + printk(KERN_WARNING " Failed to allocate IRQ\n"); return ret; } dev->irq = irq; } else { - printk("( no irq )"); + printk(KERN_INFO "( no irq )\n"); } dev->board_name = this_board->name; @@ -460,14 +460,12 @@ static int rti800_attach(struct comedi_device *dev, struct comedi_devconfig *it) s->type = COMEDI_SUBD_TIMER; #endif - printk("\n"); - return 0; } static int rti800_detach(struct comedi_device *dev) { - printk("comedi%d: rti800: remove\n", dev->minor); + printk(KERN_INFO "comedi%d: rti800: remove\n", dev->minor); if (dev->iobase) release_region(dev->iobase, RTI800_SIZE); -- cgit v1.2.3 From df16b962f06724f006ff06aa9e69971113e2fa46 Mon Sep 17 00:00:00 2001 From: Jochen Maes Date: Wed, 10 Feb 2010 00:19:46 +0100 Subject: staging: dream: Codestyle fix Fixed Codestyle issues Signed-off-by: Jochen Maes Cc: Pavel Machek Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dream/pmem.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dream/pmem.c b/drivers/staging/dream/pmem.c index def646812348..503ba212dc96 100644 --- a/drivers/staging/dream/pmem.c +++ b/drivers/staging/dream/pmem.c @@ -37,17 +37,17 @@ * the file should not be released until put_pmem_file is called */ #define PMEM_FLAGS_BUSY 0x1 /* indicates that this is a suballocation of a larger master range */ -#define PMEM_FLAGS_CONNECTED 0x1 << 1 +#define PMEM_FLAGS_CONNECTED ( 0x1 << 1 ) /* indicates this is a master and not a sub allocation and that it is mmaped */ -#define PMEM_FLAGS_MASTERMAP 0x1 << 2 +#define PMEM_FLAGS_MASTERMAP ( 0x1 << 2 ) /* submap and unsubmap flags indicate: * 00: subregion has never been mmaped * 10: subregion has been mmaped, reference to the mm was taken * 11: subretion has ben released, refernece to the mm still held * 01: subretion has been released, reference to the mm has been released */ -#define PMEM_FLAGS_SUBMAP 0x1 << 3 -#define PMEM_FLAGS_UNSUBMAP 0x1 << 4 +#define PMEM_FLAGS_SUBMAP ( 0x1 << 3 ) +#define PMEM_FLAGS_UNSUBMAP ( 0x1 << 4 ) struct pmem_data { @@ -91,7 +91,7 @@ struct pmem_region_node { #define PMEM_DEBUG_MSGS 0 #if PMEM_DEBUG_MSGS -#define DLOG(fmt,args...) \ +#define DLOG(fmt, args...) \ do { printk(KERN_INFO "[%s:%s:%d] "fmt, __FILE__, __func__, __LINE__, \ ##args); } \ while (0) @@ -152,7 +152,7 @@ struct pmem_info { static struct pmem_info pmem[PMEM_MAX_DEVICES]; static int id_count; -#define PMEM_IS_FREE(id, index) !(pmem[id].bitmap[index].allocated) +#define PMEM_IS_FREE(id, index) ( !(pmem[id].bitmap[index].allocated) ) #define PMEM_ORDER(id, index) pmem[id].bitmap[index].order #define PMEM_BUDDY_INDEX(id, index) (index ^ (1 << PMEM_ORDER(id, index))) #define PMEM_NEXT_INDEX(id, index) (index + (1 << PMEM_ORDER(id, index))) @@ -708,9 +708,8 @@ int get_pmem_addr(struct file *file, unsigned long *start, struct pmem_data *data; int id; - if (!is_pmem_file(file) || !has_allocation(file)) { + if (!is_pmem_file(file) || !has_allocation(file)) return -1; - } data = (struct pmem_data *)file->private_data; if (data->index == -1) { @@ -789,9 +788,8 @@ void flush_pmem_file(struct file *file, unsigned long offset, unsigned long len) struct list_head *elt; void *flush_start, *flush_end; - if (!is_pmem_file(file) || !has_allocation(file)) { + if (!is_pmem_file(file) || !has_allocation(file)) return; - } id = get_id(file); data = (struct pmem_data *)file->private_data; @@ -833,7 +831,7 @@ static int pmem_connect(unsigned long connect, struct file *file) src_file = fget_light(connect, &put_needed); DLOG("connect %p to %p\n", file, src_file); if (!src_file) { - printk("pmem: src file not found!\n"); + printk(KERN_INFO "pmem: src file not found!\n"); ret = -EINVAL; goto err_no_file; } @@ -846,7 +844,7 @@ static int pmem_connect(unsigned long connect, struct file *file) src_data = (struct pmem_data *)src_file->private_data; if (has_allocation(file) && (data->index != src_data->index)) { - printk("pmem: file is already mapped but doesn't match this" + printk(KERN_INFO "pmem: file is already mapped but doesn't match this" " src_file!\n"); ret = -EINVAL; goto err_bad_file; @@ -885,7 +883,7 @@ lock_mm: mm = get_task_mm(data->task); if (!mm) { #if PMEM_DEBUG - printk("pmem: can't remap task is gone!\n"); + printk(KERN_DEBUG "pmem: can't remap task is gone!\n"); #endif up_read(&data->sem); return -1; @@ -936,7 +934,7 @@ int pmem_remap(struct pmem_region *region, struct file *file, if (unlikely(!PMEM_IS_PAGE_ALIGNED(region->offset) || !PMEM_IS_PAGE_ALIGNED(region->len))) { #if PMEM_DEBUG - printk("pmem: request for unaligned pmem suballocation " + printk(KERN_DEBUG "pmem: request for unaligned pmem suballocation " "%lx %lx\n", region->offset, region->len); #endif return -EINVAL; -- cgit v1.2.3 From 451ff3737d220a17869d7304d5735146f9cc587f Mon Sep 17 00:00:00 2001 From: Jochen Maes Date: Wed, 10 Feb 2010 10:27:14 +0100 Subject: staging: dream: another Codestyle patch Fixed code style issues. Signed-off-by: Jochen Maes Acked-by: Pavel Machek Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dream/camera/msm_camera.c | 63 +++++++++++++++---------------- 1 file changed, 30 insertions(+), 33 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dream/camera/msm_camera.c b/drivers/staging/dream/camera/msm_camera.c index 87e118d18827..06dba60dda0b 100644 --- a/drivers/staging/dream/camera/msm_camera.c +++ b/drivers/staging/dream/camera/msm_camera.c @@ -2,7 +2,7 @@ * Copyright (C) 2008-2009 QUALCOMM Incorporated. */ -//FIXME: most allocations need not be GFP_ATOMIC +/* FIXME: most allocations need not be GFP_ATOMIC /* FIXME: management of mutexes */ /* FIXME: msm_pmem_region_lookup return values */ /* FIXME: way too many copy to/from user */ @@ -76,14 +76,14 @@ static LIST_HEAD(msm_sensors); list_del_init(&qcmd->list); \ kfree(qcmd); \ }; \ -} while(0) +} while (0) #define MSM_DRAIN_QUEUE(sync, name) do { \ unsigned long flags; \ spin_lock_irqsave(&(sync)->name##_lock, flags); \ MSM_DRAIN_QUEUE_NOSYNC(sync, name); \ spin_unlock_irqrestore(&(sync)->name##_lock, flags); \ -} while(0) +} while (0) static int check_overlap(struct hlist_head *ptype, unsigned long paddr, @@ -361,7 +361,7 @@ static int __msm_get_frame(struct msm_sync *sync, if (!frame->buffer) { pr_err("%s: cannot get frame, invalid lookup address " "y=%x cbcr=%x offset=%d\n", - __FUNCTION__, + __func__, pphy->y_phy, pphy->cbcr_phy, frame->y_off); @@ -455,7 +455,7 @@ static int msm_disable_vfe(struct msm_sync *sync, void __user *arg) return rc; } -static struct msm_queue_cmd* __msm_control(struct msm_sync *sync, +static struct msm_queue_cmd *__msm_control(struct msm_sync *sync, struct msm_control_device_queue *queue, struct msm_queue_cmd *qcmd, int timeout) @@ -592,8 +592,7 @@ end: * a result of a successful completion, we are freeing the qcmd that * we dequeued from queue->ctrl_status_q. */ - if (qcmd) - kfree(qcmd); + kfree(qcmd); CDBG("msm_control: end rc = %d\n", rc); return rc; @@ -670,7 +669,7 @@ static int msm_get_stats(struct msm_sync *sync, void __user *arg) &(stats.fd)); if (!stats.buffer) { pr_err("%s: msm_pmem_stats_ptov_lookup error\n", - __FUNCTION__); + __func__); rc = -EINVAL; goto failure; } @@ -718,8 +717,7 @@ static int msm_get_stats(struct msm_sync *sync, void __user *arg) buf.fmain.buffer = (unsigned long)region.vaddr; buf.fmain.fd = region.fd; - } - else { + } else { pr_err("%s: pmem lookup failed\n", __func__); rc = -EINVAL; @@ -796,8 +794,7 @@ static int msm_get_stats(struct msm_sync *sync, void __user *arg) } failure: - if (qcmd) - kfree(qcmd); + kfree(qcmd); CDBG("msm_get_stats: %d\n", rc); return rc; @@ -838,8 +835,8 @@ static int msm_ctrl_cmd_done(struct msm_control_device *ctrl_pmsm, kfree(qcmd); goto end; } - } - else ctrlcmd->value = NULL; + } else + ctrlcmd->value = NULL; end: CDBG("msm_ctrl_cmd_done: end rc = %d\n", rc); @@ -869,14 +866,14 @@ static int msm_config_vfe(struct msm_sync *sync, void __user *arg) return -EFAULT; } - switch(cfgcmd.cmd_type) { + switch (cfgcmd.cmd_type) { case CMD_STATS_ENABLE: axi_data.bufnum1 = msm_pmem_region_lookup(&sync->stats, MSM_PMEM_AEC_AWB, ®ion[0], NUM_WB_EXP_STAT_OUTPUT_BUFFERS); if (!axi_data.bufnum1) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } axi_data.region = ®ion[0]; @@ -888,7 +885,7 @@ static int msm_config_vfe(struct msm_sync *sync, void __user *arg) MSM_PMEM_AF, ®ion[0], NUM_AF_STAT_OUTPUT_BUFFERS); if (!axi_data.bufnum1) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } axi_data.region = ®ion[0]; @@ -899,7 +896,7 @@ static int msm_config_vfe(struct msm_sync *sync, void __user *arg) break; default: pr_err("%s: unknown command type %d\n", - __FUNCTION__, cfgcmd.cmd_type); + __func__, cfgcmd.cmd_type); return -EINVAL; } @@ -928,7 +925,7 @@ static int msm_frame_axi_cfg(struct msm_sync *sync, msm_pmem_region_lookup(&sync->frame, pmem_type, ®ion[0], 8); if (!axi_data.bufnum1) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } break; @@ -939,7 +936,7 @@ static int msm_frame_axi_cfg(struct msm_sync *sync, msm_pmem_region_lookup(&sync->frame, pmem_type, ®ion[0], 8); if (!axi_data.bufnum2) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } break; @@ -950,7 +947,7 @@ static int msm_frame_axi_cfg(struct msm_sync *sync, msm_pmem_region_lookup(&sync->frame, pmem_type, ®ion[0], 8); if (!axi_data.bufnum1) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } @@ -959,7 +956,7 @@ static int msm_frame_axi_cfg(struct msm_sync *sync, msm_pmem_region_lookup(&sync->frame, pmem_type, ®ion[axi_data.bufnum1], 8); if (!axi_data.bufnum2) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } break; @@ -970,7 +967,7 @@ static int msm_frame_axi_cfg(struct msm_sync *sync, msm_pmem_region_lookup(&sync->frame, pmem_type, ®ion[0], 8); if (!axi_data.bufnum2) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } break; @@ -981,7 +978,7 @@ static int msm_frame_axi_cfg(struct msm_sync *sync, default: pr_err("%s: unknown command type %d\n", - __FUNCTION__, cfgcmd->cmd_type); + __func__, cfgcmd->cmd_type); return -EINVAL; } @@ -1047,7 +1044,7 @@ static int __msm_put_frame_buf(struct msm_sync *sync, rc = sync->vfefn.vfe_config(&cfgcmd, &pphy); } else { pr_err("%s: msm_pmem_frame_vtop_lookup failed\n", - __FUNCTION__); + __func__); rc = -EINVAL; } @@ -1131,7 +1128,7 @@ static int msm_stats_axi_cfg(struct msm_sync *sync, break; default: pr_err("%s: unknown command type %d\n", - __FUNCTION__, cfgcmd->cmd_type); + __func__, cfgcmd->cmd_type); return -EINVAL; } @@ -1140,7 +1137,7 @@ static int msm_stats_axi_cfg(struct msm_sync *sync, msm_pmem_region_lookup(&sync->stats, pmem_type, ®ion[0], NUM_WB_EXP_STAT_OUTPUT_BUFFERS); if (!axi_data.bufnum1) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } axi_data.region = ®ion[0]; @@ -1177,7 +1174,7 @@ static int msm_put_stats_buffer(struct msm_sync *sync, void __user *arg) cfgcmd.cmd_type = CMD_STATS_AF_BUF_RELEASE; else { pr_err("%s: invalid buf type %d\n", - __FUNCTION__, + __func__, buf.type); rc = -EINVAL; goto put_done; @@ -1223,7 +1220,7 @@ static int msm_axi_config(struct msm_sync *sync, void __user *arg) default: pr_err("%s: unknown command type %d\n", - __FUNCTION__, + __func__, cfgcmd.cmd_type); return -EINVAL; } @@ -1622,7 +1619,7 @@ static int msm_release_control(struct inode *node, struct file *filep) int rc; struct msm_control_device *ctrl_pmsm = filep->private_data; struct msm_device *pmsm = ctrl_pmsm->pmsm; - printk("msm_camera: RELEASE %s\n", filep->f_path.dentry->d_name.name); + printk(KERN_INFO "msm_camera: RELEASE %s\n", filep->f_path.dentry->d_name.name); rc = __msm_release(pmsm->sync); if (!rc) { MSM_DRAIN_QUEUE(&ctrl_pmsm->ctrl_q, ctrl_status_q); @@ -1636,7 +1633,7 @@ static int msm_release_frame(struct inode *node, struct file *filep) { int rc; struct msm_device *pmsm = filep->private_data; - printk("msm_camera: RELEASE %s\n", filep->f_path.dentry->d_name.name); + printk(KERN_INFO "msm_camera: RELEASE %s\n", filep->f_path.dentry->d_name.name); rc = __msm_release(pmsm->sync); if (!rc) { MSM_DRAIN_QUEUE(pmsm->sync, prev_frame_q); @@ -1720,7 +1717,7 @@ static void msm_vfe_sync(struct msm_vfe_resp *vdata, qcmd->type = qtype; if (qtype == MSM_CAM_Q_VFE_MSG) { - switch(vdata->type) { + switch (vdata->type) { case VFE_MSG_OUTPUT1: case VFE_MSG_OUTPUT2: qcmd_frame = @@ -1931,7 +1928,7 @@ static int __msm_v4l2_control(struct msm_sync *sync, memcpy(out->value, ctrl->value, ctrl->length); end: - if (rcmd) kfree(rcmd); + kfree(rcmd); CDBG("__msm_v4l2_control: end rc = %d\n", rc); return rc; } -- cgit v1.2.3 From 13a21ad18cb43574a1a642baf105afdf2a9260c4 Mon Sep 17 00:00:00 2001 From: Jochen Maes Date: Thu, 11 Feb 2010 17:10:42 +0100 Subject: staging: dream: more Code style fixes Removed parenthesis from return statements, split up assignment and if condition Signed-off-by: Jochen Maes Cc: Pavel Machek Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dream/camera/s5k3e2fx.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dream/camera/s5k3e2fx.c b/drivers/staging/dream/camera/s5k3e2fx.c index 66582af5a586..cbd432da88ee 100644 --- a/drivers/staging/dream/camera/s5k3e2fx.c +++ b/drivers/staging/dream/camera/s5k3e2fx.c @@ -743,12 +743,14 @@ static int s5k3e2fx_sensor_open_init(const struct msm_camera_sensor_info *data) } /* initialize AF */ - if ((rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, - 0x3146, 0x3A)) < 0) + rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, + 0x3146, 0x3A) + if (rc < 0) goto init_fail1; - if ((rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, - 0x3130, 0x03)) < 0) + rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, + 0x3130, 0x03) + if (rc < 0) goto init_fail1; goto init_done; @@ -814,20 +816,20 @@ static uint16_t s5k3e2fx_get_prev_lines_pf(void) static uint16_t s5k3e2fx_get_prev_pixels_pl(void) { - return (s5k3e2fx_reg_pat[S_RES_PREVIEW].size_w + - s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_p); + return s5k3e2fx_reg_pat[S_RES_PREVIEW].size_w + + s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_p; } static uint16_t s5k3e2fx_get_pict_lines_pf(void) { - return (s5k3e2fx_reg_pat[S_RES_CAPTURE].size_h + - s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_l); + return s5k3e2fx_reg_pat[S_RES_CAPTURE].size_h + + s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_l; } static uint16_t s5k3e2fx_get_pict_pixels_pl(void) { - return (s5k3e2fx_reg_pat[S_RES_CAPTURE].size_w + - s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_p); + return s5k3e2fx_reg_pat[S_RES_CAPTURE].size_w + + s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_p; } static uint32_t s5k3e2fx_get_pict_max_exp_lc(void) -- cgit v1.2.3 From 742821ce5fdf691826154fe72ba0884f71a40982 Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Thu, 11 Feb 2010 12:07:35 -0600 Subject: staging: r8187se: Change to use common eeprom routines in EEPROM_93CX The TODO list includes switching this driver to use the common EEPROM routines in EEPROM_93CX. Signed-off-by: Larry Finger Tested by: Bernhard Schiffner Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8187se/Kconfig | 1 + drivers/staging/rtl8187se/Makefile | 1 - drivers/staging/rtl8187se/TODO | 1 - drivers/staging/rtl8187se/r8180_93cx6.c | 146 -------------------------------- drivers/staging/rtl8187se/r8180_93cx6.h | 17 ++-- drivers/staging/rtl8187se/r8180_core.c | 68 +++++++++++---- 6 files changed, 61 insertions(+), 173 deletions(-) delete mode 100644 drivers/staging/rtl8187se/r8180_93cx6.c (limited to 'drivers') diff --git a/drivers/staging/rtl8187se/Kconfig b/drivers/staging/rtl8187se/Kconfig index e24a6f7a0d85..155a78e07405 100644 --- a/drivers/staging/rtl8187se/Kconfig +++ b/drivers/staging/rtl8187se/Kconfig @@ -3,6 +3,7 @@ config R8187SE depends on PCI && WLAN select WIRELESS_EXT select WEXT_PRIV + select EEPROM_93CX6 default N ---help--- If built as a module, it will be called r8187se.ko. diff --git a/drivers/staging/rtl8187se/Makefile b/drivers/staging/rtl8187se/Makefile index b395acf5a38e..e6adf91cdd2c 100644 --- a/drivers/staging/rtl8187se/Makefile +++ b/drivers/staging/rtl8187se/Makefile @@ -18,7 +18,6 @@ EXTRA_CFLAGS += -DENABLE_LPS r8187se-objs := \ r8180_core.o \ - r8180_93cx6.o \ r8180_wx.o \ r8180_rtl8225z2.o \ r8185b_init.o \ diff --git a/drivers/staging/rtl8187se/TODO b/drivers/staging/rtl8187se/TODO index a762e79873e9..704949a9da0d 100644 --- a/drivers/staging/rtl8187se/TODO +++ b/drivers/staging/rtl8187se/TODO @@ -5,7 +5,6 @@ TODO: - switch to use shared "librtl" instead of private ieee80211 stack - switch to use LIB80211 - switch to use MAC80211 -- switch to use EEPROM_93CX6 - use kernel coding style - checkpatch.pl fixes - sparse fixes diff --git a/drivers/staging/rtl8187se/r8180_93cx6.c b/drivers/staging/rtl8187se/r8180_93cx6.c deleted file mode 100644 index 7e4711fb930c..000000000000 --- a/drivers/staging/rtl8187se/r8180_93cx6.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - This files contains card eeprom (93c46 or 93c56) programming routines, - memory is addressed by 16 bits words. - - This is part of rtl8180 OpenSource driver. - Copyright (C) Andrea Merello 2004 - Released under the terms of GPL (General Public Licence) - - Parts of this driver are based on the GPL part of the - official realtek driver. - - Parts of this driver are based on the rtl8180 driver skeleton - from Patric Schenke & Andres Salomon. - - Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver. - - We want to tanks the Authors of those projects and the Ndiswrapper - project Authors. -*/ - -#include "r8180_93cx6.h" - -void eprom_cs(struct net_device *dev, short bit) -{ - if(bit) - write_nic_byte(dev, EPROM_CMD, - (1<epromtype==EPROM_93c56){ - addr_str[7]=addr & 1; - addr_str[6]=addr & (1<<1); - addr_str[5]=addr & (1<<2); - addr_str[4]=addr & (1<<3); - addr_str[3]=addr & (1<<4); - addr_str[2]=addr & (1<<5); - addr_str[1]=addr & (1<<6); - addr_str[0]=addr & (1<<7); - addr_len=8; - }else{ - addr_str[5]=addr & 1; - addr_str[4]=addr & (1<<1); - addr_str[3]=addr & (1<<2); - addr_str[2]=addr & (1<<3); - addr_str[1]=addr & (1<<4); - addr_str[0]=addr & (1<<5); - addr_len=6; - } - eprom_cs(dev, 1); - eprom_ck_cycle(dev); - eprom_send_bits_string(dev, read_cmd, 3); - eprom_send_bits_string(dev, addr_str, addr_len); - - //keep chip pin D to low state while reading. - //I'm unsure if it is necessary, but anyway shouldn't hurt - eprom_w(dev, 0); - - for(i=0;i<16;i++){ - //eeprom needs a clk cycle between writing opcode&adr - //and reading data. (eeprom outs a dummy 0) - eprom_ck_cycle(dev); - ret |= (eprom_r(dev)<<(15-i)); - } - - eprom_cs(dev, 0); - eprom_ck_cycle(dev); - - //disable EPROM programming - write_nic_byte(dev, EPROM_CMD, - (EPROM_CMD_NORMAL< +#include #include "r8180_hw.h" #include "r8180.h" @@ -2642,6 +2643,36 @@ static void rtl8180_link_detect_init(plink_detect_t plink_detect) } //YJ,add,080828,end +static void rtl8187se_eeprom_register_read(struct eeprom_93cx6 *eeprom) +{ + struct net_device *dev = eeprom->data; + u8 reg = read_nic_byte(dev, EPROM_CMD); + + eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE; + eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ; + eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK; + eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS; +} + +static void rtl8187se_eeprom_register_write(struct eeprom_93cx6 *eeprom) +{ + struct net_device *dev = eeprom->data; + u8 reg = 2 << 6; + + if (eeprom->reg_data_in) + reg |= RTL818X_EEPROM_CMD_WRITE; + if (eeprom->reg_data_out) + reg |= RTL818X_EEPROM_CMD_READ; + if (eeprom->reg_data_clock) + reg |= RTL818X_EEPROM_CMD_CK; + if (eeprom->reg_chip_select) + reg |= RTL818X_EEPROM_CMD_CS; + + write_nic_byte(dev, EPROM_CMD, reg); + read_nic_byte(dev, EPROM_CMD); + udelay(10); +} + short rtl8180_init(struct net_device *dev) { struct r8180_priv *priv = ieee80211_priv(dev); @@ -2650,8 +2681,16 @@ short rtl8180_init(struct net_device *dev) u32 usValue; u16 tmpu16; int i, j; + struct eeprom_93cx6 eeprom; + u16 eeprom_val; + + eeprom.data = dev; + eeprom.register_read = rtl8187se_eeprom_register_read; + eeprom.register_write = rtl8187se_eeprom_register_write; + eeprom.width = PCI_EEPROM_WIDTH_93C46; - priv->channel_plan = eprom_read(dev, EEPROM_COUNTRY_CODE>>1) & 0xFF; + eeprom_93cx6_read(&eeprom, EEPROM_COUNTRY_CODE>>1, &eeprom_val); + priv->channel_plan = eeprom_val & 0xFF; if(priv->channel_plan > COUNTRY_CODE_GLOBAL_DOMAIN){ printk("rtl8180_init:Error channel plan! Set to default.\n"); priv->channel_plan = 0; @@ -2879,7 +2918,8 @@ short rtl8180_init(struct net_device *dev) // just for sync 85 priv->enable_gpio0 = 0; - usValue = eprom_read(dev, EEPROM_SW_REVD_OFFSET); + eeprom_93cx6_read(&eeprom, EEPROM_SW_REVD_OFFSET, &eeprom_val); + usValue = eeprom_val; DMESG("usValue is 0x%x\n",usValue); //3Read AntennaDiversity @@ -2919,27 +2959,23 @@ short rtl8180_init(struct net_device *dev) else priv->epromtype=EPROM_93c46; - dev->dev_addr[0]=eprom_read(dev,MAC_ADR) & 0xff; - dev->dev_addr[1]=(eprom_read(dev,MAC_ADR) & 0xff00)>>8; - dev->dev_addr[2]=eprom_read(dev,MAC_ADR+1) & 0xff; - dev->dev_addr[3]=(eprom_read(dev,MAC_ADR+1) & 0xff00)>>8; - dev->dev_addr[4]=eprom_read(dev,MAC_ADR+2) & 0xff; - dev->dev_addr[5]=(eprom_read(dev,MAC_ADR+2) & 0xff00)>>8; + eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *) + dev->dev_addr, 3); for(i=1,j=0; i<14; i+=2,j++){ - word = eprom_read(dev,EPROM_TXPW_CH1_2 + j); + eeprom_93cx6_read(&eeprom, EPROM_TXPW_CH1_2 + j, &word); priv->chtxpwr[i]=word & 0xff; priv->chtxpwr[i+1]=(word & 0xff00)>>8; } for (i = 1, j = 0; i < 14; i += 2, j++) { - word = eprom_read(dev, EPROM_TXPW_OFDM_CH1_2 + j); + eeprom_93cx6_read(&eeprom, EPROM_TXPW_OFDM_CH1_2 + j, &word); priv->chtxpwr_ofdm[i] = word & 0xff; priv->chtxpwr_ofdm[i+1] = (word & 0xff00) >> 8; } /* 3Read crystal calibtration and thermal meter indication on 87SE. */ + eeprom_93cx6_read(&eeprom, EEPROM_RSV>>1, &tmpu16); - tmpu16 = eprom_read(dev, EEPROM_RSV >> 1); /* Crystal calibration for Xin and Xout resp. */ priv->XtalCal_Xout = tmpu16 & EEPROM_XTAL_CAL_XOUT_MASK; priv->XtalCal_Xin = (tmpu16 & EEPROM_XTAL_CAL_XIN_MASK) >> 4; @@ -2951,17 +2987,19 @@ short rtl8180_init(struct net_device *dev) if ((tmpu16 & EEPROM_THERMAL_METER_ENABLE) >> 13) priv->bTxPowerTrack = true; - word = eprom_read(dev,EPROM_TXPW_BASE); + eeprom_93cx6_read(&eeprom, EPROM_TXPW_BASE, &word); priv->cck_txpwr_base = word & 0xf; priv->ofdm_txpwr_base = (word>>4) & 0xf; - version = eprom_read(dev,EPROM_VERSION); + eeprom_93cx6_read(&eeprom, EPROM_VERSION, &version); DMESG("EEPROM version %x",version); priv->rcr_csense = 3; - priv->cs_treshold = (eprom_read(dev, ENERGY_TRESHOLD) & 0xff00) >> 8; + eeprom_93cx6_read(&eeprom, ENERGY_TRESHOLD, &eeprom_val); + priv->cs_treshold = (eeprom_val & 0xff00) >> 8; - priv->rf_chip = 0xff & eprom_read(dev, RFCHIPID); + eeprom_93cx6_read(&eeprom, RFCHIPID, &eeprom_val); + priv->rf_chip = 0xff & eeprom_val; priv->rf_chip = RF_ZEBRA4; priv->rf_sleep = rtl8225z4_rf_sleep; -- cgit v1.2.3 From 6de92dd6495e36c0c2cddbee3e7c6a49f608e7cf Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Thu, 11 Feb 2010 14:41:24 -0600 Subject: Staging: r8187se: Fix for LED not following radio switch The current driver does not follow the state of the RF switch. Signed-off-by: Larry Finger Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8187se/r8180_core.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8187se/r8180_core.c b/drivers/staging/rtl8187se/r8180_core.c index ac987d149219..0b7ec6b949b4 100644 --- a/drivers/staging/rtl8187se/r8180_core.c +++ b/drivers/staging/rtl8187se/r8180_core.c @@ -4238,11 +4238,12 @@ void GPIOChangeRFWorkItemCallBack(struct work_struct *work) /* HW radio On/Off according to the value of FF51[4](config0) */ btConfig0 = btPSR = read_nic_byte(dev, CONFIG0); - /* Turn on LED. */ - write_nic_byte(dev, PSR, btPSR | BIT3); - eRfPowerStateToSet = (btConfig0 & BIT4) ? eRfOn : eRfOff; + /* Turn LED back on when radio enabled */ + if (eRfPowerStateToSet == eRfOn) + write_nic_byte(dev, PSR, btPSR | BIT3); + if ((priv->ieee80211->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn)) { priv->ieee80211->bHwRadioOff = false; -- cgit v1.2.3 From cd9d25ba31b2def7f84da1e3cedf21e8ebb90722 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 12 Feb 2010 14:48:01 +0300 Subject: staging: vt6655: add missing curly braces It's clear from the indent levels and the context that there are supposed to be curly braces here. Signed-off-by: Dan Carpenter Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vt6655/card.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vt6655/card.c b/drivers/staging/vt6655/card.c index db786142717f..bf4fd49709df 100644 --- a/drivers/staging/vt6655/card.c +++ b/drivers/staging/vt6655/card.c @@ -2788,16 +2788,18 @@ void CARDvUpdateBasicTopRate (PVOID pDeviceHandler) //Determines the highest basic rate. for (ii = RATE_54M; ii >= RATE_6M; ii --) { - if ( (pDevice->wBasicRate) & ((WORD)(1<wBasicRate) & ((WORD)(1<byTopOFDMBasicRate = byTopOFDM; for (ii = RATE_11M;; ii --) { - if ( (pDevice->wBasicRate) & ((WORD)(1<wBasicRate) & ((WORD)(1< Date: Sat, 13 Feb 2010 20:21:43 +0000 Subject: Staging: comedi: bracing fix to ni_atmio.c This is a patch to ni_atmio.c file to fix up bracing style problems found by checkpatch.pl tool Signed-off-by: Graham M Howe Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_atmio.c | 34 +++++++++++++++---------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_atmio.c b/drivers/staging/comedi/drivers/ni_atmio.c index 8ead31164d5c..003d00b595b0 100644 --- a/drivers/staging/comedi/drivers/ni_atmio.c +++ b/drivers/staging/comedi/drivers/ni_atmio.c @@ -329,11 +329,11 @@ static uint16_t ni_atmio_win_in(struct comedi_device *dev, int addr) } static struct pnp_device_id device_ids[] = { - {.id = "NIC1900",.driver_data = 0}, - {.id = "NIC2400",.driver_data = 0}, - {.id = "NIC2500",.driver_data = 0}, - {.id = "NIC2600",.driver_data = 0}, - {.id = "NIC2700",.driver_data = 0}, + {.id = "NIC1900", .driver_data = 0}, + {.id = "NIC2400", .driver_data = 0}, + {.id = "NIC2500", .driver_data = 0}, + {.id = "NIC2600", .driver_data = 0}, + {.id = "NIC2700", .driver_data = 0}, {.id = ""} }; @@ -362,9 +362,9 @@ static int ni_atmio_detach(struct comedi_device *dev) if (dev->iobase) release_region(dev->iobase, NI_SIZE); - if (dev->irq) { + if (dev->irq) free_irq(dev->irq, dev); - } + if (devpriv->isapnp_dev) pnp_device_detach(devpriv->isapnp_dev); @@ -387,8 +387,8 @@ static int ni_isapnp_find_board(struct pnp_dev **dev) if (pnp_device_attach(isapnp_dev) < 0) { printk - ("ni_atmio: %s found but already active, skipping.\n", - ni_boards[i].name); + ("ni_atmio: %s found but already active, skipping.\n", + ni_boards[i].name); continue; } if (pnp_activate_dev(isapnp_dev) < 0) { @@ -496,9 +496,9 @@ static int ni_atmio_attach(struct comedi_device *dev, /* generic E series stuff in ni_mio_common.c */ ret = ni_E_init(dev, it); - if (ret < 0) { + if (ret < 0) return ret; - } + return 0; } @@ -509,16 +509,16 @@ static int ni_getboardtype(struct comedi_device *dev) int i; for (i = 0; i < n_ni_boards; i++) { - if (ni_boards[i].device_id == device_id) { + if (ni_boards[i].device_id == device_id) return i; - } + } - if (device_id == 255) { + if (device_id == 255) printk(" can't find board\n"); - } else if (device_id == 0) { + else if (device_id == 0) printk(" EEPROM read error (?) or device not found\n"); - } else { + else printk(" unknown device ID %d -- contact author\n", device_id); - } + return -1; } -- cgit v1.2.3 From 46800b225f8c9dc264e1e9c15b1e104b9e0af5b5 Mon Sep 17 00:00:00 2001 From: Svenne Krap Date: Sun, 14 Feb 2010 18:59:42 +0100 Subject: Staging: wlan-ng: clean up assignments in if statements Trivial changes to code-paths. Signed-off-by: Svenne Krap Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlan-ng/hfa384x_usb.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/wlan-ng/hfa384x_usb.c b/drivers/staging/wlan-ng/hfa384x_usb.c index c6a9e17ec79b..bd2eba304842 100644 --- a/drivers/staging/wlan-ng/hfa384x_usb.c +++ b/drivers/staging/wlan-ng/hfa384x_usb.c @@ -1909,16 +1909,20 @@ int hfa384x_drvr_flashdl_enable(hfa384x_t *hw) return -EINVAL; /* Retrieve the buffer loc&size and timeout */ - if ((result = hfa384x_drvr_getconfig(hw, HFA384x_RID_DOWNLOADBUFFER, - &(hw->bufinfo), - sizeof(hw->bufinfo)))) { + + result = hfa384x_drvr_getconfig(hw, HFA384x_RID_DOWNLOADBUFFER, + &(hw->bufinfo), sizeof(hw->bufinfo)); + if (result) { return result; } hw->bufinfo.page = le16_to_cpu(hw->bufinfo.page); hw->bufinfo.offset = le16_to_cpu(hw->bufinfo.offset); hw->bufinfo.len = le16_to_cpu(hw->bufinfo.len); - if ((result = hfa384x_drvr_getconfig16(hw, HFA384x_RID_MAXLOADTIME, - &(hw->dltimeout)))) { + + result = hfa384x_drvr_getconfig16(hw, HFA384x_RID_MAXLOADTIME, + &(hw->dltimeout)); + + if (result) { return result; } hw->dltimeout = le16_to_cpu(hw->dltimeout); @@ -3073,7 +3077,9 @@ static void hfa384x_usbctlxq_run(hfa384x_t *hw) /* Now submit the URB and update the CTLX's state */ - if ((result = SUBMIT_URB(&hw->ctlx_urb, GFP_ATOMIC)) == 0) { + + result = SUBMIT_URB(&hw->ctlx_urb, GFP_ATOMIC); + if (result == 0) { /* This CTLX is now running on the active queue */ head->state = CTLX_REQ_SUBMITTED; @@ -3599,7 +3605,8 @@ static void hfa384x_int_rxmonitor(wlandevice_t *wlandev, skblen - sizeof(p80211_caphdr_t)); } - if ((skb = dev_alloc_skb(skblen)) == NULL) { + skb = dev_alloc_skb(skblen); + if (skb == NULL) { printk(KERN_ERR "alloc_skb failed trying to allocate %d bytes\n", skblen); @@ -3870,7 +3877,8 @@ retry: delresp: if (delete_resptimer) { - if ((timer_ok = del_timer(&hw->resptimer)) != 0) { + timer_ok = del_timer(&hw->resptimer); + if (timer_ok != 0) { hw->resp_timer_done = 1; } } -- cgit v1.2.3 From 5dd8acc8fd6b0476a2dc49bc6de4712d22c368c0 Mon Sep 17 00:00:00 2001 From: Svenne Krap Date: Sun, 14 Feb 2010 18:59:00 +0100 Subject: Staging: wlan-ng: multiple safe style cleanups Cleanups as suggested by checkpatch.pl utiltiy. .o's from before and after cleanup have matching SHA1s. Signed-off-by: Svenne Krap Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlan-ng/hfa384x.h | 74 ++++++++++++++++----------------- drivers/staging/wlan-ng/hfa384x_usb.c | 8 ++-- drivers/staging/wlan-ng/p80211conv.c | 23 +++++----- drivers/staging/wlan-ng/p80211conv.h | 4 +- drivers/staging/wlan-ng/p80211metadef.h | 18 ++++---- drivers/staging/wlan-ng/p80211mgmt.h | 42 +++++++++---------- drivers/staging/wlan-ng/p80211netdev.c | 7 ++-- drivers/staging/wlan-ng/p80211netdev.h | 44 ++++++++++---------- drivers/staging/wlan-ng/p80211req.c | 2 +- drivers/staging/wlan-ng/p80211req.h | 2 +- drivers/staging/wlan-ng/p80211types.h | 18 ++++---- drivers/staging/wlan-ng/p80211wext.c | 55 ++++++++++++------------ drivers/staging/wlan-ng/prism2fw.c | 60 +++++++++++++------------- drivers/staging/wlan-ng/prism2mgmt.c | 4 +- drivers/staging/wlan-ng/prism2mgmt.h | 48 ++++++++++----------- drivers/staging/wlan-ng/prism2mib.c | 6 +-- drivers/staging/wlan-ng/prism2sta.c | 18 ++++---- 17 files changed, 217 insertions(+), 216 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/wlan-ng/hfa384x.h b/drivers/staging/wlan-ng/hfa384x.h index 46cce8159e59..d93e6e90720b 100644 --- a/drivers/staging/wlan-ng/hfa384x.h +++ b/drivers/staging/wlan-ng/hfa384x.h @@ -115,8 +115,8 @@ /* Make a 32-bit flat address from AUX format 16-bit page and offset */ #define HFA384x_ADDR_AUX_MKFLAT(p, o) \ - (((u32)(((u16)(p))&HFA384x_ADDR_AUX_PAGE_MASK)) << 7) | \ - ((u32)(((u16)(o))&HFA384x_ADDR_AUX_OFF_MASK)) + ((((u32)(((u16)(p))&HFA384x_ADDR_AUX_PAGE_MASK)) << 7) | \ + ((u32)(((u16)(o))&HFA384x_ADDR_AUX_OFF_MASK))) /* Make CMD format offset and page from a 32-bit flat address */ #define HFA384x_ADDR_CMD_MKPAGE(f) \ @@ -402,7 +402,7 @@ typedef struct hfa384x_authenticateStation_data { /*-- Configuration Record: WPAData (data portion only) --*/ typedef struct hfa384x_WPAData { u16 datalen; - u8 data[0]; // max 80 + u8 data[0]; /* max 80 */ } __attribute__ ((packed)) hfa384x_WPAData_t; /*-------------------------------------------------------------------- @@ -1133,7 +1133,7 @@ struct hfa384x; typedef void (*ctlx_cmdcb_t) (struct hfa384x *, const struct hfa384x_usbctlx *); -typedef void (*ctlx_usercb_t) (struct hfa384x * hw, +typedef void (*ctlx_usercb_t) (struct hfa384x *hw, void *ctlxresult, void *usercb_data); typedef struct hfa384x_usbctlx { @@ -1320,25 +1320,25 @@ typedef struct hfa384x { } hfa384x_t; -void hfa384x_create(hfa384x_t * hw, struct usb_device *usb); -void hfa384x_destroy(hfa384x_t * hw); +void hfa384x_create(hfa384x_t *hw, struct usb_device *usb); +void hfa384x_destroy(hfa384x_t *hw); int -hfa384x_corereset(hfa384x_t * hw, int holdtime, int settletime, int genesis); -int hfa384x_drvr_commtallies(hfa384x_t * hw); -int hfa384x_drvr_disable(hfa384x_t * hw, u16 macport); -int hfa384x_drvr_enable(hfa384x_t * hw, u16 macport); -int hfa384x_drvr_flashdl_enable(hfa384x_t * hw); -int hfa384x_drvr_flashdl_disable(hfa384x_t * hw); -int hfa384x_drvr_flashdl_write(hfa384x_t * hw, u32 daddr, void *buf, u32 len); -int hfa384x_drvr_getconfig(hfa384x_t * hw, u16 rid, void *buf, u16 len); -int hfa384x_drvr_ramdl_enable(hfa384x_t * hw, u32 exeaddr); -int hfa384x_drvr_ramdl_disable(hfa384x_t * hw); -int hfa384x_drvr_ramdl_write(hfa384x_t * hw, u32 daddr, void *buf, u32 len); -int hfa384x_drvr_readpda(hfa384x_t * hw, void *buf, unsigned int len); -int hfa384x_drvr_setconfig(hfa384x_t * hw, u16 rid, void *buf, u16 len); - -static inline int hfa384x_drvr_getconfig16(hfa384x_t * hw, u16 rid, void *val) +hfa384x_corereset(hfa384x_t *hw, int holdtime, int settletime, int genesis); +int hfa384x_drvr_commtallies(hfa384x_t *hw); +int hfa384x_drvr_disable(hfa384x_t *hw, u16 macport); +int hfa384x_drvr_enable(hfa384x_t *hw, u16 macport); +int hfa384x_drvr_flashdl_enable(hfa384x_t *hw); +int hfa384x_drvr_flashdl_disable(hfa384x_t *hw); +int hfa384x_drvr_flashdl_write(hfa384x_t *hw, u32 daddr, void *buf, u32 len); +int hfa384x_drvr_getconfig(hfa384x_t *hw, u16 rid, void *buf, u16 len); +int hfa384x_drvr_ramdl_enable(hfa384x_t *hw, u32 exeaddr); +int hfa384x_drvr_ramdl_disable(hfa384x_t *hw); +int hfa384x_drvr_ramdl_write(hfa384x_t *hw, u32 daddr, void *buf, u32 len); +int hfa384x_drvr_readpda(hfa384x_t *hw, void *buf, unsigned int len); +int hfa384x_drvr_setconfig(hfa384x_t *hw, u16 rid, void *buf, u16 len); + +static inline int hfa384x_drvr_getconfig16(hfa384x_t *hw, u16 rid, void *val) { int result = 0; result = hfa384x_drvr_getconfig(hw, rid, val, sizeof(u16)); @@ -1347,44 +1347,44 @@ static inline int hfa384x_drvr_getconfig16(hfa384x_t * hw, u16 rid, void *val) return result; } -static inline int hfa384x_drvr_setconfig16(hfa384x_t * hw, u16 rid, u16 val) +static inline int hfa384x_drvr_setconfig16(hfa384x_t *hw, u16 rid, u16 val) { u16 value = cpu_to_le16(val); return hfa384x_drvr_setconfig(hw, rid, &value, sizeof(value)); } int -hfa384x_drvr_getconfig_async(hfa384x_t * hw, +hfa384x_drvr_getconfig_async(hfa384x_t *hw, u16 rid, ctlx_usercb_t usercb, void *usercb_data); int -hfa384x_drvr_setconfig_async(hfa384x_t * hw, +hfa384x_drvr_setconfig_async(hfa384x_t *hw, u16 rid, void *buf, u16 len, ctlx_usercb_t usercb, void *usercb_data); static inline int -hfa384x_drvr_setconfig16_async(hfa384x_t * hw, u16 rid, u16 val) +hfa384x_drvr_setconfig16_async(hfa384x_t *hw, u16 rid, u16 val) { u16 value = cpu_to_le16(val); return hfa384x_drvr_setconfig_async(hw, rid, &value, sizeof(value), NULL, NULL); } -int hfa384x_drvr_start(hfa384x_t * hw); -int hfa384x_drvr_stop(hfa384x_t * hw); +int hfa384x_drvr_start(hfa384x_t *hw); +int hfa384x_drvr_stop(hfa384x_t *hw); int -hfa384x_drvr_txframe(hfa384x_t * hw, struct sk_buff *skb, - p80211_hdr_t * p80211_hdr, p80211_metawep_t * p80211_wep); -void hfa384x_tx_timeout(wlandevice_t * wlandev); - -int hfa384x_cmd_initialize(hfa384x_t * hw); -int hfa384x_cmd_enable(hfa384x_t * hw, u16 macport); -int hfa384x_cmd_disable(hfa384x_t * hw, u16 macport); -int hfa384x_cmd_allocate(hfa384x_t * hw, u16 len); -int hfa384x_cmd_monitor(hfa384x_t * hw, u16 enable); +hfa384x_drvr_txframe(hfa384x_t *hw, struct sk_buff *skb, + p80211_hdr_t *p80211_hdr, p80211_metawep_t *p80211_wep); +void hfa384x_tx_timeout(wlandevice_t *wlandev); + +int hfa384x_cmd_initialize(hfa384x_t *hw); +int hfa384x_cmd_enable(hfa384x_t *hw, u16 macport); +int hfa384x_cmd_disable(hfa384x_t *hw, u16 macport); +int hfa384x_cmd_allocate(hfa384x_t *hw, u16 len); +int hfa384x_cmd_monitor(hfa384x_t *hw, u16 enable); int -hfa384x_cmd_download(hfa384x_t * hw, +hfa384x_cmd_download(hfa384x_t *hw, u16 mode, u16 lowaddr, u16 highaddr, u16 codelen); #endif /* __KERNEL__ */ diff --git a/drivers/staging/wlan-ng/hfa384x_usb.c b/drivers/staging/wlan-ng/hfa384x_usb.c index bd2eba304842..612995b3d576 100644 --- a/drivers/staging/wlan-ng/hfa384x_usb.c +++ b/drivers/staging/wlan-ng/hfa384x_usb.c @@ -126,7 +126,7 @@ #include #include -#define SUBMIT_URB(u,f) usb_submit_urb(u,f) +#define SUBMIT_URB(u, f) usb_submit_urb(u, f) #include "p80211types.h" #include "p80211hdr.h" @@ -627,7 +627,7 @@ static hfa384x_usbctlx_t *usbctlx_alloc(void) { hfa384x_usbctlx_t *ctlx; - ctlx = kmalloc(sizeof(*ctlx), in_interrupt()? GFP_ATOMIC : GFP_KERNEL); + ctlx = kmalloc(sizeof(*ctlx), in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); if (ctlx != NULL) { memset(ctlx, 0, sizeof(*ctlx)); init_completion(&ctlx->done); @@ -675,7 +675,7 @@ struct usbctlx_cmd_completor { }; typedef struct usbctlx_cmd_completor usbctlx_cmd_completor_t; -static int usbctlx_cmd_completor_fn(usbctlx_completor_t * head) +static int usbctlx_cmd_completor_fn(usbctlx_completor_t *head) { usbctlx_cmd_completor_t *complete = (usbctlx_cmd_completor_t *) head; return usbctlx_get_status(complete->cmdresp, complete->result); @@ -3649,7 +3649,7 @@ static void hfa384x_int_rxmonitor(wlandevice_t *wlandev, /* check for unencrypted stuff if WEP bit set. */ if (*(datap - hdrlen + 1) & 0x40) /* wep set */ if ((*(datap) == 0xaa) && (*(datap + 1) == 0xaa)) - *(datap - hdrlen + 1) &= 0xbf; // clear wep; it's the 802.2 header! + *(datap - hdrlen + 1) &= 0xbf; /* clear wep; it's the 802.2 header! */ } if (hw->sniff_fcs) { diff --git a/drivers/staging/wlan-ng/p80211conv.c b/drivers/staging/wlan-ng/p80211conv.c index 5952c671073f..99c5ec45b00d 100644 --- a/drivers/staging/wlan-ng/p80211conv.c +++ b/drivers/staging/wlan-ng/p80211conv.c @@ -206,12 +206,12 @@ int skb_ether_to_p80211(wlandevice_t *wlandev, u32 ethconv, /* XXXX need to pick keynum other than default? */ p80211_wep->data = kmalloc(skb->len, GFP_ATOMIC); - - if ((foo = wep_encrypt(wlandev, skb->data, p80211_wep->data, - skb->len, - (wlandev->hostwep & - HOSTWEP_DEFAULTKEY_MASK), - p80211_wep->iv, p80211_wep->icv))) { + foo = wep_encrypt(wlandev, skb->data, p80211_wep->data, + skb->len, + (wlandev->hostwep & + HOSTWEP_DEFAULTKEY_MASK), + p80211_wep->iv, p80211_wep->icv); + if (foo) { printk(KERN_WARNING "Host en-WEP failed, dropping frame (%d).\n", foo); @@ -323,11 +323,12 @@ int skb_p80211_to_ether(wlandevice_t *wlandev, u32 ethconv, skb->len); return 1; } - if ((foo = wep_decrypt(wlandev, skb->data + payload_offset + 4, - payload_length - 8, -1, - skb->data + payload_offset, - skb->data + payload_offset + - payload_length - 4))) { + foo = wep_decrypt(wlandev, skb->data + payload_offset + 4, + payload_length - 8, -1, + skb->data + payload_offset, + skb->data + payload_offset + + payload_length - 4); + if (foo) { /* de-wep failed, drop skb. */ pr_debug("Host de-WEP failed, dropping frame (%d).\n", foo); diff --git a/drivers/staging/wlan-ng/p80211conv.h b/drivers/staging/wlan-ng/p80211conv.h index 0c62df19fa7f..6fe163be24f6 100644 --- a/drivers/staging/wlan-ng/p80211conv.h +++ b/drivers/staging/wlan-ng/p80211conv.h @@ -153,8 +153,8 @@ struct wlandevice; int skb_p80211_to_ether(struct wlandevice *wlandev, u32 ethconv, struct sk_buff *skb); int skb_ether_to_p80211(struct wlandevice *wlandev, u32 ethconv, - struct sk_buff *skb, p80211_hdr_t * p80211_hdr, - p80211_metawep_t * p80211_wep); + struct sk_buff *skb, p80211_hdr_t *p80211_hdr, + p80211_metawep_t *p80211_wep); int p80211_stt_findproto(u16 proto); diff --git a/drivers/staging/wlan-ng/p80211metadef.h b/drivers/staging/wlan-ng/p80211metadef.h index da8b6f53c74f..10605285cf6e 100644 --- a/drivers/staging/wlan-ng/p80211metadef.h +++ b/drivers/staging/wlan-ng/p80211metadef.h @@ -190,9 +190,9 @@ (P80211DID_MKSECTION(2) | \ P80211DID_MKGROUP(1)) #define DIDmib_dot11mac_dot11OperationTable_dot11MACAddress \ - (P80211DID_MKSECTION(2) | \ - P80211DID_MKGROUP(1) | \ - P80211DID_MKITEM(1) | 0x18000000) + ((P80211DID_MKSECTION(2) | \ + P80211DID_MKGROUP(1) | \ + P80211DID_MKITEM(1) | 0x18000000)) #define DIDmib_dot11mac_dot11OperationTable_dot11RTSThreshold \ (P80211DID_MKSECTION(2) | \ P80211DID_MKGROUP(1) | \ @@ -210,18 +210,18 @@ P80211DID_MKGROUP(1) | \ P80211DID_MKITEM(5) | 0x18000000) #define DIDmib_dot11mac_dot11OperationTable_dot11MaxTransmitMSDULifetime \ - (P80211DID_MKSECTION(2) | \ - P80211DID_MKGROUP(1) | \ - P80211DID_MKITEM(6) | 0x10000000) + (P80211DID_MKSECTION(2) | \ + P80211DID_MKGROUP(1) | \ + P80211DID_MKITEM(6) | 0x10000000) #define DIDmib_cat_dot11phy \ P80211DID_MKSECTION(3) #define DIDmib_dot11phy_dot11PhyOperationTable \ (P80211DID_MKSECTION(3) | \ P80211DID_MKGROUP(1)) #define DIDmib_dot11phy_dot11PhyTxPowerTable_dot11CurrentTxPowerLevel \ - (P80211DID_MKSECTION(3) | \ - P80211DID_MKGROUP(3) | \ - P80211DID_MKITEM(10) | 0x18000000) + (P80211DID_MKSECTION(3) | \ + P80211DID_MKGROUP(3) | \ + P80211DID_MKITEM(10) | 0x18000000) #define DIDmib_dot11phy_dot11PhyDSSSTable \ (P80211DID_MKSECTION(3) | \ P80211DID_MKGROUP(5)) diff --git a/drivers/staging/wlan-ng/p80211mgmt.h b/drivers/staging/wlan-ng/p80211mgmt.h index 14cdc86d1676..deb52f5fd780 100644 --- a/drivers/staging/wlan-ng/p80211mgmt.h +++ b/drivers/staging/wlan-ng/p80211mgmt.h @@ -100,7 +100,7 @@ #ifndef _P80211MGMT_H #define _P80211MGMT_H -#ifndef _P80211HDR_H +#ifndef _P80211HDR_H #include "p80211hdr.h" #endif @@ -496,25 +496,25 @@ typedef struct wlan_fr_deauthen { } wlan_fr_deauthen_t; -void wlan_mgmt_encode_beacon(wlan_fr_beacon_t * f); -void wlan_mgmt_decode_beacon(wlan_fr_beacon_t * f); -void wlan_mgmt_encode_disassoc(wlan_fr_disassoc_t * f); -void wlan_mgmt_decode_disassoc(wlan_fr_disassoc_t * f); -void wlan_mgmt_encode_assocreq(wlan_fr_assocreq_t * f); -void wlan_mgmt_decode_assocreq(wlan_fr_assocreq_t * f); -void wlan_mgmt_encode_assocresp(wlan_fr_assocresp_t * f); -void wlan_mgmt_decode_assocresp(wlan_fr_assocresp_t * f); -void wlan_mgmt_encode_reassocreq(wlan_fr_reassocreq_t * f); -void wlan_mgmt_decode_reassocreq(wlan_fr_reassocreq_t * f); -void wlan_mgmt_encode_reassocresp(wlan_fr_reassocresp_t * f); -void wlan_mgmt_decode_reassocresp(wlan_fr_reassocresp_t * f); -void wlan_mgmt_encode_probereq(wlan_fr_probereq_t * f); -void wlan_mgmt_decode_probereq(wlan_fr_probereq_t * f); -void wlan_mgmt_encode_proberesp(wlan_fr_proberesp_t * f); -void wlan_mgmt_decode_proberesp(wlan_fr_proberesp_t * f); -void wlan_mgmt_encode_authen(wlan_fr_authen_t * f); -void wlan_mgmt_decode_authen(wlan_fr_authen_t * f); -void wlan_mgmt_encode_deauthen(wlan_fr_deauthen_t * f); -void wlan_mgmt_decode_deauthen(wlan_fr_deauthen_t * f); +void wlan_mgmt_encode_beacon(wlan_fr_beacon_t *f); +void wlan_mgmt_decode_beacon(wlan_fr_beacon_t *f); +void wlan_mgmt_encode_disassoc(wlan_fr_disassoc_t *f); +void wlan_mgmt_decode_disassoc(wlan_fr_disassoc_t *f); +void wlan_mgmt_encode_assocreq(wlan_fr_assocreq_t *f); +void wlan_mgmt_decode_assocreq(wlan_fr_assocreq_t *f); +void wlan_mgmt_encode_assocresp(wlan_fr_assocresp_t *f); +void wlan_mgmt_decode_assocresp(wlan_fr_assocresp_t *f); +void wlan_mgmt_encode_reassocreq(wlan_fr_reassocreq_t *f); +void wlan_mgmt_decode_reassocreq(wlan_fr_reassocreq_t *f); +void wlan_mgmt_encode_reassocresp(wlan_fr_reassocresp_t *f); +void wlan_mgmt_decode_reassocresp(wlan_fr_reassocresp_t *f); +void wlan_mgmt_encode_probereq(wlan_fr_probereq_t *f); +void wlan_mgmt_decode_probereq(wlan_fr_probereq_t *f); +void wlan_mgmt_encode_proberesp(wlan_fr_proberesp_t *f); +void wlan_mgmt_decode_proberesp(wlan_fr_proberesp_t *f); +void wlan_mgmt_encode_authen(wlan_fr_authen_t *f); +void wlan_mgmt_decode_authen(wlan_fr_authen_t *f); +void wlan_mgmt_encode_deauthen(wlan_fr_deauthen_t *f); +void wlan_mgmt_decode_deauthen(wlan_fr_deauthen_t *f); #endif /* _P80211MGMT_H */ diff --git a/drivers/staging/wlan-ng/p80211netdev.c b/drivers/staging/wlan-ng/p80211netdev.c index 22424c8903ee..763ab1187a1c 100644 --- a/drivers/staging/wlan-ng/p80211netdev.c +++ b/drivers/staging/wlan-ng/p80211netdev.c @@ -586,7 +586,8 @@ static int p80211knetdev_do_ioctl(netdevice_t *dev, struct ifreq *ifr, int cmd) } /* Allocate a buf of size req->len */ - if ((msgbuf = kmalloc(req->len, GFP_KERNEL))) { + msgbuf = kmalloc(req->len, GFP_KERNEL); + if (msgbuf) { if (copy_from_user(msgbuf, (void __user *)req->data, req->len)) result = -EFAULT; else @@ -646,7 +647,7 @@ static int p80211knetdev_set_mac_address(netdevice_t *dev, void *addr) /* Set up some convenience pointers. */ mibattr = &dot11req.mibattribute; - macaddr = (p80211item_pstr6_t *) & mibattr->data; + macaddr = (p80211item_pstr6_t *) &mibattr->data; resultcode = &dot11req.resultcode; /* Set up a dot11req_mibset */ @@ -674,7 +675,7 @@ static int p80211knetdev_set_mac_address(netdevice_t *dev, void *addr) resultcode->data = 0; /* now fire the request */ - result = p80211req_dorequest(dev->ml_priv, (u8 *) & dot11req); + result = p80211req_dorequest(dev->ml_priv, (u8 *) &dot11req); /* If the request wasn't successful, report an error and don't * change the netdev address diff --git a/drivers/staging/wlan-ng/p80211netdev.h b/drivers/staging/wlan-ng/p80211netdev.h index 8bd9dfb3b9b4..3c8c64800567 100644 --- a/drivers/staging/wlan-ng/p80211netdev.h +++ b/drivers/staging/wlan-ng/p80211netdev.h @@ -179,16 +179,16 @@ typedef struct wlandevice { unsigned int ethconv; /* device methods (init by MSD, used by p80211 */ - int (*open) (struct wlandevice * wlandev); - int (*close) (struct wlandevice * wlandev); - void (*reset) (struct wlandevice * wlandev); - int (*txframe) (struct wlandevice * wlandev, struct sk_buff * skb, - p80211_hdr_t * p80211_hdr, - p80211_metawep_t * p80211_wep); - int (*mlmerequest) (struct wlandevice * wlandev, p80211msg_t * msg); - int (*set_multicast_list) (struct wlandevice * wlandev, - netdevice_t * dev); - void (*tx_timeout) (struct wlandevice * wlandev); + int (*open) (struct wlandevice *wlandev); + int (*close) (struct wlandevice *wlandev); + void (*reset) (struct wlandevice *wlandev); + int (*txframe) (struct wlandevice *wlandev, struct sk_buff *skb, + p80211_hdr_t *p80211_hdr, + p80211_metawep_t *p80211_wep); + int (*mlmerequest) (struct wlandevice *wlandev, p80211msg_t *msg); + int (*set_multicast_list) (struct wlandevice *wlandev, + netdevice_t *dev); + void (*tx_timeout) (struct wlandevice *wlandev); /* 802.11 State */ u8 bssid[WLAN_BSSID_LEN]; @@ -227,16 +227,16 @@ typedef struct wlandevice { } wlandevice_t; /* WEP stuff */ -int wep_change_key(wlandevice_t * wlandev, int keynum, u8 * key, int keylen); -int wep_decrypt(wlandevice_t * wlandev, u8 * buf, u32 len, int key_override, - u8 * iv, u8 * icv); -int wep_encrypt(wlandevice_t * wlandev, u8 * buf, u8 * dst, u32 len, int keynum, - u8 * iv, u8 * icv); - -int wlan_setup(wlandevice_t * wlandev); -int wlan_unsetup(wlandevice_t * wlandev); -int register_wlandev(wlandevice_t * wlandev); -int unregister_wlandev(wlandevice_t * wlandev); -void p80211netdev_rx(wlandevice_t * wlandev, struct sk_buff *skb); -void p80211netdev_hwremoved(wlandevice_t * wlandev); +int wep_change_key(wlandevice_t *wlandev, int keynum, u8 *key, int keylen); +int wep_decrypt(wlandevice_t *wlandev, u8 *buf, u32 len, int key_override, + u8 *iv, u8 *icv); +int wep_encrypt(wlandevice_t *wlandev, u8 *buf, u8 *dst, u32 len, int keynum, + u8 *iv, u8 *icv); + +int wlan_setup(wlandevice_t *wlandev); +int wlan_unsetup(wlandevice_t *wlandev); +int register_wlandev(wlandevice_t *wlandev); +int unregister_wlandev(wlandevice_t *wlandev); +void p80211netdev_rx(wlandevice_t *wlandev, struct sk_buff *skb); +void p80211netdev_hwremoved(wlandevice_t *wlandev); #endif diff --git a/drivers/staging/wlan-ng/p80211req.c b/drivers/staging/wlan-ng/p80211req.c index c88156cdf681..c2e95f166828 100644 --- a/drivers/staging/wlan-ng/p80211req.c +++ b/drivers/staging/wlan-ng/p80211req.c @@ -94,7 +94,7 @@ static int p80211req_mibset_mibget(wlandevice_t *wlandev, * Potentially blocks the caller, so it's a good idea to * not call this function from an interrupt context. ----------------------------------------------------------------*/ -int p80211req_dorequest(wlandevice_t * wlandev, u8 * msgbuf) +int p80211req_dorequest(wlandevice_t *wlandev, u8 *msgbuf) { int result = 0; p80211msg_t *msg = (p80211msg_t *) msgbuf; diff --git a/drivers/staging/wlan-ng/p80211req.h b/drivers/staging/wlan-ng/p80211req.h index 5d9176762ba7..a95a45a6814d 100644 --- a/drivers/staging/wlan-ng/p80211req.h +++ b/drivers/staging/wlan-ng/p80211req.h @@ -48,6 +48,6 @@ #ifndef _LINUX_P80211REQ_H #define _LINUX_P80211REQ_H -int p80211req_dorequest(wlandevice_t * wlandev, u8 * msgbuf); +int p80211req_dorequest(wlandevice_t *wlandev, u8 *msgbuf); #endif diff --git a/drivers/staging/wlan-ng/p80211types.h b/drivers/staging/wlan-ng/p80211types.h index 2b83ab0c711b..41a99c59c6c5 100644 --- a/drivers/staging/wlan-ng/p80211types.h +++ b/drivers/staging/wlan-ng/p80211types.h @@ -168,12 +168,12 @@ P80211DID_MASK_ISTABLE, \ P80211DID_LSB_ISTABLE) -#define P80211DID_MKID(s,g,i,n,t,a) (P80211DID_MKSECTION(s) | \ - P80211DID_MKGROUP(g) | \ - P80211DID_MKITEM(i) | \ - P80211DID_MKINDEX(n) | \ - P80211DID_MKISTABLE(t) | \ - (a)) +#define P80211DID_MKID(s, g, i, n, t, a) (P80211DID_MKSECTION(s) | \ + P80211DID_MKGROUP(g) | \ + P80211DID_MKITEM(i) | \ + P80211DID_MKINDEX(n) | \ + P80211DID_MKISTABLE(t) | \ + (a)) #define P80211DID_GET(a, m, l) ((((u32)(a)) >> (l)) & (m)) @@ -340,11 +340,11 @@ struct catlistitem; /* metadata items. Some components may choose to use more, */ /* less or different metadata items. */ -typedef void (*p80211_totext_t) (struct catlistitem *, u32 did, u8 * itembuf, +typedef void (*p80211_totext_t) (struct catlistitem *, u32 did, u8 *itembuf, char *textbuf); -typedef void (*p80211_fromtext_t) (struct catlistitem *, u32 did, u8 * itembuf, +typedef void (*p80211_fromtext_t) (struct catlistitem *, u32 did, u8 *itembuf, char *textbuf); -typedef u32(*p80211_valid_t) (struct catlistitem *, u32 did, u8 * itembuf); +typedef u32(*p80211_valid_t) (struct catlistitem *, u32 did, u8 *itembuf); /*----------------------------------------------------------------*/ /* Enumeration Lists */ diff --git a/drivers/staging/wlan-ng/p80211wext.c b/drivers/staging/wlan-ng/p80211wext.c index cc4b1ca80d6f..9fb9532c72a7 100644 --- a/drivers/staging/wlan-ng/p80211wext.c +++ b/drivers/staging/wlan-ng/p80211wext.c @@ -138,7 +138,7 @@ static int p80211wext_dorequest(wlandevice_t *wlandev, u32 did, u32 data) mibitem.did = did; mibitem.data = data; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); return result; } @@ -175,7 +175,7 @@ static int p80211wext_autojoin(wlandevice_t *wlandev) memcpy(msg.ssid.data.data, ssid, data.length); msg.ssid.data.len = data.length; - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -212,7 +212,7 @@ struct iw_statistics *p80211wext_get_wireless_stats(netdevice_t *dev) if (wlandev->mlmerequest == NULL) return NULL; - retval = wlandev->mlmerequest(wlandev, (p80211msg_t *) & quality); + retval = wlandev->mlmerequest(wlandev, (p80211msg_t *) &quality); wstats->qual.qual = qual_as_percent(quality.link.data); /* overall link quality */ wstats->qual.level = quality.level.data; /* instant signal level */ @@ -273,7 +273,7 @@ static int p80211wext_giwfreq(netdevice_t *dev, memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_dot11phy_dot11PhyDSSSTable_dot11CurrentChannel; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -321,7 +321,7 @@ static int p80211wext_siwfreq(netdevice_t *dev, mibitem.data = p80211_mhz_to_channel(freq->m); memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -403,7 +403,7 @@ static int p80211wext_siwmode(netdevice_t *dev, mibitem.did = DIDmib_p2_p2Static_p2CnfPortType; mibitem.data = (*mode == IW_MODE_ADHOC) ? 0 : 1; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) err = -EFAULT; @@ -553,7 +553,8 @@ static int p80211wext_siwencode(netdevice_t *dev, } /* Check the Key index first. */ - if ((i = (erq->flags & IW_ENCODE_INDEX))) { + i = (erq->flags & IW_ENCODE_INDEX); + if (i) { if ((i < 1) || (i > NUM_WEPKEYS)) { err = -EINVAL; @@ -625,7 +626,7 @@ static int p80211wext_siwencode(netdevice_t *dev, msg.msgcode = DIDmsg_dot11req_mibset; memcpy(&msg.mibattribute.data, &pstr, sizeof(pstr)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -733,7 +734,7 @@ static int p80211wext_siwessid(netdevice_t *dev, msg.ssid.data.len = length; pr_debug("autojoin_ssid for %s \n", essid); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); pr_debug("autojoin_ssid %d\n", result); if (result) { @@ -778,7 +779,7 @@ static int p80211wext_giwrate(netdevice_t *dev, memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_p2_p2MAC_p2CurrentTxRate; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -830,7 +831,7 @@ static int p80211wext_giwrts(netdevice_t *dev, memset(&mibitem, 0, sizeof(mibitem)); mibitem.did = DIDmib_dot11mac_dot11OperationTable_dot11RTSThreshold; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -871,7 +872,7 @@ static int p80211wext_siwrts(netdevice_t *dev, mibitem.data = rts->value; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -897,7 +898,7 @@ static int p80211wext_giwfrag(netdevice_t *dev, mibitem.did = DIDmib_dot11mac_dot11OperationTable_dot11FragmentationThreshold; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -940,7 +941,7 @@ static int p80211wext_siwfrag(netdevice_t *dev, mibitem.data = frag->value; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -975,7 +976,7 @@ static int p80211wext_giwretry(netdevice_t *dev, mibitem.did = DIDmib_dot11mac_dot11OperationTable_dot11ShortRetryLimit; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -989,7 +990,7 @@ static int p80211wext_giwretry(netdevice_t *dev, mibitem.did = DIDmib_dot11mac_dot11OperationTable_dot11LongRetryLimit; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -1004,7 +1005,7 @@ static int p80211wext_giwretry(netdevice_t *dev, DIDmib_dot11mac_dot11OperationTable_dot11MaxTransmitMSDULifetime; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -1067,7 +1068,7 @@ static int p80211wext_siwretry(netdevice_t *dev, mibitem.data = rrq->value /= 1024; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -1081,7 +1082,7 @@ static int p80211wext_siwretry(netdevice_t *dev, memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -1096,7 +1097,7 @@ static int p80211wext_siwretry(netdevice_t *dev, memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -1134,7 +1135,7 @@ static int p80211wext_siwtxpow(netdevice_t *dev, else mibitem.data = rrq->value; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -1162,7 +1163,7 @@ static int p80211wext_giwtxpow(netdevice_t *dev, DIDmib_dot11phy_dot11PhyTxPowerTable_dot11CurrentTxPowerLevel; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -1310,7 +1311,7 @@ static int p80211wext_siwscan(netdevice_t *dev, msg.maxchanneltime.data = 250; msg.minchanneltime.data = 200; - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) err = prism2_result2err(msg.resultcode.data); @@ -1429,7 +1430,7 @@ static int p80211wext_giwscan(netdevice_t *dev, msg.msgcode = DIDmsg_dot11req_scan_results; msg.bssindex.data = i; - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if ((result != 0) || (msg.resultcode.data != P80211ENUM_resultcode_success)) { break; @@ -1504,7 +1505,7 @@ static int p80211wext_set_encodeext(struct net_device *dev, memcpy(wlandev->wep_keys[idx], ext->key, ext->key_len); memset(&msg, 0, sizeof(msg)); - pstr = (p80211item_pstr32_t *) & msg.mibattribute.data; + pstr = (p80211item_pstr32_t *) &msg.mibattribute.data; memcpy(pstr->data.data, ext->key, ext->key_len); pstr->data.len = ext->key_len; switch (idx) { @@ -1528,7 +1529,7 @@ static int p80211wext_set_encodeext(struct net_device *dev, break; } msg.msgcode = DIDmsg_dot11req_mibset; - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); pr_debug("result (%d)\n", result); } return result; @@ -1748,7 +1749,7 @@ struct iw_handler_def p80211wext_handler_def = { .get_wireless_stats = p80211wext_get_wireless_stats }; -int p80211wext_event_associated(wlandevice_t * wlandev, int assoc) +int p80211wext_event_associated(wlandevice_t *wlandev, int assoc) { union iwreq_data data; diff --git a/drivers/staging/wlan-ng/prism2fw.c b/drivers/staging/wlan-ng/prism2fw.c index 5e95c482fb7b..baa20a7c930d 100644 --- a/drivers/staging/wlan-ng/prism2fw.c +++ b/drivers/staging/wlan-ng/prism2fw.c @@ -265,7 +265,7 @@ int prism2_fwapply(const struct ihex_binrec *rfptr, wlandevice_t *wlandev) /* Build the PDA we're going to use. */ if (read_cardpda(&pda, wlandev)) { printk(KERN_ERR "load_cardpda failed, exiting.\n"); - return (1); + return 1; } /* read the card's PRI-SUP */ @@ -287,9 +287,8 @@ int prism2_fwapply(const struct ihex_binrec *rfptr, wlandevice_t *wlandev) /* DIDmsg_dot11req_mibget */ prism2mgmt_mibset_mibget(wlandev, &getmsg); - if (getmsg.resultcode.data != P80211ENUM_resultcode_success) { + if (getmsg.resultcode.data != P80211ENUM_resultcode_success) printk(KERN_ERR "Couldn't fetch PRI-SUP info\n"); - } /* Already in host order */ priid.role = *data++; @@ -302,19 +301,19 @@ int prism2_fwapply(const struct ihex_binrec *rfptr, wlandevice_t *wlandev) result = read_fwfile(rfptr); if (result) { printk(KERN_ERR "Failed to read the data exiting.\n"); - return (1); + return 1; } result = validate_identity(); if (result) { printk(KERN_ERR "Incompatible firmware image.\n"); - return (1); + return 1; } if (startaddr == 0x00000000) { printk(KERN_ERR "Can't RAM download a Flash image!\n"); - return (1); + return 1; } /* Make the image chunks */ @@ -324,20 +323,20 @@ int prism2_fwapply(const struct ihex_binrec *rfptr, wlandevice_t *wlandev) result = plugimage(fchunk, nfchunks, s3plug, ns3plug, &pda); if (result) { printk(KERN_ERR "Failed to plug data.\n"); - return (1); + return 1; } /* Insert any CRCs */ if (crcimage(fchunk, nfchunks, s3crc, ns3crc)) { printk(KERN_ERR "Failed to insert all CRCs\n"); - return (1); + return 1; } /* Write the image */ result = writeimage(wlandev, fchunk, nfchunks); if (result) { printk(KERN_ERR "Failed to ramwrite image data.\n"); - return (1); + return 1; } /* clear any allocated memory */ @@ -435,9 +434,8 @@ void free_chunks(imgchunk_t *fchunk, unsigned int *nfchunks) { int i; for (i = 0; i < *nfchunks; i++) { - if (fchunk[i].data != NULL) { + if (fchunk[i].data != NULL) kfree(fchunk[i].data); - } } *nfchunks = 0; memset(fchunk, 0, sizeof(*fchunk)); @@ -532,7 +530,7 @@ int mkimage(imgchunk_t *clist, unsigned int *ccnt) if (clist[i].data == NULL) { printk(KERN_ERR "failed to allocate image space, exitting.\n"); - return (1); + return 1; } memset(clist[i].data, 0, clist[i].len); pr_debug("chunk[%d]: addr=0x%06x len=%d\n", @@ -546,15 +544,14 @@ int mkimage(imgchunk_t *clist, unsigned int *ccnt) for (j = 0; j < *ccnt; j++) { cstart = clist[j].addr; cend = cstart + clist[j].len - 1; - if (s3start >= cstart && s3end <= cend) { + if (s3start >= cstart && s3end <= cend) break; - } } if (((unsigned int)j) >= (*ccnt)) { printk(KERN_ERR "s3rec(a=0x%06x,l=%d), no chunk match, exiting.\n", s3start, s3data[i].len); - return (1); + return 1; } coffset = s3start - cstart; memcpy(clist[j].data + coffset, s3data[i].data, s3data[i].len); @@ -587,7 +584,7 @@ int mkpdrlist(pda_t *pda) curroff = 0; while (curroff < (HFA384x_PDA_LEN_MAX / 2) && le16_to_cpu(pda16[curroff + 1]) != HFA384x_PDR_END_OF_PDA) { - pda->rec[pda->nrec] = (hfa384x_pdrec_t *) & (pda16[curroff]); + pda->rec[pda->nrec] = (hfa384x_pdrec_t *) &(pda16[curroff]); if (le16_to_cpu(pda->rec[pda->nrec]->code) == HFA384x_PDR_NICID) { memcpy(&nicid, &pda->rec[pda->nrec]->data.nicid, @@ -624,10 +621,10 @@ int mkpdrlist(pda_t *pda) printk(KERN_ERR "no end record found or invalid lengths in " "PDR data, exiting. %x %d\n", curroff, pda->nrec); - return (1); + return 1; } if (le16_to_cpu(pda16[curroff + 1]) == HFA384x_PDR_END_OF_PDA) { - pda->rec[pda->nrec] = (hfa384x_pdrec_t *) & (pda16[curroff]); + pda->rec[pda->nrec] = (hfa384x_pdrec_t *) &(pda16[curroff]); (pda->nrec)++; } return result; @@ -870,7 +867,7 @@ int read_fwfile(const struct ihex_binrec *record) ptr16 = (u16 *) record->data; /* parse what was an S3 srec and put it in the right array */ - switch(addr) { + switch (addr) { case S3ADDR_START: startaddr = *ptr32; pr_debug(" S7 start addr, record=%d " @@ -891,7 +888,7 @@ int read_fwfile(const struct ihex_binrec *record) s3plug[ns3plug].len); ns3plug++; - if ( ns3plug == S3PLUG_MAX ) { + if (ns3plug == S3PLUG_MAX) { printk(KERN_ERR "S3 plugrec limit reached - aborting\n"); return 1; } @@ -908,7 +905,7 @@ int read_fwfile(const struct ihex_binrec *record) s3crc[ns3crc].len, s3crc[ns3crc].dowrite); ns3crc++; - if ( ns3crc == S3CRC_MAX ) { + if (ns3crc == S3CRC_MAX) { printk(KERN_ERR "S3 crcrec limit reached - aborting\n"); return 1; } @@ -922,12 +919,12 @@ int read_fwfile(const struct ihex_binrec *record) rcnt, s3info[ns3info].len, s3info[ns3info].type); - if ( ((s3info[ns3info].len - 1) * sizeof(u16)) > sizeof(s3info[ns3info].info) ) { + if (((s3info[ns3info].len - 1) * sizeof(u16)) > sizeof(s3info[ns3info].info)) { printk(KERN_ERR " S3 inforec length too long - aborting\n"); return 1; } - tmpinfo = (u16*)&(s3info[ns3info].info.version); + tmpinfo = (u16 *)&(s3info[ns3info].info.version); pr_debug(" info="); for (i = 0; i < s3info[ns3info].len - 1; i++) { tmpinfo[i] = *(ptr16 + 2 + i); @@ -936,7 +933,7 @@ int read_fwfile(const struct ihex_binrec *record) pr_debug("\n"); ns3info++; - if ( ns3info == S3INFO_MAX ) { + if (ns3info == S3INFO_MAX) { printk(KERN_ERR "S3 inforec limit reached - aborting\n"); return 1; } @@ -946,7 +943,7 @@ int read_fwfile(const struct ihex_binrec *record) s3data[ns3data].len = len; s3data[ns3data].data = (uint8_t *) record->data; ns3data++; - if ( ns3data == S3DATA_MAX ) { + if (ns3data == S3DATA_MAX) { printk(KERN_ERR "S3 datarec limit reached - aborting\n"); return 1; } @@ -1024,7 +1021,7 @@ int writeimage(wlandevice_t *wlandev, imgchunk_t *fchunk, rstatemsg.enable.data = P80211ENUM_truth_true; rstatemsg.exeaddr.data = startaddr; - msgp = (p80211msg_t *) & rstatemsg; + msgp = (p80211msg_t *) &rstatemsg; result = prism2mgmt_ramdl_state(wlandev, msgp); if (result) { printk(KERN_ERR @@ -1064,7 +1061,7 @@ int writeimage(wlandevice_t *wlandev, imgchunk_t *fchunk, ("Sending xxxdl_write message addr=%06x len=%d.\n", currdaddr, currlen); - msgp = (p80211msg_t *) & rwritemsg; + msgp = (p80211msg_t *) &rwritemsg; result = prism2mgmt_ramdl_write(wlandev, msgp); /* Check the results */ @@ -1091,7 +1088,7 @@ int writeimage(wlandevice_t *wlandev, imgchunk_t *fchunk, rstatemsg.enable.data = P80211ENUM_truth_false; rstatemsg.exeaddr.data = 0; - msgp = (p80211msg_t *) & rstatemsg; + msgp = (p80211msg_t *) &rstatemsg; result = prism2mgmt_ramdl_state(wlandev, msgp); if (result) { printk(KERN_ERR @@ -1162,7 +1159,7 @@ int validate_identity(void) /* SEC compat range */ if ((s3info[i].info.compat.role == 1) && (s3info[i].info.compat.id == 4)) { - + /* FIXME: isn't something missing here? */ } break; @@ -1197,8 +1194,9 @@ int validate_identity(void) pr_debug("Unknown inforec type %d\n", s3info[i].type); } } - // walk through + /* walk through */ - if (trump && (result != 2)) result = 0; + if (trump && (result != 2)) + result = 0; return result; } diff --git a/drivers/staging/wlan-ng/prism2mgmt.c b/drivers/staging/wlan-ng/prism2mgmt.c index 9f7d96cae8e3..eb7469eaf4b1 100644 --- a/drivers/staging/wlan-ng/prism2mgmt.c +++ b/drivers/staging/wlan-ng/prism2mgmt.c @@ -541,7 +541,7 @@ int prism2mgmt_start(wlandevice_t *wlandev, void *msgp) /*** STATION ***/ /* Set the REQUIRED config items */ /* SSID */ - pstr = (p80211pstrd_t *) & (msg->ssid.data); + pstr = (p80211pstrd_t *) &(msg->ssid.data); prism2mgmt_pstr2bytestr(p2bytestr, pstr); result = hfa384x_drvr_setconfig(hw, HFA384x_RID_CNFOWNSSID, bytebuf, HFA384x_RID_CNFOWNSSID_LEN); @@ -1034,7 +1034,7 @@ int prism2mgmt_autojoin(wlandevice_t *wlandev, void *msgp) /* Set the ssid */ memset(bytebuf, 0, 256); - pstr = (p80211pstrd_t *) & (msg->ssid.data); + pstr = (p80211pstrd_t *) &(msg->ssid.data); prism2mgmt_pstr2bytestr(p2bytestr, pstr); result = hfa384x_drvr_setconfig(hw, HFA384x_RID_CNFDESIREDSSID, bytebuf, diff --git a/drivers/staging/wlan-ng/prism2mgmt.h b/drivers/staging/wlan-ng/prism2mgmt.h index bdf2b3e03253..07eecebeb6cc 100644 --- a/drivers/staging/wlan-ng/prism2mgmt.h +++ b/drivers/staging/wlan-ng/prism2mgmt.h @@ -63,43 +63,43 @@ extern int prism2_reset_holdtime; extern int prism2_reset_settletime; -u32 prism2sta_ifstate(wlandevice_t * wlandev, u32 ifstate); +u32 prism2sta_ifstate(wlandevice_t *wlandev, u32 ifstate); -void prism2sta_ev_info(wlandevice_t * wlandev, hfa384x_InfFrame_t * inf); -void prism2sta_ev_txexc(wlandevice_t * wlandev, u16 status); -void prism2sta_ev_tx(wlandevice_t * wlandev, u16 status); -void prism2sta_ev_rx(wlandevice_t * wlandev, struct sk_buff *skb); -void prism2sta_ev_alloc(wlandevice_t * wlandev); +void prism2sta_ev_info(wlandevice_t *wlandev, hfa384x_InfFrame_t *inf); +void prism2sta_ev_txexc(wlandevice_t *wlandev, u16 status); +void prism2sta_ev_tx(wlandevice_t *wlandev, u16 status); +void prism2sta_ev_rx(wlandevice_t *wlandev, struct sk_buff *skb); +void prism2sta_ev_alloc(wlandevice_t *wlandev); -int prism2mgmt_mibset_mibget(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_scan(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_scan_results(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_start(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_wlansniff(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_readpda(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_ramdl_state(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_ramdl_write(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_flashdl_state(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_flashdl_write(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_autojoin(wlandevice_t * wlandev, void *msgp); +int prism2mgmt_mibset_mibget(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_scan(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_scan_results(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_start(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_wlansniff(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_readpda(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_ramdl_state(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_ramdl_write(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_flashdl_state(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_flashdl_write(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_autojoin(wlandevice_t *wlandev, void *msgp); /*--------------------------------------------------------------- * conversion functions going between wlan message data types and * Prism2 data types ---------------------------------------------------------------*/ /* byte area conversion functions*/ -void prism2mgmt_pstr2bytearea(u8 * bytearea, p80211pstrd_t * pstr); -void prism2mgmt_bytearea2pstr(u8 * bytearea, p80211pstrd_t * pstr, int len); +void prism2mgmt_pstr2bytearea(u8 *bytearea, p80211pstrd_t *pstr); +void prism2mgmt_bytearea2pstr(u8 *bytearea, p80211pstrd_t *pstr, int len); /* byte string conversion functions*/ -void prism2mgmt_pstr2bytestr(hfa384x_bytestr_t * bytestr, p80211pstrd_t * pstr); -void prism2mgmt_bytestr2pstr(hfa384x_bytestr_t * bytestr, p80211pstrd_t * pstr); +void prism2mgmt_pstr2bytestr(hfa384x_bytestr_t *bytestr, p80211pstrd_t *pstr); +void prism2mgmt_bytestr2pstr(hfa384x_bytestr_t *bytestr, p80211pstrd_t *pstr); /* functions to convert Group Addresses */ -void prism2mgmt_get_grpaddr(u32 did, p80211pstrd_t * pstr, hfa384x_t * priv); +void prism2mgmt_get_grpaddr(u32 did, p80211pstrd_t *pstr, hfa384x_t *priv); int prism2mgmt_set_grpaddr(u32 did, - u8 * prism2buf, p80211pstrd_t * pstr, - hfa384x_t * priv); + u8 *prism2buf, p80211pstrd_t *pstr, + hfa384x_t *priv); int prism2mgmt_get_grpaddr_index(u32 did); void prism2sta_processing_defer(struct work_struct *data); diff --git a/drivers/staging/wlan-ng/prism2mib.c b/drivers/staging/wlan-ng/prism2mib.c index 2fff0a110bcb..10b671e973a5 100644 --- a/drivers/staging/wlan-ng/prism2mib.c +++ b/drivers/staging/wlan-ng/prism2mib.c @@ -114,7 +114,7 @@ static int prism2mib_flag(mibrec_t *mib, static int prism2mib_wepdefaultkey(mibrec_t *mib, int isget, - wlandevice_t * wlandev, + wlandevice_t *wlandev, hfa384x_t *hw, p80211msg_dot11req_mibset_t *msg, void *data); @@ -726,7 +726,7 @@ static int prism2mib_priv(mibrec_t *mib, if (isget) { hfa384x_drvr_getconfig(hw, HFA384x_RID_CNFWPADATA, - (u8 *) & wpa, + (u8 *) &wpa, sizeof(wpa)); pstr->len = le16_to_cpu(wpa.datalen); memcpy(pstr->data, wpa.data, pstr->len); @@ -737,7 +737,7 @@ static int prism2mib_priv(mibrec_t *mib, result = hfa384x_drvr_setconfig(hw, HFA384x_RID_CNFWPADATA, - (u8 *) & wpa, + (u8 *) &wpa, sizeof(wpa)); } break; diff --git a/drivers/staging/wlan-ng/prism2sta.c b/drivers/staging/wlan-ng/prism2sta.c index 50f301d65212..2da405490c65 100644 --- a/drivers/staging/wlan-ng/prism2sta.c +++ b/drivers/staging/wlan-ng/prism2sta.c @@ -1023,13 +1023,13 @@ static void prism2sta_inf_tallies(wlandevice_t *wlandev, cnt = sizeof(hfa384x_CommTallies32_t) / sizeof(u32); if (inf->framelen > 22) { - dst = (u32 *) & hw->tallies; - src32 = (u32 *) & inf->info.commtallies32; + dst = (u32 *) &hw->tallies; + src32 = (u32 *) &inf->info.commtallies32; for (i = 0; i < cnt; i++, dst++, src32++) *dst += le32_to_cpu(*src32); } else { - dst = (u32 *) & hw->tallies; - src16 = (u16 *) & inf->info.commtallies16; + dst = (u32 *) &hw->tallies; + src16 = (u16 *) &inf->info.commtallies16; for (i = 0; i < cnt; i++, dst++, src16++) *dst += le16_to_cpu(*src16); } @@ -1280,7 +1280,7 @@ void prism2sta_processing_defer(struct work_struct *data) HFA384x_RID_CURRENTSSID, result); goto failed; } - prism2mgmt_bytestr2pstr((hfa384x_bytestr_t *) & ssid, + prism2mgmt_bytestr2pstr((hfa384x_bytestr_t *) &ssid, (p80211pstrd_t *) & wlandev->ssid); @@ -1368,8 +1368,8 @@ void prism2sta_processing_defer(struct work_struct *data) HFA384x_RID_CURRENTSSID, result); goto failed; } - prism2mgmt_bytestr2pstr((hfa384x_bytestr_t *) & ssid, - (p80211pstrd_t *) & wlandev->ssid); + prism2mgmt_bytestr2pstr((hfa384x_bytestr_t *) &ssid, + (p80211pstrd_t *) &wlandev->ssid); hw->link_status = HFA384x_LINK_CONNECTED; netif_carrier_on(wlandev->netdev); @@ -2028,8 +2028,8 @@ void prism2sta_commsqual_defer(struct work_struct *data) HFA384x_RID_CURRENTSSID, result); goto done; } - prism2mgmt_bytestr2pstr((hfa384x_bytestr_t *) & ssid, - (p80211pstrd_t *) & wlandev->ssid); + prism2mgmt_bytestr2pstr((hfa384x_bytestr_t *) &ssid, + (p80211pstrd_t *) &wlandev->ssid); /* Reschedule timer */ mod_timer(&hw->commsqual_timer, jiffies + HZ); -- cgit v1.2.3 From b1b7621b08e49638aa65b5f67cdd35478f00a4c4 Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Sun, 14 Feb 2010 21:55:16 -0600 Subject: staging: r8187se: Remove write_phy routine Remove a routine that is not used. Signed-off-by: Larry Finger Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8187se/r8180_core.c | 37 ---------------------------------- 1 file changed, 37 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8187se/r8180_core.c b/drivers/staging/rtl8187se/r8180_core.c index 0b7ec6b949b4..5d0bffc27f7c 100644 --- a/drivers/staging/rtl8187se/r8180_core.c +++ b/drivers/staging/rtl8187se/r8180_core.c @@ -3165,43 +3165,6 @@ void write_phy_cck (struct net_device *dev, u8 adr, u32 data) rtl8185_write_phy(dev, adr, data | 0x10000); } -/* 70*3 = 210 ms - * I hope this is enougth - */ -#define MAX_PHY 70 -void write_phy(struct net_device *dev, u8 adr, u8 data) -{ - u32 phy; - int i; - - phy = 0xff0000; - phy |= adr; - phy |= 0x80; /* this should enable writing */ - phy |= (data<<8); - - //PHY_ADR, PHY_R and PHY_W are contig and treated as one dword - write_nic_dword(dev,PHY_ADR, phy); - - phy= 0xffff00; - phy |= adr; - - write_nic_dword(dev,PHY_ADR, phy); - for(i=0;i> 16; - if(phy == data){ //SUCCESS! - force_pci_posting(dev); - mdelay(3); //random value - return; - }else{ - force_pci_posting(dev); - mdelay(3); //random value - } - } - DMESGW ("Phy writing %x %x failed!", adr,data); -} - void rtl8185_set_rate(struct net_device *dev) { int i; -- cgit v1.2.3 From 8daba6b94dce76254b10de0a9a777f792a120322 Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Sun, 14 Feb 2010 22:04:56 -0600 Subject: Staging: r8187se: Remove two private variables that have a fixed value For the RTL8187SE, the variable priv->rf_chip is always RF_ZEBRA4 and priv->RegThreeWireMode is always HW_THREE_WIRE_SI. Remove these 2 variables. Signed-off-by: Larry Finger Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8187se/r8180.h | 4 - drivers/staging/rtl8187se/r8180_core.c | 90 ------- drivers/staging/rtl8187se/r8180_dm.c | 67 ++--- drivers/staging/rtl8187se/r8180_rtl8225z2.c | 232 ++++++++---------- drivers/staging/rtl8187se/r8185b_init.c | 366 ++++++---------------------- 5 files changed, 191 insertions(+), 568 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8187se/r8180.h b/drivers/staging/rtl8187se/r8180.h index ce828885b64f..d15bdf64efd0 100644 --- a/drivers/staging/rtl8187se/r8180.h +++ b/drivers/staging/rtl8187se/r8180.h @@ -366,7 +366,6 @@ typedef struct r8180_priv short diversity; u8 cs_treshold; short rcr_csense; - short rf_chip; u32 key0[4]; short (*rf_set_sens)(struct net_device *dev,short sens); void (*rf_set_chan)(struct net_device *dev,short ch); @@ -479,9 +478,6 @@ typedef struct r8180_priv u8 retry_rts; u16 rts; -//add for RF power on power off by lizhaoming 080512 - u8 RegThreeWireMode; // See "Three wire mode" defined above, 2006.05.31, by rcnjko. - //by amy for led LED_STRATEGY_8185 LedStrategy; //by amy for led diff --git a/drivers/staging/rtl8187se/r8180_core.c b/drivers/staging/rtl8187se/r8180_core.c index 5d0bffc27f7c..b49eed81debc 100644 --- a/drivers/staging/rtl8187se/r8180_core.c +++ b/drivers/staging/rtl8187se/r8180_core.c @@ -663,11 +663,8 @@ unsigned char STRENGTH_MAP[] = { void rtl8180_RSSI_calc(struct net_device *dev, u8 *rssi, u8 *qual) { - struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); u32 temp; u32 temp2; - u32 temp3; - u32 lsb; u32 q; u32 orig_qual; u8 _rssi; @@ -689,88 +686,6 @@ void rtl8180_RSSI_calc(struct net_device *dev, u8 *rssi, u8 *qual) *qual = temp; temp2 = *rssi; - switch(priv->rf_chip){ - case RFCHIPID_RFMD: - lsb = temp2 & 1; - temp2 &= 0x7e; - if ( !lsb || !(temp2 <= 0x3c) ) { - temp2 = 0x64; - } else { - temp2 = 100 * temp2 / 0x3c; - } - *rssi = temp2 & 0xff; - _rssi = temp2 & 0xff; - break; - case RFCHIPID_INTERSIL: - lsb = temp2; - temp2 &= 0xfffffffe; - temp2 *= 251; - temp3 = temp2; - temp2 <<= 6; - temp3 += temp2; - temp3 <<= 1; - temp2 = 0x4950df; - temp2 -= temp3; - lsb &= 1; - if ( temp2 <= 0x3e0000 ) { - if ( temp2 < 0xffef0000 ) - temp2 = 0xffef0000; - } else { - temp2 = 0x3e0000; - } - if ( !lsb ) { - temp2 -= 0xf0000; - } else { - temp2 += 0xf0000; - } - - temp3 = 0x4d0000; - temp3 -= temp2; - temp3 *= 100; - temp3 = temp3 / 0x6d; - temp3 >>= 0x10; - _rssi = temp3 & 0xff; - *rssi = temp3 & 0xff; - break; - case RFCHIPID_GCT: - lsb = temp2 & 1; - temp2 &= 0x7e; - if ( ! lsb || !(temp2 <= 0x3c) ){ - temp2 = 0x64; - } else { - temp2 = (100 * temp2) / 0x3c; - } - *rssi = temp2 & 0xff; - _rssi = temp2 & 0xff; - break; - case RFCHIPID_PHILIPS: - if( orig_qual <= 0x4e ){ - _rssi = STRENGTH_MAP[orig_qual]; - *rssi = _rssi; - } else { - orig_qual -= 0x80; - if ( !orig_qual ){ - _rssi = 1; - *rssi = 1; - } else { - _rssi = 0x32; - *rssi = 0x32; - } - } - break; - case RFCHIPID_MAXIM: - lsb = temp2 & 1; - temp2 &= 0x7e; - temp2 >>= 1; - temp2 += 0x42; - if( lsb != 0 ){ - temp2 += 0xa; - } - *rssi = temp2 & 0xff; - _rssi = temp2 & 0xff; - break; - } - if ( _rssi < 0x64 ){ if ( _rssi == 0 ) { *rssi = 1; @@ -2707,8 +2622,6 @@ short rtl8180_init(struct net_device *dev) priv->txbeaconcount = 2; priv->rx_skb_complete = 1; - priv->RegThreeWireMode = HW_THREE_WIRE_SI; - priv->RFChangeInProgress = false; priv->SetRFPowerStateInProgress = false; priv->RFProgType = 0; @@ -2999,9 +2912,6 @@ short rtl8180_init(struct net_device *dev) priv->cs_treshold = (eeprom_val & 0xff00) >> 8; eeprom_93cx6_read(&eeprom, RFCHIPID, &eeprom_val); - priv->rf_chip = 0xff & eeprom_val; - - priv->rf_chip = RF_ZEBRA4; priv->rf_sleep = rtl8225z4_rf_sleep; priv->rf_wakeup = rtl8225z4_rf_wakeup; DMESGW("**PLEASE** REPORT SUCCESSFUL/UNSUCCESSFUL TO Realtek!"); diff --git a/drivers/staging/rtl8187se/r8180_dm.c b/drivers/staging/rtl8187se/r8180_dm.c index cbca58db85e1..fc4907839c58 100644 --- a/drivers/staging/rtl8187se/r8180_dm.c +++ b/drivers/staging/rtl8187se/r8180_dm.c @@ -282,30 +282,13 @@ DIG_Zebra( // Dispatch DIG implementation according to RF. // void -DynamicInitGain( - struct net_device *dev - ) +DynamicInitGain(struct net_device *dev) { - struct r8180_priv *priv = ieee80211_priv(dev); - - switch(priv->rf_chip) - { - case RF_ZEBRA2: // [AnnieWorkaround] For Zebra2, 2005-08-01. - case RF_ZEBRA4: - DIG_Zebra( dev ); - break; - - default: - printk("DynamicInitGain(): unknown RFChipID(%d) !!!\n", priv->rf_chip); - break; - } + DIG_Zebra(dev); } void rtl8180_hw_dig_wq (struct work_struct *work) { -// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq); -// struct ieee80211_device * ieee = (struct ieee80211_device*) -// container_of(work, struct ieee80211_device, watch_dog_wq); struct delayed_work *dwork = to_delayed_work(work); struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_dig_wq); struct net_device *dev = ieee->dev; @@ -1310,44 +1293,24 @@ SetAntenna8185( switch(u1bAntennaIndex) { case 0: - switch(priv->rf_chip) - { - case RF_ZEBRA2: - case RF_ZEBRA4: - // Mac register, main antenna - write_nic_byte(dev, ANTSEL, 0x03); - //base band - write_phy_cck(dev,0x11, 0x9b); // Config CCK RX antenna. - write_phy_ofdm(dev, 0x0d, 0x5c); // Config OFDM RX antenna. - - - bAntennaSwitched = true; - break; + /* Mac register, main antenna */ + write_nic_byte(dev, ANTSEL, 0x03); + /* base band */ + write_phy_cck(dev, 0x11, 0x9b); /* Config CCK RX antenna. */ + write_phy_ofdm(dev, 0x0d, 0x5c); /* Config OFDM RX antenna. */ - default: - printk("SetAntenna8185: unknown RFChipID(%d)\n", priv->rf_chip); - break; - } + bAntennaSwitched = true; break; case 1: - switch(priv->rf_chip) - { - case RF_ZEBRA2: - case RF_ZEBRA4: - // Mac register, aux antenna - write_nic_byte(dev, ANTSEL, 0x00); - //base band - write_phy_cck(dev, 0x11, 0xbb); // Config CCK RX antenna. - write_phy_ofdm(dev, 0x0d, 0x54); // Config OFDM RX antenna. - - bAntennaSwitched = true; - break; + /* Mac register, aux antenna */ + write_nic_byte(dev, ANTSEL, 0x00); + /* base band */ + write_phy_cck(dev, 0x11, 0xbb); /* Config CCK RX antenna. */ + write_phy_ofdm(dev, 0x0d, 0x54); /* Config OFDM RX antenna. */ + + bAntennaSwitched = true; - default: - printk("SetAntenna8185: unknown RFChipID(%d)\n", priv->rf_chip); - break; - } break; default: diff --git a/drivers/staging/rtl8187se/r8180_rtl8225z2.c b/drivers/staging/rtl8187se/r8180_rtl8225z2.c index afe10f0b75a8..6edf5a46fa40 100644 --- a/drivers/staging/rtl8187se/r8180_rtl8225z2.c +++ b/drivers/staging/rtl8187se/r8180_rtl8225z2.c @@ -854,134 +854,48 @@ bool SetZebraRFPowerState8185(struct net_device *dev, btConfig3 = read_nic_byte(dev, CONFIG3); write_nic_byte(dev, CONFIG3, (btConfig3 | CONFIG3_PARM_En)); - switch (priv->rf_chip) { - case RF_ZEBRA2: - switch (eRFPowerState) { - case eRfOn: - RF_WriteReg(dev,0x4,0x9FF); + switch (eRFPowerState) { + case eRfOn: + write_nic_word(dev, 0x37C, 0x00EC); - write_nic_dword(dev, ANAPARAM, ANAPARM_ON); - write_nic_dword(dev, ANAPARAM2, ANAPARM2_ON); + /* turn on AFE */ + write_nic_byte(dev, 0x54, 0x00); + write_nic_byte(dev, 0x62, 0x00); - write_nic_byte(dev, CONFIG4, priv->RFProgType); + /* turn on RF */ + RF_WriteReg(dev, 0x0, 0x009f); udelay(500); + RF_WriteReg(dev, 0x4, 0x0972); udelay(500); - /* turn on CCK and OFDM */ - u1bTmp = read_nic_byte(dev, 0x24E); - write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6)))); - break; - case eRfSleep: - break; - case eRfOff: - break; - default: - bResult = false; - break; - } - break; - case RF_ZEBRA4: - switch (eRFPowerState) { - case eRfOn: - write_nic_word(dev, 0x37C, 0x00EC); - - /* turn on AFE */ - write_nic_byte(dev, 0x54, 0x00); - write_nic_byte(dev, 0x62, 0x00); - - /* turn on RF */ - RF_WriteReg(dev, 0x0, 0x009f); udelay(500); - RF_WriteReg(dev, 0x4, 0x0972); udelay(500); - - /* turn on RF again */ - RF_WriteReg(dev, 0x0, 0x009f); udelay(500); - RF_WriteReg(dev, 0x4, 0x0972); udelay(500); + /* turn on RF again */ + RF_WriteReg(dev, 0x0, 0x009f); udelay(500); + RF_WriteReg(dev, 0x4, 0x0972); udelay(500); - /* turn on BB */ - write_phy_ofdm(dev,0x10,0x40); - write_phy_ofdm(dev,0x12,0x40); - - /* Avoid power down at init time. */ - write_nic_byte(dev, CONFIG4, priv->RFProgType); - - u1bTmp = read_nic_byte(dev, 0x24E); - write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6)))); - break; - case eRfSleep: - for (QueueID = 0, i = 0; QueueID < 6;) { - if (get_curr_tx_free_desc(dev, QueueID) == priv->txringcount) { - QueueID++; - continue; - } else { - priv->TxPollingTimes ++; - if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) { - bActionAllowed = false; - break; - } else - udelay(10); - } - } + /* turn on BB */ + write_phy_ofdm(dev, 0x10, 0x40); + write_phy_ofdm(dev, 0x12, 0x40); - if (bActionAllowed) { - /* turn off BB RXIQ matrix to cut off rx signal */ - write_phy_ofdm(dev, 0x10, 0x00); - write_phy_ofdm(dev, 0x12, 0x00); - - /* turn off RF */ - RF_WriteReg(dev, 0x4, 0x0000); - RF_WriteReg(dev, 0x0, 0x0000); - - /* turn off AFE except PLL */ - write_nic_byte(dev, 0x62, 0xff); - write_nic_byte(dev, 0x54, 0xec); - - mdelay(1); - - { - int i = 0; - while (true) { - u8 tmp24F = read_nic_byte(dev, 0x24f); - - if ((tmp24F == 0x01) || (tmp24F == 0x09)) { - bTurnOffBB = true; - break; - } else { - udelay(10); - i++; - priv->TxPollingTimes++; - - if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) { - bTurnOffBB = false; - break; - } else - udelay(10); - } - } - } - - if (bTurnOffBB) { - /* turn off BB */ - u1bTmp = read_nic_byte(dev, 0x24E); - write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6)); - - /* turn off AFE PLL */ - write_nic_byte(dev, 0x54, 0xFC); - write_nic_word(dev, 0x37C, 0x00FC); - } - } - break; - case eRfOff: - for (QueueID = 0, i = 0; QueueID < 6;) { - if (get_curr_tx_free_desc(dev, QueueID) == priv->txringcount) { - QueueID++; - continue; - } else { - udelay(10); - i++; - } + /* Avoid power down at init time. */ + write_nic_byte(dev, CONFIG4, priv->RFProgType); - if (i >= MAX_DOZE_WAITING_TIMES_85B) + u1bTmp = read_nic_byte(dev, 0x24E); + write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6)))); + break; + case eRfSleep: + for (QueueID = 0, i = 0; QueueID < 6;) { + if (get_curr_tx_free_desc(dev, QueueID) == priv->txringcount) { + QueueID++; + continue; + } else { + priv->TxPollingTimes++; + if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) { + bActionAllowed = false; break; + } else + udelay(10); } + } + if (bActionAllowed) { /* turn off BB RXIQ matrix to cut off rx signal */ write_phy_ofdm(dev, 0x10, 0x00); write_phy_ofdm(dev, 0x12, 0x00); @@ -998,22 +912,23 @@ bool SetZebraRFPowerState8185(struct net_device *dev, { int i = 0; - - while (true) - { + while (true) { u8 tmp24F = read_nic_byte(dev, 0x24f); if ((tmp24F == 0x01) || (tmp24F == 0x09)) { bTurnOffBB = true; break; } else { - bTurnOffBB = false; udelay(10); i++; - } + priv->TxPollingTimes++; - if (i > MAX_POLLING_24F_TIMES_87SE) - break; + if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) { + bTurnOffBB = false; + break; + } else + udelay(10); + } } } @@ -1022,15 +937,68 @@ bool SetZebraRFPowerState8185(struct net_device *dev, u1bTmp = read_nic_byte(dev, 0x24E); write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6)); - /* turn off AFE PLL (80M) */ + /* turn off AFE PLL */ write_nic_byte(dev, 0x54, 0xFC); write_nic_word(dev, 0x37C, 0x00FC); } - break; - default: - bResult = false; - printk("SetZebraRFPowerState8185(): unknown state to set: 0x%X!!!\n", eRFPowerState); - break; + } + break; + case eRfOff: + for (QueueID = 0, i = 0; QueueID < 6;) { + if (get_curr_tx_free_desc(dev, QueueID) == priv->txringcount) { + QueueID++; + continue; + } else { + udelay(10); + i++; + } + + if (i >= MAX_DOZE_WAITING_TIMES_85B) + break; + } + + /* turn off BB RXIQ matrix to cut off rx signal */ + write_phy_ofdm(dev, 0x10, 0x00); + write_phy_ofdm(dev, 0x12, 0x00); + + /* turn off RF */ + RF_WriteReg(dev, 0x4, 0x0000); + RF_WriteReg(dev, 0x0, 0x0000); + + /* turn off AFE except PLL */ + write_nic_byte(dev, 0x62, 0xff); + write_nic_byte(dev, 0x54, 0xec); + + mdelay(1); + + { + int i = 0; + + while (true) { + u8 tmp24F = read_nic_byte(dev, 0x24f); + + if ((tmp24F == 0x01) || (tmp24F == 0x09)) { + bTurnOffBB = true; + break; + } else { + bTurnOffBB = false; + udelay(10); + i++; + } + + if (i > MAX_POLLING_24F_TIMES_87SE) + break; + } + } + + if (bTurnOffBB) { + /* turn off BB */ + u1bTmp = read_nic_byte(dev, 0x24E); + write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6)); + + /* turn off AFE PLL (80M) */ + write_nic_byte(dev, 0x54, 0xFC); + write_nic_word(dev, 0x37C, 0x00FC); } break; } diff --git a/drivers/staging/rtl8187se/r8185b_init.c b/drivers/staging/rtl8187se/r8185b_init.c index 50309f2da9c1..19b5c9f90b51 100644 --- a/drivers/staging/rtl8187se/r8185b_init.c +++ b/drivers/staging/rtl8187se/r8185b_init.c @@ -238,22 +238,9 @@ PlatformIORead4Byte( return data; } -void -SetOutputEnableOfRfPins( - struct net_device *dev - ) +void SetOutputEnableOfRfPins(struct net_device *dev) { - struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); - - switch(priv->rf_chip) - { - case RFCHIPID_RTL8225: - case RF_ZEBRA2: - case RF_ZEBRA4: - write_nic_word(dev, RFPinsEnable, 0x1bff); - //write_nic_word(dev, RFPinsEnable, 0x1fff); - break; - } + write_nic_word(dev, RFPinsEnable, 0x1bff); } void @@ -603,111 +590,27 @@ HwThreeWire( void -RF_WriteReg( - struct net_device *dev, - u8 offset, - u32 data - ) +RF_WriteReg(struct net_device *dev, u8 offset, u32 data) { - //RFReg reg; - u32 data2Write; - u8 len; - u8 low2high; - //u32 RF_Read = 0; - struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); - + u32 data2Write; + u8 len; - switch(priv->rf_chip) - { - case RFCHIPID_RTL8225: - case RF_ZEBRA2: // Annie 2006-05-12. - case RF_ZEBRA4: //by amy - switch(priv->RegThreeWireMode) - { - case SW_THREE_WIRE: - { // Perform SW 3-wire programming by driver. - data2Write = (data << 4) | (u32)(offset & 0x0f); - len = 16; - low2high = 0; - ZEBRA_RFSerialWrite(dev, data2Write, len, low2high); - } - break; - - case HW_THREE_WIRE: - { // Pure HW 3-wire. - data2Write = (data << 4) | (u32)(offset & 0x0f); - len = 16; - HwThreeWire( - dev, - (u8 *)(&data2Write), // pDataBuf, - len, // nDataBufBitCnt, - 0, // bHold, - 1); // bWrite - } - break; - case HW_THREE_WIRE_PI: //Parallel Interface - { // Pure HW 3-wire. - data2Write = (data << 4) | (u32)(offset & 0x0f); - len = 16; - HwHSSIThreeWire( - dev, - (u8*)(&data2Write), // pDataBuf, - len, // nDataBufBitCnt, - 0, // bSI - 1); // bWrite - - //printk("33333\n"); - } - break; + /* Pure HW 3-wire. */ + data2Write = (data << 4) | (u32)(offset & 0x0f); + len = 16; - case HW_THREE_WIRE_SI: //Serial Interface - { // Pure HW 3-wire. - data2Write = (data << 4) | (u32)(offset & 0x0f); - len = 16; -// printk(" enter ZEBRA_RFSerialWrite\n "); -// low2high = 0; -// ZEBRA_RFSerialWrite(dev, data2Write, len, low2high); - - HwHSSIThreeWire( - dev, - (u8*)(&data2Write), // pDataBuf, - len, // nDataBufBitCnt, - 1, // bSI - 1); // bWrite - -// printk(" exit ZEBRA_RFSerialWrite\n "); - } - break; - - - default: - DMESGE("RF_WriteReg(): invalid RegThreeWireMode(%d) !!!", priv->RegThreeWireMode); - break; - } - break; - - default: - DMESGE("RF_WriteReg(): unknown RFChipID: %#X", priv->rf_chip); - break; - } + HwHSSIThreeWire(dev, (u8 *)(&data2Write), len, 1, 1); } - void -ZEBRA_RFSerialRead( - struct net_device *dev, - u32 data2Write, - u8 wLength, - u32 *data2Read, - u8 rLength, - u8 low2high - ) +ZEBRA_RFSerialRead(struct net_device *dev, u32 data2Write, u8 wLength, + u32 *data2Read, u8 rLength, u8 low2high) { ThreeWireReg twreg; - int i; - u16 oval,oval2,oval3,tmp, wReg80; - u32 mask; - u8 u1bTmp; + int i; + u16 oval, oval2, oval3, tmp, wReg80; + u32 mask; + u8 u1bTmp; ThreeWireReg tdata; //PHAL_DATA_8187 pHalData = GetHalData8187(pAdapter); { // RTL8187S HSSI Read/Write Function @@ -818,71 +721,16 @@ ZEBRA_RFSerialRead( } -u32 -RF_ReadReg( - struct net_device *dev, - u8 offset - ) +u32 RF_ReadReg(struct net_device *dev, u8 offset) { - struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); - u32 data2Write; - u8 wlen; - u8 rlen; - u8 low2high; - u32 dataRead; + u32 data2Write; + u8 wlen; + u32 dataRead; - switch(priv->rf_chip) - { - case RFCHIPID_RTL8225: - case RF_ZEBRA2: - case RF_ZEBRA4: - switch(priv->RegThreeWireMode) - { - case HW_THREE_WIRE_PI: // For 87S Parallel Interface. - { - data2Write = ((u32)(offset&0x0f)); - wlen=16; - HwHSSIThreeWire( - dev, - (u8*)(&data2Write), // pDataBuf, - wlen, // nDataBufBitCnt, - 0, // bSI - 0); // bWrite - dataRead= data2Write; - } - break; - - case HW_THREE_WIRE_SI: // For 87S Serial Interface. - { - data2Write = ((u32)(offset&0x0f)) ; - wlen=16; - HwHSSIThreeWire( - dev, - (u8*)(&data2Write), // pDataBuf, - wlen, // nDataBufBitCnt, - 1, // bSI - 0 // bWrite - ); - dataRead= data2Write; - } - break; - - // Perform SW 3-wire programming by driver. - default: - { - data2Write = ((u32)(offset&0x1f)) << 27; // For Zebra E-cut. 2005.04.11, by rcnjko. - wlen = 6; - rlen = 12; - low2high = 0; - ZEBRA_RFSerialRead(dev, data2Write, wlen,&dataRead,rlen, low2high); - } - break; - } - break; - default: - dataRead = 0; - break; - } + data2Write = ((u32)(offset & 0x0f)); + wlen = 16; + HwHSSIThreeWire(dev, (u8 *)(&data2Write), wlen, 1, 0); + dataRead = data2Write; return dataRead; } @@ -1291,81 +1139,59 @@ UpdateInitialGain( return; } - switch(priv->rf_chip) - { - case RF_ZEBRA4: - // Dynamic set initial gain, follow 87B - switch(priv->InitialGain) - { - case 1: //m861dBm - //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm \n"); - write_phy_ofdm(dev, 0x17, 0x26); mdelay(1); - write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); - write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1); - break; - - case 2: //m862dBm - //DMESG("RTL8187 + 8225 Initial Gain State 2: -82 dBm \n"); - write_phy_ofdm(dev, 0x17, 0x36); mdelay(1); - write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); - write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1); - break; - - case 3: //m863dBm - //DMESG("RTL8187 + 8225 Initial Gain State 3: -82 dBm \n"); - write_phy_ofdm(dev, 0x17, 0x36); mdelay(1); - write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); - write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1); - break; - - case 4: //m864dBm - //DMESG("RTL8187 + 8225 Initial Gain State 4: -78 dBm \n"); - write_phy_ofdm(dev, 0x17, 0x46); mdelay(1); - write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); - write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1); - break; + switch (priv->InitialGain) { + case 1: /* m861dBm */ + write_phy_ofdm(dev, 0x17, 0x26); mdelay(1); + write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); + write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1); + break; - case 5: //m82dBm - //DMESG("RTL8187 + 8225 Initial Gain State 5: -74 dBm \n"); - write_phy_ofdm(dev, 0x17, 0x46); mdelay(1); - write_phy_ofdm(dev, 0x24, 0x96); mdelay(1); - write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1); - break; + case 2: /* m862dBm */ + write_phy_ofdm(dev, 0x17, 0x36); mdelay(1); + write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); + write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1); + break; - case 6: //m78dBm - //DMESG ("RTL8187 + 8225 Initial Gain State 6: -70 dBm \n"); - write_phy_ofdm(dev, 0x17, 0x56); mdelay(1); - write_phy_ofdm(dev, 0x24, 0x96); mdelay(1); - write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1); - break; + case 3: /* m863dBm */ + write_phy_ofdm(dev, 0x17, 0x36); mdelay(1); + write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); + write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1); + break; - case 7: //m74dBm - //DMESG("RTL8187 + 8225 Initial Gain State 7: -66 dBm \n"); - write_phy_ofdm(dev, 0x17, 0x56); mdelay(1); - write_phy_ofdm(dev, 0x24, 0xa6); mdelay(1); - write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1); - break; + case 4: /* m864dBm */ + write_phy_ofdm(dev, 0x17, 0x46); mdelay(1); + write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); + write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1); + break; - case 8: - //DMESG("RTL8187 + 8225 Initial Gain State 8:\n"); - write_phy_ofdm(dev, 0x17, 0x66); mdelay(1); - write_phy_ofdm(dev, 0x24, 0xb6); mdelay(1); - write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1); - break; + case 5: /* m82dBm */ + write_phy_ofdm(dev, 0x17, 0x46); mdelay(1); + write_phy_ofdm(dev, 0x24, 0x96); mdelay(1); + write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1); + break; + case 6: /* m78dBm */ + write_phy_ofdm(dev, 0x17, 0x56); mdelay(1); + write_phy_ofdm(dev, 0x24, 0x96); mdelay(1); + write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1); + break; - default: //MP - //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm (default)\n"); - write_phy_ofdm(dev, 0x17, 0x26); mdelay(1); - write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); - write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1); - break; - } + case 7: /* m74dBm */ + write_phy_ofdm(dev, 0x17, 0x56); mdelay(1); + write_phy_ofdm(dev, 0x24, 0xa6); mdelay(1); + write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1); break; + case 8: + write_phy_ofdm(dev, 0x17, 0x66); mdelay(1); + write_phy_ofdm(dev, 0x24, 0xb6); mdelay(1); + write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1); + break; - default: - DMESG("UpdateInitialGain(): unknown RFChipID: %#X\n", priv->rf_chip); + default: /* MP */ + write_phy_ofdm(dev, 0x17, 0x26); mdelay(1); + write_phy_ofdm(dev, 0x24, 0x86); mdelay(1); + write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1); break; } } @@ -1397,14 +1223,8 @@ PhyConfig8185( struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); write_nic_dword(dev, RCR, priv->ReceiveConfig); priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03; - // RF config - switch(priv->rf_chip) - { - case RF_ZEBRA2: - case RF_ZEBRA4: - ZEBRA_Config_85BASIC_HardCode( dev); - break; - } + /* RF config */ + ZEBRA_Config_85BASIC_HardCode(dev); //{by amy 080312 // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06. if(priv->bDigMechanism) @@ -1614,19 +1434,8 @@ GetSupportedWirelessMode8185( ) { u8 btSupportedWirelessMode = 0; - struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); - - switch(priv->rf_chip) - { - case RF_ZEBRA2: - case RF_ZEBRA4: - btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G); - break; - default: - btSupportedWirelessMode = WIRELESS_MODE_B; - break; - } + btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G); return btSupportedWirelessMode; } @@ -1881,23 +1690,11 @@ ActSetWirelessMode8185( } - // 2. Swtich band: RF or BB specific actions, - // for example, refresh tables in omc8255, or change initial gain if necessary. - switch(priv->rf_chip) - { - case RF_ZEBRA2: - case RF_ZEBRA4: - { - // Nothing to do for Zebra to switch band. - // Update current wireless mode if we swtich to specified band successfully. - ieee->mode = (WIRELESS_MODE)btWirelessMode; - } - break; - - default: - DMESGW("ActSetWirelessMode8185(): unsupported RF: 0x%X !!!\n", priv->rf_chip); - break; - } + /* 2. Swtich band: RF or BB specific actions, + * for example, refresh tables in omc8255, or change initial gain if necessary. + * Nothing to do for Zebra to switch band. + * Update current wireless mode if we swtich to specified band successfully. */ + ieee->mode = (WIRELESS_MODE)btWirelessMode; // 3. Change related setting. if( ieee->mode == WIRELESS_MODE_A ){ @@ -2108,18 +1905,7 @@ SetRFPowerState( return bResult; } - switch(priv->rf_chip) - { - case RF_ZEBRA2: - case RF_ZEBRA4: - bResult = SetZebraRFPowerState8185(dev, eRFPowerState); - break; - - default: - printk("SetRFPowerState8185(): unknown RFChipID: 0x%X!!!\n", priv->rf_chip); - break;; -} -// printk("<--------- SetRFPowerState(): bResult(%d)\n", bResult); + bResult = SetZebraRFPowerState8185(dev, eRFPowerState); return bResult; } -- cgit v1.2.3 From cd18964a1d67c4989474ffca0109ef1c0f8502a3 Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Sun, 14 Feb 2010 22:07:57 -0600 Subject: Staging: r8187se: Remove dead code from r8185b_init.c Remove dead code from r8185b_init.c. Signed-off-by: Larry Finger Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8187se/r8185b_init.c | 632 +------------------------------- 1 file changed, 2 insertions(+), 630 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8187se/r8185b_init.c b/drivers/staging/rtl8187se/r8185b_init.c index 19b5c9f90b51..a0ece1fd64a5 100644 --- a/drivers/staging/rtl8187se/r8185b_init.c +++ b/drivers/staging/rtl8187se/r8185b_init.c @@ -243,82 +243,7 @@ void SetOutputEnableOfRfPins(struct net_device *dev) write_nic_word(dev, RFPinsEnable, 0x1bff); } -void -ZEBRA_RFSerialWrite( - struct net_device *dev, - u32 data2Write, - u8 totalLength, - u8 low2high - ) -{ - ThreeWireReg twreg; - int i; - u16 oval,oval2,oval3; - u32 mask; - u16 UshortBuffer; - - u8 u1bTmp; - // RTL8187S HSSI Read/Write Function - u1bTmp = read_nic_byte(dev, RF_SW_CONFIG); - u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI) - write_nic_byte(dev, RF_SW_CONFIG, u1bTmp); - UshortBuffer = read_nic_word(dev, RFPinsOutput); - oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko. - - oval2 = read_nic_word(dev, RFPinsEnable); - oval3 = read_nic_word(dev, RFPinsSelect); - - // 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko. - oval3 &= 0xfff8; - - write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable - write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch - udelay(10); - - // Add this to avoid hardware and software 3-wire conflict. - // 2005.03.01, by rcnjko. - twreg.longData = 0; - twreg.struc.enableB = 1; - write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE) - udelay(2); - twreg.struc.enableB = 0; - write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE) - udelay(10); - - mask = (low2high)?0x01:((u32)0x01<<(totalLength-1)); - - for(i=0; i>1); - twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0; - write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); - write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); - twreg.struc.clk = 0; - write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); - mask = (low2high)?(mask<<1):(mask>>1); - } - - twreg.struc.enableB = 1; - twreg.struc.clk = 0; - twreg.struc.data = 0; - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); - udelay(10); - - write_nic_word(dev, RFPinsOutput, oval|0x0004); - write_nic_word(dev, RFPinsSelect, oval3|0x0000); - - SetOutputEnableOfRfPins(dev); -} -//by amy - - -int +static int HwHSSIThreeWire( struct net_device *dev, u8 *pDataBuf, @@ -456,138 +381,6 @@ HwHSSIThreeWire( return bResult; } -//by amy - -int -HwThreeWire( - struct net_device *dev, - u8 *pDataBuf, - u8 nDataBufBitCnt, - int bHold, - int bWrite - ) -{ - int bResult = 1; - u8 TryCnt; - u8 u1bTmp; - - do - { - // Check if WE and RE are cleared. - for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) - { - u1bTmp = read_nic_byte(dev, SW_3W_CMD1); - if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 ) - { - break; - } - udelay(10); - } - if (TryCnt == TC_3W_POLL_MAX_TRY_CNT) - panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp); - - // Fill up data buffer for write operation. - if(nDataBufBitCnt == 16) - { - write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf)); - } - else if(nDataBufBitCnt == 64) - { - write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf)); - write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4))); - } - else - { - int idx; - int ByteCnt = nDataBufBitCnt / 8; - - if ((nDataBufBitCnt % 8) != 0) - panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n", - nDataBufBitCnt); - - if (nDataBufBitCnt > 64) - panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n", - nDataBufBitCnt); - - for(idx = 0; idx < ByteCnt; idx++) - { - write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx)); - } - } - - // Fill up length field. - u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1. - if(bHold) - u1bTmp |= SW_3W_CMD0_HOLD; - write_nic_byte(dev, SW_3W_CMD0, u1bTmp); - - // Set up command: WE or RE. - if(bWrite) - { - write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE); - } - else - { - write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE); - } - - // Check if WE and RE are cleared and DONE is set. - for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) - { - u1bTmp = read_nic_byte(dev, SW_3W_CMD1); - if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 && - (u1bTmp & SW_3W_CMD1_DONE) != 0 ) - { - break; - } - udelay(10); - } - if(TryCnt == TC_3W_POLL_MAX_TRY_CNT) - { - //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT, - // ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp)); - // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko. - write_nic_byte(dev, SW_3W_CMD1, 0); - } - - // Read back data for read operation. - // I am not sure if this is correct output format of a read operation. - if(bWrite == 0) - { - if(nDataBufBitCnt == 16) - { - *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0); - } - else if(nDataBufBitCnt == 64) - { - *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0); - *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1); - } - else - { - int idx; - int ByteCnt = nDataBufBitCnt / 8; - - if ((nDataBufBitCnt % 8) != 0) - panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n", - nDataBufBitCnt); - - if (nDataBufBitCnt > 64) - panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n", - nDataBufBitCnt); - - for(idx = 0; idx < ByteCnt; idx++) - { - *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx)); - } - } - } - - }while(0); - - return bResult; -} - void RF_WriteReg(struct net_device *dev, u8 offset, u32 data) @@ -602,125 +395,6 @@ RF_WriteReg(struct net_device *dev, u8 offset, u32 data) HwHSSIThreeWire(dev, (u8 *)(&data2Write), len, 1, 1); } -void -ZEBRA_RFSerialRead(struct net_device *dev, u32 data2Write, u8 wLength, - u32 *data2Read, u8 rLength, u8 low2high) -{ - ThreeWireReg twreg; - int i; - u16 oval, oval2, oval3, tmp, wReg80; - u32 mask; - u8 u1bTmp; - ThreeWireReg tdata; - //PHAL_DATA_8187 pHalData = GetHalData8187(pAdapter); - { // RTL8187S HSSI Read/Write Function - u1bTmp = read_nic_byte(dev, RF_SW_CONFIG); - u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI) - write_nic_byte(dev, RF_SW_CONFIG, u1bTmp); - } - - wReg80 = oval = read_nic_word(dev, RFPinsOutput); - oval2 = read_nic_word(dev, RFPinsEnable); - oval3 = read_nic_word(dev, RFPinsSelect); - - write_nic_word(dev, RFPinsEnable, oval2|0xf); - write_nic_word(dev, RFPinsSelect, oval3|0xf); - - *data2Read = 0; - - // We must clear BIT0-3 here, otherwise, - // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open, - // which will cause the value read become 0. 2005.04.11, by rcnjko. - oval &= ~0xf; - - // Avoid collision with hardware three-wire. - twreg.longData = 0; - twreg.struc.enableB = 1; - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4); - - twreg.longData = 0; - twreg.struc.enableB = 0; - twreg.struc.clk = 0; - twreg.struc.read_write = 0; - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5); - - mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1)); - for(i = 0; i < wLength/2; i++) - { - twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0; - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1); - twreg.struc.clk = 1; - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2); - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2); - - mask = (low2high) ? (mask<<1): (mask>>1); - - if(i == 2) - { - // Commented out by Jackie, 2004.08.26. We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read. - //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe); // turn off data enable - //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe); - - twreg.struc.read_write=1; - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2); - twreg.struc.clk = 0; - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2); - break; - } - twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0; - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2); - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2); - - twreg.struc.clk = 0; - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1); - - mask = (low2high) ? (mask<<1) : (mask>>1); - } - - twreg.struc.clk = 0; - twreg.struc.data = 0; - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2); - mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1)); - - // - // 061016, by rcnjko: - // We must set data pin to HW controled, otherwise RF can't driver it and - // value RF register won't be able to read back properly. - // - write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) ); - - for(i = 0; i < rLength; i++) - { - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1); - twreg.struc.clk = 1; - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2); - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2); - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2); - tmp = read_nic_word(dev, RFPinsInput); - tdata.longData = tmp; - *data2Read |= tdata.struc.clk ? mask : 0; - - twreg.struc.clk = 0; - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2); - - mask = (low2high) ? (mask<<1) : (mask>>1); - } - twreg.struc.enableB = 1; - twreg.struc.clk = 0; - twreg.struc.data = 0; - twreg.struc.read_write = 1; - write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2); - - //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8); // Set To Output Enable - write_nic_word(dev, RFPinsEnable, oval2); // Set To Output Enable, We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12. - //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff); - write_nic_word(dev, RFPinsSelect, oval3); // Set To SW Switch - //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488); - write_nic_word(dev, RFPinsOutput, 0x3a0); - //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480); -} - - u32 RF_ReadReg(struct net_device *dev, u8 offset) { u32 data2Write; @@ -891,15 +565,12 @@ ZEBRA_Config_85BASIC_HardCode( // Page0 : reg0-reg15 -// RF_WriteReg(dev, 0x00, 0x003f); mdelay(1);//1 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);// 1 RF_WriteReg(dev, 0x01, 0x06e0); mdelay(1); -// RF_WriteReg(dev, 0x02, 0x004c); mdelay(1);//2 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);// 2 -// RF_WriteReg(dev, 0x03, 0x0000); mdelay(1);//3 RF_WriteReg(dev, 0x03, 0x07f1); mdelay(1);// 3 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); @@ -928,8 +599,6 @@ ZEBRA_Config_85BASIC_HardCode( RF_WriteReg(dev, 0x07, 0x01A0); mdelay(1); // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl. -// RF_WriteReg(dev, 0x08, 0x0597); mdelay(1); -// RF_WriteReg(dev, 0x09, 0x050a); mdelay(1); RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1); RF_WriteReg(dev, 0x0b, 0x0418); mdelay(1); @@ -945,7 +614,6 @@ ZEBRA_Config_85BASIC_HardCode( RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1); -// RF_WriteReg(dev, 0x00, 0x017f); mdelay(1);//6 RF_WriteReg(dev, 0x00, 0x01d7); mdelay(1);// 6 RF_WriteReg(dev, 0x03, 0x0e00); mdelay(1); @@ -954,20 +622,14 @@ ZEBRA_Config_85BASIC_HardCode( { RF_WriteReg(dev, 0x01, i); mdelay(1); RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1); - //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]); } RF_WriteReg(dev, 0x05, 0x0203); mdelay(1); /// 203, 343 - //RF_WriteReg(dev, 0x06, 0x0300); mdelay(1); // 400 RF_WriteReg(dev, 0x06, 0x0200); mdelay(1); // 400 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); // switch to reg16-reg30, and HSSI disable 137 mdelay(10); // Deay 10 ms. //0xfd -// RF_WriteReg(dev, 0x0c, 0x09be); mdelay(1); // 7 - //RF_WriteReg(dev, 0x0c, 0x07be); mdelay(1); - //mdelay(10); // Deay 10 ms. //0xfd - RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1); // Z4 synthesizer loop filter setting, 392 mdelay(10); // Deay 10 ms. //0xfd @@ -1013,10 +675,8 @@ ZEBRA_Config_85BASIC_HardCode( RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1); } //by amy 080312 -// RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1); //-by amy 080312 RF_WriteReg(dev, 0x00, 0x00bf); mdelay(1); // switch to reg0-reg15, and HSSI enable -// RF_WriteReg(dev, 0x0d, 0x009f); mdelay(1); // Rx BB start calibration, 00c//-edward RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1); // Rx BB start calibration, 00c//+edward RF_WriteReg(dev, 0x02, 0x004d); mdelay(1); // temperature meter off RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); // Rx mode @@ -1065,13 +725,10 @@ ZEBRA_Config_85BASIC_HardCode( // AGC.txt //============================================================================= -// PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280); // Annie, 2006-05-05 write_phy_ofdm(dev, 0x00, 0x12); - //WriteBBPortUchar(dev, 0x00001280); for (i=0; i<128; i++) { - //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]); data = ZEBRA_AGC[i+1]; data = data << 8; @@ -1087,7 +744,6 @@ ZEBRA_Config_85BASIC_HardCode( } PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080); // Annie, 2006-05-05 - //WriteBBPortUchar(dev, 0x00001080); //============================================================================= @@ -1100,8 +756,6 @@ ZEBRA_Config_85BASIC_HardCode( u4bRegOffset=i; u4bRegValue=OFDM_CONFIG[i]; - //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue); - WriteBBPortUchar(dev, (0x00000080 | (u4bRegOffset & 0x7f) | @@ -1125,9 +779,6 @@ UpdateInitialGain( ) { struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); - //unsigned char* IGTable; - //u8 DIG_CurrentInitialGain = 4; - //unsigned char u1Tmp; //lzm add 080826 if(priv->eRFPowerState != eRfOn) @@ -1205,13 +856,11 @@ InitTxPwrTracking87SE( struct net_device *dev ) { - //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); u32 u4bRfReg; u4bRfReg = RF_ReadReg(dev, 0x02); // Enable Thermal meter indication. - //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN); RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1); } @@ -1231,7 +880,6 @@ PhyConfig8185( { if(priv->InitialGain == 0) priv->InitialGain = 4; - //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain); } // @@ -1249,34 +897,17 @@ PhyConfig8185( return; } - - - void HwConfigureRTL8185( struct net_device *dev ) { //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control. -// u8 bUNIVERSAL_CONTROL_RL = 1; u8 bUNIVERSAL_CONTROL_RL = 0; - u8 bUNIVERSAL_CONTROL_AGC = 1; u8 bUNIVERSAL_CONTROL_ANT = 1; u8 bAUTO_RATE_FALLBACK_CTL = 1; u8 val8; - //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); - //struct ieee80211_device *ieee = priv->ieee80211; - //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev)) -//{by amy 080312 if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A)) -// { -// write_nic_word(dev, BRSR, 0xffff); -// } -// else -// { -// write_nic_word(dev, BRSR, 0x000f); -// } -//by amy 080312} write_nic_word(dev, BRSR, 0x0fff); // Retry limit val8 = read_nic_byte(dev, CW_CONF); @@ -1327,20 +958,11 @@ HwConfigureRTL8185( val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1; // We shall set up the ARFR according to user's setting. - //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M -//by amy - // Aadded by Roger, 2007.11.15. PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps. -//by amy - } - else - { } write_nic_byte(dev, RATE_FALLBACK, val8); } - - static void MacConfig_85BASIC_HardCode( struct net_device *dev) @@ -1368,14 +990,11 @@ MacConfig_85BASIC_HardCode( { u4bRegOffset |= (u4bPageIndex << 8); } - //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue); write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue); } //============================================================================ } - - static void MacConfig_85BASIC( struct net_device *dev) @@ -1398,8 +1017,6 @@ MacConfig_85BASIC( PlatformIOWrite1Byte(dev, 0x1F8, 0x00); // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko. - //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001); -//by amy // power save parameter based on "87SE power save parameters 20071127.doc", as follow. //Enable DA10 TX power saving @@ -1418,16 +1035,10 @@ MacConfig_85BASIC( write_nic_word(dev, 0x378, 0x0560); write_nic_word(dev, 0x37A, 0x0560); write_nic_word(dev, 0x37C, 0x00EC); -// write_nic_word(dev, 0x37E, 0x00FE);//-edward write_nic_word(dev, 0x37E, 0x00EC);//+edward write_nic_byte(dev, 0x24E,0x01); -//by amy - } - - - u8 GetSupportedWirelessMode8185( struct net_device *dev @@ -1450,7 +1061,6 @@ ActUpdateChannelAccessSetting( struct ieee80211_device *ieee = priv->ieee80211; AC_CODING eACI; AC_PARAM AcParam; - //PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos; u8 bFollowLegacySetting = 0; u8 u1bAIFS; @@ -1472,40 +1082,14 @@ ActUpdateChannelAccessSetting( ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko. write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer); - //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer ); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29. write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29. u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer ); - //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS); - //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS); - //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS); - //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS); - write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer); write_nic_byte(dev, AckTimeOutReg, 0x5B); // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08. -#ifdef TODO - // Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC. - if( pStaQos->CurrentQosMode > QOS_DISABLE ) - { // QoS mode. - if(pStaQos->QBssWirelessMode == WirelessMode) - { - // Follow AC Parameters of the QBSS. - for(eACI = 0; eACI < AC_MAX; eACI++) - { - Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) ); - } - } - else - { - // Follow Default WMM AC Parameters. - bFollowLegacySetting = 1; - } - } - else -#endif { // Legacy 802.11. bFollowLegacySetting = 1; @@ -1528,14 +1112,12 @@ ActUpdateChannelAccessSetting( AcParam.f.TXOPLimit = 0; //lzm reserved 080826 -#if 1 // For turbo mode setting. port from 87B by Isaiah 2008-08-01 if( ieee->current_network.Turbo_Enable == 1 ) AcParam.f.TXOPLimit = 0x01FF; // For 87SE with Intel 4965 Ad-Hoc mode have poor throughput (19MB) if (ieee->iw_mode == IW_MODE_ADHOC) AcParam.f.TXOPLimit = 0x0020; -#endif for(eACI = 0; eACI < AC_MAX; eACI++) { @@ -1579,18 +1161,13 @@ ActUpdateChannelAccessSetting( // Cehck ACM bit. // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13. - //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn); { PACI_AIFSN pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn); AC_CODING eACI = pAciAifsn->f.ACI; //modified Joseph //for 8187B AsynIORead issue -#ifdef TODO - u8 AcmCtrl = pHalData->AcmControl; -#else u8 AcmCtrl = 0; -#endif if( pAciAifsn->f.ACM ) { // ACM bit is 1. switch(eACI) @@ -1632,19 +1209,10 @@ ActUpdateChannelAccessSetting( break; } } - - //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl); - -#ifdef TO_DO - pHalData->AcmControl = AcmCtrl; -#endif - //write_nic_byte(dev, ACM_CONTROL, AcmCtrl); write_nic_byte(dev, ACM_CONTROL, 0); } } } - - } } @@ -1656,7 +1224,6 @@ ActSetWirelessMode8185( { struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); struct ieee80211_device *ieee = priv->ieee80211; - //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); u8 btSupportedWirelessMode = GetSupportedWirelessMode8185(dev); if( (btWirelessMode & btSupportedWirelessMode) == 0 ) @@ -1689,7 +1256,6 @@ ActSetWirelessMode8185( } } - /* 2. Swtich band: RF or BB specific actions, * for example, refresh tables in omc8255, or change initial gain if necessary. * Nothing to do for Zebra to switch band. @@ -1706,7 +1272,6 @@ ActSetWirelessMode8185( else if( ieee->mode == WIRELESS_MODE_G ){ DMESG("WIRELESS_MODE_G\n"); } - ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting); } @@ -1724,11 +1289,7 @@ DrvIFIndicateDisassociation( u16 reason ) { - //printk("==> DrvIFIndicateDisassociation()\n"); - // nothing is needed after disassociation request. - - //printk("<== DrvIFIndicateDisassociation()\n"); } void MgntDisconnectIBSS( @@ -1738,11 +1299,7 @@ MgntDisconnectIBSS( struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); u8 i; - //printk("XXXXXXXXXX MgntDisconnect IBSS\n"); - DrvIFIndicateDisassociation(dev, unspec_reason); - -// PlatformZeroMemory( pMgntInfo->Bssid, 6 ); for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x55; priv->ieee80211->state = IEEE80211_NOLINK; @@ -1754,16 +1311,10 @@ MgntDisconnectIBSS( // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send. // Disable Beacon Queue Own bit, suggested by jong -// Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0); ieee80211_stop_send_beacons(priv->ieee80211); priv->ieee80211->link_change(dev); notify_wx_assoc_event(priv->ieee80211); - - // Stop SW Beacon.Use hw beacon so do not need to do so.by amy - -// MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE ); - } void MlmeDisassociateRequest( @@ -1783,14 +1334,8 @@ MlmeDisassociateRequest( DrvIFIndicateDisassociation(dev, unspec_reason); - // pMgntInfo->AsocTimestamp = 0; for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x22; -// pMgntInfo->mBrates.Length = 0; -// Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) ); - ieee80211_disassociate(priv->ieee80211); - - } } @@ -1808,23 +1353,12 @@ MgntDisconnectAP( // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE(). // // //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success -// SecClearAllKeys(Adapter); // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking. -#ifdef TODO - if( pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch || - (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) ) // In CCKM mode will Clear key - { - SecClearAllKeys(Adapter); - RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key...")) - } -#endif // 2004.10.11, by rcnjko. - //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss ); MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn ); priv->ieee80211->state = IEEE80211_NOLINK; -// pMgntInfo->AsocTimestamp = 0; } bool MgntDisconnect( @@ -1836,20 +1370,7 @@ MgntDisconnect( // // Schedule an workitem to wake up for ps mode, 070109, by rcnjko. // -#ifdef TODO - if(pMgntInfo->mPss != eAwake) - { - // - // Using AwkaeTimer to prevent mismatch ps state. - // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31. - // - // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) ); - PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 ); - } -#endif - // Indication of disassociation event. - //DrvIFIndicateDisassociation(Adapter, asRsn); if(IS_DOT11D_ENABLE(priv->ieee80211)) Dot11d_Reset(priv->ieee80211); // In adhoc mode, update beacon frame. @@ -1857,8 +1378,6 @@ MgntDisconnect( { if( priv->ieee80211->iw_mode == IW_MODE_ADHOC ) { -// RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n")); - //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n"); MgntDisconnectIBSS(dev); } if( priv->ieee80211->iw_mode == IW_MODE_INFRA ) @@ -1868,17 +1387,10 @@ MgntDisconnect( // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is // used to handle disassociation related things to AP, e.g. send Disassoc // frame to AP. 2005.01.27, by rcnjko. -// SecClearAllKeys(Adapter); - -// RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n")); - //printk("MgntDisconnect() ===> MgntDisconnectAP\n"); MgntDisconnectAP(dev, asRsn); } - // Inidicate Disconnect, 2005.02.23, by rcnjko. -// MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE); } - return true; } // @@ -1898,10 +1410,8 @@ SetRFPowerState( struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); bool bResult = false; -// printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState); if(eRFPowerState == priv->eRFPowerState) { -// printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState); return bResult; } @@ -1935,33 +1445,25 @@ MgntActSet_RF_State( RT_RF_POWER_STATE rtState; u16 RFWaitCounter = 0; unsigned long flag; -// printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource); // // Prevent the race condition of RF state change. By Bruce, 2007-11-28. // Only one thread can change the RF state at one time, and others should wait to be executed. // -#if 1 while(true) { -// down(&priv->rf_state); spin_lock_irqsave(&priv->rf_ps_lock,flag); if(priv->RFChangeInProgress) { -// printk("====================>haha111111111\n"); -// up(&priv->rf_state); -// RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet)); spin_unlock_irqrestore(&priv->rf_ps_lock,flag); // Set RF after the previous action is done. while(priv->RFChangeInProgress) { RFWaitCounter ++; -// RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter)); udelay(1000); // 1 ms // Wait too long, return FALSE to avoid to be stuck here. if(RFWaitCounter > 1000) // 1sec { -// RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n")); printk("MgntActSet_RF_State(): Wait too long to set RF\n"); // TODO: Reset RF state? return false; @@ -1970,17 +1472,13 @@ MgntActSet_RF_State( } else { -// printk("========================>haha2\n"); priv->RFChangeInProgress = true; -// up(&priv->rf_state); spin_unlock_irqrestore(&priv->rf_ps_lock,flag); break; } } -#endif rtState = priv->eRFPowerState; - switch(StateToSet) { case eRfOn: @@ -2001,7 +1499,6 @@ MgntActSet_RF_State( } } else -// RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource)); ; break; @@ -2018,38 +1515,26 @@ MgntActSet_RF_State( // // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(), // because we do NOT need to set ssid to dummy ones. - // Revised by Roger, 2007.12.04. // MgntDisconnect( dev, disas_lv_ss ); // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI. - // 2007.05.28, by shien chang. -// PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC ); -// pMgntInfo->NumBssDesc = 0; -// PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC ); -// pMgntInfo->NumBssDesc4Query = 0; } - - priv->RfOffReason |= ChangeSource; bActionAllowed = true; break; - case eRfSleep: priv->RfOffReason |= ChangeSource; bActionAllowed = true; break; - default: break; } if(bActionAllowed) { -// RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason)); // Config HW to the specified mode. -// printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason); SetRFPowerState(dev, StateToSet); // Turn on RF. @@ -2059,7 +1544,6 @@ MgntActSet_RF_State( if(bConnectBySSID) { // by amy not supported -// MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE ); } } // Turn off RF. @@ -2068,18 +1552,11 @@ MgntActSet_RF_State( HalDisableRx8185Dummy(dev); } } - else - { - // printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason); - } // Release RF spinlock -// down(&priv->rf_state); spin_lock_irqsave(&priv->rf_ps_lock,flag); priv->RFChangeInProgress = false; -// up(&priv->rf_state); spin_unlock_irqrestore(&priv->rf_ps_lock,flag); -// printk("<===MgntActSet_RF_State()\n"); return bActionAllowed; } void @@ -2088,15 +1565,12 @@ InactivePowerSave( ) { struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); - //u8 index = 0; - // // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem // is really scheduled. // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing // blocks the IPS procedure of switching RF. - // By Bruce, 2007-12-25. // priv->bSwRfProcessing = true; @@ -2112,7 +1586,6 @@ InactivePowerSave( // // Description: // Enter the inactive power save mode. RF will be off -// 2007.08.17, by shien chang. // void IPSEnter( @@ -2121,13 +1594,11 @@ IPSEnter( { struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); RT_RF_POWER_STATE rtState; - //printk("==============================>enter IPS\n"); if (priv->bInactivePs) { rtState = priv->eRFPowerState; // - // Added by Bruce, 2007-12-25. // Do not enter IPS in the following conditions: // (1) RF is already OFF or Sleep // (2) bSwRfProcessing (indicates the IPS is still under going) @@ -2138,12 +1609,10 @@ IPSEnter( if (rtState == eRfOn && !priv->bSwRfProcessing && (priv->ieee80211->state != IEEE80211_LINKED )) { - // printk("IPSEnter(): Turn off RF.\n"); priv->eInactivePowerState = eRfOff; InactivePowerSave(dev); } } -// printk("priv->eRFPowerState is %d\n",priv->eRFPowerState); } void IPSLeave( @@ -2152,20 +1621,17 @@ IPSLeave( { struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); RT_RF_POWER_STATE rtState; - //printk("===================================>leave IPS\n"); if (priv->bInactivePs) { rtState = priv->eRFPowerState; if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS) { -// printk("IPSLeave(): Turn on RF.\n"); priv->eInactivePowerState = eRfOn; InactivePowerSave(dev); } } -// printk("priv->eRFPowerState is %d\n",priv->eRFPowerState); } -//by amy for power save + void rtl8185b_adapter_start(struct net_device *dev) { struct r8180_priv *priv = ieee80211_priv(dev); @@ -2174,75 +1640,45 @@ void rtl8185b_adapter_start(struct net_device *dev) u8 SupportedWirelessMode; u8 InitWirelessMode; u8 bInvalidWirelessMode = 0; - //int i; u8 tmpu8; - //u8 u1tmp,u2tmp; u8 btCR9346; u8 TmpU1b; u8 btPSR; - //rtl8180_rtx_disable(dev); -//{by amy 080312 write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0)); -//by amy 080312} rtl8180_reset(dev); priv->dma_poll_mask = 0; priv->dma_poll_stop_mask = 0; - //rtl8180_beacon_tx_disable(dev); - HwConfigureRTL8185(dev); - write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]); write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff ); - write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3); // default network type to 'No Link' - - //write_nic_byte(dev, BRSR, 0x0); // Set BRSR= 1M - write_nic_word(dev, BcnItv, 100); write_nic_word(dev, AtimWnd, 2); - - //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF); PlatformIOWrite2Byte(dev, FEMR, 0xFFFF); - write_nic_byte(dev, WPA_CONFIG, 0); - MacConfig_85BASIC(dev); - // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko. // BT_DEMO_BOARD type PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a); -//by amy -//#ifdef CONFIG_RTL818X_S - // for jong required -// PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56); -//#endif -//by amy - //BT_QA_BOARD - //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56); //----------------------------------------------------------------------------- // Set up PHY related. //----------------------------------------------------------------------------- // Enable Config3.PARAM_En to revise AnaaParm. write_nic_byte(dev, CR9346, 0xc0); // enable config register write -//by amy tmpu8 = read_nic_byte(dev, CONFIG3); write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) ); -//by amy // Turn on Analog power. // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko. write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON); write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON); -//by amy write_nic_word(dev, ANAPARAM3, 0x0010); -//by amy write_nic_byte(dev, CONFIG3, tmpu8); write_nic_byte(dev, CR9346, 0x00); -//{by amy 080312 for led // enable EEM0 and EEM1 in 9346CR btCR9346 = read_nic_byte(dev, CR9346); write_nic_byte(dev, CR9346, (btCR9346|0xC0) ); @@ -2260,7 +1696,6 @@ void rtl8185b_adapter_start(struct net_device *dev) // B-cut RF Radio on/off 5e[3]=0 btPSR = read_nic_byte(dev, PSR); write_nic_byte(dev, PSR, (btPSR | BIT3)); -//by amy 080312 for led} // setup initial timing for RFE. write_nic_word(dev, RFPinsOutput, 0x0480); SetOutputEnableOfRfPins(dev); @@ -2323,55 +1758,19 @@ void rtl8185b_adapter_start(struct net_device *dev) InitWirelessMode = ieee->mode; } //by amy for power save -// printk("initialize ENABLE_IPS\n"); priv->eRFPowerState = eRfOff; priv->RfOffReason = 0; { - // u32 tmp2; - // u32 tmp = jiffies; MgntActSet_RF_State(dev, eRfOn, 0); - // tmp2 = jiffies; - // printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ); } -// DrvIFIndicateCurrentPhyStatus(priv); // // If inactive power mode is enabled, disable rf while in disconnected state. - // 2007.07.16, by shien chang. // if (priv->bInactivePs) { - // u32 tmp2; - // u32 tmp = jiffies; MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS); - // tmp2 = jiffies; - // printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ); - } -// IPSEnter(dev); //by amy for power save -#ifdef TODO - // Turn off RF if necessary. 2005.08.23, by rcnjko. - // We shall turn off RF after setting CMDR, otherwise, - // RF will be turnned on after we enable MAC Tx/Rx. - if(Adapter->MgntInfo.RegRfOff == TRUE) - { - SetRFPowerState8185(Adapter, RF_OFF); - } - else - { - SetRFPowerState8185(Adapter, RF_ON); - } -#endif - -/* //these is equal with above TODO. - write_nic_byte(dev, CR9346, 0xc0); // enable config register write - write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En); - RF_WriteReg(dev, 0x4, 0x9FF); - write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON); - write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON); - write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En))); - write_nic_byte(dev, CR9346, 0x00); -*/ ActSetWirelessMode8185(dev, (u8)(InitWirelessMode)); @@ -2380,14 +1779,11 @@ void rtl8185b_adapter_start(struct net_device *dev) rtl8185b_irq_enable(dev); netif_start_queue(dev); - } - void rtl8185b_rx_enable(struct net_device *dev) { u8 cmd; - //u32 rxconf; /* for now we accept data, management & ctl frame*/ struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); @@ -2399,11 +1795,6 @@ void rtl8185b_rx_enable(struct net_device *dev) priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP; } - /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){ - rxconf = rxconf | (1<ieee80211->iw_mode == IW_MODE_MONITOR){ priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV; } @@ -2415,9 +1806,6 @@ void rtl8185b_rx_enable(struct net_device *dev) fix_rx_fifo(dev); -#ifdef DEBUG_RX - DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR)); -#endif cmd=read_nic_byte(dev,CMD); write_nic_byte(dev,CMD,cmd | (1<TransmitConfig); @@ -2438,21 +1824,7 @@ void rtl8185b_tx_enable(struct net_device *dev) fix_tx_fifo(dev); -#ifdef DEBUG_TX - DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR)); -#endif - cmd=read_nic_byte(dev,CMD); write_nic_byte(dev,CMD,cmd | (1<dma_poll_mask); - rtl8180_set_mode(dev,EPROM_CMD_NORMAL); - */ } - -- cgit v1.2.3 From 1d31a9ee698f9b8d72c5813fe62a5184197443c3 Mon Sep 17 00:00:00 2001 From: Bernie Thompson Date: Mon, 15 Feb 2010 06:45:43 -0800 Subject: Staging: udlfb: checkpatch cleanup Eliminate checkpatch.pl warnings and errors so later patches in series are clean Signed-off-by: Bernie Thompson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/udlfb/udlfb.c | 74 ++++++++++++++++++++----------------------- drivers/staging/udlfb/udlfb.h | 1 - 2 files changed, 34 insertions(+), 41 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/udlfb/udlfb.c b/drivers/staging/udlfb/udlfb.c index b61a3e58a9ec..d2adfe416a0c 100644 --- a/drivers/staging/udlfb/udlfb.c +++ b/drivers/staging/udlfb/udlfb.c @@ -30,13 +30,13 @@ #define DRIVER_VERSION "DisplayLink Framebuffer Driver 0.4.1" static struct fb_fix_screeninfo dlfb_fix = { - .id = "displaylinkfb", - .type = FB_TYPE_PACKED_PIXELS, - .visual = FB_VISUAL_TRUECOLOR, - .xpanstep = 0, - .ypanstep = 0, - .ywrapstep = 0, - .accel = FB_ACCEL_NONE, + .id = "displaylinkfb", + .type = FB_TYPE_PACKED_PIXELS, + .visual = FB_VISUAL_TRUECOLOR, + .xpanstep = 0, + .ypanstep = 0, + .ywrapstep = 0, + .accel = FB_ACCEL_NONE, }; #define NR_USB_REQUEST_I2C_SUB_IO 0x02 @@ -48,21 +48,21 @@ static struct fb_fix_screeninfo dlfb_fix = { */ static char *insert_command(char *buf, u8 reg, u8 val) { - *buf++ = 0xAF; - *buf++ = 0x20; - *buf++ = reg; - *buf++ = val; - return buf; + *buf++ = 0xAF; + *buf++ = 0x20; + *buf++ = reg; + *buf++ = val; + return buf; } static char *insert_vidreg_lock(char *buf) { - return insert_command(buf, 0xFF, 0x00); + return insert_command(buf, 0xFF, 0x00); } static char *insert_vidreg_unlock(char *buf) { - return insert_command(buf, 0xFF, 0xFF); + return insert_command(buf, 0xFF, 0xFF); } /* @@ -71,33 +71,33 @@ static char *insert_vidreg_unlock(char *buf) */ static char *insert_enable_hvsync(char *buf) { - return insert_command(buf, 0x1F, 0x00); + return insert_command(buf, 0x1F, 0x00); } static char *insert_set_color_depth(char *buf, u8 selection) { - return insert_command(buf, 0x00, selection); + return insert_command(buf, 0x00, selection); } static char *insert_set_base16bpp(char *wrptr, u32 base) { - /* the base pointer is 16 bits wide, 0x20 is hi byte. */ - wrptr = insert_command(wrptr, 0x20, base >> 16); - wrptr = insert_command(wrptr, 0x21, base >> 8); - return insert_command(wrptr, 0x22, base); + /* the base pointer is 16 bits wide, 0x20 is hi byte. */ + wrptr = insert_command(wrptr, 0x20, base >> 16); + wrptr = insert_command(wrptr, 0x21, base >> 8); + return insert_command(wrptr, 0x22, base); } static char *insert_set_base8bpp(char *wrptr, u32 base) { - wrptr = insert_command(wrptr, 0x26, base >> 16); - wrptr = insert_command(wrptr, 0x27, base >> 8); - return insert_command(wrptr, 0x28, base); + wrptr = insert_command(wrptr, 0x26, base >> 16); + wrptr = insert_command(wrptr, 0x27, base >> 8); + return insert_command(wrptr, 0x28, base); } static char *insert_command_16(char *wrptr, u8 reg, u16 value) { - wrptr = insert_command(wrptr, reg, value >> 8); - return insert_command(wrptr, reg+1, value); + wrptr = insert_command(wrptr, reg, value >> 8); + return insert_command(wrptr, reg+1, value); } /* @@ -106,8 +106,8 @@ static char *insert_command_16(char *wrptr, u8 reg, u16 value) */ static char *insert_command_16be(char *wrptr, u8 reg, u16 value) { - wrptr = insert_command(wrptr, reg, value); - return insert_command(wrptr, reg+1, value >> 8); + wrptr = insert_command(wrptr, reg, value); + return insert_command(wrptr, reg+1, value >> 8); } /* @@ -339,7 +339,7 @@ MODULE_DEVICE_TABLE(usb, id_table); static struct usb_driver dlfb_driver; -// thanks to Henrik Bjerregaard Pedersen for this function +/* thanks to Henrik Bjerregaard Pedersen for this function */ static char *rle_compress16(uint16_t * src, char *dst, int rem) { @@ -347,7 +347,7 @@ static char *rle_compress16(uint16_t * src, char *dst, int rem) uint16_t pix0; char *end_if_raw = dst + 6 + 2 * rem; - dst += 6; // header will be filled in if RLE is worth it + dst += 6; /* header will be filled in if RLE is worth it */ while (rem && dst < end_if_raw) { char *start = (char *)src; @@ -366,8 +366,8 @@ static char *rle_compress16(uint16_t * src, char *dst, int rem) } /* -Thanks to Henrik Bjerregaard Pedersen for rle implementation and code refactoring. -Next step is huffman compression. +Thanks to Henrik Bjerregaard Pedersen for rle implementation +and code refactoring. Next step is huffman compression. */ static int @@ -419,7 +419,7 @@ image_blit(struct dlfb_data *dev_info, int x, int y, int width, int height, bufptr - dev_info->buf); bufptr = dev_info->buf; } - // number of pixels to consider this time + /* number of pixels to consider this time */ thistime = rem; if (thistime > 255) thistime = 255; @@ -467,7 +467,7 @@ image_blit(struct dlfb_data *dev_info, int x, int y, int width, int height, bufptr = end_of_rle; } else { - // fallback to raw (or some other encoding?) + /* fallback to raw (or other?) */ *bufptr++ = 0xAF; *bufptr++ = 0x68; @@ -479,7 +479,6 @@ image_blit(struct dlfb_data *dev_info, int x, int y, int width, int height, *bufptr++ = (char)(base + firstdiff * 2); *bufptr++ = thistime - firstdiff; - // PUT COMPRESSION HERE for (j = firstdiff * 2; j < thistime * 2; j += 2) { *bufptr++ = data[j + 1]; @@ -621,7 +620,7 @@ static void swapfb(struct dlfb_data *dev_info) bufptr = dlfb_set_register(bufptr, 0xFF, 0x00); - // set addresses + /* set addresses */ bufptr = dlfb_set_register(bufptr, 0x20, (char)(dev_info->base16 >> 16)); bufptr = dlfb_set_register(bufptr, 0x21, (char)(dev_info->base16 >> 8)); @@ -803,9 +802,6 @@ static void dlfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) copyarea(dev, area->dx, area->dy, area->sx, area->sy, area->width, area->height); - - /* printk("COPY AREA %d %d %d %d %d %d !!!\n", area->dx, area->dy, area->sx, area->sy, area->width, area->height); */ - } static void dlfb_imageblit(struct fb_info *info, const struct fb_image *image) @@ -813,12 +809,10 @@ static void dlfb_imageblit(struct fb_info *info, const struct fb_image *image) int ret; struct dlfb_data *dev = info->par; - /* printk("IMAGE BLIT (1) %d %d %d %d DEPTH %d {%p}!!!\n", image->dx, image->dy, image->width, image->height, image->depth, dev->udev); */ cfb_imageblit(info, image); ret = image_blit(dev, image->dx, image->dy, image->width, image->height, info->screen_base); - /* printk("IMAGE BLIT (2) %d %d %d %d DEPTH %d {%p} %d!!!\n", image->dx, image->dy, image->width, image->height, image->depth, dev->udev, ret); */ } static void dlfb_fillrect(struct fb_info *info, diff --git a/drivers/staging/udlfb/udlfb.h b/drivers/staging/udlfb/udlfb.h index cdf91d0d4389..245234b2f131 100644 --- a/drivers/staging/udlfb/udlfb.h +++ b/drivers/staging/udlfb/udlfb.h @@ -44,7 +44,6 @@ static void dlfb_edid(struct dlfb_data *dev_info) usb_rcvctrlpipe(dev_info->udev, 0), (0x02), (0x80 | (0x02 << 5)), i << 8, 0xA1, rbuf, 2, 0); - /*printk("ret control msg edid %d: %d [%d]\n",i, ret, rbuf[1]); */ dev_info->edid[i] = rbuf[1]; } -- cgit v1.2.3 From cc403dc67d10b895fec14b837fa2a6cb6ee6c8bd Mon Sep 17 00:00:00 2001 From: Bernie Thompson Date: Mon, 15 Feb 2010 06:45:49 -0800 Subject: Staging: udlfb: reorganize function order Reorganize the location of a few things to be closer to related code Signed-off-by: Bernie Thompson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/udlfb/udlfb.c | 62 ++++++++++++++++++++----------------------- drivers/staging/udlfb/udlfb.h | 3 +++ 2 files changed, 32 insertions(+), 33 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/udlfb/udlfb.c b/drivers/staging/udlfb/udlfb.c index d2adfe416a0c..3306bba9df3d 100644 --- a/drivers/staging/udlfb/udlfb.c +++ b/drivers/staging/udlfb/udlfb.c @@ -39,8 +39,17 @@ static struct fb_fix_screeninfo dlfb_fix = { .accel = FB_ACCEL_NONE, }; -#define NR_USB_REQUEST_I2C_SUB_IO 0x02 -#define NR_USB_REQUEST_CHANNEL 0x12 +/* + * There are many DisplayLink-based products, all with unique PIDs. We are able + * to support all volume ones (circa 2009) with a single driver, so we match + * globally on VID. TODO: Probe() needs to detect when we might be running + * "future" chips, and bail on those, so a compatible driver can match. + */ +static struct usb_device_id id_table[] = { + {.idVendor = 0x17e9, .match_flags = USB_DEVICE_ID_MATCH_VENDOR,}, + {}, +}; +MODULE_DEVICE_TABLE(usb, id_table); /* * Inserts a specific DisplayLink controller command into the provided @@ -252,24 +261,6 @@ error: return retval; } -/* - * This is necessary before we can communicate with the display controller. - */ -static int dlfb_select_std_channel(struct dlfb_data *dev) -{ - int ret; - u8 set_def_chn[] = { 0x57, 0xCD, 0xDC, 0xA7, - 0x1C, 0x88, 0x5E, 0x15, - 0x60, 0xFE, 0xC6, 0x97, - 0x16, 0x3D, 0x47, 0xF2 }; - - ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), - NR_USB_REQUEST_CHANNEL, - (USB_DIR_OUT | USB_TYPE_VENDOR), 0, 0, - set_def_chn, sizeof(set_def_chn), USB_CTRL_SET_TIMEOUT); - return ret; -} - /* * Query EDID from the handware, then hand it off to fbdev's edid parse @@ -325,18 +316,6 @@ struct dloarea { int x2, y2; }; -/* - * There are many DisplayLink-based products, all with unique PIDs. We are able - * to support all volume ones (circa 2009) with a single driver, so we match - * globally on VID. TODO: Probe() needs to detect when we might be running - * "future" chips, and bail on those, so a compatible driver can match. - */ -static struct usb_device_id id_table[] = { - {.idVendor = 0x17e9, .match_flags = USB_DEVICE_ID_MATCH_VENDOR,}, - {}, -}; -MODULE_DEVICE_TABLE(usb, id_table); - static struct usb_driver dlfb_driver; /* thanks to Henrik Bjerregaard Pedersen for this function */ @@ -888,7 +867,6 @@ static int dlfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) } /* taken from vesafb */ - static int dlfb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info) @@ -952,6 +930,24 @@ static struct fb_ops dlfb_ops = { .fb_blank = dlfb_blank, }; +/* + * This is necessary before we can communicate with the display controller. + */ +static int dlfb_select_std_channel(struct dlfb_data *dev) +{ + int ret; + u8 set_def_chn[] = { 0x57, 0xCD, 0xDC, 0xA7, + 0x1C, 0x88, 0x5E, 0x15, + 0x60, 0xFE, 0xC6, 0x97, + 0x16, 0x3D, 0x47, 0xF2 }; + + ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), + NR_USB_REQUEST_CHANNEL, + (USB_DIR_OUT | USB_TYPE_VENDOR), 0, 0, + set_def_chn, sizeof(set_def_chn), USB_CTRL_SET_TIMEOUT); + return ret; +} + static int dlfb_probe(struct usb_interface *interface, const struct usb_device_id *id) { diff --git a/drivers/staging/udlfb/udlfb.h b/drivers/staging/udlfb/udlfb.h index 245234b2f131..15f3d3a68364 100644 --- a/drivers/staging/udlfb/udlfb.h +++ b/drivers/staging/udlfb/udlfb.h @@ -26,6 +26,9 @@ struct dlfb_data { u32 pseudo_palette[256]; }; +#define NR_USB_REQUEST_I2C_SUB_IO 0x02 +#define NR_USB_REQUEST_CHANNEL 0x12 + static void dlfb_bulk_callback(struct urb *urb) { struct dlfb_data *dev_info = urb->context; -- cgit v1.2.3 From 4a4854dd2049ddc066a162a0f843dc2a78481060 Mon Sep 17 00:00:00 2001 From: Bernie Thompson Date: Mon, 15 Feb 2010 06:45:55 -0800 Subject: Staging: udlfb: pre-allocated urb list helpers Add functions to pre-allocate and free usb bulk urbs for core render path. Udlfb currently allocates a single urb, guarded by a mutex, that is a key bottleneck. Because udlfb sends so much data, preallocation is most efficient. Functions will be used by new rendering functions in later patches. Signed-off-by: Bernie Thompson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/udlfb/udlfb.c | 192 ++++++++++++++++++++++++++++++++++++++++++ drivers/staging/udlfb/udlfb.h | 35 ++++++++ 2 files changed, 227 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/udlfb/udlfb.c b/drivers/staging/udlfb/udlfb.c index 3306bba9df3d..592b1857924f 100644 --- a/drivers/staging/udlfb/udlfb.c +++ b/drivers/staging/udlfb/udlfb.c @@ -51,6 +51,13 @@ static struct usb_device_id id_table[] = { }; MODULE_DEVICE_TABLE(usb, id_table); +/* dlfb keeps a list of urbs for efficient bulk transfers */ +static void dlfb_urb_completion(struct urb *urb); +static struct urb *dlfb_get_urb(struct dlfb_data *dev); +static int dlfb_submit_urb(struct dlfb_data *dev, struct urb * urb, size_t len); +static int dlfb_alloc_urb_list(struct dlfb_data *dev, int count, size_t size); +static void dlfb_free_urb_list(struct dlfb_data *dev); + /* * Inserts a specific DisplayLink controller command into the provided * buffer. @@ -901,6 +908,21 @@ static int dlfb_release(struct fb_info *info, int user) return 0; } +/* + * Called when all client interfaces to start transactions have been disabled, + * and all references to our device instance (dlfb_data) are released. + * Every transaction must have a reference, so we know are fully spun down + */ +static void dlfb_delete(struct kref *kref) +{ + struct dlfb_data *dev = container_of(kref, struct dlfb_data, kref); + + if (dev->backing_buffer) + vfree(dev->backing_buffer); + + kfree(dev); +} + static int dlfb_blank(int blank_mode, struct fb_info *info) { struct dlfb_data *dev_info = info->par; @@ -974,6 +996,7 @@ static int dlfb_probe(struct usb_interface *interface, mutex_init(&dev->bulk_mutex); dev->udev = usbdev; + dev->gdev = &usbdev->dev; /* our generic struct device * */ dev->interface = interface; usb_set_intfdata(interface, dev); @@ -1168,6 +1191,175 @@ static void __exit dlfb_exit(void) module_init(dlfb_init); module_exit(dlfb_exit); +static void dlfb_urb_completion(struct urb *urb) +{ + struct urb_node *unode = urb->context; + struct dlfb_data *dev = unode->dev; + unsigned long flags; + + /* sync/async unlink faults aren't errors */ + if (urb->status) { + if (!(urb->status == -ENOENT || + urb->status == -ECONNRESET || + urb->status == -ESHUTDOWN)) { + dl_err("%s - nonzero write bulk status received: %d\n", + __func__, urb->status); + atomic_set(&dev->lost_pixels, 1); + } + } + + urb->transfer_buffer_length = dev->urbs.size; /* reset to actual */ + + spin_lock_irqsave(&dev->urbs.lock, flags); + list_add_tail(&unode->entry, &dev->urbs.list); + dev->urbs.available++; + spin_unlock_irqrestore(&dev->urbs.lock, flags); + + up(&dev->urbs.limit_sem); +} + +static void dlfb_free_urb_list(struct dlfb_data *dev) +{ + int count = dev->urbs.count; + struct list_head *node; + struct urb_node *unode; + struct urb *urb; + int ret; + unsigned long flags; + + dl_notice("Waiting for completes and freeing all render urbs\n"); + + /* keep waiting and freeing, until we've got 'em all */ + while (count--) { + /* Timeout means a memory leak and/or fault */ + ret = down_timeout(&dev->urbs.limit_sem, FREE_URB_TIMEOUT); + if (ret) { + BUG_ON(ret); + break; + } + spin_lock_irqsave(&dev->urbs.lock, flags); + + node = dev->urbs.list.next; /* have reserved one with sem */ + list_del_init(node); + + spin_unlock_irqrestore(&dev->urbs.lock, flags); + + unode = list_entry(node, struct urb_node, entry); + urb = unode->urb; + + /* Free each separately allocated piece */ + usb_buffer_free(urb->dev, dev->urbs.size, + urb->transfer_buffer, urb->transfer_dma); + usb_free_urb(urb); + kfree(node); + } + + kref_put(&dev->kref, dlfb_delete); + +} + +static int dlfb_alloc_urb_list(struct dlfb_data *dev, int count, size_t size) +{ + int i = 0; + struct urb *urb; + struct urb_node *unode; + char *buf; + + spin_lock_init(&dev->urbs.lock); + + dev->urbs.size = size; + INIT_LIST_HEAD(&dev->urbs.list); + + while (i < count) { + unode = kzalloc(sizeof(struct urb_node), GFP_KERNEL); + if (!unode) + break; + unode->dev = dev; + + urb = usb_alloc_urb(0, GFP_KERNEL); + if (!urb) { + kfree(unode); + break; + } + unode->urb = urb; + + buf = usb_buffer_alloc(dev->udev, MAX_TRANSFER, GFP_KERNEL, + &urb->transfer_dma); + if (!buf) { + kfree(unode); + usb_free_urb(urb); + break; + } + + /* urb->transfer_buffer_length set to actual before submit */ + usb_fill_bulk_urb(urb, dev->udev, usb_sndbulkpipe(dev->udev, 1), + buf, size, dlfb_urb_completion, unode); + urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; + + list_add_tail(&unode->entry, &dev->urbs.list); + + i++; + } + + sema_init(&dev->urbs.limit_sem, i); + dev->urbs.count = i; + dev->urbs.available = i; + + kref_get(&dev->kref); /* released in free_render_urbs() */ + + dl_notice("allocated %d %d byte urbs \n", i, (int) size); + + return i; +} + +static struct urb *dlfb_get_urb(struct dlfb_data *dev) +{ + int ret = 0; + struct list_head *entry; + struct urb_node *unode; + struct urb *urb = NULL; + unsigned long flags; + + /* Wait for an in-flight buffer to complete and get re-queued */ + ret = down_timeout(&dev->urbs.limit_sem, GET_URB_TIMEOUT); + if (ret) { + atomic_set(&dev->lost_pixels, 1); + dl_err("wait for urb interrupted: %x\n", ret); + goto error; + } + + spin_lock_irqsave(&dev->urbs.lock, flags); + + BUG_ON(list_empty(&dev->urbs.list)); /* reserved one with limit_sem */ + entry = dev->urbs.list.next; + list_del_init(entry); + dev->urbs.available--; + + spin_unlock_irqrestore(&dev->urbs.lock, flags); + + unode = list_entry(entry, struct urb_node, entry); + urb = unode->urb; + +error: + return urb; +} + +static int dlfb_submit_urb(struct dlfb_data *dev, struct urb *urb, size_t len) +{ + int ret; + + BUG_ON(len > dev->urbs.size); + + urb->transfer_buffer_length = len; /* set to actual payload len */ + ret = usb_submit_urb(urb, GFP_KERNEL); + if (ret) { + dlfb_urb_completion(urb); /* because no one else will */ + atomic_set(&dev->lost_pixels, 1); + dl_err("usb_submit_urb error %x\n", ret); + } + return ret; +} + MODULE_AUTHOR("Roberto De Ioris , " "Jaya Kumar "); MODULE_DESCRIPTION(DRIVER_VERSION); diff --git a/drivers/staging/udlfb/udlfb.h b/drivers/staging/udlfb/udlfb.h index 15f3d3a68364..13f992fe45f7 100644 --- a/drivers/staging/udlfb/udlfb.h +++ b/drivers/staging/udlfb/udlfb.h @@ -5,16 +5,35 @@ #define BUF_HIGH_WATER_MARK 1024 #define BUF_SIZE (64*1024) +struct urb_node { + struct list_head entry; + struct dlfb_data *dev; + struct urb *urb; +}; + +struct urb_list { + struct list_head list; + spinlock_t lock; + struct semaphore limit_sem; + int available; + int count; + size_t size; +}; + struct dlfb_data { struct usb_device *udev; + struct device *gdev; /* &udev->dev */ struct usb_interface *interface; struct urb *tx_urb, *ctrl_urb; struct usb_ctrlrequest dr; struct fb_info *info; + struct urb_list urbs; + struct kref kref; char *buf; char *bufend; char *backing_buffer; struct mutex bulk_mutex; + atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */ char edid[128]; int screen_size; int line_length; @@ -29,6 +48,14 @@ struct dlfb_data { #define NR_USB_REQUEST_I2C_SUB_IO 0x02 #define NR_USB_REQUEST_CHANNEL 0x12 +/* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */ +#define BULK_SIZE 512 +#define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE) +#define WRITES_IN_FLIGHT (4) + +#define GET_URB_TIMEOUT HZ +#define FREE_URB_TIMEOUT (HZ*2) + static void dlfb_bulk_callback(struct urb *urb) { struct dlfb_data *dev_info = urb->context; @@ -72,4 +99,12 @@ static int dlfb_bulk_msg(struct dlfb_data *dev_info, int len) #define dlfb_set_register insert_command +#define dl_err(format, arg...) \ + dev_err(dev->gdev, "dlfb: " format, ## arg) +#define dl_warn(format, arg...) \ + dev_warn(dev->gdev, "dlfb: " format, ## arg) +#define dl_notice(format, arg...) \ + dev_notice(dev->gdev, "dlfb: " format, ## arg) +#define dl_info(format, arg...) \ + dev_info(dev->gdev, "dlfb: " format, ## arg) #endif -- cgit v1.2.3 From 4574203f45eb26b3fd76a171a77dd298dc1dc1ae Mon Sep 17 00:00:00 2001 From: Bernie Thompson Date: Mon, 15 Feb 2010 06:46:04 -0800 Subject: Staging: udlfb: clean up function naming Move to more consistent naming scheme All udlfb functions start with udlfb_ All functions for udlfb's fbdev interface start with udlfb_ops_ All functinos for udlfb's usb interface start with udlfb_usb_ Signed-off-by: Bernie Thompson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/udlfb/udlfb.c | 133 +++++++++++++++++++++--------------------- 1 file changed, 67 insertions(+), 66 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/udlfb/udlfb.c b/drivers/staging/udlfb/udlfb.c index 592b1857924f..8d8372fd1b36 100644 --- a/drivers/staging/udlfb/udlfb.c +++ b/drivers/staging/udlfb/udlfb.c @@ -62,7 +62,7 @@ static void dlfb_free_urb_list(struct dlfb_data *dev); * Inserts a specific DisplayLink controller command into the provided * buffer. */ -static char *insert_command(char *buf, u8 reg, u8 val) +static char *dlfb_set_register(char *buf, u8 reg, u8 val) { *buf++ = 0xAF; *buf++ = 0x20; @@ -71,59 +71,59 @@ static char *insert_command(char *buf, u8 reg, u8 val) return buf; } -static char *insert_vidreg_lock(char *buf) +static char *dlfb_vidreg_lock(char *buf) { - return insert_command(buf, 0xFF, 0x00); + return dlfb_set_register(buf, 0xFF, 0x00); } -static char *insert_vidreg_unlock(char *buf) +static char *dlfb_vidreg_unlock(char *buf) { - return insert_command(buf, 0xFF, 0xFF); + return dlfb_set_register(buf, 0xFF, 0xFF); } /* * Once you send this command, the DisplayLink framebuffer gets driven to the * display. */ -static char *insert_enable_hvsync(char *buf) +static char *dlfb_enable_hvsync(char *buf) { - return insert_command(buf, 0x1F, 0x00); + return dlfb_set_register(buf, 0x1F, 0x00); } -static char *insert_set_color_depth(char *buf, u8 selection) +static char *dlfb_set_color_depth(char *buf, u8 selection) { - return insert_command(buf, 0x00, selection); + return dlfb_set_register(buf, 0x00, selection); } -static char *insert_set_base16bpp(char *wrptr, u32 base) +static char *dlfb_set_base16bpp(char *wrptr, u32 base) { /* the base pointer is 16 bits wide, 0x20 is hi byte. */ - wrptr = insert_command(wrptr, 0x20, base >> 16); - wrptr = insert_command(wrptr, 0x21, base >> 8); - return insert_command(wrptr, 0x22, base); + wrptr = dlfb_set_register(wrptr, 0x20, base >> 16); + wrptr = dlfb_set_register(wrptr, 0x21, base >> 8); + return dlfb_set_register(wrptr, 0x22, base); } -static char *insert_set_base8bpp(char *wrptr, u32 base) +static char *dlfb_set_base8bpp(char *wrptr, u32 base) { - wrptr = insert_command(wrptr, 0x26, base >> 16); - wrptr = insert_command(wrptr, 0x27, base >> 8); - return insert_command(wrptr, 0x28, base); + wrptr = dlfb_set_register(wrptr, 0x26, base >> 16); + wrptr = dlfb_set_register(wrptr, 0x27, base >> 8); + return dlfb_set_register(wrptr, 0x28, base); } -static char *insert_command_16(char *wrptr, u8 reg, u16 value) +static char *dlfb_set_register_16(char *wrptr, u8 reg, u16 value) { - wrptr = insert_command(wrptr, reg, value >> 8); - return insert_command(wrptr, reg+1, value); + wrptr = dlfb_set_register(wrptr, reg, value >> 8); + return dlfb_set_register(wrptr, reg+1, value); } /* * This is kind of weird because the controller takes some * register values in a different byte order than other registers. */ -static char *insert_command_16be(char *wrptr, u8 reg, u16 value) +static char *dlfb_set_register_16be(char *wrptr, u8 reg, u16 value) { - wrptr = insert_command(wrptr, reg, value); - return insert_command(wrptr, reg+1, value >> 8); + wrptr = dlfb_set_register(wrptr, reg, value); + return dlfb_set_register(wrptr, reg+1, value >> 8); } /* @@ -152,64 +152,65 @@ static u16 lfsr16(u16 actual_count) * This does LFSR conversion on the value that is to be written. * See LFSR explanation above for more detail. */ -static char *insert_command_lfsr16(char *wrptr, u8 reg, u16 value) +static char *dlfb_set_register_lfsr16(char *wrptr, u8 reg, u16 value) { - return insert_command_16(wrptr, reg, lfsr16(value)); + return dlfb_set_register_16(wrptr, reg, lfsr16(value)); } /* * This takes a standard fbdev screeninfo struct and all of its monitor mode * details and converts them into the DisplayLink equivalent register commands. */ -static char *insert_set_vid_cmds(char *wrptr, struct fb_var_screeninfo *var) +static char *dlfb_set_vid_cmds(char *wrptr, struct fb_var_screeninfo *var) { u16 xds, yds; u16 xde, yde; u16 yec; - /* x display start */ xds = var->left_margin + var->hsync_len; - wrptr = insert_command_lfsr16(wrptr, 0x01, xds); + wrptr = dlfb_set_register_lfsr16(wrptr, 0x01, xds); /* x display end */ xde = xds + var->xres; - wrptr = insert_command_lfsr16(wrptr, 0x03, xde); + wrptr = dlfb_set_register_lfsr16(wrptr, 0x03, xde); /* y display start */ yds = var->upper_margin + var->vsync_len; - wrptr = insert_command_lfsr16(wrptr, 0x05, yds); + wrptr = dlfb_set_register_lfsr16(wrptr, 0x05, yds); /* y display end */ yde = yds + var->yres; - wrptr = insert_command_lfsr16(wrptr, 0x07, yde); + wrptr = dlfb_set_register_lfsr16(wrptr, 0x07, yde); /* x end count is active + blanking - 1 */ - wrptr = insert_command_lfsr16(wrptr, 0x09, xde + var->right_margin - 1); + wrptr = dlfb_set_register_lfsr16(wrptr, 0x09, + xde + var->right_margin - 1); /* libdlo hardcodes hsync start to 1 */ - wrptr = insert_command_lfsr16(wrptr, 0x0B, 1); + wrptr = dlfb_set_register_lfsr16(wrptr, 0x0B, 1); /* hsync end is width of sync pulse + 1 */ - wrptr = insert_command_lfsr16(wrptr, 0x0D, var->hsync_len + 1); + wrptr = dlfb_set_register_lfsr16(wrptr, 0x0D, var->hsync_len + 1); /* hpixels is active pixels */ - wrptr = insert_command_16(wrptr, 0x0F, var->xres); + wrptr = dlfb_set_register_16(wrptr, 0x0F, var->xres); /* yendcount is vertical active + vertical blanking */ yec = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; - wrptr = insert_command_lfsr16(wrptr, 0x11, yec); + wrptr = dlfb_set_register_lfsr16(wrptr, 0x11, yec); /* libdlo hardcodes vsync start to 0 */ - wrptr = insert_command_lfsr16(wrptr, 0x13, 0); + wrptr = dlfb_set_register_lfsr16(wrptr, 0x13, 0); /* vsync end is width of vsync pulse */ - wrptr = insert_command_lfsr16(wrptr, 0x15, var->vsync_len); + wrptr = dlfb_set_register_lfsr16(wrptr, 0x15, var->vsync_len); /* vpixels is active pixels */ - wrptr = insert_command_16(wrptr, 0x17, var->yres); + wrptr = dlfb_set_register_16(wrptr, 0x17, var->yres); /* convert picoseconds to 5kHz multiple for pclk5k = x * 1E12/5k */ - wrptr = insert_command_16be(wrptr, 0x1B, 200*1000*1000/var->pixclock); + wrptr = dlfb_set_register_16be(wrptr, 0x1B, + 200*1000*1000/var->pixclock); return wrptr; } @@ -234,16 +235,16 @@ static int dlfb_set_video_mode(struct dlfb_data *dev, * controller * associated with the display. There are 2 base * pointers, currently, we only * use the 16 bpp segment. */ - wrptr = insert_vidreg_lock(buf); - wrptr = insert_set_color_depth(wrptr, 0x00); + wrptr = dlfb_vidreg_lock(buf); + wrptr = dlfb_set_color_depth(wrptr, 0x00); /* set base for 16bpp segment to 0 */ - wrptr = insert_set_base16bpp(wrptr, 0); + wrptr = dlfb_set_base16bpp(wrptr, 0); /* set base for 8bpp segment to end of fb */ - wrptr = insert_set_base8bpp(wrptr, dev->info->fix.smem_len); + wrptr = dlfb_set_base8bpp(wrptr, dev->info->fix.smem_len); - wrptr = insert_set_vid_cmds(wrptr, var); - wrptr = insert_enable_hvsync(wrptr); - wrptr = insert_vidreg_unlock(wrptr); + wrptr = dlfb_set_vid_cmds(wrptr, var); + wrptr = dlfb_enable_hvsync(wrptr); + wrptr = dlfb_vidreg_unlock(wrptr); writesize = wrptr - buf; @@ -284,7 +285,7 @@ static int dlfb_get_var_from_edid(struct dlfb_data *dev, return ret; } -static int dlfb_mmap(struct fb_info *info, struct vm_area_struct *vma) +static int dlfb_ops_mmap(struct fb_info *info, struct vm_area_struct *vma) { unsigned long start = vma->vm_start; unsigned long size = vma->vm_end - vma->vm_start; @@ -781,18 +782,18 @@ copyarea(struct dlfb_data *dev_info, int dx, int dy, int sx, int sy, return 1; } -static void dlfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) +static void dlfb_ops_copyarea(struct fb_info *info, + const struct fb_copyarea *area) { - struct dlfb_data *dev = info->par; copyarea(dev, area->dx, area->dy, area->sx, area->sy, area->width, area->height); } -static void dlfb_imageblit(struct fb_info *info, const struct fb_image *image) +static void dlfb_ops_imageblit(struct fb_info *info, + const struct fb_image *image) { - int ret; struct dlfb_data *dev = info->par; cfb_imageblit(info, image); @@ -801,7 +802,7 @@ static void dlfb_imageblit(struct fb_info *info, const struct fb_image *image) info->screen_base); } -static void dlfb_fillrect(struct fb_info *info, +static void dlfb_ops_fillrect(struct fb_info *info, const struct fb_fillrect *region) { @@ -817,9 +818,9 @@ static void dlfb_fillrect(struct fb_info *info, } -static int dlfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) +static int dlfb_ops_ioctl(struct fb_info *info, unsigned int cmd, + unsigned long arg) { - struct dlfb_data *dev_info = info->par; struct dloarea *area = NULL; @@ -875,7 +876,7 @@ static int dlfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) /* taken from vesafb */ static int -dlfb_setcolreg(unsigned regno, unsigned red, unsigned green, +dlfb_ops_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info) { int err = 0; @@ -900,7 +901,7 @@ dlfb_setcolreg(unsigned regno, unsigned red, unsigned green, return err; } -static int dlfb_release(struct fb_info *info, int user) +static int dlfb_ops_release(struct fb_info *info, int user) { struct dlfb_data *dev_info = info->par; image_blit(dev_info, 0, 0, info->var.xres, info->var.yres, @@ -923,7 +924,7 @@ static void dlfb_delete(struct kref *kref) kfree(dev); } -static int dlfb_blank(int blank_mode, struct fb_info *info) +static int dlfb_ops_blank(int blank_mode, struct fb_info *info) { struct dlfb_data *dev_info = info->par; char *bufptr = dev_info->buf; @@ -942,14 +943,14 @@ static int dlfb_blank(int blank_mode, struct fb_info *info) } static struct fb_ops dlfb_ops = { - .fb_setcolreg = dlfb_setcolreg, - .fb_fillrect = dlfb_fillrect, - .fb_copyarea = dlfb_copyarea, - .fb_imageblit = dlfb_imageblit, - .fb_mmap = dlfb_mmap, - .fb_ioctl = dlfb_ioctl, - .fb_release = dlfb_release, - .fb_blank = dlfb_blank, + .fb_setcolreg = dlfb_ops_setcolreg, + .fb_fillrect = dlfb_ops_fillrect, + .fb_copyarea = dlfb_ops_copyarea, + .fb_imageblit = dlfb_ops_imageblit, + .fb_mmap = dlfb_ops_mmap, + .fb_ioctl = dlfb_ops_ioctl, + .fb_release = dlfb_ops_release, + .fb_blank = dlfb_ops_blank, }; /* -- cgit v1.2.3 From 7d9485e2c53caaaed9606a39de1c2746cc9ba262 Mon Sep 17 00:00:00 2001 From: Bernie Thompson Date: Mon, 15 Feb 2010 06:46:08 -0800 Subject: Staging: udlfb: Add functions to expose sysfs metrics and controls Add sysfs controls for edid and performance metrics There are 8 new files exposed in /sys/class/graphics/fb* edid - returns 128 byte edid blog, suitable for parsing with parse-edid metrics_bytes_identical metrics_bytes_rendered metrics_bytes_sent metrics_cpu_kcycles_used metrics_misc and metrics_reset, which resets all perf metrics to zero The 6 perf metrics are of type atomic_t. So these metrics return precise results for short benchmarks, but any test approx a minute or longer runtime may roll over. Signed-off-by: Bernie Thompson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/udlfb/udlfb.c | 251 ++++++++++++++++++++++++++++++++++++++++++ drivers/staging/udlfb/udlfb.h | 18 +++ 2 files changed, 269 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/udlfb/udlfb.c b/drivers/staging/udlfb/udlfb.c index 8d8372fd1b36..01672df7a243 100644 --- a/drivers/staging/udlfb/udlfb.c +++ b/drivers/staging/udlfb/udlfb.c @@ -818,6 +818,21 @@ static void dlfb_ops_fillrect(struct fb_info *info, } +static void dlfb_get_edid(struct dlfb_data *dev) +{ + int i; + int ret; + char rbuf[2]; + + for (i = 0; i < sizeof(dev->edid); i++) { + ret = usb_control_msg(dev->udev, + usb_rcvctrlpipe(dev->udev, 0), (0x02), + (0x80 | (0x02 << 5)), i << 8, 0xA1, rbuf, 2, + 0); + dev->edid[i] = rbuf[1]; + } +} + static int dlfb_ops_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) { @@ -924,6 +939,33 @@ static void dlfb_delete(struct kref *kref) kfree(dev); } +/* + * Check whether a video mode is supported by the DisplayLink chip + * We start from monitor's modes, so don't need to filter that here + */ +static int dlfb_is_valid_mode(struct fb_videomode *mode, + struct fb_info *info) +{ + struct dlfb_data *dev = info->par; + + if (mode->xres * mode->yres > dev->sku_pixel_limit) + return 0; + + return 1; +} + +static void dlfb_var_color_format(struct fb_var_screeninfo *var) +{ + const struct fb_bitfield red = { 11, 5, 0 }; + const struct fb_bitfield green = { 5, 6, 0 }; + const struct fb_bitfield blue = { 0, 5, 0 }; + + var->bits_per_pixel = 16; + var->red = red; + var->green = green; + var->blue = blue; +} + static int dlfb_ops_blank(int blank_mode, struct fb_info *info) { struct dlfb_data *dev_info = info->par; @@ -953,6 +995,215 @@ static struct fb_ops dlfb_ops = { .fb_blank = dlfb_ops_blank, }; +/* + * Calls dlfb_get_edid() to query the EDID of attached monitor via usb cmds + * Then parses EDID into three places used by various parts of fbdev: + * fb_var_screeninfo contains the timing of the monitor's preferred mode + * fb_info.monspecs is full parsed EDID info, including monspecs.modedb + * fb_info.modelist is a linked list of all monitor & VESA modes which work + * + * If EDID is not readable/valid, then modelist is all VESA modes, + * monspecs is NULL, and fb_var_screeninfo is set to safe VESA mode + * Returns 0 if EDID parses successfully + */ +static int dlfb_parse_edid(struct dlfb_data *dev, + struct fb_var_screeninfo *var, + struct fb_info *info) +{ + int i; + const struct fb_videomode *default_vmode = NULL; + int result = 0; + + fb_destroy_modelist(&info->modelist); + memset(&info->monspecs, 0, sizeof(info->monspecs)); + + dlfb_get_edid(dev); + fb_edid_to_monspecs(dev->edid, &info->monspecs); + + if (info->monspecs.modedb_len > 0) { + + for (i = 0; i < info->monspecs.modedb_len; i++) { + if (dlfb_is_valid_mode(&info->monspecs.modedb[i], info)) + fb_add_videomode(&info->monspecs.modedb[i], + &info->modelist); + } + + default_vmode = fb_find_best_display(&info->monspecs, + &info->modelist); + } else { + struct fb_videomode fb_vmode = {0}; + + dl_err("Unable to get valid EDID from device/display\n"); + result = 1; + + /* + * Add the standard VESA modes to our modelist + * Since we don't have EDID, there may be modes that + * overspec monitor and/or are incorrect aspect ratio, etc. + * But at least the user has a chance to choose + */ + for (i = 0; i < VESA_MODEDB_SIZE; i++) { + if (dlfb_is_valid_mode((struct fb_videomode *) + &vesa_modes[i], info)) + fb_add_videomode(&vesa_modes[i], + &info->modelist); + } + + /* + * default to resolution safe for projectors + * (since they are most common case without EDID) + */ + fb_vmode.xres = 800; + fb_vmode.yres = 600; + fb_vmode.refresh = 60; + default_vmode = fb_find_nearest_mode(&fb_vmode, + &info->modelist); + } + + fb_videomode_to_var(var, default_vmode); + dlfb_var_color_format(var); + + return result; +} + +static ssize_t metrics_bytes_rendered_show(struct device *fbdev, + struct device_attribute *a, char *buf) { + struct fb_info *fb_info = dev_get_drvdata(fbdev); + struct dlfb_data *dev = fb_info->par; + return snprintf(buf, PAGE_SIZE, "%u\n", + atomic_read(&dev->bytes_rendered)); +} + +static ssize_t metrics_bytes_identical_show(struct device *fbdev, + struct device_attribute *a, char *buf) { + struct fb_info *fb_info = dev_get_drvdata(fbdev); + struct dlfb_data *dev = fb_info->par; + return snprintf(buf, PAGE_SIZE, "%u\n", + atomic_read(&dev->bytes_identical)); +} + +static ssize_t metrics_bytes_sent_show(struct device *fbdev, + struct device_attribute *a, char *buf) { + struct fb_info *fb_info = dev_get_drvdata(fbdev); + struct dlfb_data *dev = fb_info->par; + return snprintf(buf, PAGE_SIZE, "%u\n", + atomic_read(&dev->bytes_sent)); +} + +static ssize_t metrics_cpu_kcycles_used_show(struct device *fbdev, + struct device_attribute *a, char *buf) { + struct fb_info *fb_info = dev_get_drvdata(fbdev); + struct dlfb_data *dev = fb_info->par; + return snprintf(buf, PAGE_SIZE, "%u\n", + atomic_read(&dev->cpu_kcycles_used)); +} + +static ssize_t metrics_misc_show(struct device *fbdev, + struct device_attribute *a, char *buf) { + struct fb_info *fb_info = dev_get_drvdata(fbdev); + struct dlfb_data *dev = fb_info->par; + return snprintf(buf, PAGE_SIZE, + "Calls to\ndamage: %u\nblit: %u\n" + "defio faults: %u\ncopy: %u\n" + "fill: %u\n\n" + "active framebuffer clients: %d\n" + "urbs available %d(%d)\n" + "Shadow framebuffer in use? %s\n" + "Any lost pixels? %s\n", + atomic_read(&dev->damage_count), + atomic_read(&dev->blit_count), + atomic_read(&dev->defio_fault_count), + atomic_read(&dev->copy_count), + atomic_read(&dev->fill_count), + dev->fb_count, + dev->urbs.available, dev->urbs.limit_sem.count, + (dev->backing_buffer) ? "yes" : "no", + atomic_read(&dev->lost_pixels) ? "yes" : "no"); +} + +static ssize_t edid_show(struct kobject *kobj, struct bin_attribute *a, + char *buf, loff_t off, size_t count) { + struct device *fbdev = container_of(kobj, struct device, kobj); + struct fb_info *fb_info = dev_get_drvdata(fbdev); + struct dlfb_data *dev = fb_info->par; + char *edid = &dev->edid[0]; + const size_t size = sizeof(dev->edid); + + if (dlfb_parse_edid(dev, &fb_info->var, fb_info)) + return 0; + + if (off >= size) + return 0; + + if (off + count > size) + count = size - off; + memcpy(buf, edid + off, count); + + return count; +} + + +static ssize_t metrics_reset_store(struct device *fbdev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fb_info *fb_info = dev_get_drvdata(fbdev); + struct dlfb_data *dev = fb_info->par; + + atomic_set(&dev->bytes_rendered, 0); + atomic_set(&dev->bytes_identical, 0); + atomic_set(&dev->bytes_sent, 0); + atomic_set(&dev->cpu_kcycles_used, 0); + atomic_set(&dev->blit_count, 0); + atomic_set(&dev->copy_count, 0); + atomic_set(&dev->fill_count, 0); + atomic_set(&dev->defio_fault_count, 0); + atomic_set(&dev->damage_count, 0); + + return count; +} + +static ssize_t use_defio_show(struct device *fbdev, + struct device_attribute *a, char *buf) { + struct fb_info *fb_info = dev_get_drvdata(fbdev); + struct dlfb_data *dev = fb_info->par; + return snprintf(buf, PAGE_SIZE, "%d\n", + atomic_read(&dev->use_defio)); +} + +static ssize_t use_defio_store(struct device *fbdev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fb_info *fb_info = dev_get_drvdata(fbdev); + struct dlfb_data *dev = fb_info->par; + + if (count > 0) { + if (buf[0] == '0') + atomic_set(&dev->use_defio, 0); + if (buf[0] == '1') + atomic_set(&dev->use_defio, 1); + } + return count; +} + +static struct bin_attribute edid_attr = { + .attr.name = "edid", + .attr.mode = 0444, + .size = 128, + .read = edid_show, +}; + +static struct device_attribute fb_device_attrs[] = { + __ATTR_RO(metrics_bytes_rendered), + __ATTR_RO(metrics_bytes_identical), + __ATTR_RO(metrics_bytes_sent), + __ATTR_RO(metrics_cpu_kcycles_used), + __ATTR_RO(metrics_misc), + __ATTR(metrics_reset, S_IWUGO, NULL, metrics_reset_store), + __ATTR_RW(use_defio), +}; + /* * This is necessary before we can communicate with the display controller. */ diff --git a/drivers/staging/udlfb/udlfb.h b/drivers/staging/udlfb/udlfb.h index 13f992fe45f7..ef343a6052d6 100644 --- a/drivers/staging/udlfb/udlfb.h +++ b/drivers/staging/udlfb/udlfb.h @@ -33,8 +33,12 @@ struct dlfb_data { char *bufend; char *backing_buffer; struct mutex bulk_mutex; + int fb_count; + atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */ atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */ + atomic_t use_defio; /* 0 = rely on ioctls and blit/copy/fill rects */ char edid[128]; + int sku_pixel_limit; int screen_size; int line_length; struct completion done; @@ -43,6 +47,17 @@ struct dlfb_data { int base8; int base8d; u32 pseudo_palette[256]; + /* blit-only rendering path metrics, exposed through sysfs */ + atomic_t bytes_rendered; /* raw pixel-bytes driver asked to render */ + atomic_t bytes_identical; /* saved effort with backbuffer comparison */ + atomic_t bytes_sent; /* to usb, after compression including overhead */ + atomic_t cpu_kcycles_used; /* transpired during pixel processing */ + /* interface usage metrics. Clients can call driver via several */ + atomic_t blit_count; + atomic_t copy_count; + atomic_t fill_count; + atomic_t damage_count; + atomic_t defio_fault_count; }; #define NR_USB_REQUEST_I2C_SUB_IO 0x02 @@ -99,6 +114,9 @@ static int dlfb_bulk_msg(struct dlfb_data *dev_info, int len) #define dlfb_set_register insert_command +/* remove once this gets added to sysfs.h */ +#define __ATTR_RW(attr) __ATTR(attr, 0644, attr##_show, attr##_store) + #define dl_err(format, arg...) \ dev_err(dev->gdev, "dlfb: " format, ## arg) #define dl_warn(format, arg...) \ -- cgit v1.2.3 From 2469d5dbcafe064859475a8aaf8da00ab33d440c Mon Sep 17 00:00:00 2001 From: Bernie Thompson Date: Mon, 15 Feb 2010 06:46:13 -0800 Subject: Staging: udlfb: Rework startup and teardown to fix race conditions Rework probe to use refcounts and std functions Because the different parts of the driver (usb, fbdev) tear down in different orders, the driver previously could crash accessing data that had already been freed. Refcounting system used to handle. Reworked probe to make use of refcounts, set mode using std fbops, and set up sysfs and pre-allocated urbs. Signed-off-by: Bernie Thompson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/udlfb/udlfb.c | 304 +++++++++++++++++++++++++++--------------- drivers/staging/udlfb/udlfb.h | 3 +- 2 files changed, 198 insertions(+), 109 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/udlfb/udlfb.c b/drivers/staging/udlfb/udlfb.c index 01672df7a243..8ee55c86cff7 100644 --- a/drivers/staging/udlfb/udlfb.c +++ b/drivers/staging/udlfb/udlfb.c @@ -3,6 +3,7 @@ * * Copyright (C) 2009 Roberto De Ioris * Copyright (C) 2009 Jaya Kumar + * Copyright (C) 2009 Bernie Thompson * * This file is subject to the terms and conditions of the GNU General Public * License v2. See the file COPYING in the main directory of this archive for @@ -27,10 +28,8 @@ #include "udlfb.h" -#define DRIVER_VERSION "DisplayLink Framebuffer Driver 0.4.1" - static struct fb_fix_screeninfo dlfb_fix = { - .id = "displaylinkfb", + .id = "udlfb", .type = FB_TYPE_PACKED_PIXELS, .visual = FB_VISUAL_TRUECOLOR, .xpanstep = 0, @@ -39,6 +38,13 @@ static struct fb_fix_screeninfo dlfb_fix = { .accel = FB_ACCEL_NONE, }; +static const u32 udlfb_info_flags = FBINFO_DEFAULT | FBINFO_READS_FAST | +#ifdef FBINFO_VIRTFB + FBINFO_VIRTFB | +#endif + FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT | + FBINFO_HWACCEL_COPYAREA | FBINFO_MISC_ALWAYS_SETPAR; + /* * There are many DisplayLink-based products, all with unique PIDs. We are able * to support all volume ones (circa 2009) with a single driver, so we match @@ -939,6 +945,29 @@ static void dlfb_delete(struct kref *kref) kfree(dev); } +/* + * Called by fbdev as last part of unregister_framebuffer() process + * No new clients can open connections. Deallocate everything fb_info. + */ +static void dlfb_ops_destroy(struct fb_info *info) +{ + struct dlfb_data *dev = info->par; + + if (info->cmap.len != 0) + fb_dealloc_cmap(&info->cmap); + if (info->monspecs.modedb) + fb_destroy_modedb(info->monspecs.modedb); + if (info->screen_base) + vfree(info->screen_base); + + fb_destroy_modelist(&info->modelist); + + framebuffer_release(info); + + /* ref taken before register_framebuffer() for dlfb_data clients */ + kref_put(&dev->kref, dlfb_delete); +} + /* * Check whether a video mode is supported by the DisplayLink chip * We start from monitor's modes, so don't need to filter that here @@ -966,6 +995,35 @@ static void dlfb_var_color_format(struct fb_var_screeninfo *var) var->blue = blue; } +static int dlfb_ops_check_var(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct fb_videomode mode; + + /* TODO: support dynamically changing framebuffer size */ + if ((var->xres * var->yres * 2) > info->fix.smem_len) + return -EINVAL; + + /* set device-specific elements of var unrelated to mode */ + dlfb_var_color_format(var); + + fb_var_to_videomode(&mode, var); + + if (!dlfb_is_valid_mode(&mode, info)) + return -EINVAL; + + return 0; +} + +static int dlfb_ops_set_par(struct fb_info *info) +{ + struct dlfb_data *dev = info->par; + + dl_notice("set_par mode %dx%d\n", info->var.xres, info->var.yres); + + return dlfb_set_video_mode(dev, &info->var); +} + static int dlfb_ops_blank(int blank_mode, struct fb_info *info) { struct dlfb_data *dev_info = info->par; @@ -985,6 +1043,7 @@ static int dlfb_ops_blank(int blank_mode, struct fb_info *info) } static struct fb_ops dlfb_ops = { + .owner = THIS_MODULE, .fb_setcolreg = dlfb_ops_setcolreg, .fb_fillrect = dlfb_ops_fillrect, .fb_copyarea = dlfb_ops_copyarea, @@ -993,6 +1052,8 @@ static struct fb_ops dlfb_ops = { .fb_ioctl = dlfb_ops_ioctl, .fb_release = dlfb_ops_release, .fb_blank = dlfb_ops_blank, + .fb_check_var = dlfb_ops_check_var, + .fb_set_par = dlfb_ops_set_par, }; /* @@ -1222,37 +1283,48 @@ static int dlfb_select_std_channel(struct dlfb_data *dev) return ret; } -static int dlfb_probe(struct usb_interface *interface, + +static int dlfb_usb_probe(struct usb_interface *interface, const struct usb_device_id *id) { - struct device *mydev; struct usb_device *usbdev; struct dlfb_data *dev; struct fb_info *info; int videomemorysize; + int i; unsigned char *videomemory; int retval = -ENOMEM; struct fb_var_screeninfo *var; - struct fb_bitfield red = { 11, 5, 0 }; - struct fb_bitfield green = { 5, 6, 0 }; - struct fb_bitfield blue = { 0, 5, 0 }; + int registered = 0; + u16 *pix_framebuffer; - usbdev = usb_get_dev(interface_to_usbdev(interface)); - mydev = &usbdev->dev; + /* usb initialization */ + + usbdev = interface_to_usbdev(interface); dev = kzalloc(sizeof(*dev), GFP_KERNEL); if (dev == NULL) { - dev_err(mydev, "failed alloc of dev struct\n"); - goto err_devalloc; + err("dlfb_usb_probe: failed alloc of dev struct\n"); + goto error; } + /* we need to wait for both usb and fbdev to spin down on disconnect */ + kref_init(&dev->kref); /* matching kref_put in usb .disconnect fn */ + kref_get(&dev->kref); /* matching kref_put in .fb_destroy function*/ + mutex_init(&dev->bulk_mutex); + dev->udev = usbdev; dev->gdev = &usbdev->dev; /* our generic struct device * */ - dev->interface = interface; usb_set_intfdata(interface, dev); - dev_info(mydev, "dlfb_probe: setting up DisplayLink device\n"); + if (!dlfb_alloc_urb_list(dev, WRITES_IN_FLIGHT, MAX_TRANSFER)) { + retval = -ENOMEM; + dl_err("dlfb_alloc_urb_list failed\n"); + goto error; + } + + mutex_init(&dev->fb_open_lock); /* * TODO: replace single 64K buffer with buffer list @@ -1260,8 +1332,8 @@ static int dlfb_probe(struct usb_interface *interface, */ dev->buf = kmalloc(BUF_SIZE, GFP_KERNEL); if (dev->buf == NULL) { - dev_err(mydev, "unable to allocate memory for dlfb commands\n"); - goto err_usballoc; + dl_err("unable to allocate memory for dlfb commands\n"); + goto error; } dev->bufend = dev->buf + BUF_SIZE; @@ -1270,49 +1342,51 @@ static int dlfb_probe(struct usb_interface *interface, usb_sndbulkpipe(dev->udev, 1), dev->buf, 0, dlfb_bulk_callback, dev); - /* allocates framebuffer driver structure, not framebuffer memory */ - info = framebuffer_alloc(0, mydev); - if (!info) - goto err_fballoc; + /* We don't register a new USB class. Our client interface is fbdev */ + /* allocates framebuffer driver structure, not framebuffer memory */ + info = framebuffer_alloc(0, &usbdev->dev); + if (!info) { + retval = -ENOMEM; + dl_err("framebuffer_alloc failed\n"); + goto error; + } dev->info = info; info->par = dev; info->pseudo_palette = dev->pseudo_palette; + info->fbops = &dlfb_ops; var = &info->var; - retval = dlfb_get_var_from_edid(dev, var); - if (retval) { - /* had a problem getting edid. so fallback to 640x480 */ - dev_err(mydev, "Problem %d with EDID.\n", retval); - var->xres = 640; - var->yres = 480; - } + + /* TODO set limit based on actual SKU detection */ + dev->sku_pixel_limit = 2048 * 1152; + + INIT_LIST_HEAD(&info->modelist); + dlfb_parse_edid(dev, var, info); /* * ok, now that we've got the size info, we can alloc our framebuffer. - * We are using 16bpp. */ - info->var.bits_per_pixel = 16; info->fix = dlfb_fix; info->fix.line_length = var->xres * (var->bits_per_pixel / 8); videomemorysize = info->fix.line_length * var->yres; /* * The big chunk of system memory we use as a virtual framebuffer. - * Pages don't need to be set RESERVED (non-swap) immediately on 2.6 - * remap_pfn_page() syscall in our mmap and/or defio will handle. + * TODO: Handle fbcon cursor code calling blit in interrupt context */ videomemory = vmalloc(videomemorysize); - if (!videomemory) - goto err_vidmem; - memset(videomemory, 0, videomemorysize); + if (!videomemory) { + retval = -ENOMEM; + dl_err("Virtual framebuffer alloc failed\n"); + goto error; + } info->screen_base = videomemory; info->fix.smem_len = PAGE_ALIGN(videomemorysize); info->fix.smem_start = (unsigned long) videomemory; - info->flags = - FBINFO_DEFAULT | FBINFO_READS_FAST | FBINFO_HWACCEL_IMAGEBLIT | - FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT; + info->flags = udlfb_info_flags; + /* * Second framebuffer copy, mirroring the state of the framebuffer @@ -1320,109 +1394,121 @@ static int dlfb_probe(struct usb_interface *interface, * But with imperfect damage info we may end up sending pixels over USB * that were, in fact, unchanged -- wasting limited USB bandwidth */ - dev->backing_buffer = vmalloc(dev->screen_size); + dev->backing_buffer = vmalloc(videomemorysize); if (!dev->backing_buffer) - dev_info(mydev, "No backing buffer allocated!\n"); + dl_warn("No shadow/backing buffer allcoated\n"); + else + memset(dev->backing_buffer, 0, videomemorysize); - info->fbops = &dlfb_ops; + retval = fb_alloc_cmap(&info->cmap, 256, 0); + if (retval < 0) { + dl_err("fb_alloc_cmap failed %x\n", retval); + goto error; + } - var->vmode = FB_VMODE_NONINTERLACED; - var->red = red; - var->green = green; - var->blue = blue; + /* ready to begin using device */ - /* - * TODO: Enable FB_CONFIG_DEFIO support +/* +#ifdef CONFIG_FB_DEFERRED_IO + atomic_set(&dev->use_defio, 1); +#endif +*/ + atomic_set(&dev->usb_active, 1); + dlfb_select_std_channel(dev); - info->fbdefio = &dlfb_defio; - fb_deferred_io_init(info); + dlfb_ops_check_var(var, info); + dlfb_ops_set_par(info); - */ + /* paint greenscreen */ +/* + pix_framebuffer = (u16 *) videomemory; + for (i = 0; i < videomemorysize / 2; i++) + pix_framebuffer[i] = 0x37e6; - retval = fb_alloc_cmap(&info->cmap, 256, 0); + dlfb_handle_damage(dev, 0, 0, info->var.xres, info->var.yres, + videomemory); +*/ + retval = register_framebuffer(info); if (retval < 0) { - dev_err(mydev, "Failed to allocate colormap\n"); - goto err_cmap; + dl_err("register_framebuffer failed %d\n", retval); + goto error; } + registered = 1; - dlfb_select_std_channel(dev); - dlfb_set_video_mode(dev, var); - /* TODO: dlfb_dpy_update(dev); */ - - retval = register_framebuffer(info); - if (retval < 0) - goto err_regfb; + for (i = 0; i < ARRAY_SIZE(fb_device_attrs); i++) + device_create_file(info->dev, &fb_device_attrs[i]); - /* paint "successful" green screen */ - draw_rect(dev, 0, 0, dev->info->var.xres, - dev->info->var.yres, 0x30, 0xff, 0x30); + device_create_bin_file(info->dev, &edid_attr); - dev_info(mydev, "DisplayLink USB device %d now attached, " - "using %dK of memory\n", info->node, - ((dev->backing_buffer) ? - videomemorysize * 2 : videomemorysize) >> 10); + dl_err("DisplayLink USB device /dev/fb%d attached. %dx%d resolution." + " Using %dK framebuffer memory\n", info->node, + var->xres, var->yres, + ((dev->backing_buffer) ? + videomemorysize * 2 : videomemorysize) >> 10); return 0; -err_regfb: - fb_dealloc_cmap(&info->cmap); -err_cmap: - /* TODO: fb_deferred_io_cleanup(info); */ - vfree(videomemory); -err_vidmem: - framebuffer_release(info); -err_fballoc: - kfree(dev->buf); -err_usballoc: - usb_set_intfdata(interface, NULL); - usb_put_dev(dev->udev); - kfree(dev); -err_devalloc: +error: + if (dev) { + if (registered) { + unregister_framebuffer(info); + dlfb_ops_destroy(info); + } else + kref_put(&dev->kref, dlfb_delete); + + if (dev->urbs.count > 0) + dlfb_free_urb_list(dev); + kref_put(&dev->kref, dlfb_delete); /* last ref from kref_init */ + + /* dev has been deallocated. Do not dereference */ + } + return retval; } -static void dlfb_disconnect(struct usb_interface *interface) +static void dlfb_usb_disconnect(struct usb_interface *interface) { struct dlfb_data *dev; struct fb_info *info; + int i; dev = usb_get_intfdata(interface); + info = dev->info; + + /* when non-active we'll update virtual framebuffer, but no new urbs */ + atomic_set(&dev->usb_active, 0); + usb_set_intfdata(interface, NULL); - usb_put_dev(dev->udev); - /* - * TODO: since, upon usb disconnect(), usb will cancel in-flight urbs - * and error out any new ones, look at eliminating need for mutex - */ - mutex_lock(&dev->bulk_mutex); - dev->interface = NULL; - info = dev->info; - mutex_unlock(&dev->bulk_mutex); + for (i = 0; i < ARRAY_SIZE(fb_device_attrs); i++) + device_remove_file(info->dev, &fb_device_attrs[i]); + + device_remove_bin_file(info->dev, &edid_attr); + + /* this function will wait for all in-flight urbs to complete */ + dlfb_free_urb_list(dev); if (info) { - dev_info(&interface->dev, "Detaching DisplayLink device %d.\n", - info->node); + dl_notice("Detaching /dev/fb%d\n", info->node); unregister_framebuffer(info); - fb_dealloc_cmap(&info->cmap); - /* TODO: fb_deferred_io_cleanup(info); */ - fb_dealloc_cmap(&info->cmap); - vfree((void __force *)info->screen_base); - framebuffer_release(info); + dlfb_ops_destroy(info); } - if (dev->backing_buffer) - vfree(dev->backing_buffer); + /* release reference taken by kref_init in probe() */ + kref_put(&dev->kref, dlfb_delete); - kfree(dev); + /* consider dlfb_data freed */ + + return; } static struct usb_driver dlfb_driver = { .name = "udlfb", - .probe = dlfb_probe, - .disconnect = dlfb_disconnect, + .probe = dlfb_usb_probe, + .disconnect = dlfb_usb_disconnect, .id_table = id_table, }; -static int __init dlfb_init(void) +static int __init dlfb_module_init(void) { int res; @@ -1435,13 +1521,13 @@ static int __init dlfb_init(void) return res; } -static void __exit dlfb_exit(void) +static void __exit dlfb_module_exit(void) { usb_deregister(&dlfb_driver); } -module_init(dlfb_init); -module_exit(dlfb_exit); +module_init(dlfb_module_init); +module_exit(dlfb_module_exit); static void dlfb_urb_completion(struct urb *urb) { @@ -1613,6 +1699,8 @@ static int dlfb_submit_urb(struct dlfb_data *dev, struct urb *urb, size_t len) } MODULE_AUTHOR("Roberto De Ioris , " - "Jaya Kumar "); -MODULE_DESCRIPTION(DRIVER_VERSION); + "Jaya Kumar , " + "Bernie Thompson "); +MODULE_DESCRIPTION("DisplayLink kernel framebuffer driver"); MODULE_LICENSE("GPL"); + diff --git a/drivers/staging/udlfb/udlfb.h b/drivers/staging/udlfb/udlfb.h index ef343a6052d6..e6c68c654677 100644 --- a/drivers/staging/udlfb/udlfb.h +++ b/drivers/staging/udlfb/udlfb.h @@ -25,13 +25,14 @@ struct dlfb_data { struct device *gdev; /* &udev->dev */ struct usb_interface *interface; struct urb *tx_urb, *ctrl_urb; - struct usb_ctrlrequest dr; struct fb_info *info; struct urb_list urbs; struct kref kref; char *buf; char *bufend; char *backing_buffer; + struct delayed_work deferred_work; + struct mutex fb_open_lock; struct mutex bulk_mutex; int fb_count; atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */ -- cgit v1.2.3 From 530f43a8a69d9fa10ec6d30652244bb5e2a29694 Mon Sep 17 00:00:00 2001 From: Bernie Thompson Date: Mon, 15 Feb 2010 06:46:21 -0800 Subject: Staging: udlfb: improved rendering performance Rework rendering for improved performance Approx 10-20% gain avg across several "benchmarks": x11perf, gtkperf, glxgears Moves from a single pre-alloc'd urb protected by a long-held mutex To a list of (4) pre-alloc'd urbs which can be dispatched asynchonously Improved rendering algorithm to hardware with lower CPU consumption, fewer system memory accesses, and slightly higher compression. Better scalability to multiple processors, especially with multiple framebuffers active. Signed-off-by: Bernie Thompson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/udlfb/udlfb.c | 842 ++++++++++++++++-------------------------- drivers/staging/udlfb/udlfb.h | 79 ++-- 2 files changed, 341 insertions(+), 580 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/udlfb/udlfb.c b/drivers/staging/udlfb/udlfb.c index 8ee55c86cff7..22f3dc310ff2 100644 --- a/drivers/staging/udlfb/udlfb.c +++ b/drivers/staging/udlfb/udlfb.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include "udlfb.h" @@ -88,12 +87,14 @@ static char *dlfb_vidreg_unlock(char *buf) } /* - * Once you send this command, the DisplayLink framebuffer gets driven to the - * display. + * On/Off for driving the DisplayLink framebuffer to the display */ -static char *dlfb_enable_hvsync(char *buf) +static char *dlfb_enable_hvsync(char *buf, bool enable) { - return dlfb_set_register(buf, 0x1F, 0x00); + if (enable) + return dlfb_set_register(buf, 0x1F, 0x00); + else + return dlfb_set_register(buf, 0x1F, 0x01); } static char *dlfb_set_color_depth(char *buf, u8 selection) @@ -233,8 +234,15 @@ static int dlfb_set_video_mode(struct dlfb_data *dev, char *wrptr; int retval = 0; int writesize; + struct urb *urb; - buf = dev->buf; + if (!atomic_read(&dev->usb_active)) + return -EPERM; + + urb = dlfb_get_urb(dev); + if (!urb) + return -ENOMEM; + buf = (char *) urb->transfer_buffer; /* * This first section has to do with setting the base address on the @@ -249,48 +257,16 @@ static int dlfb_set_video_mode(struct dlfb_data *dev, wrptr = dlfb_set_base8bpp(wrptr, dev->info->fix.smem_len); wrptr = dlfb_set_vid_cmds(wrptr, var); - wrptr = dlfb_enable_hvsync(wrptr); + wrptr = dlfb_enable_hvsync(wrptr, true); wrptr = dlfb_vidreg_unlock(wrptr); writesize = wrptr - buf; - mutex_lock(&dev->bulk_mutex); - if (!dev->interface) { /* disconnect() was called */ - mutex_unlock(&dev->bulk_mutex); - retval = -ENODEV; - goto error; - } - - retval = dlfb_bulk_msg(dev, writesize); - mutex_unlock(&dev->bulk_mutex); - if (retval) { - dev_err(&dev->udev->dev, "Problem %d with submit write bulk.\n", - retval); - goto error; - } - - return 0; + retval = dlfb_submit_urb(dev, urb, writesize); -error: return retval; } - -/* - * Query EDID from the handware, then hand it off to fbdev's edid parse - * routine which should give us back a filled in screeninfo structure. - */ -static int dlfb_get_var_from_edid(struct dlfb_data *dev, - struct fb_var_screeninfo *var) -{ - int ret; - - dlfb_edid(dev); - ret = fb_parse_edid(dev->edid, var); - - return ret; -} - static int dlfb_ops_mmap(struct fb_info *info, struct vm_area_struct *vma) { unsigned long start = vma->vm_start; @@ -323,504 +299,333 @@ static int dlfb_ops_mmap(struct fb_info *info, struct vm_area_struct *vma) } -/* ioctl structure */ -struct dloarea { - int x, y; - int w, h; - int x2, y2; -}; - -static struct usb_driver dlfb_driver; - -/* thanks to Henrik Bjerregaard Pedersen for this function */ -static char *rle_compress16(uint16_t * src, char *dst, int rem) +/* + * Trims identical data from front and back of line + * Sets new front buffer address and width + * And returns byte count of identical pixels + * Assumes CPU natural alignment (unsigned long) + * for back and front buffer ptrs and width + */ +static int dlfb_trim_hline(const u8 *bback, const u8 **bfront, int *width_bytes) { + int j, k; + const unsigned long *back = (const unsigned long *) bback; + const unsigned long *front = (const unsigned long *) *bfront; + const int width = *width_bytes / sizeof(unsigned long); + int identical = width; + int start = width; + int end = width; + + prefetch((void *) front); + prefetch((void *) back); + + for (j = 0; j < width; j++) { + if (back[j] != front[j]) { + start = j; + break; + } + } - int rl; - uint16_t pix0; - char *end_if_raw = dst + 6 + 2 * rem; - - dst += 6; /* header will be filled in if RLE is worth it */ - - while (rem && dst < end_if_raw) { - char *start = (char *)src; - - pix0 = *src++; - rl = 1; - rem--; - while (rem && *src == pix0) - rem--, rl++, src++; - *dst++ = rl; - *dst++ = start[1]; - *dst++ = start[0]; + for (k = width - 1; k > j; k--) { + if (back[k] != front[k]) { + end = k+1; + break; + } } - return dst; + identical = start + (width - end); + *bfront = (u8 *) &front[start]; + *width_bytes = (end - start) * sizeof(unsigned long); + + return identical * sizeof(unsigned long); } /* -Thanks to Henrik Bjerregaard Pedersen for rle implementation -and code refactoring. Next step is huffman compression. +Render a command stream for an encoded horizontal line segment of pixels. + +A command buffer holds several commands. +It always begins with a fresh command header +(the protocol doesn't require this, but we enforce it to allow +multiple buffers to be potentially encoded and sent in parallel). +A single command encodes one contiguous horizontal line of pixels + +The function relies on the client to do all allocation, so that +rendering can be done directly to output buffers (e.g. USB URBs). +The function fills the supplied command buffer, providing information +on where it left off, so the client may call in again with additional +buffers if the line will take several buffers to complete. + +A single command can transmit a maximum of 256 pixels, +regardless of the compression ratio (protocol design limit). +To the hardware, 0 for a size byte means 256 + +Rather than 256 pixel commands which are either rl or raw encoded, +the rlx command simply assumes alternating raw and rl spans within one cmd. +This has a slightly larger header overhead, but produces more even results. +It also processes all data (read and write) in a single pass. +Performance benchmarks of common cases show it having just slightly better +compression than 256 pixel raw -or- rle commands, with similar CPU consumpion. +But for very rl friendly data, will compress not quite as well. */ - -static int -image_blit(struct dlfb_data *dev_info, int x, int y, int width, int height, - char *data) +static void dlfb_compress_hline( + const uint16_t **pixel_start_ptr, + const uint16_t *const pixel_end, + uint32_t *device_address_ptr, + uint8_t **command_buffer_ptr, + const uint8_t *const cmd_buffer_end) { - - int i, j, base; - int rem = width; - int ret; - - int firstdiff, thistime; - - char *bufptr; - - if (x + width > dev_info->info->var.xres) - return -EINVAL; - - if (y + height > dev_info->info->var.yres) - return -EINVAL; - - mutex_lock(&dev_info->bulk_mutex); - - base = - dev_info->base16 + ((dev_info->info->var.xres * 2 * y) + (x * 2)); - - data += (dev_info->info->var.xres * 2 * y) + (x * 2); - - /* printk("IMAGE_BLIT\n"); */ - - bufptr = dev_info->buf; - - for (i = y; i < y + height; i++) { - - if (dev_info->bufend - bufptr < BUF_HIGH_WATER_MARK) { - ret = dlfb_bulk_msg(dev_info, bufptr - dev_info->buf); - bufptr = dev_info->buf; - } - - rem = width; - - /* printk("WRITING LINE %d\n", i); */ - - while (rem) { - - if (dev_info->bufend - bufptr < BUF_HIGH_WATER_MARK) { - ret = - dlfb_bulk_msg(dev_info, - bufptr - dev_info->buf); - bufptr = dev_info->buf; - } - /* number of pixels to consider this time */ - thistime = rem; - if (thistime > 255) - thistime = 255; - - if (dev_info->backing_buffer) { - /* find first pixel that has changed */ - firstdiff = -1; - for (j = 0; j < thistime * 2; j++) { - if (dev_info->backing_buffer - [base - dev_info->base16 + j] - != data[j]) { - firstdiff = j / 2; - break; - } + const uint16_t *pixel = *pixel_start_ptr; + uint32_t dev_addr = *device_address_ptr; + uint8_t *cmd = *command_buffer_ptr; + const int bpp = 2; + + while ((pixel_end > pixel) && + (cmd_buffer_end - MIN_RLX_CMD_BYTES > cmd)) { + uint8_t *raw_pixels_count_byte = 0; + uint8_t *cmd_pixels_count_byte = 0; + const uint16_t *raw_pixel_start = 0; + const uint16_t *cmd_pixel_start, *cmd_pixel_end = 0; + const uint32_t be_dev_addr = cpu_to_be32(dev_addr); + + prefetchw((void *) cmd); /* pull in one cache line at least */ + + *cmd++ = 0xAF; + *cmd++ = 0x6B; + *cmd++ = (uint8_t) ((be_dev_addr >> 8) & 0xFF); + *cmd++ = (uint8_t) ((be_dev_addr >> 16) & 0xFF); + *cmd++ = (uint8_t) ((be_dev_addr >> 24) & 0xFF); + + cmd_pixels_count_byte = cmd++; /* we'll know this later */ + cmd_pixel_start = pixel; + + raw_pixels_count_byte = cmd++; /* we'll know this later */ + raw_pixel_start = pixel; + + cmd_pixel_end = pixel + min(MAX_CMD_PIXELS + 1, + min((int)(pixel_end - pixel), + (int)(cmd_buffer_end - cmd) / bpp)); + + prefetch_range((void *) pixel, (cmd_pixel_end - pixel) * bpp); + + while (pixel < cmd_pixel_end) { + const uint16_t * const repeating_pixel = pixel; + + *(uint16_t *)cmd = cpu_to_be16p(pixel); + cmd += 2; + pixel++; + + if (unlikely((pixel < cmd_pixel_end) && + (*pixel == *repeating_pixel))) { + /* go back and fill in raw pixel count */ + *raw_pixels_count_byte = ((repeating_pixel - + raw_pixel_start) + 1) & 0xFF; + + while ((pixel < cmd_pixel_end) + && (*pixel == *repeating_pixel)) { + pixel++; } - } else { - firstdiff = 0; + /* immediately after raw data is repeat byte */ + *cmd++ = ((pixel - repeating_pixel) - 1) & 0xFF; + /* Then start another raw pixel span */ + raw_pixel_start = pixel; + raw_pixels_count_byte = cmd++; } - - if (firstdiff >= 0) { - char *end_of_rle; - - end_of_rle = - rle_compress16((uint16_t *) (data + - firstdiff * 2), - bufptr, - thistime - firstdiff); - - if (end_of_rle < - bufptr + 6 + 2 * (thistime - firstdiff)) { - bufptr[0] = 0xAF; - bufptr[1] = 0x69; - - bufptr[2] = - (char)((base + - firstdiff * 2) >> 16); - bufptr[3] = - (char)((base + firstdiff * 2) >> 8); - bufptr[4] = - (char)(base + firstdiff * 2); - bufptr[5] = thistime - firstdiff; - - bufptr = end_of_rle; - - } else { - /* fallback to raw (or other?) */ - *bufptr++ = 0xAF; - *bufptr++ = 0x68; - - *bufptr++ = - (char)((base + - firstdiff * 2) >> 16); - *bufptr++ = - (char)((base + firstdiff * 2) >> 8); - *bufptr++ = - (char)(base + firstdiff * 2); - *bufptr++ = thistime - firstdiff; - for (j = firstdiff * 2; - j < thistime * 2; j += 2) { - *bufptr++ = data[j + 1]; - *bufptr++ = data[j]; - } - } - } - - base += thistime * 2; - data += thistime * 2; - rem -= thistime; } - if (dev_info->backing_buffer) - memcpy(dev_info->backing_buffer + - (base - dev_info->base16) - - (width * 2), data - (width * 2), width * 2); - - base += (dev_info->info->var.xres * 2) - (width * 2); - data += (dev_info->info->var.xres * 2) - (width * 2); + if (pixel > raw_pixel_start) { + /* finalize last RAW span */ + *raw_pixels_count_byte = (pixel-raw_pixel_start) & 0xFF; + } + *cmd_pixels_count_byte = (pixel - cmd_pixel_start) & 0xFF; + dev_addr += (pixel - cmd_pixel_start) * bpp; } - if (bufptr > dev_info->buf) { - ret = dlfb_bulk_msg(dev_info, bufptr - dev_info->buf); + if (cmd_buffer_end <= MIN_RLX_CMD_BYTES + cmd) { + /* Fill leftover bytes with no-ops */ + if (cmd_buffer_end > cmd) + memset(cmd, 0xAF, cmd_buffer_end - cmd); + cmd = (uint8_t *) cmd_buffer_end; } - mutex_unlock(&dev_info->bulk_mutex); - - return base; + *command_buffer_ptr = cmd; + *pixel_start_ptr = pixel; + *device_address_ptr = dev_addr; + return; } -static int -draw_rect(struct dlfb_data *dev_info, int x, int y, int width, int height, - unsigned char red, unsigned char green, unsigned char blue) +/* + * There are 3 copies of every pixel: The front buffer that the fbdev + * client renders to, the actual framebuffer across the USB bus in hardware + * (that we can only write to, slowly, and can never read), and (optionally) + * our shadow copy that tracks what's been sent to that hardware buffer. + */ +static void dlfb_render_hline(struct dlfb_data *dev, struct urb **urb_ptr, + const char *front, char **urb_buf_ptr, + u32 byte_offset, u32 byte_width, + int *ident_ptr, int *sent_ptr) { + const u8 *line_start, *line_end, *next_pixel; + u32 dev_addr = dev->base16 + byte_offset; + struct urb *urb = *urb_ptr; + u8 *cmd = *urb_buf_ptr; + u8 *cmd_end = (u8 *) urb->transfer_buffer + urb->transfer_buffer_length; + + line_start = (u8 *) (front + byte_offset); + next_pixel = line_start; + line_end = next_pixel + byte_width; + + if (dev->backing_buffer) { + int offset; + const u8 *back_start = (u8 *) (dev->backing_buffer + + byte_offset); + + *ident_ptr += dlfb_trim_hline(back_start, &next_pixel, + &byte_width); + + offset = next_pixel - line_start; + line_end = next_pixel + byte_width; + dev_addr += offset; + back_start += offset; + line_start += offset; + + memcpy((char *)back_start, (char *) line_start, + byte_width); + } - int i, j, base; - int ret; - unsigned short col = - (((((red) & 0xF8) | ((green) >> 5)) & 0xFF) << 8) + - (((((green) & 0x1C) << 3) | ((blue) >> 3)) & 0xFF); - int rem = width; - - char *bufptr; - - if (x + width > dev_info->info->var.xres) - return -EINVAL; - - if (y + height > dev_info->info->var.yres) - return -EINVAL; - - mutex_lock(&dev_info->bulk_mutex); - - base = dev_info->base16 + (dev_info->info->var.xres * 2 * y) + (x * 2); - - bufptr = dev_info->buf; - - for (i = y; i < y + height; i++) { - - if (dev_info->backing_buffer) { - for (j = 0; j < width * 2; j += 2) { - dev_info->backing_buffer - [base - dev_info->base16 + j] = - (char)(col >> 8); - dev_info->backing_buffer - [base - dev_info->base16 + j + 1] = - (char)(col); - } - } - - if (dev_info->bufend - bufptr < BUF_HIGH_WATER_MARK) { - ret = dlfb_bulk_msg(dev_info, bufptr - dev_info->buf); - bufptr = dev_info->buf; - } - - rem = width; - - while (rem) { - - if (dev_info->bufend - bufptr < BUF_HIGH_WATER_MARK) { - ret = - dlfb_bulk_msg(dev_info, - bufptr - dev_info->buf); - bufptr = dev_info->buf; - } - - *bufptr++ = 0xAF; - *bufptr++ = 0x69; - - *bufptr++ = (char)(base >> 16); - *bufptr++ = (char)(base >> 8); - *bufptr++ = (char)(base); - - if (rem > 255) { - *bufptr++ = 255; - *bufptr++ = 255; - rem -= 255; - base += 255 * 2; - } else { - *bufptr++ = rem; - *bufptr++ = rem; - base += rem * 2; - rem = 0; - } - - *bufptr++ = (char)(col >> 8); - *bufptr++ = (char)(col); - + while (next_pixel < line_end) { + + dlfb_compress_hline((const uint16_t **) &next_pixel, + (const uint16_t *) line_end, &dev_addr, + (u8 **) &cmd, (u8 *) cmd_end); + + if (cmd >= cmd_end) { + int len = cmd - (u8 *) urb->transfer_buffer; + if (dlfb_submit_urb(dev, urb, len)) + return; /* lost pixels is set */ + *sent_ptr += len; + urb = dlfb_get_urb(dev); + if (!urb) + return; /* lost_pixels is set */ + *urb_ptr = urb; + cmd = urb->transfer_buffer; + cmd_end = &cmd[urb->transfer_buffer_length]; } - - base += (dev_info->info->var.xres * 2) - (width * 2); - } - if (bufptr > dev_info->buf) - ret = dlfb_bulk_msg(dev_info, bufptr - dev_info->buf); - - mutex_unlock(&dev_info->bulk_mutex); - - return 1; + *urb_buf_ptr = cmd; } -static void swapfb(struct dlfb_data *dev_info) +int dlfb_handle_damage(struct dlfb_data *dev, int x, int y, + int width, int height, char *data) { - - int tmpbase; - char *bufptr; - - mutex_lock(&dev_info->bulk_mutex); - - tmpbase = dev_info->base16; - - dev_info->base16 = dev_info->base16d; - dev_info->base16d = tmpbase; - - bufptr = dev_info->buf; - - bufptr = dlfb_set_register(bufptr, 0xFF, 0x00); - - /* set addresses */ - bufptr = - dlfb_set_register(bufptr, 0x20, (char)(dev_info->base16 >> 16)); - bufptr = dlfb_set_register(bufptr, 0x21, (char)(dev_info->base16 >> 8)); - bufptr = dlfb_set_register(bufptr, 0x22, (char)(dev_info->base16)); - - bufptr = dlfb_set_register(bufptr, 0xFF, 0x00); - - dlfb_bulk_msg(dev_info, bufptr - dev_info->buf); - - mutex_unlock(&dev_info->bulk_mutex); -} - -static int copyfb(struct dlfb_data *dev_info) -{ - int base; - int source; - int rem; int i, ret; + char *cmd; + cycles_t start_cycles, end_cycles; + int bytes_sent = 0; + int bytes_identical = 0; + struct urb *urb; + int aligned_x; - char *bufptr; - - base = dev_info->base16d; - - mutex_lock(&dev_info->bulk_mutex); - - source = dev_info->base16; - - bufptr = dev_info->buf; - - for (i = 0; i < dev_info->info->var.yres; i++) { - - if (dev_info->bufend - bufptr < BUF_HIGH_WATER_MARK) { - ret = dlfb_bulk_msg(dev_info, bufptr - dev_info->buf); - bufptr = dev_info->buf; - } - - rem = dev_info->info->var.xres; - - while (rem) { - - if (dev_info->bufend - bufptr < BUF_HIGH_WATER_MARK) { - ret = - dlfb_bulk_msg(dev_info, - bufptr - dev_info->buf); - bufptr = dev_info->buf; - - } + start_cycles = get_cycles(); - *bufptr++ = 0xAF; - *bufptr++ = 0x6A; + aligned_x = DL_ALIGN_DOWN(x, sizeof(unsigned long)); + width = DL_ALIGN_UP(width + (x-aligned_x), sizeof(unsigned long)); + x = aligned_x; - *bufptr++ = (char)(base >> 16); - *bufptr++ = (char)(base >> 8); - *bufptr++ = (char)(base); + if ((width <= 0) || + (x + width > dev->info->var.xres) || + (y + height > dev->info->var.yres)) + return -EINVAL; - if (rem > 255) { - *bufptr++ = 255; - *bufptr++ = (char)(source >> 16); - *bufptr++ = (char)(source >> 8); - *bufptr++ = (char)(source); + if (!atomic_read(&dev->usb_active)) + return 0; - rem -= 255; - base += 255 * 2; - source += 255 * 2; + urb = dlfb_get_urb(dev); + if (!urb) + return 0; + cmd = urb->transfer_buffer; - } else { - *bufptr++ = rem; - *bufptr++ = (char)(source >> 16); - *bufptr++ = (char)(source >> 8); - *bufptr++ = (char)(source); + for (i = y; i < y + height ; i++) { + const int line_offset = dev->info->fix.line_length * i; + const int byte_offset = line_offset + (x * BPP); - base += rem * 2; - source += rem * 2; - rem = 0; - } - } + dlfb_render_hline(dev, &urb, (char *) dev->info->fix.smem_start, + &cmd, byte_offset, width * BPP, + &bytes_identical, &bytes_sent); } - if (bufptr > dev_info->buf) - ret = dlfb_bulk_msg(dev_info, bufptr - dev_info->buf); - - mutex_unlock(&dev_info->bulk_mutex); - - return 1; + if (cmd > (char *) urb->transfer_buffer) { + /* Send partial buffer remaining before exiting */ + int len = cmd - (char *) urb->transfer_buffer; + ret = dlfb_submit_urb(dev, urb, len); + bytes_sent += len; + } else + dlfb_urb_completion(urb); + + atomic_add(bytes_sent, &dev->bytes_sent); + atomic_add(bytes_identical, &dev->bytes_identical); + atomic_add(width*height*2, &dev->bytes_rendered); + end_cycles = get_cycles(); + atomic_add(((unsigned int) ((end_cycles - start_cycles) + >> 10)), /* Kcycles */ + &dev->cpu_kcycles_used); + return 0; } -static int -copyarea(struct dlfb_data *dev_info, int dx, int dy, int sx, int sy, - int width, int height) +/* hardware has native COPY command (see libdlo), but not worth it for fbcon */ +static void dlfb_ops_copyarea(struct fb_info *info, + const struct fb_copyarea *area) { - int base; - int source; - int rem; - int i, ret; - - char *bufptr; - - if (dx + width > dev_info->info->var.xres) - return -EINVAL; - if (dy + height > dev_info->info->var.yres) - return -EINVAL; - - mutex_lock(&dev_info->bulk_mutex); - - base = - dev_info->base16 + (dev_info->info->var.xres * 2 * dy) + (dx * 2); - source = (dev_info->info->var.xres * 2 * sy) + (sx * 2); - - bufptr = dev_info->buf; - - for (i = sy; i < sy + height; i++) { - - memcpy(dev_info->backing_buffer + base - dev_info->base16, - dev_info->backing_buffer + source, width * 2); - - if (dev_info->bufend - bufptr < BUF_HIGH_WATER_MARK) { - ret = dlfb_bulk_msg(dev_info, bufptr - dev_info->buf); - bufptr = dev_info->buf; - } - - rem = width; - - while (rem) { - - if (dev_info->bufend - bufptr < BUF_HIGH_WATER_MARK) { - ret = - dlfb_bulk_msg(dev_info, - bufptr - dev_info->buf); - bufptr = dev_info->buf; - } + struct dlfb_data *dev = info->par; - *bufptr++ = 0xAF; - *bufptr++ = 0x6A; +#if defined CONFIG_FB_SYS_COPYAREA || defined CONFIG_FB_SYS_COPYAREA_MODULE - *bufptr++ = (char)(base >> 16); - *bufptr++ = (char)(base >> 8); - *bufptr++ = (char)(base); + sys_copyarea(info, area); - if (rem > 255) { - *bufptr++ = 255; - *bufptr++ = (char)(source >> 16); - *bufptr++ = (char)(source >> 8); - *bufptr++ = (char)(source); + dlfb_handle_damage(dev, area->dx, area->dy, + area->width, area->height, info->screen_base); +#endif + atomic_inc(&dev->copy_count); - rem -= 255; - base += 255 * 2; - source += 255 * 2; +} - } else { - *bufptr++ = rem; - *bufptr++ = (char)(source >> 16); - *bufptr++ = (char)(source >> 8); - *bufptr++ = (char)(source); +static void dlfb_ops_imageblit(struct fb_info *info, + const struct fb_image *image) +{ + struct dlfb_data *dev = info->par; - base += rem * 2; - source += rem * 2; - rem = 0; - } - } +#if defined CONFIG_FB_SYS_IMAGEBLIT || defined CONFIG_FB_SYS_IMAGEBLIT_MODULE - base += (dev_info->info->var.xres * 2) - (width * 2); - source += (dev_info->info->var.xres * 2) - (width * 2); - } + sys_imageblit(info, image); - if (bufptr > dev_info->buf) - ret = dlfb_bulk_msg(dev_info, bufptr - dev_info->buf); + dlfb_handle_damage(dev, image->dx, image->dy, + image->width, image->height, info->screen_base); - mutex_unlock(&dev_info->bulk_mutex); +#endif - return 1; + atomic_inc(&dev->blit_count); } -static void dlfb_ops_copyarea(struct fb_info *info, - const struct fb_copyarea *area) +static void dlfb_ops_fillrect(struct fb_info *info, + const struct fb_fillrect *rect) { struct dlfb_data *dev = info->par; - copyarea(dev, area->dx, area->dy, area->sx, area->sy, area->width, - area->height); -} - -static void dlfb_ops_imageblit(struct fb_info *info, - const struct fb_image *image) -{ - int ret; - struct dlfb_data *dev = info->par; - cfb_imageblit(info, image); - ret = - image_blit(dev, image->dx, image->dy, image->width, image->height, - info->screen_base); -} +#if defined CONFIG_FB_SYS_FILLRECT || defined CONFIG_FB_SYS_FILLRECT_MODULE -static void dlfb_ops_fillrect(struct fb_info *info, - const struct fb_fillrect *region) -{ + sys_fillrect(info, rect); - unsigned char red, green, blue; - struct dlfb_data *dev = info->par; + dlfb_handle_damage(dev, rect->dx, rect->dy, rect->width, + rect->height, info->screen_base); +#endif - memcpy(&red, ®ion->color, 1); - memcpy(&green, ®ion->color + 1, 1); - memcpy(&blue, ®ion->color + 2, 1); - draw_rect(dev, region->dx, region->dy, region->width, region->height, - red, green, blue); - /* printk("FILL RECT %d %d !!!\n", region->dx, region->dy); */ + atomic_inc(&dev->fill_count); } @@ -840,21 +645,26 @@ static void dlfb_get_edid(struct dlfb_data *dev) } static int dlfb_ops_ioctl(struct fb_info *info, unsigned int cmd, - unsigned long arg) + unsigned long arg) { - struct dlfb_data *dev_info = info->par; + + struct dlfb_data *dev = info->par; struct dloarea *area = NULL; - if (cmd == 0xAD) { + if (!atomic_read(&dev->usb_active)) + return 0; + + /* TODO: Update X server to get this from sysfs instead */ + if (cmd == DLFB_IOCTL_RETURN_EDID) { char *edid = (char *)arg; - dlfb_edid(dev_info); - if (copy_to_user(edid, dev_info->edid, 128)) { + dlfb_get_edid(dev); + if (copy_to_user(edid, dev->edid, sizeof(dev->edid))) return -EFAULT; - } return 0; } - if (cmd == 0xAA || cmd == 0xAB || cmd == 0xAC) { + /* TODO: Help propose a standard fb.h ioctl to report mmap damage */ + if (cmd == DLFB_IOCTL_REPORT_DAMAGE) { area = (struct dloarea *)arg; @@ -869,29 +679,14 @@ static int dlfb_ops_ioctl(struct fb_info *info, unsigned int cmd, if (area->y > info->var.yres) area->y = info->var.yres; - } - if (cmd == 0xAA) { - image_blit(dev_info, area->x, area->y, area->w, area->h, + atomic_set(&dev->use_defio, 0); + + dlfb_handle_damage(dev, area->x, area->y, area->w, area->h, info->screen_base); + atomic_inc(&dev->damage_count); } - if (cmd == 0xAC) { - copyfb(dev_info); - image_blit(dev_info, area->x, area->y, area->w, area->h, - info->screen_base); - swapfb(dev_info); - } else if (cmd == 0xAB) { - - if (area->x2 < 0) - area->x2 = 0; - if (area->y2 < 0) - area->y2 = 0; - - copyarea(dev_info, - area->x2, area->y2, area->x, area->y, area->w, - area->h); - } return 0; } @@ -925,8 +720,6 @@ dlfb_ops_setcolreg(unsigned regno, unsigned red, unsigned green, static int dlfb_ops_release(struct fb_info *info, int user) { struct dlfb_data *dev_info = info->par; - image_blit(dev_info, 0, 0, info->var.xres, info->var.yres, - info->screen_base); return 0; } @@ -1026,18 +819,28 @@ static int dlfb_ops_set_par(struct fb_info *info) static int dlfb_ops_blank(int blank_mode, struct fb_info *info) { - struct dlfb_data *dev_info = info->par; - char *bufptr = dev_info->buf; + struct dlfb_data *dev = info->par; + char *bufptr; + struct urb *urb; - bufptr = dlfb_set_register(bufptr, 0xFF, 0x00); + urb = dlfb_get_urb(dev); + if (!urb) + return 0; + bufptr = (char *) urb->transfer_buffer; + + /* overloading usb_active. UNBLANK can conflict with teardown */ + + bufptr = dlfb_vidreg_lock(bufptr); if (blank_mode != FB_BLANK_UNBLANK) { - bufptr = dlfb_set_register(bufptr, 0x1F, 0x01); + atomic_set(&dev->usb_active, 0); + bufptr = dlfb_enable_hvsync(bufptr, false); } else { - bufptr = dlfb_set_register(bufptr, 0x1F, 0x00); + atomic_set(&dev->usb_active, 1); + bufptr = dlfb_enable_hvsync(bufptr, true); } - bufptr = dlfb_set_register(bufptr, 0xFF, 0xFF); + bufptr = dlfb_vidreg_unlock(bufptr); - dlfb_bulk_msg(dev_info, bufptr - dev_info->buf); + dlfb_submit_urb(dev, urb, bufptr - (char *) urb->transfer_buffer); return 0; } @@ -1312,8 +1115,6 @@ static int dlfb_usb_probe(struct usb_interface *interface, kref_init(&dev->kref); /* matching kref_put in usb .disconnect fn */ kref_get(&dev->kref); /* matching kref_put in .fb_destroy function*/ - mutex_init(&dev->bulk_mutex); - dev->udev = usbdev; dev->gdev = &usbdev->dev; /* our generic struct device * */ usb_set_intfdata(interface, dev); @@ -1326,22 +1127,6 @@ static int dlfb_usb_probe(struct usb_interface *interface, mutex_init(&dev->fb_open_lock); - /* - * TODO: replace single 64K buffer with buffer list - * and async dispatch - */ - dev->buf = kmalloc(BUF_SIZE, GFP_KERNEL); - if (dev->buf == NULL) { - dl_err("unable to allocate memory for dlfb commands\n"); - goto error; - } - dev->bufend = dev->buf + BUF_SIZE; - - dev->tx_urb = usb_alloc_urb(0, GFP_KERNEL); - usb_fill_bulk_urb(dev->tx_urb, dev->udev, - usb_sndbulkpipe(dev->udev, 1), dev->buf, 0, - dlfb_bulk_callback, dev); - /* We don't register a new USB class. Our client interface is fbdev */ /* allocates framebuffer driver structure, not framebuffer memory */ @@ -1420,14 +1205,13 @@ static int dlfb_usb_probe(struct usb_interface *interface, dlfb_ops_set_par(info); /* paint greenscreen */ -/* pix_framebuffer = (u16 *) videomemory; for (i = 0; i < videomemorysize / 2; i++) pix_framebuffer[i] = 0x37e6; dlfb_handle_damage(dev, 0, 0, info->var.xres, info->var.yres, videomemory); -*/ + retval = register_framebuffer(info); if (retval < 0) { dl_err("register_framebuffer failed %d\n", retval); diff --git a/drivers/staging/udlfb/udlfb.h b/drivers/staging/udlfb/udlfb.h index e6c68c654677..b07a69371f1f 100644 --- a/drivers/staging/udlfb/udlfb.h +++ b/drivers/staging/udlfb/udlfb.h @@ -1,9 +1,20 @@ #ifndef UDLFB_H #define UDLFB_H -/* as libdlo */ -#define BUF_HIGH_WATER_MARK 1024 -#define BUF_SIZE (64*1024) +/* + * TODO: Propose standard fb.h ioctl for reporting damage, + * using _IOWR() and one of the existing area structs from fb.h + * Consider these ioctls deprecated, but they're still used by the + * DisplayLink X server as yet - need both to be modified in tandem + * when new ioctl(s) are ready. + */ +#define DLFB_IOCTL_RETURN_EDID 0xAD +#define DLFB_IOCTL_REPORT_DAMAGE 0xAA +struct dloarea { + int x, y; + int w, h; + int x2, y2; +}; struct urb_node { struct list_head entry; @@ -23,30 +34,20 @@ struct urb_list { struct dlfb_data { struct usb_device *udev; struct device *gdev; /* &udev->dev */ - struct usb_interface *interface; - struct urb *tx_urb, *ctrl_urb; struct fb_info *info; struct urb_list urbs; struct kref kref; - char *buf; - char *bufend; char *backing_buffer; struct delayed_work deferred_work; struct mutex fb_open_lock; - struct mutex bulk_mutex; int fb_count; atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */ atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */ atomic_t use_defio; /* 0 = rely on ioctls and blit/copy/fill rects */ char edid[128]; int sku_pixel_limit; - int screen_size; - int line_length; - struct completion done; int base16; - int base16d; int base8; - int base8d; u32 pseudo_palette[256]; /* blit-only rendering path metrics, exposed through sysfs */ atomic_t bytes_rendered; /* raw pixel-bytes driver asked to render */ @@ -72,48 +73,24 @@ struct dlfb_data { #define GET_URB_TIMEOUT HZ #define FREE_URB_TIMEOUT (HZ*2) -static void dlfb_bulk_callback(struct urb *urb) -{ - struct dlfb_data *dev_info = urb->context; - complete(&dev_info->done); -} - -static void dlfb_edid(struct dlfb_data *dev_info) -{ - int i; - int ret; - char rbuf[2]; - - for (i = 0; i < 128; i++) { - ret = - usb_control_msg(dev_info->udev, - usb_rcvctrlpipe(dev_info->udev, 0), (0x02), - (0x80 | (0x02 << 5)), i << 8, 0xA1, rbuf, 2, - 0); - dev_info->edid[i] = rbuf[1]; - } - -} - -static int dlfb_bulk_msg(struct dlfb_data *dev_info, int len) -{ - int ret; - - init_completion(&dev_info->done); +#define BPP 2 +#define MAX_CMD_PIXELS 255 - dev_info->tx_urb->actual_length = 0; - dev_info->tx_urb->transfer_buffer_length = len; +#define RLX_HEADER_BYTES 7 +#define MIN_RLX_PIX_BYTES 4 +#define MIN_RLX_CMD_BYTES (RLX_HEADER_BYTES + MIN_RLX_PIX_BYTES) - ret = usb_submit_urb(dev_info->tx_urb, GFP_KERNEL); - if (!wait_for_completion_timeout(&dev_info->done, 1000)) { - usb_kill_urb(dev_info->tx_urb); - printk("usb timeout !!!\n"); - } +#define RLE_HEADER_BYTES 6 +#define MIN_RLE_PIX_BYTES 3 +#define MIN_RLE_CMD_BYTES (RLE_HEADER_BYTES + MIN_RLE_PIX_BYTES) - return dev_info->tx_urb->actual_length; -} +#define RAW_HEADER_BYTES 6 +#define MIN_RAW_PIX_BYTES 2 +#define MIN_RAW_CMD_BYTES (RAW_HEADER_BYTES + MIN_RAW_PIX_BYTES) -#define dlfb_set_register insert_command +/* remove these once align.h patch is taken into kernel */ +#define DL_ALIGN_UP(x, a) ALIGN(x, a) +#define DL_ALIGN_DOWN(x, a) ALIGN(x-(a-1), a) /* remove once this gets added to sysfs.h */ #define __ATTR_RW(attr) __ATTR(attr, 0644, attr##_show, attr##_store) -- cgit v1.2.3 From 3e8f3d6fa672896096068296658a769649186150 Mon Sep 17 00:00:00 2001 From: Bernie Thompson Date: Mon, 15 Feb 2010 06:46:26 -0800 Subject: Staging: udlfb: Support for fbdev mmap clients (defio) Add support for fbdev mmap clients who don't send damage ioctls Because DisplayLink devices are out on the other end of usb, their "framebuffer" is just normal system memory. So memory mapped writes don't automatically trigger anything. So up to this point, standard fbdev clients who rely on mmap() will get an unchanging screen. This patch makes udlfb a client of Jaya Kumar's defio framework - which sets up page fault triggers, and those faults are accumulated and sent to udlfb on a defferred basis, to process as damage notifications for the framebuffer. Because this involves more overhead than a notification directly from the application (e.g. just passing on X DAMAGE extension notifications), a sysfs attribute is provided by udlfb to control defio support. /sys/class/graphics/fb*/use_defio - writing a "0" to this file before calling mmap() causes defio to not be initialized - instead udlfb will rely on getting damage notifications directly through the damage ioctl. There are unsolved rendering problems with defio (horizontal dead regions on framebuffer, that accumulate over time) which still needs a fix. Signed-off-by: Bernie Thompson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/udlfb/udlfb.c | 124 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 121 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/udlfb/udlfb.c b/drivers/staging/udlfb/udlfb.c index 22f3dc310ff2..939b8faba0ff 100644 --- a/drivers/staging/udlfb/udlfb.c +++ b/drivers/staging/udlfb/udlfb.c @@ -63,6 +63,11 @@ static int dlfb_submit_urb(struct dlfb_data *dev, struct urb * urb, size_t len); static int dlfb_alloc_urb_list(struct dlfb_data *dev, int count, size_t size); static void dlfb_free_urb_list(struct dlfb_data *dev); +/* other symbols with dependents */ +#ifdef CONFIG_FB_DEFERRED_IO +static struct fb_deferred_io dlfb_defio; +#endif + /* * Inserts a specific DisplayLink controller command into the provided * buffer. @@ -717,9 +722,59 @@ dlfb_ops_setcolreg(unsigned regno, unsigned red, unsigned green, return err; } +/* + * It's common for several clients to have framebuffer open simultaneously. + * e.g. both fbcon and X. Makes things interesting. + */ +static int dlfb_ops_open(struct fb_info *info, int user) +{ + struct dlfb_data *dev = info->par; + +/* if (user == 0) + * We could special case kernel mode clients (fbcon) here + */ + + mutex_lock(&dev->fb_open_lock); + + dev->fb_count++; + +#ifdef CONFIG_FB_DEFERRED_IO + if ((atomic_read(&dev->use_defio)) && (info->fbdefio == NULL)) { + /* enable defio */ + info->fbdefio = &dlfb_defio; + fb_deferred_io_init(info); + } +#endif + + dl_notice("open /dev/fb%d user=%d fb_info=%p count=%d\n", + info->node, user, info, dev->fb_count); + + mutex_unlock(&dev->fb_open_lock); + + return 0; +} + static int dlfb_ops_release(struct fb_info *info, int user) { - struct dlfb_data *dev_info = info->par; + struct dlfb_data *dev = info->par; + + mutex_lock(&dev->fb_open_lock); + + dev->fb_count--; + +#ifdef CONFIG_FB_DEFERRED_IO + if ((dev->fb_count == 0) && (info->fbdefio)) { + fb_deferred_io_cleanup(info); + info->fbdefio = NULL; + info->fbops->fb_mmap = dlfb_ops_mmap; + } +#endif + + dl_notice("release /dev/fb%d user=%d count=%d\n", + info->node, user, dev->fb_count); + + mutex_unlock(&dev->fb_open_lock); + return 0; } @@ -735,6 +790,8 @@ static void dlfb_delete(struct kref *kref) if (dev->backing_buffer) vfree(dev->backing_buffer); + mutex_destroy(&dev->fb_open_lock); + kfree(dev); } @@ -853,6 +910,7 @@ static struct fb_ops dlfb_ops = { .fb_imageblit = dlfb_ops_imageblit, .fb_mmap = dlfb_ops_mmap, .fb_ioctl = dlfb_ops_ioctl, + .fb_open = dlfb_ops_open, .fb_release = dlfb_ops_release, .fb_blank = dlfb_ops_blank, .fb_check_var = dlfb_ops_check_var, @@ -1068,6 +1126,68 @@ static struct device_attribute fb_device_attrs[] = { __ATTR_RW(use_defio), }; +#ifdef CONFIG_FB_DEFERRED_IO +static void dlfb_dpy_deferred_io(struct fb_info *info, + struct list_head *pagelist) +{ + struct page *cur; + struct fb_deferred_io *fbdefio = info->fbdefio; + struct dlfb_data *dev = info->par; + struct urb *urb; + char *cmd; + cycles_t start_cycles, end_cycles; + int bytes_sent = 0; + int bytes_identical = 0; + int bytes_rendered = 0; + int fault_count = 0; + + if (!atomic_read(&dev->use_defio)) + return; + + if (!atomic_read(&dev->usb_active)) + return; + + start_cycles = get_cycles(); + + urb = dlfb_get_urb(dev); + if (!urb) + return; + cmd = urb->transfer_buffer; + + /* walk the written page list and render each to device */ + list_for_each_entry(cur, &fbdefio->pagelist, lru) { + dlfb_render_hline(dev, &urb, (char *) info->fix.smem_start, + &cmd, cur->index << PAGE_SHIFT, + PAGE_SIZE, &bytes_identical, &bytes_sent); + bytes_rendered += PAGE_SIZE; + fault_count++; + } + + if (cmd > (char *) urb->transfer_buffer) { + /* Send partial buffer remaining before exiting */ + int len = cmd - (char *) urb->transfer_buffer; + dlfb_submit_urb(dev, urb, len); + bytes_sent += len; + } else + dlfb_urb_completion(urb); + + atomic_add(fault_count, &dev->defio_fault_count); + atomic_add(bytes_sent, &dev->bytes_sent); + atomic_add(bytes_identical, &dev->bytes_identical); + atomic_add(bytes_rendered, &dev->bytes_rendered); + end_cycles = get_cycles(); + atomic_add(((unsigned int) ((end_cycles - start_cycles) + >> 10)), /* Kcycles */ + &dev->cpu_kcycles_used); +} + +static struct fb_deferred_io dlfb_defio = { + .delay = 5, + .deferred_io = dlfb_dpy_deferred_io, +}; + +#endif + /* * This is necessary before we can communicate with the display controller. */ @@ -1193,11 +1313,9 @@ static int dlfb_usb_probe(struct usb_interface *interface, /* ready to begin using device */ -/* #ifdef CONFIG_FB_DEFERRED_IO atomic_set(&dev->use_defio, 1); #endif -*/ atomic_set(&dev->usb_active, 1); dlfb_select_std_channel(dev); -- cgit v1.2.3 From dd8015f1c83bfde9966c86a5958abd466a304398 Mon Sep 17 00:00:00 2001 From: Bernie Thompson Date: Mon, 15 Feb 2010 06:46:35 -0800 Subject: Staging: udlfb: explicit dependencies and warnings Specify Kconfig dependencies, and include warnings for building as a module udlfb is dependent on FB_DEFERRED_IO, FB_SYS_*, and FB_MODE_HELPERS Because many kernels do not include defio (which cannot be built as a module), yet users want to be able to build udlfb as a module later, udlfb has ifdefs and these dependency warnings to help udlfb build with or without certain dependencies, but also print warnings for any lost function. Even though this kind of flexibility isn't common, we've gotten feedback from a significant portion of users that they were frustrated without it. Signed-off-by: Bernie Thompson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/udlfb/Kconfig | 14 ++++++++++---- drivers/staging/udlfb/udlfb.c | 14 ++++++++++++++ 2 files changed, 24 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/udlfb/Kconfig b/drivers/staging/udlfb/Kconfig index 641692da0e4f..65bd5db4ca56 100644 --- a/drivers/staging/udlfb/Kconfig +++ b/drivers/staging/udlfb/Kconfig @@ -1,8 +1,14 @@ config FB_UDL tristate "Displaylink USB Framebuffer support" depends on FB && USB + select FB_MODE_HELPERS + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_SYS_FOPS + select FB_DEFERRED_IO ---help--- - This is an experimental driver for DisplayLink USB devices - that provides a framebuffer device. A normal framebuffer can - be used with this driver, or xorg can be run on the device - using it. + This is a kernel framebuffer driver for DisplayLink USB devices. + Supports fbdev clients like xf86-video-fbdev, kdrive, fbi, and + mplayer -vo fbdev. Supports all USB 2.0 era DisplayLink devices. + To compile as a module, choose M here: the module name is udlfb. diff --git a/drivers/staging/udlfb/udlfb.c b/drivers/staging/udlfb/udlfb.c index 939b8faba0ff..baad03a8a873 100644 --- a/drivers/staging/udlfb/udlfb.c +++ b/drivers/staging/udlfb/udlfb.c @@ -56,6 +56,20 @@ static struct usb_device_id id_table[] = { }; MODULE_DEVICE_TABLE(usb, id_table); +#ifndef CONFIG_FB_DEFERRED_IO +#warning message "kernel FB_DEFFERRED_IO option to support generic fbdev apps" +#endif + +#ifndef CONFIG_FB_SYS_IMAGEBLIT +#ifndef CONFIG_FB_SYS_IMAGEBLIT_MODULE +#warning message "FB_SYS_* in kernel or module option to support fb console" +#endif +#endif + +#ifndef CONFIG_FB_MODE_HELPERS +#warning message "kernel FB_MODE_HELPERS required. Expect build break" +#endif + /* dlfb keeps a list of urbs for efficient bulk transfers */ static void dlfb_urb_completion(struct urb *urb); static struct urb *dlfb_get_urb(struct dlfb_data *dev); -- cgit v1.2.3 From bd80816b2877879d36011815858c8681408cc625 Mon Sep 17 00:00:00 2001 From: Bernie Thompson Date: Mon, 15 Feb 2010 06:46:48 -0800 Subject: Staging: udlfb: remove printk and small cleanup Remove last remaining printk and clarify comments Signed-off-by: Bernie Thompson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/udlfb/udlfb.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/udlfb/udlfb.c b/drivers/staging/udlfb/udlfb.c index baad03a8a873..8f6223c8303a 100644 --- a/drivers/staging/udlfb/udlfb.c +++ b/drivers/staging/udlfb/udlfb.c @@ -83,8 +83,8 @@ static struct fb_deferred_io dlfb_defio; #endif /* - * Inserts a specific DisplayLink controller command into the provided - * buffer. + * All DisplayLink bulk operations start with 0xAF, followed by specific code + * All operations are written to buffers which then later get sent to device */ static char *dlfb_set_register(char *buf, u8 reg, u8 val) { @@ -129,6 +129,10 @@ static char *dlfb_set_base16bpp(char *wrptr, u32 base) return dlfb_set_register(wrptr, 0x22, base); } +/* + * DisplayLink HW has separate 16bpp and 8bpp framebuffers. + * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer + */ static char *dlfb_set_base8bpp(char *wrptr, u32 base) { wrptr = dlfb_set_register(wrptr, 0x26, base >> 16); @@ -161,7 +165,7 @@ static char *dlfb_set_register_16be(char *wrptr, u8 reg, u16 value) * same actual count. This makes sense once you read above a couple of * times and think about it from a hardware perspective. */ -static u16 lfsr16(u16 actual_count) +static u16 dlfb_lfsr16(u16 actual_count) { u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */ @@ -180,7 +184,7 @@ static u16 lfsr16(u16 actual_count) */ static char *dlfb_set_register_lfsr16(char *wrptr, u8 reg, u16 value) { - return dlfb_set_register_16(wrptr, reg, lfsr16(value)); + return dlfb_set_register_16(wrptr, reg, dlfb_lfsr16(value)); } /* @@ -292,8 +296,9 @@ static int dlfb_ops_mmap(struct fb_info *info, struct vm_area_struct *vma) unsigned long size = vma->vm_end - vma->vm_start; unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; unsigned long page, pos; + struct dlfb_data *dev = info->par; - printk("MMAP: %lu %u\n", offset + size, info->fix.smem_len); + dl_notice("MMAP: %lu %u\n", offset + size, info->fix.smem_len); if (offset + size > info->fix.smem_len) return -EINVAL; -- cgit v1.2.3 From a94f530a5ee36f72e0377d081023b8d23dacf7ce Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Tue, 16 Feb 2010 14:59:07 -0800 Subject: Staging: rtl8187se: needs semaphore.h rtl8187se needs to include semaphore.h to prevent build errors: drivers/staging/rtl8187se/ieee80211/ieee80211.h:1004: error: field 'wx_sem' has incomplete type drivers/staging/rtl8187se/ieee80211/ieee80211.h:1005: error: field 'scan_sem' has incomplete type Signed-off-by: Randy Dunlap Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8187se/ieee80211/ieee80211.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/staging/rtl8187se/ieee80211/ieee80211.h b/drivers/staging/rtl8187se/ieee80211/ieee80211.h index 04a48e7e76e6..c4ab683e8f61 100644 --- a/drivers/staging/rtl8187se/ieee80211/ieee80211.h +++ b/drivers/staging/rtl8187se/ieee80211/ieee80211.h @@ -29,6 +29,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3 From 66bd8db52ab48e7189e02d4bf1f23109cc1ede70 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Thu, 18 Feb 2010 15:12:52 +0000 Subject: Staging: vme: Renaming following split of GE Fanuc joint venture This patch corrects author email addresses and Copyright notices as a result of the split up of the GE Fanuc joint venture. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/bridges/vme_ca91cx42.c | 4 ++-- drivers/staging/vme/bridges/vme_ca91cx42.h | 4 ++-- drivers/staging/vme/bridges/vme_tsi148.c | 4 ++-- drivers/staging/vme/devices/vme_user.c | 6 +++--- drivers/staging/vme/vme.c | 6 +++--- 5 files changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index 807278485bbf..272cc26ba5ac 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c @@ -1,8 +1,8 @@ /* * Support for the Tundra Universe I/II VME-PCI Bridge Chips * - * Author: Martyn Welch - * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. + * Author: Martyn Welch + * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. * * Based on work by Tom Armistead and Ajit Prem * Copyright 2004 Motorola Inc. diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.h b/drivers/staging/vme/bridges/vme_ca91cx42.h index 95a42c240a20..2a9ad1454f4e 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.h +++ b/drivers/staging/vme/bridges/vme_ca91cx42.h @@ -7,8 +7,8 @@ * Updated by Ajit Prem * Copyright 2004 Motorola Inc. * - * Further updated by Martyn Welch - * Copyright 2009 GE Fanuc Intelligent Platforms Embedded Systems, Inc. + * Further updated by Martyn Welch + * Copyright 2009 GE Intelligent Platforms Embedded Systems, Inc. * * Derived from ca91c042.h by Michael Wyrick * diff --git a/drivers/staging/vme/bridges/vme_tsi148.c b/drivers/staging/vme/bridges/vme_tsi148.c index ed8297daf9ee..2ca5126627cd 100644 --- a/drivers/staging/vme/bridges/vme_tsi148.c +++ b/drivers/staging/vme/bridges/vme_tsi148.c @@ -1,8 +1,8 @@ /* * Support for the Tundra TSI148 VME-PCI Bridge Chip * - * Author: Martyn Welch - * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. + * Author: Martyn Welch + * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. * * Based on work by Tom Armistead and Ajit Prem * Copyright 2004 Motorola Inc. diff --git a/drivers/staging/vme/devices/vme_user.c b/drivers/staging/vme/devices/vme_user.c index 2159540d9383..48d46cadb13f 100644 --- a/drivers/staging/vme/devices/vme_user.c +++ b/drivers/staging/vme/devices/vme_user.c @@ -1,8 +1,8 @@ /* * VMEbus User access driver * - * Author: Martyn Welch - * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. + * Author: Martyn Welch + * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. * * Based on work by: * Tom Armistead and Ajit Prem @@ -818,7 +818,7 @@ MODULE_PARM_DESC(bus, "Enumeration of VMEbus to which the driver is connected"); module_param_array(bus, int, &bus_num, 0); MODULE_DESCRIPTION("VME User Space Access Driver"); -MODULE_AUTHOR("Martyn Welch - * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. + * Author: Martyn Welch + * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. * * Based on work by Tom Armistead and Ajit Prem * Copyright 2004 Motorola Inc. @@ -1533,7 +1533,7 @@ static void __exit vme_exit(void) } MODULE_DESCRIPTION("VME bridge driver framework"); -MODULE_AUTHOR("Martyn Welch Date: Thu, 18 Feb 2010 15:12:58 +0000 Subject: Staging: vme: Attribute Testing For Dma Request Check the directions in which the DMA controller is expected to operate before giving control of a resource. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/TODO | 22 ---------------------- drivers/staging/vme/bridges/vme_ca91cx42.c | 2 ++ drivers/staging/vme/bridges/vme_tsi148.c | 4 ++++ drivers/staging/vme/vme.c | 8 +++++--- drivers/staging/vme/vme.h | 10 +++++++++- drivers/staging/vme/vme_api.txt | 27 +++++++++++++++++++-------- drivers/staging/vme/vme_bridge.h | 1 + 7 files changed, 40 insertions(+), 34 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/TODO b/drivers/staging/vme/TODO index 2201ff6f74d1..bdc5f6248bcc 100644 --- a/drivers/staging/vme/TODO +++ b/drivers/staging/vme/TODO @@ -4,28 +4,6 @@ API === -DMA Resource Allocation incomplete ----------------------------------- - -The current DMA resource Allocation provides no means of selecting the -suitability of a DMA controller based on it's supported modes of operation, as -opposed to the resource allocation mechanisms for master and slave windows: - - struct vme_resource *vme_dma_request(struct device *dev); - -As opposed to: - - struct vme_resource * vme_master_request(struct device *dev, - vme_address_t aspace, vme_cycle_t cycle, vme_width_t width); - -The TSI148 can perform, VME-to-PCI, PCI-to-VME, PATTERN-to-VME, PATTERN-to-PCI, -VME-to-VME and PCI-to-PCI transfers. The CA91C142 can only provide VME-to-PCI -and PCI-to-VME. - -Add a mechanism to select a VME controller based on source/target type, -required aspace, cycle and width requirements. - - Master window broadcast select mask ----------------------------------- diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index 272cc26ba5ac..7eaba3511ea8 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c @@ -1109,6 +1109,8 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) mutex_init(&(dma_ctrlr->mtx)); dma_ctrlr->locked = 0; dma_ctrlr->number = i; + dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM | + VME_DMA_MEM_TO_VME; INIT_LIST_HEAD(&(dma_ctrlr->pending)); INIT_LIST_HEAD(&(dma_ctrlr->running)); list_add_tail(&(dma_ctrlr->list), diff --git a/drivers/staging/vme/bridges/vme_tsi148.c b/drivers/staging/vme/bridges/vme_tsi148.c index 2ca5126627cd..e74c4a953b2d 100644 --- a/drivers/staging/vme/bridges/vme_tsi148.c +++ b/drivers/staging/vme/bridges/vme_tsi148.c @@ -2421,6 +2421,10 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) mutex_init(&(dma_ctrlr->mtx)); dma_ctrlr->locked = 0; dma_ctrlr->number = i; + dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM | + VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME | + VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME | + VME_DMA_PATTERN_TO_MEM; INIT_LIST_HEAD(&(dma_ctrlr->pending)); INIT_LIST_HEAD(&(dma_ctrlr->running)); list_add_tail(&(dma_ctrlr->list), diff --git a/drivers/staging/vme/vme.c b/drivers/staging/vme/vme.c index 8d8f9cb2974d..79c501dac5f9 100644 --- a/drivers/staging/vme/vme.c +++ b/drivers/staging/vme/vme.c @@ -643,7 +643,7 @@ EXPORT_SYMBOL(vme_master_free); * Request a DMA controller with specific attributes, return some unique * identifier. */ -struct vme_resource *vme_dma_request(struct device *dev) +struct vme_resource *vme_dma_request(struct device *dev, vme_dma_route_t route) { struct vme_bridge *bridge; struct list_head *dma_pos = NULL; @@ -670,9 +670,11 @@ struct vme_resource *vme_dma_request(struct device *dev) continue; } - /* Find an unlocked controller */ + /* Find an unlocked and compatible controller */ mutex_lock(&(dma_ctrlr->mtx)); - if (dma_ctrlr->locked == 0) { + if (((dma_ctrlr->route_attr & route) == route) && + (dma_ctrlr->locked == 0)) { + dma_ctrlr->locked = 1; mutex_unlock(&(dma_ctrlr->mtx)); allocated_ctrlr = dma_ctrlr; diff --git a/drivers/staging/vme/vme.h b/drivers/staging/vme/vme.h index 5a4d163fae10..48768ca97e16 100644 --- a/drivers/staging/vme/vme.h +++ b/drivers/staging/vme/vme.h @@ -68,6 +68,14 @@ typedef u32 vme_pattern_t; #define VME_DMA_PATTERN_WORD (1<<1) #define VME_DMA_PATTERN_INCREMENT (1<<2) +typedef u32 vme_dma_route_t; +#define VME_DMA_VME_TO_MEM (1<<0) +#define VME_DMA_MEM_TO_VME (1<<1) +#define VME_DMA_VME_TO_VME (1<<2) +#define VME_DMA_MEM_TO_MEM (1<<3) +#define VME_DMA_PATTERN_TO_VME (1<<4) +#define VME_DMA_PATTERN_TO_MEM (1<<5) + struct vme_dma_attr { vme_dma_t type; void *private; @@ -124,7 +132,7 @@ unsigned int vme_master_rmw(struct vme_resource *, unsigned int, unsigned int, unsigned int, loff_t); void vme_master_free(struct vme_resource *); -struct vme_resource *vme_dma_request(struct device *); +struct vme_resource *vme_dma_request(struct device *, vme_dma_route_t); struct vme_dma_list *vme_new_dma_list(struct vme_resource *); struct vme_dma_attr *vme_dma_pattern_attribute(u32, vme_pattern_t); struct vme_dma_attr *vme_dma_pci_attribute(dma_addr_t); diff --git a/drivers/staging/vme/vme_api.txt b/drivers/staging/vme/vme_api.txt index a5c1b1cd5fcc..a910a0c4388b 100644 --- a/drivers/staging/vme/vme_api.txt +++ b/drivers/staging/vme/vme_api.txt @@ -77,16 +77,21 @@ driver in question: struct vme_resource * vme_slave_request(struct device *dev, vme_address_t aspace, vme_cycle_t cycle); - struct vme_resource *vme_dma_request(struct device *dev); + struct vme_resource *vme_dma_request(struct device *dev, + vme_dma_route_t route); For slave windows these attributes are split into those of type 'vme_address_t' -and 'vme_cycle_t'. Master windows add a further set of attributes 'vme_cycle_t'. -These attributes are defined as bitmasks and as such any combination of the -attributes can be requested for a single window, the core will assign a window -that meets the requirements, returning a pointer of type vme_resource that -should be used to identify the allocated resource when it is used. If an -unallocated window fitting the requirements can not be found a NULL pointer will -be returned. +and 'vme_cycle_t'. Master windows add a further set of attributes +'vme_cycle_t'. These attributes are defined as bitmasks and as such any +combination of the attributes can be requested for a single window, the core +will assign a window that meets the requirements, returning a pointer of type +vme_resource that should be used to identify the allocated resource when it is +used. For DMA controllers, the request function requires the potential +direction of any transfers to be provided in the route attributes. This is +typically VME-to-MEM and/or MEM-to-VME, though some hardware can support +VME-to-VME and MEM-to-MEM transfers as well as test pattern generation. If an +unallocated window fitting the requirements can not be found a NULL pointer +will be returned. Functions are also provided to free window allocations once they are no longer required. These functions should be passed the pointer to the resource provided @@ -237,6 +242,12 @@ covered under "Transfer Attributes"): struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count); +NOTE: The detailed attributes of the transfers source and destination + are not checked until an entry is added to a DMA list, the request + for a DMA channel purely checks the directions in which the + controller is expected to transfer data. As a result it is + possible for this call to return an error, for example if the + source or destination is in an unsupported VME address space. Transfer Attributes ------------------- diff --git a/drivers/staging/vme/vme_bridge.h b/drivers/staging/vme/vme_bridge.h index 92e5614ab910..f8ead21c94fb 100644 --- a/drivers/staging/vme/vme_bridge.h +++ b/drivers/staging/vme/vme_bridge.h @@ -64,6 +64,7 @@ struct vme_dma_resource { int number; struct list_head pending; struct list_head running; + vme_dma_route_t route_attr; }; struct vme_lm_resource { -- cgit v1.2.3 From 29848ac9f3b33bf171439ae2d66d40e6a71446c4 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Thu, 18 Feb 2010 15:13:05 +0000 Subject: Staging: vme: Enable drivers to handle more than one bridge At the moment the vme bridge drivers are written in a way that only allows them to support one bridge at a time. Modify the drivers to enable more than one bridge to be present per board. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/TODO | 2 - drivers/staging/vme/bridges/vme_ca91cx42.c | 411 +++++++++++-------- drivers/staging/vme/bridges/vme_ca91cx42.h | 16 + drivers/staging/vme/bridges/vme_tsi148.c | 634 ++++++++++++++++------------- drivers/staging/vme/bridges/vme_tsi148.h | 16 + drivers/staging/vme/vme.c | 10 +- drivers/staging/vme/vme_bridge.h | 8 +- 7 files changed, 633 insertions(+), 464 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/TODO b/drivers/staging/vme/TODO index bdc5f6248bcc..83d44cbf9a5f 100644 --- a/drivers/staging/vme/TODO +++ b/drivers/staging/vme/TODO @@ -47,7 +47,6 @@ Bridge Support Tempe (tsi148) -------------- -- Driver can currently only support a single bridge. - 2eSST Broadcast mode. - Mailboxes unsupported. - Improve error detection. @@ -58,7 +57,6 @@ Tempe (tsi148) Universe II (ca91c142) ---------------------- -- Driver can currently only support a single bridge. - DMA unsupported. - RMW transactions unsupported. - Location Monitors unsupported. diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index 7eaba3511ea8..c2f86a6996d5 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c @@ -41,24 +41,6 @@ static void __exit ca91cx42_exit(void); /* Module parameters */ static int geoid; -static struct vme_bridge *ca91cx42_bridge; -static wait_queue_head_t dma_queue; -static wait_queue_head_t iack_queue; -#if 0 -static wait_queue_head_t lm_queue; -#endif -static wait_queue_head_t mbox_queue; - -static void (*lm_callback[4])(int); /* Called in interrupt handler */ -static void *crcsr_kernel; -static dma_addr_t crcsr_bus; - -static struct mutex vme_rmw; /* Only one RMW cycle at a time */ -static struct mutex vme_int; /* - * Only one VME interrupt can be - * generated at a time, provide locking - */ - static char driver_name[] = "vme_ca91cx42"; static const struct pci_device_id ca91cx42_ids[] = { @@ -73,14 +55,14 @@ static struct pci_driver ca91cx42_driver = { .remove = ca91cx42_remove, }; -static u32 ca91cx42_DMA_irqhandler(void) +static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge) { - wake_up(&dma_queue); + wake_up(&(bridge->dma_queue)); return CA91CX42_LINT_DMA; } -static u32 ca91cx42_LM_irqhandler(u32 stat) +static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat) { int i; u32 serviced = 0; @@ -88,7 +70,7 @@ static u32 ca91cx42_LM_irqhandler(u32 stat) for (i = 0; i < 4; i++) { if (stat & CA91CX42_LINT_LM[i]) { /* We only enable interrupts if the callback is set */ - lm_callback[i](i); + bridge->lm_callback[i](i); serviced |= CA91CX42_LINT_LM[i]; } } @@ -97,16 +79,16 @@ static u32 ca91cx42_LM_irqhandler(u32 stat) } /* XXX This needs to be split into 4 queues */ -static u32 ca91cx42_MB_irqhandler(int mbox_mask) +static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask) { - wake_up(&mbox_queue); + wake_up(&(bridge->mbox_queue)); return CA91CX42_LINT_MBOX; } -static u32 ca91cx42_IACK_irqhandler(void) +static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge) { - wake_up(&iack_queue); + wake_up(&(bridge->iack_queue)); return CA91CX42_LINT_SW_IACK; } @@ -115,22 +97,22 @@ static u32 ca91cx42_IACK_irqhandler(void) int ca91cx42_bus_error_chk(int clrflag) { int tmp; - tmp = ioread32(ca91cx42_bridge->base + PCI_COMMAND); + tmp = ioread32(bridge->base + PCI_COMMAND); if (tmp & 0x08000000) { /* S_TA is Set */ if (clrflag) iowrite32(tmp | 0x08000000, - ca91cx42_bridge->base + PCI_COMMAND); + bridge->base + PCI_COMMAND); return 1; } return 0; } #endif -static u32 ca91cx42_VERR_irqhandler(void) +static u32 ca91cx42_VERR_irqhandler(struct ca91cx42_driver *bridge) { int val; - val = ioread32(ca91cx42_bridge->base + DGCS); + val = ioread32(bridge->base + DGCS); if (!(val & 0x00000800)) { printk(KERN_ERR "ca91c042: ca91cx42_VERR_irqhandler DMA Read " @@ -140,11 +122,11 @@ static u32 ca91cx42_VERR_irqhandler(void) return CA91CX42_LINT_VERR; } -static u32 ca91cx42_LERR_irqhandler(void) +static u32 ca91cx42_LERR_irqhandler(struct ca91cx42_driver *bridge) { int val; - val = ioread32(ca91cx42_bridge->base + DGCS); + val = ioread32(bridge->base + DGCS); if (!(val & 0x00000800)) { printk(KERN_ERR "ca91c042: ca91cx42_LERR_irqhandler DMA Read " @@ -156,13 +138,18 @@ static u32 ca91cx42_LERR_irqhandler(void) } -static u32 ca91cx42_VIRQ_irqhandler(int stat) +static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge, + int stat) { int vec, i, serviced = 0; + struct ca91cx42_driver *bridge; + + bridge = ca91cx42_bridge->driver_priv; + for (i = 7; i > 0; i--) { if (stat & (1 << i)) { - vec = ioread32(ca91cx42_bridge->base + + vec = ioread32(bridge->base + CA91CX42_V_STATID[i]) & 0xff; vme_irq_handler(ca91cx42_bridge, i, vec); @@ -174,15 +161,18 @@ static u32 ca91cx42_VIRQ_irqhandler(int stat) return serviced; } -static irqreturn_t ca91cx42_irqhandler(int irq, void *dev_id) +static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr) { u32 stat, enable, serviced = 0; + struct vme_bridge *ca91cx42_bridge; + struct ca91cx42_driver *bridge; - if (dev_id != ca91cx42_bridge->base) - return IRQ_NONE; + ca91cx42_bridge = ptr; - enable = ioread32(ca91cx42_bridge->base + LINT_EN); - stat = ioread32(ca91cx42_bridge->base + LINT_STAT); + bridge = ca91cx42_bridge->driver_priv; + + enable = ioread32(bridge->base + LINT_EN); + stat = ioread32(bridge->base + LINT_STAT); /* Only look at unmasked interrupts */ stat &= enable; @@ -191,42 +181,45 @@ static irqreturn_t ca91cx42_irqhandler(int irq, void *dev_id) return IRQ_NONE; if (stat & CA91CX42_LINT_DMA) - serviced |= ca91cx42_DMA_irqhandler(); + serviced |= ca91cx42_DMA_irqhandler(bridge); if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 | CA91CX42_LINT_LM3)) - serviced |= ca91cx42_LM_irqhandler(stat); + serviced |= ca91cx42_LM_irqhandler(bridge, stat); if (stat & CA91CX42_LINT_MBOX) - serviced |= ca91cx42_MB_irqhandler(stat); + serviced |= ca91cx42_MB_irqhandler(bridge, stat); if (stat & CA91CX42_LINT_SW_IACK) - serviced |= ca91cx42_IACK_irqhandler(); + serviced |= ca91cx42_IACK_irqhandler(bridge); if (stat & CA91CX42_LINT_VERR) - serviced |= ca91cx42_VERR_irqhandler(); + serviced |= ca91cx42_VERR_irqhandler(bridge); if (stat & CA91CX42_LINT_LERR) - serviced |= ca91cx42_LERR_irqhandler(); + serviced |= ca91cx42_LERR_irqhandler(bridge); if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 | CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 | CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 | CA91CX42_LINT_VIRQ7)) - serviced |= ca91cx42_VIRQ_irqhandler(stat); + serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat); /* Clear serviced interrupts */ - iowrite32(stat, ca91cx42_bridge->base + LINT_STAT); + iowrite32(stat, bridge->base + LINT_STAT); return IRQ_HANDLED; } -static int ca91cx42_irq_init(struct vme_bridge *bridge) +static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge) { int result, tmp; struct pci_dev *pdev; + struct ca91cx42_driver *bridge; + + bridge = ca91cx42_bridge->driver_priv; /* Need pdev */ - pdev = container_of(bridge->parent, struct pci_dev, dev); + pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev); /* Initialise list for VME bus errors */ - INIT_LIST_HEAD(&(bridge->vme_errors)); + INIT_LIST_HEAD(&(ca91cx42_bridge->vme_errors)); - mutex_init(&(bridge->irq_mtx)); + mutex_init(&(ca91cx42_bridge->irq_mtx)); /* Disable interrupts from PCI to VME */ iowrite32(0, bridge->base + VINT_EN); @@ -237,7 +230,7 @@ static int ca91cx42_irq_init(struct vme_bridge *bridge) iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED, - driver_name, pdev); + driver_name, ca91cx42_bridge); if (result) { dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n", pdev->irq); @@ -259,15 +252,16 @@ static int ca91cx42_irq_init(struct vme_bridge *bridge) return 0; } -static void ca91cx42_irq_exit(struct pci_dev *pdev) +static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge, + struct pci_dev *pdev) { /* Disable interrupts from PCI to VME */ - iowrite32(0, ca91cx42_bridge->base + VINT_EN); + iowrite32(0, bridge->base + VINT_EN); /* Disable PCI interrupts */ - iowrite32(0, ca91cx42_bridge->base + LINT_EN); + iowrite32(0, bridge->base + LINT_EN); /* Clear Any Pending PCI Interrupts */ - iowrite32(0x00FFFFFF, ca91cx42_bridge->base + LINT_STAT); + iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); free_irq(pdev->irq, pdev); } @@ -275,21 +269,25 @@ static void ca91cx42_irq_exit(struct pci_dev *pdev) /* * Set up an VME interrupt */ -void ca91cx42_irq_set(int level, int state, int sync) +void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level, int state, + int sync) { struct pci_dev *pdev; u32 tmp; + struct ca91cx42_driver *bridge; + + bridge = ca91cx42_bridge->driver_priv; /* Enable IRQ level */ - tmp = ioread32(ca91cx42_bridge->base + LINT_EN); + tmp = ioread32(bridge->base + LINT_EN); if (state == 0) tmp &= ~CA91CX42_LINT_VIRQ[level]; else tmp |= CA91CX42_LINT_VIRQ[level]; - iowrite32(tmp, ca91cx42_bridge->base + LINT_EN); + iowrite32(tmp, bridge->base + LINT_EN); if ((state == 0) && (sync != 0)) { pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, @@ -299,34 +297,38 @@ void ca91cx42_irq_set(int level, int state, int sync) } } -int ca91cx42_irq_generate(int level, int statid) +int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level, + int statid) { u32 tmp; + struct ca91cx42_driver *bridge; + + bridge = ca91cx42_bridge->driver_priv; /* Universe can only generate even vectors */ if (statid & 1) return -EINVAL; - mutex_lock(&(vme_int)); + mutex_lock(&(bridge->vme_int)); - tmp = ioread32(ca91cx42_bridge->base + VINT_EN); + tmp = ioread32(bridge->base + VINT_EN); /* Set Status/ID */ - iowrite32(statid << 24, ca91cx42_bridge->base + STATID); + iowrite32(statid << 24, bridge->base + STATID); /* Assert VMEbus IRQ */ tmp = tmp | (1 << (level + 24)); - iowrite32(tmp, ca91cx42_bridge->base + VINT_EN); + iowrite32(tmp, bridge->base + VINT_EN); /* Wait for IACK */ - wait_event_interruptible(iack_queue, 0); + wait_event_interruptible(bridge->iack_queue, 0); /* Return interrupt to low state */ - tmp = ioread32(ca91cx42_bridge->base + VINT_EN); + tmp = ioread32(bridge->base + VINT_EN); tmp = tmp & ~(1 << (level + 24)); - iowrite32(tmp, ca91cx42_bridge->base + VINT_EN); + iowrite32(tmp, bridge->base + VINT_EN); - mutex_unlock(&(vme_int)); + mutex_unlock(&(bridge->vme_int)); return 0; } @@ -338,6 +340,9 @@ int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, unsigned int i, addr = 0, granularity = 0; unsigned int temp_ctl = 0; unsigned int vme_bound, pci_offset; + struct ca91cx42_driver *bridge; + + bridge = image->parent->driver_priv; i = image->number; @@ -397,14 +402,14 @@ int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, } /* Disable while we are mucking around */ - temp_ctl = ioread32(ca91cx42_bridge->base + CA91CX42_VSI_CTL[i]); + temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); temp_ctl &= ~CA91CX42_VSI_CTL_EN; - iowrite32(temp_ctl, ca91cx42_bridge->base + CA91CX42_VSI_CTL[i]); + iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); /* Setup mapping */ - iowrite32(vme_base, ca91cx42_bridge->base + CA91CX42_VSI_BS[i]); - iowrite32(vme_bound, ca91cx42_bridge->base + CA91CX42_VSI_BD[i]); - iowrite32(pci_offset, ca91cx42_bridge->base + CA91CX42_VSI_TO[i]); + iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]); + iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]); + iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]); /* XXX Prefetch stuff currently unsupported */ #if 0 @@ -434,12 +439,12 @@ int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA; /* Write ctl reg without enable */ - iowrite32(temp_ctl, ca91cx42_bridge->base + CA91CX42_VSI_CTL[i]); + iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); if (enabled) temp_ctl |= CA91CX42_VSI_CTL_EN; - iowrite32(temp_ctl, ca91cx42_bridge->base + CA91CX42_VSI_CTL[i]); + iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); return 0; } @@ -450,6 +455,9 @@ int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled, { unsigned int i, granularity = 0, ctl = 0; unsigned long long vme_bound, pci_offset; + struct ca91cx42_driver *bridge; + + bridge = image->parent->driver_priv; i = image->number; @@ -459,11 +467,11 @@ int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled, granularity = 0x10000; /* Read Registers */ - ctl = ioread32(ca91cx42_bridge->base + CA91CX42_VSI_CTL[i]); + ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); - *vme_base = ioread32(ca91cx42_bridge->base + CA91CX42_VSI_BS[i]); - vme_bound = ioread32(ca91cx42_bridge->base + CA91CX42_VSI_BD[i]); - pci_offset = ioread32(ca91cx42_bridge->base + CA91CX42_VSI_TO[i]); + *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]); + vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]); + pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]); *pci_base = (dma_addr_t)vme_base + pci_offset; *size = (unsigned long long)((vme_bound - *vme_base) + granularity); @@ -507,6 +515,9 @@ static int ca91cx42_alloc_resource(struct vme_master_resource *image, unsigned long long existing_size; int retval = 0; struct pci_dev *pdev; + struct vme_bridge *ca91cx42_bridge; + + ca91cx42_bridge = image->parent; /* Find pci_dev container of dev */ if (ca91cx42_bridge->parent == NULL) { @@ -601,6 +612,9 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, unsigned int i; unsigned int temp_ctl = 0; unsigned long long pci_bound, vme_offset, pci_base; + struct ca91cx42_driver *bridge; + + bridge = image->parent->driver_priv; /* Verify input data */ if (vme_base & 0xFFF) { @@ -644,9 +658,9 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, i = image->number; /* Disable while we are mucking around */ - temp_ctl = ioread32(ca91cx42_bridge->base + CA91CX42_LSI_CTL[i]); + temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); temp_ctl &= ~CA91CX42_LSI_CTL_EN; - iowrite32(temp_ctl, ca91cx42_bridge->base + CA91CX42_LSI_CTL[i]); + iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); /* XXX Prefetch stuff currently unsupported */ #if 0 @@ -723,17 +737,17 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM; /* Setup mapping */ - iowrite32(pci_base, ca91cx42_bridge->base + CA91CX42_LSI_BS[i]); - iowrite32(pci_bound, ca91cx42_bridge->base + CA91CX42_LSI_BD[i]); - iowrite32(vme_offset, ca91cx42_bridge->base + CA91CX42_LSI_TO[i]); + iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]); + iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]); + iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]); /* Write ctl reg without enable */ - iowrite32(temp_ctl, ca91cx42_bridge->base + CA91CX42_LSI_CTL[i]); + iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); if (enabled) temp_ctl |= CA91CX42_LSI_CTL_EN; - iowrite32(temp_ctl, ca91cx42_bridge->base + CA91CX42_LSI_CTL[i]); + iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); spin_unlock(&(image->lock)); return 0; @@ -752,14 +766,17 @@ int __ca91cx42_master_get(struct vme_master_resource *image, int *enabled, { unsigned int i, ctl; unsigned long long pci_base, pci_bound, vme_offset; + struct ca91cx42_driver *bridge; + + bridge = image->parent->driver_priv; i = image->number; - ctl = ioread32(ca91cx42_bridge->base + CA91CX42_LSI_CTL[i]); + ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); - pci_base = ioread32(ca91cx42_bridge->base + CA91CX42_LSI_BS[i]); - vme_offset = ioread32(ca91cx42_bridge->base + CA91CX42_LSI_TO[i]); - pci_bound = ioread32(ca91cx42_bridge->base + CA91CX42_LSI_BD[i]); + pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]); + vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]); + pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]); *vme_base = pci_base + vme_offset; *size = (pci_bound - pci_base) + 0x1000; @@ -882,12 +899,15 @@ ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf, return retval; } -int ca91cx42_slot_get(void) +int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge) { u32 slot = 0; + struct ca91cx42_driver *bridge; + + bridge = ca91cx42_bridge->driver_priv; if (!geoid) { - slot = ioread32(ca91cx42_bridge->base + VCSR_BS); + slot = ioread32(bridge->base + VCSR_BS); slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27); } else slot = geoid; @@ -909,19 +929,23 @@ static int __init ca91cx42_init(void) * Auto-ID or Geographic address. This function ensures that the window is * enabled at an offset consistent with the boards geopgraphic address. */ -static int ca91cx42_crcsr_init(struct pci_dev *pdev) +static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge, + struct pci_dev *pdev) { unsigned int crcsr_addr; int tmp, slot; + struct ca91cx42_driver *bridge; + + bridge = ca91cx42_bridge->driver_priv; /* XXX We may need to set this somehow as the Universe II does not support * geographical addressing. */ #if 0 if (vme_slotnum != -1) - iowrite32(vme_slotnum << 27, ca91cx42_bridge->base + VCSR_BS); + iowrite32(vme_slotnum << 27, bridge->base + VCSR_BS); #endif - slot = ca91cx42_slot_get(); + slot = ca91cx42_slot_get(ca91cx42_bridge); dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot); if (slot == 0) { dev_err(&pdev->dev, "Slot number is unset, not configuring " @@ -930,39 +954,44 @@ static int ca91cx42_crcsr_init(struct pci_dev *pdev) } /* Allocate mem for CR/CSR image */ - crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, - &crcsr_bus); - if (crcsr_kernel == NULL) { + bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, + &(bridge->crcsr_bus)); + if (bridge->crcsr_kernel == NULL) { dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR " "image\n"); return -ENOMEM; } - memset(crcsr_kernel, 0, VME_CRCSR_BUF_SIZE); + memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE); crcsr_addr = slot * (512 * 1024); - iowrite32(crcsr_bus - crcsr_addr, ca91cx42_bridge->base + VCSR_TO); + iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO); - tmp = ioread32(ca91cx42_bridge->base + VCSR_CTL); + tmp = ioread32(bridge->base + VCSR_CTL); tmp |= CA91CX42_VCSR_CTL_EN; - iowrite32(tmp, ca91cx42_bridge->base + VCSR_CTL); + iowrite32(tmp, bridge->base + VCSR_CTL); return 0; } -static void ca91cx42_crcsr_exit(struct pci_dev *pdev) +static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge, + struct pci_dev *pdev) { u32 tmp; + struct ca91cx42_driver *bridge; + + bridge = ca91cx42_bridge->driver_priv; /* Turn off CR/CSR space */ - tmp = ioread32(ca91cx42_bridge->base + VCSR_CTL); + tmp = ioread32(bridge->base + VCSR_CTL); tmp &= ~CA91CX42_VCSR_CTL_EN; - iowrite32(tmp, ca91cx42_bridge->base + VCSR_CTL); + iowrite32(tmp, bridge->base + VCSR_CTL); /* Free image */ - iowrite32(0, ca91cx42_bridge->base + VCSR_TO); + iowrite32(0, bridge->base + VCSR_TO); - pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, crcsr_kernel, crcsr_bus); + pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, + bridge->crcsr_bus); } static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) @@ -970,6 +999,8 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) int retval, i; u32 data; struct list_head *pos = NULL; + struct vme_bridge *ca91cx42_bridge; + struct ca91cx42_driver *ca91cx42_device; struct vme_master_resource *master_image; struct vme_slave_resource *slave_image; #if 0 @@ -991,6 +1022,19 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) memset(ca91cx42_bridge, 0, sizeof(struct vme_bridge)); + ca91cx42_device = kmalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL); + + if (ca91cx42_device == NULL) { + dev_err(&pdev->dev, "Failed to allocate memory for device " + "structure\n"); + retval = -ENOMEM; + goto err_driver; + } + + memset(ca91cx42_device, 0, sizeof(struct ca91cx42_driver)); + + ca91cx42_bridge->driver_priv = ca91cx42_device; + /* Enable the device */ retval = pci_enable_device(pdev); if (retval) { @@ -1006,16 +1050,16 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) } /* map registers in BAR 0 */ - ca91cx42_bridge->base = ioremap_nocache(pci_resource_start(pdev, 0), + ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0), 4096); - if (!ca91cx42_bridge->base) { + if (!ca91cx42_device->base) { dev_err(&pdev->dev, "Unable to remap CRG region\n"); retval = -EIO; goto err_remap; } /* Check to see if the mapping worked out */ - data = ioread32(ca91cx42_bridge->base + CA91CX42_PCI_ID) & 0x0000FFFF; + data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF; if (data != PCI_VENDOR_ID_TUNDRA) { dev_err(&pdev->dev, "PCI_ID check failed\n"); retval = -EIO; @@ -1023,11 +1067,10 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) } /* Initialize wait queues & mutual exclusion flags */ - /* XXX These need to be moved to the vme_bridge structure */ - init_waitqueue_head(&dma_queue); - init_waitqueue_head(&iack_queue); - mutex_init(&(vme_int)); - mutex_init(&(vme_rmw)); + init_waitqueue_head(&(ca91cx42_device->dma_queue)); + init_waitqueue_head(&(ca91cx42_device->iack_queue)); + mutex_init(&(ca91cx42_device->vme_int)); + mutex_init(&(ca91cx42_device->vme_rmw)); ca91cx42_bridge->parent = &(pdev->dev); strcpy(ca91cx42_bridge->name, driver_name); @@ -1155,12 +1198,13 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) #endif ca91cx42_bridge->slot_get = ca91cx42_slot_get; - data = ioread32(ca91cx42_bridge->base + MISC_CTL); + data = ioread32(ca91cx42_device->base + MISC_CTL); dev_info(&pdev->dev, "Board is%s the VME system controller\n", (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not"); - dev_info(&pdev->dev, "Slot ID is %d\n", ca91cx42_slot_get()); + dev_info(&pdev->dev, "Slot ID is %d\n", + ca91cx42_slot_get(ca91cx42_bridge)); - if (ca91cx42_crcsr_init(pdev)) { + if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev)) { dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); retval = -EINVAL; #if 0 @@ -1177,11 +1221,13 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) goto err_reg; } + pci_set_drvdata(pdev, ca91cx42_bridge); + return 0; vme_unregister_bridge(ca91cx42_bridge); err_reg: - ca91cx42_crcsr_exit(pdev); + ca91cx42_crcsr_exit(ca91cx42_bridge, pdev); #if 0 err_crcsr: #endif @@ -1217,15 +1263,17 @@ err_master: kfree(master_image); } - ca91cx42_irq_exit(pdev); + ca91cx42_irq_exit(ca91cx42_device, pdev); err_irq: err_test: - iounmap(ca91cx42_bridge->base); + iounmap(ca91cx42_device->base); err_remap: pci_release_regions(pdev); err_resource: pci_disable_device(pdev); err_enable: + kfree(ca91cx42_device); +err_driver: kfree(ca91cx42_bridge); err_struct: return retval; @@ -1239,27 +1287,32 @@ void ca91cx42_remove(struct pci_dev *pdev) struct vme_slave_resource *slave_image; struct vme_dma_resource *dma_ctrlr; struct vme_lm_resource *lm; + struct ca91cx42_driver *bridge; + struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev); + + bridge = ca91cx42_bridge->driver_priv; + /* Turn off Ints */ - iowrite32(0, ca91cx42_bridge->base + LINT_EN); + iowrite32(0, bridge->base + LINT_EN); /* Turn off the windows */ - iowrite32(0x00800000, ca91cx42_bridge->base + LSI0_CTL); - iowrite32(0x00800000, ca91cx42_bridge->base + LSI1_CTL); - iowrite32(0x00800000, ca91cx42_bridge->base + LSI2_CTL); - iowrite32(0x00800000, ca91cx42_bridge->base + LSI3_CTL); - iowrite32(0x00800000, ca91cx42_bridge->base + LSI4_CTL); - iowrite32(0x00800000, ca91cx42_bridge->base + LSI5_CTL); - iowrite32(0x00800000, ca91cx42_bridge->base + LSI6_CTL); - iowrite32(0x00800000, ca91cx42_bridge->base + LSI7_CTL); - iowrite32(0x00F00000, ca91cx42_bridge->base + VSI0_CTL); - iowrite32(0x00F00000, ca91cx42_bridge->base + VSI1_CTL); - iowrite32(0x00F00000, ca91cx42_bridge->base + VSI2_CTL); - iowrite32(0x00F00000, ca91cx42_bridge->base + VSI3_CTL); - iowrite32(0x00F00000, ca91cx42_bridge->base + VSI4_CTL); - iowrite32(0x00F00000, ca91cx42_bridge->base + VSI5_CTL); - iowrite32(0x00F00000, ca91cx42_bridge->base + VSI6_CTL); - iowrite32(0x00F00000, ca91cx42_bridge->base + VSI7_CTL); + iowrite32(0x00800000, bridge->base + LSI0_CTL); + iowrite32(0x00800000, bridge->base + LSI1_CTL); + iowrite32(0x00800000, bridge->base + LSI2_CTL); + iowrite32(0x00800000, bridge->base + LSI3_CTL); + iowrite32(0x00800000, bridge->base + LSI4_CTL); + iowrite32(0x00800000, bridge->base + LSI5_CTL); + iowrite32(0x00800000, bridge->base + LSI6_CTL); + iowrite32(0x00800000, bridge->base + LSI7_CTL); + iowrite32(0x00F00000, bridge->base + VSI0_CTL); + iowrite32(0x00F00000, bridge->base + VSI1_CTL); + iowrite32(0x00F00000, bridge->base + VSI2_CTL); + iowrite32(0x00F00000, bridge->base + VSI3_CTL); + iowrite32(0x00F00000, bridge->base + VSI4_CTL); + iowrite32(0x00F00000, bridge->base + VSI5_CTL); + iowrite32(0x00F00000, bridge->base + VSI6_CTL); + iowrite32(0x00F00000, bridge->base + VSI7_CTL); vme_unregister_bridge(ca91cx42_bridge); #if 0 @@ -1294,9 +1347,9 @@ void ca91cx42_remove(struct pci_dev *pdev) kfree(master_image); } - ca91cx42_irq_exit(pdev); + ca91cx42_irq_exit(bridge, pdev); - iounmap(ca91cx42_bridge->base); + iounmap(bridge->base); pci_release_regions(pdev); @@ -1346,7 +1399,7 @@ int ca91cx42_master_rmw(vmeRmwCfg_t *vmeRmw) } /* Find the PCI address that maps to the desired VME address */ for (i = 0; i < 8; i++) { - temp_ctl = ioread32(ca91cx42_bridge->base + + temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); if ((temp_ctl & 0x80000000) == 0) { continue; @@ -1357,9 +1410,9 @@ int ca91cx42_master_rmw(vmeRmwCfg_t *vmeRmw) if (vmeOut.addrSpace != vmeRmw->addrSpace) { continue; } - tempBS = ioread32(ca91cx42_bridge->base + CA91CX42_LSI_BS[i]); - tempBD = ioread32(ca91cx42_bridge->base + CA91CX42_LSI_BD[i]); - tempTO = ioread32(ca91cx42_bridge->base + CA91CX42_LSI_TO[i]); + tempBS = ioread32(bridge->base + CA91CX42_LSI_BS[i]); + tempBD = ioread32(bridge->base + CA91CX42_LSI_BD[i]); + tempTO = ioread32(bridge->base + CA91CX42_LSI_TO[i]); vmeBS = tempBS + tempTO; vmeBD = tempBD + tempTO; if ((vmeRmw->targetAddr >= vmeBS) && @@ -1378,13 +1431,13 @@ int ca91cx42_master_rmw(vmeRmwCfg_t *vmeRmw) return -EINVAL; } /* Setup the RMW registers. */ - iowrite32(0, ca91cx42_bridge->base + SCYC_CTL); - iowrite32(SWIZZLE(vmeRmw->enableMask), ca91cx42_bridge->base + SCYC_EN); - iowrite32(SWIZZLE(vmeRmw->compareData), ca91cx42_bridge->base + + iowrite32(0, bridge->base + SCYC_CTL); + iowrite32(SWIZZLE(vmeRmw->enableMask), bridge->base + SCYC_EN); + iowrite32(SWIZZLE(vmeRmw->compareData), bridge->base + SCYC_CMP); - iowrite32(SWIZZLE(vmeRmw->swapData), ca91cx42_bridge->base + SCYC_SWP); - iowrite32((int)rmw_pci_data_ptr, ca91cx42_bridge->base + SCYC_ADDR); - iowrite32(1, ca91cx42_bridge->base + SCYC_CTL); + iowrite32(SWIZZLE(vmeRmw->swapData), bridge->base + SCYC_SWP); + iowrite32((int)rmw_pci_data_ptr, bridge->base + SCYC_ADDR); + iowrite32(1, bridge->base + SCYC_CTL); /* Run the RMW cycle until either success or max attempts. */ vmeRmw->numAttempts = 1; @@ -1393,7 +1446,7 @@ int ca91cx42_master_rmw(vmeRmwCfg_t *vmeRmw) if ((ioread32(vaDataPtr) & vmeRmw->enableMask) == (vmeRmw->swapData & vmeRmw->enableMask)) { - iowrite32(0, ca91cx42_bridge->base + SCYC_CTL); + iowrite32(0, bridge->base + SCYC_CTL); break; } @@ -1478,8 +1531,8 @@ ca91cx42_start_dma(int channel, unsigned int dgcsreg, TDMA_Cmd_Packet *vmeLL) /* Setup registers as needed for direct or chained. */ if (dgcsreg & 0x8000000) { - iowrite32(0, ca91cx42_bridge->base + DTBC); - iowrite32((unsigned int)vmeLL, ca91cx42_bridge->base + DCPP); + iowrite32(0, bridge->base + DTBC); + iowrite32((unsigned int)vmeLL, bridge->base + DCPP); } else { #if 0 printk(KERN_ERR "Starting: DGCS = %08x\n", dgcsreg); @@ -1493,17 +1546,17 @@ ca91cx42_start_dma(int channel, unsigned int dgcsreg, TDMA_Cmd_Packet *vmeLL) ioread32(&vmeLL->dctl)); #endif /* Write registers */ - iowrite32(ioread32(&vmeLL->dva), ca91cx42_bridge->base + DVA); - iowrite32(ioread32(&vmeLL->dlv), ca91cx42_bridge->base + DLA); - iowrite32(ioread32(&vmeLL->dtbc), ca91cx42_bridge->base + DTBC); - iowrite32(ioread32(&vmeLL->dctl), ca91cx42_bridge->base + DCTL); - iowrite32(0, ca91cx42_bridge->base + DCPP); + iowrite32(ioread32(&vmeLL->dva), bridge->base + DVA); + iowrite32(ioread32(&vmeLL->dlv), bridge->base + DLA); + iowrite32(ioread32(&vmeLL->dtbc), bridge->base + DTBC); + iowrite32(ioread32(&vmeLL->dctl), bridge->base + DCTL); + iowrite32(0, bridge->base + DCPP); } /* Start the operation */ - iowrite32(dgcsreg, ca91cx42_bridge->base + DGCS); + iowrite32(dgcsreg, bridge->base + DGCS); val = get_tbl(); - iowrite32(dgcsreg | 0x8000000F, ca91cx42_bridge->base + DGCS); + iowrite32(dgcsreg | 0x8000000F, bridge->base + DGCS); return val; } @@ -1704,10 +1757,10 @@ int ca91cx42_do_dma(vmeDmaPacket_t *vmeDma) } wait_event_interruptible(dma_queue, - ioread32(ca91cx42_bridge->base + DGCS) & 0x800); + ioread32(bridge->base + DGCS) & 0x800); - val = ioread32(ca91cx42_bridge->base + DGCS); - iowrite32(val | 0xF00, ca91cx42_bridge->base + DGCS); + val = ioread32(bridge->base + DGCS); + iowrite32(val | 0xF00, bridge->base + DGCS); vmeDma->vmeDmaStatus = 0; @@ -1715,15 +1768,15 @@ int ca91cx42_do_dma(vmeDmaPacket_t *vmeDma) vmeDma->vmeDmaStatus = val & 0x700; printk(KERN_ERR "ca91c042: DMA Error in ca91cx42_DMA_irqhandler" " DGCS=%08X\n", val); - val = ioread32(ca91cx42_bridge->base + DCPP); + val = ioread32(bridge->base + DCPP); printk(KERN_ERR "ca91c042: DCPP=%08X\n", val); - val = ioread32(ca91cx42_bridge->base + DCTL); + val = ioread32(bridge->base + DCTL); printk(KERN_ERR "ca91c042: DCTL=%08X\n", val); - val = ioread32(ca91cx42_bridge->base + DTBC); + val = ioread32(bridge->base + DTBC); printk(KERN_ERR "ca91c042: DTBC=%08X\n", val); - val = ioread32(ca91cx42_bridge->base + DLA); + val = ioread32(bridge->base + DLA); printk(KERN_ERR "ca91c042: DLA=%08X\n", val); - val = ioread32(ca91cx42_bridge->base + DVA); + val = ioread32(bridge->base + DVA); printk(KERN_ERR "ca91c042: DVA=%08X\n", val); } @@ -1766,9 +1819,9 @@ int ca91cx42_lm_set(vmeLmCfg_t *vmeLm) } /* Disable while we are mucking around */ - iowrite32(0x00000000, ca91cx42_bridge->base + LM_CTL); + iowrite32(0x00000000, bridge->base + LM_CTL); - iowrite32(vmeLm->addr, ca91cx42_bridge->base + LM_BS); + iowrite32(vmeLm->addr, bridge->base + LM_BS); /* Setup CTL register. */ if (vmeLm->userAccessType & VME_SUPER) @@ -1782,8 +1835,8 @@ int ca91cx42_lm_set(vmeLmCfg_t *vmeLm) /* Write ctl reg and enable */ - iowrite32(0x80000000 | temp_ctl, ca91cx42_bridge->base + LM_CTL); - temp_ctl = ioread32(ca91cx42_bridge->base + LM_CTL); + iowrite32(0x80000000 | temp_ctl, bridge->base + LM_CTL); + temp_ctl = ioread32(bridge->base + LM_CTL); return 0; } @@ -1800,7 +1853,7 @@ int ca91cx42_wait_lm(vmeLmCfg_t *vmeLm) vmeLm->lmWait = 10; interruptible_sleep_on_timeout(&lm_queue, vmeLm->lmWait); } - iowrite32(0x00000000, ca91cx42_bridge->base + LM_CTL); + iowrite32(0x00000000, bridge->base + LM_CTL); return 0; } @@ -1812,7 +1865,7 @@ int ca91cx42_set_arbiter(vmeArbiterCfg_t *vmeArb) int temp_ctl = 0; int vbto = 0; - temp_ctl = ioread32(ca91cx42_bridge->base + MISC_CTL); + temp_ctl = ioread32(bridge->base + MISC_CTL); temp_ctl &= 0x00FFFFFF; if (vmeArb->globalTimeoutTimer == 0xFFFFFFFF) { @@ -1834,7 +1887,7 @@ int ca91cx42_set_arbiter(vmeArbiterCfg_t *vmeArb) if (vmeArb->arbiterTimeoutFlag) temp_ctl |= 2 << 24; - iowrite32(temp_ctl, ca91cx42_bridge->base + MISC_CTL); + iowrite32(temp_ctl, bridge->base + MISC_CTL); return 0; } @@ -1843,7 +1896,7 @@ int ca91cx42_get_arbiter(vmeArbiterCfg_t *vmeArb) int temp_ctl = 0; int vbto = 0; - temp_ctl = ioread32(ca91cx42_bridge->base + MISC_CTL); + temp_ctl = ioread32(bridge->base + MISC_CTL); vbto = (temp_ctl >> 28) & 0xF; if (vbto != 0) @@ -1864,7 +1917,7 @@ int ca91cx42_set_requestor(vmeRequesterCfg_t *vmeReq) { int temp_ctl = 0; - temp_ctl = ioread32(ca91cx42_bridge->base + MAST_CTL); + temp_ctl = ioread32(bridge->base + MAST_CTL); temp_ctl &= 0xFF0FFFFF; if (vmeReq->releaseMode == 1) @@ -1875,7 +1928,7 @@ int ca91cx42_set_requestor(vmeRequesterCfg_t *vmeReq) temp_ctl |= (vmeReq->requestLevel << 22); - iowrite32(temp_ctl, ca91cx42_bridge->base + MAST_CTL); + iowrite32(temp_ctl, bridge->base + MAST_CTL); return 0; } @@ -1883,7 +1936,7 @@ int ca91cx42_get_requestor(vmeRequesterCfg_t *vmeReq) { int temp_ctl = 0; - temp_ctl = ioread32(ca91cx42_bridge->base + MAST_CTL); + temp_ctl = ioread32(bridge->base + MAST_CTL); if (temp_ctl & (1 << 20)) vmeReq->releaseMode = 1; diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.h b/drivers/staging/vme/bridges/vme_ca91cx42.h index 2a9ad1454f4e..df1050297849 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.h +++ b/drivers/staging/vme/bridges/vme_ca91cx42.h @@ -37,6 +37,22 @@ #define CA91C142_MAX_DMA 1 /* Max DMA Controllers */ #define CA91C142_MAX_MAILBOX 4 /* Max Mail Box registers */ +/* Structure used to hold driver specific information */ +struct ca91cx42_driver { + void *base; /* Base Address of device registers */ + wait_queue_head_t dma_queue; + wait_queue_head_t iack_queue; + wait_queue_head_t mbox_queue; + void (*lm_callback[4])(int); /* Called in interrupt handler */ + void *crcsr_kernel; + dma_addr_t crcsr_bus; + struct mutex vme_rmw; /* Only one RMW cycle at a time */ + struct mutex vme_int; /* + * Only one VME interrupt can be + * generated at a time, provide locking + */ +}; + /* See Page 2-77 in the Universe User Manual */ struct ca91cx42_dma_descriptor { unsigned int dctl; /* DMA Control */ diff --git a/drivers/staging/vme/bridges/vme_tsi148.c b/drivers/staging/vme/bridges/vme_tsi148.c index e74c4a953b2d..e3d300c9bfba 100644 --- a/drivers/staging/vme/bridges/vme_tsi148.c +++ b/drivers/staging/vme/bridges/vme_tsi148.c @@ -59,26 +59,11 @@ int tsi148_dma_list_add (struct vme_dma_list *, struct vme_dma_attr *, int tsi148_dma_list_exec(struct vme_dma_list *); int tsi148_dma_list_empty(struct vme_dma_list *); int tsi148_generate_irq(int, int); -int tsi148_slot_get(void); -/* Modue parameter */ +/* Module parameter */ static int err_chk; static int geoid; -/* XXX These should all be in a per device structure */ -static struct vme_bridge *tsi148_bridge; -static wait_queue_head_t dma_queue[2]; -static wait_queue_head_t iack_queue; -static void (*lm_callback[4])(int); /* Called in interrupt handler */ -static void *crcsr_kernel; -static dma_addr_t crcsr_bus; -static struct vme_master_resource *flush_image; -static struct mutex vme_rmw; /* Only one RMW cycle at a time */ -static struct mutex vme_int; /* - * Only one VME interrupt can be - * generated at a time, provide locking - */ - static char driver_name[] = "vme_tsi148"; static const struct pci_device_id tsi148_ids[] = { @@ -110,16 +95,17 @@ static void reg_split(unsigned long long variable, unsigned int *high, /* * Wakes up DMA queue. */ -static u32 tsi148_DMA_irqhandler(int channel_mask) +static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge, + int channel_mask) { u32 serviced = 0; if (channel_mask & TSI148_LCSR_INTS_DMA0S) { - wake_up(&dma_queue[0]); + wake_up(&(bridge->dma_queue[0])); serviced |= TSI148_LCSR_INTC_DMA0C; } if (channel_mask & TSI148_LCSR_INTS_DMA1S) { - wake_up(&dma_queue[1]); + wake_up(&(bridge->dma_queue[1])); serviced |= TSI148_LCSR_INTC_DMA1C; } @@ -129,7 +115,7 @@ static u32 tsi148_DMA_irqhandler(int channel_mask) /* * Wake up location monitor queue */ -static u32 tsi148_LM_irqhandler(u32 stat) +static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat) { int i; u32 serviced = 0; @@ -137,7 +123,7 @@ static u32 tsi148_LM_irqhandler(u32 stat) for (i = 0; i < 4; i++) { if(stat & TSI148_LCSR_INTS_LMS[i]) { /* We only enable interrupts if the callback is set */ - lm_callback[i](i); + bridge->lm_callback[i](i); serviced |= TSI148_LCSR_INTC_LMC[i]; } } @@ -150,7 +136,7 @@ static u32 tsi148_LM_irqhandler(u32 stat) * * XXX This functionality is not exposed up though API. */ -static u32 tsi148_MB_irqhandler(u32 stat) +static u32 tsi148_MB_irqhandler(struct tsi148_driver *bridge, u32 stat) { int i; u32 val; @@ -158,8 +144,7 @@ static u32 tsi148_MB_irqhandler(u32 stat) for (i = 0; i < 4; i++) { if(stat & TSI148_LCSR_INTS_MBS[i]) { - val = ioread32be(tsi148_bridge->base + - TSI148_GCSR_MBOX[i]); + val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); printk("VME Mailbox %d received: 0x%x\n", i, val); serviced |= TSI148_LCSR_INTC_MBC[i]; } @@ -171,22 +156,21 @@ static u32 tsi148_MB_irqhandler(u32 stat) /* * Display error & status message when PERR (PCI) exception interrupt occurs. */ -static u32 tsi148_PERR_irqhandler(void) +static u32 tsi148_PERR_irqhandler(struct tsi148_driver *bridge) { printk(KERN_ERR "PCI Exception at address: 0x%08x:%08x, attributes: %08x\n", - ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAU), - ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAL), - ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAT) + ioread32be(bridge->base + TSI148_LCSR_EDPAU), + ioread32be(bridge->base + TSI148_LCSR_EDPAL), + ioread32be(bridge->base + TSI148_LCSR_EDPAT) ); printk(KERN_ERR "PCI-X attribute reg: %08x, PCI-X split completion reg: %08x\n", - ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPXA), - ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPXS) + ioread32be(bridge->base + TSI148_LCSR_EDPXA), + ioread32be(bridge->base + TSI148_LCSR_EDPXS) ); - iowrite32be(TSI148_LCSR_EDPAT_EDPCL, - tsi148_bridge->base + TSI148_LCSR_EDPAT); + iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); return TSI148_LCSR_INTC_PERRC; } @@ -194,16 +178,19 @@ static u32 tsi148_PERR_irqhandler(void) /* * Save address and status when VME error interrupt occurs. */ -static u32 tsi148_VERR_irqhandler(void) +static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge) { unsigned int error_addr_high, error_addr_low; unsigned long long error_addr; u32 error_attrib; struct vme_bus_error *error; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; - error_addr_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAU); - error_addr_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAL); - error_attrib = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAT); + error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU); + error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL); + error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT); reg_join(error_addr_high, error_addr_low, &error_addr); @@ -227,8 +214,7 @@ static u32 tsi148_VERR_irqhandler(void) } /* Clear Status */ - iowrite32be(TSI148_LCSR_VEAT_VESCL, - tsi148_bridge->base + TSI148_LCSR_VEAT); + iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT); return TSI148_LCSR_INTC_VERRC; } @@ -236,9 +222,9 @@ static u32 tsi148_VERR_irqhandler(void) /* * Wake up IACK queue. */ -static u32 tsi148_IACK_irqhandler(void) +static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge) { - wake_up(&iack_queue); + wake_up(&(bridge->iack_queue)); return TSI148_LCSR_INTC_IACKC; } @@ -246,9 +232,13 @@ static u32 tsi148_IACK_irqhandler(void) /* * Calling VME bus interrupt callback if provided. */ -static u32 tsi148_VIRQ_irqhandler(u32 stat) +static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge, + u32 stat) { int vec, i, serviced = 0; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; for (i = 7; i > 0; i--) { if (stat & (1 << i)) { @@ -258,8 +248,7 @@ static u32 tsi148_VIRQ_irqhandler(u32 stat) * 8-bit IACK cycles on the bus, read from offset * 3. */ - vec = ioread8(tsi148_bridge->base + - TSI148_LCSR_VIACK[i] + 3); + vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3); vme_irq_handler(tsi148_bridge, i, vec); @@ -274,13 +263,19 @@ static u32 tsi148_VIRQ_irqhandler(u32 stat) * Top level interrupt handler. Clears appropriate interrupt status bits and * then calls appropriate sub handler(s). */ -static irqreturn_t tsi148_irqhandler(int irq, void *dev_id) +static irqreturn_t tsi148_irqhandler(int irq, void *ptr) { u32 stat, enable, serviced = 0; + struct vme_bridge *tsi148_bridge; + struct tsi148_driver *bridge; + + tsi148_bridge = ptr; + + bridge = tsi148_bridge->driver_priv; /* Determine which interrupts are unmasked and set */ - enable = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO); - stat = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTS); + enable = ioread32be(bridge->base + TSI148_LCSR_INTEO); + stat = ioread32be(bridge->base + TSI148_LCSR_INTS); /* Only look at unmasked interrupts */ stat &= enable; @@ -292,61 +287,63 @@ static irqreturn_t tsi148_irqhandler(int irq, void *dev_id) /* Call subhandlers as appropriate */ /* DMA irqs */ if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S)) - serviced |= tsi148_DMA_irqhandler(stat); + serviced |= tsi148_DMA_irqhandler(bridge, stat); /* Location monitor irqs */ if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S)) - serviced |= tsi148_LM_irqhandler(stat); + serviced |= tsi148_LM_irqhandler(bridge, stat); /* Mail box irqs */ if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S | TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S)) - serviced |= tsi148_MB_irqhandler(stat); + serviced |= tsi148_MB_irqhandler(bridge, stat); /* PCI bus error */ if (stat & TSI148_LCSR_INTS_PERRS) - serviced |= tsi148_PERR_irqhandler(); + serviced |= tsi148_PERR_irqhandler(bridge); /* VME bus error */ if (stat & TSI148_LCSR_INTS_VERRS) - serviced |= tsi148_VERR_irqhandler(); + serviced |= tsi148_VERR_irqhandler(tsi148_bridge); /* IACK irq */ if (stat & TSI148_LCSR_INTS_IACKS) - serviced |= tsi148_IACK_irqhandler(); + serviced |= tsi148_IACK_irqhandler(bridge); /* VME bus irqs */ if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S | TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S | TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S | TSI148_LCSR_INTS_IRQ1S)) - serviced |= tsi148_VIRQ_irqhandler(stat); + serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat); /* Clear serviced interrupts */ - iowrite32be(serviced, tsi148_bridge->base + TSI148_LCSR_INTC); + iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC); return IRQ_HANDLED; } -static int tsi148_irq_init(struct vme_bridge *bridge) +static int tsi148_irq_init(struct vme_bridge *tsi148_bridge) { int result; unsigned int tmp; struct pci_dev *pdev; + struct tsi148_driver *bridge; + + pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev); - /* Need pdev */ - pdev = container_of(bridge->parent, struct pci_dev, dev); + bridge = tsi148_bridge->driver_priv; /* Initialise list for VME bus errors */ - INIT_LIST_HEAD(&(bridge->vme_errors)); + INIT_LIST_HEAD(&(tsi148_bridge->vme_errors)); - mutex_init(&(bridge->irq_mtx)); + mutex_init(&(tsi148_bridge->irq_mtx)); result = request_irq(pdev->irq, tsi148_irqhandler, IRQF_SHARED, - driver_name, pdev); + driver_name, tsi148_bridge); if (result) { dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n", pdev->irq); @@ -360,7 +357,7 @@ static int tsi148_irq_init(struct vme_bridge *bridge) TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO | TSI148_LCSR_INTEO_IACKEO; - /* XXX This leaves the following interrupts masked. + /* This leaves the following interrupts masked. * TSI148_LCSR_INTEO_VIEEO * TSI148_LCSR_INTEO_SYSFLEO * TSI148_LCSR_INTEO_ACFLEO @@ -393,14 +390,14 @@ static int tsi148_irq_init(struct vme_bridge *bridge) return 0; } -static void tsi148_irq_exit(struct pci_dev *pdev) +static void tsi148_irq_exit(struct tsi148_driver *bridge, struct pci_dev *pdev) { /* Turn off interrupts */ - iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEO); - iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEN); + iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO); + iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN); /* Clear all interrupts */ - iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_INTC); + iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC); /* Detach interrupt handler */ free_irq(pdev->irq, pdev); @@ -409,11 +406,11 @@ static void tsi148_irq_exit(struct pci_dev *pdev) /* * Check to see if an IACk has been received, return true (1) or false (0). */ -int tsi148_iack_received(void) +int tsi148_iack_received(struct tsi148_driver *bridge) { u32 tmp; - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR); + tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); if (tmp & TSI148_LCSR_VICR_IRQS) return 0; @@ -424,20 +421,24 @@ int tsi148_iack_received(void) /* * Configure VME interrupt */ -void tsi148_irq_set(int level, int state, int sync) +void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level, + int state, int sync) { struct pci_dev *pdev; u32 tmp; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; /* We need to do the ordering differently for enabling and disabling */ if (state == 0) { - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); if (sync != 0) { pdev = container_of(tsi148_bridge->parent, @@ -446,13 +447,13 @@ void tsi148_irq_set(int level, int state, int sync) synchronize_irq(pdev->irq); } } else { - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); } } @@ -460,28 +461,32 @@ void tsi148_irq_set(int level, int state, int sync) * Generate a VME bus interrupt at the requested level & vector. Wait for * interrupt to be acked. */ -int tsi148_irq_generate(int level, int statid) +int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level, int statid) { u32 tmp; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; - mutex_lock(&(vme_int)); + mutex_lock(&(bridge->vme_int)); /* Read VICR register */ - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR); + tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); /* Set Status/ID */ tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) | (statid & TSI148_LCSR_VICR_STID_M); - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VICR); + iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); /* Assert VMEbus IRQ */ tmp = tmp | TSI148_LCSR_VICR_IRQL[level]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VICR); + iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); /* XXX Consider implementing a timeout? */ - wait_event_interruptible(iack_queue, tsi148_iack_received()); + wait_event_interruptible(bridge->iack_queue, + tsi148_iack_received(bridge)); - mutex_unlock(&(vme_int)); + mutex_unlock(&(bridge->vme_int)); return 0; } @@ -489,8 +494,8 @@ int tsi148_irq_generate(int level, int statid) /* * Find the first error in this address range */ -static struct vme_bus_error *tsi148_find_error(vme_address_t aspace, - unsigned long long address, size_t count) +static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge, + vme_address_t aspace, unsigned long long address, size_t count) { struct list_head *err_pos; struct vme_bus_error *vme_err, *valid = NULL; @@ -521,8 +526,8 @@ static struct vme_bus_error *tsi148_find_error(vme_address_t aspace, /* * Clear errors in the provided address range. */ -static void tsi148_clear_errors(vme_address_t aspace, - unsigned long long address, size_t count) +static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge, + vme_address_t aspace, unsigned long long address, size_t count) { struct list_head *err_pos, *temp; struct vme_bus_error *vme_err; @@ -562,6 +567,9 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, unsigned int vme_bound_low, vme_bound_high; unsigned int pci_offset_low, pci_offset_high; unsigned long long vme_bound, pci_offset; + struct tsi148_driver *bridge; + + bridge = image->parent->driver_priv; #if 0 printk("Set slave image %d to:\n", image->number); @@ -634,24 +642,24 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, #endif /* Disable while we are mucking around */ - temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); temp_ctl &= ~TSI148_LCSR_ITAT_EN; - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); /* Setup mapping */ - iowrite32be(vme_base_high, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITSAU); - iowrite32be(vme_base_low, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITSAL); - iowrite32be(vme_bound_high, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITEAU); - iowrite32be(vme_bound_low, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITEAL); - iowrite32be(pci_offset_high, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITOFU); - iowrite32be(pci_offset_low, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITOFL); /* XXX Prefetch stuff currently unsupported */ @@ -713,13 +721,13 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, temp_ctl |= TSI148_LCSR_ITAT_DATA; /* Write ctl reg without enable */ - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); if (enabled) temp_ctl |= TSI148_LCSR_ITAT_EN; - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); return 0; @@ -739,25 +747,27 @@ int tsi148_slave_get(struct vme_slave_resource *image, int *enabled, unsigned int vme_bound_low, vme_bound_high; unsigned int pci_offset_low, pci_offset_high; unsigned long long vme_bound, pci_offset; + struct tsi148_driver *bridge; + bridge = image->parent->driver_priv; i = image->number; /* Read registers */ - ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); - vme_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITSAU); - vme_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITSAL); - vme_bound_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITEAU); - vme_bound_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITEAL); - pci_offset_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITOFU); - pci_offset_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] + + pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITOFL); /* Convert 64-bit variables to 2x 32-bit variables */ @@ -834,6 +844,9 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, unsigned long long existing_size; int retval = 0; struct pci_dev *pdev; + struct vme_bridge *tsi148_bridge; + + tsi148_bridge = image->parent; /* Find pci_dev container of dev */ if (tsi148_bridge->parent == NULL) { @@ -938,6 +951,9 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, unsigned int pci_bound_low, pci_bound_high; unsigned int vme_offset_low, vme_offset_high; unsigned long long pci_bound, vme_offset, pci_base; + struct tsi148_driver *bridge; + + bridge = image->parent->driver_priv; /* Verify input data */ if (vme_base & 0xFFFF) { @@ -1008,10 +1024,10 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, i = image->number; /* Disable while we are mucking around */ - temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); temp_ctl &= ~TSI148_LCSR_OTAT_EN; - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); /* XXX Prefetch stuff currently unsupported */ @@ -1127,33 +1143,33 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, temp_ctl |= TSI148_LCSR_OTAT_PGM; /* Setup mapping */ - iowrite32be(pci_base_high, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTSAU); - iowrite32be(pci_base_low, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTSAL); - iowrite32be(pci_bound_high, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTEAU); - iowrite32be(pci_bound_low, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTEAL); - iowrite32be(vme_offset_high, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTOFU); - iowrite32be(vme_offset_low, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTOFL); /* XXX We need to deal with OTBS */ #if 0 - iowrite32be(vmeOut->bcastSelect2esst, tsi148_bridge->base + + iowrite32be(vmeOut->bcastSelect2esst, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTBS); #endif /* Write ctl reg without enable */ - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); if (enabled) temp_ctl |= TSI148_LCSR_OTAT_EN; - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); spin_unlock(&(image->lock)); @@ -1184,23 +1200,26 @@ int __tsi148_master_get( struct vme_master_resource *image, int *enabled, unsigned int vme_offset_low, vme_offset_high; unsigned long long pci_base, pci_bound, vme_offset; + struct tsi148_driver *bridge; + + bridge = image->parent->driver_priv; i = image->number; - ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); - pci_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTSAU); - pci_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTSAL); - pci_bound_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTEAU); - pci_bound_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTEAL); - vme_offset_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTOFU); - vme_offset_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTOFL); /* Convert 64-bit variables to 2x 32-bit variables */ @@ -1306,6 +1325,9 @@ ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf, vme_cycle_t cycle; vme_width_t dwidth; struct vme_bus_error *vme_err = NULL; + struct vme_bridge *tsi148_bridge; + + tsi148_bridge = image->parent; spin_lock(&(image->lock)); @@ -1318,13 +1340,15 @@ ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf, __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle, &dwidth); - vme_err = tsi148_find_error(aspace, vme_base + offset, count); + vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset, + count); if(vme_err != NULL) { dev_err(image->parent->parent, "First VME read error detected " "an at address 0x%llx\n", vme_err->address); retval = vme_err->address - (vme_base + offset); /* Clear down save errors in this address range */ - tsi148_clear_errors(aspace, vme_base + offset, count); + tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset, + count); } skip_chk: @@ -1334,9 +1358,6 @@ skip_chk: } -/* XXX We need to change vme_master_resource->mtx to a spinlock so that read - * and write functions can be used in an interrupt context - */ ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf, size_t count, loff_t offset) { @@ -1347,6 +1368,12 @@ ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf, vme_width_t dwidth; struct vme_bus_error *vme_err = NULL; + struct vme_bridge *tsi148_bridge; + struct tsi148_driver *bridge; + + tsi148_bridge = image->parent; + + bridge = tsi148_bridge->driver_priv; spin_lock(&(image->lock)); @@ -1374,15 +1401,17 @@ ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf, __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle, &dwidth); - ioread16(flush_image->kern_base + 0x7F000); + ioread16(bridge->flush_image->kern_base + 0x7F000); - vme_err = tsi148_find_error(aspace, vme_base + offset, count); + vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset, + count); if(vme_err != NULL) { printk("First VME write error detected an at address 0x%llx\n", vme_err->address); retval = vme_err->address - (vme_base + offset); /* Clear down save errors in this address range */ - tsi148_clear_errors(aspace, vme_base + offset, count); + tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset, + count); } skip_chk: @@ -1404,48 +1433,50 @@ unsigned int tsi148_master_rmw(struct vme_master_resource *image, unsigned int pci_addr_high, pci_addr_low; u32 tmp, result; int i; + struct tsi148_driver *bridge; + bridge = image->parent->driver_priv; /* Find the PCI address that maps to the desired VME address */ i = image->number; /* Locking as we can only do one of these at a time */ - mutex_lock(&(vme_rmw)); + mutex_lock(&(bridge->vme_rmw)); /* Lock image */ spin_lock(&(image->lock)); - pci_addr_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTSAU); - pci_addr_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] + + pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTSAL); reg_join(pci_addr_high, pci_addr_low, &pci_addr); reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low); /* Configure registers */ - iowrite32be(mask, tsi148_bridge->base + TSI148_LCSR_RMWEN); - iowrite32be(compare, tsi148_bridge->base + TSI148_LCSR_RMWC); - iowrite32be(swap, tsi148_bridge->base + TSI148_LCSR_RMWS); - iowrite32be(pci_addr_high, tsi148_bridge->base + TSI148_LCSR_RMWAU); - iowrite32be(pci_addr_low, tsi148_bridge->base + TSI148_LCSR_RMWAL); + iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN); + iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC); + iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS); + iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU); + iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL); /* Enable RMW */ - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL); + tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); tmp |= TSI148_LCSR_VMCTRL_RMWEN; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VMCTRL); + iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); /* Kick process off with a read to the required address. */ result = ioread32be(image->kern_base + offset); /* Disable RMW */ - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL); + tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); tmp &= ~TSI148_LCSR_VMCTRL_RMWEN; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VMCTRL); + iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); spin_unlock(&(image->lock)); - mutex_unlock(&(vme_rmw)); + mutex_unlock(&(bridge->vme_rmw)); return result; } @@ -1789,11 +1820,14 @@ err_mem: /* * Check to see if the provided DMA channel is busy. */ -static int tsi148_dma_busy(int channel) +static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel) { u32 tmp; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] + + tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSTA); if (tmp & TSI148_LCSR_DSTA_BSY) @@ -1819,9 +1853,12 @@ int tsi148_dma_list_exec(struct vme_dma_list *list) #if 0 int x; #endif + struct tsi148_driver *bridge; ctrlr = list->parent; + bridge = ctrlr->parent->driver_priv; + mutex_lock(&(ctrlr->mtx)); channel = ctrlr->number; @@ -1891,21 +1928,22 @@ int tsi148_dma_list_exec(struct vme_dma_list *list) reg_split(bus_addr, &bus_addr_high, &bus_addr_low); - iowrite32be(bus_addr_high, tsi148_bridge->base + + iowrite32be(bus_addr_high, bridge->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU); - iowrite32be(bus_addr_low, tsi148_bridge->base + + iowrite32be(bus_addr_low, bridge->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL); /* Start the operation */ - iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, tsi148_bridge->base + + iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL); - wait_event_interruptible(dma_queue[channel], tsi148_dma_busy(channel)); + wait_event_interruptible(bridge->dma_queue[channel], + tsi148_dma_busy(ctrlr->parent, channel)); /* * Read status register, this register is valid until we kick off a * new transfer. */ - val = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] + + val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSTA); if (val & TSI148_LCSR_DSTA_VBE) { @@ -1953,12 +1991,15 @@ int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, { u32 lm_base_high, lm_base_low, lm_ctl = 0; int i; + struct tsi148_driver *bridge; + + bridge = lm->parent->driver_priv; mutex_lock(&(lm->mtx)); /* If we already have a callback attached, we can't move it! */ for (i = 0; i < lm->monitors; i++) { - if(lm_callback[i] != NULL) { + if (bridge->lm_callback[i] != NULL) { mutex_unlock(&(lm->mtx)); printk("Location monitor callback attached, can't " "reset\n"); @@ -1997,9 +2038,9 @@ int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, reg_split(lm_base, &lm_base_high, &lm_base_low); - iowrite32be(lm_base_high, tsi148_bridge->base + TSI148_LCSR_LMBAU); - iowrite32be(lm_base_low, tsi148_bridge->base + TSI148_LCSR_LMBAL); - iowrite32be(lm_ctl, tsi148_bridge->base + TSI148_LCSR_LMAT); + iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU); + iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL); + iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); mutex_unlock(&(lm->mtx)); @@ -2013,12 +2054,15 @@ int tsi148_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base, vme_address_t *aspace, vme_cycle_t *cycle) { u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0; + struct tsi148_driver *bridge; + + bridge = lm->parent->driver_priv; mutex_lock(&(lm->mtx)); - lm_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMBAU); - lm_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMBAL); - lm_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT); + lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU); + lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL); + lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); reg_join(lm_base_high, lm_base_low, lm_base); @@ -2061,11 +2105,14 @@ int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor, void (*callback)(int)) { u32 lm_ctl, tmp; + struct tsi148_driver *bridge; + + bridge = lm->parent->driver_priv; mutex_lock(&(lm->mtx)); /* Ensure that the location monitor is configured - need PGM or DATA */ - lm_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT); + lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) { mutex_unlock(&(lm->mtx)); printk("Location monitor not properly configured\n"); @@ -2073,28 +2120,28 @@ int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor, } /* Check that a callback isn't already attached */ - if (lm_callback[monitor] != NULL) { + if (bridge->lm_callback[monitor] != NULL) { mutex_unlock(&(lm->mtx)); printk("Existing callback attached\n"); return -EBUSY; } /* Attach callback */ - lm_callback[monitor] = callback; + bridge->lm_callback[monitor] = callback; /* Enable Location Monitor interrupt */ - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); tmp |= TSI148_LCSR_INTEN_LMEN[monitor]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); tmp |= TSI148_LCSR_INTEO_LMEO[monitor]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); /* Ensure that global Location Monitor Enable set */ if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) { lm_ctl |= TSI148_LCSR_LMAT_EN; - iowrite32be(lm_ctl, tsi148_bridge->base + TSI148_LCSR_LMAT); + iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); } mutex_unlock(&(lm->mtx)); @@ -2108,30 +2155,33 @@ int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor, int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor) { u32 lm_en, tmp; + struct tsi148_driver *bridge; + + bridge = lm->parent->driver_priv; mutex_lock(&(lm->mtx)); /* Disable Location Monitor and ensure previous interrupts are clear */ - lm_en = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN); + lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN); lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor]; - iowrite32be(lm_en, tsi148_bridge->base + TSI148_LCSR_INTEN); + iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN); - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO); + tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor]; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO); + iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); iowrite32be(TSI148_LCSR_INTC_LMC[monitor], - tsi148_bridge->base + TSI148_LCSR_INTC); + bridge->base + TSI148_LCSR_INTC); /* Detach callback */ - lm_callback[monitor] = NULL; + bridge->lm_callback[monitor] = NULL; /* If all location monitors disabled, disable global Location Monitor */ if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) { - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT); + tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT); tmp &= ~TSI148_LCSR_LMAT_EN; - iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_LMAT); + iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT); } mutex_unlock(&(lm->mtx)); @@ -2142,12 +2192,15 @@ int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor) /* * Determine Geographical Addressing */ -int tsi148_slot_get(void) +int tsi148_slot_get(struct vme_bridge *tsi148_bridge) { u32 slot = 0; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; if (!geoid) { - slot = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT); + slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT); slot = slot & TSI148_LCSR_VSTAT_GA_M; } else slot = geoid; @@ -2172,46 +2225,50 @@ static int __init tsi148_init(void) * boards registers, this means there is a fix length 508kB window which must * be mapped onto PCI memory. */ -static int tsi148_crcsr_init(struct pci_dev *pdev) +static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge, + struct pci_dev *pdev) { u32 cbar, crat, vstat; u32 crcsr_bus_high, crcsr_bus_low; int retval; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; /* Allocate mem for CR/CSR image */ - crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, - &crcsr_bus); - if (crcsr_kernel == NULL) { + bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, + &(bridge->crcsr_bus)); + if (bridge->crcsr_kernel == NULL) { dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR " "image\n"); return -ENOMEM; } - memset(crcsr_kernel, 0, VME_CRCSR_BUF_SIZE); + memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE); - reg_split(crcsr_bus, &crcsr_bus_high, &crcsr_bus_low); + reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low); - iowrite32be(crcsr_bus_high, tsi148_bridge->base + TSI148_LCSR_CROU); - iowrite32be(crcsr_bus_low, tsi148_bridge->base + TSI148_LCSR_CROL); + iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU); + iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL); /* Ensure that the CR/CSR is configured at the correct offset */ - cbar = ioread32be(tsi148_bridge->base + TSI148_CBAR); + cbar = ioread32be(bridge->base + TSI148_CBAR); cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3; - vstat = tsi148_slot_get(); + vstat = tsi148_slot_get(tsi148_bridge); if (cbar != vstat) { cbar = vstat; dev_info(&pdev->dev, "Setting CR/CSR offset\n"); - iowrite32be(cbar<<3, tsi148_bridge->base + TSI148_CBAR); + iowrite32be(cbar<<3, bridge->base + TSI148_CBAR); } dev_info(&pdev->dev, "CR/CSR Offset: %d\n", cbar); - crat = ioread32be(tsi148_bridge->base + TSI148_LCSR_CRAT); + crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); if (crat & TSI148_LCSR_CRAT_EN) { dev_info(&pdev->dev, "Enabling CR/CSR space\n"); iowrite32be(crat | TSI148_LCSR_CRAT_EN, - tsi148_bridge->base + TSI148_LCSR_CRAT); + bridge->base + TSI148_LCSR_CRAT); } else dev_info(&pdev->dev, "CR/CSR already enabled\n"); @@ -2220,8 +2277,9 @@ static int tsi148_crcsr_init(struct pci_dev *pdev) * through VME writes. */ if(err_chk) { - retval = tsi148_master_set(flush_image, 1, (vstat * 0x80000), - 0x80000, VME_CRCSR, VME_SCT, VME_D16); + retval = tsi148_master_set(bridge->flush_image, 1, + (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT, + VME_D16); if (retval) dev_err(&pdev->dev, "Configuring flush image failed\n"); } @@ -2230,20 +2288,25 @@ static int tsi148_crcsr_init(struct pci_dev *pdev) } -static void tsi148_crcsr_exit(struct pci_dev *pdev) +static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge, + struct pci_dev *pdev) { u32 crat; + struct tsi148_driver *bridge; + + bridge = tsi148_bridge->driver_priv; /* Turn off CR/CSR space */ - crat = ioread32be(tsi148_bridge->base + TSI148_LCSR_CRAT); + crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); iowrite32be(crat & ~TSI148_LCSR_CRAT_EN, - tsi148_bridge->base + TSI148_LCSR_CRAT); + bridge->base + TSI148_LCSR_CRAT); /* Free image */ - iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CROU); - iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CROL); + iowrite32be(0, bridge->base + TSI148_LCSR_CROU); + iowrite32be(0, bridge->base + TSI148_LCSR_CROL); - pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, crcsr_kernel, crcsr_bus); + pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, + bridge->crcsr_bus); } static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) @@ -2251,6 +2314,8 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) int retval, i, master_num; u32 data; struct list_head *pos = NULL; + struct vme_bridge *tsi148_bridge; + struct tsi148_driver *tsi148_device; struct vme_master_resource *master_image; struct vme_slave_resource *slave_image; struct vme_dma_resource *dma_ctrlr; @@ -2270,6 +2335,18 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) memset(tsi148_bridge, 0, sizeof(struct vme_bridge)); + tsi148_device = kmalloc(sizeof(struct tsi148_driver), GFP_KERNEL); + if (tsi148_device == NULL) { + dev_err(&pdev->dev, "Failed to allocate memory for device " + "structure\n"); + retval = -ENOMEM; + goto err_driver; + } + + memset(tsi148_device, 0, sizeof(struct tsi148_driver)); + + tsi148_bridge->driver_priv = tsi148_device; + /* Enable the device */ retval = pci_enable_device(pdev); if (retval) { @@ -2285,15 +2362,16 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) } /* map registers in BAR 0 */ - tsi148_bridge->base = ioremap_nocache(pci_resource_start(pdev, 0), 4096); - if (!tsi148_bridge->base) { + tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0), + 4096); + if (!tsi148_device->base) { dev_err(&pdev->dev, "Unable to remap CRG region\n"); retval = -EIO; goto err_remap; } /* Check to see if the mapping worked out */ - data = ioread32(tsi148_bridge->base + TSI148_PCFS_ID) & 0x0000FFFF; + data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF; if (data != PCI_VENDOR_ID_TUNDRA) { dev_err(&pdev->dev, "CRG region check failed\n"); retval = -EIO; @@ -2301,12 +2379,11 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) } /* Initialize wait queues & mutual exclusion flags */ - /* XXX These need to be moved to the vme_bridge structure */ - init_waitqueue_head(&dma_queue[0]); - init_waitqueue_head(&dma_queue[1]); - init_waitqueue_head(&iack_queue); - mutex_init(&(vme_int)); - mutex_init(&(vme_rmw)); + init_waitqueue_head(&(tsi148_device->dma_queue[0])); + init_waitqueue_head(&(tsi148_device->dma_queue[1])); + init_waitqueue_head(&(tsi148_device->iack_queue)); + mutex_init(&(tsi148_device->vme_int)); + mutex_init(&(tsi148_device->vme_rmw)); tsi148_bridge->parent = &(pdev->dev); strcpy(tsi148_bridge->name, driver_name); @@ -2326,29 +2403,29 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) master_num = TSI148_MAX_MASTER; if(err_chk){ master_num--; - /* XXX */ - flush_image = (struct vme_master_resource *)kmalloc( - sizeof(struct vme_master_resource), GFP_KERNEL); - if (flush_image == NULL) { + + tsi148_device->flush_image = (struct vme_master_resource *) + kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL); + if (tsi148_device->flush_image == NULL) { dev_err(&pdev->dev, "Failed to allocate memory for " "flush resource structure\n"); retval = -ENOMEM; goto err_master; } - flush_image->parent = tsi148_bridge; - spin_lock_init(&(flush_image->lock)); - flush_image->locked = 1; - flush_image->number = master_num; - flush_image->address_attr = VME_A16 | VME_A24 | VME_A32 | - VME_A64; - flush_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | - VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 | - VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER | - VME_PROG | VME_DATA; - flush_image->width_attr = VME_D16 | VME_D32; - memset(&(flush_image->pci_resource), 0, + tsi148_device->flush_image->parent = tsi148_bridge; + spin_lock_init(&(tsi148_device->flush_image->lock)); + tsi148_device->flush_image->locked = 1; + tsi148_device->flush_image->number = master_num; + tsi148_device->flush_image->address_attr = VME_A16 | VME_A24 | + VME_A32 | VME_A64; + tsi148_device->flush_image->cycle_attr = VME_SCT | VME_BLT | + VME_MBLT | VME_2eVME | VME_2eSST | VME_2eSSTB | + VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER | + VME_USER | VME_PROG | VME_DATA; + tsi148_device->flush_image->width_attr = VME_D16 | VME_D32; + memset(&(tsi148_device->flush_image->pci_resource), 0, sizeof(struct resource)); - flush_image->kern_base = NULL; + tsi148_device->flush_image->kern_base = NULL; } /* Add master windows to list */ @@ -2465,45 +2542,42 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) tsi148_bridge->lm_detach = tsi148_lm_detach; tsi148_bridge->slot_get = tsi148_slot_get; - data = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT); + data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); dev_info(&pdev->dev, "Board is%s the VME system controller\n", (data & TSI148_LCSR_VSTAT_SCONS)? "" : " not"); - if (!geoid) { + if (!geoid) dev_info(&pdev->dev, "VME geographical address is %d\n", data & TSI148_LCSR_VSTAT_GA_M); - } else { + else dev_info(&pdev->dev, "VME geographical address is set to %d\n", geoid); - } + dev_info(&pdev->dev, "VME Write and flush and error check is %s\n", err_chk ? "enabled" : "disabled"); - if(tsi148_crcsr_init(pdev)) { + if (tsi148_crcsr_init(tsi148_bridge, pdev)) dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); goto err_crcsr; - } - - /* Need to save tsi148_bridge pointer locally in link list for use in - * tsi148_remove() - */ retval = vme_register_bridge(tsi148_bridge); if (retval != 0) { dev_err(&pdev->dev, "Chip Registration failed.\n"); goto err_reg; } + pci_set_drvdata(pdev, tsi148_bridge); + /* Clear VME bus "board fail", and "power-up reset" lines */ - data = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT); + data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); data &= ~TSI148_LCSR_VSTAT_BRDFL; data |= TSI148_LCSR_VSTAT_CPURST; - iowrite32be(data, tsi148_bridge->base + TSI148_LCSR_VSTAT); + iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT); return 0; vme_unregister_bridge(tsi148_bridge); err_reg: - tsi148_crcsr_exit(pdev); + tsi148_crcsr_exit(tsi148_bridge, pdev); err_crcsr: err_lm: /* resources are stored in link list */ @@ -2534,15 +2608,17 @@ err_master: kfree(master_image); } - tsi148_irq_exit(pdev); + tsi148_irq_exit(tsi148_device, pdev); err_irq: err_test: - iounmap(tsi148_bridge->base); + iounmap(tsi148_device->base); err_remap: pci_release_regions(pdev); err_resource: pci_disable_device(pdev); err_enable: + kfree(tsi148_device); +err_driver: kfree(tsi148_bridge); err_struct: return retval; @@ -2556,56 +2632,58 @@ static void tsi148_remove(struct pci_dev *pdev) struct vme_slave_resource *slave_image; struct vme_dma_resource *dma_ctrlr; int i; + struct tsi148_driver *bridge; + struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev); + + bridge = tsi148_bridge->driver_priv; - dev_dbg(&pdev->dev, "Driver is being unloaded.\n"); - /* XXX We need to find the pdev->dev in the list of vme_bridge->dev's */ + dev_dbg(&pdev->dev, "Driver is being unloaded.\n"); /* * Shutdown all inbound and outbound windows. */ for (i = 0; i < 8; i++) { - iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_IT[i] + + iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); - iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_OT[i] + + iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); } /* * Shutdown Location monitor. */ - iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_LMAT); + iowrite32be(0, bridge->base + TSI148_LCSR_LMAT); /* * Shutdown CRG map. */ - iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CSRAT); + iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT); /* * Clear error status. */ - iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_EDPAT); - iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_VEAT); - iowrite32be(0x07000700, tsi148_bridge->base + TSI148_LCSR_PSTAT); + iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT); + iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT); + iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT); /* * Remove VIRQ interrupt (if any) */ - if (ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR) & 0x800) { - iowrite32be(0x8000, tsi148_bridge->base + TSI148_LCSR_VICR); - } + if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800) + iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR); /* * Map all Interrupts to PCI INTA */ - iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTM1); - iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTM2); + iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1); + iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2); - tsi148_irq_exit(pdev); + tsi148_irq_exit(bridge, pdev); vme_unregister_bridge(tsi148_bridge); - tsi148_crcsr_exit(pdev); + tsi148_crcsr_exit(tsi148_bridge, pdev); /* resources are stored in link list */ list_for_each(pos, &(tsi148_bridge->dma_resources)) { @@ -2629,14 +2707,16 @@ static void tsi148_remove(struct pci_dev *pdev) kfree(master_image); } - tsi148_irq_exit(pdev); + tsi148_irq_exit(bridge, pdev); - iounmap(tsi148_bridge->base); + iounmap(bridge->base); pci_release_regions(pdev); pci_disable_device(pdev); + kfree(tsi148_bridge->driver_priv); + kfree(tsi148_bridge); } @@ -2724,29 +2804,29 @@ int tsi148_dma_run(struct vme_dma_resource *resource, struct vme_dma_attr src, } /* Program registers for DMA transfer */ - iowrite32be(dmaLL->dsau, tsi148_bridge->base + + iowrite32be(dmaLL->dsau, tsi148_bridge->driver_priv->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAU); - iowrite32be(dmaLL->dsal, tsi148_bridge->base + + iowrite32be(dmaLL->dsal, tsi148_bridge->driver_priv->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAL); - iowrite32be(dmaLL->ddau, tsi148_bridge->base + + iowrite32be(dmaLL->ddau, tsi148_bridge->driver_priv->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAU); - iowrite32be(dmaLL->ddal, tsi148_bridge->base + + iowrite32be(dmaLL->ddal, tsi148_bridge->driver_priv->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAL); - iowrite32be(dmaLL->dsat, tsi148_bridge->base + + iowrite32be(dmaLL->dsat, tsi148_bridge->driver_priv->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAT); - iowrite32be(dmaLL->ddat, tsi148_bridge->base + + iowrite32be(dmaLL->ddat, tsi148_bridge->driver_priv->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAT); - iowrite32be(dmaLL->dcnt, tsi148_bridge->base + + iowrite32be(dmaLL->dcnt, tsi148_bridge->driver_priv->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCNT); - iowrite32be(dmaLL->ddbs, tsi148_bridge->base + + iowrite32be(dmaLL->ddbs, tsi148_bridge->driver_priv->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDBS); /* Start the operation */ - iowrite32be(dctlreg | 0x2000000, tsi148_bridge->base + + iowrite32be(dctlreg | 0x2000000, tsi148_bridge->driver_priv->base + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL); - tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] + - TSI148_LCSR_OFFSET_DSTA); + tmp = ioread32be(tsi148_bridge->driver_priv->base + + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSTA); wait_event_interruptible(dma_queue[channel], (tmp & 0x1000000) == 0); /* @@ -2754,8 +2834,8 @@ int tsi148_dma_run(struct vme_dma_resource *resource, struct vme_dma_attr src, * handler rather than here so that we can be sure we haven't kicked off * another DMA transfer. */ - val = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] + - TSI148_LCSR_OFFSET_DSTA); + val = ioread32be(tsi148_bridge->driver_priv->base + + TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSTA); vmeDma->vmeDmaStatus = 0; if (val & 0x10000000) { @@ -2782,7 +2862,8 @@ int tempe_set_arbiter(vmeArbiterCfg_t * vmeArb) int temp_ctl = 0; int gto = 0; - temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VCTRL); + temp_ctl = ioread32be(tsi148_bridge->driver_priv->base + + TSI148_LCSR_VCTRL); temp_ctl &= 0xFFEFFF00; if (vmeArb->globalTimeoutTimer == 0xFFFFFFFF) { @@ -2810,7 +2891,8 @@ int tempe_set_arbiter(vmeArbiterCfg_t * vmeArb) if (vmeArb->noEarlyReleaseFlag) { temp_ctl |= 1 << 20; } - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_VCTRL); + iowrite32be(temp_ctl, tsi148_bridge->driver_priv->base + + TSI148_LCSR_VCTRL); return (0); } @@ -2824,7 +2906,8 @@ int tempe_get_arbiter(vmeArbiterCfg_t * vmeArb) int gto = 0; - temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VCTRL); + temp_ctl = ioread32be(tsi148_bridge->driver_priv->base + + TSI148_LCSR_VCTRL); gto = temp_ctl & 0xF; if (gto != 0) { @@ -2855,7 +2938,8 @@ int tempe_set_requestor(vmeRequesterCfg_t * vmeReq) { int temp_ctl = 0; - temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL); + temp_ctl = ioread32be(tsi148_bridge->driver_priv->base + + TSI148_LCSR_VMCTRL); temp_ctl &= 0xFFFF0000; if (vmeReq->releaseMode == 1) { @@ -2870,7 +2954,8 @@ int tempe_set_requestor(vmeRequesterCfg_t * vmeReq) temp_ctl |= (vmeReq->timeoffTimeoutTimer & 7) << 12; temp_ctl |= vmeReq->requestLevel; - iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_VMCTRL); + iowrite32be(temp_ctl, tsi148_bridge->driver_priv->base + + TSI148_LCSR_VMCTRL); return (0); } @@ -2881,7 +2966,8 @@ int tempe_get_requestor(vmeRequesterCfg_t * vmeReq) { int temp_ctl = 0; - temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL); + temp_ctl = ioread32be(tsi148_bridge->driver_priv->base + + TSI148_LCSR_VMCTRL); if (temp_ctl & 0x18) { vmeReq->releaseMode = 1; diff --git a/drivers/staging/vme/bridges/vme_tsi148.h b/drivers/staging/vme/bridges/vme_tsi148.h index 6f0f705ce6be..9e5f7fa1d744 100644 --- a/drivers/staging/vme/bridges/vme_tsi148.h +++ b/drivers/staging/vme/bridges/vme_tsi148.h @@ -33,6 +33,22 @@ #define TSI148_MAX_MAILBOX 4 /* Max Mail Box registers */ #define TSI148_MAX_SEMAPHORE 8 /* Max Semaphores */ +/* Structure used to hold driver specific information */ +struct tsi148_driver { + void *base; /* Base Address of device registers */ + wait_queue_head_t dma_queue[2]; + wait_queue_head_t iack_queue; + void (*lm_callback[4])(int); /* Called in interrupt handler */ + void *crcsr_kernel; + dma_addr_t crcsr_bus; + struct vme_master_resource *flush_image; + struct mutex vme_rmw; /* Only one RMW cycle at a time */ + struct mutex vme_int; /* + * Only one VME interrupt can be + * generated at a time, provide locking + */ +}; + /* * Layout of a DMAC Linked-List Descriptor * diff --git a/drivers/staging/vme/vme.c b/drivers/staging/vme/vme.c index 79c501dac5f9..ea2eee3f0834 100644 --- a/drivers/staging/vme/vme.c +++ b/drivers/staging/vme/vme.c @@ -993,7 +993,7 @@ void vme_irq_handler(struct vme_bridge *bridge, int level, int statid) EXPORT_SYMBOL(vme_irq_handler); int vme_irq_request(struct device *dev, int level, int statid, - void (*callback)(int level, int vector, void *priv_data), + void (*callback)(int, int, void *), void *priv_data) { struct vme_bridge *bridge; @@ -1027,7 +1027,7 @@ int vme_irq_request(struct device *dev, int level, int statid, bridge->irq[level - 1].callback[statid].func = callback; /* Enable IRQ level */ - bridge->irq_set(level, 1, 1); + bridge->irq_set(bridge, level, 1, 1); mutex_unlock(&(bridge->irq_mtx)); @@ -1061,7 +1061,7 @@ void vme_irq_free(struct device *dev, int level, int statid) /* Disable IRQ level if no more interrupts attached at this level*/ if (bridge->irq[level - 1].count == 0) - bridge->irq_set(level, 0, 1); + bridge->irq_set(bridge, level, 0, 1); bridge->irq[level - 1].callback[statid].func = NULL; bridge->irq[level - 1].callback[statid].priv_data = NULL; @@ -1090,7 +1090,7 @@ int vme_irq_generate(struct device *dev, int level, int statid) return -EINVAL; } - return bridge->irq_generate(level, statid); + return bridge->irq_generate(bridge, level, statid); } EXPORT_SYMBOL(vme_irq_generate); @@ -1303,7 +1303,7 @@ int vme_slot_get(struct device *bus) return -EINVAL; } - return bridge->slot_get(); + return bridge->slot_get(bridge); } EXPORT_SYMBOL(vme_slot_get); diff --git a/drivers/staging/vme/vme_bridge.h b/drivers/staging/vme/vme_bridge.h index f8ead21c94fb..6dc472f613e2 100644 --- a/drivers/staging/vme/vme_bridge.h +++ b/drivers/staging/vme/vme_bridge.h @@ -113,7 +113,7 @@ struct vme_bridge { /* Bridge Info - XXX Move to private structure? */ struct device *parent; /* Generic device struct (pdev->dev for PCI) */ - void *base; /* Base Address of device registers */ + void *driver_priv; /* Private pointer for the bridge driver */ struct device dev[VME_SLOTS_MAX]; /* Device registered with * device model on VME bus @@ -152,8 +152,8 @@ struct vme_bridge { int (*dma_list_empty) (struct vme_dma_list *); /* Interrupt Functions */ - void (*irq_set) (int, int, int); - int (*irq_generate) (int, int); + void (*irq_set) (struct vme_bridge *, int, int, int); + int (*irq_generate) (struct vme_bridge *, int, int); /* Location monitor functions */ int (*lm_set) (struct vme_lm_resource *, unsigned long long, @@ -164,7 +164,7 @@ struct vme_bridge { int (*lm_detach) (struct vme_lm_resource *, int); /* CR/CSR space functions */ - int (*slot_get) (void); + int (*slot_get) (struct vme_bridge *); /* Use standard master read and write functions to access CR/CSR */ #if 0 -- cgit v1.2.3 From 8fafb47638012d93134d0ff38adcc5fc661beeb1 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Thu, 18 Feb 2010 15:13:12 +0000 Subject: Staging: vme: Make vme_master_resource naming bus neutral The vme_master_resource structure contains an item called "pci_resource". Rename to make bus agnostic. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/TODO | 1 - drivers/staging/vme/bridges/vme_ca91cx42.c | 48 ++++++++++++++-------------- drivers/staging/vme/bridges/vme_tsi148.c | 50 +++++++++++++++--------------- drivers/staging/vme/vme_bridge.h | 2 +- 4 files changed, 50 insertions(+), 51 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/TODO b/drivers/staging/vme/TODO index 83d44cbf9a5f..00c0ddcfe2a0 100644 --- a/drivers/staging/vme/TODO +++ b/drivers/staging/vme/TODO @@ -37,7 +37,6 @@ chips. They are currently not supported at all by the API. Core ==== -- Rename vme_master_resource's "pci_resource" to be bus agnostic. - Improve generic sanity checks (Such as does an offset and size fit within a window and parameter checking). diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index c2f86a6996d5..ae2f69cd9d23 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c @@ -526,8 +526,8 @@ static int ca91cx42_alloc_resource(struct vme_master_resource *image, } pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev); - existing_size = (unsigned long long)(image->pci_resource.end - - image->pci_resource.start); + existing_size = (unsigned long long)(image->bus_resource.end - + image->bus_resource.start); /* If the existing size is OK, return */ if (existing_size == (size - 1)) @@ -536,15 +536,15 @@ static int ca91cx42_alloc_resource(struct vme_master_resource *image, if (existing_size != 0) { iounmap(image->kern_base); image->kern_base = NULL; - if (image->pci_resource.name != NULL) - kfree(image->pci_resource.name); - release_resource(&(image->pci_resource)); - memset(&(image->pci_resource), 0, sizeof(struct resource)); + if (image->bus_resource.name != NULL) + kfree(image->bus_resource.name); + release_resource(&(image->bus_resource)); + memset(&(image->bus_resource), 0, sizeof(struct resource)); } - if (image->pci_resource.name == NULL) { - image->pci_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL); - if (image->pci_resource.name == NULL) { + if (image->bus_resource.name == NULL) { + image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL); + if (image->bus_resource.name == NULL) { printk(KERN_ERR "Unable to allocate memory for resource" " name\n"); retval = -ENOMEM; @@ -552,26 +552,26 @@ static int ca91cx42_alloc_resource(struct vme_master_resource *image, } } - sprintf((char *)image->pci_resource.name, "%s.%d", + sprintf((char *)image->bus_resource.name, "%s.%d", ca91cx42_bridge->name, image->number); - image->pci_resource.start = 0; - image->pci_resource.end = (unsigned long)size; - image->pci_resource.flags = IORESOURCE_MEM; + image->bus_resource.start = 0; + image->bus_resource.end = (unsigned long)size; + image->bus_resource.flags = IORESOURCE_MEM; retval = pci_bus_alloc_resource(pdev->bus, - &(image->pci_resource), size, size, PCIBIOS_MIN_MEM, + &(image->bus_resource), size, size, PCIBIOS_MIN_MEM, 0, NULL, NULL); if (retval) { printk(KERN_ERR "Failed to allocate mem resource for " "window %d size 0x%lx start 0x%lx\n", image->number, (unsigned long)size, - (unsigned long)image->pci_resource.start); + (unsigned long)image->bus_resource.start); goto err_resource; } image->kern_base = ioremap_nocache( - image->pci_resource.start, size); + image->bus_resource.start, size); if (image->kern_base == NULL) { printk(KERN_ERR "Failed to remap resource\n"); retval = -ENOMEM; @@ -583,10 +583,10 @@ static int ca91cx42_alloc_resource(struct vme_master_resource *image, iounmap(image->kern_base); image->kern_base = NULL; err_remap: - release_resource(&(image->pci_resource)); + release_resource(&(image->bus_resource)); err_resource: - kfree(image->pci_resource.name); - memset(&(image->pci_resource), 0, sizeof(struct resource)); + kfree(image->bus_resource.name); + memset(&(image->bus_resource), 0, sizeof(struct resource)); err_name: return retval; } @@ -598,9 +598,9 @@ static void ca91cx42_free_resource(struct vme_master_resource *image) { iounmap(image->kern_base); image->kern_base = NULL; - release_resource(&(image->pci_resource)); - kfree(image->pci_resource.name); - memset(&(image->pci_resource), 0, sizeof(struct resource)); + release_resource(&(image->bus_resource)); + kfree(image->bus_resource.name); + memset(&(image->bus_resource), 0, sizeof(struct resource)); } @@ -646,7 +646,7 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, goto err_res; } - pci_base = (unsigned long long)image->pci_resource.start; + pci_base = (unsigned long long)image->bus_resource.start; /* * Bound address is a valid address for the window, adjust @@ -1102,7 +1102,7 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | VME_SUPER | VME_USER | VME_PROG | VME_DATA; master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64; - memset(&(master_image->pci_resource), 0, + memset(&(master_image->bus_resource), 0, sizeof(struct resource)); master_image->kern_base = NULL; list_add_tail(&(master_image->list), diff --git a/drivers/staging/vme/bridges/vme_tsi148.c b/drivers/staging/vme/bridges/vme_tsi148.c index e3d300c9bfba..a6f853a3dc24 100644 --- a/drivers/staging/vme/bridges/vme_tsi148.c +++ b/drivers/staging/vme/bridges/vme_tsi148.c @@ -855,8 +855,8 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, } pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev); - existing_size = (unsigned long long)(image->pci_resource.end - - image->pci_resource.start); + existing_size = (unsigned long long)(image->bus_resource.end - + image->bus_resource.start); /* If the existing size is OK, return */ if ((size != 0) && (existing_size == (size - 1))) @@ -865,10 +865,10 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, if (existing_size != 0) { iounmap(image->kern_base); image->kern_base = NULL; - if (image->pci_resource.name != NULL) - kfree(image->pci_resource.name); - release_resource(&(image->pci_resource)); - memset(&(image->pci_resource), 0, sizeof(struct resource)); + if (image->bus_resource.name != NULL) + kfree(image->bus_resource.name); + release_resource(&(image->bus_resource)); + memset(&(image->bus_resource), 0, sizeof(struct resource)); } /* Exit here if size is zero */ @@ -876,9 +876,9 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, return 0; } - if (image->pci_resource.name == NULL) { - image->pci_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL); - if (image->pci_resource.name == NULL) { + if (image->bus_resource.name == NULL) { + image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL); + if (image->bus_resource.name == NULL) { printk(KERN_ERR "Unable to allocate memory for resource" " name\n"); retval = -ENOMEM; @@ -886,26 +886,26 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, } } - sprintf((char *)image->pci_resource.name, "%s.%d", tsi148_bridge->name, + sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name, image->number); - image->pci_resource.start = 0; - image->pci_resource.end = (unsigned long)size; - image->pci_resource.flags = IORESOURCE_MEM; + image->bus_resource.start = 0; + image->bus_resource.end = (unsigned long)size; + image->bus_resource.flags = IORESOURCE_MEM; retval = pci_bus_alloc_resource(pdev->bus, - &(image->pci_resource), size, size, PCIBIOS_MIN_MEM, + &(image->bus_resource), size, size, PCIBIOS_MIN_MEM, 0, NULL, NULL); if (retval) { printk(KERN_ERR "Failed to allocate mem resource for " "window %d size 0x%lx start 0x%lx\n", image->number, (unsigned long)size, - (unsigned long)image->pci_resource.start); + (unsigned long)image->bus_resource.start); goto err_resource; } image->kern_base = ioremap_nocache( - image->pci_resource.start, size); + image->bus_resource.start, size); if (image->kern_base == NULL) { printk(KERN_ERR "Failed to remap resource\n"); retval = -ENOMEM; @@ -917,10 +917,10 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, iounmap(image->kern_base); image->kern_base = NULL; err_remap: - release_resource(&(image->pci_resource)); + release_resource(&(image->bus_resource)); err_resource: - kfree(image->pci_resource.name); - memset(&(image->pci_resource), 0, sizeof(struct resource)); + kfree(image->bus_resource.name); + memset(&(image->bus_resource), 0, sizeof(struct resource)); err_name: return retval; } @@ -932,9 +932,9 @@ static void tsi148_free_resource(struct vme_master_resource *image) { iounmap(image->kern_base); image->kern_base = NULL; - release_resource(&(image->pci_resource)); - kfree(image->pci_resource.name); - memset(&(image->pci_resource), 0, sizeof(struct resource)); + release_resource(&(image->bus_resource)); + kfree(image->bus_resource.name); + memset(&(image->bus_resource), 0, sizeof(struct resource)); } /* @@ -987,7 +987,7 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, pci_bound = 0; vme_offset = 0; } else { - pci_base = (unsigned long long)image->pci_resource.start; + pci_base = (unsigned long long)image->bus_resource.start; /* * Bound address is a valid address for the window, adjust @@ -2423,7 +2423,7 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER | VME_PROG | VME_DATA; tsi148_device->flush_image->width_attr = VME_D16 | VME_D32; - memset(&(tsi148_device->flush_image->pci_resource), 0, + memset(&(tsi148_device->flush_image->bus_resource), 0, sizeof(struct resource)); tsi148_device->flush_image->kern_base = NULL; } @@ -2450,7 +2450,7 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER | VME_PROG | VME_DATA; master_image->width_attr = VME_D16 | VME_D32; - memset(&(master_image->pci_resource), 0, + memset(&(master_image->bus_resource), 0, sizeof(struct resource)); master_image->kern_base = NULL; list_add_tail(&(master_image->list), diff --git a/drivers/staging/vme/vme_bridge.h b/drivers/staging/vme/vme_bridge.h index 6dc472f613e2..a2cfc1014726 100644 --- a/drivers/staging/vme/vme_bridge.h +++ b/drivers/staging/vme/vme_bridge.h @@ -19,7 +19,7 @@ struct vme_master_resource { vme_address_t address_attr; vme_cycle_t cycle_attr; vme_width_t width_attr; - struct resource pci_resource; /* XXX Rename to be bus agnostic */ + struct resource bus_resource; void *kern_base; }; -- cgit v1.2.3 From 2b82beb8c1bc81b3dde69d16cacbc22546681acf Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Thu, 18 Feb 2010 15:13:19 +0000 Subject: Staging: vme: Add location monitor support for ca91cx42 Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/TODO | 1 - drivers/staging/vme/bridges/vme_ca91cx42.c | 272 +++++++++++++++++++++-------- drivers/staging/vme/bridges/vme_ca91cx42.h | 13 ++ 3 files changed, 213 insertions(+), 73 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/TODO b/drivers/staging/vme/TODO index 00c0ddcfe2a0..723b67b08b91 100644 --- a/drivers/staging/vme/TODO +++ b/drivers/staging/vme/TODO @@ -58,7 +58,6 @@ Universe II (ca91c142) - DMA unsupported. - RMW transactions unsupported. -- Location Monitors unsupported. - Mailboxes unsupported. - Error Detection. - Control of prefetch size, threshold. diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index ae2f69cd9d23..aeb11d5f919f 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c @@ -899,6 +899,206 @@ ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf, return retval; } +/* + * All 4 location monitors reside at the same base - this is therefore a + * system wide configuration. + * + * This does not enable the LM monitor - that should be done when the first + * callback is attached and disabled when the last callback is removed. + */ +int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, + vme_address_t aspace, vme_cycle_t cycle) +{ + u32 temp_base, lm_ctl = 0; + int i; + struct ca91cx42_driver *bridge; + struct device *dev; + + bridge = lm->parent->driver_priv; + dev = lm->parent->parent; + + /* Check the alignment of the location monitor */ + temp_base = (u32)lm_base; + if (temp_base & 0xffff) { + dev_err(dev, "Location monitor must be aligned to 64KB " + "boundary"); + return -EINVAL; + } + + mutex_lock(&(lm->mtx)); + + /* If we already have a callback attached, we can't move it! */ + for (i = 0; i < lm->monitors; i++) { + if (bridge->lm_callback[i] != NULL) { + mutex_unlock(&(lm->mtx)); + dev_err(dev, "Location monitor callback attached, " + "can't reset\n"); + return -EBUSY; + } + } + + switch (aspace) { + case VME_A16: + lm_ctl |= CA91CX42_LM_CTL_AS_A16; + break; + case VME_A24: + lm_ctl |= CA91CX42_LM_CTL_AS_A24; + break; + case VME_A32: + lm_ctl |= CA91CX42_LM_CTL_AS_A32; + break; + default: + mutex_unlock(&(lm->mtx)); + dev_err(dev, "Invalid address space\n"); + return -EINVAL; + break; + } + + if (cycle & VME_SUPER) + lm_ctl |= CA91CX42_LM_CTL_SUPR; + if (cycle & VME_USER) + lm_ctl |= CA91CX42_LM_CTL_NPRIV; + if (cycle & VME_PROG) + lm_ctl |= CA91CX42_LM_CTL_PGM; + if (cycle & VME_DATA) + lm_ctl |= CA91CX42_LM_CTL_DATA; + + iowrite32(lm_base, bridge->base + LM_BS); + iowrite32(lm_ctl, bridge->base + LM_CTL); + + mutex_unlock(&(lm->mtx)); + + return 0; +} + +/* Get configuration of the callback monitor and return whether it is enabled + * or disabled. + */ +int ca91cx42_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base, + vme_address_t *aspace, vme_cycle_t *cycle) +{ + u32 lm_ctl, enabled = 0; + struct ca91cx42_driver *bridge; + + bridge = lm->parent->driver_priv; + + mutex_lock(&(lm->mtx)); + + *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS); + lm_ctl = ioread32(bridge->base + LM_CTL); + + if (lm_ctl & CA91CX42_LM_CTL_EN) + enabled = 1; + + if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16) + *aspace = VME_A16; + if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24) + *aspace = VME_A24; + if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32) + *aspace = VME_A32; + + *cycle = 0; + if (lm_ctl & CA91CX42_LM_CTL_SUPR) + *cycle |= VME_SUPER; + if (lm_ctl & CA91CX42_LM_CTL_NPRIV) + *cycle |= VME_USER; + if (lm_ctl & CA91CX42_LM_CTL_PGM) + *cycle |= VME_PROG; + if (lm_ctl & CA91CX42_LM_CTL_DATA) + *cycle |= VME_DATA; + + mutex_unlock(&(lm->mtx)); + + return enabled; +} + +/* + * Attach a callback to a specific location monitor. + * + * Callback will be passed the monitor triggered. + */ +int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor, + void (*callback)(int)) +{ + u32 lm_ctl, tmp; + struct ca91cx42_driver *bridge; + struct device *dev; + + bridge = lm->parent->driver_priv; + dev = lm->parent->parent; + + mutex_lock(&(lm->mtx)); + + /* Ensure that the location monitor is configured - need PGM or DATA */ + lm_ctl = ioread32(bridge->base + LM_CTL); + if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) { + mutex_unlock(&(lm->mtx)); + dev_err(dev, "Location monitor not properly configured\n"); + return -EINVAL; + } + + /* Check that a callback isn't already attached */ + if (bridge->lm_callback[monitor] != NULL) { + mutex_unlock(&(lm->mtx)); + dev_err(dev, "Existing callback attached\n"); + return -EBUSY; + } + + /* Attach callback */ + bridge->lm_callback[monitor] = callback; + + /* Enable Location Monitor interrupt */ + tmp = ioread32(bridge->base + LINT_EN); + tmp |= CA91CX42_LINT_LM[monitor]; + iowrite32(tmp, bridge->base + LINT_EN); + + /* Ensure that global Location Monitor Enable set */ + if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) { + lm_ctl |= CA91CX42_LM_CTL_EN; + iowrite32(lm_ctl, bridge->base + LM_CTL); + } + + mutex_unlock(&(lm->mtx)); + + return 0; +} + +/* + * Detach a callback function forn a specific location monitor. + */ +int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor) +{ + u32 tmp; + struct ca91cx42_driver *bridge; + + bridge = lm->parent->driver_priv; + + mutex_lock(&(lm->mtx)); + + /* Disable Location Monitor and ensure previous interrupts are clear */ + tmp = ioread32(bridge->base + LINT_EN); + tmp &= ~CA91CX42_LINT_LM[monitor]; + iowrite32(tmp, bridge->base + LINT_EN); + + iowrite32(CA91CX42_LINT_LM[monitor], + bridge->base + LINT_STAT); + + /* Detach callback */ + bridge->lm_callback[monitor] = NULL; + + /* If all location monitors disabled, disable global Location Monitor */ + if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 | + CA91CX42_LINT_LM3)) == 0) { + tmp = ioread32(bridge->base + LM_CTL); + tmp &= ~CA91CX42_LM_CTL_EN; + iowrite32(tmp, bridge->base + LM_CTL); + } + + mutex_unlock(&(lm->mtx)); + + return 0; +} + int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge) { u32 slot = 0; @@ -1190,12 +1390,10 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) #endif ca91cx42_bridge->irq_set = ca91cx42_irq_set; ca91cx42_bridge->irq_generate = ca91cx42_irq_generate; -#if 0 ca91cx42_bridge->lm_set = ca91cx42_lm_set; ca91cx42_bridge->lm_get = ca91cx42_lm_get; ca91cx42_bridge->lm_attach = ca91cx42_lm_attach; ca91cx42_bridge->lm_detach = ca91cx42_lm_detach; -#endif ca91cx42_bridge->slot_get = ca91cx42_slot_get; data = ioread32(ca91cx42_device->base + MISC_CTL); @@ -1786,77 +1984,7 @@ int ca91cx42_do_dma(vmeDmaPacket_t *vmeDma) return 0; } -int ca91cx42_lm_set(vmeLmCfg_t *vmeLm) -{ - int temp_ctl = 0; - if (vmeLm->addrU) - return -EINVAL; - - switch (vmeLm->addrSpace) { - case VME_A64: - case VME_USER3: - case VME_USER4: - return -EINVAL; - case VME_A16: - temp_ctl |= 0x00000; - break; - case VME_A24: - temp_ctl |= 0x10000; - break; - case VME_A32: - temp_ctl |= 0x20000; - break; - case VME_CRCSR: - temp_ctl |= 0x50000; - break; - case VME_USER1: - temp_ctl |= 0x60000; - break; - case VME_USER2: - temp_ctl |= 0x70000; - break; - } - - /* Disable while we are mucking around */ - iowrite32(0x00000000, bridge->base + LM_CTL); - - iowrite32(vmeLm->addr, bridge->base + LM_BS); - - /* Setup CTL register. */ - if (vmeLm->userAccessType & VME_SUPER) - temp_ctl |= 0x00200000; - if (vmeLm->userAccessType & VME_USER) - temp_ctl |= 0x00100000; - if (vmeLm->dataAccessType & VME_PROG) - temp_ctl |= 0x00800000; - if (vmeLm->dataAccessType & VME_DATA) - temp_ctl |= 0x00400000; - - - /* Write ctl reg and enable */ - iowrite32(0x80000000 | temp_ctl, bridge->base + LM_CTL); - temp_ctl = ioread32(bridge->base + LM_CTL); - - return 0; -} - -int ca91cx42_wait_lm(vmeLmCfg_t *vmeLm) -{ - unsigned long flags; - unsigned int tmp; - - spin_lock_irqsave(&lm_lock, flags); - spin_unlock_irqrestore(&lm_lock, flags); - if (tmp == 0) { - if (vmeLm->lmWait < 10) - vmeLm->lmWait = 10; - interruptible_sleep_on_timeout(&lm_queue, vmeLm->lmWait); - } - iowrite32(0x00000000, bridge->base + LM_CTL); - - return 0; -} diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.h b/drivers/staging/vme/bridges/vme_ca91cx42.h index df1050297849..b9b63088668c 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.h +++ b/drivers/staging/vme/bridges/vme_ca91cx42.h @@ -491,6 +491,19 @@ static const int CA91CX42_LINT_LM[] = { CA91CX42_LINT_LM0, CA91CX42_LINT_LM1, #define CA91CX42_VSI_CTL_LAS_PCI_IO (1<<0) #define CA91CX42_VSI_CTL_LAS_PCI_CONF (1<<1) +/* LM_CTL Register + * offset F64 + */ +#define CA91CX42_LM_CTL_EN (1<<31) +#define CA91CX42_LM_CTL_PGM (1<<23) +#define CA91CX42_LM_CTL_DATA (1<<22) +#define CA91CX42_LM_CTL_SUPR (1<<21) +#define CA91CX42_LM_CTL_NPRIV (1<<20) +#define CA91CX42_LM_CTL_AS_M (5<<16) +#define CA91CX42_LM_CTL_AS_A16 0 +#define CA91CX42_LM_CTL_AS_A24 (1<<16) +#define CA91CX42_LM_CTL_AS_A32 (1<<17) + /* * VRAI_CTL Register * offset F70 -- cgit v1.2.3 From 4860ab74d4d577d21fbfe0da3bd0925f3efc8907 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Thu, 18 Feb 2010 15:13:25 +0000 Subject: Staging: vme: add ca91cx42 dma support Add support for the DMA controller in the ca91cx42 bridge. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/TODO | 1 - drivers/staging/vme/bridges/Kconfig | 1 + drivers/staging/vme/bridges/vme_ca91cx42.c | 599 +++++++++++++---------------- drivers/staging/vme/bridges/vme_ca91cx42.h | 93 +++-- 4 files changed, 327 insertions(+), 367 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/TODO b/drivers/staging/vme/TODO index 723b67b08b91..f0dba3e4104d 100644 --- a/drivers/staging/vme/TODO +++ b/drivers/staging/vme/TODO @@ -56,7 +56,6 @@ Tempe (tsi148) Universe II (ca91c142) ---------------------- -- DMA unsupported. - RMW transactions unsupported. - Mailboxes unsupported. - Error Detection. diff --git a/drivers/staging/vme/bridges/Kconfig b/drivers/staging/vme/bridges/Kconfig index 66c49f5d8db8..9331064e0476 100644 --- a/drivers/staging/vme/bridges/Kconfig +++ b/drivers/staging/vme/bridges/Kconfig @@ -2,6 +2,7 @@ comment "VME Bridge Drivers" config VME_CA91CX42 tristate "Universe II" + depends on VIRT_TO_BUS help If you say Y here you get support for the Tundra CA91C142 (Universe II) VME bridge chip. diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index aeb11d5f919f..eddf071df40f 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c @@ -592,8 +592,8 @@ err_name: } /* - * * Free and unmap PCI Resource - * */ + * Free and unmap PCI Resource + */ static void ca91cx42_free_resource(struct vme_master_resource *image) { iounmap(image->kern_base); @@ -899,6 +899,261 @@ ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf, return retval; } +int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, + struct vme_dma_attr *dest, size_t count) +{ + struct ca91cx42_dma_entry *entry, *prev; + struct vme_dma_pci *pci_attr; + struct vme_dma_vme *vme_attr; + dma_addr_t desc_ptr; + int retval = 0; + + /* XXX descriptor must be aligned on 64-bit boundaries */ + entry = (struct ca91cx42_dma_entry *) + kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL); + if (entry == NULL) { + printk(KERN_ERR "Failed to allocate memory for dma resource " + "structure\n"); + retval = -ENOMEM; + goto err_mem; + } + + /* Test descriptor alignment */ + if ((unsigned long)&(entry->descriptor) & CA91CX42_DCPP_M) { + printk("Descriptor not aligned to 16 byte boundary as " + "required: %p\n", &(entry->descriptor)); + retval = -EINVAL; + goto err_align; + } + + memset(&(entry->descriptor), 0, sizeof(struct ca91cx42_dma_descriptor)); + + if (dest->type == VME_DMA_VME) { + entry->descriptor.dctl |= CA91CX42_DCTL_L2V; + vme_attr = (struct vme_dma_vme *)dest->private; + pci_attr = (struct vme_dma_pci *)src->private; + } else { + vme_attr = (struct vme_dma_vme *)src->private; + pci_attr = (struct vme_dma_pci *)dest->private; + } + + /* Check we can do fullfill required attributes */ + if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 | + VME_USER2)) != 0) { + + printk(KERN_ERR "Unsupported cycle type\n"); + retval = -EINVAL; + goto err_aspace; + } + + if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER | + VME_PROG | VME_DATA)) != 0) { + + printk(KERN_ERR "Unsupported cycle type\n"); + retval = -EINVAL; + goto err_cycle; + } + + /* Check to see if we can fullfill source and destination */ + if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) || + ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) { + + printk(KERN_ERR "Cannot perform transfer with this " + "source-destination combination\n"); + retval = -EINVAL; + goto err_direct; + } + + /* Setup cycle types */ + if (vme_attr->cycle & VME_BLT) + entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT; + + /* Setup data width */ + switch (vme_attr->dwidth) { + case VME_D8: + entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8; + break; + case VME_D16: + entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16; + break; + case VME_D32: + entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32; + break; + case VME_D64: + entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64; + break; + default: + printk(KERN_ERR "Invalid data width\n"); + return -EINVAL; + } + + /* Setup address space */ + switch (vme_attr->aspace) { + case VME_A16: + entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16; + break; + case VME_A24: + entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24; + break; + case VME_A32: + entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32; + break; + case VME_USER1: + entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1; + break; + case VME_USER2: + entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2; + break; + default: + printk(KERN_ERR "Invalid address space\n"); + return -EINVAL; + break; + } + + if (vme_attr->cycle & VME_SUPER) + entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR; + if (vme_attr->cycle & VME_PROG) + entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM; + + entry->descriptor.dtbc = count; + entry->descriptor.dla = pci_attr->address; + entry->descriptor.dva = vme_attr->address; + entry->descriptor.dcpp = CA91CX42_DCPP_NULL; + + /* Add to list */ + list_add_tail(&(entry->list), &(list->entries)); + + /* Fill out previous descriptors "Next Address" */ + if (entry->list.prev != &(list->entries)) { + prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry, + list); + /* We need the bus address for the pointer */ + desc_ptr = virt_to_bus(&(entry->descriptor)); + prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M; + } + + return 0; + +err_cycle: +err_aspace: +err_direct: +err_align: + kfree(entry); +err_mem: + return retval; +} + +static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge) +{ + u32 tmp; + struct ca91cx42_driver *bridge; + + bridge = ca91cx42_bridge->driver_priv; + + tmp = ioread32(bridge->base + DGCS); + + if (tmp & CA91CX42_DGCS_ACT) + return 0; + else + return 1; +} + +int ca91cx42_dma_list_exec(struct vme_dma_list *list) +{ + struct vme_dma_resource *ctrlr; + struct ca91cx42_dma_entry *entry; + int retval = 0; + dma_addr_t bus_addr; + u32 val; + + struct ca91cx42_driver *bridge; + + ctrlr = list->parent; + + bridge = ctrlr->parent->driver_priv; + + mutex_lock(&(ctrlr->mtx)); + + if (!(list_empty(&(ctrlr->running)))) { + /* + * XXX We have an active DMA transfer and currently haven't + * sorted out the mechanism for "pending" DMA transfers. + * Return busy. + */ + /* Need to add to pending here */ + mutex_unlock(&(ctrlr->mtx)); + return -EBUSY; + } else { + list_add(&(list->list), &(ctrlr->running)); + } + + /* Get first bus address and write into registers */ + entry = list_first_entry(&(list->entries), struct ca91cx42_dma_entry, + list); + + bus_addr = virt_to_bus(&(entry->descriptor)); + + mutex_unlock(&(ctrlr->mtx)); + + iowrite32(0, bridge->base + DTBC); + iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP); + + /* Start the operation */ + val = ioread32(bridge->base + DGCS); + + /* XXX Could set VMEbus On and Off Counters here */ + val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M); + + val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT | + CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR | + CA91CX42_DGCS_PERR); + + iowrite32(val, bridge->base + DGCS); + + val |= CA91CX42_DGCS_GO; + + iowrite32(val, bridge->base + DGCS); + + wait_event_interruptible(bridge->dma_queue, + ca91cx42_dma_busy(ctrlr->parent)); + + /* + * Read status register, this register is valid until we kick off a + * new transfer. + */ + val = ioread32(bridge->base + DGCS); + + if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR | + CA91CX42_DGCS_PERR)) { + + printk(KERN_ERR "ca91c042: DMA Error. DGCS=%08X\n", val); + val = ioread32(bridge->base + DCTL); + } + + /* Remove list from running list */ + mutex_lock(&(ctrlr->mtx)); + list_del(&(list->list)); + mutex_unlock(&(ctrlr->mtx)); + + return retval; + +} + +int ca91cx42_dma_list_empty(struct vme_dma_list *list) +{ + struct list_head *pos, *temp; + struct ca91cx42_dma_entry *entry; + + /* detach and free each entry */ + list_for_each_safe(pos, temp, &(list->entries)) { + list_del(pos); + entry = list_entry(pos, struct ca91cx42_dma_entry, list); + kfree(entry); + } + + return 0; +} + /* * All 4 location monitors reside at the same base - this is therefore a * system wide configuration. @@ -1203,9 +1458,7 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) struct ca91cx42_driver *ca91cx42_device; struct vme_master_resource *master_image; struct vme_slave_resource *slave_image; -#if 0 struct vme_dma_resource *dma_ctrlr; -#endif struct vme_lm_resource *lm; /* We want to support more than one of each bridge so we need to @@ -1336,7 +1589,7 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) list_add_tail(&(slave_image->list), &(ca91cx42_bridge->slave_resources)); } -#if 0 + /* Add dma engines to list */ INIT_LIST_HEAD(&(ca91cx42_bridge->dma_resources)); for (i = 0; i < CA91C142_MAX_DMA; i++) { @@ -1359,7 +1612,7 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) list_add_tail(&(dma_ctrlr->list), &(ca91cx42_bridge->dma_resources)); } -#endif + /* Add location monitor to list */ INIT_LIST_HEAD(&(ca91cx42_bridge->lm_resources)); lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL); @@ -1384,10 +1637,10 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) ca91cx42_bridge->master_write = ca91cx42_master_write; #if 0 ca91cx42_bridge->master_rmw = ca91cx42_master_rmw; +#endif ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add; ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec; ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty; -#endif ca91cx42_bridge->irq_set = ca91cx42_irq_set; ca91cx42_bridge->irq_generate = ca91cx42_irq_generate; ca91cx42_bridge->lm_set = ca91cx42_lm_set; @@ -1436,7 +1689,6 @@ err_lm: list_del(pos); kfree(lm); } -#if 0 err_dma: /* resources are stored in link list */ list_for_each(pos, &(ca91cx42_bridge->dma_resources)) { @@ -1444,7 +1696,6 @@ err_dma: list_del(pos); kfree(dma_ctrlr); } -#endif err_slave: /* resources are stored in link list */ list_for_each(pos, &(ca91cx42_bridge->slave_resources)) { @@ -1575,7 +1826,6 @@ module_exit(ca91cx42_exit); *--------------------------------------------------------------------------*/ #if 0 -#define SWIZZLE(X) ( ((X & 0xFF000000) >> 24) | ((X & 0x00FF0000) >> 8) | ((X & 0x0000FF00) << 8) | ((X & 0x000000FF) << 24)) int ca91cx42_master_rmw(vmeRmwCfg_t *vmeRmw) { @@ -1659,335 +1909,6 @@ int ca91cx42_master_rmw(vmeRmwCfg_t *vmeRmw) return 0; } -int uniSetupDctlReg(vmeDmaPacket_t * vmeDma, int *dctlregreturn) -{ - unsigned int dctlreg = 0x80; - struct vmeAttr *vmeAttr; - - if (vmeDma->srcBus == VME_DMA_VME) { - dctlreg = 0; - vmeAttr = &vmeDma->srcVmeAttr; - } else { - dctlreg = 0x80000000; - vmeAttr = &vmeDma->dstVmeAttr; - } - - switch (vmeAttr->maxDataWidth) { - case VME_D8: - break; - case VME_D16: - dctlreg |= 0x00400000; - break; - case VME_D32: - dctlreg |= 0x00800000; - break; - case VME_D64: - dctlreg |= 0x00C00000; - break; - } - - switch (vmeAttr->addrSpace) { - case VME_A16: - break; - case VME_A24: - dctlreg |= 0x00010000; - break; - case VME_A32: - dctlreg |= 0x00020000; - break; - case VME_USER1: - dctlreg |= 0x00060000; - break; - case VME_USER2: - dctlreg |= 0x00070000; - break; - - case VME_A64: /* not supported in Universe DMA */ - case VME_CRCSR: - case VME_USER3: - case VME_USER4: - return -EINVAL; - break; - } - if (vmeAttr->userAccessType == VME_PROG) { - dctlreg |= 0x00004000; - } - if (vmeAttr->dataAccessType == VME_SUPER) { - dctlreg |= 0x00001000; - } - if (vmeAttr->xferProtocol != VME_SCT) { - dctlreg |= 0x00000100; - } - *dctlregreturn = dctlreg; - return 0; -} - -unsigned int -ca91cx42_start_dma(int channel, unsigned int dgcsreg, TDMA_Cmd_Packet *vmeLL) -{ - unsigned int val; - - /* Setup registers as needed for direct or chained. */ - if (dgcsreg & 0x8000000) { - iowrite32(0, bridge->base + DTBC); - iowrite32((unsigned int)vmeLL, bridge->base + DCPP); - } else { -#if 0 - printk(KERN_ERR "Starting: DGCS = %08x\n", dgcsreg); - printk(KERN_ERR "Starting: DVA = %08x\n", - ioread32(&vmeLL->dva)); - printk(KERN_ERR "Starting: DLV = %08x\n", - ioread32(&vmeLL->dlv)); - printk(KERN_ERR "Starting: DTBC = %08x\n", - ioread32(&vmeLL->dtbc)); - printk(KERN_ERR "Starting: DCTL = %08x\n", - ioread32(&vmeLL->dctl)); -#endif - /* Write registers */ - iowrite32(ioread32(&vmeLL->dva), bridge->base + DVA); - iowrite32(ioread32(&vmeLL->dlv), bridge->base + DLA); - iowrite32(ioread32(&vmeLL->dtbc), bridge->base + DTBC); - iowrite32(ioread32(&vmeLL->dctl), bridge->base + DCTL); - iowrite32(0, bridge->base + DCPP); - } - - /* Start the operation */ - iowrite32(dgcsreg, bridge->base + DGCS); - val = get_tbl(); - iowrite32(dgcsreg | 0x8000000F, bridge->base + DGCS); - return val; -} - -TDMA_Cmd_Packet *ca91cx42_setup_dma(vmeDmaPacket_t * vmeDma) -{ - vmeDmaPacket_t *vmeCur; - int maxPerPage; - int currentLLcount; - TDMA_Cmd_Packet *startLL; - TDMA_Cmd_Packet *currentLL; - TDMA_Cmd_Packet *nextLL; - unsigned int dctlreg = 0; - - maxPerPage = PAGESIZE / sizeof(TDMA_Cmd_Packet) - 1; - startLL = (TDMA_Cmd_Packet *) __get_free_pages(GFP_KERNEL, 0); - if (startLL == 0) { - return startLL; - } - /* First allocate pages for descriptors and create linked list */ - vmeCur = vmeDma; - currentLL = startLL; - currentLLcount = 0; - while (vmeCur != 0) { - if (vmeCur->pNextPacket != 0) { - currentLL->dcpp = (unsigned int)(currentLL + 1); - currentLLcount++; - if (currentLLcount >= maxPerPage) { - currentLL->dcpp = - __get_free_pages(GFP_KERNEL, 0); - currentLLcount = 0; - } - currentLL = (TDMA_Cmd_Packet *) currentLL->dcpp; - } else { - currentLL->dcpp = (unsigned int)0; - } - vmeCur = vmeCur->pNextPacket; - } - - /* Next fill in information for each descriptor */ - vmeCur = vmeDma; - currentLL = startLL; - while (vmeCur != 0) { - if (vmeCur->srcBus == VME_DMA_VME) { - iowrite32(vmeCur->srcAddr, ¤tLL->dva); - iowrite32(vmeCur->dstAddr, ¤tLL->dlv); - } else { - iowrite32(vmeCur->srcAddr, ¤tLL->dlv); - iowrite32(vmeCur->dstAddr, ¤tLL->dva); - } - uniSetupDctlReg(vmeCur, &dctlreg); - iowrite32(dctlreg, ¤tLL->dctl); - iowrite32(vmeCur->byteCount, ¤tLL->dtbc); - - currentLL = (TDMA_Cmd_Packet *) currentLL->dcpp; - vmeCur = vmeCur->pNextPacket; - } - - /* Convert Links to PCI addresses. */ - currentLL = startLL; - while (currentLL != 0) { - nextLL = (TDMA_Cmd_Packet *) currentLL->dcpp; - if (nextLL == 0) { - iowrite32(1, ¤tLL->dcpp); - } else { - iowrite32((unsigned int)virt_to_bus(nextLL), - ¤tLL->dcpp); - } - currentLL = nextLL; - } - - /* Return pointer to descriptors list */ - return startLL; -} - -int ca91cx42_free_dma(TDMA_Cmd_Packet *startLL) -{ - TDMA_Cmd_Packet *currentLL; - TDMA_Cmd_Packet *prevLL; - TDMA_Cmd_Packet *nextLL; - unsigned int dcppreg; - - /* Convert Links to virtual addresses. */ - currentLL = startLL; - while (currentLL != 0) { - dcppreg = ioread32(¤tLL->dcpp); - dcppreg &= ~6; - if (dcppreg & 1) { - currentLL->dcpp = 0; - } else { - currentLL->dcpp = (unsigned int)bus_to_virt(dcppreg); - } - currentLL = (TDMA_Cmd_Packet *) currentLL->dcpp; - } - - /* Free all pages associated with the descriptors. */ - currentLL = startLL; - prevLL = currentLL; - while (currentLL != 0) { - nextLL = (TDMA_Cmd_Packet *) currentLL->dcpp; - if (currentLL + 1 != nextLL) { - free_pages((int)prevLL, 0); - prevLL = nextLL; - } - currentLL = nextLL; - } - - /* Return pointer to descriptors list */ - return 0; -} - -int ca91cx42_do_dma(vmeDmaPacket_t *vmeDma) -{ - unsigned int dgcsreg = 0; - unsigned int dctlreg = 0; - int val; - int channel, x; - vmeDmaPacket_t *curDma; - TDMA_Cmd_Packet *dmaLL; - - /* Sanity check the VME chain. */ - channel = vmeDma->channel_number; - if (channel > 0) { - return -EINVAL; - } - curDma = vmeDma; - while (curDma != 0) { - if (curDma->byteCount == 0) { - return -EINVAL; - } - if (curDma->byteCount >= 0x1000000) { - return -EINVAL; - } - if ((curDma->srcAddr & 7) != (curDma->dstAddr & 7)) { - return -EINVAL; - } - switch (curDma->srcBus) { - case VME_DMA_PCI: - if (curDma->dstBus != VME_DMA_VME) { - return -EINVAL; - } - break; - case VME_DMA_VME: - if (curDma->dstBus != VME_DMA_PCI) { - return -EINVAL; - } - break; - default: - return -EINVAL; - break; - } - if (uniSetupDctlReg(curDma, &dctlreg) < 0) { - return -EINVAL; - } - - curDma = curDma->pNextPacket; - if (curDma == vmeDma) { /* Endless Loop! */ - return -EINVAL; - } - } - - /* calculate control register */ - if (vmeDma->pNextPacket != 0) { - dgcsreg = 0x8000000; - } else { - dgcsreg = 0; - } - - for (x = 0; x < 8; x++) { /* vme block size */ - if ((256 << x) >= vmeDma->maxVmeBlockSize) { - break; - } - } - if (x == 8) - x = 7; - dgcsreg |= (x << 20); - - if (vmeDma->vmeBackOffTimer) { - for (x = 1; x < 8; x++) { /* vme timer */ - if ((16 << (x - 1)) >= vmeDma->vmeBackOffTimer) { - break; - } - } - if (x == 8) - x = 7; - dgcsreg |= (x << 16); - } - /*` Setup the dma chain */ - dmaLL = ca91cx42_setup_dma(vmeDma); - - /* Start the DMA */ - if (dgcsreg & 0x8000000) { - vmeDma->vmeDmaStartTick = - ca91cx42_start_dma(channel, dgcsreg, - (TDMA_Cmd_Packet *) virt_to_phys(dmaLL)); - } else { - vmeDma->vmeDmaStartTick = - ca91cx42_start_dma(channel, dgcsreg, dmaLL); - } - - wait_event_interruptible(dma_queue, - ioread32(bridge->base + DGCS) & 0x800); - - val = ioread32(bridge->base + DGCS); - iowrite32(val | 0xF00, bridge->base + DGCS); - - vmeDma->vmeDmaStatus = 0; - - if (!(val & 0x00000800)) { - vmeDma->vmeDmaStatus = val & 0x700; - printk(KERN_ERR "ca91c042: DMA Error in ca91cx42_DMA_irqhandler" - " DGCS=%08X\n", val); - val = ioread32(bridge->base + DCPP); - printk(KERN_ERR "ca91c042: DCPP=%08X\n", val); - val = ioread32(bridge->base + DCTL); - printk(KERN_ERR "ca91c042: DCTL=%08X\n", val); - val = ioread32(bridge->base + DTBC); - printk(KERN_ERR "ca91c042: DTBC=%08X\n", val); - val = ioread32(bridge->base + DLA); - printk(KERN_ERR "ca91c042: DLA=%08X\n", val); - val = ioread32(bridge->base + DVA); - printk(KERN_ERR "ca91c042: DVA=%08X\n", val); - - } - /* Free the dma chain */ - ca91cx42_free_dma(dmaLL); - - return 0; -} - - - - - int ca91cx42_set_arbiter(vmeArbiterCfg_t *vmeArb) { int temp_ctl = 0; diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.h b/drivers/staging/vme/bridges/vme_ca91cx42.h index b9b63088668c..221d20f0b925 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.h +++ b/drivers/staging/vme/bridges/vme_ca91cx42.h @@ -57,7 +57,7 @@ struct ca91cx42_driver { struct ca91cx42_dma_descriptor { unsigned int dctl; /* DMA Control */ unsigned int dtbc; /* Transfer Byte Count */ - unsigned int dlv; /* PCI Address */ + unsigned int dla; /* PCI Address */ unsigned int res1; /* Reserved */ unsigned int dva; /* Vme Address */ unsigned int res2; /* Reserved */ @@ -253,32 +253,6 @@ static const int CA91CX42_VSI_TO[] = { VSI0_TO, VSI1_TO, VSI2_TO, VSI3_TO, #define VCSR_SET 0x0FF8 #define VCSR_BS 0x0FFC -// DMA General Control/Status Register DGCS (0x220) -// 32-24 || GO | STOPR | HALTR | 0 || CHAIN | 0 | 0 | 0 || -// 23-16 || VON || VOFF || -// 15-08 || ACT | STOP | HALT | 0 || DONE | LERR | VERR | P_ERR || -// 07-00 || 0 | INT_S | INT_H | 0 || I_DNE | I_LER | I_VER | I_PER || - -// VON - Length Per DMA VMEBus Transfer -// 0000 = None -// 0001 = 256 Bytes -// 0010 = 512 -// 0011 = 1024 -// 0100 = 2048 -// 0101 = 4096 -// 0110 = 8192 -// 0111 = 16384 - -// VOFF - wait between DMA tenures -// 0000 = 0 us -// 0001 = 16 -// 0010 = 32 -// 0011 = 64 -// 0100 = 128 -// 0101 = 256 -// 0110 = 512 -// 0111 = 1024 - /* * PCI Class Register * offset 008 @@ -370,6 +344,71 @@ static const int CA91CX42_VSI_TO[] = { VSI0_TO, VSI1_TO, VSI2_TO, VSI3_TO, #define CA91CX42_OF_SLSI_LAS 0 #define CA91CX42_BM_SLSI_RESERVED 0x3F0F0000 +/* + * DCTL Register + * offset 200 + */ +#define CA91CX42_DCTL_L2V (1<<31) +#define CA91CX42_DCTL_VDW_M (3<<22) +#define CA91CX42_DCTL_VDW_M (3<<22) +#define CA91CX42_DCTL_VDW_D8 0 +#define CA91CX42_DCTL_VDW_D16 (1<<22) +#define CA91CX42_DCTL_VDW_D32 (1<<23) +#define CA91CX42_DCTL_VDW_D64 (3<<22) + +#define CA91CX42_DCTL_VAS_M (7<<16) +#define CA91CX42_DCTL_VAS_A16 0 +#define CA91CX42_DCTL_VAS_A24 (1<<16) +#define CA91CX42_DCTL_VAS_A32 (1<<17) +#define CA91CX42_DCTL_VAS_USER1 (3<<17) +#define CA91CX42_DCTL_VAS_USER2 (7<<16) + +#define CA91CX42_DCTL_PGM_M (1<<14) +#define CA91CX42_DCTL_PGM_DATA 0 +#define CA91CX42_DCTL_PGM_PGM (1<<14) + +#define CA91CX42_DCTL_SUPER_M (1<<12) +#define CA91CX42_DCTL_SUPER_NPRIV 0 +#define CA91CX42_DCTL_SUPER_SUPR (1<<12) + +#define CA91CX42_DCTL_VCT_M (1<<8) +#define CA91CX42_DCTL_VCT_BLT (1<<8) +#define CA91CX42_DCTL_LD64EN (1<<7) + +/* + * DCPP Register + * offset 218 + */ +#define CA91CX42_DCPP_M 0xf +#define CA91CX42_DCPP_NULL (1<<0) + +/* + * DMA General Control/Status Register (DGCS) + * offset 220 + */ +#define CA91CX42_DGCS_GO (1<<31) +#define CA91CX42_DGCS_STOP_REQ (1<<30) +#define CA91CX42_DGCS_HALT_REQ (1<<29) +#define CA91CX42_DGCS_CHAIN (1<<27) + +#define CA91CX42_DGCS_VON_M (7<<20) + +#define CA91CX42_DGCS_VOFF_M (0xf<<16) + +#define CA91CX42_DGCS_ACT (1<<15) +#define CA91CX42_DGCS_STOP (1<<14) +#define CA91CX42_DGCS_HALT (1<<13) +#define CA91CX42_DGCS_DONE (1<<11) +#define CA91CX42_DGCS_LERR (1<<10) +#define CA91CX42_DGCS_VERR (1<<9) +#define CA91CX42_DGCS_PERR (1<<8) +#define CA91CX42_DGCS_INT_STOP (1<<6) +#define CA91CX42_DGCS_INT_HALT (1<<5) +#define CA91CX42_DGCS_INT_DONE (1<<3) +#define CA91CX42_DGCS_INT_LERR (1<<2) +#define CA91CX42_DGCS_INT_VERR (1<<1) +#define CA91CX42_DGCS_INT_PERR (1<<0) + /* * PCI Interrupt Enable Register * offset 300 -- cgit v1.2.3 From 21e0cf6d2e59e19f77096e73d83157734e7f7782 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Thu, 18 Feb 2010 15:13:32 +0000 Subject: Staging: vme: Correct ca91cx42 resource handling The ca91cx42 driver currently incorrectly handles master windows, setting and retrieving the sizing parameters incorrectly. Also, in the slave window handling, it uses an incorrectly set variable. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/bridges/vme_ca91cx42.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index eddf071df40f..0348cc847302 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c @@ -337,7 +337,7 @@ int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, unsigned long long vme_base, unsigned long long size, dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle) { - unsigned int i, addr = 0, granularity = 0; + unsigned int i, addr = 0, granularity; unsigned int temp_ctl = 0; unsigned int vme_bound, pci_offset; struct ca91cx42_driver *bridge; @@ -376,7 +376,7 @@ int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, * Bound address is a valid address for the window, adjust * accordingly */ - vme_bound = vme_base + size - granularity; + vme_bound = vme_base + size; pci_offset = pci_base - vme_base; /* XXX Need to check that vme_base, vme_bound and pci_offset aren't @@ -609,20 +609,27 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth) { int retval = 0; - unsigned int i; + unsigned int i, granularity = 0; unsigned int temp_ctl = 0; unsigned long long pci_bound, vme_offset, pci_base; struct ca91cx42_driver *bridge; bridge = image->parent->driver_priv; + i = image->number; + + if ((i == 0) || (i == 4)) + granularity = 0x1000; + else + granularity = 0x10000; + /* Verify input data */ - if (vme_base & 0xFFF) { + if (vme_base & (granularity - 1)) { printk(KERN_ERR "Invalid VME Window alignment\n"); retval = -EINVAL; goto err_window; } - if (size & 0xFFF) { + if (size & (granularity - 1)) { printk(KERN_ERR "Invalid VME Window alignment\n"); retval = -EINVAL; goto err_window; @@ -652,11 +659,9 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, * Bound address is a valid address for the window, adjust * according to window granularity. */ - pci_bound = pci_base + (size - 0x1000); + pci_bound = pci_base + size; vme_offset = vme_base - pci_base; - i = image->number; - /* Disable while we are mucking around */ temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); temp_ctl &= ~CA91CX42_LSI_CTL_EN; @@ -779,7 +784,7 @@ int __ca91cx42_master_get(struct vme_master_resource *image, int *enabled, pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]); *vme_base = pci_base + vme_offset; - *size = (pci_bound - pci_base) + 0x1000; + *size = (unsigned long long)(pci_bound - pci_base); *enabled = 0; *aspace = 0; @@ -872,7 +877,7 @@ int ca91cx42_master_get(struct vme_master_resource *image, int *enabled, ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf, size_t count, loff_t offset) { - int retval; + ssize_t retval; spin_lock(&(image->lock)); -- cgit v1.2.3 From 04e10e15f9509d08c5e2194ea2ae680c013d5b63 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Thu, 18 Feb 2010 15:13:38 +0000 Subject: Staging: vme: Add ca91cx42 rmw support Add support for Master Read-Modify-Write cycles on the ca91cx42. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/TODO | 1 - drivers/staging/vme/bridges/vme_ca91cx42.c | 138 +++++++++++------------------ drivers/staging/vme/bridges/vme_ca91cx42.h | 10 +++ 3 files changed, 64 insertions(+), 85 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/TODO b/drivers/staging/vme/TODO index f0dba3e4104d..82c222b4a146 100644 --- a/drivers/staging/vme/TODO +++ b/drivers/staging/vme/TODO @@ -56,7 +56,6 @@ Tempe (tsi148) Universe II (ca91c142) ---------------------- -- RMW transactions unsupported. - Mailboxes unsupported. - Error Detection. - Control of prefetch size, threshold. diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index 0348cc847302..1edfa442d53b 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c @@ -904,6 +904,60 @@ ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf, return retval; } +unsigned int ca91cx42_master_rmw(struct vme_master_resource *image, + unsigned int mask, unsigned int compare, unsigned int swap, + loff_t offset) +{ + u32 pci_addr, result; + int i; + struct ca91cx42_driver *bridge; + struct device *dev; + + bridge = image->parent->driver_priv; + dev = image->parent->parent; + + /* Find the PCI address that maps to the desired VME address */ + i = image->number; + + /* Locking as we can only do one of these at a time */ + mutex_lock(&(bridge->vme_rmw)); + + /* Lock image */ + spin_lock(&(image->lock)); + + pci_addr = (u32)image->kern_base + offset; + + /* Address must be 4-byte aligned */ + if (pci_addr & 0x3) { + dev_err(dev, "RMW Address not 4-byte aligned\n"); + return -EINVAL; + } + + /* Ensure RMW Disabled whilst configuring */ + iowrite32(0, bridge->base + SCYC_CTL); + + /* Configure registers */ + iowrite32(mask, bridge->base + SCYC_EN); + iowrite32(compare, bridge->base + SCYC_CMP); + iowrite32(swap, bridge->base + SCYC_SWP); + iowrite32(pci_addr, bridge->base + SCYC_ADDR); + + /* Enable RMW */ + iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL); + + /* Kick process off with a read to the required address. */ + result = ioread32(image->kern_base + offset); + + /* Disable RMW */ + iowrite32(0, bridge->base + SCYC_CTL); + + spin_unlock(&(image->lock)); + + mutex_unlock(&(bridge->vme_rmw)); + + return result; +} + int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count) { @@ -1640,9 +1694,7 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) ca91cx42_bridge->master_set = ca91cx42_master_set; ca91cx42_bridge->master_read = ca91cx42_master_read; ca91cx42_bridge->master_write = ca91cx42_master_write; -#if 0 ca91cx42_bridge->master_rmw = ca91cx42_master_rmw; -#endif ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add; ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec; ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty; @@ -1832,88 +1884,6 @@ module_exit(ca91cx42_exit); #if 0 -int ca91cx42_master_rmw(vmeRmwCfg_t *vmeRmw) -{ - int temp_ctl = 0; - int tempBS = 0; - int tempBD = 0; - int tempTO = 0; - int vmeBS = 0; - int vmeBD = 0; - int *rmw_pci_data_ptr = NULL; - int *vaDataPtr = NULL; - int i; - vmeOutWindowCfg_t vmeOut; - if (vmeRmw->maxAttempts < 1) { - return -EINVAL; - } - if (vmeRmw->targetAddrU) { - return -EINVAL; - } - /* Find the PCI address that maps to the desired VME address */ - for (i = 0; i < 8; i++) { - temp_ctl = ioread32(bridge->base + - CA91CX42_LSI_CTL[i]); - if ((temp_ctl & 0x80000000) == 0) { - continue; - } - memset(&vmeOut, 0, sizeof(vmeOut)); - vmeOut.windowNbr = i; - ca91cx42_get_out_bound(&vmeOut); - if (vmeOut.addrSpace != vmeRmw->addrSpace) { - continue; - } - tempBS = ioread32(bridge->base + CA91CX42_LSI_BS[i]); - tempBD = ioread32(bridge->base + CA91CX42_LSI_BD[i]); - tempTO = ioread32(bridge->base + CA91CX42_LSI_TO[i]); - vmeBS = tempBS + tempTO; - vmeBD = tempBD + tempTO; - if ((vmeRmw->targetAddr >= vmeBS) && - (vmeRmw->targetAddr < vmeBD)) { - rmw_pci_data_ptr = - (int *)(tempBS + (vmeRmw->targetAddr - vmeBS)); - vaDataPtr = - (int *)(out_image_va[i] + - (vmeRmw->targetAddr - vmeBS)); - break; - } - } - - /* If no window - fail. */ - if (rmw_pci_data_ptr == NULL) { - return -EINVAL; - } - /* Setup the RMW registers. */ - iowrite32(0, bridge->base + SCYC_CTL); - iowrite32(SWIZZLE(vmeRmw->enableMask), bridge->base + SCYC_EN); - iowrite32(SWIZZLE(vmeRmw->compareData), bridge->base + - SCYC_CMP); - iowrite32(SWIZZLE(vmeRmw->swapData), bridge->base + SCYC_SWP); - iowrite32((int)rmw_pci_data_ptr, bridge->base + SCYC_ADDR); - iowrite32(1, bridge->base + SCYC_CTL); - - /* Run the RMW cycle until either success or max attempts. */ - vmeRmw->numAttempts = 1; - while (vmeRmw->numAttempts <= vmeRmw->maxAttempts) { - - if ((ioread32(vaDataPtr) & vmeRmw->enableMask) == - (vmeRmw->swapData & vmeRmw->enableMask)) { - - iowrite32(0, bridge->base + SCYC_CTL); - break; - - } - vmeRmw->numAttempts++; - } - - /* If no success, set num Attempts to be greater than max attempts */ - if (vmeRmw->numAttempts > vmeRmw->maxAttempts) { - vmeRmw->numAttempts = vmeRmw->maxAttempts + 1; - } - - return 0; -} - int ca91cx42_set_arbiter(vmeArbiterCfg_t *vmeArb) { int temp_ctl = 0; diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.h b/drivers/staging/vme/bridges/vme_ca91cx42.h index 221d20f0b925..e72c65b193ec 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.h +++ b/drivers/staging/vme/bridges/vme_ca91cx42.h @@ -316,6 +316,16 @@ static const int CA91CX42_VSI_TO[] = { VSI0_TO, VSI1_TO, VSI2_TO, VSI3_TO, #define CA91CX42_LSI_CTL_VCT_MBLT (1<<8) #define CA91CX42_LSI_CTL_LAS (1<<0) +/* + * SCYC_CTL Register + * offset 178 + */ +#define CA91CX42_SCYC_CTL_LAS_PCIMEM 0 +#define CA91CX42_SCYC_CTL_LAS_PCIIO (1<<2) + +#define CA91CX42_SCYC_CTL_CYC_M (3<<0) +#define CA91CX42_SCYC_CTL_CYC_RMW (1<<0) +#define CA91CX42_SCYC_CTL_CYC_ADOH (1<<1) /* * LMISC Register -- cgit v1.2.3 From 25331ba2f8e36abe77211765fa879106cdbc43e6 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Thu, 18 Feb 2010 15:13:45 +0000 Subject: Staging: vme: ca91cx42 slot detection Sort out slot detection on the ca91cx42. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/bridges/vme_ca91cx42.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index 1edfa442d53b..ecd917986678 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c @@ -1452,14 +1452,12 @@ static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge, bridge = ca91cx42_bridge->driver_priv; -/* XXX We may need to set this somehow as the Universe II does not support - * geographical addressing. - */ -#if 0 - if (vme_slotnum != -1) - iowrite32(vme_slotnum << 27, bridge->base + VCSR_BS); -#endif slot = ca91cx42_slot_get(ca91cx42_bridge); + + /* Write CSR Base Address if slot ID is supplied as a module param */ + if (geoid) + iowrite32(geoid << 27, bridge->base + VCSR_BS); + dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot); if (slot == 0) { dev_err(&pdev->dev, "Slot number is unset, not configuring " @@ -1714,10 +1712,6 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev)) { dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); - retval = -EINVAL; -#if 0 - goto err_crcsr; -#endif } /* Need to save ca91cx42_bridge pointer locally in link list for use in @@ -1736,9 +1730,6 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) vme_unregister_bridge(ca91cx42_bridge); err_reg: ca91cx42_crcsr_exit(ca91cx42_bridge, pdev); -#if 0 -err_crcsr: -#endif err_lm: /* resources are stored in link list */ list_for_each(pos, &(ca91cx42_bridge->lm_resources)) { -- cgit v1.2.3 From bb9ea89ec8a3d80a835d53afc388ad5f67fd3cb3 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Thu, 18 Feb 2010 16:22:13 +0000 Subject: Staging: vme: Remove legacy unsupported code Remove the code from the drivers that we are not going to implement before submitting for review. Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/bridges/vme_ca91cx42.c | 150 +----------- drivers/staging/vme/bridges/vme_tsi148.c | 351 +---------------------------- drivers/staging/vme/vme.c | 4 - drivers/staging/vme/vme_bridge.h | 58 ----- 4 files changed, 4 insertions(+), 559 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index ecd917986678..2795ff2411e0 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c @@ -93,21 +93,6 @@ static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge) return CA91CX42_LINT_SW_IACK; } -#if 0 -int ca91cx42_bus_error_chk(int clrflag) -{ - int tmp; - tmp = ioread32(bridge->base + PCI_COMMAND); - if (tmp & 0x08000000) { /* S_TA is Set */ - if (clrflag) - iowrite32(tmp | 0x08000000, - bridge->base + PCI_COMMAND); - return 1; - } - return 0; -} -#endif - static u32 ca91cx42_VERR_irqhandler(struct ca91cx42_driver *bridge) { int val; @@ -379,10 +364,6 @@ int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, vme_bound = vme_base + size; pci_offset = pci_base - vme_base; - /* XXX Need to check that vme_base, vme_bound and pci_offset aren't - * too big for registers - */ - if ((i == 0) || (i == 4)) granularity = 0x1000; else @@ -411,18 +392,6 @@ int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]); iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]); -/* XXX Prefetch stuff currently unsupported */ -#if 0 - if (vmeIn->wrPostEnable) - temp_ctl |= CA91CX42_VSI_CTL_PWEN; - if (vmeIn->prefetchEnable) - temp_ctl |= CA91CX42_VSI_CTL_PREN; - if (vmeIn->rmwLock) - temp_ctl |= CA91CX42_VSI_CTL_LLRMW; - if (vmeIn->data64BitCapable) - temp_ctl |= CA91CX42_VSI_CTL_LD64EN; -#endif - /* Setup address space */ temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M; temp_ctl |= addr; @@ -637,9 +606,6 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, spin_lock(&(image->lock)); - /* XXX We should do this much later, so that we can exit without - * needing to redo the mapping... - */ /* * Let's allocate the resource here rather than further up the stack as * it avoids pushing loads of bus dependant stuff up the stack @@ -667,12 +633,6 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, temp_ctl &= ~CA91CX42_LSI_CTL_EN; iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); -/* XXX Prefetch stuff currently unsupported */ -#if 0 - if (vmeOut->wrPostEnable) - temp_ctl |= 0x40000000; -#endif - /* Setup cycle types */ temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M; if (cycle & VME_BLT) @@ -849,12 +809,6 @@ int __ca91cx42_master_get(struct vme_master_resource *image, int *enabled, break; } -/* XXX Prefetch stuff currently unsupported */ -#if 0 - if (ctl & 0x40000000) - vmeOut->wrPostEnable = 1; -#endif - return 0; } @@ -1812,9 +1766,9 @@ void ca91cx42_remove(struct pci_dev *pdev) iowrite32(0x00F00000, bridge->base + VSI7_CTL); vme_unregister_bridge(ca91cx42_bridge); -#if 0 - ca91cx42_crcsr_exit(pdev); -#endif + + ca91cx42_crcsr_exit(ca91cx42_bridge, pdev); + /* resources are stored in link list */ list_for_each(pos, &(ca91cx42_bridge->lm_resources)) { lm = list_entry(pos, struct vme_lm_resource, list); @@ -1868,101 +1822,3 @@ MODULE_LICENSE("GPL"); module_init(ca91cx42_init); module_exit(ca91cx42_exit); - -/*---------------------------------------------------------------------------- - * STAGING - *--------------------------------------------------------------------------*/ - -#if 0 - -int ca91cx42_set_arbiter(vmeArbiterCfg_t *vmeArb) -{ - int temp_ctl = 0; - int vbto = 0; - - temp_ctl = ioread32(bridge->base + MISC_CTL); - temp_ctl &= 0x00FFFFFF; - - if (vmeArb->globalTimeoutTimer == 0xFFFFFFFF) { - vbto = 7; - } else if (vmeArb->globalTimeoutTimer > 1024) { - return -EINVAL; - } else if (vmeArb->globalTimeoutTimer == 0) { - vbto = 0; - } else { - vbto = 1; - while ((16 * (1 << (vbto - 1))) < vmeArb->globalTimeoutTimer) - vbto += 1; - } - temp_ctl |= (vbto << 28); - - if (vmeArb->arbiterMode == VME_PRIORITY_MODE) - temp_ctl |= 1 << 26; - - if (vmeArb->arbiterTimeoutFlag) - temp_ctl |= 2 << 24; - - iowrite32(temp_ctl, bridge->base + MISC_CTL); - return 0; -} - -int ca91cx42_get_arbiter(vmeArbiterCfg_t *vmeArb) -{ - int temp_ctl = 0; - int vbto = 0; - - temp_ctl = ioread32(bridge->base + MISC_CTL); - - vbto = (temp_ctl >> 28) & 0xF; - if (vbto != 0) - vmeArb->globalTimeoutTimer = (16 * (1 << (vbto - 1))); - - if (temp_ctl & (1 << 26)) - vmeArb->arbiterMode = VME_PRIORITY_MODE; - else - vmeArb->arbiterMode = VME_R_ROBIN_MODE; - - if (temp_ctl & (3 << 24)) - vmeArb->arbiterTimeoutFlag = 1; - - return 0; -} - -int ca91cx42_set_requestor(vmeRequesterCfg_t *vmeReq) -{ - int temp_ctl = 0; - - temp_ctl = ioread32(bridge->base + MAST_CTL); - temp_ctl &= 0xFF0FFFFF; - - if (vmeReq->releaseMode == 1) - temp_ctl |= (1 << 20); - - if (vmeReq->fairMode == 1) - temp_ctl |= (1 << 21); - - temp_ctl |= (vmeReq->requestLevel << 22); - - iowrite32(temp_ctl, bridge->base + MAST_CTL); - return 0; -} - -int ca91cx42_get_requestor(vmeRequesterCfg_t *vmeReq) -{ - int temp_ctl = 0; - - temp_ctl = ioread32(bridge->base + MAST_CTL); - - if (temp_ctl & (1 << 20)) - vmeReq->releaseMode = 1; - - if (temp_ctl & (1 << 21)) - vmeReq->fairMode = 1; - - vmeReq->requestLevel = (temp_ctl & 0xC00000) >> 22; - - return 0; -} - - -#endif diff --git a/drivers/staging/vme/bridges/vme_tsi148.c b/drivers/staging/vme/bridges/vme_tsi148.c index a6f853a3dc24..faf652edb70f 100644 --- a/drivers/staging/vme/bridges/vme_tsi148.c +++ b/drivers/staging/vme/bridges/vme_tsi148.c @@ -571,16 +571,6 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, bridge = image->parent->driver_priv; -#if 0 - printk("Set slave image %d to:\n", image->number); - printk("\tEnabled: %s\n", (enabled == 1)? "yes" : "no"); - printk("\tVME Base:0x%llx\n", vme_base); - printk("\tWindow Size:0x%llx\n", size); - printk("\tPCI Base:0x%lx\n", (unsigned long)pci_base); - printk("\tAddress Space:0x%x\n", aspace); - printk("\tTransfer Cycle Properties:0x%x\n", cycle); -#endif - i = image->number; switch (aspace) { @@ -636,11 +626,6 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, return -EINVAL; } -#if 0 - printk("\tVME Bound:0x%llx\n", vme_bound); - printk("\tPCI Offset:0x%llx\n", pci_offset); -#endif - /* Disable while we are mucking around */ temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITAT); @@ -662,23 +647,6 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] + TSI148_LCSR_OFFSET_ITOFL); -/* XXX Prefetch stuff currently unsupported */ -#if 0 - - for (x = 0; x < 4; x++) { - if ((64 << x) >= vmeIn->prefetchSize) { - break; - } - } - if (x == 4) - x--; - temp_ctl |= (x << 16); - - if (vmeIn->prefetchThreshold) - if (vmeIn->prefetchThreshold) - temp_ctl |= 0x40000; -#endif - /* Setup 2eSST speeds */ temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M; switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { @@ -735,8 +703,6 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, /* * Get slave window configuration. - * - * XXX Prefetch currently unsupported. */ int tsi148_slave_get(struct vme_slave_resource *image, int *enabled, unsigned long long *vme_base, unsigned long long *size, @@ -1030,20 +996,6 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); -/* XXX Prefetch stuff currently unsupported */ -#if 0 - if (vmeOut->prefetchEnable) { - temp_ctl |= 0x40000; - for (x = 0; x < 4; x++) { - if ((2 << x) >= vmeOut->prefetchSize) - break; - } - if (x == 4) - x = 3; - temp_ctl |= (x << 16); - } -#endif - /* Setup 2eSST speeds */ temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M; switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { @@ -1156,12 +1108,6 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTOFL); -/* XXX We need to deal with OTBS */ -#if 0 - iowrite32be(vmeOut->bcastSelect2esst, bridge->base + - TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTBS); -#endif - /* Write ctl reg without enable */ iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTAT); @@ -1669,8 +1615,6 @@ static int tsi148_dma_set_vme_dest_attributes(u32 *attr, vme_address_t aspace, /* * Add a link list descriptor to the list - * - * XXX Need to handle 2eSST Broadcast select bits */ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count) @@ -1683,7 +1627,7 @@ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src, dma_addr_t desc_ptr; int retval = 0; - /* XXX descriptor must be aligned on 64-bit boundaries */ + /* Descriptor must be aligned on 64-bit boundaries */ entry = (struct tsi148_dma_entry *)kmalloc( sizeof(struct tsi148_dma_entry), GFP_KERNEL); if (entry == NULL) { @@ -1850,9 +1794,6 @@ int tsi148_dma_list_exec(struct vme_dma_list *list) dma_addr_t bus_addr; u32 bus_addr_high, bus_addr_low; u32 val, dctlreg = 0; -#if 0 - int x; -#endif struct tsi148_driver *bridge; ctrlr = list->parent; @@ -1875,48 +1816,6 @@ int tsi148_dma_list_exec(struct vme_dma_list *list) } else { list_add(&(list->list), &(ctrlr->running)); } -#if 0 - /* XXX Still todo */ - for (x = 0; x < 8; x++) { /* vme block size */ - if ((32 << x) >= vmeDma->maxVmeBlockSize) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 12); - - for (x = 0; x < 8; x++) { /* pci block size */ - if ((32 << x) >= vmeDma->maxPciBlockSize) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 4); - - if (vmeDma->vmeBackOffTimer) { - for (x = 1; x < 8; x++) { /* vme timer */ - if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 8); - } - - if (vmeDma->pciBackOffTimer) { - for (x = 1; x < 8; x++) { /* pci timer */ - if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 0); - } -#endif /* Get first bus address and write into registers */ entry = list_first_entry(&(list->entries), struct tsi148_dma_entry, @@ -2738,251 +2637,3 @@ MODULE_LICENSE("GPL"); module_init(tsi148_init); module_exit(tsi148_exit); - -/*---------------------------------------------------------------------------- - * STAGING - *--------------------------------------------------------------------------*/ - -#if 0 -/* - * Direct Mode DMA transfer - * - * XXX Not looking at direct mode for now, we can always use link list mode - * with a single entry. - */ -int tsi148_dma_run(struct vme_dma_resource *resource, struct vme_dma_attr src, - struct vme_dma_attr dest, size_t count) -{ - u32 dctlreg = 0; - unsigned int tmp; - int val; - int channel, x; - struct vmeDmaPacket *cur_dma; - struct tsi148_dma_descriptor *dmaLL; - - /* direct mode */ - dctlreg = 0x800000; - - for (x = 0; x < 8; x++) { /* vme block size */ - if ((32 << x) >= vmeDma->maxVmeBlockSize) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 12); - - for (x = 0; x < 8; x++) { /* pci block size */ - if ((32 << x) >= vmeDma->maxPciBlockSize) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 4); - - if (vmeDma->vmeBackOffTimer) { - for (x = 1; x < 8; x++) { /* vme timer */ - if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 8); - } - - if (vmeDma->pciBackOffTimer) { - for (x = 1; x < 8; x++) { /* pci timer */ - if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) { - break; - } - } - if (x == 8) - x = 7; - dctlreg |= (x << 0); - } - - /* Program registers for DMA transfer */ - iowrite32be(dmaLL->dsau, tsi148_bridge->driver_priv->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAU); - iowrite32be(dmaLL->dsal, tsi148_bridge->driver_priv->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAL); - iowrite32be(dmaLL->ddau, tsi148_bridge->driver_priv->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAU); - iowrite32be(dmaLL->ddal, tsi148_bridge->driver_priv->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAL); - iowrite32be(dmaLL->dsat, tsi148_bridge->driver_priv->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAT); - iowrite32be(dmaLL->ddat, tsi148_bridge->driver_priv->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAT); - iowrite32be(dmaLL->dcnt, tsi148_bridge->driver_priv->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCNT); - iowrite32be(dmaLL->ddbs, tsi148_bridge->driver_priv->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDBS); - - /* Start the operation */ - iowrite32be(dctlreg | 0x2000000, tsi148_bridge->driver_priv->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL); - - tmp = ioread32be(tsi148_bridge->driver_priv->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSTA); - wait_event_interruptible(dma_queue[channel], (tmp & 0x1000000) == 0); - - /* - * Read status register, we should probably do this in some error - * handler rather than here so that we can be sure we haven't kicked off - * another DMA transfer. - */ - val = ioread32be(tsi148_bridge->driver_priv->base + - TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSTA); - - vmeDma->vmeDmaStatus = 0; - if (val & 0x10000000) { - printk(KERN_ERR - "DMA Error in DMA_tempe_irqhandler DSTA=%08X\n", - val); - vmeDma->vmeDmaStatus = val; - - } - return (0); -} -#endif - -#if 0 - -/* Global VME controller information */ -struct pci_dev *vme_pci_dev; - -/* - * Set the VME bus arbiter with the requested attributes - */ -int tempe_set_arbiter(vmeArbiterCfg_t * vmeArb) -{ - int temp_ctl = 0; - int gto = 0; - - temp_ctl = ioread32be(tsi148_bridge->driver_priv->base + - TSI148_LCSR_VCTRL); - temp_ctl &= 0xFFEFFF00; - - if (vmeArb->globalTimeoutTimer == 0xFFFFFFFF) { - gto = 8; - } else if (vmeArb->globalTimeoutTimer > 2048) { - return (-EINVAL); - } else if (vmeArb->globalTimeoutTimer == 0) { - gto = 0; - } else { - gto = 1; - while ((16 * (1 << (gto - 1))) < vmeArb->globalTimeoutTimer) { - gto += 1; - } - } - temp_ctl |= gto; - - if (vmeArb->arbiterMode != VME_PRIORITY_MODE) { - temp_ctl |= 1 << 6; - } - - if (vmeArb->arbiterTimeoutFlag) { - temp_ctl |= 1 << 7; - } - - if (vmeArb->noEarlyReleaseFlag) { - temp_ctl |= 1 << 20; - } - iowrite32be(temp_ctl, tsi148_bridge->driver_priv->base + - TSI148_LCSR_VCTRL); - - return (0); -} - -/* - * Return the attributes of the VME bus arbiter. - */ -int tempe_get_arbiter(vmeArbiterCfg_t * vmeArb) -{ - int temp_ctl = 0; - int gto = 0; - - - temp_ctl = ioread32be(tsi148_bridge->driver_priv->base + - TSI148_LCSR_VCTRL); - - gto = temp_ctl & 0xF; - if (gto != 0) { - vmeArb->globalTimeoutTimer = (16 * (1 << (gto - 1))); - } - - if (temp_ctl & (1 << 6)) { - vmeArb->arbiterMode = VME_R_ROBIN_MODE; - } else { - vmeArb->arbiterMode = VME_PRIORITY_MODE; - } - - if (temp_ctl & (1 << 7)) { - vmeArb->arbiterTimeoutFlag = 1; - } - - if (temp_ctl & (1 << 20)) { - vmeArb->noEarlyReleaseFlag = 1; - } - - return (0); -} - -/* - * Set the VME bus requestor with the requested attributes - */ -int tempe_set_requestor(vmeRequesterCfg_t * vmeReq) -{ - int temp_ctl = 0; - - temp_ctl = ioread32be(tsi148_bridge->driver_priv->base + - TSI148_LCSR_VMCTRL); - temp_ctl &= 0xFFFF0000; - - if (vmeReq->releaseMode == 1) { - temp_ctl |= (1 << 3); - } - - if (vmeReq->fairMode == 1) { - temp_ctl |= (1 << 2); - } - - temp_ctl |= (vmeReq->timeonTimeoutTimer & 7) << 8; - temp_ctl |= (vmeReq->timeoffTimeoutTimer & 7) << 12; - temp_ctl |= vmeReq->requestLevel; - - iowrite32be(temp_ctl, tsi148_bridge->driver_priv->base + - TSI148_LCSR_VMCTRL); - return (0); -} - -/* - * Return the attributes of the VME bus requestor - */ -int tempe_get_requestor(vmeRequesterCfg_t * vmeReq) -{ - int temp_ctl = 0; - - temp_ctl = ioread32be(tsi148_bridge->driver_priv->base + - TSI148_LCSR_VMCTRL); - - if (temp_ctl & 0x18) { - vmeReq->releaseMode = 1; - } - - if (temp_ctl & (1 << 2)) { - vmeReq->fairMode = 1; - } - - vmeReq->requestLevel = temp_ctl & 3; - vmeReq->timeonTimeoutTimer = (temp_ctl >> 8) & 7; - vmeReq->timeoffTimeoutTimer = (temp_ctl >> 12) & 7; - - return (0); -} - - -#endif diff --git a/drivers/staging/vme/vme.c b/drivers/staging/vme/vme.c index ea2eee3f0834..d6d84ebeeec0 100644 --- a/drivers/staging/vme/vme.c +++ b/drivers/staging/vme/vme.c @@ -825,8 +825,6 @@ struct vme_dma_attr *vme_dma_vme_attribute(unsigned long long address, struct vme_dma_attr *attributes; struct vme_dma_vme *vme_attr; - /* XXX Run some sanity checks here */ - attributes = kmalloc( sizeof(struct vme_dma_attr), GFP_KERNEL); if (attributes == NULL) { @@ -1191,8 +1189,6 @@ int vme_lm_set(struct vme_resource *resource, unsigned long long lm_base, return -EINVAL; } - /* XXX Check parameters */ - return bridge->lm_set(lm, lm_base, aspace, cycle); } EXPORT_SYMBOL(vme_lm_set); diff --git a/drivers/staging/vme/vme_bridge.h b/drivers/staging/vme/vme_bridge.h index a2cfc1014726..b653ec02e1fc 100644 --- a/drivers/staging/vme/vme_bridge.h +++ b/drivers/staging/vme/vme_bridge.h @@ -165,16 +165,6 @@ struct vme_bridge { /* CR/CSR space functions */ int (*slot_get) (struct vme_bridge *); - /* Use standard master read and write functions to access CR/CSR */ - -#if 0 - int (*set_prefetch) (void); - int (*get_prefetch) (void); - int (*set_arbiter) (void); - int (*get_arbiter) (void); - int (*set_requestor) (void); - int (*get_requestor) (void); -#endif }; void vme_irq_handler(struct vme_bridge *, int, int); @@ -183,51 +173,3 @@ int vme_register_bridge(struct vme_bridge *); void vme_unregister_bridge(struct vme_bridge *); #endif /* _VME_BRIDGE_H_ */ - -#if 0 -/* - * VMEbus GET INFO Arg Structure - */ -struct vmeInfoCfg { - int vmeSlotNum; /* VME slot number of interest */ - int boardResponded; /* Board responded */ - char sysConFlag; /* System controller flag */ - int vmeControllerID; /* Vendor/device ID of VME bridge */ - int vmeControllerRev; /* Revision of VME bridge */ - char osName[8]; /* Name of OS e.g. "Linux" */ - int vmeSharedDataValid; /* Validity of data struct */ - int vmeDriverRev; /* Revision of VME driver */ - unsigned int vmeAddrHi[8]; /* Address on VME bus */ - unsigned int vmeAddrLo[8]; /* Address on VME bus */ - unsigned int vmeSize[8]; /* Size on VME bus */ - unsigned int vmeAm[8]; /* Address modifier on VME bus */ - int reserved; /* For future use */ -}; -typedef struct vmeInfoCfg vmeInfoCfg_t; - -/* - * VMEbus Requester Arg Structure - */ -struct vmeRequesterCfg { - int requestLevel; /* Requester Bus Request Level */ - char fairMode; /* Requester Fairness Mode Indicator */ - int releaseMode; /* Requester Bus Release Mode */ - int timeonTimeoutTimer; /* Master Time-on Time-out Timer */ - int timeoffTimeoutTimer; /* Master Time-off Time-out Timer */ - int reserved; /* For future use */ -}; -typedef struct vmeRequesterCfg vmeRequesterCfg_t; - -/* - * VMEbus Arbiter Arg Structure - */ -struct vmeArbiterCfg { - vme_arbitration_t arbiterMode; /* Arbitration Scheduling Algorithm */ - char arbiterTimeoutFlag; /* Arbiter Time-out Timer Indicator */ - int globalTimeoutTimer; /* VMEbus Global Time-out Timer */ - char noEarlyReleaseFlag; /* No Early Release on BBUSY */ - int reserved; /* For future use */ -}; -typedef struct vmeArbiterCfg vmeArbiterCfg_t; - -#endif -- cgit v1.2.3 From 877de4b4866f1cc0a25a4d67d3927304556f5d1f Mon Sep 17 00:00:00 2001 From: Arthur Benilov Date: Tue, 16 Feb 2010 15:40:30 +0100 Subject: Staging: vme: llseek support in user driver Provide vme_user_llseek() implementation. Signed-off-by: Arthur Benilov Signed-off-by: Vincent Bossier Acked-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/devices/vme_user.c | 35 ++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/vme/devices/vme_user.c b/drivers/staging/vme/devices/vme_user.c index 48d46cadb13f..ddecbe5105b9 100644 --- a/drivers/staging/vme/devices/vme_user.c +++ b/drivers/staging/vme/devices/vme_user.c @@ -400,8 +400,39 @@ static ssize_t vme_user_write(struct file *file, const char *buf, size_t count, static loff_t vme_user_llseek(struct file *file, loff_t off, int whence) { - printk(KERN_ERR "Llseek currently incomplete\n"); - return -EINVAL; + loff_t absolute = -1; + unsigned int minor = MINOR(file->f_dentry->d_inode->i_rdev); + size_t image_size; + + down(&image[minor].sem); + image_size = vme_get_size(image[minor].resource); + + switch (whence) { + case SEEK_SET: + absolute = off; + break; + case SEEK_CUR: + absolute = file->f_pos + off; + break; + case SEEK_END: + absolute = image_size + off; + break; + default: + up(&image[minor].sem); + return -EINVAL; + break; + } + + if ((absolute < 0) || (absolute >= image_size)) { + up(&image[minor].sem); + return -EINVAL; + } + + file->f_pos = absolute; + + up(&image[minor].sem); + + return absolute; } /* -- cgit v1.2.3 From 5188d74cc4597a63a0907b8996ca0a2d36f1b970 Mon Sep 17 00:00:00 2001 From: Arthur Benilov Date: Tue, 16 Feb 2010 15:40:58 +0100 Subject: Staging: vme: Use A24 when requesting slave resource When requesting slave resources A16 addressing mode flag is used to find available windows. Since the ca91cx42 bridge only supports two A16 slave windows but four are requested, the driver fails to initialize. The flag has been changed to A24, which is supported by all slave windows. Signed-off-by: Arthur Benilov Signed-off-by: Vincent Bossier Acked-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/devices/vme_user.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/vme/devices/vme_user.c b/drivers/staging/vme/devices/vme_user.c index ddecbe5105b9..0d404f1a27f4 100644 --- a/drivers/staging/vme/devices/vme_user.c +++ b/drivers/staging/vme/devices/vme_user.c @@ -701,8 +701,12 @@ static int __init vme_user_probe(struct device *dev, int cur_bus, int cur_slot) /* Request slave resources and allocate buffers (128kB wide) */ for (i = SLAVE_MINOR; i < (SLAVE_MAX + 1); i++) { /* XXX Need to properly request attributes */ + /* For ca91cx42 bridge there are only two slave windows + * supporting A16 addressing, so we request A24 supported + * by all windows. + */ image[i].resource = vme_slave_request(vme_user_bridge, - VME_A16, VME_SCT); + VME_A24, VME_SCT); if (image[i].resource == NULL) { printk(KERN_WARNING "Unable to allocate slave " "resource\n"); -- cgit v1.2.3 From 33e920d9ebaddbc9cf51cf6e1de7baa8d7b8d6dd Mon Sep 17 00:00:00 2001 From: Arthur Benilov Date: Tue, 16 Feb 2010 15:41:21 +0100 Subject: Staging: vme: Allocate memory buffers for master windows For VME device I/O operations on master windows the user driver tends to use kern_buf buffer array which is not allocated. This causes an error when reading from master window device files. Signed-off-by: Arthur Benilov Signed-off-by: Vincent Bossier Acked-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/devices/vme_user.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/vme/devices/vme_user.c b/drivers/staging/vme/devices/vme_user.c index 0d404f1a27f4..c60c80fb241d 100644 --- a/drivers/staging/vme/devices/vme_user.c +++ b/drivers/staging/vme/devices/vme_user.c @@ -738,6 +738,14 @@ static int __init vme_user_probe(struct device *dev, int cur_bus, int cur_slot) "resource\n"); goto err_master; } + image[i].size_buf = PCI_BUF_SIZE; + image[i].kern_buf = kmalloc(image[i].size_buf, GFP_KERNEL); + if (image[i].kern_buf == NULL) { + printk(KERN_WARNING "Unable to allocate memory for " + "master window buffers\n"); + err = -ENOMEM; + goto err_master_buf; + } } /* Create sysfs entries - on udev systems this creates the dev files */ @@ -791,6 +799,9 @@ err_sysfs: /* Ensure counter set correcty to unalloc all master windows */ i = MASTER_MAX + 1; +err_master_buf: + for (i = MASTER_MINOR; i < (MASTER_MAX + 1); i++) + kfree(image[i].kern_buf); err_master: while (i > MASTER_MINOR) { i--; @@ -826,6 +837,9 @@ static int __exit vme_user_remove(struct device *dev, int cur_bus, int cur_slot) } class_destroy(vme_user_sysfs_class); + for (i = MASTER_MINOR; i < (MASTER_MAX + 1); i++) + kfree(image[i].kern_buf); + for (i = SLAVE_MINOR; i < (SLAVE_MAX + 1); i++) { vme_slave_set(image[i].resource, 0, 0, 0, 0, VME_A32, 0); vme_slave_free(image[i].resource); -- cgit v1.2.3 From 3c2aabc41da7e9f957bc826363115a54764fb396 Mon Sep 17 00:00:00 2001 From: Arthur Benilov Date: Tue, 16 Feb 2010 15:41:51 +0100 Subject: Staging: vme: VMIVME-7805 board support VMIVME-7805 board has a special control register that has to be used in order to activate the VME bus access via the Universe II bridge. This control register also handles endianess convertion. Signed-off-by: Arthur Benilov Signed-off-by: Vincent Bossier Acked-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/staging/vme/Kconfig | 2 + drivers/staging/vme/Makefile | 1 + drivers/staging/vme/boards/Kconfig | 9 ++ drivers/staging/vme/boards/Makefile | 5 ++ drivers/staging/vme/boards/vme_vmivme7805.c | 124 ++++++++++++++++++++++++++++ drivers/staging/vme/boards/vme_vmivme7805.h | 37 +++++++++ 6 files changed, 178 insertions(+) create mode 100644 drivers/staging/vme/boards/Kconfig create mode 100644 drivers/staging/vme/boards/Makefile create mode 100644 drivers/staging/vme/boards/vme_vmivme7805.c create mode 100644 drivers/staging/vme/boards/vme_vmivme7805.h (limited to 'drivers') diff --git a/drivers/staging/vme/Kconfig b/drivers/staging/vme/Kconfig index ae628a58b0c6..6411ae51ed3f 100644 --- a/drivers/staging/vme/Kconfig +++ b/drivers/staging/vme/Kconfig @@ -14,4 +14,6 @@ source "drivers/staging/vme/bridges/Kconfig" source "drivers/staging/vme/devices/Kconfig" +source "drivers/staging/vme/boards/Kconfig" + endif # VME diff --git a/drivers/staging/vme/Makefile b/drivers/staging/vme/Makefile index 8c3b90ee5853..b4ea3f8d0a50 100644 --- a/drivers/staging/vme/Makefile +++ b/drivers/staging/vme/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_VME_BUS) += vme.o obj-y += bridges/ obj-y += devices/ +obj-y += boards/ diff --git a/drivers/staging/vme/boards/Kconfig b/drivers/staging/vme/boards/Kconfig new file mode 100644 index 000000000000..761631353527 --- /dev/null +++ b/drivers/staging/vme/boards/Kconfig @@ -0,0 +1,9 @@ +comment "VME Board Drivers" + +config VMIVME_7805 + tristate "VMIVME-7805" + help + If you say Y here you get support for the VMIVME-7805 board. + This board has an additional control interface to the Universe II + chip. This driver has to be included if you want to access VME bus + with VMIVME-7805 board. diff --git a/drivers/staging/vme/boards/Makefile b/drivers/staging/vme/boards/Makefile new file mode 100644 index 000000000000..43658340885d --- /dev/null +++ b/drivers/staging/vme/boards/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the VME board drivers. +# + +obj-$(CONFIG_VMIVME_7805) += vme_vmivme7805.o diff --git a/drivers/staging/vme/boards/vme_vmivme7805.c b/drivers/staging/vme/boards/vme_vmivme7805.c new file mode 100644 index 000000000000..843c9edde555 --- /dev/null +++ b/drivers/staging/vme/boards/vme_vmivme7805.c @@ -0,0 +1,124 @@ +/* + * Support for the VMIVME-7805 board access to the Universe II bridge. + * + * Author: Arthur Benilov + * Copyright 2010 Ion Beam Application, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "vme_vmivme7805.h" + +static int __init vmic_init(void); +static int vmic_probe(struct pci_dev *, const struct pci_device_id *); +static void vmic_remove(struct pci_dev *); +static void __exit vmic_exit(void); + +/** Base address to access FPGA register */ +static void *vmic_base; + +static char driver_name[] = "vmivme_7805"; + +static struct pci_device_id vmic_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_VMIC, PCI_DEVICE_ID_VTIMR) }, + { }, +}; + +static struct pci_driver vmic_driver = { + .name = driver_name, + .id_table = vmic_ids, + .probe = vmic_probe, + .remove = vmic_remove, +}; + +static int __init vmic_init(void) +{ + return pci_register_driver(&vmic_driver); +} + +static int vmic_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + int retval; + u32 data; + + /* Enable the device */ + retval = pci_enable_device(pdev); + if (retval) { + dev_err(&pdev->dev, "Unable to enable device\n"); + goto err; + } + + /* Map Registers */ + retval = pci_request_regions(pdev, driver_name); + if (retval) { + dev_err(&pdev->dev, "Unable to reserve resources\n"); + goto err_resource; + } + + /* Map registers in BAR 0 */ + vmic_base = ioremap_nocache(pci_resource_start(pdev, 0), 16); + if (!vmic_base) { + dev_err(&pdev->dev, "Unable to remap CRG region\n"); + retval = -EIO; + goto err_remap; + } + + /* Clear the FPGA VME IF contents */ + iowrite32(0, vmic_base + VME_CONTROL); + + /* Clear any initial BERR */ + data = ioread32(vmic_base + VME_CONTROL) & 0x00000FFF; + data |= BM_VME_CONTROL_BERRST; + iowrite32(data, vmic_base + VME_CONTROL); + + /* Enable the vme interface and byte swapping */ + data = ioread32(vmic_base + VME_CONTROL) & 0x00000FFF; + data = data | BM_VME_CONTROL_MASTER_ENDIAN | + BM_VME_CONTROL_SLAVE_ENDIAN | + BM_VME_CONTROL_ABLE | + BM_VME_CONTROL_BERRI | + BM_VME_CONTROL_BPENA | + BM_VME_CONTROL_VBENA; + iowrite32(data, vmic_base + VME_CONTROL); + + return 0; + +err_remap: + pci_release_regions(pdev); +err_resource: + pci_disable_device(pdev); +err: + return retval; +} + +static void vmic_remove(struct pci_dev *pdev) +{ + iounmap(vmic_base); + pci_release_regions(pdev); + pci_disable_device(pdev); + +} + +static void __exit vmic_exit(void) +{ + pci_unregister_driver(&vmic_driver); +} + +MODULE_DESCRIPTION("VMIVME-7805 board support driver"); +MODULE_AUTHOR("Arthur Benilov "); +MODULE_LICENSE("GPL"); + +module_init(vmic_init); +module_exit(vmic_exit); + diff --git a/drivers/staging/vme/boards/vme_vmivme7805.h b/drivers/staging/vme/boards/vme_vmivme7805.h new file mode 100644 index 000000000000..44c2c449808c --- /dev/null +++ b/drivers/staging/vme/boards/vme_vmivme7805.h @@ -0,0 +1,37 @@ +/* + * vmivme_7805.h + * + * Support for the VMIVME-7805 board access to the Universe II bridge. + * + * Author: Arthur Benilov + * Copyright 2010 Ion Beam Application, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + + +#ifndef _VMIVME_7805_H +#define _VMIVME_7805_H + +#ifndef PCI_VENDOR_ID_VMIC +#define PCI_VENDOR_ID_VMIC 0x114A +#endif + +#ifndef PCI_DEVICE_ID_VTIMR +#define PCI_DEVICE_ID_VTIMR 0x0004 +#endif + +#define VME_CONTROL 0x0000 +#define BM_VME_CONTROL_MASTER_ENDIAN 0x0001 +#define BM_VME_CONTROL_SLAVE_ENDIAN 0x0002 +#define BM_VME_CONTROL_ABLE 0x0004 +#define BM_VME_CONTROL_BERRI 0x0040 +#define BM_VME_CONTROL_BERRST 0x0080 +#define BM_VME_CONTROL_BPENA 0x0400 +#define BM_VME_CONTROL_VBENA 0x0800 + +#endif /* _VMIVME_7805_H */ + -- cgit v1.2.3 From 9a16a92c11e82a0a80b4847343cfb8b5c54ed6b6 Mon Sep 17 00:00:00 2001 From: Graham M Howe Date: Mon, 15 Feb 2010 10:04:26 +0000 Subject: Staging: comedi: fix brace and 80 character coding style issue in ni_daq_700.c This is a patch to the ni_daq_700.c file that fixes up brace and 80 character warnings found by the checkpatch.pl tool Signed-off-by: Graham M Howe Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_daq_700.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_daq_700.c b/drivers/staging/comedi/drivers/ni_daq_700.c index ef5e1183d47d..c9b0395a6103 100644 --- a/drivers/staging/comedi/drivers/ni_daq_700.c +++ b/drivers/staging/comedi/drivers/ni_daq_700.c @@ -76,13 +76,15 @@ struct dio700_board { static const struct dio700_board dio700_boards[] = { { .name = "daqcard-700", - .device_id = 0x4743, /* 0x10b is manufacturer id, 0x4743 is device id */ + /* 0x10b is manufacturer id, 0x4743 is device id */ + .device_id = 0x4743, .bustype = pcmcia_bustype, .have_dio = 1, }, { .name = "ni_daq_700", - .device_id = 0x4743, /* 0x10b is manufacturer id, 0x4743 is device id */ + /* 0x10b is manufacturer id, 0x4743 is device id */ + .device_id = 0x4743, .bustype = pcmcia_bustype, .have_dio = 1, }, @@ -309,11 +311,11 @@ int subdev_700_init(struct comedi_device *dev, struct comedi_subdevice *s, return -ENOMEM; CALLBACK_ARG = arg; - if (cb == NULL) { + if (cb == NULL) CALLBACK_FUNC = subdev_700_cb; - } else { + else CALLBACK_FUNC = cb; - } + s->insn_bits = subdev_700_insn; s->insn_config = subdev_700_insn_config; @@ -345,12 +347,10 @@ int subdev_700_init_irq(struct comedi_device *dev, struct comedi_subdevice *s, void subdev_700_cleanup(struct comedi_device *dev, struct comedi_subdevice *s) { - if (s->private) { - if (subdevpriv->have_irq) { - } + if (s->private) + if (subdevpriv->have_irq) - kfree(s->private); - } + kfree(s->private); } EXPORT_SYMBOL(subdev_700_init); @@ -390,9 +390,9 @@ static int dio700_attach(struct comedi_device *dev, struct comedi_devconfig *it) printk("comedi%d: ni_daq_700: %s, io 0x%lx", dev->minor, thisboard->name, iobase); #ifdef incomplete - if (irq) { + if (irq) printk(", irq %u", irq); - } + #endif printk("\n"); -- cgit v1.2.3 From 77712e5fbe2e47476823f4853d756cc5ad1dfabc Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 18 Feb 2010 17:19:17 +0000 Subject: Staging: iio: Staticise non-exported functions Staticise a number of functions which aren't exported outside their source files, and also add a __user annotation for the buffer in iio_event_chrdev_read(). Signed-off-by: Mark Brown Acked-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/staging/iio/industrialio-core.c | 14 +++++++------- drivers/staging/iio/trigger_consumer.h | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/iio/industrialio-core.c b/drivers/staging/iio/industrialio-core.c index 4ff683a3df31..b456dfc8fe27 100644 --- a/drivers/staging/iio/industrialio-core.c +++ b/drivers/staging/iio/industrialio-core.c @@ -118,7 +118,7 @@ int iio_push_event(struct iio_dev *dev_info, EXPORT_SYMBOL(iio_push_event); /* Generic interrupt line interrupt handler */ -irqreturn_t iio_interrupt_handler(int irq, void *_int_info) +static irqreturn_t iio_interrupt_handler(int irq, void *_int_info) { struct iio_interrupt *int_info = _int_info; struct iio_dev *dev_info = int_info->dev_info; @@ -252,10 +252,10 @@ void iio_remove_event_from_list(struct iio_event_handler_list *el, } EXPORT_SYMBOL(iio_remove_event_from_list); -ssize_t iio_event_chrdev_read(struct file *filep, - char *buf, - size_t count, - loff_t *f_ps) +static ssize_t iio_event_chrdev_read(struct file *filep, + char __user *buf, + size_t count, + loff_t *f_ps) { struct iio_event_interface *ev_int = filep->private_data; struct iio_detected_event_list *el; @@ -313,7 +313,7 @@ error_ret: return ret; } -int iio_event_chrdev_release(struct inode *inode, struct file *filep) +static int iio_event_chrdev_release(struct inode *inode, struct file *filep) { struct iio_handler *hand = iio_cdev_to_handler(inode->i_cdev); struct iio_event_interface *ev_int = hand->private; @@ -335,7 +335,7 @@ int iio_event_chrdev_release(struct inode *inode, struct file *filep) return 0; } -int iio_event_chrdev_open(struct inode *inode, struct file *filep) +static int iio_event_chrdev_open(struct inode *inode, struct file *filep) { struct iio_handler *hand = iio_cdev_to_handler(inode->i_cdev); struct iio_event_interface *ev_int = hand->private; diff --git a/drivers/staging/iio/trigger_consumer.h b/drivers/staging/iio/trigger_consumer.h index a02d70b0d24a..9d52d9637777 100644 --- a/drivers/staging/iio/trigger_consumer.h +++ b/drivers/staging/iio/trigger_consumer.h @@ -27,7 +27,7 @@ int iio_device_unregister_trigger_consumer(struct iio_dev *dev_info); * iio_device_register_trigger_consumer() - set up an iio_dev to use triggers * @dev_info: iio_dev associated with the device that will consume the trigger **/ -int iio_device_register_trigger_consumer(struct iio_dev *dev_info) +static int iio_device_register_trigger_consumer(struct iio_dev *dev_info) { return 0; }; @@ -36,7 +36,7 @@ int iio_device_register_trigger_consumer(struct iio_dev *dev_info) * iio_device_unregister_trigger_consumer() - reverse the registration process * @dev_info: iio_dev associated with the device that consumed the trigger **/ -int iio_device_unregister_trigger_consumer(struct iio_dev *dev_info) +static int iio_device_unregister_trigger_consumer(struct iio_dev *dev_info) { return 0; }; -- cgit v1.2.3 From 0fce64362d4f2144586e3ffcff6f259bf8abc2f8 Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Fri, 19 Feb 2010 16:18:04 +0100 Subject: Staging: batman-adv: depend on NET instead of PACKET in Kconfig The code which uses the raw packet sockets was removed. The only related dependencies are the skb and netdev handling code. This is provided by NET in Kconfig. Signed-off-by: Sven Eckelmann Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/Kconfig b/drivers/staging/batman-adv/Kconfig index 69e8fb039be0..1e7e0a8dbc8b 100644 --- a/drivers/staging/batman-adv/Kconfig +++ b/drivers/staging/batman-adv/Kconfig @@ -4,7 +4,7 @@ config BATMAN_ADV tristate "B.A.T.M.A.N. Advanced Meshing Protocol" - depends on PROC_FS && PACKET + depends on PROC_FS && NET default n ---help--- -- cgit v1.2.3 From eb50081d8fb76d5de9d65628d7f41977ece7044b Mon Sep 17 00:00:00 2001 From: Simon Wunderlich Date: Fri, 19 Feb 2010 16:18:05 +0100 Subject: Staging: batman-adv: don't lock while sending packets As in other parts of batman-adv, we should not lock while sending a packet but keep the lock held for as short as possible. Additionally, we should check whether the interface is active, otherwise batman_if->net_dev might not be available ... Signed-off-by: Simon Wunderlich Acked-by: Marek Lindner Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/device.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/device.c b/drivers/staging/batman-adv/device.c index a3e74296abfd..451898cd9ecb 100644 --- a/drivers/staging/batman-adv/device.c +++ b/drivers/staging/batman-adv/device.c @@ -25,6 +25,7 @@ #include "send.h" #include "types.h" #include "hash.h" +#include "hard-interface.h" static struct class *batman_class; @@ -206,6 +207,7 @@ ssize_t bat_device_write(struct file *file, const char __user *buff, struct icmp_packet icmp_packet; struct orig_node *orig_node; struct batman_if *batman_if; + uint8_t dstaddr[ETH_ALEN]; unsigned long flags; if (len < sizeof(struct icmp_packet)) { @@ -251,9 +253,15 @@ ssize_t bat_device_write(struct file *file, const char __user *buff, goto unlock; batman_if = orig_node->batman_if; + memcpy(dstaddr, orig_node->router->addr, ETH_ALEN); + + spin_unlock_irqrestore(&orig_hash_lock, flags); if (!batman_if) - goto unlock; + goto dst_unreach; + + if (batman_if->if_active != IF_ACTIVE) + goto dst_unreach; memcpy(icmp_packet.orig, batman_if->net_dev->dev_addr, @@ -261,9 +269,8 @@ ssize_t bat_device_write(struct file *file, const char __user *buff, send_raw_packet((unsigned char *)&icmp_packet, sizeof(struct icmp_packet), - batman_if, orig_node->router->addr); + batman_if, dstaddr); - spin_unlock_irqrestore(&orig_hash_lock, flags); goto out; unlock: -- cgit v1.2.3 From 149de2e58b53cb87c9637a46441c477f0caf74bd Mon Sep 17 00:00:00 2001 From: Marek Lindner Date: Fri, 19 Feb 2010 16:18:06 +0100 Subject: Staging: batman-adv: avoid having the same error message more than once The routing code has 2 sections which warn about ttl exceeded. The corresponding warnings were identical which makes it hard to debug. In addition, batman-adv does not need to warn about ttl exceeded in case we encountered an echo request as this is commonly used to generate traceroute graphs. Signed-off-by: Marek Lindner Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/routing.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index 09917e57b41c..8abaa6193ac3 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -655,14 +655,15 @@ static int recv_icmp_ttl_exceeded(struct sk_buff *skb) unsigned long flags; uint8_t dstaddr[ETH_ALEN]; - icmp_packet = (struct icmp_packet *) skb->data; - ethhdr = (struct ethhdr *) skb_mac_header(skb); - - printk(KERN_WARNING "batman-adv:Warning - can't send packet from %pM to %pM: ttl exceeded\n", icmp_packet->orig, icmp_packet->dst); + icmp_packet = (struct icmp_packet *)skb->data; + ethhdr = (struct ethhdr *)skb_mac_header(skb); /* send TTL exceeded if packet is an echo request (traceroute) */ - if (icmp_packet->msg_type != ECHO_REQUEST) + if (icmp_packet->msg_type != ECHO_REQUEST) { + printk(KERN_WARNING "batman-adv:Warning - can't forward icmp packet from %pM to %pM: ttl exceeded\n", + icmp_packet->orig, icmp_packet->dst); return NET_RX_DROP; + } /* get routing information */ spin_lock_irqsave(&orig_hash_lock, flags); @@ -825,7 +826,8 @@ int recv_unicast_packet(struct sk_buff *skb) /* TTL exceeded */ if (unicast_packet->ttl < 2) { - printk(KERN_WARNING "batman-adv:Warning - can't send packet from %pM to %pM: ttl exceeded\n", ethhdr->h_source, unicast_packet->dest); + printk(KERN_WARNING "batman-adv:Warning - can't forward unicast packet from %pM to %pM: ttl exceeded\n", + ethhdr->h_source, unicast_packet->dest); return NET_RX_DROP; } -- cgit v1.2.3 From bc0ad071a788625abb23aee4cb3c07d17d501641 Mon Sep 17 00:00:00 2001 From: Marek Lindner Date: Fri, 19 Feb 2010 16:18:07 +0100 Subject: Staging: batman-adv: remove obsolete variables This patch removes a variable that became obsolete since the skb handling replaced the packet handling thread. Signed-off-by: Marek Lindner Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/routing.c | 2 -- drivers/staging/batman-adv/routing.h | 1 - 2 files changed, 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index 8abaa6193ac3..7dc9aef9bef4 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -35,8 +35,6 @@ DECLARE_WAIT_QUEUE_HEAD(thread_wait); -atomic_t exit_cond; - void slide_own_bcast_window(struct batman_if *batman_if) { HASHIT(hashit); diff --git a/drivers/staging/batman-adv/routing.h b/drivers/staging/batman-adv/routing.h index c217241d0efd..939b8d4f733c 100644 --- a/drivers/staging/batman-adv/routing.h +++ b/drivers/staging/batman-adv/routing.h @@ -22,7 +22,6 @@ #include "types.h" extern wait_queue_head_t thread_wait; -extern atomic_t exit_cond; void slide_own_bcast_window(struct batman_if *batman_if); void receive_bat_packet(struct ethhdr *ethhdr, -- cgit v1.2.3 From 837b8248f6206a6b08b3d6defe2946282e432679 Mon Sep 17 00:00:00 2001 From: Linus Luessing Date: Fri, 19 Feb 2010 16:18:08 +0100 Subject: Staging: batman-adv: atomic variable for vis-srv activation This fixes the bug discovered by Marek Lindner which did not allow turning on the vis-server before an interface has been added. With this patch we are using a global atomic variable for activating and deactiating the vis-server-mode, which can be used before inserting an interface. Signed-off-by: Linus Luessing Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/main.c | 2 ++ drivers/staging/batman-adv/main.h | 1 + drivers/staging/batman-adv/proc.c | 15 ++++++------- drivers/staging/batman-adv/send.c | 3 ++- drivers/staging/batman-adv/vis.c | 46 +++++---------------------------------- drivers/staging/batman-adv/vis.h | 2 -- 6 files changed, 18 insertions(+), 51 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/main.c b/drivers/staging/batman-adv/main.c index 3f780753a2bf..2e0b482e710a 100644 --- a/drivers/staging/batman-adv/main.c +++ b/drivers/staging/batman-adv/main.c @@ -43,6 +43,7 @@ DEFINE_SPINLOCK(forw_bcast_list_lock); atomic_t originator_interval; atomic_t vis_interval; +atomic_t vis_mode; atomic_t aggregation_enabled; int16_t num_hna; int16_t num_ifs; @@ -83,6 +84,7 @@ int init_module(void) atomic_set(&originator_interval, 1000); atomic_set(&vis_interval, 1000);/* TODO: raise this later, this is only * for debugging now. */ + atomic_set(&vis_mode, VIS_TYPE_CLIENT_UPDATE); atomic_set(&aggregation_enabled, 1); /* the name should not be longer than 10 chars - see diff --git a/drivers/staging/batman-adv/main.h b/drivers/staging/batman-adv/main.h index eb6a702c6444..deb41f5beda6 100644 --- a/drivers/staging/batman-adv/main.h +++ b/drivers/staging/batman-adv/main.h @@ -130,6 +130,7 @@ extern spinlock_t forw_bcast_list_lock; extern atomic_t originator_interval; extern atomic_t vis_interval; +extern atomic_t vis_mode; extern atomic_t aggregation_enabled; extern int16_t num_hna; extern int16_t num_ifs; diff --git a/drivers/staging/batman-adv/proc.c b/drivers/staging/batman-adv/proc.c index 68c36b097a07..0eadc6b48d75 100644 --- a/drivers/staging/batman-adv/proc.c +++ b/drivers/staging/batman-adv/proc.c @@ -338,11 +338,11 @@ static ssize_t proc_vis_srv_write(struct file *file, const char __user * buffer, if ((strcmp(vis_mode_string, "client") == 0) || (strcmp(vis_mode_string, "disabled") == 0)) { printk(KERN_INFO "batman-adv:Setting VIS mode to client (disabling vis server)\n"); - vis_set_mode(VIS_TYPE_CLIENT_UPDATE); + atomic_set(&vis_mode, VIS_TYPE_CLIENT_UPDATE); } else if ((strcmp(vis_mode_string, "server") == 0) || (strcmp(vis_mode_string, "enabled") == 0)) { printk(KERN_INFO "batman-adv:Setting VIS mode to server (enabling vis server)\n"); - vis_set_mode(VIS_TYPE_SERVER_SYNC); + atomic_set(&vis_mode, VIS_TYPE_SERVER_SYNC); } else printk(KERN_ERR "batman-adv:Unknown VIS mode: %s\n", vis_mode_string); @@ -353,12 +353,12 @@ static ssize_t proc_vis_srv_write(struct file *file, const char __user * buffer, static int proc_vis_srv_read(struct seq_file *seq, void *offset) { - int vis_server = is_vis_server(); + int vis_server = atomic_read(&vis_mode); seq_printf(seq, "[%c] client mode (server disabled) \n", - (!vis_server) ? 'x' : ' '); + (vis_server == VIS_TYPE_CLIENT_UPDATE) ? 'x' : ' '); seq_printf(seq, "[%c] server mode (server enabled) \n", - (vis_server) ? 'x' : ' '); + (vis_server == VIS_TYPE_SERVER_SYNC) ? 'x' : ' '); return 0; } @@ -377,9 +377,10 @@ static int proc_vis_data_read(struct seq_file *seq, void *offset) int i; char tmp_addr_str[ETH_STR_LEN]; unsigned long flags; + int vis_server = atomic_read(&vis_mode); rcu_read_lock(); - if (list_empty(&if_list) || (!is_vis_server())) { + if (list_empty(&if_list) || (vis_server == VIS_TYPE_CLIENT_UPDATE)) { rcu_read_unlock(); goto end; } @@ -672,5 +673,3 @@ int setup_procfs(void) return 0; } - - diff --git a/drivers/staging/batman-adv/send.c b/drivers/staging/batman-adv/send.c index 944b2cdbdff8..2a9fac8c240e 100644 --- a/drivers/staging/batman-adv/send.c +++ b/drivers/staging/batman-adv/send.c @@ -248,6 +248,7 @@ void schedule_own_packet(struct batman_if *batman_if) { unsigned long send_time; struct batman_packet *batman_packet; + int vis_server = atomic_read(&vis_mode); /** * the interface gets activated here to avoid race conditions between @@ -272,7 +273,7 @@ void schedule_own_packet(struct batman_if *batman_if) /* change sequence number to network order */ batman_packet->seqno = htons((uint16_t)atomic_read(&batman_if->seqno)); - if (is_vis_server()) + if (vis_server == VIS_TYPE_SERVER_SYNC) batman_packet->flags = VIS_SERVER; else batman_packet->flags = 0; diff --git a/drivers/staging/batman-adv/vis.c b/drivers/staging/batman-adv/vis.c index ec8bb3f382c6..fedec1bb3097 100644 --- a/drivers/staging/batman-adv/vis.c +++ b/drivers/staging/batman-adv/vis.c @@ -48,41 +48,6 @@ static void free_info(void *data) kfree(info); } -/* set the mode of the visualization to client or server */ -void vis_set_mode(int mode) -{ - unsigned long flags; - spin_lock_irqsave(&vis_hash_lock, flags); - - if (my_vis_info != NULL) - my_vis_info->packet.vis_type = mode; - - spin_unlock_irqrestore(&vis_hash_lock, flags); -} - -/* is_vis_server(), locked outside */ -static int is_vis_server_locked(void) -{ - if (my_vis_info != NULL) - if (my_vis_info->packet.vis_type == VIS_TYPE_SERVER_SYNC) - return 1; - - return 0; -} - -/* get the current set mode */ -int is_vis_server(void) -{ - int ret = 0; - unsigned long flags; - - spin_lock_irqsave(&vis_hash_lock, flags); - ret = is_vis_server_locked(); - spin_unlock_irqrestore(&vis_hash_lock, flags); - - return ret; -} - /* Compare two vis packets, used by the hashing algorithm */ static int vis_info_cmp(void *data1, void *data2) { @@ -271,6 +236,7 @@ void receive_server_sync_packet(struct vis_packet *vis_packet, int vis_info_len) struct vis_info *info; int is_new; unsigned long flags; + int vis_server = atomic_read(&vis_mode); spin_lock_irqsave(&vis_hash_lock, flags); info = add_packet(vis_packet, vis_info_len, &is_new); @@ -279,7 +245,7 @@ void receive_server_sync_packet(struct vis_packet *vis_packet, int vis_info_len) /* only if we are server ourselves and packet is newer than the one in * hash.*/ - if (is_vis_server_locked() && is_new) { + if (vis_server == VIS_TYPE_SERVER_SYNC && is_new) { memcpy(info->packet.target_orig, broadcastAddr, ETH_ALEN); if (list_empty(&info->send_list)) list_add_tail(&info->send_list, &send_list); @@ -295,6 +261,7 @@ void receive_client_update_packet(struct vis_packet *vis_packet, struct vis_info *info; int is_new; unsigned long flags; + int vis_server = atomic_read(&vis_mode); /* clients shall not broadcast. */ if (is_bcast(vis_packet->target_orig)) @@ -308,7 +275,7 @@ void receive_client_update_packet(struct vis_packet *vis_packet, /* send only if we're the target server or ... */ - if (is_vis_server_locked() && + if (vis_server == VIS_TYPE_SERVER_SYNC && is_my_mac(info->packet.target_orig) && is_new) { info->packet.vis_type = VIS_TYPE_SERVER_SYNC; /* upgrade! */ @@ -372,6 +339,7 @@ static int generate_vis_packet(void) unsigned long flags; info->first_seen = jiffies; + info->packet.vis_type = atomic_read(&vis_mode); spin_lock_irqsave(&orig_hash_lock, flags); memcpy(info->packet.target_orig, broadcastAddr, ETH_ALEN); @@ -379,7 +347,7 @@ static int generate_vis_packet(void) info->packet.seqno++; info->packet.entries = 0; - if (!is_vis_server_locked()) { + if (info->packet.vis_type == VIS_TYPE_CLIENT_UPDATE) { best_tq = find_best_vis_server(info); if (best_tq < 0) { spin_unlock_irqrestore(&orig_hash_lock, flags); @@ -577,7 +545,6 @@ int vis_init(void) INIT_LIST_HEAD(&my_vis_info->send_list); my_vis_info->packet.version = COMPAT_VERSION; my_vis_info->packet.packet_type = BAT_VIS; - my_vis_info->packet.vis_type = VIS_TYPE_CLIENT_UPDATE; my_vis_info->packet.ttl = TTL; my_vis_info->packet.seqno = 0; my_vis_info->packet.entries = 0; @@ -628,4 +595,3 @@ static void start_vis_timer(void) queue_delayed_work(bat_event_workqueue, &vis_timer_wq, (atomic_read(&vis_interval) * HZ) / 1000); } - diff --git a/drivers/staging/batman-adv/vis.h b/drivers/staging/batman-adv/vis.h index 2e24258e69a4..0cdafde0ec3a 100644 --- a/drivers/staging/batman-adv/vis.h +++ b/drivers/staging/batman-adv/vis.h @@ -48,8 +48,6 @@ struct recvlist_node { extern struct hashtable_t *vis_hash; extern spinlock_t vis_hash_lock; -void vis_set_mode(int mode); -int is_vis_server(void); void proc_vis_read_entry(struct seq_file *seq, struct vis_info_entry *entry, struct hlist_head *if_list, -- cgit v1.2.3 From 8d03847c090b12694fb9fa81dbefa7b3e4f10f1d Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Fri, 19 Feb 2010 16:18:09 +0100 Subject: Staging: batman-adv: Fix skbuff leak in VIS code. The vis code takes a copy of the data inside the skbuf if it is interesting for us, so we always need to release the skbuf. Reported-by: Linus Luessing Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/routing.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/routing.c b/drivers/staging/batman-adv/routing.c index 7dc9aef9bef4..d89048beebe1 100644 --- a/drivers/staging/batman-adv/routing.c +++ b/drivers/staging/batman-adv/routing.c @@ -939,7 +939,6 @@ int recv_vis_packet(struct sk_buff *skb) struct vis_packet *vis_packet; struct ethhdr *ethhdr; int hdr_size = sizeof(struct vis_packet); - int ret; if (skb_headlen(skb) < hdr_size) return NET_RX_DROP; @@ -962,18 +961,18 @@ int recv_vis_packet(struct sk_buff *skb) case VIS_TYPE_SERVER_SYNC: /* TODO: handle fragmented skbs properly */ receive_server_sync_packet(vis_packet, skb_headlen(skb)); - ret = NET_RX_SUCCESS; break; case VIS_TYPE_CLIENT_UPDATE: /* TODO: handle fragmented skbs properly */ receive_client_update_packet(vis_packet, skb_headlen(skb)); - ret = NET_RX_SUCCESS; break; default: /* ignore unknown packet */ - ret = NET_RX_DROP; break; } - return ret; + + /* We take a copy of the data in the packet, so we should + always free the skbuf. */ + return NET_RX_DROP; } -- cgit v1.2.3 From da6d6c7ac366ad3189e494cd78376db7a4f40d59 Mon Sep 17 00:00:00 2001 From: Marek Lindner Date: Fri, 19 Feb 2010 16:18:10 +0100 Subject: Staging: batman-adv: avoid crash on memory allocation error skb_share_check() returns NULL if it can't allocate more memory but it still frees the skbuff. Signed-off-by: Marek Lindner Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/hard-interface.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/hard-interface.c b/drivers/staging/batman-adv/hard-interface.c index f8b1ba3910ad..0f94158b2660 100644 --- a/drivers/staging/batman-adv/hard-interface.c +++ b/drivers/staging/batman-adv/hard-interface.c @@ -426,10 +426,11 @@ int batman_skb_recv(struct sk_buff *skb, struct net_device *dev, struct net_device_stats *stats; int ret; - skb = skb_share_check(skb, GFP_ATOMIC); + skb = skb_share_check(skb, GFP_ATOMIC); - if (skb == NULL) - goto err_free; + /* skb was released by skb_share_check() */ + if (!skb) + goto err_out; /* packet should hold at least type and version */ if (unlikely(skb_headlen(skb) < 2)) @@ -444,7 +445,7 @@ int batman_skb_recv(struct sk_buff *skb, struct net_device *dev, if (!batman_if) goto err_free; - stats = (struct net_device_stats *) dev_get_stats(skb->dev); + stats = (struct net_device_stats *)dev_get_stats(skb->dev); if (stats) { stats->rx_packets++; stats->rx_bytes += skb->len; @@ -490,6 +491,7 @@ int batman_skb_recv(struct sk_buff *skb, struct net_device *dev, default: ret = NET_RX_DROP; } + if (ret == NET_RX_DROP) kfree_skb(skb); @@ -500,9 +502,9 @@ int batman_skb_recv(struct sk_buff *skb, struct net_device *dev, return NET_RX_SUCCESS; err_free: - kfree_skb(skb); - return NET_RX_DROP; - + kfree_skb(skb); +err_out: + return NET_RX_DROP; } -- cgit v1.2.3 From af71b816cdc623bc7c0b616ededbf3dadaf03156 Mon Sep 17 00:00:00 2001 From: Marek Lindner Date: Fri, 19 Feb 2010 16:18:11 +0100 Subject: Staging: batman-adv: fix module initialization Make sure that batman-adv does not process packets before its initialization is complete. Some sanity checks added to the receiver function. Signed-off-by: Marek Lindner Signed-off-by: Simon Wunderlich Signed-off-by: Andrew Lunn Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/hard-interface.c | 7 +++++++ drivers/staging/batman-adv/proc.c | 17 ++++++----------- 2 files changed, 13 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/hard-interface.c b/drivers/staging/batman-adv/hard-interface.c index 0f94158b2660..befd48839519 100644 --- a/drivers/staging/batman-adv/hard-interface.c +++ b/drivers/staging/batman-adv/hard-interface.c @@ -432,6 +432,9 @@ int batman_skb_recv(struct sk_buff *skb, struct net_device *dev, if (!skb) goto err_out; + if (atomic_read(&module_state) != MODULE_ACTIVE) + goto err_free; + /* packet should hold at least type and version */ if (unlikely(skb_headlen(skb) < 2)) goto err_free; @@ -445,6 +448,10 @@ int batman_skb_recv(struct sk_buff *skb, struct net_device *dev, if (!batman_if) goto err_free; + /* discard frames on not active interfaces */ + if (batman_if->if_active != IF_ACTIVE) + goto err_free; + stats = (struct net_device_stats *)dev_get_stats(skb->dev); if (stats) { stats->rx_packets++; diff --git a/drivers/staging/batman-adv/proc.c b/drivers/staging/batman-adv/proc.c index 0eadc6b48d75..7de60e84bc96 100644 --- a/drivers/staging/batman-adv/proc.c +++ b/drivers/staging/batman-adv/proc.c @@ -63,7 +63,7 @@ static ssize_t proc_interfaces_write(struct file *instance, size_t count, loff_t *data) { char *if_string, *colon_ptr = NULL, *cr_ptr = NULL; - int not_copied = 0, if_num = 0; + int not_copied = 0, if_num = 0, add_success; struct batman_if *batman_if = NULL; if_string = kmalloc(count, GFP_KERNEL); @@ -109,22 +109,17 @@ static ssize_t proc_interfaces_write(struct file *instance, } rcu_read_unlock(); - hardif_add_interface(if_string, if_num); + add_success = hardif_add_interface(if_string, if_num); + if (add_success < 0) + goto end; + + num_ifs = if_num + 1; if ((atomic_read(&module_state) == MODULE_INACTIVE) && (hardif_get_active_if_num() > 0)) activate_module(); - rcu_read_lock(); - if (list_empty(&if_list)) { - rcu_read_unlock(); - goto end; - } - rcu_read_unlock(); - - num_ifs = if_num + 1; return count; - end: kfree(if_string); return count; -- cgit v1.2.3 From e41a6f6d9cb7404420d596f27609a3f4f55dcaf5 Mon Sep 17 00:00:00 2001 From: Stewart Robertson Date: Sun, 21 Feb 2010 10:13:21 +0000 Subject: Staging: comedi: fix coding style issues in ni_labpc.c This is a patch to the ni_labpc.c file that fixes the brace warnings and comments over 80 characters found by the checkpatch.pl tool. Some code still goes over 80 characters because I didn't know what to do with it. Signed-off-by: Stewart Robertson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_labpc.c | 231 +++++++++++++++++++----------- 1 file changed, 145 insertions(+), 86 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_labpc.c b/drivers/staging/comedi/drivers/ni_labpc.c index 566b791e00c7..bc5662e2a9bf 100644 --- a/drivers/staging/comedi/drivers/ni_labpc.c +++ b/drivers/staging/comedi/drivers/ni_labpc.c @@ -90,8 +90,10 @@ NI manuals: #define DRV_NAME "ni_labpc" -#define LABPC_SIZE 32 /* size of io region used by board */ -#define LABPC_TIMER_BASE 500 /* 2 MHz master clock */ +/* size of io region used by board */ +#define LABPC_SIZE 32 +/* 2 MHz master clock */ +#define LABPC_TIMER_BASE 500 /* Registers for the lab-pc+ */ @@ -99,69 +101,110 @@ NI manuals: #define COMMAND1_REG 0x0 #define ADC_GAIN_MASK (0x7 << 4) #define ADC_CHAN_BITS(x) ((x) & 0x7) -#define ADC_SCAN_EN_BIT 0x80 /* enables multi channel scans */ +/* enables multi channel scans */ +#define ADC_SCAN_EN_BIT 0x80 #define COMMAND2_REG 0x1 -#define PRETRIG_BIT 0x1 /* enable pretriggering (used in conjunction with SWTRIG) */ -#define HWTRIG_BIT 0x2 /* enable paced conversions on external trigger */ -#define SWTRIG_BIT 0x4 /* enable paced conversions */ -#define CASCADE_BIT 0x8 /* use two cascaded counters for pacing */ +/* enable pretriggering (used in conjunction with SWTRIG) */ +#define PRETRIG_BIT 0x1 +/* enable paced conversions on external trigger */ +#define HWTRIG_BIT 0x2 +/* enable paced conversions */ +#define SWTRIG_BIT 0x4 +/* use two cascaded counters for pacing */ +#define CASCADE_BIT 0x8 #define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1)) #define COMMAND3_REG 0x2 -#define DMA_EN_BIT 0x1 /* enable dma transfers */ -#define DIO_INTR_EN_BIT 0x2 /* enable interrupts for 8255 */ -#define DMATC_INTR_EN_BIT 0x4 /* enable dma terminal count interrupt */ -#define TIMER_INTR_EN_BIT 0x8 /* enable timer interrupt */ -#define ERR_INTR_EN_BIT 0x10 /* enable error interrupt */ -#define ADC_FNE_INTR_EN_BIT 0x20 /* enable fifo not empty interrupt */ +/* enable dma transfers */ +#define DMA_EN_BIT 0x1 +/* enable interrupts for 8255 */ +#define DIO_INTR_EN_BIT 0x2 +/* enable dma terminal count interrupt */ +#define DMATC_INTR_EN_BIT 0x4 +/* enable timer interrupt */ +#define TIMER_INTR_EN_BIT 0x8 +/* enable error interrupt */ +#define ERR_INTR_EN_BIT 0x10 +/* enable fifo not empty interrupt */ +#define ADC_FNE_INTR_EN_BIT 0x20 #define ADC_CONVERT_REG 0x3 #define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1)) #define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1)) #define ADC_CLEAR_REG 0x8 #define DMATC_CLEAR_REG 0xa #define TIMER_CLEAR_REG 0xc -#define COMMAND6_REG 0xe /* 1200 boards only */ -#define ADC_COMMON_BIT 0x1 /* select ground or common-mode reference */ -#define ADC_UNIP_BIT 0x2 /* adc unipolar */ -#define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1)) /* dac unipolar */ -#define ADC_FHF_INTR_EN_BIT 0x20 /* enable fifo half full interrupt */ -#define A1_INTR_EN_BIT 0x40 /* enable interrupt on end of hardware count */ -#define ADC_SCAN_UP_BIT 0x80 /* scan up from channel zero instead of down to zero */ +/* 1200 boards only */ +#define COMMAND6_REG 0xe +/* select ground or common-mode reference */ +#define ADC_COMMON_BIT 0x1 +/* adc unipolar */ +#define ADC_UNIP_BIT 0x2 +/* dac unipolar */ +#define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1)) +/* enable fifo half full interrupt */ +#define ADC_FHF_INTR_EN_BIT 0x20 +/* enable interrupt on end of hardware count */ +#define A1_INTR_EN_BIT 0x40 +/* scan up from channel zero instead of down to zero */ +#define ADC_SCAN_UP_BIT 0x80 #define COMMAND4_REG 0xf -#define INTERVAL_SCAN_EN_BIT 0x1 /* enables 'interval' scanning */ -#define EXT_SCAN_EN_BIT 0x2 /* enables external signal on counter b1 output to trigger scan */ -#define EXT_CONVERT_OUT_BIT 0x4 /* chooses direction (output or input) for EXTCONV* line */ -#define ADC_DIFF_BIT 0x8 /* chooses differential inputs for adc (in conjunction with board jumper) */ +/* enables 'interval' scanning */ +#define INTERVAL_SCAN_EN_BIT 0x1 +/* enables external signal on counter b1 output to trigger scan */ +#define EXT_SCAN_EN_BIT 0x2 +/* chooses direction (output or input) for EXTCONV* line */ +#define EXT_CONVERT_OUT_BIT 0x4 +/* chooses differential inputs for adc (in conjunction with board jumper) */ +#define ADC_DIFF_BIT 0x8 #define EXT_CONVERT_DISABLE_BIT 0x10 -#define COMMAND5_REG 0x1c /* 1200 boards only, calibration stuff */ -#define EEPROM_WRITE_UNPROTECT_BIT 0x4 /* enable eeprom for write */ -#define DITHER_EN_BIT 0x8 /* enable dithering */ -#define CALDAC_LOAD_BIT 0x10 /* load calibration dac */ -#define SCLOCK_BIT 0x20 /* serial clock - rising edge writes, falling edge reads */ -#define SDATA_BIT 0x40 /* serial data bit for writing to eeprom or calibration dacs */ -#define EEPROM_EN_BIT 0x80 /* enable eeprom for read/write */ +/* 1200 boards only, calibration stuff */ +#define COMMAND5_REG 0x1c +/* enable eeprom for write */ +#define EEPROM_WRITE_UNPROTECT_BIT 0x4 +/* enable dithering */ +#define DITHER_EN_BIT 0x8 +/* load calibration dac */ +#define CALDAC_LOAD_BIT 0x10 +/* serial clock - rising edge writes, falling edge reads */ +#define SCLOCK_BIT 0x20 +/* serial data bit for writing to eeprom or calibration dacs */ +#define SDATA_BIT 0x40 +/* enable eeprom for read/write */ +#define EEPROM_EN_BIT 0x80 #define INTERVAL_COUNT_REG 0x1e #define INTERVAL_LOAD_REG 0x1f #define INTERVAL_LOAD_BITS 0x1 /* read-only registers */ #define STATUS1_REG 0x0 -#define DATA_AVAIL_BIT 0x1 /* data is available in fifo */ -#define OVERRUN_BIT 0x2 /* overrun has occurred */ -#define OVERFLOW_BIT 0x4 /* fifo overflow */ -#define TIMER_BIT 0x8 /* timer interrupt has occured */ -#define DMATC_BIT 0x10 /* dma terminal count has occured */ -#define EXT_TRIG_BIT 0x40 /* external trigger has occured */ -#define STATUS2_REG 0x1d /* 1200 boards only */ -#define EEPROM_OUT_BIT 0x1 /* programmable eeprom serial output */ -#define A1_TC_BIT 0x2 /* counter A1 terminal count */ -#define FNHF_BIT 0x4 /* fifo not half full */ +/* data is available in fifo */ +#define DATA_AVAIL_BIT 0x1 +/* overrun has occurred */ +#define OVERRUN_BIT 0x2 +/* fifo overflow */ +#define OVERFLOW_BIT 0x4 +/* timer interrupt has occured */ +#define TIMER_BIT 0x8 +/* dma terminal count has occured */ +#define DMATC_BIT 0x10 +/* external trigger has occured */ +#define EXT_TRIG_BIT 0x40 +/* 1200 boards only */ +#define STATUS2_REG 0x1d +/* programmable eeprom serial output */ +#define EEPROM_OUT_BIT 0x1 +/* counter A1 terminal count */ +#define A1_TC_BIT 0x2 +/* fifo not half full */ +#define FNHF_BIT 0x4 #define ADC_FIFO_REG 0xa #define DIO_BASE_REG 0x10 #define COUNTER_A_BASE_REG 0x14 #define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3) -#define INIT_A0_BITS 0x14 /* check modes put conversion pacer output in harmless state (a0 mode 2) */ -#define INIT_A1_BITS 0x70 /* put hardware conversion counter output in harmless state (a1 mode 0) */ +/* check modes put conversion pacer output in harmless state (a0 mode 2) */ +#define INIT_A0_BITS 0x14 +/* put hardware conversion counter output in harmless state (a1 mode 0) */ +#define INIT_A1_BITS 0x70 #define COUNTER_B_BASE_REG 0x18 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it); @@ -423,7 +466,7 @@ static const struct labpc_board_struct labpc_boards[] = { .ai_scan_up = 1, .memory_mapped_io = 1, }, - /* dummy entry so pci board works when comedi_config is passed driver name */ +/* dummy entry so pci board works when comedi_config is passed driver name */ { .name = DRV_NAME, .bustype = pci_bustype, @@ -436,8 +479,10 @@ static const struct labpc_board_struct labpc_boards[] = { */ #define thisboard ((struct labpc_board_struct *)dev->board_ptr) -static const int dma_buffer_size = 0xff00; /* size in bytes of dma buffer */ -static const int sample_size = 2; /* 2 bytes per sample */ +/* size in bytes of dma buffer */ +static const int dma_buffer_size = 0xff00; +/* 2 bytes per sample */ +static const int sample_size = 2; #define devpriv ((struct labpc_private *)dev->private) @@ -511,7 +556,7 @@ int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, devpriv->read_byte = labpc_inb; devpriv->write_byte = labpc_outb; } - /* initialize board's command registers */ + /* initialize board's command registers */ devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); @@ -536,12 +581,12 @@ int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, } dev->irq = irq; - /* grab dma channel */ + /* grab dma channel */ if (dma_chan > 3) { printk(" invalid dma channel %u\n", dma_chan); return -EINVAL; } else if (dma_chan) { - /* allocate dma buffer */ + /* allocate dma buffer */ devpriv->dma_buffer = kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA); if (devpriv->dma_buffer == NULL) { @@ -573,7 +618,7 @@ int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ; s->n_chan = 8; s->len_chanlist = 8; - s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ + s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ s->range_table = thisboard->ai_range_table; s->do_cmd = labpc_ai_cmd; s->do_cmdtest = labpc_ai_cmdtest; @@ -667,7 +712,7 @@ static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) if (alloc_private(dev, sizeof(struct labpc_private)) < 0) return -ENOMEM; - /* get base address, irq etc. based on bustype */ + /* get base address, irq etc. based on bustype */ switch (thisboard->bustype) { case isa_bustype: iobase = it->options[0]; @@ -712,7 +757,7 @@ static int labpc_find_device(struct comedi_device *dev, int bus, int slot) for (mite = mite_devices; mite; mite = mite->next) { if (mite->used) continue; - /* if bus/slot are specified then make sure we have the right bus/slot */ +/* if bus/slot are specified then make sure we have the right bus/slot */ if (bus || slot) { if (bus != mite->pcidev->bus->number || slot != PCI_SLOT(mite->pcidev->devfn)) @@ -723,7 +768,7 @@ static int labpc_find_device(struct comedi_device *dev, int bus, int slot) continue; if (mite_device_id(mite) == labpc_boards[i].device_id) { devpriv->mite = mite; - /* fixup board pointer, in case we were using the dummy "ni_labpc" entry */ +/* fixup board pointer, in case we were using the dummy "ni_labpc" entry */ dev->board_ptr = &labpc_boards[i]; return 0; } @@ -991,7 +1036,7 @@ static int labpc_ai_cmdtest(struct comedi_device *dev, cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE) err++; - /* can't have external stop and start triggers at once */ + /* can't have external stop and start triggers at once */ if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) err++; @@ -1019,7 +1064,7 @@ static int labpc_ai_cmdtest(struct comedi_device *dev, err++; } } - /* make sure scan timing is not too fast */ + /* make sure scan timing is not too fast */ if (cmd->scan_begin_src == TRIG_TIMER) { if (cmd->convert_src == TRIG_TIMER && cmd->scan_begin_arg < @@ -1035,7 +1080,7 @@ static int labpc_ai_cmdtest(struct comedi_device *dev, err++; } } - /* stop source */ + /* stop source */ switch (cmd->stop_src) { case TRIG_COUNT: if (!cmd->stop_arg) { @@ -1092,7 +1137,7 @@ static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) range = CR_RANGE(cmd->chanlist[0]); aref = CR_AREF(cmd->chanlist[0]); - /* make sure board is disabled before setting up aquisition */ + /* make sure board is disabled before setting up aquisition */ spin_lock_irqsave(&dev->spinlock, flags); devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); @@ -1172,17 +1217,18 @@ static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); else channel = CR_CHAN(cmd->chanlist[0]); - /* munge channel bits for differential / scan disabled mode */ + /* munge channel bits for differential / scan disabled mode */ if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF) channel *= 2; devpriv->command1_bits |= ADC_CHAN_BITS(channel); devpriv->command1_bits |= thisboard->ai_range_code[range]; devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); - /* manual says to set scan enable bit on second pass */ + /* manual says to set scan enable bit on second pass */ if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP || labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) { devpriv->command1_bits |= ADC_SCAN_EN_BIT; - /* need a brief delay before enabling scan, or scan list will get screwed when you switch + /* need a brief delay before enabling scan, or scan + * list will get screwed when you switch * between scan up to scan down mode - dunno why */ udelay(1); devpriv->write_byte(devpriv->command1_bits, @@ -1334,7 +1380,7 @@ static irqreturn_t labpc_interrupt(int irq, void *d) cmd = &async->cmd; async->events = 0; - /* read board status */ + /* read board status */ devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); if (thisboard->register_layout == labpc_1200_layout) devpriv->status2_bits = @@ -1348,7 +1394,7 @@ static irqreturn_t labpc_interrupt(int irq, void *d) } if (devpriv->status1_bits & OVERRUN_BIT) { - /* clear error interrupt */ + /* clear error interrupt */ devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; comedi_event(dev, s); @@ -1357,7 +1403,7 @@ static irqreturn_t labpc_interrupt(int irq, void *d) } if (devpriv->current_transfer == isa_dma_transfer) { - /* if a dma terminal count of external stop trigger has occurred */ + /* if a dma terminal count of external stop trigger has occurred */ if (devpriv->status1_bits & DMATC_BIT || (thisboard->register_layout == labpc_1200_layout && devpriv->status2_bits & A1_TC_BIT)) { @@ -1532,41 +1578,41 @@ static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, chan = CR_CHAN(insn->chanspec); range = CR_RANGE(insn->chanspec); devpriv->command1_bits |= thisboard->ai_range_code[range]; - /* munge channel bits for differential/scan disabled mode */ + /* munge channel bits for differential/scan disabled mode */ if (CR_AREF(insn->chanspec) == AREF_DIFF) chan *= 2; devpriv->command1_bits |= ADC_CHAN_BITS(chan); devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); - /* setup command6 register for 1200 boards */ + /* setup command6 register for 1200 boards */ if (thisboard->register_layout == labpc_1200_layout) { /* reference inputs to ground or common? */ if (CR_AREF(insn->chanspec) != AREF_GROUND) devpriv->command6_bits |= ADC_COMMON_BIT; else devpriv->command6_bits &= ~ADC_COMMON_BIT; - /* bipolar or unipolar range? */ + /* bipolar or unipolar range? */ if (thisboard->ai_range_is_unipolar[range]) devpriv->command6_bits |= ADC_UNIP_BIT; else devpriv->command6_bits &= ~ADC_UNIP_BIT; - /* don't interrupt on fifo half full */ + /* don't interrupt on fifo half full */ devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; - /* don't enable interrupt on counter a1 terminal count? */ + /* don't enable interrupt on counter a1 terminal count? */ devpriv->command6_bits &= ~A1_INTR_EN_BIT; - /* write to register */ + /* write to register */ devpriv->write_byte(devpriv->command6_bits, dev->iobase + COMMAND6_REG); } - /* setup command4 register */ + /* setup command4 register */ devpriv->command4_bits = 0; devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; - /* single-ended/differential */ + /* single-ended/differential */ if (CR_AREF(insn->chanspec) == AREF_DIFF) devpriv->command4_bits |= ADC_DIFF_BIT; devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); - /* initialize pacer counter output to make sure it doesn't cause any problems */ + /* initialize pacer counter output to make sure it doesn't cause any problems */ devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG); labpc_clear_adc_fifo(dev); @@ -1603,7 +1649,7 @@ static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, channel = CR_CHAN(insn->chanspec); - /* turn off pacing of analog output channel */ + /* turn off pacing of analog output channel */ /* note: hardware bug in daqcard-1200 means pacing cannot * be independently enabled/disabled for its the two channels */ spin_lock_irqsave(&dev->spinlock, flags); @@ -1611,7 +1657,7 @@ static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); spin_unlock_irqrestore(&dev->spinlock, flags); - /* set range */ + /* set range */ if (thisboard->register_layout == labpc_1200_layout) { range = CR_RANGE(insn->chanspec); if (range & AO_RANGE_IS_UNIPOLAR) @@ -1622,13 +1668,13 @@ static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, devpriv->write_byte(devpriv->command6_bits, dev->iobase + COMMAND6_REG); } - /* send data */ + /* send data */ lsb = data[0] & 0xff; msb = (data[0] >> 8) & 0xff; devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); - /* remember value for readback */ + /* remember value for readback */ devpriv->ao_value[channel] = data[0]; return 1; @@ -1700,14 +1746,14 @@ static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd) if (cmd.convert_src == TRIG_TIMER) freq = 1000000000 / cmd.convert_arg; - /* return some default value */ + /* return some default value */ else freq = 0xffffffff; - /* make buffer fill in no more than 1/3 second */ + /* make buffer fill in no more than 1/3 second */ size = (freq / 3) * sample_size; - /* set a minimum and maximum size allowed */ + /* set a minimum and maximum size allowed */ if (size > dma_buffer_size) size = dma_buffer_size - dma_buffer_size % sample_size; else if (size < sample_size) @@ -1719,13 +1765,21 @@ static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd) /* figures out what counter values to use based on command */ static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) { - const int max_counter_value = 0x10000; /* max value for 16 bit counter in mode 2 */ - const int min_counter_value = 2; /* min value for 16 bit counter in mode 2 */ + /* max value for 16 bit counter in mode 2 */ + const int max_counter_value = 0x10000; + /* min value for 16 bit counter in mode 2 */ + const int min_counter_value = 2; unsigned int base_period; - /* if both convert and scan triggers are TRIG_TIMER, then they both rely on counter b0 */ + /* + * if both convert and scan triggers are TRIG_TIMER, then they + * both rely on counter b0 + */ if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) { - /* pick the lowest b0 divisor value we can (for maximum input clock speed on convert and scan counters) */ + /* + * pick the lowest b0 divisor value we can (for maximum input + * clock speed on convert and scan counters) + */ devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) / (LABPC_TIMER_BASE * max_counter_value) + 1; if (devpriv->divisor_b0 < min_counter_value) @@ -1775,7 +1829,10 @@ static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) base_period * devpriv->divisor_a0); labpc_set_ai_scan_period(cmd, base_period * devpriv->divisor_b1); - /* if only one TRIG_TIMER is used, we can employ the generic cascaded timing functions */ + /* + * if only one TRIG_TIMER is used, we can employ the generic + * cascaded timing functions + */ } else if (labpc_ai_scan_period(cmd)) { unsigned int scan_period; @@ -1870,8 +1927,10 @@ static unsigned int labpc_eeprom_read(struct comedi_device *dev, unsigned int address) { unsigned int value; - const int read_instruction = 0x3; /* bits to tell eeprom to expect a read */ - const int write_length = 8; /* 8 bit write lengths to eeprom */ + /* bits to tell eeprom to expect a read */ + const int read_instruction = 0x3; + /* 8 bit write lengths to eeprom */ + const int write_length = 8; /* enable read/write to eeprom */ devpriv->command5_bits &= ~EEPROM_EN_BIT; -- cgit v1.2.3 From e20ad20d849eb902628553be1fd2dc9ccc40a4bd Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Sun, 21 Feb 2010 21:25:33 +0100 Subject: Staging: comedi: aio_iiro_16: Checkpatch cleanups This fixes all checkpatch issues in the aio_iiro_16 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/aio_iiro_16.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/aio_iiro_16.c b/drivers/staging/comedi/drivers/aio_iiro_16.c index 3857fd566d21..4baef9ff932a 100644 --- a/drivers/staging/comedi/drivers/aio_iiro_16.c +++ b/drivers/staging/comedi/drivers/aio_iiro_16.c @@ -98,7 +98,7 @@ static int aio_iiro_16_attach(struct comedi_device *dev, int iobase; struct comedi_subdevice *s; - printk("comedi%d: aio_iiro_16: ", dev->minor); + printk(KERN_INFO "comedi%d: aio_iiro_16: ", dev->minor); dev->board_name = thisboard->name; @@ -140,7 +140,7 @@ static int aio_iiro_16_attach(struct comedi_device *dev, static int aio_iiro_16_detach(struct comedi_device *dev) { - printk("comedi%d: aio_iiro_16: remove\n", dev->minor); + printk(KERN_INFO "comedi%d: aio_iiro_16: remove\n", dev->minor); if (dev->iobase) release_region(dev->iobase, AIO_IIRO_16_SIZE); -- cgit v1.2.3 From 669c930c8fe266917865f923db51c3b654ab78a3 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Sun, 21 Feb 2010 21:44:57 +0100 Subject: Staging: comedi: amplc_dio200: Checkpatch cleanups This fixes all checkpatch issues in the amplc_dio200 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/amplc_dio200.c | 122 +++++++++++--------------- 1 file changed, 51 insertions(+), 71 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/amplc_dio200.c b/drivers/staging/comedi/drivers/amplc_dio200.c index 69ab2813dd2e..204f30ef6e96 100644 --- a/drivers/staging/comedi/drivers/amplc_dio200.c +++ b/drivers/staging/comedi/drivers/amplc_dio200.c @@ -48,8 +48,8 @@ Passing a zero for an option is the same as leaving it unspecified. SUBDEVICES - PC218E PC212E PC215E/PCI215 - ------------- ------------- ------------- + PC218E PC212E PC215E/PCI215 + ------------- ------------- ------------- Subdevices 7 6 5 0 CTR-X1 PPI-X PPI-X 1 CTR-X2 CTR-Y1 PPI-Y @@ -59,8 +59,8 @@ SUBDEVICES 5 CTR-Z2 INTERRUPT 6 INTERRUPT - PC214E PC272E/PCI272 - ------------- ------------- + PC214E PC272E/PCI272 + ------------- ------------- Subdevices 4 4 0 PPI-X PPI-X 1 PPI-Y PPI-Y @@ -96,8 +96,8 @@ instructions are supported: 0 to 7 as follows: 0. CLK n, the counter channel's dedicated CLK input from the SK1 - connector. (N.B. for other values, the counter channel's CLKn - pin on the SK1 connector is an output!) + connector. (N.B. for other values, the counter channel's CLKn + pin on the SK1 connector is an output!) 1. Internal 10 MHz clock. 2. Internal 1 MHz clock. 3. Internal 100 kHz clock. @@ -105,8 +105,8 @@ instructions are supported: 5. Internal 1 kHz clock. 6. OUT n-1, the output of counter channel n-1 (see note 1 below). 7. Ext Clock, the counter chip's dedicated Ext Clock input from - the SK1 connector. This pin is shared by all three counter - channels on the chip. + the SK1 connector. This pin is shared by all three counter + channels on the chip. INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current clock source in data[1]. For internal clock sources, data[2] is set @@ -120,10 +120,10 @@ instructions are supported: 0. VCC (internal +5V d.c.), i.e. gate permanently enabled. 1. GND (internal 0V d.c.), i.e. gate permanently disabled. 2. GAT n, the counter channel's dedicated GAT input from the SK1 - connector. (N.B. for other values, the counter channel's GATn - pin on the SK1 connector is an output!) + connector. (N.B. for other values, the counter channel's GATn + pin on the SK1 connector is an output!) 3. /OUT n-2, the inverted output of counter channel n-2 (see note - 2 below). + 2 below). 4. Reserved. 5. Reserved. 6. Reserved. @@ -153,8 +153,8 @@ below. INTERRUPT SOURCES - PC218E PC212E PC215E/PCI215 - ------------- ------------- ------------- + PC218E PC212E PC215E/PCI215 + ------------- ------------- ------------- Sources 6 6 6 0 CTR-X1-OUT PPI-X-C0 PPI-X-C0 1 CTR-X2-OUT PPI-X-C3 PPI-X-C3 @@ -163,8 +163,8 @@ INTERRUPT SOURCES 4 CTR-Z1-OUT CTR-Z1-OUT CTR-Z1-OUT 5 CTR-Z2-OUT CTR-Z2-OUT CTR-Z2-OUT - PC214E PC272E/PCI272 - ------------- ------------- + PC214E PC272E/PCI272 + ------------- ------------- Sources 1 6 0 JUMPER-J5 PPI-X-C0 1 PPI-X-C3 @@ -435,11 +435,13 @@ MODULE_DEVICE_TABLE(pci, dio200_pci_table); * Useful for shorthand access to the particular board structure */ #define thisboard ((const struct dio200_board *)dev->board_ptr) -#define thislayout (&dio200_layouts[((struct dio200_board *)dev->board_ptr)->layout]) +#define thislayout (&dio200_layouts[((struct dio200_board *) \ + dev->board_ptr)->layout]) /* this structure is for data unique to this hardware driver. If several hardware drivers keep similar information in this structure, - feel free to suggest moving the variable to the struct comedi_device struct. */ + feel free to suggest moving the variable to the struct comedi_device struct. + */ struct dio200_private { #ifdef CONFIG_COMEDI_PCI struct pci_dev *pci_dev; /* PCI device */ @@ -603,9 +605,8 @@ static void dio200_stop_intr(struct comedi_device *dev, subpriv->active = 0; subpriv->enabled_isns = 0; - if (subpriv->has_int_sce) { + if (subpriv->has_int_sce) outb(0, subpriv->iobase); - } } /* @@ -629,16 +630,14 @@ static int dio200_start_intr(struct comedi_device *dev, /* Determine interrupt sources to enable. */ isn_bits = 0; if (cmd->chanlist) { - for (n = 0; n < cmd->chanlist_len; n++) { + for (n = 0; n < cmd->chanlist_len; n++) isn_bits |= (1U << CR_CHAN(cmd->chanlist[n])); - } } isn_bits &= subpriv->valid_isns; /* Enable interrupt sources. */ subpriv->enabled_isns = isn_bits; - if (subpriv->has_int_sce) { + if (subpriv->has_int_sce) outb(isn_bits, subpriv->iobase); - } } return retval; @@ -662,14 +661,13 @@ dio200_inttrig_start_intr(struct comedi_device *dev, struct comedi_subdevice *s, spin_lock_irqsave(&subpriv->spinlock, flags); s->async->inttrig = 0; - if (subpriv->active) { + if (subpriv->active) event = dio200_start_intr(dev, s); - } + spin_unlock_irqrestore(&subpriv->spinlock, flags); - if (event) { + if (event) comedi_event(dev, s); - } return 1; } @@ -726,9 +724,8 @@ static int dio200_handle_read_intr(struct comedi_device *dev, * Reenable them NOW to minimize the time they are disabled. */ cur_enabled = subpriv->enabled_isns; - if (subpriv->has_int_sce) { + if (subpriv->has_int_sce) outb(cur_enabled, subpriv->iobase); - } if (subpriv->active) { /* @@ -747,9 +744,8 @@ static int dio200_handle_read_intr(struct comedi_device *dev, len = s->async->cmd.chanlist_len; for (n = 0; n < len; n++) { ch = CR_CHAN(s->async->cmd.chanlist[n]); - if (triggered & (1U << ch)) { + if (triggered & (1U << ch)) val |= (1U << n); - } } /* Write the scan to the buffer. */ if (comedi_buf_put(s->async, val)) { @@ -781,9 +777,8 @@ static int dio200_handle_read_intr(struct comedi_device *dev, } spin_unlock_irqrestore(&subpriv->spinlock, flags); - if (oldevents != s->async->events) { + if (oldevents != s->async->events) comedi_event(dev, s); - } return (triggered != 0); } @@ -798,9 +793,9 @@ static int dio200_subdev_intr_cancel(struct comedi_device *dev, unsigned long flags; spin_lock_irqsave(&subpriv->spinlock, flags); - if (subpriv->active) { + if (subpriv->active) dio200_stop_intr(dev, s); - } + spin_unlock_irqrestore(&subpriv->spinlock, flags); return 0; @@ -846,7 +841,8 @@ dio200_subdev_intr_cmdtest(struct comedi_device *dev, if (err) return 1; - /* step 2: make sure trigger sources are unique and mutually compatible */ + /* step 2: make sure trigger sources are unique and mutually + compatible */ /* these tests are true if more than one _src bit is set */ if ((cmd->start_src & (cmd->start_src - 1)) != 0) @@ -952,9 +948,8 @@ static int dio200_subdev_intr_cmd(struct comedi_device *dev, } spin_unlock_irqrestore(&subpriv->spinlock, flags); - if (event) { + if (event) comedi_event(dev, s); - } return 0; } @@ -980,9 +975,8 @@ dio200_subdev_intr_init(struct comedi_device *dev, struct comedi_subdevice *s, subpriv->valid_isns = valid_isns; spin_lock_init(&subpriv->spinlock); - if (has_int_sce) { + if (has_int_sce) outb(0, subpriv->iobase); /* Disable interrupt sources. */ - } s->private = subpriv; s->type = COMEDI_SUBD_DI; @@ -1013,10 +1007,7 @@ dio200_subdev_intr_cleanup(struct comedi_device *dev, struct comedi_subdevice *s) { struct dio200_subdev_intr *subpriv = s->private; - - if (subpriv) { - kfree(subpriv); - } + kfree(subpriv); } /* @@ -1027,9 +1018,8 @@ static irqreturn_t dio200_interrupt(int irq, void *d) struct comedi_device *dev = d; int handled; - if (!dev->attached) { + if (!dev->attached) return IRQ_NONE; - } if (devpriv->intr_sd >= 0) { handled = dio200_handle_read_intr(dev, @@ -1266,10 +1256,7 @@ dio200_subdev_8254_cleanup(struct comedi_device *dev, struct comedi_subdevice *s) { struct dio200_subdev_intr *subpriv = s->private; - - if (subpriv) { - kfree(subpriv); - } + kfree(subpriv); } /* @@ -1348,9 +1335,8 @@ static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it) #endif { ret = dio200_request_region(dev->minor, iobase, DIO200_IO_SIZE); - if (ret < 0) { + if (ret < 0) return ret; - } } dev->iobase = iobase; @@ -1371,17 +1357,17 @@ static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it) ret = dio200_subdev_8254_init(dev, s, iobase, layout->sdinfo[n], layout->has_clk_gat_sce); - if (ret < 0) { + if (ret < 0) return ret; - } + break; case sd_8255: /* digital i/o subdevice (8255) */ ret = subdev_8255_init(dev, s, 0, iobase + layout->sdinfo[n]); - if (ret < 0) { + if (ret < 0) return ret; - } + break; case sd_intr: /* 'INTERRUPT' subdevice */ @@ -1392,9 +1378,9 @@ static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it) layout->sdinfo[n], layout-> has_int_sce); - if (ret < 0) { + if (ret < 0) return ret; - } + devpriv->intr_sd = n; } else { s->type = COMEDI_SUBD_UNUSED; @@ -1407,9 +1393,8 @@ static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it) } sdx = devpriv->intr_sd; - if (sdx >= 0 && sdx < dev->n_subdevices) { + if (sdx >= 0 && sdx < dev->n_subdevices) dev->read_subdev = &dev->subdevices[sdx]; - } dev->board_name = thisboard->name; @@ -1434,11 +1419,10 @@ static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it) printk("(pci %s) ", pci_name(pci_dev)); #endif } - if (irq) { + if (irq) printk("(irq %u%s) ", irq, (dev->irq ? "" : " UNAVAILABLE")); - } else { + else printk("(no irq) "); - } printk("attached\n"); @@ -1461,9 +1445,8 @@ static int dio200_detach(struct comedi_device *dev) printk(KERN_DEBUG "comedi%d: %s: detach\n", dev->minor, DIO200_DRIVER_NAME); - if (dev->irq) { + if (dev->irq) free_irq(dev->irq, dev); - } if (dev->subdevices) { layout = thislayout; for (n = 0; n < dev->n_subdevices; n++) { @@ -1486,22 +1469,19 @@ static int dio200_detach(struct comedi_device *dev) if (devpriv) { #ifdef CONFIG_COMEDI_PCI if (devpriv->pci_dev) { - if (dev->iobase) { + if (dev->iobase) comedi_pci_disable(devpriv->pci_dev); - } pci_dev_put(devpriv->pci_dev); } else #endif { - if (dev->iobase) { + if (dev->iobase) release_region(dev->iobase, DIO200_IO_SIZE); - } } } - if (dev->board_name) { + if (dev->board_name) printk(KERN_INFO "comedi%d: %s removed\n", dev->minor, dev->board_name); - } return 0; } -- cgit v1.2.3 From 9f7a344b69485dc1052534a4e1b2e5a8f7de086e Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Sun, 21 Feb 2010 21:51:00 +0100 Subject: Staging: comedi: amplc_pc236: Checkpatch cleanups This fixes all checkpatch issues in the amplc_pc236 comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/amplc_pc236.c | 46 +++++++++++++--------------- 1 file changed, 21 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/amplc_pc236.c b/drivers/staging/comedi/drivers/amplc_pc236.c index 1032a8110d6e..a307d68d79c6 100644 --- a/drivers/staging/comedi/drivers/amplc_pc236.c +++ b/drivers/staging/comedi/drivers/amplc_pc236.c @@ -78,18 +78,18 @@ unused. */ /* Disable interrupt, also clear any interrupt there */ #define PCI236_INTR_DISABLE (PLX9052_INTCSR_LI1ENAB_DISABLED \ - | PLX9052_INTCSR_LI1POL_HIGH \ - | PLX9052_INTCSR_LI2POL_HIGH \ - | PLX9052_INTCSR_PCIENAB_DISABLED \ - | PLX9052_INTCSR_LI1SEL_EDGE \ - | PLX9052_INTCSR_LI1CLRINT_ASSERTED) + | PLX9052_INTCSR_LI1POL_HIGH \ + | PLX9052_INTCSR_LI2POL_HIGH \ + | PLX9052_INTCSR_PCIENAB_DISABLED \ + | PLX9052_INTCSR_LI1SEL_EDGE \ + | PLX9052_INTCSR_LI1CLRINT_ASSERTED) /* Enable interrupt, also clear any interrupt there. */ #define PCI236_INTR_ENABLE (PLX9052_INTCSR_LI1ENAB_ENABLED \ - | PLX9052_INTCSR_LI1POL_HIGH \ - | PLX9052_INTCSR_LI2POL_HIGH \ - | PLX9052_INTCSR_PCIENAB_ENABLED \ - | PLX9052_INTCSR_LI1SEL_EDGE \ - | PLX9052_INTCSR_LI1CLRINT_ASSERTED) + | PLX9052_INTCSR_LI1POL_HIGH \ + | PLX9052_INTCSR_LI2POL_HIGH \ + | PLX9052_INTCSR_PCIENAB_ENABLED \ + | PLX9052_INTCSR_LI1SEL_EDGE \ + | PLX9052_INTCSR_LI1CLRINT_ASSERTED) /* * Board descriptions for Amplicon PC36AT and PCI236. @@ -150,12 +150,13 @@ MODULE_DEVICE_TABLE(pci, pc236_pci_table); /* this structure is for data unique to this hardware driver. If several hardware drivers keep similar information in this structure, - feel free to suggest moving the variable to the struct comedi_device struct. */ + feel free to suggest moving the variable to the struct comedi_device struct. + */ struct pc236_private { #ifdef CONFIG_COMEDI_PCI /* PCI device */ struct pci_dev *pci_dev; - unsigned long lcr_iobase; /* PLX PCI9052 config registers in PCIBAR1 */ + unsigned long lcr_iobase; /* PLX PCI9052 config registers in PCIBAR1 */ #endif int enable_irq; }; @@ -345,9 +346,8 @@ static int pc236_attach(struct comedi_device *dev, struct comedi_devconfig *it) #endif { ret = pc236_request_region(dev->minor, iobase, PC236_IO_SIZE); - if (ret < 0) { + if (ret < 0) return ret; - } } dev->iobase = iobase; @@ -399,11 +399,10 @@ static int pc236_attach(struct comedi_device *dev, struct comedi_devconfig *it) printk("(pci %s) ", pci_name(pci_dev)); #endif } - if (irq) { + if (irq) printk("(irq %u%s) ", irq, (dev->irq ? "" : " UNAVAILABLE")); - } else { + else printk("(no irq) "); - } printk("attached\n"); @@ -422,27 +421,24 @@ static int pc236_detach(struct comedi_device *dev) { printk(KERN_DEBUG "comedi%d: %s: detach\n", dev->minor, PC236_DRIVER_NAME); - if (devpriv) { + if (devpriv) pc236_intr_disable(dev); - } + if (dev->irq) free_irq(dev->irq, dev); - if (dev->subdevices) { + if (dev->subdevices) subdev_8255_cleanup(dev, dev->subdevices + 0); - } if (devpriv) { #ifdef CONFIG_COMEDI_PCI if (devpriv->pci_dev) { - if (dev->iobase) { + if (dev->iobase) comedi_pci_disable(devpriv->pci_dev); - } pci_dev_put(devpriv->pci_dev); } else #endif { - if (dev->iobase) { + if (dev->iobase) release_region(dev->iobase, PC236_IO_SIZE); - } } } if (dev->board_name) { -- cgit v1.2.3 From 2021937c6d8ec1212b8f4fa01e86f852c9b96368 Mon Sep 17 00:00:00 2001 From: OGAWA Hirofumi Date: Tue, 23 Feb 2010 03:04:42 +0900 Subject: Staging: comedi: serial2002: Fix filp_open usage Signed-off-by: OGAWA Hirofumi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/serial2002.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/serial2002.c b/drivers/staging/comedi/drivers/serial2002.c index db37dcdd98b6..dd2b90372794 100644 --- a/drivers/staging/comedi/drivers/serial2002.c +++ b/drivers/staging/comedi/drivers/serial2002.c @@ -397,7 +397,7 @@ static void serial_2002_open(struct comedi_device *dev) char port[20]; sprintf(port, "/dev/ttyS%d", devpriv->port); - devpriv->tty = filp_open(port, 0, O_RDWR); + devpriv->tty = filp_open(port, O_RDWR, 0); if (IS_ERR(devpriv->tty)) { printk("serial_2002: file open error = %ld\n", PTR_ERR(devpriv->tty)); -- cgit v1.2.3 From ea12ac4fd241a141cc64683f4293f48bed84fd42 Mon Sep 17 00:00:00 2001 From: Frank Mori Hess Date: Mon, 22 Feb 2010 15:32:32 -0500 Subject: Staging: comedi: Increased timeout for digital output dma loading Increased timeout for digital output dma loading, due to report of it being too short for some hardware. Signed-off-by: Frank Mori Hess Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_mio_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_mio_common.c b/drivers/staging/comedi/drivers/ni_mio_common.c index d6d49c3bbf1c..bd16f913af23 100644 --- a/drivers/staging/comedi/drivers/ni_mio_common.c +++ b/drivers/staging/comedi/drivers/ni_mio_common.c @@ -3795,7 +3795,7 @@ static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, #endif int retval = 0; unsigned i; - const unsigned timeout = 100; + const unsigned timeout = 1000; s->async->inttrig = NULL; -- cgit v1.2.3 From 0f7cf0034c6b9aafea3605ec61145c9b54b1b208 Mon Sep 17 00:00:00 2001 From: Sylvain Trias Date: Wed, 24 Feb 2010 00:17:52 +0100 Subject: Staging: line6: variax.c: fixed a space a "x ? a : b" coding style issue Fixed a coding style issue. Signed-off-by: Sylvain Trias Signed-off-by: Greg Kroah-Hartman --- drivers/staging/line6/variax.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c index 48d834b0fa1b..58fef82c247d 100644 --- a/drivers/staging/line6/variax.c +++ b/drivers/staging/line6/variax.c @@ -254,7 +254,7 @@ static ssize_t variax_set_active(struct device *dev, if (ret) return ret; - variax->buffer_activate[VARIAX_OFFSET_ACTIVATE] = value ? 1: 0; + variax->buffer_activate[VARIAX_OFFSET_ACTIVATE] = value ? 1 : 0; line6_send_raw_message_async(&variax->line6, variax->buffer_activate, sizeof(variax_activate)); return count; -- cgit v1.2.3 From 128a5d0223ebef1cb6c0d94b3f87b49e38a11443 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 24 Feb 2010 11:39:20 -0800 Subject: Staging: rtl8192* needs semaphore.h The rtl8192* drivers in staging use semaphores, so they need to #include . (similar to staging-rtl8187se-needs-semaphore.h.patch) drivers/staging/rtl8192e/ieee80211/ieee80211.h:2038: error: field 'ips_sem' has incomplete type drivers/staging/rtl8192e/ieee80211/ieee80211.h:2249: error: field 'wx_sem' has incomplete type drivers/staging/rtl8192e/ieee80211/ieee80211.h:2250: error: field 'scan_sem' has incomplete type drivers/staging/rtl8192e/ieee80211/ieee80211_softmac.c:442: error: implicit declaration of function 'down' drivers/staging/rtl8192e/ieee80211/ieee80211_softmac.c:500: error: implicit declaration of function 'up' drivers/staging/rtl8192e/ieee80 211/ieee80211_softmac.c:3165: error: implicit declaration of function 'sema_init' drivers/staging/rtl8192su/ieee80211/ieee80211.h:1330: error: field 'wx_sem' has incomplete type drivers/staging/rtl8192su/ieee80211/ieee80211.h:1331: error: field 'scan_sem' has incomplete type drivers/staging/rtl8192u/ieee80211/ieee80211.h:2010: error: field 'wx_sem' has incomplete type drivers/staging/rtl8192u/ieee80211/ieee80211.h:2011: error: field 'scan_sem' has incomplete type Signed-off-by: Randy Dunlap Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/ieee80211/ieee80211.h | 1 + drivers/staging/rtl8192su/ieee80211/ieee80211.h | 1 + drivers/staging/rtl8192u/ieee80211/ieee80211.h | 1 + 3 files changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/staging/rtl8192e/ieee80211/ieee80211.h b/drivers/staging/rtl8192e/ieee80211/ieee80211.h index 5859f66ff013..1f613a28152f 100644 --- a/drivers/staging/rtl8192e/ieee80211/ieee80211.h +++ b/drivers/staging/rtl8192e/ieee80211/ieee80211.h @@ -35,6 +35,7 @@ #endif #include #include +#include #include #include diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211.h b/drivers/staging/rtl8192su/ieee80211/ieee80211.h index 159fddf628e2..caa580e2c662 100644 --- a/drivers/staging/rtl8192su/ieee80211/ieee80211.h +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211.h @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211.h b/drivers/staging/rtl8192u/ieee80211/ieee80211.h index 3cda38bb6b77..39847c81e29c 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211.h +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211.h @@ -30,6 +30,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3 From 83a0f9bc658b20b06740691d9ee711c5d14b6e8a Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Thu, 25 Feb 2010 09:55:03 -0800 Subject: Staging: fix wlan-ng printk format warning Fix prism2fw.c printk format warning: drivers/staging/wlan-ng/prism2fw.c:209: warning: format '%d' expects type 'int', but argument 3 has type 'size_t' Signed-off-by: Randy Dunlap Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlan-ng/prism2fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/wlan-ng/prism2fw.c b/drivers/staging/wlan-ng/prism2fw.c index baa20a7c930d..b57601250dc7 100644 --- a/drivers/staging/wlan-ng/prism2fw.c +++ b/drivers/staging/wlan-ng/prism2fw.c @@ -205,7 +205,7 @@ int prism2_fwtry(struct usb_device *udev, wlandevice_t *wlandev) return 1; } - printk(KERN_INFO "prism2_usb: %s will be processed, size %d\n", + printk(KERN_INFO "prism2_usb: %s will be processed, size %zu\n", PRISM2_USB_FWFILE, fw_entry->size); prism2_fwapply((const struct ihex_binrec *)fw_entry->data, wlandev); -- cgit v1.2.3 From 582de7caf578f3ed1f52bc93ad926a580af885b4 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Thu, 25 Feb 2010 14:41:22 -0800 Subject: Staging/pohmelfs: fix write_inode parameter warning sparse warns that: drivers/staging/pohmelfs/inode.c:1797: warning: initialization from incompatible pointer type so fix pohmelfs_write_inode() to have the expected parameters. Signed-off-by: Randy Dunlap Cc: Evgeniy Polyakov Signed-off-by: Greg Kroah-Hartman --- drivers/staging/pohmelfs/inode.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/pohmelfs/inode.c b/drivers/staging/pohmelfs/inode.c index eec3798eaf25..bf38280def3f 100644 --- a/drivers/staging/pohmelfs/inode.c +++ b/drivers/staging/pohmelfs/inode.c @@ -396,7 +396,8 @@ int pohmelfs_remove_child(struct pohmelfs_inode *pi, struct pohmelfs_name *n) /* * Writeback for given inode. */ -static int pohmelfs_write_inode(struct inode *inode, int sync) +static int pohmelfs_write_inode(struct inode *inode, + struct writeback_control *wbc) { struct pohmelfs_inode *pi = POHMELFS_I(inode); -- cgit v1.2.3 From 092579690107ffdf9b146de7e67379d8434e9bb0 Mon Sep 17 00:00:00 2001 From: Jim Dog Date: Thu, 25 Feb 2010 11:38:21 +0000 Subject: Staging: wlan-ng: Fixed line length issues in prism2usb.c This is a patch to the prism2usb.c that fixes one line which was over the 80 character limit by wrapping it to a new line and removes a commented out configuration for a ZyDAS ZD1201 device since support for this device with this driver is now deprecated. Signed-off-by: Jim Dog Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlan-ng/prism2usb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/wlan-ng/prism2usb.c b/drivers/staging/wlan-ng/prism2usb.c index 9dde68be8d74..501d27f74c7d 100644 --- a/drivers/staging/wlan-ng/prism2usb.c +++ b/drivers/staging/wlan-ng/prism2usb.c @@ -24,8 +24,9 @@ static struct usb_device_id usb_prism_tbl[] = { (0x066b, 0x2213, "Linksys WUSB12v1.1 11Mbps WLAN USB Adapter")}, {PRISM_USB_DEVICE (0x067c, 0x1022, "Siemens SpeedStream 1022 11Mbps WLAN USB Adapter")}, - {PRISM_USB_DEVICE(0x049f, 0x0033, - "Compaq/Intel W100 PRO/Wireless 11Mbps multiport WLAN Adapter")}, + {PRISM_USB_DEVICE + (0x049f, 0x0033, + "Compaq/Intel W100 PRO/Wireless 11Mbps multiport WLAN Adapter")}, {PRISM_USB_DEVICE (0x0411, 0x0016, "Melco WLI-USB-S11 11Mbps WLAN Adapter")}, {PRISM_USB_DEVICE @@ -55,7 +56,6 @@ static struct usb_device_id usb_prism_tbl[] = { (0x04f1, 0x3009, "JVC MP-XP7250 Builtin USB WLAN Adapter")}, {PRISM_USB_DEVICE(0x0846, 0x4110, "NetGear MA111")}, {PRISM_USB_DEVICE(0x03f3, 0x0020, "Adaptec AWN-8020 USB WLAN Adapter")}, -/* {PRISM_USB_DEVICE(0x0ace, 0x1201, "ZyDAS ZD1201 Wireless USB Adapter")}, */ {PRISM_USB_DEVICE(0x2821, 0x3300, "ASUS-WL140 Wireless USB Adapter")}, {PRISM_USB_DEVICE(0x2001, 0x3700, "DWL-122 Wireless USB Adapter")}, {PRISM_USB_DEVICE -- cgit v1.2.3 From 21b0838c1a03686277e0cfeda42015e4538b9ea3 Mon Sep 17 00:00:00 2001 From: Ameya Palande <2ameya@gmail.com> Date: Wed, 24 Feb 2010 20:18:28 +0200 Subject: Staging: crystalhd: Misc improvements for crystalhd_lnx.c This patch does following improvements: 1. Follow kernel style for comments 2. Reorganize code for readability improvement 3. Use PCI helper macros 4. Use __devinit, __devexit, __devexit_p at necessary places 5. Mark functions and data as static when it is not exported Signed-off-by: Ameya Palande <2ameya@gmail.com> Cc: Naren Sankar Cc: Jarod Wilson Cc: Scott Davilla Cc: Manu Abraham Signed-off-by: Greg Kroah-Hartman --- drivers/staging/crystalhd/crystalhd_cmds.c | 4 +- drivers/staging/crystalhd/crystalhd_lnx.c | 77 ++++++++++++------------------ drivers/staging/crystalhd/crystalhd_misc.c | 3 +- 3 files changed, 35 insertions(+), 49 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/crystalhd/crystalhd_cmds.c b/drivers/staging/crystalhd/crystalhd_cmds.c index 39c641d6b672..26145a8d0f78 100644 --- a/drivers/staging/crystalhd/crystalhd_cmds.c +++ b/drivers/staging/crystalhd/crystalhd_cmds.c @@ -948,7 +948,7 @@ BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx, struct crystalhd_user * * Called at the time of driver load. */ -BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, +BC_STATUS __devinit crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, struct crystalhd_adp *adp) { int i = 0; @@ -983,7 +983,7 @@ BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, * * Called at the time of driver un-load. */ -BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx) +BC_STATUS __devexit crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx) { BCMLOG(BCMLOG_DBG, "Deleting Command context..\n"); diff --git a/drivers/staging/crystalhd/crystalhd_lnx.c b/drivers/staging/crystalhd/crystalhd_lnx.c index 1f36b4db6fce..3eac70aa213c 100644 --- a/drivers/staging/crystalhd/crystalhd_lnx.c +++ b/drivers/staging/crystalhd/crystalhd_lnx.c @@ -1,28 +1,19 @@ /*************************************************************************** - * Copyright (c) 2005-2009, Broadcom Corporation. - * - * Name: crystalhd_lnx . c - * - * Description: - * BCM70010 Linux driver - * - * HISTORY: - * - ********************************************************************** - * This file is part of the crystalhd device driver. - * - * This driver is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, version 2 of the License. - * - * This driver is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this driver. If not, see . - **********************************************************************/ + BCM70010 Linux driver + Copyright (c) 2005-2009, Broadcom Corporation. + + This driver is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, version 2 of the License. + + This driver is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this driver. If not, see . +***************************************************************************/ #include @@ -268,7 +259,7 @@ static int chd_dec_api_cmd(struct crystalhd_adp *adp, unsigned long ua, return rc; } -/* ========================= API interfaces =================================*/ +/* API interfaces */ static int chd_dec_ioctl(struct inode *in, struct file *fd, unsigned int cmd, unsigned long ua) { @@ -358,7 +349,7 @@ static const struct file_operations chd_dec_fops = { .release = chd_dec_close, }; -static int chd_dec_init_chdev(struct crystalhd_adp *adp) +static int __devinit chd_dec_init_chdev(struct crystalhd_adp *adp) { crystalhd_ioctl_data *temp; struct device *dev; @@ -420,7 +411,7 @@ fail: return rc; } -static void chd_dec_release_chdev(struct crystalhd_adp *adp) +static void __devexit chd_dec_release_chdev(struct crystalhd_adp *adp) { crystalhd_ioctl_data *temp = NULL; if (!adp) @@ -446,7 +437,7 @@ static void chd_dec_release_chdev(struct crystalhd_adp *adp) crystalhd_delete_elem_pool(adp); } -static int chd_pci_reserve_mem(struct crystalhd_adp *pinfo) +static int __devinit chd_pci_reserve_mem(struct crystalhd_adp *pinfo) { int rc; unsigned long bar2 = pci_resource_start(pinfo->pdev, 2); @@ -499,7 +490,7 @@ static int chd_pci_reserve_mem(struct crystalhd_adp *pinfo) return 0; } -static void chd_pci_release_mem(struct crystalhd_adp *pinfo) +static void __devexit chd_pci_release_mem(struct crystalhd_adp *pinfo) { if (!pinfo) return; @@ -514,7 +505,7 @@ static void chd_pci_release_mem(struct crystalhd_adp *pinfo) } -static void chd_dec_pci_remove(struct pci_dev *pdev) +static void __devexit chd_dec_pci_remove(struct pci_dev *pdev) { struct crystalhd_adp *pinfo; BC_STATUS sts = BC_STS_SUCCESS; @@ -542,7 +533,7 @@ static void chd_dec_pci_remove(struct pci_dev *pdev) g_adp_info = NULL; } -static int chd_dec_pci_probe(struct pci_dev *pdev, +static int __devinit chd_dec_pci_probe(struct pci_dev *pdev, const struct pci_device_id *entry) { struct crystalhd_adp *pinfo; @@ -621,7 +612,6 @@ static int chd_dec_pci_probe(struct pci_dev *pdev, g_adp_info = pinfo; return 0; - } #ifdef CONFIG_PM @@ -700,24 +690,22 @@ int chd_dec_pci_resume(struct pci_dev *pdev) } #endif -static struct pci_device_id chd_dec_pci_id_table[] = { -/* vendor, device, subvendor, subdevice, class, classmask, driver_data */ - { 0x14e4, 0x1612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 }, +static DEFINE_PCI_DEVICE_TABLE(chd_dec_pci_id_table) = { + { PCI_VDEVICE(BROADCOM, 0x1612), 8 }, { 0, }, }; +MODULE_DEVICE_TABLE(pci, chd_dec_pci_id_table); -struct pci_driver bc_chd_70012_driver = { +static struct pci_driver bc_chd_70012_driver = { .name = "Broadcom 70012 Decoder", .probe = chd_dec_pci_probe, - .remove = chd_dec_pci_remove, + .remove = __devexit_p(chd_dec_pci_remove), .id_table = chd_dec_pci_id_table, #ifdef CONFIG_PM .suspend = chd_dec_pci_suspend, .resume = chd_dec_pci_resume #endif }; -MODULE_DEVICE_TABLE(pci, chd_dec_pci_id_table); - void chd_set_log_level(struct crystalhd_adp *adp, char *arg) { @@ -744,7 +732,7 @@ struct crystalhd_adp *chd_get_adp(void) return g_adp_info; } -int __init chd_dec_module_init(void) +static int __init chd_dec_module_init(void) { int rc; @@ -759,22 +747,19 @@ int __init chd_dec_module_init(void) return rc; } +module_init(chd_dec_module_init); -void __exit chd_dec_module_cleanup(void) +static void __exit chd_dec_module_cleanup(void) { BCMLOG(BCMLOG_DATA, "unloading crystalhd %d.%d.%d \n", crystalhd_kmod_major, crystalhd_kmod_minor, crystalhd_kmod_rev); pci_unregister_driver(&bc_chd_70012_driver); } - +module_exit(chd_dec_module_cleanup); MODULE_AUTHOR("Naren Sankar "); MODULE_AUTHOR("Prasad Bolisetty "); MODULE_DESCRIPTION(CRYSTAL_HD_NAME); MODULE_LICENSE("GPL"); MODULE_ALIAS("bcm70012"); - -module_init(chd_dec_module_init); -module_exit(chd_dec_module_cleanup); - diff --git a/drivers/staging/crystalhd/crystalhd_misc.c b/drivers/staging/crystalhd/crystalhd_misc.c index 32e632c2ab3e..587dcc477865 100644 --- a/drivers/staging/crystalhd/crystalhd_misc.c +++ b/drivers/staging/crystalhd/crystalhd_misc.c @@ -959,7 +959,8 @@ void crystalhd_destroy_dio_pool(struct crystalhd_adp *adp) * Create general purpose list element pool to hold pending, * and active requests. */ -int crystalhd_create_elem_pool(struct crystalhd_adp *adp, uint32_t pool_size) +int __devinit crystalhd_create_elem_pool(struct crystalhd_adp *adp, + uint32_t pool_size) { uint32_t i; crystalhd_elem_t *temp; -- cgit v1.2.3 From c852ab66727558e7fb9c994a12ff30cc3d0e2448 Mon Sep 17 00:00:00 2001 From: Sven-Thorsten Dietrich Date: Tue, 23 Feb 2010 13:59:18 -0800 Subject: Staging: make drivers use spin_lock_init() This fixes some RT-triggered compile errors and typos. Signed-off-by: Sven-Thorsten Dietrich Acked-by: Marek Lindner Acked-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/staging/batman-adv/device.c | 2 +- drivers/staging/iio/ring_generic.h | 3 +-- drivers/staging/iio/ring_sw.c | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/batman-adv/device.c b/drivers/staging/batman-adv/device.c index 451898cd9ecb..e7f44215b5f3 100644 --- a/drivers/staging/batman-adv/device.c +++ b/drivers/staging/batman-adv/device.c @@ -118,7 +118,7 @@ int bat_device_open(struct inode *inode, struct file *file) INIT_LIST_HEAD(&device_client->queue_list); device_client->queue_len = 0; device_client->index = i; - device_client->lock = __SPIN_LOCK_UNLOCKED(device_client->lock); + spin_lock_init(&device_client->lock); init_waitqueue_head(&device_client->queue_wait); file->private_data = device_client; diff --git a/drivers/staging/iio/ring_generic.h b/drivers/staging/iio/ring_generic.h index 93b91b28a02f..09044adf7327 100644 --- a/drivers/staging/iio/ring_generic.h +++ b/drivers/staging/iio/ring_generic.h @@ -146,8 +146,7 @@ static inline void __iio_init_ring_buffer(struct iio_ring_buffer *ring, ring->length = length; ring->loopcount = 0; ring->shared_ev_pointer.ev_p = 0; - ring->shared_ev_pointer.lock = - __SPIN_LOCK_UNLOCKED(ring->shared_ev_pointer->loc); + spin_lock_init(&ring->shared_ev_pointer.lock); } /** diff --git a/drivers/staging/iio/ring_sw.c b/drivers/staging/iio/ring_sw.c index b746cf603225..6f7f4d5a93f3 100644 --- a/drivers/staging/iio/ring_sw.c +++ b/drivers/staging/iio/ring_sw.c @@ -20,7 +20,7 @@ static inline int __iio_init_sw_ring_buffer(struct iio_sw_ring_buffer *ring, return -EINVAL; __iio_init_ring_buffer(&ring->buf, bytes_per_datum, length); - ring->use_lock = __SPIN_LOCK_UNLOCKED((ring)->use_lock); + spin_lock_init(&ring->use_lock); ring->data = kmalloc(length*ring->buf.bpd, GFP_KERNEL); ring->read_p = 0; ring->write_p = 0; -- cgit v1.2.3 From 2f22560880786acceb6bc63cbda7125e8d9a2206 Mon Sep 17 00:00:00 2001 From: Florian Schilhabel Date: Fri, 19 Feb 2010 20:10:00 +0100 Subject: Staging: rtl8192su: Remove Firmware from r8192SU_HWImg.c Because the Firmware is loaded from RTL8192SU/rtl8192sfw.bin, it it save, to remove it from r8192SU_HWImg.c Signed-off-by: Florian Schilhabel Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192su/r8192SU_HWImg.c | 4276 --------------------------- drivers/staging/rtl8192su/r8192SU_HWImg.h | 2 - drivers/staging/rtl8192su/r8192S_firmware.c | 125 +- drivers/staging/rtl8192su/r8192S_firmware.h | 7 - drivers/staging/rtl8192su/r8192U.h | 1 - 5 files changed, 33 insertions(+), 4378 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192su/r8192SU_HWImg.c b/drivers/staging/rtl8192su/r8192SU_HWImg.c index cbb65795a302..ba8e12c209ca 100644 --- a/drivers/staging/rtl8192su/r8192SU_HWImg.c +++ b/drivers/staging/rtl8192su/r8192SU_HWImg.c @@ -2,4282 +2,6 @@ #include "r8192SU_HWImg.h" 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-0x00,0x00,0x00,0x00,0x00,0x26,0x65,0x60,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x02, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0xf2,0x30,0xb8,0xff,0xff,0xff,0xff, -}; - u8 Rtl8192SUFwMainArray[MainArrayLength] = { 0x0, }; diff --git a/drivers/staging/rtl8192su/r8192SU_HWImg.h b/drivers/staging/rtl8192su/r8192SU_HWImg.h index 96b15252ea86..36e84aff6ed6 100644 --- a/drivers/staging/rtl8192su/r8192SU_HWImg.h +++ b/drivers/staging/rtl8192su/r8192SU_HWImg.h @@ -5,8 +5,6 @@ /*Created on 2009/ 3/ 6, 5:29*/ -#define ImgArrayLength 68368 -extern u8 Rtl8192SUFwImgArray[ImgArrayLength]; #define MainArrayLength 1 extern u8 Rtl8192SUFwMainArray[MainArrayLength]; #define DataArrayLength 1 diff --git a/drivers/staging/rtl8192su/r8192S_firmware.c b/drivers/staging/rtl8192su/r8192S_firmware.c index ff65bd125afc..752a3f1fb3f5 100644 --- a/drivers/staging/rtl8192su/r8192S_firmware.c +++ b/drivers/staging/rtl8192su/r8192S_firmware.c @@ -360,117 +360,58 @@ bool FirmwareDownload92S(struct net_device *dev) RT_TRACE(COMP_FIRMWARE, " --->FirmwareDownload92S()\n"); - //3// - //3 //<1> Open Image file, and map file to contineous memory if open file success. - //3 // or read image file from array. Default load from BIN file - //3// - priv->firmware_source = FW_SOURCE_IMG_FILE;// We should decided by Reg. - - switch( priv->firmware_source ) +/* +* Load the firmware from RTL8192SU/rtl8192sfw.bin +*/ + if(pFirmware->szFwTmpBufferLen == 0) { - case FW_SOURCE_IMG_FILE: - if(pFirmware->szFwTmpBufferLen == 0) - { - - rc = request_firmware(&fw_entry, pFwImageFileName[ulInitStep],&priv->udev->dev);//===>1 - if(rc < 0 ) { - RT_TRACE(COMP_ERR, "request firmware fail!\n"); - goto DownloadFirmware_Fail; - } - - if(fw_entry->size > sizeof(pFirmware->szFwTmpBuffer)) - { - RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n"); - release_firmware(fw_entry); - goto DownloadFirmware_Fail; - } + rc = request_firmware(&fw_entry, pFwImageFileName[ulInitStep],&priv->udev->dev); + if(rc < 0 ) { + RT_TRACE(COMP_ERR, "request firmware fail!\n"); + goto DownloadFirmware_Fail; + } - memcpy(pFirmware->szFwTmpBuffer,fw_entry->data,fw_entry->size); - pFirmware->szFwTmpBufferLen = fw_entry->size; + if(fw_entry->size > sizeof(pFirmware->szFwTmpBuffer)) { + RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n"); release_firmware(fw_entry); - - pucMappedFile = pFirmware->szFwTmpBuffer; - file_length = pFirmware->szFwTmpBufferLen; - - //Retrieve FW header. - pFirmware->pFwHeader = (PRT_8192S_FIRMWARE_HDR) pucMappedFile; - pFwHdr = pFirmware->pFwHeader; - RT_TRACE(COMP_FIRMWARE,"signature:%x, version:%x, size:%x, imemsize:%x, sram size:%x\n", \ - pFwHdr->Signature, pFwHdr->Version, pFwHdr->DMEMSize, \ - pFwHdr->IMG_IMEM_SIZE, pFwHdr->IMG_SRAM_SIZE); - pFirmware->FirmwareVersion = byte(pFwHdr->Version ,0); - if ((pFwHdr->IMG_IMEM_SIZE==0) || (pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM))) - { - RT_TRACE(COMP_ERR, "%s: memory for data image is less than IMEM required\n",\ - __FUNCTION__); - goto DownloadFirmware_Fail; - } else { - pucMappedFile+=FwHdrSize; - - //Retrieve IMEM image. - memcpy(pFirmware->FwIMEM, pucMappedFile, pFwHdr->IMG_IMEM_SIZE); - pFirmware->FwIMEMLen = pFwHdr->IMG_IMEM_SIZE; - } - - if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM)) - { - RT_TRACE(COMP_ERR, "%s: memory for data image is less than EMEM required\n",\ - __FUNCTION__); - goto DownloadFirmware_Fail; - } else { - pucMappedFile += pFirmware->FwIMEMLen; - - /* Retriecve EMEM image */ - memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE);//===>6 - pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE; - } - - + goto DownloadFirmware_Fail; } - break; - case FW_SOURCE_HEADER_FILE: -#if 1 -#define Rtl819XFwImageArray Rtl8192SUFwImgArray - //2008.11.10 Add by tynli. - pucMappedFile = Rtl819XFwImageArray; - ulFileLength = ImgArrayLength; + memcpy(pFirmware->szFwTmpBuffer,fw_entry->data,fw_entry->size); + pFirmware->szFwTmpBufferLen = fw_entry->size; + release_firmware(fw_entry); + + pucMappedFile = pFirmware->szFwTmpBuffer; + file_length = pFirmware->szFwTmpBufferLen; - RT_TRACE(COMP_INIT,"Fw download from header.\n"); - /* Retrieve FW header*/ + /* Retrieve FW header. */ pFirmware->pFwHeader = (PRT_8192S_FIRMWARE_HDR) pucMappedFile; pFwHdr = pFirmware->pFwHeader; RT_TRACE(COMP_FIRMWARE,"signature:%x, version:%x, size:%x, imemsize:%x, sram size:%x\n", \ pFwHdr->Signature, pFwHdr->Version, pFwHdr->DMEMSize, \ pFwHdr->IMG_IMEM_SIZE, pFwHdr->IMG_SRAM_SIZE); pFirmware->FirmwareVersion = byte(pFwHdr->Version ,0); - - if ((pFwHdr->IMG_IMEM_SIZE==0) || (pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM))) - { - printk("FirmwareDownload92S(): memory for data image is less than IMEM required\n"); + if ((pFwHdr->IMG_IMEM_SIZE==0) || (pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM))) { + RT_TRACE(COMP_ERR, "%s: memory for data image is less than IMEM required\n",\ + __FUNCTION__); goto DownloadFirmware_Fail; } else { pucMappedFile+=FwHdrSize; - //Retrieve IMEM image. + /* Retrieve IMEM image. */ memcpy(pFirmware->FwIMEM, pucMappedFile, pFwHdr->IMG_IMEM_SIZE); pFirmware->FwIMEMLen = pFwHdr->IMG_IMEM_SIZE; } - if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM)) - { - printk(" FirmwareDownload92S(): memory for data image is less than EMEM required\n"); - goto DownloadFirmware_Fail; - } else { - pucMappedFile+= pFirmware->FwIMEMLen; - - //Retriecve EMEM image. - memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE); - pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE; - } -#endif - break; - default: - break; + if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM)) { + RT_TRACE(COMP_ERR, "%s: memory for data image is less than EMEM required\n",\ + __FUNCTION__); + goto DownloadFirmware_Fail; + } else { + pucMappedFile += pFirmware->FwIMEMLen; + /* Retriecve EMEM image */ + memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE);//===>6 + pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE; + } } FwStatus = FirmwareGetNextStatus(pFirmware->FWStatus); diff --git a/drivers/staging/rtl8192su/r8192S_firmware.h b/drivers/staging/rtl8192su/r8192S_firmware.h index c525380e6473..2c2cf8032ded 100644 --- a/drivers/staging/rtl8192su/r8192S_firmware.h +++ b/drivers/staging/rtl8192su/r8192S_firmware.h @@ -59,12 +59,6 @@ typedef enum _desc_packet_type_e{ DESC_PACKET_TYPE_NORMAL = 1, }desc_packet_type_e; -typedef enum _firmware_source{ - FW_SOURCE_IMG_FILE = 0, - FW_SOURCE_HEADER_FILE = 1, -}firmware_source_e, *pfirmware_source_e; - - typedef enum _opt_rst_type{ OPT_SYSTEM_RESET = 0, OPT_FIRMWARE_RESET = 1, @@ -185,7 +179,6 @@ typedef enum _FIRMWARE_8192S_STATUS{ #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k typedef struct _rt_firmware{ - firmware_source_e eFWSource; PRT_8192S_FIRMWARE_HDR pFwHeader; FIRMWARE_8192S_STATUS FWStatus; u16 FirmwareVersion; diff --git a/drivers/staging/rtl8192su/r8192U.h b/drivers/staging/rtl8192su/r8192U.h index 2a11e0113d3a..ba87623f32ee 100644 --- a/drivers/staging/rtl8192su/r8192U.h +++ b/drivers/staging/rtl8192su/r8192U.h @@ -1258,7 +1258,6 @@ typedef struct r8192_priv u8 Rf_Mode; //add for Firmware RF -R/W switch prt_firmware pFirmware; rtl819xUsb_loopback_e LoopbackMode; - firmware_source_e firmware_source; bool usb_error; u16 EEPROMTxPowerDiff; -- cgit v1.2.3 From 29a1fbc88b822497a0a4d8e9cb7d8a471e70f339 Mon Sep 17 00:00:00 2001 From: Florian Schilhabel Date: Fri, 19 Feb 2010 20:11:37 +0100 Subject: Staging: rtl8192su: fix for rtl819xU:Error TX URB for zero byte xxx, error -2 according to 'linux device drivers', ENOENT, ECONNRESET, ESHUTDOWN are not real transmission errors. also, a little cosmetics. Signed-off-by: Florian Schilhabel Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192su/r8192U_core.c | 36 +++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192su/r8192U_core.c b/drivers/staging/rtl8192su/r8192U_core.c index 23d1d35be7ed..8393bc57bdfc 100644 --- a/drivers/staging/rtl8192su/r8192U_core.c +++ b/drivers/staging/rtl8192su/r8192U_core.c @@ -2340,25 +2340,24 @@ short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb) skb->len, rtl8192_tx_isr, skb); status = usb_submit_urb(tx_urb, GFP_ATOMIC); - if (!status){ -//we need to send 0 byte packet whenever 512N bytes/64N(HIGN SPEED/NORMAL SPEED) bytes packet has been transmitted. Otherwise, it will be halt to wait for another packet. WB. 2008.08.27 + if (!status) { + /* + * we need to send 0 byte packet whenever 512N bytes/64N(HIGN SPEED/NORMAL SPEED) bytes packet has been transmitted. + * Otherwise, it will be halt to wait for another packet. WB. 2008.08.27 + */ bool bSend0Byte = false; u8 zero = 0; - if(udev->speed == USB_SPEED_HIGH) - { + if(udev->speed == USB_SPEED_HIGH) { if (skb->len > 0 && skb->len % 512 == 0) bSend0Byte = true; } - else - { + else { if (skb->len > 0 && skb->len % 64 == 0) bSend0Byte = true; } - if (bSend0Byte) - { -#if 1 + if (bSend0Byte) { tx_urb_zero = usb_alloc_urb(0,GFP_ATOMIC); - if(!tx_urb_zero){ + if(!tx_urb_zero) { RT_TRACE(COMP_ERR, "can't alloc urb for zero byte\n"); return -ENOMEM; } @@ -2366,16 +2365,23 @@ short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb) usb_sndbulkpipe(udev,idx_pipe), &zero, 0, tx_zero_isr, dev); status = usb_submit_urb(tx_urb_zero, GFP_ATOMIC); - if (status){ - RT_TRACE(COMP_ERR, "Error TX URB for zero byte %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]), status); - return -1; + switch (status) { + case 0: + break; + case -ECONNRESET: + case -ENOENT: + case -ESHUTDOWN: + break; + default: + RT_TRACE(COMP_ERR, "Error TX URB for zero byte %d, error %d", + atomic_read(&priv->tx_pending[tcb_desc->queue_index]), status); + return -1; } -#endif } dev->trans_start = jiffies; atomic_inc(&priv->tx_pending[tcb_desc->queue_index]); return 0; - }else{ + } else { RT_TRACE(COMP_ERR, "Error TX URB %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]), status); return -1; -- cgit v1.2.3 From a99840b1aa66d3797bfe0be4fb6982bba62d815b Mon Sep 17 00:00:00 2001 From: Florian Schilhabel Date: Fri, 19 Feb 2010 20:11:54 +0100 Subject: Staging: rtl8192su: re-enable tx-stats currently, interface statistics look like this: wlan0 Link encap:Ethernet HWaddr xx:xx:xx:xx:xx:xx inet addr:xxx.xxx.xxx.xxx Bcast:xxx.xxx.xxx.xxx Mask:xxx.xxx.xxx.xxx UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:435 errors:0 dropped:1 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:456758 (446.0 Kb) TX bytes:0 (0.0 b) after re-enabling the tx-stats it looks like this: wlan0 Link encap:Ethernet HWaddr xx:xx:xx:xx:xx:xx inet addr:xxx.xxx.xxx.xxx Bcast:xxx.xxx.xxx.xxx Mask:xxx.xxx.xxx.xxx UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:1269 errors:0 dropped:1 overruns:0 frame:0 TX packets:1049 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:1667442 (1.5 Mb) TX bytes:82606 (80.6 Kb) Signed-off-by: Florian Schilhabel Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c index e46f3bc6a21a..1dfc9458f833 100644 --- a/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c @@ -2145,8 +2145,8 @@ void ieee80211_softmac_xmit(struct ieee80211_txb *txb, struct ieee80211_device * ieee80211_sta_wakeup(ieee,0); /* update the tx status */ -// ieee->stats.tx_bytes += txb->payload_size; -// ieee->stats.tx_packets++; + ieee->stats.tx_bytes += txb->payload_size; + ieee->stats.tx_packets++; tcb_desc = (cb_desc *)(txb->fragments[0]->cb + MAX_DEV_ADDR_SIZE); if(tcb_desc->bMulticast) { ieee->stats.multicast++; -- cgit v1.2.3 From 7bd795bfcd7eb2f2962d458bf787d5ee0d1167cd Mon Sep 17 00:00:00 2001 From: Florian Schilhabel Date: Fri, 19 Feb 2010 20:12:12 +0100 Subject: Staging: rtl8192su: use list_for_each_safe() in ieee80211_crypto_deinit Signed-off-by: Florian Schilhabel Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192su/TODO | 1 - drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.c | 19 ++++++++++--------- 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rtl8192su/TODO b/drivers/staging/rtl8192su/TODO index f11eec700030..3c8da157a93c 100644 --- a/drivers/staging/rtl8192su/TODO +++ b/drivers/staging/rtl8192su/TODO @@ -4,7 +4,6 @@ TODO: - cleanup ieee80211.h - move rtl8192su's specific code out from ieee80211.h - abstract rtl819su's specific code - - use list_for_each_safe() in ieee80211_crypto_deinit - switch to use shared "librtl" instead of private ieee80211 stack - switch to use LIB80211 - switch to use MAC80211 diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.c index 521e7b989934..c4640e63196b 100644 --- a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.c +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.c @@ -226,19 +226,20 @@ out: void __exit ieee80211_crypto_deinit(void) { struct list_head *ptr, *n; + struct ieee80211_crypto_alg *alg = NULL; if (hcrypt == NULL) return; - for (ptr = hcrypt->algs.next, n = ptr->next; ptr != &hcrypt->algs; - ptr = n, n = ptr->next) { - struct ieee80211_crypto_alg *alg = - (struct ieee80211_crypto_alg *) ptr; - list_del(ptr); - printk(KERN_DEBUG "ieee80211_crypt: unregistered algorithm " - "'%s' (deinit)\n", alg->ops->name); - kfree(alg); + list_for_each_safe(ptr, n, &hcrypt->algs) { + alg = list_entry(ptr, struct ieee80211_crypto_alg, list); + if (alg) { + list_del(ptr); + printk(KERN_DEBUG + "ieee80211_crypt: unregistered algorithm '%s' (deinit)\n", + alg->ops->name); + kfree(alg); + } } - kfree(hcrypt); } -- cgit v1.2.3 From 02c7b237f6a01f580319187d4bdbf712b27a5460 Mon Sep 17 00:00:00 2001 From: Alessio Igor Bogani Date: Fri, 26 Feb 2010 08:44:27 +0100 Subject: Staging: Cleanup useless headers BKL isn't anymore present into these files thus it is no necessary still include smp_lock.h. Signed-off-by: Alessio Igor Bogani Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/comedi_compat32.c | 1 - drivers/staging/comedi/drivers/usbdux.c | 1 - drivers/staging/comedi/drivers/usbduxfast.c | 1 - drivers/staging/panel/panel.c | 1 - 4 files changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/comedi_compat32.c b/drivers/staging/comedi/comedi_compat32.c index a9fdcda5db7a..581aa5fee2e3 100644 --- a/drivers/staging/comedi/comedi_compat32.c +++ b/drivers/staging/comedi/comedi_compat32.c @@ -26,7 +26,6 @@ #define __NO_VERSION__ #include "comedi.h" -#include #include #include "comedi_compat32.h" diff --git a/drivers/staging/comedi/drivers/usbdux.c b/drivers/staging/comedi/drivers/usbdux.c index bcf46dab2052..8942ae45708d 100644 --- a/drivers/staging/comedi/drivers/usbdux.c +++ b/drivers/staging/comedi/drivers/usbdux.c @@ -95,7 +95,6 @@ sampling rate. If you sample two channels you get 4kHz and so on. #include #include #include -#include #include #include #include diff --git a/drivers/staging/comedi/drivers/usbduxfast.c b/drivers/staging/comedi/drivers/usbduxfast.c index b96cf3b96fd3..e89b81812538 100644 --- a/drivers/staging/comedi/drivers/usbduxfast.c +++ b/drivers/staging/comedi/drivers/usbduxfast.c @@ -44,7 +44,6 @@ #include #include #include -#include #include #include #include "comedi_fc.h" diff --git a/drivers/staging/panel/panel.c b/drivers/staging/panel/panel.c index 95c93e82ccec..377884f3480d 100644 --- a/drivers/staging/panel/panel.c +++ b/drivers/staging/panel/panel.c @@ -41,7 +41,6 @@ #include #include #include -#include #include #include #include -- cgit v1.2.3 From 48d07f2bf3fd6d0bbe7577f1844f7edfaf7399f6 Mon Sep 17 00:00:00 2001 From: d binderman Date: Sun, 21 Feb 2010 10:02:59 +0000 Subject: Staging: comedi: amplc_pci224.c: coding style cleanups Signed-off-by: David Binderman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/amplc_pci224.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/amplc_pci224.c b/drivers/staging/comedi/drivers/amplc_pci224.c index d9836879355e..b41e5e5963aa 100644 --- a/drivers/staging/comedi/drivers/amplc_pci224.c +++ b/drivers/staging/comedi/drivers/amplc_pci224.c @@ -1536,20 +1536,12 @@ static int pci224_detach(struct comedi_device *dev) s = dev->subdevices + 0; /* AO subdevice */ - if (s->range_table_list) { - kfree(s->range_table_list); - } + kfree(s->range_table_list); } if (devpriv) { - if (devpriv->ao_readback) { - kfree(devpriv->ao_readback); - } - if (devpriv->ao_scan_vals) { - kfree(devpriv->ao_scan_vals); - } - if (devpriv->ao_scan_order) { - kfree(devpriv->ao_scan_order); - } + kfree(devpriv->ao_readback); + kfree(devpriv->ao_scan_vals); + kfree(devpriv->ao_scan_order); if (devpriv->pci_dev) { if (dev->iobase) { comedi_pci_disable(devpriv->pci_dev); -- cgit v1.2.3 From 015fadba7c30a082cc8efa0f353be096b75e3952 Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:14:56 +0100 Subject: Staging: comedi: addi_amcc_S5920.c: Checkpatch cleanup WARNING: braces {} are not necessary for any arm of this statement + if (i_Counter == 0) { [...] + } else { [...] Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/addi-data/addi_amcc_S5920.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/addi-data/addi_amcc_S5920.c b/drivers/staging/comedi/drivers/addi-data/addi_amcc_S5920.c index bd7e4619b3df..97c10aaa691d 100644 --- a/drivers/staging/comedi/drivers/addi-data/addi_amcc_S5920.c +++ b/drivers/staging/comedi/drivers/addi-data/addi_amcc_S5920.c @@ -173,11 +173,10 @@ int i_AddiHeaderRW_ReadEeprom(int i_NbOfWordsToRead, } while (dw_eeprom_busy == EEPROM_BUSY); /* Select the upper address part */ - if (i_Counter == 0) { + if (i_Counter == 0) b_ReadLowByte = pb_ReadByte[0]; - } else { + else b_ReadHighByte = pb_ReadByte[0]; - } /* Sleep */ msleep(1); -- cgit v1.2.3 From a9ecb5bb5847b084d6d8bf5c60549fd5598c053a Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:14:57 +0100 Subject: Staging: comedi: addi_common.h: Checkpatch cleanup ERROR: code indent should use tabs where possible + const struct comedi_lrange *pr_AiRangelist;^I/* rangelist for A/D */$ ERROR: code indent should use tabs where possible + const struct comedi_lrange *pr_AoRangelist;^I/* rangelist for D/A */$ Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/addi-data/addi_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/addi-data/addi_common.h b/drivers/staging/comedi/drivers/addi-data/addi_common.h index 3ab27cf0facc..caeb6fd2d9b1 100644 --- a/drivers/staging/comedi/drivers/addi-data/addi_common.h +++ b/drivers/staging/comedi/drivers/addi-data/addi_common.h @@ -77,8 +77,8 @@ struct addi_board { int i_NbrAoChannel; /* num of D/A chans */ int i_AiMaxdata; /* resolution of A/D */ int i_AoMaxdata; /* resolution of D/A */ - const struct comedi_lrange *pr_AiRangelist; /* rangelist for A/D */ - const struct comedi_lrange *pr_AoRangelist; /* rangelist for D/A */ + const struct comedi_lrange *pr_AiRangelist; /* rangelist for A/D */ + const struct comedi_lrange *pr_AoRangelist; /* rangelist for D/A */ int i_NbrDiChannel; /* Number of DI channels */ int i_NbrDoChannel; /* Number of DO channels */ -- cgit v1.2.3 From 882e1233a1abb650149496b33eaeb1d09bbc0b7a Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:14:58 +0100 Subject: Staging: comedi: hwdrv_apci1032.c: Checkpatch cleanup ERROR: do not initialise externals to 0 or NULL +unsigned int ui_InterruptStatus = 0; WARNING: braces {} are not necessary for single statement blocks + else { + outl(0x6, devpriv->iobase + APCI1032_DIGITAL_IP_IRQ); + } /* else if(data[1] == ADDIDATA_OR) */ WARNING: braces {} are not necessary for single statement blocks + if (data[1] == 1) { + *data = ui_InterruptStatus; + } /* if(data[1]==1) */ Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/addi-data/hwdrv_apci1032.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1032.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1032.c index 27c68aac32d1..fe06789699f3 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1032.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci1032.c @@ -54,7 +54,7 @@ You should also find the complete GPL in the COPYING file accompanying this sour #include "hwdrv_apci1032.h" #include /* Global variables */ -unsigned int ui_InterruptStatus = 0; +unsigned int ui_InterruptStatus; /* +----------------------------------------------------------------------------+ @@ -108,9 +108,9 @@ int i_APCI1032_ConfigDigitalInput(struct comedi_device *dev, struct comedi_subde ui_TmpValue = inl(devpriv->iobase + APCI1032_DIGITAL_IP_IRQ); } /* if (data[1] == ADDIDATA_OR) */ - else { + else outl(0x6, devpriv->iobase + APCI1032_DIGITAL_IP_IRQ); - } /* else if(data[1] == ADDIDATA_OR) */ + /* else if(data[1] == ADDIDATA_OR) */ } /* if( data[0] == ADDIDATA_ENABLE) */ else { ul_Command1 = ul_Command1 & 0xFFFF0000; @@ -221,9 +221,9 @@ int i_APCI1032_ReadMoreDigitalInput(struct comedi_device *dev, struct comedi_sub } /* switch(ui_NoOfChannels) */ } /* if(data[1]==0) */ else { - if (data[1] == 1) { + if (data[1] == 1) *data = ui_InterruptStatus; - } /* if(data[1]==1) */ + /* if(data[1]==1) */ } /* else if(data[1]==0) */ return insn->n; } -- cgit v1.2.3 From 2d238b2972bf365153ae8d699177c7a19a5f3056 Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:14:59 +0100 Subject: Staging: comedi: cb_pcidas.c: Checkpatch cleanup ERROR: "foo * bar" should be "foo *bar" + uint8_t * data); WARNING: braces {} are not necessary for single statement blocks + if (devpriv->s5933_config) { + comedi_pci_disable(devpriv->pci_dev); + } WARNING: braces {} are not necessary for single statement blocks + if (cmd->stop_src == TRIG_COUNT) { + devpriv->count = cmd->chanlist_len * cmd->stop_arg; + } WARNING: braces {} are not necessary for single statement blocks + if (cmd->stop_src == TRIG_COUNT) { + devpriv->ao_count = cmd->chanlist_len * cmd->stop_arg; + } WARNING: braces {} are not necessary for single statement blocks + if (cmd->stop_src == TRIG_COUNT) { + devpriv->ao_count -= num_points; + } WARNING: braces {} are not necessary for single statement blocks + if (dev->attached == 0) { + return IRQ_NONE; + } WARNING: braces {} are not necessary for single statement blocks + if ((status & (INT | EOAI | LADFUL | DAHFI | DAEMI)) == 0) { + comedi_error(dev, "spurious interrupt"); + } WARNING: braces {} are not necessary for single statement blocks + if (status & (DAHFI | DAEMI)) { + handle_ao_interrupt(dev, status); + } WARNING: braces {} are not necessary for single statement blocks + if (async->cmd.stop_src == TRIG_COUNT) { + devpriv->ao_count -= num_points; + } ERROR: "foo * bar" should be "foo *bar" + uint8_t * data) Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/cb_pcidas.c | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/cb_pcidas.c b/drivers/staging/comedi/drivers/cb_pcidas.c index f3e66c440a38..434591de37c5 100644 --- a/drivers/staging/comedi/drivers/cb_pcidas.c +++ b/drivers/staging/comedi/drivers/cb_pcidas.c @@ -518,7 +518,7 @@ static int trimpot_7376_write(struct comedi_device *dev, uint8_t value); static int trimpot_8402_write(struct comedi_device *dev, unsigned int channel, uint8_t value); static int nvram_read(struct comedi_device *dev, unsigned int address, - uint8_t * data); + uint8_t *data); static inline unsigned int cal_enable_bits(struct comedi_device *dev) { @@ -760,9 +760,8 @@ static int cb_pcidas_detach(struct comedi_device *dev) if (dev->subdevices) subdev_8255_cleanup(dev, dev->subdevices + 2); if (devpriv && devpriv->pci_dev) { - if (devpriv->s5933_config) { + if (devpriv->s5933_config) comedi_pci_disable(devpriv->pci_dev); - } pci_dev_put(devpriv->pci_dev); } @@ -1248,9 +1247,8 @@ static int cb_pcidas_ai_cmd(struct comedi_device *dev, cmd->flags & TRIG_ROUND_MASK); /* set number of conversions */ - if (cmd->stop_src == TRIG_COUNT) { + if (cmd->stop_src == TRIG_COUNT) devpriv->count = cmd->chanlist_len * cmd->stop_arg; - } /* enable interrupts */ spin_lock_irqsave(&dev->spinlock, flags); devpriv->adc_fifo_bits |= INTE; @@ -1449,9 +1447,8 @@ static int cb_pcidas_ao_cmd(struct comedi_device *dev, devpriv->ao_divisor2, 2); } /* set number of conversions */ - if (cmd->stop_src == TRIG_COUNT) { + if (cmd->stop_src == TRIG_COUNT) devpriv->ao_count = cmd->chanlist_len * cmd->stop_arg; - } /* set pacer source */ spin_lock_irqsave(&dev->spinlock, flags); switch (cmd->scan_begin_src) { @@ -1494,9 +1491,8 @@ static int cb_pcidas_ao_inttrig(struct comedi_device *dev, num_points * sizeof(short)); num_points = num_bytes / sizeof(short); - if (cmd->stop_src == TRIG_COUNT) { + if (cmd->stop_src == TRIG_COUNT) devpriv->ao_count -= num_points; - } /* write data to board's fifo */ outsw(devpriv->ao_registers + DACDATA, devpriv->ao_buffer, num_bytes); @@ -1534,9 +1530,8 @@ static irqreturn_t cb_pcidas_interrupt(int irq, void *d) static const int timeout = 10000; unsigned long flags; - if (dev->attached == 0) { + if (dev->attached == 0) return IRQ_NONE; - } async = s->async; async->events = 0; @@ -1558,15 +1553,13 @@ static irqreturn_t cb_pcidas_interrupt(int irq, void *d) status = inw(devpriv->control_status + INT_ADCFIFO); #ifdef CB_PCIDAS_DEBUG - if ((status & (INT | EOAI | LADFUL | DAHFI | DAEMI)) == 0) { + if ((status & (INT | EOAI | LADFUL | DAHFI | DAEMI)) == 0) comedi_error(dev, "spurious interrupt"); - } #endif /* check for analog output interrupt */ - if (status & (DAHFI | DAEMI)) { + if (status & (DAHFI | DAEMI)) handle_ao_interrupt(dev, status); - } /* check for analog input interrupts */ /* if fifo half-full */ if (status & ADHFI) { @@ -1675,9 +1668,8 @@ static void handle_ao_interrupt(struct comedi_device *dev, unsigned int status) num_points * sizeof(short)); num_points = num_bytes / sizeof(short); - if (async->cmd.stop_src == TRIG_COUNT) { + if (async->cmd.stop_src == TRIG_COUNT) devpriv->ao_count -= num_points; - } /* write data to board's fifo */ outsw(devpriv->ao_registers + DACDATA, devpriv->ao_buffer, num_points); @@ -1852,7 +1844,7 @@ static int wait_for_nvram_ready(unsigned long s5933_base_addr) } static int nvram_read(struct comedi_device *dev, unsigned int address, - uint8_t * data) + uint8_t *data) { unsigned long iobase = devpriv->s5933_config; -- cgit v1.2.3 From 20db7d7de7027ddee5df1b51b3d013568273b9df Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:15:00 +0100 Subject: Staging: comedi: cb_pcidda.c: Checkpatch cleanup WARNING: braces {} are not necessary for single statement blocks + if (devpriv->dac) { + comedi_pci_disable(devpriv->pci_dev); + } WARNING: braces {} are not necessary for single statement blocks + if (inw_p(devpriv->dac + DACALIBRATION1) & SERIAL_OUT_BIT) { + value |= 1 << (value_width - i); + } WARNING: braces {} are not necessary for single statement blocks + for (i = 0; i < max_num_caldacs; i++) { + cal2_bits |= DESELECT_CALDAC_BIT(i); + } WARNING: braces {} are not necessary for single statement blocks + for (i = 0; i < max_num_caldacs; i++) { + cal2_bits |= DESELECT_CALDAC_BIT(i); + } Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/cb_pcidda.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/cb_pcidda.c b/drivers/staging/comedi/drivers/cb_pcidda.c index 782357732eed..81829d6fd287 100644 --- a/drivers/staging/comedi/drivers/cb_pcidda.c +++ b/drivers/staging/comedi/drivers/cb_pcidda.c @@ -410,9 +410,8 @@ static int cb_pcidda_detach(struct comedi_device *dev) */ if (devpriv) { if (devpriv->pci_dev) { - if (devpriv->dac) { + if (devpriv->dac) comedi_pci_disable(devpriv->pci_dev); - } pci_dev_put(devpriv->pci_dev); } } @@ -677,9 +676,8 @@ static unsigned int cb_pcidda_serial_in(struct comedi_device *dev) for (i = 1; i <= value_width; i++) { /* read bits most significant bit first */ - if (inw_p(devpriv->dac + DACALIBRATION1) & SERIAL_OUT_BIT) { + if (inw_p(devpriv->dac + DACALIBRATION1) & SERIAL_OUT_BIT) value |= 1 << (value_width - i); - } } return value; @@ -716,9 +714,8 @@ static unsigned int cb_pcidda_read_eeprom(struct comedi_device *dev, /* send serial output stream to eeprom */ cal2_bits = SELECT_EEPROM_BIT | DESELECT_REF_DAC_BIT | DUMMY_BIT; /* deactivate caldacs (one caldac for every two channels) */ - for (i = 0; i < max_num_caldacs; i++) { + for (i = 0; i < max_num_caldacs; i++) cal2_bits |= DESELECT_CALDAC_BIT(i); - } outw_p(cal2_bits, devpriv->dac + DACALIBRATION2); /* tell eeprom we want to read */ @@ -756,9 +753,8 @@ static void cb_pcidda_write_caldac(struct comedi_device *dev, */ cal2_bits = DESELECT_REF_DAC_BIT | DUMMY_BIT; /* deactivate caldacs (one caldac for every two channels) */ - for (i = 0; i < max_num_caldacs; i++) { + for (i = 0; i < max_num_caldacs; i++) cal2_bits |= DESELECT_CALDAC_BIT(i); - } /* activate the caldac we want */ cal2_bits &= ~DESELECT_CALDAC_BIT(caldac); outw_p(cal2_bits, devpriv->dac + DACALIBRATION2); -- cgit v1.2.3 From e3a21d0ac2ee4f6c1be5314e76939867a2d0b470 Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:15:01 +0100 Subject: Staging: comedi: cb_pcidio.c: Checkpatch cleanup WARNING: braces {} are not necessary for single statement blocks + if (devpriv->dio_reg_base) { + comedi_pci_disable(devpriv->pci_dev); + } WARNING: braces {} are not necessary for single statement blocks + for (i = 0; i < thisboard->n_8255; i++) { + subdev_8255_cleanup(dev, dev->subdevices + i); + } Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/cb_pcidio.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/cb_pcidio.c b/drivers/staging/comedi/drivers/cb_pcidio.c index 7daad0a17fb1..38ccd105fa35 100644 --- a/drivers/staging/comedi/drivers/cb_pcidio.c +++ b/drivers/staging/comedi/drivers/cb_pcidio.c @@ -283,17 +283,15 @@ static int pcidio_detach(struct comedi_device *dev) printk("comedi%d: cb_pcidio: remove\n", dev->minor); if (devpriv) { if (devpriv->pci_dev) { - if (devpriv->dio_reg_base) { + if (devpriv->dio_reg_base) comedi_pci_disable(devpriv->pci_dev); - } pci_dev_put(devpriv->pci_dev); } } if (dev->subdevices) { int i; - for (i = 0; i < thisboard->n_8255; i++) { + for (i = 0; i < thisboard->n_8255; i++) subdev_8255_cleanup(dev, dev->subdevices + i); - } } return 0; } -- cgit v1.2.3 From 7c2f1946a5d41da3cfc1696944aaa420db5b5145 Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:15:02 +0100 Subject: Staging: comedi: cb_pcimdas.c: Checkpatch cleanup WARNING: braces {} are not necessary for any arm of this statement + if (thisboard->has_dio) { [...] + } else { [...] WARNING: braces {} are not necessary for single statement blocks + if (devpriv->BADR0) { + comedi_pci_disable(devpriv->pci_dev); + } Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/cb_pcimdas.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/cb_pcimdas.c b/drivers/staging/comedi/drivers/cb_pcimdas.c index cbbca05acb96..2e61727fc9a0 100644 --- a/drivers/staging/comedi/drivers/cb_pcimdas.c +++ b/drivers/staging/comedi/drivers/cb_pcimdas.c @@ -330,11 +330,10 @@ found: s = dev->subdevices + 2; /* digital i/o subdevice */ - if (thisboard->has_dio) { + if (thisboard->has_dio) subdev_8255_init(dev, s, NULL, devpriv->BADR4); - } else { + else s->type = COMEDI_SUBD_UNUSED; - } printk("attached\n"); @@ -365,9 +364,8 @@ static int cb_pcimdas_detach(struct comedi_device *dev) free_irq(dev->irq, dev); if (devpriv) { if (devpriv->pci_dev) { - if (devpriv->BADR0) { + if (devpriv->BADR0) comedi_pci_disable(devpriv->pci_dev); - } pci_dev_put(devpriv->pci_dev); } } -- cgit v1.2.3 From f1c54e82726fe51a55a18d15dc9377b8fd568ca2 Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:15:03 +0100 Subject: Staging: comedi: cb_pcimdda.c: Checkpatch cleanup WARNING: braces {} are not necessary for any arm of this statement + if (it->options[2]) { [...] + } else { [...] WARNING: braces {} are not necessary for single statement blocks + if (devpriv->registers) { + comedi_pci_disable(devpriv->pci_dev); + } Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/cb_pcimdda.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/cb_pcimdda.c b/drivers/staging/comedi/drivers/cb_pcimdda.c index 980fa0aacf92..e32a31763d50 100644 --- a/drivers/staging/comedi/drivers/cb_pcimdda.c +++ b/drivers/staging/comedi/drivers/cb_pcimdda.c @@ -284,11 +284,10 @@ static int attach(struct comedi_device *dev, struct comedi_devconfig *it) s->n_chan = thisboard->ao_chans; s->maxdata = figure_out_maxdata(thisboard->ao_bits); /* this is hard-coded here */ - if (it->options[2]) { + if (it->options[2]) s->range_table = &range_bipolar10; - } else { + else s->range_table = &range_bipolar5; - } s->insn_write = &ao_winsn; s->insn_read = &ao_rinsn; @@ -337,9 +336,8 @@ static int detach(struct comedi_device *dev) } if (devpriv->pci_dev) { - if (devpriv->registers) { + if (devpriv->registers) comedi_pci_disable(devpriv->pci_dev); - } pci_dev_put(devpriv->pci_dev); } -- cgit v1.2.3 From 426054ce11ecb416048aa0f92628fa4ba93c3a0e Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:15:04 +0100 Subject: Staging: comedi: contec_pci_dio.c: Checkpatch cleanup WARNING: braces {} are not necessary for single statement blocks + if (dev->iobase) { + comedi_pci_disable(devpriv->pci_dev); + } Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/contec_pci_dio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/contec_pci_dio.c b/drivers/staging/comedi/drivers/contec_pci_dio.c index b16d652f7763..9511814e6413 100644 --- a/drivers/staging/comedi/drivers/contec_pci_dio.c +++ b/drivers/staging/comedi/drivers/contec_pci_dio.c @@ -173,9 +173,8 @@ static int contec_detach(struct comedi_device *dev) printk("comedi%d: contec: remove\n", dev->minor); if (devpriv && devpriv->pci_dev) { - if (dev->iobase) { + if (dev->iobase) comedi_pci_disable(devpriv->pci_dev); - } pci_dev_put(devpriv->pci_dev); } -- cgit v1.2.3 From d539047c7bb3d462b4b505accbb3cc31dce87801 Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:15:05 +0100 Subject: Staging: comedi: das08_cs.c: Checkpatch cleanup ERROR: code indent should use tabs where possible + NONE$ ERROR: do not initialise statics to 0 or NULL +static struct pcmcia_device *cur_dev = NULL; Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/das08_cs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/das08_cs.c b/drivers/staging/comedi/drivers/das08_cs.c index 9b945e5fdd32..f12ef1cd6f53 100644 --- a/drivers/staging/comedi/drivers/das08_cs.c +++ b/drivers/staging/comedi/drivers/das08_cs.c @@ -34,7 +34,7 @@ This is the PCMCIA-specific support split off from the das08 driver. Options (for pcm-das08): - NONE + NONE Command support does not exist, but could be added for this board. */ @@ -52,7 +52,7 @@ Command support does not exist, but could be added for this board. #include #include -static struct pcmcia_device *cur_dev = NULL; +static struct pcmcia_device *cur_dev; #define thisboard ((const struct das08_board_struct *)dev->board_ptr) -- cgit v1.2.3 From dd105f08c0e9d4081629f96b09abadc0bb51e0d8 Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:15:06 +0100 Subject: Staging: comedi: hwdrv_apci3120.c: Checkpatch cleanup ERROR: do not initialise statics to 0 or NULL +static unsigned int ui_Temp = 0; WARNING: braces {} are not necessary for any arm of this statement + if (data[1]) { [...] + } else [...] WARNING: braces {} are not necessary for single statement blocks + for (i = 0; i < devpriv->ui_AiNbrofChannels; i++) { + devpriv->ui_AiChannelList[i] = data[4 + i]; + } ERROR: that open brace { should be on the previous line + } else /* EOC */ + { WARNING: braces {} are not necessary for any arm of this statement + if (data[1]) { [...] + } else { [...] ERROR: that open brace { should be on the previous line + if (insn->unused[0] == 222) /* second insn read */ + { WARNING: braces {} are not necessary for single statement blocks + for (i = 0; i < insn->n; i++) { + data[i] = devpriv->ui_AiReadData[i]; + } WARNING: braces {} are not necessary for single statement blocks + if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) { + err++; + } ERROR: that open brace { should be on the previous line + if (cmd->scan_begin_src == TRIG_TIMER) /* Test Delay timing */ + { ERROR: that open brace { should be on the previous line + if (cmd->convert_src == TRIG_TIMER) /* Test Acquisition timing */ + { WARNING: braces {} are not necessary for any arm of this statement + if (cmd->stop_src == TRIG_COUNT) { [...] + } else { [...] WARNING: braces {} are not necessary for single statement blocks + if (devpriv->b_ExttrigEnable == APCI3120_ENABLE) { + i_APCI3120_ExttrigEnable(dev); /* activate EXT trigger */ + } WARNING: braces {} are not necessary for single statement blocks + if (dmalen0 > (devpriv->ui_AiDataLength)) { + dmalen0 = devpriv->ui_AiDataLength; + } WARNING: braces {} are not necessary for single statement blocks + if (dmalen1 > (devpriv->ui_AiDataLength)) { + dmalen1 = devpriv->ui_AiDataLength; + } WARNING: braces {} are not necessary for any arm of this statement + if (CR_RANGE(chanlist[i]) < APCI3120_BIPOLAR_RANGES) { [...] + } else { [...] ERROR: that open brace { should be on the previous line + if (devpriv->b_EocEosInterrupt == APCI3120_ENABLE) /* enable this in without DMA ??? */ + { ERROR: that open brace { should be on the previous line + if (data[0] == APCI3120_TIMER) /* initialize timer */ + { ERROR: that open brace { should be on the previous line + } else /* Initialize Watch dog */ + { ERROR: that open brace { should be on the previous line + if (data[0] == 2) /* write new value */ + { ERROR: that open brace { should be on the previous line + if (devpriv->b_Timer2Mode == APCI3120_TIMER) /* start timer */ + { ERROR: that open brace { should be on the previous line + } else /* start watch dog */ + { ERROR: that open brace { should be on the previous line + if (devpriv->b_Timer2Mode == APCI3120_TIMER) /* start timer */ + { ERROR: that open brace { should be on the previous line + } else /* Read watch dog status */ + { WARNING: braces {} are not necessary for single statement blocks + if (!devpriv->b_OutputMemoryStatus) { + ui_Temp = 0; + + } /* if(!devpriv->b_OutputMemoryStatus ) */ ERROR: code indent should use tabs where possible + data[0] Value to be written$ ERROR: code indent should use tabs where possible + data[1] :1 Set digital o/p ON$ ERROR: code indent should use tabs where possible + data[1] 2 Set digital o/p OFF with memory ON$ ERROR: that open brace { should be on the previous line + if (ui_Range) /* if 1 then unipolar */ + { ERROR: that open brace { should be on the previous line + } else /* if 0 then bipolar */ + { ERROR: that open brace { should be on the previous line + do /* Waiting of DA_READY BIT */ + { Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- .../comedi/drivers/addi-data/hwdrv_apci3120.c | 119 ++++++++------------- 1 file changed, 46 insertions(+), 73 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c index 07123fd766a3..f93ddd4eb06c 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c @@ -45,7 +45,7 @@ You should also find the complete GPL in the COPYING file accompanying this sour */ #include "hwdrv_apci3120.h" -static unsigned int ui_Temp = 0; +static unsigned int ui_Temp; /* FUNCTION DEFINITIONS */ @@ -98,25 +98,22 @@ int i_APCI3120_InsnConfigAnalogInput(struct comedi_device *dev, struct comedi_su devpriv->b_InterruptMode = APCI3120_EOS_MODE; - if (data[1]) { + if (data[1]) devpriv->b_EocEosInterrupt = APCI3120_ENABLE; - } else + else devpriv->b_EocEosInterrupt = APCI3120_DISABLE; /* Copy channel list and Range List to devpriv */ devpriv->ui_AiNbrofChannels = data[3]; - for (i = 0; i < devpriv->ui_AiNbrofChannels; i++) { + for (i = 0; i < devpriv->ui_AiNbrofChannels; i++) devpriv->ui_AiChannelList[i] = data[4 + i]; - } - } else /* EOC */ - { + } else { /* EOC */ devpriv->b_InterruptMode = APCI3120_EOC_MODE; - if (data[1]) { + if (data[1]) devpriv->b_EocEosInterrupt = APCI3120_ENABLE; - } else { + else devpriv->b_EocEosInterrupt = APCI3120_DISABLE; - } } return insn->n; @@ -166,13 +163,9 @@ int i_APCI3120_InsnReadAnalogInput(struct comedi_device *dev, struct comedi_subd devpriv->us_OutputRegister = 0; /* devpriv->b_DigitalOutputRegister=0; */ - if (insn->unused[0] == 222) /* second insn read */ - { - - for (i = 0; i < insn->n; i++) { + if (insn->unused[0] == 222) { /* second insn read */ + for (i = 0; i < insn->n; i++) data[i] = devpriv->ui_AiReadData[i]; - } - } else { devpriv->tsk_Current = current; /* Save the current process task structure */ /* @@ -519,9 +512,8 @@ int i_APCI3120_CommandTestAnalogInput(struct comedi_device *dev, struct comedi_s /* step 2: make sure trigger sources are unique and mutually compatible */ - if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) { + if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) err++; - } if (cmd->scan_begin_src != TRIG_TIMER && cmd->scan_begin_src != TRIG_FOLLOW) @@ -548,16 +540,14 @@ int i_APCI3120_CommandTestAnalogInput(struct comedi_device *dev, struct comedi_s err++; } - if (cmd->scan_begin_src == TRIG_TIMER) /* Test Delay timing */ - { + if (cmd->scan_begin_src == TRIG_TIMER) { /* Test Delay timing */ if (cmd->scan_begin_arg < this_board->ui_MinDelaytimeNs) { cmd->scan_begin_arg = this_board->ui_MinDelaytimeNs; err++; } } - if (cmd->convert_src == TRIG_TIMER) /* Test Acquisition timing */ - { + if (cmd->convert_src == TRIG_TIMER) { /* Test Acquisition timing */ if (cmd->scan_begin_src == TRIG_TIMER) { if ((cmd->convert_arg) && (cmd->convert_arg < @@ -653,11 +643,10 @@ int i_APCI3120_CommandAnalogInput(struct comedi_device *dev, struct comedi_subde /* UPDATE-0.7.57->0.7.68devpriv->ui_AiDataLength=s->async->data_len; */ devpriv->ui_AiDataLength = s->async->prealloc_bufsz; - if (cmd->stop_src == TRIG_COUNT) { + if (cmd->stop_src == TRIG_COUNT) devpriv->ui_AiNbrofScans = cmd->stop_arg; - } else { + else devpriv->ui_AiNbrofScans = 0; - } devpriv->ui_AiTimer0 = 0; /* variables changed to timer0,timer1 */ devpriv->ui_AiTimer1 = 0; @@ -849,9 +838,8 @@ int i_APCI3120_CyclicAnalogInput(int mode, struct comedi_device *dev, } /*** EL241003 End ******************************************************************************/ - if (devpriv->b_ExttrigEnable == APCI3120_ENABLE) { + if (devpriv->b_ExttrigEnable == APCI3120_ENABLE) i_APCI3120_ExttrigEnable(dev); /* activate EXT trigger */ - } switch (mode) { case 1: /* init timer0 in mode 2 */ @@ -1049,12 +1037,10 @@ int i_APCI3120_CyclicAnalogInput(int mode, struct comedi_device *dev, dmalen1 = 4; } } else { /* isn't output buff smaller that our DMA buff? */ - if (dmalen0 > (devpriv->ui_AiDataLength)) { + if (dmalen0 > (devpriv->ui_AiDataLength)) dmalen0 = devpriv->ui_AiDataLength; - } - if (dmalen1 > (devpriv->ui_AiDataLength)) { + if (dmalen1 > (devpriv->ui_AiDataLength)) dmalen1 = devpriv->ui_AiDataLength; - } } devpriv->ui_DmaBufferUsesize[0] = dmalen0; devpriv->ui_DmaBufferUsesize[1] = dmalen1; @@ -1356,11 +1342,10 @@ int i_APCI3120_SetupChannelList(struct comedi_device *dev, struct comedi_subdevi /* store range list to card */ us_TmpValue = CR_CHAN(chanlist[i]); /* get channel number; */ - if (CR_RANGE(chanlist[i]) < APCI3120_BIPOLAR_RANGES) { + if (CR_RANGE(chanlist[i]) < APCI3120_BIPOLAR_RANGES) us_TmpValue &= ((~APCI3120_UNIPOLAR) & 0xff); /* set bipolar */ - } else { + else us_TmpValue |= APCI3120_UNIPOLAR; /* enable unipolar...... */ - } gain = CR_RANGE(chanlist[i]); /* get gain number */ us_TmpValue |= ((gain & 0x03) << 4); /* <<4 for G0 and G1 bit in RAM */ @@ -1514,8 +1499,7 @@ void v_APCI3120_Interrupt(int irq, void *d) /* Check If EOS interrupt */ if ((int_daq & 0x2) && (devpriv->b_InterruptMode == APCI3120_EOS_MODE)) { - if (devpriv->b_EocEosInterrupt == APCI3120_ENABLE) /* enable this in without DMA ??? */ - { + if (devpriv->b_EocEosInterrupt == APCI3120_ENABLE) { /* enable this in without DMA ??? */ if (devpriv->b_AiCyclicAcquisition == APCI3120_ENABLE) { ui_Check = 0; @@ -1966,8 +1950,7 @@ int i_APCI3120_InsnConfigTimer(struct comedi_device *dev, struct comedi_subdevic APCI3120_DISABLE_EOS_INT; outb(devpriv->b_ModeSelectRegister, devpriv->iobase + APCI3120_WRITE_MODE_SELECT); - if (data[0] == APCI3120_TIMER) /* initialize timer */ - { + if (data[0] == APCI3120_TIMER) { /* initialize timer */ /* devpriv->b_ModeSelectRegister=devpriv->b_ModeSelectRegister | * APCI3120_ENABLE_TIMER_INT; */ @@ -2006,8 +1989,7 @@ int i_APCI3120_InsnConfigTimer(struct comedi_device *dev, struct comedi_subdevic /* timer2 in Timer mode enabled */ devpriv->b_Timer2Mode = APCI3120_TIMER; - } else /* Initialize Watch dog */ - { + } else { /* Initialize Watch dog */ /* Set the Timer 2 in mode 5(Watchdog) */ @@ -2092,8 +2074,7 @@ int i_APCI3120_InsnWriteTimer(struct comedi_device *dev, struct comedi_subdevice return -EINVAL; } - if (data[0] == 2) /* write new value */ - { + if (data[0] == 2) { /* write new value */ if (devpriv->b_Timer2Mode != APCI3120_TIMER) { comedi_error(dev, "write :timer2 not configured in TIMER MODE"); @@ -2113,13 +2094,11 @@ int i_APCI3120_InsnWriteTimer(struct comedi_device *dev, struct comedi_subdevice /* Reset FC_TIMER BIT */ inb(devpriv->iobase + APCI3120_TIMER_STATUS_REGISTER); - if (devpriv->b_Timer2Mode == APCI3120_TIMER) /* start timer */ - { + if (devpriv->b_Timer2Mode == APCI3120_TIMER) { /* start timer */ /* Enable Timer */ devpriv->b_ModeSelectRegister = devpriv->b_ModeSelectRegister & 0x0B; - } else /* start watch dog */ - { + } else { /* start watch dog */ /* Enable WatchDog */ devpriv->b_ModeSelectRegister = (devpriv-> @@ -2146,8 +2125,7 @@ int i_APCI3120_InsnWriteTimer(struct comedi_device *dev, struct comedi_subdevice outb(devpriv->b_ModeSelectRegister, devpriv->iobase + APCI3120_WRITE_MODE_SELECT); - if (devpriv->b_Timer2Mode == APCI3120_TIMER) /* start timer */ - { + if (devpriv->b_Timer2Mode == APCI3120_TIMER) { /* start timer */ /* For Timer mode is Gate2 must be activated **timer started */ devpriv->us_OutputRegister = devpriv-> @@ -2299,8 +2277,7 @@ int i_APCI3120_InsnReadTimer(struct comedi_device *dev, struct comedi_subdevice /* combining both words */ data[0] = (unsigned int) ((us_TmpValue) | ((us_TmpValue_2) << 16)); - } else /* Read watch dog status */ - { + } else { /* Read watch dog status */ us_StatusValue = inw(devpriv->iobase + APCI3120_RD_STATUS); us_StatusValue = @@ -2441,10 +2418,9 @@ int i_APCI3120_InsnConfigDigitalOutput(struct comedi_device *dev, devpriv->b_OutputMemoryStatus = APCI3120_DISABLE; devpriv->b_DigitalOutputRegister = 0; } - if (!devpriv->b_OutputMemoryStatus) { + if (!devpriv->b_OutputMemoryStatus) ui_Temp = 0; - - } /* if(!devpriv->b_OutputMemoryStatus ) */ + /* if(!devpriv->b_OutputMemoryStatus ) */ return insn->n; } @@ -2504,23 +2480,23 @@ int i_APCI3120_InsnBitsDigitalOutput(struct comedi_device *dev, /* +----------------------------------------------------------------------------+ -| Function name :int i_APCI3120_InsnWriteDigitalOutput(struct comedi_device *dev,| -|struct comedi_subdevice *s,struct comedi_insn *insn,unsigned int *data) | -| | +| Function name :int i_APCI3120_InsnWriteDigitalOutput(struct comedi_device *dev,| +|struct comedi_subdevice *s,struct comedi_insn *insn,unsigned int *data) | +| | +----------------------------------------------------------------------------+ -| Task : Write digiatl output | -| | +| Task : Write digiatl output | +| | +----------------------------------------------------------------------------+ -| Input Parameters : struct comedi_device *dev | -| struct comedi_subdevice *s | -| struct comedi_insn *insn | -| unsigned int *data | - data[0] Value to be written - data[1] :1 Set digital o/p ON - data[1] 2 Set digital o/p OFF with memory ON +| Input Parameters : struct comedi_device *dev | +| struct comedi_subdevice *s | +| struct comedi_insn *insn | +| unsigned int *data | + data[0] Value to be written + data[1] :1 Set digital o/p ON + data[1] 2 Set digital o/p OFF with memory ON +----------------------------------------------------------------------------+ -| Return Value : | -| | +| Return Value : | +| | +----------------------------------------------------------------------------+ */ @@ -2615,8 +2591,7 @@ int i_APCI3120_InsnWriteAnalogOutput(struct comedi_device *dev, ui_Channel = CR_CHAN(insn->chanspec); /* this_board->i_hwdrv_InsnWriteAnalogOutput(dev, ui_Range, ui_Channel,data[0]); */ - if (ui_Range) /* if 1 then unipolar */ - { + if (ui_Range) { /* if 1 then unipolar */ if (data[0] != 0) data[0] = @@ -2627,8 +2602,7 @@ int i_APCI3120_InsnWriteAnalogOutput(struct comedi_device *dev, ((((ui_Channel & 0x03) << 14) & 0xC000) | (1 << 13) | 8192); - } else /* if 0 then bipolar */ - { + } else { /* if 0 then bipolar */ data[0] = ((((ui_Channel & 0x03) << 14) & 0xC000) | (0 << 13) | data[0]); @@ -2639,8 +2613,7 @@ int i_APCI3120_InsnWriteAnalogOutput(struct comedi_device *dev, * out put n values at the given channel. printk("\nwaiting for * DA_READY BIT"); */ - do /* Waiting of DA_READY BIT */ - { + do { /* Waiting of DA_READY BIT */ us_TmpValue = ((unsigned short) inw(devpriv->iobase + APCI3120_RD_STATUS)) & 0x0001; -- cgit v1.2.3 From ecd89ddcabf8646651f152155bff5f8bed9c6e92 Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:15:07 +0100 Subject: Staging: comedi: das6402.c: Checkpatch cleanup ERROR: Macros with complex values should be enclosed in parenthesis +#define N_WORDS 3000*64 Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/das6402.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/das6402.c b/drivers/staging/comedi/drivers/das6402.c index 92487f58fd8b..a404a1831911 100644 --- a/drivers/staging/comedi/drivers/das6402.c +++ b/drivers/staging/comedi/drivers/das6402.c @@ -45,7 +45,7 @@ This driver has suffered bitrot. #define DAS6402_SIZE 16 -#define N_WORDS 3000*64 +#define N_WORDS (3000*64) #define STOP 0 #define START 1 -- cgit v1.2.3 From 882e5b32b5d68960f46331215fc3c301df508110 Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:15:08 +0100 Subject: Staging: comedi: cb_pcimdas.c: more Checkpatch cleanup WARNING: braces {} are not necessary for single statement blocks + if (fifo_empty) { + break; + } WARNING: braces {} are not necessary for single statement blocks + if (irq) { + printk(", irq %u", irq); + } Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/das800.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/das800.c b/drivers/staging/comedi/drivers/das800.c index ecb97cdbce26..aadc4971c909 100644 --- a/drivers/staging/comedi/drivers/das800.c +++ b/drivers/staging/comedi/drivers/das800.c @@ -399,9 +399,8 @@ static irqreturn_t das800_interrupt(int irq, void *d) } else { fifo_empty = 0; /* cio-das802/16 has no fifo empty status bit */ } - if (fifo_empty) { + if (fifo_empty) break; - } /* strip off extraneous bits for 12 bit cards */ if (thisboard->resolution == 12) dataPoint = (dataPoint >> 4) & 0xfff; @@ -457,9 +456,8 @@ static int das800_attach(struct comedi_device *dev, struct comedi_devconfig *it) int board; printk("comedi%d: das800: io 0x%lx", dev->minor, iobase); - if (irq) { + if (irq) printk(", irq %u", irq); - } printk("\n"); /* allocate and initialize dev->private */ -- cgit v1.2.3 From 20962c10c19862c58c03eec2434279a5d104c40e Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:15:09 +0100 Subject: Staging: comedi: dmm32at.c: Checkpatch cleanup WARNING: braces {} are not necessary for any arm of this statement + if (data[0] == COMEDI_OUTPUT) { [...] + } else { [...] Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/dmm32at.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/dmm32at.c b/drivers/staging/comedi/drivers/dmm32at.c index 9db9a467c8f8..d5cbd515c370 100644 --- a/drivers/staging/comedi/drivers/dmm32at.c +++ b/drivers/staging/comedi/drivers/dmm32at.c @@ -1048,11 +1048,10 @@ static int dmm32at_dio_insn_config(struct comedi_device *dev, * value COMEDI_INPUT or COMEDI_OUTPUT. */ /* if output clear the bit, otherwise set it */ - if (data[0] == COMEDI_OUTPUT) { + if (data[0] == COMEDI_OUTPUT) devpriv->dio_config &= ~chanbit; - } else { + else devpriv->dio_config |= chanbit; - } /* get access to the DIO regs */ dmm_outb(dev, DMM32AT_CNTRL, DMM32AT_DIOACC); /* set the DIO's to the new configuration setting */ -- cgit v1.2.3 From fa93e19dcf8600c87a60160735b1065cd4bb4dbb Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:15:10 +0100 Subject: Staging: comedi: dt2801.c: Checkpatch cleanup ERROR: code indent should use tabs where possible + 0 = [-10,10]$ ERROR: code indent should use tabs where possible + 0 = [-10,10]$ WARNING: braces {} are not necessary for single statement blocks + if (stat & (DT_S_COMPOSITE_ERROR | DT_S_READY)) { + return stat; + } WARNING: braces {} are not necessary for single statement blocks + if (stat & DT_S_COMPOSITE_ERROR) { + return stat; + } WARNING: braces {} are not necessary for single statement blocks + if (stat & DT_S_READY) { + return 0; + } WARNING: braces {} are not necessary for single statement blocks + if (stat & DT_S_COMPOSITE_ERROR) { + return stat; + } WARNING: braces {} are not necessary for single statement blocks + if (stat & DT_S_READY) { + return 0; + } WARNING: braces {} are not necessary for single statement blocks + if (!(stat & DT_S_READY)) { + printk("dt2801: !ready in dt2801_writecmd(), ignoring\n"); + } WARNING: braces {} are not necessary for single statement blocks + if (!timeout) { + printk("dt2801: timeout 1 status=0x%02x\n", stat); + } WARNING: braces {} are not necessary for single statement blocks + if (!timeout) { + printk("dt2801: timeout 2 status=0x%02x\n", stat); + } WARNING: braces {} are not necessary for any arm of this statement + if (stat == -ETIME) { [...] + } else { [...] Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/dt2801.c | 33 ++++++++++++--------------------- 1 file changed, 12 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/dt2801.c b/drivers/staging/comedi/drivers/dt2801.c index 7b9af5d755e0..3f365aee4822 100644 --- a/drivers/staging/comedi/drivers/dt2801.c +++ b/drivers/staging/comedi/drivers/dt2801.c @@ -18,10 +18,10 @@ Configuration options: [1] - unused [2] - A/D reference 0=differential, 1=single-ended [3] - A/D range - 0 = [-10,10] + 0 = [-10, 10] 1 = [0,10] [4] - D/A 0 range - 0 = [-10,10] + 0 = [-10, 10] 1 = [-5,5] 2 = [-2.5,2.5] 3 = [0,10] @@ -279,9 +279,8 @@ static int dt2801_readdata(struct comedi_device *dev, int *data) do { stat = inb_p(dev->iobase + DT2801_STATUS); - if (stat & (DT_S_COMPOSITE_ERROR | DT_S_READY)) { + if (stat & (DT_S_COMPOSITE_ERROR | DT_S_READY)) return stat; - } if (stat & DT_S_DATA_OUT_READY) { *data = inb_p(dev->iobase + DT2801_DATA); return 0; @@ -315,9 +314,8 @@ static int dt2801_writedata(struct comedi_device *dev, unsigned int data) do { stat = inb_p(dev->iobase + DT2801_STATUS); - if (stat & DT_S_COMPOSITE_ERROR) { + if (stat & DT_S_COMPOSITE_ERROR) return stat; - } if (!(stat & DT_S_DATA_IN_FULL)) { outb_p(data & 0xff, dev->iobase + DT2801_DATA); return 0; @@ -354,18 +352,15 @@ static int dt2801_wait_for_ready(struct comedi_device *dev) int stat; stat = inb_p(dev->iobase + DT2801_STATUS); - if (stat & DT_S_READY) { + if (stat & DT_S_READY) return 0; - } do { stat = inb_p(dev->iobase + DT2801_STATUS); - if (stat & DT_S_COMPOSITE_ERROR) { + if (stat & DT_S_COMPOSITE_ERROR) return stat; - } - if (stat & DT_S_READY) { + if (stat & DT_S_READY) return 0; - } } while (--timeout > 0); return -ETIME; @@ -382,9 +377,8 @@ static int dt2801_writecmd(struct comedi_device *dev, int command) printk ("dt2801: composite-error in dt2801_writecmd(), ignoring\n"); } - if (!(stat & DT_S_READY)) { + if (!(stat & DT_S_READY)) printk("dt2801: !ready in dt2801_writecmd(), ignoring\n"); - } outb_p(command, dev->iobase + DT2801_CMD); return 0; @@ -418,9 +412,8 @@ static int dt2801_reset(struct comedi_device *dev) if (stat & DT_S_READY) break; } while (timeout--); - if (!timeout) { + if (!timeout) printk("dt2801: timeout 1 status=0x%02x\n", stat); - } /* printk("dt2801: reading dummy\n"); */ /* dt2801_readdata(dev,&board_code); */ @@ -436,9 +429,8 @@ static int dt2801_reset(struct comedi_device *dev) if (stat & DT_S_READY) break; } while (timeout--); - if (!timeout) { + if (!timeout) printk("dt2801: timeout 2 status=0x%02x\n", stat); - } DPRINTK("dt2801: reading code\n"); dt2801_readdata(dev, &board_code); @@ -623,11 +615,10 @@ static int dt2801_detach(struct comedi_device *dev) static int dt2801_error(struct comedi_device *dev, int stat) { if (stat < 0) { - if (stat == -ETIME) { + if (stat == -ETIME) printk("dt2801: timeout\n"); - } else { + else printk("dt2801: error %d\n", stat); - } return stat; } printk("dt2801: error status 0x%02x, resetting...\n", stat); -- cgit v1.2.3 From a5a8695987b4c541f2003640d8583412b8c154ff Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:15:11 +0100 Subject: Staging: arlan: arlan.h: Checkpatch cleanup ERROR: trailing whitespace + * Copyright (C) 1998 Elmer.Joandi@ut.ee, +37-255-13500^I$ WARNING: Use #include instead of +#include ERROR: do not use C99 // comments +//#define ARLAN_DEBUGGING 1 ERROR: "foo * bar" should be "foo *bar" +extern int arlan_command(struct net_device * dev, int command); ERROR: trailing whitespace + $ ERROR: trailing whitespace +#define IFDEBUG( L ) if ( (L) & arlan_debug ) $ ERROR: space prohibited after that open parenthesis '(' +#define IFDEBUG( L ) if ( (L) & arlan_debug ) ERROR: space prohibited before that close parenthesis ')' +#define IFDEBUG( L ) if ( (L) & arlan_debug ) ERROR: trailing whitespace +#define ARLAN_FAKE_HDR_LEN 12 $ ERROR: space required after that ',' (ctx:VxV) + #define ARLAN_DEBUG(a,b) printk(KERN_DEBUG a, b) ^ ERROR: trailing whitespace +^I#define ARLAN_DEBUG(a,b) $ ERROR: space required after that ',' (ctx:VxV) + #define ARLAN_DEBUG(a,b) ^ ERROR: open brace '{' following struct go on the same line +struct arlan_shmem +{ ERROR: trailing whitespace + /* Header Signature */ $ ERROR: trailing whitespace + $ ERROR: trailing whitespace + $ ERROR: trailing whitespace + $ ERROR: trailing whitespace + $ ERROR: trailing whitespace + int systemId; $ ERROR: open brace '{' following struct go on the same line +struct TxParam +{ ERROR: "foo * bar" should be "foo *bar" + struct arlan_shmem __iomem * card; ERROR: "foo * bar" should be "foo *bar" + struct arlan_shmem * conf; ERROR: trailing whitespace + struct arlan_conf_stru * Conf;^I $ ERROR: "foo * bar" should be "foo *bar" + struct arlan_conf_stru * Conf; ERROR: trailing whitespace + $ ERROR: space required after that ',' (ctx:VxV) +#define READSHM(to,from,atype) {\ ^ ERROR: space required after that ',' (ctx:VxV) +#define READSHM(to,from,atype) {\ ^ ERROR: space required after that ',' (ctx:VxO) + memcpy_fromio(&(tmp),&(from),sizeof(atype));\ ^ ERROR: space required before that '&' (ctx:OxV) + memcpy_fromio(&(tmp),&(from),sizeof(atype));\ ^ ERROR: space required after that ',' (ctx:VxV) + memcpy_fromio(&(tmp),&(from),sizeof(atype));\ ^ ERROR: space required after that ',' (ctx:VxV) +#define READSHMEM(from,atype)\ ^ ERROR: space required after that ',' (ctx:VxV) +#define WRITESHM(to,from,atype) \ ^ ERROR: space required after that ',' (ctx:VxV) +#define WRITESHM(to,from,atype) \ ^ ERROR: space required after that ',' (ctx:VxO) + memcpy_toio(&(to),&tmpSHM,sizeof(atype));\ ^ ERROR: space required before that '&' (ctx:OxV) + memcpy_toio(&(to),&tmpSHM,sizeof(atype));\ ^ ERROR: space required after that ',' (ctx:VxV) + memcpy_toio(&(to),&tmpSHM,sizeof(atype));\ ^ ERROR: space required after that ',' (ctx:VxV) +#define DEBUGSHM(levelSHM,stringSHM,stuff,atype) \ ^ ERROR: space required after that ',' (ctx:VxV) +#define DEBUGSHM(levelSHM,stringSHM,stuff,atype) \ ^ ERROR: space required after that ',' (ctx:VxV) +#define DEBUGSHM(levelSHM,stringSHM,stuff,atype) \ ^ ERROR: space required after that ',' (ctx:VxO) + memcpy_fromio(&tmpSHM,&(stuff),sizeof(atype));\ ^ ERROR: space required before that '&' (ctx:OxV) + memcpy_fromio(&tmpSHM,&(stuff),sizeof(atype));\ ^ ERROR: space required after that ',' (ctx:VxV) + memcpy_fromio(&tmpSHM,&(stuff),sizeof(atype));\ ^ ERROR: space required after that ',' (ctx:VxV) + IFDEBUG(levelSHM) printk(stringSHM,tmpSHM);\ ^ ERROR: space required after that ',' (ctx:VxO) + writeb(val,&(to)) ^ ERROR: space required before that '&' (ctx:OxV) + writeb(val,&(to)) ^ ERROR: space required after that ',' (ctx:VxO) + writew(val,&(to)) ^ ERROR: space required before that '&' (ctx:OxV) + writew(val,&(to)) ^ ERROR: space required after that ',' (ctx:VxO) + writel(val,&(to)) ^ ERROR: space required before that '&' (ctx:OxV) + writel(val,&(to)) ^ ERROR: space prohibited after that open parenthesis '(' + ( ( READSHMB(((struct arlan_private *)netdev_priv(dev))->card->registrationMode) > 0) && \ ERROR: space prohibited after that open parenthesis '(' + ( READSHMB(((struct arlan_private *)netdev_priv(dev))->card->registrationStatus) == 0) ) ERROR: space prohibited before that close parenthesis ')' + ( READSHMB(((struct arlan_private *)netdev_priv(dev))->card->registrationStatus) == 0) ) ERROR: code indent should use tabs where possible + ^IREADSHMB(((struct arlan_private *)netdev_priv(dev))->card->cntrlRegImage)$ ERROR: space required before the open brace '{' +#define writeControlRegister(dev, v){\ ERROR: space required after that ',' (ctx:WxV) + WRITESHMB(((struct arlan_private *)netdev_priv(dev))->card->cntrlRegImage ,((v) &0xF) );\ ^ ERROR: need consistent spacing around '&' (ctx:WxV) + WRITESHMB(((struct arlan_private *)netdev_priv(dev))->card->cntrlRegImage ,((v) &0xF) );\ ^ ERROR: space prohibited before that close parenthesis ')' + WRITESHMB(((struct arlan_private *)netdev_priv(dev))->card->cntrlRegImage ,((v) &0xF) );\ ERROR: space required after that ',' (ctx:WxV) + WRITESHMB(((struct arlan_private *)netdev_priv(dev))->card->controlRegister ,(v) );} ^ ERROR: space required after that ';' (ctx:VxV) + WRITESHMB(((struct arlan_private *)netdev_priv(dev))->card->controlRegister ,(v) );} ^ ERROR: space prohibited before that close parenthesis ')' + WRITESHMB(((struct arlan_private *)netdev_priv(dev))->card->controlRegister ,(v) );} WARNING: suspect code indent for conditional statements (3, 6) + if (cr & ARLAN_CHANNEL_ATTENTION){ \ + writeControlRegister(dev, (cr & ~ARLAN_CHANNEL_ATTENTION));\ ERROR: space required before the open brace '{' + if (cr & ARLAN_CHANNEL_ATTENTION){ \ ERROR: space required after that close brace '}' + }else \ ERROR: space required before the open brace '{' +#define clearChannelAttention(dev){ \ ERROR: space required after that ',' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_CHANNEL_ATTENTION);} ^ ERROR: space required after that ';' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_CHANNEL_ATTENTION);} ^ ERROR: space required after that ',' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) | ARLAN_RESET);} ^ ERROR: space required after that ';' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) | ARLAN_RESET);} ^ ERROR: space required after that ',' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_RESET);} ^ ERROR: space required after that ';' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_RESET);} ^ ERROR: space required before the open brace '{' +#define setInterruptEnable(dev){\ ERROR: space required after that ',' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) | ARLAN_INTERRUPT_ENABLE) ;} ^ ERROR: space required after that ';' (ctx:WxV) + writeControlRegister(dev,readControlRegister(dev) | ARLAN_INTERRUPT_ENABLE) ;} ^ ERROR: space required before the open brace '{' +#define clearInterruptEnable(dev){\ ERROR: space required after that ',' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_INTERRUPT_ENABLE) ;} ^ ERROR: space required after that ';' (ctx:WxV) + writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_INTERRUPT_ENABLE) ;} ^ ERROR: space required before the open brace '{' +#define setClearInterrupt(dev){\ ERROR: space required after that ',' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) | ARLAN_CLEAR_INTERRUPT) ;} ^ ERROR: space required after that ';' (ctx:WxV) + writeControlRegister(dev,readControlRegister(dev) | ARLAN_CLEAR_INTERRUPT) ;} ^ ERROR: space required before the open brace '{' +#define clearClearInterrupt(dev){\ ERROR: space required after that ',' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_CLEAR_INTERRUPT);} ^ ERROR: space required after that ';' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_CLEAR_INTERRUPT);} ^ ERROR: space required before the open brace '{' +#define setPowerOff(dev){\ ERROR: space required after that ',' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) | (ARLAN_POWER && ARLAN_ACCESS));\ ^ ERROR: space required after that ',' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_ACCESS);} ^ ERROR: space required after that ';' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_ACCESS);} ^ ERROR: space required before the open brace '{' +#define setPowerOn(dev){\ ERROR: space required after that ',' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) & ~(ARLAN_POWER)); } ^ ERROR: space required before the open brace '{' +#define arlan_lock_card_access(dev){\ ERROR: space required after that ',' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_ACCESS);} ^ ERROR: space required after that ';' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_ACCESS);} ^ ERROR: space required before the open brace '{' +#define arlan_unlock_card_access(dev){\ ERROR: trailing whitespace + writeControlRegister(dev,readControlRegister(dev) | ARLAN_ACCESS ); } $ ERROR: space required after that ',' (ctx:VxV) + writeControlRegister(dev,readControlRegister(dev) | ARLAN_ACCESS ); } ^ ERROR: space prohibited before that close parenthesis ')' + writeControlRegister(dev,readControlRegister(dev) | ARLAN_ACCESS ); } ERROR: trailing whitespace + $ ERROR: trailing whitespace + $ Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/arlan/arlan.h | 132 ++++++++++++++++++++---------------------- 1 file changed, 64 insertions(+), 68 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/arlan/arlan.h b/drivers/staging/arlan/arlan.h index fb3ad51a1caf..19161f1feb5b 100644 --- a/drivers/staging/arlan/arlan.h +++ b/drivers/staging/arlan/arlan.h @@ -1,6 +1,6 @@ /* * Copyright (C) 1997 Cullen Jennings - * Copyright (C) 1998 Elmer.Joandi@ut.ee, +37-255-13500 + * Copyright (C) 1998 Elmer.Joandi@ut.ee, +37-255-13500 * GNU General Public License applies */ @@ -20,14 +20,14 @@ #include #include #include -#include +#include #include #include #include #include -//#define ARLAN_DEBUGGING 1 +/* #define ARLAN_DEBUGGING 1 */ #define ARLAN_PROC_INTERFACE #define MAX_ARLANS 4 /* not more than 4 ! */ @@ -51,8 +51,8 @@ extern int arlan_debug; extern int arlan_entry_debug; extern int arlan_exit_debug; extern int testMemory; -extern int arlan_command(struct net_device * dev, int command); - +extern int arlan_command(struct net_device *dev, int command); + #define SIDUNKNOWN -1 #define radioNodeIdUNKNOWN -1 #define irqUNKNOWN 0 @@ -65,22 +65,21 @@ extern int arlan_command(struct net_device * dev, int command); #define registrationModeUNKNOWN -1 -#define IFDEBUG( L ) if ( (L) & arlan_debug ) -#define ARLAN_FAKE_HDR_LEN 12 +#define IFDEBUG(L) if ((L) & arlan_debug) +#define ARLAN_FAKE_HDR_LEN 12 #ifdef ARLAN_DEBUGGING #define DEBUG 1 #define ARLAN_ENTRY_EXIT_DEBUGGING 1 - #define ARLAN_DEBUG(a,b) printk(KERN_DEBUG a, b) + #define ARLAN_DEBUG(a, b) printk(KERN_DEBUG a, b) #else - #define ARLAN_DEBUG(a,b) + #define ARLAN_DEBUG(a, b) #endif #define ARLAN_SHMEM_SIZE 0x2000 -struct arlan_shmem -{ - /* Header Signature */ +struct arlan_shmem { + /* Header Signature */ volatile char textRegion[48]; volatile u_char resetFlag; volatile u_char diagnosticInfo; @@ -94,7 +93,7 @@ struct arlan_shmem volatile u_char radioModule;// shows EEPROM, can be overridden at 0x111 volatile u_char defaultChannelSet; // shows EEProm, can be overriiden at 0x10A volatile u_char _2[47]; - + /* Control/Status Block - 0x0080 */ volatile u_char interruptInProgress; /* not used by lancpu */ volatile u_char cntrlRegImage; /* not used by lancpu */ @@ -113,7 +112,7 @@ struct arlan_shmem volatile u_char rxQuality; volatile u_char scrambled; volatile u_char _4[1]; - + /* Transmit Status - 0x00b0 */ volatile u_char txStatus; volatile u_char txAckQuality; @@ -151,7 +150,7 @@ struct arlan_shmem volatile u_short routerId; volatile u_char _10[9]; volatile u_char txAttenuation; - volatile u_char systemId[4]; + volatile u_char systemId[4]; volatile u_short globalChecksum; volatile u_char _11[4]; volatile u_short maxDatagramSize; @@ -207,19 +206,19 @@ struct arlan_shmem volatile u_char hostcpuLock; volatile u_char lancpuLock; volatile u_char resetTime[18]; - + volatile u_char numDatagramsTransmitted[4]; volatile u_char numReTransmissions[4]; volatile u_char numFramesDiscarded[4]; volatile u_char numDatagramsReceived[4]; volatile u_char numDuplicateReceivedFrames[4]; volatile u_char numDatagramsDiscarded[4]; - + volatile u_short maxNumReTransmitDatagram; volatile u_short maxNumReTransmitFrames; volatile u_short maxNumConsecutiveDuplicateFrames; /* misaligned here so we have to go to characters */ - + volatile u_char numBytesTransmitted[4]; volatile u_char numBytesReceived[4]; volatile u_char numCRCErrors[4]; @@ -259,7 +258,7 @@ struct arlan_conf_stru { int channelNumber; int scramblingDisable; int txAttenuation; - int systemId; + int systemId; int maxDatagramSize; int maxFrameSize; int maxRetries; @@ -316,8 +315,7 @@ struct arlan_conf_stru { extern struct arlan_conf_stru arlan_conf[MAX_ARLANS]; -struct TxParam -{ +struct TxParam { volatile short offset; volatile short length; volatile u_char dest[6]; @@ -330,12 +328,12 @@ struct TxParam #define TX_RING_SIZE 2 /* Information that need to be kept for each board. */ struct arlan_private { - struct arlan_shmem __iomem * card; - struct arlan_shmem * conf; + struct arlan_shmem __iomem *card; + struct arlan_shmem *conf; - struct arlan_conf_stru * Conf; + struct arlan_conf_stru *Conf; int bad; - int reset; + int reset; unsigned long lastReset; struct timer_list timer; struct timer_list tx_delay_timer; @@ -407,38 +405,38 @@ struct arlan_private { #define TXBuffStart(dev) offsetof(struct arlan_shmem, txBuffer) #define TXBuffEnd(dev) offsetof(struct arlan_shmem, xxBuffer) - -#define READSHM(to,from,atype) {\ + +#define READSHM(to, from, atype) {\ atype tmp;\ - memcpy_fromio(&(tmp),&(from),sizeof(atype));\ + memcpy_fromio(&(tmp), &(from), sizeof(atype));\ to = tmp;\ } -#define READSHMEM(from,atype)\ +#define READSHMEM(from, atype)\ atype from; \ READSHM(from, arlan->from, atype); -#define WRITESHM(to,from,atype) \ +#define WRITESHM(to, from, atype) \ { atype tmpSHM = from;\ - memcpy_toio(&(to),&tmpSHM,sizeof(atype));\ + memcpy_toio(&(to), &tmpSHM, sizeof(atype));\ } -#define DEBUGSHM(levelSHM,stringSHM,stuff,atype) \ +#define DEBUGSHM(levelSHM, stringSHM, stuff, atype) \ { atype tmpSHM; \ - memcpy_fromio(&tmpSHM,&(stuff),sizeof(atype));\ - IFDEBUG(levelSHM) printk(stringSHM,tmpSHM);\ + memcpy_fromio(&tmpSHM, &(stuff), sizeof(atype));\ + IFDEBUG(levelSHM) printk(stringSHM, tmpSHM);\ } #define WRITESHMB(to, val) \ - writeb(val,&(to)) + writeb(val, &(to)) #define READSHMB(to) \ readb(&(to)) #define WRITESHMS(to, val) \ - writew(val,&(to)) + writew(val, &(to)) #define READSHMS(to) \ readw(&(to)) #define WRITESHMI(to, val) \ - writel(val,&(to)) + writel(val, &(to)) #define READSHMI(to) \ readl(&(to)) @@ -447,51 +445,51 @@ struct arlan_private { #define registrationBad(dev)\ - ( ( READSHMB(((struct arlan_private *)netdev_priv(dev))->card->registrationMode) > 0) && \ - ( READSHMB(((struct arlan_private *)netdev_priv(dev))->card->registrationStatus) == 0) ) + (( READSHMB(((struct arlan_private *)netdev_priv(dev))->card->registrationMode) > 0) && \ + ( READSHMB(((struct arlan_private *)netdev_priv(dev))->card->registrationStatus) == 0)) #define readControlRegister(dev)\ - READSHMB(((struct arlan_private *)netdev_priv(dev))->card->cntrlRegImage) + READSHMB(((struct arlan_private *)netdev_priv(dev))->card->cntrlRegImage) -#define writeControlRegister(dev, v){\ - WRITESHMB(((struct arlan_private *)netdev_priv(dev))->card->cntrlRegImage ,((v) &0xF) );\ - WRITESHMB(((struct arlan_private *)netdev_priv(dev))->card->controlRegister ,(v) );} +#define writeControlRegister(dev, v) {\ + WRITESHMB(((struct arlan_private *)netdev_priv(dev))->card->cntrlRegImage, ((v) & 0xF));\ + WRITESHMB(((struct arlan_private *)netdev_priv(dev))->card->controlRegister, (v)); } #define arlan_interrupt_lancpu(dev) {\ int cr; \ \ cr = readControlRegister(dev);\ - if (cr & ARLAN_CHANNEL_ATTENTION){ \ + if (cr & ARLAN_CHANNEL_ATTENTION) { \ writeControlRegister(dev, (cr & ~ARLAN_CHANNEL_ATTENTION));\ - }else \ + } else \ writeControlRegister(dev, (cr | ARLAN_CHANNEL_ATTENTION));\ } -#define clearChannelAttention(dev){ \ - writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_CHANNEL_ATTENTION);} +#define clearChannelAttention(dev) { \ + writeControlRegister(dev, readControlRegister(dev) & ~ARLAN_CHANNEL_ATTENTION); } #define setHardwareReset(dev) {\ - writeControlRegister(dev,readControlRegister(dev) | ARLAN_RESET);} + writeControlRegister(dev, readControlRegister(dev) | ARLAN_RESET); } #define clearHardwareReset(dev) {\ - writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_RESET);} -#define setInterruptEnable(dev){\ - writeControlRegister(dev,readControlRegister(dev) | ARLAN_INTERRUPT_ENABLE) ;} -#define clearInterruptEnable(dev){\ - writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_INTERRUPT_ENABLE) ;} -#define setClearInterrupt(dev){\ - writeControlRegister(dev,readControlRegister(dev) | ARLAN_CLEAR_INTERRUPT) ;} -#define clearClearInterrupt(dev){\ - writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_CLEAR_INTERRUPT);} -#define setPowerOff(dev){\ - writeControlRegister(dev,readControlRegister(dev) | (ARLAN_POWER && ARLAN_ACCESS));\ - writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_ACCESS);} -#define setPowerOn(dev){\ - writeControlRegister(dev,readControlRegister(dev) & ~(ARLAN_POWER)); } -#define arlan_lock_card_access(dev){\ - writeControlRegister(dev,readControlRegister(dev) & ~ARLAN_ACCESS);} -#define arlan_unlock_card_access(dev){\ - writeControlRegister(dev,readControlRegister(dev) | ARLAN_ACCESS ); } + writeControlRegister(dev, readControlRegister(dev) & ~ARLAN_RESET); } +#define setInterruptEnable(dev) {\ + writeControlRegister(dev, readControlRegister(dev) | ARLAN_INTERRUPT_ENABLE) ; } +#define clearInterruptEnable(dev) {\ + writeControlRegister(dev, readControlRegister(dev) & ~ARLAN_INTERRUPT_ENABLE) ; } +#define setClearInterrupt(dev) {\ + writeControlRegister(dev, readControlRegister(dev) | ARLAN_CLEAR_INTERRUPT) ; } +#define clearClearInterrupt(dev) {\ + writeControlRegister(dev, readControlRegister(dev) & ~ARLAN_CLEAR_INTERRUPT); } +#define setPowerOff(dev) {\ + writeControlRegister(dev, readControlRegister(dev) | (ARLAN_POWER && ARLAN_ACCESS));\ + writeControlRegister(dev, readControlRegister(dev) & ~ARLAN_ACCESS); } +#define setPowerOn(dev) {\ + writeControlRegister(dev, readControlRegister(dev) & ~(ARLAN_POWER)); } +#define arlan_lock_card_access(dev) {\ + writeControlRegister(dev, readControlRegister(dev) & ~ARLAN_ACCESS); } +#define arlan_unlock_card_access(dev) {\ + writeControlRegister(dev, readControlRegister(dev) | ARLAN_ACCESS); } @@ -525,7 +523,6 @@ struct arlan_private { | ARLAN_COMMAND_RESET) - #define ARLAN_DEBUG_CHAIN_LOCKS 0x00001 #define ARLAN_DEBUG_RESET 0x00002 #define ARLAN_DEBUG_TIMING 0x00004 @@ -536,4 +533,3 @@ struct arlan_private { #define ARLAN_DEBUG_INTERRUPT 0x00080 #define ARLAN_DEBUG_STARTUP 0x00100 #define ARLAN_DEBUG_SHUTDOWN 0x00200 - -- cgit v1.2.3 From aa1468b3faca778274ed0a79da52613fee48672e Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 17:36:57 +0100 Subject: Staging: rt3070: md4.h: Checkpatch cleanup WARNING: space prohibited between function name and open parenthesis '(' +void MD4Init (MD4_CTX *); WARNING: space prohibited between function name and open parenthesis '(' +void MD4Update (MD4_CTX *, u8 *, UINT); WARNING: space prohibited between function name and open parenthesis '(' +void MD4Final (u8 [16], MD4_CTX *); ERROR: do not use C99 // comments +#endif //__MD4_H__ Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rt3070/md4.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/rt3070/md4.h b/drivers/staging/rt3070/md4.h index a9cc7b0f3ee3..b3fb63726182 100644 --- a/drivers/staging/rt3070/md4.h +++ b/drivers/staging/rt3070/md4.h @@ -35,8 +35,8 @@ typedef struct _MD4_CTX_ { u8 buffer[64]; /* input buffer */ } MD4_CTX; -void MD4Init (MD4_CTX *); -void MD4Update (MD4_CTX *, u8 *, UINT); -void MD4Final (u8 [16], MD4_CTX *); +void MD4Init(MD4_CTX *); +void MD4Update(MD4_CTX *, u8 *, UINT); +void MD4Final(u8 [16], MD4_CTX *); -#endif //__MD4_H__ \ No newline at end of file +#endif /*__MD4_H__*/ -- cgit v1.2.3 From e22245b6c26fbb7dfb948382ceb242edccb3a7e3 Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 17:36:59 +0100 Subject: Staging: arlan: Makefile: Checkpatch cleanup ERROR: trailing whitespace +obj-$(CONFIG_ARLAN) += arlan.o $ Signed-off-by: Andrea Gelmini --- drivers/staging/arlan/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/staging/arlan/Makefile b/drivers/staging/arlan/Makefile index 9e58e5fae7b9..5a84d4402f21 100644 --- a/drivers/staging/arlan/Makefile +++ b/drivers/staging/arlan/Makefile @@ -1,3 +1,3 @@ -obj-$(CONFIG_ARLAN) += arlan.o +obj-$(CONFIG_ARLAN) += arlan.o arlan-objs := arlan-main.o arlan-proc.o -- cgit v1.2.3 From b91665e95d1968c3cd8dd0c3a9a8d617639db1a6 Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 17:36:58 +0100 Subject: Staging: arlan: arlan.h: more Checkpatch cleanup ERROR: do not use C99 // comments + volatile u_char radioModule;// shows EEPROM, can be overridden at 0x111 ERROR: do not use C99 // comments + volatile u_char defaultChannelSet; // shows EEProm, can be overriiden at 0x10A Signed-off-by: Andrea Gelmini --- drivers/staging/arlan/arlan.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/arlan/arlan.h b/drivers/staging/arlan/arlan.h index 19161f1feb5b..ffcd3ea048aa 100644 --- a/drivers/staging/arlan/arlan.h +++ b/drivers/staging/arlan/arlan.h @@ -90,8 +90,8 @@ struct arlan_shmem { volatile u_char hardwareType; volatile u_char majorHardwareVersion; volatile u_char minorHardwareVersion; - volatile u_char radioModule;// shows EEPROM, can be overridden at 0x111 - volatile u_char defaultChannelSet; // shows EEProm, can be overriiden at 0x10A + volatile u_char radioModule;/* shows EEPROM, can be overridden at 0x111 */ + volatile u_char defaultChannelSet; /* shows EEProm, can be overriiden at 0x10A */ volatile u_char _2[47]; /* Control/Status Block - 0x0080 */ -- cgit v1.2.3 From 5617f9da4619ec975514e6b385a052e024215da3 Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 17:37:00 +0100 Subject: Staging: comedi: drivers.c: Checkpatch cleanup WARNING: Use #include instead of +#include WARNING: braces {} are not necessary for any arm of this statement + if (dev->driver) { [...] + } else { [...] WARNING: braces {} are not necessary for single statement blocks + if (insn->insn == INSN_READ) { + data[0] = (new_data[1] >> (chan - base_bitfield_channel)) & 1; + } WARNING: braces {} are not necessary for single statement blocks + if (async->prealloc_buf && async->prealloc_bufsz == new_size) { + return 0; + } WARNING: braces {} are not necessary for single statement blocks + if (async->buf_page_list[i].virt_addr == NULL) { + break; + } WARNING: braces {} are not necessary for single statement blocks + if ((int)(async->buf_write_alloc_count + nbytes - free_end) > 0) { + nbytes = free_end - async->buf_write_alloc_count; + } WARNING: braces {} are not necessary for single statement blocks + if ((int)(async->buf_write_alloc_count + nbytes - free_end) > 0) { + nbytes = 0; + } WARNING: braces {} are not necessary for single statement blocks + if (async->buf_write_ptr >= async->prealloc_bufsz) { + async->buf_write_ptr %= async->prealloc_bufsz; + } Signed-off-by: Andrea Gelmini --- drivers/staging/comedi/drivers.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers.c b/drivers/staging/comedi/drivers.c index c2a632d31c61..44d6b62c230d 100644 --- a/drivers/staging/comedi/drivers.c +++ b/drivers/staging/comedi/drivers.c @@ -44,7 +44,7 @@ #include #include -#include +#include #include static int postconfig(struct comedi_device *dev); @@ -99,11 +99,10 @@ static void cleanup_device(struct comedi_device *dev) static void __comedi_device_detach(struct comedi_device *dev) { dev->attached = 0; - if (dev->driver) { + if (dev->driver) dev->driver->detach(dev); - } else { + else printk("BUG: dev->driver=NULL in comedi_device_detach()\n"); - } cleanup_device(dev); } @@ -380,9 +379,8 @@ static int insn_rw_emulate_bits(struct comedi_device *dev, if (ret < 0) return ret; - if (insn->insn == INSN_READ) { + if (insn->insn == INSN_READ) data[0] = (new_data[1] >> (chan - base_bitfield_channel)) & 1; - } return 1; } @@ -429,9 +427,9 @@ int comedi_buf_alloc(struct comedi_device *dev, struct comedi_subdevice *s, new_size = (new_size + PAGE_SIZE - 1) & PAGE_MASK; /* if no change is required, do nothing */ - if (async->prealloc_buf && async->prealloc_bufsz == new_size) { + if (async->prealloc_buf && async->prealloc_bufsz == new_size) return 0; - } + /* deallocate old buffer */ if (async->prealloc_buf) { vunmap(async->prealloc_buf); @@ -494,9 +492,9 @@ int comedi_buf_alloc(struct comedi_device *dev, struct comedi_subdevice *s, (void *) get_zeroed_page(GFP_KERNEL); } - if (async->buf_page_list[i].virt_addr == NULL) { + if (async->buf_page_list[i].virt_addr == NULL) break; - } + mem_map_reserve(virt_to_page (async->buf_page_list[i]. virt_addr)); @@ -619,9 +617,9 @@ unsigned int comedi_buf_write_alloc(struct comedi_async *async, { unsigned int free_end = async->buf_read_count + async->prealloc_bufsz; - if ((int)(async->buf_write_alloc_count + nbytes - free_end) > 0) { + if ((int)(async->buf_write_alloc_count + nbytes - free_end) > 0) nbytes = free_end - async->buf_write_alloc_count; - } + async->buf_write_alloc_count += nbytes; /* barrier insures the read of buf_read_count above occurs before we write data to the write-alloc'ed buffer space */ @@ -635,9 +633,9 @@ unsigned int comedi_buf_write_alloc_strict(struct comedi_async *async, { unsigned int free_end = async->buf_read_count + async->prealloc_bufsz; - if ((int)(async->buf_write_alloc_count + nbytes - free_end) > 0) { + if ((int)(async->buf_write_alloc_count + nbytes - free_end) > 0) nbytes = 0; - } + async->buf_write_alloc_count += nbytes; /* barrier insures the read of buf_read_count above occurs before we write data to the write-alloc'ed buffer space */ @@ -657,9 +655,9 @@ unsigned comedi_buf_write_free(struct comedi_async *async, unsigned int nbytes) async->buf_write_count += nbytes; async->buf_write_ptr += nbytes; comedi_buf_munge(async, async->buf_write_count - async->munge_count); - if (async->buf_write_ptr >= async->prealloc_bufsz) { + if (async->buf_write_ptr >= async->prealloc_bufsz) async->buf_write_ptr %= async->prealloc_bufsz; - } + return nbytes; } -- cgit v1.2.3 From 3a8954e8f22cf31791d8c524c2839433e39f9368 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Fri, 26 Feb 2010 17:58:07 -0700 Subject: staging: dt3155: revert u_long to u64 usage Commit 9c1390a923ddb6fba1cf9d7440743369140c6d8a replaced all u_int's with u32 and u_long's with u64. Unfortunately, a u_long is still only 32-bits so they should have been replaced with u32 also. This can be verified by the register definitions in dt3155_io.h. It specifically states that the memory mapped registers are 32-bit. Fix this by changing all the u64 to u32. Signed-off-by: H Hartley Sweeten Cc: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dt3155/allocator.c | 2 +- drivers/staging/dt3155/allocator.h | 2 +- drivers/staging/dt3155/dt3155.h | 24 ++--- drivers/staging/dt3155/dt3155_drv.c | 28 +++--- drivers/staging/dt3155/dt3155_io.c | 16 ++-- drivers/staging/dt3155/dt3155_io.h | 174 ++++++++++++++++++------------------ drivers/staging/dt3155/dt3155_isr.c | 54 +++++------ drivers/staging/dt3155/dt3155_isr.h | 2 +- 8 files changed, 151 insertions(+), 151 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dt3155/allocator.c b/drivers/staging/dt3155/allocator.c index 114e2a86fefa..c74234c66895 100644 --- a/drivers/staging/dt3155/allocator.c +++ b/drivers/staging/dt3155/allocator.c @@ -195,7 +195,7 @@ int allocator_free_dma(unsigned long address) * On cleanup everything is released. If the list is not empty, that a * problem of our clients */ -int allocator_init(u64 *allocator_max) +int allocator_init(u32 *allocator_max) { /* check how much free memory is there */ void *remapped; diff --git a/drivers/staging/dt3155/allocator.h b/drivers/staging/dt3155/allocator.h index 4cd81bdb3faa..bdf3268ca52d 100644 --- a/drivers/staging/dt3155/allocator.h +++ b/drivers/staging/dt3155/allocator.h @@ -24,5 +24,5 @@ void allocator_free_dma(unsigned long address); unsigned long allocator_allocate_dma(unsigned long kilobytes, int priority); -int allocator_init(u64 *); +int allocator_init(u32 *); void allocator_cleanup(void); diff --git a/drivers/staging/dt3155/dt3155.h b/drivers/staging/dt3155/dt3155.h index 22292b102a33..1bf786364eec 100644 --- a/drivers/staging/dt3155/dt3155.h +++ b/drivers/staging/dt3155/dt3155.h @@ -79,8 +79,8 @@ struct dt3155_config_s { /* hold data for each frame */ typedef struct { - u64 addr; /* address of the buffer with the frame */ - u64 tag; /* unique number for the frame */ + u32 addr; /* address of the buffer with the frame */ + u32 tag; /* unique number for the frame */ struct timeval time; /* time that capture took place */ } frame_info_t; @@ -101,14 +101,14 @@ struct dt3155_fbuffer_s { int locked_buf; /* Buffers used by user */ int ready_que[BOARD_MAX_BUFFS]; - u64 ready_head; /* The most recent buffer located here */ - u64 ready_len; /* The number of ready buffers */ + u32 ready_head; /* The most recent buffer located here */ + u32 ready_len; /* The number of ready buffers */ int even_happened; int even_stopped; int stop_acquire; /* Flag to stop interrupts */ - u64 frame_count; /* Counter for frames acquired by this card */ + u32 frame_count; /* Counter for frames acquired by this card */ }; @@ -122,13 +122,13 @@ struct dt3155_fbuffer_s { /* There is one status structure for each card. */ typedef struct dt3155_status_s { int fixed_mode; /* if 1, we are in fixed frame mode */ - u64 reg_addr; /* Register address for a single card */ - u64 mem_addr; /* Buffer start addr for this card */ - u64 mem_size; /* This is the amount of mem available */ + u32 reg_addr; /* Register address for a single card */ + u32 mem_addr; /* Buffer start addr for this card */ + u32 mem_size; /* This is the amount of mem available */ u32 irq; /* this card's irq */ struct dt3155_config_s config; /* configuration struct */ struct dt3155_fbuffer_s fbuffer; /* frame buffer state struct */ - u64 state; /* this card's state */ + u32 state; /* this card's state */ u32 device_installed; /* Flag if installed. 1=installed */ } dt3155_status_t; @@ -161,9 +161,9 @@ extern struct dt3155_status_s dt3155_status[MAXBOARDS]; /* User code will probably want to declare one of these for each card */ typedef struct dt3155_read_s { - u64 offset; - u64 frame_seq; - u64 state; + u32 offset; + u32 frame_seq; + u32 state; frame_info_t frame_info; } dt3155_read_t; diff --git a/drivers/staging/dt3155/dt3155_drv.c b/drivers/staging/dt3155/dt3155_drv.c index 930a3e666c0a..a67c622869d2 100644 --- a/drivers/staging/dt3155/dt3155_drv.c +++ b/drivers/staging/dt3155/dt3155_drv.c @@ -137,7 +137,7 @@ u32 dt3155_dev_open[ MAXBOARDS ] = {0 }; u32 ndevices = 0; -u64 unique_tag = 0;; +u32 unique_tag = 0;; /* @@ -180,7 +180,7 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) int minor = -1; int index; unsigned long flags; - u64 buffer_addr; + u32 buffer_addr; /* find out who issued the interrupt */ for ( index = 0; index < ndevices; index++ ) { @@ -249,7 +249,7 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) { /* GCS (Aug 2, 2002) -- In field mode, dma the odd field into the lower half of the buffer */ - const u64 stride = dt3155_status[ minor ].config.cols; + const u32 stride = dt3155_status[ minor ].config.cols; buffer_addr = dt3155_fbuffer[ minor ]-> frame_info[ dt3155_fbuffer[ minor ]->active_buf ].addr + (DT3155_MAX_ROWS / 2) * stride; @@ -312,7 +312,7 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) dt3155_fbuffer[ minor ]->even_stopped = 0; printk(KERN_DEBUG "dt3155: state is now %x\n", - (u32)dt3155_status[minor].state); + dt3155_status[minor].state); } else { @@ -428,7 +428,7 @@ static inline void dt3155_isr( int irq, void *dev_id, struct pt_regs *regs ) *****************************************************/ static void dt3155_init_isr(int minor) { - const u64 stride = dt3155_status[ minor ].config.cols; + const u32 stride = dt3155_status[ minor ].config.cols; switch (dt3155_status[ minor ].state & DT3155_STATE_MODE) { @@ -706,7 +706,7 @@ static int dt3155_open( struct inode* inode, struct file* filep) if (dt3155_status[ minor ].state != DT3155_STATE_IDLE) { printk ("DT3155: Not in idle state (state = %x)\n", - (u32)dt3155_status[ minor ].state); + dt3155_status[ minor ].state); return -EBUSY; } @@ -762,7 +762,7 @@ static ssize_t dt3155_read(struct file *filep, char __user *buf, { /* which device are we reading from? */ int minor = MINOR(filep->f_dentry->d_inode->i_rdev); - u64 offset; + u32 offset; int frame_index; frame_info_t *frame_info_p; @@ -820,11 +820,11 @@ static ssize_t dt3155_read(struct file *filep, char __user *buf, offset = frame_info_p->addr - dt3155_status[minor].mem_addr; put_user(offset, (unsigned int *) buf); - buf += sizeof(u64); + buf += sizeof(u32); put_user( dt3155_status[minor].fbuffer.frame_count, (unsigned int *) buf); - buf += sizeof(u64); + buf += sizeof(u32); put_user(dt3155_status[minor].state, (unsigned int *) buf); - buf += sizeof(u64); + buf += sizeof(u32); if (copy_to_user(buf, frame_info_p, sizeof(frame_info_t))) return -EFAULT; @@ -931,7 +931,7 @@ static int find_PCI (void) dt3155_status[ pci_index-1 ].device_installed = 1; printk("DT3155: Installing device %d w/irq %d and address %p\n", pci_index, - (u32)dt3155_status[pci_index-1].irq, + dt3155_status[pci_index-1].irq, dt3155_lbase[pci_index-1]); } @@ -944,7 +944,7 @@ err: return DT_3155_FAILURE; } -u64 allocatorAddr = 0; +u32 allocatorAddr = 0; /***************************************************** * init_module() @@ -1024,9 +1024,9 @@ int init_module(void) dt3155_status[ index ].config.rows); printk("DT3155: m_addr = 0x%x; m_size = %ld; " "state = %d; device_installed = %d\n", - (u32)dt3155_status[ index ].mem_addr, + dt3155_status[ index ].mem_addr, (long int)dt3155_status[ index ].mem_size, - (u32)dt3155_status[ index ].state, + dt3155_status[ index ].state, dt3155_status[ index ].device_installed); } diff --git a/drivers/staging/dt3155/dt3155_io.c b/drivers/staging/dt3155/dt3155_io.c index 1c15604f4313..6b9c68501a61 100644 --- a/drivers/staging/dt3155/dt3155_io.c +++ b/drivers/staging/dt3155/dt3155_io.c @@ -27,12 +27,12 @@ /****** local copies of board's 32 bit registers ******/ -u64 even_dma_start_r; /* bit 0 should always be 0 */ -u64 odd_dma_start_r; /* .. */ -u64 even_dma_stride_r; /* bits 0&1 should always be 0 */ -u64 odd_dma_stride_r; /* .. */ -u64 even_pixel_fmt_r; -u64 odd_pixel_fmt_r; +u32 even_dma_start_r; /* bit 0 should always be 0 */ +u32 odd_dma_start_r; /* .. */ +u32 even_dma_stride_r; /* bits 0&1 should always be 0 */ +u32 odd_dma_stride_r; /* .. */ +u32 even_pixel_fmt_r; +u32 odd_pixel_fmt_r; FIFO_TRIGGER_R fifo_trigger_r; XFER_MODE_R xfer_mode_r; @@ -40,8 +40,8 @@ CSR1_R csr1_r; RETRY_WAIT_CNT_R retry_wait_cnt_r; INT_CSR_R int_csr_r; -u64 even_fld_mask_r; -u64 odd_fld_mask_r; +u32 even_fld_mask_r; +u32 odd_fld_mask_r; MASK_LENGTH_R mask_length_r; FIFO_FLAG_CNT_R fifo_flag_cnt_r; diff --git a/drivers/staging/dt3155/dt3155_io.h b/drivers/staging/dt3155/dt3155_io.h index a135aada5902..d1a25100169f 100644 --- a/drivers/staging/dt3155/dt3155_io.h +++ b/drivers/staging/dt3155/dt3155_io.h @@ -36,8 +36,8 @@ MA 02111-1307 USA /* macros to access registers */ -#define WriteMReg(Address, Data) (*((u64 *)(Address)) = Data) -#define ReadMReg(Address, Data) (Data = *((u64 *)(Address))) +#define WriteMReg(Address, Data) (*((u32 *)(Address)) = Data) +#define ReadMReg(Address, Data) (Data = *((u32 *)(Address))) /***************** 32 bit register globals **************/ @@ -71,114 +71,114 @@ MA 02111-1307 USA /******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/ typedef union fifo_trigger_tag { - u64 reg; + u32 reg; struct { - u64 PACKED:6; - u64 :9; - u64 PLANER:7; - u64 :9; + u32 PACKED:6; + u32 :9; + u32 PLANER:7; + u32 :9; } fld; } FIFO_TRIGGER_R; typedef union xfer_mode_tag { - u64 reg; + u32 reg; struct { - u64 :2; - u64 FIELD_TOGGLE:1; - u64 :5; - u64 :2; - u64 :22; + u32 :2; + u32 FIELD_TOGGLE:1; + u32 :5; + u32 :2; + u32 :22; } fld; } XFER_MODE_R; typedef union csr1_tag { - u64 reg; + u32 reg; struct { - u64 CAP_CONT_EVE:1; - u64 CAP_CONT_ODD:1; - u64 CAP_SNGL_EVE:1; - u64 CAP_SNGL_ODD:1; - u64 FLD_DN_EVE :1; - u64 FLD_DN_ODD :1; - u64 SRST :1; - u64 FIFO_EN :1; - u64 FLD_CRPT_EVE:1; - u64 FLD_CRPT_ODD:1; - u64 ADDR_ERR_EVE:1; - u64 ADDR_ERR_ODD:1; - u64 CRPT_DIS :1; - u64 RANGE_EN :1; - u64 :16; + u32 CAP_CONT_EVE:1; + u32 CAP_CONT_ODD:1; + u32 CAP_SNGL_EVE:1; + u32 CAP_SNGL_ODD:1; + u32 FLD_DN_EVE :1; + u32 FLD_DN_ODD :1; + u32 SRST :1; + u32 FIFO_EN :1; + u32 FLD_CRPT_EVE:1; + u32 FLD_CRPT_ODD:1; + u32 ADDR_ERR_EVE:1; + u32 ADDR_ERR_ODD:1; + u32 CRPT_DIS :1; + u32 RANGE_EN :1; + u32 :16; } fld; } CSR1_R; typedef union retry_wait_cnt_tag { - u64 reg; + u32 reg; struct { - u64 RTRY_WAIT_CNT:8; - u64 :24; + u32 RTRY_WAIT_CNT:8; + u32 :24; } fld; } RETRY_WAIT_CNT_R; typedef union int_csr_tag { - u64 reg; + u32 reg; struct { - u64 FLD_END_EVE :1; - u64 FLD_END_ODD :1; - u64 FLD_START :1; - u64 :5; - u64 FLD_END_EVE_EN:1; - u64 FLD_END_ODD_EN:1; - u64 FLD_START_EN :1; - u64 :21; + u32 FLD_END_EVE :1; + u32 FLD_END_ODD :1; + u32 FLD_START :1; + u32 :5; + u32 FLD_END_EVE_EN:1; + u32 FLD_END_ODD_EN:1; + u32 FLD_START_EN :1; + u32 :21; } fld; } INT_CSR_R; typedef union mask_length_tag { - u64 reg; + u32 reg; struct { - u64 MASK_LEN_EVE:5; - u64 :11; - u64 MASK_LEN_ODD:5; - u64 :11; + u32 MASK_LEN_EVE:5; + u32 :11; + u32 MASK_LEN_ODD:5; + u32 :11; } fld; } MASK_LENGTH_R; typedef union fifo_flag_cnt_tag { - u64 reg; + u32 reg; struct { - u64 AF_COUNT:7; - u64 :9; - u64 AE_COUNT:7; - u64 :9; + u32 AF_COUNT:7; + u32 :9; + u32 AE_COUNT:7; + u32 :9; } fld; } FIFO_FLAG_CNT_R; typedef union iic_clk_dur { - u64 reg; + u32 reg; struct { - u64 PHASE_1:8; - u64 PHASE_2:8; - u64 PHASE_3:8; - u64 PHASE_4:8; + u32 PHASE_1:8; + u32 PHASE_2:8; + u32 PHASE_3:8; + u32 PHASE_4:8; } fld; } IIC_CLK_DUR_R; typedef union iic_csr1_tag { - u64 reg; + u32 reg; struct { - u64 AUTO_EN :1; - u64 BYPASS :1; - u64 SDA_OUT :1; - u64 SCL_OUT :1; - u64 :4; - u64 AUTO_ABORT :1; - u64 DIRECT_ABORT:1; - u64 SDA_IN :1; - u64 SCL_IN :1; - u64 :4; - u64 AUTO_ADDR :8; - u64 RD_DATA :8; + u32 AUTO_EN :1; + u32 BYPASS :1; + u32 SDA_OUT :1; + u32 SCL_OUT :1; + u32 :4; + u32 AUTO_ABORT :1; + u32 DIRECT_ABORT:1; + u32 SDA_IN :1; + u32 SCL_IN :1; + u32 :4; + u32 AUTO_ADDR :8; + u32 RD_DATA :8; } fld; } IIC_CSR1_R; @@ -186,14 +186,14 @@ typedef union iic_csr1_tag { * iic_csr2_tag */ typedef union iic_csr2_tag { - u64 reg; + u32 reg; struct { - u64 DIR_WR_DATA :8; - u64 DIR_SUB_ADDR:8; - u64 DIR_RD :1; - u64 DIR_ADDR :7; - u64 NEW_CYCLE :1; - u64 :7; + u32 DIR_WR_DATA :8; + u32 DIR_SUB_ADDR:8; + u32 DIR_RD :1; + u32 DIR_ADDR :7; + u32 NEW_CYCLE :1; + u32 :7; } fld; } IIC_CSR2_R; @@ -203,10 +203,10 @@ typedef union iic_csr2_tag { * dma_upper_lmt_tag */ typedef union dma_upper_lmt_tag { - u64 reg; + u32 reg; struct { - u64 DMA_UPPER_LMT_VAL:24; - u64 :8; + u32 DMA_UPPER_LMT_VAL:24; + u32 :8; } fld; } DMA_UPPER_LMT_R; @@ -214,12 +214,12 @@ typedef union dma_upper_lmt_tag { /* * Global declarations of local copies of boards' 32 bit registers */ -extern u64 even_dma_start_r; /* bit 0 should always be 0 */ -extern u64 odd_dma_start_r; /* .. */ -extern u64 even_dma_stride_r; /* bits 0&1 should always be 0 */ -extern u64 odd_dma_stride_r; /* .. */ -extern u64 even_pixel_fmt_r; -extern u64 odd_pixel_fmt_r; +extern u32 even_dma_start_r; /* bit 0 should always be 0 */ +extern u32 odd_dma_start_r; /* .. */ +extern u32 even_dma_stride_r; /* bits 0&1 should always be 0 */ +extern u32 odd_dma_stride_r; /* .. */ +extern u32 even_pixel_fmt_r; +extern u32 odd_pixel_fmt_r; extern FIFO_TRIGGER_R fifo_trigger_r; extern XFER_MODE_R xfer_mode_r; @@ -227,8 +227,8 @@ extern CSR1_R csr1_r; extern RETRY_WAIT_CNT_R retry_wait_cnt_r; extern INT_CSR_R int_csr_r; -extern u64 even_fld_mask_r; -extern u64 odd_fld_mask_r; +extern u32 even_fld_mask_r; +extern u32 odd_fld_mask_r; extern MASK_LENGTH_R mask_length_r; extern FIFO_FLAG_CNT_R fifo_flag_cnt_r; diff --git a/drivers/staging/dt3155/dt3155_isr.c b/drivers/staging/dt3155/dt3155_isr.c index 5b790867c292..fd7f93d6c33d 100644 --- a/drivers/staging/dt3155/dt3155_isr.c +++ b/drivers/staging/dt3155/dt3155_isr.c @@ -220,7 +220,7 @@ inline void printques( int m ) * the start address up to the beginning of the * next 4MB chunk (assuming bufsize < 4MB). *****************************************************/ -u64 adjust_4MB (u64 buf_addr, u64 bufsize) { +u32 adjust_4MB (u32 buf_addr, u32 bufsize) { if (((buf_addr+bufsize) & UPPER_10_BITS) != (buf_addr & UPPER_10_BITS)) return (buf_addr+bufsize) & UPPER_10_BITS; else @@ -235,26 +235,26 @@ u64 adjust_4MB (u64 buf_addr, u64 bufsize) { * buffers. If there is not enough free space * try for less memory. *****************************************************/ -void allocate_buffers (u64 *buf_addr, u64* total_size_kbs, - u64 bufsize) +void allocate_buffers (u32 *buf_addr, u32* total_size_kbs, + u32 bufsize) { /* Compute the minimum amount of memory guaranteed to hold all MAXBUFFERS such that no buffer crosses the 4MB boundary. Store this value in the variable "full_size" */ - u64 allocator_max; - u64 bufs_per_chunk = (FOUR_MB / bufsize); - u64 filled_chunks = (MAXBUFFERS-1) / bufs_per_chunk; - u64 leftover_bufs = MAXBUFFERS - filled_chunks * bufs_per_chunk; + u32 allocator_max; + u32 bufs_per_chunk = (FOUR_MB / bufsize); + u32 filled_chunks = (MAXBUFFERS-1) / bufs_per_chunk; + u32 leftover_bufs = MAXBUFFERS - filled_chunks * bufs_per_chunk; - u64 full_size = bufsize /* possibly unusable part of 1st chunk */ + u32 full_size = bufsize /* possibly unusable part of 1st chunk */ + filled_chunks * FOUR_MB /* max # of completely filled 4mb chunks */ + leftover_bufs * bufsize; /* these buffs will be in a partly filled chunk at beginning or end */ - u64 full_size_kbs = 1 + (full_size-1) / 1024; - u64 min_size_kbs = 2*ndevices*bufsize / 1024; - u64 size_kbs; + u32 full_size_kbs = 1 + (full_size-1) / 1024; + u32 min_size_kbs = 2*ndevices*bufsize / 1024; + u32 size_kbs; /* Now, try to allocate full_size. If this fails, keep trying for less & less memory until it succeeds. */ @@ -264,13 +264,13 @@ void allocate_buffers (u64 *buf_addr, u64* total_size_kbs, #endif size_kbs = full_size_kbs; *buf_addr = 0; - printk ("DT3155: We would like to get: %d KB\n", (u32)(full_size_kbs)); - printk ("DT3155: ...but need at least: %d KB\n", (u32)(min_size_kbs)); - printk ("DT3155: ...the allocator has: %d KB\n", (u32)(allocator_max)); + printk("DT3155: We would like to get: %d KB\n", full_size_kbs); + printk("DT3155: ...but need at least: %d KB\n", min_size_kbs); + printk("DT3155: ...the allocator has: %d KB\n", allocator_max); size_kbs = (full_size_kbs <= allocator_max ? full_size_kbs : allocator_max); if (size_kbs > min_size_kbs) { if ((*buf_addr = allocator_allocate_dma (size_kbs, GFP_KERNEL)) != 0) { - printk ("DT3155: Managed to allocate: %d KB\n", (u32)size_kbs); + printk("DT3155: Managed to allocate: %d KB\n", size_kbs); *total_size_kbs = size_kbs; return; } @@ -298,17 +298,17 @@ void allocate_buffers (u64 *buf_addr, u64* total_size_kbs, * 4MB boundary. Also, add error checking. This * function will return -ENOMEM when not enough memory. *****************************************************/ -u64 dt3155_setup_buffers(u64 *allocatorAddr) +u32 dt3155_setup_buffers(u32 *allocatorAddr) { - u64 index; - u64 rambuff_addr; /* start of allocation */ - u64 rambuff_size; /* total size allocated to driver */ - u64 rambuff_acm; /* accumlator, keep track of how much + u32 index; + u32 rambuff_addr; /* start of allocation */ + u32 rambuff_size; /* total size allocated to driver */ + u32 rambuff_acm; /* accumlator, keep track of how much is left after being split up*/ - u64 rambuff_end; /* end of rambuff */ - u64 numbufs; /* number of useful buffers allocated (per device) */ - u64 bufsize = DT3155_MAX_ROWS * DT3155_MAX_COLS; + u32 rambuff_end; /* end of rambuff */ + u32 numbufs; /* number of useful buffers allocated (per device) */ + u32 bufsize = DT3155_MAX_ROWS * DT3155_MAX_COLS; int m; /* minor # of device, looped for all devs */ /* zero the fbuffer status and address structure */ @@ -326,9 +326,9 @@ u64 dt3155_setup_buffers(u64 *allocatorAddr) /* allocate a large contiguous chunk of RAM */ allocate_buffers (&rambuff_addr, &rambuff_size, bufsize); - printk( "DT3155: mem info\n" ); - printk( " - rambuf_addr = 0x%x \n", (u32)rambuff_addr ); - printk( " - length (kb) = %u \n", (u32)rambuff_size ); + printk("DT3155: mem info\n"); + printk(" - rambuf_addr = 0x%x \n", rambuff_addr); + printk(" - length (kb) = %u \n", rambuff_size); if( rambuff_addr == 0 ) { printk( KERN_INFO @@ -350,7 +350,7 @@ u64 dt3155_setup_buffers(u64 *allocatorAddr) /* Following line is OK, will waste buffers if index * not evenly divisible by ndevices -NJC*/ numbufs = index / ndevices; - printk (" - numbufs = %u\n", (u32) numbufs); + printk(" - numbufs = %u\n", numbufs); if (numbufs < 2) { printk( KERN_INFO "DT3155: Error setup_buffers() couldn't allocate 2 bufs/board\n" ); diff --git a/drivers/staging/dt3155/dt3155_isr.h b/drivers/staging/dt3155/dt3155_isr.h index 7f27910eb941..7595cb16c988 100644 --- a/drivers/staging/dt3155/dt3155_isr.h +++ b/drivers/staging/dt3155/dt3155_isr.h @@ -42,7 +42,7 @@ extern struct dt3155_fbuffer_s *dt3155_fbuffer[MAXBOARDS]; /* Initialize the buffering system. This should */ /* be called prior to enabling interrupts */ -u64 dt3155_setup_buffers(u64 *allocatorAddr); +u32 dt3155_setup_buffers(u32 *allocatorAddr); /* Get the next frame of data if it is ready. Returns */ /* zero if no data is ready. If there is data but */ -- cgit v1.2.3 From aa75db0080603bae27961c0502812dfd0f522bb3 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 3 Mar 2010 21:21:10 -0700 Subject: ioat: close potential BUG_ON race in the descriptor cleanup path Since ioat_cleanup_preamble() and the update of the last completed descriptor are not synchronized there is a chance that two cleanup threads can see descriptors to clean. If the first cleans up all pending descriptors then the second will trigger the BUG_ON. Signed-off-by: Dan Williams --- drivers/dma/ioat/dma_v2.c | 2 +- drivers/dma/ioat/dma_v3.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index c6e4531fe524..01ed1cfd3eb6 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -158,7 +158,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete) seen_current = true; } ioat->tail += i; - BUG_ON(!seen_current); /* no active descs have written a completion? */ + BUG_ON(active && !seen_current); /* no active descs have written a completion? */ chan->last_completion = phys_complete; if (ioat->head == ioat->tail) { diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index bff48e8cffc4..39520f2f7da9 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -293,7 +293,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete) } } ioat->tail += i; - BUG_ON(!seen_current); /* no active descs have written a completion? */ + BUG_ON(active && !seen_current); /* no active descs have written a completion? */ chan->last_completion = phys_complete; if (ioat->head == ioat->tail) { dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", -- cgit v1.2.3 From b9cc98697d1ca35a86bbb708acc6d93993c28f0f Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 3 Mar 2010 21:21:13 -0700 Subject: ioat3: interrupt coalescing The hardware automatically disables further interrupts after each event until rearmed. This allows a delay to be injected between the occurence of the interrupt and the running of the cleanup routine. The delay is scaled by the descriptor backlog and then written to the INTRDELAY register which specifies the number of microseconds to hold off interrupt delivery after an interrupt event occurs. According to powertop this reduces the interrupt rate from ~5000 intr/s to ~150 intr/s per without affecting throughput (simple dd to a raid6 array). Signed-off-by: Dan Williams --- drivers/dma/ioat/dma_v3.c | 37 +++++++++++++++++++++++++++++++++---- drivers/dma/ioat/registers.h | 2 +- 2 files changed, 34 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index 39520f2f7da9..9988f1340186 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -295,15 +295,23 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete) ioat->tail += i; BUG_ON(active && !seen_current); /* no active descs have written a completion? */ chan->last_completion = phys_complete; - if (ioat->head == ioat->tail) { + + active = ioat2_ring_active(ioat); + if (active == 0) { dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", __func__); clear_bit(IOAT_COMPLETION_PENDING, &chan->state); mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); } + /* 5 microsecond delay per pending descriptor */ + writew(min((5 * active), IOAT_INTRDELAY_MASK), + chan->device->reg_base + IOAT_INTRDELAY_OFFSET); } -static void ioat3_cleanup(struct ioat2_dma_chan *ioat) +/* try to cleanup, but yield (via spin_trylock) to incoming submissions + * with the expectation that we will immediately poll again shortly + */ +static void ioat3_cleanup_poll(struct ioat2_dma_chan *ioat) { struct ioat_chan_common *chan = &ioat->base; unsigned long phys_complete; @@ -329,11 +337,32 @@ static void ioat3_cleanup(struct ioat2_dma_chan *ioat) spin_unlock_bh(&chan->cleanup_lock); } +/* run cleanup now because we already delayed the interrupt via INTRDELAY */ +static void ioat3_cleanup_sync(struct ioat2_dma_chan *ioat) +{ + struct ioat_chan_common *chan = &ioat->base; + unsigned long phys_complete; + + prefetch(chan->completion); + + spin_lock_bh(&chan->cleanup_lock); + if (!ioat_cleanup_preamble(chan, &phys_complete)) { + spin_unlock_bh(&chan->cleanup_lock); + return; + } + spin_lock_bh(&ioat->ring_lock); + + __cleanup(ioat, phys_complete); + + spin_unlock_bh(&ioat->ring_lock); + spin_unlock_bh(&chan->cleanup_lock); +} + static void ioat3_cleanup_tasklet(unsigned long data) { struct ioat2_dma_chan *ioat = (void *) data; - ioat3_cleanup(ioat); + ioat3_cleanup_sync(ioat); writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); } @@ -417,7 +446,7 @@ ioat3_is_complete(struct dma_chan *c, dma_cookie_t cookie, if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) return DMA_SUCCESS; - ioat3_cleanup(ioat); + ioat3_cleanup_poll(ioat); return ioat_is_complete(c, cookie, done, used); } diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h index e8ae63baf588..1391798542b6 100644 --- a/drivers/dma/ioat/registers.h +++ b/drivers/dma/ioat/registers.h @@ -60,7 +60,7 @@ #define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */ #define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */ -#define IOAT_INTRDELAY_INT_DELAY_MASK 0x3FFF /* Interrupt Delay Time */ +#define IOAT_INTRDELAY_MASK 0x3FFF /* Interrupt Delay Time */ #define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */ #define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */ -- cgit v1.2.3 From aa4d72ae946a4fa40486b871717778734184fa29 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 3 Mar 2010 21:21:13 -0700 Subject: ioat: cleanup ->timer_fn() and ->cleanup_fn() prototypes If the calling convention of ->timer_fn() and ->cleanup_fn() are unified across hardware versions we can drop parameters to ioat_init_channel() and unify ioat_is_dma_complete() implementations. Both ->timer_fn() and ->cleanup_fn() are modified to expect a struct dma_chan pointer. Signed-off-by: Dan Williams --- drivers/dma/ioat/dma.c | 46 ++++++++++++++++++++-------------------------- drivers/dma/ioat/dma.h | 11 +++++------ drivers/dma/ioat/dma_v2.c | 34 ++++++++-------------------------- drivers/dma/ioat/dma_v2.h | 4 +--- drivers/dma/ioat/dma_v3.c | 12 ++++++------ 5 files changed, 40 insertions(+), 67 deletions(-) (limited to 'drivers') diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index dcc4ab78b32b..5d0e42b263df 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -94,16 +94,12 @@ static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) return IRQ_HANDLED; } -static void ioat1_cleanup_tasklet(unsigned long data); - /* common channel initialization */ -void ioat_init_channel(struct ioatdma_device *device, - struct ioat_chan_common *chan, int idx, - void (*timer_fn)(unsigned long), - void (*tasklet)(unsigned long), - unsigned long ioat) +void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *chan, int idx) { struct dma_device *dma = &device->common; + struct dma_chan *c = &chan->common; + unsigned long data = (unsigned long) c; chan->device = device; chan->reg_base = device->reg_base + (0x80 * (idx + 1)); @@ -112,14 +108,12 @@ void ioat_init_channel(struct ioatdma_device *device, list_add_tail(&chan->common.device_node, &dma->channels); device->idx[idx] = chan; init_timer(&chan->timer); - chan->timer.function = timer_fn; - chan->timer.data = ioat; - tasklet_init(&chan->cleanup_task, tasklet, ioat); + chan->timer.function = device->timer_fn; + chan->timer.data = data; + tasklet_init(&chan->cleanup_task, device->cleanup_fn, data); tasklet_disable(&chan->cleanup_task); } -static void ioat1_timer_event(unsigned long data); - /** * ioat1_dma_enumerate_channels - find and initialize the device's channels * @device: the device to be enumerated @@ -155,10 +149,7 @@ static int ioat1_enumerate_channels(struct ioatdma_device *device) if (!ioat) break; - ioat_init_channel(device, &ioat->base, i, - ioat1_timer_event, - ioat1_cleanup_tasklet, - (unsigned long) ioat); + ioat_init_channel(device, &ioat->base, i); ioat->xfercap = xfercap; spin_lock_init(&ioat->desc_lock); INIT_LIST_HEAD(&ioat->free_desc); @@ -532,12 +523,12 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, return &desc->txd; } -static void ioat1_cleanup_tasklet(unsigned long data) +static void ioat1_cleanup_event(unsigned long data) { - struct ioat_dma_chan *chan = (void *)data; + struct ioat_dma_chan *ioat = to_ioat_chan((void *) data); - ioat1_cleanup(chan); - writew(IOAT_CHANCTRL_RUN, chan->base.reg_base + IOAT_CHANCTRL_OFFSET); + ioat1_cleanup(ioat); + writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); } void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, @@ -687,7 +678,7 @@ static void ioat1_cleanup(struct ioat_dma_chan *ioat) static void ioat1_timer_event(unsigned long data) { - struct ioat_dma_chan *ioat = (void *) data; + struct ioat_dma_chan *ioat = to_ioat_chan((void *) data); struct ioat_chan_common *chan = &ioat->base; dev_dbg(to_dev(chan), "%s: state: %lx\n", __func__, chan->state); @@ -734,16 +725,17 @@ static void ioat1_timer_event(unsigned long data) spin_unlock_bh(&chan->cleanup_lock); } -static enum dma_status -ioat1_dma_is_complete(struct dma_chan *c, dma_cookie_t cookie, +enum dma_status +ioat_is_dma_complete(struct dma_chan *c, dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used) { - struct ioat_dma_chan *ioat = to_ioat_chan(c); + struct ioat_chan_common *chan = to_chan_common(c); + struct ioatdma_device *device = chan->device; if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) return DMA_SUCCESS; - ioat1_cleanup(ioat); + device->cleanup_fn((unsigned long) c); return ioat_is_complete(c, cookie, done, used); } @@ -1199,12 +1191,14 @@ int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca) device->intr_quirk = ioat1_intr_quirk; device->enumerate_channels = ioat1_enumerate_channels; device->self_test = ioat_dma_self_test; + device->timer_fn = ioat1_timer_event; + device->cleanup_fn = ioat1_cleanup_event; dma = &device->common; dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy; dma->device_issue_pending = ioat1_dma_memcpy_issue_pending; dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources; dma->device_free_chan_resources = ioat1_dma_free_chan_resources; - dma->device_is_tx_complete = ioat1_dma_is_complete; + dma->device_is_tx_complete = ioat_is_dma_complete; err = ioat_probe(device); if (err) diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index bbc3e78ef333..4f747a254074 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -61,7 +61,7 @@ * @intr_quirk: interrupt setup quirk (for ioat_v1 devices) * @enumerate_channels: hw version specific channel enumeration * @reset_hw: hw version specific channel (re)initialization - * @cleanup_tasklet: select between the v2 and v3 cleanup routines + * @cleanup_fn: select between the v2 and v3 cleanup routines * @timer_fn: select between the v2 and v3 timer watchdog routines * @self_test: hardware version specific self test for each supported op type * @@ -80,7 +80,7 @@ struct ioatdma_device { void (*intr_quirk)(struct ioatdma_device *device); int (*enumerate_channels)(struct ioatdma_device *device); int (*reset_hw)(struct ioat_chan_common *chan); - void (*cleanup_tasklet)(unsigned long data); + void (*cleanup_fn)(unsigned long data); void (*timer_fn)(unsigned long data); int (*self_test)(struct ioatdma_device *device); }; @@ -337,10 +337,9 @@ struct dca_provider * __devinit ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); unsigned long ioat_get_current_completion(struct ioat_chan_common *chan); void ioat_init_channel(struct ioatdma_device *device, - struct ioat_chan_common *chan, int idx, - void (*timer_fn)(unsigned long), - void (*tasklet)(unsigned long), - unsigned long ioat); + struct ioat_chan_common *chan, int idx); +enum dma_status ioat_is_dma_complete(struct dma_chan *c, dma_cookie_t cookie, + dma_cookie_t *done, dma_cookie_t *used); void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, size_t len, struct ioat_dma_descriptor *hw); bool ioat_cleanup_preamble(struct ioat_chan_common *chan, diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 01ed1cfd3eb6..25a3c72b2941 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -199,9 +199,9 @@ static void ioat2_cleanup(struct ioat2_dma_chan *ioat) spin_unlock_bh(&chan->cleanup_lock); } -void ioat2_cleanup_tasklet(unsigned long data) +void ioat2_cleanup_event(unsigned long data) { - struct ioat2_dma_chan *ioat = (void *) data; + struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); ioat2_cleanup(ioat); writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); @@ -283,7 +283,7 @@ static void ioat2_restart_channel(struct ioat2_dma_chan *ioat) void ioat2_timer_event(unsigned long data) { - struct ioat2_dma_chan *ioat = (void *) data; + struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); struct ioat_chan_common *chan = &ioat->base; spin_lock_bh(&chan->cleanup_lock); @@ -389,10 +389,7 @@ int ioat2_enumerate_channels(struct ioatdma_device *device) if (!ioat) break; - ioat_init_channel(device, &ioat->base, i, - device->timer_fn, - device->cleanup_tasklet, - (unsigned long) ioat); + ioat_init_channel(device, &ioat->base, i); ioat->xfercap_log = xfercap_log; spin_lock_init(&ioat->ring_lock); if (device->reset_hw(&ioat->base)) { @@ -692,7 +689,7 @@ int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_descs) mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); spin_unlock_bh(&chan->cleanup_lock); - device->timer_fn((unsigned long) ioat); + device->timer_fn((unsigned long) &chan->common); } else spin_unlock_bh(&chan->cleanup_lock); return -ENOMEM; @@ -776,7 +773,7 @@ void ioat2_free_chan_resources(struct dma_chan *c) tasklet_disable(&chan->cleanup_task); del_timer_sync(&chan->timer); - device->cleanup_tasklet((unsigned long) ioat); + device->cleanup_fn((unsigned long) c); device->reset_hw(chan); spin_lock_bh(&ioat->ring_lock); @@ -809,21 +806,6 @@ void ioat2_free_chan_resources(struct dma_chan *c) ioat->dmacount = 0; } -enum dma_status -ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie, - dma_cookie_t *done, dma_cookie_t *used) -{ - struct ioat2_dma_chan *ioat = to_ioat2_chan(c); - struct ioatdma_device *device = ioat->base.device; - - if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) - return DMA_SUCCESS; - - device->cleanup_tasklet((unsigned long) ioat); - - return ioat_is_complete(c, cookie, done, used); -} - static ssize_t ring_size_show(struct dma_chan *c, char *page) { struct ioat2_dma_chan *ioat = to_ioat2_chan(c); @@ -864,7 +846,7 @@ int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca) device->enumerate_channels = ioat2_enumerate_channels; device->reset_hw = ioat2_reset_hw; - device->cleanup_tasklet = ioat2_cleanup_tasklet; + device->cleanup_fn = ioat2_cleanup_event; device->timer_fn = ioat2_timer_event; device->self_test = ioat_dma_self_test; dma = &device->common; @@ -872,7 +854,7 @@ int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca) dma->device_issue_pending = ioat2_issue_pending; dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; dma->device_free_chan_resources = ioat2_free_chan_resources; - dma->device_is_tx_complete = ioat2_is_complete; + dma->device_is_tx_complete = ioat_is_dma_complete; err = ioat_probe(device); if (err) diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h index d211335b48f8..ef2871fd7868 100644 --- a/drivers/dma/ioat/dma_v2.h +++ b/drivers/dma/ioat/dma_v2.h @@ -176,12 +176,10 @@ ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, void ioat2_issue_pending(struct dma_chan *chan); int ioat2_alloc_chan_resources(struct dma_chan *c); void ioat2_free_chan_resources(struct dma_chan *c); -enum dma_status ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie, - dma_cookie_t *done, dma_cookie_t *used); void __ioat2_restart_chan(struct ioat2_dma_chan *ioat); bool reshape_ring(struct ioat2_dma_chan *ioat, int order); void __ioat2_issue_pending(struct ioat2_dma_chan *ioat); -void ioat2_cleanup_tasklet(unsigned long data); +void ioat2_cleanup_event(unsigned long data); void ioat2_timer_event(unsigned long data); int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo); int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo); diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index 9988f1340186..26febc56dab1 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -358,9 +358,9 @@ static void ioat3_cleanup_sync(struct ioat2_dma_chan *ioat) spin_unlock_bh(&chan->cleanup_lock); } -static void ioat3_cleanup_tasklet(unsigned long data) +static void ioat3_cleanup_event(unsigned long data) { - struct ioat2_dma_chan *ioat = (void *) data; + struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); ioat3_cleanup_sync(ioat); writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); @@ -380,7 +380,7 @@ static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) static void ioat3_timer_event(unsigned long data) { - struct ioat2_dma_chan *ioat = (void *) data; + struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); struct ioat_chan_common *chan = &ioat->base; spin_lock_bh(&chan->cleanup_lock); @@ -1259,11 +1259,11 @@ int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) if (is_raid_device) { dma->device_is_tx_complete = ioat3_is_complete; - device->cleanup_tasklet = ioat3_cleanup_tasklet; + device->cleanup_fn = ioat3_cleanup_event; device->timer_fn = ioat3_timer_event; } else { - dma->device_is_tx_complete = ioat2_is_complete; - device->cleanup_tasklet = ioat2_cleanup_tasklet; + dma->device_is_tx_complete = ioat_is_dma_complete; + device->cleanup_fn = ioat2_cleanup_event; device->timer_fn = ioat2_timer_event; } -- cgit v1.2.3 From 604b2ad7ccb11569d3b843bb1ce0fbe034e70769 Mon Sep 17 00:00:00 2001 From: Amit Shah Date: Wed, 24 Feb 2010 10:36:51 +0530 Subject: virtio: console: Fix type of 'len' as unsigned int We declare 'len' as int type but it should be 'unsigned int', as get_buf() wants it to be. Signed-off-by: Amit Shah Reported-by: Juan Quintela --- drivers/char/virtio_console.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/char/virtio_console.c b/drivers/char/virtio_console.c index 213373b5f17f..2bd6a9c302c8 100644 --- a/drivers/char/virtio_console.c +++ b/drivers/char/virtio_console.c @@ -379,7 +379,7 @@ static ssize_t send_control_msg(struct port *port, unsigned int event, struct scatterlist sg[1]; struct virtio_console_control cpkt; struct virtqueue *vq; - int len; + unsigned int len; if (!use_multiport(port->portdev)) return 0; -- cgit v1.2.3 From 335a64a5c21ed58de21c0130c90c7e647cdcf572 Mon Sep 17 00:00:00 2001 From: Amit Shah Date: Wed, 24 Feb 2010 10:37:44 +0530 Subject: virtio: console: Use better variable names for fill_queue operation We want to keep track of the number of buffers added to a vq. Use nr_added_bufs instead of 'ret'. Also, the users of fill_queue() overloaded a local 'err' variable to check the numbers of buffers allocated. Use nr_added_bufs instead of err. Signed-off-by: Amit Shah Reported-by: Juan Quintela --- drivers/char/virtio_console.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/char/virtio_console.c b/drivers/char/virtio_console.c index 2bd6a9c302c8..f404ccfc9c20 100644 --- a/drivers/char/virtio_console.c +++ b/drivers/char/virtio_console.c @@ -1071,27 +1071,27 @@ static void config_intr(struct virtio_device *vdev) static unsigned int fill_queue(struct virtqueue *vq, spinlock_t *lock) { struct port_buffer *buf; - unsigned int ret; - int err; + unsigned int nr_added_bufs; + int ret; - ret = 0; + nr_added_bufs = 0; do { buf = alloc_buf(PAGE_SIZE); if (!buf) break; spin_lock_irq(lock); - err = add_inbuf(vq, buf); - if (err < 0) { + ret = add_inbuf(vq, buf); + if (ret < 0) { spin_unlock_irq(lock); free_buf(buf); break; } - ret++; + nr_added_bufs++; spin_unlock_irq(lock); - } while (err > 0); + } while (ret > 0); - return ret; + return nr_added_bufs; } static int add_port(struct ports_device *portdev, u32 id) @@ -1100,6 +1100,7 @@ static int add_port(struct ports_device *portdev, u32 id) struct port *port; struct port_buffer *buf; dev_t devt; + unsigned int nr_added_bufs; int err; port = kmalloc(sizeof(*port), GFP_KERNEL); @@ -1144,8 +1145,8 @@ static int add_port(struct ports_device *portdev, u32 id) init_waitqueue_head(&port->waitqueue); /* Fill the in_vq with buffers so the host can send us data. */ - err = fill_queue(port->in_vq, &port->inbuf_lock); - if (!err) { + nr_added_bufs = fill_queue(port->in_vq, &port->inbuf_lock); + if (!nr_added_bufs) { dev_err(port->dev, "Error allocating inbufs\n"); err = -ENOMEM; goto free_device; @@ -1442,12 +1443,14 @@ static int __devinit virtcons_probe(struct virtio_device *vdev) INIT_LIST_HEAD(&portdev->ports); if (multiport) { + unsigned int nr_added_bufs; + spin_lock_init(&portdev->cvq_lock); INIT_WORK(&portdev->control_work, &control_work_handler); INIT_WORK(&portdev->config_work, &config_work_handler); - err = fill_queue(portdev->c_ivq, &portdev->cvq_lock); - if (!err) { + nr_added_bufs = fill_queue(portdev->c_ivq, &portdev->cvq_lock); + if (!nr_added_bufs) { dev_err(&vdev->dev, "Error allocating buffers for control queue\n"); err = -ENOMEM; -- cgit v1.2.3 From 4c020a961a812ffae9846b917304cea504c3a733 Mon Sep 17 00:00:00 2001 From: David Dillow Date: Wed, 3 Mar 2010 16:33:10 +0000 Subject: r8169: use correct barrier between cacheable and non-cacheable memory r8169 needs certain writes to be visible to other CPUs or the NIC before touching the hardware, but was using smp_wmb() which is only required to order cacheable memory access. Switch to wmb() which is required to order both cacheable and non-cacheable memory. Noticed by Catalin Marinas and Paul Mackerras. Signed-off-by: David Dillow Signed-off-by: David S. Miller --- drivers/net/r8169.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index dfc3573c91bb..9d3ebf3e975e 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -4270,7 +4270,7 @@ static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, tp->cur_tx += frags + 1; - smp_wmb(); + wmb(); RTL_W8(TxPoll, NPQ); /* set polling bit */ @@ -4621,7 +4621,7 @@ static int rtl8169_poll(struct napi_struct *napi, int budget) * until it does. */ tp->intr_mask = 0xffff; - smp_wmb(); + wmb(); RTL_W16(IntrMask, tp->intr_event); } -- cgit v1.2.3 From 0eddba525cf4c3a4aab9feaf36b12b465290d4a7 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 3 Mar 2010 08:18:58 +0000 Subject: gianfar: Fix TX ring processing on SMP machines Starting with commit a3bc1f11e9b867a4f49505 ("gianfar: Revive SKB recycling") gianfar driver sooner or later stops transmitting any packets on SMP machines. start_xmit() prepares new skb for transmitting, generally it does three things: 1. sets up all BDs (marks them ready to send), except the first one. 2. stores skb into tx_queue->tx_skbuff so that clean_tx_ring() would cleanup it later. 3. sets up the first BD, i.e. marks it ready. Here is what clean_tx_ring() does: 1. reads skbs from tx_queue->tx_skbuff 2. checks if the *last* BD is ready. If it's still ready [to send] then it it isn't transmitted, so clean_tx_ring() returns. Otherwise it actually cleanups BDs. All is OK. Now, if there is just one BD, code flow: - start_xmit(): stores skb into tx_skbuff. Note that the first BD (which is also the last one) isn't marked as ready, yet. - clean_tx_ring(): sees that skb is not null, *and* its lstatus says that it is NOT ready (like if BD was sent), so it cleans it up (bad!) - start_xmit(): marks BD as ready [to send], but it's too late. We can fix this simply by reordering lstatus/tx_skbuff writes. Reported-by: Martyn Welch Bisected-by: Paul Gortmaker Signed-off-by: Anton Vorontsov Tested-by: Paul Gortmaker Tested-by: Martyn Welch Cc: Sandeep Gopalpet Cc: Stable [2.6.33] Signed-off-by: David S. Miller --- drivers/net/gianfar.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index 6aa526ee9096..c3f061957c04 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c @@ -2021,7 +2021,6 @@ static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) } /* setup the TxBD length and buffer pointer for the first BD */ - tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); @@ -2053,6 +2052,10 @@ static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) txbdp_start->lstatus = lstatus; + eieio(); /* force lstatus write before tx_skbuff */ + + tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; + /* Update the current skb pointer to the next entry we will use * (wrapping if necessary) */ tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & -- cgit v1.2.3 From a6f018e324ba91d0464cca6895447c2b89e6d578 Mon Sep 17 00:00:00 2001 From: Divy Le Ray Date: Wed, 3 Mar 2010 09:49:47 +0000 Subject: cxgb3: fix hot plug removal crash queue restart tasklets need to be stopped after napi handlers are stopped since the latter can restart them. So stop them after stopping napi. Signed-off-by: Divy Le Ray Signed-off-by: David S. Miller --- drivers/net/cxgb3/cxgb3_main.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/net/cxgb3/cxgb3_main.c b/drivers/net/cxgb3/cxgb3_main.c index 6fd968abb073..cecdec1551db 100644 --- a/drivers/net/cxgb3/cxgb3_main.c +++ b/drivers/net/cxgb3/cxgb3_main.c @@ -1280,6 +1280,7 @@ static void cxgb_down(struct adapter *adapter) free_irq_resources(adapter); quiesce_rx(adapter); + t3_sge_stop(adapter); flush_workqueue(cxgb3_wq); /* wait for external IRQ handler */ } -- cgit v1.2.3 From 4c147dd81966bd4ba7f026476237ba67ea72d5d9 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Wed, 3 Mar 2010 17:42:11 -0800 Subject: [SCSI] bfa: Added separate MSI-X module parameters. Added separate MSI-X module parameters to selectively enable / disable MSI-X interrupts for both Brocade HBA and CNA's. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfad_attr.c | 3 +++ drivers/scsi/bfa/bfad_intr.c | 11 ++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfad_attr.c b/drivers/scsi/bfa/bfad_attr.c index 9129ae3040ff..adf801dbfa15 100644 --- a/drivers/scsi/bfa/bfad_attr.c +++ b/drivers/scsi/bfa/bfad_attr.c @@ -229,7 +229,9 @@ bfad_im_get_host_speed(struct Scsi_Host *shost) (struct bfad_im_port_s *) shost->hostdata[0]; struct bfad_s *bfad = im_port->bfad; struct bfa_pport_attr_s attr; + unsigned long flags; + spin_lock_irqsave(shost->host_lock, flags); bfa_pport_get_attr(&bfad->bfa, &attr); switch (attr.speed) { case BFA_PPORT_SPEED_8GBPS: @@ -248,6 +250,7 @@ bfad_im_get_host_speed(struct Scsi_Host *shost) fc_host_speed(shost) = FC_PORTSPEED_UNKNOWN; break; } + spin_unlock_irqrestore(shost->host_lock, flags); } /** diff --git a/drivers/scsi/bfa/bfad_intr.c b/drivers/scsi/bfa/bfad_intr.c index 7de8832f6fee..2b7dbecbebca 100644 --- a/drivers/scsi/bfa/bfad_intr.c +++ b/drivers/scsi/bfa/bfad_intr.c @@ -23,8 +23,10 @@ BFA_TRC_FILE(LDRV, INTR); /** * bfa_isr BFA driver interrupt functions */ -static int msix_disable; -module_param(msix_disable, int, S_IRUGO | S_IWUSR); +static int msix_disable_cb; +static int msix_disable_ct; +module_param(msix_disable_cb, int, S_IRUGO | S_IWUSR); +module_param(msix_disable_ct, int, S_IRUGO | S_IWUSR); /** * Line based interrupt handler. */ @@ -141,6 +143,7 @@ bfad_setup_intr(struct bfad_s *bfad) int error = 0; u32 mask = 0, i, num_bit = 0, max_bit = 0; struct msix_entry msix_entries[MAX_MSIX_ENTRY]; + struct pci_dev *pdev = bfad->pcidev; /* Call BFA to get the msix map for this PCI function. */ bfa_msix_getvecs(&bfad->bfa, &mask, &num_bit, &max_bit); @@ -148,7 +151,9 @@ bfad_setup_intr(struct bfad_s *bfad) /* Set up the msix entry table */ bfad_init_msix_entry(bfad, msix_entries, mask, max_bit); - if (!msix_disable) { + if ((pdev->device == BFA_PCI_DEVICE_ID_CT && !msix_disable_ct) || + (pdev->device != BFA_PCI_DEVICE_ID_CT && !msix_disable_cb)) { + error = pci_enable_msix(bfad->pcidev, msix_entries, bfad->nvec); if (error) { /* -- cgit v1.2.3 From 5c1fb1d55672a74d1c318f67cdddbb599df9a76c Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Wed, 3 Mar 2010 17:42:39 -0800 Subject: [SCSI] bfa: Defined a new LPS event to clear virtual link on a vport Clear virtual links was not propagated upwards to bfa from fw. This resulted in HBA and switch being in an inconsistent state. So defined a new LPS event for clear virtual link on a vport, and also now clear virtual link on a baseport, is sent as a link down event from the fw. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_lps.c | 71 +++++++++++++++++++++++++++++++++- drivers/scsi/bfa/include/bfa_svc.h | 1 + drivers/scsi/bfa/include/bfi/bfi_lps.h | 8 ++++ drivers/scsi/bfa/include/cs/bfa_plog.h | 9 ++++- drivers/scsi/bfa/vport.c | 11 ++++++ 5 files changed, 97 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_lps.c b/drivers/scsi/bfa/bfa_lps.c index 9844b45412b6..c8c2564af725 100644 --- a/drivers/scsi/bfa/bfa_lps.c +++ b/drivers/scsi/bfa/bfa_lps.c @@ -49,7 +49,7 @@ static void bfa_lps_send_login(struct bfa_lps_s *lps); static void bfa_lps_send_logout(struct bfa_lps_s *lps); static void bfa_lps_login_comp(struct bfa_lps_s *lps); static void bfa_lps_logout_comp(struct bfa_lps_s *lps); - +static void bfa_lps_cvl_event(struct bfa_lps_s *lps); /** * lps_pvt BFA LPS private functions @@ -62,6 +62,7 @@ enum bfa_lps_event { BFA_LPS_SM_RESUME = 4, /* space present in reqq queue */ BFA_LPS_SM_DELETE = 5, /* lps delete from user */ BFA_LPS_SM_OFFLINE = 6, /* Link is offline */ + BFA_LPS_SM_RX_CVL = 7, /* Rx clear virtual link */ }; static void bfa_lps_sm_init(struct bfa_lps_s *lps, enum bfa_lps_event event); @@ -101,6 +102,7 @@ bfa_lps_sm_init(struct bfa_lps_s *lps, enum bfa_lps_event event) bfa_lps_free(lps); break; + case BFA_LPS_SM_RX_CVL: case BFA_LPS_SM_OFFLINE: break; @@ -162,6 +164,14 @@ bfa_lps_sm_loginwait(struct bfa_lps_s *lps, enum bfa_lps_event event) bfa_reqq_wcancel(&lps->wqe); break; + case BFA_LPS_SM_RX_CVL: + /* + * Login was not even sent out; so when getting out + * of this state, it will appear like a login retry + * after Clear virtual link + */ + break; + default: bfa_assert(0); } @@ -187,6 +197,15 @@ bfa_lps_sm_online(struct bfa_lps_s *lps, enum bfa_lps_event event) } break; + case BFA_LPS_SM_RX_CVL: + bfa_sm_set_state(lps, bfa_lps_sm_init); + + /* Let the vport module know about this event */ + bfa_lps_cvl_event(lps); + bfa_plog_str(lps->bfa->plog, BFA_PL_MID_LPS, + BFA_PL_EID_FIP_FCF_CVL, 0, "FCF Clear Virt. Link Rx"); + break; + case BFA_LPS_SM_OFFLINE: case BFA_LPS_SM_DELETE: bfa_sm_set_state(lps, bfa_lps_sm_init); @@ -395,6 +414,20 @@ bfa_lps_logout_rsp(struct bfa_s *bfa, struct bfi_lps_logout_rsp_s *rsp) bfa_sm_send_event(lps, BFA_LPS_SM_FWRSP); } +/** + * Firmware received a Clear virtual link request (for FCoE) + */ +static void +bfa_lps_rx_cvl_event(struct bfa_s *bfa, struct bfi_lps_cvl_event_s *cvl) +{ + struct bfa_lps_mod_s *mod = BFA_LPS_MOD(bfa); + struct bfa_lps_s *lps; + + lps = BFA_LPS_FROM_TAG(mod, cvl->lp_tag); + + bfa_sm_send_event(lps, BFA_LPS_SM_RX_CVL); +} + /** * Space is available in request queue, resume queueing request to firmware. */ @@ -531,7 +564,39 @@ bfa_lps_logout_comp(struct bfa_lps_s *lps) bfa_cb_lps_flogo_comp(lps->bfa->bfad, lps->uarg); } +/** + * Clear virtual link completion handler for non-fcs + */ +static void +bfa_lps_cvl_event_cb(void *arg, bfa_boolean_t complete) +{ + struct bfa_lps_s *lps = arg; + + if (!complete) + return; + + /* Clear virtual link to base port will result in link down */ + if (lps->fdisc) + bfa_cb_lps_cvl_event(lps->bfa->bfad, lps->uarg); +} + +/** + * Received Clear virtual link event --direct call for fcs, + * queue for others + */ +static void +bfa_lps_cvl_event(struct bfa_lps_s *lps) +{ + if (!lps->bfa->fcs) { + bfa_cb_queue(lps->bfa, &lps->hcb_qe, bfa_lps_cvl_event_cb, + lps); + return; + } + /* Clear virtual link to base port will result in link down */ + if (lps->fdisc) + bfa_cb_lps_cvl_event(lps->bfa->bfad, lps->uarg); +} /** * lps_public BFA LPS public functions @@ -773,6 +838,10 @@ bfa_lps_isr(struct bfa_s *bfa, struct bfi_msg_s *m) bfa_lps_logout_rsp(bfa, msg.logout_rsp); break; + case BFI_LPS_H2I_CVL_EVENT: + bfa_lps_rx_cvl_event(bfa, msg.cvl_event); + break; + default: bfa_trc(bfa, m->mhdr.msg_id); bfa_assert(0); diff --git a/drivers/scsi/bfa/include/bfa_svc.h b/drivers/scsi/bfa/include/bfa_svc.h index 268d956bad89..2e4372f66b8b 100644 --- a/drivers/scsi/bfa/include/bfa_svc.h +++ b/drivers/scsi/bfa/include/bfa_svc.h @@ -319,6 +319,7 @@ void bfa_cb_lps_flogi_comp(void *bfad, void *uarg, bfa_status_t status); void bfa_cb_lps_flogo_comp(void *bfad, void *uarg); void bfa_cb_lps_fdisc_comp(void *bfad, void *uarg, bfa_status_t status); void bfa_cb_lps_fdisclogo_comp(void *bfad, void *uarg); +void bfa_cb_lps_cvl_event(void *bfad, void *uarg); #endif /* __BFA_SVC_H__ */ diff --git a/drivers/scsi/bfa/include/bfi/bfi_lps.h b/drivers/scsi/bfa/include/bfi/bfi_lps.h index c59d47badb4b..7ed31bbb8696 100644 --- a/drivers/scsi/bfa/include/bfi/bfi_lps.h +++ b/drivers/scsi/bfa/include/bfi/bfi_lps.h @@ -30,6 +30,7 @@ enum bfi_lps_h2i_msgs { enum bfi_lps_i2h_msgs { BFI_LPS_H2I_LOGIN_RSP = BFA_I2HM(1), BFI_LPS_H2I_LOGOUT_RSP = BFA_I2HM(2), + BFI_LPS_H2I_CVL_EVENT = BFA_I2HM(3), }; struct bfi_lps_login_req_s { @@ -77,6 +78,12 @@ struct bfi_lps_logout_rsp_s { u8 rsvd[2]; }; +struct bfi_lps_cvl_event_s { + struct bfi_mhdr_s mh; /* common msg header */ + u8 lp_tag; + u8 rsvd[3]; +}; + union bfi_lps_h2i_msg_u { struct bfi_mhdr_s *msg; struct bfi_lps_login_req_s *login_req; @@ -87,6 +94,7 @@ union bfi_lps_i2h_msg_u { struct bfi_msg_s *msg; struct bfi_lps_login_rsp_s *login_rsp; struct bfi_lps_logout_rsp_s *logout_rsp; + struct bfi_lps_cvl_event_s *cvl_event; }; #pragma pack() diff --git a/drivers/scsi/bfa/include/cs/bfa_plog.h b/drivers/scsi/bfa/include/cs/bfa_plog.h index 670f86e5fc6e..f5bef63b5877 100644 --- a/drivers/scsi/bfa/include/cs/bfa_plog.h +++ b/drivers/scsi/bfa/include/cs/bfa_plog.h @@ -80,7 +80,8 @@ enum bfa_plog_mid { BFA_PL_MID_HAL_FCXP = 4, BFA_PL_MID_HAL_UF = 5, BFA_PL_MID_FCS = 6, - BFA_PL_MID_MAX = 7 + BFA_PL_MID_LPS = 7, + BFA_PL_MID_MAX = 8 }; #define BFA_PL_MID_STRLEN 8 @@ -118,7 +119,11 @@ enum bfa_plog_eid { BFA_PL_EID_RSCN = 17, BFA_PL_EID_DEBUG = 18, BFA_PL_EID_MISC = 19, - BFA_PL_EID_MAX = 20 + BFA_PL_EID_FIP_FCF_DISC = 20, + BFA_PL_EID_FIP_FCF_CVL = 21, + BFA_PL_EID_LOGIN = 22, + BFA_PL_EID_LOGO = 23, + BFA_PL_EID_MAX = 24 }; #define BFA_PL_ENAME_STRLEN 8 diff --git a/drivers/scsi/bfa/vport.c b/drivers/scsi/bfa/vport.c index e90f1e38c32d..8d18589e1da2 100644 --- a/drivers/scsi/bfa/vport.c +++ b/drivers/scsi/bfa/vport.c @@ -888,4 +888,15 @@ bfa_cb_lps_fdisclogo_comp(void *bfad, void *uarg) bfa_sm_send_event(vport, BFA_FCS_VPORT_SM_RSP_OK); } +/** + * Received clear virtual link + */ +void +bfa_cb_lps_cvl_event(void *bfad, void *uarg) +{ + struct bfa_fcs_vport_s *vport = uarg; + /* Send an Offline followed by an ONLINE */ + bfa_sm_send_event(vport, BFA_FCS_VPORT_SM_OFFLINE); + bfa_sm_send_event(vport, BFA_FCS_VPORT_SM_ONLINE); +} -- cgit v1.2.3 From 2f9b8857a914b71ba1b84fb23a0a20a87de41c91 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Wed, 3 Mar 2010 17:42:51 -0800 Subject: [SCSI] bfa: Enable IOC auto-recovery and IOC type fix. bfa_ioc.c: - Enable IOC auto-recovery by default. - When CNA is in FC mode, return IOC type as FC (not FCoE) bfa_iocfc.c: - Set fcmode before pci initialization/setup. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_ioc.c | 6 +++--- drivers/scsi/bfa/bfa_iocfc.c | 5 +++-- 2 files changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_ioc.c b/drivers/scsi/bfa/bfa_ioc.c index 397d7e9eade5..569b35d19a25 100644 --- a/drivers/scsi/bfa/bfa_ioc.c +++ b/drivers/scsi/bfa/bfa_ioc.c @@ -56,7 +56,7 @@ BFA_TRC_FILE(HAL, IOC); #define BFA_FLASH_CHUNK_NO(off) (off / BFI_FLASH_CHUNK_SZ_WORDS) #define BFA_FLASH_OFFSET_IN_CHUNK(off) (off % BFI_FLASH_CHUNK_SZ_WORDS) #define BFA_FLASH_CHUNK_ADDR(chunkno) (chunkno * BFI_FLASH_CHUNK_SZ_WORDS) -bfa_boolean_t bfa_auto_recover = BFA_FALSE; +bfa_boolean_t bfa_auto_recover = BFA_TRUE; /* * forward declarations @@ -1642,7 +1642,7 @@ bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type, u32 boot_param) void bfa_ioc_auto_recover(bfa_boolean_t auto_recover) { - bfa_auto_recover = BFA_FALSE; + bfa_auto_recover = auto_recover; } @@ -2082,7 +2082,7 @@ bfa_ioc_get_attr(struct bfa_ioc_s *ioc, struct bfa_ioc_attr_s *ioc_attr) ioc_attr->state = bfa_sm_to_state(ioc_sm_table, ioc->fsm); ioc_attr->port_id = ioc->port_id; - if (!ioc->ctdev) + if (!ioc->ctdev || ioc->fcmode) ioc_attr->ioc_type = BFA_IOC_TYPE_FC; else if (ioc->ioc_mc == BFI_MC_IOCFC) ioc_attr->ioc_type = BFA_IOC_TYPE_FCoE; diff --git a/drivers/scsi/bfa/bfa_iocfc.c b/drivers/scsi/bfa/bfa_iocfc.c index d7ab792a9e54..b5e7224bda4a 100644 --- a/drivers/scsi/bfa/bfa_iocfc.c +++ b/drivers/scsi/bfa/bfa_iocfc.c @@ -619,8 +619,6 @@ bfa_iocfc_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, bfa_ioc_attach(&bfa->ioc, bfa, &bfa_iocfc_cbfn, &bfa->timer_mod, bfa->trcmod, bfa->aen, bfa->logm); - bfa_ioc_pci_init(&bfa->ioc, pcidev, BFI_MC_IOCFC); - bfa_ioc_mbox_register(&bfa->ioc, bfa_mbox_isrs); /** * Choose FC (ssid: 0x1C) v/s FCoE (ssid: 0x14) mode. @@ -628,6 +626,9 @@ bfa_iocfc_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, if (0) bfa_ioc_set_fcmode(&bfa->ioc); + bfa_ioc_pci_init(&bfa->ioc, pcidev, BFI_MC_IOCFC); + bfa_ioc_mbox_register(&bfa->ioc, bfa_mbox_isrs); + bfa_iocfc_init_mem(bfa, bfad, cfg, pcidev); bfa_iocfc_mem_claim(bfa, cfg, meminfo); bfa_timer_init(&bfa->timer_mod); -- cgit v1.2.3 From ab5336189a12b6561a1b5708d782a4e27e2e3b79 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Wed, 3 Mar 2010 17:43:09 -0800 Subject: [SCSI] bfa: Enable new halt interrupt in BFA. bfa_intr.c: Enable new halt interrupt in BFA. bfi_ctreg.h: Expose new halt interrupt bit definition to host. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_intr.c | 7 ++++--- drivers/scsi/bfa/include/bfi/bfi_ctreg.h | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_intr.c b/drivers/scsi/bfa/bfa_intr.c index b36540e4ed76..ab463db11144 100644 --- a/drivers/scsi/bfa/bfa_intr.c +++ b/drivers/scsi/bfa/bfa_intr.c @@ -15,7 +15,7 @@ * General Public License for more details. */ #include -#include +#include #include #include #include @@ -96,7 +96,8 @@ bfa_isr_enable(struct bfa_s *bfa) bfa_msix_install(bfa); intr_unmask = (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | - __HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS); + __HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS | + __HFN_INT_LL_HALT); if (pci_func == 0) intr_unmask |= (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | @@ -205,7 +206,7 @@ bfa_msix_lpu_err(struct bfa_s *bfa, int vec) if (intr & (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | __HFN_INT_ERR_LPU1 | - __HFN_INT_ERR_PSS)) + __HFN_INT_ERR_PSS | __HFN_INT_LL_HALT)) bfa_msix_errint(bfa, intr); } diff --git a/drivers/scsi/bfa/include/bfi/bfi_ctreg.h b/drivers/scsi/bfa/include/bfi/bfi_ctreg.h index d3caa58c0a0a..dd2992c38afb 100644 --- a/drivers/scsi/bfa/include/bfi/bfi_ctreg.h +++ b/drivers/scsi/bfa/include/bfi/bfi_ctreg.h @@ -589,6 +589,7 @@ enum { #define __HFN_INT_MBOX_LPU1 0x00200000U #define __HFN_INT_MBOX1_LPU0 0x00400000U #define __HFN_INT_MBOX1_LPU1 0x00800000U +#define __HFN_INT_LL_HALT 0x01000000U #define __HFN_INT_CPE_MASK 0x000000ffU #define __HFN_INT_RME_MASK 0x0000ff00U -- cgit v1.2.3 From 5b098082e22c168b7df4c5c3cd924047cee7d995 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Wed, 3 Mar 2010 17:43:19 -0800 Subject: [SCSI] bfa: Changes to support FDMI Driver Parameter Added a FCS function to be called during driver init, to set the FDMI Driver parameter. fdmi.c: Created a disabled state when fdmi is disabled. bfad.c: * Added fdmi_enable driver parameter. * Added support to call bfa_fcs_set_fdmi_param() to initialize fcs fdmi setting. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_fcs.c | 17 +++++++++++++++++ drivers/scsi/bfa/bfad.c | 3 +++ drivers/scsi/bfa/fdmi.c | 22 +++++++++++++++++++++- drivers/scsi/bfa/include/fcs/bfa_fcs.h | 2 ++ 4 files changed, 43 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_fcs.c b/drivers/scsi/bfa/bfa_fcs.c index 7cb39a306ea9..50120c285fff 100644 --- a/drivers/scsi/bfa/bfa_fcs.c +++ b/drivers/scsi/bfa/bfa_fcs.c @@ -126,6 +126,23 @@ bfa_fcs_driver_info_init(struct bfa_fcs_s *fcs, bfa_fcs_fabric_psymb_init(&fcs->fabric); } +/** + * @brief + * FCS FDMI Driver Parameter Initialization + * + * @param[in] fcs FCS instance + * @param[in] fdmi_enable TRUE/FALSE + * + * @return None + */ +void +bfa_fcs_set_fdmi_param(struct bfa_fcs_s *fcs, bfa_boolean_t fdmi_enable) +{ + + fcs->fdmi_enabled = fdmi_enable; + +} + /** * FCS instance cleanup and exit. * diff --git a/drivers/scsi/bfa/bfad.c b/drivers/scsi/bfa/bfad.c index b52b773d49d9..8e2b2a26cb74 100644 --- a/drivers/scsi/bfa/bfad.c +++ b/drivers/scsi/bfa/bfad.c @@ -53,6 +53,7 @@ static int log_level = BFA_LOG_WARNING; static int ioc_auto_recover = BFA_TRUE; static int ipfc_enable = BFA_FALSE; static int ipfc_mtu = -1; +static int fdmi_enable = BFA_TRUE; int bfa_lun_queue_depth = BFAD_LUN_QUEUE_DEPTH; int bfa_linkup_delay = -1; @@ -74,6 +75,7 @@ module_param(log_level, int, S_IRUGO | S_IWUSR); module_param(ioc_auto_recover, int, S_IRUGO | S_IWUSR); module_param(ipfc_enable, int, S_IRUGO | S_IWUSR); module_param(ipfc_mtu, int, S_IRUGO | S_IWUSR); +module_param(fdmi_enable, int, S_IRUGO | S_IWUSR); module_param(bfa_linkup_delay, int, S_IRUGO | S_IWUSR); /* @@ -748,6 +750,7 @@ bfad_drv_init(struct bfad_s *bfad) bfa_fcs_aen_init(&bfad->bfa_fcs, bfad->aen); bfa_fcs_init(&bfad->bfa_fcs, &bfad->bfa, bfad, BFA_FALSE); bfa_fcs_driver_info_init(&bfad->bfa_fcs, &driver_info); + bfa_fcs_set_fdmi_param(&bfad->bfa_fcs, fdmi_enable); spin_unlock_irqrestore(&bfad->bfad_lock, flags); bfad->bfad_flags |= BFAD_DRV_INIT_DONE; diff --git a/drivers/scsi/bfa/fdmi.c b/drivers/scsi/bfa/fdmi.c index df2a1e54e16b..d76d9220b6e6 100644 --- a/drivers/scsi/bfa/fdmi.c +++ b/drivers/scsi/bfa/fdmi.c @@ -116,6 +116,9 @@ static void bfa_fcs_port_fdmi_sm_rpa_retry(struct bfa_fcs_port_fdmi_s *fdmi, enum port_fdmi_event event); static void bfa_fcs_port_fdmi_sm_online(struct bfa_fcs_port_fdmi_s *fdmi, enum port_fdmi_event event); +static void bfa_fcs_port_fdmi_sm_disabled(struct bfa_fcs_port_fdmi_s *fdmi, + enum port_fdmi_event event); + /** * Start in offline state - awaiting MS to send start. */ @@ -479,6 +482,20 @@ bfa_fcs_port_fdmi_sm_online(struct bfa_fcs_port_fdmi_s *fdmi, } } +/** + * FDMI is disabled state. + */ +static void +bfa_fcs_port_fdmi_sm_disabled(struct bfa_fcs_port_fdmi_s *fdmi, + enum port_fdmi_event event) +{ + struct bfa_fcs_port_s *port = fdmi->ms->port; + + bfa_trc(port->fcs, port->port_cfg.pwwn); + bfa_trc(port->fcs, event); + + /* No op State. It can only be enabled at Driver Init. */ +} /** * RHBA : Register HBA Attributes. @@ -1201,7 +1218,10 @@ bfa_fcs_port_fdmi_init(struct bfa_fcs_port_ms_s *ms) struct bfa_fcs_port_fdmi_s *fdmi = &ms->fdmi; fdmi->ms = ms; - bfa_sm_set_state(fdmi, bfa_fcs_port_fdmi_sm_offline); + if (ms->port->fcs->fdmi_enabled) + bfa_sm_set_state(fdmi, bfa_fcs_port_fdmi_sm_offline); + else + bfa_sm_set_state(fdmi, bfa_fcs_port_fdmi_sm_disabled); } void diff --git a/drivers/scsi/bfa/include/fcs/bfa_fcs.h b/drivers/scsi/bfa/include/fcs/bfa_fcs.h index 627669c65546..0396ec460532 100644 --- a/drivers/scsi/bfa/include/fcs/bfa_fcs.h +++ b/drivers/scsi/bfa/include/fcs/bfa_fcs.h @@ -49,6 +49,7 @@ struct bfa_fcs_s { struct bfa_trc_mod_s *trcmod; /* tracing module */ struct bfa_aen_s *aen; /* aen component */ bfa_boolean_t vf_enabled; /* VF mode is enabled */ + bfa_boolean_t fdmi_enabled; /*!< FDMI is enabled */ bfa_boolean_t min_cfg; /* min cfg enabled/disabled */ u16 port_vfid; /* port default VF ID */ struct bfa_fcs_driver_info_s driver_info; @@ -64,6 +65,7 @@ void bfa_fcs_init(struct bfa_fcs_s *fcs, struct bfa_s *bfa, struct bfad_s *bfad, bfa_boolean_t min_cfg); void bfa_fcs_driver_info_init(struct bfa_fcs_s *fcs, struct bfa_fcs_driver_info_s *driver_info); +void bfa_fcs_set_fdmi_param(struct bfa_fcs_s *fcs, bfa_boolean_t fdmi_enable); void bfa_fcs_exit(struct bfa_fcs_s *fcs); void bfa_fcs_trc_init(struct bfa_fcs_s *fcs, struct bfa_trc_mod_s *trcmod); void bfa_fcs_log_init(struct bfa_fcs_s *fcs, struct bfa_log_mod_s *logmod); -- cgit v1.2.3 From 82794a2e4153657d12a0c29272e40b47eaadb748 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Wed, 3 Mar 2010 17:43:30 -0800 Subject: [SCSI] bfa: New interface to handle firmware upgrade scenario Split bfa_fcs_init() into bfa_fcs_attach() and bfa_fcs_init(). Removed empty function definitions in FCS modules Modified driver to call bfa_fcs_attach() and bfa_fcs_init() as needed. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_fcs.c | 46 +++++++++++++++++++++------------- drivers/scsi/bfa/bfa_fcs_port.c | 11 ++------ drivers/scsi/bfa/bfa_fcs_uf.c | 8 +----- drivers/scsi/bfa/bfad.c | 3 ++- drivers/scsi/bfa/fabric.c | 11 +++++--- drivers/scsi/bfa/fcpim.c | 19 -------------- drivers/scsi/bfa/fcs_fabric.h | 1 + drivers/scsi/bfa/fcs_fcpim.h | 5 ---- drivers/scsi/bfa/fcs_port.h | 3 +-- drivers/scsi/bfa/fcs_rport.h | 3 --- drivers/scsi/bfa/fcs_uf.h | 3 +-- drivers/scsi/bfa/fcs_vport.h | 7 ------ drivers/scsi/bfa/include/fcs/bfa_fcs.h | 3 ++- drivers/scsi/bfa/rport.c | 17 ------------- drivers/scsi/bfa/vport.c | 17 ------------- 15 files changed, 47 insertions(+), 110 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_fcs.c b/drivers/scsi/bfa/bfa_fcs.c index 50120c285fff..3516172c597c 100644 --- a/drivers/scsi/bfa/bfa_fcs.c +++ b/drivers/scsi/bfa/bfa_fcs.c @@ -36,6 +36,7 @@ * FCS sub-modules */ struct bfa_fcs_mod_s { + void (*attach) (struct bfa_fcs_s *fcs); void (*modinit) (struct bfa_fcs_s *fcs); void (*modexit) (struct bfa_fcs_s *fcs); }; @@ -43,12 +44,10 @@ struct bfa_fcs_mod_s { #define BFA_FCS_MODULE(_mod) { _mod ## _modinit, _mod ## _modexit } static struct bfa_fcs_mod_s fcs_modules[] = { - BFA_FCS_MODULE(bfa_fcs_pport), - BFA_FCS_MODULE(bfa_fcs_uf), - BFA_FCS_MODULE(bfa_fcs_fabric), - BFA_FCS_MODULE(bfa_fcs_vport), - BFA_FCS_MODULE(bfa_fcs_rport), - BFA_FCS_MODULE(bfa_fcs_fcpim), + { bfa_fcs_pport_attach, NULL, NULL }, + { bfa_fcs_uf_attach, NULL, NULL }, + { bfa_fcs_fabric_attach, bfa_fcs_fabric_modinit, + bfa_fcs_fabric_modexit }, }; /** @@ -71,16 +70,10 @@ bfa_fcs_exit_comp(void *fcs_cbarg) */ /** - * FCS instance initialization. - * - * param[in] fcs FCS instance - * param[in] bfa BFA instance - * param[in] bfad BFA driver instance - * - * return None + * fcs attach -- called once to initialize data structures at driver attach time */ void -bfa_fcs_init(struct bfa_fcs_s *fcs, struct bfa_s *bfa, struct bfad_s *bfad, +bfa_fcs_attach(struct bfa_fcs_s *fcs, struct bfa_s *bfa, struct bfad_s *bfad, bfa_boolean_t min_cfg) { int i; @@ -95,7 +88,24 @@ bfa_fcs_init(struct bfa_fcs_s *fcs, struct bfa_s *bfa, struct bfad_s *bfad, for (i = 0; i < sizeof(fcs_modules) / sizeof(fcs_modules[0]); i++) { mod = &fcs_modules[i]; - mod->modinit(fcs); + if (mod->attach) + mod->attach(fcs); + } +} + +/** + * fcs initialization, called once after bfa initialization is complete + */ +void +bfa_fcs_init(struct bfa_fcs_s *fcs) +{ + int i; + struct bfa_fcs_mod_s *mod; + + for (i = 0; i < sizeof(fcs_modules) / sizeof(fcs_modules[0]); i++) { + mod = &fcs_modules[i]; + if (mod->modinit) + mod->modinit(fcs); } } @@ -160,10 +170,12 @@ bfa_fcs_exit(struct bfa_fcs_s *fcs) nmods = sizeof(fcs_modules) / sizeof(fcs_modules[0]); for (i = 0; i < nmods; i++) { - bfa_wc_up(&fcs->wc); mod = &fcs_modules[i]; - mod->modexit(fcs); + if (mod->modexit) { + bfa_wc_up(&fcs->wc); + mod->modexit(fcs); + } } bfa_wc_wait(&fcs->wc); diff --git a/drivers/scsi/bfa/bfa_fcs_port.c b/drivers/scsi/bfa/bfa_fcs_port.c index 9c4b24e62de1..53808d0418a1 100644 --- a/drivers/scsi/bfa/bfa_fcs_port.c +++ b/drivers/scsi/bfa/bfa_fcs_port.c @@ -55,14 +55,7 @@ bfa_fcs_pport_event_handler(void *cbarg, bfa_pport_event_t event) } void -bfa_fcs_pport_modinit(struct bfa_fcs_s *fcs) +bfa_fcs_pport_attach(struct bfa_fcs_s *fcs) { - bfa_pport_event_register(fcs->bfa, bfa_fcs_pport_event_handler, - fcs); -} - -void -bfa_fcs_pport_modexit(struct bfa_fcs_s *fcs) -{ - bfa_fcs_modexit_comp(fcs); + bfa_pport_event_register(fcs->bfa, bfa_fcs_pport_event_handler, fcs); } diff --git a/drivers/scsi/bfa/bfa_fcs_uf.c b/drivers/scsi/bfa/bfa_fcs_uf.c index ad01db6444b2..3d57d48bbae4 100644 --- a/drivers/scsi/bfa/bfa_fcs_uf.c +++ b/drivers/scsi/bfa/bfa_fcs_uf.c @@ -93,13 +93,7 @@ bfa_fcs_uf_recv(void *cbarg, struct bfa_uf_s *uf) } void -bfa_fcs_uf_modinit(struct bfa_fcs_s *fcs) +bfa_fcs_uf_attach(struct bfa_fcs_s *fcs) { bfa_uf_recv_register(fcs->bfa, bfa_fcs_uf_recv, fcs); } - -void -bfa_fcs_uf_modexit(struct bfa_fcs_s *fcs) -{ - bfa_fcs_modexit_comp(fcs); -} diff --git a/drivers/scsi/bfa/bfad.c b/drivers/scsi/bfa/bfad.c index 8e2b2a26cb74..965dfb575e5a 100644 --- a/drivers/scsi/bfa/bfad.c +++ b/drivers/scsi/bfa/bfad.c @@ -748,7 +748,8 @@ bfad_drv_init(struct bfad_s *bfad) bfa_fcs_log_init(&bfad->bfa_fcs, bfad->logmod); bfa_fcs_trc_init(&bfad->bfa_fcs, bfad->trcmod); bfa_fcs_aen_init(&bfad->bfa_fcs, bfad->aen); - bfa_fcs_init(&bfad->bfa_fcs, &bfad->bfa, bfad, BFA_FALSE); + bfa_fcs_attach(&bfad->bfa_fcs, &bfad->bfa, bfad, BFA_FALSE); + bfa_fcs_init(&bfad->bfa_fcs); bfa_fcs_driver_info_init(&bfad->bfa_fcs, &driver_info); bfa_fcs_set_fdmi_param(&bfad->bfa_fcs, fdmi_enable); spin_unlock_irqrestore(&bfad->bfad_lock, flags); diff --git a/drivers/scsi/bfa/fabric.c b/drivers/scsi/bfa/fabric.c index a4b5dd449573..e22989886646 100644 --- a/drivers/scsi/bfa/fabric.c +++ b/drivers/scsi/bfa/fabric.c @@ -814,10 +814,10 @@ bfa_fcs_fabric_delete_comp(void *cbarg) */ /** - * Module initialization + * Attach time initialization */ void -bfa_fcs_fabric_modinit(struct bfa_fcs_s *fcs) +bfa_fcs_fabric_attach(struct bfa_fcs_s *fcs) { struct bfa_fcs_fabric_s *fabric; @@ -841,7 +841,12 @@ bfa_fcs_fabric_modinit(struct bfa_fcs_s *fcs) bfa_wc_up(&fabric->wc); /* For the base port */ bfa_sm_set_state(fabric, bfa_fcs_fabric_sm_uninit); - bfa_sm_send_event(fabric, BFA_FCS_FABRIC_SM_CREATE); +} + +void +bfa_fcs_fabric_modinit(struct bfa_fcs_s *fcs) +{ + bfa_sm_send_event(&fcs->fabric, BFA_FCS_FABRIC_SM_CREATE); bfa_trc(fcs, 0); } diff --git a/drivers/scsi/bfa/fcpim.c b/drivers/scsi/bfa/fcpim.c index 1f3c06efaa9e..06f8a46d1977 100644 --- a/drivers/scsi/bfa/fcpim.c +++ b/drivers/scsi/bfa/fcpim.c @@ -822,22 +822,3 @@ void bfa_fcs_itnim_resume(struct bfa_fcs_itnim_s *itnim) { } - -/** - * Module initialization - */ -void -bfa_fcs_fcpim_modinit(struct bfa_fcs_s *fcs) -{ -} - -/** - * Module cleanup - */ -void -bfa_fcs_fcpim_modexit(struct bfa_fcs_s *fcs) -{ - bfa_fcs_modexit_comp(fcs); -} - - diff --git a/drivers/scsi/bfa/fcs_fabric.h b/drivers/scsi/bfa/fcs_fabric.h index eee960820f86..8237bd5e7217 100644 --- a/drivers/scsi/bfa/fcs_fabric.h +++ b/drivers/scsi/bfa/fcs_fabric.h @@ -29,6 +29,7 @@ /* * fcs friend functions: only between fcs modules */ +void bfa_fcs_fabric_attach(struct bfa_fcs_s *fcs); void bfa_fcs_fabric_modinit(struct bfa_fcs_s *fcs); void bfa_fcs_fabric_modexit(struct bfa_fcs_s *fcs); void bfa_fcs_fabric_modsusp(struct bfa_fcs_s *fcs); diff --git a/drivers/scsi/bfa/fcs_fcpim.h b/drivers/scsi/bfa/fcs_fcpim.h index 61e9e2687de3..11e6e7bce9f6 100644 --- a/drivers/scsi/bfa/fcs_fcpim.h +++ b/drivers/scsi/bfa/fcs_fcpim.h @@ -34,11 +34,6 @@ void bfa_fcs_itnim_is_initiator(struct bfa_fcs_itnim_s *itnim); void bfa_fcs_itnim_pause(struct bfa_fcs_itnim_s *itnim); void bfa_fcs_itnim_resume(struct bfa_fcs_itnim_s *itnim); -/* - * Modudle init/cleanup routines. - */ -void bfa_fcs_fcpim_modinit(struct bfa_fcs_s *fcs); -void bfa_fcs_fcpim_modexit(struct bfa_fcs_s *fcs); void bfa_fcs_fcpim_uf_recv(struct bfa_fcs_itnim_s *itnim, struct fchs_s *fchs, u16 len); #endif /* __FCS_FCPIM_H__ */ diff --git a/drivers/scsi/bfa/fcs_port.h b/drivers/scsi/bfa/fcs_port.h index abb65191dd27..408c06a7d164 100644 --- a/drivers/scsi/bfa/fcs_port.h +++ b/drivers/scsi/bfa/fcs_port.h @@ -26,7 +26,6 @@ /* * fcs friend functions: only between fcs modules */ -void bfa_fcs_pport_modinit(struct bfa_fcs_s *fcs); -void bfa_fcs_pport_modexit(struct bfa_fcs_s *fcs); +void bfa_fcs_pport_attach(struct bfa_fcs_s *fcs); #endif /* __FCS_PPORT_H__ */ diff --git a/drivers/scsi/bfa/fcs_rport.h b/drivers/scsi/bfa/fcs_rport.h index f601e9d74236..9c8d1d292380 100644 --- a/drivers/scsi/bfa/fcs_rport.h +++ b/drivers/scsi/bfa/fcs_rport.h @@ -24,9 +24,6 @@ #include -void bfa_fcs_rport_modinit(struct bfa_fcs_s *fcs); -void bfa_fcs_rport_modexit(struct bfa_fcs_s *fcs); - void bfa_fcs_rport_uf_recv(struct bfa_fcs_rport_s *rport, struct fchs_s *fchs, u16 len); void bfa_fcs_rport_scn(struct bfa_fcs_rport_s *rport); diff --git a/drivers/scsi/bfa/fcs_uf.h b/drivers/scsi/bfa/fcs_uf.h index 96f1bdcb31ed..f591072214fe 100644 --- a/drivers/scsi/bfa/fcs_uf.h +++ b/drivers/scsi/bfa/fcs_uf.h @@ -26,7 +26,6 @@ /* * fcs friend functions: only between fcs modules */ -void bfa_fcs_uf_modinit(struct bfa_fcs_s *fcs); -void bfa_fcs_uf_modexit(struct bfa_fcs_s *fcs); +void bfa_fcs_uf_attach(struct bfa_fcs_s *fcs); #endif /* __FCS_UF_H__ */ diff --git a/drivers/scsi/bfa/fcs_vport.h b/drivers/scsi/bfa/fcs_vport.h index 9e80b6a97b7f..32565ba666eb 100644 --- a/drivers/scsi/bfa/fcs_vport.h +++ b/drivers/scsi/bfa/fcs_vport.h @@ -22,13 +22,6 @@ #include #include -/* - * Modudle init/cleanup routines. - */ - -void bfa_fcs_vport_modinit(struct bfa_fcs_s *fcs); -void bfa_fcs_vport_modexit(struct bfa_fcs_s *fcs); - void bfa_fcs_vport_cleanup(struct bfa_fcs_vport_s *vport); void bfa_fcs_vport_online(struct bfa_fcs_vport_s *vport); void bfa_fcs_vport_offline(struct bfa_fcs_vport_s *vport); diff --git a/drivers/scsi/bfa/include/fcs/bfa_fcs.h b/drivers/scsi/bfa/include/fcs/bfa_fcs.h index 0396ec460532..f2fd35fdee28 100644 --- a/drivers/scsi/bfa/include/fcs/bfa_fcs.h +++ b/drivers/scsi/bfa/include/fcs/bfa_fcs.h @@ -61,8 +61,9 @@ struct bfa_fcs_s { /* * bfa fcs API functions */ -void bfa_fcs_init(struct bfa_fcs_s *fcs, struct bfa_s *bfa, struct bfad_s *bfad, +void bfa_fcs_attach(struct bfa_fcs_s *fcs, struct bfa_s *bfa, struct bfad_s *bfad, bfa_boolean_t min_cfg); +void bfa_fcs_init(struct bfa_fcs_s *fcs); void bfa_fcs_driver_info_init(struct bfa_fcs_s *fcs, struct bfa_fcs_driver_info_s *driver_info); void bfa_fcs_set_fdmi_param(struct bfa_fcs_s *fcs, bfa_boolean_t fdmi_enable); diff --git a/drivers/scsi/bfa/rport.c b/drivers/scsi/bfa/rport.c index 9cf58bb138dc..df714dcdf031 100644 --- a/drivers/scsi/bfa/rport.c +++ b/drivers/scsi/bfa/rport.c @@ -2574,23 +2574,6 @@ bfa_fcs_rport_send_ls_rjt(struct bfa_fcs_rport_s *rport, struct fchs_s *rx_fchs, FC_CLASS_3, len, &fchs, NULL, NULL, FC_MAX_PDUSZ, 0); } -/** - * Module initialization - */ -void -bfa_fcs_rport_modinit(struct bfa_fcs_s *fcs) -{ -} - -/** - * Module cleanup - */ -void -bfa_fcs_rport_modexit(struct bfa_fcs_s *fcs) -{ - bfa_fcs_modexit_comp(fcs); -} - /** * Return state of rport. */ diff --git a/drivers/scsi/bfa/vport.c b/drivers/scsi/bfa/vport.c index 8d18589e1da2..75d6f058a461 100644 --- a/drivers/scsi/bfa/vport.c +++ b/drivers/scsi/bfa/vport.c @@ -616,23 +616,6 @@ bfa_fcs_vport_delete_comp(struct bfa_fcs_vport_s *vport) bfa_sm_send_event(vport, BFA_FCS_VPORT_SM_DELCOMP); } -/** - * Module initialization - */ -void -bfa_fcs_vport_modinit(struct bfa_fcs_s *fcs) -{ -} - -/** - * Module cleanup - */ -void -bfa_fcs_vport_modexit(struct bfa_fcs_s *fcs) -{ - bfa_fcs_modexit_comp(fcs); -} - u32 bfa_fcs_vport_get_max(struct bfa_fcs_s *fcs) { -- cgit v1.2.3 From a046bf0559018ba3d16c412fc4e1aa2be5f11f36 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Wed, 3 Mar 2010 17:43:45 -0800 Subject: [SCSI] bfa: Fix to allow creation of only 190 vports on CNA. Brocade CNA currently supports only 190 vports (instead of 191), since there are only 192 unicast cam entries reserved for FCoE. Brocade CNA has a total of 256 unicast cam entries (192 FCoE + 64 LL) 192 cam entries = 1 burned in mac + 1 baseport FPMA mac + 190 vport FPMA macs. Made changes to the code to support only 190 vports. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_lps.c | 20 ++++++++++++++++++++ drivers/scsi/bfa/fcs_vport.h | 1 - drivers/scsi/bfa/include/bfa_svc.h | 1 + drivers/scsi/bfa/include/fcs/bfa_fcs_lport.h | 8 -------- drivers/scsi/bfa/lport_api.c | 3 ++- drivers/scsi/bfa/vport.c | 17 +---------------- 6 files changed, 24 insertions(+), 26 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_lps.c b/drivers/scsi/bfa/bfa_lps.c index c8c2564af725..66b9b15f4294 100644 --- a/drivers/scsi/bfa/bfa_lps.c +++ b/drivers/scsi/bfa/bfa_lps.c @@ -18,6 +18,7 @@ #include #include #include +#include BFA_TRC_FILE(HAL, LPS); BFA_MODULE(lps); @@ -25,6 +26,12 @@ BFA_MODULE(lps); #define BFA_LPS_MIN_LPORTS (1) #define BFA_LPS_MAX_LPORTS (256) +/* + * Maximum Vports supported per physical port or vf. + */ +#define BFA_LPS_MAX_VPORTS_SUPP_CB 255 +#define BFA_LPS_MAX_VPORTS_SUPP_CT 190 + /** * forward declarations */ @@ -598,6 +605,19 @@ bfa_lps_cvl_event(struct bfa_lps_s *lps) bfa_cb_lps_cvl_event(lps->bfa->bfad, lps->uarg); } +u32 +bfa_lps_get_max_vport(struct bfa_s *bfa) +{ + struct bfa_ioc_attr_s ioc_attr; + + bfa_get_attr(bfa, &ioc_attr); + + if (ioc_attr.pci_attr.device_id == BFA_PCI_DEVICE_ID_CT) + return (BFA_LPS_MAX_VPORTS_SUPP_CT); + else + return (BFA_LPS_MAX_VPORTS_SUPP_CB); +} + /** * lps_public BFA LPS public functions */ diff --git a/drivers/scsi/bfa/fcs_vport.h b/drivers/scsi/bfa/fcs_vport.h index 32565ba666eb..13c32ebf946c 100644 --- a/drivers/scsi/bfa/fcs_vport.h +++ b/drivers/scsi/bfa/fcs_vport.h @@ -26,7 +26,6 @@ void bfa_fcs_vport_cleanup(struct bfa_fcs_vport_s *vport); void bfa_fcs_vport_online(struct bfa_fcs_vport_s *vport); void bfa_fcs_vport_offline(struct bfa_fcs_vport_s *vport); void bfa_fcs_vport_delete_comp(struct bfa_fcs_vport_s *vport); -u32 bfa_fcs_vport_get_max(struct bfa_fcs_s *fcs); #endif /* __FCS_VPORT_H__ */ diff --git a/drivers/scsi/bfa/include/bfa_svc.h b/drivers/scsi/bfa/include/bfa_svc.h index 2e4372f66b8b..0d7ed4d963a7 100644 --- a/drivers/scsi/bfa/include/bfa_svc.h +++ b/drivers/scsi/bfa/include/bfa_svc.h @@ -293,6 +293,7 @@ void bfa_uf_free(struct bfa_uf_s *uf); * bfa lport service api */ +u32 bfa_lps_get_max_vport(struct bfa_s *bfa); struct bfa_lps_s *bfa_lps_alloc(struct bfa_s *bfa); void bfa_lps_delete(struct bfa_lps_s *lps); void bfa_lps_discard(struct bfa_lps_s *lps); diff --git a/drivers/scsi/bfa/include/fcs/bfa_fcs_lport.h b/drivers/scsi/bfa/include/fcs/bfa_fcs_lport.h index 967ceb0eb074..ceaefd3060f4 100644 --- a/drivers/scsi/bfa/include/fcs/bfa_fcs_lport.h +++ b/drivers/scsi/bfa/include/fcs/bfa_fcs_lport.h @@ -34,14 +34,6 @@ struct bfa_fcs_s; struct bfa_fcs_fabric_s; /* -* @todo : need to move to a global config file. - * Maximum Vports supported per physical port or vf. - */ -#define BFA_FCS_MAX_VPORTS_SUPP_CB 255 -#define BFA_FCS_MAX_VPORTS_SUPP_CT 191 - -/* -* @todo : need to move to a global config file. * Maximum Rports supported per port (physical/logical). */ #define BFA_FCS_MAX_RPORTS_SUPP 256 /* @todo : tentative value */ diff --git a/drivers/scsi/bfa/lport_api.c b/drivers/scsi/bfa/lport_api.c index 1e06792cd4c2..4a4ccce99364 100644 --- a/drivers/scsi/bfa/lport_api.c +++ b/drivers/scsi/bfa/lport_api.c @@ -235,7 +235,8 @@ bfa_fcs_port_get_info(struct bfa_fcs_port_s *port, port_info->port_wwn = bfa_fcs_port_get_pwwn(port); port_info->node_wwn = bfa_fcs_port_get_nwwn(port); - port_info->max_vports_supp = bfa_fcs_vport_get_max(port->fcs); + port_info->max_vports_supp = + bfa_lps_get_max_vport(port->fcs->bfa); port_info->num_vports_inuse = bfa_fcs_fabric_vport_count(port->fabric); port_info->max_rports_supp = BFA_FCS_MAX_RPORTS_SUPP; diff --git a/drivers/scsi/bfa/vport.c b/drivers/scsi/bfa/vport.c index 75d6f058a461..3dce9e1c947d 100644 --- a/drivers/scsi/bfa/vport.c +++ b/drivers/scsi/bfa/vport.c @@ -616,21 +616,6 @@ bfa_fcs_vport_delete_comp(struct bfa_fcs_vport_s *vport) bfa_sm_send_event(vport, BFA_FCS_VPORT_SM_DELCOMP); } -u32 -bfa_fcs_vport_get_max(struct bfa_fcs_s *fcs) -{ - struct bfa_ioc_attr_s ioc_attr; - - bfa_get_attr(fcs->bfa, &ioc_attr); - - if (ioc_attr.pci_attr.device_id == BFA_PCI_DEVICE_ID_CT) - return BFA_FCS_MAX_VPORTS_SUPP_CT; - else - return BFA_FCS_MAX_VPORTS_SUPP_CB; -} - - - /** * fcs_vport_api Virtual port API */ @@ -667,7 +652,7 @@ bfa_fcs_vport_create(struct bfa_fcs_vport_s *vport, struct bfa_fcs_s *fcs, return BFA_STATUS_VPORT_EXISTS; if (bfa_fcs_fabric_vport_count(&fcs->fabric) == - bfa_fcs_vport_get_max(fcs)) + bfa_lps_get_max_vport(fcs->bfa)) return BFA_STATUS_VPORT_MAX; vport->lps = bfa_lps_alloc(fcs->bfa); -- cgit v1.2.3 From e67143243a1a6b47e1bdcda189ffac46d2a8744d Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Wed, 3 Mar 2010 17:44:02 -0800 Subject: [SCSI] bfa: Resume BFA operations after firmware mismatch is resolved. bfad.c & bfad_drv.h: * Created a kernel thread from pci_probe that does the bfad start operations after BFA init done on a firmware mismatch. * The kernel thread on a fw mismatch waits for an event from IOC call back and is woken up from bfa_cb_init() on BFA init success. * In normal cases of no firmware mismatch this thread is terminated in pci_probe. bfa_fcs_lport.c, fabric.c, fcs_lport.h & vport.c: * Split the lport init to attach time and init time code, so that proper config attributes are set after firmware mismatch. bfa_iocfc.c: * Handle an IOC timer issue, where the IOC timer would expire before the init completion and send Init fail event to the driver, however IOC init continues and completes successfully at the later stage. The bfa and driver were not handling this kind of deferred init completion. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_fcs_lport.c | 30 ++++--- drivers/scsi/bfa/bfa_iocfc.c | 6 +- drivers/scsi/bfa/bfad.c | 189 ++++++++++++++++++++++++++++++--------- drivers/scsi/bfa/bfad_drv.h | 12 ++- drivers/scsi/bfa/fabric.c | 4 +- drivers/scsi/bfa/fcs_lport.h | 7 +- drivers/scsi/bfa/vport.c | 3 +- 7 files changed, 192 insertions(+), 59 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_fcs_lport.c b/drivers/scsi/bfa/bfa_fcs_lport.c index c7ab257f10a7..3d62e456950b 100644 --- a/drivers/scsi/bfa/bfa_fcs_lport.c +++ b/drivers/scsi/bfa/bfa_fcs_lport.c @@ -873,36 +873,46 @@ bfa_fcs_port_is_online(struct bfa_fcs_port_s *port) } /** - * Logical port initialization of base or virtual port. - * Called by fabric for base port or by vport for virtual ports. + * Attach time initialization of logical ports. */ void -bfa_fcs_lport_init(struct bfa_fcs_port_s *lport, struct bfa_fcs_s *fcs, - u16 vf_id, struct bfa_port_cfg_s *port_cfg, - struct bfa_fcs_vport_s *vport) +bfa_fcs_lport_attach(struct bfa_fcs_port_s *lport, struct bfa_fcs_s *fcs, + uint16_t vf_id, struct bfa_fcs_vport_s *vport) { lport->fcs = fcs; lport->fabric = bfa_fcs_vf_lookup(fcs, vf_id); - bfa_os_assign(lport->port_cfg, *port_cfg); lport->vport = vport; lport->lp_tag = (vport) ? bfa_lps_get_tag(vport->lps) : bfa_lps_get_tag(lport->fabric->lps); INIT_LIST_HEAD(&lport->rport_q); lport->num_rports = 0; +} + +/** + * Logical port initialization of base or virtual port. + * Called by fabric for base port or by vport for virtual ports. + */ - lport->bfad_port = - bfa_fcb_port_new(fcs->bfad, lport, lport->port_cfg.roles, +void +bfa_fcs_lport_init(struct bfa_fcs_port_s *lport, + struct bfa_port_cfg_s *port_cfg) +{ + struct bfa_fcs_vport_s *vport = lport->vport; + + bfa_os_assign(lport->port_cfg, *port_cfg); + + lport->bfad_port = bfa_fcb_port_new(lport->fcs->bfad, lport, + lport->port_cfg.roles, lport->fabric->vf_drv, vport ? vport->vport_drv : NULL); + bfa_fcs_port_aen_post(lport, BFA_LPORT_AEN_NEW); bfa_sm_set_state(lport, bfa_fcs_port_sm_uninit); bfa_sm_send_event(lport, BFA_FCS_PORT_SM_CREATE); } - - /** * fcs_lport_api */ diff --git a/drivers/scsi/bfa/bfa_iocfc.c b/drivers/scsi/bfa/bfa_iocfc.c index b5e7224bda4a..137591c984d7 100644 --- a/drivers/scsi/bfa/bfa_iocfc.c +++ b/drivers/scsi/bfa/bfa_iocfc.c @@ -336,8 +336,10 @@ bfa_iocfc_init_cb(void *bfa_arg, bfa_boolean_t complete) bfa_cb_init(bfa->bfad, BFA_STATUS_OK); else bfa_cb_init(bfa->bfad, BFA_STATUS_FAILED); - } else - bfa->iocfc.action = BFA_IOCFC_ACT_NONE; + } else { + if (bfa->iocfc.cfgdone) + bfa->iocfc.action = BFA_IOCFC_ACT_NONE; + } } static void diff --git a/drivers/scsi/bfa/bfad.c b/drivers/scsi/bfa/bfad.c index 965dfb575e5a..4ccaeaecd14c 100644 --- a/drivers/scsi/bfa/bfad.c +++ b/drivers/scsi/bfa/bfad.c @@ -20,6 +20,7 @@ */ #include +#include #include "bfad_drv.h" #include "bfad_im.h" #include "bfad_tm.h" @@ -97,6 +98,8 @@ bfad_fc4_probe(struct bfad_s *bfad) if (ipfc_enable) bfad_ipfc_probe(bfad); + + bfad->bfad_flags |= BFAD_FC4_PROBE_DONE; ext: return rc; } @@ -108,6 +111,7 @@ bfad_fc4_probe_undo(struct bfad_s *bfad) bfad_tm_probe_undo(bfad); if (ipfc_enable) bfad_ipfc_probe_undo(bfad); + bfad->bfad_flags &= ~BFAD_FC4_PROBE_DONE; } static void @@ -175,9 +179,19 @@ bfa_cb_init(void *drv, bfa_status_t init_status) { struct bfad_s *bfad = drv; - if (init_status == BFA_STATUS_OK) + if (init_status == BFA_STATUS_OK) { bfad->bfad_flags |= BFAD_HAL_INIT_DONE; + /* If BFAD_HAL_INIT_FAIL flag is set: + * Wake up the kernel thread to start + * the bfad operations after HAL init done + */ + if ((bfad->bfad_flags & BFAD_HAL_INIT_FAIL)) { + bfad->bfad_flags &= ~BFAD_HAL_INIT_FAIL; + wake_up_process(bfad->bfad_tsk); + } + } + complete(&bfad->comp); } @@ -749,7 +763,13 @@ bfad_drv_init(struct bfad_s *bfad) bfa_fcs_trc_init(&bfad->bfa_fcs, bfad->trcmod); bfa_fcs_aen_init(&bfad->bfa_fcs, bfad->aen); bfa_fcs_attach(&bfad->bfa_fcs, &bfad->bfa, bfad, BFA_FALSE); - bfa_fcs_init(&bfad->bfa_fcs); + + /* Do FCS init only when HAL init is done */ + if ((bfad->bfad_flags & BFAD_HAL_INIT_DONE)) { + bfa_fcs_init(&bfad->bfa_fcs); + bfad->bfad_flags |= BFAD_FCS_INIT_DONE; + } + bfa_fcs_driver_info_init(&bfad->bfa_fcs, &driver_info); bfa_fcs_set_fdmi_param(&bfad->bfa_fcs, fdmi_enable); spin_unlock_irqrestore(&bfad->bfad_lock, flags); @@ -767,12 +787,22 @@ out_hal_mem_alloc_failure: void bfad_drv_uninit(struct bfad_s *bfad) { + unsigned long flags; + + spin_lock_irqsave(&bfad->bfad_lock, flags); + init_completion(&bfad->comp); + bfa_stop(&bfad->bfa); + spin_unlock_irqrestore(&bfad->bfad_lock, flags); + wait_for_completion(&bfad->comp); + del_timer_sync(&bfad->hal_tmo); bfa_isr_disable(&bfad->bfa); bfa_detach(&bfad->bfa); bfad_remove_intr(bfad); bfa_assert(list_empty(&bfad->file_q)); bfad_hal_mem_release(bfad); + + bfad->bfad_flags &= ~BFAD_DRV_INIT_DONE; } void @@ -863,6 +893,86 @@ bfad_drv_log_level_set(struct bfad_s *bfad) bfa_log_set_level_all(&bfad->log_data, log_level); } +bfa_status_t +bfad_start_ops(struct bfad_s *bfad) +{ + int retval; + + /* PPORT FCS config */ + bfad_fcs_port_cfg(bfad); + + retval = bfad_cfg_pport(bfad, BFA_PORT_ROLE_FCP_IM); + if (retval != BFA_STATUS_OK) + goto out_cfg_pport_failure; + + /* BFAD level FC4 (IM/TM/IPFC) specific resource allocation */ + retval = bfad_fc4_probe(bfad); + if (retval != BFA_STATUS_OK) { + printk(KERN_WARNING "bfad_fc4_probe failed\n"); + goto out_fc4_probe_failure; + } + + bfad_drv_start(bfad); + + /* + * If bfa_linkup_delay is set to -1 default; try to retrive the + * value using the bfad_os_get_linkup_delay(); else use the + * passed in module param value as the bfa_linkup_delay. + */ + if (bfa_linkup_delay < 0) { + + bfa_linkup_delay = bfad_os_get_linkup_delay(bfad); + bfad_os_rport_online_wait(bfad); + bfa_linkup_delay = -1; + + } else { + bfad_os_rport_online_wait(bfad); + } + + bfa_log(bfad->logmod, BFA_LOG_LINUX_DEVICE_CLAIMED, bfad->pci_name); + + return BFA_STATUS_OK; + +out_fc4_probe_failure: + bfad_fc4_probe_undo(bfad); + bfad_uncfg_pport(bfad); +out_cfg_pport_failure: + return BFA_STATUS_FAILED; +} + +int +bfad_worker (void *ptr) +{ + struct bfad_s *bfad; + unsigned long flags; + + bfad = (struct bfad_s *)ptr; + + while (!kthread_should_stop()) { + + /* Check if the FCS init is done from bfad_drv_init; + * if not done do FCS init and set the flag. + */ + if (!(bfad->bfad_flags & BFAD_FCS_INIT_DONE)) { + spin_lock_irqsave(&bfad->bfad_lock, flags); + bfa_fcs_init(&bfad->bfa_fcs); + bfad->bfad_flags |= BFAD_FCS_INIT_DONE; + spin_unlock_irqrestore(&bfad->bfad_lock, flags); + } + + /* Start the bfad operations after HAL init done */ + bfad_start_ops(bfad); + + spin_lock_irqsave(&bfad->bfad_lock, flags); + bfad->bfad_tsk = NULL; + spin_unlock_irqrestore(&bfad->bfad_lock, flags); + + break; + } + + return 0; +} + /* * PCI_entry PCI driver entries * { */ @@ -937,57 +1047,39 @@ bfad_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid) bfad->ref_count = 0; bfad->pport.bfad = bfad; + bfad->bfad_tsk = kthread_create(bfad_worker, (void *) bfad, "%s", + "bfad_worker"); + if (IS_ERR(bfad->bfad_tsk)) { + printk(KERN_INFO "bfad[%d]: Kernel thread" + " creation failed!\n", + bfad->inst_no); + goto out_kthread_create_failure; + } + retval = bfad_drv_init(bfad); if (retval != BFA_STATUS_OK) goto out_drv_init_failure; if (!(bfad->bfad_flags & BFAD_HAL_INIT_DONE)) { + bfad->bfad_flags |= BFAD_HAL_INIT_FAIL; printk(KERN_WARNING "bfad%d: hal init failed\n", bfad->inst_no); goto ok; } - /* - * PPORT FCS config - */ - bfad_fcs_port_cfg(bfad); - - retval = bfad_cfg_pport(bfad, BFA_PORT_ROLE_FCP_IM); + retval = bfad_start_ops(bfad); if (retval != BFA_STATUS_OK) - goto out_cfg_pport_failure; + goto out_start_ops_failure; - /* - * BFAD level FC4 (IM/TM/IPFC) specific resource allocation - */ - retval = bfad_fc4_probe(bfad); - if (retval != BFA_STATUS_OK) { - printk(KERN_WARNING "bfad_fc4_probe failed\n"); - goto out_fc4_probe_failure; - } - - bfad_drv_start(bfad); + kthread_stop(bfad->bfad_tsk); + bfad->bfad_tsk = NULL; - /* - * If bfa_linkup_delay is set to -1 default; try to retrive the - * value using the bfad_os_get_linkup_delay(); else use the - * passed in module param value as the bfa_linkup_delay. - */ - if (bfa_linkup_delay < 0) { - bfa_linkup_delay = bfad_os_get_linkup_delay(bfad); - bfad_os_rport_online_wait(bfad); - bfa_linkup_delay = -1; - } else { - bfad_os_rport_online_wait(bfad); - } - - bfa_log(bfad->logmod, BFA_LOG_LINUX_DEVICE_CLAIMED, bfad->pci_name); ok: return 0; -out_fc4_probe_failure: - bfad_fc4_probe_undo(bfad); - bfad_uncfg_pport(bfad); -out_cfg_pport_failure: +out_start_ops_failure: bfad_drv_uninit(bfad); out_drv_init_failure: + kthread_stop(bfad->bfad_tsk); +out_kthread_create_failure: mutex_lock(&bfad_mutex); bfad_inst--; list_del(&bfad->list_entry); @@ -1012,6 +1104,11 @@ bfad_pci_remove(struct pci_dev *pdev) bfa_trc(bfad, bfad->inst_no); + spin_lock_irqsave(&bfad->bfad_lock, flags); + if (bfad->bfad_tsk != NULL) + kthread_stop(bfad->bfad_tsk); + spin_unlock_irqrestore(&bfad->bfad_lock, flags); + if ((bfad->bfad_flags & BFAD_DRV_INIT_DONE) && !(bfad->bfad_flags & BFAD_HAL_INIT_DONE)) { @@ -1028,13 +1125,25 @@ bfad_pci_remove(struct pci_dev *pdev) goto remove_sysfs; } - if (bfad->bfad_flags & BFAD_HAL_START_DONE) + if (bfad->bfad_flags & BFAD_HAL_START_DONE) { bfad_drv_stop(bfad); + } else if (bfad->bfad_flags & BFAD_DRV_INIT_DONE) { + /* Invoking bfa_stop() before bfa_detach + * when HAL and DRV init are success + * but HAL start did not occur. + */ + spin_lock_irqsave(&bfad->bfad_lock, flags); + init_completion(&bfad->comp); + bfa_stop(&bfad->bfa); + spin_unlock_irqrestore(&bfad->bfad_lock, flags); + wait_for_completion(&bfad->comp); + } bfad_remove_intr(bfad); - del_timer_sync(&bfad->hal_tmo); - bfad_fc4_probe_undo(bfad); + + if (bfad->bfad_flags & BFAD_FC4_PROBE_DONE) + bfad_fc4_probe_undo(bfad); if (bfad->bfad_flags & BFAD_CFG_PPORT_DONE) bfad_uncfg_pport(bfad); diff --git a/drivers/scsi/bfa/bfad_drv.h b/drivers/scsi/bfa/bfad_drv.h index 172c81e25c1c..9fa801a50250 100644 --- a/drivers/scsi/bfa/bfad_drv.h +++ b/drivers/scsi/bfa/bfad_drv.h @@ -62,7 +62,9 @@ #define BFAD_HAL_START_DONE 0x00000010 #define BFAD_PORT_ONLINE 0x00000020 #define BFAD_RPORT_ONLINE 0x00000040 - +#define BFAD_FCS_INIT_DONE 0x00000080 +#define BFAD_HAL_INIT_FAIL 0x00000100 +#define BFAD_FC4_PROBE_DONE 0x00000200 #define BFAD_PORT_DELETE 0x00000001 /* @@ -168,6 +170,7 @@ struct bfad_s { u32 inst_no; /* BFAD instance number */ u32 bfad_flags; spinlock_t bfad_lock; + struct task_struct *bfad_tsk; struct bfad_cfg_param_s cfg_data; struct bfad_msix_s msix_tab[MAX_MSIX_ENTRY]; int nvec; @@ -258,6 +261,7 @@ bfa_status_t bfad_vf_create(struct bfad_s *bfad, u16 vf_id, struct bfa_port_cfg_s *port_cfg); bfa_status_t bfad_cfg_pport(struct bfad_s *bfad, enum bfa_port_role role); bfa_status_t bfad_drv_init(struct bfad_s *bfad); +bfa_status_t bfad_start_ops(struct bfad_s *bfad); void bfad_drv_start(struct bfad_s *bfad); void bfad_uncfg_pport(struct bfad_s *bfad); void bfad_drv_stop(struct bfad_s *bfad); @@ -280,6 +284,12 @@ void bfad_drv_log_level_set(struct bfad_s *bfad); bfa_status_t bfad_fc4_module_init(void); void bfad_fc4_module_exit(void); +bfa_status_t bfad_os_kthread_create(struct bfad_s *bfad); +void bfad_os_kthread_stop(struct bfad_s *bfad); +void bfad_os_kthread_wakeup(struct bfad_s *bfad); +int bfad_os_kthread_should_stop(void); +int bfad_worker (void *ptr); + void bfad_pci_remove(struct pci_dev *pdev); int bfad_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid); void bfad_os_rport_online_wait(struct bfad_s *bfad); diff --git a/drivers/scsi/bfa/fabric.c b/drivers/scsi/bfa/fabric.c index e22989886646..20a686a420a2 100644 --- a/drivers/scsi/bfa/fabric.c +++ b/drivers/scsi/bfa/fabric.c @@ -136,8 +136,7 @@ bfa_fcs_fabric_sm_uninit(struct bfa_fcs_fabric_s *fabric, case BFA_FCS_FABRIC_SM_CREATE: bfa_sm_set_state(fabric, bfa_fcs_fabric_sm_created); bfa_fcs_fabric_init(fabric); - bfa_fcs_lport_init(&fabric->bport, fabric->fcs, FC_VF_ID_NULL, - &fabric->bport.port_cfg, NULL); + bfa_fcs_lport_init(&fabric->bport, &fabric->bport.port_cfg); break; case BFA_FCS_FABRIC_SM_LINK_UP: @@ -841,6 +840,7 @@ bfa_fcs_fabric_attach(struct bfa_fcs_s *fcs) bfa_wc_up(&fabric->wc); /* For the base port */ bfa_sm_set_state(fabric, bfa_fcs_fabric_sm_uninit); + bfa_fcs_lport_attach(&fabric->bport, fabric->fcs, FC_VF_ID_NULL, NULL); } void diff --git a/drivers/scsi/bfa/fcs_lport.h b/drivers/scsi/bfa/fcs_lport.h index ae744ba35671..a6508c8ab184 100644 --- a/drivers/scsi/bfa/fcs_lport.h +++ b/drivers/scsi/bfa/fcs_lport.h @@ -84,9 +84,10 @@ void bfa_fcs_port_uf_recv(struct bfa_fcs_port_s *lport, struct fchs_s *fchs, * Following routines will be called by Fabric to indicate port * online/offline to vport. */ -void bfa_fcs_lport_init(struct bfa_fcs_port_s *lport, struct bfa_fcs_s *fcs, - u16 vf_id, struct bfa_port_cfg_s *port_cfg, - struct bfa_fcs_vport_s *vport); +void bfa_fcs_lport_attach(struct bfa_fcs_port_s *lport, struct bfa_fcs_s *fcs, + uint16_t vf_id, struct bfa_fcs_vport_s *vport); +void bfa_fcs_lport_init(struct bfa_fcs_port_s *lport, + struct bfa_port_cfg_s *port_cfg); void bfa_fcs_port_online(struct bfa_fcs_port_s *port); void bfa_fcs_port_offline(struct bfa_fcs_port_s *port); void bfa_fcs_port_delete(struct bfa_fcs_port_s *port); diff --git a/drivers/scsi/bfa/vport.c b/drivers/scsi/bfa/vport.c index 3dce9e1c947d..13f737139379 100644 --- a/drivers/scsi/bfa/vport.c +++ b/drivers/scsi/bfa/vport.c @@ -662,7 +662,8 @@ bfa_fcs_vport_create(struct bfa_fcs_vport_s *vport, struct bfa_fcs_s *fcs, vport->vport_drv = vport_drv; bfa_sm_set_state(vport, bfa_fcs_vport_sm_uninit); - bfa_fcs_lport_init(&vport->lport, fcs, vf_id, vport_cfg, vport); + bfa_fcs_lport_attach(&vport->lport, fcs, vf_id, vport); + bfa_fcs_lport_init(&vport->lport, vport_cfg); bfa_sm_send_event(vport, BFA_FCS_VPORT_SM_CREATE); -- cgit v1.2.3 From 12c3400a84742f8bb0e4edc822e9ccba58781e0c Mon Sep 17 00:00:00 2001 From: Jiri Pirko Date: Thu, 4 Mar 2010 03:32:16 -0800 Subject: rndis_wlan: correct multicast_list handling V3 My previous patch (655ffee284dfcf9a24ac0343f3e5ee6db85b85c5) added locking in a bad way. Because rndis_set_oid can sleep, there is need to prepare multicast addresses into local buffer under netif_addr_lock first, then call rndis_set_oid outside. This caused reorganizing of the whole function. Signed-off-by: Jiri Pirko Reported-by: Jussi Kivilinna Signed-off-by: David S. Miller --- drivers/net/wireless/rndis_wlan.c | 66 ++++++++++++++++++++++++--------------- 1 file changed, 41 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/rndis_wlan.c b/drivers/net/wireless/rndis_wlan.c index 9f6d6bf06b8e..2887047069f2 100644 --- a/drivers/net/wireless/rndis_wlan.c +++ b/drivers/net/wireless/rndis_wlan.c @@ -1496,51 +1496,67 @@ static void set_multicast_list(struct usbnet *usbdev) { struct rndis_wlan_private *priv = get_rndis_wlan_priv(usbdev); struct dev_mc_list *mclist; - __le32 filter; - int ret, i, size; - char *buf; + __le32 filter, basefilter; + int ret; + char *mc_addrs = NULL; + int mc_count; - filter = RNDIS_PACKET_TYPE_DIRECTED | RNDIS_PACKET_TYPE_BROADCAST; + basefilter = filter = RNDIS_PACKET_TYPE_DIRECTED | + RNDIS_PACKET_TYPE_BROADCAST; - netif_addr_lock_bh(usbdev->net); if (usbdev->net->flags & IFF_PROMISC) { filter |= RNDIS_PACKET_TYPE_PROMISCUOUS | RNDIS_PACKET_TYPE_ALL_LOCAL; - } else if (usbdev->net->flags & IFF_ALLMULTI || - netdev_mc_count(usbdev->net) > priv->multicast_size) { + } else if (usbdev->net->flags & IFF_ALLMULTI) { + filter |= RNDIS_PACKET_TYPE_ALL_MULTICAST; + } + + if (filter != basefilter) + goto set_filter; + + /* + * mc_list should be accessed holding the lock, so copy addresses to + * local buffer first. + */ + netif_addr_lock_bh(usbdev->net); + mc_count = netdev_mc_count(usbdev->net); + if (mc_count > priv->multicast_size) { filter |= RNDIS_PACKET_TYPE_ALL_MULTICAST; - } else if (!netdev_mc_empty(usbdev->net)) { - size = min(priv->multicast_size, netdev_mc_count(usbdev->net)); - buf = kmalloc(size * ETH_ALEN, GFP_KERNEL); - if (!buf) { + } else if (mc_count) { + int i = 0; + + mc_addrs = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC); + if (!mc_addrs) { netdev_warn(usbdev->net, "couldn't alloc %d bytes of memory\n", - size * ETH_ALEN); + mc_count * ETH_ALEN); netif_addr_unlock_bh(usbdev->net); return; } - i = 0; - netdev_for_each_mc_addr(mclist, usbdev->net) { - if (i == size) - break; - memcpy(buf + i++ * ETH_ALEN, mclist->dmi_addr, ETH_ALEN); - } + netdev_for_each_mc_addr(mclist, usbdev->net) + memcpy(mc_addrs + i++ * ETH_ALEN, + mclist->dmi_addr, ETH_ALEN); + } + netif_addr_unlock_bh(usbdev->net); - ret = rndis_set_oid(usbdev, OID_802_3_MULTICAST_LIST, buf, - i * ETH_ALEN); - if (ret == 0 && i > 0) + if (filter != basefilter) + goto set_filter; + + if (mc_count) { + ret = rndis_set_oid(usbdev, OID_802_3_MULTICAST_LIST, mc_addrs, + mc_count * ETH_ALEN); + kfree(mc_addrs); + if (ret == 0) filter |= RNDIS_PACKET_TYPE_MULTICAST; else filter |= RNDIS_PACKET_TYPE_ALL_MULTICAST; netdev_dbg(usbdev->net, "OID_802_3_MULTICAST_LIST(%d, max: %d) -> %d\n", - i, priv->multicast_size, ret); - - kfree(buf); + mc_count, priv->multicast_size, ret); } - netif_addr_unlock_bh(usbdev->net); +set_filter: ret = rndis_set_oid(usbdev, OID_GEN_CURRENT_PACKET_FILTER, &filter, sizeof(filter)); if (ret < 0) { -- cgit v1.2.3 From 52d83bde6f10480268c454b3373bfcec8c2e3c3e Mon Sep 17 00:00:00 2001 From: Chihau Chau Date: Thu, 4 Feb 2010 22:27:05 -0300 Subject: Staging: comedi: poc: fix coding style issues This fixes a line over 80 characters and a brace warnings. Signed-off-by: Chihau Chau Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/poc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/poc.c b/drivers/staging/comedi/drivers/poc.c index d23e588d0632..28eba6d3cb5a 100644 --- a/drivers/staging/comedi/drivers/poc.c +++ b/drivers/staging/comedi/drivers/poc.c @@ -136,8 +136,8 @@ static int poc_attach(struct comedi_device *dev, struct comedi_devconfig *it) /* check if io addresses are available */ if (!request_region(iobase, iosize, "dac02")) { printk - ("I/O port conflict: failed to allocate ports 0x%lx to 0x%lx\n", - iobase, iobase + iosize - 1); + ("I/O port conflict: failed to allocate ports 0x%lx to " + "0x%lx\n", iobase, iobase + iosize - 1); return -EIO; } dev->iobase = iobase; @@ -156,9 +156,8 @@ static int poc_attach(struct comedi_device *dev, struct comedi_devconfig *it) s->insn_write = this_board->winsn; s->insn_read = this_board->rinsn; s->insn_bits = this_board->insnbits; - if (s->type == COMEDI_SUBD_AO || s->type == COMEDI_SUBD_DO) { + if (s->type == COMEDI_SUBD_AO || s->type == COMEDI_SUBD_DO) s->subdev_flags = SDF_WRITABLE; - } return 0; } -- cgit v1.2.3 From dedf3ad1534ff5e30a2eba88afe64bbe7beecfb6 Mon Sep 17 00:00:00 2001 From: Benjamin Adolphi Date: Sat, 6 Feb 2010 20:06:50 +0100 Subject: Staging: comedi: pcmad: Checkpatch cleanups This fixes all checkpatch issues in the pcmad comedi driver. Signed-off-by: Benjamin Adolphi Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/pcmad.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/pcmad.c b/drivers/staging/comedi/drivers/pcmad.c index acac67090810..f7991a9e0a78 100644 --- a/drivers/staging/comedi/drivers/pcmad.c +++ b/drivers/staging/comedi/drivers/pcmad.c @@ -34,11 +34,11 @@ Configuration options: [0] - I/O port base [1] - unused [2] - Analog input reference - 0 = single ended - 1 = differential + 0 = single ended + 1 = differential [3] - Analog input encoding (must match jumpers) - 0 = straight binary - 1 = two's complement + 0 = straight binary + 1 = two's complement */ #include @@ -113,9 +113,8 @@ static int pcmad_ai_insn_read(struct comedi_device *dev, data[n] = inb(dev->iobase + PCMAD_LSB); data[n] |= (inb(dev->iobase + PCMAD_MSB) << 8); - if (devpriv->twos_comp) { + if (devpriv->twos_comp) data[n] ^= (1 << (this_board->n_ai_bits - 1)); - } } return n; @@ -135,7 +134,7 @@ static int pcmad_attach(struct comedi_device *dev, struct comedi_devconfig *it) unsigned long iobase; iobase = it->options[0]; - printk("comedi%d: pcmad: 0x%04lx ", dev->minor, iobase); + printk(KERN_INFO "comedi%d: pcmad: 0x%04lx ", dev->minor, iobase); if (!request_region(iobase, PCMAD_SIZE, "pcmad")) { printk("I/O port conflict\n"); return -EIO; @@ -166,11 +165,11 @@ static int pcmad_attach(struct comedi_device *dev, struct comedi_devconfig *it) static int pcmad_detach(struct comedi_device *dev) { - printk("comedi%d: pcmad: remove\n", dev->minor); + printk(KERN_INFO "comedi%d: pcmad: remove\n", dev->minor); - if (dev->irq) { + if (dev->irq) free_irq(dev->irq, dev); - } + if (dev->iobase) release_region(dev->iobase, PCMAD_SIZE); -- cgit v1.2.3 From c2ca6a476a2fde7239a576c1bde8d7cd2ded87a8 Mon Sep 17 00:00:00 2001 From: Graham M Howe Date: Tue, 9 Feb 2010 23:42:25 +0000 Subject: Staging: comedi: fix bracing coding style issue in ni_65xx.c This is a patch to the ni_65xx.c file that fixes up a brace warning found by the checkpatch.pl tool Signed-off-by: Graham M Howe Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_65xx.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_65xx.c b/drivers/staging/comedi/drivers/ni_65xx.c index bbf75eb6d7f2..dad79d5efec6 100644 --- a/drivers/staging/comedi/drivers/ni_65xx.c +++ b/drivers/staging/comedi/drivers/ni_65xx.c @@ -26,12 +26,13 @@ /* Driver: ni_65xx Description: National Instruments 65xx static dio boards -Author: Jon Grierson , Frank Mori Hess +Author: Jon Grierson , + Frank Mori Hess Status: testing -Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510, PCI-6511, - PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514, PXI-6514, PCI-6515, - PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519, PCI-6520, PCI-6521, PXI-6521, - PCI-6528, PXI-6528 +Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510, + PCI-6511, PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514, + PXI-6514, PCI-6515, PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519, + PCI-6520, PCI-6521, PXI-6521, PCI-6528, PXI-6528 Updated: Wed Oct 18 08:59:11 EDT 2006 Based on the PCI-6527 driver by ds. @@ -418,7 +419,8 @@ static int ni_65xx_dio_insn_bits(struct comedi_device *dev, return -EINVAL; base_bitfield_channel = CR_CHAN(insn->chanspec); for (j = 0; j < max_ports_per_bitfield; ++j) { - const unsigned port_offset = ni_65xx_port_by_channel(base_bitfield_channel) + j; + const unsigned port_offset = + ni_65xx_port_by_channel(base_bitfield_channel) + j; const unsigned port = sprivate(s)->base_port + port_offset; unsigned base_port_channel; @@ -463,11 +465,11 @@ static int ni_65xx_dio_insn_bits(struct comedi_device *dev, * subdevice.) */ port_read_bits ^= 0xFF; } - if (bitshift > 0) { + if (bitshift > 0) port_read_bits <<= bitshift; - } else { + else port_read_bits >>= -bitshift; - } + read_bits |= port_read_bits; } data[1] = read_bits; @@ -532,7 +534,8 @@ static int ni_65xx_intr_cmdtest(struct comedi_device *dev, if (err) return 1; - /* step 2: make sure trigger sources are unique and mutually compatible */ + /* step 2: make sure trigger sources are unique and mutually + compatible */ if (err) return 2; @@ -790,9 +793,9 @@ static int ni_65xx_detach(struct comedi_device *dev) Master_Interrupt_Control); } - if (dev->irq) { + if (dev->irq) free_irq(dev->irq, dev); - } + if (private(dev)) { unsigned i; @@ -802,9 +805,9 @@ static int ni_65xx_detach(struct comedi_device *dev) dev->subdevices[i].private = NULL; } } - if (private(dev)->mite) { + if (private(dev)->mite) mite_unsetup(private(dev)->mite); - } + } return 0; } -- cgit v1.2.3 From 0054a361e44bf71b8bb79b863bcf00e04dc4a464 Mon Sep 17 00:00:00 2001 From: Graham M Howe Date: Wed, 10 Feb 2010 18:11:47 +0000 Subject: Staging: comedi: fix bracing coding style and 80 character issues in ni_660x.c This is a patch to the ni_660x.c file that fixes up the brace and 80 character issues found by the checkpatch tool Signed-off-by: Graham M Howe Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_660x.c | 48 ++++++++++++++++---------------- 1 file changed, 24 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_660x.c b/drivers/staging/comedi/drivers/ni_660x.c index 404d3c516ed1..df61e5a03ae1 100644 --- a/drivers/staging/comedi/drivers/ni_660x.c +++ b/drivers/staging/comedi/drivers/ni_660x.c @@ -52,7 +52,8 @@ enum ni_660x_constants { }; #define NUM_PFI_CHANNELS 40 -/* really there are only up to 3 dma channels, but the register layout allows for 4 */ +/* really there are only up to 3 dma channels, but the register layout allows +for 4 */ #define MAX_DMA_CHANNEL 4 /* See Register-Level Programmer Manual page 3.1 */ @@ -198,7 +199,7 @@ struct NI_660xRegisterData { const char *name; /* Register Name */ int offset; /* Offset from base address from GPCT chip */ enum ni_660x_register_direction direction; - enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */ + enum ni_660x_register_width size; /*1 byte, 2 bytes, or 4 bytes*/ }; static const struct NI_660xRegisterData registerData[NumRegisters] = { @@ -382,8 +383,8 @@ enum global_interrupt_config_register_bits { }; /* Offset of the GPCT chips from the base-adress of the card */ -static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 }; /* First chip is at base-address + - 0x00, etc. */ +/* First chip is at base-address + 0x00, etc. */ +static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 }; /* Board description*/ struct ni_660x_board { @@ -993,9 +994,9 @@ static int ni_660x_allocate_private(struct comedi_device *dev) spin_lock_init(&private(dev)->mite_channel_lock); spin_lock_init(&private(dev)->interrupt_lock); spin_lock_init(&private(dev)->soft_reg_copy_lock); - for (i = 0; i < NUM_PFI_CHANNELS; ++i) { + for (i = 0; i < NUM_PFI_CHANNELS; ++i) private(dev)->pfi_output_selects[i] = pfi_output_select_counter; - } + return 0; } @@ -1008,9 +1009,8 @@ static int ni_660x_alloc_mite_rings(struct comedi_device *dev) for (j = 0; j < counters_per_chip; ++j) { private(dev)->mite_rings[i][j] = mite_alloc_ring(private(dev)->mite); - if (private(dev)->mite_rings[i][j] == NULL) { + if (private(dev)->mite_rings[i][j] == NULL) return -ENOMEM; - } } } return 0; @@ -1022,9 +1022,8 @@ static void ni_660x_free_mite_rings(struct comedi_device *dev) unsigned j; for (i = 0; i < board(dev)->n_chips; ++i) { - for (j = 0; j < counters_per_chip; ++j) { + for (j = 0; j < counters_per_chip; ++j) mite_free_ring(private(dev)->mite_rings[i][j]); - } } } @@ -1078,15 +1077,16 @@ static int ni_660x_attach(struct comedi_device *dev, s->insn_bits = ni_660x_dio_insn_bits; s->insn_config = ni_660x_dio_insn_config; s->io_bits = 0; /* all bits default to input */ - /* we use the ioconfig registers to control dio direction, so zero output enables in stc dio control reg */ + /* we use the ioconfig registers to control dio direction, so zero + output enables in stc dio control reg */ ni_660x_write_register(dev, 0, 0, STCDIOControl); private(dev)->counter_dev = ni_gpct_device_construct(dev, - &ni_gpct_write_register, - &ni_gpct_read_register, - ni_gpct_variant_660x, - ni_660x_num_counters - (dev)); + &ni_gpct_write_register, + &ni_gpct_read_register, + ni_gpct_variant_660x, + ni_660x_num_counters + (dev)); if (private(dev)->counter_dev == NULL) return -ENOMEM; for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) { @@ -1118,12 +1118,12 @@ static int ni_660x_attach(struct comedi_device *dev, s->type = COMEDI_SUBD_UNUSED; } } - for (i = 0; i < board(dev)->n_chips; ++i) { + for (i = 0; i < board(dev)->n_chips; ++i) init_tio_chip(dev, i); - } - for (i = 0; i < ni_660x_num_counters(dev); ++i) { + + for (i = 0; i < ni_660x_num_counters(dev); ++i) ni_tio_init_counter(&private(dev)->counter_dev->counters[i]); - } + for (i = 0; i < NUM_PFI_CHANNELS; ++i) { if (i < min_counter_pfi_chan) ni_660x_set_pfi_routing(dev, i, pfi_output_select_do); @@ -1134,9 +1134,9 @@ static int ni_660x_attach(struct comedi_device *dev, } /* to be safe, set counterswap bits on tio chips after all the counter outputs have been set to high impedance mode */ - for (i = 0; i < board(dev)->n_chips; ++i) { + for (i = 0; i < board(dev)->n_chips; ++i) set_tio_counterswap(dev, i); - } + ret = request_irq(mite_irq(private(dev)->mite), ni_660x_interrupt, IRQF_SHARED, "ni_660x", dev); if (ret < 0) { @@ -1193,9 +1193,9 @@ static void init_tio_chip(struct comedi_device *dev, int chipset) private(dev)-> dma_configuration_soft_copies[chipset], DMAConfigRegister); - for (i = 0; i < NUM_PFI_CHANNELS; ++i) { + for (i = 0; i < NUM_PFI_CHANNELS; ++i) ni_660x_write_register(dev, chipset, 0, IOConfigReg(i)); - } + } static int -- cgit v1.2.3 From 49c9b5c7bd6cf87ccc1d820dec8d23ba3ae53f64 Mon Sep 17 00:00:00 2001 From: Chihau Chau Date: Thu, 11 Feb 2010 15:47:47 -0300 Subject: Staging: dream: camera: msm_camera: fix coding style issues This fixes some coding style issues like to use __func__ instead __FUNCTION__, "foo *bar" instead "foo* bar" and a initial comment with "/* */" instead "//" Signed-off-by: Chihau Chau Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dream/camera/msm_camera.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dream/camera/msm_camera.c b/drivers/staging/dream/camera/msm_camera.c index 7d938772eacc..4f808dc2ca48 100644 --- a/drivers/staging/dream/camera/msm_camera.c +++ b/drivers/staging/dream/camera/msm_camera.c @@ -2,7 +2,7 @@ * Copyright (C) 2008-2009 QUALCOMM Incorporated. */ -//FIXME: most allocations need not be GFP_ATOMIC +/* FIXME: most allocations need not be GFP_ATOMIC */ /* FIXME: management of mutexes */ /* FIXME: msm_pmem_region_lookup return values */ /* FIXME: way too many copy to/from user */ @@ -361,7 +361,7 @@ static int __msm_get_frame(struct msm_sync *sync, if (!frame->buffer) { pr_err("%s: cannot get frame, invalid lookup address " "y=%x cbcr=%x offset=%d\n", - __FUNCTION__, + __func__, pphy->y_phy, pphy->cbcr_phy, frame->y_off); @@ -455,7 +455,7 @@ static int msm_disable_vfe(struct msm_sync *sync, void __user *arg) return rc; } -static struct msm_queue_cmd* __msm_control(struct msm_sync *sync, +static struct msm_queue_cmd *__msm_control(struct msm_sync *sync, struct msm_control_device_queue *queue, struct msm_queue_cmd *qcmd, int timeout) -- cgit v1.2.3 From 71508ee489e09dc206ea3f62542dd3bd11c0e201 Mon Sep 17 00:00:00 2001 From: Alessandro Ghedini Date: Mon, 15 Feb 2010 12:25:22 +0100 Subject: Staging: wlan-ng: fix most of the style issues in hfa384x.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fixes all the errors and the majority of the warnings found with checkpatch.pl script in hfa384x.h, following Gábor Stefanik hints Signed-off-by: Alessandro Ghedini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlan-ng/hfa384x.h | 182 ++++++++++++++++++++++---------------- 1 file changed, 107 insertions(+), 75 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/wlan-ng/hfa384x.h b/drivers/staging/wlan-ng/hfa384x.h index 46cce8159e59..5984d74dfce2 100644 --- a/drivers/staging/wlan-ng/hfa384x.h +++ b/drivers/staging/wlan-ng/hfa384x.h @@ -61,17 +61,17 @@ #include /*--- Mins & Maxs -----------------------------------*/ -#define HFA384x_PORTID_MAX ((u16)7) -#define HFA384x_NUMPORTS_MAX ((u16)(HFA384x_PORTID_MAX+1)) -#define HFA384x_PDR_LEN_MAX ((u16)512) /* in bytes, from EK */ -#define HFA384x_PDA_RECS_MAX ((u16)200) /* a guess */ -#define HFA384x_PDA_LEN_MAX ((u16)1024) /* in bytes, from EK */ -#define HFA384x_SCANRESULT_MAX ((u16)31) -#define HFA384x_HSCANRESULT_MAX ((u16)31) -#define HFA384x_CHINFORESULT_MAX ((u16)16) -#define HFA384x_RID_GUESSING_MAXLEN 2048 /* I'm not really sure */ -#define HFA384x_RIDDATA_MAXLEN HFA384x_RID_GUESSING_MAXLEN -#define HFA384x_USB_RWMEM_MAXLEN 2048 +#define HFA384x_PORTID_MAX ((u16)7) +#define HFA384x_NUMPORTS_MAX ((u16)(HFA384x_PORTID_MAX+1)) +#define HFA384x_PDR_LEN_MAX ((u16)512) /* in bytes, from EK */ +#define HFA384x_PDA_RECS_MAX ((u16)200) /* a guess */ +#define HFA384x_PDA_LEN_MAX ((u16)1024) /* in bytes, from EK*/ +#define HFA384x_SCANRESULT_MAX ((u16)31) +#define HFA384x_HSCANRESULT_MAX ((u16)31) +#define HFA384x_CHINFORESULT_MAX ((u16)16) +#define HFA384x_RID_GUESSING_MAXLEN 2048 /* I'm not really sure */ +#define HFA384x_RIDDATA_MAXLEN HFA384x_RID_GUESSING_MAXLEN +#define HFA384x_USB_RWMEM_MAXLEN 2048 /*--- Support Constants -----------------------------*/ #define HFA384x_PORTTYPE_IBSS ((u16)0) @@ -114,9 +114,9 @@ #define HFA384x_ADDR_AUX_OFF_MASK (0x007f) /* Make a 32-bit flat address from AUX format 16-bit page and offset */ -#define HFA384x_ADDR_AUX_MKFLAT(p, o) \ - (((u32)(((u16)(p))&HFA384x_ADDR_AUX_PAGE_MASK)) << 7) | \ - ((u32)(((u16)(o))&HFA384x_ADDR_AUX_OFF_MASK)) +#define HFA384x_ADDR_AUX_MKFLAT(p, o) \ + ((((u32)(((u16)(p))&HFA384x_ADDR_AUX_PAGE_MASK)) << 7) | \ + ((u32)(((u16)(o))&HFA384x_ADDR_AUX_OFF_MASK))) /* Make CMD format offset and page from a 32-bit flat address */ #define HFA384x_ADDR_CMD_MKPAGE(f) \ @@ -135,12 +135,21 @@ #define HFA384x_DLSTATE_FLASHENABLED 2 /*--- Register Field Masks --------------------------*/ -#define HFA384x_CMD_AINFO ((u16)(BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8))) -#define HFA384x_CMD_MACPORT ((u16)(BIT(10) | BIT(9) | BIT(8))) +#define HFA384x_CMD_AINFO ((u16)(BIT(14) | BIT(13) \ + | BIT(12) | BIT(11) \ + | BIT(10) | BIT(9) \ + | BIT(8))) +#define HFA384x_CMD_MACPORT ((u16)(BIT(10) | BIT(9) | \ + BIT(8))) #define HFA384x_CMD_PROGMODE ((u16)(BIT(9) | BIT(8))) -#define HFA384x_CMD_CMDCODE ((u16)(BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0))) +#define HFA384x_CMD_CMDCODE ((u16)(BIT(5) | BIT(4) | \ + BIT(3) | BIT(2) | \ + BIT(1) | BIT(0))) -#define HFA384x_STATUS_RESULT ((u16)(BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8))) +#define HFA384x_STATUS_RESULT ((u16)(BIT(14) | BIT(13) \ + | BIT(12) | BIT(11) \ + | BIT(10) | BIT(9) \ + | BIT(8))) /*--- Command Code Constants --------------------------*/ /*--- Controller Commands --------------------------*/ @@ -244,8 +253,10 @@ Information RID Lengths: MAC Information This is the length of JUST the DATA part of the RID (does not include the len or code fields) --------------------------------------------------------------------*/ -#define HFA384x_RID_DBMCOMMSQUALITY_LEN ((u16)sizeof(hfa384x_dbmcommsquality_t)) -#define HFA384x_RID_JOINREQUEST_LEN ((u16)sizeof(hfa384x_JoinRequest_data_t)) +#define HFA384x_RID_DBMCOMMSQUALITY_LEN \ + ((u16) sizeof(hfa384x_dbmcommsquality_t)) +#define HFA384x_RID_JOINREQUEST_LEN \ + ((u16)sizeof(hfa384x_JoinRequest_data_t)) /*-------------------------------------------------------------------- Information RIDs: Modem Information @@ -322,9 +333,11 @@ PD Record codes /*--- Register Test/Get/Set Field macros ------------------------*/ -#define HFA384x_CMD_AINFO_SET(value) ((u16)((u16)(value) << 8)) -#define HFA384x_CMD_MACPORT_SET(value) ((u16)HFA384x_CMD_AINFO_SET(value)) -#define HFA384x_CMD_PROGMODE_SET(value) ((u16)HFA384x_CMD_AINFO_SET((u16)value)) +#define HFA384x_CMD_AINFO_SET(value) ((u16)((u16)(value) << 8)) +#define HFA384x_CMD_MACPORT_SET(value) \ + ((u16)HFA384x_CMD_AINFO_SET(value)) +#define HFA384x_CMD_PROGMODE_SET(value) \ + ((u16)HFA384x_CMD_AINFO_SET((u16)value)) #define HFA384x_CMD_CMDCODE_SET(value) ((u16)(value)) #define HFA384x_STATUS_RESULT_SET(value) (((u16)(value)) << 8) @@ -402,7 +415,7 @@ typedef struct hfa384x_authenticateStation_data { /*-- Configuration Record: WPAData (data portion only) --*/ typedef struct hfa384x_WPAData { u16 datalen; - u8 data[0]; // max 80 + u8 data[0]; /* max 80 */ } __attribute__ ((packed)) hfa384x_WPAData_t; /*-------------------------------------------------------------------- @@ -479,7 +492,8 @@ Communication Frames: Field Masks for Transmit Frames #define HFA384x_TXSTATUS_AGEDERR ((u16)BIT(1)) #define HFA384x_TXSTATUS_RETRYERR ((u16)BIT(0)) /*-- Transmit Control Field --*/ -#define HFA384x_TX_MACPORT ((u16)(BIT(10) | BIT(9) | BIT(8))) +#define HFA384x_TX_MACPORT ((u16)(BIT(10) | \ + BIT(9) | BIT(8))) #define HFA384x_TX_STRUCTYPE ((u16)(BIT(4) | BIT(3))) #define HFA384x_TX_TXEX ((u16)BIT(2)) #define HFA384x_TX_TXOK ((u16)BIT(1)) @@ -496,7 +510,8 @@ Communication Frames: Test/Get/Set Field Values for Transmit Frames #define HFA384x_TX_SET(v, m, s) ((((u16)(v))<<((u16)(s)))&((u16)(m))) #define HFA384x_TX_MACPORT_SET(v) HFA384x_TX_SET(v, HFA384x_TX_MACPORT, 8) -#define HFA384x_TX_STRUCTYPE_SET(v) HFA384x_TX_SET(v, HFA384x_TX_STRUCTYPE, 3) +#define HFA384x_TX_STRUCTYPE_SET(v) HFA384x_TX_SET(v, \ + HFA384x_TX_STRUCTYPE, 3) #define HFA384x_TX_TXEX_SET(v) HFA384x_TX_SET(v, HFA384x_TX_TXEX, 2) #define HFA384x_TX_TXOK_SET(v) HFA384x_TX_SET(v, HFA384x_TX_TXOK, 1) /*-------------------------------------------------------------------- @@ -534,13 +549,17 @@ Communication Frames: Field Masks for Receive Frames --------------------------------------------------------------------*/ /*-- Status Fields --*/ -#define HFA384x_RXSTATUS_MACPORT ((u16)(BIT(10) | BIT(9) | BIT(8))) +#define HFA384x_RXSTATUS_MACPORT ((u16)(BIT(10) | \ + BIT(9) | \ + BIT(8))) #define HFA384x_RXSTATUS_FCSERR ((u16)BIT(0)) /*-------------------------------------------------------------------- Communication Frames: Test/Get/Set Field Values for Receive Frames --------------------------------------------------------------------*/ -#define HFA384x_RXSTATUS_MACPORT_GET(value) ((u16)((((u16)(value)) & HFA384x_RXSTATUS_MACPORT) >> 8)) -#define HFA384x_RXSTATUS_ISFCSERR(value) ((u16)(((u16)(value)) & HFA384x_RXSTATUS_FCSERR)) +#define HFA384x_RXSTATUS_MACPORT_GET(value) ((u16)((((u16)(value)) \ + & HFA384x_RXSTATUS_MACPORT) >> 8)) +#define HFA384x_RXSTATUS_ISFCSERR(value) ((u16)(((u16)(value)) \ + & HFA384x_RXSTATUS_FCSERR)) /*-------------------------------------------------------------------- FRAME STRUCTURES: Information Types and Information Frame Structures ---------------------------------------------------------------------- @@ -1133,7 +1152,7 @@ struct hfa384x; typedef void (*ctlx_cmdcb_t) (struct hfa384x *, const struct hfa384x_usbctlx *); -typedef void (*ctlx_usercb_t) (struct hfa384x * hw, +typedef void (*ctlx_usercb_t) (struct hfa384x *hw, void *ctlxresult, void *usercb_data); typedef struct hfa384x_usbctlx { @@ -1174,14 +1193,14 @@ typedef struct hfa484x_metacmd { } hfa384x_metacmd_t; #define MAX_GRP_ADDR 32 -#define WLAN_COMMENT_MAX 80 /* Max. length of user comment string. */ +#define WLAN_COMMENT_MAX 80 /* Max. length of user comment string. */ -#define WLAN_AUTH_MAX 60 /* Max. # of authenticated stations. */ -#define WLAN_ACCESS_MAX 60 /* Max. # of stations in an access list. */ -#define WLAN_ACCESS_NONE 0 /* No stations may be authenticated. */ -#define WLAN_ACCESS_ALL 1 /* All stations may be authenticated. */ -#define WLAN_ACCESS_ALLOW 2 /* Authenticate only "allowed" stations. */ -#define WLAN_ACCESS_DENY 3 /* Do not authenticate "denied" stations. */ +#define WLAN_AUTH_MAX 60 /* Max. # of authenticated stations. */ +#define WLAN_ACCESS_MAX 60 /* Max. # of stations in an access list. */ +#define WLAN_ACCESS_NONE 0 /* No stations may be authenticated. */ +#define WLAN_ACCESS_ALL 1 /* All stations may be authenticated. */ +#define WLAN_ACCESS_ALLOW 2 /* Authenticate only "allowed" stations. */ +#define WLAN_ACCESS_DENY 3 /* Do not authenticate "denied" stations. */ /* XXX These are going away ASAP */ typedef struct prism2sta_authlist { @@ -1294,10 +1313,23 @@ typedef struct hfa384x { hfa384x_caplevel_t cap_sup_ap; /* Actor compatibility ranges */ - hfa384x_caplevel_t cap_act_pri_cfi; /* pri f/w to controller interface */ - hfa384x_caplevel_t cap_act_sta_cfi; /* sta f/w to controller interface */ + hfa384x_caplevel_t cap_act_pri_cfi; /* + * pri f/w to controller + * interface + */ + + hfa384x_caplevel_t cap_act_sta_cfi; /* + * sta f/w to controller + * interface + */ + hfa384x_caplevel_t cap_act_sta_mfi; /* sta f/w to modem interface */ - hfa384x_caplevel_t cap_act_ap_cfi; /* ap f/w to controller interface */ + + hfa384x_caplevel_t cap_act_ap_cfi; /* + * ap f/w to controller + * interface + */ + hfa384x_caplevel_t cap_act_ap_mfi; /* ap f/w to modem interface */ u32 psusercount; /* Power save user count. */ @@ -1320,25 +1352,25 @@ typedef struct hfa384x { } hfa384x_t; -void hfa384x_create(hfa384x_t * hw, struct usb_device *usb); -void hfa384x_destroy(hfa384x_t * hw); +void hfa384x_create(hfa384x_t *hw, struct usb_device *usb); +void hfa384x_destroy(hfa384x_t *hw); int -hfa384x_corereset(hfa384x_t * hw, int holdtime, int settletime, int genesis); -int hfa384x_drvr_commtallies(hfa384x_t * hw); -int hfa384x_drvr_disable(hfa384x_t * hw, u16 macport); -int hfa384x_drvr_enable(hfa384x_t * hw, u16 macport); -int hfa384x_drvr_flashdl_enable(hfa384x_t * hw); -int hfa384x_drvr_flashdl_disable(hfa384x_t * hw); -int hfa384x_drvr_flashdl_write(hfa384x_t * hw, u32 daddr, void *buf, u32 len); -int hfa384x_drvr_getconfig(hfa384x_t * hw, u16 rid, void *buf, u16 len); -int hfa384x_drvr_ramdl_enable(hfa384x_t * hw, u32 exeaddr); -int hfa384x_drvr_ramdl_disable(hfa384x_t * hw); -int hfa384x_drvr_ramdl_write(hfa384x_t * hw, u32 daddr, void *buf, u32 len); -int hfa384x_drvr_readpda(hfa384x_t * hw, void *buf, unsigned int len); -int hfa384x_drvr_setconfig(hfa384x_t * hw, u16 rid, void *buf, u16 len); - -static inline int hfa384x_drvr_getconfig16(hfa384x_t * hw, u16 rid, void *val) +hfa384x_corereset(hfa384x_t *hw, int holdtime, int settletime, int genesis); +int hfa384x_drvr_commtallies(hfa384x_t *hw); +int hfa384x_drvr_disable(hfa384x_t *hw, u16 macport); +int hfa384x_drvr_enable(hfa384x_t *hw, u16 macport); +int hfa384x_drvr_flashdl_enable(hfa384x_t *hw); +int hfa384x_drvr_flashdl_disable(hfa384x_t *hw); +int hfa384x_drvr_flashdl_write(hfa384x_t *hw, u32 daddr, void *buf, u32 len); +int hfa384x_drvr_getconfig(hfa384x_t *hw, u16 rid, void *buf, u16 len); +int hfa384x_drvr_ramdl_enable(hfa384x_t *hw, u32 exeaddr); +int hfa384x_drvr_ramdl_disable(hfa384x_t *hw); +int hfa384x_drvr_ramdl_write(hfa384x_t *hw, u32 daddr, void *buf, u32 len); +int hfa384x_drvr_readpda(hfa384x_t *hw, void *buf, unsigned int len); +int hfa384x_drvr_setconfig(hfa384x_t *hw, u16 rid, void *buf, u16 len); + +static inline int hfa384x_drvr_getconfig16(hfa384x_t *hw, u16 rid, void *val) { int result = 0; result = hfa384x_drvr_getconfig(hw, rid, val, sizeof(u16)); @@ -1347,46 +1379,46 @@ static inline int hfa384x_drvr_getconfig16(hfa384x_t * hw, u16 rid, void *val) return result; } -static inline int hfa384x_drvr_setconfig16(hfa384x_t * hw, u16 rid, u16 val) +static inline int hfa384x_drvr_setconfig16(hfa384x_t *hw, u16 rid, u16 val) { u16 value = cpu_to_le16(val); return hfa384x_drvr_setconfig(hw, rid, &value, sizeof(value)); } int -hfa384x_drvr_getconfig_async(hfa384x_t * hw, +hfa384x_drvr_getconfig_async(hfa384x_t *hw, u16 rid, ctlx_usercb_t usercb, void *usercb_data); int -hfa384x_drvr_setconfig_async(hfa384x_t * hw, +hfa384x_drvr_setconfig_async(hfa384x_t *hw, u16 rid, void *buf, u16 len, ctlx_usercb_t usercb, void *usercb_data); static inline int -hfa384x_drvr_setconfig16_async(hfa384x_t * hw, u16 rid, u16 val) +hfa384x_drvr_setconfig16_async(hfa384x_t *hw, u16 rid, u16 val) { u16 value = cpu_to_le16(val); return hfa384x_drvr_setconfig_async(hw, rid, &value, sizeof(value), NULL, NULL); } -int hfa384x_drvr_start(hfa384x_t * hw); -int hfa384x_drvr_stop(hfa384x_t * hw); +int hfa384x_drvr_start(hfa384x_t *hw); +int hfa384x_drvr_stop(hfa384x_t *hw); int -hfa384x_drvr_txframe(hfa384x_t * hw, struct sk_buff *skb, - p80211_hdr_t * p80211_hdr, p80211_metawep_t * p80211_wep); -void hfa384x_tx_timeout(wlandevice_t * wlandev); - -int hfa384x_cmd_initialize(hfa384x_t * hw); -int hfa384x_cmd_enable(hfa384x_t * hw, u16 macport); -int hfa384x_cmd_disable(hfa384x_t * hw, u16 macport); -int hfa384x_cmd_allocate(hfa384x_t * hw, u16 len); -int hfa384x_cmd_monitor(hfa384x_t * hw, u16 enable); +hfa384x_drvr_txframe(hfa384x_t *hw, struct sk_buff *skb, + p80211_hdr_t *p80211_hdr, p80211_metawep_t *p80211_wep); +void hfa384x_tx_timeout(wlandevice_t *wlandev); + +int hfa384x_cmd_initialize(hfa384x_t *hw); +int hfa384x_cmd_enable(hfa384x_t *hw, u16 macport); +int hfa384x_cmd_disable(hfa384x_t *hw, u16 macport); +int hfa384x_cmd_allocate(hfa384x_t *hw, u16 len); +int hfa384x_cmd_monitor(hfa384x_t *hw, u16 enable); int -hfa384x_cmd_download(hfa384x_t * hw, +hfa384x_cmd_download(hfa384x_t *hw, u16 mode, u16 lowaddr, u16 highaddr, u16 codelen); -#endif /* __KERNEL__ */ +#endif /*__KERNEL__ */ -#endif /* _HFA384x_H */ +#endif /*_HFA384x_H */ -- cgit v1.2.3 From d4023a5ee2f683f57636346c0baf94cda710055a Mon Sep 17 00:00:00 2001 From: Chihau Chau Date: Thu, 25 Feb 2010 18:13:00 -0300 Subject: Staging: dream: camera: msm_camera: fix some code style issues This fixes some code style issues like else staments after the close braces '}' and to use __func__ instead of __FUNCTION__. Signed-off-by: Chihau Chau Acked-by: Pavel Machek Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dream/camera/msm_camera.c | 37 +++++++++++++++---------------- 1 file changed, 18 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dream/camera/msm_camera.c b/drivers/staging/dream/camera/msm_camera.c index 4f808dc2ca48..925e16c324d2 100644 --- a/drivers/staging/dream/camera/msm_camera.c +++ b/drivers/staging/dream/camera/msm_camera.c @@ -670,7 +670,7 @@ static int msm_get_stats(struct msm_sync *sync, void __user *arg) &(stats.fd)); if (!stats.buffer) { pr_err("%s: msm_pmem_stats_ptov_lookup error\n", - __FUNCTION__); + __func__); rc = -EINVAL; goto failure; } @@ -718,8 +718,7 @@ static int msm_get_stats(struct msm_sync *sync, void __user *arg) buf.fmain.buffer = (unsigned long)region.vaddr; buf.fmain.fd = region.fd; - } - else { + } else { pr_err("%s: pmem lookup failed\n", __func__); rc = -EINVAL; @@ -838,8 +837,8 @@ static int msm_ctrl_cmd_done(struct msm_control_device *ctrl_pmsm, kfree(qcmd); goto end; } - } - else ctrlcmd->value = NULL; + } else + ctrlcmd->value = NULL; end: CDBG("msm_ctrl_cmd_done: end rc = %d\n", rc); @@ -876,7 +875,7 @@ static int msm_config_vfe(struct msm_sync *sync, void __user *arg) MSM_PMEM_AEC_AWB, ®ion[0], NUM_WB_EXP_STAT_OUTPUT_BUFFERS); if (!axi_data.bufnum1) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } axi_data.region = ®ion[0]; @@ -888,7 +887,7 @@ static int msm_config_vfe(struct msm_sync *sync, void __user *arg) MSM_PMEM_AF, ®ion[0], NUM_AF_STAT_OUTPUT_BUFFERS); if (!axi_data.bufnum1) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } axi_data.region = ®ion[0]; @@ -899,7 +898,7 @@ static int msm_config_vfe(struct msm_sync *sync, void __user *arg) break; default: pr_err("%s: unknown command type %d\n", - __FUNCTION__, cfgcmd.cmd_type); + __func__, cfgcmd.cmd_type); return -EINVAL; } @@ -928,7 +927,7 @@ static int msm_frame_axi_cfg(struct msm_sync *sync, msm_pmem_region_lookup(&sync->frame, pmem_type, ®ion[0], 8); if (!axi_data.bufnum1) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } break; @@ -939,7 +938,7 @@ static int msm_frame_axi_cfg(struct msm_sync *sync, msm_pmem_region_lookup(&sync->frame, pmem_type, ®ion[0], 8); if (!axi_data.bufnum2) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } break; @@ -950,7 +949,7 @@ static int msm_frame_axi_cfg(struct msm_sync *sync, msm_pmem_region_lookup(&sync->frame, pmem_type, ®ion[0], 8); if (!axi_data.bufnum1) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } @@ -959,7 +958,7 @@ static int msm_frame_axi_cfg(struct msm_sync *sync, msm_pmem_region_lookup(&sync->frame, pmem_type, ®ion[axi_data.bufnum1], 8); if (!axi_data.bufnum2) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } break; @@ -970,7 +969,7 @@ static int msm_frame_axi_cfg(struct msm_sync *sync, msm_pmem_region_lookup(&sync->frame, pmem_type, ®ion[0], 8); if (!axi_data.bufnum2) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } break; @@ -981,7 +980,7 @@ static int msm_frame_axi_cfg(struct msm_sync *sync, default: pr_err("%s: unknown command type %d\n", - __FUNCTION__, cfgcmd->cmd_type); + __func__, cfgcmd->cmd_type); return -EINVAL; } @@ -1047,7 +1046,7 @@ static int __msm_put_frame_buf(struct msm_sync *sync, rc = sync->vfefn.vfe_config(&cfgcmd, &pphy); } else { pr_err("%s: msm_pmem_frame_vtop_lookup failed\n", - __FUNCTION__); + __func__); rc = -EINVAL; } @@ -1131,7 +1130,7 @@ static int msm_stats_axi_cfg(struct msm_sync *sync, break; default: pr_err("%s: unknown command type %d\n", - __FUNCTION__, cfgcmd->cmd_type); + __func__, cfgcmd->cmd_type); return -EINVAL; } @@ -1140,7 +1139,7 @@ static int msm_stats_axi_cfg(struct msm_sync *sync, msm_pmem_region_lookup(&sync->stats, pmem_type, ®ion[0], NUM_WB_EXP_STAT_OUTPUT_BUFFERS); if (!axi_data.bufnum1) { - pr_err("%s: pmem region lookup error\n", __FUNCTION__); + pr_err("%s: pmem region lookup error\n", __func__); return -EINVAL; } axi_data.region = ®ion[0]; @@ -1177,7 +1176,7 @@ static int msm_put_stats_buffer(struct msm_sync *sync, void __user *arg) cfgcmd.cmd_type = CMD_STATS_AF_BUF_RELEASE; else { pr_err("%s: invalid buf type %d\n", - __FUNCTION__, + __func__, buf.type); rc = -EINVAL; goto put_done; @@ -1223,7 +1222,7 @@ static int msm_axi_config(struct msm_sync *sync, void __user *arg) default: pr_err("%s: unknown command type %d\n", - __FUNCTION__, + __func__, cfgcmd.cmd_type); return -EINVAL; } -- cgit v1.2.3 From a917d4c4251314afc196fd7a7d9d10faff2effda Mon Sep 17 00:00:00 2001 From: Chihau Chau Date: Thu, 25 Feb 2010 17:40:28 -0300 Subject: Staging: comedi: poc: Adding some KERN_ facility level This fixes some coding style issues like include KERN_ facility levels in some printk() and one trailing whitespace error. Signed-off-by: Chihau Chau Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/poc.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/poc.c b/drivers/staging/comedi/drivers/poc.c index 28eba6d3cb5a..e15fbd7d3141 100644 --- a/drivers/staging/comedi/drivers/poc.c +++ b/drivers/staging/comedi/drivers/poc.c @@ -122,22 +122,21 @@ static int poc_attach(struct comedi_device *dev, struct comedi_devconfig *it) unsigned int iosize; iobase = it->options[0]; - printk("comedi%d: poc: using %s iobase 0x%lx\n", dev->minor, + printk(KERN_INFO "comedi%d: poc: using %s iobase 0x%lx\n", dev->minor, this_board->name, iobase); dev->board_name = this_board->name; if (iobase == 0) { - printk("io base address required\n"); + printk(KERN_ERR "io base address required\n"); return -EINVAL; } iosize = this_board->iosize; /* check if io addresses are available */ if (!request_region(iobase, iosize, "dac02")) { - printk - ("I/O port conflict: failed to allocate ports 0x%lx to " - "0x%lx\n", iobase, iobase + iosize - 1); + printk(KERN_ERR "I/O port conflict: failed to allocate ports " + "0x%lx to 0x%lx\n", iobase, iobase + iosize - 1); return -EIO; } dev->iobase = iobase; -- cgit v1.2.3 From 8377e813c75cf5aca46032fb780ca74c923dbe86 Mon Sep 17 00:00:00 2001 From: Maurice Dawson Date: Fri, 19 Feb 2010 10:53:13 +0000 Subject: Staging: comedi: fix brace coding style issue in ni_labpc.c This is a patch to the ni_labpc.c file that fixes up a brace warning found by the checkpatch.pl tool. Signed-off-by: Maurice Dawson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_labpc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_labpc.c b/drivers/staging/comedi/drivers/ni_labpc.c index dc3f398cb3ed..a01e35d4b31e 100644 --- a/drivers/staging/comedi/drivers/ni_labpc.c +++ b/drivers/staging/comedi/drivers/ni_labpc.c @@ -483,12 +483,10 @@ int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, printk("comedi%d: ni_labpc: %s, io 0x%lx", dev->minor, thisboard->name, iobase); - if (irq) { + if (irq) printk(", irq %u", irq); - } - if (dma_chan) { + if (dma_chan) printk(", dma %u", dma_chan); - } printk("\n"); if (iobase == 0) { -- cgit v1.2.3 From 2bb9c335902a5d59fc084170aaae0ccc9d9d4012 Mon Sep 17 00:00:00 2001 From: Maurice Dawson Date: Fri, 19 Feb 2010 10:53:14 +0000 Subject: Staging: comedi: fix another brace coding style issues in ni_labpc.c This is a patch to the ni_labpc.c file that fixes up a brace warning found by the checkpatch.pl tool Signed-off-by: Maurice Dawson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_labpc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_labpc.c b/drivers/staging/comedi/drivers/ni_labpc.c index a01e35d4b31e..5dc8606009aa 100644 --- a/drivers/staging/comedi/drivers/ni_labpc.c +++ b/drivers/staging/comedi/drivers/ni_labpc.c @@ -638,9 +638,8 @@ int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, s->insn_read = labpc_eeprom_read_insn; s->insn_write = labpc_eeprom_write_insn; - for (i = 0; i < EEPROM_SIZE; i++) { + for (i = 0; i < EEPROM_SIZE; i++) devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); - } #ifdef LABPC_DEBUG printk(" eeprom:"); for (i = 0; i < EEPROM_SIZE; i++) { -- cgit v1.2.3 From 65d6d26c6bcd802ebe2b22a29d9b6bbebfd8d7f8 Mon Sep 17 00:00:00 2001 From: Maurice Dawson Date: Fri, 19 Feb 2010 10:53:15 +0000 Subject: Staging: comedi: fix yet another brace coding style issue in ni_labpc.c This is a patch to the ni_labpc.c file that fixes up all the brace warnings found by the checkpatch.pl tool Signed-off-by: Maurice Dawson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_labpc.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_labpc.c b/drivers/staging/comedi/drivers/ni_labpc.c index 5dc8606009aa..d6b5c05ee199 100644 --- a/drivers/staging/comedi/drivers/ni_labpc.c +++ b/drivers/staging/comedi/drivers/ni_labpc.c @@ -642,9 +642,8 @@ int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); #ifdef LABPC_DEBUG printk(" eeprom:"); - for (i = 0; i < EEPROM_SIZE; i++) { + for (i = 0; i < EEPROM_SIZE; i++) printk(" %i:0x%x ", i, devpriv->eeprom_data[i]); - } printk("\n"); #endif } else @@ -676,9 +675,8 @@ static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) case pci_bustype: #ifdef CONFIG_COMEDI_PCI retval = labpc_find_device(dev, it->options[0], it->options[1]); - if (retval < 0) { + if (retval < 0) return retval; - } retval = mite_setup(devpriv->mite); if (retval < 0) return retval; @@ -1005,9 +1003,9 @@ static int labpc_ai_cmdtest(struct comedi_device *dev, err++; } - if (!cmd->chanlist_len) { + if (!cmd->chanlist_len) err++; - } + if (cmd->scan_end_arg != cmd->chanlist_len) { cmd->scan_end_arg = cmd->chanlist_len; err++; @@ -1102,9 +1100,9 @@ static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); /* initialize software conversion count */ - if (cmd->stop_src == TRIG_COUNT) { + if (cmd->stop_src == TRIG_COUNT) devpriv->count = cmd->stop_arg * cmd->chanlist_len; - } + /* setup hardware conversion counter */ if (cmd->stop_src == TRIG_EXT) { /* load counter a1 with count of 3 (pc+ manual says this is minimum allowed) using mode 0 */ @@ -1476,9 +1474,9 @@ static void labpc_drain_dma(struct comedi_device *dev) } /* write data to comedi buffer */ - for (i = 0; i < num_points; i++) { + for (i = 0; i < num_points; i++) cfc_write_to_buffer(s, devpriv->dma_buffer[i]); - } + if (async->cmd.stop_src == TRIG_COUNT) devpriv->count -= num_points; @@ -1861,9 +1859,9 @@ static unsigned int labpc_serial_in(struct comedi_device *dev) udelay(1); devpriv->status2_bits = devpriv->read_byte(dev->iobase + STATUS2_REG); - if (devpriv->status2_bits & EEPROM_OUT_BIT) { + if (devpriv->status2_bits & EEPROM_OUT_BIT) value |= 1 << (value_width - i); - } + } return value; -- cgit v1.2.3 From 639b9f1ee5987270be2bca4bf8b7e6110d3b47ec Mon Sep 17 00:00:00 2001 From: Stewart Robertson Date: Sun, 21 Feb 2010 11:21:37 +0000 Subject: Staging: comedi: fix suspect code indent in ni_labpc.c This is a patch to the ni_labpc.c file that fixes suspect code indent for conditional statements found by the checkpatch.pl tool Signed-off-by: Stewart Robertson Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/ni_labpc.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/drivers/ni_labpc.c b/drivers/staging/comedi/drivers/ni_labpc.c index d6b5c05ee199..ddc3b0715dc3 100644 --- a/drivers/staging/comedi/drivers/ni_labpc.c +++ b/drivers/staging/comedi/drivers/ni_labpc.c @@ -583,8 +583,11 @@ int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, /* analog output */ s = dev->subdevices + 1; if (thisboard->has_ao) { -/* Could provide command support, except it only has a one sample - * hardware buffer for analog output and no underrun flag. */ + /* + * Could provide command support, except it only has a + * one sample hardware buffer for analog output and no + * underrun flag. + */ s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; s->n_chan = NUM_AO_CHAN; @@ -1356,7 +1359,10 @@ static irqreturn_t labpc_interrupt(int irq, void *d) } if (devpriv->current_transfer == isa_dma_transfer) { - /* if a dma terminal count of external stop trigger has occurred */ + /* + * if a dma terminal count of external stop trigger + * has occurred + */ if (devpriv->status1_bits & DMATC_BIT || (thisboard->register_layout == labpc_1200_layout && devpriv->status2_bits & A1_TC_BIT)) { -- cgit v1.2.3 From 6705b68d0be284e2f9949f3657ea65d426d0f988 Mon Sep 17 00:00:00 2001 From: Andrea Gelmini Date: Fri, 26 Feb 2010 10:14:55 +0100 Subject: Staging: comedi: comedi_fops.c: Checkpatch cleanup ERROR: do not initialise externals to 0 or NULL +int comedi_num_legacy_minors = 0; WARNING: braces {} are not necessary for single statement blocks + if (s->subdev_flags & SDF_CMD_READ) { + kill_fasync(&dev->async_queue, SIGIO, POLL_IN); + } WARNING: braces {} are not necessary for single statement blocks + if (s->subdev_flags & SDF_CMD_WRITE) { + kill_fasync(&dev->async_queue, SIGIO, POLL_OUT); + } Signed-off-by: Andrea Gelmini Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/comedi_fops.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/comedi/comedi_fops.c b/drivers/staging/comedi/comedi_fops.c index 8117748ad5a5..aca96747e5e2 100644 --- a/drivers/staging/comedi/comedi_fops.c +++ b/drivers/staging/comedi/comedi_fops.c @@ -63,7 +63,7 @@ module_param(comedi_debug, int, 0644); int comedi_autoconfig = 1; module_param(comedi_autoconfig, bool, 0444); -int comedi_num_legacy_minors = 0; +int comedi_num_legacy_minors; module_param(comedi_num_legacy_minors, int, 0444); static DEFINE_SPINLOCK(comedi_file_info_table_lock); @@ -1510,7 +1510,7 @@ static unsigned int comedi_poll(struct file *file, poll_table * wait) } static ssize_t comedi_write(struct file *file, const char *buf, size_t nbytes, - loff_t * offset) + loff_t *offset) { struct comedi_subdevice *s; struct comedi_async *async; @@ -1612,7 +1612,7 @@ done: } static ssize_t comedi_read(struct file *file, char *buf, size_t nbytes, - loff_t * offset) + loff_t *offset) { struct comedi_subdevice *s; struct comedi_async *async; @@ -2004,12 +2004,10 @@ void comedi_event(struct comedi_device *dev, struct comedi_subdevice *s) if (async->cb_mask & s->async->events) { if (comedi_get_subdevice_runflags(s) & SRF_USER) { wake_up_interruptible(&async->wait_head); - if (s->subdev_flags & SDF_CMD_READ) { + if (s->subdev_flags & SDF_CMD_READ) kill_fasync(&dev->async_queue, SIGIO, POLL_IN); - } - if (s->subdev_flags & SDF_CMD_WRITE) { + if (s->subdev_flags & SDF_CMD_WRITE) kill_fasync(&dev->async_queue, SIGIO, POLL_OUT); - } } else { if (async->cb_func) async->cb_func(s->async->events, async->cb_arg); -- cgit v1.2.3 From ef1a0ed7f1793531e5fb3ee489cb1e2b627f76fd Mon Sep 17 00:00:00 2001 From: Andrew Elwell Date: Thu, 18 Feb 2010 23:56:12 +0100 Subject: Staging: wlan-ng - checkpatch.pl fixups Basic fixups in the staging/wlan-ng directory. (First kernel patch - thanks to FOSDEM talk) Signed-off-by: Andrew Elwell Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlan-ng/hfa384x_usb.c | 12 +++--- drivers/staging/wlan-ng/p80211conv.h | 4 +- drivers/staging/wlan-ng/p80211metadef.h | 18 ++++----- drivers/staging/wlan-ng/p80211mgmt.h | 42 ++++++++++---------- drivers/staging/wlan-ng/p80211netdev.c | 4 +- drivers/staging/wlan-ng/p80211netdev.h | 44 ++++++++++----------- drivers/staging/wlan-ng/p80211req.c | 2 +- drivers/staging/wlan-ng/p80211req.h | 2 +- drivers/staging/wlan-ng/p80211types.h | 12 +++--- drivers/staging/wlan-ng/p80211wext.c | 56 +++++++++++++------------- drivers/staging/wlan-ng/prism2fw.c | 69 +++++++++++++++------------------ drivers/staging/wlan-ng/prism2mgmt.c | 30 +++++++------- drivers/staging/wlan-ng/prism2mgmt.h | 48 +++++++++++------------ drivers/staging/wlan-ng/prism2mib.c | 11 +++--- drivers/staging/wlan-ng/prism2sta.c | 23 ++++++----- 15 files changed, 183 insertions(+), 194 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/wlan-ng/hfa384x_usb.c b/drivers/staging/wlan-ng/hfa384x_usb.c index 925678babd9e..730d085c3f87 100644 --- a/drivers/staging/wlan-ng/hfa384x_usb.c +++ b/drivers/staging/wlan-ng/hfa384x_usb.c @@ -118,15 +118,15 @@ #include #include #include -#include +#include #include #include -#include +#include #include #include #include -#define SUBMIT_URB(u,f) usb_submit_urb(u,f) +#define SUBMIT_URB(u, f) usb_submit_urb(u, f) #include "p80211types.h" #include "p80211hdr.h" @@ -627,7 +627,7 @@ static hfa384x_usbctlx_t *usbctlx_alloc(void) { hfa384x_usbctlx_t *ctlx; - ctlx = kmalloc(sizeof(*ctlx), in_interrupt()? GFP_ATOMIC : GFP_KERNEL); + ctlx = kmalloc(sizeof(*ctlx), in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); if (ctlx != NULL) { memset(ctlx, 0, sizeof(*ctlx)); init_completion(&ctlx->done); @@ -675,7 +675,7 @@ struct usbctlx_cmd_completor { }; typedef struct usbctlx_cmd_completor usbctlx_cmd_completor_t; -static int usbctlx_cmd_completor_fn(usbctlx_completor_t * head) +static int usbctlx_cmd_completor_fn(usbctlx_completor_t *head) { usbctlx_cmd_completor_t *complete = (usbctlx_cmd_completor_t *) head; return usbctlx_get_status(complete->cmdresp, complete->result); @@ -3642,7 +3642,7 @@ static void hfa384x_int_rxmonitor(wlandevice_t *wlandev, /* check for unencrypted stuff if WEP bit set. */ if (*(datap - hdrlen + 1) & 0x40) /* wep set */ if ((*(datap) == 0xaa) && (*(datap + 1) == 0xaa)) - *(datap - hdrlen + 1) &= 0xbf; // clear wep; it's the 802.2 header! + *(datap - hdrlen + 1) &= 0xbf; /* clear wep; it's the 802.2 header! */ } if (hw->sniff_fcs) { diff --git a/drivers/staging/wlan-ng/p80211conv.h b/drivers/staging/wlan-ng/p80211conv.h index 0c62df19fa7f..6fe163be24f6 100644 --- a/drivers/staging/wlan-ng/p80211conv.h +++ b/drivers/staging/wlan-ng/p80211conv.h @@ -153,8 +153,8 @@ struct wlandevice; int skb_p80211_to_ether(struct wlandevice *wlandev, u32 ethconv, struct sk_buff *skb); int skb_ether_to_p80211(struct wlandevice *wlandev, u32 ethconv, - struct sk_buff *skb, p80211_hdr_t * p80211_hdr, - p80211_metawep_t * p80211_wep); + struct sk_buff *skb, p80211_hdr_t *p80211_hdr, + p80211_metawep_t *p80211_wep); int p80211_stt_findproto(u16 proto); diff --git a/drivers/staging/wlan-ng/p80211metadef.h b/drivers/staging/wlan-ng/p80211metadef.h index da8b6f53c74f..0ccfba1294de 100644 --- a/drivers/staging/wlan-ng/p80211metadef.h +++ b/drivers/staging/wlan-ng/p80211metadef.h @@ -190,9 +190,9 @@ (P80211DID_MKSECTION(2) | \ P80211DID_MKGROUP(1)) #define DIDmib_dot11mac_dot11OperationTable_dot11MACAddress \ - (P80211DID_MKSECTION(2) | \ - P80211DID_MKGROUP(1) | \ - P80211DID_MKITEM(1) | 0x18000000) + (P80211DID_MKSECTION(2) | \ + P80211DID_MKGROUP(1) | \ + P80211DID_MKITEM(1) | 0x18000000) #define DIDmib_dot11mac_dot11OperationTable_dot11RTSThreshold \ (P80211DID_MKSECTION(2) | \ P80211DID_MKGROUP(1) | \ @@ -210,18 +210,18 @@ P80211DID_MKGROUP(1) | \ P80211DID_MKITEM(5) | 0x18000000) #define DIDmib_dot11mac_dot11OperationTable_dot11MaxTransmitMSDULifetime \ - (P80211DID_MKSECTION(2) | \ - P80211DID_MKGROUP(1) | \ - P80211DID_MKITEM(6) | 0x10000000) + (P80211DID_MKSECTION(2) | \ + P80211DID_MKGROUP(1) | \ + P80211DID_MKITEM(6) | 0x10000000) #define DIDmib_cat_dot11phy \ P80211DID_MKSECTION(3) #define DIDmib_dot11phy_dot11PhyOperationTable \ (P80211DID_MKSECTION(3) | \ P80211DID_MKGROUP(1)) #define DIDmib_dot11phy_dot11PhyTxPowerTable_dot11CurrentTxPowerLevel \ - (P80211DID_MKSECTION(3) | \ - P80211DID_MKGROUP(3) | \ - P80211DID_MKITEM(10) | 0x18000000) + (P80211DID_MKSECTION(3) | \ + P80211DID_MKGROUP(3) | \ + P80211DID_MKITEM(10) | 0x18000000) #define DIDmib_dot11phy_dot11PhyDSSSTable \ (P80211DID_MKSECTION(3) | \ P80211DID_MKGROUP(5)) diff --git a/drivers/staging/wlan-ng/p80211mgmt.h b/drivers/staging/wlan-ng/p80211mgmt.h index 14cdc86d1676..deb52f5fd780 100644 --- a/drivers/staging/wlan-ng/p80211mgmt.h +++ b/drivers/staging/wlan-ng/p80211mgmt.h @@ -100,7 +100,7 @@ #ifndef _P80211MGMT_H #define _P80211MGMT_H -#ifndef _P80211HDR_H +#ifndef _P80211HDR_H #include "p80211hdr.h" #endif @@ -496,25 +496,25 @@ typedef struct wlan_fr_deauthen { } wlan_fr_deauthen_t; -void wlan_mgmt_encode_beacon(wlan_fr_beacon_t * f); -void wlan_mgmt_decode_beacon(wlan_fr_beacon_t * f); -void wlan_mgmt_encode_disassoc(wlan_fr_disassoc_t * f); -void wlan_mgmt_decode_disassoc(wlan_fr_disassoc_t * f); -void wlan_mgmt_encode_assocreq(wlan_fr_assocreq_t * f); -void wlan_mgmt_decode_assocreq(wlan_fr_assocreq_t * f); -void wlan_mgmt_encode_assocresp(wlan_fr_assocresp_t * f); -void wlan_mgmt_decode_assocresp(wlan_fr_assocresp_t * f); -void wlan_mgmt_encode_reassocreq(wlan_fr_reassocreq_t * f); -void wlan_mgmt_decode_reassocreq(wlan_fr_reassocreq_t * f); -void wlan_mgmt_encode_reassocresp(wlan_fr_reassocresp_t * f); -void wlan_mgmt_decode_reassocresp(wlan_fr_reassocresp_t * f); -void wlan_mgmt_encode_probereq(wlan_fr_probereq_t * f); -void wlan_mgmt_decode_probereq(wlan_fr_probereq_t * f); -void wlan_mgmt_encode_proberesp(wlan_fr_proberesp_t * f); -void wlan_mgmt_decode_proberesp(wlan_fr_proberesp_t * f); -void wlan_mgmt_encode_authen(wlan_fr_authen_t * f); -void wlan_mgmt_decode_authen(wlan_fr_authen_t * f); -void wlan_mgmt_encode_deauthen(wlan_fr_deauthen_t * f); -void wlan_mgmt_decode_deauthen(wlan_fr_deauthen_t * f); +void wlan_mgmt_encode_beacon(wlan_fr_beacon_t *f); +void wlan_mgmt_decode_beacon(wlan_fr_beacon_t *f); +void wlan_mgmt_encode_disassoc(wlan_fr_disassoc_t *f); +void wlan_mgmt_decode_disassoc(wlan_fr_disassoc_t *f); +void wlan_mgmt_encode_assocreq(wlan_fr_assocreq_t *f); +void wlan_mgmt_decode_assocreq(wlan_fr_assocreq_t *f); +void wlan_mgmt_encode_assocresp(wlan_fr_assocresp_t *f); +void wlan_mgmt_decode_assocresp(wlan_fr_assocresp_t *f); +void wlan_mgmt_encode_reassocreq(wlan_fr_reassocreq_t *f); +void wlan_mgmt_decode_reassocreq(wlan_fr_reassocreq_t *f); +void wlan_mgmt_encode_reassocresp(wlan_fr_reassocresp_t *f); +void wlan_mgmt_decode_reassocresp(wlan_fr_reassocresp_t *f); +void wlan_mgmt_encode_probereq(wlan_fr_probereq_t *f); +void wlan_mgmt_decode_probereq(wlan_fr_probereq_t *f); +void wlan_mgmt_encode_proberesp(wlan_fr_proberesp_t *f); +void wlan_mgmt_decode_proberesp(wlan_fr_proberesp_t *f); +void wlan_mgmt_encode_authen(wlan_fr_authen_t *f); +void wlan_mgmt_decode_authen(wlan_fr_authen_t *f); +void wlan_mgmt_encode_deauthen(wlan_fr_deauthen_t *f); +void wlan_mgmt_decode_deauthen(wlan_fr_deauthen_t *f); #endif /* _P80211MGMT_H */ diff --git a/drivers/staging/wlan-ng/p80211netdev.c b/drivers/staging/wlan-ng/p80211netdev.c index 22424c8903ee..e27d72cf5714 100644 --- a/drivers/staging/wlan-ng/p80211netdev.c +++ b/drivers/staging/wlan-ng/p80211netdev.c @@ -646,7 +646,7 @@ static int p80211knetdev_set_mac_address(netdevice_t *dev, void *addr) /* Set up some convenience pointers. */ mibattr = &dot11req.mibattribute; - macaddr = (p80211item_pstr6_t *) & mibattr->data; + macaddr = (p80211item_pstr6_t *) &mibattr->data; resultcode = &dot11req.resultcode; /* Set up a dot11req_mibset */ @@ -674,7 +674,7 @@ static int p80211knetdev_set_mac_address(netdevice_t *dev, void *addr) resultcode->data = 0; /* now fire the request */ - result = p80211req_dorequest(dev->ml_priv, (u8 *) & dot11req); + result = p80211req_dorequest(dev->ml_priv, (u8 *) &dot11req); /* If the request wasn't successful, report an error and don't * change the netdev address diff --git a/drivers/staging/wlan-ng/p80211netdev.h b/drivers/staging/wlan-ng/p80211netdev.h index 8bd9dfb3b9b4..3c8c64800567 100644 --- a/drivers/staging/wlan-ng/p80211netdev.h +++ b/drivers/staging/wlan-ng/p80211netdev.h @@ -179,16 +179,16 @@ typedef struct wlandevice { unsigned int ethconv; /* device methods (init by MSD, used by p80211 */ - int (*open) (struct wlandevice * wlandev); - int (*close) (struct wlandevice * wlandev); - void (*reset) (struct wlandevice * wlandev); - int (*txframe) (struct wlandevice * wlandev, struct sk_buff * skb, - p80211_hdr_t * p80211_hdr, - p80211_metawep_t * p80211_wep); - int (*mlmerequest) (struct wlandevice * wlandev, p80211msg_t * msg); - int (*set_multicast_list) (struct wlandevice * wlandev, - netdevice_t * dev); - void (*tx_timeout) (struct wlandevice * wlandev); + int (*open) (struct wlandevice *wlandev); + int (*close) (struct wlandevice *wlandev); + void (*reset) (struct wlandevice *wlandev); + int (*txframe) (struct wlandevice *wlandev, struct sk_buff *skb, + p80211_hdr_t *p80211_hdr, + p80211_metawep_t *p80211_wep); + int (*mlmerequest) (struct wlandevice *wlandev, p80211msg_t *msg); + int (*set_multicast_list) (struct wlandevice *wlandev, + netdevice_t *dev); + void (*tx_timeout) (struct wlandevice *wlandev); /* 802.11 State */ u8 bssid[WLAN_BSSID_LEN]; @@ -227,16 +227,16 @@ typedef struct wlandevice { } wlandevice_t; /* WEP stuff */ -int wep_change_key(wlandevice_t * wlandev, int keynum, u8 * key, int keylen); -int wep_decrypt(wlandevice_t * wlandev, u8 * buf, u32 len, int key_override, - u8 * iv, u8 * icv); -int wep_encrypt(wlandevice_t * wlandev, u8 * buf, u8 * dst, u32 len, int keynum, - u8 * iv, u8 * icv); - -int wlan_setup(wlandevice_t * wlandev); -int wlan_unsetup(wlandevice_t * wlandev); -int register_wlandev(wlandevice_t * wlandev); -int unregister_wlandev(wlandevice_t * wlandev); -void p80211netdev_rx(wlandevice_t * wlandev, struct sk_buff *skb); -void p80211netdev_hwremoved(wlandevice_t * wlandev); +int wep_change_key(wlandevice_t *wlandev, int keynum, u8 *key, int keylen); +int wep_decrypt(wlandevice_t *wlandev, u8 *buf, u32 len, int key_override, + u8 *iv, u8 *icv); +int wep_encrypt(wlandevice_t *wlandev, u8 *buf, u8 *dst, u32 len, int keynum, + u8 *iv, u8 *icv); + +int wlan_setup(wlandevice_t *wlandev); +int wlan_unsetup(wlandevice_t *wlandev); +int register_wlandev(wlandevice_t *wlandev); +int unregister_wlandev(wlandevice_t *wlandev); +void p80211netdev_rx(wlandevice_t *wlandev, struct sk_buff *skb); +void p80211netdev_hwremoved(wlandevice_t *wlandev); #endif diff --git a/drivers/staging/wlan-ng/p80211req.c b/drivers/staging/wlan-ng/p80211req.c index c88156cdf681..c2e95f166828 100644 --- a/drivers/staging/wlan-ng/p80211req.c +++ b/drivers/staging/wlan-ng/p80211req.c @@ -94,7 +94,7 @@ static int p80211req_mibset_mibget(wlandevice_t *wlandev, * Potentially blocks the caller, so it's a good idea to * not call this function from an interrupt context. ----------------------------------------------------------------*/ -int p80211req_dorequest(wlandevice_t * wlandev, u8 * msgbuf) +int p80211req_dorequest(wlandevice_t *wlandev, u8 *msgbuf) { int result = 0; p80211msg_t *msg = (p80211msg_t *) msgbuf; diff --git a/drivers/staging/wlan-ng/p80211req.h b/drivers/staging/wlan-ng/p80211req.h index 5d9176762ba7..a95a45a6814d 100644 --- a/drivers/staging/wlan-ng/p80211req.h +++ b/drivers/staging/wlan-ng/p80211req.h @@ -48,6 +48,6 @@ #ifndef _LINUX_P80211REQ_H #define _LINUX_P80211REQ_H -int p80211req_dorequest(wlandevice_t * wlandev, u8 * msgbuf); +int p80211req_dorequest(wlandevice_t *wlandev, u8 *msgbuf); #endif diff --git a/drivers/staging/wlan-ng/p80211types.h b/drivers/staging/wlan-ng/p80211types.h index 2b83ab0c711b..db235517df92 100644 --- a/drivers/staging/wlan-ng/p80211types.h +++ b/drivers/staging/wlan-ng/p80211types.h @@ -168,10 +168,10 @@ P80211DID_MASK_ISTABLE, \ P80211DID_LSB_ISTABLE) -#define P80211DID_MKID(s,g,i,n,t,a) (P80211DID_MKSECTION(s) | \ +#define P80211DID_MKID(s, g, i, n, t, a) (P80211DID_MKSECTION(s) | \ P80211DID_MKGROUP(g) | \ - P80211DID_MKITEM(i) | \ - P80211DID_MKINDEX(n) | \ + P80211DID_MKITEM(i) | \ + P80211DID_MKINDEX(n) | \ P80211DID_MKISTABLE(t) | \ (a)) @@ -340,11 +340,11 @@ struct catlistitem; /* metadata items. Some components may choose to use more, */ /* less or different metadata items. */ -typedef void (*p80211_totext_t) (struct catlistitem *, u32 did, u8 * itembuf, +typedef void (*p80211_totext_t) (struct catlistitem *, u32 did, u8 *itembuf, char *textbuf); -typedef void (*p80211_fromtext_t) (struct catlistitem *, u32 did, u8 * itembuf, +typedef void (*p80211_fromtext_t) (struct catlistitem *, u32 did, u8 *itembuf, char *textbuf); -typedef u32(*p80211_valid_t) (struct catlistitem *, u32 did, u8 * itembuf); +typedef u32(*p80211_valid_t) (struct catlistitem *, u32 did, u8 *itembuf); /*----------------------------------------------------------------*/ /* Enumeration Lists */ diff --git a/drivers/staging/wlan-ng/p80211wext.c b/drivers/staging/wlan-ng/p80211wext.c index 74d8022adb24..040c9e3e1d51 100644 --- a/drivers/staging/wlan-ng/p80211wext.c +++ b/drivers/staging/wlan-ng/p80211wext.c @@ -46,8 +46,8 @@ #include #include #include -#include -#include +#include +#include #include #include #include @@ -137,7 +137,7 @@ static int p80211wext_dorequest(wlandevice_t *wlandev, u32 did, u32 data) mibitem.did = did; mibitem.data = data; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); return result; } @@ -174,7 +174,7 @@ static int p80211wext_autojoin(wlandevice_t *wlandev) memcpy(msg.ssid.data.data, ssid, data.length); msg.ssid.data.len = data.length; - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -211,7 +211,7 @@ struct iw_statistics *p80211wext_get_wireless_stats(netdevice_t *dev) if (wlandev->mlmerequest == NULL) return NULL; - retval = wlandev->mlmerequest(wlandev, (p80211msg_t *) & quality); + retval = wlandev->mlmerequest(wlandev, (p80211msg_t *) &quality); wstats->qual.qual = qual_as_percent(quality.link.data); /* overall link quality */ wstats->qual.level = quality.level.data; /* instant signal level */ @@ -271,7 +271,7 @@ static int p80211wext_giwfreq(netdevice_t *dev, msg.msgcode = DIDmsg_dot11req_mibget; mibitem.did = DIDmib_dot11phy_dot11PhyDSSSTable_dot11CurrentChannel; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -318,7 +318,7 @@ static int p80211wext_siwfreq(netdevice_t *dev, mibitem.data = p80211_mhz_to_channel(freq->m); memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -399,7 +399,7 @@ static int p80211wext_siwmode(netdevice_t *dev, mibitem.did = DIDmib_p2_p2Static_p2CnfPortType; mibitem.data = (*mode == IW_MODE_ADHOC) ? 0 : 1; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) err = -EFAULT; @@ -621,7 +621,7 @@ static int p80211wext_siwencode(netdevice_t *dev, msg.msgcode = DIDmsg_dot11req_mibset; memcpy(&msg.mibattribute.data, &pstr, sizeof(pstr)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -729,7 +729,7 @@ static int p80211wext_siwessid(netdevice_t *dev, msg.ssid.data.len = length; pr_debug("autojoin_ssid for %s \n", essid); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); pr_debug("autojoin_ssid %d\n", result); if (result) { @@ -773,7 +773,7 @@ static int p80211wext_giwrate(netdevice_t *dev, msg.msgcode = DIDmsg_dot11req_mibget; mibitem.did = DIDmib_p2_p2MAC_p2CurrentTxRate; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -824,7 +824,7 @@ static int p80211wext_giwrts(netdevice_t *dev, msg.msgcode = DIDmsg_dot11req_mibget; mibitem.did = DIDmib_dot11mac_dot11OperationTable_dot11RTSThreshold; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -864,7 +864,7 @@ static int p80211wext_siwrts(netdevice_t *dev, mibitem.data = rts->value; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -889,7 +889,7 @@ static int p80211wext_giwfrag(netdevice_t *dev, mibitem.did = DIDmib_dot11mac_dot11OperationTable_dot11FragmentationThreshold; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -931,7 +931,7 @@ static int p80211wext_siwfrag(netdevice_t *dev, mibitem.data = frag->value; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -965,7 +965,7 @@ static int p80211wext_giwretry(netdevice_t *dev, mibitem.did = DIDmib_dot11mac_dot11OperationTable_dot11ShortRetryLimit; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -979,7 +979,7 @@ static int p80211wext_giwretry(netdevice_t *dev, mibitem.did = DIDmib_dot11mac_dot11OperationTable_dot11LongRetryLimit; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -994,7 +994,7 @@ static int p80211wext_giwretry(netdevice_t *dev, DIDmib_dot11mac_dot11OperationTable_dot11MaxTransmitMSDULifetime; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -1055,7 +1055,7 @@ static int p80211wext_siwretry(netdevice_t *dev, mibitem.data = rrq->value /= 1024; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -1069,7 +1069,7 @@ static int p80211wext_siwretry(netdevice_t *dev, memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -1084,7 +1084,7 @@ static int p80211wext_siwretry(netdevice_t *dev, memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -1121,7 +1121,7 @@ static int p80211wext_siwtxpow(netdevice_t *dev, else mibitem.data = rrq->value; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -1147,7 +1147,7 @@ static int p80211wext_giwtxpow(netdevice_t *dev, DIDmib_dot11phy_dot11PhyTxPowerTable_dot11CurrentTxPowerLevel; memcpy(&msg.mibattribute.data, &mibitem, sizeof(mibitem)); - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) { err = -EFAULT; @@ -1295,7 +1295,7 @@ static int p80211wext_siwscan(netdevice_t *dev, msg.maxchanneltime.data = 250; msg.minchanneltime.data = 200; - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if (result) err = prism2_result2err(msg.resultcode.data); @@ -1414,7 +1414,7 @@ static int p80211wext_giwscan(netdevice_t *dev, msg.msgcode = DIDmsg_dot11req_scan_results; msg.bssindex.data = i; - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); if ((result != 0) || (msg.resultcode.data != P80211ENUM_resultcode_success)) { break; @@ -1489,7 +1489,7 @@ static int p80211wext_set_encodeext(struct net_device *dev, memcpy(wlandev->wep_keys[idx], ext->key, ext->key_len); memset(&msg, 0, sizeof(msg)); - pstr = (p80211item_pstr32_t *) & msg.mibattribute.data; + pstr = (p80211item_pstr32_t *) &msg.mibattribute.data; memcpy(pstr->data.data, ext->key, ext->key_len); pstr->data.len = ext->key_len; switch (idx) { @@ -1513,7 +1513,7 @@ static int p80211wext_set_encodeext(struct net_device *dev, break; } msg.msgcode = DIDmsg_dot11req_mibset; - result = p80211req_dorequest(wlandev, (u8 *) & msg); + result = p80211req_dorequest(wlandev, (u8 *) &msg); pr_debug("result (%d)\n", result); } return result; @@ -1737,7 +1737,7 @@ struct iw_handler_def p80211wext_handler_def = { .get_wireless_stats = p80211wext_get_wireless_stats }; -int p80211wext_event_associated(wlandevice_t * wlandev, int assoc) +int p80211wext_event_associated(wlandevice_t *wlandev, int assoc) { union iwreq_data data; diff --git a/drivers/staging/wlan-ng/prism2fw.c b/drivers/staging/wlan-ng/prism2fw.c index aaa70ed57710..343614561f4c 100644 --- a/drivers/staging/wlan-ng/prism2fw.c +++ b/drivers/staging/wlan-ng/prism2fw.c @@ -108,9 +108,9 @@ typedef struct pda { } pda_t; typedef struct imgchunk { - u32 addr; /* start address */ - u32 len; /* in bytes */ - u16 crc; /* CRC value (if it falls at a chunk boundary) */ + u32 addr; /* start address */ + u32 len; /* in bytes */ + u16 crc; /* CRC value (if it falls at a chunk boundary) */ u8 *data; } imgchunk_t; @@ -264,7 +264,7 @@ int prism2_fwapply(const struct ihex_binrec *rfptr, wlandevice_t *wlandev) /* Build the PDA we're going to use. */ if (read_cardpda(&pda, wlandev)) { printk(KERN_ERR "load_cardpda failed, exiting.\n"); - return (1); + return 1; } /* read the card's PRI-SUP */ @@ -286,9 +286,8 @@ int prism2_fwapply(const struct ihex_binrec *rfptr, wlandevice_t *wlandev) /* DIDmsg_dot11req_mibget */ prism2mgmt_mibset_mibget(wlandev, &getmsg); - if (getmsg.resultcode.data != P80211ENUM_resultcode_success) { + if (getmsg.resultcode.data != P80211ENUM_resultcode_success) printk(KERN_ERR "Couldn't fetch PRI-SUP info\n"); - } /* Already in host order */ priid.role = *data++; @@ -301,19 +300,19 @@ int prism2_fwapply(const struct ihex_binrec *rfptr, wlandevice_t *wlandev) result = read_fwfile(rfptr); if (result) { printk(KERN_ERR "Failed to read the data exiting.\n"); - return (1); + return 1; } result = validate_identity(); if (result) { printk(KERN_ERR "Incompatible firmware image.\n"); - return (1); + return 1; } if (startaddr == 0x00000000) { printk(KERN_ERR "Can't RAM download a Flash image!\n"); - return (1); + return 1; } /* Make the image chunks */ @@ -323,20 +322,20 @@ int prism2_fwapply(const struct ihex_binrec *rfptr, wlandevice_t *wlandev) result = plugimage(fchunk, nfchunks, s3plug, ns3plug, &pda); if (result) { printk(KERN_ERR "Failed to plug data.\n"); - return (1); + return 1; } /* Insert any CRCs */ if (crcimage(fchunk, nfchunks, s3crc, ns3crc)) { printk(KERN_ERR "Failed to insert all CRCs\n"); - return (1); + return 1; } /* Write the image */ result = writeimage(wlandev, fchunk, nfchunks); if (result) { printk(KERN_ERR "Failed to ramwrite image data.\n"); - return (1); + return 1; } /* clear any allocated memory */ @@ -434,9 +433,8 @@ void free_chunks(imgchunk_t *fchunk, unsigned int *nfchunks) { int i; for (i = 0; i < *nfchunks; i++) { - if (fchunk[i].data != NULL) { + if (fchunk[i].data != NULL) kfree(fchunk[i].data); - } } *nfchunks = 0; memset(fchunk, 0, sizeof(*fchunk)); @@ -531,7 +529,7 @@ int mkimage(imgchunk_t *clist, unsigned int *ccnt) if (clist[i].data == NULL) { printk(KERN_ERR "failed to allocate image space, exitting.\n"); - return (1); + return 1; } memset(clist[i].data, 0, clist[i].len); pr_debug("chunk[%d]: addr=0x%06x len=%d\n", @@ -545,15 +543,14 @@ int mkimage(imgchunk_t *clist, unsigned int *ccnt) for (j = 0; j < *ccnt; j++) { cstart = clist[j].addr; cend = cstart + clist[j].len - 1; - if (s3start >= cstart && s3end <= cend) { + if (s3start >= cstart && s3end <= cend) break; - } } if (((unsigned int)j) >= (*ccnt)) { printk(KERN_ERR "s3rec(a=0x%06x,l=%d), no chunk match, exiting.\n", s3start, s3data[i].len); - return (1); + return 1; } coffset = s3start - cstart; memcpy(clist[j].data + coffset, s3data[i].data, s3data[i].len); @@ -586,7 +583,7 @@ int mkpdrlist(pda_t *pda) curroff = 0; while (curroff < (HFA384x_PDA_LEN_MAX / 2) && le16_to_cpu(pda16[curroff + 1]) != HFA384x_PDR_END_OF_PDA) { - pda->rec[pda->nrec] = (hfa384x_pdrec_t *) & (pda16[curroff]); + pda->rec[pda->nrec] = (hfa384x_pdrec_t *) &(pda16[curroff]); if (le16_to_cpu(pda->rec[pda->nrec]->code) == HFA384x_PDR_NICID) { memcpy(&nicid, &pda->rec[pda->nrec]->data.nicid, @@ -623,10 +620,10 @@ int mkpdrlist(pda_t *pda) printk(KERN_ERR "no end record found or invalid lengths in " "PDR data, exiting. %x %d\n", curroff, pda->nrec); - return (1); + return 1; } if (le16_to_cpu(pda16[curroff + 1]) == HFA384x_PDR_END_OF_PDA) { - pda->rec[pda->nrec] = (hfa384x_pdrec_t *) & (pda16[curroff]); + pda->rec[pda->nrec] = (hfa384x_pdrec_t *) &(pda16[curroff]); (pda->nrec)++; } return result; @@ -869,7 +866,7 @@ int read_fwfile(const struct ihex_binrec *record) ptr16 = (u16 *) record->data; /* parse what was an S3 srec and put it in the right array */ - switch(addr) { + switch (addr) { case S3ADDR_START: startaddr = *ptr32; pr_debug(" S7 start addr, record=%d " @@ -890,7 +887,7 @@ int read_fwfile(const struct ihex_binrec *record) s3plug[ns3plug].len); ns3plug++; - if ( ns3plug == S3PLUG_MAX ) { + if (ns3plug == S3PLUG_MAX) { printk(KERN_ERR "S3 plugrec limit reached - aborting\n"); return 1; } @@ -907,7 +904,7 @@ int read_fwfile(const struct ihex_binrec *record) s3crc[ns3crc].len, s3crc[ns3crc].dowrite); ns3crc++; - if ( ns3crc == S3CRC_MAX ) { + if (ns3crc == S3CRC_MAX) { printk(KERN_ERR "S3 crcrec limit reached - aborting\n"); return 1; } @@ -921,12 +918,12 @@ int read_fwfile(const struct ihex_binrec *record) rcnt, s3info[ns3info].len, s3info[ns3info].type); - if ( ((s3info[ns3info].len - 1) * sizeof(u16)) > sizeof(s3info[ns3info].info) ) { + if (((s3info[ns3info].len - 1) * sizeof(u16)) > sizeof(s3info[ns3info].info)) { printk(KERN_ERR " S3 inforec length too long - aborting\n"); return 1; } - tmpinfo = (u16*)&(s3info[ns3info].info.version); + tmpinfo = (u16 *)&(s3info[ns3info].info.version); pr_debug(" info="); for (i = 0; i < s3info[ns3info].len - 1; i++) { tmpinfo[i] = *(ptr16 + 2 + i); @@ -935,7 +932,7 @@ int read_fwfile(const struct ihex_binrec *record) pr_debug("\n"); ns3info++; - if ( ns3info == S3INFO_MAX ) { + if (ns3info == S3INFO_MAX) { printk(KERN_ERR "S3 inforec limit reached - aborting\n"); return 1; } @@ -945,7 +942,7 @@ int read_fwfile(const struct ihex_binrec *record) s3data[ns3data].len = len; s3data[ns3data].data = (uint8_t *) record->data; ns3data++; - if ( ns3data == S3DATA_MAX ) { + if (ns3data == S3DATA_MAX) { printk(KERN_ERR "S3 datarec limit reached - aborting\n"); return 1; } @@ -1023,7 +1020,7 @@ int writeimage(wlandevice_t *wlandev, imgchunk_t *fchunk, rstatemsg.enable.data = P80211ENUM_truth_true; rstatemsg.exeaddr.data = startaddr; - msgp = (p80211msg_t *) & rstatemsg; + msgp = (p80211msg_t *) &rstatemsg; result = prism2mgmt_ramdl_state(wlandev, msgp); if (result) { printk(KERN_ERR @@ -1063,7 +1060,7 @@ int writeimage(wlandevice_t *wlandev, imgchunk_t *fchunk, ("Sending xxxdl_write message addr=%06x len=%d.\n", currdaddr, currlen); - msgp = (p80211msg_t *) & rwritemsg; + msgp = (p80211msg_t *) &rwritemsg; result = prism2mgmt_ramdl_write(wlandev, msgp); /* Check the results */ @@ -1090,7 +1087,7 @@ int writeimage(wlandevice_t *wlandev, imgchunk_t *fchunk, rstatemsg.enable.data = P80211ENUM_truth_false; rstatemsg.exeaddr.data = 0; - msgp = (p80211msg_t *) & rstatemsg; + msgp = (p80211msg_t *) &rstatemsg; result = prism2mgmt_ramdl_state(wlandev, msgp); if (result) { printk(KERN_ERR @@ -1160,10 +1157,7 @@ int validate_identity(void) } /* SEC compat range */ if ((s3info[i].info.compat.role == 1) && - (s3info[i].info.compat.id == 4)) { - - } - + (s3info[i].info.compat.id == 4)) break; case 3: pr_debug("Seq: %#x\n", s3info[i].info.buildseq); @@ -1196,8 +1190,9 @@ int validate_identity(void) pr_debug("Unknown inforec type %d\n", s3info[i].type); } } - // walk through + /* walk through */ - if (trump && (result != 2)) result = 0; + if (trump && (result != 2)) + result = 0; return result; } diff --git a/drivers/staging/wlan-ng/prism2mgmt.c b/drivers/staging/wlan-ng/prism2mgmt.c index 9f7d96cae8e3..ad163da72ae4 100644 --- a/drivers/staging/wlan-ng/prism2mgmt.c +++ b/drivers/staging/wlan-ng/prism2mgmt.c @@ -67,7 +67,7 @@ #include #include #include -#include +#include #include #include #include @@ -541,7 +541,7 @@ int prism2mgmt_start(wlandevice_t *wlandev, void *msgp) /*** STATION ***/ /* Set the REQUIRED config items */ /* SSID */ - pstr = (p80211pstrd_t *) & (msg->ssid.data); + pstr = (p80211pstrd_t *) &(msg->ssid.data); prism2mgmt_pstr2bytestr(p2bytestr, pstr); result = hfa384x_drvr_setconfig(hw, HFA384x_RID_CNFOWNSSID, bytebuf, HFA384x_RID_CNFOWNSSID_LEN); @@ -1034,7 +1034,7 @@ int prism2mgmt_autojoin(wlandevice_t *wlandev, void *msgp) /* Set the ssid */ memset(bytebuf, 0, 256); - pstr = (p80211pstrd_t *) & (msg->ssid.data); + pstr = (p80211pstrd_t *) &(msg->ssid.data); prism2mgmt_pstr2bytestr(p2bytestr, pstr); result = hfa384x_drvr_setconfig(hw, HFA384x_RID_CNFDESIREDSSID, bytebuf, @@ -1123,8 +1123,8 @@ int prism2mgmt_wlansniff(wlandevice_t *wlandev, void *msgp) if (hw->presniff_port_type != 0) { word = hw->presniff_port_type; result = hfa384x_drvr_setconfig16(hw, - HFA384x_RID_CNFPORTTYPE, - word); + HFA384x_RID_CNFPORTTYPE, + word); if (result) { pr_debug ("failed to restore porttype, result=%d\n", @@ -1156,10 +1156,8 @@ int prism2mgmt_wlansniff(wlandevice_t *wlandev, void *msgp) if (wlandev->netdev->type == ARPHRD_ETHER) { /* Save macport 0 state */ result = hfa384x_drvr_getconfig16(hw, - HFA384x_RID_CNFPORTTYPE, - & - (hw-> - presniff_port_type)); + HFA384x_RID_CNFPORTTYPE, + &(hw->presniff_port_type)); if (result) { pr_debug ("failed to read porttype, result=%d\n", @@ -1168,10 +1166,8 @@ int prism2mgmt_wlansniff(wlandevice_t *wlandev, void *msgp) } /* Save the wepflags state */ result = hfa384x_drvr_getconfig16(hw, - HFA384x_RID_CNFWEPFLAGS, - & - (hw-> - presniff_wepflags)); + HFA384x_RID_CNFWEPFLAGS, + &(hw->presniff_wepflags)); if (result) { pr_debug ("failed to read wepflags, result=%d\n", @@ -1218,8 +1214,8 @@ int prism2mgmt_wlansniff(wlandevice_t *wlandev, void *msgp) /* Set the port type to pIbss */ word = HFA384x_PORTTYPE_PSUEDOIBSS; result = hfa384x_drvr_setconfig16(hw, - HFA384x_RID_CNFPORTTYPE, - word); + HFA384x_RID_CNFPORTTYPE, + word); if (result) { pr_debug ("failed to set porttype %d, result=%d\n", @@ -1235,8 +1231,8 @@ int prism2mgmt_wlansniff(wlandevice_t *wlandev, void *msgp) HFA384x_WEPFLAGS_DISABLE_RXCRYPT; result = hfa384x_drvr_setconfig16(hw, - HFA384x_RID_CNFWEPFLAGS, - word); + HFA384x_RID_CNFWEPFLAGS, + word); } if (result) { diff --git a/drivers/staging/wlan-ng/prism2mgmt.h b/drivers/staging/wlan-ng/prism2mgmt.h index bdf2b3e03253..07eecebeb6cc 100644 --- a/drivers/staging/wlan-ng/prism2mgmt.h +++ b/drivers/staging/wlan-ng/prism2mgmt.h @@ -63,43 +63,43 @@ extern int prism2_reset_holdtime; extern int prism2_reset_settletime; -u32 prism2sta_ifstate(wlandevice_t * wlandev, u32 ifstate); +u32 prism2sta_ifstate(wlandevice_t *wlandev, u32 ifstate); -void prism2sta_ev_info(wlandevice_t * wlandev, hfa384x_InfFrame_t * inf); -void prism2sta_ev_txexc(wlandevice_t * wlandev, u16 status); -void prism2sta_ev_tx(wlandevice_t * wlandev, u16 status); -void prism2sta_ev_rx(wlandevice_t * wlandev, struct sk_buff *skb); -void prism2sta_ev_alloc(wlandevice_t * wlandev); +void prism2sta_ev_info(wlandevice_t *wlandev, hfa384x_InfFrame_t *inf); +void prism2sta_ev_txexc(wlandevice_t *wlandev, u16 status); +void prism2sta_ev_tx(wlandevice_t *wlandev, u16 status); +void prism2sta_ev_rx(wlandevice_t *wlandev, struct sk_buff *skb); +void prism2sta_ev_alloc(wlandevice_t *wlandev); -int prism2mgmt_mibset_mibget(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_scan(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_scan_results(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_start(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_wlansniff(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_readpda(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_ramdl_state(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_ramdl_write(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_flashdl_state(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_flashdl_write(wlandevice_t * wlandev, void *msgp); -int prism2mgmt_autojoin(wlandevice_t * wlandev, void *msgp); +int prism2mgmt_mibset_mibget(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_scan(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_scan_results(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_start(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_wlansniff(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_readpda(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_ramdl_state(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_ramdl_write(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_flashdl_state(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_flashdl_write(wlandevice_t *wlandev, void *msgp); +int prism2mgmt_autojoin(wlandevice_t *wlandev, void *msgp); /*--------------------------------------------------------------- * conversion functions going between wlan message data types and * Prism2 data types ---------------------------------------------------------------*/ /* byte area conversion functions*/ -void prism2mgmt_pstr2bytearea(u8 * bytearea, p80211pstrd_t * pstr); -void prism2mgmt_bytearea2pstr(u8 * bytearea, p80211pstrd_t * pstr, int len); +void prism2mgmt_pstr2bytearea(u8 *bytearea, p80211pstrd_t *pstr); +void prism2mgmt_bytearea2pstr(u8 *bytearea, p80211pstrd_t *pstr, int len); /* byte string conversion functions*/ -void prism2mgmt_pstr2bytestr(hfa384x_bytestr_t * bytestr, p80211pstrd_t * pstr); -void prism2mgmt_bytestr2pstr(hfa384x_bytestr_t * bytestr, p80211pstrd_t * pstr); +void prism2mgmt_pstr2bytestr(hfa384x_bytestr_t *bytestr, p80211pstrd_t *pstr); +void prism2mgmt_bytestr2pstr(hfa384x_bytestr_t *bytestr, p80211pstrd_t *pstr); /* functions to convert Group Addresses */ -void prism2mgmt_get_grpaddr(u32 did, p80211pstrd_t * pstr, hfa384x_t * priv); +void prism2mgmt_get_grpaddr(u32 did, p80211pstrd_t *pstr, hfa384x_t *priv); int prism2mgmt_set_grpaddr(u32 did, - u8 * prism2buf, p80211pstrd_t * pstr, - hfa384x_t * priv); + u8 *prism2buf, p80211pstrd_t *pstr, + hfa384x_t *priv); int prism2mgmt_get_grpaddr_index(u32 did); void prism2sta_processing_defer(struct work_struct *data); diff --git a/drivers/staging/wlan-ng/prism2mib.c b/drivers/staging/wlan-ng/prism2mib.c index 2fff0a110bcb..0cbbe510307e 100644 --- a/drivers/staging/wlan-ng/prism2mib.c +++ b/drivers/staging/wlan-ng/prism2mib.c @@ -113,8 +113,7 @@ static int prism2mib_flag(mibrec_t *mib, p80211msg_dot11req_mibset_t *msg, void *data); static int prism2mib_wepdefaultkey(mibrec_t *mib, - int isget, - wlandevice_t * wlandev, + int isget, wlandevice_t *wlandev, hfa384x_t *hw, p80211msg_dot11req_mibset_t *msg, void *data); @@ -726,7 +725,7 @@ static int prism2mib_priv(mibrec_t *mib, if (isget) { hfa384x_drvr_getconfig(hw, HFA384x_RID_CNFWPADATA, - (u8 *) & wpa, + (u8 *) &wpa, sizeof(wpa)); pstr->len = le16_to_cpu(wpa.datalen); memcpy(pstr->data, wpa.data, pstr->len); @@ -736,9 +735,9 @@ static int prism2mib_priv(mibrec_t *mib, result = hfa384x_drvr_setconfig(hw, - HFA384x_RID_CNFWPADATA, - (u8 *) & wpa, - sizeof(wpa)); + HFA384x_RID_CNFWPADATA, + (u8 *) &wpa, + sizeof(wpa)); } break; } diff --git a/drivers/staging/wlan-ng/prism2sta.c b/drivers/staging/wlan-ng/prism2sta.c index 50f301d65212..32a3db854625 100644 --- a/drivers/staging/wlan-ng/prism2sta.c +++ b/drivers/staging/wlan-ng/prism2sta.c @@ -64,7 +64,7 @@ #include #include -#include +#include #include #include #include @@ -1023,13 +1023,13 @@ static void prism2sta_inf_tallies(wlandevice_t *wlandev, cnt = sizeof(hfa384x_CommTallies32_t) / sizeof(u32); if (inf->framelen > 22) { - dst = (u32 *) & hw->tallies; - src32 = (u32 *) & inf->info.commtallies32; + dst = (u32 *) &hw->tallies; + src32 = (u32 *) &inf->info.commtallies32; for (i = 0; i < cnt; i++, dst++, src32++) *dst += le32_to_cpu(*src32); } else { - dst = (u32 *) & hw->tallies; - src16 = (u16 *) & inf->info.commtallies16; + dst = (u32 *) &hw->tallies; + src16 = (u16 *) &inf->info.commtallies16; for (i = 0; i < cnt; i++, dst++, src16++) *dst += le16_to_cpu(*src16); } @@ -1280,9 +1280,8 @@ void prism2sta_processing_defer(struct work_struct *data) HFA384x_RID_CURRENTSSID, result); goto failed; } - prism2mgmt_bytestr2pstr((hfa384x_bytestr_t *) & ssid, - (p80211pstrd_t *) & - wlandev->ssid); + prism2mgmt_bytestr2pstr((hfa384x_bytestr_t *) &ssid, + (p80211pstrd_t *) &wlandev->ssid); /* Collect the port status */ result = hfa384x_drvr_getconfig16(hw, @@ -1368,8 +1367,8 @@ void prism2sta_processing_defer(struct work_struct *data) HFA384x_RID_CURRENTSSID, result); goto failed; } - prism2mgmt_bytestr2pstr((hfa384x_bytestr_t *) & ssid, - (p80211pstrd_t *) & wlandev->ssid); + prism2mgmt_bytestr2pstr((hfa384x_bytestr_t *) &ssid, + (p80211pstrd_t *) &wlandev->ssid); hw->link_status = HFA384x_LINK_CONNECTED; netif_carrier_on(wlandev->netdev); @@ -2028,8 +2027,8 @@ void prism2sta_commsqual_defer(struct work_struct *data) HFA384x_RID_CURRENTSSID, result); goto done; } - prism2mgmt_bytestr2pstr((hfa384x_bytestr_t *) & ssid, - (p80211pstrd_t *) & wlandev->ssid); + prism2mgmt_bytestr2pstr((hfa384x_bytestr_t *) &ssid, + (p80211pstrd_t *) &wlandev->ssid); /* Reschedule timer */ mod_timer(&hw->commsqual_timer, jiffies + HZ); -- cgit v1.2.3 From 3f4b4e779714ae2dd55757617a8033ab338fa7f0 Mon Sep 17 00:00:00 2001 From: Andrew Elwell Date: Thu, 18 Feb 2010 23:56:13 +0100 Subject: Staging: wlan-ng: More checkpatch.pl error cleanups Signed-off-by: Andrew Elwell Signed-off-by: Greg Kroah-Hartman --- drivers/staging/wlan-ng/hfa384x_usb.c | 28 +++++++++++++++------------- drivers/staging/wlan-ng/p80211conv.c | 14 +++++++------- drivers/staging/wlan-ng/p80211netdev.c | 3 ++- drivers/staging/wlan-ng/p80211wext.c | 8 ++++---- 4 files changed, 28 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/wlan-ng/hfa384x_usb.c b/drivers/staging/wlan-ng/hfa384x_usb.c index 730d085c3f87..d3a85f249e96 100644 --- a/drivers/staging/wlan-ng/hfa384x_usb.c +++ b/drivers/staging/wlan-ng/hfa384x_usb.c @@ -1909,18 +1909,19 @@ int hfa384x_drvr_flashdl_enable(hfa384x_t *hw) return -EINVAL; /* Retrieve the buffer loc&size and timeout */ - if ((result = hfa384x_drvr_getconfig(hw, HFA384x_RID_DOWNLOADBUFFER, - &(hw->bufinfo), - sizeof(hw->bufinfo)))) { + result = hfa384x_drvr_getconfig(hw, HFA384x_RID_DOWNLOADBUFFER, + &(hw->bufinfo), sizeof(hw->bufinfo)); + if (result) return result; - } + hw->bufinfo.page = le16_to_cpu(hw->bufinfo.page); hw->bufinfo.offset = le16_to_cpu(hw->bufinfo.offset); hw->bufinfo.len = le16_to_cpu(hw->bufinfo.len); - if ((result = hfa384x_drvr_getconfig16(hw, HFA384x_RID_MAXLOADTIME, - &(hw->dltimeout)))) { + result = hfa384x_drvr_getconfig16(hw, HFA384x_RID_MAXLOADTIME, + &(hw->dltimeout)); + if (result) return result; - } + hw->dltimeout = le16_to_cpu(hw->dltimeout); pr_debug("flashdl_enable\n"); @@ -3071,9 +3072,9 @@ static void hfa384x_usbctlxq_run(hfa384x_t *hw) hfa384x_ctlxout_callback, hw); hw->ctlx_urb.transfer_flags |= USB_QUEUE_BULK; - /* Now submit the URB and update the CTLX's state - */ - if ((result = SUBMIT_URB(&hw->ctlx_urb, GFP_ATOMIC)) == 0) { + /* Now submit the URB and update the CTLX's state */ + result = SUBMIT_URB(&hw->ctlx_urb, GFP_ATOMIC); + if (result == 0) { /* This CTLX is now running on the active queue */ head->state = CTLX_REQ_SUBMITTED; @@ -3599,7 +3600,8 @@ static void hfa384x_int_rxmonitor(wlandevice_t *wlandev, skblen - sizeof(p80211_caphdr_t)); } - if ((skb = dev_alloc_skb(skblen)) == NULL) { + skb = dev_alloc_skb(skblen); + if (skb == NULL) { printk(KERN_ERR "alloc_skb failed trying to allocate %d bytes\n", skblen); @@ -3870,9 +3872,9 @@ retry: delresp: if (delete_resptimer) { - if ((timer_ok = del_timer(&hw->resptimer)) != 0) { + timer_ok = del_timer(&hw->resptimer); + if (timer_ok != 0) hw->resp_timer_done = 1; - } } spin_unlock_irqrestore(&hw->ctlxq.lock, flags); diff --git a/drivers/staging/wlan-ng/p80211conv.c b/drivers/staging/wlan-ng/p80211conv.c index 5952c671073f..3ba5eabdb583 100644 --- a/drivers/staging/wlan-ng/p80211conv.c +++ b/drivers/staging/wlan-ng/p80211conv.c @@ -207,11 +207,10 @@ int skb_ether_to_p80211(wlandevice_t *wlandev, u32 ethconv, p80211_wep->data = kmalloc(skb->len, GFP_ATOMIC); - if ((foo = wep_encrypt(wlandev, skb->data, p80211_wep->data, - skb->len, - (wlandev->hostwep & - HOSTWEP_DEFAULTKEY_MASK), - p80211_wep->iv, p80211_wep->icv))) { + foo = wep_encrypt(wlandev, skb->data, p80211_wep->data, + skb->len, (wlandev->hostwep &HOSTWEP_DEFAULTKEY_MASK), + p80211_wep->iv, p80211_wep->icv); + if (foo) { printk(KERN_WARNING "Host en-WEP failed, dropping frame (%d).\n", foo); @@ -323,11 +322,12 @@ int skb_p80211_to_ether(wlandevice_t *wlandev, u32 ethconv, skb->len); return 1; } - if ((foo = wep_decrypt(wlandev, skb->data + payload_offset + 4, + foo = wep_decrypt(wlandev, skb->data + payload_offset + 4, payload_length - 8, -1, skb->data + payload_offset, skb->data + payload_offset + - payload_length - 4))) { + payload_length - 4); + if (foo) { /* de-wep failed, drop skb. */ pr_debug("Host de-WEP failed, dropping frame (%d).\n", foo); diff --git a/drivers/staging/wlan-ng/p80211netdev.c b/drivers/staging/wlan-ng/p80211netdev.c index e27d72cf5714..763ab1187a1c 100644 --- a/drivers/staging/wlan-ng/p80211netdev.c +++ b/drivers/staging/wlan-ng/p80211netdev.c @@ -586,7 +586,8 @@ static int p80211knetdev_do_ioctl(netdevice_t *dev, struct ifreq *ifr, int cmd) } /* Allocate a buf of size req->len */ - if ((msgbuf = kmalloc(req->len, GFP_KERNEL))) { + msgbuf = kmalloc(req->len, GFP_KERNEL); + if (msgbuf) { if (copy_from_user(msgbuf, (void __user *)req->data, req->len)) result = -EFAULT; else diff --git a/drivers/staging/wlan-ng/p80211wext.c b/drivers/staging/wlan-ng/p80211wext.c index 040c9e3e1d51..108a8060d1f5 100644 --- a/drivers/staging/wlan-ng/p80211wext.c +++ b/drivers/staging/wlan-ng/p80211wext.c @@ -549,14 +549,14 @@ static int p80211wext_siwencode(netdevice_t *dev, } /* Check the Key index first. */ - if ((i = (erq->flags & IW_ENCODE_INDEX))) { - + i = (erq->flags & IW_ENCODE_INDEX); + if (i) { if ((i < 1) || (i > NUM_WEPKEYS)) { err = -EINVAL; goto exit; - } else + } else { i--; - + } /* Set current key number only if no keys are given */ if (erq->flags & IW_ENCODE_NOKEY) { result = -- cgit v1.2.3 From df84f941e9370be6798fa11aa5a77396d8869fdc Mon Sep 17 00:00:00 2001 From: Chihau Chau Date: Thu, 25 Feb 2010 19:57:39 -0300 Subject: Staging: dream: camera: msm_camera: fix code style issues This fixes some code style issues like to add one space after a while or switch statement and before a open parenthesis '(', and to include KERN_ facility level in the printk() functions. Signed-off-by: Chihau Chau Acked-by: Pavel Machek Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dream/camera/msm_camera.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dream/camera/msm_camera.c b/drivers/staging/dream/camera/msm_camera.c index 925e16c324d2..223918f858e7 100644 --- a/drivers/staging/dream/camera/msm_camera.c +++ b/drivers/staging/dream/camera/msm_camera.c @@ -76,14 +76,14 @@ static LIST_HEAD(msm_sensors); list_del_init(&qcmd->list); \ kfree(qcmd); \ }; \ -} while(0) +} while (0) #define MSM_DRAIN_QUEUE(sync, name) do { \ unsigned long flags; \ spin_lock_irqsave(&(sync)->name##_lock, flags); \ MSM_DRAIN_QUEUE_NOSYNC(sync, name); \ spin_unlock_irqrestore(&(sync)->name##_lock, flags); \ -} while(0) +} while (0) static int check_overlap(struct hlist_head *ptype, unsigned long paddr, @@ -868,7 +868,7 @@ static int msm_config_vfe(struct msm_sync *sync, void __user *arg) return -EFAULT; } - switch(cfgcmd.cmd_type) { + switch (cfgcmd.cmd_type) { case CMD_STATS_ENABLE: axi_data.bufnum1 = msm_pmem_region_lookup(&sync->stats, @@ -1621,7 +1621,8 @@ static int msm_release_control(struct inode *node, struct file *filep) int rc; struct msm_control_device *ctrl_pmsm = filep->private_data; struct msm_device *pmsm = ctrl_pmsm->pmsm; - printk("msm_camera: RELEASE %s\n", filep->f_path.dentry->d_name.name); + printk(KERN_INFO "msm_camera: RELEASE %s\n", + filep->f_path.dentry->d_name.name); rc = __msm_release(pmsm->sync); if (!rc) { MSM_DRAIN_QUEUE(&ctrl_pmsm->ctrl_q, ctrl_status_q); @@ -1635,7 +1636,8 @@ static int msm_release_frame(struct inode *node, struct file *filep) { int rc; struct msm_device *pmsm = filep->private_data; - printk("msm_camera: RELEASE %s\n", filep->f_path.dentry->d_name.name); + printk(KERN_INFO "msm_camera: RELEASE %s\n", + filep->f_path.dentry->d_name.name); rc = __msm_release(pmsm->sync); if (!rc) { MSM_DRAIN_QUEUE(pmsm->sync, prev_frame_q); @@ -1719,7 +1721,7 @@ static void msm_vfe_sync(struct msm_vfe_resp *vdata, qcmd->type = qtype; if (qtype == MSM_CAM_Q_VFE_MSG) { - switch(vdata->type) { + switch (vdata->type) { case VFE_MSG_OUTPUT1: case VFE_MSG_OUTPUT2: qcmd_frame = @@ -1928,7 +1930,8 @@ static int __msm_v4l2_control(struct msm_sync *sync, memcpy(out->value, ctrl->value, ctrl->length); end: - if (rcmd) kfree(rcmd); + if (rcmd) + kfree(rcmd); CDBG("__msm_v4l2_control: end rc = %d\n", rc); return rc; } -- cgit v1.2.3 From b94c765ac31f8eb9c6fe895ba611bb446b799635 Mon Sep 17 00:00:00 2001 From: Chihau Chau Date: Thu, 25 Feb 2010 20:20:09 -0300 Subject: Staging: dream: camera: sk5k3e2fx: fix code style issues This fixes some code style issues about assignments in if conditions. Signed-off-by: Chihau Chau Acked-by: Pavel Machek Signed-off-by: Greg Kroah-Hartman --- drivers/staging/dream/camera/s5k3e2fx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/dream/camera/s5k3e2fx.c b/drivers/staging/dream/camera/s5k3e2fx.c index edba19889b0f..2426f5e5b2aa 100644 --- a/drivers/staging/dream/camera/s5k3e2fx.c +++ b/drivers/staging/dream/camera/s5k3e2fx.c @@ -743,12 +743,12 @@ static int s5k3e2fx_sensor_open_init(const struct msm_camera_sensor_info *data) } /* initialize AF */ - if ((rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, - 0x3146, 0x3A)) < 0) + rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, 0x3146, 0x3A); + if (rc < 0) goto init_fail1; - if ((rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, - 0x3130, 0x03)) < 0) + rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, 0x3130, 0x03); + if (rc < 0) goto init_fail1; goto init_done; -- cgit v1.2.3 From a71b676fa9b92119c0fb4e3fab34e45a17f15107 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 4 Mar 2010 08:44:13 -0800 Subject: Staging: winbond: fix up wireless api errors The wireless core made a number of api changes that caused the winbond driver to break. This patch fixes those errors by making the needed changes to the driver. Signed-off-by: Greg Kroah-Hartman --- drivers/staging/winbond/wbusb.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/winbond/wbusb.c b/drivers/staging/winbond/wbusb.c index ecf418dcefd9..3482eec18651 100644 --- a/drivers/staging/winbond/wbusb.c +++ b/drivers/staging/winbond/wbusb.c @@ -65,17 +65,17 @@ static void hal_set_beacon_period(struct hw_data *pHwData, u16 beacon_period) } static int wbsoft_add_interface(struct ieee80211_hw *dev, - struct ieee80211_if_init_conf *conf) + struct ieee80211_vif *vif) { struct wbsoft_priv *priv = dev->priv; - hal_set_beacon_period(&priv->sHwData, conf->vif->bss_conf.beacon_int); + hal_set_beacon_period(&priv->sHwData, vif->bss_conf.beacon_int); return 0; } static void wbsoft_remove_interface(struct ieee80211_hw *dev, - struct ieee80211_if_init_conf *conf) + struct ieee80211_vif *vif) { printk("wbsoft_remove interface called\n"); } @@ -92,13 +92,6 @@ static int wbsoft_get_stats(struct ieee80211_hw *hw, return 0; } -static int wbsoft_get_tx_stats(struct ieee80211_hw *hw, - struct ieee80211_tx_queue_stats *stats) -{ - printk(KERN_INFO "%s called\n", __func__); - return 0; -} - static u64 wbsoft_prepare_multicast(struct ieee80211_hw *hw, int mc_count, struct dev_addr_list *mc_list) { @@ -287,7 +280,6 @@ static const struct ieee80211_ops wbsoft_ops = { .prepare_multicast = wbsoft_prepare_multicast, .configure_filter = wbsoft_configure_filter, .get_stats = wbsoft_get_stats, - .get_tx_stats = wbsoft_get_tx_stats, .get_tsf = wbsoft_get_tsf, }; -- cgit v1.2.3 From b43fa8284d7790d9cca32c9c55e24f29be2fa33b Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Wed, 3 Mar 2010 09:05:03 -0500 Subject: dquot: cleanup dquot transfer routine Get rid of the transfer dquot operation - it is now always called from the filesystem and if a filesystem really needs it's own (which none currently does) it can just call into it's own routine directly. Rename the now static low-level dquot_transfer helper to __dquot_transfer and vfs_dq_transfer to dquot_transfer to have a consistent namespace, and make the new dquot_transfer return a normal negative errno value which all callers expect. Signed-off-by: Christoph Hellwig Signed-off-by: Jan Kara --- Documentation/filesystems/Locking | 2 -- drivers/staging/pohmelfs/inode.c | 2 +- fs/ext2/inode.c | 2 +- fs/ext3/inode.c | 2 +- fs/ext3/super.c | 1 - fs/ext4/inode.c | 2 +- fs/ext4/super.c | 1 - fs/jfs/file.c | 5 +++-- fs/ocfs2/file.c | 4 ++-- fs/ocfs2/quota_global.c | 1 - fs/quota/dquot.c | 12 +++++------- fs/reiserfs/inode.c | 3 +-- fs/reiserfs/super.c | 1 - fs/udf/file.c | 2 +- fs/ufs/truncate.c | 2 +- include/linux/quota.h | 1 - include/linux/quotaops.h | 5 ++--- 17 files changed, 19 insertions(+), 29 deletions(-) (limited to 'drivers') diff --git a/Documentation/filesystems/Locking b/Documentation/filesystems/Locking index 4428f55f2131..4574e0272bdd 100644 --- a/Documentation/filesystems/Locking +++ b/Documentation/filesystems/Locking @@ -462,7 +462,6 @@ in sys_read() and friends. prototypes: int (*initialize) (struct inode *, int); int (*drop) (struct inode *); - int (*transfer) (struct inode *, struct iattr *); int (*write_dquot) (struct dquot *); int (*acquire_dquot) (struct dquot *); int (*release_dquot) (struct dquot *); @@ -477,7 +476,6 @@ What filesystem should expect from the generic quota functions: FS recursion Held locks when called initialize: yes maybe dqonoff_sem drop: yes - -transfer: yes - write_dquot: yes dqonoff_sem or dqptr_sem acquire_dquot: yes dqonoff_sem or dqptr_sem release_dquot: yes dqonoff_sem or dqptr_sem diff --git a/drivers/staging/pohmelfs/inode.c b/drivers/staging/pohmelfs/inode.c index f69b7783027f..11fc4d5c43e1 100644 --- a/drivers/staging/pohmelfs/inode.c +++ b/drivers/staging/pohmelfs/inode.c @@ -969,7 +969,7 @@ int pohmelfs_setattr_raw(struct inode *inode, struct iattr *attr) if ((attr->ia_valid & ATTR_UID && attr->ia_uid != inode->i_uid) || (attr->ia_valid & ATTR_GID && attr->ia_gid != inode->i_gid)) { - err = vfs_dq_transfer(inode, attr) ? -EDQUOT : 0; + err = dquot_transfer(inode, attr); if (err) goto err_out_exit; } diff --git a/fs/ext2/inode.c b/fs/ext2/inode.c index 71b032c65a02..3cfcfd9a131a 100644 --- a/fs/ext2/inode.c +++ b/fs/ext2/inode.c @@ -1459,7 +1459,7 @@ int ext2_setattr(struct dentry *dentry, struct iattr *iattr) return error; if ((iattr->ia_valid & ATTR_UID && iattr->ia_uid != inode->i_uid) || (iattr->ia_valid & ATTR_GID && iattr->ia_gid != inode->i_gid)) { - error = vfs_dq_transfer(inode, iattr) ? -EDQUOT : 0; + error = dquot_transfer(inode, iattr); if (error) return error; } diff --git a/fs/ext3/inode.c b/fs/ext3/inode.c index 20f02d69365c..14d40a4dd6f0 100644 --- a/fs/ext3/inode.c +++ b/fs/ext3/inode.c @@ -3160,7 +3160,7 @@ int ext3_setattr(struct dentry *dentry, struct iattr *attr) error = PTR_ERR(handle); goto err_out; } - error = vfs_dq_transfer(inode, attr) ? -EDQUOT : 0; + error = dquot_transfer(inode, attr); if (error) { ext3_journal_stop(handle); return error; diff --git a/fs/ext3/super.c b/fs/ext3/super.c index 8b8bc4f9cb14..f7d4a2c19dee 100644 --- a/fs/ext3/super.c +++ b/fs/ext3/super.c @@ -752,7 +752,6 @@ static ssize_t ext3_quota_write(struct super_block *sb, int type, static const struct dquot_operations ext3_quota_operations = { .initialize = dquot_initialize, .drop = dquot_drop, - .transfer = dquot_transfer, .write_dquot = ext3_write_dquot, .acquire_dquot = ext3_acquire_dquot, .release_dquot = ext3_release_dquot, diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c index 9f607ea411c8..6a002a6d0624 100644 --- a/fs/ext4/inode.c +++ b/fs/ext4/inode.c @@ -5263,7 +5263,7 @@ int ext4_setattr(struct dentry *dentry, struct iattr *attr) error = PTR_ERR(handle); goto err_out; } - error = vfs_dq_transfer(inode, attr) ? -EDQUOT : 0; + error = dquot_transfer(inode, attr); if (error) { ext4_journal_stop(handle); return error; diff --git a/fs/ext4/super.c b/fs/ext4/super.c index d231da8798e3..b4253fb7bab6 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -1017,7 +1017,6 @@ static const struct dquot_operations ext4_quota_operations = { #ifdef CONFIG_QUOTA .get_reserved_space = ext4_get_reserved_space, #endif - .transfer = dquot_transfer, .write_dquot = ext4_write_dquot, .acquire_dquot = ext4_acquire_dquot, .release_dquot = ext4_release_dquot, diff --git a/fs/jfs/file.c b/fs/jfs/file.c index a4229e49330e..2c201783836f 100644 --- a/fs/jfs/file.c +++ b/fs/jfs/file.c @@ -100,8 +100,9 @@ int jfs_setattr(struct dentry *dentry, struct iattr *iattr) if ((iattr->ia_valid & ATTR_UID && iattr->ia_uid != inode->i_uid) || (iattr->ia_valid & ATTR_GID && iattr->ia_gid != inode->i_gid)) { - if (vfs_dq_transfer(inode, iattr)) - return -EDQUOT; + rc = dquot_transfer(inode, iattr); + if (rc) + return rc; } rc = inode_setattr(inode, iattr); diff --git a/fs/ocfs2/file.c b/fs/ocfs2/file.c index 6cf3d8d18369..472e8f8bc892 100644 --- a/fs/ocfs2/file.c +++ b/fs/ocfs2/file.c @@ -1020,7 +1020,7 @@ int ocfs2_setattr(struct dentry *dentry, struct iattr *attr) /* * Gather pointers to quota structures so that allocation / * freeing of quota structures happens here and not inside - * vfs_dq_transfer() where we have problems with lock ordering + * dquot_transfer() where we have problems with lock ordering */ if (attr->ia_valid & ATTR_UID && attr->ia_uid != inode->i_uid && OCFS2_HAS_RO_COMPAT_FEATURE(sb, @@ -1053,7 +1053,7 @@ int ocfs2_setattr(struct dentry *dentry, struct iattr *attr) mlog_errno(status); goto bail_unlock; } - status = vfs_dq_transfer(inode, attr) ? -EDQUOT : 0; + status = dquot_transfer(inode, attr); if (status < 0) goto bail_commit; } else { diff --git a/fs/ocfs2/quota_global.c b/fs/ocfs2/quota_global.c index ed96b3eeb13c..b654bd103b6f 100644 --- a/fs/ocfs2/quota_global.c +++ b/fs/ocfs2/quota_global.c @@ -853,7 +853,6 @@ static void ocfs2_destroy_dquot(struct dquot *dquot) const struct dquot_operations ocfs2_quota_operations = { .initialize = dquot_initialize, .drop = dquot_drop, - .transfer = dquot_transfer, .write_dquot = ocfs2_write_dquot, .acquire_dquot = ocfs2_acquire_dquot, .release_dquot = ocfs2_release_dquot, diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index ed131318b849..78ce4c48ad77 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -1669,7 +1669,7 @@ EXPORT_SYMBOL(dquot_free_inode); * This operation can block, but only after everything is updated * A transaction must be started when entering this function. */ -int dquot_transfer(struct inode *inode, qid_t *chid, unsigned long mask) +static int __dquot_transfer(struct inode *inode, qid_t *chid, unsigned long mask) { qsize_t space, cur_space; qsize_t rsv_space = 0; @@ -1766,12 +1766,11 @@ over_quota: ret = NO_QUOTA; goto warn_put_all; } -EXPORT_SYMBOL(dquot_transfer); /* Wrapper for transferring ownership of an inode for uid/gid only * Called from FSXXX_setattr() */ -int vfs_dq_transfer(struct inode *inode, struct iattr *iattr) +int dquot_transfer(struct inode *inode, struct iattr *iattr) { qid_t chid[MAXQUOTAS]; unsigned long mask = 0; @@ -1786,12 +1785,12 @@ int vfs_dq_transfer(struct inode *inode, struct iattr *iattr) } if (sb_any_quota_active(inode->i_sb) && !IS_NOQUOTA(inode)) { vfs_dq_init(inode); - if (inode->i_sb->dq_op->transfer(inode, chid, mask) == NO_QUOTA) - return 1; + if (__dquot_transfer(inode, chid, mask) == NO_QUOTA) + return -EDQUOT; } return 0; } -EXPORT_SYMBOL(vfs_dq_transfer); +EXPORT_SYMBOL(dquot_transfer); /* * Write info of quota file to disk @@ -1814,7 +1813,6 @@ EXPORT_SYMBOL(dquot_commit_info); const struct dquot_operations dquot_operations = { .initialize = dquot_initialize, .drop = dquot_drop, - .transfer = dquot_transfer, .write_dquot = dquot_commit, .acquire_dquot = dquot_acquire, .release_dquot = dquot_release, diff --git a/fs/reiserfs/inode.c b/fs/reiserfs/inode.c index f56a3d2e6497..99a5e5a8ab5a 100644 --- a/fs/reiserfs/inode.c +++ b/fs/reiserfs/inode.c @@ -3134,8 +3134,7 @@ int reiserfs_setattr(struct dentry *dentry, struct iattr *attr) jbegin_count); if (error) goto out; - error = - vfs_dq_transfer(inode, attr) ? -EDQUOT : 0; + error = dquot_transfer(inode, attr); if (error) { journal_end(&th, inode->i_sb, jbegin_count); diff --git a/fs/reiserfs/super.c b/fs/reiserfs/super.c index e942ceecf2b8..97c3e8ed7db6 100644 --- a/fs/reiserfs/super.c +++ b/fs/reiserfs/super.c @@ -618,7 +618,6 @@ static int reiserfs_quota_on(struct super_block *, int, int, char *, int); static const struct dquot_operations reiserfs_quota_operations = { .initialize = dquot_initialize, .drop = dquot_drop, - .transfer = dquot_transfer, .write_dquot = reiserfs_write_dquot, .acquire_dquot = reiserfs_acquire_dquot, .release_dquot = reiserfs_release_dquot, diff --git a/fs/udf/file.c b/fs/udf/file.c index 35ca47281faa..2df7fcb677b3 100644 --- a/fs/udf/file.c +++ b/fs/udf/file.c @@ -229,7 +229,7 @@ static int udf_setattr(struct dentry *dentry, struct iattr *iattr) if ((iattr->ia_valid & ATTR_UID && iattr->ia_uid != inode->i_uid) || (iattr->ia_valid & ATTR_GID && iattr->ia_gid != inode->i_gid)) { - error = vfs_dq_transfer(inode, iattr) ? -EDQUOT : 0; + error = dquot_transfer(inode, iattr); if (error) return error; } diff --git a/fs/ufs/truncate.c b/fs/ufs/truncate.c index 56ab31f00bd0..87bbab685901 100644 --- a/fs/ufs/truncate.c +++ b/fs/ufs/truncate.c @@ -520,7 +520,7 @@ static int ufs_setattr(struct dentry *dentry, struct iattr *attr) if ((ia_valid & ATTR_UID && attr->ia_uid != inode->i_uid) || (ia_valid & ATTR_GID && attr->ia_gid != inode->i_gid)) { - error = vfs_dq_transfer(inode, attr) ? -EDQUOT : 0; + error = dquot_transfer(inode, attr); if (error) return error; } diff --git a/include/linux/quota.h b/include/linux/quota.h index e3b07895d327..422e6aa78edc 100644 --- a/include/linux/quota.h +++ b/include/linux/quota.h @@ -297,7 +297,6 @@ struct quota_format_ops { struct dquot_operations { int (*initialize) (struct inode *, int); int (*drop) (struct inode *); - int (*transfer) (struct inode *, qid_t *, unsigned long); int (*write_dquot) (struct dquot *); /* Ordinary dquot write */ struct dquot *(*alloc_dquot)(struct super_block *, int); /* Allocate memory for new dquot */ void (*destroy_dquot)(struct dquot *); /* Free memory for dquot */ diff --git a/include/linux/quotaops.h b/include/linux/quotaops.h index 9ce7f051a4ba..fa27b7218c82 100644 --- a/include/linux/quotaops.h +++ b/include/linux/quotaops.h @@ -42,7 +42,6 @@ int dquot_alloc_inode(const struct inode *inode); int dquot_claim_space_nodirty(struct inode *inode, qsize_t number); void dquot_free_inode(const struct inode *inode); -int dquot_transfer(struct inode *inode, qid_t *chid, unsigned long mask); int dquot_commit(struct dquot *dquot); int dquot_acquire(struct dquot *dquot); int dquot_release(struct dquot *dquot); @@ -66,7 +65,7 @@ int vfs_get_dqblk(struct super_block *sb, int type, qid_t id, struct if_dqblk *d int vfs_set_dqblk(struct super_block *sb, int type, qid_t id, struct if_dqblk *di); void vfs_dq_drop(struct inode *inode); -int vfs_dq_transfer(struct inode *inode, struct iattr *iattr); +int dquot_transfer(struct inode *inode, struct iattr *iattr); int vfs_dq_quota_on_remount(struct super_block *sb); static inline struct mem_dqinfo *sb_dqinfo(struct super_block *sb, int type) @@ -234,7 +233,7 @@ static inline int vfs_dq_quota_on_remount(struct super_block *sb) return 0; } -static inline int vfs_dq_transfer(struct inode *inode, struct iattr *iattr) +static inline int dquot_transfer(struct inode *inode, struct iattr *iattr) { return 0; } -- cgit v1.2.3 From 5bc923c505926af927d4f3011da92c243787d6a7 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 5 Mar 2010 00:31:33 -0800 Subject: Input: gamecon - fix off by one range check It should be >= GC_MAX not > GC_MAX. Signed-off-by: Dan Carpenter Signed-off-by: Dmitry Torokhov --- drivers/input/joystick/gamecon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/input/joystick/gamecon.c b/drivers/input/joystick/gamecon.c index ae998d99a5ae..7a55714a1486 100644 --- a/drivers/input/joystick/gamecon.c +++ b/drivers/input/joystick/gamecon.c @@ -819,7 +819,7 @@ static int __init gc_setup_pad(struct gc *gc, int idx, int pad_type) int i; int err; - if (pad_type < 1 || pad_type > GC_MAX) { + if (pad_type < 1 || pad_type >= GC_MAX) { pr_err("Pad type %d unknown\n", pad_type); return -EINVAL; } -- cgit v1.2.3 From 776943fd6f104a6e8457dc95a17282e69e963666 Mon Sep 17 00:00:00 2001 From: Ping Cheng Date: Thu, 4 Mar 2010 21:50:59 -0800 Subject: Input: wacom - merge out and in prox events Process out and in prox events for Graphire and Tablet PC devices in the same loop to simplify the data parsing logic. Signed-off-by: Ping Cheng Signed-off-by: Dmitry Torokhov --- drivers/input/tablet/wacom_wac.c | 163 ++++++++++++++------------------------- 1 file changed, 59 insertions(+), 104 deletions(-) (limited to 'drivers') diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c index 4a852d815c68..b3ba3437a2eb 100644 --- a/drivers/input/tablet/wacom_wac.c +++ b/drivers/input/tablet/wacom_wac.c @@ -155,19 +155,19 @@ static int wacom_graphire_irq(struct wacom_wac *wacom, void *wcombo) { struct wacom_features *features = &wacom->features; unsigned char *data = wacom->data; - int x, y, rw; - static int penData = 0; + int x, y, prox; + int rw = 0; + int retval = 0; if (data[0] != WACOM_REPORT_PENABLED) { dbg("wacom_graphire_irq: received unknown report #%d", data[0]); - return 0; + goto exit; } - if (data[1] & 0x80) { - /* in prox and not a pad data */ - penData = 1; - - switch ((data[1] >> 5) & 3) { + prox = data[1] & 0x80; + if (prox || wacom->id[0]) { + if (prox) { + switch ((data[1] >> 5) & 3) { case 0: /* Pen */ wacom->tool[0] = BTN_TOOL_PEN; @@ -181,23 +181,13 @@ static int wacom_graphire_irq(struct wacom_wac *wacom, void *wcombo) case 2: /* Mouse with wheel */ wacom_report_key(wcombo, BTN_MIDDLE, data[1] & 0x04); - if (features->type == WACOM_G4 || features->type == WACOM_MO) { - rw = data[7] & 0x04 ? (data[7] & 0x03)-4 : (data[7] & 0x03); - wacom_report_rel(wcombo, REL_WHEEL, -rw); - } else - wacom_report_rel(wcombo, REL_WHEEL, -(signed char) data[6]); /* fall through */ case 3: /* Mouse without wheel */ wacom->tool[0] = BTN_TOOL_MOUSE; wacom->id[0] = CURSOR_DEVICE_ID; - wacom_report_key(wcombo, BTN_LEFT, data[1] & 0x01); - wacom_report_key(wcombo, BTN_RIGHT, data[1] & 0x02); - if (features->type == WACOM_G4 || features->type == WACOM_MO) - wacom_report_abs(wcombo, ABS_DISTANCE, data[6] & 0x3f); - else - wacom_report_abs(wcombo, ABS_DISTANCE, data[7] & 0x3f); break; + } } x = wacom_le16_to_cpu(&data[2]); y = wacom_le16_to_cpu(&data[4]); @@ -208,36 +198,32 @@ static int wacom_graphire_irq(struct wacom_wac *wacom, void *wcombo) wacom_report_key(wcombo, BTN_TOUCH, data[1] & 0x01); wacom_report_key(wcombo, BTN_STYLUS, data[1] & 0x02); wacom_report_key(wcombo, BTN_STYLUS2, data[1] & 0x04); - } - wacom_report_abs(wcombo, ABS_MISC, wacom->id[0]); /* report tool id */ - wacom_report_key(wcombo, wacom->tool[0], 1); - } else if (wacom->id[0]) { - wacom_report_abs(wcombo, ABS_X, 0); - wacom_report_abs(wcombo, ABS_Y, 0); - if (wacom->tool[0] == BTN_TOOL_MOUSE) { - wacom_report_key(wcombo, BTN_LEFT, 0); - wacom_report_key(wcombo, BTN_RIGHT, 0); - wacom_report_abs(wcombo, ABS_DISTANCE, 0); } else { - wacom_report_abs(wcombo, ABS_PRESSURE, 0); - wacom_report_key(wcombo, BTN_TOUCH, 0); - wacom_report_key(wcombo, BTN_STYLUS, 0); - wacom_report_key(wcombo, BTN_STYLUS2, 0); + wacom_report_key(wcombo, BTN_LEFT, data[1] & 0x01); + wacom_report_key(wcombo, BTN_RIGHT, data[1] & 0x02); + if (features->type == WACOM_G4 || + features->type == WACOM_MO) { + wacom_report_abs(wcombo, ABS_DISTANCE, data[6] & 0x3f); + rw = (signed)(data[7] & 0x04) - (data[7] & 0x03); + } else { + wacom_report_abs(wcombo, ABS_DISTANCE, data[7] & 0x3f); + rw = -(signed)data[6]; + } + wacom_report_rel(wcombo, REL_WHEEL, rw); } - wacom->id[0] = 0; - wacom_report_abs(wcombo, ABS_MISC, 0); /* reset tool id */ - wacom_report_key(wcombo, wacom->tool[0], 0); + + if (!prox) + wacom->id[0] = 0; + wacom_report_abs(wcombo, ABS_MISC, wacom->id[0]); /* report tool id */ + wacom_report_key(wcombo, wacom->tool[0], prox); + wacom_input_sync(wcombo); /* sync last event */ } /* send pad data */ switch (features->type) { case WACOM_G4: - if (data[7] & 0xf8) { - if (penData) { - wacom_input_sync(wcombo); /* sync last event */ - if (!wacom->id[0]) - penData = 0; - } + prox = data[7] & 0xf8; + if (prox || wacom->id[1]) { wacom->id[1] = PAD_DEVICE_ID; wacom_report_key(wcombo, BTN_0, (data[7] & 0x40)); wacom_report_key(wcombo, BTN_4, (data[7] & 0x80)); @@ -245,29 +231,16 @@ static int wacom_graphire_irq(struct wacom_wac *wacom, void *wcombo) wacom_report_rel(wcombo, REL_WHEEL, rw); wacom_report_key(wcombo, BTN_TOOL_FINGER, 0xf0); wacom_report_abs(wcombo, ABS_MISC, wacom->id[1]); - wacom_input_event(wcombo, EV_MSC, MSC_SERIAL, 0xf0); - } else if (wacom->id[1]) { - if (penData) { - wacom_input_sync(wcombo); /* sync last event */ - if (!wacom->id[0]) - penData = 0; - } - wacom->id[1] = 0; - wacom_report_key(wcombo, BTN_0, (data[7] & 0x40)); - wacom_report_key(wcombo, BTN_4, (data[7] & 0x80)); - wacom_report_rel(wcombo, REL_WHEEL, 0); - wacom_report_key(wcombo, BTN_TOOL_FINGER, 0); - wacom_report_abs(wcombo, ABS_MISC, 0); + if (!prox) + wacom->id[1] = 0; + wacom_report_abs(wcombo, ABS_MISC, wacom->id[1]); wacom_input_event(wcombo, EV_MSC, MSC_SERIAL, 0xf0); } + retval = 1; break; case WACOM_MO: - if ((data[7] & 0xf8) || (data[8] & 0xff)) { - if (penData) { - wacom_input_sync(wcombo); /* sync last event */ - if (!wacom->id[0]) - penData = 0; - } + prox = (data[7] & 0xf8) || data[8]; + if (prox || wacom->id[1]) { wacom->id[1] = PAD_DEVICE_ID; wacom_report_key(wcombo, BTN_0, (data[7] & 0x08)); wacom_report_key(wcombo, BTN_1, (data[7] & 0x20)); @@ -275,27 +248,16 @@ static int wacom_graphire_irq(struct wacom_wac *wacom, void *wcombo) wacom_report_key(wcombo, BTN_5, (data[7] & 0x40)); wacom_report_abs(wcombo, ABS_WHEEL, (data[8] & 0x7f)); wacom_report_key(wcombo, BTN_TOOL_FINGER, 0xf0); + if (!prox) + wacom->id[1] = 0; wacom_report_abs(wcombo, ABS_MISC, wacom->id[1]); wacom_input_event(wcombo, EV_MSC, MSC_SERIAL, 0xf0); - } else if (wacom->id[1]) { - if (penData) { - wacom_input_sync(wcombo); /* sync last event */ - if (!wacom->id[0]) - penData = 0; - } - wacom->id[1] = 0; - wacom_report_key(wcombo, BTN_0, (data[7] & 0x08)); - wacom_report_key(wcombo, BTN_1, (data[7] & 0x20)); - wacom_report_key(wcombo, BTN_4, (data[7] & 0x10)); - wacom_report_key(wcombo, BTN_5, (data[7] & 0x40)); - wacom_report_abs(wcombo, ABS_WHEEL, (data[8] & 0x7f)); - wacom_report_key(wcombo, BTN_TOOL_FINGER, 0); - wacom_report_abs(wcombo, ABS_MISC, 0); - wacom_input_event(wcombo, EV_MSC, MSC_SERIAL, 0xf0); } + retval = 1; break; } - return 1; +exit: + return retval; } static int wacom_intuos_inout(struct wacom_wac *wacom, void *wcombo) @@ -636,9 +598,9 @@ static int wacom_intuos_irq(struct wacom_wac *wacom, void *wcombo) static void wacom_tpc_finger_in(struct wacom_wac *wacom, void *wcombo, char *data, int idx) { wacom_report_abs(wcombo, ABS_X, - (data[2 + idx * 2] & 0xff) | ((data[3 + idx * 2] & 0x7f) << 8)); + data[2 + idx * 2] | ((data[3 + idx * 2] & 0x7f) << 8)); wacom_report_abs(wcombo, ABS_Y, - (data[6 + idx * 2] & 0xff) | ((data[7 + idx * 2] & 0x7f) << 8)); + data[6 + idx * 2] | ((data[7 + idx * 2] & 0x7f) << 8)); wacom_report_abs(wcombo, ABS_MISC, wacom->id[0]); wacom_report_key(wcombo, wacom->tool[idx], 1); if (idx) @@ -782,31 +744,24 @@ static int wacom_tpc_irq(struct wacom_wac *wacom, void *wcombo) touchInProx = 0; - if (prox) { /* in prox */ - if (!wacom->id[0]) { - /* Going into proximity select tool */ - wacom->tool[0] = (data[1] & 0x0c) ? BTN_TOOL_RUBBER : BTN_TOOL_PEN; - if (wacom->tool[0] == BTN_TOOL_PEN) - wacom->id[0] = STYLUS_DEVICE_ID; - else - wacom->id[0] = ERASER_DEVICE_ID; - } - wacom_report_key(wcombo, BTN_STYLUS, data[1] & 0x02); - wacom_report_key(wcombo, BTN_STYLUS2, data[1] & 0x10); - wacom_report_abs(wcombo, ABS_X, wacom_le16_to_cpu(&data[2])); - wacom_report_abs(wcombo, ABS_Y, wacom_le16_to_cpu(&data[4])); - pressure = ((data[7] & 0x01) << 8) | data[6]; - if (pressure < 0) - pressure = features->pressure_max + pressure + 1; - wacom_report_abs(wcombo, ABS_PRESSURE, pressure); - wacom_report_key(wcombo, BTN_TOUCH, data[1] & 0x05); - } else { - wacom_report_abs(wcombo, ABS_X, 0); - wacom_report_abs(wcombo, ABS_Y, 0); - wacom_report_abs(wcombo, ABS_PRESSURE, 0); - wacom_report_key(wcombo, BTN_STYLUS, 0); - wacom_report_key(wcombo, BTN_STYLUS2, 0); - wacom_report_key(wcombo, BTN_TOUCH, 0); + if (!wacom->id[0]) { /* first in prox */ + /* Going into proximity select tool */ + wacom->tool[0] = (data[1] & 0x0c) ? BTN_TOOL_RUBBER : BTN_TOOL_PEN; + if (wacom->tool[0] == BTN_TOOL_PEN) + wacom->id[0] = STYLUS_DEVICE_ID; + else + wacom->id[0] = ERASER_DEVICE_ID; + } + wacom_report_key(wcombo, BTN_STYLUS, data[1] & 0x02); + wacom_report_key(wcombo, BTN_STYLUS2, data[1] & 0x10); + wacom_report_abs(wcombo, ABS_X, wacom_le16_to_cpu(&data[2])); + wacom_report_abs(wcombo, ABS_Y, wacom_le16_to_cpu(&data[4])); + pressure = ((data[7] & 0x01) << 8) | data[6]; + if (pressure < 0) + pressure = features->pressure_max + pressure + 1; + wacom_report_abs(wcombo, ABS_PRESSURE, pressure); + wacom_report_key(wcombo, BTN_TOUCH, data[1] & 0x05); + if (!prox) { /* out-prox */ wacom->id[0] = 0; /* pen is out so touch can be enabled now */ touchInProx = 1; -- cgit v1.2.3 From 6771ea1fff988651593f78c122bc02e80f5100a0 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:13 +0100 Subject: hwmon: (lm90) Add support for the Winbond/Nuvoton W83L771AWG/ASG This chips is found on several Zotac Ion ITX boards, amongst others. Signed-off-by: Jean Delvare Cc: MC Matti Cc: Manuel Lamotte-Schubert --- Documentation/hwmon/lm90 | 10 ++++++++++ drivers/hwmon/Kconfig | 5 +++-- drivers/hwmon/lm90.c | 12 +++++++++++- 3 files changed, 24 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/Documentation/hwmon/lm90 b/Documentation/hwmon/lm90 index 93d8e3d55150..08106ad7089c 100644 --- a/Documentation/hwmon/lm90 +++ b/Documentation/hwmon/lm90 @@ -84,6 +84,10 @@ Supported chips: Addresses scanned: I2C 0x4c Datasheet: Publicly available at the Maxim website http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3500 + * Winbond/Nuvoton W83L771AWG/ASG + Prefix: 'w83l771' + Addresses scanned: I2C 0x4c + Datasheet: Not publicly available, can be requested from Nuvoton Author: Jean Delvare @@ -147,6 +151,12 @@ MAX6680 and MAX6681: * Selectable address * Remote sensor type selection +W83L771AWG/ASG + * The AWG and ASG variants only differ in package format. + * Filter and alert configuration register at 0xBF + * Diode ideality factor configuration (remote sensor) at 0xE3 + * Moving average (depending on conversion rate) + All temperature values are given in degrees Celsius. Resolution is 1.0 degree for the local temperature, 0.125 degree for the remote temperature, except for the MAX6657, MAX6658 and MAX6659 which have a diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 68cf87749a42..9234c2e2c7d9 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -563,9 +563,10 @@ config SENSORS_LM90 depends on I2C help If you say yes here you get support for National Semiconductor LM90, - LM86, LM89 and LM99, Analog Devices ADM1032 and ADT7461, and Maxim + LM86, LM89 and LM99, Analog Devices ADM1032 and ADT7461, Maxim MAX6646, MAX6647, MAX6648, MAX6649, MAX6657, MAX6658, MAX6659, - MAX6680, MAX6681 and MAX6692 sensor chips. + MAX6680, MAX6681 and MAX6692, and Winbond/Nuvoton W83L771AWG/ASG + sensor chips. This driver can also be built as a module. If so, the module will be called lm90. diff --git a/drivers/hwmon/lm90.c b/drivers/hwmon/lm90.c index 7c9bdc167426..ddf617f3a713 100644 --- a/drivers/hwmon/lm90.c +++ b/drivers/hwmon/lm90.c @@ -93,7 +93,8 @@ static const unsigned short normal_i2c[] = { 0x18, 0x19, 0x1a, 0x29, 0x2a, 0x2b, 0x4c, 0x4d, 0x4e, I2C_CLIENT_END }; -enum chips { lm90, adm1032, lm99, lm86, max6657, adt7461, max6680, max6646 }; +enum chips { lm90, adm1032, lm99, lm86, max6657, adt7461, max6680, max6646, + w83l771 }; /* * The LM90 registers @@ -173,6 +174,7 @@ static const struct i2c_device_id lm90_id[] = { { "max6659", max6657 }, { "max6680", max6680 }, { "max6681", max6680 }, + { "w83l771", w83l771 }, { } }; MODULE_DEVICE_TABLE(i2c, lm90_id); @@ -758,6 +760,14 @@ static int lm90_detect(struct i2c_client *new_client, && reg_convrate <= 0x07) { name = "max6646"; } + } else + if (address == 0x4C + && man_id == 0x5C) { /* Winbond/Nuvoton */ + if ((chip_id & 0xFE) == 0x10 /* W83L771AWG/ASG */ + && (reg_config1 & 0x2A) == 0x00 + && reg_convrate <= 0x08) { + name = "w83l771"; + } } if (!name) { /* identification failed */ -- cgit v1.2.3 From 95238364167edaf93ce2890e5f55326b63194851 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:14 +0100 Subject: hwmon: (lm90) Restore configuration on exit Restore the chip configuration when unloading the driver. This ensures we don't leave the chip running if it was initially stopped. Signed-off-by: Jean Delvare --- drivers/hwmon/lm90.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/lm90.c b/drivers/hwmon/lm90.c index ddf617f3a713..4cbbf1563de6 100644 --- a/drivers/hwmon/lm90.c +++ b/drivers/hwmon/lm90.c @@ -1,7 +1,7 @@ /* * lm90.c - Part of lm_sensors, Linux kernel modules for hardware * monitoring - * Copyright (C) 2003-2009 Jean Delvare + * Copyright (C) 2003-2010 Jean Delvare * * Based on the lm83 driver. The LM90 is a sensor chip made by National * Semiconductor. It reports up to two temperatures (its own plus up to @@ -203,6 +203,8 @@ struct lm90_data { int kind; int flags; + u8 config_orig; /* Original configuration register value */ + /* registers values */ s8 temp8[4]; /* 0: local low limit 1: local high limit @@ -840,7 +842,7 @@ exit: static void lm90_init_client(struct i2c_client *client) { - u8 config, config_orig; + u8 config; struct lm90_data *data = i2c_get_clientdata(client); /* @@ -852,7 +854,7 @@ static void lm90_init_client(struct i2c_client *client) dev_warn(&client->dev, "Initialization failed!\n"); return; } - config_orig = config; + data->config_orig = config; /* Check Temperature Range Select */ if (data->kind == adt7461) { @@ -870,7 +872,7 @@ static void lm90_init_client(struct i2c_client *client) } config &= 0xBF; /* run */ - if (config != config_orig) /* Only write if changed */ + if (config != data->config_orig) /* Only write if changed */ i2c_smbus_write_byte_data(client, LM90_REG_W_CONFIG1, config); } @@ -885,6 +887,10 @@ static int lm90_remove(struct i2c_client *client) device_remove_file(&client->dev, &sensor_dev_attr_temp2_offset.dev_attr); + /* Restore initial configuration */ + i2c_smbus_write_byte_data(client, LM90_REG_W_CONFIG1, + data->config_orig); + kfree(data); return 0; } -- cgit v1.2.3 From 53de33427fa3d7dd62cc5ec75ce0d4e6c6d602dd Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:15 +0100 Subject: hwmon: (lm90) Add SMBus alert support Tested successfully with an ADM1032 chip on its evaluation board. It should work fine with all other chips as well. At this point this is more of a proof-of-concept, we don't do anything terribly useful on SMBus alert: we simply log the event. But this could later evolve into libsensors signaling so that user-space applications can take an appropriate action. Signed-off-by: Jean Delvare Cc: David Brownell Cc: Trent Piepho --- Documentation/hwmon/lm90 | 12 +++++++++ drivers/hwmon/lm90.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) (limited to 'drivers') diff --git a/Documentation/hwmon/lm90 b/Documentation/hwmon/lm90 index 08106ad7089c..6a03dd4bcc94 100644 --- a/Documentation/hwmon/lm90 +++ b/Documentation/hwmon/lm90 @@ -173,6 +173,18 @@ The lm90 driver will not update its values more frequently than every other second; reading them more often will do no harm, but will return 'old' values. +SMBus Alert Support +------------------- + +This driver has basic support for SMBus alert. When an alert is received, +the status register is read and the faulty temperature channel is logged. + +The Analog Devices chips (ADM1032 and ADT7461) do not implement the SMBus +alert protocol properly so additional care is needed: the ALERT output is +disabled when an alert is received, and is re-enabled only when the alarm +is gone. Otherwise the chip would block alerts from other chips in the bus +as long as the alarm is active. + PEC Support ----------- diff --git a/drivers/hwmon/lm90.c b/drivers/hwmon/lm90.c index 4cbbf1563de6..7cc2708871ab 100644 --- a/drivers/hwmon/lm90.c +++ b/drivers/hwmon/lm90.c @@ -152,6 +152,7 @@ static int lm90_detect(struct i2c_client *client, struct i2c_board_info *info); static int lm90_probe(struct i2c_client *client, const struct i2c_device_id *id); static void lm90_init_client(struct i2c_client *client); +static void lm90_alert(struct i2c_client *client, unsigned int flag); static int lm90_remove(struct i2c_client *client); static struct lm90_data *lm90_update_device(struct device *dev); @@ -186,6 +187,7 @@ static struct i2c_driver lm90_driver = { }, .probe = lm90_probe, .remove = lm90_remove, + .alert = lm90_alert, .id_table = lm90_id, .detect = lm90_detect, .address_list = normal_i2c, @@ -204,6 +206,7 @@ struct lm90_data { int flags; u8 config_orig; /* Original configuration register value */ + u8 alert_alarms; /* Which alarm bits trigger ALERT# */ /* registers values */ s8 temp8[4]; /* 0: local low limit @@ -806,6 +809,19 @@ static int lm90_probe(struct i2c_client *new_client, new_client->flags &= ~I2C_CLIENT_PEC; } + /* Different devices have different alarm bits triggering the + * ALERT# output */ + switch (data->kind) { + case lm90: + case lm99: + case lm86: + data->alert_alarms = 0x7b; + break; + default: + data->alert_alarms = 0x7c; + break; + } + /* Initialize the LM90 chip */ lm90_init_client(new_client); @@ -895,6 +911,38 @@ static int lm90_remove(struct i2c_client *client) return 0; } +static void lm90_alert(struct i2c_client *client, unsigned int flag) +{ + struct lm90_data *data = i2c_get_clientdata(client); + u8 config, alarms; + + lm90_read_reg(client, LM90_REG_R_STATUS, &alarms); + if ((alarms & 0x7f) == 0) { + dev_info(&client->dev, "Everything OK\n"); + } else { + if (alarms & 0x61) + dev_warn(&client->dev, + "temp%d out of range, please check!\n", 1); + if (alarms & 0x1a) + dev_warn(&client->dev, + "temp%d out of range, please check!\n", 2); + if (alarms & 0x04) + dev_warn(&client->dev, + "temp%d diode open, please check!\n", 2); + + /* Disable ALERT# output, because these chips don't implement + SMBus alert correctly; they should only hold the alert line + low briefly. */ + if ((data->kind == adm1032 || data->kind == adt7461) + && (alarms & data->alert_alarms)) { + dev_dbg(&client->dev, "Disabling ALERT#\n"); + lm90_read_reg(client, LM90_REG_R_CONFIG1, &config); + i2c_smbus_write_byte_data(client, LM90_REG_W_CONFIG1, + config | 0x80); + } + } +} + static int lm90_read16(struct i2c_client *client, u8 regh, u8 regl, u16 *value) { int err; @@ -982,6 +1030,21 @@ static struct lm90_data *lm90_update_device(struct device *dev) } lm90_read_reg(client, LM90_REG_R_STATUS, &data->alarms); + /* Re-enable ALERT# output if it was originally enabled and + * relevant alarms are all clear */ + if ((data->config_orig & 0x80) == 0 + && (data->alarms & data->alert_alarms) == 0) { + u8 config; + + lm90_read_reg(client, LM90_REG_R_CONFIG1, &config); + if (config & 0x80) { + dev_dbg(&client->dev, "Re-enabling ALERT#\n"); + i2c_smbus_write_byte_data(client, + LM90_REG_W_CONFIG1, + config & ~0x80); + } + } + data->last_updated = jiffies; data->valid = 1; } -- cgit v1.2.3 From b99883dcd565e30299a6c5c3250725a4d48a8253 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:15 +0100 Subject: hwmon: (it87) Display fan outputs in automatic mode as such The it87 driver doesn't yet support automatic fan control. Let it at least tell the user when a fan output is in automatic mode. Also let the user switch from automatic mode (possibly set by the BIOS) to manual mode and back without losing the settings. Signed-off-by: Jean Delvare --- drivers/hwmon/it87.c | 99 ++++++++++++++++++++++++++++++++-------------------- 1 file changed, 61 insertions(+), 38 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index 0ffe84d190bb..49022bd2a0a5 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -281,7 +281,14 @@ struct it87_data { u32 alarms; /* Register encoding, combined */ u8 fan_main_ctrl; /* Register value */ u8 fan_ctl; /* Register value */ - u8 manual_pwm_ctl[3]; /* manual PWM value set by user */ + + /* The following 3 arrays correspond to the same registers. The + * meaning of bits 6-0 depends on the value of bit 7, and we want + * to preserve settings on mode changes, so we have to track all + * values separately. */ + u8 pwm_ctrl[3]; /* Register value */ + u8 pwm_duty[3]; /* Manual PWM value set by user (bit 6-0) */ + u8 pwm_temp_map[3]; /* PWM to temp. chan. mapping (bits 1-0) */ }; static inline int has_16bit_fans(const struct it87_data *data) @@ -531,6 +538,19 @@ show_sensor_offset(2); show_sensor_offset(3); /* 3 Fans */ + +static int pwm_mode(const struct it87_data *data, int nr) +{ + int ctrl = data->fan_main_ctrl & (1 << nr); + + if (ctrl == 0) /* Full speed */ + return 0; + if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */ + return 2; + else /* Manual mode */ + return 1; +} + static ssize_t show_fan(struct device *dev, struct device_attribute *attr, char *buf) { @@ -567,7 +587,7 @@ static ssize_t show_pwm_enable(struct device *dev, struct device_attribute *attr int nr = sensor_attr->index; struct it87_data *data = it87_update_device(dev); - return sprintf(buf,"%d\n", (data->fan_main_ctrl & (1 << nr)) ? 1 : 0); + return sprintf(buf, "%d\n", pwm_mode(data, nr)); } static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, char *buf) @@ -576,7 +596,7 @@ static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, int nr = sensor_attr->index; struct it87_data *data = it87_update_device(dev); - return sprintf(buf,"%d\n", data->manual_pwm_ctl[nr]); + return sprintf(buf, "%d\n", PWM_FROM_REG(data->pwm_duty[nr])); } static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr, char *buf) @@ -660,6 +680,9 @@ static ssize_t set_pwm_enable(struct device *dev, struct it87_data *data = dev_get_drvdata(dev); int val = simple_strtol(buf, NULL, 10); + if (val < 0 || val > 2) + return -EINVAL; + mutex_lock(&data->update_lock); if (val == 0) { @@ -670,15 +693,15 @@ static ssize_t set_pwm_enable(struct device *dev, /* set on/off mode */ data->fan_main_ctrl &= ~(1 << nr); it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl); - } else if (val == 1) { + } else { + if (val == 1) /* Manual mode */ + data->pwm_ctrl[nr] = data->pwm_duty[nr]; + else /* Automatic mode */ + data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr]; + it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]); /* set SmartGuardian mode */ data->fan_main_ctrl |= (1 << nr); it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl); - /* set saved pwm value, clear FAN_CTLX PWM mode bit */ - it87_write_value(data, IT87_REG_PWM(nr), PWM_TO_REG(data->manual_pwm_ctl[nr])); - } else { - mutex_unlock(&data->update_lock); - return -EINVAL; } mutex_unlock(&data->update_lock); @@ -697,9 +720,13 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, return -EINVAL; mutex_lock(&data->update_lock); - data->manual_pwm_ctl[nr] = val; - if (data->fan_main_ctrl & (1 << nr)) - it87_write_value(data, IT87_REG_PWM(nr), PWM_TO_REG(data->manual_pwm_ctl[nr])); + data->pwm_duty[nr] = PWM_TO_REG(val); + /* If we are in manual mode, write the duty cycle immediately; + * otherwise, just store it for later use. */ + if (!(data->pwm_ctrl[nr] & 0x80)) { + data->pwm_ctrl[nr] = data->pwm_duty[nr]; + it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]); + } mutex_unlock(&data->update_lock); return count; } @@ -1387,15 +1414,17 @@ static void __devinit it87_init_device(struct platform_device *pdev) int tmp, i; u8 mask; - /* initialize to sane defaults: - * - if the chip is in manual pwm mode, this will be overwritten with - * the actual settings on the chip (so in this case, initialization - * is not needed) - * - if in automatic or on/off mode, we could switch to manual mode, - * read the registers and set manual_pwm_ctl accordingly, but currently - * this is not implemented, so we initialize to something sane */ + /* For each PWM channel: + * - If it is in automatic mode, setting to manual mode should set + * the fan to full speed by default. + * - If it is in manual mode, we need a mapping to temperature + * channels to use when later setting to automatic mode later. + * Use a 1:1 mapping by default (we are clueless.) + * In both cases, the value can (and should) be changed by the user + * prior to switching to a different mode. */ for (i = 0; i < 3; i++) { - data->manual_pwm_ctl[i] = 0xff; + data->pwm_temp_map[i] = i; + data->pwm_duty[i] = 0x7f; /* Full speed */ } /* Some chips seem to have default value 0xff for all limit @@ -1461,30 +1490,21 @@ static void __devinit it87_init_device(struct platform_device *pdev) /* Fan input pins may be used for alternative functions */ data->has_fan &= ~sio_data->skip_fan; - /* Set current fan mode registers and the default settings for the - * other mode registers */ - for (i = 0; i < 3; i++) { - if (data->fan_main_ctrl & (1 << i)) { - /* pwm mode */ - tmp = it87_read_value(data, IT87_REG_PWM(i)); - if (tmp & 0x80) { - /* automatic pwm - not yet implemented, but - * leave the settings made by the BIOS alone - * until a change is requested via the sysfs - * interface */ - } else { - /* manual pwm */ - data->manual_pwm_ctl[i] = PWM_FROM_REG(tmp); - } - } - } - /* Start monitoring */ it87_write_value(data, IT87_REG_CONFIG, (it87_read_value(data, IT87_REG_CONFIG) & 0x36) | (update_vbat ? 0x41 : 0x01)); } +static void it87_update_pwm_ctrl(struct it87_data *data, int nr) +{ + data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM(nr)); + if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */ + data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; + else /* Manual mode */ + data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f; +} + static struct it87_data *it87_update_device(struct device *dev) { struct it87_data *data = dev_get_drvdata(dev); @@ -1551,9 +1571,12 @@ static struct it87_data *it87_update_device(struct device *dev) it87_read_value(data, IT87_REG_ALARM1) | (it87_read_value(data, IT87_REG_ALARM2) << 8) | (it87_read_value(data, IT87_REG_ALARM3) << 16); + data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL); + for (i = 0; i < 3; i++) + it87_update_pwm_ctrl(data, i); data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE); /* The 8705 does not have VID capability. -- cgit v1.2.3 From 94ac7ee616809d1c919f222037330eca211da9e4 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:16 +0100 Subject: hwmon: (it87) Expose the PWM/temperature mappings Let the user read the PWM-to-temperature mappings. Until the trip points are also exposed, this is essentially a way to know how the BIOS has set things up. The ability to change the settings will be added later, together with the trip points. Signed-off-by: Jean Delvare --- drivers/hwmon/it87.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 69 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index 49022bd2a0a5..41b55a74ce89 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -751,6 +751,59 @@ static ssize_t set_pwm_freq(struct device *dev, return count; } +static ssize_t show_pwm_temp_map(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); + int nr = sensor_attr->index; + + struct it87_data *data = it87_update_device(dev); + int map; + + if (data->pwm_temp_map[nr] < 3) + map = 1 << data->pwm_temp_map[nr]; + else + map = 0; /* Should never happen */ + return sprintf(buf, "%d\n", map); +} +static ssize_t set_pwm_temp_map(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); + int nr = sensor_attr->index; + + struct it87_data *data = dev_get_drvdata(dev); + long val; + u8 reg; + + if (strict_strtol(buf, 10, &val) < 0) + return -EINVAL; + + switch (val) { + case (1 << 0): + reg = 0x00; + break; + case (1 << 1): + reg = 0x01; + break; + case (1 << 2): + reg = 0x02; + break; + default: + return -EINVAL; + } + + mutex_lock(&data->update_lock); + data->pwm_temp_map[nr] = reg; + /* If we are in automatic mode, write the temp mapping immediately; + * otherwise, just store it for later use. */ + if (data->pwm_ctrl[nr] & 0x80) { + data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr]; + it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]); + } + mutex_unlock(&data->update_lock); + return count; +} #define show_fan_offset(offset) \ static SENSOR_DEVICE_ATTR(fan##offset##_input, S_IRUGO, \ @@ -771,7 +824,10 @@ static SENSOR_DEVICE_ATTR(pwm##offset, S_IRUGO | S_IWUSR, \ show_pwm, set_pwm, offset - 1); \ static DEVICE_ATTR(pwm##offset##_freq, \ (offset == 1 ? S_IRUGO | S_IWUSR : S_IRUGO), \ - show_pwm_freq, (offset == 1 ? set_pwm_freq : NULL)); + show_pwm_freq, (offset == 1 ? set_pwm_freq : NULL)); \ +static SENSOR_DEVICE_ATTR(pwm##offset##_auto_channels_temp, \ + S_IRUGO, show_pwm_temp_map, set_pwm_temp_map, \ + offset - 1); show_pwm_offset(1); show_pwm_offset(2); @@ -995,6 +1051,9 @@ static struct attribute *it87_attributes_opt[] = { &dev_attr_pwm1_freq.attr, &dev_attr_pwm2_freq.attr, &dev_attr_pwm3_freq.attr, + &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr, + &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr, + &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr, &dev_attr_vrm.attr, &dev_attr_cpu0_vid.attr, @@ -1268,7 +1327,9 @@ static int __devinit it87_probe(struct platform_device *pdev) || (err = device_create_file(dev, &sensor_dev_attr_pwm1.dev_attr)) || (err = device_create_file(dev, - &dev_attr_pwm1_freq))) + &dev_attr_pwm1_freq)) + || (err = device_create_file(dev, + &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr))) goto ERROR4; } if (!(sio_data->skip_pwm & (1 << 1))) { @@ -1277,7 +1338,9 @@ static int __devinit it87_probe(struct platform_device *pdev) || (err = device_create_file(dev, &sensor_dev_attr_pwm2.dev_attr)) || (err = device_create_file(dev, - &dev_attr_pwm2_freq))) + &dev_attr_pwm2_freq)) + || (err = device_create_file(dev, + &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr))) goto ERROR4; } if (!(sio_data->skip_pwm & (1 << 2))) { @@ -1286,7 +1349,9 @@ static int __devinit it87_probe(struct platform_device *pdev) || (err = device_create_file(dev, &sensor_dev_attr_pwm3.dev_attr)) || (err = device_create_file(dev, - &dev_attr_pwm3_freq))) + &dev_attr_pwm3_freq)) + || (err = device_create_file(dev, + &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr))) goto ERROR4; } } -- cgit v1.2.3 From 723a0aa0a10f111d7e9e0977d51ac996bf8edbbf Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:16 +0100 Subject: hwmon: (it87) Refactor attributes creation and removal There is a lot of code redundancy in the creation of the fan and pwm attributes. Move these attributes to arrays so that the code can be simplified. This in turns makes the attributes removal code larger, so move it to a separate function that can be called in both the standard removal case and the error path during probing. Signed-off-by: Jean Delvare --- drivers/hwmon/it87.c | 233 +++++++++++++++++++++++---------------------------- 1 file changed, 103 insertions(+), 130 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index 41b55a74ce89..5df0824fc832 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -1014,47 +1014,100 @@ static const struct attribute_group it87_group = { .attrs = it87_attributes, }; -static struct attribute *it87_attributes_opt[] = { +static struct attribute *it87_attributes_fan16[5][3+1] = { { &sensor_dev_attr_fan1_input16.dev_attr.attr, &sensor_dev_attr_fan1_min16.dev_attr.attr, + &sensor_dev_attr_fan1_alarm.dev_attr.attr, + NULL +}, { &sensor_dev_attr_fan2_input16.dev_attr.attr, &sensor_dev_attr_fan2_min16.dev_attr.attr, + &sensor_dev_attr_fan2_alarm.dev_attr.attr, + NULL +}, { &sensor_dev_attr_fan3_input16.dev_attr.attr, &sensor_dev_attr_fan3_min16.dev_attr.attr, + &sensor_dev_attr_fan3_alarm.dev_attr.attr, + NULL +}, { &sensor_dev_attr_fan4_input16.dev_attr.attr, &sensor_dev_attr_fan4_min16.dev_attr.attr, + &sensor_dev_attr_fan4_alarm.dev_attr.attr, + NULL +}, { &sensor_dev_attr_fan5_input16.dev_attr.attr, &sensor_dev_attr_fan5_min16.dev_attr.attr, + &sensor_dev_attr_fan5_alarm.dev_attr.attr, + NULL +} }; + +static const struct attribute_group it87_group_fan16[5] = { + { .attrs = it87_attributes_fan16[0] }, + { .attrs = it87_attributes_fan16[1] }, + { .attrs = it87_attributes_fan16[2] }, + { .attrs = it87_attributes_fan16[3] }, + { .attrs = it87_attributes_fan16[4] }, +}; +static struct attribute *it87_attributes_fan[3][4+1] = { { &sensor_dev_attr_fan1_input.dev_attr.attr, &sensor_dev_attr_fan1_min.dev_attr.attr, &sensor_dev_attr_fan1_div.dev_attr.attr, + &sensor_dev_attr_fan1_alarm.dev_attr.attr, + NULL +}, { &sensor_dev_attr_fan2_input.dev_attr.attr, &sensor_dev_attr_fan2_min.dev_attr.attr, &sensor_dev_attr_fan2_div.dev_attr.attr, + &sensor_dev_attr_fan2_alarm.dev_attr.attr, + NULL +}, { &sensor_dev_attr_fan3_input.dev_attr.attr, &sensor_dev_attr_fan3_min.dev_attr.attr, &sensor_dev_attr_fan3_div.dev_attr.attr, - - &sensor_dev_attr_fan1_alarm.dev_attr.attr, - &sensor_dev_attr_fan2_alarm.dev_attr.attr, &sensor_dev_attr_fan3_alarm.dev_attr.attr, - &sensor_dev_attr_fan4_alarm.dev_attr.attr, - &sensor_dev_attr_fan5_alarm.dev_attr.attr, + NULL +} }; + +static const struct attribute_group it87_group_fan[3] = { + { .attrs = it87_attributes_fan[0] }, + { .attrs = it87_attributes_fan[1] }, + { .attrs = it87_attributes_fan[2] }, +}; + +static const struct attribute_group * +it87_get_fan_group(const struct it87_data *data) +{ + return has_16bit_fans(data) ? it87_group_fan16 : it87_group_fan; +} +static struct attribute *it87_attributes_pwm[3][4+1] = { { &sensor_dev_attr_pwm1_enable.dev_attr.attr, - &sensor_dev_attr_pwm2_enable.dev_attr.attr, - &sensor_dev_attr_pwm3_enable.dev_attr.attr, &sensor_dev_attr_pwm1.dev_attr.attr, - &sensor_dev_attr_pwm2.dev_attr.attr, - &sensor_dev_attr_pwm3.dev_attr.attr, &dev_attr_pwm1_freq.attr, - &dev_attr_pwm2_freq.attr, - &dev_attr_pwm3_freq.attr, &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr, + NULL +}, { + &sensor_dev_attr_pwm2_enable.dev_attr.attr, + &sensor_dev_attr_pwm2.dev_attr.attr, + &dev_attr_pwm2_freq.attr, &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr, + NULL +}, { + &sensor_dev_attr_pwm3_enable.dev_attr.attr, + &sensor_dev_attr_pwm3.dev_attr.attr, + &dev_attr_pwm3_freq.attr, &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr, + NULL +} }; +static const struct attribute_group it87_group_pwm[3] = { + { .attrs = it87_attributes_pwm[0] }, + { .attrs = it87_attributes_pwm[1] }, + { .attrs = it87_attributes_pwm[2] }, +}; + +static struct attribute *it87_attributes_opt[] = { &dev_attr_vrm.attr, &dev_attr_cpu0_vid.attr, NULL @@ -1179,13 +1232,35 @@ exit: return err; } +static void it87_remove_files(struct device *dev) +{ + struct it87_data *data = platform_get_drvdata(pdev); + struct it87_sio_data *sio_data = dev->platform_data; + const struct attribute_group *fan_group = it87_get_fan_group(data); + int i; + + sysfs_remove_group(&dev->kobj, &it87_group); + for (i = 0; i < 5; i++) { + if (!(data->has_fan & (1 << i))) + continue; + sysfs_remove_group(&dev->kobj, &fan_group[i]); + } + for (i = 0; i < 3; i++) { + if (sio_data->skip_pwm & (1 << 0)) + continue; + sysfs_remove_group(&dev->kobj, &it87_group_pwm[i]); + } + sysfs_remove_group(&dev->kobj, &it87_group_opt); +} + static int __devinit it87_probe(struct platform_device *pdev) { struct it87_data *data; struct resource *res; struct device *dev = &pdev->dev; struct it87_sio_data *sio_data = dev->platform_data; - int err = 0; + const struct attribute_group *fan_group; + int err = 0, i; int enable_pwm_interface; static const char *names[] = { "it87", @@ -1236,122 +1311,22 @@ static int __devinit it87_probe(struct platform_device *pdev) goto ERROR2; /* Do not create fan files for disabled fans */ - if (has_16bit_fans(data)) { - /* 16-bit tachometers */ - if (data->has_fan & (1 << 0)) { - if ((err = device_create_file(dev, - &sensor_dev_attr_fan1_input16.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan1_min16.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan1_alarm.dev_attr))) - goto ERROR4; - } - if (data->has_fan & (1 << 1)) { - if ((err = device_create_file(dev, - &sensor_dev_attr_fan2_input16.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan2_min16.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan2_alarm.dev_attr))) - goto ERROR4; - } - if (data->has_fan & (1 << 2)) { - if ((err = device_create_file(dev, - &sensor_dev_attr_fan3_input16.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan3_min16.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan3_alarm.dev_attr))) - goto ERROR4; - } - if (data->has_fan & (1 << 3)) { - if ((err = device_create_file(dev, - &sensor_dev_attr_fan4_input16.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan4_min16.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan4_alarm.dev_attr))) - goto ERROR4; - } - if (data->has_fan & (1 << 4)) { - if ((err = device_create_file(dev, - &sensor_dev_attr_fan5_input16.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan5_min16.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan5_alarm.dev_attr))) - goto ERROR4; - } - } else { - /* 8-bit tachometers with clock divider */ - if (data->has_fan & (1 << 0)) { - if ((err = device_create_file(dev, - &sensor_dev_attr_fan1_input.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan1_min.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan1_div.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan1_alarm.dev_attr))) - goto ERROR4; - } - if (data->has_fan & (1 << 1)) { - if ((err = device_create_file(dev, - &sensor_dev_attr_fan2_input.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan2_min.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan2_div.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan2_alarm.dev_attr))) - goto ERROR4; - } - if (data->has_fan & (1 << 2)) { - if ((err = device_create_file(dev, - &sensor_dev_attr_fan3_input.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan3_min.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan3_div.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_fan3_alarm.dev_attr))) - goto ERROR4; - } + fan_group = it87_get_fan_group(data); + for (i = 0; i < 5; i++) { + if (!(data->has_fan & (1 << i))) + continue; + err = sysfs_create_group(&dev->kobj, &fan_group[i]); + if (err) + goto ERROR4; } if (enable_pwm_interface) { - if (!(sio_data->skip_pwm & (1 << 0))) { - if ((err = device_create_file(dev, - &sensor_dev_attr_pwm1_enable.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_pwm1.dev_attr)) - || (err = device_create_file(dev, - &dev_attr_pwm1_freq)) - || (err = device_create_file(dev, - &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr))) - goto ERROR4; - } - if (!(sio_data->skip_pwm & (1 << 1))) { - if ((err = device_create_file(dev, - &sensor_dev_attr_pwm2_enable.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_pwm2.dev_attr)) - || (err = device_create_file(dev, - &dev_attr_pwm2_freq)) - || (err = device_create_file(dev, - &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr))) - goto ERROR4; - } - if (!(sio_data->skip_pwm & (1 << 2))) { - if ((err = device_create_file(dev, - &sensor_dev_attr_pwm3_enable.dev_attr)) - || (err = device_create_file(dev, - &sensor_dev_attr_pwm3.dev_attr)) - || (err = device_create_file(dev, - &dev_attr_pwm3_freq)) - || (err = device_create_file(dev, - &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr))) + for (i = 0; i < 3; i++) { + if (sio_data->skip_pwm & (1 << i)) + continue; + err = sysfs_create_group(&dev->kobj, + &it87_group_pwm[i]); + if (err) goto ERROR4; } } @@ -1376,8 +1351,7 @@ static int __devinit it87_probe(struct platform_device *pdev) return 0; ERROR4: - sysfs_remove_group(&dev->kobj, &it87_group); - sysfs_remove_group(&dev->kobj, &it87_group_opt); + it87_remove_files(dev); ERROR2: platform_set_drvdata(pdev, NULL); kfree(data); @@ -1392,8 +1366,7 @@ static int __devexit it87_remove(struct platform_device *pdev) struct it87_data *data = platform_get_drvdata(pdev); hwmon_device_unregister(data->hwmon_dev); - sysfs_remove_group(&pdev->dev.kobj, &it87_group); - sysfs_remove_group(&pdev->dev.kobj, &it87_group_opt); + it87_remove_files(&pdev->dev); release_region(data->addr, IT87_EC_EXTENT); platform_set_drvdata(pdev, NULL); -- cgit v1.2.3 From 6a8d7acfbef8ac6bf34421eae980f903cbe36874 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:16 +0100 Subject: hwmon: (it87) Create vid attributes by group Only VID-related attributes are left in it87_attributes_opt, so we might as well rename it to it87_attributes_vid and use this group to create all attributes at once. Signed-off-by: Jean Delvare --- drivers/hwmon/it87.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index 5df0824fc832..7a349e066fdc 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -1107,14 +1107,14 @@ static const struct attribute_group it87_group_pwm[3] = { { .attrs = it87_attributes_pwm[2] }, }; -static struct attribute *it87_attributes_opt[] = { +static struct attribute *it87_attributes_vid[] = { &dev_attr_vrm.attr, &dev_attr_cpu0_vid.attr, NULL }; -static const struct attribute_group it87_group_opt = { - .attrs = it87_attributes_opt, +static const struct attribute_group it87_group_vid = { + .attrs = it87_attributes_vid, }; /* SuperIO detection - will change isa_address if a chip is found */ @@ -1250,7 +1250,8 @@ static void it87_remove_files(struct device *dev) continue; sysfs_remove_group(&dev->kobj, &it87_group_pwm[i]); } - sysfs_remove_group(&dev->kobj, &it87_group_opt); + if (!sio_data->skip_vid) + sysfs_remove_group(&dev->kobj, &it87_group_vid); } static int __devinit it87_probe(struct platform_device *pdev) @@ -1335,10 +1336,8 @@ static int __devinit it87_probe(struct platform_device *pdev) data->vrm = vid_which_vrm(); /* VID reading from Super-I/O config space if available */ data->vid = sio_data->vid_value; - if ((err = device_create_file(dev, - &dev_attr_vrm)) - || (err = device_create_file(dev, - &dev_attr_cpu0_vid))) + err = sysfs_create_group(&dev->kobj, &it87_group_vid); + if (err) goto ERROR4; } -- cgit v1.2.3 From d9b327c310030fa80abbbc9eaaca9f1a6228dbf3 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:17 +0100 Subject: hwmon: (it87) Add support for beep on alarm The IT87xxF chips support beeping on alarm, if properly wired and configured. There is one control bit for each input type (temperature, fan, voltage.) Let the user see and change them. Signed-off-by: Jean Delvare --- Documentation/hwmon/it87 | 4 ++ drivers/hwmon/it87.c | 122 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 126 insertions(+) (limited to 'drivers') diff --git a/Documentation/hwmon/it87 b/Documentation/hwmon/it87 index f9ba96c0ac4a..23b773fa2675 100644 --- a/Documentation/hwmon/it87 +++ b/Documentation/hwmon/it87 @@ -136,6 +136,10 @@ registers are read whenever any data is read (unless it is less than 1.5 seconds since the last update). This means that you can easily miss once-only alarms. +Out-of-limit readings can also result in beeping, if the chip is properly +wired and configured. Beeping can be enabled or disabled per sensor type +(temperatures, voltages and fans.) + The IT87xx only updates its values each 1.5 seconds; reading it more often will do no harm, but will return 'old' values. diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index 7a349e066fdc..d70c6ec31725 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -128,6 +128,7 @@ superio_exit(void) #define IT87_SIO_GPIO5_REG 0x29 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */ #define IT87_SIO_VID_REG 0xfc /* VID value */ +#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */ /* Update battery voltage after every reading if true */ static int update_vbat; @@ -187,6 +188,7 @@ static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87 }; #define IT87_REG_VIN_ENABLE 0x50 #define IT87_REG_TEMP_ENABLE 0x51 +#define IT87_REG_BEEP_ENABLE 0x5c #define IT87_REG_CHIPID 0x58 @@ -246,6 +248,7 @@ struct it87_sio_data { /* Values read from Super-I/O config space */ u8 revision; u8 vid_value; + u8 beep_pin; /* Features skipped based on config or DMI */ u8 skip_vid; u8 skip_fan; @@ -279,6 +282,7 @@ struct it87_data { u8 vid; /* Register encoding, combined */ u8 vrm; u32 alarms; /* Register encoding, combined */ + u8 beeps; /* Register encoding */ u8 fan_main_ctrl; /* Register value */ u8 fan_ctl; /* Register value */ @@ -919,6 +923,55 @@ static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16); static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17); static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18); +static ssize_t show_beep(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int bitnr = to_sensor_dev_attr(attr)->index; + struct it87_data *data = it87_update_device(dev); + return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1); +} +static ssize_t set_beep(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int bitnr = to_sensor_dev_attr(attr)->index; + struct it87_data *data = dev_get_drvdata(dev); + long val; + + if (strict_strtol(buf, 10, &val) < 0 + || (val != 0 && val != 1)) + return -EINVAL; + + mutex_lock(&data->update_lock); + data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); + if (val) + data->beeps |= (1 << bitnr); + else + data->beeps &= ~(1 << bitnr); + it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps); + mutex_unlock(&data->update_lock); + return count; +} + +static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR, + show_beep, set_beep, 1); +static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1); +static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1); +static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1); +static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1); +static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1); +static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1); +static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1); +/* fanX_beep writability is set later */ +static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0); +static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0); +static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0); +static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0); +static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0); +static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR, + show_beep, set_beep, 2); +static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2); +static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2); + static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1014,6 +1067,26 @@ static const struct attribute_group it87_group = { .attrs = it87_attributes, }; +static struct attribute *it87_attributes_beep[] = { + &sensor_dev_attr_in0_beep.dev_attr.attr, + &sensor_dev_attr_in1_beep.dev_attr.attr, + &sensor_dev_attr_in2_beep.dev_attr.attr, + &sensor_dev_attr_in3_beep.dev_attr.attr, + &sensor_dev_attr_in4_beep.dev_attr.attr, + &sensor_dev_attr_in5_beep.dev_attr.attr, + &sensor_dev_attr_in6_beep.dev_attr.attr, + &sensor_dev_attr_in7_beep.dev_attr.attr, + + &sensor_dev_attr_temp1_beep.dev_attr.attr, + &sensor_dev_attr_temp2_beep.dev_attr.attr, + &sensor_dev_attr_temp3_beep.dev_attr.attr, + NULL +}; + +static const struct attribute_group it87_group_beep = { + .attrs = it87_attributes_beep, +}; + static struct attribute *it87_attributes_fan16[5][3+1] = { { &sensor_dev_attr_fan1_input16.dev_attr.attr, &sensor_dev_attr_fan1_min16.dev_attr.attr, @@ -1107,6 +1180,14 @@ static const struct attribute_group it87_group_pwm[3] = { { .attrs = it87_attributes_pwm[2] }, }; +static struct attribute *it87_attributes_fan_beep[] = { + &sensor_dev_attr_fan1_beep.dev_attr.attr, + &sensor_dev_attr_fan2_beep.dev_attr.attr, + &sensor_dev_attr_fan3_beep.dev_attr.attr, + &sensor_dev_attr_fan4_beep.dev_attr.attr, + &sensor_dev_attr_fan5_beep.dev_attr.attr, +}; + static struct attribute *it87_attributes_vid[] = { &dev_attr_vrm.attr, &dev_attr_cpu0_vid.attr, @@ -1174,6 +1255,10 @@ static int __init it87_find(unsigned short *address, if (sio_data->type == it87) { /* The IT8705F doesn't have VID pins at all */ sio_data->skip_vid = 1; + + /* The IT8705F has a different LD number for GPIO */ + superio_select(5); + sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f; } else { int reg; @@ -1207,7 +1292,11 @@ static int __init it87_find(unsigned short *address, pr_info("it87: in3 is VCC (+5V)\n"); if (reg & (1 << 1)) pr_info("it87: in7 is VCCH (+5V Stand-By)\n"); + + sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f; } + if (sio_data->beep_pin) + pr_info("it87: Beeping is supported\n"); /* Disable specific features based on DMI strings */ board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR); @@ -1240,10 +1329,15 @@ static void it87_remove_files(struct device *dev) int i; sysfs_remove_group(&dev->kobj, &it87_group); + if (sio_data->beep_pin) + sysfs_remove_group(&dev->kobj, &it87_group_beep); for (i = 0; i < 5; i++) { if (!(data->has_fan & (1 << i))) continue; sysfs_remove_group(&dev->kobj, &fan_group[i]); + if (sio_data->beep_pin) + sysfs_remove_file(&dev->kobj, + it87_attributes_fan_beep[i]); } for (i = 0; i < 3; i++) { if (sio_data->skip_pwm & (1 << 0)) @@ -1263,6 +1357,7 @@ static int __devinit it87_probe(struct platform_device *pdev) const struct attribute_group *fan_group; int err = 0, i; int enable_pwm_interface; + int fan_beep_need_rw; static const char *names[] = { "it87", "it8712", @@ -1311,14 +1406,40 @@ static int __devinit it87_probe(struct platform_device *pdev) if ((err = sysfs_create_group(&dev->kobj, &it87_group))) goto ERROR2; + if (sio_data->beep_pin) { + err = sysfs_create_group(&dev->kobj, &it87_group_beep); + if (err) + goto ERROR4; + } + /* Do not create fan files for disabled fans */ fan_group = it87_get_fan_group(data); + fan_beep_need_rw = 1; for (i = 0; i < 5; i++) { if (!(data->has_fan & (1 << i))) continue; err = sysfs_create_group(&dev->kobj, &fan_group[i]); if (err) goto ERROR4; + + if (sio_data->beep_pin) { + err = sysfs_create_file(&dev->kobj, + it87_attributes_fan_beep[i]); + if (err) + goto ERROR4; + if (!fan_beep_need_rw) + continue; + + /* As we have a single beep enable bit for all fans, + * only the first enabled fan has a writable attribute + * for it. */ + if (sysfs_chmod_file(&dev->kobj, + it87_attributes_fan_beep[i], + S_IRUGO | S_IWUSR)) + dev_dbg(dev, "chmod +w fan%d_beep failed\n", + i + 1); + fan_beep_need_rw = 0; + } } if (enable_pwm_interface) { @@ -1608,6 +1729,7 @@ static struct it87_data *it87_update_device(struct device *dev) it87_read_value(data, IT87_REG_ALARM1) | (it87_read_value(data, IT87_REG_ALARM2) << 8) | (it87_read_value(data, IT87_REG_ALARM3) << 16); + data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); -- cgit v1.2.3 From 5f2dc798cadd144659cc9f5b6fc2a0a12c6dbdb0 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:18 +0100 Subject: hwmon: (it87) Fix many checkpatch errors and warnings Fix 20 errors and 11 warnings reported by the checkpatch script. The remainining errors would require more work. The remaining warnings will be addressed later. Signed-off-by: Jean Delvare --- drivers/hwmon/it87.c | 162 +++++++++++++++++++++++++++------------------------ 1 file changed, 87 insertions(+), 75 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index d70c6ec31725..96306a6f844e 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -1,40 +1,40 @@ /* - it87.c - Part of lm_sensors, Linux kernel modules for hardware - monitoring. - - The IT8705F is an LPC-based Super I/O part that contains UARTs, a - parallel port, an IR port, a MIDI port, a floppy controller, etc., in - addition to an Environment Controller (Enhanced Hardware Monitor and - Fan Controller) - - This driver supports only the Environment Controller in the IT8705F and - similar parts. The other devices are supported by different drivers. - - Supports: IT8705F Super I/O chip w/LPC interface - IT8712F Super I/O chip w/LPC interface - IT8716F Super I/O chip w/LPC interface - IT8718F Super I/O chip w/LPC interface - IT8720F Super I/O chip w/LPC interface - IT8726F Super I/O chip w/LPC interface - Sis950 A clone of the IT8705F - - Copyright (C) 2001 Chris Gauthron - Copyright (C) 2005-2007 Jean Delvare - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ + * it87.c - Part of lm_sensors, Linux kernel modules for hardware + * monitoring. + * + * The IT8705F is an LPC-based Super I/O part that contains UARTs, a + * parallel port, an IR port, a MIDI port, a floppy controller, etc., in + * addition to an Environment Controller (Enhanced Hardware Monitor and + * Fan Controller) + * + * This driver supports only the Environment Controller in the IT8705F and + * similar parts. The other devices are supported by different drivers. + * + * Supports: IT8705F Super I/O chip w/LPC interface + * IT8712F Super I/O chip w/LPC interface + * IT8716F Super I/O chip w/LPC interface + * IT8718F Super I/O chip w/LPC interface + * IT8720F Super I/O chip w/LPC interface + * IT8726F Super I/O chip w/LPC interface + * Sis950 A clone of the IT8705F + * + * Copyright (C) 2001 Chris Gauthron + * Copyright (C) 2005-2010 Jean Delvare + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ #include #include @@ -494,8 +494,9 @@ static ssize_t show_sensor(struct device *dev, struct device_attribute *attr, int nr = sensor_attr->index; struct it87_data *data = it87_update_device(dev); - u8 reg = data->sensor; /* In case the value is updated while we use it */ - + u8 reg = data->sensor; /* In case the value is updated while + we use it */ + if (reg & (1 << nr)) return sprintf(buf, "3\n"); /* thermal diode */ if (reg & (8 << nr)) @@ -522,9 +523,9 @@ static ssize_t set_sensor(struct device *dev, struct device_attribute *attr, } /* 3 = thermal diode; 4 = thermistor; 0 = disabled */ if (val == 3) - data->sensor |= 1 << nr; + data->sensor |= 1 << nr; else if (val == 4) - data->sensor |= 8 << nr; + data->sensor |= 8 << nr; else if (val != 0) { mutex_unlock(&data->update_lock); return -EINVAL; @@ -562,7 +563,7 @@ static ssize_t show_fan(struct device *dev, struct device_attribute *attr, int nr = sensor_attr->index; struct it87_data *data = it87_update_device(dev); - return sprintf(buf,"%d\n", FAN_FROM_REG(data->fan[nr], + return sprintf(buf, "%d\n", FAN_FROM_REG(data->fan[nr], DIV_FROM_REG(data->fan_div[nr]))); } static ssize_t show_fan_min(struct device *dev, struct device_attribute *attr, @@ -572,8 +573,8 @@ static ssize_t show_fan_min(struct device *dev, struct device_attribute *attr, int nr = sensor_attr->index; struct it87_data *data = it87_update_device(dev); - return sprintf(buf,"%d\n", - FAN_FROM_REG(data->fan_min[nr], DIV_FROM_REG(data->fan_div[nr]))); + return sprintf(buf, "%d\n", FAN_FROM_REG(data->fan_min[nr], + DIV_FROM_REG(data->fan_div[nr]))); } static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr, char *buf) @@ -584,8 +585,8 @@ static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr, struct it87_data *data = it87_update_device(dev); return sprintf(buf, "%d\n", DIV_FROM_REG(data->fan_div[nr])); } -static ssize_t show_pwm_enable(struct device *dev, struct device_attribute *attr, - char *buf) +static ssize_t show_pwm_enable(struct device *dev, + struct device_attribute *attr, char *buf) { struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); int nr = sensor_attr->index; @@ -623,9 +624,15 @@ static ssize_t set_fan_min(struct device *dev, struct device_attribute *attr, mutex_lock(&data->update_lock); reg = it87_read_value(data, IT87_REG_FAN_DIV); switch (nr) { - case 0: data->fan_div[nr] = reg & 0x07; break; - case 1: data->fan_div[nr] = (reg >> 3) & 0x07; break; - case 2: data->fan_div[nr] = (reg & 0x40) ? 3 : 1; break; + case 0: + data->fan_div[nr] = reg & 0x07; + break; + case 1: + data->fan_div[nr] = (reg >> 3) & 0x07; + break; + case 2: + data->fan_div[nr] = (reg & 0x40) ? 3 : 1; + break; } data->fan_min[nr] = FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); @@ -696,7 +703,8 @@ static ssize_t set_pwm_enable(struct device *dev, it87_write_value(data, IT87_REG_FAN_CTL, tmp | (1 << nr)); /* set on/off mode */ data->fan_main_ctrl &= ~(1 << nr); - it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl); + it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, + data->fan_main_ctrl); } else { if (val == 1) /* Manual mode */ data->pwm_ctrl[nr] = data->pwm_duty[nr]; @@ -705,7 +713,8 @@ static ssize_t set_pwm_enable(struct device *dev, it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]); /* set SmartGuardian mode */ data->fan_main_ctrl |= (1 << nr); - it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl); + it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, + data->fan_main_ctrl); } mutex_unlock(&data->update_lock); @@ -892,7 +901,8 @@ show_fan16_offset(4); show_fan16_offset(5); /* Alarms */ -static ssize_t show_alarms(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t show_alarms(struct device *dev, struct device_attribute *attr, + char *buf) { struct it87_data *data = it87_update_device(dev); return sprintf(buf, "%u\n", data->alarms); @@ -972,14 +982,14 @@ static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR, static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2); static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2); -static ssize_t -show_vrm_reg(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr, + char *buf) { struct it87_data *data = dev_get_drvdata(dev); return sprintf(buf, "%u\n", data->vrm); } -static ssize_t -store_vrm_reg(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) +static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) { struct it87_data *data = dev_get_drvdata(dev); u32 val; @@ -991,8 +1001,8 @@ store_vrm_reg(struct device *dev, struct device_attribute *attr, const char *buf } static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg); -static ssize_t -show_vid_reg(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr, + char *buf) { struct it87_data *data = it87_update_device(dev); return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm)); @@ -1375,7 +1385,8 @@ static int __devinit it87_probe(struct platform_device *pdev) goto ERROR0; } - if (!(data = kzalloc(sizeof(struct it87_data), GFP_KERNEL))) { + data = kzalloc(sizeof(struct it87_data), GFP_KERNEL); + if (!data) { err = -ENOMEM; goto ERROR1; } @@ -1403,7 +1414,8 @@ static int __devinit it87_probe(struct platform_device *pdev) it87_init_device(pdev); /* Register sysfs hooks */ - if ((err = sysfs_create_group(&dev->kobj, &it87_group))) + err = sysfs_create_group(&dev->kobj, &it87_group); + if (err) goto ERROR2; if (sio_data->beep_pin) { @@ -1623,7 +1635,8 @@ static void __devinit it87_init_device(struct platform_device *pdev) if ((data->fan_main_ctrl & mask) == 0) { /* Enable all fan tachometers */ data->fan_main_ctrl |= mask; - it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl); + it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, + data->fan_main_ctrl); } data->has_fan = (data->fan_main_ctrl >> 4) & 0x07; @@ -1672,24 +1685,22 @@ static struct it87_data *it87_update_device(struct device *dev) if (time_after(jiffies, data->last_updated + HZ + HZ / 2) || !data->valid) { - if (update_vbat) { /* Cleared after each update, so reenable. Value - returned by this read will be previous value */ + returned by this read will be previous value */ it87_write_value(data, IT87_REG_CONFIG, - it87_read_value(data, IT87_REG_CONFIG) | 0x40); + it87_read_value(data, IT87_REG_CONFIG) | 0x40); } for (i = 0; i <= 7; i++) { data->in[i] = - it87_read_value(data, IT87_REG_VIN(i)); + it87_read_value(data, IT87_REG_VIN(i)); data->in_min[i] = - it87_read_value(data, IT87_REG_VIN_MIN(i)); + it87_read_value(data, IT87_REG_VIN_MIN(i)); data->in_max[i] = - it87_read_value(data, IT87_REG_VIN_MAX(i)); + it87_read_value(data, IT87_REG_VIN_MAX(i)); } /* in8 (battery) has no limit registers */ - data->in[8] = - it87_read_value(data, IT87_REG_VIN(8)); + data->in[8] = it87_read_value(data, IT87_REG_VIN(8)); for (i = 0; i < 5; i++) { /* Skip disabled fans */ @@ -1697,7 +1708,7 @@ static struct it87_data *it87_update_device(struct device *dev) continue; data->fan_min[i] = - it87_read_value(data, IT87_REG_FAN_MIN[i]); + it87_read_value(data, IT87_REG_FAN_MIN[i]); data->fan[i] = it87_read_value(data, IT87_REG_FAN[i]); /* Add high byte if in 16-bit mode */ @@ -1710,11 +1721,11 @@ static struct it87_data *it87_update_device(struct device *dev) } for (i = 0; i < 3; i++) { data->temp[i] = - it87_read_value(data, IT87_REG_TEMP(i)); + it87_read_value(data, IT87_REG_TEMP(i)); data->temp_high[i] = - it87_read_value(data, IT87_REG_TEMP_HIGH(i)); + it87_read_value(data, IT87_REG_TEMP_HIGH(i)); data->temp_low[i] = - it87_read_value(data, IT87_REG_TEMP_LOW(i)); + it87_read_value(data, IT87_REG_TEMP_LOW(i)); } /* Newer chips don't have clock dividers */ @@ -1810,7 +1821,7 @@ exit: static int __init sm_it87_init(void) { int err; - unsigned short isa_address=0; + unsigned short isa_address = 0; struct it87_sio_data sio_data; memset(&sio_data, 0, sizeof(struct it87_sio_data)); @@ -1822,7 +1833,7 @@ static int __init sm_it87_init(void) return err; err = it87_device_add(isa_address, &sio_data); - if (err){ + if (err) { platform_driver_unregister(&it87_driver); return err; } @@ -1843,7 +1854,8 @@ MODULE_DESCRIPTION("IT8705F/8712F/8716F/8718F/8720F/8726F, SiS950 driver"); module_param(update_vbat, bool, 0); MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value"); module_param(fix_pwm_polarity, bool, 0); -MODULE_PARM_DESC(fix_pwm_polarity, "Force PWM polarity to active high (DANGEROUS)"); +MODULE_PARM_DESC(fix_pwm_polarity, + "Force PWM polarity to active high (DANGEROUS)"); MODULE_LICENSE("GPL"); module_init(sm_it87_init); -- cgit v1.2.3 From f5f64501e430784251b23625850ce6d690800acf Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:19 +0100 Subject: hwmon: (it87) Use strict_strtol instead of simple_strtol For consistency and robustness, use strict_strtol instead of simple_strtol. Signed-off-by: Jean Delvare --- drivers/hwmon/it87.c | 59 +++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 44 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index 96306a6f844e..8282282eb4ca 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -363,7 +363,10 @@ static ssize_t set_in_min(struct device *dev, struct device_attribute *attr, int nr = sensor_attr->index; struct it87_data *data = dev_get_drvdata(dev); - unsigned long val = simple_strtoul(buf, NULL, 10); + unsigned long val; + + if (strict_strtoul(buf, 10, &val) < 0) + return -EINVAL; mutex_lock(&data->update_lock); data->in_min[nr] = IN_TO_REG(val); @@ -379,7 +382,10 @@ static ssize_t set_in_max(struct device *dev, struct device_attribute *attr, int nr = sensor_attr->index; struct it87_data *data = dev_get_drvdata(dev); - unsigned long val = simple_strtoul(buf, NULL, 10); + unsigned long val; + + if (strict_strtoul(buf, 10, &val) < 0) + return -EINVAL; mutex_lock(&data->update_lock); data->in_max[nr] = IN_TO_REG(val); @@ -452,7 +458,10 @@ static ssize_t set_temp_max(struct device *dev, struct device_attribute *attr, int nr = sensor_attr->index; struct it87_data *data = dev_get_drvdata(dev); - int val = simple_strtol(buf, NULL, 10); + long val; + + if (strict_strtol(buf, 10, &val) < 0) + return -EINVAL; mutex_lock(&data->update_lock); data->temp_high[nr] = TEMP_TO_REG(val); @@ -467,7 +476,10 @@ static ssize_t set_temp_min(struct device *dev, struct device_attribute *attr, int nr = sensor_attr->index; struct it87_data *data = dev_get_drvdata(dev); - int val = simple_strtol(buf, NULL, 10); + long val; + + if (strict_strtol(buf, 10, &val) < 0) + return -EINVAL; mutex_lock(&data->update_lock); data->temp_low[nr] = TEMP_TO_REG(val); @@ -510,7 +522,10 @@ static ssize_t set_sensor(struct device *dev, struct device_attribute *attr, int nr = sensor_attr->index; struct it87_data *data = dev_get_drvdata(dev); - int val = simple_strtol(buf, NULL, 10); + long val; + + if (strict_strtol(buf, 10, &val) < 0) + return -EINVAL; mutex_lock(&data->update_lock); @@ -618,9 +633,12 @@ static ssize_t set_fan_min(struct device *dev, struct device_attribute *attr, int nr = sensor_attr->index; struct it87_data *data = dev_get_drvdata(dev); - int val = simple_strtol(buf, NULL, 10); + long val; u8 reg; + if (strict_strtol(buf, 10, &val) < 0) + return -EINVAL; + mutex_lock(&data->update_lock); reg = it87_read_value(data, IT87_REG_FAN_DIV); switch (nr) { @@ -647,10 +665,13 @@ static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr, int nr = sensor_attr->index; struct it87_data *data = dev_get_drvdata(dev); - unsigned long val = simple_strtoul(buf, NULL, 10); + unsigned long val; int min; u8 old; + if (strict_strtoul(buf, 10, &val) < 0) + return -EINVAL; + mutex_lock(&data->update_lock); old = it87_read_value(data, IT87_REG_FAN_DIV); @@ -689,9 +710,9 @@ static ssize_t set_pwm_enable(struct device *dev, int nr = sensor_attr->index; struct it87_data *data = dev_get_drvdata(dev); - int val = simple_strtol(buf, NULL, 10); + long val; - if (val < 0 || val > 2) + if (strict_strtol(buf, 10, &val) < 0 || val < 0 || val > 2) return -EINVAL; mutex_lock(&data->update_lock); @@ -727,9 +748,9 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, int nr = sensor_attr->index; struct it87_data *data = dev_get_drvdata(dev); - int val = simple_strtol(buf, NULL, 10); + long val; - if (val < 0 || val > 255) + if (strict_strtol(buf, 10, &val) < 0 || val < 0 || val > 255) return -EINVAL; mutex_lock(&data->update_lock); @@ -747,9 +768,12 @@ static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct it87_data *data = dev_get_drvdata(dev); - unsigned long val = simple_strtoul(buf, NULL, 10); + unsigned long val; int i; + if (strict_strtoul(buf, 10, &val) < 0) + return -EINVAL; + /* Search for the nearest available frequency */ for (i = 0; i < 7; i++) { if (val > (pwm_freq[i] + pwm_freq[i+1]) / 2) @@ -871,7 +895,10 @@ static ssize_t set_fan16_min(struct device *dev, struct device_attribute *attr, struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); int nr = sensor_attr->index; struct it87_data *data = dev_get_drvdata(dev); - int val = simple_strtol(buf, NULL, 10); + long val; + + if (strict_strtol(buf, 10, &val) < 0) + return -EINVAL; mutex_lock(&data->update_lock); data->fan_min[nr] = FAN16_TO_REG(val); @@ -992,9 +1019,11 @@ static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct it87_data *data = dev_get_drvdata(dev); - u32 val; + unsigned long val; + + if (strict_strtoul(buf, 10, &val) < 0) + return -EINVAL; - val = simple_strtoul(buf, NULL, 10); data->vrm = val; return count; -- cgit v1.2.3 From 4f3f51bc21d434f8d91a79438a1957ec0baa9e30 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:21 +0100 Subject: hwmon: (it87) Add support for old automatic fan speed control Add support for the automatic fan speed control interface as implemented by IT8705F chips up to revision F and IT8712F chips up to revision G. This implementation fits very well in our standard sysfs interface. I implemented the old and not the new interface because the only chip I have at hand is an old one, and the new interface is more difficult to map to the standard sysfs interface. Adding support later should be possible though, if someone with a supported chip is interested. Signed-off-by: Jean Delvare --- Documentation/hwmon/it87 | 27 ++++++- drivers/hwmon/it87.c | 182 ++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 205 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/Documentation/hwmon/it87 b/Documentation/hwmon/it87 index a96a70fe802a..0083bd317351 100644 --- a/Documentation/hwmon/it87 +++ b/Documentation/hwmon/it87 @@ -146,11 +146,34 @@ Fan speed control ----------------- The fan speed control features are limited to manual PWM mode. Automatic -"Smart Guardian" mode control handling is not implemented. However -if you want to go for "manual mode" just write 1 to pwmN_enable. +"Smart Guardian" mode control handling is only implemented for older chips +(see below.) However if you want to go for "manual mode" just write 1 to +pwmN_enable. If you are only able to control the fan speed with very small PWM values, try lowering the PWM base frequency (pwm1_freq). Depending on the fan, it may give you a somewhat greater control range. The same frequency is used to drive all fan outputs, which is why pwm2_freq and pwm3_freq are read-only. + + +Automatic fan speed control (old interface) +------------------------------------------- + +The driver supports the old interface to automatic fan speed control +which is implemented by IT8705F chips up to revision F and IT8712F +chips up to revision G. + +This interface implements 4 temperature vs. PWM output trip points. +The PWM output of trip point 4 is always the maximum value (fan running +at full speed) while the PWM output of the other 3 trip points can be +freely chosen. The temperature of all 4 trip points can be freely chosen. +Additionally, trip point 1 has an hysteresis temperature attached, to +prevent fast switching between fan on and off. + +The chip automatically computes the PWM output value based on the input +temperature, based on this simple rule: if the temperature value is +between trip point N and trip point N+1 then the PWM output value is +the one of trip point N. The automatic control mode is less flexible +than the manual control mode, but it reacts faster, is more robust and +doesn't use CPU cycles. diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index 8282282eb4ca..bbb0c7443b9b 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -192,6 +192,9 @@ static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87 }; #define IT87_REG_CHIPID 0x58 +#define IT87_REG_AUTO_TEMP(nr, i) (0x60 + (nr) * 8 + (i)) +#define IT87_REG_AUTO_PWM(nr, i) (0x65 + (nr) * 8 + (i)) + #define IN_TO_REG(val) (SENSORS_LIMIT((((val) + 8)/16),0,255)) #define IN_FROM_REG(val) ((val) * 16) @@ -293,6 +296,10 @@ struct it87_data { u8 pwm_ctrl[3]; /* Register value */ u8 pwm_duty[3]; /* Manual PWM value set by user (bit 6-0) */ u8 pwm_temp_map[3]; /* PWM to temp. chan. mapping (bits 1-0) */ + + /* Automatic fan speed control registers */ + u8 auto_pwm[3][4]; /* [nr][3] is hard-coded */ + s8 auto_temp[3][5]; /* [nr][0] is point1_temp_hyst */ }; static inline int has_16bit_fans(const struct it87_data *data) @@ -307,6 +314,15 @@ static inline int has_16bit_fans(const struct it87_data *data) || data->type == it8720; } +static inline int has_old_autopwm(const struct it87_data *data) +{ + /* The old automatic fan speed control interface is implemented + by IT8705F chips up to revision F and IT8712F chips up to + revision G. */ + return (data->type == it87 && data->revision < 0x03) + || (data->type == it8712 && data->revision < 0x08); +} + static int it87_probe(struct platform_device *pdev); static int __devexit it87_remove(struct platform_device *pdev); @@ -813,6 +829,13 @@ static ssize_t set_pwm_temp_map(struct device *dev, long val; u8 reg; + /* This check can go away if we ever support automatic fan speed + control on newer chips. */ + if (!has_old_autopwm(data)) { + dev_notice(dev, "Mapping change disabled for safety reasons\n"); + return -EINVAL; + } + if (strict_strtol(buf, 10, &val) < 0) return -EINVAL; @@ -842,6 +865,72 @@ static ssize_t set_pwm_temp_map(struct device *dev, return count; } +static ssize_t show_auto_pwm(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct it87_data *data = it87_update_device(dev); + struct sensor_device_attribute_2 *sensor_attr = + to_sensor_dev_attr_2(attr); + int nr = sensor_attr->nr; + int point = sensor_attr->index; + + return sprintf(buf, "%d\n", PWM_FROM_REG(data->auto_pwm[nr][point])); +} + +static ssize_t set_auto_pwm(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct it87_data *data = dev_get_drvdata(dev); + struct sensor_device_attribute_2 *sensor_attr = + to_sensor_dev_attr_2(attr); + int nr = sensor_attr->nr; + int point = sensor_attr->index; + long val; + + if (strict_strtol(buf, 10, &val) < 0 || val < 0 || val > 255) + return -EINVAL; + + mutex_lock(&data->update_lock); + data->auto_pwm[nr][point] = PWM_TO_REG(val); + it87_write_value(data, IT87_REG_AUTO_PWM(nr, point), + data->auto_pwm[nr][point]); + mutex_unlock(&data->update_lock); + return count; +} + +static ssize_t show_auto_temp(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct it87_data *data = it87_update_device(dev); + struct sensor_device_attribute_2 *sensor_attr = + to_sensor_dev_attr_2(attr); + int nr = sensor_attr->nr; + int point = sensor_attr->index; + + return sprintf(buf, "%d\n", TEMP_FROM_REG(data->auto_temp[nr][point])); +} + +static ssize_t set_auto_temp(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct it87_data *data = dev_get_drvdata(dev); + struct sensor_device_attribute_2 *sensor_attr = + to_sensor_dev_attr_2(attr); + int nr = sensor_attr->nr; + int point = sensor_attr->index; + long val; + + if (strict_strtol(buf, 10, &val) < 0 || val < -128000 || val > 127000) + return -EINVAL; + + mutex_lock(&data->update_lock); + data->auto_temp[nr][point] = TEMP_TO_REG(val); + it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), + data->auto_temp[nr][point]); + mutex_unlock(&data->update_lock); + return count; +} + #define show_fan_offset(offset) \ static SENSOR_DEVICE_ATTR(fan##offset##_input, S_IRUGO, \ show_fan, NULL, offset - 1); \ @@ -863,8 +952,34 @@ static DEVICE_ATTR(pwm##offset##_freq, \ (offset == 1 ? S_IRUGO | S_IWUSR : S_IRUGO), \ show_pwm_freq, (offset == 1 ? set_pwm_freq : NULL)); \ static SENSOR_DEVICE_ATTR(pwm##offset##_auto_channels_temp, \ - S_IRUGO, show_pwm_temp_map, set_pwm_temp_map, \ - offset - 1); + S_IRUGO | S_IWUSR, show_pwm_temp_map, set_pwm_temp_map, \ + offset - 1); \ +static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point1_pwm, \ + S_IRUGO | S_IWUSR, show_auto_pwm, set_auto_pwm, \ + offset - 1, 0); \ +static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point2_pwm, \ + S_IRUGO | S_IWUSR, show_auto_pwm, set_auto_pwm, \ + offset - 1, 1); \ +static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point3_pwm, \ + S_IRUGO | S_IWUSR, show_auto_pwm, set_auto_pwm, \ + offset - 1, 2); \ +static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point4_pwm, \ + S_IRUGO, show_auto_pwm, NULL, offset - 1, 3); \ +static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point1_temp, \ + S_IRUGO | S_IWUSR, show_auto_temp, set_auto_temp, \ + offset - 1, 1); \ +static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point1_temp_hyst, \ + S_IRUGO | S_IWUSR, show_auto_temp, set_auto_temp, \ + offset - 1, 0); \ +static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point2_temp, \ + S_IRUGO | S_IWUSR, show_auto_temp, set_auto_temp, \ + offset - 1, 2); \ +static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point3_temp, \ + S_IRUGO | S_IWUSR, show_auto_temp, set_auto_temp, \ + offset - 1, 3); \ +static SENSOR_DEVICE_ATTR_2(pwm##offset##_auto_point4_temp, \ + S_IRUGO | S_IWUSR, show_auto_temp, set_auto_temp, \ + offset - 1, 4); show_pwm_offset(1); show_pwm_offset(2); @@ -1219,6 +1334,47 @@ static const struct attribute_group it87_group_pwm[3] = { { .attrs = it87_attributes_pwm[2] }, }; +static struct attribute *it87_attributes_autopwm[3][9+1] = { { + &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, + &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, + &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr, + &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr, + &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr, + &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr, + &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr, + &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr, + &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr, + NULL +}, { + &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, + &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, + &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr, + &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr, + &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr, + &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr, + &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr, + &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr, + &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr, + NULL +}, { + &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, + &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, + &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr, + &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr, + &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr, + &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr, + &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr, + &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr, + &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr, + NULL +} }; + +static const struct attribute_group it87_group_autopwm[3] = { + { .attrs = it87_attributes_autopwm[0] }, + { .attrs = it87_attributes_autopwm[1] }, + { .attrs = it87_attributes_autopwm[2] }, +}; + static struct attribute *it87_attributes_fan_beep[] = { &sensor_dev_attr_fan1_beep.dev_attr.attr, &sensor_dev_attr_fan2_beep.dev_attr.attr, @@ -1382,6 +1538,9 @@ static void it87_remove_files(struct device *dev) if (sio_data->skip_pwm & (1 << 0)) continue; sysfs_remove_group(&dev->kobj, &it87_group_pwm[i]); + if (has_old_autopwm(data)) + sysfs_remove_group(&dev->kobj, + &it87_group_autopwm[i]); } if (!sio_data->skip_vid) sysfs_remove_group(&dev->kobj, &it87_group_vid); @@ -1491,6 +1650,13 @@ static int __devinit it87_probe(struct platform_device *pdev) &it87_group_pwm[i]); if (err) goto ERROR4; + + if (!has_old_autopwm(data)) + continue; + err = sysfs_create_group(&dev->kobj, + &it87_group_autopwm[i]); + if (err) + goto ERROR4; } } @@ -1624,6 +1790,7 @@ static void __devinit it87_init_device(struct platform_device *pdev) for (i = 0; i < 3; i++) { data->pwm_temp_map[i] = i; data->pwm_duty[i] = 0x7f; /* Full speed */ + data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */ } /* Some chips seem to have default value 0xff for all limit @@ -1703,6 +1870,17 @@ static void it87_update_pwm_ctrl(struct it87_data *data, int nr) data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; else /* Manual mode */ data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f; + + if (has_old_autopwm(data)) { + int i; + + for (i = 0; i < 5 ; i++) + data->auto_temp[nr][i] = it87_read_value(data, + IT87_REG_AUTO_TEMP(nr, i)); + for (i = 0; i < 3 ; i++) + data->auto_pwm[nr][i] = it87_read_value(data, + IT87_REG_AUTO_PWM(nr, i)); + } } static struct it87_data *it87_update_device(struct device *dev) -- cgit v1.2.3 From cccfc9c4bb3c7888f8249b36e08d6e115238c613 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:21 +0100 Subject: hwmon: (it87) Validate auto pwm settings Before switching to automatic fan control mode, make sure that all the trip points make sense. Otherwise, the control loop could lead to weird fan behavior. Signed-off-by: Jean Delvare --- Documentation/hwmon/it87 | 4 ++++ drivers/hwmon/it87.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) (limited to 'drivers') diff --git a/Documentation/hwmon/it87 b/Documentation/hwmon/it87 index 0083bd317351..8d08bf0d38ed 100644 --- a/Documentation/hwmon/it87 +++ b/Documentation/hwmon/it87 @@ -177,3 +177,7 @@ between trip point N and trip point N+1 then the PWM output value is the one of trip point N. The automatic control mode is less flexible than the manual control mode, but it reacts faster, is more robust and doesn't use CPU cycles. + +Trip points must be set properly before switching to automatic fan speed +control mode. The driver will perform basic integrity checks before +actually switching to automatic control mode. diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index bbb0c7443b9b..1002befd87d5 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -719,6 +719,32 @@ static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr, mutex_unlock(&data->update_lock); return count; } + +/* Returns 0 if OK, -EINVAL otherwise */ +static int check_trip_points(struct device *dev, int nr) +{ + const struct it87_data *data = dev_get_drvdata(dev); + int i, err = 0; + + if (has_old_autopwm(data)) { + for (i = 0; i < 3; i++) { + if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) + err = -EINVAL; + } + for (i = 0; i < 2; i++) { + if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1]) + err = -EINVAL; + } + } + + if (err) { + dev_err(dev, "Inconsistent trip points, not switching to " + "automatic mode\n"); + dev_err(dev, "Adjust the trip points and try again\n"); + } + return err; +} + static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { @@ -731,6 +757,12 @@ static ssize_t set_pwm_enable(struct device *dev, if (strict_strtol(buf, 10, &val) < 0 || val < 0 || val > 2) return -EINVAL; + /* Check trip points before switching to automatic mode */ + if (val == 2) { + if (check_trip_points(dev, nr) < 0) + return -EINVAL; + } + mutex_lock(&data->update_lock); if (val == 0) { -- cgit v1.2.3 From ebec05bdc4f7d3da852aa86fb54b163d9aeb9848 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:22 +0100 Subject: hwmon: (g760a) Make rpm_from_cnt static Function rpm_from_cnt is only used internally so it can be made static. Make it inline while we're here, for performance reasons (although hopefully gcc would figure out by itself...) Signed-off-by: Jean Delvare Cc: Herbert Valerio Riedel Acked-by: Martin Michlmayr --- drivers/hwmon/g760a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/hwmon/g760a.c b/drivers/hwmon/g760a.c index 19c01a49f6be..09ea12e0a551 100644 --- a/drivers/hwmon/g760a.c +++ b/drivers/hwmon/g760a.c @@ -68,7 +68,7 @@ struct g760a_data { #define PWM_FROM_CNT(cnt) (0xff-(cnt)) #define PWM_TO_CNT(pwm) (0xff-(pwm)) -unsigned int rpm_from_cnt(u8 val, u32 clk, u16 div) +static inline unsigned int rpm_from_cnt(u8 val, u32 clk, u16 div) { return ((val == 0x00) ? 0 : ((clk*30)/(val*div))); } -- cgit v1.2.3 From 5852f9609d21794c45964129b03365883150a6d0 Mon Sep 17 00:00:00 2001 From: Sven Anders Date: Fri, 5 Mar 2010 22:17:22 +0100 Subject: hwmon: (w83793) Add watchdog functionality Add watchdog functionality to the Winbond W83793 driver. Signed-off-by: Sven Anders Acked-by: Hans de Goede Signed-off-by: Jean Delvare --- drivers/hwmon/Kconfig | 3 +- drivers/hwmon/w83793.c | 482 ++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 481 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 9234c2e2c7d9..cdfb0637f247 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -910,7 +910,8 @@ config SENSORS_W83793 select HWMON_VID help If you say yes here you get support for the Winbond W83793 - hardware monitoring chip. + hardware monitoring chip, including support for the integrated + watchdog. This driver can also be built as a module. If so, the module will be called w83793. diff --git a/drivers/hwmon/w83793.c b/drivers/hwmon/w83793.c index 9a2022b67495..9de81a4c15a2 100644 --- a/drivers/hwmon/w83793.c +++ b/drivers/hwmon/w83793.c @@ -3,6 +3,10 @@ Copyright (C) 2006 Winbond Electronics Corp. Yuan Mu Rudolf Marek + Copyright (C) 2009-2010 Sven Anders , ANDURAS AG. + Watchdog driver part + (Based partially on fschmd driver, + Copyright 2007-2008 by Hans de Goede) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -35,6 +39,16 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include + +/* Default values */ +#define WATCHDOG_TIMEOUT 2 /* 2 minute default timeout */ /* Addresses to scan */ static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, 0x2f, @@ -51,6 +65,18 @@ static int reset; module_param(reset, bool, 0); MODULE_PARM_DESC(reset, "Set to 1 to reset chip, not recommended"); +static int timeout = WATCHDOG_TIMEOUT; /* default timeout in minutes */ +module_param(timeout, int, 0); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in minutes. 2<= timeout <=255 (default=" + __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); + +static int nowayout = WATCHDOG_NOWAYOUT; +module_param(nowayout, int, 0); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); + /* Address 0x00, 0x0d, 0x0e, 0x0f in all three banks are reserved as ID, Bank Select registers @@ -72,6 +98,11 @@ MODULE_PARM_DESC(reset, "Set to 1 to reset chip, not recommended"); #define W83793_REG_VID_LATCHB 0x08 #define W83793_REG_VID_CTRL 0x59 +#define W83793_REG_WDT_LOCK 0x01 +#define W83793_REG_WDT_ENABLE 0x02 +#define W83793_REG_WDT_STATUS 0x03 +#define W83793_REG_WDT_TIMEOUT 0x04 + static u16 W83793_REG_TEMP_MODE[2] = { 0x5e, 0x5f }; #define TEMP_READ 0 @@ -223,8 +254,37 @@ struct w83793_data { u8 tolerance[3]; /* Temp tolerance(Smart Fan I/II) */ u8 sf2_pwm[6][7]; /* Smart FanII: Fan duty cycle */ u8 sf2_temp[6][7]; /* Smart FanII: Temp level point */ + + /* watchdog */ + struct i2c_client *client; + struct mutex watchdog_lock; + struct list_head list; /* member of the watchdog_data_list */ + struct kref kref; + struct miscdevice watchdog_miscdev; + unsigned long watchdog_is_open; + char watchdog_expect_close; + char watchdog_name[10]; /* must be unique to avoid sysfs conflict */ + unsigned int watchdog_caused_reboot; + int watchdog_timeout; /* watchdog timeout in minutes */ }; +/* Somewhat ugly :( global data pointer list with all devices, so that + we can find our device data as when using misc_register. There is no + other method to get to one's device data from the open file-op and + for usage in the reboot notifier callback. */ +static LIST_HEAD(watchdog_data_list); + +/* Note this lock not only protect list access, but also data.kref access */ +static DEFINE_MUTEX(watchdog_data_mutex); + +/* Release our data struct when we're detached from the i2c client *and* all + references to our watchdog device are released */ +static void w83793_release_resources(struct kref *ref) +{ + struct w83793_data *data = container_of(ref, struct w83793_data, kref); + kfree(data); +} + static u8 w83793_read_value(struct i2c_client *client, u16 reg); static int w83793_write_value(struct i2c_client *client, u16 reg, u8 value); static int w83793_probe(struct i2c_client *client, @@ -1063,14 +1123,349 @@ static void w83793_init_client(struct i2c_client *client) /* Start monitoring */ w83793_write_value(client, W83793_REG_CONFIG, w83793_read_value(client, W83793_REG_CONFIG) | 0x01); +} + +/* + * Watchdog routines + */ + +static int watchdog_set_timeout(struct w83793_data *data, int timeout) +{ + int ret, mtimeout; + + mtimeout = DIV_ROUND_UP(timeout, 60); + + if (mtimeout > 255) + return -EINVAL; + + mutex_lock(&data->watchdog_lock); + if (!data->client) { + ret = -ENODEV; + goto leave; + } + + data->watchdog_timeout = mtimeout; + + /* Set Timeout value (in Minutes) */ + w83793_write_value(data->client, W83793_REG_WDT_TIMEOUT, + data->watchdog_timeout); + + ret = mtimeout * 60; + +leave: + mutex_unlock(&data->watchdog_lock); + return ret; +} + +static int watchdog_get_timeout(struct w83793_data *data) +{ + int timeout; + + mutex_lock(&data->watchdog_lock); + timeout = data->watchdog_timeout * 60; + mutex_unlock(&data->watchdog_lock); + + return timeout; +} + +static int watchdog_trigger(struct w83793_data *data) +{ + int ret = 0; + + mutex_lock(&data->watchdog_lock); + if (!data->client) { + ret = -ENODEV; + goto leave; + } + + /* Set Timeout value (in Minutes) */ + w83793_write_value(data->client, W83793_REG_WDT_TIMEOUT, + data->watchdog_timeout); + +leave: + mutex_unlock(&data->watchdog_lock); + return ret; +} + +static int watchdog_enable(struct w83793_data *data) +{ + int ret = 0; + + mutex_lock(&data->watchdog_lock); + if (!data->client) { + ret = -ENODEV; + goto leave; + } + + /* Set initial timeout */ + w83793_write_value(data->client, W83793_REG_WDT_TIMEOUT, + data->watchdog_timeout); + + /* Enable Soft Watchdog */ + w83793_write_value(data->client, W83793_REG_WDT_LOCK, 0x55); + +leave: + mutex_unlock(&data->watchdog_lock); + return ret; +} + +static int watchdog_disable(struct w83793_data *data) +{ + int ret = 0; + + mutex_lock(&data->watchdog_lock); + if (!data->client) { + ret = -ENODEV; + goto leave; + } + + /* Disable Soft Watchdog */ + w83793_write_value(data->client, W83793_REG_WDT_LOCK, 0xAA); + +leave: + mutex_unlock(&data->watchdog_lock); + return ret; +} + +static int watchdog_open(struct inode *inode, struct file *filp) +{ + struct w83793_data *pos, *data = NULL; + int watchdog_is_open; + + /* We get called from drivers/char/misc.c with misc_mtx hold, and we + call misc_register() from w83793_probe() with watchdog_data_mutex + hold, as misc_register() takes the misc_mtx lock, this is a possible + deadlock, so we use mutex_trylock here. */ + if (!mutex_trylock(&watchdog_data_mutex)) + return -ERESTARTSYS; + list_for_each_entry(pos, &watchdog_data_list, list) { + if (pos->watchdog_miscdev.minor == iminor(inode)) { + data = pos; + break; + } + } + + /* Check, if device is already open */ + watchdog_is_open = test_and_set_bit(0, &data->watchdog_is_open); + + /* Increase data reference counter (if not already done). + Note we can never not have found data, so we don't check for this */ + if (!watchdog_is_open) + kref_get(&data->kref); + + mutex_unlock(&watchdog_data_mutex); + + /* Check, if device is already open and possibly issue error */ + if (watchdog_is_open) + return -EBUSY; + + /* Enable Soft Watchdog */ + watchdog_enable(data); + + /* Store pointer to data into filp's private data */ + filp->private_data = data; + + return nonseekable_open(inode, filp); +} + +static int watchdog_close(struct inode *inode, struct file *filp) +{ + struct w83793_data *data = filp->private_data; + if (data->watchdog_expect_close) { + watchdog_disable(data); + data->watchdog_expect_close = 0; + } else { + watchdog_trigger(data); + dev_crit(&data->client->dev, + "unexpected close, not stopping watchdog!\n"); + } + + clear_bit(0, &data->watchdog_is_open); + + /* Decrease data reference counter */ + mutex_lock(&watchdog_data_mutex); + kref_put(&data->kref, w83793_release_resources); + mutex_unlock(&watchdog_data_mutex); + + return 0; +} + +static ssize_t watchdog_write(struct file *filp, const char __user *buf, + size_t count, loff_t *offset) +{ + size_t ret; + struct w83793_data *data = filp->private_data; + + if (count) { + if (!nowayout) { + size_t i; + + /* Clear it in case it was set with a previous write */ + data->watchdog_expect_close = 0; + + for (i = 0; i != count; i++) { + char c; + if (get_user(c, buf + i)) + return -EFAULT; + if (c == 'V') + data->watchdog_expect_close = 1; + } + } + ret = watchdog_trigger(data); + if (ret < 0) + return ret; + } + return count; +} + +static int watchdog_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + static struct watchdog_info ident = { + .options = WDIOF_KEEPALIVEPING | + WDIOF_SETTIMEOUT | + WDIOF_CARDRESET, + .identity = "w83793 watchdog" + }; + + int val, ret = 0; + struct w83793_data *data = filp->private_data; + + switch (cmd) { + case WDIOC_GETSUPPORT: + if (!nowayout) + ident.options |= WDIOF_MAGICCLOSE; + if (copy_to_user((void __user *)arg, &ident, sizeof(ident))) + ret = -EFAULT; + break; + + case WDIOC_GETSTATUS: + val = data->watchdog_caused_reboot ? WDIOF_CARDRESET : 0; + ret = put_user(val, (int __user *)arg); + break; + + case WDIOC_GETBOOTSTATUS: + ret = put_user(0, (int __user *)arg); + break; + + case WDIOC_KEEPALIVE: + ret = watchdog_trigger(data); + break; + + case WDIOC_GETTIMEOUT: + val = watchdog_get_timeout(data); + ret = put_user(val, (int __user *)arg); + break; + + case WDIOC_SETTIMEOUT: + if (get_user(val, (int __user *)arg)) { + ret = -EFAULT; + break; + } + ret = watchdog_set_timeout(data, val); + if (ret > 0) + ret = put_user(ret, (int __user *)arg); + break; + + case WDIOC_SETOPTIONS: + if (get_user(val, (int __user *)arg)) { + ret = -EFAULT; + break; + } + + if (val & WDIOS_DISABLECARD) + ret = watchdog_disable(data); + else if (val & WDIOS_ENABLECARD) + ret = watchdog_enable(data); + else + ret = -EINVAL; + + break; + default: + ret = -ENOTTY; + } + + return ret; +} + +static const struct file_operations watchdog_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .open = watchdog_open, + .release = watchdog_close, + .write = watchdog_write, + .ioctl = watchdog_ioctl, +}; + +/* + * Notifier for system down + */ + +static int watchdog_notify_sys(struct notifier_block *this, unsigned long code, + void *unused) +{ + struct w83793_data *data = NULL; + + if (code == SYS_DOWN || code == SYS_HALT) { + + /* Disable each registered watchdog */ + mutex_lock(&watchdog_data_mutex); + list_for_each_entry(data, &watchdog_data_list, list) { + if (data->watchdog_miscdev.minor) + watchdog_disable(data); + } + mutex_unlock(&watchdog_data_mutex); + } + + return NOTIFY_DONE; } +/* + * The WDT needs to learn about soft shutdowns in order to + * turn the timebomb registers off. + */ + +static struct notifier_block watchdog_notifier = { + .notifier_call = watchdog_notify_sys, +}; + +/* + * Init / remove routines + */ + static int w83793_remove(struct i2c_client *client) { struct w83793_data *data = i2c_get_clientdata(client); struct device *dev = &client->dev; - int i; + int i, tmp; + + /* Unregister the watchdog (if registered) */ + if (data->watchdog_miscdev.minor) { + misc_deregister(&data->watchdog_miscdev); + + if (data->watchdog_is_open) { + dev_warn(&client->dev, + "i2c client detached with watchdog open! " + "Stopping watchdog.\n"); + watchdog_disable(data); + } + + mutex_lock(&watchdog_data_mutex); + list_del(&data->list); + mutex_unlock(&watchdog_data_mutex); + + /* Tell the watchdog code the client is gone */ + mutex_lock(&data->watchdog_lock); + data->client = NULL; + mutex_unlock(&data->watchdog_lock); + } + + /* Reset Configuration Register to Disable Watch Dog Registers */ + tmp = w83793_read_value(client, W83793_REG_CONFIG); + w83793_write_value(client, W83793_REG_CONFIG, tmp & ~0x04); + + unregister_reboot_notifier(&watchdog_notifier); hwmon_device_unregister(data->hwmon_dev); @@ -1099,7 +1494,10 @@ static int w83793_remove(struct i2c_client *client) if (data->lm75[1] != NULL) i2c_unregister_device(data->lm75[1]); - kfree(data); + /* Decrease data reference counter */ + mutex_lock(&watchdog_data_mutex); + kref_put(&data->kref, w83793_release_resources); + mutex_unlock(&watchdog_data_mutex); return 0; } @@ -1203,6 +1601,7 @@ static int w83793_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct device *dev = &client->dev; + const int watchdog_minors[] = { WATCHDOG_MINOR, 212, 213, 214, 215 }; struct w83793_data *data; int i, tmp, val, err; int files_fan = ARRAY_SIZE(w83793_left_fan) / 7; @@ -1218,6 +1617,14 @@ static int w83793_probe(struct i2c_client *client, i2c_set_clientdata(client, data); data->bank = i2c_smbus_read_byte_data(client, W83793_REG_BANKSEL); mutex_init(&data->update_lock); + mutex_init(&data->watchdog_lock); + INIT_LIST_HEAD(&data->list); + kref_init(&data->kref); + + /* Store client pointer in our data struct for watchdog usage + (where the client is found through a data ptr instead of the + otherway around) */ + data->client = client; err = w83793_detect_subclients(client); if (err) @@ -1380,8 +1787,77 @@ static int w83793_probe(struct i2c_client *client, goto exit_remove; } + /* Watchdog initialization */ + + /* Register boot notifier */ + err = register_reboot_notifier(&watchdog_notifier); + if (err != 0) { + dev_err(&client->dev, + "cannot register reboot notifier (err=%d)\n", err); + goto exit_devunreg; + } + + /* Enable Watchdog registers. + Set Configuration Register to Enable Watch Dog Registers + (Bit 2) = XXXX, X1XX. */ + tmp = w83793_read_value(client, W83793_REG_CONFIG); + w83793_write_value(client, W83793_REG_CONFIG, tmp | 0x04); + + /* Set the default watchdog timeout */ + data->watchdog_timeout = timeout; + + /* Check, if last reboot was caused by watchdog */ + data->watchdog_caused_reboot = + w83793_read_value(data->client, W83793_REG_WDT_STATUS) & 0x01; + + /* Disable Soft Watchdog during initialiation */ + watchdog_disable(data); + + /* We take the data_mutex lock early so that watchdog_open() cannot + run when misc_register() has completed, but we've not yet added + our data to the watchdog_data_list (and set the default timeout) */ + mutex_lock(&watchdog_data_mutex); + for (i = 0; i < ARRAY_SIZE(watchdog_minors); i++) { + /* Register our watchdog part */ + snprintf(data->watchdog_name, sizeof(data->watchdog_name), + "watchdog%c", (i == 0) ? '\0' : ('0' + i)); + data->watchdog_miscdev.name = data->watchdog_name; + data->watchdog_miscdev.fops = &watchdog_fops; + data->watchdog_miscdev.minor = watchdog_minors[i]; + + err = misc_register(&data->watchdog_miscdev); + if (err == -EBUSY) + continue; + if (err) { + data->watchdog_miscdev.minor = 0; + dev_err(&client->dev, + "Registering watchdog chardev: %d\n", err); + break; + } + + list_add(&data->list, &watchdog_data_list); + + dev_info(&client->dev, + "Registered watchdog chardev major 10, minor: %d\n", + watchdog_minors[i]); + break; + } + if (i == ARRAY_SIZE(watchdog_minors)) { + data->watchdog_miscdev.minor = 0; + dev_warn(&client->dev, "Couldn't register watchdog chardev " + "(due to no free minor)\n"); + } + + mutex_unlock(&watchdog_data_mutex); + return 0; + /* Unregister hwmon device */ + +exit_devunreg: + + hwmon_device_unregister(data->hwmon_dev); + /* Unregister sysfs hooks */ exit_remove: @@ -1628,7 +2104,7 @@ static void __exit sensors_w83793_exit(void) i2c_del_driver(&w83793_driver); } -MODULE_AUTHOR("Yuan Mu"); +MODULE_AUTHOR("Yuan Mu, Sven Anders"); MODULE_DESCRIPTION("w83793 driver"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From d84ca5b345c2b77ebf053d534ada6af2332a43b6 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 5 Mar 2010 22:17:23 +0100 Subject: hwmon: Add driver for ADT7411 voltage and temperature sensor Add basic support for the ADT7411. Reads out all conversion results (via I2C, SPI yet missing) and allows some on-the-fly configuration. Tested with a custom board. Signed-off-by: Sascha Hauer Signed-off-by: Wolfram Sang Signed-off-by: Jean Delvare --- Documentation/hwmon/adt7411 | 42 ++++++ drivers/hwmon/Kconfig | 10 ++ drivers/hwmon/Makefile | 1 + drivers/hwmon/adt7411.c | 359 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 412 insertions(+) create mode 100644 Documentation/hwmon/adt7411 create mode 100644 drivers/hwmon/adt7411.c (limited to 'drivers') diff --git a/Documentation/hwmon/adt7411 b/Documentation/hwmon/adt7411 new file mode 100644 index 000000000000..1632960f9745 --- /dev/null +++ b/Documentation/hwmon/adt7411 @@ -0,0 +1,42 @@ +Kernel driver adt7411 +===================== + +Supported chips: + * Analog Devices ADT7411 + Prefix: 'adt7411' + Addresses scanned: 0x48, 0x4a, 0x4b + Datasheet: Publicly available at the Analog Devices website + +Author: Wolfram Sang (based on adt7470 by Darrick J. Wong) + +Description +----------- + +This driver implements support for the Analog Devices ADT7411 chip. There may +be other chips that implement this interface. + +The ADT7411 can use an I2C/SMBus compatible 2-wire interface or an +SPI-compatible 4-wire interface. It provides a 10-bit analog to digital +converter which measures 1 temperature, vdd and 8 input voltages. It has an +internal temperature sensor, but an external one can also be connected (one +loses 2 inputs then). There are high- and low-limit registers for all inputs. + +Check the datasheet for details. + +sysfs-Interface +--------------- + +in0_input - vdd voltage input +in[1-8]_input - analog 1-8 input +temp1_input - temperature input + +Besides standard interfaces, this driver adds (0 = off, 1 = on): + + adc_ref_vdd - Use vdd as reference instead of 2.25 V + fast_sampling - Sample at 22.5 kHz instead of 1.4 kHz, but drop filters + no_average - Turn off averaging over 16 samples + +Notes +----- + +SPI, external temperature sensor and limit registers are not supported yet. diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index cdfb0637f247..77d032fb813d 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -170,6 +170,16 @@ config SENSORS_ADM9240 This driver can also be built as a module. If so, the module will be called adm9240. +config SENSORS_ADT7411 + tristate "Analog Devices ADT7411" + depends on I2C && EXPERIMENTAL + help + If you say yes here you get support for the Analog Devices + ADT7411 voltage and temperature monitoring chip. + + This driver can also be built as a module. If so, the module + will be called adt7411. + config SENSORS_ADT7462 tristate "Analog Devices ADT7462" depends on I2C && EXPERIMENTAL diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 4bc215c0953f..5fe67bf961b3 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_SENSORS_ADM1029) += adm1029.o obj-$(CONFIG_SENSORS_ADM1031) += adm1031.o obj-$(CONFIG_SENSORS_ADM9240) += adm9240.o obj-$(CONFIG_SENSORS_ADS7828) += ads7828.o +obj-$(CONFIG_SENSORS_ADT7411) += adt7411.o obj-$(CONFIG_SENSORS_ADT7462) += adt7462.o obj-$(CONFIG_SENSORS_ADT7470) += adt7470.o obj-$(CONFIG_SENSORS_ADT7473) += adt7473.o diff --git a/drivers/hwmon/adt7411.c b/drivers/hwmon/adt7411.c new file mode 100644 index 000000000000..9e9246fe2245 --- /dev/null +++ b/drivers/hwmon/adt7411.c @@ -0,0 +1,359 @@ +/* + * Driver for the ADT7411 (I2C/SPI 8 channel 10 bit ADC & temperature-sensor) + * + * Copyright (C) 2008, 2010 Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * TODO: SPI, support for external temperature sensor + * use power-down mode for suspend?, interrupt handling? + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ADT7411_REG_INT_TEMP_VDD_LSB 0x03 +#define ADT7411_REG_EXT_TEMP_AIN14_LSB 0x04 +#define ADT7411_REG_VDD_MSB 0x06 +#define ADT7411_REG_INT_TEMP_MSB 0x07 +#define ADT7411_REG_EXT_TEMP_AIN1_MSB 0x08 + +#define ADT7411_REG_CFG1 0x18 +#define ADT7411_CFG1_START_MONITOR (1 << 0) + +#define ADT7411_REG_CFG2 0x19 +#define ADT7411_CFG2_DISABLE_AVG (1 << 5) + +#define ADT7411_REG_CFG3 0x1a +#define ADT7411_CFG3_ADC_CLK_225 (1 << 0) +#define ADT7411_CFG3_REF_VDD (1 << 4) + +#define ADT7411_REG_DEVICE_ID 0x4d +#define ADT7411_REG_MANUFACTURER_ID 0x4e + +#define ADT7411_DEVICE_ID 0x2 +#define ADT7411_MANUFACTURER_ID 0x41 + +static const unsigned short normal_i2c[] = { 0x48, 0x4a, 0x4b, I2C_CLIENT_END }; + +struct adt7411_data { + struct mutex device_lock; /* for "atomic" device accesses */ + unsigned long next_update; + int vref_cached; + bool ref_is_vdd; + struct device *hwmon_dev; +}; + +/* + * When reading a register containing (up to 4) lsb, all associated + * msb-registers get locked by the hardware. After _one_ of those msb is read, + * _all_ are unlocked. In order to use this locking correctly, reading lsb/msb + * is protected here with a mutex, too. + */ +static int adt7411_read_10_bit(struct i2c_client *client, u8 lsb_reg, + u8 msb_reg, u8 lsb_shift) +{ + struct adt7411_data *data = i2c_get_clientdata(client); + int val, tmp; + + mutex_lock(&data->device_lock); + + val = i2c_smbus_read_byte_data(client, lsb_reg); + if (val < 0) + goto exit_unlock; + + tmp = (val >> lsb_shift) & 3; + val = i2c_smbus_read_byte_data(client, msb_reg); + + if (val >= 0) + val = (val << 2) | tmp; + + exit_unlock: + mutex_unlock(&data->device_lock); + + return val; +} + +static int adt7411_modify_bit(struct i2c_client *client, u8 reg, u8 bit, + bool flag) +{ + struct adt7411_data *data = i2c_get_clientdata(client); + int ret, val; + + mutex_lock(&data->device_lock); + + ret = i2c_smbus_read_byte_data(client, reg); + if (ret < 0) + goto exit_unlock; + + if (flag) + val = ret | bit; + else + val = ret & ~bit; + + ret = i2c_smbus_write_byte_data(client, reg, val); + + exit_unlock: + mutex_unlock(&data->device_lock); + return ret; +} + +static ssize_t adt7411_show_vdd(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + int ret = adt7411_read_10_bit(client, ADT7411_REG_INT_TEMP_VDD_LSB, + ADT7411_REG_VDD_MSB, 2); + + return ret < 0 ? ret : sprintf(buf, "%u\n", ret * 7000 / 1024); +} + +static ssize_t adt7411_show_temp(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + int val = adt7411_read_10_bit(client, ADT7411_REG_INT_TEMP_VDD_LSB, + ADT7411_REG_INT_TEMP_MSB, 0); + + if (val < 0) + return val; + + val = val & 0x200 ? val - 0x400 : val; /* 10 bit signed */ + + return sprintf(buf, "%d\n", val * 250); +} + +static ssize_t adt7411_show_input(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int nr = to_sensor_dev_attr(attr)->index; + struct i2c_client *client = to_i2c_client(dev); + struct adt7411_data *data = i2c_get_clientdata(client); + int val; + u8 lsb_reg, lsb_shift; + + if (time_after_eq(jiffies, data->next_update)) { + val = i2c_smbus_read_byte_data(client, ADT7411_REG_CFG3); + if (val < 0) + return val; + data->ref_is_vdd = val & ADT7411_CFG3_REF_VDD; + + if (data->ref_is_vdd) { + val = adt7411_read_10_bit(client, + ADT7411_REG_INT_TEMP_VDD_LSB, + ADT7411_REG_VDD_MSB, 2); + if (val < 0) + return val; + + data->vref_cached = val * 7000 / 1024; + } else { + data->vref_cached = 2250; + } + + data->next_update = jiffies + HZ; + } + + lsb_reg = ADT7411_REG_EXT_TEMP_AIN14_LSB + (nr >> 2); + lsb_shift = 2 * (nr & 0x03); + val = adt7411_read_10_bit(client, lsb_reg, + ADT7411_REG_EXT_TEMP_AIN1_MSB + nr, lsb_shift); + + return val < 0 ? val : + sprintf(buf, "%u\n", val * data->vref_cached / 1024); +} + +static ssize_t adt7411_show_bit(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sensor_device_attribute_2 *attr2 = to_sensor_dev_attr_2(attr); + struct i2c_client *client = to_i2c_client(dev); + int ret = i2c_smbus_read_byte_data(client, attr2->index); + + return ret < 0 ? ret : sprintf(buf, "%u\n", !!(ret & attr2->nr)); +} + +static ssize_t adt7411_set_bit(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct sensor_device_attribute_2 *s_attr2 = to_sensor_dev_attr_2(attr); + struct i2c_client *client = to_i2c_client(dev); + struct adt7411_data *data = i2c_get_clientdata(client); + int ret; + unsigned long flag; + + ret = strict_strtoul(buf, 0, &flag); + if (ret || flag > 1) + return -EINVAL; + + ret = adt7411_modify_bit(client, s_attr2->index, s_attr2->nr, flag); + + /* force update */ + data->next_update = jiffies; + + return ret < 0 ? ret : count; +} + +#define ADT7411_BIT_ATTR(__name, __reg, __bit) \ + SENSOR_DEVICE_ATTR_2(__name, S_IRUGO | S_IWUSR, adt7411_show_bit, \ + adt7411_set_bit, __bit, __reg) + +static DEVICE_ATTR(temp1_input, S_IRUGO, adt7411_show_temp, NULL); +static DEVICE_ATTR(in0_input, S_IRUGO, adt7411_show_vdd, NULL); +static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, adt7411_show_input, NULL, 0); +static SENSOR_DEVICE_ATTR(in2_input, S_IRUGO, adt7411_show_input, NULL, 1); +static SENSOR_DEVICE_ATTR(in3_input, S_IRUGO, adt7411_show_input, NULL, 2); +static SENSOR_DEVICE_ATTR(in4_input, S_IRUGO, adt7411_show_input, NULL, 3); +static SENSOR_DEVICE_ATTR(in5_input, S_IRUGO, adt7411_show_input, NULL, 4); +static SENSOR_DEVICE_ATTR(in6_input, S_IRUGO, adt7411_show_input, NULL, 5); +static SENSOR_DEVICE_ATTR(in7_input, S_IRUGO, adt7411_show_input, NULL, 6); +static SENSOR_DEVICE_ATTR(in8_input, S_IRUGO, adt7411_show_input, NULL, 7); +static ADT7411_BIT_ATTR(no_average, ADT7411_REG_CFG2, ADT7411_CFG2_DISABLE_AVG); +static ADT7411_BIT_ATTR(fast_sampling, ADT7411_REG_CFG3, ADT7411_CFG3_ADC_CLK_225); +static ADT7411_BIT_ATTR(adc_ref_vdd, ADT7411_REG_CFG3, ADT7411_CFG3_REF_VDD); + +static struct attribute *adt7411_attrs[] = { + &dev_attr_temp1_input.attr, + &dev_attr_in0_input.attr, + &sensor_dev_attr_in1_input.dev_attr.attr, + &sensor_dev_attr_in2_input.dev_attr.attr, + &sensor_dev_attr_in3_input.dev_attr.attr, + &sensor_dev_attr_in4_input.dev_attr.attr, + &sensor_dev_attr_in5_input.dev_attr.attr, + &sensor_dev_attr_in6_input.dev_attr.attr, + &sensor_dev_attr_in7_input.dev_attr.attr, + &sensor_dev_attr_in8_input.dev_attr.attr, + &sensor_dev_attr_no_average.dev_attr.attr, + &sensor_dev_attr_fast_sampling.dev_attr.attr, + &sensor_dev_attr_adc_ref_vdd.dev_attr.attr, + NULL +}; + +static const struct attribute_group adt7411_attr_grp = { + .attrs = adt7411_attrs, +}; + +static int adt7411_detect(struct i2c_client *client, + struct i2c_board_info *info) +{ + int val; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) + return -ENODEV; + + val = i2c_smbus_read_byte_data(client, ADT7411_REG_MANUFACTURER_ID); + if (val < 0 || val != ADT7411_MANUFACTURER_ID) { + dev_dbg(&client->dev, "Wrong manufacturer ID. Got %d, " + "expected %d\n", val, ADT7411_MANUFACTURER_ID); + return -ENODEV; + } + + val = i2c_smbus_read_byte_data(client, ADT7411_REG_DEVICE_ID); + if (val < 0 || val != ADT7411_DEVICE_ID) { + dev_dbg(&client->dev, "Wrong device ID. Got %d, " + "expected %d\n", val, ADT7411_DEVICE_ID); + return -ENODEV; + } + + strlcpy(info->type, "adt7411", I2C_NAME_SIZE); + + return 0; +} + +static int __devinit adt7411_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct adt7411_data *data; + int ret; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + i2c_set_clientdata(client, data); + mutex_init(&data->device_lock); + + ret = adt7411_modify_bit(client, ADT7411_REG_CFG1, + ADT7411_CFG1_START_MONITOR, 1); + if (ret < 0) + goto exit_free; + + /* force update on first occasion */ + data->next_update = jiffies; + + ret = sysfs_create_group(&client->dev.kobj, &adt7411_attr_grp); + if (ret) + goto exit_free; + + data->hwmon_dev = hwmon_device_register(&client->dev); + if (IS_ERR(data->hwmon_dev)) { + ret = PTR_ERR(data->hwmon_dev); + goto exit_remove; + } + + dev_info(&client->dev, "successfully registered\n"); + + return 0; + + exit_remove: + sysfs_remove_group(&client->dev.kobj, &adt7411_attr_grp); + exit_free: + i2c_set_clientdata(client, NULL); + kfree(data); + return ret; +} + +static int __devexit adt7411_remove(struct i2c_client *client) +{ + struct adt7411_data *data = i2c_get_clientdata(client); + + hwmon_device_unregister(data->hwmon_dev); + sysfs_remove_group(&client->dev.kobj, &adt7411_attr_grp); + i2c_set_clientdata(client, NULL); + kfree(data); + return 0; +} + +static const struct i2c_device_id adt7411_id[] = { + { "adt7411", 0 }, + { } +}; + +static struct i2c_driver adt7411_driver = { + .driver = { + .name = "adt7411", + }, + .probe = adt7411_probe, + .remove = __devexit_p(adt7411_remove), + .id_table = adt7411_id, + .detect = adt7411_detect, + .address_list = normal_i2c, + .class = I2C_CLASS_HWMON, +}; + +static int __init sensors_adt7411_init(void) +{ + return i2c_add_driver(&adt7411_driver); +} +module_init(sensors_adt7411_init) + +static void __exit sensors_adt7411_exit(void) +{ + i2c_del_driver(&adt7411_driver); +} +module_exit(sensors_adt7411_exit) + +MODULE_AUTHOR("Sascha Hauer and " + "Wolfram Sang "); +MODULE_DESCRIPTION("ADT7411 driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 232449850229deeda84194e8a3c93a49ab6a043e Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 5 Mar 2010 22:17:23 +0100 Subject: hwmon: (adt7411) Improve locking Add proper locking for the cached variables. Also get rid of ref_is_vdd, which became obsolete. Signed-off-by: Wolfram Sang Signed-off-by: Jean Delvare --- drivers/hwmon/adt7411.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/adt7411.c b/drivers/hwmon/adt7411.c index 9e9246fe2245..3471884e42d2 100644 --- a/drivers/hwmon/adt7411.c +++ b/drivers/hwmon/adt7411.c @@ -48,9 +48,9 @@ static const unsigned short normal_i2c[] = { 0x48, 0x4a, 0x4b, I2C_CLIENT_END }; struct adt7411_data { struct mutex device_lock; /* for "atomic" device accesses */ + struct mutex update_lock; unsigned long next_update; int vref_cached; - bool ref_is_vdd; struct device *hwmon_dev; }; @@ -142,18 +142,18 @@ static ssize_t adt7411_show_input(struct device *dev, int val; u8 lsb_reg, lsb_shift; + mutex_lock(&data->update_lock); if (time_after_eq(jiffies, data->next_update)) { val = i2c_smbus_read_byte_data(client, ADT7411_REG_CFG3); if (val < 0) - return val; - data->ref_is_vdd = val & ADT7411_CFG3_REF_VDD; + goto exit_unlock; - if (data->ref_is_vdd) { + if (val & ADT7411_CFG3_REF_VDD) { val = adt7411_read_10_bit(client, ADT7411_REG_INT_TEMP_VDD_LSB, ADT7411_REG_VDD_MSB, 2); if (val < 0) - return val; + goto exit_unlock; data->vref_cached = val * 7000 / 1024; } else { @@ -167,9 +167,13 @@ static ssize_t adt7411_show_input(struct device *dev, lsb_shift = 2 * (nr & 0x03); val = adt7411_read_10_bit(client, lsb_reg, ADT7411_REG_EXT_TEMP_AIN1_MSB + nr, lsb_shift); + if (val < 0) + goto exit_unlock; - return val < 0 ? val : - sprintf(buf, "%u\n", val * data->vref_cached / 1024); + val = sprintf(buf, "%u\n", val * data->vref_cached / 1024); + exit_unlock: + mutex_unlock(&data->update_lock); + return val; } static ssize_t adt7411_show_bit(struct device *dev, @@ -199,7 +203,9 @@ static ssize_t adt7411_set_bit(struct device *dev, ret = adt7411_modify_bit(client, s_attr2->index, s_attr2->nr, flag); /* force update */ + mutex_lock(&data->update_lock); data->next_update = jiffies; + mutex_unlock(&data->update_lock); return ret < 0 ? ret : count; } @@ -282,6 +288,7 @@ static int __devinit adt7411_probe(struct i2c_client *client, i2c_set_clientdata(client, data); mutex_init(&data->device_lock); + mutex_init(&data->update_lock); ret = adt7411_modify_bit(client, ADT7411_REG_CFG1, ADT7411_CFG1_START_MONITOR, 1); -- cgit v1.2.3 From d58de038728221f780e11d50b32aa40d420c1150 Mon Sep 17 00:00:00 2001 From: George Joseph Date: Fri, 5 Mar 2010 22:17:25 +0100 Subject: hwmon: Driver for Andigilog aSC7621 family monitoring chips Hwmon driver for Andigilog aSC7621 family monitoring chips. Signed-off-by: George Joseph Acked-by: Hans de Goede Signed-off-by: Jean Delvare --- Documentation/hwmon/asc7621 | 296 ++++++++++ MAINTAINERS | 7 + drivers/hwmon/Kconfig | 13 + drivers/hwmon/Makefile | 1 + drivers/hwmon/asc7621.c | 1255 +++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 1572 insertions(+) create mode 100644 Documentation/hwmon/asc7621 create mode 100644 drivers/hwmon/asc7621.c (limited to 'drivers') diff --git a/Documentation/hwmon/asc7621 b/Documentation/hwmon/asc7621 new file mode 100644 index 000000000000..7287be7e1f21 --- /dev/null +++ b/Documentation/hwmon/asc7621 @@ -0,0 +1,296 @@ +Kernel driver asc7621 +================== + +Supported chips: + Andigilog aSC7621 and aSC7621a + Prefix: 'asc7621' + Addresses scanned: I2C 0x2c, 0x2d, 0x2e + Datasheet: http://www.fairview5.com/linux/asc7621/asc7621.pdf + +Author: + George Joseph + +Description provided by Dave Pivin @ Andigilog: + +Andigilog has both the PECI and pre-PECI versions of the Heceta-6, as +Intel calls them. Heceta-6e has high frequency PWM and Heceta-6p has +added PECI and a 4th thermal zone. The Andigilog aSC7611 is the +Heceta-6e part and aSC7621 is the Heceta-6p part. They are both in +volume production, shipping to Intel and their subs. + +We have enhanced both parts relative to the governing Intel +specification. First enhancement is temperature reading resolution. We +have used registers below 20h for vendor-specific functions in addition +to those in the Intel-specified vendor range. + +Our conversion process produces a result that is reported as two bytes. +The fan speed control uses this finer value to produce a "step-less" fan +PWM output. These two bytes are "read-locked" to guarantee that once a +high or low byte is read, the other byte is locked-in until after the +next read of any register. So to get an atomic reading, read high or low +byte, then the very next read should be the opposite byte. Our data +sheet says 10-bits of resolution, although you may find the lower bits +are active, they are not necessarily reliable or useful externally. We +chose not to mask them. + +We employ significant filtering that is user tunable as described in the +data sheet. Our temperature reports and fan PWM outputs are very smooth +when compared to the competition, in addition to the higher resolution +temperature reports. The smoother PWM output does not require user +intervention. + +We offer GPIO features on the former VID pins. These are open-drain +outputs or inputs and may be used as general purpose I/O or as alarm +outputs that are based on temperature limits. These are in 19h and 1Ah. + +We offer flexible mapping of temperature readings to thermal zones. Any +temperature may be mapped to any zone, which has a default assignment +that follows Intel's specs. + +Since there is a fan to zone assignment that allows for the "hotter" of +a set of zones to control the PWM of an individual fan, but there is no +indication to the user, we have added an indicator that shows which zone +is currently controlling the PWM for a given fan. This is in register +00h. + +Both remote diode temperature readings may be given an offset value such +that the reported reading as well as the temperature used to determine +PWM may be offset for system calibration purposes. + +PECI Extended configuration allows for having more than two domains per +PECI address and also provides an enabling function for each PECI +address. One could use our flexible zone assignment to have a zone +assigned to up to 4 PECI addresses. This is not possible in the default +Intel configuration. This would be useful in multi-CPU systems with +individual fans on each that would benefit from individual fan control. +This is in register 0Eh. + +The tachometer measurement system is flexible and able to adapt to many +fan types. We can also support pulse-stretched PWM so that 3-wire fans +may be used. These characteristics are in registers 04h to 07h. + +Finally, we have added a tach disable function that turns off the tach +measurement system for individual tachs in order to save power. That is +in register 75h. + +-- +aSC7621 Product Description + +The aSC7621 has a two wire digital interface compatible with SMBus 2.0. +Using a 10-bit ADC, the aSC7621 measures the temperature of two remote diode +connected transistors as well as its own die. Support for Platform +Environmental Control Interface (PECI) is included. + +Using temperature information from these four zones, an automatic fan speed +control algorithm is employed to minimize acoustic impact while achieving +recommended CPU temperature under varying operational loads. + +To set fan speed, the aSC7621 has three independent pulse width modulation +(PWM) outputs that are controlled by one, or a combination of three, +temperature zones. Both high- and low-frequency PWM ranges are supported. + +The aSC7621 also includes a digital filter that can be invoked to smooth +temperature readings for better control of fan speed and minimum acoustic +impact. + +The aSC7621 has tachometer inputs to measure fan speed on up to four fans. +Limit and status registers for all measured values are included to alert +the system host that any measurements are outside of programmed limits +via status registers. + +System voltages of VCCP, 2.5V, 3.3V, 5.0V, and 12V motherboard power are +monitored efficiently with internal scaling resistors. + +Features +- Supports PECI interface and monitors internal and remote thermal diodes +- 2-wire, SMBus 2.0 compliant, serial interface +- 10-bit ADC +- Monitors VCCP, 2.5V, 3.3V, 5.0V, and 12V motherboard/processor supplies +- Programmable autonomous fan control based on temperature readings +- Noise filtering of temperature reading for fan speed control +- 0.25C digital temperature sensor resolution +- 3 PWM fan speed control outputs for 2-, 3- or 4-wire fans and up to 4 fan + tachometer inputs +- Enhanced measured temperature to Temperature Zone assignment. +- Provides high and low PWM frequency ranges +- 3 GPIO pins for custom use +- 24-Lead QSOP package + +Configuration Notes +=================== + +Except where noted below, the sysfs entries created by this driver follow +the standards defined in "sysfs-interface". + +temp1_source + 0 (default) peci_legacy = 0, Remote 1 Temperature + peci_legacy = 1, PECI Processor Temperature 0 + 1 Remote 1 Temperature + 2 Remote 2 Temperature + 3 Internal Temperature + 4 PECI Processor Temperature 0 + 5 PECI Processor Temperature 1 + 6 PECI Processor Temperature 2 + 7 PECI Processor Temperature 3 + +temp2_source + 0 (default) Internal Temperature + 1 Remote 1 Temperature + 2 Remote 2 Temperature + 3 Internal Temperature + 4 PECI Processor Temperature 0 + 5 PECI Processor Temperature 1 + 6 PECI Processor Temperature 2 + 7 PECI Processor Temperature 3 + +temp3_source + 0 (default) Remote 2 Temperature + 1 Remote 1 Temperature + 2 Remote 2 Temperature + 3 Internal Temperature + 4 PECI Processor Temperature 0 + 5 PECI Processor Temperature 1 + 6 PECI Processor Temperature 2 + 7 PECI Processor Temperature 3 + +temp4_source + 0 (default) peci_legacy = 0, PECI Processor Temperature 0 + peci_legacy = 1, Remote 1 Temperature + 1 Remote 1 Temperature + 2 Remote 2 Temperature + 3 Internal Temperature + 4 PECI Processor Temperature 0 + 5 PECI Processor Temperature 1 + 6 PECI Processor Temperature 2 + 7 PECI Processor Temperature 3 + +temp[1-4]_smoothing_enable +temp[1-4]_smoothing_time + Smooths spikes in temp readings caused by noise. + Valid values in milliseconds are: + 35000 + 17600 + 11800 + 7000 + 4400 + 3000 + 1600 + 800 + +temp[1-4]_crit + When the corresponding zone temperature reaches this value, + ALL pwm outputs will got to 100%. + +temp[5-8]_input +temp[5-8]_enable + The aSC7621 can also read temperatures provided by the processor + via the PECI bus. Usually these are "core" temps and are relative + to the point where the automatic thermal control circuit starts + throttling. This means that these are usually negative numbers. + +pwm[1-3]_enable + 0 Fan off. + 1 Fan on manual control. + 2 Fan on automatic control and will run at the minimum pwm + if the temperature for the zone is below the minimum. + 3 Fan on automatic control but will be off if the temperature + for the zone is below the minimum. + 4-254 Ignored. + 255 Fan on full. + +pwm[1-3]_auto_channels + Bitmap as described in sysctl-interface with the following + exceptions... + Only the following combination of zones (and their corresponding masks) + are valid: + 1 + 2 + 3 + 2,3 + 1,2,3 + 4 + 1,2,3,4 + + Special values: + 0 Disabled. + 16 Fan on manual control. + 31 Fan on full. + + +pwm[1-3]_invert + When set, inverts the meaning of pwm[1-3]. + i.e. when pwm = 0, the fan will be on full and + when pwm = 255 the fan will be off. + +pwm[1-3]_freq + PWM frequency in Hz + Valid values in Hz are: + + 10 + 15 + 23 + 30 (default) + 38 + 47 + 62 + 94 + 23000 + 24000 + 25000 + 26000 + 27000 + 28000 + 29000 + 30000 + + Setting any other value will be ignored. + +peci_enable + Enables or disables PECI + +peci_avg + Input filter average time. + + 0 0 Sec. (no Smoothing) (default) + 1 0.25 Sec. + 2 0.5 Sec. + 3 1.0 Sec. + 4 2.0 Sec. + 5 4.0 Sec. + 6 8.0 Sec. + 7 0.0 Sec. + +peci_legacy + + 0 Standard Mode (default) + Remote Diode 1 reading is associated with + Temperature Zone 1, PECI is associated with + Zone 4 + + 1 Legacy Mode + PECI is associated with Temperature Zone 1, + Remote Diode 1 is associated with Zone 4 + +peci_diode + Diode filter + + 0 0.25 Sec. + 1 1.1 Sec. + 2 2.4 Sec. (default) + 3 3.4 Sec. + 4 5.0 Sec. + 5 6.8 Sec. + 6 10.2 Sec. + 7 16.4 Sec. + +peci_4domain + Four domain enable + + 0 1 or 2 Domains for enabled processors (default) + 1 3 or 4 Domains for enabled processors + +peci_domain + Domain + + 0 Processor contains a single domain (0) (default) + 1 Processor contains two domains (0,1) diff --git a/MAINTAINERS b/MAINTAINERS index bb6ec71f025b..d6cbddb57326 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -966,6 +966,13 @@ W: http://www.arm.linux.org.uk/ S: Maintained F: arch/arm/vfp/ +ASC7621 HARDWARE MONITOR DRIVER +M: George Joseph +L: lm-sensors@lm-sensors.org +S: Maintained +F: Documentation/hwmon/asc7621 +F: drivers/hwmon/asc7621.c + ASUS ACPI EXTRAS DRIVER M: Corentin Chary M: Karol Kozimor diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 77d032fb813d..b6d65aa20825 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -226,6 +226,19 @@ config SENSORS_ADT7475 This driver can also be build as a module. If so, the module will be called adt7475. +config SENSORS_ASC7621 + tristate "Andigilog aSC7621" + depends on HWMON && I2C + help + If you say yes here you get support for the aSC7621 + family of SMBus sensors chip found on most Intel X48, X38, 975, + 965 and 945 desktop boards. Currently supported chips: + aSC7621 + aSC7621a + + This driver can also be built as a module. If so, the module + will be called asc7621. + config SENSORS_K8TEMP tristate "AMD Athlon64/FX or Opteron temperature sensor" depends on X86 && PCI && EXPERIMENTAL diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 5fe67bf961b3..865da80f2b90 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_SENSORS_ADT7473) += adt7473.o obj-$(CONFIG_SENSORS_ADT7475) += adt7475.o obj-$(CONFIG_SENSORS_APPLESMC) += applesmc.o obj-$(CONFIG_SENSORS_AMS) += ams/ +obj-$(CONFIG_SENSORS_ASC7621) += asc7621.o obj-$(CONFIG_SENSORS_ATXP1) += atxp1.o obj-$(CONFIG_SENSORS_CORETEMP) += coretemp.o obj-$(CONFIG_SENSORS_DME1737) += dme1737.o diff --git a/drivers/hwmon/asc7621.c b/drivers/hwmon/asc7621.c new file mode 100644 index 000000000000..7f948105d8ad --- /dev/null +++ b/drivers/hwmon/asc7621.c @@ -0,0 +1,1255 @@ +/* + * asc7621.c - Part of lm_sensors, Linux kernel modules for hardware monitoring + * Copyright (c) 2007, 2010 George Joseph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Addresses to scan */ +static unsigned short normal_i2c[] = { + 0x2c, 0x2d, 0x2e, I2C_CLIENT_END +}; + +enum asc7621_type { + asc7621, + asc7621a +}; + +#define INTERVAL_HIGH (HZ + HZ / 2) +#define INTERVAL_LOW (1 * 60 * HZ) +#define PRI_NONE 0 +#define PRI_LOW 1 +#define PRI_HIGH 2 +#define FIRST_CHIP asc7621 +#define LAST_CHIP asc7621a + +struct asc7621_chip { + char *name; + enum asc7621_type chip_type; + u8 company_reg; + u8 company_id; + u8 verstep_reg; + u8 verstep_id; + unsigned short *addresses; +}; + +static struct asc7621_chip asc7621_chips[] = { + { + .name = "asc7621", + .chip_type = asc7621, + .company_reg = 0x3e, + .company_id = 0x61, + .verstep_reg = 0x3f, + .verstep_id = 0x6c, + .addresses = normal_i2c, + }, + { + .name = "asc7621a", + .chip_type = asc7621a, + .company_reg = 0x3e, + .company_id = 0x61, + .verstep_reg = 0x3f, + .verstep_id = 0x6d, + .addresses = normal_i2c, + }, +}; + +/* + * Defines the highest register to be used, not the count. + * The actual count will probably be smaller because of gaps + * in the implementation (unused register locations). + * This define will safely set the array size of both the parameter + * and data arrays. + * This comes from the data sheet register description table. + */ +#define LAST_REGISTER 0xff + +struct asc7621_data { + struct i2c_client client; + struct device *class_dev; + struct mutex update_lock; + int valid; /* !=0 if following fields are valid */ + unsigned long last_high_reading; /* In jiffies */ + unsigned long last_low_reading; /* In jiffies */ + /* + * Registers we care about occupy the corresponding index + * in the array. Registers we don't care about are left + * at 0. + */ + u8 reg[LAST_REGISTER + 1]; +}; + +/* + * Macro to get the parent asc7621_param structure + * from a sensor_device_attribute passed into the + * show/store functions. + */ +#define to_asc7621_param(_sda) \ + container_of(_sda, struct asc7621_param, sda) + +/* + * Each parameter to be retrieved needs an asc7621_param structure + * allocated. It contains the sensor_device_attribute structure + * and the control info needed to retrieve the value from the register map. + */ +struct asc7621_param { + struct sensor_device_attribute sda; + u8 priority; + u8 msb[3]; + u8 lsb[3]; + u8 mask[3]; + u8 shift[3]; +}; + +/* + * This is the map that ultimately indicates whether we'll be + * retrieving a register value or not, and at what frequency. + */ +static u8 asc7621_register_priorities[255]; + +static struct asc7621_data *asc7621_update_device(struct device *dev); + +static inline u8 read_byte(struct i2c_client *client, u8 reg) +{ + int res = i2c_smbus_read_byte_data(client, reg); + if (res < 0) { + dev_err(&client->dev, + "Unable to read from register 0x%02x.\n", reg); + return 0; + }; + return res & 0xff; +} + +static inline int write_byte(struct i2c_client *client, u8 reg, u8 data) +{ + int res = i2c_smbus_write_byte_data(client, reg, data); + if (res < 0) { + dev_err(&client->dev, + "Unable to write value 0x%02x to register 0x%02x.\n", + data, reg); + }; + return res; +} + +/* + * Data Handlers + * Each function handles the formatting, storage + * and retrieval of like parameters. + */ + +#define SETUP_SHOW_data_param(d, a) \ + struct sensor_device_attribute *sda = to_sensor_dev_attr(a); \ + struct asc7621_data *data = asc7621_update_device(d); \ + struct asc7621_param *param = to_asc7621_param(sda) + +#define SETUP_STORE_data_param(d, a) \ + struct sensor_device_attribute *sda = to_sensor_dev_attr(a); \ + struct i2c_client *client = to_i2c_client(d); \ + struct asc7621_data *data = i2c_get_clientdata(client); \ + struct asc7621_param *param = to_asc7621_param(sda) + +/* + * u8 is just what it sounds like...an unsigned byte with no + * special formatting. + */ +static ssize_t show_u8(struct device *dev, struct device_attribute *attr, + char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + + return sprintf(buf, "%u\n", data->reg[param->msb[0]]); +} + +static ssize_t store_u8(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + SETUP_STORE_data_param(dev, attr); + long reqval; + + if (strict_strtol(buf, 10, &reqval)) + return -EINVAL; + + reqval = SENSORS_LIMIT(reqval, 0, 255); + + mutex_lock(&data->update_lock); + data->reg[param->msb[0]] = reqval; + write_byte(client, param->msb[0], reqval); + mutex_unlock(&data->update_lock); + return count; +} + +/* + * Many of the config values occupy only a few bits of a register. + */ +static ssize_t show_bitmask(struct device *dev, + struct device_attribute *attr, char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + + return sprintf(buf, "%u\n", + (data->reg[param->msb[0]] >> param-> + shift[0]) & param->mask[0]); +} + +static ssize_t store_bitmask(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + SETUP_STORE_data_param(dev, attr); + long reqval; + u8 currval; + + if (strict_strtol(buf, 10, &reqval)) + return -EINVAL; + + reqval = SENSORS_LIMIT(reqval, 0, param->mask[0]); + + reqval = (reqval & param->mask[0]) << param->shift[0]; + + mutex_lock(&data->update_lock); + currval = read_byte(client, param->msb[0]); + reqval |= (currval & ~(param->mask[0] << param->shift[0])); + data->reg[param->msb[0]] = reqval; + write_byte(client, param->msb[0], reqval); + mutex_unlock(&data->update_lock); + return count; +} + +/* + * 16 bit fan rpm values + * reported by the device as the number of 11.111us periods (90khz) + * between full fan rotations. Therefore... + * RPM = (90000 * 60) / register value + */ +static ssize_t show_fan16(struct device *dev, + struct device_attribute *attr, char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + u16 regval; + + mutex_lock(&data->update_lock); + regval = (data->reg[param->msb[0]] << 8) | data->reg[param->lsb[0]]; + mutex_unlock(&data->update_lock); + + return sprintf(buf, "%u\n", + (regval == 0 ? -1 : (regval) == + 0xffff ? 0 : 5400000 / regval)); +} + +static ssize_t store_fan16(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + SETUP_STORE_data_param(dev, attr); + long reqval; + + if (strict_strtol(buf, 10, &reqval)) + return -EINVAL; + + reqval = + (SENSORS_LIMIT((reqval) <= 0 ? 0 : 5400000 / (reqval), 0, 65534)); + + mutex_lock(&data->update_lock); + data->reg[param->msb[0]] = (reqval >> 8) & 0xff; + data->reg[param->lsb[0]] = reqval & 0xff; + write_byte(client, param->msb[0], data->reg[param->msb[0]]); + write_byte(client, param->lsb[0], data->reg[param->lsb[0]]); + mutex_unlock(&data->update_lock); + + return count; +} + +/* + * Voltages are scaled in the device so that the nominal voltage + * is 3/4ths of the 0-255 range (i.e. 192). + * If all voltages are 'normal' then all voltage registers will + * read 0xC0. This doesn't help us if we don't have a point of refernce. + * The data sheet however provides us with the full scale value for each + * which is stored in in_scaling. The sda->index parameter value provides + * the index into in_scaling. + * + * NOTE: The chip expects the first 2 inputs be 2.5 and 2.25 volts + * respectively. That doesn't mean that's what the motherboard provides. :) + */ + +static int asc7621_in_scaling[] = { + 3320, 3000, 4380, 6640, 16000 +}; + +static ssize_t show_in10(struct device *dev, struct device_attribute *attr, + char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + u16 regval; + u8 nr = sda->index; + + mutex_lock(&data->update_lock); + regval = (data->reg[param->msb[0]] * asc7621_in_scaling[nr]) / 256; + + /* The LSB value is a 2-bit scaling of the MSB's LSbit value. + * I.E. If the maximim voltage for this input is 6640 millivolts then + * a MSB register value of 0 = 0mv and 255 = 6640mv. + * A 1 step change therefore represents 25.9mv (6640 / 256). + * The extra 2-bits therefore represent increments of 6.48mv. + */ + regval += ((asc7621_in_scaling[nr] / 256) / 4) * + (data->reg[param->lsb[0]] >> 6); + + mutex_unlock(&data->update_lock); + + return sprintf(buf, "%u\n", regval); +} + +/* 8 bit voltage values (the mins and maxs) */ +static ssize_t show_in8(struct device *dev, struct device_attribute *attr, + char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + u8 nr = sda->index; + + return sprintf(buf, "%u\n", + ((data->reg[param->msb[0]] * + asc7621_in_scaling[nr]) / 256)); +} + +static ssize_t store_in8(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + SETUP_STORE_data_param(dev, attr); + long reqval; + u8 nr = sda->index; + + if (strict_strtol(buf, 10, &reqval)) + return -EINVAL; + + reqval = SENSORS_LIMIT(reqval, 0, asc7621_in_scaling[nr]); + + reqval = (reqval * 255 + 128) / asc7621_in_scaling[nr]; + + mutex_lock(&data->update_lock); + data->reg[param->msb[0]] = reqval; + write_byte(client, param->msb[0], reqval); + mutex_unlock(&data->update_lock); + + return count; +} + +static ssize_t show_temp8(struct device *dev, + struct device_attribute *attr, char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + + return sprintf(buf, "%d\n", ((s8) data->reg[param->msb[0]]) * 1000); +} + +static ssize_t store_temp8(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + SETUP_STORE_data_param(dev, attr); + long reqval; + s8 temp; + + if (strict_strtol(buf, 10, &reqval)) + return -EINVAL; + + reqval = SENSORS_LIMIT(reqval, -127000, 127000); + + temp = reqval / 1000; + + mutex_lock(&data->update_lock); + data->reg[param->msb[0]] = temp; + write_byte(client, param->msb[0], temp); + mutex_unlock(&data->update_lock); + return count; +} + +/* + * Temperatures that occupy 2 bytes always have the whole + * number of degrees in the MSB with some part of the LSB + * indicating fractional degrees. + */ + +/* mmmmmmmm.llxxxxxx */ +static ssize_t show_temp10(struct device *dev, + struct device_attribute *attr, char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + u8 msb, lsb; + int temp; + + mutex_lock(&data->update_lock); + msb = data->reg[param->msb[0]]; + lsb = (data->reg[param->lsb[0]] >> 6) & 0x03; + temp = (((s8) msb) * 1000) + (lsb * 250); + mutex_unlock(&data->update_lock); + + return sprintf(buf, "%d\n", temp); +} + +/* mmmmmm.ll */ +static ssize_t show_temp62(struct device *dev, + struct device_attribute *attr, char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + u8 regval = data->reg[param->msb[0]]; + int temp = ((s8) (regval & 0xfc) * 1000) + ((regval & 0x03) * 250); + + return sprintf(buf, "%d\n", temp); +} + +static ssize_t store_temp62(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + SETUP_STORE_data_param(dev, attr); + long reqval, i, f; + s8 temp; + + if (strict_strtol(buf, 10, &reqval)) + return -EINVAL; + + reqval = SENSORS_LIMIT(reqval, -32000, 31750); + i = reqval / 1000; + f = reqval - (i * 1000); + temp = i << 2; + temp |= f / 250; + + mutex_lock(&data->update_lock); + data->reg[param->msb[0]] = temp; + write_byte(client, param->msb[0], temp); + mutex_unlock(&data->update_lock); + return count; +} + +/* + * The aSC7621 doesn't provide an "auto_point2". Instead, you + * specify the auto_point1 and a range. To keep with the sysfs + * hwmon specs, we synthesize the auto_point_2 from them. + */ + +static u32 asc7621_range_map[] = { + 2000, 2500, 3330, 4000, 5000, 6670, 8000, 10000, + 13330, 16000, 20000, 26670, 32000, 40000, 53330, 80000, +}; + +static ssize_t show_ap2_temp(struct device *dev, + struct device_attribute *attr, char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + long auto_point1; + u8 regval; + int temp; + + mutex_lock(&data->update_lock); + auto_point1 = ((s8) data->reg[param->msb[1]]) * 1000; + regval = + ((data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]); + temp = auto_point1 + asc7621_range_map[SENSORS_LIMIT(regval, 0, 15)]; + mutex_unlock(&data->update_lock); + + return sprintf(buf, "%d\n", temp); + +} + +static ssize_t store_ap2_temp(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + SETUP_STORE_data_param(dev, attr); + long reqval, auto_point1; + int i; + u8 currval, newval = 0; + + if (strict_strtol(buf, 10, &reqval)) + return -EINVAL; + + mutex_lock(&data->update_lock); + auto_point1 = data->reg[param->msb[1]] * 1000; + reqval = SENSORS_LIMIT(reqval, auto_point1 + 2000, auto_point1 + 80000); + + for (i = ARRAY_SIZE(asc7621_range_map) - 1; i >= 0; i--) { + if (reqval >= auto_point1 + asc7621_range_map[i]) { + newval = i; + break; + } + } + + newval = (newval & param->mask[0]) << param->shift[0]; + currval = read_byte(client, param->msb[0]); + newval |= (currval & ~(param->mask[0] << param->shift[0])); + data->reg[param->msb[0]] = newval; + write_byte(client, param->msb[0], newval); + mutex_unlock(&data->update_lock); + return count; +} + +static ssize_t show_pwm_ac(struct device *dev, + struct device_attribute *attr, char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + u8 config, altbit, regval; + u8 map[] = { + 0x01, 0x02, 0x04, 0x1f, 0x00, 0x06, 0x07, 0x10, + 0x08, 0x0f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f + }; + + mutex_lock(&data->update_lock); + config = (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; + altbit = (data->reg[param->msb[1]] >> param->shift[1]) & param->mask[1]; + regval = config | (altbit << 3); + mutex_unlock(&data->update_lock); + + return sprintf(buf, "%u\n", map[SENSORS_LIMIT(regval, 0, 15)]); +} + +static ssize_t store_pwm_ac(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + SETUP_STORE_data_param(dev, attr); + unsigned long reqval; + u8 currval, config, altbit, newval; + u16 map[] = { + 0x04, 0x00, 0x01, 0xff, 0x02, 0xff, 0x05, 0x06, + 0x08, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, + 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x03, + }; + + if (strict_strtoul(buf, 10, &reqval)) + return -EINVAL; + + if (reqval > 31) + return -EINVAL; + + reqval = map[reqval]; + if (reqval == 0xff) + return -EINVAL; + + config = reqval & 0x07; + altbit = (reqval >> 3) & 0x01; + + config = (config & param->mask[0]) << param->shift[0]; + altbit = (altbit & param->mask[1]) << param->shift[1]; + + mutex_lock(&data->update_lock); + currval = read_byte(client, param->msb[0]); + newval = config | (currval & ~(param->mask[0] << param->shift[0])); + newval = altbit | (newval & ~(param->mask[1] << param->shift[1])); + data->reg[param->msb[0]] = newval; + write_byte(client, param->msb[0], newval); + mutex_unlock(&data->update_lock); + return count; +} + +static ssize_t show_pwm_enable(struct device *dev, + struct device_attribute *attr, char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + u8 config, altbit, minoff, val, newval; + + mutex_lock(&data->update_lock); + config = (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; + altbit = (data->reg[param->msb[1]] >> param->shift[1]) & param->mask[1]; + minoff = (data->reg[param->msb[2]] >> param->shift[2]) & param->mask[2]; + mutex_unlock(&data->update_lock); + + val = config | (altbit << 3); + newval = 0; + + if (val == 3 || val >= 10) + newval = 255; + else if (val == 4) + newval = 0; + else if (val == 7) + newval = 1; + else if (minoff == 1) + newval = 2; + else + newval = 3; + + return sprintf(buf, "%u\n", newval); +} + +static ssize_t store_pwm_enable(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + SETUP_STORE_data_param(dev, attr); + long reqval; + u8 currval, config, altbit, newval, minoff = 255; + + if (strict_strtol(buf, 10, &reqval)) + return -EINVAL; + + switch (reqval) { + case 0: + newval = 0x04; + break; + case 1: + newval = 0x07; + break; + case 2: + newval = 0x00; + minoff = 1; + break; + case 3: + newval = 0x00; + minoff = 0; + break; + case 255: + newval = 0x03; + break; + default: + return -EINVAL; + } + + config = newval & 0x07; + altbit = (newval >> 3) & 0x01; + + mutex_lock(&data->update_lock); + config = (config & param->mask[0]) << param->shift[0]; + altbit = (altbit & param->mask[1]) << param->shift[1]; + currval = read_byte(client, param->msb[0]); + newval = config | (currval & ~(param->mask[0] << param->shift[0])); + newval = altbit | (newval & ~(param->mask[1] << param->shift[1])); + data->reg[param->msb[0]] = newval; + write_byte(client, param->msb[0], newval); + if (minoff < 255) { + minoff = (minoff & param->mask[2]) << param->shift[2]; + currval = read_byte(client, param->msb[2]); + newval = + minoff | (currval & ~(param->mask[2] << param->shift[2])); + data->reg[param->msb[2]] = newval; + write_byte(client, param->msb[2], newval); + } + mutex_unlock(&data->update_lock); + return count; +} + +static u32 asc7621_pwm_freq_map[] = { + 10, 15, 23, 30, 38, 47, 62, 94, + 23000, 24000, 25000, 26000, 27000, 28000, 29000, 30000 +}; + +static ssize_t show_pwm_freq(struct device *dev, + struct device_attribute *attr, char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + u8 regval = + (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; + + regval = SENSORS_LIMIT(regval, 0, 15); + + return sprintf(buf, "%u\n", asc7621_pwm_freq_map[regval]); +} + +static ssize_t store_pwm_freq(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + SETUP_STORE_data_param(dev, attr); + unsigned long reqval; + u8 currval, newval = 255; + int i; + + if (strict_strtoul(buf, 10, &reqval)) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(asc7621_pwm_freq_map); i++) { + if (reqval == asc7621_pwm_freq_map[i]) { + newval = i; + break; + } + } + if (newval == 255) + return -EINVAL; + + newval = (newval & param->mask[0]) << param->shift[0]; + + mutex_lock(&data->update_lock); + currval = read_byte(client, param->msb[0]); + newval |= (currval & ~(param->mask[0] << param->shift[0])); + data->reg[param->msb[0]] = newval; + write_byte(client, param->msb[0], newval); + mutex_unlock(&data->update_lock); + return count; +} + +static u32 asc7621_pwm_auto_spinup_map[] = { + 0, 100, 250, 400, 700, 1000, 2000, 4000 +}; + +static ssize_t show_pwm_ast(struct device *dev, + struct device_attribute *attr, char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + u8 regval = + (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; + + regval = SENSORS_LIMIT(regval, 0, 7); + + return sprintf(buf, "%u\n", asc7621_pwm_auto_spinup_map[regval]); + +} + +static ssize_t store_pwm_ast(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + SETUP_STORE_data_param(dev, attr); + long reqval; + u8 currval, newval = 255; + u32 i; + + if (strict_strtol(buf, 10, &reqval)) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(asc7621_pwm_auto_spinup_map); i++) { + if (reqval == asc7621_pwm_auto_spinup_map[i]) { + newval = i; + break; + } + } + if (newval == 255) + return -EINVAL; + + newval = (newval & param->mask[0]) << param->shift[0]; + + mutex_lock(&data->update_lock); + currval = read_byte(client, param->msb[0]); + newval |= (currval & ~(param->mask[0] << param->shift[0])); + data->reg[param->msb[0]] = newval; + write_byte(client, param->msb[0], newval); + mutex_unlock(&data->update_lock); + return count; +} + +static u32 asc7621_temp_smoothing_time_map[] = { + 35000, 17600, 11800, 7000, 4400, 3000, 1600, 800 +}; + +static ssize_t show_temp_st(struct device *dev, + struct device_attribute *attr, char *buf) +{ + SETUP_SHOW_data_param(dev, attr); + u8 regval = + (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; + regval = SENSORS_LIMIT(regval, 0, 7); + + return sprintf(buf, "%u\n", asc7621_temp_smoothing_time_map[regval]); +} + +static ssize_t store_temp_st(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + SETUP_STORE_data_param(dev, attr); + long reqval; + u8 currval, newval = 255; + u32 i; + + if (strict_strtol(buf, 10, &reqval)) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(asc7621_temp_smoothing_time_map); i++) { + if (reqval == asc7621_temp_smoothing_time_map[i]) { + newval = i; + break; + } + } + + if (newval == 255) + return -EINVAL; + + newval = (newval & param->mask[0]) << param->shift[0]; + + mutex_lock(&data->update_lock); + currval = read_byte(client, param->msb[0]); + newval |= (currval & ~(param->mask[0] << param->shift[0])); + data->reg[param->msb[0]] = newval; + write_byte(client, param->msb[0], newval); + mutex_unlock(&data->update_lock); + return count; +} + +/* + * End of data handlers + * + * These defines do nothing more than make the table easier + * to read when wrapped at column 80. + */ + +/* + * Creates a variable length array inititalizer. + * VAA(1,3,5,7) would produce {1,3,5,7} + */ +#define VAA(args...) {args} + +#define PREAD(name, n, pri, rm, rl, m, s, r) \ + {.sda = SENSOR_ATTR(name, S_IRUGO, show_##r, NULL, n), \ + .priority = pri, .msb[0] = rm, .lsb[0] = rl, .mask[0] = m, \ + .shift[0] = s,} + +#define PWRITE(name, n, pri, rm, rl, m, s, r) \ + {.sda = SENSOR_ATTR(name, S_IRUGO | S_IWUSR, show_##r, store_##r, n), \ + .priority = pri, .msb[0] = rm, .lsb[0] = rl, .mask[0] = m, \ + .shift[0] = s,} + +/* + * PWRITEM assumes that the initializers for the .msb, .lsb, .mask and .shift + * were created using the VAA macro. + */ +#define PWRITEM(name, n, pri, rm, rl, m, s, r) \ + {.sda = SENSOR_ATTR(name, S_IRUGO | S_IWUSR, show_##r, store_##r, n), \ + .priority = pri, .msb = rm, .lsb = rl, .mask = m, .shift = s,} + +static struct asc7621_param asc7621_params[] = { + PREAD(in0_input, 0, PRI_HIGH, 0x20, 0x13, 0, 0, in10), + PREAD(in1_input, 1, PRI_HIGH, 0x21, 0x18, 0, 0, in10), + PREAD(in2_input, 2, PRI_HIGH, 0x22, 0x11, 0, 0, in10), + PREAD(in3_input, 3, PRI_HIGH, 0x23, 0x12, 0, 0, in10), + PREAD(in4_input, 4, PRI_HIGH, 0x24, 0x14, 0, 0, in10), + + PWRITE(in0_min, 0, PRI_LOW, 0x44, 0, 0, 0, in8), + PWRITE(in1_min, 1, PRI_LOW, 0x46, 0, 0, 0, in8), + PWRITE(in2_min, 2, PRI_LOW, 0x48, 0, 0, 0, in8), + PWRITE(in3_min, 3, PRI_LOW, 0x4a, 0, 0, 0, in8), + PWRITE(in4_min, 4, PRI_LOW, 0x4c, 0, 0, 0, in8), + + PWRITE(in0_max, 0, PRI_LOW, 0x45, 0, 0, 0, in8), + PWRITE(in1_max, 1, PRI_LOW, 0x47, 0, 0, 0, in8), + PWRITE(in2_max, 2, PRI_LOW, 0x49, 0, 0, 0, in8), + PWRITE(in3_max, 3, PRI_LOW, 0x4b, 0, 0, 0, in8), + PWRITE(in4_max, 4, PRI_LOW, 0x4d, 0, 0, 0, in8), + + PREAD(in0_alarm, 0, PRI_LOW, 0x41, 0, 0x01, 0, bitmask), + PREAD(in1_alarm, 1, PRI_LOW, 0x41, 0, 0x01, 1, bitmask), + PREAD(in2_alarm, 2, PRI_LOW, 0x41, 0, 0x01, 2, bitmask), + PREAD(in3_alarm, 3, PRI_LOW, 0x41, 0, 0x01, 3, bitmask), + PREAD(in4_alarm, 4, PRI_LOW, 0x42, 0, 0x01, 0, bitmask), + + PREAD(fan1_input, 0, PRI_HIGH, 0x29, 0x28, 0, 0, fan16), + PREAD(fan2_input, 1, PRI_HIGH, 0x2b, 0x2a, 0, 0, fan16), + PREAD(fan3_input, 2, PRI_HIGH, 0x2d, 0x2c, 0, 0, fan16), + PREAD(fan4_input, 3, PRI_HIGH, 0x2f, 0x2e, 0, 0, fan16), + + PWRITE(fan1_min, 0, PRI_LOW, 0x55, 0x54, 0, 0, fan16), + PWRITE(fan2_min, 1, PRI_LOW, 0x57, 0x56, 0, 0, fan16), + PWRITE(fan3_min, 2, PRI_LOW, 0x59, 0x58, 0, 0, fan16), + PWRITE(fan4_min, 3, PRI_LOW, 0x5b, 0x5a, 0, 0, fan16), + + PREAD(fan1_alarm, 0, PRI_LOW, 0x42, 0, 0x01, 0, bitmask), + PREAD(fan2_alarm, 1, PRI_LOW, 0x42, 0, 0x01, 1, bitmask), + PREAD(fan3_alarm, 2, PRI_LOW, 0x42, 0, 0x01, 2, bitmask), + PREAD(fan4_alarm, 3, PRI_LOW, 0x42, 0, 0x01, 3, bitmask), + + PREAD(temp1_input, 0, PRI_HIGH, 0x25, 0x10, 0, 0, temp10), + PREAD(temp2_input, 1, PRI_HIGH, 0x26, 0x15, 0, 0, temp10), + PREAD(temp3_input, 2, PRI_HIGH, 0x27, 0x16, 0, 0, temp10), + PREAD(temp4_input, 3, PRI_HIGH, 0x33, 0x17, 0, 0, temp10), + PREAD(temp5_input, 4, PRI_HIGH, 0xf7, 0xf6, 0, 0, temp10), + PREAD(temp6_input, 5, PRI_HIGH, 0xf9, 0xf8, 0, 0, temp10), + PREAD(temp7_input, 6, PRI_HIGH, 0xfb, 0xfa, 0, 0, temp10), + PREAD(temp8_input, 7, PRI_HIGH, 0xfd, 0xfc, 0, 0, temp10), + + PWRITE(temp1_min, 0, PRI_LOW, 0x4e, 0, 0, 0, temp8), + PWRITE(temp2_min, 1, PRI_LOW, 0x50, 0, 0, 0, temp8), + PWRITE(temp3_min, 2, PRI_LOW, 0x52, 0, 0, 0, temp8), + PWRITE(temp4_min, 3, PRI_LOW, 0x34, 0, 0, 0, temp8), + + PWRITE(temp1_max, 0, PRI_LOW, 0x4f, 0, 0, 0, temp8), + PWRITE(temp2_max, 1, PRI_LOW, 0x51, 0, 0, 0, temp8), + PWRITE(temp3_max, 2, PRI_LOW, 0x53, 0, 0, 0, temp8), + PWRITE(temp4_max, 3, PRI_LOW, 0x35, 0, 0, 0, temp8), + + PREAD(temp1_alarm, 0, PRI_LOW, 0x41, 0, 0x01, 4, bitmask), + PREAD(temp2_alarm, 1, PRI_LOW, 0x41, 0, 0x01, 5, bitmask), + PREAD(temp3_alarm, 2, PRI_LOW, 0x41, 0, 0x01, 6, bitmask), + PREAD(temp4_alarm, 3, PRI_LOW, 0x43, 0, 0x01, 0, bitmask), + + PWRITE(temp1_source, 0, PRI_LOW, 0x02, 0, 0x07, 4, bitmask), + PWRITE(temp2_source, 1, PRI_LOW, 0x02, 0, 0x07, 0, bitmask), + PWRITE(temp3_source, 2, PRI_LOW, 0x03, 0, 0x07, 4, bitmask), + PWRITE(temp4_source, 3, PRI_LOW, 0x03, 0, 0x07, 0, bitmask), + + PWRITE(temp1_smoothing_enable, 0, PRI_LOW, 0x62, 0, 0x01, 3, bitmask), + PWRITE(temp2_smoothing_enable, 1, PRI_LOW, 0x63, 0, 0x01, 7, bitmask), + PWRITE(temp3_smoothing_enable, 2, PRI_LOW, 0x64, 0, 0x01, 3, bitmask), + PWRITE(temp4_smoothing_enable, 3, PRI_LOW, 0x3c, 0, 0x01, 3, bitmask), + + PWRITE(temp1_smoothing_time, 0, PRI_LOW, 0x62, 0, 0x07, 0, temp_st), + PWRITE(temp2_smoothing_time, 1, PRI_LOW, 0x63, 0, 0x07, 4, temp_st), + PWRITE(temp3_smoothing_time, 2, PRI_LOW, 0x63, 0, 0x07, 0, temp_st), + PWRITE(temp4_smoothing_time, 3, PRI_LOW, 0x3c, 0, 0x07, 0, temp_st), + + PWRITE(temp1_auto_point1_temp_hyst, 0, PRI_LOW, 0x6d, 0, 0x0f, 4, + bitmask), + PWRITE(temp2_auto_point1_temp_hyst, 1, PRI_LOW, 0x6d, 0, 0x0f, 0, + bitmask), + PWRITE(temp3_auto_point1_temp_hyst, 2, PRI_LOW, 0x6e, 0, 0x0f, 4, + bitmask), + PWRITE(temp4_auto_point1_temp_hyst, 3, PRI_LOW, 0x6e, 0, 0x0f, 0, + bitmask), + + PREAD(temp1_auto_point2_temp_hyst, 0, PRI_LOW, 0x6d, 0, 0x0f, 4, + bitmask), + PREAD(temp2_auto_point2_temp_hyst, 1, PRI_LOW, 0x6d, 0, 0x0f, 0, + bitmask), + PREAD(temp3_auto_point2_temp_hyst, 2, PRI_LOW, 0x6e, 0, 0x0f, 4, + bitmask), + PREAD(temp4_auto_point2_temp_hyst, 3, PRI_LOW, 0x6e, 0, 0x0f, 0, + bitmask), + + PWRITE(temp1_auto_point1_temp, 0, PRI_LOW, 0x67, 0, 0, 0, temp8), + PWRITE(temp2_auto_point1_temp, 1, PRI_LOW, 0x68, 0, 0, 0, temp8), + PWRITE(temp3_auto_point1_temp, 2, PRI_LOW, 0x69, 0, 0, 0, temp8), + PWRITE(temp4_auto_point1_temp, 3, PRI_LOW, 0x3b, 0, 0, 0, temp8), + + PWRITEM(temp1_auto_point2_temp, 0, PRI_LOW, VAA(0x5f, 0x67), VAA(0), + VAA(0x0f), VAA(4), ap2_temp), + PWRITEM(temp2_auto_point2_temp, 1, PRI_LOW, VAA(0x60, 0x68), VAA(0), + VAA(0x0f), VAA(4), ap2_temp), + PWRITEM(temp3_auto_point2_temp, 2, PRI_LOW, VAA(0x61, 0x69), VAA(0), + VAA(0x0f), VAA(4), ap2_temp), + PWRITEM(temp4_auto_point2_temp, 3, PRI_LOW, VAA(0x3c, 0x3b), VAA(0), + VAA(0x0f), VAA(4), ap2_temp), + + PWRITE(temp1_crit, 0, PRI_LOW, 0x6a, 0, 0, 0, temp8), + PWRITE(temp2_crit, 1, PRI_LOW, 0x6b, 0, 0, 0, temp8), + PWRITE(temp3_crit, 2, PRI_LOW, 0x6c, 0, 0, 0, temp8), + PWRITE(temp4_crit, 3, PRI_LOW, 0x3d, 0, 0, 0, temp8), + + PWRITE(temp5_enable, 4, PRI_LOW, 0x0e, 0, 0x01, 0, bitmask), + PWRITE(temp6_enable, 5, PRI_LOW, 0x0e, 0, 0x01, 1, bitmask), + PWRITE(temp7_enable, 6, PRI_LOW, 0x0e, 0, 0x01, 2, bitmask), + PWRITE(temp8_enable, 7, PRI_LOW, 0x0e, 0, 0x01, 3, bitmask), + + PWRITE(remote1_offset, 0, PRI_LOW, 0x1c, 0, 0, 0, temp62), + PWRITE(remote2_offset, 1, PRI_LOW, 0x1d, 0, 0, 0, temp62), + + PWRITE(pwm1, 0, PRI_HIGH, 0x30, 0, 0, 0, u8), + PWRITE(pwm2, 1, PRI_HIGH, 0x31, 0, 0, 0, u8), + PWRITE(pwm3, 2, PRI_HIGH, 0x32, 0, 0, 0, u8), + + PWRITE(pwm1_invert, 0, PRI_LOW, 0x5c, 0, 0x01, 4, bitmask), + PWRITE(pwm2_invert, 1, PRI_LOW, 0x5d, 0, 0x01, 4, bitmask), + PWRITE(pwm3_invert, 2, PRI_LOW, 0x5e, 0, 0x01, 4, bitmask), + + PWRITEM(pwm1_enable, 0, PRI_LOW, VAA(0x5c, 0x5c, 0x62), VAA(0, 0, 0), + VAA(0x07, 0x01, 0x01), VAA(5, 3, 5), pwm_enable), + PWRITEM(pwm2_enable, 1, PRI_LOW, VAA(0x5d, 0x5d, 0x62), VAA(0, 0, 0), + VAA(0x07, 0x01, 0x01), VAA(5, 3, 6), pwm_enable), + PWRITEM(pwm3_enable, 2, PRI_LOW, VAA(0x5e, 0x5e, 0x62), VAA(0, 0, 0), + VAA(0x07, 0x01, 0x01), VAA(5, 3, 7), pwm_enable), + + PWRITEM(pwm1_auto_channels, 0, PRI_LOW, VAA(0x5c, 0x5c), VAA(0, 0), + VAA(0x07, 0x01), VAA(5, 3), pwm_ac), + PWRITEM(pwm2_auto_channels, 1, PRI_LOW, VAA(0x5d, 0x5d), VAA(0, 0), + VAA(0x07, 0x01), VAA(5, 3), pwm_ac), + PWRITEM(pwm3_auto_channels, 2, PRI_LOW, VAA(0x5e, 0x5e), VAA(0, 0), + VAA(0x07, 0x01), VAA(5, 3), pwm_ac), + + PWRITE(pwm1_auto_point1_pwm, 0, PRI_LOW, 0x64, 0, 0, 0, u8), + PWRITE(pwm2_auto_point1_pwm, 1, PRI_LOW, 0x65, 0, 0, 0, u8), + PWRITE(pwm3_auto_point1_pwm, 2, PRI_LOW, 0x66, 0, 0, 0, u8), + + PWRITE(pwm1_auto_point2_pwm, 0, PRI_LOW, 0x38, 0, 0, 0, u8), + PWRITE(pwm2_auto_point2_pwm, 1, PRI_LOW, 0x39, 0, 0, 0, u8), + PWRITE(pwm3_auto_point2_pwm, 2, PRI_LOW, 0x3a, 0, 0, 0, u8), + + PWRITE(pwm1_freq, 0, PRI_LOW, 0x5f, 0, 0x0f, 0, pwm_freq), + PWRITE(pwm2_freq, 1, PRI_LOW, 0x60, 0, 0x0f, 0, pwm_freq), + PWRITE(pwm3_freq, 2, PRI_LOW, 0x61, 0, 0x0f, 0, pwm_freq), + + PREAD(pwm1_auto_zone_assigned, 0, PRI_LOW, 0, 0, 0x03, 2, bitmask), + PREAD(pwm2_auto_zone_assigned, 1, PRI_LOW, 0, 0, 0x03, 4, bitmask), + PREAD(pwm3_auto_zone_assigned, 2, PRI_LOW, 0, 0, 0x03, 6, bitmask), + + PWRITE(pwm1_auto_spinup_time, 0, PRI_LOW, 0x5c, 0, 0x07, 0, pwm_ast), + PWRITE(pwm2_auto_spinup_time, 1, PRI_LOW, 0x5d, 0, 0x07, 0, pwm_ast), + PWRITE(pwm3_auto_spinup_time, 2, PRI_LOW, 0x5e, 0, 0x07, 0, pwm_ast), + + PWRITE(peci_enable, 0, PRI_LOW, 0x40, 0, 0x01, 4, bitmask), + PWRITE(peci_avg, 0, PRI_LOW, 0x36, 0, 0x07, 0, bitmask), + PWRITE(peci_domain, 0, PRI_LOW, 0x36, 0, 0x01, 3, bitmask), + PWRITE(peci_legacy, 0, PRI_LOW, 0x36, 0, 0x01, 4, bitmask), + PWRITE(peci_diode, 0, PRI_LOW, 0x0e, 0, 0x07, 4, bitmask), + PWRITE(peci_4domain, 0, PRI_LOW, 0x0e, 0, 0x01, 4, bitmask), + +}; + +static struct asc7621_data *asc7621_update_device(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct asc7621_data *data = i2c_get_clientdata(client); + int i; + +/* + * The asc7621 chips guarantee consistent reads of multi-byte values + * regardless of the order of the reads. No special logic is needed + * so we can just read the registers in whatever order they appear + * in the asc7621_params array. + */ + + mutex_lock(&data->update_lock); + + /* Read all the high priority registers */ + + if (!data->valid || + time_after(jiffies, data->last_high_reading + INTERVAL_HIGH)) { + + for (i = 0; i < ARRAY_SIZE(asc7621_register_priorities); i++) { + if (asc7621_register_priorities[i] == PRI_HIGH) { + data->reg[i] = + i2c_smbus_read_byte_data(client, i) & 0xff; + } + } + data->last_high_reading = jiffies; + }; /* last_reading */ + + /* Read all the low priority registers. */ + + if (!data->valid || + time_after(jiffies, data->last_low_reading + INTERVAL_LOW)) { + + for (i = 0; i < ARRAY_SIZE(asc7621_params); i++) { + if (asc7621_register_priorities[i] == PRI_LOW) { + data->reg[i] = + i2c_smbus_read_byte_data(client, i) & 0xff; + } + } + data->last_low_reading = jiffies; + }; /* last_reading */ + + data->valid = 1; + + mutex_unlock(&data->update_lock); + + return data; +} + +/* + * Standard detection and initialization below + * + * Helper function that checks if an address is valid + * for a particular chip. + */ + +static inline int valid_address_for_chip(int chip_type, int address) +{ + int i; + + for (i = 0; asc7621_chips[chip_type].addresses[i] != I2C_CLIENT_END; + i++) { + if (asc7621_chips[chip_type].addresses[i] == address) + return 1; + } + return 0; +} + +static void asc7621_init_client(struct i2c_client *client) +{ + int value; + + /* Warn if part was not "READY" */ + + value = read_byte(client, 0x40); + + if (value & 0x02) { + dev_err(&client->dev, + "Client (%d,0x%02x) config is locked.\n", + i2c_adapter_id(client->adapter), client->addr); + }; + if (!(value & 0x04)) { + dev_err(&client->dev, "Client (%d,0x%02x) is not ready.\n", + i2c_adapter_id(client->adapter), client->addr); + }; + +/* + * Start monitoring + * + * Try to clear LOCK, Set START, save everything else + */ + value = (value & ~0x02) | 0x01; + write_byte(client, 0x40, value & 0xff); + +} + +static int +asc7621_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct asc7621_data *data; + int i, err; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) + return -EIO; + + data = kzalloc(sizeof(struct asc7621_data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + + i2c_set_clientdata(client, data); + data->valid = 0; + mutex_init(&data->update_lock); + + /* Initialize the asc7621 chip */ + asc7621_init_client(client); + + /* Create the sysfs entries */ + for (i = 0; i < ARRAY_SIZE(asc7621_params); i++) { + err = + device_create_file(&client->dev, + &(asc7621_params[i].sda.dev_attr)); + if (err) + goto exit_remove; + } + + data->class_dev = hwmon_device_register(&client->dev); + if (IS_ERR(data->class_dev)) { + err = PTR_ERR(data->class_dev); + goto exit_remove; + } + + return 0; + +exit_remove: + for (i = 0; i < ARRAY_SIZE(asc7621_params); i++) { + device_remove_file(&client->dev, + &(asc7621_params[i].sda.dev_attr)); + } + + i2c_set_clientdata(client, NULL); + kfree(data); + return err; +} + +static int asc7621_detect(struct i2c_client *client, + struct i2c_board_info *info) +{ + struct i2c_adapter *adapter = client->adapter; + int company, verstep, chip_index; + struct device *dev; + + dev = &client->dev; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) + return -ENODEV; + + for (chip_index = FIRST_CHIP; chip_index <= LAST_CHIP; chip_index++) { + + if (!valid_address_for_chip(chip_index, client->addr)) + continue; + + company = read_byte(client, + asc7621_chips[chip_index].company_reg); + verstep = read_byte(client, + asc7621_chips[chip_index].verstep_reg); + + if (company == asc7621_chips[chip_index].company_id && + verstep == asc7621_chips[chip_index].verstep_id) { + strlcpy(client->name, asc7621_chips[chip_index].name, + I2C_NAME_SIZE); + strlcpy(info->type, asc7621_chips[chip_index].name, + I2C_NAME_SIZE); + + dev_info(&adapter->dev, "Matched %s\n", + asc7621_chips[chip_index].name); + return 0; + } + } + + return -ENODEV; +} + +static int asc7621_remove(struct i2c_client *client) +{ + struct asc7621_data *data = i2c_get_clientdata(client); + int i; + + hwmon_device_unregister(data->class_dev); + + for (i = 0; i < ARRAY_SIZE(asc7621_params); i++) { + device_remove_file(&client->dev, + &(asc7621_params[i].sda.dev_attr)); + } + + i2c_set_clientdata(client, NULL); + kfree(data); + return 0; +} + +static const struct i2c_device_id asc7621_id[] = { + {"asc7621", asc7621}, + {"asc7621a", asc7621a}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, asc7621_id); + +static struct i2c_driver asc7621_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "asc7621", + }, + .probe = asc7621_probe, + .remove = asc7621_remove, + .id_table = asc7621_id, + .detect = asc7621_detect, + .address_list = normal_i2c, +}; + +static int __init sm_asc7621_init(void) +{ + int i, j; +/* + * Collect all the registers needed into a single array. + * This way, if a register isn't actually used for anything, + * we don't retrieve it. + */ + + for (i = 0; i < ARRAY_SIZE(asc7621_params); i++) { + for (j = 0; j < ARRAY_SIZE(asc7621_params[i].msb); j++) + asc7621_register_priorities[asc7621_params[i].msb[j]] = + asc7621_params[i].priority; + for (j = 0; j < ARRAY_SIZE(asc7621_params[i].lsb); j++) + asc7621_register_priorities[asc7621_params[i].lsb[j]] = + asc7621_params[i].priority; + } + return i2c_add_driver(&asc7621_driver); +} + +static void __exit sm_asc7621_exit(void) +{ + i2c_del_driver(&asc7621_driver); +} + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("George Joseph"); +MODULE_DESCRIPTION("Andigilog aSC7621 and aSC7621a driver"); + +module_init(sm_asc7621_init); +module_exit(sm_asc7621_exit); -- cgit v1.2.3 From 8d59582a867470a3e0c3eced4a01625ae8dc546b Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:25 +0100 Subject: hwmon: (tmp421) Restore missing inputs An off-by-one error caused some inputs to not be created by the driver when they should. TMP421 gets only one input instead of two, TMP422 gets two instead of three, etc. Fix the bug by listing explicitly the number of inputs each device has. Signed-off-by: Jean Delvare Tested-by: Andre Prendel Cc: stable@kernel.org --- drivers/hwmon/tmp421.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/tmp421.c b/drivers/hwmon/tmp421.c index 4f7c051e2d7b..a97e299b233b 100644 --- a/drivers/hwmon/tmp421.c +++ b/drivers/hwmon/tmp421.c @@ -61,9 +61,9 @@ static const u8 TMP421_TEMP_LSB[4] = { 0x10, 0x11, 0x12, 0x13 }; #define TMP423_DEVICE_ID 0x23 static const struct i2c_device_id tmp421_id[] = { - { "tmp421", tmp421 }, - { "tmp422", tmp422 }, - { "tmp423", tmp423 }, + { "tmp421", 2 }, + { "tmp422", 3 }, + { "tmp423", 4 }, { } }; MODULE_DEVICE_TABLE(i2c, tmp421_id); @@ -73,7 +73,7 @@ struct tmp421_data { struct mutex update_lock; char valid; unsigned long last_updated; - int kind; + int channels; u8 config; s16 temp[4]; }; @@ -107,7 +107,7 @@ static struct tmp421_data *tmp421_update_device(struct device *dev) data->config = i2c_smbus_read_byte_data(client, TMP421_CONFIG_REG_1); - for (i = 0; i <= data->kind; i++) { + for (i = 0; i < data->channels; i++) { data->temp[i] = i2c_smbus_read_byte_data(client, TMP421_TEMP_MSB[i]) << 8; data->temp[i] |= i2c_smbus_read_byte_data(client, @@ -166,7 +166,7 @@ static mode_t tmp421_is_visible(struct kobject *kobj, struct attribute *a, devattr = container_of(a, struct device_attribute, attr); index = to_sensor_dev_attr(devattr)->index; - if (data->kind > index) + if (index < data->channels) return a->mode; return 0; @@ -271,7 +271,7 @@ static int tmp421_probe(struct i2c_client *client, i2c_set_clientdata(client, data); mutex_init(&data->update_lock); - data->kind = id->driver_data; + data->channels = id->driver_data; err = tmp421_init_client(client); if (err) -- cgit v1.2.3 From a44908d742a577fb5ccb9a8c082326d4cea234c2 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:25 +0100 Subject: hwmon: (tmp421) Fix temperature conversions The low bits of temperature registers are status bits, they must be masked out before converting the register values to temperatures. Signed-off-by: Jean Delvare Tested-by: Andre Prendel Cc: stable@kernel.org --- drivers/hwmon/tmp421.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/tmp421.c b/drivers/hwmon/tmp421.c index a97e299b233b..bb9760d7e8b6 100644 --- a/drivers/hwmon/tmp421.c +++ b/drivers/hwmon/tmp421.c @@ -80,14 +80,16 @@ struct tmp421_data { static int temp_from_s16(s16 reg) { - int temp = reg; + /* Mask out status bits */ + int temp = reg & ~0xf; return (temp * 1000 + 128) / 256; } static int temp_from_u16(u16 reg) { - int temp = reg; + /* Mask out status bits */ + int temp = reg & ~0xf; /* Add offset for extended temperature range. */ temp -= 64 * 256; -- cgit v1.2.3 From dc71afe5ac7e8d049bb991330518e4c898a7d92e Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Fri, 5 Mar 2010 22:17:26 +0100 Subject: hwmon: Fix off-by-one kind values Recent changes on the I2C front have left off-by-one array indexes in 3 hwmon drivers. Fix them. Faulty commit: e5e9f44c2 i2c: Drop I2C_CLIENT_INSMOD_2 to 8 Reported-by: Dan Carpenter Signed-off-by: Jean Delvare Cc: Hans de Goede Cc: Andre Prendel Cc: stable@kernel.org --- drivers/hwmon/fschmd.c | 15 ++++++--------- drivers/hwmon/tmp401.c | 7 +++---- drivers/hwmon/tmp421.c | 4 ++-- 3 files changed, 11 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/fschmd.c b/drivers/hwmon/fschmd.c index fa0728232e71..0627f7a5b9b8 100644 --- a/drivers/hwmon/fschmd.c +++ b/drivers/hwmon/fschmd.c @@ -267,7 +267,7 @@ struct fschmd_data { struct list_head list; /* member of the watchdog_data_list */ struct kref kref; struct miscdevice watchdog_miscdev; - int kind; + enum chips kind; unsigned long watchdog_is_open; char watchdog_expect_close; char watchdog_name[10]; /* must be unique to avoid sysfs conflict */ @@ -325,8 +325,7 @@ static ssize_t show_in_value(struct device *dev, int index = to_sensor_dev_attr(devattr)->index; struct fschmd_data *data = fschmd_update_device(dev); - /* fscher / fschrc - 1 as data->kind is an array index, not a chips */ - if (data->kind == (fscher - 1) || data->kind >= (fschrc - 1)) + if (data->kind == fscher || data->kind >= fschrc) return sprintf(buf, "%d\n", (data->volt[index] * dmi_vref * dmi_mult[index]) / 255 + dmi_offset[index]); else @@ -492,7 +491,7 @@ static ssize_t show_pwm_auto_point1_pwm(struct device *dev, int val = data->fan_min[index]; /* 0 = allow turning off (except on the syl), 1-255 = 50-100% */ - if (val || data->kind == fscsyl - 1) + if (val || data->kind == fscsyl) val = val / 2 + 128; return sprintf(buf, "%d\n", val); @@ -506,7 +505,7 @@ static ssize_t store_pwm_auto_point1_pwm(struct device *dev, unsigned long v = simple_strtoul(buf, NULL, 10); /* reg: 0 = allow turning off (except on the syl), 1-255 = 50-100% */ - if (v || data->kind == fscsyl - 1) { + if (v || data->kind == fscsyl) { v = SENSORS_LIMIT(v, 128, 255); v = (v - 128) * 2 + 1; } @@ -1037,7 +1036,7 @@ static int fschmd_detect(struct i2c_client *client, else return -ENODEV; - strlcpy(info->type, fschmd_id[kind - 1].name, I2C_NAME_SIZE); + strlcpy(info->type, fschmd_id[kind].name, I2C_NAME_SIZE); return 0; } @@ -1065,6 +1064,7 @@ static int fschmd_probe(struct i2c_client *client, (where the client is found through a data ptr instead of the otherway around) */ data->client = client; + data->kind = kind; if (kind == fscpos) { /* The Poseidon has hardwired temp limits, fill these @@ -1085,9 +1085,6 @@ static int fschmd_probe(struct i2c_client *client, } } - /* i2c kind goes from 1-6, we want from 0-5 to address arrays */ - data->kind = kind - 1; - /* Read in some never changing registers */ data->revision = i2c_smbus_read_byte_data(client, FSCHMD_REG_REVISION); data->global_control = i2c_smbus_read_byte_data(client, diff --git a/drivers/hwmon/tmp401.c b/drivers/hwmon/tmp401.c index a13b30e8d8d8..d14a1af9f550 100644 --- a/drivers/hwmon/tmp401.c +++ b/drivers/hwmon/tmp401.c @@ -134,7 +134,7 @@ struct tmp401_data { struct mutex update_lock; char valid; /* zero until following fields are valid */ unsigned long last_updated; /* in jiffies */ - int kind; + enum chips kind; /* register values */ u8 status; @@ -524,7 +524,7 @@ static int tmp401_detect(struct i2c_client *client, if (reg > 15) return -ENODEV; - strlcpy(info->type, tmp401_id[kind - 1].name, I2C_NAME_SIZE); + strlcpy(info->type, tmp401_id[kind].name, I2C_NAME_SIZE); return 0; } @@ -572,8 +572,7 @@ static int tmp401_probe(struct i2c_client *client, goto exit_remove; } - dev_info(&client->dev, "Detected TI %s chip\n", - names[data->kind - 1]); + dev_info(&client->dev, "Detected TI %s chip\n", names[data->kind]); return 0; diff --git a/drivers/hwmon/tmp421.c b/drivers/hwmon/tmp421.c index bb9760d7e8b6..738c472ece27 100644 --- a/drivers/hwmon/tmp421.c +++ b/drivers/hwmon/tmp421.c @@ -254,9 +254,9 @@ static int tmp421_detect(struct i2c_client *client, return -ENODEV; } - strlcpy(info->type, tmp421_id[kind - 1].name, I2C_NAME_SIZE); + strlcpy(info->type, tmp421_id[kind].name, I2C_NAME_SIZE); dev_info(&adapter->dev, "Detected TI %s chip at 0x%02x\n", - names[kind - 1], client->addr); + names[kind], client->addr); return 0; } -- cgit v1.2.3 From a0a5e3488a51c46f383c5faa86b53828e30ce153 Mon Sep 17 00:00:00 2001 From: Amerigo Wang Date: Fri, 5 Mar 2010 22:17:26 +0100 Subject: hwmon: Remove the deprecated adt7473 driver adt7473 driver is obsoleted by adt7475 driver. And it is scheduled to be removed in Feb 2010. Signed-off-by: WANG Cong Signed-off-by: Jean Delvare --- Documentation/feature-removal-schedule.txt | 6 - Documentation/hwmon/adt7473 | 74 -- drivers/hwmon/Kconfig | 14 - drivers/hwmon/Makefile | 1 - drivers/hwmon/adt7473.c | 1180 ---------------------------- 5 files changed, 1275 deletions(-) delete mode 100644 Documentation/hwmon/adt7473 delete mode 100644 drivers/hwmon/adt7473.c (limited to 'drivers') diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt index 03497909539e..8debdd625e1a 100644 --- a/Documentation/feature-removal-schedule.txt +++ b/Documentation/feature-removal-schedule.txt @@ -449,12 +449,6 @@ Who: Alok N Kataria ---------------------------- -What: adt7473 hardware monitoring driver -When: February 2010 -Why: Obsoleted by the adt7475 driver. -Who: Jean Delvare - ---------------------------- What: Support for lcd_switch and display_get in asus-laptop driver When: March 2010 Why: These two features use non-standard interfaces. There are the diff --git a/Documentation/hwmon/adt7473 b/Documentation/hwmon/adt7473 deleted file mode 100644 index 446612bd1fb9..000000000000 --- a/Documentation/hwmon/adt7473 +++ /dev/null @@ -1,74 +0,0 @@ -Kernel driver adt7473 -====================== - -Supported chips: - * Analog Devices ADT7473 - Prefix: 'adt7473' - Addresses scanned: I2C 0x2C, 0x2D, 0x2E - Datasheet: Publicly available at the Analog Devices website - -Author: Darrick J. Wong - -This driver is depreacted, please use the adt7475 driver instead. - -Description ------------ - -This driver implements support for the Analog Devices ADT7473 chip family. - -The ADT7473 uses the 2-wire interface compatible with the SMBUS 2.0 -specification. Using an analog to digital converter it measures three (3) -temperatures and two (2) voltages. It has four (4) 16-bit counters for -measuring fan speed. There are three (3) PWM outputs that can be used -to control fan speed. - -A sophisticated control system for the PWM outputs is designed into the -ADT7473 that allows fan speed to be adjusted automatically based on any of the -three temperature sensors. Each PWM output is individually adjustable and -programmable. Once configured, the ADT7473 will adjust the PWM outputs in -response to the measured temperatures without further host intervention. -This feature can also be disabled for manual control of the PWM's. - -Each of the measured inputs (voltage, temperature, fan speed) has -corresponding high/low limit values. The ADT7473 will signal an ALARM if -any measured value exceeds either limit. - -The ADT7473 samples all inputs continuously. The driver will not read -the registers more often than once every other second. Further, -configuration data is only read once per minute. - -Special Features ----------------- - -The ADT7473 have a 10-bit ADC and can therefore measure temperatures -with 0.25 degC resolution. Temperature readings can be configured either -for twos complement format or "Offset 64" format, wherein 63 is subtracted -from the raw value to get the temperature value. - -The Analog Devices datasheet is very detailed and describes a procedure for -determining an optimal configuration for the automatic PWM control. - -Configuration Notes -------------------- - -Besides standard interfaces driver adds the following: - -* PWM Control - -* pwm#_auto_point1_pwm and temp#_auto_point1_temp and -* pwm#_auto_point2_pwm and temp#_auto_point2_temp - - -point1: Set the pwm speed at a lower temperature bound. -point2: Set the pwm speed at a higher temperature bound. - -The ADT7473 will scale the pwm between the lower and higher pwm speed when -the temperature is between the two temperature boundaries. PWM values range -from 0 (off) to 255 (full speed). Fan speed will be set to maximum when the -temperature sensor associated with the PWM control exceeds temp#_max. - -Notes ------ - -The NVIDIA binary driver presents an ADT7473 chip via an on-card i2c bus. -Unfortunately, they fail to set the i2c adapter class, so this driver may -fail to find the chip until the nvidia driver is patched. diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index b6d65aa20825..e4595e6147b4 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -200,20 +200,6 @@ config SENSORS_ADT7470 This driver can also be built as a module. If so, the module will be called adt7470. -config SENSORS_ADT7473 - tristate "Analog Devices ADT7473 (DEPRECATED)" - depends on I2C && EXPERIMENTAL - select SENSORS_ADT7475 - help - If you say yes here you get support for the Analog Devices - ADT7473 temperature monitoring chips. - - This driver is deprecated, you should use the adt7475 driver - instead. - - This driver can also be built as a module. If so, the module - will be called adt7473. - config SENSORS_ADT7475 tristate "Analog Devices ADT7473, ADT7475, ADT7476 and ADT7490" depends on I2C && EXPERIMENTAL diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 865da80f2b90..4aa1a3d112ad 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -32,7 +32,6 @@ obj-$(CONFIG_SENSORS_ADS7828) += ads7828.o obj-$(CONFIG_SENSORS_ADT7411) += adt7411.o obj-$(CONFIG_SENSORS_ADT7462) += adt7462.o obj-$(CONFIG_SENSORS_ADT7470) += adt7470.o -obj-$(CONFIG_SENSORS_ADT7473) += adt7473.o obj-$(CONFIG_SENSORS_ADT7475) += adt7475.o obj-$(CONFIG_SENSORS_APPLESMC) += applesmc.o obj-$(CONFIG_SENSORS_AMS) += ams/ diff --git a/drivers/hwmon/adt7473.c b/drivers/hwmon/adt7473.c deleted file mode 100644 index 434576f61c84..000000000000 --- a/drivers/hwmon/adt7473.c +++ /dev/null @@ -1,1180 +0,0 @@ -/* - * A hwmon driver for the Analog Devices ADT7473 - * Copyright (C) 2007 IBM - * - * Author: Darrick J. Wong - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Addresses to scan */ -static const unsigned short normal_i2c[] = { 0x2C, 0x2D, 0x2E, I2C_CLIENT_END }; - -/* ADT7473 registers */ -#define ADT7473_REG_BASE_ADDR 0x20 - -#define ADT7473_REG_VOLT_BASE_ADDR 0x21 -#define ADT7473_REG_VOLT_MIN_BASE_ADDR 0x46 - -#define ADT7473_REG_TEMP_BASE_ADDR 0x25 -#define ADT7473_REG_TEMP_LIMITS_BASE_ADDR 0x4E -#define ADT7473_REG_TEMP_TMIN_BASE_ADDR 0x67 -#define ADT7473_REG_TEMP_TMAX_BASE_ADDR 0x6A - -#define ADT7473_REG_FAN_BASE_ADDR 0x28 -#define ADT7473_REG_FAN_MIN_BASE_ADDR 0x54 - -#define ADT7473_REG_PWM_BASE_ADDR 0x30 -#define ADT7473_REG_PWM_MIN_BASE_ADDR 0x64 -#define ADT7473_REG_PWM_MAX_BASE_ADDR 0x38 -#define ADT7473_REG_PWM_BHVR_BASE_ADDR 0x5C -#define ADT7473_PWM_BHVR_MASK 0xE0 -#define ADT7473_PWM_BHVR_SHIFT 5 - -#define ADT7473_REG_CFG1 0x40 -#define ADT7473_CFG1_START 0x01 -#define ADT7473_CFG1_READY 0x04 -#define ADT7473_REG_CFG2 0x73 -#define ADT7473_REG_CFG3 0x78 -#define ADT7473_REG_CFG4 0x7D -#define ADT7473_CFG4_MAX_DUTY_AT_OVT 0x08 -#define ADT7473_REG_CFG5 0x7C -#define ADT7473_CFG5_TEMP_TWOS 0x01 -#define ADT7473_CFG5_TEMP_OFFSET 0x02 - -#define ADT7473_REG_DEVICE 0x3D -#define ADT7473_VENDOR 0x41 -#define ADT7473_REG_VENDOR 0x3E -#define ADT7473_DEVICE 0x73 -#define ADT7473_REG_REVISION 0x3F -#define ADT7473_REV_68 0x68 -#define ADT7473_REV_69 0x69 - -#define ADT7473_REG_ALARM1 0x41 -#define ADT7473_VCCP_ALARM 0x02 -#define ADT7473_VCC_ALARM 0x04 -#define ADT7473_R1T_ALARM 0x10 -#define ADT7473_LT_ALARM 0x20 -#define ADT7473_R2T_ALARM 0x40 -#define ADT7473_OOL 0x80 -#define ADT7473_REG_ALARM2 0x42 -#define ADT7473_OVT_ALARM 0x02 -#define ADT7473_FAN1_ALARM 0x04 -#define ADT7473_FAN2_ALARM 0x08 -#define ADT7473_FAN3_ALARM 0x10 -#define ADT7473_FAN4_ALARM 0x20 -#define ADT7473_R1T_SHORT 0x40 -#define ADT7473_R2T_SHORT 0x80 - -#define ALARM2(x) ((x) << 8) - -#define ADT7473_VOLT_COUNT 2 -#define ADT7473_REG_VOLT(x) (ADT7473_REG_VOLT_BASE_ADDR + (x)) -#define ADT7473_REG_VOLT_MIN(x) (ADT7473_REG_VOLT_MIN_BASE_ADDR + ((x) * 2)) -#define ADT7473_REG_VOLT_MAX(x) (ADT7473_REG_VOLT_MIN_BASE_ADDR + \ - ((x) * 2) + 1) - -#define ADT7473_TEMP_COUNT 3 -#define ADT7473_REG_TEMP(x) (ADT7473_REG_TEMP_BASE_ADDR + (x)) -#define ADT7473_REG_TEMP_MIN(x) (ADT7473_REG_TEMP_LIMITS_BASE_ADDR + ((x) * 2)) -#define ADT7473_REG_TEMP_MAX(x) (ADT7473_REG_TEMP_LIMITS_BASE_ADDR + \ - ((x) * 2) + 1) -#define ADT7473_REG_TEMP_TMIN(x) (ADT7473_REG_TEMP_TMIN_BASE_ADDR + (x)) -#define ADT7473_REG_TEMP_TMAX(x) (ADT7473_REG_TEMP_TMAX_BASE_ADDR + (x)) - -#define ADT7473_FAN_COUNT 4 -#define ADT7473_REG_FAN(x) (ADT7473_REG_FAN_BASE_ADDR + ((x) * 2)) -#define ADT7473_REG_FAN_MIN(x) (ADT7473_REG_FAN_MIN_BASE_ADDR + ((x) * 2)) - -#define ADT7473_PWM_COUNT 3 -#define ADT7473_REG_PWM(x) (ADT7473_REG_PWM_BASE_ADDR + (x)) -#define ADT7473_REG_PWM_MAX(x) (ADT7473_REG_PWM_MAX_BASE_ADDR + (x)) -#define ADT7473_REG_PWM_MIN(x) (ADT7473_REG_PWM_MIN_BASE_ADDR + (x)) -#define ADT7473_REG_PWM_BHVR(x) (ADT7473_REG_PWM_BHVR_BASE_ADDR + (x)) - -/* How often do we reread sensors values? (In jiffies) */ -#define SENSOR_REFRESH_INTERVAL (2 * HZ) - -/* How often do we reread sensor limit values? (In jiffies) */ -#define LIMIT_REFRESH_INTERVAL (60 * HZ) - -/* datasheet says to divide this number by the fan reading to get fan rpm */ -#define FAN_PERIOD_TO_RPM(x) ((90000 * 60) / (x)) -#define FAN_RPM_TO_PERIOD FAN_PERIOD_TO_RPM -#define FAN_PERIOD_INVALID 65535 -#define FAN_DATA_VALID(x) ((x) && (x) != FAN_PERIOD_INVALID) - -struct adt7473_data { - struct device *hwmon_dev; - struct attribute_group attrs; - struct mutex lock; - char sensors_valid; - char limits_valid; - unsigned long sensors_last_updated; /* In jiffies */ - unsigned long limits_last_updated; /* In jiffies */ - - u8 volt[ADT7473_VOLT_COUNT]; - s8 volt_min[ADT7473_VOLT_COUNT]; - s8 volt_max[ADT7473_VOLT_COUNT]; - - s8 temp[ADT7473_TEMP_COUNT]; - s8 temp_min[ADT7473_TEMP_COUNT]; - s8 temp_max[ADT7473_TEMP_COUNT]; - s8 temp_tmin[ADT7473_TEMP_COUNT]; - /* This is called the !THERM limit in the datasheet */ - s8 temp_tmax[ADT7473_TEMP_COUNT]; - - u16 fan[ADT7473_FAN_COUNT]; - u16 fan_min[ADT7473_FAN_COUNT]; - - u8 pwm[ADT7473_PWM_COUNT]; - u8 pwm_max[ADT7473_PWM_COUNT]; - u8 pwm_min[ADT7473_PWM_COUNT]; - u8 pwm_behavior[ADT7473_PWM_COUNT]; - - u8 temp_twos_complement; - u8 temp_offset; - - u16 alarm; - u8 max_duty_at_overheat; -}; - -static int adt7473_probe(struct i2c_client *client, - const struct i2c_device_id *id); -static int adt7473_detect(struct i2c_client *client, - struct i2c_board_info *info); -static int adt7473_remove(struct i2c_client *client); - -static const struct i2c_device_id adt7473_id[] = { - { "adt7473", 0 }, - { } -}; - -static struct i2c_driver adt7473_driver = { - .class = I2C_CLASS_HWMON, - .driver = { - .name = "adt7473", - }, - .probe = adt7473_probe, - .remove = adt7473_remove, - .id_table = adt7473_id, - .detect = adt7473_detect, - .address_list = normal_i2c, -}; - -/* - * 16-bit registers on the ADT7473 are low-byte first. The data sheet says - * that the low byte must be read before the high byte. - */ -static inline int adt7473_read_word_data(struct i2c_client *client, u8 reg) -{ - u16 foo; - foo = i2c_smbus_read_byte_data(client, reg); - foo |= ((u16)i2c_smbus_read_byte_data(client, reg + 1) << 8); - return foo; -} - -static inline int adt7473_write_word_data(struct i2c_client *client, u8 reg, - u16 value) -{ - return i2c_smbus_write_byte_data(client, reg, value & 0xFF) - && i2c_smbus_write_byte_data(client, reg + 1, value >> 8); -} - -static void adt7473_init_client(struct i2c_client *client) -{ - int reg = i2c_smbus_read_byte_data(client, ADT7473_REG_CFG1); - - if (!(reg & ADT7473_CFG1_READY)) { - dev_err(&client->dev, "Chip not ready.\n"); - } else { - /* start monitoring */ - i2c_smbus_write_byte_data(client, ADT7473_REG_CFG1, - reg | ADT7473_CFG1_START); - } -} - -static struct adt7473_data *adt7473_update_device(struct device *dev) -{ - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - unsigned long local_jiffies = jiffies; - u8 cfg; - int i; - - mutex_lock(&data->lock); - if (time_before(local_jiffies, data->sensors_last_updated + - SENSOR_REFRESH_INTERVAL) - && data->sensors_valid) - goto no_sensor_update; - - for (i = 0; i < ADT7473_VOLT_COUNT; i++) - data->volt[i] = i2c_smbus_read_byte_data(client, - ADT7473_REG_VOLT(i)); - - /* Determine temperature encoding */ - cfg = i2c_smbus_read_byte_data(client, ADT7473_REG_CFG5); - data->temp_twos_complement = (cfg & ADT7473_CFG5_TEMP_TWOS); - - /* - * What does this do? it implies a variable temperature sensor - * offset, but the datasheet doesn't say anything about this bit - * and other parts of the datasheet imply that "offset64" mode - * means that you shift temp values by -64 if the above bit was set. - */ - data->temp_offset = (cfg & ADT7473_CFG5_TEMP_OFFSET); - - for (i = 0; i < ADT7473_TEMP_COUNT; i++) - data->temp[i] = i2c_smbus_read_byte_data(client, - ADT7473_REG_TEMP(i)); - - for (i = 0; i < ADT7473_FAN_COUNT; i++) - data->fan[i] = adt7473_read_word_data(client, - ADT7473_REG_FAN(i)); - - for (i = 0; i < ADT7473_PWM_COUNT; i++) - data->pwm[i] = i2c_smbus_read_byte_data(client, - ADT7473_REG_PWM(i)); - - data->alarm = i2c_smbus_read_byte_data(client, ADT7473_REG_ALARM1); - if (data->alarm & ADT7473_OOL) - data->alarm |= ALARM2(i2c_smbus_read_byte_data(client, - ADT7473_REG_ALARM2)); - - data->sensors_last_updated = local_jiffies; - data->sensors_valid = 1; - -no_sensor_update: - if (time_before(local_jiffies, data->limits_last_updated + - LIMIT_REFRESH_INTERVAL) - && data->limits_valid) - goto out; - - for (i = 0; i < ADT7473_VOLT_COUNT; i++) { - data->volt_min[i] = i2c_smbus_read_byte_data(client, - ADT7473_REG_VOLT_MIN(i)); - data->volt_max[i] = i2c_smbus_read_byte_data(client, - ADT7473_REG_VOLT_MAX(i)); - } - - for (i = 0; i < ADT7473_TEMP_COUNT; i++) { - data->temp_min[i] = i2c_smbus_read_byte_data(client, - ADT7473_REG_TEMP_MIN(i)); - data->temp_max[i] = i2c_smbus_read_byte_data(client, - ADT7473_REG_TEMP_MAX(i)); - data->temp_tmin[i] = i2c_smbus_read_byte_data(client, - ADT7473_REG_TEMP_TMIN(i)); - data->temp_tmax[i] = i2c_smbus_read_byte_data(client, - ADT7473_REG_TEMP_TMAX(i)); - } - - for (i = 0; i < ADT7473_FAN_COUNT; i++) - data->fan_min[i] = adt7473_read_word_data(client, - ADT7473_REG_FAN_MIN(i)); - - for (i = 0; i < ADT7473_PWM_COUNT; i++) { - data->pwm_max[i] = i2c_smbus_read_byte_data(client, - ADT7473_REG_PWM_MAX(i)); - data->pwm_min[i] = i2c_smbus_read_byte_data(client, - ADT7473_REG_PWM_MIN(i)); - data->pwm_behavior[i] = i2c_smbus_read_byte_data(client, - ADT7473_REG_PWM_BHVR(i)); - } - - i = i2c_smbus_read_byte_data(client, ADT7473_REG_CFG4); - data->max_duty_at_overheat = !!(i & ADT7473_CFG4_MAX_DUTY_AT_OVT); - - data->limits_last_updated = local_jiffies; - data->limits_valid = 1; - -out: - mutex_unlock(&data->lock); - return data; -} - -/* - * Conversions - */ - -/* IN are scaled acording to built-in resistors */ -static const int adt7473_scaling[] = { /* .001 Volts */ - 2250, 3300 -}; -#define SCALE(val, from, to) (((val) * (to) + ((from) / 2)) / (from)) - -static int decode_volt(int volt_index, u8 raw) -{ - return SCALE(raw, 192, adt7473_scaling[volt_index]); -} - -static u8 encode_volt(int volt_index, int cooked) -{ - int raw = SCALE(cooked, adt7473_scaling[volt_index], 192); - return SENSORS_LIMIT(raw, 0, 255); -} - -static ssize_t show_volt_min(struct device *dev, - struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - return sprintf(buf, "%d\n", - decode_volt(attr->index, data->volt_min[attr->index])); -} - -static ssize_t set_volt_min(struct device *dev, - struct device_attribute *devattr, - const char *buf, - size_t count) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - long volt; - - if (strict_strtol(buf, 10, &volt)) - return -EINVAL; - - volt = encode_volt(attr->index, volt); - - mutex_lock(&data->lock); - data->volt_min[attr->index] = volt; - i2c_smbus_write_byte_data(client, ADT7473_REG_VOLT_MIN(attr->index), - volt); - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t show_volt_max(struct device *dev, - struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - return sprintf(buf, "%d\n", - decode_volt(attr->index, data->volt_max[attr->index])); -} - -static ssize_t set_volt_max(struct device *dev, - struct device_attribute *devattr, - const char *buf, - size_t count) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - long volt; - - if (strict_strtol(buf, 10, &volt)) - return -EINVAL; - - volt = encode_volt(attr->index, volt); - - mutex_lock(&data->lock); - data->volt_max[attr->index] = volt; - i2c_smbus_write_byte_data(client, ADT7473_REG_VOLT_MAX(attr->index), - volt); - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t show_volt(struct device *dev, struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - - return sprintf(buf, "%d\n", - decode_volt(attr->index, data->volt[attr->index])); -} - -/* - * This chip can report temperature data either as a two's complement - * number in the range -128 to 127, or as an unsigned number that must - * be offset by 64. - */ -static int decode_temp(u8 twos_complement, u8 raw) -{ - return twos_complement ? (s8)raw : raw - 64; -} - -static u8 encode_temp(u8 twos_complement, int cooked) -{ - u8 ret = twos_complement ? cooked & 0xFF : cooked + 64; - return SENSORS_LIMIT(ret, 0, 255); -} - -static ssize_t show_temp_min(struct device *dev, - struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - return sprintf(buf, "%d\n", 1000 * decode_temp( - data->temp_twos_complement, - data->temp_min[attr->index])); -} - -static ssize_t set_temp_min(struct device *dev, - struct device_attribute *devattr, - const char *buf, - size_t count) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - long temp; - - if (strict_strtol(buf, 10, &temp)) - return -EINVAL; - - temp = DIV_ROUND_CLOSEST(temp, 1000); - temp = encode_temp(data->temp_twos_complement, temp); - - mutex_lock(&data->lock); - data->temp_min[attr->index] = temp; - i2c_smbus_write_byte_data(client, ADT7473_REG_TEMP_MIN(attr->index), - temp); - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t show_temp_max(struct device *dev, - struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - return sprintf(buf, "%d\n", 1000 * decode_temp( - data->temp_twos_complement, - data->temp_max[attr->index])); -} - -static ssize_t set_temp_max(struct device *dev, - struct device_attribute *devattr, - const char *buf, - size_t count) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - long temp; - - if (strict_strtol(buf, 10, &temp)) - return -EINVAL; - - temp = DIV_ROUND_CLOSEST(temp, 1000); - temp = encode_temp(data->temp_twos_complement, temp); - - mutex_lock(&data->lock); - data->temp_max[attr->index] = temp; - i2c_smbus_write_byte_data(client, ADT7473_REG_TEMP_MAX(attr->index), - temp); - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t show_temp(struct device *dev, struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - return sprintf(buf, "%d\n", 1000 * decode_temp( - data->temp_twos_complement, - data->temp[attr->index])); -} - -static ssize_t show_fan_min(struct device *dev, - struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - - if (FAN_DATA_VALID(data->fan_min[attr->index])) - return sprintf(buf, "%d\n", - FAN_PERIOD_TO_RPM(data->fan_min[attr->index])); - else - return sprintf(buf, "0\n"); -} - -static ssize_t set_fan_min(struct device *dev, - struct device_attribute *devattr, - const char *buf, size_t count) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - long temp; - - if (strict_strtol(buf, 10, &temp) || !temp) - return -EINVAL; - - temp = FAN_RPM_TO_PERIOD(temp); - temp = SENSORS_LIMIT(temp, 1, 65534); - - mutex_lock(&data->lock); - data->fan_min[attr->index] = temp; - adt7473_write_word_data(client, ADT7473_REG_FAN_MIN(attr->index), temp); - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t show_fan(struct device *dev, struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - - if (FAN_DATA_VALID(data->fan[attr->index])) - return sprintf(buf, "%d\n", - FAN_PERIOD_TO_RPM(data->fan[attr->index])); - else - return sprintf(buf, "0\n"); -} - -static ssize_t show_max_duty_at_crit(struct device *dev, - struct device_attribute *devattr, - char *buf) -{ - struct adt7473_data *data = adt7473_update_device(dev); - return sprintf(buf, "%d\n", data->max_duty_at_overheat); -} - -static ssize_t set_max_duty_at_crit(struct device *dev, - struct device_attribute *devattr, - const char *buf, - size_t count) -{ - u8 reg; - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - long temp; - - if (strict_strtol(buf, 10, &temp)) - return -EINVAL; - - mutex_lock(&data->lock); - data->max_duty_at_overheat = !!temp; - reg = i2c_smbus_read_byte_data(client, ADT7473_REG_CFG4); - if (temp) - reg |= ADT7473_CFG4_MAX_DUTY_AT_OVT; - else - reg &= ~ADT7473_CFG4_MAX_DUTY_AT_OVT; - i2c_smbus_write_byte_data(client, ADT7473_REG_CFG4, reg); - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t show_pwm(struct device *dev, struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - return sprintf(buf, "%d\n", data->pwm[attr->index]); -} - -static ssize_t set_pwm(struct device *dev, struct device_attribute *devattr, - const char *buf, size_t count) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - long temp; - - if (strict_strtol(buf, 10, &temp)) - return -EINVAL; - - temp = SENSORS_LIMIT(temp, 0, 255); - - mutex_lock(&data->lock); - data->pwm[attr->index] = temp; - i2c_smbus_write_byte_data(client, ADT7473_REG_PWM(attr->index), temp); - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t show_pwm_max(struct device *dev, - struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - return sprintf(buf, "%d\n", data->pwm_max[attr->index]); -} - -static ssize_t set_pwm_max(struct device *dev, - struct device_attribute *devattr, - const char *buf, - size_t count) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - long temp; - - if (strict_strtol(buf, 10, &temp)) - return -EINVAL; - - temp = SENSORS_LIMIT(temp, 0, 255); - - mutex_lock(&data->lock); - data->pwm_max[attr->index] = temp; - i2c_smbus_write_byte_data(client, ADT7473_REG_PWM_MAX(attr->index), - temp); - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t show_pwm_min(struct device *dev, - struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - return sprintf(buf, "%d\n", data->pwm_min[attr->index]); -} - -static ssize_t set_pwm_min(struct device *dev, - struct device_attribute *devattr, - const char *buf, - size_t count) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - long temp; - - if (strict_strtol(buf, 10, &temp)) - return -EINVAL; - - temp = SENSORS_LIMIT(temp, 0, 255); - - mutex_lock(&data->lock); - data->pwm_min[attr->index] = temp; - i2c_smbus_write_byte_data(client, ADT7473_REG_PWM_MIN(attr->index), - temp); - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t show_temp_tmax(struct device *dev, - struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - return sprintf(buf, "%d\n", 1000 * decode_temp( - data->temp_twos_complement, - data->temp_tmax[attr->index])); -} - -static ssize_t set_temp_tmax(struct device *dev, - struct device_attribute *devattr, - const char *buf, - size_t count) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - long temp; - - if (strict_strtol(buf, 10, &temp)) - return -EINVAL; - - temp = DIV_ROUND_CLOSEST(temp, 1000); - temp = encode_temp(data->temp_twos_complement, temp); - - mutex_lock(&data->lock); - data->temp_tmax[attr->index] = temp; - i2c_smbus_write_byte_data(client, ADT7473_REG_TEMP_TMAX(attr->index), - temp); - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t show_temp_tmin(struct device *dev, - struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - return sprintf(buf, "%d\n", 1000 * decode_temp( - data->temp_twos_complement, - data->temp_tmin[attr->index])); -} - -static ssize_t set_temp_tmin(struct device *dev, - struct device_attribute *devattr, - const char *buf, - size_t count) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - long temp; - - if (strict_strtol(buf, 10, &temp)) - return -EINVAL; - - temp = DIV_ROUND_CLOSEST(temp, 1000); - temp = encode_temp(data->temp_twos_complement, temp); - - mutex_lock(&data->lock); - data->temp_tmin[attr->index] = temp; - i2c_smbus_write_byte_data(client, ADT7473_REG_TEMP_TMIN(attr->index), - temp); - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t show_pwm_enable(struct device *dev, - struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - - switch (data->pwm_behavior[attr->index] >> ADT7473_PWM_BHVR_SHIFT) { - case 3: - return sprintf(buf, "0\n"); - case 7: - return sprintf(buf, "1\n"); - default: - return sprintf(buf, "2\n"); - } -} - -static ssize_t set_pwm_enable(struct device *dev, - struct device_attribute *devattr, - const char *buf, - size_t count) -{ - u8 reg; - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - long temp; - - if (strict_strtol(buf, 10, &temp)) - return -EINVAL; - - switch (temp) { - case 0: - temp = 3; - break; - case 1: - temp = 7; - break; - case 2: - /* Enter automatic mode with fans off */ - temp = 4; - break; - default: - return -EINVAL; - } - - mutex_lock(&data->lock); - reg = i2c_smbus_read_byte_data(client, - ADT7473_REG_PWM_BHVR(attr->index)); - reg = (temp << ADT7473_PWM_BHVR_SHIFT) | - (reg & ~ADT7473_PWM_BHVR_MASK); - i2c_smbus_write_byte_data(client, ADT7473_REG_PWM_BHVR(attr->index), - reg); - data->pwm_behavior[attr->index] = reg; - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t show_pwm_auto_temp(struct device *dev, - struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - int bhvr = data->pwm_behavior[attr->index] >> ADT7473_PWM_BHVR_SHIFT; - - switch (bhvr) { - case 3: - case 4: - case 7: - return sprintf(buf, "0\n"); - case 0: - case 1: - case 5: - case 6: - return sprintf(buf, "%d\n", bhvr + 1); - case 2: - return sprintf(buf, "4\n"); - } - /* shouldn't ever get here */ - BUG(); -} - -static ssize_t set_pwm_auto_temp(struct device *dev, - struct device_attribute *devattr, - const char *buf, - size_t count) -{ - u8 reg; - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct i2c_client *client = to_i2c_client(dev); - struct adt7473_data *data = i2c_get_clientdata(client); - long temp; - - if (strict_strtol(buf, 10, &temp)) - return -EINVAL; - - switch (temp) { - case 1: - case 2: - case 6: - case 7: - temp--; - break; - case 0: - temp = 4; - break; - default: - return -EINVAL; - } - - mutex_lock(&data->lock); - reg = i2c_smbus_read_byte_data(client, - ADT7473_REG_PWM_BHVR(attr->index)); - reg = (temp << ADT7473_PWM_BHVR_SHIFT) | - (reg & ~ADT7473_PWM_BHVR_MASK); - i2c_smbus_write_byte_data(client, ADT7473_REG_PWM_BHVR(attr->index), - reg); - data->pwm_behavior[attr->index] = reg; - mutex_unlock(&data->lock); - - return count; -} - -static ssize_t show_alarm(struct device *dev, - struct device_attribute *devattr, - char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); - struct adt7473_data *data = adt7473_update_device(dev); - - if (data->alarm & attr->index) - return sprintf(buf, "1\n"); - else - return sprintf(buf, "0\n"); -} - - -static SENSOR_DEVICE_ATTR(in1_max, S_IWUSR | S_IRUGO, show_volt_max, - set_volt_max, 0); -static SENSOR_DEVICE_ATTR(in2_max, S_IWUSR | S_IRUGO, show_volt_max, - set_volt_max, 1); - -static SENSOR_DEVICE_ATTR(in1_min, S_IWUSR | S_IRUGO, show_volt_min, - set_volt_min, 0); -static SENSOR_DEVICE_ATTR(in2_min, S_IWUSR | S_IRUGO, show_volt_min, - set_volt_min, 1); - -static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, show_volt, NULL, 0); -static SENSOR_DEVICE_ATTR(in2_input, S_IRUGO, show_volt, NULL, 1); - -static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, - ADT7473_VCCP_ALARM); -static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, - ADT7473_VCC_ALARM); - -static SENSOR_DEVICE_ATTR(temp1_max, S_IWUSR | S_IRUGO, show_temp_max, - set_temp_max, 0); -static SENSOR_DEVICE_ATTR(temp2_max, S_IWUSR | S_IRUGO, show_temp_max, - set_temp_max, 1); -static SENSOR_DEVICE_ATTR(temp3_max, S_IWUSR | S_IRUGO, show_temp_max, - set_temp_max, 2); - -static SENSOR_DEVICE_ATTR(temp1_min, S_IWUSR | S_IRUGO, show_temp_min, - set_temp_min, 0); -static SENSOR_DEVICE_ATTR(temp2_min, S_IWUSR | S_IRUGO, show_temp_min, - set_temp_min, 1); -static SENSOR_DEVICE_ATTR(temp3_min, S_IWUSR | S_IRUGO, show_temp_min, - set_temp_min, 2); - -static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0); -static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1); -static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2); - -static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, - ADT7473_R1T_ALARM | ALARM2(ADT7473_R1T_SHORT)); -static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, - ADT7473_LT_ALARM); -static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, - ADT7473_R2T_ALARM | ALARM2(ADT7473_R2T_SHORT)); - -static SENSOR_DEVICE_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min, - set_fan_min, 0); -static SENSOR_DEVICE_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min, - set_fan_min, 1); -static SENSOR_DEVICE_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min, - set_fan_min, 2); -static SENSOR_DEVICE_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min, - set_fan_min, 3); - -static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0); -static SENSOR_DEVICE_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1); -static SENSOR_DEVICE_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2); -static SENSOR_DEVICE_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3); - -static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, - ALARM2(ADT7473_FAN1_ALARM)); -static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, - ALARM2(ADT7473_FAN2_ALARM)); -static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, - ALARM2(ADT7473_FAN3_ALARM)); -static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, - ALARM2(ADT7473_FAN4_ALARM)); - -static SENSOR_DEVICE_ATTR(pwm_use_point2_pwm_at_crit, S_IWUSR | S_IRUGO, - show_max_duty_at_crit, set_max_duty_at_crit, 0); - -static SENSOR_DEVICE_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, set_pwm, 0); -static SENSOR_DEVICE_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, set_pwm, 1); -static SENSOR_DEVICE_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, set_pwm, 2); - -static SENSOR_DEVICE_ATTR(pwm1_auto_point1_pwm, S_IWUSR | S_IRUGO, - show_pwm_min, set_pwm_min, 0); -static SENSOR_DEVICE_ATTR(pwm2_auto_point1_pwm, S_IWUSR | S_IRUGO, - show_pwm_min, set_pwm_min, 1); -static SENSOR_DEVICE_ATTR(pwm3_auto_point1_pwm, S_IWUSR | S_IRUGO, - show_pwm_min, set_pwm_min, 2); - -static SENSOR_DEVICE_ATTR(pwm1_auto_point2_pwm, S_IWUSR | S_IRUGO, - show_pwm_max, set_pwm_max, 0); -static SENSOR_DEVICE_ATTR(pwm2_auto_point2_pwm, S_IWUSR | S_IRUGO, - show_pwm_max, set_pwm_max, 1); -static SENSOR_DEVICE_ATTR(pwm3_auto_point2_pwm, S_IWUSR | S_IRUGO, - show_pwm_max, set_pwm_max, 2); - -static SENSOR_DEVICE_ATTR(temp1_auto_point1_temp, S_IWUSR | S_IRUGO, - show_temp_tmin, set_temp_tmin, 0); -static SENSOR_DEVICE_ATTR(temp2_auto_point1_temp, S_IWUSR | S_IRUGO, - show_temp_tmin, set_temp_tmin, 1); -static SENSOR_DEVICE_ATTR(temp3_auto_point1_temp, S_IWUSR | S_IRUGO, - show_temp_tmin, set_temp_tmin, 2); - -static SENSOR_DEVICE_ATTR(temp1_auto_point2_temp, S_IWUSR | S_IRUGO, - show_temp_tmax, set_temp_tmax, 0); -static SENSOR_DEVICE_ATTR(temp2_auto_point2_temp, S_IWUSR | S_IRUGO, - show_temp_tmax, set_temp_tmax, 1); -static SENSOR_DEVICE_ATTR(temp3_auto_point2_temp, S_IWUSR | S_IRUGO, - show_temp_tmax, set_temp_tmax, 2); - -static SENSOR_DEVICE_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable, - set_pwm_enable, 0); -static SENSOR_DEVICE_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable, - set_pwm_enable, 1); -static SENSOR_DEVICE_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable, - set_pwm_enable, 2); - -static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IWUSR | S_IRUGO, - show_pwm_auto_temp, set_pwm_auto_temp, 0); -static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IWUSR | S_IRUGO, - show_pwm_auto_temp, set_pwm_auto_temp, 1); -static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IWUSR | S_IRUGO, - show_pwm_auto_temp, set_pwm_auto_temp, 2); - -static struct attribute *adt7473_attr[] = -{ - &sensor_dev_attr_in1_max.dev_attr.attr, - &sensor_dev_attr_in2_max.dev_attr.attr, - &sensor_dev_attr_in1_min.dev_attr.attr, - &sensor_dev_attr_in2_min.dev_attr.attr, - &sensor_dev_attr_in1_input.dev_attr.attr, - &sensor_dev_attr_in2_input.dev_attr.attr, - &sensor_dev_attr_in1_alarm.dev_attr.attr, - &sensor_dev_attr_in2_alarm.dev_attr.attr, - - &sensor_dev_attr_temp1_max.dev_attr.attr, - &sensor_dev_attr_temp2_max.dev_attr.attr, - &sensor_dev_attr_temp3_max.dev_attr.attr, - &sensor_dev_attr_temp1_min.dev_attr.attr, - &sensor_dev_attr_temp2_min.dev_attr.attr, - &sensor_dev_attr_temp3_min.dev_attr.attr, - &sensor_dev_attr_temp1_input.dev_attr.attr, - &sensor_dev_attr_temp2_input.dev_attr.attr, - &sensor_dev_attr_temp3_input.dev_attr.attr, - &sensor_dev_attr_temp1_alarm.dev_attr.attr, - &sensor_dev_attr_temp2_alarm.dev_attr.attr, - &sensor_dev_attr_temp3_alarm.dev_attr.attr, - &sensor_dev_attr_temp1_auto_point1_temp.dev_attr.attr, - &sensor_dev_attr_temp2_auto_point1_temp.dev_attr.attr, - &sensor_dev_attr_temp3_auto_point1_temp.dev_attr.attr, - &sensor_dev_attr_temp1_auto_point2_temp.dev_attr.attr, - &sensor_dev_attr_temp2_auto_point2_temp.dev_attr.attr, - &sensor_dev_attr_temp3_auto_point2_temp.dev_attr.attr, - - &sensor_dev_attr_fan1_min.dev_attr.attr, - &sensor_dev_attr_fan2_min.dev_attr.attr, - &sensor_dev_attr_fan3_min.dev_attr.attr, - &sensor_dev_attr_fan4_min.dev_attr.attr, - &sensor_dev_attr_fan1_input.dev_attr.attr, - &sensor_dev_attr_fan2_input.dev_attr.attr, - &sensor_dev_attr_fan3_input.dev_attr.attr, - &sensor_dev_attr_fan4_input.dev_attr.attr, - &sensor_dev_attr_fan1_alarm.dev_attr.attr, - &sensor_dev_attr_fan2_alarm.dev_attr.attr, - &sensor_dev_attr_fan3_alarm.dev_attr.attr, - &sensor_dev_attr_fan4_alarm.dev_attr.attr, - - &sensor_dev_attr_pwm_use_point2_pwm_at_crit.dev_attr.attr, - - &sensor_dev_attr_pwm1.dev_attr.attr, - &sensor_dev_attr_pwm2.dev_attr.attr, - &sensor_dev_attr_pwm3.dev_attr.attr, - &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, - &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, - &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, - &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, - &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, - &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, - - &sensor_dev_attr_pwm1_enable.dev_attr.attr, - &sensor_dev_attr_pwm2_enable.dev_attr.attr, - &sensor_dev_attr_pwm3_enable.dev_attr.attr, - &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr, - &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr, - &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr, - - NULL -}; - -/* Return 0 if detection is successful, -ENODEV otherwise */ -static int adt7473_detect(struct i2c_client *client, - struct i2c_board_info *info) -{ - struct i2c_adapter *adapter = client->adapter; - int vendor, device, revision; - - if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) - return -ENODEV; - - vendor = i2c_smbus_read_byte_data(client, ADT7473_REG_VENDOR); - if (vendor != ADT7473_VENDOR) - return -ENODEV; - - device = i2c_smbus_read_byte_data(client, ADT7473_REG_DEVICE); - if (device != ADT7473_DEVICE) - return -ENODEV; - - revision = i2c_smbus_read_byte_data(client, ADT7473_REG_REVISION); - if (revision != ADT7473_REV_68 && revision != ADT7473_REV_69) - return -ENODEV; - - strlcpy(info->type, "adt7473", I2C_NAME_SIZE); - - return 0; -} - -static int adt7473_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct adt7473_data *data; - int err; - - data = kzalloc(sizeof(struct adt7473_data), GFP_KERNEL); - if (!data) { - err = -ENOMEM; - goto exit; - } - - i2c_set_clientdata(client, data); - mutex_init(&data->lock); - - dev_info(&client->dev, "%s chip found\n", client->name); - - /* Initialize the ADT7473 chip */ - adt7473_init_client(client); - - /* Register sysfs hooks */ - data->attrs.attrs = adt7473_attr; - err = sysfs_create_group(&client->dev.kobj, &data->attrs); - if (err) - goto exit_free; - - data->hwmon_dev = hwmon_device_register(&client->dev); - if (IS_ERR(data->hwmon_dev)) { - err = PTR_ERR(data->hwmon_dev); - goto exit_remove; - } - - return 0; - -exit_remove: - sysfs_remove_group(&client->dev.kobj, &data->attrs); -exit_free: - kfree(data); -exit: - return err; -} - -static int adt7473_remove(struct i2c_client *client) -{ - struct adt7473_data *data = i2c_get_clientdata(client); - - hwmon_device_unregister(data->hwmon_dev); - sysfs_remove_group(&client->dev.kobj, &data->attrs); - kfree(data); - return 0; -} - -static int __init adt7473_init(void) -{ - pr_notice("The adt7473 driver is deprecated, please use the adt7475 " - "driver instead\n"); - return i2c_add_driver(&adt7473_driver); -} - -static void __exit adt7473_exit(void) -{ - i2c_del_driver(&adt7473_driver); -} - -MODULE_AUTHOR("Darrick J. Wong "); -MODULE_DESCRIPTION("ADT7473 driver"); -MODULE_LICENSE("GPL"); - -module_init(adt7473_init); -module_exit(adt7473_exit); -- cgit v1.2.3 From 4b79a1aedcb9dd6e3f27b970dcb553aefcd97254 Mon Sep 17 00:00:00 2001 From: David Brown Date: Fri, 5 Mar 2010 09:12:34 +0000 Subject: net: smc91x: Support Qualcomm MSM development boards. Signed-off-by: David Brown Signed-off-by: Daniel Walker Acked-by: Nicolas Pitre Signed-off-by: David S. Miller --- drivers/net/smc91x.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers') diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h index 54799544bda3..a6ee883d1b0e 100644 --- a/drivers/net/smc91x.h +++ b/drivers/net/smc91x.h @@ -330,6 +330,20 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r, #include +#elif defined(CONFIG_ARCH_MSM) + +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_NOWAIT 1 + +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) + +#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH + #else /* -- cgit v1.2.3 From 5fe88eae26dbd24eed73eb0b681e13981fd486b3 Mon Sep 17 00:00:00 2001 From: David Dillow Date: Thu, 4 Mar 2010 04:37:16 +0000 Subject: typhoon: fix incorrect use of smp_wmb() The typhoon driver was incorrectly using smp_wmb() to order memory accesses against IO to the NIC in a few instances. Use wmb() instead, which is required to actually order between memory types. Signed-off-by: David Dillow Signed-off-by: David S. Miller --- drivers/net/typhoon.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/typhoon.c b/drivers/net/typhoon.c index e3ddcb8f29df..1cf012d3e072 100644 --- a/drivers/net/typhoon.c +++ b/drivers/net/typhoon.c @@ -480,7 +480,7 @@ typhoon_hello(struct typhoon *tp) typhoon_inc_cmd_index(&ring->lastWrite, 1); INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP); - smp_wmb(); + wmb(); iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY); spin_unlock(&tp->command_lock); } @@ -1311,13 +1311,15 @@ typhoon_init_interface(struct typhoon *tp) tp->txlo_dma_addr = le32_to_cpu(iface->txLoAddr); tp->card_state = Sleeping; - smp_wmb(); tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM; tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON; spin_lock_init(&tp->command_lock); spin_lock_init(&tp->state_lock); + + /* Force the writes to the shared memory area out before continuing. */ + wmb(); } static void -- cgit v1.2.3 From a80483d3722b603dae8a52495f8d88a7d4b1bf1c Mon Sep 17 00:00:00 2001 From: Jesse Brandeburg Date: Fri, 5 Mar 2010 02:21:44 +0000 Subject: e1000e: fix packet corruption and tx hang during NFSv2 when receiving a particular type of NFS v2 UDP traffic, the hardware could DMA some bad data and then hang, possibly corrupting memory. Disable the NFS parsing in this hardware, verified to fix the bug. Originally reported and reproduced by RedHat's Neil Horman CC: nhorman@tuxdriver.com Signed-off-by: Jesse Brandeburg Signed-off-by: Jeff Kirsher Acked-by: Neil Horman Signed-off-by: David S. Miller --- drivers/net/e1000e/defines.h | 2 ++ drivers/net/e1000e/ich8lan.c | 10 ++++++++++ 2 files changed, 12 insertions(+) (limited to 'drivers') diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index db05ec355749..e301e26d6897 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h @@ -320,6 +320,8 @@ #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ /* Header split receive */ +#define E1000_RFCTL_NFSW_DIS 0x00000040 +#define E1000_RFCTL_NFSR_DIS 0x00000080 #define E1000_RFCTL_ACK_DIS 0x00001000 #define E1000_RFCTL_EXTEN 0x00008000 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index 54d03a0ce3ce..8b5e157e9c87 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c @@ -2740,6 +2740,16 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) reg &= ~(1 << 31); ew32(STATUS, reg); } + + /* + * work-around descriptor data corruption issue during nfs v2 udp + * traffic, just disable the nfs filtering capability + */ + reg = er32(RFCTL); + reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); + ew32(RFCTL, reg); + + return; } /** -- cgit v1.2.3 From 3a22813a5aaf8e8c72be575dabe0ba26f9352f4d Mon Sep 17 00:00:00 2001 From: Breno Leitao Date: Thu, 4 Mar 2010 10:40:44 +0000 Subject: s2io: Fixing debug message Currently s2io is dumping debug messages using the interface name before it was allocated, showing a message like the following: s2io: eth%d: Ring Mem PHY: 0x7ef80000 s2io: s2io_reset: Resetting XFrame card eth%d This patch just fixes it, printing the pci bus information for the card instead of the interface name. Signed-off-by: Breno Leitao Signed-off-by: David S. Miller --- drivers/net/s2io.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c index 43bc66aa8405..df70657260dd 100644 --- a/drivers/net/s2io.c +++ b/drivers/net/s2io.c @@ -923,8 +923,8 @@ static int init_shared_mem(struct s2io_nic *nic) tmp_v_addr = mac_control->stats_mem; mac_control->stats_info = (struct stat_block *)tmp_v_addr; memset(tmp_v_addr, 0, size); - DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n", dev->name, - (unsigned long long)tmp_p_addr); + DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n", + dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr); mac_control->stats_info->sw_stat.mem_allocated += mem_allocated; return SUCCESS; } @@ -3480,7 +3480,7 @@ static void s2io_reset(struct s2io_nic *sp) struct swStat *swstats; DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n", - __func__, sp->dev->name); + __func__, pci_name(sp->pdev)); /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */ pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd)); -- cgit v1.2.3 From bb910a7040e90a0ca3d3e8245d6d5c128a5d1287 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Sat, 27 Feb 2010 21:37:37 +0100 Subject: PCI/PM Runtime: Make runtime PM of PCI devices inactive by default Make the run-time power management of PCI devices be inactive by default by calling pm_runtime_forbid() for each PCI device during its initialization. This setting may be overriden by the user space with the help of the /sys/devices/.../power/control interface. That's necessary to avoid breakage on systems where ACPI-based wake-up is known to fail for some devices. Signed-off-by: Rafael J. Wysocki Signed-off-by: Jesse Barnes --- drivers/pci/pci.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 5b548aee9cbc..6e100ae7f5b5 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1540,8 +1540,10 @@ void pci_pm_init(struct pci_dev *dev) int pm; u16 pmc; + pm_runtime_forbid(&dev->dev); device_enable_async_suspend(&dev->dev); dev->wakeup_prepared = false; + dev->pm_cap = 0; /* find PCI PM capability in list */ -- cgit v1.2.3 From 83c0d5d5388a8d45f7a45e0ec34adc52a78c81ad Mon Sep 17 00:00:00 2001 From: "Moger, Babu" Date: Sat, 6 Mar 2010 02:29:45 +0000 Subject: dm mpath: pass struct pgpath to pg init done This patch removes some unnecessary argument casting. There is no functional change with this patch. Passes 'struct pgpath' through to pg_init_done() instead of the enclosed 'struct dm_path'. Tested the changes with LSI storage.. CC: Chandra Seetharaman Signed-off-by: Babu Moger Acked-by: Kiyoshi Ueda Signed-off-by: Alasdair G Kergon --- drivers/md/dm-mpath.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm-mpath.c b/drivers/md/dm-mpath.c index e81345a1d08f..2c6bf74ad5c1 100644 --- a/drivers/md/dm-mpath.c +++ b/drivers/md/dm-mpath.c @@ -1128,8 +1128,7 @@ static int pg_init_limit_reached(struct multipath *m, struct pgpath *pgpath) static void pg_init_done(void *data, int errors) { - struct dm_path *path = data; - struct pgpath *pgpath = path_to_pgpath(path); + struct pgpath *pgpath = data; struct priority_group *pg = pgpath->pg; struct multipath *m = pg->m; unsigned long flags; @@ -1198,7 +1197,7 @@ static void activate_path(struct work_struct *work) container_of(work, struct pgpath, activate_path); scsi_dh_activate(bdev_get_queue(pgpath->path.dev->bdev), - pg_init_done, &pgpath->path); + pg_init_done, pgpath); } /* -- cgit v1.2.3 From f7b934c8127deebf4eb56fbe4a4ae0da16b6dbcd Mon Sep 17 00:00:00 2001 From: "Moger, Babu" Date: Sat, 6 Mar 2010 02:29:49 +0000 Subject: dm mpath: skip activate_path for failed paths This patch adds two minor fixes while processing device mapper path activation. Skip failed paths while calling activate_path. If the path is already failed then activate_path will fail for sure. We don't have to call in that case. In some case this might cause prolonged retries unnecessarily. Change the misleading message if the path being activated fails with SCSI_DH_NOSYS. Signed-off-by: Babu Moger Signed-off-by: Alasdair G Kergon --- drivers/md/dm-mpath.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm-mpath.c b/drivers/md/dm-mpath.c index 2c6bf74ad5c1..ecada419809c 100644 --- a/drivers/md/dm-mpath.c +++ b/drivers/md/dm-mpath.c @@ -461,6 +461,9 @@ static void process_queued_ios(struct work_struct *work) m->pg_init_count++; m->pg_init_required = 0; list_for_each_entry(tmp, &pgpath->pg->pgpaths, list) { + /* Skip failed paths */ + if (!tmp->is_active) + continue; if (queue_work(kmpath_handlerd, &tmp->activate_path)) m->pg_init_in_progress++; } @@ -1142,8 +1145,8 @@ static void pg_init_done(void *data, int errors) errors = 0; break; } - DMERR("Cannot failover device because scsi_dh_%s was not " - "loaded.", m->hw_handler_name); + DMERR("Could not failover the device: Handler scsi_dh_%s " + "Error %d.", m->hw_handler_name, errors); /* * Fail path for now, so we do not ping pong */ -- cgit v1.2.3 From ecdb2e257abc33ae6798d3ccba87bdafa40ef6b6 Mon Sep 17 00:00:00 2001 From: Kiyoshi Ueda Date: Sat, 6 Mar 2010 02:29:52 +0000 Subject: dm table: remove dm_get from dm_table_get_md Remove the dm_get() in dm_table_get_md() because dm_table_get_md() could be called from presuspend/postsuspend, which are called while mapped_device is in DMF_FREEING state, where dm_get() is not allowed. Justification for that is the lifetime of both objects: As far as the current dm design/implementation, mapped_device is never freed while targets are doing something, because dm core waits for targets to become quiet in dm_put() using presuspend/postsuspend. So targets should be able to touch mapped_device without holding reference count of the mapped_device, and we should allow targets to touch mapped_device even if it is in DMF_FREEING state. Backgrounds: I'm trying to remove the multipath internal queue, since dm core now has a generic queue for request-based dm. In the patch-set, the multipath target wants to request dm core to start/stop queue. One of such start/stop requests can happen during postsuspend() while the target waits for pg-init to complete, because the target stops queue when starting pg-init and tries to restart it when completing pg-init. Since queue belongs to mapped_device, it involves calling dm_table_get_md() and dm_put(). On the other hand, postsuspend() is called in dm_put() for mapped_device which is in DMF_FREEING state, and that triggers BUG_ON(DMF_FREEING) in the 2nd dm_put(). I had tried to solve this problem by changing only multipath not to touch mapped_device which is in DMF_FREEING state, but I couldn't and I came up with a question why we need dm_get() in dm_table_get_md(). Signed-off-by: Kiyoshi Ueda Signed-off-by: Jun'ichi Nomura Signed-off-by: Alasdair G Kergon --- drivers/md/dm-table.c | 2 -- drivers/md/dm-uevent.c | 7 ++----- drivers/md/dm.c | 14 ++------------ 3 files changed, 4 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm-table.c b/drivers/md/dm-table.c index 4b22feb01a0c..7d70cca585ac 100644 --- a/drivers/md/dm-table.c +++ b/drivers/md/dm-table.c @@ -1231,8 +1231,6 @@ void dm_table_unplug_all(struct dm_table *t) struct mapped_device *dm_table_get_md(struct dm_table *t) { - dm_get(t->md); - return t->md; } diff --git a/drivers/md/dm-uevent.c b/drivers/md/dm-uevent.c index c7c555a8c7b2..6b1e3b61b25e 100644 --- a/drivers/md/dm-uevent.c +++ b/drivers/md/dm-uevent.c @@ -187,7 +187,7 @@ void dm_path_uevent(enum dm_uevent_type event_type, struct dm_target *ti, if (event_type >= ARRAY_SIZE(_dm_uevent_type_names)) { DMERR("%s: Invalid event_type %d", __func__, event_type); - goto out; + return; } event = dm_build_path_uevent(md, ti, @@ -195,12 +195,9 @@ void dm_path_uevent(enum dm_uevent_type event_type, struct dm_target *ti, _dm_uevent_type_names[event_type].name, path, nr_valid_paths); if (IS_ERR(event)) - goto out; + return; dm_uevent_add(md, &event->elist); - -out: - dm_put(md); } EXPORT_SYMBOL_GPL(dm_path_uevent); diff --git a/drivers/md/dm.c b/drivers/md/dm.c index aa4e2aa86d49..21222f5193fb 100644 --- a/drivers/md/dm.c +++ b/drivers/md/dm.c @@ -2699,23 +2699,13 @@ int dm_suspended_md(struct mapped_device *md) int dm_suspended(struct dm_target *ti) { - struct mapped_device *md = dm_table_get_md(ti->table); - int r = dm_suspended_md(md); - - dm_put(md); - - return r; + return dm_suspended_md(dm_table_get_md(ti->table)); } EXPORT_SYMBOL_GPL(dm_suspended); int dm_noflush_suspending(struct dm_target *ti) { - struct mapped_device *md = dm_table_get_md(ti->table); - int r = __noflush_suspending(md); - - dm_put(md); - - return r; + return __noflush_suspending(dm_table_get_md(ti->table)); } EXPORT_SYMBOL_GPL(dm_noflush_suspending); -- cgit v1.2.3 From fce323dd68e13354071538c765b062859e6f8286 Mon Sep 17 00:00:00 2001 From: Kiyoshi Ueda Date: Sat, 6 Mar 2010 02:29:59 +0000 Subject: dm mpath: avoid storing private suspended state 'suspended' flag in struct multipath was introduced to check whether the multipath target is in suspended state, but the same check is done through dm_suspended() now, so remove the flag and related code. Signed-off-by: Kiyoshi Ueda Signed-off-by: Jun'ichi Nomura Cc: Mike Anderson Signed-off-by: Alasdair G Kergon --- drivers/md/dm-mpath.c | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm-mpath.c b/drivers/md/dm-mpath.c index ecada419809c..8fa0c955eeb5 100644 --- a/drivers/md/dm-mpath.c +++ b/drivers/md/dm-mpath.c @@ -95,8 +95,6 @@ struct multipath { mempool_t *mpio_pool; struct mutex work_mutex; - - unsigned suspended; /* Don't create new I/O internally when set. */ }; /* @@ -1278,7 +1276,6 @@ static void multipath_postsuspend(struct dm_target *ti) struct multipath *m = ti->private; mutex_lock(&m->work_mutex); - m->suspended = 1; flush_multipath_work(); mutex_unlock(&m->work_mutex); } @@ -1291,10 +1288,6 @@ static void multipath_resume(struct dm_target *ti) struct multipath *m = (struct multipath *) ti->private; unsigned long flags; - mutex_lock(&m->work_mutex); - m->suspended = 0; - mutex_unlock(&m->work_mutex); - spin_lock_irqsave(&m->lock, flags); m->queue_if_no_path = m->saved_queue_if_no_path; spin_unlock_irqrestore(&m->lock, flags); @@ -1430,11 +1423,6 @@ static int multipath_message(struct dm_target *ti, unsigned argc, char **argv) mutex_lock(&m->work_mutex); - if (m->suspended) { - r = -EBUSY; - goto out; - } - if (dm_suspended(ti)) { r = -EBUSY; goto out; -- cgit v1.2.3 From d0259bf0eefc503d3c9c9ccda35033c3dd3aac30 Mon Sep 17 00:00:00 2001 From: Kiyoshi Ueda Date: Sat, 6 Mar 2010 02:30:02 +0000 Subject: dm mpath: hold io until all pg_inits completed m->queue_io is set to block processing I/Os, and it needs to be kept while pg-init, which issues multiple path activations, is in progress. But m->queue is cleared when a path activation completes without error in pg_init_done(), even while other path activations are in progress. That may cause undesired -EIO on paths which are not complete activation. This patch fixes that by not clearing m->queue_io until all path activations complete. (Before the hardware handlers were moved into the SCSI layer, pg_init only used one path.) Signed-off-by: Kiyoshi Ueda Signed-off-by: Jun'ichi Nomura Signed-off-by: Alasdair G Kergon --- drivers/md/dm-mpath.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm-mpath.c b/drivers/md/dm-mpath.c index 8fa0c955eeb5..ae187e5d7d58 100644 --- a/drivers/md/dm-mpath.c +++ b/drivers/md/dm-mpath.c @@ -1181,14 +1181,19 @@ static void pg_init_done(void *data, int errors) m->current_pgpath = NULL; m->current_pg = NULL; } - } else if (!m->pg_init_required) { - m->queue_io = 0; + } else if (!m->pg_init_required) pg->bypassed = 0; - } - m->pg_init_in_progress--; - if (!m->pg_init_in_progress) - queue_work(kmultipathd, &m->process_queued_ios); + if (--m->pg_init_in_progress) + /* Activations of other paths are still on going */ + goto out; + + if (!m->pg_init_required) + m->queue_io = 0; + + queue_work(kmultipathd, &m->process_queued_ios); + +out: spin_unlock_irqrestore(&m->lock, flags); } -- cgit v1.2.3 From 2bded7bd7e8b12a913b0b58167a48220560e1514 Mon Sep 17 00:00:00 2001 From: Kiyoshi Ueda Date: Sat, 6 Mar 2010 02:32:13 +0000 Subject: dm mpath: wait for pg_init completion when suspending When suspending the device we must wait for all I/O to complete, but pg-init may be still in progress even after flushing the workqueue for kmpath_handlerd in multipath_postsuspend. This patch waits for pg-init completion correctly in multipath_postsuspend(). Signed-off-by: Kiyoshi Ueda Signed-off-by: Jun'ichi Nomura Signed-off-by: Alasdair G Kergon --- drivers/md/dm-mpath.c | 38 +++++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm-mpath.c b/drivers/md/dm-mpath.c index ae187e5d7d58..030bc2a053ec 100644 --- a/drivers/md/dm-mpath.c +++ b/drivers/md/dm-mpath.c @@ -69,6 +69,7 @@ struct multipath { struct list_head priority_groups; unsigned pg_init_required; /* pg_init needs calling? */ unsigned pg_init_in_progress; /* Only one pg_init allowed at once */ + wait_queue_head_t pg_init_wait; /* Wait for pg_init completion */ unsigned nr_valid_paths; /* Total number of usable paths */ struct pgpath *current_pgpath; @@ -200,6 +201,7 @@ static struct multipath *alloc_multipath(struct dm_target *ti) m->queue_io = 1; INIT_WORK(&m->process_queued_ios, process_queued_ios); INIT_WORK(&m->trigger_event, trigger_event); + init_waitqueue_head(&m->pg_init_wait); mutex_init(&m->work_mutex); m->mpio_pool = mempool_create_slab_pool(MIN_IOS, _mpio_cache); if (!m->mpio_pool) { @@ -891,9 +893,34 @@ static int multipath_ctr(struct dm_target *ti, unsigned int argc, return r; } -static void flush_multipath_work(void) +static void multipath_wait_for_pg_init_completion(struct multipath *m) +{ + DECLARE_WAITQUEUE(wait, current); + unsigned long flags; + + add_wait_queue(&m->pg_init_wait, &wait); + + while (1) { + set_current_state(TASK_UNINTERRUPTIBLE); + + spin_lock_irqsave(&m->lock, flags); + if (!m->pg_init_in_progress) { + spin_unlock_irqrestore(&m->lock, flags); + break; + } + spin_unlock_irqrestore(&m->lock, flags); + + io_schedule(); + } + set_current_state(TASK_RUNNING); + + remove_wait_queue(&m->pg_init_wait, &wait); +} + +static void flush_multipath_work(struct multipath *m) { flush_workqueue(kmpath_handlerd); + multipath_wait_for_pg_init_completion(m); flush_workqueue(kmultipathd); flush_scheduled_work(); } @@ -902,7 +929,7 @@ static void multipath_dtr(struct dm_target *ti) { struct multipath *m = ti->private; - flush_multipath_work(); + flush_multipath_work(m); free_multipath(m); } @@ -1193,6 +1220,11 @@ static void pg_init_done(void *data, int errors) queue_work(kmultipathd, &m->process_queued_ios); + /* + * Wake up any thread waiting to suspend. + */ + wake_up(&m->pg_init_wait); + out: spin_unlock_irqrestore(&m->lock, flags); } @@ -1281,7 +1313,7 @@ static void multipath_postsuspend(struct dm_target *ti) struct multipath *m = ti->private; mutex_lock(&m->work_mutex); - flush_multipath_work(); + flush_multipath_work(m); mutex_unlock(&m->work_mutex); } -- cgit v1.2.3 From fb61264297ca42a2a132f0433f75ccf7fd304ac6 Mon Sep 17 00:00:00 2001 From: Kiyoshi Ueda Date: Sat, 6 Mar 2010 02:32:18 +0000 Subject: dm mpath: refactor pg_init This patch pulls the pg_init path activation code out of process_queued_ios() into a new function. No functional change. Signed-off-by: Kiyoshi Ueda Signed-off-by: Jun'ichi Nomura Signed-off-by: Alasdair G Kergon --- drivers/md/dm-mpath.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm-mpath.c b/drivers/md/dm-mpath.c index 030bc2a053ec..c1335487cc72 100644 --- a/drivers/md/dm-mpath.c +++ b/drivers/md/dm-mpath.c @@ -235,6 +235,21 @@ static void free_multipath(struct multipath *m) * Path selection *-----------------------------------------------*/ +static void __pg_init_all_paths(struct multipath *m) +{ + struct pgpath *pgpath; + + m->pg_init_count++; + m->pg_init_required = 0; + list_for_each_entry(pgpath, &m->current_pg->pgpaths, list) { + /* Skip failed paths */ + if (!pgpath->is_active) + continue; + if (queue_work(kmpath_handlerd, &pgpath->activate_path)) + m->pg_init_in_progress++; + } +} + static void __switch_pg(struct multipath *m, struct pgpath *pgpath) { m->current_pg = pgpath->pg; @@ -439,7 +454,7 @@ static void process_queued_ios(struct work_struct *work) { struct multipath *m = container_of(work, struct multipath, process_queued_ios); - struct pgpath *pgpath = NULL, *tmp; + struct pgpath *pgpath = NULL; unsigned must_queue = 1; unsigned long flags; @@ -457,17 +472,9 @@ static void process_queued_ios(struct work_struct *work) (!pgpath && !m->queue_if_no_path)) must_queue = 0; - if (m->pg_init_required && !m->pg_init_in_progress && pgpath) { - m->pg_init_count++; - m->pg_init_required = 0; - list_for_each_entry(tmp, &pgpath->pg->pgpaths, list) { - /* Skip failed paths */ - if (!tmp->is_active) - continue; - if (queue_work(kmpath_handlerd, &tmp->activate_path)) - m->pg_init_in_progress++; - } - } + if (m->pg_init_required && !m->pg_init_in_progress && pgpath) + __pg_init_all_paths(m); + out: spin_unlock_irqrestore(&m->lock, flags); if (!must_queue) -- cgit v1.2.3 From ede5ea0b8b815560dc54c712536fdf0b456b6ad0 Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Sat, 6 Mar 2010 02:32:22 +0000 Subject: dm raid1: always return error if all legs fail If all mirror legs fail, always return an error instead of holding the bio, even if the handle_errors option was set. At present it is the responsibility of the driver underneath us to deal with retries, multipath etc. The patch adds the bio to the failures list instead of holding it directly. do_failures tests first if all legs failed and, if so, returns the bio with -EIO. If any leg is still alive and handle_errors is set, do_failures calls hold_bio. Reviewed-by: Takahiro Yasui Signed-off-by: Mikulas Patocka Signed-off-by: Alasdair G Kergon --- drivers/md/dm-raid1.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm-raid1.c b/drivers/md/dm-raid1.c index 6c1046df81f6..de26fde4098f 100644 --- a/drivers/md/dm-raid1.c +++ b/drivers/md/dm-raid1.c @@ -737,9 +737,12 @@ static void do_writes(struct mirror_set *ms, struct bio_list *writes) dm_rh_delay(ms->rh, bio); while ((bio = bio_list_pop(&nosync))) { - if (unlikely(ms->leg_failure) && errors_handled(ms)) - hold_bio(ms, bio); - else { + if (unlikely(ms->leg_failure) && errors_handled(ms)) { + spin_lock_irq(&ms->lock); + bio_list_add(&ms->failures, bio); + spin_unlock_irq(&ms->lock); + wakeup_mirrord(ms); + } else { map_bio(get_default_mirror(ms), bio); generic_make_request(bio); } -- cgit v1.2.3 From 0f3649a9e305ea22eb196a84a2d7520afcaa6060 Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Sat, 6 Mar 2010 02:32:24 +0000 Subject: dm ioctl: only issue uevent on resume if state changed Only issue a uevent on a resume if the state of the device changed, i.e. if it was suspended and/or its table was replaced. Signed-off-by: Dave Wysochanski Signed-off-by: Mike Snitzer Cc: stable@kernel.org Signed-off-by: Alasdair G Kergon --- drivers/md/dm-ioctl.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm-ioctl.c b/drivers/md/dm-ioctl.c index 1d669322b27c..e3cf5686d0aa 100644 --- a/drivers/md/dm-ioctl.c +++ b/drivers/md/dm-ioctl.c @@ -897,16 +897,17 @@ static int do_resume(struct dm_ioctl *param) set_disk_ro(dm_disk(md), 1); } - if (dm_suspended_md(md)) + if (dm_suspended_md(md)) { r = dm_resume(md); + if (!r) + dm_kobject_uevent(md, KOBJ_CHANGE, param->event_nr); + } if (old_map) dm_table_destroy(old_map); - if (!r) { - dm_kobject_uevent(md, KOBJ_CHANGE, param->event_nr); + if (!r) r = __dev_status(md, param); - } dm_put(md); return r; -- cgit v1.2.3 From 8215d6ec5fee1e76545decea2cd73717efb5cb42 Mon Sep 17 00:00:00 2001 From: Nikanth Karthikesan Date: Sat, 6 Mar 2010 02:32:27 +0000 Subject: dm table: remove unused dm_get_device range parameters Remove unused parameters(start and len) of dm_get_device() and fix the callers. Signed-off-by: Nikanth Karthikesan Signed-off-by: Alasdair G Kergon --- drivers/md/dm-crypt.c | 3 +-- drivers/md/dm-delay.c | 8 ++++---- drivers/md/dm-linear.c | 3 +-- drivers/md/dm-log.c | 3 +-- drivers/md/dm-mpath.c | 7 +++---- drivers/md/dm-raid1.c | 3 +-- drivers/md/dm-snap.c | 8 +++----- drivers/md/dm-stripe.c | 3 +-- drivers/md/dm-table.c | 10 ++++------ include/linux/device-mapper.h | 5 ++--- 10 files changed, 21 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c index a93637223c8d..3bdbb6115702 100644 --- a/drivers/md/dm-crypt.c +++ b/drivers/md/dm-crypt.c @@ -1160,8 +1160,7 @@ static int crypt_ctr(struct dm_target *ti, unsigned int argc, char **argv) } cc->start = tmpll; - if (dm_get_device(ti, argv[3], cc->start, ti->len, - dm_table_get_mode(ti->table), &cc->dev)) { + if (dm_get_device(ti, argv[3], dm_table_get_mode(ti->table), &cc->dev)) { ti->error = "Device lookup failed"; goto bad_device; } diff --git a/drivers/md/dm-delay.c b/drivers/md/dm-delay.c index ebe7381f47c8..852052880d7a 100644 --- a/drivers/md/dm-delay.c +++ b/drivers/md/dm-delay.c @@ -156,8 +156,8 @@ static int delay_ctr(struct dm_target *ti, unsigned int argc, char **argv) goto bad; } - if (dm_get_device(ti, argv[0], dc->start_read, ti->len, - dm_table_get_mode(ti->table), &dc->dev_read)) { + if (dm_get_device(ti, argv[0], dm_table_get_mode(ti->table), + &dc->dev_read)) { ti->error = "Device lookup failed"; goto bad; } @@ -177,8 +177,8 @@ static int delay_ctr(struct dm_target *ti, unsigned int argc, char **argv) goto bad_dev_read; } - if (dm_get_device(ti, argv[3], dc->start_write, ti->len, - dm_table_get_mode(ti->table), &dc->dev_write)) { + if (dm_get_device(ti, argv[3], dm_table_get_mode(ti->table), + &dc->dev_write)) { ti->error = "Write device lookup failed"; goto bad_dev_read; } diff --git a/drivers/md/dm-linear.c b/drivers/md/dm-linear.c index 82f7d6e6b1ea..9200dbf2391a 100644 --- a/drivers/md/dm-linear.c +++ b/drivers/md/dm-linear.c @@ -47,8 +47,7 @@ static int linear_ctr(struct dm_target *ti, unsigned int argc, char **argv) } lc->start = tmp; - if (dm_get_device(ti, argv[0], lc->start, ti->len, - dm_table_get_mode(ti->table), &lc->dev)) { + if (dm_get_device(ti, argv[0], dm_table_get_mode(ti->table), &lc->dev)) { ti->error = "dm-linear: Device lookup failed"; goto bad; } diff --git a/drivers/md/dm-log.c b/drivers/md/dm-log.c index 7035582786fb..5a08be0222db 100644 --- a/drivers/md/dm-log.c +++ b/drivers/md/dm-log.c @@ -543,8 +543,7 @@ static int disk_ctr(struct dm_dirty_log *log, struct dm_target *ti, return -EINVAL; } - r = dm_get_device(ti, argv[0], 0, 0 /* FIXME */, - FMODE_READ | FMODE_WRITE, &dev); + r = dm_get_device(ti, argv[0], FMODE_READ | FMODE_WRITE, &dev); if (r) return r; diff --git a/drivers/md/dm-mpath.c b/drivers/md/dm-mpath.c index c1335487cc72..826bce7343b3 100644 --- a/drivers/md/dm-mpath.c +++ b/drivers/md/dm-mpath.c @@ -607,8 +607,8 @@ static struct pgpath *parse_path(struct arg_set *as, struct path_selector *ps, if (!p) return ERR_PTR(-ENOMEM); - r = dm_get_device(ti, shift(as), ti->begin, ti->len, - dm_table_get_mode(ti->table), &p->path.dev); + r = dm_get_device(ti, shift(as), dm_table_get_mode(ti->table), + &p->path.dev); if (r) { ti->error = "error getting device"; goto bad; @@ -1505,8 +1505,7 @@ static int multipath_message(struct dm_target *ti, unsigned argc, char **argv) goto out; } - r = dm_get_device(ti, argv[1], ti->begin, ti->len, - dm_table_get_mode(ti->table), &dev); + r = dm_get_device(ti, argv[1], dm_table_get_mode(ti->table), &dev); if (r) { DMWARN("message: error getting device %s", argv[1]); diff --git a/drivers/md/dm-raid1.c b/drivers/md/dm-raid1.c index de26fde4098f..6d66ddf39071 100644 --- a/drivers/md/dm-raid1.c +++ b/drivers/md/dm-raid1.c @@ -920,8 +920,7 @@ static int get_mirror(struct mirror_set *ms, struct dm_target *ti, return -EINVAL; } - if (dm_get_device(ti, argv[0], offset, ti->len, - dm_table_get_mode(ti->table), + if (dm_get_device(ti, argv[0], dm_table_get_mode(ti->table), &ms->mirror[mirror].dev)) { ti->error = "Device lookup failure"; return -ENXIO; diff --git a/drivers/md/dm-snap.c b/drivers/md/dm-snap.c index ee8eb283650d..0789c22ff0d4 100644 --- a/drivers/md/dm-snap.c +++ b/drivers/md/dm-snap.c @@ -1081,8 +1081,7 @@ static int snapshot_ctr(struct dm_target *ti, unsigned int argc, char **argv) argv++; argc--; - r = dm_get_device(ti, cow_path, 0, 0, - FMODE_READ | FMODE_WRITE, &s->cow); + r = dm_get_device(ti, cow_path, FMODE_READ | FMODE_WRITE, &s->cow); if (r) { ti->error = "Cannot get COW device"; goto bad_cow; @@ -1098,7 +1097,7 @@ static int snapshot_ctr(struct dm_target *ti, unsigned int argc, char **argv) argv += args_used; argc -= args_used; - r = dm_get_device(ti, origin_path, 0, ti->len, origin_mode, &s->origin); + r = dm_get_device(ti, origin_path, origin_mode, &s->origin); if (r) { ti->error = "Cannot get origin device"; goto bad_origin; @@ -2100,8 +2099,7 @@ static int origin_ctr(struct dm_target *ti, unsigned int argc, char **argv) return -EINVAL; } - r = dm_get_device(ti, argv[0], 0, ti->len, - dm_table_get_mode(ti->table), &dev); + r = dm_get_device(ti, argv[0], dm_table_get_mode(ti->table), &dev); if (r) { ti->error = "Cannot get target device"; return r; diff --git a/drivers/md/dm-stripe.c b/drivers/md/dm-stripe.c index bd58703ee8f6..e610725db766 100644 --- a/drivers/md/dm-stripe.c +++ b/drivers/md/dm-stripe.c @@ -80,8 +80,7 @@ static int get_stripe(struct dm_target *ti, struct stripe_c *sc, if (sscanf(argv[1], "%llu", &start) != 1) return -EINVAL; - if (dm_get_device(ti, argv[0], start, sc->stripe_width, - dm_table_get_mode(ti->table), + if (dm_get_device(ti, argv[0], dm_table_get_mode(ti->table), &sc->stripe[stripe].dev)) return -ENXIO; diff --git a/drivers/md/dm-table.c b/drivers/md/dm-table.c index 7d70cca585ac..9924ea23032d 100644 --- a/drivers/md/dm-table.c +++ b/drivers/md/dm-table.c @@ -429,8 +429,7 @@ static int upgrade_mode(struct dm_dev_internal *dd, fmode_t new_mode, * it's already present. */ static int __table_get_device(struct dm_table *t, struct dm_target *ti, - const char *path, sector_t start, sector_t len, - fmode_t mode, struct dm_dev **result) + const char *path, fmode_t mode, struct dm_dev **result) { int r; dev_t uninitialized_var(dev); @@ -527,11 +526,10 @@ int dm_set_device_limits(struct dm_target *ti, struct dm_dev *dev, } EXPORT_SYMBOL_GPL(dm_set_device_limits); -int dm_get_device(struct dm_target *ti, const char *path, sector_t start, - sector_t len, fmode_t mode, struct dm_dev **result) +int dm_get_device(struct dm_target *ti, const char *path, fmode_t mode, + struct dm_dev **result) { - return __table_get_device(ti->table, ti, path, - start, len, mode, result); + return __table_get_device(ti->table, ti, path, mode, result); } diff --git a/include/linux/device-mapper.h b/include/linux/device-mapper.h index d4c9c0b88adc..1381cd97b4ed 100644 --- a/include/linux/device-mapper.h +++ b/include/linux/device-mapper.h @@ -118,10 +118,9 @@ struct dm_dev { /* * Constructors should call these functions to ensure destination devices * are opened/closed correctly. - * FIXME: too many arguments. */ -int dm_get_device(struct dm_target *ti, const char *path, sector_t start, - sector_t len, fmode_t mode, struct dm_dev **result); +int dm_get_device(struct dm_target *ti, const char *path, fmode_t mode, + struct dm_dev **result); void dm_put_device(struct dm_target *ti, struct dm_dev *d); /* -- cgit v1.2.3 From a97f925a32aad2a37971d7bfb657006acf04e42d Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Sat, 6 Mar 2010 02:32:29 +0000 Subject: dm: free dm_io before bio_endio not after Free the dm_io structure before calling bio_endio() instead of after it, to ensure that the io_pool containing it is not referenced after it is freed. This partially fixes a problem described here https://www.redhat.com/archives/dm-devel/2010-February/msg00109.html thread 1: bio_endio(bio, io_error); /* scheduling happens */ thread 2: close the device remove the device thread 1: free_io(md, io); Thread 2, when removing the device, sees non-empty md->io_pool (because the io hasn't been freed by thread 1 yet) and may crash with BUG in mempool_free. Thread 1 may also crash, when freeing into a nonexisting mempool. To fix this we must make sure that bio_endio() is the last call and the md structure is not accessed afterwards. There is another bio_endio in process_barrier, but it is called from the thread and the thread is destroyed prior to freeing the mempools, so this call is not affected by the bug. A similar bug exists with module unloads - the module may be unloaded immediately after bio_endio - but that is more difficult to fix. Signed-off-by: Mikulas Patocka Cc: stable@kernel.org Signed-off-by: Alasdair G Kergon --- drivers/md/dm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm.c b/drivers/md/dm.c index 21222f5193fb..7199846364e9 100644 --- a/drivers/md/dm.c +++ b/drivers/md/dm.c @@ -635,8 +635,10 @@ static void dec_pending(struct dm_io *io, int error) if (!md->barrier_error && io_error != -EOPNOTSUPP) md->barrier_error = io_error; end_io_acct(io); + free_io(md, io); } else { end_io_acct(io); + free_io(md, io); if (io_error != DM_ENDIO_REQUEUE) { trace_block_bio_complete(md->queue, bio); @@ -644,8 +646,6 @@ static void dec_pending(struct dm_io *io, int error) bio_endio(bio, io_error); } } - - free_io(md, io); } } -- cgit v1.2.3 From 3abf85b5b5851b5f28d3d8a920ebb844edd08352 Mon Sep 17 00:00:00 2001 From: Peter Rajnoha Date: Sat, 6 Mar 2010 02:32:31 +0000 Subject: dm ioctl: introduce flag indicating uevent was generated Set a new DM_UEVENT_GENERATED_FLAG when returning from ioctls to indicate that a uevent was actually generated. This tells the userspace caller that it may need to wait for the event to be processed. Signed-off-by: Peter Rajnoha Signed-off-by: Alasdair G Kergon --- drivers/md/dm-ioctl.c | 19 ++++++++++++------- drivers/md/dm.c | 7 ++++--- drivers/md/dm.h | 4 ++-- include/linux/dm-ioctl.h | 9 +++++++-- 4 files changed, 25 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm-ioctl.c b/drivers/md/dm-ioctl.c index e3cf5686d0aa..d7500e1c26f2 100644 --- a/drivers/md/dm-ioctl.c +++ b/drivers/md/dm-ioctl.c @@ -285,7 +285,8 @@ retry: up_write(&_hash_lock); } -static int dm_hash_rename(uint32_t cookie, const char *old, const char *new) +static int dm_hash_rename(uint32_t cookie, uint32_t *flags, const char *old, + const char *new) { char *new_name, *old_name; struct hash_cell *hc; @@ -344,7 +345,8 @@ static int dm_hash_rename(uint32_t cookie, const char *old, const char *new) dm_table_put(table); } - dm_kobject_uevent(hc->md, KOBJ_CHANGE, cookie); + if (!dm_kobject_uevent(hc->md, KOBJ_CHANGE, cookie)) + *flags |= DM_UEVENT_GENERATED_FLAG; dm_put(hc->md); up_write(&_hash_lock); @@ -736,10 +738,10 @@ static int dev_remove(struct dm_ioctl *param, size_t param_size) __hash_remove(hc); up_write(&_hash_lock); - dm_kobject_uevent(md, KOBJ_REMOVE, param->event_nr); + if (!dm_kobject_uevent(md, KOBJ_REMOVE, param->event_nr)) + param->flags |= DM_UEVENT_GENERATED_FLAG; dm_put(md); - param->data_size = 0; return 0; } @@ -773,7 +775,9 @@ static int dev_rename(struct dm_ioctl *param, size_t param_size) return r; param->data_size = 0; - return dm_hash_rename(param->event_nr, param->name, new_name); + + return dm_hash_rename(param->event_nr, ¶m->flags, param->name, + new_name); } static int dev_set_geometry(struct dm_ioctl *param, size_t param_size) @@ -899,8 +903,8 @@ static int do_resume(struct dm_ioctl *param) if (dm_suspended_md(md)) { r = dm_resume(md); - if (!r) - dm_kobject_uevent(md, KOBJ_CHANGE, param->event_nr); + if (!r && !dm_kobject_uevent(md, KOBJ_CHANGE, param->event_nr)) + param->flags |= DM_UEVENT_GENERATED_FLAG; } if (old_map) @@ -1477,6 +1481,7 @@ static int validate_params(uint cmd, struct dm_ioctl *param) { /* Always clear this flag */ param->flags &= ~DM_BUFFER_FULL_FLAG; + param->flags &= ~DM_UEVENT_GENERATED_FLAG; /* Ignores parameters */ if (cmd == DM_REMOVE_ALL_CMD || diff --git a/drivers/md/dm.c b/drivers/md/dm.c index 7199846364e9..d21e1284604f 100644 --- a/drivers/md/dm.c +++ b/drivers/md/dm.c @@ -2618,18 +2618,19 @@ out: /*----------------------------------------------------------------- * Event notification. *---------------------------------------------------------------*/ -void dm_kobject_uevent(struct mapped_device *md, enum kobject_action action, +int dm_kobject_uevent(struct mapped_device *md, enum kobject_action action, unsigned cookie) { char udev_cookie[DM_COOKIE_LENGTH]; char *envp[] = { udev_cookie, NULL }; if (!cookie) - kobject_uevent(&disk_to_dev(md->disk)->kobj, action); + return kobject_uevent(&disk_to_dev(md->disk)->kobj, action); else { snprintf(udev_cookie, DM_COOKIE_LENGTH, "%s=%u", DM_COOKIE_ENV_VAR_NAME, cookie); - kobject_uevent_env(&disk_to_dev(md->disk)->kobj, action, envp); + return kobject_uevent_env(&disk_to_dev(md->disk)->kobj, + action, envp); } } diff --git a/drivers/md/dm.h b/drivers/md/dm.h index 8dadaa5bc396..bad1724d4869 100644 --- a/drivers/md/dm.h +++ b/drivers/md/dm.h @@ -125,8 +125,8 @@ void dm_stripe_exit(void); int dm_open_count(struct mapped_device *md); int dm_lock_for_deletion(struct mapped_device *md); -void dm_kobject_uevent(struct mapped_device *md, enum kobject_action action, - unsigned cookie); +int dm_kobject_uevent(struct mapped_device *md, enum kobject_action action, + unsigned cookie); int dm_io_init(void); void dm_io_exit(void); diff --git a/include/linux/dm-ioctl.h b/include/linux/dm-ioctl.h index aa95508d2f95..2c445e113790 100644 --- a/include/linux/dm-ioctl.h +++ b/include/linux/dm-ioctl.h @@ -266,9 +266,9 @@ enum { #define DM_DEV_SET_GEOMETRY _IOWR(DM_IOCTL, DM_DEV_SET_GEOMETRY_CMD, struct dm_ioctl) #define DM_VERSION_MAJOR 4 -#define DM_VERSION_MINOR 16 +#define DM_VERSION_MINOR 17 #define DM_VERSION_PATCHLEVEL 0 -#define DM_VERSION_EXTRA "-ioctl (2009-11-05)" +#define DM_VERSION_EXTRA "-ioctl (2010-03-05)" /* Status bits */ #define DM_READONLY_FLAG (1 << 0) /* In/Out */ @@ -316,4 +316,9 @@ enum { */ #define DM_QUERY_INACTIVE_TABLE_FLAG (1 << 12) /* In */ +/* + * If set, a uevent was generated for which the caller may need to wait. + */ +#define DM_UEVENT_GENERATED_FLAG (1 << 13) /* Out */ + #endif /* _LINUX_DM_IOCTL_H */ -- cgit v1.2.3 From 924e600d417ead9ef67043988055ba236f114718 Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Sat, 6 Mar 2010 02:32:33 +0000 Subject: dm: eliminate some holes data structures Eliminate a 4-byte hole in 'struct dm_io_memory' by moving 'offset' above the 'ptr' to which it applies (size reduced from 24 to 16 bytes). And by association, 1-4 byte hole is eliminated in 'struct dm_io_request' (size reduced from 56 to 48 bytes). Eliminate all 6 4-byte holes and 1 cache-line in 'struct dm_snapshot' (size reduced from 392 to 368 bytes). Signed-off-by: Mike Snitzer Signed-off-by: Alasdair G Kergon --- drivers/md/dm-snap.c | 26 +++++++++++++------------- include/linux/dm-io.h | 4 ++-- 2 files changed, 15 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm-snap.c b/drivers/md/dm-snap.c index 0789c22ff0d4..54853773510c 100644 --- a/drivers/md/dm-snap.c +++ b/drivers/md/dm-snap.c @@ -83,10 +83,10 @@ struct dm_snapshot { /* Whether or not owning mapped_device is suspended */ int suspended; - mempool_t *pending_pool; - atomic_t pending_exceptions_count; + mempool_t *pending_pool; + struct dm_exception_table pending; struct dm_exception_table complete; @@ -96,6 +96,11 @@ struct dm_snapshot { */ spinlock_t pe_lock; + /* Chunks with outstanding reads */ + spinlock_t tracked_chunk_lock; + mempool_t *tracked_chunk_pool; + struct hlist_head tracked_chunk_hash[DM_TRACKED_CHUNK_HASH_SIZE]; + /* The on disk metadata handler */ struct dm_exception_store *store; @@ -105,10 +110,12 @@ struct dm_snapshot { struct bio_list queued_bios; struct work_struct queued_bios_work; - /* Chunks with outstanding reads */ - mempool_t *tracked_chunk_pool; - spinlock_t tracked_chunk_lock; - struct hlist_head tracked_chunk_hash[DM_TRACKED_CHUNK_HASH_SIZE]; + /* Wait for events based on state_bits */ + unsigned long state_bits; + + /* Range of chunks currently being merged. */ + chunk_t first_merging_chunk; + int num_merging_chunks; /* * The merge operation failed if this flag is set. @@ -125,13 +132,6 @@ struct dm_snapshot { */ int merge_failed; - /* Wait for events based on state_bits */ - unsigned long state_bits; - - /* Range of chunks currently being merged. */ - chunk_t first_merging_chunk; - int num_merging_chunks; - /* * Incoming bios that overlap with chunks being merged must wait * for them to be committed. diff --git a/include/linux/dm-io.h b/include/linux/dm-io.h index b6bf17ee2f61..5c9186b93fff 100644 --- a/include/linux/dm-io.h +++ b/include/linux/dm-io.h @@ -37,14 +37,14 @@ enum dm_io_mem_type { struct dm_io_memory { enum dm_io_mem_type type; + unsigned offset; + union { struct page_list *pl; struct bio_vec *bvec; void *vma; void *addr; } ptr; - - unsigned offset; }; struct dm_io_notify { -- cgit v1.2.3 From f070304094edb8d516423e79edd27c97ec2020b0 Mon Sep 17 00:00:00 2001 From: Takahiro Yasui Date: Sat, 6 Mar 2010 02:32:35 +0000 Subject: dm raid1: fix deadlock when suspending failed device To prevent deadlock, bios in the hold list should be flushed before dm_rh_stop_recovery() is called in mirror_suspend(). The recovery can't start because there are pending bios and therefore dm_rh_stop_recovery deadlocks. When there are pending bios in the hold list, the recovery waits for the completion of the bios after recovery_count is acquired. The recovery_count is released when the recovery finished, however, the bios in the hold list are processed after dm_rh_stop_recovery() in mirror_presuspend(). dm_rh_stop_recovery() also acquires recovery_count, then deadlock occurs. Signed-off-by: Takahiro Yasui Signed-off-by: Alasdair G Kergon Reviewed-by: Mikulas Patocka --- drivers/md/dm-raid1.c | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/md/dm-raid1.c b/drivers/md/dm-raid1.c index 6d66ddf39071..ddda531723dc 100644 --- a/drivers/md/dm-raid1.c +++ b/drivers/md/dm-raid1.c @@ -465,9 +465,17 @@ static void map_region(struct dm_io_region *io, struct mirror *m, static void hold_bio(struct mirror_set *ms, struct bio *bio) { /* - * If device is suspended, complete the bio. + * Lock is required to avoid race condition during suspend + * process. */ + spin_lock_irq(&ms->lock); + if (atomic_read(&ms->suspend)) { + spin_unlock_irq(&ms->lock); + + /* + * If device is suspended, complete the bio. + */ if (dm_noflush_suspending(ms->ti)) bio_endio(bio, DM_ENDIO_REQUEUE); else @@ -478,7 +486,6 @@ static void hold_bio(struct mirror_set *ms, struct bio *bio) /* * Hold bio until the suspend is complete. */ - spin_lock_irq(&ms->lock); bio_list_add(&ms->holds, bio); spin_unlock_irq(&ms->lock); } @@ -1260,6 +1267,20 @@ static void mirror_presuspend(struct dm_target *ti) atomic_set(&ms->suspend, 1); + /* + * Process bios in the hold list to start recovery waiting + * for bios in the hold list. After the process, no bio has + * a chance to be added in the hold list because ms->suspend + * is set. + */ + spin_lock_irq(&ms->lock); + holds = ms->holds; + bio_list_init(&ms->holds); + spin_unlock_irq(&ms->lock); + + while ((bio = bio_list_pop(&holds))) + hold_bio(ms, bio); + /* * We must finish up all the work that we've * generated (i.e. recovery work). @@ -1280,22 +1301,6 @@ static void mirror_presuspend(struct dm_target *ti) * we know that all of our I/O has been pushed. */ flush_workqueue(ms->kmirrord_wq); - - /* - * Now set ms->suspend is set and the workqueue flushed, no more - * entries can be added to ms->hold list, so process it. - * - * Bios can still arrive concurrently with or after this - * presuspend function, but they cannot join the hold list - * because ms->suspend is set. - */ - spin_lock_irq(&ms->lock); - holds = ms->holds; - bio_list_init(&ms->holds); - spin_unlock_irq(&ms->lock); - - while ((bio = bio_list_pop(&holds))) - hold_bio(ms, bio); } static void mirror_postsuspend(struct dm_target *ti) -- cgit v1.2.3 From c90bf2aa94c08a0f48874f64ebdeb5fe973cf02e Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Sun, 29 Nov 2009 16:58:38 +0200 Subject: [WATCHDOG] ep93xx: implemented watchdog timer driver for TS-72xx SBCs Technologic Systems TS-72xx SBCs have external glue logic CPLD which includes watchdog timer. This driver implements kernel support for that. Signed-off-by: Mika Westerberg Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/Kconfig | 11 + drivers/watchdog/Makefile | 1 + drivers/watchdog/ts72xx_wdt.c | 516 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 528 insertions(+) create mode 100644 drivers/watchdog/ts72xx_wdt.c (limited to 'drivers') diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 3da3f48720a7..1e48d4c45f86 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -289,6 +289,17 @@ config ADX_WATCHDOG Say Y here if you want support for the watchdog timer on Avionic Design Xanthos boards. +config TS72XX_WATCHDOG + tristate "TS-72XX SBC Watchdog" + depends on MACH_TS72XX + help + Technologic Systems TS-7200, TS-7250 and TS-7260 boards have + watchdog timer implemented in a external CPLD chip. Say Y here + if you want to support for the watchdog timer on TS-72XX boards. + + To compile this driver as a module, choose M here: the + module will be called ts72xx_wdt. + # AVR32 Architecture config AT32AP700X_WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 475c61100069..2fd15947deb7 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o obj-$(CONFIG_STMP3XXX_WATCHDOG) += stmp3xxx_wdt.o obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o obj-$(CONFIG_ADX_WATCHDOG) += adx_wdt.o +obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o # AVR32 Architecture obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o diff --git a/drivers/watchdog/ts72xx_wdt.c b/drivers/watchdog/ts72xx_wdt.c new file mode 100644 index 000000000000..c4a4d37f85af --- /dev/null +++ b/drivers/watchdog/ts72xx_wdt.c @@ -0,0 +1,516 @@ +/* + * Watchdog driver for Technologic Systems TS-72xx based SBCs + * (TS-7200, TS-7250 and TS-7260). These boards have external + * glue logic CPLD chip, which includes programmable watchdog + * timer. + * + * Copyright (c) 2009 Mika Westerberg + * + * This driver is based on ep93xx_wdt and wm831x_wdt drivers. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TS72XX_WDT_FEED_VAL 0x05 +#define TS72XX_WDT_DEFAULT_TIMEOUT 8 + +static int timeout = TS72XX_WDT_DEFAULT_TIMEOUT; +module_param(timeout, int, 0); +MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. " + "(1 <= timeout <= 8, default=" + __MODULE_STRING(TS72XX_WDT_DEFAULT_TIMEOUT) + ")"); + +static int nowayout = WATCHDOG_NOWAYOUT; +module_param(nowayout, int, 0); +MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close"); + +/** + * struct ts72xx_wdt - watchdog control structure + * @lock: lock that protects this structure + * @regval: watchdog timeout value suitable for control register + * @flags: flags controlling watchdog device state + * @control_reg: watchdog control register + * @feed_reg: watchdog feed register + * @pdev: back pointer to platform dev + */ +struct ts72xx_wdt { + struct mutex lock; + int regval; + +#define TS72XX_WDT_BUSY_FLAG 1 +#define TS72XX_WDT_EXPECT_CLOSE_FLAG 2 + int flags; + + void __iomem *control_reg; + void __iomem *feed_reg; + + struct platform_device *pdev; +}; + +struct platform_device *ts72xx_wdt_pdev; + +/* + * TS-72xx Watchdog supports following timeouts (value written + * to control register): + * value description + * ------------------------- + * 0x00 watchdog disabled + * 0x01 250ms + * 0x02 500ms + * 0x03 1s + * 0x04 reserved + * 0x05 2s + * 0x06 4s + * 0x07 8s + * + * Timeouts below 1s are not very usable so we don't + * allow them at all. + * + * We provide two functions that convert between these: + * timeout_to_regval() and regval_to_timeout(). + */ +static const struct { + int timeout; + int regval; +} ts72xx_wdt_map[] = { + { 1, 3 }, + { 2, 5 }, + { 4, 6 }, + { 8, 7 }, +}; + +/** + * timeout_to_regval() - converts given timeout to control register value + * @new_timeout: timeout in seconds to be converted + * + * Function converts given @new_timeout into valid value that can + * be programmed into watchdog control register. When conversion is + * not possible, function returns %-EINVAL. + */ +static int timeout_to_regval(int new_timeout) +{ + int i; + + /* first limit it to 1 - 8 seconds */ + new_timeout = clamp_val(new_timeout, 1, 8); + + for (i = 0; i < ARRAY_SIZE(ts72xx_wdt_map); i++) { + if (ts72xx_wdt_map[i].timeout >= new_timeout) + return ts72xx_wdt_map[i].regval; + } + + return -EINVAL; +} + +/** + * regval_to_timeout() - converts control register value to timeout + * @regval: control register value to be converted + * + * Function converts given @regval to timeout in seconds (1, 2, 4 or 8). + * If @regval cannot be converted, function returns %-EINVAL. + */ +static int regval_to_timeout(int regval) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ts72xx_wdt_map); i++) { + if (ts72xx_wdt_map[i].regval == regval) + return ts72xx_wdt_map[i].timeout; + } + + return -EINVAL; +} + +/** + * ts72xx_wdt_kick() - kick the watchdog + * @wdt: watchdog to be kicked + * + * Called with @wdt->lock held. + */ +static inline void ts72xx_wdt_kick(struct ts72xx_wdt *wdt) +{ + __raw_writeb(TS72XX_WDT_FEED_VAL, wdt->feed_reg); +} + +/** + * ts72xx_wdt_start() - starts the watchdog timer + * @wdt: watchdog to be started + * + * This function programs timeout to watchdog timer + * and starts it. + * + * Called with @wdt->lock held. + */ +static void ts72xx_wdt_start(struct ts72xx_wdt *wdt) +{ + /* + * To program the wdt, it first must be "fed" and + * only after that (within 30 usecs) the configuration + * can be changed. + */ + ts72xx_wdt_kick(wdt); + __raw_writeb((u8)wdt->regval, wdt->control_reg); +} + +/** + * ts72xx_wdt_stop() - stops the watchdog timer + * @wdt: watchdog to be stopped + * + * Called with @wdt->lock held. + */ +static void ts72xx_wdt_stop(struct ts72xx_wdt *wdt) +{ + ts72xx_wdt_kick(wdt); + __raw_writeb(0, wdt->control_reg); +} + +static int ts72xx_wdt_open(struct inode *inode, struct file *file) +{ + struct ts72xx_wdt *wdt = platform_get_drvdata(ts72xx_wdt_pdev); + int regval; + + /* + * Try to convert default timeout to valid register + * value first. + */ + regval = timeout_to_regval(timeout); + if (regval < 0) { + dev_err(&wdt->pdev->dev, + "failed to convert timeout (%d) to register value\n", + timeout); + return -EINVAL; + } + + if (mutex_lock_interruptible(&wdt->lock)) + return -ERESTARTSYS; + + if ((wdt->flags & TS72XX_WDT_BUSY_FLAG) != 0) { + mutex_unlock(&wdt->lock); + return -EBUSY; + } + + wdt->flags = TS72XX_WDT_BUSY_FLAG; + wdt->regval = regval; + file->private_data = wdt; + + ts72xx_wdt_start(wdt); + + mutex_unlock(&wdt->lock); + return nonseekable_open(inode, file); +} + +static int ts72xx_wdt_release(struct inode *inode, struct file *file) +{ + struct ts72xx_wdt *wdt = file->private_data; + + if (mutex_lock_interruptible(&wdt->lock)) + return -ERESTARTSYS; + + if ((wdt->flags & TS72XX_WDT_EXPECT_CLOSE_FLAG) != 0) { + ts72xx_wdt_stop(wdt); + } else { + dev_warn(&wdt->pdev->dev, + "TS-72XX WDT device closed unexpectly. " + "Watchdog timer will not stop!\n"); + /* + * Kick it one more time, to give userland some time + * to recover (for example, respawning the kicker + * daemon). + */ + ts72xx_wdt_kick(wdt); + } + + wdt->flags = 0; + + mutex_unlock(&wdt->lock); + return 0; +} + +static ssize_t ts72xx_wdt_write(struct file *file, + const char __user *data, + size_t len, + loff_t *ppos) +{ + struct ts72xx_wdt *wdt = file->private_data; + + if (!len) + return 0; + + if (mutex_lock_interruptible(&wdt->lock)) + return -ERESTARTSYS; + + ts72xx_wdt_kick(wdt); + + /* + * Support for magic character closing. User process + * writes 'V' into the device, just before it is closed. + * This means that we know that the wdt timer can be + * stopped after user closes the device. + */ + if (!nowayout) { + int i; + + for (i = 0; i < len; i++) { + char c; + + /* In case it was set long ago */ + wdt->flags &= ~TS72XX_WDT_EXPECT_CLOSE_FLAG; + + if (get_user(c, data + i)) { + mutex_unlock(&wdt->lock); + return -EFAULT; + } + if (c == 'V') { + wdt->flags |= TS72XX_WDT_EXPECT_CLOSE_FLAG; + break; + } + } + } + + mutex_unlock(&wdt->lock); + return len; +} + +static const struct watchdog_info winfo = { + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | + WDIOF_MAGICCLOSE, + .firmware_version = 1, + .identity = "TS-72XX WDT", +}; + +static long ts72xx_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct ts72xx_wdt *wdt = file->private_data; + void __user *argp = (void __user *)arg; + int __user *p = (int __user *)argp; + int error = 0; + + if (mutex_lock_interruptible(&wdt->lock)) + return -ERESTARTSYS; + + switch (cmd) { + case WDIOC_GETSUPPORT: + error = copy_to_user(argp, &winfo, sizeof(winfo)); + break; + + case WDIOC_KEEPALIVE: + ts72xx_wdt_kick(wdt); + break; + + case WDIOC_SETOPTIONS: { + int options; + + if (get_user(options, p)) { + error = -EFAULT; + break; + } + + error = -EINVAL; + + if ((options & WDIOS_DISABLECARD) != 0) { + ts72xx_wdt_stop(wdt); + error = 0; + } + if ((options & WDIOS_ENABLECARD) != 0) { + ts72xx_wdt_start(wdt); + error = 0; + } + + break; + } + + case WDIOC_SETTIMEOUT: { + int new_timeout; + + if (get_user(new_timeout, p)) { + error = -EFAULT; + } else { + int regval; + + regval = timeout_to_regval(new_timeout); + if (regval < 0) { + error = -EINVAL; + } else { + ts72xx_wdt_stop(wdt); + wdt->regval = regval; + ts72xx_wdt_start(wdt); + } + } + if (error) + break; + + /*FALLTHROUGH*/ + } + + case WDIOC_GETTIMEOUT: + if (put_user(regval_to_timeout(wdt->regval), p)) + error = -EFAULT; + break; + + default: + error = -ENOTTY; + break; + } + + mutex_unlock(&wdt->lock); + return error; +} + +static const struct file_operations ts72xx_wdt_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .open = ts72xx_wdt_open, + .release = ts72xx_wdt_release, + .write = ts72xx_wdt_write, + .unlocked_ioctl = ts72xx_wdt_ioctl, +}; + +static struct miscdevice ts72xx_wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = &ts72xx_wdt_fops, +}; + +static __devinit int ts72xx_wdt_probe(struct platform_device *pdev) +{ + struct ts72xx_wdt *wdt; + struct resource *r1, *r2; + int error = 0; + + wdt = kzalloc(sizeof(struct ts72xx_wdt), GFP_KERNEL); + if (!wdt) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + r1 = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r1) { + dev_err(&pdev->dev, "failed to get memory resource\n"); + error = -ENODEV; + goto fail; + } + + r1 = request_mem_region(r1->start, resource_size(r1), pdev->name); + if (!r1) { + dev_err(&pdev->dev, "cannot request memory region\n"); + error = -EBUSY; + goto fail; + } + + wdt->control_reg = ioremap(r1->start, resource_size(r1)); + if (!wdt->control_reg) { + dev_err(&pdev->dev, "failed to map memory\n"); + error = -ENODEV; + goto fail_free_control; + } + + r2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!r2) { + dev_err(&pdev->dev, "failed to get memory resource\n"); + error = -ENODEV; + goto fail_unmap_control; + } + + r2 = request_mem_region(r2->start, resource_size(r2), pdev->name); + if (!r2) { + dev_err(&pdev->dev, "cannot request memory region\n"); + error = -EBUSY; + goto fail_unmap_control; + } + + wdt->feed_reg = ioremap(r2->start, resource_size(r2)); + if (!wdt->feed_reg) { + dev_err(&pdev->dev, "failed to map memory\n"); + error = -ENODEV; + goto fail_free_feed; + } + + platform_set_drvdata(pdev, wdt); + ts72xx_wdt_pdev = pdev; + wdt->pdev = pdev; + mutex_init(&wdt->lock); + + error = misc_register(&ts72xx_wdt_miscdev); + if (error) { + dev_err(&pdev->dev, "failed to register miscdev\n"); + goto fail_unmap_feed; + } + + dev_info(&pdev->dev, "TS-72xx Watchdog driver\n"); + + return 0; + +fail_unmap_feed: + platform_set_drvdata(pdev, NULL); + iounmap(wdt->feed_reg); +fail_free_feed: + release_mem_region(r2->start, resource_size(r2)); +fail_unmap_control: + iounmap(wdt->control_reg); +fail_free_control: + release_mem_region(r1->start, resource_size(r1)); +fail: + kfree(wdt); + return error; +} + +static __devexit int ts72xx_wdt_remove(struct platform_device *pdev) +{ + struct ts72xx_wdt *wdt = platform_get_drvdata(pdev); + struct resource *res; + int error; + + error = misc_deregister(&ts72xx_wdt_miscdev); + platform_set_drvdata(pdev, NULL); + + iounmap(wdt->control_reg); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, resource_size(res)); + + iounmap(wdt->feed_reg); + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + release_mem_region(res->start, resource_size(res)); + + kfree(wdt); + return error; +} + +static struct platform_driver ts72xx_wdt_driver = { + .probe = ts72xx_wdt_probe, + .remove = __devexit_p(ts72xx_wdt_remove), + .driver = { + .name = "ts72xx-wdt", + .owner = THIS_MODULE, + }, +}; + +static __init int ts72xx_wdt_init(void) +{ + return platform_driver_register(&ts72xx_wdt_driver); +} +module_init(ts72xx_wdt_init); + +static __exit void ts72xx_wdt_exit(void) +{ + platform_driver_unregister(&ts72xx_wdt_driver); +} +module_exit(ts72xx_wdt_exit); + +MODULE_AUTHOR("Mika Westerberg "); +MODULE_DESCRIPTION("TS-72xx SBC Watchdog"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:ts72xx-wdt"); -- cgit v1.2.3 From 66aaa7a5592c0d8ca768c77d15d561bd43f514d8 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Thu, 4 Feb 2010 20:08:56 +0000 Subject: [WATCHDOG] support for max63xx watchdog timer chips This driver adds support for the max63{69,70,71,72,73,74} family of watchdog timer chips. It has been tested on an Arcom Zeus (max6369). Signed-off-by: Marc Zyngier Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/Kconfig | 5 + drivers/watchdog/Makefile | 1 + drivers/watchdog/max63xx_wdt.c | 397 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 403 insertions(+) create mode 100644 drivers/watchdog/max63xx_wdt.c (limited to 'drivers') diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 1e48d4c45f86..713b1cef37d3 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -55,6 +55,11 @@ config SOFT_WATCHDOG To compile this driver as a module, choose M here: the module will be called softdog. +config MAX63XX_WATCHDOG + tristate "Max63xx watchdog" + help + Support for memory mapped max63{69,70,71,72,73,74} watchdog timer. + config WM831X_WATCHDOG tristate "WM831x watchdog" depends on MFD_WM831X diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 2fd15947deb7..5e3cb95bb0e9 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -143,4 +143,5 @@ obj-$(CONFIG_WATCHDOG_CP1XXX) += cpwd.o # Architecture Independant obj-$(CONFIG_WM831X_WATCHDOG) += wm831x_wdt.o obj-$(CONFIG_WM8350_WATCHDOG) += wm8350_wdt.o +obj-$(CONFIG_MAX63XX_WATCHDOG) += max63xx_wdt.o obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o diff --git a/drivers/watchdog/max63xx_wdt.c b/drivers/watchdog/max63xx_wdt.c new file mode 100644 index 000000000000..6eb91d757604 --- /dev/null +++ b/drivers/watchdog/max63xx_wdt.c @@ -0,0 +1,397 @@ +/* + * drivers/char/watchdog/max63xx_wdt.c + * + * Driver for max63{69,70,71,72,73,74} watchdog timers + * + * Copyright (C) 2009 Marc Zyngier + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This driver assumes the watchdog pins are memory mapped (as it is + * the case for the Arcom Zeus). Should it be connected over GPIOs or + * another interface, some abstraction will have to be introduced. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEFAULT_HEARTBEAT 60 +#define MAX_HEARTBEAT 60 + +static int heartbeat = DEFAULT_HEARTBEAT; +static int nowayout = WATCHDOG_NOWAYOUT; + +/* + * Memory mapping: a single byte, 3 first lower bits to select bit 3 + * to ping the watchdog. + */ +#define MAX6369_WDSET (7 << 0) +#define MAX6369_WDI (1 << 3) + +static DEFINE_SPINLOCK(io_lock); + +static unsigned long wdt_status; +#define WDT_IN_USE 0 +#define WDT_RUNNING 1 +#define WDT_OK_TO_CLOSE 2 + +static int nodelay; +static struct resource *wdt_mem; +static void __iomem *wdt_base; +static struct platform_device *max63xx_pdev; + +/* + * The timeout values used are actually the absolute minimum the chip + * offers. Typical values on my board are slightly over twice as long + * (10s setting ends up with a 25s timeout), and can be up to 3 times + * the nominal setting (according to the datasheet). So please take + * these values with a grain of salt. Same goes for the initial delay + * "feature". Only max6373/74 have a few settings without this initial + * delay (selected with the "nodelay" parameter). + * + * I also decided to remove from the tables any timeout smaller than a + * second, as it looked completly overkill... + */ + +/* Timeouts in second */ +struct max63xx_timeout { + u8 wdset; + u8 tdelay; + u8 twd; +}; + +static struct max63xx_timeout max6369_table[] = { + { 5, 1, 1 }, + { 6, 10, 10 }, + { 7, 60, 60 }, + { }, +}; + +static struct max63xx_timeout max6371_table[] = { + { 6, 60, 3 }, + { 7, 60, 60 }, + { }, +}; + +static struct max63xx_timeout max6373_table[] = { + { 2, 60, 1 }, + { 5, 0, 1 }, + { 1, 3, 3 }, + { 7, 60, 10 }, + { 6, 0, 10 }, + { }, +}; + +static struct max63xx_timeout *current_timeout; + +static struct max63xx_timeout * +max63xx_select_timeout(struct max63xx_timeout *table, int value) +{ + while (table->twd) { + if (value <= table->twd) { + if (nodelay && table->tdelay == 0) + return table; + + if (!nodelay) + return table; + } + + table++; + } + + return NULL; +} + +static void max63xx_wdt_ping(void) +{ + u8 val; + + spin_lock(&io_lock); + + val = __raw_readb(wdt_base); + + __raw_writeb(val | MAX6369_WDI, wdt_base); + __raw_writeb(val & ~MAX6369_WDI, wdt_base); + + spin_unlock(&io_lock); +} + +static void max63xx_wdt_enable(struct max63xx_timeout *entry) +{ + u8 val; + + if (test_and_set_bit(WDT_RUNNING, &wdt_status)) + return; + + spin_lock(&io_lock); + + val = __raw_readb(wdt_base); + val &= ~MAX6369_WDSET; + val |= entry->wdset; + __raw_writeb(val, wdt_base); + + spin_unlock(&io_lock); + + /* check for a edge triggered startup */ + if (entry->tdelay == 0) + max63xx_wdt_ping(); +} + +static void max63xx_wdt_disable(void) +{ + spin_lock(&io_lock); + + __raw_writeb(3, wdt_base); + + spin_unlock(&io_lock); + + clear_bit(WDT_RUNNING, &wdt_status); +} + +static int max63xx_wdt_open(struct inode *inode, struct file *file) +{ + if (test_and_set_bit(WDT_IN_USE, &wdt_status)) + return -EBUSY; + + max63xx_wdt_enable(current_timeout); + clear_bit(WDT_OK_TO_CLOSE, &wdt_status); + + return nonseekable_open(inode, file); +} + +static ssize_t max63xx_wdt_write(struct file *file, const char *data, + size_t len, loff_t *ppos) +{ + if (len) { + if (!nowayout) { + size_t i; + + clear_bit(WDT_OK_TO_CLOSE, &wdt_status); + for (i = 0; i != len; i++) { + char c; + + if (get_user(c, data + i)) + return -EFAULT; + + if (c == 'V') + set_bit(WDT_OK_TO_CLOSE, &wdt_status); + } + } + + max63xx_wdt_ping(); + } + + return len; +} + +static const struct watchdog_info ident = { + .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, + .identity = "max63xx Watchdog", +}; + +static long max63xx_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + int ret = -ENOTTY; + + switch (cmd) { + case WDIOC_GETSUPPORT: + ret = copy_to_user((struct watchdog_info *)arg, &ident, + sizeof(ident)) ? -EFAULT : 0; + break; + + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + ret = put_user(0, (int *)arg); + break; + + case WDIOC_KEEPALIVE: + max63xx_wdt_ping(); + ret = 0; + break; + + case WDIOC_GETTIMEOUT: + ret = put_user(heartbeat, (int *)arg); + break; + } + return ret; +} + +static int max63xx_wdt_release(struct inode *inode, struct file *file) +{ + if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) + max63xx_wdt_disable(); + else + dev_crit(&max63xx_pdev->dev, + "device closed unexpectedly - timer will not stop\n"); + + clear_bit(WDT_IN_USE, &wdt_status); + clear_bit(WDT_OK_TO_CLOSE, &wdt_status); + + return 0; +} + +static const struct file_operations max63xx_wdt_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = max63xx_wdt_write, + .unlocked_ioctl = max63xx_wdt_ioctl, + .open = max63xx_wdt_open, + .release = max63xx_wdt_release, +}; + +static struct miscdevice max63xx_wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = &max63xx_wdt_fops, +}; + +static int __devinit max63xx_wdt_probe(struct platform_device *pdev) +{ + int ret = 0; + int size; + struct resource *res; + struct device *dev = &pdev->dev; + struct max63xx_timeout *table; + + table = (struct max63xx_timeout *)pdev->id_entry->driver_data; + + if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT) + heartbeat = DEFAULT_HEARTBEAT; + + dev_info(dev, "requesting %ds heartbeat\n", heartbeat); + current_timeout = max63xx_select_timeout(table, heartbeat); + + if (!current_timeout) { + dev_err(dev, "unable to satisfy heartbeat request\n"); + return -EINVAL; + } + + dev_info(dev, "using %ds heartbeat with %ds initial delay\n", + current_timeout->twd, current_timeout->tdelay); + + heartbeat = current_timeout->twd; + + max63xx_pdev = pdev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(dev, "failed to get memory region resource\n"); + return -ENOENT; + } + + size = resource_size(res); + wdt_mem = request_mem_region(res->start, size, pdev->name); + + if (wdt_mem == NULL) { + dev_err(dev, "failed to get memory region\n"); + return -ENOENT; + } + + wdt_base = ioremap(res->start, size); + if (!wdt_base) { + dev_err(dev, "failed to map memory region\n"); + ret = -ENOMEM; + goto out_request; + } + + ret = misc_register(&max63xx_wdt_miscdev); + if (ret < 0) { + dev_err(dev, "cannot register misc device\n"); + goto out_unmap; + } + + return 0; + +out_unmap: + iounmap(wdt_base); +out_request: + release_resource(wdt_mem); + kfree(wdt_mem); + + return ret; +} + +static int __devexit max63xx_wdt_remove(struct platform_device *pdev) +{ + misc_deregister(&max63xx_wdt_miscdev); + if (wdt_mem) { + release_resource(wdt_mem); + kfree(wdt_mem); + wdt_mem = NULL; + } + + if (wdt_base) + iounmap(wdt_base); + + return 0; +} + +static struct platform_device_id max63xx_id_table[] = { + { "max6369_wdt", (kernel_ulong_t)max6369_table, }, + { "max6370_wdt", (kernel_ulong_t)max6369_table, }, + { "max6371_wdt", (kernel_ulong_t)max6371_table, }, + { "max6372_wdt", (kernel_ulong_t)max6371_table, }, + { "max6373_wdt", (kernel_ulong_t)max6373_table, }, + { "max6374_wdt", (kernel_ulong_t)max6373_table, }, + { }, +}; +MODULE_DEVICE_TABLE(platform, max63xx_id_table); + +static struct platform_driver max63xx_wdt_driver = { + .probe = max63xx_wdt_probe, + .remove = __devexit_p(max63xx_wdt_remove), + .id_table = max63xx_id_table, + .driver = { + .name = "max63xx_wdt", + .owner = THIS_MODULE, + }, +}; + +static int __init max63xx_wdt_init(void) +{ + return platform_driver_register(&max63xx_wdt_driver); +} + +static void __exit max63xx_wdt_exit(void) +{ + platform_driver_unregister(&max63xx_wdt_driver); +} + +module_init(max63xx_wdt_init); +module_exit(max63xx_wdt_exit); + +MODULE_AUTHOR("Marc Zyngier "); +MODULE_DESCRIPTION("max63xx Watchdog Driver"); + +module_param(heartbeat, int, 0); +MODULE_PARM_DESC(heartbeat, + "Watchdog heartbeat period in seconds from 1 to " + __MODULE_STRING(MAX_HEARTBEAT) ", default " + __MODULE_STRING(DEFAULT_HEARTBEAT)); + +module_param(nowayout, int, 0); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); + +module_param(nodelay, int, 0); +MODULE_PARM_DESC(nodelay, + "Force selection of a timeout setting without initial delay " + "(max6373/74 only, default=0)"); + +MODULE_LICENSE("GPL"); +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -- cgit v1.2.3 From f538ed9ea0a54ba2121f35f52d63e4025c534909 Mon Sep 17 00:00:00 2001 From: Wim Van Sebroeck Date: Wed, 10 Feb 2010 19:34:05 +0000 Subject: [WATCHDOG] ep93xx: watchdog timer driver for TS-72xx SBCs cleanup Clean-up driver: * make release the reverse of probe so that both are consistent * add WDIOC_GETSTATUS & WDIOC_GETBOOTSTATUS ioctls. Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/ts72xx_wdt.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/ts72xx_wdt.c b/drivers/watchdog/ts72xx_wdt.c index c4a4d37f85af..565a2c3321e5 100644 --- a/drivers/watchdog/ts72xx_wdt.c +++ b/drivers/watchdog/ts72xx_wdt.c @@ -307,6 +307,10 @@ static long ts72xx_wdt_ioctl(struct file *file, unsigned int cmd, error = copy_to_user(argp, &winfo, sizeof(winfo)); break; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_KEEPALIVE: ts72xx_wdt_kick(wdt); break; @@ -477,14 +481,14 @@ static __devexit int ts72xx_wdt_remove(struct platform_device *pdev) error = misc_deregister(&ts72xx_wdt_miscdev); platform_set_drvdata(pdev, NULL); - iounmap(wdt->control_reg); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - release_mem_region(res->start, resource_size(res)); - iounmap(wdt->feed_reg); res = platform_get_resource(pdev, IORESOURCE_MEM, 1); release_mem_region(res->start, resource_size(res)); + iounmap(wdt->control_reg); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, resource_size(res)); + kfree(wdt); return error; } -- cgit v1.2.3 From ec26985be4a22652c323f264cf570e4fbe3610b6 Mon Sep 17 00:00:00 2001 From: Naga Chumbalkar Date: Tue, 9 Feb 2010 00:42:02 +0100 Subject: [WATCHDOG] iTCO_wdt: clean up probe(), modify err msg It's possible that the platform is not allowing reboot via TCO timer expiration. Also, differentiate between not finding a chipset that has TCO, and the case where TCO is present but the driver fails to initialize for some reason. Signed-off-by: Naga Chumbalkar Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/iTCO_wdt.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c index 4bdb7f1a9077..a619b9b74991 100644 --- a/drivers/watchdog/iTCO_wdt.c +++ b/drivers/watchdog/iTCO_wdt.c @@ -698,7 +698,7 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, if (iTCO_wdt_private.iTCO_version == 2) { pci_read_config_dword(pdev, 0xf0, &base_address); if ((base_address & 1) == 0) { - printk(KERN_ERR PFX "RCBA is disabled by harddware\n"); + printk(KERN_ERR PFX "RCBA is disabled by hardware\n"); ret = -ENODEV; goto out; } @@ -708,8 +708,8 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, /* Check chipset's NO_REBOOT bit */ if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) { - printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, " - "reboot disabled by hardware\n"); + printk(KERN_INFO PFX "unable to reset NO_REBOOT flag, " + "platform may have disabled it\n"); ret = -ENODEV; /* Cannot reset NO_REBOOT bit */ goto out_unmap; } @@ -805,6 +805,7 @@ static void __devexit iTCO_wdt_cleanup(void) static int __devinit iTCO_wdt_probe(struct platform_device *dev) { + int ret = -ENODEV; int found = 0; struct pci_dev *pdev = NULL; const struct pci_device_id *ent; @@ -814,19 +815,17 @@ static int __devinit iTCO_wdt_probe(struct platform_device *dev) for_each_pci_dev(pdev) { ent = pci_match_id(iTCO_wdt_pci_tbl, pdev); if (ent) { - if (!(iTCO_wdt_init(pdev, ent, dev))) { - found++; + found++; + ret = iTCO_wdt_init(pdev, ent, dev); + if (!ret) break; - } } } - if (!found) { + if (!found) printk(KERN_INFO PFX "No card detected\n"); - return -ENODEV; - } - return 0; + return ret; } static int __devexit iTCO_wdt_remove(struct platform_device *dev) -- cgit v1.2.3 From cda61c9420028ddd251b60f1445c9eed756991c7 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Mon, 1 Mar 2010 17:06:20 +0000 Subject: [WATCHDOG] gef_wdt: Author corrections following split of GE Fanuc joint venture This patch corrects author and copyright notices following the split-up of the GE Fanuc joint venture. Signed-off-by: Martyn Welch Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/Kconfig | 4 ++-- drivers/watchdog/gef_wdt.c | 14 +++++++------- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 713b1cef37d3..bdcdbd53da89 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -861,10 +861,10 @@ config TXX9_WDT # POWERPC Architecture config GEF_WDT - tristate "GE Fanuc Watchdog Timer" + tristate "GE Watchdog Timer" depends on GEF_SBC610 || GEF_SBC310 || GEF_PPC9A ---help--- - Watchdog timer found in a number of GE Fanuc single board computers. + Watchdog timer found in a number of GE single board computers. config MPC5200_WDT bool "MPC52xx Watchdog Timer" diff --git a/drivers/watchdog/gef_wdt.c b/drivers/watchdog/gef_wdt.c index 734d9806a872..26447bdeac22 100644 --- a/drivers/watchdog/gef_wdt.c +++ b/drivers/watchdog/gef_wdt.c @@ -1,9 +1,9 @@ /* - * GE Fanuc watchdog userspace interface + * GE watchdog userspace interface * - * Author: Martyn Welch + * Author: Martyn Welch * - * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. + * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -165,7 +165,7 @@ static long gef_wdt_ioctl(struct file *file, unsigned int cmd, .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, .firmware_version = 0, - .identity = "GE Fanuc watchdog", + .identity = "GE watchdog", }; switch (cmd) { @@ -311,7 +311,7 @@ static struct of_platform_driver gef_wdt_driver = { static int __init gef_wdt_init(void) { - printk(KERN_INFO "GE Fanuc watchdog driver\n"); + printk(KERN_INFO "GE watchdog driver\n"); return of_register_platform_driver(&gef_wdt_driver); } @@ -323,8 +323,8 @@ static void __exit gef_wdt_exit(void) module_init(gef_wdt_init); module_exit(gef_wdt_exit); -MODULE_AUTHOR("Martyn Welch "); -MODULE_DESCRIPTION("GE Fanuc watchdog driver"); +MODULE_AUTHOR("Martyn Welch "); +MODULE_DESCRIPTION("GE watchdog driver"); MODULE_LICENSE("GPL"); MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); MODULE_ALIAS("platform: gef_wdt"); -- cgit v1.2.3 From e3cb91ce1ac1d93a7cc6f81bb5247f7602b572bb Mon Sep 17 00:00:00 2001 From: David Miller Date: Fri, 5 Mar 2010 13:41:36 -0800 Subject: timbgpio: fix build MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use of get_irq_chip_data() et al. requires including linux/irq.h Signed-off-by: David S. Miller Cc: Richard Röjfors Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/gpio/timbgpio.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpio/timbgpio.c b/drivers/gpio/timbgpio.c index a4d344ba8e5c..d941f45fe557 100644 --- a/drivers/gpio/timbgpio.c +++ b/drivers/gpio/timbgpio.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include -- cgit v1.2.3 From 984b3f5746ed2cde3d184651dabf26980f2b66e5 Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Fri, 5 Mar 2010 13:41:37 -0800 Subject: bitops: rename for_each_bit() to for_each_set_bit() Rename for_each_bit to for_each_set_bit in the kernel source tree. To permit for_each_clear_bit(), should that ever be added. The patch includes a macro to map the old for_each_bit() onto the new for_each_set_bit(). This is a (very) temporary thing to ease the migration. [akpm@linux-foundation.org: add temporary for_each_bit()] Suggested-by: Alexey Dobriyan Suggested-by: Andrew Morton Signed-off-by: Akinobu Mita Cc: "David S. Miller" Cc: Russell King Cc: David Woodhouse Cc: Artem Bityutskiy Cc: Stephen Rothwell Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/x86/kernel/cpu/perf_event.c | 2 +- arch/x86/kernel/cpu/perf_event_intel.c | 2 +- drivers/dma/ioat/dma.c | 2 +- drivers/gpio/pl061.c | 2 +- drivers/gpio/timbgpio.c | 2 +- drivers/i2c/busses/i2c-designware.c | 4 ++-- drivers/mfd/htc-egpio.c | 2 +- drivers/misc/sgi-xp/xpnet.c | 2 +- drivers/net/gianfar.c | 12 ++++++------ drivers/net/ixgbe/ixgbe_main.c | 2 +- drivers/net/ixgbevf/ixgbevf_main.c | 2 +- drivers/net/wireless/ath/ar9170/main.c | 2 +- drivers/net/wireless/iwmc3200wifi/debugfs.c | 2 +- drivers/net/wireless/iwmc3200wifi/rx.c | 2 +- fs/ocfs2/quota_local.c | 2 +- include/linux/bitops.h | 4 +++- kernel/sched_cpupri.c | 2 +- sound/soc/codecs/uda1380.c | 2 +- 18 files changed, 26 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 641ccb9dddbc..b1fbdeecf6c9 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -676,7 +676,7 @@ static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) if (c->weight != w) continue; - for_each_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { + for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { if (!test_bit(j, used_mask)) break; } diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index cf6590cf4a5f..977e7544738c 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -757,7 +757,7 @@ again: inc_irq_stat(apic_perf_irqs); ack = status; - for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { + for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { struct perf_event *event = cpuc->events[bit]; clear_bit(bit, (unsigned long *) &status); diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 5d0e42b263df..af14c9a5b8d4 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -71,7 +71,7 @@ static irqreturn_t ioat_dma_do_interrupt(int irq, void *data) } attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); - for_each_bit(bit, &attnstatus, BITS_PER_LONG) { + for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) { chan = ioat_chan_by_index(instance, bit); tasklet_schedule(&chan->cleanup_task); } diff --git a/drivers/gpio/pl061.c b/drivers/gpio/pl061.c index 4ee4c8367a3f..3ad1eeb49609 100644 --- a/drivers/gpio/pl061.c +++ b/drivers/gpio/pl061.c @@ -219,7 +219,7 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc) if (pending == 0) continue; - for_each_bit(offset, &pending, PL061_GPIO_NR) + for_each_set_bit(offset, &pending, PL061_GPIO_NR) generic_handle_irq(pl061_to_irq(&chip->gc, offset)); } desc->chip->unmask(irq); diff --git a/drivers/gpio/timbgpio.c b/drivers/gpio/timbgpio.c index d941f45fe557..4ecba6e5a32d 100644 --- a/drivers/gpio/timbgpio.c +++ b/drivers/gpio/timbgpio.c @@ -175,7 +175,7 @@ static void timbgpio_irq(unsigned int irq, struct irq_desc *desc) ipr = ioread32(tgpio->membase + TGPIO_IPR); iowrite32(ipr, tgpio->membase + TGPIO_ICR); - for_each_bit(offset, &ipr, tgpio->gpio.ngpio) + for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio) generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset)); } diff --git a/drivers/i2c/busses/i2c-designware.c b/drivers/i2c/busses/i2c-designware.c index 9e18ef97f156..3e72b69aa7f8 100644 --- a/drivers/i2c/busses/i2c-designware.c +++ b/drivers/i2c/busses/i2c-designware.c @@ -497,13 +497,13 @@ static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) int i; if (abort_source & DW_IC_TX_ABRT_NOACK) { - for_each_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) + for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) dev_dbg(dev->dev, "%s: %s\n", __func__, abort_sources[i]); return -EREMOTEIO; } - for_each_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) + for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); if (abort_source & DW_IC_TX_ARB_LOST) diff --git a/drivers/mfd/htc-egpio.c b/drivers/mfd/htc-egpio.c index aa266e1f69b2..addb846c1e34 100644 --- a/drivers/mfd/htc-egpio.c +++ b/drivers/mfd/htc-egpio.c @@ -108,7 +108,7 @@ static void egpio_handler(unsigned int irq, struct irq_desc *desc) ack_irqs(ei); /* Process all set pins. */ readval &= ei->irqs_enabled; - for_each_bit(irqpin, &readval, ei->nirqs) { + for_each_set_bit(irqpin, &readval, ei->nirqs) { /* Run irq handler */ pr_debug("got IRQ %d\n", irqpin); irq = ei->irq_start + irqpin; diff --git a/drivers/misc/sgi-xp/xpnet.c b/drivers/misc/sgi-xp/xpnet.c index 16f0abda1423..57b152f8d1b9 100644 --- a/drivers/misc/sgi-xp/xpnet.c +++ b/drivers/misc/sgi-xp/xpnet.c @@ -475,7 +475,7 @@ xpnet_dev_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) if (skb->data[0] == 0xff) { /* we are being asked to broadcast to all partitions */ - for_each_bit(dest_partid, xpnet_broadcast_partitions, + for_each_set_bit(dest_partid, xpnet_broadcast_partitions, xp_max_npartitions) { xpnet_send(skb, queued_msg, start_addr, end_addr, diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index 6aa526ee9096..61a7b4351e78 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c @@ -998,7 +998,7 @@ static int gfar_probe(struct of_device *ofdev, } /* Need to reverse the bit maps as bit_map's MSB is q0 - * but, for_each_bit parses from right to left, which + * but, for_each_set_bit parses from right to left, which * basically reverses the queue numbers */ for (i = 0; i< priv->num_grps; i++) { priv->gfargrp[i].tx_bit_map = reverse_bitmap( @@ -1011,7 +1011,7 @@ static int gfar_probe(struct of_device *ofdev, * also assign queues to groups */ for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { priv->gfargrp[grp_idx].num_rx_queues = 0x0; - for_each_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, + for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, priv->num_rx_queues) { priv->gfargrp[grp_idx].num_rx_queues++; priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; @@ -1019,7 +1019,7 @@ static int gfar_probe(struct of_device *ofdev, rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); } priv->gfargrp[grp_idx].num_tx_queues = 0x0; - for_each_bit (i, &priv->gfargrp[grp_idx].tx_bit_map, + for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, priv->num_tx_queues) { priv->gfargrp[grp_idx].num_tx_queues++; priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; @@ -1709,7 +1709,7 @@ void gfar_configure_coalescing(struct gfar_private *priv, if (priv->mode == MQ_MG_MODE) { baddr = ®s->txic0; - for_each_bit (i, &tx_mask, priv->num_tx_queues) { + for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { if (likely(priv->tx_queue[i]->txcoalescing)) { gfar_write(baddr + i, 0); gfar_write(baddr + i, priv->tx_queue[i]->txic); @@ -1717,7 +1717,7 @@ void gfar_configure_coalescing(struct gfar_private *priv, } baddr = ®s->rxic0; - for_each_bit (i, &rx_mask, priv->num_rx_queues) { + for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { if (likely(priv->rx_queue[i]->rxcoalescing)) { gfar_write(baddr + i, 0); gfar_write(baddr + i, priv->rx_queue[i]->rxic); @@ -2607,7 +2607,7 @@ static int gfar_poll(struct napi_struct *napi, int budget) budget_per_queue = left_over_budget/num_queues; left_over_budget = 0; - for_each_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { + for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { if (test_bit(i, &serviced_queues)) continue; rx_queue = priv->rx_queue[i]; diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index 45e3532b166f..684af371462d 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c @@ -1050,7 +1050,7 @@ static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) */ for (v_idx = 0; v_idx < q_vectors; v_idx++) { q_vector = adapter->q_vector[v_idx]; - /* XXX for_each_bit(...) */ + /* XXX for_each_set_bit(...) */ r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); diff --git a/drivers/net/ixgbevf/ixgbevf_main.c b/drivers/net/ixgbevf/ixgbevf_main.c index 235b5fd4b8d4..ca653c49b765 100644 --- a/drivers/net/ixgbevf/ixgbevf_main.c +++ b/drivers/net/ixgbevf/ixgbevf_main.c @@ -751,7 +751,7 @@ static void ixgbevf_configure_msix(struct ixgbevf_adapter *adapter) */ for (v_idx = 0; v_idx < q_vectors; v_idx++) { q_vector = adapter->q_vector[v_idx]; - /* XXX for_each_bit(...) */ + /* XXX for_each_set_bit(...) */ r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); diff --git a/drivers/net/wireless/ath/ar9170/main.c b/drivers/net/wireless/ath/ar9170/main.c index 8a964f130367..a6452af9c6c5 100644 --- a/drivers/net/wireless/ath/ar9170/main.c +++ b/drivers/net/wireless/ath/ar9170/main.c @@ -394,7 +394,7 @@ static void ar9170_tx_fake_ampdu_status(struct ar9170 *ar) ieee80211_tx_status_irqsafe(ar->hw, skb); } - for_each_bit(i, &queue_bitmap, BITS_PER_BYTE) { + for_each_set_bit(i, &queue_bitmap, BITS_PER_BYTE) { #ifdef AR9170_QUEUE_STOP_DEBUG printk(KERN_DEBUG "%s: wake queue %d\n", wiphy_name(ar->hw->wiphy), i); diff --git a/drivers/net/wireless/iwmc3200wifi/debugfs.c b/drivers/net/wireless/iwmc3200wifi/debugfs.c index be992ca41cf1..c29c994de0e2 100644 --- a/drivers/net/wireless/iwmc3200wifi/debugfs.c +++ b/drivers/net/wireless/iwmc3200wifi/debugfs.c @@ -89,7 +89,7 @@ static int iwm_debugfs_dbg_modules_write(void *data, u64 val) for (i = 0; i < __IWM_DM_NR; i++) iwm->dbg.dbg_module[i] = 0; - for_each_bit(bit, &iwm->dbg.dbg_modules, __IWM_DM_NR) + for_each_set_bit(bit, &iwm->dbg.dbg_modules, __IWM_DM_NR) iwm->dbg.dbg_module[bit] = iwm->dbg.dbg_level; return 0; diff --git a/drivers/net/wireless/iwmc3200wifi/rx.c b/drivers/net/wireless/iwmc3200wifi/rx.c index ad8f7eabb5aa..8456b4dbd146 100644 --- a/drivers/net/wireless/iwmc3200wifi/rx.c +++ b/drivers/net/wireless/iwmc3200wifi/rx.c @@ -1116,7 +1116,7 @@ static int iwm_ntf_stop_resume_tx(struct iwm_priv *iwm, u8 *buf, return -EINVAL; } - for_each_bit(bit, (unsigned long *)&tid_msk, IWM_UMAC_TID_NR) { + for_each_set_bit(bit, (unsigned long *)&tid_msk, IWM_UMAC_TID_NR) { tid_info = &sta_info->tid_info[bit]; mutex_lock(&tid_info->mutex); diff --git a/fs/ocfs2/quota_local.c b/fs/ocfs2/quota_local.c index 21f9e71223ca..a6467f3d262e 100644 --- a/fs/ocfs2/quota_local.c +++ b/fs/ocfs2/quota_local.c @@ -457,7 +457,7 @@ static int ocfs2_recover_local_quota_file(struct inode *lqinode, break; } dchunk = (struct ocfs2_local_disk_chunk *)hbh->b_data; - for_each_bit(bit, rchunk->rc_bitmap, ol_chunk_entries(sb)) { + for_each_set_bit(bit, rchunk->rc_bitmap, ol_chunk_entries(sb)) { qbh = NULL; status = ocfs2_read_quota_block(lqinode, ol_dqblk_block(sb, chunk, bit), diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 25b8b2f33ae9..b79389879238 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -16,11 +16,13 @@ */ #include -#define for_each_bit(bit, addr, size) \ +#define for_each_set_bit(bit, addr, size) \ for ((bit) = find_first_bit((addr), (size)); \ (bit) < (size); \ (bit) = find_next_bit((addr), (size), (bit) + 1)) +/* Temporary */ +#define for_each_bit(bit, addr, size) for_each_set_bit(bit, addr, size) static __inline__ int get_bitmask_order(unsigned int count) { diff --git a/kernel/sched_cpupri.c b/kernel/sched_cpupri.c index eeb3506c4834..82095bf2099f 100644 --- a/kernel/sched_cpupri.c +++ b/kernel/sched_cpupri.c @@ -47,7 +47,7 @@ static int convert_prio(int prio) } #define for_each_cpupri_active(array, idx) \ - for_each_bit(idx, array, CPUPRI_NR_PRIORITIES) + for_each_set_bit(idx, array, CPUPRI_NR_PRIORITIES) /** * cpupri_find - find the best (lowest-pri) CPU in the system diff --git a/sound/soc/codecs/uda1380.c b/sound/soc/codecs/uda1380.c index a2763c2e7348..9cd0a66b7663 100644 --- a/sound/soc/codecs/uda1380.c +++ b/sound/soc/codecs/uda1380.c @@ -137,7 +137,7 @@ static void uda1380_flush_work(struct work_struct *work) { int bit, reg; - for_each_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) { + for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) { reg = 0x10 + bit; pr_debug("uda1380: flush reg %x val %x:\n", reg, uda1380_read_reg_cache(uda1380_codec, reg)); -- cgit v1.2.3 From 19b629f581320999ddb9f6597051b79cdb53459c Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Fri, 5 Mar 2010 13:41:38 -0800 Subject: infiniband: use for_each_set_bit() Replace open-coded loop with for_each_set_bit(). Signed-off-by: Akinobu Mita Acked-by: Roland Dreier Cc: Sean Hefty Cc: Hal Rosenstock Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/infiniband/core/mad.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/infiniband/core/mad.c b/drivers/infiniband/core/mad.c index 7522008fda86..58463da814d1 100644 --- a/drivers/infiniband/core/mad.c +++ b/drivers/infiniband/core/mad.c @@ -1193,10 +1193,7 @@ static int method_in_use(struct ib_mad_mgmt_method_table **method, { int i; - for (i = find_first_bit(mad_reg_req->method_mask, IB_MGMT_MAX_METHODS); - i < IB_MGMT_MAX_METHODS; - i = find_next_bit(mad_reg_req->method_mask, IB_MGMT_MAX_METHODS, - 1+i)) { + for_each_set_bit(i, mad_reg_req->method_mask, IB_MGMT_MAX_METHODS) { if ((*method)->agent[i]) { printk(KERN_ERR PFX "Method %d already in use\n", i); return -EINVAL; @@ -1330,13 +1327,9 @@ static int add_nonoui_reg_req(struct ib_mad_reg_req *mad_reg_req, goto error3; /* Finally, add in methods being registered */ - for (i = find_first_bit(mad_reg_req->method_mask, - IB_MGMT_MAX_METHODS); - i < IB_MGMT_MAX_METHODS; - i = find_next_bit(mad_reg_req->method_mask, IB_MGMT_MAX_METHODS, - 1+i)) { + for_each_set_bit(i, mad_reg_req->method_mask, IB_MGMT_MAX_METHODS) (*method)->agent[i] = agent_priv; - } + return 0; error3: @@ -1429,13 +1422,9 @@ check_in_use: goto error4; /* Finally, add in methods being registered */ - for (i = find_first_bit(mad_reg_req->method_mask, - IB_MGMT_MAX_METHODS); - i < IB_MGMT_MAX_METHODS; - i = find_next_bit(mad_reg_req->method_mask, IB_MGMT_MAX_METHODS, - 1+i)) { + for_each_set_bit(i, mad_reg_req->method_mask, IB_MGMT_MAX_METHODS) (*method)->agent[i] = agent_priv; - } + return 0; error4: -- cgit v1.2.3 From d96ae5309165d9ed7c008a178238977b73595cd9 Mon Sep 17 00:00:00 2001 From: "akpm@linux-foundation.org" Date: Fri, 5 Mar 2010 13:41:58 -0800 Subject: memory-hotplug: create /sys/firmware/memmap entry for new memory A memmap is a directory in sysfs which includes 3 text files: start, end and type. For example: start: 0x100000 end: 0x7e7b1cff type: System RAM Interface firmware_map_add was not called explicitly. Remove it and add function firmware_map_add_hotplug as hotplug interface of memmap. Each memory entry has a memmap in sysfs, When we hot-add new memory, sysfs does not export memmap entry for it. We add a call in function add_memory to function firmware_map_add_hotplug. Add a new function add_sysfs_fw_map_entry() to create memmap entry, it will be called when initialize memmap and hot-add memory. [akpm@linux-foundation.org: un-kernedoc a no longer kerneldoc comment] Signed-off-by: Shaohui Zheng Acked-by: Andi Kleen Acked-by: Yasunori Goto Reviewed-by: Wu Fengguang Cc: Dave Hansen Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/firmware/memmap.c | 57 ++++++++++++++++++++++++++++---------------- include/linux/firmware-map.h | 6 ++--- mm/memory_hotplug.c | 4 ++++ 3 files changed, 43 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/firmware/memmap.c b/drivers/firmware/memmap.c index 56f9234781fa..20f645743ead 100644 --- a/drivers/firmware/memmap.c +++ b/drivers/firmware/memmap.c @@ -122,29 +122,53 @@ static int firmware_map_add_entry(u64 start, u64 end, return 0; } +/* + * Add memmap entry on sysfs + */ +static int add_sysfs_fw_map_entry(struct firmware_map_entry *entry) +{ + static int map_entries_nr; + static struct kset *mmap_kset; + + if (!mmap_kset) { + mmap_kset = kset_create_and_add("memmap", NULL, firmware_kobj); + if (!mmap_kset) + return -ENOMEM; + } + + entry->kobj.kset = mmap_kset; + if (kobject_add(&entry->kobj, NULL, "%d", map_entries_nr++)) + kobject_put(&entry->kobj); + + return 0; +} + /** - * firmware_map_add() - Adds a firmware mapping entry. + * firmware_map_add_hotplug() - Adds a firmware mapping entry when we do + * memory hotplug. * @start: Start of the memory range. * @end: End of the memory range (inclusive). * @type: Type of the memory range. * - * This function uses kmalloc() for memory - * allocation. Use firmware_map_add_early() if you want to use the bootmem - * allocator. - * - * That function must be called before late_initcall. + * Adds a firmware mapping entry. This function is for memory hotplug, it is + * similar to function firmware_map_add_early(). The only difference is that + * it will create the syfs entry dynamically. * * Returns 0 on success, or -ENOMEM if no memory could be allocated. **/ -int firmware_map_add(u64 start, u64 end, const char *type) +int __meminit firmware_map_add_hotplug(u64 start, u64 end, const char *type) { struct firmware_map_entry *entry; - entry = kmalloc(sizeof(struct firmware_map_entry), GFP_ATOMIC); + entry = kzalloc(sizeof(struct firmware_map_entry), GFP_ATOMIC); if (!entry) return -ENOMEM; - return firmware_map_add_entry(start, end, type, entry); + firmware_map_add_entry(start, end, type, entry); + /* create the memmap entry */ + add_sysfs_fw_map_entry(entry); + + return 0; } /** @@ -154,7 +178,7 @@ int firmware_map_add(u64 start, u64 end, const char *type) * @type: Type of the memory range. * * Adds a firmware mapping entry. This function uses the bootmem allocator - * for memory allocation. Use firmware_map_add() if you want to use kmalloc(). + * for memory allocation. * * That function must be called before late_initcall. * @@ -214,19 +238,10 @@ static ssize_t memmap_attr_show(struct kobject *kobj, */ static int __init memmap_init(void) { - int i = 0; struct firmware_map_entry *entry; - struct kset *memmap_kset; - - memmap_kset = kset_create_and_add("memmap", NULL, firmware_kobj); - if (WARN_ON(!memmap_kset)) - return -ENOMEM; - list_for_each_entry(entry, &map_entries, list) { - entry->kobj.kset = memmap_kset; - if (kobject_add(&entry->kobj, NULL, "%d", i++)) - kobject_put(&entry->kobj); - } + list_for_each_entry(entry, &map_entries, list) + add_sysfs_fw_map_entry(entry); return 0; } diff --git a/include/linux/firmware-map.h b/include/linux/firmware-map.h index 875451f1373a..c6dcc1dfe781 100644 --- a/include/linux/firmware-map.h +++ b/include/linux/firmware-map.h @@ -24,17 +24,17 @@ */ #ifdef CONFIG_FIRMWARE_MEMMAP -int firmware_map_add(u64 start, u64 end, const char *type); int firmware_map_add_early(u64 start, u64 end, const char *type); +int firmware_map_add_hotplug(u64 start, u64 end, const char *type); #else /* CONFIG_FIRMWARE_MEMMAP */ -static inline int firmware_map_add(u64 start, u64 end, const char *type) +static inline int firmware_map_add_early(u64 start, u64 end, const char *type) { return 0; } -static inline int firmware_map_add_early(u64 start, u64 end, const char *type) +static inline int firmware_map_add_hotplug(u64 start, u64 end, const char *type) { return 0; } diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c index 030ce8a5bb0e..78e34e63c7b8 100644 --- a/mm/memory_hotplug.c +++ b/mm/memory_hotplug.c @@ -28,6 +28,7 @@ #include #include #include +#include #include @@ -523,6 +524,9 @@ int __ref add_memory(int nid, u64 start, u64 size) BUG_ON(ret); } + /* create new memmap entry */ + firmware_map_add_hotplug(start, start + size, "System RAM"); + goto out; error: -- cgit v1.2.3 From 56e6943b41468826c26155139629c9a5379550ab Mon Sep 17 00:00:00 2001 From: Richard Kennedy Date: Fri, 5 Mar 2010 13:42:30 -0800 Subject: cpuidle menu: remove 8 bytes of padding on 64 bit builds Reorder struct menu_device to remove 8 bytes of padding on 64 bit builds. Size drops from 136 to 128 bytes, so possibly needing one fewer cache lines. Signed-off-by: Richard Kennedy Cc: Arjan van de Ven Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/cpuidle/governors/menu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/cpuidle/governors/menu.c b/drivers/cpuidle/governors/menu.c index 73655aeb3a60..1aea7157d8ff 100644 --- a/drivers/cpuidle/governors/menu.c +++ b/drivers/cpuidle/governors/menu.c @@ -100,8 +100,8 @@ struct menu_device { int needs_update; unsigned int expected_us; - u64 predicted_us; unsigned int measured_us; + u64 predicted_us; unsigned int exit_us; unsigned int bucket; u64 correction_factor[BUCKETS]; -- cgit v1.2.3 From 9c8f05c2837b06bb2739e85204c0d34009fb6494 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Fri, 5 Mar 2010 13:42:35 -0800 Subject: MFGPT: move clocksource menu Move the CS5535 MFGPT hrtimer kconfig option to be with the other MFGPT options. This makes it easier to find and also removes it from the main "Device Drivers" menu, where it should not have been. Signed-off-by: Randy Dunlap Acked-by: Andres Salomon Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/Kconfig | 2 -- drivers/clocksource/Kconfig | 9 --------- drivers/misc/Kconfig | 9 +++++++++ 3 files changed, 9 insertions(+), 11 deletions(-) delete mode 100644 drivers/clocksource/Kconfig (limited to 'drivers') diff --git a/drivers/Kconfig b/drivers/Kconfig index 368ae6d3a096..a2b902f4d437 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -96,8 +96,6 @@ source "drivers/edac/Kconfig" source "drivers/rtc/Kconfig" -source "drivers/clocksource/Kconfig" - source "drivers/dma/Kconfig" source "drivers/dca/Kconfig" diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig deleted file mode 100644 index 08f726c5fee5..000000000000 --- a/drivers/clocksource/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -config CS5535_CLOCK_EVENT_SRC - tristate "CS5535/CS5536 high-res timer (MFGPT) events" - depends on GENERIC_TIME && GENERIC_CLOCKEVENTS && CS5535_MFGPT - help - This driver provides a clock event source based on the MFGPT - timer(s) in the CS5535 and CS5536 companion chips. - MFGPTs have a better resolution and max interval than the - generic PIT, and are suitable for use as high-res timers. - diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index e3551d20464f..d16af6a423fb 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -212,6 +212,15 @@ config CS5535_MFGPT_DEFAULT_IRQ want to use a different IRQ by default. This is here for architectures to set as necessary. +config CS5535_CLOCK_EVENT_SRC + tristate "CS5535/CS5536 high-res timer (MFGPT) events" + depends on GENERIC_TIME && GENERIC_CLOCKEVENTS && CS5535_MFGPT + help + This driver provides a clock event source based on the MFGPT + timer(s) in the CS5535 and CS5536 companion chips. + MFGPTs have a better resolution and max interval than the + generic PIT, and are suitable for use as high-res timers. + config HP_ILO tristate "Channel interface driver for HP iLO/iLO2 processor" depends on PCI -- cgit v1.2.3 From 08d9e7363b87a4c5fb3fc17070607a75a9eb4cc8 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Fri, 5 Mar 2010 13:42:47 -0800 Subject: drivers/misc/iwmc3200top/main.c: eliminate useless code The variable priv is initialized twice to the same (side effect-free) expression. Drop one initialization. A simplified version of the semantic match that finds this problem is: (http://coccinelle.lip6.fr/) // @forall@ idexpression *x; identifier f!=ERR_PTR; @@ x = f(...) ... when != x ( x = f(...,<+...x...+>,...) | * x = f(...) ) // Signed-off-by: Julia Lawall Cc: Tomas Winkler Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/misc/iwmc3200top/main.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers') diff --git a/drivers/misc/iwmc3200top/main.c b/drivers/misc/iwmc3200top/main.c index dd0a3913bf6d..3b7292a5cea9 100644 --- a/drivers/misc/iwmc3200top/main.c +++ b/drivers/misc/iwmc3200top/main.c @@ -597,8 +597,6 @@ static void iwmct_remove(struct sdio_func *func) struct iwmct_work_struct *read_req; struct iwmct_priv *priv = sdio_get_drvdata(func); - priv = sdio_get_drvdata(func); - LOG_INFO(priv, INIT, "enter\n"); sdio_claim_host(func); -- cgit v1.2.3 From 33fd797b3e2c6a7663b9331150da0acdb31990a2 Mon Sep 17 00:00:00 2001 From: Thadeu Lima de Souza Cascardo Date: Fri, 5 Mar 2010 13:42:48 -0800 Subject: eisa: fix coding style for eisa bus code Signed-off-by: Thadeu Lima de Souza Cascardo Cc: Kay Sievers Cc: Greg Kroah-Hartman Cc: Alan Cox Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/eisa/eisa-bus.c | 240 ++++++++++++++++++++++++++---------------------- 1 file changed, 128 insertions(+), 112 deletions(-) (limited to 'drivers') diff --git a/drivers/eisa/eisa-bus.c b/drivers/eisa/eisa-bus.c index 66958b3f10b4..806c77bfd434 100644 --- a/drivers/eisa/eisa-bus.c +++ b/drivers/eisa/eisa-bus.c @@ -39,10 +39,10 @@ static unsigned int enable_dev_count; static int disable_dev[EISA_MAX_FORCED_DEV]; static unsigned int disable_dev_count; -static int is_forced_dev (int *forced_tab, - int forced_count, - struct eisa_root_device *root, - struct eisa_device *edev) +static int is_forced_dev(int *forced_tab, + int forced_count, + struct eisa_root_device *root, + struct eisa_device *edev) { int i, x; @@ -55,21 +55,21 @@ static int is_forced_dev (int *forced_tab, return 0; } -static void __init eisa_name_device (struct eisa_device *edev) +static void __init eisa_name_device(struct eisa_device *edev) { #ifdef CONFIG_EISA_NAMES int i; for (i = 0; i < EISA_INFOS; i++) { - if (!strcmp (edev->id.sig, eisa_table[i].id.sig)) { - strlcpy (edev->pretty_name, - eisa_table[i].name, - sizeof(edev->pretty_name)); + if (!strcmp(edev->id.sig, eisa_table[i].id.sig)) { + strlcpy(edev->pretty_name, + eisa_table[i].name, + sizeof(edev->pretty_name)); return; } } /* No name was found */ - sprintf (edev->pretty_name, "EISA device %.7s", edev->id.sig); + sprintf(edev->pretty_name, "EISA device %.7s", edev->id.sig); #endif } @@ -91,7 +91,7 @@ static char __init *decode_eisa_sig(unsigned long addr) */ outb(0x80 + i, addr); #endif - sig[i] = inb (addr + i); + sig[i] = inb(addr + i); if (!i && (sig[0] & 0x80)) return NULL; @@ -106,17 +106,17 @@ static char __init *decode_eisa_sig(unsigned long addr) return sig_str; } -static int eisa_bus_match (struct device *dev, struct device_driver *drv) +static int eisa_bus_match(struct device *dev, struct device_driver *drv) { - struct eisa_device *edev = to_eisa_device (dev); - struct eisa_driver *edrv = to_eisa_driver (drv); + struct eisa_device *edev = to_eisa_device(dev); + struct eisa_driver *edrv = to_eisa_driver(drv); const struct eisa_device_id *eids = edrv->id_table; if (!eids) return 0; - while (strlen (eids->sig)) { - if (!strcmp (eids->sig, edev->id.sig) && + while (strlen(eids->sig)) { + if (!strcmp(eids->sig, edev->id.sig) && edev->state & EISA_CONFIG_ENABLED) { edev->id.driver_data = eids->driver_data; return 1; @@ -141,61 +141,71 @@ struct bus_type eisa_bus_type = { .match = eisa_bus_match, .uevent = eisa_bus_uevent, }; +EXPORT_SYMBOL(eisa_bus_type); -int eisa_driver_register (struct eisa_driver *edrv) +int eisa_driver_register(struct eisa_driver *edrv) { edrv->driver.bus = &eisa_bus_type; - return driver_register (&edrv->driver); + return driver_register(&edrv->driver); } +EXPORT_SYMBOL(eisa_driver_register); -void eisa_driver_unregister (struct eisa_driver *edrv) +void eisa_driver_unregister(struct eisa_driver *edrv) { - driver_unregister (&edrv->driver); + driver_unregister(&edrv->driver); } +EXPORT_SYMBOL(eisa_driver_unregister); -static ssize_t eisa_show_sig (struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t eisa_show_sig(struct device *dev, struct device_attribute *attr, + char *buf) { - struct eisa_device *edev = to_eisa_device (dev); - return sprintf (buf,"%s\n", edev->id.sig); + struct eisa_device *edev = to_eisa_device(dev); + return sprintf(buf, "%s\n", edev->id.sig); } static DEVICE_ATTR(signature, S_IRUGO, eisa_show_sig, NULL); -static ssize_t eisa_show_state (struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t eisa_show_state(struct device *dev, + struct device_attribute *attr, + char *buf) { - struct eisa_device *edev = to_eisa_device (dev); - return sprintf (buf,"%d\n", edev->state & EISA_CONFIG_ENABLED); + struct eisa_device *edev = to_eisa_device(dev); + return sprintf(buf, "%d\n", edev->state & EISA_CONFIG_ENABLED); } static DEVICE_ATTR(enabled, S_IRUGO, eisa_show_state, NULL); -static ssize_t eisa_show_modalias (struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t eisa_show_modalias(struct device *dev, + struct device_attribute *attr, + char *buf) { - struct eisa_device *edev = to_eisa_device (dev); - return sprintf (buf, EISA_DEVICE_MODALIAS_FMT "\n", edev->id.sig); + struct eisa_device *edev = to_eisa_device(dev); + return sprintf(buf, EISA_DEVICE_MODALIAS_FMT "\n", edev->id.sig); } static DEVICE_ATTR(modalias, S_IRUGO, eisa_show_modalias, NULL); -static int __init eisa_init_device (struct eisa_root_device *root, - struct eisa_device *edev, - int slot) +static int __init eisa_init_device(struct eisa_root_device *root, + struct eisa_device *edev, + int slot) { char *sig; - unsigned long sig_addr; + unsigned long sig_addr; int i; - sig_addr = SLOT_ADDRESS (root, slot) + EISA_VENDOR_ID_OFFSET; + sig_addr = SLOT_ADDRESS(root, slot) + EISA_VENDOR_ID_OFFSET; - if (!(sig = decode_eisa_sig (sig_addr))) + sig = decode_eisa_sig(sig_addr); + if (!sig) return -1; /* No EISA device here */ - memcpy (edev->id.sig, sig, EISA_SIG_LEN); + memcpy(edev->id.sig, sig, EISA_SIG_LEN); edev->slot = slot; - edev->state = inb (SLOT_ADDRESS (root, slot) + EISA_CONFIG_OFFSET) & EISA_CONFIG_ENABLED; - edev->base_addr = SLOT_ADDRESS (root, slot); + edev->state = inb(SLOT_ADDRESS(root, slot) + EISA_CONFIG_OFFSET) + & EISA_CONFIG_ENABLED; + edev->base_addr = SLOT_ADDRESS(root, slot); edev->dma_mask = root->dma_mask; /* Default DMA mask */ - eisa_name_device (edev); + eisa_name_device(edev); edev->dev.parent = root->dev; edev->dev.bus = &eisa_bus_type; edev->dev.dma_mask = &edev->dma_mask; @@ -210,42 +220,45 @@ static int __init eisa_init_device (struct eisa_root_device *root, #endif } - if (is_forced_dev (enable_dev, enable_dev_count, root, edev)) + if (is_forced_dev(enable_dev, enable_dev_count, root, edev)) edev->state = EISA_CONFIG_ENABLED | EISA_CONFIG_FORCED; - if (is_forced_dev (disable_dev, disable_dev_count, root, edev)) + if (is_forced_dev(disable_dev, disable_dev_count, root, edev)) edev->state = EISA_CONFIG_FORCED; return 0; } -static int __init eisa_register_device (struct eisa_device *edev) +static int __init eisa_register_device(struct eisa_device *edev) { - int rc = device_register (&edev->dev); + int rc = device_register(&edev->dev); if (rc) return rc; - rc = device_create_file (&edev->dev, &dev_attr_signature); - if (rc) goto err_devreg; - rc = device_create_file (&edev->dev, &dev_attr_enabled); - if (rc) goto err_sig; - rc = device_create_file (&edev->dev, &dev_attr_modalias); - if (rc) goto err_enab; + rc = device_create_file(&edev->dev, &dev_attr_signature); + if (rc) + goto err_devreg; + rc = device_create_file(&edev->dev, &dev_attr_enabled); + if (rc) + goto err_sig; + rc = device_create_file(&edev->dev, &dev_attr_modalias); + if (rc) + goto err_enab; return 0; err_enab: - device_remove_file (&edev->dev, &dev_attr_enabled); + device_remove_file(&edev->dev, &dev_attr_enabled); err_sig: - device_remove_file (&edev->dev, &dev_attr_signature); + device_remove_file(&edev->dev, &dev_attr_signature); err_devreg: device_unregister(&edev->dev); return rc; } -static int __init eisa_request_resources (struct eisa_root_device *root, - struct eisa_device *edev, - int slot) +static int __init eisa_request_resources(struct eisa_root_device *root, + struct eisa_device *edev, + int slot) { int i; @@ -263,17 +276,19 @@ static int __init eisa_request_resources (struct eisa_root_device *root, if (slot) { edev->res[i].name = NULL; - edev->res[i].start = SLOT_ADDRESS (root, slot) + (i * 0x400); + edev->res[i].start = SLOT_ADDRESS(root, slot) + + (i * 0x400); edev->res[i].end = edev->res[i].start + 0xff; edev->res[i].flags = IORESOURCE_IO; } else { edev->res[i].name = NULL; - edev->res[i].start = SLOT_ADDRESS (root, slot) + EISA_VENDOR_ID_OFFSET; + edev->res[i].start = SLOT_ADDRESS(root, slot) + + EISA_VENDOR_ID_OFFSET; edev->res[i].end = edev->res[i].start + 3; edev->res[i].flags = IORESOURCE_BUSY; } - if (request_resource (root->res, &edev->res[i])) + if (request_resource(root->res, &edev->res[i])) goto failed; } @@ -281,99 +296,100 @@ static int __init eisa_request_resources (struct eisa_root_device *root, failed: while (--i >= 0) - release_resource (&edev->res[i]); + release_resource(&edev->res[i]); return -1; } -static void __init eisa_release_resources (struct eisa_device *edev) +static void __init eisa_release_resources(struct eisa_device *edev) { int i; for (i = 0; i < EISA_MAX_RESOURCES; i++) if (edev->res[i].start || edev->res[i].end) - release_resource (&edev->res[i]); + release_resource(&edev->res[i]); } -static int __init eisa_probe (struct eisa_root_device *root) +static int __init eisa_probe(struct eisa_root_device *root) { int i, c; struct eisa_device *edev; - printk (KERN_INFO "EISA: Probing bus %d at %s\n", - root->bus_nr, dev_name(root->dev)); + printk(KERN_INFO "EISA: Probing bus %d at %s\n", + root->bus_nr, dev_name(root->dev)); /* First try to get hold of slot 0. If there is no device * here, simply fail, unless root->force_probe is set. */ - if (!(edev = kzalloc (sizeof (*edev), GFP_KERNEL))) { - printk (KERN_ERR "EISA: Couldn't allocate mainboard slot\n"); + edev = kzalloc(sizeof(*edev), GFP_KERNEL); + if (!edev) { + printk(KERN_ERR "EISA: Couldn't allocate mainboard slot\n"); return -ENOMEM; } - if (eisa_request_resources (root, edev, 0)) { - printk (KERN_WARNING \ - "EISA: Cannot allocate resource for mainboard\n"); - kfree (edev); + if (eisa_request_resources(root, edev, 0)) { + printk(KERN_WARNING \ + "EISA: Cannot allocate resource for mainboard\n"); + kfree(edev); if (!root->force_probe) return -EBUSY; goto force_probe; } - if (eisa_init_device (root, edev, 0)) { - eisa_release_resources (edev); - kfree (edev); + if (eisa_init_device(root, edev, 0)) { + eisa_release_resources(edev); + kfree(edev); if (!root->force_probe) return -ENODEV; goto force_probe; } - printk (KERN_INFO "EISA: Mainboard %s detected.\n", edev->id.sig); + printk(KERN_INFO "EISA: Mainboard %s detected.\n", edev->id.sig); - if (eisa_register_device (edev)) { - printk (KERN_ERR "EISA: Failed to register %s\n", - edev->id.sig); - eisa_release_resources (edev); - kfree (edev); + if (eisa_register_device(edev)) { + printk(KERN_ERR "EISA: Failed to register %s\n", + edev->id.sig); + eisa_release_resources(edev); + kfree(edev); } force_probe: for (c = 0, i = 1; i <= root->slots; i++) { - if (!(edev = kzalloc (sizeof (*edev), GFP_KERNEL))) { - printk (KERN_ERR "EISA: Out of memory for slot %d\n", - i); + edev = kzalloc(sizeof(*edev), GFP_KERNEL); + if (!edev) { + printk(KERN_ERR "EISA: Out of memory for slot %d\n", i); continue; } - if (eisa_request_resources (root, edev, i)) { - printk (KERN_WARNING \ - "Cannot allocate resource for EISA slot %d\n", - i); - kfree (edev); + if (eisa_request_resources(root, edev, i)) { + printk(KERN_WARNING \ + "Cannot allocate resource for EISA slot %d\n", + i); + kfree(edev); continue; } - if (eisa_init_device (root, edev, i)) { - eisa_release_resources (edev); - kfree (edev); + if (eisa_init_device(root, edev, i)) { + eisa_release_resources(edev); + kfree(edev); continue; } - printk (KERN_INFO "EISA: slot %d : %s detected", - i, edev->id.sig); + printk(KERN_INFO "EISA: slot %d : %s detected", + i, edev->id.sig); switch (edev->state) { case EISA_CONFIG_ENABLED | EISA_CONFIG_FORCED: - printk (" (forced enabled)"); + printk(" (forced enabled)"); break; case EISA_CONFIG_FORCED: - printk (" (forced disabled)"); + printk(" (forced disabled)"); break; case 0: - printk (" (disabled)"); + printk(" (disabled)"); break; } @@ -381,15 +397,15 @@ static int __init eisa_probe (struct eisa_root_device *root) c++; - if (eisa_register_device (edev)) { - printk (KERN_ERR "EISA: Failed to register %s\n", - edev->id.sig); - eisa_release_resources (edev); - kfree (edev); + if (eisa_register_device(edev)) { + printk(KERN_ERR "EISA: Failed to register %s\n", + edev->id.sig); + eisa_release_resources(edev); + kfree(edev); } } - printk (KERN_INFO "EISA: Detected %d card%s.\n", c, c == 1 ? "" : "s"); + printk(KERN_INFO "EISA: Detected %d card%s.\n", c, c == 1 ? "" : "s"); return 0; } @@ -403,7 +419,7 @@ static struct resource eisa_root_res = { static int eisa_bus_count; -int __init eisa_root_register (struct eisa_root_device *root) +int __init eisa_root_register(struct eisa_root_device *root) { int err; @@ -417,35 +433,35 @@ int __init eisa_root_register (struct eisa_root_device *root) root->eisa_root_res.end = root->res->end; root->eisa_root_res.flags = IORESOURCE_BUSY; - if ((err = request_resource (&eisa_root_res, &root->eisa_root_res))) + err = request_resource(&eisa_root_res, &root->eisa_root_res); + if (err) return err; root->bus_nr = eisa_bus_count++; - if ((err = eisa_probe (root))) - release_resource (&root->eisa_root_res); + err = eisa_probe(root); + if (err) + release_resource(&root->eisa_root_res); return err; } -static int __init eisa_init (void) +static int __init eisa_init(void) { int r; - if ((r = bus_register (&eisa_bus_type))) + r = bus_register(&eisa_bus_type); + if (r) return r; - printk (KERN_INFO "EISA bus registered\n"); + printk(KERN_INFO "EISA bus registered\n"); return 0; } module_param_array(enable_dev, int, &enable_dev_count, 0444); module_param_array(disable_dev, int, &disable_dev_count, 0444); -postcore_initcall (eisa_init); +postcore_initcall(eisa_init); int EISA_bus; /* for legacy drivers */ -EXPORT_SYMBOL (EISA_bus); -EXPORT_SYMBOL (eisa_bus_type); -EXPORT_SYMBOL (eisa_driver_register); -EXPORT_SYMBOL (eisa_driver_unregister); +EXPORT_SYMBOL(EISA_bus); -- cgit v1.2.3 From 0347af4ee3922220f6bfe74b87b526aa709a0365 Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Fri, 5 Mar 2010 13:42:49 -0800 Subject: lkdtm: add debugfs access and loosen KPROBE ties Add adds a debugfs interface and additional failure modes to LKDTM to provide similar functionality to the provoke-crash driver submitted here: http://lwn.net/Articles/371208/ Crashes can now be induced either through module parameters (as before) or through the debugfs interface as in provoke-crash. The patch also provides a new "direct" interface, where KPROBES are not used, i.e., the crash is invoked directly upon write to the debugfs file. When built without KPROBES configured, only this mode is available. Signed-off-by: Simon Kagstrom Cc: M. Mohan Kumar Cc: Americo Wang Cc: David Woodhouse Cc: Ingo Molnar Cc: "Eric W. Biederman" , Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/fault-injection/provoke-crashes.txt | 38 ++ drivers/misc/lkdtm.c | 472 ++++++++++++++++++---- lib/Kconfig.debug | 5 +- 3 files changed, 430 insertions(+), 85 deletions(-) create mode 100644 Documentation/fault-injection/provoke-crashes.txt (limited to 'drivers') diff --git a/Documentation/fault-injection/provoke-crashes.txt b/Documentation/fault-injection/provoke-crashes.txt new file mode 100644 index 000000000000..7a9d3d81525b --- /dev/null +++ b/Documentation/fault-injection/provoke-crashes.txt @@ -0,0 +1,38 @@ +The lkdtm module provides an interface to crash or injure the kernel at +predefined crashpoints to evaluate the reliability of crash dumps obtained +using different dumping solutions. The module uses KPROBEs to instrument +crashing points, but can also crash the kernel directly without KRPOBE +support. + + +You can provide the way either through module arguments when inserting +the module, or through a debugfs interface. + +Usage: insmod lkdtm.ko [recur_count={>0}] cpoint_name=<> cpoint_type=<> + [cpoint_count={>0}] + + recur_count : Recursion level for the stack overflow test. Default is 10. + + cpoint_name : Crash point where the kernel is to be crashed. It can be + one of INT_HARDWARE_ENTRY, INT_HW_IRQ_EN, INT_TASKLET_ENTRY, + FS_DEVRW, MEM_SWAPOUT, TIMERADD, SCSI_DISPATCH_CMD, + IDE_CORE_CP, DIRECT + + cpoint_type : Indicates the action to be taken on hitting the crash point. + It can be one of PANIC, BUG, EXCEPTION, LOOP, OVERFLOW, + CORRUPT_STACK, UNALIGNED_LOAD_STORE_WRITE, OVERWRITE_ALLOCATION, + WRITE_AFTER_FREE, + + cpoint_count : Indicates the number of times the crash point is to be hit + to trigger an action. The default is 10. + +You can also induce failures by mounting debugfs and writing the type to +/provoke-crash/. E.g., + + mount -t debugfs debugfs /mnt + echo EXCEPTION > /mnt/provoke-crash/INT_HARDWARE_ENTRY + + +A special file is `DIRECT' which will induce the crash directly without +KPROBE instrumentation. This mode is the only one available when the module +is built on a kernel without KPROBEs support. diff --git a/drivers/misc/lkdtm.c b/drivers/misc/lkdtm.c index 3648b23d5c92..4a0648301fdf 100644 --- a/drivers/misc/lkdtm.c +++ b/drivers/misc/lkdtm.c @@ -26,21 +26,9 @@ * It is adapted from the Linux Kernel Dump Test Tool by * Fernando Luis Vazquez Cao * - * Usage : insmod lkdtm.ko [recur_count={>0}] cpoint_name=<> cpoint_type=<> - * [cpoint_count={>0}] + * Debugfs support added by Simon Kagstrom * - * recur_count : Recursion level for the stack overflow test. Default is 10. - * - * cpoint_name : Crash point where the kernel is to be crashed. It can be - * one of INT_HARDWARE_ENTRY, INT_HW_IRQ_EN, INT_TASKLET_ENTRY, - * FS_DEVRW, MEM_SWAPOUT, TIMERADD, SCSI_DISPATCH_CMD, - * IDE_CORE_CP - * - * cpoint_type : Indicates the action to be taken on hitting the crash point. - * It can be one of PANIC, BUG, EXCEPTION, LOOP, OVERFLOW - * - * cpoint_count : Indicates the number of times the crash point is to be hit - * to trigger an action. The default is 10. + * See Documentation/fault-injection/provoke-crashes.txt for instructions */ #include @@ -53,13 +41,12 @@ #include #include #include +#include #ifdef CONFIG_IDE #include #endif -#define NUM_CPOINTS 8 -#define NUM_CPOINT_TYPES 5 #define DEFAULT_COUNT 10 #define REC_NUM_DEFAULT 10 @@ -72,7 +59,8 @@ enum cname { MEM_SWAPOUT, TIMERADD, SCSI_DISPATCH_CMD, - IDE_CORE_CP + IDE_CORE_CP, + DIRECT, }; enum ctype { @@ -81,7 +69,11 @@ enum ctype { BUG, EXCEPTION, LOOP, - OVERFLOW + OVERFLOW, + CORRUPT_STACK, + UNALIGNED_LOAD_STORE_WRITE, + OVERWRITE_ALLOCATION, + WRITE_AFTER_FREE, }; static char* cp_name[] = { @@ -92,7 +84,8 @@ static char* cp_name[] = { "MEM_SWAPOUT", "TIMERADD", "SCSI_DISPATCH_CMD", - "IDE_CORE_CP" + "IDE_CORE_CP", + "DIRECT", }; static char* cp_type[] = { @@ -100,7 +93,11 @@ static char* cp_type[] = { "BUG", "EXCEPTION", "LOOP", - "OVERFLOW" + "OVERFLOW", + "CORRUPT_STACK", + "UNALIGNED_LOAD_STORE_WRITE", + "OVERWRITE_ALLOCATION", + "WRITE_AFTER_FREE", }; static struct jprobe lkdtm; @@ -193,34 +190,66 @@ int jp_generic_ide_ioctl(ide_drive_t *drive, struct file *file, } #endif +/* Return the crashpoint number or NONE if the name is invalid */ +static enum ctype parse_cp_type(const char *what, size_t count) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cp_type); i++) { + if (!strcmp(what, cp_type[i])) + return i + 1; + } + + return NONE; +} + +static const char *cp_type_to_str(enum ctype type) +{ + if (type == NONE || type < 0 || type > ARRAY_SIZE(cp_type)) + return "None"; + + return cp_type[type - 1]; +} + +static const char *cp_name_to_str(enum cname name) +{ + if (name == INVALID || name < 0 || name > ARRAY_SIZE(cp_name)) + return "INVALID"; + + return cp_name[name - 1]; +} + + static int lkdtm_parse_commandline(void) { int i; - if (cpoint_name == NULL || cpoint_type == NULL || - cpoint_count < 1 || recur_count < 1) + if (cpoint_count < 1 || recur_count < 1) return -EINVAL; - for (i = 0; i < NUM_CPOINTS; ++i) { + count = cpoint_count; + + /* No special parameters */ + if (!cpoint_type && !cpoint_name) + return 0; + + /* Neither or both of these need to be set */ + if (!cpoint_type || !cpoint_name) + return -EINVAL; + + cptype = parse_cp_type(cpoint_type, strlen(cpoint_type)); + if (cptype == NONE) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(cp_name); i++) { if (!strcmp(cpoint_name, cp_name[i])) { cpoint = i + 1; - break; - } - } - - for (i = 0; i < NUM_CPOINT_TYPES; ++i) { - if (!strcmp(cpoint_type, cp_type[i])) { - cptype = i + 1; - break; + return 0; } } - if (cpoint == INVALID || cptype == NONE) - return -EINVAL; - - count = cpoint_count; - - return 0; + /* Could not find a valid crash point */ + return -EINVAL; } static int recursive_loop(int a) @@ -235,53 +264,92 @@ static int recursive_loop(int a) return recursive_loop(a); } -void lkdtm_handler(void) +static void lkdtm_do_action(enum ctype which) { - printk(KERN_INFO "lkdtm : Crash point %s of type %s hit\n", - cpoint_name, cpoint_type); - --count; + switch (which) { + case PANIC: + panic("dumptest"); + break; + case BUG: + BUG(); + break; + case EXCEPTION: + *((int *) 0) = 0; + break; + case LOOP: + for (;;) + ; + break; + case OVERFLOW: + (void) recursive_loop(0); + break; + case CORRUPT_STACK: { + volatile u32 data[8]; + volatile u32 *p = data; + + p[12] = 0x12345678; + break; + } + case UNALIGNED_LOAD_STORE_WRITE: { + static u8 data[5] __attribute__((aligned(4))) = {1, 2, + 3, 4, 5}; + u32 *p; + u32 val = 0x12345678; + + p = (u32 *)(data + 1); + if (*p == 0) + val = 0x87654321; + *p = val; + break; + } + case OVERWRITE_ALLOCATION: { + size_t len = 1020; + u32 *data = kmalloc(len, GFP_KERNEL); + + data[1024 / sizeof(u32)] = 0x12345678; + kfree(data); + break; + } + case WRITE_AFTER_FREE: { + size_t len = 1024; + u32 *data = kmalloc(len, GFP_KERNEL); + + kfree(data); + schedule(); + memset(data, 0x78, len); + break; + } + case NONE: + default: + break; + } + +} + +static void lkdtm_handler(void) +{ + count--; + printk(KERN_INFO "lkdtm: Crash point %s of type %s hit, trigger in %d rounds\n", + cp_name_to_str(cpoint), cp_type_to_str(cptype), count); if (count == 0) { - switch (cptype) { - case NONE: - break; - case PANIC: - printk(KERN_INFO "lkdtm : PANIC\n"); - panic("dumptest"); - break; - case BUG: - printk(KERN_INFO "lkdtm : BUG\n"); - BUG(); - break; - case EXCEPTION: - printk(KERN_INFO "lkdtm : EXCEPTION\n"); - *((int *) 0) = 0; - break; - case LOOP: - printk(KERN_INFO "lkdtm : LOOP\n"); - for (;;); - break; - case OVERFLOW: - printk(KERN_INFO "lkdtm : OVERFLOW\n"); - (void) recursive_loop(0); - break; - default: - break; - } + lkdtm_do_action(cptype); count = cpoint_count; } } -static int __init lkdtm_module_init(void) +static int lkdtm_register_cpoint(enum cname which) { int ret; - if (lkdtm_parse_commandline() == -EINVAL) { - printk(KERN_INFO "lkdtm : Invalid command\n"); - return -EINVAL; - } + cpoint = INVALID; + if (lkdtm.entry != NULL) + unregister_jprobe(&lkdtm); - switch (cpoint) { + switch (which) { + case DIRECT: + lkdtm_do_action(cptype); + return 0; case INT_HARDWARE_ENTRY: lkdtm.kp.symbol_name = "do_IRQ"; lkdtm.entry = (kprobe_opcode_t*) jp_do_irq; @@ -315,28 +383,268 @@ static int __init lkdtm_module_init(void) lkdtm.kp.symbol_name = "generic_ide_ioctl"; lkdtm.entry = (kprobe_opcode_t*) jp_generic_ide_ioctl; #else - printk(KERN_INFO "lkdtm : Crash point not available\n"); + printk(KERN_INFO "lkdtm: Crash point not available\n"); + return -EINVAL; #endif break; default: - printk(KERN_INFO "lkdtm : Invalid Crash Point\n"); - break; + printk(KERN_INFO "lkdtm: Invalid Crash Point\n"); + return -EINVAL; } + cpoint = which; if ((ret = register_jprobe(&lkdtm)) < 0) { - printk(KERN_INFO "lkdtm : Couldn't register jprobe\n"); - return ret; + printk(KERN_INFO "lkdtm: Couldn't register jprobe\n"); + cpoint = INVALID; + } + + return ret; +} + +static ssize_t do_register_entry(enum cname which, struct file *f, + const char __user *user_buf, size_t count, loff_t *off) +{ + char *buf; + int err; + + if (count >= PAGE_SIZE) + return -EINVAL; + + buf = (char *)__get_free_page(GFP_KERNEL); + if (!buf) + return -ENOMEM; + if (copy_from_user(buf, user_buf, count)) { + free_page((unsigned long) buf); + return -EFAULT; + } + /* NULL-terminate and remove enter */ + buf[count] = '\0'; + strim(buf); + + cptype = parse_cp_type(buf, count); + free_page((unsigned long) buf); + + if (cptype == NONE) + return -EINVAL; + + err = lkdtm_register_cpoint(which); + if (err < 0) + return err; + + *off += count; + + return count; +} + +/* Generic read callback that just prints out the available crash types */ +static ssize_t lkdtm_debugfs_read(struct file *f, char __user *user_buf, + size_t count, loff_t *off) +{ + char *buf; + int i, n, out; + + buf = (char *)__get_free_page(GFP_KERNEL); + + n = snprintf(buf, PAGE_SIZE, "Available crash types:\n"); + for (i = 0; i < ARRAY_SIZE(cp_type); i++) + n += snprintf(buf + n, PAGE_SIZE - n, "%s\n", cp_type[i]); + buf[n] = '\0'; + + out = simple_read_from_buffer(user_buf, count, off, + buf, n); + free_page((unsigned long) buf); + + return out; +} + +static int lkdtm_debugfs_open(struct inode *inode, struct file *file) +{ + return 0; +} + + +static ssize_t int_hardware_entry(struct file *f, const char __user *buf, + size_t count, loff_t *off) +{ + return do_register_entry(INT_HARDWARE_ENTRY, f, buf, count, off); +} + +static ssize_t int_hw_irq_en(struct file *f, const char __user *buf, + size_t count, loff_t *off) +{ + return do_register_entry(INT_HW_IRQ_EN, f, buf, count, off); +} + +static ssize_t int_tasklet_entry(struct file *f, const char __user *buf, + size_t count, loff_t *off) +{ + return do_register_entry(INT_TASKLET_ENTRY, f, buf, count, off); +} + +static ssize_t fs_devrw_entry(struct file *f, const char __user *buf, + size_t count, loff_t *off) +{ + return do_register_entry(FS_DEVRW, f, buf, count, off); +} + +static ssize_t mem_swapout_entry(struct file *f, const char __user *buf, + size_t count, loff_t *off) +{ + return do_register_entry(MEM_SWAPOUT, f, buf, count, off); +} + +static ssize_t timeradd_entry(struct file *f, const char __user *buf, + size_t count, loff_t *off) +{ + return do_register_entry(TIMERADD, f, buf, count, off); +} + +static ssize_t scsi_dispatch_cmd_entry(struct file *f, + const char __user *buf, size_t count, loff_t *off) +{ + return do_register_entry(SCSI_DISPATCH_CMD, f, buf, count, off); +} + +static ssize_t ide_core_cp_entry(struct file *f, const char __user *buf, + size_t count, loff_t *off) +{ + return do_register_entry(IDE_CORE_CP, f, buf, count, off); +} + +/* Special entry to just crash directly. Available without KPROBEs */ +static ssize_t direct_entry(struct file *f, const char __user *user_buf, + size_t count, loff_t *off) +{ + enum ctype type; + char *buf; + + if (count >= PAGE_SIZE) + return -EINVAL; + if (count < 1) + return -EINVAL; + + buf = (char *)__get_free_page(GFP_KERNEL); + if (!buf) + return -ENOMEM; + if (copy_from_user(buf, user_buf, count)) { + free_page((unsigned long) buf); + return -EFAULT; + } + /* NULL-terminate and remove enter */ + buf[count] = '\0'; + strim(buf); + + type = parse_cp_type(buf, count); + free_page((unsigned long) buf); + if (type == NONE) + return -EINVAL; + + printk(KERN_INFO "lkdtm: Performing direct entry %s\n", + cp_type_to_str(type)); + lkdtm_do_action(type); + *off += count; + + return count; +} + +struct crash_entry { + const char *name; + const struct file_operations fops; +}; + +static const struct crash_entry crash_entries[] = { + {"DIRECT", {.read = lkdtm_debugfs_read, + .open = lkdtm_debugfs_open, + .write = direct_entry} }, + {"INT_HARDWARE_ENTRY", {.read = lkdtm_debugfs_read, + .open = lkdtm_debugfs_open, + .write = int_hardware_entry} }, + {"INT_HW_IRQ_EN", {.read = lkdtm_debugfs_read, + .open = lkdtm_debugfs_open, + .write = int_hw_irq_en} }, + {"INT_TASKLET_ENTRY", {.read = lkdtm_debugfs_read, + .open = lkdtm_debugfs_open, + .write = int_tasklet_entry} }, + {"FS_DEVRW", {.read = lkdtm_debugfs_read, + .open = lkdtm_debugfs_open, + .write = fs_devrw_entry} }, + {"MEM_SWAPOUT", {.read = lkdtm_debugfs_read, + .open = lkdtm_debugfs_open, + .write = mem_swapout_entry} }, + {"TIMERADD", {.read = lkdtm_debugfs_read, + .open = lkdtm_debugfs_open, + .write = timeradd_entry} }, + {"SCSI_DISPATCH_CMD", {.read = lkdtm_debugfs_read, + .open = lkdtm_debugfs_open, + .write = scsi_dispatch_cmd_entry} }, + {"IDE_CORE_CP", {.read = lkdtm_debugfs_read, + .open = lkdtm_debugfs_open, + .write = ide_core_cp_entry} }, +}; + +static struct dentry *lkdtm_debugfs_root; + +static int __init lkdtm_module_init(void) +{ + int ret = -EINVAL; + int n_debugfs_entries = 1; /* Assume only the direct entry */ + int i; + + /* Register debugfs interface */ + lkdtm_debugfs_root = debugfs_create_dir("provoke-crash", NULL); + if (!lkdtm_debugfs_root) { + printk(KERN_ERR "lkdtm: creating root dir failed\n"); + return -ENODEV; + } + +#ifdef CONFIG_KPROBES + n_debugfs_entries = ARRAY_SIZE(crash_entries); +#endif + + for (i = 0; i < n_debugfs_entries; i++) { + const struct crash_entry *cur = &crash_entries[i]; + struct dentry *de; + + de = debugfs_create_file(cur->name, 0644, lkdtm_debugfs_root, + NULL, &cur->fops); + if (de == NULL) { + printk(KERN_ERR "lkdtm: could not create %s\n", + cur->name); + goto out_err; + } + } + + if (lkdtm_parse_commandline() == -EINVAL) { + printk(KERN_INFO "lkdtm: Invalid command\n"); + goto out_err; + } + + if (cpoint != INVALID && cptype != NONE) { + ret = lkdtm_register_cpoint(cpoint); + if (ret < 0) { + printk(KERN_INFO "lkdtm: Invalid crash point %d\n", + cpoint); + goto out_err; + } + printk(KERN_INFO "lkdtm: Crash point %s of type %s registered\n", + cpoint_name, cpoint_type); + } else { + printk(KERN_INFO "lkdtm: No crash points registered, enable through debugfs\n"); } - printk(KERN_INFO "lkdtm : Crash point %s of type %s registered\n", - cpoint_name, cpoint_type); return 0; + +out_err: + debugfs_remove_recursive(lkdtm_debugfs_root); + return ret; } static void __exit lkdtm_module_exit(void) { - unregister_jprobe(&lkdtm); - printk(KERN_INFO "lkdtm : Crash point unregistered\n"); + debugfs_remove_recursive(lkdtm_debugfs_root); + + unregister_jprobe(&lkdtm); + printk(KERN_INFO "lkdtm: Crash point unregistered\n"); } module_init(lkdtm_module_init); diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index 5e3407d997b2..b520ec1f33c5 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -864,8 +864,7 @@ config DEBUG_FORCE_WEAK_PER_CPU config LKDTM tristate "Linux Kernel Dump Test Tool Module" - depends on DEBUG_KERNEL - depends on KPROBES + depends on DEBUG_FS depends on BLOCK default n help @@ -876,7 +875,7 @@ config LKDTM called lkdtm. Documentation on how to use the module can be found in - drivers/misc/lkdtm.c + Documentation/fault-injection/provoke-crashes.txt config FAULT_INJECTION bool "Fault-injection framework" -- cgit v1.2.3 From a069c266ae5fdfbf5b4aecf2c672413aa33b2504 Mon Sep 17 00:00:00 2001 From: Don Mullis Date: Fri, 5 Mar 2010 13:43:16 -0800 Subject: lib: build list_sort() only if needed Build list_sort() only for configs that need it -- those that don't save ~581 bytes (i386). Signed-off-by: Don Mullis Cc: Dave Airlie Cc: Andi Kleen Cc: Dave Chinner Cc: Artem Bityutskiy Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/gpu/drm/Kconfig | 1 + fs/ubifs/Kconfig | 1 + lib/Kconfig | 3 +++ lib/Makefile | 3 ++- 4 files changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 305c59003963..3d2ab03f1296 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -9,6 +9,7 @@ menuconfig DRM depends on (AGP || AGP=n) && PCI && !EMULATED_CMPXCHG && MMU select I2C select I2C_ALGOBIT + select LIST_SORT help Kernel-level support for the Direct Rendering Infrastructure (DRI) introduced in XFree86 4.0. If you say Y here, you need to select diff --git a/fs/ubifs/Kconfig b/fs/ubifs/Kconfig index 830e3f76f442..430c69f39842 100644 --- a/fs/ubifs/Kconfig +++ b/fs/ubifs/Kconfig @@ -7,6 +7,7 @@ config UBIFS_FS select CRYPTO if UBIFS_FS_ZLIB select CRYPTO_LZO if UBIFS_FS_LZO select CRYPTO_DEFLATE if UBIFS_FS_ZLIB + select LIST_SORT depends on MTD_UBI help UBIFS is a file system for flash devices which works on top of UBI. diff --git a/lib/Kconfig b/lib/Kconfig index 97b136ff117e..8034c46327cb 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -160,6 +160,9 @@ config TEXTSEARCH_BM config TEXTSEARCH_FSM tristate +config LIST_SORT + boolean + config HAS_IOMEM boolean depends on !NO_IOMEM diff --git a/lib/Makefile b/lib/Makefile index 3b0b4a696db9..e39c361b0be3 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -21,7 +21,7 @@ lib-y += kobject.o kref.o klist.o obj-y += bcd.o div64.o sort.o parser.o halfmd4.o debug_locks.o random32.o \ bust_spinlocks.o hexdump.o kasprintf.o bitmap.o scatterlist.o \ - string_helpers.o gcd.o list_sort.o + string_helpers.o gcd.o ifeq ($(CONFIG_DEBUG_KOBJECT),y) CFLAGS_kobject.o += -DDEBUG @@ -40,6 +40,7 @@ lib-$(CONFIG_GENERIC_FIND_FIRST_BIT) += find_next_bit.o lib-$(CONFIG_GENERIC_FIND_NEXT_BIT) += find_next_bit.o obj-$(CONFIG_GENERIC_FIND_LAST_BIT) += find_last_bit.o obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o +obj-$(CONFIG_LIST_SORT) += list_sort.o obj-$(CONFIG_LOCK_KERNEL) += kernel_lock.o obj-$(CONFIG_DEBUG_PREEMPT) += smp_processor_id.o obj-$(CONFIG_DEBUG_LIST) += list_debug.o -- cgit v1.2.3 From 03cd8f7ebe0cbef5ca7eed349774085e92a3d726 Mon Sep 17 00:00:00 2001 From: Maxim Levitsky Date: Fri, 5 Mar 2010 13:43:20 -0800 Subject: ricoh_mmc: port from driver to pci quirk This patch solves nasty problem original driver has. Original goal of the ricoh_mmc was to disable this device because then, mmc cards can be read using standard SDHCI controller, thus avoiding writing of yet another driver. However, the act of disablement, makes other pci functions that belong to this controller (xD and memstick) shift up one level, thus pci core has now wrong idea about these devices. To fix this issue, this patch moves the driver into the pci quirk section, thus it is executes before the pci is enumerated, and therefore solving that issue, also same sequence of commands is performed on resume for same reasons. Also regardless of the above, this way is cleaner. You still need to set CONFIG_MMC_RICOH_MMC to enable this quirk Signed-off-by: Maxim Levitsky Acked-by: Philip Langdale Acked-by: Wolfram Sang Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/Kconfig | 10 +- drivers/mmc/host/Makefile | 1 - drivers/mmc/host/ricoh_mmc.c | 262 ------------------------------------------- drivers/pci/quirks.c | 85 ++++++++++++++ 4 files changed, 88 insertions(+), 270 deletions(-) delete mode 100644 drivers/mmc/host/ricoh_mmc.c (limited to 'drivers') diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index ce1d28884e29..6bc3ecb1f247 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -69,20 +69,16 @@ config MMC_SDHCI_PCI If unsure, say N. config MMC_RICOH_MMC - tristate "Ricoh MMC Controller Disabler (EXPERIMENTAL)" + bool "Ricoh MMC Controller Disabler (EXPERIMENTAL)" depends on MMC_SDHCI_PCI help - This selects the disabler for the Ricoh MMC Controller. This + This adds a pci quirk to disable Ricoh MMC Controller. This proprietary controller is unnecessary because the SDHCI driver supports MMC cards on the SD controller, but if it is not disabled, it will steal the MMC cards away - rendering them - useless. It is safe to select this driver even if you don't + useless. It is safe to select this even if you don't have a Ricoh based card reader. - - To compile this driver as a module, choose M here: - the module will be called ricoh_mmc. - If unsure, say Y. config MMC_SDHCI_OF diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 3d253dd4240f..f4803977dfce 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -12,7 +12,6 @@ obj-$(CONFIG_MMC_IMX) += imxmmc.o obj-$(CONFIG_MMC_MXC) += mxcmmc.o obj-$(CONFIG_MMC_SDHCI) += sdhci.o obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o -obj-$(CONFIG_MMC_RICOH_MMC) += ricoh_mmc.o obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o obj-$(CONFIG_MMC_WBSD) += wbsd.o diff --git a/drivers/mmc/host/ricoh_mmc.c b/drivers/mmc/host/ricoh_mmc.c deleted file mode 100644 index f62790513322..000000000000 --- a/drivers/mmc/host/ricoh_mmc.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - * ricoh_mmc.c - Dummy driver to disable the Rioch MMC controller. - * - * Copyright (C) 2007 Philip Langdale, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or (at - * your option) any later version. - */ - -/* - * This is a conceptually ridiculous driver, but it is required by the way - * the Ricoh multi-function chips (R5CXXX) work. These chips implement - * the four main memory card controllers (SD, MMC, MS, xD) and one or both - * of cardbus or firewire. It happens that they implement SD and MMC - * support as separate controllers (and PCI functions). The linux SDHCI - * driver supports MMC cards but the chip detects MMC cards in hardware - * and directs them to the MMC controller - so the SDHCI driver never sees - * them. To get around this, we must disable the useless MMC controller. - * At that point, the SDHCI controller will start seeing them. As a bonus, - * a detection event occurs immediately, even if the MMC card is already - * in the reader. - * - * It seems to be the case that the relevant PCI registers to deactivate the - * MMC controller live on PCI function 0, which might be the cardbus controller - * or the firewire controller, depending on the particular chip in question. As - * such, it makes what this driver has to do unavoidably ugly. Such is life. - */ - -#include - -#define DRIVER_NAME "ricoh-mmc" - -static const struct pci_device_id pci_ids[] __devinitdata = { - { - .vendor = PCI_VENDOR_ID_RICOH, - .device = PCI_DEVICE_ID_RICOH_R5C843, - .subvendor = PCI_ANY_ID, - .subdevice = PCI_ANY_ID, - }, - { /* end: all zeroes */ }, -}; - -MODULE_DEVICE_TABLE(pci, pci_ids); - -static int ricoh_mmc_disable(struct pci_dev *fw_dev) -{ - u8 write_enable; - u8 write_target; - u8 disable; - - if (fw_dev->device == PCI_DEVICE_ID_RICOH_RL5C476) { - /* via RL5C476 */ - - pci_read_config_byte(fw_dev, 0xB7, &disable); - if (disable & 0x02) { - printk(KERN_INFO DRIVER_NAME - ": Controller already disabled. " \ - "Nothing to do.\n"); - return -ENODEV; - } - - pci_read_config_byte(fw_dev, 0x8E, &write_enable); - pci_write_config_byte(fw_dev, 0x8E, 0xAA); - pci_read_config_byte(fw_dev, 0x8D, &write_target); - pci_write_config_byte(fw_dev, 0x8D, 0xB7); - pci_write_config_byte(fw_dev, 0xB7, disable | 0x02); - pci_write_config_byte(fw_dev, 0x8E, write_enable); - pci_write_config_byte(fw_dev, 0x8D, write_target); - } else { - /* via R5C832 */ - - pci_read_config_byte(fw_dev, 0xCB, &disable); - if (disable & 0x02) { - printk(KERN_INFO DRIVER_NAME - ": Controller already disabled. " \ - "Nothing to do.\n"); - return -ENODEV; - } - - pci_read_config_byte(fw_dev, 0xCA, &write_enable); - pci_write_config_byte(fw_dev, 0xCA, 0x57); - pci_write_config_byte(fw_dev, 0xCB, disable | 0x02); - pci_write_config_byte(fw_dev, 0xCA, write_enable); - } - - printk(KERN_INFO DRIVER_NAME - ": Controller is now disabled.\n"); - - return 0; -} - -static int ricoh_mmc_enable(struct pci_dev *fw_dev) -{ - u8 write_enable; - u8 write_target; - u8 disable; - - if (fw_dev->device == PCI_DEVICE_ID_RICOH_RL5C476) { - /* via RL5C476 */ - - pci_read_config_byte(fw_dev, 0x8E, &write_enable); - pci_write_config_byte(fw_dev, 0x8E, 0xAA); - pci_read_config_byte(fw_dev, 0x8D, &write_target); - pci_write_config_byte(fw_dev, 0x8D, 0xB7); - pci_read_config_byte(fw_dev, 0xB7, &disable); - pci_write_config_byte(fw_dev, 0xB7, disable & ~0x02); - pci_write_config_byte(fw_dev, 0x8E, write_enable); - pci_write_config_byte(fw_dev, 0x8D, write_target); - } else { - /* via R5C832 */ - - pci_read_config_byte(fw_dev, 0xCA, &write_enable); - pci_read_config_byte(fw_dev, 0xCB, &disable); - pci_write_config_byte(fw_dev, 0xCA, 0x57); - pci_write_config_byte(fw_dev, 0xCB, disable & ~0x02); - pci_write_config_byte(fw_dev, 0xCA, write_enable); - } - - printk(KERN_INFO DRIVER_NAME - ": Controller is now re-enabled.\n"); - - return 0; -} - -static int __devinit ricoh_mmc_probe(struct pci_dev *pdev, - const struct pci_device_id *ent) -{ - u8 rev; - u8 ctrlfound = 0; - - struct pci_dev *fw_dev = NULL; - - BUG_ON(pdev == NULL); - BUG_ON(ent == NULL); - - pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev); - - printk(KERN_INFO DRIVER_NAME - ": Ricoh MMC controller found at %s [%04x:%04x] (rev %x)\n", - pci_name(pdev), (int)pdev->vendor, (int)pdev->device, - (int)rev); - - while ((fw_dev = - pci_get_device(PCI_VENDOR_ID_RICOH, - PCI_DEVICE_ID_RICOH_RL5C476, fw_dev))) { - if (PCI_SLOT(pdev->devfn) == PCI_SLOT(fw_dev->devfn) && - PCI_FUNC(fw_dev->devfn) == 0 && - pdev->bus == fw_dev->bus) { - if (ricoh_mmc_disable(fw_dev) != 0) - return -ENODEV; - - pci_set_drvdata(pdev, fw_dev); - - ++ctrlfound; - break; - } - } - - fw_dev = NULL; - - while (!ctrlfound && - (fw_dev = pci_get_device(PCI_VENDOR_ID_RICOH, - PCI_DEVICE_ID_RICOH_R5C832, fw_dev))) { - if (PCI_SLOT(pdev->devfn) == PCI_SLOT(fw_dev->devfn) && - PCI_FUNC(fw_dev->devfn) == 0 && - pdev->bus == fw_dev->bus) { - if (ricoh_mmc_disable(fw_dev) != 0) - return -ENODEV; - - pci_set_drvdata(pdev, fw_dev); - - ++ctrlfound; - } - } - - if (!ctrlfound) { - printk(KERN_WARNING DRIVER_NAME - ": Main Ricoh function not found. Cannot disable controller.\n"); - return -ENODEV; - } - - return 0; -} - -static void __devexit ricoh_mmc_remove(struct pci_dev *pdev) -{ - struct pci_dev *fw_dev = NULL; - - fw_dev = pci_get_drvdata(pdev); - BUG_ON(fw_dev == NULL); - - ricoh_mmc_enable(fw_dev); - - pci_set_drvdata(pdev, NULL); -} - -static int ricoh_mmc_suspend_late(struct pci_dev *pdev, pm_message_t state) -{ - struct pci_dev *fw_dev = NULL; - - fw_dev = pci_get_drvdata(pdev); - BUG_ON(fw_dev == NULL); - - printk(KERN_INFO DRIVER_NAME ": Suspending.\n"); - - ricoh_mmc_enable(fw_dev); - - return 0; -} - -static int ricoh_mmc_resume_early(struct pci_dev *pdev) -{ - struct pci_dev *fw_dev = NULL; - - fw_dev = pci_get_drvdata(pdev); - BUG_ON(fw_dev == NULL); - - printk(KERN_INFO DRIVER_NAME ": Resuming.\n"); - - ricoh_mmc_disable(fw_dev); - - return 0; -} - -static struct pci_driver ricoh_mmc_driver = { - .name = DRIVER_NAME, - .id_table = pci_ids, - .probe = ricoh_mmc_probe, - .remove = __devexit_p(ricoh_mmc_remove), - .suspend_late = ricoh_mmc_suspend_late, - .resume_early = ricoh_mmc_resume_early, -}; - -/*****************************************************************************\ - * * - * Driver init/exit * - * * -\*****************************************************************************/ - -static int __init ricoh_mmc_drv_init(void) -{ - printk(KERN_INFO DRIVER_NAME - ": Ricoh MMC Controller disabling driver\n"); - printk(KERN_INFO DRIVER_NAME ": Copyright(c) Philip Langdale\n"); - - return pci_register_driver(&ricoh_mmc_driver); -} - -static void __exit ricoh_mmc_drv_exit(void) -{ - pci_unregister_driver(&ricoh_mmc_driver); -} - -module_init(ricoh_mmc_drv_init); -module_exit(ricoh_mmc_drv_exit); - -MODULE_AUTHOR("Philip Langdale "); -MODULE_DESCRIPTION("Ricoh MMC Controller disabling driver"); -MODULE_LICENSE("GPL"); - diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 039e87b71442..81d19d5683ac 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2533,6 +2533,91 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1518, quirk_i82576_sriov); #endif /* CONFIG_PCI_IOV */ +/* + * This is a quirk for the Ricoh MMC controller found as a part of + * some mulifunction chips. + + * This is very similiar and based on the ricoh_mmc driver written by + * Philip Langdale. Thank you for these magic sequences. + * + * These chips implement the four main memory card controllers (SD, MMC, MS, xD) + * and one or both of cardbus or firewire. + * + * It happens that they implement SD and MMC + * support as separate controllers (and PCI functions). The linux SDHCI + * driver supports MMC cards but the chip detects MMC cards in hardware + * and directs them to the MMC controller - so the SDHCI driver never sees + * them. + * + * To get around this, we must disable the useless MMC controller. + * At that point, the SDHCI controller will start seeing them + * It seems to be the case that the relevant PCI registers to deactivate the + * MMC controller live on PCI function 0, which might be the cardbus controller + * or the firewire controller, depending on the particular chip in question + * + * This has to be done early, because as soon as we disable the MMC controller + * other pci functions shift up one level, e.g. function #2 becomes function + * #1, and this will confuse the pci core. + */ + +#ifdef CONFIG_MMC_RICOH_MMC +static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) +{ + /* disable via cardbus interface */ + u8 write_enable; + u8 write_target; + u8 disable; + + /* disable must be done via function #0 */ + if (PCI_FUNC(dev->devfn)) + return; + + pci_read_config_byte(dev, 0xB7, &disable); + if (disable & 0x02) + return; + + pci_read_config_byte(dev, 0x8E, &write_enable); + pci_write_config_byte(dev, 0x8E, 0xAA); + pci_read_config_byte(dev, 0x8D, &write_target); + pci_write_config_byte(dev, 0x8D, 0xB7); + pci_write_config_byte(dev, 0xB7, disable | 0x02); + pci_write_config_byte(dev, 0x8E, write_enable); + pci_write_config_byte(dev, 0x8D, write_target); + + dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); + dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); + +static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) +{ + /* disable via firewire interface */ + u8 write_enable; + u8 disable; + + /* disable must be done via function #0 */ + if (PCI_FUNC(dev->devfn)) + return; + + pci_read_config_byte(dev, 0xCB, &disable); + + if (disable & 0x02) + return; + + pci_read_config_byte(dev, 0xCA, &write_enable); + pci_write_config_byte(dev, 0xCA, 0x57); + pci_write_config_byte(dev, 0xCB, disable | 0x02); + pci_write_config_byte(dev, 0xCA, write_enable); + + dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); + dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); +#endif /*CONFIG_MMC_RICOH_MMC*/ + + static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) { -- cgit v1.2.3 From 132f10746c2bb2e4bcfc3fadff12f390ace2d183 Mon Sep 17 00:00:00 2001 From: Vipin Bhandari Date: Fri, 5 Mar 2010 13:43:21 -0800 Subject: davinci: MMC: add support for 8bit MMC cards Add support for 8bit MMC cards. The controller data width is configurable depending on the wires setting in the platform data structure. MMC 8bit is tested on OMAPL137 and MMC 4bit is tested on OMAPL138 EVM. Signed-off-by: Vipin Bhandari Cc: David Brownell Cc: Chaithrika U S Cc: Sudhakar Rajashekhara Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/davinci_mmc.c | 45 ++++++++++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c index dd45e7c3517e..3bd0ba294e9d 100644 --- a/drivers/mmc/host/davinci_mmc.c +++ b/drivers/mmc/host/davinci_mmc.c @@ -73,6 +73,7 @@ /* DAVINCI_MMCCTL definitions */ #define MMCCTL_DATRST (1 << 0) #define MMCCTL_CMDRST (1 << 1) +#define MMCCTL_WIDTH_8_BIT (1 << 8) #define MMCCTL_WIDTH_4_BIT (1 << 2) #define MMCCTL_DATEG_DISABLED (0 << 6) #define MMCCTL_DATEG_RISING (1 << 6) @@ -791,22 +792,42 @@ static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { - unsigned int mmc_pclk = 0; struct mmc_davinci_host *host = mmc_priv(mmc); - mmc_pclk = host->mmc_input_clk; dev_dbg(mmc_dev(host->mmc), "clock %dHz busmode %d powermode %d Vdd %04x\n", ios->clock, ios->bus_mode, ios->power_mode, ios->vdd); - if (ios->bus_width == MMC_BUS_WIDTH_4) { - dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); - writel(readl(host->base + DAVINCI_MMCCTL) | MMCCTL_WIDTH_4_BIT, - host->base + DAVINCI_MMCCTL); - } else { - dev_dbg(mmc_dev(host->mmc), "Disabling 4 bit mode\n"); - writel(readl(host->base + DAVINCI_MMCCTL) & ~MMCCTL_WIDTH_4_BIT, + + switch (ios->bus_width) { + case MMC_BUS_WIDTH_8: + dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); + writel((readl(host->base + DAVINCI_MMCCTL) & + ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT, host->base + DAVINCI_MMCCTL); + break; + case MMC_BUS_WIDTH_4: + dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); + if (host->version == MMC_CTLR_VERSION_2) + writel((readl(host->base + DAVINCI_MMCCTL) & + ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT, + host->base + DAVINCI_MMCCTL); + else + writel(readl(host->base + DAVINCI_MMCCTL) | + MMCCTL_WIDTH_4_BIT, + host->base + DAVINCI_MMCCTL); + break; + case MMC_BUS_WIDTH_1: + dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); + if (host->version == MMC_CTLR_VERSION_2) + writel(readl(host->base + DAVINCI_MMCCTL) & + ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT), + host->base + DAVINCI_MMCCTL); + else + writel(readl(host->base + DAVINCI_MMCCTL) & + ~MMCCTL_WIDTH_4_BIT, + host->base + DAVINCI_MMCCTL); + break; } calculate_clk_divider(mmc, ios); @@ -1189,10 +1210,14 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev) /* REVISIT: someday, support IRQ-driven card detection. */ mmc->caps |= MMC_CAP_NEEDS_POLL; + mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; - if (!pdata || pdata->wires == 4 || pdata->wires == 0) + if (pdata && (pdata->wires == 4 || pdata->wires == 0)) mmc->caps |= MMC_CAP_4_BIT_DATA; + if (pdata && (pdata->wires == 8)) + mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); + host->version = pdata->version; mmc->ops = &mmc_davinci_ops; -- cgit v1.2.3 From 09591dd3183d5aeae515bd5fcba718ec49e11ece Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 5 Mar 2010 13:43:22 -0800 Subject: mmc: Atmel host kconfig cleanup for everyone else This prevents those without an Atmel chip having a line in kernel configuration which says "Atmel SD/MMC Driver" without any option. Signed-off-by: Jonathan Cameron Signed-off-by: Nicolas Ferre Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 6bc3ecb1f247..25a4b7f3e15f 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -189,6 +189,7 @@ config MMC_AU1X choice prompt "Atmel SD/MMC Driver" + depends on AVR32 || ARCH_AT91 default MMC_ATMELMCI if AVR32 help Choose which driver to use for the Atmel MCI Silicon -- cgit v1.2.3 From c744d988729db9be37d1c877d143cfe63941c25c Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 5 Mar 2010 13:43:23 -0800 Subject: mmc: bfin_sdh: fix unused sg warning on BF51x/BF52x systems The local sg variable is only used with BF54x code. Signed-off-by: Mike Frysinger Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/bfin_sdh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/host/bfin_sdh.c b/drivers/mmc/host/bfin_sdh.c index 3343a57355cc..f218a9964552 100644 --- a/drivers/mmc/host/bfin_sdh.c +++ b/drivers/mmc/host/bfin_sdh.c @@ -115,7 +115,6 @@ static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data) unsigned int length; unsigned int data_ctl; unsigned int dma_cfg; - struct scatterlist *sg; dev_dbg(mmc_dev(host->mmc), "%s enter flags: 0x%x\n", __func__, data->flags); host->data = data; @@ -151,6 +150,7 @@ static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data) #if defined(CONFIG_BF54x) dma_cfg |= DMAFLOW_ARRAY | NDSIZE_5 | RESTART | WDSIZE_32 | DMAEN; { + struct scatterlist *sg; int i; for_each_sg(data->sg, sg, host->dma_len, i) { host->sg_cpu[i].start_addr = sg_dma_address(sg); -- cgit v1.2.3 From 05dabcc4a51eab7342b2220f0121b4f4a5109386 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 5 Mar 2010 13:43:24 -0800 Subject: mmc: bfin_sdh: drop redundant MMC depend string The host/Kconfig file is only included when MMC is selected. Signed-off-by: Mike Frysinger Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 25a4b7f3e15f..7b431bbab7f1 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -396,7 +396,7 @@ config MMC_VIA_SDMMC config SDH_BFIN tristate "Blackfin Secure Digital Host support" - depends on MMC && ((BF54x && !BF544) || (BF51x && !BF512)) + depends on (BF54x && !BF544) || (BF51x && !BF512) help If you say yes here you will get support for the Blackfin on-chip Secure Digital Host interface. This includes support for MMC and -- cgit v1.2.3 From 729adf1b5f4562f67fe8bf6c1df97edc1128fac7 Mon Sep 17 00:00:00 2001 From: Cliff Cai Date: Fri, 5 Mar 2010 13:43:25 -0800 Subject: mmc: bfin_sdh: set timeout based on actual card data The hardcoded value doesn't really work for all cards. Signed-off-by: Cliff Cai Signed-off-by: Mike Frysinger Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/bfin_sdh.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/bfin_sdh.c b/drivers/mmc/host/bfin_sdh.c index f218a9964552..56f7b448b911 100644 --- a/drivers/mmc/host/bfin_sdh.c +++ b/drivers/mmc/host/bfin_sdh.c @@ -115,6 +115,7 @@ static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data) unsigned int length; unsigned int data_ctl; unsigned int dma_cfg; + unsigned int cycle_ns, timeout; dev_dbg(mmc_dev(host->mmc), "%s enter flags: 0x%x\n", __func__, data->flags); host->data = data; @@ -135,8 +136,11 @@ static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data) data_ctl |= ((ffs(data->blksz) - 1) << 4); bfin_write_SDH_DATA_CTL(data_ctl); - - bfin_write_SDH_DATA_TIMER(0xFFFF); + /* the time of a host clock period in ns */ + cycle_ns = 1000000000 / (get_sclk() / (2 * (host->clk_div + 1))); + timeout = data->timeout_ns / cycle_ns; + timeout += data->timeout_clks; + bfin_write_SDH_DATA_TIMER(timeout); SSYNC(); if (data->flags & MMC_DATA_READ) { -- cgit v1.2.3 From 3fb7fb4a01d09f81d1daaf65e52d929734bd691f Mon Sep 17 00:00:00 2001 From: Bing Zhao Date: Fri, 5 Mar 2010 13:43:25 -0800 Subject: sdio: add quirk to clamp byte mode transfer Some SDIO cards expect byte transfers not to exceed the configured block transfer size. Add a quirk to that effect. Patches to make use of this quirk will be sent separately. Signed-off-by: Bing Zhao Signed-off-by: Nicolas Pitre Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/core/sdio_io.c | 7 ++++++- include/linux/mmc/card.h | 7 +++++++ 2 files changed, 13 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/core/sdio_io.c b/drivers/mmc/core/sdio_io.c index f9aa8a7deffa..87c618904ee2 100644 --- a/drivers/mmc/core/sdio_io.c +++ b/drivers/mmc/core/sdio_io.c @@ -189,7 +189,12 @@ static inline unsigned int sdio_max_byte_size(struct sdio_func *func) { unsigned mval = min(func->card->host->max_seg_size, func->card->host->max_blk_size); - mval = min(mval, func->max_blksize); + + if (mmc_blksz_for_byte_mode(func->card)) + mval = min(mval, func->cur_blksize); + else + mval = min(mval, func->max_blksize); + return min(mval, 512u); /* maximum size for byte mode */ } diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index 2ee22e8af110..d02d2c6e0cfe 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -99,6 +99,8 @@ struct mmc_card { #define MMC_STATE_BLOCKADDR (1<<3) /* card uses block-addressing */ unsigned int quirks; /* card quirks */ #define MMC_QUIRK_LENIENT_FN0 (1<<0) /* allow SDIO FN0 writes outside of the VS CCCR range */ +#define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1) /* use func->cur_blksize */ + /* for byte mode */ u32 raw_cid[4]; /* raw card CID */ u32 raw_csd[4]; /* raw card CSD */ @@ -139,6 +141,11 @@ static inline int mmc_card_lenient_fn0(const struct mmc_card *c) return c->quirks & MMC_QUIRK_LENIENT_FN0; } +static inline int mmc_blksz_for_byte_mode(const struct mmc_card *c) +{ + return c->quirks & MMC_QUIRK_BLKSZ_FOR_BYTE_MODE; +} + #define mmc_card_name(c) ((c)->cid.prod_name) #define mmc_card_id(c) (dev_name(&(c)->dev)) -- cgit v1.2.3 From 118cd17d4137f34c747c32765c1cb4d3910c04d4 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 5 Mar 2010 13:43:26 -0800 Subject: sdhci: add adma descriptor set call The code to write the ADMA descriptor into memory is repeated several times throughout sdhci_adma_table_pre, and thus should be moved into a common function. This will also be useful if the patch to make the write more efficient is accepted. Signed-off-by: Ben Dooks Cc: Pierre Ossman Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/sdhci.c | 50 +++++++++++++++++++----------------------------- 1 file changed, 20 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index c279fbc4c2e5..fcdd00785033 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -376,6 +376,20 @@ static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) local_irq_restore(*flags); } +static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) +{ + desc[7] = (addr >> 24) & 0xff; + desc[6] = (addr >> 16) & 0xff; + desc[5] = (addr >> 8) & 0xff; + desc[4] = (addr >> 0) & 0xff; + + desc[3] = (len >> 8) & 0xff; + desc[2] = (len >> 0) & 0xff; + + desc[0] = cmd & 0xff; + desc[1] = cmd >> 8; +} + static int sdhci_adma_table_pre(struct sdhci_host *host, struct mmc_data *data) { @@ -443,19 +457,11 @@ static int sdhci_adma_table_pre(struct sdhci_host *host, sdhci_kunmap_atomic(buffer, &flags); } - desc[7] = (align_addr >> 24) & 0xff; - desc[6] = (align_addr >> 16) & 0xff; - desc[5] = (align_addr >> 8) & 0xff; - desc[4] = (align_addr >> 0) & 0xff; + /* tran, valid */ + sdhci_set_adma_desc(desc, align_addr, offset, 0x21); BUG_ON(offset > 65536); - desc[3] = (offset >> 8) & 0xff; - desc[2] = (offset >> 0) & 0xff; - - desc[1] = 0x00; - desc[0] = 0x21; /* tran, valid */ - align += 4; align_addr += 4; @@ -465,19 +471,10 @@ static int sdhci_adma_table_pre(struct sdhci_host *host, len -= offset; } - desc[7] = (addr >> 24) & 0xff; - desc[6] = (addr >> 16) & 0xff; - desc[5] = (addr >> 8) & 0xff; - desc[4] = (addr >> 0) & 0xff; - BUG_ON(len > 65536); - desc[3] = (len >> 8) & 0xff; - desc[2] = (len >> 0) & 0xff; - - desc[1] = 0x00; - desc[0] = 0x21; /* tran, valid */ - + /* tran, valid */ + sdhci_set_adma_desc(desc, addr, len, 0x21); desc += 8; /* @@ -490,16 +487,9 @@ static int sdhci_adma_table_pre(struct sdhci_host *host, /* * Add a terminating entry. */ - desc[7] = 0; - desc[6] = 0; - desc[5] = 0; - desc[4] = 0; - - desc[3] = 0; - desc[2] = 0; - desc[1] = 0x00; - desc[0] = 0x03; /* nop, end, valid */ + /* nop, end, valid */ + sdhci_set_adma_desc(desc, 0, 0, 0x3); /* * Resync align buffer as we might have changed it. -- cgit v1.2.3 From 9e506f35b1dc327c448d4791bc098f07b9b2efe9 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 5 Mar 2010 13:43:29 -0800 Subject: sdhci: improve sdhci sdhci_set_adma_desc() code sdhci_set_adma_desc() is using byte-writes to write data in a specified order into memory. Change to using __le16 for the two byte and __le32 for the four byte cases and use the cpu_to_{le16,le32} to do the conversion before writing. This will reduce the size of the code and the number of writes as we no longer need to chop the data up before writing. As an example on ARM S3C64XX SoC, in little-endian configuration: 000000d4 : - d8: e1a0c423 lsr ip, r3, #8 - dc: e1a0ec21 lsr lr, r1, #24 - e0: e1a04821 lsr r4, r1, #16 - e4: e1a05421 lsr r5, r1, #8 - e8: e1a06442 asr r6, r2, #8 - ec: e5c0c001 strb ip, [r0, #1] - f0: e5c0e007 strb lr, [r0, #7] - f4: e5c04006 strb r4, [r0, #6] - f8: e5c05005 strb r5, [r0, #5] - fc: e5c01004 strb r1, [r0, #4] - 100: e5c06003 strb r6, [r0, #3] - 104: e5c02002 strb r2, [r0, #2] - 108: e5c03000 strb r3, [r0] + d4: e5801004 str r1, [r0, #4] + d8: e1c030b0 strh r3, [r0] + dc: e1c020b2 strh r2, [r0, #2] Signed-off-by: Ben Dooks Cc: Pierre Ossman Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/sdhci.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index fcdd00785033..6c866b43b03c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -378,16 +378,16 @@ static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) { - desc[7] = (addr >> 24) & 0xff; - desc[6] = (addr >> 16) & 0xff; - desc[5] = (addr >> 8) & 0xff; - desc[4] = (addr >> 0) & 0xff; + __le32 *dataddr = (__le32 __force *)(desc + 4); + __le16 *cmdlen = (__le16 __force *)desc; - desc[3] = (len >> 8) & 0xff; - desc[2] = (len >> 0) & 0xff; + /* SDHCI specification says ADMA descriptors should be 4 byte + * aligned, so using 16 or 32bit operations should be safe. */ - desc[0] = cmd & 0xff; - desc[1] = cmd >> 8; + cmdlen[0] = cpu_to_le16(cmd); + cmdlen[1] = cpu_to_le16(len); + + dataddr[0] = cpu_to_le32(addr); } static int sdhci_adma_table_pre(struct sdhci_host *host, -- cgit v1.2.3 From da68c4eb258cd9f3f0b8aeb7e46b8118bb6358b6 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Fri, 5 Mar 2010 13:43:31 -0800 Subject: sdio: introduce API for special power management features This patch series provides the core changes needed to allow SDIO cards to remain powered and active while the host system is suspended, and let them wake up the host system when needed. This is used to implement wake-on-lan with SDIO wireless cards at the moment. Patches to add that support to the libertas driver will be posted separately. This patch: Some SDIO cards have the ability to keep on running autonomously when the host system is suspended, and wake it up when needed. This however requires that the host controller preserve power to the card, and configure itself appropriately for wake-up. There is however 4 layers of abstractions involved: the host controller driver, the MMC core code, the SDIO card management code, and the actual SDIO function driver. To make things simple and manageable, host drivers must advertise their PM capabilities with a feature bitmask, then function drivers can query and set those features from their suspend method. Then each layer in the suspend call chain is expected to act upon those bits accordingly. [akpm@linux-foundation.org: fix typo in comment] Signed-off-by: Nicolas Pitre Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/core/core.c | 12 ++++++++--- drivers/mmc/core/sdio_io.c | 49 +++++++++++++++++++++++++++++++++++++++++++ include/linux/mmc/host.h | 5 +++++ include/linux/mmc/pm.h | 30 ++++++++++++++++++++++++++ include/linux/mmc/sdio_func.h | 5 +++++ 5 files changed, 98 insertions(+), 3 deletions(-) create mode 100644 include/linux/mmc/pm.h (limited to 'drivers') diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 30acd5265821..f4b97d3c3d0f 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -1151,6 +1151,9 @@ void mmc_stop_host(struct mmc_host *host) cancel_delayed_work(&host->detect); mmc_flush_scheduled_work(); + /* clear pm flags now and let card drivers set them as needed */ + host->pm_flags = 0; + mmc_bus_get(host); if (host->bus_ops && !host->bus_dead) { if (host->bus_ops->remove) @@ -1273,12 +1276,13 @@ int mmc_suspend_host(struct mmc_host *host, pm_message_t state) mmc_claim_host(host); mmc_detach_bus(host); mmc_release_host(host); + host->pm_flags = 0; err = 0; } } mmc_bus_put(host); - if (!err) + if (!err && !(host->pm_flags & MMC_PM_KEEP_POWER)) mmc_power_off(host); return err; @@ -1296,8 +1300,10 @@ int mmc_resume_host(struct mmc_host *host) mmc_bus_get(host); if (host->bus_ops && !host->bus_dead) { - mmc_power_up(host); - mmc_select_voltage(host, host->ocr); + if (!(host->pm_flags & MMC_PM_KEEP_POWER)) { + mmc_power_up(host); + mmc_select_voltage(host, host->ocr); + } BUG_ON(!host->bus_ops->resume); err = host->bus_ops->resume(host); if (err) { diff --git a/drivers/mmc/core/sdio_io.c b/drivers/mmc/core/sdio_io.c index 87c618904ee2..ff27c8c71355 100644 --- a/drivers/mmc/core/sdio_io.c +++ b/drivers/mmc/core/sdio_io.c @@ -640,3 +640,52 @@ void sdio_f0_writeb(struct sdio_func *func, unsigned char b, unsigned int addr, *err_ret = ret; } EXPORT_SYMBOL_GPL(sdio_f0_writeb); + +/** + * sdio_get_host_pm_caps - get host power management capabilities + * @func: SDIO function attached to host + * + * Returns a capability bitmask corresponding to power management + * features supported by the host controller that the card function + * might rely upon during a system suspend. The host doesn't need + * to be claimed, nor the function active, for this information to be + * obtained. + */ +mmc_pm_flag_t sdio_get_host_pm_caps(struct sdio_func *func) +{ + BUG_ON(!func); + BUG_ON(!func->card); + + return func->card->host->pm_caps; +} +EXPORT_SYMBOL_GPL(sdio_get_host_pm_caps); + +/** + * sdio_set_host_pm_flags - set wanted host power management capabilities + * @func: SDIO function attached to host + * + * Set a capability bitmask corresponding to wanted host controller + * power management features for the upcoming suspend state. + * This must be called, if needed, each time the suspend method of + * the function driver is called, and must contain only bits that + * were returned by sdio_get_host_pm_caps(). + * The host doesn't need to be claimed, nor the function active, + * for this information to be set. + */ +int sdio_set_host_pm_flags(struct sdio_func *func, mmc_pm_flag_t flags) +{ + struct mmc_host *host; + + BUG_ON(!func); + BUG_ON(!func->card); + + host = func->card->host; + + if (flags & ~host->pm_caps) + return -EINVAL; + + /* function suspend methods are serialized, hence no lock needed */ + host->pm_flags |= flags; + return 0; +} +EXPORT_SYMBOL_GPL(sdio_set_host_pm_flags); diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index eaf36364b7d4..43eaf5ca5848 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -14,6 +14,7 @@ #include #include +#include struct mmc_ios { unsigned int clock; /* clock rate */ @@ -152,6 +153,8 @@ struct mmc_host { #define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ + mmc_pm_flag_t pm_caps; /* supported pm features */ + /* host specific block data */ unsigned int max_seg_size; /* see blk_queue_max_segment_size */ unsigned short max_hw_segs; /* see blk_queue_max_hw_segments */ @@ -197,6 +200,8 @@ struct mmc_host { struct task_struct *sdio_irq_thread; atomic_t sdio_irq_thread_abort; + mmc_pm_flag_t pm_flags; /* requested pm features */ + #ifdef CONFIG_LEDS_TRIGGERS struct led_trigger *led; /* activity led */ #endif diff --git a/include/linux/mmc/pm.h b/include/linux/mmc/pm.h new file mode 100644 index 000000000000..d37aac49cf9a --- /dev/null +++ b/include/linux/mmc/pm.h @@ -0,0 +1,30 @@ +/* + * linux/include/linux/mmc/pm.h + * + * Author: Nicolas Pitre + * Copyright: (C) 2009 Marvell Technology Group Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef LINUX_MMC_PM_H +#define LINUX_MMC_PM_H + +/* + * These flags are used to describe power management features that + * some cards (typically SDIO cards) might wish to benefit from when + * the host system is being suspended. There are several layers of + * abstractions involved, from the host controller driver, to the MMC core + * code, to the SDIO core code, to finally get to the actual SDIO function + * driver. This file is therefore used for common definitions shared across + * all those layers. + */ + +typedef unsigned int mmc_pm_flag_t; + +#define MMC_PM_KEEP_POWER (1 << 0) /* preserve card power during suspend */ +#define MMC_PM_WAKE_SDIO_IRQ (1 << 1) /* wake up host system on SDIO IRQ assertion */ + +#endif diff --git a/include/linux/mmc/sdio_func.h b/include/linux/mmc/sdio_func.h index ac3ab683fec6..c6c0cceba5fe 100644 --- a/include/linux/mmc/sdio_func.h +++ b/include/linux/mmc/sdio_func.h @@ -15,6 +15,8 @@ #include #include +#include + struct mmc_card; struct sdio_func; @@ -153,5 +155,8 @@ extern unsigned char sdio_f0_readb(struct sdio_func *func, extern void sdio_f0_writeb(struct sdio_func *func, unsigned char b, unsigned int addr, int *err_ret); +extern mmc_pm_flag_t sdio_get_host_pm_caps(struct sdio_func *func); +extern int sdio_set_host_pm_flags(struct sdio_func *func, mmc_pm_flag_t flags); + #endif -- cgit v1.2.3 From 2f4cbb3d834922ffa0309b6a08fa42dac87ef9d2 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Fri, 5 Mar 2010 13:43:32 -0800 Subject: sdio: sdhci support for suspend mode PM features Tested with an XO v1.5 from OLPC. Signed-off-by: Nicolas Pitre Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/sdhci-pci.c | 17 ++++++++++++++--- drivers/mmc/host/sdhci.c | 26 +++++++++++++++++--------- 2 files changed, 31 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c index 5c3a1767770a..dbf054315fe2 100644 --- a/drivers/mmc/host/sdhci-pci.c +++ b/drivers/mmc/host/sdhci-pci.c @@ -501,6 +501,7 @@ static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state) { struct sdhci_pci_chip *chip; struct sdhci_pci_slot *slot; + mmc_pm_flag_t pm_flags = 0; int i, ret; chip = pci_get_drvdata(pdev); @@ -519,6 +520,8 @@ static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state) sdhci_resume_host(chip->slots[i]->host); return ret; } + + pm_flags |= slot->host->mmc->pm_flags; } if (chip->fixes && chip->fixes->suspend) { @@ -531,9 +534,15 @@ static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state) } pci_save_state(pdev); - pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); - pci_disable_device(pdev); - pci_set_power_state(pdev, pci_choose_state(pdev, state)); + if (pm_flags & MMC_PM_KEEP_POWER) { + if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) + pci_enable_wake(pdev, PCI_D3hot, 1); + pci_set_power_state(pdev, PCI_D3hot); + } else { + pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); + pci_disable_device(pdev); + pci_set_power_state(pdev, pci_choose_state(pdev, state)); + } return 0; } @@ -653,6 +662,8 @@ static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot( goto unmap; } + host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; + ret = sdhci_add_host(host); if (ret) goto remove; diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 6c866b43b03c..d6ab62d539fb 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -174,20 +174,31 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask) sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); } -static void sdhci_init(struct sdhci_host *host) +static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); + +static void sdhci_init(struct sdhci_host *host, int soft) { - sdhci_reset(host, SDHCI_RESET_ALL); + if (soft) + sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); + else + sdhci_reset(host, SDHCI_RESET_ALL); sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); + + if (soft) { + /* force clock reconfiguration */ + host->clock = 0; + sdhci_set_ios(host->mmc, &host->mmc->ios); + } } static void sdhci_reinit(struct sdhci_host *host) { - sdhci_init(host); + sdhci_init(host, 0); sdhci_enable_card_detection(host); } @@ -1600,16 +1611,13 @@ int sdhci_resume_host(struct sdhci_host *host) if (ret) return ret; - sdhci_init(host); + sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); mmiowb(); ret = mmc_resume_host(host->mmc); - if (ret) - return ret; - sdhci_enable_card_detection(host); - return 0; + return ret; } EXPORT_SYMBOL_GPL(sdhci_resume_host); @@ -1864,7 +1872,7 @@ int sdhci_add_host(struct sdhci_host *host) if (ret) goto untasklet; - sdhci_init(host); + sdhci_init(host, 0); #ifdef CONFIG_MMC_DEBUG sdhci_dumpregs(host); -- cgit v1.2.3 From 3bca4cf703826fcb2bbabbe19c6fc7b2fc4fd7cc Mon Sep 17 00:00:00 2001 From: Chris Ball Date: Fri, 5 Mar 2010 13:43:33 -0800 Subject: sdio: don't use CMD[357] as part of a powered SDIO resume Seen on a Marvell 8686 SDIO card and Via VX855 controller: we must avoid sending CMD3/5/7 on a resume where power has been maintained, because the 8686 will refuse to respond to them and the MMC stack will give up on the card. Signed-off-by: Chris Ball Signed-off-by: Nicolas Pitre Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/core/sdio.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index 06b64085a355..7d8ba64b0170 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -224,7 +224,7 @@ static int sdio_enable_hs(struct mmc_card *card) * we're trying to reinitialise. */ static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr, - struct mmc_card *oldcard) + struct mmc_card *oldcard, int powered_resume) { struct mmc_card *card; int err; @@ -235,9 +235,11 @@ static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr, /* * Inform the card of the voltage */ - err = mmc_send_io_op_cond(host, host->ocr, &ocr); - if (err) - goto err; + if (!powered_resume) { + err = mmc_send_io_op_cond(host, host->ocr, &ocr); + if (err) + goto err; + } /* * For SPI, enable CRC as appropriate. @@ -262,7 +264,7 @@ static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr, /* * For native busses: set card RCA and quit open drain mode. */ - if (!mmc_host_is_spi(host)) { + if (!powered_resume && !mmc_host_is_spi(host)) { err = mmc_send_relative_addr(host, &card->rca); if (err) goto remove; @@ -273,7 +275,7 @@ static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr, /* * Select card, as all following commands rely on that. */ - if (!mmc_host_is_spi(host)) { + if (!powered_resume && !mmc_host_is_spi(host)) { err = mmc_select_card(card); if (err) goto remove; @@ -437,7 +439,8 @@ static int mmc_sdio_resume(struct mmc_host *host) /* Basic card reinitialization. */ mmc_claim_host(host); - err = mmc_sdio_init_card(host, host->ocr, host->card); + err = mmc_sdio_init_card(host, host->ocr, host->card, + (host->pm_flags & MMC_PM_KEEP_POWER)); mmc_release_host(host); /* @@ -507,7 +510,7 @@ int mmc_attach_sdio(struct mmc_host *host, u32 ocr) /* * Detect and init the card. */ - err = mmc_sdio_init_card(host, host->ocr, NULL); + err = mmc_sdio_init_card(host, host->ocr, NULL, 0); if (err) goto err; card = host->card; -- cgit v1.2.3 From 40216842dca4fa485cb1aa5eb231149a4a57cc85 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Fri, 5 Mar 2010 13:43:34 -0800 Subject: sdio: kick the interrupt thread upon a resume Some SDIO cards may suspend while keeping function interrupts active especially in the powered suspend case. Upon resume we need to kick the SDIO interrupt thread to check for pending interrupts and to restart card IRQ detection at the host controller level. Signed-off-by: Nicolas Pitre Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/core/sdio.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index 7d8ba64b0170..5840de106b69 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -441,6 +441,8 @@ static int mmc_sdio_resume(struct mmc_host *host) mmc_claim_host(host); err = mmc_sdio_init_card(host, host->ocr, host->card, (host->pm_flags & MMC_PM_KEEP_POWER)); + if (!err && host->sdio_irqs) + mmc_signal_sdio_irq(host); mmc_release_host(host); /* -- cgit v1.2.3 From 6b5eda369ac3772dad416ef96d86064204d74770 Mon Sep 17 00:00:00 2001 From: Daniel Drake Date: Fri, 5 Mar 2010 13:43:34 -0800 Subject: sdio: put active devices into 1-bit mode during suspend And bring them back to 4-bit mode during resume. Signed-off-by: Daniel Drake Signed-off-by: Nicolas Pitre Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/core/sdio.c | 43 +++++++++++++++++++++++++++++++++++++++++++ include/linux/mmc/sdio.h | 2 ++ 2 files changed, 45 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index 5840de106b69..2dd4cfe7ca17 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -187,6 +187,40 @@ static int sdio_disable_cd(struct mmc_card *card) return mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_IF, ctrl, NULL); } +/* + * Devices that remain active during a system suspend are + * put back into 1-bit mode. + */ +static int sdio_disable_wide(struct mmc_card *card) +{ + int ret; + u8 ctrl; + + if (!(card->host->caps & MMC_CAP_4_BIT_DATA)) + return 0; + + if (card->cccr.low_speed && !card->cccr.wide_bus) + return 0; + + ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_IF, 0, &ctrl); + if (ret) + return ret; + + if (!(ctrl & SDIO_BUS_WIDTH_4BIT)) + return 0; + + ctrl &= ~SDIO_BUS_WIDTH_4BIT; + ctrl |= SDIO_BUS_ASYNC_INT; + + ret = mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_IF, ctrl, NULL); + if (ret) + return ret; + + mmc_set_bus_width(card->host, MMC_BUS_WIDTH_1); + + return 0; +} + /* * Test if the card supports high-speed mode and, if so, switch to it. */ @@ -427,6 +461,12 @@ static int mmc_sdio_suspend(struct mmc_host *host) } } + if (!err && host->pm_flags & MMC_PM_KEEP_POWER) { + mmc_claim_host(host); + sdio_disable_wide(host->card); + mmc_release_host(host); + } + return err; } @@ -441,6 +481,9 @@ static int mmc_sdio_resume(struct mmc_host *host) mmc_claim_host(host); err = mmc_sdio_init_card(host, host->ocr, host->card, (host->pm_flags & MMC_PM_KEEP_POWER)); + if (!err) + /* We may have switched to 1-bit mode during suspend. */ + err = sdio_enable_wide(host->card); if (!err && host->sdio_irqs) mmc_signal_sdio_irq(host); mmc_release_host(host); diff --git a/include/linux/mmc/sdio.h b/include/linux/mmc/sdio.h index 47ba464f5170..0ebaef577ff5 100644 --- a/include/linux/mmc/sdio.h +++ b/include/linux/mmc/sdio.h @@ -95,6 +95,8 @@ #define SDIO_BUS_WIDTH_1BIT 0x00 #define SDIO_BUS_WIDTH_4BIT 0x02 +#define SDIO_BUS_ASYNC_INT 0x20 + #define SDIO_BUS_CD_DISABLE 0x80 /* disable pull-up on DAT3 (pin 1) */ #define SDIO_CCCR_CAPS 0x08 -- cgit v1.2.3 From c212808a1ba6bfba489006399b8152a047305acf Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 5 Mar 2010 13:43:35 -0800 Subject: s3cmci: initialize default platform data no_wprotect and no_detect with 1 If no platform_data was givin to the device it's going to use it's default platform data struct which has all fields initialized to zero. As a result the driver is going to try to request gpio0 both as write protect and card detect pin. Which of course will fail and makes the driver unusable Previously to the introduction of no_wprotect and no_detect the behavior was to assume that if no platform data was given there is no write protect or card detect pin. This patch restores that behavior. Signed-off-by: Lars-Peter Clausen Cc: Ben Dooks Cc: Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/s3cmci.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c index d96e1abf2d64..b9c96cc87b04 100644 --- a/drivers/mmc/host/s3cmci.c +++ b/drivers/mmc/host/s3cmci.c @@ -1360,6 +1360,8 @@ static struct mmc_host_ops s3cmci_ops = { static struct s3c24xx_mci_pdata s3cmci_def_pdata = { /* This is currently here to avoid a number of if (host->pdata) * checks. Any zero fields to ensure reasonable defaults are picked. */ + .no_wprotect = 1, + .no_detect = 1, }; #ifdef CONFIG_CPU_FREQ -- cgit v1.2.3 From dc2ed552804f3a2ae41c0ffe4bc09879ec8f7396 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 5 Mar 2010 13:43:37 -0800 Subject: s3cmci: s3cmci_card_present: Use no_detect to decide whether there is a card detect pin Signed-off-by: Lars-Peter Clausen Cc: Ben Dooks Cc: Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/s3cmci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c index b9c96cc87b04..2fdf7689ae6c 100644 --- a/drivers/mmc/host/s3cmci.c +++ b/drivers/mmc/host/s3cmci.c @@ -1179,7 +1179,7 @@ static int s3cmci_card_present(struct mmc_host *mmc) struct s3c24xx_mci_pdata *pdata = host->pdata; int ret; - if (pdata->gpio_detect == 0) + if (pdata->no_detect) return -ENOSYS; ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1; -- cgit v1.2.3 From 0b3520f2df8e4e5dad6a7b2743d037bf06c22024 Mon Sep 17 00:00:00 2001 From: Wolfgang Muees Date: Fri, 5 Mar 2010 13:43:38 -0800 Subject: mmc: at91_mci: fix pointer errors Fixes two pointer errors, one which leads to memory overwrites if used with large chunks of data. Signed-off-by: Wolfgang Muees Signed-off-by: Nicolas Ferre Cc: Andrew Victor Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/at91_mci.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c index 63924e0c7ea9..4e1b2e6288da 100644 --- a/drivers/mmc/host/at91_mci.c +++ b/drivers/mmc/host/at91_mci.c @@ -227,11 +227,13 @@ static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data for (index = 0; index < (amount / 4); index++) *dmabuf++ = swab32(sgbuffer[index]); } else { - memcpy(dmabuf, sgbuffer, amount); - dmabuf += amount; + char *tmpv = (char *)dmabuf; + memcpy(tmpv, sgbuffer, amount); + tmpv += amount; + dmabuf = (unsigned *)tmpv; } - kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ); + kunmap_atomic(((void *)sgbuffer) - sg->offset, KM_BIO_SRC_IRQ); if (size == 0) break; -- cgit v1.2.3 From a04ac5b9b45a7adec7d3ee3968e677b6e4b98f25 Mon Sep 17 00:00:00 2001 From: Wolfgang Muees Date: Fri, 5 Mar 2010 13:43:39 -0800 Subject: mmc: at91_mci: fix timeout errors Fix two timeout errors, one for slow SDHC cards and one for slow users while inserting SD cards. Signed-off-by: Wolfgang Muees Signed-off-by: Nicolas Ferre Cc: Andrew Victor Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/at91_mci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c index 4e1b2e6288da..37efe6b3f12d 100644 --- a/drivers/mmc/host/at91_mci.c +++ b/drivers/mmc/host/at91_mci.c @@ -756,7 +756,8 @@ static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) host->request = mrq; host->flags = 0; - mod_timer(&host->timer, jiffies + HZ); + /* more than 1s timeout needed with slow SD cards */ + mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000)); at91_mci_process_next(host); } @@ -944,7 +945,8 @@ static irqreturn_t at91_mmc_det_irq(int irq, void *_host) pr_debug("****** Resetting SD-card bus width ******\n"); at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); } - mmc_detect_change(host->mmc, msecs_to_jiffies(100)); + /* 0.5s needed because of early card detect switch firing */ + mmc_detect_change(host->mmc, msecs_to_jiffies(500)); } return IRQ_HANDLED; } -- cgit v1.2.3 From 3780d90602dfef6df3d8b39b203d6bf7fb99f22a Mon Sep 17 00:00:00 2001 From: Wolfgang Muees Date: Fri, 5 Mar 2010 13:43:40 -0800 Subject: mmc: at91_mci: use one coherent DMA buffer The TX DMA buffer is allocated only once, because the allocation/deallocation of the buffer for EACH chunk of data is time-consuming and prone to memory fragmentation. Using a coherent DMA buffer avoids extra data cache calls. [nicolas.ferre@atmel.com: coding style modifications] Signed-off-by: Wolfgang Muees Signed-off-by: Nicolas Ferre Cc: Andrew Victor Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/at91_mci.c | 49 ++++++++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c index 37efe6b3f12d..76cb05ab9341 100644 --- a/drivers/mmc/host/at91_mci.c +++ b/drivers/mmc/host/at91_mci.c @@ -88,6 +88,10 @@ #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg)) #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg)) +#define MCI_BLKSIZE 512 +#define MCI_MAXBLKSIZE 4095 +#define MCI_BLKATONCE 256 +#define MCI_BUFSIZE (MCI_BLKSIZE * MCI_BLKATONCE) /* * Low level type for this driver @@ -604,7 +608,6 @@ static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command /* * Handle a read */ - host->buffer = NULL; host->total_length = 0; at91_mci_pre_dma_read(host); @@ -623,20 +626,8 @@ static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command if (host->total_length < 12) host->total_length = 12; - host->buffer = kmalloc(host->total_length, GFP_KERNEL); - if (!host->buffer) { - pr_debug("Can't alloc tx buffer\n"); - cmd->error = -ENOMEM; - mmc_request_done(host->mmc, host->request); - return; - } - at91_mci_sg_to_dma(host, data); - host->physical_address = dma_map_single(NULL, - host->buffer, host->total_length, - DMA_TO_DEVICE); - pr_debug("Transmitting %d bytes\n", host->total_length); at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address); @@ -703,14 +694,6 @@ static void at91_mci_completed_command(struct at91mci_host *host, unsigned int s cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2)); cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3)); - if (host->buffer) { - dma_unmap_single(NULL, - host->physical_address, host->total_length, - DMA_TO_DEVICE); - kfree(host->buffer); - host->buffer = NULL; - } - pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n", status, at91_mci_read(host, AT91_MCI_SR), cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); @@ -1012,12 +995,12 @@ static int __init at91_mci_probe(struct platform_device *pdev) mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; mmc->caps = MMC_CAP_SDIO_IRQ; - mmc->max_blk_size = 4095; - mmc->max_blk_count = mmc->max_req_size; + mmc->max_blk_size = MCI_MAXBLKSIZE; + mmc->max_blk_count = MCI_BLKATONCE; + mmc->max_req_size = MCI_BUFSIZE; host = mmc_priv(mmc); host->mmc = mmc; - host->buffer = NULL; host->bus_mode = 0; host->board = pdev->dev.platform_data; if (host->board->wire4) { @@ -1028,6 +1011,14 @@ static int __init at91_mci_probe(struct platform_device *pdev) " - using 1 wire\n"); } + host->buffer = dma_alloc_coherent(&pdev->dev, MCI_BUFSIZE, + &host->physical_address, GFP_KERNEL); + if (!host->buffer) { + ret = -ENOMEM; + dev_err(&pdev->dev, "Can't allocate transmit buffer\n"); + goto fail5; + } + /* * Reserve GPIOs ... board init code makes sure these pins are set * up as GPIOs with the right direction (input, except for vcc) @@ -1036,7 +1027,7 @@ static int __init at91_mci_probe(struct platform_device *pdev) ret = gpio_request(host->board->det_pin, "mmc_detect"); if (ret < 0) { dev_dbg(&pdev->dev, "couldn't claim card detect pin\n"); - goto fail5; + goto fail4b; } } if (host->board->wp_pin) { @@ -1136,6 +1127,10 @@ fail3: fail4: if (host->board->det_pin) gpio_free(host->board->det_pin); +fail4b: + if (host->buffer) + dma_free_coherent(&pdev->dev, MCI_BUFSIZE, + host->buffer, host->physical_address); fail5: mmc_free_host(mmc); fail6: @@ -1158,6 +1153,10 @@ static int __exit at91_mci_remove(struct platform_device *pdev) host = mmc_priv(mmc); + if (host->buffer) + dma_free_coherent(&pdev->dev, MCI_BUFSIZE, + host->buffer, host->physical_address); + if (host->board->det_pin) { if (device_can_wakeup(&pdev->dev)) free_irq(gpio_to_irq(host->board->det_pin), host); -- cgit v1.2.3 From 86ee26f5b0a889bf7e9f6351bbf01516d0686461 Mon Sep 17 00:00:00 2001 From: Wolfgang Muees Date: Fri, 5 Mar 2010 13:43:41 -0800 Subject: mmc: at91_mci: use DMA buffer for read Convert the read to use the DMA buffer as well. The old code was doing double-buffering DMA with the PDC; no way to make it work. Replace it with a single-PDC approach. It also simplify things removing the need for a pre_dma_read() function. [nicolas.ferre@atmel.com coding style modifications] Signed-off-by: Wolfgang Muees Signed-off-by: Nicolas Ferre Cc: Andrew Victor Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/at91_mci.c | 128 +++++++++++--------------------------------- 1 file changed, 32 insertions(+), 96 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c index 76cb05ab9341..818b4e75708a 100644 --- a/drivers/mmc/host/at91_mci.c +++ b/drivers/mmc/host/at91_mci.c @@ -250,74 +250,6 @@ static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data BUG_ON(size != 0); } -/* - * Prepare a dma read - */ -static void at91_mci_pre_dma_read(struct at91mci_host *host) -{ - int i; - struct scatterlist *sg; - struct mmc_command *cmd; - struct mmc_data *data; - - pr_debug("pre dma read\n"); - - cmd = host->cmd; - if (!cmd) { - pr_debug("no command\n"); - return; - } - - data = cmd->data; - if (!data) { - pr_debug("no data\n"); - return; - } - - for (i = 0; i < 2; i++) { - /* nothing left to transfer */ - if (host->transfer_index >= data->sg_len) { - pr_debug("Nothing left to transfer (index = %d)\n", host->transfer_index); - break; - } - - /* Check to see if this needs filling */ - if (i == 0) { - if (at91_mci_read(host, ATMEL_PDC_RCR) != 0) { - pr_debug("Transfer active in current\n"); - continue; - } - } - else { - if (at91_mci_read(host, ATMEL_PDC_RNCR) != 0) { - pr_debug("Transfer active in next\n"); - continue; - } - } - - /* Setup the next transfer */ - pr_debug("Using transfer index %d\n", host->transfer_index); - - sg = &data->sg[host->transfer_index++]; - pr_debug("sg = %p\n", sg); - - sg->dma_address = dma_map_page(NULL, sg_page(sg), sg->offset, sg->length, DMA_FROM_DEVICE); - - pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length); - - if (i == 0) { - at91_mci_write(host, ATMEL_PDC_RPR, sg->dma_address); - at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ? sg->length : sg->length / 4); - } - else { - at91_mci_write(host, ATMEL_PDC_RNPR, sg->dma_address); - at91_mci_write(host, ATMEL_PDC_RNCR, (data->blksz & 0x3) ? sg->length : sg->length / 4); - } - } - - pr_debug("pre dma read done\n"); -} - /* * Handle after a dma read */ @@ -325,6 +257,8 @@ static void at91_mci_post_dma_read(struct at91mci_host *host) { struct mmc_command *cmd; struct mmc_data *data; + unsigned int len, i, size; + unsigned *dmabuf = host->buffer; pr_debug("post dma read\n"); @@ -340,42 +274,39 @@ static void at91_mci_post_dma_read(struct at91mci_host *host) return; } - while (host->in_use_index < host->transfer_index) { - struct scatterlist *sg; + size = data->blksz * data->blocks; + len = data->sg_len; - pr_debug("finishing index %d\n", host->in_use_index); + at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX); + at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF); - sg = &data->sg[host->in_use_index++]; + for (i = 0; i < len; i++) { + struct scatterlist *sg; + int amount; + unsigned int *sgbuffer; - pr_debug("Unmapping page %08X\n", sg->dma_address); + sg = &data->sg[i]; - dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE); + sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; + amount = min(size, sg->length); + size -= amount; if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ - unsigned int *buffer; int index; - - /* Swap the contents of the buffer */ - buffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; - pr_debug("buffer = %p, length = %d\n", buffer, sg->length); - - for (index = 0; index < (sg->length / 4); index++) - buffer[index] = swab32(buffer[index]); - - kunmap_atomic(buffer, KM_BIO_SRC_IRQ); + for (index = 0; index < (amount / 4); index++) + sgbuffer[index] = swab32(*dmabuf++); + } else { + char *tmpv = (char *)dmabuf; + memcpy(sgbuffer, tmpv, amount); + tmpv += amount; + dmabuf = (unsigned *)tmpv; } - flush_dcache_page(sg_page(sg)); - - data->bytes_xfered += sg->length; - } - - /* Is there another transfer to trigger? */ - if (host->transfer_index < data->sg_len) - at91_mci_pre_dma_read(host); - else { - at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX); - at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF); + kunmap_atomic(((void *)sgbuffer)-sg->offset, KM_BIO_SRC_IRQ); + dmac_flush_range((void *)sgbuffer, ((void *)sgbuffer) + amount); + data->bytes_xfered += amount; + if (size == 0) + break; } pr_debug("post dma read done\n"); @@ -610,7 +541,12 @@ static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command */ host->total_length = 0; - at91_mci_pre_dma_read(host); + at91_mci_write(host, ATMEL_PDC_RPR, host->physical_address); + at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ? + (blocks * block_length) : (blocks * block_length) / 4); + at91_mci_write(host, ATMEL_PDC_RNPR, 0); + at91_mci_write(host, ATMEL_PDC_RNCR, 0); + ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; } else { -- cgit v1.2.3 From 9af13be2acac60ca5593e41a601d4a5b6bc35302 Mon Sep 17 00:00:00 2001 From: Wolfgang Muees Date: Fri, 5 Mar 2010 13:43:42 -0800 Subject: mmc: at91_mci: enable large data blocks This patch is setting some max_ variables for the IO elevator, so the elevator will put requests for large data blocks to the driver. This is critical for a) speed and b) wear leveling of the flash chip controller: Otherwise the controller will treat the SD card badly with millions of single 4 KByte write commands. This will lead to a shorter life time for the SD cards. Signed-off-by: Wolfgang Muees Signed-off-by: Nicolas Ferre Cc: Andrew Victor Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/at91_mci.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c index 818b4e75708a..3cd00c6f2584 100644 --- a/drivers/mmc/host/at91_mci.c +++ b/drivers/mmc/host/at91_mci.c @@ -934,6 +934,9 @@ static int __init at91_mci_probe(struct platform_device *pdev) mmc->max_blk_size = MCI_MAXBLKSIZE; mmc->max_blk_count = MCI_BLKATONCE; mmc->max_req_size = MCI_BUFSIZE; + mmc->max_phys_segs = MCI_BLKATONCE; + mmc->max_hw_segs = MCI_BLKATONCE; + mmc->max_seg_size = MCI_BUFSIZE; host = mmc_priv(mmc); host->mmc = mmc; -- cgit v1.2.3 From 541e7ef0399c6c5753cc8d3e8f371dcb3627e8a4 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 5 Mar 2010 13:43:43 -0800 Subject: mmc: at91_mci: Enable MMC_CAP_SDIO_IRQ only when it actually works. According to the datasheets AT91SAM9261 does not support SDIO interrupts, and AT91SAM9260/9263 have an erratum requiring 4bit mode while using slot B for the interrupt to work. Signed-off-by: Nicolas Ferre Cc: Wolfgang Muees Cc: Andrew Victor Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/at91_mci.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c index 3cd00c6f2584..8327daebb396 100644 --- a/drivers/mmc/host/at91_mci.c +++ b/drivers/mmc/host/at91_mci.c @@ -929,7 +929,7 @@ static int __init at91_mci_probe(struct platform_device *pdev) mmc->f_min = 375000; mmc->f_max = 25000000; mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->caps = MMC_CAP_SDIO_IRQ; + mmc->caps = 0; mmc->max_blk_size = MCI_MAXBLKSIZE; mmc->max_blk_count = MCI_BLKATONCE; @@ -958,6 +958,13 @@ static int __init at91_mci_probe(struct platform_device *pdev) goto fail5; } + /* Add SDIO capability when available */ + if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) { + /* AT91SAM9260/9263 erratum */ + if (host->board->wire4 || !host->board->slot_b) + mmc->caps |= MMC_CAP_SDIO_IRQ; + } + /* * Reserve GPIOs ... board init code makes sure these pins are set * up as GPIOs with the right direction (input, except for vcc) -- cgit v1.2.3 From 5b27a1a566c5a4cce81d75107a0f130e43c6a5f8 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 5 Mar 2010 13:43:44 -0800 Subject: mmc: at91_mci: introduce per-mci-revision conditional code We used to manage features and differences on a per-cpu basis. As several cpus share the same mci revision, this patch aggregates cpus that have the same IP revision in one defined constant. We use the at91mci_is_mci1rev2xx() funtion name not to mess with newer Atmel sd/mmc IP called "MCI2". _rev2 naming could have been confusing... Signed-off-by: Nicolas Ferre Cc: Wolfgang Muees Cc: Andrew Victor Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/at91_mci.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c index 8327daebb396..55507dacb789 100644 --- a/drivers/mmc/host/at91_mci.c +++ b/drivers/mmc/host/at91_mci.c @@ -78,6 +78,17 @@ #define DRIVER_NAME "at91_mci" +static inline int at91mci_is_mci1rev2xx(void) +{ + return ( cpu_is_at91sam9260() + || cpu_is_at91sam9263() + || cpu_is_at91cap9() + || cpu_is_at91sam9rl() + || cpu_is_at91sam9g10() + || cpu_is_at91sam9g20() + ); +} + #define FL_SENT_COMMAND (1 << 0) #define FL_SENT_STOP (1 << 1) @@ -204,8 +215,8 @@ static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data size = data->blksz * data->blocks; len = data->sg_len; - /* AT91SAM926[0/3] Data Write Operation and number of bytes erratum */ - if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) + /* MCI1 rev2xx Data Write Operation and number of bytes erratum */ + if (at91mci_is_mci1rev2xx()) if (host->total_length == 12) memset(dmabuf, 0, 12); @@ -398,7 +409,7 @@ static void at91_mci_enable(struct at91mci_host *host) at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); mr = AT91_MCI_PDCMODE | 0x34a; - if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) + if (at91mci_is_mci1rev2xx()) mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; at91_mci_write(host, AT91_MCI_MR, mr); @@ -555,10 +566,10 @@ static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command */ host->total_length = block_length * blocks; /* - * AT91SAM926[0/3] Data Write Operation and + * MCI1 rev2xx Data Write Operation and * number of bytes erratum */ - if (cpu_is_at91sam9260 () || cpu_is_at91sam9263()) + if (at91mci_is_mci1rev2xx()) if (host->total_length < 12) host->total_length = 12; @@ -943,7 +954,7 @@ static int __init at91_mci_probe(struct platform_device *pdev) host->bus_mode = 0; host->board = pdev->dev.platform_data; if (host->board->wire4) { - if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) + if (at91mci_is_mci1rev2xx()) mmc->caps |= MMC_CAP_4_BIT_DATA; else dev_warn(&pdev->dev, "4 wire bus mode not supported" @@ -959,8 +970,8 @@ static int __init at91_mci_probe(struct platform_device *pdev) } /* Add SDIO capability when available */ - if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) { - /* AT91SAM9260/9263 erratum */ + if (at91mci_is_mci1rev2xx()) { + /* at91mci MCI1 rev2xx sdio interrupt erratum */ if (host->board->wire4 || !host->board->slot_b) mmc->caps |= MMC_CAP_SDIO_IRQ; } -- cgit v1.2.3 From 752993ef8e40d1863b26c7dc51e12223588d0fe0 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 5 Mar 2010 13:43:45 -0800 Subject: mmc: at91_mci: correct kunmap_atomic() kunmap_atomic() accepts a pointer to any location in the page so we do not need the subtraction and cast. Signed-off-by: Nicolas Ferre Cc: Wolfgang Muees Cc: Andrew Victor Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/at91_mci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c index 55507dacb789..91dc60cd032b 100644 --- a/drivers/mmc/host/at91_mci.c +++ b/drivers/mmc/host/at91_mci.c @@ -248,7 +248,7 @@ static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data dmabuf = (unsigned *)tmpv; } - kunmap_atomic(((void *)sgbuffer) - sg->offset, KM_BIO_SRC_IRQ); + kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ); if (size == 0) break; @@ -313,7 +313,7 @@ static void at91_mci_post_dma_read(struct at91mci_host *host) dmabuf = (unsigned *)tmpv; } - kunmap_atomic(((void *)sgbuffer)-sg->offset, KM_BIO_SRC_IRQ); + kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ); dmac_flush_range((void *)sgbuffer, ((void *)sgbuffer) + amount); data->bytes_xfered += amount; if (size == 0) -- cgit v1.2.3 From 849382948992cc6482c778b1e854c19368b60c05 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Fri, 5 Mar 2010 13:43:46 -0800 Subject: mmc: enable DMA on Ricoh sdhci reader by default This card reader doesn't advertise, however DMA works well. Probably windows SDHCI driver assumes that all readers support DMA and thus we see that bug. Signed-off-by: Vasily Khoruzhick Tested-by: Maxim Levitsky Signed-off-by: Maxim Levitsky Cc: Harald Welte Cc: Norbert Preining Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/host/sdhci-pci.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c index dbf054315fe2..8e1020cf73f4 100644 --- a/drivers/mmc/host/sdhci-pci.c +++ b/drivers/mmc/host/sdhci-pci.c @@ -80,9 +80,6 @@ struct sdhci_pci_chip { static int ricoh_probe(struct sdhci_pci_chip *chip) { - if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_IBM) - chip->quirks |= SDHCI_QUIRK_CLOCK_BEFORE_RESET; - if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; @@ -92,7 +89,9 @@ static int ricoh_probe(struct sdhci_pci_chip *chip) static const struct sdhci_pci_fixes sdhci_ricoh = { .probe = ricoh_probe, - .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR, + .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | + SDHCI_QUIRK_FORCE_DMA | + SDHCI_QUIRK_CLOCK_BEFORE_RESET, }; static const struct sdhci_pci_fixes sdhci_ene_712 = { -- cgit v1.2.3 From 4cae787840ae82aa02649f45c46839b349034435 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Fri, 5 Mar 2010 13:43:56 -0800 Subject: drivers/hwmon/vt8231.c: fix continuation line formats String constants that are continued on subsequent lines with \ will cause spurious whitespace in the resulting output. Signed-off-by: Joe Perches Cc: Roger Lucas Cc: Jean Delvare Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/hwmon/vt8231.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/vt8231.c b/drivers/hwmon/vt8231.c index d47b4c9949c2..e6078c9f0e27 100644 --- a/drivers/hwmon/vt8231.c +++ b/drivers/hwmon/vt8231.c @@ -948,8 +948,7 @@ static int __devinit vt8231_pci_probe(struct pci_dev *dev, address = val & ~(VT8231_EXTENT - 1); if (address == 0) { - dev_err(&dev->dev, "base address not set -\ - upgrade BIOS or use force_addr=0xaddr\n"); + dev_err(&dev->dev, "base address not set - upgrade BIOS or use force_addr=0xaddr\n"); return -ENODEV; } -- cgit v1.2.3 From 5748150eabdacd3f870c311b63d32f5e312bf624 Mon Sep 17 00:00:00 2001 From: José Miguel Gonçalves Date: Fri, 5 Mar 2010 13:43:58 -0800 Subject: drivers/hwmon/adcxx.c: fix for single-channel ADCs While testing an ADC121S021 in an embedded board with a S3C2142 SoC (ARM core), I have found that the 'adcxx' driver does not handle correctly single channel ADCs from this chip family. For single channel chips you must only issue one read transfer for correct measurement. Signed-off-by: Jose Miguel Goncalves Cc: Marc Pignat Cc: Anton Vorontsov Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/hwmon/adcxx.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/adcxx.c b/drivers/hwmon/adcxx.c index 5e9e095f1136..74d9c5195e44 100644 --- a/drivers/hwmon/adcxx.c +++ b/drivers/hwmon/adcxx.c @@ -62,18 +62,23 @@ static ssize_t adcxx_read(struct device *dev, struct spi_device *spi = to_spi_device(dev); struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); struct adcxx *adc = dev_get_drvdata(&spi->dev); - u8 tx_buf[2] = { attr->index << 3 }; /* other bits are don't care */ + u8 tx_buf[2]; u8 rx_buf[2]; int status; - int value; + u32 value; if (mutex_lock_interruptible(&adc->lock)) return -ERESTARTSYS; - status = spi_write_then_read(spi, tx_buf, sizeof(tx_buf), - rx_buf, sizeof(rx_buf)); + if (adc->channels == 1) { + status = spi_read(spi, rx_buf, sizeof(rx_buf)); + } else { + tx_buf[0] = attr->index << 3; /* other bits are don't care */ + status = spi_write_then_read(spi, tx_buf, sizeof(tx_buf), + rx_buf, sizeof(rx_buf)); + } if (status < 0) { - dev_warn(dev, "spi_write_then_read failed with status %d\n", + dev_warn(dev, "SPI synch. transfer failed with status %d\n", status); goto out; } -- cgit v1.2.3 From a52712af5a7473b9f85d8499153f4bbfe875f942 Mon Sep 17 00:00:00 2001 From: Amerigo Wang Date: Fri, 5 Mar 2010 13:44:17 -0800 Subject: console: limit the range of VGACON_SOFT_SCROLLBACK_SIZE BuraphaLinux reported that we will trigger a mm warning when we CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=65536, this is because mm cann't allocate so many pages. We should limit the range of CONFIG_VGACON_SOFT_SCROLLBACK_SIZE, don't give a user any chance to trigger that. Reported-by: BuraphaLinux Server Tested-by: BuraphaLinux Server Signed-off-by: WANG Cong Cc: David S. Miller Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/video/console/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig index fc7d9bbb548c..8e8f18d29d7a 100644 --- a/drivers/video/console/Kconfig +++ b/drivers/video/console/Kconfig @@ -37,6 +37,7 @@ config VGACON_SOFT_SCROLLBACK config VGACON_SOFT_SCROLLBACK_SIZE int "Scrollback Buffer Size (in KB)" depends on VGACON_SOFT_SCROLLBACK + range 1 1024 default "64" help Enter the amount of System RAM to allocate for the scrollback -- cgit v1.2.3 From 6aed359df4d82c38145d95957b741f0b08d24074 Mon Sep 17 00:00:00 2001 From: Thiago Farina Date: Fri, 5 Mar 2010 13:44:17 -0800 Subject: console/vgacon.c: mark file-local symbol static warning: symbol 'vgacon_text_mode_force' was not declared. Should it be static? Signed-off-by: Thiago Farina Acked-by: Matthew Garrett Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/video/console/vgacon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/console/vgacon.c b/drivers/video/console/vgacon.c index cc4bbbe44aca..182dd6f8aadd 100644 --- a/drivers/video/console/vgacon.c +++ b/drivers/video/console/vgacon.c @@ -112,7 +112,7 @@ static int vga_video_font_height; static int vga_scan_lines __read_mostly; static unsigned int vga_rolled_over; -int vgacon_text_mode_force = 0; +static int vgacon_text_mode_force; bool vgacon_text_force(void) { -- cgit v1.2.3 From 27fb7f009bdb1ff13d4e4c008a2fd36b2305055b Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Fri, 5 Mar 2010 13:44:18 -0800 Subject: xen: add kconfig menu Currently the xen support drivers are displayed in the main Device Drivers menu of the config tools instead of in their own sub-menu, so move them to their own sub-menu, like the rest of the driver world uses. This keeps the main Device Drivers menu from becoming messy. Signed-off-by: Randy Dunlap Cc: Jeremy Fitzhardinge Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/xen/Kconfig | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig index cab100acf983..fad3df2c1276 100644 --- a/drivers/xen/Kconfig +++ b/drivers/xen/Kconfig @@ -1,6 +1,8 @@ +menu "Xen driver support" + depends on XEN + config XEN_BALLOON bool "Xen memory balloon driver" - depends on XEN default y help The balloon driver allows the Xen domain to request more memory from @@ -20,7 +22,6 @@ config XEN_SCRUB_PAGES config XEN_DEV_EVTCHN tristate "Xen /dev/xen/evtchn device" - depends on XEN default y help The evtchn driver allows a userspace process to triger event @@ -30,7 +31,6 @@ config XEN_DEV_EVTCHN config XENFS tristate "Xen filesystem" - depends on XEN default y help The xen filesystem provides a way for domains to share @@ -53,11 +53,13 @@ config XEN_COMPAT_XENFS config XEN_SYS_HYPERVISOR bool "Create xen entries under /sys/hypervisor" - depends on XEN && SYSFS + depends on SYSFS select SYS_HYPERVISOR default y help Create entries under /sys/hypervisor describing the Xen hypervisor environment. When running native or in another virtual environment, /sys/hypervisor will still be present, - but will have no xen contents. \ No newline at end of file + but will have no xen contents. + +endmenu -- cgit v1.2.3 From 49908e739e23e2672d3efb9b1a35f877f8e86342 Mon Sep 17 00:00:00 2001 From: Alexander Beregalov Date: Fri, 5 Mar 2010 13:44:19 -0800 Subject: rtc: mxc: fix memory leak Free pdata before exit. Found by cppcheck. [yuasa@linux-mips.org: add missing iounmap()] Signed-off-by: Alexander Beregalov Reviewed-by: WANG Cong Acked-by: Daniel Mack Acked-by: Alessandro Zummo Cc Yoichi Yuasa Cc: Paul Gortmaker Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/rtc/rtc-mxc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/rtc-mxc.c b/drivers/rtc/rtc-mxc.c index 6bd5072d4eb7..8710f9415d98 100644 --- a/drivers/rtc/rtc-mxc.c +++ b/drivers/rtc/rtc-mxc.c @@ -396,8 +396,11 @@ static int __init mxc_rtc_probe(struct platform_device *pdev) pdata->ioaddr = ioremap(res->start, resource_size(res)); clk = clk_get(&pdev->dev, "ckil"); - if (IS_ERR(clk)) - return PTR_ERR(clk); + if (IS_ERR(clk)) { + iounmap(pdata->ioaddr); + ret = PTR_ERR(clk); + goto exit_free_pdata; + } rate = clk_get_rate(clk); clk_put(clk); -- cgit v1.2.3 From b4877d2b3678f4455f2b8b0211868ac57c3b1ff6 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Fri, 5 Mar 2010 13:44:20 -0800 Subject: rtc-ep93xx.c: cleanup probe/remove routines Fix issue with rtc device not getting unregistered in probe error path. Use the devres managed resource functions in the probe routine to cleanup the error path. Use sysfs_{create/remove}_group to add/remove the sysfs files. Reduces the text size by 132 bytes, increases data by 12 bytes: text data bss dec hex filename - 937 124 0 1061 425 rtc-ep93xx.o + 805 136 0 941 3ad rtc-ep93xx.o Signed-off-by: H Hartley Sweeten Acked-by: Alessandro Zummo Cc: Paul Gortmaker Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/rtc/rtc-ep93xx.c | 71 +++++++++++++++++++----------------------------- 1 file changed, 28 insertions(+), 43 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/rtc-ep93xx.c b/drivers/rtc/rtc-ep93xx.c index 9da02d108b73..91bde976bc0f 100644 --- a/drivers/rtc/rtc-ep93xx.c +++ b/drivers/rtc/rtc-ep93xx.c @@ -115,6 +115,15 @@ static ssize_t ep93xx_rtc_show_comp_delete(struct device *dev, } static DEVICE_ATTR(comp_delete, S_IRUGO, ep93xx_rtc_show_comp_delete, NULL); +static struct attribute *ep93xx_rtc_attrs[] = { + &dev_attr_comp_preload.attr, + &dev_attr_comp_delete.attr, + NULL +}; + +static const struct attribute_group ep93xx_rtc_sysfs_files = { + .attrs = ep93xx_rtc_attrs, +}; static int __init ep93xx_rtc_probe(struct platform_device *pdev) { @@ -123,27 +132,22 @@ static int __init ep93xx_rtc_probe(struct platform_device *pdev) struct rtc_device *rtc; int err; - ep93xx_rtc = kzalloc(sizeof(struct ep93xx_rtc), GFP_KERNEL); - if (ep93xx_rtc == NULL) + ep93xx_rtc = devm_kzalloc(&pdev->dev, sizeof(*ep93xx_rtc), GFP_KERNEL); + if (!ep93xx_rtc) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res == NULL) { - err = -ENXIO; - goto fail_free; - } + if (!res) + return -ENXIO; - res = request_mem_region(res->start, resource_size(res), pdev->name); - if (res == NULL) { - err = -EBUSY; - goto fail_free; - } + if (!devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), pdev->name)) + return -EBUSY; - ep93xx_rtc->mmio_base = ioremap(res->start, resource_size(res)); - if (ep93xx_rtc->mmio_base == NULL) { - err = -ENXIO; - goto fail; - } + ep93xx_rtc->mmio_base = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!ep93xx_rtc->mmio_base) + return -ENXIO; pdev->dev.platform_data = ep93xx_rtc; @@ -151,53 +155,34 @@ static int __init ep93xx_rtc_probe(struct platform_device *pdev) &pdev->dev, &ep93xx_rtc_ops, THIS_MODULE); if (IS_ERR(rtc)) { err = PTR_ERR(rtc); - goto fail; + goto exit; } platform_set_drvdata(pdev, rtc); - err = device_create_file(&pdev->dev, &dev_attr_comp_preload); + err = sysfs_create_group(&pdev->dev.kobj, &ep93xx_rtc_sysfs_files); if (err) goto fail; - err = device_create_file(&pdev->dev, &dev_attr_comp_delete); - if (err) { - device_remove_file(&pdev->dev, &dev_attr_comp_preload); - goto fail; - } return 0; fail: - if (ep93xx_rtc->mmio_base) { - iounmap(ep93xx_rtc->mmio_base); - pdev->dev.platform_data = NULL; - } - release_mem_region(res->start, resource_size(res)); -fail_free: - kfree(ep93xx_rtc); + platform_set_drvdata(pdev, NULL); + rtc_device_unregister(rtc); +exit: + pdev->dev.platform_data = NULL; return err; } static int __exit ep93xx_rtc_remove(struct platform_device *pdev) { struct rtc_device *rtc = platform_get_drvdata(pdev); - struct ep93xx_rtc *ep93xx_rtc = pdev->dev.platform_data; - struct resource *res; - - /* cleanup sysfs */ - device_remove_file(&pdev->dev, &dev_attr_comp_delete); - device_remove_file(&pdev->dev, &dev_attr_comp_preload); + sysfs_remove_group(&pdev->dev.kobj, &ep93xx_rtc_sysfs_files); + platform_set_drvdata(pdev, NULL); rtc_device_unregister(rtc); - - iounmap(ep93xx_rtc->mmio_base); pdev->dev.platform_data = NULL; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - release_mem_region(res->start, resource_size(res)); - - platform_set_drvdata(pdev, NULL); - return 0; } -- cgit v1.2.3 From b51e8293182764ca7b1a1bdb28a5c5dc60152c76 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 5 Mar 2010 13:44:21 -0800 Subject: rtc-pcf2123: move pcf2123_remove to .devexit.text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The function pcf2123_remove is used only wrapped by __devexit_p so define it using __devexit. Signed-off-by: Uwe Kleine-König Signed-off-by: Alessandro Zummo Cc: Christian Pellegrin Cc: Chris Verges Cc: Paul Gortmaker Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/rtc/rtc-pcf2123.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/rtc/rtc-pcf2123.c b/drivers/rtc/rtc-pcf2123.c index e75df9d50e27..2ceb365533b2 100644 --- a/drivers/rtc/rtc-pcf2123.c +++ b/drivers/rtc/rtc-pcf2123.c @@ -315,7 +315,7 @@ kfree_exit: return ret; } -static int pcf2123_remove(struct spi_device *spi) +static int __devexit pcf2123_remove(struct spi_device *spi) { struct pcf2123_plat_data *pdata = spi->dev.platform_data; int i; -- cgit v1.2.3 From 870a2761a8df7dea7449b4225c9babcf22c6ead4 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Fri, 5 Mar 2010 13:44:23 -0800 Subject: rtc-at91sam9: Correct size given to memset Memset should be given the size of the structure, not the size of the pointer. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // @@ type T; T *x; expression E; @@ memset(x, E, sizeof( + * x)) // Signed-off-by: Julia Lawall Signed-off-by: Alessandro Zummo Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/rtc/rtc-at91sam9.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c index 86c61f143515..78a018b5c941 100644 --- a/drivers/rtc/rtc-at91sam9.c +++ b/drivers/rtc/rtc-at91sam9.c @@ -161,7 +161,7 @@ static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) if (offset == 0) return -EILSEQ; - memset(alrm, 0, sizeof(alrm)); + memset(alrm, 0, sizeof(*alrm)); if (alarm != ALARM_DISABLED && offset != 0) { rtc_time_to_tm(offset + alarm, tm); -- cgit v1.2.3 From 2e84067b6e557b0b85cdbceaf9a9189fc2c26536 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 5 Mar 2010 13:44:23 -0800 Subject: rtc-twl: Storage class should be before const qualifier The C99 specification states in section 6.11.5: The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature. Signed-off-by: Tobias Klauser Signed-off-by: Alessandro Zummo Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/rtc/rtc-twl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c index c6a83a2a722c..ed1b86828124 100644 --- a/drivers/rtc/rtc-twl.c +++ b/drivers/rtc/rtc-twl.c @@ -57,7 +57,7 @@ enum { REG_RTC_COMP_LSB_REG, REG_RTC_COMP_MSB_REG, }; -const static u8 twl4030_rtc_reg_map[] = { +static const u8 twl4030_rtc_reg_map[] = { [REG_SECONDS_REG] = 0x00, [REG_MINUTES_REG] = 0x01, [REG_HOURS_REG] = 0x02, @@ -80,7 +80,7 @@ const static u8 twl4030_rtc_reg_map[] = { [REG_RTC_COMP_LSB_REG] = 0x10, [REG_RTC_COMP_MSB_REG] = 0x11, }; -const static u8 twl6030_rtc_reg_map[] = { +static const u8 twl6030_rtc_reg_map[] = { [REG_SECONDS_REG] = 0x00, [REG_MINUTES_REG] = 0x01, [REG_HOURS_REG] = 0x02, -- cgit v1.2.3 From 2a7a06a0cdd86d572e91657603180da5992be6d3 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Fri, 5 Mar 2010 13:44:24 -0800 Subject: rtc-core: fix memory leak The idr should be destroyed when the module is unloaded. Found with kmemleak. Signed-off-by: Aaro Koskinen Cc: Alessandro Zummo Cc: stable Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/rtc/class.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/rtc/class.c b/drivers/rtc/class.c index be5a6b73e601..40845c7e9322 100644 --- a/drivers/rtc/class.c +++ b/drivers/rtc/class.c @@ -226,6 +226,7 @@ static void __exit rtc_exit(void) { rtc_dev_exit(); class_destroy(rtc_class); + idr_destroy(&rtc_idr); } subsys_initcall(rtc_init); -- cgit v1.2.3 From 57205026da070b59e9546df352fe465f1aeacf99 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 5 Mar 2010 13:44:25 -0800 Subject: mc13783: rename mc13783_{{un,}mask,ack_irq} to have a mc13783_irq prefix MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In the source file group these functions together. The mc13783 header file provides fallback implementations for the old names to prevent build failures. When all users of the old names are fixed to use the new names these can go away. Signed-off-by: Uwe Kleine-König Cc: Alessandro Zummo Cc: Paul Gortmaker Cc: Valentin Longchamp Cc: Sascha Hauer Cc: Samuel Ortiz Cc: Dmitry Torokhov Cc: Luotao Fu Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mfd/mc13783-core.c | 38 +++++++++++++++++++------------------- include/linux/mfd/mc13783.h | 24 +++++++++++++++++++++--- 2 files changed, 40 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/mc13783-core.c b/drivers/mfd/mc13783-core.c index 735c8a4d164f..a2bd44552042 100644 --- a/drivers/mfd/mc13783-core.c +++ b/drivers/mfd/mc13783-core.c @@ -225,7 +225,7 @@ int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset, } EXPORT_SYMBOL(mc13783_reg_rmw); -int mc13783_mask(struct mc13783 *mc13783, int irq) +int mc13783_irq_mask(struct mc13783 *mc13783, int irq) { int ret; unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1; @@ -245,9 +245,9 @@ int mc13783_mask(struct mc13783 *mc13783, int irq) return mc13783_reg_write(mc13783, offmask, mask | irqbit); } -EXPORT_SYMBOL(mc13783_mask); +EXPORT_SYMBOL(mc13783_irq_mask); -int mc13783_unmask(struct mc13783 *mc13783, int irq) +int mc13783_irq_unmask(struct mc13783 *mc13783, int irq) { int ret; unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1; @@ -267,7 +267,18 @@ int mc13783_unmask(struct mc13783 *mc13783, int irq) return mc13783_reg_write(mc13783, offmask, mask & ~irqbit); } -EXPORT_SYMBOL(mc13783_unmask); +EXPORT_SYMBOL(mc13783_irq_unmask); + +int mc13783_irq_ack(struct mc13783 *mc13783, int irq) +{ + unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1; + unsigned int val = 1 << (irq < 24 ? irq : irq - 24); + + BUG_ON(irq < 0 || irq >= MC13783_NUM_IRQ); + + return mc13783_reg_write(mc13783, offstat, val); +} +EXPORT_SYMBOL(mc13783_irq_ack); int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq, irq_handler_t handler, const char *name, void *dev) @@ -297,7 +308,7 @@ int mc13783_irq_request(struct mc13783 *mc13783, int irq, if (ret) return ret; - ret = mc13783_unmask(mc13783, irq); + ret = mc13783_irq_unmask(mc13783, irq); if (ret) { mc13783->irqhandler[irq] = NULL; mc13783->irqdata[irq] = NULL; @@ -317,7 +328,7 @@ int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev) mc13783->irqdata[irq] != dev) return -EINVAL; - ret = mc13783_mask(mc13783, irq); + ret = mc13783_irq_mask(mc13783, irq); if (ret) return ret; @@ -333,17 +344,6 @@ static inline irqreturn_t mc13783_irqhandler(struct mc13783 *mc13783, int irq) return mc13783->irqhandler[irq](irq, mc13783->irqdata[irq]); } -int mc13783_ackirq(struct mc13783 *mc13783, int irq) -{ - unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1; - unsigned int val = 1 << (irq < 24 ? irq : irq - 24); - - BUG_ON(irq < 0 || irq >= MC13783_NUM_IRQ); - - return mc13783_reg_write(mc13783, offstat, val); -} -EXPORT_SYMBOL(mc13783_ackirq); - /* * returns: number of handled irqs or negative error * locking: holds mc13783->lock @@ -422,7 +422,7 @@ static irqreturn_t mc13783_handler_adcdone(int irq, void *data) { struct mc13783_adcdone_data *adcdone_data = data; - mc13783_ackirq(adcdone_data->mc13783, irq); + mc13783_irq_ack(adcdone_data->mc13783, irq); complete_all(&adcdone_data->done); @@ -486,7 +486,7 @@ int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode, dev_dbg(&mc13783->spidev->dev, "%s: request irq\n", __func__); mc13783_irq_request(mc13783, MC13783_IRQ_ADCDONE, mc13783_handler_adcdone, __func__, &adcdone_data); - mc13783_ackirq(mc13783, MC13783_IRQ_ADCDONE); + mc13783_irq_ack(mc13783, MC13783_IRQ_ADCDONE); mc13783_reg_write(mc13783, MC13783_REG_ADC_0, adc0); mc13783_reg_write(mc13783, MC13783_REG_ADC_1, adc1); diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h index 94cb51a64037..b8b9f3b4f3e2 100644 --- a/include/linux/mfd/mc13783.h +++ b/include/linux/mfd/mc13783.h @@ -26,10 +26,28 @@ int mc13783_irq_request(struct mc13783 *mc13783, int irq, int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq, irq_handler_t handler, const char *name, void *dev); int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev); -int mc13783_ackirq(struct mc13783 *mc13783, int irq); -int mc13783_mask(struct mc13783 *mc13783, int irq); -int mc13783_unmask(struct mc13783 *mc13783, int irq); +int mc13783_irq_mask(struct mc13783 *mc13783, int irq); +int mc13783_irq_unmask(struct mc13783 *mc13783, int irq); +int mc13783_irq_ack(struct mc13783 *mc13783, int irq); + +static inline int mc13783_mask(struct mc13783 *mc13783, int irq) __deprecated; +static inline int mc13783_mask(struct mc13783 *mc13783, int irq) +{ + return mc13783_irq_mask(mc13783, irq); +} + +static inline int mc13783_unmask(struct mc13783 *mc13783, int irq) __deprecated; +static inline int mc13783_unmask(struct mc13783 *mc13783, int irq) +{ + return mc13783_irq_unmask(mc13783, irq); +} + +static inline int mc13783_ackirq(struct mc13783 *mc13783, int irq) __deprecated; +static inline int mc13783_ackirq(struct mc13783 *mc13783, int irq) +{ + return mc13783_irq_ack(mc13783, irq); +} #define MC13783_ADC0 43 #define MC13783_ADC0_ADREFEN (1 << 10) -- cgit v1.2.3 From 2a83319182afe9ba7d958180b3bd3a32a9e3d1be Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 5 Mar 2010 13:44:26 -0800 Subject: input/mc13783-ts: don't use deprecated mc13783 API calls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mc13783_ackirq is deprecated, use the drop in replacement mc13783_irq_ack. Signed-off-by: Uwe Kleine-König Cc: Alessandro Zummo Cc: Paul Gortmaker Cc: Valentin Longchamp Cc: Sascha Hauer Cc: Samuel Ortiz Acked-by: Dmitry Torokhov Cc: Luotao Fu Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/input/touchscreen/mc13783_ts.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/input/touchscreen/mc13783_ts.c b/drivers/input/touchscreen/mc13783_ts.c index be115b3b65eb..be54fd639aca 100644 --- a/drivers/input/touchscreen/mc13783_ts.c +++ b/drivers/input/touchscreen/mc13783_ts.c @@ -44,7 +44,7 @@ static irqreturn_t mc13783_ts_handler(int irq, void *data) { struct mc13783_ts_priv *priv = data; - mc13783_ackirq(priv->mc13783, irq); + mc13783_irq_ack(priv->mc13783, irq); /* * Kick off reading coordinates. Note that if work happens already @@ -135,7 +135,7 @@ static int mc13783_ts_open(struct input_dev *dev) mc13783_lock(priv->mc13783); - mc13783_ackirq(priv->mc13783, MC13783_IRQ_TS); + mc13783_irq_ack(priv->mc13783, MC13783_IRQ_TS); ret = mc13783_irq_request(priv->mc13783, MC13783_IRQ_TS, mc13783_ts_handler, MC13783_TS_NAME, priv); -- cgit v1.2.3 From 4dd4dd655cedb7c5c0bf45bc1d012ebbe21e8319 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 5 Mar 2010 13:44:28 -0800 Subject: rtc/mc13783: don't use deprecated mc13783 API calls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mc13783_ackirq, mc13783_unmask and mc13783_mask are deprecated, use the drop in replacements with the nicer names. Signed-off-by: Uwe Kleine-König Cc: Alessandro Zummo Cc: Paul Gortmaker Cc: Valentin Longchamp Cc: Sascha Hauer Cc: Samuel Ortiz Cc: Dmitry Torokhov Cc: Luotao Fu Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/rtc/rtc-mc13783.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/rtc-mc13783.c b/drivers/rtc/rtc-mc13783.c index 850f983c039c..0a978a0e40fc 100644 --- a/drivers/rtc/rtc-mc13783.c +++ b/drivers/rtc/rtc-mc13783.c @@ -101,11 +101,11 @@ static int mc13783_rtc_set_mmss(struct device *dev, unsigned long secs) if (unlikely(ret)) goto out; - ret = mc13783_ackirq(priv->mc13783, MC13783_IRQ_RTCRST); + ret = mc13783_irq_ack(priv->mc13783, MC13783_IRQ_RTCRST); if (unlikely(ret)) goto out; - ret = mc13783_unmask(priv->mc13783, MC13783_IRQ_RTCRST); + ret = mc13783_irq_unmask(priv->mc13783, MC13783_IRQ_RTCRST); out: priv->valid = !ret; @@ -123,7 +123,7 @@ static irqreturn_t mc13783_rtc_update_handler(int irq, void *dev) rtc_update_irq(priv->rtc, 1, RTC_IRQF | RTC_UF); - mc13783_ackirq(mc13783, irq); + mc13783_irq_ack(mc13783, irq); return IRQ_HANDLED; } @@ -138,7 +138,7 @@ static int mc13783_rtc_update_irq_enable(struct device *dev, if (!priv->valid) goto out; - ret = (enabled ? mc13783_unmask : mc13783_mask)(priv->mc13783, + ret = (enabled ? mc13783_irq_unmask : mc13783_irq_mask)(priv->mc13783, MC13783_IRQ_1HZ); out: mc13783_unlock(priv->mc13783); @@ -160,7 +160,7 @@ static irqreturn_t mc13783_rtc_reset_handler(int irq, void *dev) dev_dbg(&priv->rtc->dev, "RTCRST\n"); priv->valid = 0; - mc13783_mask(mc13783, irq); + mc13783_irq_mask(mc13783, irq); return IRQ_HANDLED; } -- cgit v1.2.3 From 86c3400810a7a33e176bf33b6b074d881e829374 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 5 Mar 2010 13:44:29 -0800 Subject: mfd/mc13783: new function reading irq mask and status register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The driver for the mc13783 rtc needs to know if the TODA irq is pending. Instead of tracking in the rtc driver if the irq is enabled provide that information, too. Signed-off-by: Uwe Kleine-König Cc: Alessandro Zummo Cc: Paul Gortmaker Cc: Valentin Longchamp Cc: Sascha Hauer Cc: Samuel Ortiz Cc: Dmitry Torokhov Cc: Luotao Fu Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mfd/mc13783-core.c | 35 +++++++++++++++++++++++++++++++++++ include/linux/mfd/mc13783.h | 2 ++ 2 files changed, 37 insertions(+) (limited to 'drivers') diff --git a/drivers/mfd/mc13783-core.c b/drivers/mfd/mc13783-core.c index a2bd44552042..62a847e4c2d8 100644 --- a/drivers/mfd/mc13783-core.c +++ b/drivers/mfd/mc13783-core.c @@ -269,6 +269,41 @@ int mc13783_irq_unmask(struct mc13783 *mc13783, int irq) } EXPORT_SYMBOL(mc13783_irq_unmask); +int mc13783_irq_status(struct mc13783 *mc13783, int irq, + int *enabled, int *pending) +{ + int ret; + unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1; + unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1; + u32 irqbit = 1 << (irq < 24 ? irq : irq - 24); + + if (irq < 0 || irq >= MC13783_NUM_IRQ) + return -EINVAL; + + if (enabled) { + u32 mask; + + ret = mc13783_reg_read(mc13783, offmask, &mask); + if (ret) + return ret; + + *enabled = mask & irqbit; + } + + if (pending) { + u32 stat; + + ret = mc13783_reg_read(mc13783, offstat, &stat); + if (ret) + return ret; + + *pending = stat & irqbit; + } + + return 0; +} +EXPORT_SYMBOL(mc13783_irq_status); + int mc13783_irq_ack(struct mc13783 *mc13783, int irq) { unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1; diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h index b8b9f3b4f3e2..8895d9d8879c 100644 --- a/include/linux/mfd/mc13783.h +++ b/include/linux/mfd/mc13783.h @@ -29,6 +29,8 @@ int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev); int mc13783_irq_mask(struct mc13783 *mc13783, int irq); int mc13783_irq_unmask(struct mc13783 *mc13783, int irq); +int mc13783_irq_status(struct mc13783 *mc13783, int irq, + int *enabled, int *pending); int mc13783_irq_ack(struct mc13783 *mc13783, int irq); static inline int mc13783_mask(struct mc13783 *mc13783, int irq) __deprecated; -- cgit v1.2.3 From 4c014e872e02baa5b0bde38b2b2867ccf1f9df76 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 5 Mar 2010 13:44:30 -0800 Subject: rtc/mc13783: protect rtc {,un}registration by mc13783 lock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is to protect from interrupt handlers using an unregistered rtc device. To assert that the reset irq is considered now before the rtc is registered the corresponding status is checked before. Signed-off-by: Uwe Kleine-König Cc: Alessandro Zummo Cc: Paul Gortmaker Cc: Valentin Longchamp Cc: Sascha Hauer Cc: Samuel Ortiz Cc: Dmitry Torokhov Cc: Luotao Fu Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/rtc/rtc-mc13783.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/rtc-mc13783.c b/drivers/rtc/rtc-mc13783.c index 0a978a0e40fc..6a36201178a8 100644 --- a/drivers/rtc/rtc-mc13783.c +++ b/drivers/rtc/rtc-mc13783.c @@ -169,6 +169,7 @@ static int __devinit mc13783_rtc_probe(struct platform_device *pdev) { int ret; struct mc13783_rtc *priv; + int rtcrst_pending; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) @@ -177,8 +178,6 @@ static int __devinit mc13783_rtc_probe(struct platform_device *pdev) priv->mc13783 = dev_get_drvdata(pdev->dev.parent); platform_set_drvdata(pdev, priv); - priv->valid = 1; - mc13783_lock(priv->mc13783); ret = mc13783_irq_request(priv->mc13783, MC13783_IRQ_RTCRST, @@ -186,33 +185,37 @@ static int __devinit mc13783_rtc_probe(struct platform_device *pdev) if (ret) goto err_reset_irq_request; + ret = mc13783_irq_status(priv->mc13783, MC13783_IRQ_RTCRST, + NULL, &rtcrst_pending); + if (ret) + goto err_reset_irq_status; + + priv->valid = !rtcrst_pending; + ret = mc13783_irq_request_nounmask(priv->mc13783, MC13783_IRQ_1HZ, mc13783_rtc_update_handler, DRIVER_NAME, priv); if (ret) goto err_update_irq_request; - mc13783_unlock(priv->mc13783); - priv->rtc = rtc_device_register(pdev->name, &pdev->dev, &mc13783_rtc_ops, THIS_MODULE); - if (IS_ERR(priv->rtc)) { ret = PTR_ERR(priv->rtc); - mc13783_lock(priv->mc13783); - mc13783_irq_free(priv->mc13783, MC13783_IRQ_1HZ, priv); err_update_irq_request: +err_reset_irq_status: + mc13783_irq_free(priv->mc13783, MC13783_IRQ_RTCRST, priv); err_reset_irq_request: - mc13783_unlock(priv->mc13783); - platform_set_drvdata(pdev, NULL); kfree(priv); } + mc13783_unlock(priv->mc13783); + return ret; } @@ -220,10 +223,10 @@ static int __devexit mc13783_rtc_remove(struct platform_device *pdev) { struct mc13783_rtc *priv = platform_get_drvdata(pdev); - rtc_device_unregister(priv->rtc); - mc13783_lock(priv->mc13783); + rtc_device_unregister(priv->rtc); + mc13783_irq_free(priv->mc13783, MC13783_IRQ_1HZ, priv); mc13783_irq_free(priv->mc13783, MC13783_IRQ_RTCRST, priv); -- cgit v1.2.3 From 9407351d7cce01a9ada942f00201e92e2541d9cb Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 5 Mar 2010 13:44:30 -0800 Subject: rtc/mc13783: implement alarm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Cc: Alessandro Zummo Cc: Paul Gortmaker Cc: Valentin Longchamp Cc: Sascha Hauer Cc: Samuel Ortiz Cc: Dmitry Torokhov Cc: Luotao Fu Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/rtc/rtc-mc13783.c | 185 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 172 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/rtc-mc13783.c b/drivers/rtc/rtc-mc13783.c index 6a36201178a8..d60c81b7b693 100644 --- a/drivers/rtc/rtc-mc13783.c +++ b/drivers/rtc/rtc-mc13783.c @@ -28,6 +28,34 @@ struct mc13783_rtc { int valid; }; +static int mc13783_rtc_irq_enable_unlocked(struct device *dev, + unsigned int enabled, int irq) +{ + struct mc13783_rtc *priv = dev_get_drvdata(dev); + int (*func)(struct mc13783 *mc13783, int irq); + + if (!priv->valid) + return -ENODATA; + + func = enabled ? mc13783_irq_unmask : mc13783_irq_mask; + return func(priv->mc13783, irq); +} + +static int mc13783_rtc_irq_enable(struct device *dev, + unsigned int enabled, int irq) +{ + struct mc13783_rtc *priv = dev_get_drvdata(dev); + int ret; + + mc13783_lock(priv->mc13783); + + ret = mc13783_rtc_irq_enable_unlocked(dev, enabled, irq); + + mc13783_unlock(priv->mc13783); + + return ret; +} + static int mc13783_rtc_read_time(struct device *dev, struct rtc_time *tm) { struct mc13783_rtc *priv = dev_get_drvdata(dev); @@ -78,6 +106,7 @@ static int mc13783_rtc_set_mmss(struct device *dev, unsigned long secs) { struct mc13783_rtc *priv = dev_get_drvdata(dev); unsigned int seconds, days; + unsigned int alarmseconds; int ret; seconds = secs % 86400; @@ -86,7 +115,22 @@ static int mc13783_rtc_set_mmss(struct device *dev, unsigned long secs) mc13783_lock(priv->mc13783); /* - * first write seconds=0 to prevent a day switch between writing days + * temporarily invalidate alarm to prevent triggering it when the day is + * already updated while the time isn't yet. + */ + ret = mc13783_reg_read(priv->mc13783, MC13783_RTCTODA, &alarmseconds); + if (unlikely(ret)) + goto out; + + if (alarmseconds < 86400) { + ret = mc13783_reg_write(priv->mc13783, + MC13783_RTCTODA, 0x1ffff); + if (unlikely(ret)) + goto out; + } + + /* + * write seconds=0 to prevent a day switch between writing days * and seconds below */ ret = mc13783_reg_write(priv->mc13783, MC13783_RTCTOD, 0); @@ -101,6 +145,14 @@ static int mc13783_rtc_set_mmss(struct device *dev, unsigned long secs) if (unlikely(ret)) goto out; + /* restore alarm */ + if (alarmseconds < 86400) { + ret = mc13783_reg_write(priv->mc13783, + MC13783_RTCTODA, alarmseconds); + if (unlikely(ret)) + goto out; + } + ret = mc13783_irq_ack(priv->mc13783, MC13783_IRQ_RTCRST); if (unlikely(ret)) goto out; @@ -114,6 +166,107 @@ out: return ret; } +static int mc13783_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct mc13783_rtc *priv = dev_get_drvdata(dev); + unsigned seconds, days; + unsigned long s1970; + int enabled, pending; + int ret; + + mc13783_lock(priv->mc13783); + + ret = mc13783_reg_read(priv->mc13783, MC13783_RTCTODA, &seconds); + if (unlikely(ret)) + goto out; + if (seconds >= 86400) { + ret = -ENODATA; + goto out; + } + + ret = mc13783_reg_read(priv->mc13783, MC13783_RTCDAY, &days); + if (unlikely(ret)) + goto out; + + ret = mc13783_irq_status(priv->mc13783, MC13783_IRQ_TODA, + &enabled, &pending); + +out: + mc13783_unlock(priv->mc13783); + + if (ret) + return ret; + + alarm->enabled = enabled; + alarm->pending = pending; + + s1970 = days * 86400 + seconds; + + rtc_time_to_tm(s1970, &alarm->time); + dev_dbg(dev, "%s: %lu\n", __func__, s1970); + + return 0; +} + +static int mc13783_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct mc13783_rtc *priv = dev_get_drvdata(dev); + unsigned long s1970; + unsigned seconds, days; + int ret; + + mc13783_lock(priv->mc13783); + + /* disable alarm to prevent false triggering */ + ret = mc13783_reg_write(priv->mc13783, MC13783_RTCTODA, 0x1ffff); + if (unlikely(ret)) + goto out; + + ret = mc13783_irq_ack(priv->mc13783, MC13783_IRQ_TODA); + if (unlikely(ret)) + goto out; + + ret = rtc_tm_to_time(&alarm->time, &s1970); + if (unlikely(ret)) + goto out; + + dev_dbg(dev, "%s: o%2.s %lu\n", __func__, alarm->enabled ? "n" : "ff", + s1970); + + ret = mc13783_rtc_irq_enable_unlocked(dev, alarm->enabled, + MC13783_IRQ_TODA); + if (unlikely(ret)) + goto out; + + seconds = s1970 % 86400; + days = s1970 / 86400; + + ret = mc13783_reg_write(priv->mc13783, MC13783_RTCDAYA, days); + if (unlikely(ret)) + goto out; + + ret = mc13783_reg_write(priv->mc13783, MC13783_RTCTODA, seconds); + +out: + mc13783_unlock(priv->mc13783); + + return ret; +} + +static irqreturn_t mc13783_rtc_alarm_handler(int irq, void *dev) +{ + struct mc13783_rtc *priv = dev; + struct mc13783 *mc13783 = priv->mc13783; + + dev_dbg(&priv->rtc->dev, "Alarm\n"); + + rtc_update_irq(priv->rtc, 1, RTC_IRQF | RTC_AF); + + mc13783_irq_ack(mc13783, irq); + + return IRQ_HANDLED; +} + static irqreturn_t mc13783_rtc_update_handler(int irq, void *dev) { struct mc13783_rtc *priv = dev; @@ -131,24 +284,21 @@ static irqreturn_t mc13783_rtc_update_handler(int irq, void *dev) static int mc13783_rtc_update_irq_enable(struct device *dev, unsigned int enabled) { - struct mc13783_rtc *priv = dev_get_drvdata(dev); - int ret = -ENODATA; - - mc13783_lock(priv->mc13783); - if (!priv->valid) - goto out; - - ret = (enabled ? mc13783_irq_unmask : mc13783_irq_mask)(priv->mc13783, - MC13783_IRQ_1HZ); -out: - mc13783_unlock(priv->mc13783); + return mc13783_rtc_irq_enable(dev, enabled, MC13783_IRQ_1HZ); +} - return ret; +static int mc13783_rtc_alarm_irq_enable(struct device *dev, + unsigned int enabled) +{ + return mc13783_rtc_irq_enable(dev, enabled, MC13783_IRQ_TODA); } static const struct rtc_class_ops mc13783_rtc_ops = { .read_time = mc13783_rtc_read_time, .set_mmss = mc13783_rtc_set_mmss, + .read_alarm = mc13783_rtc_read_alarm, + .set_alarm = mc13783_rtc_set_alarm, + .alarm_irq_enable = mc13783_rtc_alarm_irq_enable, .update_irq_enable = mc13783_rtc_update_irq_enable, }; @@ -197,11 +347,19 @@ static int __devinit mc13783_rtc_probe(struct platform_device *pdev) if (ret) goto err_update_irq_request; + ret = mc13783_irq_request_nounmask(priv->mc13783, MC13783_IRQ_TODA, + mc13783_rtc_alarm_handler, DRIVER_NAME, priv); + if (ret) + goto err_alarm_irq_request; + priv->rtc = rtc_device_register(pdev->name, &pdev->dev, &mc13783_rtc_ops, THIS_MODULE); if (IS_ERR(priv->rtc)) { ret = PTR_ERR(priv->rtc); + mc13783_irq_free(priv->mc13783, MC13783_IRQ_TODA, priv); +err_alarm_irq_request: + mc13783_irq_free(priv->mc13783, MC13783_IRQ_1HZ, priv); err_update_irq_request: @@ -227,6 +385,7 @@ static int __devexit mc13783_rtc_remove(struct platform_device *pdev) rtc_device_unregister(priv->rtc); + mc13783_irq_free(priv->mc13783, MC13783_IRQ_TODA, priv); mc13783_irq_free(priv->mc13783, MC13783_IRQ_1HZ, priv); mc13783_irq_free(priv->mc13783, MC13783_IRQ_RTCRST, priv); -- cgit v1.2.3 From 5a98c04d78c896d52baef20ffc11f6d1ba6eb786 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Fri, 5 Mar 2010 13:44:31 -0800 Subject: rtc-coh901331: fix braces in resume code The else part of the if statement is indented but does not have braces around it. It clearly should since it uses clk_enable and clk_disable which are supposed to balance. Signed-off-by: James Hogan Acked-by: Linus Walleij Acked-by: Alessandro Zummo Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/rtc/rtc-coh901331.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/rtc-coh901331.c b/drivers/rtc/rtc-coh901331.c index 03ea530981d1..44c4399ee714 100644 --- a/drivers/rtc/rtc-coh901331.c +++ b/drivers/rtc/rtc-coh901331.c @@ -271,12 +271,13 @@ static int coh901331_resume(struct platform_device *pdev) { struct coh901331_port *rtap = dev_get_drvdata(&pdev->dev); - if (device_may_wakeup(&pdev->dev)) + if (device_may_wakeup(&pdev->dev)) { disable_irq_wake(rtap->irq); - else + } else { clk_enable(rtap->clk); writel(rtap->irqmaskstore, rtap->virtbase + COH901331_IRQ_MASK); clk_disable(rtap->clk); + } return 0; } #else -- cgit v1.2.3 From e952805d2d2e706aed182723e5ab3ec0b1f91de3 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 5 Mar 2010 13:44:33 -0800 Subject: gpio: add driver for MAX7300 I2C GPIO extender Add the MAX7300-I2C variant of the MAX7301-SPI version. Both chips share the same core logic, so the generic part of the in-kernel SPI-driver is refactored into a generic part. The I2C and SPI specific funtions are then wrapped into seperate drivers picking up the generic part. Signed-off-by: Wolfram Sang Cc: Juergen Beisert Cc: David Brownell Cc: Jean Delvare Cc: Anton Vorontsov Cc: Randy Dunlap Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/gpio/Kconfig | 13 +- drivers/gpio/Makefile | 2 + drivers/gpio/max7300.c | 94 ++++++++++++++ drivers/gpio/max7301.c | 293 +++++--------------------------------------- drivers/gpio/max730x.c | 244 ++++++++++++++++++++++++++++++++++++ include/linux/spi/max7301.h | 18 +++ 6 files changed, 404 insertions(+), 260 deletions(-) create mode 100644 drivers/gpio/max7300.c create mode 100644 drivers/gpio/max730x.c (limited to 'drivers') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1f1d88ae68d6..f3549b8779d8 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -65,6 +65,9 @@ config GPIO_SYSFS # put expanders in the right section, in alphabetical order +config GPIO_MAX730X + tristate + comment "Memory mapped GPIO expanders:" config GPIO_PL061 @@ -87,6 +90,13 @@ config GPIO_VR41XX comment "I2C GPIO expanders:" +config GPIO_MAX7300 + tristate "Maxim MAX7300 GPIO expander" + depends on I2C + select GPIO_MAX730X + help + GPIO driver for Maxim MAX7301 I2C-based GPIO expander. + config GPIO_MAX732X tristate "MAX7319, MAX7320-7327 I2C Port Expanders" depends on I2C @@ -226,8 +236,9 @@ comment "SPI GPIO expanders:" config GPIO_MAX7301 tristate "Maxim MAX7301 GPIO expander" depends on SPI_MASTER + select GPIO_MAX730X help - gpio driver for Maxim MAX7301 SPI GPIO expander. + GPIO driver for Maxim MAX7301 SPI-based GPIO expander. config GPIO_MCP23S08 tristate "Microchip MCP23S08 I/O expander" diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 48687238edb1..508a1b202cdb 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -7,6 +7,8 @@ obj-$(CONFIG_GPIOLIB) += gpiolib.o obj-$(CONFIG_GPIO_ADP5520) += adp5520-gpio.o obj-$(CONFIG_GPIO_ADP5588) += adp5588-gpio.o obj-$(CONFIG_GPIO_LANGWELL) += langwell_gpio.o +obj-$(CONFIG_GPIO_MAX730X) += max730x.o +obj-$(CONFIG_GPIO_MAX7300) += max7300.o obj-$(CONFIG_GPIO_MAX7301) += max7301.o obj-$(CONFIG_GPIO_MAX732X) += max732x.o obj-$(CONFIG_GPIO_MC33880) += mc33880.o diff --git a/drivers/gpio/max7300.c b/drivers/gpio/max7300.c new file mode 100644 index 000000000000..9d74eef1157a --- /dev/null +++ b/drivers/gpio/max7300.c @@ -0,0 +1,94 @@ +/* + * drivers/gpio/max7300.c + * + * Copyright (C) 2009 Wolfram Sang, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Check max730x.c for further details. + */ + +#include +#include +#include +#include +#include +#include + +static int max7300_i2c_write(struct device *dev, unsigned int reg, + unsigned int val) +{ + struct i2c_client *client = to_i2c_client(dev); + + return i2c_smbus_write_byte_data(client, reg, val); +} + +static int max7300_i2c_read(struct device *dev, unsigned int reg) +{ + struct i2c_client *client = to_i2c_client(dev); + + return i2c_smbus_read_byte_data(client, reg); +} + +static int __devinit max7300_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct max7301 *ts; + int ret; + + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_BYTE_DATA)) + return -EIO; + + ts = kzalloc(sizeof(struct max7301), GFP_KERNEL); + if (!ts) + return -ENOMEM; + + ts->read = max7300_i2c_read; + ts->write = max7300_i2c_write; + ts->dev = &client->dev; + + ret = __max730x_probe(ts); + if (ret) + kfree(ts); + return ret; +} + +static int __devexit max7300_remove(struct i2c_client *client) +{ + return __max730x_remove(&client->dev); +} + +static const struct i2c_device_id max7300_id[] = { + { "max7300", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, max7300_id); + +static struct i2c_driver max7300_driver = { + .driver = { + .name = "max7300", + .owner = THIS_MODULE, + }, + .probe = max7300_probe, + .remove = __devexit_p(max7300_remove), + .id_table = max7300_id, +}; + +static int __init max7300_init(void) +{ + return i2c_add_driver(&max7300_driver); +} +subsys_initcall(max7300_init); + +static void __exit max7300_exit(void) +{ + i2c_del_driver(&max7300_driver); +} +module_exit(max7300_exit); + +MODULE_AUTHOR("Wolfram Sang"); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MAX7300 GPIO-Expander"); diff --git a/drivers/gpio/max7301.c b/drivers/gpio/max7301.c index 480956f1ca50..965d9b1ea13e 100644 --- a/drivers/gpio/max7301.c +++ b/drivers/gpio/max7301.c @@ -1,98 +1,41 @@ -/** +/* * drivers/gpio/max7301.c * * Copyright (C) 2006 Juergen Beisert, Pengutronix * Copyright (C) 2008 Guennadi Liakhovetski, Pengutronix + * Copyright (C) 2009 Wolfram Sang, Pengutronix * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * The Maxim's MAX7301 device is an SPI driven GPIO expander. There are - * 28 GPIOs. 8 of them can trigger an interrupt. See datasheet for more - * details - * Note: - * - DIN must be stable at the rising edge of clock. - * - when writing: - * - always clock in 16 clocks at once - * - at DIN: D15 first, D0 last - * - D0..D7 = databyte, D8..D14 = commandbyte - * - D15 = low -> write command - * - when reading - * - always clock in 16 clocks at once - * - at DIN: D15 first, D0 last - * - D0..D7 = dummy, D8..D14 = register address - * - D15 = high -> read command - * - raise CS and assert it again - * - always clock in 16 clocks at once - * - at DOUT: D15 first, D0 last - * - D0..D7 contains the data from the first cycle - * - * The driver exports a standard gpiochip interface + * Check max730x.c for further details. */ +#include #include #include #include #include #include -#include - -#define DRIVER_NAME "max7301" - -/* - * Pin configurations, see MAX7301 datasheet page 6 - */ -#define PIN_CONFIG_MASK 0x03 -#define PIN_CONFIG_IN_PULLUP 0x03 -#define PIN_CONFIG_IN_WO_PULLUP 0x02 -#define PIN_CONFIG_OUT 0x01 - -#define PIN_NUMBER 28 - - -/* - * Some registers must be read back to modify. - * To save time we cache them here in memory - */ -struct max7301 { - struct mutex lock; - u8 port_config[8]; /* field 0 is unused */ - u32 out_level; /* cached output levels */ - struct gpio_chip chip; - struct spi_device *spi; -}; -/** - * max7301_write - Write a new register content - * @spi: The SPI device - * @reg: Register offset - * @val: Value to write - * - * A write to the MAX7301 means one message with one transfer - * - * Returns 0 if successful or a negative value on error - */ -static int max7301_write(struct spi_device *spi, unsigned int reg, unsigned int val) +/* A write to the MAX7301 means one message with one transfer */ +static int max7301_spi_write(struct device *dev, unsigned int reg, + unsigned int val) { + struct spi_device *spi = to_spi_device(dev); u16 word = ((reg & 0x7F) << 8) | (val & 0xFF); + return spi_write(spi, (const u8 *)&word, sizeof(word)); } -/** - * max7301_read - Read back register content - * @spi: The SPI device - * @reg: Register offset - * - * A read from the MAX7301 means two transfers; here, one message each - * - * Returns positive 8 bit value from device if successful or a - * negative value on error - */ -static int max7301_read(struct spi_device *spi, unsigned int reg) +/* A read from the MAX7301 means two transfers; here, one message each */ + +static int max7301_spi_read(struct device *dev, unsigned int reg) { int ret; u16 word; + struct spi_device *spi = to_spi_device(dev); word = 0x8000 | (reg << 8); ret = spi_write(spi, (const u8 *)&word, sizeof(word)); @@ -108,125 +51,13 @@ static int max7301_read(struct spi_device *spi, unsigned int reg) return word & 0xff; } -static int max7301_direction_input(struct gpio_chip *chip, unsigned offset) -{ - struct max7301 *ts = container_of(chip, struct max7301, chip); - u8 *config; - int ret; - - /* First 4 pins are unused in the controller */ - offset += 4; - - config = &ts->port_config[offset >> 2]; - - mutex_lock(&ts->lock); - - /* Standard GPIO API doesn't support pull-ups, has to be extended. - * Hard-coding no pollup for now. */ - *config = (*config & ~(3 << (offset & 3))) | (1 << (offset & 3)); - - ret = max7301_write(ts->spi, 0x08 + (offset >> 2), *config); - - mutex_unlock(&ts->lock); - - return ret; -} - -static int __max7301_set(struct max7301 *ts, unsigned offset, int value) -{ - if (value) { - ts->out_level |= 1 << offset; - return max7301_write(ts->spi, 0x20 + offset, 0x01); - } else { - ts->out_level &= ~(1 << offset); - return max7301_write(ts->spi, 0x20 + offset, 0x00); - } -} - -static int max7301_direction_output(struct gpio_chip *chip, unsigned offset, - int value) -{ - struct max7301 *ts = container_of(chip, struct max7301, chip); - u8 *config; - int ret; - - /* First 4 pins are unused in the controller */ - offset += 4; - - config = &ts->port_config[offset >> 2]; - - mutex_lock(&ts->lock); - - *config = (*config & ~(3 << (offset & 3))) | (1 << (offset & 3)); - - ret = __max7301_set(ts, offset, value); - - if (!ret) - ret = max7301_write(ts->spi, 0x08 + (offset >> 2), *config); - - mutex_unlock(&ts->lock); - - return ret; -} - -static int max7301_get(struct gpio_chip *chip, unsigned offset) -{ - struct max7301 *ts = container_of(chip, struct max7301, chip); - int config, level = -EINVAL; - - /* First 4 pins are unused in the controller */ - offset += 4; - - mutex_lock(&ts->lock); - - config = (ts->port_config[offset >> 2] >> ((offset & 3) * 2)) & 3; - - switch (config) { - case 1: - /* Output: return cached level */ - level = !!(ts->out_level & (1 << offset)); - break; - case 2: - case 3: - /* Input: read out */ - level = max7301_read(ts->spi, 0x20 + offset) & 0x01; - } - mutex_unlock(&ts->lock); - - return level; -} - -static void max7301_set(struct gpio_chip *chip, unsigned offset, int value) -{ - struct max7301 *ts = container_of(chip, struct max7301, chip); - - /* First 4 pins are unused in the controller */ - offset += 4; - - mutex_lock(&ts->lock); - - __max7301_set(ts, offset, value); - - mutex_unlock(&ts->lock); -} - static int __devinit max7301_probe(struct spi_device *spi) { struct max7301 *ts; - struct max7301_platform_data *pdata; - int i, ret; - - pdata = spi->dev.platform_data; - if (!pdata || !pdata->base) { - dev_dbg(&spi->dev, "incorrect or missing platform data\n"); - return -EINVAL; - } + int ret; - /* - * bits_per_word cannot be configured in platform data - */ + /* bits_per_word cannot be configured in platform data */ spi->bits_per_word = 16; - ret = spi_setup(spi); if (ret < 0) return ret; @@ -235,90 +66,35 @@ static int __devinit max7301_probe(struct spi_device *spi) if (!ts) return -ENOMEM; - mutex_init(&ts->lock); - - dev_set_drvdata(&spi->dev, ts); + ts->read = max7301_spi_read; + ts->write = max7301_spi_write; + ts->dev = &spi->dev; - /* Power up the chip and disable IRQ output */ - max7301_write(spi, 0x04, 0x01); - - ts->spi = spi; - - ts->chip.label = DRIVER_NAME, - - ts->chip.direction_input = max7301_direction_input; - ts->chip.get = max7301_get; - ts->chip.direction_output = max7301_direction_output; - ts->chip.set = max7301_set; - - ts->chip.base = pdata->base; - ts->chip.ngpio = PIN_NUMBER; - ts->chip.can_sleep = 1; - ts->chip.dev = &spi->dev; - ts->chip.owner = THIS_MODULE; - - /* - * tristate all pins in hardware and cache the - * register values for later use. - */ - for (i = 1; i < 8; i++) { - int j; - /* 0xAA means input with internal pullup disabled */ - max7301_write(spi, 0x08 + i, 0xAA); - ts->port_config[i] = 0xAA; - for (j = 0; j < 4; j++) { - int offset = (i - 1) * 4 + j; - ret = max7301_direction_input(&ts->chip, offset); - if (ret) - goto exit_destroy; - } - } - - ret = gpiochip_add(&ts->chip); + ret = __max730x_probe(ts); if (ret) - goto exit_destroy; - - return ret; - -exit_destroy: - dev_set_drvdata(&spi->dev, NULL); - mutex_destroy(&ts->lock); - kfree(ts); + kfree(ts); return ret; } static int __devexit max7301_remove(struct spi_device *spi) { - struct max7301 *ts; - int ret; - - ts = dev_get_drvdata(&spi->dev); - if (ts == NULL) - return -ENODEV; - - dev_set_drvdata(&spi->dev, NULL); - - /* Power down the chip and disable IRQ output */ - max7301_write(spi, 0x04, 0x00); - - ret = gpiochip_remove(&ts->chip); - if (!ret) { - mutex_destroy(&ts->lock); - kfree(ts); - } else - dev_err(&spi->dev, "Failed to remove the GPIO controller: %d\n", - ret); - - return ret; + return __max730x_remove(&spi->dev); } +static const struct spi_device_id max7301_id[] = { + { "max7301", 0 }, + { } +}; +MODULE_DEVICE_TABLE(spi, max7301_id); + static struct spi_driver max7301_driver = { .driver = { - .name = DRIVER_NAME, - .owner = THIS_MODULE, + .name = "max7301", + .owner = THIS_MODULE, }, - .probe = max7301_probe, - .remove = __devexit_p(max7301_remove), + .probe = max7301_probe, + .remove = __devexit_p(max7301_remove), + .id_table = max7301_id, }; static int __init max7301_init(void) @@ -336,7 +112,6 @@ static void __exit max7301_exit(void) } module_exit(max7301_exit); -MODULE_AUTHOR("Juergen Beisert"); +MODULE_AUTHOR("Juergen Beisert, Wolfram Sang"); MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("MAX7301 SPI based GPIO-Expander"); -MODULE_ALIAS("spi:" DRIVER_NAME); +MODULE_DESCRIPTION("MAX7301 GPIO-Expander"); diff --git a/drivers/gpio/max730x.c b/drivers/gpio/max730x.c new file mode 100644 index 000000000000..c9bced55f82b --- /dev/null +++ b/drivers/gpio/max730x.c @@ -0,0 +1,244 @@ +/** + * drivers/gpio/max7301.c + * + * Copyright (C) 2006 Juergen Beisert, Pengutronix + * Copyright (C) 2008 Guennadi Liakhovetski, Pengutronix + * Copyright (C) 2009 Wolfram Sang, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * The Maxim MAX7300/1 device is an I2C/SPI driven GPIO expander. There are + * 28 GPIOs. 8 of them can trigger an interrupt. See datasheet for more + * details + * Note: + * - DIN must be stable at the rising edge of clock. + * - when writing: + * - always clock in 16 clocks at once + * - at DIN: D15 first, D0 last + * - D0..D7 = databyte, D8..D14 = commandbyte + * - D15 = low -> write command + * - when reading + * - always clock in 16 clocks at once + * - at DIN: D15 first, D0 last + * - D0..D7 = dummy, D8..D14 = register address + * - D15 = high -> read command + * - raise CS and assert it again + * - always clock in 16 clocks at once + * - at DOUT: D15 first, D0 last + * - D0..D7 contains the data from the first cycle + * + * The driver exports a standard gpiochip interface + */ + +#include +#include +#include +#include +#include +#include + +/* + * Pin configurations, see MAX7301 datasheet page 6 + */ +#define PIN_CONFIG_MASK 0x03 +#define PIN_CONFIG_IN_PULLUP 0x03 +#define PIN_CONFIG_IN_WO_PULLUP 0x02 +#define PIN_CONFIG_OUT 0x01 + +#define PIN_NUMBER 28 + +static int max7301_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct max7301 *ts = container_of(chip, struct max7301, chip); + u8 *config; + u8 offset_bits; + int ret; + + /* First 4 pins are unused in the controller */ + offset += 4; + offset_bits = (offset & 3) << 1; + + config = &ts->port_config[offset >> 2]; + + mutex_lock(&ts->lock); + + /* Standard GPIO API doesn't support pull-ups, has to be extended. + * Hard-coding no pollup for now. */ + *config = (*config & ~(PIN_CONFIG_MASK << offset_bits)) + | (PIN_CONFIG_IN_WO_PULLUP << offset_bits); + + ret = ts->write(ts->dev, 0x08 + (offset >> 2), *config); + + mutex_unlock(&ts->lock); + + return ret; +} + +static int __max7301_set(struct max7301 *ts, unsigned offset, int value) +{ + if (value) { + ts->out_level |= 1 << offset; + return ts->write(ts->dev, 0x20 + offset, 0x01); + } else { + ts->out_level &= ~(1 << offset); + return ts->write(ts->dev, 0x20 + offset, 0x00); + } +} + +static int max7301_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct max7301 *ts = container_of(chip, struct max7301, chip); + u8 *config; + u8 offset_bits; + int ret; + + /* First 4 pins are unused in the controller */ + offset += 4; + offset_bits = (offset & 3) << 1; + + config = &ts->port_config[offset >> 2]; + + mutex_lock(&ts->lock); + + *config = (*config & ~(PIN_CONFIG_MASK << offset_bits)) + | (PIN_CONFIG_OUT << offset_bits); + + ret = __max7301_set(ts, offset, value); + + if (!ret) + ret = ts->write(ts->dev, 0x08 + (offset >> 2), *config); + + mutex_unlock(&ts->lock); + + return ret; +} + +static int max7301_get(struct gpio_chip *chip, unsigned offset) +{ + struct max7301 *ts = container_of(chip, struct max7301, chip); + int config, level = -EINVAL; + + /* First 4 pins are unused in the controller */ + offset += 4; + + mutex_lock(&ts->lock); + + config = (ts->port_config[offset >> 2] >> ((offset & 3) << 1)) + & PIN_CONFIG_MASK; + + switch (config) { + case PIN_CONFIG_OUT: + /* Output: return cached level */ + level = !!(ts->out_level & (1 << offset)); + break; + case PIN_CONFIG_IN_WO_PULLUP: + case PIN_CONFIG_IN_PULLUP: + /* Input: read out */ + level = ts->read(ts->dev, 0x20 + offset) & 0x01; + } + mutex_unlock(&ts->lock); + + return level; +} + +static void max7301_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct max7301 *ts = container_of(chip, struct max7301, chip); + + /* First 4 pins are unused in the controller */ + offset += 4; + + mutex_lock(&ts->lock); + + __max7301_set(ts, offset, value); + + mutex_unlock(&ts->lock); +} + +int __devinit __max730x_probe(struct max7301 *ts) +{ + struct device *dev = ts->dev; + struct max7301_platform_data *pdata; + int i, ret; + + pdata = dev->platform_data; + if (!pdata || !pdata->base) { + dev_err(dev, "incorrect or missing platform data\n"); + return -EINVAL; + } + + mutex_init(&ts->lock); + dev_set_drvdata(dev, ts); + + /* Power up the chip and disable IRQ output */ + ts->write(dev, 0x04, 0x01); + + ts->chip.label = dev->driver->name; + + ts->chip.direction_input = max7301_direction_input; + ts->chip.get = max7301_get; + ts->chip.direction_output = max7301_direction_output; + ts->chip.set = max7301_set; + + ts->chip.base = pdata->base; + ts->chip.ngpio = PIN_NUMBER; + ts->chip.can_sleep = 1; + ts->chip.dev = dev; + ts->chip.owner = THIS_MODULE; + + /* + * tristate all pins in hardware and cache the + * register values for later use. + */ + for (i = 1; i < 8; i++) { + int j; + /* 0xAA means input with internal pullup disabled */ + ts->write(dev, 0x08 + i, 0xAA); + ts->port_config[i] = 0xAA; + for (j = 0; j < 4; j++) { + int offset = (i - 1) * 4 + j; + ret = max7301_direction_input(&ts->chip, offset); + if (ret) + goto exit_destroy; + } + } + + ret = gpiochip_add(&ts->chip); + if (ret) + goto exit_destroy; + + return ret; + +exit_destroy: + dev_set_drvdata(dev, NULL); + mutex_destroy(&ts->lock); + return ret; +} +EXPORT_SYMBOL_GPL(__max730x_probe); + +int __devexit __max730x_remove(struct device *dev) +{ + struct max7301 *ts = dev_get_drvdata(dev); + int ret; + + if (ts == NULL) + return -ENODEV; + + dev_set_drvdata(dev, NULL); + + /* Power down the chip and disable IRQ output */ + ts->write(dev, 0x04, 0x00); + + ret = gpiochip_remove(&ts->chip); + if (!ret) { + mutex_destroy(&ts->lock); + kfree(ts); + } else + dev_err(dev, "Failed to remove GPIO controller: %d\n", ret); + + return ret; +} +EXPORT_SYMBOL_GPL(__max730x_remove); diff --git a/include/linux/spi/max7301.h b/include/linux/spi/max7301.h index 6dfd83f19b4b..34af0a3477bf 100644 --- a/include/linux/spi/max7301.h +++ b/include/linux/spi/max7301.h @@ -1,9 +1,27 @@ #ifndef LINUX_SPI_MAX7301_H #define LINUX_SPI_MAX7301_H +#include + +/* + * Some registers must be read back to modify. + * To save time we cache them here in memory + */ +struct max7301 { + struct mutex lock; + u8 port_config[8]; /* field 0 is unused */ + u32 out_level; /* cached output levels */ + struct gpio_chip chip; + struct device *dev; + int (*write)(struct device *dev, unsigned int reg, unsigned int val); + int (*read)(struct device *dev, unsigned int reg); +}; + struct max7301_platform_data { /* number assigned to the first GPIO */ unsigned base; }; +extern int __max730x_remove(struct device *dev); +extern int __max730x_probe(struct max7301 *ts); #endif -- cgit v1.2.3 From 3e45f1d1155894e6f4291f5536b224874d52d8e2 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Fri, 5 Mar 2010 13:44:35 -0800 Subject: gpio: introduce gpio_request_one() and friends gpio_request() without initial configuration of the GPIO is normally useless, introduce gpio_request_one() together with GPIOF_ flags for input/output direction and initial output level. gpio_{request,free}_array() for multiple GPIOs. Signed-off-by: Eric Miao Cc: David Brownell Cc: Ben Nizette Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/gpio.txt | 64 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/gpio/gpiolib.c | 58 +++++++++++++++++++++++++++++++++++++++++ include/asm-generic/gpio.h | 26 +++++++++++++++++++ 3 files changed, 148 insertions(+) (limited to 'drivers') diff --git a/Documentation/gpio.txt b/Documentation/gpio.txt index 1866c27eec69..c2c6e9b39bbe 100644 --- a/Documentation/gpio.txt +++ b/Documentation/gpio.txt @@ -253,6 +253,70 @@ pin setup (e.g. controlling which pin the GPIO uses, pullup/pulldown). Also note that it's your responsibility to have stopped using a GPIO before you free it. +Considering in most cases GPIOs are actually configured right after they +are claimed, three additional calls are defined: + + /* request a single GPIO, with initial configuration specified by + * 'flags', identical to gpio_request() wrt other arguments and + * return value + */ + int gpio_request_one(unsigned gpio, unsigned long flags, const char *label); + + /* request multiple GPIOs in a single call + */ + int gpio_request_array(struct gpio *array, size_t num); + + /* release multiple GPIOs in a single call + */ + void gpio_free_array(struct gpio *array, size_t num); + +where 'flags' is currently defined to specify the following properties: + + * GPIOF_DIR_IN - to configure direction as input + * GPIOF_DIR_OUT - to configure direction as output + + * GPIOF_INIT_LOW - as output, set initial level to LOW + * GPIOF_INIT_HIGH - as output, set initial level to HIGH + +since GPIOF_INIT_* are only valid when configured as output, so group valid +combinations as: + + * GPIOF_IN - configure as input + * GPIOF_OUT_INIT_LOW - configured as output, initial level LOW + * GPIOF_OUT_INIT_HIGH - configured as output, initial level HIGH + +In the future, these flags can be extended to support more properties such +as open-drain status. + +Further more, to ease the claim/release of multiple GPIOs, 'struct gpio' is +introduced to encapsulate all three fields as: + + struct gpio { + unsigned gpio; + unsigned long flags; + const char *label; + }; + +A typical example of usage: + + static struct gpio leds_gpios[] = { + { 32, GPIOF_OUT_INIT_HIGH, "Power LED" }, /* default to ON */ + { 33, GPIOF_OUT_INIT_LOW, "Green LED" }, /* default to OFF */ + { 34, GPIOF_OUT_INIT_LOW, "Red LED" }, /* default to OFF */ + { 35, GPIOF_OUT_INIT_LOW, "Blue LED" }, /* default to OFF */ + { ... }, + }; + + err = gpio_request_one(31, GPIOF_IN, "Reset Button"); + if (err) + ... + + err = gpio_request_array(leds_gpios, ARRAY_SIZE(leds_gpios)); + if (err) + ... + + gpio_free_array(leds_gpios, ARRAY_SIZE(leds_gpios)); + GPIOs mapped to IRQs -------------------- diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 350842ad3632..9006fdb26fea 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1237,6 +1237,64 @@ void gpio_free(unsigned gpio) } EXPORT_SYMBOL_GPL(gpio_free); +/** + * gpio_request_one - request a single GPIO with initial configuration + * @gpio: the GPIO number + * @flags: GPIO configuration as specified by GPIOF_* + * @label: a literal description string of this GPIO + */ +int gpio_request_one(unsigned gpio, unsigned long flags, const char *label) +{ + int err; + + err = gpio_request(gpio, label); + if (err) + return err; + + if (flags & GPIOF_DIR_IN) + err = gpio_direction_input(gpio); + else + err = gpio_direction_output(gpio, + (flags & GPIOF_INIT_HIGH) ? 1 : 0); + + return err; +} +EXPORT_SYMBOL_GPL(gpio_request_one); + +/** + * gpio_request_array - request multiple GPIOs in a single call + * @array: array of the 'struct gpio' + * @num: how many GPIOs in the array + */ +int gpio_request_array(struct gpio *array, size_t num) +{ + int i, err; + + for (i = 0; i < num; i++, array++) { + err = gpio_request_one(array->gpio, array->flags, array->label); + if (err) + goto err_free; + } + return 0; + +err_free: + while (i--) + gpio_free((--array)->gpio); + return err; +} +EXPORT_SYMBOL_GPL(gpio_request_array); + +/** + * gpio_free_array - release multiple GPIOs in a single call + * @array: array of the 'struct gpio' + * @num: how many GPIOs in the array + */ +void gpio_free_array(struct gpio *array, size_t num) +{ + while (num--) + gpio_free((array++)->gpio); +} +EXPORT_SYMBOL_GPL(gpio_free_array); /** * gpiochip_is_requested - return string iff signal was requested diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 485eeb6c4ef3..979c6a57f2f1 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -136,6 +136,32 @@ extern int __gpio_cansleep(unsigned gpio); extern int __gpio_to_irq(unsigned gpio); +#define GPIOF_DIR_OUT (0 << 0) +#define GPIOF_DIR_IN (1 << 0) + +#define GPIOF_INIT_LOW (0 << 1) +#define GPIOF_INIT_HIGH (1 << 1) + +#define GPIOF_IN (GPIOF_DIR_IN) +#define GPIOF_OUT_INIT_LOW (GPIOF_DIR_OUT | GPIOF_INIT_LOW) +#define GPIOF_OUT_INIT_HIGH (GPIOF_DIR_OUT | GPIOF_INIT_HIGH) + +/** + * struct gpio - a structure describing a GPIO with configuration + * @gpio: the GPIO number + * @flags: GPIO configuration as specified by GPIOF_* + * @label: a literal description string of this GPIO + */ +struct gpio { + unsigned gpio; + unsigned long flags; + const char *label; +}; + +extern int gpio_request_one(unsigned gpio, unsigned long flags, const char *label); +extern int gpio_request_array(struct gpio *array, size_t num); +extern void gpio_free_array(struct gpio *array, size_t num); + #ifdef CONFIG_GPIO_SYSFS /* -- cgit v1.2.3 From 8c35c89aa3d7e0f253c3a10456a8b075288b4565 Mon Sep 17 00:00:00 2001 From: Richard Röjfors Date: Fri, 5 Mar 2010 13:44:35 -0800 Subject: timbgpio: add support for interrupt triggering on both flanks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce support for triggering interrupts on both rising and falling edge. This feature requires version 3 or newer of the IP, a version check is done when triggering on both edges is requested. Signed-off-by: Richard Röjfors Cc: David Brownell Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/gpio/timbgpio.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/timbgpio.c b/drivers/gpio/timbgpio.c index 4ecba6e5a32d..d4295fa5369e 100644 --- a/drivers/gpio/timbgpio.c +++ b/drivers/gpio/timbgpio.c @@ -38,6 +38,8 @@ #define TGPIO_ICR 0x14 #define TGPIO_FLR 0x18 #define TGPIO_LVR 0x1c +#define TGPIO_VER 0x20 +#define TGPIO_BFLR 0x24 struct timbgpio { void __iomem *membase; @@ -126,17 +128,23 @@ static int timbgpio_irq_type(unsigned irq, unsigned trigger) struct timbgpio *tgpio = get_irq_chip_data(irq); int offset = irq - tgpio->irq_base; unsigned long flags; - u32 lvr, flr; + u32 lvr, flr, bflr = 0; + u32 ver; if (offset < 0 || offset > tgpio->gpio.ngpio) return -EINVAL; + ver = ioread32(tgpio->membase + TGPIO_VER); + spin_lock_irqsave(&tgpio->lock, flags); lvr = ioread32(tgpio->membase + TGPIO_LVR); flr = ioread32(tgpio->membase + TGPIO_FLR); + if (ver > 2) + bflr = ioread32(tgpio->membase + TGPIO_BFLR); if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { + bflr &= ~(1 << offset); flr &= ~(1 << offset); if (trigger & IRQ_TYPE_LEVEL_HIGH) lvr |= 1 << offset; @@ -144,21 +152,27 @@ static int timbgpio_irq_type(unsigned irq, unsigned trigger) lvr &= ~(1 << offset); } - if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) - return -EINVAL; - else { + if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { + if (ver < 3) + return -EINVAL; + else { + flr |= 1 << offset; + bflr |= 1 << offset; + } + } else { + bflr &= ~(1 << offset); flr |= 1 << offset; - /* opposite compared to the datasheet, but it mirrors the - * reality - */ if (trigger & IRQ_TYPE_EDGE_FALLING) - lvr |= 1 << offset; - else lvr &= ~(1 << offset); + else + lvr |= 1 << offset; } iowrite32(lvr, tgpio->membase + TGPIO_LVR); iowrite32(flr, tgpio->membase + TGPIO_FLR); + if (ver > 2) + iowrite32(bflr, tgpio->membase + TGPIO_BFLR); + iowrite32(1 << offset, tgpio->membase + TGPIO_ICR); spin_unlock_irqrestore(&tgpio->lock, flags); -- cgit v1.2.3 From 89ea8bbe9c3eb2ea0cb57a4ecf283cab7326f0b0 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Fri, 5 Mar 2010 13:44:36 -0800 Subject: gpio: pca953x.c: add interrupt handling capability Most of the GPIO expanders controlled by the pca953x driver are able to report changes on the input pins through an *INT pin. This patch implements the irq_chip functionality (edge detection only). The driver has been tested on an Arcom Zeus. [akpm@linux-foundation.org: the compiler does inlining for us nowadays] Signed-off-by: Marc Zyngier Cc: Eric Miao Cc: Haojian Zhuang Cc: David Brownell Cc: Nate Case Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/gpio/Kconfig | 7 ++ drivers/gpio/pca953x.c | 249 +++++++++++++++++++++++++++++++++++++++++--- include/linux/i2c/pca953x.h | 3 + 3 files changed, 247 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f3549b8779d8..c5cc7d9d88e3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -134,6 +134,13 @@ config GPIO_PCA953X This driver can also be built as a module. If so, the module will be called pca953x. +config GPIO_PCA953X_IRQ + bool "Interrupt controller support for PCA953x" + depends on GPIO_PCA953X=y + help + Say yes here to enable the pca953x to be used as an interrupt + controller. It requires the driver to be built in the kernel. + config GPIO_PCF857X tristate "PCF857x, PCA{85,96}7x, and MAX732[89] I2C GPIO expanders" depends on I2C diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index 6a2fb3fbb3d9..ab5daab14bc2 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include #ifdef CONFIG_OF_GPIO @@ -26,23 +28,28 @@ #define PCA953X_INVERT 2 #define PCA953X_DIRECTION 3 +#define PCA953X_GPIOS 0x00FF +#define PCA953X_INT 0x0100 + static const struct i2c_device_id pca953x_id[] = { - { "pca9534", 8, }, - { "pca9535", 16, }, + { "pca9534", 8 | PCA953X_INT, }, + { "pca9535", 16 | PCA953X_INT, }, { "pca9536", 4, }, - { "pca9537", 4, }, - { "pca9538", 8, }, - { "pca9539", 16, }, - { "pca9554", 8, }, - { "pca9555", 16, }, + { "pca9537", 4 | PCA953X_INT, }, + { "pca9538", 8 | PCA953X_INT, }, + { "pca9539", 16 | PCA953X_INT, }, + { "pca9554", 8 | PCA953X_INT, }, + { "pca9555", 16 | PCA953X_INT, }, { "pca9556", 8, }, { "pca9557", 8, }, { "max7310", 8, }, - { "max7315", 8, }, - { "pca6107", 8, }, - { "tca6408", 8, }, - { "tca6416", 16, }, + { "max7312", 16 | PCA953X_INT, }, + { "max7313", 16 | PCA953X_INT, }, + { "max7315", 8 | PCA953X_INT, }, + { "pca6107", 8 | PCA953X_INT, }, + { "tca6408", 8 | PCA953X_INT, }, + { "tca6416", 16 | PCA953X_INT, }, /* NYET: { "tca6424", 24, }, */ { } }; @@ -53,6 +60,15 @@ struct pca953x_chip { uint16_t reg_output; uint16_t reg_direction; +#ifdef CONFIG_GPIO_PCA953X_IRQ + struct mutex irq_lock; + uint16_t irq_mask; + uint16_t irq_stat; + uint16_t irq_trig_raise; + uint16_t irq_trig_fall; + int irq_base; +#endif + struct i2c_client *client; struct pca953x_platform_data *dyn_pdata; struct gpio_chip gpio_chip; @@ -202,6 +218,210 @@ static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) gc->names = chip->names; } +#ifdef CONFIG_GPIO_PCA953X_IRQ +static int pca953x_gpio_to_irq(struct gpio_chip *gc, unsigned off) +{ + struct pca953x_chip *chip; + + chip = container_of(gc, struct pca953x_chip, gpio_chip); + return chip->irq_base + off; +} + +static void pca953x_irq_mask(unsigned int irq) +{ + struct pca953x_chip *chip = get_irq_chip_data(irq); + + chip->irq_mask &= ~(1 << (irq - chip->irq_base)); +} + +static void pca953x_irq_unmask(unsigned int irq) +{ + struct pca953x_chip *chip = get_irq_chip_data(irq); + + chip->irq_mask |= 1 << (irq - chip->irq_base); +} + +static void pca953x_irq_bus_lock(unsigned int irq) +{ + struct pca953x_chip *chip = get_irq_chip_data(irq); + + mutex_lock(&chip->irq_lock); +} + +static void pca953x_irq_bus_sync_unlock(unsigned int irq) +{ + struct pca953x_chip *chip = get_irq_chip_data(irq); + + mutex_unlock(&chip->irq_lock); +} + +static int pca953x_irq_set_type(unsigned int irq, unsigned int type) +{ + struct pca953x_chip *chip = get_irq_chip_data(irq); + uint16_t level = irq - chip->irq_base; + uint16_t mask = 1 << level; + + if (!(type & IRQ_TYPE_EDGE_BOTH)) { + dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", + irq, type); + return -EINVAL; + } + + if (type & IRQ_TYPE_EDGE_FALLING) + chip->irq_trig_fall |= mask; + else + chip->irq_trig_fall &= ~mask; + + if (type & IRQ_TYPE_EDGE_RISING) + chip->irq_trig_raise |= mask; + else + chip->irq_trig_raise &= ~mask; + + return pca953x_gpio_direction_input(&chip->gpio_chip, level); +} + +static struct irq_chip pca953x_irq_chip = { + .name = "pca953x", + .mask = pca953x_irq_mask, + .unmask = pca953x_irq_unmask, + .bus_lock = pca953x_irq_bus_lock, + .bus_sync_unlock = pca953x_irq_bus_sync_unlock, + .set_type = pca953x_irq_set_type, +}; + +static uint16_t pca953x_irq_pending(struct pca953x_chip *chip) +{ + uint16_t cur_stat; + uint16_t old_stat; + uint16_t pending; + uint16_t trigger; + int ret; + + ret = pca953x_read_reg(chip, PCA953X_INPUT, &cur_stat); + if (ret) + return 0; + + /* Remove output pins from the equation */ + cur_stat &= chip->reg_direction; + + old_stat = chip->irq_stat; + trigger = (cur_stat ^ old_stat) & chip->irq_mask; + + if (!trigger) + return 0; + + chip->irq_stat = cur_stat; + + pending = (old_stat & chip->irq_trig_fall) | + (cur_stat & chip->irq_trig_raise); + pending &= trigger; + + return pending; +} + +static irqreturn_t pca953x_irq_handler(int irq, void *devid) +{ + struct pca953x_chip *chip = devid; + uint16_t pending; + uint16_t level; + + pending = pca953x_irq_pending(chip); + + if (!pending) + return IRQ_HANDLED; + + do { + level = __ffs(pending); + handle_nested_irq(level + chip->irq_base); + + pending &= ~(1 << level); + } while (pending); + + return IRQ_HANDLED; +} + +static int pca953x_irq_setup(struct pca953x_chip *chip, + const struct i2c_device_id *id) +{ + struct i2c_client *client = chip->client; + struct pca953x_platform_data *pdata = client->dev.platform_data; + int ret; + + if (pdata->irq_base && (id->driver_data & PCA953X_INT)) { + int lvl; + + ret = pca953x_read_reg(chip, PCA953X_INPUT, + &chip->irq_stat); + if (ret) + goto out_failed; + + /* + * There is no way to know which GPIO line generated the + * interrupt. We have to rely on the previous read for + * this purpose. + */ + chip->irq_stat &= chip->reg_direction; + chip->irq_base = pdata->irq_base; + mutex_init(&chip->irq_lock); + + for (lvl = 0; lvl < chip->gpio_chip.ngpio; lvl++) { + int irq = lvl + chip->irq_base; + + set_irq_chip_data(irq, chip); + set_irq_chip_and_handler(irq, &pca953x_irq_chip, + handle_edge_irq); + set_irq_nested_thread(irq, 1); +#ifdef CONFIG_ARM + set_irq_flags(irq, IRQF_VALID); +#else + set_irq_noprobe(irq); +#endif + } + + ret = request_threaded_irq(client->irq, + NULL, + pca953x_irq_handler, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + dev_name(&client->dev), chip); + if (ret) { + dev_err(&client->dev, "failed to request irq %d\n", + client->irq); + goto out_failed; + } + + chip->gpio_chip.to_irq = pca953x_gpio_to_irq; + } + + return 0; + +out_failed: + chip->irq_base = 0; + return ret; +} + +static void pca953x_irq_teardown(struct pca953x_chip *chip) +{ + if (chip->irq_base) + free_irq(chip->client->irq, chip); +} +#else /* CONFIG_GPIO_PCA953X_IRQ */ +static int pca953x_irq_setup(struct pca953x_chip *chip, + const struct i2c_device_id *id) +{ + struct i2c_client *client = chip->client; + struct pca953x_platform_data *pdata = client->dev.platform_data; + + if (pdata->irq_base && (id->driver_data & PCA953X_INT)) + dev_warn(&client->dev, "interrupt support not compiled in\n"); + + return 0; +} + +static void pca953x_irq_teardown(struct pca953x_chip *chip) +{ +} +#endif + /* * Handlers for alternative sources of platform_data */ @@ -286,7 +506,7 @@ static int __devinit pca953x_probe(struct i2c_client *client, /* initialize cached registers from their original values. * we can't share this chip with another i2c master. */ - pca953x_setup_gpio(chip, id->driver_data); + pca953x_setup_gpio(chip, id->driver_data & PCA953X_GPIOS); ret = pca953x_read_reg(chip, PCA953X_OUTPUT, &chip->reg_output); if (ret) @@ -301,6 +521,9 @@ static int __devinit pca953x_probe(struct i2c_client *client, if (ret) goto out_failed; + ret = pca953x_irq_setup(chip, id); + if (ret) + goto out_failed; ret = gpiochip_add(&chip->gpio_chip); if (ret) @@ -317,6 +540,7 @@ static int __devinit pca953x_probe(struct i2c_client *client, return 0; out_failed: + pca953x_irq_teardown(chip); kfree(chip->dyn_pdata); kfree(chip); return ret; @@ -345,6 +569,7 @@ static int pca953x_remove(struct i2c_client *client) return ret; } + pca953x_irq_teardown(chip); kfree(chip->dyn_pdata); kfree(chip); return 0; diff --git a/include/linux/i2c/pca953x.h b/include/linux/i2c/pca953x.h index 29699f8dc5a4..d5c5a60c8a0b 100644 --- a/include/linux/i2c/pca953x.h +++ b/include/linux/i2c/pca953x.h @@ -13,6 +13,9 @@ struct pca953x_platform_data { /* initial polarity inversion setting */ uint16_t invert; + /* interrupt base */ + int irq_base; + void *context; /* param to setup/teardown */ int (*setup)(struct i2c_client *client, -- cgit v1.2.3 From a8a5164c297c16c2f4be776714ca47dba252cc3d Mon Sep 17 00:00:00 2001 From: Ben Gardner Date: Fri, 5 Mar 2010 13:44:38 -0800 Subject: gpio: cs5535-gpio: fix input direction The cs5535-gpio driver's get() function was returning the output value. This means that the GPIO pins would never work as an input, even if configured as an input. The driver should return the READ_BACK value, which is the sensed line value. To make that work when the direction is 'output', INPUT_ENABLE needs to be set. In addition, the driver was not disabling OUTPUT_ENABLE when the direction is set to 'input'. That would cause the GPIO to continue to drive the pin if the direction was ever set to output. This issue was noticed when attempting to use the gpiolib driver to read an external input. I had previously been using the char/cs5535-gpio driver. Signed-off-by: Ben Gardner Acked-by: Andres Salomon Cc: Andrew Morton Cc: David Brownell Cc: Mark Brown Cc: [2.6.33.x] Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/gpio/cs5535-gpio.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/cs5535-gpio.c b/drivers/gpio/cs5535-gpio.c index 0fdbe94f24a3..0c3c498f2260 100644 --- a/drivers/gpio/cs5535-gpio.c +++ b/drivers/gpio/cs5535-gpio.c @@ -154,7 +154,7 @@ static int chip_gpio_request(struct gpio_chip *c, unsigned offset) static int chip_gpio_get(struct gpio_chip *chip, unsigned offset) { - return cs5535_gpio_isset(offset, GPIO_OUTPUT_VAL); + return cs5535_gpio_isset(offset, GPIO_READ_BACK); } static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val) @@ -172,6 +172,7 @@ static int chip_direction_input(struct gpio_chip *c, unsigned offset) spin_lock_irqsave(&chip->lock, flags); __cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE); + __cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_ENABLE); spin_unlock_irqrestore(&chip->lock, flags); return 0; @@ -184,6 +185,7 @@ static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val) spin_lock_irqsave(&chip->lock, flags); + __cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE); __cs5535_gpio_set(chip, offset, GPIO_OUTPUT_ENABLE); if (val) __cs5535_gpio_set(chip, offset, GPIO_OUTPUT_VAL); -- cgit v1.2.3 From 9cc0cb3c7d54f320b9eede6f4a49072ecadd864d Mon Sep 17 00:00:00 2001 From: Denis Turischev Date: Fri, 5 Mar 2010 13:44:39 -0800 Subject: gpio: introduce it8761e_gpio driver for IT8761E Super I/O chip Signed-off-by: Denis Turischev Cc: David Brownell Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/gpio/Kconfig | 6 ++ drivers/gpio/Makefile | 1 + drivers/gpio/it8761e_gpio.c | 231 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 238 insertions(+) create mode 100644 drivers/gpio/it8761e_gpio.c (limited to 'drivers') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index c5cc7d9d88e3..a4cdbd51b1c6 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -70,6 +70,12 @@ config GPIO_MAX730X comment "Memory mapped GPIO expanders:" +config GPIO_IT8761E + tristate "IT8761E GPIO support" + depends on GPIOLIB + help + Say yes here to support GPIO functionality of IT8761E super I/O chip. + config GPIO_PL061 bool "PrimeCell PL061 GPIO support" depends on ARM_AMBA diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 508a1b202cdb..128abf8a98da 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -22,5 +22,6 @@ obj-$(CONFIG_GPIO_UCB1400) += ucb1400_gpio.o obj-$(CONFIG_GPIO_XILINX) += xilinx_gpio.o obj-$(CONFIG_GPIO_CS5535) += cs5535-gpio.o obj-$(CONFIG_GPIO_BT8XX) += bt8xxgpio.o +obj-$(CONFIG_GPIO_IT8761E) += it8761e_gpio.o obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o obj-$(CONFIG_GPIO_WM831X) += wm831x-gpio.o diff --git a/drivers/gpio/it8761e_gpio.c b/drivers/gpio/it8761e_gpio.c new file mode 100644 index 000000000000..753219cf993a --- /dev/null +++ b/drivers/gpio/it8761e_gpio.c @@ -0,0 +1,231 @@ +/* + * it8761_gpio.c - GPIO interface for IT8761E Super I/O chip + * + * Author: Denis Turischev + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define SIO_CHIP_ID 0x8761 +#define CHIP_ID_HIGH_BYTE 0x20 +#define CHIP_ID_LOW_BYTE 0x21 + +static u8 ports[2] = { 0x2e, 0x4e }; +static u8 port; + +static DEFINE_SPINLOCK(sio_lock); + +#define GPIO_NAME "it8761-gpio" +#define GPIO_BA_HIGH_BYTE 0x60 +#define GPIO_BA_LOW_BYTE 0x61 +#define GPIO_IOSIZE 4 +#define GPIO1X_IO 0xf0 +#define GPIO2X_IO 0xf1 + +static u16 gpio_ba; + +static u8 read_reg(u8 addr, u8 port) +{ + outb(addr, port); + return inb(port + 1); +} + +static void write_reg(u8 data, u8 addr, u8 port) +{ + outb(addr, port); + outb(data, port + 1); +} + +static void enter_conf_mode(u8 port) +{ + outb(0x87, port); + outb(0x61, port); + outb(0x55, port); + outb((port == 0x2e) ? 0x55 : 0xaa, port); +} + +static void exit_conf_mode(u8 port) +{ + outb(0x2, port); + outb(0x2, port + 1); +} + +static void enter_gpio_mode(u8 port) +{ + write_reg(0x2, 0x7, port); +} + +static int it8761e_gpio_get(struct gpio_chip *gc, unsigned gpio_num) +{ + u16 reg; + u8 bit; + + bit = gpio_num % 7; + reg = (gpio_num >= 7) ? gpio_ba + 1 : gpio_ba; + + return !!(inb(reg) & (1 << bit)); +} + +static int it8761e_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num) +{ + u8 curr_dirs; + u8 io_reg, bit; + + bit = gpio_num % 7; + io_reg = (gpio_num >= 7) ? GPIO2X_IO : GPIO1X_IO; + + spin_lock(&sio_lock); + + enter_conf_mode(port); + enter_gpio_mode(port); + + curr_dirs = read_reg(io_reg, port); + + if (curr_dirs & (1 << bit)) + write_reg(curr_dirs & ~(1 << bit), io_reg, port); + + exit_conf_mode(port); + + spin_unlock(&sio_lock); + return 0; +} + +static void it8761e_gpio_set(struct gpio_chip *gc, + unsigned gpio_num, int val) +{ + u8 curr_vals, bit; + u16 reg; + + bit = gpio_num % 7; + reg = (gpio_num >= 7) ? gpio_ba + 1 : gpio_ba; + + spin_lock(&sio_lock); + + curr_vals = inb(reg); + if (val) + outb(curr_vals | (1 << bit) , reg); + else + outb(curr_vals & ~(1 << bit), reg); + + spin_unlock(&sio_lock); +} + +static int it8761e_gpio_direction_out(struct gpio_chip *gc, + unsigned gpio_num, int val) +{ + u8 curr_dirs, io_reg, bit; + + bit = gpio_num % 7; + io_reg = (gpio_num >= 7) ? GPIO2X_IO : GPIO1X_IO; + + it8761e_gpio_set(gc, gpio_num, val); + + spin_lock(&sio_lock); + + enter_conf_mode(port); + enter_gpio_mode(port); + + curr_dirs = read_reg(io_reg, port); + + if (!(curr_dirs & (1 << bit))) + write_reg(curr_dirs | (1 << bit), io_reg, port); + + exit_conf_mode(port); + + spin_unlock(&sio_lock); + return 0; +} + +static struct gpio_chip it8761e_gpio_chip = { + .label = GPIO_NAME, + .owner = THIS_MODULE, + .get = it8761e_gpio_get, + .direction_input = it8761e_gpio_direction_in, + .set = it8761e_gpio_set, + .direction_output = it8761e_gpio_direction_out, +}; + +static int __init it8761e_gpio_init(void) +{ + int i, id, err; + + /* chip and port detection */ + for (i = 0; i < ARRAY_SIZE(ports); i++) { + spin_lock(&sio_lock); + enter_conf_mode(ports[i]); + + id = (read_reg(CHIP_ID_HIGH_BYTE, ports[i]) << 8) + + read_reg(CHIP_ID_LOW_BYTE, ports[i]); + + exit_conf_mode(ports[i]); + spin_unlock(&sio_lock); + + if (id == SIO_CHIP_ID) { + port = ports[i]; + break; + } + } + + if (!port) + return -ENODEV; + + /* fetch GPIO base address */ + enter_conf_mode(port); + enter_gpio_mode(port); + gpio_ba = (read_reg(GPIO_BA_HIGH_BYTE, port) << 8) + + read_reg(GPIO_BA_LOW_BYTE, port); + exit_conf_mode(port); + + if (!request_region(gpio_ba, GPIO_IOSIZE, GPIO_NAME)) + return -EBUSY; + + it8761e_gpio_chip.base = -1; + it8761e_gpio_chip.ngpio = 14; + + err = gpiochip_add(&it8761e_gpio_chip); + if (err < 0) + goto gpiochip_add_err; + + return 0; + +gpiochip_add_err: + release_region(gpio_ba, GPIO_IOSIZE); + gpio_ba = 0; + return err; +} + +static void __exit it8761e_gpio_exit(void) +{ + if (gpio_ba) { + gpiochip_remove(&it8761e_gpio_chip); + + release_region(gpio_ba, GPIO_IOSIZE); + gpio_ba = 0; + } +} +module_init(it8761e_gpio_init); +module_exit(it8761e_gpio_exit); + +MODULE_AUTHOR("Denis Turischev "); +MODULE_DESCRIPTION("GPIO interface for IT8761E Super I/O chip"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From d690b2cd222afc75320b9b8e9da7df02e9e630ca Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Sat, 6 Mar 2010 21:28:37 +0100 Subject: PM: Provide generic subsystem-level callbacks There are subsystems whose power management callbacks only need to invoke the callbacks provided by device drivers. Still, their system sleep PM callbacks should play well with the runtime PM callbacks, so that devices suspended at run time can be left in that state for a system sleep transition. Provide a set of generic PM callbacks for such subsystems and define convenience macros for populating dev_pm_ops structures. Signed-off-by: Rafael J. Wysocki --- Documentation/power/runtime_pm.txt | 65 +++++++++++ drivers/base/power/Makefile | 1 + drivers/base/power/generic_ops.c | 233 +++++++++++++++++++++++++++++++++++++ include/linux/pm.h | 51 +++++++- include/linux/pm_runtime.h | 6 + 5 files changed, 350 insertions(+), 6 deletions(-) create mode 100644 drivers/base/power/generic_ops.c (limited to 'drivers') diff --git a/Documentation/power/runtime_pm.txt b/Documentation/power/runtime_pm.txt index f19370641684..ab00eeddecaf 100644 --- a/Documentation/power/runtime_pm.txt +++ b/Documentation/power/runtime_pm.txt @@ -335,6 +335,10 @@ drivers/base/power/runtime.c and include/linux/pm_runtime.h: 'power.runtime_error' is set or 'power.disable_depth' is greater than zero) + bool pm_runtime_suspended(struct device *dev); + - return true if the device's runtime PM status is 'suspended', or false + otherwise + void pm_runtime_allow(struct device *dev); - set the power.runtime_auto flag for the device and decrease its usage counter (used by the /sys/devices/.../power/control interface to @@ -459,3 +463,64 @@ The PM core always increments the run-time usage counter before calling the ->prepare() callback and decrements it after calling the ->complete() callback. Hence disabling run-time PM temporarily like this will not cause any run-time suspend callbacks to be lost. + +7. Generic subsystem callbacks + +Subsystems may wish to conserve code space by using the set of generic power +management callbacks provided by the PM core, defined in +driver/base/power/generic_ops.c: + + int pm_generic_runtime_idle(struct device *dev); + - invoke the ->runtime_idle() callback provided by the driver of this + device, if defined, and call pm_runtime_suspend() for this device if the + return value is 0 or the callback is not defined + + int pm_generic_runtime_suspend(struct device *dev); + - invoke the ->runtime_suspend() callback provided by the driver of this + device and return its result, or return -EINVAL if not defined + + int pm_generic_runtime_resume(struct device *dev); + - invoke the ->runtime_resume() callback provided by the driver of this + device and return its result, or return -EINVAL if not defined + + int pm_generic_suspend(struct device *dev); + - if the device has not been suspended at run time, invoke the ->suspend() + callback provided by its driver and return its result, or return 0 if not + defined + + int pm_generic_resume(struct device *dev); + - invoke the ->resume() callback provided by the driver of this device and, + if successful, change the device's runtime PM status to 'active' + + int pm_generic_freeze(struct device *dev); + - if the device has not been suspended at run time, invoke the ->freeze() + callback provided by its driver and return its result, or return 0 if not + defined + + int pm_generic_thaw(struct device *dev); + - if the device has not been suspended at run time, invoke the ->thaw() + callback provided by its driver and return its result, or return 0 if not + defined + + int pm_generic_poweroff(struct device *dev); + - if the device has not been suspended at run time, invoke the ->poweroff() + callback provided by its driver and return its result, or return 0 if not + defined + + int pm_generic_restore(struct device *dev); + - invoke the ->restore() callback provided by the driver of this device and, + if successful, change the device's runtime PM status to 'active' + +These functions can be assigned to the ->runtime_idle(), ->runtime_suspend(), +->runtime_resume(), ->suspend(), ->resume(), ->freeze(), ->thaw(), ->poweroff(), +or ->restore() callback pointers in the subsystem-level dev_pm_ops structures. + +If a subsystem wishes to use all of them at the same time, it can simply assign +the GENERIC_SUBSYS_PM_OPS macro, defined in include/linux/pm.h, to its +dev_pm_ops structure pointer. + +Device drivers that wish to use the same function as a system suspend, freeze, +poweroff and run-time suspend callback, and similarly for system resume, thaw, +restore, and run-time resume, can achieve this with the help of the +UNIVERSAL_DEV_PM_OPS macro defined in include/linux/pm.h (possibly setting its +last argument to NULL). diff --git a/drivers/base/power/Makefile b/drivers/base/power/Makefile index 3ce3519e8f30..89de75325cea 100644 --- a/drivers/base/power/Makefile +++ b/drivers/base/power/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_PM) += sysfs.o obj-$(CONFIG_PM_SLEEP) += main.o obj-$(CONFIG_PM_RUNTIME) += runtime.o +obj-$(CONFIG_PM_OPS) += generic_ops.o obj-$(CONFIG_PM_TRACE_RTC) += trace.o ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG diff --git a/drivers/base/power/generic_ops.c b/drivers/base/power/generic_ops.c new file mode 100644 index 000000000000..4b29d4981253 --- /dev/null +++ b/drivers/base/power/generic_ops.c @@ -0,0 +1,233 @@ +/* + * drivers/base/power/generic_ops.c - Generic PM callbacks for subsystems + * + * Copyright (c) 2010 Rafael J. Wysocki , Novell Inc. + * + * This file is released under the GPLv2. + */ + +#include +#include + +#ifdef CONFIG_PM_RUNTIME +/** + * pm_generic_runtime_idle - Generic runtime idle callback for subsystems. + * @dev: Device to handle. + * + * If PM operations are defined for the @dev's driver and they include + * ->runtime_idle(), execute it and return its error code, if nonzero. + * Otherwise, execute pm_runtime_suspend() for the device and return 0. + */ +int pm_generic_runtime_idle(struct device *dev) +{ + const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; + + if (pm && pm->runtime_idle) { + int ret = pm->runtime_idle(dev); + if (ret) + return ret; + } + + pm_runtime_suspend(dev); + return 0; +} +EXPORT_SYMBOL_GPL(pm_generic_runtime_idle); + +/** + * pm_generic_runtime_suspend - Generic runtime suspend callback for subsystems. + * @dev: Device to suspend. + * + * If PM operations are defined for the @dev's driver and they include + * ->runtime_suspend(), execute it and return its error code. Otherwise, + * return -EINVAL. + */ +int pm_generic_runtime_suspend(struct device *dev) +{ + const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; + int ret; + + ret = pm && pm->runtime_suspend ? pm->runtime_suspend(dev) : -EINVAL; + + return ret; +} +EXPORT_SYMBOL_GPL(pm_generic_runtime_suspend); + +/** + * pm_generic_runtime_resume - Generic runtime resume callback for subsystems. + * @dev: Device to resume. + * + * If PM operations are defined for the @dev's driver and they include + * ->runtime_resume(), execute it and return its error code. Otherwise, + * return -EINVAL. + */ +int pm_generic_runtime_resume(struct device *dev) +{ + const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; + int ret; + + ret = pm && pm->runtime_resume ? pm->runtime_resume(dev) : -EINVAL; + + return ret; +} +EXPORT_SYMBOL_GPL(pm_generic_runtime_resume); +#endif /* CONFIG_PM_RUNTIME */ + +#ifdef CONFIG_PM_SLEEP +/** + * __pm_generic_call - Generic suspend/freeze/poweroff/thaw subsystem callback. + * @dev: Device to handle. + * @event: PM transition of the system under way. + * + * If the device has not been suspended at run time, execute the + * suspend/freeze/poweroff/thaw callback provided by its driver, if defined, and + * return its error code. Otherwise, return zero. + */ +static int __pm_generic_call(struct device *dev, int event) +{ + const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; + int (*callback)(struct device *); + + if (!pm || pm_runtime_suspended(dev)) + return 0; + + switch (event) { + case PM_EVENT_SUSPEND: + callback = pm->suspend; + break; + case PM_EVENT_FREEZE: + callback = pm->freeze; + break; + case PM_EVENT_HIBERNATE: + callback = pm->poweroff; + break; + case PM_EVENT_THAW: + callback = pm->thaw; + break; + default: + callback = NULL; + break; + } + + return callback ? callback(dev) : 0; +} + +/** + * pm_generic_suspend - Generic suspend callback for subsystems. + * @dev: Device to suspend. + */ +int pm_generic_suspend(struct device *dev) +{ + return __pm_generic_call(dev, PM_EVENT_SUSPEND); +} +EXPORT_SYMBOL_GPL(pm_generic_suspend); + +/** + * pm_generic_freeze - Generic freeze callback for subsystems. + * @dev: Device to freeze. + */ +int pm_generic_freeze(struct device *dev) +{ + return __pm_generic_call(dev, PM_EVENT_FREEZE); +} +EXPORT_SYMBOL_GPL(pm_generic_freeze); + +/** + * pm_generic_poweroff - Generic poweroff callback for subsystems. + * @dev: Device to handle. + */ +int pm_generic_poweroff(struct device *dev) +{ + return __pm_generic_call(dev, PM_EVENT_HIBERNATE); +} +EXPORT_SYMBOL_GPL(pm_generic_poweroff); + +/** + * pm_generic_thaw - Generic thaw callback for subsystems. + * @dev: Device to thaw. + */ +int pm_generic_thaw(struct device *dev) +{ + return __pm_generic_call(dev, PM_EVENT_THAW); +} +EXPORT_SYMBOL_GPL(pm_generic_thaw); + +/** + * __pm_generic_resume - Generic resume/restore callback for subsystems. + * @dev: Device to handle. + * @event: PM transition of the system under way. + * + * Execute the resume/resotre callback provided by the @dev's driver, if + * defined. If it returns 0, change the device's runtime PM status to 'active'. + * Return the callback's error code. + */ +static int __pm_generic_resume(struct device *dev, int event) +{ + const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; + int (*callback)(struct device *); + int ret; + + if (!pm) + return 0; + + switch (event) { + case PM_EVENT_RESUME: + callback = pm->resume; + break; + case PM_EVENT_RESTORE: + callback = pm->restore; + break; + default: + callback = NULL; + break; + } + + if (!callback) + return 0; + + ret = callback(dev); + if (!ret) { + pm_runtime_disable(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + } + + return ret; +} + +/** + * pm_generic_resume - Generic resume callback for subsystems. + * @dev: Device to resume. + */ +int pm_generic_resume(struct device *dev) +{ + return __pm_generic_resume(dev, PM_EVENT_RESUME); +} +EXPORT_SYMBOL_GPL(pm_generic_resume); + +/** + * pm_generic_restore - Generic restore callback for subsystems. + * @dev: Device to restore. + */ +int pm_generic_restore(struct device *dev) +{ + return __pm_generic_resume(dev, PM_EVENT_RESTORE); +} +EXPORT_SYMBOL_GPL(pm_generic_restore); +#endif /* CONFIG_PM_SLEEP */ + +struct dev_pm_ops generic_subsys_pm_ops = { +#ifdef CONFIG_PM_SLEEP + .suspend = pm_generic_suspend, + .resume = pm_generic_resume, + .freeze = pm_generic_freeze, + .thaw = pm_generic_thaw, + .poweroff = pm_generic_poweroff, + .restore = pm_generic_restore, +#endif +#ifdef CONFIG_PM_RUNTIME + .runtime_suspend = pm_generic_runtime_suspend, + .runtime_resume = pm_generic_runtime_resume, + .runtime_idle = pm_generic_runtime_idle, +#endif +}; +EXPORT_SYMBOL_GPL(generic_subsys_pm_ops); diff --git a/include/linux/pm.h b/include/linux/pm.h index e80df06ad22a..8e258c727971 100644 --- a/include/linux/pm.h +++ b/include/linux/pm.h @@ -215,20 +215,59 @@ struct dev_pm_ops { int (*runtime_idle)(struct device *dev); }; +#ifdef CONFIG_PM_SLEEP +#define SET_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) \ + .suspend = suspend_fn, \ + .resume = resume_fn, \ + .freeze = suspend_fn, \ + .thaw = resume_fn, \ + .poweroff = suspend_fn, \ + .restore = resume_fn, +#else +#define SET_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) +#endif + +#ifdef CONFIG_PM_RUNTIME +#define SET_RUNTIME_PM_OPS(suspend_fn, resume_fn, idle_fn) \ + .runtime_suspend = suspend_fn, \ + .runtime_resume = resume_fn, \ + .runtime_idle = idle_fn, +#else +#define SET_RUNTIME_PM_OPS(suspend_fn, resume_fn, idle_fn) +#endif + /* * Use this if you want to use the same suspend and resume callbacks for suspend * to RAM and hibernation. */ #define SIMPLE_DEV_PM_OPS(name, suspend_fn, resume_fn) \ const struct dev_pm_ops name = { \ - .suspend = suspend_fn, \ - .resume = resume_fn, \ - .freeze = suspend_fn, \ - .thaw = resume_fn, \ - .poweroff = suspend_fn, \ - .restore = resume_fn, \ + SET_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) \ +} + +/* + * Use this for defining a set of PM operations to be used in all situations + * (sustem suspend, hibernation or runtime PM). + */ +#define UNIVERSAL_DEV_PM_OPS(name, suspend_fn, resume_fn, idle_fn) \ +const struct dev_pm_ops name = { \ + SET_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) \ + SET_RUNTIME_PM_OPS(suspend_fn, resume_fn, idle_fn) \ } +/* + * Use this for subsystems (bus types, device types, device classes) that don't + * need any special suspend/resume handling in addition to invoking the PM + * callbacks provided by device drivers supporting both the system sleep PM and + * runtime PM, make the pm member point to generic_subsys_pm_ops. + */ +#ifdef CONFIG_PM_OPS +extern struct dev_pm_ops generic_subsys_pm_ops; +#define GENERIC_SUBSYS_PM_OPS (&generic_subsys_pm_ops) +#else +#define GENERIC_SUBSYS_PM_OPS NULL +#endif + /** * PM_EVENT_ messages * diff --git a/include/linux/pm_runtime.h b/include/linux/pm_runtime.h index 7d773aac5314..b776db737244 100644 --- a/include/linux/pm_runtime.h +++ b/include/linux/pm_runtime.h @@ -62,6 +62,11 @@ static inline void device_set_run_wake(struct device *dev, bool enable) dev->power.run_wake = enable; } +static inline bool pm_runtime_suspended(struct device *dev) +{ + return dev->power.runtime_status == RPM_SUSPENDED; +} + #else /* !CONFIG_PM_RUNTIME */ static inline int pm_runtime_idle(struct device *dev) { return -ENOSYS; } @@ -89,6 +94,7 @@ static inline void pm_runtime_get_noresume(struct device *dev) {} static inline void pm_runtime_put_noidle(struct device *dev) {} static inline bool device_run_wake(struct device *dev) { return false; } static inline void device_set_run_wake(struct device *dev, bool enable) {} +static inline bool pm_runtime_suspended(struct device *dev) { return false; } #endif /* !CONFIG_PM_RUNTIME */ -- cgit v1.2.3 From a3bee03e718c9251456676b71a723a34c999e891 Mon Sep 17 00:00:00 2001 From: Frans Pop Date: Sat, 6 Feb 2010 17:47:14 +0000 Subject: parisc: remove trailing space in messages Signed-off-by: Frans Pop Cc: linux-parisc@vger.kernel.org Cc: Kyle McMartin Cc: Helge Deller Signed-off-by: Kyle McMartin --- arch/parisc/kernel/cache.c | 4 ++-- drivers/parisc/eisa_enumerator.c | 2 +- drivers/parisc/superio.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c index 1054baa2fc69..d054f3da3ff5 100644 --- a/arch/parisc/kernel/cache.c +++ b/arch/parisc/kernel/cache.c @@ -171,14 +171,14 @@ parisc_cache_init(void) cache_info.ic_conf.cc_cst, cache_info.ic_conf.cc_hv); - printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n", + printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n", cache_info.dt_conf.tc_sh, cache_info.dt_conf.tc_page, cache_info.dt_conf.tc_cst, cache_info.dt_conf.tc_aid, cache_info.dt_conf.tc_pad1); - printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n", + printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n", cache_info.it_conf.tc_sh, cache_info.it_conf.tc_page, cache_info.it_conf.tc_cst, diff --git a/drivers/parisc/eisa_enumerator.c b/drivers/parisc/eisa_enumerator.c index 0be1d50645ab..caa153133754 100644 --- a/drivers/parisc/eisa_enumerator.c +++ b/drivers/parisc/eisa_enumerator.c @@ -460,7 +460,7 @@ static int init_slot(int slot, struct eeprom_eisa_slot_info *es) slot, id_string); print_eisa_id(id_string, es->eisa_slot_id); - printk(" expected %s \n", id_string); + printk(" expected %s\n", id_string); return -1; diff --git a/drivers/parisc/superio.c b/drivers/parisc/superio.c index a35c9c5b89e8..f7806d81f1e0 100644 --- a/drivers/parisc/superio.c +++ b/drivers/parisc/superio.c @@ -169,7 +169,7 @@ superio_init(struct pci_dev *pcidev) /* ...then properly fixup the USB to point at suckyio PIC */ sio->usb_pdev->irq = superio_fixup_irq(sio->usb_pdev); - printk(KERN_INFO PFX "Found NS87560 Legacy I/O device at %s (IRQ %i) \n", + printk(KERN_INFO PFX "Found NS87560 Legacy I/O device at %s (IRQ %i)\n", pci_name(pdev), pdev->irq); pci_read_config_dword (pdev, SIO_SP1BAR, &sio->sp1_base); -- cgit v1.2.3 From 7bc80cd935a4d5fd8574f6994bd95d0aad273d56 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sat, 6 Mar 2010 16:34:34 -0800 Subject: usbfs: fix deadlock on 'usbfs_mutex', clean up poll The caller of usbfs_conn_disc_event() in some cases (but not always) already holds usbfs_mutex, so trying to protect the event counter with that lock causes nasty deadlocks. The problem was introduced by commit 554f76962d ("USB: Remove BKL from poll()") when the BLK protection was turned into using the mutex instead. So fix this by using an atomic variable instead. And while we're at it, get rid of the atrocious naming of said variable and the waitqueue it is associated with. This also cleans up the unnecessary locking in the poll routine, since the whole point of how the pollwait table works is that you can just add yourself to the waiting list, and then check the condition you're waiting for afterwards - avoiding all races. It also gets rid of the unnecessary dynamic allocation of the device status that just contained a single word. We should use f_version for this, as Dmitry Torokhov points out. That simplifies everything further. Reported-and-tested-by: Jeff Chua Acked-by: Greg Kroah-Hartman Acked-by: Alan Stern Cc: Oliver Neukum Cc: Dmitry Torokhov Signed-off-by: Linus Torvalds --- drivers/usb/core/devices.c | 66 +++++++++++++++++----------------------------- 1 file changed, 24 insertions(+), 42 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/core/devices.c b/drivers/usb/core/devices.c index c83c975152a6..6053a8b730cd 100644 --- a/drivers/usb/core/devices.c +++ b/drivers/usb/core/devices.c @@ -117,9 +117,21 @@ static const char *format_endpt = * However, these will come from functions that return ptrs to each of them. */ -static DECLARE_WAIT_QUEUE_HEAD(deviceconndiscwq); -/* guarded by usbfs_mutex */ -static unsigned int conndiscevcnt; +/* + * Wait for an connect/disconnect event to happen. We initialize + * the event counter with an odd number, and each event will increment + * the event counter by two, so it will always _stay_ odd. That means + * that it will never be zero, so "event 0" will never match a current + * event, and thus 'poll' will always trigger as readable for the first + * time it gets called. + */ +static struct device_connect_event { + atomic_t count; + wait_queue_head_t wait; +} device_event = { + .count = ATOMIC_INIT(1), + .wait = __WAIT_QUEUE_HEAD_INITIALIZER(device_event.wait) +}; /* this struct stores the poll state for /devices pollers */ struct usb_device_status { @@ -157,10 +169,8 @@ static const struct class_info clas_info[] = void usbfs_conn_disc_event(void) { - mutex_lock(&usbfs_mutex); - conndiscevcnt++; - mutex_unlock(&usbfs_mutex); - wake_up(&deviceconndiscwq); + atomic_add(2, &device_event.count); + wake_up(&device_event.wait); } static const char *class_decode(const int class) @@ -632,42 +642,16 @@ static ssize_t usb_device_read(struct file *file, char __user *buf, static unsigned int usb_device_poll(struct file *file, struct poll_table_struct *wait) { - struct usb_device_status *st; - unsigned int mask = 0; - - mutex_lock(&usbfs_mutex); - st = file->private_data; - if (!st) { - st = kmalloc(sizeof(struct usb_device_status), GFP_KERNEL); - if (!st) { - mutex_unlock(&usbfs_mutex); - return POLLIN; - } - - st->lastev = conndiscevcnt; - file->private_data = st; - mask = POLLIN; - } + unsigned int event_count; - if (file->f_mode & FMODE_READ) - poll_wait(file, &deviceconndiscwq, wait); - if (st->lastev != conndiscevcnt) - mask |= POLLIN; - st->lastev = conndiscevcnt; - mutex_unlock(&usbfs_mutex); - return mask; -} + poll_wait(file, &device_event.wait, wait); -static int usb_device_open(struct inode *inode, struct file *file) -{ - file->private_data = NULL; - return 0; -} + event_count = atomic_read(&device_event.count); + if (file->f_version != event_count) { + file->f_version = event_count; + return POLLIN | POLLRDNORM; + } -static int usb_device_release(struct inode *inode, struct file *file) -{ - kfree(file->private_data); - file->private_data = NULL; return 0; } @@ -699,6 +683,4 @@ const struct file_operations usbfs_devices_fops = { .llseek = usb_device_lseek, .read = usb_device_read, .poll = usb_device_poll, - .open = usb_device_open, - .release = usb_device_release, }; -- cgit v1.2.3 From 0a20de446c76529028cb239bf2a13cb0f05b263a Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:34:20 -0800 Subject: [SCSI] bfa: IOC changes: Support faster recovery and split bfa_ioc.c into ASIC specific code. Add support for faster IOC recovery after failure. Split bfa_ioc.c into three files: bfa_ioc.c: Common code shared between crossbow and catapult ASIC's. bfa_ioc_cb.c: Code specific to the crossbow, reg mapping and interrupt related routines. bfa_ioc_ct.c: Code specific to the catapult, reg mapping and interrupt related routines. Fix to make sure IOC reinitialize's properly on enable request - update the ioc_fwstate reg with BFI_IOC_FAIL on ioc disable mbox cmd timeout. Makefile changes to support the 2 newly added files bfa_ioc_cb.c and bfa_ioc_ct.c. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/Makefile | 8 +- drivers/scsi/bfa/bfa_core.c | 10 + drivers/scsi/bfa/bfa_ioc.c | 546 +++++--------------------- drivers/scsi/bfa/bfa_ioc.h | 45 ++- drivers/scsi/bfa/bfa_ioc_cb.c | 273 +++++++++++++ drivers/scsi/bfa/bfa_ioc_ct.c | 422 ++++++++++++++++++++ drivers/scsi/bfa/include/bfa.h | 1 + drivers/scsi/bfa/include/bfa_timer.h | 2 +- drivers/scsi/bfa/include/bfi/bfi_cbreg.h | 3 +- drivers/scsi/bfa/include/bfi/bfi_ctreg.h | 2 + drivers/scsi/bfa/include/bfi/bfi_ioc.h | 2 +- drivers/scsi/bfa/include/cna/bfa_cna_trcmod.h | 4 + 12 files changed, 859 insertions(+), 459 deletions(-) create mode 100644 drivers/scsi/bfa/bfa_ioc_cb.c create mode 100644 drivers/scsi/bfa/bfa_ioc_ct.c (limited to 'drivers') diff --git a/drivers/scsi/bfa/Makefile b/drivers/scsi/bfa/Makefile index 1d6009490d1c..17e06cae71b2 100644 --- a/drivers/scsi/bfa/Makefile +++ b/drivers/scsi/bfa/Makefile @@ -2,14 +2,14 @@ obj-$(CONFIG_SCSI_BFA_FC) := bfa.o bfa-y := bfad.o bfad_intr.o bfad_os.o bfad_im.o bfad_attr.o bfad_fwimg.o -bfa-y += bfa_core.o bfa_ioc.o bfa_iocfc.o bfa_fcxp.o bfa_lps.o -bfa-y += bfa_hw_cb.o bfa_hw_ct.o bfa_intr.o bfa_timer.o bfa_rport.o +bfa-y += bfa_core.o bfa_ioc.o bfa_ioc_ct.o bfa_ioc_cb.o bfa_iocfc.o bfa_fcxp.o +bfa-y += bfa_lps.o bfa_hw_cb.o bfa_hw_ct.o bfa_intr.o bfa_timer.o bfa_rport.o bfa-y += bfa_fcport.o bfa_port.o bfa_uf.o bfa_sgpg.o bfa_module.o bfa_ioim.o bfa-y += bfa_itnim.o bfa_fcpim.o bfa_tskim.o bfa_log.o bfa_log_module.o bfa-y += bfa_csdebug.o bfa_sm.o plog.o -bfa-y += fcbuild.o fabric.o fcpim.o vfapi.o fcptm.o bfa_fcs.o bfa_fcs_port.o +bfa-y += fcbuild.o fabric.o fcpim.o vfapi.o fcptm.o bfa_fcs.o bfa_fcs_port.o bfa-y += bfa_fcs_uf.o bfa_fcs_lport.o fab.o fdmi.o ms.o ns.o scn.o loop.o bfa-y += lport_api.o n2n.o rport.o rport_api.o rport_ftrs.o vport.o -ccflags-y := -I$(obj) -I$(obj)/include -I$(obj)/include/cna +ccflags-y := -I$(obj) -I$(obj)/include -I$(obj)/include/cna -DBFA_PERF_BUILD diff --git a/drivers/scsi/bfa/bfa_core.c b/drivers/scsi/bfa/bfa_core.c index 44e2d1155c51..72e3f2f63b2e 100644 --- a/drivers/scsi/bfa/bfa_core.c +++ b/drivers/scsi/bfa/bfa_core.c @@ -399,4 +399,14 @@ bfa_debug_fwtrc(struct bfa_s *bfa, void *trcdata, int *trclen) { return bfa_ioc_debug_fwtrc(&bfa->ioc, trcdata, trclen); } + +/** + * Reset hw semaphore & usage cnt regs and initialize. + */ +void +bfa_chip_reset(struct bfa_s *bfa) +{ + bfa_ioc_ownership_reset(&bfa->ioc); + bfa_ioc_pll_init(&bfa->ioc); +} #endif diff --git a/drivers/scsi/bfa/bfa_ioc.c b/drivers/scsi/bfa/bfa_ioc.c index 569b35d19a25..a5f9745315b1 100644 --- a/drivers/scsi/bfa/bfa_ioc.c +++ b/drivers/scsi/bfa/bfa_ioc.c @@ -33,12 +33,11 @@ BFA_TRC_FILE(HAL, IOC); * IOC local definitions */ #define BFA_IOC_TOV 2000 /* msecs */ -#define BFA_IOC_HB_TOV 1000 /* msecs */ -#define BFA_IOC_HB_FAIL_MAX 4 -#define BFA_IOC_HWINIT_MAX 2 +#define BFA_IOC_HWSEM_TOV 500 /* msecs */ +#define BFA_IOC_HB_TOV 500 /* msecs */ +#define BFA_IOC_HWINIT_MAX 2 #define BFA_IOC_FWIMG_MINSZ (16 * 1024) -#define BFA_IOC_TOV_RECOVER (BFA_IOC_HB_FAIL_MAX * BFA_IOC_HB_TOV \ - + BFA_IOC_TOV) +#define BFA_IOC_TOV_RECOVER BFA_IOC_HB_TOV #define bfa_ioc_timer_start(__ioc) \ bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->ioc_timer, \ @@ -51,11 +50,24 @@ BFA_TRC_FILE(HAL, IOC); (sizeof(struct bfa_trc_mod_s) - \ BFA_TRC_MAX * sizeof(struct bfa_trc_s))) #define BFA_DBG_FWTRC_OFF(_fn) (BFI_IOC_TRC_OFF + BFA_DBG_FWTRC_LEN * (_fn)) -#define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++) -#define BFA_FLASH_CHUNK_NO(off) (off / BFI_FLASH_CHUNK_SZ_WORDS) -#define BFA_FLASH_OFFSET_IN_CHUNK(off) (off % BFI_FLASH_CHUNK_SZ_WORDS) -#define BFA_FLASH_CHUNK_ADDR(chunkno) (chunkno * BFI_FLASH_CHUNK_SZ_WORDS) +/** + * Asic specific macros : see bfa_hw_cb.c and bfa_hw_ct.c for details. + */ + +#define bfa_ioc_firmware_lock(__ioc) \ + ((__ioc)->ioc_hwif->ioc_firmware_lock(__ioc)) +#define bfa_ioc_firmware_unlock(__ioc) \ + ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc)) +#define bfa_ioc_fwimg_get_chunk(__ioc, __off) \ + ((__ioc)->ioc_hwif->ioc_fwimg_get_chunk(__ioc, __off)) +#define bfa_ioc_fwimg_get_size(__ioc) \ + ((__ioc)->ioc_hwif->ioc_fwimg_get_size(__ioc)) +#define bfa_ioc_reg_init(__ioc) ((__ioc)->ioc_hwif->ioc_reg_init(__ioc)) +#define bfa_ioc_map_port(__ioc) ((__ioc)->ioc_hwif->ioc_map_port(__ioc)) +#define bfa_ioc_notify_hbfail(__ioc) \ + ((__ioc)->ioc_hwif->ioc_notify_hbfail(__ioc)) + bfa_boolean_t bfa_auto_recover = BFA_TRUE; /* @@ -64,7 +76,6 @@ bfa_boolean_t bfa_auto_recover = BFA_TRUE; static void bfa_ioc_aen_post(struct bfa_ioc_s *bfa, enum bfa_ioc_aen_event event); static void bfa_ioc_hw_sem_get(struct bfa_ioc_s *ioc); -static void bfa_ioc_hw_sem_release(struct bfa_ioc_s *ioc); static void bfa_ioc_hw_sem_get_cancel(struct bfa_ioc_s *ioc); static void bfa_ioc_hwinit(struct bfa_ioc_s *ioc, bfa_boolean_t force); static void bfa_ioc_timeout(void *ioc); @@ -77,8 +88,6 @@ static void bfa_ioc_reset(struct bfa_ioc_s *ioc, bfa_boolean_t force); static void bfa_ioc_mbox_poll(struct bfa_ioc_s *ioc); static void bfa_ioc_mbox_hbfail(struct bfa_ioc_s *ioc); static void bfa_ioc_recover(struct bfa_ioc_s *ioc); -static bfa_boolean_t bfa_ioc_firmware_lock(struct bfa_ioc_s *ioc); -static void bfa_ioc_firmware_unlock(struct bfa_ioc_s *ioc); static void bfa_ioc_disable_comp(struct bfa_ioc_s *ioc); static void bfa_ioc_lpu_stop(struct bfa_ioc_s *ioc); @@ -508,14 +517,19 @@ bfa_ioc_sm_disabling(struct bfa_ioc_s *ioc, enum ioc_event event) bfa_trc(ioc, event); switch (event) { - case IOC_E_HWERROR: case IOC_E_FWRSP_DISABLE: + bfa_ioc_timer_stop(ioc); + bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled); + break; + + case IOC_E_HWERROR: bfa_ioc_timer_stop(ioc); /* * !!! fall through !!! */ case IOC_E_TIMEOUT: + bfa_reg_write(ioc->ioc_regs.ioc_fwstate, BFI_IOC_FAIL); bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled); break; @@ -608,15 +622,12 @@ bfa_ioc_sm_hbfail_entry(struct bfa_ioc_s *ioc) * Mark IOC as failed in hardware and stop firmware. */ bfa_ioc_lpu_stop(ioc); - bfa_reg_write(ioc->ioc_regs.ioc_fwstate, BFI_IOC_HBFAIL); + bfa_reg_write(ioc->ioc_regs.ioc_fwstate, BFI_IOC_FAIL); - if (ioc->pcidev.device_id == BFA_PCI_DEVICE_ID_CT) { - bfa_reg_write(ioc->ioc_regs.ll_halt, __FW_INIT_HALT_P); - /* - * Wait for halt to take effect - */ - bfa_reg_read(ioc->ioc_regs.ll_halt); - } + /** + * Notify other functions on HB failure. + */ + bfa_ioc_notify_hbfail(ioc); /** * Notify driver and common modules registered for notification. @@ -672,6 +683,12 @@ bfa_ioc_sm_hbfail(struct bfa_ioc_s *ioc, enum ioc_event event) */ break; + case IOC_E_HWERROR: + /* + * HB failure notification, ignore. + */ + break; + default: bfa_sm_fault(ioc, event); } @@ -700,7 +717,7 @@ bfa_ioc_disable_comp(struct bfa_ioc_s *ioc) } } -static void +void bfa_ioc_sem_timeout(void *ioc_arg) { struct bfa_ioc_s *ioc = (struct bfa_ioc_s *)ioc_arg; @@ -708,26 +725,32 @@ bfa_ioc_sem_timeout(void *ioc_arg) bfa_ioc_hw_sem_get(ioc); } -static void -bfa_ioc_usage_sem_get(struct bfa_ioc_s *ioc) +bfa_boolean_t +bfa_ioc_sem_get(bfa_os_addr_t sem_reg) { - u32 r32; - int cnt = 0; -#define BFA_SEM_SPINCNT 1000 + u32 r32; + int cnt = 0; +#define BFA_SEM_SPINCNT 3000 - do { - r32 = bfa_reg_read(ioc->ioc_regs.ioc_usage_sem_reg); + r32 = bfa_reg_read(sem_reg); + + while (r32 && (cnt < BFA_SEM_SPINCNT)) { cnt++; - if (cnt > BFA_SEM_SPINCNT) - break; - } while (r32 != 0); + bfa_os_udelay(2); + r32 = bfa_reg_read(sem_reg); + } + + if (r32 == 0) + return BFA_TRUE; + bfa_assert(cnt < BFA_SEM_SPINCNT); + return BFA_FALSE; } -static void -bfa_ioc_usage_sem_release(struct bfa_ioc_s *ioc) +void +bfa_ioc_sem_release(bfa_os_addr_t sem_reg) { - bfa_reg_write(ioc->ioc_regs.ioc_usage_sem_reg, 1); + bfa_reg_write(sem_reg, 1); } static void @@ -737,7 +760,7 @@ bfa_ioc_hw_sem_get(struct bfa_ioc_s *ioc) /** * First read to the semaphore register will return 0, subsequent reads - * will return 1. Semaphore is released by writing 0 to the register + * will return 1. Semaphore is released by writing 1 to the register */ r32 = bfa_reg_read(ioc->ioc_regs.ioc_sem_reg); if (r32 == 0) { @@ -746,10 +769,10 @@ bfa_ioc_hw_sem_get(struct bfa_ioc_s *ioc) } bfa_timer_begin(ioc->timer_mod, &ioc->sem_timer, bfa_ioc_sem_timeout, - ioc, BFA_IOC_TOV); + ioc, BFA_IOC_HWSEM_TOV); } -static void +void bfa_ioc_hw_sem_release(struct bfa_ioc_s *ioc) { bfa_reg_write(ioc->ioc_regs.ioc_sem_reg, 1); @@ -828,7 +851,7 @@ bfa_ioc_lpu_stop(struct bfa_ioc_s *ioc) /** * Get driver and firmware versions. */ -static void +void bfa_ioc_fwver_get(struct bfa_ioc_s *ioc, struct bfi_ioc_image_hdr_s *fwhdr) { u32 pgnum, pgoff; @@ -847,24 +870,10 @@ bfa_ioc_fwver_get(struct bfa_ioc_s *ioc, struct bfi_ioc_image_hdr_s *fwhdr) } } -static u32 * -bfa_ioc_fwimg_get_chunk(struct bfa_ioc_s *ioc, u32 off) -{ - if (ioc->ctdev) - return bfi_image_ct_get_chunk(off); - return bfi_image_cb_get_chunk(off); -} - -static u32 -bfa_ioc_fwimg_get_size(struct bfa_ioc_s *ioc) -{ -return (ioc->ctdev) ? bfi_image_ct_size : bfi_image_cb_size; -} - /** * Returns TRUE if same. */ -static bfa_boolean_t +bfa_boolean_t bfa_ioc_fwver_cmp(struct bfa_ioc_s *ioc, struct bfi_ioc_image_hdr_s *fwhdr) { struct bfi_ioc_image_hdr_s *drv_fwhdr; @@ -920,95 +929,6 @@ bfa_ioc_fwver_valid(struct bfa_ioc_s *ioc) return bfa_ioc_fwver_cmp(ioc, &fwhdr); } -/** - * Return true if firmware of current driver matches the running firmware. - */ -static bfa_boolean_t -bfa_ioc_firmware_lock(struct bfa_ioc_s *ioc) -{ - enum bfi_ioc_state ioc_fwstate; - u32 usecnt; - struct bfi_ioc_image_hdr_s fwhdr; - - /** - * Firmware match check is relevant only for CNA. - */ - if (!ioc->cna) - return BFA_TRUE; - - /** - * If bios boot (flash based) -- do not increment usage count - */ - if (bfa_ioc_fwimg_get_size(ioc) < BFA_IOC_FWIMG_MINSZ) - return BFA_TRUE; - - bfa_ioc_usage_sem_get(ioc); - usecnt = bfa_reg_read(ioc->ioc_regs.ioc_usage_reg); - - /** - * If usage count is 0, always return TRUE. - */ - if (usecnt == 0) { - bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, 1); - bfa_ioc_usage_sem_release(ioc); - bfa_trc(ioc, usecnt); - return BFA_TRUE; - } - - ioc_fwstate = bfa_reg_read(ioc->ioc_regs.ioc_fwstate); - bfa_trc(ioc, ioc_fwstate); - - /** - * Use count cannot be non-zero and chip in uninitialized state. - */ - bfa_assert(ioc_fwstate != BFI_IOC_UNINIT); - - /** - * Check if another driver with a different firmware is active - */ - bfa_ioc_fwver_get(ioc, &fwhdr); - if (!bfa_ioc_fwver_cmp(ioc, &fwhdr)) { - bfa_ioc_usage_sem_release(ioc); - bfa_trc(ioc, usecnt); - return BFA_FALSE; - } - - /** - * Same firmware version. Increment the reference count. - */ - usecnt++; - bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, usecnt); - bfa_ioc_usage_sem_release(ioc); - bfa_trc(ioc, usecnt); - return BFA_TRUE; -} - -static void -bfa_ioc_firmware_unlock(struct bfa_ioc_s *ioc) -{ - u32 usecnt; - - /** - * Firmware lock is relevant only for CNA. - * If bios boot (flash based) -- do not decrement usage count - */ - if (!ioc->cna || (bfa_ioc_fwimg_get_size(ioc) < BFA_IOC_FWIMG_MINSZ)) - return; - - /** - * decrement usage count - */ - bfa_ioc_usage_sem_get(ioc); - usecnt = bfa_reg_read(ioc->ioc_regs.ioc_usage_reg); - bfa_assert(usecnt > 0); - - usecnt--; - bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, usecnt); - bfa_trc(ioc, usecnt); - - bfa_ioc_usage_sem_release(ioc); -} - /** * Conditionally flush any pending message from firmware at start. */ @@ -1152,33 +1072,27 @@ bfa_ioc_send_getattr(struct bfa_ioc_s *ioc) static void bfa_ioc_hb_check(void *cbarg) { - struct bfa_ioc_s *ioc = cbarg; - u32 hb_count; + struct bfa_ioc_s *ioc = cbarg; + u32 hb_count; hb_count = bfa_reg_read(ioc->ioc_regs.heartbeat); if (ioc->hb_count == hb_count) { - ioc->hb_fail++; - } else { - ioc->hb_count = hb_count; - ioc->hb_fail = 0; - } - - if (ioc->hb_fail >= BFA_IOC_HB_FAIL_MAX) { - bfa_log(ioc->logm, BFA_LOG_HAL_HEARTBEAT_FAILURE, hb_count); - ioc->hb_fail = 0; + bfa_log(ioc->logm, BFA_LOG_HAL_HEARTBEAT_FAILURE, + hb_count); bfa_ioc_recover(ioc); return; + } else { + ioc->hb_count = hb_count; } bfa_ioc_mbox_poll(ioc); - bfa_timer_begin(ioc->timer_mod, &ioc->ioc_timer, bfa_ioc_hb_check, ioc, - BFA_IOC_HB_TOV); + bfa_timer_begin(ioc->timer_mod, &ioc->ioc_timer, bfa_ioc_hb_check, + ioc, BFA_IOC_HB_TOV); } static void bfa_ioc_hb_monitor(struct bfa_ioc_s *ioc) { - ioc->hb_fail = 0; ioc->hb_count = bfa_reg_read(ioc->ioc_regs.heartbeat); bfa_timer_begin(ioc->timer_mod, &ioc->ioc_timer, bfa_ioc_hb_check, ioc, BFA_IOC_HB_TOV); @@ -1190,112 +1104,6 @@ bfa_ioc_hb_stop(struct bfa_ioc_s *ioc) bfa_timer_stop(&ioc->ioc_timer); } -/** - * Host to LPU mailbox message addresses - */ -static struct { - u32 hfn_mbox, lpu_mbox, hfn_pgn; -} iocreg_fnreg[] = { - { - HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0}, { - HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1}, { - HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2}, { - HOSTFN3_LPU_MBOX0_8, LPU_HOSTFN3_MBOX0_8, HOST_PAGE_NUM_FN3} -}; - -/** - * Host <-> LPU mailbox command/status registers - port 0 - */ -static struct { - u32 hfn, lpu; -} iocreg_mbcmd_p0[] = { - { - HOSTFN0_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN0_MBOX0_CMD_STAT}, { - HOSTFN1_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN1_MBOX0_CMD_STAT}, { - HOSTFN2_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN2_MBOX0_CMD_STAT}, { - HOSTFN3_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN3_MBOX0_CMD_STAT} -}; - -/** - * Host <-> LPU mailbox command/status registers - port 1 - */ -static struct { - u32 hfn, lpu; -} iocreg_mbcmd_p1[] = { - { - HOSTFN0_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN0_MBOX0_CMD_STAT}, { - HOSTFN1_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN1_MBOX0_CMD_STAT}, { - HOSTFN2_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN2_MBOX0_CMD_STAT}, { - HOSTFN3_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN3_MBOX0_CMD_STAT} -}; - -/** - * Shared IRQ handling in INTX mode - */ -static struct { - u32 isr, msk; -} iocreg_shirq_next[] = { - { - HOSTFN1_INT_STATUS, HOSTFN1_INT_MSK}, { - HOSTFN2_INT_STATUS, HOSTFN2_INT_MSK}, { - HOSTFN3_INT_STATUS, HOSTFN3_INT_MSK}, { -HOSTFN0_INT_STATUS, HOSTFN0_INT_MSK},}; - -static void -bfa_ioc_reg_init(struct bfa_ioc_s *ioc) -{ - bfa_os_addr_t rb; - int pcifn = bfa_ioc_pcifn(ioc); - - rb = bfa_ioc_bar0(ioc); - - ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox; - ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox; - ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn; - - if (ioc->port_id == 0) { - ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG; - ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG; - ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].hfn; - ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].lpu; - ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; - } else { - ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG); - ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG); - ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].hfn; - ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].lpu; - ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; - } - - /** - * Shared IRQ handling in INTX mode - */ - ioc->ioc_regs.shirq_isr_next = rb + iocreg_shirq_next[pcifn].isr; - ioc->ioc_regs.shirq_msk_next = rb + iocreg_shirq_next[pcifn].msk; - - /* - * PSS control registers - */ - ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); - ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_425_CTL_REG); - ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_312_CTL_REG); - - /* - * IOC semaphore registers and serialization - */ - ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG); - ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG); - ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT); - - /** - * sram memory access - */ - ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START); - ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CB; - if (ioc->pcidev.device_id == BFA_PCI_DEVICE_ID_CT) - ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT; -} - /** * Initiate a full firmware download. */ @@ -1332,17 +1140,17 @@ bfa_ioc_download_fw(struct bfa_ioc_s *ioc, u32 boot_type, for (i = 0; i < bfa_ioc_fwimg_get_size(ioc); i++) { - if (BFA_FLASH_CHUNK_NO(i) != chunkno) { - chunkno = BFA_FLASH_CHUNK_NO(i); + if (BFA_IOC_FLASH_CHUNK_NO(i) != chunkno) { + chunkno = BFA_IOC_FLASH_CHUNK_NO(i); fwimg = bfa_ioc_fwimg_get_chunk(ioc, - BFA_FLASH_CHUNK_ADDR(chunkno)); + BFA_IOC_FLASH_CHUNK_ADDR(chunkno)); } /** * write smem */ bfa_mem_write(ioc->ioc_regs.smem_page_start, loff, - fwimg[BFA_FLASH_OFFSET_IN_CHUNK(i)]); + fwimg[BFA_IOC_FLASH_OFFSET_IN_CHUNK(i)]); loff += sizeof(u32); @@ -1439,168 +1247,10 @@ bfa_ioc_mbox_hbfail(struct bfa_ioc_s *ioc) bfa_q_deq(&mod->cmd_q, &cmd); } -/** - * Initialize IOC to port mapping. - */ - -#define FNC_PERS_FN_SHIFT(__fn) ((__fn) * 8) -static void -bfa_ioc_map_port(struct bfa_ioc_s *ioc) -{ - bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; - u32 r32; - - /** - * For crossbow, port id is same as pci function. - */ - if (ioc->pcidev.device_id != BFA_PCI_DEVICE_ID_CT) { - ioc->port_id = bfa_ioc_pcifn(ioc); - return; - } - - /** - * For catapult, base port id on personality register and IOC type - */ - r32 = bfa_reg_read(rb + FNC_PERS_REG); - r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)); - ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH; - - bfa_trc(ioc, bfa_ioc_pcifn(ioc)); - bfa_trc(ioc, ioc->port_id); -} - - - /** * bfa_ioc_public */ -/** -* Set interrupt mode for a function: INTX or MSIX - */ -void -bfa_ioc_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix) -{ - bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; - u32 r32, mode; - - r32 = bfa_reg_read(rb + FNC_PERS_REG); - bfa_trc(ioc, r32); - - mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) & - __F0_INTX_STATUS; - - /** - * If already in desired mode, do not change anything - */ - if (!msix && mode) - return; - - if (msix) - mode = __F0_INTX_STATUS_MSIX; - else - mode = __F0_INTX_STATUS_INTA; - - r32 &= ~(__F0_INTX_STATUS << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))); - r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))); - bfa_trc(ioc, r32); - - bfa_reg_write(rb + FNC_PERS_REG, r32); -} - -bfa_status_t -bfa_ioc_pll_init(struct bfa_ioc_s *ioc) -{ - bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; - u32 pll_sclk, pll_fclk, r32; - - if (ioc->pcidev.device_id == BFA_PCI_DEVICE_ID_CT) { - pll_sclk = - __APP_PLL_312_ENABLE | __APP_PLL_312_LRESETN | - __APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(0U) | - __APP_PLL_312_JITLMT0_1(3U) | - __APP_PLL_312_CNTLMT0_1(1U); - pll_fclk = - __APP_PLL_425_ENABLE | __APP_PLL_425_LRESETN | - __APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(0U) | - __APP_PLL_425_JITLMT0_1(3U) | - __APP_PLL_425_CNTLMT0_1(1U); - - /** - * For catapult, choose operational mode FC/FCoE - */ - if (ioc->fcmode) { - bfa_reg_write((rb + OP_MODE), 0); - bfa_reg_write((rb + ETH_MAC_SER_REG), - __APP_EMS_CMLCKSEL | __APP_EMS_REFCKBUFEN2 - | __APP_EMS_CHANNEL_SEL); - } else { - ioc->pllinit = BFA_TRUE; - bfa_reg_write((rb + OP_MODE), __GLOBAL_FCOE_MODE); - bfa_reg_write((rb + ETH_MAC_SER_REG), - __APP_EMS_REFCKBUFEN1); - } - } else { - pll_sclk = - __APP_PLL_312_ENABLE | __APP_PLL_312_LRESETN | - __APP_PLL_312_P0_1(3U) | __APP_PLL_312_JITLMT0_1(3U) | - __APP_PLL_312_CNTLMT0_1(3U); - pll_fclk = - __APP_PLL_425_ENABLE | __APP_PLL_425_LRESETN | - __APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(3U) | - __APP_PLL_425_JITLMT0_1(3U) | - __APP_PLL_425_CNTLMT0_1(3U); - } - - bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_UNINIT); - bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_UNINIT); - - bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); - bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); - bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); - bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); - bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); - bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); - - bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, - __APP_PLL_312_LOGIC_SOFT_RESET); - bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, - __APP_PLL_312_BYPASS | __APP_PLL_312_LOGIC_SOFT_RESET); - bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, - __APP_PLL_425_LOGIC_SOFT_RESET); - bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, - __APP_PLL_425_BYPASS | __APP_PLL_425_LOGIC_SOFT_RESET); - bfa_os_udelay(2); - bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, - __APP_PLL_312_LOGIC_SOFT_RESET); - bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, - __APP_PLL_425_LOGIC_SOFT_RESET); - - bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, - pll_sclk | __APP_PLL_312_LOGIC_SOFT_RESET); - bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, - pll_fclk | __APP_PLL_425_LOGIC_SOFT_RESET); - - /** - * Wait for PLLs to lock. - */ - bfa_os_udelay(2000); - bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); - bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); - - bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk); - bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk); - - if (ioc->pcidev.device_id == BFA_PCI_DEVICE_ID_CT) { - bfa_reg_write((rb + MBIST_CTL_REG), __EDRAM_BISTR_START); - bfa_os_udelay(1000); - r32 = bfa_reg_read((rb + MBIST_STAT_REG)); - bfa_trc(ioc, r32); - } - - return BFA_STATUS_OK; -} - /** * Interface used by diag module to do firmware boot with memory test * as the entry vector. @@ -1764,6 +1414,14 @@ bfa_ioc_pci_init(struct bfa_ioc_s *ioc, struct bfa_pcidev_s *pcidev, ioc->ctdev = (ioc->pcidev.device_id == BFA_PCI_DEVICE_ID_CT); ioc->cna = ioc->ctdev && !ioc->fcmode; + /** + * Set asic specific interfaces. See bfa_ioc_cb.c and bfa_ioc_ct.c + */ + if (ioc->ctdev) + bfa_ioc_set_ct_hwif(ioc); + else + bfa_ioc_set_cb_hwif(ioc); + bfa_ioc_map_port(ioc); bfa_ioc_reg_init(ioc); } @@ -1973,7 +1631,7 @@ bfa_ioc_fw_mismatch(struct bfa_ioc_s *ioc) ((__sm) == BFI_IOC_INITING) || \ ((__sm) == BFI_IOC_HWINIT) || \ ((__sm) == BFI_IOC_DISABLED) || \ - ((__sm) == BFI_IOC_HBFAIL) || \ + ((__sm) == BFI_IOC_FAIL) || \ ((__sm) == BFI_IOC_CFG_DISABLED)) /** @@ -2194,29 +1852,6 @@ bfa_ioc_get_fcmode(struct bfa_ioc_s *ioc) return ioc->fcmode || (ioc->pcidev.device_id != BFA_PCI_DEVICE_ID_CT); } -/** - * Return true if interrupt should be claimed. - */ -bfa_boolean_t -bfa_ioc_intx_claim(struct bfa_ioc_s *ioc) -{ - u32 isr, msk; - - /** - * Always claim if not catapult. - */ - if (!ioc->ctdev) - return BFA_TRUE; - - /** - * FALSE if next device is claiming interrupt. - * TRUE if next device is not interrupting or not present. - */ - msk = bfa_reg_read(ioc->ioc_regs.shirq_msk_next); - isr = bfa_reg_read(ioc->ioc_regs.shirq_isr_next); - return !(isr & ~msk); -} - /** * Send AEN notification */ @@ -2304,6 +1939,13 @@ bfa_ioc_debug_fwtrc(struct bfa_ioc_s *ioc, void *trcdata, int *trclen) pgnum = bfa_ioc_smem_pgnum(ioc, loff); loff = bfa_ioc_smem_pgoff(ioc, loff); + + /* + * Hold semaphore to serialize pll init and fwtrc. + */ + if (BFA_FALSE == bfa_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg)) + return BFA_STATUS_FAILED; + bfa_reg_write(ioc->ioc_regs.host_page_num_fn, pgnum); tlen = *trclen; @@ -2329,6 +1971,12 @@ bfa_ioc_debug_fwtrc(struct bfa_ioc_s *ioc, void *trcdata, int *trclen) } bfa_reg_write(ioc->ioc_regs.host_page_num_fn, bfa_ioc_smem_pgnum(ioc, 0)); + + /* + * release semaphore. + */ + bfa_ioc_sem_release(ioc->ioc_regs.ioc_init_sem_reg); + bfa_trc(ioc, pgnum); *trclen = tlen * sizeof(u32); diff --git a/drivers/scsi/bfa/bfa_ioc.h b/drivers/scsi/bfa/bfa_ioc.h index 7c30f05ab137..1633a50187f7 100644 --- a/drivers/scsi/bfa/bfa_ioc.h +++ b/drivers/scsi/bfa/bfa_ioc.h @@ -78,11 +78,13 @@ struct bfa_ioc_regs_s { bfa_os_addr_t app_pll_slow_ctl_reg; bfa_os_addr_t ioc_sem_reg; bfa_os_addr_t ioc_usage_sem_reg; + bfa_os_addr_t ioc_init_sem_reg; bfa_os_addr_t ioc_usage_reg; bfa_os_addr_t host_page_num_fn; bfa_os_addr_t heartbeat; bfa_os_addr_t ioc_fwstate; bfa_os_addr_t ll_halt; + bfa_os_addr_t err_set; bfa_os_addr_t shirq_isr_next; bfa_os_addr_t shirq_msk_next; bfa_os_addr_t smem_page_start; @@ -154,7 +156,6 @@ struct bfa_ioc_s { struct bfa_timer_s ioc_timer; struct bfa_timer_s sem_timer; u32 hb_count; - u32 hb_fail; u32 retry_count; struct list_head hb_notify_q; void *dbg_fwsave; @@ -177,6 +178,22 @@ struct bfa_ioc_s { struct bfi_ioc_attr_s *attr; struct bfa_ioc_cbfn_s *cbfn; struct bfa_ioc_mbox_mod_s mbox_mod; + struct bfa_ioc_hwif_s *ioc_hwif; +}; + +struct bfa_ioc_hwif_s { + bfa_status_t (*ioc_pll_init) (struct bfa_ioc_s *ioc); + bfa_boolean_t (*ioc_firmware_lock) (struct bfa_ioc_s *ioc); + void (*ioc_firmware_unlock) (struct bfa_ioc_s *ioc); + u32 * (*ioc_fwimg_get_chunk) (struct bfa_ioc_s *ioc, + u32 off); + u32 (*ioc_fwimg_get_size) (struct bfa_ioc_s *ioc); + void (*ioc_reg_init) (struct bfa_ioc_s *ioc); + void (*ioc_map_port) (struct bfa_ioc_s *ioc); + void (*ioc_isr_mode_set) (struct bfa_ioc_s *ioc, + bfa_boolean_t msix); + void (*ioc_notify_hbfail) (struct bfa_ioc_s *ioc); + void (*ioc_ownership_reset) (struct bfa_ioc_s *ioc); }; #define bfa_ioc_pcifn(__ioc) ((__ioc)->pcidev.pci_func) @@ -191,6 +208,15 @@ struct bfa_ioc_s { #define bfa_ioc_rx_bbcredit(__ioc) ((__ioc)->attr->rx_bbcredit) #define bfa_ioc_speed_sup(__ioc) \ BFI_ADAPTER_GETP(SPEED, (__ioc)->attr->adapter_prop) +#define bfa_ioc_get_nports(__ioc) \ + BFI_ADAPTER_GETP(NPORTS, (__ioc)->attr->adapter_prop) + +#define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++) +#define BFA_IOC_FWIMG_MINSZ (16 * 1024) + +#define BFA_IOC_FLASH_CHUNK_NO(off) (off / BFI_FLASH_CHUNK_SZ_WORDS) +#define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off) (off % BFI_FLASH_CHUNK_SZ_WORDS) +#define BFA_IOC_FLASH_CHUNK_ADDR(chunkno) (chunkno * BFI_FLASH_CHUNK_SZ_WORDS) /** * IOC mailbox interface @@ -207,6 +233,14 @@ void bfa_ioc_mbox_regisr(struct bfa_ioc_s *ioc, enum bfi_mclass mc, /** * IOC interfaces */ +#define bfa_ioc_pll_init(__ioc) ((__ioc)->ioc_hwif->ioc_pll_init(__ioc)) +#define bfa_ioc_isr_mode_set(__ioc, __msix) \ + ((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix)) +#define bfa_ioc_ownership_reset(__ioc) \ + ((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc)) + +void bfa_ioc_set_ct_hwif(struct bfa_ioc_s *ioc); +void bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc); void bfa_ioc_attach(struct bfa_ioc_s *ioc, void *bfa, struct bfa_ioc_cbfn_s *cbfn, struct bfa_timer_mod_s *timer_mod, struct bfa_trc_mod_s *trcmod, @@ -223,8 +257,6 @@ bfa_boolean_t bfa_ioc_intx_claim(struct bfa_ioc_s *ioc); void bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type, u32 boot_param); void bfa_ioc_isr(struct bfa_ioc_s *ioc, struct bfi_mbmsg_s *msg); void bfa_ioc_error_isr(struct bfa_ioc_s *ioc); -void bfa_ioc_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t intx); -bfa_status_t bfa_ioc_pll_init(struct bfa_ioc_s *ioc); bfa_boolean_t bfa_ioc_is_operational(struct bfa_ioc_s *ioc); bfa_boolean_t bfa_ioc_is_disabled(struct bfa_ioc_s *ioc); bfa_boolean_t bfa_ioc_fw_mismatch(struct bfa_ioc_s *ioc); @@ -245,6 +277,13 @@ void bfa_ioc_set_fcmode(struct bfa_ioc_s *ioc); bfa_boolean_t bfa_ioc_get_fcmode(struct bfa_ioc_s *ioc); void bfa_ioc_hbfail_register(struct bfa_ioc_s *ioc, struct bfa_ioc_hbfail_notify_s *notify); +bfa_boolean_t bfa_ioc_sem_get(bfa_os_addr_t sem_reg); +void bfa_ioc_sem_release(bfa_os_addr_t sem_reg); +void bfa_ioc_hw_sem_release(struct bfa_ioc_s *ioc); +void bfa_ioc_fwver_get(struct bfa_ioc_s *ioc, + struct bfi_ioc_image_hdr_s *fwhdr); +bfa_boolean_t bfa_ioc_fwver_cmp(struct bfa_ioc_s *ioc, + struct bfi_ioc_image_hdr_s *fwhdr); /* * bfa mfg wwn API functions diff --git a/drivers/scsi/bfa/bfa_ioc_cb.c b/drivers/scsi/bfa/bfa_ioc_cb.c new file mode 100644 index 000000000000..d1d625bcd721 --- /dev/null +++ b/drivers/scsi/bfa/bfa_ioc_cb.c @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2005-2009 Brocade Communications Systems, Inc. + * All rights reserved + * www.brocade.com + * + * Linux driver for Brocade Fibre Channel Host Bus Adapter. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License (GPL) Version 2 as + * published by the Free Software Foundation + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +BFA_TRC_FILE(CNA, IOC_CB); + +/* + * forward declarations + */ +static bfa_status_t bfa_ioc_cb_pll_init(struct bfa_ioc_s *ioc); +static bfa_boolean_t bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc); +static void bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc); +static u32 *bfa_ioc_cb_fwimg_get_chunk(struct bfa_ioc_s *ioc, u32 off); +static u32 bfa_ioc_cb_fwimg_get_size(struct bfa_ioc_s *ioc); +static void bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc); +static void bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc); +static void bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix); +static void bfa_ioc_cb_notify_hbfail(struct bfa_ioc_s *ioc); +static void bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc); + +struct bfa_ioc_hwif_s hwif_cb = { + bfa_ioc_cb_pll_init, + bfa_ioc_cb_firmware_lock, + bfa_ioc_cb_firmware_unlock, + bfa_ioc_cb_fwimg_get_chunk, + bfa_ioc_cb_fwimg_get_size, + bfa_ioc_cb_reg_init, + bfa_ioc_cb_map_port, + bfa_ioc_cb_isr_mode_set, + bfa_ioc_cb_notify_hbfail, + bfa_ioc_cb_ownership_reset, +}; + +/** + * Called from bfa_ioc_attach() to map asic specific calls. + */ +void +bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc) +{ + ioc->ioc_hwif = &hwif_cb; +} + +static uint32_t * +bfa_ioc_cb_fwimg_get_chunk(struct bfa_ioc_s *ioc, uint32_t off) +{ + return bfi_image_cb_get_chunk(off); +} + +static uint32_t +bfa_ioc_cb_fwimg_get_size(struct bfa_ioc_s *ioc) +{ + return bfi_image_cb_size; +} + +/** + * Return true if firmware of current driver matches the running firmware. + */ +static bfa_boolean_t +bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc) +{ + return BFA_TRUE; +} + +static void +bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc) +{ +} + +/** + * Notify other functions on HB failure. + */ +static void +bfa_ioc_cb_notify_hbfail(struct bfa_ioc_s *ioc) +{ + bfa_reg_write(ioc->ioc_regs.err_set, __PSS_ERR_STATUS_SET); + bfa_reg_read(ioc->ioc_regs.err_set); +} + +/** + * Host to LPU mailbox message addresses + */ +static struct { uint32_t hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = { + { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 }, + { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 } +}; + +/** + * Host <-> LPU mailbox command/status registers + */ +static struct { uint32_t hfn, lpu; } iocreg_mbcmd[] = { + { HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT }, + { HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT } +}; + +static void +bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc) +{ + bfa_os_addr_t rb; + int pcifn = bfa_ioc_pcifn(ioc); + + rb = bfa_ioc_bar0(ioc); + + ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox; + ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox; + ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn; + + if (ioc->port_id == 0) { + ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG; + ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG; + } else { + ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG); + ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG); + } + + /** + * Host <-> LPU mailbox command/status registers + */ + ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn; + ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu; + + /* + * PSS control registers + */ + ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); + ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_400_CTL_REG); + ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_212_CTL_REG); + + /* + * IOC semaphore registers and serialization + */ + ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG); + ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG); + + /** + * sram memory access + */ + ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START); + ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CB; + + /* + * err set reg : for notification of hb failure + */ + ioc->ioc_regs.err_set = (rb + ERR_SET_REG); +} + +/** + * Initialize IOC to port mapping. + */ +static void +bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc) +{ + /** + * For crossbow, port id is same as pci function. + */ + ioc->port_id = bfa_ioc_pcifn(ioc); + bfa_trc(ioc, ioc->port_id); +} + +/** + * Set interrupt mode for a function: INTX or MSIX + */ +static void +bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix) +{ +} + +static bfa_status_t +bfa_ioc_cb_pll_init(struct bfa_ioc_s *ioc) +{ + bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; + uint32_t pll_sclk, pll_fclk; + + /* + * Hold semaphore so that nobody can access the chip during init. + */ + bfa_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg); + + pll_sclk = __APP_PLL_212_ENABLE | __APP_PLL_212_LRESETN | + __APP_PLL_212_P0_1(3U) | + __APP_PLL_212_JITLMT0_1(3U) | + __APP_PLL_212_CNTLMT0_1(3U); + pll_fclk = __APP_PLL_400_ENABLE | __APP_PLL_400_LRESETN | + __APP_PLL_400_RSEL200500 | __APP_PLL_400_P0_1(3U) | + __APP_PLL_400_JITLMT0_1(3U) | + __APP_PLL_400_CNTLMT0_1(3U); + + bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_UNINIT); + bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_UNINIT); + + bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); + bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); + bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); + bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); + bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); + bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); + + bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, + __APP_PLL_212_LOGIC_SOFT_RESET); + bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, + __APP_PLL_212_BYPASS | + __APP_PLL_212_LOGIC_SOFT_RESET); + bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, + __APP_PLL_400_LOGIC_SOFT_RESET); + bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, + __APP_PLL_400_BYPASS | + __APP_PLL_400_LOGIC_SOFT_RESET); + bfa_os_udelay(2); + bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, + __APP_PLL_212_LOGIC_SOFT_RESET); + bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, + __APP_PLL_400_LOGIC_SOFT_RESET); + + bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, + pll_sclk | __APP_PLL_212_LOGIC_SOFT_RESET); + bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, + pll_fclk | __APP_PLL_400_LOGIC_SOFT_RESET); + + /** + * Wait for PLLs to lock. + */ + bfa_os_udelay(2000); + bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); + bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); + + bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk); + bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk); + + /* + * release semaphore. + */ + bfa_ioc_sem_release(ioc->ioc_regs.ioc_init_sem_reg); + + return BFA_STATUS_OK; +} + +/** + * Cleanup hw semaphore and usecnt registers + */ +static void +bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc) +{ + + /* + * Read the hw sem reg to make sure that it is locked + * before we clear it. If it is not locked, writing 1 + * will lock it instead of clearing it. + */ + bfa_reg_read(ioc->ioc_regs.ioc_sem_reg); + bfa_ioc_hw_sem_release(ioc); +} diff --git a/drivers/scsi/bfa/bfa_ioc_ct.c b/drivers/scsi/bfa/bfa_ioc_ct.c new file mode 100644 index 000000000000..5de9c24efacf --- /dev/null +++ b/drivers/scsi/bfa/bfa_ioc_ct.c @@ -0,0 +1,422 @@ +/* + * Copyright (c) 2005-2009 Brocade Communications Systems, Inc. + * All rights reserved + * www.brocade.com + * + * Linux driver for Brocade Fibre Channel Host Bus Adapter. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License (GPL) Version 2 as + * published by the Free Software Foundation + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +BFA_TRC_FILE(CNA, IOC_CT); + +/* + * forward declarations + */ +static bfa_status_t bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc); +static bfa_boolean_t bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc); +static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc); +static uint32_t* bfa_ioc_ct_fwimg_get_chunk(struct bfa_ioc_s *ioc, + uint32_t off); +static uint32_t bfa_ioc_ct_fwimg_get_size(struct bfa_ioc_s *ioc); +static void bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc); +static void bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc); +static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix); +static void bfa_ioc_ct_notify_hbfail(struct bfa_ioc_s *ioc); +static void bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc); + +struct bfa_ioc_hwif_s hwif_ct = { + bfa_ioc_ct_pll_init, + bfa_ioc_ct_firmware_lock, + bfa_ioc_ct_firmware_unlock, + bfa_ioc_ct_fwimg_get_chunk, + bfa_ioc_ct_fwimg_get_size, + bfa_ioc_ct_reg_init, + bfa_ioc_ct_map_port, + bfa_ioc_ct_isr_mode_set, + bfa_ioc_ct_notify_hbfail, + bfa_ioc_ct_ownership_reset, +}; + +/** + * Called from bfa_ioc_attach() to map asic specific calls. + */ +void +bfa_ioc_set_ct_hwif(struct bfa_ioc_s *ioc) +{ + ioc->ioc_hwif = &hwif_ct; +} + +static uint32_t* +bfa_ioc_ct_fwimg_get_chunk(struct bfa_ioc_s *ioc, uint32_t off) +{ + return bfi_image_ct_get_chunk(off); +} + +static uint32_t +bfa_ioc_ct_fwimg_get_size(struct bfa_ioc_s *ioc) +{ + return bfi_image_ct_size; +} + +/** + * Return true if firmware of current driver matches the running firmware. + */ +static bfa_boolean_t +bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc) +{ + enum bfi_ioc_state ioc_fwstate; + uint32_t usecnt; + struct bfi_ioc_image_hdr_s fwhdr; + + /** + * Firmware match check is relevant only for CNA. + */ + if (!ioc->cna) + return BFA_TRUE; + + /** + * If bios boot (flash based) -- do not increment usage count + */ + if (bfa_ioc_ct_fwimg_get_size(ioc) < BFA_IOC_FWIMG_MINSZ) + return BFA_TRUE; + + bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg); + usecnt = bfa_reg_read(ioc->ioc_regs.ioc_usage_reg); + + /** + * If usage count is 0, always return TRUE. + */ + if (usecnt == 0) { + bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, 1); + bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg); + bfa_trc(ioc, usecnt); + return BFA_TRUE; + } + + ioc_fwstate = bfa_reg_read(ioc->ioc_regs.ioc_fwstate); + bfa_trc(ioc, ioc_fwstate); + + /** + * Use count cannot be non-zero and chip in uninitialized state. + */ + bfa_assert(ioc_fwstate != BFI_IOC_UNINIT); + + /** + * Check if another driver with a different firmware is active + */ + bfa_ioc_fwver_get(ioc, &fwhdr); + if (!bfa_ioc_fwver_cmp(ioc, &fwhdr)) { + bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg); + bfa_trc(ioc, usecnt); + return BFA_FALSE; + } + + /** + * Same firmware version. Increment the reference count. + */ + usecnt++; + bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, usecnt); + bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg); + bfa_trc(ioc, usecnt); + return BFA_TRUE; +} + +static void +bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc) +{ + uint32_t usecnt; + + /** + * Firmware lock is relevant only for CNA. + * If bios boot (flash based) -- do not decrement usage count + */ + if (!ioc->cna || bfa_ioc_ct_fwimg_get_size(ioc) < BFA_IOC_FWIMG_MINSZ) + return; + + /** + * decrement usage count + */ + bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg); + usecnt = bfa_reg_read(ioc->ioc_regs.ioc_usage_reg); + bfa_assert(usecnt > 0); + + usecnt--; + bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, usecnt); + bfa_trc(ioc, usecnt); + + bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg); +} + +/** + * Notify other functions on HB failure. + */ +static void +bfa_ioc_ct_notify_hbfail(struct bfa_ioc_s *ioc) +{ + + bfa_reg_write(ioc->ioc_regs.ll_halt, __FW_INIT_HALT_P); + /* Wait for halt to take effect */ + bfa_reg_read(ioc->ioc_regs.ll_halt); +} + +/** + * Host to LPU mailbox message addresses + */ +static struct { uint32_t hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = { + { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 }, + { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 }, + { HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 }, + { HOSTFN3_LPU_MBOX0_8, LPU_HOSTFN3_MBOX0_8, HOST_PAGE_NUM_FN3 } +}; + +/** + * Host <-> LPU mailbox command/status registers - port 0 + */ +static struct { uint32_t hfn, lpu; } iocreg_mbcmd_p0[] = { + { HOSTFN0_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN0_MBOX0_CMD_STAT }, + { HOSTFN1_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN1_MBOX0_CMD_STAT }, + { HOSTFN2_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN2_MBOX0_CMD_STAT }, + { HOSTFN3_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN3_MBOX0_CMD_STAT } +}; + +/** + * Host <-> LPU mailbox command/status registers - port 1 + */ +static struct { uint32_t hfn, lpu; } iocreg_mbcmd_p1[] = { + { HOSTFN0_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN0_MBOX0_CMD_STAT }, + { HOSTFN1_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN1_MBOX0_CMD_STAT }, + { HOSTFN2_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN2_MBOX0_CMD_STAT }, + { HOSTFN3_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN3_MBOX0_CMD_STAT } +}; + +static void +bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc) +{ + bfa_os_addr_t rb; + int pcifn = bfa_ioc_pcifn(ioc); + + rb = bfa_ioc_bar0(ioc); + + ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox; + ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox; + ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn; + + if (ioc->port_id == 0) { + ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG; + ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG; + ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].hfn; + ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].lpu; + ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; + } else { + ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG); + ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG); + ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].hfn; + ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].lpu; + ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; + } + + /* + * PSS control registers + */ + ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); + ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_425_CTL_REG); + ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_312_CTL_REG); + + /* + * IOC semaphore registers and serialization + */ + ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG); + ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG); + ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG); + ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT); + + /** + * sram memory access + */ + ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START); + ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT; +} + +/** + * Initialize IOC to port mapping. + */ + +#define FNC_PERS_FN_SHIFT(__fn) ((__fn) * 8) +static void +bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc) +{ + bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; + uint32_t r32; + + /** + * For catapult, base port id on personality register and IOC type + */ + r32 = bfa_reg_read(rb + FNC_PERS_REG); + r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)); + ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH; + + bfa_trc(ioc, bfa_ioc_pcifn(ioc)); + bfa_trc(ioc, ioc->port_id); +} + +/** + * Set interrupt mode for a function: INTX or MSIX + */ +static void +bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix) +{ + bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; + uint32_t r32, mode; + + r32 = bfa_reg_read(rb + FNC_PERS_REG); + bfa_trc(ioc, r32); + + mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) & + __F0_INTX_STATUS; + + /** + * If already in desired mode, do not change anything + */ + if (!msix && mode) + return; + + if (msix) + mode = __F0_INTX_STATUS_MSIX; + else + mode = __F0_INTX_STATUS_INTA; + + r32 &= ~(__F0_INTX_STATUS << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))); + r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))); + bfa_trc(ioc, r32); + + bfa_reg_write(rb + FNC_PERS_REG, r32); +} + +static bfa_status_t +bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc) +{ + bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; + uint32_t pll_sclk, pll_fclk, r32; + + /* + * Hold semaphore so that nobody can access the chip during init. + */ + bfa_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg); + + pll_sclk = __APP_PLL_312_ENABLE | __APP_PLL_312_LRESETN | + __APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(0U) | + __APP_PLL_312_JITLMT0_1(3U) | + __APP_PLL_312_CNTLMT0_1(1U); + pll_fclk = __APP_PLL_425_ENABLE | __APP_PLL_425_LRESETN | + __APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(0U) | + __APP_PLL_425_JITLMT0_1(3U) | + __APP_PLL_425_CNTLMT0_1(1U); + + /** + * For catapult, choose operational mode FC/FCoE + */ + if (ioc->fcmode) { + bfa_reg_write((rb + OP_MODE), 0); + bfa_reg_write((rb + ETH_MAC_SER_REG), + __APP_EMS_CMLCKSEL | + __APP_EMS_REFCKBUFEN2 | + __APP_EMS_CHANNEL_SEL); + } else { + ioc->pllinit = BFA_TRUE; + bfa_reg_write((rb + OP_MODE), __GLOBAL_FCOE_MODE); + bfa_reg_write((rb + ETH_MAC_SER_REG), + __APP_EMS_REFCKBUFEN1); + } + + bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_UNINIT); + bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_UNINIT); + + bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); + bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); + bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); + bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); + bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); + bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); + + bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, + __APP_PLL_312_LOGIC_SOFT_RESET); + bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, + __APP_PLL_312_BYPASS | + __APP_PLL_312_LOGIC_SOFT_RESET); + bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, + __APP_PLL_425_LOGIC_SOFT_RESET); + bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, + __APP_PLL_425_BYPASS | + __APP_PLL_425_LOGIC_SOFT_RESET); + bfa_os_udelay(2); + bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, + __APP_PLL_312_LOGIC_SOFT_RESET); + bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, + __APP_PLL_425_LOGIC_SOFT_RESET); + + bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, + pll_sclk | __APP_PLL_312_LOGIC_SOFT_RESET); + bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, + pll_fclk | __APP_PLL_425_LOGIC_SOFT_RESET); + + /** + * Wait for PLLs to lock. + */ + bfa_os_udelay(2000); + bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); + bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); + + bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk); + bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk); + + bfa_reg_write((rb + MBIST_CTL_REG), __EDRAM_BISTR_START); + bfa_os_udelay(1000); + r32 = bfa_reg_read((rb + MBIST_STAT_REG)); + bfa_trc(ioc, r32); + /* + * release semaphore. + */ + bfa_ioc_sem_release(ioc->ioc_regs.ioc_init_sem_reg); + + return BFA_STATUS_OK; +} + +/** + * Cleanup hw semaphore and usecnt registers + */ +static void +bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc) +{ + + if (ioc->cna) { + bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg); + bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, 0); + bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg); + } + + /* + * Read the hw sem reg to make sure that it is locked + * before we clear it. If it is not locked, writing 1 + * will lock it instead of clearing it. + */ + bfa_reg_read(ioc->ioc_regs.ioc_sem_reg); + bfa_ioc_hw_sem_release(ioc); +} diff --git a/drivers/scsi/bfa/include/bfa.h b/drivers/scsi/bfa/include/bfa.h index d4bc0d9fa42c..942ae64038c9 100644 --- a/drivers/scsi/bfa/include/bfa.h +++ b/drivers/scsi/bfa/include/bfa.h @@ -161,6 +161,7 @@ bfa_status_t bfa_iocfc_israttr_set(struct bfa_s *bfa, void bfa_iocfc_enable(struct bfa_s *bfa); void bfa_iocfc_disable(struct bfa_s *bfa); void bfa_ioc_auto_recover(bfa_boolean_t auto_recover); +void bfa_chip_reset(struct bfa_s *bfa); void bfa_cb_ioc_disable(void *bfad); void bfa_timer_tick(struct bfa_s *bfa); #define bfa_timer_start(_bfa, _timer, _timercb, _arg, _timeout) \ diff --git a/drivers/scsi/bfa/include/bfa_timer.h b/drivers/scsi/bfa/include/bfa_timer.h index e407103fa565..f71087448222 100644 --- a/drivers/scsi/bfa/include/bfa_timer.h +++ b/drivers/scsi/bfa/include/bfa_timer.h @@ -41,7 +41,7 @@ struct bfa_timer_mod_s { struct list_head timer_q; }; -#define BFA_TIMER_FREQ 500 /**< specified in millisecs */ +#define BFA_TIMER_FREQ 200 /**< specified in millisecs */ void bfa_timer_beat(struct bfa_timer_mod_s *mod); void bfa_timer_init(struct bfa_timer_mod_s *mod); diff --git a/drivers/scsi/bfa/include/bfi/bfi_cbreg.h b/drivers/scsi/bfa/include/bfi/bfi_cbreg.h index b3bb52b565b1..781cefafb659 100644 --- a/drivers/scsi/bfa/include/bfi/bfi_cbreg.h +++ b/drivers/scsi/bfa/include/bfi/bfi_cbreg.h @@ -177,7 +177,8 @@ #define __PSS_LMEM_INIT_EN 0x00000100 #define __PSS_LPU1_RESET 0x00000002 #define __PSS_LPU0_RESET 0x00000001 - +#define ERR_SET_REG 0x00018818 +#define __PSS_ERR_STATUS_SET 0x00000fff /* * These definitions are either in error/missing in spec. Its auto-generated diff --git a/drivers/scsi/bfa/include/bfi/bfi_ctreg.h b/drivers/scsi/bfa/include/bfi/bfi_ctreg.h index dd2992c38afb..d84ebae70cb4 100644 --- a/drivers/scsi/bfa/include/bfi/bfi_ctreg.h +++ b/drivers/scsi/bfa/include/bfi/bfi_ctreg.h @@ -430,6 +430,8 @@ enum { #define __PSS_LMEM_INIT_EN 0x00000100 #define __PSS_LPU1_RESET 0x00000002 #define __PSS_LPU0_RESET 0x00000001 +#define ERR_SET_REG 0x00018818 +#define __PSS_ERR_STATUS_SET 0x003fffff #define HQM_QSET0_RXQ_DRBL_P0 0x00038000 #define __RXQ0_ADD_VECTORS_P 0x80000000 #define __RXQ0_STOP_P 0x40000000 diff --git a/drivers/scsi/bfa/include/bfi/bfi_ioc.h b/drivers/scsi/bfa/include/bfi/bfi_ioc.h index 96ef05670659..a0158aac0024 100644 --- a/drivers/scsi/bfa/include/bfi/bfi_ioc.h +++ b/drivers/scsi/bfa/include/bfi/bfi_ioc.h @@ -123,7 +123,7 @@ enum bfi_ioc_state { BFI_IOC_DISABLING = 5, /* IOC is being disabled */ BFI_IOC_DISABLED = 6, /* IOC is disabled */ BFI_IOC_CFG_DISABLED = 7, /* IOC is being disabled;transient */ - BFI_IOC_HBFAIL = 8, /* IOC heart-beat failure */ + BFI_IOC_FAIL = 8, /* IOC heart-beat failure */ BFI_IOC_MEMTEST = 9, /* IOC is doing memtest */ }; diff --git a/drivers/scsi/bfa/include/cna/bfa_cna_trcmod.h b/drivers/scsi/bfa/include/cna/bfa_cna_trcmod.h index 43ba7064e81a..a75a1f3be315 100644 --- a/drivers/scsi/bfa/include/cna/bfa_cna_trcmod.h +++ b/drivers/scsi/bfa/include/cna/bfa_cna_trcmod.h @@ -31,6 +31,10 @@ enum { BFA_TRC_CNA_CEE = 1, BFA_TRC_CNA_PORT = 2, + BFA_TRC_CNA_IOC = 3, + BFA_TRC_CNA_DIAG = 4, + BFA_TRC_CNA_IOC_CB = 5, + BFA_TRC_CNA_IOC_CT = 6, }; #endif /* __BFA_CNA_TRCMOD_H__ */ -- cgit v1.2.3 From 8b651b4294e67789028982d18779a9ebe75c2b8a Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:34:44 -0800 Subject: [SCSI] bfa: Clear LL_HALT and PSS_ERR bit when IOC crashes. Clear LL_HALT and PSS_ERR bit in the interrupt status register on an IOC crash. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_intr.c | 35 ++++++++++++++++++++++++++++---- drivers/scsi/bfa/bfa_ioc.h | 1 + drivers/scsi/bfa/bfa_ioc_cb.c | 1 + drivers/scsi/bfa/bfa_ioc_ct.c | 1 + drivers/scsi/bfa/include/bfi/bfi_cbreg.h | 13 ++++++++++++ drivers/scsi/bfa/include/bfi/bfi_ctreg.h | 23 +++++++++++++++++++++ 6 files changed, 70 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_intr.c b/drivers/scsi/bfa/bfa_intr.c index ab463db11144..c42254613f73 100644 --- a/drivers/scsi/bfa/bfa_intr.c +++ b/drivers/scsi/bfa/bfa_intr.c @@ -197,17 +197,44 @@ bfa_msix_rspq(struct bfa_s *bfa, int rsp_qid) void bfa_msix_lpu_err(struct bfa_s *bfa, int vec) { - u32 intr; + u32 intr, curr_value; intr = bfa_reg_read(bfa->iocfc.bfa_regs.intr_status); if (intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1)) bfa_msix_lpu(bfa); - if (intr & (__HFN_INT_ERR_EMC | - __HFN_INT_ERR_LPU0 | __HFN_INT_ERR_LPU1 | - __HFN_INT_ERR_PSS | __HFN_INT_LL_HALT)) + intr &= (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | + __HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS | __HFN_INT_LL_HALT); + + if (intr) { + if (intr & __HFN_INT_LL_HALT) { + /** + * If LL_HALT bit is set then FW Init Halt LL Port + * Register needs to be cleared as well so Interrupt + * Status Register will be cleared. + */ + curr_value = bfa_reg_read(bfa->ioc.ioc_regs.ll_halt); + curr_value &= ~__FW_INIT_HALT_P; + bfa_reg_write(bfa->ioc.ioc_regs.ll_halt, curr_value); + } + + if (intr & __HFN_INT_ERR_PSS) { + /** + * ERR_PSS bit needs to be cleared as well in case + * interrups are shared so driver's interrupt handler is + * still called eventhough it is already masked out. + */ + curr_value = bfa_reg_read( + bfa->ioc.ioc_regs.pss_err_status_reg); + curr_value &= __PSS_ERR_STATUS_SET; + bfa_reg_write(bfa->ioc.ioc_regs.pss_err_status_reg, + curr_value); + } + + bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, intr); bfa_msix_errint(bfa, intr); + } } void diff --git a/drivers/scsi/bfa/bfa_ioc.h b/drivers/scsi/bfa/bfa_ioc.h index 1633a50187f7..853cc3136f0e 100644 --- a/drivers/scsi/bfa/bfa_ioc.h +++ b/drivers/scsi/bfa/bfa_ioc.h @@ -74,6 +74,7 @@ struct bfa_ioc_regs_s { bfa_os_addr_t lpu_mbox_cmd; bfa_os_addr_t lpu_mbox; bfa_os_addr_t pss_ctl_reg; + bfa_os_addr_t pss_err_status_reg; bfa_os_addr_t app_pll_fast_ctl_reg; bfa_os_addr_t app_pll_slow_ctl_reg; bfa_os_addr_t ioc_sem_reg; diff --git a/drivers/scsi/bfa/bfa_ioc_cb.c b/drivers/scsi/bfa/bfa_ioc_cb.c index d1d625bcd721..1fa052ef9ce0 100644 --- a/drivers/scsi/bfa/bfa_ioc_cb.c +++ b/drivers/scsi/bfa/bfa_ioc_cb.c @@ -145,6 +145,7 @@ bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc) * PSS control registers */ ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); + ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_400_CTL_REG); ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_212_CTL_REG); diff --git a/drivers/scsi/bfa/bfa_ioc_ct.c b/drivers/scsi/bfa/bfa_ioc_ct.c index 5de9c24efacf..0430edd2e011 100644 --- a/drivers/scsi/bfa/bfa_ioc_ct.c +++ b/drivers/scsi/bfa/bfa_ioc_ct.c @@ -237,6 +237,7 @@ bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc) * PSS control registers */ ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); + ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_425_CTL_REG); ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_312_CTL_REG); diff --git a/drivers/scsi/bfa/include/bfi/bfi_cbreg.h b/drivers/scsi/bfa/include/bfi/bfi_cbreg.h index 781cefafb659..a51ee61ddb19 100644 --- a/drivers/scsi/bfa/include/bfi/bfi_cbreg.h +++ b/drivers/scsi/bfa/include/bfi/bfi_cbreg.h @@ -177,6 +177,19 @@ #define __PSS_LMEM_INIT_EN 0x00000100 #define __PSS_LPU1_RESET 0x00000002 #define __PSS_LPU0_RESET 0x00000001 +#define PSS_ERR_STATUS_REG 0x00018810 +#define __PSS_LMEM1_CORR_ERR 0x00000800 +#define __PSS_LMEM0_CORR_ERR 0x00000400 +#define __PSS_LMEM1_UNCORR_ERR 0x00000200 +#define __PSS_LMEM0_UNCORR_ERR 0x00000100 +#define __PSS_BAL_PERR 0x00000080 +#define __PSS_DIP_IF_ERR 0x00000040 +#define __PSS_IOH_IF_ERR 0x00000020 +#define __PSS_TDS_IF_ERR 0x00000010 +#define __PSS_RDS_IF_ERR 0x00000008 +#define __PSS_SGM_IF_ERR 0x00000004 +#define __PSS_LPU1_RAM_ERR 0x00000002 +#define __PSS_LPU0_RAM_ERR 0x00000001 #define ERR_SET_REG 0x00018818 #define __PSS_ERR_STATUS_SET 0x00000fff diff --git a/drivers/scsi/bfa/include/bfi/bfi_ctreg.h b/drivers/scsi/bfa/include/bfi/bfi_ctreg.h index d84ebae70cb4..57a8497105af 100644 --- a/drivers/scsi/bfa/include/bfi/bfi_ctreg.h +++ b/drivers/scsi/bfa/include/bfi/bfi_ctreg.h @@ -430,6 +430,29 @@ enum { #define __PSS_LMEM_INIT_EN 0x00000100 #define __PSS_LPU1_RESET 0x00000002 #define __PSS_LPU0_RESET 0x00000001 +#define PSS_ERR_STATUS_REG 0x00018810 +#define __PSS_LPU1_TCM_READ_ERR 0x00200000 +#define __PSS_LPU0_TCM_READ_ERR 0x00100000 +#define __PSS_LMEM5_CORR_ERR 0x00080000 +#define __PSS_LMEM4_CORR_ERR 0x00040000 +#define __PSS_LMEM3_CORR_ERR 0x00020000 +#define __PSS_LMEM2_CORR_ERR 0x00010000 +#define __PSS_LMEM1_CORR_ERR 0x00008000 +#define __PSS_LMEM0_CORR_ERR 0x00004000 +#define __PSS_LMEM5_UNCORR_ERR 0x00002000 +#define __PSS_LMEM4_UNCORR_ERR 0x00001000 +#define __PSS_LMEM3_UNCORR_ERR 0x00000800 +#define __PSS_LMEM2_UNCORR_ERR 0x00000400 +#define __PSS_LMEM1_UNCORR_ERR 0x00000200 +#define __PSS_LMEM0_UNCORR_ERR 0x00000100 +#define __PSS_BAL_PERR 0x00000080 +#define __PSS_DIP_IF_ERR 0x00000040 +#define __PSS_IOH_IF_ERR 0x00000020 +#define __PSS_TDS_IF_ERR 0x00000010 +#define __PSS_RDS_IF_ERR 0x00000008 +#define __PSS_SGM_IF_ERR 0x00000004 +#define __PSS_LPU1_RAM_ERR 0x00000002 +#define __PSS_LPU0_RAM_ERR 0x00000001 #define ERR_SET_REG 0x00018818 #define __PSS_ERR_STATUS_SET 0x003fffff #define HQM_QSET0_RXQ_DRBL_P0 0x00038000 -- cgit v1.2.3 From e641de37e67953fa9ecad72608942481a5d66a1d Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:35:02 -0800 Subject: [SCSI] bfa: Replace bfa_assert() with bfa_sm_fault() Replace bfa_assert() with bfa_sm_fault() to get unhandled events for debugging. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_fcs_lport.c | 10 ++++----- drivers/scsi/bfa/bfa_ioim.c | 22 ++++++++++---------- drivers/scsi/bfa/bfa_itnim.c | 30 +++++++++++++-------------- drivers/scsi/bfa/bfa_lps.c | 12 +++++------ drivers/scsi/bfa/bfa_rport.c | 26 ++++++++++++------------ drivers/scsi/bfa/bfa_tskim.c | 14 ++++++------- drivers/scsi/bfa/fcpim.c | 16 +++++++-------- drivers/scsi/bfa/fdmi.c | 22 ++++++++++---------- drivers/scsi/bfa/ms.c | 22 ++++++++++---------- drivers/scsi/bfa/ns.c | 34 +++++++++++++++---------------- drivers/scsi/bfa/rport.c | 44 ++++++++++++++++++++-------------------- drivers/scsi/bfa/rport_ftrs.c | 12 +++++------ drivers/scsi/bfa/scn.c | 10 ++++----- drivers/scsi/bfa/vport.c | 18 ++++++++-------- 14 files changed, 146 insertions(+), 146 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_fcs_lport.c b/drivers/scsi/bfa/bfa_fcs_lport.c index 3d62e456950b..960ae1a7bcd0 100644 --- a/drivers/scsi/bfa/bfa_fcs_lport.c +++ b/drivers/scsi/bfa/bfa_fcs_lport.c @@ -114,7 +114,7 @@ bfa_fcs_port_sm_uninit(struct bfa_fcs_port_s *port, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -136,7 +136,7 @@ bfa_fcs_port_sm_init(struct bfa_fcs_port_s *port, enum bfa_fcs_port_event event) break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -176,7 +176,7 @@ bfa_fcs_port_sm_online(struct bfa_fcs_port_s *port, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -214,7 +214,7 @@ bfa_fcs_port_sm_offline(struct bfa_fcs_port_s *port, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -234,7 +234,7 @@ bfa_fcs_port_sm_deleting(struct bfa_fcs_port_s *port, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } diff --git a/drivers/scsi/bfa/bfa_ioim.c b/drivers/scsi/bfa/bfa_ioim.c index f81d359b7089..5b107abe46e5 100644 --- a/drivers/scsi/bfa/bfa_ioim.c +++ b/drivers/scsi/bfa/bfa_ioim.c @@ -149,7 +149,7 @@ bfa_ioim_sm_uninit(struct bfa_ioim_s *ioim, enum bfa_ioim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ioim->bfa, event); } } @@ -194,7 +194,7 @@ bfa_ioim_sm_sgalloc(struct bfa_ioim_s *ioim, enum bfa_ioim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ioim->bfa, event); } } @@ -259,7 +259,7 @@ bfa_ioim_sm_active(struct bfa_ioim_s *ioim, enum bfa_ioim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ioim->bfa, event); } } @@ -317,7 +317,7 @@ bfa_ioim_sm_abort(struct bfa_ioim_s *ioim, enum bfa_ioim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ioim->bfa, event); } } @@ -377,7 +377,7 @@ bfa_ioim_sm_cleanup(struct bfa_ioim_s *ioim, enum bfa_ioim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ioim->bfa, event); } } @@ -419,7 +419,7 @@ bfa_ioim_sm_qfull(struct bfa_ioim_s *ioim, enum bfa_ioim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ioim->bfa, event); } } @@ -467,7 +467,7 @@ bfa_ioim_sm_abort_qfull(struct bfa_ioim_s *ioim, enum bfa_ioim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ioim->bfa, event); } } @@ -516,7 +516,7 @@ bfa_ioim_sm_cleanup_qfull(struct bfa_ioim_s *ioim, enum bfa_ioim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ioim->bfa, event); } } @@ -544,7 +544,7 @@ bfa_ioim_sm_hcb(struct bfa_ioim_s *ioim, enum bfa_ioim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ioim->bfa, event); } } @@ -577,7 +577,7 @@ bfa_ioim_sm_hcb_free(struct bfa_ioim_s *ioim, enum bfa_ioim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ioim->bfa, event); } } @@ -605,7 +605,7 @@ bfa_ioim_sm_resfree(struct bfa_ioim_s *ioim, enum bfa_ioim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ioim->bfa, event); } } diff --git a/drivers/scsi/bfa/bfa_itnim.c b/drivers/scsi/bfa/bfa_itnim.c index eabf7d38bd09..a914ff255135 100644 --- a/drivers/scsi/bfa/bfa_itnim.c +++ b/drivers/scsi/bfa/bfa_itnim.c @@ -144,7 +144,7 @@ bfa_itnim_sm_uninit(struct bfa_itnim_s *itnim, enum bfa_itnim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -175,7 +175,7 @@ bfa_itnim_sm_created(struct bfa_itnim_s *itnim, enum bfa_itnim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -212,7 +212,7 @@ bfa_itnim_sm_fwcreate(struct bfa_itnim_s *itnim, enum bfa_itnim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -247,7 +247,7 @@ bfa_itnim_sm_fwcreate_qfull(struct bfa_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -275,7 +275,7 @@ bfa_itnim_sm_delete_pending(struct bfa_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -317,7 +317,7 @@ bfa_itnim_sm_online(struct bfa_itnim_s *itnim, enum bfa_itnim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -348,7 +348,7 @@ bfa_itnim_sm_sler(struct bfa_itnim_s *itnim, enum bfa_itnim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -385,7 +385,7 @@ bfa_itnim_sm_cleanup_offline(struct bfa_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -413,7 +413,7 @@ bfa_itnim_sm_cleanup_delete(struct bfa_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -442,7 +442,7 @@ bfa_itnim_sm_fwdelete(struct bfa_itnim_s *itnim, enum bfa_itnim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -470,7 +470,7 @@ bfa_itnim_sm_fwdelete_qfull(struct bfa_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -502,7 +502,7 @@ bfa_itnim_sm_offline(struct bfa_itnim_s *itnim, enum bfa_itnim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -538,7 +538,7 @@ bfa_itnim_sm_iocdisable(struct bfa_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -559,7 +559,7 @@ bfa_itnim_sm_deleting(struct bfa_itnim_s *itnim, enum bfa_itnim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } @@ -583,7 +583,7 @@ bfa_itnim_sm_deleting_qfull(struct bfa_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->bfa, event); } } diff --git a/drivers/scsi/bfa/bfa_lps.c b/drivers/scsi/bfa/bfa_lps.c index 66b9b15f4294..4c98bdab3119 100644 --- a/drivers/scsi/bfa/bfa_lps.c +++ b/drivers/scsi/bfa/bfa_lps.c @@ -121,7 +121,7 @@ bfa_lps_sm_init(struct bfa_lps_s *lps, enum bfa_lps_event event) break; default: - bfa_assert(0); + bfa_sm_fault(lps->bfa, event); } } @@ -148,7 +148,7 @@ bfa_lps_sm_login(struct bfa_lps_s *lps, enum bfa_lps_event event) break; default: - bfa_assert(0); + bfa_sm_fault(lps->bfa, event); } } @@ -180,7 +180,7 @@ bfa_lps_sm_loginwait(struct bfa_lps_s *lps, enum bfa_lps_event event) break; default: - bfa_assert(0); + bfa_sm_fault(lps->bfa, event); } } @@ -219,7 +219,7 @@ bfa_lps_sm_online(struct bfa_lps_s *lps, enum bfa_lps_event event) break; default: - bfa_assert(0); + bfa_sm_fault(lps->bfa, event); } } @@ -243,7 +243,7 @@ bfa_lps_sm_logout(struct bfa_lps_s *lps, enum bfa_lps_event event) break; default: - bfa_assert(0); + bfa_sm_fault(lps->bfa, event); } } @@ -268,7 +268,7 @@ bfa_lps_sm_logowait(struct bfa_lps_s *lps, enum bfa_lps_event event) break; default: - bfa_assert(0); + bfa_sm_fault(lps->bfa, event); } } diff --git a/drivers/scsi/bfa/bfa_rport.c b/drivers/scsi/bfa/bfa_rport.c index 3e1990a74258..7c509fa244e4 100644 --- a/drivers/scsi/bfa/bfa_rport.c +++ b/drivers/scsi/bfa/bfa_rport.c @@ -114,7 +114,7 @@ bfa_rport_sm_uninit(struct bfa_rport_s *rp, enum bfa_rport_event event) default: bfa_stats(rp, sm_un_unexp); - bfa_assert(0); + bfa_sm_fault(rp->bfa, event); } } @@ -146,7 +146,7 @@ bfa_rport_sm_created(struct bfa_rport_s *rp, enum bfa_rport_event event) default: bfa_stats(rp, sm_cr_unexp); - bfa_assert(0); + bfa_sm_fault(rp->bfa, event); } } @@ -183,7 +183,7 @@ bfa_rport_sm_fwcreate(struct bfa_rport_s *rp, enum bfa_rport_event event) default: bfa_stats(rp, sm_fwc_unexp); - bfa_assert(0); + bfa_sm_fault(rp->bfa, event); } } @@ -224,7 +224,7 @@ bfa_rport_sm_fwcreate_qfull(struct bfa_rport_s *rp, enum bfa_rport_event event) default: bfa_stats(rp, sm_fwc_unexp); - bfa_assert(0); + bfa_sm_fault(rp->bfa, event); } } @@ -296,7 +296,7 @@ bfa_rport_sm_online(struct bfa_rport_s *rp, enum bfa_rport_event event) default: bfa_stats(rp, sm_on_unexp); - bfa_assert(0); + bfa_sm_fault(rp->bfa, event); } } @@ -329,7 +329,7 @@ bfa_rport_sm_fwdelete(struct bfa_rport_s *rp, enum bfa_rport_event event) default: bfa_stats(rp, sm_fwd_unexp); - bfa_assert(0); + bfa_sm_fault(rp->bfa, event); } } @@ -359,7 +359,7 @@ bfa_rport_sm_fwdelete_qfull(struct bfa_rport_s *rp, enum bfa_rport_event event) default: bfa_stats(rp, sm_fwd_unexp); - bfa_assert(0); + bfa_sm_fault(rp->bfa, event); } } @@ -394,7 +394,7 @@ bfa_rport_sm_offline(struct bfa_rport_s *rp, enum bfa_rport_event event) default: bfa_stats(rp, sm_off_unexp); - bfa_assert(0); + bfa_sm_fault(rp->bfa, event); } } @@ -421,7 +421,7 @@ bfa_rport_sm_deleting(struct bfa_rport_s *rp, enum bfa_rport_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rp->bfa, event); } } @@ -446,7 +446,7 @@ bfa_rport_sm_deleting_qfull(struct bfa_rport_s *rp, enum bfa_rport_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rp->bfa, event); } } @@ -477,7 +477,7 @@ bfa_rport_sm_delete_pending(struct bfa_rport_s *rp, default: bfa_stats(rp, sm_delp_unexp); - bfa_assert(0); + bfa_sm_fault(rp->bfa, event); } } @@ -512,7 +512,7 @@ bfa_rport_sm_offline_pending(struct bfa_rport_s *rp, default: bfa_stats(rp, sm_offp_unexp); - bfa_assert(0); + bfa_sm_fault(rp->bfa, event); } } @@ -550,7 +550,7 @@ bfa_rport_sm_iocdisable(struct bfa_rport_s *rp, enum bfa_rport_event event) default: bfa_stats(rp, sm_iocd_unexp); - bfa_assert(0); + bfa_sm_fault(rp->bfa, event); } } diff --git a/drivers/scsi/bfa/bfa_tskim.c b/drivers/scsi/bfa/bfa_tskim.c index ff7a4dc0bf3c..ad9aaaedd3f1 100644 --- a/drivers/scsi/bfa/bfa_tskim.c +++ b/drivers/scsi/bfa/bfa_tskim.c @@ -110,7 +110,7 @@ bfa_tskim_sm_uninit(struct bfa_tskim_s *tskim, enum bfa_tskim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(tskim->bfa, event); } } @@ -146,7 +146,7 @@ bfa_tskim_sm_active(struct bfa_tskim_s *tskim, enum bfa_tskim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(tskim->bfa, event); } } @@ -178,7 +178,7 @@ bfa_tskim_sm_cleanup(struct bfa_tskim_s *tskim, enum bfa_tskim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(tskim->bfa, event); } } @@ -207,7 +207,7 @@ bfa_tskim_sm_iocleanup(struct bfa_tskim_s *tskim, enum bfa_tskim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(tskim->bfa, event); } } @@ -242,7 +242,7 @@ bfa_tskim_sm_qfull(struct bfa_tskim_s *tskim, enum bfa_tskim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(tskim->bfa, event); } } @@ -277,7 +277,7 @@ bfa_tskim_sm_cleanup_qfull(struct bfa_tskim_s *tskim, break; default: - bfa_assert(0); + bfa_sm_fault(tskim->bfa, event); } } @@ -303,7 +303,7 @@ bfa_tskim_sm_hcb(struct bfa_tskim_s *tskim, enum bfa_tskim_event event) break; default: - bfa_assert(0); + bfa_sm_fault(tskim->bfa, event); } } diff --git a/drivers/scsi/bfa/fcpim.c b/drivers/scsi/bfa/fcpim.c index 06f8a46d1977..71d23d19bc9d 100644 --- a/drivers/scsi/bfa/fcpim.c +++ b/drivers/scsi/bfa/fcpim.c @@ -126,7 +126,7 @@ bfa_fcs_itnim_sm_offline(struct bfa_fcs_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->fcs, event); } } @@ -161,7 +161,7 @@ bfa_fcs_itnim_sm_prli_send(struct bfa_fcs_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->fcs, event); } } @@ -205,7 +205,7 @@ bfa_fcs_itnim_sm_prli(struct bfa_fcs_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->fcs, event); } } @@ -240,7 +240,7 @@ bfa_fcs_itnim_sm_prli_retry(struct bfa_fcs_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->fcs, event); } } @@ -270,7 +270,7 @@ bfa_fcs_itnim_sm_hcb_online(struct bfa_fcs_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->fcs, event); } } @@ -298,7 +298,7 @@ bfa_fcs_itnim_sm_online(struct bfa_fcs_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->fcs, event); } } @@ -321,7 +321,7 @@ bfa_fcs_itnim_sm_hcb_offline(struct bfa_fcs_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->fcs, event); } } @@ -354,7 +354,7 @@ bfa_fcs_itnim_sm_initiator(struct bfa_fcs_itnim_s *itnim, break; default: - bfa_assert(0); + bfa_sm_fault(itnim->fcs, event); } } diff --git a/drivers/scsi/bfa/fdmi.c b/drivers/scsi/bfa/fdmi.c index d76d9220b6e6..e8120868701b 100644 --- a/drivers/scsi/bfa/fdmi.c +++ b/drivers/scsi/bfa/fdmi.c @@ -158,7 +158,7 @@ bfa_fcs_port_fdmi_sm_offline(struct bfa_fcs_port_fdmi_s *fdmi, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -183,7 +183,7 @@ bfa_fcs_port_fdmi_sm_sending_rhba(struct bfa_fcs_port_fdmi_s *fdmi, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -230,7 +230,7 @@ bfa_fcs_port_fdmi_sm_rhba(struct bfa_fcs_port_fdmi_s *fdmi, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -258,7 +258,7 @@ bfa_fcs_port_fdmi_sm_rhba_retry(struct bfa_fcs_port_fdmi_s *fdmi, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -286,7 +286,7 @@ bfa_fcs_port_fdmi_sm_sending_rprt(struct bfa_fcs_port_fdmi_s *fdmi, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -331,7 +331,7 @@ bfa_fcs_port_fdmi_sm_rprt(struct bfa_fcs_port_fdmi_s *fdmi, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -359,7 +359,7 @@ bfa_fcs_port_fdmi_sm_rprt_retry(struct bfa_fcs_port_fdmi_s *fdmi, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -387,7 +387,7 @@ bfa_fcs_port_fdmi_sm_sending_rpa(struct bfa_fcs_port_fdmi_s *fdmi, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -431,7 +431,7 @@ bfa_fcs_port_fdmi_sm_rpa(struct bfa_fcs_port_fdmi_s *fdmi, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -459,7 +459,7 @@ bfa_fcs_port_fdmi_sm_rpa_retry(struct bfa_fcs_port_fdmi_s *fdmi, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } @@ -478,7 +478,7 @@ bfa_fcs_port_fdmi_sm_online(struct bfa_fcs_port_fdmi_s *fdmi, break; default: - bfa_assert(0); + bfa_sm_fault(port->fcs, event); } } diff --git a/drivers/scsi/bfa/ms.c b/drivers/scsi/bfa/ms.c index c96b3ca007ae..f0275a409fd2 100644 --- a/drivers/scsi/bfa/ms.c +++ b/drivers/scsi/bfa/ms.c @@ -118,7 +118,7 @@ bfa_fcs_port_ms_sm_offline(struct bfa_fcs_port_ms_s *ms, break; default: - bfa_assert(0); + bfa_sm_fault(ms->port->fcs, event); } } @@ -141,7 +141,7 @@ bfa_fcs_port_ms_sm_plogi_sending(struct bfa_fcs_port_ms_s *ms, break; default: - bfa_assert(0); + bfa_sm_fault(ms->port->fcs, event); } } @@ -190,7 +190,7 @@ bfa_fcs_port_ms_sm_plogi(struct bfa_fcs_port_ms_s *ms, enum port_ms_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ms->port->fcs, event); } } @@ -216,7 +216,7 @@ bfa_fcs_port_ms_sm_plogi_retry(struct bfa_fcs_port_ms_s *ms, break; default: - bfa_assert(0); + bfa_sm_fault(ms->port->fcs, event); } } @@ -243,7 +243,7 @@ bfa_fcs_port_ms_sm_online(struct bfa_fcs_port_ms_s *ms, break; default: - bfa_assert(0); + bfa_sm_fault(ms->port->fcs, event); } } @@ -266,7 +266,7 @@ bfa_fcs_port_ms_sm_gmal_sending(struct bfa_fcs_port_ms_s *ms, break; default: - bfa_assert(0); + bfa_sm_fault(ms->port->fcs, event); } } @@ -304,7 +304,7 @@ bfa_fcs_port_ms_sm_gmal(struct bfa_fcs_port_ms_s *ms, enum port_ms_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ms->port->fcs, event); } } @@ -330,7 +330,7 @@ bfa_fcs_port_ms_sm_gmal_retry(struct bfa_fcs_port_ms_s *ms, break; default: - bfa_assert(0); + bfa_sm_fault(ms->port->fcs, event); } } @@ -466,7 +466,7 @@ bfa_fcs_port_ms_sm_gfn_sending(struct bfa_fcs_port_ms_s *ms, break; default: - bfa_assert(0); + bfa_sm_fault(ms->port->fcs, event); } } @@ -502,7 +502,7 @@ bfa_fcs_port_ms_sm_gfn(struct bfa_fcs_port_ms_s *ms, enum port_ms_event event) break; default: - bfa_assert(0); + bfa_sm_fault(ms->port->fcs, event); } } @@ -528,7 +528,7 @@ bfa_fcs_port_ms_sm_gfn_retry(struct bfa_fcs_port_ms_s *ms, break; default: - bfa_assert(0); + bfa_sm_fault(ms->port->fcs, event); } } diff --git a/drivers/scsi/bfa/ns.c b/drivers/scsi/bfa/ns.c index 2f8b880060bb..6de06a557e2d 100644 --- a/drivers/scsi/bfa/ns.c +++ b/drivers/scsi/bfa/ns.c @@ -164,7 +164,7 @@ bfa_fcs_port_ns_sm_offline(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -187,7 +187,7 @@ bfa_fcs_port_ns_sm_plogi_sending(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -221,7 +221,7 @@ bfa_fcs_port_ns_sm_plogi(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -247,7 +247,7 @@ bfa_fcs_port_ns_sm_plogi_retry(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -270,7 +270,7 @@ bfa_fcs_port_ns_sm_sending_rspn_id(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -304,7 +304,7 @@ bfa_fcs_port_ns_sm_rspn_id(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -330,7 +330,7 @@ bfa_fcs_port_ns_sm_rspn_id_retry(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -353,7 +353,7 @@ bfa_fcs_port_ns_sm_sending_rft_id(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -390,7 +390,7 @@ bfa_fcs_port_ns_sm_rft_id(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -413,7 +413,7 @@ bfa_fcs_port_ns_sm_rft_id_retry(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -436,7 +436,7 @@ bfa_fcs_port_ns_sm_sending_rff_id(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -494,7 +494,7 @@ bfa_fcs_port_ns_sm_rff_id(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -517,7 +517,7 @@ bfa_fcs_port_ns_sm_rff_id_retry(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } static void @@ -539,7 +539,7 @@ bfa_fcs_port_ns_sm_sending_gid_ft(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -575,7 +575,7 @@ bfa_fcs_port_ns_sm_gid_ft(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -598,7 +598,7 @@ bfa_fcs_port_ns_sm_gid_ft_retry(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } @@ -626,7 +626,7 @@ bfa_fcs_port_ns_sm_online(struct bfa_fcs_port_ns_s *ns, break; default: - bfa_assert(0); + bfa_sm_fault(ns->port->fcs, event); } } diff --git a/drivers/scsi/bfa/rport.c b/drivers/scsi/bfa/rport.c index df714dcdf031..32cf180ec791 100644 --- a/drivers/scsi/bfa/rport.c +++ b/drivers/scsi/bfa/rport.c @@ -224,7 +224,7 @@ bfa_fcs_rport_sm_uninit(struct bfa_fcs_rport_s *rport, enum rport_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -276,7 +276,7 @@ bfa_fcs_rport_sm_plogi_sending(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -332,7 +332,7 @@ bfa_fcs_rport_sm_plogiacc_sending(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -406,7 +406,7 @@ bfa_fcs_rport_sm_plogi_retry(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -481,7 +481,7 @@ bfa_fcs_rport_sm_plogi(struct bfa_fcs_rport_s *rport, enum rport_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -534,7 +534,7 @@ bfa_fcs_rport_sm_hal_online(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -589,7 +589,7 @@ bfa_fcs_rport_sm_online(struct bfa_fcs_rport_s *rport, enum rport_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -646,7 +646,7 @@ bfa_fcs_rport_sm_nsquery_sending(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -704,7 +704,7 @@ bfa_fcs_rport_sm_nsquery(struct bfa_fcs_rport_s *rport, enum rport_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -754,7 +754,7 @@ bfa_fcs_rport_sm_adisc_sending(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -816,7 +816,7 @@ bfa_fcs_rport_sm_adisc(struct bfa_fcs_rport_s *rport, enum rport_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -846,7 +846,7 @@ bfa_fcs_rport_sm_fc4_logorcv(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -869,7 +869,7 @@ bfa_fcs_rport_sm_fc4_logosend(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -905,7 +905,7 @@ bfa_fcs_rport_sm_fc4_offline(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -951,7 +951,7 @@ bfa_fcs_rport_sm_hcb_offline(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -1011,7 +1011,7 @@ bfa_fcs_rport_sm_hcb_logorcv(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -1038,7 +1038,7 @@ bfa_fcs_rport_sm_hcb_logosend(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -1073,7 +1073,7 @@ bfa_fcs_rport_sm_logo_sending(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -1132,7 +1132,7 @@ bfa_fcs_rport_sm_offline(struct bfa_fcs_rport_s *rport, enum rport_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -1188,7 +1188,7 @@ bfa_fcs_rport_sm_nsdisc_sending(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -1249,7 +1249,7 @@ bfa_fcs_rport_sm_nsdisc_retry(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -1334,7 +1334,7 @@ bfa_fcs_rport_sm_nsdisc_sent(struct bfa_fcs_rport_s *rport, break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } diff --git a/drivers/scsi/bfa/rport_ftrs.c b/drivers/scsi/bfa/rport_ftrs.c index e1932c885ac2..ae7bba67ae2a 100644 --- a/drivers/scsi/bfa/rport_ftrs.c +++ b/drivers/scsi/bfa/rport_ftrs.c @@ -91,7 +91,7 @@ bfa_fcs_rpf_sm_uninit(struct bfa_fcs_rpf_s *rpf, enum rpf_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -114,7 +114,7 @@ bfa_fcs_rpf_sm_rpsc_sending(struct bfa_fcs_rpf_s *rpf, enum rpf_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -160,7 +160,7 @@ bfa_fcs_rpf_sm_rpsc(struct bfa_fcs_rpf_s *rpf, enum rpf_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -186,7 +186,7 @@ bfa_fcs_rpf_sm_rpsc_retry(struct bfa_fcs_rpf_s *rpf, enum rpf_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -206,7 +206,7 @@ bfa_fcs_rpf_sm_online(struct bfa_fcs_rpf_s *rpf, enum rpf_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } @@ -229,7 +229,7 @@ bfa_fcs_rpf_sm_offline(struct bfa_fcs_rpf_s *rpf, enum rpf_event event) break; default: - bfa_assert(0); + bfa_sm_fault(rport->fcs, event); } } /** diff --git a/drivers/scsi/bfa/scn.c b/drivers/scsi/bfa/scn.c index bd4771ff62c8..8fe09ba88a91 100644 --- a/drivers/scsi/bfa/scn.c +++ b/drivers/scsi/bfa/scn.c @@ -90,7 +90,7 @@ bfa_fcs_port_scn_sm_offline(struct bfa_fcs_port_scn_s *scn, break; default: - bfa_assert(0); + bfa_sm_fault(scn->port->fcs, event); } } @@ -109,7 +109,7 @@ bfa_fcs_port_scn_sm_sending_scr(struct bfa_fcs_port_scn_s *scn, break; default: - bfa_assert(0); + bfa_sm_fault(scn->port->fcs, event); } } @@ -137,7 +137,7 @@ bfa_fcs_port_scn_sm_scr(struct bfa_fcs_port_scn_s *scn, break; default: - bfa_assert(0); + bfa_sm_fault(scn->port->fcs, event); } } @@ -157,7 +157,7 @@ bfa_fcs_port_scn_sm_scr_retry(struct bfa_fcs_port_scn_s *scn, break; default: - bfa_assert(0); + bfa_sm_fault(scn->port->fcs, event); } } @@ -171,7 +171,7 @@ bfa_fcs_port_scn_sm_online(struct bfa_fcs_port_scn_s *scn, break; default: - bfa_assert(0); + bfa_sm_fault(scn->port->fcs, event); } } diff --git a/drivers/scsi/bfa/vport.c b/drivers/scsi/bfa/vport.c index 13f737139379..14fb7ac2bfbc 100644 --- a/drivers/scsi/bfa/vport.c +++ b/drivers/scsi/bfa/vport.c @@ -122,7 +122,7 @@ bfa_fcs_vport_sm_uninit(struct bfa_fcs_vport_s *vport, break; default: - bfa_assert(0); + bfa_sm_fault(__vport_fcs(vport), event); } } @@ -165,7 +165,7 @@ bfa_fcs_vport_sm_created(struct bfa_fcs_vport_s *vport, break; default: - bfa_assert(0); + bfa_sm_fault(__vport_fcs(vport), event); } } @@ -202,7 +202,7 @@ bfa_fcs_vport_sm_offline(struct bfa_fcs_vport_s *vport, break; default: - bfa_assert(0); + bfa_sm_fault(__vport_fcs(vport), event); } } @@ -249,7 +249,7 @@ bfa_fcs_vport_sm_fdisc(struct bfa_fcs_vport_s *vport, break; default: - bfa_assert(0); + bfa_sm_fault(__vport_fcs(vport), event); } } @@ -283,7 +283,7 @@ bfa_fcs_vport_sm_fdisc_retry(struct bfa_fcs_vport_s *vport, break; default: - bfa_assert(0); + bfa_sm_fault(__vport_fcs(vport), event); } } @@ -310,7 +310,7 @@ bfa_fcs_vport_sm_online(struct bfa_fcs_vport_s *vport, break; default: - bfa_assert(0); + bfa_sm_fault(__vport_fcs(vport), event); } } @@ -339,7 +339,7 @@ bfa_fcs_vport_sm_deleting(struct bfa_fcs_vport_s *vport, break; default: - bfa_assert(0); + bfa_sm_fault(__vport_fcs(vport), event); } } @@ -387,7 +387,7 @@ bfa_fcs_vport_sm_cleanup(struct bfa_fcs_vport_s *vport, break; default: - bfa_assert(0); + bfa_sm_fault(__vport_fcs(vport), event); } } @@ -419,7 +419,7 @@ bfa_fcs_vport_sm_logo(struct bfa_fcs_vport_s *vport, break; default: - bfa_assert(0); + bfa_sm_fault(__vport_fcs(vport), event); } } -- cgit v1.2.3 From 72041ed8fc8ed92c11af90949bab7b08f3e34fd3 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:35:16 -0800 Subject: [SCSI] bfa: RPORT state machine: direct attach mode fix. Make sure that in direct attach mode, we do not query the name server after a target is marked offline. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/rport.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/rport.c b/drivers/scsi/bfa/rport.c index 32cf180ec791..80592e352226 100644 --- a/drivers/scsi/bfa/rport.c +++ b/drivers/scsi/bfa/rport.c @@ -925,10 +925,17 @@ bfa_fcs_rport_sm_hcb_offline(struct bfa_fcs_rport_s *rport, case RPSM_EVENT_HCB_OFFLINE: case RPSM_EVENT_ADDRESS_CHANGE: if (bfa_fcs_port_is_online(rport->port)) { - bfa_sm_set_state(rport, - bfa_fcs_rport_sm_nsdisc_sending); - rport->ns_retries = 0; - bfa_fcs_rport_send_gidpn(rport, NULL); + if (bfa_fcs_fabric_is_switched(rport->port->fabric)) { + bfa_sm_set_state(rport, + bfa_fcs_rport_sm_nsdisc_sending); + rport->ns_retries = 0; + bfa_fcs_rport_send_gidpn(rport, NULL); + } else { + bfa_sm_set_state(rport, + bfa_fcs_rport_sm_plogi_sending); + rport->plogi_retries = 0; + bfa_fcs_rport_send_plogi(rport, NULL); + } } else { rport->pid = 0; bfa_sm_set_state(rport, bfa_fcs_rport_sm_offline); -- cgit v1.2.3 From 86e32dabbad0d860b2be3c30a33c10a134d4ccf1 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:35:33 -0800 Subject: [SCSI] bfa: Fix to copy fpma MAC when requested by user space application. Copy fpma MAC when requested by user space application. Added FPMA mac address to the lport attributes structure. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_fcs_lport.c | 7 ++++++- drivers/scsi/bfa/bfa_lps.c | 12 ++++++++++-- drivers/scsi/bfa/include/bfa_svc.h | 1 + drivers/scsi/bfa/include/defs/bfa_defs_port.h | 4 +++- 4 files changed, 20 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_fcs_lport.c b/drivers/scsi/bfa/bfa_fcs_lport.c index 960ae1a7bcd0..7bb182dcbd7d 100644 --- a/drivers/scsi/bfa/bfa_fcs_lport.c +++ b/drivers/scsi/bfa/bfa_fcs_lport.c @@ -936,8 +936,13 @@ bfa_fcs_port_get_attr(struct bfa_fcs_port_s *port, bfa_fcs_port_get_fabric_ipaddr(port), BFA_FCS_FABRIC_IPADDR_SZ); - if (port->vport != NULL) + if (port->vport != NULL) { port_attr->port_type = BFA_PPORT_TYPE_VPORT; + port_attr->fpma_mac = + bfa_lps_get_lp_mac(port->vport->lps); + } else + port_attr->fpma_mac = + bfa_lps_get_lp_mac(port->fabric->lps); } else { port_attr->port_type = BFA_PPORT_TYPE_UNKNOWN; diff --git a/drivers/scsi/bfa/bfa_lps.c b/drivers/scsi/bfa/bfa_lps.c index 4c98bdab3119..730616f6e671 100644 --- a/drivers/scsi/bfa/bfa_lps.c +++ b/drivers/scsi/bfa/bfa_lps.c @@ -613,9 +613,9 @@ bfa_lps_get_max_vport(struct bfa_s *bfa) bfa_get_attr(bfa, &ioc_attr); if (ioc_attr.pci_attr.device_id == BFA_PCI_DEVICE_ID_CT) - return (BFA_LPS_MAX_VPORTS_SUPP_CT); + return BFA_LPS_MAX_VPORTS_SUPP_CT; else - return (BFA_LPS_MAX_VPORTS_SUPP_CB); + return BFA_LPS_MAX_VPORTS_SUPP_CB; } /** @@ -837,6 +837,14 @@ bfa_lps_get_lsrjt_expl(struct bfa_lps_s *lps) return lps->lsrjt_expl; } +/** + * Return fpma/spma MAC for lport + */ +struct mac_s +bfa_lps_get_lp_mac(struct bfa_lps_s *lps) +{ + return lps->lp_mac; +} /** * LPS firmware message class handler. diff --git a/drivers/scsi/bfa/include/bfa_svc.h b/drivers/scsi/bfa/include/bfa_svc.h index 0d7ed4d963a7..71ffb75a71ca 100644 --- a/drivers/scsi/bfa/include/bfa_svc.h +++ b/drivers/scsi/bfa/include/bfa_svc.h @@ -316,6 +316,7 @@ wwn_t bfa_lps_get_peer_pwwn(struct bfa_lps_s *lps); wwn_t bfa_lps_get_peer_nwwn(struct bfa_lps_s *lps); u8 bfa_lps_get_lsrjt_rsn(struct bfa_lps_s *lps); u8 bfa_lps_get_lsrjt_expl(struct bfa_lps_s *lps); +mac_t bfa_lps_get_lp_mac(struct bfa_lps_s *lps); void bfa_cb_lps_flogi_comp(void *bfad, void *uarg, bfa_status_t status); void bfa_cb_lps_flogo_comp(void *bfad, void *uarg); void bfa_cb_lps_fdisc_comp(void *bfad, void *uarg, bfa_status_t status); diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_port.h b/drivers/scsi/bfa/include/defs/bfa_defs_port.h index de0696c81bc4..1c74a8b94aad 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_port.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_port.h @@ -185,6 +185,8 @@ struct bfa_port_attr_s { wwn_t fabric_name; /* attached switch's nwwn */ u8 fabric_ip_addr[BFA_FCS_FABRIC_IPADDR_SZ]; /* attached * fabric's ip addr */ + struct mac_s fpma_mac; /* Lport's FPMA Mac address */ + u16 authfail; /* auth failed state */ }; /** @@ -235,7 +237,7 @@ struct bfa_port_aen_data_s { enum bfa_ioc_type_e ioc_type; wwn_t pwwn; /* WWN of the physical port */ wwn_t fwwn; /* WWN of the fabric port */ - mac_t mac; /* MAC addres of the ethernet port, + mac_t mac; /* MAC address of the ethernet port, * applicable to CNA port only */ int phy_port_num; /*! For SFP related events */ enum bfa_port_aen_sfp_pom level; /* Only transitions will -- cgit v1.2.3 From 7af074dc9d343f69bab4bfd699e6d7ba09915fd9 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:35:45 -0800 Subject: [SCSI] bfa: PCI VPD, FIP and include file changes. Changed PCI VPD to incorporate specific OEM vendors. Added FCoE specific interrupt latency and delay params. Added some variables needed by FIP 2.0. Added some new logging and tracing definitions. Added reserved members to make the structures (IOC, IOCFC) 64bit aligned. Changed the module identifiers, as some files were moved. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_ioc.c | 4 +- drivers/scsi/bfa/bfa_trcmod_priv.h | 62 +++++++------ drivers/scsi/bfa/include/defs/bfa_defs_cee.h | 14 ++- drivers/scsi/bfa/include/defs/bfa_defs_ioc.h | 1 + drivers/scsi/bfa/include/defs/bfa_defs_iocfc.h | 11 ++- drivers/scsi/bfa/include/defs/bfa_defs_mfg.h | 111 +++++++++++++++++++++--- drivers/scsi/bfa/include/defs/bfa_defs_status.h | 12 ++- drivers/scsi/bfa/include/log/bfa_log_hal.h | 6 ++ drivers/scsi/bfa/include/log/bfa_log_linux.h | 16 ++++ 9 files changed, 178 insertions(+), 59 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_ioc.c b/drivers/scsi/bfa/bfa_ioc.c index a5f9745315b1..8a6361cf2439 100644 --- a/drivers/scsi/bfa/bfa_ioc.c +++ b/drivers/scsi/bfa/bfa_ioc.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include @@ -27,7 +27,7 @@ #include #include -BFA_TRC_FILE(HAL, IOC); +BFA_TRC_FILE(CNA, IOC); /** * IOC local definitions diff --git a/drivers/scsi/bfa/bfa_trcmod_priv.h b/drivers/scsi/bfa/bfa_trcmod_priv.h index b3562dce7e9f..3d947d47b837 100644 --- a/drivers/scsi/bfa/bfa_trcmod_priv.h +++ b/drivers/scsi/bfa/bfa_trcmod_priv.h @@ -29,38 +29,36 @@ * !!! needed between trace utility and driver version */ enum { - BFA_TRC_HAL_IOC = 1, - BFA_TRC_HAL_INTR = 2, - BFA_TRC_HAL_FCXP = 3, - BFA_TRC_HAL_UF = 4, - BFA_TRC_HAL_DIAG = 5, - BFA_TRC_HAL_RPORT = 6, - BFA_TRC_HAL_FCPIM = 7, - BFA_TRC_HAL_IOIM = 8, - BFA_TRC_HAL_TSKIM = 9, - BFA_TRC_HAL_ITNIM = 10, - BFA_TRC_HAL_PPORT = 11, - BFA_TRC_HAL_SGPG = 12, - BFA_TRC_HAL_FLASH = 13, - BFA_TRC_HAL_DEBUG = 14, - BFA_TRC_HAL_WWN = 15, - BFA_TRC_HAL_FLASH_RAW = 16, - BFA_TRC_HAL_SBOOT = 17, - BFA_TRC_HAL_SBOOT_IO = 18, - BFA_TRC_HAL_SBOOT_INTR = 19, - BFA_TRC_HAL_SBTEST = 20, - BFA_TRC_HAL_IPFC = 21, - BFA_TRC_HAL_IOCFC = 22, - BFA_TRC_HAL_FCPTM = 23, - BFA_TRC_HAL_IOTM = 24, - BFA_TRC_HAL_TSKTM = 25, - BFA_TRC_HAL_TIN = 26, - BFA_TRC_HAL_LPS = 27, - BFA_TRC_HAL_FCDIAG = 28, - BFA_TRC_HAL_PBIND = 29, - BFA_TRC_HAL_IOCFC_CT = 30, - BFA_TRC_HAL_IOCFC_CB = 31, - BFA_TRC_HAL_IOCFC_Q = 32, + BFA_TRC_HAL_INTR = 1, + BFA_TRC_HAL_FCXP = 2, + BFA_TRC_HAL_UF = 3, + BFA_TRC_HAL_RPORT = 4, + BFA_TRC_HAL_FCPIM = 5, + BFA_TRC_HAL_IOIM = 6, + BFA_TRC_HAL_TSKIM = 7, + BFA_TRC_HAL_ITNIM = 8, + BFA_TRC_HAL_PPORT = 9, + BFA_TRC_HAL_SGPG = 10, + BFA_TRC_HAL_FLASH = 11, + BFA_TRC_HAL_DEBUG = 12, + BFA_TRC_HAL_WWN = 13, + BFA_TRC_HAL_FLASH_RAW = 14, + BFA_TRC_HAL_SBOOT = 15, + BFA_TRC_HAL_SBOOT_IO = 16, + BFA_TRC_HAL_SBOOT_INTR = 17, + BFA_TRC_HAL_SBTEST = 18, + BFA_TRC_HAL_IPFC = 19, + BFA_TRC_HAL_IOCFC = 20, + BFA_TRC_HAL_FCPTM = 21, + BFA_TRC_HAL_IOTM = 22, + BFA_TRC_HAL_TSKTM = 23, + BFA_TRC_HAL_TIN = 24, + BFA_TRC_HAL_LPS = 25, + BFA_TRC_HAL_FCDIAG = 26, + BFA_TRC_HAL_PBIND = 27, + BFA_TRC_HAL_IOCFC_CT = 28, + BFA_TRC_HAL_IOCFC_CB = 29, + BFA_TRC_HAL_IOCFC_Q = 30, }; #endif /* __BFA_TRCMOD_PRIV_H__ */ diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_cee.h b/drivers/scsi/bfa/include/defs/bfa_defs_cee.h index 520a22f52dd1..b0ac9ac15c5d 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_cee.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_cee.h @@ -28,10 +28,6 @@ #define BFA_CEE_LLDP_MAX_STRING_LEN (128) - -/* FIXME: this is coming from the protocol spec. Can the host & apps share the - protocol .h files ? - */ #define BFA_CEE_LLDP_SYS_CAP_OTHER 0x0001 #define BFA_CEE_LLDP_SYS_CAP_REPEATER 0x0002 #define BFA_CEE_LLDP_SYS_CAP_MAC_BRIDGE 0x0004 @@ -94,9 +90,10 @@ struct bfa_cee_dcbx_cfg_s { /* CEE status */ /* Making this to tri-state for the benefit of port list command */ enum bfa_cee_status_e { - CEE_PHY_DOWN = 0, - CEE_PHY_UP = 1, - CEE_UP = 2, + CEE_UP = 0, + CEE_PHY_UP = 1, + CEE_LOOPBACK = 2, + CEE_PHY_DOWN = 3, }; /* CEE Query */ @@ -107,7 +104,8 @@ struct bfa_cee_attr_s { struct bfa_cee_dcbx_cfg_s dcbx_remote; mac_t src_mac; u8 link_speed; - u8 filler[3]; + u8 nw_priority; + u8 filler[2]; }; diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_ioc.h b/drivers/scsi/bfa/include/defs/bfa_defs_ioc.h index b1d532da3a9d..6c721b13aca4 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_ioc.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_ioc.h @@ -126,6 +126,7 @@ struct bfa_ioc_attr_s { struct bfa_ioc_driver_attr_s driver_attr; /* driver attr */ struct bfa_ioc_pci_attr_s pci_attr; u8 port_id; /* port number */ + u8 rsvd[7]; /*!< 64bit align */ }; /** diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_iocfc.h b/drivers/scsi/bfa/include/defs/bfa_defs_iocfc.h index d76bcbd9820f..87f0401c6439 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_iocfc.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_iocfc.h @@ -26,6 +26,8 @@ #define BFA_IOCFC_INTR_DELAY 1125 #define BFA_IOCFC_INTR_LATENCY 225 +#define BFA_IOCFCOE_INTR_DELAY 25 +#define BFA_IOCFCOE_INTR_LATENCY 5 /** * Interrupt coalescing configuration. @@ -50,7 +52,7 @@ struct bfa_iocfc_fwcfg_s { u16 num_fcxp_reqs; /* unassisted FC exchanges */ u16 num_uf_bufs; /* unsolicited recv buffers */ u8 num_cqs; - u8 rsvd; + u8 rsvd[5]; }; struct bfa_iocfc_drvcfg_s { @@ -224,6 +226,11 @@ struct bfa_fw_port_physm_stats_s { struct bfa_fw_fip_stats_s { + u32 vlan_req; /* vlan discovery requests */ + u32 vlan_notify; /* vlan notifications */ + u32 vlan_err; /* vlan response error */ + u32 vlan_timeouts; /* vlan disvoery timeouts */ + u32 vlan_invalids; /* invalid vlan in discovery advert. */ u32 disc_req; /* Discovery solicit requests */ u32 disc_rsp; /* Discovery solicit response */ u32 disc_err; /* Discovery advt. parse errors */ @@ -235,7 +242,7 @@ struct bfa_fw_fip_stats_s { u32 clrvlink_req; /* Clear virtual link req */ u32 op_unsupp; /* Unsupported FIP operation */ u32 untagged; /* Untagged frames (ignored) */ - u32 rsvd; + u32 invalid_version; /*!< Invalid FIP version */ }; diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_mfg.h b/drivers/scsi/bfa/include/defs/bfa_defs_mfg.h index 13fd4ab6aae2..c5bd9c36ad4d 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_mfg.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_mfg.h @@ -22,7 +22,47 @@ /** * Manufacturing block version */ -#define BFA_MFG_VERSION 1 +#define BFA_MFG_VERSION 2 + +/** + * Manufacturing block encrypted version + */ +#define BFA_MFG_ENC_VER 2 + +/** + * Manufacturing block version 1 length + */ +#define BFA_MFG_VER1_LEN 128 + +/** + * Manufacturing block header length + */ +#define BFA_MFG_HDR_LEN 4 + +/** + * Checksum size + */ +#define BFA_MFG_CHKSUM_SIZE 16 + +/** + * Manufacturing block encrypted version + */ +#define BFA_MFG_ENC_VER 2 + +/** + * Manufacturing block version 1 length + */ +#define BFA_MFG_VER1_LEN 128 + +/** + * Manufacturing block header length + */ +#define BFA_MFG_HDR_LEN 4 + +/** + * Checksum size + */ +#define BFA_MFG_CHKSUM_SIZE 16 /** * Manufacturing block format @@ -30,29 +70,74 @@ #define BFA_MFG_SERIALNUM_SIZE 11 #define BFA_MFG_PARTNUM_SIZE 14 #define BFA_MFG_SUPPLIER_ID_SIZE 10 -#define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20 -#define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20 -#define BFA_MFG_SUPPLIER_REVISION_SIZE 4 +#define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20 +#define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20 +#define BFA_MFG_SUPPLIER_REVISION_SIZE 4 #define STRSZ(_n) (((_n) + 4) & ~3) +/** + * Manufacturing card type + */ +enum { + BFA_MFG_TYPE_CB_MAX = 825, /* Crossbow card type max */ + BFA_MFG_TYPE_FC8P2 = 825, /* 8G 2port FC card */ + BFA_MFG_TYPE_FC8P1 = 815, /* 8G 1port FC card */ + BFA_MFG_TYPE_FC4P2 = 425, /* 4G 2port FC card */ + BFA_MFG_TYPE_FC4P1 = 415, /* 4G 1port FC card */ + BFA_MFG_TYPE_CNA10P2 = 1020, /* 10G 2port CNA card */ + BFA_MFG_TYPE_CNA10P1 = 1010, /* 10G 1port CNA card */ +}; + +#pragma pack(1) + +/** + * Card type to port number conversion + */ +#define bfa_mfg_type2port_num(card_type) (((card_type) / 10) % 10) + + +/** + * All numerical fields are in big-endian format. + */ +struct bfa_mfg_block_s { +}; + /** * VPD data length */ -#define BFA_MFG_VPD_LEN 256 +#define BFA_MFG_VPD_LEN 512 + +#define BFA_MFG_VPD_PCI_HDR_OFF 137 +#define BFA_MFG_VPD_PCI_VER_MASK 0x07 /* version mask 3 bits */ +#define BFA_MFG_VPD_PCI_VDR_MASK 0xf8 /* vendor mask 5 bits */ + +/** + * VPD vendor tag + */ +enum { + BFA_MFG_VPD_UNKNOWN = 0, /* vendor unknown */ + BFA_MFG_VPD_IBM = 1, /* vendor IBM */ + BFA_MFG_VPD_HP = 2, /* vendor HP */ + BFA_MFG_VPD_DELL = 3, /* vendor DELL */ + BFA_MFG_VPD_PCI_IBM = 0x08, /* PCI VPD IBM */ + BFA_MFG_VPD_PCI_HP = 0x10, /* PCI VPD HP */ + BFA_MFG_VPD_PCI_DELL = 0x20, /* PCI VPD DELL */ + BFA_MFG_VPD_PCI_BRCD = 0xf8, /* PCI VPD Brocade */ +}; /** * All numerical fields are in big-endian format. */ struct bfa_mfg_vpd_s { - u8 version; /* vpd data version */ - u8 vpd_sig[3]; /* characters 'V', 'P', 'D' */ - u8 chksum; /* u8 checksum */ - u8 vendor; /* vendor */ - u8 len; /* vpd data length excluding header */ - u8 rsv; - u8 data[BFA_MFG_VPD_LEN]; /* vpd data */ + u8 version; /* vpd data version */ + u8 vpd_sig[3]; /* characters 'V', 'P', 'D' */ + u8 chksum; /* u8 checksum */ + u8 vendor; /* vendor */ + u8 len; /* vpd data length excluding header */ + u8 rsv; + u8 data[BFA_MFG_VPD_LEN]; /* vpd data */ }; -#pragma pack(1) +#pragma pack() #endif /* __BFA_DEFS_MFG_H__ */ diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_status.h b/drivers/scsi/bfa/include/defs/bfa_defs_status.h index cdceaeb9f4b8..d8a74ebfe1ae 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_status.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_status.h @@ -180,8 +180,8 @@ enum bfa_status { BFA_STATUS_IM_ADAPT_ALREADY_IN_TEAM = 114, /* Given adapter is part * of another team */ BFA_STATUS_IM_ADAPT_HAS_VLANS = 115, /* Adapter has VLANs configured. - * Delete all VLANs before - * creating team */ + * Delete all VLANs to become + * part of the team */ BFA_STATUS_IM_PVID_MISMATCH = 116, /* Mismatching PVIDs configured * for adapters */ BFA_STATUS_IM_LINK_SPEED_MISMATCH = 117, /* Mismatching link speeds @@ -242,6 +242,14 @@ enum bfa_status { * failed */ BFA_STATUS_IM_UNBIND_FAILED = 149, /* ! < IM Driver unbind operation * failed */ + BFA_STATUS_IM_PORT_IN_TEAM = 150, /* Port is already part of the + * team */ + BFA_STATUS_IM_VLAN_NOT_FOUND = 151, /* VLAN ID doesn't exists */ + BFA_STATUS_IM_TEAM_NOT_FOUND = 152, /* Teaming configuration doesn't + * exists */ + BFA_STATUS_IM_TEAM_CFG_NOT_ALLOWED = 153, /* Given settings are not + * allowed for the current + * Teaming mode */ BFA_STATUS_MAX_VAL /* Unknown error code */ }; #define bfa_status_t enum bfa_status diff --git a/drivers/scsi/bfa/include/log/bfa_log_hal.h b/drivers/scsi/bfa/include/log/bfa_log_hal.h index 0412aea2ec30..5f8f5e30b9e8 100644 --- a/drivers/scsi/bfa/include/log/bfa_log_hal.h +++ b/drivers/scsi/bfa/include/log/bfa_log_hal.h @@ -27,4 +27,10 @@ (((u32) BFA_LOG_HAL_ID << BFA_LOG_MODID_OFFSET) | 3) #define BFA_LOG_HAL_SM_ASSERT \ (((u32) BFA_LOG_HAL_ID << BFA_LOG_MODID_OFFSET) | 4) +#define BFA_LOG_HAL_DRIVER_ERROR \ + (((u32) BFA_LOG_HAL_ID << BFA_LOG_MODID_OFFSET) | 5) +#define BFA_LOG_HAL_DRIVER_CONFIG_ERROR \ + (((u32) BFA_LOG_HAL_ID << BFA_LOG_MODID_OFFSET) | 6) +#define BFA_LOG_HAL_MBOX_ERROR \ + (((u32) BFA_LOG_HAL_ID << BFA_LOG_MODID_OFFSET) | 7) #endif diff --git a/drivers/scsi/bfa/include/log/bfa_log_linux.h b/drivers/scsi/bfa/include/log/bfa_log_linux.h index 317c0547ee16..bd451db4c30a 100644 --- a/drivers/scsi/bfa/include/log/bfa_log_linux.h +++ b/drivers/scsi/bfa/include/log/bfa_log_linux.h @@ -41,4 +41,20 @@ (((u32) BFA_LOG_LINUX_ID << BFA_LOG_MODID_OFFSET) | 10) #define BFA_LOG_LINUX_SCSI_ABORT_COMP \ (((u32) BFA_LOG_LINUX_ID << BFA_LOG_MODID_OFFSET) | 11) +#define BFA_LOG_LINUX_DRIVER_CONFIG_ERROR \ + (((u32) BFA_LOG_LINUX_ID << BFA_LOG_MODID_OFFSET) | 12) +#define BFA_LOG_LINUX_BNA_STATE_MACHINE \ + (((u32) BFA_LOG_LINUX_ID << BFA_LOG_MODID_OFFSET) | 13) +#define BFA_LOG_LINUX_IOC_ERROR \ + (((u32) BFA_LOG_LINUX_ID << BFA_LOG_MODID_OFFSET) | 14) +#define BFA_LOG_LINUX_RESOURCE_ALLOC_ERROR \ + (((u32) BFA_LOG_LINUX_ID << BFA_LOG_MODID_OFFSET) | 15) +#define BFA_LOG_LINUX_RING_BUFFER_ERROR \ + (((u32) BFA_LOG_LINUX_ID << BFA_LOG_MODID_OFFSET) | 16) +#define BFA_LOG_LINUX_DRIVER_ERROR \ + (((u32) BFA_LOG_LINUX_ID << BFA_LOG_MODID_OFFSET) | 17) +#define BFA_LOG_LINUX_DRIVER_DIAG \ + (((u32) BFA_LOG_LINUX_ID << BFA_LOG_MODID_OFFSET) | 18) +#define BFA_LOG_LINUX_DRIVER_AEN \ + (((u32) BFA_LOG_LINUX_ID << BFA_LOG_MODID_OFFSET) | 19) #endif -- cgit v1.2.3 From f926a05f5c1507aeae0e36175a03c0a19c201187 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:36:00 -0800 Subject: [SCSI] bfa: FCS authentication related changes. Made FCS authentication related changes to state machines and header files. Made changes in FCS state machines to handle the case when secret string is NULL. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_fcs_lport.c | 2 ++ drivers/scsi/bfa/fabric.c | 6 ++++++ drivers/scsi/bfa/fcs_fabric.h | 1 + drivers/scsi/bfa/include/defs/bfa_defs_auth.h | 22 ++++++++++++++++++++++ drivers/scsi/bfa/include/defs/bfa_defs_pport.h | 4 ++-- 5 files changed, 33 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_fcs_lport.c b/drivers/scsi/bfa/bfa_fcs_lport.c index 7bb182dcbd7d..4a51aac7ab04 100644 --- a/drivers/scsi/bfa/bfa_fcs_lport.c +++ b/drivers/scsi/bfa/bfa_fcs_lport.c @@ -931,6 +931,8 @@ bfa_fcs_port_get_attr(struct bfa_fcs_port_s *port, if (port->fabric) { port_attr->port_type = bfa_fcs_fabric_port_type(port->fabric); port_attr->loopback = bfa_fcs_fabric_is_loopback(port->fabric); + port_attr->authfail = + bfa_fcs_fabric_is_auth_failed(port->fabric); port_attr->fabric_name = bfa_fcs_port_get_fabric_name(port); memcpy(port_attr->fabric_ip_addr, bfa_fcs_port_get_fabric_ipaddr(port), diff --git a/drivers/scsi/bfa/fabric.c b/drivers/scsi/bfa/fabric.c index 20a686a420a2..b02ed7653eb6 100644 --- a/drivers/scsi/bfa/fabric.c +++ b/drivers/scsi/bfa/fabric.c @@ -895,6 +895,12 @@ bfa_fcs_fabric_is_loopback(struct bfa_fcs_fabric_s *fabric) return bfa_sm_cmp_state(fabric, bfa_fcs_fabric_sm_loopback); } +bfa_boolean_t +bfa_fcs_fabric_is_auth_failed(struct bfa_fcs_fabric_s *fabric) +{ + return bfa_sm_cmp_state(fabric, bfa_fcs_fabric_sm_auth_failed); +} + enum bfa_pport_type bfa_fcs_fabric_port_type(struct bfa_fcs_fabric_s *fabric) { diff --git a/drivers/scsi/bfa/fcs_fabric.h b/drivers/scsi/bfa/fcs_fabric.h index 8237bd5e7217..244c3f00c50c 100644 --- a/drivers/scsi/bfa/fcs_fabric.h +++ b/drivers/scsi/bfa/fcs_fabric.h @@ -47,6 +47,7 @@ void bfa_fcs_fabric_uf_recv(struct bfa_fcs_fabric_s *fabric, struct fchs_s *fchs, u16 len); u16 bfa_fcs_fabric_vport_count(struct bfa_fcs_fabric_s *fabric); bfa_boolean_t bfa_fcs_fabric_is_loopback(struct bfa_fcs_fabric_s *fabric); +bfa_boolean_t bfa_fcs_fabric_is_auth_failed(struct bfa_fcs_fabric_s *fabric); enum bfa_pport_type bfa_fcs_fabric_port_type(struct bfa_fcs_fabric_s *fabric); void bfa_fcs_fabric_psymb_init(struct bfa_fcs_fabric_s *fabric); void bfa_fcs_fabric_port_delete_comp(struct bfa_fcs_fabric_s *fabric); diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_auth.h b/drivers/scsi/bfa/include/defs/bfa_defs_auth.h index dd19c83aba58..45df32820911 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_auth.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_auth.h @@ -23,6 +23,7 @@ #define PRIVATE_KEY 19009 #define KEY_LEN 32399 #define BFA_AUTH_SECRET_STRING_LEN 256 +#define BFA_AUTH_FAIL_NO_PASSWORD 0xFE #define BFA_AUTH_FAIL_TIMEOUT 0xFF /** @@ -41,6 +42,27 @@ enum bfa_auth_status { BFA_AUTH_STATUS_UNKNOWN = 9, /* authentication status unknown */ }; +enum bfa_auth_rej_code { + BFA_AUTH_RJT_CODE_AUTH_FAILURE = 1, /* auth failure */ + BFA_AUTH_RJT_CODE_LOGICAL_ERR = 2, /* logical error */ +}; + +/** + * Authentication reject codes + */ +enum bfa_auth_rej_code_exp { + BFA_AUTH_MECH_NOT_USABLE = 1, /* auth. mechanism not usable */ + BFA_AUTH_DH_GROUP_NOT_USABLE = 2, /* DH Group not usable */ + BFA_AUTH_HASH_FUNC_NOT_USABLE = 3, /* hash Function not usable */ + BFA_AUTH_AUTH_XACT_STARTED = 4, /* auth xact started */ + BFA_AUTH_AUTH_FAILED = 5, /* auth failed */ + BFA_AUTH_INCORRECT_PLD = 6, /* incorrect payload */ + BFA_AUTH_INCORRECT_PROTO_MSG = 7, /* incorrect proto msg */ + BFA_AUTH_RESTART_AUTH_PROTO = 8, /* restart auth protocol */ + BFA_AUTH_AUTH_CONCAT_NOT_SUPP = 9, /* auth concat not supported */ + BFA_AUTH_PROTO_VER_NOT_SUPP = 10,/* proto version not supported */ +}; + struct auth_proto_stats_s { u32 auth_rjts; u32 auth_negs; diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_pport.h b/drivers/scsi/bfa/include/defs/bfa_defs_pport.h index bf320412ee24..88662a15a21b 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_pport.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_pport.h @@ -232,7 +232,7 @@ struct bfa_pport_attr_s { u32 pid; /* port ID */ enum bfa_pport_type port_type; /* current topology */ u32 loopback; /* external loopback */ - u32 rsvd1; + u32 authfail; /* auth fail state */ u32 rsvd2; /* padding for 64 bit */ }; @@ -247,7 +247,7 @@ struct bfa_pport_fc_stats_s { u64 rx_words; /* received words */ u64 lip_count; /* LIPs seen */ u64 nos_count; /* NOS count */ - u64 error_frames; /* errored frames (sent?) */ + u64 error_frames; /* errored frames */ u64 dropped_frames; /* dropped frames */ u64 link_failures; /* link failure count */ u64 loss_of_syncs; /* loss of sync count */ -- cgit v1.2.3 From 738c9e66dcb7e17a962a7d65c976386b970d10ca Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:36:19 -0800 Subject: [SCSI] bfa: Added firmware save clear feature for BFA driver. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_core.c | 9 +++++++++ drivers/scsi/bfa/bfa_ioc.c | 10 +++++++++- drivers/scsi/bfa/bfa_ioc.h | 1 + drivers/scsi/bfa/include/bfa.h | 1 + 4 files changed, 20 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_core.c b/drivers/scsi/bfa/bfa_core.c index 72e3f2f63b2e..0c08e185a766 100644 --- a/drivers/scsi/bfa/bfa_core.c +++ b/drivers/scsi/bfa/bfa_core.c @@ -384,6 +384,15 @@ bfa_debug_fwsave(struct bfa_s *bfa, void *trcdata, int *trclen) return bfa_ioc_debug_fwsave(&bfa->ioc, trcdata, trclen); } +/** + * Clear the saved firmware trace information of an IOC. + */ +void +bfa_debug_fwsave_clear(struct bfa_s *bfa) +{ + bfa_ioc_debug_fwsave_clear(&bfa->ioc); +} + /** * Fetch firmware trace data. * diff --git a/drivers/scsi/bfa/bfa_ioc.c b/drivers/scsi/bfa/bfa_ioc.c index 8a6361cf2439..0019ff7359db 100644 --- a/drivers/scsi/bfa/bfa_ioc.c +++ b/drivers/scsi/bfa/bfa_ioc.c @@ -1488,7 +1488,6 @@ return (auto_recover) ? BFA_DBG_FWTRC_LEN : 0; void bfa_ioc_debug_memclaim(struct bfa_ioc_s *ioc, void *dbg_fwsave) { - bfa_assert(ioc->auto_recover); ioc->dbg_fwsave = dbg_fwsave; ioc->dbg_fwsave_len = bfa_ioc_debug_trcsz(ioc->auto_recover); } @@ -1924,6 +1923,15 @@ bfa_ioc_debug_fwsave(struct bfa_ioc_s *ioc, void *trcdata, int *trclen) return BFA_STATUS_OK; } +/** + * Clear saved firmware trace + */ +void +bfa_ioc_debug_fwsave_clear(struct bfa_ioc_s *ioc) +{ + ioc->dbg_fwsave_once = BFA_TRUE; +} + /** * Retrieve saved firmware trace from a prior IOC failure. */ diff --git a/drivers/scsi/bfa/bfa_ioc.h b/drivers/scsi/bfa/bfa_ioc.h index 853cc3136f0e..4b73efad1ee5 100644 --- a/drivers/scsi/bfa/bfa_ioc.h +++ b/drivers/scsi/bfa/bfa_ioc.h @@ -270,6 +270,7 @@ int bfa_ioc_debug_trcsz(bfa_boolean_t auto_recover); void bfa_ioc_debug_memclaim(struct bfa_ioc_s *ioc, void *dbg_fwsave); bfa_status_t bfa_ioc_debug_fwsave(struct bfa_ioc_s *ioc, void *trcdata, int *trclen); +void bfa_ioc_debug_fwsave_clear(struct bfa_ioc_s *ioc); bfa_status_t bfa_ioc_debug_fwtrc(struct bfa_ioc_s *ioc, void *trcdata, int *trclen); u32 bfa_ioc_smem_pgnum(struct bfa_ioc_s *ioc, u32 fmaddr); diff --git a/drivers/scsi/bfa/include/bfa.h b/drivers/scsi/bfa/include/bfa.h index 942ae64038c9..17654cae0c75 100644 --- a/drivers/scsi/bfa/include/bfa.h +++ b/drivers/scsi/bfa/include/bfa.h @@ -172,6 +172,7 @@ void bfa_timer_tick(struct bfa_s *bfa); */ bfa_status_t bfa_debug_fwtrc(struct bfa_s *bfa, void *trcdata, int *trclen); bfa_status_t bfa_debug_fwsave(struct bfa_s *bfa, void *trcdata, int *trclen); +void bfa_debug_fwsave_clear(struct bfa_s *bfa); #include "bfa_priv.h" -- cgit v1.2.3 From 9693e7dff5c2911b4e445f5f656ef57b3a5bffac Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:36:30 -0800 Subject: [SCSI] bfa: Introduce a link notification state machine. Introduce a link notification state machine to handle next incoming link events while the current event is being delivered to the driver. When the event has been processed by the driver, the link notification state machine will queue the next event (if there is any) to the driver. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_fcport.c | 232 ++++++++++++++++++++++++++++++++++++--- drivers/scsi/bfa/bfa_port_priv.h | 13 ++- 2 files changed, 230 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_fcport.c b/drivers/scsi/bfa/bfa_fcport.c index aef648b55dfc..4ed048bf45cb 100644 --- a/drivers/scsi/bfa/bfa_fcport.c +++ b/drivers/scsi/bfa/bfa_fcport.c @@ -26,16 +26,6 @@ BFA_TRC_FILE(HAL, PPORT); BFA_MODULE(pport); -#define bfa_pport_callback(__pport, __event) do { \ - if ((__pport)->bfa->fcs) { \ - (__pport)->event_cbfn((__pport)->event_cbarg, (__event)); \ - } else { \ - (__pport)->hcb_event = (__event); \ - bfa_cb_queue((__pport)->bfa, &(__pport)->hcb_qe, \ - __bfa_cb_port_event, (__pport)); \ - } \ -} while (0) - /* * The port is considered disabled if corresponding physical port or IOC are * disabled explicitly @@ -57,7 +47,10 @@ static void __bfa_cb_port_stats(void *cbarg, bfa_boolean_t complete); static void __bfa_cb_port_stats_clr(void *cbarg, bfa_boolean_t complete); static void bfa_port_stats_timeout(void *cbarg); static void bfa_port_stats_clr_timeout(void *cbarg); - +static void bfa_pport_callback(struct bfa_pport_s *pport, + enum bfa_pport_linkstate event); +static void bfa_pport_queue_cb(struct bfa_pport_ln_s *ln, + enum bfa_pport_linkstate event); /** * bfa_pport_private */ @@ -77,6 +70,16 @@ enum bfa_pport_sm_event { BFA_PPORT_SM_HWFAIL = 9, /* IOC h/w failure */ }; +/** + * BFA port link notification state machine events + */ + +enum bfa_pport_ln_sm_event { + BFA_PPORT_LN_SM_LINKUP = 1, /* linkup event */ + BFA_PPORT_LN_SM_LINKDOWN = 2, /* linkdown event */ + BFA_PPORT_LN_SM_NOTIFICATION = 3 /* done notification */ +}; + static void bfa_pport_sm_uninit(struct bfa_pport_s *pport, enum bfa_pport_sm_event event); static void bfa_pport_sm_enabling_qwait(struct bfa_pport_s *pport, @@ -100,6 +103,21 @@ static void bfa_pport_sm_iocdown(struct bfa_pport_s *pport, static void bfa_pport_sm_iocfail(struct bfa_pport_s *pport, enum bfa_pport_sm_event event); +static void bfa_pport_ln_sm_dn(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event); +static void bfa_pport_ln_sm_dn_nf(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event); +static void bfa_pport_ln_sm_dn_up_nf(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event); +static void bfa_pport_ln_sm_up(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event); +static void bfa_pport_ln_sm_up_nf(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event); +static void bfa_pport_ln_sm_up_dn_nf(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event); +static void bfa_pport_ln_sm_up_dn_up_nf(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event); + static struct bfa_sm_table_s hal_pport_sm_table[] = { {BFA_SM(bfa_pport_sm_uninit), BFA_PPORT_ST_UNINIT}, {BFA_SM(bfa_pport_sm_enabling_qwait), BFA_PPORT_ST_ENABLING_QWAIT}, @@ -619,7 +637,163 @@ bfa_pport_sm_iocfail(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) } } +/** + * Link state is down + */ +static void +bfa_pport_ln_sm_dn(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event) +{ + bfa_trc(ln->pport->bfa, event); + + switch (event) { + case BFA_PPORT_LN_SM_LINKUP: + bfa_sm_set_state(ln, bfa_pport_ln_sm_up_nf); + bfa_pport_queue_cb(ln, BFA_PPORT_LINKUP); + break; + + default: + bfa_sm_fault(ln->pport->bfa, event); + } +} + +/** + * Link state is waiting for down notification + */ +static void +bfa_pport_ln_sm_dn_nf(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event) +{ + bfa_trc(ln->pport->bfa, event); + + switch (event) { + case BFA_PPORT_LN_SM_LINKUP: + bfa_sm_set_state(ln, bfa_pport_ln_sm_dn_up_nf); + break; + + case BFA_PPORT_LN_SM_NOTIFICATION: + bfa_sm_set_state(ln, bfa_pport_ln_sm_dn); + break; + + default: + bfa_sm_fault(ln->pport->bfa, event); + } +} + +/** + * Link state is waiting for down notification and there is a pending up + */ +static void +bfa_pport_ln_sm_dn_up_nf(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event) +{ + bfa_trc(ln->pport->bfa, event); + + switch (event) { + case BFA_PPORT_LN_SM_LINKDOWN: + bfa_sm_set_state(ln, bfa_pport_ln_sm_dn_nf); + break; + + case BFA_PPORT_LN_SM_NOTIFICATION: + bfa_sm_set_state(ln, bfa_pport_ln_sm_up_nf); + bfa_pport_queue_cb(ln, BFA_PPORT_LINKUP); + break; + + default: + bfa_sm_fault(ln->pport->bfa, event); + } +} + +/** + * Link state is up + */ +static void +bfa_pport_ln_sm_up(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event) +{ + bfa_trc(ln->pport->bfa, event); + + switch (event) { + case BFA_PPORT_LN_SM_LINKDOWN: + bfa_sm_set_state(ln, bfa_pport_ln_sm_dn_nf); + bfa_pport_queue_cb(ln, BFA_PPORT_LINKDOWN); + break; + + default: + bfa_sm_fault(ln->pport->bfa, event); + } +} + +/** + * Link state is waiting for up notification + */ +static void +bfa_pport_ln_sm_up_nf(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event) +{ + bfa_trc(ln->pport->bfa, event); + + switch (event) { + case BFA_PPORT_LN_SM_LINKDOWN: + bfa_sm_set_state(ln, bfa_pport_ln_sm_up_dn_nf); + break; + + case BFA_PPORT_LN_SM_NOTIFICATION: + bfa_sm_set_state(ln, bfa_pport_ln_sm_up); + break; + + default: + bfa_sm_fault(ln->pport->bfa, event); + } +} + +/** + * Link state is waiting for up notification and there is a pending down + */ +static void +bfa_pport_ln_sm_up_dn_nf(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event) +{ + bfa_trc(ln->pport->bfa, event); + switch (event) { + case BFA_PPORT_LN_SM_LINKUP: + bfa_sm_set_state(ln, bfa_pport_ln_sm_up_dn_up_nf); + break; + + case BFA_PPORT_LN_SM_NOTIFICATION: + bfa_sm_set_state(ln, bfa_pport_ln_sm_dn_nf); + bfa_pport_queue_cb(ln, BFA_PPORT_LINKDOWN); + break; + + default: + bfa_sm_fault(ln->pport->bfa, event); + } +} + +/** + * Link state is waiting for up notification and there are pending down and up + */ +static void +bfa_pport_ln_sm_up_dn_up_nf(struct bfa_pport_ln_s *ln, + enum bfa_pport_ln_sm_event event) +{ + bfa_trc(ln->pport->bfa, event); + + switch (event) { + case BFA_PPORT_LN_SM_LINKDOWN: + bfa_sm_set_state(ln, bfa_pport_ln_sm_up_dn_nf); + break; + + case BFA_PPORT_LN_SM_NOTIFICATION: + bfa_sm_set_state(ln, bfa_pport_ln_sm_dn_up_nf); + bfa_pport_queue_cb(ln, BFA_PPORT_LINKDOWN); + break; + + default: + bfa_sm_fault(ln->pport->bfa, event); + } +} /** * bfa_pport_private @@ -628,10 +802,12 @@ bfa_pport_sm_iocfail(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) static void __bfa_cb_port_event(void *cbarg, bfa_boolean_t complete) { - struct bfa_pport_s *pport = cbarg; + struct bfa_pport_ln_s *ln = cbarg; if (complete) - pport->event_cbfn(pport->event_cbarg, pport->hcb_event); + ln->pport->event_cbfn(ln->pport->event_cbarg, ln->ln_event); + else + bfa_sm_send_event(ln, BFA_PPORT_LN_SM_NOTIFICATION); } #define PPORT_STATS_DMA_SZ (BFA_ROUNDUP(sizeof(union bfa_pport_stats_u), \ @@ -681,13 +857,16 @@ bfa_pport_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, { struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); struct bfa_pport_cfg_s *port_cfg = &pport->cfg; + struct bfa_pport_ln_s *ln = &pport->ln; bfa_os_memset(pport, 0, sizeof(struct bfa_pport_s)); pport->bfa = bfa; + ln->pport = pport; bfa_pport_mem_claim(pport, meminfo); bfa_sm_set_state(pport, bfa_pport_sm_uninit); + bfa_sm_set_state(ln, bfa_pport_ln_sm_dn); /** * initialize and set default configuration @@ -1368,6 +1547,33 @@ bfa_port_stats_clr_timeout(void *cbarg) bfa_cb_queue(port->bfa, &port->hcb_qe, __bfa_cb_port_stats_clr, port); } +static void +bfa_pport_callback(struct bfa_pport_s *pport, enum bfa_pport_linkstate event) +{ + if (pport->bfa->fcs) { + pport->event_cbfn(pport->event_cbarg, event); + return; + } + + switch (event) { + case BFA_PPORT_LINKUP: + bfa_sm_send_event(&pport->ln, BFA_PPORT_LN_SM_LINKUP); + break; + case BFA_PPORT_LINKDOWN: + bfa_sm_send_event(&pport->ln, BFA_PPORT_LN_SM_LINKDOWN); + break; + default: + bfa_assert(0); + } +} + +static void +bfa_pport_queue_cb(struct bfa_pport_ln_s *ln, enum bfa_pport_linkstate event) +{ + ln->ln_event = event; + bfa_cb_queue(ln->pport->bfa, &ln->ln_qe, __bfa_cb_port_event, ln); +} + static void __bfa_cb_port_stats(void *cbarg, bfa_boolean_t complete) { diff --git a/drivers/scsi/bfa/bfa_port_priv.h b/drivers/scsi/bfa/bfa_port_priv.h index 51f698a06b6d..f29701bd2369 100644 --- a/drivers/scsi/bfa/bfa_port_priv.h +++ b/drivers/scsi/bfa/bfa_port_priv.h @@ -22,6 +22,16 @@ #include #include "bfa_intr_priv.h" +/** + * Link notification data structure + */ +struct bfa_pport_ln_s { + struct bfa_pport_s *pport; + bfa_sm_t sm; + struct bfa_cb_qe_s ln_qe; /* BFA callback queue elem for ln */ + enum bfa_pport_linkstate ln_event; /* ln event for callback */ +}; + /** * BFA physical port data structure */ @@ -52,9 +62,8 @@ struct bfa_pport_s { union bfi_pport_i2h_msg_u i2hmsg; } event_arg; void *bfad; /* BFA driver handle */ + struct bfa_pport_ln_s ln; /* Link Notification */ struct bfa_cb_qe_s hcb_qe; /* BFA callback queue elem */ - enum bfa_pport_linkstate hcb_event; - /* link event for callback */ u32 msgtag; /* fimrware msg tag for reply */ u8 *stats_kva; u64 stats_pa; -- cgit v1.2.3 From 2993cc71d1bff61999ade7f2b6b3ea2dd1e2c8d9 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:36:47 -0800 Subject: [SCSI] bfa: AEN and byte alignment fixes. Replace enum types with int and rearrange the fields to fix some alignment issue. Local var ioc_attr is causing the stack to overflow, so removed the usage of the local ioc_attr var and now invoking an API to return the ioc_type. Fix some AEN issues. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_fcport.c | 1 + drivers/scsi/bfa/bfa_ioc.c | 32 +++++++++++------ drivers/scsi/bfa/bfad.c | 9 +---- drivers/scsi/bfa/bfad_drv.h | 12 +------ drivers/scsi/bfa/include/aen/bfa_aen.h | 50 ++++++++++++++------------ drivers/scsi/bfa/include/defs/bfa_defs_aen.h | 10 ++++++ drivers/scsi/bfa/include/defs/bfa_defs_ioc.h | 2 +- drivers/scsi/bfa/include/defs/bfa_defs_lport.h | 4 +-- drivers/scsi/bfa/include/defs/bfa_defs_port.h | 17 ++++----- 9 files changed, 73 insertions(+), 64 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_fcport.c b/drivers/scsi/bfa/bfa_fcport.c index 4ed048bf45cb..bdea7f0eb6bd 100644 --- a/drivers/scsi/bfa/bfa_fcport.c +++ b/drivers/scsi/bfa/bfa_fcport.c @@ -142,6 +142,7 @@ bfa_pport_aen_post(struct bfa_pport_s *pport, enum bfa_port_aen_event event) char pwwn_ptr[BFA_STRING_32]; struct bfa_ioc_attr_s ioc_attr; + memset(&aen_data, 0, sizeof(aen_data)); wwn2str(pwwn_ptr, pwwn); switch (event) { case BFA_PORT_AEN_ONLINE: diff --git a/drivers/scsi/bfa/bfa_ioc.c b/drivers/scsi/bfa/bfa_ioc.c index 0019ff7359db..2f09d17730cc 100644 --- a/drivers/scsi/bfa/bfa_ioc.c +++ b/drivers/scsi/bfa/bfa_ioc.c @@ -1731,6 +1731,21 @@ bfa_ioc_get_adapter_attr(struct bfa_ioc_s *ioc, ad_attr->cna_capable = ioc->cna; } +enum bfa_ioc_type_e +bfa_ioc_get_type(struct bfa_ioc_s *ioc) +{ + if (!ioc->ctdev || ioc->fcmode) + return BFA_IOC_TYPE_FC; + else if (ioc->ioc_mc == BFI_MC_IOCFC) + return BFA_IOC_TYPE_FCoE; + else if (ioc->ioc_mc == BFI_MC_LL) + return BFA_IOC_TYPE_LL; + else { + bfa_assert(ioc->ioc_mc == BFI_MC_LL); + return BFA_IOC_TYPE_LL; + } +} + void bfa_ioc_get_attr(struct bfa_ioc_s *ioc, struct bfa_ioc_attr_s *ioc_attr) { @@ -1739,12 +1754,7 @@ bfa_ioc_get_attr(struct bfa_ioc_s *ioc, struct bfa_ioc_attr_s *ioc_attr) ioc_attr->state = bfa_sm_to_state(ioc_sm_table, ioc->fsm); ioc_attr->port_id = ioc->port_id; - if (!ioc->ctdev || ioc->fcmode) - ioc_attr->ioc_type = BFA_IOC_TYPE_FC; - else if (ioc->ioc_mc == BFI_MC_IOCFC) - ioc_attr->ioc_type = BFA_IOC_TYPE_FCoE; - else if (ioc->ioc_mc == BFI_MC_LL) - ioc_attr->ioc_type = BFA_IOC_TYPE_LL; + ioc_attr->ioc_type = bfa_ioc_get_type(ioc); bfa_ioc_get_adapter_attr(ioc, &ioc_attr->adapter_attr); @@ -1860,7 +1870,7 @@ bfa_ioc_aen_post(struct bfa_ioc_s *ioc, enum bfa_ioc_aen_event event) union bfa_aen_data_u aen_data; struct bfa_log_mod_s *logmod = ioc->logm; s32 inst_num = 0; - struct bfa_ioc_attr_s ioc_attr; + enum bfa_ioc_type_e ioc_type; switch (event) { case BFA_IOC_AEN_HBGOOD: @@ -1884,8 +1894,8 @@ bfa_ioc_aen_post(struct bfa_ioc_s *ioc, enum bfa_ioc_aen_event event) memset(&aen_data.ioc.pwwn, 0, sizeof(aen_data.ioc.pwwn)); memset(&aen_data.ioc.mac, 0, sizeof(aen_data.ioc.mac)); - bfa_ioc_get_attr(ioc, &ioc_attr); - switch (ioc_attr.ioc_type) { + ioc_type = bfa_ioc_get_type(ioc); + switch (ioc_type) { case BFA_IOC_TYPE_FC: aen_data.ioc.pwwn = bfa_ioc_get_pwwn(ioc); break; @@ -1897,10 +1907,10 @@ bfa_ioc_aen_post(struct bfa_ioc_s *ioc, enum bfa_ioc_aen_event event) aen_data.ioc.mac = bfa_ioc_get_mac(ioc); break; default: - bfa_assert(ioc_attr.ioc_type == BFA_IOC_TYPE_FC); + bfa_assert(ioc_type == BFA_IOC_TYPE_FC); break; } - aen_data.ioc.ioc_type = ioc_attr.ioc_type; + aen_data.ioc.ioc_type = ioc_type; } /** diff --git a/drivers/scsi/bfa/bfad.c b/drivers/scsi/bfa/bfad.c index 4ccaeaecd14c..79956c152af9 100644 --- a/drivers/scsi/bfa/bfad.c +++ b/drivers/scsi/bfa/bfad.c @@ -677,7 +677,6 @@ bfad_drv_init(struct bfad_s *bfad) bfa_status_t rc; unsigned long flags; struct bfa_fcs_driver_info_s driver_info; - int i; bfad->cfg_data.rport_del_timeout = rport_del_timeout; bfad->cfg_data.lun_queue_depth = bfa_lun_queue_depth; @@ -697,12 +696,7 @@ bfad_drv_init(struct bfad_s *bfad) bfa_init_log(&bfad->bfa, bfad->logmod); bfa_init_trc(&bfad->bfa, bfad->trcmod); bfa_init_aen(&bfad->bfa, bfad->aen); - INIT_LIST_HEAD(&bfad->file_q); - INIT_LIST_HEAD(&bfad->file_free_q); - for (i = 0; i < BFAD_AEN_MAX_APPS; i++) { - bfa_q_qe_init(&bfad->file_buf[i].qe); - list_add_tail(&bfad->file_buf[i].qe, &bfad->file_free_q); - } + memset(bfad->file_map, 0, sizeof(bfad->file_map)); bfa_init_plog(&bfad->bfa, &bfad->plog_buf); bfa_plog_init(&bfad->plog_buf); bfa_plog_str(&bfad->plog_buf, BFA_PL_MID_DRVR, BFA_PL_EID_DRIVER_START, @@ -799,7 +793,6 @@ bfad_drv_uninit(struct bfad_s *bfad) bfa_isr_disable(&bfad->bfa); bfa_detach(&bfad->bfa); bfad_remove_intr(bfad); - bfa_assert(list_empty(&bfad->file_q)); bfad_hal_mem_release(bfad); bfad->bfad_flags &= ~BFAD_DRV_INIT_DONE; diff --git a/drivers/scsi/bfa/bfad_drv.h b/drivers/scsi/bfa/bfad_drv.h index 9fa801a50250..94f4d84c71c9 100644 --- a/drivers/scsi/bfa/bfad_drv.h +++ b/drivers/scsi/bfa/bfad_drv.h @@ -139,14 +139,6 @@ struct bfad_cfg_param_s { u32 binding_method; }; -#define BFAD_AEN_MAX_APPS 8 -struct bfad_aen_file_s { - struct list_head qe; - struct bfad_s *bfad; - s32 ri; - s32 app_id; -}; - /* * BFAD (PCI function) data structure */ @@ -186,9 +178,7 @@ struct bfad_s { struct bfa_log_mod_s *logmod; struct bfa_aen_s *aen; struct bfa_aen_s aen_buf; - struct bfad_aen_file_s file_buf[BFAD_AEN_MAX_APPS]; - struct list_head file_q; - struct list_head file_free_q; + void *file_map[BFA_AEN_MAX_APP]; struct bfa_plog_s plog_buf; int ref_count; bfa_boolean_t ipfc_enabled; diff --git a/drivers/scsi/bfa/include/aen/bfa_aen.h b/drivers/scsi/bfa/include/aen/bfa_aen.h index d9cbc2a783d4..6abbab005db6 100644 --- a/drivers/scsi/bfa/include/aen/bfa_aen.h +++ b/drivers/scsi/bfa/include/aen/bfa_aen.h @@ -18,21 +18,24 @@ #define __BFA_AEN_H__ #include "defs/bfa_defs_aen.h" +#include "defs/bfa_defs_status.h" +#include "cs/bfa_debug.h" -#define BFA_AEN_MAX_ENTRY 512 +#define BFA_AEN_MAX_ENTRY 512 -extern s32 bfa_aen_max_cfg_entry; +extern int bfa_aen_max_cfg_entry; struct bfa_aen_s { void *bfad; - s32 max_entry; - s32 write_index; - s32 read_index; - u32 bfad_num; - u32 seq_num; + int max_entry; + int write_index; + int read_index; + int bfad_num; + int seq_num; void (*aen_cb_notify)(void *bfad); void (*gettimeofday)(struct bfa_timeval_s *tv); - struct bfa_trc_mod_s *trcmod; - struct bfa_aen_entry_s list[BFA_AEN_MAX_ENTRY]; /* Must be the last */ + struct bfa_trc_mod_s *trcmod; + int app_ri[BFA_AEN_MAX_APP]; /* For multiclient support */ + struct bfa_aen_entry_s list[BFA_AEN_MAX_ENTRY]; /* Must be the last */ }; @@ -45,48 +48,49 @@ bfa_aen_set_max_cfg_entry(int max_entry) bfa_aen_max_cfg_entry = max_entry; } -static inline s32 +static inline int bfa_aen_get_max_cfg_entry(void) { return bfa_aen_max_cfg_entry; } -static inline s32 +static inline int bfa_aen_get_meminfo(void) { return sizeof(struct bfa_aen_entry_s) * bfa_aen_get_max_cfg_entry(); } -static inline s32 +static inline int bfa_aen_get_wi(struct bfa_aen_s *aen) { return aen->write_index; } -static inline s32 +static inline int bfa_aen_get_ri(struct bfa_aen_s *aen) { return aen->read_index; } -static inline s32 -bfa_aen_fetch_count(struct bfa_aen_s *aen, s32 read_index) +static inline int +bfa_aen_fetch_count(struct bfa_aen_s *aen, enum bfa_aen_app app_id) { - return ((aen->write_index + aen->max_entry) - read_index) + bfa_assert((app_id < BFA_AEN_MAX_APP) && (app_id >= bfa_aen_app_bcu)); + return ((aen->write_index + aen->max_entry) - aen->app_ri[app_id]) % aen->max_entry; } -s32 bfa_aen_init(struct bfa_aen_s *aen, struct bfa_trc_mod_s *trcmod, - void *bfad, u32 inst_id, void (*aen_cb_notify)(void *), +int bfa_aen_init(struct bfa_aen_s *aen, struct bfa_trc_mod_s *trcmod, + void *bfad, int bfad_num, void (*aen_cb_notify)(void *), void (*gettimeofday)(struct bfa_timeval_s *)); -s32 bfa_aen_post(struct bfa_aen_s *aen, enum bfa_aen_category aen_category, +void bfa_aen_post(struct bfa_aen_s *aen, enum bfa_aen_category aen_category, int aen_type, union bfa_aen_data_u *aen_data); -s32 bfa_aen_fetch(struct bfa_aen_s *aen, struct bfa_aen_entry_s *aen_entry, - s32 entry_space, s32 rii, s32 *ri_arr, - s32 ri_arr_cnt); +bfa_status_t bfa_aen_fetch(struct bfa_aen_s *aen, + struct bfa_aen_entry_s *aen_entry, + int entry_req, enum bfa_aen_app app_id, int *entry_ret); -s32 bfa_aen_get_inst(struct bfa_aen_s *aen); +int bfa_aen_get_inst(struct bfa_aen_s *aen); #endif /* __BFA_AEN_H__ */ diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_aen.h b/drivers/scsi/bfa/include/defs/bfa_defs_aen.h index 4c81a613db3d..35244698fcdc 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_aen.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_aen.h @@ -30,6 +30,16 @@ #include #include +#define BFA_AEN_MAX_APP 5 + +enum bfa_aen_app { + bfa_aen_app_bcu = 0, /* No thread for bcu */ + bfa_aen_app_hcm = 1, + bfa_aen_app_cim = 2, + bfa_aen_app_snia = 3, + bfa_aen_app_test = 4, /* To be removed after unit test */ +}; + enum bfa_aen_category { BFA_AEN_CAT_ADAPTER = 1, BFA_AEN_CAT_PORT = 2, diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_ioc.h b/drivers/scsi/bfa/include/defs/bfa_defs_ioc.h index 6c721b13aca4..8d8e6a966537 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_ioc.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_ioc.h @@ -144,8 +144,8 @@ enum bfa_ioc_aen_event { * BFA IOC level event data, now just a place holder */ struct bfa_ioc_aen_data_s { - enum bfa_ioc_type_e ioc_type; wwn_t pwwn; + s16 ioc_type; mac_t mac; }; diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_lport.h b/drivers/scsi/bfa/include/defs/bfa_defs_lport.h index 7359f82aacfc..0952a139c47c 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_lport.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_lport.h @@ -59,8 +59,8 @@ enum bfa_lport_aen_event { */ struct bfa_lport_aen_data_s { u16 vf_id; /* vf_id of this logical port */ - u16 rsvd; - enum bfa_port_role roles; /* Logical port mode,IM/TM/IP etc */ + s16 roles; /* Logical port mode,IM/TM/IP etc */ + u32 rsvd; wwn_t ppwwn; /* WWN of its physical port */ wwn_t lpwwn; /* WWN of this logical port */ }; diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_port.h b/drivers/scsi/bfa/include/defs/bfa_defs_port.h index 1c74a8b94aad..501bc9739d9d 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_port.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_port.h @@ -234,14 +234,15 @@ enum bfa_port_aen_sfp_pom { }; struct bfa_port_aen_data_s { - enum bfa_ioc_type_e ioc_type; - wwn_t pwwn; /* WWN of the physical port */ - wwn_t fwwn; /* WWN of the fabric port */ - mac_t mac; /* MAC address of the ethernet port, - * applicable to CNA port only */ - int phy_port_num; /*! For SFP related events */ - enum bfa_port_aen_sfp_pom level; /* Only transitions will - * be informed */ + wwn_t pwwn; /* WWN of the physical port */ + wwn_t fwwn; /* WWN of the fabric port */ + s32 phy_port_num; /*! For SFP related events */ + s16 ioc_type; + s16 level; /* Only transitions will + * be informed */ + struct mac_s mac; /* MAC address of the ethernet port, + * applicable to CNA port only */ + s16 rsvd; }; #endif /* __BFA_DEFS_PORT_H__ */ -- cgit v1.2.3 From 816e49b8ed209e5e08d4c43359635cbca17e7196 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:36:56 -0800 Subject: [SCSI] bfa: IOC recovery fix in fcmode. ioc_recover failed to work in fcmode. Fixed the code to initialize the ioc_regs.err_set during the notify_hbfail. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_ioc_ct.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_ioc_ct.c b/drivers/scsi/bfa/bfa_ioc_ct.c index 0430edd2e011..469da95aedf3 100644 --- a/drivers/scsi/bfa/bfa_ioc_ct.c +++ b/drivers/scsi/bfa/bfa_ioc_ct.c @@ -171,10 +171,14 @@ bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc) static void bfa_ioc_ct_notify_hbfail(struct bfa_ioc_s *ioc) { - - bfa_reg_write(ioc->ioc_regs.ll_halt, __FW_INIT_HALT_P); - /* Wait for halt to take effect */ - bfa_reg_read(ioc->ioc_regs.ll_halt); + if (ioc->cna) { + bfa_reg_write(ioc->ioc_regs.ll_halt, __FW_INIT_HALT_P); + /* Wait for halt to take effect */ + bfa_reg_read(ioc->ioc_regs.ll_halt); + } else { + bfa_reg_write(ioc->ioc_regs.err_set, __PSS_ERR_STATUS_SET); + bfa_reg_read(ioc->ioc_regs.err_set); + } } /** @@ -254,6 +258,11 @@ bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc) */ ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START); ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT; + + /* + * err set reg : for notification of hb failure in fcmode + */ + ioc->ioc_regs.err_set = (rb + ERR_SET_REG); } /** -- cgit v1.2.3 From f5713c5dfb4d61cd77debf61d3873eb36877ff1f Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:37:09 -0800 Subject: [SCSI] bfa: Fix Command Queue (CPE) full condition check and ack CPE interrupt. Fixed the issue of not acknowledging the command queue full-to-non-full interrupt. Implemented separate acknowledging functions for different ASIC and interrupt mode. Fixed the case of missing CPE interrupt by always processing the pending requests in the completion path. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_hw_cb.c | 13 ++++++++ drivers/scsi/bfa/bfa_hw_ct.c | 9 ++++++ drivers/scsi/bfa/bfa_intr.c | 71 +++++++++++++++++++++++++++++--------------- drivers/scsi/bfa/bfa_iocfc.c | 2 ++ drivers/scsi/bfa/bfa_iocfc.h | 3 ++ 5 files changed, 74 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_hw_cb.c b/drivers/scsi/bfa/bfa_hw_cb.c index ede1438619e2..871a4e28575c 100644 --- a/drivers/scsi/bfa/bfa_hw_cb.c +++ b/drivers/scsi/bfa/bfa_hw_cb.c @@ -52,6 +52,18 @@ bfa_hwcb_reginit(struct bfa_s *bfa) } } +void +bfa_hwcb_reqq_ack(struct bfa_s *bfa, int reqq) +{ +} + +static void +bfa_hwcb_reqq_ack_msix(struct bfa_s *bfa, int reqq) +{ + bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, + __HFN_INT_CPE_Q0 << CPE_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), reqq)); +} + void bfa_hwcb_rspq_ack(struct bfa_s *bfa, int rspq) { @@ -136,6 +148,7 @@ bfa_hwcb_msix_uninstall(struct bfa_s *bfa) void bfa_hwcb_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix) { + bfa->iocfc.hwif.hw_reqq_ack = bfa_hwcb_reqq_ack_msix; bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack_msix; } diff --git a/drivers/scsi/bfa/bfa_hw_ct.c b/drivers/scsi/bfa/bfa_hw_ct.c index 51ae5740e6e9..76ceb9a4bf2f 100644 --- a/drivers/scsi/bfa/bfa_hw_ct.c +++ b/drivers/scsi/bfa/bfa_hw_ct.c @@ -84,6 +84,15 @@ bfa_hwct_reginit(struct bfa_s *bfa) } } +void +bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq) +{ + u32 r32; + + r32 = bfa_reg_read(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]); + bfa_reg_write(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq], r32); +} + void bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq) { diff --git a/drivers/scsi/bfa/bfa_intr.c b/drivers/scsi/bfa/bfa_intr.c index c42254613f73..0eba3f930d5b 100644 --- a/drivers/scsi/bfa/bfa_intr.c +++ b/drivers/scsi/bfa/bfa_intr.c @@ -34,6 +34,26 @@ bfa_msix_lpu(struct bfa_s *bfa) bfa_ioc_mbox_isr(&bfa->ioc); } +static void +bfa_reqq_resume(struct bfa_s *bfa, int qid) +{ + struct list_head *waitq, *qe, *qen; + struct bfa_reqq_wait_s *wqe; + + waitq = bfa_reqq(bfa, qid); + list_for_each_safe(qe, qen, waitq) { + /** + * Callback only as long as there is room in request queue + */ + if (bfa_reqq_full(bfa, qid)) + break; + + list_del(qe); + wqe = (struct bfa_reqq_wait_s *) qe; + wqe->qresume(wqe->cbarg); + } +} + void bfa_msix_all(struct bfa_s *bfa, int vec) { @@ -128,23 +148,18 @@ bfa_isr_disable(struct bfa_s *bfa) void bfa_msix_reqq(struct bfa_s *bfa, int qid) { - struct list_head *waitq, *qe, *qen; - struct bfa_reqq_wait_s *wqe; + struct list_head *waitq; qid &= (BFI_IOC_MAX_CQS - 1); - waitq = bfa_reqq(bfa, qid); - list_for_each_safe(qe, qen, waitq) { - /** - * Callback only as long as there is room in request queue - */ - if (bfa_reqq_full(bfa, qid)) - break; + bfa->iocfc.hwif.hw_reqq_ack(bfa, qid); - list_del(qe); - wqe = (struct bfa_reqq_wait_s *) qe; - wqe->qresume(wqe->cbarg); - } + /** + * Resume any pending requests in the corresponding reqq. + */ + waitq = bfa_reqq(bfa, qid); + if (!list_empty(waitq)) + bfa_reqq_resume(bfa, qid); } void @@ -158,26 +173,27 @@ bfa_isr_unhandled(struct bfa_s *bfa, struct bfi_msg_s *m) } void -bfa_msix_rspq(struct bfa_s *bfa, int rsp_qid) +bfa_msix_rspq(struct bfa_s *bfa, int qid) { - struct bfi_msg_s *m; - u32 pi, ci; + struct bfi_msg_s *m; + u32 pi, ci; + struct list_head *waitq; - bfa_trc_fp(bfa, rsp_qid); + bfa_trc_fp(bfa, qid); - rsp_qid &= (BFI_IOC_MAX_CQS - 1); + qid &= (BFI_IOC_MAX_CQS - 1); - bfa->iocfc.hwif.hw_rspq_ack(bfa, rsp_qid); + bfa->iocfc.hwif.hw_rspq_ack(bfa, qid); - ci = bfa_rspq_ci(bfa, rsp_qid); - pi = bfa_rspq_pi(bfa, rsp_qid); + ci = bfa_rspq_ci(bfa, qid); + pi = bfa_rspq_pi(bfa, qid); bfa_trc_fp(bfa, ci); bfa_trc_fp(bfa, pi); if (bfa->rme_process) { while (ci != pi) { - m = bfa_rspq_elem(bfa, rsp_qid, ci); + m = bfa_rspq_elem(bfa, qid, ci); bfa_assert_fp(m->mhdr.msg_class < BFI_MC_MAX); bfa_isrs[m->mhdr.msg_class] (bfa, m); @@ -189,9 +205,16 @@ bfa_msix_rspq(struct bfa_s *bfa, int rsp_qid) /** * update CI */ - bfa_rspq_ci(bfa, rsp_qid) = pi; - bfa_reg_write(bfa->iocfc.bfa_regs.rme_q_ci[rsp_qid], pi); + bfa_rspq_ci(bfa, qid) = pi; + bfa_reg_write(bfa->iocfc.bfa_regs.rme_q_ci[qid], pi); bfa_os_mmiowb(); + + /** + * Resume any pending requests in the corresponding reqq. + */ + waitq = bfa_reqq(bfa, qid); + if (!list_empty(waitq)) + bfa_reqq_resume(bfa, qid); } void diff --git a/drivers/scsi/bfa/bfa_iocfc.c b/drivers/scsi/bfa/bfa_iocfc.c index 137591c984d7..a5551db6dba6 100644 --- a/drivers/scsi/bfa/bfa_iocfc.c +++ b/drivers/scsi/bfa/bfa_iocfc.c @@ -172,6 +172,7 @@ bfa_iocfc_init_mem(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, */ if (bfa_ioc_devid(&bfa->ioc) == BFA_PCI_DEVICE_ID_CT) { iocfc->hwif.hw_reginit = bfa_hwct_reginit; + iocfc->hwif.hw_reqq_ack = bfa_hwct_reqq_ack; iocfc->hwif.hw_rspq_ack = bfa_hwct_rspq_ack; iocfc->hwif.hw_msix_init = bfa_hwct_msix_init; iocfc->hwif.hw_msix_install = bfa_hwct_msix_install; @@ -180,6 +181,7 @@ bfa_iocfc_init_mem(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, iocfc->hwif.hw_msix_getvecs = bfa_hwct_msix_getvecs; } else { iocfc->hwif.hw_reginit = bfa_hwcb_reginit; + iocfc->hwif.hw_reqq_ack = bfa_hwcb_reqq_ack; iocfc->hwif.hw_rspq_ack = bfa_hwcb_rspq_ack; iocfc->hwif.hw_msix_init = bfa_hwcb_msix_init; iocfc->hwif.hw_msix_install = bfa_hwcb_msix_install; diff --git a/drivers/scsi/bfa/bfa_iocfc.h b/drivers/scsi/bfa/bfa_iocfc.h index ce9a830a4207..fbb4bdc9d600 100644 --- a/drivers/scsi/bfa/bfa_iocfc.h +++ b/drivers/scsi/bfa/bfa_iocfc.h @@ -54,6 +54,7 @@ struct bfa_msix_s { */ struct bfa_hwif_s { void (*hw_reginit)(struct bfa_s *bfa); + void (*hw_reqq_ack)(struct bfa_s *bfa, int reqq); void (*hw_rspq_ack)(struct bfa_s *bfa, int rspq); void (*hw_msix_init)(struct bfa_s *bfa, int nvecs); void (*hw_msix_install)(struct bfa_s *bfa); @@ -143,6 +144,7 @@ void bfa_msix_rspq(struct bfa_s *bfa, int vec); void bfa_msix_lpu_err(struct bfa_s *bfa, int vec); void bfa_hwcb_reginit(struct bfa_s *bfa); +void bfa_hwcb_reqq_ack(struct bfa_s *bfa, int rspq); void bfa_hwcb_rspq_ack(struct bfa_s *bfa, int rspq); void bfa_hwcb_msix_init(struct bfa_s *bfa, int nvecs); void bfa_hwcb_msix_install(struct bfa_s *bfa); @@ -151,6 +153,7 @@ void bfa_hwcb_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix); void bfa_hwcb_msix_getvecs(struct bfa_s *bfa, u32 *vecmap, u32 *nvecs, u32 *maxvec); void bfa_hwct_reginit(struct bfa_s *bfa); +void bfa_hwct_reqq_ack(struct bfa_s *bfa, int rspq); void bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq); void bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs); void bfa_hwct_msix_install(struct bfa_s *bfa); -- cgit v1.2.3 From 78f915f7b095dda76970c8c9568489fa779ef73f Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:37:18 -0800 Subject: [SCSI] bfa: In MSIX mode, ignore spurious RME interrupts when FCoE ports are in FW mismatch state. Use dummy interrupt handlers till chip initialization is complete. Install real interrupt handlers after chip initialization. Also removed msix installation code in bfa_iocfc_init(). Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_ioc_ct.c | 43 +++++++++++++++++-------------------------- drivers/scsi/bfa/bfa_iocfc.c | 1 - 2 files changed, 17 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_ioc_ct.c b/drivers/scsi/bfa/bfa_ioc_ct.c index 469da95aedf3..2431922c34a4 100644 --- a/drivers/scsi/bfa/bfa_ioc_ct.c +++ b/drivers/scsi/bfa/bfa_ioc_ct.c @@ -331,12 +331,12 @@ bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc) */ bfa_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg); - pll_sclk = __APP_PLL_312_ENABLE | __APP_PLL_312_LRESETN | - __APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(0U) | + pll_sclk = __APP_PLL_312_LRESETN | __APP_PLL_312_ENARST | + __APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(3U) | __APP_PLL_312_JITLMT0_1(3U) | __APP_PLL_312_CNTLMT0_1(1U); - pll_fclk = __APP_PLL_425_ENABLE | __APP_PLL_425_LRESETN | - __APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(0U) | + pll_fclk = __APP_PLL_425_LRESETN | __APP_PLL_425_ENARST | + __APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(3U) | __APP_PLL_425_JITLMT0_1(3U) | __APP_PLL_425_CNTLMT0_1(1U); @@ -366,36 +366,27 @@ bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc) bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); - bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, - __APP_PLL_312_LOGIC_SOFT_RESET); - bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, - __APP_PLL_312_BYPASS | - __APP_PLL_312_LOGIC_SOFT_RESET); - bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, - __APP_PLL_425_LOGIC_SOFT_RESET); - bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, - __APP_PLL_425_BYPASS | - __APP_PLL_425_LOGIC_SOFT_RESET); - bfa_os_udelay(2); - bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, - __APP_PLL_312_LOGIC_SOFT_RESET); - bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, - __APP_PLL_425_LOGIC_SOFT_RESET); - - bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, - pll_sclk | __APP_PLL_312_LOGIC_SOFT_RESET); - bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, - pll_fclk | __APP_PLL_425_LOGIC_SOFT_RESET); + bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk | + __APP_PLL_312_LOGIC_SOFT_RESET); + bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk | + __APP_PLL_425_LOGIC_SOFT_RESET); + bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk | + __APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE); + bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk | + __APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE); /** * Wait for PLLs to lock. */ + bfa_reg_read(rb + HOSTFN0_INT_MSK); bfa_os_udelay(2000); bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); - bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk); - bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk); + bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk | + __APP_PLL_312_ENABLE); + bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk | + __APP_PLL_425_ENABLE); bfa_reg_write((rb + MBIST_CTL_REG), __EDRAM_BISTR_START); bfa_os_udelay(1000); diff --git a/drivers/scsi/bfa/bfa_iocfc.c b/drivers/scsi/bfa/bfa_iocfc.c index a5551db6dba6..6677f83f2c99 100644 --- a/drivers/scsi/bfa/bfa_iocfc.c +++ b/drivers/scsi/bfa/bfa_iocfc.c @@ -659,7 +659,6 @@ bfa_iocfc_init(struct bfa_s *bfa) { bfa->iocfc.action = BFA_IOCFC_ACT_INIT; bfa_ioc_enable(&bfa->ioc); - bfa_msix_install(bfa); } /** -- cgit v1.2.3 From 13cc20c5e764e6ef8d57f33980ab8c386c25fb4d Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:37:29 -0800 Subject: [SCSI] bfa: IOC fixes, check for IOC down condition. Currently BFA was not checking for IOC down condition when issuing getstats/clearstats Add check to see if IOC is operational, before issuing getstats/clearstats. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_ioc.c | 11 ++++++++--- drivers/scsi/bfa/bfa_iocfc.c | 10 ++++++++++ 2 files changed, 18 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_ioc.c b/drivers/scsi/bfa/bfa_ioc.c index 2f09d17730cc..4d9a47ccffe9 100644 --- a/drivers/scsi/bfa/bfa_ioc.c +++ b/drivers/scsi/bfa/bfa_ioc.c @@ -1129,9 +1129,6 @@ bfa_ioc_download_fw(struct bfa_ioc_s *ioc, u32 boot_type, if (bfa_ioc_fwimg_get_size(ioc) < BFA_IOC_FWIMG_MINSZ) boot_type = BFI_BOOT_TYPE_FLASH; fwimg = bfa_ioc_fwimg_get_chunk(ioc, chunkno); - fwimg[BFI_BOOT_TYPE_OFF / sizeof(u32)] = bfa_os_swap32(boot_type); - fwimg[BFI_BOOT_PARAM_OFF / sizeof(u32)] = - bfa_os_swap32(boot_param); pgnum = bfa_ioc_smem_pgnum(ioc, loff); pgoff = bfa_ioc_smem_pgoff(ioc, loff); @@ -1166,6 +1163,14 @@ bfa_ioc_download_fw(struct bfa_ioc_s *ioc, u32 boot_type, bfa_reg_write(ioc->ioc_regs.host_page_num_fn, bfa_ioc_smem_pgnum(ioc, 0)); + + /* + * Set boot type and boot param at the end. + */ + bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_BOOT_TYPE_OFF, + bfa_os_swap32(boot_type)); + bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_BOOT_PARAM_OFF, + bfa_os_swap32(boot_param)); } static void diff --git a/drivers/scsi/bfa/bfa_iocfc.c b/drivers/scsi/bfa/bfa_iocfc.c index 6677f83f2c99..a76de2669bfc 100644 --- a/drivers/scsi/bfa/bfa_iocfc.c +++ b/drivers/scsi/bfa/bfa_iocfc.c @@ -801,6 +801,11 @@ bfa_iocfc_get_stats(struct bfa_s *bfa, struct bfa_iocfc_stats_s *stats, return BFA_STATUS_DEVBUSY; } + if (!bfa_iocfc_is_operational(bfa)) { + bfa_trc(bfa, 0); + return BFA_STATUS_IOC_NON_OP; + } + iocfc->stats_busy = BFA_TRUE; iocfc->stats_ret = stats; iocfc->stats_cbfn = cbfn; @@ -821,6 +826,11 @@ bfa_iocfc_clear_stats(struct bfa_s *bfa, bfa_cb_ioc_t cbfn, void *cbarg) return BFA_STATUS_DEVBUSY; } + if (!bfa_iocfc_is_operational(bfa)) { + bfa_trc(bfa, 0); + return BFA_STATUS_IOC_NON_OP; + } + iocfc->stats_busy = BFA_TRUE; iocfc->stats_cbfn = cbfn; iocfc->stats_cbarg = cbarg; -- cgit v1.2.3 From 1c8a4c37494932acd59079b4fc8d8f69fb329c2a Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:37:37 -0800 Subject: [SCSI] bfa: Rename pport to fcport in BFA FCS. Rename pport structures to fcport in BFA FCS, to resolve confusion about the port structures in the firmware, and make sure the SG page is setup correctly. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_fcport.c | 1570 +++++++++++++--------- drivers/scsi/bfa/bfa_fcs_port.c | 2 +- drivers/scsi/bfa/bfa_module.c | 4 +- drivers/scsi/bfa/bfa_modules_priv.h | 2 +- drivers/scsi/bfa/bfa_port_priv.h | 19 +- drivers/scsi/bfa/bfa_priv.h | 2 +- drivers/scsi/bfa/bfa_trcmod_priv.h | 2 +- drivers/scsi/bfa/bfad.c | 2 +- drivers/scsi/bfa/bfad_attr.c | 6 +- drivers/scsi/bfa/bfad_im.c | 2 +- drivers/scsi/bfa/fabric.c | 20 +- drivers/scsi/bfa/fdmi.c | 2 +- drivers/scsi/bfa/include/bfa_svc.h | 76 +- drivers/scsi/bfa/include/bfi/bfi_pport.h | 5 + drivers/scsi/bfa/include/cs/bfa_sm.h | 8 + drivers/scsi/bfa/include/defs/bfa_defs_ethport.h | 1 + drivers/scsi/bfa/include/defs/bfa_defs_fcport.h | 94 ++ drivers/scsi/bfa/include/defs/bfa_defs_iocfc.h | 1 + drivers/scsi/bfa/loop.c | 2 +- drivers/scsi/bfa/lport_api.c | 2 +- drivers/scsi/bfa/ms.c | 2 +- drivers/scsi/bfa/ns.c | 2 +- drivers/scsi/bfa/rport.c | 8 +- drivers/scsi/bfa/rport_api.c | 2 +- drivers/scsi/bfa/vport.c | 2 +- 25 files changed, 1103 insertions(+), 735 deletions(-) create mode 100644 drivers/scsi/bfa/include/defs/bfa_defs_fcport.h (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_fcport.c b/drivers/scsi/bfa/bfa_fcport.c index bdea7f0eb6bd..f392a7fa8c7f 100644 --- a/drivers/scsi/bfa/bfa_fcport.c +++ b/drivers/scsi/bfa/bfa_fcport.c @@ -23,34 +23,40 @@ #include #include -BFA_TRC_FILE(HAL, PPORT); -BFA_MODULE(pport); +BFA_TRC_FILE(HAL, FCPORT); +BFA_MODULE(fcport); /* * The port is considered disabled if corresponding physical port or IOC are * disabled explicitly */ #define BFA_PORT_IS_DISABLED(bfa) \ - ((bfa_pport_is_disabled(bfa) == BFA_TRUE) || \ + ((bfa_fcport_is_disabled(bfa) == BFA_TRUE) || \ (bfa_ioc_is_disabled(&bfa->ioc) == BFA_TRUE)) /* * forward declarations */ -static bfa_boolean_t bfa_pport_send_enable(struct bfa_pport_s *port); -static bfa_boolean_t bfa_pport_send_disable(struct bfa_pport_s *port); -static void bfa_pport_update_linkinfo(struct bfa_pport_s *pport); -static void bfa_pport_reset_linkinfo(struct bfa_pport_s *pport); -static void bfa_pport_set_wwns(struct bfa_pport_s *port); -static void __bfa_cb_port_event(void *cbarg, bfa_boolean_t complete); +static bfa_boolean_t bfa_fcport_send_enable(struct bfa_fcport_s *fcport); +static bfa_boolean_t bfa_fcport_send_disable(struct bfa_fcport_s *fcport); +static void bfa_fcport_update_linkinfo(struct bfa_fcport_s *fcport); +static void bfa_fcport_reset_linkinfo(struct bfa_fcport_s *fcport); +static void bfa_fcport_set_wwns(struct bfa_fcport_s *fcport); +static void __bfa_cb_fcport_event(void *cbarg, bfa_boolean_t complete); +static void bfa_fcport_callback(struct bfa_fcport_s *fcport, + enum bfa_pport_linkstate event); +static void bfa_fcport_queue_cb(struct bfa_fcport_ln_s *ln, + enum bfa_pport_linkstate event); +static void __bfa_cb_fcport_stats(void *cbarg, bfa_boolean_t complete); +static void __bfa_cb_fcport_stats_clr(void *cbarg, bfa_boolean_t complete); +static void bfa_fcport_stats_timeout(void *cbarg); +static void bfa_fcport_stats_clr_timeout(void *cbarg); + static void __bfa_cb_port_stats(void *cbarg, bfa_boolean_t complete); static void __bfa_cb_port_stats_clr(void *cbarg, bfa_boolean_t complete); static void bfa_port_stats_timeout(void *cbarg); static void bfa_port_stats_clr_timeout(void *cbarg); -static void bfa_pport_callback(struct bfa_pport_s *pport, - enum bfa_pport_linkstate event); -static void bfa_pport_queue_cb(struct bfa_pport_ln_s *ln, - enum bfa_pport_linkstate event); + /** * bfa_pport_private */ @@ -58,87 +64,86 @@ static void bfa_pport_queue_cb(struct bfa_pport_ln_s *ln, /** * BFA port state machine events */ -enum bfa_pport_sm_event { - BFA_PPORT_SM_START = 1, /* start port state machine */ - BFA_PPORT_SM_STOP = 2, /* stop port state machine */ - BFA_PPORT_SM_ENABLE = 3, /* enable port */ - BFA_PPORT_SM_DISABLE = 4, /* disable port state machine */ - BFA_PPORT_SM_FWRSP = 5, /* firmware enable/disable rsp */ - BFA_PPORT_SM_LINKUP = 6, /* firmware linkup event */ - BFA_PPORT_SM_LINKDOWN = 7, /* firmware linkup down */ - BFA_PPORT_SM_QRESUME = 8, /* CQ space available */ - BFA_PPORT_SM_HWFAIL = 9, /* IOC h/w failure */ +enum bfa_fcport_sm_event { + BFA_FCPORT_SM_START = 1, /* start port state machine */ + BFA_FCPORT_SM_STOP = 2, /* stop port state machine */ + BFA_FCPORT_SM_ENABLE = 3, /* enable port */ + BFA_FCPORT_SM_DISABLE = 4, /* disable port state machine */ + BFA_FCPORT_SM_FWRSP = 5, /* firmware enable/disable rsp */ + BFA_FCPORT_SM_LINKUP = 6, /* firmware linkup event */ + BFA_FCPORT_SM_LINKDOWN = 7, /* firmware linkup down */ + BFA_FCPORT_SM_QRESUME = 8, /* CQ space available */ + BFA_FCPORT_SM_HWFAIL = 9, /* IOC h/w failure */ }; /** * BFA port link notification state machine events */ -enum bfa_pport_ln_sm_event { - BFA_PPORT_LN_SM_LINKUP = 1, /* linkup event */ - BFA_PPORT_LN_SM_LINKDOWN = 2, /* linkdown event */ - BFA_PPORT_LN_SM_NOTIFICATION = 3 /* done notification */ +enum bfa_fcport_ln_sm_event { + BFA_FCPORT_LN_SM_LINKUP = 1, /* linkup event */ + BFA_FCPORT_LN_SM_LINKDOWN = 2, /* linkdown event */ + BFA_FCPORT_LN_SM_NOTIFICATION = 3 /* done notification */ }; -static void bfa_pport_sm_uninit(struct bfa_pport_s *pport, - enum bfa_pport_sm_event event); -static void bfa_pport_sm_enabling_qwait(struct bfa_pport_s *pport, - enum bfa_pport_sm_event event); -static void bfa_pport_sm_enabling(struct bfa_pport_s *pport, - enum bfa_pport_sm_event event); -static void bfa_pport_sm_linkdown(struct bfa_pport_s *pport, - enum bfa_pport_sm_event event); -static void bfa_pport_sm_linkup(struct bfa_pport_s *pport, - enum bfa_pport_sm_event event); -static void bfa_pport_sm_disabling(struct bfa_pport_s *pport, - enum bfa_pport_sm_event event); -static void bfa_pport_sm_disabling_qwait(struct bfa_pport_s *pport, - enum bfa_pport_sm_event event); -static void bfa_pport_sm_disabled(struct bfa_pport_s *pport, - enum bfa_pport_sm_event event); -static void bfa_pport_sm_stopped(struct bfa_pport_s *pport, - enum bfa_pport_sm_event event); -static void bfa_pport_sm_iocdown(struct bfa_pport_s *pport, - enum bfa_pport_sm_event event); -static void bfa_pport_sm_iocfail(struct bfa_pport_s *pport, - enum bfa_pport_sm_event event); - -static void bfa_pport_ln_sm_dn(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event); -static void bfa_pport_ln_sm_dn_nf(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event); -static void bfa_pport_ln_sm_dn_up_nf(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event); -static void bfa_pport_ln_sm_up(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event); -static void bfa_pport_ln_sm_up_nf(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event); -static void bfa_pport_ln_sm_up_dn_nf(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event); -static void bfa_pport_ln_sm_up_dn_up_nf(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event); +static void bfa_fcport_sm_uninit(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event); +static void bfa_fcport_sm_enabling_qwait(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event); +static void bfa_fcport_sm_enabling(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event); +static void bfa_fcport_sm_linkdown(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event); +static void bfa_fcport_sm_linkup(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event); +static void bfa_fcport_sm_disabling(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event); +static void bfa_fcport_sm_disabling_qwait(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event); +static void bfa_fcport_sm_disabled(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event); +static void bfa_fcport_sm_stopped(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event); +static void bfa_fcport_sm_iocdown(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event); +static void bfa_fcport_sm_iocfail(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event); + +static void bfa_fcport_ln_sm_dn(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event); +static void bfa_fcport_ln_sm_dn_nf(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event); +static void bfa_fcport_ln_sm_dn_up_nf(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event); +static void bfa_fcport_ln_sm_up(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event); +static void bfa_fcport_ln_sm_up_nf(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event); +static void bfa_fcport_ln_sm_up_dn_nf(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event); +static void bfa_fcport_ln_sm_up_dn_up_nf(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event); static struct bfa_sm_table_s hal_pport_sm_table[] = { - {BFA_SM(bfa_pport_sm_uninit), BFA_PPORT_ST_UNINIT}, - {BFA_SM(bfa_pport_sm_enabling_qwait), BFA_PPORT_ST_ENABLING_QWAIT}, - {BFA_SM(bfa_pport_sm_enabling), BFA_PPORT_ST_ENABLING}, - {BFA_SM(bfa_pport_sm_linkdown), BFA_PPORT_ST_LINKDOWN}, - {BFA_SM(bfa_pport_sm_linkup), BFA_PPORT_ST_LINKUP}, - {BFA_SM(bfa_pport_sm_disabling_qwait), - BFA_PPORT_ST_DISABLING_QWAIT}, - {BFA_SM(bfa_pport_sm_disabling), BFA_PPORT_ST_DISABLING}, - {BFA_SM(bfa_pport_sm_disabled), BFA_PPORT_ST_DISABLED}, - {BFA_SM(bfa_pport_sm_stopped), BFA_PPORT_ST_STOPPED}, - {BFA_SM(bfa_pport_sm_iocdown), BFA_PPORT_ST_IOCDOWN}, - {BFA_SM(bfa_pport_sm_iocfail), BFA_PPORT_ST_IOCDOWN}, + {BFA_SM(bfa_fcport_sm_uninit), BFA_PPORT_ST_UNINIT}, + {BFA_SM(bfa_fcport_sm_enabling_qwait), BFA_PPORT_ST_ENABLING_QWAIT}, + {BFA_SM(bfa_fcport_sm_enabling), BFA_PPORT_ST_ENABLING}, + {BFA_SM(bfa_fcport_sm_linkdown), BFA_PPORT_ST_LINKDOWN}, + {BFA_SM(bfa_fcport_sm_linkup), BFA_PPORT_ST_LINKUP}, + {BFA_SM(bfa_fcport_sm_disabling_qwait), BFA_PPORT_ST_DISABLING_QWAIT}, + {BFA_SM(bfa_fcport_sm_disabling), BFA_PPORT_ST_DISABLING}, + {BFA_SM(bfa_fcport_sm_disabled), BFA_PPORT_ST_DISABLED}, + {BFA_SM(bfa_fcport_sm_stopped), BFA_PPORT_ST_STOPPED}, + {BFA_SM(bfa_fcport_sm_iocdown), BFA_PPORT_ST_IOCDOWN}, + {BFA_SM(bfa_fcport_sm_iocfail), BFA_PPORT_ST_IOCDOWN}, }; static void -bfa_pport_aen_post(struct bfa_pport_s *pport, enum bfa_port_aen_event event) +bfa_fcport_aen_post(struct bfa_fcport_s *fcport, enum bfa_port_aen_event event) { union bfa_aen_data_u aen_data; - struct bfa_log_mod_s *logmod = pport->bfa->logm; - wwn_t pwwn = pport->pwwn; + struct bfa_log_mod_s *logmod = fcport->bfa->logm; + wwn_t pwwn = fcport->pwwn; char pwwn_ptr[BFA_STRING_32]; struct bfa_ioc_attr_s ioc_attr; @@ -167,28 +172,29 @@ bfa_pport_aen_post(struct bfa_pport_s *pport, enum bfa_port_aen_event event) break; } - bfa_ioc_get_attr(&pport->bfa->ioc, &ioc_attr); + bfa_ioc_get_attr(&fcport->bfa->ioc, &ioc_attr); aen_data.port.ioc_type = ioc_attr.ioc_type; aen_data.port.pwwn = pwwn; } static void -bfa_pport_sm_uninit(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) +bfa_fcport_sm_uninit(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event) { - bfa_trc(pport->bfa, event); + bfa_trc(fcport->bfa, event); switch (event) { - case BFA_PPORT_SM_START: + case BFA_FCPORT_SM_START: /** * Start event after IOC is configured and BFA is started. */ - if (bfa_pport_send_enable(pport)) - bfa_sm_set_state(pport, bfa_pport_sm_enabling); + if (bfa_fcport_send_enable(fcport)) + bfa_sm_set_state(fcport, bfa_fcport_sm_enabling); else - bfa_sm_set_state(pport, bfa_pport_sm_enabling_qwait); + bfa_sm_set_state(fcport, bfa_fcport_sm_enabling_qwait); break; - case BFA_PPORT_SM_ENABLE: + case BFA_FCPORT_SM_ENABLE: /** * Port is persistently configured to be in enabled state. Do * not change state. Port enabling is done when START event is @@ -196,389 +202,395 @@ bfa_pport_sm_uninit(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) */ break; - case BFA_PPORT_SM_DISABLE: + case BFA_FCPORT_SM_DISABLE: /** * If a port is persistently configured to be disabled, the * first event will a port disable request. */ - bfa_sm_set_state(pport, bfa_pport_sm_disabled); + bfa_sm_set_state(fcport, bfa_fcport_sm_disabled); break; - case BFA_PPORT_SM_HWFAIL: - bfa_sm_set_state(pport, bfa_pport_sm_iocdown); + case BFA_FCPORT_SM_HWFAIL: + bfa_sm_set_state(fcport, bfa_fcport_sm_iocdown); break; default: - bfa_sm_fault(pport->bfa, event); + bfa_sm_fault(fcport->bfa, event); } } static void -bfa_pport_sm_enabling_qwait(struct bfa_pport_s *pport, - enum bfa_pport_sm_event event) +bfa_fcport_sm_enabling_qwait(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event) { - bfa_trc(pport->bfa, event); + bfa_trc(fcport->bfa, event); switch (event) { - case BFA_PPORT_SM_QRESUME: - bfa_sm_set_state(pport, bfa_pport_sm_enabling); - bfa_pport_send_enable(pport); + case BFA_FCPORT_SM_QRESUME: + bfa_sm_set_state(fcport, bfa_fcport_sm_enabling); + bfa_fcport_send_enable(fcport); break; - case BFA_PPORT_SM_STOP: - bfa_reqq_wcancel(&pport->reqq_wait); - bfa_sm_set_state(pport, bfa_pport_sm_stopped); + case BFA_FCPORT_SM_STOP: + bfa_reqq_wcancel(&fcport->reqq_wait); + bfa_sm_set_state(fcport, bfa_fcport_sm_stopped); break; - case BFA_PPORT_SM_ENABLE: + case BFA_FCPORT_SM_ENABLE: /** * Already enable is in progress. */ break; - case BFA_PPORT_SM_DISABLE: + case BFA_FCPORT_SM_DISABLE: /** * Just send disable request to firmware when room becomes * available in request queue. */ - bfa_sm_set_state(pport, bfa_pport_sm_disabled); - bfa_reqq_wcancel(&pport->reqq_wait); - bfa_plog_str(pport->bfa->plog, BFA_PL_MID_HAL, + bfa_sm_set_state(fcport, bfa_fcport_sm_disabled); + bfa_reqq_wcancel(&fcport->reqq_wait); + bfa_plog_str(fcport->bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_PORT_DISABLE, 0, "Port Disable"); - bfa_pport_aen_post(pport, BFA_PORT_AEN_DISABLE); + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_DISABLE); break; - case BFA_PPORT_SM_LINKUP: - case BFA_PPORT_SM_LINKDOWN: + case BFA_FCPORT_SM_LINKUP: + case BFA_FCPORT_SM_LINKDOWN: /** * Possible to get link events when doing back-to-back * enable/disables. */ break; - case BFA_PPORT_SM_HWFAIL: - bfa_reqq_wcancel(&pport->reqq_wait); - bfa_sm_set_state(pport, bfa_pport_sm_iocdown); + case BFA_FCPORT_SM_HWFAIL: + bfa_reqq_wcancel(&fcport->reqq_wait); + bfa_sm_set_state(fcport, bfa_fcport_sm_iocdown); break; default: - bfa_sm_fault(pport->bfa, event); + bfa_sm_fault(fcport->bfa, event); } } static void -bfa_pport_sm_enabling(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) +bfa_fcport_sm_enabling(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event) { - bfa_trc(pport->bfa, event); + bfa_trc(fcport->bfa, event); switch (event) { - case BFA_PPORT_SM_FWRSP: - case BFA_PPORT_SM_LINKDOWN: - bfa_sm_set_state(pport, bfa_pport_sm_linkdown); + case BFA_FCPORT_SM_FWRSP: + case BFA_FCPORT_SM_LINKDOWN: + bfa_sm_set_state(fcport, bfa_fcport_sm_linkdown); break; - case BFA_PPORT_SM_LINKUP: - bfa_pport_update_linkinfo(pport); - bfa_sm_set_state(pport, bfa_pport_sm_linkup); + case BFA_FCPORT_SM_LINKUP: + bfa_fcport_update_linkinfo(fcport); + bfa_sm_set_state(fcport, bfa_fcport_sm_linkup); - bfa_assert(pport->event_cbfn); - bfa_pport_callback(pport, BFA_PPORT_LINKUP); + bfa_assert(fcport->event_cbfn); + bfa_fcport_callback(fcport, BFA_PPORT_LINKUP); break; - case BFA_PPORT_SM_ENABLE: + case BFA_FCPORT_SM_ENABLE: /** * Already being enabled. */ break; - case BFA_PPORT_SM_DISABLE: - if (bfa_pport_send_disable(pport)) - bfa_sm_set_state(pport, bfa_pport_sm_disabling); + case BFA_FCPORT_SM_DISABLE: + if (bfa_fcport_send_disable(fcport)) + bfa_sm_set_state(fcport, bfa_fcport_sm_disabling); else - bfa_sm_set_state(pport, bfa_pport_sm_disabling_qwait); + bfa_sm_set_state(fcport, bfa_fcport_sm_disabling_qwait); - bfa_plog_str(pport->bfa->plog, BFA_PL_MID_HAL, + bfa_plog_str(fcport->bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_PORT_DISABLE, 0, "Port Disable"); - bfa_pport_aen_post(pport, BFA_PORT_AEN_DISABLE); + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_DISABLE); break; - case BFA_PPORT_SM_STOP: - bfa_sm_set_state(pport, bfa_pport_sm_stopped); + case BFA_FCPORT_SM_STOP: + bfa_sm_set_state(fcport, bfa_fcport_sm_stopped); break; - case BFA_PPORT_SM_HWFAIL: - bfa_sm_set_state(pport, bfa_pport_sm_iocdown); + case BFA_FCPORT_SM_HWFAIL: + bfa_sm_set_state(fcport, bfa_fcport_sm_iocdown); break; default: - bfa_sm_fault(pport->bfa, event); + bfa_sm_fault(fcport->bfa, event); } } static void -bfa_pport_sm_linkdown(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) +bfa_fcport_sm_linkdown(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event) { - bfa_trc(pport->bfa, event); + bfa_trc(fcport->bfa, event); switch (event) { - case BFA_PPORT_SM_LINKUP: - bfa_pport_update_linkinfo(pport); - bfa_sm_set_state(pport, bfa_pport_sm_linkup); - bfa_assert(pport->event_cbfn); - bfa_plog_str(pport->bfa->plog, BFA_PL_MID_HAL, + case BFA_FCPORT_SM_LINKUP: + bfa_fcport_update_linkinfo(fcport); + bfa_sm_set_state(fcport, bfa_fcport_sm_linkup); + bfa_assert(fcport->event_cbfn); + bfa_plog_str(fcport->bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_PORT_ST_CHANGE, 0, "Port Linkup"); - bfa_pport_callback(pport, BFA_PPORT_LINKUP); - bfa_pport_aen_post(pport, BFA_PORT_AEN_ONLINE); + bfa_fcport_callback(fcport, BFA_PPORT_LINKUP); + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_ONLINE); /** * If QoS is enabled and it is not online, * Send a separate event. */ - if ((pport->cfg.qos_enabled) - && (bfa_os_ntohl(pport->qos_attr.state) != BFA_QOS_ONLINE)) - bfa_pport_aen_post(pport, BFA_PORT_AEN_QOS_NEG); + if ((fcport->cfg.qos_enabled) + && (bfa_os_ntohl(fcport->qos_attr.state) != BFA_QOS_ONLINE)) + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_QOS_NEG); break; - case BFA_PPORT_SM_LINKDOWN: + case BFA_FCPORT_SM_LINKDOWN: /** * Possible to get link down event. */ break; - case BFA_PPORT_SM_ENABLE: + case BFA_FCPORT_SM_ENABLE: /** * Already enabled. */ break; - case BFA_PPORT_SM_DISABLE: - if (bfa_pport_send_disable(pport)) - bfa_sm_set_state(pport, bfa_pport_sm_disabling); + case BFA_FCPORT_SM_DISABLE: + if (bfa_fcport_send_disable(fcport)) + bfa_sm_set_state(fcport, bfa_fcport_sm_disabling); else - bfa_sm_set_state(pport, bfa_pport_sm_disabling_qwait); + bfa_sm_set_state(fcport, bfa_fcport_sm_disabling_qwait); - bfa_plog_str(pport->bfa->plog, BFA_PL_MID_HAL, + bfa_plog_str(fcport->bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_PORT_DISABLE, 0, "Port Disable"); - bfa_pport_aen_post(pport, BFA_PORT_AEN_DISABLE); + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_DISABLE); break; - case BFA_PPORT_SM_STOP: - bfa_sm_set_state(pport, bfa_pport_sm_stopped); + case BFA_FCPORT_SM_STOP: + bfa_sm_set_state(fcport, bfa_fcport_sm_stopped); break; - case BFA_PPORT_SM_HWFAIL: - bfa_sm_set_state(pport, bfa_pport_sm_iocdown); + case BFA_FCPORT_SM_HWFAIL: + bfa_sm_set_state(fcport, bfa_fcport_sm_iocdown); break; default: - bfa_sm_fault(pport->bfa, event); + bfa_sm_fault(fcport->bfa, event); } } static void -bfa_pport_sm_linkup(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) +bfa_fcport_sm_linkup(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event) { - bfa_trc(pport->bfa, event); + bfa_trc(fcport->bfa, event); switch (event) { - case BFA_PPORT_SM_ENABLE: + case BFA_FCPORT_SM_ENABLE: /** * Already enabled. */ break; - case BFA_PPORT_SM_DISABLE: - if (bfa_pport_send_disable(pport)) - bfa_sm_set_state(pport, bfa_pport_sm_disabling); + case BFA_FCPORT_SM_DISABLE: + if (bfa_fcport_send_disable(fcport)) + bfa_sm_set_state(fcport, bfa_fcport_sm_disabling); else - bfa_sm_set_state(pport, bfa_pport_sm_disabling_qwait); + bfa_sm_set_state(fcport, bfa_fcport_sm_disabling_qwait); - bfa_pport_reset_linkinfo(pport); - bfa_pport_callback(pport, BFA_PPORT_LINKDOWN); - bfa_plog_str(pport->bfa->plog, BFA_PL_MID_HAL, + bfa_fcport_reset_linkinfo(fcport); + bfa_fcport_callback(fcport, BFA_PPORT_LINKDOWN); + bfa_plog_str(fcport->bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_PORT_DISABLE, 0, "Port Disable"); - bfa_pport_aen_post(pport, BFA_PORT_AEN_OFFLINE); - bfa_pport_aen_post(pport, BFA_PORT_AEN_DISABLE); + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_OFFLINE); + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_DISABLE); break; - case BFA_PPORT_SM_LINKDOWN: - bfa_sm_set_state(pport, bfa_pport_sm_linkdown); - bfa_pport_reset_linkinfo(pport); - bfa_pport_callback(pport, BFA_PPORT_LINKDOWN); - bfa_plog_str(pport->bfa->plog, BFA_PL_MID_HAL, + case BFA_FCPORT_SM_LINKDOWN: + bfa_sm_set_state(fcport, bfa_fcport_sm_linkdown); + bfa_fcport_reset_linkinfo(fcport); + bfa_fcport_callback(fcport, BFA_PPORT_LINKDOWN); + bfa_plog_str(fcport->bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_PORT_ST_CHANGE, 0, "Port Linkdown"); - if (BFA_PORT_IS_DISABLED(pport->bfa)) - bfa_pport_aen_post(pport, BFA_PORT_AEN_OFFLINE); + if (BFA_PORT_IS_DISABLED(fcport->bfa)) + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_OFFLINE); else - bfa_pport_aen_post(pport, BFA_PORT_AEN_DISCONNECT); + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_DISCONNECT); break; - case BFA_PPORT_SM_STOP: - bfa_sm_set_state(pport, bfa_pport_sm_stopped); - bfa_pport_reset_linkinfo(pport); - if (BFA_PORT_IS_DISABLED(pport->bfa)) - bfa_pport_aen_post(pport, BFA_PORT_AEN_OFFLINE); + case BFA_FCPORT_SM_STOP: + bfa_sm_set_state(fcport, bfa_fcport_sm_stopped); + bfa_fcport_reset_linkinfo(fcport); + if (BFA_PORT_IS_DISABLED(fcport->bfa)) + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_OFFLINE); else - bfa_pport_aen_post(pport, BFA_PORT_AEN_DISCONNECT); + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_DISCONNECT); break; - case BFA_PPORT_SM_HWFAIL: - bfa_sm_set_state(pport, bfa_pport_sm_iocdown); - bfa_pport_reset_linkinfo(pport); - bfa_pport_callback(pport, BFA_PPORT_LINKDOWN); - if (BFA_PORT_IS_DISABLED(pport->bfa)) - bfa_pport_aen_post(pport, BFA_PORT_AEN_OFFLINE); + case BFA_FCPORT_SM_HWFAIL: + bfa_sm_set_state(fcport, bfa_fcport_sm_iocdown); + bfa_fcport_reset_linkinfo(fcport); + bfa_fcport_callback(fcport, BFA_PPORT_LINKDOWN); + if (BFA_PORT_IS_DISABLED(fcport->bfa)) + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_OFFLINE); else - bfa_pport_aen_post(pport, BFA_PORT_AEN_DISCONNECT); + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_DISCONNECT); break; default: - bfa_sm_fault(pport->bfa, event); + bfa_sm_fault(fcport->bfa, event); } } static void -bfa_pport_sm_disabling_qwait(struct bfa_pport_s *pport, - enum bfa_pport_sm_event event) +bfa_fcport_sm_disabling_qwait(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event) { - bfa_trc(pport->bfa, event); + bfa_trc(fcport->bfa, event); switch (event) { - case BFA_PPORT_SM_QRESUME: - bfa_sm_set_state(pport, bfa_pport_sm_disabling); - bfa_pport_send_disable(pport); + case BFA_FCPORT_SM_QRESUME: + bfa_sm_set_state(fcport, bfa_fcport_sm_disabling); + bfa_fcport_send_disable(fcport); break; - case BFA_PPORT_SM_STOP: - bfa_sm_set_state(pport, bfa_pport_sm_stopped); - bfa_reqq_wcancel(&pport->reqq_wait); + case BFA_FCPORT_SM_STOP: + bfa_sm_set_state(fcport, bfa_fcport_sm_stopped); + bfa_reqq_wcancel(&fcport->reqq_wait); break; - case BFA_PPORT_SM_DISABLE: + case BFA_FCPORT_SM_DISABLE: /** * Already being disabled. */ break; - case BFA_PPORT_SM_LINKUP: - case BFA_PPORT_SM_LINKDOWN: + case BFA_FCPORT_SM_LINKUP: + case BFA_FCPORT_SM_LINKDOWN: /** * Possible to get link events when doing back-to-back * enable/disables. */ break; - case BFA_PPORT_SM_HWFAIL: - bfa_sm_set_state(pport, bfa_pport_sm_iocfail); - bfa_reqq_wcancel(&pport->reqq_wait); + case BFA_FCPORT_SM_HWFAIL: + bfa_sm_set_state(fcport, bfa_fcport_sm_iocfail); + bfa_reqq_wcancel(&fcport->reqq_wait); break; default: - bfa_sm_fault(pport->bfa, event); + bfa_sm_fault(fcport->bfa, event); } } static void -bfa_pport_sm_disabling(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) +bfa_fcport_sm_disabling(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event) { - bfa_trc(pport->bfa, event); + bfa_trc(fcport->bfa, event); switch (event) { - case BFA_PPORT_SM_FWRSP: - bfa_sm_set_state(pport, bfa_pport_sm_disabled); + case BFA_FCPORT_SM_FWRSP: + bfa_sm_set_state(fcport, bfa_fcport_sm_disabled); break; - case BFA_PPORT_SM_DISABLE: + case BFA_FCPORT_SM_DISABLE: /** * Already being disabled. */ break; - case BFA_PPORT_SM_ENABLE: - if (bfa_pport_send_enable(pport)) - bfa_sm_set_state(pport, bfa_pport_sm_enabling); + case BFA_FCPORT_SM_ENABLE: + if (bfa_fcport_send_enable(fcport)) + bfa_sm_set_state(fcport, bfa_fcport_sm_enabling); else - bfa_sm_set_state(pport, bfa_pport_sm_enabling_qwait); + bfa_sm_set_state(fcport, bfa_fcport_sm_enabling_qwait); - bfa_plog_str(pport->bfa->plog, BFA_PL_MID_HAL, + bfa_plog_str(fcport->bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_PORT_ENABLE, 0, "Port Enable"); - bfa_pport_aen_post(pport, BFA_PORT_AEN_ENABLE); + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_ENABLE); break; - case BFA_PPORT_SM_STOP: - bfa_sm_set_state(pport, bfa_pport_sm_stopped); + case BFA_FCPORT_SM_STOP: + bfa_sm_set_state(fcport, bfa_fcport_sm_stopped); break; - case BFA_PPORT_SM_LINKUP: - case BFA_PPORT_SM_LINKDOWN: + case BFA_FCPORT_SM_LINKUP: + case BFA_FCPORT_SM_LINKDOWN: /** * Possible to get link events when doing back-to-back * enable/disables. */ break; - case BFA_PPORT_SM_HWFAIL: - bfa_sm_set_state(pport, bfa_pport_sm_iocfail); + case BFA_FCPORT_SM_HWFAIL: + bfa_sm_set_state(fcport, bfa_fcport_sm_iocfail); break; default: - bfa_sm_fault(pport->bfa, event); + bfa_sm_fault(fcport->bfa, event); } } static void -bfa_pport_sm_disabled(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) +bfa_fcport_sm_disabled(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event) { - bfa_trc(pport->bfa, event); + bfa_trc(fcport->bfa, event); switch (event) { - case BFA_PPORT_SM_START: + case BFA_FCPORT_SM_START: /** * Ignore start event for a port that is disabled. */ break; - case BFA_PPORT_SM_STOP: - bfa_sm_set_state(pport, bfa_pport_sm_stopped); + case BFA_FCPORT_SM_STOP: + bfa_sm_set_state(fcport, bfa_fcport_sm_stopped); break; - case BFA_PPORT_SM_ENABLE: - if (bfa_pport_send_enable(pport)) - bfa_sm_set_state(pport, bfa_pport_sm_enabling); + case BFA_FCPORT_SM_ENABLE: + if (bfa_fcport_send_enable(fcport)) + bfa_sm_set_state(fcport, bfa_fcport_sm_enabling); else - bfa_sm_set_state(pport, bfa_pport_sm_enabling_qwait); + bfa_sm_set_state(fcport, bfa_fcport_sm_enabling_qwait); - bfa_plog_str(pport->bfa->plog, BFA_PL_MID_HAL, + bfa_plog_str(fcport->bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_PORT_ENABLE, 0, "Port Enable"); - bfa_pport_aen_post(pport, BFA_PORT_AEN_ENABLE); + bfa_fcport_aen_post(fcport, BFA_PORT_AEN_ENABLE); break; - case BFA_PPORT_SM_DISABLE: + case BFA_FCPORT_SM_DISABLE: /** * Already disabled. */ break; - case BFA_PPORT_SM_HWFAIL: - bfa_sm_set_state(pport, bfa_pport_sm_iocfail); + case BFA_FCPORT_SM_HWFAIL: + bfa_sm_set_state(fcport, bfa_fcport_sm_iocfail); break; default: - bfa_sm_fault(pport->bfa, event); + bfa_sm_fault(fcport->bfa, event); } } static void -bfa_pport_sm_stopped(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) +bfa_fcport_sm_stopped(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event) { - bfa_trc(pport->bfa, event); + bfa_trc(fcport->bfa, event); switch (event) { - case BFA_PPORT_SM_START: - if (bfa_pport_send_enable(pport)) - bfa_sm_set_state(pport, bfa_pport_sm_enabling); + case BFA_FCPORT_SM_START: + if (bfa_fcport_send_enable(fcport)) + bfa_sm_set_state(fcport, bfa_fcport_sm_enabling); else - bfa_sm_set_state(pport, bfa_pport_sm_enabling_qwait); + bfa_sm_set_state(fcport, bfa_fcport_sm_enabling_qwait); break; default: @@ -593,16 +605,17 @@ bfa_pport_sm_stopped(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) * Port is enabled. IOC is down/failed. */ static void -bfa_pport_sm_iocdown(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) +bfa_fcport_sm_iocdown(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event) { - bfa_trc(pport->bfa, event); + bfa_trc(fcport->bfa, event); switch (event) { - case BFA_PPORT_SM_START: - if (bfa_pport_send_enable(pport)) - bfa_sm_set_state(pport, bfa_pport_sm_enabling); + case BFA_FCPORT_SM_START: + if (bfa_fcport_send_enable(fcport)) + bfa_sm_set_state(fcport, bfa_fcport_sm_enabling); else - bfa_sm_set_state(pport, bfa_pport_sm_enabling_qwait); + bfa_sm_set_state(fcport, bfa_fcport_sm_enabling_qwait); break; default: @@ -617,17 +630,18 @@ bfa_pport_sm_iocdown(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) * Port is disabled. IOC is down/failed. */ static void -bfa_pport_sm_iocfail(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) +bfa_fcport_sm_iocfail(struct bfa_fcport_s *fcport, + enum bfa_fcport_sm_event event) { - bfa_trc(pport->bfa, event); + bfa_trc(fcport->bfa, event); switch (event) { - case BFA_PPORT_SM_START: - bfa_sm_set_state(pport, bfa_pport_sm_disabled); + case BFA_FCPORT_SM_START: + bfa_sm_set_state(fcport, bfa_fcport_sm_disabled); break; - case BFA_PPORT_SM_ENABLE: - bfa_sm_set_state(pport, bfa_pport_sm_iocdown); + case BFA_FCPORT_SM_ENABLE: + bfa_sm_set_state(fcport, bfa_fcport_sm_iocdown); break; default: @@ -642,19 +656,19 @@ bfa_pport_sm_iocfail(struct bfa_pport_s *pport, enum bfa_pport_sm_event event) * Link state is down */ static void -bfa_pport_ln_sm_dn(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event) +bfa_fcport_ln_sm_dn(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event) { - bfa_trc(ln->pport->bfa, event); + bfa_trc(ln->fcport->bfa, event); switch (event) { - case BFA_PPORT_LN_SM_LINKUP: - bfa_sm_set_state(ln, bfa_pport_ln_sm_up_nf); - bfa_pport_queue_cb(ln, BFA_PPORT_LINKUP); + case BFA_FCPORT_LN_SM_LINKUP: + bfa_sm_set_state(ln, bfa_fcport_ln_sm_up_nf); + bfa_fcport_queue_cb(ln, BFA_PPORT_LINKUP); break; default: - bfa_sm_fault(ln->pport->bfa, event); + bfa_sm_fault(ln->fcport->bfa, event); } } @@ -662,22 +676,22 @@ bfa_pport_ln_sm_dn(struct bfa_pport_ln_s *ln, * Link state is waiting for down notification */ static void -bfa_pport_ln_sm_dn_nf(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event) +bfa_fcport_ln_sm_dn_nf(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event) { - bfa_trc(ln->pport->bfa, event); + bfa_trc(ln->fcport->bfa, event); switch (event) { - case BFA_PPORT_LN_SM_LINKUP: - bfa_sm_set_state(ln, bfa_pport_ln_sm_dn_up_nf); + case BFA_FCPORT_LN_SM_LINKUP: + bfa_sm_set_state(ln, bfa_fcport_ln_sm_dn_up_nf); break; - case BFA_PPORT_LN_SM_NOTIFICATION: - bfa_sm_set_state(ln, bfa_pport_ln_sm_dn); + case BFA_FCPORT_LN_SM_NOTIFICATION: + bfa_sm_set_state(ln, bfa_fcport_ln_sm_dn); break; default: - bfa_sm_fault(ln->pport->bfa, event); + bfa_sm_fault(ln->fcport->bfa, event); } } @@ -685,23 +699,23 @@ bfa_pport_ln_sm_dn_nf(struct bfa_pport_ln_s *ln, * Link state is waiting for down notification and there is a pending up */ static void -bfa_pport_ln_sm_dn_up_nf(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event) +bfa_fcport_ln_sm_dn_up_nf(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event) { - bfa_trc(ln->pport->bfa, event); + bfa_trc(ln->fcport->bfa, event); switch (event) { - case BFA_PPORT_LN_SM_LINKDOWN: - bfa_sm_set_state(ln, bfa_pport_ln_sm_dn_nf); + case BFA_FCPORT_LN_SM_LINKDOWN: + bfa_sm_set_state(ln, bfa_fcport_ln_sm_dn_nf); break; - case BFA_PPORT_LN_SM_NOTIFICATION: - bfa_sm_set_state(ln, bfa_pport_ln_sm_up_nf); - bfa_pport_queue_cb(ln, BFA_PPORT_LINKUP); + case BFA_FCPORT_LN_SM_NOTIFICATION: + bfa_sm_set_state(ln, bfa_fcport_ln_sm_up_nf); + bfa_fcport_queue_cb(ln, BFA_PPORT_LINKUP); break; default: - bfa_sm_fault(ln->pport->bfa, event); + bfa_sm_fault(ln->fcport->bfa, event); } } @@ -709,19 +723,19 @@ bfa_pport_ln_sm_dn_up_nf(struct bfa_pport_ln_s *ln, * Link state is up */ static void -bfa_pport_ln_sm_up(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event) +bfa_fcport_ln_sm_up(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event) { - bfa_trc(ln->pport->bfa, event); + bfa_trc(ln->fcport->bfa, event); switch (event) { - case BFA_PPORT_LN_SM_LINKDOWN: - bfa_sm_set_state(ln, bfa_pport_ln_sm_dn_nf); - bfa_pport_queue_cb(ln, BFA_PPORT_LINKDOWN); + case BFA_FCPORT_LN_SM_LINKDOWN: + bfa_sm_set_state(ln, bfa_fcport_ln_sm_dn_nf); + bfa_fcport_queue_cb(ln, BFA_PPORT_LINKDOWN); break; default: - bfa_sm_fault(ln->pport->bfa, event); + bfa_sm_fault(ln->fcport->bfa, event); } } @@ -729,22 +743,22 @@ bfa_pport_ln_sm_up(struct bfa_pport_ln_s *ln, * Link state is waiting for up notification */ static void -bfa_pport_ln_sm_up_nf(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event) +bfa_fcport_ln_sm_up_nf(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event) { - bfa_trc(ln->pport->bfa, event); + bfa_trc(ln->fcport->bfa, event); switch (event) { - case BFA_PPORT_LN_SM_LINKDOWN: - bfa_sm_set_state(ln, bfa_pport_ln_sm_up_dn_nf); + case BFA_FCPORT_LN_SM_LINKDOWN: + bfa_sm_set_state(ln, bfa_fcport_ln_sm_up_dn_nf); break; - case BFA_PPORT_LN_SM_NOTIFICATION: - bfa_sm_set_state(ln, bfa_pport_ln_sm_up); + case BFA_FCPORT_LN_SM_NOTIFICATION: + bfa_sm_set_state(ln, bfa_fcport_ln_sm_up); break; default: - bfa_sm_fault(ln->pport->bfa, event); + bfa_sm_fault(ln->fcport->bfa, event); } } @@ -752,23 +766,23 @@ bfa_pport_ln_sm_up_nf(struct bfa_pport_ln_s *ln, * Link state is waiting for up notification and there is a pending down */ static void -bfa_pport_ln_sm_up_dn_nf(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event) +bfa_fcport_ln_sm_up_dn_nf(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event) { - bfa_trc(ln->pport->bfa, event); + bfa_trc(ln->fcport->bfa, event); switch (event) { - case BFA_PPORT_LN_SM_LINKUP: - bfa_sm_set_state(ln, bfa_pport_ln_sm_up_dn_up_nf); + case BFA_FCPORT_LN_SM_LINKUP: + bfa_sm_set_state(ln, bfa_fcport_ln_sm_up_dn_up_nf); break; - case BFA_PPORT_LN_SM_NOTIFICATION: - bfa_sm_set_state(ln, bfa_pport_ln_sm_dn_nf); - bfa_pport_queue_cb(ln, BFA_PPORT_LINKDOWN); + case BFA_FCPORT_LN_SM_NOTIFICATION: + bfa_sm_set_state(ln, bfa_fcport_ln_sm_dn_nf); + bfa_fcport_queue_cb(ln, BFA_PPORT_LINKDOWN); break; default: - bfa_sm_fault(ln->pport->bfa, event); + bfa_sm_fault(ln->fcport->bfa, event); } } @@ -776,23 +790,23 @@ bfa_pport_ln_sm_up_dn_nf(struct bfa_pport_ln_s *ln, * Link state is waiting for up notification and there are pending down and up */ static void -bfa_pport_ln_sm_up_dn_up_nf(struct bfa_pport_ln_s *ln, - enum bfa_pport_ln_sm_event event) +bfa_fcport_ln_sm_up_dn_up_nf(struct bfa_fcport_ln_s *ln, + enum bfa_fcport_ln_sm_event event) { - bfa_trc(ln->pport->bfa, event); + bfa_trc(ln->fcport->bfa, event); switch (event) { - case BFA_PPORT_LN_SM_LINKDOWN: - bfa_sm_set_state(ln, bfa_pport_ln_sm_up_dn_nf); + case BFA_FCPORT_LN_SM_LINKDOWN: + bfa_sm_set_state(ln, bfa_fcport_ln_sm_up_dn_nf); break; - case BFA_PPORT_LN_SM_NOTIFICATION: - bfa_sm_set_state(ln, bfa_pport_ln_sm_dn_up_nf); - bfa_pport_queue_cb(ln, BFA_PPORT_LINKDOWN); + case BFA_FCPORT_LN_SM_NOTIFICATION: + bfa_sm_set_state(ln, bfa_fcport_ln_sm_dn_up_nf); + bfa_fcport_queue_cb(ln, BFA_PPORT_LINKDOWN); break; default: - bfa_sm_fault(ln->pport->bfa, event); + bfa_sm_fault(ln->fcport->bfa, event); } } @@ -801,36 +815,40 @@ bfa_pport_ln_sm_up_dn_up_nf(struct bfa_pport_ln_s *ln, */ static void -__bfa_cb_port_event(void *cbarg, bfa_boolean_t complete) +__bfa_cb_fcport_event(void *cbarg, bfa_boolean_t complete) { - struct bfa_pport_ln_s *ln = cbarg; + struct bfa_fcport_ln_s *ln = cbarg; if (complete) - ln->pport->event_cbfn(ln->pport->event_cbarg, ln->ln_event); + ln->fcport->event_cbfn(ln->fcport->event_cbarg, ln->ln_event); else - bfa_sm_send_event(ln, BFA_PPORT_LN_SM_NOTIFICATION); + bfa_sm_send_event(ln, BFA_FCPORT_LN_SM_NOTIFICATION); } -#define PPORT_STATS_DMA_SZ (BFA_ROUNDUP(sizeof(union bfa_pport_stats_u), \ +#define PPORT_STATS_DMA_SZ (BFA_ROUNDUP(sizeof(union bfa_fcport_stats_u), \ + BFA_CACHELINE_SZ)) + +#define FCPORT_STATS_DMA_SZ (BFA_ROUNDUP(sizeof(union bfa_fcport_stats_u), \ BFA_CACHELINE_SZ)) static void -bfa_pport_meminfo(struct bfa_iocfc_cfg_s *cfg, u32 *ndm_len, +bfa_fcport_meminfo(struct bfa_iocfc_cfg_s *cfg, u32 *ndm_len, u32 *dm_len) { *dm_len += PPORT_STATS_DMA_SZ; + *dm_len += PPORT_STATS_DMA_SZ; } static void -bfa_pport_qresume(void *cbarg) +bfa_fcport_qresume(void *cbarg) { - struct bfa_pport_s *port = cbarg; + struct bfa_fcport_s *port = cbarg; - bfa_sm_send_event(port, BFA_PPORT_SM_QRESUME); + bfa_sm_send_event(port, BFA_FCPORT_SM_QRESUME); } static void -bfa_pport_mem_claim(struct bfa_pport_s *pport, struct bfa_meminfo_s *meminfo) +bfa_fcport_mem_claim(struct bfa_fcport_s *fcport, struct bfa_meminfo_s *meminfo) { u8 *dm_kva; u64 dm_pa; @@ -838,13 +856,22 @@ bfa_pport_mem_claim(struct bfa_pport_s *pport, struct bfa_meminfo_s *meminfo) dm_kva = bfa_meminfo_dma_virt(meminfo); dm_pa = bfa_meminfo_dma_phys(meminfo); - pport->stats_kva = dm_kva; - pport->stats_pa = dm_pa; - pport->stats = (union bfa_pport_stats_u *)dm_kva; + fcport->stats_kva = dm_kva; + fcport->stats_pa = dm_pa; + fcport->stats = (union bfa_pport_stats_u *)dm_kva; dm_kva += PPORT_STATS_DMA_SZ; dm_pa += PPORT_STATS_DMA_SZ; + /* FC port stats */ + + fcport->fcport_stats_kva = dm_kva; + fcport->fcport_stats_pa = dm_pa; + fcport->fcport_stats = (union bfa_fcport_stats_u *) dm_kva; + + dm_kva += FCPORT_STATS_DMA_SZ; + dm_pa += FCPORT_STATS_DMA_SZ; + bfa_meminfo_dma_virt(meminfo) = dm_kva; bfa_meminfo_dma_phys(meminfo) = dm_pa; } @@ -853,21 +880,21 @@ bfa_pport_mem_claim(struct bfa_pport_s *pport, struct bfa_meminfo_s *meminfo) * Memory initialization. */ static void -bfa_pport_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, +bfa_fcport_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, struct bfa_meminfo_s *meminfo, struct bfa_pcidev_s *pcidev) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); - struct bfa_pport_cfg_s *port_cfg = &pport->cfg; - struct bfa_pport_ln_s *ln = &pport->ln; + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); + struct bfa_pport_cfg_s *port_cfg = &fcport->cfg; + struct bfa_fcport_ln_s *ln = &fcport->ln; - bfa_os_memset(pport, 0, sizeof(struct bfa_pport_s)); - pport->bfa = bfa; - ln->pport = pport; + bfa_os_memset(fcport, 0, sizeof(struct bfa_fcport_s)); + fcport->bfa = bfa; + ln->fcport = fcport; - bfa_pport_mem_claim(pport, meminfo); + bfa_fcport_mem_claim(fcport, meminfo); - bfa_sm_set_state(pport, bfa_pport_sm_uninit); - bfa_sm_set_state(ln, bfa_pport_ln_sm_dn); + bfa_sm_set_state(fcport, bfa_fcport_sm_uninit); + bfa_sm_set_state(ln, bfa_fcport_ln_sm_dn); /** * initialize and set default configuration @@ -879,30 +906,30 @@ bfa_pport_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, port_cfg->trl_def_speed = BFA_PPORT_SPEED_1GBPS; - bfa_reqq_winit(&pport->reqq_wait, bfa_pport_qresume, pport); + bfa_reqq_winit(&fcport->reqq_wait, bfa_fcport_qresume, fcport); } static void -bfa_pport_initdone(struct bfa_s *bfa) +bfa_fcport_initdone(struct bfa_s *bfa) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); /** * Initialize port attributes from IOC hardware data. */ - bfa_pport_set_wwns(pport); - if (pport->cfg.maxfrsize == 0) - pport->cfg.maxfrsize = bfa_ioc_maxfrsize(&bfa->ioc); - pport->cfg.rx_bbcredit = bfa_ioc_rx_bbcredit(&bfa->ioc); - pport->speed_sup = bfa_ioc_speed_sup(&bfa->ioc); + bfa_fcport_set_wwns(fcport); + if (fcport->cfg.maxfrsize == 0) + fcport->cfg.maxfrsize = bfa_ioc_maxfrsize(&bfa->ioc); + fcport->cfg.rx_bbcredit = bfa_ioc_rx_bbcredit(&bfa->ioc); + fcport->speed_sup = bfa_ioc_speed_sup(&bfa->ioc); - bfa_assert(pport->cfg.maxfrsize); - bfa_assert(pport->cfg.rx_bbcredit); - bfa_assert(pport->speed_sup); + bfa_assert(fcport->cfg.maxfrsize); + bfa_assert(fcport->cfg.rx_bbcredit); + bfa_assert(fcport->speed_sup); } static void -bfa_pport_detach(struct bfa_s *bfa) +bfa_fcport_detach(struct bfa_s *bfa) { } @@ -910,62 +937,63 @@ bfa_pport_detach(struct bfa_s *bfa) * Called when IOC is ready. */ static void -bfa_pport_start(struct bfa_s *bfa) +bfa_fcport_start(struct bfa_s *bfa) { - bfa_sm_send_event(BFA_PORT_MOD(bfa), BFA_PPORT_SM_START); + bfa_sm_send_event(BFA_FCPORT_MOD(bfa), BFA_FCPORT_SM_START); } /** * Called before IOC is stopped. */ static void -bfa_pport_stop(struct bfa_s *bfa) +bfa_fcport_stop(struct bfa_s *bfa) { - bfa_sm_send_event(BFA_PORT_MOD(bfa), BFA_PPORT_SM_STOP); + bfa_sm_send_event(BFA_FCPORT_MOD(bfa), BFA_FCPORT_SM_STOP); } /** * Called when IOC failure is detected. */ static void -bfa_pport_iocdisable(struct bfa_s *bfa) +bfa_fcport_iocdisable(struct bfa_s *bfa) { - bfa_sm_send_event(BFA_PORT_MOD(bfa), BFA_PPORT_SM_HWFAIL); + bfa_sm_send_event(BFA_FCPORT_MOD(bfa), BFA_FCPORT_SM_HWFAIL); } static void -bfa_pport_update_linkinfo(struct bfa_pport_s *pport) +bfa_fcport_update_linkinfo(struct bfa_fcport_s *fcport) { - struct bfi_pport_event_s *pevent = pport->event_arg.i2hmsg.event; + struct bfi_pport_event_s *pevent = fcport->event_arg.i2hmsg.event; - pport->speed = pevent->link_state.speed; - pport->topology = pevent->link_state.topology; + fcport->speed = pevent->link_state.speed; + fcport->topology = pevent->link_state.topology; - if (pport->topology == BFA_PPORT_TOPOLOGY_LOOP) - pport->myalpa = pevent->link_state.tl.loop_info.myalpa; + if (fcport->topology == BFA_PPORT_TOPOLOGY_LOOP) + fcport->myalpa = + pevent->link_state.tl.loop_info.myalpa; /* * QoS Details */ - bfa_os_assign(pport->qos_attr, pevent->link_state.qos_attr); - bfa_os_assign(pport->qos_vc_attr, pevent->link_state.qos_vc_attr); + bfa_os_assign(fcport->qos_attr, pevent->link_state.qos_attr); + bfa_os_assign(fcport->qos_vc_attr, pevent->link_state.qos_vc_attr); - bfa_trc(pport->bfa, pport->speed); - bfa_trc(pport->bfa, pport->topology); + bfa_trc(fcport->bfa, fcport->speed); + bfa_trc(fcport->bfa, fcport->topology); } static void -bfa_pport_reset_linkinfo(struct bfa_pport_s *pport) +bfa_fcport_reset_linkinfo(struct bfa_fcport_s *fcport) { - pport->speed = BFA_PPORT_SPEED_UNKNOWN; - pport->topology = BFA_PPORT_TOPOLOGY_NONE; + fcport->speed = BFA_PPORT_SPEED_UNKNOWN; + fcport->topology = BFA_PPORT_TOPOLOGY_NONE; } /** * Send port enable message to firmware. */ static bfa_boolean_t -bfa_pport_send_enable(struct bfa_pport_s *port) +bfa_fcport_send_enable(struct bfa_fcport_s *fcport) { struct bfi_pport_enable_req_s *m; @@ -973,32 +1001,34 @@ bfa_pport_send_enable(struct bfa_pport_s *port) * Increment message tag before queue check, so that responses to old * requests are discarded. */ - port->msgtag++; + fcport->msgtag++; /** * check for room in queue to send request now */ - m = bfa_reqq_next(port->bfa, BFA_REQQ_PORT); + m = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); if (!m) { - bfa_reqq_wait(port->bfa, BFA_REQQ_PORT, &port->reqq_wait); + bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, + &fcport->reqq_wait); return BFA_FALSE; } bfi_h2i_set(m->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_ENABLE_REQ, - bfa_lpuid(port->bfa)); - m->nwwn = port->nwwn; - m->pwwn = port->pwwn; - m->port_cfg = port->cfg; - m->msgtag = port->msgtag; - m->port_cfg.maxfrsize = bfa_os_htons(port->cfg.maxfrsize); - bfa_dma_be_addr_set(m->stats_dma_addr, port->stats_pa); - bfa_trc(port->bfa, m->stats_dma_addr.a32.addr_lo); - bfa_trc(port->bfa, m->stats_dma_addr.a32.addr_hi); + bfa_lpuid(fcport->bfa)); + m->nwwn = fcport->nwwn; + m->pwwn = fcport->pwwn; + m->port_cfg = fcport->cfg; + m->msgtag = fcport->msgtag; + m->port_cfg.maxfrsize = bfa_os_htons(fcport->cfg.maxfrsize); + bfa_dma_be_addr_set(m->stats_dma_addr, fcport->stats_pa); + bfa_dma_be_addr_set(m->fcport_stats_dma_addr, fcport->fcport_stats_pa); + bfa_trc(fcport->bfa, m->stats_dma_addr.a32.addr_lo); + bfa_trc(fcport->bfa, m->stats_dma_addr.a32.addr_hi); /** * queue I/O message to firmware */ - bfa_reqq_produce(port->bfa, BFA_REQQ_PORT); + bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); return BFA_TRUE; } @@ -1006,7 +1036,7 @@ bfa_pport_send_enable(struct bfa_pport_s *port) * Send port disable message to firmware. */ static bfa_boolean_t -bfa_pport_send_disable(struct bfa_pport_s *port) +bfa_fcport_send_disable(struct bfa_fcport_s *fcport) { bfi_pport_disable_req_t *m; @@ -1014,63 +1044,64 @@ bfa_pport_send_disable(struct bfa_pport_s *port) * Increment message tag before queue check, so that responses to old * requests are discarded. */ - port->msgtag++; + fcport->msgtag++; /** * check for room in queue to send request now */ - m = bfa_reqq_next(port->bfa, BFA_REQQ_PORT); + m = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); if (!m) { - bfa_reqq_wait(port->bfa, BFA_REQQ_PORT, &port->reqq_wait); + bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, + &fcport->reqq_wait); return BFA_FALSE; } bfi_h2i_set(m->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_DISABLE_REQ, - bfa_lpuid(port->bfa)); - m->msgtag = port->msgtag; + bfa_lpuid(fcport->bfa)); + m->msgtag = fcport->msgtag; /** * queue I/O message to firmware */ - bfa_reqq_produce(port->bfa, BFA_REQQ_PORT); + bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); return BFA_TRUE; } static void -bfa_pport_set_wwns(struct bfa_pport_s *port) +bfa_fcport_set_wwns(struct bfa_fcport_s *fcport) { - port->pwwn = bfa_ioc_get_pwwn(&port->bfa->ioc); - port->nwwn = bfa_ioc_get_nwwn(&port->bfa->ioc); + fcport->pwwn = bfa_ioc_get_pwwn(&fcport->bfa->ioc); + fcport->nwwn = bfa_ioc_get_nwwn(&fcport->bfa->ioc); - bfa_trc(port->bfa, port->pwwn); - bfa_trc(port->bfa, port->nwwn); + bfa_trc(fcport->bfa, fcport->pwwn); + bfa_trc(fcport->bfa, fcport->nwwn); } static void -bfa_port_send_txcredit(void *port_cbarg) +bfa_fcport_send_txcredit(void *port_cbarg) { - struct bfa_pport_s *port = port_cbarg; + struct bfa_fcport_s *fcport = port_cbarg; struct bfi_pport_set_svc_params_req_s *m; /** * check for room in queue to send request now */ - m = bfa_reqq_next(port->bfa, BFA_REQQ_PORT); + m = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); if (!m) { - bfa_trc(port->bfa, port->cfg.tx_bbcredit); + bfa_trc(fcport->bfa, fcport->cfg.tx_bbcredit); return; } bfi_h2i_set(m->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_SET_SVC_PARAMS_REQ, - bfa_lpuid(port->bfa)); - m->tx_bbcredit = bfa_os_htons((u16) port->cfg.tx_bbcredit); + bfa_lpuid(fcport->bfa)); + m->tx_bbcredit = bfa_os_htons((u16) fcport->cfg.tx_bbcredit); /** * queue I/O message to firmware */ - bfa_reqq_produce(port->bfa, BFA_REQQ_PORT); + bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); } @@ -1083,32 +1114,32 @@ bfa_port_send_txcredit(void *port_cbarg) * Firmware message handler. */ void -bfa_pport_isr(struct bfa_s *bfa, struct bfi_msg_s *msg) +bfa_fcport_isr(struct bfa_s *bfa, struct bfi_msg_s *msg) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); union bfi_pport_i2h_msg_u i2hmsg; i2hmsg.msg = msg; - pport->event_arg.i2hmsg = i2hmsg; + fcport->event_arg.i2hmsg = i2hmsg; switch (msg->mhdr.msg_id) { case BFI_PPORT_I2H_ENABLE_RSP: - if (pport->msgtag == i2hmsg.enable_rsp->msgtag) - bfa_sm_send_event(pport, BFA_PPORT_SM_FWRSP); + if (fcport->msgtag == i2hmsg.enable_rsp->msgtag) + bfa_sm_send_event(fcport, BFA_FCPORT_SM_FWRSP); break; case BFI_PPORT_I2H_DISABLE_RSP: - if (pport->msgtag == i2hmsg.enable_rsp->msgtag) - bfa_sm_send_event(pport, BFA_PPORT_SM_FWRSP); + if (fcport->msgtag == i2hmsg.enable_rsp->msgtag) + bfa_sm_send_event(fcport, BFA_FCPORT_SM_FWRSP); break; case BFI_PPORT_I2H_EVENT: switch (i2hmsg.event->link_state.linkstate) { case BFA_PPORT_LINKUP: - bfa_sm_send_event(pport, BFA_PPORT_SM_LINKUP); + bfa_sm_send_event(fcport, BFA_FCPORT_SM_LINKUP); break; case BFA_PPORT_LINKDOWN: - bfa_sm_send_event(pport, BFA_PPORT_SM_LINKDOWN); + bfa_sm_send_event(fcport, BFA_FCPORT_SM_LINKDOWN); break; case BFA_PPORT_TRUNK_LINKDOWN: /** todo: event notification */ @@ -1121,32 +1152,63 @@ bfa_pport_isr(struct bfa_s *bfa, struct bfi_msg_s *msg) /* * check for timer pop before processing the rsp */ - if (pport->stats_busy == BFA_FALSE - || pport->stats_status == BFA_STATUS_ETIMER) + if (fcport->stats_busy == BFA_FALSE + || fcport->stats_status == BFA_STATUS_ETIMER) break; - bfa_timer_stop(&pport->timer); - pport->stats_status = i2hmsg.getstats_rsp->status; - bfa_cb_queue(pport->bfa, &pport->hcb_qe, __bfa_cb_port_stats, - pport); + bfa_timer_stop(&fcport->timer); + fcport->stats_status = i2hmsg.getstats_rsp->status; + bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, __bfa_cb_port_stats, + fcport); break; case BFI_PPORT_I2H_CLEAR_STATS_RSP: case BFI_PPORT_I2H_CLEAR_QOS_STATS_RSP: /* * check for timer pop before processing the rsp */ - if (pport->stats_busy == BFA_FALSE - || pport->stats_status == BFA_STATUS_ETIMER) + if (fcport->stats_busy == BFA_FALSE + || fcport->stats_status == BFA_STATUS_ETIMER) break; - bfa_timer_stop(&pport->timer); - pport->stats_status = BFA_STATUS_OK; - bfa_cb_queue(pport->bfa, &pport->hcb_qe, - __bfa_cb_port_stats_clr, pport); + bfa_timer_stop(&fcport->timer); + fcport->stats_status = BFA_STATUS_OK; + bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, + __bfa_cb_port_stats_clr, fcport); + break; + + case BFI_FCPORT_I2H_GET_STATS_RSP: + /* + * check for timer pop before processing the rsp + */ + if (fcport->stats_busy == BFA_FALSE || + fcport->stats_status == BFA_STATUS_ETIMER) { + break; + } + + bfa_timer_stop(&fcport->timer); + fcport->stats_status = i2hmsg.getstats_rsp->status; + bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, + __bfa_cb_fcport_stats, fcport); + break; + + case BFI_FCPORT_I2H_CLEAR_STATS_RSP: + /* + * check for timer pop before processing the rsp + */ + if (fcport->stats_busy == BFA_FALSE || + fcport->stats_status == BFA_STATUS_ETIMER) { + break; + } + + bfa_timer_stop(&fcport->timer); + fcport->stats_status = BFA_STATUS_OK; + bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, + __bfa_cb_fcport_stats_clr, fcport); break; default: bfa_assert(0); + break; } } @@ -1160,35 +1222,35 @@ bfa_pport_isr(struct bfa_s *bfa, struct bfi_msg_s *msg) * Registered callback for port events. */ void -bfa_pport_event_register(struct bfa_s *bfa, +bfa_fcport_event_register(struct bfa_s *bfa, void (*cbfn) (void *cbarg, bfa_pport_event_t event), void *cbarg) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - pport->event_cbfn = cbfn; - pport->event_cbarg = cbarg; + fcport->event_cbfn = cbfn; + fcport->event_cbarg = cbarg; } bfa_status_t -bfa_pport_enable(struct bfa_s *bfa) +bfa_fcport_enable(struct bfa_s *bfa) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - if (pport->diag_busy) + if (fcport->diag_busy) return BFA_STATUS_DIAG_BUSY; else if (bfa_sm_cmp_state - (BFA_PORT_MOD(bfa), bfa_pport_sm_disabling_qwait)) + (BFA_FCPORT_MOD(bfa), bfa_fcport_sm_disabling_qwait)) return BFA_STATUS_DEVBUSY; - bfa_sm_send_event(BFA_PORT_MOD(bfa), BFA_PPORT_SM_ENABLE); + bfa_sm_send_event(BFA_FCPORT_MOD(bfa), BFA_FCPORT_SM_ENABLE); return BFA_STATUS_OK; } bfa_status_t -bfa_pport_disable(struct bfa_s *bfa) +bfa_fcport_disable(struct bfa_s *bfa) { - bfa_sm_send_event(BFA_PORT_MOD(bfa), BFA_PPORT_SM_DISABLE); + bfa_sm_send_event(BFA_FCPORT_MOD(bfa), BFA_FCPORT_SM_DISABLE); return BFA_STATUS_OK; } @@ -1196,18 +1258,18 @@ bfa_pport_disable(struct bfa_s *bfa) * Configure port speed. */ bfa_status_t -bfa_pport_cfg_speed(struct bfa_s *bfa, enum bfa_pport_speed speed) +bfa_fcport_cfg_speed(struct bfa_s *bfa, enum bfa_pport_speed speed) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); bfa_trc(bfa, speed); - if ((speed != BFA_PPORT_SPEED_AUTO) && (speed > pport->speed_sup)) { - bfa_trc(bfa, pport->speed_sup); + if ((speed != BFA_PPORT_SPEED_AUTO) && (speed > fcport->speed_sup)) { + bfa_trc(bfa, fcport->speed_sup); return BFA_STATUS_UNSUPP_SPEED; } - pport->cfg.speed = speed; + fcport->cfg.speed = speed; return BFA_STATUS_OK; } @@ -1216,23 +1278,23 @@ bfa_pport_cfg_speed(struct bfa_s *bfa, enum bfa_pport_speed speed) * Get current speed. */ enum bfa_pport_speed -bfa_pport_get_speed(struct bfa_s *bfa) +bfa_fcport_get_speed(struct bfa_s *bfa) { - struct bfa_pport_s *port = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - return port->speed; + return fcport->speed; } /** * Configure port topology. */ bfa_status_t -bfa_pport_cfg_topology(struct bfa_s *bfa, enum bfa_pport_topology topology) +bfa_fcport_cfg_topology(struct bfa_s *bfa, enum bfa_pport_topology topology) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); bfa_trc(bfa, topology); - bfa_trc(bfa, pport->cfg.topology); + bfa_trc(bfa, fcport->cfg.topology); switch (topology) { case BFA_PPORT_TOPOLOGY_P2P: @@ -1244,7 +1306,7 @@ bfa_pport_cfg_topology(struct bfa_s *bfa, enum bfa_pport_topology topology) return BFA_STATUS_EINVAL; } - pport->cfg.topology = topology; + fcport->cfg.topology = topology; return BFA_STATUS_OK; } @@ -1252,64 +1314,64 @@ bfa_pport_cfg_topology(struct bfa_s *bfa, enum bfa_pport_topology topology) * Get current topology. */ enum bfa_pport_topology -bfa_pport_get_topology(struct bfa_s *bfa) +bfa_fcport_get_topology(struct bfa_s *bfa) { - struct bfa_pport_s *port = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - return port->topology; + return fcport->topology; } bfa_status_t -bfa_pport_cfg_hardalpa(struct bfa_s *bfa, u8 alpa) +bfa_fcport_cfg_hardalpa(struct bfa_s *bfa, u8 alpa) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); bfa_trc(bfa, alpa); - bfa_trc(bfa, pport->cfg.cfg_hardalpa); - bfa_trc(bfa, pport->cfg.hardalpa); + bfa_trc(bfa, fcport->cfg.cfg_hardalpa); + bfa_trc(bfa, fcport->cfg.hardalpa); - pport->cfg.cfg_hardalpa = BFA_TRUE; - pport->cfg.hardalpa = alpa; + fcport->cfg.cfg_hardalpa = BFA_TRUE; + fcport->cfg.hardalpa = alpa; return BFA_STATUS_OK; } bfa_status_t -bfa_pport_clr_hardalpa(struct bfa_s *bfa) +bfa_fcport_clr_hardalpa(struct bfa_s *bfa) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - bfa_trc(bfa, pport->cfg.cfg_hardalpa); - bfa_trc(bfa, pport->cfg.hardalpa); + bfa_trc(bfa, fcport->cfg.cfg_hardalpa); + bfa_trc(bfa, fcport->cfg.hardalpa); - pport->cfg.cfg_hardalpa = BFA_FALSE; + fcport->cfg.cfg_hardalpa = BFA_FALSE; return BFA_STATUS_OK; } bfa_boolean_t -bfa_pport_get_hardalpa(struct bfa_s *bfa, u8 *alpa) +bfa_fcport_get_hardalpa(struct bfa_s *bfa, u8 *alpa) { - struct bfa_pport_s *port = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - *alpa = port->cfg.hardalpa; - return port->cfg.cfg_hardalpa; + *alpa = fcport->cfg.hardalpa; + return fcport->cfg.cfg_hardalpa; } u8 -bfa_pport_get_myalpa(struct bfa_s *bfa) +bfa_fcport_get_myalpa(struct bfa_s *bfa) { - struct bfa_pport_s *port = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - return port->myalpa; + return fcport->myalpa; } bfa_status_t -bfa_pport_cfg_maxfrsize(struct bfa_s *bfa, u16 maxfrsize) +bfa_fcport_cfg_maxfrsize(struct bfa_s *bfa, u16 maxfrsize) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); bfa_trc(bfa, maxfrsize); - bfa_trc(bfa, pport->cfg.maxfrsize); + bfa_trc(bfa, fcport->cfg.maxfrsize); /* * with in range @@ -1323,41 +1385,41 @@ bfa_pport_cfg_maxfrsize(struct bfa_s *bfa, u16 maxfrsize) if ((maxfrsize != FC_MAX_PDUSZ) && (maxfrsize & (maxfrsize - 1))) return BFA_STATUS_INVLD_DFSZ; - pport->cfg.maxfrsize = maxfrsize; + fcport->cfg.maxfrsize = maxfrsize; return BFA_STATUS_OK; } u16 -bfa_pport_get_maxfrsize(struct bfa_s *bfa) +bfa_fcport_get_maxfrsize(struct bfa_s *bfa) { - struct bfa_pport_s *port = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - return port->cfg.maxfrsize; + return fcport->cfg.maxfrsize; } u32 -bfa_pport_mypid(struct bfa_s *bfa) +bfa_fcport_mypid(struct bfa_s *bfa) { - struct bfa_pport_s *port = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - return port->mypid; + return fcport->mypid; } u8 -bfa_pport_get_rx_bbcredit(struct bfa_s *bfa) +bfa_fcport_get_rx_bbcredit(struct bfa_s *bfa) { - struct bfa_pport_s *port = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - return port->cfg.rx_bbcredit; + return fcport->cfg.rx_bbcredit; } void -bfa_pport_set_tx_bbcredit(struct bfa_s *bfa, u16 tx_bbcredit) +bfa_fcport_set_tx_bbcredit(struct bfa_s *bfa, u16 tx_bbcredit) { - struct bfa_pport_s *port = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - port->cfg.tx_bbcredit = (u8) tx_bbcredit; - bfa_port_send_txcredit(port); + fcport->cfg.tx_bbcredit = (u8) tx_bbcredit; + bfa_fcport_send_txcredit(fcport); } /** @@ -1365,78 +1427,79 @@ bfa_pport_set_tx_bbcredit(struct bfa_s *bfa, u16 tx_bbcredit) */ wwn_t -bfa_pport_get_wwn(struct bfa_s *bfa, bfa_boolean_t node) +bfa_fcport_get_wwn(struct bfa_s *bfa, bfa_boolean_t node) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); if (node) - return pport->nwwn; + return fcport->nwwn; else - return pport->pwwn; + return fcport->pwwn; } void -bfa_pport_get_attr(struct bfa_s *bfa, struct bfa_pport_attr_s *attr) +bfa_fcport_get_attr(struct bfa_s *bfa, struct bfa_pport_attr_s *attr) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); bfa_os_memset(attr, 0, sizeof(struct bfa_pport_attr_s)); - attr->nwwn = pport->nwwn; - attr->pwwn = pport->pwwn; + attr->nwwn = fcport->nwwn; + attr->pwwn = fcport->pwwn; - bfa_os_memcpy(&attr->pport_cfg, &pport->cfg, + bfa_os_memcpy(&attr->pport_cfg, &fcport->cfg, sizeof(struct bfa_pport_cfg_s)); /* * speed attributes */ - attr->pport_cfg.speed = pport->cfg.speed; - attr->speed_supported = pport->speed_sup; - attr->speed = pport->speed; + attr->pport_cfg.speed = fcport->cfg.speed; + attr->speed_supported = fcport->speed_sup; + attr->speed = fcport->speed; attr->cos_supported = FC_CLASS_3; /* * topology attributes */ - attr->pport_cfg.topology = pport->cfg.topology; - attr->topology = pport->topology; + attr->pport_cfg.topology = fcport->cfg.topology; + attr->topology = fcport->topology; /* * beacon attributes */ - attr->beacon = pport->beacon; - attr->link_e2e_beacon = pport->link_e2e_beacon; - attr->plog_enabled = bfa_plog_get_setting(pport->bfa->plog); + attr->beacon = fcport->beacon; + attr->link_e2e_beacon = fcport->link_e2e_beacon; + attr->plog_enabled = bfa_plog_get_setting(fcport->bfa->plog); attr->pport_cfg.path_tov = bfa_fcpim_path_tov_get(bfa); attr->pport_cfg.q_depth = bfa_fcpim_qdepth_get(bfa); - attr->port_state = bfa_sm_to_state(hal_pport_sm_table, pport->sm); - if (bfa_ioc_is_disabled(&pport->bfa->ioc)) + attr->port_state = bfa_sm_to_state(hal_pport_sm_table, fcport->sm); + if (bfa_ioc_is_disabled(&fcport->bfa->ioc)) attr->port_state = BFA_PPORT_ST_IOCDIS; - else if (bfa_ioc_fw_mismatch(&pport->bfa->ioc)) + else if (bfa_ioc_fw_mismatch(&fcport->bfa->ioc)) attr->port_state = BFA_PPORT_ST_FWMISMATCH; } static void bfa_port_stats_query(void *cbarg) { - struct bfa_pport_s *port = (struct bfa_pport_s *)cbarg; + struct bfa_fcport_s *fcport = (struct bfa_fcport_s *)cbarg; bfi_pport_get_stats_req_t *msg; - msg = bfa_reqq_next(port->bfa, BFA_REQQ_PORT); + msg = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); if (!msg) { - port->stats_qfull = BFA_TRUE; - bfa_reqq_winit(&port->stats_reqq_wait, bfa_port_stats_query, - port); - bfa_reqq_wait(port->bfa, BFA_REQQ_PORT, &port->stats_reqq_wait); + fcport->stats_qfull = BFA_TRUE; + bfa_reqq_winit(&fcport->stats_reqq_wait, bfa_port_stats_query, + fcport); + bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, + &fcport->stats_reqq_wait); return; } - port->stats_qfull = BFA_FALSE; + fcport->stats_qfull = BFA_FALSE; bfa_os_memset(msg, 0, sizeof(bfi_pport_get_stats_req_t)); bfi_h2i_set(msg->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_GET_STATS_REQ, - bfa_lpuid(port->bfa)); - bfa_reqq_produce(port->bfa, BFA_REQQ_PORT); + bfa_lpuid(fcport->bfa)); + bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); return; } @@ -1444,65 +1507,111 @@ bfa_port_stats_query(void *cbarg) static void bfa_port_stats_clear(void *cbarg) { - struct bfa_pport_s *port = (struct bfa_pport_s *)cbarg; + struct bfa_fcport_s *fcport = (struct bfa_fcport_s *)cbarg; bfi_pport_clear_stats_req_t *msg; - msg = bfa_reqq_next(port->bfa, BFA_REQQ_PORT); + msg = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); if (!msg) { - port->stats_qfull = BFA_TRUE; - bfa_reqq_winit(&port->stats_reqq_wait, bfa_port_stats_clear, - port); - bfa_reqq_wait(port->bfa, BFA_REQQ_PORT, &port->stats_reqq_wait); + fcport->stats_qfull = BFA_TRUE; + bfa_reqq_winit(&fcport->stats_reqq_wait, bfa_port_stats_clear, + fcport); + bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, + &fcport->stats_reqq_wait); return; } - port->stats_qfull = BFA_FALSE; + fcport->stats_qfull = BFA_FALSE; bfa_os_memset(msg, 0, sizeof(bfi_pport_clear_stats_req_t)); bfi_h2i_set(msg->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_CLEAR_STATS_REQ, - bfa_lpuid(port->bfa)); - bfa_reqq_produce(port->bfa, BFA_REQQ_PORT); + bfa_lpuid(fcport->bfa)); + bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); return; } +static void +bfa_fcport_stats_query(void *cbarg) +{ + struct bfa_fcport_s *fcport = (struct bfa_fcport_s *) cbarg; + bfi_pport_get_stats_req_t *msg; + + msg = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); + + if (!msg) { + fcport->stats_qfull = BFA_TRUE; + bfa_reqq_winit(&fcport->stats_reqq_wait, + bfa_fcport_stats_query, fcport); + bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, + &fcport->stats_reqq_wait); + return; + } + fcport->stats_qfull = BFA_FALSE; + + bfa_os_memset(msg, 0, sizeof(bfi_pport_get_stats_req_t)); + bfi_h2i_set(msg->mh, BFI_MC_FC_PORT, BFI_FCPORT_H2I_GET_STATS_REQ, + bfa_lpuid(fcport->bfa)); + bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); +} + +static void +bfa_fcport_stats_clear(void *cbarg) +{ + struct bfa_fcport_s *fcport = (struct bfa_fcport_s *) cbarg; + bfi_pport_clear_stats_req_t *msg; + + msg = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); + + if (!msg) { + fcport->stats_qfull = BFA_TRUE; + bfa_reqq_winit(&fcport->stats_reqq_wait, + bfa_fcport_stats_clear, fcport); + bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, + &fcport->stats_reqq_wait); + return; + } + fcport->stats_qfull = BFA_FALSE; + + bfa_os_memset(msg, 0, sizeof(bfi_pport_clear_stats_req_t)); + bfi_h2i_set(msg->mh, BFI_MC_FC_PORT, BFI_FCPORT_H2I_CLEAR_STATS_REQ, + bfa_lpuid(fcport->bfa)); + bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); +} + static void bfa_port_qos_stats_clear(void *cbarg) { - struct bfa_pport_s *port = (struct bfa_pport_s *)cbarg; + struct bfa_fcport_s *fcport = (struct bfa_fcport_s *)cbarg; bfi_pport_clear_qos_stats_req_t *msg; - msg = bfa_reqq_next(port->bfa, BFA_REQQ_PORT); + msg = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); if (!msg) { - port->stats_qfull = BFA_TRUE; - bfa_reqq_winit(&port->stats_reqq_wait, bfa_port_qos_stats_clear, - port); - bfa_reqq_wait(port->bfa, BFA_REQQ_PORT, &port->stats_reqq_wait); + fcport->stats_qfull = BFA_TRUE; + bfa_reqq_winit(&fcport->stats_reqq_wait, + bfa_port_qos_stats_clear, fcport); + bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, + &fcport->stats_reqq_wait); return; } - port->stats_qfull = BFA_FALSE; + fcport->stats_qfull = BFA_FALSE; bfa_os_memset(msg, 0, sizeof(bfi_pport_clear_qos_stats_req_t)); bfi_h2i_set(msg->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_CLEAR_QOS_STATS_REQ, - bfa_lpuid(port->bfa)); - bfa_reqq_produce(port->bfa, BFA_REQQ_PORT); + bfa_lpuid(fcport->bfa)); + bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); return; } static void -bfa_pport_stats_swap(union bfa_pport_stats_u *d, union bfa_pport_stats_u *s) +bfa_fcport_stats_swap(union bfa_fcport_stats_u *d, union bfa_fcport_stats_u *s) { - u32 *dip = (u32 *) d; - u32 *sip = (u32 *) s; + u32 *dip = (u32 *) d; + u32 *sip = (u32 *) s; int i; - /* - * Do 64 bit fields swap first - */ - for (i = 0; - i < - ((sizeof(union bfa_pport_stats_u) - - sizeof(struct bfa_qos_stats_s)) / sizeof(u32)); i = i + 2) { + /* Do 64 bit fields swap first */ + for (i = 0; i < ((sizeof(union bfa_fcport_stats_u) - + sizeof(struct bfa_qos_stats_s))/sizeof(u32)); i = i + 2) { #ifdef __BIGENDIAN dip[i] = bfa_os_ntohl(sip[i]); dip[i + 1] = bfa_os_ntohl(sip[i + 1]); @@ -1512,56 +1621,88 @@ bfa_pport_stats_swap(union bfa_pport_stats_u *d, union bfa_pport_stats_u *s) #endif } - /* - * Now swap the 32 bit fields - */ - for (; i < (sizeof(union bfa_pport_stats_u) / sizeof(u32)); ++i) + /* Now swap the 32 bit fields */ + for (; i < (sizeof(union bfa_fcport_stats_u)/sizeof(u32)); ++i) + dip[i] = bfa_os_ntohl(sip[i]); +} + +static void +bfa_port_stats_swap(union bfa_pport_stats_u *d, union bfa_pport_stats_u *s) +{ + u32 *dip = (u32 *) d; + u32 *sip = (u32 *) s; + int i; + + /* Do 64 bit fields swap first */ + for (i = 0; i < (sizeof(union bfa_pport_stats_u) / sizeof(u32)); + i = i + 2) { +#ifdef __BIGENDIAN dip[i] = bfa_os_ntohl(sip[i]); + dip[i + 1] = bfa_os_ntohl(sip[i + 1]); +#else + dip[i] = bfa_os_ntohl(sip[i + 1]); + dip[i + 1] = bfa_os_ntohl(sip[i]); +#endif + } } static void __bfa_cb_port_stats_clr(void *cbarg, bfa_boolean_t complete) { - struct bfa_pport_s *port = cbarg; + struct bfa_fcport_s *fcport = cbarg; if (complete) { - port->stats_cbfn(port->stats_cbarg, port->stats_status); + fcport->stats_cbfn(fcport->stats_cbarg, fcport->stats_status); } else { - port->stats_busy = BFA_FALSE; - port->stats_status = BFA_STATUS_OK; + fcport->stats_busy = BFA_FALSE; + fcport->stats_status = BFA_STATUS_OK; + } +} + +static void +__bfa_cb_fcport_stats_clr(void *cbarg, bfa_boolean_t complete) +{ + struct bfa_fcport_s *fcport = cbarg; + + if (complete) { + fcport->stats_cbfn(fcport->stats_cbarg, fcport->stats_status); + } else { + fcport->stats_busy = BFA_FALSE; + fcport->stats_status = BFA_STATUS_OK; } } static void bfa_port_stats_clr_timeout(void *cbarg) { - struct bfa_pport_s *port = (struct bfa_pport_s *)cbarg; + struct bfa_fcport_s *fcport = (struct bfa_fcport_s *)cbarg; - bfa_trc(port->bfa, port->stats_qfull); + bfa_trc(fcport->bfa, fcport->stats_qfull); - if (port->stats_qfull) { - bfa_reqq_wcancel(&port->stats_reqq_wait); - port->stats_qfull = BFA_FALSE; + if (fcport->stats_qfull) { + bfa_reqq_wcancel(&fcport->stats_reqq_wait); + fcport->stats_qfull = BFA_FALSE; } - port->stats_status = BFA_STATUS_ETIMER; - bfa_cb_queue(port->bfa, &port->hcb_qe, __bfa_cb_port_stats_clr, port); + fcport->stats_status = BFA_STATUS_ETIMER; + bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, + __bfa_cb_port_stats_clr, fcport); } static void -bfa_pport_callback(struct bfa_pport_s *pport, enum bfa_pport_linkstate event) +bfa_fcport_callback(struct bfa_fcport_s *fcport, enum bfa_pport_linkstate event) { - if (pport->bfa->fcs) { - pport->event_cbfn(pport->event_cbarg, event); + if (fcport->bfa->fcs) { + fcport->event_cbfn(fcport->event_cbarg, event); return; } switch (event) { case BFA_PPORT_LINKUP: - bfa_sm_send_event(&pport->ln, BFA_PPORT_LN_SM_LINKUP); + bfa_sm_send_event(&fcport->ln, BFA_FCPORT_LN_SM_LINKUP); break; case BFA_PPORT_LINKDOWN: - bfa_sm_send_event(&pport->ln, BFA_PPORT_LN_SM_LINKDOWN); + bfa_sm_send_event(&fcport->ln, BFA_FCPORT_LN_SM_LINKDOWN); break; default: bfa_assert(0); @@ -1569,41 +1710,92 @@ bfa_pport_callback(struct bfa_pport_s *pport, enum bfa_pport_linkstate event) } static void -bfa_pport_queue_cb(struct bfa_pport_ln_s *ln, enum bfa_pport_linkstate event) +bfa_fcport_queue_cb(struct bfa_fcport_ln_s *ln, enum bfa_pport_linkstate event) { ln->ln_event = event; - bfa_cb_queue(ln->pport->bfa, &ln->ln_qe, __bfa_cb_port_event, ln); + bfa_cb_queue(ln->fcport->bfa, &ln->ln_qe, __bfa_cb_fcport_event, ln); +} + +static void +bfa_fcport_stats_clr_timeout(void *cbarg) +{ + struct bfa_fcport_s *fcport = (struct bfa_fcport_s *) cbarg; + + bfa_trc(fcport->bfa, fcport->stats_qfull); + + if (fcport->stats_qfull) { + bfa_reqq_wcancel(&fcport->stats_reqq_wait); + fcport->stats_qfull = BFA_FALSE; + } + + fcport->stats_status = BFA_STATUS_ETIMER; + bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, __bfa_cb_fcport_stats_clr, + fcport); } static void __bfa_cb_port_stats(void *cbarg, bfa_boolean_t complete) { - struct bfa_pport_s *port = cbarg; + struct bfa_fcport_s *fcport = cbarg; if (complete) { - if (port->stats_status == BFA_STATUS_OK) - bfa_pport_stats_swap(port->stats_ret, port->stats); - port->stats_cbfn(port->stats_cbarg, port->stats_status); + if (fcport->stats_status == BFA_STATUS_OK) + bfa_port_stats_swap(fcport->stats_ret, fcport->stats); + fcport->stats_cbfn(fcport->stats_cbarg, fcport->stats_status); } else { - port->stats_busy = BFA_FALSE; - port->stats_status = BFA_STATUS_OK; + fcport->stats_busy = BFA_FALSE; + fcport->stats_status = BFA_STATUS_OK; } } static void bfa_port_stats_timeout(void *cbarg) { - struct bfa_pport_s *port = (struct bfa_pport_s *)cbarg; + struct bfa_fcport_s *fcport = (struct bfa_fcport_s *)cbarg; - bfa_trc(port->bfa, port->stats_qfull); + bfa_trc(fcport->bfa, fcport->stats_qfull); - if (port->stats_qfull) { - bfa_reqq_wcancel(&port->stats_reqq_wait); - port->stats_qfull = BFA_FALSE; + if (fcport->stats_qfull) { + bfa_reqq_wcancel(&fcport->stats_reqq_wait); + fcport->stats_qfull = BFA_FALSE; } - port->stats_status = BFA_STATUS_ETIMER; - bfa_cb_queue(port->bfa, &port->hcb_qe, __bfa_cb_port_stats, port); + fcport->stats_status = BFA_STATUS_ETIMER; + bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, __bfa_cb_port_stats, fcport); +} + +static void +__bfa_cb_fcport_stats(void *cbarg, bfa_boolean_t complete) +{ + struct bfa_fcport_s *fcport = cbarg; + + if (complete) { + if (fcport->stats_status == BFA_STATUS_OK) { + bfa_fcport_stats_swap(fcport->fcport_stats_ret, + fcport->fcport_stats); + } + fcport->stats_cbfn(fcport->stats_cbarg, fcport->stats_status); + } else { + fcport->stats_busy = BFA_FALSE; + fcport->stats_status = BFA_STATUS_OK; + } +} + +static void +bfa_fcport_stats_timeout(void *cbarg) +{ + struct bfa_fcport_s *fcport = (struct bfa_fcport_s *) cbarg; + + bfa_trc(fcport->bfa, fcport->stats_qfull); + + if (fcport->stats_qfull) { + bfa_reqq_wcancel(&fcport->stats_reqq_wait); + fcport->stats_qfull = BFA_FALSE; + } + + fcport->stats_status = BFA_STATUS_ETIMER; + bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, __bfa_cb_fcport_stats, + fcport); } #define BFA_PORT_STATS_TOV 1000 @@ -1615,21 +1807,21 @@ bfa_status_t bfa_pport_get_stats(struct bfa_s *bfa, union bfa_pport_stats_u *stats, bfa_cb_pport_t cbfn, void *cbarg) { - struct bfa_pport_s *port = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - if (port->stats_busy) { - bfa_trc(bfa, port->stats_busy); + if (fcport->stats_busy) { + bfa_trc(bfa, fcport->stats_busy); return BFA_STATUS_DEVBUSY; } - port->stats_busy = BFA_TRUE; - port->stats_ret = stats; - port->stats_cbfn = cbfn; - port->stats_cbarg = cbarg; + fcport->stats_busy = BFA_TRUE; + fcport->stats_ret = stats; + fcport->stats_cbfn = cbfn; + fcport->stats_cbarg = cbarg; - bfa_port_stats_query(port); + bfa_port_stats_query(fcport); - bfa_timer_start(bfa, &port->timer, bfa_port_stats_timeout, port, + bfa_timer_start(bfa, &fcport->timer, bfa_port_stats_timeout, fcport, BFA_PORT_STATS_TOV); return BFA_STATUS_OK; } @@ -1637,57 +1829,111 @@ bfa_pport_get_stats(struct bfa_s *bfa, union bfa_pport_stats_u *stats, bfa_status_t bfa_pport_clear_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg) { - struct bfa_pport_s *port = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); + + if (fcport->stats_busy) { + bfa_trc(bfa, fcport->stats_busy); + return BFA_STATUS_DEVBUSY; + } + + fcport->stats_busy = BFA_TRUE; + fcport->stats_cbfn = cbfn; + fcport->stats_cbarg = cbarg; + + bfa_port_stats_clear(fcport); + + bfa_timer_start(bfa, &fcport->timer, bfa_port_stats_clr_timeout, + fcport, BFA_PORT_STATS_TOV); + return BFA_STATUS_OK; +} + +/** + * @brief + * Fetch FCPort statistics. + * Todo TBD: sharing timer,stats_busy and other resources of fcport for now - + * ideally we want to create seperate ones for fcport once bfa_fcport_s is + * decided. + * + */ +bfa_status_t +bfa_fcport_get_stats(struct bfa_s *bfa, union bfa_fcport_stats_u *stats, + bfa_cb_pport_t cbfn, void *cbarg) +{ + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - if (port->stats_busy) { - bfa_trc(bfa, port->stats_busy); + if (fcport->stats_busy) { + bfa_trc(bfa, fcport->stats_busy); return BFA_STATUS_DEVBUSY; } - port->stats_busy = BFA_TRUE; - port->stats_cbfn = cbfn; - port->stats_cbarg = cbarg; + fcport->stats_busy = BFA_TRUE; + fcport->fcport_stats_ret = stats; + fcport->stats_cbfn = cbfn; + fcport->stats_cbarg = cbarg; - bfa_port_stats_clear(port); + bfa_fcport_stats_query(fcport); - bfa_timer_start(bfa, &port->timer, bfa_port_stats_clr_timeout, port, + bfa_timer_start(bfa, &fcport->timer, bfa_fcport_stats_timeout, fcport, BFA_PORT_STATS_TOV); + + return BFA_STATUS_OK; +} + +bfa_status_t +bfa_fcport_clear_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg) +{ + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); + + if (fcport->stats_busy) { + bfa_trc(bfa, fcport->stats_busy); + return BFA_STATUS_DEVBUSY; + } + + fcport->stats_busy = BFA_TRUE; + fcport->stats_cbfn = cbfn; + fcport->stats_cbarg = cbarg; + + bfa_fcport_stats_clear(fcport); + + bfa_timer_start(bfa, &fcport->timer, bfa_fcport_stats_clr_timeout, + fcport, BFA_PORT_STATS_TOV); + return BFA_STATUS_OK; } bfa_status_t -bfa_pport_trunk_enable(struct bfa_s *bfa, u8 bitmap) +bfa_fcport_trunk_enable(struct bfa_s *bfa, u8 bitmap) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); bfa_trc(bfa, bitmap); - bfa_trc(bfa, pport->cfg.trunked); - bfa_trc(bfa, pport->cfg.trunk_ports); + bfa_trc(bfa, fcport->cfg.trunked); + bfa_trc(bfa, fcport->cfg.trunk_ports); if (!bitmap || (bitmap & (bitmap - 1))) return BFA_STATUS_EINVAL; - pport->cfg.trunked = BFA_TRUE; - pport->cfg.trunk_ports = bitmap; + fcport->cfg.trunked = BFA_TRUE; + fcport->cfg.trunk_ports = bitmap; return BFA_STATUS_OK; } void -bfa_pport_qos_get_attr(struct bfa_s *bfa, struct bfa_qos_attr_s *qos_attr) +bfa_fcport_qos_get_attr(struct bfa_s *bfa, struct bfa_qos_attr_s *qos_attr) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - qos_attr->state = bfa_os_ntohl(pport->qos_attr.state); - qos_attr->total_bb_cr = bfa_os_ntohl(pport->qos_attr.total_bb_cr); + qos_attr->state = bfa_os_ntohl(fcport->qos_attr.state); + qos_attr->total_bb_cr = bfa_os_ntohl(fcport->qos_attr.total_bb_cr); } void -bfa_pport_qos_get_vc_attr(struct bfa_s *bfa, +bfa_fcport_qos_get_vc_attr(struct bfa_s *bfa, struct bfa_qos_vc_attr_s *qos_vc_attr) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); - struct bfa_qos_vc_attr_s *bfa_vc_attr = &pport->qos_vc_attr; + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); + struct bfa_qos_vc_attr_s *bfa_vc_attr = &fcport->qos_vc_attr; u32 i = 0; qos_vc_attr->total_vc_count = bfa_os_ntohs(bfa_vc_attr->total_vc_count); @@ -1713,7 +1959,7 @@ bfa_pport_qos_get_vc_attr(struct bfa_s *bfa, * Fetch QoS Stats. */ bfa_status_t -bfa_pport_get_qos_stats(struct bfa_s *bfa, union bfa_pport_stats_u *stats, +bfa_fcport_get_qos_stats(struct bfa_s *bfa, union bfa_pport_stats_u *stats, bfa_cb_pport_t cbfn, void *cbarg) { /* @@ -1723,23 +1969,23 @@ bfa_pport_get_qos_stats(struct bfa_s *bfa, union bfa_pport_stats_u *stats, } bfa_status_t -bfa_pport_clear_qos_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg) +bfa_fcport_clear_qos_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg) { - struct bfa_pport_s *port = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - if (port->stats_busy) { - bfa_trc(bfa, port->stats_busy); + if (fcport->stats_busy) { + bfa_trc(bfa, fcport->stats_busy); return BFA_STATUS_DEVBUSY; } - port->stats_busy = BFA_TRUE; - port->stats_cbfn = cbfn; - port->stats_cbarg = cbarg; + fcport->stats_busy = BFA_TRUE; + fcport->stats_cbfn = cbfn; + fcport->stats_cbarg = cbarg; - bfa_port_qos_stats_clear(port); + bfa_port_qos_stats_clear(fcport); - bfa_timer_start(bfa, &port->timer, bfa_port_stats_clr_timeout, port, - BFA_PORT_STATS_TOV); + bfa_timer_start(bfa, &fcport->timer, bfa_port_stats_clr_timeout, + fcport, BFA_PORT_STATS_TOV); return BFA_STATUS_OK; } @@ -1747,82 +1993,82 @@ bfa_pport_clear_qos_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg) * Fetch port attributes. */ bfa_status_t -bfa_pport_trunk_disable(struct bfa_s *bfa) +bfa_fcport_trunk_disable(struct bfa_s *bfa) { return BFA_STATUS_OK; } bfa_boolean_t -bfa_pport_trunk_query(struct bfa_s *bfa, u32 *bitmap) +bfa_fcport_trunk_query(struct bfa_s *bfa, u32 *bitmap) { - struct bfa_pport_s *port = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - *bitmap = port->cfg.trunk_ports; - return port->cfg.trunked; + *bitmap = fcport->cfg.trunk_ports; + return fcport->cfg.trunked; } bfa_boolean_t -bfa_pport_is_disabled(struct bfa_s *bfa) +bfa_fcport_is_disabled(struct bfa_s *bfa) { - struct bfa_pport_s *port = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - return bfa_sm_to_state(hal_pport_sm_table, port->sm) == + return bfa_sm_to_state(hal_pport_sm_table, fcport->sm) == BFA_PPORT_ST_DISABLED; } bfa_boolean_t -bfa_pport_is_ratelim(struct bfa_s *bfa) +bfa_fcport_is_ratelim(struct bfa_s *bfa) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - return pport->cfg.ratelimit ? BFA_TRUE : BFA_FALSE; + return fcport->cfg.ratelimit ? BFA_TRUE : BFA_FALSE; } void -bfa_pport_cfg_qos(struct bfa_s *bfa, bfa_boolean_t on_off) +bfa_fcport_cfg_qos(struct bfa_s *bfa, bfa_boolean_t on_off) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); bfa_trc(bfa, on_off); - bfa_trc(bfa, pport->cfg.qos_enabled); + bfa_trc(bfa, fcport->cfg.qos_enabled); - pport->cfg.qos_enabled = on_off; + fcport->cfg.qos_enabled = on_off; } void -bfa_pport_cfg_ratelim(struct bfa_s *bfa, bfa_boolean_t on_off) +bfa_fcport_cfg_ratelim(struct bfa_s *bfa, bfa_boolean_t on_off) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); bfa_trc(bfa, on_off); - bfa_trc(bfa, pport->cfg.ratelimit); + bfa_trc(bfa, fcport->cfg.ratelimit); - pport->cfg.ratelimit = on_off; - if (pport->cfg.trl_def_speed == BFA_PPORT_SPEED_UNKNOWN) - pport->cfg.trl_def_speed = BFA_PPORT_SPEED_1GBPS; + fcport->cfg.ratelimit = on_off; + if (fcport->cfg.trl_def_speed == BFA_PPORT_SPEED_UNKNOWN) + fcport->cfg.trl_def_speed = BFA_PPORT_SPEED_1GBPS; } /** * Configure default minimum ratelim speed */ bfa_status_t -bfa_pport_cfg_ratelim_speed(struct bfa_s *bfa, enum bfa_pport_speed speed) +bfa_fcport_cfg_ratelim_speed(struct bfa_s *bfa, enum bfa_pport_speed speed) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); bfa_trc(bfa, speed); /* * Auto and speeds greater than the supported speed, are invalid */ - if ((speed == BFA_PPORT_SPEED_AUTO) || (speed > pport->speed_sup)) { - bfa_trc(bfa, pport->speed_sup); + if ((speed == BFA_PPORT_SPEED_AUTO) || (speed > fcport->speed_sup)) { + bfa_trc(bfa, fcport->speed_sup); return BFA_STATUS_UNSUPP_SPEED; } - pport->cfg.trl_def_speed = speed; + fcport->cfg.trl_def_speed = speed; return BFA_STATUS_OK; } @@ -1831,45 +2077,45 @@ bfa_pport_cfg_ratelim_speed(struct bfa_s *bfa, enum bfa_pport_speed speed) * Get default minimum ratelim speed */ enum bfa_pport_speed -bfa_pport_get_ratelim_speed(struct bfa_s *bfa) +bfa_fcport_get_ratelim_speed(struct bfa_s *bfa) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - bfa_trc(bfa, pport->cfg.trl_def_speed); - return pport->cfg.trl_def_speed; + bfa_trc(bfa, fcport->cfg.trl_def_speed); + return fcport->cfg.trl_def_speed; } void -bfa_pport_busy(struct bfa_s *bfa, bfa_boolean_t status) +bfa_fcport_busy(struct bfa_s *bfa, bfa_boolean_t status) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); bfa_trc(bfa, status); - bfa_trc(bfa, pport->diag_busy); + bfa_trc(bfa, fcport->diag_busy); - pport->diag_busy = status; + fcport->diag_busy = status; } void -bfa_pport_beacon(struct bfa_s *bfa, bfa_boolean_t beacon, +bfa_fcport_beacon(struct bfa_s *bfa, bfa_boolean_t beacon, bfa_boolean_t link_e2e_beacon) { - struct bfa_pport_s *pport = BFA_PORT_MOD(bfa); + struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); bfa_trc(bfa, beacon); bfa_trc(bfa, link_e2e_beacon); - bfa_trc(bfa, pport->beacon); - bfa_trc(bfa, pport->link_e2e_beacon); + bfa_trc(bfa, fcport->beacon); + bfa_trc(bfa, fcport->link_e2e_beacon); - pport->beacon = beacon; - pport->link_e2e_beacon = link_e2e_beacon; + fcport->beacon = beacon; + fcport->link_e2e_beacon = link_e2e_beacon; } bfa_boolean_t -bfa_pport_is_linkup(struct bfa_s *bfa) +bfa_fcport_is_linkup(struct bfa_s *bfa) { - return bfa_sm_cmp_state(BFA_PORT_MOD(bfa), bfa_pport_sm_linkup); + return bfa_sm_cmp_state(BFA_FCPORT_MOD(bfa), bfa_fcport_sm_linkup); } diff --git a/drivers/scsi/bfa/bfa_fcs_port.c b/drivers/scsi/bfa/bfa_fcs_port.c index 53808d0418a1..3c27788cd527 100644 --- a/drivers/scsi/bfa/bfa_fcs_port.c +++ b/drivers/scsi/bfa/bfa_fcs_port.c @@ -57,5 +57,5 @@ bfa_fcs_pport_event_handler(void *cbarg, bfa_pport_event_t event) void bfa_fcs_pport_attach(struct bfa_fcs_s *fcs) { - bfa_pport_event_register(fcs->bfa, bfa_fcs_pport_event_handler, fcs); + bfa_fcport_event_register(fcs->bfa, bfa_fcs_pport_event_handler, fcs); } diff --git a/drivers/scsi/bfa/bfa_module.c b/drivers/scsi/bfa/bfa_module.c index 32eda8e1ec65..a7fcc80c177e 100644 --- a/drivers/scsi/bfa/bfa_module.c +++ b/drivers/scsi/bfa/bfa_module.c @@ -24,7 +24,7 @@ */ struct bfa_module_s *hal_mods[] = { &hal_mod_sgpg, - &hal_mod_pport, + &hal_mod_fcport, &hal_mod_fcxp, &hal_mod_lps, &hal_mod_uf, @@ -45,7 +45,7 @@ bfa_isr_func_t bfa_isrs[BFI_MC_MAX] = { bfa_isr_unhandled, /* BFI_MC_DIAG */ bfa_isr_unhandled, /* BFI_MC_FLASH */ bfa_isr_unhandled, /* BFI_MC_CEE */ - bfa_pport_isr, /* BFI_MC_PORT */ + bfa_fcport_isr, /* BFI_MC_FCPORT */ bfa_isr_unhandled, /* BFI_MC_IOCFC */ bfa_isr_unhandled, /* BFI_MC_LL */ bfa_uf_isr, /* BFI_MC_UF */ diff --git a/drivers/scsi/bfa/bfa_modules_priv.h b/drivers/scsi/bfa/bfa_modules_priv.h index 96f70534593c..f554c2fad6a9 100644 --- a/drivers/scsi/bfa/bfa_modules_priv.h +++ b/drivers/scsi/bfa/bfa_modules_priv.h @@ -29,7 +29,7 @@ struct bfa_modules_s { - struct bfa_pport_s pport; /* physical port module */ + struct bfa_fcport_s fcport; /* fc port module */ struct bfa_fcxp_mod_s fcxp_mod; /* fcxp module */ struct bfa_lps_mod_s lps_mod; /* fcxp module */ struct bfa_uf_mod_s uf_mod; /* unsolicited frame module */ diff --git a/drivers/scsi/bfa/bfa_port_priv.h b/drivers/scsi/bfa/bfa_port_priv.h index f29701bd2369..6d315ffb1e99 100644 --- a/drivers/scsi/bfa/bfa_port_priv.h +++ b/drivers/scsi/bfa/bfa_port_priv.h @@ -25,17 +25,17 @@ /** * Link notification data structure */ -struct bfa_pport_ln_s { - struct bfa_pport_s *pport; +struct bfa_fcport_ln_s { + struct bfa_fcport_s *fcport; bfa_sm_t sm; struct bfa_cb_qe_s ln_qe; /* BFA callback queue elem for ln */ enum bfa_pport_linkstate ln_event; /* ln event for callback */ }; /** - * BFA physical port data structure + * BFA FC port data structure */ -struct bfa_pport_s { +struct bfa_fcport_s { struct bfa_s *bfa; /* parent BFA instance */ bfa_sm_t sm; /* port state machine */ wwn_t nwwn; /* node wwn of physical port */ @@ -62,7 +62,7 @@ struct bfa_pport_s { union bfi_pport_i2h_msg_u i2hmsg; } event_arg; void *bfad; /* BFA driver handle */ - struct bfa_pport_ln_s ln; /* Link Notification */ + struct bfa_fcport_ln_s ln; /* Link Notification */ struct bfa_cb_qe_s hcb_qe; /* BFA callback queue elem */ u32 msgtag; /* fimrware msg tag for reply */ u8 *stats_kva; @@ -88,12 +88,17 @@ struct bfa_pport_s { /* driver callback function */ void *stats_cbarg; /* *!< user callback arg */ + /* FCport stats */ + u8 *fcport_stats_kva; + u64 fcport_stats_pa; + union bfa_fcport_stats_u *fcport_stats; + union bfa_fcport_stats_u *fcport_stats_ret; }; -#define BFA_PORT_MOD(__bfa) (&(__bfa)->modules.pport) +#define BFA_FCPORT_MOD(__bfa) (&(__bfa)->modules.fcport) /* * public functions */ -void bfa_pport_isr(struct bfa_s *bfa, struct bfi_msg_s *msg); +void bfa_fcport_isr(struct bfa_s *bfa, struct bfi_msg_s *msg); #endif /* __BFA_PORT_PRIV_H__ */ diff --git a/drivers/scsi/bfa/bfa_priv.h b/drivers/scsi/bfa/bfa_priv.h index 0747a6b26f7b..be80fc7e1b0e 100644 --- a/drivers/scsi/bfa/bfa_priv.h +++ b/drivers/scsi/bfa/bfa_priv.h @@ -101,7 +101,7 @@ extern bfa_boolean_t bfa_auto_recover; extern struct bfa_module_s hal_mod_flash; extern struct bfa_module_s hal_mod_fcdiag; extern struct bfa_module_s hal_mod_sgpg; -extern struct bfa_module_s hal_mod_pport; +extern struct bfa_module_s hal_mod_fcport; extern struct bfa_module_s hal_mod_fcxp; extern struct bfa_module_s hal_mod_lps; extern struct bfa_module_s hal_mod_uf; diff --git a/drivers/scsi/bfa/bfa_trcmod_priv.h b/drivers/scsi/bfa/bfa_trcmod_priv.h index 3d947d47b837..a7a82610db85 100644 --- a/drivers/scsi/bfa/bfa_trcmod_priv.h +++ b/drivers/scsi/bfa/bfa_trcmod_priv.h @@ -37,7 +37,7 @@ enum { BFA_TRC_HAL_IOIM = 6, BFA_TRC_HAL_TSKIM = 7, BFA_TRC_HAL_ITNIM = 8, - BFA_TRC_HAL_PPORT = 9, + BFA_TRC_HAL_FCPORT = 9, BFA_TRC_HAL_SGPG = 10, BFA_TRC_HAL_FLASH = 11, BFA_TRC_HAL_DEBUG = 12, diff --git a/drivers/scsi/bfa/bfad.c b/drivers/scsi/bfa/bfad.c index 79956c152af9..a8a529d5fea4 100644 --- a/drivers/scsi/bfa/bfad.c +++ b/drivers/scsi/bfa/bfad.c @@ -664,7 +664,7 @@ bfad_fcs_port_cfg(struct bfad_s *bfad) sprintf(symname, "%s-%d", BFAD_DRIVER_NAME, bfad->inst_no); memcpy(port_cfg.sym_name.symname, symname, strlen(symname)); - bfa_pport_get_attr(&bfad->bfa, &attr); + bfa_fcport_get_attr(&bfad->bfa, &attr); port_cfg.nwwn = attr.nwwn; port_cfg.pwwn = attr.pwwn; diff --git a/drivers/scsi/bfa/bfad_attr.c b/drivers/scsi/bfa/bfad_attr.c index adf801dbfa15..a691133c31a2 100644 --- a/drivers/scsi/bfa/bfad_attr.c +++ b/drivers/scsi/bfa/bfad_attr.c @@ -141,7 +141,7 @@ bfad_im_get_host_port_type(struct Scsi_Host *shost) struct bfad_s *bfad = im_port->bfad; struct bfa_pport_attr_s attr; - bfa_pport_get_attr(&bfad->bfa, &attr); + bfa_fcport_get_attr(&bfad->bfa, &attr); switch (attr.port_type) { case BFA_PPORT_TYPE_NPORT: @@ -173,7 +173,7 @@ bfad_im_get_host_port_state(struct Scsi_Host *shost) struct bfad_s *bfad = im_port->bfad; struct bfa_pport_attr_s attr; - bfa_pport_get_attr(&bfad->bfa, &attr); + bfa_fcport_get_attr(&bfad->bfa, &attr); switch (attr.port_state) { case BFA_PPORT_ST_LINKDOWN: @@ -232,7 +232,7 @@ bfad_im_get_host_speed(struct Scsi_Host *shost) unsigned long flags; spin_lock_irqsave(shost->host_lock, flags); - bfa_pport_get_attr(&bfad->bfa, &attr); + bfa_fcport_get_attr(&bfad->bfa, &attr); switch (attr.speed) { case BFA_PPORT_SPEED_8GBPS: fc_host_speed(shost) = FC_PORTSPEED_8GBIT; diff --git a/drivers/scsi/bfa/bfad_im.c b/drivers/scsi/bfa/bfad_im.c index f788c2a0ab07..23390b40b9c3 100644 --- a/drivers/scsi/bfa/bfad_im.c +++ b/drivers/scsi/bfa/bfad_im.c @@ -966,7 +966,7 @@ bfad_os_fc_host_init(struct bfad_im_port_s *im_port) FC_PORTSPEED_1GBIT; memset(&attr.pattr, 0, sizeof(attr.pattr)); - bfa_pport_get_attr(&bfad->bfa, &attr.pattr); + bfa_fcport_get_attr(&bfad->bfa, &attr.pattr); fc_host_maxframe_size(host) = attr.pattr.pport_cfg.maxfrsize; } diff --git a/drivers/scsi/bfa/fabric.c b/drivers/scsi/bfa/fabric.c index b02ed7653eb6..e1a4b312e9d4 100644 --- a/drivers/scsi/bfa/fabric.c +++ b/drivers/scsi/bfa/fabric.c @@ -37,7 +37,7 @@ BFA_TRC_FILE(FCS, FABRIC); #define BFA_FCS_FABRIC_CLEANUP_DELAY (10000) /* Milliseconds */ #define bfa_fcs_fabric_set_opertype(__fabric) do { \ - if (bfa_pport_get_topology((__fabric)->fcs->bfa) \ + if (bfa_fcport_get_topology((__fabric)->fcs->bfa) \ == BFA_PPORT_TOPOLOGY_P2P) \ (__fabric)->oper_type = BFA_PPORT_TYPE_NPORT; \ else \ @@ -160,7 +160,7 @@ bfa_fcs_fabric_sm_created(struct bfa_fcs_fabric_s *fabric, switch (event) { case BFA_FCS_FABRIC_SM_START: - if (bfa_pport_is_linkup(fabric->fcs->bfa)) { + if (bfa_fcport_is_linkup(fabric->fcs->bfa)) { bfa_sm_set_state(fabric, bfa_fcs_fabric_sm_flogi); bfa_fcs_fabric_login(fabric); } else @@ -224,7 +224,7 @@ bfa_fcs_fabric_sm_flogi(struct bfa_fcs_fabric_s *fabric, switch (event) { case BFA_FCS_FABRIC_SM_CONT_OP: - bfa_pport_set_tx_bbcredit(fabric->fcs->bfa, fabric->bb_credit); + bfa_fcport_set_tx_bbcredit(fabric->fcs->bfa, fabric->bb_credit); fabric->fab_type = BFA_FCS_FABRIC_SWITCHED; if (fabric->auth_reqd && fabric->is_auth) { @@ -251,7 +251,7 @@ bfa_fcs_fabric_sm_flogi(struct bfa_fcs_fabric_s *fabric, case BFA_FCS_FABRIC_SM_NO_FABRIC: fabric->fab_type = BFA_FCS_FABRIC_N2N; - bfa_pport_set_tx_bbcredit(fabric->fcs->bfa, fabric->bb_credit); + bfa_fcport_set_tx_bbcredit(fabric->fcs->bfa, fabric->bb_credit); bfa_fcs_fabric_notify_online(fabric); bfa_sm_set_state(fabric, bfa_fcs_fabric_sm_nofabric); break; @@ -418,7 +418,7 @@ bfa_fcs_fabric_sm_nofabric(struct bfa_fcs_fabric_s *fabric, case BFA_FCS_FABRIC_SM_NO_FABRIC: bfa_trc(fabric->fcs, fabric->bb_credit); - bfa_pport_set_tx_bbcredit(fabric->fcs->bfa, fabric->bb_credit); + bfa_fcport_set_tx_bbcredit(fabric->fcs->bfa, fabric->bb_credit); break; default: @@ -718,10 +718,10 @@ bfa_fcs_fabric_login(struct bfa_fcs_fabric_s *fabric) struct bfa_port_cfg_s *pcfg = &fabric->bport.port_cfg; u8 alpa = 0; - if (bfa_pport_get_topology(bfa) == BFA_PPORT_TOPOLOGY_LOOP) - alpa = bfa_pport_get_myalpa(bfa); + if (bfa_fcport_get_topology(bfa) == BFA_PPORT_TOPOLOGY_LOOP) + alpa = bfa_fcport_get_myalpa(bfa); - bfa_lps_flogi(fabric->lps, fabric, alpa, bfa_pport_get_maxfrsize(bfa), + bfa_lps_flogi(fabric->lps, fabric, alpa, bfa_fcport_get_maxfrsize(bfa), pcfg->pwwn, pcfg->nwwn, fabric->auth_reqd); fabric->stats.flogi_sent++; @@ -1176,8 +1176,8 @@ bfa_fcs_fabric_send_flogi_acc(struct bfa_fcs_fabric_s *fabric) reqlen = fc_flogi_acc_build(&fchs, bfa_fcxp_get_reqbuf(fcxp), bfa_os_hton3b(FC_FABRIC_PORT), n2n_port->reply_oxid, pcfg->pwwn, - pcfg->nwwn, bfa_pport_get_maxfrsize(bfa), - bfa_pport_get_rx_bbcredit(bfa)); + pcfg->nwwn, bfa_fcport_get_maxfrsize(bfa), + bfa_fcport_get_rx_bbcredit(bfa)); bfa_fcxp_send(fcxp, NULL, fabric->vf_id, bfa_lps_get_tag(fabric->lps), BFA_FALSE, FC_CLASS_3, reqlen, &fchs, diff --git a/drivers/scsi/bfa/fdmi.c b/drivers/scsi/bfa/fdmi.c index e8120868701b..2c9e7132a368 100644 --- a/drivers/scsi/bfa/fdmi.c +++ b/drivers/scsi/bfa/fdmi.c @@ -1175,7 +1175,7 @@ bfa_fcs_fdmi_get_portattr(struct bfa_fcs_port_fdmi_s *fdmi, /* * get pport attributes from hal */ - bfa_pport_get_attr(port->fcs->bfa, &pport_attr); + bfa_fcport_get_attr(port->fcs->bfa, &pport_attr); /* * get FC4 type Bitmask diff --git a/drivers/scsi/bfa/include/bfa_svc.h b/drivers/scsi/bfa/include/bfa_svc.h index 71ffb75a71ca..f2c30858900b 100644 --- a/drivers/scsi/bfa/include/bfa_svc.h +++ b/drivers/scsi/bfa/include/bfa_svc.h @@ -26,6 +26,7 @@ struct bfa_fcxp_s; #include #include #include +#include #include #include @@ -151,60 +152,67 @@ struct bfa_lps_s { bfa_eproto_status_t ext_status; }; +#define BFA_FCPORT(_bfa) (&((_bfa)->modules.port)) + /* * bfa pport API functions */ -bfa_status_t bfa_pport_enable(struct bfa_s *bfa); -bfa_status_t bfa_pport_disable(struct bfa_s *bfa); -bfa_status_t bfa_pport_cfg_speed(struct bfa_s *bfa, +bfa_status_t bfa_fcport_enable(struct bfa_s *bfa); +bfa_status_t bfa_fcport_disable(struct bfa_s *bfa); +bfa_status_t bfa_fcport_cfg_speed(struct bfa_s *bfa, enum bfa_pport_speed speed); -enum bfa_pport_speed bfa_pport_get_speed(struct bfa_s *bfa); -bfa_status_t bfa_pport_cfg_topology(struct bfa_s *bfa, +enum bfa_pport_speed bfa_fcport_get_speed(struct bfa_s *bfa); +bfa_status_t bfa_fcport_cfg_topology(struct bfa_s *bfa, enum bfa_pport_topology topo); -enum bfa_pport_topology bfa_pport_get_topology(struct bfa_s *bfa); -bfa_status_t bfa_pport_cfg_hardalpa(struct bfa_s *bfa, u8 alpa); -bfa_boolean_t bfa_pport_get_hardalpa(struct bfa_s *bfa, u8 *alpa); -u8 bfa_pport_get_myalpa(struct bfa_s *bfa); -bfa_status_t bfa_pport_clr_hardalpa(struct bfa_s *bfa); -bfa_status_t bfa_pport_cfg_maxfrsize(struct bfa_s *bfa, u16 maxsize); -u16 bfa_pport_get_maxfrsize(struct bfa_s *bfa); -u32 bfa_pport_mypid(struct bfa_s *bfa); -u8 bfa_pport_get_rx_bbcredit(struct bfa_s *bfa); -bfa_status_t bfa_pport_trunk_enable(struct bfa_s *bfa, u8 bitmap); -bfa_status_t bfa_pport_trunk_disable(struct bfa_s *bfa); -bfa_boolean_t bfa_pport_trunk_query(struct bfa_s *bfa, u32 *bitmap); -void bfa_pport_get_attr(struct bfa_s *bfa, struct bfa_pport_attr_s *attr); -wwn_t bfa_pport_get_wwn(struct bfa_s *bfa, bfa_boolean_t node); +enum bfa_pport_topology bfa_fcport_get_topology(struct bfa_s *bfa); +bfa_status_t bfa_fcport_cfg_hardalpa(struct bfa_s *bfa, u8 alpa); +bfa_boolean_t bfa_fcport_get_hardalpa(struct bfa_s *bfa, u8 *alpa); +u8 bfa_fcport_get_myalpa(struct bfa_s *bfa); +bfa_status_t bfa_fcport_clr_hardalpa(struct bfa_s *bfa); +bfa_status_t bfa_fcport_cfg_maxfrsize(struct bfa_s *bfa, u16 maxsize); +u16 bfa_fcport_get_maxfrsize(struct bfa_s *bfa); +u32 bfa_fcport_mypid(struct bfa_s *bfa); +u8 bfa_fcport_get_rx_bbcredit(struct bfa_s *bfa); +bfa_status_t bfa_fcport_trunk_enable(struct bfa_s *bfa, u8 bitmap); +bfa_status_t bfa_fcport_trunk_disable(struct bfa_s *bfa); +bfa_boolean_t bfa_fcport_trunk_query(struct bfa_s *bfa, u32 *bitmap); +void bfa_fcport_get_attr(struct bfa_s *bfa, struct bfa_pport_attr_s *attr); +wwn_t bfa_fcport_get_wwn(struct bfa_s *bfa, bfa_boolean_t node); bfa_status_t bfa_pport_get_stats(struct bfa_s *bfa, union bfa_pport_stats_u *stats, bfa_cb_pport_t cbfn, void *cbarg); bfa_status_t bfa_pport_clear_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg); -void bfa_pport_event_register(struct bfa_s *bfa, +void bfa_fcport_event_register(struct bfa_s *bfa, void (*event_cbfn) (void *cbarg, bfa_pport_event_t event), void *event_cbarg); -bfa_boolean_t bfa_pport_is_disabled(struct bfa_s *bfa); -void bfa_pport_cfg_qos(struct bfa_s *bfa, bfa_boolean_t on_off); -void bfa_pport_cfg_ratelim(struct bfa_s *bfa, bfa_boolean_t on_off); -bfa_status_t bfa_pport_cfg_ratelim_speed(struct bfa_s *bfa, +bfa_boolean_t bfa_fcport_is_disabled(struct bfa_s *bfa); +void bfa_fcport_cfg_qos(struct bfa_s *bfa, bfa_boolean_t on_off); +void bfa_fcport_cfg_ratelim(struct bfa_s *bfa, bfa_boolean_t on_off); +bfa_status_t bfa_fcport_cfg_ratelim_speed(struct bfa_s *bfa, enum bfa_pport_speed speed); -enum bfa_pport_speed bfa_pport_get_ratelim_speed(struct bfa_s *bfa); +enum bfa_pport_speed bfa_fcport_get_ratelim_speed(struct bfa_s *bfa); -void bfa_pport_set_tx_bbcredit(struct bfa_s *bfa, u16 tx_bbcredit); -void bfa_pport_busy(struct bfa_s *bfa, bfa_boolean_t status); -void bfa_pport_beacon(struct bfa_s *bfa, bfa_boolean_t beacon, +void bfa_fcport_set_tx_bbcredit(struct bfa_s *bfa, u16 tx_bbcredit); +void bfa_fcport_busy(struct bfa_s *bfa, bfa_boolean_t status); +void bfa_fcport_beacon(struct bfa_s *bfa, bfa_boolean_t beacon, bfa_boolean_t link_e2e_beacon); void bfa_cb_pport_event(void *cbarg, bfa_pport_event_t event); -void bfa_pport_qos_get_attr(struct bfa_s *bfa, struct bfa_qos_attr_s *qos_attr); -void bfa_pport_qos_get_vc_attr(struct bfa_s *bfa, +void bfa_fcport_qos_get_attr(struct bfa_s *bfa, struct bfa_qos_attr_s *qos_attr); +void bfa_fcport_qos_get_vc_attr(struct bfa_s *bfa, struct bfa_qos_vc_attr_s *qos_vc_attr); -bfa_status_t bfa_pport_get_qos_stats(struct bfa_s *bfa, +bfa_status_t bfa_fcport_get_qos_stats(struct bfa_s *bfa, union bfa_pport_stats_u *stats, bfa_cb_pport_t cbfn, void *cbarg); -bfa_status_t bfa_pport_clear_qos_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, +bfa_status_t bfa_fcport_clear_qos_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg); -bfa_boolean_t bfa_pport_is_ratelim(struct bfa_s *bfa); -bfa_boolean_t bfa_pport_is_linkup(struct bfa_s *bfa); +bfa_boolean_t bfa_fcport_is_ratelim(struct bfa_s *bfa); +bfa_boolean_t bfa_fcport_is_linkup(struct bfa_s *bfa); +bfa_status_t bfa_fcport_get_stats(struct bfa_s *bfa, + union bfa_fcport_stats_u *stats, + bfa_cb_pport_t cbfn, void *cbarg); +bfa_status_t bfa_fcport_clear_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, + void *cbarg); /* * bfa rport API functions diff --git a/drivers/scsi/bfa/include/bfi/bfi_pport.h b/drivers/scsi/bfa/include/bfi/bfi_pport.h index c96d246851af..5c3d289d986d 100644 --- a/drivers/scsi/bfa/include/bfi/bfi_pport.h +++ b/drivers/scsi/bfa/include/bfi/bfi_pport.h @@ -32,6 +32,8 @@ enum bfi_pport_h2i { BFI_PPORT_H2I_ENABLE_TX_VF_TAG_REQ = (7), BFI_PPORT_H2I_GET_QOS_STATS_REQ = (8), BFI_PPORT_H2I_CLEAR_QOS_STATS_REQ = (9), + BFI_FCPORT_H2I_GET_STATS_REQ = (10), + BFI_FCPORT_H2I_CLEAR_STATS_REQ = (11), }; enum bfi_pport_i2h { @@ -45,6 +47,8 @@ enum bfi_pport_i2h { BFI_PPORT_I2H_EVENT = BFA_I2HM(8), BFI_PPORT_I2H_GET_QOS_STATS_RSP = BFA_I2HM(9), BFI_PPORT_I2H_CLEAR_QOS_STATS_RSP = BFA_I2HM(10), + BFI_FCPORT_I2H_GET_STATS_RSP = BFA_I2HM(11), + BFI_FCPORT_I2H_CLEAR_STATS_RSP = BFA_I2HM(12), }; /** @@ -75,6 +79,7 @@ struct bfi_pport_enable_req_s { wwn_t pwwn; /* port wwn of physical port */ struct bfa_pport_cfg_s port_cfg; /* port configuration */ union bfi_addr_u stats_dma_addr; /* DMA address for stats */ + union bfi_addr_u fcport_stats_dma_addr;/*!< DMA address for stats */ u32 msgtag; /* msgtag for reply */ u32 rsvd2; }; diff --git a/drivers/scsi/bfa/include/cs/bfa_sm.h b/drivers/scsi/bfa/include/cs/bfa_sm.h index b0a92baf6657..11fba9082f05 100644 --- a/drivers/scsi/bfa/include/cs/bfa_sm.h +++ b/drivers/scsi/bfa/include/cs/bfa_sm.h @@ -23,6 +23,14 @@ #define __BFA_SM_H__ typedef void (*bfa_sm_t)(void *sm, int event); +/** + * oc - object class eg. bfa_ioc + * st - state, eg. reset + * otype - object type, eg. struct bfa_ioc_s + * etype - object type, eg. enum ioc_event + */ +#define bfa_sm_state_decl(oc, st, otype, etype) \ + static void oc ## _sm_ ## st(otype * fsm, etype event) #define bfa_sm_set_state(_sm, _state) ((_sm)->sm = (bfa_sm_t)(_state)) #define bfa_sm_send_event(_sm, _event) ((_sm)->sm((_sm), (_event))) diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_ethport.h b/drivers/scsi/bfa/include/defs/bfa_defs_ethport.h index 79f9b3e146f7..b4fa0923aa89 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_ethport.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_ethport.h @@ -19,6 +19,7 @@ #define __BFA_DEFS_ETHPORT_H__ #include +#include #include #include #include diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_fcport.h b/drivers/scsi/bfa/include/defs/bfa_defs_fcport.h new file mode 100644 index 000000000000..a07ef4a3cd78 --- /dev/null +++ b/drivers/scsi/bfa/include/defs/bfa_defs_fcport.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2005-2009 Brocade Communications Systems, Inc. + * All rights reserved + * www.brocade.com + * + * bfa_defs_fcport.h + * + * Linux driver for Brocade Fibre Channel Host Bus Adapter. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License (GPL) Version 2 as + * published by the Free Software Foundation + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ +#ifndef __BFA_DEFS_FCPORT_H__ +#define __BFA_DEFS_FCPORT_H__ + +#include +#include + +#pragma pack(1) + +/** + * FCoE statistics + */ +struct bfa_fcoe_stats_s { + u64 secs_reset; /* Seconds since stats reset */ + u64 cee_linkups; /* CEE link up */ + u64 cee_linkdns; /* CEE link down */ + u64 fip_linkups; /* FIP link up */ + u64 fip_linkdns; /* FIP link down */ + u64 fip_fails; /* FIP failures */ + u64 mac_invalids; /* Invalid mac assignments */ + u64 vlan_req; /* Vlan requests */ + u64 vlan_notify; /* Vlan notifications */ + u64 vlan_err; /* Vlan notification errors */ + u64 vlan_timeouts; /* Vlan request timeouts */ + u64 vlan_invalids; /* Vlan invalids */ + u64 disc_req; /* Discovery requests */ + u64 disc_rsp; /* Discovery responses */ + u64 disc_err; /* Discovery error frames */ + u64 disc_unsol; /* Discovery unsolicited */ + u64 disc_timeouts; /* Discovery timeouts */ + u64 disc_fcf_unavail; /* Discovery FCF not avail */ + u64 linksvc_unsupp; /* FIP link service req unsupp. */ + u64 linksvc_err; /* FIP link service req errors */ + u64 logo_req; /* FIP logo */ + u64 clrvlink_req; /* Clear virtual link requests */ + u64 op_unsupp; /* FIP operation unsupp. */ + u64 untagged; /* FIP untagged frames */ + u64 txf_ucast; /* Tx FCoE unicast frames */ + u64 txf_ucast_vlan; /* Tx FCoE unicast vlan frames */ + u64 txf_ucast_octets; /* Tx FCoE unicast octets */ + u64 txf_mcast; /* Tx FCoE mutlicast frames */ + u64 txf_mcast_vlan; /* Tx FCoE mutlicast vlan frames */ + u64 txf_mcast_octets; /* Tx FCoE multicast octets */ + u64 txf_bcast; /* Tx FCoE broadcast frames */ + u64 txf_bcast_vlan; /* Tx FCoE broadcast vlan frames */ + u64 txf_bcast_octets; /* Tx FCoE broadcast octets */ + u64 txf_timeout; /* Tx timeouts */ + u64 txf_parity_errors; /* Transmit parity err */ + u64 txf_fid_parity_errors; /* Transmit FID parity err */ + u64 tx_pause; /* Tx pause frames */ + u64 tx_zero_pause; /* Tx zero pause frames */ + u64 tx_first_pause; /* Tx first pause frames */ + u64 rx_pause; /* Rx pause frames */ + u64 rx_zero_pause; /* Rx zero pause frames */ + u64 rx_first_pause; /* Rx first pause frames */ + u64 rxf_ucast_octets; /* Rx unicast octets */ + u64 rxf_ucast; /* Rx unicast frames */ + u64 rxf_ucast_vlan; /* Rx unicast vlan frames */ + u64 rxf_mcast_octets; /* Rx multicast octets */ + u64 rxf_mcast; /* Rx multicast frames */ + u64 rxf_mcast_vlan; /* Rx multicast vlan frames */ + u64 rxf_bcast_octets; /* Rx broadcast octests */ + u64 rxf_bcast; /* Rx broadcast frames */ + u64 rxf_bcast_vlan; /* Rx broadcast vlan frames */ +}; + +/** + * QoS or FCoE stats (fcport stats excluding physical FC port stats) + */ +union bfa_fcport_stats_u { + struct bfa_qos_stats_s fcqos; + struct bfa_fcoe_stats_s fcoe; +}; + +#pragma pack() + +#endif /* __BFA_DEFS_FCPORT_H__ */ diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_iocfc.h b/drivers/scsi/bfa/include/defs/bfa_defs_iocfc.h index 87f0401c6439..c290fb13d2d1 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_iocfc.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_iocfc.h @@ -236,6 +236,7 @@ struct bfa_fw_fip_stats_s { u32 disc_err; /* Discovery advt. parse errors */ u32 disc_unsol; /* Discovery unsolicited */ u32 disc_timeouts; /* Discovery timeouts */ + u32 disc_fcf_unavail; /* Discovery FCF Not Avail. */ u32 linksvc_unsupp; /* Unsupported link service req */ u32 linksvc_err; /* Parse error in link service req */ u32 logo_req; /* Number of FIP logos received */ diff --git a/drivers/scsi/bfa/loop.c b/drivers/scsi/bfa/loop.c index f7c7f4f3c640..f6342efb6a90 100644 --- a/drivers/scsi/bfa/loop.c +++ b/drivers/scsi/bfa/loop.c @@ -162,7 +162,7 @@ bfa_fcs_port_loop_send_plogi(struct bfa_fcs_port_s *port, u8 alpa) len = fc_plogi_build(&fchs, bfa_fcxp_get_reqbuf(fcxp), alpa, bfa_fcs_port_get_fcid(port), 0, port->port_cfg.pwwn, port->port_cfg.nwwn, - bfa_pport_get_maxfrsize(port->fcs->bfa)); + bfa_fcport_get_maxfrsize(port->fcs->bfa)); bfa_fcxp_send(fcxp, NULL, port->fabric->vf_id, port->lp_tag, BFA_FALSE, FC_CLASS_3, len, &fchs, diff --git a/drivers/scsi/bfa/lport_api.c b/drivers/scsi/bfa/lport_api.c index 4a4ccce99364..d3907d184e2b 100644 --- a/drivers/scsi/bfa/lport_api.c +++ b/drivers/scsi/bfa/lport_api.c @@ -156,7 +156,7 @@ bfa_fcs_port_get_rport_max_speed(struct bfa_fcs_port_s *port) /* * Get Physical port's current speed */ - bfa_pport_get_attr(port->fcs->bfa, &pport_attr); + bfa_fcport_get_attr(port->fcs->bfa, &pport_attr); pport_speed = pport_attr.speed; bfa_trc(fcs, pport_speed); diff --git a/drivers/scsi/bfa/ms.c b/drivers/scsi/bfa/ms.c index f0275a409fd2..e6db5fd301f2 100644 --- a/drivers/scsi/bfa/ms.c +++ b/drivers/scsi/bfa/ms.c @@ -637,7 +637,7 @@ bfa_fcs_port_ms_send_plogi(void *ms_cbarg, struct bfa_fcxp_s *fcxp_alloced) bfa_os_hton3b(FC_MGMT_SERVER), bfa_fcs_port_get_fcid(port), 0, port->port_cfg.pwwn, port->port_cfg.nwwn, - bfa_pport_get_maxfrsize(port->fcs->bfa)); + bfa_fcport_get_maxfrsize(port->fcs->bfa)); bfa_fcxp_send(fcxp, NULL, port->fabric->vf_id, port->lp_tag, BFA_FALSE, FC_CLASS_3, len, &fchs, bfa_fcs_port_ms_plogi_response, diff --git a/drivers/scsi/bfa/ns.c b/drivers/scsi/bfa/ns.c index 6de06a557e2d..d20dd7e15742 100644 --- a/drivers/scsi/bfa/ns.c +++ b/drivers/scsi/bfa/ns.c @@ -660,7 +660,7 @@ bfa_fcs_port_ns_send_plogi(void *ns_cbarg, struct bfa_fcxp_s *fcxp_alloced) bfa_os_hton3b(FC_NAME_SERVER), bfa_fcs_port_get_fcid(port), 0, port->port_cfg.pwwn, port->port_cfg.nwwn, - bfa_pport_get_maxfrsize(port->fcs->bfa)); + bfa_fcport_get_maxfrsize(port->fcs->bfa)); bfa_fcxp_send(fcxp, NULL, port->fabric->vf_id, port->lp_tag, BFA_FALSE, FC_CLASS_3, len, &fchs, bfa_fcs_port_ns_plogi_response, diff --git a/drivers/scsi/bfa/rport.c b/drivers/scsi/bfa/rport.c index 80592e352226..8c5969c86934 100644 --- a/drivers/scsi/bfa/rport.c +++ b/drivers/scsi/bfa/rport.c @@ -1373,7 +1373,7 @@ bfa_fcs_rport_send_plogi(void *rport_cbarg, struct bfa_fcxp_s *fcxp_alloced) len = fc_plogi_build(&fchs, bfa_fcxp_get_reqbuf(fcxp), rport->pid, bfa_fcs_port_get_fcid(port), 0, port->port_cfg.pwwn, port->port_cfg.nwwn, - bfa_pport_get_maxfrsize(port->fcs->bfa)); + bfa_fcport_get_maxfrsize(port->fcs->bfa)); bfa_fcxp_send(fcxp, NULL, port->fabric->vf_id, port->lp_tag, BFA_FALSE, FC_CLASS_3, len, &fchs, bfa_fcs_rport_plogi_response, @@ -1485,7 +1485,7 @@ bfa_fcs_rport_send_plogiacc(void *rport_cbarg, struct bfa_fcxp_s *fcxp_alloced) len = fc_plogi_acc_build(&fchs, bfa_fcxp_get_reqbuf(fcxp), rport->pid, bfa_fcs_port_get_fcid(port), rport->reply_oxid, port->port_cfg.pwwn, port->port_cfg.nwwn, - bfa_pport_get_maxfrsize(port->fcs->bfa)); + bfa_fcport_get_maxfrsize(port->fcs->bfa)); bfa_fcxp_send(fcxp, NULL, port->fabric->vf_id, port->lp_tag, BFA_FALSE, FC_CLASS_3, len, &fchs, NULL, NULL, FC_MAX_PDUSZ, 0); @@ -1820,7 +1820,7 @@ bfa_fcs_rport_process_rpsc(struct bfa_fcs_rport_s *rport, /* * get curent speed from pport attributes from BFA */ - bfa_pport_get_attr(port->fcs->bfa, &pport_attr); + bfa_fcport_get_attr(port->fcs->bfa, &pport_attr); speeds.port_op_speed = fc_bfa_speed_to_rpsc_operspeed(pport_attr.speed); @@ -2171,7 +2171,7 @@ bfa_fcs_rport_update(struct bfa_fcs_rport_s *rport, struct fc_logi_s *plogi) bfa_trc(port->fcs, port->fabric->bb_credit); port->fabric->bb_credit = bfa_os_ntohs(plogi->csp.bbcred); - bfa_pport_set_tx_bbcredit(port->fcs->bfa, + bfa_fcport_set_tx_bbcredit(port->fcs->bfa, port->fabric->bb_credit); } diff --git a/drivers/scsi/bfa/rport_api.c b/drivers/scsi/bfa/rport_api.c index 3dae1774181e..a441f41d2a64 100644 --- a/drivers/scsi/bfa/rport_api.c +++ b/drivers/scsi/bfa/rport_api.c @@ -102,7 +102,7 @@ bfa_fcs_rport_get_attr(struct bfa_fcs_rport_s *rport, rport_attr->qos_attr = qos_attr; rport_attr->trl_enforced = BFA_FALSE; - if (bfa_pport_is_ratelim(port->fcs->bfa)) { + if (bfa_fcport_is_ratelim(port->fcs->bfa)) { if ((rport->rpf.rpsc_speed == BFA_PPORT_SPEED_UNKNOWN) || (rport->rpf.rpsc_speed < bfa_fcs_port_get_rport_max_speed(port))) diff --git a/drivers/scsi/bfa/vport.c b/drivers/scsi/bfa/vport.c index 14fb7ac2bfbc..c5e534eb1620 100644 --- a/drivers/scsi/bfa/vport.c +++ b/drivers/scsi/bfa/vport.c @@ -478,7 +478,7 @@ static void bfa_fcs_vport_do_fdisc(struct bfa_fcs_vport_s *vport) { bfa_lps_fdisc(vport->lps, vport, - bfa_pport_get_maxfrsize(__vport_bfa(vport)), + bfa_fcport_get_maxfrsize(__vport_bfa(vport)), __vport_pwwn(vport), __vport_nwwn(vport)); vport->vport_stats.fdisc_sent++; } -- cgit v1.2.3 From f58e9ebbf78bd36c6cf1ca651280d39efe73a7c0 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:37:45 -0800 Subject: [SCSI] bfa: New portlog entries for events (FIP/FLOGI/FDISC/LOGO). Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_fcport.c | 21 ++++++++++++++++---- drivers/scsi/bfa/bfa_lps.c | 27 ++++++++++++++++++++++++-- drivers/scsi/bfa/include/defs/bfa_defs_pport.h | 21 ++++++++++++++++++-- drivers/scsi/bfa/include/protocol/fc.h | 5 +++++ 4 files changed, 66 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_fcport.c b/drivers/scsi/bfa/bfa_fcport.c index f392a7fa8c7f..a48413c230a5 100644 --- a/drivers/scsi/bfa/bfa_fcport.c +++ b/drivers/scsi/bfa/bfa_fcport.c @@ -326,6 +326,7 @@ static void bfa_fcport_sm_linkdown(struct bfa_fcport_s *fcport, enum bfa_fcport_sm_event event) { + struct bfi_pport_event_s *pevent = fcport->event_arg.i2hmsg.event; bfa_trc(fcport->bfa, event); switch (event) { @@ -335,6 +336,22 @@ bfa_fcport_sm_linkdown(struct bfa_fcport_s *fcport, bfa_assert(fcport->event_cbfn); bfa_plog_str(fcport->bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_PORT_ST_CHANGE, 0, "Port Linkup"); + + if (!bfa_ioc_get_fcmode(&fcport->bfa->ioc)) { + + bfa_trc(fcport->bfa, pevent->link_state.fcf.fipenabled); + bfa_trc(fcport->bfa, pevent->link_state.fcf.fipfailed); + + if (pevent->link_state.fcf.fipfailed) + bfa_plog_str(fcport->bfa->plog, BFA_PL_MID_HAL, + BFA_PL_EID_FIP_FCF_DISC, 0, + "FIP FCF Discovery Failed"); + else + bfa_plog_str(fcport->bfa->plog, BFA_PL_MID_HAL, + BFA_PL_EID_FIP_FCF_DISC, 0, + "FIP FCF Discovered"); + } + bfa_fcport_callback(fcport, BFA_PPORT_LINKUP); bfa_fcport_aen_post(fcport, BFA_PORT_AEN_ONLINE); /** @@ -1500,8 +1517,6 @@ bfa_port_stats_query(void *cbarg) bfi_h2i_set(msg->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_GET_STATS_REQ, bfa_lpuid(fcport->bfa)); bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); - - return; } static void @@ -1526,7 +1541,6 @@ bfa_port_stats_clear(void *cbarg) bfi_h2i_set(msg->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_CLEAR_STATS_REQ, bfa_lpuid(fcport->bfa)); bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); - return; } static void @@ -1599,7 +1613,6 @@ bfa_port_qos_stats_clear(void *cbarg) bfi_h2i_set(msg->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_CLEAR_QOS_STATS_REQ, bfa_lpuid(fcport->bfa)); bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); - return; } static void diff --git a/drivers/scsi/bfa/bfa_lps.c b/drivers/scsi/bfa/bfa_lps.c index 730616f6e671..d2d48a619c30 100644 --- a/drivers/scsi/bfa/bfa_lps.c +++ b/drivers/scsi/bfa/bfa_lps.c @@ -99,6 +99,12 @@ bfa_lps_sm_init(struct bfa_lps_s *lps, enum bfa_lps_event event) bfa_sm_set_state(lps, bfa_lps_sm_login); bfa_lps_send_login(lps); } + if (lps->fdisc) + bfa_plog_str(lps->bfa->plog, BFA_PL_MID_LPS, + BFA_PL_EID_LOGIN, 0, "FDISC Request"); + else + bfa_plog_str(lps->bfa->plog, BFA_PL_MID_LPS, + BFA_PL_EID_LOGIN, 0, "FLOGI Request"); break; case BFA_LPS_SM_LOGOUT: @@ -136,10 +142,25 @@ bfa_lps_sm_login(struct bfa_lps_s *lps, enum bfa_lps_event event) switch (event) { case BFA_LPS_SM_FWRSP: - if (lps->status == BFA_STATUS_OK) + if (lps->status == BFA_STATUS_OK) { bfa_sm_set_state(lps, bfa_lps_sm_online); - else + if (lps->fdisc) + bfa_plog_str(lps->bfa->plog, BFA_PL_MID_LPS, + BFA_PL_EID_LOGIN, 0, "FDISC Accept"); + else + bfa_plog_str(lps->bfa->plog, BFA_PL_MID_LPS, + BFA_PL_EID_LOGIN, 0, "FLOGI Accept"); + } else { bfa_sm_set_state(lps, bfa_lps_sm_init); + if (lps->fdisc) + bfa_plog_str(lps->bfa->plog, BFA_PL_MID_LPS, + BFA_PL_EID_LOGIN, 0, + "FDISC Fail (RJT or timeout)"); + else + bfa_plog_str(lps->bfa->plog, BFA_PL_MID_LPS, + BFA_PL_EID_LOGIN, 0, + "FLOGI Fail (RJT or timeout)"); + } bfa_lps_login_comp(lps); break; @@ -202,6 +223,8 @@ bfa_lps_sm_online(struct bfa_lps_s *lps, enum bfa_lps_event event) bfa_sm_set_state(lps, bfa_lps_sm_logout); bfa_lps_send_logout(lps); } + bfa_plog_str(lps->bfa->plog, BFA_PL_MID_LPS, + BFA_PL_EID_LOGO, 0, "Logout"); break; case BFA_LPS_SM_RX_CVL: diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_pport.h b/drivers/scsi/bfa/include/defs/bfa_defs_pport.h index 88662a15a21b..164cfbef9b12 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_pport.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_pport.h @@ -333,8 +333,7 @@ struct bfa_pport_fcpmap_s { }; /** - * Port RNID info. - */ + * Port RNI */ struct bfa_pport_rnid_s { wwn_t wwn; u32 unittype; @@ -347,6 +346,23 @@ struct bfa_pport_rnid_s { u16 topologydiscoveryflags; }; +struct bfa_fcport_fcf_s { + wwn_t name; /* FCF name */ + wwn_t fabric_name; /* Fabric Name */ + u8 fipenabled; /* FIP enabled or not */ + u8 fipfailed; /* FIP failed or not */ + u8 resv[2]; + u8 pri; /* FCF priority */ + u8 version; /* FIP version used */ + u8 available; /* Available for login */ + u8 fka_disabled; /* FKA is disabled */ + u8 maxsz_verified; /* FCoE max size verified */ + u8 fc_map[3]; /* FC map */ + u16 vlan; /* FCoE vlan tag/priority */ + u32 fka_adv_per; /* FIP ka advert. period */ + struct mac_s mac; /* FCF mac */ +}; + /** * Link state information */ @@ -378,6 +394,7 @@ struct bfa_pport_link_s { struct fc_alpabm_s alpabm; /* alpa bitmap */ } loop_info; } tl; + struct bfa_fcport_fcf_s fcf; /*!< FCF information (for FCoE) */ }; #endif /* __BFA_DEFS_PPORT_H__ */ diff --git a/drivers/scsi/bfa/include/protocol/fc.h b/drivers/scsi/bfa/include/protocol/fc.h index 14969eecf6a9..8d1038035a76 100644 --- a/drivers/scsi/bfa/include/protocol/fc.h +++ b/drivers/scsi/bfa/include/protocol/fc.h @@ -50,6 +50,11 @@ struct fchs_s { u32 ro; /* relative offset */ }; + +#define FC_SOF_LEN 4 +#define FC_EOF_LEN 4 +#define FC_CRC_LEN 4 + /* * Fibre Channel BB_E Header Structure */ -- cgit v1.2.3 From 0a4b1fc0b24fc7adbaf8413f2992ce1395991a78 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:37:57 -0800 Subject: [SCSI] bfa: Replace bfa_get_attr() with specific APIs bfa_ioc_attr_s is a big structure and some times could cause stack overflow if defined locally, so add specific APIs that are needed to replace the use of ioc_attr local var. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_fcport.c | 33 ++------ drivers/scsi/bfa/bfa_fcs_lport.c | 26 +----- drivers/scsi/bfa/bfa_ioc.c | 155 +++++++++++++++++++++------------- drivers/scsi/bfa/bfa_ioc.h | 10 +++ drivers/scsi/bfa/bfa_lps.c | 6 +- drivers/scsi/bfa/bfad.c | 4 +- drivers/scsi/bfa/bfad_attr.c | 62 ++++++-------- drivers/scsi/bfa/bfad_drv.h | 13 +++ drivers/scsi/bfa/bfad_im.c | 29 +++---- drivers/scsi/bfa/fabric.c | 10 +-- drivers/scsi/bfa/fcpim.c | 15 +--- drivers/scsi/bfa/include/bfa.h | 20 +++++ drivers/scsi/bfa/include/cs/bfa_log.h | 2 +- drivers/scsi/bfa/rport.c | 7 +- drivers/scsi/bfa/vport.c | 18 +--- 15 files changed, 195 insertions(+), 215 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_fcport.c b/drivers/scsi/bfa/bfa_fcport.c index a48413c230a5..0da612010787 100644 --- a/drivers/scsi/bfa/bfa_fcport.c +++ b/drivers/scsi/bfa/bfa_fcport.c @@ -145,35 +145,12 @@ bfa_fcport_aen_post(struct bfa_fcport_s *fcport, enum bfa_port_aen_event event) struct bfa_log_mod_s *logmod = fcport->bfa->logm; wwn_t pwwn = fcport->pwwn; char pwwn_ptr[BFA_STRING_32]; - struct bfa_ioc_attr_s ioc_attr; memset(&aen_data, 0, sizeof(aen_data)); wwn2str(pwwn_ptr, pwwn); - switch (event) { - case BFA_PORT_AEN_ONLINE: - bfa_log(logmod, BFA_AEN_PORT_ONLINE, pwwn_ptr); - break; - case BFA_PORT_AEN_OFFLINE: - bfa_log(logmod, BFA_AEN_PORT_OFFLINE, pwwn_ptr); - break; - case BFA_PORT_AEN_ENABLE: - bfa_log(logmod, BFA_AEN_PORT_ENABLE, pwwn_ptr); - break; - case BFA_PORT_AEN_DISABLE: - bfa_log(logmod, BFA_AEN_PORT_DISABLE, pwwn_ptr); - break; - case BFA_PORT_AEN_DISCONNECT: - bfa_log(logmod, BFA_AEN_PORT_DISCONNECT, pwwn_ptr); - break; - case BFA_PORT_AEN_QOS_NEG: - bfa_log(logmod, BFA_AEN_PORT_QOS_NEG, pwwn_ptr); - break; - default: - break; - } + bfa_log(logmod, BFA_LOG_CREATE_ID(BFA_AEN_CAT_PORT, event), pwwn_ptr); - bfa_ioc_get_attr(&fcport->bfa->ioc, &ioc_attr); - aen_data.port.ioc_type = ioc_attr.ioc_type; + aen_data.port.ioc_type = bfa_get_type(fcport->bfa); aen_data.port.pwwn = pwwn; } @@ -2043,11 +2020,15 @@ void bfa_fcport_cfg_qos(struct bfa_s *bfa, bfa_boolean_t on_off) { struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); + enum bfa_ioc_type_e ioc_type = bfa_get_type(bfa); bfa_trc(bfa, on_off); bfa_trc(bfa, fcport->cfg.qos_enabled); - fcport->cfg.qos_enabled = on_off; + bfa_trc(bfa, ioc_type); + + if (ioc_type == BFA_IOC_TYPE_FC) + fcport->cfg.qos_enabled = on_off; } void diff --git a/drivers/scsi/bfa/bfa_fcs_lport.c b/drivers/scsi/bfa/bfa_fcs_lport.c index 4a51aac7ab04..7c1251c682d8 100644 --- a/drivers/scsi/bfa/bfa_fcs_lport.c +++ b/drivers/scsi/bfa/bfa_fcs_lport.c @@ -263,30 +263,8 @@ bfa_fcs_port_aen_post(struct bfa_fcs_port_s *port, bfa_assert(role <= BFA_PORT_ROLE_FCP_MAX); - switch (event) { - case BFA_LPORT_AEN_ONLINE: - bfa_log(logmod, BFA_AEN_LPORT_ONLINE, lpwwn_ptr, - role_str[role / 2]); - break; - case BFA_LPORT_AEN_OFFLINE: - bfa_log(logmod, BFA_AEN_LPORT_OFFLINE, lpwwn_ptr, - role_str[role / 2]); - break; - case BFA_LPORT_AEN_NEW: - bfa_log(logmod, BFA_AEN_LPORT_NEW, lpwwn_ptr, - role_str[role / 2]); - break; - case BFA_LPORT_AEN_DELETE: - bfa_log(logmod, BFA_AEN_LPORT_DELETE, lpwwn_ptr, - role_str[role / 2]); - break; - case BFA_LPORT_AEN_DISCONNECT: - bfa_log(logmod, BFA_AEN_LPORT_DISCONNECT, lpwwn_ptr, - role_str[role / 2]); - break; - default: - break; - } + bfa_log(logmod, BFA_LOG_CREATE_ID(BFA_AEN_CAT_LPORT, event), lpwwn_ptr, + role_str[role/2]); aen_data.lport.vf_id = port->fabric->vf_id; aen_data.lport.roles = role; diff --git a/drivers/scsi/bfa/bfa_ioc.c b/drivers/scsi/bfa/bfa_ioc.c index 4d9a47ccffe9..e038bc9769f6 100644 --- a/drivers/scsi/bfa/bfa_ioc.c +++ b/drivers/scsi/bfa/bfa_ioc.c @@ -1679,46 +1679,28 @@ bfa_ioc_get_adapter_attr(struct bfa_ioc_s *ioc, struct bfa_adapter_attr_s *ad_attr) { struct bfi_ioc_attr_s *ioc_attr; - char model[BFA_ADAPTER_MODEL_NAME_LEN]; ioc_attr = ioc->attr; - bfa_os_memcpy((void *)&ad_attr->serial_num, - (void *)ioc_attr->brcd_serialnum, - BFA_ADAPTER_SERIAL_NUM_LEN); - - bfa_os_memcpy(&ad_attr->fw_ver, ioc_attr->fw_version, BFA_VERSION_LEN); - bfa_os_memcpy(&ad_attr->optrom_ver, ioc_attr->optrom_version, - BFA_VERSION_LEN); - bfa_os_memcpy(&ad_attr->manufacturer, BFA_MFG_NAME, - BFA_ADAPTER_MFG_NAME_LEN); + + bfa_ioc_get_adapter_serial_num(ioc, ad_attr->serial_num); + bfa_ioc_get_adapter_fw_ver(ioc, ad_attr->fw_ver); + bfa_ioc_get_adapter_optrom_ver(ioc, ad_attr->optrom_ver); + bfa_ioc_get_adapter_manufacturer(ioc, ad_attr->manufacturer); bfa_os_memcpy(&ad_attr->vpd, &ioc_attr->vpd, sizeof(struct bfa_mfg_vpd_s)); - ad_attr->nports = BFI_ADAPTER_GETP(NPORTS, ioc_attr->adapter_prop); - ad_attr->max_speed = BFI_ADAPTER_GETP(SPEED, ioc_attr->adapter_prop); + ad_attr->nports = bfa_ioc_get_nports(ioc); + ad_attr->max_speed = bfa_ioc_speed_sup(ioc); - /** - * model name - */ - if (BFI_ADAPTER_GETP(SPEED, ioc_attr->adapter_prop) == 10) { - strcpy(model, "BR-10?0"); - model[5] = '0' + ad_attr->nports; - } else { - strcpy(model, "Brocade-??5"); - model[8] = - '0' + BFI_ADAPTER_GETP(SPEED, ioc_attr->adapter_prop); - model[9] = '0' + ad_attr->nports; - } + bfa_ioc_get_adapter_model(ioc, ad_attr->model); + /* For now, model descr uses same model string */ + bfa_ioc_get_adapter_model(ioc, ad_attr->model_descr); if (BFI_ADAPTER_IS_SPECIAL(ioc_attr->adapter_prop)) ad_attr->prototype = 1; else ad_attr->prototype = 0; - bfa_os_memcpy(&ad_attr->model, model, BFA_ADAPTER_MODEL_NAME_LEN); - bfa_os_memcpy(&ad_attr->model_descr, &ad_attr->model, - BFA_ADAPTER_MODEL_NAME_LEN); - ad_attr->pwwn = bfa_ioc_get_pwwn(ioc); ad_attr->mac = bfa_ioc_get_mac(ioc); @@ -1726,12 +1708,8 @@ bfa_ioc_get_adapter_attr(struct bfa_ioc_s *ioc, ad_attr->pcie_lanes = ioc_attr->pcie_lanes; ad_attr->pcie_lanes_orig = ioc_attr->pcie_lanes_orig; ad_attr->asic_rev = ioc_attr->asic_rev; - ad_attr->hw_ver[0] = 'R'; - ad_attr->hw_ver[1] = 'e'; - ad_attr->hw_ver[2] = 'v'; - ad_attr->hw_ver[3] = '-'; - ad_attr->hw_ver[4] = ioc_attr->asic_rev; - ad_attr->hw_ver[5] = '\0'; + + bfa_ioc_get_pci_chip_rev(ioc, ad_attr->hw_ver); ad_attr->cna_capable = ioc->cna; } @@ -1751,12 +1729,92 @@ bfa_ioc_get_type(struct bfa_ioc_s *ioc) } } +void +bfa_ioc_get_adapter_serial_num(struct bfa_ioc_s *ioc, char *serial_num) +{ + bfa_os_memset((void *)serial_num, 0, BFA_ADAPTER_SERIAL_NUM_LEN); + bfa_os_memcpy((void *)serial_num, + (void *)ioc->attr->brcd_serialnum, + BFA_ADAPTER_SERIAL_NUM_LEN); +} + +void +bfa_ioc_get_adapter_fw_ver(struct bfa_ioc_s *ioc, char *fw_ver) +{ + bfa_os_memset((void *)fw_ver, 0, BFA_VERSION_LEN); + bfa_os_memcpy(fw_ver, ioc->attr->fw_version, BFA_VERSION_LEN); +} + +void +bfa_ioc_get_pci_chip_rev(struct bfa_ioc_s *ioc, char *chip_rev) +{ + bfa_assert(chip_rev); + + bfa_os_memset((void *)chip_rev, 0, BFA_IOC_CHIP_REV_LEN); + + chip_rev[0] = 'R'; + chip_rev[1] = 'e'; + chip_rev[2] = 'v'; + chip_rev[3] = '-'; + chip_rev[4] = ioc->attr->asic_rev; + chip_rev[5] = '\0'; +} + +void +bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc_s *ioc, char *optrom_ver) +{ + bfa_os_memset((void *)optrom_ver, 0, BFA_VERSION_LEN); + bfa_os_memcpy(optrom_ver, ioc->attr->optrom_version, + BFA_VERSION_LEN); +} + +void +bfa_ioc_get_adapter_manufacturer(struct bfa_ioc_s *ioc, char *manufacturer) +{ + bfa_os_memset((void *)manufacturer, 0, BFA_ADAPTER_MFG_NAME_LEN); + bfa_os_memcpy(manufacturer, BFA_MFG_NAME, BFA_ADAPTER_MFG_NAME_LEN); +} + +void +bfa_ioc_get_adapter_model(struct bfa_ioc_s *ioc, char *model) +{ + struct bfi_ioc_attr_s *ioc_attr; + u8 nports; + u8 max_speed; + + bfa_assert(model); + bfa_os_memset((void *)model, 0, BFA_ADAPTER_MODEL_NAME_LEN); + + ioc_attr = ioc->attr; + + nports = bfa_ioc_get_nports(ioc); + max_speed = bfa_ioc_speed_sup(ioc); + + /** + * model name + */ + if (max_speed == 10) { + strcpy(model, "BR-10?0"); + model[5] = '0' + nports; + } else { + strcpy(model, "Brocade-??5"); + model[8] = '0' + max_speed; + model[9] = '0' + nports; + } +} + +enum bfa_ioc_state +bfa_ioc_get_state(struct bfa_ioc_s *ioc) +{ + return bfa_sm_to_state(ioc_sm_table, ioc->fsm); +} + void bfa_ioc_get_attr(struct bfa_ioc_s *ioc, struct bfa_ioc_attr_s *ioc_attr) { bfa_os_memset((void *)ioc_attr, 0, sizeof(struct bfa_ioc_attr_s)); - ioc_attr->state = bfa_sm_to_state(ioc_sm_table, ioc->fsm); + ioc_attr->state = bfa_ioc_get_state(ioc); ioc_attr->port_id = ioc->port_id; ioc_attr->ioc_type = bfa_ioc_get_type(ioc); @@ -1765,12 +1823,7 @@ bfa_ioc_get_attr(struct bfa_ioc_s *ioc, struct bfa_ioc_attr_s *ioc_attr) ioc_attr->pci_attr.device_id = ioc->pcidev.device_id; ioc_attr->pci_attr.pcifn = ioc->pcidev.pci_func; - ioc_attr->pci_attr.chip_rev[0] = 'R'; - ioc_attr->pci_attr.chip_rev[1] = 'e'; - ioc_attr->pci_attr.chip_rev[2] = 'v'; - ioc_attr->pci_attr.chip_rev[3] = '-'; - ioc_attr->pci_attr.chip_rev[4] = ioc_attr->adapter_attr.asic_rev; - ioc_attr->pci_attr.chip_rev[5] = '\0'; + bfa_ioc_get_pci_chip_rev(ioc, ioc_attr->pci_attr.chip_rev); } /** @@ -1877,25 +1930,7 @@ bfa_ioc_aen_post(struct bfa_ioc_s *ioc, enum bfa_ioc_aen_event event) s32 inst_num = 0; enum bfa_ioc_type_e ioc_type; - switch (event) { - case BFA_IOC_AEN_HBGOOD: - bfa_log(logmod, BFA_AEN_IOC_HBGOOD, inst_num); - break; - case BFA_IOC_AEN_HBFAIL: - bfa_log(logmod, BFA_AEN_IOC_HBFAIL, inst_num); - break; - case BFA_IOC_AEN_ENABLE: - bfa_log(logmod, BFA_AEN_IOC_ENABLE, inst_num); - break; - case BFA_IOC_AEN_DISABLE: - bfa_log(logmod, BFA_AEN_IOC_DISABLE, inst_num); - break; - case BFA_IOC_AEN_FWMISMATCH: - bfa_log(logmod, BFA_AEN_IOC_FWMISMATCH, inst_num); - break; - default: - break; - } + bfa_log(logmod, BFA_LOG_CREATE_ID(BFA_AEN_CAT_IOC, event), inst_num); memset(&aen_data.ioc.pwwn, 0, sizeof(aen_data.ioc.pwwn)); memset(&aen_data.ioc.mac, 0, sizeof(aen_data.ioc.mac)); diff --git a/drivers/scsi/bfa/bfa_ioc.h b/drivers/scsi/bfa/bfa_ioc.h index 4b73efad1ee5..d0804406ea1a 100644 --- a/drivers/scsi/bfa/bfa_ioc.h +++ b/drivers/scsi/bfa/bfa_ioc.h @@ -263,6 +263,16 @@ bfa_boolean_t bfa_ioc_is_disabled(struct bfa_ioc_s *ioc); bfa_boolean_t bfa_ioc_fw_mismatch(struct bfa_ioc_s *ioc); bfa_boolean_t bfa_ioc_adapter_is_disabled(struct bfa_ioc_s *ioc); void bfa_ioc_cfg_complete(struct bfa_ioc_s *ioc); +enum bfa_ioc_type_e bfa_ioc_get_type(struct bfa_ioc_s *ioc); +void bfa_ioc_get_adapter_serial_num(struct bfa_ioc_s *ioc, char *serial_num); +void bfa_ioc_get_adapter_fw_ver(struct bfa_ioc_s *ioc, char *fw_ver); +void bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc_s *ioc, char *optrom_ver); +void bfa_ioc_get_adapter_model(struct bfa_ioc_s *ioc, char *model); +void bfa_ioc_get_adapter_manufacturer(struct bfa_ioc_s *ioc, + char *manufacturer); +void bfa_ioc_get_pci_chip_rev(struct bfa_ioc_s *ioc, char *chip_rev); +enum bfa_ioc_state bfa_ioc_get_state(struct bfa_ioc_s *ioc); + void bfa_ioc_get_attr(struct bfa_ioc_s *ioc, struct bfa_ioc_attr_s *ioc_attr); void bfa_ioc_get_adapter_attr(struct bfa_ioc_s *ioc, struct bfa_adapter_attr_s *ad_attr); diff --git a/drivers/scsi/bfa/bfa_lps.c b/drivers/scsi/bfa/bfa_lps.c index d2d48a619c30..ad06f6189092 100644 --- a/drivers/scsi/bfa/bfa_lps.c +++ b/drivers/scsi/bfa/bfa_lps.c @@ -631,11 +631,7 @@ bfa_lps_cvl_event(struct bfa_lps_s *lps) u32 bfa_lps_get_max_vport(struct bfa_s *bfa) { - struct bfa_ioc_attr_s ioc_attr; - - bfa_get_attr(bfa, &ioc_attr); - - if (ioc_attr.pci_attr.device_id == BFA_PCI_DEVICE_ID_CT) + if (bfa_ioc_devid(&bfa->ioc) == BFA_PCI_DEVICE_ID_CT) return BFA_LPS_MAX_VPORTS_SUPP_CT; else return BFA_LPS_MAX_VPORTS_SUPP_CB; diff --git a/drivers/scsi/bfa/bfad.c b/drivers/scsi/bfa/bfad.c index a8a529d5fea4..6bff08ea4029 100644 --- a/drivers/scsi/bfa/bfad.c +++ b/drivers/scsi/bfa/bfad.c @@ -978,7 +978,6 @@ bfad_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid) { struct bfad_s *bfad; int error = -ENODEV, retval; - char buf[16]; /* * For single port cards - only claim function 0 @@ -1009,8 +1008,7 @@ bfad_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid) bfa_trc(bfad, bfad_inst); bfad->logmod = &bfad->log_data; - sprintf(buf, "%d", bfad_inst); - bfa_log_init(bfad->logmod, buf, bfa_os_printf); + bfa_log_init(bfad->logmod, (char *)pci_name(pdev), bfa_os_printf); bfad_drv_log_level_set(bfad); diff --git a/drivers/scsi/bfa/bfad_attr.c b/drivers/scsi/bfa/bfad_attr.c index a691133c31a2..dd5cb20d4b37 100644 --- a/drivers/scsi/bfa/bfad_attr.c +++ b/drivers/scsi/bfa/bfad_attr.c @@ -424,12 +424,10 @@ bfad_im_serial_num_show(struct device *dev, struct device_attribute *attr, struct bfad_im_port_s *im_port = (struct bfad_im_port_s *) shost->hostdata[0]; struct bfad_s *bfad = im_port->bfad; - struct bfa_ioc_attr_s ioc_attr; + char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN]; - memset(&ioc_attr, 0, sizeof(ioc_attr)); - bfa_get_attr(&bfad->bfa, &ioc_attr); - return snprintf(buf, PAGE_SIZE, "%s\n", - ioc_attr.adapter_attr.serial_num); + bfa_get_adapter_serial_num(&bfad->bfa, serial_num); + return snprintf(buf, PAGE_SIZE, "%s\n", serial_num); } static ssize_t @@ -440,11 +438,10 @@ bfad_im_model_show(struct device *dev, struct device_attribute *attr, struct bfad_im_port_s *im_port = (struct bfad_im_port_s *) shost->hostdata[0]; struct bfad_s *bfad = im_port->bfad; - struct bfa_ioc_attr_s ioc_attr; + char model[BFA_ADAPTER_MODEL_NAME_LEN]; - memset(&ioc_attr, 0, sizeof(ioc_attr)); - bfa_get_attr(&bfad->bfa, &ioc_attr); - return snprintf(buf, PAGE_SIZE, "%s\n", ioc_attr.adapter_attr.model); + bfa_get_adapter_model(&bfad->bfa, model); + return snprintf(buf, PAGE_SIZE, "%s\n", model); } static ssize_t @@ -455,12 +452,10 @@ bfad_im_model_desc_show(struct device *dev, struct device_attribute *attr, struct bfad_im_port_s *im_port = (struct bfad_im_port_s *) shost->hostdata[0]; struct bfad_s *bfad = im_port->bfad; - struct bfa_ioc_attr_s ioc_attr; + char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN]; - memset(&ioc_attr, 0, sizeof(ioc_attr)); - bfa_get_attr(&bfad->bfa, &ioc_attr); - return snprintf(buf, PAGE_SIZE, "%s\n", - ioc_attr.adapter_attr.model_descr); + bfa_get_adapter_model(&bfad->bfa, model_descr); + return snprintf(buf, PAGE_SIZE, "%s\n", model_descr); } static ssize_t @@ -485,14 +480,13 @@ bfad_im_symbolic_name_show(struct device *dev, struct device_attribute *attr, struct bfad_im_port_s *im_port = (struct bfad_im_port_s *) shost->hostdata[0]; struct bfad_s *bfad = im_port->bfad; - struct bfa_ioc_attr_s ioc_attr; - - memset(&ioc_attr, 0, sizeof(ioc_attr)); - bfa_get_attr(&bfad->bfa, &ioc_attr); + char model[BFA_ADAPTER_MODEL_NAME_LEN]; + char fw_ver[BFA_VERSION_LEN]; + bfa_get_adapter_model(&bfad->bfa, model); + bfa_get_adapter_fw_ver(&bfad->bfa, fw_ver); return snprintf(buf, PAGE_SIZE, "Brocade %s FV%s DV%s\n", - ioc_attr.adapter_attr.model, - ioc_attr.adapter_attr.fw_ver, BFAD_DRIVER_VERSION); + model, fw_ver, BFAD_DRIVER_VERSION); } static ssize_t @@ -503,11 +497,10 @@ bfad_im_hw_version_show(struct device *dev, struct device_attribute *attr, struct bfad_im_port_s *im_port = (struct bfad_im_port_s *) shost->hostdata[0]; struct bfad_s *bfad = im_port->bfad; - struct bfa_ioc_attr_s ioc_attr; + char hw_ver[BFA_VERSION_LEN]; - memset(&ioc_attr, 0, sizeof(ioc_attr)); - bfa_get_attr(&bfad->bfa, &ioc_attr); - return snprintf(buf, PAGE_SIZE, "%s\n", ioc_attr.adapter_attr.hw_ver); + bfa_get_pci_chip_rev(&bfad->bfa, hw_ver); + return snprintf(buf, PAGE_SIZE, "%s\n", hw_ver); } static ssize_t @@ -525,12 +518,10 @@ bfad_im_optionrom_version_show(struct device *dev, struct bfad_im_port_s *im_port = (struct bfad_im_port_s *) shost->hostdata[0]; struct bfad_s *bfad = im_port->bfad; - struct bfa_ioc_attr_s ioc_attr; + char optrom_ver[BFA_VERSION_LEN]; - memset(&ioc_attr, 0, sizeof(ioc_attr)); - bfa_get_attr(&bfad->bfa, &ioc_attr); - return snprintf(buf, PAGE_SIZE, "%s\n", - ioc_attr.adapter_attr.optrom_ver); + bfa_get_adapter_optrom_ver(&bfad->bfa, optrom_ver); + return snprintf(buf, PAGE_SIZE, "%s\n", optrom_ver); } static ssize_t @@ -541,11 +532,10 @@ bfad_im_fw_version_show(struct device *dev, struct device_attribute *attr, struct bfad_im_port_s *im_port = (struct bfad_im_port_s *) shost->hostdata[0]; struct bfad_s *bfad = im_port->bfad; - struct bfa_ioc_attr_s ioc_attr; + char fw_ver[BFA_VERSION_LEN]; - memset(&ioc_attr, 0, sizeof(ioc_attr)); - bfa_get_attr(&bfad->bfa, &ioc_attr); - return snprintf(buf, PAGE_SIZE, "%s\n", ioc_attr.adapter_attr.fw_ver); + bfa_get_adapter_fw_ver(&bfad->bfa, fw_ver); + return snprintf(buf, PAGE_SIZE, "%s\n", fw_ver); } static ssize_t @@ -556,11 +546,9 @@ bfad_im_num_of_ports_show(struct device *dev, struct device_attribute *attr, struct bfad_im_port_s *im_port = (struct bfad_im_port_s *) shost->hostdata[0]; struct bfad_s *bfad = im_port->bfad; - struct bfa_ioc_attr_s ioc_attr; - memset(&ioc_attr, 0, sizeof(ioc_attr)); - bfa_get_attr(&bfad->bfa, &ioc_attr); - return snprintf(buf, PAGE_SIZE, "%d\n", ioc_attr.adapter_attr.nports); + return snprintf(buf, PAGE_SIZE, "%d\n", + bfa_get_nports(&bfad->bfa)); } static ssize_t diff --git a/drivers/scsi/bfa/bfad_drv.h b/drivers/scsi/bfa/bfad_drv.h index 94f4d84c71c9..8617a1aa8b25 100644 --- a/drivers/scsi/bfa/bfad_drv.h +++ b/drivers/scsi/bfa/bfad_drv.h @@ -139,6 +139,18 @@ struct bfad_cfg_param_s { u32 binding_method; }; +union bfad_tmp_buf { + /* From struct bfa_adapter_attr_s */ + char manufacturer[BFA_ADAPTER_MFG_NAME_LEN]; + char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN]; + char model[BFA_ADAPTER_MODEL_NAME_LEN]; + char fw_ver[BFA_VERSION_LEN]; + char optrom_ver[BFA_VERSION_LEN]; + + /* From struct bfa_ioc_pci_attr_s */ + u8 chip_rev[BFA_IOC_CHIP_REV_LEN]; /* chip revision */ +}; + /* * BFAD (PCI function) data structure */ @@ -182,6 +194,7 @@ struct bfad_s { struct bfa_plog_s plog_buf; int ref_count; bfa_boolean_t ipfc_enabled; + union bfad_tmp_buf tmp_buf; struct fc_host_statistics link_stats; struct kobject *bfa_kobj; diff --git a/drivers/scsi/bfa/bfad_im.c b/drivers/scsi/bfa/bfad_im.c index 23390b40b9c3..cee3d89d1412 100644 --- a/drivers/scsi/bfa/bfad_im.c +++ b/drivers/scsi/bfa/bfad_im.c @@ -167,17 +167,15 @@ bfad_im_info(struct Scsi_Host *shost) static char bfa_buf[256]; struct bfad_im_port_s *im_port = (struct bfad_im_port_s *) shost->hostdata[0]; - struct bfa_ioc_attr_s ioc_attr; struct bfad_s *bfad = im_port->bfad; + char model[BFA_ADAPTER_MODEL_NAME_LEN]; - memset(&ioc_attr, 0, sizeof(ioc_attr)); - bfa_get_attr(&bfad->bfa, &ioc_attr); + bfa_get_adapter_model(&bfad->bfa, model); memset(bfa_buf, 0, sizeof(bfa_buf)); snprintf(bfa_buf, sizeof(bfa_buf), - "Brocade FC/FCOE Adapter, " "model: %s hwpath: %s driver: %s", - ioc_attr.adapter_attr.model, bfad->pci_name, - BFAD_DRIVER_VERSION); + "Brocade FC/FCOE Adapter, " "model: %s hwpath: %s driver: %s", + model, bfad->pci_name, BFAD_DRIVER_VERSION); return bfa_buf; } @@ -931,10 +929,9 @@ bfad_os_fc_host_init(struct bfad_im_port_s *im_port) struct Scsi_Host *host = im_port->shost; struct bfad_s *bfad = im_port->bfad; struct bfad_port_s *port = im_port->port; - union attr { - struct bfa_pport_attr_s pattr; - struct bfa_ioc_attr_s ioc_attr; - } attr; + struct bfa_pport_attr_s pattr; + char model[BFA_ADAPTER_MODEL_NAME_LEN]; + char fw_ver[BFA_VERSION_LEN]; fc_host_node_name(host) = bfa_os_htonll((bfa_fcs_port_get_nwwn(port->fcs_port))); @@ -954,20 +951,18 @@ bfad_os_fc_host_init(struct bfad_im_port_s *im_port) /* For fibre channel services type 0x20 */ fc_host_supported_fc4s(host)[7] = 1; - memset(&attr.ioc_attr, 0, sizeof(attr.ioc_attr)); - bfa_get_attr(&bfad->bfa, &attr.ioc_attr); + bfa_get_adapter_model(&bfad->bfa, model); + bfa_get_adapter_fw_ver(&bfad->bfa, fw_ver); sprintf(fc_host_symbolic_name(host), "Brocade %s FV%s DV%s", - attr.ioc_attr.adapter_attr.model, - attr.ioc_attr.adapter_attr.fw_ver, BFAD_DRIVER_VERSION); + model, fw_ver, BFAD_DRIVER_VERSION); fc_host_supported_speeds(host) = 0; fc_host_supported_speeds(host) |= FC_PORTSPEED_8GBIT | FC_PORTSPEED_4GBIT | FC_PORTSPEED_2GBIT | FC_PORTSPEED_1GBIT; - memset(&attr.pattr, 0, sizeof(attr.pattr)); - bfa_fcport_get_attr(&bfad->bfa, &attr.pattr); - fc_host_maxframe_size(host) = attr.pattr.pport_cfg.maxfrsize; + bfa_fcport_get_attr(&bfad->bfa, &pattr); + fc_host_maxframe_size(host) = pattr.pport_cfg.maxfrsize; } static void diff --git a/drivers/scsi/bfa/fabric.c b/drivers/scsi/bfa/fabric.c index e1a4b312e9d4..b4e05ad1b47e 100644 --- a/drivers/scsi/bfa/fabric.c +++ b/drivers/scsi/bfa/fabric.c @@ -1235,14 +1235,8 @@ bfa_fcs_fabric_aen_post(struct bfa_fcs_port_s *port, wwn2str(pwwn_ptr, pwwn); wwn2str(fwwn_ptr, fwwn); - switch (event) { - case BFA_PORT_AEN_FABRIC_NAME_CHANGE: - bfa_log(logmod, BFA_AEN_PORT_FABRIC_NAME_CHANGE, pwwn_ptr, - fwwn_ptr); - break; - default: - break; - } + bfa_log(logmod, BFA_LOG_CREATE_ID(BFA_AEN_CAT_PORT, event), + pwwn_ptr, fwwn_ptr); aen_data.port.pwwn = pwwn; aen_data.port.fwwn = fwwn; diff --git a/drivers/scsi/bfa/fcpim.c b/drivers/scsi/bfa/fcpim.c index 71d23d19bc9d..ef50ec2a1950 100644 --- a/drivers/scsi/bfa/fcpim.c +++ b/drivers/scsi/bfa/fcpim.c @@ -385,19 +385,8 @@ bfa_fcs_itnim_aen_post(struct bfa_fcs_itnim_s *itnim, wwn2str(lpwwn_ptr, lpwwn); wwn2str(rpwwn_ptr, rpwwn); - switch (event) { - case BFA_ITNIM_AEN_ONLINE: - bfa_log(logmod, BFA_AEN_ITNIM_ONLINE, rpwwn_ptr, lpwwn_ptr); - break; - case BFA_ITNIM_AEN_OFFLINE: - bfa_log(logmod, BFA_AEN_ITNIM_OFFLINE, rpwwn_ptr, lpwwn_ptr); - break; - case BFA_ITNIM_AEN_DISCONNECT: - bfa_log(logmod, BFA_AEN_ITNIM_DISCONNECT, rpwwn_ptr, lpwwn_ptr); - break; - default: - break; - } + bfa_log(logmod, BFA_LOG_CREATE_ID(BFA_AEN_CAT_ITNIM, event), + rpwwn_ptr, lpwwn_ptr); aen_data.itnim.vf_id = rport->port->fabric->vf_id; aen_data.itnim.ppwwn = diff --git a/drivers/scsi/bfa/include/bfa.h b/drivers/scsi/bfa/include/bfa.h index 17654cae0c75..1f5966cfbd16 100644 --- a/drivers/scsi/bfa/include/bfa.h +++ b/drivers/scsi/bfa/include/bfa.h @@ -106,6 +106,26 @@ struct bfa_sge_s { bfa_ioc_fetch_stats(&(__bfa)->ioc, __ioc_stats) #define bfa_ioc_clear_stats(__bfa) \ bfa_ioc_clr_stats(&(__bfa)->ioc) +#define bfa_get_nports(__bfa) \ + bfa_ioc_get_nports(&(__bfa)->ioc) +#define bfa_get_adapter_manufacturer(__bfa, __manufacturer) \ + bfa_ioc_get_adapter_manufacturer(&(__bfa)->ioc, __manufacturer) +#define bfa_get_adapter_model(__bfa, __model) \ + bfa_ioc_get_adapter_model(&(__bfa)->ioc, __model) +#define bfa_get_adapter_serial_num(__bfa, __serial_num) \ + bfa_ioc_get_adapter_serial_num(&(__bfa)->ioc, __serial_num) +#define bfa_get_adapter_fw_ver(__bfa, __fw_ver) \ + bfa_ioc_get_adapter_fw_ver(&(__bfa)->ioc, __fw_ver) +#define bfa_get_adapter_optrom_ver(__bfa, __optrom_ver) \ + bfa_ioc_get_adapter_optrom_ver(&(__bfa)->ioc, __optrom_ver) +#define bfa_get_pci_chip_rev(__bfa, __chip_rev) \ + bfa_ioc_get_pci_chip_rev(&(__bfa)->ioc, __chip_rev) +#define bfa_get_ioc_state(__bfa) \ + bfa_ioc_get_state(&(__bfa)->ioc) +#define bfa_get_type(__bfa) \ + bfa_ioc_get_type(&(__bfa)->ioc) +#define bfa_get_mac(__bfa) \ + bfa_ioc_get_mac(&(__bfa)->ioc) /* * bfa API functions diff --git a/drivers/scsi/bfa/include/cs/bfa_log.h b/drivers/scsi/bfa/include/cs/bfa_log.h index 761cbe22130a..bc334e0a93fa 100644 --- a/drivers/scsi/bfa/include/cs/bfa_log.h +++ b/drivers/scsi/bfa/include/cs/bfa_log.h @@ -157,7 +157,7 @@ typedef void (*bfa_log_cb_t)(struct bfa_log_mod_s *log_mod, u32 msg_id, struct bfa_log_mod_s { - char instance_info[16]; /* instance info */ + char instance_info[BFA_STRING_32]; /* instance info */ int log_level[BFA_LOG_MODULE_ID_MAX + 1]; /* log level for modules */ bfa_log_cb_t cbfn; /* callback function */ diff --git a/drivers/scsi/bfa/rport.c b/drivers/scsi/bfa/rport.c index 8c5969c86934..8e73dd9a625a 100644 --- a/drivers/scsi/bfa/rport.c +++ b/drivers/scsi/bfa/rport.c @@ -2039,13 +2039,10 @@ bfa_fcs_rport_aen_post(struct bfa_fcs_rport_s *rport, switch (event) { case BFA_RPORT_AEN_ONLINE: - bfa_log(logmod, BFA_AEN_RPORT_ONLINE, rpwwn_ptr, lpwwn_ptr); - break; case BFA_RPORT_AEN_OFFLINE: - bfa_log(logmod, BFA_AEN_RPORT_OFFLINE, rpwwn_ptr, lpwwn_ptr); - break; case BFA_RPORT_AEN_DISCONNECT: - bfa_log(logmod, BFA_AEN_RPORT_DISCONNECT, rpwwn_ptr, lpwwn_ptr); + bfa_log(logmod, BFA_LOG_CREATE_ID(BFA_AEN_CAT_RPORT, event), + rpwwn_ptr, lpwwn_ptr); break; case BFA_RPORT_AEN_QOS_PRIO: aen_data.rport.priv.qos = data->priv.qos; diff --git a/drivers/scsi/bfa/vport.c b/drivers/scsi/bfa/vport.c index c5e534eb1620..27cd619a227a 100644 --- a/drivers/scsi/bfa/vport.c +++ b/drivers/scsi/bfa/vport.c @@ -447,22 +447,8 @@ bfa_fcs_vport_aen_post(bfa_fcs_lport_t *port, enum bfa_lport_aen_event event) bfa_assert(role <= BFA_PORT_ROLE_FCP_MAX); - switch (event) { - case BFA_LPORT_AEN_NPIV_DUP_WWN: - bfa_log(logmod, BFA_AEN_LPORT_NPIV_DUP_WWN, lpwwn_ptr, - role_str[role / 2]); - break; - case BFA_LPORT_AEN_NPIV_FABRIC_MAX: - bfa_log(logmod, BFA_AEN_LPORT_NPIV_FABRIC_MAX, lpwwn_ptr, - role_str[role / 2]); - break; - case BFA_LPORT_AEN_NPIV_UNKNOWN: - bfa_log(logmod, BFA_AEN_LPORT_NPIV_UNKNOWN, lpwwn_ptr, - role_str[role / 2]); - break; - default: - break; - } + bfa_log(logmod, BFA_LOG_CREATE_ID(BFA_AEN_CAT_LPORT, event), lpwwn_ptr, + role_str[role/2]); aen_data.lport.vf_id = port->fabric->vf_id; aen_data.lport.roles = role; -- cgit v1.2.3 From ca8b4327e405820966971236224db0e0724b5673 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:38:07 -0800 Subject: [SCSI] bfa: Modified the portstats get/clear logic Modified the portstats get/clear logic for port physical/FCoE/QoS stats. Added more stats to FC Fixed some issues with FCoE stats collection. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_fcport.c | 732 +++++++++---------------- drivers/scsi/bfa/bfa_port_priv.h | 41 +- drivers/scsi/bfa/bfad_attr.c | 5 +- drivers/scsi/bfa/include/bfa_svc.h | 24 +- drivers/scsi/bfa/include/bfi/bfi.h | 4 +- drivers/scsi/bfa/include/bfi/bfi_pport.h | 177 ++---- drivers/scsi/bfa/include/defs/bfa_defs_pport.h | 128 ++--- 7 files changed, 405 insertions(+), 706 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_fcport.c b/drivers/scsi/bfa/bfa_fcport.c index 0da612010787..d109e651b1c5 100644 --- a/drivers/scsi/bfa/bfa_fcport.c +++ b/drivers/scsi/bfa/bfa_fcport.c @@ -47,16 +47,10 @@ static void bfa_fcport_callback(struct bfa_fcport_s *fcport, enum bfa_pport_linkstate event); static void bfa_fcport_queue_cb(struct bfa_fcport_ln_s *ln, enum bfa_pport_linkstate event); -static void __bfa_cb_fcport_stats(void *cbarg, bfa_boolean_t complete); static void __bfa_cb_fcport_stats_clr(void *cbarg, bfa_boolean_t complete); -static void bfa_fcport_stats_timeout(void *cbarg); +static void bfa_fcport_stats_get_timeout(void *cbarg); static void bfa_fcport_stats_clr_timeout(void *cbarg); -static void __bfa_cb_port_stats(void *cbarg, bfa_boolean_t complete); -static void __bfa_cb_port_stats_clr(void *cbarg, bfa_boolean_t complete); -static void bfa_port_stats_timeout(void *cbarg); -static void bfa_port_stats_clr_timeout(void *cbarg); - /** * bfa_pport_private */ @@ -303,7 +297,7 @@ static void bfa_fcport_sm_linkdown(struct bfa_fcport_s *fcport, enum bfa_fcport_sm_event event) { - struct bfi_pport_event_s *pevent = fcport->event_arg.i2hmsg.event; + struct bfi_fcport_event_s *pevent = fcport->event_arg.i2hmsg.event; bfa_trc(fcport->bfa, event); switch (event) { @@ -819,8 +813,32 @@ __bfa_cb_fcport_event(void *cbarg, bfa_boolean_t complete) bfa_sm_send_event(ln, BFA_FCPORT_LN_SM_NOTIFICATION); } -#define PPORT_STATS_DMA_SZ (BFA_ROUNDUP(sizeof(union bfa_fcport_stats_u), \ - BFA_CACHELINE_SZ)) +static void +bfa_fcport_callback(struct bfa_fcport_s *fcport, enum bfa_pport_linkstate event) +{ + if (fcport->bfa->fcs) { + fcport->event_cbfn(fcport->event_cbarg, event); + return; + } + + switch (event) { + case BFA_PPORT_LINKUP: + bfa_sm_send_event(&fcport->ln, BFA_FCPORT_LN_SM_LINKUP); + break; + case BFA_PPORT_LINKDOWN: + bfa_sm_send_event(&fcport->ln, BFA_FCPORT_LN_SM_LINKDOWN); + break; + default: + bfa_assert(0); + } +} + +static void +bfa_fcport_queue_cb(struct bfa_fcport_ln_s *ln, enum bfa_pport_linkstate event) +{ + ln->ln_event = event; + bfa_cb_queue(ln->fcport->bfa, &ln->ln_qe, __bfa_cb_fcport_event, ln); +} #define FCPORT_STATS_DMA_SZ (BFA_ROUNDUP(sizeof(union bfa_fcport_stats_u), \ BFA_CACHELINE_SZ)) @@ -829,8 +847,7 @@ static void bfa_fcport_meminfo(struct bfa_iocfc_cfg_s *cfg, u32 *ndm_len, u32 *dm_len) { - *dm_len += PPORT_STATS_DMA_SZ; - *dm_len += PPORT_STATS_DMA_SZ; + *dm_len += FCPORT_STATS_DMA_SZ; } static void @@ -852,16 +869,7 @@ bfa_fcport_mem_claim(struct bfa_fcport_s *fcport, struct bfa_meminfo_s *meminfo) fcport->stats_kva = dm_kva; fcport->stats_pa = dm_pa; - fcport->stats = (union bfa_pport_stats_u *)dm_kva; - - dm_kva += PPORT_STATS_DMA_SZ; - dm_pa += PPORT_STATS_DMA_SZ; - - /* FC port stats */ - - fcport->fcport_stats_kva = dm_kva; - fcport->fcport_stats_pa = dm_pa; - fcport->fcport_stats = (union bfa_fcport_stats_u *) dm_kva; + fcport->stats = (union bfa_fcport_stats_u *)dm_kva; dm_kva += FCPORT_STATS_DMA_SZ; dm_pa += FCPORT_STATS_DMA_SZ; @@ -957,7 +965,7 @@ bfa_fcport_iocdisable(struct bfa_s *bfa) static void bfa_fcport_update_linkinfo(struct bfa_fcport_s *fcport) { - struct bfi_pport_event_s *pevent = fcport->event_arg.i2hmsg.event; + struct bfi_fcport_event_s *pevent = fcport->event_arg.i2hmsg.event; fcport->speed = pevent->link_state.speed; fcport->topology = pevent->link_state.topology; @@ -989,7 +997,7 @@ bfa_fcport_reset_linkinfo(struct bfa_fcport_s *fcport) static bfa_boolean_t bfa_fcport_send_enable(struct bfa_fcport_s *fcport) { - struct bfi_pport_enable_req_s *m; + struct bfi_fcport_enable_req_s *m; /** * Increment message tag before queue check, so that responses to old @@ -1007,15 +1015,14 @@ bfa_fcport_send_enable(struct bfa_fcport_s *fcport) return BFA_FALSE; } - bfi_h2i_set(m->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_ENABLE_REQ, - bfa_lpuid(fcport->bfa)); + bfi_h2i_set(m->mh, BFI_MC_FCPORT, BFI_FCPORT_H2I_ENABLE_REQ, + bfa_lpuid(fcport->bfa)); m->nwwn = fcport->nwwn; m->pwwn = fcport->pwwn; m->port_cfg = fcport->cfg; m->msgtag = fcport->msgtag; m->port_cfg.maxfrsize = bfa_os_htons(fcport->cfg.maxfrsize); bfa_dma_be_addr_set(m->stats_dma_addr, fcport->stats_pa); - bfa_dma_be_addr_set(m->fcport_stats_dma_addr, fcport->fcport_stats_pa); bfa_trc(fcport->bfa, m->stats_dma_addr.a32.addr_lo); bfa_trc(fcport->bfa, m->stats_dma_addr.a32.addr_hi); @@ -1032,7 +1039,7 @@ bfa_fcport_send_enable(struct bfa_fcport_s *fcport) static bfa_boolean_t bfa_fcport_send_disable(struct bfa_fcport_s *fcport) { - bfi_pport_disable_req_t *m; + struct bfi_fcport_req_s *m; /** * Increment message tag before queue check, so that responses to old @@ -1050,8 +1057,8 @@ bfa_fcport_send_disable(struct bfa_fcport_s *fcport) return BFA_FALSE; } - bfi_h2i_set(m->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_DISABLE_REQ, - bfa_lpuid(fcport->bfa)); + bfi_h2i_set(m->mh, BFI_MC_FCPORT, BFI_FCPORT_H2I_DISABLE_REQ, + bfa_lpuid(fcport->bfa)); m->msgtag = fcport->msgtag; /** @@ -1077,7 +1084,7 @@ bfa_fcport_send_txcredit(void *port_cbarg) { struct bfa_fcport_s *fcport = port_cbarg; - struct bfi_pport_set_svc_params_req_s *m; + struct bfi_fcport_set_svc_params_req_s *m; /** * check for room in queue to send request now @@ -1088,8 +1095,8 @@ bfa_fcport_send_txcredit(void *port_cbarg) return; } - bfi_h2i_set(m->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_SET_SVC_PARAMS_REQ, - bfa_lpuid(fcport->bfa)); + bfi_h2i_set(m->mh, BFI_MC_FCPORT, BFI_FCPORT_H2I_SET_SVC_PARAMS_REQ, + bfa_lpuid(fcport->bfa)); m->tx_bbcredit = bfa_os_htons((u16) fcport->cfg.tx_bbcredit); /** @@ -1098,7 +1105,158 @@ bfa_fcport_send_txcredit(void *port_cbarg) bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); } +static void +bfa_fcport_qos_stats_swap(struct bfa_qos_stats_s *d, + struct bfa_qos_stats_s *s) +{ + u32 *dip = (u32 *) d; + u32 *sip = (u32 *) s; + int i; + + /* Now swap the 32 bit fields */ + for (i = 0; i < (sizeof(struct bfa_qos_stats_s)/sizeof(u32)); ++i) + dip[i] = bfa_os_ntohl(sip[i]); +} + +static void +bfa_fcport_fcoe_stats_swap(struct bfa_fcoe_stats_s *d, + struct bfa_fcoe_stats_s *s) +{ + u32 *dip = (u32 *) d; + u32 *sip = (u32 *) s; + int i; + + for (i = 0; i < ((sizeof(struct bfa_fcoe_stats_s))/sizeof(u32)); + i = i + 2) { +#ifdef __BIGENDIAN + dip[i] = bfa_os_ntohl(sip[i]); + dip[i + 1] = bfa_os_ntohl(sip[i + 1]); +#else + dip[i] = bfa_os_ntohl(sip[i + 1]); + dip[i + 1] = bfa_os_ntohl(sip[i]); +#endif + } +} + +static void +__bfa_cb_fcport_stats_get(void *cbarg, bfa_boolean_t complete) +{ + struct bfa_fcport_s *fcport = cbarg; + + if (complete) { + if (fcport->stats_status == BFA_STATUS_OK) { + + /* Swap FC QoS or FCoE stats */ + if (bfa_ioc_get_fcmode(&fcport->bfa->ioc)) + bfa_fcport_qos_stats_swap( + &fcport->stats_ret->fcqos, + &fcport->stats->fcqos); + else + bfa_fcport_fcoe_stats_swap( + &fcport->stats_ret->fcoe, + &fcport->stats->fcoe); + } + fcport->stats_cbfn(fcport->stats_cbarg, fcport->stats_status); + } else { + fcport->stats_busy = BFA_FALSE; + fcport->stats_status = BFA_STATUS_OK; + } +} + +static void +bfa_fcport_stats_get_timeout(void *cbarg) +{ + struct bfa_fcport_s *fcport = (struct bfa_fcport_s *) cbarg; + + bfa_trc(fcport->bfa, fcport->stats_qfull); + + if (fcport->stats_qfull) { + bfa_reqq_wcancel(&fcport->stats_reqq_wait); + fcport->stats_qfull = BFA_FALSE; + } + + fcport->stats_status = BFA_STATUS_ETIMER; + bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, __bfa_cb_fcport_stats_get, + fcport); +} + +static void +bfa_fcport_send_stats_get(void *cbarg) +{ + struct bfa_fcport_s *fcport = (struct bfa_fcport_s *) cbarg; + struct bfi_fcport_req_s *msg; + + msg = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); + + if (!msg) { + fcport->stats_qfull = BFA_TRUE; + bfa_reqq_winit(&fcport->stats_reqq_wait, + bfa_fcport_send_stats_get, fcport); + bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, + &fcport->stats_reqq_wait); + return; + } + fcport->stats_qfull = BFA_FALSE; + + bfa_os_memset(msg, 0, sizeof(struct bfi_fcport_req_s)); + bfi_h2i_set(msg->mh, BFI_MC_FCPORT, BFI_FCPORT_H2I_STATS_GET_REQ, + bfa_lpuid(fcport->bfa)); + bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); +} + +static void +__bfa_cb_fcport_stats_clr(void *cbarg, bfa_boolean_t complete) +{ + struct bfa_fcport_s *fcport = cbarg; + + if (complete) { + fcport->stats_cbfn(fcport->stats_cbarg, fcport->stats_status); + } else { + fcport->stats_busy = BFA_FALSE; + fcport->stats_status = BFA_STATUS_OK; + } +} + +static void +bfa_fcport_stats_clr_timeout(void *cbarg) +{ + struct bfa_fcport_s *fcport = (struct bfa_fcport_s *) cbarg; + + bfa_trc(fcport->bfa, fcport->stats_qfull); + + if (fcport->stats_qfull) { + bfa_reqq_wcancel(&fcport->stats_reqq_wait); + fcport->stats_qfull = BFA_FALSE; + } + + fcport->stats_status = BFA_STATUS_ETIMER; + bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, + __bfa_cb_fcport_stats_clr, fcport); +} + +static void +bfa_fcport_send_stats_clear(void *cbarg) +{ + struct bfa_fcport_s *fcport = (struct bfa_fcport_s *) cbarg; + struct bfi_fcport_req_s *msg; + msg = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); + + if (!msg) { + fcport->stats_qfull = BFA_TRUE; + bfa_reqq_winit(&fcport->stats_reqq_wait, + bfa_fcport_send_stats_clear, fcport); + bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, + &fcport->stats_reqq_wait); + return; + } + fcport->stats_qfull = BFA_FALSE; + + bfa_os_memset(msg, 0, sizeof(struct bfi_fcport_req_s)); + bfi_h2i_set(msg->mh, BFI_MC_FCPORT, BFI_FCPORT_H2I_STATS_CLEAR_REQ, + bfa_lpuid(fcport->bfa)); + bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); +} /** * bfa_pport_public @@ -1111,23 +1269,23 @@ void bfa_fcport_isr(struct bfa_s *bfa, struct bfi_msg_s *msg) { struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - union bfi_pport_i2h_msg_u i2hmsg; + union bfi_fcport_i2h_msg_u i2hmsg; i2hmsg.msg = msg; fcport->event_arg.i2hmsg = i2hmsg; switch (msg->mhdr.msg_id) { - case BFI_PPORT_I2H_ENABLE_RSP: - if (fcport->msgtag == i2hmsg.enable_rsp->msgtag) + case BFI_FCPORT_I2H_ENABLE_RSP: + if (fcport->msgtag == i2hmsg.penable_rsp->msgtag) bfa_sm_send_event(fcport, BFA_FCPORT_SM_FWRSP); break; - case BFI_PPORT_I2H_DISABLE_RSP: - if (fcport->msgtag == i2hmsg.enable_rsp->msgtag) + case BFI_FCPORT_I2H_DISABLE_RSP: + if (fcport->msgtag == i2hmsg.penable_rsp->msgtag) bfa_sm_send_event(fcport, BFA_FCPORT_SM_FWRSP); break; - case BFI_PPORT_I2H_EVENT: + case BFI_FCPORT_I2H_EVENT: switch (i2hmsg.event->link_state.linkstate) { case BFA_PPORT_LINKUP: bfa_sm_send_event(fcport, BFA_FCPORT_SM_LINKUP); @@ -1141,58 +1299,27 @@ bfa_fcport_isr(struct bfa_s *bfa, struct bfi_msg_s *msg) } break; - case BFI_PPORT_I2H_GET_STATS_RSP: - case BFI_PPORT_I2H_GET_QOS_STATS_RSP: - /* - * check for timer pop before processing the rsp - */ - if (fcport->stats_busy == BFA_FALSE - || fcport->stats_status == BFA_STATUS_ETIMER) - break; - - bfa_timer_stop(&fcport->timer); - fcport->stats_status = i2hmsg.getstats_rsp->status; - bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, __bfa_cb_port_stats, - fcport); - break; - case BFI_PPORT_I2H_CLEAR_STATS_RSP: - case BFI_PPORT_I2H_CLEAR_QOS_STATS_RSP: - /* - * check for timer pop before processing the rsp - */ - if (fcport->stats_busy == BFA_FALSE - || fcport->stats_status == BFA_STATUS_ETIMER) - break; - - bfa_timer_stop(&fcport->timer); - fcport->stats_status = BFA_STATUS_OK; - bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, - __bfa_cb_port_stats_clr, fcport); - break; - - case BFI_FCPORT_I2H_GET_STATS_RSP: + case BFI_FCPORT_I2H_STATS_GET_RSP: /* * check for timer pop before processing the rsp */ if (fcport->stats_busy == BFA_FALSE || - fcport->stats_status == BFA_STATUS_ETIMER) { + fcport->stats_status == BFA_STATUS_ETIMER) break; - } bfa_timer_stop(&fcport->timer); - fcport->stats_status = i2hmsg.getstats_rsp->status; + fcport->stats_status = i2hmsg.pstatsget_rsp->status; bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, - __bfa_cb_fcport_stats, fcport); + __bfa_cb_fcport_stats_get, fcport); break; - case BFI_FCPORT_I2H_CLEAR_STATS_RSP: + case BFI_FCPORT_I2H_STATS_CLEAR_RSP: /* * check for timer pop before processing the rsp */ if (fcport->stats_busy == BFA_FALSE || - fcport->stats_status == BFA_STATUS_ETIMER) { + fcport->stats_status == BFA_STATUS_ETIMER) break; - } bfa_timer_stop(&fcport->timer); fcport->stats_status = BFA_STATUS_OK; @@ -1206,8 +1333,6 @@ bfa_fcport_isr(struct bfa_s *bfa, struct bfi_msg_s *msg) } } - - /** * bfa_pport_api */ @@ -1472,329 +1597,13 @@ bfa_fcport_get_attr(struct bfa_s *bfa, struct bfa_pport_attr_s *attr) attr->port_state = BFA_PPORT_ST_FWMISMATCH; } -static void -bfa_port_stats_query(void *cbarg) -{ - struct bfa_fcport_s *fcport = (struct bfa_fcport_s *)cbarg; - bfi_pport_get_stats_req_t *msg; - - msg = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); - - if (!msg) { - fcport->stats_qfull = BFA_TRUE; - bfa_reqq_winit(&fcport->stats_reqq_wait, bfa_port_stats_query, - fcport); - bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, - &fcport->stats_reqq_wait); - return; - } - fcport->stats_qfull = BFA_FALSE; - - bfa_os_memset(msg, 0, sizeof(bfi_pport_get_stats_req_t)); - bfi_h2i_set(msg->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_GET_STATS_REQ, - bfa_lpuid(fcport->bfa)); - bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); -} - -static void -bfa_port_stats_clear(void *cbarg) -{ - struct bfa_fcport_s *fcport = (struct bfa_fcport_s *)cbarg; - bfi_pport_clear_stats_req_t *msg; - - msg = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); - - if (!msg) { - fcport->stats_qfull = BFA_TRUE; - bfa_reqq_winit(&fcport->stats_reqq_wait, bfa_port_stats_clear, - fcport); - bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, - &fcport->stats_reqq_wait); - return; - } - fcport->stats_qfull = BFA_FALSE; - - bfa_os_memset(msg, 0, sizeof(bfi_pport_clear_stats_req_t)); - bfi_h2i_set(msg->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_CLEAR_STATS_REQ, - bfa_lpuid(fcport->bfa)); - bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); -} - -static void -bfa_fcport_stats_query(void *cbarg) -{ - struct bfa_fcport_s *fcport = (struct bfa_fcport_s *) cbarg; - bfi_pport_get_stats_req_t *msg; - - msg = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); - - if (!msg) { - fcport->stats_qfull = BFA_TRUE; - bfa_reqq_winit(&fcport->stats_reqq_wait, - bfa_fcport_stats_query, fcport); - bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, - &fcport->stats_reqq_wait); - return; - } - fcport->stats_qfull = BFA_FALSE; - - bfa_os_memset(msg, 0, sizeof(bfi_pport_get_stats_req_t)); - bfi_h2i_set(msg->mh, BFI_MC_FC_PORT, BFI_FCPORT_H2I_GET_STATS_REQ, - bfa_lpuid(fcport->bfa)); - bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); -} - -static void -bfa_fcport_stats_clear(void *cbarg) -{ - struct bfa_fcport_s *fcport = (struct bfa_fcport_s *) cbarg; - bfi_pport_clear_stats_req_t *msg; - - msg = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); - - if (!msg) { - fcport->stats_qfull = BFA_TRUE; - bfa_reqq_winit(&fcport->stats_reqq_wait, - bfa_fcport_stats_clear, fcport); - bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, - &fcport->stats_reqq_wait); - return; - } - fcport->stats_qfull = BFA_FALSE; - - bfa_os_memset(msg, 0, sizeof(bfi_pport_clear_stats_req_t)); - bfi_h2i_set(msg->mh, BFI_MC_FC_PORT, BFI_FCPORT_H2I_CLEAR_STATS_REQ, - bfa_lpuid(fcport->bfa)); - bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); -} - -static void -bfa_port_qos_stats_clear(void *cbarg) -{ - struct bfa_fcport_s *fcport = (struct bfa_fcport_s *)cbarg; - bfi_pport_clear_qos_stats_req_t *msg; - - msg = bfa_reqq_next(fcport->bfa, BFA_REQQ_PORT); - - if (!msg) { - fcport->stats_qfull = BFA_TRUE; - bfa_reqq_winit(&fcport->stats_reqq_wait, - bfa_port_qos_stats_clear, fcport); - bfa_reqq_wait(fcport->bfa, BFA_REQQ_PORT, - &fcport->stats_reqq_wait); - return; - } - fcport->stats_qfull = BFA_FALSE; - - bfa_os_memset(msg, 0, sizeof(bfi_pport_clear_qos_stats_req_t)); - bfi_h2i_set(msg->mh, BFI_MC_FC_PORT, BFI_PPORT_H2I_CLEAR_QOS_STATS_REQ, - bfa_lpuid(fcport->bfa)); - bfa_reqq_produce(fcport->bfa, BFA_REQQ_PORT); -} - -static void -bfa_fcport_stats_swap(union bfa_fcport_stats_u *d, union bfa_fcport_stats_u *s) -{ - u32 *dip = (u32 *) d; - u32 *sip = (u32 *) s; - int i; - - /* Do 64 bit fields swap first */ - for (i = 0; i < ((sizeof(union bfa_fcport_stats_u) - - sizeof(struct bfa_qos_stats_s))/sizeof(u32)); i = i + 2) { -#ifdef __BIGENDIAN - dip[i] = bfa_os_ntohl(sip[i]); - dip[i + 1] = bfa_os_ntohl(sip[i + 1]); -#else - dip[i] = bfa_os_ntohl(sip[i + 1]); - dip[i + 1] = bfa_os_ntohl(sip[i]); -#endif - } - - /* Now swap the 32 bit fields */ - for (; i < (sizeof(union bfa_fcport_stats_u)/sizeof(u32)); ++i) - dip[i] = bfa_os_ntohl(sip[i]); -} - -static void -bfa_port_stats_swap(union bfa_pport_stats_u *d, union bfa_pport_stats_u *s) -{ - u32 *dip = (u32 *) d; - u32 *sip = (u32 *) s; - int i; - - /* Do 64 bit fields swap first */ - for (i = 0; i < (sizeof(union bfa_pport_stats_u) / sizeof(u32)); - i = i + 2) { -#ifdef __BIGENDIAN - dip[i] = bfa_os_ntohl(sip[i]); - dip[i + 1] = bfa_os_ntohl(sip[i + 1]); -#else - dip[i] = bfa_os_ntohl(sip[i + 1]); - dip[i + 1] = bfa_os_ntohl(sip[i]); -#endif - } -} - -static void -__bfa_cb_port_stats_clr(void *cbarg, bfa_boolean_t complete) -{ - struct bfa_fcport_s *fcport = cbarg; - - if (complete) { - fcport->stats_cbfn(fcport->stats_cbarg, fcport->stats_status); - } else { - fcport->stats_busy = BFA_FALSE; - fcport->stats_status = BFA_STATUS_OK; - } -} - -static void -__bfa_cb_fcport_stats_clr(void *cbarg, bfa_boolean_t complete) -{ - struct bfa_fcport_s *fcport = cbarg; - - if (complete) { - fcport->stats_cbfn(fcport->stats_cbarg, fcport->stats_status); - } else { - fcport->stats_busy = BFA_FALSE; - fcport->stats_status = BFA_STATUS_OK; - } -} - -static void -bfa_port_stats_clr_timeout(void *cbarg) -{ - struct bfa_fcport_s *fcport = (struct bfa_fcport_s *)cbarg; - - bfa_trc(fcport->bfa, fcport->stats_qfull); - - if (fcport->stats_qfull) { - bfa_reqq_wcancel(&fcport->stats_reqq_wait); - fcport->stats_qfull = BFA_FALSE; - } - - fcport->stats_status = BFA_STATUS_ETIMER; - bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, - __bfa_cb_port_stats_clr, fcport); -} - -static void -bfa_fcport_callback(struct bfa_fcport_s *fcport, enum bfa_pport_linkstate event) -{ - if (fcport->bfa->fcs) { - fcport->event_cbfn(fcport->event_cbarg, event); - return; - } - - switch (event) { - case BFA_PPORT_LINKUP: - bfa_sm_send_event(&fcport->ln, BFA_FCPORT_LN_SM_LINKUP); - break; - case BFA_PPORT_LINKDOWN: - bfa_sm_send_event(&fcport->ln, BFA_FCPORT_LN_SM_LINKDOWN); - break; - default: - bfa_assert(0); - } -} - -static void -bfa_fcport_queue_cb(struct bfa_fcport_ln_s *ln, enum bfa_pport_linkstate event) -{ - ln->ln_event = event; - bfa_cb_queue(ln->fcport->bfa, &ln->ln_qe, __bfa_cb_fcport_event, ln); -} - -static void -bfa_fcport_stats_clr_timeout(void *cbarg) -{ - struct bfa_fcport_s *fcport = (struct bfa_fcport_s *) cbarg; - - bfa_trc(fcport->bfa, fcport->stats_qfull); - - if (fcport->stats_qfull) { - bfa_reqq_wcancel(&fcport->stats_reqq_wait); - fcport->stats_qfull = BFA_FALSE; - } - - fcport->stats_status = BFA_STATUS_ETIMER; - bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, __bfa_cb_fcport_stats_clr, - fcport); -} - -static void -__bfa_cb_port_stats(void *cbarg, bfa_boolean_t complete) -{ - struct bfa_fcport_s *fcport = cbarg; - - if (complete) { - if (fcport->stats_status == BFA_STATUS_OK) - bfa_port_stats_swap(fcport->stats_ret, fcport->stats); - fcport->stats_cbfn(fcport->stats_cbarg, fcport->stats_status); - } else { - fcport->stats_busy = BFA_FALSE; - fcport->stats_status = BFA_STATUS_OK; - } -} - -static void -bfa_port_stats_timeout(void *cbarg) -{ - struct bfa_fcport_s *fcport = (struct bfa_fcport_s *)cbarg; - - bfa_trc(fcport->bfa, fcport->stats_qfull); - - if (fcport->stats_qfull) { - bfa_reqq_wcancel(&fcport->stats_reqq_wait); - fcport->stats_qfull = BFA_FALSE; - } - - fcport->stats_status = BFA_STATUS_ETIMER; - bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, __bfa_cb_port_stats, fcport); -} - -static void -__bfa_cb_fcport_stats(void *cbarg, bfa_boolean_t complete) -{ - struct bfa_fcport_s *fcport = cbarg; - - if (complete) { - if (fcport->stats_status == BFA_STATUS_OK) { - bfa_fcport_stats_swap(fcport->fcport_stats_ret, - fcport->fcport_stats); - } - fcport->stats_cbfn(fcport->stats_cbarg, fcport->stats_status); - } else { - fcport->stats_busy = BFA_FALSE; - fcport->stats_status = BFA_STATUS_OK; - } -} - -static void -bfa_fcport_stats_timeout(void *cbarg) -{ - struct bfa_fcport_s *fcport = (struct bfa_fcport_s *) cbarg; - - bfa_trc(fcport->bfa, fcport->stats_qfull); - - if (fcport->stats_qfull) { - bfa_reqq_wcancel(&fcport->stats_reqq_wait); - fcport->stats_qfull = BFA_FALSE; - } - - fcport->stats_status = BFA_STATUS_ETIMER; - bfa_cb_queue(fcport->bfa, &fcport->hcb_qe, __bfa_cb_fcport_stats, - fcport); -} - -#define BFA_PORT_STATS_TOV 1000 +#define BFA_FCPORT_STATS_TOV 1000 /** - * Fetch port attributes. + * Fetch port attributes (FCQoS or FCoE). */ bfa_status_t -bfa_pport_get_stats(struct bfa_s *bfa, union bfa_pport_stats_u *stats, +bfa_fcport_get_stats(struct bfa_s *bfa, union bfa_fcport_stats_u *stats, bfa_cb_pport_t cbfn, void *cbarg) { struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); @@ -1804,20 +1613,23 @@ bfa_pport_get_stats(struct bfa_s *bfa, union bfa_pport_stats_u *stats, return BFA_STATUS_DEVBUSY; } - fcport->stats_busy = BFA_TRUE; - fcport->stats_ret = stats; - fcport->stats_cbfn = cbfn; + fcport->stats_busy = BFA_TRUE; + fcport->stats_ret = stats; + fcport->stats_cbfn = cbfn; fcport->stats_cbarg = cbarg; - bfa_port_stats_query(fcport); + bfa_fcport_send_stats_get(fcport); - bfa_timer_start(bfa, &fcport->timer, bfa_port_stats_timeout, fcport, - BFA_PORT_STATS_TOV); + bfa_timer_start(bfa, &fcport->timer, bfa_fcport_stats_get_timeout, + fcport, BFA_FCPORT_STATS_TOV); return BFA_STATUS_OK; } +/** + * Reset port statistics (FCQoS or FCoE). + */ bfa_status_t -bfa_pport_clear_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg) +bfa_fcport_clear_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg) { struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); @@ -1830,65 +1642,61 @@ bfa_pport_clear_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg) fcport->stats_cbfn = cbfn; fcport->stats_cbarg = cbarg; - bfa_port_stats_clear(fcport); + bfa_fcport_send_stats_clear(fcport); - bfa_timer_start(bfa, &fcport->timer, bfa_port_stats_clr_timeout, - fcport, BFA_PORT_STATS_TOV); + bfa_timer_start(bfa, &fcport->timer, bfa_fcport_stats_clr_timeout, + fcport, BFA_FCPORT_STATS_TOV); return BFA_STATUS_OK; } /** - * @brief - * Fetch FCPort statistics. - * Todo TBD: sharing timer,stats_busy and other resources of fcport for now - - * ideally we want to create seperate ones for fcport once bfa_fcport_s is - * decided. - * + * Fetch FCQoS port statistics */ bfa_status_t -bfa_fcport_get_stats(struct bfa_s *bfa, union bfa_fcport_stats_u *stats, - bfa_cb_pport_t cbfn, void *cbarg) +bfa_fcport_get_qos_stats(struct bfa_s *bfa, union bfa_fcport_stats_u *stats, + bfa_cb_pport_t cbfn, void *cbarg) { - struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - - if (fcport->stats_busy) { - bfa_trc(bfa, fcport->stats_busy); - return BFA_STATUS_DEVBUSY; - } - - fcport->stats_busy = BFA_TRUE; - fcport->fcport_stats_ret = stats; - fcport->stats_cbfn = cbfn; - fcport->stats_cbarg = cbarg; + /* Meaningful only for FC mode */ + bfa_assert(bfa_ioc_get_fcmode(&bfa->ioc)); - bfa_fcport_stats_query(fcport); - - bfa_timer_start(bfa, &fcport->timer, bfa_fcport_stats_timeout, fcport, - BFA_PORT_STATS_TOV); - - return BFA_STATUS_OK; + return bfa_fcport_get_stats(bfa, stats, cbfn, cbarg); } +/** + * Reset FCoE port statistics + */ bfa_status_t -bfa_fcport_clear_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg) +bfa_fcport_clear_qos_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg) { - struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); + /* Meaningful only for FC mode */ + bfa_assert(bfa_ioc_get_fcmode(&bfa->ioc)); - if (fcport->stats_busy) { - bfa_trc(bfa, fcport->stats_busy); - return BFA_STATUS_DEVBUSY; - } + return bfa_fcport_clear_stats(bfa, cbfn, cbarg); +} - fcport->stats_busy = BFA_TRUE; - fcport->stats_cbfn = cbfn; - fcport->stats_cbarg = cbarg; +/** + * Fetch FCQoS port statistics + */ +bfa_status_t +bfa_fcport_get_fcoe_stats(struct bfa_s *bfa, union bfa_fcport_stats_u *stats, + bfa_cb_pport_t cbfn, void *cbarg) +{ + /* Meaningful only for FCoE mode */ + bfa_assert(!bfa_ioc_get_fcmode(&bfa->ioc)); - bfa_fcport_stats_clear(fcport); + return bfa_fcport_get_stats(bfa, stats, cbfn, cbarg); +} - bfa_timer_start(bfa, &fcport->timer, bfa_fcport_stats_clr_timeout, - fcport, BFA_PORT_STATS_TOV); +/** + * Reset FCoE port statistics + */ +bfa_status_t +bfa_fcport_clear_fcoe_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg) +{ + /* Meaningful only for FCoE mode */ + bfa_assert(!bfa_ioc_get_fcmode(&bfa->ioc)); - return BFA_STATUS_OK; + return bfa_fcport_clear_stats(bfa, cbfn, cbarg); } bfa_status_t @@ -1945,40 +1753,6 @@ bfa_fcport_qos_get_vc_attr(struct bfa_s *bfa, } } -/** - * Fetch QoS Stats. - */ -bfa_status_t -bfa_fcport_get_qos_stats(struct bfa_s *bfa, union bfa_pport_stats_u *stats, - bfa_cb_pport_t cbfn, void *cbarg) -{ - /* - * QoS stats is embedded in port stats - */ - return bfa_pport_get_stats(bfa, stats, cbfn, cbarg); -} - -bfa_status_t -bfa_fcport_clear_qos_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg) -{ - struct bfa_fcport_s *fcport = BFA_FCPORT_MOD(bfa); - - if (fcport->stats_busy) { - bfa_trc(bfa, fcport->stats_busy); - return BFA_STATUS_DEVBUSY; - } - - fcport->stats_busy = BFA_TRUE; - fcport->stats_cbfn = cbfn; - fcport->stats_cbarg = cbarg; - - bfa_port_qos_stats_clear(fcport); - - bfa_timer_start(bfa, &fcport->timer, bfa_port_stats_clr_timeout, - fcport, BFA_PORT_STATS_TOV); - return BFA_STATUS_OK; -} - /** * Fetch port attributes. */ diff --git a/drivers/scsi/bfa/bfa_port_priv.h b/drivers/scsi/bfa/bfa_port_priv.h index 6d315ffb1e99..40e256ec67ff 100644 --- a/drivers/scsi/bfa/bfa_port_priv.h +++ b/drivers/scsi/bfa/bfa_port_priv.h @@ -46,6 +46,8 @@ struct bfa_fcport_s { enum bfa_pport_topology topology; /* current topology */ u8 myalpa; /* my ALPA in LOOP topology */ u8 rsvd[3]; + u32 mypid:24; + u32 rsvd_b:8; struct bfa_pport_cfg_s cfg; /* current port configuration */ struct bfa_qos_attr_s qos_attr; /* QoS Attributes */ struct bfa_qos_vc_attr_s qos_vc_attr; /* VC info from ELP */ @@ -59,40 +61,25 @@ struct bfa_fcport_s { void (*event_cbfn) (void *cbarg, bfa_pport_event_t event); union { - union bfi_pport_i2h_msg_u i2hmsg; + union bfi_fcport_i2h_msg_u i2hmsg; } event_arg; void *bfad; /* BFA driver handle */ struct bfa_fcport_ln_s ln; /* Link Notification */ struct bfa_cb_qe_s hcb_qe; /* BFA callback queue elem */ + struct bfa_timer_s timer; /* timer */ u32 msgtag; /* fimrware msg tag for reply */ u8 *stats_kva; u64 stats_pa; - union bfa_pport_stats_u *stats; /* pport stats */ - u32 mypid:24; - u32 rsvd_b:8; - struct bfa_timer_s timer; /* timer */ - union bfa_pport_stats_u *stats_ret; - /* driver stats location */ - bfa_status_t stats_status; - /* stats/statsclr status */ - bfa_boolean_t stats_busy; - /* outstanding stats/statsclr */ - bfa_boolean_t stats_qfull; - bfa_boolean_t diag_busy; - /* diag busy status */ - bfa_boolean_t beacon; - /* port beacon status */ - bfa_boolean_t link_e2e_beacon; - /* link beacon status */ - bfa_cb_pport_t stats_cbfn; - /* driver callback function */ - void *stats_cbarg; - /* *!< user callback arg */ - /* FCport stats */ - u8 *fcport_stats_kva; - u64 fcport_stats_pa; - union bfa_fcport_stats_u *fcport_stats; - union bfa_fcport_stats_u *fcport_stats_ret; + union bfa_fcport_stats_u *stats; + union bfa_fcport_stats_u *stats_ret; /* driver stats location */ + bfa_status_t stats_status; /* stats/statsclr status */ + bfa_boolean_t stats_busy; /* outstanding stats/statsclr */ + bfa_boolean_t stats_qfull; + bfa_cb_pport_t stats_cbfn; /* driver callback function */ + void *stats_cbarg; /* *!< user callback arg */ + bfa_boolean_t diag_busy; /* diag busy status */ + bfa_boolean_t beacon; /* port beacon status */ + bfa_boolean_t link_e2e_beacon; /* link beacon status */ }; #define BFA_FCPORT_MOD(__bfa) (&(__bfa)->modules.fcport) diff --git a/drivers/scsi/bfa/bfad_attr.c b/drivers/scsi/bfa/bfad_attr.c index dd5cb20d4b37..d97f69191838 100644 --- a/drivers/scsi/bfa/bfad_attr.c +++ b/drivers/scsi/bfa/bfad_attr.c @@ -288,7 +288,7 @@ bfad_im_get_stats(struct Scsi_Host *shost) init_completion(&fcomp.comp); spin_lock_irqsave(&bfad->bfad_lock, flags); memset(hstats, 0, sizeof(struct fc_host_statistics)); - rc = bfa_pport_get_stats(&bfad->bfa, + rc = bfa_port_get_stats(BFA_FCPORT(&bfad->bfa), (union bfa_pport_stats_u *) hstats, bfad_hcb_comp, &fcomp); spin_unlock_irqrestore(&bfad->bfad_lock, flags); @@ -315,7 +315,8 @@ bfad_im_reset_stats(struct Scsi_Host *shost) init_completion(&fcomp.comp); spin_lock_irqsave(&bfad->bfad_lock, flags); - rc = bfa_pport_clear_stats(&bfad->bfa, bfad_hcb_comp, &fcomp); + rc = bfa_port_clear_stats(BFA_FCPORT(&bfad->bfa), bfad_hcb_comp, + &fcomp); spin_unlock_irqrestore(&bfad->bfad_lock, flags); if (rc != BFA_STATUS_OK) diff --git a/drivers/scsi/bfa/include/bfa_svc.h b/drivers/scsi/bfa/include/bfa_svc.h index f2c30858900b..1349b99a3c6d 100644 --- a/drivers/scsi/bfa/include/bfa_svc.h +++ b/drivers/scsi/bfa/include/bfa_svc.h @@ -36,7 +36,7 @@ struct bfa_fcxp_s; struct bfa_rport_info_s { u16 max_frmsz; /* max rcv pdu size */ u32 pid:24, /* remote port ID */ - lp_tag:8; + lp_tag:8; /* tag */ u32 local_pid:24, /* local port ID */ cisc:8; /* CIRO supported */ u8 fc_class; /* supported FC classes. enum fc_cos */ @@ -55,7 +55,7 @@ struct bfa_rport_s { void *rport_drv; /* fcs/driver rport object */ u16 fw_handle; /* firmware rport handle */ u16 rport_tag; /* BFA rport tag */ - struct bfa_rport_info_s rport_info; /* rport info from *fcs/driver */ + struct bfa_rport_info_s rport_info; /* rport info from fcs/driver */ struct bfa_reqq_wait_s reqq_wait; /* to wait for room in reqq */ struct bfa_cb_qe_s hcb_qe; /* BFA callback qelem */ struct bfa_rport_hal_stats_s stats; /* BFA rport statistics */ @@ -102,7 +102,7 @@ struct bfa_uf_buf_s { struct bfa_uf_s { struct list_head qe; /* queue element */ struct bfa_s *bfa; /* bfa instance */ - u16 uf_tag; /* identifying tag f/w messages */ + u16 uf_tag; /* identifying tag fw msgs */ u16 vf_id; u16 src_rport_handle; u16 rsvd; @@ -128,7 +128,7 @@ struct bfa_lps_s { u8 reqq; /* lport request queue */ u8 alpa; /* ALPA for loop topologies */ u32 lp_pid; /* lport port ID */ - bfa_boolean_t fdisc; /* send FDISC instead of FLOGI*/ + bfa_boolean_t fdisc; /* send FDISC instead of FLOGI */ bfa_boolean_t auth_en; /* enable authentication */ bfa_boolean_t auth_req; /* authentication required */ bfa_boolean_t npiv_en; /* NPIV is allowed by peer */ @@ -178,11 +178,6 @@ bfa_status_t bfa_fcport_trunk_disable(struct bfa_s *bfa); bfa_boolean_t bfa_fcport_trunk_query(struct bfa_s *bfa, u32 *bitmap); void bfa_fcport_get_attr(struct bfa_s *bfa, struct bfa_pport_attr_s *attr); wwn_t bfa_fcport_get_wwn(struct bfa_s *bfa, bfa_boolean_t node); -bfa_status_t bfa_pport_get_stats(struct bfa_s *bfa, - union bfa_pport_stats_u *stats, - bfa_cb_pport_t cbfn, void *cbarg); -bfa_status_t bfa_pport_clear_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, - void *cbarg); void bfa_fcport_event_register(struct bfa_s *bfa, void (*event_cbfn) (void *cbarg, bfa_pport_event_t event), void *event_cbarg); @@ -198,14 +193,21 @@ void bfa_fcport_busy(struct bfa_s *bfa, bfa_boolean_t status); void bfa_fcport_beacon(struct bfa_s *bfa, bfa_boolean_t beacon, bfa_boolean_t link_e2e_beacon); void bfa_cb_pport_event(void *cbarg, bfa_pport_event_t event); -void bfa_fcport_qos_get_attr(struct bfa_s *bfa, struct bfa_qos_attr_s *qos_attr); +void bfa_fcport_qos_get_attr(struct bfa_s *bfa, + struct bfa_qos_attr_s *qos_attr); void bfa_fcport_qos_get_vc_attr(struct bfa_s *bfa, struct bfa_qos_vc_attr_s *qos_vc_attr); bfa_status_t bfa_fcport_get_qos_stats(struct bfa_s *bfa, - union bfa_pport_stats_u *stats, + union bfa_fcport_stats_u *stats, bfa_cb_pport_t cbfn, void *cbarg); bfa_status_t bfa_fcport_clear_qos_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, void *cbarg); +bfa_status_t bfa_fcport_get_fcoe_stats(struct bfa_s *bfa, + union bfa_fcport_stats_u *stats, + bfa_cb_pport_t cbfn, void *cbarg); +bfa_status_t bfa_fcport_clear_fcoe_stats(struct bfa_s *bfa, bfa_cb_pport_t cbfn, + void *cbarg); + bfa_boolean_t bfa_fcport_is_ratelim(struct bfa_s *bfa); bfa_boolean_t bfa_fcport_is_linkup(struct bfa_s *bfa); bfa_status_t bfa_fcport_get_stats(struct bfa_s *bfa, diff --git a/drivers/scsi/bfa/include/bfi/bfi.h b/drivers/scsi/bfa/include/bfi/bfi.h index 7042c18e542d..a550e80cabd2 100644 --- a/drivers/scsi/bfa/include/bfi/bfi.h +++ b/drivers/scsi/bfa/include/bfi/bfi.h @@ -143,8 +143,8 @@ enum bfi_mclass { BFI_MC_IOC = 1, /* IO Controller (IOC) */ BFI_MC_DIAG = 2, /* Diagnostic Msgs */ BFI_MC_FLASH = 3, /* Flash message class */ - BFI_MC_CEE = 4, - BFI_MC_FC_PORT = 5, /* FC port */ + BFI_MC_CEE = 4, /* CEE */ + BFI_MC_FCPORT = 5, /* FC port */ BFI_MC_IOCFC = 6, /* FC - IO Controller (IOC) */ BFI_MC_LL = 7, /* Link Layer */ BFI_MC_UF = 8, /* Unsolicited frame receive */ diff --git a/drivers/scsi/bfa/include/bfi/bfi_pport.h b/drivers/scsi/bfa/include/bfi/bfi_pport.h index 5c3d289d986d..50dcf45c7470 100644 --- a/drivers/scsi/bfa/include/bfi/bfi_pport.h +++ b/drivers/scsi/bfa/include/bfi/bfi_pport.h @@ -22,168 +22,97 @@ #pragma pack(1) -enum bfi_pport_h2i { - BFI_PPORT_H2I_ENABLE_REQ = (1), - BFI_PPORT_H2I_DISABLE_REQ = (2), - BFI_PPORT_H2I_GET_STATS_REQ = (3), - BFI_PPORT_H2I_CLEAR_STATS_REQ = (4), - BFI_PPORT_H2I_SET_SVC_PARAMS_REQ = (5), - BFI_PPORT_H2I_ENABLE_RX_VF_TAG_REQ = (6), - BFI_PPORT_H2I_ENABLE_TX_VF_TAG_REQ = (7), - BFI_PPORT_H2I_GET_QOS_STATS_REQ = (8), - BFI_PPORT_H2I_CLEAR_QOS_STATS_REQ = (9), - BFI_FCPORT_H2I_GET_STATS_REQ = (10), - BFI_FCPORT_H2I_CLEAR_STATS_REQ = (11), +enum bfi_fcport_h2i { + BFI_FCPORT_H2I_ENABLE_REQ = (1), + BFI_FCPORT_H2I_DISABLE_REQ = (2), + BFI_FCPORT_H2I_SET_SVC_PARAMS_REQ = (3), + BFI_FCPORT_H2I_STATS_GET_REQ = (4), + BFI_FCPORT_H2I_STATS_CLEAR_REQ = (5), }; -enum bfi_pport_i2h { - BFI_PPORT_I2H_ENABLE_RSP = BFA_I2HM(1), - BFI_PPORT_I2H_DISABLE_RSP = BFA_I2HM(2), - BFI_PPORT_I2H_GET_STATS_RSP = BFA_I2HM(3), - BFI_PPORT_I2H_CLEAR_STATS_RSP = BFA_I2HM(4), - BFI_PPORT_I2H_SET_SVC_PARAMS_RSP = BFA_I2HM(5), - BFI_PPORT_I2H_ENABLE_RX_VF_TAG_RSP = BFA_I2HM(6), - BFI_PPORT_I2H_ENABLE_TX_VF_TAG_RSP = BFA_I2HM(7), - BFI_PPORT_I2H_EVENT = BFA_I2HM(8), - BFI_PPORT_I2H_GET_QOS_STATS_RSP = BFA_I2HM(9), - BFI_PPORT_I2H_CLEAR_QOS_STATS_RSP = BFA_I2HM(10), - BFI_FCPORT_I2H_GET_STATS_RSP = BFA_I2HM(11), - BFI_FCPORT_I2H_CLEAR_STATS_RSP = BFA_I2HM(12), +enum bfi_fcport_i2h { + BFI_FCPORT_I2H_ENABLE_RSP = BFA_I2HM(1), + BFI_FCPORT_I2H_DISABLE_RSP = BFA_I2HM(2), + BFI_FCPORT_I2H_SET_SVC_PARAMS_RSP = BFA_I2HM(3), + BFI_FCPORT_I2H_STATS_GET_RSP = BFA_I2HM(4), + BFI_FCPORT_I2H_STATS_CLEAR_RSP = BFA_I2HM(5), + BFI_FCPORT_I2H_EVENT = BFA_I2HM(6), }; /** * Generic REQ type */ -struct bfi_pport_generic_req_s { +struct bfi_fcport_req_s { struct bfi_mhdr_s mh; /* msg header */ - u32 msgtag; /* msgtag for reply */ + u32 msgtag; /* msgtag for reply */ }; /** * Generic RSP type */ -struct bfi_pport_generic_rsp_s { +struct bfi_fcport_rsp_s { struct bfi_mhdr_s mh; /* common msg header */ - u8 status; /* port enable status */ - u8 rsvd[3]; - u32 msgtag; /* msgtag for reply */ + u8 status; /* port enable status */ + u8 rsvd[3]; + u32 msgtag; /* msgtag for reply */ }; /** - * BFI_PPORT_H2I_ENABLE_REQ + * BFI_FCPORT_H2I_ENABLE_REQ */ -struct bfi_pport_enable_req_s { +struct bfi_fcport_enable_req_s { struct bfi_mhdr_s mh; /* msg header */ - u32 rsvd1; - wwn_t nwwn; /* node wwn of physical port */ - wwn_t pwwn; /* port wwn of physical port */ - struct bfa_pport_cfg_s port_cfg; /* port configuration */ - union bfi_addr_u stats_dma_addr; /* DMA address for stats */ - union bfi_addr_u fcport_stats_dma_addr;/*!< DMA address for stats */ - u32 msgtag; /* msgtag for reply */ - u32 rsvd2; + u32 rsvd1; + wwn_t nwwn; /* node wwn of physical port */ + wwn_t pwwn; /* port wwn of physical port */ + struct bfa_pport_cfg_s port_cfg; /* port configuration */ + union bfi_addr_u stats_dma_addr; /* DMA address for stats */ + u32 msgtag; /* msgtag for reply */ + u32 rsvd2; }; /** - * BFI_PPORT_I2H_ENABLE_RSP + * BFI_FCPORT_H2I_SET_SVC_PARAMS_REQ */ -#define bfi_pport_enable_rsp_t struct bfi_pport_generic_rsp_s - -/** - * BFI_PPORT_H2I_DISABLE_REQ - */ -#define bfi_pport_disable_req_t struct bfi_pport_generic_req_s - -/** - * BFI_PPORT_I2H_DISABLE_RSP - */ -#define bfi_pport_disable_rsp_t struct bfi_pport_generic_rsp_s - -/** - * BFI_PPORT_H2I_GET_STATS_REQ - */ -#define bfi_pport_get_stats_req_t struct bfi_pport_generic_req_s - -/** - * BFI_PPORT_I2H_GET_STATS_RSP - */ -#define bfi_pport_get_stats_rsp_t struct bfi_pport_generic_rsp_s - -/** - * BFI_PPORT_H2I_CLEAR_STATS_REQ - */ -#define bfi_pport_clear_stats_req_t struct bfi_pport_generic_req_s - -/** - * BFI_PPORT_I2H_CLEAR_STATS_RSP - */ -#define bfi_pport_clear_stats_rsp_t struct bfi_pport_generic_rsp_s - -/** - * BFI_PPORT_H2I_GET_QOS_STATS_REQ - */ -#define bfi_pport_get_qos_stats_req_t struct bfi_pport_generic_req_s - -/** - * BFI_PPORT_H2I_GET_QOS_STATS_RSP - */ -#define bfi_pport_get_qos_stats_rsp_t struct bfi_pport_generic_rsp_s - -/** - * BFI_PPORT_H2I_CLEAR_QOS_STATS_REQ - */ -#define bfi_pport_clear_qos_stats_req_t struct bfi_pport_generic_req_s - -/** - * BFI_PPORT_H2I_CLEAR_QOS_STATS_RSP - */ -#define bfi_pport_clear_qos_stats_rsp_t struct bfi_pport_generic_rsp_s - -/** - * BFI_PPORT_H2I_SET_SVC_PARAMS_REQ - */ -struct bfi_pport_set_svc_params_req_s { +struct bfi_fcport_set_svc_params_req_s { struct bfi_mhdr_s mh; /* msg header */ - u16 tx_bbcredit; /* Tx credits */ - u16 rsvd; + u16 tx_bbcredit; /* Tx credits */ + u16 rsvd; }; /** - * BFI_PPORT_I2H_SET_SVC_PARAMS_RSP - */ - -/** - * BFI_PPORT_I2H_EVENT + * BFI_FCPORT_I2H_EVENT */ -struct bfi_pport_event_s { +struct bfi_fcport_event_s { struct bfi_mhdr_s mh; /* common msg header */ struct bfa_pport_link_s link_state; }; -union bfi_pport_h2i_msg_u { +/** + * fcport H2I message + */ +union bfi_fcport_h2i_msg_u { struct bfi_mhdr_s *mhdr; - struct bfi_pport_enable_req_s *penable; - struct bfi_pport_generic_req_s *pdisable; - struct bfi_pport_generic_req_s *pgetstats; - struct bfi_pport_generic_req_s *pclearstats; - struct bfi_pport_set_svc_params_req_s *psetsvcparams; - struct bfi_pport_get_qos_stats_req_s *pgetqosstats; - struct bfi_pport_generic_req_s *pclearqosstats; + struct bfi_fcport_enable_req_s *penable; + struct bfi_fcport_req_s *pdisable; + struct bfi_fcport_set_svc_params_req_s *psetsvcparams; + struct bfi_fcport_req_s *pstatsget; + struct bfi_fcport_req_s *pstatsclear; }; -union bfi_pport_i2h_msg_u { +/** + * fcport I2H message + */ +union bfi_fcport_i2h_msg_u { struct bfi_msg_s *msg; - struct bfi_pport_generic_rsp_s *enable_rsp; - struct bfi_pport_disable_rsp_s *disable_rsp; - struct bfi_pport_generic_rsp_s *getstats_rsp; - struct bfi_pport_clear_stats_rsp_s *clearstats_rsp; - struct bfi_pport_set_svc_params_rsp_s *setsvcparasm_rsp; - struct bfi_pport_get_qos_stats_rsp_s *getqosstats_rsp; - struct bfi_pport_clear_qos_stats_rsp_s *clearqosstats_rsp; - struct bfi_pport_event_s *event; + struct bfi_fcport_rsp_s *penable_rsp; + struct bfi_fcport_rsp_s *pdisable_rsp; + struct bfi_fcport_rsp_s *psetsvcparams_rsp; + struct bfi_fcport_rsp_s *pstatsget_rsp; + struct bfi_fcport_rsp_s *pstatsclear_rsp; + struct bfi_fcport_event_s *event; }; #pragma pack() #endif /* __BFI_PPORT_H__ */ - diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_pport.h b/drivers/scsi/bfa/include/defs/bfa_defs_pport.h index 164cfbef9b12..26e5cc78095d 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_pport.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_pport.h @@ -240,73 +240,79 @@ struct bfa_pport_attr_s { * FC Port statistics. */ struct bfa_pport_fc_stats_s { - u64 secs_reset; /* seconds since stats is reset */ - u64 tx_frames; /* transmitted frames */ - u64 tx_words; /* transmitted words */ - u64 rx_frames; /* received frames */ - u64 rx_words; /* received words */ - u64 lip_count; /* LIPs seen */ - u64 nos_count; /* NOS count */ - u64 error_frames; /* errored frames */ - u64 dropped_frames; /* dropped frames */ - u64 link_failures; /* link failure count */ - u64 loss_of_syncs; /* loss of sync count */ - u64 loss_of_signals;/* loss of signal count */ - u64 primseq_errs; /* primitive sequence protocol */ - u64 bad_os_count; /* invalid ordered set */ - u64 err_enc_out; /* Encoding error outside frame */ - u64 invalid_crcs; /* frames received with invalid CRC*/ - u64 undersized_frm; /* undersized frames */ - u64 oversized_frm; /* oversized frames */ - u64 bad_eof_frm; /* frames with bad EOF */ - struct bfa_qos_stats_s qos_stats; /* QoS statistics */ + u64 secs_reset; /* Seconds since stats is reset */ + u64 tx_frames; /* Tx frames */ + u64 tx_words; /* Tx words */ + u64 tx_lip; /* TX LIP */ + u64 tx_nos; /* Tx NOS */ + u64 tx_ols; /* Tx OLS */ + u64 tx_lr; /* Tx LR */ + u64 tx_lrr; /* Tx LRR */ + u64 rx_frames; /* Rx frames */ + u64 rx_words; /* Rx words */ + u64 lip_count; /* Rx LIP */ + u64 nos_count; /* Rx NOS */ + u64 ols_count; /* Rx OLS */ + u64 lr_count; /* Rx LR */ + u64 lrr_count; /* Rx LRR */ + u64 invalid_crcs; /* Rx CRC err frames */ + u64 invalid_crc_gd_eof; /* Rx CRC err good EOF frames */ + u64 undersized_frm; /* Rx undersized frames */ + u64 oversized_frm; /* Rx oversized frames */ + u64 bad_eof_frm; /* Rx frames with bad EOF */ + u64 error_frames; /* Errored frames */ + u64 dropped_frames; /* Dropped frames */ + u64 link_failures; /* Link Failure (LF) count */ + u64 loss_of_syncs; /* Loss of sync count */ + u64 loss_of_signals;/* Loss of signal count */ + u64 primseq_errs; /* Primitive sequence protocol err. */ + u64 bad_os_count; /* Invalid ordered sets */ + u64 err_enc_out; /* Encoding err nonframe_8b10b */ + u64 err_enc; /* Encoding err frame_8b10b */ }; /** * Eth Port statistics. */ struct bfa_pport_eth_stats_s { - u64 secs_reset; /* seconds since stats is reset */ - u64 frame_64; /* both rx and tx counter */ - u64 frame_65_127; /* both rx and tx counter */ - u64 frame_128_255; /* both rx and tx counter */ - u64 frame_256_511; /* both rx and tx counter */ - u64 frame_512_1023; /* both rx and tx counter */ - u64 frame_1024_1518; /* both rx and tx counter */ - u64 frame_1519_1522; /* both rx and tx counter */ - - u64 tx_bytes; - u64 tx_packets; - u64 tx_mcast_packets; - u64 tx_bcast_packets; - u64 tx_control_frame; - u64 tx_drop; - u64 tx_jabber; - u64 tx_fcs_error; - u64 tx_fragments; - - u64 rx_bytes; - u64 rx_packets; - u64 rx_mcast_packets; - u64 rx_bcast_packets; - u64 rx_control_frames; - u64 rx_unknown_opcode; - u64 rx_drop; - u64 rx_jabber; - u64 rx_fcs_error; - u64 rx_alignment_error; - u64 rx_frame_length_error; - u64 rx_code_error; - u64 rx_fragments; - - u64 rx_pause; /* BPC */ - u64 rx_zero_pause; /* BPC Pause cancellation */ - u64 tx_pause; /* BPC */ - u64 tx_zero_pause; /* BPC Pause cancellation */ - u64 rx_fcoe_pause; /* BPC */ - u64 rx_fcoe_zero_pause; /* BPC Pause cancellation */ - u64 tx_fcoe_pause; /* BPC */ - u64 tx_fcoe_zero_pause; /* BPC Pause cancellation */ + u64 secs_reset; /* Seconds since stats is reset */ + u64 frame_64; /* Frames 64 bytes */ + u64 frame_65_127; /* Frames 65-127 bytes */ + u64 frame_128_255; /* Frames 128-255 bytes */ + u64 frame_256_511; /* Frames 256-511 bytes */ + u64 frame_512_1023; /* Frames 512-1023 bytes */ + u64 frame_1024_1518; /* Frames 1024-1518 bytes */ + u64 frame_1519_1522; /* Frames 1519-1522 bytes */ + u64 tx_bytes; /* Tx bytes */ + u64 tx_packets; /* Tx packets */ + u64 tx_mcast_packets; /* Tx multicast packets */ + u64 tx_bcast_packets; /* Tx broadcast packets */ + u64 tx_control_frame; /* Tx control frame */ + u64 tx_drop; /* Tx drops */ + u64 tx_jabber; /* Tx jabber */ + u64 tx_fcs_error; /* Tx FCS error */ + u64 tx_fragments; /* Tx fragments */ + u64 rx_bytes; /* Rx bytes */ + u64 rx_packets; /* Rx packets */ + u64 rx_mcast_packets; /* Rx multicast packets */ + u64 rx_bcast_packets; /* Rx broadcast packets */ + u64 rx_control_frames; /* Rx control frames */ + u64 rx_unknown_opcode; /* Rx unknown opcode */ + u64 rx_drop; /* Rx drops */ + u64 rx_jabber; /* Rx jabber */ + u64 rx_fcs_error; /* Rx FCS errors */ + u64 rx_alignment_error; /* Rx alignment errors */ + u64 rx_frame_length_error; /* Rx frame len errors */ + u64 rx_code_error; /* Rx code errors */ + u64 rx_fragments; /* Rx fragments */ + u64 rx_pause; /* Rx pause */ + u64 rx_zero_pause; /* Rx zero pause */ + u64 tx_pause; /* Tx pause */ + u64 tx_zero_pause; /* Tx zero pause */ + u64 rx_fcoe_pause; /* Rx fcoe pause */ + u64 rx_fcoe_zero_pause; /* Rx FCoE zero pause */ + u64 tx_fcoe_pause; /* Tx FCoE pause */ + u64 tx_fcoe_zero_pause; /* Tx FCoE zero pause */ }; /** -- cgit v1.2.3 From 25e2934c26f5efaea156c9fda4457d01a8bb44e1 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:38:17 -0800 Subject: [SCSI] bfa: FCS and include file changes. MS module did not invoke fdmi offline in all cases, call fdmi offline when ms module receives a port offline, so that fdmi offline is from one place in the ms module. Make changes to handle 10G speed in the conversion routine. Replaced the usage of bfa_adapter_attr_s struct with specific API's. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/fabric.c | 8 +++--- drivers/scsi/bfa/fcbuild.h | 6 +++++ drivers/scsi/bfa/fdmi.c | 33 ++++++++----------------- drivers/scsi/bfa/include/defs/bfa_defs_status.h | 5 ++-- drivers/scsi/bfa/ms.c | 5 +--- 5 files changed, 22 insertions(+), 35 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/fabric.c b/drivers/scsi/bfa/fabric.c index b4e05ad1b47e..8166e9745ec0 100644 --- a/drivers/scsi/bfa/fabric.c +++ b/drivers/scsi/bfa/fabric.c @@ -562,17 +562,15 @@ void bfa_fcs_fabric_psymb_init(struct bfa_fcs_fabric_s *fabric) { struct bfa_port_cfg_s *port_cfg = &fabric->bport.port_cfg; - struct bfa_adapter_attr_s adapter_attr; + char model[BFA_ADAPTER_MODEL_NAME_LEN] = {0}; struct bfa_fcs_driver_info_s *driver_info = &fabric->fcs->driver_info; - bfa_os_memset((void *)&adapter_attr, 0, - sizeof(struct bfa_adapter_attr_s)); - bfa_ioc_get_adapter_attr(&fabric->fcs->bfa->ioc, &adapter_attr); + bfa_ioc_get_adapter_model(&fabric->fcs->bfa->ioc, model); /* * Model name/number */ - strncpy((char *)&port_cfg->sym_name, adapter_attr.model, + strncpy((char *)&port_cfg->sym_name, model, BFA_FCS_PORT_SYMBNAME_MODEL_SZ); strncat((char *)&port_cfg->sym_name, BFA_FCS_PORT_SYMBNAME_SEPARATOR, sizeof(BFA_FCS_PORT_SYMBNAME_SEPARATOR)); diff --git a/drivers/scsi/bfa/fcbuild.h b/drivers/scsi/bfa/fcbuild.h index 8fa7f270ef7b..981d98d542b9 100644 --- a/drivers/scsi/bfa/fcbuild.h +++ b/drivers/scsi/bfa/fcbuild.h @@ -72,6 +72,9 @@ fc_rpsc_operspeed_to_bfa_speed(enum fc_rpsc_op_speed_s speed) case RPSC_OP_SPEED_8G: return BFA_PPORT_SPEED_8GBPS; + case RPSC_OP_SPEED_10G: + return BFA_PPORT_SPEED_10GBPS; + default: return BFA_PPORT_SPEED_UNKNOWN; } @@ -97,6 +100,9 @@ fc_bfa_speed_to_rpsc_operspeed(enum bfa_pport_speed op_speed) case BFA_PPORT_SPEED_8GBPS: return RPSC_OP_SPEED_8G; + case BFA_PPORT_SPEED_10GBPS: + return RPSC_OP_SPEED_10G; + default: return RPSC_OP_SPEED_NOT_EST; } diff --git a/drivers/scsi/bfa/fdmi.c b/drivers/scsi/bfa/fdmi.c index 2c9e7132a368..8f17076d1a87 100644 --- a/drivers/scsi/bfa/fdmi.c +++ b/drivers/scsi/bfa/fdmi.c @@ -1114,36 +1114,23 @@ bfa_fcs_fdmi_get_hbaattr(struct bfa_fcs_port_fdmi_s *fdmi, { struct bfa_fcs_port_s *port = fdmi->ms->port; struct bfa_fcs_driver_info_s *driver_info = &port->fcs->driver_info; - struct bfa_adapter_attr_s adapter_attr; bfa_os_memset(hba_attr, 0, sizeof(struct bfa_fcs_fdmi_hba_attr_s)); - bfa_os_memset(&adapter_attr, 0, sizeof(struct bfa_adapter_attr_s)); - bfa_ioc_get_adapter_attr(&port->fcs->bfa->ioc, &adapter_attr); - - strncpy(hba_attr->manufacturer, adapter_attr.manufacturer, - sizeof(adapter_attr.manufacturer)); - - strncpy(hba_attr->serial_num, adapter_attr.serial_num, - sizeof(adapter_attr.serial_num)); - - strncpy(hba_attr->model, adapter_attr.model, sizeof(hba_attr->model)); - - strncpy(hba_attr->model_desc, adapter_attr.model_descr, - sizeof(hba_attr->model_desc)); - - strncpy(hba_attr->hw_version, adapter_attr.hw_ver, - sizeof(hba_attr->hw_version)); + bfa_ioc_get_adapter_manufacturer(&port->fcs->bfa->ioc, + hba_attr->manufacturer); + bfa_ioc_get_adapter_serial_num(&port->fcs->bfa->ioc, + hba_attr->serial_num); + bfa_ioc_get_adapter_model(&port->fcs->bfa->ioc, hba_attr->model); + bfa_ioc_get_adapter_model(&port->fcs->bfa->ioc, hba_attr->model_desc); + bfa_ioc_get_pci_chip_rev(&port->fcs->bfa->ioc, hba_attr->hw_version); + bfa_ioc_get_adapter_optrom_ver(&port->fcs->bfa->ioc, + hba_attr->option_rom_ver); + bfa_ioc_get_adapter_fw_ver(&port->fcs->bfa->ioc, hba_attr->fw_version); strncpy(hba_attr->driver_version, (char *)driver_info->version, sizeof(hba_attr->driver_version)); - strncpy(hba_attr->option_rom_ver, adapter_attr.optrom_ver, - sizeof(hba_attr->option_rom_ver)); - - strncpy(hba_attr->fw_version, adapter_attr.fw_ver, - sizeof(hba_attr->fw_version)); - strncpy(hba_attr->os_name, driver_info->host_os_name, sizeof(hba_attr->os_name)); diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_status.h b/drivers/scsi/bfa/include/defs/bfa_defs_status.h index d8a74ebfe1ae..4374494bd566 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_status.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_status.h @@ -213,7 +213,7 @@ enum bfa_status { * loaded */ BFA_STATUS_CARD_TYPE_MISMATCH = 131, /* Card type mismatch */ BFA_STATUS_BAD_ASICBLK = 132, /* Bad ASIC block */ - BFA_STATUS_NO_DRIVER = 133, /* Storage/Ethernet driver not loaded */ + BFA_STATUS_NO_DRIVER = 133, /* Brocade adapter/driver not installed or loaded */ BFA_STATUS_INVALID_MAC = 134, /* Invalid mac address */ BFA_STATUS_IM_NO_VLAN = 135, /* No VLANs configured on the adapter */ BFA_STATUS_IM_ETH_LB_FAILED = 136, /* Ethernet loopback test failed */ @@ -228,8 +228,7 @@ enum bfa_status { BFA_STATUS_IM_GET_INETCFG_FAILED = 142, /* Acquiring Network Subsytem * handle Failed. Please try * after some time */ - BFA_STATUS_IM_NOT_BOUND = 143, /* Brocade 10G Ethernet Service is not - * Enabled on this port */ + BFA_STATUS_IM_NOT_BOUND = 143, /* IM driver is not active */ BFA_STATUS_INSUFFICIENT_PERMS = 144, /* User doesn't have sufficient * permissions to execute the BCU * application */ diff --git a/drivers/scsi/bfa/ms.c b/drivers/scsi/bfa/ms.c index e6db5fd301f2..5e8c8dee6c97 100644 --- a/drivers/scsi/bfa/ms.c +++ b/drivers/scsi/bfa/ms.c @@ -230,10 +230,6 @@ bfa_fcs_port_ms_sm_online(struct bfa_fcs_port_ms_s *ms, switch (event) { case MSSM_EVENT_PORT_OFFLINE: bfa_sm_set_state(ms, bfa_fcs_port_ms_sm_offline); - /* - * now invoke MS related sub-modules - */ - bfa_fcs_port_fdmi_offline(ms); break; case MSSM_EVENT_PORT_FABRIC_RSCN: @@ -735,6 +731,7 @@ bfa_fcs_port_ms_offline(struct bfa_fcs_port_s *port) ms->port = port; bfa_sm_send_event(ms, MSSM_EVENT_PORT_OFFLINE); + bfa_fcs_port_fdmi_offline(ms); } void -- cgit v1.2.3 From 95aa060decd2472d319c3f12b0b1b699a5f35058 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:38:27 -0800 Subject: [SCSI] bfa: Handle SCSI IO underrun case. When IO is completed with underrun and with good SCSI status, check if the transferred bytes against scsi_cmnd->underflow, which is set to minimum number of bytes that must be transferred for this command, if is less than required minimum, complete the IO with DID_ERROR. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfad_im.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfad_im.c b/drivers/scsi/bfa/bfad_im.c index cee3d89d1412..fb7aefaba129 100644 --- a/drivers/scsi/bfa/bfad_im.c +++ b/drivers/scsi/bfa/bfad_im.c @@ -43,11 +43,11 @@ bfa_cb_ioim_done(void *drv, struct bfad_ioim_s *dio, struct bfad_s *bfad = drv; struct bfad_itnim_data_s *itnim_data; struct bfad_itnim_s *itnim; + u8 host_status = DID_OK; switch (io_status) { case BFI_IOIM_STS_OK: bfa_trc(bfad, scsi_status); - cmnd->result = ScsiResult(DID_OK, scsi_status); scsi_set_resid(cmnd, 0); if (sns_len > 0) { @@ -56,8 +56,18 @@ bfa_cb_ioim_done(void *drv, struct bfad_ioim_s *dio, sns_len = SCSI_SENSE_BUFFERSIZE; memcpy(cmnd->sense_buffer, sns_info, sns_len); } - if (residue > 0) + if (residue > 0) { + bfa_trc(bfad, residue); scsi_set_resid(cmnd, residue); + if (!sns_len && (scsi_status == SAM_STAT_GOOD) && + (scsi_bufflen(cmnd) - residue) < + cmnd->underflow) { + bfa_trc(bfad, 0); + host_status = DID_ERROR; + } + } + cmnd->result = ScsiResult(host_status, scsi_status); + break; case BFI_IOIM_STS_ABORTED: -- cgit v1.2.3 From d1c61f8ef582055569de76a86fa1984f9b6698cf Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:38:44 -0800 Subject: [SCSI] bfa: Remove unused header files and did some cleanup. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfa_fcport.c | 4 +- drivers/scsi/bfa/bfa_ioc_cb.c | 12 ++-- drivers/scsi/bfa/bfa_ioc_ct.c | 28 ++++---- drivers/scsi/bfa/bfad_attr.h | 9 --- drivers/scsi/bfa/bfad_drv.h | 10 --- drivers/scsi/bfa/bfad_im.c | 10 --- drivers/scsi/bfa/bfad_im.h | 5 -- drivers/scsi/bfa/fcpim.c | 1 - drivers/scsi/bfa/include/defs/bfa_defs_driver.h | 3 +- drivers/scsi/bfa/include/defs/bfa_defs_im_common.h | 32 --------- drivers/scsi/bfa/include/defs/bfa_defs_im_team.h | 72 --------------------- drivers/scsi/bfa/include/fcb/bfa_fcb_fcpim.h | 1 - drivers/scsi/bfa/include/protocol/pcifw.h | 75 ---------------------- 13 files changed, 24 insertions(+), 238 deletions(-) delete mode 100644 drivers/scsi/bfa/include/defs/bfa_defs_im_common.h delete mode 100644 drivers/scsi/bfa/include/defs/bfa_defs_im_team.h delete mode 100644 drivers/scsi/bfa/include/protocol/pcifw.h (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfa_fcport.c b/drivers/scsi/bfa/bfa_fcport.c index d109e651b1c5..c589488db0c1 100644 --- a/drivers/scsi/bfa/bfa_fcport.c +++ b/drivers/scsi/bfa/bfa_fcport.c @@ -853,9 +853,9 @@ bfa_fcport_meminfo(struct bfa_iocfc_cfg_s *cfg, u32 *ndm_len, static void bfa_fcport_qresume(void *cbarg) { - struct bfa_fcport_s *port = cbarg; + struct bfa_fcport_s *fcport = cbarg; - bfa_sm_send_event(port, BFA_FCPORT_SM_QRESUME); + bfa_sm_send_event(fcport, BFA_FCPORT_SM_QRESUME); } static void diff --git a/drivers/scsi/bfa/bfa_ioc_cb.c b/drivers/scsi/bfa/bfa_ioc_cb.c index 1fa052ef9ce0..3ce85319f739 100644 --- a/drivers/scsi/bfa/bfa_ioc_cb.c +++ b/drivers/scsi/bfa/bfa_ioc_cb.c @@ -63,13 +63,13 @@ bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc) ioc->ioc_hwif = &hwif_cb; } -static uint32_t * -bfa_ioc_cb_fwimg_get_chunk(struct bfa_ioc_s *ioc, uint32_t off) +static u32 * +bfa_ioc_cb_fwimg_get_chunk(struct bfa_ioc_s *ioc, u32 off) { return bfi_image_cb_get_chunk(off); } -static uint32_t +static u32 bfa_ioc_cb_fwimg_get_size(struct bfa_ioc_s *ioc) { return bfi_image_cb_size; @@ -102,7 +102,7 @@ bfa_ioc_cb_notify_hbfail(struct bfa_ioc_s *ioc) /** * Host to LPU mailbox message addresses */ -static struct { uint32_t hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = { +static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = { { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 }, { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 } }; @@ -110,7 +110,7 @@ static struct { uint32_t hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = { /** * Host <-> LPU mailbox command/status registers */ -static struct { uint32_t hfn, lpu; } iocreg_mbcmd[] = { +static struct { u32 hfn, lpu; } iocreg_mbcmd[] = { { HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT }, { HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT } }; @@ -192,7 +192,7 @@ static bfa_status_t bfa_ioc_cb_pll_init(struct bfa_ioc_s *ioc) { bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; - uint32_t pll_sclk, pll_fclk; + u32 pll_sclk, pll_fclk; /* * Hold semaphore so that nobody can access the chip during init. diff --git a/drivers/scsi/bfa/bfa_ioc_ct.c b/drivers/scsi/bfa/bfa_ioc_ct.c index 2431922c34a4..20b58ad5f95c 100644 --- a/drivers/scsi/bfa/bfa_ioc_ct.c +++ b/drivers/scsi/bfa/bfa_ioc_ct.c @@ -33,9 +33,9 @@ BFA_TRC_FILE(CNA, IOC_CT); static bfa_status_t bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc); static bfa_boolean_t bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc); static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc); -static uint32_t* bfa_ioc_ct_fwimg_get_chunk(struct bfa_ioc_s *ioc, - uint32_t off); -static uint32_t bfa_ioc_ct_fwimg_get_size(struct bfa_ioc_s *ioc); +static u32* bfa_ioc_ct_fwimg_get_chunk(struct bfa_ioc_s *ioc, + u32 off); +static u32 bfa_ioc_ct_fwimg_get_size(struct bfa_ioc_s *ioc); static void bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc); static void bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc); static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix); @@ -64,13 +64,13 @@ bfa_ioc_set_ct_hwif(struct bfa_ioc_s *ioc) ioc->ioc_hwif = &hwif_ct; } -static uint32_t* -bfa_ioc_ct_fwimg_get_chunk(struct bfa_ioc_s *ioc, uint32_t off) +static u32* +bfa_ioc_ct_fwimg_get_chunk(struct bfa_ioc_s *ioc, u32 off) { return bfi_image_ct_get_chunk(off); } -static uint32_t +static u32 bfa_ioc_ct_fwimg_get_size(struct bfa_ioc_s *ioc) { return bfi_image_ct_size; @@ -83,7 +83,7 @@ static bfa_boolean_t bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc) { enum bfi_ioc_state ioc_fwstate; - uint32_t usecnt; + u32 usecnt; struct bfi_ioc_image_hdr_s fwhdr; /** @@ -142,7 +142,7 @@ bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc) static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc) { - uint32_t usecnt; + u32 usecnt; /** * Firmware lock is relevant only for CNA. @@ -184,7 +184,7 @@ bfa_ioc_ct_notify_hbfail(struct bfa_ioc_s *ioc) /** * Host to LPU mailbox message addresses */ -static struct { uint32_t hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = { +static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = { { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 }, { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 }, { HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 }, @@ -194,7 +194,7 @@ static struct { uint32_t hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = { /** * Host <-> LPU mailbox command/status registers - port 0 */ -static struct { uint32_t hfn, lpu; } iocreg_mbcmd_p0[] = { +static struct { u32 hfn, lpu; } iocreg_mbcmd_p0[] = { { HOSTFN0_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN0_MBOX0_CMD_STAT }, { HOSTFN1_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN1_MBOX0_CMD_STAT }, { HOSTFN2_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN2_MBOX0_CMD_STAT }, @@ -204,7 +204,7 @@ static struct { uint32_t hfn, lpu; } iocreg_mbcmd_p0[] = { /** * Host <-> LPU mailbox command/status registers - port 1 */ -static struct { uint32_t hfn, lpu; } iocreg_mbcmd_p1[] = { +static struct { u32 hfn, lpu; } iocreg_mbcmd_p1[] = { { HOSTFN0_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN0_MBOX0_CMD_STAT }, { HOSTFN1_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN1_MBOX0_CMD_STAT }, { HOSTFN2_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN2_MBOX0_CMD_STAT }, @@ -274,7 +274,7 @@ static void bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc) { bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; - uint32_t r32; + u32 r32; /** * For catapult, base port id on personality register and IOC type @@ -294,7 +294,7 @@ static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix) { bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; - uint32_t r32, mode; + u32 r32, mode; r32 = bfa_reg_read(rb + FNC_PERS_REG); bfa_trc(ioc, r32); @@ -324,7 +324,7 @@ static bfa_status_t bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc) { bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; - uint32_t pll_sclk, pll_fclk, r32; + u32 pll_sclk, pll_fclk, r32; /* * Hold semaphore so that nobody can access the chip during init. diff --git a/drivers/scsi/bfa/bfad_attr.h b/drivers/scsi/bfa/bfad_attr.h index 4d3312da6a81..bf0102076508 100644 --- a/drivers/scsi/bfa/bfad_attr.h +++ b/drivers/scsi/bfa/bfad_attr.h @@ -17,9 +17,6 @@ #ifndef __BFAD_ATTR_H__ #define __BFAD_ATTR_H__ -/** - * bfad_attr.h VMware driver configuration interface module. - */ /** * FC_transport_template FC transport template @@ -52,12 +49,6 @@ bfad_im_get_starget_port_name(struct scsi_target *starget); void bfad_im_get_host_port_id(struct Scsi_Host *shost); -/** - * FC transport template entry, issue a LIP. - */ -int -bfad_im_issue_fc_host_lip(struct Scsi_Host *shost); - struct Scsi_Host* bfad_os_starget_to_shost(struct scsi_target *starget); diff --git a/drivers/scsi/bfa/bfad_drv.h b/drivers/scsi/bfa/bfad_drv.h index 8617a1aa8b25..2ccd0f2ea6d1 100644 --- a/drivers/scsi/bfa/bfad_drv.h +++ b/drivers/scsi/bfa/bfad_drv.h @@ -196,11 +196,6 @@ struct bfad_s { bfa_boolean_t ipfc_enabled; union bfad_tmp_buf tmp_buf; struct fc_host_statistics link_stats; - - struct kobject *bfa_kobj; - struct kobject *ioc_kobj; - struct kobject *pport_kobj; - struct kobject *lport_kobj; }; /* @@ -286,11 +281,6 @@ void bfad_drv_uninit(struct bfad_s *bfad); void bfad_drv_log_level_set(struct bfad_s *bfad); bfa_status_t bfad_fc4_module_init(void); void bfad_fc4_module_exit(void); - -bfa_status_t bfad_os_kthread_create(struct bfad_s *bfad); -void bfad_os_kthread_stop(struct bfad_s *bfad); -void bfad_os_kthread_wakeup(struct bfad_s *bfad); -int bfad_os_kthread_should_stop(void); int bfad_worker (void *ptr); void bfad_pci_remove(struct pci_dev *pdev); diff --git a/drivers/scsi/bfa/bfad_im.c b/drivers/scsi/bfa/bfad_im.c index fb7aefaba129..f9fc67a25bf2 100644 --- a/drivers/scsi/bfa/bfad_im.c +++ b/drivers/scsi/bfa/bfad_im.c @@ -508,16 +508,6 @@ void bfa_fcb_itnim_tov(struct bfad_itnim_s *itnim) itnim->state = ITNIM_STATE_TIMEOUT; } -/** - * Path TOV processing begin notification -- dummy for linux - */ -void -bfa_fcb_itnim_tov_begin(struct bfad_itnim_s *itnim) -{ -} - - - /** * Allocate a Scsi_Host for a port. */ diff --git a/drivers/scsi/bfa/bfad_im.h b/drivers/scsi/bfa/bfad_im.h index 189a5b29e21a..85ab2da21321 100644 --- a/drivers/scsi/bfa/bfad_im.h +++ b/drivers/scsi/bfa/bfad_im.h @@ -23,7 +23,6 @@ #define FCPI_NAME " fcpim" -void bfad_flags_set(struct bfad_s *bfad, u32 flags); bfa_status_t bfad_im_module_init(void); void bfad_im_module_exit(void); bfa_status_t bfad_im_probe(struct bfad_s *bfad); @@ -126,7 +125,6 @@ bfa_status_t bfad_os_thread_workq(struct bfad_s *bfad); void bfad_os_destroy_workq(struct bfad_im_s *im); void bfad_os_itnim_process(struct bfad_itnim_s *itnim_drv); void bfad_os_fc_host_init(struct bfad_im_port_s *im_port); -void bfad_os_init_work(struct bfad_im_port_s *im_port); void bfad_os_scsi_host_free(struct bfad_s *bfad, struct bfad_im_port_s *im_port); void bfad_os_ramp_up_qdepth(struct bfad_itnim_s *itnim, @@ -136,9 +134,6 @@ struct bfad_itnim_s *bfad_os_get_itnim(struct bfad_im_port_s *im_port, int id); int bfad_os_scsi_add_host(struct Scsi_Host *shost, struct bfad_im_port_s *im_port, struct bfad_s *bfad); -/* - * scsi_host_template entries - */ void bfad_im_itnim_unmap(struct bfad_im_port_s *im_port, struct bfad_itnim_s *itnim); diff --git a/drivers/scsi/bfa/fcpim.c b/drivers/scsi/bfa/fcpim.c index ef50ec2a1950..8ae4a2cfa85b 100644 --- a/drivers/scsi/bfa/fcpim.c +++ b/drivers/scsi/bfa/fcpim.c @@ -678,7 +678,6 @@ bfa_cb_itnim_tov_begin(void *cb_arg) struct bfa_fcs_itnim_s *itnim = (struct bfa_fcs_itnim_s *)cb_arg; bfa_trc(itnim->fcs, itnim->rport->pwwn); - bfa_fcb_itnim_tov_begin(itnim->itnim_drv); } /** diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_driver.h b/drivers/scsi/bfa/include/defs/bfa_defs_driver.h index 57049805762b..50382dd2ab41 100644 --- a/drivers/scsi/bfa/include/defs/bfa_defs_driver.h +++ b/drivers/scsi/bfa/include/defs/bfa_defs_driver.h @@ -21,6 +21,7 @@ /** * Driver statistics */ +struct bfa_driver_stats_s { u16 tm_io_abort; u16 tm_io_abort_comp; u16 tm_lun_reset; @@ -34,7 +35,7 @@ u64 output_req; u64 input_words; u64 output_words; -} bfa_driver_stats_t; +}; #endif /* __BFA_DEFS_DRIVER_H__ */ diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_im_common.h b/drivers/scsi/bfa/include/defs/bfa_defs_im_common.h deleted file mode 100644 index 9ccf53bef65a..000000000000 --- a/drivers/scsi/bfa/include/defs/bfa_defs_im_common.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2005-2009 Brocade Communications Systems, Inc. - * All rights reserved - * www.brocade.com - * - * Linux driver for Brocade Fibre Channel Host Bus Adapter. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License (GPL) Version 2 as - * published by the Free Software Foundation - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ - -#ifndef __BFA_DEFS_IM_COMMON_H__ -#define __BFA_DEFS_IM_COMMON_H__ - -#define BFA_ADAPTER_NAME_LEN 256 -#define BFA_ADAPTER_GUID_LEN 256 -#define RESERVED_VLAN_NAME L"PORT VLAN" -#define PASSTHRU_VLAN_NAME L"PASSTHRU VLAN" - - u64 tx_pkt_cnt; - u64 rx_pkt_cnt; - u32 duration; - u8 status; -} bfa_im_stats_t, *pbfa_im_stats_t; - -#endif /* __BFA_DEFS_IM_COMMON_H__ */ diff --git a/drivers/scsi/bfa/include/defs/bfa_defs_im_team.h b/drivers/scsi/bfa/include/defs/bfa_defs_im_team.h deleted file mode 100644 index a486a7eb81d6..000000000000 --- a/drivers/scsi/bfa/include/defs/bfa_defs_im_team.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2005-2009 Brocade Communications Systems, Inc. - * All rights reserved - * www.brocade.com - * - * Linux driver for Brocade Fibre Channel Host Bus Adapter. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License (GPL) Version 2 as - * published by the Free Software Foundation - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ - -#ifndef __BFA_DEFS_IM_TEAM_H__ -#define __BFA_DEFS_IM_TEAM_H__ - -#include - -#define BFA_TEAM_MAX_PORTS 8 -#define BFA_TEAM_NAME_LEN 256 -#define BFA_MAX_NUM_TEAMS 16 -#define BFA_TEAM_INVALID_DELAY -1 - - BFA_LACP_RATE_SLOW = 1, - BFA_LACP_RATE_FAST -} bfa_im_lacp_rate_t; - - BFA_TEAM_MODE_FAIL_OVER = 1, - BFA_TEAM_MODE_FAIL_BACK, - BFA_TEAM_MODE_LACP, - BFA_TEAM_MODE_NONE -} bfa_im_team_mode_t; - - BFA_XMIT_POLICY_L2 = 1, - BFA_XMIT_POLICY_L3_L4 -} bfa_im_xmit_policy_t; - - bfa_im_team_mode_t team_mode; - bfa_im_lacp_rate_t lacp_rate; - bfa_im_xmit_policy_t xmit_policy; - int delay; - wchar_t primary[BFA_ADAPTER_NAME_LEN]; - wchar_t preferred_primary[BFA_ADAPTER_NAME_LEN]; - mac_t mac; - u16 num_ports; - u16 num_vlans; - u16 vlan_list[BFA_MAX_VLANS_PER_PORT]; - wchar_t team_guid_list[BFA_TEAM_MAX_PORTS][BFA_ADAPTER_GUID_LEN]; - wchar_t ioc_name_list[BFA_TEAM_MAX_PORTS][BFA_ADAPTER_NAME_LEN]; -} bfa_im_team_attr_t; - - wchar_t team_name[BFA_TEAM_NAME_LEN]; - bfa_im_xmit_policy_t xmit_policy; - int delay; - wchar_t primary[BFA_ADAPTER_NAME_LEN]; - wchar_t preferred_primary[BFA_ADAPTER_NAME_LEN]; -} bfa_im_team_edit_t, *pbfa_im_team_edit_t; - - wchar_t team_name[BFA_TEAM_NAME_LEN]; - bfa_im_team_mode_t team_mode; - mac_t mac; -} bfa_im_team_info_t; - - bfa_im_team_info_t team_info[BFA_MAX_NUM_TEAMS]; - u16 num_teams; -} bfa_im_team_list_t, *pbfa_im_team_list_t; - -#endif /* __BFA_DEFS_IM_TEAM_H__ */ diff --git a/drivers/scsi/bfa/include/fcb/bfa_fcb_fcpim.h b/drivers/scsi/bfa/include/fcb/bfa_fcb_fcpim.h index a6c70aee0aa3..52585d3dd891 100644 --- a/drivers/scsi/bfa/include/fcb/bfa_fcb_fcpim.h +++ b/drivers/scsi/bfa/include/fcb/bfa_fcb_fcpim.h @@ -70,7 +70,6 @@ void bfa_fcb_itnim_online(struct bfad_itnim_s *itnim_drv); */ void bfa_fcb_itnim_offline(struct bfad_itnim_s *itnim_drv); -void bfa_fcb_itnim_tov_begin(struct bfad_itnim_s *itnim_drv); void bfa_fcb_itnim_tov(struct bfad_itnim_s *itnim_drv); #endif /* __BFAD_FCB_FCPIM_H__ */ diff --git a/drivers/scsi/bfa/include/protocol/pcifw.h b/drivers/scsi/bfa/include/protocol/pcifw.h deleted file mode 100644 index 6830dc3ee58a..000000000000 --- a/drivers/scsi/bfa/include/protocol/pcifw.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2005-2009 Brocade Communications Systems, Inc. - * All rights reserved - * www.brocade.com - * - * Linux driver for Brocade Fibre Channel Host Bus Adapter. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License (GPL) Version 2 as - * published by the Free Software Foundation - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ - -/** - * pcifw.h PCI FW related headers - */ - -#ifndef __PCIFW_H__ -#define __PCIFW_H__ - -#pragma pack(1) - -struct pnp_hdr_s{ - u32 signature; /* "$PnP" */ - u8 rev; /* Struct revision */ - u8 len; /* Header structure len in multiples - * of 16 bytes */ - u16 off; /* Offset to next header 00 if none */ - u8 rsvd; /* Reserved byte */ - u8 cksum; /* 8-bit checksum for this header */ - u32 pnp_dev_id; /* PnP Device Id */ - u16 mfstr; /* Pointer to manufacturer string */ - u16 prstr; /* Pointer to product string */ - u8 devtype[3]; /* Device Type Code */ - u8 devind; /* Device Indicator */ - u16 bcventr; /* Bootstrap entry vector */ - u16 rsvd2; /* Reserved */ - u16 sriv; /* Static resource information vector */ -}; - -struct pci_3_0_ds_s{ - u32 sig; /* Signature "PCIR" */ - u16 vendid; /* Vendor ID */ - u16 devid; /* Device ID */ - u16 devlistoff; /* Device List Offset */ - u16 len; /* PCI Data Structure Length */ - u8 rev; /* PCI Data Structure Revision */ - u8 clcode[3]; /* Class Code */ - u16 imglen; /* Code image length in multiples of - * 512 bytes */ - u16 coderev; /* Revision level of code/data */ - u8 codetype; /* Code type 0x00 - BIOS */ - u8 indr; /* Last image indicator */ - u16 mrtimglen; /* Max Run Time Image Length */ - u16 cuoff; /* Config Utility Code Header Offset */ - u16 dmtfclp; /* DMTF CLP entry point offset */ -}; - -struct pci_optrom_hdr_s{ - u16 sig; /* Signature 0x55AA */ - u8 len; /* Option ROM length in units of 512 bytes */ - u8 inivec[3]; /* Initialization vector */ - u8 rsvd[16]; /* Reserved field */ - u16 verptr; /* Pointer to version string - private */ - u16 pcids; /* Pointer to PCI data structure */ - u16 pnphdr; /* Pointer to PnP expansion header */ -}; - -#pragma pack() - -#endif -- cgit v1.2.3 From d55f88f0275e4b21435957d3d354a79bb9edeec7 Mon Sep 17 00:00:00 2001 From: Krishna Gudipati Date: Fri, 5 Mar 2010 19:38:52 -0800 Subject: [SCSI] bfa: Update the driver version to 2.1.2.1. Upgrade the upstream driver from 2.0.0.0 to 2.1.2.1. Signed-off-by: Krishna Gudipati Signed-off-by: James Bottomley --- drivers/scsi/bfa/bfad_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/scsi/bfa/bfad_drv.h b/drivers/scsi/bfa/bfad_drv.h index 2ccd0f2ea6d1..107848cd3b6d 100644 --- a/drivers/scsi/bfa/bfad_drv.h +++ b/drivers/scsi/bfa/bfad_drv.h @@ -46,7 +46,7 @@ #ifdef BFA_DRIVER_VERSION #define BFAD_DRIVER_VERSION BFA_DRIVER_VERSION #else -#define BFAD_DRIVER_VERSION "2.0.0.0" +#define BFAD_DRIVER_VERSION "2.1.2.1" #endif -- cgit v1.2.3 From 42747d712de56cf2087b702d2ad90af114c53138 Mon Sep 17 00:00:00 2001 From: Wim Van Sebroeck Date: Sat, 26 Dec 2009 18:55:22 +0000 Subject: [WATCHDOG] watchdog_info constify make the watchdog_info struct const where possible. Signed-off-by: Wim Van Sebroeck --- arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 2 +- drivers/watchdog/acquirewdt.c | 2 +- drivers/watchdog/advantechwdt.c | 2 +- drivers/watchdog/adx_wdt.c | 2 +- drivers/watchdog/alim1535_wdt.c | 2 +- drivers/watchdog/alim7101_wdt.c | 2 +- drivers/watchdog/ar7_wdt.c | 2 +- drivers/watchdog/at32ap700x_wdt.c | 2 +- drivers/watchdog/at91rm9200_wdt.c | 2 +- drivers/watchdog/bcm47xx_wdt.c | 2 +- drivers/watchdog/bfin_wdt.c | 4 ++-- drivers/watchdog/booke_wdt.c | 2 +- drivers/watchdog/coh901327_wdt.c | 2 +- drivers/watchdog/cpu5wdt.c | 2 +- drivers/watchdog/cpwd.c | 2 +- drivers/watchdog/davinci_wdt.c | 2 +- drivers/watchdog/ep93xx_wdt.c | 2 +- drivers/watchdog/eurotechwdt.c | 2 +- drivers/watchdog/gef_wdt.c | 2 +- drivers/watchdog/geodewdt.c | 2 +- drivers/watchdog/hpwdt.c | 2 +- drivers/watchdog/i6300esb.c | 2 +- drivers/watchdog/iTCO_wdt.c | 2 +- drivers/watchdog/ib700wdt.c | 2 +- drivers/watchdog/indydog.c | 2 +- drivers/watchdog/it8712f_wdt.c | 2 +- drivers/watchdog/it87_wdt.c | 2 +- drivers/watchdog/ixp2000_wdt.c | 2 +- drivers/watchdog/ixp4xx_wdt.c | 2 +- drivers/watchdog/ks8695_wdt.c | 2 +- drivers/watchdog/machzwd.c | 2 +- drivers/watchdog/mixcomwd.c | 2 +- drivers/watchdog/mpc8xxx_wdt.c | 2 +- drivers/watchdog/mpcore_wdt.c | 2 +- drivers/watchdog/mv64x60_wdt.c | 2 +- drivers/watchdog/pc87413_wdt.c | 2 +- drivers/watchdog/pcwd.c | 2 +- drivers/watchdog/pcwd_pci.c | 2 +- drivers/watchdog/pcwd_usb.c | 2 +- drivers/watchdog/pika_wdt.c | 2 +- drivers/watchdog/pnx833x_wdt.c | 2 +- drivers/watchdog/rc32434_wdt.c | 2 +- drivers/watchdog/rdc321x_wdt.c | 2 +- drivers/watchdog/riowd.c | 2 +- drivers/watchdog/sbc_fitpc2_wdt.c | 2 +- drivers/watchdog/sch311x_wdt.c | 2 +- drivers/watchdog/stmp3xxx_wdt.c | 2 +- drivers/watchdog/w83627hf_wdt.c | 2 +- drivers/watchdog/w83977f_wdt.c | 2 +- drivers/watchdog/wdrtas.c | 2 +- drivers/watchdog/wm831x_wdt.c | 2 +- drivers/watchdog/wm8350_wdt.c | 2 +- 52 files changed, 53 insertions(+), 53 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c index 6f8ebe1085b3..072b948b2e2d 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c @@ -553,7 +553,7 @@ static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data, return 0; } -static struct watchdog_info mpc5200_wdt_info = { +static const struct watchdog_info mpc5200_wdt_info = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, .identity = WDT_IDENTITY, }; diff --git a/drivers/watchdog/acquirewdt.c b/drivers/watchdog/acquirewdt.c index 4d18c874d963..2ffce4d75443 100644 --- a/drivers/watchdog/acquirewdt.c +++ b/drivers/watchdog/acquirewdt.c @@ -150,7 +150,7 @@ static long acq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) int options, retval = -EINVAL; void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = WATCHDOG_NAME, diff --git a/drivers/watchdog/advantechwdt.c b/drivers/watchdog/advantechwdt.c index 824d076a5cd6..4d40965d2c9f 100644 --- a/drivers/watchdog/advantechwdt.c +++ b/drivers/watchdog/advantechwdt.c @@ -137,7 +137,7 @@ static long advwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) int new_timeout; void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, diff --git a/drivers/watchdog/adx_wdt.c b/drivers/watchdog/adx_wdt.c index 9d7d155364f8..a5ca7a6ee133 100644 --- a/drivers/watchdog/adx_wdt.c +++ b/drivers/watchdog/adx_wdt.c @@ -37,7 +37,7 @@ struct adx_wdt { spinlock_t lock; }; -static struct watchdog_info adx_wdt_info = { +static const struct watchdog_info adx_wdt_info = { .identity = "Avionic Design Xanthos Watchdog", .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, }; diff --git a/drivers/watchdog/alim1535_wdt.c b/drivers/watchdog/alim1535_wdt.c index 937a80fb61e1..1e9caea8ff8a 100644 --- a/drivers/watchdog/alim1535_wdt.c +++ b/drivers/watchdog/alim1535_wdt.c @@ -180,7 +180,7 @@ static long ali_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, diff --git a/drivers/watchdog/alim7101_wdt.c b/drivers/watchdog/alim7101_wdt.c index f90afdb1b255..d8d4da9a483d 100644 --- a/drivers/watchdog/alim7101_wdt.c +++ b/drivers/watchdog/alim7101_wdt.c @@ -238,7 +238,7 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, .firmware_version = 1, diff --git a/drivers/watchdog/ar7_wdt.c b/drivers/watchdog/ar7_wdt.c index 2bb95cd308c1..c764c52412e4 100644 --- a/drivers/watchdog/ar7_wdt.c +++ b/drivers/watchdog/ar7_wdt.c @@ -219,7 +219,7 @@ static ssize_t ar7_wdt_write(struct file *file, const char *data, static long ar7_wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .identity = LONGNAME, .firmware_version = 1, .options = (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | diff --git a/drivers/watchdog/at32ap700x_wdt.c b/drivers/watchdog/at32ap700x_wdt.c index 037847923dcb..6873376f986c 100644 --- a/drivers/watchdog/at32ap700x_wdt.c +++ b/drivers/watchdog/at32ap700x_wdt.c @@ -202,7 +202,7 @@ static int at32_wdt_get_status(void) return status; } -static struct watchdog_info at32_wdt_info = { +static const struct watchdog_info at32_wdt_info = { .identity = "at32ap700x watchdog", .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | diff --git a/drivers/watchdog/at91rm9200_wdt.c b/drivers/watchdog/at91rm9200_wdt.c index b185dafe1494..b3046dc4b56c 100644 --- a/drivers/watchdog/at91rm9200_wdt.c +++ b/drivers/watchdog/at91rm9200_wdt.c @@ -121,7 +121,7 @@ static int at91_wdt_settimeout(int new_time) return 0; } -static struct watchdog_info at91_wdt_info = { +static const struct watchdog_info at91_wdt_info = { .identity = "at91 watchdog", .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, }; diff --git a/drivers/watchdog/bcm47xx_wdt.c b/drivers/watchdog/bcm47xx_wdt.c index 751c003864ad..5f245522397b 100644 --- a/drivers/watchdog/bcm47xx_wdt.c +++ b/drivers/watchdog/bcm47xx_wdt.c @@ -149,7 +149,7 @@ static ssize_t bcm47xx_wdt_write(struct file *file, const char __user *data, return len; } -static struct watchdog_info bcm47xx_wdt_info = { +static const struct watchdog_info bcm47xx_wdt_info = { .identity = DRV_NAME, .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | diff --git a/drivers/watchdog/bfin_wdt.c b/drivers/watchdog/bfin_wdt.c index 2159e668751c..8c6babb2d652 100644 --- a/drivers/watchdog/bfin_wdt.c +++ b/drivers/watchdog/bfin_wdt.c @@ -74,7 +74,7 @@ static unsigned int timeout = WATCHDOG_TIMEOUT; static int nowayout = WATCHDOG_NOWAYOUT; -static struct watchdog_info bfin_wdt_info; +static const struct watchdog_info bfin_wdt_info; static unsigned long open_check; static char expect_close; static DEFINE_SPINLOCK(bfin_wdt_spinlock); @@ -388,7 +388,7 @@ static struct miscdevice bfin_wdt_miscdev = { .fops = &bfin_wdt_fops, }; -static struct watchdog_info bfin_wdt_info = { +static const struct watchdog_info bfin_wdt_info = { .identity = "Blackfin Watchdog", .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | diff --git a/drivers/watchdog/booke_wdt.c b/drivers/watchdog/booke_wdt.c index e8380ef65c1c..8b724aad6825 100644 --- a/drivers/watchdog/booke_wdt.c +++ b/drivers/watchdog/booke_wdt.c @@ -121,7 +121,7 @@ static ssize_t booke_wdt_write(struct file *file, const char __user *buf, return count; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, .identity = "PowerPC Book-E Watchdog", }; diff --git a/drivers/watchdog/coh901327_wdt.c b/drivers/watchdog/coh901327_wdt.c index 923cc68dba26..9291506b8b23 100644 --- a/drivers/watchdog/coh901327_wdt.c +++ b/drivers/watchdog/coh901327_wdt.c @@ -257,7 +257,7 @@ static long coh901327_ioctl(struct file *file, unsigned int cmd, struct watchdog_info __user *ident; int __user *i; } uarg; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, diff --git a/drivers/watchdog/cpu5wdt.c b/drivers/watchdog/cpu5wdt.c index 71f6d7eec9a8..edd3475f41db 100644 --- a/drivers/watchdog/cpu5wdt.c +++ b/drivers/watchdog/cpu5wdt.c @@ -154,7 +154,7 @@ static long cpu5wdt_ioctl(struct file *file, unsigned int cmd, void __user *argp = (void __user *)arg; int __user *p = argp; unsigned int value; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_CARDRESET, .identity = "CPU5 WDT", }; diff --git a/drivers/watchdog/cpwd.c b/drivers/watchdog/cpwd.c index 081f2955419e..37ea052d4dee 100644 --- a/drivers/watchdog/cpwd.c +++ b/drivers/watchdog/cpwd.c @@ -403,7 +403,7 @@ static int cpwd_release(struct inode *inode, struct file *file) static long cpwd_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { - static struct watchdog_info info = { + static const struct watchdog_info info = { .options = WDIOF_SETTIMEOUT, .firmware_version = 1, .identity = DRIVER_NAME, diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c index 887136de1857..56162c87f5d8 100644 --- a/drivers/watchdog/davinci_wdt.c +++ b/drivers/watchdog/davinci_wdt.c @@ -142,7 +142,7 @@ davinci_wdt_write(struct file *file, const char *data, size_t len, return len; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING, .identity = "DaVinci Watchdog", }; diff --git a/drivers/watchdog/ep93xx_wdt.c b/drivers/watchdog/ep93xx_wdt.c index cdd55e0d09f8..88ed54e50f74 100644 --- a/drivers/watchdog/ep93xx_wdt.c +++ b/drivers/watchdog/ep93xx_wdt.c @@ -131,7 +131,7 @@ ep93xx_wdt_write(struct file *file, const char __user *data, size_t len, return len; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE, .identity = "EP93xx Watchdog", }; diff --git a/drivers/watchdog/eurotechwdt.c b/drivers/watchdog/eurotechwdt.c index 9add3541fb42..d1c4e55b1db0 100644 --- a/drivers/watchdog/eurotechwdt.c +++ b/drivers/watchdog/eurotechwdt.c @@ -238,7 +238,7 @@ static long eurwdt_ioctl(struct file *file, { void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, .firmware_version = 1, diff --git a/drivers/watchdog/gef_wdt.c b/drivers/watchdog/gef_wdt.c index 26447bdeac22..abdbad034a6c 100644 --- a/drivers/watchdog/gef_wdt.c +++ b/drivers/watchdog/gef_wdt.c @@ -161,7 +161,7 @@ static long gef_wdt_ioctl(struct file *file, unsigned int cmd, int timeout; int options; void __user *argp = (void __user *)arg; - static struct watchdog_info info = { + static const struct watchdog_info info = { .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, .firmware_version = 0, diff --git a/drivers/watchdog/geodewdt.c b/drivers/watchdog/geodewdt.c index 38252ff828ca..9b49b125ad5a 100644 --- a/drivers/watchdog/geodewdt.c +++ b/drivers/watchdog/geodewdt.c @@ -142,7 +142,7 @@ static long geodewdt_ioctl(struct file *file, unsigned int cmd, int __user *p = argp; int interval; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, .firmware_version = 1, diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c index a6c5674c78e6..70c2c24660d0 100644 --- a/drivers/watchdog/hpwdt.c +++ b/drivers/watchdog/hpwdt.c @@ -554,7 +554,7 @@ static ssize_t hpwdt_write(struct file *file, const char __user *data, return len; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, diff --git a/drivers/watchdog/i6300esb.c b/drivers/watchdog/i6300esb.c index 7ba0b11ec525..2fbe7fea7ee6 100644 --- a/drivers/watchdog/i6300esb.c +++ b/drivers/watchdog/i6300esb.c @@ -256,7 +256,7 @@ static long esb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) int new_heartbeat; void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c index a619b9b74991..44bc6aa46edf 100644 --- a/drivers/watchdog/iTCO_wdt.c +++ b/drivers/watchdog/iTCO_wdt.c @@ -584,7 +584,7 @@ static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd, int new_heartbeat; void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, diff --git a/drivers/watchdog/ib700wdt.c b/drivers/watchdog/ib700wdt.c index 4bef3ddff4a5..0149d8dfc81d 100644 --- a/drivers/watchdog/ib700wdt.c +++ b/drivers/watchdog/ib700wdt.c @@ -174,7 +174,7 @@ static long ibwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, .firmware_version = 1, diff --git a/drivers/watchdog/indydog.c b/drivers/watchdog/indydog.c index bea8a124a559..1cc5609666d1 100644 --- a/drivers/watchdog/indydog.c +++ b/drivers/watchdog/indydog.c @@ -111,7 +111,7 @@ static long indydog_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { int options, retval = -EINVAL; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING, .firmware_version = 0, .identity = "Hardware Watchdog for SGI IP22", diff --git a/drivers/watchdog/it8712f_wdt.c b/drivers/watchdog/it8712f_wdt.c index daed48ded7fe..f52c162b1bea 100644 --- a/drivers/watchdog/it8712f_wdt.c +++ b/drivers/watchdog/it8712f_wdt.c @@ -236,7 +236,7 @@ static long it8712f_wdt_ioctl(struct file *file, unsigned int cmd, { void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .identity = "IT8712F Watchdog", .firmware_version = 1, .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | diff --git a/drivers/watchdog/it87_wdt.c b/drivers/watchdog/it87_wdt.c index cc133c531d08..b709b3b2d1ef 100644 --- a/drivers/watchdog/it87_wdt.c +++ b/drivers/watchdog/it87_wdt.c @@ -421,7 +421,7 @@ static ssize_t wdt_write(struct file *file, const char __user *buf, return count; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, .firmware_version = 1, .identity = WATCHDOG_NAME, diff --git a/drivers/watchdog/ixp2000_wdt.c b/drivers/watchdog/ixp2000_wdt.c index 3c79dc587958..e86952a7168c 100644 --- a/drivers/watchdog/ixp2000_wdt.c +++ b/drivers/watchdog/ixp2000_wdt.c @@ -100,7 +100,7 @@ static ssize_t ixp2000_wdt_write(struct file *file, const char *data, } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, .identity = "IXP2000 Watchdog", diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c index 147b4d5c63b3..e02c0ecda26b 100644 --- a/drivers/watchdog/ixp4xx_wdt.c +++ b/drivers/watchdog/ixp4xx_wdt.c @@ -89,7 +89,7 @@ ixp4xx_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) return len; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, .identity = "IXP4xx Watchdog", diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c index e1c82769b08e..2852bb2e3fd9 100644 --- a/drivers/watchdog/ks8695_wdt.c +++ b/drivers/watchdog/ks8695_wdt.c @@ -145,7 +145,7 @@ static int ks8695_wdt_close(struct inode *inode, struct file *file) return 0; } -static struct watchdog_info ks8695_wdt_info = { +static const struct watchdog_info ks8695_wdt_info = { .identity = "ks8695 watchdog", .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, }; diff --git a/drivers/watchdog/machzwd.c b/drivers/watchdog/machzwd.c index 47d719717a3b..2d118cf022fc 100644 --- a/drivers/watchdog/machzwd.c +++ b/drivers/watchdog/machzwd.c @@ -101,7 +101,7 @@ MODULE_PARM_DESC(nowayout, #define PFX "machzwd" -static struct watchdog_info zf_info = { +static const struct watchdog_info zf_info = { .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = "ZF-Logic watchdog", diff --git a/drivers/watchdog/mixcomwd.c b/drivers/watchdog/mixcomwd.c index 407b025cb104..bc820d16699a 100644 --- a/drivers/watchdog/mixcomwd.c +++ b/drivers/watchdog/mixcomwd.c @@ -201,7 +201,7 @@ static long mixcomwd_ioctl(struct file *file, void __user *argp = (void __user *)arg; int __user *p = argp; int status; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = "MixCOM watchdog", diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c index 38c588ee694f..4e3941c5e293 100644 --- a/drivers/watchdog/mpc8xxx_wdt.c +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -148,7 +148,7 @@ static long mpc8xxx_wdt_ioctl(struct file *file, unsigned int cmd, { void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING, .firmware_version = 1, .identity = "MPC8xxx", diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c index a2dc07c2ed49..b0646dac924e 100644 --- a/drivers/watchdog/mpcore_wdt.c +++ b/drivers/watchdog/mpcore_wdt.c @@ -213,7 +213,7 @@ static ssize_t mpcore_wdt_write(struct file *file, const char *data, return len; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, diff --git a/drivers/watchdog/mv64x60_wdt.c b/drivers/watchdog/mv64x60_wdt.c index a51dbe4c43da..97f8a48d8b78 100644 --- a/drivers/watchdog/mv64x60_wdt.c +++ b/drivers/watchdog/mv64x60_wdt.c @@ -179,7 +179,7 @@ static long mv64x60_wdt_ioctl(struct file *file, int timeout; int options; void __user *argp = (void __user *)arg; - static struct watchdog_info info = { + static const struct watchdog_info info = { .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, diff --git a/drivers/watchdog/pc87413_wdt.c b/drivers/watchdog/pc87413_wdt.c index 1a2b916e3f8d..d3aa2f1fe61d 100644 --- a/drivers/watchdog/pc87413_wdt.c +++ b/drivers/watchdog/pc87413_wdt.c @@ -407,7 +407,7 @@ static long pc87413_ioctl(struct file *file, unsigned int cmd, int __user *i; } uarg; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, diff --git a/drivers/watchdog/pcwd.c b/drivers/watchdog/pcwd.c index aa9512321f3a..06f7922606c0 100644 --- a/drivers/watchdog/pcwd.c +++ b/drivers/watchdog/pcwd.c @@ -606,7 +606,7 @@ static long pcwd_ioctl(struct file *file, unsigned int cmd, unsigned long arg) int temperature; int new_heartbeat; int __user *argp = (int __user *)arg; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_OVERHEAT | WDIOF_CARDRESET | WDIOF_KEEPALIVEPING | diff --git a/drivers/watchdog/pcwd_pci.c b/drivers/watchdog/pcwd_pci.c index 698f51bff1bc..64374d636f09 100644 --- a/drivers/watchdog/pcwd_pci.c +++ b/drivers/watchdog/pcwd_pci.c @@ -481,7 +481,7 @@ static long pcipcwd_ioctl(struct file *file, unsigned int cmd, { void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_OVERHEAT | WDIOF_CARDRESET | WDIOF_KEEPALIVEPING | diff --git a/drivers/watchdog/pcwd_usb.c b/drivers/watchdog/pcwd_usb.c index 052fe451851f..8e4eacc5bb52 100644 --- a/drivers/watchdog/pcwd_usb.c +++ b/drivers/watchdog/pcwd_usb.c @@ -404,7 +404,7 @@ static long usb_pcwd_ioctl(struct file *file, unsigned int cmd, { void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, diff --git a/drivers/watchdog/pika_wdt.c b/drivers/watchdog/pika_wdt.c index 2d22e996e996..435ec2aed4fe 100644 --- a/drivers/watchdog/pika_wdt.c +++ b/drivers/watchdog/pika_wdt.c @@ -52,7 +52,7 @@ static struct { struct timer_list timer; /* The timer that pings the watchdog */ } pikawdt_private; -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .identity = DRV_NAME, .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | diff --git a/drivers/watchdog/pnx833x_wdt.c b/drivers/watchdog/pnx833x_wdt.c index 538ec2c05197..09102f09e681 100644 --- a/drivers/watchdog/pnx833x_wdt.c +++ b/drivers/watchdog/pnx833x_wdt.c @@ -141,7 +141,7 @@ static long pnx833x_wdt_ioctl(struct file *file, unsigned int cmd, int options, new_timeout = 0; uint32_t timeout, timeout_left = 0; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, .firmware_version = 0, .identity = "Hardware Watchdog for PNX833x", diff --git a/drivers/watchdog/rc32434_wdt.c b/drivers/watchdog/rc32434_wdt.c index bf12d06b5877..d4c29b5311a4 100644 --- a/drivers/watchdog/rc32434_wdt.c +++ b/drivers/watchdog/rc32434_wdt.c @@ -198,7 +198,7 @@ static long rc32434_wdt_ioctl(struct file *file, unsigned int cmd, void __user *argp = (void __user *)arg; int new_timeout; unsigned int value; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, diff --git a/drivers/watchdog/rdc321x_wdt.c b/drivers/watchdog/rdc321x_wdt.c index 4976bfd1fce6..69c6adbd8205 100644 --- a/drivers/watchdog/rdc321x_wdt.c +++ b/drivers/watchdog/rdc321x_wdt.c @@ -149,7 +149,7 @@ static long rdc321x_wdt_ioctl(struct file *file, unsigned int cmd, { void __user *argp = (void __user *)arg; unsigned int value; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_CARDRESET, .identity = "RDC321x WDT", }; diff --git a/drivers/watchdog/riowd.c b/drivers/watchdog/riowd.c index c14ae8676903..ae57bf9e1b03 100644 --- a/drivers/watchdog/riowd.c +++ b/drivers/watchdog/riowd.c @@ -85,7 +85,7 @@ static int riowd_release(struct inode *inode, struct file *filp) static long riowd_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { - static struct watchdog_info info = { + static const struct watchdog_info info = { .options = WDIOF_SETTIMEOUT, .firmware_version = 1, .identity = DRIVER_NAME, diff --git a/drivers/watchdog/sbc_fitpc2_wdt.c b/drivers/watchdog/sbc_fitpc2_wdt.c index e6763d2a567b..8d44c9b6fb5b 100644 --- a/drivers/watchdog/sbc_fitpc2_wdt.c +++ b/drivers/watchdog/sbc_fitpc2_wdt.c @@ -111,7 +111,7 @@ out: } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, .identity = WATCHDOG_NAME, diff --git a/drivers/watchdog/sch311x_wdt.c b/drivers/watchdog/sch311x_wdt.c index 569eb295a7a8..9c40f48804f5 100644 --- a/drivers/watchdog/sch311x_wdt.c +++ b/drivers/watchdog/sch311x_wdt.c @@ -250,7 +250,7 @@ static long sch311x_wdt_ioctl(struct file *file, unsigned int cmd, int new_timeout; void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, diff --git a/drivers/watchdog/stmp3xxx_wdt.c b/drivers/watchdog/stmp3xxx_wdt.c index 5dd952681f32..b3421fd2cda8 100644 --- a/drivers/watchdog/stmp3xxx_wdt.c +++ b/drivers/watchdog/stmp3xxx_wdt.c @@ -94,7 +94,7 @@ static ssize_t stmp3xxx_wdt_write(struct file *file, const char __user *data, return len; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | diff --git a/drivers/watchdog/w83627hf_wdt.c b/drivers/watchdog/w83627hf_wdt.c index f201accc4e3d..0f5288df0091 100644 --- a/drivers/watchdog/w83627hf_wdt.c +++ b/drivers/watchdog/w83627hf_wdt.c @@ -201,7 +201,7 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) void __user *argp = (void __user *)arg; int __user *p = argp; int new_timeout; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, .firmware_version = 1, diff --git a/drivers/watchdog/w83977f_wdt.c b/drivers/watchdog/w83977f_wdt.c index 0560182a1d09..6e6743d1066f 100644 --- a/drivers/watchdog/w83977f_wdt.c +++ b/drivers/watchdog/w83977f_wdt.c @@ -371,7 +371,7 @@ static ssize_t wdt_write(struct file *file, const char __user *buf, * according to their available features. */ -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, .firmware_version = 1, .identity = WATCHDOG_NAME, diff --git a/drivers/watchdog/wdrtas.c b/drivers/watchdog/wdrtas.c index 5bfb1f2c5319..94ec22b9e66b 100644 --- a/drivers/watchdog/wdrtas.c +++ b/drivers/watchdog/wdrtas.c @@ -312,7 +312,7 @@ static long wdrtas_ioctl(struct file *file, unsigned int cmd, { int __user *argp = (void __user *)arg; int i; - static struct watchdog_info wdinfo = { + static const struct watchdog_info wdinfo = { .options = WDRTAS_SUPPORTED_MASK, .firmware_version = 0, .identity = "wdrtas", diff --git a/drivers/watchdog/wm831x_wdt.c b/drivers/watchdog/wm831x_wdt.c index 775bcd807f31..8c4b2d5bb7da 100644 --- a/drivers/watchdog/wm831x_wdt.c +++ b/drivers/watchdog/wm831x_wdt.c @@ -213,7 +213,7 @@ static ssize_t wm831x_wdt_write(struct file *file, return count; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, .identity = "WM831x Watchdog", }; diff --git a/drivers/watchdog/wm8350_wdt.c b/drivers/watchdog/wm8350_wdt.c index a2d2e8eb2282..89dd7b035295 100644 --- a/drivers/watchdog/wm8350_wdt.c +++ b/drivers/watchdog/wm8350_wdt.c @@ -177,7 +177,7 @@ static ssize_t wm8350_wdt_write(struct file *file, return count; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, .identity = "WM8350 Watchdog", }; -- cgit v1.2.3 From 168b5251adddb1554926cfb94f79a8a28bc6ebe5 Mon Sep 17 00:00:00 2001 From: Wim Van Sebroeck Date: Sat, 26 Dec 2009 19:13:00 +0000 Subject: [WATCHDOG] change reboot_notifier to platform-shutdown method. Platform device drivers can use the .shutdown method to handle soft shutdown's instead of reboot_notifier's. Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/bfin_wdt.c | 52 +++++++++++++-------------------------------- drivers/watchdog/txx9wdt.c | 25 ++++++---------------- 2 files changed, 21 insertions(+), 56 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/bfin_wdt.c b/drivers/watchdog/bfin_wdt.c index 8c6babb2d652..9c7ccd1e9088 100644 --- a/drivers/watchdog/bfin_wdt.c +++ b/drivers/watchdog/bfin_wdt.c @@ -19,8 +19,6 @@ #include #include #include -#include -#include #include #include #include @@ -309,26 +307,6 @@ static long bfin_wdt_ioctl(struct file *file, } } -/** - * bfin_wdt_notify_sys - Notifier Handler - * @this: notifier block - * @code: notifier event - * @unused: unused - * - * Handles specific events, such as turning off the watchdog during a - * shutdown event. - */ -static int bfin_wdt_notify_sys(struct notifier_block *this, - unsigned long code, void *unused) -{ - stampit(); - - if (code == SYS_DOWN || code == SYS_HALT) - bfin_wdt_stop(); - - return NOTIFY_DONE; -} - #ifdef CONFIG_PM static int state_before_suspend; @@ -395,33 +373,21 @@ static const struct watchdog_info bfin_wdt_info = { WDIOF_MAGICCLOSE, }; -static struct notifier_block bfin_wdt_notifier = { - .notifier_call = bfin_wdt_notify_sys, -}; - /** * bfin_wdt_probe - Initialize module * - * Registers the misc device and notifier handler. Actual device + * Registers the misc device. Actual device * initialization is handled by bfin_wdt_open(). */ static int __devinit bfin_wdt_probe(struct platform_device *pdev) { int ret; - ret = register_reboot_notifier(&bfin_wdt_notifier); - if (ret) { - pr_devinit(KERN_ERR PFX - "cannot register reboot notifier (err=%d)\n", ret); - return ret; - } - ret = misc_register(&bfin_wdt_miscdev); if (ret) { pr_devinit(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", WATCHDOG_MINOR, ret); - unregister_reboot_notifier(&bfin_wdt_notifier); return ret; } @@ -434,21 +400,33 @@ static int __devinit bfin_wdt_probe(struct platform_device *pdev) /** * bfin_wdt_remove - Initialize module * - * Unregisters the misc device and notifier handler. Actual device + * Unregisters the misc device. Actual device * deinitialization is handled by bfin_wdt_close(). */ static int __devexit bfin_wdt_remove(struct platform_device *pdev) { misc_deregister(&bfin_wdt_miscdev); - unregister_reboot_notifier(&bfin_wdt_notifier); return 0; } +/** + * bfin_wdt_shutdown - Soft Shutdown Handler + * + * Handles the soft shutdown event. + */ +static void bfin_wdt_shutdown(struct platform_device *pdev) +{ + stampit(); + + bfin_wdt_stop(); +} + static struct platform_device *bfin_wdt_device; static struct platform_driver bfin_wdt_driver = { .probe = bfin_wdt_probe, .remove = __devexit_p(bfin_wdt_remove), + .shutdown = bfin_wdt_shutdown, .suspend = bfin_wdt_suspend, .resume = bfin_wdt_resume, .driver = { diff --git a/drivers/watchdog/txx9wdt.c b/drivers/watchdog/txx9wdt.c index d635566e9307..9e9ed7bfabcb 100644 --- a/drivers/watchdog/txx9wdt.c +++ b/drivers/watchdog/txx9wdt.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -166,14 +165,6 @@ static long txx9wdt_ioctl(struct file *file, unsigned int cmd, } } -static int txx9wdt_notify_sys(struct notifier_block *this, unsigned long code, - void *unused) -{ - if (code == SYS_DOWN || code == SYS_HALT) - txx9wdt_stop(); - return NOTIFY_DONE; -} - static const struct file_operations txx9wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, @@ -189,10 +180,6 @@ static struct miscdevice txx9wdt_miscdev = { .fops = &txx9wdt_fops, }; -static struct notifier_block txx9wdt_notifier = { - .notifier_call = txx9wdt_notify_sys, -}; - static int __init txx9wdt_probe(struct platform_device *dev) { struct resource *res; @@ -221,13 +208,8 @@ static int __init txx9wdt_probe(struct platform_device *dev) if (!txx9wdt_reg) goto exit_busy; - ret = register_reboot_notifier(&txx9wdt_notifier); - if (ret) - goto exit; - ret = misc_register(&txx9wdt_miscdev); if (ret) { - unregister_reboot_notifier(&txx9wdt_notifier); goto exit; } @@ -249,14 +231,19 @@ exit: static int __exit txx9wdt_remove(struct platform_device *dev) { misc_deregister(&txx9wdt_miscdev); - unregister_reboot_notifier(&txx9wdt_notifier); clk_disable(txx9_imclk); clk_put(txx9_imclk); return 0; } +static void txx9wdt_shutdown(struct platform_device *dev) +{ + txx9wdt_stop(); +} + static struct platform_driver txx9wdt_driver = { .remove = __exit_p(txx9wdt_remove), + .shutdown = txx9wdt_shutdown, .driver = { .name = "txx9wdt", .owner = THIS_MODULE, -- cgit v1.2.3 From c1bf3acffcddcf794e3d8a1d25fb8bd4d5912383 Mon Sep 17 00:00:00 2001 From: Andrew Morton Date: Wed, 3 Mar 2010 11:57:40 -0800 Subject: [WATCHDOG] drivers/watchdog/wdt.c:wdt_ioctl(): make `ident' non-static Making this instance static exposes the code to SMP races, etc. Signed-off-by: Andrew Morton Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/wdt.c | 2 +- drivers/watchdog/wdt_pci.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/wdt.c b/drivers/watchdog/wdt.c index 3bbefe9a2634..bfda2e99dd89 100644 --- a/drivers/watchdog/wdt.c +++ b/drivers/watchdog/wdt.c @@ -358,7 +358,7 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) int new_heartbeat; int status; - static struct watchdog_info ident = { + struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT| WDIOF_MAGICCLOSE| WDIOF_KEEPALIVEPING, diff --git a/drivers/watchdog/wdt_pci.c b/drivers/watchdog/wdt_pci.c index f368dd87083a..7b22e3cdbc81 100644 --- a/drivers/watchdog/wdt_pci.c +++ b/drivers/watchdog/wdt_pci.c @@ -412,7 +412,7 @@ static long wdtpci_ioctl(struct file *file, unsigned int cmd, int new_heartbeat; int status; - static struct watchdog_info ident = { + struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT| WDIOF_MAGICCLOSE| WDIOF_KEEPALIVEPING, -- cgit v1.2.3 From 1dace8c801ac531022bd31a7316a6b4351837617 Mon Sep 17 00:00:00 2001 From: Jeff Dike Date: Thu, 4 Mar 2010 16:10:14 -0500 Subject: vhost: fix error path in vhost_net_set_backend An error could cause vhost_net_set_backend to exit without unlocking vq->mutex. Fix this. Signed-off-by: Jeff Dike Signed-off-by: Michael S. Tsirkin --- drivers/vhost/net.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/vhost/net.c b/drivers/vhost/net.c index ad37da2b6cb5..fcafb6b170fb 100644 --- a/drivers/vhost/net.c +++ b/drivers/vhost/net.c @@ -508,12 +508,12 @@ static long vhost_net_set_backend(struct vhost_net *n, unsigned index, int fd) /* Verify that ring has been setup correctly. */ if (!vhost_vq_access_ok(vq)) { r = -EFAULT; - goto err; + goto err_vq; } sock = get_socket(fd); if (IS_ERR(sock)) { r = PTR_ERR(sock); - goto err; + goto err_vq; } /* start polling new socket */ @@ -524,12 +524,14 @@ static long vhost_net_set_backend(struct vhost_net *n, unsigned index, int fd) vhost_net_disable_vq(n, vq); rcu_assign_pointer(vq->private_data, sock); vhost_net_enable_vq(n, vq); - mutex_unlock(&vq->mutex); done: if (oldsock) { vhost_net_flush_vq(n, index); fput(oldsock->file); } + +err_vq: + mutex_unlock(&vq->mutex); err: mutex_unlock(&n->dev.mutex); return r; -- cgit v1.2.3 From b8fa05719ba4349be80ce929237249b57886a203 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sun, 7 Mar 2010 09:54:44 -0800 Subject: Revert "lib: build list_sort() only if needed" This reverts commit a069c266ae5fdfbf5b4aecf2c672413aa33b2504. It turns ou that not only was it missing a case (XFS) that needed it, but perhaps more importantly, people sometimes want to enable new modules that they hadn't had enabled before, and if such a module uses list_sort(), it can't easily be inserted any more. So rather than add a "select LIST_SORT" to the XFS case, just leave it compiled in. It's not all _that_ big, after all, and the inconvenience isn't worth it. Requested-by: Alexey Dobriyan Cc: Christoph Hellwig Cc: Don Mullis Cc: Andrew Morton Cc: Dave Chinner Signed-off-by: Linus Torvalds --- drivers/gpu/drm/Kconfig | 1 - fs/ubifs/Kconfig | 1 - lib/Kconfig | 3 --- lib/Makefile | 3 +-- 4 files changed, 1 insertion(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 3d2ab03f1296..305c59003963 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -9,7 +9,6 @@ menuconfig DRM depends on (AGP || AGP=n) && PCI && !EMULATED_CMPXCHG && MMU select I2C select I2C_ALGOBIT - select LIST_SORT help Kernel-level support for the Direct Rendering Infrastructure (DRI) introduced in XFree86 4.0. If you say Y here, you need to select diff --git a/fs/ubifs/Kconfig b/fs/ubifs/Kconfig index 430c69f39842..830e3f76f442 100644 --- a/fs/ubifs/Kconfig +++ b/fs/ubifs/Kconfig @@ -7,7 +7,6 @@ config UBIFS_FS select CRYPTO if UBIFS_FS_ZLIB select CRYPTO_LZO if UBIFS_FS_LZO select CRYPTO_DEFLATE if UBIFS_FS_ZLIB - select LIST_SORT depends on MTD_UBI help UBIFS is a file system for flash devices which works on top of UBI. diff --git a/lib/Kconfig b/lib/Kconfig index 496d16e1fa2c..170d8ca901d8 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -160,9 +160,6 @@ config TEXTSEARCH_BM config TEXTSEARCH_FSM tristate -config LIST_SORT - boolean - config BTREE boolean diff --git a/lib/Makefile b/lib/Makefile index 59e46a014bc6..2e152aed7198 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -21,7 +21,7 @@ lib-y += kobject.o kref.o klist.o obj-y += bcd.o div64.o sort.o parser.o halfmd4.o debug_locks.o random32.o \ bust_spinlocks.o hexdump.o kasprintf.o bitmap.o scatterlist.o \ - string_helpers.o gcd.o + string_helpers.o gcd.o list_sort.o ifeq ($(CONFIG_DEBUG_KOBJECT),y) CFLAGS_kobject.o += -DDEBUG @@ -40,7 +40,6 @@ lib-$(CONFIG_GENERIC_FIND_FIRST_BIT) += find_next_bit.o lib-$(CONFIG_GENERIC_FIND_NEXT_BIT) += find_next_bit.o obj-$(CONFIG_GENERIC_FIND_LAST_BIT) += find_last_bit.o obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o -obj-$(CONFIG_LIST_SORT) += list_sort.o obj-$(CONFIG_LOCK_KERNEL) += kernel_lock.o obj-$(CONFIG_BTREE) += btree.o obj-$(CONFIG_DEBUG_PREEMPT) += smp_processor_id.o -- cgit v1.2.3 From 3ceb85ae35421c5bc560c7af8d0dd1c73d071ad0 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Sun, 7 Mar 2010 12:37:17 -0800 Subject: USB: remove unused defintion of struct usb_device_status The recent rework of /proc/bus/usb/devices polling support made this structure unused so let's remove it. Signed-off-by: Dmitry Torokhov Signed-off-by: Linus Torvalds --- drivers/usb/core/devices.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/core/devices.c b/drivers/usb/core/devices.c index 6053a8b730cd..d41811bfef2a 100644 --- a/drivers/usb/core/devices.c +++ b/drivers/usb/core/devices.c @@ -133,11 +133,6 @@ static struct device_connect_event { .wait = __WAIT_QUEUE_HEAD_INITIALIZER(device_event.wait) }; -/* this struct stores the poll state for /devices pollers */ -struct usb_device_status { - unsigned int lastev; -}; - struct class_info { int class; char *class_name; -- cgit v1.2.3 From 311e54c07e784fe63d421f724dcc597d1f82ccad Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Tue, 5 Jan 2010 19:55:54 +0100 Subject: mfd: Use resource_size() in sm501 The requested memory region is smaller than the actual ioremap(). Use resource_size() to get the correct size. Signed-off-by: H Hartley Sweeten Cc: Ben Dooks Signed-off-by: Samuel Ortiz --- drivers/mfd/sm501.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c index 0cc5eeff5ee8..dc9ea95c0561 100644 --- a/drivers/mfd/sm501.c +++ b/drivers/mfd/sm501.c @@ -1430,7 +1430,7 @@ static int __devinit sm501_plat_probe(struct platform_device *dev) } sm->regs_claim = request_mem_region(sm->io_res->start, - 0x100, "sm501"); + resource_size(sm->io_res), "sm501"); if (sm->regs_claim == NULL) { dev_err(&dev->dev, "cannot claim registers\n"); @@ -1440,8 +1440,7 @@ static int __devinit sm501_plat_probe(struct platform_device *dev) platform_set_drvdata(dev, sm); - sm->regs = ioremap(sm->io_res->start, - (sm->io_res->end - sm->io_res->start) - 1); + sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res)); if (sm->regs == NULL) { dev_err(&dev->dev, "cannot remap registers\n"); @@ -1645,7 +1644,7 @@ static int __devinit sm501_pci_probe(struct pci_dev *dev, sm->mem_res = &dev->resource[0]; sm->regs_claim = request_mem_region(sm->io_res->start, - 0x100, "sm501"); + resource_size(sm->io_res), "sm501"); if (sm->regs_claim == NULL) { dev_err(&dev->dev, "cannot claim registers\n"); err= -EBUSY; -- cgit v1.2.3 From c02e6a5ff43d24d73cf7830c2925e213fc72e037 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Tue, 5 Jan 2010 19:58:34 +0100 Subject: mfd: Use resource_size() for t7l66xb Use resource_size() for ioremap. Signed-off-by: H Hartley Sweeten Cc: Ian Molton Signed-off-by: Samuel Ortiz --- drivers/mfd/t7l66xb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mfd/t7l66xb.c b/drivers/mfd/t7l66xb.c index bcf4687d4af5..e0bbddd7aac2 100644 --- a/drivers/mfd/t7l66xb.c +++ b/drivers/mfd/t7l66xb.c @@ -360,7 +360,7 @@ static int t7l66xb_probe(struct platform_device *dev) if (ret) goto err_request_scr; - t7l66xb->scr = ioremap(rscr->start, rscr->end - rscr->start + 1); + t7l66xb->scr = ioremap(rscr->start, resource_size(rscr)); if (!t7l66xb->scr) { ret = -ENOMEM; goto err_ioremap; -- cgit v1.2.3 From 1ecc09e765d3ae16ef42a4d454836d9ed804fd18 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Tue, 5 Jan 2010 20:01:16 +0100 Subject: mfd: Use resouce_size for tc6393xb Use resource_size() for ioremap. Signed-off-by: H Hartley Sweeten Cc: Ian Molton Signed-off-by: Samuel Ortiz --- drivers/mfd/tc6393xb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mfd/tc6393xb.c b/drivers/mfd/tc6393xb.c index 4bc5a08a2b09..c59e5c5737d0 100644 --- a/drivers/mfd/tc6393xb.c +++ b/drivers/mfd/tc6393xb.c @@ -647,7 +647,7 @@ static int __devinit tc6393xb_probe(struct platform_device *dev) if (ret) goto err_request_scr; - tc6393xb->scr = ioremap(rscr->start, rscr->end - rscr->start + 1); + tc6393xb->scr = ioremap(rscr->start, resource_size(rscr)); if (!tc6393xb->scr) { ret = -ENOMEM; goto err_ioremap; -- cgit v1.2.3 From 0e820ab60118e06db62ef4e55b6dd96db807a34e Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Tue, 22 Dec 2009 21:31:43 +0100 Subject: mfd: Correct use after free for t7l66xb The structure t7l66xb should not be freed before the subsequent references to its fields in the arguments to clk_put. Furthermore, this structure is allocated near the beginning of the function, and a goto to the label err_noirq appears after a successful allocation, so it would seem that the kfree should be moved down below this label. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // @@ expression x,e; identifier f; iterator I; statement S; @@ *kfree(x); ... when != &x when != x = e when != I(x,...) S *x->f // Signed-off-by: Julia Lawall --- drivers/mfd/t7l66xb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mfd/t7l66xb.c b/drivers/mfd/t7l66xb.c index e0bbddd7aac2..26d9176fca91 100644 --- a/drivers/mfd/t7l66xb.c +++ b/drivers/mfd/t7l66xb.c @@ -403,12 +403,12 @@ static int t7l66xb_probe(struct platform_device *dev) err_ioremap: release_resource(&t7l66xb->rscr); err_request_scr: - kfree(t7l66xb); clk_put(t7l66xb->clk48m); err_clk48m_get: clk_put(t7l66xb->clk32k); err_clk32k_get: err_noirq: + kfree(t7l66xb); return ret; } -- cgit v1.2.3 From f99344fc69c3df46786a39ea4283a4175ea40b3f Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 5 Jan 2010 13:59:07 +0000 Subject: mfd: Add a data argument to the WM8350 IRQ free function To better match genirq. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/mfd/wm8350-irq.c | 2 +- drivers/power/wm8350_power.c | 24 ++++++++++++------------ drivers/regulator/wm8350-regulator.c | 2 +- drivers/rtc/rtc-wm8350.c | 4 ++-- include/linux/mfd/wm8350/core.h | 3 ++- sound/soc/codecs/wm8350.c | 4 ++-- 6 files changed, 20 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/wm8350-irq.c b/drivers/mfd/wm8350-irq.c index 9025f29e2707..655836bc69a0 100644 --- a/drivers/mfd/wm8350-irq.c +++ b/drivers/mfd/wm8350-irq.c @@ -451,7 +451,7 @@ int wm8350_register_irq(struct wm8350 *wm8350, int irq, } EXPORT_SYMBOL_GPL(wm8350_register_irq); -int wm8350_free_irq(struct wm8350 *wm8350, int irq) +int wm8350_free_irq(struct wm8350 *wm8350, int irq, void *data) { if (irq < 0 || irq >= WM8350_NUM_IRQ) return -EINVAL; diff --git a/drivers/power/wm8350_power.c b/drivers/power/wm8350_power.c index ad4f071e1287..3839a5e1c4a7 100644 --- a/drivers/power/wm8350_power.c +++ b/drivers/power/wm8350_power.c @@ -428,18 +428,18 @@ static void wm8350_init_charger(struct wm8350 *wm8350) static void free_charger_irq(struct wm8350 *wm8350) { - wm8350_free_irq(wm8350, WM8350_IRQ_CHG_BAT_HOT); - wm8350_free_irq(wm8350, WM8350_IRQ_CHG_BAT_COLD); - wm8350_free_irq(wm8350, WM8350_IRQ_CHG_BAT_FAIL); - wm8350_free_irq(wm8350, WM8350_IRQ_CHG_TO); - wm8350_free_irq(wm8350, WM8350_IRQ_CHG_END); - wm8350_free_irq(wm8350, WM8350_IRQ_CHG_START); - wm8350_free_irq(wm8350, WM8350_IRQ_CHG_VBATT_LT_3P9); - wm8350_free_irq(wm8350, WM8350_IRQ_CHG_VBATT_LT_3P1); - wm8350_free_irq(wm8350, WM8350_IRQ_CHG_VBATT_LT_2P85); - wm8350_free_irq(wm8350, WM8350_IRQ_EXT_USB_FB); - wm8350_free_irq(wm8350, WM8350_IRQ_EXT_WALL_FB); - wm8350_free_irq(wm8350, WM8350_IRQ_EXT_BAT_FB); + wm8350_free_irq(wm8350, WM8350_IRQ_CHG_BAT_HOT, wm8350); + wm8350_free_irq(wm8350, WM8350_IRQ_CHG_BAT_COLD, wm8350); + wm8350_free_irq(wm8350, WM8350_IRQ_CHG_BAT_FAIL, wm8350); + wm8350_free_irq(wm8350, WM8350_IRQ_CHG_TO, wm8350); + wm8350_free_irq(wm8350, WM8350_IRQ_CHG_END, wm8350); + wm8350_free_irq(wm8350, WM8350_IRQ_CHG_START, wm8350); + wm8350_free_irq(wm8350, WM8350_IRQ_CHG_VBATT_LT_3P9, wm8350); + wm8350_free_irq(wm8350, WM8350_IRQ_CHG_VBATT_LT_3P1, wm8350); + wm8350_free_irq(wm8350, WM8350_IRQ_CHG_VBATT_LT_2P85, wm8350); + wm8350_free_irq(wm8350, WM8350_IRQ_EXT_USB_FB, wm8350); + wm8350_free_irq(wm8350, WM8350_IRQ_EXT_WALL_FB, wm8350); + wm8350_free_irq(wm8350, WM8350_IRQ_EXT_BAT_FB, wm8350); } static __devinit int wm8350_power_probe(struct platform_device *pdev) diff --git a/drivers/regulator/wm8350-regulator.c b/drivers/regulator/wm8350-regulator.c index 94227dd6ba7b..723cd1fb4867 100644 --- a/drivers/regulator/wm8350-regulator.c +++ b/drivers/regulator/wm8350-regulator.c @@ -1453,7 +1453,7 @@ static int wm8350_regulator_remove(struct platform_device *pdev) struct regulator_dev *rdev = platform_get_drvdata(pdev); struct wm8350 *wm8350 = rdev_get_drvdata(rdev); - wm8350_free_irq(wm8350, wm8350_reg[pdev->id].irq); + wm8350_free_irq(wm8350, wm8350_reg[pdev->id].irq, rdev); regulator_unregister(rdev); diff --git a/drivers/rtc/rtc-wm8350.c b/drivers/rtc/rtc-wm8350.c index f1e440521c54..a5512f515998 100644 --- a/drivers/rtc/rtc-wm8350.c +++ b/drivers/rtc/rtc-wm8350.c @@ -478,8 +478,8 @@ static int __devexit wm8350_rtc_remove(struct platform_device *pdev) struct wm8350 *wm8350 = platform_get_drvdata(pdev); struct wm8350_rtc *wm_rtc = &wm8350->rtc; - wm8350_free_irq(wm8350, WM8350_IRQ_RTC_SEC); - wm8350_free_irq(wm8350, WM8350_IRQ_RTC_ALM); + wm8350_free_irq(wm8350, WM8350_IRQ_RTC_SEC, wm8350); + wm8350_free_irq(wm8350, WM8350_IRQ_RTC_ALM, wm8350); rtc_device_unregister(wm_rtc->rtc); diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h index 43868899bf49..8883125ddea1 100644 --- a/include/linux/mfd/wm8350/core.h +++ b/include/linux/mfd/wm8350/core.h @@ -680,7 +680,8 @@ int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src); int wm8350_register_irq(struct wm8350 *wm8350, int irq, irq_handler_t handler, unsigned long flags, const char *name, void *data); -int wm8350_free_irq(struct wm8350 *wm8350, int irq); +int wm8350_free_irq(struct wm8350 *wm8350, int irq, void *data); + int wm8350_mask_irq(struct wm8350 *wm8350, int irq); int wm8350_unmask_irq(struct wm8350 *wm8350, int irq); int wm8350_irq_init(struct wm8350 *wm8350, int irq, diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c index 718ef912e758..079bf745bf05 100644 --- a/sound/soc/codecs/wm8350.c +++ b/sound/soc/codecs/wm8350.c @@ -1521,8 +1521,8 @@ static int wm8350_remove(struct platform_device *pdev) WM8350_JDL_ENA | WM8350_JDR_ENA); wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); - wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L); - wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); + wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv); + wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv); priv->hpl.jack = NULL; priv->hpr.jack = NULL; -- cgit v1.2.3 From 29c71b138c83c8191f1f7e46fcc28b9d6bc8a5dd Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 5 Jan 2010 13:59:08 +0000 Subject: rtc: Suppress duplicate enable/disable of WM8350 update interrupt Unlike the wm8350-custom code genirq nests enable and disable calls so we can't just unconditionally mask or unmask the interrupt, we need to remember the state we set and only mask or unmask when there is a real change. Signed-off-by: Mark Brown Acked-by: Alessandro Zummo Cc: rtc-linux@googlegroups.com Signed-off-by: Samuel Ortiz --- drivers/rtc/rtc-wm8350.c | 7 +++++++ include/linux/mfd/wm8350/rtc.h | 1 + 2 files changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/rtc/rtc-wm8350.c b/drivers/rtc/rtc-wm8350.c index a5512f515998..3d0dc76b38af 100644 --- a/drivers/rtc/rtc-wm8350.c +++ b/drivers/rtc/rtc-wm8350.c @@ -307,11 +307,18 @@ static int wm8350_rtc_update_irq_enable(struct device *dev, { struct wm8350 *wm8350 = dev_get_drvdata(dev); + /* Suppress duplicate changes since genirq nests enable and + * disable calls. */ + if (enabled == wm8350->rtc.update_enabled) + return 0; + if (enabled) wm8350_unmask_irq(wm8350, WM8350_IRQ_RTC_SEC); else wm8350_mask_irq(wm8350, WM8350_IRQ_RTC_SEC); + wm8350->rtc.update_enabled = enabled; + return 0; } diff --git a/include/linux/mfd/wm8350/rtc.h b/include/linux/mfd/wm8350/rtc.h index 24add2bef6c9..ebd72ffc62d1 100644 --- a/include/linux/mfd/wm8350/rtc.h +++ b/include/linux/mfd/wm8350/rtc.h @@ -263,6 +263,7 @@ struct wm8350_rtc { struct platform_device *pdev; struct rtc_device *rtc; int alarm_enabled; /* used over suspend/resume */ + int update_enabled; }; #endif -- cgit v1.2.3 From 760e4518788df6762700e6bb9dd8692379f11168 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 5 Jan 2010 13:59:09 +0000 Subject: mfd: Convert WM8350 to genirq This gives us use of the diagnostic facilities genirq provides and will allow implementation of interrupt support for the WM8350 GPIOs. Stub functions are provided to ease the transition of the individual drivers, probably after additional work to pass the IRQ numbers via the struct devices. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/mfd/wm8350-irq.c | 155 ++++++++++++++++++++++------------------ include/linux/mfd/wm8350/core.h | 44 ++++++++---- 2 files changed, 118 insertions(+), 81 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/wm8350-irq.c b/drivers/mfd/wm8350-irq.c index 655836bc69a0..f56c9adf9493 100644 --- a/drivers/mfd/wm8350-irq.c +++ b/drivers/mfd/wm8350-irq.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include @@ -29,8 +29,6 @@ #include #include -#define WM8350_NUM_IRQ_REGS 7 - #define WM8350_INT_OFFSET_1 0 #define WM8350_INT_OFFSET_2 1 #define WM8350_POWER_UP_INT_OFFSET 2 @@ -366,19 +364,10 @@ static struct wm8350_irq_data wm8350_irqs[] = { }, }; -static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq) +static inline struct wm8350_irq_data *irq_to_wm8350_irq(struct wm8350 *wm8350, + int irq) { - mutex_lock(&wm8350->irq_mutex); - - if (wm8350->irq[irq].handler) - wm8350->irq[irq].handler(irq, wm8350->irq[irq].data); - else { - dev_err(wm8350->dev, "irq %d nobody cared. now masked.\n", - irq); - wm8350_mask_irq(wm8350, irq); - } - - mutex_unlock(&wm8350->irq_mutex); + return &wm8350_irqs[irq - wm8350->irq_base]; } /* @@ -386,7 +375,9 @@ static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq) * interrupts are clear on read the IRQ line will be reasserted and * the physical IRQ will be handled again if another interrupt is * asserted while we run - in the normal course of events this is a - * rare occurrence so we save I2C/SPI reads. + * rare occurrence so we save I2C/SPI reads. We're also assuming that + * it's rare to get lots of interrupts firing simultaneously so try to + * minimise I/O. */ static irqreturn_t wm8350_irq(int irq, void *irq_data) { @@ -397,7 +388,6 @@ static irqreturn_t wm8350_irq(int irq, void *irq_data) struct wm8350_irq_data *data; int i; - /* TODO: Use block reads to improve performance? */ level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS) & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK); @@ -416,93 +406,101 @@ static irqreturn_t wm8350_irq(int irq, void *irq_data) sub_reg[data->reg] = wm8350_reg_read(wm8350, WM8350_INT_STATUS_1 + data->reg); - sub_reg[data->reg] &= - ~wm8350_reg_read(wm8350, - WM8350_INT_STATUS_1_MASK + - data->reg); + sub_reg[data->reg] &= ~wm8350->irq_masks[data->reg]; read_done[data->reg] = 1; } if (sub_reg[data->reg] & data->mask) - wm8350_irq_call_handler(wm8350, i); + handle_nested_irq(wm8350->irq_base + i); } return IRQ_HANDLED; } -int wm8350_register_irq(struct wm8350 *wm8350, int irq, - irq_handler_t handler, unsigned long flags, - const char *name, void *data) +static void wm8350_irq_lock(unsigned int irq) { - if (irq < 0 || irq >= WM8350_NUM_IRQ || !handler) - return -EINVAL; - - if (wm8350->irq[irq].handler) - return -EBUSY; - - mutex_lock(&wm8350->irq_mutex); - wm8350->irq[irq].handler = handler; - wm8350->irq[irq].data = data; - mutex_unlock(&wm8350->irq_mutex); - - wm8350_unmask_irq(wm8350, irq); + struct wm8350 *wm8350 = get_irq_chip_data(irq); - return 0; + mutex_lock(&wm8350->irq_lock); } -EXPORT_SYMBOL_GPL(wm8350_register_irq); -int wm8350_free_irq(struct wm8350 *wm8350, int irq, void *data) +static void wm8350_irq_sync_unlock(unsigned int irq) { - if (irq < 0 || irq >= WM8350_NUM_IRQ) - return -EINVAL; + struct wm8350 *wm8350 = get_irq_chip_data(irq); + int i; - wm8350_mask_irq(wm8350, irq); + for (i = 0; i < ARRAY_SIZE(wm8350->irq_masks); i++) { + /* If there's been a change in the mask write it back + * to the hardware. */ + if (wm8350->irq_masks[i] != + wm8350->reg_cache[WM8350_INT_STATUS_1_MASK + i]) + WARN_ON(wm8350_reg_write(wm8350, + WM8350_INT_STATUS_1_MASK + i, + wm8350->irq_masks[i])); + } - mutex_lock(&wm8350->irq_mutex); - wm8350->irq[irq].handler = NULL; - mutex_unlock(&wm8350->irq_mutex); - return 0; + mutex_unlock(&wm8350->irq_lock); } -EXPORT_SYMBOL_GPL(wm8350_free_irq); -int wm8350_mask_irq(struct wm8350 *wm8350, int irq) +static void wm8350_irq_enable(unsigned int irq) { - return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK + - wm8350_irqs[irq].reg, - wm8350_irqs[irq].mask); + struct wm8350 *wm8350 = get_irq_chip_data(irq); + struct wm8350_irq_data *irq_data = irq_to_wm8350_irq(wm8350, irq); + + wm8350->irq_masks[irq_data->reg] &= ~irq_data->mask; } -EXPORT_SYMBOL_GPL(wm8350_mask_irq); -int wm8350_unmask_irq(struct wm8350 *wm8350, int irq) +static void wm8350_irq_disable(unsigned int irq) { - return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK + - wm8350_irqs[irq].reg, - wm8350_irqs[irq].mask); + struct wm8350 *wm8350 = get_irq_chip_data(irq); + struct wm8350_irq_data *irq_data = irq_to_wm8350_irq(wm8350, irq); + + wm8350->irq_masks[irq_data->reg] |= irq_data->mask; } -EXPORT_SYMBOL_GPL(wm8350_unmask_irq); + +static struct irq_chip wm8350_irq_chip = { + .name = "wm8350", + .bus_lock = wm8350_irq_lock, + .bus_sync_unlock = wm8350_irq_sync_unlock, + .disable = wm8350_irq_disable, + .enable = wm8350_irq_enable, +}; int wm8350_irq_init(struct wm8350 *wm8350, int irq, struct wm8350_platform_data *pdata) { - int ret; + int ret, cur_irq, i; int flags = IRQF_ONESHOT; if (!irq) { - dev_err(wm8350->dev, "No IRQ configured\n"); - return -EINVAL; + dev_warn(wm8350->dev, "No interrupt support, no core IRQ\n"); + return 0; + } + + if (!pdata || !pdata->irq_base) { + dev_warn(wm8350->dev, "No interrupt support, no IRQ base\n"); + return 0; } + /* Mask top level interrupts */ wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0xFFFF); - wm8350_reg_write(wm8350, WM8350_INT_STATUS_1_MASK, 0xFFFF); - wm8350_reg_write(wm8350, WM8350_INT_STATUS_2_MASK, 0xFFFF); - wm8350_reg_write(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS_MASK, 0xFFFF); - wm8350_reg_write(wm8350, WM8350_GPIO_INT_STATUS_MASK, 0xFFFF); - wm8350_reg_write(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK, 0xFFFF); - mutex_init(&wm8350->irq_mutex); + /* Mask all individual interrupts by default and cache the + * masks. We read the masks back since there are unwritable + * bits in the mask registers. */ + for (i = 0; i < ARRAY_SIZE(wm8350->irq_masks); i++) { + wm8350_reg_write(wm8350, WM8350_INT_STATUS_1_MASK + i, + 0xFFFF); + wm8350->irq_masks[i] = + wm8350_reg_read(wm8350, + WM8350_INT_STATUS_1_MASK + i); + } + + mutex_init(&wm8350->irq_lock); wm8350->chip_irq = irq; + wm8350->irq_base = pdata->irq_base; - if (pdata && pdata->irq_high) { + if (pdata->irq_high) { flags |= IRQF_TRIGGER_HIGH; wm8350_set_bits(wm8350, WM8350_SYSTEM_CONTROL_1, @@ -514,11 +512,32 @@ int wm8350_irq_init(struct wm8350 *wm8350, int irq, WM8350_IRQ_POL); } + /* Register with genirq */ + for (cur_irq = wm8350->irq_base; + cur_irq < ARRAY_SIZE(wm8350_irqs) + wm8350->irq_base; + cur_irq++) { + set_irq_chip_data(cur_irq, wm8350); + set_irq_chip_and_handler(cur_irq, &wm8350_irq_chip, + handle_edge_irq); + set_irq_nested_thread(cur_irq, 1); + + /* ARM needs us to explicitly flag the IRQ as valid + * and will set them noprobe when we do so. */ +#ifdef CONFIG_ARM + set_irq_flags(cur_irq, IRQF_VALID); +#else + set_irq_noprobe(cur_irq); +#endif + } + ret = request_threaded_irq(irq, NULL, wm8350_irq, flags, "wm8350", wm8350); if (ret != 0) dev_err(wm8350->dev, "Failed to request IRQ: %d\n", ret); + /* Allow interrupts to fire */ + wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0); + return ret; } diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h index 8883125ddea1..04217a71f173 100644 --- a/include/linux/mfd/wm8350/core.h +++ b/include/linux/mfd/wm8350/core.h @@ -579,6 +579,8 @@ #define WM8350_NUM_IRQ 63 +#define WM8350_NUM_IRQ_REGS 7 + struct wm8350_reg_access { u16 readable; /* Mask of readable bits */ u16 writable; /* Mask of writable bits */ @@ -600,11 +602,6 @@ extern const u16 wm8352_mode3_defaults[]; struct wm8350; -struct wm8350_irq { - irq_handler_t handler; - void *data; -}; - struct wm8350_hwmon { struct platform_device *pdev; struct device *classdev; @@ -626,9 +623,10 @@ struct wm8350 { struct mutex auxadc_mutex; /* Interrupt handling */ - struct mutex irq_mutex; /* IRQ table mutex */ - struct wm8350_irq irq[WM8350_NUM_IRQ]; + struct mutex irq_lock; int chip_irq; + int irq_base; + u16 irq_masks[WM8350_NUM_IRQ_REGS]; /* Client devices */ struct wm8350_codec codec; @@ -677,13 +675,33 @@ int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src); /* * WM8350 internal interrupts */ -int wm8350_register_irq(struct wm8350 *wm8350, int irq, - irq_handler_t handler, unsigned long flags, - const char *name, void *data); -int wm8350_free_irq(struct wm8350 *wm8350, int irq, void *data); +static inline int wm8350_register_irq(struct wm8350 *wm8350, int irq, + irq_handler_t handler, + unsigned long flags, + const char *name, void *data) +{ + if (!wm8350->irq_base) + return -ENODEV; + + return request_threaded_irq(irq + wm8350->irq_base, NULL, + handler, flags, name, data); +} + +static inline void wm8350_free_irq(struct wm8350 *wm8350, int irq, void *data) +{ + free_irq(irq + wm8350->irq_base, data); +} + +static inline void wm8350_mask_irq(struct wm8350 *wm8350, int irq) +{ + disable_irq(irq + wm8350->irq_base); +} + +static inline void wm8350_unmask_irq(struct wm8350 *wm8350, int irq) +{ + enable_irq(irq + wm8350->irq_base); +} -int wm8350_mask_irq(struct wm8350 *wm8350, int irq); -int wm8350_unmask_irq(struct wm8350 *wm8350, int irq); int wm8350_irq_init(struct wm8350 *wm8350, int irq, struct wm8350_platform_data *pdata); int wm8350_irq_exit(struct wm8350 *wm8350); -- cgit v1.2.3 From ecf926bcda5ba1da7269dcaa71a1b6920dc48349 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 5 Jan 2010 20:40:47 +0000 Subject: mfd: Don't allow WM8350 to be built modular The genirq implementation does not allow modules to implement irq_chips so the conversion of WM8350 to genirq means we can no longer allow the driver to be built as a module. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/mfd/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index b670d10d5c92..d957373d77e4 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -205,7 +205,7 @@ config MFD_WM831X functionality of the device. config MFD_WM8350 - tristate + bool config MFD_WM8350_CONFIG_MODE_0 bool @@ -256,9 +256,9 @@ config MFD_WM8352_CONFIG_MODE_3 depends on MFD_WM8350 config MFD_WM8350_I2C - tristate "Support Wolfson Microelectronics WM8350 with I2C" + bool "Support Wolfson Microelectronics WM8350 with I2C" select MFD_WM8350 - depends on I2C + depends on I2C=y help The WM8350 is an integrated audio and power management subsystem with watchdog and RTC functionality for embedded -- cgit v1.2.3 From 59f25070df0325067d7916b467ad15725657fedc Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 6 Jan 2010 19:24:25 +0000 Subject: mfd: Update WM8350 drivers for changed interrupt numbers The headphone detect and charger are using the IRQ numbers so need to take account of irq_base with the genirq conversion. I obviously picked the wrong system for initial testing. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/power/wm8350_power.c | 2 +- sound/soc/codecs/wm8350.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/power/wm8350_power.c b/drivers/power/wm8350_power.c index 3839a5e1c4a7..0693902d6151 100644 --- a/drivers/power/wm8350_power.c +++ b/drivers/power/wm8350_power.c @@ -190,7 +190,7 @@ static irqreturn_t wm8350_charger_handler(int irq, void *data) struct wm8350_power *power = &wm8350->power; struct wm8350_charger_policy *policy = power->policy; - switch (irq) { + switch (irq - wm8350->irq_base) { case WM8350_IRQ_CHG_BAT_FAIL: dev_err(wm8350->dev, "battery failed\n"); break; diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c index 079bf745bf05..df2c6d9617fb 100644 --- a/sound/soc/codecs/wm8350.c +++ b/sound/soc/codecs/wm8350.c @@ -1349,7 +1349,7 @@ static irqreturn_t wm8350_hp_jack_handler(int irq, void *data) int mask; struct wm8350_jack_data *jack = NULL; - switch (irq) { + switch (irq - wm8350->irq_base) { case WM8350_IRQ_CODEC_JCK_DET_L: jack = &priv->hpl; mask = WM8350_JACK_L_LVL; @@ -1424,7 +1424,7 @@ int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which, wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena); /* Sync status */ - wm8350_hp_jack_handler(irq, priv); + wm8350_hp_jack_handler(irq + wm8350->irq_base, priv); return 0; } -- cgit v1.2.3 From 38f6ce45f0bca04ac653c57cacd375c469995321 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 7 Jan 2010 16:10:08 +0000 Subject: gpiolib: Add support for WM8350 GPIO controller Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/wm8350-gpiolib.c | 181 ++++++++++++++++++++++++++++++++++++++++ include/linux/mfd/wm8350/core.h | 2 + include/linux/mfd/wm8350/gpio.h | 1 + 5 files changed, 192 insertions(+) create mode 100644 drivers/gpio/wm8350-gpiolib.c (limited to 'drivers') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index a4cdbd51b1c6..acac9f60db1d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -185,6 +185,13 @@ config GPIO_WM831X Say yes here to access the GPIO signals of WM831x power management chips from Wolfson Microelectronics. +config GPIO_WM8350 + tristate "WM8350 GPIOs" + depends on MFD_WM8350 + help + Say yes here to access the GPIO signals of WM8350 power management + chips from Wolfson Microelectronics. + config GPIO_ADP5520 tristate "GPIO Support for ADP5520 PMIC" depends on PMIC_ADP5520 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 128abf8a98da..90b0880923de 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -25,3 +25,4 @@ obj-$(CONFIG_GPIO_BT8XX) += bt8xxgpio.o obj-$(CONFIG_GPIO_IT8761E) += it8761e_gpio.o obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o obj-$(CONFIG_GPIO_WM831X) += wm831x-gpio.o +obj-$(CONFIG_GPIO_WM8350) += wm8350-gpiolib.o diff --git a/drivers/gpio/wm8350-gpiolib.c b/drivers/gpio/wm8350-gpiolib.c new file mode 100644 index 000000000000..511840d1c7ba --- /dev/null +++ b/drivers/gpio/wm8350-gpiolib.c @@ -0,0 +1,181 @@ +/* + * wm835x-gpiolib.c -- gpiolib support for Wolfson WM835x PMICs + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +struct wm8350_gpio_data { + struct wm8350 *wm8350; + struct gpio_chip gpio_chip; +}; + +static inline struct wm8350_gpio_data *to_wm8350_gpio(struct gpio_chip *chip) +{ + return container_of(chip, struct wm8350_gpio_data, gpio_chip); +} + +static int wm8350_gpio_direction_in(struct gpio_chip *chip, unsigned offset) +{ + struct wm8350_gpio_data *wm8350_gpio = to_wm8350_gpio(chip); + struct wm8350 *wm8350 = wm8350_gpio->wm8350; + + return wm8350_set_bits(wm8350, WM8350_GPIO_CONFIGURATION_I_O, + 1 << offset); +} + +static int wm8350_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct wm8350_gpio_data *wm8350_gpio = to_wm8350_gpio(chip); + struct wm8350 *wm8350 = wm8350_gpio->wm8350; + int ret; + + ret = wm8350_reg_read(wm8350, WM8350_GPIO_LEVEL); + if (ret < 0) + return ret; + + if (ret & (1 << offset)) + return 1; + else + return 0; +} + +static void wm8350_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct wm8350_gpio_data *wm8350_gpio = to_wm8350_gpio(chip); + struct wm8350 *wm8350 = wm8350_gpio->wm8350; + + if (value) + wm8350_set_bits(wm8350, WM8350_GPIO_LEVEL, 1 << offset); + else + wm8350_clear_bits(wm8350, WM8350_GPIO_LEVEL, 1 << offset); +} + +static int wm8350_gpio_direction_out(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct wm8350_gpio_data *wm8350_gpio = to_wm8350_gpio(chip); + struct wm8350 *wm8350 = wm8350_gpio->wm8350; + int ret; + + ret = wm8350_clear_bits(wm8350, WM8350_GPIO_CONFIGURATION_I_O, + 1 << offset); + if (ret < 0) + return ret; + + /* Don't have an atomic direction/value setup */ + wm8350_gpio_set(chip, offset, value); + + return 0; +} + +static int wm8350_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct wm8350_gpio_data *wm8350_gpio = to_wm8350_gpio(chip); + struct wm8350 *wm8350 = wm8350_gpio->wm8350; + + if (!wm8350->irq_base) + return -EINVAL; + + return wm8350->irq_base + WM8350_IRQ_GPIO(offset); +} + +static struct gpio_chip template_chip = { + .label = "wm8350", + .owner = THIS_MODULE, + .direction_input = wm8350_gpio_direction_in, + .get = wm8350_gpio_get, + .direction_output = wm8350_gpio_direction_out, + .set = wm8350_gpio_set, + .to_irq = wm8350_gpio_to_irq, + .can_sleep = 1, +}; + +static int __devinit wm8350_gpio_probe(struct platform_device *pdev) +{ + struct wm8350 *wm8350 = dev_get_drvdata(pdev->dev.parent); + struct wm8350_platform_data *pdata = wm8350->dev->platform_data; + struct wm8350_gpio_data *wm8350_gpio; + int ret; + + wm8350_gpio = kzalloc(sizeof(*wm8350_gpio), GFP_KERNEL); + if (wm8350_gpio == NULL) + return -ENOMEM; + + wm8350_gpio->wm8350 = wm8350; + wm8350_gpio->gpio_chip = template_chip; + wm8350_gpio->gpio_chip.ngpio = 13; + wm8350_gpio->gpio_chip.dev = &pdev->dev; + if (pdata && pdata->gpio_base) + wm8350_gpio->gpio_chip.base = pdata->gpio_base; + else + wm8350_gpio->gpio_chip.base = -1; + + ret = gpiochip_add(&wm8350_gpio->gpio_chip); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip, %d\n", + ret); + goto err; + } + + platform_set_drvdata(pdev, wm8350_gpio); + + return ret; + +err: + kfree(wm8350_gpio); + return ret; +} + +static int __devexit wm8350_gpio_remove(struct platform_device *pdev) +{ + struct wm8350_gpio_data *wm8350_gpio = platform_get_drvdata(pdev); + int ret; + + ret = gpiochip_remove(&wm8350_gpio->gpio_chip); + if (ret == 0) + kfree(wm8350_gpio); + + return ret; +} + +static struct platform_driver wm8350_gpio_driver = { + .driver.name = "wm8350-gpio", + .driver.owner = THIS_MODULE, + .probe = wm8350_gpio_probe, + .remove = __devexit_p(wm8350_gpio_remove), +}; + +static int __init wm8350_gpio_init(void) +{ + return platform_driver_register(&wm8350_gpio_driver); +} +subsys_initcall(wm8350_gpio_init); + +static void __exit wm8350_gpio_exit(void) +{ + platform_driver_unregister(&wm8350_gpio_driver); +} +module_exit(wm8350_gpio_exit); + +MODULE_AUTHOR("Mark Brown "); +MODULE_DESCRIPTION("GPIO interface for WM8350 PMICs"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:wm8350-gpio"); diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h index 04217a71f173..fae08aa65413 100644 --- a/include/linux/mfd/wm8350/core.h +++ b/include/linux/mfd/wm8350/core.h @@ -645,11 +645,13 @@ struct wm8350 { * used by the platform to configure GPIO functions and similar. * @irq_high: Set if WM8350 IRQ is active high. * @irq_base: Base IRQ for genirq (not currently used). + * @gpio_base: Base for gpiolib. */ struct wm8350_platform_data { int (*init)(struct wm8350 *wm8350); int irq_high; int irq_base; + int gpio_base; }; diff --git a/include/linux/mfd/wm8350/gpio.h b/include/linux/mfd/wm8350/gpio.h index 71af3d6ebe9d..d657bcd6d955 100644 --- a/include/linux/mfd/wm8350/gpio.h +++ b/include/linux/mfd/wm8350/gpio.h @@ -29,6 +29,7 @@ #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E #define WM8350_GPIO_FUNCTION_SELECT_4 0x8F +#define WM8350_GPIO_LEVEL 0xE6 /* * GPIO Functions -- cgit v1.2.3 From 0df883df8e8aea79b501f6262b595e66dec175dc Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 8 Jan 2010 10:44:16 +0100 Subject: mfd: Convert AB3100 driver to threaded IRQ This converts the AB3100 core MFD driver to use a threaded interrupt handler instead of the explicit top/bottom-half construction with a workqueue. This saves some code and make it more similar to other modern MFD drivers. Signed-off-by: Linus Walleij Signed-off-by: Samuel Ortiz --- drivers/mfd/ab3100-core.c | 43 +++++++++++++------------------------------ include/linux/mfd/ab3100.h | 3 --- 2 files changed, 13 insertions(+), 33 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/ab3100-core.c b/drivers/mfd/ab3100-core.c index fd42a80e7bf9..aa3824a1b4f2 100644 --- a/drivers/mfd/ab3100-core.c +++ b/drivers/mfd/ab3100-core.c @@ -365,10 +365,13 @@ int ab3100_event_registers_startup_state_get(struct ab3100 *ab3100, } EXPORT_SYMBOL(ab3100_event_registers_startup_state_get); -/* Interrupt handling worker */ -static void ab3100_work(struct work_struct *work) +/* + * This is a threaded interrupt handler so we can make some + * I2C calls etc. + */ +static irqreturn_t ab3100_irq_handler(int irq, void *data) { - struct ab3100 *ab3100 = container_of(work, struct ab3100, work); + struct ab3100 *ab3100 = data; u8 event_regs[3]; u32 fatevent; int err; @@ -376,7 +379,7 @@ static void ab3100_work(struct work_struct *work) err = ab3100_get_register_page_interruptible(ab3100, AB3100_EVENTA1, event_regs, 3); if (err) - goto err_event_wq; + goto err_event; fatevent = (event_regs[0] << 16) | (event_regs[1] << 8) | @@ -398,29 +401,11 @@ static void ab3100_work(struct work_struct *work) dev_dbg(ab3100->dev, "IRQ Event: 0x%08x\n", fatevent); - /* By now the IRQ should be acked and deasserted so enable it again */ - enable_irq(ab3100->i2c_client->irq); - return; + return IRQ_HANDLED; - err_event_wq: + err_event: dev_dbg(ab3100->dev, - "error in event workqueue\n"); - /* Enable the IRQ anyway, what choice do we have? */ - enable_irq(ab3100->i2c_client->irq); - return; -} - -static irqreturn_t ab3100_irq_handler(int irq, void *data) -{ - struct ab3100 *ab3100 = data; - /* - * Disable the IRQ and dispatch a worker to handle the - * event. Since the chip resides on I2C this is slow - * stuff and we will re-enable the interrupts once th - * worker has finished. - */ - disable_irq_nosync(irq); - schedule_work(&ab3100->work); + "error reading event status\n"); return IRQ_HANDLED; } @@ -904,12 +889,10 @@ static int __init ab3100_probe(struct i2c_client *client, if (err) goto exit_no_setup; - INIT_WORK(&ab3100->work, ab3100_work); - /* This real unpredictable IRQ is of course sampled for entropy */ - err = request_irq(client->irq, ab3100_irq_handler, - IRQF_DISABLED | IRQF_SAMPLE_RANDOM, - "AB3100 IRQ", ab3100); + err = request_threaded_irq(client->irq, NULL, ab3100_irq_handler, + IRQF_ONESHOT, + "ab3100-core", ab3100); if (err) goto exit_no_irq; diff --git a/include/linux/mfd/ab3100.h b/include/linux/mfd/ab3100.h index e9aa4c9d749d..9a881c305a50 100644 --- a/include/linux/mfd/ab3100.h +++ b/include/linux/mfd/ab3100.h @@ -6,7 +6,6 @@ */ #include -#include #include #ifndef MFD_AB3100_H @@ -74,7 +73,6 @@ * @testreg_client: secondary client for test registers * @chip_name: name of this chip variant * @chip_id: 8 bit chip ID for this chip variant - * @work: an event handling worker * @event_subscribers: event subscribers are listed here * @startup_events: a copy of the first reading of the event registers * @startup_events_read: whether the first events have been read @@ -90,7 +88,6 @@ struct ab3100 { struct i2c_client *testreg_client; char chip_name[32]; u8 chip_id; - struct work_struct work; struct blocking_notifier_head event_subscribers; u32 startup_events; bool startup_events_read; -- cgit v1.2.3 From bbd51b1ff1bf57b9ed7f062486a415509968d4d9 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 6 Jan 2010 17:04:18 -0500 Subject: mfd: Split 88pm8607 driver Create 88pm8607-i2c driver to support all I2C operation of 88PM8607. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/mfd/88pm8607.c | 302 ------------------------------------------- drivers/mfd/88pm860x-core.c | 134 +++++++++++++++++++ drivers/mfd/88pm860x-i2c.c | 202 +++++++++++++++++++++++++++++ drivers/mfd/Makefile | 2 +- include/linux/mfd/88pm8607.h | 12 +- 5 files changed, 346 insertions(+), 306 deletions(-) delete mode 100644 drivers/mfd/88pm8607.c create mode 100644 drivers/mfd/88pm860x-core.c create mode 100644 drivers/mfd/88pm860x-i2c.c (limited to 'drivers') diff --git a/drivers/mfd/88pm8607.c b/drivers/mfd/88pm8607.c deleted file mode 100644 index 7e3f65907993..000000000000 --- a/drivers/mfd/88pm8607.c +++ /dev/null @@ -1,302 +0,0 @@ -/* - * Base driver for Marvell 88PM8607 - * - * Copyright (C) 2009 Marvell International Ltd. - * Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include - - -#define PM8607_REG_RESOURCE(_start, _end) \ -{ \ - .start = PM8607_##_start, \ - .end = PM8607_##_end, \ - .flags = IORESOURCE_IO, \ -} - -static struct resource pm8607_regulator_resources[] = { - PM8607_REG_RESOURCE(BUCK1, BUCK1), - PM8607_REG_RESOURCE(BUCK2, BUCK2), - PM8607_REG_RESOURCE(BUCK3, BUCK3), - PM8607_REG_RESOURCE(LDO1, LDO1), - PM8607_REG_RESOURCE(LDO2, LDO2), - PM8607_REG_RESOURCE(LDO3, LDO3), - PM8607_REG_RESOURCE(LDO4, LDO4), - PM8607_REG_RESOURCE(LDO5, LDO5), - PM8607_REG_RESOURCE(LDO6, LDO6), - PM8607_REG_RESOURCE(LDO7, LDO7), - PM8607_REG_RESOURCE(LDO8, LDO8), - PM8607_REG_RESOURCE(LDO9, LDO9), - PM8607_REG_RESOURCE(LDO10, LDO10), - PM8607_REG_RESOURCE(LDO12, LDO12), - PM8607_REG_RESOURCE(LDO14, LDO14), -}; - -#define PM8607_REG_DEVS(_name, _id) \ -{ \ - .name = "88pm8607-" #_name, \ - .num_resources = 1, \ - .resources = &pm8607_regulator_resources[PM8607_ID_##_id], \ -} - -static struct mfd_cell pm8607_devs[] = { - PM8607_REG_DEVS(buck1, BUCK1), - PM8607_REG_DEVS(buck2, BUCK2), - PM8607_REG_DEVS(buck3, BUCK3), - PM8607_REG_DEVS(ldo1, LDO1), - PM8607_REG_DEVS(ldo2, LDO2), - PM8607_REG_DEVS(ldo3, LDO3), - PM8607_REG_DEVS(ldo4, LDO4), - PM8607_REG_DEVS(ldo5, LDO5), - PM8607_REG_DEVS(ldo6, LDO6), - PM8607_REG_DEVS(ldo7, LDO7), - PM8607_REG_DEVS(ldo8, LDO8), - PM8607_REG_DEVS(ldo9, LDO9), - PM8607_REG_DEVS(ldo10, LDO10), - PM8607_REG_DEVS(ldo12, LDO12), - PM8607_REG_DEVS(ldo14, LDO14), -}; - -static inline int pm8607_read_device(struct pm8607_chip *chip, - int reg, int bytes, void *dest) -{ - struct i2c_client *i2c = chip->client; - unsigned char data; - int ret; - - data = (unsigned char)reg; - ret = i2c_master_send(i2c, &data, 1); - if (ret < 0) - return ret; - - ret = i2c_master_recv(i2c, dest, bytes); - if (ret < 0) - return ret; - return 0; -} - -static inline int pm8607_write_device(struct pm8607_chip *chip, - int reg, int bytes, void *src) -{ - struct i2c_client *i2c = chip->client; - unsigned char buf[bytes + 1]; - int ret; - - buf[0] = (unsigned char)reg; - memcpy(&buf[1], src, bytes); - - ret = i2c_master_send(i2c, buf, bytes + 1); - if (ret < 0) - return ret; - return 0; -} - -int pm8607_reg_read(struct pm8607_chip *chip, int reg) -{ - unsigned char data; - int ret; - - mutex_lock(&chip->io_lock); - ret = chip->read(chip, reg, 1, &data); - mutex_unlock(&chip->io_lock); - - if (ret < 0) - return ret; - else - return (int)data; -} -EXPORT_SYMBOL(pm8607_reg_read); - -int pm8607_reg_write(struct pm8607_chip *chip, int reg, - unsigned char data) -{ - int ret; - - mutex_lock(&chip->io_lock); - ret = chip->write(chip, reg, 1, &data); - mutex_unlock(&chip->io_lock); - - return ret; -} -EXPORT_SYMBOL(pm8607_reg_write); - -int pm8607_bulk_read(struct pm8607_chip *chip, int reg, - int count, unsigned char *buf) -{ - int ret; - - mutex_lock(&chip->io_lock); - ret = chip->read(chip, reg, count, buf); - mutex_unlock(&chip->io_lock); - - return ret; -} -EXPORT_SYMBOL(pm8607_bulk_read); - -int pm8607_bulk_write(struct pm8607_chip *chip, int reg, - int count, unsigned char *buf) -{ - int ret; - - mutex_lock(&chip->io_lock); - ret = chip->write(chip, reg, count, buf); - mutex_unlock(&chip->io_lock); - - return ret; -} -EXPORT_SYMBOL(pm8607_bulk_write); - -int pm8607_set_bits(struct pm8607_chip *chip, int reg, - unsigned char mask, unsigned char data) -{ - unsigned char value; - int ret; - - mutex_lock(&chip->io_lock); - ret = chip->read(chip, reg, 1, &value); - if (ret < 0) - goto out; - value &= ~mask; - value |= data; - ret = chip->write(chip, reg, 1, &value); -out: - mutex_unlock(&chip->io_lock); - return ret; -} -EXPORT_SYMBOL(pm8607_set_bits); - - -static const struct i2c_device_id pm8607_id_table[] = { - { "88PM8607", 0 }, - {} -}; -MODULE_DEVICE_TABLE(i2c, pm8607_id_table); - - -static int __devinit pm8607_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct pm8607_platform_data *pdata = client->dev.platform_data; - struct pm8607_chip *chip; - int i, count; - int ret; - - chip = kzalloc(sizeof(struct pm8607_chip), GFP_KERNEL); - if (chip == NULL) - return -ENOMEM; - - chip->client = client; - chip->dev = &client->dev; - chip->read = pm8607_read_device; - chip->write = pm8607_write_device; - i2c_set_clientdata(client, chip); - - mutex_init(&chip->io_lock); - dev_set_drvdata(chip->dev, chip); - - ret = pm8607_reg_read(chip, PM8607_CHIP_ID); - if (ret < 0) { - dev_err(chip->dev, "Failed to read CHIP ID: %d\n", ret); - goto out; - } - if ((ret & CHIP_ID_MASK) == CHIP_ID) - dev_info(chip->dev, "Marvell 88PM8607 (ID: %02x) detected\n", - ret); - else { - dev_err(chip->dev, "Failed to detect Marvell 88PM8607. " - "Chip ID: %02x\n", ret); - goto out; - } - chip->chip_id = ret; - - ret = pm8607_reg_read(chip, PM8607_BUCK3); - if (ret < 0) { - dev_err(chip->dev, "Failed to read BUCK3 register: %d\n", ret); - goto out; - } - if (ret & PM8607_BUCK3_DOUBLE) - chip->buck3_double = 1; - - ret = pm8607_reg_read(chip, PM8607_MISC1); - if (ret < 0) { - dev_err(chip->dev, "Failed to read MISC1 register: %d\n", ret); - goto out; - } - if (pdata->i2c_port == PI2C_PORT) - ret |= PM8607_MISC1_PI2C; - else - ret &= ~PM8607_MISC1_PI2C; - ret = pm8607_reg_write(chip, PM8607_MISC1, ret); - if (ret < 0) { - dev_err(chip->dev, "Failed to write MISC1 register: %d\n", ret); - goto out; - } - - - count = ARRAY_SIZE(pm8607_devs); - for (i = 0; i < count; i++) { - ret = mfd_add_devices(chip->dev, i, &pm8607_devs[i], - 1, NULL, 0); - if (ret != 0) { - dev_err(chip->dev, "Failed to add subdevs\n"); - goto out; - } - } - - return 0; - -out: - i2c_set_clientdata(client, NULL); - kfree(chip); - return ret; -} - -static int __devexit pm8607_remove(struct i2c_client *client) -{ - struct pm8607_chip *chip = i2c_get_clientdata(client); - - mfd_remove_devices(chip->dev); - kfree(chip); - return 0; -} - -static struct i2c_driver pm8607_driver = { - .driver = { - .name = "88PM8607", - .owner = THIS_MODULE, - }, - .probe = pm8607_probe, - .remove = __devexit_p(pm8607_remove), - .id_table = pm8607_id_table, -}; - -static int __init pm8607_init(void) -{ - int ret; - ret = i2c_add_driver(&pm8607_driver); - if (ret != 0) - pr_err("Failed to register 88PM8607 I2C driver: %d\n", ret); - return ret; -} -subsys_initcall(pm8607_init); - -static void __exit pm8607_exit(void) -{ - i2c_del_driver(&pm8607_driver); -} -module_exit(pm8607_exit); - -MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM8607"); -MODULE_AUTHOR("Haojian Zhuang "); -MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c new file mode 100644 index 000000000000..d1464e54e656 --- /dev/null +++ b/drivers/mfd/88pm860x-core.c @@ -0,0 +1,134 @@ +/* + * Base driver for Marvell 88PM8607 + * + * Copyright (C) 2009 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + + +#define PM8607_REG_RESOURCE(_start, _end) \ +{ \ + .start = PM8607_##_start, \ + .end = PM8607_##_end, \ + .flags = IORESOURCE_IO, \ +} + +static struct resource pm8607_regulator_resources[] = { + PM8607_REG_RESOURCE(BUCK1, BUCK1), + PM8607_REG_RESOURCE(BUCK2, BUCK2), + PM8607_REG_RESOURCE(BUCK3, BUCK3), + PM8607_REG_RESOURCE(LDO1, LDO1), + PM8607_REG_RESOURCE(LDO2, LDO2), + PM8607_REG_RESOURCE(LDO3, LDO3), + PM8607_REG_RESOURCE(LDO4, LDO4), + PM8607_REG_RESOURCE(LDO5, LDO5), + PM8607_REG_RESOURCE(LDO6, LDO6), + PM8607_REG_RESOURCE(LDO7, LDO7), + PM8607_REG_RESOURCE(LDO8, LDO8), + PM8607_REG_RESOURCE(LDO9, LDO9), + PM8607_REG_RESOURCE(LDO10, LDO10), + PM8607_REG_RESOURCE(LDO12, LDO12), + PM8607_REG_RESOURCE(LDO14, LDO14), +}; + +#define PM8607_REG_DEVS(_name, _id) \ +{ \ + .name = "88pm8607-" #_name, \ + .num_resources = 1, \ + .resources = &pm8607_regulator_resources[PM8607_ID_##_id], \ +} + +static struct mfd_cell pm8607_devs[] = { + PM8607_REG_DEVS(buck1, BUCK1), + PM8607_REG_DEVS(buck2, BUCK2), + PM8607_REG_DEVS(buck3, BUCK3), + PM8607_REG_DEVS(ldo1, LDO1), + PM8607_REG_DEVS(ldo2, LDO2), + PM8607_REG_DEVS(ldo3, LDO3), + PM8607_REG_DEVS(ldo4, LDO4), + PM8607_REG_DEVS(ldo5, LDO5), + PM8607_REG_DEVS(ldo6, LDO6), + PM8607_REG_DEVS(ldo7, LDO7), + PM8607_REG_DEVS(ldo8, LDO8), + PM8607_REG_DEVS(ldo9, LDO9), + PM8607_REG_DEVS(ldo10, LDO10), + PM8607_REG_DEVS(ldo12, LDO12), + PM8607_REG_DEVS(ldo14, LDO14), +}; + +int pm860x_device_init(struct pm8607_chip *chip, + struct pm8607_platform_data *pdata) +{ + int i, count; + int ret; + + ret = pm8607_reg_read(chip, PM8607_CHIP_ID); + if (ret < 0) { + dev_err(chip->dev, "Failed to read CHIP ID: %d\n", ret); + goto out; + } + if ((ret & PM8607_ID_MASK) == PM8607_ID) + dev_info(chip->dev, "Marvell 88PM8607 (ID: %02x) detected\n", + ret); + else { + dev_err(chip->dev, "Failed to detect Marvell 88PM8607. " + "Chip ID: %02x\n", ret); + goto out; + } + chip->chip_id = ret; + + ret = pm8607_reg_read(chip, PM8607_BUCK3); + if (ret < 0) { + dev_err(chip->dev, "Failed to read BUCK3 register: %d\n", ret); + goto out; + } + if (ret & PM8607_BUCK3_DOUBLE) + chip->buck3_double = 1; + + ret = pm8607_reg_read(chip, PM8607_MISC1); + if (ret < 0) { + dev_err(chip->dev, "Failed to read MISC1 register: %d\n", ret); + goto out; + } + if (pdata->i2c_port == PI2C_PORT) + ret |= PM8607_MISC1_PI2C; + else + ret &= ~PM8607_MISC1_PI2C; + ret = pm8607_reg_write(chip, PM8607_MISC1, ret); + if (ret < 0) { + dev_err(chip->dev, "Failed to write MISC1 register: %d\n", ret); + goto out; + } + + count = ARRAY_SIZE(pm8607_devs); + for (i = 0; i < count; i++) { + ret = mfd_add_devices(chip->dev, i, &pm8607_devs[i], + 1, NULL, 0); + if (ret != 0) { + dev_err(chip->dev, "Failed to add subdevs\n"); + goto out; + } + } +out: + return ret; +} + +void pm8607_device_exit(struct pm8607_chip *chip) +{ + mfd_remove_devices(chip->dev); +} + +MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM8607"); +MODULE_AUTHOR("Haojian Zhuang "); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/88pm860x-i2c.c b/drivers/mfd/88pm860x-i2c.c new file mode 100644 index 000000000000..dda23cbfe415 --- /dev/null +++ b/drivers/mfd/88pm860x-i2c.c @@ -0,0 +1,202 @@ +/* + * I2C driver for Marvell 88PM8607 + * + * Copyright (C) 2009 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include + +static inline int pm8607_read_device(struct pm8607_chip *chip, + int reg, int bytes, void *dest) +{ + struct i2c_client *i2c = chip->client; + unsigned char data; + int ret; + + data = (unsigned char)reg; + ret = i2c_master_send(i2c, &data, 1); + if (ret < 0) + return ret; + + ret = i2c_master_recv(i2c, dest, bytes); + if (ret < 0) + return ret; + return 0; +} + +static inline int pm8607_write_device(struct pm8607_chip *chip, + int reg, int bytes, void *src) +{ + struct i2c_client *i2c = chip->client; + unsigned char buf[bytes + 1]; + int ret; + + buf[0] = (unsigned char)reg; + memcpy(&buf[1], src, bytes); + + ret = i2c_master_send(i2c, buf, bytes + 1); + if (ret < 0) + return ret; + return 0; +} + +int pm8607_reg_read(struct pm8607_chip *chip, int reg) +{ + unsigned char data; + int ret; + + mutex_lock(&chip->io_lock); + ret = chip->read(chip, reg, 1, &data); + mutex_unlock(&chip->io_lock); + + if (ret < 0) + return ret; + else + return (int)data; +} +EXPORT_SYMBOL(pm8607_reg_read); + +int pm8607_reg_write(struct pm8607_chip *chip, int reg, + unsigned char data) +{ + int ret; + + mutex_lock(&chip->io_lock); + ret = chip->write(chip, reg, 1, &data); + mutex_unlock(&chip->io_lock); + + return ret; +} +EXPORT_SYMBOL(pm8607_reg_write); + +int pm8607_bulk_read(struct pm8607_chip *chip, int reg, + int count, unsigned char *buf) +{ + int ret; + + mutex_lock(&chip->io_lock); + ret = chip->read(chip, reg, count, buf); + mutex_unlock(&chip->io_lock); + + return ret; +} +EXPORT_SYMBOL(pm8607_bulk_read); + +int pm8607_bulk_write(struct pm8607_chip *chip, int reg, + int count, unsigned char *buf) +{ + int ret; + + mutex_lock(&chip->io_lock); + ret = chip->write(chip, reg, count, buf); + mutex_unlock(&chip->io_lock); + + return ret; +} +EXPORT_SYMBOL(pm8607_bulk_write); + +int pm8607_set_bits(struct pm8607_chip *chip, int reg, + unsigned char mask, unsigned char data) +{ + unsigned char value; + int ret; + + mutex_lock(&chip->io_lock); + ret = chip->read(chip, reg, 1, &value); + if (ret < 0) + goto out; + value &= ~mask; + value |= data; + ret = chip->write(chip, reg, 1, &value); +out: + mutex_unlock(&chip->io_lock); + return ret; +} +EXPORT_SYMBOL(pm8607_set_bits); + + +static const struct i2c_device_id pm860x_id_table[] = { + { "88PM8607", 0 }, + {} +}; +MODULE_DEVICE_TABLE(i2c, pm860x_id_table); + +static int __devinit pm860x_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct pm8607_platform_data *pdata = client->dev.platform_data; + struct pm8607_chip *chip; + int ret; + + chip = kzalloc(sizeof(struct pm8607_chip), GFP_KERNEL); + if (chip == NULL) + return -ENOMEM; + + chip->client = client; + chip->dev = &client->dev; + chip->read = pm8607_read_device; + chip->write = pm8607_write_device; + memcpy(&chip->id, id, sizeof(struct i2c_device_id)); + i2c_set_clientdata(client, chip); + + mutex_init(&chip->io_lock); + dev_set_drvdata(chip->dev, chip); + + ret = pm860x_device_init(chip, pdata); + if (ret < 0) + goto out; + + + return 0; + +out: + i2c_set_clientdata(client, NULL); + kfree(chip); + return ret; +} + +static int __devexit pm860x_remove(struct i2c_client *client) +{ + struct pm8607_chip *chip = i2c_get_clientdata(client); + + kfree(chip); + return 0; +} + +static struct i2c_driver pm860x_driver = { + .driver = { + .name = "88PM860x", + .owner = THIS_MODULE, + }, + .probe = pm860x_probe, + .remove = __devexit_p(pm860x_remove), + .id_table = pm860x_id_table, +}; + +static int __init pm860x_i2c_init(void) +{ + int ret; + ret = i2c_add_driver(&pm860x_driver); + if (ret != 0) + pr_err("Failed to register 88PM860x I2C driver: %d\n", ret); + return ret; +} +subsys_initcall(pm860x_i2c_init); + +static void __exit pm860x_i2c_exit(void) +{ + i2c_del_driver(&pm860x_driver); +} +module_exit(pm860x_i2c_exit); + +MODULE_DESCRIPTION("I2C Driver for Marvell 88PM860x"); +MODULE_AUTHOR("Haojian Zhuang "); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 78295d6a75f7..88fa200188cf 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -2,6 +2,7 @@ # Makefile for multifunction miscellaneous devices # +obj-$(CONFIG_MFD_88PM8607) += 88pm860x-core.o 88pm860x-i2c.o obj-$(CONFIG_MFD_SM501) += sm501.o obj-$(CONFIG_MFD_ASIC3) += asic3.o tmio_core.o obj-$(CONFIG_MFD_SH_MOBILE_SDHI) += sh_mobile_sdhi.o @@ -55,5 +56,4 @@ obj-$(CONFIG_AB3100_CORE) += ab3100-core.o obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o obj-$(CONFIG_AB4500_CORE) += ab4500-core.o obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o -obj-$(CONFIG_MFD_88PM8607) += 88pm8607.o obj-$(CONFIG_PMIC_ADP5520) += adp5520.o diff --git a/include/linux/mfd/88pm8607.h b/include/linux/mfd/88pm8607.h index f41b428d2cec..6e4dcdca02a8 100644 --- a/include/linux/mfd/88pm8607.h +++ b/include/linux/mfd/88pm8607.h @@ -33,8 +33,8 @@ enum { PM8607_ID_RG_MAX, }; -#define CHIP_ID (0x40) -#define CHIP_ID_MASK (0xF8) +#define PM8607_ID (0x40) /* 8607 chip ID */ +#define PM8607_ID_MASK (0xF8) /* 8607 chip ID mask */ /* Interrupt Registers */ #define PM8607_STATUS_1 (0x01) @@ -185,6 +185,7 @@ struct pm8607_chip { struct device *dev; struct mutex io_lock; struct i2c_client *client; + struct i2c_device_id id; int (*read)(struct pm8607_chip *chip, int reg, int bytes, void *dest); int (*write)(struct pm8607_chip *chip, int reg, int bytes, void *src); @@ -214,4 +215,9 @@ extern int pm8607_bulk_write(struct pm8607_chip *, int, int, unsigned char *); extern int pm8607_set_bits(struct pm8607_chip *, int, unsigned char, unsigned char); -#endif /* __LINUX_MFD_88PM8607_H */ + +extern int pm860x_device_init(struct pm8607_chip *chip, + struct pm8607_platform_data *pdata); +extern void pm860x_device_exit(struct pm8607_chip *chip); + +#endif /* __LINUX_MFD_88PM860X_H */ -- cgit v1.2.3 From 53dbab7af9ca13fa95605e9a5c31bb803dcba363 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 8 Jan 2010 06:01:24 -0500 Subject: mfd: Support 88pm8606 in 860x driver 88PM8606 and 88PM8607 are two discrete chips used for power management. Hardware designer can use them together or only one of them according to requirement. There's some logic tightly linked between these two chips. For example, USB charger driver needs to access both chips by I2C interface. Now share one driver to these two devices. Only one I2C client is identified in platform init data. If another chip is also used, user should mark it in companion_addr field of platform init data. Then driver could create another I2C client for the companion chip. All I2C operations are accessed by 860x-i2c driver. In order to support both I2C client address, the read/write API is changed in below. reg_read(client, offset) reg_write(client, offset, data) The benefit is that client drivers only need one kind of read/write API. I2C and MFD driver can be shared in both 8606 and 8607. Since API is changed, update API in 8607 regulator driver. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/mfd/88pm860x-core.c | 61 ++++++++---- drivers/mfd/88pm860x-i2c.c | 172 ++++++++++++++++++++++---------- drivers/regulator/88pm8607.c | 32 +++--- include/linux/mfd/88pm8607.h | 223 ------------------------------------------ include/linux/mfd/88pm860x.h | 227 +++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 402 insertions(+), 313 deletions(-) delete mode 100644 include/linux/mfd/88pm8607.h create mode 100644 include/linux/mfd/88pm860x.h (limited to 'drivers') diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c index d1464e54e656..72b00304dc3a 100644 --- a/drivers/mfd/88pm860x-core.c +++ b/drivers/mfd/88pm860x-core.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #define PM8607_REG_RESOURCE(_start, _end) \ @@ -67,18 +67,23 @@ static struct mfd_cell pm8607_devs[] = { PM8607_REG_DEVS(ldo14, LDO14), }; -int pm860x_device_init(struct pm8607_chip *chip, - struct pm8607_platform_data *pdata) +static void device_8606_init(struct pm860x_chip *chip, struct i2c_client *i2c, + struct pm860x_platform_data *pdata) +{ +} + +static void device_8607_init(struct pm860x_chip *chip, struct i2c_client *i2c, + struct pm860x_platform_data *pdata) { int i, count; int ret; - ret = pm8607_reg_read(chip, PM8607_CHIP_ID); + ret = pm860x_reg_read(i2c, PM8607_CHIP_ID); if (ret < 0) { dev_err(chip->dev, "Failed to read CHIP ID: %d\n", ret); goto out; } - if ((ret & PM8607_ID_MASK) == PM8607_ID) + if ((ret & PM8607_VERSION_MASK) == PM8607_VERSION) dev_info(chip->dev, "Marvell 88PM8607 (ID: %02x) detected\n", ret); else { @@ -86,9 +91,9 @@ int pm860x_device_init(struct pm8607_chip *chip, "Chip ID: %02x\n", ret); goto out; } - chip->chip_id = ret; + chip->chip_version = ret; - ret = pm8607_reg_read(chip, PM8607_BUCK3); + ret = pm860x_reg_read(i2c, PM8607_BUCK3); if (ret < 0) { dev_err(chip->dev, "Failed to read BUCK3 register: %d\n", ret); goto out; @@ -96,20 +101,11 @@ int pm860x_device_init(struct pm8607_chip *chip, if (ret & PM8607_BUCK3_DOUBLE) chip->buck3_double = 1; - ret = pm8607_reg_read(chip, PM8607_MISC1); + ret = pm860x_reg_read(i2c, PM8607_MISC1); if (ret < 0) { dev_err(chip->dev, "Failed to read MISC1 register: %d\n", ret); goto out; } - if (pdata->i2c_port == PI2C_PORT) - ret |= PM8607_MISC1_PI2C; - else - ret &= ~PM8607_MISC1_PI2C; - ret = pm8607_reg_write(chip, PM8607_MISC1, ret); - if (ret < 0) { - dev_err(chip->dev, "Failed to write MISC1 register: %d\n", ret); - goto out; - } count = ARRAY_SIZE(pm8607_devs); for (i = 0; i < count; i++) { @@ -121,14 +117,39 @@ int pm860x_device_init(struct pm8607_chip *chip, } } out: - return ret; + return; +} + +int pm860x_device_init(struct pm860x_chip *chip, + struct pm860x_platform_data *pdata) +{ + switch (chip->id) { + case CHIP_PM8606: + device_8606_init(chip, chip->client, pdata); + break; + case CHIP_PM8607: + device_8607_init(chip, chip->client, pdata); + break; + } + + if (chip->companion) { + switch (chip->id) { + case CHIP_PM8607: + device_8606_init(chip, chip->companion, pdata); + break; + case CHIP_PM8606: + device_8607_init(chip, chip->companion, pdata); + break; + } + } + return 0; } -void pm8607_device_exit(struct pm8607_chip *chip) +void pm860x_device_exit(struct pm860x_chip *chip) { mfd_remove_devices(chip->dev); } -MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM8607"); +MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM860x"); MODULE_AUTHOR("Haojian Zhuang "); MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/88pm860x-i2c.c b/drivers/mfd/88pm860x-i2c.c index dda23cbfe415..6d7dba2bce8a 100644 --- a/drivers/mfd/88pm860x-i2c.c +++ b/drivers/mfd/88pm860x-i2c.c @@ -1,5 +1,5 @@ /* - * I2C driver for Marvell 88PM8607 + * I2C driver for Marvell 88PM860x * * Copyright (C) 2009 Marvell International Ltd. * Haojian Zhuang @@ -12,12 +12,11 @@ #include #include #include -#include +#include -static inline int pm8607_read_device(struct pm8607_chip *chip, +static inline int pm860x_read_device(struct i2c_client *i2c, int reg, int bytes, void *dest) { - struct i2c_client *i2c = chip->client; unsigned char data; int ret; @@ -32,10 +31,9 @@ static inline int pm8607_read_device(struct pm8607_chip *chip, return 0; } -static inline int pm8607_write_device(struct pm8607_chip *chip, +static inline int pm860x_write_device(struct i2c_client *i2c, int reg, int bytes, void *src) { - struct i2c_client *i2c = chip->client; unsigned char buf[bytes + 1]; int ret; @@ -48,13 +46,14 @@ static inline int pm8607_write_device(struct pm8607_chip *chip, return 0; } -int pm8607_reg_read(struct pm8607_chip *chip, int reg) +int pm860x_reg_read(struct i2c_client *i2c, int reg) { + struct pm860x_chip *chip = i2c_get_clientdata(i2c); unsigned char data; int ret; mutex_lock(&chip->io_lock); - ret = chip->read(chip, reg, 1, &data); + ret = pm860x_read_device(i2c, reg, 1, &data); mutex_unlock(&chip->io_lock); if (ret < 0) @@ -62,111 +61,178 @@ int pm8607_reg_read(struct pm8607_chip *chip, int reg) else return (int)data; } -EXPORT_SYMBOL(pm8607_reg_read); +EXPORT_SYMBOL(pm860x_reg_read); -int pm8607_reg_write(struct pm8607_chip *chip, int reg, +int pm860x_reg_write(struct i2c_client *i2c, int reg, unsigned char data) { + struct pm860x_chip *chip = i2c_get_clientdata(i2c); int ret; mutex_lock(&chip->io_lock); - ret = chip->write(chip, reg, 1, &data); + ret = pm860x_write_device(i2c, reg, 1, &data); mutex_unlock(&chip->io_lock); return ret; } -EXPORT_SYMBOL(pm8607_reg_write); +EXPORT_SYMBOL(pm860x_reg_write); -int pm8607_bulk_read(struct pm8607_chip *chip, int reg, +int pm860x_bulk_read(struct i2c_client *i2c, int reg, int count, unsigned char *buf) { + struct pm860x_chip *chip = i2c_get_clientdata(i2c); int ret; mutex_lock(&chip->io_lock); - ret = chip->read(chip, reg, count, buf); + ret = pm860x_read_device(i2c, reg, count, buf); mutex_unlock(&chip->io_lock); return ret; } -EXPORT_SYMBOL(pm8607_bulk_read); +EXPORT_SYMBOL(pm860x_bulk_read); -int pm8607_bulk_write(struct pm8607_chip *chip, int reg, +int pm860x_bulk_write(struct i2c_client *i2c, int reg, int count, unsigned char *buf) { + struct pm860x_chip *chip = i2c_get_clientdata(i2c); int ret; mutex_lock(&chip->io_lock); - ret = chip->write(chip, reg, count, buf); + ret = pm860x_write_device(i2c, reg, count, buf); mutex_unlock(&chip->io_lock); return ret; } -EXPORT_SYMBOL(pm8607_bulk_write); +EXPORT_SYMBOL(pm860x_bulk_write); -int pm8607_set_bits(struct pm8607_chip *chip, int reg, +int pm860x_set_bits(struct i2c_client *i2c, int reg, unsigned char mask, unsigned char data) { + struct pm860x_chip *chip = i2c_get_clientdata(i2c); unsigned char value; int ret; mutex_lock(&chip->io_lock); - ret = chip->read(chip, reg, 1, &value); + ret = pm860x_read_device(i2c, reg, 1, &value); if (ret < 0) goto out; value &= ~mask; value |= data; - ret = chip->write(chip, reg, 1, &value); + ret = pm860x_write_device(i2c, reg, 1, &value); out: mutex_unlock(&chip->io_lock); return ret; } -EXPORT_SYMBOL(pm8607_set_bits); +EXPORT_SYMBOL(pm860x_set_bits); static const struct i2c_device_id pm860x_id_table[] = { - { "88PM8607", 0 }, + { "88PM860x", 0 }, {} }; MODULE_DEVICE_TABLE(i2c, pm860x_id_table); +static int verify_addr(struct i2c_client *i2c) +{ + unsigned short addr_8607[] = {0x30, 0x34}; + unsigned short addr_8606[] = {0x10, 0x11}; + int size, i; + + if (i2c == NULL) + return 0; + size = ARRAY_SIZE(addr_8606); + for (i = 0; i < size; i++) { + if (i2c->addr == *(addr_8606 + i)) + return CHIP_PM8606; + } + size = ARRAY_SIZE(addr_8607); + for (i = 0; i < size; i++) { + if (i2c->addr == *(addr_8607 + i)) + return CHIP_PM8607; + } + return 0; +} + static int __devinit pm860x_probe(struct i2c_client *client, const struct i2c_device_id *id) { - struct pm8607_platform_data *pdata = client->dev.platform_data; - struct pm8607_chip *chip; - int ret; - - chip = kzalloc(sizeof(struct pm8607_chip), GFP_KERNEL); - if (chip == NULL) - return -ENOMEM; - - chip->client = client; - chip->dev = &client->dev; - chip->read = pm8607_read_device; - chip->write = pm8607_write_device; - memcpy(&chip->id, id, sizeof(struct i2c_device_id)); - i2c_set_clientdata(client, chip); - - mutex_init(&chip->io_lock); - dev_set_drvdata(chip->dev, chip); - - ret = pm860x_device_init(chip, pdata); - if (ret < 0) - goto out; - - + struct pm860x_platform_data *pdata = client->dev.platform_data; + static struct pm860x_chip *chip; + struct i2c_board_info i2c_info = { + .type = "88PM860x", + .platform_data = client->dev.platform_data, + }; + int addr_c, found_companion = 0; + + if (pdata == NULL) { + pr_info("No platform data in %s!\n", __func__); + return -EINVAL; + } + + /* + * Both client and companion client shares same platform driver. + * Driver distinguishes them by pdata->companion_addr. + * pdata->companion_addr is only assigned if companion chip exists. + * At the same time, the companion_addr shouldn't equal to client + * address. + */ + addr_c = pdata->companion_addr; + if (addr_c && (addr_c != client->addr)) { + i2c_info.addr = addr_c; + found_companion = 1; + } + + if (found_companion || (addr_c == 0)) { + chip = kzalloc(sizeof(struct pm860x_chip), GFP_KERNEL); + if (chip == NULL) + return -ENOMEM; + + chip->id = verify_addr(client); + chip->companion_addr = addr_c; + chip->client = client; + i2c_set_clientdata(client, chip); + chip->dev = &client->dev; + mutex_init(&chip->io_lock); + dev_set_drvdata(chip->dev, chip); + + if (found_companion) { + /* + * If this driver is built in, probe function is + * recursive. + * If this driver is built as module, the next probe + * function is called after the first one finished. + */ + chip->companion = i2c_new_device(client->adapter, + &i2c_info); + } + } + + /* + * If companion chip existes, it's called by companion probe. + * If there's no companion chip, it's called by client probe. + */ + if ((addr_c == 0) || (addr_c == client->addr)) { + chip->companion = client; + i2c_set_clientdata(chip->companion, chip); + pm860x_device_init(chip, pdata); + } return 0; - -out: - i2c_set_clientdata(client, NULL); - kfree(chip); - return ret; } static int __devexit pm860x_remove(struct i2c_client *client) { - struct pm8607_chip *chip = i2c_get_clientdata(client); - + struct pm860x_chip *chip = i2c_get_clientdata(client); + + /* + * If companion existes, companion client is removed first. + * Because companion client is registered last and removed first. + */ + if (chip->companion_addr == client->addr) + return 0; + pm860x_device_exit(chip); + i2c_unregister_device(chip->companion); + i2c_set_clientdata(chip->companion, NULL); + i2c_set_clientdata(chip->client, NULL); kfree(chip); return 0; } diff --git a/drivers/regulator/88pm8607.c b/drivers/regulator/88pm8607.c index 04719551381b..97897a6bf4f3 100644 --- a/drivers/regulator/88pm8607.c +++ b/drivers/regulator/88pm8607.c @@ -11,15 +11,17 @@ #include #include #include +#include #include #include #include -#include +#include struct pm8607_regulator_info { struct regulator_desc desc; - struct pm8607_chip *chip; + struct pm860x_chip *chip; struct regulator_dev *regulator; + struct i2c_client *i2c; int min_uV; int max_uV; @@ -46,7 +48,7 @@ static inline int check_range(struct pm8607_regulator_info *info, static int pm8607_list_voltage(struct regulator_dev *rdev, unsigned index) { struct pm8607_regulator_info *info = rdev_get_drvdata(rdev); - uint8_t chip_id = info->chip->chip_id; + uint8_t chip_id = info->chip->chip_version; int ret = -EINVAL; switch (info->desc.id) { @@ -169,7 +171,7 @@ static int pm8607_list_voltage(struct regulator_dev *rdev, unsigned index) static int choose_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) { struct pm8607_regulator_info *info = rdev_get_drvdata(rdev); - uint8_t chip_id = info->chip->chip_id; + uint8_t chip_id = info->chip->chip_version; int val = -ENOENT; int ret; @@ -428,7 +430,6 @@ static int pm8607_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) { struct pm8607_regulator_info *info = rdev_get_drvdata(rdev); - struct pm8607_chip *chip = info->chip; uint8_t val, mask; int ret; @@ -443,13 +444,13 @@ static int pm8607_set_voltage(struct regulator_dev *rdev, val = (uint8_t)(ret << info->vol_shift); mask = ((1 << info->vol_nbits) - 1) << info->vol_shift; - ret = pm8607_set_bits(chip, info->vol_reg, mask, val); + ret = pm860x_set_bits(info->i2c, info->vol_reg, mask, val); if (ret) return ret; switch (info->desc.id) { case PM8607_ID_BUCK1: case PM8607_ID_BUCK3: - ret = pm8607_set_bits(chip, info->update_reg, + ret = pm860x_set_bits(info->i2c, info->update_reg, 1 << info->update_bit, 1 << info->update_bit); break; @@ -460,11 +461,10 @@ static int pm8607_set_voltage(struct regulator_dev *rdev, static int pm8607_get_voltage(struct regulator_dev *rdev) { struct pm8607_regulator_info *info = rdev_get_drvdata(rdev); - struct pm8607_chip *chip = info->chip; uint8_t val, mask; int ret; - ret = pm8607_reg_read(chip, info->vol_reg); + ret = pm860x_reg_read(info->i2c, info->vol_reg); if (ret < 0) return ret; @@ -477,9 +477,8 @@ static int pm8607_get_voltage(struct regulator_dev *rdev) static int pm8607_enable(struct regulator_dev *rdev) { struct pm8607_regulator_info *info = rdev_get_drvdata(rdev); - struct pm8607_chip *chip = info->chip; - return pm8607_set_bits(chip, info->enable_reg, + return pm860x_set_bits(info->i2c, info->enable_reg, 1 << info->enable_bit, 1 << info->enable_bit); } @@ -487,19 +486,17 @@ static int pm8607_enable(struct regulator_dev *rdev) static int pm8607_disable(struct regulator_dev *rdev) { struct pm8607_regulator_info *info = rdev_get_drvdata(rdev); - struct pm8607_chip *chip = info->chip; - return pm8607_set_bits(chip, info->enable_reg, + return pm860x_set_bits(info->i2c, info->enable_reg, 1 << info->enable_bit, 0); } static int pm8607_is_enabled(struct regulator_dev *rdev) { struct pm8607_regulator_info *info = rdev_get_drvdata(rdev); - struct pm8607_chip *chip = info->chip; int ret; - ret = pm8607_reg_read(chip, info->enable_reg); + ret = pm860x_reg_read(info->i2c, info->enable_reg); if (ret < 0) return ret; @@ -589,8 +586,8 @@ static inline struct pm8607_regulator_info *find_regulator_info(int id) static int __devinit pm8607_regulator_probe(struct platform_device *pdev) { - struct pm8607_chip *chip = dev_get_drvdata(pdev->dev.parent); - struct pm8607_platform_data *pdata = chip->dev->platform_data; + struct pm860x_chip *chip = dev_get_drvdata(pdev->dev.parent); + struct pm860x_platform_data *pdata = chip->dev->platform_data; struct pm8607_regulator_info *info = NULL; info = find_regulator_info(pdev->id); @@ -599,6 +596,7 @@ static int __devinit pm8607_regulator_probe(struct platform_device *pdev) return -EINVAL; } + info->i2c = (chip->id == CHIP_PM8607) ? chip->client : chip->companion; info->chip = chip; info->regulator = regulator_register(&info->desc, &pdev->dev, diff --git a/include/linux/mfd/88pm8607.h b/include/linux/mfd/88pm8607.h deleted file mode 100644 index 6e4dcdca02a8..000000000000 --- a/include/linux/mfd/88pm8607.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Marvell 88PM8607 Interface - * - * Copyright (C) 2009 Marvell International Ltd. - * Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __LINUX_MFD_88PM8607_H -#define __LINUX_MFD_88PM8607_H - -enum { - PM8607_ID_BUCK1 = 0, - PM8607_ID_BUCK2, - PM8607_ID_BUCK3, - - PM8607_ID_LDO1, - PM8607_ID_LDO2, - PM8607_ID_LDO3, - PM8607_ID_LDO4, - PM8607_ID_LDO5, - PM8607_ID_LDO6, - PM8607_ID_LDO7, - PM8607_ID_LDO8, - PM8607_ID_LDO9, - PM8607_ID_LDO10, - PM8607_ID_LDO12, - PM8607_ID_LDO14, - - PM8607_ID_RG_MAX, -}; - -#define PM8607_ID (0x40) /* 8607 chip ID */ -#define PM8607_ID_MASK (0xF8) /* 8607 chip ID mask */ - -/* Interrupt Registers */ -#define PM8607_STATUS_1 (0x01) -#define PM8607_STATUS_2 (0x02) -#define PM8607_INT_STATUS1 (0x03) -#define PM8607_INT_STATUS2 (0x04) -#define PM8607_INT_STATUS3 (0x05) -#define PM8607_INT_MASK_1 (0x06) -#define PM8607_INT_MASK_2 (0x07) -#define PM8607_INT_MASK_3 (0x08) - -/* Regulator Control Registers */ -#define PM8607_LDO1 (0x10) -#define PM8607_LDO2 (0x11) -#define PM8607_LDO3 (0x12) -#define PM8607_LDO4 (0x13) -#define PM8607_LDO5 (0x14) -#define PM8607_LDO6 (0x15) -#define PM8607_LDO7 (0x16) -#define PM8607_LDO8 (0x17) -#define PM8607_LDO9 (0x18) -#define PM8607_LDO10 (0x19) -#define PM8607_LDO12 (0x1A) -#define PM8607_LDO14 (0x1B) -#define PM8607_SLEEP_MODE1 (0x1C) -#define PM8607_SLEEP_MODE2 (0x1D) -#define PM8607_SLEEP_MODE3 (0x1E) -#define PM8607_SLEEP_MODE4 (0x1F) -#define PM8607_GO (0x20) -#define PM8607_SLEEP_BUCK1 (0x21) -#define PM8607_SLEEP_BUCK2 (0x22) -#define PM8607_SLEEP_BUCK3 (0x23) -#define PM8607_BUCK1 (0x24) -#define PM8607_BUCK2 (0x25) -#define PM8607_BUCK3 (0x26) -#define PM8607_BUCK_CONTROLS (0x27) -#define PM8607_SUPPLIES_EN11 (0x2B) -#define PM8607_SUPPLIES_EN12 (0x2C) -#define PM8607_GROUP1 (0x2D) -#define PM8607_GROUP2 (0x2E) -#define PM8607_GROUP3 (0x2F) -#define PM8607_GROUP4 (0x30) -#define PM8607_GROUP5 (0x31) -#define PM8607_GROUP6 (0x32) -#define PM8607_SUPPLIES_EN21 (0x33) -#define PM8607_SUPPLIES_EN22 (0x34) - -/* RTC Control Registers */ -#define PM8607_RTC1 (0xA0) -#define PM8607_RTC_COUNTER1 (0xA1) -#define PM8607_RTC_COUNTER2 (0xA2) -#define PM8607_RTC_COUNTER3 (0xA3) -#define PM8607_RTC_COUNTER4 (0xA4) -#define PM8607_RTC_EXPIRE1 (0xA5) -#define PM8607_RTC_EXPIRE2 (0xA6) -#define PM8607_RTC_EXPIRE3 (0xA7) -#define PM8607_RTC_EXPIRE4 (0xA8) -#define PM8607_RTC_TRIM1 (0xA9) -#define PM8607_RTC_TRIM2 (0xAA) -#define PM8607_RTC_TRIM3 (0xAB) -#define PM8607_RTC_TRIM4 (0xAC) -#define PM8607_RTC_MISC1 (0xAD) -#define PM8607_RTC_MISC2 (0xAE) -#define PM8607_RTC_MISC3 (0xAF) - -/* Misc Registers */ -#define PM8607_CHIP_ID (0x00) -#define PM8607_LDO1 (0x10) -#define PM8607_DVC3 (0x26) -#define PM8607_MISC1 (0x40) - -/* bit definitions for PM8607 events */ -#define PM8607_EVENT_ONKEY (1 << 0) -#define PM8607_EVENT_EXTON (1 << 1) -#define PM8607_EVENT_CHG (1 << 2) -#define PM8607_EVENT_BAT (1 << 3) -#define PM8607_EVENT_RTC (1 << 4) -#define PM8607_EVENT_CC (1 << 5) -#define PM8607_EVENT_VBAT (1 << 8) -#define PM8607_EVENT_VCHG (1 << 9) -#define PM8607_EVENT_VSYS (1 << 10) -#define PM8607_EVENT_TINT (1 << 11) -#define PM8607_EVENT_GPADC0 (1 << 12) -#define PM8607_EVENT_GPADC1 (1 << 13) -#define PM8607_EVENT_GPADC2 (1 << 14) -#define PM8607_EVENT_GPADC3 (1 << 15) -#define PM8607_EVENT_AUDIO_SHORT (1 << 16) -#define PM8607_EVENT_PEN (1 << 17) -#define PM8607_EVENT_HEADSET (1 << 18) -#define PM8607_EVENT_HOOK (1 << 19) -#define PM8607_EVENT_MICIN (1 << 20) -#define PM8607_EVENT_CHG_TIMEOUT (1 << 21) -#define PM8607_EVENT_CHG_DONE (1 << 22) -#define PM8607_EVENT_CHG_FAULT (1 << 23) - -/* bit definitions of Status Query Interface */ -#define PM8607_STATUS_CC (1 << 3) -#define PM8607_STATUS_PEN (1 << 4) -#define PM8607_STATUS_HEADSET (1 << 5) -#define PM8607_STATUS_HOOK (1 << 6) -#define PM8607_STATUS_MICIN (1 << 7) -#define PM8607_STATUS_ONKEY (1 << 8) -#define PM8607_STATUS_EXTON (1 << 9) -#define PM8607_STATUS_CHG (1 << 10) -#define PM8607_STATUS_BAT (1 << 11) -#define PM8607_STATUS_VBUS (1 << 12) -#define PM8607_STATUS_OV (1 << 13) - -/* bit definitions of BUCK3 */ -#define PM8607_BUCK3_DOUBLE (1 << 6) - -/* bit definitions of Misc1 */ -#define PM8607_MISC1_PI2C (1 << 0) - -/* Interrupt Number in 88PM8607 */ -enum { - PM8607_IRQ_ONKEY = 0, - PM8607_IRQ_EXTON, - PM8607_IRQ_CHG, - PM8607_IRQ_BAT, - PM8607_IRQ_RTC, - PM8607_IRQ_VBAT = 8, - PM8607_IRQ_VCHG, - PM8607_IRQ_VSYS, - PM8607_IRQ_TINT, - PM8607_IRQ_GPADC0, - PM8607_IRQ_GPADC1, - PM8607_IRQ_GPADC2, - PM8607_IRQ_GPADC3, - PM8607_IRQ_AUDIO_SHORT = 16, - PM8607_IRQ_PEN, - PM8607_IRQ_HEADSET, - PM8607_IRQ_HOOK, - PM8607_IRQ_MICIN, - PM8607_IRQ_CHG_FAIL, - PM8607_IRQ_CHG_DONE, - PM8607_IRQ_CHG_FAULT, -}; - -enum { - PM8607_CHIP_A0 = 0x40, - PM8607_CHIP_A1 = 0x41, - PM8607_CHIP_B0 = 0x48, -}; - - -struct pm8607_chip { - struct device *dev; - struct mutex io_lock; - struct i2c_client *client; - struct i2c_device_id id; - - int (*read)(struct pm8607_chip *chip, int reg, int bytes, void *dest); - int (*write)(struct pm8607_chip *chip, int reg, int bytes, void *src); - - int buck3_double; /* DVC ramp slope double */ - unsigned char chip_id; - -}; - -#define PM8607_MAX_REGULATOR 15 /* 3 Bucks, 12 LDOs */ - -enum { - GI2C_PORT = 0, - PI2C_PORT, -}; - -struct pm8607_platform_data { - int i2c_port; /* Controlled by GI2C or PI2C */ - struct regulator_init_data *regulator[PM8607_MAX_REGULATOR]; -}; - -extern int pm8607_reg_read(struct pm8607_chip *, int); -extern int pm8607_reg_write(struct pm8607_chip *, int, unsigned char); -extern int pm8607_bulk_read(struct pm8607_chip *, int, int, - unsigned char *); -extern int pm8607_bulk_write(struct pm8607_chip *, int, int, - unsigned char *); -extern int pm8607_set_bits(struct pm8607_chip *, int, unsigned char, - unsigned char); - -extern int pm860x_device_init(struct pm8607_chip *chip, - struct pm8607_platform_data *pdata); -extern void pm860x_device_exit(struct pm8607_chip *chip); - -#endif /* __LINUX_MFD_88PM860X_H */ diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h new file mode 100644 index 000000000000..5845ae47df30 --- /dev/null +++ b/include/linux/mfd/88pm860x.h @@ -0,0 +1,227 @@ +/* + * Marvell 88PM860x Interface + * + * Copyright (C) 2009 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_MFD_88PM860X_H +#define __LINUX_MFD_88PM860X_H + +enum { + CHIP_INVALID = 0, + CHIP_PM8606, + CHIP_PM8607, + CHIP_MAX, +}; + +enum { + PM8607_ID_BUCK1 = 0, + PM8607_ID_BUCK2, + PM8607_ID_BUCK3, + + PM8607_ID_LDO1, + PM8607_ID_LDO2, + PM8607_ID_LDO3, + PM8607_ID_LDO4, + PM8607_ID_LDO5, + PM8607_ID_LDO6, + PM8607_ID_LDO7, + PM8607_ID_LDO8, + PM8607_ID_LDO9, + PM8607_ID_LDO10, + PM8607_ID_LDO12, + PM8607_ID_LDO14, + + PM8607_ID_RG_MAX, +}; + +#define PM8607_VERSION (0x40) /* 8607 chip ID */ +#define PM8607_VERSION_MASK (0xF0) /* 8607 chip ID mask */ + +/* Interrupt Registers */ +#define PM8607_STATUS_1 (0x01) +#define PM8607_STATUS_2 (0x02) +#define PM8607_INT_STATUS1 (0x03) +#define PM8607_INT_STATUS2 (0x04) +#define PM8607_INT_STATUS3 (0x05) +#define PM8607_INT_MASK_1 (0x06) +#define PM8607_INT_MASK_2 (0x07) +#define PM8607_INT_MASK_3 (0x08) + +/* Regulator Control Registers */ +#define PM8607_LDO1 (0x10) +#define PM8607_LDO2 (0x11) +#define PM8607_LDO3 (0x12) +#define PM8607_LDO4 (0x13) +#define PM8607_LDO5 (0x14) +#define PM8607_LDO6 (0x15) +#define PM8607_LDO7 (0x16) +#define PM8607_LDO8 (0x17) +#define PM8607_LDO9 (0x18) +#define PM8607_LDO10 (0x19) +#define PM8607_LDO12 (0x1A) +#define PM8607_LDO14 (0x1B) +#define PM8607_SLEEP_MODE1 (0x1C) +#define PM8607_SLEEP_MODE2 (0x1D) +#define PM8607_SLEEP_MODE3 (0x1E) +#define PM8607_SLEEP_MODE4 (0x1F) +#define PM8607_GO (0x20) +#define PM8607_SLEEP_BUCK1 (0x21) +#define PM8607_SLEEP_BUCK2 (0x22) +#define PM8607_SLEEP_BUCK3 (0x23) +#define PM8607_BUCK1 (0x24) +#define PM8607_BUCK2 (0x25) +#define PM8607_BUCK3 (0x26) +#define PM8607_BUCK_CONTROLS (0x27) +#define PM8607_SUPPLIES_EN11 (0x2B) +#define PM8607_SUPPLIES_EN12 (0x2C) +#define PM8607_GROUP1 (0x2D) +#define PM8607_GROUP2 (0x2E) +#define PM8607_GROUP3 (0x2F) +#define PM8607_GROUP4 (0x30) +#define PM8607_GROUP5 (0x31) +#define PM8607_GROUP6 (0x32) +#define PM8607_SUPPLIES_EN21 (0x33) +#define PM8607_SUPPLIES_EN22 (0x34) + +/* RTC Control Registers */ +#define PM8607_RTC1 (0xA0) +#define PM8607_RTC_COUNTER1 (0xA1) +#define PM8607_RTC_COUNTER2 (0xA2) +#define PM8607_RTC_COUNTER3 (0xA3) +#define PM8607_RTC_COUNTER4 (0xA4) +#define PM8607_RTC_EXPIRE1 (0xA5) +#define PM8607_RTC_EXPIRE2 (0xA6) +#define PM8607_RTC_EXPIRE3 (0xA7) +#define PM8607_RTC_EXPIRE4 (0xA8) +#define PM8607_RTC_TRIM1 (0xA9) +#define PM8607_RTC_TRIM2 (0xAA) +#define PM8607_RTC_TRIM3 (0xAB) +#define PM8607_RTC_TRIM4 (0xAC) +#define PM8607_RTC_MISC1 (0xAD) +#define PM8607_RTC_MISC2 (0xAE) +#define PM8607_RTC_MISC3 (0xAF) + +/* Misc Registers */ +#define PM8607_CHIP_ID (0x00) +#define PM8607_LDO1 (0x10) +#define PM8607_DVC3 (0x26) +#define PM8607_MISC1 (0x40) + +/* bit definitions for PM8607 events */ +#define PM8607_EVENT_ONKEY (1 << 0) +#define PM8607_EVENT_EXTON (1 << 1) +#define PM8607_EVENT_CHG (1 << 2) +#define PM8607_EVENT_BAT (1 << 3) +#define PM8607_EVENT_RTC (1 << 4) +#define PM8607_EVENT_CC (1 << 5) +#define PM8607_EVENT_VBAT (1 << 8) +#define PM8607_EVENT_VCHG (1 << 9) +#define PM8607_EVENT_VSYS (1 << 10) +#define PM8607_EVENT_TINT (1 << 11) +#define PM8607_EVENT_GPADC0 (1 << 12) +#define PM8607_EVENT_GPADC1 (1 << 13) +#define PM8607_EVENT_GPADC2 (1 << 14) +#define PM8607_EVENT_GPADC3 (1 << 15) +#define PM8607_EVENT_AUDIO_SHORT (1 << 16) +#define PM8607_EVENT_PEN (1 << 17) +#define PM8607_EVENT_HEADSET (1 << 18) +#define PM8607_EVENT_HOOK (1 << 19) +#define PM8607_EVENT_MICIN (1 << 20) +#define PM8607_EVENT_CHG_TIMEOUT (1 << 21) +#define PM8607_EVENT_CHG_DONE (1 << 22) +#define PM8607_EVENT_CHG_FAULT (1 << 23) + +/* bit definitions of Status Query Interface */ +#define PM8607_STATUS_CC (1 << 3) +#define PM8607_STATUS_PEN (1 << 4) +#define PM8607_STATUS_HEADSET (1 << 5) +#define PM8607_STATUS_HOOK (1 << 6) +#define PM8607_STATUS_MICIN (1 << 7) +#define PM8607_STATUS_ONKEY (1 << 8) +#define PM8607_STATUS_EXTON (1 << 9) +#define PM8607_STATUS_CHG (1 << 10) +#define PM8607_STATUS_BAT (1 << 11) +#define PM8607_STATUS_VBUS (1 << 12) +#define PM8607_STATUS_OV (1 << 13) + +/* bit definitions of BUCK3 */ +#define PM8607_BUCK3_DOUBLE (1 << 6) + +/* bit definitions of Misc1 */ +#define PM8607_MISC1_PI2C (1 << 0) + +/* Interrupt Number in 88PM8607 */ +enum { + PM8607_IRQ_ONKEY = 0, + PM8607_IRQ_EXTON, + PM8607_IRQ_CHG, + PM8607_IRQ_BAT, + PM8607_IRQ_RTC, + PM8607_IRQ_VBAT = 8, + PM8607_IRQ_VCHG, + PM8607_IRQ_VSYS, + PM8607_IRQ_TINT, + PM8607_IRQ_GPADC0, + PM8607_IRQ_GPADC1, + PM8607_IRQ_GPADC2, + PM8607_IRQ_GPADC3, + PM8607_IRQ_AUDIO_SHORT = 16, + PM8607_IRQ_PEN, + PM8607_IRQ_HEADSET, + PM8607_IRQ_HOOK, + PM8607_IRQ_MICIN, + PM8607_IRQ_CHG_FAIL, + PM8607_IRQ_CHG_DONE, + PM8607_IRQ_CHG_FAULT, +}; + +enum { + PM8607_CHIP_A0 = 0x40, + PM8607_CHIP_A1 = 0x41, + PM8607_CHIP_B0 = 0x48, +}; + +struct pm860x_chip { + struct device *dev; + struct mutex io_lock; + struct i2c_client *client; + struct i2c_client *companion; /* companion chip client */ + + int buck3_double; /* DVC ramp slope double */ + unsigned short companion_addr; + int id; + unsigned char chip_version; + +}; + +#define PM8607_MAX_REGULATOR 15 /* 3 Bucks, 12 LDOs */ + +enum { + GI2C_PORT = 0, + PI2C_PORT, +}; + +struct pm860x_platform_data { + unsigned short companion_addr; /* I2C address of companion chip */ + int i2c_port; /* Controlled by GI2C or PI2C */ + struct regulator_init_data *regulator[PM8607_MAX_REGULATOR]; +}; + +extern int pm860x_reg_read(struct i2c_client *, int); +extern int pm860x_reg_write(struct i2c_client *, int, unsigned char); +extern int pm860x_bulk_read(struct i2c_client *, int, int, unsigned char *); +extern int pm860x_bulk_write(struct i2c_client *, int, int, unsigned char *); +extern int pm860x_set_bits(struct i2c_client *, int, unsigned char, + unsigned char); + +extern int pm860x_device_init(struct pm860x_chip *chip, + struct pm860x_platform_data *pdata); +extern void pm860x_device_exit(struct pm860x_chip *chip); + +#endif /* __LINUX_MFD_88PM860X_H */ -- cgit v1.2.3 From 2cc50bee9934deb6dfe32929a4c1742cf83d6db3 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 6 Jan 2010 17:07:13 -0500 Subject: mfd: Rename 88pm8607 to 88pm860x in mfd Rename 88PM8607 to 88PM860X in both Makefile and Kconfig under mfd directory. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/mfd/Kconfig | 20 ++++++++++---------- drivers/mfd/Makefile | 3 ++- drivers/regulator/Kconfig | 2 +- 3 files changed, 13 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index d957373d77e4..815907eb70a4 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -9,6 +9,16 @@ config MFD_CORE tristate default n +config MFD_88PM860X + bool "Support Marvell 88PM8606/88PM8607" + depends on I2C=y + select MFD_CORE + help + This supports for Marvell 88PM8606/88PM8607 Power Management IC. + This includes the I2C driver and the core APIs _only_, you have to + select individual components like voltage regulators, RTC and + battery-charger under the corresponding menus. + config MFD_SM501 tristate "Support for Silicon Motion SM501" ---help--- @@ -329,16 +339,6 @@ config EZX_PCAP This enables the PCAP ASIC present on EZX Phones. This is needed for MMC, TouchScreen, Sound, USB, etc.. -config MFD_88PM8607 - bool "Support Marvell 88PM8607" - depends on I2C=y - select MFD_CORE - help - This supports for Marvell 88PM8607 Power Management IC. This includes - the I2C driver and the core APIs _only_, you have to select - individual components like voltage regulators, RTC and - battery-charger under the corresponding menus. - config AB4500_CORE tristate "ST-Ericsson's AB4500 Mixed Signal Power management chip" depends on SPI diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 88fa200188cf..1e3ae062c1f6 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -2,7 +2,8 @@ # Makefile for multifunction miscellaneous devices # -obj-$(CONFIG_MFD_88PM8607) += 88pm860x-core.o 88pm860x-i2c.o +88pm860x-objs := 88pm860x-core.o 88pm860x-i2c.o +obj-$(CONFIG_MFD_88PM860X) += 88pm860x.o obj-$(CONFIG_MFD_SM501) += sm501.o obj-$(CONFIG_MFD_ASIC3) += asic3.o tmio_core.o obj-$(CONFIG_MFD_SH_MOBILE_SDHI) += sh_mobile_sdhi.o diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 834b48441829..dbfe31a4a519 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -191,7 +191,7 @@ config REGULATOR_TPS6507X config REGULATOR_88PM8607 bool "Marvell 88PM8607 Power regulators" - depends on MFD_88PM8607=y + depends on MFD_88PM860X=y help This driver supports 88PM8607 voltage regulator chips. -- cgit v1.2.3 From 5c42e8c4a9c86ea26ed4ecb732a842dea0dfb6b6 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Tue, 15 Dec 2009 16:01:47 -0500 Subject: mfd: Add irq support in 88pm860x 88PM860x is a complex PMIC device. It contains touch, charger, sound, rtc, backlight, led, and so on. Host communicates to 88PM860x by I2C bus. Use thread irq to support this usage case. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/mfd/88pm860x-core.c | 226 +++++++++++++++++++++++++++++++++++++++++-- include/linux/mfd/88pm860x.h | 54 ++++++----- 2 files changed, 247 insertions(+), 33 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c index 72b00304dc3a..9185f0d945f4 100644 --- a/drivers/mfd/88pm860x-core.c +++ b/drivers/mfd/88pm860x-core.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -67,15 +68,209 @@ static struct mfd_cell pm8607_devs[] = { PM8607_REG_DEVS(ldo14, LDO14), }; -static void device_8606_init(struct pm860x_chip *chip, struct i2c_client *i2c, - struct pm860x_platform_data *pdata) +#define CHECK_IRQ(irq) \ +do { \ + if ((irq < 0) || (irq >= PM860X_NUM_IRQ)) \ + return -EINVAL; \ +} while (0) + +/* IRQs only occur on 88PM8607 */ +int pm860x_mask_irq(struct pm860x_chip *chip, int irq) +{ + struct i2c_client *i2c = (chip->id == CHIP_PM8607) ? chip->client \ + : chip->companion; + int offset, data, ret; + + CHECK_IRQ(irq); + + offset = (irq >> 3) + PM8607_INT_MASK_1; + data = 1 << (irq % 8); + ret = pm860x_set_bits(i2c, offset, data, 0); + + return ret; +} +EXPORT_SYMBOL(pm860x_mask_irq); + +int pm860x_unmask_irq(struct pm860x_chip *chip, int irq) +{ + struct i2c_client *i2c = (chip->id == CHIP_PM8607) ? chip->client \ + : chip->companion; + int offset, data, ret; + + CHECK_IRQ(irq); + + offset = (irq >> 3) + PM8607_INT_MASK_1; + data = 1 << (irq % 8); + ret = pm860x_set_bits(i2c, offset, data, data); + + return ret; +} +EXPORT_SYMBOL(pm860x_unmask_irq); + +#define INT_STATUS_NUM (3) + +static irqreturn_t pm8607_irq_thread(int irq, void *data) +{ + DECLARE_BITMAP(irq_status, PM860X_NUM_IRQ); + struct pm860x_chip *chip = data; + struct i2c_client *i2c = (chip->id == CHIP_PM8607) ? chip->client \ + : chip->companion; + unsigned char status_buf[INT_STATUS_NUM << 1]; + unsigned long value; + int i, ret; + + irq_status[0] = 0; + + /* read out status register */ + ret = pm860x_bulk_read(i2c, PM8607_INT_STATUS1, + INT_STATUS_NUM << 1, status_buf); + if (ret < 0) + goto out; + if (chip->irq_mode) { + /* 0, clear by read. 1, clear by write */ + ret = pm860x_bulk_write(i2c, PM8607_INT_STATUS1, + INT_STATUS_NUM, status_buf); + if (ret < 0) + goto out; + } + + /* clear masked interrupt status */ + for (i = 0, value = 0; i < INT_STATUS_NUM; i++) { + status_buf[i] &= status_buf[i + INT_STATUS_NUM]; + irq_status[0] |= status_buf[i] << (i * 8); + } + + while (!bitmap_empty(irq_status, PM860X_NUM_IRQ)) { + irq = find_first_bit(irq_status, PM860X_NUM_IRQ); + clear_bit(irq, irq_status); + dev_dbg(chip->dev, "Servicing IRQ #%d\n", irq); + + mutex_lock(&chip->irq_lock); + if (chip->irq[irq].handler) + chip->irq[irq].handler(irq, chip->irq[irq].data); + else { + pm860x_mask_irq(chip, irq); + dev_err(chip->dev, "Nobody cares IRQ %d. " + "Now mask it.\n", irq); + for (i = 0; i < (INT_STATUS_NUM << 1); i++) { + dev_err(chip->dev, "status[%d]:%x\n", i, + status_buf[i]); + } + } + mutex_unlock(&chip->irq_lock); + } +out: + return IRQ_HANDLED; +} + +int pm860x_request_irq(struct pm860x_chip *chip, int irq, + irq_handler_t handler, void *data) { + CHECK_IRQ(irq); + if (!handler) + return -EINVAL; + + mutex_lock(&chip->irq_lock); + chip->irq[irq].handler = handler; + chip->irq[irq].data = data; + mutex_unlock(&chip->irq_lock); + + return 0; } +EXPORT_SYMBOL(pm860x_request_irq); -static void device_8607_init(struct pm860x_chip *chip, struct i2c_client *i2c, - struct pm860x_platform_data *pdata) +int pm860x_free_irq(struct pm860x_chip *chip, int irq) { - int i, count; + CHECK_IRQ(irq); + + mutex_lock(&chip->irq_lock); + chip->irq[irq].handler = NULL; + chip->irq[irq].data = NULL; + mutex_unlock(&chip->irq_lock); + + return 0; +} +EXPORT_SYMBOL(pm860x_free_irq); + +static int __devinit device_irq_init(struct pm860x_chip *chip, + struct pm860x_platform_data *pdata) +{ + struct i2c_client *i2c = (chip->id == CHIP_PM8607) ? chip->client \ + : chip->companion; + unsigned char status_buf[INT_STATUS_NUM]; + int data, mask, ret = -EINVAL; + + mutex_init(&chip->irq_lock); + + mask = PM8607_B0_MISC1_INV_INT | PM8607_B0_MISC1_INT_CLEAR + | PM8607_B0_MISC1_INT_MASK; + data = 0; + chip->irq_mode = 0; + if (pdata && pdata->irq_mode) { + /* + * irq_mode defines the way of clearing interrupt. If it's 1, + * clear IRQ by write. Otherwise, clear it by read. + * This control bit is valid from 88PM8607 B0 steping. + */ + data |= PM8607_B0_MISC1_INT_CLEAR; + chip->irq_mode = 1; + } + ret = pm860x_set_bits(i2c, PM8607_B0_MISC1, mask, data); + if (ret < 0) + goto out; + + /* mask all IRQs */ + memset(status_buf, 0, INT_STATUS_NUM); + ret = pm860x_bulk_write(i2c, PM8607_INT_MASK_1, + INT_STATUS_NUM, status_buf); + if (ret < 0) + goto out; + + if (chip->irq_mode) { + /* clear interrupt status by write */ + memset(status_buf, 0xFF, INT_STATUS_NUM); + ret = pm860x_bulk_write(i2c, PM8607_INT_STATUS1, + INT_STATUS_NUM, status_buf); + } else { + /* clear interrupt status by read */ + ret = pm860x_bulk_read(i2c, PM8607_INT_STATUS1, + INT_STATUS_NUM, status_buf); + } + if (ret < 0) + goto out; + + memset(chip->irq, 0, sizeof(struct pm860x_irq) * PM860X_NUM_IRQ); + + ret = request_threaded_irq(i2c->irq, NULL, pm8607_irq_thread, + IRQF_ONESHOT | IRQF_TRIGGER_LOW, + "88PM8607", chip); + if (ret < 0) { + dev_err(chip->dev, "Failed to request IRQ #%d.\n", i2c->irq); + goto out; + } + chip->chip_irq = i2c->irq; + return 0; +out: + return ret; +} + +static void __devexit device_irq_exit(struct pm860x_chip *chip) +{ + if (chip->chip_irq >= 0) + free_irq(chip->chip_irq, chip); +} + +static void __devinit device_8606_init(struct pm860x_chip *chip, + struct i2c_client *i2c, + struct pm860x_platform_data *pdata) +{ +} + +static void __devinit device_8607_init(struct pm860x_chip *chip, + struct i2c_client *i2c, + struct pm860x_platform_data *pdata) +{ + int i, count, data; int ret; ret = pm860x_reg_read(i2c, PM8607_CHIP_ID); @@ -91,7 +286,6 @@ static void device_8607_init(struct pm860x_chip *chip, struct i2c_client *i2c, "Chip ID: %02x\n", ret); goto out; } - chip->chip_version = ret; ret = pm860x_reg_read(i2c, PM8607_BUCK3); if (ret < 0) { @@ -101,12 +295,26 @@ static void device_8607_init(struct pm860x_chip *chip, struct i2c_client *i2c, if (ret & PM8607_BUCK3_DOUBLE) chip->buck3_double = 1; - ret = pm860x_reg_read(i2c, PM8607_MISC1); + ret = pm860x_reg_read(i2c, PM8607_B0_MISC1); if (ret < 0) { dev_err(chip->dev, "Failed to read MISC1 register: %d\n", ret); goto out; } + if (pdata && (pdata->i2c_port == PI2C_PORT)) + data = PM8607_B0_MISC1_PI2C; + else + data = 0; + ret = pm860x_set_bits(i2c, PM8607_B0_MISC1, PM8607_B0_MISC1_PI2C, data); + if (ret < 0) { + dev_err(chip->dev, "Failed to access MISC1:%d\n", ret); + goto out; + } + + ret = device_irq_init(chip, pdata); + if (ret < 0) + goto out; + count = ARRAY_SIZE(pm8607_devs); for (i = 0; i < count; i++) { ret = mfd_add_devices(chip->dev, i, &pm8607_devs[i], @@ -123,6 +331,8 @@ out: int pm860x_device_init(struct pm860x_chip *chip, struct pm860x_platform_data *pdata) { + chip->chip_irq = -EINVAL; + switch (chip->id) { case CHIP_PM8606: device_8606_init(chip, chip->client, pdata); @@ -142,11 +352,13 @@ int pm860x_device_init(struct pm860x_chip *chip, break; } } + return 0; } void pm860x_device_exit(struct pm860x_chip *chip) { + device_irq_exit(chip); mfd_remove_devices(chip->dev); } diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h index 5845ae47df30..b4d6018ba0d6 100644 --- a/include/linux/mfd/88pm860x.h +++ b/include/linux/mfd/88pm860x.h @@ -12,6 +12,8 @@ #ifndef __LINUX_MFD_88PM860X_H #define __LINUX_MFD_88PM860X_H +#include + enum { CHIP_INVALID = 0, CHIP_PM8606, @@ -109,33 +111,10 @@ enum { /* Misc Registers */ #define PM8607_CHIP_ID (0x00) +#define PM8607_B0_MISC1 (0x0C) #define PM8607_LDO1 (0x10) #define PM8607_DVC3 (0x26) -#define PM8607_MISC1 (0x40) - -/* bit definitions for PM8607 events */ -#define PM8607_EVENT_ONKEY (1 << 0) -#define PM8607_EVENT_EXTON (1 << 1) -#define PM8607_EVENT_CHG (1 << 2) -#define PM8607_EVENT_BAT (1 << 3) -#define PM8607_EVENT_RTC (1 << 4) -#define PM8607_EVENT_CC (1 << 5) -#define PM8607_EVENT_VBAT (1 << 8) -#define PM8607_EVENT_VCHG (1 << 9) -#define PM8607_EVENT_VSYS (1 << 10) -#define PM8607_EVENT_TINT (1 << 11) -#define PM8607_EVENT_GPADC0 (1 << 12) -#define PM8607_EVENT_GPADC1 (1 << 13) -#define PM8607_EVENT_GPADC2 (1 << 14) -#define PM8607_EVENT_GPADC3 (1 << 15) -#define PM8607_EVENT_AUDIO_SHORT (1 << 16) -#define PM8607_EVENT_PEN (1 << 17) -#define PM8607_EVENT_HEADSET (1 << 18) -#define PM8607_EVENT_HOOK (1 << 19) -#define PM8607_EVENT_MICIN (1 << 20) -#define PM8607_EVENT_CHG_TIMEOUT (1 << 21) -#define PM8607_EVENT_CHG_DONE (1 << 22) -#define PM8607_EVENT_CHG_FAULT (1 << 23) +#define PM8607_A1_MISC1 (0x40) /* bit definitions of Status Query Interface */ #define PM8607_STATUS_CC (1 << 3) @@ -154,7 +133,12 @@ enum { #define PM8607_BUCK3_DOUBLE (1 << 6) /* bit definitions of Misc1 */ -#define PM8607_MISC1_PI2C (1 << 0) +#define PM8607_A1_MISC1_PI2C (1 << 0) +#define PM8607_B0_MISC1_INV_INT (1 << 0) +#define PM8607_B0_MISC1_INT_CLEAR (1 << 1) +#define PM8607_B0_MISC1_INT_MASK (1 << 2) +#define PM8607_B0_MISC1_PI2C (1 << 3) +#define PM8607_B0_MISC1_RESET (1 << 6) /* Interrupt Number in 88PM8607 */ enum { @@ -187,15 +171,26 @@ enum { PM8607_CHIP_B0 = 0x48, }; +#define PM860X_NUM_IRQ 24 + +struct pm860x_irq { + irq_handler_t handler; + void *data; +}; + struct pm860x_chip { struct device *dev; struct mutex io_lock; + struct mutex irq_lock; struct i2c_client *client; struct i2c_client *companion; /* companion chip client */ + struct pm860x_irq irq[PM860X_NUM_IRQ]; int buck3_double; /* DVC ramp slope double */ unsigned short companion_addr; int id; + int irq_mode; + int chip_irq; unsigned char chip_version; }; @@ -210,6 +205,7 @@ enum { struct pm860x_platform_data { unsigned short companion_addr; /* I2C address of companion chip */ int i2c_port; /* Controlled by GI2C or PI2C */ + int irq_mode; /* Clear interrupt by read/write(0/1) */ struct regulator_init_data *regulator[PM8607_MAX_REGULATOR]; }; @@ -220,6 +216,12 @@ extern int pm860x_bulk_write(struct i2c_client *, int, int, unsigned char *); extern int pm860x_set_bits(struct i2c_client *, int, unsigned char, unsigned char); +extern int pm860x_mask_irq(struct pm860x_chip *, int); +extern int pm860x_unmask_irq(struct pm860x_chip *, int); +extern int pm860x_request_irq(struct pm860x_chip *, int, + irq_handler_t handler, void *); +extern int pm860x_free_irq(struct pm860x_chip *, int); + extern int pm860x_device_init(struct pm860x_chip *chip, struct pm860x_platform_data *pdata); extern void pm860x_device_exit(struct pm860x_chip *chip); -- cgit v1.2.3 From a16122bcacf050e7f83015183053cf799713cc37 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Tue, 15 Dec 2009 16:04:36 -0500 Subject: mfd: Append subdev into 88pm860x driver Append backlight, led & touch subdevs into 88pm860x driver. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/mfd/88pm860x-core.c | 217 ++++++++++++++++++++++++++++++++++++++++--- include/linux/mfd/88pm860x.h | 151 ++++++++++++++++++++++++++++++ 2 files changed, 356 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c index 9185f0d945f4..16f0dca707a7 100644 --- a/drivers/mfd/88pm860x-core.c +++ b/drivers/mfd/88pm860x-core.c @@ -17,6 +17,100 @@ #include #include +char pm860x_backlight_name[][MFD_NAME_SIZE] = { + "backlight-0", + "backlight-1", + "backlight-2", +}; +EXPORT_SYMBOL(pm860x_backlight_name); + +char pm860x_led_name[][MFD_NAME_SIZE] = { + "led0-red", + "led0-green", + "led0-blue", + "led1-red", + "led1-green", + "led1-blue", +}; +EXPORT_SYMBOL(pm860x_led_name); + +#define PM8606_BACKLIGHT_RESOURCE(_i, _x) \ +{ \ + .name = pm860x_backlight_name[_i], \ + .start = PM8606_##_x, \ + .end = PM8606_##_x, \ + .flags = IORESOURCE_IO, \ +} + +static struct resource backlight_resources[] = { + PM8606_BACKLIGHT_RESOURCE(PM8606_BACKLIGHT1, WLED1A), + PM8606_BACKLIGHT_RESOURCE(PM8606_BACKLIGHT2, WLED2A), + PM8606_BACKLIGHT_RESOURCE(PM8606_BACKLIGHT3, WLED3A), +}; + +#define PM8606_BACKLIGHT_DEVS(_i) \ +{ \ + .name = "88pm860x-backlight", \ + .num_resources = 1, \ + .resources = &backlight_resources[_i], \ + .id = _i, \ +} + +static struct mfd_cell backlight_devs[] = { + PM8606_BACKLIGHT_DEVS(PM8606_BACKLIGHT1), + PM8606_BACKLIGHT_DEVS(PM8606_BACKLIGHT2), + PM8606_BACKLIGHT_DEVS(PM8606_BACKLIGHT3), +}; + +#define PM8606_LED_RESOURCE(_i, _x) \ +{ \ + .name = pm860x_led_name[_i], \ + .start = PM8606_##_x, \ + .end = PM8606_##_x, \ + .flags = IORESOURCE_IO, \ +} + +static struct resource led_resources[] = { + PM8606_LED_RESOURCE(PM8606_LED1_RED, RGB2B), + PM8606_LED_RESOURCE(PM8606_LED1_GREEN, RGB2C), + PM8606_LED_RESOURCE(PM8606_LED1_BLUE, RGB2D), + PM8606_LED_RESOURCE(PM8606_LED2_RED, RGB1B), + PM8606_LED_RESOURCE(PM8606_LED2_GREEN, RGB1C), + PM8606_LED_RESOURCE(PM8606_LED2_BLUE, RGB1D), +}; + +#define PM8606_LED_DEVS(_i) \ +{ \ + .name = "88pm860x-led", \ + .num_resources = 1, \ + .resources = &led_resources[_i], \ + .id = _i, \ +} + +static struct mfd_cell led_devs[] = { + PM8606_LED_DEVS(PM8606_LED1_RED), + PM8606_LED_DEVS(PM8606_LED1_GREEN), + PM8606_LED_DEVS(PM8606_LED1_BLUE), + PM8606_LED_DEVS(PM8606_LED2_RED), + PM8606_LED_DEVS(PM8606_LED2_GREEN), + PM8606_LED_DEVS(PM8606_LED2_BLUE), +}; + +static struct resource touch_resources[] = { + { + .start = PM8607_IRQ_PEN, + .end = PM8607_IRQ_PEN, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mfd_cell touch_devs[] = { + { + .name = "88pm860x-touch", + .num_resources = 1, + .resources = &touch_resources[0], + }, +}; #define PM8607_REG_RESOURCE(_start, _end) \ { \ @@ -25,7 +119,7 @@ .flags = IORESOURCE_IO, \ } -static struct resource pm8607_regulator_resources[] = { +static struct resource regulator_resources[] = { PM8607_REG_RESOURCE(BUCK1, BUCK1), PM8607_REG_RESOURCE(BUCK2, BUCK2), PM8607_REG_RESOURCE(BUCK3, BUCK3), @@ -47,10 +141,11 @@ static struct resource pm8607_regulator_resources[] = { { \ .name = "88pm8607-" #_name, \ .num_resources = 1, \ - .resources = &pm8607_regulator_resources[PM8607_ID_##_id], \ + .resources = ®ulator_resources[PM8607_ID_##_id], \ + .id = PM8607_ID_##_id, \ } -static struct mfd_cell pm8607_devs[] = { +static struct mfd_cell regulator_devs[] = { PM8607_REG_DEVS(buck1, BUCK1), PM8607_REG_DEVS(buck2, BUCK2), PM8607_REG_DEVS(buck3, BUCK3), @@ -192,6 +287,61 @@ int pm860x_free_irq(struct pm860x_chip *chip, int irq) } EXPORT_SYMBOL(pm860x_free_irq); +static int __devinit device_gpadc_init(struct pm860x_chip *chip, + struct pm860x_platform_data *pdata) +{ + struct i2c_client *i2c = (chip->id == CHIP_PM8607) ? chip->client \ + : chip->companion; + int use_gpadc = 0, data, ret; + + /* initialize GPADC without activating it */ + + if (pdata && pdata->touch) { + /* set GPADC MISC1 register */ + data = 0; + data |= (pdata->touch->gpadc_prebias << 1) + & PM8607_GPADC_PREBIAS_MASK; + data |= (pdata->touch->slot_cycle << 3) + & PM8607_GPADC_SLOT_CYCLE_MASK; + data |= (pdata->touch->off_scale << 5) + & PM8607_GPADC_OFF_SCALE_MASK; + data |= (pdata->touch->sw_cal << 7) + & PM8607_GPADC_SW_CAL_MASK; + if (data) { + ret = pm860x_reg_write(i2c, PM8607_GPADC_MISC1, data); + if (ret < 0) + goto out; + } + /* set tsi prebias time */ + if (pdata->touch->tsi_prebias) { + data = pdata->touch->tsi_prebias; + ret = pm860x_reg_write(i2c, PM8607_TSI_PREBIAS, data); + if (ret < 0) + goto out; + } + /* set prebias & prechg time of pen detect */ + data = 0; + data |= pdata->touch->pen_prebias & PM8607_PD_PREBIAS_MASK; + data |= (pdata->touch->pen_prechg << 5) + & PM8607_PD_PRECHG_MASK; + if (data) { + ret = pm860x_reg_write(i2c, PM8607_PD_PREBIAS, data); + if (ret < 0) + goto out; + } + + use_gpadc = 1; + } + + /* turn on GPADC */ + if (use_gpadc) { + ret = pm860x_set_bits(i2c, PM8607_GPADC_MISC1, + PM8607_GPADC_EN, PM8607_GPADC_EN); + } +out: + return ret; +} + static int __devinit device_irq_init(struct pm860x_chip *chip, struct pm860x_platform_data *pdata) { @@ -264,14 +414,40 @@ static void __devinit device_8606_init(struct pm860x_chip *chip, struct i2c_client *i2c, struct pm860x_platform_data *pdata) { + int ret; + + if (pdata && pdata->backlight) { + ret = mfd_add_devices(chip->dev, 0, &backlight_devs[0], + ARRAY_SIZE(backlight_devs), + &backlight_resources[0], 0); + if (ret < 0) { + dev_err(chip->dev, "Failed to add backlight " + "subdev\n"); + goto out_dev; + } + } + + if (pdata && pdata->led) { + ret = mfd_add_devices(chip->dev, 0, &led_devs[0], + ARRAY_SIZE(led_devs), + &led_resources[0], 0); + if (ret < 0) { + dev_err(chip->dev, "Failed to add led " + "subdev\n"); + goto out_dev; + } + } + return; +out_dev: + mfd_remove_devices(chip->dev); + device_irq_exit(chip); } static void __devinit device_8607_init(struct pm860x_chip *chip, struct i2c_client *i2c, struct pm860x_platform_data *pdata) { - int i, count, data; - int ret; + int data, ret; ret = pm860x_reg_read(i2c, PM8607_CHIP_ID); if (ret < 0) { @@ -311,19 +487,36 @@ static void __devinit device_8607_init(struct pm860x_chip *chip, goto out; } + ret = device_gpadc_init(chip, pdata); + if (ret < 0) + goto out; + ret = device_irq_init(chip, pdata); if (ret < 0) goto out; - count = ARRAY_SIZE(pm8607_devs); - for (i = 0; i < count; i++) { - ret = mfd_add_devices(chip->dev, i, &pm8607_devs[i], - 1, NULL, 0); - if (ret != 0) { - dev_err(chip->dev, "Failed to add subdevs\n"); - goto out; + ret = mfd_add_devices(chip->dev, 0, ®ulator_devs[0], + ARRAY_SIZE(regulator_devs), + ®ulator_resources[0], 0); + if (ret < 0) { + dev_err(chip->dev, "Failed to add regulator subdev\n"); + goto out_dev; + } + + if (pdata && pdata->touch) { + ret = mfd_add_devices(chip->dev, 0, &touch_devs[0], + ARRAY_SIZE(touch_devs), + &touch_resources[0], 0); + if (ret < 0) { + dev_err(chip->dev, "Failed to add touch " + "subdev\n"); + goto out_dev; } } + return; +out_dev: + mfd_remove_devices(chip->dev); + device_irq_exit(chip); out: return; } diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h index b4d6018ba0d6..d7edf11784f5 100644 --- a/include/linux/mfd/88pm860x.h +++ b/include/linux/mfd/88pm860x.h @@ -14,6 +14,8 @@ #include +#define MFD_NAME_SIZE (40) + enum { CHIP_INVALID = 0, CHIP_PM8606, @@ -21,6 +23,99 @@ enum { CHIP_MAX, }; +enum { + PM8606_ID_INVALID, + PM8606_ID_BACKLIGHT, + PM8606_ID_LED, + PM8606_ID_VIBRATOR, + PM8606_ID_TOUCH, + PM8606_ID_SOUND, + PM8606_ID_CHARGER, + PM8606_ID_MAX, +}; + +enum { + PM8606_BACKLIGHT1 = 0, + PM8606_BACKLIGHT2, + PM8606_BACKLIGHT3, +}; + +enum { + PM8606_LED1_RED = 0, + PM8606_LED1_GREEN, + PM8606_LED1_BLUE, + PM8606_LED2_RED, + PM8606_LED2_GREEN, + PM8606_LED2_BLUE, + PM8607_LED_VIBRATOR, +}; + + +/* 8606 Registers */ +#define PM8606_DCM_BOOST (0x00) +#define PM8606_PWM (0x01) + +/* Backlight Registers */ +#define PM8606_WLED1A (0x02) +#define PM8606_WLED1B (0x03) +#define PM8606_WLED2A (0x04) +#define PM8606_WLED2B (0x05) +#define PM8606_WLED3A (0x06) +#define PM8606_WLED3B (0x07) + +/* LED Registers */ +#define PM8606_RGB2A (0x08) +#define PM8606_RGB2B (0x09) +#define PM8606_RGB2C (0x0A) +#define PM8606_RGB2D (0x0B) +#define PM8606_RGB1A (0x0C) +#define PM8606_RGB1B (0x0D) +#define PM8606_RGB1C (0x0E) +#define PM8606_RGB1D (0x0F) + +#define PM8606_PREREGULATORA (0x10) +#define PM8606_PREREGULATORB (0x11) +#define PM8606_VIBRATORA (0x12) +#define PM8606_VIBRATORB (0x13) +#define PM8606_VCHG (0x14) +#define PM8606_VSYS (0x15) +#define PM8606_MISC (0x16) +#define PM8606_CHIP_ID (0x17) +#define PM8606_STATUS (0x18) +#define PM8606_FLAGS (0x19) +#define PM8606_PROTECTA (0x1A) +#define PM8606_PROTECTB (0x1B) +#define PM8606_PROTECTC (0x1C) + +/* Bit definitions of PM8606 registers */ +#define PM8606_DCM_500MA (0x0) /* current limit */ +#define PM8606_DCM_750MA (0x1) +#define PM8606_DCM_1000MA (0x2) +#define PM8606_DCM_1250MA (0x3) +#define PM8606_DCM_250MV (0x0 << 2) +#define PM8606_DCM_300MV (0x1 << 2) +#define PM8606_DCM_350MV (0x2 << 2) +#define PM8606_DCM_400MV (0x3 << 2) + +#define PM8606_PWM_31200HZ (0x0) +#define PM8606_PWM_15600HZ (0x1) +#define PM8606_PWM_7800HZ (0x2) +#define PM8606_PWM_3900HZ (0x3) +#define PM8606_PWM_1950HZ (0x4) +#define PM8606_PWM_976HZ (0x5) +#define PM8606_PWM_488HZ (0x6) +#define PM8606_PWM_244HZ (0x7) +#define PM8606_PWM_FREQ_MASK (0x7) + +#define PM8606_WLED_ON (1 << 0) +#define PM8606_WLED_CURRENT(x) ((x & 0x1F) << 1) + +#define PM8606_LED_CURRENT(x) (((x >> 2) & 0x07) << 5) + +#define PM8606_VSYS_EN (1 << 1) + +#define PM8606_MISC_OSC_EN (1 << 4) + enum { PM8607_ID_BUCK1 = 0, PM8607_ID_BUCK2, @@ -91,6 +186,21 @@ enum { #define PM8607_SUPPLIES_EN21 (0x33) #define PM8607_SUPPLIES_EN22 (0x34) +/* Vibrator Control Registers */ +#define PM8607_VIBRATOR_SET (0x28) +#define PM8607_VIBRATOR_PWM (0x29) + +/* GPADC Registers */ +#define PM8607_GP_BIAS1 (0x4F) +#define PM8607_MEAS_EN1 (0x50) +#define PM8607_MEAS_EN2 (0x51) +#define PM8607_MEAS_EN3 (0x52) +#define PM8607_MEAS_OFF_TIME1 (0x53) +#define PM8607_MEAS_OFF_TIME2 (0x54) +#define PM8607_TSI_PREBIAS (0x55) /* prebias time */ +#define PM8607_PD_PREBIAS (0x56) /* prebias time */ +#define PM8607_GPADC_MISC1 (0x57) + /* RTC Control Registers */ #define PM8607_RTC1 (0xA0) #define PM8607_RTC_COUNTER1 (0xA1) @@ -140,6 +250,16 @@ enum { #define PM8607_B0_MISC1_PI2C (1 << 3) #define PM8607_B0_MISC1_RESET (1 << 6) +/* bits definitions of GPADC */ +#define PM8607_GPADC_EN (1 << 0) +#define PM8607_GPADC_PREBIAS_MASK (3 << 1) +#define PM8607_GPADC_SLOT_CYCLE_MASK (3 << 3) /* slow mode */ +#define PM8607_GPADC_OFF_SCALE_MASK (3 << 5) /* GP sleep mode */ +#define PM8607_GPADC_SW_CAL_MASK (1 << 7) + +#define PM8607_PD_PREBIAS_MASK (0x1F << 0) +#define PM8607_PD_PRECHG_MASK (7 << 5) + /* Interrupt Number in 88PM8607 */ enum { PM8607_IRQ_ONKEY = 0, @@ -202,13 +322,44 @@ enum { PI2C_PORT, }; +struct pm860x_backlight_pdata { + int id; + int pwm; + int iset; + unsigned long flags; +}; + +struct pm860x_led_pdata { + int id; + int iset; + unsigned long flags; +}; + +struct pm860x_touch_pdata { + int gpadc_prebias; + int slot_cycle; + int off_scale; + int sw_cal; + int tsi_prebias; /* time, slot */ + int pen_prebias; /* time, slot */ + int pen_prechg; /* time, slot */ + unsigned long flags; +}; + struct pm860x_platform_data { + struct pm860x_backlight_pdata *backlight; + struct pm860x_led_pdata *led; + struct pm860x_touch_pdata *touch; + unsigned short companion_addr; /* I2C address of companion chip */ int i2c_port; /* Controlled by GI2C or PI2C */ int irq_mode; /* Clear interrupt by read/write(0/1) */ struct regulator_init_data *regulator[PM8607_MAX_REGULATOR]; }; +extern char pm860x_backlight_name[][MFD_NAME_SIZE]; +extern char pm860x_led_name[][MFD_NAME_SIZE]; + extern int pm860x_reg_read(struct i2c_client *, int); extern int pm860x_reg_write(struct i2c_client *, int, unsigned char); extern int pm860x_bulk_read(struct i2c_client *, int, int, unsigned char *); -- cgit v1.2.3 From d07e8bf83fd71567aaf9c27c3b133ab3cf8f3c4c Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 9 Nov 2009 12:41:07 -0500 Subject: backlight: Enable backlight in 88pm860x At most, three backlight device can be supported in 88pm860x driver. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/video/backlight/88pm860x_bl.c | 304 ++++++++++++++++++++++++++++++++++ drivers/video/backlight/Kconfig | 6 + drivers/video/backlight/Makefile | 1 + 3 files changed, 311 insertions(+) create mode 100644 drivers/video/backlight/88pm860x_bl.c (limited to 'drivers') diff --git a/drivers/video/backlight/88pm860x_bl.c b/drivers/video/backlight/88pm860x_bl.c new file mode 100644 index 000000000000..b8f705cca438 --- /dev/null +++ b/drivers/video/backlight/88pm860x_bl.c @@ -0,0 +1,304 @@ +/* + * Backlight driver for Marvell Semiconductor 88PM8606 + * + * Copyright (C) 2009 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MAX_BRIGHTNESS (0xFF) +#define MIN_BRIGHTNESS (0) + +#define CURRENT_MASK (0x1F << 1) + +struct pm860x_backlight_data { + struct pm860x_chip *chip; + struct i2c_client *i2c; + int current_brightness; + int port; + int pwm; + int iset; +}; + +static inline int wled_a(int port) +{ + int ret; + + ret = ((port - PM8606_BACKLIGHT1) << 1) + 2; + return ret; +} + +static inline int wled_b(int port) +{ + int ret; + + ret = ((port - PM8606_BACKLIGHT1) << 1) + 3; + return ret; +} + +/* WLED2 & WLED3 share the same IDC */ +static inline int wled_idc(int port) +{ + int ret; + + switch (port) { + case PM8606_BACKLIGHT1: + case PM8606_BACKLIGHT2: + ret = ((port - PM8606_BACKLIGHT1) << 1) + 3; + break; + case PM8606_BACKLIGHT3: + default: + ret = ((port - PM8606_BACKLIGHT2) << 1) + 3; + break; + } + return ret; +} + +static int pm860x_backlight_set(struct backlight_device *bl, int brightness) +{ + struct pm860x_backlight_data *data = bl_get_data(bl); + struct pm860x_chip *chip = data->chip; + unsigned char value; + int ret; + + if (brightness > MAX_BRIGHTNESS) + value = MAX_BRIGHTNESS; + else + value = brightness; + + ret = pm860x_reg_write(data->i2c, wled_a(data->port), value); + if (ret < 0) + goto out; + + if ((data->current_brightness == 0) && brightness) { + if (data->iset) { + ret = pm860x_set_bits(data->i2c, wled_idc(data->port), + CURRENT_MASK, data->iset); + if (ret < 0) + goto out; + } + if (data->pwm) { + ret = pm860x_set_bits(data->i2c, PM8606_PWM, + PM8606_PWM_FREQ_MASK, data->pwm); + if (ret < 0) + goto out; + } + if (brightness == MAX_BRIGHTNESS) { + /* set WLED_ON bit as 100% */ + ret = pm860x_set_bits(data->i2c, wled_b(data->port), + PM8606_WLED_ON, PM8606_WLED_ON); + } + } else { + if (brightness == MAX_BRIGHTNESS) { + /* set WLED_ON bit as 100% */ + ret = pm860x_set_bits(data->i2c, wled_b(data->port), + PM8606_WLED_ON, PM8606_WLED_ON); + } else { + /* clear WLED_ON bit since it's not 100% */ + ret = pm860x_set_bits(data->i2c, wled_b(data->port), + PM8606_WLED_ON, 0); + } + } + if (ret < 0) + goto out; + + dev_dbg(chip->dev, "set brightness %d\n", value); + data->current_brightness = value; + return 0; +out: + dev_dbg(chip->dev, "set brightness %d failure with return " + "value:%d\n", value, ret); + return ret; +} + +static int pm860x_backlight_update_status(struct backlight_device *bl) +{ + int brightness = bl->props.brightness; + + if (bl->props.power != FB_BLANK_UNBLANK) + brightness = 0; + + if (bl->props.fb_blank != FB_BLANK_UNBLANK) + brightness = 0; + + if (bl->props.state & BL_CORE_SUSPENDED) + brightness = 0; + + return pm860x_backlight_set(bl, brightness); +} + +static int pm860x_backlight_get_brightness(struct backlight_device *bl) +{ + struct pm860x_backlight_data *data = bl_get_data(bl); + struct pm860x_chip *chip = data->chip; + int ret; + + ret = pm860x_reg_read(data->i2c, wled_a(data->port)); + if (ret < 0) + goto out; + data->current_brightness = ret; + dev_dbg(chip->dev, "get brightness %d\n", data->current_brightness); + return data->current_brightness; +out: + return -EINVAL; +} + +static struct backlight_ops pm860x_backlight_ops = { + .options = BL_CORE_SUSPENDRESUME, + .update_status = pm860x_backlight_update_status, + .get_brightness = pm860x_backlight_get_brightness, +}; + +static int __check_device(struct pm860x_backlight_pdata *pdata, char *name) +{ + struct pm860x_backlight_pdata *p = pdata; + int ret = -EINVAL; + + while (p && p->id) { + if ((p->id != PM8606_ID_BACKLIGHT) || (p->flags < 0)) + break; + + if (!strncmp(name, pm860x_backlight_name[p->flags], + MFD_NAME_SIZE)) { + ret = (int)p->flags; + break; + } + p++; + } + return ret; +} + +static int pm860x_backlight_probe(struct platform_device *pdev) +{ + struct pm860x_chip *chip = dev_get_drvdata(pdev->dev.parent); + struct pm860x_platform_data *pm860x_pdata; + struct pm860x_backlight_pdata *pdata = NULL; + struct pm860x_backlight_data *data; + struct backlight_device *bl; + struct resource *res; + unsigned char value; + char name[MFD_NAME_SIZE]; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_IO, 0); + if (res == NULL) { + dev_err(&pdev->dev, "No I/O resource!\n"); + return -EINVAL; + } + + if (pdev->dev.parent->platform_data) { + pm860x_pdata = pdev->dev.parent->platform_data; + pdata = pm860x_pdata->backlight; + } + if (pdata == NULL) { + dev_err(&pdev->dev, "platform data isn't assigned to " + "backlight\n"); + return -EINVAL; + } + + data = kzalloc(sizeof(struct pm860x_backlight_data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + strncpy(name, res->name, MFD_NAME_SIZE); + data->chip = chip; + data->i2c = (chip->id == CHIP_PM8606) ? chip->client \ + : chip->companion; + data->current_brightness = MAX_BRIGHTNESS; + data->pwm = pdata->pwm; + data->iset = pdata->iset; + data->port = __check_device(pdata, name); + if (data->port < 0) { + dev_err(&pdev->dev, "wrong platform data is assigned"); + return -EINVAL; + } + + bl = backlight_device_register(name, &pdev->dev, data, + &pm860x_backlight_ops); + if (IS_ERR(bl)) { + dev_err(&pdev->dev, "failed to register backlight\n"); + kfree(data); + return PTR_ERR(bl); + } + bl->props.max_brightness = MAX_BRIGHTNESS; + bl->props.brightness = MAX_BRIGHTNESS; + + platform_set_drvdata(pdev, bl); + + /* Enable reference VSYS */ + ret = pm860x_reg_read(data->i2c, PM8606_VSYS); + if (ret < 0) + goto out; + if ((ret & PM8606_VSYS_EN) == 0) { + value = ret | PM8606_VSYS_EN; + ret = pm860x_reg_write(data->i2c, PM8606_VSYS, value); + if (ret < 0) + goto out; + } + /* Enable reference OSC */ + ret = pm860x_reg_read(data->i2c, PM8606_MISC); + if (ret < 0) + goto out; + if ((ret & PM8606_MISC_OSC_EN) == 0) { + value = ret | PM8606_MISC_OSC_EN; + ret = pm860x_reg_write(data->i2c, PM8606_MISC, value); + if (ret < 0) + goto out; + } + /* read current backlight */ + ret = pm860x_backlight_get_brightness(bl); + if (ret < 0) + goto out; + + backlight_update_status(bl); + return 0; +out: + kfree(data); + return ret; +} + +static int pm860x_backlight_remove(struct platform_device *pdev) +{ + struct backlight_device *bl = platform_get_drvdata(pdev); + struct pm860x_backlight_data *data = bl_get_data(bl); + + backlight_device_unregister(bl); + kfree(data); + return 0; +} + +static struct platform_driver pm860x_backlight_driver = { + .driver = { + .name = "88pm860x-backlight", + .owner = THIS_MODULE, + }, + .probe = pm860x_backlight_probe, + .remove = pm860x_backlight_remove, +}; + +static int __init pm860x_backlight_init(void) +{ + return platform_driver_register(&pm860x_backlight_driver); +} +module_init(pm860x_backlight_init); + +static void __exit pm860x_backlight_exit(void) +{ + platform_driver_unregister(&pm860x_backlight_driver); +} +module_exit(pm860x_backlight_exit); + +MODULE_DESCRIPTION("Backlight Driver for Marvell Semiconductor 88PM8606"); +MODULE_AUTHOR("Haojian Zhuang "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:88pm860x-backlight"); diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig index 09bfa9662e4d..96a6b3060ac0 100644 --- a/drivers/video/backlight/Kconfig +++ b/drivers/video/backlight/Kconfig @@ -262,3 +262,9 @@ config BACKLIGHT_ADP5520 To compile this driver as a module, choose M here: the module will be called adp5520_bl. +config BACKLIGHT_88PM860X + tristate "Backlight Driver for 88PM8606 using WLED" + depends on BACKLIGHT_CLASS_DEVICE && MFD_88PM860X + help + Say Y to enable the backlight driver for Marvell 88PM8606. + diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile index 9a405548874c..802d467b08c0 100644 --- a/drivers/video/backlight/Makefile +++ b/drivers/video/backlight/Makefile @@ -28,4 +28,5 @@ obj-$(CONFIG_BACKLIGHT_SAHARA) += kb3886_bl.o obj-$(CONFIG_BACKLIGHT_WM831X) += wm831x_bl.o obj-$(CONFIG_BACKLIGHT_ADX) += adx_bl.o obj-$(CONFIG_BACKLIGHT_ADP5520) += adp5520_bl.o +obj-$(CONFIG_BACKLIGHT_88PM860X) += 88pm860x_bl.o -- cgit v1.2.3 From 0a2f915b405ac1a8d19d9b7cf7873f26ba682a24 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 6 Jan 2010 17:10:09 -0500 Subject: led: Enable led in 88pm860x Enable led sub device in Marvell 88PM860x. Two LED arrays can be supported. Each LED array can be used for R,G,B leds. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/leds/Kconfig | 7 + drivers/leds/Makefile | 1 + drivers/leds/leds-88pm860x.c | 325 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 333 insertions(+) create mode 100644 drivers/leds/leds-88pm860x.c (limited to 'drivers') diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 8a0e1ec95e4a..e0b64312e66a 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -17,6 +17,13 @@ config LEDS_CLASS comment "LED drivers" +config LEDS_88PM860X + tristate "LED Support for Marvell 88PM860x PMIC" + depends on LEDS_CLASS && MFD_88PM860X + help + This option enables support for on-chip LED drivers found on Marvell + Semiconductor 88PM8606 PMIC. + config LEDS_ATMEL_PWM tristate "LED Support using Atmel PWM outputs" depends on LEDS_CLASS && ATMEL_PWM diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 9e63869d7c0d..d76fb32b77c0 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_LEDS_CLASS) += led-class.o obj-$(CONFIG_LEDS_TRIGGERS) += led-triggers.o # LED Platform Drivers +obj-$(CONFIG_LEDS_88PM860X) += leds-88pm860x.o obj-$(CONFIG_LEDS_ATMEL_PWM) += leds-atmel-pwm.o obj-$(CONFIG_LEDS_BD2802) += leds-bd2802.o obj-$(CONFIG_LEDS_LOCOMO) += leds-locomo.o diff --git a/drivers/leds/leds-88pm860x.c b/drivers/leds/leds-88pm860x.c new file mode 100644 index 000000000000..d196073a6aeb --- /dev/null +++ b/drivers/leds/leds-88pm860x.c @@ -0,0 +1,325 @@ +/* + * LED driver for Marvell 88PM860x + * + * Copyright (C) 2009 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#define LED_PWM_SHIFT (3) +#define LED_PWM_MASK (0x1F) +#define LED_CURRENT_MASK (0x07 << 5) + +#define LED_BLINK_ON_MASK (0x07) +#define LED_BLINK_PERIOD_MASK (0x0F << 3) +#define LED_BLINK_MASK (0x7F) + +#define LED_BLINK_ON(x) ((x & 0x7) * 66 + 66) +#define LED_BLINK_PERIOD(x) ((x & 0xF) * 530 + 930) +#define LED_BLINK_ON_MIN LED_BLINK_ON(0) +#define LED_BLINK_ON_MAX LED_BLINK_ON(0x7) +#define LED_BLINK_PERIOD_MIN LED_BLINK_PERIOD(0) +#define LED_BLINK_PERIOD_MAX LED_BLINK_PERIOD(0xE) +#define LED_TO_ON(x) ((x - 66) / 66) +#define LED_TO_PERIOD(x) ((x - 930) / 530) + +#define LED1_BLINK_EN (1 << 1) +#define LED2_BLINK_EN (1 << 2) + +enum { + SET_BRIGHTNESS, + SET_BLINK, +}; + +struct pm860x_led { + struct led_classdev cdev; + struct i2c_client *i2c; + struct work_struct work; + struct pm860x_chip *chip; + struct mutex lock; + char name[MFD_NAME_SIZE]; + + int port; + int iset; + int command; + int offset; + unsigned char brightness; + unsigned char current_brightness; + + int blink_data; + int blink_time; + int blink_on; + int blink_off; +}; + +/* return offset of color register */ +static inline int __led_off(int port) +{ + int ret = -EINVAL; + + switch (port) { + case PM8606_LED1_RED: + case PM8606_LED1_GREEN: + case PM8606_LED1_BLUE: + ret = port - PM8606_LED1_RED + PM8606_RGB1B; + break; + case PM8606_LED2_RED: + case PM8606_LED2_GREEN: + case PM8606_LED2_BLUE: + ret = port - PM8606_LED2_RED + PM8606_RGB2B; + break; + } + return ret; +} + +/* return offset of blink register */ +static inline int __blink_off(int port) +{ + int ret = -EINVAL; + + switch (port) { + case PM8606_LED1_RED: + case PM8606_LED1_GREEN: + case PM8606_LED1_BLUE: + ret = PM8606_RGB1A; + case PM8606_LED2_RED: + case PM8606_LED2_GREEN: + case PM8606_LED2_BLUE: + ret = PM8606_RGB2A; + } + return ret; +} + +static inline int __blink_ctl_mask(int port) +{ + int ret = -EINVAL; + + switch (port) { + case PM8606_LED1_RED: + case PM8606_LED1_GREEN: + case PM8606_LED1_BLUE: + ret = LED1_BLINK_EN; + break; + case PM8606_LED2_RED: + case PM8606_LED2_GREEN: + case PM8606_LED2_BLUE: + ret = LED2_BLINK_EN; + break; + } + return ret; +} + +static int __led_set(struct pm860x_led *led, int command) +{ + struct pm860x_chip *chip = led->chip; + int mask, ret; + + mutex_lock(&led->lock); + switch (command) { + case SET_BRIGHTNESS: + if ((led->current_brightness == 0) && led->brightness) { + if (led->iset) { + ret = pm860x_set_bits(led->i2c, led->offset, + LED_CURRENT_MASK, led->iset); + if (ret < 0) + goto out; + } + } else if (led->brightness == 0) { + ret = pm860x_set_bits(led->i2c, led->offset, + LED_CURRENT_MASK, 0); + if (ret < 0) + goto out; + } + ret = pm860x_set_bits(led->i2c, led->offset, LED_PWM_MASK, + led->brightness); + if (ret < 0) + goto out; + led->current_brightness = led->brightness; + dev_dbg(chip->dev, "Update LED. (reg:%d, brightness:%d)\n", + led->offset, led->brightness); + break; + case SET_BLINK: + ret = pm860x_set_bits(led->i2c, led->offset, + LED_BLINK_MASK, led->blink_data); + if (ret < 0) + goto out; + + mask = __blink_ctl_mask(led->port); + ret = pm860x_set_bits(led->i2c, PM8606_WLED3B, mask, mask); + if (ret < 0) + goto out; + dev_dbg(chip->dev, "LED blink delay on:%dms, delay off:%dms\n", + led->blink_on, led->blink_off); + break; + } +out: + mutex_unlock(&led->lock); + return 0; +} + +static void pm860x_led_work(struct work_struct *work) +{ + struct pm860x_led *led; + + led = container_of(work, struct pm860x_led, work); + __led_set(led, led->command); +} + +static void pm860x_led_set(struct led_classdev *cdev, + enum led_brightness value) +{ + struct pm860x_led *data = container_of(cdev, struct pm860x_led, cdev); + + data->offset = __led_off(data->port); + data->brightness = value >> 3; + data->command = SET_BRIGHTNESS; + schedule_work(&data->work); +} + +static int pm860x_led_blink(struct led_classdev *cdev, + unsigned long *delay_on, + unsigned long *delay_off) +{ + struct pm860x_led *data = container_of(cdev, struct pm860x_led, cdev); + int period, on; + + on = *delay_on; + if ((on < LED_BLINK_ON_MIN) || (on > LED_BLINK_ON_MAX)) + return -EINVAL; + + on = LED_TO_ON(on); + on = LED_BLINK_ON(on); + + period = on + *delay_off; + if ((period < LED_BLINK_PERIOD_MIN) || (period > LED_BLINK_PERIOD_MAX)) + return -EINVAL; + period = LED_TO_PERIOD(period); + period = LED_BLINK_PERIOD(period); + + data->offset = __blink_off(data->port); + data->blink_on = on; + data->blink_off = period - data->blink_on; + data->blink_data = (period << 3) | data->blink_on; + data->command = SET_BLINK; + schedule_work(&data->work); + + return 0; +} + +static int __check_device(struct pm860x_led_pdata *pdata, char *name) +{ + struct pm860x_led_pdata *p = pdata; + int ret = -EINVAL; + + while (p && p->id) { + if ((p->id != PM8606_ID_LED) || (p->flags < 0)) + break; + + if (!strncmp(name, pm860x_led_name[p->flags], + MFD_NAME_SIZE)) { + ret = (int)p->flags; + break; + } + p++; + } + return ret; +} + +static int pm860x_led_probe(struct platform_device *pdev) +{ + struct pm860x_chip *chip = dev_get_drvdata(pdev->dev.parent); + struct pm860x_platform_data *pm860x_pdata; + struct pm860x_led_pdata *pdata; + struct pm860x_led *data; + struct resource *res; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_IO, 0); + if (res == NULL) { + dev_err(&pdev->dev, "No I/O resource!\n"); + return -EINVAL; + } + + if (pdev->dev.parent->platform_data) { + pm860x_pdata = pdev->dev.parent->platform_data; + pdata = pm860x_pdata->led; + } else + pdata = NULL; + + data = kzalloc(sizeof(struct pm860x_led), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + strncpy(data->name, res->name, MFD_NAME_SIZE); + dev_set_drvdata(&pdev->dev, data); + data->chip = chip; + data->i2c = (chip->id == CHIP_PM8606) ? chip->client : chip->companion; + data->iset = pdata->iset; + data->port = __check_device(pdata, data->name); + if (data->port < 0) + return -EINVAL; + + data->current_brightness = 0; + data->cdev.name = data->name; + data->cdev.brightness_set = pm860x_led_set; + data->cdev.blink_set = pm860x_led_blink; + mutex_init(&data->lock); + INIT_WORK(&data->work, pm860x_led_work); + + ret = led_classdev_register(chip->dev, &data->cdev); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to register LED: %d\n", ret); + goto out; + } + return 0; +out: + kfree(data); + return ret; +} + +static int pm860x_led_remove(struct platform_device *pdev) +{ + struct pm860x_led *data = platform_get_drvdata(pdev); + + led_classdev_unregister(&data->cdev); + kfree(data); + + return 0; +} + +static struct platform_driver pm860x_led_driver = { + .driver = { + .name = "88pm860x-led", + .owner = THIS_MODULE, + }, + .probe = pm860x_led_probe, + .remove = pm860x_led_remove, +}; + +static int __devinit pm860x_led_init(void) +{ + return platform_driver_register(&pm860x_led_driver); +} +module_init(pm860x_led_init); + +static void __devexit pm860x_led_exit(void) +{ + platform_driver_unregister(&pm860x_led_driver); +} +module_exit(pm860x_led_exit); + +MODULE_DESCRIPTION("LED driver for Marvell PM860x"); +MODULE_AUTHOR("Haojian Zhuang "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:88pm860x-led"); -- cgit v1.2.3 From 866a98ae6e1a9768cd25fe1185481569c7e4b4a9 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Tue, 15 Dec 2009 16:06:17 -0500 Subject: input: Enable touch on 88pm860x Enable touchscreen driver for the 88pm860x multi function core. Signed-off-by: Haojian Zhuang Acked-by: Dmitry Torokhov Signed-off-by: Samuel Ortiz --- drivers/input/touchscreen/88pm860x-ts.c | 241 ++++++++++++++++++++++++++++++++ drivers/input/touchscreen/Kconfig | 12 ++ drivers/input/touchscreen/Makefile | 1 + include/linux/mfd/88pm860x.h | 1 + 4 files changed, 255 insertions(+) create mode 100644 drivers/input/touchscreen/88pm860x-ts.c (limited to 'drivers') diff --git a/drivers/input/touchscreen/88pm860x-ts.c b/drivers/input/touchscreen/88pm860x-ts.c new file mode 100644 index 000000000000..56254d2a1f6e --- /dev/null +++ b/drivers/input/touchscreen/88pm860x-ts.c @@ -0,0 +1,241 @@ +/* + * Touchscreen driver for Marvell 88PM860x + * + * Copyright (C) 2009 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include + +#define MEAS_LEN (8) +#define ACCURATE_BIT (12) + +/* touch register */ +#define MEAS_EN3 (0x52) + +#define MEAS_TSIX_1 (0x8D) +#define MEAS_TSIX_2 (0x8E) +#define MEAS_TSIY_1 (0x8F) +#define MEAS_TSIY_2 (0x90) +#define MEAS_TSIZ1_1 (0x91) +#define MEAS_TSIZ1_2 (0x92) +#define MEAS_TSIZ2_1 (0x93) +#define MEAS_TSIZ2_2 (0x94) + +/* bit definitions of touch */ +#define MEAS_PD_EN (1 << 3) +#define MEAS_TSIX_EN (1 << 4) +#define MEAS_TSIY_EN (1 << 5) +#define MEAS_TSIZ1_EN (1 << 6) +#define MEAS_TSIZ2_EN (1 << 7) + +struct pm860x_touch { + struct input_dev *idev; + struct i2c_client *i2c; + struct pm860x_chip *chip; + int irq; + int res_x; /* resistor of Xplate */ +}; + +static irqreturn_t pm860x_touch_handler(int irq, void *data) +{ + struct pm860x_touch *touch = data; + struct pm860x_chip *chip = touch->chip; + unsigned char buf[MEAS_LEN]; + int x, y, pen_down; + int z1, z2, rt = 0; + int ret; + + pm860x_mask_irq(chip, irq); + ret = pm860x_bulk_read(touch->i2c, MEAS_TSIX_1, MEAS_LEN, buf); + if (ret < 0) + goto out; + + pen_down = buf[1] & (1 << 6); + x = ((buf[0] & 0xFF) << 4) | (buf[1] & 0x0F); + y = ((buf[2] & 0xFF) << 4) | (buf[3] & 0x0F); + z1 = ((buf[4] & 0xFF) << 4) | (buf[5] & 0x0F); + z2 = ((buf[6] & 0xFF) << 4) | (buf[7] & 0x0F); + + if (pen_down) { + if ((x != 0) && (z1 != 0) && (touch->res_x != 0)) { + rt = z2 / z1 - 1; + rt = (rt * touch->res_x * x) >> ACCURATE_BIT; + dev_dbg(chip->dev, "z1:%d, z2:%d, rt:%d\n", + z1, z2, rt); + } + input_report_abs(touch->idev, ABS_X, x); + input_report_abs(touch->idev, ABS_Y, y); + input_report_abs(touch->idev, ABS_PRESSURE, rt); + input_report_key(touch->idev, BTN_TOUCH, 1); + dev_dbg(chip->dev, "pen down at [%d, %d].\n", x, y); + } else { + input_report_abs(touch->idev, ABS_PRESSURE, 0); + input_report_key(touch->idev, BTN_TOUCH, 0); + dev_dbg(chip->dev, "pen release\n"); + } + input_sync(touch->idev); + pm860x_unmask_irq(chip, irq); + +out: + return IRQ_HANDLED; +} + +static int pm860x_touch_open(struct input_dev *dev) +{ + struct pm860x_touch *touch = input_get_drvdata(dev); + struct pm860x_chip *chip = touch->chip; + int data, ret; + + data = MEAS_PD_EN | MEAS_TSIX_EN | MEAS_TSIY_EN + | MEAS_TSIZ1_EN | MEAS_TSIZ2_EN; + ret = pm860x_set_bits(touch->i2c, MEAS_EN3, data, data); + if (ret < 0) + goto out; + pm860x_unmask_irq(chip, touch->irq); + return 0; +out: + return ret; +} + +static void pm860x_touch_close(struct input_dev *dev) +{ + struct pm860x_touch *touch = input_get_drvdata(dev); + struct pm860x_chip *chip = touch->chip; + int data; + + data = MEAS_PD_EN | MEAS_TSIX_EN | MEAS_TSIY_EN + | MEAS_TSIZ1_EN | MEAS_TSIZ2_EN; + pm860x_set_bits(touch->i2c, MEAS_EN3, data, 0); + pm860x_mask_irq(chip, touch->irq); +} + +static int __devinit pm860x_touch_probe(struct platform_device *pdev) +{ + struct pm860x_chip *chip = dev_get_drvdata(pdev->dev.parent); + struct pm860x_platform_data *pm860x_pdata = \ + pdev->dev.parent->platform_data; + struct pm860x_touch_pdata *pdata = NULL; + struct pm860x_touch *touch; + int irq, ret; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "No IRQ resource!\n"); + return -EINVAL; + } + + if (!pm860x_pdata) { + dev_err(&pdev->dev, "platform data is missing\n"); + return -EINVAL; + } + + pdata = pm860x_pdata->touch; + if (!pdata) { + dev_err(&pdev->dev, "touchscreen data is missing\n"); + return -EINVAL; + } + + touch = kzalloc(sizeof(struct pm860x_touch), GFP_KERNEL); + if (touch == NULL) + return -ENOMEM; + dev_set_drvdata(&pdev->dev, touch); + + touch->idev = input_allocate_device(); + if (touch->idev == NULL) { + dev_err(&pdev->dev, "Failed to allocate input device!\n"); + ret = -ENOMEM; + goto out; + } + + touch->idev->name = "88pm860x-touch"; + touch->idev->phys = "88pm860x/input0"; + touch->idev->id.bustype = BUS_I2C; + touch->idev->dev.parent = &pdev->dev; + touch->idev->open = pm860x_touch_open; + touch->idev->close = pm860x_touch_close; + touch->chip = chip; + touch->i2c = (chip->id == CHIP_PM8607) ? chip->client : chip->companion; + touch->irq = irq; + touch->res_x = pdata->res_x; + input_set_drvdata(touch->idev, touch); + + ret = pm860x_request_irq(chip, irq, pm860x_touch_handler, touch); + if (ret < 0) + goto out_irq; + + __set_bit(EV_ABS, touch->idev->evbit); + __set_bit(ABS_X, touch->idev->absbit); + __set_bit(ABS_Y, touch->idev->absbit); + __set_bit(ABS_PRESSURE, touch->idev->absbit); + __set_bit(EV_SYN, touch->idev->evbit); + __set_bit(EV_KEY, touch->idev->evbit); + __set_bit(BTN_TOUCH, touch->idev->keybit); + + input_set_abs_params(touch->idev, ABS_X, 0, 1 << ACCURATE_BIT, 0, 0); + input_set_abs_params(touch->idev, ABS_Y, 0, 1 << ACCURATE_BIT, 0, 0); + input_set_abs_params(touch->idev, ABS_PRESSURE, 0, 1 << ACCURATE_BIT, + 0, 0); + + ret = input_register_device(touch->idev); + if (ret < 0) { + dev_err(chip->dev, "Failed to register touch!\n"); + goto out_rg; + } + + platform_set_drvdata(pdev, touch); + return 0; +out_rg: + pm860x_free_irq(chip, irq); +out_irq: + input_free_device(touch->idev); +out: + kfree(touch); + return ret; +} + +static int __devexit pm860x_touch_remove(struct platform_device *pdev) +{ + struct pm860x_touch *touch = platform_get_drvdata(pdev); + + input_unregister_device(touch->idev); + pm860x_free_irq(touch->chip, touch->irq); + platform_set_drvdata(pdev, NULL); + kfree(touch); + return 0; +} + +static struct platform_driver pm860x_touch_driver = { + .driver = { + .name = "88pm860x-touch", + .owner = THIS_MODULE, + }, + .probe = pm860x_touch_probe, + .remove = __devexit_p(pm860x_touch_remove), +}; + +static int __init pm860x_touch_init(void) +{ + return platform_driver_register(&pm860x_touch_driver); +} +module_init(pm860x_touch_init); + +static void __exit pm860x_touch_exit(void) +{ + platform_driver_unregister(&pm860x_touch_driver); +} +module_exit(pm860x_touch_exit); + +MODULE_DESCRIPTION("Touchscreen driver for Marvell Semiconductor 88PM860x"); +MODULE_AUTHOR("Haojian Zhuang "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:88pm860x-touch"); + diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 6457e060ae49..7208654a94ae 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -11,6 +11,18 @@ menuconfig INPUT_TOUCHSCREEN if INPUT_TOUCHSCREEN +config TOUCHSCREEN_88PM860X + tristate "Marvell 88PM860x touchscreen" + depends on MFD_88PM860X + help + Say Y here if you have a 88PM860x PMIC and want to enable + support for the built-in touchscreen. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called 88pm860x-ts. + config TOUCHSCREEN_ADS7846 tristate "ADS7846/TSC2046 and ADS7843 based touchscreens" depends on SPI_MASTER diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index d61a3b4def9a..7fef7d5cca23 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -6,6 +6,7 @@ wm97xx-ts-y := wm97xx-core.o +obj-$(CONFIG_TOUCHSCREEN_88PM860X) += 88pm860x-ts.o obj-$(CONFIG_TOUCHSCREEN_AD7877) += ad7877.o obj-$(CONFIG_TOUCHSCREEN_AD7879) += ad7879.o obj-$(CONFIG_TOUCHSCREEN_ADS7846) += ads7846.o diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h index d7edf11784f5..80bc82a7ac96 100644 --- a/include/linux/mfd/88pm860x.h +++ b/include/linux/mfd/88pm860x.h @@ -343,6 +343,7 @@ struct pm860x_touch_pdata { int tsi_prebias; /* time, slot */ int pen_prebias; /* time, slot */ int pen_prechg; /* time, slot */ + int res_x; /* resistor of Xplate */ unsigned long flags; }; -- cgit v1.2.3 From 34a4b2391e9fbd12de9817de4ae409528bd7d7b6 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Thu, 10 Dec 2009 06:06:17 -0500 Subject: regulator: Unsupport 88pm8607 A0 and A1 Remove the support 88PM8607 A0/A1 stepping. There's some register definition changes in B0 stepping. It can make software more efficient. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/regulator/88pm8607.c | 290 ++++++++++++------------------------------- 1 file changed, 77 insertions(+), 213 deletions(-) (limited to 'drivers') diff --git a/drivers/regulator/88pm8607.c b/drivers/regulator/88pm8607.c index 97897a6bf4f3..5fb83e2ced25 100644 --- a/drivers/regulator/88pm8607.c +++ b/drivers/regulator/88pm8607.c @@ -48,7 +48,6 @@ static inline int check_range(struct pm8607_regulator_info *info, static int pm8607_list_voltage(struct regulator_dev *rdev, unsigned index) { struct pm8607_regulator_info *info = rdev_get_drvdata(rdev); - uint8_t chip_id = info->chip->chip_version; int ret = -EINVAL; switch (info->desc.id) { @@ -90,79 +89,29 @@ static int pm8607_list_voltage(struct regulator_dev *rdev, unsigned index) case PM8607_ID_LDO2: case PM8607_ID_LDO3: case PM8607_ID_LDO9: - switch (chip_id) { - case PM8607_CHIP_A0: - case PM8607_CHIP_A1: - ret = (index < 3) ? (index * 50000 + 1800000) : - ((index < 8) ? (index * 50000 + 2550000) : - -EINVAL); - break; - case PM8607_CHIP_B0: - ret = (index < 3) ? (index * 50000 + 1800000) : - ((index < 7) ? (index * 50000 + 2550000) : - 3300000); - break; - } + ret = (index < 3) ? (index * 50000 + 1800000) : + ((index < 7) ? (index * 50000 + 2550000) : + 3300000); break; case PM8607_ID_LDO4: - switch (chip_id) { - case PM8607_CHIP_A0: - case PM8607_CHIP_A1: - ret = (index < 3) ? (index * 50000 + 1800000) : - ((index < 8) ? (index * 50000 + 2550000) : - -EINVAL); - break; - case PM8607_CHIP_B0: - ret = (index < 3) ? (index * 50000 + 1800000) : - ((index < 6) ? (index * 50000 + 2550000) : - ((index == 6) ? 2900000 : 3300000)); - break; - } + ret = (index < 3) ? (index * 50000 + 1800000) : + ((index < 6) ? (index * 50000 + 2550000) : + ((index == 6) ? 2900000 : 3300000)); break; case PM8607_ID_LDO6: - switch (chip_id) { - case PM8607_CHIP_A0: - case PM8607_CHIP_A1: - ret = (index < 3) ? (index * 50000 + 1800000) : - ((index < 8) ? (index * 50000 + 2450000) : - -EINVAL); - break; - case PM8607_CHIP_B0: - ret = (index < 2) ? (index * 50000 + 1800000) : - ((index < 7) ? (index * 50000 + 2500000) : - 3300000); - break; - } + ret = (index < 2) ? (index * 50000 + 1800000) : + ((index < 7) ? (index * 50000 + 2500000) : + 3300000); break; case PM8607_ID_LDO10: - switch (chip_id) { - case PM8607_CHIP_A0: - case PM8607_CHIP_A1: - ret = (index < 3) ? (index * 50000 + 1800000) : - ((index < 8) ? (index * 50000 + 2550000) : - 1200000); - break; - case PM8607_CHIP_B0: - ret = (index < 3) ? (index * 50000 + 1800000) : - ((index < 7) ? (index * 50000 + 2550000) : - ((index == 7) ? 3300000 : 1200000)); - break; - } + ret = (index < 3) ? (index * 50000 + 1800000) : + ((index < 7) ? (index * 50000 + 2550000) : + ((index == 7) ? 3300000 : 1200000)); break; case PM8607_ID_LDO14: - switch (chip_id) { - case PM8607_CHIP_A0: - case PM8607_CHIP_A1: - ret = (index < 3) ? (index * 50000 + 1800000) : - ((index < 8) ? (index * 50000 + 2550000) : - -EINVAL); - break; - case PM8607_CHIP_B0: - ret = (index < 2) ? (index * 50000 + 1800000) : - ((index < 7) ? (index * 50000 + 2600000) : - 3300000); - break; - } + ret = (index < 2) ? (index * 50000 + 1800000) : + ((index < 7) ? (index * 50000 + 2600000) : + 3300000); break; } return ret; @@ -171,7 +120,6 @@ static int pm8607_list_voltage(struct regulator_dev *rdev, unsigned index) static int choose_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) { struct pm8607_regulator_info *info = rdev_get_drvdata(rdev); - uint8_t chip_id = info->chip->chip_version; int val = -ENOENT; int ret; @@ -256,161 +204,77 @@ static int choose_voltage(struct regulator_dev *rdev, int min_uV, int max_uV) case PM8607_ID_LDO2: case PM8607_ID_LDO3: case PM8607_ID_LDO9: - switch (chip_id) { - case PM8607_CHIP_A0: - case PM8607_CHIP_A1: - if (min_uV < 2700000) /* 1800mV ~ 1900mV / 50mV */ - if (min_uV <= 1800000) - val = 0; - else if (min_uV <= 1900000) - val = (min_uV - 1750001) / 50000; - else - val = 3; /* 2700mV */ - else { /* 2700mV ~ 2900mV / 50mV */ - if (min_uV <= 2900000) { - val = (min_uV - 2650001) / 50000; - val += 3; - } else - val = -EINVAL; - } - break; - case PM8607_CHIP_B0: - if (min_uV < 2700000) { /* 1800mV ~ 1900mV / 50mV */ - if (min_uV <= 1800000) - val = 0; - else if (min_uV <= 1900000) - val = (min_uV - 1750001) / 50000; - else - val = 3; /* 2700mV */ - } else { /* 2700mV ~ 2850mV / 50mV */ - if (min_uV <= 2850000) { - val = (min_uV - 2650001) / 50000; - val += 3; - } else if (min_uV <= 3300000) - val = 7; - else - val = -EINVAL; - } - break; + if (min_uV < 2700000) { /* 1800mV ~ 1900mV / 50mV */ + if (min_uV <= 1800000) + val = 0; + else if (min_uV <= 1900000) + val = (min_uV - 1750001) / 50000; + else + val = 3; /* 2700mV */ + } else { /* 2700mV ~ 2850mV / 50mV */ + if (min_uV <= 2850000) { + val = (min_uV - 2650001) / 50000; + val += 3; + } else if (min_uV <= 3300000) + val = 7; + else + val = -EINVAL; } break; case PM8607_ID_LDO4: - switch (chip_id) { - case PM8607_CHIP_A0: - case PM8607_CHIP_A1: - if (min_uV < 2700000) /* 1800mV ~ 1900mV / 50mV */ - if (min_uV <= 1800000) - val = 0; - else if (min_uV <= 1900000) - val = (min_uV - 1750001) / 50000; - else - val = 3; /* 2700mV */ - else { /* 2700mV ~ 2900mV / 50mV */ - if (min_uV <= 2900000) { - val = (min_uV - 2650001) / 50000; - val += 3; - } else - val = -EINVAL; - } - break; - case PM8607_CHIP_B0: - if (min_uV < 2700000) { /* 1800mV ~ 1900mV / 50mV */ - if (min_uV <= 1800000) - val = 0; - else if (min_uV <= 1900000) - val = (min_uV - 1750001) / 50000; - else - val = 3; /* 2700mV */ - } else { /* 2700mV ~ 2800mV / 50mV */ - if (min_uV <= 2850000) { - val = (min_uV - 2650001) / 50000; - val += 3; - } else if (min_uV <= 2900000) - val = 6; - else if (min_uV <= 3300000) - val = 7; - else - val = -EINVAL; - } - break; + if (min_uV < 2700000) { /* 1800mV ~ 1900mV / 50mV */ + if (min_uV <= 1800000) + val = 0; + else if (min_uV <= 1900000) + val = (min_uV - 1750001) / 50000; + else + val = 3; /* 2700mV */ + } else { /* 2700mV ~ 2800mV / 50mV */ + if (min_uV <= 2850000) { + val = (min_uV - 2650001) / 50000; + val += 3; + } else if (min_uV <= 2900000) + val = 6; + else if (min_uV <= 3300000) + val = 7; + else + val = -EINVAL; } break; case PM8607_ID_LDO6: - switch (chip_id) { - case PM8607_CHIP_A0: - case PM8607_CHIP_A1: - if (min_uV < 2600000) { /* 1800mV ~ 1900mV / 50mV */ - if (min_uV <= 1800000) - val = 0; - else if (min_uV <= 1900000) - val = (min_uV - 1750001) / 50000; - else - val = 3; /* 2600mV */ - } else { /* 2600mV ~ 2800mV / 50mV */ - if (min_uV <= 2800000) { - val = (min_uV - 2550001) / 50000; - val += 3; - } else - val = -EINVAL; - } - break; - case PM8607_CHIP_B0: - if (min_uV < 2600000) { /* 1800mV ~ 1850mV / 50mV */ - if (min_uV <= 1800000) - val = 0; - else if (min_uV <= 1850000) - val = (min_uV - 1750001) / 50000; - else - val = 2; /* 2600mV */ - } else { /* 2600mV ~ 2800mV / 50mV */ - if (min_uV <= 2800000) { - val = (min_uV - 2550001) / 50000; - val += 2; - } else if (min_uV <= 3300000) - val = 7; - else - val = -EINVAL; - } - break; + if (min_uV < 2600000) { /* 1800mV ~ 1850mV / 50mV */ + if (min_uV <= 1800000) + val = 0; + else if (min_uV <= 1850000) + val = (min_uV - 1750001) / 50000; + else + val = 2; /* 2600mV */ + } else { /* 2600mV ~ 2800mV / 50mV */ + if (min_uV <= 2800000) { + val = (min_uV - 2550001) / 50000; + val += 2; + } else if (min_uV <= 3300000) + val = 7; + else + val = -EINVAL; } break; case PM8607_ID_LDO14: - switch (chip_id) { - case PM8607_CHIP_A0: - case PM8607_CHIP_A1: - if (min_uV < 2700000) { /* 1800mV ~ 1900mV / 50mV */ - if (min_uV <= 1800000) - val = 0; - else if (min_uV <= 1900000) - val = (min_uV - 1750001) / 50000; - else - val = 3; /* 2700mV */ - } else { /* 2700mV ~ 2900mV / 50mV */ - if (min_uV <= 2900000) { - val = (min_uV - 2650001) / 50000; - val += 3; - } else - val = -EINVAL; - } - break; - case PM8607_CHIP_B0: - if (min_uV < 2700000) { /* 1800mV ~ 1850mV / 50mV */ - if (min_uV <= 1800000) - val = 0; - else if (min_uV <= 1850000) - val = (min_uV - 1750001) / 50000; - else - val = 2; /* 2700mV */ - } else { /* 2700mV ~ 2900mV / 50mV */ - if (min_uV <= 2900000) { - val = (min_uV - 2650001) / 50000; - val += 2; - } else if (min_uV <= 3300000) - val = 7; - else - val = -EINVAL; - } - break; + if (min_uV < 2700000) { /* 1800mV ~ 1850mV / 50mV */ + if (min_uV <= 1800000) + val = 0; + else if (min_uV <= 1850000) + val = (min_uV - 1750001) / 50000; + else + val = 2; /* 2700mV */ + } else { /* 2700mV ~ 2900mV / 50mV */ + if (min_uV <= 2900000) { + val = (min_uV - 2650001) / 50000; + val += 2; + } else if (min_uV <= 3300000) + val = 7; + else + val = -EINVAL; } break; } -- cgit v1.2.3 From d50f8f339f6901fccc9d4292b65ce8b69d7413d4 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 8 Jan 2010 12:29:23 +0100 Subject: mfd: Initial max8925 support Basic Max8925 support, which is a power management IC from Maxim Semiconductor. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/mfd/Kconfig | 9 ++ drivers/mfd/Makefile | 2 + drivers/mfd/max8925-core.c | 262 ++++++++++++++++++++++++++++++++++++++++++++ drivers/mfd/max8925-i2c.c | 210 +++++++++++++++++++++++++++++++++++ include/linux/mfd/max8925.h | 119 ++++++++++++++++++++ 5 files changed, 602 insertions(+) create mode 100644 drivers/mfd/max8925-core.c create mode 100644 drivers/mfd/max8925-i2c.c create mode 100644 include/linux/mfd/max8925.h (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 815907eb70a4..ee416eefb8e9 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -194,6 +194,15 @@ config PMIC_ADP5520 individual components like LCD backlight, LEDs, GPIOs and Kepad under the corresponding menus. +config MFD_MAX8925 + tristate "Maxim Semiconductor MAX8925 PMIC Support" + depends on I2C + help + Say yes here to support for Maxim Semiconductor MAX8925. This is + a Power Management IC. This driver provies common support for + accessing the device, additional drivers must be enabled in order + to use the functionality of the device. + config MFD_WM8400 tristate "Support Wolfson Microelectronics WM8400" select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 1e3ae062c1f6..261635700243 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -49,6 +49,8 @@ endif obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o obj-$(CONFIG_PMIC_DA903X) += da903x.o +max8925-objs := max8925-core.o max8925-i2c.o +obj-$(CONFIG_MFD_MAX8925) += max8925.o obj-$(CONFIG_MFD_PCF50633) += pcf50633-core.o obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o diff --git a/drivers/mfd/max8925-core.c b/drivers/mfd/max8925-core.c new file mode 100644 index 000000000000..3e26267960b1 --- /dev/null +++ b/drivers/mfd/max8925-core.c @@ -0,0 +1,262 @@ +/* + * Base driver for Maxim MAX8925 + * + * Copyright (C) 2009 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define IRQ_MODE_STATUS 0 +#define IRQ_MODE_MASK 1 + +static int __get_irq_offset(struct max8925_chip *chip, int irq, int mode, + int *offset, int *bit) +{ + if (!offset || !bit) + return -EINVAL; + + switch (chip->chip_id) { + case MAX8925_GPM: + *bit = irq % BITS_PER_BYTE; + if (irq < (BITS_PER_BYTE << 1)) { /* irq = [0,15] */ + *offset = (mode) ? MAX8925_CHG_IRQ1_MASK + : MAX8925_CHG_IRQ1; + if (irq >= BITS_PER_BYTE) + (*offset)++; + } else { /* irq = [16,31] */ + *offset = (mode) ? MAX8925_ON_OFF_IRQ1_MASK + : MAX8925_ON_OFF_IRQ1; + if (irq >= (BITS_PER_BYTE * 3)) + (*offset)++; + } + break; + case MAX8925_ADC: + *bit = irq % BITS_PER_BYTE; + *offset = (mode) ? MAX8925_TSC_IRQ_MASK : MAX8925_TSC_IRQ; + break; + default: + goto out; + } + return 0; +out: + dev_err(chip->dev, "Wrong irq #%d is assigned\n", irq); + return -EINVAL; +} + +static int __check_irq(int irq) +{ + if ((irq < 0) || (irq >= MAX8925_NUM_IRQ)) + return -EINVAL; + return 0; +} + +int max8925_mask_irq(struct max8925_chip *chip, int irq) +{ + int offset, bit, ret; + + ret = __get_irq_offset(chip, irq, IRQ_MODE_MASK, &offset, &bit); + if (ret < 0) + return ret; + ret = max8925_set_bits(chip->i2c, offset, 1 << bit, 1 << bit); + return ret; +} + +int max8925_unmask_irq(struct max8925_chip *chip, int irq) +{ + int offset, bit, ret; + + ret = __get_irq_offset(chip, irq, IRQ_MODE_MASK, &offset, &bit); + if (ret < 0) + return ret; + ret = max8925_set_bits(chip->i2c, offset, 1 << bit, 0); + return ret; +} + +#define INT_STATUS_NUM (MAX8925_NUM_IRQ / BITS_PER_BYTE) + +static irqreturn_t max8925_irq_thread(int irq, void *data) +{ + struct max8925_chip *chip = data; + unsigned long irq_status[INT_STATUS_NUM]; + unsigned char status_buf[INT_STATUS_NUM << 1]; + int i, ret; + + memset(irq_status, 0, sizeof(unsigned long) * INT_STATUS_NUM); + + /* all these interrupt status registers are read-only */ + switch (chip->chip_id) { + case MAX8925_GPM: + ret = max8925_bulk_read(chip->i2c, MAX8925_CHG_IRQ1, + 4, status_buf); + if (ret < 0) + goto out; + ret = max8925_bulk_read(chip->i2c, MAX8925_ON_OFF_IRQ1, + 2, &status_buf[4]); + if (ret < 0) + goto out; + ret = max8925_bulk_read(chip->i2c, MAX8925_ON_OFF_IRQ2, + 2, &status_buf[6]); + if (ret < 0) + goto out; + /* clear masked interrupt status */ + status_buf[0] &= (~status_buf[2] & CHG_IRQ1_MASK); + irq_status[0] |= status_buf[0]; + status_buf[1] &= (~status_buf[3] & CHG_IRQ2_MASK); + irq_status[0] |= (status_buf[1] << BITS_PER_BYTE); + status_buf[4] &= (~status_buf[5] & ON_OFF_IRQ1_MASK); + irq_status[0] |= (status_buf[4] << (BITS_PER_BYTE * 2)); + status_buf[6] &= (~status_buf[7] & ON_OFF_IRQ2_MASK); + irq_status[0] |= (status_buf[6] << (BITS_PER_BYTE * 3)); + break; + case MAX8925_ADC: + ret = max8925_bulk_read(chip->i2c, MAX8925_TSC_IRQ, + 2, status_buf); + if (ret < 0) + goto out; + /* clear masked interrupt status */ + status_buf[0] &= (~status_buf[1] & TSC_IRQ_MASK); + irq_status[0] |= status_buf[0]; + break; + default: + goto out; + } + + for_each_bit(i, &irq_status[0], MAX8925_NUM_IRQ) { + clear_bit(i, irq_status); + dev_dbg(chip->dev, "Servicing IRQ #%d in %s\n", i, chip->name); + + mutex_lock(&chip->irq_lock); + if (chip->irq[i].handler) + chip->irq[i].handler(i, chip->irq[i].data); + else { + max8925_mask_irq(chip, i); + dev_err(chip->dev, "Noboday cares IRQ #%d in %s. " + "Now mask it.\n", i, chip->name); + } + mutex_unlock(&chip->irq_lock); + } +out: + return IRQ_HANDLED; +} + +int max8925_request_irq(struct max8925_chip *chip, int irq, + irq_handler_t handler, void *data) +{ + if ((__check_irq(irq) < 0) || !handler) + return -EINVAL; + + mutex_lock(&chip->irq_lock); + chip->irq[irq].handler = handler; + chip->irq[irq].data = data; + mutex_unlock(&chip->irq_lock); + return 0; +} +EXPORT_SYMBOL(max8925_request_irq); + +int max8925_free_irq(struct max8925_chip *chip, int irq) +{ + if (__check_irq(irq) < 0) + return -EINVAL; + + mutex_lock(&chip->irq_lock); + chip->irq[irq].handler = NULL; + chip->irq[irq].data = NULL; + mutex_unlock(&chip->irq_lock); + return 0; +} +EXPORT_SYMBOL(max8925_free_irq); + +static int __devinit device_gpm_init(struct max8925_chip *chip, + struct i2c_client *i2c, + struct max8925_platform_data *pdata) +{ + int ret; + + /* mask all IRQs */ + ret = max8925_set_bits(i2c, MAX8925_CHG_IRQ1_MASK, 0x7, 0x7); + if (ret < 0) + goto out; + ret = max8925_set_bits(i2c, MAX8925_CHG_IRQ2_MASK, 0xff, 0xff); + if (ret < 0) + goto out; + ret = max8925_set_bits(i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff, 0xff); + if (ret < 0) + goto out; + ret = max8925_set_bits(i2c, MAX8925_ON_OFF_IRQ2_MASK, 0x3, 0x3); + if (ret < 0) + goto out; + + chip->name = "GPM"; + memset(chip->irq, 0, sizeof(struct max8925_irq) * MAX8925_NUM_IRQ); + ret = request_threaded_irq(i2c->irq, NULL, max8925_irq_thread, + IRQF_ONESHOT | IRQF_TRIGGER_LOW, + "max8925-gpm", chip); + if (ret < 0) { + dev_err(chip->dev, "Failed to request IRQ #%d.\n", i2c->irq); + goto out; + } + chip->chip_irq = i2c->irq; + + /* enable hard-reset for ONKEY power-off */ + max8925_set_bits(i2c, MAX8925_SYSENSEL, 0x80, 0x80); +out: + return ret; +} + +static int __devinit device_adc_init(struct max8925_chip *chip, + struct i2c_client *i2c, + struct max8925_platform_data *pdata) +{ + int ret; + + /* mask all IRQs */ + ret = max8925_set_bits(i2c, MAX8925_TSC_IRQ_MASK, 3, 3); + + chip->name = "ADC"; + memset(chip->irq, 0, sizeof(struct max8925_irq) * MAX8925_NUM_IRQ); + ret = request_threaded_irq(i2c->irq, NULL, max8925_irq_thread, + IRQF_ONESHOT | IRQF_TRIGGER_LOW, + "max8925-adc", chip); + if (ret < 0) { + dev_err(chip->dev, "Failed to request IRQ #%d.\n", i2c->irq); + goto out; + } + chip->chip_irq = i2c->irq; +out: + return ret; +} + +int __devinit max8925_device_init(struct max8925_chip *chip, + struct max8925_platform_data *pdata) +{ + switch (chip->chip_id) { + case MAX8925_GPM: + device_gpm_init(chip, chip->i2c, pdata); + break; + case MAX8925_ADC: + device_adc_init(chip, chip->i2c, pdata); + break; + } + return 0; +} + +void max8925_device_exit(struct max8925_chip *chip) +{ + if (chip->chip_irq >= 0) + free_irq(chip->chip_irq, chip); +} + +MODULE_DESCRIPTION("PMIC Driver for Maxim MAX8925"); +MODULE_AUTHOR("Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include + +static inline int max8925_read_device(struct i2c_client *i2c, + int reg, int bytes, void *dest) +{ + unsigned char data; + unsigned char *buf; + int ret; + + buf = kzalloc(bytes + 1, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + data = (unsigned char)reg; + ret = i2c_master_send(i2c, &data, 1); + if (ret < 0) + return ret; + + ret = i2c_master_recv(i2c, buf, bytes + 1); + if (ret < 0) + return ret; + memcpy(dest, buf, bytes); + return 0; +} + +static inline int max8925_write_device(struct i2c_client *i2c, + int reg, int bytes, void *src) +{ + unsigned char buf[bytes + 1]; + int ret; + + buf[0] = (unsigned char)reg; + memcpy(&buf[1], src, bytes); + + ret = i2c_master_send(i2c, buf, bytes + 1); + if (ret < 0) + return ret; + return 0; +} + +int max8925_reg_read(struct i2c_client *i2c, int reg) +{ + struct max8925_chip *chip = i2c_get_clientdata(i2c); + unsigned char data; + int ret; + + mutex_lock(&chip->io_lock); + ret = max8925_read_device(i2c, reg, 1, &data); + mutex_unlock(&chip->io_lock); + + if (ret < 0) + return ret; + else + return (int)data; +} +EXPORT_SYMBOL(max8925_reg_read); + +int max8925_reg_write(struct i2c_client *i2c, int reg, + unsigned char data) +{ + struct max8925_chip *chip = i2c_get_clientdata(i2c); + int ret; + + mutex_lock(&chip->io_lock); + ret = max8925_write_device(i2c, reg, 1, &data); + mutex_unlock(&chip->io_lock); + + return ret; +} +EXPORT_SYMBOL(max8925_reg_write); + +int max8925_bulk_read(struct i2c_client *i2c, int reg, + int count, unsigned char *buf) +{ + struct max8925_chip *chip = i2c_get_clientdata(i2c); + int ret; + + mutex_lock(&chip->io_lock); + ret = max8925_read_device(i2c, reg, count, buf); + mutex_unlock(&chip->io_lock); + + return ret; +} +EXPORT_SYMBOL(max8925_bulk_read); + +int max8925_bulk_write(struct i2c_client *i2c, int reg, + int count, unsigned char *buf) +{ + struct max8925_chip *chip = i2c_get_clientdata(i2c); + int ret; + + mutex_lock(&chip->io_lock); + ret = max8925_write_device(i2c, reg, count, buf); + mutex_unlock(&chip->io_lock); + + return ret; +} +EXPORT_SYMBOL(max8925_bulk_write); + +int max8925_set_bits(struct i2c_client *i2c, int reg, + unsigned char mask, unsigned char data) +{ + struct max8925_chip *chip = i2c_get_clientdata(i2c); + unsigned char value; + int ret; + + mutex_lock(&chip->io_lock); + ret = max8925_read_device(i2c, reg, 1, &value); + if (ret < 0) + goto out; + value &= ~mask; + value |= data; + ret = max8925_write_device(i2c, reg, 1, &value); +out: + mutex_unlock(&chip->io_lock); + return ret; +} +EXPORT_SYMBOL(max8925_set_bits); + + +static const struct i2c_device_id max8925_id_table[] = { + { "max8925", 0 }, + {} +}; +MODULE_DEVICE_TABLE(i2c, max8925_id_table); + +static int __devinit max8925_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct max8925_platform_data *pdata = client->dev.platform_data; + struct max8925_chip *chip; + + if (!pdata) { + pr_info("%s: platform data is missing\n", __func__); + return -EINVAL; + } + if ((pdata->chip_id <= MAX8925_INVALID) + || (pdata->chip_id >= MAX8925_MAX)) { + pr_info("#%s: wrong chip identification\n", __func__); + return -EINVAL; + } + + chip = kzalloc(sizeof(struct max8925_chip), GFP_KERNEL); + if (chip == NULL) + return -ENOMEM; + chip->i2c = client; + chip->chip_id = pdata->chip_id; + i2c_set_clientdata(client, chip); + chip->dev = &client->dev; + mutex_init(&chip->io_lock); + dev_set_drvdata(chip->dev, chip); + max8925_device_init(chip, pdata); + + return 0; +} + +static int __devexit max8925_remove(struct i2c_client *client) +{ + struct max8925_chip *chip = i2c_get_clientdata(client); + + max8925_device_exit(chip); + i2c_set_clientdata(client, NULL); + kfree(chip); + return 0; +} + +static struct i2c_driver max8925_driver = { + .driver = { + .name = "max8925", + .owner = THIS_MODULE, + }, + .probe = max8925_probe, + .remove = __devexit_p(max8925_remove), + .id_table = max8925_id_table, +}; + +static int __init max8925_i2c_init(void) +{ + int ret; + + ret = i2c_add_driver(&max8925_driver); + if (ret != 0) + pr_err("Failed to register MAX8925 I2C driver: %d\n", ret); + return ret; +} +subsys_initcall(max8925_i2c_init); + +static void __exit max8925_i2c_exit(void) +{ + i2c_del_driver(&max8925_driver); +} +module_exit(max8925_i2c_exit); + +MODULE_DESCRIPTION("I2C Driver for Maxim 8925"); +MODULE_AUTHOR("Haojian Zhuang "); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/max8925.h b/include/linux/mfd/max8925.h new file mode 100644 index 000000000000..2326246ddef2 --- /dev/null +++ b/include/linux/mfd/max8925.h @@ -0,0 +1,119 @@ +/* + * Maxim8925 Interface + * + * Copyright (C) 2009 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_MFD_MAX8925_H +#define __LINUX_MFD_MAX8925_H + +#include + +/* Charger registers */ +#define MAX8925_CHG_IRQ1 (0x7e) +#define MAX8925_CHG_IRQ2 (0x7f) +#define MAX8925_CHG_IRQ1_MASK (0x80) +#define MAX8925_CHG_IRQ2_MASK (0x81) + +/* GPM registers */ +#define MAX8925_SYSENSEL (0x00) +#define MAX8925_ON_OFF_IRQ1 (0x01) +#define MAX8925_ON_OFF_IRQ1_MASK (0x02) +#define MAX8925_ON_OFF_STAT (0x03) +#define MAX8925_ON_OFF_IRQ2 (0x0d) +#define MAX8925_ON_OFF_IRQ2_MASK (0x0e) +#define MAX8925_RESET_CNFG (0x0f) + +/* Touch registers */ +#define MAX8925_TSC_IRQ (0x00) +#define MAX8925_TSC_IRQ_MASK (0x01) + +/* RTC registers */ +#define MAX8925_RTC_STATUS (0x1a) +#define MAX8925_RTC_IRQ (0x1c) +#define MAX8925_RTC_IRQ_MASK (0x1d) + +/* bit definitions */ +#define CHG_IRQ1_MASK (0x07) +#define CHG_IRQ2_MASK (0xff) +#define ON_OFF_IRQ1_MASK (0xff) +#define ON_OFF_IRQ2_MASK (0x03) +#define TSC_IRQ_MASK (0x03) +#define RTC_IRQ_MASK (0x0c) + +#define MAX8925_NUM_IRQ (32) + +#define MAX8925_NAME_SIZE (32) + +enum { + MAX8925_INVALID = 0, + MAX8925_RTC, + MAX8925_ADC, + MAX8925_GPM, /* general power management */ + MAX8925_MAX, +}; + +#define MAX8925_IRQ_VCHG_OVP (0) +#define MAX8925_IRQ_VCHG_F (1) +#define MAX8925_IRQ_VCHG_R (2) +#define MAX8925_IRQ_VCHG_THM_OK_R (8) +#define MAX8925_IRQ_VCHG_THM_OK_F (9) +#define MAX8925_IRQ_VCHG_BATTLOW_F (10) +#define MAX8925_IRQ_VCHG_BATTLOW_R (11) +#define MAX8925_IRQ_VCHG_RST (12) +#define MAX8925_IRQ_VCHG_DONE (13) +#define MAX8925_IRQ_VCHG_TOPOFF (14) +#define MAX8925_IRQ_VCHG_TMR_FAULT (15) +#define MAX8925_IRQ_GPM_RSTIN (16) +#define MAX8925_IRQ_GPM_MPL (17) +#define MAX8925_IRQ_GPM_SW_3SEC (18) +#define MAX8925_IRQ_GPM_EXTON_F (19) +#define MAX8925_IRQ_GPM_EXTON_R (20) +#define MAX8925_IRQ_GPM_SW_1SEC (21) +#define MAX8925_IRQ_GPM_SW_F (22) +#define MAX8925_IRQ_GPM_SW_R (23) +#define MAX8925_IRQ_GPM_SYSCKEN_F (24) +#define MAX8925_IRQ_GPM_SYSCKEN_R (25) + +#define MAX8925_IRQ_TSC_STICK (0) +#define MAX8925_IRQ_TSC_NSTICK (1) + +struct max8925_irq { + irq_handler_t handler; + void *data; +}; + +struct max8925_chip { + struct device *dev; + struct mutex io_lock; + struct mutex irq_lock; + struct i2c_client *i2c; + struct max8925_irq irq[MAX8925_NUM_IRQ]; + + const char *name; + int chip_id; + int chip_irq; +}; + +struct max8925_platform_data { + int chip_id; + int chip_irq; +}; + +extern int max8925_reg_read(struct i2c_client *, int); +extern int max8925_reg_write(struct i2c_client *, int, unsigned char); +extern int max8925_bulk_read(struct i2c_client *, int, int, unsigned char *); +extern int max8925_bulk_write(struct i2c_client *, int, int, unsigned char *); +extern int max8925_set_bits(struct i2c_client *, int, unsigned char, + unsigned char); + +extern int max8925_device_init(struct max8925_chip *, + struct max8925_platform_data *); +extern void max8925_device_exit(struct max8925_chip *); +#endif /* __LINUX_MFD_MAX8925_H */ + -- cgit v1.2.3 From 1ad998934e9c6cbae91662a05e0cb8772b1f4f75 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 8 Jan 2010 12:43:29 -0500 Subject: mfd: Add subdevs in max8925 Add subdevs in MAX8925. MAX8925 includes regulator, backlight and touch components. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/mfd/Kconfig | 1 + drivers/mfd/max8925-core.c | 142 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/mfd/max8925.h | 96 ++++++++++++++++++++++++++++++ 3 files changed, 239 insertions(+) (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index ee416eefb8e9..d63ab2eec661 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -197,6 +197,7 @@ config PMIC_ADP5520 config MFD_MAX8925 tristate "Maxim Semiconductor MAX8925 PMIC Support" depends on I2C + select MFD_CORE help Say yes here to support for Maxim Semiconductor MAX8925. This is a Power Management IC. This driver provies common support for diff --git a/drivers/mfd/max8925-core.c b/drivers/mfd/max8925-core.c index 3e26267960b1..f36c494b80f1 100644 --- a/drivers/mfd/max8925-core.c +++ b/drivers/mfd/max8925-core.c @@ -20,6 +20,109 @@ #define IRQ_MODE_STATUS 0 #define IRQ_MODE_MASK 1 +static struct resource backlight_resources[] = { + { + .name = "max8925-backlight", + .start = MAX8925_WLED_MODE_CNTL, + .end = MAX8925_WLED_CNTL, + .flags = IORESOURCE_IO, + }, +}; + +static struct mfd_cell backlight_devs[] = { + { + .name = "max8925-backlight", + .num_resources = 1, + .resources = &backlight_resources[0], + .id = -1, + }, +}; + +static struct resource touch_resources[] = { + { + .name = "max8925-tsc", + .start = MAX8925_TSC_IRQ, + .end = MAX8925_ADC_RES_END, + .flags = IORESOURCE_IO, + }, +}; + +static struct mfd_cell touch_devs[] = { + { + .name = "max8925-touch", + .num_resources = 1, + .resources = &touch_resources[0], + .id = -1, + }, +}; + +#define MAX8925_REG_RESOURCE(_start, _end) \ +{ \ + .start = MAX8925_##_start, \ + .end = MAX8925_##_end, \ + .flags = IORESOURCE_IO, \ +} + +static struct resource regulator_resources[] = { + MAX8925_REG_RESOURCE(SDCTL1, SDCTL1), + MAX8925_REG_RESOURCE(SDCTL2, SDCTL2), + MAX8925_REG_RESOURCE(SDCTL3, SDCTL3), + MAX8925_REG_RESOURCE(LDOCTL1, LDOCTL1), + MAX8925_REG_RESOURCE(LDOCTL2, LDOCTL2), + MAX8925_REG_RESOURCE(LDOCTL3, LDOCTL3), + MAX8925_REG_RESOURCE(LDOCTL4, LDOCTL4), + MAX8925_REG_RESOURCE(LDOCTL5, LDOCTL5), + MAX8925_REG_RESOURCE(LDOCTL6, LDOCTL6), + MAX8925_REG_RESOURCE(LDOCTL7, LDOCTL7), + MAX8925_REG_RESOURCE(LDOCTL8, LDOCTL8), + MAX8925_REG_RESOURCE(LDOCTL9, LDOCTL9), + MAX8925_REG_RESOURCE(LDOCTL10, LDOCTL10), + MAX8925_REG_RESOURCE(LDOCTL11, LDOCTL11), + MAX8925_REG_RESOURCE(LDOCTL12, LDOCTL12), + MAX8925_REG_RESOURCE(LDOCTL13, LDOCTL13), + MAX8925_REG_RESOURCE(LDOCTL14, LDOCTL14), + MAX8925_REG_RESOURCE(LDOCTL15, LDOCTL15), + MAX8925_REG_RESOURCE(LDOCTL16, LDOCTL16), + MAX8925_REG_RESOURCE(LDOCTL17, LDOCTL17), + MAX8925_REG_RESOURCE(LDOCTL18, LDOCTL18), + MAX8925_REG_RESOURCE(LDOCTL19, LDOCTL19), + MAX8925_REG_RESOURCE(LDOCTL20, LDOCTL20), +}; + +#define MAX8925_REG_DEVS(_id) \ +{ \ + .name = "max8925-regulator", \ + .num_resources = 1, \ + .resources = ®ulator_resources[MAX8925_ID_##_id], \ + .id = MAX8925_ID_##_id, \ +} + +static struct mfd_cell regulator_devs[] = { + MAX8925_REG_DEVS(SD1), + MAX8925_REG_DEVS(SD2), + MAX8925_REG_DEVS(SD3), + MAX8925_REG_DEVS(LDO1), + MAX8925_REG_DEVS(LDO2), + MAX8925_REG_DEVS(LDO3), + MAX8925_REG_DEVS(LDO4), + MAX8925_REG_DEVS(LDO5), + MAX8925_REG_DEVS(LDO6), + MAX8925_REG_DEVS(LDO7), + MAX8925_REG_DEVS(LDO8), + MAX8925_REG_DEVS(LDO9), + MAX8925_REG_DEVS(LDO10), + MAX8925_REG_DEVS(LDO11), + MAX8925_REG_DEVS(LDO12), + MAX8925_REG_DEVS(LDO13), + MAX8925_REG_DEVS(LDO14), + MAX8925_REG_DEVS(LDO15), + MAX8925_REG_DEVS(LDO16), + MAX8925_REG_DEVS(LDO17), + MAX8925_REG_DEVS(LDO18), + MAX8925_REG_DEVS(LDO19), + MAX8925_REG_DEVS(LDO20), +}; + static int __get_irq_offset(struct max8925_chip *chip, int irq, int mode, int *offset, int *bit) { @@ -210,6 +313,30 @@ static int __devinit device_gpm_init(struct max8925_chip *chip, /* enable hard-reset for ONKEY power-off */ max8925_set_bits(i2c, MAX8925_SYSENSEL, 0x80, 0x80); + + ret = mfd_add_devices(chip->dev, 0, ®ulator_devs[0], + ARRAY_SIZE(regulator_devs), + ®ulator_resources[0], 0); + if (ret < 0) { + dev_err(chip->dev, "Failed to add regulator subdev\n"); + goto out_irq; + } + + if (pdata && pdata->backlight) { + ret = mfd_add_devices(chip->dev, 0, &backlight_devs[0], + ARRAY_SIZE(backlight_devs), + &backlight_resources[0], 0); + if (ret < 0) { + dev_err(chip->dev, "Failed to add backlight subdev\n"); + goto out_dev; + } + } + return 0; +out_dev: + mfd_remove_devices(chip->dev); +out_irq: + if (chip->chip_irq) + free_irq(chip->chip_irq, chip); out: return ret; } @@ -233,6 +360,20 @@ static int __devinit device_adc_init(struct max8925_chip *chip, goto out; } chip->chip_irq = i2c->irq; + + if (pdata && pdata->touch) { + ret = mfd_add_devices(chip->dev, 0, &touch_devs[0], + ARRAY_SIZE(touch_devs), + &touch_resources[0], 0); + if (ret < 0) { + dev_err(chip->dev, "Failed to add touch subdev\n"); + goto out_irq; + } + } + return 0; +out_irq: + if (chip->chip_irq) + free_irq(chip->chip_irq, chip); out: return ret; } @@ -255,6 +396,7 @@ void max8925_device_exit(struct max8925_chip *chip) { if (chip->chip_irq >= 0) free_irq(chip->chip_irq, chip); + mfd_remove_devices(chip->dev); } MODULE_DESCRIPTION("PMIC Driver for Maxim MAX8925"); diff --git a/include/linux/mfd/max8925.h b/include/linux/mfd/max8925.h index 2326246ddef2..b72dbe174d51 100644 --- a/include/linux/mfd/max8925.h +++ b/include/linux/mfd/max8925.h @@ -14,6 +14,33 @@ #include +/* Unified sub device IDs for MAX8925 */ +enum { + MAX8925_ID_SD1, + MAX8925_ID_SD2, + MAX8925_ID_SD3, + MAX8925_ID_LDO1, + MAX8925_ID_LDO2, + MAX8925_ID_LDO3, + MAX8925_ID_LDO4, + MAX8925_ID_LDO5, + MAX8925_ID_LDO6, + MAX8925_ID_LDO7, + MAX8925_ID_LDO8, + MAX8925_ID_LDO9, + MAX8925_ID_LDO10, + MAX8925_ID_LDO11, + MAX8925_ID_LDO12, + MAX8925_ID_LDO13, + MAX8925_ID_LDO14, + MAX8925_ID_LDO15, + MAX8925_ID_LDO16, + MAX8925_ID_LDO17, + MAX8925_ID_LDO18, + MAX8925_ID_LDO19, + MAX8925_ID_LDO20, +}; + /* Charger registers */ #define MAX8925_CHG_IRQ1 (0x7e) #define MAX8925_CHG_IRQ2 (0x7f) @@ -32,12 +59,65 @@ /* Touch registers */ #define MAX8925_TSC_IRQ (0x00) #define MAX8925_TSC_IRQ_MASK (0x01) +#define MAX8925_ADC_RES_END (0x6f) /* RTC registers */ #define MAX8925_RTC_STATUS (0x1a) #define MAX8925_RTC_IRQ (0x1c) #define MAX8925_RTC_IRQ_MASK (0x1d) +/* WLED registers */ +#define MAX8925_WLED_MODE_CNTL (0x84) +#define MAX8925_WLED_CNTL (0x85) + +/* MAX8925 Registers */ +#define MAX8925_SDCTL1 (0x04) +#define MAX8925_SDCTL2 (0x07) +#define MAX8925_SDCTL3 (0x0A) +#define MAX8925_SDV1 (0x06) +#define MAX8925_SDV2 (0x09) +#define MAX8925_SDV3 (0x0C) +#define MAX8925_LDOCTL1 (0x18) +#define MAX8925_LDOCTL2 (0x1C) +#define MAX8925_LDOCTL3 (0x20) +#define MAX8925_LDOCTL4 (0x24) +#define MAX8925_LDOCTL5 (0x28) +#define MAX8925_LDOCTL6 (0x2C) +#define MAX8925_LDOCTL7 (0x30) +#define MAX8925_LDOCTL8 (0x34) +#define MAX8925_LDOCTL9 (0x38) +#define MAX8925_LDOCTL10 (0x3C) +#define MAX8925_LDOCTL11 (0x40) +#define MAX8925_LDOCTL12 (0x44) +#define MAX8925_LDOCTL13 (0x48) +#define MAX8925_LDOCTL14 (0x4C) +#define MAX8925_LDOCTL15 (0x50) +#define MAX8925_LDOCTL16 (0x10) +#define MAX8925_LDOCTL17 (0x14) +#define MAX8925_LDOCTL18 (0x72) +#define MAX8925_LDOCTL19 (0x5C) +#define MAX8925_LDOCTL20 (0x9C) +#define MAX8925_LDOVOUT1 (0x1A) +#define MAX8925_LDOVOUT2 (0x1E) +#define MAX8925_LDOVOUT3 (0x22) +#define MAX8925_LDOVOUT4 (0x26) +#define MAX8925_LDOVOUT5 (0x2A) +#define MAX8925_LDOVOUT6 (0x2E) +#define MAX8925_LDOVOUT7 (0x32) +#define MAX8925_LDOVOUT8 (0x36) +#define MAX8925_LDOVOUT9 (0x3A) +#define MAX8925_LDOVOUT10 (0x3E) +#define MAX8925_LDOVOUT11 (0x42) +#define MAX8925_LDOVOUT12 (0x46) +#define MAX8925_LDOVOUT13 (0x4A) +#define MAX8925_LDOVOUT14 (0x4E) +#define MAX8925_LDOVOUT15 (0x52) +#define MAX8925_LDOVOUT16 (0x12) +#define MAX8925_LDOVOUT17 (0x16) +#define MAX8925_LDOVOUT18 (0x74) +#define MAX8925_LDOVOUT19 (0x5E) +#define MAX8925_LDOVOUT20 (0x9E) + /* bit definitions */ #define CHG_IRQ1_MASK (0x07) #define CHG_IRQ2_MASK (0xff) @@ -83,6 +163,8 @@ enum { #define MAX8925_IRQ_TSC_STICK (0) #define MAX8925_IRQ_TSC_NSTICK (1) +#define MAX8925_MAX_REGULATOR (23) + struct max8925_irq { irq_handler_t handler; void *data; @@ -100,7 +182,21 @@ struct max8925_chip { int chip_irq; }; +struct max8925_backlight_pdata { + int lxw_scl; /* 0/1 -- 0.8Ohm/0.4Ohm */ + int lxw_freq; /* 700KHz ~ 1400KHz */ + int dual_string; /* 0/1 -- single/dual string */ +}; + +struct max8925_touch_pdata { + unsigned int flags; +}; + struct max8925_platform_data { + struct max8925_backlight_pdata *backlight; + struct max8925_touch_pdata *touch; + struct regulator_init_data *regulator[MAX8925_MAX_REGULATOR]; + int chip_id; int chip_irq; }; -- cgit v1.2.3 From 4f811ef0d40048ae80b6ea77080b814725bffc58 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 18 Dec 2009 10:01:45 -0500 Subject: backlight: Enable max8925 backlight Enable max8925 backlight sub device. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/video/backlight/Kconfig | 7 ++ drivers/video/backlight/Makefile | 1 + drivers/video/backlight/max8925_bl.c | 200 +++++++++++++++++++++++++++++++++++ 3 files changed, 208 insertions(+) create mode 100644 drivers/video/backlight/max8925_bl.c (limited to 'drivers') diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig index 96a6b3060ac0..0c77fc610212 100644 --- a/drivers/video/backlight/Kconfig +++ b/drivers/video/backlight/Kconfig @@ -212,6 +212,13 @@ config BACKLIGHT_DA903X If you have a LCD backlight connected to the WLED output of DA9030 or DA9034 WLED output, say Y here to enable this driver. +config BACKLIGHT_MAX8925 + tristate "Backlight driver for MAX8925" + depends on BACKLIGHT_CLASS_DEVICE && MFD_MAX8925 + help + If you have a LCD backlight connected to the WLED output of MAX8925 + WLED output, say Y here to enable this driver. + config BACKLIGHT_MBP_NVIDIA tristate "MacBook Pro Nvidia Backlight Driver" depends on BACKLIGHT_CLASS_DEVICE && X86 diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile index 802d467b08c0..6c704d41462d 100644 --- a/drivers/video/backlight/Makefile +++ b/drivers/video/backlight/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o obj-$(CONFIG_BACKLIGHT_PWM) += pwm_bl.o obj-$(CONFIG_BACKLIGHT_DA903X) += da903x_bl.o +obj-$(CONFIG_BACKLIGHT_MAX8925) += max8925_bl.o obj-$(CONFIG_BACKLIGHT_MBP_NVIDIA) += mbp_nvidia_bl.o obj-$(CONFIG_BACKLIGHT_TOSA) += tosa_bl.o obj-$(CONFIG_BACKLIGHT_SAHARA) += kb3886_bl.o diff --git a/drivers/video/backlight/max8925_bl.c b/drivers/video/backlight/max8925_bl.c new file mode 100644 index 000000000000..c267069a52a3 --- /dev/null +++ b/drivers/video/backlight/max8925_bl.c @@ -0,0 +1,200 @@ +/* + * Backlight driver for Maxim MAX8925 + * + * Copyright (C) 2009 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MAX_BRIGHTNESS (0xff) +#define MIN_BRIGHTNESS (0) + +#define LWX_FREQ(x) (((x - 601) / 100) & 0x7) + +struct max8925_backlight_data { + struct max8925_chip *chip; + + int current_brightness; +}; + +static int max8925_backlight_set(struct backlight_device *bl, int brightness) +{ + struct max8925_backlight_data *data = bl_get_data(bl); + struct max8925_chip *chip = data->chip; + unsigned char value; + int ret; + + if (brightness > MAX_BRIGHTNESS) + value = MAX_BRIGHTNESS; + else + value = brightness; + + ret = max8925_reg_write(chip->i2c, MAX8925_WLED_CNTL, value); + if (ret < 0) + goto out; + + if (!data->current_brightness && brightness) + /* enable WLED output */ + ret = max8925_set_bits(chip->i2c, MAX8925_WLED_MODE_CNTL, 1, 1); + else if (!brightness) + /* disable WLED output */ + ret = max8925_set_bits(chip->i2c, MAX8925_WLED_MODE_CNTL, 1, 0); + if (ret < 0) + goto out; + dev_dbg(chip->dev, "set brightness %d\n", value); + data->current_brightness = value; + return 0; +out: + dev_dbg(chip->dev, "set brightness %d failure with return value:%d\n", + value, ret); + return ret; +} + +static int max8925_backlight_update_status(struct backlight_device *bl) +{ + int brightness = bl->props.brightness; + + if (bl->props.power != FB_BLANK_UNBLANK) + brightness = 0; + + if (bl->props.fb_blank != FB_BLANK_UNBLANK) + brightness = 0; + + if (bl->props.state & BL_CORE_SUSPENDED) + brightness = 0; + + return max8925_backlight_set(bl, brightness); +} + +static int max8925_backlight_get_brightness(struct backlight_device *bl) +{ + struct max8925_backlight_data *data = bl_get_data(bl); + struct max8925_chip *chip = data->chip; + int ret; + + ret = max8925_reg_read(chip->i2c, MAX8925_WLED_CNTL); + if (ret < 0) + return -EINVAL; + data->current_brightness = ret; + dev_dbg(chip->dev, "get brightness %d\n", data->current_brightness); + return ret; +} + +static struct backlight_ops max8925_backlight_ops = { + .options = BL_CORE_SUSPENDRESUME, + .update_status = max8925_backlight_update_status, + .get_brightness = max8925_backlight_get_brightness, +}; + +static int __devinit max8925_backlight_probe(struct platform_device *pdev) +{ + struct max8925_chip *chip = dev_get_drvdata(pdev->dev.parent); + struct max8925_platform_data *max8925_pdata; + struct max8925_backlight_pdata *pdata = NULL; + struct max8925_backlight_data *data; + struct backlight_device *bl; + struct resource *res; + char name[MAX8925_NAME_SIZE]; + unsigned char value; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_IO, 0); + if (res == NULL) { + dev_err(&pdev->dev, "No I/O resource!\n"); + return -EINVAL; + } + + if (pdev->dev.parent->platform_data) { + max8925_pdata = pdev->dev.parent->platform_data; + pdata = max8925_pdata->backlight; + } + + if (!pdata) { + dev_err(&pdev->dev, "platform data isn't assigned to " + "backlight\n"); + return -EINVAL; + } + + data = kzalloc(sizeof(struct max8925_backlight_data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + strncpy(name, res->name, MAX8925_NAME_SIZE); + data->chip = chip; + data->current_brightness = 0; + + bl = backlight_device_register(name, &pdev->dev, data, + &max8925_backlight_ops); + if (IS_ERR(bl)) { + dev_err(&pdev->dev, "failed to register backlight\n"); + kfree(data); + return PTR_ERR(bl); + } + bl->props.max_brightness = MAX_BRIGHTNESS; + bl->props.brightness = MAX_BRIGHTNESS; + + platform_set_drvdata(pdev, bl); + + value = 0; + if (pdata->lxw_scl) + value |= (1 << 7); + if (pdata->lxw_freq) + value |= (LWX_FREQ(pdata->lxw_freq) << 4); + if (pdata->dual_string) + value |= (1 << 1); + ret = max8925_set_bits(chip->i2c, MAX8925_WLED_MODE_CNTL, 0xfe, value); + if (ret < 0) + goto out; + + backlight_update_status(bl); + return 0; +out: + kfree(data); + return ret; +} + +static int __devexit max8925_backlight_remove(struct platform_device *pdev) +{ + struct backlight_device *bl = platform_get_drvdata(pdev); + struct max8925_backlight_data *data = bl_get_data(bl); + + backlight_device_unregister(bl); + kfree(data); + return 0; +} + +static struct platform_driver max8925_backlight_driver = { + .driver = { + .name = "max8925-backlight", + .owner = THIS_MODULE, + }, + .probe = max8925_backlight_probe, + .remove = __devexit_p(max8925_backlight_remove), +}; + +static int __init max8925_backlight_init(void) +{ + return platform_driver_register(&max8925_backlight_driver); +} +module_init(max8925_backlight_init); + +static void __exit max8925_backlight_exit(void) +{ + platform_driver_unregister(&max8925_backlight_driver); +}; +module_exit(max8925_backlight_exit); + +MODULE_DESCRIPTION("Backlight Driver for Maxim MAX8925"); +MODULE_AUTHOR("Haojian Zhuang "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:max8925-backlight"); -- cgit v1.2.3 From 08ff6f2a9908c87b0adffe6453291be22db3a62f Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 11 Jan 2010 13:10:08 +0100 Subject: regulator: Add max8925 support MAX8925 contains 3 Buck and 20 LDO regulator. Signed-off-by: Haojian Zhuang Acked-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/regulator/Kconfig | 6 + drivers/regulator/Makefile | 1 + drivers/regulator/max8925-regulator.c | 306 ++++++++++++++++++++++++++++++++++ 3 files changed, 313 insertions(+) create mode 100644 drivers/regulator/max8925-regulator.c (limited to 'drivers') diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index dbfe31a4a519..04f2e085116a 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -94,6 +94,12 @@ config REGULATOR_MAX8660 This driver controls a Maxim 8660/8661 voltage output regulator via I2C bus. +config REGULATOR_MAX8925 + tristate "Maxim MAX8925 Power Management IC" + depends on MFD_MAX8925 + help + Say y here to support the voltage regulaltor of Maxim MAX8925 PMIC. + config REGULATOR_TWL4030 bool "TI TWL4030/TWL5030/TWL6030/TPS695x0 PMIC" depends on TWL4030_CORE diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index e845b66ad59c..4e7feece22d5 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o obj-$(CONFIG_REGULATOR_TWL4030) += twl-regulator.o obj-$(CONFIG_REGULATOR_MAX8649) += max8649.o obj-$(CONFIG_REGULATOR_MAX8660) += max8660.o +obj-$(CONFIG_REGULATOR_MAX8925) += max8925-regulator.o obj-$(CONFIG_REGULATOR_WM831X) += wm831x-dcdc.o obj-$(CONFIG_REGULATOR_WM831X) += wm831x-isink.o obj-$(CONFIG_REGULATOR_WM831X) += wm831x-ldo.o diff --git a/drivers/regulator/max8925-regulator.c b/drivers/regulator/max8925-regulator.c new file mode 100644 index 000000000000..67873f08ed40 --- /dev/null +++ b/drivers/regulator/max8925-regulator.c @@ -0,0 +1,306 @@ +/* + * Regulators driver for Maxim max8925 + * + * Copyright (C) 2009 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define SD1_DVM_VMIN 850000 +#define SD1_DVM_VMAX 1000000 +#define SD1_DVM_STEP 50000 +#define SD1_DVM_SHIFT 5 /* SDCTL1 bit5 */ +#define SD1_DVM_EN 6 /* SDV1 bit 6 */ + +struct max8925_regulator_info { + struct regulator_desc desc; + struct regulator_dev *regulator; + struct i2c_client *i2c; + struct max8925_chip *chip; + + int min_uV; + int max_uV; + int step_uV; + int vol_reg; + int vol_shift; + int vol_nbits; + int enable_bit; + int enable_reg; +}; + +static inline int check_range(struct max8925_regulator_info *info, + int min_uV, int max_uV) +{ + if (min_uV < info->min_uV || min_uV > info->max_uV) + return -EINVAL; + + return 0; +} + +static int max8925_list_voltage(struct regulator_dev *rdev, unsigned index) +{ + struct max8925_regulator_info *info = rdev_get_drvdata(rdev); + return info->min_uV + index * info->step_uV; +} + +static int max8925_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV) +{ + struct max8925_regulator_info *info = rdev_get_drvdata(rdev); + unsigned char data, mask; + + if (check_range(info, min_uV, max_uV)) { + dev_err(info->chip->dev, "invalid voltage range (%d, %d) uV\n", + min_uV, max_uV); + return -EINVAL; + } + data = (min_uV - info->min_uV + info->step_uV - 1) / info->step_uV; + data <<= info->vol_shift; + mask = ((1 << info->vol_nbits) - 1) << info->vol_shift; + + return max8925_set_bits(info->i2c, info->vol_reg, mask, data); +} + +static int max8925_get_voltage(struct regulator_dev *rdev) +{ + struct max8925_regulator_info *info = rdev_get_drvdata(rdev); + unsigned char data, mask; + int ret; + + ret = max8925_reg_read(info->i2c, info->vol_reg); + if (ret < 0) + return ret; + mask = ((1 << info->vol_nbits) - 1) << info->vol_shift; + data = (ret & mask) >> info->vol_shift; + + return max8925_list_voltage(rdev, data); +} + +static int max8925_enable(struct regulator_dev *rdev) +{ + struct max8925_regulator_info *info = rdev_get_drvdata(rdev); + + return max8925_set_bits(info->i2c, info->enable_reg, + 1 << info->enable_bit, + 1 << info->enable_bit); +} + +static int max8925_disable(struct regulator_dev *rdev) +{ + struct max8925_regulator_info *info = rdev_get_drvdata(rdev); + + return max8925_set_bits(info->i2c, info->enable_reg, + 1 << info->enable_bit, 0); +} + +static int max8925_is_enabled(struct regulator_dev *rdev) +{ + struct max8925_regulator_info *info = rdev_get_drvdata(rdev); + int ret; + + ret = max8925_reg_read(info->i2c, info->vol_reg); + if (ret < 0) + return ret; + + return ret & (1 << info->enable_bit); +} + +static int max8925_set_dvm_voltage(struct regulator_dev *rdev, int uV) +{ + struct max8925_regulator_info *info = rdev_get_drvdata(rdev); + unsigned char data, mask; + + if (uV < SD1_DVM_VMIN || uV > SD1_DVM_VMAX) + return -EINVAL; + + data = (uV - SD1_DVM_VMIN + SD1_DVM_STEP - 1) / SD1_DVM_STEP; + data <<= SD1_DVM_SHIFT; + mask = 3 << SD1_DVM_SHIFT; + + return max8925_set_bits(info->i2c, info->enable_reg, mask, data); +} + +static int max8925_set_dvm_enable(struct regulator_dev *rdev) +{ + struct max8925_regulator_info *info = rdev_get_drvdata(rdev); + + return max8925_set_bits(info->i2c, info->vol_reg, 1 << SD1_DVM_EN, + 1 << SD1_DVM_EN); +} + +static int max8925_set_dvm_disable(struct regulator_dev *rdev) +{ + struct max8925_regulator_info *info = rdev_get_drvdata(rdev); + + return max8925_set_bits(info->i2c, info->vol_reg, 1 << SD1_DVM_EN, 0); +} + +static struct regulator_ops max8925_regulator_sdv_ops = { + .set_voltage = max8925_set_voltage, + .get_voltage = max8925_get_voltage, + .enable = max8925_enable, + .disable = max8925_disable, + .is_enabled = max8925_is_enabled, + .set_suspend_voltage = max8925_set_dvm_voltage, + .set_suspend_enable = max8925_set_dvm_enable, + .set_suspend_disable = max8925_set_dvm_disable, +}; + +static struct regulator_ops max8925_regulator_ldo_ops = { + .set_voltage = max8925_set_voltage, + .get_voltage = max8925_get_voltage, + .enable = max8925_enable, + .disable = max8925_disable, + .is_enabled = max8925_is_enabled, +}; + +#define MAX8925_SDV(_id, min, max, step) \ +{ \ + .desc = { \ + .name = "SDV" #_id, \ + .ops = &max8925_regulator_sdv_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MAX8925_ID_SD##_id, \ + .owner = THIS_MODULE, \ + }, \ + .min_uV = min * 1000, \ + .max_uV = max * 1000, \ + .step_uV = step * 1000, \ + .vol_reg = MAX8925_SDV##_id, \ + .vol_shift = 0, \ + .vol_nbits = 6, \ + .enable_reg = MAX8925_SDCTL##_id, \ + .enable_bit = 0, \ +} + +#define MAX8925_LDO(_id, min, max, step) \ +{ \ + .desc = { \ + .name = "LDO" #_id, \ + .ops = &max8925_regulator_ldo_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MAX8925_ID_LDO##_id, \ + .owner = THIS_MODULE, \ + }, \ + .min_uV = min * 1000, \ + .max_uV = max * 1000, \ + .step_uV = step * 1000, \ + .vol_reg = MAX8925_LDOVOUT##_id, \ + .vol_shift = 0, \ + .vol_nbits = 6, \ + .enable_reg = MAX8925_LDOCTL##_id, \ + .enable_bit = 0, \ +} + +static struct max8925_regulator_info max8925_regulator_info[] = { + MAX8925_SDV(1, 637.5, 1425, 12.5), + MAX8925_SDV(2, 650, 2225, 25), + MAX8925_SDV(3, 750, 3900, 50), + + MAX8925_LDO(1, 750, 3900, 50), + MAX8925_LDO(2, 650, 2250, 25), + MAX8925_LDO(3, 650, 2250, 25), + MAX8925_LDO(4, 750, 3900, 50), + MAX8925_LDO(5, 750, 3900, 50), + MAX8925_LDO(6, 750, 3900, 50), + MAX8925_LDO(7, 750, 3900, 50), + MAX8925_LDO(8, 750, 3900, 50), + MAX8925_LDO(9, 750, 3900, 50), + MAX8925_LDO(10, 750, 3900, 50), + MAX8925_LDO(11, 750, 3900, 50), + MAX8925_LDO(12, 750, 3900, 50), + MAX8925_LDO(13, 750, 3900, 50), + MAX8925_LDO(14, 750, 3900, 50), + MAX8925_LDO(15, 750, 3900, 50), + MAX8925_LDO(16, 750, 3900, 50), + MAX8925_LDO(17, 650, 2250, 25), + MAX8925_LDO(18, 650, 2250, 25), + MAX8925_LDO(19, 750, 3900, 50), + MAX8925_LDO(20, 750, 3900, 50), +}; + +static inline struct max8925_regulator_info *find_regulator_info(int id) +{ + struct max8925_regulator_info *ri; + int i; + + for (i = 0; i < ARRAY_SIZE(max8925_regulator_info); i++) { + ri = &max8925_regulator_info[i]; + if (ri->desc.id == id) + return ri; + } + return NULL; +} + +static int __devinit max8925_regulator_probe(struct platform_device *pdev) +{ + struct max8925_chip *chip = dev_get_drvdata(pdev->dev.parent); + struct max8925_platform_data *pdata = chip->dev->platform_data; + struct max8925_regulator_info *ri = NULL; + struct regulator_dev *rdev; + + ri = find_regulator_info(pdev->id); + if (ri == NULL) { + dev_err(&pdev->dev, "invalid regulator ID specified\n"); + return -EINVAL; + } + ri->i2c = chip->i2c; + ri->chip = chip; + + rdev = regulator_register(&ri->desc, &pdev->dev, + pdata->regulator[pdev->id], ri); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register regulator %s\n", + ri->desc.name); + return PTR_ERR(rdev); + } + + platform_set_drvdata(pdev, rdev); + return 0; +} + +static int __devexit max8925_regulator_remove(struct platform_device *pdev) +{ + struct regulator_dev *rdev = platform_get_drvdata(pdev); + + regulator_unregister(rdev); + return 0; +} + +static struct platform_driver max8925_regulator_driver = { + .driver = { + .name = "max8925-regulator", + .owner = THIS_MODULE, + }, + .probe = max8925_regulator_probe, + .remove = __devexit_p(max8925_regulator_remove), +}; + +static int __init max8925_regulator_init(void) +{ + return platform_driver_register(&max8925_regulator_driver); +} +subsys_initcall(max8925_regulator_init); + +static void __exit max8925_regulator_exit(void) +{ + platform_driver_unregister(&max8925_regulator_driver); +} +module_exit(max8925_regulator_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Haojian Zhuang "); +MODULE_DESCRIPTION("Regulator Driver for Maxim 8925 PMIC"); +MODULE_ALIAS("platform:max8925-regulator"); + -- cgit v1.2.3 From 6048a3dd2371c58611ea0ab8b306f8f1469399ae Mon Sep 17 00:00:00 2001 From: Cory Maccarrone Date: Tue, 19 Jan 2010 11:22:45 +0100 Subject: mfd: Add HTCPLD driver This change introduces a driver for the HTC PLD chip found on some smartphones, such as the HTC Wizard and HTC Herald. It works through the I2C bus and acts as a GPIO extender. Specifically: * it can have several sub-devices, each with its own I2C address * Each sub-device provides 8 output and 8 input pins * The chip attaches to one GPIO to signal when any of the input GPIOs change -- at which point all chips must be scanned for changes This driver implements the GPIOs throught the kernel's GPIO and IRQ framework. This allows any GPIO-servicing drivers to operate on htcpld pins, such as the gpio-keys and gpio-leds drivers. Signed-off-by: Cory Maccarrone Signed-off-by: Samuel Ortiz --- drivers/mfd/Kconfig | 9 + drivers/mfd/Makefile | 1 + drivers/mfd/htc-i2cpld.c | 710 +++++++++++++++++++++++++++++++++++++++++++++++ include/linux/htcpld.h | 24 ++ 4 files changed, 744 insertions(+) create mode 100644 drivers/mfd/htc-i2cpld.c create mode 100644 include/linux/htcpld.h (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index d63ab2eec661..9bcd447e71e2 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -78,6 +78,15 @@ config HTC_PASIC3 HTC Magician devices, respectively. Actual functionality is handled by the leds-pasic3 and ds1wm drivers. +config HTC_I2CPLD + bool "HTC I2C PLD chip support" + depends on I2C=y + help + If you say yes here you get support for the supposed CPLD + found on omap850 HTC devices like the HTC Wizard and HTC Herald. + This device provides input and output GPIOs through an I2C + interface to one or more sub-chips. + config UCB1400_CORE tristate "Philips UCB1400 Core driver" depends on AC97_BUS diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 261635700243..142d31202b14 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_MFD_SH_MOBILE_SDHI) += sh_mobile_sdhi.o obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o +obj-$(CONFIG_HTC_I2CPLD) += htc-i2cpld.o obj-$(CONFIG_MFD_DM355EVM_MSP) += dm355evm_msp.o diff --git a/drivers/mfd/htc-i2cpld.c b/drivers/mfd/htc-i2cpld.c new file mode 100644 index 000000000000..37b9fdab4f36 --- /dev/null +++ b/drivers/mfd/htc-i2cpld.c @@ -0,0 +1,710 @@ +/* + * htc-i2cpld.c + * Chip driver for an unknown CPLD chip found on omap850 HTC devices like + * the HTC Wizard and HTC Herald. + * The cpld is located on the i2c bus and acts as an input/output GPIO + * extender. + * + * Copyright (C) 2009 Cory Maccarrone + * + * Based on work done in the linwizard project + * Copyright (C) 2008-2009 Angelo Arrifano + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct htcpld_chip { + spinlock_t lock; + + /* chip info */ + u8 reset; + u8 addr; + struct device *dev; + struct i2c_client *client; + + /* Output details */ + u8 cache_out; + struct gpio_chip chip_out; + + /* Input details */ + u8 cache_in; + struct gpio_chip chip_in; + + u16 irqs_enabled; + uint irq_start; + int nirqs; + + /* + * Work structure to allow for setting values outside of any + * possible interrupt context + */ + struct work_struct set_val_work; +}; + +struct htcpld_data { + /* irq info */ + u16 irqs_enabled; + uint irq_start; + int nirqs; + uint chained_irq; + unsigned int int_reset_gpio_hi; + unsigned int int_reset_gpio_lo; + + /* htcpld info */ + struct htcpld_chip *chip; + unsigned int nchips; +}; + +/* There does not appear to be a way to proactively mask interrupts + * on the htcpld chip itself. So, we simply ignore interrupts that + * aren't desired. */ +static void htcpld_mask(unsigned int irq) +{ + struct htcpld_chip *chip = get_irq_chip_data(irq); + chip->irqs_enabled &= ~(1 << (irq - chip->irq_start)); + pr_debug("HTCPLD mask %d %04x\n", irq, chip->irqs_enabled); +} +static void htcpld_unmask(unsigned int irq) +{ + struct htcpld_chip *chip = get_irq_chip_data(irq); + chip->irqs_enabled |= 1 << (irq - chip->irq_start); + pr_debug("HTCPLD unmask %d %04x\n", irq, chip->irqs_enabled); +} + +static int htcpld_set_type(unsigned int irq, unsigned int flags) +{ + struct irq_desc *d = irq_to_desc(irq); + + if (!d) { + pr_err("HTCPLD invalid IRQ: %d\n", irq); + return -EINVAL; + } + + if (flags & ~IRQ_TYPE_SENSE_MASK) + return -EINVAL; + + /* We only allow edge triggering */ + if (flags & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)) + return -EINVAL; + + d->status &= ~IRQ_TYPE_SENSE_MASK; + d->status |= flags; + + return 0; +} + +static struct irq_chip htcpld_muxed_chip = { + .name = "htcpld", + .mask = htcpld_mask, + .unmask = htcpld_unmask, + .set_type = htcpld_set_type, +}; + +/* To properly dispatch IRQ events, we need to read from the + * chip. This is an I2C action that could possibly sleep + * (which is bad in interrupt context) -- so we use a threaded + * interrupt handler to get around that. + */ +static irqreturn_t htcpld_handler(int irq, void *dev) +{ + struct htcpld_data *htcpld = dev; + unsigned int i; + unsigned long flags; + int irqpin; + struct irq_desc *desc; + + if (!htcpld) { + pr_debug("htcpld is null in ISR\n"); + return IRQ_HANDLED; + } + + /* + * For each chip, do a read of the chip and trigger any interrupts + * desired. The interrupts will be triggered from LSB to MSB (i.e. + * bit 0 first, then bit 1, etc.) + * + * For chips that have no interrupt range specified, just skip 'em. + */ + for (i = 0; i < htcpld->nchips; i++) { + struct htcpld_chip *chip = &htcpld->chip[i]; + struct i2c_client *client; + int val; + unsigned long uval, old_val; + + if (!chip) { + pr_debug("chip %d is null in ISR\n", i); + continue; + } + + if (chip->nirqs == 0) + continue; + + client = chip->client; + if (!client) { + pr_debug("client %d is null in ISR\n", i); + continue; + } + + /* Scan the chip */ + val = i2c_smbus_read_byte_data(client, chip->cache_out); + if (val < 0) { + /* Throw a warning and skip this chip */ + dev_warn(chip->dev, "Unable to read from chip: %d\n", + val); + continue; + } + + uval = (unsigned long)val; + + spin_lock_irqsave(&chip->lock, flags); + + /* Save away the old value so we can compare it */ + old_val = chip->cache_in; + + /* Write the new value */ + chip->cache_in = uval; + + spin_unlock_irqrestore(&chip->lock, flags); + + /* + * For each bit in the data (starting at bit 0), trigger + * associated interrupts. + */ + for (irqpin = 0; irqpin < chip->nirqs; irqpin++) { + unsigned oldb, newb; + int flags; + + irq = chip->irq_start + irqpin; + desc = irq_to_desc(irq); + flags = desc->status; + + /* Run the IRQ handler, but only if the bit value + * changed, and the proper flags are set */ + oldb = (old_val >> irqpin) & 1; + newb = (uval >> irqpin) & 1; + + if ((!oldb && newb && (flags & IRQ_TYPE_EDGE_RISING)) || + (oldb && !newb && + (flags & IRQ_TYPE_EDGE_FALLING))) { + pr_debug("fire IRQ %d\n", irqpin); + desc->handle_irq(irq, desc); + } + } + } + + /* + * In order to continue receiving interrupts, the int_reset_gpio must + * be asserted. + */ + if (htcpld->int_reset_gpio_hi) + gpio_set_value(htcpld->int_reset_gpio_hi, 1); + if (htcpld->int_reset_gpio_lo) + gpio_set_value(htcpld->int_reset_gpio_lo, 0); + + return IRQ_HANDLED; +} + +/* + * The GPIO set routines can be called from interrupt context, especially if, + * for example they're attached to the led-gpio framework and a trigger is + * enabled. As such, we declared work above in the htcpld_chip structure, + * and that work is scheduled in the set routine. The kernel can then run + * the I2C functions, which will sleep, in process context. + */ +void htcpld_chip_set(struct gpio_chip *chip, unsigned offset, int val) +{ + struct i2c_client *client; + struct htcpld_chip *chip_data; + unsigned long flags; + + chip_data = container_of(chip, struct htcpld_chip, chip_out); + if (!chip_data) + return; + + client = chip_data->client; + if (client == NULL) + return; + + spin_lock_irqsave(&chip_data->lock, flags); + if (val) + chip_data->cache_out |= (1 << offset); + else + chip_data->cache_out &= ~(1 << offset); + spin_unlock_irqrestore(&chip_data->lock, flags); + + schedule_work(&(chip_data->set_val_work)); +} + +void htcpld_chip_set_ni(struct work_struct *work) +{ + struct htcpld_chip *chip_data; + struct i2c_client *client; + + chip_data = container_of(work, struct htcpld_chip, set_val_work); + client = chip_data->client; + i2c_smbus_read_byte_data(client, chip_data->cache_out); +} + +int htcpld_chip_get(struct gpio_chip *chip, unsigned offset) +{ + struct htcpld_chip *chip_data; + int val = 0; + int is_input = 0; + + /* Try out first */ + chip_data = container_of(chip, struct htcpld_chip, chip_out); + if (!chip_data) { + /* Try in */ + is_input = 1; + chip_data = container_of(chip, struct htcpld_chip, chip_in); + if (!chip_data) + return -EINVAL; + } + + /* Determine if this is an input or output GPIO */ + if (!is_input) + /* Use the output cache */ + val = (chip_data->cache_out >> offset) & 1; + else + /* Use the input cache */ + val = (chip_data->cache_in >> offset) & 1; + + if (val) + return 1; + else + return 0; +} + +static int htcpld_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + htcpld_chip_set(chip, offset, value); + return 0; +} + +static int htcpld_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + /* + * No-op: this function can only be called on the input chip. + * We do however make sure the offset is within range. + */ + return (offset < chip->ngpio) ? 0 : -EINVAL; +} + +int htcpld_chip_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct htcpld_chip *chip_data; + + chip_data = container_of(chip, struct htcpld_chip, chip_in); + + if (offset < chip_data->nirqs) + return chip_data->irq_start + offset; + else + return -EINVAL; +} + +void htcpld_chip_reset(struct i2c_client *client) +{ + struct htcpld_chip *chip_data = i2c_get_clientdata(client); + if (!chip_data) + return; + + i2c_smbus_read_byte_data( + client, (chip_data->cache_out = chip_data->reset)); +} + +static int __devinit htcpld_setup_chip_irq( + struct platform_device *pdev, + int chip_index) +{ + struct htcpld_data *htcpld; + struct device *dev = &pdev->dev; + struct htcpld_core_platform_data *pdata; + struct htcpld_chip *chip; + struct htcpld_chip_platform_data *plat_chip_data; + unsigned int irq, irq_end; + int ret = 0; + + /* Get the platform and driver data */ + pdata = dev->platform_data; + htcpld = platform_get_drvdata(pdev); + chip = &htcpld->chip[chip_index]; + plat_chip_data = &pdata->chip[chip_index]; + + /* Setup irq handlers */ + irq_end = chip->irq_start + chip->nirqs; + for (irq = chip->irq_start; irq < irq_end; irq++) { + set_irq_chip(irq, &htcpld_muxed_chip); + set_irq_chip_data(irq, chip); + set_irq_handler(irq, handle_simple_irq); +#ifdef CONFIG_ARM + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); +#else + set_irq_probe(irq); +#endif + } + + return ret; +} + +static int __devinit htcpld_register_chip_i2c( + struct platform_device *pdev, + int chip_index) +{ + struct htcpld_data *htcpld; + struct device *dev = &pdev->dev; + struct htcpld_core_platform_data *pdata; + struct htcpld_chip *chip; + struct htcpld_chip_platform_data *plat_chip_data; + struct i2c_adapter *adapter; + struct i2c_client *client; + struct i2c_board_info info; + + /* Get the platform and driver data */ + pdata = dev->platform_data; + htcpld = platform_get_drvdata(pdev); + chip = &htcpld->chip[chip_index]; + plat_chip_data = &pdata->chip[chip_index]; + + adapter = i2c_get_adapter(pdata->i2c_adapter_id); + if (adapter == NULL) { + /* Eek, no such I2C adapter! Bail out. */ + dev_warn(dev, "Chip at i2c address 0x%x: Invalid i2c adapter %d\n", + plat_chip_data->addr, pdata->i2c_adapter_id); + return -ENODEV; + } + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_READ_BYTE_DATA)) { + dev_warn(dev, "i2c adapter %d non-functional\n", + pdata->i2c_adapter_id); + return -EINVAL; + } + + memset(&info, 0, sizeof(struct i2c_board_info)); + info.addr = plat_chip_data->addr; + strlcpy(info.type, "htcpld-chip", I2C_NAME_SIZE); + info.platform_data = chip; + + /* Add the I2C device. This calls the probe() function. */ + client = i2c_new_device(adapter, &info); + if (!client) { + /* I2C device registration failed, contineu with the next */ + dev_warn(dev, "Unable to add I2C device for 0x%x\n", + plat_chip_data->addr); + return -ENODEV; + } + + i2c_set_clientdata(client, chip); + snprintf(client->name, I2C_NAME_SIZE, "Chip_0x%d", client->addr); + chip->client = client; + + /* Reset the chip */ + htcpld_chip_reset(client); + chip->cache_in = i2c_smbus_read_byte_data(client, chip->cache_out); + + return 0; +} + +static void __devinit htcpld_unregister_chip_i2c( + struct platform_device *pdev, + int chip_index) +{ + struct htcpld_data *htcpld; + struct htcpld_chip *chip; + + /* Get the platform and driver data */ + htcpld = platform_get_drvdata(pdev); + chip = &htcpld->chip[chip_index]; + + if (chip->client) + i2c_unregister_device(chip->client); +} + +static int __devinit htcpld_register_chip_gpio( + struct platform_device *pdev, + int chip_index) +{ + struct htcpld_data *htcpld; + struct device *dev = &pdev->dev; + struct htcpld_core_platform_data *pdata; + struct htcpld_chip *chip; + struct htcpld_chip_platform_data *plat_chip_data; + struct gpio_chip *gpio_chip; + int ret = 0; + + /* Get the platform and driver data */ + pdata = dev->platform_data; + htcpld = platform_get_drvdata(pdev); + chip = &htcpld->chip[chip_index]; + plat_chip_data = &pdata->chip[chip_index]; + + /* Setup the GPIO chips */ + gpio_chip = &(chip->chip_out); + gpio_chip->label = "htcpld-out"; + gpio_chip->dev = dev; + gpio_chip->owner = THIS_MODULE; + gpio_chip->get = htcpld_chip_get; + gpio_chip->set = htcpld_chip_set; + gpio_chip->direction_input = NULL; + gpio_chip->direction_output = htcpld_direction_output; + gpio_chip->base = plat_chip_data->gpio_out_base; + gpio_chip->ngpio = plat_chip_data->num_gpios; + + gpio_chip = &(chip->chip_in); + gpio_chip->label = "htcpld-in"; + gpio_chip->dev = dev; + gpio_chip->owner = THIS_MODULE; + gpio_chip->get = htcpld_chip_get; + gpio_chip->set = NULL; + gpio_chip->direction_input = htcpld_direction_input; + gpio_chip->direction_output = NULL; + gpio_chip->to_irq = htcpld_chip_to_irq; + gpio_chip->base = plat_chip_data->gpio_in_base; + gpio_chip->ngpio = plat_chip_data->num_gpios; + + /* Add the GPIO chips */ + ret = gpiochip_add(&(chip->chip_out)); + if (ret) { + dev_warn(dev, "Unable to register output GPIOs for 0x%x: %d\n", + plat_chip_data->addr, ret); + return ret; + } + + ret = gpiochip_add(&(chip->chip_in)); + if (ret) { + int error; + + dev_warn(dev, "Unable to register input GPIOs for 0x%x: %d\n", + plat_chip_data->addr, ret); + + error = gpiochip_remove(&(chip->chip_out)); + if (error) + dev_warn(dev, "Error while trying to unregister gpio chip: %d\n", error); + + return ret; + } + + return 0; +} + +static int __devinit htcpld_setup_chips(struct platform_device *pdev) +{ + struct htcpld_data *htcpld; + struct device *dev = &pdev->dev; + struct htcpld_core_platform_data *pdata; + int i; + + /* Get the platform and driver data */ + pdata = dev->platform_data; + htcpld = platform_get_drvdata(pdev); + + /* Setup each chip's output GPIOs */ + htcpld->nchips = pdata->num_chip; + htcpld->chip = kzalloc(sizeof(struct htcpld_chip) * htcpld->nchips, + GFP_KERNEL); + if (!htcpld->chip) { + dev_warn(dev, "Unable to allocate memory for chips\n"); + return -ENOMEM; + } + + /* Add the chips as best we can */ + for (i = 0; i < htcpld->nchips; i++) { + int ret; + + /* Setup the HTCPLD chips */ + htcpld->chip[i].reset = pdata->chip[i].reset; + htcpld->chip[i].cache_out = pdata->chip[i].reset; + htcpld->chip[i].cache_in = 0; + htcpld->chip[i].dev = dev; + htcpld->chip[i].irq_start = pdata->chip[i].irq_base; + htcpld->chip[i].nirqs = pdata->chip[i].num_irqs; + + INIT_WORK(&(htcpld->chip[i].set_val_work), &htcpld_chip_set_ni); + spin_lock_init(&(htcpld->chip[i].lock)); + + /* Setup the interrupts for the chip */ + if (htcpld->chained_irq) { + ret = htcpld_setup_chip_irq(pdev, i); + if (ret) + continue; + } + + /* Register the chip with I2C */ + ret = htcpld_register_chip_i2c(pdev, i); + if (ret) + continue; + + + /* Register the chips with the GPIO subsystem */ + ret = htcpld_register_chip_gpio(pdev, i); + if (ret) { + /* Unregister the chip from i2c and continue */ + htcpld_unregister_chip_i2c(pdev, i); + continue; + } + + dev_info(dev, "Registered chip at 0x%x\n", pdata->chip[i].addr); + } + + return 0; +} + +static int __devinit htcpld_core_probe(struct platform_device *pdev) +{ + struct htcpld_data *htcpld; + struct device *dev = &pdev->dev; + struct htcpld_core_platform_data *pdata; + struct resource *res; + int ret = 0; + + if (!dev) + return -ENODEV; + + pdata = dev->platform_data; + if (!pdata) { + dev_warn(dev, "Platform data not found for htcpld core!\n"); + return -ENXIO; + } + + htcpld = kzalloc(sizeof(struct htcpld_data), GFP_KERNEL); + if (!htcpld) + return -ENOMEM; + + /* Find chained irq */ + ret = -EINVAL; + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res) { + int flags; + htcpld->chained_irq = res->start; + + /* Setup the chained interrupt handler */ + flags = IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING; + ret = request_threaded_irq(htcpld->chained_irq, + NULL, htcpld_handler, + flags, pdev->name, htcpld); + if (ret) { + dev_warn(dev, "Unable to setup chained irq handler: %d\n", ret); + goto fail; + } else + device_init_wakeup(dev, 0); + } + + /* Set the driver data */ + platform_set_drvdata(pdev, htcpld); + + /* Setup the htcpld chips */ + ret = htcpld_setup_chips(pdev); + if (ret) + goto fail; + + /* Request the GPIO(s) for the int reset and set them up */ + if (pdata->int_reset_gpio_hi) { + ret = gpio_request(pdata->int_reset_gpio_hi, "htcpld-core"); + if (ret) { + /* + * If it failed, that sucks, but we can probably + * continue on without it. + */ + dev_warn(dev, "Unable to request int_reset_gpio_hi -- interrupts may not work\n"); + htcpld->int_reset_gpio_hi = 0; + } else { + htcpld->int_reset_gpio_hi = pdata->int_reset_gpio_hi; + gpio_set_value(htcpld->int_reset_gpio_hi, 1); + } + } + + if (pdata->int_reset_gpio_lo) { + ret = gpio_request(pdata->int_reset_gpio_lo, "htcpld-core"); + if (ret) { + /* + * If it failed, that sucks, but we can probably + * continue on without it. + */ + dev_warn(dev, "Unable to request int_reset_gpio_lo -- interrupts may not work\n"); + htcpld->int_reset_gpio_lo = 0; + } else { + htcpld->int_reset_gpio_lo = pdata->int_reset_gpio_lo; + gpio_set_value(htcpld->int_reset_gpio_lo, 0); + } + } + + dev_info(dev, "Initialized successfully\n"); + return 0; + +fail: + kfree(htcpld); + return ret; +} + +/* The I2C Driver -- used internally */ +static const struct i2c_device_id htcpld_chip_id[] = { + { "htcpld-chip", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, htcpld_chip_id); + + +static struct i2c_driver htcpld_chip_driver = { + .driver = { + .name = "htcpld-chip", + }, + .id_table = htcpld_chip_id, +}; + +/* The Core Driver */ +static struct platform_driver htcpld_core_driver = { + .driver = { + .name = "i2c-htcpld", + }, +}; + +static int __init htcpld_core_init(void) +{ + int ret; + + /* Register the I2C Chip driver */ + ret = i2c_add_driver(&htcpld_chip_driver); + if (ret) + return ret; + + /* Probe for our chips */ + return platform_driver_probe(&htcpld_core_driver, htcpld_core_probe); +} + +static void __exit htcpld_core_exit(void) +{ + i2c_del_driver(&htcpld_chip_driver); + platform_driver_unregister(&htcpld_core_driver); +} + +module_init(htcpld_core_init); +module_exit(htcpld_core_exit); + +MODULE_AUTHOR("Cory Maccarrone "); +MODULE_DESCRIPTION("I2C HTC PLD Driver"); +MODULE_LICENSE("GPL"); + diff --git a/include/linux/htcpld.h b/include/linux/htcpld.h new file mode 100644 index 000000000000..ab3f6cb4dddc --- /dev/null +++ b/include/linux/htcpld.h @@ -0,0 +1,24 @@ +#ifndef __LINUX_HTCPLD_H +#define __LINUX_HTCPLD_H + +struct htcpld_chip_platform_data { + unsigned int addr; + unsigned int reset; + unsigned int num_gpios; + unsigned int gpio_out_base; + unsigned int gpio_in_base; + unsigned int irq_base; + unsigned int num_irqs; +}; + +struct htcpld_core_platform_data { + unsigned int int_reset_gpio_hi; + unsigned int int_reset_gpio_lo; + unsigned int i2c_adapter_id; + + struct htcpld_chip_platform_data *chip; + unsigned int num_chip; +}; + +#endif /* __LINUX_HTCPLD_H */ + -- cgit v1.2.3 From 2071db4848ea809887e97248dd3dec02a2e3dd6b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 Jan 2010 11:41:52 +0100 Subject: mfd: Use AB3100 MFD core IRQ for interrupt randomness This reintroduces the entropy sampling of the AB3100 IRQ as the IRQF_SAMPLE_RANDOM is going out according to the feature removal schedule. I'm trying to do this the right way then, so CC:ing some random people for a quick review. We add entropy for interrupt events in the AB3100 which are truly random in nature, like external cables being connected, voltages on batteries dropping below certain ranges, ADC triggers or overheating. Signed-off-by: Linus Walleij Cc: Robin Getz Acked-by: Matt Mackall Signed-off-by: Samuel Ortiz --- drivers/mfd/Kconfig | 4 ++-- drivers/mfd/ab3100-core.c | 17 +++++++++-------- 2 files changed, 11 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 9bcd447e71e2..ea2557bb0bd4 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -329,8 +329,8 @@ config PCF50633_GPIO the PCF50633 chip. config AB3100_CORE - tristate "ST-Ericsson AB3100 Mixed Signal Circuit core functions" - depends on I2C + bool "ST-Ericsson AB3100 Mixed Signal Circuit core functions" + depends on I2C=y default y if ARCH_U300 help Select this to enable the AB3100 Mixed Signal IC core diff --git a/drivers/mfd/ab3100-core.c b/drivers/mfd/ab3100-core.c index aa3824a1b4f2..a2ce3b6af4a2 100644 --- a/drivers/mfd/ab3100-core.c +++ b/drivers/mfd/ab3100-core.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007-2009 ST-Ericsson + * Copyright (C) 2007-2010 ST-Ericsson * License terms: GNU General Public License (GPL) version 2 * Low-level core for exclusive access to the AB3100 IC on the I2C bus * and some basic chip-configuration. @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -376,6 +377,8 @@ static irqreturn_t ab3100_irq_handler(int irq, void *data) u32 fatevent; int err; + add_interrupt_randomness(irq); + err = ab3100_get_register_page_interruptible(ab3100, AB3100_EVENTA1, event_regs, 3); if (err) @@ -720,10 +723,7 @@ static struct platform_device ab3100_##devname##_device = { \ .id = -1, \ } -/* - * This lists all the subdevices and corresponding register - * ranges. - */ +/* This lists all the subdevices */ AB3100_DEVICE(dac, "ab3100-dac"); AB3100_DEVICE(leds, "ab3100-leds"); AB3100_DEVICE(power, "ab3100-power"); @@ -889,10 +889,11 @@ static int __init ab3100_probe(struct i2c_client *client, if (err) goto exit_no_setup; - /* This real unpredictable IRQ is of course sampled for entropy */ err = request_threaded_irq(client->irq, NULL, ab3100_irq_handler, - IRQF_ONESHOT, - "ab3100-core", ab3100); + IRQF_ONESHOT, "ab3100-core", ab3100); + /* This real unpredictable IRQ is of course sampled for entropy */ + rand_initialize_irq(client->irq); + if (err) goto exit_no_irq; -- cgit v1.2.3 From ca229f1b624a72a1c9eb1d94bbca7a0c094a1b8b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 17 Jan 2010 20:57:43 +0100 Subject: mfd: Fix debugfs code in AB3100 OTP driver This fixes the aged and unreachable debugfs code in the AB3100 OTP driver so that it's (A) reachable and (B) works. Bug detected in parallell by Christoph Egger using VAMOS and Robert P. J. Day by his kernel scanning script. Signed-off-by: Linus Walleij Cc: Christoph Egger Cc: Robert P. J. Day Signed-off-by: Samuel Ortiz --- drivers/mfd/ab3100-otp.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/ab3100-otp.c b/drivers/mfd/ab3100-otp.c index 0499b2031a2c..b603469dff69 100644 --- a/drivers/mfd/ab3100-otp.c +++ b/drivers/mfd/ab3100-otp.c @@ -13,6 +13,7 @@ #include #include #include +#include /* The OTP registers */ #define AB3100_OTP0 0xb0 @@ -95,11 +96,10 @@ static int __init ab3100_otp_read(struct ab3100_otp *otp) * This is a simple debugfs human-readable file that dumps out * the contents of the OTP. */ -#ifdef CONFIG_DEBUGFS -static int show_otp(struct seq_file *s, void *v) +#ifdef CONFIG_DEBUG_FS +static int ab3100_show_otp(struct seq_file *s, void *v) { struct ab3100_otp *otp = s->private; - int err; seq_printf(s, "OTP is %s\n", otp->locked ? "LOCKED" : "UNLOCKED"); seq_printf(s, "OTP clock switch startup is %uHz\n", otp->freq); @@ -113,7 +113,7 @@ static int show_otp(struct seq_file *s, void *v) static int ab3100_otp_open(struct inode *inode, struct file *file) { - return single_open(file, ab3100_otp_show, inode->i_private); + return single_open(file, ab3100_show_otp, inode->i_private); } static const struct file_operations ab3100_otp_operations = { @@ -131,13 +131,14 @@ static int __init ab3100_otp_init_debugfs(struct device *dev, &ab3100_otp_operations); if (!otp->debugfs) { dev_err(dev, "AB3100 debugfs OTP file registration failed!\n"); - return err; + return -ENOENT; } + return 0; } static void __exit ab3100_otp_exit_debugfs(struct ab3100_otp *otp) { - debugfs_remove_file(otp->debugfs); + debugfs_remove(otp->debugfs); } #else /* Compile this out if debugfs not selected */ -- cgit v1.2.3 From f7ea2dc59ed46dcd0f1cfaccda02211f4507207b Mon Sep 17 00:00:00 2001 From: Christoph Egger Date: Fri, 15 Jan 2010 15:33:46 +0100 Subject: mfd: Remove leftover from discontinued TWL4030 battery patch The TWL4030_BCI_BATTERY config option originates from a patch to the omap git tree. However inclusion in linux was seemingly rejected and the functionality nears inclusion under a different name so this removes the bits of the old version that made it into the mainline kernel again. Signed-off-by: Christoph Egger Signed-off-by: Samuel Ortiz --- drivers/mfd/twl-core.c | 19 ------------------- include/linux/i2c/twl.h | 7 +------ 2 files changed, 1 insertion(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c index 19a930d06241..d81003f4867e 100644 --- a/drivers/mfd/twl-core.c +++ b/drivers/mfd/twl-core.c @@ -58,13 +58,6 @@ #define DRIVER_NAME "twl" -#if defined(CONFIG_TWL4030_BCI_BATTERY) || \ - defined(CONFIG_TWL4030_BCI_BATTERY_MODULE) -#define twl_has_bci() true -#else -#define twl_has_bci() false -#endif - #if defined(CONFIG_KEYBOARD_TWL4030) || defined(CONFIG_KEYBOARD_TWL4030_MODULE) #define twl_has_keypad() true #else @@ -588,18 +581,6 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features) struct device *child; unsigned sub_chip_id; - if (twl_has_bci() && pdata->bci && - !(features & (TPS_SUBSET | TWL5031))) { - child = add_child(3, "twl4030_bci", - pdata->bci, sizeof(*pdata->bci), - false, - /* irq0 = CHG_PRES, irq1 = BCI */ - pdata->irq_base + BCI_PRES_INTR_OFFSET, - pdata->irq_base + BCI_INTR_OFFSET); - if (IS_ERR(child)) - return PTR_ERR(child); - } - if (twl_has_gpio() && pdata->gpio) { child = add_child(SUB_CHIP_ID1, "twl4030_gpio", pdata->gpio, sizeof(*pdata->gpio), diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index 7897f3096560..9733e9e53f2b 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -605,12 +605,7 @@ int twl4030_sih_setup(int module); #define TWL4030_VAUX3_DEV_GRP 0x1F #define TWL4030_VAUX3_DEDICATED 0x22 -#if defined(CONFIG_TWL4030_BCI_BATTERY) || \ - defined(CONFIG_TWL4030_BCI_BATTERY_MODULE) - extern int twl4030charger_usb_en(int enable); -#else - static inline int twl4030charger_usb_en(int enable) { return 0; } -#endif +static inline int twl4030charger_usb_en(int enable) { return 0; } /*----------------------------------------------------------------------*/ -- cgit v1.2.3 From bef3e20c9f8ce5cb8809cf33494d95a78db07857 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 20 Jan 2010 19:55:34 -0800 Subject: mfd: htc-i2cpld depends on GPIOLIB htc-i2cpld should depend on GPIOLIB, otherwise there are many build errors: drivers/mfd/htc-i2cpld.c:50: error: field 'chip_out' has incomplete type drivers/mfd/htc-i2cpld.c:54: error: field 'chip_in' has incomplete type drivers/mfd/htc-i2cpld.c:243: warning: type defaults to 'int' in declaration of '__mptr' drivers/mfd/htc-i2cpld.c:243: warning: initialization from incompatible pointer type drivers/mfd/htc-i2cpld.c:278: warning: type defaults to 'int' in declaration of '__mptr' drivers/mfd/htc-i2cpld.c:278: warning: initialization from incompatible pointer type drivers/mfd/htc-i2cpld.c:282: warning: type defaults to 'int' in declaration of '__mptr' drivers/mfd/htc-i2cpld.c:282: warning: initialization from incompatible pointer type drivers/mfd/htc-i2cpld.c:315: error: dereferencing pointer to incomplete type drivers/mfd/htc-i2cpld.c:322: warning: type defaults to 'int' in declaration of '__mptr' drivers/mfd/htc-i2cpld.c:322: warning: initialization from incompatible pointer type drivers/mfd/htc-i2cpld.c:467+: error: dereferencing pointer to incomplete type [19X] drivers/mfd/htc-i2cpld.c:490: error: implicit declaration of function 'gpiochip_add' drivers/mfd/htc-i2cpld.c:504: error: implicit declaration of function 'gpiochip_remove' Signed-off-by: Randy Dunlap Signed-off-by: Samuel Ortiz --- drivers/mfd/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index ea2557bb0bd4..a760dbefd27a 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -80,7 +80,7 @@ config HTC_PASIC3 config HTC_I2CPLD bool "HTC I2C PLD chip support" - depends on I2C=y + depends on I2C=y && GPIOLIB help If you say yes here you get support for the supposed CPLD found on omap850 HTC devices like the HTC Wizard and HTC Herald. -- cgit v1.2.3 From 9e50108668a70a9927257298bd4e679300124420 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 29 Jan 2010 18:20:29 +0000 Subject: mfd: Add initial WM8994 support The WM8994 is a highly integrated ultra low power audio hub CODEC. Since it includes on-board regulators and GPIOs it is represented as a multi-function device, though the overwhelming majority of the functionality is provided by the ASoC CODEC driver. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/mfd/Kconfig | 12 + drivers/mfd/Makefile | 1 + drivers/mfd/wm8994-core.c | 537 +++++++++++++++++++++++++++++++++++++++ include/linux/mfd/wm8994/core.h | 54 ++++ include/linux/mfd/wm8994/gpio.h | 72 ++++++ include/linux/mfd/wm8994/pdata.h | 97 +++++++ 6 files changed, 773 insertions(+) create mode 100644 drivers/mfd/wm8994-core.c create mode 100644 include/linux/mfd/wm8994/core.h create mode 100644 include/linux/mfd/wm8994/gpio.h create mode 100644 include/linux/mfd/wm8994/pdata.h (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index a760dbefd27a..64fbe3334eb3 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -295,6 +295,18 @@ config MFD_WM8350_I2C I2C as the control interface. Additional options must be selected to enable support for the functionality of the chip. +config MFD_WM8994 + tristate "Support Wolfson Microelectronics WM8994" + select MFD_CORE + depends on I2C + help + The WM8994 is a highly integrated hi-fi CODEC designed for + smartphone applicatiosn. As well as audio functionality it + has on board GPIO and regulator functionality which is + supported via the relevant subsystems. This driver provides + core support for the WM8994, in order to use the actual + functionaltiy of the device other drivers must be enabled. + config MFD_PCF50633 tristate "Support for NXP PCF50633" depends on I2C diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 142d31202b14..878cac691067 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -25,6 +25,7 @@ wm8350-objs := wm8350-core.o wm8350-regmap.o wm8350-gpio.o wm8350-objs += wm8350-irq.o obj-$(CONFIG_MFD_WM8350) += wm8350.o obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o +obj-$(CONFIG_MFD_WM8994) += wm8994-core.o obj-$(CONFIG_TPS65010) += tps65010.o obj-$(CONFIG_MENELAUS) += menelaus.o diff --git a/drivers/mfd/wm8994-core.c b/drivers/mfd/wm8994-core.c new file mode 100644 index 000000000000..299c1af1334e --- /dev/null +++ b/drivers/mfd/wm8994-core.c @@ -0,0 +1,537 @@ +/* + * wm8994-core.c -- Device access for Wolfson WM8994 + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static int wm8994_read(struct wm8994 *wm8994, unsigned short reg, + int bytes, void *dest) +{ + int ret, i; + u16 *buf = dest; + + BUG_ON(bytes % 2); + BUG_ON(bytes <= 0); + + ret = wm8994->read_dev(wm8994, reg, bytes, dest); + if (ret < 0) + return ret; + + for (i = 0; i < bytes / 2; i++) { + buf[i] = be16_to_cpu(buf[i]); + + dev_vdbg(wm8994->dev, "Read %04x from R%d(0x%x)\n", + buf[i], reg + i, reg + i); + } + + return 0; +} + +/** + * wm8994_reg_read: Read a single WM8994 register. + * + * @wm8994: Device to read from. + * @reg: Register to read. + */ +int wm8994_reg_read(struct wm8994 *wm8994, unsigned short reg) +{ + unsigned short val; + int ret; + + mutex_lock(&wm8994->io_lock); + + ret = wm8994_read(wm8994, reg, 2, &val); + + mutex_unlock(&wm8994->io_lock); + + if (ret < 0) + return ret; + else + return val; +} +EXPORT_SYMBOL_GPL(wm8994_reg_read); + +/** + * wm8994_bulk_read: Read multiple WM8994 registers + * + * @wm8994: Device to read from + * @reg: First register + * @count: Number of registers + * @buf: Buffer to fill. + */ +int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg, + int count, u16 *buf) +{ + int ret; + + mutex_lock(&wm8994->io_lock); + + ret = wm8994_read(wm8994, reg, count * 2, buf); + + mutex_unlock(&wm8994->io_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm8994_bulk_read); + +static int wm8994_write(struct wm8994 *wm8994, unsigned short reg, + int bytes, void *src) +{ + u16 *buf = src; + int i; + + BUG_ON(bytes % 2); + BUG_ON(bytes <= 0); + + for (i = 0; i < bytes / 2; i++) { + dev_vdbg(wm8994->dev, "Write %04x to R%d(0x%x)\n", + buf[i], reg + i, reg + i); + + buf[i] = cpu_to_be16(buf[i]); + } + + return wm8994->write_dev(wm8994, reg, bytes, src); +} + +/** + * wm8994_reg_write: Write a single WM8994 register. + * + * @wm8994: Device to write to. + * @reg: Register to write to. + * @val: Value to write. + */ +int wm8994_reg_write(struct wm8994 *wm8994, unsigned short reg, + unsigned short val) +{ + int ret; + + mutex_lock(&wm8994->io_lock); + + ret = wm8994_write(wm8994, reg, 2, &val); + + mutex_unlock(&wm8994->io_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm8994_reg_write); + +/** + * wm8994_set_bits: Set the value of a bitfield in a WM8994 register + * + * @wm8994: Device to write to. + * @reg: Register to write to. + * @mask: Mask of bits to set. + * @val: Value to set (unshifted) + */ +int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg, + unsigned short mask, unsigned short val) +{ + int ret; + u16 r; + + mutex_lock(&wm8994->io_lock); + + ret = wm8994_read(wm8994, reg, 2, &r); + if (ret < 0) + goto out; + + r &= ~mask; + r |= val; + + ret = wm8994_write(wm8994, reg, 2, &r); + +out: + mutex_unlock(&wm8994->io_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm8994_set_bits); + +static struct mfd_cell wm8994_regulator_devs[] = { + { .name = "wm8994-ldo", .id = 1 }, + { .name = "wm8994-ldo", .id = 2 }, +}; + +static struct mfd_cell wm8994_devs[] = { + { .name = "wm8994-codec" }, + { .name = "wm8994-gpio" }, +}; + +/* + * Supplies for the main bulk of CODEC; the LDO supplies are ignored + * and should be handled via the standard regulator API supply + * management. + */ +static const char *wm8994_main_supplies[] = { + "DBVDD", + "DCVDD", + "AVDD1", + "AVDD2", + "CPVDD", + "SPKVDD1", + "SPKVDD2", +}; + +#ifdef CONFIG_PM +static int wm8994_device_suspend(struct device *dev) +{ + struct wm8994 *wm8994 = dev_get_drvdata(dev); + int ret; + + /* GPIO configuration state is saved here since we may be configuring + * the GPIO alternate functions even if we're not using the gpiolib + * driver for them. + */ + ret = wm8994_read(wm8994, WM8994_GPIO_1, WM8994_NUM_GPIO_REGS * 2, + &wm8994->gpio_regs); + if (ret < 0) + dev_err(dev, "Failed to save GPIO registers: %d\n", ret); + + /* For similar reasons we also stash the regulator states */ + ret = wm8994_read(wm8994, WM8994_LDO_1, WM8994_NUM_LDO_REGS * 2, + &wm8994->ldo_regs); + if (ret < 0) + dev_err(dev, "Failed to save LDO registers: %d\n", ret); + + ret = regulator_bulk_disable(ARRAY_SIZE(wm8994_main_supplies), + wm8994->supplies); + if (ret != 0) { + dev_err(dev, "Failed to disable supplies: %d\n", ret); + return ret; + } + + return 0; +} + +static int wm8994_device_resume(struct device *dev) +{ + struct wm8994 *wm8994 = dev_get_drvdata(dev); + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(wm8994_main_supplies), + wm8994->supplies); + if (ret != 0) { + dev_err(dev, "Failed to enable supplies: %d\n", ret); + return ret; + } + + ret = wm8994_write(wm8994, WM8994_LDO_1, WM8994_NUM_LDO_REGS * 2, + &wm8994->ldo_regs); + if (ret < 0) + dev_err(dev, "Failed to restore LDO registers: %d\n", ret); + + ret = wm8994_write(wm8994, WM8994_GPIO_1, WM8994_NUM_GPIO_REGS * 2, + &wm8994->gpio_regs); + if (ret < 0) + dev_err(dev, "Failed to restore GPIO registers: %d\n", ret); + + return 0; +} +#endif + +#ifdef CONFIG_REGULATOR +static int wm8994_ldo_in_use(struct wm8994_pdata *pdata, int ldo) +{ + struct wm8994_ldo_pdata *ldo_pdata; + + if (!pdata) + return 0; + + ldo_pdata = &pdata->ldo[ldo]; + + if (!ldo_pdata->init_data) + return 0; + + return ldo_pdata->init_data->num_consumer_supplies != 0; +} +#else +static int wm8994_ldo_in_use(struct wm8994_pdata *pdata, int ldo) +{ + return 0; +} +#endif + +/* + * Instantiate the generic non-control parts of the device. + */ +static int wm8994_device_init(struct wm8994 *wm8994, unsigned long id, int irq) +{ + struct wm8994_pdata *pdata = wm8994->dev->platform_data; + int ret, i; + + mutex_init(&wm8994->io_lock); + dev_set_drvdata(wm8994->dev, wm8994); + + /* Add the on-chip regulators first for bootstrapping */ + ret = mfd_add_devices(wm8994->dev, -1, + wm8994_regulator_devs, + ARRAY_SIZE(wm8994_regulator_devs), + NULL, 0); + if (ret != 0) { + dev_err(wm8994->dev, "Failed to add children: %d\n", ret); + goto err; + } + + wm8994->supplies = kzalloc(sizeof(struct regulator_bulk_data) * + ARRAY_SIZE(wm8994_main_supplies), + GFP_KERNEL); + if (!wm8994->supplies) + goto err; + + for (i = 0; i < ARRAY_SIZE(wm8994_main_supplies); i++) + wm8994->supplies[i].supply = wm8994_main_supplies[i]; + + ret = regulator_bulk_get(wm8994->dev, ARRAY_SIZE(wm8994_main_supplies), + wm8994->supplies); + if (ret != 0) { + dev_err(wm8994->dev, "Failed to get supplies: %d\n", ret); + goto err_get; + } + + ret = regulator_bulk_enable(ARRAY_SIZE(wm8994_main_supplies), + wm8994->supplies); + if (ret != 0) { + dev_err(wm8994->dev, "Failed to enable supplies: %d\n", ret); + goto err_supplies; + } + + ret = wm8994_reg_read(wm8994, WM8994_SOFTWARE_RESET); + if (ret < 0) { + dev_err(wm8994->dev, "Failed to read ID register\n"); + goto err_enable; + } + if (ret != 0x8994) { + dev_err(wm8994->dev, "Device is not a WM8994, ID is %x\n", + ret); + ret = -EINVAL; + goto err_enable; + } + + ret = wm8994_reg_read(wm8994, WM8994_CHIP_REVISION); + if (ret < 0) { + dev_err(wm8994->dev, "Failed to read revision register: %d\n", + ret); + goto err_enable; + } + + switch (ret) { + case 0: + case 1: + dev_warn(wm8994->dev, "revision %c not fully supported\n", + 'A' + ret); + break; + default: + dev_info(wm8994->dev, "revision %c\n", 'A' + ret); + break; + } + + + if (pdata) { + wm8994->gpio_base = pdata->gpio_base; + + /* GPIO configuration is only applied if it's non-zero */ + for (i = 0; i < ARRAY_SIZE(pdata->gpio_defaults); i++) { + if (pdata->gpio_defaults[i]) { + wm8994_set_bits(wm8994, WM8994_GPIO_1 + i, + 0xffff, + pdata->gpio_defaults[i]); + } + } + } + + /* In some system designs where the regulators are not in use, + * we can achieve a small reduction in leakage currents by + * floating LDO outputs. This bit makes no difference if the + * LDOs are enabled, it only affects cases where the LDOs were + * in operation and are then disabled. + */ + for (i = 0; i < WM8994_NUM_LDO_REGS; i++) { + if (wm8994_ldo_in_use(pdata, i)) + wm8994_set_bits(wm8994, WM8994_LDO_1 + i, + WM8994_LDO1_DISCH, WM8994_LDO1_DISCH); + else + wm8994_set_bits(wm8994, WM8994_LDO_1 + i, + WM8994_LDO1_DISCH, 0); + } + + ret = mfd_add_devices(wm8994->dev, -1, + wm8994_devs, ARRAY_SIZE(wm8994_devs), + NULL, 0); + if (ret != 0) { + dev_err(wm8994->dev, "Failed to add children: %d\n", ret); + goto err_enable; + } + + return 0; + +err_enable: + regulator_bulk_disable(ARRAY_SIZE(wm8994_main_supplies), + wm8994->supplies); +err_get: + regulator_bulk_free(ARRAY_SIZE(wm8994_main_supplies), wm8994->supplies); +err_supplies: + kfree(wm8994->supplies); +err: + mfd_remove_devices(wm8994->dev); + kfree(wm8994); + return ret; +} + +static void wm8994_device_exit(struct wm8994 *wm8994) +{ + mfd_remove_devices(wm8994->dev); + regulator_bulk_disable(ARRAY_SIZE(wm8994_main_supplies), + wm8994->supplies); + regulator_bulk_free(ARRAY_SIZE(wm8994_main_supplies), wm8994->supplies); + kfree(wm8994->supplies); + kfree(wm8994); +} + +static int wm8994_i2c_read_device(struct wm8994 *wm8994, unsigned short reg, + int bytes, void *dest) +{ + struct i2c_client *i2c = wm8994->control_data; + int ret; + u16 r = cpu_to_be16(reg); + + ret = i2c_master_send(i2c, (unsigned char *)&r, 2); + if (ret < 0) + return ret; + if (ret != 2) + return -EIO; + + ret = i2c_master_recv(i2c, dest, bytes); + if (ret < 0) + return ret; + if (ret != bytes) + return -EIO; + return 0; +} + +/* Currently we allocate the write buffer on the stack; this is OK for + * small writes - if we need to do large writes this will need to be + * revised. + */ +static int wm8994_i2c_write_device(struct wm8994 *wm8994, unsigned short reg, + int bytes, void *src) +{ + struct i2c_client *i2c = wm8994->control_data; + unsigned char msg[bytes + 2]; + int ret; + + reg = cpu_to_be16(reg); + memcpy(&msg[0], ®, 2); + memcpy(&msg[2], src, bytes); + + ret = i2c_master_send(i2c, msg, bytes + 2); + if (ret < 0) + return ret; + if (ret < bytes + 2) + return -EIO; + + return 0; +} + +static int wm8994_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct wm8994 *wm8994; + + wm8994 = kzalloc(sizeof(struct wm8994), GFP_KERNEL); + if (wm8994 == NULL) { + kfree(i2c); + return -ENOMEM; + } + + i2c_set_clientdata(i2c, wm8994); + wm8994->dev = &i2c->dev; + wm8994->control_data = i2c; + wm8994->read_dev = wm8994_i2c_read_device; + wm8994->write_dev = wm8994_i2c_write_device; + + return wm8994_device_init(wm8994, id->driver_data, i2c->irq); +} + +static int wm8994_i2c_remove(struct i2c_client *i2c) +{ + struct wm8994 *wm8994 = i2c_get_clientdata(i2c); + + wm8994_device_exit(wm8994); + + return 0; +} + +#ifdef CONFIG_PM +static int wm8994_i2c_suspend(struct i2c_client *i2c, pm_message_t state) +{ + return wm8994_device_suspend(&i2c->dev); +} + +static int wm8994_i2c_resume(struct i2c_client *i2c) +{ + return wm8994_device_resume(&i2c->dev); +} +#else +#define wm8994_i2c_suspend NULL +#define wm8994_i2c_resume NULL +#endif + +static const struct i2c_device_id wm8994_i2c_id[] = { + { "wm8994", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, wm8994_i2c_id); + +static struct i2c_driver wm8994_i2c_driver = { + .driver = { + .name = "wm8994", + .owner = THIS_MODULE, + }, + .probe = wm8994_i2c_probe, + .remove = wm8994_i2c_remove, + .suspend = wm8994_i2c_suspend, + .resume = wm8994_i2c_resume, + .id_table = wm8994_i2c_id, +}; + +static int __init wm8994_i2c_init(void) +{ + int ret; + + ret = i2c_add_driver(&wm8994_i2c_driver); + if (ret != 0) + pr_err("Failed to register wm8994 I2C driver: %d\n", ret); + + return ret; +} +module_init(wm8994_i2c_init); + +static void __exit wm8994_i2c_exit(void) +{ + i2c_del_driver(&wm8994_i2c_driver); +} +module_exit(wm8994_i2c_exit); + +MODULE_DESCRIPTION("Core support for the WM8994 audio CODEC"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Mark Brown "); diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h new file mode 100644 index 000000000000..b06ff2846748 --- /dev/null +++ b/include/linux/mfd/wm8994/core.h @@ -0,0 +1,54 @@ +/* + * include/linux/mfd/wm8994/core.h -- Core interface for WM8994 + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __MFD_WM8994_CORE_H__ +#define __MFD_WM8994_CORE_H__ + +struct regulator_dev; +struct regulator_bulk_data; + +#define WM8994_NUM_GPIO_REGS 11 +#define WM8994_NUM_LDO_REGS 2 + +struct wm8994 { + struct mutex io_lock; + + struct device *dev; + int (*read_dev)(struct wm8994 *wm8994, unsigned short reg, + int bytes, void *dest); + int (*write_dev)(struct wm8994 *wm8994, unsigned short reg, + int bytes, void *src); + + void *control_data; + + int gpio_base; + + /* Used over suspend/resume */ + u16 ldo_regs[WM8994_NUM_LDO_REGS]; + u16 gpio_regs[WM8994_NUM_GPIO_REGS]; + + struct regulator_dev *dbvdd; + struct regulator_bulk_data *supplies; +}; + +/* Device I/O API */ +int wm8994_reg_read(struct wm8994 *wm8994, unsigned short reg); +int wm8994_reg_write(struct wm8994 *wm8994, unsigned short reg, + unsigned short val); +int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg, + unsigned short mask, unsigned short val); +int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg, + int count, u16 *buf); + +#endif diff --git a/include/linux/mfd/wm8994/gpio.h b/include/linux/mfd/wm8994/gpio.h new file mode 100644 index 000000000000..b4d4c22991e8 --- /dev/null +++ b/include/linux/mfd/wm8994/gpio.h @@ -0,0 +1,72 @@ +/* + * include/linux/mfd/wm8994/gpio.h - GPIO configuration for WM8994 + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __MFD_WM8994_GPIO_H__ +#define __MFD_WM8994_GPIO_H__ + +#define WM8994_GPIO_MAX 11 + +#define WM8994_GP_FN_PIN_SPECIFIC 0 +#define WM8994_GP_FN_GPIO 1 +#define WM8994_GP_FN_SDOUT 2 +#define WM8994_GP_FN_IRQ 3 +#define WM8994_GP_FN_TEMPERATURE 4 +#define WM8994_GP_FN_MICBIAS1_DET 5 +#define WM8994_GP_FN_MICBIAS1_SHORT 6 +#define WM8994_GP_FN_MICBIAS2_DET 7 +#define WM8994_GP_FN_MICBIAS2_SHORT 8 +#define WM8994_GP_FN_FLL1_LOCK 9 +#define WM8994_GP_FN_FLL2_LOCK 10 +#define WM8994_GP_FN_SRC1_LOCK 11 +#define WM8994_GP_FN_SRC2_LOCK 12 +#define WM8994_GP_FN_DRC1_ACT 13 +#define WM8994_GP_FN_DRC2_ACT 14 +#define WM8994_GP_FN_DRC3_ACT 15 +#define WM8994_GP_FN_WSEQ_STATUS 16 +#define WM8994_GP_FN_FIFO_ERROR 17 +#define WM8994_GP_FN_OPCLK 18 + +#define WM8994_GPN_DIR 0x8000 /* GPN_DIR */ +#define WM8994_GPN_DIR_MASK 0x8000 /* GPN_DIR */ +#define WM8994_GPN_DIR_SHIFT 15 /* GPN_DIR */ +#define WM8994_GPN_DIR_WIDTH 1 /* GPN_DIR */ +#define WM8994_GPN_PU 0x4000 /* GPN_PU */ +#define WM8994_GPN_PU_MASK 0x4000 /* GPN_PU */ +#define WM8994_GPN_PU_SHIFT 14 /* GPN_PU */ +#define WM8994_GPN_PU_WIDTH 1 /* GPN_PU */ +#define WM8994_GPN_PD 0x2000 /* GPN_PD */ +#define WM8994_GPN_PD_MASK 0x2000 /* GPN_PD */ +#define WM8994_GPN_PD_SHIFT 13 /* GPN_PD */ +#define WM8994_GPN_PD_WIDTH 1 /* GPN_PD */ +#define WM8994_GPN_POL 0x0400 /* GPN_POL */ +#define WM8994_GPN_POL_MASK 0x0400 /* GPN_POL */ +#define WM8994_GPN_POL_SHIFT 10 /* GPN_POL */ +#define WM8994_GPN_POL_WIDTH 1 /* GPN_POL */ +#define WM8994_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */ +#define WM8994_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */ +#define WM8994_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */ +#define WM8994_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */ +#define WM8994_GPN_DB 0x0100 /* GPN_DB */ +#define WM8994_GPN_DB_MASK 0x0100 /* GPN_DB */ +#define WM8994_GPN_DB_SHIFT 8 /* GPN_DB */ +#define WM8994_GPN_DB_WIDTH 1 /* GPN_DB */ +#define WM8994_GPN_LVL 0x0040 /* GPN_LVL */ +#define WM8994_GPN_LVL_MASK 0x0040 /* GPN_LVL */ +#define WM8994_GPN_LVL_SHIFT 6 /* GPN_LVL */ +#define WM8994_GPN_LVL_WIDTH 1 /* GPN_LVL */ +#define WM8994_GPN_FN_MASK 0x001F /* GPN_FN - [4:0] */ +#define WM8994_GPN_FN_SHIFT 0 /* GPN_FN - [4:0] */ +#define WM8994_GPN_FN_WIDTH 5 /* GPN_FN - [4:0] */ + +#endif diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h new file mode 100644 index 000000000000..70d6a8687dc5 --- /dev/null +++ b/include/linux/mfd/wm8994/pdata.h @@ -0,0 +1,97 @@ +/* + * include/linux/mfd/wm8994/pdata.h -- Platform data for WM8994 + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __MFD_WM8994_PDATA_H__ +#define __MFD_WM8994_PDATA_H__ + +#define WM8994_NUM_LDO 2 +#define WM8994_NUM_GPIO 11 + +struct wm8994_ldo_pdata { + /** GPIOs to enable regulator, 0 or less if not available */ + int enable; + + const char *supply; + struct regulator_init_data *init_data; +}; + +#define WM8994_CONFIGURE_GPIO 0x8000 + +#define WM8994_DRC_REGS 5 +#define WM8994_EQ_REGS 19 + +/** + * DRC configurations are specified with a label and a set of register + * values to write (the enable bits will be ignored). At runtime an + * enumerated control will be presented for each DRC block allowing + * the user to choose the configration to use. + * + * Configurations may be generated by hand or by using the DRC control + * panel provided by the WISCE - see http://www.wolfsonmicro.com/wisce/ + * for details. + */ +struct wm8994_drc_cfg { + const char *name; + u16 regs[WM8994_DRC_REGS]; +}; + +/** + * ReTune Mobile configurations are specified with a label, sample + * rate and set of values to write (the enable bits will be ignored). + * + * Configurations are expected to be generated using the ReTune Mobile + * control panel in WISCE - see http://www.wolfsonmicro.com/wisce/ + */ +struct wm8994_retune_mobile_cfg { + const char *name; + unsigned int rate; + u16 regs[WM8994_EQ_REGS]; +}; + +struct wm8994_pdata { + int gpio_base; + + /** + * Default values for GPIOs if non-zero, WM8994_CONFIGURE_GPIO + * can be used for all zero values. + */ + int gpio_defaults[WM8994_NUM_GPIO]; + + struct wm8994_ldo_pdata ldo[WM8994_NUM_LDO]; + + + int num_drc_cfgs; + struct wm8994_drc_cfg *drc_cfgs; + + int num_retune_mobile_cfgs; + struct wm8994_retune_mobile_cfg *retune_mobile_cfgs; + + /* LINEOUT can be differential or single ended */ + unsigned int lineout1_diff:1; + unsigned int lineout2_diff:1; + + /* Common mode feedback */ + unsigned int lineout1fb:1; + unsigned int lineout2fb:1; + + /* Microphone biases: 0=0.9*AVDD1 1=0.65*AVVD1 */ + unsigned int micbias1_lvl:1; + unsigned int micbias2_lvl:1; + + /* Jack detect threashold levels, see datasheet for values */ + unsigned int jd_scthr:2; + unsigned int jd_thr:2; +}; + +#endif -- cgit v1.2.3 From 2955c309921e23d592ef585cf8e7ded1e11565b7 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 29 Jan 2010 18:20:30 +0000 Subject: gpiolib: Add WM8994 GPIO support The WM8994 has 11 GPIO lines. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/wm8994-gpio.c | 204 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 212 insertions(+) create mode 100644 drivers/gpio/wm8994-gpio.c (limited to 'drivers') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index acac9f60db1d..f42cb317a779 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -192,6 +192,13 @@ config GPIO_WM8350 Say yes here to access the GPIO signals of WM8350 power management chips from Wolfson Microelectronics. +config GPIO_WM8994 + tristate "WM8994 GPIOs" + depends on MFD_WM8994 + help + Say yes here to access the GPIO signals of WM8994 audio hub + CODECs from Wolfson Microelectronics. + config GPIO_ADP5520 tristate "GPIO Support for ADP5520 PMIC" depends on PMIC_ADP5520 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 90b0880923de..594bb70f65af 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -26,3 +26,4 @@ obj-$(CONFIG_GPIO_IT8761E) += it8761e_gpio.o obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o obj-$(CONFIG_GPIO_WM831X) += wm831x-gpio.o obj-$(CONFIG_GPIO_WM8350) += wm8350-gpiolib.o +obj-$(CONFIG_GPIO_WM8994) += wm8994-gpio.o diff --git a/drivers/gpio/wm8994-gpio.c b/drivers/gpio/wm8994-gpio.c new file mode 100644 index 000000000000..de28b4a470ea --- /dev/null +++ b/drivers/gpio/wm8994-gpio.c @@ -0,0 +1,204 @@ +/* + * wm8994-gpio.c -- gpiolib support for Wolfson WM8994 + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +struct wm8994_gpio { + struct wm8994 *wm8994; + struct gpio_chip gpio_chip; +}; + +static inline struct wm8994_gpio *to_wm8994_gpio(struct gpio_chip *chip) +{ + return container_of(chip, struct wm8994_gpio, gpio_chip); +} + +static int wm8994_gpio_direction_in(struct gpio_chip *chip, unsigned offset) +{ + struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip); + struct wm8994 *wm8994 = wm8994_gpio->wm8994; + + return wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset, + WM8994_GPN_DIR, WM8994_GPN_DIR); +} + +static int wm8994_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip); + struct wm8994 *wm8994 = wm8994_gpio->wm8994; + int ret; + + ret = wm8994_reg_read(wm8994, WM8994_GPIO_1 + offset); + if (ret < 0) + return ret; + + if (ret & WM8994_GPN_LVL) + return 1; + else + return 0; +} + +static int wm8994_gpio_direction_out(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip); + struct wm8994 *wm8994 = wm8994_gpio->wm8994; + + return wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset, + WM8994_GPN_DIR, 0); +} + +static void wm8994_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip); + struct wm8994 *wm8994 = wm8994_gpio->wm8994; + + if (value) + value = WM8994_GPN_LVL; + + wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset, WM8994_GPN_LVL, value); +} + +#ifdef CONFIG_DEBUG_FS +static void wm8994_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip); + struct wm8994 *wm8994 = wm8994_gpio->wm8994; + int i; + + for (i = 0; i < chip->ngpio; i++) { + int gpio = i + chip->base; + int reg; + const char *label; + + /* We report the GPIO even if it's not requested since + * we're also reporting things like alternate + * functions which apply even when the GPIO is not in + * use as a GPIO. + */ + label = gpiochip_is_requested(chip, i); + if (!label) + label = "Unrequested"; + + seq_printf(s, " gpio-%-3d (%-20.20s) ", gpio, label); + + reg = wm8994_reg_read(wm8994, WM8994_GPIO_1 + i); + if (reg < 0) { + dev_err(wm8994->dev, + "GPIO control %d read failed: %d\n", + gpio, reg); + seq_printf(s, "\n"); + continue; + } + + /* No decode yet; note that GPIO2 is special */ + seq_printf(s, "(%x)\n", reg); + } +} +#else +#define wm8994_gpio_dbg_show NULL +#endif + +static struct gpio_chip template_chip = { + .label = "wm8994", + .owner = THIS_MODULE, + .direction_input = wm8994_gpio_direction_in, + .get = wm8994_gpio_get, + .direction_output = wm8994_gpio_direction_out, + .set = wm8994_gpio_set, + .dbg_show = wm8994_gpio_dbg_show, + .can_sleep = 1, +}; + +static int __devinit wm8994_gpio_probe(struct platform_device *pdev) +{ + struct wm8994 *wm8994 = dev_get_drvdata(pdev->dev.parent); + struct wm8994_pdata *pdata = wm8994->dev->platform_data; + struct wm8994_gpio *wm8994_gpio; + int ret; + + wm8994_gpio = kzalloc(sizeof(*wm8994_gpio), GFP_KERNEL); + if (wm8994_gpio == NULL) + return -ENOMEM; + + wm8994_gpio->wm8994 = wm8994; + wm8994_gpio->gpio_chip = template_chip; + wm8994_gpio->gpio_chip.ngpio = WM8994_GPIO_MAX; + wm8994_gpio->gpio_chip.dev = &pdev->dev; + if (pdata && pdata->gpio_base) + wm8994_gpio->gpio_chip.base = pdata->gpio_base; + else + wm8994_gpio->gpio_chip.base = -1; + + ret = gpiochip_add(&wm8994_gpio->gpio_chip); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip, %d\n", + ret); + goto err; + } + + platform_set_drvdata(pdev, wm8994_gpio); + + return ret; + +err: + kfree(wm8994_gpio); + return ret; +} + +static int __devexit wm8994_gpio_remove(struct platform_device *pdev) +{ + struct wm8994_gpio *wm8994_gpio = platform_get_drvdata(pdev); + int ret; + + ret = gpiochip_remove(&wm8994_gpio->gpio_chip); + if (ret == 0) + kfree(wm8994_gpio); + + return ret; +} + +static struct platform_driver wm8994_gpio_driver = { + .driver.name = "wm8994-gpio", + .driver.owner = THIS_MODULE, + .probe = wm8994_gpio_probe, + .remove = __devexit_p(wm8994_gpio_remove), +}; + +static int __init wm8994_gpio_init(void) +{ + return platform_driver_register(&wm8994_gpio_driver); +} +subsys_initcall(wm8994_gpio_init); + +static void __exit wm8994_gpio_exit(void) +{ + platform_driver_unregister(&wm8994_gpio_driver); +} +module_exit(wm8994_gpio_exit); + +MODULE_AUTHOR("Mark Brown "); +MODULE_DESCRIPTION("GPIO interface for WM8994"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:wm8994-gpio"); -- cgit v1.2.3 From 1ea933f4cdbb88197139b9e62778beba0120e229 Mon Sep 17 00:00:00 2001 From: Mike Turquette Date: Fri, 5 Feb 2010 09:51:37 +0100 Subject: mfd: Program twl4030 remap_sleep correctly Variable remap was incorrectly referencing remap_off for the remap_sleep case when configuring TWL4030 power scripts. Signed-off-by: Mike Turquette Signed-off-by: Samuel Ortiz --- drivers/mfd/twl4030-power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c index 0815292fdafc..5b045ff4a2c2 100644 --- a/drivers/mfd/twl4030-power.c +++ b/drivers/mfd/twl4030-power.c @@ -405,7 +405,7 @@ static int __init twl4030_configure_resource(struct twl4030_resconfig *rconfig) if (rconfig->remap_sleep != TWL4030_RESCONFIG_UNDEF) { remap &= ~SLEEP_STATE_MASK; - remap |= rconfig->remap_off << SLEEP_STATE_SHIFT; + remap |= rconfig->remap_sleep << SLEEP_STATE_SHIFT; } err = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, -- cgit v1.2.3 From b13c0df517bedbc40cff4ab5f797b08b1111918b Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 25 Jan 2010 06:26:34 -0500 Subject: mfd: Update i2c driver for max8925 Update I2C driver in order to fit all of three I2C components in max8925. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/mfd/max8925-i2c.c | 57 ++++++++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 28 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/max8925-i2c.c b/drivers/mfd/max8925-i2c.c index 942068e730f9..c0b883c14f41 100644 --- a/drivers/mfd/max8925-i2c.c +++ b/drivers/mfd/max8925-i2c.c @@ -14,27 +14,23 @@ #include #include +#define RTC_I2C_ADDR 0x68 +#define ADC_I2C_ADDR 0x47 + static inline int max8925_read_device(struct i2c_client *i2c, int reg, int bytes, void *dest) { - unsigned char data; - unsigned char *buf; int ret; - buf = kzalloc(bytes + 1, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - data = (unsigned char)reg; - ret = i2c_master_send(i2c, &data, 1); - if (ret < 0) - return ret; - - ret = i2c_master_recv(i2c, buf, bytes + 1); - if (ret < 0) - return ret; - memcpy(dest, buf, bytes); - return 0; + if (bytes > 1) + ret = i2c_smbus_read_i2c_block_data(i2c, reg, bytes, dest); + else { + ret = i2c_smbus_read_byte_data(i2c, reg); + if (ret < 0) + return ret; + *(unsigned char *)dest = (unsigned char)ret; + } + return ret; } static inline int max8925_write_device(struct i2c_client *i2c, @@ -55,7 +51,7 @@ static inline int max8925_write_device(struct i2c_client *i2c, int max8925_reg_read(struct i2c_client *i2c, int reg) { struct max8925_chip *chip = i2c_get_clientdata(i2c); - unsigned char data; + unsigned char data = 0; int ret; mutex_lock(&chip->io_lock); @@ -134,7 +130,7 @@ EXPORT_SYMBOL(max8925_set_bits); static const struct i2c_device_id max8925_id_table[] = { { "max8925", 0 }, - {} + { }, }; MODULE_DEVICE_TABLE(i2c, max8925_id_table); @@ -142,27 +138,28 @@ static int __devinit max8925_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct max8925_platform_data *pdata = client->dev.platform_data; - struct max8925_chip *chip; + static struct max8925_chip *chip; if (!pdata) { pr_info("%s: platform data is missing\n", __func__); return -EINVAL; } - if ((pdata->chip_id <= MAX8925_INVALID) - || (pdata->chip_id >= MAX8925_MAX)) { - pr_info("#%s: wrong chip identification\n", __func__); - return -EINVAL; - } chip = kzalloc(sizeof(struct max8925_chip), GFP_KERNEL); if (chip == NULL) return -ENOMEM; chip->i2c = client; - chip->chip_id = pdata->chip_id; - i2c_set_clientdata(client, chip); chip->dev = &client->dev; - mutex_init(&chip->io_lock); + i2c_set_clientdata(client, chip); dev_set_drvdata(chip->dev, chip); + mutex_init(&chip->io_lock); + + chip->rtc = i2c_new_dummy(chip->i2c->adapter, RTC_I2C_ADDR); + i2c_set_clientdata(chip->rtc, chip); + + chip->adc = i2c_new_dummy(chip->i2c->adapter, ADC_I2C_ADDR); + i2c_set_clientdata(chip->adc, chip); + max8925_device_init(chip, pdata); return 0; @@ -173,7 +170,11 @@ static int __devexit max8925_remove(struct i2c_client *client) struct max8925_chip *chip = i2c_get_clientdata(client); max8925_device_exit(chip); - i2c_set_clientdata(client, NULL); + i2c_unregister_device(chip->adc); + i2c_unregister_device(chip->rtc); + i2c_set_clientdata(chip->adc, NULL); + i2c_set_clientdata(chip->rtc, NULL); + i2c_set_clientdata(chip->i2c, NULL); kfree(chip); return 0; } -- cgit v1.2.3 From 1f1cf8f98cf6588365efeaab8e7e7758aaa77f6e Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 5 Feb 2010 16:07:54 +0100 Subject: mfd: Update irq handler in max8925 Update thread irq handler. Simply the interface of using thread irq. Signed-off-by: Haojian Zhuang Acked-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/mfd/Kconfig | 4 +- drivers/mfd/max8925-core.c | 678 ++++++++++++++++++++++++++++++-------------- include/linux/mfd/max8925.h | 139 ++++++--- 3 files changed, 564 insertions(+), 257 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 64fbe3334eb3..84a68d260772 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -204,8 +204,8 @@ config PMIC_ADP5520 under the corresponding menus. config MFD_MAX8925 - tristate "Maxim Semiconductor MAX8925 PMIC Support" - depends on I2C + bool "Maxim Semiconductor MAX8925 PMIC Support" + depends on I2C=y select MFD_CORE help Say yes here to support for Maxim Semiconductor MAX8925. This is diff --git a/drivers/mfd/max8925-core.c b/drivers/mfd/max8925-core.c index f36c494b80f1..85d63c04749b 100644 --- a/drivers/mfd/max8925-core.c +++ b/drivers/mfd/max8925-core.c @@ -1,7 +1,7 @@ /* * Base driver for Maxim MAX8925 * - * Copyright (C) 2009 Marvell International Ltd. + * Copyright (C) 2009-2010 Marvell International Ltd. * Haojian Zhuang * * This program is free software; you can redistribute it and/or modify @@ -12,14 +12,12 @@ #include #include #include +#include #include #include #include #include -#define IRQ_MODE_STATUS 0 -#define IRQ_MODE_MASK 1 - static struct resource backlight_resources[] = { { .name = "max8925-backlight", @@ -56,6 +54,42 @@ static struct mfd_cell touch_devs[] = { }, }; +static struct resource power_supply_resources[] = { + { + .name = "max8925-power", + .start = MAX8925_CHG_IRQ1, + .end = MAX8925_CHG_IRQ1_MASK, + .flags = IORESOURCE_IO, + }, +}; + +static struct mfd_cell power_devs[] = { + { + .name = "max8925-power", + .num_resources = 1, + .resources = &power_supply_resources[0], + .id = -1, + }, +}; + +static struct resource rtc_resources[] = { + { + .name = "max8925-rtc", + .start = MAX8925_RTC_IRQ, + .end = MAX8925_RTC_IRQ_MASK, + .flags = IORESOURCE_IO, + }, +}; + +static struct mfd_cell rtc_devs[] = { + { + .name = "max8925-rtc", + .num_resources = 1, + .resources = &rtc_resources[0], + .id = -1, + }, +}; + #define MAX8925_REG_RESOURCE(_start, _end) \ { \ .start = MAX8925_##_start, \ @@ -123,203 +157,450 @@ static struct mfd_cell regulator_devs[] = { MAX8925_REG_DEVS(LDO20), }; -static int __get_irq_offset(struct max8925_chip *chip, int irq, int mode, - int *offset, int *bit) +enum { + FLAGS_ADC = 1, /* register in ADC component */ + FLAGS_RTC, /* register in RTC component */ +}; + +struct max8925_irq_data { + int reg; + int mask_reg; + int enable; /* enable or not */ + int offs; /* bit offset in mask register */ + int flags; + int tsc_irq; +}; + +static struct max8925_irq_data max8925_irqs[] = { + [MAX8925_IRQ_VCHG_DC_OVP] = { + .reg = MAX8925_CHG_IRQ1, + .mask_reg = MAX8925_CHG_IRQ1_MASK, + .offs = 1 << 0, + }, + [MAX8925_IRQ_VCHG_DC_F] = { + .reg = MAX8925_CHG_IRQ1, + .mask_reg = MAX8925_CHG_IRQ1_MASK, + .offs = 1 << 1, + }, + [MAX8925_IRQ_VCHG_DC_R] = { + .reg = MAX8925_CHG_IRQ1, + .mask_reg = MAX8925_CHG_IRQ1_MASK, + .offs = 1 << 2, + }, + [MAX8925_IRQ_VCHG_USB_OVP] = { + .reg = MAX8925_CHG_IRQ1, + .mask_reg = MAX8925_CHG_IRQ1_MASK, + .offs = 1 << 3, + }, + [MAX8925_IRQ_VCHG_USB_F] = { + .reg = MAX8925_CHG_IRQ1, + .mask_reg = MAX8925_CHG_IRQ1_MASK, + .offs = 1 << 4, + }, + [MAX8925_IRQ_VCHG_USB_R] = { + .reg = MAX8925_CHG_IRQ1, + .mask_reg = MAX8925_CHG_IRQ1_MASK, + .offs = 1 << 5, + }, + [MAX8925_IRQ_VCHG_THM_OK_R] = { + .reg = MAX8925_CHG_IRQ2, + .mask_reg = MAX8925_CHG_IRQ2_MASK, + .offs = 1 << 0, + }, + [MAX8925_IRQ_VCHG_THM_OK_F] = { + .reg = MAX8925_CHG_IRQ2, + .mask_reg = MAX8925_CHG_IRQ2_MASK, + .offs = 1 << 1, + }, + [MAX8925_IRQ_VCHG_SYSLOW_F] = { + .reg = MAX8925_CHG_IRQ2, + .mask_reg = MAX8925_CHG_IRQ2_MASK, + .offs = 1 << 2, + }, + [MAX8925_IRQ_VCHG_SYSLOW_R] = { + .reg = MAX8925_CHG_IRQ2, + .mask_reg = MAX8925_CHG_IRQ2_MASK, + .offs = 1 << 3, + }, + [MAX8925_IRQ_VCHG_RST] = { + .reg = MAX8925_CHG_IRQ2, + .mask_reg = MAX8925_CHG_IRQ2_MASK, + .offs = 1 << 4, + }, + [MAX8925_IRQ_VCHG_DONE] = { + .reg = MAX8925_CHG_IRQ2, + .mask_reg = MAX8925_CHG_IRQ2_MASK, + .offs = 1 << 5, + }, + [MAX8925_IRQ_VCHG_TOPOFF] = { + .reg = MAX8925_CHG_IRQ2, + .mask_reg = MAX8925_CHG_IRQ2_MASK, + .offs = 1 << 6, + }, + [MAX8925_IRQ_VCHG_TMR_FAULT] = { + .reg = MAX8925_CHG_IRQ2, + .mask_reg = MAX8925_CHG_IRQ2_MASK, + .offs = 1 << 7, + }, + [MAX8925_IRQ_GPM_RSTIN] = { + .reg = MAX8925_ON_OFF_IRQ1, + .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, + .offs = 1 << 0, + }, + [MAX8925_IRQ_GPM_MPL] = { + .reg = MAX8925_ON_OFF_IRQ1, + .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, + .offs = 1 << 1, + }, + [MAX8925_IRQ_GPM_SW_3SEC] = { + .reg = MAX8925_ON_OFF_IRQ1, + .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, + .offs = 1 << 2, + }, + [MAX8925_IRQ_GPM_EXTON_F] = { + .reg = MAX8925_ON_OFF_IRQ1, + .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, + .offs = 1 << 3, + }, + [MAX8925_IRQ_GPM_EXTON_R] = { + .reg = MAX8925_ON_OFF_IRQ1, + .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, + .offs = 1 << 4, + }, + [MAX8925_IRQ_GPM_SW_1SEC] = { + .reg = MAX8925_ON_OFF_IRQ1, + .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, + .offs = 1 << 5, + }, + [MAX8925_IRQ_GPM_SW_F] = { + .reg = MAX8925_ON_OFF_IRQ1, + .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, + .offs = 1 << 6, + }, + [MAX8925_IRQ_GPM_SW_R] = { + .reg = MAX8925_ON_OFF_IRQ1, + .mask_reg = MAX8925_ON_OFF_IRQ1_MASK, + .offs = 1 << 7, + }, + [MAX8925_IRQ_GPM_SYSCKEN_F] = { + .reg = MAX8925_ON_OFF_IRQ2, + .mask_reg = MAX8925_ON_OFF_IRQ2_MASK, + .offs = 1 << 0, + }, + [MAX8925_IRQ_GPM_SYSCKEN_R] = { + .reg = MAX8925_ON_OFF_IRQ2, + .mask_reg = MAX8925_ON_OFF_IRQ2_MASK, + .offs = 1 << 1, + }, + [MAX8925_IRQ_RTC_ALARM1] = { + .reg = MAX8925_RTC_IRQ, + .mask_reg = MAX8925_RTC_IRQ_MASK, + .offs = 1 << 2, + .flags = FLAGS_RTC, + }, + [MAX8925_IRQ_RTC_ALARM0] = { + .reg = MAX8925_RTC_IRQ, + .mask_reg = MAX8925_RTC_IRQ_MASK, + .offs = 1 << 3, + .flags = FLAGS_RTC, + }, + [MAX8925_IRQ_TSC_STICK] = { + .reg = MAX8925_TSC_IRQ, + .mask_reg = MAX8925_TSC_IRQ_MASK, + .offs = 1 << 0, + .flags = FLAGS_ADC, + .tsc_irq = 1, + }, + [MAX8925_IRQ_TSC_NSTICK] = { + .reg = MAX8925_TSC_IRQ, + .mask_reg = MAX8925_TSC_IRQ_MASK, + .offs = 1 << 1, + .flags = FLAGS_ADC, + .tsc_irq = 1, + }, +}; + +static inline struct max8925_irq_data *irq_to_max8925(struct max8925_chip *chip, + int irq) { - if (!offset || !bit) - return -EINVAL; + return &max8925_irqs[irq - chip->irq_base]; +} - switch (chip->chip_id) { - case MAX8925_GPM: - *bit = irq % BITS_PER_BYTE; - if (irq < (BITS_PER_BYTE << 1)) { /* irq = [0,15] */ - *offset = (mode) ? MAX8925_CHG_IRQ1_MASK - : MAX8925_CHG_IRQ1; - if (irq >= BITS_PER_BYTE) - (*offset)++; - } else { /* irq = [16,31] */ - *offset = (mode) ? MAX8925_ON_OFF_IRQ1_MASK - : MAX8925_ON_OFF_IRQ1; - if (irq >= (BITS_PER_BYTE * 3)) - (*offset)++; +static irqreturn_t max8925_irq(int irq, void *data) +{ + struct max8925_chip *chip = data; + struct max8925_irq_data *irq_data; + struct i2c_client *i2c; + int read_reg = -1, value = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) { + irq_data = &max8925_irqs[i]; + /* TSC IRQ should be serviced in max8925_tsc_irq() */ + if (irq_data->tsc_irq) + continue; + if (irq_data->flags == FLAGS_RTC) + i2c = chip->rtc; + else if (irq_data->flags == FLAGS_ADC) + i2c = chip->adc; + else + i2c = chip->i2c; + if (read_reg != irq_data->reg) { + read_reg = irq_data->reg; + value = max8925_reg_read(i2c, irq_data->reg); } - break; - case MAX8925_ADC: - *bit = irq % BITS_PER_BYTE; - *offset = (mode) ? MAX8925_TSC_IRQ_MASK : MAX8925_TSC_IRQ; - break; - default: - goto out; + if (value & irq_data->enable) + handle_nested_irq(chip->irq_base + i); } - return 0; -out: - dev_err(chip->dev, "Wrong irq #%d is assigned\n", irq); - return -EINVAL; + return IRQ_HANDLED; } -static int __check_irq(int irq) +static irqreturn_t max8925_tsc_irq(int irq, void *data) { - if ((irq < 0) || (irq >= MAX8925_NUM_IRQ)) - return -EINVAL; - return 0; + struct max8925_chip *chip = data; + struct max8925_irq_data *irq_data; + struct i2c_client *i2c; + int read_reg = -1, value = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) { + irq_data = &max8925_irqs[i]; + /* non TSC IRQ should be serviced in max8925_irq() */ + if (!irq_data->tsc_irq) + continue; + if (irq_data->flags == FLAGS_RTC) + i2c = chip->rtc; + else if (irq_data->flags == FLAGS_ADC) + i2c = chip->adc; + else + i2c = chip->i2c; + if (read_reg != irq_data->reg) { + read_reg = irq_data->reg; + value = max8925_reg_read(i2c, irq_data->reg); + } + if (value & irq_data->enable) + handle_nested_irq(chip->irq_base + i); + } + return IRQ_HANDLED; } -int max8925_mask_irq(struct max8925_chip *chip, int irq) +static void max8925_irq_lock(unsigned int irq) { - int offset, bit, ret; + struct max8925_chip *chip = get_irq_chip_data(irq); - ret = __get_irq_offset(chip, irq, IRQ_MODE_MASK, &offset, &bit); - if (ret < 0) - return ret; - ret = max8925_set_bits(chip->i2c, offset, 1 << bit, 1 << bit); - return ret; + mutex_lock(&chip->irq_lock); } -int max8925_unmask_irq(struct max8925_chip *chip, int irq) +static void max8925_irq_sync_unlock(unsigned int irq) { - int offset, bit, ret; + struct max8925_chip *chip = get_irq_chip_data(irq); + struct max8925_irq_data *irq_data; + static unsigned char cache_chg[2] = {0xff, 0xff}; + static unsigned char cache_on[2] = {0xff, 0xff}; + static unsigned char cache_rtc = 0xff, cache_tsc = 0xff; + unsigned char irq_chg[2], irq_on[2]; + unsigned char irq_rtc, irq_tsc; + int i; + + /* Load cached value. In initial, all IRQs are masked */ + irq_chg[0] = cache_chg[0]; + irq_chg[1] = cache_chg[1]; + irq_on[0] = cache_on[0]; + irq_on[1] = cache_on[1]; + irq_rtc = cache_rtc; + irq_tsc = cache_tsc; + for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) { + irq_data = &max8925_irqs[i]; + switch (irq_data->mask_reg) { + case MAX8925_CHG_IRQ1_MASK: + irq_chg[0] &= irq_data->enable; + break; + case MAX8925_CHG_IRQ2_MASK: + irq_chg[1] &= irq_data->enable; + break; + case MAX8925_ON_OFF_IRQ1_MASK: + irq_on[0] &= irq_data->enable; + break; + case MAX8925_ON_OFF_IRQ2_MASK: + irq_on[1] &= irq_data->enable; + break; + case MAX8925_RTC_IRQ_MASK: + irq_rtc &= irq_data->enable; + break; + case MAX8925_TSC_IRQ_MASK: + irq_tsc &= irq_data->enable; + break; + default: + dev_err(chip->dev, "wrong IRQ\n"); + break; + } + } + /* update mask into registers */ + if (cache_chg[0] != irq_chg[0]) { + cache_chg[0] = irq_chg[0]; + max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, + irq_chg[0]); + } + if (cache_chg[1] != irq_chg[1]) { + cache_chg[1] = irq_chg[1]; + max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK, + irq_chg[1]); + } + if (cache_on[0] != irq_on[0]) { + cache_on[0] = irq_on[0]; + max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, + irq_on[0]); + } + if (cache_on[1] != irq_on[1]) { + cache_on[1] = irq_on[1]; + max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, + irq_on[1]); + } + if (cache_rtc != irq_rtc) { + cache_rtc = irq_rtc; + max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, irq_rtc); + } + if (cache_tsc != irq_tsc) { + cache_tsc = irq_tsc; + max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, irq_tsc); + } - ret = __get_irq_offset(chip, irq, IRQ_MODE_MASK, &offset, &bit); - if (ret < 0) - return ret; - ret = max8925_set_bits(chip->i2c, offset, 1 << bit, 0); - return ret; + mutex_unlock(&chip->irq_lock); } -#define INT_STATUS_NUM (MAX8925_NUM_IRQ / BITS_PER_BYTE) - -static irqreturn_t max8925_irq_thread(int irq, void *data) +static void max8925_irq_enable(unsigned int irq) { - struct max8925_chip *chip = data; - unsigned long irq_status[INT_STATUS_NUM]; - unsigned char status_buf[INT_STATUS_NUM << 1]; - int i, ret; - - memset(irq_status, 0, sizeof(unsigned long) * INT_STATUS_NUM); - - /* all these interrupt status registers are read-only */ - switch (chip->chip_id) { - case MAX8925_GPM: - ret = max8925_bulk_read(chip->i2c, MAX8925_CHG_IRQ1, - 4, status_buf); - if (ret < 0) - goto out; - ret = max8925_bulk_read(chip->i2c, MAX8925_ON_OFF_IRQ1, - 2, &status_buf[4]); - if (ret < 0) - goto out; - ret = max8925_bulk_read(chip->i2c, MAX8925_ON_OFF_IRQ2, - 2, &status_buf[6]); - if (ret < 0) - goto out; - /* clear masked interrupt status */ - status_buf[0] &= (~status_buf[2] & CHG_IRQ1_MASK); - irq_status[0] |= status_buf[0]; - status_buf[1] &= (~status_buf[3] & CHG_IRQ2_MASK); - irq_status[0] |= (status_buf[1] << BITS_PER_BYTE); - status_buf[4] &= (~status_buf[5] & ON_OFF_IRQ1_MASK); - irq_status[0] |= (status_buf[4] << (BITS_PER_BYTE * 2)); - status_buf[6] &= (~status_buf[7] & ON_OFF_IRQ2_MASK); - irq_status[0] |= (status_buf[6] << (BITS_PER_BYTE * 3)); - break; - case MAX8925_ADC: - ret = max8925_bulk_read(chip->i2c, MAX8925_TSC_IRQ, - 2, status_buf); - if (ret < 0) - goto out; - /* clear masked interrupt status */ - status_buf[0] &= (~status_buf[1] & TSC_IRQ_MASK); - irq_status[0] |= status_buf[0]; - break; - default: - goto out; - } - - for_each_bit(i, &irq_status[0], MAX8925_NUM_IRQ) { - clear_bit(i, irq_status); - dev_dbg(chip->dev, "Servicing IRQ #%d in %s\n", i, chip->name); - - mutex_lock(&chip->irq_lock); - if (chip->irq[i].handler) - chip->irq[i].handler(i, chip->irq[i].data); - else { - max8925_mask_irq(chip, i); - dev_err(chip->dev, "Noboday cares IRQ #%d in %s. " - "Now mask it.\n", i, chip->name); - } - mutex_unlock(&chip->irq_lock); - } -out: - return IRQ_HANDLED; + struct max8925_chip *chip = get_irq_chip_data(irq); + max8925_irqs[irq - chip->irq_base].enable + = max8925_irqs[irq - chip->irq_base].offs; } -int max8925_request_irq(struct max8925_chip *chip, int irq, - irq_handler_t handler, void *data) +static void max8925_irq_disable(unsigned int irq) { - if ((__check_irq(irq) < 0) || !handler) - return -EINVAL; - - mutex_lock(&chip->irq_lock); - chip->irq[irq].handler = handler; - chip->irq[irq].data = data; - mutex_unlock(&chip->irq_lock); - return 0; + struct max8925_chip *chip = get_irq_chip_data(irq); + max8925_irqs[irq - chip->irq_base].enable = 0; } -EXPORT_SYMBOL(max8925_request_irq); -int max8925_free_irq(struct max8925_chip *chip, int irq) +static struct irq_chip max8925_irq_chip = { + .name = "max8925", + .bus_lock = max8925_irq_lock, + .bus_sync_unlock = max8925_irq_sync_unlock, + .enable = max8925_irq_enable, + .disable = max8925_irq_disable, +}; + +static int max8925_irq_init(struct max8925_chip *chip, int irq, + struct max8925_platform_data *pdata) { - if (__check_irq(irq) < 0) + unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT; + struct irq_desc *desc; + int i, ret; + int __irq; + + if (!pdata || !pdata->irq_base) { + dev_warn(chip->dev, "No interrupt support on IRQ base\n"); return -EINVAL; + } + /* clear all interrupts */ + max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ1); + max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ2); + max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ1); + max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ2); + max8925_reg_read(chip->rtc, MAX8925_RTC_IRQ); + max8925_reg_read(chip->adc, MAX8925_TSC_IRQ); + /* mask all interrupts */ + max8925_reg_write(chip->rtc, MAX8925_ALARM0_CNTL, 0); + max8925_reg_write(chip->rtc, MAX8925_ALARM1_CNTL, 0); + max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, 0xff); + max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK, 0xff); + max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff); + max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, 0xff); + max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, 0xff); + max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, 0xff); + + mutex_init(&chip->irq_lock); + chip->core_irq = irq; + chip->irq_base = pdata->irq_base; + desc = irq_to_desc(chip->core_irq); + + /* register with genirq */ + for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) { + __irq = i + chip->irq_base; + set_irq_chip_data(__irq, chip); + set_irq_chip_and_handler(__irq, &max8925_irq_chip, + handle_edge_irq); + set_irq_nested_thread(__irq, 1); +#ifdef CONFIG_ARM + set_irq_flags(__irq, IRQF_VALID); +#else + set_irq_noprobe(__irq); +#endif + } + if (!irq) { + dev_warn(chip->dev, "No interrupt support on core IRQ\n"); + goto tsc_irq; + } - mutex_lock(&chip->irq_lock); - chip->irq[irq].handler = NULL; - chip->irq[irq].data = NULL; - mutex_unlock(&chip->irq_lock); + ret = request_threaded_irq(irq, NULL, max8925_irq, flags, + "max8925", chip); + if (ret) { + dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret); + chip->core_irq = 0; + } +tsc_irq: + if (!pdata->tsc_irq) { + dev_warn(chip->dev, "No interrupt support on TSC IRQ\n"); + return 0; + } + chip->tsc_irq = pdata->tsc_irq; + + ret = request_threaded_irq(chip->tsc_irq, NULL, max8925_tsc_irq, + flags, "max8925-tsc", chip); + if (ret) { + dev_err(chip->dev, "Failed to request TSC IRQ: %d\n", ret); + chip->tsc_irq = 0; + } return 0; } -EXPORT_SYMBOL(max8925_free_irq); -static int __devinit device_gpm_init(struct max8925_chip *chip, - struct i2c_client *i2c, - struct max8925_platform_data *pdata) +int __devinit max8925_device_init(struct max8925_chip *chip, + struct max8925_platform_data *pdata) { int ret; - /* mask all IRQs */ - ret = max8925_set_bits(i2c, MAX8925_CHG_IRQ1_MASK, 0x7, 0x7); - if (ret < 0) - goto out; - ret = max8925_set_bits(i2c, MAX8925_CHG_IRQ2_MASK, 0xff, 0xff); - if (ret < 0) - goto out; - ret = max8925_set_bits(i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff, 0xff); - if (ret < 0) - goto out; - ret = max8925_set_bits(i2c, MAX8925_ON_OFF_IRQ2_MASK, 0x3, 0x3); - if (ret < 0) - goto out; - - chip->name = "GPM"; - memset(chip->irq, 0, sizeof(struct max8925_irq) * MAX8925_NUM_IRQ); - ret = request_threaded_irq(i2c->irq, NULL, max8925_irq_thread, - IRQF_ONESHOT | IRQF_TRIGGER_LOW, - "max8925-gpm", chip); - if (ret < 0) { - dev_err(chip->dev, "Failed to request IRQ #%d.\n", i2c->irq); - goto out; + max8925_irq_init(chip, chip->i2c->irq, pdata); + + if (pdata && (pdata->power || pdata->touch)) { + /* enable ADC to control internal reference */ + max8925_set_bits(chip->i2c, MAX8925_RESET_CNFG, 1, 1); + /* enable internal reference for ADC */ + max8925_set_bits(chip->adc, MAX8925_TSC_CNFG1, 3, 2); + /* check for internal reference IRQ */ + do { + ret = max8925_reg_read(chip->adc, MAX8925_TSC_IRQ); + } while (ret & MAX8925_NREF_OK); + /* enaable ADC scheduler, interval is 1 second */ + max8925_set_bits(chip->adc, MAX8925_ADC_SCHED, 3, 2); } - chip->chip_irq = i2c->irq; - /* enable hard-reset for ONKEY power-off */ - max8925_set_bits(i2c, MAX8925_SYSENSEL, 0x80, 0x80); + /* enable Momentary Power Loss */ + max8925_set_bits(chip->rtc, MAX8925_MPL_CNTL, 1 << 4, 1 << 4); - ret = mfd_add_devices(chip->dev, 0, ®ulator_devs[0], - ARRAY_SIZE(regulator_devs), - ®ulator_resources[0], 0); + ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0], + ARRAY_SIZE(rtc_devs), + &rtc_resources[0], 0); if (ret < 0) { - dev_err(chip->dev, "Failed to add regulator subdev\n"); - goto out_irq; + dev_err(chip->dev, "Failed to add rtc subdev\n"); + goto out; + } + if (pdata && pdata->regulator[0]) { + ret = mfd_add_devices(chip->dev, 0, ®ulator_devs[0], + ARRAY_SIZE(regulator_devs), + ®ulator_resources[0], 0); + if (ret < 0) { + dev_err(chip->dev, "Failed to add regulator subdev\n"); + goto out_dev; + } } if (pdata && pdata->backlight) { @@ -331,35 +612,17 @@ static int __devinit device_gpm_init(struct max8925_chip *chip, goto out_dev; } } - return 0; -out_dev: - mfd_remove_devices(chip->dev); -out_irq: - if (chip->chip_irq) - free_irq(chip->chip_irq, chip); -out: - return ret; -} - -static int __devinit device_adc_init(struct max8925_chip *chip, - struct i2c_client *i2c, - struct max8925_platform_data *pdata) -{ - int ret; - - /* mask all IRQs */ - ret = max8925_set_bits(i2c, MAX8925_TSC_IRQ_MASK, 3, 3); - chip->name = "ADC"; - memset(chip->irq, 0, sizeof(struct max8925_irq) * MAX8925_NUM_IRQ); - ret = request_threaded_irq(i2c->irq, NULL, max8925_irq_thread, - IRQF_ONESHOT | IRQF_TRIGGER_LOW, - "max8925-adc", chip); - if (ret < 0) { - dev_err(chip->dev, "Failed to request IRQ #%d.\n", i2c->irq); - goto out; + if (pdata && pdata->power) { + ret = mfd_add_devices(chip->dev, 0, &power_devs[0], + ARRAY_SIZE(power_devs), + &power_supply_resources[0], 0); + if (ret < 0) { + dev_err(chip->dev, "Failed to add power supply " + "subdev\n"); + goto out_dev; + } } - chip->chip_irq = i2c->irq; if (pdata && pdata->touch) { ret = mfd_add_devices(chip->dev, 0, &touch_devs[0], @@ -367,38 +630,27 @@ static int __devinit device_adc_init(struct max8925_chip *chip, &touch_resources[0], 0); if (ret < 0) { dev_err(chip->dev, "Failed to add touch subdev\n"); - goto out_irq; + goto out_dev; } } + return 0; -out_irq: - if (chip->chip_irq) - free_irq(chip->chip_irq, chip); +out_dev: + mfd_remove_devices(chip->dev); out: return ret; } -int __devinit max8925_device_init(struct max8925_chip *chip, - struct max8925_platform_data *pdata) +void __devexit max8925_device_exit(struct max8925_chip *chip) { - switch (chip->chip_id) { - case MAX8925_GPM: - device_gpm_init(chip, chip->i2c, pdata); - break; - case MAX8925_ADC: - device_adc_init(chip, chip->i2c, pdata); - break; - } - return 0; -} - -void max8925_device_exit(struct max8925_chip *chip) -{ - if (chip->chip_irq >= 0) - free_irq(chip->chip_irq, chip); + if (chip->core_irq) + free_irq(chip->core_irq, chip); + if (chip->tsc_irq) + free_irq(chip->tsc_irq, chip); mfd_remove_devices(chip->dev); } + MODULE_DESCRIPTION("PMIC Driver for Maxim MAX8925"); MODULE_AUTHOR("Haojian Zhuang #include /* Unified sub device IDs for MAX8925 */ @@ -39,6 +40,30 @@ enum { MAX8925_ID_LDO18, MAX8925_ID_LDO19, MAX8925_ID_LDO20, + MAX8925_ID_MAX, +}; + +enum { + /* + * Charging current threshold trigger going from fast charge + * to TOPOFF charge. From 5% to 20% of fasting charging current. + */ + MAX8925_TOPOFF_THR_5PER, + MAX8925_TOPOFF_THR_10PER, + MAX8925_TOPOFF_THR_15PER, + MAX8925_TOPOFF_THR_20PER, +}; + +enum { + /* Fast charging current */ + MAX8925_FCHG_85MA, + MAX8925_FCHG_300MA, + MAX8925_FCHG_460MA, + MAX8925_FCHG_600MA, + MAX8925_FCHG_700MA, + MAX8925_FCHG_800MA, + MAX8925_FCHG_900MA, + MAX8925_FCHG_1000MA, }; /* Charger registers */ @@ -46,12 +71,13 @@ enum { #define MAX8925_CHG_IRQ2 (0x7f) #define MAX8925_CHG_IRQ1_MASK (0x80) #define MAX8925_CHG_IRQ2_MASK (0x81) +#define MAX8925_CHG_STATUS (0x82) /* GPM registers */ #define MAX8925_SYSENSEL (0x00) #define MAX8925_ON_OFF_IRQ1 (0x01) #define MAX8925_ON_OFF_IRQ1_MASK (0x02) -#define MAX8925_ON_OFF_STAT (0x03) +#define MAX8925_ON_OFF_STATUS (0x03) #define MAX8925_ON_OFF_IRQ2 (0x0d) #define MAX8925_ON_OFF_IRQ2_MASK (0x0e) #define MAX8925_RESET_CNFG (0x0f) @@ -59,12 +85,18 @@ enum { /* Touch registers */ #define MAX8925_TSC_IRQ (0x00) #define MAX8925_TSC_IRQ_MASK (0x01) +#define MAX8925_TSC_CNFG1 (0x02) +#define MAX8925_ADC_SCHED (0x10) #define MAX8925_ADC_RES_END (0x6f) +#define MAX8925_NREF_OK (1 << 4) + /* RTC registers */ -#define MAX8925_RTC_STATUS (0x1a) +#define MAX8925_ALARM0_CNTL (0x18) +#define MAX8925_ALARM1_CNTL (0x19) #define MAX8925_RTC_IRQ (0x1c) #define MAX8925_RTC_IRQ_MASK (0x1d) +#define MAX8925_MPL_CNTL (0x1e) /* WLED registers */ #define MAX8925_WLED_MODE_CNTL (0x84) @@ -126,45 +158,48 @@ enum { #define TSC_IRQ_MASK (0x03) #define RTC_IRQ_MASK (0x0c) -#define MAX8925_NUM_IRQ (32) +#define MAX8925_GPM_NUM_IRQ (40) +#define MAX8925_ADC_NUM_IRQ (8) +#define MAX8925_NUM_IRQ (MAX8925_GPM_NUM_IRQ \ + + MAX8925_ADC_NUM_IRQ) + +#define MAX8925_MAX_REGULATOR (23) #define MAX8925_NAME_SIZE (32) +/* IRQ definitions */ enum { - MAX8925_INVALID = 0, - MAX8925_RTC, - MAX8925_ADC, - MAX8925_GPM, /* general power management */ - MAX8925_MAX, + MAX8925_IRQ_VCHG_DC_OVP, + MAX8925_IRQ_VCHG_DC_F, + MAX8925_IRQ_VCHG_DC_R, + MAX8925_IRQ_VCHG_USB_OVP, + MAX8925_IRQ_VCHG_USB_F, + MAX8925_IRQ_VCHG_USB_R, + MAX8925_IRQ_VCHG_THM_OK_R, + MAX8925_IRQ_VCHG_THM_OK_F, + MAX8925_IRQ_VCHG_SYSLOW_F, + MAX8925_IRQ_VCHG_SYSLOW_R, + MAX8925_IRQ_VCHG_RST, + MAX8925_IRQ_VCHG_DONE, + MAX8925_IRQ_VCHG_TOPOFF, + MAX8925_IRQ_VCHG_TMR_FAULT, + MAX8925_IRQ_GPM_RSTIN, + MAX8925_IRQ_GPM_MPL, + MAX8925_IRQ_GPM_SW_3SEC, + MAX8925_IRQ_GPM_EXTON_F, + MAX8925_IRQ_GPM_EXTON_R, + MAX8925_IRQ_GPM_SW_1SEC, + MAX8925_IRQ_GPM_SW_F, + MAX8925_IRQ_GPM_SW_R, + MAX8925_IRQ_GPM_SYSCKEN_F, + MAX8925_IRQ_GPM_SYSCKEN_R, + MAX8925_IRQ_RTC_ALARM1, + MAX8925_IRQ_RTC_ALARM0, + MAX8925_IRQ_TSC_STICK, + MAX8925_IRQ_TSC_NSTICK, + MAX8925_NR_IRQS, }; -#define MAX8925_IRQ_VCHG_OVP (0) -#define MAX8925_IRQ_VCHG_F (1) -#define MAX8925_IRQ_VCHG_R (2) -#define MAX8925_IRQ_VCHG_THM_OK_R (8) -#define MAX8925_IRQ_VCHG_THM_OK_F (9) -#define MAX8925_IRQ_VCHG_BATTLOW_F (10) -#define MAX8925_IRQ_VCHG_BATTLOW_R (11) -#define MAX8925_IRQ_VCHG_RST (12) -#define MAX8925_IRQ_VCHG_DONE (13) -#define MAX8925_IRQ_VCHG_TOPOFF (14) -#define MAX8925_IRQ_VCHG_TMR_FAULT (15) -#define MAX8925_IRQ_GPM_RSTIN (16) -#define MAX8925_IRQ_GPM_MPL (17) -#define MAX8925_IRQ_GPM_SW_3SEC (18) -#define MAX8925_IRQ_GPM_EXTON_F (19) -#define MAX8925_IRQ_GPM_EXTON_R (20) -#define MAX8925_IRQ_GPM_SW_1SEC (21) -#define MAX8925_IRQ_GPM_SW_F (22) -#define MAX8925_IRQ_GPM_SW_R (23) -#define MAX8925_IRQ_GPM_SYSCKEN_F (24) -#define MAX8925_IRQ_GPM_SYSCKEN_R (25) - -#define MAX8925_IRQ_TSC_STICK (0) -#define MAX8925_IRQ_TSC_NSTICK (1) - -#define MAX8925_MAX_REGULATOR (23) - struct max8925_irq { irq_handler_t handler; void *data; @@ -172,14 +207,16 @@ struct max8925_irq { struct max8925_chip { struct device *dev; + struct i2c_client *i2c; + struct i2c_client *adc; + struct i2c_client *rtc; + struct max8925_irq irqs[MAX8925_NUM_IRQ]; struct mutex io_lock; struct mutex irq_lock; - struct i2c_client *i2c; - struct max8925_irq irq[MAX8925_NUM_IRQ]; - const char *name; - int chip_id; - int chip_irq; + int irq_base; + int core_irq; + int tsc_irq; }; struct max8925_backlight_pdata { @@ -192,13 +229,25 @@ struct max8925_touch_pdata { unsigned int flags; }; +struct max8925_power_pdata { + int (*set_charger)(int); + unsigned batt_detect:1; + unsigned topoff_threshold:2; + unsigned fast_charge:3; /* charge current */ +}; + +/* + * irq_base: stores IRQ base number of MAX8925 in platform + * tsc_irq: stores IRQ number of MAX8925 TSC + */ struct max8925_platform_data { struct max8925_backlight_pdata *backlight; struct max8925_touch_pdata *touch; + struct max8925_power_pdata *power; struct regulator_init_data *regulator[MAX8925_MAX_REGULATOR]; - int chip_id; - int chip_irq; + int irq_base; + int tsc_irq; }; extern int max8925_reg_read(struct i2c_client *, int); @@ -208,6 +257,12 @@ extern int max8925_bulk_write(struct i2c_client *, int, int, unsigned char *); extern int max8925_set_bits(struct i2c_client *, int, unsigned char, unsigned char); +extern int max8925_request_irq(struct max8925_chip *, int, + irq_handler_t, void *); +extern int max8925_free_irq(struct max8925_chip *, int); +extern int max8925_mask_irq(struct max8925_chip *, int); +extern int max8925_unmask_irq(struct max8925_chip *, int); + extern int max8925_device_init(struct max8925_chip *, struct max8925_platform_data *); extern void max8925_device_exit(struct max8925_chip *); -- cgit v1.2.3 From a39069f6ce6500a5ca39e534108247f25169d8e0 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 25 Jan 2010 06:30:29 -0500 Subject: rtc: Enable rtc in max8925 MAX8925 is a PMIC that contains RTC component. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/rtc/Kconfig | 10 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-max8925.c | 314 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 325 insertions(+) create mode 100644 drivers/rtc/rtc-max8925.c (limited to 'drivers') diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 2bb8a8b7ffaf..6a1303759432 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -175,6 +175,16 @@ config RTC_DRV_MAX6900 This driver can also be built as a module. If so, the module will be called rtc-max6900. +config RTC_DRV_MAX8925 + tristate "Maxim MAX8925" + depends on MFD_MAX8925 + help + If you say yes here you will get support for the + RTC of Maxim MAX8925 PMIC. + + This driver can also be built as a module. If so, the module + will be called rtc-max8925. + config RTC_DRV_RS5C372 tristate "Ricoh R2025S/D, RS5C372A/B, RV5C386, RV5C387A" help diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index b7148afb8f55..44ef194a9573 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_RTC_DRV_M48T59) += rtc-m48t59.o obj-$(CONFIG_RTC_DRV_M48T86) += rtc-m48t86.o obj-$(CONFIG_RTC_MXC) += rtc-mxc.o obj-$(CONFIG_RTC_DRV_MAX6900) += rtc-max6900.o +obj-$(CONFIG_RTC_DRV_MAX8925) += rtc-max8925.o obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o obj-$(CONFIG_RTC_DRV_MC13783) += rtc-mc13783.o obj-$(CONFIG_RTC_DRV_MSM6242) += rtc-msm6242.o diff --git a/drivers/rtc/rtc-max8925.c b/drivers/rtc/rtc-max8925.c new file mode 100644 index 000000000000..acdbb1760187 --- /dev/null +++ b/drivers/rtc/rtc-max8925.c @@ -0,0 +1,314 @@ +/* + * RTC driver for Maxim MAX8925 + * + * Copyright (C) 2009-2010 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +enum { + RTC_SEC = 0, + RTC_MIN, + RTC_HOUR, + RTC_WEEKDAY, + RTC_DATE, + RTC_MONTH, + RTC_YEAR1, + RTC_YEAR2, +}; + +#define MAX8925_RTC_SEC 0x00 +#define MAX8925_RTC_MIN 0x01 +#define MAX8925_RTC_HOUR 0x02 +#define MAX8925_RTC_WEEKDAY 0x03 +#define MAX8925_RTC_DATE 0x04 +#define MAX8925_RTC_MONTH 0x05 +#define MAX8925_RTC_YEAR1 0x06 +#define MAX8925_RTC_YEAR2 0x07 +#define MAX8925_ALARM0_SEC 0x08 +#define MAX8925_ALARM0_MIN 0x09 +#define MAX8925_ALARM0_HOUR 0x0a +#define MAX8925_ALARM0_WEEKDAY 0x0b +#define MAX8925_ALARM0_DATE 0x0c +#define MAX8925_ALARM0_MON 0x0d +#define MAX8925_ALARM0_YEAR1 0x0e +#define MAX8925_ALARM0_YEAR2 0x0f +#define MAX8925_ALARM1_SEC 0x10 +#define MAX8925_ALARM1_MIN 0x11 +#define MAX8925_ALARM1_HOUR 0x12 +#define MAX8925_ALARM1_WEEKDAY 0x13 +#define MAX8925_ALARM1_DATE 0x14 +#define MAX8925_ALARM1_MON 0x15 +#define MAX8925_ALARM1_YEAR1 0x16 +#define MAX8925_ALARM1_YEAR2 0x17 +#define MAX8925_RTC_CNTL 0x1b +#define MAX8925_RTC_STATUS 0x20 + +#define TIME_NUM 8 +#define ALARM_1SEC (1 << 7) +#define HOUR_12 (1 << 7) +#define HOUR_AM_PM (1 << 5) +#define ALARM0_IRQ (1 << 3) +#define ALARM1_IRQ (1 << 2) +#define ALARM0_STATUS (1 << 2) +#define ALARM1_STATUS (1 << 1) + + +struct max8925_rtc_info { + struct rtc_device *rtc_dev; + struct max8925_chip *chip; + struct i2c_client *rtc; + struct device *dev; +}; + +static irqreturn_t rtc_update_handler(int irq, void *data) +{ + struct max8925_rtc_info *info = (struct max8925_rtc_info *)data; + + /* disable ALARM0 except for 1SEC alarm */ + max8925_set_bits(info->rtc, MAX8925_ALARM0_CNTL, 0x7f, 0); + rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); + return IRQ_HANDLED; +} + +static int tm_calc(struct rtc_time *tm, unsigned char *buf, int len) +{ + if (len < TIME_NUM) + return -EINVAL; + tm->tm_year = (buf[RTC_YEAR2] >> 4) * 1000 + + (buf[RTC_YEAR2] & 0xf) * 100 + + (buf[RTC_YEAR1] >> 4) * 10 + + (buf[RTC_YEAR1] & 0xf); + tm->tm_year -= 1900; + tm->tm_mon = ((buf[RTC_MONTH] >> 4) & 0x01) * 10 + + (buf[RTC_MONTH] & 0x0f); + tm->tm_mday = ((buf[RTC_DATE] >> 4) & 0x03) * 10 + + (buf[RTC_DATE] & 0x0f); + tm->tm_wday = buf[RTC_WEEKDAY] & 0x07; + if (buf[RTC_HOUR] & HOUR_12) { + tm->tm_hour = ((buf[RTC_HOUR] >> 4) & 0x1) * 10 + + (buf[RTC_HOUR] & 0x0f); + if (buf[RTC_HOUR] & HOUR_AM_PM) + tm->tm_hour += 12; + } else + tm->tm_hour = ((buf[RTC_HOUR] >> 4) & 0x03) * 10 + + (buf[RTC_HOUR] & 0x0f); + tm->tm_min = ((buf[RTC_MIN] >> 4) & 0x7) * 10 + + (buf[RTC_MIN] & 0x0f); + tm->tm_sec = ((buf[RTC_SEC] >> 4) & 0x7) * 10 + + (buf[RTC_SEC] & 0x0f); + return 0; +} + +static int data_calc(unsigned char *buf, struct rtc_time *tm, int len) +{ + unsigned char high, low; + + if (len < TIME_NUM) + return -EINVAL; + + high = (tm->tm_year + 1900) / 1000; + low = (tm->tm_year + 1900) / 100; + low = low - high * 10; + buf[RTC_YEAR2] = (high << 4) + low; + high = (tm->tm_year + 1900) / 10; + low = tm->tm_year + 1900; + low = low - high * 10; + high = high - (high / 10) * 10; + buf[RTC_YEAR1] = (high << 4) + low; + high = tm->tm_mon / 10; + low = tm->tm_mon; + low = low - high * 10; + buf[RTC_MONTH] = (high << 4) + low; + high = tm->tm_mday / 10; + low = tm->tm_mday; + low = low - high * 10; + buf[RTC_DATE] = (high << 4) + low; + buf[RTC_WEEKDAY] = tm->tm_wday; + high = tm->tm_hour / 10; + low = tm->tm_hour; + low = low - high * 10; + buf[RTC_HOUR] = (high << 4) + low; + high = tm->tm_min / 10; + low = tm->tm_min; + low = low - high * 10; + buf[RTC_MIN] = (high << 4) + low; + high = tm->tm_sec / 10; + low = tm->tm_sec; + low = low - high * 10; + buf[RTC_SEC] = (high << 4) + low; + return 0; +} + +static int max8925_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct max8925_rtc_info *info = dev_get_drvdata(dev); + unsigned char buf[TIME_NUM]; + int ret; + + ret = max8925_bulk_read(info->rtc, MAX8925_RTC_SEC, TIME_NUM, buf); + if (ret < 0) + goto out; + ret = tm_calc(tm, buf, TIME_NUM); +out: + return ret; +} + +static int max8925_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct max8925_rtc_info *info = dev_get_drvdata(dev); + unsigned char buf[TIME_NUM]; + int ret; + + ret = data_calc(buf, tm, TIME_NUM); + if (ret < 0) + goto out; + ret = max8925_bulk_write(info->rtc, MAX8925_RTC_SEC, TIME_NUM, buf); +out: + return ret; +} + +static int max8925_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct max8925_rtc_info *info = dev_get_drvdata(dev); + unsigned char buf[TIME_NUM]; + int ret; + + ret = max8925_bulk_read(info->rtc, MAX8925_ALARM0_SEC, TIME_NUM, buf); + if (ret < 0) + goto out; + ret = tm_calc(&alrm->time, buf, TIME_NUM); + if (ret < 0) + goto out; + ret = max8925_reg_read(info->rtc, MAX8925_RTC_IRQ_MASK); + if (ret < 0) + goto out; + if ((ret & ALARM0_IRQ) == 0) + alrm->enabled = 1; + else + alrm->enabled = 0; + ret = max8925_reg_read(info->rtc, MAX8925_RTC_STATUS); + if (ret < 0) + goto out; + if (ret & ALARM0_STATUS) + alrm->pending = 1; + else + alrm->pending = 0; +out: + return ret; +} + +static int max8925_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct max8925_rtc_info *info = dev_get_drvdata(dev); + unsigned char buf[TIME_NUM]; + int ret; + + ret = data_calc(buf, &alrm->time, TIME_NUM); + if (ret < 0) + goto out; + ret = max8925_bulk_write(info->rtc, MAX8925_ALARM0_SEC, TIME_NUM, buf); + if (ret < 0) + goto out; + /* only enable alarm on year/month/day/hour/min/sec */ + ret = max8925_reg_write(info->rtc, MAX8925_ALARM0_CNTL, 0x77); + if (ret < 0) + goto out; +out: + return ret; +} + +static const struct rtc_class_ops max8925_rtc_ops = { + .read_time = max8925_rtc_read_time, + .set_time = max8925_rtc_set_time, + .read_alarm = max8925_rtc_read_alarm, + .set_alarm = max8925_rtc_set_alarm, +}; + +static int __devinit max8925_rtc_probe(struct platform_device *pdev) +{ + struct max8925_chip *chip = dev_get_drvdata(pdev->dev.parent); + struct max8925_rtc_info *info; + int irq, ret; + + info = kzalloc(sizeof(struct max8925_rtc_info), GFP_KERNEL); + if (!info) + return -ENOMEM; + info->chip = chip; + info->rtc = chip->rtc; + info->dev = &pdev->dev; + irq = chip->irq_base + MAX8925_IRQ_RTC_ALARM0; + + ret = request_threaded_irq(irq, NULL, rtc_update_handler, + IRQF_ONESHOT, "rtc-alarm0", info); + if (ret < 0) { + dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n", + irq, ret); + goto out_irq; + } + + info->rtc_dev = rtc_device_register("max8925-rtc", &pdev->dev, + &max8925_rtc_ops, THIS_MODULE); + ret = PTR_ERR(info->rtc_dev); + if (IS_ERR(info->rtc_dev)) { + dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret); + goto out_rtc; + } + + dev_set_drvdata(&pdev->dev, info); + platform_set_drvdata(pdev, info); + + return 0; +out_rtc: + free_irq(chip->irq_base + MAX8925_IRQ_RTC_ALARM0, info); +out_irq: + kfree(info); + return ret; +} + +static int __devexit max8925_rtc_remove(struct platform_device *pdev) +{ + struct max8925_rtc_info *info = platform_get_drvdata(pdev); + + if (info) { + free_irq(info->chip->irq_base + MAX8925_IRQ_RTC_ALARM0, info); + rtc_device_unregister(info->rtc_dev); + kfree(info); + } + return 0; +} + +static struct platform_driver max8925_rtc_driver = { + .driver = { + .name = "max8925-rtc", + .owner = THIS_MODULE, + }, + .probe = max8925_rtc_probe, + .remove = __devexit_p(max8925_rtc_remove), +}; + +static int __init max8925_rtc_init(void) +{ + return platform_driver_register(&max8925_rtc_driver); +} +module_init(max8925_rtc_init); + +static void __exit max8925_rtc_exit(void) +{ + platform_driver_unregister(&max8925_rtc_driver); +} +module_exit(max8925_rtc_exit); + +MODULE_DESCRIPTION("Maxim MAX8925 RTC driver"); +MODULE_AUTHOR("Haojian Zhuang "); +MODULE_LICENSE("GPL"); + -- cgit v1.2.3 From 28db38888b2a53b6bdd70104c2d2a199632ca507 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 25 Jan 2010 10:38:35 -0500 Subject: power_supply: Enable power supply of max8925 MAX8925 is a PMIC that contains charger component Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/power/Kconfig | 7 + drivers/power/Makefile | 1 + drivers/power/max8925_power.c | 534 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 542 insertions(+) create mode 100644 drivers/power/max8925_power.c (limited to 'drivers') diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index bf1467213954..faaa9b4d0d07 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -29,6 +29,13 @@ config APM_POWER Say Y here to enable support APM status emulation using battery class devices. +config MAX8925_POWER + tristate "MAX8925 battery charger support" + depends on MFD_MAX8925 + help + Say Y here to enable support for the battery charger in the Maxim + MAX8925 PMIC. + config WM831X_BACKUP tristate "WM831X backup battery charger support" depends on MFD_WM831X diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 573597c683b4..a2ba7c85c97a 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_POWER_SUPPLY) += power_supply.o obj-$(CONFIG_PDA_POWER) += pda_power.o obj-$(CONFIG_APM_POWER) += apm_power.o +obj-$(CONFIG_MAX8925_POWER) += max8925_power.o obj-$(CONFIG_WM831X_BACKUP) += wm831x_backup.o obj-$(CONFIG_WM831X_POWER) += wm831x_power.o obj-$(CONFIG_WM8350_POWER) += wm8350_power.o diff --git a/drivers/power/max8925_power.c b/drivers/power/max8925_power.c new file mode 100644 index 000000000000..a1b4410544d7 --- /dev/null +++ b/drivers/power/max8925_power.c @@ -0,0 +1,534 @@ +/* + * Battery driver for Maxim MAX8925 + * + * Copyright (c) 2009-2010 Marvell International Ltd. + * Haojian Zhuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* registers in GPM */ +#define MAX8925_OUT5VEN 0x54 +#define MAX8925_OUT3VEN 0x58 +#define MAX8925_CHG_CNTL1 0x7c + +/* bits definition */ +#define MAX8925_CHG_STAT_VSYSLOW (1 << 0) +#define MAX8925_CHG_STAT_MODE_MASK (3 << 2) +#define MAX8925_CHG_STAT_EN_MASK (1 << 4) +#define MAX8925_CHG_MBDET (1 << 1) +#define MAX8925_CHG_AC_RANGE_MASK (3 << 6) + +/* registers in ADC */ +#define MAX8925_ADC_RES_CNFG1 0x06 +#define MAX8925_ADC_AVG_CNFG1 0x07 +#define MAX8925_ADC_ACQ_CNFG1 0x08 +#define MAX8925_ADC_ACQ_CNFG2 0x09 +/* 2 bytes registers in below. MSB is 1st, LSB is 2nd. */ +#define MAX8925_ADC_AUX2 0x62 +#define MAX8925_ADC_VCHG 0x64 +#define MAX8925_ADC_VBBATT 0x66 +#define MAX8925_ADC_VMBATT 0x68 +#define MAX8925_ADC_ISNS 0x6a +#define MAX8925_ADC_THM 0x6c +#define MAX8925_ADC_TDIE 0x6e +#define MAX8925_CMD_AUX2 0xc8 +#define MAX8925_CMD_VCHG 0xd0 +#define MAX8925_CMD_VBBATT 0xd8 +#define MAX8925_CMD_VMBATT 0xe0 +#define MAX8925_CMD_ISNS 0xe8 +#define MAX8925_CMD_THM 0xf0 +#define MAX8925_CMD_TDIE 0xf8 + +enum { + MEASURE_AUX2, + MEASURE_VCHG, + MEASURE_VBBATT, + MEASURE_VMBATT, + MEASURE_ISNS, + MEASURE_THM, + MEASURE_TDIE, + MEASURE_MAX, +}; + +struct max8925_power_info { + struct max8925_chip *chip; + struct i2c_client *gpm; + struct i2c_client *adc; + + struct power_supply ac; + struct power_supply usb; + struct power_supply battery; + int irq_base; + unsigned ac_online:1; + unsigned usb_online:1; + unsigned bat_online:1; + unsigned chg_mode:2; + unsigned batt_detect:1; /* detecing MB by ID pin */ + unsigned topoff_threshold:2; + unsigned fast_charge:3; + + int (*set_charger) (int); +}; + +static int __set_charger(struct max8925_power_info *info, int enable) +{ + struct max8925_chip *chip = info->chip; + if (enable) { + /* enable charger in platform */ + if (info->set_charger) + info->set_charger(1); + /* enable charger */ + max8925_set_bits(info->gpm, MAX8925_CHG_CNTL1, 1 << 7, 0); + } else { + /* disable charge */ + max8925_set_bits(info->gpm, MAX8925_CHG_CNTL1, 1 << 7, 1 << 7); + if (info->set_charger) + info->set_charger(0); + } + dev_dbg(chip->dev, "%s\n", (enable) ? "Enable charger" + : "Disable charger"); + return 0; +} + +static irqreturn_t max8925_charger_handler(int irq, void *data) +{ + struct max8925_power_info *info = (struct max8925_power_info *)data; + struct max8925_chip *chip = info->chip; + + switch (irq - chip->irq_base) { + case MAX8925_IRQ_VCHG_DC_R: + info->ac_online = 1; + __set_charger(info, 1); + dev_dbg(chip->dev, "Adapter inserted\n"); + break; + case MAX8925_IRQ_VCHG_DC_F: + info->ac_online = 0; + __set_charger(info, 0); + dev_dbg(chip->dev, "Adapter is removal\n"); + break; + case MAX8925_IRQ_VCHG_USB_R: + info->usb_online = 1; + __set_charger(info, 1); + dev_dbg(chip->dev, "USB inserted\n"); + break; + case MAX8925_IRQ_VCHG_USB_F: + info->usb_online = 0; + __set_charger(info, 0); + dev_dbg(chip->dev, "USB is removal\n"); + break; + case MAX8925_IRQ_VCHG_THM_OK_F: + /* Battery is not ready yet */ + dev_dbg(chip->dev, "Battery temperature is out of range\n"); + case MAX8925_IRQ_VCHG_DC_OVP: + dev_dbg(chip->dev, "Error detection\n"); + __set_charger(info, 0); + break; + case MAX8925_IRQ_VCHG_THM_OK_R: + /* Battery is ready now */ + dev_dbg(chip->dev, "Battery temperature is in range\n"); + break; + case MAX8925_IRQ_VCHG_SYSLOW_R: + /* VSYS is low */ + dev_info(chip->dev, "Sys power is too low\n"); + break; + case MAX8925_IRQ_VCHG_SYSLOW_F: + dev_dbg(chip->dev, "Sys power is above low threshold\n"); + break; + case MAX8925_IRQ_VCHG_DONE: + __set_charger(info, 0); + dev_dbg(chip->dev, "Charging is done\n"); + break; + case MAX8925_IRQ_VCHG_TOPOFF: + dev_dbg(chip->dev, "Charging in top-off mode\n"); + break; + case MAX8925_IRQ_VCHG_TMR_FAULT: + __set_charger(info, 0); + dev_dbg(chip->dev, "Safe timer is expired\n"); + break; + case MAX8925_IRQ_VCHG_RST: + __set_charger(info, 0); + dev_dbg(chip->dev, "Charger is reset\n"); + break; + } + return IRQ_HANDLED; +} + +static int start_measure(struct max8925_power_info *info, int type) +{ + unsigned char buf[2] = {0, 0}; + int meas_reg = 0, ret; + + switch (type) { + case MEASURE_VCHG: + meas_reg = MAX8925_ADC_VCHG; + break; + case MEASURE_VBBATT: + meas_reg = MAX8925_ADC_VBBATT; + break; + case MEASURE_VMBATT: + meas_reg = MAX8925_ADC_VMBATT; + break; + case MEASURE_ISNS: + meas_reg = MAX8925_ADC_ISNS; + break; + default: + return -EINVAL; + } + + max8925_bulk_read(info->adc, meas_reg, 2, buf); + ret = (buf[0] << 4) | (buf[1] >> 4); + + return ret; +} + +static int max8925_ac_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct max8925_power_info *info = dev_get_drvdata(psy->dev->parent); + int ret = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + val->intval = info->ac_online; + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + if (info->ac_online) { + ret = start_measure(info, MEASURE_VCHG); + if (ret >= 0) { + val->intval = ret << 1; /* unit is mV */ + goto out; + } + } + ret = -ENODATA; + break; + default: + ret = -ENODEV; + break; + } +out: + return ret; +} + +static enum power_supply_property max8925_ac_props[] = { + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_VOLTAGE_NOW, +}; + +static int max8925_usb_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct max8925_power_info *info = dev_get_drvdata(psy->dev->parent); + int ret = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + val->intval = info->usb_online; + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + if (info->usb_online) { + ret = start_measure(info, MEASURE_VCHG); + if (ret >= 0) { + val->intval = ret << 1; /* unit is mV */ + goto out; + } + } + ret = -ENODATA; + break; + default: + ret = -ENODEV; + break; + } +out: + return ret; +} + +static enum power_supply_property max8925_usb_props[] = { + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_VOLTAGE_NOW, +}; + +static int max8925_bat_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct max8925_power_info *info = dev_get_drvdata(psy->dev->parent); + long long int tmp = 0; + int ret = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + val->intval = info->bat_online; + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + if (info->bat_online) { + ret = start_measure(info, MEASURE_VMBATT); + if (ret >= 0) { + val->intval = ret << 1; /* unit is mV */ + ret = 0; + break; + } + } + ret = -ENODATA; + break; + case POWER_SUPPLY_PROP_CURRENT_NOW: + if (info->bat_online) { + ret = start_measure(info, MEASURE_ISNS); + if (ret >= 0) { + tmp = (long long int)ret * 6250 / 4096 - 3125; + ret = (int)tmp; + val->intval = 0; + if (ret > 0) + val->intval = ret; /* unit is mA */ + ret = 0; + break; + } + } + ret = -ENODATA; + break; + case POWER_SUPPLY_PROP_CHARGE_TYPE: + if (!info->bat_online) { + ret = -ENODATA; + break; + } + ret = max8925_reg_read(info->gpm, MAX8925_CHG_STATUS); + ret = (ret & MAX8925_CHG_STAT_MODE_MASK) >> 2; + switch (ret) { + case 1: + val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST; + break; + case 0: + case 2: + val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; + break; + case 3: + val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; + break; + } + ret = 0; + break; + case POWER_SUPPLY_PROP_STATUS: + if (!info->bat_online) { + ret = -ENODATA; + break; + } + ret = max8925_reg_read(info->gpm, MAX8925_CHG_STATUS); + if (info->usb_online || info->ac_online) { + val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; + if (ret & MAX8925_CHG_STAT_EN_MASK) + val->intval = POWER_SUPPLY_STATUS_CHARGING; + } else + val->intval = POWER_SUPPLY_STATUS_DISCHARGING; + ret = 0; + break; + default: + ret = -ENODEV; + break; + } + return ret; +} + +static enum power_supply_property max8925_battery_props[] = { + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_CHARGE_TYPE, + POWER_SUPPLY_PROP_STATUS, +}; + +#define REQUEST_IRQ(_irq, _name) \ +do { \ + ret = request_threaded_irq(chip->irq_base + _irq, NULL, \ + max8925_charger_handler, \ + IRQF_ONESHOT, _name, info); \ + if (ret) \ + dev_err(chip->dev, "Failed to request IRQ #%d: %d\n", \ + _irq, ret); \ +} while (0) + +static __devinit int max8925_init_charger(struct max8925_chip *chip, + struct max8925_power_info *info) +{ + int ret; + + REQUEST_IRQ(MAX8925_IRQ_VCHG_DC_OVP, "ac-ovp"); + REQUEST_IRQ(MAX8925_IRQ_VCHG_DC_F, "ac-remove"); + REQUEST_IRQ(MAX8925_IRQ_VCHG_DC_R, "ac-insert"); + REQUEST_IRQ(MAX8925_IRQ_VCHG_USB_OVP, "usb-ovp"); + REQUEST_IRQ(MAX8925_IRQ_VCHG_USB_F, "usb-remove"); + REQUEST_IRQ(MAX8925_IRQ_VCHG_USB_R, "usb-insert"); + REQUEST_IRQ(MAX8925_IRQ_VCHG_THM_OK_R, "batt-temp-in-range"); + REQUEST_IRQ(MAX8925_IRQ_VCHG_THM_OK_F, "batt-temp-out-range"); + REQUEST_IRQ(MAX8925_IRQ_VCHG_SYSLOW_F, "vsys-high"); + REQUEST_IRQ(MAX8925_IRQ_VCHG_SYSLOW_R, "vsys-low"); + REQUEST_IRQ(MAX8925_IRQ_VCHG_RST, "charger-reset"); + REQUEST_IRQ(MAX8925_IRQ_VCHG_DONE, "charger-done"); + REQUEST_IRQ(MAX8925_IRQ_VCHG_TOPOFF, "charger-topoff"); + REQUEST_IRQ(MAX8925_IRQ_VCHG_TMR_FAULT, "charger-timer-expire"); + + info->ac_online = 0; + info->usb_online = 0; + info->bat_online = 0; + ret = max8925_reg_read(info->gpm, MAX8925_CHG_STATUS); + if (ret >= 0) { + /* + * If battery detection is enabled, ID pin of battery is + * connected to MBDET pin of MAX8925. It could be used to + * detect battery presence. + * Otherwise, we have to assume that battery is always on. + */ + if (info->batt_detect) + info->bat_online = (ret & MAX8925_CHG_MBDET) ? 0 : 1; + else + info->bat_online = 1; + if (ret & MAX8925_CHG_AC_RANGE_MASK) + info->ac_online = 1; + else + info->ac_online = 0; + } + /* disable charge */ + max8925_set_bits(info->gpm, MAX8925_CHG_CNTL1, 1 << 7, 1 << 7); + /* set charging current in charge topoff mode */ + max8925_set_bits(info->gpm, MAX8925_CHG_CNTL1, 3 << 5, + info->topoff_threshold << 5); + /* set charing current in fast charge mode */ + max8925_set_bits(info->gpm, MAX8925_CHG_CNTL1, 7, info->fast_charge); + + return 0; +} + +static __devexit int max8925_deinit_charger(struct max8925_power_info *info) +{ + struct max8925_chip *chip = info->chip; + int irq; + + irq = chip->irq_base + MAX8925_IRQ_VCHG_DC_OVP; + for (; irq <= chip->irq_base + MAX8925_IRQ_VCHG_TMR_FAULT; irq++) + free_irq(irq, info); + + return 0; +} + +static __devinit int max8925_power_probe(struct platform_device *pdev) +{ + struct max8925_chip *chip = dev_get_drvdata(pdev->dev.parent); + struct max8925_platform_data *max8925_pdata; + struct max8925_power_pdata *pdata = NULL; + struct max8925_power_info *info; + int ret; + + if (pdev->dev.parent->platform_data) { + max8925_pdata = pdev->dev.parent->platform_data; + pdata = max8925_pdata->power; + } + + if (!pdata) { + dev_err(&pdev->dev, "platform data isn't assigned to " + "power supply\n"); + return -EINVAL; + } + + info = kzalloc(sizeof(struct max8925_power_info), GFP_KERNEL); + if (!info) + return -ENOMEM; + info->chip = chip; + info->gpm = chip->i2c; + info->adc = chip->adc; + + info->ac.name = "max8925-ac"; + info->ac.type = POWER_SUPPLY_TYPE_MAINS; + info->ac.properties = max8925_ac_props; + info->ac.num_properties = ARRAY_SIZE(max8925_ac_props); + info->ac.get_property = max8925_ac_get_prop; + ret = power_supply_register(&pdev->dev, &info->ac); + if (ret) + goto out; + info->ac.dev->parent = &pdev->dev; + + info->usb.name = "max8925-usb"; + info->usb.type = POWER_SUPPLY_TYPE_USB; + info->usb.properties = max8925_usb_props; + info->usb.num_properties = ARRAY_SIZE(max8925_usb_props); + info->usb.get_property = max8925_usb_get_prop; + ret = power_supply_register(&pdev->dev, &info->usb); + if (ret) + goto out_usb; + info->usb.dev->parent = &pdev->dev; + + info->battery.name = "max8925-battery"; + info->battery.type = POWER_SUPPLY_TYPE_BATTERY; + info->battery.properties = max8925_battery_props; + info->battery.num_properties = ARRAY_SIZE(max8925_battery_props); + info->battery.get_property = max8925_bat_get_prop; + ret = power_supply_register(&pdev->dev, &info->battery); + if (ret) + goto out_battery; + info->battery.dev->parent = &pdev->dev; + + info->batt_detect = pdata->batt_detect; + info->topoff_threshold = pdata->topoff_threshold; + info->fast_charge = pdata->fast_charge; + info->set_charger = pdata->set_charger; + dev_set_drvdata(&pdev->dev, info); + platform_set_drvdata(pdev, info); + + max8925_init_charger(chip, info); + return 0; +out_battery: + power_supply_unregister(&info->battery); +out_usb: + power_supply_unregister(&info->ac); +out: + kfree(info); + return ret; +} + +static __devexit int max8925_power_remove(struct platform_device *pdev) +{ + struct max8925_power_info *info = platform_get_drvdata(pdev); + + if (info) { + power_supply_unregister(&info->ac); + power_supply_unregister(&info->usb); + power_supply_unregister(&info->battery); + max8925_deinit_charger(info); + kfree(info); + } + return 0; +} + +static struct platform_driver max8925_power_driver = { + .probe = max8925_power_probe, + .remove = __devexit_p(max8925_power_remove), + .driver = { + .name = "max8925-power", + }, +}; + +static int __init max8925_power_init(void) +{ + return platform_driver_register(&max8925_power_driver); +} +module_init(max8925_power_init); + +static void __exit max8925_power_exit(void) +{ + platform_driver_unregister(&max8925_power_driver); +} +module_exit(max8925_power_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Power supply driver for MAX8925"); +MODULE_ALIAS("platform:max8925-power"); -- cgit v1.2.3 From e8343ddaccb322b1a2a989ac362cabd1e94597ad Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 3 Feb 2010 15:38:12 -0500 Subject: mfd: Use i2c_dummy in 88pm860x Use i2c_dummy in 88pm860x driver to avoid using static in probe function. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/mfd/88pm860x-i2c.c | 72 +++++++++++++--------------------------------- 1 file changed, 20 insertions(+), 52 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/88pm860x-i2c.c b/drivers/mfd/88pm860x-i2c.c index 6d7dba2bce8a..c37e12bf3004 100644 --- a/drivers/mfd/88pm860x-i2c.c +++ b/drivers/mfd/88pm860x-i2c.c @@ -157,18 +157,24 @@ static int __devinit pm860x_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct pm860x_platform_data *pdata = client->dev.platform_data; - static struct pm860x_chip *chip; - struct i2c_board_info i2c_info = { - .type = "88PM860x", - .platform_data = client->dev.platform_data, - }; - int addr_c, found_companion = 0; - - if (pdata == NULL) { + struct pm860x_chip *chip; + + if (!pdata) { pr_info("No platform data in %s!\n", __func__); return -EINVAL; } + chip = kzalloc(sizeof(struct pm860x_chip), GFP_KERNEL); + if (chip == NULL) + return -ENOMEM; + + chip->id = verify_addr(client); + chip->client = client; + i2c_set_clientdata(client, chip); + chip->dev = &client->dev; + mutex_init(&chip->io_lock); + dev_set_drvdata(chip->dev, chip); + /* * Both client and companion client shares same platform driver. * Driver distinguishes them by pdata->companion_addr. @@ -176,46 +182,14 @@ static int __devinit pm860x_probe(struct i2c_client *client, * At the same time, the companion_addr shouldn't equal to client * address. */ - addr_c = pdata->companion_addr; - if (addr_c && (addr_c != client->addr)) { - i2c_info.addr = addr_c; - found_companion = 1; - } - - if (found_companion || (addr_c == 0)) { - chip = kzalloc(sizeof(struct pm860x_chip), GFP_KERNEL); - if (chip == NULL) - return -ENOMEM; - - chip->id = verify_addr(client); - chip->companion_addr = addr_c; - chip->client = client; - i2c_set_clientdata(client, chip); - chip->dev = &client->dev; - mutex_init(&chip->io_lock); - dev_set_drvdata(chip->dev, chip); - - if (found_companion) { - /* - * If this driver is built in, probe function is - * recursive. - * If this driver is built as module, the next probe - * function is called after the first one finished. - */ - chip->companion = i2c_new_device(client->adapter, - &i2c_info); - } - } - - /* - * If companion chip existes, it's called by companion probe. - * If there's no companion chip, it's called by client probe. - */ - if ((addr_c == 0) || (addr_c == client->addr)) { - chip->companion = client; + if (pdata->companion_addr && (pdata->companion_addr != client->addr)) { + chip->companion_addr = pdata->companion_addr; + chip->companion = i2c_new_dummy(chip->client->adapter, + chip->companion_addr); i2c_set_clientdata(chip->companion, chip); - pm860x_device_init(chip, pdata); } + + pm860x_device_init(chip, pdata); return 0; } @@ -223,12 +197,6 @@ static int __devexit pm860x_remove(struct i2c_client *client) { struct pm860x_chip *chip = i2c_get_clientdata(client); - /* - * If companion existes, companion client is removed first. - * Because companion client is registered last and removed first. - */ - if (chip->companion_addr == client->addr) - return 0; pm860x_device_exit(chip); i2c_unregister_device(chip->companion); i2c_set_clientdata(chip->companion, NULL); -- cgit v1.2.3 From 7731074ab21745cde00578148ce760df107eaf27 Mon Sep 17 00:00:00 2001 From: Joonyoung Shim Date: Sun, 7 Feb 2010 10:16:14 +0900 Subject: mfd: Fix WM8994 error handling This patch fixes wrong goto statement for error handling on probe. Signed-off-by: Myungjoo Ham Signed-off-by: Joonyoung Shim Acked-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/mfd/wm8994-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/wm8994-core.c b/drivers/mfd/wm8994-core.c index 299c1af1334e..844e1c1b7d90 100644 --- a/drivers/mfd/wm8994-core.c +++ b/drivers/mfd/wm8994-core.c @@ -305,14 +305,14 @@ static int wm8994_device_init(struct wm8994 *wm8994, unsigned long id, int irq) wm8994->supplies); if (ret != 0) { dev_err(wm8994->dev, "Failed to get supplies: %d\n", ret); - goto err_get; + goto err_supplies; } ret = regulator_bulk_enable(ARRAY_SIZE(wm8994_main_supplies), wm8994->supplies); if (ret != 0) { dev_err(wm8994->dev, "Failed to enable supplies: %d\n", ret); - goto err_supplies; + goto err_get; } ret = wm8994_reg_read(wm8994, WM8994_SOFTWARE_RESET); -- cgit v1.2.3 From 2afa62ea76027b00e472ddb672191e6e15425b43 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 8 Feb 2010 05:02:00 -0500 Subject: mfd: Use genirq in 88pm860x Use genirq to simplify IRQ handling in 88pm860x. Remove the interface of mask/free IRQs on 88pm860x. All these work is taken by genirq. Update the touchscreen driver of 88pm860x since IRQ handling is changed. Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- drivers/input/touchscreen/88pm860x-ts.c | 15 +- drivers/mfd/88pm860x-core.c | 408 +++++++++++++++++++++++--------- include/linux/mfd/88pm860x.h | 30 +-- 3 files changed, 311 insertions(+), 142 deletions(-) (limited to 'drivers') diff --git a/drivers/input/touchscreen/88pm860x-ts.c b/drivers/input/touchscreen/88pm860x-ts.c index 56254d2a1f6e..286bb490a9f2 100644 --- a/drivers/input/touchscreen/88pm860x-ts.c +++ b/drivers/input/touchscreen/88pm860x-ts.c @@ -54,7 +54,6 @@ static irqreturn_t pm860x_touch_handler(int irq, void *data) int z1, z2, rt = 0; int ret; - pm860x_mask_irq(chip, irq); ret = pm860x_bulk_read(touch->i2c, MEAS_TSIX_1, MEAS_LEN, buf); if (ret < 0) goto out; @@ -83,7 +82,6 @@ static irqreturn_t pm860x_touch_handler(int irq, void *data) dev_dbg(chip->dev, "pen release\n"); } input_sync(touch->idev); - pm860x_unmask_irq(chip, irq); out: return IRQ_HANDLED; @@ -92,7 +90,6 @@ out: static int pm860x_touch_open(struct input_dev *dev) { struct pm860x_touch *touch = input_get_drvdata(dev); - struct pm860x_chip *chip = touch->chip; int data, ret; data = MEAS_PD_EN | MEAS_TSIX_EN | MEAS_TSIY_EN @@ -100,7 +97,6 @@ static int pm860x_touch_open(struct input_dev *dev) ret = pm860x_set_bits(touch->i2c, MEAS_EN3, data, data); if (ret < 0) goto out; - pm860x_unmask_irq(chip, touch->irq); return 0; out: return ret; @@ -109,13 +105,11 @@ out: static void pm860x_touch_close(struct input_dev *dev) { struct pm860x_touch *touch = input_get_drvdata(dev); - struct pm860x_chip *chip = touch->chip; int data; data = MEAS_PD_EN | MEAS_TSIX_EN | MEAS_TSIY_EN | MEAS_TSIZ1_EN | MEAS_TSIZ2_EN; pm860x_set_bits(touch->i2c, MEAS_EN3, data, 0); - pm860x_mask_irq(chip, touch->irq); } static int __devinit pm860x_touch_probe(struct platform_device *pdev) @@ -164,11 +158,12 @@ static int __devinit pm860x_touch_probe(struct platform_device *pdev) touch->idev->close = pm860x_touch_close; touch->chip = chip; touch->i2c = (chip->id == CHIP_PM8607) ? chip->client : chip->companion; - touch->irq = irq; + touch->irq = irq + chip->irq_base; touch->res_x = pdata->res_x; input_set_drvdata(touch->idev, touch); - ret = pm860x_request_irq(chip, irq, pm860x_touch_handler, touch); + ret = request_threaded_irq(touch->irq, NULL, pm860x_touch_handler, + IRQF_ONESHOT, "touch", touch); if (ret < 0) goto out_irq; @@ -194,7 +189,7 @@ static int __devinit pm860x_touch_probe(struct platform_device *pdev) platform_set_drvdata(pdev, touch); return 0; out_rg: - pm860x_free_irq(chip, irq); + free_irq(touch->irq, touch); out_irq: input_free_device(touch->idev); out: @@ -207,7 +202,7 @@ static int __devexit pm860x_touch_remove(struct platform_device *pdev) struct pm860x_touch *touch = platform_get_drvdata(pdev); input_unregister_device(touch->idev); - pm860x_free_irq(touch->chip, touch->irq); + free_irq(touch->irq, touch); platform_set_drvdata(pdev, NULL); kfree(touch); return 0; diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c index 16f0dca707a7..6a14d2b1ccf0 100644 --- a/drivers/mfd/88pm860x-core.c +++ b/drivers/mfd/88pm860x-core.c @@ -12,11 +12,14 @@ #include #include #include +#include #include #include #include #include +#define INT_STATUS_NUM 3 + char pm860x_backlight_name[][MFD_NAME_SIZE] = { "backlight-0", "backlight-1", @@ -119,6 +122,42 @@ static struct mfd_cell touch_devs[] = { .flags = IORESOURCE_IO, \ } +static struct resource power_supply_resources[] = { + { + .name = "88pm860x-power", + .start = PM8607_IRQ_CHG, + .end = PM8607_IRQ_CHG, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mfd_cell power_devs[] = { + { + .name = "88pm860x-power", + .num_resources = 1, + .resources = &power_supply_resources[0], + .id = -1, + }, +}; + +static struct resource onkey_resources[] = { + { + .name = "88pm860x-onkey", + .start = PM8607_IRQ_ONKEY, + .end = PM8607_IRQ_ONKEY, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mfd_cell onkey_devs[] = { + { + .name = "88pm860x-onkey", + .num_resources = 1, + .resources = &onkey_resources[0], + .id = -1, + }, +}; + static struct resource regulator_resources[] = { PM8607_REG_RESOURCE(BUCK1, BUCK1), PM8607_REG_RESOURCE(BUCK2, BUCK2), @@ -163,129 +202,224 @@ static struct mfd_cell regulator_devs[] = { PM8607_REG_DEVS(ldo14, LDO14), }; -#define CHECK_IRQ(irq) \ -do { \ - if ((irq < 0) || (irq >= PM860X_NUM_IRQ)) \ - return -EINVAL; \ -} while (0) - -/* IRQs only occur on 88PM8607 */ -int pm860x_mask_irq(struct pm860x_chip *chip, int irq) -{ - struct i2c_client *i2c = (chip->id == CHIP_PM8607) ? chip->client \ - : chip->companion; - int offset, data, ret; - - CHECK_IRQ(irq); - - offset = (irq >> 3) + PM8607_INT_MASK_1; - data = 1 << (irq % 8); - ret = pm860x_set_bits(i2c, offset, data, 0); +struct pm860x_irq_data { + int reg; + int mask_reg; + int enable; /* enable or not */ + int offs; /* bit offset in mask register */ +}; - return ret; -} -EXPORT_SYMBOL(pm860x_mask_irq); +static struct pm860x_irq_data pm860x_irqs[] = { + [PM8607_IRQ_ONKEY] = { + .reg = PM8607_INT_STATUS1, + .mask_reg = PM8607_INT_MASK_1, + .offs = 1 << 0, + }, + [PM8607_IRQ_EXTON] = { + .reg = PM8607_INT_STATUS1, + .mask_reg = PM8607_INT_MASK_1, + .offs = 1 << 1, + }, + [PM8607_IRQ_CHG] = { + .reg = PM8607_INT_STATUS1, + .mask_reg = PM8607_INT_MASK_1, + .offs = 1 << 2, + }, + [PM8607_IRQ_BAT] = { + .reg = PM8607_INT_STATUS1, + .mask_reg = PM8607_INT_MASK_1, + .offs = 1 << 3, + }, + [PM8607_IRQ_RTC] = { + .reg = PM8607_INT_STATUS1, + .mask_reg = PM8607_INT_MASK_1, + .offs = 1 << 4, + }, + [PM8607_IRQ_CC] = { + .reg = PM8607_INT_STATUS1, + .mask_reg = PM8607_INT_MASK_1, + .offs = 1 << 5, + }, + [PM8607_IRQ_VBAT] = { + .reg = PM8607_INT_STATUS2, + .mask_reg = PM8607_INT_MASK_2, + .offs = 1 << 0, + }, + [PM8607_IRQ_VCHG] = { + .reg = PM8607_INT_STATUS2, + .mask_reg = PM8607_INT_MASK_2, + .offs = 1 << 1, + }, + [PM8607_IRQ_VSYS] = { + .reg = PM8607_INT_STATUS2, + .mask_reg = PM8607_INT_MASK_2, + .offs = 1 << 2, + }, + [PM8607_IRQ_TINT] = { + .reg = PM8607_INT_STATUS2, + .mask_reg = PM8607_INT_MASK_2, + .offs = 1 << 3, + }, + [PM8607_IRQ_GPADC0] = { + .reg = PM8607_INT_STATUS2, + .mask_reg = PM8607_INT_MASK_2, + .offs = 1 << 4, + }, + [PM8607_IRQ_GPADC1] = { + .reg = PM8607_INT_STATUS2, + .mask_reg = PM8607_INT_MASK_2, + .offs = 1 << 5, + }, + [PM8607_IRQ_GPADC2] = { + .reg = PM8607_INT_STATUS2, + .mask_reg = PM8607_INT_MASK_2, + .offs = 1 << 6, + }, + [PM8607_IRQ_GPADC3] = { + .reg = PM8607_INT_STATUS2, + .mask_reg = PM8607_INT_MASK_2, + .offs = 1 << 7, + }, + [PM8607_IRQ_AUDIO_SHORT] = { + .reg = PM8607_INT_STATUS3, + .mask_reg = PM8607_INT_MASK_3, + .offs = 1 << 0, + }, + [PM8607_IRQ_PEN] = { + .reg = PM8607_INT_STATUS3, + .mask_reg = PM8607_INT_MASK_3, + .offs = 1 << 1, + }, + [PM8607_IRQ_HEADSET] = { + .reg = PM8607_INT_STATUS3, + .mask_reg = PM8607_INT_MASK_3, + .offs = 1 << 2, + }, + [PM8607_IRQ_HOOK] = { + .reg = PM8607_INT_STATUS3, + .mask_reg = PM8607_INT_MASK_3, + .offs = 1 << 3, + }, + [PM8607_IRQ_MICIN] = { + .reg = PM8607_INT_STATUS3, + .mask_reg = PM8607_INT_MASK_3, + .offs = 1 << 4, + }, + [PM8607_IRQ_CHG_FAIL] = { + .reg = PM8607_INT_STATUS3, + .mask_reg = PM8607_INT_MASK_3, + .offs = 1 << 5, + }, + [PM8607_IRQ_CHG_DONE] = { + .reg = PM8607_INT_STATUS3, + .mask_reg = PM8607_INT_MASK_3, + .offs = 1 << 6, + }, + [PM8607_IRQ_CHG_FAULT] = { + .reg = PM8607_INT_STATUS3, + .mask_reg = PM8607_INT_MASK_3, + .offs = 1 << 7, + }, +}; -int pm860x_unmask_irq(struct pm860x_chip *chip, int irq) +static inline struct pm860x_irq_data *irq_to_pm860x(struct pm860x_chip *chip, + int irq) { - struct i2c_client *i2c = (chip->id == CHIP_PM8607) ? chip->client \ - : chip->companion; - int offset, data, ret; - - CHECK_IRQ(irq); - - offset = (irq >> 3) + PM8607_INT_MASK_1; - data = 1 << (irq % 8); - ret = pm860x_set_bits(i2c, offset, data, data); - - return ret; + return &pm860x_irqs[irq - chip->irq_base]; } -EXPORT_SYMBOL(pm860x_unmask_irq); -#define INT_STATUS_NUM (3) - -static irqreturn_t pm8607_irq_thread(int irq, void *data) +static irqreturn_t pm860x_irq(int irq, void *data) { - DECLARE_BITMAP(irq_status, PM860X_NUM_IRQ); struct pm860x_chip *chip = data; - struct i2c_client *i2c = (chip->id == CHIP_PM8607) ? chip->client \ - : chip->companion; - unsigned char status_buf[INT_STATUS_NUM << 1]; - unsigned long value; - int i, ret; - - irq_status[0] = 0; - - /* read out status register */ - ret = pm860x_bulk_read(i2c, PM8607_INT_STATUS1, - INT_STATUS_NUM << 1, status_buf); - if (ret < 0) - goto out; - if (chip->irq_mode) { - /* 0, clear by read. 1, clear by write */ - ret = pm860x_bulk_write(i2c, PM8607_INT_STATUS1, - INT_STATUS_NUM, status_buf); - if (ret < 0) - goto out; - } - - /* clear masked interrupt status */ - for (i = 0, value = 0; i < INT_STATUS_NUM; i++) { - status_buf[i] &= status_buf[i + INT_STATUS_NUM]; - irq_status[0] |= status_buf[i] << (i * 8); - } - - while (!bitmap_empty(irq_status, PM860X_NUM_IRQ)) { - irq = find_first_bit(irq_status, PM860X_NUM_IRQ); - clear_bit(irq, irq_status); - dev_dbg(chip->dev, "Servicing IRQ #%d\n", irq); - - mutex_lock(&chip->irq_lock); - if (chip->irq[irq].handler) - chip->irq[irq].handler(irq, chip->irq[irq].data); - else { - pm860x_mask_irq(chip, irq); - dev_err(chip->dev, "Nobody cares IRQ %d. " - "Now mask it.\n", irq); - for (i = 0; i < (INT_STATUS_NUM << 1); i++) { - dev_err(chip->dev, "status[%d]:%x\n", i, - status_buf[i]); - } + struct pm860x_irq_data *irq_data; + struct i2c_client *i2c; + int read_reg = -1, value = 0; + int i; + + i2c = (chip->id == CHIP_PM8607) ? chip->client : chip->companion; + for (i = 0; i < ARRAY_SIZE(pm860x_irqs); i++) { + irq_data = &pm860x_irqs[i]; + if (read_reg != irq_data->reg) { + read_reg = irq_data->reg; + value = pm860x_reg_read(i2c, irq_data->reg); } - mutex_unlock(&chip->irq_lock); + if (value & irq_data->enable) + handle_nested_irq(chip->irq_base + i); } -out: return IRQ_HANDLED; } -int pm860x_request_irq(struct pm860x_chip *chip, int irq, - irq_handler_t handler, void *data) +static void pm860x_irq_lock(unsigned int irq) { - CHECK_IRQ(irq); - if (!handler) - return -EINVAL; + struct pm860x_chip *chip = get_irq_chip_data(irq); mutex_lock(&chip->irq_lock); - chip->irq[irq].handler = handler; - chip->irq[irq].data = data; - mutex_unlock(&chip->irq_lock); - - return 0; } -EXPORT_SYMBOL(pm860x_request_irq); -int pm860x_free_irq(struct pm860x_chip *chip, int irq) +static void pm860x_irq_sync_unlock(unsigned int irq) { - CHECK_IRQ(irq); + struct pm860x_chip *chip = get_irq_chip_data(irq); + struct pm860x_irq_data *irq_data; + struct i2c_client *i2c; + static unsigned char cached[3] = {0x0, 0x0, 0x0}; + unsigned char mask[3]; + int i; + + i2c = (chip->id == CHIP_PM8607) ? chip->client : chip->companion; + /* Load cached value. In initial, all IRQs are masked */ + for (i = 0; i < 3; i++) + mask[i] = cached[i]; + for (i = 0; i < ARRAY_SIZE(pm860x_irqs); i++) { + irq_data = &pm860x_irqs[i]; + switch (irq_data->mask_reg) { + case PM8607_INT_MASK_1: + mask[0] &= ~irq_data->offs; + mask[0] |= irq_data->enable; + break; + case PM8607_INT_MASK_2: + mask[1] &= ~irq_data->offs; + mask[1] |= irq_data->enable; + break; + case PM8607_INT_MASK_3: + mask[2] &= ~irq_data->offs; + mask[2] |= irq_data->enable; + break; + default: + dev_err(chip->dev, "wrong IRQ\n"); + break; + } + } + /* update mask into registers */ + for (i = 0; i < 3; i++) { + if (mask[i] != cached[i]) { + cached[i] = mask[i]; + pm860x_reg_write(i2c, PM8607_INT_MASK_1 + i, mask[i]); + } + } - mutex_lock(&chip->irq_lock); - chip->irq[irq].handler = NULL; - chip->irq[irq].data = NULL; mutex_unlock(&chip->irq_lock); +} - return 0; +static void pm860x_irq_enable(unsigned int irq) +{ + struct pm860x_chip *chip = get_irq_chip_data(irq); + pm860x_irqs[irq - chip->irq_base].enable + = pm860x_irqs[irq - chip->irq_base].offs; } -EXPORT_SYMBOL(pm860x_free_irq); + +static void pm860x_irq_disable(unsigned int irq) +{ + struct pm860x_chip *chip = get_irq_chip_data(irq); + pm860x_irqs[irq - chip->irq_base].enable = 0; +} + +static struct irq_chip pm860x_irq_chip = { + .name = "88pm860x", + .bus_lock = pm860x_irq_lock, + .bus_sync_unlock = pm860x_irq_sync_unlock, + .enable = pm860x_irq_enable, + .disable = pm860x_irq_disable, +}; static int __devinit device_gpadc_init(struct pm860x_chip *chip, struct pm860x_platform_data *pdata) @@ -348,9 +482,15 @@ static int __devinit device_irq_init(struct pm860x_chip *chip, struct i2c_client *i2c = (chip->id == CHIP_PM8607) ? chip->client \ : chip->companion; unsigned char status_buf[INT_STATUS_NUM]; - int data, mask, ret = -EINVAL; + unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT; + struct irq_desc *desc; + int i, data, mask, ret = -EINVAL; + int __irq; - mutex_init(&chip->irq_lock); + if (!pdata || !pdata->irq_base) { + dev_warn(chip->dev, "No interrupt support on IRQ base\n"); + return -EINVAL; + } mask = PM8607_B0_MISC1_INV_INT | PM8607_B0_MISC1_INT_CLEAR | PM8607_B0_MISC1_INT_MASK; @@ -389,25 +529,45 @@ static int __devinit device_irq_init(struct pm860x_chip *chip, if (ret < 0) goto out; - memset(chip->irq, 0, sizeof(struct pm860x_irq) * PM860X_NUM_IRQ); - - ret = request_threaded_irq(i2c->irq, NULL, pm8607_irq_thread, - IRQF_ONESHOT | IRQF_TRIGGER_LOW, - "88PM8607", chip); - if (ret < 0) { - dev_err(chip->dev, "Failed to request IRQ #%d.\n", i2c->irq); + mutex_init(&chip->irq_lock); + chip->irq_base = pdata->irq_base; + chip->core_irq = i2c->irq; + if (!chip->core_irq) goto out; + + desc = irq_to_desc(chip->core_irq); + + /* register IRQ by genirq */ + for (i = 0; i < ARRAY_SIZE(pm860x_irqs); i++) { + __irq = i + chip->irq_base; + set_irq_chip_data(__irq, chip); + set_irq_chip_and_handler(__irq, &pm860x_irq_chip, + handle_edge_irq); + set_irq_nested_thread(__irq, 1); +#ifdef CONFIG_ARM + set_irq_flags(__irq, IRQF_VALID); +#else + set_irq_noprobe(__irq); +#endif } - chip->chip_irq = i2c->irq; + + ret = request_threaded_irq(chip->core_irq, NULL, pm860x_irq, flags, + "88pm860x", chip); + if (ret) { + dev_err(chip->dev, "Failed to request IRQ: %d\n", ret); + chip->core_irq = 0; + } + return 0; out: + chip->core_irq = 0; return ret; } static void __devexit device_irq_exit(struct pm860x_chip *chip) { - if (chip->chip_irq >= 0) - free_irq(chip->chip_irq, chip); + if (chip->core_irq) + free_irq(chip->core_irq, chip); } static void __devinit device_8606_init(struct pm860x_chip *chip, @@ -513,6 +673,26 @@ static void __devinit device_8607_init(struct pm860x_chip *chip, goto out_dev; } } + + if (pdata && pdata->power) { + ret = mfd_add_devices(chip->dev, 0, &power_devs[0], + ARRAY_SIZE(power_devs), + &power_supply_resources[0], 0); + if (ret < 0) { + dev_err(chip->dev, "Failed to add power supply " + "subdev\n"); + goto out_dev; + } + } + + ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0], + ARRAY_SIZE(onkey_devs), + &onkey_resources[0], 0); + if (ret < 0) { + dev_err(chip->dev, "Failed to add onkey subdev\n"); + goto out_dev; + } + return; out_dev: mfd_remove_devices(chip->dev); @@ -524,7 +704,7 @@ out: int pm860x_device_init(struct pm860x_chip *chip, struct pm860x_platform_data *pdata) { - chip->chip_irq = -EINVAL; + chip->core_irq = 0; switch (chip->id) { case CHIP_PM8606: diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h index 80bc82a7ac96..73f92c5feea2 100644 --- a/include/linux/mfd/88pm860x.h +++ b/include/linux/mfd/88pm860x.h @@ -262,12 +262,13 @@ enum { /* Interrupt Number in 88PM8607 */ enum { - PM8607_IRQ_ONKEY = 0, + PM8607_IRQ_ONKEY, PM8607_IRQ_EXTON, PM8607_IRQ_CHG, PM8607_IRQ_BAT, PM8607_IRQ_RTC, - PM8607_IRQ_VBAT = 8, + PM8607_IRQ_CC, + PM8607_IRQ_VBAT, PM8607_IRQ_VCHG, PM8607_IRQ_VSYS, PM8607_IRQ_TINT, @@ -275,7 +276,7 @@ enum { PM8607_IRQ_GPADC1, PM8607_IRQ_GPADC2, PM8607_IRQ_GPADC3, - PM8607_IRQ_AUDIO_SHORT = 16, + PM8607_IRQ_AUDIO_SHORT, PM8607_IRQ_PEN, PM8607_IRQ_HEADSET, PM8607_IRQ_HOOK, @@ -291,26 +292,19 @@ enum { PM8607_CHIP_B0 = 0x48, }; -#define PM860X_NUM_IRQ 24 - -struct pm860x_irq { - irq_handler_t handler; - void *data; -}; - struct pm860x_chip { struct device *dev; struct mutex io_lock; struct mutex irq_lock; struct i2c_client *client; struct i2c_client *companion; /* companion chip client */ - struct pm860x_irq irq[PM860X_NUM_IRQ]; int buck3_double; /* DVC ramp slope double */ unsigned short companion_addr; int id; int irq_mode; - int chip_irq; + int irq_base; + int core_irq; unsigned char chip_version; }; @@ -347,14 +341,20 @@ struct pm860x_touch_pdata { unsigned long flags; }; +struct pm860x_power_pdata { + unsigned fast_charge; /* charge current */ +}; + struct pm860x_platform_data { struct pm860x_backlight_pdata *backlight; struct pm860x_led_pdata *led; struct pm860x_touch_pdata *touch; + struct pm860x_power_pdata *power; unsigned short companion_addr; /* I2C address of companion chip */ int i2c_port; /* Controlled by GI2C or PI2C */ int irq_mode; /* Clear interrupt by read/write(0/1) */ + int irq_base; /* IRQ base number of 88pm860x */ struct regulator_init_data *regulator[PM8607_MAX_REGULATOR]; }; @@ -368,12 +368,6 @@ extern int pm860x_bulk_write(struct i2c_client *, int, int, unsigned char *); extern int pm860x_set_bits(struct i2c_client *, int, unsigned char, unsigned char); -extern int pm860x_mask_irq(struct pm860x_chip *, int); -extern int pm860x_unmask_irq(struct pm860x_chip *, int); -extern int pm860x_request_irq(struct pm860x_chip *, int, - irq_handler_t handler, void *); -extern int pm860x_free_irq(struct pm860x_chip *, int); - extern int pm860x_device_init(struct pm860x_chip *chip, struct pm860x_platform_data *pdata); extern void pm860x_device_exit(struct pm860x_chip *chip); -- cgit v1.2.3 From 6985403138b74ad28c8ddac8baf88869556bec9a Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 3 Feb 2010 15:40:59 -0500 Subject: input: Support onkey in 88pm860x Signed-off-by: Haojian Zhuang Acked-by: Dmitry Torokhov Signed-off-by: Samuel Ortiz --- drivers/input/misc/88pm860x_onkey.c | 155 ++++++++++++++++++++++++++++++++++++ drivers/input/misc/Kconfig | 10 +++ drivers/input/misc/Makefile | 1 + 3 files changed, 166 insertions(+) create mode 100644 drivers/input/misc/88pm860x_onkey.c (limited to 'drivers') diff --git a/drivers/input/misc/88pm860x_onkey.c b/drivers/input/misc/88pm860x_onkey.c new file mode 100644 index 000000000000..69a48e8701b9 --- /dev/null +++ b/drivers/input/misc/88pm860x_onkey.c @@ -0,0 +1,155 @@ +/* + * 88pm860x_onkey.c - Marvell 88PM860x ONKEY driver + * + * Copyright (C) 2009-2010 Marvell International Ltd. + * Haojian Zhuang + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file "COPYING" in the main directory of this + * archive for more details. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PM8607_WAKEUP 0x0b + +#define LONG_ONKEY_EN (1 << 1) +#define ONKEY_STATUS (1 << 0) + +struct pm860x_onkey_info { + struct input_dev *idev; + struct pm860x_chip *chip; + struct i2c_client *i2c; + struct device *dev; + int irq; +}; + +/* 88PM860x gives us an interrupt when ONKEY is held */ +static irqreturn_t pm860x_onkey_handler(int irq, void *data) +{ + struct pm860x_onkey_info *info = data; + int ret; + + ret = pm860x_reg_read(info->i2c, PM8607_STATUS_2); + ret &= ONKEY_STATUS; + input_report_key(info->idev, KEY_POWER, ret); + input_sync(info->idev); + + /* Enable 8-second long onkey detection */ + pm860x_set_bits(info->i2c, PM8607_WAKEUP, 3, LONG_ONKEY_EN); + return IRQ_HANDLED; +} + +static int __devinit pm860x_onkey_probe(struct platform_device *pdev) +{ + struct pm860x_chip *chip = dev_get_drvdata(pdev->dev.parent); + struct pm860x_onkey_info *info; + int irq, ret; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "No IRQ resource!\n"); + return -EINVAL; + } + + info = kzalloc(sizeof(struct pm860x_onkey_info), GFP_KERNEL); + if (!info) + return -ENOMEM; + info->chip = chip; + info->i2c = (chip->id == CHIP_PM8607) ? chip->client : chip->companion; + info->dev = &pdev->dev; + info->irq = irq + chip->irq_base; + + info->idev = input_allocate_device(); + if (!info->idev) { + dev_err(chip->dev, "Failed to allocate input dev\n"); + ret = -ENOMEM; + goto out; + } + + info->idev->name = "88pm860x_on"; + info->idev->phys = "88pm860x_on/input0"; + info->idev->id.bustype = BUS_I2C; + info->idev->dev.parent = &pdev->dev; + info->irq = irq; + info->idev->evbit[0] = BIT_MASK(EV_KEY); + info->idev->keybit[BIT_WORD(KEY_POWER)] = BIT_MASK(KEY_POWER); + + ret = input_register_device(info->idev); + if (ret) { + dev_err(chip->dev, "Can't register input device: %d\n", ret); + goto out_reg; + } + + ret = request_threaded_irq(info->irq, NULL, pm860x_onkey_handler, + IRQF_ONESHOT, "onkey", info); + if (ret < 0) { + dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n", + info->irq, ret); + goto out_irq; + } + + platform_set_drvdata(pdev, info); + return 0; + +out_irq: + input_unregister_device(info->idev); + kfree(info); + return ret; + +out_reg: + input_free_device(info->idev); +out: + kfree(info); + return ret; +} + +static int __devexit pm860x_onkey_remove(struct platform_device *pdev) +{ + struct pm860x_onkey_info *info = platform_get_drvdata(pdev); + + free_irq(info->irq, info); + input_unregister_device(info->idev); + kfree(info); + return 0; +} + +static struct platform_driver pm860x_onkey_driver = { + .driver = { + .name = "88pm860x-onkey", + .owner = THIS_MODULE, + }, + .probe = pm860x_onkey_probe, + .remove = __devexit_p(pm860x_onkey_remove), +}; + +static int __init pm860x_onkey_init(void) +{ + return platform_driver_register(&pm860x_onkey_driver); +} +module_init(pm860x_onkey_init); + +static void __exit pm860x_onkey_exit(void) +{ + platform_driver_unregister(&pm860x_onkey_driver); +} +module_exit(pm860x_onkey_exit); + +MODULE_DESCRIPTION("Marvell 88PM860x ONKEY driver"); +MODULE_AUTHOR("Haojian Zhuang "); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 16ec5233441c..7097bfe581d7 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -12,6 +12,16 @@ menuconfig INPUT_MISC if INPUT_MISC +config INPUT_88PM860X_ONKEY + tristate "88PM860x ONKEY support" + depends on MFD_88PM860X + help + Support the ONKEY of Marvell 88PM860x PMICs as an input device + reporting power button status. + + To compile this driver as a module, choose M here: the module + will be called 88pm860x_onkey. + config INPUT_PCSPKR tristate "PC Speaker support" depends on PCSPKR_PLATFORM diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index a8b84854fb7b..b611615e24ad 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -4,6 +4,7 @@ # Each configuration option enables a list of files. +obj-$(CONFIG_INPUT_88PM860X_ONKEY) += 88pm860x_onkey.o obj-$(CONFIG_INPUT_APANEL) += apanel.o obj-$(CONFIG_INPUT_ATI_REMOTE) += ati_remote.o obj-$(CONFIG_INPUT_ATI_REMOTE2) += ati_remote2.o -- cgit v1.2.3 From 14e5c82ca32870698b7cbe54196e00682d929ca5 Mon Sep 17 00:00:00 2001 From: Eduardo Valentin Date: Thu, 11 Feb 2010 13:47:09 +0100 Subject: mfd: Fix twl_has_pwrbutton typo Change the typo CONFIG_INPUT_TWL4030_PWBUTTON_MODULE in the twl_has_pwrbutton definition to CONFIG_INPUT_TWL4030_PWRBUTTON_MODULE. Signed-off-by: Eduardo Valentin Signed-off-by: Christoph Egger Signed-off-by: Samuel Ortiz --- drivers/mfd/twl-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c index d81003f4867e..942a1e837819 100644 --- a/drivers/mfd/twl-core.c +++ b/drivers/mfd/twl-core.c @@ -123,7 +123,7 @@ #define TWL_NUM_SLAVES 4 #if defined(CONFIG_INPUT_TWL4030_PWRBUTTON) \ - || defined(CONFIG_INPUT_TWL4030_PWBUTTON_MODULE) + || defined(CONFIG_INPUT_TWL4030_PWRBUTTON_MODULE) #define twl_has_pwrbutton() true #else #define twl_has_pwrbutton() false -- cgit v1.2.3 From 91fedede0338eb6203cdd618d8ece873fdb7c22c Mon Sep 17 00:00:00 2001 From: Samuel Ortiz Date: Fri, 19 Feb 2010 11:07:59 +0100 Subject: mfd: Check for ACPI conflicts For ACPI based systems, we should check for ACPI conflicts when adding the platform devices. The test will always succeed for non ACPI platforms. Signed-off-by: Samuel Ortiz --- drivers/mfd/mfd-core.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c index ae15e495e20e..aa17f4bddc56 100644 --- a/drivers/mfd/mfd-core.c +++ b/drivers/mfd/mfd-core.c @@ -13,6 +13,7 @@ #include #include +#include #include static int mfd_add_device(struct device *parent, int id, @@ -62,6 +63,10 @@ static int mfd_add_device(struct device *parent, int id, res[r].start = cell->resources[r].start; res[r].end = cell->resources[r].end; } + + ret = acpi_check_resource_conflict(res); + if (ret) + goto fail_res; } platform_device_add_resources(pdev, res, cell->num_resources); -- cgit v1.2.3 From e82c60ae7d3a7f19c4b9b3e7bd6ea298fa5efe93 Mon Sep 17 00:00:00 2001 From: Denis Turischev Date: Fri, 19 Feb 2010 11:26:25 +0100 Subject: mfd: Introduce lpc_sch for Intel SCH LPC bridge Intel Poulsbo (SCH) chipset LPC bridge controller contains several functions. Creating and MFD driver for the LPC bridge controller allows simultaneous use of SMBus and GPIO interfaces on the SCH. Signed-off-by: Denis Turischev Signed-off-by: Samuel Ortiz --- drivers/mfd/Kconfig | 9 ++++ drivers/mfd/Makefile | 1 + drivers/mfd/lpc_sch.c | 133 ++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 drivers/mfd/lpc_sch.c (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 84a68d260772..9b25fe28233e 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -389,6 +389,15 @@ config MFD_TIMBERDALE The timberdale FPGA can be found on the Intel Atom development board for in-vehicle infontainment, called Russellville. + +config LPC_SCH + tristate "Intel SCH LPC" + depends on PCI + select MFD_CORE + help + LPC bridge function of the Intel SCH provides support for + System Management Bus and General Purpose I/O. + endmenu menu "Multimedia Capabilities Port drivers" diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 878cac691067..22715add99a7 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -62,3 +62,4 @@ obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o obj-$(CONFIG_AB4500_CORE) += ab4500-core.o obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o obj-$(CONFIG_PMIC_ADP5520) += adp5520.o +obj-$(CONFIG_LPC_SCH) += lpc_sch.o \ No newline at end of file diff --git a/drivers/mfd/lpc_sch.c b/drivers/mfd/lpc_sch.c new file mode 100644 index 000000000000..51b2f6065a0b --- /dev/null +++ b/drivers/mfd/lpc_sch.c @@ -0,0 +1,133 @@ +/* + * lpc_sch.c - LPC interface for Intel Poulsbo SCH + * + * LPC bridge function of the Intel SCH contains many other + * functional units, such as Interrupt controllers, Timers, + * Power Management, System Management, GPIO, RTC, and LPC + * Configuration Registers. + * + * Copyright (c) 2010 CompuLab Ltd + * Author: Denis Turischev + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SMBASE 0x40 +#define SMBUS_IO_SIZE 64 + +#define GPIOBASE 0x44 +#define GPIO_IO_SIZE 64 + +static struct resource smbus_sch_resource = { + .flags = IORESOURCE_IO, +}; + + +static struct resource gpio_sch_resource = { + .flags = IORESOURCE_IO, +}; + +static struct mfd_cell lpc_sch_cells[] = { + { + .name = "isch_smbus", + .num_resources = 1, + .resources = &smbus_sch_resource, + }, + { + .name = "sch_gpio", + .num_resources = 1, + .resources = &gpio_sch_resource, + }, +}; + +static struct pci_device_id lpc_sch_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC) }, + { 0, } +}; +MODULE_DEVICE_TABLE(pci, lpc_sch_ids); + +static int __devinit lpc_sch_probe(struct pci_dev *dev, + const struct pci_device_id *id) +{ + unsigned int base_addr_cfg; + unsigned short base_addr; + + pci_read_config_dword(dev, SMBASE, &base_addr_cfg); + if (!(base_addr_cfg & (1 << 31))) { + dev_err(&dev->dev, "Decode of the SMBus I/O range disabled\n"); + return -ENODEV; + } + base_addr = (unsigned short)base_addr_cfg; + if (base_addr == 0) { + dev_err(&dev->dev, "I/O space for SMBus uninitialized\n"); + return -ENODEV; + } + + smbus_sch_resource.start = base_addr; + smbus_sch_resource.end = base_addr + SMBUS_IO_SIZE - 1; + + pci_read_config_dword(dev, GPIOBASE, &base_addr_cfg); + if (!(base_addr_cfg & (1 << 31))) { + dev_err(&dev->dev, "Decode of the GPIO I/O range disabled\n"); + return -ENODEV; + } + base_addr = (unsigned short)base_addr_cfg; + if (base_addr == 0) { + dev_err(&dev->dev, "I/O space for GPIO uninitialized\n"); + return -ENODEV; + } + + gpio_sch_resource.start = base_addr; + gpio_sch_resource.end = base_addr + GPIO_IO_SIZE - 1; + + return mfd_add_devices(&dev->dev, -1, + lpc_sch_cells, ARRAY_SIZE(lpc_sch_cells), NULL, 0); +} + +static void __devexit lpc_sch_remove(struct pci_dev *dev) +{ + mfd_remove_devices(&dev->dev); +} + +static struct pci_driver lpc_sch_driver = { + .name = "lpc_sch", + .id_table = lpc_sch_ids, + .probe = lpc_sch_probe, + .remove = __devexit_p(lpc_sch_remove), +}; + +static int __init lpc_sch_init(void) +{ + return pci_register_driver(&lpc_sch_driver); +} + +static void __exit lpc_sch_exit(void) +{ + pci_unregister_driver(&lpc_sch_driver); +} + +module_init(lpc_sch_init); +module_exit(lpc_sch_exit); + +MODULE_AUTHOR("Denis Turischev "); +MODULE_DESCRIPTION("LPC interface for Intel Poulsbo SCH"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From a29aaf55cd6faa75e35abfe00bd3ffc537490485 Mon Sep 17 00:00:00 2001 From: Moiz Sonasath Date: Tue, 16 Feb 2010 18:57:21 -0600 Subject: mfd: Disable TWL4030/5030 I2C1/I2C4 internal pull-ups This patch disables TWL4030/5030 I2C1 adn I2C4(SR) internal pull-up, to use only the external HW resistor >=470 Ohm for the assured functionality in HS mode. While testing the I2C in High Speed mode, it was discovered that without a proper pull-up resistor, there is data corruption during multi-byte transfer. RTC(time_set) test case was used for testing. From the analysis done, it was concluded that ideally we need a pull-up of 1.6k Ohm(recomended) or atleast 470 Ohm or greater for assured performance in HS mode. Signed-off-by: Moiz Sonasath Signed-off-by: Allen Pais Signed-off-by: Samuel Ortiz --- drivers/mfd/twl-core.c | 13 +++++++++++++ include/linux/i2c/twl.h | 15 +++++++++++++++ 2 files changed, 28 insertions(+) (limited to 'drivers') diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c index 942a1e837819..7ccc39f3aa48 100644 --- a/drivers/mfd/twl-core.c +++ b/drivers/mfd/twl-core.c @@ -958,6 +958,7 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id) int status; unsigned i; struct twl4030_platform_data *pdata = client->dev.platform_data; + u8 temp; if (!pdata) { dev_dbg(&client->dev, "no platform data?\n"); @@ -1025,6 +1026,18 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id) goto fail; } + /* Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface. + * Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0, + * SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0. + */ + + if (twl_class_is_4030()) { + twl_i2c_read_u8(TWL4030_MODULE_INTBR, &temp, REG_GPPUPDCTR1); + temp &= ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \ + I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU); + twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1); + } + status = add_children(pdata, id->driver_data); fail: if (status < 0) diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index 9733e9e53f2b..e28d4c0e45bd 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -239,6 +239,21 @@ int twl6030_interrupt_mask(u8 bit_mask, u8 offset); /*----------------------------------------------------------------------*/ +/*Interface Bit Register (INTBR) offsets + *(Use TWL_4030_MODULE_INTBR) + */ + +#define REG_GPPUPDCTR1 0x0F + +/*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */ + +#define I2C_SCL_CTRL_PU BIT(0) +#define I2C_SDA_CTRL_PU BIT(2) +#define SR_I2C_SCL_CTRL_PU BIT(4) +#define SR_I2C_SDA_CTRL_PU BIT(6) + +/*----------------------------------------------------------------------*/ + /* * Keypad register offsets (use TWL4030_MODULE_KEYPAD) * ... SIH/interrupt only -- cgit v1.2.3 From fa0d976298b25d090fafc3460c63fee1c8eea854 Mon Sep 17 00:00:00 2001 From: Balaji T K Date: Fri, 19 Feb 2010 12:39:38 +0100 Subject: mfd: Add twl6030 base addr for ID0, ID1, ID2 Add base address for generic slave ID0, ID1, ID2 and introduced one more entry to align RTC module number between twl4030 and twl6030 Signed-off-by: Balaji T K Signed-off-by: Samuel Ortiz --- drivers/mfd/twl-core.c | 7 +++++-- include/linux/i2c/twl.h | 5 +++++ 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c index 7ccc39f3aa48..562cd4935e17 100644 --- a/drivers/mfd/twl-core.c +++ b/drivers/mfd/twl-core.c @@ -198,6 +198,7 @@ /* subchip/slave 3 0x4B - AUDIO */ #define TWL6030_BASEADD_AUDIO 0x0000 #define TWL6030_BASEADD_RSV 0x0000 +#define TWL6030_BASEADD_ZERO 0x0000 /* Few power values */ #define R_CFG_BOOT 0x05 @@ -313,9 +314,11 @@ static struct twl_mapping twl6030_map[] = { { SUB_CHIP_ID1, TWL6030_BASEADD_CHARGER }, { SUB_CHIP_ID1, TWL6030_BASEADD_GASGAUGE }, { SUB_CHIP_ID1, TWL6030_BASEADD_PWM }, - { SUB_CHIP_ID2, TWL6030_BASEADD_RSV }, - { SUB_CHIP_ID2, TWL6030_BASEADD_RSV }, + { SUB_CHIP_ID0, TWL6030_BASEADD_ZERO }, + { SUB_CHIP_ID1, TWL6030_BASEADD_ZERO }, + { SUB_CHIP_ID2, TWL6030_BASEADD_ZERO }, + { SUB_CHIP_ID2, TWL6030_BASEADD_ZERO }, { SUB_CHIP_ID2, TWL6030_BASEADD_RSV }, { SUB_CHIP_ID2, TWL6030_BASEADD_RSV }, { SUB_CHIP_ID2, TWL6030_BASEADD_RSV }, diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index e28d4c0e45bd..70d4caf48571 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -80,6 +80,11 @@ #define TWL_MODULE_PM_MASTER TWL4030_MODULE_PM_MASTER #define TWL_MODULE_PM_RECEIVER TWL4030_MODULE_PM_RECEIVER #define TWL_MODULE_RTC TWL4030_MODULE_RTC +#define TWL_MODULE_PWM TWL4030_MODULE_PWM0 + +#define TWL6030_MODULE_ID0 0x0D +#define TWL6030_MODULE_ID1 0x0E +#define TWL6030_MODULE_ID2 0x0F #define GPIO_INTR_OFFSET 0 #define KEYPAD_INTR_OFFSET 1 -- cgit v1.2.3 From a8c39d8deb8341d15fc0eabaa9750f7a1db9d0df Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 17 Feb 2010 16:37:45 +0900 Subject: tmio_mmc: Keep card-detect interrupts enabled On SuperH platforms the SDHI controller does not produce any command IRQs after a completed IO. This leads to card-detect interrupts staying disabled. Do not disable card-detect interrupts on DATA IRQs. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Magnus Damm Signed-off-by: Samuel Ortiz --- drivers/mmc/host/tmio_mmc.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h index 692dc23363b9..dafecfbcd91a 100644 --- a/drivers/mmc/host/tmio_mmc.h +++ b/drivers/mmc/host/tmio_mmc.h @@ -55,10 +55,8 @@ /* Define some IRQ masks */ /* This is the mask used at reset by the chip */ #define TMIO_MASK_ALL 0x837f031d -#define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND | \ - TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) -#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND | \ - TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) +#define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND) +#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND) #define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \ TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) #define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD) -- cgit v1.2.3 From b741d440a97c376af309e902eeb2f3c5673d2c92 Mon Sep 17 00:00:00 2001 From: Yusuke Goda Date: Wed, 17 Feb 2010 16:37:55 +0900 Subject: tmio_mmc: Add MMC_CAP_MMC_HIGHSPEED support V2 Enable MMC_CAP_XX support in the tmio_mmc driver if pdata->capabilities is set. Signed-off-by: Yusuke Goda Signed-off-by: Magnus Damm Signed-off-by: Samuel Ortiz --- drivers/mmc/host/tmio_mmc.c | 1 + include/linux/mfd/tmio.h | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c index e22c3fa3516a..e2c0cc9a0ca6 100644 --- a/drivers/mmc/host/tmio_mmc.c +++ b/drivers/mmc/host/tmio_mmc.c @@ -550,6 +550,7 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev) mmc->ops = &tmio_mmc_ops; mmc->caps = MMC_CAP_4_BIT_DATA; + mmc->caps |= pdata->capabilities; mmc->f_max = pdata->hclk; mmc->f_min = mmc->f_max / 512; mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h index 9cb1834deffa..37d941420ce4 100644 --- a/include/linux/mfd/tmio.h +++ b/include/linux/mfd/tmio.h @@ -60,6 +60,7 @@ void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state); */ struct tmio_mmc_data { const unsigned int hclk; + unsigned long capabilities; void (*set_pwr)(struct platform_device *host, int state); void (*set_clk_div)(struct platform_device *host, int state); }; -- cgit v1.2.3 From 6d9af5af61a6c30676ef6f56a791d4036c92d249 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 17 Feb 2010 16:38:04 +0900 Subject: tmio_mmc: Use 100ms mmc_detect_change() delay This patch changes the tmio_mmc driver to wait 100ms before checking the card detect status. This type of delay is quite common among mmc drivers, it seems that most hardware platforms need to give the hardware some time to settle before checking card availabilty. Hotplug is half-broken without this patch on the sh7724 Ecovec board. Hot insertion seems ok but eject is never detected without this patch. Signed-off-by: Magnus Damm Signed-off-by: Samuel Ortiz --- drivers/mmc/host/tmio_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c index e2c0cc9a0ca6..7b2376d4050a 100644 --- a/drivers/mmc/host/tmio_mmc.c +++ b/drivers/mmc/host/tmio_mmc.c @@ -323,7 +323,7 @@ static irqreturn_t tmio_mmc_irq(int irq, void *devid) if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) { ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE); - mmc_detect_change(host->mmc, 0); + mmc_detect_change(host->mmc, msecs_to_jiffies(100)); } /* CRC and other errors */ -- cgit v1.2.3 From 7ee422dc6e947fcdc153246d47f26ae0b7cf083d Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 17 Feb 2010 16:38:23 +0900 Subject: tmio_mmc: Balance cell enable()/disable() calls This patch adds cell->disable() calls to the tmio-mmc probe() error handling and the remove() function. Signed-off-by: Magnus Damm Signed-off-by: Samuel Ortiz --- drivers/mmc/host/tmio_mmc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c index 7b2376d4050a..b2b577f6afd4 100644 --- a/drivers/mmc/host/tmio_mmc.c +++ b/drivers/mmc/host/tmio_mmc.c @@ -569,14 +569,14 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev) if (ret >= 0) host->irq = ret; else - goto unmap_ctl; + goto cell_disable; disable_mmc_irqs(host, TMIO_MASK_ALL); ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED | IRQF_TRIGGER_FALLING, dev_name(&dev->dev), host); if (ret) - goto unmap_ctl; + goto cell_disable; mmc_add_host(mmc); @@ -588,6 +588,9 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev) return 0; +cell_disable: + if (cell->disable) + cell->disable(dev); unmap_ctl: iounmap(host->ctl); host_free: @@ -598,6 +601,7 @@ out: static int __devexit tmio_mmc_remove(struct platform_device *dev) { + struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data; struct mmc_host *mmc = platform_get_drvdata(dev); platform_set_drvdata(dev, NULL); @@ -606,6 +610,8 @@ static int __devexit tmio_mmc_remove(struct platform_device *dev) struct tmio_mmc_host *host = mmc_priv(mmc); mmc_remove_host(mmc); free_irq(host->irq, host); + if (cell->disable) + cell->disable(dev); iounmap(host->ctl); mmc_free_host(mmc); } -- cgit v1.2.3 From 3383d23d86791503559cb87837491af37469d9e5 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 17 Feb 2010 18:04:35 +0000 Subject: gpiolib: Actually set output state in wm831x_gpio_direction_output() wm831x_gpio_direction_output() ignored the state passed into it. Signed-off-by: Mark Brown Cc: stable@kernel.org Signed-off-by: Samuel Ortiz --- drivers/gpio/wm831x-gpio.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/wm831x-gpio.c b/drivers/gpio/wm831x-gpio.c index b4468b616890..c5a00f7a7bf0 100644 --- a/drivers/gpio/wm831x-gpio.c +++ b/drivers/gpio/wm831x-gpio.c @@ -60,23 +60,31 @@ static int wm831x_gpio_get(struct gpio_chip *chip, unsigned offset) return 0; } -static int wm831x_gpio_direction_out(struct gpio_chip *chip, - unsigned offset, int value) +static void wm831x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { struct wm831x_gpio *wm831x_gpio = to_wm831x_gpio(chip); struct wm831x *wm831x = wm831x_gpio->wm831x; - return wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + offset, - WM831X_GPN_DIR | WM831X_GPN_TRI, 0); + wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << offset, + value << offset); } -static void wm831x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +static int wm831x_gpio_direction_out(struct gpio_chip *chip, + unsigned offset, int value) { struct wm831x_gpio *wm831x_gpio = to_wm831x_gpio(chip); struct wm831x *wm831x = wm831x_gpio->wm831x; + int ret; - wm831x_set_bits(wm831x, WM831X_GPIO_LEVEL, 1 << offset, - value << offset); + ret = wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + offset, + WM831X_GPN_DIR | WM831X_GPN_TRI, 0); + if (ret < 0) + return ret; + + /* Can only set GPIO state once it's in output mode */ + wm831x_gpio_set(chip, offset, value); + + return 0; } static int wm831x_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -- cgit v1.2.3 From 6b8274fafeec9b112cee5b6ced5f9189957c889f Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 17 Feb 2010 18:45:24 +0000 Subject: gpiolib: Correct debugfs display of WM831x GPIO inversion Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/gpio/wm831x-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/wm831x-gpio.c b/drivers/gpio/wm831x-gpio.c index c5a00f7a7bf0..2554180534a1 100644 --- a/drivers/gpio/wm831x-gpio.c +++ b/drivers/gpio/wm831x-gpio.c @@ -176,7 +176,7 @@ static void wm831x_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) wm831x_gpio_get(chip, i) ? "high" : "low", pull, powerdomain, - reg & WM831X_GPN_POL ? " inverted" : "", + reg & WM831X_GPN_POL ? "" : " inverted", reg & WM831X_GPN_OD ? "open-drain" : "CMOS", reg & WM831X_GPN_TRI ? " tristated" : "", reg); -- cgit v1.2.3 From f92e8f8144243a3651b2e350b706ea2d04931f8c Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 17 Feb 2010 18:45:25 +0000 Subject: mfd: Add WM831x revision B support Revision B of the WM831x devices changes the sense of the tristate bit for GPIO configuration, inverting it to become an enable instead. Take account of this in the gpiolib driver. A current sink regulation status bit has also been added in revision B, add a flag indicating if it's present but don't use it yet. This revision also adds an interrupt on key up for the ON pin event which the existing code is able to take advantage of. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/gpio/wm831x-gpio.c | 21 ++++++++++++++++----- drivers/mfd/wm831x-core.c | 15 +++++++++++++++ include/linux/mfd/wm831x/core.h | 4 ++++ include/linux/mfd/wm831x/gpio.h | 4 ++++ 4 files changed, 39 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/wm831x-gpio.c b/drivers/gpio/wm831x-gpio.c index 2554180534a1..5b8dc098d80f 100644 --- a/drivers/gpio/wm831x-gpio.c +++ b/drivers/gpio/wm831x-gpio.c @@ -38,10 +38,13 @@ static int wm831x_gpio_direction_in(struct gpio_chip *chip, unsigned offset) { struct wm831x_gpio *wm831x_gpio = to_wm831x_gpio(chip); struct wm831x *wm831x = wm831x_gpio->wm831x; + int val = WM831X_GPN_DIR; + + if (wm831x->has_gpio_ena) + val |= WM831X_GPN_TRI; return wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + offset, - WM831X_GPN_DIR | WM831X_GPN_TRI, - WM831X_GPN_DIR); + WM831X_GPN_DIR | WM831X_GPN_TRI, val); } static int wm831x_gpio_get(struct gpio_chip *chip, unsigned offset) @@ -74,10 +77,14 @@ static int wm831x_gpio_direction_out(struct gpio_chip *chip, { struct wm831x_gpio *wm831x_gpio = to_wm831x_gpio(chip); struct wm831x *wm831x = wm831x_gpio->wm831x; + int val = 0; int ret; + if (wm831x->has_gpio_ena) + val |= WM831X_GPN_TRI; + ret = wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + offset, - WM831X_GPN_DIR | WM831X_GPN_TRI, 0); + WM831X_GPN_DIR | WM831X_GPN_TRI, val); if (ret < 0) return ret; @@ -103,7 +110,7 @@ static void wm831x_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) { struct wm831x_gpio *wm831x_gpio = to_wm831x_gpio(chip); struct wm831x *wm831x = wm831x_gpio->wm831x; - int i; + int i, tristated; for (i = 0; i < chip->ngpio; i++) { int gpio = i + chip->base; @@ -170,6 +177,10 @@ static void wm831x_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) break; } + tristated = reg & WM831X_GPN_TRI; + if (wm831x->has_gpio_ena) + tristated = !tristated; + seq_printf(s, " %s %s %s %s%s\n" " %s%s (0x%4x)\n", reg & WM831X_GPN_DIR ? "in" : "out", @@ -178,7 +189,7 @@ static void wm831x_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) powerdomain, reg & WM831X_GPN_POL ? "" : " inverted", reg & WM831X_GPN_OD ? "open-drain" : "CMOS", - reg & WM831X_GPN_TRI ? " tristated" : "", + tristated ? " tristated" : "", reg); } } diff --git a/drivers/mfd/wm831x-core.c b/drivers/mfd/wm831x-core.c index 4b2021af1d96..c428d9f918fc 100644 --- a/drivers/mfd/wm831x-core.c +++ b/drivers/mfd/wm831x-core.c @@ -1449,18 +1449,33 @@ static int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq) case WM8310: parent = WM8310; wm831x->num_gpio = 16; + if (rev > 0) { + wm831x->has_gpio_ena = 1; + wm831x->has_cs_sts = 1; + } + dev_info(wm831x->dev, "WM8310 revision %c\n", 'A' + rev); break; case WM8311: parent = WM8311; wm831x->num_gpio = 16; + if (rev > 0) { + wm831x->has_gpio_ena = 1; + wm831x->has_cs_sts = 1; + } + dev_info(wm831x->dev, "WM8311 revision %c\n", 'A' + rev); break; case WM8312: parent = WM8312; wm831x->num_gpio = 16; + if (rev > 0) { + wm831x->has_gpio_ena = 1; + wm831x->has_cs_sts = 1; + } + dev_info(wm831x->dev, "WM8312 revision %c\n", 'A' + rev); break; diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h index 5184b79c700b..53580b592bc9 100644 --- a/include/linux/mfd/wm831x/core.h +++ b/include/linux/mfd/wm831x/core.h @@ -254,6 +254,10 @@ struct wm831x { int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */ int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ + /* Chip revision based flags */ + unsigned has_gpio_ena:1; /* Has GPIO enable bit */ + unsigned has_cs_sts:1; /* Has current sink status bit */ + int num_gpio; struct mutex auxadc_lock; diff --git a/include/linux/mfd/wm831x/gpio.h b/include/linux/mfd/wm831x/gpio.h index 2835614af0e3..9b163c58865f 100644 --- a/include/linux/mfd/wm831x/gpio.h +++ b/include/linux/mfd/wm831x/gpio.h @@ -41,6 +41,10 @@ #define WM831X_GPN_OD_MASK 0x0200 /* GPN_OD */ #define WM831X_GPN_OD_SHIFT 9 /* GPN_OD */ #define WM831X_GPN_OD_WIDTH 1 /* GPN_OD */ +#define WM831X_GPN_ENA 0x0080 /* GPN_ENA */ +#define WM831X_GPN_ENA_MASK 0x0080 /* GPN_ENA */ +#define WM831X_GPN_ENA_SHIFT 7 /* GPN_ENA */ +#define WM831X_GPN_ENA_WIDTH 1 /* GPN_ENA */ #define WM831X_GPN_TRI 0x0080 /* GPN_TRI */ #define WM831X_GPN_TRI_MASK 0x0080 /* GPN_TRI */ #define WM831X_GPN_TRI_SHIFT 7 /* GPN_TRI */ -- cgit v1.2.3 From 1bca748cccec1c7f30b4424882de965100744432 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 17 Feb 2010 18:45:26 +0000 Subject: gpiolib: Force wm831x GPIOs into GPIO mode when requested This is the chip default but it's possible the bootloader or OTP will have been configured to a different mode (eg, to provide feedback during startup). Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/gpio/wm831x-gpio.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/wm831x-gpio.c b/drivers/gpio/wm831x-gpio.c index 5b8dc098d80f..d09021f4a7d3 100644 --- a/drivers/gpio/wm831x-gpio.c +++ b/drivers/gpio/wm831x-gpio.c @@ -44,7 +44,8 @@ static int wm831x_gpio_direction_in(struct gpio_chip *chip, unsigned offset) val |= WM831X_GPN_TRI; return wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + offset, - WM831X_GPN_DIR | WM831X_GPN_TRI, val); + WM831X_GPN_DIR | WM831X_GPN_TRI | + WM831X_GPN_FN_MASK, val); } static int wm831x_gpio_get(struct gpio_chip *chip, unsigned offset) @@ -84,7 +85,8 @@ static int wm831x_gpio_direction_out(struct gpio_chip *chip, val |= WM831X_GPN_TRI; ret = wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + offset, - WM831X_GPN_DIR | WM831X_GPN_TRI, val); + WM831X_GPN_DIR | WM831X_GPN_TRI | + WM831X_GPN_FN_MASK, val); if (ret < 0) return ret; -- cgit v1.2.3 From 3c49e810507c9d0659b8aa61f7f91aecda428ee3 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 22 Feb 2010 13:37:09 +0900 Subject: mfd: sh_mobile_sdhi MMC_CAP_MMC_HIGHSPEED support Add MMC_CAP_MMC_HIGHSPEED support to the sh_mobile_sdhi driver. Also, remove type cast and FIXME comment. Signed-off-by: Magnus Damm Signed-off-by: Samuel Ortiz --- drivers/mfd/sh_mobile_sdhi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/sh_mobile_sdhi.c b/drivers/mfd/sh_mobile_sdhi.c index 03efae8041ab..468fd366d4da 100644 --- a/drivers/mfd/sh_mobile_sdhi.c +++ b/drivers/mfd/sh_mobile_sdhi.c @@ -21,7 +21,7 @@ #include #include #include - +#include #include #include #include @@ -95,9 +95,9 @@ static int __init sh_mobile_sdhi_probe(struct platform_device *pdev) clk_enable(priv->clk); - /* FIXME: silly const unsigned int hclk */ - *(unsigned int *)&priv->mmc_data.hclk = clk_get_rate(priv->clk); + priv->mmc_data.hclk = clk_get_rate(priv->clk); priv->mmc_data.set_pwr = sh_mobile_sdhi_set_pwr; + priv->mmc_data.capabilities = MMC_CAP_MMC_HIGHSPEED; memcpy(&priv->cell_mmc, &sh_mobile_sdhi_cell, sizeof(priv->cell_mmc)); priv->cell_mmc.driver_data = &priv->mmc_data; -- cgit v1.2.3 From 3d8ca8c0b9fe42d005360e255fbf7a6f8580ef87 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 22 Feb 2010 13:40:59 +0900 Subject: mfd/mmc: SDHI Kconfig update Enable the sh_mobile_sdhi mfd driver on SH-Mobile ARM processors. While at it, make CONFIG_TMIO_MMC depend on CONFIG_MFD_SH_MOBILE_SDHI. Signed-off-by: Magnus Damm Signed-off-by: Samuel Ortiz --- drivers/mfd/Kconfig | 2 +- drivers/mmc/host/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 9b25fe28233e..951fa9b93fbe 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -47,7 +47,7 @@ config MFD_ASIC3 config MFD_SH_MOBILE_SDHI bool "Support for SuperH Mobile SDHI" - depends on SUPERH + depends on SUPERH || ARCH_SHMOBILE select MFD_CORE ---help--- This driver supports the SDHI hardware block found in many diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 7b431bbab7f1..2e13b94769fd 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -365,7 +365,7 @@ config MMC_SDRICOH_CS config MMC_TMIO tristate "Toshiba Mobile IO Controller (TMIO) MMC/SD function support" - depends on MFD_TMIO || MFD_ASIC3 || SUPERH + depends on MFD_TMIO || MFD_ASIC3 || MFD_SH_MOBILE_SDHI help This provides support for the SD/MMC cell found in TC6393XB, T7L66XB and also HTC ASIC3 -- cgit v1.2.3 From 11a441ce82d6ffecfd39b324024de0cd630b36c1 Mon Sep 17 00:00:00 2001 From: Mike Turquette Date: Mon, 22 Feb 2010 11:16:30 -0600 Subject: mfd: Introduce remove_script function for twl4030 New function twl4030_remove_script(u8 flags) takes a script type as defined in twl.h and prevents any script already loaded in that position from running. This is accomplished by programming SEQ_ADD_* to 0x3f, the END_OF_SCRIPT value, where SEQ_ADD_* is determined by flags. (Future) users of this function include OMAP board files for machines facing a race condition between sleep and warm reset. Signed-off-by: Mike Turquette Signed-off-by: Samuel Ortiz --- drivers/mfd/twl4030-power.c | 50 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/i2c/twl.h | 1 + 2 files changed, 51 insertions(+) (limited to 'drivers') diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c index 5b045ff4a2c2..7efa8789a3a2 100644 --- a/drivers/mfd/twl4030-power.c +++ b/drivers/mfd/twl4030-power.c @@ -461,6 +461,56 @@ out: return err; } +int twl4030_remove_script(u8 flags) +{ + int err = 0; + + err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, R_KEY_1, + R_PROTECT_KEY); + if (err) { + pr_err("twl4030: unable to unlock PROTECT_KEY\n"); + return err; + } + + err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, R_KEY_2, + R_PROTECT_KEY); + if (err) { + pr_err("twl4030: unable to unlock PROTECT_KEY\n"); + return err; + } + + if (flags & TWL4030_WRST_SCRIPT) { + err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, END_OF_SCRIPT, + R_SEQ_ADD_WARM); + if (err) + return err; + } + if (flags & TWL4030_WAKEUP12_SCRIPT) { + if (err) + err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, END_OF_SCRIPT, + R_SEQ_ADD_S2A12); + return err; + } + if (flags & TWL4030_WAKEUP3_SCRIPT) { + err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, END_OF_SCRIPT, + R_SEQ_ADD_S2A3); + if (err) + return err; + } + if (flags & TWL4030_SLEEP_SCRIPT) { + err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, END_OF_SCRIPT, + R_SEQ_ADD_A2S); + if (err) + return err; + } + + err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY); + if (err) + pr_err("TWL4030 Unable to relock registers\n"); + + return err; +} + void __init twl4030_power_init(struct twl4030_power_data *twl4030_scripts) { int err = 0; diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index 70d4caf48571..fb6784e86d5f 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -550,6 +550,7 @@ struct twl4030_power_data { }; extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts); +extern int twl4030_remove_script(u8 flags); struct twl4030_codec_audio_data { unsigned int audio_mclk; -- cgit v1.2.3 From d19663ac61a6e36eec655d3c84a106686ebddd2c Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 23 Feb 2010 11:08:05 +0000 Subject: mfd: Use completion interrupt for WM835x AUXADC Use the completion interrupt generated by the device rather than polling for conversions to complete. As a backup we still check the state of the AUXADC if we don't get a completion, mostly for systems that don't have the WM8350 interrupt infrastructure hooked up. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/mfd/wm8350-core.c | 35 +++++++++++++++++++++++++++++------ include/linux/mfd/wm8350/core.h | 2 ++ 2 files changed, 31 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/wm8350-core.c b/drivers/mfd/wm8350-core.c index 9a970bd68775..bd75807d5302 100644 --- a/drivers/mfd/wm8350-core.c +++ b/drivers/mfd/wm8350-core.c @@ -339,7 +339,6 @@ EXPORT_SYMBOL_GPL(wm8350_reg_unlock); int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref) { u16 reg, result = 0; - int tries = 5; if (channel < WM8350_AUXADC_AUX1 || channel > WM8350_AUXADC_TEMP) return -EINVAL; @@ -363,12 +362,13 @@ int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref) reg |= 1 << channel | WM8350_AUXADC_POLL; wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_1, reg); - do { - schedule_timeout_interruptible(1); - reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1); - } while ((reg & WM8350_AUXADC_POLL) && --tries); + /* We ignore the result of the completion and just check for a + * conversion result, allowing us to soldier on if the IRQ + * infrastructure is not set up for the chip. */ + wait_for_completion_timeout(&wm8350->auxadc_done, msecs_to_jiffies(5)); - if (!tries) + reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1); + if (reg & WM8350_AUXADC_POLL) dev_err(wm8350->dev, "adc chn %d read timeout\n", channel); else result = wm8350_reg_read(wm8350, @@ -385,6 +385,15 @@ int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref) } EXPORT_SYMBOL_GPL(wm8350_read_auxadc); +static irqreturn_t wm8350_auxadc_irq(int irq, void *irq_data) +{ + struct wm8350 *wm8350 = irq_data; + + complete(&wm8350->auxadc_done); + + return IRQ_HANDLED; +} + /* * Cache is always host endian. */ @@ -682,11 +691,22 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq, } mutex_init(&wm8350->auxadc_mutex); + init_completion(&wm8350->auxadc_done); ret = wm8350_irq_init(wm8350, irq, pdata); if (ret < 0) goto err; + if (wm8350->irq_base) { + ret = request_threaded_irq(wm8350->irq_base + + WM8350_IRQ_AUXADC_DATARDY, + NULL, wm8350_auxadc_irq, 0, + "auxadc", wm8350); + if (ret < 0) + dev_warn(wm8350->dev, + "Failed to request AUXADC IRQ: %d\n", ret); + } + if (pdata && pdata->init) { ret = pdata->init(wm8350); if (ret != 0) { @@ -736,6 +756,9 @@ void wm8350_device_exit(struct wm8350 *wm8350) platform_device_unregister(wm8350->gpio.pdev); platform_device_unregister(wm8350->codec.pdev); + if (wm8350->irq_base) + free_irq(wm8350->irq_base + WM8350_IRQ_AUXADC_DATARDY, wm8350); + wm8350_irq_exit(wm8350); kfree(wm8350->reg_cache); diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h index fae08aa65413..98fcc977e82b 100644 --- a/include/linux/mfd/wm8350/core.h +++ b/include/linux/mfd/wm8350/core.h @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -621,6 +622,7 @@ struct wm8350 { u16 *reg_cache; struct mutex auxadc_mutex; + struct completion auxadc_done; /* Interrupt handling */ struct mutex irq_lock; -- cgit v1.2.3 From 473fe73650b9f92114edbedfbb616561c1a0026c Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Tue, 23 Feb 2010 11:08:06 +0000 Subject: mfd: Use completion interrupt for WM831x AUXADC Use the completion interrupt generated by the device rather than polling for conversions to complete. As a backup we still check the status of the AUXADC if we don't get a completion, mostly for systems that don't have the WM831x interrupt infrastructure hooked up. Also reduce the timeout for completion of conversions to 5ms from the previous 10ms, the lower timeout should be sufficient. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/mfd/wm831x-core.c | 36 +++++++++++++++++++++++++++++------- include/linux/mfd/wm831x/core.h | 2 ++ 2 files changed, 31 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/wm831x-core.c b/drivers/mfd/wm831x-core.c index c428d9f918fc..07101e9e1cba 100644 --- a/drivers/mfd/wm831x-core.c +++ b/drivers/mfd/wm831x-core.c @@ -321,7 +321,6 @@ EXPORT_SYMBOL_GPL(wm831x_set_bits); */ int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input) { - int tries = 10; int ret, src; mutex_lock(&wm831x->auxadc_lock); @@ -349,13 +348,14 @@ int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input) goto disable; } - do { - msleep(1); + /* Ignore the result to allow us to soldier on without IRQ hookup */ + wait_for_completion_timeout(&wm831x->auxadc_done, msecs_to_jiffies(5)); - ret = wm831x_reg_read(wm831x, WM831X_AUXADC_CONTROL); - if (ret < 0) - ret = WM831X_AUX_CVT_ENA; - } while ((ret & WM831X_AUX_CVT_ENA) && --tries); + ret = wm831x_reg_read(wm831x, WM831X_AUXADC_CONTROL); + if (ret < 0) { + dev_err(wm831x->dev, "AUXADC status read failed: %d\n", ret); + goto disable; + } if (ret & WM831X_AUX_CVT_ENA) { dev_err(wm831x->dev, "Timed out reading AUXADC\n"); @@ -390,6 +390,15 @@ out: } EXPORT_SYMBOL_GPL(wm831x_auxadc_read); +static irqreturn_t wm831x_auxadc_irq(int irq, void *irq_data) +{ + struct wm831x *wm831x = irq_data; + + complete(&wm831x->auxadc_done); + + return IRQ_HANDLED; +} + /** * wm831x_auxadc_read_uv: Read a voltage from the WM831x AUXADC * @@ -1411,6 +1420,7 @@ static int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq) mutex_init(&wm831x->io_lock); mutex_init(&wm831x->key_lock); mutex_init(&wm831x->auxadc_lock); + init_completion(&wm831x->auxadc_done); dev_set_drvdata(wm831x->dev, wm831x); ret = wm831x_reg_read(wm831x, WM831X_PARENT_ID); @@ -1523,6 +1533,16 @@ static int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq) if (ret != 0) goto err; + if (wm831x->irq_base) { + ret = request_threaded_irq(wm831x->irq_base + + WM831X_IRQ_AUXADC_DATA, + NULL, wm831x_auxadc_irq, 0, + "auxadc", wm831x); + if (ret < 0) + dev_err(wm831x->dev, "AUXADC IRQ request failed: %d\n", + ret); + } + /* The core device is up, instantiate the subdevices. */ switch (parent) { case WM8310: @@ -1593,6 +1613,8 @@ static void wm831x_device_exit(struct wm831x *wm831x) { wm831x_otp_exit(wm831x); mfd_remove_devices(wm831x->dev); + if (wm831x->irq_base) + free_irq(wm831x->irq_base + WM831X_IRQ_AUXADC_DATA, wm831x); wm831x_irq_exit(wm831x); kfree(wm831x); } diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h index 53580b592bc9..5915f6e3d9ab 100644 --- a/include/linux/mfd/wm831x/core.h +++ b/include/linux/mfd/wm831x/core.h @@ -15,6 +15,7 @@ #ifndef __MFD_WM831X_CORE_H__ #define __MFD_WM831X_CORE_H__ +#include #include /* @@ -261,6 +262,7 @@ struct wm831x { int num_gpio; struct mutex auxadc_lock; + struct completion auxadc_done; /* The WM831x has a security key blocking access to certain * registers. The mutex is taken by the accessors for locking -- cgit v1.2.3 From fd46a0064af171c90664e5b7165c0c9f94478a87 Mon Sep 17 00:00:00 2001 From: Denis Turischev Date: Mon, 1 Mar 2010 18:59:55 +0200 Subject: i2c: convert i2c-isch to platform_device Convert i2c-isch to platform_device for the lpc mfd core to add it at probe time. Signed-off-by: Denis Turischev Signed-off-by: Samuel Ortiz --- drivers/i2c/busses/Kconfig | 2 +- drivers/i2c/busses/i2c-isch.c | 68 +++++++++++++++++-------------------------- 2 files changed, 28 insertions(+), 42 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 4cc3807bd31c..f22eff1da87e 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -105,7 +105,7 @@ config I2C_I801 config I2C_ISCH tristate "Intel SCH SMBus 1.0" - depends on PCI + select LPC_SCH help Say Y here if you want to use SMBus controller on the Intel SCH based systems. diff --git a/drivers/i2c/busses/i2c-isch.c b/drivers/i2c/busses/i2c-isch.c index 69c22f79f231..ddc258edb34f 100644 --- a/drivers/i2c/busses/i2c-isch.c +++ b/drivers/i2c/busses/i2c-isch.c @@ -27,7 +27,7 @@ */ #include -#include +#include #include #include #include @@ -46,12 +46,6 @@ #define SMBHSTDAT1 (7 + sch_smba) #define SMBBLKDAT (0x20 + sch_smba) -/* count for request_region */ -#define SMBIOSIZE 64 - -/* PCI Address Constants */ -#define SMBBA_SCH 0x40 - /* Other settings */ #define MAX_TIMEOUT 500 @@ -63,7 +57,6 @@ #define SCH_BLOCK_DATA 0x05 static unsigned short sch_smba; -static struct pci_driver sch_driver; static struct i2c_adapter sch_adapter; /* @@ -256,37 +249,23 @@ static struct i2c_adapter sch_adapter = { .algo = &smbus_algorithm, }; -static const struct pci_device_id sch_ids[] = { - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC) }, - { 0, } -}; - -MODULE_DEVICE_TABLE(pci, sch_ids); - -static int __devinit sch_probe(struct pci_dev *dev, - const struct pci_device_id *id) +static int __devinit smbus_sch_probe(struct platform_device *dev) { + struct resource *res; int retval; - unsigned int smba; - pci_read_config_dword(dev, SMBBA_SCH, &smba); - if (!(smba & (1 << 31))) { - dev_err(&dev->dev, "SMBus I/O space disabled!\n"); - return -ENODEV; - } + res = platform_get_resource(dev, IORESOURCE_IO, 0); + if (!res) + return -EBUSY; - sch_smba = (unsigned short)smba; - if (sch_smba == 0) { - dev_err(&dev->dev, "SMBus base address uninitialized!\n"); - return -ENODEV; - } - if (acpi_check_region(sch_smba, SMBIOSIZE, sch_driver.name)) - return -ENODEV; - if (!request_region(sch_smba, SMBIOSIZE, sch_driver.name)) { + if (!request_region(res->start, resource_size(res), dev->name)) { dev_err(&dev->dev, "SMBus region 0x%x already in use!\n", sch_smba); return -EBUSY; } + + sch_smba = res->start; + dev_dbg(&dev->dev, "SMBA = 0x%X\n", sch_smba); /* set up the sysfs linkage to our parent device */ @@ -298,37 +277,43 @@ static int __devinit sch_probe(struct pci_dev *dev, retval = i2c_add_adapter(&sch_adapter); if (retval) { dev_err(&dev->dev, "Couldn't register adapter!\n"); - release_region(sch_smba, SMBIOSIZE); + release_region(res->start, resource_size(res)); sch_smba = 0; } return retval; } -static void __devexit sch_remove(struct pci_dev *dev) +static int __devexit smbus_sch_remove(struct platform_device *pdev) { + struct resource *res; if (sch_smba) { i2c_del_adapter(&sch_adapter); - release_region(sch_smba, SMBIOSIZE); + res = platform_get_resource(pdev, IORESOURCE_IO, 0); + release_region(res->start, resource_size(res)); sch_smba = 0; } + + return 0; } -static struct pci_driver sch_driver = { - .name = "isch_smbus", - .id_table = sch_ids, - .probe = sch_probe, - .remove = __devexit_p(sch_remove), +static struct platform_driver smbus_sch_driver = { + .driver = { + .name = "isch_smbus", + .owner = THIS_MODULE, + }, + .probe = smbus_sch_probe, + .remove = __devexit_p(smbus_sch_remove), }; static int __init i2c_sch_init(void) { - return pci_register_driver(&sch_driver); + return platform_driver_register(&smbus_sch_driver); } static void __exit i2c_sch_exit(void) { - pci_unregister_driver(&sch_driver); + platform_driver_unregister(&smbus_sch_driver); } MODULE_AUTHOR("Jacob Pan "); @@ -337,3 +322,4 @@ MODULE_LICENSE("GPL"); module_init(i2c_sch_init); module_exit(i2c_sch_exit); +MODULE_ALIAS("platform:isch_smbus"); -- cgit v1.2.3 From be9b06b2d80fe661491138c6993f944babb26260 Mon Sep 17 00:00:00 2001 From: Denis Turischev Date: Tue, 2 Mar 2010 10:48:55 +0100 Subject: gpio: add Intel SCH GPIO controller driver Signed-off-by: Denis Turischev Signed-off-by: Samuel Ortiz --- drivers/gpio/Kconfig | 16 +++ drivers/gpio/Makefile | 1 + drivers/gpio/sch_gpio.c | 282 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 299 insertions(+) create mode 100644 drivers/gpio/sch_gpio.c (limited to 'drivers') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f42cb317a779..60cb3632c8fd 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -94,6 +94,22 @@ config GPIO_VR41XX help Say yes here to support the NEC VR4100 series General-purpose I/O Uint +config GPIO_SCH + tristate "Intel SCH GPIO" + depends on GPIOLIB + select LPC_SCH + help + Say yes here to support GPIO interface on Intel Poulsbo SCH. + The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are + powered by the core power rail and are turned off during sleep + modes (S3 and higher). The remaining four GPIOs are powered by + the Intel SCH suspend power supply. These GPIOs remain + active during S3. The suspend powered GPIOs can be used to wake the + system from the Suspend-to-RAM state. + + This driver can also be built as a module. If so, the module + will be called sch-gpio. + comment "I2C GPIO expanders:" config GPIO_MAX7300 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 594bb70f65af..10f3f8d958b1 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,3 +27,4 @@ obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o obj-$(CONFIG_GPIO_WM831X) += wm831x-gpio.o obj-$(CONFIG_GPIO_WM8350) += wm8350-gpiolib.o obj-$(CONFIG_GPIO_WM8994) += wm8994-gpio.o +obj-$(CONFIG_GPIO_SCH) += sch_gpio.o \ No newline at end of file diff --git a/drivers/gpio/sch_gpio.c b/drivers/gpio/sch_gpio.c new file mode 100644 index 000000000000..761071ae3596 --- /dev/null +++ b/drivers/gpio/sch_gpio.c @@ -0,0 +1,282 @@ +/* + * sch_gpio.c - GPIO interface for Intel Poulsbo SCH + * + * Copyright (c) 2010 CompuLab Ltd + * Author: Denis Turischev + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +static DEFINE_SPINLOCK(gpio_lock); + +#define CGEN (0x00) +#define CGIO (0x04) +#define CGLV (0x08) + +#define RGEN (0x20) +#define RGIO (0x24) +#define RGLV (0x28) + +static unsigned short gpio_ba; + +static int sch_gpio_core_direction_in(struct gpio_chip *gc, unsigned gpio_num) +{ + u8 curr_dirs; + unsigned short offset, bit; + + spin_lock(&gpio_lock); + + offset = CGIO + gpio_num / 8; + bit = gpio_num % 8; + + curr_dirs = inb(gpio_ba + offset); + + if (!(curr_dirs & (1 << bit))) + outb(curr_dirs | (1 << bit), gpio_ba + offset); + + spin_unlock(&gpio_lock); + return 0; +} + +static int sch_gpio_core_get(struct gpio_chip *gc, unsigned gpio_num) +{ + int res; + unsigned short offset, bit; + + offset = CGLV + gpio_num / 8; + bit = gpio_num % 8; + + res = !!(inb(gpio_ba + offset) & (1 << bit)); + return res; +} + +static void sch_gpio_core_set(struct gpio_chip *gc, unsigned gpio_num, int val) +{ + u8 curr_vals; + unsigned short offset, bit; + + spin_lock(&gpio_lock); + + offset = CGLV + gpio_num / 8; + bit = gpio_num % 8; + + curr_vals = inb(gpio_ba + offset); + + if (val) + outb(curr_vals | (1 << bit), gpio_ba + offset); + else + outb((curr_vals & ~(1 << bit)), gpio_ba + offset); + spin_unlock(&gpio_lock); +} + +static int sch_gpio_core_direction_out(struct gpio_chip *gc, + unsigned gpio_num, int val) +{ + u8 curr_dirs; + unsigned short offset, bit; + + sch_gpio_core_set(gc, gpio_num, val); + + spin_lock(&gpio_lock); + + offset = CGIO + gpio_num / 8; + bit = gpio_num % 8; + + curr_dirs = inb(gpio_ba + offset); + if (curr_dirs & (1 << bit)) + outb(curr_dirs & ~(1 << bit), gpio_ba + offset); + + spin_unlock(&gpio_lock); + return 0; +} + +static struct gpio_chip sch_gpio_core = { + .label = "sch_gpio_core", + .owner = THIS_MODULE, + .direction_input = sch_gpio_core_direction_in, + .get = sch_gpio_core_get, + .direction_output = sch_gpio_core_direction_out, + .set = sch_gpio_core_set, +}; + +static int sch_gpio_resume_direction_in(struct gpio_chip *gc, + unsigned gpio_num) +{ + u8 curr_dirs; + + spin_lock(&gpio_lock); + + curr_dirs = inb(gpio_ba + RGIO); + + if (!(curr_dirs & (1 << gpio_num))) + outb(curr_dirs | (1 << gpio_num) , gpio_ba + RGIO); + + spin_unlock(&gpio_lock); + return 0; +} + +static int sch_gpio_resume_get(struct gpio_chip *gc, unsigned gpio_num) +{ + return !!(inb(gpio_ba + RGLV) & (1 << gpio_num)); +} + +static void sch_gpio_resume_set(struct gpio_chip *gc, + unsigned gpio_num, int val) +{ + u8 curr_vals; + + spin_lock(&gpio_lock); + + curr_vals = inb(gpio_ba + RGLV); + + if (val) + outb(curr_vals | (1 << gpio_num), gpio_ba + RGLV); + else + outb((curr_vals & ~(1 << gpio_num)), gpio_ba + RGLV); + + spin_unlock(&gpio_lock); +} + +static int sch_gpio_resume_direction_out(struct gpio_chip *gc, + unsigned gpio_num, int val) +{ + u8 curr_dirs; + + sch_gpio_resume_set(gc, gpio_num, val); + + spin_lock(&gpio_lock); + + curr_dirs = inb(gpio_ba + RGIO); + if (curr_dirs & (1 << gpio_num)) + outb(curr_dirs & ~(1 << gpio_num), gpio_ba + RGIO); + + spin_unlock(&gpio_lock); + return 0; +} + +static struct gpio_chip sch_gpio_resume = { + .label = "sch_gpio_resume", + .owner = THIS_MODULE, + .direction_input = sch_gpio_resume_direction_in, + .get = sch_gpio_resume_get, + .direction_output = sch_gpio_resume_direction_out, + .set = sch_gpio_resume_set, +}; + +static int __devinit sch_gpio_probe(struct platform_device *pdev) +{ + struct resource *res; + int err; + + res = platform_get_resource(pdev, IORESOURCE_IO, 0); + if (!res) + return -EBUSY; + + if (!request_region(res->start, resource_size(res), pdev->name)) + return -EBUSY; + + gpio_ba = res->start; + + sch_gpio_core.base = 0; + sch_gpio_core.ngpio = 10; + sch_gpio_core.dev = &pdev->dev; + + sch_gpio_resume.base = 10; + sch_gpio_resume.ngpio = 4; + sch_gpio_resume.dev = &pdev->dev; + + err = gpiochip_add(&sch_gpio_core); + if (err < 0) + goto err_sch_gpio_core; + + err = gpiochip_add(&sch_gpio_resume); + if (err < 0) + goto err_sch_gpio_resume; + + /* + * GPIO[6:0] enabled by default + * GPIO7 is configured by the CMC as SLPIOVR + * Enable GPIO[9:8] core powered gpios explicitly + */ + outb(0x3, gpio_ba + CGEN + 1); + /* + * SUS_GPIO[2:0] enabled by default + * Enable SUS_GPIO3 resume powered gpio explicitly + */ + outb(0x8, gpio_ba + RGEN); + + return 0; + +err_sch_gpio_resume: + gpiochip_remove(&sch_gpio_core); + +err_sch_gpio_core: + release_region(res->start, resource_size(res)); + gpio_ba = 0; + + return err; +} + +static int __devexit sch_gpio_remove(struct platform_device *pdev) +{ + struct resource *res; + if (gpio_ba) { + gpiochip_remove(&sch_gpio_core); + gpiochip_remove(&sch_gpio_resume); + + res = platform_get_resource(pdev, IORESOURCE_IO, 0); + + release_region(res->start, resource_size(res)); + gpio_ba = 0; + } + + return 0; +} + +static struct platform_driver sch_gpio_driver = { + .driver = { + .name = "sch_gpio", + .owner = THIS_MODULE, + }, + .probe = sch_gpio_probe, + .remove = __devexit_p(sch_gpio_remove), +}; + +static int __init sch_gpio_init(void) +{ + return platform_driver_register(&sch_gpio_driver); +} + +static void __exit sch_gpio_exit(void) +{ + platform_driver_unregister(&sch_gpio_driver); +} + +module_init(sch_gpio_init); +module_exit(sch_gpio_exit); + +MODULE_AUTHOR("Denis Turischev "); +MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:sch_gpio"); -- cgit v1.2.3 From 8e7aafe41be2a7cd5c181ed68876e9ec55ccdba7 Mon Sep 17 00:00:00 2001 From: Samuel Ortiz Date: Fri, 5 Mar 2010 17:14:01 +0100 Subject: gpio: Fix sch_gpio warning We need to check for gpiochip_remove() errors. Signed-off-by: Samuel Ortiz --- drivers/gpio/sch_gpio.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/sch_gpio.c b/drivers/gpio/sch_gpio.c index 761071ae3596..583521352c16 100644 --- a/drivers/gpio/sch_gpio.c +++ b/drivers/gpio/sch_gpio.c @@ -229,7 +229,10 @@ static int __devinit sch_gpio_probe(struct platform_device *pdev) return 0; err_sch_gpio_resume: - gpiochip_remove(&sch_gpio_core); + err = gpiochip_remove(&sch_gpio_core); + if (err) + dev_err(&pdev->dev, "%s failed, %d\n", + "gpiochip_remove()", err); err_sch_gpio_core: release_region(res->start, resource_size(res)); @@ -242,13 +245,23 @@ static int __devexit sch_gpio_remove(struct platform_device *pdev) { struct resource *res; if (gpio_ba) { - gpiochip_remove(&sch_gpio_core); - gpiochip_remove(&sch_gpio_resume); + int err; + + err = gpiochip_remove(&sch_gpio_core); + if (err) + dev_err(&pdev->dev, "%s failed, %d\n", + "gpiochip_remove()", err); + err = gpiochip_remove(&sch_gpio_resume); + if (err) + dev_err(&pdev->dev, "%s failed, %d\n", + "gpiochip_remove()", err); res = platform_get_resource(pdev, IORESOURCE_IO, 0); release_region(res->start, resource_size(res)); gpio_ba = 0; + + return err; } return 0; -- cgit v1.2.3 From 860fb8c134ebca9be8bc2ddd2b13e19ac10c192e Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Fri, 5 Mar 2010 09:43:06 -0800 Subject: mfd: Fix lpc_sch related depends/selects, fix build error LPC_SCH is selected by GPI_SCH and I2C_ISCH, even when PCI is not enabled, but LPC_SCH depends on PCI, so make GPI_SCH and I2C_ISCH also depend on PCI. Those 2 selects also need to select what LPC_SCH selects, since kconfig does not follow selects. Signed-off-by: Randy Dunlap Cc: Denis Turischev Signed-off-by: Samuel Ortiz --- drivers/gpio/Kconfig | 3 ++- drivers/i2c/busses/Kconfig | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 60cb3632c8fd..fee678f74a19 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -96,7 +96,8 @@ config GPIO_VR41XX config GPIO_SCH tristate "Intel SCH GPIO" - depends on GPIOLIB + depends on GPIOLIB && PCI + select MFD_CORE select LPC_SCH help Say yes here to support GPIO interface on Intel Poulsbo SCH. diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index f22eff1da87e..4cd1ff77ceda 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -105,6 +105,8 @@ config I2C_I801 config I2C_ISCH tristate "Intel SCH SMBus 1.0" + depends on PCI + select MFD_CORE select LPC_SCH help Say Y here if you want to use SMBus controller on the Intel SCH -- cgit v1.2.3 From 2c08583c6a6b4c5f5dea4cb0931eca82af7db6fe Mon Sep 17 00:00:00 2001 From: Peter Huewe Date: Sat, 6 Mar 2010 14:36:38 +0100 Subject: mfd: Fix ucb1x00 build failure for collie_defconfig This patch fixes a build failure[1], by adding the missing semaphore.h include References: [1] http://kisskb.ellerman.id.au/kisskb/buildresult/2234322/ Signed-off-by: Peter Huewe Signed-off-by: Samuel Ortiz --- drivers/mfd/ucb1x00-core.c | 1 + include/linux/mfd/ucb1x00.h | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/mfd/ucb1x00-core.c b/drivers/mfd/ucb1x00-core.c index 252b74188ec2..b281217334eb 100644 --- a/drivers/mfd/ucb1x00-core.c +++ b/drivers/mfd/ucb1x00-core.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/include/linux/mfd/ucb1x00.h b/include/linux/mfd/ucb1x00.h index aa9c3789bed4..4321f044d1e4 100644 --- a/include/linux/mfd/ucb1x00.h +++ b/include/linux/mfd/ucb1x00.h @@ -12,6 +12,7 @@ #include #include +#include #define UCB_IO_DATA 0x00 #define UCB_IO_DIR 0x01 -- cgit v1.2.3 From 3f9900f17cdb0366d234c0487df80a6b0d18c852 Mon Sep 17 00:00:00 2001 From: srinidhi kasagar Date: Mon, 1 Feb 2010 19:44:54 +0530 Subject: i2c: Add support for Ux500/Nomadik I2C controller This adds support for ST-Ericsson's I2C block found in Ux500 and Nomadik 8815 platforms. Signed-off-by: srinidhi kasagar Acked-by: Andrea Gallo Acked-by: Linus Walleij Reviewed-by: Linus Walleij Signed-off-by: Ben Dooks --- drivers/i2c/busses/Kconfig | 7 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-nomadik.c | 959 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 967 insertions(+) create mode 100644 drivers/i2c/busses/i2c-nomadik.c (limited to 'drivers') diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 4cc3807bd31c..10041813c6ed 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -440,6 +440,13 @@ config I2C_MV64XXX This driver can also be built as a module. If so, the module will be called i2c-mv64xxx. +config I2C_NOMADIK + tristate "ST-Ericsson Nomadik/Ux500 I2C Controller" + depends on PLAT_NOMADIK + help + If you say yes to this option, support will be included for the + I2C interface from ST-Ericsson's Nomadik and Ux500 architectures. + config I2C_OCORES tristate "OpenCores I2C Controller" depends on EXPERIMENTAL diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index c2c4ea1908d8..59abcf48e6a9 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o obj-$(CONFIG_I2C_MPC) += i2c-mpc.o obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o +obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o obj-$(CONFIG_I2C_OMAP) += i2c-omap.o obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c new file mode 100644 index 000000000000..a15f731fa451 --- /dev/null +++ b/drivers/i2c/busses/i2c-nomadik.c @@ -0,0 +1,959 @@ +/* + * Copyright (C) 2009 ST-Ericsson + * Copyright (C) 2009 STMicroelectronics + * + * I2C master mode controller driver, used in Nomadik 8815 + * and Ux500 platforms. + * + * Author: Srinidhi Kasagar + * Author: Sachin Verma + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define DRIVER_NAME "nmk-i2c" + +/* I2C Controller register offsets */ +#define I2C_CR (0x000) +#define I2C_SCR (0x004) +#define I2C_HSMCR (0x008) +#define I2C_MCR (0x00C) +#define I2C_TFR (0x010) +#define I2C_SR (0x014) +#define I2C_RFR (0x018) +#define I2C_TFTR (0x01C) +#define I2C_RFTR (0x020) +#define I2C_DMAR (0x024) +#define I2C_BRCR (0x028) +#define I2C_IMSCR (0x02C) +#define I2C_RISR (0x030) +#define I2C_MISR (0x034) +#define I2C_ICR (0x038) + +/* Control registers */ +#define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */ +#define I2C_CR_OM (0x3 << 1) /* Operating mode */ +#define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */ +#define I2C_CR_SM (0x3 << 4) /* Speed mode */ +#define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */ +#define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */ +#define I2C_CR_FRX (0x1 << 8) /* Flush Receive */ +#define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */ +#define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */ +#define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */ +#define I2C_CR_LM (0x1 << 12) /* Loopback mode */ +#define I2C_CR_FON (0x3 << 13) /* Filtering on */ +#define I2C_CR_FS (0x3 << 15) /* Force stop enable */ + +/* Master controller (MCR) register */ +#define I2C_MCR_OP (0x1 << 0) /* Operation */ +#define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ +#define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ +#define I2C_MCR_SB (0x1 << 11) /* Extended address */ +#define I2C_MCR_AM (0x3 << 12) /* Address type */ +#define I2C_MCR_STOP (0x1 << 14) /* Stop condition */ +#define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */ + +/* Status register (SR) */ +#define I2C_SR_OP (0x3 << 0) /* Operation */ +#define I2C_SR_STATUS (0x3 << 2) /* controller status */ +#define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */ +#define I2C_SR_TYPE (0x3 << 7) /* Receive type */ +#define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */ + +/* Interrupt mask set/clear (IMSCR) bits */ +#define I2C_IT_TXFE (0x1 << 0) +#define I2C_IT_TXFNE (0x1 << 1) +#define I2C_IT_TXFF (0x1 << 2) +#define I2C_IT_TXFOVR (0x1 << 3) +#define I2C_IT_RXFE (0x1 << 4) +#define I2C_IT_RXFNF (0x1 << 5) +#define I2C_IT_RXFF (0x1 << 6) +#define I2C_IT_RFSR (0x1 << 16) +#define I2C_IT_RFSE (0x1 << 17) +#define I2C_IT_WTSR (0x1 << 18) +#define I2C_IT_MTD (0x1 << 19) +#define I2C_IT_STD (0x1 << 20) +#define I2C_IT_MAL (0x1 << 24) +#define I2C_IT_BERR (0x1 << 25) +#define I2C_IT_MTDWS (0x1 << 28) + +#define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) + +/* some bits in ICR are reserved */ +#define I2C_CLEAR_ALL_INTS 0x131f007f + +/* first three msb bits are reserved */ +#define IRQ_MASK(mask) (mask & 0x1fffffff) + +/* maximum threshold value */ +#define MAX_I2C_FIFO_THRESHOLD 15 + +enum i2c_status { + I2C_NOP, + I2C_ON_GOING, + I2C_OK, + I2C_ABORT +}; + +/* operation */ +enum i2c_operation { + I2C_NO_OPERATION = 0xff, + I2C_WRITE = 0x00, + I2C_READ = 0x01 +}; + +/* controller response timeout in ms */ +#define I2C_TIMEOUT_MS 500 + +/** + * struct i2c_nmk_client - client specific data + * @slave_adr: 7-bit slave address + * @count: no. bytes to be transfered + * @buffer: client data buffer + * @xfer_bytes: bytes transfered till now + * @operation: current I2C operation + */ +struct i2c_nmk_client { + unsigned short slave_adr; + unsigned long count; + unsigned char *buffer; + unsigned long xfer_bytes; + enum i2c_operation operation; +}; + +/** + * struct nmk_i2c_dev - private data structure of the controller + * @pdev: parent platform device + * @adap: corresponding I2C adapter + * @irq: interrupt line for the controller + * @virtbase: virtual io memory area + * @clk: hardware i2c block clock + * @cfg: machine provided controller configuration + * @cli: holder of client specific data + * @stop: stop condition + * @xfer_complete: acknowledge completion for a I2C message + * @result: controller propogated result + */ +struct nmk_i2c_dev { + struct platform_device *pdev; + struct i2c_adapter adap; + int irq; + void __iomem *virtbase; + struct clk *clk; + struct nmk_i2c_controller cfg; + struct i2c_nmk_client cli; + int stop; + struct completion xfer_complete; + int result; +}; + +/* controller's abort causes */ +static const char *abort_causes[] = { + "no ack received after address transmission", + "no ack received during data phase", + "ack received after xmission of master code", + "master lost arbitration", + "slave restarts", + "slave reset", + "overflow, maxsize is 2047 bytes", +}; + +static inline void i2c_set_bit(void __iomem *reg, u32 mask) +{ + writel(readl(reg) | mask, reg); +} + +static inline void i2c_clr_bit(void __iomem *reg, u32 mask) +{ + writel(readl(reg) & ~mask, reg); +} + +/** + * flush_i2c_fifo() - This function flushes the I2C FIFO + * @dev: private data of I2C Driver + * + * This function flushes the I2C Tx and Rx FIFOs. It returns + * 0 on successful flushing of FIFO + */ +static int flush_i2c_fifo(struct nmk_i2c_dev *dev) +{ +#define LOOP_ATTEMPTS 10 + int i; + unsigned long timeout; + + /* + * flush the transmit and receive FIFO. The flushing + * operation takes several cycles before to be completed. + * On the completion, the I2C internal logic clears these + * bits, until then no one must access Tx, Rx FIFO and + * should poll on these bits waiting for the completion. + */ + writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); + + for (i = 0; i < LOOP_ATTEMPTS; i++) { + timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT_MS); + + while (!time_after(jiffies, timeout)) { + if ((readl(dev->virtbase + I2C_CR) & + (I2C_CR_FTX | I2C_CR_FRX)) == 0) + return 0; + } + } + + dev_err(&dev->pdev->dev, "flushing operation timed out " + "giving up after %d attempts", LOOP_ATTEMPTS); + + return -ETIMEDOUT; +} + +/** + * disable_all_interrupts() - Disable all interrupts of this I2c Bus + * @dev: private data of I2C Driver + */ +static void disable_all_interrupts(struct nmk_i2c_dev *dev) +{ + u32 mask = IRQ_MASK(0); + writel(mask, dev->virtbase + I2C_IMSCR); +} + +/** + * clear_all_interrupts() - Clear all interrupts of I2C Controller + * @dev: private data of I2C Driver + */ +static void clear_all_interrupts(struct nmk_i2c_dev *dev) +{ + u32 mask; + mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); + writel(mask, dev->virtbase + I2C_ICR); +} + +/** + * init_hw() - initialize the I2C hardware + * @dev: private data of I2C Driver + */ +static int init_hw(struct nmk_i2c_dev *dev) +{ + int stat; + + stat = flush_i2c_fifo(dev); + if (stat) + return stat; + + /* disable the controller */ + i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); + + disable_all_interrupts(dev); + + clear_all_interrupts(dev); + + dev->cli.operation = I2C_NO_OPERATION; + + return 0; +} + +/* enable peripheral, master mode operation */ +#define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE) + +/** + * load_i2c_mcr_reg() - load the MCR register + * @dev: private data of controller + */ +static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev) +{ + u32 mcr = 0; + + /* 7-bit address transaction */ + mcr |= GEN_MASK(1, I2C_MCR_AM, 12); + mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); + + /* start byte procedure not applied */ + mcr |= GEN_MASK(0, I2C_MCR_SB, 11); + + /* check the operation, master read/write? */ + if (dev->cli.operation == I2C_WRITE) + mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); + else + mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); + + /* stop or repeated start? */ + if (dev->stop) + mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); + else + mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); + + mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); + + return mcr; +} + +/** + * setup_i2c_controller() - setup the controller + * @dev: private data of controller + */ +static void setup_i2c_controller(struct nmk_i2c_dev *dev) +{ + u32 brcr1, brcr2; + u32 i2c_clk, div; + + writel(0x0, dev->virtbase + I2C_CR); + writel(0x0, dev->virtbase + I2C_HSMCR); + writel(0x0, dev->virtbase + I2C_TFTR); + writel(0x0, dev->virtbase + I2C_RFTR); + writel(0x0, dev->virtbase + I2C_DMAR); + + /* + * set the slsu: + * + * slsu defines the data setup time after SCL clock + * stretching in terms of i2c clk cycles. The + * needed setup time for the three modes are 250ns, + * 100ns, 10ns repectively thus leading to the values + * of 14, 6, 2 for a 48 MHz i2c clk. + */ + writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR); + + i2c_clk = clk_get_rate(dev->clk); + + /* fallback to std. mode if machine has not provided it */ + if (dev->cfg.clk_freq == 0) + dev->cfg.clk_freq = 100000; + + /* + * The spec says, in case of std. mode the divider is + * 2 whereas it is 3 for fast and fastplus mode of + * operation. TODO - high speed support. + */ + div = (dev->cfg.clk_freq > 100000) ? 3 : 2; + + /* + * generate the mask for baud rate counters. The controller + * has two baud rate counters. One is used for High speed + * operation, and the other is for std, fast mode, fast mode + * plus operation. Currently we do not supprt high speed mode + * so set brcr1 to 0. + */ + brcr1 = 0 << 16; + brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff; + + /* set the baud rate counter register */ + writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); + + /* + * set the speed mode. Currently we support + * only standard and fast mode of operation + * TODO - support for fast mode plus (upto 1Mb/s) + * and high speed (up to 3.4 Mb/s) + */ + if (dev->cfg.sm > I2C_FREQ_MODE_FAST) { + dev_err(&dev->pdev->dev, "do not support this mode " + "defaulting to std. mode\n"); + brcr2 = i2c_clk/(100000 * 2) & 0xffff; + writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); + writel(I2C_FREQ_MODE_STANDARD << 4, + dev->virtbase + I2C_CR); + } + writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR); + + /* set the Tx and Rx FIFO threshold */ + writel(dev->cfg.tft, dev->virtbase + I2C_TFTR); + writel(dev->cfg.rft, dev->virtbase + I2C_RFTR); +} + +/** + * read_i2c() - Read from I2C client device + * @dev: private data of I2C Driver + * + * This function reads from i2c client device when controller is in + * master mode. There is a completion timeout. If there is no transfer + * before timeout error is returned. + */ +static int read_i2c(struct nmk_i2c_dev *dev) +{ + u32 status = 0; + u32 mcr; + u32 irq_mask = 0; + int timeout; + + mcr = load_i2c_mcr_reg(dev); + writel(mcr, dev->virtbase + I2C_MCR); + + /* load the current CR value */ + writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, + dev->virtbase + I2C_CR); + + /* enable the controller */ + i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); + + init_completion(&dev->xfer_complete); + + /* enable interrupts by setting the mask */ + irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | + I2C_IT_MAL | I2C_IT_BERR); + + if (dev->stop) + irq_mask |= I2C_IT_MTD; + else + irq_mask |= I2C_IT_MTDWS; + + irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); + + writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, + dev->virtbase + I2C_IMSCR); + + timeout = wait_for_completion_interruptible_timeout( + &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS)); + + if (timeout < 0) { + dev_err(&dev->pdev->dev, + "wait_for_completion_interruptible_timeout" + "returned %d waiting for event\n", timeout); + status = timeout; + } + + if (timeout == 0) { + /* controler has timedout, re-init the h/w */ + dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n"); + (void) init_hw(dev); + status = -ETIMEDOUT; + } + + return status; +} + +/** + * write_i2c() - Write data to I2C client. + * @dev: private data of I2C Driver + * + * This function writes data to I2C client + */ +static int write_i2c(struct nmk_i2c_dev *dev) +{ + u32 status = 0; + u32 mcr; + u32 irq_mask = 0; + int timeout; + + mcr = load_i2c_mcr_reg(dev); + + writel(mcr, dev->virtbase + I2C_MCR); + + /* load the current CR value */ + writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, + dev->virtbase + I2C_CR); + + /* enable the controller */ + i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); + + init_completion(&dev->xfer_complete); + + /* enable interrupts by settings the masks */ + irq_mask = (I2C_IT_TXFNE | I2C_IT_TXFOVR | + I2C_IT_MAL | I2C_IT_BERR); + + /* + * check if we want to transfer a single or multiple bytes, if so + * set the MTDWS bit (Master Transaction Done Without Stop) + * to start repeated start operation + */ + if (dev->stop) + irq_mask |= I2C_IT_MTD; + else + irq_mask |= I2C_IT_MTDWS; + + irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); + + writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, + dev->virtbase + I2C_IMSCR); + + timeout = wait_for_completion_interruptible_timeout( + &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS)); + + if (timeout < 0) { + dev_err(&dev->pdev->dev, + "wait_for_completion_interruptible_timeout" + "returned %d waiting for event\n", timeout); + status = timeout; + } + + if (timeout == 0) { + /* controler has timedout, re-init the h/w */ + dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n"); + (void) init_hw(dev); + status = -ETIMEDOUT; + } + + return status; +} + +/** + * nmk_i2c_xfer() - I2C transfer function used by kernel framework + * @i2c_adap - Adapter pointer to the controller + * @msgs[] - Pointer to data to be written. + * @num_msgs - Number of messages to be executed + * + * This is the function called by the generic kernel i2c_transfer() + * or i2c_smbus...() API calls. Note that this code is protected by the + * semaphore set in the kernel i2c_transfer() function. + * + * NOTE: + * READ TRANSFER : We impose a restriction of the first message to be the + * index message for any read transaction. + * - a no index is coded as '0', + * - 2byte big endian index is coded as '3' + * !!! msg[0].buf holds the actual index. + * This is compatible with generic messages of smbus emulator + * that send a one byte index. + * eg. a I2C transation to read 2 bytes from index 0 + * idx = 0; + * msg[0].addr = client->addr; + * msg[0].flags = 0x0; + * msg[0].len = 1; + * msg[0].buf = &idx; + * + * msg[1].addr = client->addr; + * msg[1].flags = I2C_M_RD; + * msg[1].len = 2; + * msg[1].buf = rd_buff + * i2c_transfer(adap, msg, 2); + * + * WRITE TRANSFER : The I2C standard interface interprets all data as payload. + * If you want to emulate an SMBUS write transaction put the + * index as first byte(or first and second) in the payload. + * eg. a I2C transation to write 2 bytes from index 1 + * wr_buff[0] = 0x1; + * wr_buff[1] = 0x23; + * wr_buff[2] = 0x46; + * msg[0].flags = 0x0; + * msg[0].len = 3; + * msg[0].buf = wr_buff; + * i2c_transfer(adap, msg, 1); + * + * To read or write a block of data (multiple bytes) using SMBUS emulation + * please use the i2c_smbus_read_i2c_block_data() + * or i2c_smbus_write_i2c_block_data() API + */ +static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg msgs[], int num_msgs) +{ + int status; + int i; + u32 cause; + struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap); + + status = init_hw(dev); + if (status) + return status; + + /* setup the i2c controller */ + setup_i2c_controller(dev); + + for (i = 0; i < num_msgs; i++) { + if (unlikely(msgs[i].flags & I2C_M_TEN)) { + dev_err(&dev->pdev->dev, "10 bit addressing" + "not supported\n"); + return -EINVAL; + } + dev->cli.slave_adr = msgs[i].addr; + dev->cli.buffer = msgs[i].buf; + dev->cli.count = msgs[i].len; + dev->stop = (i < (num_msgs - 1)) ? 0 : 1; + dev->result = 0; + + if (msgs[i].flags & I2C_M_RD) { + /* it is a read operation */ + dev->cli.operation = I2C_READ; + status = read_i2c(dev); + } else { + /* write operation */ + dev->cli.operation = I2C_WRITE; + status = write_i2c(dev); + } + if (status || (dev->result)) { + /* get the abort cause */ + cause = (readl(dev->virtbase + I2C_SR) >> 4) & 0x7; + dev_err(&dev->pdev->dev, "error during I2C" + "message xfer: %d\n", cause); + dev_err(&dev->pdev->dev, "%s\n", + cause >= ARRAY_SIZE(abort_causes) + ? "unknown reason" : abort_causes[cause]); + return status; + } + mdelay(1); + } + /* return the no. messages processed */ + if (status) + return status; + else + return num_msgs; +} + +/** + * disable_interrupts() - disable the interrupts + * @dev: private data of controller + */ +static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) +{ + irq = IRQ_MASK(irq); + writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), + dev->virtbase + I2C_IMSCR); + return 0; +} + +/** + * i2c_irq_handler() - interrupt routine + * @irq: interrupt number + * @arg: data passed to the handler + * + * This is the interrupt handler for the i2c driver. Currently + * it handles the major interrupts like Rx & Tx FIFO management + * interrupts, master transaction interrupts, arbitration and + * bus error interrupts. The rest of the interrupts are treated as + * unhandled. + */ +static irqreturn_t i2c_irq_handler(int irq, void *arg) +{ + struct nmk_i2c_dev *dev = arg; + u32 tft, rft; + u32 count; + u32 misr; + u32 src = 0; + + /* load Tx FIFO and Rx FIFO threshold values */ + tft = readl(dev->virtbase + I2C_TFTR); + rft = readl(dev->virtbase + I2C_RFTR); + + /* read interrupt status register */ + misr = readl(dev->virtbase + I2C_MISR); + + src = __ffs(misr); + switch ((1 << src)) { + + /* Transmit FIFO nearly empty interrupt */ + case I2C_IT_TXFNE: + { + if (dev->cli.operation == I2C_READ) { + /* + * in read operation why do we care for writing? + * so disable the Transmit FIFO interrupt + */ + disable_interrupts(dev, I2C_IT_TXFNE); + } else { + for (count = (MAX_I2C_FIFO_THRESHOLD - tft - 2); + (count > 0) && + (dev->cli.count != 0); + count--) { + /* write to the Tx FIFO */ + writeb(*dev->cli.buffer, + dev->virtbase + I2C_TFR); + dev->cli.buffer++; + dev->cli.count--; + dev->cli.xfer_bytes++; + } + /* + * if done, close the transfer by disabling the + * corresponding TXFNE interrupt + */ + if (dev->cli.count == 0) + disable_interrupts(dev, I2C_IT_TXFNE); + } + } + break; + + /* + * Rx FIFO nearly full interrupt. + * This is set when the numer of entries in Rx FIFO is + * greater or equal than the threshold value programmed + * in RFT + */ + case I2C_IT_RXFNF: + for (count = rft; count > 0; count--) { + /* Read the Rx FIFO */ + *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); + dev->cli.buffer++; + } + dev->cli.count -= rft; + dev->cli.xfer_bytes += rft; + break; + + /* Rx FIFO full */ + case I2C_IT_RXFF: + for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { + *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); + dev->cli.buffer++; + } + dev->cli.count -= MAX_I2C_FIFO_THRESHOLD; + dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; + break; + + /* Master Transaction Done with/without stop */ + case I2C_IT_MTD: + case I2C_IT_MTDWS: + if (dev->cli.operation == I2C_READ) { + while (!readl(dev->virtbase + I2C_RISR) & I2C_IT_RXFE) { + if (dev->cli.count == 0) + break; + *dev->cli.buffer = + readb(dev->virtbase + I2C_RFR); + dev->cli.buffer++; + dev->cli.count--; + dev->cli.xfer_bytes++; + } + } + + i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTD); + i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTDWS); + + disable_interrupts(dev, + (I2C_IT_TXFNE | I2C_IT_TXFE | I2C_IT_TXFF + | I2C_IT_TXFOVR | I2C_IT_RXFNF + | I2C_IT_RXFF | I2C_IT_RXFE)); + + if (dev->cli.count) { + dev->result = -1; + dev_err(&dev->pdev->dev, "%lu bytes still remain to be" + "xfered\n", dev->cli.count); + (void) init_hw(dev); + } + complete(&dev->xfer_complete); + + break; + + /* Master Arbitration lost interrupt */ + case I2C_IT_MAL: + dev->result = -1; + (void) init_hw(dev); + + i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL); + complete(&dev->xfer_complete); + + break; + + /* + * Bus Error interrupt. + * This happens when an unexpected start/stop condition occurs + * during the transaction. + */ + case I2C_IT_BERR: + dev->result = -1; + /* get the status */ + if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) + (void) init_hw(dev); + + i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR); + complete(&dev->xfer_complete); + + break; + + /* + * Tx FIFO overrun interrupt. + * This is set when a write operation in Tx FIFO is performed and + * the Tx FIFO is full. + */ + case I2C_IT_TXFOVR: + dev->result = -1; + (void) init_hw(dev); + + dev_err(&dev->pdev->dev, "Tx Fifo Over run\n"); + complete(&dev->xfer_complete); + + break; + + /* unhandled interrupts by this driver - TODO*/ + case I2C_IT_TXFE: + case I2C_IT_TXFF: + case I2C_IT_RXFE: + case I2C_IT_RFSR: + case I2C_IT_RFSE: + case I2C_IT_WTSR: + case I2C_IT_STD: + dev_err(&dev->pdev->dev, "unhandled Interrupt\n"); + break; + default: + dev_err(&dev->pdev->dev, "spurious Interrupt..\n"); + break; + } + + return IRQ_HANDLED; +} + +static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C + | I2C_FUNC_SMBUS_BYTE_DATA + | I2C_FUNC_SMBUS_WORD_DATA + | I2C_FUNC_SMBUS_I2C_BLOCK; +} + +static const struct i2c_algorithm nmk_i2c_algo = { + .master_xfer = nmk_i2c_xfer, + .functionality = nmk_i2c_functionality +}; + +static int __devinit nmk_i2c_probe(struct platform_device *pdev) +{ + int ret = 0; + struct resource *res; + struct nmk_i2c_controller *pdata = + pdev->dev.platform_data; + struct nmk_i2c_dev *dev; + struct i2c_adapter *adap; + + dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); + if (!dev) { + dev_err(&pdev->dev, "cannot allocate memory\n"); + ret = -ENOMEM; + goto err_no_mem; + } + + dev->pdev = pdev; + platform_set_drvdata(pdev, dev); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -ENOENT; + goto err_no_resource; + } + + if (request_mem_region(res->start, resource_size(res), + DRIVER_NAME "I/O region") == NULL) { + ret = -EBUSY; + goto err_no_region; + } + + dev->virtbase = ioremap(res->start, resource_size(res)); + if (!dev->virtbase) { + ret = -ENOMEM; + goto err_no_ioremap; + } + + dev->irq = platform_get_irq(pdev, 0); + ret = request_irq(dev->irq, i2c_irq_handler, IRQF_DISABLED, + DRIVER_NAME, dev); + if (ret) { + dev_err(&pdev->dev, "cannot claim the irq %d\n", dev->irq); + goto err_irq; + } + + dev->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(dev->clk)) { + dev_err(&pdev->dev, "could not get i2c clock\n"); + ret = PTR_ERR(dev->clk); + goto err_no_clk; + } + + clk_enable(dev->clk); + + adap = &dev->adap; + adap->dev.parent = &pdev->dev; + adap->owner = THIS_MODULE; + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; + adap->algo = &nmk_i2c_algo; + + /* fetch the controller id */ + adap->nr = pdev->id; + + /* fetch the controller configuration from machine */ + dev->cfg.clk_freq = pdata->clk_freq; + dev->cfg.slsu = pdata->slsu; + dev->cfg.tft = pdata->tft; + dev->cfg.rft = pdata->rft; + dev->cfg.sm = pdata->sm; + + i2c_set_adapdata(adap, dev); + + ret = init_hw(dev); + if (ret != 0) { + dev_err(&pdev->dev, "error in initializing i2c hardware\n"); + goto err_init_hw; + } + + dev_dbg(&pdev->dev, "initialize I2C%d bus on virtual " + "base %p\n", pdev->id, dev->virtbase); + + ret = i2c_add_numbered_adapter(adap); + if (ret) { + dev_err(&pdev->dev, "failed to add adapter\n"); + goto err_add_adap; + } + + return 0; + + err_init_hw: + clk_disable(dev->clk); + err_add_adap: + clk_put(dev->clk); + err_no_clk: + free_irq(dev->irq, dev); + err_irq: + iounmap(dev->virtbase); + err_no_ioremap: + release_mem_region(res->start, resource_size(res)); + err_no_region: + platform_set_drvdata(pdev, NULL); + err_no_resource: + kfree(dev); + err_no_mem: + + return ret; +} + +static int __devexit nmk_i2c_remove(struct platform_device *pdev) +{ + struct nmk_i2c_dev *dev = platform_get_drvdata(pdev); + + i2c_del_adapter(&dev->adap); + flush_i2c_fifo(dev); + disable_all_interrupts(dev); + clear_all_interrupts(dev); + /* disable the controller */ + i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); + free_irq(dev->irq, dev); + iounmap(dev->virtbase); + clk_disable(dev->clk); + clk_put(dev->clk); + platform_set_drvdata(pdev, NULL); + kfree(dev); + + return 0; +} + +static struct platform_driver nmk_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = DRIVER_NAME, + }, + .probe = nmk_i2c_probe, + .remove = __devexit_p(nmk_i2c_remove), +}; + +static int __init nmk_i2c_init(void) +{ + return platform_driver_register(&nmk_i2c_driver); +} + +static void __exit nmk_i2c_exit(void) +{ + platform_driver_unregister(&nmk_i2c_driver); +} + +subsys_initcall(nmk_i2c_init); +module_exit(nmk_i2c_exit); + +MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR"); +MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRIVER_NAME); -- cgit v1.2.3 From 96eb7164e3c2f8c1b53118078e5c06f7c34c2d49 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Mon, 1 Feb 2010 15:57:25 +0100 Subject: i2c/imx: don't add probe function to the driver struct MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Having a pointer to the probe function is unnecessary when using platform_driver_probe and yields a section mismatch warning after removing the white list entry "*driver" for { .data$, .data.rel$ } -> { .init.* } mismatches in modpost. Signed-off-by: Uwe Kleine-König Signed-off-by: Ben Dooks --- drivers/i2c/busses/i2c-imx.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index 75bf820e7ccb..32375bddae7d 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -627,7 +627,6 @@ static int __exit i2c_imx_remove(struct platform_device *pdev) } static struct platform_driver i2c_imx_driver = { - .probe = i2c_imx_probe, .remove = __exit_p(i2c_imx_remove), .driver = { .name = DRIVER_NAME, -- cgit v1.2.3 From 6e56dd3d0e1e899a824c247aa72bc4250ce7668a Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Wed, 17 Feb 2010 11:19:17 +0100 Subject: i2c-mpc: use __devinit[data] for initialization functions and data "__devinit[data]" has not yet been used for all initialization functions and data. To avoid truncating lines, the struct "mpc_i2c_match_data" has been renamed to "mpc_i2c_data", which is even the better name. Signed-off-by: Wolfgang Grandegger Tested-by: Wolfram Sang Signed-off-by: Ben Dooks --- drivers/i2c/busses/i2c-mpc.c | 99 ++++++++++++++++++++------------------------ 1 file changed, 46 insertions(+), 53 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c index f627001108b8..2f74d9b6c0b9 100644 --- a/drivers/i2c/busses/i2c-mpc.c +++ b/drivers/i2c/busses/i2c-mpc.c @@ -66,7 +66,7 @@ struct mpc_i2c_divider { u16 fdr; /* including dfsrr */ }; -struct mpc_i2c_match_data { +struct mpc_i2c_data { void (*setclock)(struct device_node *node, struct mpc_i2c *i2c, u32 clock, u32 prescaler); @@ -165,7 +165,7 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing) } #ifdef CONFIG_PPC_MPC52xx -static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { +static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = { {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23}, {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02}, {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28}, @@ -186,7 +186,8 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f} }; -int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler) +static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, + int prescaler) { const struct mpc_i2c_divider *div = NULL; unsigned int pvr = mfspr(SPRN_PVR); @@ -215,9 +216,9 @@ int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler) return div ? (int)div->fdr : -EINVAL; } -static void mpc_i2c_setclock_52xx(struct device_node *node, - struct mpc_i2c *i2c, - u32 clock, u32 prescaler) +static void __devinit mpc_i2c_setclock_52xx(struct device_node *node, + struct mpc_i2c *i2c, + u32 clock, u32 prescaler) { int ret, fdr; @@ -230,15 +231,15 @@ static void mpc_i2c_setclock_52xx(struct device_node *node, dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr); } #else /* !CONFIG_PPC_MPC52xx */ -static void mpc_i2c_setclock_52xx(struct device_node *node, - struct mpc_i2c *i2c, - u32 clock, u32 prescaler) +static void __devinit mpc_i2c_setclock_52xx(struct device_node *node, + struct mpc_i2c *i2c, + u32 clock, u32 prescaler) { } #endif /* CONFIG_PPC_MPC52xx*/ #ifdef CONFIG_FSL_SOC -static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = { +static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] __devinitconst = { {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123}, {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102}, {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127}, @@ -258,7 +259,7 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = { {49152, 0x011e}, {61440, 0x011f} }; -u32 mpc_i2c_get_sec_cfg_8xxx(void) +static u32 __devinit mpc_i2c_get_sec_cfg_8xxx(void) { struct device_node *node = NULL; u32 __iomem *reg; @@ -287,7 +288,8 @@ u32 mpc_i2c_get_sec_cfg_8xxx(void) return val; } -int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler) +static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, + u32 prescaler) { const struct mpc_i2c_divider *div = NULL; u32 divider; @@ -320,9 +322,9 @@ int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler) return div ? (int)div->fdr : -EINVAL; } -static void mpc_i2c_setclock_8xxx(struct device_node *node, - struct mpc_i2c *i2c, - u32 clock, u32 prescaler) +static void __devinit mpc_i2c_setclock_8xxx(struct device_node *node, + struct mpc_i2c *i2c, + u32 clock, u32 prescaler) { int ret, fdr; @@ -338,9 +340,9 @@ static void mpc_i2c_setclock_8xxx(struct device_node *node, } #else /* !CONFIG_FSL_SOC */ -static void mpc_i2c_setclock_8xxx(struct device_node *node, - struct mpc_i2c *i2c, - u32 clock, u32 prescaler) +static void __devinit mpc_i2c_setclock_8xxx(struct device_node *node, + struct mpc_i2c *i2c, + u32 clock, u32 prescaler) { } #endif /* CONFIG_FSL_SOC */ @@ -529,8 +531,8 @@ static int __devinit fsl_i2c_probe(struct of_device *op, clock = *prop; if (match->data) { - struct mpc_i2c_match_data *data = - (struct mpc_i2c_match_data *)match->data; + struct mpc_i2c_data *data = + (struct mpc_i2c_data *)match->data; data->setclock(op->node, i2c, clock, data->prescaler); } else { /* Backwards compatibility */ @@ -582,44 +584,35 @@ static int __devexit fsl_i2c_remove(struct of_device *op) return 0; }; +static struct mpc_i2c_data mpc_i2c_data_52xx __devinitdata = { + .setclock = mpc_i2c_setclock_52xx, +}; + +static struct mpc_i2c_data mpc_i2c_data_8313 __devinitdata = { + .setclock = mpc_i2c_setclock_8xxx, +}; + +static struct mpc_i2c_data mpc_i2c_data_8543 __devinitdata = { + .setclock = mpc_i2c_setclock_8xxx, + .prescaler = 2, +}; + +static struct mpc_i2c_data mpc_i2c_data_8544 __devinitdata = { + .setclock = mpc_i2c_setclock_8xxx, + .prescaler = 3, +}; + static const struct of_device_id mpc_i2c_of_match[] = { - {.compatible = "mpc5200-i2c", - .data = &(struct mpc_i2c_match_data) { - .setclock = mpc_i2c_setclock_52xx, - }, - }, - {.compatible = "fsl,mpc5200b-i2c", - .data = &(struct mpc_i2c_match_data) { - .setclock = mpc_i2c_setclock_52xx, - }, - }, - {.compatible = "fsl,mpc5200-i2c", - .data = &(struct mpc_i2c_match_data) { - .setclock = mpc_i2c_setclock_52xx, - }, - }, - {.compatible = "fsl,mpc8313-i2c", - .data = &(struct mpc_i2c_match_data) { - .setclock = mpc_i2c_setclock_8xxx, - }, - }, - {.compatible = "fsl,mpc8543-i2c", - .data = &(struct mpc_i2c_match_data) { - .setclock = mpc_i2c_setclock_8xxx, - .prescaler = 2, - }, - }, - {.compatible = "fsl,mpc8544-i2c", - .data = &(struct mpc_i2c_match_data) { - .setclock = mpc_i2c_setclock_8xxx, - .prescaler = 3, - }, + {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, + {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, }, + {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, + {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, }, + {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, }, + {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, }, /* Backward compatibility */ - }, {.compatible = "fsl-i2c", }, {}, }; - MODULE_DEVICE_TABLE(of, mpc_i2c_of_match); -- cgit v1.2.3 From a93522116ee5aa13eeb74c0fd73d8c5d15211e64 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Wed, 17 Feb 2010 11:19:18 +0100 Subject: i2c-mpc: rename "setclock" initialization functions to "setup" To prepare support for the MPC512x processors from Freescale the "setclock" initialization functions have been renamed to "setup" because I2C interrupts must be enabled for the MPC512x by this function as well. Signed-off-by: Wolfgang Grandegger Acked-by: Wolfram Sang Signed-off-by: Ben Dooks --- drivers/i2c/busses/i2c-mpc.c | 42 ++++++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c index 2f74d9b6c0b9..370c342e5e81 100644 --- a/drivers/i2c/busses/i2c-mpc.c +++ b/drivers/i2c/busses/i2c-mpc.c @@ -67,9 +67,8 @@ struct mpc_i2c_divider { }; struct mpc_i2c_data { - void (*setclock)(struct device_node *node, - struct mpc_i2c *i2c, - u32 clock, u32 prescaler); + void (*setup)(struct device_node *node, struct mpc_i2c *i2c, + u32 clock, u32 prescaler); u32 prescaler; }; @@ -216,9 +215,9 @@ static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, return div ? (int)div->fdr : -EINVAL; } -static void __devinit mpc_i2c_setclock_52xx(struct device_node *node, - struct mpc_i2c *i2c, - u32 clock, u32 prescaler) +static void __devinit mpc_i2c_setup_52xx(struct device_node *node, + struct mpc_i2c *i2c, + u32 clock, u32 prescaler) { int ret, fdr; @@ -231,9 +230,9 @@ static void __devinit mpc_i2c_setclock_52xx(struct device_node *node, dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr); } #else /* !CONFIG_PPC_MPC52xx */ -static void __devinit mpc_i2c_setclock_52xx(struct device_node *node, - struct mpc_i2c *i2c, - u32 clock, u32 prescaler) +static void __devinit mpc_i2c_setup_52xx(struct device_node *node, + struct mpc_i2c *i2c, + u32 clock, u32 prescaler) { } #endif /* CONFIG_PPC_MPC52xx*/ @@ -322,9 +321,9 @@ static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, return div ? (int)div->fdr : -EINVAL; } -static void __devinit mpc_i2c_setclock_8xxx(struct device_node *node, - struct mpc_i2c *i2c, - u32 clock, u32 prescaler) +static void __devinit mpc_i2c_setup_8xxx(struct device_node *node, + struct mpc_i2c *i2c, + u32 clock, u32 prescaler) { int ret, fdr; @@ -340,9 +339,9 @@ static void __devinit mpc_i2c_setclock_8xxx(struct device_node *node, } #else /* !CONFIG_FSL_SOC */ -static void __devinit mpc_i2c_setclock_8xxx(struct device_node *node, - struct mpc_i2c *i2c, - u32 clock, u32 prescaler) +static void __devinit mpc_i2c_setup_8xxx(struct device_node *node, + struct mpc_i2c *i2c, + u32 clock, u32 prescaler) { } #endif /* CONFIG_FSL_SOC */ @@ -533,12 +532,11 @@ static int __devinit fsl_i2c_probe(struct of_device *op, if (match->data) { struct mpc_i2c_data *data = (struct mpc_i2c_data *)match->data; - data->setclock(op->node, i2c, clock, data->prescaler); + data->setup(op->node, i2c, clock, data->prescaler); } else { /* Backwards compatibility */ if (of_get_property(op->node, "dfsrr", NULL)) - mpc_i2c_setclock_8xxx(op->node, i2c, - clock, 0); + mpc_i2c_setup_8xxx(op->node, i2c, clock, 0); } } @@ -585,20 +583,20 @@ static int __devexit fsl_i2c_remove(struct of_device *op) }; static struct mpc_i2c_data mpc_i2c_data_52xx __devinitdata = { - .setclock = mpc_i2c_setclock_52xx, + .setup = mpc_i2c_setup_52xx, }; static struct mpc_i2c_data mpc_i2c_data_8313 __devinitdata = { - .setclock = mpc_i2c_setclock_8xxx, + .setup = mpc_i2c_setup_8xxx, }; static struct mpc_i2c_data mpc_i2c_data_8543 __devinitdata = { - .setclock = mpc_i2c_setclock_8xxx, + .setup = mpc_i2c_setup_8xxx, .prescaler = 2, }; static struct mpc_i2c_data mpc_i2c_data_8544 __devinitdata = { - .setclock = mpc_i2c_setclock_8xxx, + .setup = mpc_i2c_setup_8xxx, .prescaler = 3, }; -- cgit v1.2.3 From f00d738f04899534e2c372b2ad8b670050a945e2 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Wed, 17 Feb 2010 11:19:19 +0100 Subject: i2c-mpc: add support for the MPC512x processors from Freescale As I2C interrupts must be enabled for the MPC512x by the setup function as well, "fsl,preserve-clocking" is handled in a slighly different way. Also, the old settings are now reported calling dev_dbg(). For the MPC512x the clock setup function of the MPC52xx can be re-used. Furthermore, the Kconfig help has been updated and corrected. Signed-off-by: Wolfgang Grandegger Reviewed-by: Wolfram Sang Signed-off-by: Ben Dooks --- drivers/i2c/busses/Kconfig | 7 ++-- drivers/i2c/busses/i2c-mpc.c | 93 +++++++++++++++++++++++++++++++++++--------- 2 files changed, 78 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 10041813c6ed..ecf079b7f931 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -419,13 +419,12 @@ config I2C_IXP2000 instead. config I2C_MPC - tristate "MPC107/824x/85xx/52xx/86xx" + tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" depends on PPC32 help If you say yes to this option, support will be included for the - built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC8245 and - MPC85xx/MPC8641 family processors. The driver may also work on 52xx - family processors, though interrupts are known not to work. + built-in I2C interface on the MPC107, Tsi107, MPC512x, MPC52xx, + MPC8240, MPC8245, MPC83xx, MPC85xx and MPC8641 family processors. This driver can also be built as a module. If so, the module will be called i2c-mpc. diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c index 370c342e5e81..78a15af32942 100644 --- a/drivers/i2c/busses/i2c-mpc.c +++ b/drivers/i2c/busses/i2c-mpc.c @@ -31,6 +31,9 @@ #define DRV_NAME "mpc-i2c" +#define MPC_I2C_CLOCK_LEGACY 0 +#define MPC_I2C_CLOCK_PRESERVE (~0U) + #define MPC_I2C_FDR 0x04 #define MPC_I2C_CR 0x08 #define MPC_I2C_SR 0x0c @@ -163,7 +166,7 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing) return 0; } -#ifdef CONFIG_PPC_MPC52xx +#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x) static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = { {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23}, {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02}, @@ -193,7 +196,7 @@ static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, u32 divider; int i; - if (!clock) + if (clock == MPC_I2C_CLOCK_LEGACY) return -EINVAL; /* Determine divider value */ @@ -221,6 +224,12 @@ static void __devinit mpc_i2c_setup_52xx(struct device_node *node, { int ret, fdr; + if (clock == MPC_I2C_CLOCK_PRESERVE) { + dev_dbg(i2c->dev, "using fdr %d\n", + readb(i2c->base + MPC_I2C_FDR)); + return; + } + ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler); fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */ @@ -229,13 +238,49 @@ static void __devinit mpc_i2c_setup_52xx(struct device_node *node, if (ret >= 0) dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr); } -#else /* !CONFIG_PPC_MPC52xx */ +#else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */ static void __devinit mpc_i2c_setup_52xx(struct device_node *node, struct mpc_i2c *i2c, u32 clock, u32 prescaler) { } -#endif /* CONFIG_PPC_MPC52xx*/ +#endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */ + +#ifdef CONFIG_PPC_MPC512x +static void __devinit mpc_i2c_setup_512x(struct device_node *node, + struct mpc_i2c *i2c, + u32 clock, u32 prescaler) +{ + struct device_node *node_ctrl; + void __iomem *ctrl; + const u32 *pval; + u32 idx; + + /* Enable I2C interrupts for mpc5121 */ + node_ctrl = of_find_compatible_node(NULL, NULL, + "fsl,mpc5121-i2c-ctrl"); + if (node_ctrl) { + ctrl = of_iomap(node_ctrl, 0); + if (ctrl) { + /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */ + pval = of_get_property(node, "reg", NULL); + idx = (*pval & 0xff) / 0x20; + setbits32(ctrl, 1 << (24 + idx * 2)); + iounmap(ctrl); + } + of_node_put(node_ctrl); + } + + /* The clock setup for the 52xx works also fine for the 512x */ + mpc_i2c_setup_52xx(node, i2c, clock, prescaler); +} +#else /* CONFIG_PPC_MPC512x */ +static void __devinit mpc_i2c_setup_512x(struct device_node *node, + struct mpc_i2c *i2c, + u32 clock, u32 prescaler) +{ +} +#endif /* CONFIG_PPC_MPC512x */ #ifdef CONFIG_FSL_SOC static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] __devinitconst = { @@ -294,7 +339,7 @@ static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 divider; int i; - if (!clock) + if (clock == MPC_I2C_CLOCK_LEGACY) return -EINVAL; /* Determine proper divider value */ @@ -327,6 +372,13 @@ static void __devinit mpc_i2c_setup_8xxx(struct device_node *node, { int ret, fdr; + if (clock == MPC_I2C_CLOCK_PRESERVE) { + dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n", + readb(i2c->base + MPC_I2C_DFSRR), + readb(i2c->base + MPC_I2C_FDR)); + return; + } + ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler); fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */ @@ -495,7 +547,7 @@ static int __devinit fsl_i2c_probe(struct of_device *op, { struct mpc_i2c *i2c; const u32 *prop; - u32 clock = 0; + u32 clock = MPC_I2C_CLOCK_LEGACY; int result = 0; int plen; @@ -524,20 +576,21 @@ static int __devinit fsl_i2c_probe(struct of_device *op, } } - if (!of_get_property(op->node, "fsl,preserve-clocking", NULL)) { + if (of_get_property(op->node, "fsl,preserve-clocking", NULL)) { + clock = MPC_I2C_CLOCK_PRESERVE; + } else { prop = of_get_property(op->node, "clock-frequency", &plen); if (prop && plen == sizeof(u32)) clock = *prop; + } - if (match->data) { - struct mpc_i2c_data *data = - (struct mpc_i2c_data *)match->data; - data->setup(op->node, i2c, clock, data->prescaler); - } else { - /* Backwards compatibility */ - if (of_get_property(op->node, "dfsrr", NULL)) - mpc_i2c_setup_8xxx(op->node, i2c, clock, 0); - } + if (match->data) { + struct mpc_i2c_data *data = match->data; + data->setup(op->node, i2c, clock, data->prescaler); + } else { + /* Backwards compatibility */ + if (of_get_property(op->node, "dfsrr", NULL)) + mpc_i2c_setup_8xxx(op->node, i2c, clock, 0); } dev_set_drvdata(&op->dev, i2c); @@ -582,6 +635,10 @@ static int __devexit fsl_i2c_remove(struct of_device *op) return 0; }; +static struct mpc_i2c_data mpc_i2c_data_512x __devinitdata = { + .setup = mpc_i2c_setup_512x, +}; + static struct mpc_i2c_data mpc_i2c_data_52xx __devinitdata = { .setup = mpc_i2c_setup_52xx, }; @@ -604,6 +661,7 @@ static const struct of_device_id mpc_i2c_of_match[] = { {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, }, {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, + {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, }, {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, }, {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, }, {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, }, @@ -613,7 +671,6 @@ static const struct of_device_id mpc_i2c_of_match[] = { }; MODULE_DEVICE_TABLE(of, mpc_i2c_of_match); - /* Structure for a device driver */ static struct of_platform_driver mpc_i2c_driver = { .match_table = mpc_i2c_of_match, @@ -646,5 +703,5 @@ module_exit(fsl_i2c_exit); MODULE_AUTHOR("Adrian Cox "); MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and " - "MPC824x/85xx/52xx processors"); + "MPC824x/83xx/85xx/86xx/512x/52xx processors"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From ad0194e8d624df67a970a36e8ef9e61514e25553 Mon Sep 17 00:00:00 2001 From: Luotao Fu Date: Mon, 1 Mar 2010 13:24:24 +0100 Subject: i2c-pnx: fix setting start/stop condition The start/stop condtions are set in different places repetedly in the i2c-pnx driver. Beside in i2c_pnx_start and i2c_pnx_stop the start/stop bit are also set during the transfer of a i2c message in the master_xmit/rcv calls. This is wrong since we can't set the start/stop condition during the transaction of a single message any way. As a matter of fact, the driver will sometimes set both the start and the stop bits at one time. This can be easily reproduced by sending a simple read request like e.g struct i2c_msg msgs[] = { { addr, 0, 1, buf }, { addr, I2C_M_RD, offset, buf } }; While processing the first message the i2c_pnx_master_xmit will set both the start_bit and the stop_bit, which will eventually confuse the slave. Fixed by remove setting start/stop condition from the transmit routines. Signed-off-by: Luotao Fu Signed-off-by: Ben Dooks --- drivers/i2c/busses/i2c-pnx.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/busses/i2c-pnx.c b/drivers/i2c/busses/i2c-pnx.c index 2b0bd0b042d6..9532dee6b580 100644 --- a/drivers/i2c/busses/i2c-pnx.c +++ b/drivers/i2c/busses/i2c-pnx.c @@ -172,12 +172,6 @@ static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data) /* We still have something to talk about... */ val = *alg_data->mif.buf++; - if (alg_data->mif.len == 1) { - val |= stop_bit; - if (!alg_data->last) - val |= start_bit; - } - alg_data->mif.len--; iowrite32(val, I2C_REG_TX(alg_data)); @@ -251,11 +245,6 @@ static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data) __func__); if (alg_data->mif.len == 1) { - /* Last byte, do not acknowledge next rcv. */ - val |= stop_bit; - if (!alg_data->last) - val |= start_bit; - /* * Enable interrupt RFDAIE (data in Rx fifo), * and disable DRMIE (need data for Tx) -- cgit v1.2.3 From d84d3ea317ce0db89ce0903b4037f800c5d4c477 Mon Sep 17 00:00:00 2001 From: Cory Maccarrone Date: Sat, 12 Dec 2009 17:54:02 -0800 Subject: i2c: omap: Add support for 16-bit registers The current i2c-omap driver is set up for 32-bit registers, which corresponds to most OMAP devices. However, OMAP730/850 based devices use a 16-bit register size. This change modifies the driver to perform a runtime CPU type check to determine the register sizes, and uses a bit shift of either 1 or 2 bits to compute the proper register sizes for all registers. Signed-off-by: Cory Maccarrone Acked-by: Tony Lindgren Signed-off-by: Ben Dooks --- drivers/i2c/busses/i2c-omap.c | 44 ++++++++++++++++++++++++------------------- 1 file changed, 25 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 0037e31076ba..913abd7c172f 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -49,24 +49,24 @@ #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) #define OMAP_I2C_REV_REG 0x00 -#define OMAP_I2C_IE_REG 0x04 -#define OMAP_I2C_STAT_REG 0x08 -#define OMAP_I2C_IV_REG 0x0c +#define OMAP_I2C_IE_REG 0x01 +#define OMAP_I2C_STAT_REG 0x02 +#define OMAP_I2C_IV_REG 0x03 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ -#define OMAP_I2C_WE_REG 0x0c -#define OMAP_I2C_SYSS_REG 0x10 -#define OMAP_I2C_BUF_REG 0x14 -#define OMAP_I2C_CNT_REG 0x18 -#define OMAP_I2C_DATA_REG 0x1c -#define OMAP_I2C_SYSC_REG 0x20 -#define OMAP_I2C_CON_REG 0x24 -#define OMAP_I2C_OA_REG 0x28 -#define OMAP_I2C_SA_REG 0x2c -#define OMAP_I2C_PSC_REG 0x30 -#define OMAP_I2C_SCLL_REG 0x34 -#define OMAP_I2C_SCLH_REG 0x38 -#define OMAP_I2C_SYSTEST_REG 0x3c -#define OMAP_I2C_BUFSTAT_REG 0x40 +#define OMAP_I2C_WE_REG 0x03 +#define OMAP_I2C_SYSS_REG 0x04 +#define OMAP_I2C_BUF_REG 0x05 +#define OMAP_I2C_CNT_REG 0x06 +#define OMAP_I2C_DATA_REG 0x07 +#define OMAP_I2C_SYSC_REG 0x08 +#define OMAP_I2C_CON_REG 0x09 +#define OMAP_I2C_OA_REG 0x0a +#define OMAP_I2C_SA_REG 0x0b +#define OMAP_I2C_PSC_REG 0x0c +#define OMAP_I2C_SCLL_REG 0x0d +#define OMAP_I2C_SCLH_REG 0x0e +#define OMAP_I2C_SYSTEST_REG 0x0f +#define OMAP_I2C_BUFSTAT_REG 0x10 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ @@ -161,6 +161,7 @@ struct omap_i2c_dev { struct device *dev; void __iomem *base; /* virtual */ int irq; + int reg_shift; /* bit shift for I2C register addresses */ struct clk *iclk; /* Interface clock */ struct clk *fclk; /* Functional clock */ struct completion cmd_complete; @@ -189,12 +190,12 @@ struct omap_i2c_dev { static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, int reg, u16 val) { - __raw_writew(val, i2c_dev->base + reg); + __raw_writew(val, i2c_dev->base + (reg << i2c_dev->reg_shift)); } static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) { - return __raw_readw(i2c_dev->base + reg); + return __raw_readw(i2c_dev->base + (reg << i2c_dev->reg_shift)); } static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev) @@ -924,6 +925,11 @@ omap_i2c_probe(struct platform_device *pdev) dev->b_hw = 1; /* Enable hardware fixes */ } + if (cpu_is_omap7xx()) + dev->reg_shift = 1; + else + dev->reg_shift = 2; + /* reset ASAP, clearing any IRQs */ omap_i2c_init(dev); -- cgit v1.2.3 From e1d5b6598cdc33257fe68302ae9db81d2f7bb883 Mon Sep 17 00:00:00 2001 From: Richard Röjfors Date: Thu, 11 Feb 2010 10:42:00 +0100 Subject: i2c: Add support for Xilinx XPS IIC Bus Interface MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds support for the Xilinx XPS IIC Bus Interface. The driver uses the dynamic mode, supporting to put several I2C messages in the FIFO to reduce the number of interrupts. It has the same feature as ocores, it can be passed a list of devices that will be added when the bus is probed. Signed-off-by: Richard Röjfors Signed-off-by: Ben Dooks --- drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-xiic.c | 824 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 835 insertions(+) create mode 100644 drivers/i2c/busses/i2c-xiic.c (limited to 'drivers') diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 10041813c6ed..de04cd850353 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -582,6 +582,16 @@ config I2C_OCTEON This driver can also be built as a module. If so, the module will be called i2c-octeon. +config I2C_XILINX + tristate "Xilinx I2C Controller" + depends on EXPERIMENTAL && HAS_IOMEM + help + If you say yes to this option, support will be included for the + Xilinx I2C controller. + + This driver can also be built as a module. If so, the module + will be called xilinx_i2c. + comment "External I2C/SMBus adapter drivers" config I2C_PARPORT diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 59abcf48e6a9..097236f631e8 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o obj-$(CONFIG_I2C_STU300) += i2c-stu300.o obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o +obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c new file mode 100644 index 000000000000..eece39a5a30e --- /dev/null +++ b/drivers/i2c/busses/i2c-xiic.c @@ -0,0 +1,824 @@ +/* + * i2c-xiic.c + * Copyright (c) 2002-2007 Xilinx Inc. + * Copyright (c) 2009-2010 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * This code was implemented by Mocean Laboratories AB when porting linux + * to the automotive development board Russellville. The copyright holder + * as seen in the header is Intel corporation. + * Mocean Laboratories forked off the GNU/Linux platform work into a + * separate company called Pelagicore AB, which commited the code to the + * kernel. + */ + +/* Supports: + * Xilinx IIC + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "xiic-i2c" + +enum xilinx_i2c_state { + STATE_DONE, + STATE_ERROR, + STATE_START +}; + +/** + * struct xiic_i2c - Internal representation of the XIIC I2C bus + * @base: Memory base of the HW registers + * @wait: Wait queue for callers + * @adap: Kernel adapter representation + * @tx_msg: Messages from above to be sent + * @lock: Mutual exclusion + * @tx_pos: Current pos in TX message + * @nmsgs: Number of messages in tx_msg + * @state: See STATE_ + * @rx_msg: Current RX message + * @rx_pos: Position within current RX message + */ +struct xiic_i2c { + void __iomem *base; + wait_queue_head_t wait; + struct i2c_adapter adap; + struct i2c_msg *tx_msg; + spinlock_t lock; + unsigned int tx_pos; + unsigned int nmsgs; + enum xilinx_i2c_state state; + struct i2c_msg *rx_msg; + int rx_pos; +}; + + +#define XIIC_MSB_OFFSET 0 +#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) + +/* + * Register offsets in bytes from RegisterBase. Three is added to the + * base offset to access LSB (IBM style) of the word + */ +#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ +#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ +#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ +#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ +#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ +#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ +#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ +#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ +#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ +#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ + +/* Control Register masks */ +#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ +#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ +#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ +#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ +#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ +#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ +#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ + +/* Status Register masks */ +#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ +#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ +#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ +#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ +#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ +#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ +#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ +#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ + +/* Interrupt Status Register masks Interrupt occurs when... */ +#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ +#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ +#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ +#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ +#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ +#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ +#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ +#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ + +/* The following constants specify the depth of the FIFOs */ +#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ +#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ + +/* The following constants specify groups of interrupts that are typically + * enabled or disables at the same time + */ +#define XIIC_TX_INTERRUPTS \ +(XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) + +#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) + +/* The following constants are used with the following macros to specify the + * operation, a read or write operation. + */ +#define XIIC_READ_OPERATION 1 +#define XIIC_WRITE_OPERATION 0 + +/* + * Tx Fifo upper bit masks. + */ +#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ +#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ + +/* + * The following constants define the register offsets for the Interrupt + * registers. There are some holes in the memory map for reserved addresses + * to allow other registers to be added and still match the memory map of the + * interrupt controller registers + */ +#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ +#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ +#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ +#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ + +#define XIIC_RESET_MASK 0xAUL + +/* + * The following constant is used for the device global interrupt enable + * register, to enable all interrupts for the device, this is the only bit + * in the register + */ +#define XIIC_GINTR_ENABLE_MASK 0x80000000UL + +#define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) +#define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) + +static void xiic_start_xfer(struct xiic_i2c *i2c); +static void __xiic_start_xfer(struct xiic_i2c *i2c); + +static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) +{ + iowrite8(value, i2c->base + reg); +} + +static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) +{ + return ioread8(i2c->base + reg); +} + +static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) +{ + iowrite16(value, i2c->base + reg); +} + +static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) +{ + iowrite32(value, i2c->base + reg); +} + +static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) +{ + return ioread32(i2c->base + reg); +} + +static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) +{ + u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); + xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); +} + +static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) +{ + u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); + xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); +} + +static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) +{ + u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); + xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); +} + +static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) +{ + xiic_irq_clr(i2c, mask); + xiic_irq_en(i2c, mask); +} + +static void xiic_clear_rx_fifo(struct xiic_i2c *i2c) +{ + u8 sr; + for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); + !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); + sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) + xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); +} + +static void xiic_reinit(struct xiic_i2c *i2c) +{ + xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); + + /* Set receive Fifo depth to maximum (zero based). */ + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); + + /* Reset Tx Fifo. */ + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); + + /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); + + /* make sure RX fifo is empty */ + xiic_clear_rx_fifo(i2c); + + /* Enable interrupts */ + xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); + + xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK); +} + +static void xiic_deinit(struct xiic_i2c *i2c) +{ + u8 cr; + + xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); + + /* Disable IIC Device. */ + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); +} + +static void xiic_read_rx(struct xiic_i2c *i2c) +{ + u8 bytes_in_fifo; + int i; + + bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; + + dev_dbg(i2c->adap.dev.parent, "%s entry, bytes in fifo: %d, msg: %d" + ", SR: 0x%x, CR: 0x%x\n", + __func__, bytes_in_fifo, xiic_rx_space(i2c), + xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); + + if (bytes_in_fifo > xiic_rx_space(i2c)) + bytes_in_fifo = xiic_rx_space(i2c); + + for (i = 0; i < bytes_in_fifo; i++) + i2c->rx_msg->buf[i2c->rx_pos++] = + xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); + + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, + (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? + IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); +} + +static int xiic_tx_fifo_space(struct xiic_i2c *i2c) +{ + /* return the actual space left in the FIFO */ + return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; +} + +static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) +{ + u8 fifo_space = xiic_tx_fifo_space(i2c); + int len = xiic_tx_space(i2c); + + len = (len > fifo_space) ? fifo_space : len; + + dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", + __func__, len, fifo_space); + + while (len--) { + u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; + if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { + /* last message in transfer -> STOP */ + data |= XIIC_TX_DYN_STOP_MASK; + dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); + + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); + } else + xiic_setreg8(i2c, XIIC_DTR_REG_OFFSET, data); + } +} + +static void xiic_wakeup(struct xiic_i2c *i2c, int code) +{ + i2c->tx_msg = NULL; + i2c->rx_msg = NULL; + i2c->nmsgs = 0; + i2c->state = code; + wake_up(&i2c->wait); +} + +static void xiic_process(struct xiic_i2c *i2c) +{ + u32 pend, isr, ier; + u32 clr = 0; + + /* Get the interrupt Status from the IPIF. There is no clearing of + * interrupts in the IPIF. Interrupts must be cleared at the source. + * To find which interrupts are pending; AND interrupts pending with + * interrupts masked. + */ + isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); + ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); + pend = isr & ier; + + dev_dbg(i2c->adap.dev.parent, "%s entry, IER: 0x%x, ISR: 0x%x, " + "pend: 0x%x, SR: 0x%x, msg: %p, nmsgs: %d\n", + __func__, ier, isr, pend, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), + i2c->tx_msg, i2c->nmsgs); + + /* Do not processes a devices interrupts if the device has no + * interrupts pending + */ + if (!pend) + return; + + /* Service requesting interrupt */ + if ((pend & XIIC_INTR_ARB_LOST_MASK) || + ((pend & XIIC_INTR_TX_ERROR_MASK) && + !(pend & XIIC_INTR_RX_FULL_MASK))) { + /* bus arbritration lost, or... + * Transmit error _OR_ RX completed + * if this happens when RX_FULL is not set + * this is probably a TX error + */ + + dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); + + /* dynamic mode seem to suffer from problems if we just flushes + * fifos and the next message is a TX with len 0 (only addr) + * reset the IP instead of just flush fifos + */ + xiic_reinit(i2c); + + if (i2c->tx_msg) + xiic_wakeup(i2c, STATE_ERROR); + + } else if (pend & XIIC_INTR_RX_FULL_MASK) { + /* Receive register/FIFO is full */ + + clr = XIIC_INTR_RX_FULL_MASK; + if (!i2c->rx_msg) { + dev_dbg(i2c->adap.dev.parent, + "%s unexpexted RX IRQ\n", __func__); + xiic_clear_rx_fifo(i2c); + goto out; + } + + xiic_read_rx(i2c); + if (xiic_rx_space(i2c) == 0) { + /* this is the last part of the message */ + i2c->rx_msg = NULL; + + /* also clear TX error if there (RX complete) */ + clr |= (isr & XIIC_INTR_TX_ERROR_MASK); + + dev_dbg(i2c->adap.dev.parent, + "%s end of message, nmsgs: %d\n", + __func__, i2c->nmsgs); + + /* send next message if this wasn't the last, + * otherwise the transfer will be finialise when + * receiving the bus not busy interrupt + */ + if (i2c->nmsgs > 1) { + i2c->nmsgs--; + i2c->tx_msg++; + dev_dbg(i2c->adap.dev.parent, + "%s will start next...\n", __func__); + + __xiic_start_xfer(i2c); + } + } + } else if (pend & XIIC_INTR_BNB_MASK) { + /* IIC bus has transitioned to not busy */ + clr = XIIC_INTR_BNB_MASK; + + /* The bus is not busy, disable BusNotBusy interrupt */ + xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); + + if (!i2c->tx_msg) + goto out; + + if ((i2c->nmsgs == 1) && !i2c->rx_msg && + xiic_tx_space(i2c) == 0) + xiic_wakeup(i2c, STATE_DONE); + else + xiic_wakeup(i2c, STATE_ERROR); + + } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { + /* Transmit register/FIFO is empty or ½ empty */ + + clr = pend & + (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK); + + if (!i2c->tx_msg) { + dev_dbg(i2c->adap.dev.parent, + "%s unexpexted TX IRQ\n", __func__); + goto out; + } + + xiic_fill_tx_fifo(i2c); + + /* current message sent and there is space in the fifo */ + if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { + dev_dbg(i2c->adap.dev.parent, + "%s end of message sent, nmsgs: %d\n", + __func__, i2c->nmsgs); + if (i2c->nmsgs > 1) { + i2c->nmsgs--; + i2c->tx_msg++; + __xiic_start_xfer(i2c); + } else { + xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); + + dev_dbg(i2c->adap.dev.parent, + "%s Got TX IRQ but no more to do...\n", + __func__); + } + } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) + /* current frame is sent and is last, + * make sure to disable tx half + */ + xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); + } else { + /* got IRQ which is not acked */ + dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n", + __func__); + clr = pend; + } +out: + dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); + + xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); +} + +static int xiic_bus_busy(struct xiic_i2c *i2c) +{ + u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); + + return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; +} + +static int xiic_busy(struct xiic_i2c *i2c) +{ + int tries = 3; + int err; + + if (i2c->tx_msg) + return -EBUSY; + + /* for instance if previous transfer was terminated due to TX error + * it might be that the bus is on it's way to become available + * give it at most 3 ms to wake + */ + err = xiic_bus_busy(i2c); + while (err && tries--) { + mdelay(1); + err = xiic_bus_busy(i2c); + } + + return err; +} + +static void xiic_start_recv(struct xiic_i2c *i2c) +{ + u8 rx_watermark; + struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; + + /* Clear and enable Rx full interrupt. */ + xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); + + /* we want to get all but last byte, because the TX_ERROR IRQ is used + * to inidicate error ACK on the address, and negative ack on the last + * received byte, so to not mix them receive all but last. + * In the case where there is only one byte to receive + * we can check if ERROR and RX full is set at the same time + */ + rx_watermark = msg->len; + if (rx_watermark > IIC_RX_FIFO_DEPTH) + rx_watermark = IIC_RX_FIFO_DEPTH; + xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); + + if (!(msg->flags & I2C_M_NOSTART)) + /* write the address */ + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, + (msg->addr << 1) | XIIC_READ_OPERATION | + XIIC_TX_DYN_START_MASK); + + xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); + + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, + msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); + if (i2c->nmsgs == 1) + /* very last, enable bus not busy as well */ + xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); + + /* the message is tx:ed */ + i2c->tx_pos = msg->len; +} + +static void xiic_start_send(struct xiic_i2c *i2c) +{ + struct i2c_msg *msg = i2c->tx_msg; + + xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); + + dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d, " + "ISR: 0x%x, CR: 0x%x\n", + __func__, msg, msg->len, xiic_getreg32(i2c, XIIC_IISR_OFFSET), + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); + + if (!(msg->flags & I2C_M_NOSTART)) { + /* write the address */ + u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION | + XIIC_TX_DYN_START_MASK; + if ((i2c->nmsgs == 1) && msg->len == 0) + /* no data and last message -> add STOP */ + data |= XIIC_TX_DYN_STOP_MASK; + + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); + } + + xiic_fill_tx_fifo(i2c); + + /* Clear any pending Tx empty, Tx Error and then enable them. */ + xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | + XIIC_INTR_BNB_MASK); +} + +static irqreturn_t xiic_isr(int irq, void *dev_id) +{ + struct xiic_i2c *i2c = dev_id; + + spin_lock(&i2c->lock); + /* disable interrupts globally */ + xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0); + + dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); + + xiic_process(i2c); + + xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); + spin_unlock(&i2c->lock); + + return IRQ_HANDLED; +} + +static void __xiic_start_xfer(struct xiic_i2c *i2c) +{ + int first = 1; + int fifo_space = xiic_tx_fifo_space(i2c); + dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", + __func__, i2c->tx_msg, fifo_space); + + if (!i2c->tx_msg) + return; + + i2c->rx_pos = 0; + i2c->tx_pos = 0; + i2c->state = STATE_START; + while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) { + if (!first) { + i2c->nmsgs--; + i2c->tx_msg++; + i2c->tx_pos = 0; + } else + first = 0; + + if (i2c->tx_msg->flags & I2C_M_RD) { + /* we dont date putting several reads in the FIFO */ + xiic_start_recv(i2c); + return; + } else { + xiic_start_send(i2c); + if (xiic_tx_space(i2c) != 0) { + /* the message could not be completely sent */ + break; + } + } + + fifo_space = xiic_tx_fifo_space(i2c); + } + + /* there are more messages or the current one could not be completely + * put into the FIFO, also enable the half empty interrupt + */ + if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) + xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); + +} + +static void xiic_start_xfer(struct xiic_i2c *i2c) +{ + unsigned long flags; + + spin_lock_irqsave(&i2c->lock, flags); + xiic_reinit(i2c); + /* disable interrupts globally */ + xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0); + spin_unlock_irqrestore(&i2c->lock, flags); + + __xiic_start_xfer(i2c); + xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); +} + +static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +{ + struct xiic_i2c *i2c = i2c_get_adapdata(adap); + int err; + + dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, + xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); + + err = xiic_busy(i2c); + if (err) + return err; + + i2c->tx_msg = msgs; + i2c->nmsgs = num; + + xiic_start_xfer(i2c); + + if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || + (i2c->state == STATE_DONE), HZ)) + return (i2c->state == STATE_DONE) ? num : -EIO; + else { + i2c->tx_msg = NULL; + i2c->rx_msg = NULL; + i2c->nmsgs = 0; + return -ETIMEDOUT; + } +} + +static u32 xiic_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm xiic_algorithm = { + .master_xfer = xiic_xfer, + .functionality = xiic_func, +}; + +static struct i2c_adapter xiic_adapter = { + .owner = THIS_MODULE, + .name = DRIVER_NAME, + .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, + .algo = &xiic_algorithm, +}; + + +static int __devinit xiic_i2c_probe(struct platform_device *pdev) +{ + struct xiic_i2c *i2c; + struct xiic_i2c_platform_data *pdata; + struct resource *res; + int ret, irq; + u8 i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + goto resource_missing; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + goto resource_missing; + + pdata = (struct xiic_i2c_platform_data *) pdev->dev.platform_data; + if (!pdata) + return -EINVAL; + + i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return -ENOMEM; + + if (!request_mem_region(res->start, resource_size(res), pdev->name)) { + dev_err(&pdev->dev, "Memory region busy\n"); + ret = -EBUSY; + goto request_mem_failed; + } + + i2c->base = ioremap(res->start, resource_size(res)); + if (!i2c->base) { + dev_err(&pdev->dev, "Unable to map registers\n"); + ret = -EIO; + goto map_failed; + } + + /* hook up driver to tree */ + platform_set_drvdata(pdev, i2c); + i2c->adap = xiic_adapter; + i2c_set_adapdata(&i2c->adap, i2c); + i2c->adap.dev.parent = &pdev->dev; + + xiic_reinit(i2c); + + spin_lock_init(&i2c->lock); + init_waitqueue_head(&i2c->wait); + ret = request_irq(irq, xiic_isr, 0, pdev->name, i2c); + if (ret) { + dev_err(&pdev->dev, "Cannot claim IRQ\n"); + goto request_irq_failed; + } + + /* add i2c adapter to i2c tree */ + ret = i2c_add_adapter(&i2c->adap); + if (ret) { + dev_err(&pdev->dev, "Failed to add adapter\n"); + goto add_adapter_failed; + } + + /* add in known devices to the bus */ + for (i = 0; i < pdata->num_devices; i++) + i2c_new_device(&i2c->adap, pdata->devices + i); + + return 0; + +add_adapter_failed: + free_irq(irq, i2c); +request_irq_failed: + xiic_deinit(i2c); + iounmap(i2c->base); +map_failed: + release_mem_region(res->start, resource_size(res)); +request_mem_failed: + kfree(i2c); + + return ret; +resource_missing: + dev_err(&pdev->dev, "IRQ or Memory resource is missing\n"); + return -ENOENT; +} + +static int __devexit xiic_i2c_remove(struct platform_device* pdev) +{ + struct xiic_i2c *i2c = platform_get_drvdata(pdev); + struct resource *res; + + /* remove adapter & data */ + i2c_del_adapter(&i2c->adap); + + xiic_deinit(i2c); + + platform_set_drvdata(pdev, NULL); + + free_irq(platform_get_irq(pdev, 0), i2c); + + iounmap(i2c->base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res) + release_mem_region(res->start, resource_size(res)); + + kfree(i2c); + + return 0; +} + + +/* work with hotplug and coldplug */ +MODULE_ALIAS("platform:"DRIVER_NAME); + +static struct platform_driver xiic_i2c_driver = { + .probe = xiic_i2c_probe, + .remove = __devexit_p(xiic_i2c_remove), + .driver = { + .owner = THIS_MODULE, + .name = DRIVER_NAME, + }, +}; + +static int __init xiic_i2c_init(void) +{ + return platform_driver_register(&xiic_i2c_driver); +} + +static void __exit xiic_i2c_exit(void) +{ + platform_driver_unregister(&xiic_i2c_driver); +} + +module_init(xiic_i2c_init); +module_exit(xiic_i2c_exit); + +MODULE_AUTHOR("info@mocean-labs.com"); +MODULE_DESCRIPTION("Xilinx I2C bus driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From f9fed7cd7efaa0d050f21f6f9ed532d3143b7369 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 1 Mar 2010 18:51:42 +0000 Subject: USB: Fix s3c-hsotg build following Samsung platform header moves Fix a reference to regs-sys.h got missed in the reorganisation of the Samsung platform headers targetted for 2.6.34. Signed-off-by: Mark Brown Acked-by: Greg Kroah-Hartman Signed-off-by: Ben Dooks --- drivers/usb/gadget/s3c-hsotg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c index 4b5dbd0127f5..458f7651957d 100644 --- a/drivers/usb/gadget/s3c-hsotg.c +++ b/drivers/usb/gadget/s3c-hsotg.c @@ -30,7 +30,7 @@ #include #include -#include +#include #include #define DMA_ADDR_INVALID (~((dma_addr_t)0)) -- cgit v1.2.3 From b96b894c518bc7399e6b86b635b5e8cd7356a8e9 Mon Sep 17 00:00:00 2001 From: "Figo.zhang" Date: Fri, 5 Mar 2010 16:36:02 +0000 Subject: fix a race in ks8695_poll fix a race at the end of NAPI processing in ks8695_poll() function. Signed-off-by:Figo.zhang Signed-off-by: David S. Miller --- drivers/net/arm/ks8695net.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/arm/ks8695net.c b/drivers/net/arm/ks8695net.c index 8ca639127dbc..a1d4188c430b 100644 --- a/drivers/net/arm/ks8695net.c +++ b/drivers/net/arm/ks8695net.c @@ -575,9 +575,9 @@ static int ks8695_poll(struct napi_struct *napi, int budget) if (work_done < budget) { unsigned long flags; spin_lock_irqsave(&ksp->rx_lock, flags); + __napi_complete(napi); /*enable rx interrupt*/ writel(isr | mask_bit, KS8695_IRQ_VA + KS8695_INTEN); - __napi_complete(napi); spin_unlock_irqrestore(&ksp->rx_lock, flags); } return work_done; -- cgit v1.2.3 From ea3fb371b2a391958670f2a65e1203f7dba61671 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sat, 6 Mar 2010 01:11:38 +0000 Subject: ems_usb: cleanup: remove uneeded check "skb" is alway non-null here, but even if it were null the check isn't needed because dev_kfree_skb() can handle it. This eliminates a smatch warning about dereferencing a variable before checking that it is non-null. Signed-off-by: Dan Carpenter Signed-off-by: David S. Miller --- drivers/net/can/usb/ems_usb.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/can/usb/ems_usb.c b/drivers/net/can/usb/ems_usb.c index 11c87840cc00..33451092b8e8 100644 --- a/drivers/net/can/usb/ems_usb.c +++ b/drivers/net/can/usb/ems_usb.c @@ -876,9 +876,7 @@ static netdev_tx_t ems_usb_start_xmit(struct sk_buff *skb, struct net_device *ne return NETDEV_TX_OK; nomem: - if (skb) - dev_kfree_skb(skb); - + dev_kfree_skb(skb); stats->tx_dropped++; return NETDEV_TX_OK; -- cgit v1.2.3 From 0e2b807234c42fab59f98ec913db30dfda0e63a7 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sun, 7 Mar 2010 02:35:42 +0000 Subject: irda-usb: add error handling and fix leak If the call to kcalloc() fails then we should return -ENOMEM. Signed-off-by: Dan Carpenter Signed-off-by: David S. Miller --- drivers/net/irda/irda-usb.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/net/irda/irda-usb.c b/drivers/net/irda/irda-usb.c index e8e33bb9d876..2c9b3af16612 100644 --- a/drivers/net/irda/irda-usb.c +++ b/drivers/net/irda/irda-usb.c @@ -1651,6 +1651,8 @@ static int irda_usb_probe(struct usb_interface *intf, self->rx_urb = kcalloc(self->max_rx_urb, sizeof(struct urb *), GFP_KERNEL); + if (!self->rx_urb) + goto err_free_net; for (i = 0; i < self->max_rx_urb; i++) { self->rx_urb[i] = usb_alloc_urb(0, GFP_KERNEL); @@ -1783,6 +1785,8 @@ err_out_2: err_out_1: for (i = 0; i < self->max_rx_urb; i++) usb_free_urb(self->rx_urb[i]); + kfree(self->rx_urb); +err_free_net: free_netdev(net); err_out: return ret; -- cgit v1.2.3 From e7111eac8ebda724d1e4d9e6aaf4569744a584d5 Mon Sep 17 00:00:00 2001 From: Petko Manolov Date: Sun, 7 Mar 2010 06:10:01 +0000 Subject: another pegasus usb net device This one removes trailing whitespace in pegasus.h and more importantly adds new Pegasus compatible device. Signed-off-by: Julian Brown Signed-off-by: Petko Manolov Signed-off-by: David S. Miller --- drivers/net/usb/pegasus.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/usb/pegasus.h b/drivers/net/usb/pegasus.h index 5d02f0200737..b90d8766ab74 100644 --- a/drivers/net/usb/pegasus.h +++ b/drivers/net/usb/pegasus.h @@ -177,7 +177,7 @@ PEGASUS_DEV( "USB 10/100 Fast Ethernet", VENDOR_ABOCOM, 0x400c, PEGASUS_DEV( "USB 10/100 Fast Ethernet", VENDOR_ABOCOM, 0xabc1, DEFAULT_GPIO_RESET ) PEGASUS_DEV( "USB 10/100 Fast Ethernet", VENDOR_ABOCOM, 0x200c, - DEFAULT_GPIO_RESET | PEGASUS_II ) + DEFAULT_GPIO_RESET | PEGASUS_II ) PEGASUS_DEV( "Accton USB 10/100 Ethernet Adapter", VENDOR_ACCTON, 0x1046, DEFAULT_GPIO_RESET ) PEGASUS_DEV( "SpeedStream USB 10/100 Ethernet", VENDOR_ACCTON, 0x5046, @@ -208,6 +208,8 @@ PEGASUS_DEV( "Allied Telesyn Int. AT-USB100", VENDOR_ALLIEDTEL, 0xb100, */ PEGASUS_DEV_CLASS( "Belkin F5D5050 USB Ethernet", VENDOR_BELKIN, 0x0121, 0x00, DEFAULT_GPIO_RESET | PEGASUS_II ) +PEGASUS_DEV( "Belkin F5U122 10/100 USB Ethernet", VENDOR_BELKIN, 0x0122, + DEFAULT_GPIO_RESET | PEGASUS_II ) PEGASUS_DEV( "Billionton USB-100", VENDOR_BILLIONTON, 0x0986, DEFAULT_GPIO_RESET ) PEGASUS_DEV( "Billionton USBLP-100", VENDOR_BILLIONTON, 0x0987, @@ -249,7 +251,7 @@ PEGASUS_DEV( "GIGABYTE GN-BR402W Wireless Router", VENDOR_GIGABYTE, 0x8002, PEGASUS_DEV( "Hawking UF100 10/100 Ethernet", VENDOR_HAWKING, 0x400c, DEFAULT_GPIO_RESET | PEGASUS_II ) PEGASUS_DEV( "HP hn210c Ethernet USB", VENDOR_HP, 0x811c, - DEFAULT_GPIO_RESET | PEGASUS_II ) + DEFAULT_GPIO_RESET | PEGASUS_II ) PEGASUS_DEV( "IO DATA USB ET/TX", VENDOR_IODATA, 0x0904, DEFAULT_GPIO_RESET ) PEGASUS_DEV( "IO DATA USB ET/TX-S", VENDOR_IODATA, 0x0913, -- cgit v1.2.3 From 30765d0502905a9248e5de72fc7ac83c23422861 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sun, 7 Mar 2010 00:55:26 +0000 Subject: cpmac: fix the receiving of 802.1q frames Despite what the comment above CPMAC_SKB_SIZE says, the hardware also needs to account for the FCS length in a received frame. This patch fix the receiving of 802.1q frames which have 4 more bytes. While at it unhardcode the definition and use the one from if_vlan.h. Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller --- drivers/net/cpmac.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c index 9d489421535e..55ee055d3321 100644 --- a/drivers/net/cpmac.c +++ b/drivers/net/cpmac.c @@ -28,6 +28,7 @@ #include #include +#include #include #include #include @@ -56,8 +57,8 @@ MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable"); MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus"); #define CPMAC_VERSION "0.5.1" -/* frame size + 802.1q tag */ -#define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4) +/* frame size + 802.1q tag + FCS size */ +#define CPMAC_SKB_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) #define CPMAC_QUEUES 8 /* Ethernet registers */ -- cgit v1.2.3 From 9fba1c31f4f3f9f860a4afee0b409cde27d06741 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sun, 7 Mar 2010 00:55:47 +0000 Subject: cpmac: fallback to switch mode if no PHY chip found If we were unable to detect a PHY on any of the MDIO bus id we tried instead of bailing out with -ENODEV, assume the MAC is connected to a switch and use MDIO bus 0. This unbreaks quite a lot of devices out there whose switch cannot be detected. Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller --- drivers/net/cpmac.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c index 55ee055d3321..baeb5bab05b5 100644 --- a/drivers/net/cpmac.c +++ b/drivers/net/cpmac.c @@ -1137,8 +1137,9 @@ static int __devinit cpmac_probe(struct platform_device *pdev) } if (phy_id == PHY_MAX_ADDR) { - dev_err(&pdev->dev, "no PHY present\n"); - return -ENODEV; + dev_err(&pdev->dev, "no PHY present, falling back to switch on MDIO bus 0\n"); + strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */ + phy_id = pdev->id; } dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES); -- cgit v1.2.3 From 25dc27d17dc868aae78fd03bef3113cf586b12e5 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sun, 7 Mar 2010 00:55:50 +0000 Subject: cpmac: bump version to 0.5.2 Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller --- drivers/net/cpmac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c index baeb5bab05b5..60777fd90b33 100644 --- a/drivers/net/cpmac.c +++ b/drivers/net/cpmac.c @@ -56,7 +56,7 @@ module_param(dumb_switch, int, 0444); MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable"); MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus"); -#define CPMAC_VERSION "0.5.1" +#define CPMAC_VERSION "0.5.2" /* frame size + 802.1q tag + FCS size */ #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) #define CPMAC_QUEUES 8 -- cgit v1.2.3 From 77d3d7c1d561f49f755d7390f0764dff90765974 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Fri, 5 Feb 2010 17:57:02 +0900 Subject: driver-core: fix race condition in get_device_parent() sysfs is creating several devices in cuse class concurrently and with CONFIG_SYSFS_DEPRECATED turned off, it triggers the following oops. BUG: unable to handle kernel NULL pointer dereference at 0000000000000038 IP: [] sysfs_addrm_start+0x4a/0xf0 PGD 75bb067 PUD 75be067 PMD 0 Oops: 0000 [#1] PREEMPT SMP last sysfs file: /sys/devices/system/cpu/cpu7/topology/core_siblings CPU 1 Modules linked in: cuse fuse Pid: 4737, comm: osspd Not tainted 2.6.31-work #77 RIP: 0010:[] [] sysfs_addrm_start+0x4a/0xf0 RSP: 0018:ffff88000042f8f8 EFLAGS: 00010296 RAX: ffff88000042ffd8 RBX: 0000000000000000 RCX: 0000000000000000 RDX: 0000000000000000 RSI: ffff880007eef660 RDI: 0000000000000001 RBP: ffff88000042f918 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000001 R11: ffffffff81158b0a R12: ffff88000042f928 R13: 00000000fffffff4 R14: 0000000000000000 R15: ffff88000042f9a0 FS: 00007fe93905a950(0000) GS:ffff880008600000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b CR2: 0000000000000038 CR3: 00000000077c9000 CR4: 00000000000006e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 Process osspd (pid: 4737, threadinfo ffff88000042e000, task ffff880007eef040) Stack: ffff880005da10e8 0000000011cc8d6e ffff88000042f928 ffff880003d28a28 <0> ffff88000042f988 ffffffff811592d7 0000000000000000 0000000000000000 <0> 0000000000000000 0000000000000000 ffff88000042f958 0000000011cc8d6e Call Trace: [] create_dir+0x67/0xe0 [] sysfs_create_dir+0x58/0xb0 [] ? kobject_add_internal+0xcc/0x220 [] ? vsnprintf+0x3c1/0xb90 [] kobject_add_internal+0x107/0x220 [] kobject_add_varg+0x47/0x80 [] kobject_add+0x53/0x90 [] device_add+0xd4/0x690 [] ? dev_set_name+0x4b/0x70 [] cuse_process_init_reply+0x2b4/0x420 [cuse] ... The problem is that kobject_add_internal() first adds a kobject to the kset and then try to create sysfs directory for it. If the creation fails, it remove the kobject from the kset. get_device_parent() accesses class_dirs kset while only holding class_dirs.list_lock to see whether the cuse class dir exists. But when it exists, it may not have finished initialization yet or may fail and get removed soon. In the above case, the former happened so the second one ends up trying to create subdirectory under NULL sysfs_dirent. Fix it by grabbing a mutex in get_device_parent(). Signed-off-by: Tejun Heo Reported-by: Colin Guthrie Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/base/core.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/base/core.c b/drivers/base/core.c index 282025770429..fb4bc4f5151c 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -607,6 +607,7 @@ static struct kobject *get_device_parent(struct device *dev, int retval; if (dev->class) { + static DEFINE_MUTEX(gdp_mutex); struct kobject *kobj = NULL; struct kobject *parent_kobj; struct kobject *k; @@ -623,6 +624,8 @@ static struct kobject *get_device_parent(struct device *dev, else parent_kobj = &parent->kobj; + mutex_lock(&gdp_mutex); + /* find our class-directory at the parent and reference it */ spin_lock(&dev->class->p->class_dirs.list_lock); list_for_each_entry(k, &dev->class->p->class_dirs.list, entry) @@ -631,20 +634,26 @@ static struct kobject *get_device_parent(struct device *dev, break; } spin_unlock(&dev->class->p->class_dirs.list_lock); - if (kobj) + if (kobj) { + mutex_unlock(&gdp_mutex); return kobj; + } /* or create a new class-directory at the parent device */ k = kobject_create(); - if (!k) + if (!k) { + mutex_unlock(&gdp_mutex); return NULL; + } k->kset = &dev->class->p->class_dirs; retval = kobject_add(k, parent_kobj, "%s", dev->class->name); if (retval < 0) { + mutex_unlock(&gdp_mutex); kobject_put(k); return NULL; } /* do not emit an uevent for this simple "glue" directory */ + mutex_unlock(&gdp_mutex); return k; } -- cgit v1.2.3 From ecdf6ceb8cf4756bd4214bf9755755752b6015f5 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 29 Dec 2009 20:11:20 -0800 Subject: Driver core: add platform_create_bundle() helper Many legacy-style module create singleton platform devices themselves, along with corresponding platform driver. Instead of replicating error handling code in all such drivers, provide a helper that allocates and registers a single platform device and a driver and binds them together. Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/base/platform.c | 58 +++++++++++++++++++++++++++++++++++++++++ include/linux/platform_device.h | 5 ++++ 2 files changed, 63 insertions(+) (limited to 'drivers') diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 58efaf2f1259..937d58021d1b 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -548,6 +548,64 @@ int __init_or_module platform_driver_probe(struct platform_driver *drv, } EXPORT_SYMBOL_GPL(platform_driver_probe); +/** + * platform_create_bundle - register driver and create corresponding device + * @driver: platform driver structure + * @probe: the driver probe routine, probably from an __init section + * @res: set of resources that needs to be allocated for the device + * @n_res: number of resources + * @data: platform specific data for this platform device + * @size: size of platform specific data + * + * Use this in legacy-style modules that probe hardware directly and + * register a single platform device and corresponding platform driver. + */ +struct platform_device * __init_or_module platform_create_bundle( + struct platform_driver *driver, + int (*probe)(struct platform_device *), + struct resource *res, unsigned int n_res, + const void *data, size_t size) +{ + struct platform_device *pdev; + int error; + + pdev = platform_device_alloc(driver->driver.name, -1); + if (!pdev) { + error = -ENOMEM; + goto err_out; + } + + if (res) { + error = platform_device_add_resources(pdev, res, n_res); + if (error) + goto err_pdev_put; + } + + if (data) { + error = platform_device_add_data(pdev, data, size); + if (error) + goto err_pdev_put; + } + + error = platform_device_add(pdev); + if (error) + goto err_pdev_put; + + error = platform_driver_probe(driver, probe); + if (error) + goto err_pdev_del; + + return pdev; + +err_pdev_del: + platform_device_del(pdev); +err_pdev_put: + platform_device_put(pdev); +err_out: + return ERR_PTR(error); +} +EXPORT_SYMBOL_GPL(platform_create_bundle); + /* modalias support enables more hands-off userspace setup: * (a) environment variable lets new-style hotplug events work once system is * fully running: "modprobe $MODALIAS" diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index 71ff887ca44e..25e64b43e644 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -77,6 +77,11 @@ extern int platform_driver_probe(struct platform_driver *driver, #define platform_get_drvdata(_dev) dev_get_drvdata(&(_dev)->dev) #define platform_set_drvdata(_dev,data) dev_set_drvdata(&(_dev)->dev, (data)) +extern struct platform_device *platform_create_bundle(struct platform_driver *driver, + int (*probe)(struct platform_device *), + struct resource *res, unsigned int n_res, + const void *data, size_t size); + /* early platform driver interface */ struct early_platform_driver { const char *class_str; -- cgit v1.2.3 From c9be0a36f9bf392a7984473124a67a12964df11f Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Tue, 5 Jan 2010 12:47:58 +0100 Subject: sysdev: Pass attribute in sysdev_class attributes show/store Passing the attribute to the low level IO functions allows all kinds of cleanups, by sharing low level IO code without requiring an own function for every piece of data. Also drivers can extend the attributes with own data fields and use that in the low level function. Similar to sysdev_attributes and normal attributes. This is a tree-wide sweep, converting everything in one go. No functional changes in this patch other than passing the new argument everywhere. Tested on x86, the non x86 parts are uncompiled. Signed-off-by: Andi Kleen Signed-off-by: Greg Kroah-Hartman --- arch/mips/txx9/generic/7segled.c | 5 +++- arch/s390/kernel/smp.c | 8 +++++-- arch/s390/kernel/time.c | 49 ++++++++++++++++++++++++++++++---------- drivers/base/cpu.c | 9 +++++--- drivers/base/node.c | 17 ++++++++++---- drivers/base/sys.c | 4 ++-- drivers/cpuidle/sysfs.c | 4 ++++ include/linux/sysdev.h | 6 +++-- kernel/perf_event.c | 13 ++++++++--- kernel/sched.c | 4 ++++ 10 files changed, 89 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/arch/mips/txx9/generic/7segled.c b/arch/mips/txx9/generic/7segled.c index 727ab21b6618..7f8416f86222 100644 --- a/arch/mips/txx9/generic/7segled.c +++ b/arch/mips/txx9/generic/7segled.c @@ -58,13 +58,16 @@ static ssize_t raw_store(struct sys_device *dev, static SYSDEV_ATTR(ascii, 0200, NULL, ascii_store); static SYSDEV_ATTR(raw, 0200, NULL, raw_store); -static ssize_t map_seg7_show(struct sysdev_class *class, char *buf) +static ssize_t map_seg7_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { memcpy(buf, &txx9_seg7map, sizeof(txx9_seg7map)); return sizeof(txx9_seg7map); } static ssize_t map_seg7_store(struct sysdev_class *class, + struct sysdev_class_attribute *attr, const char *buf, size_t size) { if (size != sizeof(txx9_seg7map)) diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index 8b10127c00ad..e2121099f03b 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -1020,7 +1020,9 @@ out: return rc; } -static ssize_t __ref rescan_store(struct sysdev_class *class, const char *buf, +static ssize_t __ref rescan_store(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + const char *buf, size_t count) { int rc; @@ -1041,7 +1043,9 @@ static ssize_t dispatching_show(struct sysdev_class *class, char *buf) return count; } -static ssize_t dispatching_store(struct sysdev_class *dev, const char *buf, +static ssize_t dispatching_store(struct sysdev_class *dev, + struct sysdev_class_attribute *attr, + const char *buf, size_t count) { int val, rc; diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c index a8f93f1705ad..75894c281710 100644 --- a/arch/s390/kernel/time.c +++ b/arch/s390/kernel/time.c @@ -1116,14 +1116,18 @@ static struct sys_device etr_port1_dev = { /* * ETR class attributes */ -static ssize_t etr_stepping_port_show(struct sysdev_class *class, char *buf) +static ssize_t etr_stepping_port_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { return sprintf(buf, "%i\n", etr_port0.esw.p); } static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL); -static ssize_t etr_stepping_mode_show(struct sysdev_class *class, char *buf) +static ssize_t etr_stepping_mode_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { char *mode_str; @@ -1584,7 +1588,9 @@ static struct sysdev_class stp_sysclass = { .name = "stp", }; -static ssize_t stp_ctn_id_show(struct sysdev_class *class, char *buf) +static ssize_t stp_ctn_id_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { if (!stp_online) return -ENODATA; @@ -1594,7 +1600,9 @@ static ssize_t stp_ctn_id_show(struct sysdev_class *class, char *buf) static SYSDEV_CLASS_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL); -static ssize_t stp_ctn_type_show(struct sysdev_class *class, char *buf) +static ssize_t stp_ctn_type_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { if (!stp_online) return -ENODATA; @@ -1603,7 +1611,9 @@ static ssize_t stp_ctn_type_show(struct sysdev_class *class, char *buf) static SYSDEV_CLASS_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL); -static ssize_t stp_dst_offset_show(struct sysdev_class *class, char *buf) +static ssize_t stp_dst_offset_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { if (!stp_online || !(stp_info.vbits & 0x2000)) return -ENODATA; @@ -1612,7 +1622,9 @@ static ssize_t stp_dst_offset_show(struct sysdev_class *class, char *buf) static SYSDEV_CLASS_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL); -static ssize_t stp_leap_seconds_show(struct sysdev_class *class, char *buf) +static ssize_t stp_leap_seconds_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { if (!stp_online || !(stp_info.vbits & 0x8000)) return -ENODATA; @@ -1621,7 +1633,9 @@ static ssize_t stp_leap_seconds_show(struct sysdev_class *class, char *buf) static SYSDEV_CLASS_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL); -static ssize_t stp_stratum_show(struct sysdev_class *class, char *buf) +static ssize_t stp_stratum_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { if (!stp_online) return -ENODATA; @@ -1630,7 +1644,9 @@ static ssize_t stp_stratum_show(struct sysdev_class *class, char *buf) static SYSDEV_CLASS_ATTR(stratum, 0400, stp_stratum_show, NULL); -static ssize_t stp_time_offset_show(struct sysdev_class *class, char *buf) +static ssize_t stp_time_offset_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { if (!stp_online || !(stp_info.vbits & 0x0800)) return -ENODATA; @@ -1639,7 +1655,9 @@ static ssize_t stp_time_offset_show(struct sysdev_class *class, char *buf) static SYSDEV_CLASS_ATTR(time_offset, 0400, stp_time_offset_show, NULL); -static ssize_t stp_time_zone_offset_show(struct sysdev_class *class, char *buf) +static ssize_t stp_time_zone_offset_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { if (!stp_online || !(stp_info.vbits & 0x4000)) return -ENODATA; @@ -1649,7 +1667,9 @@ static ssize_t stp_time_zone_offset_show(struct sysdev_class *class, char *buf) static SYSDEV_CLASS_ATTR(time_zone_offset, 0400, stp_time_zone_offset_show, NULL); -static ssize_t stp_timing_mode_show(struct sysdev_class *class, char *buf) +static ssize_t stp_timing_mode_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { if (!stp_online) return -ENODATA; @@ -1658,7 +1678,9 @@ static ssize_t stp_timing_mode_show(struct sysdev_class *class, char *buf) static SYSDEV_CLASS_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL); -static ssize_t stp_timing_state_show(struct sysdev_class *class, char *buf) +static ssize_t stp_timing_state_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { if (!stp_online) return -ENODATA; @@ -1667,12 +1689,15 @@ static ssize_t stp_timing_state_show(struct sysdev_class *class, char *buf) static SYSDEV_CLASS_ATTR(timing_state, 0400, stp_timing_state_show, NULL); -static ssize_t stp_online_show(struct sysdev_class *class, char *buf) +static ssize_t stp_online_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { return sprintf(buf, "%i\n", stp_online); } static ssize_t stp_online_store(struct sysdev_class *class, + struct sysdev_class_attribute *attr, const char *buf, size_t count) { unsigned int value; diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c index 958bd1540c30..fd1b2f9b7b8f 100644 --- a/drivers/base/cpu.c +++ b/drivers/base/cpu.c @@ -151,7 +151,8 @@ static ssize_t print_cpus_map(char *buf, const struct cpumask *map) } #define print_cpus_func(type) \ -static ssize_t print_cpus_##type(struct sysdev_class *class, char *buf) \ +static ssize_t print_cpus_##type(struct sysdev_class *class, \ + struct sysdev_class_attribute *attr, char *buf) \ { \ return print_cpus_map(buf, cpu_##type##_mask); \ } \ @@ -165,7 +166,8 @@ print_cpus_func(present); /* * Print values for NR_CPUS and offlined cpus */ -static ssize_t print_cpus_kernel_max(struct sysdev_class *class, char *buf) +static ssize_t print_cpus_kernel_max(struct sysdev_class *class, + struct sysdev_class_attribute *attr, char *buf) { int n = snprintf(buf, PAGE_SIZE-2, "%d\n", NR_CPUS - 1); return n; @@ -175,7 +177,8 @@ static SYSDEV_CLASS_ATTR(kernel_max, 0444, print_cpus_kernel_max, NULL); /* arch-optional setting to enable display of offline cpus >= nr_cpu_ids */ unsigned int total_cpus; -static ssize_t print_cpus_offline(struct sysdev_class *class, char *buf) +static ssize_t print_cpus_offline(struct sysdev_class *class, + struct sysdev_class_attribute *attr, char *buf) { int n = 0, len = PAGE_SIZE-2; cpumask_var_t offline; diff --git a/drivers/base/node.c b/drivers/base/node.c index 70122791683d..85c9d30d7004 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -544,23 +544,29 @@ static ssize_t print_nodes_state(enum node_states state, char *buf) return n; } -static ssize_t print_nodes_possible(struct sysdev_class *class, char *buf) +static ssize_t print_nodes_possible(struct sysdev_class *class, + struct sysdev_class_attribute *attr, char *buf) { return print_nodes_state(N_POSSIBLE, buf); } -static ssize_t print_nodes_online(struct sysdev_class *class, char *buf) +static ssize_t print_nodes_online(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { return print_nodes_state(N_ONLINE, buf); } static ssize_t print_nodes_has_normal_memory(struct sysdev_class *class, - char *buf) + struct sysdev_class_attribute *attr, + char *buf) { return print_nodes_state(N_NORMAL_MEMORY, buf); } -static ssize_t print_nodes_has_cpu(struct sysdev_class *class, char *buf) +static ssize_t print_nodes_has_cpu(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { return print_nodes_state(N_CPU, buf); } @@ -573,7 +579,8 @@ static SYSDEV_CLASS_ATTR(has_cpu, 0444, print_nodes_has_cpu, NULL); #ifdef CONFIG_HIGHMEM static ssize_t print_nodes_has_high_memory(struct sysdev_class *class, - char *buf) + struct sysdev_class_attribute *attr, + char *buf) { return print_nodes_state(N_HIGH_MEMORY, buf); } diff --git a/drivers/base/sys.c b/drivers/base/sys.c index 0d903909af7e..a38445c0f8c5 100644 --- a/drivers/base/sys.c +++ b/drivers/base/sys.c @@ -89,7 +89,7 @@ static ssize_t sysdev_class_show(struct kobject *kobj, struct attribute *attr, struct sysdev_class_attribute *class_attr = to_sysdev_class_attr(attr); if (class_attr->show) - return class_attr->show(class, buffer); + return class_attr->show(class, class_attr, buffer); return -EIO; } @@ -100,7 +100,7 @@ static ssize_t sysdev_class_store(struct kobject *kobj, struct attribute *attr, struct sysdev_class_attribute *class_attr = to_sysdev_class_attr(attr); if (class_attr->store) - return class_attr->store(class, buffer, count); + return class_attr->store(class, class_attr, buffer, count); return -EIO; } diff --git a/drivers/cpuidle/sysfs.c b/drivers/cpuidle/sysfs.c index 97b003839fb6..c9cefacabf37 100644 --- a/drivers/cpuidle/sysfs.c +++ b/drivers/cpuidle/sysfs.c @@ -22,6 +22,7 @@ static int __init cpuidle_sysfs_setup(char *unused) __setup("cpuidle_sysfs_switch", cpuidle_sysfs_setup); static ssize_t show_available_governors(struct sysdev_class *class, + struct sysdev_class_attribute *attr, char *buf) { ssize_t i = 0; @@ -41,6 +42,7 @@ out: } static ssize_t show_current_driver(struct sysdev_class *class, + struct sysdev_class_attribute *attr, char *buf) { ssize_t ret; @@ -56,6 +58,7 @@ static ssize_t show_current_driver(struct sysdev_class *class, } static ssize_t show_current_governor(struct sysdev_class *class, + struct sysdev_class_attribute *attr, char *buf) { ssize_t ret; @@ -71,6 +74,7 @@ static ssize_t show_current_governor(struct sysdev_class *class, } static ssize_t store_current_governor(struct sysdev_class *class, + struct sysdev_class_attribute *attr, const char *buf, size_t count) { char gov_name[CPUIDLE_NAME_LEN]; diff --git a/include/linux/sysdev.h b/include/linux/sysdev.h index f395bb3fa2f2..c2458fa8376c 100644 --- a/include/linux/sysdev.h +++ b/include/linux/sysdev.h @@ -41,8 +41,10 @@ struct sysdev_class { struct sysdev_class_attribute { struct attribute attr; - ssize_t (*show)(struct sysdev_class *, char *); - ssize_t (*store)(struct sysdev_class *, const char *, size_t); + ssize_t (*show)(struct sysdev_class *, struct sysdev_class_attribute *, + char *); + ssize_t (*store)(struct sysdev_class *, struct sysdev_class_attribute *, + const char *, size_t); }; #define _SYSDEV_CLASS_ATTR(_name,_mode,_show,_store) \ diff --git a/kernel/perf_event.c b/kernel/perf_event.c index 8e352c756ba7..f40560b86544 100644 --- a/kernel/perf_event.c +++ b/kernel/perf_event.c @@ -5481,13 +5481,16 @@ void __init perf_event_init(void) register_cpu_notifier(&perf_cpu_nb); } -static ssize_t perf_show_reserve_percpu(struct sysdev_class *class, char *buf) +static ssize_t perf_show_reserve_percpu(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { return sprintf(buf, "%d\n", perf_reserved_percpu); } static ssize_t perf_set_reserve_percpu(struct sysdev_class *class, + struct sysdev_class_attribute *attr, const char *buf, size_t count) { @@ -5516,13 +5519,17 @@ perf_set_reserve_percpu(struct sysdev_class *class, return count; } -static ssize_t perf_show_overcommit(struct sysdev_class *class, char *buf) +static ssize_t perf_show_overcommit(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { return sprintf(buf, "%d\n", perf_overcommit); } static ssize_t -perf_set_overcommit(struct sysdev_class *class, const char *buf, size_t count) +perf_set_overcommit(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + const char *buf, size_t count) { unsigned long val; int err; diff --git a/kernel/sched.c b/kernel/sched.c index b47ceeec1a91..150b6988de49 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -7406,11 +7406,13 @@ static ssize_t sched_power_savings_store(const char *buf, size_t count, int smt) #ifdef CONFIG_SCHED_MC static ssize_t sched_mc_power_savings_show(struct sysdev_class *class, + struct sysdev_class_attribute *attr, char *page) { return sprintf(page, "%u\n", sched_mc_power_savings); } static ssize_t sched_mc_power_savings_store(struct sysdev_class *class, + struct sysdev_class_attribute *attr, const char *buf, size_t count) { return sched_power_savings_store(buf, count, 0); @@ -7422,11 +7424,13 @@ static SYSDEV_CLASS_ATTR(sched_mc_power_savings, 0644, #ifdef CONFIG_SCHED_SMT static ssize_t sched_smt_power_savings_show(struct sysdev_class *dev, + struct sysdev_class_attribute *attr, char *page) { return sprintf(page, "%u\n", sched_smt_power_savings); } static ssize_t sched_smt_power_savings_store(struct sysdev_class *dev, + struct sysdev_class_attribute *attr, const char *buf, size_t count) { return sched_power_savings_store(buf, count, 1); -- cgit v1.2.3 From b15f562fc2f5429f27e5dfb0b0ee5ec44f661986 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Tue, 5 Jan 2010 12:47:59 +0100 Subject: sysdev: Convert node driver class attributes to be data driven Using the new attribute argument convert the node driver class attributes to carry the node state. Then use a shared function to do what a lot of individual functions did before. Signed-off-by: Andi Kleen Signed-off-by: Greg Kroah-Hartman --- drivers/base/node.c | 65 +++++++++++++++-------------------------------------- 1 file changed, 18 insertions(+), 47 deletions(-) (limited to 'drivers') diff --git a/drivers/base/node.c b/drivers/base/node.c index 85c9d30d7004..aa8bc4bff4f6 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -544,59 +544,29 @@ static ssize_t print_nodes_state(enum node_states state, char *buf) return n; } -static ssize_t print_nodes_possible(struct sysdev_class *class, - struct sysdev_class_attribute *attr, char *buf) -{ - return print_nodes_state(N_POSSIBLE, buf); -} - -static ssize_t print_nodes_online(struct sysdev_class *class, - struct sysdev_class_attribute *attr, - char *buf) -{ - return print_nodes_state(N_ONLINE, buf); -} - -static ssize_t print_nodes_has_normal_memory(struct sysdev_class *class, - struct sysdev_class_attribute *attr, - char *buf) -{ - return print_nodes_state(N_NORMAL_MEMORY, buf); -} - -static ssize_t print_nodes_has_cpu(struct sysdev_class *class, - struct sysdev_class_attribute *attr, - char *buf) -{ - return print_nodes_state(N_CPU, buf); -} - -static SYSDEV_CLASS_ATTR(possible, 0444, print_nodes_possible, NULL); -static SYSDEV_CLASS_ATTR(online, 0444, print_nodes_online, NULL); -static SYSDEV_CLASS_ATTR(has_normal_memory, 0444, print_nodes_has_normal_memory, - NULL); -static SYSDEV_CLASS_ATTR(has_cpu, 0444, print_nodes_has_cpu, NULL); +struct node_attr { + struct sysdev_class_attribute attr; + enum node_states state; +}; -#ifdef CONFIG_HIGHMEM -static ssize_t print_nodes_has_high_memory(struct sysdev_class *class, - struct sysdev_class_attribute *attr, - char *buf) +static ssize_t show_node_state(struct sysdev_class *class, + struct sysdev_class_attribute *attr, char *buf) { - return print_nodes_state(N_HIGH_MEMORY, buf); + struct node_attr *na = container_of(attr, struct node_attr, attr); + return print_nodes_state(na->state, buf); } -static SYSDEV_CLASS_ATTR(has_high_memory, 0444, print_nodes_has_high_memory, - NULL); -#endif +#define _NODE_ATTR(name, state) \ + { _SYSDEV_CLASS_ATTR(name, 0444, show_node_state, NULL), state } -struct sysdev_class_attribute *node_state_attr[] = { - &attr_possible, - &attr_online, - &attr_has_normal_memory, +static struct node_attr node_state_attr[] = { + _NODE_ATTR(possible, N_POSSIBLE), + _NODE_ATTR(online, N_ONLINE), + _NODE_ATTR(has_normal_memory, N_NORMAL_MEMORY), + _NODE_ATTR(has_cpu, N_CPU), #ifdef CONFIG_HIGHMEM - &attr_has_high_memory, + _NODE_ATTR(has_high_memory, N_HIGH_MEMORY), #endif - &attr_has_cpu, }; static int node_states_init(void) @@ -604,9 +574,10 @@ static int node_states_init(void) int i; int err = 0; + BUILD_BUG_ON(ARRAY_SIZE(node_state_attr) != NR_NODE_STATES); for (i = 0; i < NR_NODE_STATES; i++) { int ret; - ret = sysdev_class_create_file(&node_class, node_state_attr[i]); + ret = sysdev_class_create_file(&node_class, &node_state_attr[i].attr); if (!err) err = ret; } -- cgit v1.2.3 From 265d2e2e31c5f6dc1b20ae1653a17fdba706f79e Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Tue, 5 Jan 2010 12:48:00 +0100 Subject: sysdev: Convert cpu driver sysdev class attributes Using the new attribute argument convert the cpu driver class attributes to carry the node state. Then use a shared function to do what a lot of individual functions did before. This eliminates an ugly macro. Signed-off-by: Andi Kleen Signed-off-by: Greg Kroah-Hartman --- drivers/base/cpu.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c index fd1b2f9b7b8f..b04ecfc63b51 100644 --- a/drivers/base/cpu.c +++ b/drivers/base/cpu.c @@ -141,27 +141,32 @@ static SYSDEV_ATTR(crash_notes, 0400, show_crash_notes, NULL); /* * Print cpu online, possible, present, and system maps */ -static ssize_t print_cpus_map(char *buf, const struct cpumask *map) + +struct cpu_attr { + struct sysdev_class_attribute attr; + const struct cpumask *const * const map; +}; + +static ssize_t show_cpus_attr(struct sysdev_class *class, + struct sysdev_class_attribute *attr, + char *buf) { - int n = cpulist_scnprintf(buf, PAGE_SIZE-2, map); + struct cpu_attr *ca = container_of(attr, struct cpu_attr, attr); + int n = cpulist_scnprintf(buf, PAGE_SIZE-2, *(ca->map)); buf[n++] = '\n'; buf[n] = '\0'; return n; } -#define print_cpus_func(type) \ -static ssize_t print_cpus_##type(struct sysdev_class *class, \ - struct sysdev_class_attribute *attr, char *buf) \ -{ \ - return print_cpus_map(buf, cpu_##type##_mask); \ -} \ -static struct sysdev_class_attribute attr_##type##_map = \ - _SYSDEV_CLASS_ATTR(type, 0444, print_cpus_##type, NULL) +#define _CPU_ATTR(name, map) \ + { _SYSDEV_CLASS_ATTR(name, 0444, show_cpus_attr, NULL), map } -print_cpus_func(online); -print_cpus_func(possible); -print_cpus_func(present); +static struct cpu_attr cpu_attrs[] = { + _CPU_ATTR(online, &cpu_online_mask), + _CPU_ATTR(possible, &cpu_possible_mask), + _CPU_ATTR(present, &cpu_present_mask), +}; /* * Print values for NR_CPUS and offlined cpus @@ -208,9 +213,9 @@ static ssize_t print_cpus_offline(struct sysdev_class *class, static SYSDEV_CLASS_ATTR(offline, 0444, print_cpus_offline, NULL); static struct sysdev_class_attribute *cpu_state_attr[] = { - &attr_online_map, - &attr_possible_map, - &attr_present_map, + &cpu_attrs[0].attr, + &cpu_attrs[1].attr, + &cpu_attrs[2].attr, &attr_kernel_max, &attr_offline, }; -- cgit v1.2.3 From 38457ab3a0d36320370c715145ba6da514127194 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Tue, 5 Jan 2010 12:48:02 +0100 Subject: sysfs: Add attribute array to sysdev classes Add a attribute array that is automatically registered and unregistered to struct sysdev_class. This is similar to what struct class has. A lot of drivers add list of attributes, so it's better to do this easily in the common sysdev layer. This adds a new field to struct sysdev_class. I audited the whole tree and there are no dynamically allocated sysdev classes, so this is fully compatible. Signed-off-by: Andi Kleen Signed-off-by: Greg Kroah-Hartman --- drivers/base/sys.c | 9 ++++++++- include/linux/sysdev.h | 2 ++ 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/base/sys.c b/drivers/base/sys.c index a38445c0f8c5..747c99e0568b 100644 --- a/drivers/base/sys.c +++ b/drivers/base/sys.c @@ -145,13 +145,20 @@ int sysdev_class_register(struct sysdev_class *cls) if (retval) return retval; - return kset_register(&cls->kset); + retval = kset_register(&cls->kset); + if (!retval && cls->attrs) + retval = sysfs_create_files(&cls->kset.kobj, + (const struct attribute **)cls->attrs); + return retval; } void sysdev_class_unregister(struct sysdev_class *cls) { pr_debug("Unregistering sysdev class '%s'\n", kobject_name(&cls->kset.kobj)); + if (cls->attrs) + sysfs_remove_files(&cls->kset.kobj, + (const struct attribute **)cls->attrs); kset_unregister(&cls->kset); } diff --git a/include/linux/sysdev.h b/include/linux/sysdev.h index c2458fa8376c..b6244f9b533f 100644 --- a/include/linux/sysdev.h +++ b/include/linux/sysdev.h @@ -27,10 +27,12 @@ struct sys_device; +struct sysdev_class_attribute; struct sysdev_class { const char *name; struct list_head drivers; + struct sysdev_class_attribute **attrs; /* Default operations for these types of devices */ int (*shutdown)(struct sys_device *); -- cgit v1.2.3 From e1a7e29a266ba3313a873d302b352521403bd155 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Tue, 5 Jan 2010 12:48:03 +0100 Subject: sysdev: Convert node driver Use sysdev_class attribute arrays in node driver Convert the node driver to sysdev_class attribute arrays. This greatly cleans up the code and remove a lot of code. Signed-off-by: Andi Kleen Signed-off-by: Greg Kroah-Hartman --- drivers/base/cpu.c | 57 ++++++++++++++++-------------------------------------- 1 file changed, 17 insertions(+), 40 deletions(-) (limited to 'drivers') diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c index b04ecfc63b51..fb456b729803 100644 --- a/drivers/base/cpu.c +++ b/drivers/base/cpu.c @@ -13,8 +13,11 @@ #include "base.h" +static struct sysdev_class_attribute *cpu_sysdev_class_attrs[]; + struct sysdev_class cpu_sysdev_class = { .name = "cpu", + .attrs = cpu_sysdev_class_attrs, }; EXPORT_SYMBOL(cpu_sysdev_class); @@ -90,20 +93,6 @@ static ssize_t cpu_release_store(struct class *class, const char *buf, static CLASS_ATTR(probe, S_IWUSR, NULL, cpu_probe_store); static CLASS_ATTR(release, S_IWUSR, NULL, cpu_release_store); - -int __init cpu_probe_release_init(void) -{ - int rc; - - rc = sysfs_create_file(&cpu_sysdev_class.kset.kobj, - &class_attr_probe.attr); - if (!rc) - rc = sysfs_create_file(&cpu_sysdev_class.kset.kobj, - &class_attr_release.attr); - - return rc; -} -device_initcall(cpu_probe_release_init); #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */ #else /* ... !CONFIG_HOTPLUG_CPU */ @@ -162,6 +151,7 @@ static ssize_t show_cpus_attr(struct sysdev_class *class, #define _CPU_ATTR(name, map) \ { _SYSDEV_CLASS_ATTR(name, 0444, show_cpus_attr, NULL), map } +/* Keep in sync with cpu_sysdev_class_attrs */ static struct cpu_attr cpu_attrs[] = { _CPU_ATTR(online, &cpu_online_mask), _CPU_ATTR(possible, &cpu_possible_mask), @@ -212,29 +202,6 @@ static ssize_t print_cpus_offline(struct sysdev_class *class, } static SYSDEV_CLASS_ATTR(offline, 0444, print_cpus_offline, NULL); -static struct sysdev_class_attribute *cpu_state_attr[] = { - &cpu_attrs[0].attr, - &cpu_attrs[1].attr, - &cpu_attrs[2].attr, - &attr_kernel_max, - &attr_offline, -}; - -static int cpu_states_init(void) -{ - int i; - int err = 0; - - for (i = 0; i < ARRAY_SIZE(cpu_state_attr); i++) { - int ret; - ret = sysdev_class_create_file(&cpu_sysdev_class, - cpu_state_attr[i]); - if (!err) - err = ret; - } - return err; -} - /* * register_cpu - Setup a sysfs device for a CPU. * @cpu - cpu->hotpluggable field set to 1 will generate a control file in @@ -280,9 +247,6 @@ int __init cpu_dev_init(void) int err; err = sysdev_class_register(&cpu_sysdev_class); - if (!err) - err = cpu_states_init(); - #if defined(CONFIG_SCHED_MC) || defined(CONFIG_SCHED_SMT) if (!err) err = sched_create_sysfs_power_savings_entries(&cpu_sysdev_class); @@ -290,3 +254,16 @@ int __init cpu_dev_init(void) return err; } + +static struct sysdev_class_attribute *cpu_sysdev_class_attrs[] = { +#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE + &class_attr_probe.attr, + &class_attr_release.attr, +#endif + &cpu_attrs[0].attr, + &cpu_attrs[1].attr, + &cpu_attrs[2].attr, + &attr_kernel_max, + &attr_offline, + NULL +}; -- cgit v1.2.3 From 3701cde6e35245e26f63252f46c62e8a790fa996 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Tue, 5 Jan 2010 12:48:04 +0100 Subject: sysdev: Use sysdev_class attribute arrays in node driver Convert the node driver to sysdev_class attribute arrays. This greatly cleans up the code and remove a lot of code. Saves ~150 bytes of code on x86-64. Signed-off-by: Andi Kleen Signed-off-by: Greg Kroah-Hartman --- drivers/base/node.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/base/node.c b/drivers/base/node.c index aa8bc4bff4f6..ad43185ec15a 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -16,8 +16,11 @@ #include #include +static struct sysdev_class_attribute *node_state_attrs[]; + static struct sysdev_class node_class = { .name = "node", + .attrs = node_state_attrs, }; @@ -569,29 +572,27 @@ static struct node_attr node_state_attr[] = { #endif }; -static int node_states_init(void) -{ - int i; - int err = 0; - - BUILD_BUG_ON(ARRAY_SIZE(node_state_attr) != NR_NODE_STATES); - for (i = 0; i < NR_NODE_STATES; i++) { - int ret; - ret = sysdev_class_create_file(&node_class, &node_state_attr[i].attr); - if (!err) - err = ret; - } - return err; -} +static struct sysdev_class_attribute *node_state_attrs[] = { + &node_state_attr[0].attr, + &node_state_attr[1].attr, + &node_state_attr[2].attr, + &node_state_attr[3].attr, +#ifdef CONFIG_HIGHMEM + &node_state_attr[4].attr, +#endif + NULL +}; #define NODE_CALLBACK_PRI 2 /* lower than SLAB */ static int __init register_node_type(void) { int ret; + BUILD_BUG_ON(ARRAY_SIZE(node_state_attr) != NR_NODE_STATES); + BUILD_BUG_ON(ARRAY_SIZE(node_state_attrs)-1 != NR_NODE_STATES); + ret = sysdev_class_register(&node_class); if (!ret) { - ret = node_states_init(); hotplug_memory_notifier(node_memory_callback, NODE_CALLBACK_PRI); } -- cgit v1.2.3 From 8564a6c140317de04a71eb203bdbb58845d69f9c Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Tue, 5 Jan 2010 12:48:06 +0100 Subject: sysdev: Fix type of sysdev class attribute in memory driver This attribute is really a sysdev_class attribute, not a plain class attribute. They are identical in layout currently, but this might not always be the case. Signed-off-by: Andi Kleen Signed-off-by: Greg Kroah-Hartman --- drivers/base/memory.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/base/memory.c b/drivers/base/memory.c index bd025059711f..563656ad75a1 100644 --- a/drivers/base/memory.c +++ b/drivers/base/memory.c @@ -309,17 +309,18 @@ static SYSDEV_ATTR(removable, 0444, show_mem_removable, NULL); * Block size attribute stuff */ static ssize_t -print_block_size(struct class *class, char *buf) +print_block_size(struct sysdev_class *class, struct sysdev_class_attribute *attr, + char *buf) { return sprintf(buf, "%#lx\n", (unsigned long)PAGES_PER_SECTION * PAGE_SIZE); } -static CLASS_ATTR(block_size_bytes, 0444, print_block_size, NULL); +static SYSDEV_CLASS_ATTR(block_size_bytes, 0444, print_block_size, NULL); static int block_size_init(void) { return sysfs_create_file(&memory_sysdev_class.kset.kobj, - &class_attr_block_size_bytes.attr); + &attr_block_size_bytes.attr); } /* -- cgit v1.2.3 From 28812fe11a21826ba4c97c6c7971a619987cd912 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Tue, 5 Jan 2010 12:48:07 +0100 Subject: driver-core: Add attribute argument to class_attribute show/store Passing the attribute to the low level IO functions allows all kinds of cleanups, by sharing low level IO code without requiring an own function for every piece of data. Also drivers can extend the attributes with own data fields and use that in the low level function. This makes the class attributes the same as sysdev_class attributes and plain attributes. This will allow further cleanups in drivers. Full tree sweep converting all users. Signed-off-by: Andi Kleen Signed-off-by: Greg Kroah-Hartman --- drivers/base/class.c | 4 ++-- drivers/base/cpu.c | 8 ++++++-- drivers/base/firmware_class.c | 8 ++++++-- drivers/base/memory.c | 11 ++++++++--- drivers/block/osdblk.c | 12 +++++++++--- drivers/block/pktcdvd.c | 12 +++++++++--- drivers/gpio/gpiolib.c | 8 ++++++-- drivers/gpu/drm/drm_sysfs.c | 3 ++- drivers/infiniband/core/ucm.c | 4 +++- drivers/infiniband/core/user_mad.c | 4 +++- drivers/infiniband/core/uverbs_main.c | 4 +++- drivers/misc/phantom.c | 2 +- drivers/mtd/ubi/build.c | 3 ++- drivers/net/bonding/bond_sysfs.c | 5 ++++- drivers/staging/asus_oled/asus_oled.c | 4 +++- drivers/uwb/driver.c | 5 ++++- include/linux/device.h | 6 ++++-- net/bluetooth/l2cap.c | 4 +++- net/bluetooth/rfcomm/core.c | 4 +++- net/bluetooth/rfcomm/sock.c | 4 +++- net/bluetooth/sco.c | 4 +++- 21 files changed, 87 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/base/class.c b/drivers/base/class.c index 6e2c3b064f53..34a2de9c5385 100644 --- a/drivers/base/class.c +++ b/drivers/base/class.c @@ -31,7 +31,7 @@ static ssize_t class_attr_show(struct kobject *kobj, struct attribute *attr, ssize_t ret = -EIO; if (class_attr->show) - ret = class_attr->show(cp->class, buf); + ret = class_attr->show(cp->class, class_attr, buf); return ret; } @@ -43,7 +43,7 @@ static ssize_t class_attr_store(struct kobject *kobj, struct attribute *attr, ssize_t ret = -EIO; if (class_attr->store) - ret = class_attr->store(cp->class, buf, count); + ret = class_attr->store(cp->class, class_attr, buf, count); return ret; } diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c index fb456b729803..9121c77b77fa 100644 --- a/drivers/base/cpu.c +++ b/drivers/base/cpu.c @@ -79,13 +79,17 @@ void unregister_cpu(struct cpu *cpu) } #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE -static ssize_t cpu_probe_store(struct class *class, const char *buf, +static ssize_t cpu_probe_store(struct class *class, + struct class_attribute *attr, + const char *buf, size_t count) { return arch_cpu_probe(buf, count); } -static ssize_t cpu_release_store(struct class *class, const char *buf, +static ssize_t cpu_release_store(struct class *class, + struct class_attribute *attr, + const char *buf, size_t count) { return arch_cpu_release(buf, count); diff --git a/drivers/base/firmware_class.c b/drivers/base/firmware_class.c index a95024166b66..6604fb33d072 100644 --- a/drivers/base/firmware_class.c +++ b/drivers/base/firmware_class.c @@ -69,7 +69,9 @@ fw_load_abort(struct firmware_priv *fw_priv) } static ssize_t -firmware_timeout_show(struct class *class, char *buf) +firmware_timeout_show(struct class *class, + struct class_attribute *attr, + char *buf) { return sprintf(buf, "%d\n", loading_timeout); } @@ -87,7 +89,9 @@ firmware_timeout_show(struct class *class, char *buf) * Note: zero means 'wait forever'. **/ static ssize_t -firmware_timeout_store(struct class *class, const char *buf, size_t count) +firmware_timeout_store(struct class *class, + struct class_attribute *attr, + const char *buf, size_t count) { loading_timeout = simple_strtol(buf, NULL, 10); if (loading_timeout < 0) diff --git a/drivers/base/memory.c b/drivers/base/memory.c index 563656ad75a1..495f15e92d4c 100644 --- a/drivers/base/memory.c +++ b/drivers/base/memory.c @@ -331,7 +331,8 @@ static int block_size_init(void) */ #ifdef CONFIG_ARCH_MEMORY_PROBE static ssize_t -memory_probe_store(struct class *class, const char *buf, size_t count) +memory_probe_store(struct class *class, struct class_attribute *attr, + const char *buf, size_t count) { u64 phys_addr; int nid; @@ -368,7 +369,9 @@ static inline int memory_probe_init(void) /* Soft offline a page */ static ssize_t -store_soft_offline_page(struct class *class, const char *buf, size_t count) +store_soft_offline_page(struct class *class, + struct class_attribute *attr, + const char *buf, size_t count) { int ret; u64 pfn; @@ -385,7 +388,9 @@ store_soft_offline_page(struct class *class, const char *buf, size_t count) /* Forcibly offline a page, including killing processes. */ static ssize_t -store_hard_offline_page(struct class *class, const char *buf, size_t count) +store_hard_offline_page(struct class *class, + struct class_attribute *attr, + const char *buf, size_t count) { int ret; u64 pfn; diff --git a/drivers/block/osdblk.c b/drivers/block/osdblk.c index a808b1530b3b..eb2091aa1c19 100644 --- a/drivers/block/osdblk.c +++ b/drivers/block/osdblk.c @@ -476,7 +476,9 @@ static void class_osdblk_release(struct class *cls) kfree(cls); } -static ssize_t class_osdblk_list(struct class *c, char *data) +static ssize_t class_osdblk_list(struct class *c, + struct class_attribute *attr, + char *data) { int n = 0; struct list_head *tmp; @@ -500,7 +502,9 @@ static ssize_t class_osdblk_list(struct class *c, char *data) return n; } -static ssize_t class_osdblk_add(struct class *c, const char *buf, size_t count) +static ssize_t class_osdblk_add(struct class *c, + struct class_attribute *attr, + const char *buf, size_t count) { struct osdblk_device *osdev; ssize_t rc; @@ -592,7 +596,9 @@ err_out_mod: return rc; } -static ssize_t class_osdblk_remove(struct class *c, const char *buf, +static ssize_t class_osdblk_remove(struct class *c, + struct class_attribute *attr, + const char *buf, size_t count) { struct osdblk_device *osdev = NULL; diff --git a/drivers/block/pktcdvd.c b/drivers/block/pktcdvd.c index b72935b8f203..73d815d3f1b2 100644 --- a/drivers/block/pktcdvd.c +++ b/drivers/block/pktcdvd.c @@ -337,7 +337,9 @@ static void class_pktcdvd_release(struct class *cls) { kfree(cls); } -static ssize_t class_pktcdvd_show_map(struct class *c, char *data) +static ssize_t class_pktcdvd_show_map(struct class *c, + struct class_attribute *attr, + char *data) { int n = 0; int idx; @@ -356,7 +358,9 @@ static ssize_t class_pktcdvd_show_map(struct class *c, char *data) return n; } -static ssize_t class_pktcdvd_store_add(struct class *c, const char *buf, +static ssize_t class_pktcdvd_store_add(struct class *c, + struct class_attribute *attr, + const char *buf, size_t count) { unsigned int major, minor; @@ -376,7 +380,9 @@ static ssize_t class_pktcdvd_store_add(struct class *c, const char *buf, return -EINVAL; } -static ssize_t class_pktcdvd_store_remove(struct class *c, const char *buf, +static ssize_t class_pktcdvd_store_remove(struct class *c, + struct class_attribute *attr, + const char *buf, size_t count) { unsigned int major, minor; diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 9006fdb26fea..6d1b86661e63 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -623,7 +623,9 @@ static const struct attribute_group gpiochip_attr_group = { * /sys/class/gpio/unexport ... write-only * integer N ... number of GPIO to unexport */ -static ssize_t export_store(struct class *class, const char *buf, size_t len) +static ssize_t export_store(struct class *class, + struct class_attribute *attr, + const char *buf, size_t len) { long gpio; int status; @@ -653,7 +655,9 @@ done: return status ? : len; } -static ssize_t unexport_store(struct class *class, const char *buf, size_t len) +static ssize_t unexport_store(struct class *class, + struct class_attribute *attr, + const char *buf, size_t len) { long gpio; int status; diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index 7e42b7e9d43a..b95aaf23596e 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -71,7 +71,8 @@ static int drm_class_resume(struct device *dev) } /* Display the version of drm_core. This doesn't work right in current design */ -static ssize_t version_show(struct class *dev, char *buf) +static ssize_t version_show(struct class *dev, struct class_attribute *attr, + char *buf) { return sprintf(buf, "%s %d.%d.%d %s\n", CORE_NAME, CORE_MAJOR, CORE_MINOR, CORE_PATCHLEVEL, CORE_DATE); diff --git a/drivers/infiniband/core/ucm.c b/drivers/infiniband/core/ucm.c index 1b09b735c5a8..02e209ff33fd 100644 --- a/drivers/infiniband/core/ucm.c +++ b/drivers/infiniband/core/ucm.c @@ -1336,7 +1336,9 @@ static void ib_ucm_remove_one(struct ib_device *device) device_unregister(&ucm_dev->dev); } -static ssize_t show_abi_version(struct class *class, char *buf) +static ssize_t show_abi_version(struct class *class, + struct class_attribute *attr, + char *buf) { return sprintf(buf, "%d\n", IB_USER_CM_ABI_VERSION); } diff --git a/drivers/infiniband/core/user_mad.c b/drivers/infiniband/core/user_mad.c index 02d360cfc2f7..d0de8f265f45 100644 --- a/drivers/infiniband/core/user_mad.c +++ b/drivers/infiniband/core/user_mad.c @@ -965,7 +965,9 @@ static ssize_t show_port(struct device *dev, struct device_attribute *attr, } static DEVICE_ATTR(port, S_IRUGO, show_port, NULL); -static ssize_t show_abi_version(struct class *class, char *buf) +static ssize_t show_abi_version(struct class *class, + struct class_attribute *attr, + char *buf) { return sprintf(buf, "%d\n", IB_USER_MAD_ABI_VERSION); } diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c index 4fa2e6516441..60879399207a 100644 --- a/drivers/infiniband/core/uverbs_main.c +++ b/drivers/infiniband/core/uverbs_main.c @@ -691,7 +691,9 @@ static ssize_t show_dev_abi_version(struct device *device, } static DEVICE_ATTR(abi_version, S_IRUGO, show_dev_abi_version, NULL); -static ssize_t show_abi_version(struct class *class, char *buf) +static ssize_t show_abi_version(struct class *class, + struct class_attribute *attr, + char *buf) { return sprintf(buf, "%d\n", IB_USER_VERBS_ABI_VERSION); } diff --git a/drivers/misc/phantom.c b/drivers/misc/phantom.c index 04c27266f567..d30ae9560309 100644 --- a/drivers/misc/phantom.c +++ b/drivers/misc/phantom.c @@ -497,7 +497,7 @@ static struct pci_driver phantom_pci_driver = { .resume = phantom_resume }; -static ssize_t phantom_show_version(struct class *cls, char *buf) +static ssize_t phantom_show_version(struct class *cls, struct class_attribute *attr, char *buf) { return sprintf(buf, PHANTOM_VERSION "\n"); } diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index bc45ef9af17d..fad40aa6f099 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -89,7 +89,8 @@ DEFINE_MUTEX(ubi_devices_mutex); static DEFINE_SPINLOCK(ubi_devices_lock); /* "Show" method for files in '//class/ubi/' */ -static ssize_t ubi_version_show(struct class *class, char *buf) +static ssize_t ubi_version_show(struct class *class, struct class_attribute *attr, + char *buf) { return sprintf(buf, "%d\n", UBI_VERSION); } diff --git a/drivers/net/bonding/bond_sysfs.c b/drivers/net/bonding/bond_sysfs.c index 5acd557cea9b..b8bec086daa1 100644 --- a/drivers/net/bonding/bond_sysfs.c +++ b/drivers/net/bonding/bond_sysfs.c @@ -51,7 +51,9 @@ * "show" function for the bond_masters attribute. * The class parameter is ignored. */ -static ssize_t bonding_show_bonds(struct class *cls, char *buf) +static ssize_t bonding_show_bonds(struct class *cls, + struct class_attribute *attr, + char *buf) { struct net *net = current->nsproxy->net_ns; struct bond_net *bn = net_generic(net, bond_net_id); @@ -98,6 +100,7 @@ static struct net_device *bond_get_by_name(struct net *net, const char *ifname) */ static ssize_t bonding_store_bonds(struct class *cls, + struct class_attribute *attr, const char *buffer, size_t count) { struct net *net = current->nsproxy->net_ns; diff --git a/drivers/staging/asus_oled/asus_oled.c b/drivers/staging/asus_oled/asus_oled.c index cadb6f7321ad..7d93f50a0a64 100644 --- a/drivers/staging/asus_oled/asus_oled.c +++ b/drivers/staging/asus_oled/asus_oled.c @@ -770,7 +770,9 @@ static struct usb_driver oled_driver = { .id_table = id_table, }; -static ssize_t version_show(struct class *dev, char *buf) +static ssize_t version_show(struct class *dev, + struct class_attribute *attr, + char *buf) { return sprintf(buf, ASUS_OLED_UNDERSCORE_NAME " %s\n", ASUS_OLED_VERSION); diff --git a/drivers/uwb/driver.c b/drivers/uwb/driver.c index da77e41de990..08bd6dbfd4a6 100644 --- a/drivers/uwb/driver.c +++ b/drivers/uwb/driver.c @@ -74,13 +74,16 @@ unsigned long beacon_timeout_ms = 500; static -ssize_t beacon_timeout_ms_show(struct class *class, char *buf) +ssize_t beacon_timeout_ms_show(struct class *class, + struct class_attribute *attr, + char *buf) { return scnprintf(buf, PAGE_SIZE, "%lu\n", beacon_timeout_ms); } static ssize_t beacon_timeout_ms_store(struct class *class, + struct class_attribute *attr, const char *buf, size_t size) { unsigned long bt; diff --git a/include/linux/device.h b/include/linux/device.h index b30527db3ac0..190f8d30d1d3 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -251,8 +251,10 @@ extern struct device *class_find_device(struct class *class, struct class_attribute { struct attribute attr; - ssize_t (*show)(struct class *class, char *buf); - ssize_t (*store)(struct class *class, const char *buf, size_t count); + ssize_t (*show)(struct class *class, struct class_attribute *attr, + char *buf); + ssize_t (*store)(struct class *class, struct class_attribute *attr, + const char *buf, size_t count); }; #define CLASS_ATTR(_name, _mode, _show, _store) \ diff --git a/net/bluetooth/l2cap.c b/net/bluetooth/l2cap.c index 400efa26ddba..4db7ae2fe07d 100644 --- a/net/bluetooth/l2cap.c +++ b/net/bluetooth/l2cap.c @@ -3937,7 +3937,9 @@ drop: return 0; } -static ssize_t l2cap_sysfs_show(struct class *dev, char *buf) +static ssize_t l2cap_sysfs_show(struct class *dev, + struct class_attribute *attr, + char *buf) { struct sock *sk; struct hlist_node *node; diff --git a/net/bluetooth/rfcomm/core.c b/net/bluetooth/rfcomm/core.c index 89f4a59eb82b..db8a68e1a5ba 100644 --- a/net/bluetooth/rfcomm/core.c +++ b/net/bluetooth/rfcomm/core.c @@ -2098,7 +2098,9 @@ static struct hci_cb rfcomm_cb = { .security_cfm = rfcomm_security_cfm }; -static ssize_t rfcomm_dlc_sysfs_show(struct class *dev, char *buf) +static ssize_t rfcomm_dlc_sysfs_show(struct class *dev, + struct class_attribute *attr, + char *buf) { struct rfcomm_session *s; struct list_head *pp, *p; diff --git a/net/bluetooth/rfcomm/sock.c b/net/bluetooth/rfcomm/sock.c index 4b5968dda673..ca87d6ac6a20 100644 --- a/net/bluetooth/rfcomm/sock.c +++ b/net/bluetooth/rfcomm/sock.c @@ -1061,7 +1061,9 @@ done: return result; } -static ssize_t rfcomm_sock_sysfs_show(struct class *dev, char *buf) +static ssize_t rfcomm_sock_sysfs_show(struct class *dev, + struct class_attribute *attr, + char *buf) { struct sock *sk; struct hlist_node *node; diff --git a/net/bluetooth/sco.c b/net/bluetooth/sco.c index dd8f6ec57dce..f93b939539bc 100644 --- a/net/bluetooth/sco.c +++ b/net/bluetooth/sco.c @@ -953,7 +953,9 @@ drop: return 0; } -static ssize_t sco_sysfs_show(struct class *dev, char *buf) +static ssize_t sco_sysfs_show(struct class *dev, + struct class_attribute *attr, + char *buf) { struct sock *sk; struct hlist_node *node; -- cgit v1.2.3 From 869dfc875e32fd832385fd52ce54525a10401ed6 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Tue, 5 Jan 2010 12:48:08 +0100 Subject: driver core: Add class_attr_string for simple read-only string Several drivers just export a static string as class attributes. Use the new extensible attribute support to define a simple CLASS_ATTR_STRING() macro for this. This will allow to remove code from drivers in followon patches. Signed-off-by: Andi Kleen Signed-off-by: Greg Kroah-Hartman --- drivers/base/class.c | 10 ++++++++++ include/linux/device.h | 17 +++++++++++++++++ 2 files changed, 27 insertions(+) (limited to 'drivers') diff --git a/drivers/base/class.c b/drivers/base/class.c index 34a2de9c5385..2e297cc4cd3d 100644 --- a/drivers/base/class.c +++ b/drivers/base/class.c @@ -490,6 +490,16 @@ void class_interface_unregister(struct class_interface *class_intf) class_put(parent); } +ssize_t show_class_attr_string(struct class *class, struct class_attribute *attr, + char *buf) +{ + struct class_attribute_string *cs; + cs = container_of(attr, struct class_attribute_string, attr); + return snprintf(buf, PAGE_SIZE, "%s\n", cs->str); +} + +EXPORT_SYMBOL_GPL(show_class_attr_string); + struct class_compat { struct kobject *kobj; }; diff --git a/include/linux/device.h b/include/linux/device.h index 190f8d30d1d3..f95d5bfe8248 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -265,6 +265,23 @@ extern int __must_check class_create_file(struct class *class, extern void class_remove_file(struct class *class, const struct class_attribute *attr); +/* Simple class attribute that is just a static string */ + +struct class_attribute_string { + struct class_attribute attr; + char *str; +}; + +/* Currently read-only only */ +#define _CLASS_ATTR_STRING(_name, _mode, _str) \ + { __ATTR(_name, _mode, show_class_attr_string, NULL), _str } +#define CLASS_ATTR_STRING(_name, _mode, _str) \ + struct class_attribute_string class_attr_##_name = \ + _CLASS_ATTR_STRING(_name, _mode, _str) + +extern ssize_t show_class_attr_string(struct class *class, struct class_attribute *attr, + char *buf); + struct class_interface { struct list_head node; struct class *class; -- cgit v1.2.3 From 0933e2d98d1b170ef62d48e18157f5dc43b58217 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Tue, 5 Jan 2010 12:48:09 +0100 Subject: driver core: Convert some drivers to CLASS_ATTR_STRING Convert some drivers who export a single string as class attribute to the new class_attr_string functions. This removes redundant code all over. Signed-off-by: Andi Kleen Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/drm_sysfs.c | 19 ++++++++----------- drivers/infiniband/core/ucm.c | 15 +++++---------- drivers/infiniband/core/user_mad.c | 11 +++-------- drivers/infiniband/core/uverbs_main.c | 11 +++-------- drivers/misc/phantom.c | 13 ++++--------- drivers/staging/asus_oled/asus_oled.c | 15 ++++----------- 6 files changed, 27 insertions(+), 57 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index b95aaf23596e..014ce24761b9 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -70,20 +70,17 @@ static int drm_class_resume(struct device *dev) return 0; } -/* Display the version of drm_core. This doesn't work right in current design */ -static ssize_t version_show(struct class *dev, struct class_attribute *attr, - char *buf) -{ - return sprintf(buf, "%s %d.%d.%d %s\n", CORE_NAME, CORE_MAJOR, - CORE_MINOR, CORE_PATCHLEVEL, CORE_DATE); -} - static char *drm_devnode(struct device *dev, mode_t *mode) { return kasprintf(GFP_KERNEL, "dri/%s", dev_name(dev)); } -static CLASS_ATTR(version, S_IRUGO, version_show, NULL); +static CLASS_ATTR_STRING(version, S_IRUGO, + CORE_NAME " " + __stringify(CORE_MAJOR) "." + __stringify(CORE_MINOR) "." + __stringify(CORE_PATCHLEVEL) " " + CORE_DATE); /** * drm_sysfs_create - create a struct drm_sysfs_class structure @@ -110,7 +107,7 @@ struct class *drm_sysfs_create(struct module *owner, char *name) class->suspend = drm_class_suspend; class->resume = drm_class_resume; - err = class_create_file(class, &class_attr_version); + err = class_create_file(class, &class_attr_version.attr); if (err) goto err_out_class; @@ -133,7 +130,7 @@ void drm_sysfs_destroy(void) { if ((drm_class == NULL) || (IS_ERR(drm_class))) return; - class_remove_file(drm_class, &class_attr_version); + class_remove_file(drm_class, &class_attr_version.attr); class_destroy(drm_class); } diff --git a/drivers/infiniband/core/ucm.c b/drivers/infiniband/core/ucm.c index 02e209ff33fd..017d6e24448f 100644 --- a/drivers/infiniband/core/ucm.c +++ b/drivers/infiniband/core/ucm.c @@ -1336,13 +1336,8 @@ static void ib_ucm_remove_one(struct ib_device *device) device_unregister(&ucm_dev->dev); } -static ssize_t show_abi_version(struct class *class, - struct class_attribute *attr, - char *buf) -{ - return sprintf(buf, "%d\n", IB_USER_CM_ABI_VERSION); -} -static CLASS_ATTR(abi_version, S_IRUGO, show_abi_version, NULL); +static CLASS_ATTR_STRING(abi_version, S_IRUGO, + __stringify(IB_USER_CM_ABI_VERSION)); static int __init ib_ucm_init(void) { @@ -1355,7 +1350,7 @@ static int __init ib_ucm_init(void) goto error1; } - ret = class_create_file(&cm_class, &class_attr_abi_version); + ret = class_create_file(&cm_class, &class_attr_abi_version.attr); if (ret) { printk(KERN_ERR "ucm: couldn't create abi_version attribute\n"); goto error2; @@ -1369,7 +1364,7 @@ static int __init ib_ucm_init(void) return 0; error3: - class_remove_file(&cm_class, &class_attr_abi_version); + class_remove_file(&cm_class, &class_attr_abi_version.attr); error2: unregister_chrdev_region(IB_UCM_BASE_DEV, IB_UCM_MAX_DEVICES); error1: @@ -1379,7 +1374,7 @@ error1: static void __exit ib_ucm_cleanup(void) { ib_unregister_client(&ucm_client); - class_remove_file(&cm_class, &class_attr_abi_version); + class_remove_file(&cm_class, &class_attr_abi_version.attr); unregister_chrdev_region(IB_UCM_BASE_DEV, IB_UCM_MAX_DEVICES); if (overflow_maj) unregister_chrdev_region(overflow_maj, IB_UCM_MAX_DEVICES); diff --git a/drivers/infiniband/core/user_mad.c b/drivers/infiniband/core/user_mad.c index d0de8f265f45..04b585e86cb2 100644 --- a/drivers/infiniband/core/user_mad.c +++ b/drivers/infiniband/core/user_mad.c @@ -965,13 +965,8 @@ static ssize_t show_port(struct device *dev, struct device_attribute *attr, } static DEVICE_ATTR(port, S_IRUGO, show_port, NULL); -static ssize_t show_abi_version(struct class *class, - struct class_attribute *attr, - char *buf) -{ - return sprintf(buf, "%d\n", IB_USER_MAD_ABI_VERSION); -} -static CLASS_ATTR(abi_version, S_IRUGO, show_abi_version, NULL); +static CLASS_ATTR_STRING(abi_version, S_IRUGO, + __stringify(IB_USER_MAD_ABI_VERSION)); static dev_t overflow_maj; static DECLARE_BITMAP(overflow_map, IB_UMAD_MAX_PORTS); @@ -1196,7 +1191,7 @@ static int __init ib_umad_init(void) goto out_chrdev; } - ret = class_create_file(umad_class, &class_attr_abi_version); + ret = class_create_file(umad_class, &class_attr_abi_version.attr); if (ret) { printk(KERN_ERR "user_mad: couldn't create abi_version attribute\n"); goto out_class; diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c index 60879399207a..d805cf365c8d 100644 --- a/drivers/infiniband/core/uverbs_main.c +++ b/drivers/infiniband/core/uverbs_main.c @@ -691,13 +691,8 @@ static ssize_t show_dev_abi_version(struct device *device, } static DEVICE_ATTR(abi_version, S_IRUGO, show_dev_abi_version, NULL); -static ssize_t show_abi_version(struct class *class, - struct class_attribute *attr, - char *buf) -{ - return sprintf(buf, "%d\n", IB_USER_VERBS_ABI_VERSION); -} -static CLASS_ATTR(abi_version, S_IRUGO, show_abi_version, NULL); +static CLASS_ATTR_STRING(abi_version, S_IRUGO, + __stringify(IB_USER_VERBS_ABI_VERSION)); static dev_t overflow_maj; static DECLARE_BITMAP(overflow_map, IB_UVERBS_MAX_DEVICES); @@ -843,7 +838,7 @@ static int __init ib_uverbs_init(void) goto out_chrdev; } - ret = class_create_file(uverbs_class, &class_attr_abi_version); + ret = class_create_file(uverbs_class, &class_attr_abi_version.attr); if (ret) { printk(KERN_ERR "user_verbs: couldn't create abi_version attribute\n"); goto out_class; diff --git a/drivers/misc/phantom.c b/drivers/misc/phantom.c index d30ae9560309..779aa8ebe4cf 100644 --- a/drivers/misc/phantom.c +++ b/drivers/misc/phantom.c @@ -497,12 +497,7 @@ static struct pci_driver phantom_pci_driver = { .resume = phantom_resume }; -static ssize_t phantom_show_version(struct class *cls, struct class_attribute *attr, char *buf) -{ - return sprintf(buf, PHANTOM_VERSION "\n"); -} - -static CLASS_ATTR(version, 0444, phantom_show_version, NULL); +static CLASS_ATTR_STRING(version, 0444, PHANTOM_VERSION); static int __init phantom_init(void) { @@ -515,7 +510,7 @@ static int __init phantom_init(void) printk(KERN_ERR "phantom: can't register phantom class\n"); goto err; } - retval = class_create_file(phantom_class, &class_attr_version); + retval = class_create_file(phantom_class, &class_attr_version.attr); if (retval) { printk(KERN_ERR "phantom: can't create sysfs version file\n"); goto err_class; @@ -541,7 +536,7 @@ static int __init phantom_init(void) err_unchr: unregister_chrdev_region(dev, PHANTOM_MAX_MINORS); err_attr: - class_remove_file(phantom_class, &class_attr_version); + class_remove_file(phantom_class, &class_attr_version.attr); err_class: class_destroy(phantom_class); err: @@ -554,7 +549,7 @@ static void __exit phantom_exit(void) unregister_chrdev_region(MKDEV(phantom_major, 0), PHANTOM_MAX_MINORS); - class_remove_file(phantom_class, &class_attr_version); + class_remove_file(phantom_class, &class_attr_version.attr); class_destroy(phantom_class); pr_debug("phantom: module successfully removed\n"); diff --git a/drivers/staging/asus_oled/asus_oled.c b/drivers/staging/asus_oled/asus_oled.c index 7d93f50a0a64..7ebecc92c61b 100644 --- a/drivers/staging/asus_oled/asus_oled.c +++ b/drivers/staging/asus_oled/asus_oled.c @@ -770,15 +770,8 @@ static struct usb_driver oled_driver = { .id_table = id_table, }; -static ssize_t version_show(struct class *dev, - struct class_attribute *attr, - char *buf) -{ - return sprintf(buf, ASUS_OLED_UNDERSCORE_NAME " %s\n", - ASUS_OLED_VERSION); -} - -static CLASS_ATTR(version, S_IRUGO, version_show, NULL); +static CLASS_ATTR_STRING(version, S_IRUGO, + ASUS_OLED_UNDERSCORE_NAME " " ASUS_OLED_VERSION); static int __init asus_oled_init(void) { @@ -790,7 +783,7 @@ static int __init asus_oled_init(void) return PTR_ERR(oled_class); } - retval = class_create_file(oled_class, &class_attr_version); + retval = class_create_file(oled_class, &class_attr_version.attr); if (retval) { err("Error creating class version file"); goto error; @@ -812,7 +805,7 @@ error: static void __exit asus_oled_exit(void) { - class_remove_file(oled_class, &class_attr_version); + class_remove_file(oled_class, &class_attr_version.attr); class_destroy(oled_class); usb_deregister(&oled_driver); -- cgit v1.2.3 From 5e31d76f2817bd50258a092a7c5b15b3006fd61c Mon Sep 17 00:00:00 2001 From: Kay Sievers Date: Wed, 13 Jan 2010 14:16:36 +0100 Subject: Driver-Core: devtmpfs - reset inode permissions before unlinking Before unlinking the inode, reset the current permissions of possible references like hardlinks, so granted permissions can not be retained across the device lifetime by creating hardlinks, in the unusual case that there is a user-writable directory on the same filesystem. Signed-off-by: Kay Sievers Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/base/devtmpfs.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers') diff --git a/drivers/base/devtmpfs.c b/drivers/base/devtmpfs.c index 42ae452b36b0..dac478c6e460 100644 --- a/drivers/base/devtmpfs.c +++ b/drivers/base/devtmpfs.c @@ -301,6 +301,19 @@ int devtmpfs_delete_node(struct device *dev) if (dentry->d_inode) { err = vfs_getattr(nd.path.mnt, dentry, &stat); if (!err && dev_mynode(dev, dentry->d_inode, &stat)) { + struct iattr newattrs; + /* + * before unlinking this node, reset permissions + * of possible references like hardlinks + */ + newattrs.ia_uid = 0; + newattrs.ia_gid = 0; + newattrs.ia_mode = stat.mode & ~0777; + newattrs.ia_valid = + ATTR_UID|ATTR_GID|ATTR_MODE; + mutex_lock(&dentry->d_inode->i_mutex); + notify_change(dentry, &newattrs); + mutex_unlock(&dentry->d_inode->i_mutex); err = vfs_unlink(nd.path.dentry->d_inode, dentry); if (!err || err == -ENOENT) -- cgit v1.2.3 From 4237e5fd3e07da268029cd4862cf551d9a74e33f Mon Sep 17 00:00:00 2001 From: Kay Sievers Date: Thu, 14 Jan 2010 22:47:57 +0100 Subject: Driver-Core: devtmpfs - remove EXPERIMENTAL and flush out the description All major distros enable devtmpfs on recent systems, so remove the EXPERIMENTAL flag, and make the description a bit more instructive. Signed-off-by: Kay Sievers Signed-off-by: Greg Kroah-Hartman --- drivers/base/Kconfig | 41 ++++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig index ee377270beb9..8021e19fa1ea 100644 --- a/drivers/base/Kconfig +++ b/drivers/base/Kconfig @@ -9,29 +9,36 @@ config UEVENT_HELPER_PATH every uevent. config DEVTMPFS - bool "Create a kernel maintained /dev tmpfs (EXPERIMENTAL)" + bool "Maintain a devtmpfs filesystem to mount at /dev" depends on HOTPLUG && SHMEM && TMPFS help - This creates a tmpfs filesystem, and mounts it at bootup - and mounts it at /dev. The kernel driver core creates device - nodes for all registered devices in that filesystem. All device - nodes are owned by root and have the default mode of 0600. - Userspace can add and delete the nodes as needed. This is - intended to simplify bootup, and make it possible to delay - the initial coldplug at bootup done by udev in userspace. - It should also provide a simpler way for rescue systems - to bring up a kernel with dynamic major/minor numbers. - Meaningful symlinks, permissions and device ownership must - still be handled by userspace. - If unsure, say N here. + This creates a tmpfs filesystem instance early at bootup. + In this filesystem, the kernel driver core maintains device + nodes with their default names and permissions for all + registered devices with an assigned major/minor number. + Userspace can modify the filesystem content as needed, add + symlinks, and apply needed permissions. + It provides a fully functional /dev directory, where usually + udev runs on top, managing permissions and adding meaningful + symlinks. + In very limited environments, it may provide a sufficient + functional /dev without any further help. It also allows simple + rescue systems, and reliably handles dynamic major/minor numbers. config DEVTMPFS_MOUNT - bool "Automount devtmpfs at /dev" + bool "Automount devtmpfs at /dev, after the kernel mounted the rootfs" depends on DEVTMPFS help - This will mount devtmpfs at /dev if the kernel mounts the root - filesystem. It will not affect initramfs based mounting. - If unsure, say N here. + This will instruct the kernel to automatically mount the + devtmpfs filesystem at /dev, directly after the kernel has + mounted the root filesystem. The behavior can be overridden + with the commandline parameter: devtmpfs.mount=0|1. + This option does not affect initramfs based booting, here + the devtmpfs filesystem always needs to be mounted manually + after the roots is mounted. + With this option enabled, it allows to bring up a system in + rescue mode with init=/bin/sh, even when the /dev directory + on the rootfs is completely empty. config STANDALONE bool "Select only drivers that don't need compile-time external firmware" if EXPERIMENTAL -- cgit v1.2.3 From 7934779a69f1184f29d786b89e77dd14519bd226 Mon Sep 17 00:00:00 2001 From: Kay Sievers Date: Thu, 14 Jan 2010 22:49:39 +0100 Subject: Driver-Core: disable /sbin/hotplug by default No recent mainstream system uses the /sbin/hotplug fork-bomb any more. Disable it by default to reflect how it is used these days. Signed-off-by: Kay Sievers Signed-off-by: Greg Kroah-Hartman --- drivers/base/Kconfig | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig index 8021e19fa1ea..fd52c48ee762 100644 --- a/drivers/base/Kconfig +++ b/drivers/base/Kconfig @@ -3,10 +3,18 @@ menu "Generic Driver Options" config UEVENT_HELPER_PATH string "path to uevent helper" depends on HOTPLUG - default "/sbin/hotplug" + default "" help Path to uevent helper program forked by the kernel for every uevent. + Before the switch to the netlink-based uevent source, this was + used to hook hotplug scripts into kernel device events. It + usually pointed to a shell script at /sbin/hotplug. + This should not be used today, because usual systems create + many events at bootup or device discovery in a very short time + frame. One forked process per event can create so many processes + that it creates a high system load, or on smaller systems + it is known to create out-of-memory situations during bootup. config DEVTMPFS bool "Maintain a devtmpfs filesystem to mount at /dev" -- cgit v1.2.3 From 3f5468c9ae293cbca43e4ffe6ca3b3235189042a Mon Sep 17 00:00:00 2001 From: Kay Sievers Date: Thu, 14 Jan 2010 22:54:37 +0100 Subject: Driver-Core: require valid action string in uevent trigger No longer fall back to "add" and warn, but always require a valid action-string written to the "uevent" file. Signed-off-by: Kay Sievers Signed-off-by: Greg Kroah-Hartman --- drivers/base/core.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/base/core.c b/drivers/base/core.c index fb4bc4f5151c..f6c73a9e3d95 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -306,15 +306,10 @@ static ssize_t store_uevent(struct device *dev, struct device_attribute *attr, { enum kobject_action action; - if (kobject_action_type(buf, count, &action) == 0) { + if (kobject_action_type(buf, count, &action) == 0) kobject_uevent(&dev->kobj, action); - goto out; - } - - dev_err(dev, "uevent: unsupported action-string; this will " - "be ignored in a future kernel version\n"); - kobject_uevent(&dev->kobj, KOBJ_ADD); -out: + else + dev_err(dev, "uevent: unknown action-string\n"); return count; } -- cgit v1.2.3 From 985fc176a6c03836454629be2f2a611ccc7c7002 Mon Sep 17 00:00:00 2001 From: "Luis R. Rodriguez" Date: Wed, 13 Jan 2010 21:18:15 -0500 Subject: driver-core: firmware_class: remove base.h header inclusion base.h is used by base drivers for sharing internal structures. Turns out firmware_class does not depend on it at all so remove it. Cc: Johannes Berg Signed-off-by: Luis R. Rodriguez Acked-by: Marcel Holtmann Signed-off-by: Greg Kroah-Hartman --- drivers/base/firmware_class.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/base/firmware_class.c b/drivers/base/firmware_class.c index 6604fb33d072..07977484cb3c 100644 --- a/drivers/base/firmware_class.c +++ b/drivers/base/firmware_class.c @@ -19,7 +19,6 @@ #include #include #include -#include "base.h" #define to_dev(obj) container_of(obj, struct device, kobj) -- cgit v1.2.3 From 9cd43611ccfb46632bfa7d19f688924ea93f1613 Mon Sep 17 00:00:00 2001 From: Emese Revfy Date: Thu, 31 Dec 2009 14:52:51 +0100 Subject: kobject: Constify struct kset_uevent_ops Constify struct kset_uevent_ops. This is part of the ops structure constification effort started by Arjan van de Ven et al. Benefits of this constification: * prevents modification of data that is shared (referenced) by many other structure instances at runtime * detects/prevents accidental (but not intentional) modification attempts on archs that enforce read-only kernel data at runtime * potentially better optimized code as the compiler can assume that the const data cannot be changed * the compiler/linker move const data into .rodata and therefore exclude them from false sharing Signed-off-by: Emese Revfy Signed-off-by: Greg Kroah-Hartman --- drivers/base/bus.c | 2 +- drivers/base/core.c | 2 +- drivers/base/memory.c | 2 +- fs/gfs2/sys.c | 2 +- include/linux/kobject.h | 10 +++++----- kernel/params.c | 2 +- lib/kobject.c | 4 ++-- lib/kobject_uevent.c | 2 +- mm/slub.c | 2 +- 9 files changed, 14 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/base/bus.c b/drivers/base/bus.c index c0c5a43d9fb3..2afe599eb35d 100644 --- a/drivers/base/bus.c +++ b/drivers/base/bus.c @@ -154,7 +154,7 @@ static int bus_uevent_filter(struct kset *kset, struct kobject *kobj) return 0; } -static struct kset_uevent_ops bus_uevent_ops = { +static const struct kset_uevent_ops bus_uevent_ops = { .filter = bus_uevent_filter, }; diff --git a/drivers/base/core.c b/drivers/base/core.c index f6c73a9e3d95..58ec1069f4b0 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -252,7 +252,7 @@ static int dev_uevent(struct kset *kset, struct kobject *kobj, return retval; } -static struct kset_uevent_ops device_uevent_ops = { +static const struct kset_uevent_ops device_uevent_ops = { .filter = dev_uevent_filter, .name = dev_uevent_name, .uevent = dev_uevent, diff --git a/drivers/base/memory.c b/drivers/base/memory.c index 495f15e92d4c..2f8691511190 100644 --- a/drivers/base/memory.c +++ b/drivers/base/memory.c @@ -44,7 +44,7 @@ static int memory_uevent(struct kset *kset, struct kobject *obj, struct kobj_uev return retval; } -static struct kset_uevent_ops memory_uevent_ops = { +static const struct kset_uevent_ops memory_uevent_ops = { .name = memory_uevent_name, .uevent = memory_uevent, }; diff --git a/fs/gfs2/sys.c b/fs/gfs2/sys.c index b5f1a46133c8..543503010ed0 100644 --- a/fs/gfs2/sys.c +++ b/fs/gfs2/sys.c @@ -574,7 +574,7 @@ static int gfs2_uevent(struct kset *kset, struct kobject *kobj, return 0; } -static struct kset_uevent_ops gfs2_uevent_ops = { +static const struct kset_uevent_ops gfs2_uevent_ops = { .uevent = gfs2_uevent, }; diff --git a/include/linux/kobject.h b/include/linux/kobject.h index 58ae8e00fcdd..57a1eaae9096 100644 --- a/include/linux/kobject.h +++ b/include/linux/kobject.h @@ -118,9 +118,9 @@ struct kobj_uevent_env { }; struct kset_uevent_ops { - int (*filter)(struct kset *kset, struct kobject *kobj); - const char *(*name)(struct kset *kset, struct kobject *kobj); - int (*uevent)(struct kset *kset, struct kobject *kobj, + int (* const filter)(struct kset *kset, struct kobject *kobj); + const char *(* const name)(struct kset *kset, struct kobject *kobj); + int (* const uevent)(struct kset *kset, struct kobject *kobj, struct kobj_uevent_env *env); }; @@ -155,14 +155,14 @@ struct kset { struct list_head list; spinlock_t list_lock; struct kobject kobj; - struct kset_uevent_ops *uevent_ops; + const struct kset_uevent_ops *uevent_ops; }; extern void kset_init(struct kset *kset); extern int __must_check kset_register(struct kset *kset); extern void kset_unregister(struct kset *kset); extern struct kset * __must_check kset_create_and_add(const char *name, - struct kset_uevent_ops *u, + const struct kset_uevent_ops *u, struct kobject *parent_kobj); static inline struct kset *to_kset(struct kobject *kobj) diff --git a/kernel/params.c b/kernel/params.c index 8d95f5451b22..48370be3c0a1 100644 --- a/kernel/params.c +++ b/kernel/params.c @@ -736,7 +736,7 @@ static int uevent_filter(struct kset *kset, struct kobject *kobj) return 0; } -static struct kset_uevent_ops module_uevent_ops = { +static const struct kset_uevent_ops module_uevent_ops = { .filter = uevent_filter, }; diff --git a/lib/kobject.c b/lib/kobject.c index b512b746d2af..cecf5a0ef6e1 100644 --- a/lib/kobject.c +++ b/lib/kobject.c @@ -789,7 +789,7 @@ static struct kobj_type kset_ktype = { * If the kset was not able to be created, NULL will be returned. */ static struct kset *kset_create(const char *name, - struct kset_uevent_ops *uevent_ops, + const struct kset_uevent_ops *uevent_ops, struct kobject *parent_kobj) { struct kset *kset; @@ -832,7 +832,7 @@ static struct kset *kset_create(const char *name, * If the kset was not able to be created, NULL will be returned. */ struct kset *kset_create_and_add(const char *name, - struct kset_uevent_ops *uevent_ops, + const struct kset_uevent_ops *uevent_ops, struct kobject *parent_kobj) { struct kset *kset; diff --git a/lib/kobject_uevent.c b/lib/kobject_uevent.c index 920a3ca6e259..c9d3a3e8405d 100644 --- a/lib/kobject_uevent.c +++ b/lib/kobject_uevent.c @@ -95,7 +95,7 @@ int kobject_uevent_env(struct kobject *kobj, enum kobject_action action, const char *subsystem; struct kobject *top_kobj; struct kset *kset; - struct kset_uevent_ops *uevent_ops; + const struct kset_uevent_ops *uevent_ops; u64 seq; int i = 0; int retval = 0; diff --git a/mm/slub.c b/mm/slub.c index 0bfd3863d521..a26753c12dcd 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -4409,7 +4409,7 @@ static int uevent_filter(struct kset *kset, struct kobject *kobj) return 0; } -static struct kset_uevent_ops slab_uevent_ops = { +static const struct kset_uevent_ops slab_uevent_ops = { .filter = uevent_filter, }; -- cgit v1.2.3 From 6c1733aca0b48db4d0e660d54976a1cca25b5eaf Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 21 Jan 2010 15:07:59 -0800 Subject: sysdev: fix up the probe/release attributes These should be sysdev attributes, not class attributes. This patch should resolve the problem. Thanks to Stephen Rothwell for pointing out the problem. Reported-by: Stephen Rothwell Cc: Andi Kleen Signed-off-by: Greg Kroah-Hartman --- drivers/base/cpu.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c index 9121c77b77fa..7036e8e96ab8 100644 --- a/drivers/base/cpu.c +++ b/drivers/base/cpu.c @@ -79,24 +79,24 @@ void unregister_cpu(struct cpu *cpu) } #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE -static ssize_t cpu_probe_store(struct class *class, - struct class_attribute *attr, +static ssize_t cpu_probe_store(struct sys_device *dev, + struct sysdev_attribute *attr, const char *buf, size_t count) { return arch_cpu_probe(buf, count); } -static ssize_t cpu_release_store(struct class *class, - struct class_attribute *attr, +static ssize_t cpu_release_store(struct sys_device *dev, + struct sysdev_attribute *attr, const char *buf, size_t count) { return arch_cpu_release(buf, count); } -static CLASS_ATTR(probe, S_IWUSR, NULL, cpu_probe_store); -static CLASS_ATTR(release, S_IWUSR, NULL, cpu_release_store); +static SYSDEV_ATTR(probe, S_IWUSR, NULL, cpu_probe_store); +static SYSDEV_ATTR(release, S_IWUSR, NULL, cpu_release_store); #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */ #else /* ... !CONFIG_HOTPLUG_CPU */ @@ -261,8 +261,8 @@ int __init cpu_dev_init(void) static struct sysdev_class_attribute *cpu_sysdev_class_attrs[] = { #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE - &class_attr_probe.attr, - &class_attr_release.attr, + &attr_probe, + &attr_release, #endif &cpu_attrs[0].attr, &cpu_attrs[1].attr, -- cgit v1.2.3 From 52cf25d0ab7f78eeecc59ac652ed5090f69b619e Mon Sep 17 00:00:00 2001 From: Emese Revfy Date: Tue, 19 Jan 2010 02:58:23 +0100 Subject: Driver core: Constify struct sysfs_ops in struct kobj_type Constify struct sysfs_ops. This is part of the ops structure constification effort started by Arjan van de Ven et al. Benefits of this constification: * prevents modification of data that is shared (referenced) by many other structure instances at runtime * detects/prevents accidental (but not intentional) modification attempts on archs that enforce read-only kernel data at runtime * potentially better optimized code as the compiler can assume that the const data cannot be changed * the compiler/linker move const data into .rodata and therefore exclude them from false sharing Signed-off-by: Emese Revfy Acked-by: David Teigland Acked-by: Matt Domsch Acked-by: Maciej Sosnowski Acked-by: Hans J. Koch Acked-by: Pekka Enberg Acked-by: Jens Axboe Acked-by: Stephen Hemminger Signed-off-by: Greg Kroah-Hartman --- Documentation/kobject.txt | 2 +- arch/ia64/kernel/topology.c | 2 +- arch/powerpc/kernel/cacheinfo.c | 2 +- arch/sh/kernel/cpu/sh4/sq.c | 2 +- arch/x86/kernel/cpu/intel_cacheinfo.c | 2 +- arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +- block/blk-integrity.c | 2 +- block/blk-sysfs.c | 2 +- block/elevator.c | 2 +- drivers/base/bus.c | 4 ++-- drivers/base/class.c | 2 +- drivers/base/core.c | 2 +- drivers/base/sys.c | 4 ++-- drivers/block/pktcdvd.c | 2 +- drivers/cpufreq/cpufreq.c | 2 +- drivers/cpuidle/sysfs.c | 4 ++-- drivers/dma/ioat/dma.c | 2 +- drivers/dma/ioat/dma.h | 2 +- drivers/edac/edac_device_sysfs.c | 6 +++--- drivers/edac/edac_mc_sysfs.c | 4 ++-- drivers/edac/edac_pci_sysfs.c | 4 ++-- drivers/firmware/edd.c | 2 +- drivers/firmware/efivars.c | 2 +- drivers/firmware/iscsi_ibft.c | 2 +- drivers/firmware/memmap.c | 2 +- drivers/gpu/drm/ttm/ttm_bo.c | 2 +- drivers/gpu/drm/ttm/ttm_memory.c | 2 +- drivers/infiniband/core/cm.c | 2 +- drivers/infiniband/core/sysfs.c | 2 +- drivers/md/dm-sysfs.c | 2 +- drivers/md/md.c | 4 ++-- drivers/net/ibmveth.c | 2 +- drivers/net/iseries_veth.c | 4 ++-- drivers/parisc/pdc_stable.c | 2 +- drivers/pci/hotplug/fakephp.c | 2 +- drivers/pci/slot.c | 2 +- drivers/uio/uio.c | 4 ++-- drivers/uwb/wlp/sysfs.c | 3 +-- drivers/video/omap2/dss/manager.c | 2 +- drivers/video/omap2/dss/overlay.c | 2 +- drivers/xen/sys-hypervisor.c | 2 +- fs/btrfs/sysfs.c | 4 ++-- fs/dlm/lockspace.c | 2 +- fs/ext4/super.c | 2 +- fs/gfs2/sys.c | 2 +- fs/ocfs2/cluster/masklog.c | 2 +- fs/sysfs/file.c | 8 ++++---- include/linux/kobject.h | 4 ++-- kernel/params.c | 2 +- lib/kobject.c | 2 +- mm/slub.c | 2 +- net/bridge/br_private.h | 2 +- net/bridge/br_sysfs_if.c | 2 +- samples/kobject/kset-example.c | 2 +- 54 files changed, 69 insertions(+), 70 deletions(-) (limited to 'drivers') diff --git a/Documentation/kobject.txt b/Documentation/kobject.txt index c79ab996dada..bdb13817e1e9 100644 --- a/Documentation/kobject.txt +++ b/Documentation/kobject.txt @@ -266,7 +266,7 @@ kobj_type: struct kobj_type { void (*release)(struct kobject *); - struct sysfs_ops *sysfs_ops; + const struct sysfs_ops *sysfs_ops; struct attribute **default_attrs; }; diff --git a/arch/ia64/kernel/topology.c b/arch/ia64/kernel/topology.c index 8f060352e129..b3a5818088d9 100644 --- a/arch/ia64/kernel/topology.c +++ b/arch/ia64/kernel/topology.c @@ -282,7 +282,7 @@ static ssize_t cache_show(struct kobject * kobj, struct attribute * attr, char * return ret; } -static struct sysfs_ops cache_sysfs_ops = { +static const struct sysfs_ops cache_sysfs_ops = { .show = cache_show }; diff --git a/arch/powerpc/kernel/cacheinfo.c b/arch/powerpc/kernel/cacheinfo.c index bb37b1d19a58..01fe9ce28379 100644 --- a/arch/powerpc/kernel/cacheinfo.c +++ b/arch/powerpc/kernel/cacheinfo.c @@ -642,7 +642,7 @@ static struct kobj_attribute *cache_index_opt_attrs[] = { &cache_assoc_attr, }; -static struct sysfs_ops cache_index_ops = { +static const struct sysfs_ops cache_index_ops = { .show = cache_index_show, }; diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c index fc065f9da6e5..14726eef1ce0 100644 --- a/arch/sh/kernel/cpu/sh4/sq.c +++ b/arch/sh/kernel/cpu/sh4/sq.c @@ -326,7 +326,7 @@ static struct attribute *sq_sysfs_attrs[] = { NULL, }; -static struct sysfs_ops sq_sysfs_ops = { +static const struct sysfs_ops sq_sysfs_ops = { .show = sq_sysfs_show, .store = sq_sysfs_store, }; diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index eddb1bdd1b8f..b3eeb66c0a51 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -903,7 +903,7 @@ static ssize_t store(struct kobject *kobj, struct attribute *attr, return ret; } -static struct sysfs_ops sysfs_ops = { +static const struct sysfs_ops sysfs_ops = { .show = show, .store = store, }; diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 83a3d1f4efca..cda932ca3ade 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -388,7 +388,7 @@ static ssize_t store(struct kobject *kobj, struct attribute *attr, return ret; } -static struct sysfs_ops threshold_ops = { +static const struct sysfs_ops threshold_ops = { .show = show, .store = store, }; diff --git a/block/blk-integrity.c b/block/blk-integrity.c index 15c630813b1c..96e83c2bdb94 100644 --- a/block/blk-integrity.c +++ b/block/blk-integrity.c @@ -278,7 +278,7 @@ static struct attribute *integrity_attrs[] = { NULL, }; -static struct sysfs_ops integrity_ops = { +static const struct sysfs_ops integrity_ops = { .show = &integrity_attr_show, .store = &integrity_attr_store, }; diff --git a/block/blk-sysfs.c b/block/blk-sysfs.c index e85442415db3..2ae2cb3f362f 100644 --- a/block/blk-sysfs.c +++ b/block/blk-sysfs.c @@ -450,7 +450,7 @@ static void blk_release_queue(struct kobject *kobj) kmem_cache_free(blk_requestq_cachep, q); } -static struct sysfs_ops queue_sysfs_ops = { +static const struct sysfs_ops queue_sysfs_ops = { .show = queue_attr_show, .store = queue_attr_store, }; diff --git a/block/elevator.c b/block/elevator.c index ee3a883840f2..df75676f6671 100644 --- a/block/elevator.c +++ b/block/elevator.c @@ -892,7 +892,7 @@ elv_attr_store(struct kobject *kobj, struct attribute *attr, return error; } -static struct sysfs_ops elv_sysfs_ops = { +static const struct sysfs_ops elv_sysfs_ops = { .show = elv_attr_show, .store = elv_attr_store, }; diff --git a/drivers/base/bus.c b/drivers/base/bus.c index 2afe599eb35d..cca1aa10054c 100644 --- a/drivers/base/bus.c +++ b/drivers/base/bus.c @@ -70,7 +70,7 @@ static ssize_t drv_attr_store(struct kobject *kobj, struct attribute *attr, return ret; } -static struct sysfs_ops driver_sysfs_ops = { +static const struct sysfs_ops driver_sysfs_ops = { .show = drv_attr_show, .store = drv_attr_store, }; @@ -115,7 +115,7 @@ static ssize_t bus_attr_store(struct kobject *kobj, struct attribute *attr, return ret; } -static struct sysfs_ops bus_sysfs_ops = { +static const struct sysfs_ops bus_sysfs_ops = { .show = bus_attr_show, .store = bus_attr_store, }; diff --git a/drivers/base/class.c b/drivers/base/class.c index 2e297cc4cd3d..0147f476b8a9 100644 --- a/drivers/base/class.c +++ b/drivers/base/class.c @@ -63,7 +63,7 @@ static void class_release(struct kobject *kobj) kfree(cp); } -static struct sysfs_ops class_sysfs_ops = { +static const struct sysfs_ops class_sysfs_ops = { .show = class_attr_show, .store = class_attr_store, }; diff --git a/drivers/base/core.c b/drivers/base/core.c index 58ec1069f4b0..b0d6646a2814 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -100,7 +100,7 @@ static ssize_t dev_attr_store(struct kobject *kobj, struct attribute *attr, return ret; } -static struct sysfs_ops dev_sysfs_ops = { +static const struct sysfs_ops dev_sysfs_ops = { .show = dev_attr_show, .store = dev_attr_store, }; diff --git a/drivers/base/sys.c b/drivers/base/sys.c index 747c99e0568b..8980feec5d14 100644 --- a/drivers/base/sys.c +++ b/drivers/base/sys.c @@ -54,7 +54,7 @@ sysdev_store(struct kobject *kobj, struct attribute *attr, return -EIO; } -static struct sysfs_ops sysfs_ops = { +static const struct sysfs_ops sysfs_ops = { .show = sysdev_show, .store = sysdev_store, }; @@ -104,7 +104,7 @@ static ssize_t sysdev_class_store(struct kobject *kobj, struct attribute *attr, return -EIO; } -static struct sysfs_ops sysfs_class_ops = { +static const struct sysfs_ops sysfs_class_ops = { .show = sysdev_class_show, .store = sysdev_class_store, }; diff --git a/drivers/block/pktcdvd.c b/drivers/block/pktcdvd.c index 73d815d3f1b2..39c8514442eb 100644 --- a/drivers/block/pktcdvd.c +++ b/drivers/block/pktcdvd.c @@ -284,7 +284,7 @@ static ssize_t kobj_pkt_store(struct kobject *kobj, return len; } -static struct sysfs_ops kobj_pkt_ops = { +static const struct sysfs_ops kobj_pkt_ops = { .show = kobj_pkt_show, .store = kobj_pkt_store }; diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 67bc2ece7b4b..2d5d575e889d 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -766,7 +766,7 @@ static void cpufreq_sysfs_release(struct kobject *kobj) complete(&policy->kobj_unregister); } -static struct sysfs_ops sysfs_ops = { +static const struct sysfs_ops sysfs_ops = { .show = show, .store = store, }; diff --git a/drivers/cpuidle/sysfs.c b/drivers/cpuidle/sysfs.c index c9cefacabf37..8719b36e1a4d 100644 --- a/drivers/cpuidle/sysfs.c +++ b/drivers/cpuidle/sysfs.c @@ -195,7 +195,7 @@ static ssize_t cpuidle_store(struct kobject * kobj, struct attribute * attr, return ret; } -static struct sysfs_ops cpuidle_sysfs_ops = { +static const struct sysfs_ops cpuidle_sysfs_ops = { .show = cpuidle_show, .store = cpuidle_store, }; @@ -281,7 +281,7 @@ static ssize_t cpuidle_state_show(struct kobject * kobj, return ret; } -static struct sysfs_ops cpuidle_state_sysfs_ops = { +static const struct sysfs_ops cpuidle_state_sysfs_ops = { .show = cpuidle_state_show, }; diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index af14c9a5b8d4..0099340b9616 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -1138,7 +1138,7 @@ ioat_attr_show(struct kobject *kobj, struct attribute *attr, char *page) return entry->show(&chan->common, page); } -struct sysfs_ops ioat_sysfs_ops = { +const struct sysfs_ops ioat_sysfs_ops = { .show = ioat_attr_show, }; diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index 4f747a254074..86b97ac8774e 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -346,7 +346,7 @@ bool ioat_cleanup_preamble(struct ioat_chan_common *chan, unsigned long *phys_complete); void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type); void ioat_kobject_del(struct ioatdma_device *device); -extern struct sysfs_ops ioat_sysfs_ops; +extern const struct sysfs_ops ioat_sysfs_ops; extern struct ioat_sysfs_entry ioat_version_attr; extern struct ioat_sysfs_entry ioat_cap_attr; #endif /* IOATDMA_H */ diff --git a/drivers/edac/edac_device_sysfs.c b/drivers/edac/edac_device_sysfs.c index 53764577035f..5fdedbc0f545 100644 --- a/drivers/edac/edac_device_sysfs.c +++ b/drivers/edac/edac_device_sysfs.c @@ -137,7 +137,7 @@ static ssize_t edac_dev_ctl_info_store(struct kobject *kobj, } /* edac_dev file operations for an 'ctl_info' */ -static struct sysfs_ops device_ctl_info_ops = { +static const struct sysfs_ops device_ctl_info_ops = { .show = edac_dev_ctl_info_show, .store = edac_dev_ctl_info_store }; @@ -373,7 +373,7 @@ static ssize_t edac_dev_instance_store(struct kobject *kobj, } /* edac_dev file operations for an 'instance' */ -static struct sysfs_ops device_instance_ops = { +static const struct sysfs_ops device_instance_ops = { .show = edac_dev_instance_show, .store = edac_dev_instance_store }; @@ -476,7 +476,7 @@ static ssize_t edac_dev_block_store(struct kobject *kobj, } /* edac_dev file operations for a 'block' */ -static struct sysfs_ops device_block_ops = { +static const struct sysfs_ops device_block_ops = { .show = edac_dev_block_show, .store = edac_dev_block_store }; diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c index e1d4ce083481..88840e9fa3e0 100644 --- a/drivers/edac/edac_mc_sysfs.c +++ b/drivers/edac/edac_mc_sysfs.c @@ -245,7 +245,7 @@ static ssize_t csrowdev_store(struct kobject *kobj, struct attribute *attr, return -EIO; } -static struct sysfs_ops csrowfs_ops = { +static const struct sysfs_ops csrowfs_ops = { .show = csrowdev_show, .store = csrowdev_store }; @@ -575,7 +575,7 @@ static ssize_t mcidev_store(struct kobject *kobj, struct attribute *attr, } /* Intermediate show/store table */ -static struct sysfs_ops mci_ops = { +static const struct sysfs_ops mci_ops = { .show = mcidev_show, .store = mcidev_store }; diff --git a/drivers/edac/edac_pci_sysfs.c b/drivers/edac/edac_pci_sysfs.c index fb60a877d768..bef94e3d9944 100644 --- a/drivers/edac/edac_pci_sysfs.c +++ b/drivers/edac/edac_pci_sysfs.c @@ -121,7 +121,7 @@ static ssize_t edac_pci_instance_store(struct kobject *kobj, } /* fs_ops table */ -static struct sysfs_ops pci_instance_ops = { +static const struct sysfs_ops pci_instance_ops = { .show = edac_pci_instance_show, .store = edac_pci_instance_store }; @@ -261,7 +261,7 @@ static ssize_t edac_pci_dev_store(struct kobject *kobj, return -EIO; } -static struct sysfs_ops edac_pci_sysfs_ops = { +static const struct sysfs_ops edac_pci_sysfs_ops = { .show = edac_pci_dev_show, .store = edac_pci_dev_store }; diff --git a/drivers/firmware/edd.c b/drivers/firmware/edd.c index 9e4f59dc7f1e..110e24e50883 100644 --- a/drivers/firmware/edd.c +++ b/drivers/firmware/edd.c @@ -122,7 +122,7 @@ edd_attr_show(struct kobject * kobj, struct attribute *attr, char *buf) return ret; } -static struct sysfs_ops edd_attr_ops = { +static const struct sysfs_ops edd_attr_ops = { .show = edd_attr_show, }; diff --git a/drivers/firmware/efivars.c b/drivers/firmware/efivars.c index f4f709d1370b..082f06ecd327 100644 --- a/drivers/firmware/efivars.c +++ b/drivers/firmware/efivars.c @@ -362,7 +362,7 @@ static ssize_t efivar_attr_store(struct kobject *kobj, struct attribute *attr, return ret; } -static struct sysfs_ops efivar_attr_ops = { +static const struct sysfs_ops efivar_attr_ops = { .show = efivar_attr_show, .store = efivar_attr_store, }; diff --git a/drivers/firmware/iscsi_ibft.c b/drivers/firmware/iscsi_ibft.c index a3600e3ed0fa..ed2801c378de 100644 --- a/drivers/firmware/iscsi_ibft.c +++ b/drivers/firmware/iscsi_ibft.c @@ -519,7 +519,7 @@ static ssize_t ibft_show_attribute(struct kobject *kobj, return ret; } -static struct sysfs_ops ibft_attr_ops = { +static const struct sysfs_ops ibft_attr_ops = { .show = ibft_show_attribute, }; diff --git a/drivers/firmware/memmap.c b/drivers/firmware/memmap.c index 20f645743ead..d59f7cad2269 100644 --- a/drivers/firmware/memmap.c +++ b/drivers/firmware/memmap.c @@ -74,7 +74,7 @@ static struct attribute *def_attrs[] = { NULL }; -static struct sysfs_ops memmap_attr_ops = { +static const struct sysfs_ops memmap_attr_ops = { .show = memmap_attr_show, }; diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index c7320ce4567d..89c38c49066f 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -128,7 +128,7 @@ static struct attribute *ttm_bo_global_attrs[] = { NULL }; -static struct sysfs_ops ttm_bo_global_ops = { +static const struct sysfs_ops ttm_bo_global_ops = { .show = &ttm_bo_global_show }; diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c index f5245c02b8fd..eb143e04d402 100644 --- a/drivers/gpu/drm/ttm/ttm_memory.c +++ b/drivers/gpu/drm/ttm/ttm_memory.c @@ -152,7 +152,7 @@ static struct attribute *ttm_mem_zone_attrs[] = { NULL }; -static struct sysfs_ops ttm_mem_zone_ops = { +static const struct sysfs_ops ttm_mem_zone_ops = { .show = &ttm_mem_zone_show, .store = &ttm_mem_zone_store }; diff --git a/drivers/infiniband/core/cm.c b/drivers/infiniband/core/cm.c index 5130fc55b8e2..764787ebe8d8 100644 --- a/drivers/infiniband/core/cm.c +++ b/drivers/infiniband/core/cm.c @@ -3597,7 +3597,7 @@ static ssize_t cm_show_counter(struct kobject *obj, struct attribute *attr, atomic_long_read(&group->counter[cm_attr->index])); } -static struct sysfs_ops cm_counter_ops = { +static const struct sysfs_ops cm_counter_ops = { .show = cm_show_counter }; diff --git a/drivers/infiniband/core/sysfs.c b/drivers/infiniband/core/sysfs.c index 158a214da2f7..1558bb7fc74d 100644 --- a/drivers/infiniband/core/sysfs.c +++ b/drivers/infiniband/core/sysfs.c @@ -79,7 +79,7 @@ static ssize_t port_attr_show(struct kobject *kobj, return port_attr->show(p, port_attr, buf); } -static struct sysfs_ops port_sysfs_ops = { +static const struct sysfs_ops port_sysfs_ops = { .show = port_attr_show }; diff --git a/drivers/md/dm-sysfs.c b/drivers/md/dm-sysfs.c index f91b40942e07..84d2b91e4efb 100644 --- a/drivers/md/dm-sysfs.c +++ b/drivers/md/dm-sysfs.c @@ -75,7 +75,7 @@ static struct attribute *dm_attrs[] = { NULL, }; -static struct sysfs_ops dm_sysfs_ops = { +static const struct sysfs_ops dm_sysfs_ops = { .show = dm_attr_show, }; diff --git a/drivers/md/md.c b/drivers/md/md.c index a20a71e5efd3..fdc1890b6ac5 100644 --- a/drivers/md/md.c +++ b/drivers/md/md.c @@ -2642,7 +2642,7 @@ static void rdev_free(struct kobject *ko) mdk_rdev_t *rdev = container_of(ko, mdk_rdev_t, kobj); kfree(rdev); } -static struct sysfs_ops rdev_sysfs_ops = { +static const struct sysfs_ops rdev_sysfs_ops = { .show = rdev_attr_show, .store = rdev_attr_store, }; @@ -4059,7 +4059,7 @@ static void md_free(struct kobject *ko) kfree(mddev); } -static struct sysfs_ops md_sysfs_ops = { +static const struct sysfs_ops md_sysfs_ops = { .show = md_attr_show, .store = md_attr_store, }; diff --git a/drivers/net/ibmveth.c b/drivers/net/ibmveth.c index f2b937966950..0bc777bac9b4 100644 --- a/drivers/net/ibmveth.c +++ b/drivers/net/ibmveth.c @@ -1577,7 +1577,7 @@ static struct attribute * veth_pool_attrs[] = { NULL, }; -static struct sysfs_ops veth_pool_ops = { +static const struct sysfs_ops veth_pool_ops = { .show = veth_pool_show, .store = veth_pool_store, }; diff --git a/drivers/net/iseries_veth.c b/drivers/net/iseries_veth.c index 966de5d69521..e6e972d9b7ca 100644 --- a/drivers/net/iseries_veth.c +++ b/drivers/net/iseries_veth.c @@ -384,7 +384,7 @@ static struct attribute *veth_cnx_default_attrs[] = { NULL }; -static struct sysfs_ops veth_cnx_sysfs_ops = { +static const struct sysfs_ops veth_cnx_sysfs_ops = { .show = veth_cnx_attribute_show }; @@ -441,7 +441,7 @@ static struct attribute *veth_port_default_attrs[] = { NULL }; -static struct sysfs_ops veth_port_sysfs_ops = { +static const struct sysfs_ops veth_port_sysfs_ops = { .show = veth_port_attribute_show }; diff --git a/drivers/parisc/pdc_stable.c b/drivers/parisc/pdc_stable.c index 0bc5d474b168..1062b8ffe244 100644 --- a/drivers/parisc/pdc_stable.c +++ b/drivers/parisc/pdc_stable.c @@ -481,7 +481,7 @@ pdcspath_attr_store(struct kobject *kobj, struct attribute *attr, return ret; } -static struct sysfs_ops pdcspath_attr_ops = { +static const struct sysfs_ops pdcspath_attr_ops = { .show = pdcspath_attr_show, .store = pdcspath_attr_store, }; diff --git a/drivers/pci/hotplug/fakephp.c b/drivers/pci/hotplug/fakephp.c index 6151389fd903..0a894efd4b9b 100644 --- a/drivers/pci/hotplug/fakephp.c +++ b/drivers/pci/hotplug/fakephp.c @@ -73,7 +73,7 @@ static void legacy_release(struct kobject *kobj) } static struct kobj_type legacy_ktype = { - .sysfs_ops = &(struct sysfs_ops){ + .sysfs_ops = &(const struct sysfs_ops){ .store = legacy_store, .show = legacy_show }, .release = &legacy_release, diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c index 49c9e6c9779a..f75a44d37fbe 100644 --- a/drivers/pci/slot.c +++ b/drivers/pci/slot.c @@ -29,7 +29,7 @@ static ssize_t pci_slot_attr_store(struct kobject *kobj, return attribute->store ? attribute->store(slot, buf, len) : -EIO; } -static struct sysfs_ops pci_slot_sysfs_ops = { +static const struct sysfs_ops pci_slot_sysfs_ops = { .show = pci_slot_attr_show, .store = pci_slot_attr_store, }; diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c index e941367dd28f..4de382acd8f2 100644 --- a/drivers/uio/uio.c +++ b/drivers/uio/uio.c @@ -129,7 +129,7 @@ static ssize_t map_type_show(struct kobject *kobj, struct attribute *attr, return entry->show(mem, buf); } -static struct sysfs_ops map_sysfs_ops = { +static const struct sysfs_ops map_sysfs_ops = { .show = map_type_show, }; @@ -217,7 +217,7 @@ static ssize_t portio_type_show(struct kobject *kobj, struct attribute *attr, return entry->show(port, buf); } -static struct sysfs_ops portio_sysfs_ops = { +static const struct sysfs_ops portio_sysfs_ops = { .show = portio_type_show, }; diff --git a/drivers/uwb/wlp/sysfs.c b/drivers/uwb/wlp/sysfs.c index 0370399ff4bb..6627c94cc854 100644 --- a/drivers/uwb/wlp/sysfs.c +++ b/drivers/uwb/wlp/sysfs.c @@ -615,8 +615,7 @@ ssize_t wlp_wss_attr_store(struct kobject *kobj, struct attribute *attr, return ret; } -static -struct sysfs_ops wss_sysfs_ops = { +static const struct sysfs_ops wss_sysfs_ops = { .show = wlp_wss_attr_show, .store = wlp_wss_attr_store, }; diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c index 913142d4cab1..9acef00c47ea 100644 --- a/drivers/video/omap2/dss/manager.c +++ b/drivers/video/omap2/dss/manager.c @@ -341,7 +341,7 @@ static ssize_t manager_attr_store(struct kobject *kobj, struct attribute *attr, return manager_attr->store(manager, buf, size); } -static struct sysfs_ops manager_sysfs_ops = { +static const struct sysfs_ops manager_sysfs_ops = { .show = manager_attr_show, .store = manager_attr_store, }; diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c index 0c5bea263ac6..aed3f3194347 100644 --- a/drivers/video/omap2/dss/overlay.c +++ b/drivers/video/omap2/dss/overlay.c @@ -320,7 +320,7 @@ static ssize_t overlay_attr_store(struct kobject *kobj, struct attribute *attr, return overlay_attr->store(overlay, buf, size); } -static struct sysfs_ops overlay_sysfs_ops = { +static const struct sysfs_ops overlay_sysfs_ops = { .show = overlay_attr_show, .store = overlay_attr_store, }; diff --git a/drivers/xen/sys-hypervisor.c b/drivers/xen/sys-hypervisor.c index ae5cb05a1a1c..bb71ab2336c8 100644 --- a/drivers/xen/sys-hypervisor.c +++ b/drivers/xen/sys-hypervisor.c @@ -426,7 +426,7 @@ static ssize_t hyp_sysfs_store(struct kobject *kobj, return 0; } -static struct sysfs_ops hyp_sysfs_ops = { +static const struct sysfs_ops hyp_sysfs_ops = { .show = hyp_sysfs_show, .store = hyp_sysfs_store, }; diff --git a/fs/btrfs/sysfs.c b/fs/btrfs/sysfs.c index a240b6fa81df..4ce16ef702a3 100644 --- a/fs/btrfs/sysfs.c +++ b/fs/btrfs/sysfs.c @@ -164,12 +164,12 @@ static void btrfs_root_release(struct kobject *kobj) complete(&root->kobj_unregister); } -static struct sysfs_ops btrfs_super_attr_ops = { +static const struct sysfs_ops btrfs_super_attr_ops = { .show = btrfs_super_attr_show, .store = btrfs_super_attr_store, }; -static struct sysfs_ops btrfs_root_attr_ops = { +static const struct sysfs_ops btrfs_root_attr_ops = { .show = btrfs_root_attr_show, .store = btrfs_root_attr_store, }; diff --git a/fs/dlm/lockspace.c b/fs/dlm/lockspace.c index 26a8bd40400a..f994a7dfda85 100644 --- a/fs/dlm/lockspace.c +++ b/fs/dlm/lockspace.c @@ -148,7 +148,7 @@ static void lockspace_kobj_release(struct kobject *k) kfree(ls); } -static struct sysfs_ops dlm_attr_ops = { +static const struct sysfs_ops dlm_attr_ops = { .show = dlm_attr_show, .store = dlm_attr_store, }; diff --git a/fs/ext4/super.c b/fs/ext4/super.c index 2b83b96cb2eb..ce84a6ed4a48 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -2358,7 +2358,7 @@ static void ext4_sb_release(struct kobject *kobj) } -static struct sysfs_ops ext4_attr_ops = { +static const struct sysfs_ops ext4_attr_ops = { .show = ext4_attr_show, .store = ext4_attr_store, }; diff --git a/fs/gfs2/sys.c b/fs/gfs2/sys.c index 543503010ed0..419042f7f0b6 100644 --- a/fs/gfs2/sys.c +++ b/fs/gfs2/sys.c @@ -49,7 +49,7 @@ static ssize_t gfs2_attr_store(struct kobject *kobj, struct attribute *attr, return a->store ? a->store(sdp, buf, len) : len; } -static struct sysfs_ops gfs2_attr_ops = { +static const struct sysfs_ops gfs2_attr_ops = { .show = gfs2_attr_show, .store = gfs2_attr_store, }; diff --git a/fs/ocfs2/cluster/masklog.c b/fs/ocfs2/cluster/masklog.c index b39da877b12f..3bb928a2bf7d 100644 --- a/fs/ocfs2/cluster/masklog.c +++ b/fs/ocfs2/cluster/masklog.c @@ -136,7 +136,7 @@ static ssize_t mlog_store(struct kobject *obj, struct attribute *attr, return mlog_mask_store(mlog_attr->mask, buf, count); } -static struct sysfs_ops mlog_attr_ops = { +static const struct sysfs_ops mlog_attr_ops = { .show = mlog_show, .store = mlog_store, }; diff --git a/fs/sysfs/file.c b/fs/sysfs/file.c index 50b725bcc3f3..ced2299f1c9a 100644 --- a/fs/sysfs/file.c +++ b/fs/sysfs/file.c @@ -53,7 +53,7 @@ struct sysfs_buffer { size_t count; loff_t pos; char * page; - struct sysfs_ops * ops; + const struct sysfs_ops * ops; struct mutex mutex; int needs_read_fill; int event; @@ -75,7 +75,7 @@ static int fill_read_buffer(struct dentry * dentry, struct sysfs_buffer * buffer { struct sysfs_dirent *attr_sd = dentry->d_fsdata; struct kobject *kobj = attr_sd->s_parent->s_dir.kobj; - struct sysfs_ops * ops = buffer->ops; + const struct sysfs_ops * ops = buffer->ops; int ret = 0; ssize_t count; @@ -199,7 +199,7 @@ flush_write_buffer(struct dentry * dentry, struct sysfs_buffer * buffer, size_t { struct sysfs_dirent *attr_sd = dentry->d_fsdata; struct kobject *kobj = attr_sd->s_parent->s_dir.kobj; - struct sysfs_ops * ops = buffer->ops; + const struct sysfs_ops * ops = buffer->ops; int rc; /* need attr_sd for attr and ops, its parent for kobj */ @@ -335,7 +335,7 @@ static int sysfs_open_file(struct inode *inode, struct file *file) struct sysfs_dirent *attr_sd = file->f_path.dentry->d_fsdata; struct kobject *kobj = attr_sd->s_parent->s_dir.kobj; struct sysfs_buffer *buffer; - struct sysfs_ops *ops; + const struct sysfs_ops *ops; int error = -EACCES; char *p; diff --git a/include/linux/kobject.h b/include/linux/kobject.h index 57a1eaae9096..3950d3c2850d 100644 --- a/include/linux/kobject.h +++ b/include/linux/kobject.h @@ -106,7 +106,7 @@ extern char *kobject_get_path(struct kobject *kobj, gfp_t flag); struct kobj_type { void (*release)(struct kobject *kobj); - struct sysfs_ops *sysfs_ops; + const struct sysfs_ops *sysfs_ops; struct attribute **default_attrs; }; @@ -132,7 +132,7 @@ struct kobj_attribute { const char *buf, size_t count); }; -extern struct sysfs_ops kobj_sysfs_ops; +extern const struct sysfs_ops kobj_sysfs_ops; /** * struct kset - a set of kobjects of a specific type, belonging to a specific subsystem. diff --git a/kernel/params.c b/kernel/params.c index 48370be3c0a1..68396d73c838 100644 --- a/kernel/params.c +++ b/kernel/params.c @@ -722,7 +722,7 @@ static ssize_t module_attr_store(struct kobject *kobj, return ret; } -static struct sysfs_ops module_sysfs_ops = { +static const struct sysfs_ops module_sysfs_ops = { .show = module_attr_show, .store = module_attr_store, }; diff --git a/lib/kobject.c b/lib/kobject.c index cecf5a0ef6e1..8115eb1bbf4d 100644 --- a/lib/kobject.c +++ b/lib/kobject.c @@ -700,7 +700,7 @@ static ssize_t kobj_attr_store(struct kobject *kobj, struct attribute *attr, return ret; } -struct sysfs_ops kobj_sysfs_ops = { +const struct sysfs_ops kobj_sysfs_ops = { .show = kobj_attr_show, .store = kobj_attr_store, }; diff --git a/mm/slub.c b/mm/slub.c index a26753c12dcd..a2b8969ba6d0 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -4390,7 +4390,7 @@ static void kmem_cache_release(struct kobject *kobj) kfree(s); } -static struct sysfs_ops slab_sysfs_ops = { +static const struct sysfs_ops slab_sysfs_ops = { .show = slab_attr_show, .store = slab_attr_store, }; diff --git a/net/bridge/br_private.h b/net/bridge/br_private.h index 1cf2cef78584..fef0384e3c0b 100644 --- a/net/bridge/br_private.h +++ b/net/bridge/br_private.h @@ -423,7 +423,7 @@ extern void br_ifinfo_notify(int event, struct net_bridge_port *port); #ifdef CONFIG_SYSFS /* br_sysfs_if.c */ -extern struct sysfs_ops brport_sysfs_ops; +extern const struct sysfs_ops brport_sysfs_ops; extern int br_sysfs_addif(struct net_bridge_port *p); /* br_sysfs_br.c */ diff --git a/net/bridge/br_sysfs_if.c b/net/bridge/br_sysfs_if.c index 696596cd3384..0b9916489d6b 100644 --- a/net/bridge/br_sysfs_if.c +++ b/net/bridge/br_sysfs_if.c @@ -238,7 +238,7 @@ static ssize_t brport_store(struct kobject * kobj, return ret; } -struct sysfs_ops brport_sysfs_ops = { +const struct sysfs_ops brport_sysfs_ops = { .show = brport_show, .store = brport_store, }; diff --git a/samples/kobject/kset-example.c b/samples/kobject/kset-example.c index 7c6088140528..3b126d1f8599 100644 --- a/samples/kobject/kset-example.c +++ b/samples/kobject/kset-example.c @@ -87,7 +87,7 @@ static ssize_t foo_attr_store(struct kobject *kobj, } /* Our custom sysfs_ops that we will associate with our ktype later on */ -static struct sysfs_ops foo_sysfs_ops = { +static const struct sysfs_ops foo_sysfs_ops = { .show = foo_attr_show, .store = foo_attr_store, }; -- cgit v1.2.3 From 831fad2f75f0d7bfc339de81173e7068a3c72276 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 26 Jan 2010 09:35:00 +0100 Subject: Driver core: make struct platform_driver.id_table const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes a warning on several pxa based machines: arch/arm/mach-pxa/ssp.c:475: warning: initialization discards qualifiers from pointer target type Signed-off-by: Uwe Kleine-König Acked-by: Vikram Dhillon Acked-by: Eric Miao Signed-off-by: Greg Kroah-Hartman --- drivers/base/platform.c | 2 +- include/linux/platform_device.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 937d58021d1b..575e08bc6630 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -636,7 +636,7 @@ static int platform_uevent(struct device *dev, struct kobj_uevent_env *env) } static const struct platform_device_id *platform_match_id( - struct platform_device_id *id, + const struct platform_device_id *id, struct platform_device *pdev) { while (id->name[0]) { diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index 2c2d035bfb92..212da17d06af 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -62,7 +62,7 @@ struct platform_driver { int (*suspend)(struct platform_device *, pm_message_t state); int (*resume)(struct platform_device *); struct device_driver driver; - struct platform_device_id *id_table; + const struct platform_device_id *id_table; }; extern int platform_driver_register(struct platform_driver *); -- cgit v1.2.3 From 1b07193b34c1bc1c184e2d53a62633a73ea9b0a0 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 4 Feb 2010 20:56:50 +0100 Subject: platform-drivers: move probe to .devinit.text in drivers/scsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A pointer to a probe callback is passed to the core via platform_driver_register and so the function must not disappear when the .init sections are discarded. Otherwise (if also having HOTPLUG=y) unbinding and binding a device to the driver via sysfs will result in an oops as does a device being registered late. An alternative to this patch is using platform_driver_probe instead of platform_driver_register plus removing the pointer to the probe function from the struct platform_driver. Signed-off-by: Uwe Kleine-König Cc: Andrew Morton Cc: David Brownell Cc: Dmitri Vorobiev Cc: Henrik Kretzschmar Cc: James Bottomley Cc: Kay Sievers Cc: peter fuerst Cc: Thomas Bogendoerfer Acked-by: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/sgiwd93.c | 2 +- drivers/scsi/sni_53c710.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/sgiwd93.c b/drivers/scsi/sgiwd93.c index 0807b260268b..fef0e3c75b16 100644 --- a/drivers/scsi/sgiwd93.c +++ b/drivers/scsi/sgiwd93.c @@ -226,7 +226,7 @@ static struct scsi_host_template sgiwd93_template = { .use_clustering = DISABLE_CLUSTERING, }; -static int __init sgiwd93_probe(struct platform_device *pdev) +static int __devinit sgiwd93_probe(struct platform_device *pdev) { struct sgiwd93_platform_data *pd = pdev->dev.platform_data; unsigned char *wdregs = pd->wdregs; diff --git a/drivers/scsi/sni_53c710.c b/drivers/scsi/sni_53c710.c index 37b3359e863e..56cf0bb4ed1f 100644 --- a/drivers/scsi/sni_53c710.c +++ b/drivers/scsi/sni_53c710.c @@ -64,7 +64,7 @@ static struct scsi_host_template snirm710_template = { .module = THIS_MODULE, }; -static int __init snirm710_probe(struct platform_device *dev) +static int __devinit snirm710_probe(struct platform_device *dev) { unsigned long base; struct NCR_700_Host_Parameters *hostdata; -- cgit v1.2.3 From c2e13037e6794bd0d9de3f9ecabf5615f15c160b Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 4 Feb 2010 20:56:51 +0100 Subject: platform-drivers: move probe to .devinit.text in drivers/video MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A pointer to a probe callback is passed to the core via platform_driver_register and so the function must not disappear when the .init sections are discarded. Otherwise (if also having HOTPLUG=y) unbinding and binding a device to the driver via sysfs will result in an oops as does a device being registered late. An alternative to this patch is using platform_driver_probe instead of platform_driver_register plus removing the pointer to the probe function from the struct platform_driver. Signed-off-by: Uwe Kleine-König Cc: Adrian Bunk Cc: Alberto Mardegan Cc: Andrew Morton Cc: Andriy Skulysh Cc: Antonino Daplas Cc: Anton Vorontsov Cc: Ben Dooks Cc: Chandramouli Narayanan Cc: Christoph Hellwig Cc: Frans Pop Cc: Geert Uytterhoeven Cc: Greg Kroah-Hartman Cc: Helge Deller Cc: Huang Ying Cc: Ian Molton Cc: Joshua Kinard Cc: Kaj-Michael Lang Cc: Krzysztof Helt Cc: linux-fbdev-devel@lists.sourceforge.net Cc: Maciej W. Rozycki Cc: Magnus Damm Cc: Martin Michlmayr Cc: Matthias Kaehlcke Cc: Paul Mundt Cc: Pavel Machek Cc: Philipp Zabel Cc: Richard Purdie Cc: Roel Kluin Cc: Roland Stigge Cc: Russell King Cc: Thomas Bogendoerfer Cc: Vincent Sanders Cc: Yoichi Yuasa Acked-by: Ralf Baechle Acked-by: Arnaud Patard Acked-by: James Simmons Acked-by: Peter Jones Acked-by: Jaya Kumar Signed-off-by: Greg Kroah-Hartman --- drivers/video/acornfb.c | 2 +- drivers/video/arcfb.c | 2 +- drivers/video/cobalt_lcdfb.c | 2 +- drivers/video/efifb.c | 2 +- drivers/video/epson1355fb.c | 2 +- drivers/video/gbefb.c | 2 +- drivers/video/hgafb.c | 2 +- drivers/video/hitfb.c | 2 +- drivers/video/q40fb.c | 2 +- drivers/video/s3c2410fb.c | 4 ++-- drivers/video/sa1100fb.c | 2 +- drivers/video/sgivwfb.c | 2 +- drivers/video/sh_mobile_lcdcfb.c | 2 +- drivers/video/vesafb.c | 2 +- drivers/video/vfb.c | 2 +- drivers/video/vga16fb.c | 2 +- drivers/video/w100fb.c | 2 +- 17 files changed, 18 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/video/acornfb.c b/drivers/video/acornfb.c index 0bcc59eb37fa..43d7d5067361 100644 --- a/drivers/video/acornfb.c +++ b/drivers/video/acornfb.c @@ -1221,7 +1221,7 @@ free_unused_pages(unsigned int virtual_start, unsigned int virtual_end) printk("acornfb: freed %dK memory\n", mb_freed); } -static int __init acornfb_probe(struct platform_device *dev) +static int __devinit acornfb_probe(struct platform_device *dev) { unsigned long size; u_int h_sync, v_sync; diff --git a/drivers/video/arcfb.c b/drivers/video/arcfb.c index c3431691c9f2..01554d696528 100644 --- a/drivers/video/arcfb.c +++ b/drivers/video/arcfb.c @@ -504,7 +504,7 @@ static struct fb_ops arcfb_ops = { .fb_ioctl = arcfb_ioctl, }; -static int __init arcfb_probe(struct platform_device *dev) +static int __devinit arcfb_probe(struct platform_device *dev) { struct fb_info *info; int retval = -ENOMEM; diff --git a/drivers/video/cobalt_lcdfb.c b/drivers/video/cobalt_lcdfb.c index 108b89e09a80..5eb61b5adfe8 100644 --- a/drivers/video/cobalt_lcdfb.c +++ b/drivers/video/cobalt_lcdfb.c @@ -287,7 +287,7 @@ static struct fb_ops cobalt_lcd_fbops = { .fb_cursor = cobalt_lcdfb_cursor, }; -static int __init cobalt_lcdfb_probe(struct platform_device *dev) +static int __devinit cobalt_lcdfb_probe(struct platform_device *dev) { struct fb_info *info; struct resource *res; diff --git a/drivers/video/efifb.c b/drivers/video/efifb.c index d25df51bb0d2..581d2dbf675a 100644 --- a/drivers/video/efifb.c +++ b/drivers/video/efifb.c @@ -210,7 +210,7 @@ static int __init efifb_setup(char *options) return 0; } -static int __init efifb_probe(struct platform_device *dev) +static int __devinit efifb_probe(struct platform_device *dev) { struct fb_info *info; int err; diff --git a/drivers/video/epson1355fb.c b/drivers/video/epson1355fb.c index 2735b79e52a1..6d755bb3a2bc 100644 --- a/drivers/video/epson1355fb.c +++ b/drivers/video/epson1355fb.c @@ -602,7 +602,7 @@ static int epson1355fb_remove(struct platform_device *dev) return 0; } -int __init epson1355fb_probe(struct platform_device *dev) +int __devinit epson1355fb_probe(struct platform_device *dev) { struct epson1355_par *default_par; struct fb_info *info; diff --git a/drivers/video/gbefb.c b/drivers/video/gbefb.c index 695fa013fe7e..5643a35c1746 100644 --- a/drivers/video/gbefb.c +++ b/drivers/video/gbefb.c @@ -1128,7 +1128,7 @@ static int __init gbefb_setup(char *options) return 0; } -static int __init gbefb_probe(struct platform_device *p_dev) +static int __devinit gbefb_probe(struct platform_device *p_dev) { int i, ret = 0; struct fb_info *info; diff --git a/drivers/video/hgafb.c b/drivers/video/hgafb.c index 0129c044f6d6..db9b785b56eb 100644 --- a/drivers/video/hgafb.c +++ b/drivers/video/hgafb.c @@ -551,7 +551,7 @@ static struct fb_ops hgafb_ops = { * Initialization */ -static int __init hgafb_probe(struct platform_device *pdev) +static int __devinit hgafb_probe(struct platform_device *pdev) { struct fb_info *info; diff --git a/drivers/video/hitfb.c b/drivers/video/hitfb.c index 73c83a8de2d3..bf78779199c6 100644 --- a/drivers/video/hitfb.c +++ b/drivers/video/hitfb.c @@ -325,7 +325,7 @@ static struct fb_ops hitfb_ops = { .fb_imageblit = cfb_imageblit, }; -static int __init hitfb_probe(struct platform_device *dev) +static int __devinit hitfb_probe(struct platform_device *dev) { unsigned short lcdclor, ldr3, ldvndr; struct fb_info *info; diff --git a/drivers/video/q40fb.c b/drivers/video/q40fb.c index 4beac1df617b..de40a626dc76 100644 --- a/drivers/video/q40fb.c +++ b/drivers/video/q40fb.c @@ -85,7 +85,7 @@ static struct fb_ops q40fb_ops = { .fb_imageblit = cfb_imageblit, }; -static int __init q40fb_probe(struct platform_device *dev) +static int __devinit q40fb_probe(struct platform_device *dev) { struct fb_info *info; diff --git a/drivers/video/s3c2410fb.c b/drivers/video/s3c2410fb.c index aac661225c78..2b094dec4a56 100644 --- a/drivers/video/s3c2410fb.c +++ b/drivers/video/s3c2410fb.c @@ -1004,12 +1004,12 @@ dealloc_fb: return ret; } -static int __init s3c2410fb_probe(struct platform_device *pdev) +static int __devinit s3c2410fb_probe(struct platform_device *pdev) { return s3c24xxfb_probe(pdev, DRV_S3C2410); } -static int __init s3c2412fb_probe(struct platform_device *pdev) +static int __devinit s3c2412fb_probe(struct platform_device *pdev) { return s3c24xxfb_probe(pdev, DRV_S3C2412); } diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c index cdaa873a6054..e8b76d65a070 100644 --- a/drivers/video/sa1100fb.c +++ b/drivers/video/sa1100fb.c @@ -1435,7 +1435,7 @@ static struct sa1100fb_info * __init sa1100fb_init_fbinfo(struct device *dev) return fbi; } -static int __init sa1100fb_probe(struct platform_device *pdev) +static int __devinit sa1100fb_probe(struct platform_device *pdev) { struct sa1100fb_info *fbi; int ret, irq; diff --git a/drivers/video/sgivwfb.c b/drivers/video/sgivwfb.c index f86012239bff..7a3a5e28eca1 100644 --- a/drivers/video/sgivwfb.c +++ b/drivers/video/sgivwfb.c @@ -745,7 +745,7 @@ int __init sgivwfb_setup(char *options) /* * Initialisation */ -static int __init sgivwfb_probe(struct platform_device *dev) +static int __devinit sgivwfb_probe(struct platform_device *dev) { struct sgivw_par *par; struct fb_info *info; diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c index 8d7653e56df5..bbd1dbf4026a 100644 --- a/drivers/video/sh_mobile_lcdcfb.c +++ b/drivers/video/sh_mobile_lcdcfb.c @@ -943,7 +943,7 @@ static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = { static int sh_mobile_lcdc_remove(struct platform_device *pdev); -static int __init sh_mobile_lcdc_probe(struct platform_device *pdev) +static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev) { struct fb_info *info; struct sh_mobile_lcdc_priv *priv; diff --git a/drivers/video/vesafb.c b/drivers/video/vesafb.c index bd37ee1f6a25..ef4128c8e57a 100644 --- a/drivers/video/vesafb.c +++ b/drivers/video/vesafb.c @@ -226,7 +226,7 @@ static int __init vesafb_setup(char *options) return 0; } -static int __init vesafb_probe(struct platform_device *dev) +static int __devinit vesafb_probe(struct platform_device *dev) { struct fb_info *info; int i, err; diff --git a/drivers/video/vfb.c b/drivers/video/vfb.c index 050d432c7d95..b8ab995fbda7 100644 --- a/drivers/video/vfb.c +++ b/drivers/video/vfb.c @@ -479,7 +479,7 @@ static int __init vfb_setup(char *options) * Initialisation */ -static int __init vfb_probe(struct platform_device *dev) +static int __devinit vfb_probe(struct platform_device *dev) { struct fb_info *info; int retval = -ENOMEM; diff --git a/drivers/video/vga16fb.c b/drivers/video/vga16fb.c index 5b2938903ac2..76d8dae5b1bb 100644 --- a/drivers/video/vga16fb.c +++ b/drivers/video/vga16fb.c @@ -1293,7 +1293,7 @@ static int vga16fb_setup(char *options) } #endif -static int __init vga16fb_probe(struct platform_device *dev) +static int __devinit vga16fb_probe(struct platform_device *dev) { struct fb_info *info; struct vga16fb_par *par; diff --git a/drivers/video/w100fb.c b/drivers/video/w100fb.c index 2376f688ec8b..5d223959778a 100644 --- a/drivers/video/w100fb.c +++ b/drivers/video/w100fb.c @@ -628,7 +628,7 @@ static int w100fb_resume(struct platform_device *dev) #endif -int __init w100fb_probe(struct platform_device *pdev) +int __devinit w100fb_probe(struct platform_device *pdev) { int err = -EIO; struct w100fb_mach_info *inf; -- cgit v1.2.3 From ea79632d90754409b11388410bbe23b62394401d Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 4 Feb 2010 20:56:52 +0100 Subject: x86: move hp-wmi's probe function to .devinit.text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A pointer to hp_wmi_bios_setup is passed to the core via platform_driver_register and so the function must not disappear when the .init sections are discarded. Otherwise (if also having HOTPLUG=y) unbinding and binding a device to the driver via sysfs will result in an oops as does a device being registered late. An alternative to this patch is using platform_driver_probe instead of platform_driver_register plus removing the pointer to the probe function from the struct platform_driver. Signed-off-by: Uwe Kleine-König Cc: Frans Pop Cc: Larry Finger Cc: Len Brown Cc: Helge Deller Cc: Andrew Morton Acked-by: Matthew Garrett Signed-off-by: Greg Kroah-Hartman --- drivers/platform/x86/hp-wmi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/platform/x86/hp-wmi.c b/drivers/platform/x86/hp-wmi.c index 3aa57da8b43b..7ccf33c08967 100644 --- a/drivers/platform/x86/hp-wmi.c +++ b/drivers/platform/x86/hp-wmi.c @@ -57,7 +57,7 @@ enum hp_wmi_radio { HPWMI_WWAN = 2, }; -static int __init hp_wmi_bios_setup(struct platform_device *device); +static int __devinit hp_wmi_bios_setup(struct platform_device *device); static int __exit hp_wmi_bios_remove(struct platform_device *device); static int hp_wmi_resume_handler(struct device *device); @@ -447,7 +447,7 @@ static void cleanup_sysfs(struct platform_device *device) device_remove_file(&device->dev, &dev_attr_tablet); } -static int __init hp_wmi_bios_setup(struct platform_device *device) +static int __devinit hp_wmi_bios_setup(struct platform_device *device) { int err; int wireless = hp_wmi_perform_query(HPWMI_WIRELESS_QUERY, 0, 0); -- cgit v1.2.3 From 1139aea97a6325270bda6c86ea1c9711a0c21e33 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 4 Feb 2010 20:56:53 +0100 Subject: i2c: move i2c_omap's probe function to .devinit.text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A pointer to omap_i2c_probe is passed to the core via platform_driver_register and so the function must not disappear when the .init sections are discarded. Otherwise (if also having HOTPLUG=y) unbinding and binding a device to the driver via sysfs will result in an oops as does a device being registered late. An alternative to this patch is using platform_driver_probe instead of platform_driver_register plus removing the pointer to the probe function from the struct platform_driver. Signed-off-by: Uwe Kleine-König Cc: Kalle Jokiniemi Cc: Tony Lindgren Cc: Paul Walmsley Cc: Richard Woodruff Cc: chandra shekhar Cc: Jason P Marini Cc: Syed Mohammed Khasim Cc: Jarkko Nikula Cc: Juha Yrjola Cc: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- drivers/i2c/busses/i2c-omap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 913abd7c172f..c7c237537f81 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -850,7 +850,7 @@ static const struct i2c_algorithm omap_i2c_algo = { .functionality = omap_i2c_func, }; -static int __init +static int __devinit omap_i2c_probe(struct platform_device *pdev) { struct omap_i2c_dev *dev; -- cgit v1.2.3 From a96b9121862bbd18e00c865d9516e0a98bb135ef Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 4 Feb 2010 20:56:54 +0100 Subject: w1: move omap_hdq's probe function to .devinit.text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A pointer to omap_hdq_probe is passed to the core via platform_driver_register and so the function must not disappear when the .init sections are discarded. Otherwise (if also having HOTPLUG=y) unbinding and binding a device to the driver via sysfs will result in an oops as does a device being registered late. An alternative to this patch is using platform_driver_probe instead of platform_driver_register plus removing the pointer to the probe function from the struct platform_driver. Signed-off-by: Uwe Kleine-König Cc: Stanley.Miao Acked-by: Evgeniy Polyakov Cc: Andrew Morton Cc: Madhusudhan Chikkature Cc: Felipe Balbi Signed-off-by: Greg Kroah-Hartman --- drivers/w1/masters/omap_hdq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c index 0d92969404c3..22977d30f89e 100644 --- a/drivers/w1/masters/omap_hdq.c +++ b/drivers/w1/masters/omap_hdq.c @@ -72,7 +72,7 @@ struct hdq_data { int init_trans; }; -static int __init omap_hdq_probe(struct platform_device *pdev); +static int __devinit omap_hdq_probe(struct platform_device *pdev); static int omap_hdq_remove(struct platform_device *pdev); static struct platform_driver omap_hdq_driver = { @@ -558,7 +558,7 @@ static void omap_w1_write_byte(void *_hdq, u8 byte) return; } -static int __init omap_hdq_probe(struct platform_device *pdev) +static int __devinit omap_hdq_probe(struct platform_device *pdev) { struct hdq_data *hdq_data; struct resource *res; -- cgit v1.2.3 From ea180ca4d6fbeeb8f8bea4a175d2b84b9129b693 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 4 Feb 2010 20:56:55 +0100 Subject: media: move omap24xxcam's probe function to .devinit.text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A pointer to omap24xxcam_probe is passed to the core via platform_driver_register and so the function must not disappear when the .init sections are discarded. Otherwise (if also having HOTPLUG=y) unbinding and binding a device to the driver via sysfs will result in an oops as does a device being registered late. An alternative to this patch is using platform_driver_probe instead of platform_driver_register plus removing the pointer to the probe function from the struct platform_driver. Signed-off-by: Uwe Kleine-König Acked-by: Sakari Ailus Acked-by: Trilok Soni Cc: Hans Verkuil Cc: Mauro Carvalho Chehab Cc: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- drivers/media/video/omap24xxcam.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/media/video/omap24xxcam.c b/drivers/media/video/omap24xxcam.c index 7400eacb4d64..142c327afb32 100644 --- a/drivers/media/video/omap24xxcam.c +++ b/drivers/media/video/omap24xxcam.c @@ -1735,7 +1735,7 @@ static struct v4l2_int_device omap24xxcam = { * */ -static int __init omap24xxcam_probe(struct platform_device *pdev) +static int __devinit omap24xxcam_probe(struct platform_device *pdev) { struct omap24xxcam_device *cam; struct resource *mem; -- cgit v1.2.3 From 57f1e87523bdb6c39659ead7c0f72eea9e520fbe Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 4 Feb 2010 20:56:56 +0100 Subject: auxdisplay: move cfag12864bfb's probe function to .devinit.text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A pointer to cfag12864bfb_probe is passed to the core via platform_driver_register and so the function must not disappear when the .init sections are discarded. Otherwise (if also having HOTPLUG=y) unbinding and binding a device to the driver via sysfs will result in an oops as does a device being registered late. An alternative to this patch is using platform_driver_probe instead of platform_driver_register plus removing the pointer to the probe function from the struct platform_driver. Signed-off-by: Uwe Kleine-König Acked-by: Miguel Ojeda Cc: Andrew Morton Cc: Avuton Olrich Cc: Antonino Daplas Signed-off-by: Greg Kroah-Hartman --- drivers/auxdisplay/cfag12864bfb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/auxdisplay/cfag12864bfb.c b/drivers/auxdisplay/cfag12864bfb.c index fe3a865be4e5..b0ca5a47f47d 100644 --- a/drivers/auxdisplay/cfag12864bfb.c +++ b/drivers/auxdisplay/cfag12864bfb.c @@ -81,7 +81,7 @@ static struct fb_ops cfag12864bfb_ops = { .fb_mmap = cfag12864bfb_mmap, }; -static int __init cfag12864bfb_probe(struct platform_device *device) +static int __devinit cfag12864bfb_probe(struct platform_device *device) { int ret = -EINVAL; struct fb_info *info = framebuffer_alloc(0, &device->dev); -- cgit v1.2.3 From 8f314cfc1259d3f5039b142ce6fdc90367c22d82 Mon Sep 17 00:00:00 2001 From: "Hans J. Koch" Date: Tue, 9 Feb 2010 20:13:49 +0100 Subject: UIO: Add a driver for Hilscher netX-based fieldbus cards This patch adds a Userspace IO driver for netX-based fieldbus cards by Hilscher (see http://www.hilscher.com). ATM, cifX and comX cards are supported. The userspace part for this driver is provided by Hilscher and should come with the card. The driver is in use for several months now and has been tested by people at Hilscher and Linutronix. Signed-off-by: Hans J. Koch Signed-off-by: Greg Kroah-Hartman --- drivers/uio/Kconfig | 11 ++++ drivers/uio/Makefile | 1 + drivers/uio/uio_netx.c | 172 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 184 insertions(+) create mode 100644 drivers/uio/uio_netx.c (limited to 'drivers') diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig index 8aa1955f35ed..069b1443be6c 100644 --- a/drivers/uio/Kconfig +++ b/drivers/uio/Kconfig @@ -94,4 +94,15 @@ config UIO_PCI_GENERIC primarily, for virtualization scenarios. If you compile this as a module, it will be called uio_pci_generic. +config UIO_NETX + tristate "Hilscher NetX Card driver" + depends on PCI + help + Driver for Hilscher NetX based fieldbus cards (cifX, comX). + This driver requires a userspace component that comes with the card + or is available from Hilscher (http://www.hilscher.com). + + To compile this driver as a module, choose M here; the module + will be called uio_netx. + endif diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile index 73b2e7516729..aa7d0333fa78 100644 --- a/drivers/uio/Makefile +++ b/drivers/uio/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_UIO_SMX) += uio_smx.o obj-$(CONFIG_UIO_AEC) += uio_aec.o obj-$(CONFIG_UIO_SERCOS3) += uio_sercos3.o obj-$(CONFIG_UIO_PCI_GENERIC) += uio_pci_generic.o +obj-$(CONFIG_UIO_NETX) += uio_netx.o diff --git a/drivers/uio/uio_netx.c b/drivers/uio/uio_netx.c new file mode 100644 index 000000000000..afbf0bd55cc9 --- /dev/null +++ b/drivers/uio/uio_netx.c @@ -0,0 +1,172 @@ +/* + * UIO driver for Hilscher NetX based fieldbus cards (cifX, comX). + * See http://www.hilscher.com for details. + * + * (C) 2007 Hans J. Koch + * (C) 2008 Manuel Traut + * + * Licensed under GPL version 2 only. + * + */ + +#include +#include +#include +#include +#include + +#define PCI_VENDOR_ID_HILSCHER 0x15CF +#define PCI_DEVICE_ID_HILSCHER_NETX 0x0000 +#define PCI_SUBDEVICE_ID_NXSB_PCA 0x3235 +#define PCI_SUBDEVICE_ID_NXPCA 0x3335 + +#define DPM_HOST_INT_EN0 0xfff0 +#define DPM_HOST_INT_STAT0 0xffe0 + +#define DPM_HOST_INT_MASK 0xe600ffff +#define DPM_HOST_INT_GLOBAL_EN 0x80000000 + +static irqreturn_t netx_handler(int irq, struct uio_info *dev_info) +{ + void __iomem *int_enable_reg = dev_info->mem[0].internal_addr + + DPM_HOST_INT_EN0; + void __iomem *int_status_reg = dev_info->mem[0].internal_addr + + DPM_HOST_INT_STAT0; + + /* Is one of our interrupts enabled and active ? */ + if (!(ioread32(int_enable_reg) & ioread32(int_status_reg) + & DPM_HOST_INT_MASK)) + return IRQ_NONE; + + /* Disable interrupt */ + iowrite32(ioread32(int_enable_reg) & ~DPM_HOST_INT_GLOBAL_EN, + int_enable_reg); + return IRQ_HANDLED; +} + +static int __devinit netx_pci_probe(struct pci_dev *dev, + const struct pci_device_id *id) +{ + struct uio_info *info; + int bar; + + info = kzalloc(sizeof(struct uio_info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + if (pci_enable_device(dev)) + goto out_free; + + if (pci_request_regions(dev, "netx")) + goto out_disable; + + switch (id->device) { + case PCI_DEVICE_ID_HILSCHER_NETX: + bar = 0; + info->name = "netx"; + break; + default: + bar = 2; + info->name = "netx_plx"; + } + + /* BAR0 or 2 points to the card's dual port memory */ + info->mem[0].addr = pci_resource_start(dev, bar); + if (!info->mem[0].addr) + goto out_release; + info->mem[0].internal_addr = ioremap(pci_resource_start(dev, bar), + pci_resource_len(dev, bar)); + + if (!info->mem[0].internal_addr) + goto out_release; + + info->mem[0].size = pci_resource_len(dev, bar); + info->mem[0].memtype = UIO_MEM_PHYS; + info->irq = dev->irq; + info->irq_flags = IRQF_SHARED; + info->handler = netx_handler; + info->version = "0.0.1"; + + /* Make sure all interrupts are disabled */ + iowrite32(0, info->mem[0].internal_addr + DPM_HOST_INT_EN0); + + if (uio_register_device(&dev->dev, info)) + goto out_unmap; + + pci_set_drvdata(dev, info); + dev_info(&dev->dev, "Found %s card, registered UIO device.\n", + info->name); + + return 0; + +out_unmap: + iounmap(info->mem[0].internal_addr); +out_release: + pci_release_regions(dev); +out_disable: + pci_disable_device(dev); +out_free: + kfree(info); + return -ENODEV; +} + +static void netx_pci_remove(struct pci_dev *dev) +{ + struct uio_info *info = pci_get_drvdata(dev); + + /* Disable all interrupts */ + iowrite32(0, info->mem[0].internal_addr + DPM_HOST_INT_EN0); + uio_unregister_device(info); + pci_release_regions(dev); + pci_disable_device(dev); + pci_set_drvdata(dev, NULL); + iounmap(info->mem[0].internal_addr); + + kfree(info); +} + +static struct pci_device_id netx_pci_ids[] = { + { + .vendor = PCI_VENDOR_ID_HILSCHER, + .device = PCI_DEVICE_ID_HILSCHER_NETX, + .subvendor = 0, + .subdevice = 0, + }, + { + .vendor = PCI_VENDOR_ID_PLX, + .device = PCI_DEVICE_ID_PLX_9030, + .subvendor = PCI_VENDOR_ID_PLX, + .subdevice = PCI_SUBDEVICE_ID_NXSB_PCA, + }, + { + .vendor = PCI_VENDOR_ID_PLX, + .device = PCI_DEVICE_ID_PLX_9030, + .subvendor = PCI_VENDOR_ID_PLX, + .subdevice = PCI_SUBDEVICE_ID_NXPCA, + }, + { 0, } +}; + +static struct pci_driver netx_pci_driver = { + .name = "netx", + .id_table = netx_pci_ids, + .probe = netx_pci_probe, + .remove = netx_pci_remove, +}; + +static int __init netx_init_module(void) +{ + return pci_register_driver(&netx_pci_driver); +} + +static void __exit netx_exit_module(void) +{ + pci_unregister_driver(&netx_pci_driver); +} + +module_init(netx_init_module); +module_exit(netx_exit_module); + +MODULE_DEVICE_TABLE(pci, netx_pci_ids); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Hans J. Koch, Manuel Traut"); -- cgit v1.2.3 From 0a965eb9f69caf0fb331d45556da8bab1c8dcb11 Mon Sep 17 00:00:00 2001 From: John Ogness Date: Thu, 11 Feb 2010 15:38:53 +0100 Subject: UIO: minor Kconfig fixes Two trivial fixes for the Userspace IO Kconfig file: 1) uio_sercos3 is a PCI driver, so let it depend on PCI. 2) "default n" under UIO_PCI_GENERIC is luxury since it is already the default. Acked-by: John Ogness Signed-off-by: Hans J. Koch Signed-off-by: Greg Kroah-Hartman --- drivers/uio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig index 069b1443be6c..6dd2a290f323 100644 --- a/drivers/uio/Kconfig +++ b/drivers/uio/Kconfig @@ -74,6 +74,7 @@ config UIO_AEC config UIO_SERCOS3 tristate "Automata Sercos III PCI card driver" + depends on PCI help Userspace I/O interface for the Sercos III PCI card from Automata GmbH. The userspace part of this driver will be @@ -87,7 +88,6 @@ config UIO_SERCOS3 config UIO_PCI_GENERIC tristate "Generic driver for PCI 2.3 and PCI Express cards" depends on PCI - default n help Generic driver that you can bind, dynamically, to any PCI 2.3 compliant and PCI Express card. It is useful, -- cgit v1.2.3 From d6e976c0d258c9547a308bd8a9a82ec93e2bc6e2 Mon Sep 17 00:00:00 2001 From: "Hans J. Koch" Date: Wed, 10 Feb 2010 20:12:42 +0100 Subject: UIO: Remove SMX Cryptengine driver Ben Nizette, the author of this driver, told me in a private mail that this project has been cancelled. He suggested to remove the driver for now, and will come back with a new version should the hardware really exist. This patch completely removes the driver. Signed-off-by: Hans J. Koch Acked-by: Ben Nizette Signed-off-by: Greg Kroah-Hartman --- drivers/uio/Kconfig | 11 ---- drivers/uio/Makefile | 1 - drivers/uio/uio_smx.c | 140 -------------------------------------------------- 3 files changed, 152 deletions(-) delete mode 100644 drivers/uio/uio_smx.c (limited to 'drivers') diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig index 6dd2a290f323..1da73ecd9799 100644 --- a/drivers/uio/Kconfig +++ b/drivers/uio/Kconfig @@ -44,17 +44,6 @@ config UIO_PDRV_GENIRQ If you don't know what to do here, say N. -config UIO_SMX - tristate "SMX cryptengine UIO interface" - help - Userspace IO interface to the Cryptography engine found on the - Nias Digital SMX boards. These will be available from Q4 2008 - from http://www.niasdigital.com. The userspace part of this - driver will be released under the GPL at the same time as the - hardware and will be able to be downloaded from the same site. - - If you compile this as a module, it will be called uio_smx. - config UIO_AEC tristate "AEC video timestamp device" depends on PCI diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile index aa7d0333fa78..18fd818c5b97 100644 --- a/drivers/uio/Makefile +++ b/drivers/uio/Makefile @@ -2,7 +2,6 @@ obj-$(CONFIG_UIO) += uio.o obj-$(CONFIG_UIO_CIF) += uio_cif.o obj-$(CONFIG_UIO_PDRV) += uio_pdrv.o obj-$(CONFIG_UIO_PDRV_GENIRQ) += uio_pdrv_genirq.o -obj-$(CONFIG_UIO_SMX) += uio_smx.o obj-$(CONFIG_UIO_AEC) += uio_aec.o obj-$(CONFIG_UIO_SERCOS3) += uio_sercos3.o obj-$(CONFIG_UIO_PCI_GENERIC) += uio_pci_generic.o diff --git a/drivers/uio/uio_smx.c b/drivers/uio/uio_smx.c deleted file mode 100644 index 44054a650a8a..000000000000 --- a/drivers/uio/uio_smx.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * UIO SMX Cryptengine driver. - * - * (C) 2008 Nias Digital P/L - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include -#include -#include -#include - -#define DRV_NAME "smx-ce" -#define DRV_VERSION "0.03" - -#define SMX_CSR 0x00000000 -#define SMX_EnD 0x00000001 -#define SMX_RUN 0x00000002 -#define SMX_DRDY 0x00000004 -#define SMX_ERR 0x00000008 - -static irqreturn_t smx_handler(int irq, struct uio_info *dev_info) -{ - void __iomem *csr = dev_info->mem[0].internal_addr + SMX_CSR; - - u32 status = ioread32(csr); - - if (!(status & SMX_DRDY)) - return IRQ_NONE; - - /* Disable interrupt */ - iowrite32(status & ~SMX_DRDY, csr); - return IRQ_HANDLED; -} - -static int __devinit smx_ce_probe(struct platform_device *dev) -{ - - int ret = -ENODEV; - struct uio_info *info; - struct resource *regs; - - info = kzalloc(sizeof(struct uio_info), GFP_KERNEL); - if (!info) - return -ENOMEM; - - regs = platform_get_resource(dev, IORESOURCE_MEM, 0); - if (!regs) { - dev_err(&dev->dev, "No memory resource specified\n"); - goto out_free; - } - - info->mem[0].addr = regs->start; - if (!info->mem[0].addr) { - dev_err(&dev->dev, "Invalid memory resource\n"); - goto out_free; - } - - info->mem[0].size = regs->end - regs->start + 1; - info->mem[0].internal_addr = ioremap(regs->start, info->mem[0].size); - - if (!info->mem[0].internal_addr) { - dev_err(&dev->dev, "Can't remap memory address range\n"); - goto out_free; - } - - info->mem[0].memtype = UIO_MEM_PHYS; - - info->name = "smx-ce"; - info->version = "0.03"; - - info->irq = platform_get_irq(dev, 0); - if (info->irq < 0) { - ret = info->irq; - dev_err(&dev->dev, "No (or invalid) IRQ resource specified\n"); - goto out_unmap; - } - - info->irq_flags = IRQF_SHARED; - info->handler = smx_handler; - - platform_set_drvdata(dev, info); - - ret = uio_register_device(&dev->dev, info); - - if (ret) - goto out_unmap; - - return 0; - -out_unmap: - iounmap(info->mem[0].internal_addr); -out_free: - kfree(info); - - return ret; -} - -static int __devexit smx_ce_remove(struct platform_device *dev) -{ - struct uio_info *info = platform_get_drvdata(dev); - - uio_unregister_device(info); - platform_set_drvdata(dev, NULL); - iounmap(info->mem[0].internal_addr); - - kfree(info); - - return 0; -} - -static struct platform_driver smx_ce_driver = { - .probe = smx_ce_probe, - .remove = __devexit_p(smx_ce_remove), - .driver = { - .name = DRV_NAME, - .owner = THIS_MODULE, - }, -}; - -static int __init smx_ce_init_module(void) -{ - return platform_driver_register(&smx_ce_driver); -} -module_init(smx_ce_init_module); - -static void __exit smx_ce_exit_module(void) -{ - platform_driver_unregister(&smx_ce_driver); -} -module_exit(smx_ce_exit_module); - -MODULE_LICENSE("GPL v2"); -MODULE_VERSION(DRV_VERSION); -MODULE_AUTHOR("Ben Nizette "); -- cgit v1.2.3 From 3c31f07ad0dab02fe17195d32a965d57fd947707 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Sun, 14 Feb 2010 14:18:53 +0000 Subject: Driver core: Fix first line of kernel-doc for a few functions The function name must be followed by a space, hypen, space, and a short description. Signed-off-by: Ben Hutchings Signed-off-by: Greg Kroah-Hartman --- drivers/base/firmware_class.c | 2 +- drivers/base/platform.c | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/base/firmware_class.c b/drivers/base/firmware_class.c index 07977484cb3c..d0dc26ad5387 100644 --- a/drivers/base/firmware_class.c +++ b/drivers/base/firmware_class.c @@ -613,7 +613,7 @@ request_firmware_work_func(void *arg) } /** - * request_firmware_nowait: asynchronous version of request_firmware + * request_firmware_nowait - asynchronous version of request_firmware * @module: module requesting the firmware * @uevent: sends uevent to copy the firmware image if this flag * is non-zero else the firmware copy must be done manually. diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 575e08bc6630..1ba9d617d241 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -128,7 +128,7 @@ struct platform_object { }; /** - * platform_device_put + * platform_device_put - destroy a platform device * @pdev: platform device to free * * Free all memory associated with a platform device. This function must @@ -152,7 +152,7 @@ static void platform_device_release(struct device *dev) } /** - * platform_device_alloc + * platform_device_alloc - create a platform device * @name: base name of the device we're adding * @id: instance id * @@ -177,7 +177,7 @@ struct platform_device *platform_device_alloc(const char *name, int id) EXPORT_SYMBOL_GPL(platform_device_alloc); /** - * platform_device_add_resources + * platform_device_add_resources - add resources to a platform device * @pdev: platform device allocated by platform_device_alloc to add resources to * @res: set of resources that needs to be allocated for the device * @num: number of resources @@ -202,7 +202,7 @@ int platform_device_add_resources(struct platform_device *pdev, EXPORT_SYMBOL_GPL(platform_device_add_resources); /** - * platform_device_add_data + * platform_device_add_data - add platform-specific data to a platform device * @pdev: platform device allocated by platform_device_alloc to add resources to * @data: platform specific data for this platform device * @size: size of platform specific data @@ -344,7 +344,7 @@ void platform_device_unregister(struct platform_device *pdev) EXPORT_SYMBOL_GPL(platform_device_unregister); /** - * platform_device_register_simple + * platform_device_register_simple - add a platform-level device and its resources * @name: base name of the device we're adding * @id: instance id * @res: set of resources that needs to be allocated for the device @@ -396,7 +396,7 @@ error: EXPORT_SYMBOL_GPL(platform_device_register_simple); /** - * platform_device_register_data + * platform_device_register_data - add a platform-level device with platform-specific data * @parent: parent device for the device we're adding * @name: base name of the device we're adding * @id: instance id @@ -473,7 +473,7 @@ static void platform_drv_shutdown(struct device *_dev) } /** - * platform_driver_register + * platform_driver_register - register a driver for platform-level devices * @drv: platform driver structure */ int platform_driver_register(struct platform_driver *drv) @@ -491,7 +491,7 @@ int platform_driver_register(struct platform_driver *drv) EXPORT_SYMBOL_GPL(platform_driver_register); /** - * platform_driver_unregister + * platform_driver_unregister - unregister a driver for platform-level devices * @drv: platform driver structure */ void platform_driver_unregister(struct platform_driver *drv) -- cgit v1.2.3 From a07e4156a2ee6359d31a44946d7ee7f85dbf6bca Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Thu, 11 Feb 2010 15:23:05 -0800 Subject: sysfs: Use sysfs_attr_init and sysfs_bin_attr_init on dynamic attributes These are the non-static sysfs attributes that exist on my test machine. Fix them to use sysfs_attr_init or sysfs_bin_attr_init as appropriate. It simply requires making a sysfs attribute present to see this. So this is a little bit tedious but otherwise not too bad. Signed-off-by: Eric W. Biederman Acked-by: WANG Cong Cc: Tejun Heo Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/mcheck/mce.c | 1 + drivers/acpi/system.c | 2 ++ drivers/pci/pci-sysfs.c | 5 +++++ kernel/params.c | 1 + 4 files changed, 9 insertions(+) (limited to 'drivers') diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index a8aacd4b513c..28cba46bf32c 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -2044,6 +2044,7 @@ static __init void mce_init_banks(void) struct mce_bank *b = &mce_banks[i]; struct sysdev_attribute *a = &b->attr; + sysfs_attr_init(&a->attr); a->attr.name = b->attrname; snprintf(b->attrname, ATTR_LEN, "bank%d", i); diff --git a/drivers/acpi/system.c b/drivers/acpi/system.c index a206a12da78a..743f2445e2a1 100644 --- a/drivers/acpi/system.c +++ b/drivers/acpi/system.c @@ -101,6 +101,7 @@ static void acpi_table_attr_init(struct acpi_table_attr *table_attr, struct acpi_table_header *header = NULL; struct acpi_table_attr *attr = NULL; + sysfs_attr_init(&table_attr->attr.attr); if (table_header->signature[0] != '\0') memcpy(table_attr->name, table_header->signature, ACPI_NAME_SIZE); @@ -475,6 +476,7 @@ void acpi_irq_stats_init(void) goto fail; strncpy(name, buffer, strlen(buffer) + 1); + sysfs_attr_init(&counter_attrs[i].attr); counter_attrs[i].attr.name = name; counter_attrs[i].attr.mode = 0644; counter_attrs[i].show = counter_show; diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 807224ec8351..9fa183cfb0e9 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -642,6 +642,7 @@ void pci_create_legacy_files(struct pci_bus *b) if (!b->legacy_io) goto kzalloc_err; + sysfs_bin_attr_init(&b->legacy_io); b->legacy_io->attr.name = "legacy_io"; b->legacy_io->size = 0xffff; b->legacy_io->attr.mode = S_IRUSR | S_IWUSR; @@ -654,6 +655,7 @@ void pci_create_legacy_files(struct pci_bus *b) goto legacy_io_err; /* Allocated above after the legacy_io struct */ + sysfs_bin_attr_init(&b->legacy_mem); b->legacy_mem = b->legacy_io + 1; b->legacy_mem->attr.name = "legacy_mem"; b->legacy_mem->size = 1024*1024; @@ -800,6 +802,7 @@ static int pci_create_attr(struct pci_dev *pdev, int num, int write_combine) if (res_attr) { char *res_attr_name = (char *)(res_attr + 1); + sysfs_bin_attr_init(res_attr); if (write_combine) { pdev->res_attr_wc[num] = res_attr; sprintf(res_attr_name, "resource%d_wc", num); @@ -972,6 +975,7 @@ static int pci_create_capabilities_sysfs(struct pci_dev *dev) if (!attr) return -ENOMEM; + sysfs_bin_attr_init(attr); attr->size = dev->vpd->len; attr->attr.name = "vpd"; attr->attr.mode = S_IRUSR | S_IWUSR; @@ -1038,6 +1042,7 @@ int __must_check pci_create_sysfs_dev_files (struct pci_dev *pdev) retval = -ENOMEM; goto err_resource_files; } + sysfs_bin_attr_init(attr); attr->size = rom_size; attr->attr.name = "rom"; attr->attr.mode = S_IRUSR; diff --git a/kernel/params.c b/kernel/params.c index 68396d73c838..d55a53ec9234 100644 --- a/kernel/params.c +++ b/kernel/params.c @@ -516,6 +516,7 @@ static __modinit int add_sysfs_param(struct module_kobject *mk, new->grp.attrs = attrs; /* Tack new one on the end. */ + sysfs_attr_init(&new->attrs[num].mattr.attr); new->attrs[num].param = kp; new->attrs[num].mattr.show = param_attr_show; new->attrs[num].mattr.store = param_attr_store; -- cgit v1.2.3 From b35c74dab64f4c212f36d868419108556c9cf3e2 Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Sat, 20 Feb 2010 16:43:02 +0100 Subject: sysfs: windfarm: init sysfs attributes This is required for lockdep. Signed-off-by: Johannes Berg Signed-off-by: Greg Kroah-Hartman --- drivers/macintosh/windfarm_core.c | 1 + drivers/macintosh/windfarm_smu_controls.c | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/macintosh/windfarm_core.c b/drivers/macintosh/windfarm_core.c index 437f55c5d18d..419795f4a2aa 100644 --- a/drivers/macintosh/windfarm_core.c +++ b/drivers/macintosh/windfarm_core.c @@ -321,6 +321,7 @@ int wf_register_sensor(struct wf_sensor *new_sr) kref_init(&new_sr->ref); list_add(&new_sr->link, &wf_sensors); + sysfs_attr_init(&new_sr->attr.attr); new_sr->attr.attr.name = new_sr->name; new_sr->attr.attr.mode = 0444; new_sr->attr.show = wf_show_sensor; diff --git a/drivers/macintosh/windfarm_smu_controls.c b/drivers/macintosh/windfarm_smu_controls.c index 6c68b9e5f5c4..43137b421f92 100644 --- a/drivers/macintosh/windfarm_smu_controls.c +++ b/drivers/macintosh/windfarm_smu_controls.c @@ -173,6 +173,7 @@ static struct smu_fan_control *smu_fan_create(struct device_node *node, fct->fan_type = pwm_fan; fct->ctrl.type = pwm_fan ? WF_CONTROL_PWM_FAN : WF_CONTROL_RPM_FAN; + sysfs_attr_init(&fct->ctrl.attr.attr); /* We use the name & location here the same way we do for SMU sensors, * see the comment in windfarm_smu_sensors.c. The locations are a bit -- cgit v1.2.3 From 2354dcc7218853a6537ec722be40fde9a11c413b Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Fri, 12 Feb 2010 19:22:26 -0800 Subject: driver core: Use sysfs_rename_link in device_rename Don't open code the renaming of symlinks in sysfs instead use the new helper function sysfs_rename_link Acked-by: Tejun Heo Acked-by: Serge Hallyn Signed-off-by: Eric W. Biederman Signed-off-by: Greg Kroah-Hartman --- drivers/base/core.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/base/core.c b/drivers/base/core.c index b0d6646a2814..ef55df34ddd0 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -1578,22 +1578,16 @@ int device_rename(struct device *dev, char *new_name) if (old_class_name) { new_class_name = make_class_name(dev->class->name, &dev->kobj); if (new_class_name) { - error = sysfs_create_link_nowarn(&dev->parent->kobj, - &dev->kobj, - new_class_name); - if (error) - goto out; - sysfs_remove_link(&dev->parent->kobj, old_class_name); + error = sysfs_rename_link(&dev->parent->kobj, + &dev->kobj, + old_class_name, + new_class_name); } } #else if (dev->class) { - error = sysfs_create_link_nowarn(&dev->class->p->class_subsys.kobj, - &dev->kobj, dev_name(dev)); - if (error) - goto out; - sysfs_remove_link(&dev->class->p->class_subsys.kobj, - old_device_name); + error = sysfs_rename_link(&dev->class->p->class_subsys.kobj, + &dev->kobj, old_device_name, new_name); } #endif -- cgit v1.2.3 From 62e877b893e6350c900d381f353aa62ed48dcc97 Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Mon, 1 Mar 2010 20:38:36 +1100 Subject: sysfs: fix for thinko with sysfs_bin_attr_init() After merging the final tree, today's linux-next build (powerpc allyesconfig) failed like this: drivers/pci/pci-sysfs.c: In function 'pci_create_legacy_files': drivers/pci/pci-sysfs.c:645: error: lvalue required as unary '&' operand drivers/pci/pci-sysfs.c:658: error: lvalue required as unary '&' operand Caused by commit "sysfs: Use sysfs_attr_init and sysfs_bin_attr_init on dynamic attributes" interacting with commit "sysfs: Use one lockdep class per sysfs attribute") both from the driver-core tree. Signed-off-by: Stephen Rothwell Cc: "Eric W. Biederman" Signed-off-by: Greg Kroah-Hartman --- drivers/pci/pci-sysfs.c | 4 ++-- include/linux/sysfs.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 9fa183cfb0e9..de296452c957 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -642,7 +642,7 @@ void pci_create_legacy_files(struct pci_bus *b) if (!b->legacy_io) goto kzalloc_err; - sysfs_bin_attr_init(&b->legacy_io); + sysfs_bin_attr_init(b->legacy_io); b->legacy_io->attr.name = "legacy_io"; b->legacy_io->size = 0xffff; b->legacy_io->attr.mode = S_IRUSR | S_IWUSR; @@ -655,7 +655,7 @@ void pci_create_legacy_files(struct pci_bus *b) goto legacy_io_err; /* Allocated above after the legacy_io struct */ - sysfs_bin_attr_init(&b->legacy_mem); + sysfs_bin_attr_init(b->legacy_mem); b->legacy_mem = b->legacy_io + 1; b->legacy_mem->attr.name = "legacy_mem"; b->legacy_mem->size = 1024*1024; diff --git a/include/linux/sysfs.h b/include/linux/sysfs.h index d77cde6d0498..f0496b3d1811 100644 --- a/include/linux/sysfs.h +++ b/include/linux/sysfs.h @@ -110,7 +110,7 @@ struct bin_attribute { * enabled. Lockdep gives a nice error when your attribute is * added to sysfs if you don't have this. */ -#define sysfs_bin_attr_init(bin_attr) sysfs_attr_init(&bin_attr->attr) +#define sysfs_bin_attr_init(bin_attr) sysfs_attr_init(&(bin_attr)->attr) struct sysfs_ops { ssize_t (*show)(struct kobject *, struct attribute *,char *); -- cgit v1.2.3 From 8e9394ce2412254ec69fd2a4f3e44a66eade2297 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 17 Feb 2010 10:57:05 -0800 Subject: Driver core: create lock/unlock functions for struct device In the future, we are going to be changing the lock type for struct device (once we get the lockdep infrastructure properly worked out) To make that changeover easier, and to possibly burry the lock in a different part of struct device, let's create some functions to lock and unlock a device so that no out-of-core code needs to be changed in the future. This patch creates the device_lock/unlock/trylock() functions, and converts all in-tree users to them. Cc: Thomas Gleixner Cc: Jean Delvare Cc: Dave Young Cc: Ming Lei Cc: Jiri Kosina Cc: Phil Carmody Cc: Arjan van de Ven Cc: Cornelia Huck Cc: Rafael J. Wysocki Cc: Pavel Machek Cc: Len Brown Cc: Magnus Damm Cc: Alan Stern Cc: Randy Dunlap Cc: Stefan Richter Cc: David Brownell Cc: Vegard Nossum Cc: Jesse Barnes Cc: Alex Chiang Cc: Kenji Kaneshige Cc: Andrew Morton Cc: Andrew Patterson Cc: Yu Zhao Cc: Dominik Brodowski Cc: Samuel Ortiz Cc: Wolfram Sang Cc: CHENG Renquan Cc: Oliver Neukum Cc: Frans Pop Cc: David Vrabel Cc: Kay Sievers Cc: Sarah Sharp Signed-off-by: Greg Kroah-Hartman --- drivers/base/bus.c | 20 ++++++++++---------- drivers/base/dd.c | 38 +++++++++++++++++++------------------- drivers/base/power/main.c | 20 ++++++++++---------- drivers/firewire/core-device.c | 5 ++--- drivers/ieee1394/nodemgr.c | 5 ++--- drivers/pci/bus.c | 4 ++-- drivers/pci/pci.c | 4 ++-- drivers/pcmcia/ds.c | 8 ++++---- drivers/usb/core/driver.c | 4 ++-- drivers/uwb/umc-bus.c | 4 ++-- drivers/uwb/uwb-internal.h | 4 ++-- include/linux/device.h | 17 ++++++++++++++++- include/linux/usb.h | 6 +++--- 13 files changed, 76 insertions(+), 63 deletions(-) (limited to 'drivers') diff --git a/drivers/base/bus.c b/drivers/base/bus.c index cca1aa10054c..71f6af5c8b0b 100644 --- a/drivers/base/bus.c +++ b/drivers/base/bus.c @@ -173,10 +173,10 @@ static ssize_t driver_unbind(struct device_driver *drv, dev = bus_find_device_by_name(bus, NULL, buf); if (dev && dev->driver == drv) { if (dev->parent) /* Needed for USB */ - down(&dev->parent->sem); + device_lock(dev->parent); device_release_driver(dev); if (dev->parent) - up(&dev->parent->sem); + device_unlock(dev->parent); err = count; } put_device(dev); @@ -200,12 +200,12 @@ static ssize_t driver_bind(struct device_driver *drv, dev = bus_find_device_by_name(bus, NULL, buf); if (dev && dev->driver == NULL && driver_match_device(drv, dev)) { if (dev->parent) /* Needed for USB */ - down(&dev->parent->sem); - down(&dev->sem); + device_lock(dev->parent); + device_lock(dev); err = driver_probe_device(drv, dev); - up(&dev->sem); + device_unlock(dev); if (dev->parent) - up(&dev->parent->sem); + device_unlock(dev->parent); if (err > 0) { /* success */ @@ -744,10 +744,10 @@ static int __must_check bus_rescan_devices_helper(struct device *dev, if (!dev->driver) { if (dev->parent) /* Needed for USB */ - down(&dev->parent->sem); + device_lock(dev->parent); ret = device_attach(dev); if (dev->parent) - up(&dev->parent->sem); + device_unlock(dev->parent); } return ret < 0 ? ret : 0; } @@ -779,10 +779,10 @@ int device_reprobe(struct device *dev) { if (dev->driver) { if (dev->parent) /* Needed for USB */ - down(&dev->parent->sem); + device_lock(dev->parent); device_release_driver(dev); if (dev->parent) - up(&dev->parent->sem); + device_unlock(dev->parent); } return bus_rescan_devices_helper(dev, NULL); } diff --git a/drivers/base/dd.c b/drivers/base/dd.c index ee95c76bfd3d..c89291f8a16b 100644 --- a/drivers/base/dd.c +++ b/drivers/base/dd.c @@ -85,7 +85,7 @@ static void driver_sysfs_remove(struct device *dev) * for before calling this. (It is ok to call with no other effort * from a driver's probe() method.) * - * This function must be called with @dev->sem held. + * This function must be called with the device lock held. */ int device_bind_driver(struct device *dev) { @@ -190,8 +190,8 @@ EXPORT_SYMBOL_GPL(wait_for_device_probe); * This function returns -ENODEV if the device is not registered, * 1 if the device is bound successfully and 0 otherwise. * - * This function must be called with @dev->sem held. When called for a - * USB interface, @dev->parent->sem must be held as well. + * This function must be called with @dev lock held. When called for a + * USB interface, @dev->parent lock must be held as well. */ int driver_probe_device(struct device_driver *drv, struct device *dev) { @@ -233,13 +233,13 @@ static int __device_attach(struct device_driver *drv, void *data) * 0 if no matching driver was found; * -ENODEV if the device is not registered. * - * When called for a USB interface, @dev->parent->sem must be held. + * When called for a USB interface, @dev->parent lock must be held. */ int device_attach(struct device *dev) { int ret = 0; - down(&dev->sem); + device_lock(dev); if (dev->driver) { ret = device_bind_driver(dev); if (ret == 0) @@ -253,7 +253,7 @@ int device_attach(struct device *dev) ret = bus_for_each_drv(dev->bus, NULL, dev, __device_attach); pm_runtime_put_sync(dev); } - up(&dev->sem); + device_unlock(dev); return ret; } EXPORT_SYMBOL_GPL(device_attach); @@ -276,13 +276,13 @@ static int __driver_attach(struct device *dev, void *data) return 0; if (dev->parent) /* Needed for USB */ - down(&dev->parent->sem); - down(&dev->sem); + device_lock(dev->parent); + device_lock(dev); if (!dev->driver) driver_probe_device(drv, dev); - up(&dev->sem); + device_unlock(dev); if (dev->parent) - up(&dev->parent->sem); + device_unlock(dev->parent); return 0; } @@ -303,8 +303,8 @@ int driver_attach(struct device_driver *drv) EXPORT_SYMBOL_GPL(driver_attach); /* - * __device_release_driver() must be called with @dev->sem held. - * When called for a USB interface, @dev->parent->sem must be held as well. + * __device_release_driver() must be called with @dev lock held. + * When called for a USB interface, @dev->parent lock must be held as well. */ static void __device_release_driver(struct device *dev) { @@ -343,7 +343,7 @@ static void __device_release_driver(struct device *dev) * @dev: device. * * Manually detach device from driver. - * When called for a USB interface, @dev->parent->sem must be held. + * When called for a USB interface, @dev->parent lock must be held. */ void device_release_driver(struct device *dev) { @@ -352,9 +352,9 @@ void device_release_driver(struct device *dev) * within their ->remove callback for the same device, they * will deadlock right here. */ - down(&dev->sem); + device_lock(dev); __device_release_driver(dev); - up(&dev->sem); + device_unlock(dev); } EXPORT_SYMBOL_GPL(device_release_driver); @@ -381,13 +381,13 @@ void driver_detach(struct device_driver *drv) spin_unlock(&drv->p->klist_devices.k_lock); if (dev->parent) /* Needed for USB */ - down(&dev->parent->sem); - down(&dev->sem); + device_lock(dev->parent); + device_lock(dev); if (dev->driver == drv) __device_release_driver(dev); - up(&dev->sem); + device_unlock(dev); if (dev->parent) - up(&dev->parent->sem); + device_unlock(dev->parent); put_device(dev); } } diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c index 0e26a6f6fd48..d477f4dc5e51 100644 --- a/drivers/base/power/main.c +++ b/drivers/base/power/main.c @@ -35,8 +35,8 @@ * because children are guaranteed to be discovered after parents, and * are inserted at the back of the list on discovery. * - * Since device_pm_add() may be called with a device semaphore held, - * we must never try to acquire a device semaphore while holding + * Since device_pm_add() may be called with a device lock held, + * we must never try to acquire a device lock while holding * dpm_list_mutex. */ @@ -508,7 +508,7 @@ static int device_resume(struct device *dev, pm_message_t state, bool async) TRACE_RESUME(0); dpm_wait(dev->parent, async); - down(&dev->sem); + device_lock(dev); dev->power.status = DPM_RESUMING; @@ -543,7 +543,7 @@ static int device_resume(struct device *dev, pm_message_t state, bool async) } } End: - up(&dev->sem); + device_unlock(dev); complete_all(&dev->power.completion); TRACE_RESUME(error); @@ -629,7 +629,7 @@ static void dpm_resume(pm_message_t state) */ static void device_complete(struct device *dev, pm_message_t state) { - down(&dev->sem); + device_lock(dev); if (dev->class && dev->class->pm && dev->class->pm->complete) { pm_dev_dbg(dev, state, "completing class "); @@ -646,7 +646,7 @@ static void device_complete(struct device *dev, pm_message_t state) dev->bus->pm->complete(dev); } - up(&dev->sem); + device_unlock(dev); } /** @@ -809,7 +809,7 @@ static int __device_suspend(struct device *dev, pm_message_t state, bool async) int error = 0; dpm_wait_for_children(dev, async); - down(&dev->sem); + device_lock(dev); if (async_error) goto End; @@ -849,7 +849,7 @@ static int __device_suspend(struct device *dev, pm_message_t state, bool async) dev->power.status = DPM_OFF; End: - up(&dev->sem); + device_unlock(dev); complete_all(&dev->power.completion); return error; @@ -938,7 +938,7 @@ static int device_prepare(struct device *dev, pm_message_t state) { int error = 0; - down(&dev->sem); + device_lock(dev); if (dev->bus && dev->bus->pm && dev->bus->pm->prepare) { pm_dev_dbg(dev, state, "preparing "); @@ -962,7 +962,7 @@ static int device_prepare(struct device *dev, pm_message_t state) suspend_report_result(dev->class->pm->prepare, error); } End: - up(&dev->sem); + device_unlock(dev); return error; } diff --git a/drivers/firewire/core-device.c b/drivers/firewire/core-device.c index 014cabd3afda..5db0518c66da 100644 --- a/drivers/firewire/core-device.c +++ b/drivers/firewire/core-device.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include #include @@ -828,9 +827,9 @@ static int update_unit(struct device *dev, void *data) struct fw_driver *driver = (struct fw_driver *)dev->driver; if (is_fw_unit(dev) && driver != NULL && driver->update != NULL) { - down(&dev->sem); + device_lock(dev); driver->update(unit); - up(&dev->sem); + device_unlock(dev); } return 0; diff --git a/drivers/ieee1394/nodemgr.c b/drivers/ieee1394/nodemgr.c index 5122b5a8aa2d..18350213479e 100644 --- a/drivers/ieee1394/nodemgr.c +++ b/drivers/ieee1394/nodemgr.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "csr.h" @@ -1397,9 +1396,9 @@ static int update_pdrv(struct device *dev, void *data) pdrv = container_of(drv, struct hpsb_protocol_driver, driver); if (pdrv->update) { - down(&ud->device.sem); + device_lock(&ud->device); error = pdrv->update(ud); - up(&ud->device.sem); + device_unlock(&ud->device); } if (error) device_release_driver(&ud->device); diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index 712250f5874a..26301cb25e7f 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -288,9 +288,9 @@ void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), next = dev->bus_list.next; /* Run device routines with the device locked */ - down(&dev->dev.sem); + device_lock(&dev->dev); retval = cb(dev, userdata); - up(&dev->dev.sem); + device_unlock(&dev->dev); if (retval) break; } diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 77b493b3d97b..897fa5ccdb78 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2486,7 +2486,7 @@ static int pci_dev_reset(struct pci_dev *dev, int probe) if (!probe) { pci_block_user_cfg_access(dev); /* block PM suspend, driver probe, etc. */ - down(&dev->dev.sem); + device_lock(&dev->dev); } rc = pci_dev_specific_reset(dev, probe); @@ -2508,7 +2508,7 @@ static int pci_dev_reset(struct pci_dev *dev, int probe) rc = pci_parent_bus_reset(dev, probe); done: if (!probe) { - up(&dev->dev.sem); + device_unlock(&dev->dev); pci_unblock_user_cfg_access(dev); } diff --git a/drivers/pcmcia/ds.c b/drivers/pcmcia/ds.c index 0f98be4450b7..ad93ebd7b2a2 100644 --- a/drivers/pcmcia/ds.c +++ b/drivers/pcmcia/ds.c @@ -971,9 +971,9 @@ static int runtime_suspend(struct device *dev) { int rc; - down(&dev->sem); + device_lock(dev); rc = pcmcia_dev_suspend(dev, PMSG_SUSPEND); - up(&dev->sem); + device_unlock(dev); return rc; } @@ -981,9 +981,9 @@ static int runtime_resume(struct device *dev) { int rc; - down(&dev->sem); + device_lock(dev); rc = pcmcia_dev_resume(dev); - up(&dev->sem); + device_unlock(dev); return rc; } diff --git a/drivers/usb/core/driver.c b/drivers/usb/core/driver.c index a7037bf81688..f3c233806fa3 100644 --- a/drivers/usb/core/driver.c +++ b/drivers/usb/core/driver.c @@ -489,10 +489,10 @@ void usb_driver_release_interface(struct usb_driver *driver, if (device_is_registered(dev)) { device_release_driver(dev); } else { - down(&dev->sem); + device_lock(dev); usb_unbind_interface(dev); dev->driver = NULL; - up(&dev->sem); + device_unlock(dev); } } EXPORT_SYMBOL_GPL(usb_driver_release_interface); diff --git a/drivers/uwb/umc-bus.c b/drivers/uwb/umc-bus.c index cdd6c8efc9f8..5fad4e791b3e 100644 --- a/drivers/uwb/umc-bus.c +++ b/drivers/uwb/umc-bus.c @@ -62,12 +62,12 @@ int umc_controller_reset(struct umc_dev *umc) struct device *parent = umc->dev.parent; int ret = 0; - if(down_trylock(&parent->sem)) + if (device_trylock(parent)) return -EAGAIN; ret = device_for_each_child(parent, parent, umc_bus_pre_reset_helper); if (ret >= 0) ret = device_for_each_child(parent, parent, umc_bus_post_reset_helper); - up(&parent->sem); + device_unlock(parent); return ret; } diff --git a/drivers/uwb/uwb-internal.h b/drivers/uwb/uwb-internal.h index d5bcfc1c227a..157485c862c0 100644 --- a/drivers/uwb/uwb-internal.h +++ b/drivers/uwb/uwb-internal.h @@ -366,12 +366,12 @@ struct dentry *uwb_dbg_create_pal_dir(struct uwb_pal *pal); static inline void uwb_dev_lock(struct uwb_dev *uwb_dev) { - down(&uwb_dev->dev.sem); + device_lock(&uwb_dev->dev); } static inline void uwb_dev_unlock(struct uwb_dev *uwb_dev) { - up(&uwb_dev->dev.sem); + device_unlock(&uwb_dev->dev); } #endif /* #ifndef __UWB_INTERNAL_H__ */ diff --git a/include/linux/device.h b/include/linux/device.h index f95d5bfe8248..182192892d45 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -106,7 +106,7 @@ extern int bus_unregister_notifier(struct bus_type *bus, /* All 4 notifers below get called with the target struct device * * as an argument. Note that those functions are likely to be called - * with the device semaphore held in the core, so be careful. + * with the device lock held in the core, so be careful. */ #define BUS_NOTIFY_ADD_DEVICE 0x00000001 /* device added */ #define BUS_NOTIFY_DEL_DEVICE 0x00000002 /* device removed */ @@ -508,6 +508,21 @@ static inline bool device_async_suspend_enabled(struct device *dev) return !!dev->power.async_suspend; } +static inline void device_lock(struct device *dev) +{ + down(&dev->sem); +} + +static inline int device_trylock(struct device *dev) +{ + return down_trylock(&dev->sem); +} + +static inline void device_unlock(struct device *dev) +{ + up(&dev->sem); +} + void driver_init(void); /* diff --git a/include/linux/usb.h b/include/linux/usb.h index 3492abf82e75..8c9f053111bb 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -512,9 +512,9 @@ extern struct usb_device *usb_get_dev(struct usb_device *dev); extern void usb_put_dev(struct usb_device *dev); /* USB device locking */ -#define usb_lock_device(udev) down(&(udev)->dev.sem) -#define usb_unlock_device(udev) up(&(udev)->dev.sem) -#define usb_trylock_device(udev) down_trylock(&(udev)->dev.sem) +#define usb_lock_device(udev) device_lock(&(udev)->dev) +#define usb_unlock_device(udev) device_unlock(&(udev)->dev) +#define usb_trylock_device(udev) device_trylock(&(udev)->dev) extern int usb_lock_device_for_reset(struct usb_device *udev, const struct usb_interface *iface); -- cgit v1.2.3 From 46d0e9e091ba5dd29cac7543e97084540da9c4b7 Mon Sep 17 00:00:00 2001 From: "Lee, Chun-Yi" Date: Sat, 9 Jan 2010 21:16:52 +0800 Subject: msi-laptop: Support standard ec 66/62 command on MSI notebook and nebook Suppport standard ec 66/62 command on MSI notebook and nebook. MSI netbook and notebook already support 66/62 command, so, add new get_state function, and put the old model to non-standard model, but driver still support those old model. Signed-off-by: Lee, Chun-Yi Cc: Lennart Poettering Signed-off-by: Greg Kroah-Hartman --- drivers/platform/x86/msi-laptop.c | 43 +++++++++++++++++++++++++++++++++++---- 1 file changed, 39 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c index 759763d18e4c..323e99460c9f 100644 --- a/drivers/platform/x86/msi-laptop.c +++ b/drivers/platform/x86/msi-laptop.c @@ -66,6 +66,11 @@ #define MSI_EC_COMMAND_WIRELESS 0x10 #define MSI_EC_COMMAND_LCD_LEVEL 0x11 +#define MSI_STANDARD_EC_COMMAND_ADDRESS 0x2e +#define MSI_STANDARD_EC_BLUETOOTH_MASK (1 << 0) +#define MSI_STANDARD_EC_WEBCAM_MASK (1 << 1) +#define MSI_STANDARD_EC_WLAN_MASK (1 << 3) + static int force; module_param(force, bool, 0); MODULE_PARM_DESC(force, "Force driver load, ignore DMI data"); @@ -74,6 +79,9 @@ static int auto_brightness; module_param(auto_brightness, int, 0); MODULE_PARM_DESC(auto_brightness, "Enable automatic brightness control (0: disabled; 1: enabled; 2: don't touch)"); +static bool old_ec_model; +static int wlan_s, bluetooth_s; + /* Hardware access */ static int set_lcd_level(int level) @@ -148,6 +156,22 @@ static int get_wireless_state(int *wlan, int *bluetooth) return 0; } +static int get_wireless_state_ec_standard(void) +{ + u8 rdata; + int result; + + result = ec_read(MSI_STANDARD_EC_COMMAND_ADDRESS, &rdata); + if (result < 0) + return -1; + + wlan_s = !!(rdata & MSI_STANDARD_EC_WLAN_MASK); + + bluetooth_s = !!(rdata & MSI_STANDARD_EC_BLUETOOTH_MASK); + + return 0; +} + /* Backlight device stuff */ static int bl_get_brightness(struct backlight_device *b) @@ -176,7 +200,12 @@ static ssize_t show_wlan(struct device *dev, int ret, enabled; - ret = get_wireless_state(&enabled, NULL); + if (old_ec_model) { + ret = get_wireless_state(&enabled, NULL); + } else { + ret = get_wireless_state_ec_standard(); + enabled = wlan_s; + } if (ret < 0) return ret; @@ -189,7 +218,12 @@ static ssize_t show_bluetooth(struct device *dev, int ret, enabled; - ret = get_wireless_state(NULL, &enabled); + if (old_ec_model) { + ret = get_wireless_state(NULL, &enabled); + } else { + ret = get_wireless_state_ec_standard(); + enabled = bluetooth_s; + } if (ret < 0) return ret; @@ -339,8 +373,8 @@ static int __init msi_init(void) if (acpi_disabled) return -ENODEV; - if (!force && !dmi_check_system(msi_dmi_table)) - return -ENODEV; + if (force || dmi_check_system(msi_dmi_table)) + old_ec_model = 1; if (auto_brightness < 0 || auto_brightness > 2) return -EINVAL; @@ -435,3 +469,4 @@ MODULE_ALIAS("dmi:*:svnMICRO-STARINT'LCO.,LTD:pnMS-1013:pvr0131*:cvnMICRO-STARIN MODULE_ALIAS("dmi:*:svnMicro-StarInternational:pnMS-1058:pvr0581:rvnMSI:rnMS-1058:*:ct10:*"); MODULE_ALIAS("dmi:*:svnMicro-StarInternational:pnMS-1412:*:rvnMSI:rnMS-1412:*:cvnMICRO-STARINT'LCO.,LTD:ct10:*"); MODULE_ALIAS("dmi:*:svnNOTEBOOK:pnSAM2000:pvr0131*:cvnMICRO-STARINT'LCO.,LTD:ct10:*"); +MODULE_ALIAS("dmi:*:svnMICRO-STARINTERNATIONAL*:pnMS-N034:*"); -- cgit v1.2.3 From fc0dc4c926e6b7afe680aecf809f48eef3faa182 Mon Sep 17 00:00:00 2001 From: "Lee, Chun-Yi" Date: Sat, 9 Jan 2010 23:17:07 +0800 Subject: msi-laptop: Add threeg sysfs file for support query 3G state by standard 66/62 ec command Add threeg sysfs file for support query 3G state by standard 66/62 ec command, the MSI standard ec interface supported this feature. Signed-off-by: Lee, Chun-Yi Cc: Lennart Poettering Signed-off-by: Greg Kroah-Hartman --- drivers/platform/x86/msi-laptop.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c index 323e99460c9f..1784d5588d41 100644 --- a/drivers/platform/x86/msi-laptop.c +++ b/drivers/platform/x86/msi-laptop.c @@ -70,6 +70,7 @@ #define MSI_STANDARD_EC_BLUETOOTH_MASK (1 << 0) #define MSI_STANDARD_EC_WEBCAM_MASK (1 << 1) #define MSI_STANDARD_EC_WLAN_MASK (1 << 3) +#define MSI_STANDARD_EC_3G_MASK (1 << 4) static int force; module_param(force, bool, 0); @@ -80,7 +81,7 @@ module_param(auto_brightness, int, 0); MODULE_PARM_DESC(auto_brightness, "Enable automatic brightness control (0: disabled; 1: enabled; 2: don't touch)"); static bool old_ec_model; -static int wlan_s, bluetooth_s; +static int wlan_s, bluetooth_s, threeg_s; /* Hardware access */ @@ -169,6 +170,8 @@ static int get_wireless_state_ec_standard(void) bluetooth_s = !!(rdata & MSI_STANDARD_EC_BLUETOOTH_MASK); + threeg_s = !!(rdata & MSI_STANDARD_EC_3G_MASK); + return 0; } @@ -230,6 +233,23 @@ static ssize_t show_bluetooth(struct device *dev, return sprintf(buf, "%i\n", enabled); } +static ssize_t show_threeg(struct device *dev, + struct device_attribute *attr, char *buf) +{ + + int ret; + + /* old msi ec not support 3G */ + if (old_ec_model) + return -1; + + ret = get_wireless_state_ec_standard(); + if (ret < 0) + return ret; + + return sprintf(buf, "%i\n", threeg_s); +} + static ssize_t show_lcd_level(struct device *dev, struct device_attribute *attr, char *buf) { @@ -292,6 +312,7 @@ static DEVICE_ATTR(lcd_level, 0644, show_lcd_level, store_lcd_level); static DEVICE_ATTR(auto_brightness, 0644, show_auto_brightness, store_auto_brightness); static DEVICE_ATTR(bluetooth, 0444, show_bluetooth, NULL); static DEVICE_ATTR(wlan, 0444, show_wlan, NULL); +static DEVICE_ATTR(threeg, 0444, show_threeg, NULL); static struct attribute *msipf_attributes[] = { &dev_attr_lcd_level.attr, @@ -412,6 +433,12 @@ static int __init msi_init(void) if (ret) goto fail_platform_device2; + if (!old_ec_model) { + ret = device_create_file(&msipf_device->dev, &dev_attr_threeg); + if (ret) + goto fail_platform_device2; + } + /* Disable automatic brightness control by default because * this module was probably loaded to do brightness control in * software. */ @@ -446,6 +473,8 @@ static void __exit msi_cleanup(void) { sysfs_remove_group(&msipf_device->dev.kobj, &msipf_attribute_group); + if (!old_ec_model) + device_remove_file(&msipf_device->dev, &dev_attr_threeg); platform_device_unregister(msipf_device); platform_driver_unregister(&msipf_driver); backlight_device_unregister(msibl_device); -- cgit v1.2.3 From 472ea12d1a265c868e1605abb59bf21f595eedfc Mon Sep 17 00:00:00 2001 From: "Lee, Chun-Yi" Date: Fri, 22 Jan 2010 00:15:59 +0800 Subject: msi-laptop: Support some MSI 3G netbook that is need load SCM Some MSI 3G netbook only have one fn key to control Wlan/Bluetooth/3G, those netbook will load the SCM (windows app) to disable the original Wlan/Bluetooth control by BIOS when user press fn key, then control Wlan/Bluetooth/3G by SCM (software control by OS). Without SCM, user cann't on/off 3G module on those 3G netbook. On Linux, msi-laptop driver will do the same thing to disable the original BIOS control, then might need use HAL or other userland application to do the software control that simulate with SCM. e.g. MSI N034 netbook Signed-off-by: Lee, Chun-Yi Cc: Lennart Poettering Signed-off-by: Greg Kroah-Hartman --- drivers/platform/x86/msi-laptop.c | 238 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 238 insertions(+) (limited to 'drivers') diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c index 1784d5588d41..ff21d1acf3be 100644 --- a/drivers/platform/x86/msi-laptop.c +++ b/drivers/platform/x86/msi-laptop.c @@ -58,6 +58,7 @@ #include #include #include +#include #define MSI_DRIVER_VERSION "0.5" @@ -72,6 +73,10 @@ #define MSI_STANDARD_EC_WLAN_MASK (1 << 3) #define MSI_STANDARD_EC_3G_MASK (1 << 4) +/* For set SCM load flag to disable BIOS fn key */ +#define MSI_STANDARD_EC_SCM_LOAD_ADDRESS 0x2d +#define MSI_STANDARD_EC_SCM_LOAD_MASK (1 << 0) + static int force; module_param(force, bool, 0); MODULE_PARM_DESC(force, "Force driver load, ignore DMI data"); @@ -83,6 +88,19 @@ MODULE_PARM_DESC(auto_brightness, "Enable automatic brightness control (0: disab static bool old_ec_model; static int wlan_s, bluetooth_s, threeg_s; +/* Some MSI 3G netbook only have one fn key to control Wlan/Bluetooth/3G, + * those netbook will load the SCM (windows app) to disable the original + * Wlan/Bluetooth control by BIOS when user press fn key, then control + * Wlan/Bluetooth/3G by SCM (software control by OS). Without SCM, user + * cann't on/off 3G module on those 3G netbook. + * On Linux, msi-laptop driver will do the same thing to disable the + * original BIOS control, then might need use HAL or other userland + * application to do the software control that simulate with SCM. + * e.g. MSI N034 netbook + */ +static bool load_scm_model; +static struct rfkill *rfk_wlan, *rfk_bluetooth, *rfk_threeg; + /* Hardware access */ static int set_lcd_level(int level) @@ -139,6 +157,35 @@ static int set_auto_brightness(int enable) return ec_transaction(MSI_EC_COMMAND_LCD_LEVEL, wdata, 2, NULL, 0, 1); } +static ssize_t set_device_state(const char *buf, size_t count, u8 mask) +{ + int status; + u8 wdata = 0, rdata; + int result; + + if (sscanf(buf, "%i", &status) != 1 || (status < 0 || status > 1)) + return -EINVAL; + + /* read current device state */ + result = ec_read(MSI_STANDARD_EC_COMMAND_ADDRESS, &rdata); + if (result < 0) + return -EINVAL; + + if (!!(rdata & mask) != status) { + /* reverse device bit */ + if (rdata & mask) + wdata = rdata & ~mask; + else + wdata = rdata | mask; + + result = ec_write(MSI_STANDARD_EC_COMMAND_ADDRESS, wdata); + if (result < 0) + return -EINVAL; + } + + return count; +} + static int get_wireless_state(int *wlan, int *bluetooth) { u8 wdata = 0, rdata; @@ -215,6 +262,12 @@ static ssize_t show_wlan(struct device *dev, return sprintf(buf, "%i\n", enabled); } +static ssize_t store_wlan(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + return set_device_state(buf, count, MSI_STANDARD_EC_WLAN_MASK); +} + static ssize_t show_bluetooth(struct device *dev, struct device_attribute *attr, char *buf) { @@ -233,6 +286,12 @@ static ssize_t show_bluetooth(struct device *dev, return sprintf(buf, "%i\n", enabled); } +static ssize_t store_bluetooth(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + return set_device_state(buf, count, MSI_STANDARD_EC_BLUETOOTH_MASK); +} + static ssize_t show_threeg(struct device *dev, struct device_attribute *attr, char *buf) { @@ -250,6 +309,12 @@ static ssize_t show_threeg(struct device *dev, return sprintf(buf, "%i\n", threeg_s); } +static ssize_t store_threeg(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + return set_device_state(buf, count, MSI_STANDARD_EC_3G_MASK); +} + static ssize_t show_lcd_level(struct device *dev, struct device_attribute *attr, char *buf) { @@ -387,6 +452,169 @@ static struct dmi_system_id __initdata msi_dmi_table[] = { { } }; +static struct dmi_system_id __initdata msi_load_scm_models_dmi_table[] = { + { + .ident = "MSI N034", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, + "MICRO-STAR INTERNATIONAL CO., LTD"), + DMI_MATCH(DMI_PRODUCT_NAME, "MS-N034"), + DMI_MATCH(DMI_CHASSIS_VENDOR, + "MICRO-STAR INTERNATIONAL CO., LTD") + }, + .callback = dmi_check_cb + }, + { } +}; + +static int rfkill_bluetooth_set(void *data, bool blocked) +{ + /* Do something with blocked...*/ + /* + * blocked == false is on + * blocked == true is off + */ + if (blocked) + set_device_state("0", 0, MSI_STANDARD_EC_BLUETOOTH_MASK); + else + set_device_state("1", 0, MSI_STANDARD_EC_BLUETOOTH_MASK); + + return 0; +} + +static int rfkill_wlan_set(void *data, bool blocked) +{ + if (blocked) + set_device_state("0", 0, MSI_STANDARD_EC_WLAN_MASK); + else + set_device_state("1", 0, MSI_STANDARD_EC_WLAN_MASK); + + return 0; +} + +static int rfkill_threeg_set(void *data, bool blocked) +{ + if (blocked) + set_device_state("0", 0, MSI_STANDARD_EC_3G_MASK); + else + set_device_state("1", 0, MSI_STANDARD_EC_3G_MASK); + + return 0; +} + +static struct rfkill_ops rfkill_bluetooth_ops = { + .set_block = rfkill_bluetooth_set +}; + +static struct rfkill_ops rfkill_wlan_ops = { + .set_block = rfkill_wlan_set +}; + +static struct rfkill_ops rfkill_threeg_ops = { + .set_block = rfkill_threeg_set +}; + +static void rfkill_cleanup(void) +{ + if (rfk_bluetooth) { + rfkill_unregister(rfk_bluetooth); + rfkill_destroy(rfk_bluetooth); + } + + if (rfk_threeg) { + rfkill_unregister(rfk_threeg); + rfkill_destroy(rfk_threeg); + } + + if (rfk_wlan) { + rfkill_unregister(rfk_wlan); + rfkill_destroy(rfk_wlan); + } +} + +static int rfkill_init(struct platform_device *sdev) +{ + /* add rfkill */ + int retval; + + rfk_bluetooth = rfkill_alloc("msi-bluetooth", &sdev->dev, + RFKILL_TYPE_BLUETOOTH, + &rfkill_bluetooth_ops, NULL); + if (!rfk_bluetooth) { + retval = -ENOMEM; + goto err_bluetooth; + } + retval = rfkill_register(rfk_bluetooth); + if (retval) + goto err_bluetooth; + + rfk_wlan = rfkill_alloc("msi-wlan", &sdev->dev, RFKILL_TYPE_WLAN, + &rfkill_wlan_ops, NULL); + if (!rfk_wlan) { + retval = -ENOMEM; + goto err_wlan; + } + retval = rfkill_register(rfk_wlan); + if (retval) + goto err_wlan; + + rfk_threeg = rfkill_alloc("msi-threeg", &sdev->dev, RFKILL_TYPE_WWAN, + &rfkill_threeg_ops, NULL); + if (!rfk_threeg) { + retval = -ENOMEM; + goto err_threeg; + } + retval = rfkill_register(rfk_threeg); + if (retval) + goto err_threeg; + + return 0; + +err_threeg: + rfkill_destroy(rfk_threeg); + if (rfk_wlan) + rfkill_unregister(rfk_wlan); +err_wlan: + rfkill_destroy(rfk_wlan); + if (rfk_bluetooth) + rfkill_unregister(rfk_bluetooth); +err_bluetooth: + rfkill_destroy(rfk_bluetooth); + + return retval; +} + +static int load_scm_model_init(struct platform_device *sdev) +{ + u8 data; + int result; + + /* allow userland write sysfs file */ + dev_attr_bluetooth.store = store_bluetooth; + dev_attr_wlan.store = store_wlan; + dev_attr_threeg.store = store_threeg; + dev_attr_bluetooth.attr.mode |= S_IWUSR; + dev_attr_wlan.attr.mode |= S_IWUSR; + dev_attr_threeg.attr.mode |= S_IWUSR; + + /* disable hardware control by fn key */ + result = ec_read(MSI_STANDARD_EC_SCM_LOAD_ADDRESS, &data); + if (result < 0) + return result; + + result = ec_write(MSI_STANDARD_EC_SCM_LOAD_ADDRESS, + data | MSI_STANDARD_EC_SCM_LOAD_MASK); + if (result < 0) + return result; + + /* initial rfkill */ + result = rfkill_init(sdev); + if (result < 0) + return result; + + return 0; +} + static int __init msi_init(void) { int ret; @@ -397,6 +625,9 @@ static int __init msi_init(void) if (force || dmi_check_system(msi_dmi_table)) old_ec_model = 1; + if (!old_ec_model && dmi_check_system(msi_load_scm_models_dmi_table)) + load_scm_model = 1; + if (auto_brightness < 0 || auto_brightness > 2) return -EINVAL; @@ -429,6 +660,11 @@ static int __init msi_init(void) if (ret) goto fail_platform_device1; + if (load_scm_model && (load_scm_model_init(msipf_device) < 0)) { + ret = -EINVAL; + goto fail_platform_device1; + } + ret = sysfs_create_group(&msipf_device->dev.kobj, &msipf_attribute_group); if (ret) goto fail_platform_device2; @@ -479,6 +715,8 @@ static void __exit msi_cleanup(void) platform_driver_unregister(&msipf_driver); backlight_device_unregister(msibl_device); + rfkill_cleanup(); + /* Enable automatic brightness control again */ if (auto_brightness != 2) set_auto_brightness(1); -- cgit v1.2.3 From ec766278ba927f3d3c75211ea7697aae37f327f0 Mon Sep 17 00:00:00 2001 From: "Lee, Chun-Yi" Date: Wed, 27 Jan 2010 00:13:45 +0800 Subject: msi-laptop: Add resume method for set the SCM load again Implement the resume method for set the load SCM flag after system reusme. Without this patch, the wifi function key on SCM model will back to BIOS control mode then confuse with the userland software control. e.g. MSI N034 Signed-off-by: Lee, Chun-Yi Cc: Lennart Poettering Signed-off-by: Greg Kroah-Hartman --- drivers/platform/x86/msi-laptop.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c index ff21d1acf3be..af1b62f76117 100644 --- a/drivers/platform/x86/msi-laptop.c +++ b/drivers/platform/x86/msi-laptop.c @@ -77,6 +77,8 @@ #define MSI_STANDARD_EC_SCM_LOAD_ADDRESS 0x2d #define MSI_STANDARD_EC_SCM_LOAD_MASK (1 << 0) +static int msi_laptop_resume(struct platform_device *device); + static int force; module_param(force, bool, 0); MODULE_PARM_DESC(force, "Force driver load, ignore DMI data"); @@ -395,7 +397,8 @@ static struct platform_driver msipf_driver = { .driver = { .name = "msi-laptop-pf", .owner = THIS_MODULE, - } + }, + .resume = msi_laptop_resume, }; static struct platform_device *msipf_device; @@ -584,6 +587,27 @@ err_bluetooth: return retval; } +static int msi_laptop_resume(struct platform_device *device) +{ + u8 data; + int result; + + if (!load_scm_model) + return 0; + + /* set load SCM to disable hardware control by fn key */ + result = ec_read(MSI_STANDARD_EC_SCM_LOAD_ADDRESS, &data); + if (result < 0) + return result; + + result = ec_write(MSI_STANDARD_EC_SCM_LOAD_ADDRESS, + data | MSI_STANDARD_EC_SCM_LOAD_MASK); + if (result < 0) + return result; + + return 0; +} + static int load_scm_model_init(struct platform_device *sdev) { u8 data; -- cgit v1.2.3 From e22388e71b8787b26dc33d023e5c1eec58865541 Mon Sep 17 00:00:00 2001 From: "Lee, Chun-Yi" Date: Wed, 27 Jan 2010 12:23:00 +0800 Subject: msi-laptop: Detect 3G device exists by standard ec command Detect 3G device exists by standard ec command. Driver will not create the threeg sysfs file and threeg rfkill interface if there have no internal 3G device in MSI notebook/netbook. Signed-off-by: Lee, Chun-Yi Cc: Lennart Poettering Signed-off-by: Greg Kroah-Hartman --- drivers/platform/x86/msi-laptop.c | 44 ++++++++++++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c index af1b62f76117..c2b05da4289a 100644 --- a/drivers/platform/x86/msi-laptop.c +++ b/drivers/platform/x86/msi-laptop.c @@ -79,6 +79,8 @@ static int msi_laptop_resume(struct platform_device *device); +#define MSI_STANDARD_EC_DEVICES_EXISTS_ADDRESS 0x2f + static int force; module_param(force, bool, 0); MODULE_PARM_DESC(force, "Force driver load, ignore DMI data"); @@ -89,6 +91,7 @@ MODULE_PARM_DESC(auto_brightness, "Enable automatic brightness control (0: disab static bool old_ec_model; static int wlan_s, bluetooth_s, threeg_s; +static int threeg_exists; /* Some MSI 3G netbook only have one fn key to control Wlan/Bluetooth/3G, * those netbook will load the SCM (windows app) to disable the original @@ -224,6 +227,20 @@ static int get_wireless_state_ec_standard(void) return 0; } +static int get_threeg_exists(void) +{ + u8 rdata; + int result; + + result = ec_read(MSI_STANDARD_EC_DEVICES_EXISTS_ADDRESS, &rdata); + if (result < 0) + return -1; + + threeg_exists = !!(rdata & MSI_STANDARD_EC_3G_MASK); + + return 0; +} + /* Backlight device stuff */ static int bl_get_brightness(struct backlight_device *b) @@ -561,15 +578,17 @@ static int rfkill_init(struct platform_device *sdev) if (retval) goto err_wlan; - rfk_threeg = rfkill_alloc("msi-threeg", &sdev->dev, RFKILL_TYPE_WWAN, - &rfkill_threeg_ops, NULL); - if (!rfk_threeg) { - retval = -ENOMEM; - goto err_threeg; + if (threeg_exists) { + rfk_threeg = rfkill_alloc("msi-threeg", &sdev->dev, + RFKILL_TYPE_WWAN, &rfkill_threeg_ops, NULL); + if (!rfk_threeg) { + retval = -ENOMEM; + goto err_threeg; + } + retval = rfkill_register(rfk_threeg); + if (retval) + goto err_threeg; } - retval = rfkill_register(rfk_threeg); - if (retval) - goto err_threeg; return 0; @@ -649,6 +668,9 @@ static int __init msi_init(void) if (force || dmi_check_system(msi_dmi_table)) old_ec_model = 1; + if (!old_ec_model) + get_threeg_exists(); + if (!old_ec_model && dmi_check_system(msi_load_scm_models_dmi_table)) load_scm_model = 1; @@ -694,7 +716,9 @@ static int __init msi_init(void) goto fail_platform_device2; if (!old_ec_model) { - ret = device_create_file(&msipf_device->dev, &dev_attr_threeg); + if (threeg_exists) + ret = device_create_file(&msipf_device->dev, + &dev_attr_threeg); if (ret) goto fail_platform_device2; } @@ -733,7 +757,7 @@ static void __exit msi_cleanup(void) { sysfs_remove_group(&msipf_device->dev.kobj, &msipf_attribute_group); - if (!old_ec_model) + if (!old_ec_model && threeg_exists) device_remove_file(&msipf_device->dev, &dev_attr_threeg); platform_device_unregister(msipf_device); platform_driver_unregister(&msipf_driver); -- cgit v1.2.3 From 410c17651998944630a95fbb286a50362de2dbb0 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 3 Feb 2010 14:24:28 -0800 Subject: msi-laptop: depends on RFKILL msi-laptop uses rfkill*() interfaces so it should depend on RFKILL. msi-laptop.c:(.text+0x1fcd1b): undefined reference to `rfkill_alloc' msi-laptop.c:(.text+0x1fcd76): undefined reference to `rfkill_register' msi-laptop.c:(.text+0x1fcdc8): undefined reference to `rfkill_destroy' msi-laptop.c:(.text+0x1fcdd9): undefined reference to `rfkill_unregister' This repairs "msi-laptop: Detect 3G device exists by standard ec command", which is in some gregkh tree. Signed-off-by: Randy Dunlap Cc: Lennart Poettering Cc: Lee, Chun-Yi Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- drivers/platform/x86/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index cd2ee6fce1b4..e631dbeafd79 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig @@ -150,6 +150,7 @@ config MSI_LAPTOP tristate "MSI Laptop Extras" depends on ACPI depends on BACKLIGHT_CLASS_DEVICE + depends on RFKILL ---help--- This is a driver for laptops built by MSI (MICRO-STAR INTERNATIONAL): -- cgit v1.2.3 From a8941dad1f12b4e8a87a517ed27f29d0209c817c Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 8 Mar 2010 13:33:17 +0900 Subject: sh: Support CPU affinity masks for INTC controllers. This hooks up the ->set_affinity() for the INTC controllers, which can be done as just a simple copy of the cpumask. The enable/disable paths already handle SMP register strides, so we just test the affinity mask in these paths to determine which strides to skip over. The early enable/disable path happens prior to the IRQs being registered, so we have no affinity mask established at that point, in which case we just default to CPU_MASK_ALL. This is left as it is to permit the force enable/disable code to retain existing semantics. Signed-off-by: Paul Mundt --- drivers/sh/intc.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c index 3a5a17db9474..b8983fed76f5 100644 --- a/drivers/sh/intc.c +++ b/drivers/sh/intc.c @@ -2,7 +2,7 @@ * Shared interrupt handling code for IPR and INTC2 types of IRQs. * * Copyright (C) 2007, 2008 Magnus Damm - * Copyright (C) 2009 Paul Mundt + * Copyright (C) 2009, 2010 Paul Mundt * * Based on intc2.c and ipr.c * @@ -26,6 +26,7 @@ #include #include #include +#include #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \ ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \ @@ -234,6 +235,10 @@ static inline void _intc_enable(unsigned int irq, unsigned long handle) unsigned int cpu; for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) { +#ifdef CONFIG_SMP + if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity)) + continue; +#endif addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu); intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\ [_INTC_FN(handle)], irq); @@ -253,6 +258,10 @@ static void intc_disable(unsigned int irq) unsigned int cpu; for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) { +#ifdef CONFIG_SMP + if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity)) + continue; +#endif addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu); intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\ [_INTC_FN(handle)], irq); @@ -301,6 +310,23 @@ static int intc_set_wake(unsigned int irq, unsigned int on) return 0; /* allow wakeup, but setup hardware in intc_suspend() */ } +#ifdef CONFIG_SMP +/* + * This is held with the irq desc lock held, so we don't require any + * additional locking here at the intc desc level. The affinity mask is + * later tested in the enable/disable paths. + */ +static int intc_set_affinity(unsigned int irq, const struct cpumask *cpumask) +{ + if (!cpumask_intersects(cpumask, cpu_online_mask)) + return -1; + + cpumask_copy(irq_to_desc(irq)->affinity, cpumask); + + return 0; +} +#endif + static void intc_mask_ack(unsigned int irq) { struct intc_desc_int *d = get_intc_desc(irq); @@ -843,6 +869,9 @@ void __init register_intc_controller(struct intc_desc *desc) d->chip.shutdown = intc_disable; d->chip.set_type = intc_set_sense; d->chip.set_wake = intc_set_wake; +#ifdef CONFIG_SMP + d->chip.set_affinity = intc_set_affinity; +#endif if (hw->ack_regs) { for (i = 0; i < hw->nr_ack_regs; i++) -- cgit v1.2.3 From 39f3be72c1a1b20d7e6e35717afa2ddb89259650 Mon Sep 17 00:00:00 2001 From: Wim Van Sebroeck Date: Mon, 8 Mar 2010 11:02:38 +0000 Subject: [WATCHDOG] i6300esb: fix unlock register with Before you can read or write from the i6300esb memeory mapped registers, you need to unlock these. This is done by writing the magic numbers 0x80 and 0x86 to the reload register. The size of the reload register is 32bit though. Also binary 11 is hex 0x03 and not 0x11. Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/i6300esb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/i6300esb.c b/drivers/watchdog/i6300esb.c index 2fbe7fea7ee6..3e00dc5b5a20 100644 --- a/drivers/watchdog/i6300esb.c +++ b/drivers/watchdog/i6300esb.c @@ -65,7 +65,7 @@ /* Config register bits */ #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */ #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */ -#define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */ +#define ESB_WDT_INTTYPE (0x03 << 0) /* Interrupt type on timer1 timeout */ /* Reload register bits */ #define ESB_WDT_TIMEOUT (0x01 << 9) /* Watchdog timed out */ @@ -111,8 +111,8 @@ MODULE_PARM_DESC(nowayout, */ static inline void esb_unlock_registers(void) { - writeb(ESB_UNLOCK1, ESB_RELOAD_REG); - writeb(ESB_UNLOCK2, ESB_RELOAD_REG); + writew(ESB_UNLOCK1, ESB_RELOAD_REG); + writew(ESB_UNLOCK2, ESB_RELOAD_REG); } static int esb_timer_start(void) -- cgit v1.2.3 From 91a970d9889c7d6f451ee91ed361d0f0119d3778 Mon Sep 17 00:00:00 2001 From: Hendrik Brueckner Date: Mon, 8 Mar 2010 12:25:15 +0100 Subject: [S390] hvc_iucv: allocate memory buffers for IUCV in zone DMA The device driver must allocate memory for IUCV buffers with GFP_DMA, because IUCV cannot address memory above 2GB (31bit addresses only). Because the IUCV ignores the higher bits of the address, sending and receiving IUCV data with this driver might cause memory corruptions. Signed-off-by: Hendrik Brueckner Signed-off-by: Martin Schwidefsky --- drivers/char/hvc_iucv.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/char/hvc_iucv.c b/drivers/char/hvc_iucv.c index 21681a81cc35..37b0542a4eeb 100644 --- a/drivers/char/hvc_iucv.c +++ b/drivers/char/hvc_iucv.c @@ -139,6 +139,8 @@ struct hvc_iucv_private *hvc_iucv_get_private(uint32_t num) * * This function allocates a new struct iucv_tty_buffer element and, optionally, * allocates an internal data buffer with the specified size @size. + * The internal data buffer is always allocated with GFP_DMA which is + * required for receiving and sending data with IUCV. * Note: The total message size arises from the internal buffer size and the * members of the iucv_tty_msg structure. * The function returns NULL if memory allocation has failed. @@ -154,7 +156,7 @@ static struct iucv_tty_buffer *alloc_tty_buffer(size_t size, gfp_t flags) if (size > 0) { bufp->msg.length = MSG_SIZE(size); - bufp->mbuf = kmalloc(bufp->msg.length, flags); + bufp->mbuf = kmalloc(bufp->msg.length, flags | GFP_DMA); if (!bufp->mbuf) { mempool_free(bufp, hvc_iucv_mempool); return NULL; @@ -237,7 +239,7 @@ static int hvc_iucv_write(struct hvc_iucv_private *priv, if (!rb->mbuf) { /* message not yet received ... */ /* allocate mem to store msg data; if no memory is available * then leave the buffer on the list and re-try later */ - rb->mbuf = kmalloc(rb->msg.length, GFP_ATOMIC); + rb->mbuf = kmalloc(rb->msg.length, GFP_ATOMIC | GFP_DMA); if (!rb->mbuf) return -ENOMEM; -- cgit v1.2.3 From 52898025cf7d458d029c18773d0ef49b4789d829 Mon Sep 17 00:00:00 2001 From: Nigel Hislop Date: Mon, 8 Mar 2010 12:25:16 +0100 Subject: [S390] dasd: security and PSF update patch for EMC CKD ioctl Remove the PSF order/suborder check from the Symmetrix CKD dasd ioctl. In exchange restrict the ioctl to CAP_SYS_ADMIN and CAP_SYS_RAWIO. Signed-off-by: Nigel Hislop Signed-off-by: Martin Schwidefsky --- drivers/s390/block/dasd_eckd.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/s390/block/dasd_eckd.c b/drivers/s390/block/dasd_eckd.c index 1cca21aafaba..d7163f904f40 100644 --- a/drivers/s390/block/dasd_eckd.c +++ b/drivers/s390/block/dasd_eckd.c @@ -2839,8 +2839,13 @@ static int dasd_symm_io(struct dasd_device *device, void __user *argp) char *psf_data, *rssd_result; struct dasd_ccw_req *cqr; struct ccw1 *ccw; + char psf0, psf1; int rc; + if (!capable(CAP_SYS_ADMIN) && !capable(CAP_SYS_RAWIO)) + return -EACCES; + psf0 = psf1 = 0; + /* Copy parms from caller */ rc = -EFAULT; if (copy_from_user(&usrparm, argp, sizeof(usrparm))) @@ -2869,12 +2874,8 @@ static int dasd_symm_io(struct dasd_device *device, void __user *argp) (void __user *)(unsigned long) usrparm.psf_data, usrparm.psf_data_len)) goto out_free; - - /* sanity check on syscall header */ - if (psf_data[0] != 0x17 && psf_data[1] != 0xce) { - rc = -EINVAL; - goto out_free; - } + psf0 = psf_data[0]; + psf1 = psf_data[1]; /* setup CCWs for PSF + RSSD */ cqr = dasd_smalloc_request(DASD_ECKD_MAGIC, 2 , 0, device); @@ -2925,7 +2926,9 @@ out_free: kfree(rssd_result); kfree(psf_data); out: - DBF_DEV_EVENT(DBF_WARNING, device, "Symmetrix ioctl: rc=%d", rc); + DBF_DEV_EVENT(DBF_WARNING, device, + "Symmetrix ioctl (0x%02x 0x%02x): rc=%d", + (int) psf0, (int) psf1, rc); return rc; } -- cgit v1.2.3 From a290156f479af436f94ac23f5729a1e33c94293b Mon Sep 17 00:00:00 2001 From: Sebastian Ott Date: Mon, 8 Mar 2010 12:25:17 +0100 Subject: [S390] cio: fix init_count in case of recognition after steal lock After we try to steal a lock on a ccw device in boxed state, we have to restart device recognition and potentially reprobing. In this case ccw_device_init_count was erroneously decreased twice. This patch fixes the issue. Signed-off-by: Sebastian Ott Signed-off-by: Martin Schwidefsky --- drivers/s390/cio/device.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/s390/cio/device.c b/drivers/s390/cio/device.c index c6abb75c4615..6d229f3523a0 100644 --- a/drivers/s390/cio/device.c +++ b/drivers/s390/cio/device.c @@ -764,7 +764,7 @@ static void sch_create_and_recog_new_device(struct subchannel *sch) static void io_subchannel_register(struct ccw_device *cdev) { struct subchannel *sch; - int ret; + int ret, adjust_init_count = 1; unsigned long flags; sch = to_subchannel(cdev->dev.parent); @@ -793,6 +793,7 @@ static void io_subchannel_register(struct ccw_device *cdev) cdev->private->dev_id.ssid, cdev->private->dev_id.devno); } + adjust_init_count = 0; goto out; } /* @@ -818,7 +819,7 @@ out: cdev->private->flags.recog_done = 1; wake_up(&cdev->private->wait_q); out_err: - if (atomic_dec_and_test(&ccw_device_init_count)) + if (adjust_init_count && atomic_dec_and_test(&ccw_device_init_count)) wake_up(&ccw_device_init_wq); } -- cgit v1.2.3 From bd6e8a162ecdec4f1d8895b0f330f75425993567 Mon Sep 17 00:00:00 2001 From: Ursula Braun Date: Mon, 8 Mar 2010 12:25:18 +0100 Subject: [S390] qdio: add missing bracket Add a missing bracket to only log the outbound handler event in the appropriate case. Signed-off-by: Ursula Braun Signed-off-by: Jan Glauber Signed-off-by: Martin Schwidefsky --- drivers/s390/cio/qdio_main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index 232ef047ba34..4f8f74311778 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -588,10 +588,11 @@ static void qdio_kick_handler(struct qdio_q *q) if (q->is_input_q) { qperf_inc(q, inbound_handler); DBF_DEV_EVENT(DBF_INFO, q->irq_ptr, "kih s:%02x c:%02x", start, count); - } else + } else { qperf_inc(q, outbound_handler); DBF_DEV_EVENT(DBF_INFO, q->irq_ptr, "koh: s:%02x c:%02x", start, count); + } q->handler(q->irq_ptr->cdev, q->qdio_error, q->nr, start, count, q->irq_ptr->int_parm); -- cgit v1.2.3 From 584dfddfce1bd81d877f14de2b56d4bc747af821 Mon Sep 17 00:00:00 2001 From: Ursula Braun Date: Mon, 8 Mar 2010 12:25:20 +0100 Subject: [S390] remove unused qdio flags in zfcp and qeth zfcp and qeth are setting flags for the qdio-layer, but these flags are not used in qdio. Patch removes the flag definitions from qdio and their settings in zfcp and qeth. Cc: Jan Glauber Cc: Christof Schmitt Signed-off-by: Ursula Braun Signed-off-by: Martin Schwidefsky --- arch/s390/include/asm/qdio.h | 7 ------- drivers/s390/cio/qdio_debug.c | 1 - drivers/s390/net/qeth_core_main.c | 3 --- drivers/s390/scsi/zfcp_qdio.c | 2 -- 4 files changed, 13 deletions(-) (limited to 'drivers') diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h index c666bfe5e984..9b04b1102bbc 100644 --- a/arch/s390/include/asm/qdio.h +++ b/arch/s390/include/asm/qdio.h @@ -321,11 +321,6 @@ typedef void qdio_handler_t(struct ccw_device *, unsigned int, int, #define QDIO_ERROR_ACTIVATE_CHECK_CONDITION 0x40 #define QDIO_ERROR_SLSB_STATE 0x80 -/* for qdio_initialize */ -#define QDIO_INBOUND_0COPY_SBALS 0x01 -#define QDIO_OUTBOUND_0COPY_SBALS 0x02 -#define QDIO_USE_OUTBOUND_PCIS 0x04 - /* for qdio_cleanup */ #define QDIO_FLAG_CLEANUP_USING_CLEAR 0x01 #define QDIO_FLAG_CLEANUP_USING_HALT 0x02 @@ -344,7 +339,6 @@ typedef void qdio_handler_t(struct ccw_device *, unsigned int, int, * @input_handler: handler to be called for input queues * @output_handler: handler to be called for output queues * @int_parm: interruption parameter - * @flags: initialization flags * @input_sbal_addr_array: address of no_input_qs * 128 pointers * @output_sbal_addr_array: address of no_output_qs * 128 pointers */ @@ -361,7 +355,6 @@ struct qdio_initialize { qdio_handler_t *input_handler; qdio_handler_t *output_handler; unsigned long int_parm; - unsigned long flags; void **input_sbal_addr_array; void **output_sbal_addr_array; }; diff --git a/drivers/s390/cio/qdio_debug.c b/drivers/s390/cio/qdio_debug.c index c94eb2a0fa2e..6ce83f56d537 100644 --- a/drivers/s390/cio/qdio_debug.c +++ b/drivers/s390/cio/qdio_debug.c @@ -33,7 +33,6 @@ void qdio_allocate_dbf(struct qdio_initialize *init_data, DBF_HEX(&init_data->input_handler, sizeof(void *)); DBF_HEX(&init_data->output_handler, sizeof(void *)); DBF_HEX(&init_data->int_parm, sizeof(long)); - DBF_HEX(&init_data->flags, sizeof(long)); DBF_HEX(&init_data->input_sbal_addr_array, sizeof(void *)); DBF_HEX(&init_data->output_sbal_addr_array, sizeof(void *)); DBF_EVENT("irq:%8lx", (unsigned long)irq_ptr); diff --git a/drivers/s390/net/qeth_core_main.c b/drivers/s390/net/qeth_core_main.c index fa8a519218ac..7d25bdd443cd 100644 --- a/drivers/s390/net/qeth_core_main.c +++ b/drivers/s390/net/qeth_core_main.c @@ -3805,9 +3805,6 @@ static int qeth_qdio_establish(struct qeth_card *card) init_data.input_handler = card->discipline.input_handler; init_data.output_handler = card->discipline.output_handler; init_data.int_parm = (unsigned long) card; - init_data.flags = QDIO_INBOUND_0COPY_SBALS | - QDIO_OUTBOUND_0COPY_SBALS | - QDIO_USE_OUTBOUND_PCIS; init_data.input_sbal_addr_array = (void **) in_sbal_ptrs; init_data.output_sbal_addr_array = (void **) out_sbal_ptrs; diff --git a/drivers/s390/scsi/zfcp_qdio.c b/drivers/s390/scsi/zfcp_qdio.c index 71b97ff77cf0..6479273a3094 100644 --- a/drivers/s390/scsi/zfcp_qdio.c +++ b/drivers/s390/scsi/zfcp_qdio.c @@ -319,8 +319,6 @@ static void zfcp_qdio_setup_init_data(struct qdio_initialize *id, id->input_handler = zfcp_qdio_int_resp; id->output_handler = zfcp_qdio_int_req; id->int_parm = (unsigned long) qdio; - id->flags = QDIO_INBOUND_0COPY_SBALS | - QDIO_OUTBOUND_0COPY_SBALS | QDIO_USE_OUTBOUND_PCIS; id->input_sbal_addr_array = (void **) (qdio->resp_q.sbal); id->output_sbal_addr_array = (void **) (qdio->req_q.sbal); -- cgit v1.2.3 From 33b62a30f78536b976183cc764c08038ac011e0a Mon Sep 17 00:00:00 2001 From: Stefan Weinhuber Date: Mon, 8 Mar 2010 12:26:24 +0100 Subject: [S390] dasd: automatic recognition of read-only devices In z/VM it is possible to attach a device as read-only. To prevent unintentional write requests and subsequent I/O errors, we can detect this configuration using the z/VM DIAG 210 interface and set the respective linux block device to read-only as well. Signed-off-by: Stefan Weinhuber Signed-off-by: Martin Schwidefsky --- drivers/s390/block/dasd.c | 36 ++++++++++++++++++++++++++++++++++++ drivers/s390/block/dasd_3990_erp.c | 4 ++++ drivers/s390/block/dasd_devmap.c | 13 ++++++++----- drivers/s390/block/dasd_diag.c | 6 ++---- drivers/s390/block/dasd_eckd.c | 10 ++++++++-- drivers/s390/block/dasd_fba.c | 10 ++++++++-- drivers/s390/block/dasd_genhd.c | 3 ++- drivers/s390/block/dasd_int.h | 7 +++++++ drivers/s390/block/dasd_ioctl.c | 6 ++++-- 9 files changed, 79 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/s390/block/dasd.c b/drivers/s390/block/dasd.c index 4951aa82e9f5..bbea90baf98f 100644 --- a/drivers/s390/block/dasd.c +++ b/drivers/s390/block/dasd.c @@ -26,6 +26,7 @@ #include #include #include +#include /* This is ugly... */ #define PRINTK_HEADER "dasd:" @@ -2212,6 +2213,13 @@ static int dasd_open(struct block_device *bdev, fmode_t mode) goto out; } + if ((mode & FMODE_WRITE) && + (test_bit(DASD_FLAG_DEVICE_RO, &base->flags) || + (base->features & DASD_FEATURE_READONLY))) { + rc = -EROFS; + goto out; + } + return 0; out: @@ -2289,6 +2297,34 @@ dasd_exit(void) * SECTION: common functions for ccw_driver use */ +/* + * Is the device read-only? + * Note that this function does not report the setting of the + * readonly device attribute, but how it is configured in z/VM. + */ +int dasd_device_is_ro(struct dasd_device *device) +{ + struct ccw_dev_id dev_id; + struct diag210 diag_data; + int rc; + + if (!MACHINE_IS_VM) + return 0; + ccw_device_get_id(device->cdev, &dev_id); + memset(&diag_data, 0, sizeof(diag_data)); + diag_data.vrdcdvno = dev_id.devno; + diag_data.vrdclen = sizeof(diag_data); + rc = diag210(&diag_data); + if (rc == 0 || rc == 2) { + return diag_data.vrdcvfla & 0x80; + } else { + DBF_EVENT(DBF_WARNING, "diag210 failed for dev=%04x with rc=%d", + dev_id.devno, rc); + return 0; + } +} +EXPORT_SYMBOL_GPL(dasd_device_is_ro); + static void dasd_generic_auto_online(void *data, async_cookie_t cookie) { struct ccw_device *cdev = data; diff --git a/drivers/s390/block/dasd_3990_erp.c b/drivers/s390/block/dasd_3990_erp.c index 44796ba4eb9b..51224f76b980 100644 --- a/drivers/s390/block/dasd_3990_erp.c +++ b/drivers/s390/block/dasd_3990_erp.c @@ -1045,6 +1045,10 @@ dasd_3990_erp_com_rej(struct dasd_ccw_req * erp, char *sense) erp->retries = 5; + } else if (sense[1] & SNS1_WRITE_INHIBITED) { + dev_err(&device->cdev->dev, "An I/O request was rejected" + " because writing is inhibited\n"); + erp = dasd_3990_erp_cleanup(erp, DASD_CQR_FAILED); } else { /* fatal error - set status to FAILED internal error 09 - Command Reject */ diff --git a/drivers/s390/block/dasd_devmap.c b/drivers/s390/block/dasd_devmap.c index d49766f3b940..8e23919c8704 100644 --- a/drivers/s390/block/dasd_devmap.c +++ b/drivers/s390/block/dasd_devmap.c @@ -742,6 +742,7 @@ dasd_ro_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct dasd_devmap *devmap; + struct dasd_device *device; int val; char *endp; @@ -758,12 +759,14 @@ dasd_ro_store(struct device *dev, struct device_attribute *attr, devmap->features |= DASD_FEATURE_READONLY; else devmap->features &= ~DASD_FEATURE_READONLY; - if (devmap->device) - devmap->device->features = devmap->features; - if (devmap->device && devmap->device->block - && devmap->device->block->gdp) - set_disk_ro(devmap->device->block->gdp, val); + device = devmap->device; + if (device) { + device->features = devmap->features; + val = val || test_bit(DASD_FLAG_DEVICE_RO, &device->flags); + } spin_unlock(&dasd_devmap_lock); + if (device && device->block && device->block->gdp) + set_disk_ro(device->block->gdp, val); return count; } diff --git a/drivers/s390/block/dasd_diag.c b/drivers/s390/block/dasd_diag.c index 6e14863f5c70..687f323cdc38 100644 --- a/drivers/s390/block/dasd_diag.c +++ b/drivers/s390/block/dasd_diag.c @@ -145,12 +145,10 @@ dasd_diag_erp(struct dasd_device *device) mdsk_term_io(device); rc = mdsk_init_io(device, device->block->bp_block, 0, NULL); if (rc == 4) { - if (!(device->features & DASD_FEATURE_READONLY)) { + if (!(test_and_set_bit(DASD_FLAG_DEVICE_RO, &device->flags))) pr_warning("%s: The access mode of a DIAG device " "changed to read-only\n", dev_name(&device->cdev->dev)); - device->features |= DASD_FEATURE_READONLY; - } rc = 0; } if (rc) @@ -449,7 +447,7 @@ dasd_diag_check_device(struct dasd_device *device) rc = -EIO; } else { if (rc == 4) - device->features |= DASD_FEATURE_READONLY; + set_bit(DASD_FLAG_DEVICE_RO, &device->flags); pr_info("%s: New DASD with %ld byte/block, total size %ld " "KB%s\n", dev_name(&device->cdev->dev), (unsigned long) block->bp_block, diff --git a/drivers/s390/block/dasd_eckd.c b/drivers/s390/block/dasd_eckd.c index d7163f904f40..01f4e7a34aa8 100644 --- a/drivers/s390/block/dasd_eckd.c +++ b/drivers/s390/block/dasd_eckd.c @@ -1089,6 +1089,7 @@ dasd_eckd_check_characteristics(struct dasd_device *device) struct dasd_eckd_private *private; struct dasd_block *block; int is_known, rc; + int readonly; if (!ccw_device_is_pathgroup(device->cdev)) { dev_warn(&device->cdev->dev, @@ -1182,15 +1183,20 @@ dasd_eckd_check_characteristics(struct dasd_device *device) else private->real_cyl = private->rdc_data.no_cyl; + readonly = dasd_device_is_ro(device); + if (readonly) + set_bit(DASD_FLAG_DEVICE_RO, &device->flags); + dev_info(&device->cdev->dev, "New DASD %04X/%02X (CU %04X/%02X) " - "with %d cylinders, %d heads, %d sectors\n", + "with %d cylinders, %d heads, %d sectors%s\n", private->rdc_data.dev_type, private->rdc_data.dev_model, private->rdc_data.cu_type, private->rdc_data.cu_model.model, private->real_cyl, private->rdc_data.trk_per_cyl, - private->rdc_data.sec_per_trk); + private->rdc_data.sec_per_trk, + readonly ? ", read-only device" : ""); return 0; out_err3: diff --git a/drivers/s390/block/dasd_fba.c b/drivers/s390/block/dasd_fba.c index 0f152444ac77..37282b90eecc 100644 --- a/drivers/s390/block/dasd_fba.c +++ b/drivers/s390/block/dasd_fba.c @@ -124,6 +124,7 @@ dasd_fba_check_characteristics(struct dasd_device *device) struct dasd_fba_private *private; struct ccw_device *cdev = device->cdev; int rc; + int readonly; private = (struct dasd_fba_private *) device->private; if (!private) { @@ -162,16 +163,21 @@ dasd_fba_check_characteristics(struct dasd_device *device) return rc; } + readonly = dasd_device_is_ro(device); + if (readonly) + set_bit(DASD_FLAG_DEVICE_RO, &device->flags); + dev_info(&device->cdev->dev, "New FBA DASD %04X/%02X (CU %04X/%02X) with %d MB " - "and %d B/blk\n", + "and %d B/blk%s\n", cdev->id.dev_type, cdev->id.dev_model, cdev->id.cu_type, cdev->id.cu_model, ((private->rdc_data.blk_bdsa * (private->rdc_data.blk_size >> 9)) >> 11), - private->rdc_data.blk_size); + private->rdc_data.blk_size, + readonly ? ", read-only device" : ""); return 0; } diff --git a/drivers/s390/block/dasd_genhd.c b/drivers/s390/block/dasd_genhd.c index 94f92a1247f2..30a1ca3d08b7 100644 --- a/drivers/s390/block/dasd_genhd.c +++ b/drivers/s390/block/dasd_genhd.c @@ -70,7 +70,8 @@ int dasd_gendisk_alloc(struct dasd_block *block) } len += sprintf(gdp->disk_name + len, "%c", 'a'+(base->devindex%26)); - if (block->base->features & DASD_FEATURE_READONLY) + if (base->features & DASD_FEATURE_READONLY || + test_bit(DASD_FLAG_DEVICE_RO, &base->flags)) set_disk_ro(gdp, 1); gdp->private_data = block; gdp->queue = block->request_queue; diff --git a/drivers/s390/block/dasd_int.h b/drivers/s390/block/dasd_int.h index ed73ce550822..a91d4a97d4f2 100644 --- a/drivers/s390/block/dasd_int.h +++ b/drivers/s390/block/dasd_int.h @@ -436,6 +436,10 @@ struct dasd_block { #define DASD_FLAG_OFFLINE 3 /* device is in offline processing */ #define DASD_FLAG_EER_SNSS 4 /* A SNSS is required */ #define DASD_FLAG_EER_IN_USE 5 /* A SNSS request is running */ +#define DASD_FLAG_DEVICE_RO 6 /* The device itself is read-only. Don't + * confuse this with the user specified + * read-only feature. + */ void dasd_put_device_wake(struct dasd_device *); @@ -609,6 +613,9 @@ char *dasd_get_sense(struct irb *); void dasd_device_set_stop_bits(struct dasd_device *, int); void dasd_device_remove_stop_bits(struct dasd_device *, int); +int dasd_device_is_ro(struct dasd_device *); + + /* externals in dasd_devmap.c */ extern int dasd_max_devindex; extern int dasd_probeonly; diff --git a/drivers/s390/block/dasd_ioctl.c b/drivers/s390/block/dasd_ioctl.c index 7039d9cf0fb4..3479f8158a1b 100644 --- a/drivers/s390/block/dasd_ioctl.c +++ b/drivers/s390/block/dasd_ioctl.c @@ -199,7 +199,8 @@ dasd_ioctl_format(struct block_device *bdev, void __user *argp) if (!argp) return -EINVAL; - if (block->base->features & DASD_FEATURE_READONLY) + if (block->base->features & DASD_FEATURE_READONLY || + test_bit(DASD_FLAG_DEVICE_RO, &block->base->flags)) return -EROFS; if (copy_from_user(&fdata, argp, sizeof(struct format_data_t))) return -EFAULT; @@ -349,7 +350,8 @@ dasd_ioctl_set_ro(struct block_device *bdev, void __user *argp) return -EINVAL; if (get_user(intval, (int __user *)argp)) return -EFAULT; - + if (!intval && test_bit(DASD_FLAG_DEVICE_RO, &block->base->flags)) + return -EROFS; set_disk_ro(bdev->bd_disk, intval); return dasd_set_feature(block->base->cdev, DASD_FEATURE_READONLY, intval); } -- cgit v1.2.3 From 09003ed90a2880de7e36b170a9298dd10d53e322 Mon Sep 17 00:00:00 2001 From: Hendrik Brueckner Date: Mon, 8 Mar 2010 12:26:25 +0100 Subject: [S390] smsgiucv: declare char pointers as "const" Declare the smsgiucv prefix char pointer as "const" and use use const char pointers in callback functions. Signed-off-by: Hendrik Brueckner Signed-off-by: Martin Schwidefsky --- arch/s390/mm/cmm.c | 2 +- drivers/s390/net/smsgiucv.c | 13 +++++++------ drivers/s390/net/smsgiucv.h | 6 ++++-- 3 files changed, 12 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/arch/s390/mm/cmm.c b/arch/s390/mm/cmm.c index 76a3637b88e0..f16bd04e39e9 100644 --- a/arch/s390/mm/cmm.c +++ b/arch/s390/mm/cmm.c @@ -374,7 +374,7 @@ static struct ctl_table cmm_dir_table[] = { #ifdef CONFIG_CMM_IUCV #define SMSG_PREFIX "CMM" static void -cmm_smsg_target(char *from, char *msg) +cmm_smsg_target(const char *from, char *msg) { long nr, seconds; diff --git a/drivers/s390/net/smsgiucv.c b/drivers/s390/net/smsgiucv.c index 67f2485d2372..3e666b6e77b4 100644 --- a/drivers/s390/net/smsgiucv.c +++ b/drivers/s390/net/smsgiucv.c @@ -31,9 +31,9 @@ struct smsg_callback { struct list_head list; - char *prefix; + const char *prefix; int len; - void (*callback)(char *from, char *str); + void (*callback)(const char *from, char *str); }; MODULE_AUTHOR @@ -100,8 +100,8 @@ static void smsg_message_pending(struct iucv_path *path, kfree(buffer); } -int smsg_register_callback(char *prefix, - void (*callback)(char *from, char *str)) +int smsg_register_callback(const char *prefix, + void (*callback)(const char *from, char *str)) { struct smsg_callback *cb; @@ -117,8 +117,9 @@ int smsg_register_callback(char *prefix, return 0; } -void smsg_unregister_callback(char *prefix, - void (*callback)(char *from, char *str)) +void smsg_unregister_callback(const char *prefix, + void (*callback)(const char *from, + char *str)) { struct smsg_callback *cb, *tmp; diff --git a/drivers/s390/net/smsgiucv.h b/drivers/s390/net/smsgiucv.h index 67f5d4f8378d..9410b45fde03 100644 --- a/drivers/s390/net/smsgiucv.h +++ b/drivers/s390/net/smsgiucv.h @@ -5,6 +5,8 @@ * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com) */ -int smsg_register_callback(char *, void (*)(char *, char *)); -void smsg_unregister_callback(char *, void (*)(char *, char *)); +int smsg_register_callback(const char *, + void (*)(const char *, char *)); +void smsg_unregister_callback(const char *, + void (*)(const char *, char *)); -- cgit v1.2.3 From 1ffaa640c6ba135aafc91841204e41846eae6841 Mon Sep 17 00:00:00 2001 From: Hendrik Brueckner Date: Mon, 8 Mar 2010 12:26:26 +0100 Subject: [S390] smsgiucv_app: deliver z/VM CP special messages (SMSG) as uevents The smsgiucv_app driver registers a callback with the smsgiucv driver to receive z/VM CP special messages (SMSG) starting with "APP". When the callback is called for special messages, the driver creates an uevent for the received message. The uevent consists of additional environment data containing the message prefix ("APP"), message sender, and message content. udev rules can be used to trigger application specific actions through matching the content or sender of the special message. Signed-off-by: Hendrik Brueckner Signed-off-by: Martin Schwidefsky --- drivers/s390/net/Kconfig | 10 ++ drivers/s390/net/Makefile | 1 + drivers/s390/net/smsgiucv.c | 2 +- drivers/s390/net/smsgiucv.h | 2 + drivers/s390/net/smsgiucv_app.c | 211 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 225 insertions(+), 1 deletion(-) create mode 100644 drivers/s390/net/smsgiucv_app.c (limited to 'drivers') diff --git a/drivers/s390/net/Kconfig b/drivers/s390/net/Kconfig index cb909a5b5047..977bb4d4ed15 100644 --- a/drivers/s390/net/Kconfig +++ b/drivers/s390/net/Kconfig @@ -43,6 +43,16 @@ config SMSGIUCV Select this option if you want to be able to receive SMSG messages from other VM guest systems. +config SMSGIUCV_EVENT + tristate "Deliver IUCV special messages as uevents (VM only)" + depends on SMSGIUCV + help + Select this option to deliver CP special messages (SMSGs) as + uevents. The driver handles only those special messages that + start with "APP". + + To compile as a module, choose M. The module name is "smsgiucv_app". + config CLAW tristate "CLAW device support" depends on CCW && NETDEVICES diff --git a/drivers/s390/net/Makefile b/drivers/s390/net/Makefile index 6cab5a62f99e..4dfe8c1092da 100644 --- a/drivers/s390/net/Makefile +++ b/drivers/s390/net/Makefile @@ -6,6 +6,7 @@ ctcm-y += ctcm_main.o ctcm_fsms.o ctcm_mpc.o ctcm_sysfs.o ctcm_dbug.o obj-$(CONFIG_CTCM) += ctcm.o fsm.o obj-$(CONFIG_NETIUCV) += netiucv.o fsm.o obj-$(CONFIG_SMSGIUCV) += smsgiucv.o +obj-$(CONFIG_SMSGIUCV_EVENT) += smsgiucv_app.o obj-$(CONFIG_LCS) += lcs.o obj-$(CONFIG_CLAW) += claw.o qeth-y += qeth_core_sys.o qeth_core_main.o qeth_core_mpc.o diff --git a/drivers/s390/net/smsgiucv.c b/drivers/s390/net/smsgiucv.c index 3e666b6e77b4..ecef1edee701 100644 --- a/drivers/s390/net/smsgiucv.c +++ b/drivers/s390/net/smsgiucv.c @@ -177,7 +177,7 @@ static const struct dev_pm_ops smsg_pm_ops = { static struct device_driver smsg_driver = { .owner = THIS_MODULE, - .name = "SMSGIUCV", + .name = SMSGIUCV_DRV_NAME, .bus = &iucv_bus, .pm = &smsg_pm_ops, }; diff --git a/drivers/s390/net/smsgiucv.h b/drivers/s390/net/smsgiucv.h index 9410b45fde03..149a1151608d 100644 --- a/drivers/s390/net/smsgiucv.h +++ b/drivers/s390/net/smsgiucv.h @@ -5,6 +5,8 @@ * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com) */ +#define SMSGIUCV_DRV_NAME "SMSGIUCV" + int smsg_register_callback(const char *, void (*)(const char *, char *)); void smsg_unregister_callback(const char *, diff --git a/drivers/s390/net/smsgiucv_app.c b/drivers/s390/net/smsgiucv_app.c new file mode 100644 index 000000000000..91579dc6a2b0 --- /dev/null +++ b/drivers/s390/net/smsgiucv_app.c @@ -0,0 +1,211 @@ +/* + * Deliver z/VM CP special messages (SMSG) as uevents. + * + * The driver registers for z/VM CP special messages with the + * "APP" prefix. Incoming messages are delivered to user space + * as uevents. + * + * Copyright IBM Corp. 2010 + * Author(s): Hendrik Brueckner + * + */ +#define KMSG_COMPONENT "smsgiucv_app" +#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "smsgiucv.h" + +/* prefix used for SMSG registration */ +#define SMSG_PREFIX "APP" + +/* SMSG related uevent environment variables */ +#define ENV_SENDER_STR "SMSG_SENDER=" +#define ENV_SENDER_LEN (strlen(ENV_SENDER_STR) + 8 + 1) +#define ENV_PREFIX_STR "SMSG_ID=" +#define ENV_PREFIX_LEN (strlen(ENV_PREFIX_STR) + \ + strlen(SMSG_PREFIX) + 1) +#define ENV_TEXT_STR "SMSG_TEXT=" +#define ENV_TEXT_LEN(msg) (strlen(ENV_TEXT_STR) + strlen((msg)) + 1) + +/* z/VM user ID which is permitted to send SMSGs + * If the value is undefined or empty (""), special messages are + * accepted from any z/VM user ID. */ +static char *sender; +module_param(sender, charp, 0400); +MODULE_PARM_DESC(sender, "z/VM user ID from which CP SMSGs are accepted"); + +/* SMSG device representation */ +static struct device *smsg_app_dev; + +/* list element for queuing received messages for delivery */ +struct smsg_app_event { + struct list_head list; + char *buf; + char *envp[4]; +}; + +/* queue for outgoing uevents */ +static LIST_HEAD(smsg_event_queue); +static DEFINE_SPINLOCK(smsg_event_queue_lock); + +static void smsg_app_event_free(struct smsg_app_event *ev) +{ + kfree(ev->buf); + kfree(ev); +} + +static struct smsg_app_event *smsg_app_event_alloc(const char *from, + const char *msg) +{ + struct smsg_app_event *ev; + + ev = kzalloc(sizeof(*ev), GFP_ATOMIC); + if (!ev) + return NULL; + + ev->buf = kzalloc(ENV_SENDER_LEN + ENV_PREFIX_LEN + + ENV_TEXT_LEN(msg), GFP_ATOMIC); + if (!ev->buf) { + kfree(ev); + return NULL; + } + + /* setting up environment pointers into buf */ + ev->envp[0] = ev->buf; + ev->envp[1] = ev->envp[0] + ENV_SENDER_LEN; + ev->envp[2] = ev->envp[1] + ENV_PREFIX_LEN; + ev->envp[3] = NULL; + + /* setting up environment: sender, prefix name, and message text */ + snprintf(ev->envp[0], ENV_SENDER_LEN, ENV_SENDER_STR "%s", from); + snprintf(ev->envp[1], ENV_PREFIX_LEN, ENV_PREFIX_STR "%s", SMSG_PREFIX); + snprintf(ev->envp[2], ENV_TEXT_LEN(msg), ENV_TEXT_STR "%s", msg); + + return ev; +} + +static void smsg_event_work_fn(struct work_struct *work) +{ + LIST_HEAD(event_queue); + struct smsg_app_event *p, *n; + struct device *dev; + + dev = get_device(smsg_app_dev); + if (!dev) + return; + + spin_lock_bh(&smsg_event_queue_lock); + list_splice_init(&smsg_event_queue, &event_queue); + spin_unlock_bh(&smsg_event_queue_lock); + + list_for_each_entry_safe(p, n, &event_queue, list) { + list_del(&p->list); + kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, p->envp); + smsg_app_event_free(p); + } + + put_device(dev); +} +static DECLARE_WORK(smsg_event_work, smsg_event_work_fn); + +static void smsg_app_callback(const char *from, char *msg) +{ + struct smsg_app_event *se; + + /* check if the originating z/VM user ID matches + * the configured sender. */ + if (sender && strlen(sender) > 0 && strcmp(from, sender) != 0) + return; + + /* get start of message text (skip prefix and leading blanks) */ + msg += strlen(SMSG_PREFIX); + while (*msg && isspace(*msg)) + msg++; + if (*msg == '\0') + return; + + /* allocate event list element and its environment */ + se = smsg_app_event_alloc(from, msg); + if (!se) + return; + + /* queue event and schedule work function */ + spin_lock(&smsg_event_queue_lock); + list_add_tail(&se->list, &smsg_event_queue); + spin_unlock(&smsg_event_queue_lock); + + schedule_work(&smsg_event_work); + return; +} + +static int __init smsgiucv_app_init(void) +{ + struct device_driver *smsgiucv_drv; + int rc; + + if (!MACHINE_IS_VM) + return -ENODEV; + + smsg_app_dev = kzalloc(sizeof(*smsg_app_dev), GFP_KERNEL); + if (!smsg_app_dev) + return -ENOMEM; + + smsgiucv_drv = driver_find(SMSGIUCV_DRV_NAME, &iucv_bus); + if (!smsgiucv_drv) { + kfree(smsg_app_dev); + return -ENODEV; + } + + rc = dev_set_name(smsg_app_dev, KMSG_COMPONENT); + if (rc) { + kfree(smsg_app_dev); + goto fail_put_driver; + } + smsg_app_dev->bus = &iucv_bus; + smsg_app_dev->parent = iucv_root; + smsg_app_dev->release = (void (*)(struct device *)) kfree; + smsg_app_dev->driver = smsgiucv_drv; + rc = device_register(smsg_app_dev); + if (rc) { + put_device(smsg_app_dev); + goto fail_put_driver; + } + + /* register with the smsgiucv device driver */ + rc = smsg_register_callback(SMSG_PREFIX, smsg_app_callback); + if (rc) { + device_unregister(smsg_app_dev); + goto fail_put_driver; + } + + rc = 0; +fail_put_driver: + put_driver(smsgiucv_drv); + return rc; +} +module_init(smsgiucv_app_init); + +static void __exit smsgiucv_app_exit(void) +{ + /* unregister callback */ + smsg_unregister_callback(SMSG_PREFIX, smsg_app_callback); + + /* cancel pending work and flush any queued event work */ + cancel_work_sync(&smsg_event_work); + smsg_event_work_fn(&smsg_event_work); + + device_unregister(smsg_app_dev); +} +module_exit(smsgiucv_app_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Deliver z/VM CP SMSG as uevents"); +MODULE_AUTHOR("Hendrik Brueckner "); -- cgit v1.2.3 From 2786095a58fd55931fa0298ff6e3914331edaaf2 Mon Sep 17 00:00:00 2001 From: Wim Van Sebroeck Date: Mon, 8 Mar 2010 13:48:01 +0000 Subject: [WATCHDOG] i6300esb.c: change platform_driver to pci_driver Since the intel 6300esb platform uses a dedicated PCI ID for it's watchdog timer (00:1d.4), it's better and easier to have this as a pci_driver. Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/i6300esb.c | 93 ++++++++++++++++----------------------------- 1 file changed, 33 insertions(+), 60 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/i6300esb.c b/drivers/watchdog/i6300esb.c index 3e00dc5b5a20..bb9750a03942 100644 --- a/drivers/watchdog/i6300esb.c +++ b/drivers/watchdog/i6300esb.c @@ -34,7 +34,6 @@ #include #include #include -#include #include #include #include @@ -42,7 +41,7 @@ #include /* Module and version information */ -#define ESB_VERSION "0.04" +#define ESB_VERSION "0.05" #define ESB_MODULE_NAME "i6300ESB timer" #define ESB_DRIVER_NAME ESB_MODULE_NAME ", v" ESB_VERSION #define PFX ESB_MODULE_NAME ": " @@ -82,7 +81,9 @@ static unsigned long timer_alive; static struct pci_dev *esb_pci; static unsigned short triggered; /* The status of the watchdog upon boot */ static char esb_expect_close; -static struct platform_device *esb_platform_device; + +/* We can only use 1 card due to the /dev/watchdog restriction */ +static int cards_found; /* module parameters */ /* 30 sec default heartbeat (1 < heartbeat < 2*1023) */ @@ -332,11 +333,6 @@ static struct miscdevice esb_miscdev = { /* * Data for PCI driver interface - * - * This data only exists for exporting the supported - * PCI ids via MODULE_DEVICE_TABLE. We do not actually - * register a pci_driver, because someone else might one day - * want to register another driver on the same PCI id. */ static struct pci_device_id esb_pci_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), }, @@ -348,29 +344,19 @@ MODULE_DEVICE_TABLE(pci, esb_pci_tbl); * Init & exit routines */ -static unsigned char __devinit esb_getdevice(void) +static unsigned char __devinit esb_getdevice(struct pci_dev *pdev) { - /* - * Find the PCI device - */ - - esb_pci = pci_get_device(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_ESB_9, NULL); - - if (!esb_pci) - return 0; - - if (pci_enable_device(esb_pci)) { + if (pci_enable_device(pdev)) { printk(KERN_ERR PFX "failed to enable device\n"); goto err_devput; } - if (pci_request_region(esb_pci, 0, ESB_MODULE_NAME)) { + if (pci_request_region(pdev, 0, ESB_MODULE_NAME)) { printk(KERN_ERR PFX "failed to request region\n"); goto err_disable; } - BASEADDR = pci_ioremap_bar(esb_pci, 0); + BASEADDR = pci_ioremap_bar(pdev, 0); if (BASEADDR == NULL) { /* Something's wrong here, BASEADDR has to be set */ printk(KERN_ERR PFX "failed to get BASEADDR\n"); @@ -378,14 +364,14 @@ static unsigned char __devinit esb_getdevice(void) } /* Done */ + esb_pci = pdev; return 1; err_release: - pci_release_region(esb_pci, 0); + pci_release_region(pdev, 0); err_disable: - pci_disable_device(esb_pci); + pci_disable_device(pdev); err_devput: - pci_dev_put(esb_pci); return 0; } @@ -430,12 +416,23 @@ static void __devinit esb_initdevice(void) esb_timer_set_heartbeat(heartbeat); } -static int __devinit esb_probe(struct platform_device *dev) +static int __devinit esb_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) { int ret; + cards_found++; + if (cards_found == 1) + printk(KERN_INFO PFX "Intel 6300ESB WatchDog Timer Driver v%s\n", + ESB_VERSION); + + if (cards_found > 1) { + printk(KERN_ERR PFX "This driver only supports 1 device\n"); + return -ENODEV; + } + /* Check whether or not the hardware watchdog is there */ - if (!esb_getdevice() || esb_pci == NULL) + if (!esb_getdevice(pdev) || esb_pci == NULL) return -ENODEV; /* Check that the heartbeat value is within it's range; @@ -467,11 +464,11 @@ err_unmap: iounmap(BASEADDR); pci_release_region(esb_pci, 0); pci_disable_device(esb_pci); - pci_dev_put(esb_pci); + esb_pci = NULL; return ret; } -static int __devexit esb_remove(struct platform_device *dev) +static void __devexit esb_remove(struct pci_dev *pdev) { /* Stop the timer before we leave */ if (!nowayout) @@ -482,54 +479,30 @@ static int __devexit esb_remove(struct platform_device *dev) iounmap(BASEADDR); pci_release_region(esb_pci, 0); pci_disable_device(esb_pci); - pci_dev_put(esb_pci); - return 0; + esb_pci = NULL; } -static void esb_shutdown(struct platform_device *dev) +static void esb_shutdown(struct pci_dev *pdev) { esb_timer_stop(); } -static struct platform_driver esb_platform_driver = { +static struct pci_driver esb_driver = { + .name = ESB_MODULE_NAME, + .id_table = esb_pci_tbl, .probe = esb_probe, .remove = __devexit_p(esb_remove), .shutdown = esb_shutdown, - .driver = { - .owner = THIS_MODULE, - .name = ESB_MODULE_NAME, - }, }; static int __init watchdog_init(void) { - int err; - - printk(KERN_INFO PFX "Intel 6300ESB WatchDog Timer Driver v%s\n", - ESB_VERSION); - - err = platform_driver_register(&esb_platform_driver); - if (err) - return err; - - esb_platform_device = platform_device_register_simple(ESB_MODULE_NAME, - -1, NULL, 0); - if (IS_ERR(esb_platform_device)) { - err = PTR_ERR(esb_platform_device); - goto unreg_platform_driver; - } - - return 0; - -unreg_platform_driver: - platform_driver_unregister(&esb_platform_driver); - return err; + return pci_register_driver(&esb_driver); } static void __exit watchdog_cleanup(void) { - platform_device_unregister(esb_platform_device); - platform_driver_unregister(&esb_platform_driver); + pci_unregister_driver(&esb_driver); printk(KERN_INFO PFX "Watchdog Module Unloaded.\n"); } -- cgit v1.2.3 From 0d9dc7c8b9b7fa0f53647423b41056ee1beed735 Mon Sep 17 00:00:00 2001 From: Gal Rosen Date: Thu, 21 Jan 2010 10:15:32 +0200 Subject: [SCSI] scsi_transport_fc: Fix synchronization issue while deleting vport The issue occur while deleting 60 virtual ports through the sys interface /sys/class/fc_vports/vport-X/vport_delete. It happen while in a mistake each request sent twice for the same vport. This interface is asynchronous, entering the delete request into a work queue, allowing more than one request to enter to the delete work queue. The result is a NULL pointer. The first request already delete the vport, while the second request got a pointer to the vport before the device destroyed. Re-create vport later cause system freeze. Solution: Check vport flags before entering the request to the work queue. [jejb: fixed int<->long problem on spinlock flags variable] Signed-off-by: Gal Rosen Acked-by: James Smart Cc: Stable Tree Signed-off-by: James Bottomley --- drivers/scsi/scsi_transport_fc.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/scsi_transport_fc.c b/drivers/scsi/scsi_transport_fc.c index 79660ee3e211..1d5b72173dd8 100644 --- a/drivers/scsi/scsi_transport_fc.c +++ b/drivers/scsi/scsi_transport_fc.c @@ -1232,6 +1232,15 @@ store_fc_vport_delete(struct device *dev, struct device_attribute *attr, { struct fc_vport *vport = transport_class_to_vport(dev); struct Scsi_Host *shost = vport_to_shost(vport); + unsigned long flags; + + spin_lock_irqsave(shost->host_lock, flags); + if (vport->flags & (FC_VPORT_DEL | FC_VPORT_CREATING)) { + spin_unlock_irqrestore(shost->host_lock, flags); + return -EBUSY; + } + vport->flags |= FC_VPORT_DELETING; + spin_unlock_irqrestore(shost->host_lock, flags); fc_queue_work(shost, &vport->vport_delete_work); return count; @@ -1821,6 +1830,9 @@ store_fc_host_vport_delete(struct device *dev, struct device_attribute *attr, list_for_each_entry(vport, &fc_host->vports, peers) { if ((vport->channel == 0) && (vport->port_name == wwpn) && (vport->node_name == wwnn)) { + if (vport->flags & (FC_VPORT_DEL | FC_VPORT_CREATING)) + break; + vport->flags |= FC_VPORT_DELETING; match = 1; break; } @@ -3370,18 +3382,6 @@ fc_vport_terminate(struct fc_vport *vport) unsigned long flags; int stat; - spin_lock_irqsave(shost->host_lock, flags); - if (vport->flags & FC_VPORT_CREATING) { - spin_unlock_irqrestore(shost->host_lock, flags); - return -EBUSY; - } - if (vport->flags & (FC_VPORT_DEL)) { - spin_unlock_irqrestore(shost->host_lock, flags); - return -EALREADY; - } - vport->flags |= FC_VPORT_DELETING; - spin_unlock_irqrestore(shost->host_lock, flags); - if (i->f->vport_delete) stat = i->f->vport_delete(vport); else -- cgit v1.2.3 From 500ca9ba241304937c54c379e515b24400379353 Mon Sep 17 00:00:00 2001 From: Ajit Khaparde Date: Sun, 7 Mar 2010 14:21:27 +0000 Subject: be2net: remove usage of be_pci_func When PCI functions are virtuialized in applications by assigning PCI functions to VM (PCI passthrough), the be2net driver in the VM sees a different function number. So, use of PCI function number in any calculation will break existing code. This patch takes care of it. Signed-off-by: Ajit Khaparde Signed-off-by: David S. Miller --- drivers/net/benet/be.h | 5 ----- drivers/net/benet/be_cmds.c | 6 ------ drivers/net/benet/be_main.c | 2 +- 3 files changed, 1 insertion(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/net/benet/be.h b/drivers/net/benet/be.h index be81fb2d10f7..8f0752553681 100644 --- a/drivers/net/benet/be.h +++ b/drivers/net/benet/be.h @@ -290,11 +290,6 @@ extern const struct ethtool_ops be_ethtool_ops; #define drvr_stats(adapter) (&adapter->stats.drvr_stats) -static inline unsigned int be_pci_func(struct be_adapter *adapter) -{ - return PCI_FUNC(adapter->pdev->devfn); -} - #define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops) #define PAGE_SHIFT_4K 12 diff --git a/drivers/net/benet/be_cmds.c b/drivers/net/benet/be_cmds.c index 4b1f80519ca4..c59215361f4e 100644 --- a/drivers/net/benet/be_cmds.c +++ b/drivers/net/benet/be_cmds.c @@ -465,8 +465,6 @@ int be_cmd_eq_create(struct be_adapter *adapter, req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); - AMAP_SET_BITS(struct amap_eq_context, func, req->context, - be_pci_func(adapter)); AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); /* 4byte eqe*/ AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); @@ -629,7 +627,6 @@ int be_cmd_cq_create(struct be_adapter *adapter, AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1); - AMAP_SET_BITS(struct amap_cq_context, func, ctxt, be_pci_func(adapter)); be_dws_cpu_to_le(ctxt, sizeof(req->context)); be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); @@ -678,7 +675,6 @@ int be_cmd_mccq_create(struct be_adapter *adapter, req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); - AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, be_pci_func(adapter)); AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1); AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt, be_encoded_q_len(mccq->len)); @@ -727,8 +723,6 @@ int be_cmd_txq_create(struct be_adapter *adapter, AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, be_encoded_q_len(txq->len)); - AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt, - be_pci_func(adapter)); AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1); AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id); diff --git a/drivers/net/benet/be_main.c b/drivers/net/benet/be_main.c index 22f787f2a30b..7c9b57eb780e 100644 --- a/drivers/net/benet/be_main.c +++ b/drivers/net/benet/be_main.c @@ -1382,7 +1382,7 @@ rx_eq_free: /* There are 8 evt ids per func. Retruns the evt id's bit number */ static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id) { - return eq_id - 8 * be_pci_func(adapter); + return eq_id % 8; } static irqreturn_t be_intx(int irq, void *dev) -- cgit v1.2.3 From 7e8a9298adf7531c58d73ba9c499353e3807cf19 Mon Sep 17 00:00:00 2001 From: Ajit Khaparde Date: Sun, 7 Mar 2010 14:23:44 +0000 Subject: be2net: remove unused code in be_load_fw This patch cleans up some unused code from be_load_fw(). Signed-off-by: Ajit Khaparde Signed-off-by: David S. Miller --- drivers/net/benet/be_main.c | 9 --------- 1 file changed, 9 deletions(-) (limited to 'drivers') diff --git a/drivers/net/benet/be_main.c b/drivers/net/benet/be_main.c index 7c9b57eb780e..43e8032f9236 100644 --- a/drivers/net/benet/be_main.c +++ b/drivers/net/benet/be_main.c @@ -1993,16 +1993,7 @@ int be_load_fw(struct be_adapter *adapter, u8 *func) struct be_dma_mem flash_cmd; int status, i = 0; const u8 *p; - char fw_ver[FW_VER_LEN]; - char fw_cfg; - status = be_cmd_get_fw_ver(adapter, fw_ver); - if (status) - return status; - - fw_cfg = *(fw_ver + 2); - if (fw_cfg == '0') - fw_cfg = '1'; strcpy(fw_file, func); status = request_firmware(&fw, fw_file, &adapter->pdev->dev); -- cgit v1.2.3 From 8bae5698616ac336938684ce7a7370299bd55d01 Mon Sep 17 00:00:00 2001 From: Sucheta Chakraborty Date: Mon, 8 Mar 2010 00:14:45 +0000 Subject: qlcnic: fix tx csum status Kernel default tx csum function (ethtool_op_get_tx_csum) doesn't show correct csum status. It takes various FLAGS (NETIF_F_ALL_CSUM) in account to show tx csum status, which driver doesn't set while disabling tx csum. Signed-off-by: Sucheta Chakraborty Signed-off-by: Amit Kumar Salecha Signed-off-by: David S. Miller --- drivers/net/qlcnic/qlcnic_ethtool.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/net/qlcnic/qlcnic_ethtool.c b/drivers/net/qlcnic/qlcnic_ethtool.c index 8da6ec8c13b9..ef12792a88be 100644 --- a/drivers/net/qlcnic/qlcnic_ethtool.c +++ b/drivers/net/qlcnic/qlcnic_ethtool.c @@ -785,6 +785,11 @@ qlcnic_get_ethtool_stats(struct net_device *dev, } } +static u32 qlcnic_get_tx_csum(struct net_device *dev) +{ + return dev->features & NETIF_F_IP_CSUM; +} + static u32 qlcnic_get_rx_csum(struct net_device *dev) { struct qlcnic_adapter *adapter = netdev_priv(dev); @@ -995,6 +1000,7 @@ const struct ethtool_ops qlcnic_ethtool_ops = { .set_ringparam = qlcnic_set_ringparam, .get_pauseparam = qlcnic_get_pauseparam, .set_pauseparam = qlcnic_set_pauseparam, + .get_tx_csum = qlcnic_get_tx_csum, .set_tx_csum = ethtool_op_set_tx_csum, .set_sg = ethtool_op_set_sg, .get_tso = qlcnic_get_tso, -- cgit v1.2.3 From 8bfe8b91b8b877066c8ac788f59a40324eaac6d8 Mon Sep 17 00:00:00 2001 From: Sucheta Chakraborty Date: Mon, 8 Mar 2010 00:14:46 +0000 Subject: qlcnic: additional driver statistics. Statistics added for lro/lso bytes, count for tx stop queue and wake queue and skb alloc failure count. Signed-off-by: Sucheta Chakraborty Signed-off-by: Amit Kumar Salecha Signed-off-by: David S. Miller --- drivers/net/qlcnic/qlcnic.h | 5 +++++ drivers/net/qlcnic/qlcnic_ethtool.c | 11 +++++++++++ drivers/net/qlcnic/qlcnic_hw.c | 1 + drivers/net/qlcnic/qlcnic_init.c | 8 ++++++-- drivers/net/qlcnic/qlcnic_main.c | 5 +++++ 5 files changed, 28 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/qlcnic/qlcnic.h b/drivers/net/qlcnic/qlcnic.h index b40a851ec7d1..9897b699752f 100644 --- a/drivers/net/qlcnic/qlcnic.h +++ b/drivers/net/qlcnic/qlcnic.h @@ -423,6 +423,11 @@ struct qlcnic_adapter_stats { u64 lro_pkts; u64 rxbytes; u64 txbytes; + u64 lrobytes; + u64 lso_frames; + u64 xmit_on; + u64 xmit_off; + u64 skb_alloc_failure; }; /* diff --git a/drivers/net/qlcnic/qlcnic_ethtool.c b/drivers/net/qlcnic/qlcnic_ethtool.c index ef12792a88be..f83e15fe3e1b 100644 --- a/drivers/net/qlcnic/qlcnic_ethtool.c +++ b/drivers/net/qlcnic/qlcnic_ethtool.c @@ -59,6 +59,17 @@ static const struct qlcnic_stats qlcnic_gstrings_stats[] = { QLC_SIZEOF(stats.rxbytes), QLC_OFF(stats.rxbytes)}, {"tx_bytes", QLC_SIZEOF(stats.txbytes), QLC_OFF(stats.txbytes)}, + {"lrobytes", + QLC_SIZEOF(stats.lrobytes), QLC_OFF(stats.lrobytes)}, + {"lso_frames", + QLC_SIZEOF(stats.lso_frames), QLC_OFF(stats.lso_frames)}, + {"xmit_on", + QLC_SIZEOF(stats.xmit_on), QLC_OFF(stats.xmit_on)}, + {"xmit_off", + QLC_SIZEOF(stats.xmit_off), QLC_OFF(stats.xmit_off)}, + {"skb_alloc_failure", QLC_SIZEOF(stats.skb_alloc_failure), + QLC_OFF(stats.skb_alloc_failure)}, + }; #define QLCNIC_STATS_LEN ARRAY_SIZE(qlcnic_gstrings_stats) diff --git a/drivers/net/qlcnic/qlcnic_hw.c b/drivers/net/qlcnic/qlcnic_hw.c index 99a4d1379d00..e95646bf7d56 100644 --- a/drivers/net/qlcnic/qlcnic_hw.c +++ b/drivers/net/qlcnic/qlcnic_hw.c @@ -349,6 +349,7 @@ qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter, if (nr_desc >= qlcnic_tx_avail(tx_ring)) { netif_tx_stop_queue(tx_ring->txq); __netif_tx_unlock_bh(tx_ring->txq); + adapter->stats.xmit_off++; return -EBUSY; } diff --git a/drivers/net/qlcnic/qlcnic_init.c b/drivers/net/qlcnic/qlcnic_init.c index ea00ab4d4feb..f0df9717aece 100644 --- a/drivers/net/qlcnic/qlcnic_init.c +++ b/drivers/net/qlcnic/qlcnic_init.c @@ -1114,8 +1114,10 @@ qlcnic_alloc_rx_skb(struct qlcnic_adapter *adapter, struct pci_dev *pdev = adapter->pdev; buffer->skb = dev_alloc_skb(rds_ring->skb_size); - if (!buffer->skb) + if (!buffer->skb) { + adapter->stats.skb_alloc_failure++; return -ENOMEM; + } skb = buffer->skb; @@ -1289,7 +1291,7 @@ qlcnic_process_lro(struct qlcnic_adapter *adapter, netif_receive_skb(skb); adapter->stats.lro_pkts++; - adapter->stats.rxbytes += length; + adapter->stats.lrobytes += length; return buffer; } @@ -1505,6 +1507,8 @@ qlcnic_process_rcv_diag(struct qlcnic_adapter *adapter, adapter->diag_cnt++; dev_kfree_skb_any(skb); + adapter->stats.rx_pkts++; + adapter->stats.rxbytes += length; return buffer; } diff --git a/drivers/net/qlcnic/qlcnic_main.c b/drivers/net/qlcnic/qlcnic_main.c index 665e8e56b6a8..fc721564e69e 100644 --- a/drivers/net/qlcnic/qlcnic_main.c +++ b/drivers/net/qlcnic/qlcnic_main.c @@ -118,6 +118,7 @@ qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter, if (qlcnic_tx_avail(tx_ring) <= TX_STOP_THRESH) { netif_stop_queue(adapter->netdev); smp_mb(); + adapter->stats.xmit_off++; } } @@ -1385,6 +1386,7 @@ qlcnic_tso_check(struct net_device *netdev, int copied, offset, copy_len, hdr_len = 0, tso = 0, vlan_oob = 0; struct cmd_desc_type0 *hwdesc; struct vlan_ethhdr *vh; + struct qlcnic_adapter *adapter = netdev_priv(netdev); if (protocol == cpu_to_be16(ETH_P_8021Q)) { @@ -1494,6 +1496,7 @@ qlcnic_tso_check(struct net_device *netdev, tx_ring->producer = producer; barrier(); + adapter->stats.lso_frames++; } static int @@ -1573,6 +1576,7 @@ qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev) if (unlikely(no_of_desc + 2 > qlcnic_tx_avail(tx_ring))) { netif_stop_queue(netdev); + adapter->stats.xmit_off++; return NETDEV_TX_BUSY; } @@ -1880,6 +1884,7 @@ static int qlcnic_process_cmd_ring(struct qlcnic_adapter *adapter) if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH) { netif_wake_queue(netdev); adapter->tx_timeo_cnt = 0; + adapter->stats.xmit_on++; } __netif_tx_unlock(tx_ring->txq); } -- cgit v1.2.3 From 9ab17b3968f9521bb4fffd8767953d2b0148aad0 Mon Sep 17 00:00:00 2001 From: Sucheta Chakraborty Date: Mon, 8 Mar 2010 00:14:47 +0000 Subject: qlcnic: fix multicast handling For promiscuous mode, driver send request to device for deleting multicast addresses and again it send request for adding them back while exiting from this mode, this is bad for performance. Just setting device in promiscuous mode is enough, no need to del/add multicast addresses. Signed-off-by: Sucheta Chakraborty Signed-off-by: Amit Kumar Salecha Signed-off-by: David S. Miller --- drivers/net/qlcnic/qlcnic_hw.c | 31 ++++++------------------------- 1 file changed, 6 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/net/qlcnic/qlcnic_hw.c b/drivers/net/qlcnic/qlcnic_hw.c index e95646bf7d56..da00e162b6d3 100644 --- a/drivers/net/qlcnic/qlcnic_hw.c +++ b/drivers/net/qlcnic/qlcnic_hw.c @@ -398,20 +398,16 @@ qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr, return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); } -static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, - u8 *addr, struct list_head *del_list) +static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr) { struct list_head *head; struct qlcnic_mac_list_s *cur; /* look up if already exists */ - list_for_each(head, del_list) { + list_for_each(head, &adapter->mac_list) { cur = list_entry(head, struct qlcnic_mac_list_s, list); - - if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) { - list_move_tail(head, &adapter->mac_list); + if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) return 0; - } } cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC); @@ -433,14 +429,9 @@ void qlcnic_set_multi(struct net_device *netdev) struct dev_mc_list *mc_ptr; u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; u32 mode = VPORT_MISS_MODE_DROP; - LIST_HEAD(del_list); - struct list_head *head; - struct qlcnic_mac_list_s *cur; - list_splice_tail_init(&adapter->mac_list, &del_list); - - qlcnic_nic_add_mac(adapter, adapter->mac_addr, &del_list); - qlcnic_nic_add_mac(adapter, bcast_addr, &del_list); + qlcnic_nic_add_mac(adapter, adapter->mac_addr); + qlcnic_nic_add_mac(adapter, bcast_addr); if (netdev->flags & IFF_PROMISC) { mode = VPORT_MISS_MODE_ACCEPT_ALL; @@ -455,22 +446,12 @@ void qlcnic_set_multi(struct net_device *netdev) if (!netdev_mc_empty(netdev)) { netdev_for_each_mc_addr(mc_ptr, netdev) { - qlcnic_nic_add_mac(adapter, mc_ptr->dmi_addr, - &del_list); + qlcnic_nic_add_mac(adapter, mc_ptr->dmi_addr); } } send_fw_cmd: qlcnic_nic_set_promisc(adapter, mode); - head = &del_list; - while (!list_empty(head)) { - cur = list_entry(head->next, struct qlcnic_mac_list_s, list); - - qlcnic_sre_macaddr_change(adapter, - cur->mac_addr, QLCNIC_MAC_DEL); - list_del(&cur->list); - kfree(cur); - } } int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode) -- cgit v1.2.3 From b7eff1007fea3d153a9a5c0f872304ec19412bbb Mon Sep 17 00:00:00 2001 From: Sucheta Chakraborty Date: Mon, 8 Mar 2010 00:14:48 +0000 Subject: qlcnic: validate unified fw image Validate all sections of unified fw image, before accessing them, to avoid seg fault. Signed-off-by: Sucheta Chakraborty Signed-off-by: Amit Kumar Salecha Signed-off-by: David S. Miller --- drivers/net/qlcnic/qlcnic_init.c | 146 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 139 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/net/qlcnic/qlcnic_init.c b/drivers/net/qlcnic/qlcnic_init.c index f0df9717aece..21a6e9f3dac5 100644 --- a/drivers/net/qlcnic/qlcnic_init.c +++ b/drivers/net/qlcnic/qlcnic_init.c @@ -568,21 +568,123 @@ struct uni_table_desc *qlcnic_get_table_desc(const u8 *unirom, int section) return NULL; } +#define FILEHEADER_SIZE (14 * 4) + static int -qlcnic_set_product_offs(struct qlcnic_adapter *adapter) +qlcnic_validate_header(struct qlcnic_adapter *adapter) { - struct uni_table_desc *ptab_descr; const u8 *unirom = adapter->fw->data; - u32 i; + struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0]; + __le32 fw_file_size = adapter->fw->size; __le32 entries; + __le32 entry_size; + __le32 tab_size; + + if (fw_file_size < FILEHEADER_SIZE) + return -EINVAL; + + entries = cpu_to_le32(directory->num_entries); + entry_size = cpu_to_le32(directory->entry_size); + tab_size = cpu_to_le32(directory->findex) + (entries * entry_size); + + if (fw_file_size < tab_size) + return -EINVAL; + + return 0; +} + +static int +qlcnic_validate_bootld(struct qlcnic_adapter *adapter) +{ + struct uni_table_desc *tab_desc; + struct uni_data_desc *descr; + const u8 *unirom = adapter->fw->data; + int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] + + QLCNIC_UNI_BOOTLD_IDX_OFF)); + __le32 offs; + __le32 tab_size; + __le32 data_size; + + tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_BOOTLD); + + if (!tab_desc) + return -EINVAL; + + tab_size = cpu_to_le32(tab_desc->findex) + + (cpu_to_le32(tab_desc->entry_size * (idx + 1))); + + if (adapter->fw->size < tab_size) + return -EINVAL; + + offs = cpu_to_le32(tab_desc->findex) + + (cpu_to_le32(tab_desc->entry_size) * (idx)); + descr = (struct uni_data_desc *)&unirom[offs]; + + data_size = descr->findex + cpu_to_le32(descr->size); + + if (adapter->fw->size < data_size) + return -EINVAL; + + return 0; +} + +static int +qlcnic_validate_fw(struct qlcnic_adapter *adapter) +{ + struct uni_table_desc *tab_desc; + struct uni_data_desc *descr; + const u8 *unirom = adapter->fw->data; + int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] + + QLCNIC_UNI_FIRMWARE_IDX_OFF)); + __le32 offs; + __le32 tab_size; + __le32 data_size; + + tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_FW); + + if (!tab_desc) + return -EINVAL; + + tab_size = cpu_to_le32(tab_desc->findex) + + (cpu_to_le32(tab_desc->entry_size * (idx + 1))); + + if (adapter->fw->size < tab_size) + return -EINVAL; + + offs = cpu_to_le32(tab_desc->findex) + + (cpu_to_le32(tab_desc->entry_size) * (idx)); + descr = (struct uni_data_desc *)&unirom[offs]; + data_size = descr->findex + cpu_to_le32(descr->size); + + if (adapter->fw->size < data_size) + return -EINVAL; + + return 0; +} + +static int +qlcnic_validate_product_offs(struct qlcnic_adapter *adapter) +{ + struct uni_table_desc *ptab_descr; + const u8 *unirom = adapter->fw->data; int mn_present = qlcnic_has_mn(adapter); + __le32 entries; + __le32 entry_size; + __le32 tab_size; + u32 i; ptab_descr = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_PRODUCT_TBL); - if (ptab_descr == NULL) - return -1; + if (!ptab_descr) + return -EINVAL; entries = cpu_to_le32(ptab_descr->num_entries); + entry_size = cpu_to_le32(ptab_descr->entry_size); + tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size); + + if (adapter->fw->size < tab_size) + return -EINVAL; + nomn: for (i = 0; i < entries; i++) { @@ -609,7 +711,37 @@ nomn: mn_present = 0; goto nomn; } - return -1; + return -EINVAL; +} + +static int +qlcnic_validate_unified_romimage(struct qlcnic_adapter *adapter) +{ + if (qlcnic_validate_header(adapter)) { + dev_err(&adapter->pdev->dev, + "unified image: header validation failed\n"); + return -EINVAL; + } + + if (qlcnic_validate_product_offs(adapter)) { + dev_err(&adapter->pdev->dev, + "unified image: product validation failed\n"); + return -EINVAL; + } + + if (qlcnic_validate_bootld(adapter)) { + dev_err(&adapter->pdev->dev, + "unified image: bootld validation failed\n"); + return -EINVAL; + } + + if (qlcnic_validate_fw(adapter)) { + dev_err(&adapter->pdev->dev, + "unified image: firmware validation failed\n"); + return -EINVAL; + } + + return 0; } static @@ -858,7 +990,7 @@ qlcnic_validate_firmware(struct qlcnic_adapter *adapter) u8 fw_type = adapter->fw_type; if (fw_type == QLCNIC_UNIFIED_ROMIMAGE) { - if (qlcnic_set_product_offs(adapter)) + if (qlcnic_validate_unified_romimage(adapter)) return -EINVAL; min_size = QLCNIC_UNI_FW_MIN_SIZE; -- cgit v1.2.3 From addd5abf49be31787aeb6203d266e0bd31a3fadd Mon Sep 17 00:00:00 2001 From: Amit Kumar Salecha Date: Mon, 8 Mar 2010 00:14:49 +0000 Subject: qlcnic: fix bios version check Bios sub version from unified fw image is calculated incorrect. Signed-off-by: Amit Kumar Salecha Signed-off-by: David S. Miller --- drivers/net/qlcnic/qlcnic_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/qlcnic/qlcnic_init.c b/drivers/net/qlcnic/qlcnic_init.c index 21a6e9f3dac5..7c34e4e29b3f 100644 --- a/drivers/net/qlcnic/qlcnic_init.c +++ b/drivers/net/qlcnic/qlcnic_init.c @@ -847,7 +847,7 @@ qlcnic_get_bios_version(struct qlcnic_adapter *adapter) bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off]) + QLCNIC_UNI_BIOS_VERSION_OFF)); - return (bios_ver << 24) + ((bios_ver >> 8) & 0xff00) + (bios_ver >> 24); + return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) + (bios_ver >> 24); } int -- cgit v1.2.3 From 1515faf2f995add976d4428bbc1583a4a0c81e5f Mon Sep 17 00:00:00 2001 From: Amit Kumar Salecha Date: Mon, 8 Mar 2010 00:14:50 +0000 Subject: qlcnic: remove extra space from board names Signed-off-by: Amit Kumar Salecha Signed-off-by: David S. Miller --- drivers/net/qlcnic/qlcnic.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/net/qlcnic/qlcnic.h b/drivers/net/qlcnic/qlcnic.h index 9897b699752f..0da94b208db1 100644 --- a/drivers/net/qlcnic/qlcnic.h +++ b/drivers/net/qlcnic/qlcnic.h @@ -1100,11 +1100,11 @@ struct qlcnic_brdinfo { static const struct qlcnic_brdinfo qlcnic_boards[] = { {0x1077, 0x8020, 0x1077, 0x203, - "8200 Series Single Port 10GbE Converged Network Adapter \ - (TCP/IP Networking)"}, + "8200 Series Single Port 10GbE Converged Network Adapter " + "(TCP/IP Networking)"}, {0x1077, 0x8020, 0x1077, 0x207, - "8200 Series Dual Port 10GbE Converged Network Adapter \ - (TCP/IP Networking)"}, + "8200 Series Dual Port 10GbE Converged Network Adapter " + "(TCP/IP Networking)"}, {0x1077, 0x8020, 0x1077, 0x20b, "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"}, {0x1077, 0x8020, 0x1077, 0x20c, -- cgit v1.2.3 From 77d3926306bf4eecac50150ba5625797219f14ba Mon Sep 17 00:00:00 2001 From: Meelis Roos Date: Mon, 8 Mar 2010 10:53:08 -0800 Subject: qlogicpti: Remove slash in QlogicPTI irq name qlogicpti driver registers its irq with a name containing slash. This results in [ 71.049735] WARNING: at fs/proc/generic.c:316 __xlate_proc_name+0xa8/0xb8() [ 71.132815] name 'Qlogic/PTI' because proc_mkdir with the name of the irq fails. Fix it by just removing the slash from irq name. Discovered and tested on real hardware (Sun Ultra 1). Signed-off-by: Meelis Roos Signed-off-by: David S. Miller --- drivers/scsi/qlogicpti.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/scsi/qlogicpti.c b/drivers/scsi/qlogicpti.c index fa34b92850a6..1b8217076b0e 100644 --- a/drivers/scsi/qlogicpti.c +++ b/drivers/scsi/qlogicpti.c @@ -738,7 +738,7 @@ static int __devinit qpti_register_irq(struct qlogicpti *qpti) * sanely maintain. */ if (request_irq(qpti->irq, qpti_intr, - IRQF_SHARED, "Qlogic/PTI", qpti)) + IRQF_SHARED, "QlogicPTI", qpti)) goto fail; printk("qlogicpti%d: IRQ %d ", qpti->qpti_id, qpti->irq); -- cgit v1.2.3 From f6bb13aa1ea3bb26a4c783822347873f085b9000 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Thu, 4 Mar 2010 01:52:58 +0100 Subject: ACPI / EC / PM: Close race between EC and resume from hibernation There is a race between resume from hibernation and the EC driver that may result in restoring the hibernation image in the middle of an EC transaction in progress, which in turn may lead to unpredictable behavior of the platform. To remove that race condition, add a helpers for suspending and resuming EC transactions in a safe way to be executed by the ACPI platform hibernate pre-restore and restore cleanup callbacks. http://bugzilla.kernel.org/show_bug.cgi?id=14668 Signed-off-by: Rafael J. Wysocki Reported-and-tested-by: Maxim Levitsky Signed-off-by: Len Brown --- drivers/acpi/ec.c | 33 ++++++++++++++++++++++++++++++++- drivers/acpi/internal.h | 2 ++ drivers/acpi/sleep.c | 19 ++++++++++++++----- 3 files changed, 48 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c index d6471bb6852f..19f93e114225 100644 --- a/drivers/acpi/ec.c +++ b/drivers/acpi/ec.c @@ -76,8 +76,9 @@ enum ec_command { enum { EC_FLAGS_QUERY_PENDING, /* Query is pending */ EC_FLAGS_GPE_STORM, /* GPE storm detected */ - EC_FLAGS_HANDLERS_INSTALLED /* Handlers for GPE and + EC_FLAGS_HANDLERS_INSTALLED, /* Handlers for GPE and * OpReg are installed */ + EC_FLAGS_FROZEN, /* Transactions are suspended */ }; /* If we find an EC via the ECDT, we need to keep a ptr to its context */ @@ -291,6 +292,10 @@ static int acpi_ec_transaction(struct acpi_ec *ec, struct transaction *t) if (t->rdata) memset(t->rdata, 0, t->rlen); mutex_lock(&ec->lock); + if (test_bit(EC_FLAGS_FROZEN, &ec->flags)) { + status = -EINVAL; + goto unlock; + } if (ec->global_lock) { status = acpi_acquire_global_lock(ACPI_EC_UDELAY_GLK, &glk); if (ACPI_FAILURE(status)) { @@ -445,6 +450,32 @@ int ec_transaction(u8 command, EXPORT_SYMBOL(ec_transaction); +void acpi_ec_suspend_transactions(void) +{ + struct acpi_ec *ec = first_ec; + + if (!ec) + return; + + mutex_lock(&ec->lock); + /* Prevent transactions from being carried out */ + set_bit(EC_FLAGS_FROZEN, &ec->flags); + mutex_unlock(&ec->lock); +} + +void acpi_ec_resume_transactions(void) +{ + struct acpi_ec *ec = first_ec; + + if (!ec) + return; + + mutex_lock(&ec->lock); + /* Allow transactions to be carried out again */ + clear_bit(EC_FLAGS_FROZEN, &ec->flags); + mutex_unlock(&ec->lock); +} + static int acpi_ec_query_unlocked(struct acpi_ec *ec, u8 * data) { int result; diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h index cb28e0502acc..78742460f1fc 100644 --- a/drivers/acpi/internal.h +++ b/drivers/acpi/internal.h @@ -51,6 +51,8 @@ void acpi_early_processor_set_pdc(void); int acpi_ec_init(void); int acpi_ec_ecdt_probe(void); int acpi_boot_ec_enable(void); +void acpi_ec_suspend_transactions(void); +void acpi_ec_resume_transactions(void); /*-------------------------------------------------------------------------- Suspend/Resume diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c index 79d33d908b5a..f01f8e84fd3d 100644 --- a/drivers/acpi/sleep.c +++ b/drivers/acpi/sleep.c @@ -552,8 +552,17 @@ static void acpi_hibernation_leave(void) hibernate_nvs_restore(); } -static void acpi_pm_enable_gpes(void) +static int acpi_pm_pre_restore(void) { + acpi_disable_all_gpes(); + acpi_os_wait_events_complete(NULL); + acpi_ec_suspend_transactions(); + return 0; +} + +static void acpi_pm_restore_cleanup(void) +{ + acpi_ec_resume_transactions(); acpi_enable_all_runtime_gpes(); } @@ -565,8 +574,8 @@ static struct platform_hibernation_ops acpi_hibernation_ops = { .prepare = acpi_pm_prepare, .enter = acpi_hibernation_enter, .leave = acpi_hibernation_leave, - .pre_restore = acpi_pm_disable_gpes, - .restore_cleanup = acpi_pm_enable_gpes, + .pre_restore = acpi_pm_pre_restore, + .restore_cleanup = acpi_pm_restore_cleanup, }; /** @@ -618,8 +627,8 @@ static struct platform_hibernation_ops acpi_hibernation_ops_old = { .prepare = acpi_pm_disable_gpes, .enter = acpi_hibernation_enter, .leave = acpi_hibernation_leave, - .pre_restore = acpi_pm_disable_gpes, - .restore_cleanup = acpi_pm_enable_gpes, + .pre_restore = acpi_pm_pre_restore, + .restore_cleanup = acpi_pm_restore_cleanup, .recover = acpi_pm_finish, }; #endif /* CONFIG_HIBERNATION */ -- cgit v1.2.3 From e9dcd1613f0ac0b3573b7d813a2c5672cd8302eb Mon Sep 17 00:00:00 2001 From: Barry Song Date: Mon, 8 Mar 2010 12:13:57 -0800 Subject: can: fix bfin_can build error after alloc_candev() change Looks like commit a6e4bc530403 didn't include updates to drivers so the Blackfin CAN driver fails to build now. Signed-off-by: Barry Song Signed-off-by: Mike Frysinger Acked-by: Wolfgang Grandegger Signed-off-by: David S. Miller --- drivers/net/can/bfin_can.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/can/bfin_can.c b/drivers/net/can/bfin_can.c index bf7f9ba2d903..866905fa4119 100644 --- a/drivers/net/can/bfin_can.c +++ b/drivers/net/can/bfin_can.c @@ -26,6 +26,7 @@ #define DRV_NAME "bfin_can" #define BFIN_CAN_TIMEOUT 100 +#define TX_ECHO_SKB_MAX 1 /* * transmit and receive channels @@ -593,7 +594,7 @@ struct net_device *alloc_bfin_candev(void) struct net_device *dev; struct bfin_can_priv *priv; - dev = alloc_candev(sizeof(*priv)); + dev = alloc_candev(sizeof(*priv), TX_ECHO_SKB_MAX); if (!dev) return NULL; -- cgit v1.2.3 From de0b632ba05bc88949e67d33d1c313fcf922ae2e Mon Sep 17 00:00:00 2001 From: Josh Boyer Date: Fri, 5 Feb 2010 03:52:16 +0000 Subject: powerpc: Fix G5 thermal shutdown This changes the thresholds for the liquid cooled G5 thermal shutdown mechanism to prevent an errant shutdown with some models. Signed-off-by: David Woodhouse Signed-off-by: Benjamin Herrenschmidt --- drivers/macintosh/therm_pm72.c | 30 ++++++++++++++++++++++++------ drivers/macintosh/therm_pm72.h | 2 +- 2 files changed, 25 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/macintosh/therm_pm72.c b/drivers/macintosh/therm_pm72.c index 5738d8bf2d97..921373e4e3af 100644 --- a/drivers/macintosh/therm_pm72.c +++ b/drivers/macintosh/therm_pm72.c @@ -948,10 +948,16 @@ static void do_monitor_cpu_combined(void) printk(KERN_WARNING "Warning ! Temperature way above maximum (%d) !\n", temp_combi >> 16); state0->overtemp += CPU_MAX_OVERTEMP / 4; - } else if (temp_combi > (state0->mpu.tmax << 16)) + } else if (temp_combi > (state0->mpu.tmax << 16)) { state0->overtemp++; - else + printk(KERN_WARNING "Temperature %d above max %d. overtemp %d\n", + temp_combi >> 16, state0->mpu.tmax, state0->overtemp); + } else { + if (state0->overtemp) + printk(KERN_WARNING "Temperature back down to %d\n", + temp_combi >> 16); state0->overtemp = 0; + } if (state0->overtemp >= CPU_MAX_OVERTEMP) critical_state = 1; if (state0->overtemp > 0) { @@ -1023,10 +1029,16 @@ static void do_monitor_cpu_split(struct cpu_pid_state *state) " (%d) !\n", state->index, temp >> 16); state->overtemp += CPU_MAX_OVERTEMP / 4; - } else if (temp > (state->mpu.tmax << 16)) + } else if (temp > (state->mpu.tmax << 16)) { state->overtemp++; - else + printk(KERN_WARNING "CPU %d temperature %d above max %d. overtemp %d\n", + state->index, temp >> 16, state->mpu.tmax, state->overtemp); + } else { + if (state->overtemp) + printk(KERN_WARNING "CPU %d temperature back down to %d\n", + state->index, temp >> 16); state->overtemp = 0; + } if (state->overtemp >= CPU_MAX_OVERTEMP) critical_state = 1; if (state->overtemp > 0) { @@ -1085,10 +1097,16 @@ static void do_monitor_cpu_rack(struct cpu_pid_state *state) " (%d) !\n", state->index, temp >> 16); state->overtemp = CPU_MAX_OVERTEMP / 4; - } else if (temp > (state->mpu.tmax << 16)) + } else if (temp > (state->mpu.tmax << 16)) { state->overtemp++; - else + printk(KERN_WARNING "CPU %d temperature %d above max %d. overtemp %d\n", + state->index, temp >> 16, state->mpu.tmax, state->overtemp); + } else { + if (state->overtemp) + printk(KERN_WARNING "CPU %d temperature back down to %d\n", + state->index, temp >> 16); state->overtemp = 0; + } if (state->overtemp >= CPU_MAX_OVERTEMP) critical_state = 1; if (state->overtemp > 0) { diff --git a/drivers/macintosh/therm_pm72.h b/drivers/macintosh/therm_pm72.h index 393cc9df94e1..df3680e2a22f 100644 --- a/drivers/macintosh/therm_pm72.h +++ b/drivers/macintosh/therm_pm72.h @@ -269,7 +269,7 @@ struct slots_pid_state #define CPU_TEMP_HISTORY_SIZE 2 #define CPU_POWER_HISTORY_SIZE 10 #define CPU_PID_INTERVAL 1 -#define CPU_MAX_OVERTEMP 30 +#define CPU_MAX_OVERTEMP 90 #define CPUA_PUMP_RPM_INDEX 7 #define CPUB_PUMP_RPM_INDEX 8 -- cgit v1.2.3 From ec62e1c8dd2f9b2a833b48d4a2f58f0c5e07384c Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Mon, 8 Mar 2010 22:37:09 -0800 Subject: Input: i8042 - use platfrom_create_bundle() helper Signed-off-by: Dmitry Torokhov --- drivers/input/serio/i8042.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c index b54aee7cd9e3..fce8ab7e89a1 100644 --- a/drivers/input/serio/i8042.c +++ b/drivers/input/serio/i8042.c @@ -1386,6 +1386,8 @@ static int __init i8042_probe(struct platform_device *dev) { int error; + i8042_platform_device = dev; + error = i8042_controller_selftest(); if (error) return error; @@ -1421,6 +1423,7 @@ static int __init i8042_probe(struct platform_device *dev) i8042_free_aux_ports(); /* in case KBD failed but AUX not */ i8042_free_irqs(); i8042_controller_reset(); + i8042_platform_device = NULL; return error; } @@ -1430,6 +1433,7 @@ static int __devexit i8042_remove(struct platform_device *dev) i8042_unregister_ports(); i8042_free_irqs(); i8042_controller_reset(); + i8042_platform_device = NULL; return 0; } @@ -1448,6 +1452,7 @@ static struct platform_driver i8042_driver = { static int __init i8042_init(void) { + struct platform_device *pdev; int err; dbg_init(); @@ -1460,31 +1465,18 @@ static int __init i8042_init(void) if (err) goto err_platform_exit; - i8042_platform_device = platform_device_alloc("i8042", -1); - if (!i8042_platform_device) { - err = -ENOMEM; + pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0); + if (IS_ERR(pdev)) { + err = PTR_ERR(pdev); goto err_platform_exit; } - err = platform_device_add(i8042_platform_device); - if (err) - goto err_free_device; - - err = platform_driver_probe(&i8042_driver, i8042_probe); - if (err) - goto err_del_device; - panic_blink = i8042_panic_blink; return 0; - err_del_device: - platform_device_del(i8042_platform_device); - err_free_device: - platform_device_put(i8042_platform_device); err_platform_exit: i8042_platform_exit(); - return err; } -- cgit v1.2.3 From 58b939959d228681208ba997595411fddc860849 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Mon, 8 Mar 2010 22:37:10 -0800 Subject: Input: scancode in get/set_keycodes should be unsigned MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The HID layer has some scan codes of the form 0xffbc0000 for logitech devices which do not work if scancode is typed as signed int, so we need to switch to unsigned it instead. While at it keycode being signed does not make much sense either. Acked-by: Márton Németh Acked-by: Matthew Garrett Acked-by: Jiri Kosina Signed-off-by: Dmitry Torokhov --- drivers/hid/hid-input.c | 24 ++++++++++++------------ drivers/input/evdev.c | 2 +- drivers/input/input.c | 20 +++++++++----------- drivers/input/misc/ati_remote2.c | 14 +++++++------- drivers/input/misc/winbond-cir.c | 12 +++++------- drivers/input/sparse-keymap.c | 6 ++++-- drivers/media/IR/ir-keytable.c | 4 ++-- drivers/media/dvb/dvb-usb/dvb-usb-remote.c | 4 ++-- drivers/platform/x86/dell-wmi.c | 16 +++++++--------- drivers/platform/x86/hp-wmi.c | 15 +++++++-------- drivers/platform/x86/panasonic-laptop.c | 15 +++++++-------- drivers/platform/x86/topstar-laptop.c | 13 ++++++------- drivers/platform/x86/toshiba_acpi.c | 17 +++++++---------- include/linux/input.h | 20 ++++++++++++-------- 14 files changed, 88 insertions(+), 94 deletions(-) (limited to 'drivers') diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c index 79d9edd0bdfa..7a0d2e4661a1 100644 --- a/drivers/hid/hid-input.c +++ b/drivers/hid/hid-input.c @@ -68,22 +68,25 @@ static const struct { #define map_key_clear(c) hid_map_usage_clear(hidinput, usage, &bit, \ &max, EV_KEY, (c)) -static inline int match_scancode(int code, int scancode) +static inline int match_scancode(unsigned int code, unsigned int scancode) { if (scancode == 0) return 1; - return ((code & (HID_USAGE_PAGE | HID_USAGE)) == scancode); + + return (code & (HID_USAGE_PAGE | HID_USAGE)) == scancode; } -static inline int match_keycode(int code, int keycode) +static inline int match_keycode(unsigned int code, unsigned int keycode) { if (keycode == 0) return 1; - return (code == keycode); + + return code == keycode; } static struct hid_usage *hidinput_find_key(struct hid_device *hid, - int scancode, int keycode) + unsigned int scancode, + unsigned int keycode) { int i, j, k; struct hid_report *report; @@ -105,8 +108,8 @@ static struct hid_usage *hidinput_find_key(struct hid_device *hid, return NULL; } -static int hidinput_getkeycode(struct input_dev *dev, int scancode, - int *keycode) +static int hidinput_getkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int *keycode) { struct hid_device *hid = input_get_drvdata(dev); struct hid_usage *usage; @@ -119,16 +122,13 @@ static int hidinput_getkeycode(struct input_dev *dev, int scancode, return -EINVAL; } -static int hidinput_setkeycode(struct input_dev *dev, int scancode, - int keycode) +static int hidinput_setkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int keycode) { struct hid_device *hid = input_get_drvdata(dev); struct hid_usage *usage; int old_keycode; - if (keycode < 0 || keycode > KEY_MAX) - return -EINVAL; - usage = hidinput_find_key(hid, scancode, 0); if (usage) { old_keycode = usage->code; diff --git a/drivers/input/evdev.c b/drivers/input/evdev.c index 9f9816baeb97..2ee6c7a68bdc 100644 --- a/drivers/input/evdev.c +++ b/drivers/input/evdev.c @@ -515,7 +515,7 @@ static long evdev_do_ioctl(struct file *file, unsigned int cmd, struct input_absinfo abs; struct ff_effect effect; int __user *ip = (int __user *)p; - int i, t, u, v; + unsigned int i, t, u, v; int error; switch (cmd) { diff --git a/drivers/input/input.c b/drivers/input/input.c index 41168d5f8c17..e2dd8858e19d 100644 --- a/drivers/input/input.c +++ b/drivers/input/input.c @@ -582,7 +582,8 @@ static int input_fetch_keycode(struct input_dev *dev, int scancode) } static int input_default_getkeycode(struct input_dev *dev, - int scancode, int *keycode) + unsigned int scancode, + unsigned int *keycode) { if (!dev->keycodesize) return -EINVAL; @@ -596,7 +597,8 @@ static int input_default_getkeycode(struct input_dev *dev, } static int input_default_setkeycode(struct input_dev *dev, - int scancode, int keycode) + unsigned int scancode, + unsigned int keycode) { int old_keycode; int i; @@ -654,11 +656,9 @@ static int input_default_setkeycode(struct input_dev *dev, * This function should be called by anyone interested in retrieving current * keymap. Presently keyboard and evdev handlers use it. */ -int input_get_keycode(struct input_dev *dev, int scancode, int *keycode) +int input_get_keycode(struct input_dev *dev, + unsigned int scancode, unsigned int *keycode) { - if (scancode < 0) - return -EINVAL; - return dev->getkeycode(dev, scancode, keycode); } EXPORT_SYMBOL(input_get_keycode); @@ -672,16 +672,14 @@ EXPORT_SYMBOL(input_get_keycode); * This function should be called by anyone needing to update current * keymap. Presently keyboard and evdev handlers use it. */ -int input_set_keycode(struct input_dev *dev, int scancode, int keycode) +int input_set_keycode(struct input_dev *dev, + unsigned int scancode, unsigned int keycode) { unsigned long flags; int old_keycode; int retval; - if (scancode < 0) - return -EINVAL; - - if (keycode < 0 || keycode > KEY_MAX) + if (keycode > KEY_MAX) return -EINVAL; spin_lock_irqsave(&dev->event_lock, flags); diff --git a/drivers/input/misc/ati_remote2.c b/drivers/input/misc/ati_remote2.c index 0501f0e65157..15be5430bc6d 100644 --- a/drivers/input/misc/ati_remote2.c +++ b/drivers/input/misc/ati_remote2.c @@ -474,10 +474,11 @@ static void ati_remote2_complete_key(struct urb *urb) } static int ati_remote2_getkeycode(struct input_dev *idev, - int scancode, int *keycode) + unsigned int scancode, unsigned int *keycode) { struct ati_remote2 *ar2 = input_get_drvdata(idev); - int index, mode; + unsigned int mode; + int index; mode = scancode >> 8; if (mode > ATI_REMOTE2_PC || !((1 << mode) & ar2->mode_mask)) @@ -491,10 +492,12 @@ static int ati_remote2_getkeycode(struct input_dev *idev, return 0; } -static int ati_remote2_setkeycode(struct input_dev *idev, int scancode, int keycode) +static int ati_remote2_setkeycode(struct input_dev *idev, + unsigned int scancode, unsigned int keycode) { struct ati_remote2 *ar2 = input_get_drvdata(idev); - int index, mode, old_keycode; + unsigned int mode, old_keycode; + int index; mode = scancode >> 8; if (mode > ATI_REMOTE2_PC || !((1 << mode) & ar2->mode_mask)) @@ -504,9 +507,6 @@ static int ati_remote2_setkeycode(struct input_dev *idev, int scancode, int keyc if (index < 0) return -EINVAL; - if (keycode < KEY_RESERVED || keycode > KEY_MAX) - return -EINVAL; - old_keycode = ar2->keycode[mode][index]; ar2->keycode[mode][index] = keycode; __set_bit(keycode, idev->keybit); diff --git a/drivers/input/misc/winbond-cir.c b/drivers/input/misc/winbond-cir.c index cbec3dfdd42b..9c155a43abc2 100644 --- a/drivers/input/misc/winbond-cir.c +++ b/drivers/input/misc/winbond-cir.c @@ -385,26 +385,24 @@ wbcir_do_getkeycode(struct wbcir_data *data, u32 scancode) } static int -wbcir_getkeycode(struct input_dev *dev, int scancode, int *keycode) +wbcir_getkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int *keycode) { struct wbcir_data *data = input_get_drvdata(dev); - *keycode = (int)wbcir_do_getkeycode(data, (u32)scancode); + *keycode = wbcir_do_getkeycode(data, scancode); return 0; } static int -wbcir_setkeycode(struct input_dev *dev, int sscancode, int keycode) +wbcir_setkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int keycode) { struct wbcir_data *data = input_get_drvdata(dev); struct wbcir_keyentry *keyentry; struct wbcir_keyentry *new_keyentry; unsigned long flags; unsigned int old_keycode = KEY_RESERVED; - u32 scancode = (u32)sscancode; - - if (keycode < 0 || keycode > KEY_MAX) - return -EINVAL; new_keyentry = kmalloc(sizeof(*new_keyentry), GFP_KERNEL); if (!new_keyentry) diff --git a/drivers/input/sparse-keymap.c b/drivers/input/sparse-keymap.c index fbd3987af57f..e6bde55e5203 100644 --- a/drivers/input/sparse-keymap.c +++ b/drivers/input/sparse-keymap.c @@ -64,7 +64,8 @@ struct key_entry *sparse_keymap_entry_from_keycode(struct input_dev *dev, EXPORT_SYMBOL(sparse_keymap_entry_from_keycode); static int sparse_keymap_getkeycode(struct input_dev *dev, - int scancode, int *keycode) + unsigned int scancode, + unsigned int *keycode) { const struct key_entry *key = sparse_keymap_entry_from_scancode(dev, scancode); @@ -78,7 +79,8 @@ static int sparse_keymap_getkeycode(struct input_dev *dev, } static int sparse_keymap_setkeycode(struct input_dev *dev, - int scancode, int keycode) + unsigned int scancode, + unsigned int keycode) { struct key_entry *key; int old_keycode; diff --git a/drivers/media/IR/ir-keytable.c b/drivers/media/IR/ir-keytable.c index 0903f539bf68..0a3b4ed38e48 100644 --- a/drivers/media/IR/ir-keytable.c +++ b/drivers/media/IR/ir-keytable.c @@ -123,7 +123,7 @@ static int ir_copy_table(struct ir_scancode_table *destin, * If the key is not found, returns -EINVAL, otherwise, returns 0. */ static int ir_getkeycode(struct input_dev *dev, - int scancode, int *keycode) + unsigned int scancode, unsigned int *keycode) { int elem; struct ir_input_dev *ir_dev = input_get_drvdata(dev); @@ -291,7 +291,7 @@ static int ir_insert_key(struct ir_scancode_table *rc_tab, * If the key is not found, returns -EINVAL, otherwise, returns 0. */ static int ir_setkeycode(struct input_dev *dev, - int scancode, int keycode) + unsigned int scancode, unsigned int keycode) { int rc = 0; struct ir_input_dev *ir_dev = input_get_drvdata(dev); diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-remote.c b/drivers/media/dvb/dvb-usb/dvb-usb-remote.c index a03ef7efec9a..852fe89539cf 100644 --- a/drivers/media/dvb/dvb-usb/dvb-usb-remote.c +++ b/drivers/media/dvb/dvb-usb/dvb-usb-remote.c @@ -9,7 +9,7 @@ #include static int dvb_usb_getkeycode(struct input_dev *dev, - int scancode, int *keycode) + unsigned int scancode, unsigned int *keycode) { struct dvb_usb_device *d = input_get_drvdata(dev); @@ -39,7 +39,7 @@ static int dvb_usb_getkeycode(struct input_dev *dev, } static int dvb_usb_setkeycode(struct input_dev *dev, - int scancode, int keycode) + unsigned int scancode, unsigned int keycode) { struct dvb_usb_device *d = input_get_drvdata(dev); diff --git a/drivers/platform/x86/dell-wmi.c b/drivers/platform/x86/dell-wmi.c index 1b1dddbd5744..bed764e3ea2a 100644 --- a/drivers/platform/x86/dell-wmi.c +++ b/drivers/platform/x86/dell-wmi.c @@ -142,7 +142,7 @@ static struct key_entry *dell_wmi_keymap = dell_legacy_wmi_keymap; static struct input_dev *dell_wmi_input_dev; -static struct key_entry *dell_wmi_get_entry_by_scancode(int code) +static struct key_entry *dell_wmi_get_entry_by_scancode(unsigned int code) { struct key_entry *key; @@ -153,7 +153,7 @@ static struct key_entry *dell_wmi_get_entry_by_scancode(int code) return NULL; } -static struct key_entry *dell_wmi_get_entry_by_keycode(int keycode) +static struct key_entry *dell_wmi_get_entry_by_keycode(unsigned int keycode) { struct key_entry *key; @@ -164,8 +164,8 @@ static struct key_entry *dell_wmi_get_entry_by_keycode(int keycode) return NULL; } -static int dell_wmi_getkeycode(struct input_dev *dev, int scancode, - int *keycode) +static int dell_wmi_getkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int *keycode) { struct key_entry *key = dell_wmi_get_entry_by_scancode(scancode); @@ -177,13 +177,11 @@ static int dell_wmi_getkeycode(struct input_dev *dev, int scancode, return -EINVAL; } -static int dell_wmi_setkeycode(struct input_dev *dev, int scancode, int keycode) +static int dell_wmi_setkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int keycode) { struct key_entry *key; - int old_keycode; - - if (keycode < 0 || keycode > KEY_MAX) - return -EINVAL; + unsigned int old_keycode; key = dell_wmi_get_entry_by_scancode(scancode); if (key && key->type == KE_KEY) { diff --git a/drivers/platform/x86/hp-wmi.c b/drivers/platform/x86/hp-wmi.c index 7ccf33c08967..56086363becc 100644 --- a/drivers/platform/x86/hp-wmi.c +++ b/drivers/platform/x86/hp-wmi.c @@ -278,7 +278,7 @@ static DEVICE_ATTR(als, S_IRUGO | S_IWUSR, show_als, set_als); static DEVICE_ATTR(dock, S_IRUGO, show_dock, NULL); static DEVICE_ATTR(tablet, S_IRUGO, show_tablet, NULL); -static struct key_entry *hp_wmi_get_entry_by_scancode(int code) +static struct key_entry *hp_wmi_get_entry_by_scancode(unsigned int code) { struct key_entry *key; @@ -289,7 +289,7 @@ static struct key_entry *hp_wmi_get_entry_by_scancode(int code) return NULL; } -static struct key_entry *hp_wmi_get_entry_by_keycode(int keycode) +static struct key_entry *hp_wmi_get_entry_by_keycode(unsigned int keycode) { struct key_entry *key; @@ -300,7 +300,8 @@ static struct key_entry *hp_wmi_get_entry_by_keycode(int keycode) return NULL; } -static int hp_wmi_getkeycode(struct input_dev *dev, int scancode, int *keycode) +static int hp_wmi_getkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int *keycode) { struct key_entry *key = hp_wmi_get_entry_by_scancode(scancode); @@ -312,13 +313,11 @@ static int hp_wmi_getkeycode(struct input_dev *dev, int scancode, int *keycode) return -EINVAL; } -static int hp_wmi_setkeycode(struct input_dev *dev, int scancode, int keycode) +static int hp_wmi_setkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int keycode) { struct key_entry *key; - int old_keycode; - - if (keycode < 0 || keycode > KEY_MAX) - return -EINVAL; + unsigned int old_keycode; key = hp_wmi_get_entry_by_scancode(scancode); if (key && key->type == KE_KEY) { diff --git a/drivers/platform/x86/panasonic-laptop.c b/drivers/platform/x86/panasonic-laptop.c index fe7cf0188acc..c9fc479fc290 100644 --- a/drivers/platform/x86/panasonic-laptop.c +++ b/drivers/platform/x86/panasonic-laptop.c @@ -200,7 +200,7 @@ static struct acpi_driver acpi_pcc_driver = { }; #define KEYMAP_SIZE 11 -static const int initial_keymap[KEYMAP_SIZE] = { +static const unsigned int initial_keymap[KEYMAP_SIZE] = { /* 0 */ KEY_RESERVED, /* 1 */ KEY_BRIGHTNESSDOWN, /* 2 */ KEY_BRIGHTNESSUP, @@ -222,7 +222,7 @@ struct pcc_acpi { struct acpi_device *device; struct input_dev *input_dev; struct backlight_device *backlight; - int keymap[KEYMAP_SIZE]; + unsigned int keymap[KEYMAP_SIZE]; }; struct pcc_keyinput { @@ -445,7 +445,8 @@ static struct attribute_group pcc_attr_group = { /* hotkey input device driver */ -static int pcc_getkeycode(struct input_dev *dev, int scancode, int *keycode) +static int pcc_getkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int *keycode) { struct pcc_acpi *pcc = input_get_drvdata(dev); @@ -457,7 +458,7 @@ static int pcc_getkeycode(struct input_dev *dev, int scancode, int *keycode) return 0; } -static int keymap_get_by_keycode(struct pcc_acpi *pcc, int keycode) +static int keymap_get_by_keycode(struct pcc_acpi *pcc, unsigned int keycode) { int i; @@ -469,7 +470,8 @@ static int keymap_get_by_keycode(struct pcc_acpi *pcc, int keycode) return 0; } -static int pcc_setkeycode(struct input_dev *dev, int scancode, int keycode) +static int pcc_setkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int keycode) { struct pcc_acpi *pcc = input_get_drvdata(dev); int oldkeycode; @@ -477,9 +479,6 @@ static int pcc_setkeycode(struct input_dev *dev, int scancode, int keycode) if (scancode >= ARRAY_SIZE(pcc->keymap)) return -EINVAL; - if (keycode < 0 || keycode > KEY_MAX) - return -EINVAL; - oldkeycode = pcc->keymap[scancode]; pcc->keymap[scancode] = keycode; diff --git a/drivers/platform/x86/topstar-laptop.c b/drivers/platform/x86/topstar-laptop.c index 02f3d4e9e666..4d6516fded7e 100644 --- a/drivers/platform/x86/topstar-laptop.c +++ b/drivers/platform/x86/topstar-laptop.c @@ -46,7 +46,7 @@ static struct tps_key_entry topstar_keymap[] = { { } }; -static struct tps_key_entry *tps_get_key_by_scancode(int code) +static struct tps_key_entry *tps_get_key_by_scancode(unsigned int code) { struct tps_key_entry *key; @@ -57,7 +57,7 @@ static struct tps_key_entry *tps_get_key_by_scancode(int code) return NULL; } -static struct tps_key_entry *tps_get_key_by_keycode(int code) +static struct tps_key_entry *tps_get_key_by_keycode(unsigned int code) { struct tps_key_entry *key; @@ -126,7 +126,8 @@ static int acpi_topstar_fncx_switch(struct acpi_device *device, bool state) return 0; } -static int topstar_getkeycode(struct input_dev *dev, int scancode, int *keycode) +static int topstar_getkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int *keycode) { struct tps_key_entry *key = tps_get_key_by_scancode(scancode); @@ -137,14 +138,12 @@ static int topstar_getkeycode(struct input_dev *dev, int scancode, int *keycode) return 0; } -static int topstar_setkeycode(struct input_dev *dev, int scancode, int keycode) +static int topstar_setkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int keycode) { struct tps_key_entry *key; int old_keycode; - if (keycode < 0 || keycode > KEY_MAX) - return -EINVAL; - key = tps_get_key_by_scancode(scancode); if (!key) diff --git a/drivers/platform/x86/toshiba_acpi.c b/drivers/platform/x86/toshiba_acpi.c index 405b969734d6..789240d1b577 100644 --- a/drivers/platform/x86/toshiba_acpi.c +++ b/drivers/platform/x86/toshiba_acpi.c @@ -745,7 +745,7 @@ static struct backlight_ops toshiba_backlight_data = { .update_status = set_lcd_status, }; -static struct key_entry *toshiba_acpi_get_entry_by_scancode(int code) +static struct key_entry *toshiba_acpi_get_entry_by_scancode(unsigned int code) { struct key_entry *key; @@ -756,7 +756,7 @@ static struct key_entry *toshiba_acpi_get_entry_by_scancode(int code) return NULL; } -static struct key_entry *toshiba_acpi_get_entry_by_keycode(int code) +static struct key_entry *toshiba_acpi_get_entry_by_keycode(unsigned int code) { struct key_entry *key; @@ -767,8 +767,8 @@ static struct key_entry *toshiba_acpi_get_entry_by_keycode(int code) return NULL; } -static int toshiba_acpi_getkeycode(struct input_dev *dev, int scancode, - int *keycode) +static int toshiba_acpi_getkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int *keycode) { struct key_entry *key = toshiba_acpi_get_entry_by_scancode(scancode); @@ -780,14 +780,11 @@ static int toshiba_acpi_getkeycode(struct input_dev *dev, int scancode, return -EINVAL; } -static int toshiba_acpi_setkeycode(struct input_dev *dev, int scancode, - int keycode) +static int toshiba_acpi_setkeycode(struct input_dev *dev, + unsigned int scancode, unsigned int keycode) { struct key_entry *key; - int old_keycode; - - if (keycode < 0 || keycode > KEY_MAX) - return -EINVAL; + unsigned int old_keycode; key = toshiba_acpi_get_entry_by_scancode(scancode); if (key && key->type == KE_KEY) { diff --git a/include/linux/input.h b/include/linux/input.h index dc24effb6d0e..7ed2251b33f1 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -58,10 +58,10 @@ struct input_absinfo { #define EVIOCGVERSION _IOR('E', 0x01, int) /* get driver version */ #define EVIOCGID _IOR('E', 0x02, struct input_id) /* get device ID */ -#define EVIOCGREP _IOR('E', 0x03, int[2]) /* get repeat settings */ -#define EVIOCSREP _IOW('E', 0x03, int[2]) /* set repeat settings */ -#define EVIOCGKEYCODE _IOR('E', 0x04, int[2]) /* get keycode */ -#define EVIOCSKEYCODE _IOW('E', 0x04, int[2]) /* set keycode */ +#define EVIOCGREP _IOR('E', 0x03, unsigned int[2]) /* get repeat settings */ +#define EVIOCSREP _IOW('E', 0x03, unsigned int[2]) /* set repeat settings */ +#define EVIOCGKEYCODE _IOR('E', 0x04, unsigned int[2]) /* get keycode */ +#define EVIOCSKEYCODE _IOW('E', 0x04, unsigned int[2]) /* set keycode */ #define EVIOCGNAME(len) _IOC(_IOC_READ, 'E', 0x06, len) /* get device name */ #define EVIOCGPHYS(len) _IOC(_IOC_READ, 'E', 0x07, len) /* get physical location */ @@ -1142,8 +1142,10 @@ struct input_dev { unsigned int keycodemax; unsigned int keycodesize; void *keycode; - int (*setkeycode)(struct input_dev *dev, int scancode, int keycode); - int (*getkeycode)(struct input_dev *dev, int scancode, int *keycode); + int (*setkeycode)(struct input_dev *dev, + unsigned int scancode, unsigned int keycode); + int (*getkeycode)(struct input_dev *dev, + unsigned int scancode, unsigned int *keycode); struct ff_device *ff; @@ -1415,8 +1417,10 @@ static inline void input_set_abs_params(struct input_dev *dev, int axis, int min dev->absbit[BIT_WORD(axis)] |= BIT_MASK(axis); } -int input_get_keycode(struct input_dev *dev, int scancode, int *keycode); -int input_set_keycode(struct input_dev *dev, int scancode, int keycode); +int input_get_keycode(struct input_dev *dev, + unsigned int scancode, unsigned int *keycode); +int input_set_keycode(struct input_dev *dev, + unsigned int scancode, unsigned int keycode); extern struct class input_class; -- cgit v1.2.3 From 3e6e15a862a0bc20128497bbdc54254cdec21835 Mon Sep 17 00:00:00 2001 From: Alan Stern Date: Mon, 8 Mar 2010 23:42:46 -0800 Subject: Input: enable remote wakeup for PNP i8042 keyboard ports This patch (as1355) enables remote wakeup by default on PNP i8042 keyboard ports. Signed-off-by: Alan Stern Signed-off-by: Dmitry Torokhov --- drivers/input/serio/i8042-x86ia64io.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h index 2a5982e532f8..3696cab40598 100644 --- a/drivers/input/serio/i8042-x86ia64io.h +++ b/drivers/input/serio/i8042-x86ia64io.h @@ -624,6 +624,9 @@ static int i8042_pnp_kbd_probe(struct pnp_dev *dev, const struct pnp_device_id * strlcat(i8042_pnp_kbd_name, pnp_dev_name(dev), sizeof(i8042_pnp_kbd_name)); } + /* Keyboard ports are always supposed to be wakeup-enabled */ + device_set_wakeup_enable(&dev->dev, true); + i8042_pnp_kbd_devices++; return 0; } -- cgit v1.2.3 From 3dd1b39497b6820219581af16e6a8831a582bb3a Mon Sep 17 00:00:00 2001 From: Jari Vanhala Date: Tue, 9 Mar 2010 00:29:46 -0800 Subject: Input: add driver for TWL4030 vibrator device TWL4030 Vibrator implemented via Force Feedback interface. This uses MFD TWL4030 codec and own dynamic workqueue. Signed-off-by: Jari Vanhala Signed-off-by: Dmitry Torokhov --- drivers/input/misc/Kconfig | 11 ++ drivers/input/misc/Makefile | 1 + drivers/input/misc/twl4030-vibra.c | 297 +++++++++++++++++++++++++++++++++++++ 3 files changed, 309 insertions(+) create mode 100644 drivers/input/misc/twl4030-vibra.c (limited to 'drivers') diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 7097bfe581d7..23140a3bb8e0 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -214,6 +214,17 @@ config INPUT_TWL4030_PWRBUTTON To compile this driver as a module, choose M here. The module will be called twl4030_pwrbutton. +config INPUT_TWL4030_VIBRA + tristate "Support for TWL4030 Vibrator" + depends on TWL4030_CORE + select TWL4030_CODEC + select INPUT_FF_MEMLESS + help + This option enables support for TWL4030 Vibrator Driver. + + To compile this driver as a module, choose M here. The module will + be called twl4030_vibra. + config INPUT_UINPUT tristate "User level driver support" help diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index b611615e24ad..7e95a5d474dc 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_INPUT_GPIO_ROTARY_ENCODER) += rotary_encoder.o obj-$(CONFIG_INPUT_SGI_BTNS) += sgi_btns.o obj-$(CONFIG_INPUT_SPARCSPKR) += sparcspkr.o obj-$(CONFIG_INPUT_TWL4030_PWRBUTTON) += twl4030-pwrbutton.o +obj-$(CONFIG_INPUT_TWL4030_VIBRA) += twl4030-vibra.o obj-$(CONFIG_INPUT_UINPUT) += uinput.o obj-$(CONFIG_INPUT_WINBOND_CIR) += winbond-cir.o obj-$(CONFIG_INPUT_WISTRON_BTNS) += wistron_btns.o diff --git a/drivers/input/misc/twl4030-vibra.c b/drivers/input/misc/twl4030-vibra.c new file mode 100644 index 000000000000..2fb79e064da3 --- /dev/null +++ b/drivers/input/misc/twl4030-vibra.c @@ -0,0 +1,297 @@ +/* + * twl4030-vibra.c - TWL4030 Vibrator driver + * + * Copyright (C) 2008-2010 Nokia Corporation + * + * Written by Henrik Saari + * Updates by Felipe Balbi + * Input by Jari Vanhala + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/* MODULE ID2 */ +#define LEDEN 0x00 + +/* ForceFeedback */ +#define EFFECT_DIR_180_DEG 0x8000 /* range is 0 - 0xFFFF */ + +struct vibra_info { + struct device *dev; + struct input_dev *input_dev; + + struct workqueue_struct *workqueue; + struct work_struct play_work; + + bool enabled; + int speed; + int direction; + + bool coexist; +}; + +static void vibra_disable_leds(void) +{ + u8 reg; + + /* Disable LEDA & LEDB, cannot be used with vibra (PWM) */ + twl_i2c_read_u8(TWL4030_MODULE_LED, ®, LEDEN); + reg &= ~0x03; + twl_i2c_write_u8(TWL4030_MODULE_LED, LEDEN, reg); +} + +/* Powers H-Bridge and enables audio clk */ +static void vibra_enable(struct vibra_info *info) +{ + u8 reg; + + twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER); + + /* turn H-Bridge on */ + twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, + ®, TWL4030_REG_VIBRA_CTL); + twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, + (reg | TWL4030_VIBRA_EN), TWL4030_REG_VIBRA_CTL); + + twl4030_codec_enable_resource(TWL4030_CODEC_RES_APLL); + + info->enabled = true; +} + +static void vibra_disable(struct vibra_info *info) +{ + u8 reg; + + /* Power down H-Bridge */ + twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, + ®, TWL4030_REG_VIBRA_CTL); + twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, + (reg & ~TWL4030_VIBRA_EN), TWL4030_REG_VIBRA_CTL); + + twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER); + twl4030_codec_disable_resource(TWL4030_CODEC_RES_APLL); + + info->enabled = false; +} + +static void vibra_play_work(struct work_struct *work) +{ + struct vibra_info *info = container_of(work, + struct vibra_info, play_work); + int dir; + int pwm; + u8 reg; + + dir = info->direction; + pwm = info->speed; + + twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, + ®, TWL4030_REG_VIBRA_CTL); + if (pwm && (!info->coexist || !(reg & TWL4030_VIBRA_SEL))) { + + if (!info->enabled) + vibra_enable(info); + + /* set vibra rotation direction */ + twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, + ®, TWL4030_REG_VIBRA_CTL); + reg = (dir) ? (reg | TWL4030_VIBRA_DIR) : + (reg & ~TWL4030_VIBRA_DIR); + twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, + reg, TWL4030_REG_VIBRA_CTL); + + /* set PWM, 1 = max, 255 = min */ + twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, + 256 - pwm, TWL4030_REG_VIBRA_SET); + } else { + if (info->enabled) + vibra_disable(info); + } +} + +/*** Input/ForceFeedback ***/ + +static int vibra_play(struct input_dev *input, void *data, + struct ff_effect *effect) +{ + struct vibra_info *info = input_get_drvdata(input); + + info->speed = effect->u.rumble.strong_magnitude >> 8; + if (!info->speed) + info->speed = effect->u.rumble.weak_magnitude >> 9; + info->direction = effect->direction < EFFECT_DIR_180_DEG ? 0 : 1; + queue_work(info->workqueue, &info->play_work); + return 0; +} + +static int twl4030_vibra_open(struct input_dev *input) +{ + struct vibra_info *info = input_get_drvdata(input); + + info->workqueue = create_singlethread_workqueue("vibra"); + if (info->workqueue == NULL) { + dev_err(&input->dev, "couldn't create workqueue\n"); + return -ENOMEM; + } + return 0; +} + +static void twl4030_vibra_close(struct input_dev *input) +{ + struct vibra_info *info = input_get_drvdata(input); + + cancel_work_sync(&info->play_work); + INIT_WORK(&info->play_work, vibra_play_work); /* cleanup */ + destroy_workqueue(info->workqueue); + info->workqueue = NULL; + + if (info->enabled) + vibra_disable(info); +} + +/*** Module ***/ +#if CONFIG_PM +static int twl4030_vibra_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct vibra_info *info = platform_get_drvdata(pdev); + + if (info->enabled) + vibra_disable(info); + + return 0; +} + +static int twl4030_vibra_resume(struct device *dev) +{ + vibra_disable_leds(); + return 0; +} + +static SIMPLE_DEV_PM_OPS(twl4030_vibra_pm_ops, + twl4030_vibra_suspend, twl4030_vibra_resume); +#endif + +static int __devinit twl4030_vibra_probe(struct platform_device *pdev) +{ + struct twl4030_codec_vibra_data *pdata = pdev->dev.platform_data; + struct vibra_info *info; + int ret; + + if (!pdata) { + dev_dbg(&pdev->dev, "platform_data not available\n"); + return -EINVAL; + } + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->dev = &pdev->dev; + info->coexist = pdata->coexist; + INIT_WORK(&info->play_work, vibra_play_work); + + info->input_dev = input_allocate_device(); + if (info->input_dev == NULL) { + dev_err(&pdev->dev, "couldn't allocate input device\n"); + ret = -ENOMEM; + goto err_kzalloc; + } + + input_set_drvdata(info->input_dev, info); + + info->input_dev->name = "twl4030:vibrator"; + info->input_dev->id.version = 1; + info->input_dev->dev.parent = pdev->dev.parent; + info->input_dev->open = twl4030_vibra_open; + info->input_dev->close = twl4030_vibra_close; + __set_bit(FF_RUMBLE, info->input_dev->ffbit); + + ret = input_ff_create_memless(info->input_dev, NULL, vibra_play); + if (ret < 0) { + dev_dbg(&pdev->dev, "couldn't register vibrator to FF\n"); + goto err_ialloc; + } + + ret = input_register_device(info->input_dev); + if (ret < 0) { + dev_dbg(&pdev->dev, "couldn't register input device\n"); + goto err_iff; + } + + vibra_disable_leds(); + + platform_set_drvdata(pdev, info); + return 0; + +err_iff: + input_ff_destroy(info->input_dev); +err_ialloc: + input_free_device(info->input_dev); +err_kzalloc: + kfree(info); + return ret; +} + +static int __devexit twl4030_vibra_remove(struct platform_device *pdev) +{ + struct vibra_info *info = platform_get_drvdata(pdev); + + /* this also free ff-memless and calls close if needed */ + input_unregister_device(info->input_dev); + kfree(info); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver twl4030_vibra_driver = { + .probe = twl4030_vibra_probe, + .remove = __devexit_p(twl4030_vibra_remove), + .driver = { + .name = "twl4030_codec_vibra", + .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &twl4030_vibra_pm_ops, +#endif + }, +}; + +static int __init twl4030_vibra_init(void) +{ + return platform_driver_register(&twl4030_vibra_driver); +} +module_init(twl4030_vibra_init); + +static void __exit twl4030_vibra_exit(void) +{ + platform_driver_unregister(&twl4030_vibra_driver); +} +module_exit(twl4030_vibra_exit); + +MODULE_ALIAS("platform:twl4030_codec_vibra"); + +MODULE_DESCRIPTION("TWL4030 Vibra driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nokia Corporation"); -- cgit v1.2.3 From 28918c211d86b6eeb70182c523800c7bc442960c Mon Sep 17 00:00:00 2001 From: Michael Poole Date: Tue, 9 Mar 2010 06:47:35 -0500 Subject: HID: magicmouse: fix oops after device removal Ask the HID core not to register an input device for the mouse. Fix an oops after removing the device, due to leaving the new input device registered. Signed-off-by: Michael Poole Signed-off-by: Jiri Kosina --- drivers/hid/hid-magicmouse.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/hid/hid-magicmouse.c b/drivers/hid/hid-magicmouse.c index 4a3a94f2b10c..c174b64c3810 100644 --- a/drivers/hid/hid-magicmouse.c +++ b/drivers/hid/hid-magicmouse.c @@ -353,7 +353,7 @@ static int magicmouse_probe(struct hid_device *hdev, goto err_free; } - ret = hid_hw_start(hdev, HID_CONNECT_DEFAULT); + ret = hid_hw_start(hdev, HID_CONNECT_DEFAULT & ~HID_CONNECT_HIDINPUT); if (ret) { dev_err(&hdev->dev, "magicmouse hw start failed\n"); goto err_free; @@ -409,8 +409,11 @@ err_free: static void magicmouse_remove(struct hid_device *hdev) { + struct magicmouse_sc *msc = hid_get_drvdata(hdev); + hid_hw_stop(hdev); - kfree(hid_get_drvdata(hdev)); + input_unregister_device(msc->input); + kfree(msc); } static const struct hid_device_id magic_mice[] = { -- cgit v1.2.3 From eff7f270e9a05688066f40589d7b44e1dcf335dc Mon Sep 17 00:00:00 2001 From: Andrej Gelenberg Date: Tue, 9 Mar 2010 13:49:54 +0100 Subject: HID: add quirk for UC-Logik WP4030 tablet Add HID_QUIRK_MULTI_INPUT for UC-Logik tablet. $ lsusb ... Bus 004 Device 002: ID 5543:0003 UC-Logic Technology Corp. Genius MousePen 4x3 Tablet/Aquila L1 Tablet Signed-off-by: Andrej Gelenberg Signed-off-by: Jiri Kosina --- drivers/hid/hid-ids.h | 1 + drivers/hid/usbhid/hid-quirks.c | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index 72c05f90553c..797e06470356 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -445,6 +445,7 @@ #define USB_VENDOR_ID_UCLOGIC 0x5543 #define USB_DEVICE_ID_UCLOGIC_TABLET_PF1209 0x0042 +#define USB_DEVICE_ID_UCLOGIC_TABLET_WP4030U 0x0003 #define USB_VENDOR_ID_VERNIER 0x08f7 #define USB_DEVICE_ID_VERNIER_LABPRO 0x0001 diff --git a/drivers/hid/usbhid/hid-quirks.c b/drivers/hid/usbhid/hid-quirks.c index 7844280897d1..928943c7ce9a 100644 --- a/drivers/hid/usbhid/hid-quirks.c +++ b/drivers/hid/usbhid/hid-quirks.c @@ -63,6 +63,7 @@ static const struct hid_blacklist { { USB_VENDOR_ID_SUN, USB_DEVICE_ID_RARITAN_KVM_DONGLE, HID_QUIRK_NOGET }, { USB_VENDOR_ID_TURBOX, USB_DEVICE_ID_TURBOX_KEYBOARD, HID_QUIRK_NOGET }, { USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_TABLET_PF1209, HID_QUIRK_MULTI_INPUT }, + { USB_VENDOR_ID_UCLOGIC, USB_DEVICE_ID_UCLOGIC_TABLET_WP4030U, HID_QUIRK_MULTI_INPUT }, { USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_DUAL_USB_JOYPAD, HID_QUIRK_NOGET | HID_QUIRK_MULTI_INPUT | HID_QUIRK_SKIP_OUTPUT_REPORTS }, { USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_QUAD_USB_JOYPAD, HID_QUIRK_NOGET | HID_QUIRK_MULTI_INPUT }, -- cgit v1.2.3 From 1d79e53c56afe0826a311c3bc1653ad938166c22 Mon Sep 17 00:00:00 2001 From: Reinette Chatre Date: Fri, 26 Feb 2010 11:01:36 -0800 Subject: iwl3945: fix memory corruption Recent patch "iwlwifi: move 3945 clip groups to 3945 data" exposed a memory corruption problem. When initializing the clip groups the code was mistakenly using the iwlagn rate count, not the 3945 rate count. This resulted in more memory being written than was allocated. "iwlwifi: move 3945 clip groups to 3945 data" moved the location where the clip groups are stored and the impact is now severe in that the number of configured TX queues is modified. Previously the "temperature" field was overwritten, which did not seem to affect the operation. Fix this one instance where wrong rate count was used. I also noticed one more location where the iwlagn rate count was used to index an iwl3945 array, fix this. I also modified one location that modified the iwlagn rate count to obtain the iwl3945 rate count ... just use the iwl3945 rate count directly. This fixes http://bugzilla.intellinuxwireless.org/show_bug.cgi?id=2165 and http://bugzilla.intellinuxwireless.org/show_bug.cgi?id=2168 Signed-off-by: Reinette Chatre --- drivers/net/wireless/iwlwifi/iwl-3945.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c index 303cc8193adc..e0678d921055 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945.c +++ b/drivers/net/wireless/iwlwifi/iwl-3945.c @@ -184,7 +184,7 @@ static int iwl3945_hwrate_to_plcp_idx(u8 plcp) { int idx; - for (idx = 0; idx < IWL_RATE_COUNT; idx++) + for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++) if (iwl3945_rates[idx].plcp == plcp) return idx; return -1; @@ -805,7 +805,7 @@ void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, int sta_id, int tx_id) { u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value; - u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1); + u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945); u16 rate_mask; int rate; u8 rts_retry_limit; @@ -2146,7 +2146,7 @@ static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv) /* fill in channel group's nominal powers for each rate */ for (rate_index = 0; - rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) { + rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) { switch (rate_index) { case IWL_RATE_36M_INDEX_TABLE: if (i == 0) /* B/G */ -- cgit v1.2.3 From 1382c71c764540880d35485b033a44ce104d8e2e Mon Sep 17 00:00:00 2001 From: Reinette Chatre Date: Thu, 25 Feb 2010 10:02:19 -0800 Subject: Revert "iwlwifi: Send broadcast probe request only when asked to" This reverts commit 21b2d8bd2f0d4e0f21ade147fd193c8b9c1fd2b9. As explained by Johannes: When we build a probe request frame in the buffer with the SSID, we could arrive over the limit of 200 bytes. When we build it in the buffer without the SSID (wildcard) we don't arrive over 200 bytes, but the ucode still allows direct probe in addition because it has an internal buffer that is larger when it inserts the SSID... Signed-off-by: Reinette Chatre --- drivers/net/wireless/iwlwifi/iwl-agn.c | 2 +- drivers/net/wireless/iwlwifi/iwl-scan.c | 49 +++++++++++---------------------- 2 files changed, 17 insertions(+), 34 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index 47b021477967..818367b57bab 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c @@ -2653,7 +2653,7 @@ static int iwl_mac_setup_register(struct iwl_priv *priv) */ hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; - hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX + 1; + hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; /* we create the 802.11 header and a zero-length SSID element */ hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2; diff --git a/drivers/net/wireless/iwlwifi/iwl-scan.c b/drivers/net/wireless/iwlwifi/iwl-scan.c index dd9ff2ed645a..bd2f7c420563 100644 --- a/drivers/net/wireless/iwlwifi/iwl-scan.c +++ b/drivers/net/wireless/iwlwifi/iwl-scan.c @@ -638,20 +638,9 @@ u16 iwl_fill_probe_req(struct iwl_priv *priv, struct ieee80211_mgmt *frame, if (left < 0) return 0; *pos++ = WLAN_EID_SSID; - if (!priv->is_internal_short_scan && - priv->scan_request->n_ssids) { - struct cfg80211_ssid *ssid = - priv->scan_request->ssids; - - /* Broadcast if ssid_len is 0 */ - *pos++ = ssid->ssid_len; - memcpy(pos, ssid->ssid, ssid->ssid_len); - pos += ssid->ssid_len; - len += 2 + ssid->ssid_len; - } else { - *pos++ = 0; - len += 2; - } + *pos++ = 0; + + len += 2; if (WARN_ON(left < ie_len)) return len; @@ -780,26 +769,20 @@ static void iwl_bg_request_scan(struct work_struct *data) if (priv->is_internal_short_scan) { IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n"); } else if (priv->scan_request->n_ssids) { + int i, p = 0; IWL_DEBUG_SCAN(priv, "Kicking off active scan\n"); - /* - * The first SSID to scan is stuffed into the probe request - * template and the remaining ones are handled through the - * direct_scan array. - */ - if (priv->scan_request->n_ssids > 1) { - int i, p = 0; - for (i = 1; i < priv->scan_request->n_ssids; i++) { - if (!priv->scan_request->ssids[i].ssid_len) - continue; - scan->direct_scan[p].id = WLAN_EID_SSID; - scan->direct_scan[p].len = - priv->scan_request->ssids[i].ssid_len; - memcpy(scan->direct_scan[p].ssid, - priv->scan_request->ssids[i].ssid, - priv->scan_request->ssids[i].ssid_len); - n_probes++; - p++; - } + for (i = 0; i < priv->scan_request->n_ssids; i++) { + /* always does wildcard anyway */ + if (!priv->scan_request->ssids[i].ssid_len) + continue; + scan->direct_scan[p].id = WLAN_EID_SSID; + scan->direct_scan[p].len = + priv->scan_request->ssids[i].ssid_len; + memcpy(scan->direct_scan[p].ssid, + priv->scan_request->ssids[i].ssid, + priv->scan_request->ssids[i].ssid_len); + n_probes++; + p++; } is_active = true; } else -- cgit v1.2.3 From c90c6a885ac9827921e8f94f3ce4360ae11148f1 Mon Sep 17 00:00:00 2001 From: Thadeu Lima de Souza Cascardo Date: Tue, 9 Mar 2010 20:38:47 -0800 Subject: Input: mousedev - remove BKL There's no need for BKL in mousedev, relevan protection is provided by a private mutex. Signed-off-by: Thadeu Lima de Souza Cascardo Acked-by: Arnd Bergmann Signed-off-by: Dmitry Torokhov --- drivers/input/mousedev.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'drivers') diff --git a/drivers/input/mousedev.c b/drivers/input/mousedev.c index a13d80f7da17..f34b22bce4ff 100644 --- a/drivers/input/mousedev.c +++ b/drivers/input/mousedev.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include @@ -542,10 +541,8 @@ static int mousedev_open(struct inode *inode, struct file *file) if (i >= MOUSEDEV_MINORS) return -ENODEV; - lock_kernel(); error = mutex_lock_interruptible(&mousedev_table_mutex); if (error) { - unlock_kernel(); return error; } mousedev = mousedev_table[i]; @@ -554,7 +551,6 @@ static int mousedev_open(struct inode *inode, struct file *file) mutex_unlock(&mousedev_table_mutex); if (!mousedev) { - unlock_kernel(); return -ENODEV; } @@ -575,7 +571,6 @@ static int mousedev_open(struct inode *inode, struct file *file) goto err_free_client; file->private_data = client; - unlock_kernel(); return 0; err_free_client: @@ -583,7 +578,6 @@ static int mousedev_open(struct inode *inode, struct file *file) kfree(client); err_put_mousedev: put_device(&mousedev->dev); - unlock_kernel(); return error; } -- cgit v1.2.3 From 77554b4d1fac6a66d4e624a6e36c020a4f5b6b64 Mon Sep 17 00:00:00 2001 From: Thadeu Lima de Souza Cascardo Date: Tue, 9 Mar 2010 20:38:47 -0800 Subject: Input: serio_raw - remove BKL serio_raw open function already uses a mutex. Also change formatting a bit. Signed-off-by: Thadeu Lima de Souza Cascardo Acked-by: Arnd Bergmann Signed-off-by: Dmitry Torokhov --- drivers/input/serio/serio_raw.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/input/serio/serio_raw.c b/drivers/input/serio/serio_raw.c index 27fdaaffbb40..998664854440 100644 --- a/drivers/input/serio/serio_raw.c +++ b/drivers/input/serio/serio_raw.c @@ -81,12 +81,12 @@ static int serio_raw_open(struct inode *inode, struct file *file) struct serio_raw_list *list; int retval = 0; - lock_kernel(); retval = mutex_lock_interruptible(&serio_raw_mutex); if (retval) - goto out_bkl; + return retval; - if (!(serio_raw = serio_raw_locate(iminor(inode)))) { + serio_raw = serio_raw_locate(iminor(inode)); + if (!serio_raw) { retval = -ENODEV; goto out; } @@ -96,7 +96,8 @@ static int serio_raw_open(struct inode *inode, struct file *file) goto out; } - if (!(list = kzalloc(sizeof(struct serio_raw_list), GFP_KERNEL))) { + list = kzalloc(sizeof(struct serio_raw_list), GFP_KERNEL); + if (!list) { retval = -ENOMEM; goto out; } @@ -109,8 +110,6 @@ static int serio_raw_open(struct inode *inode, struct file *file) out: mutex_unlock(&serio_raw_mutex); -out_bkl: - unlock_kernel(); return retval; } -- cgit v1.2.3 From 2f2177c8dadbcb08c14f796ac983c5475eca1bd3 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 9 Mar 2010 20:38:48 -0800 Subject: Input: remove BKL, fix input_open_file() locking Holding the BKL in input_open_file seems pointless because it does not protect against updates of input_table, and all open functions from the underlying drivers have proper mutex locking. This makes input_open_file take the input_mutex when accessing the table and no lock when calling into the lower function. Signed-off-by: Arnd Bergmann Acked-by: Thadeu Lima de Souza Cascardo Signed-off-by: Dmitry Torokhov --- drivers/input/input.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/input/input.c b/drivers/input/input.c index e2dd8858e19d..e2aad0a51826 100644 --- a/drivers/input/input.c +++ b/drivers/input/input.c @@ -1879,35 +1879,37 @@ static int input_open_file(struct inode *inode, struct file *file) const struct file_operations *old_fops, *new_fops = NULL; int err; - lock_kernel(); + err = mutex_lock_interruptible(&input_mutex); + if (err) + return err; + /* No load-on-demand here? */ handler = input_table[iminor(inode) >> 5]; - if (!handler || !(new_fops = fops_get(handler->fops))) { - err = -ENODEV; - goto out; - } + if (handler) + new_fops = fops_get(handler->fops); + + mutex_unlock(&input_mutex); /* * That's _really_ odd. Usually NULL ->open means "nothing special", * not "no device". Oh, well... */ - if (!new_fops->open) { + if (!new_fops || !new_fops->open) { fops_put(new_fops); err = -ENODEV; goto out; } + old_fops = file->f_op; file->f_op = new_fops; err = new_fops->open(inode, file); - if (err) { fops_put(file->f_op); file->f_op = fops_get(old_fops); } fops_put(old_fops); out: - unlock_kernel(); return err; } -- cgit v1.2.3 From eb8bff85c5bd5caef7c374ff32b86545029efb56 Mon Sep 17 00:00:00 2001 From: Thomas Bächler Date: Tue, 9 Mar 2010 20:38:48 -0800 Subject: Input: alps - add support for the touchpad on Toshiba Tecra A11-11L MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Thomas Bächler Cc: stable@kernel.org Signed-off-by: Dmitry Torokhov --- drivers/input/mouse/alps.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/input/mouse/alps.c b/drivers/input/mouse/alps.c index f93c2c0daf1f..f6dad83539e0 100644 --- a/drivers/input/mouse/alps.c +++ b/drivers/input/mouse/alps.c @@ -63,6 +63,8 @@ static const struct alps_model_info alps_model_data[] = { { { 0x62, 0x02, 0x14 }, 0xcf, 0xcf, ALPS_PASS | ALPS_DUALPOINT | ALPS_PS2_INTERLEAVED }, { { 0x73, 0x02, 0x50 }, 0xcf, 0xcf, ALPS_FOUR_BUTTONS }, /* Dell Vostro 1400 */ + { { 0x52, 0x01, 0x14 }, 0xff, 0xff, + ALPS_PASS | ALPS_DUALPOINT | ALPS_PS2_INTERLEAVED }, /* Toshiba Tecra A11-11L */ }; /* -- cgit v1.2.3 From 9e49f6c1339a7972e23a335c4c71a289b4c6f65b Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 9 Mar 2010 20:38:45 -0800 Subject: Input: bf54x-keys - fix system hang when pressing a key We need to use the nosync version of disable_irq so that we don't hang in the IRQ handler as we don't ACK the interrupt until later. This used to work regardless, but at some point, the IRQ behavior changed. Not sure when exactly. Signed-off-by: Mike Frysinger Signed-off-by: Dmitry Torokhov --- drivers/input/keyboard/bf54x-keys.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/input/keyboard/bf54x-keys.c b/drivers/input/keyboard/bf54x-keys.c index fe376a27fe57..593c052416b9 100644 --- a/drivers/input/keyboard/bf54x-keys.c +++ b/drivers/input/keyboard/bf54x-keys.c @@ -162,7 +162,7 @@ static irqreturn_t bfin_kpad_isr(int irq, void *dev_id) input_sync(input); if (bfin_kpad_get_keypressed(bf54x_kpad)) { - disable_irq(bf54x_kpad->irq); + disable_irq_nosync(bf54x_kpad->irq); bf54x_kpad->lastkey = key; mod_timer(&bf54x_kpad->timer, jiffies + bf54x_kpad->keyup_test_jiffies); -- cgit v1.2.3 From 06a09124b5ec65f81df66c56695d9a9ae04a0114 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 9 Mar 2010 20:38:45 -0800 Subject: Input: ads7846 - add support for AD7843 parts The AD7873 is almost identical to the ADS7846; the only difference is related to the Power Management bits PD0 and PD1. This results in a slightly different PENIRQ enable behavior. For the AD7873, VREF should be turned off during differential measurements. So, add the AD7873/43 to the list of driver supported devices, and prevent VREF usage during differential/ratiometric conversion modes. Signed-off-by: Michael Hennerich Signed-off-by: Mike Frysinger Signed-off-by: Dmitry Torokhov --- drivers/input/touchscreen/Kconfig | 9 +++++---- drivers/input/touchscreen/ads7846.c | 10 ++++++++++ include/linux/spi/ads7846.h | 2 +- 3 files changed, 16 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 7208654a94ae..8a8fa4d2d6a8 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -24,17 +24,18 @@ config TOUCHSCREEN_88PM860X module will be called 88pm860x-ts. config TOUCHSCREEN_ADS7846 - tristate "ADS7846/TSC2046 and ADS7843 based touchscreens" + tristate "ADS7846/TSC2046/AD7873 and AD(S)7843 based touchscreens" depends on SPI_MASTER depends on HWMON = n || HWMON help Say Y here if you have a touchscreen interface using the - ADS7846/TSC2046 or ADS7843 controller, and your board-specific - setup code includes that in its table of SPI devices. + ADS7846/TSC2046/AD7873 or ADS7843/AD7843 controller, + and your board-specific setup code includes that in its + table of SPI devices. If HWMON is selected, and the driver is told the reference voltage on your board, you will also get hwmon interfaces for the voltage - (and on ads7846/tsc2046, temperature) sensors of this chip. + (and on ads7846/tsc2046/ad7873, temperature) sensors of this chip. If unsure, say N (but it's safe to say "Y"). diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c index 8b05d8e97543..d187be05955f 100644 --- a/drivers/input/touchscreen/ads7846.c +++ b/drivers/input/touchscreen/ads7846.c @@ -36,6 +36,7 @@ * TSC2046 is just newer ads7846 silicon. * Support for ads7843 tested on Atmel at91sam926x-EK. * Support for ads7845 has only been stubbed in. + * Support for Analog Devices AD7873 and AD7843 tested. * * IRQ handling needs a workaround because of a shortcoming in handling * edge triggered IRQs on some platforms like the OMAP1/2. These @@ -984,6 +985,15 @@ static int __devinit ads7846_probe(struct spi_device *spi) vref = pdata->keep_vref_on; + if (ts->model == 7873) { + /* The AD7873 is almost identical to the ADS7846 + * keep VREF off during differential/ratiometric + * conversion modes + */ + ts->model = 7846; + vref = 0; + } + /* set up the transfers to read touchscreen state; this assumes we * use formula #2 for pressure, not #3. */ diff --git a/include/linux/spi/ads7846.h b/include/linux/spi/ads7846.h index 51948eb6927a..5710c15d394a 100644 --- a/include/linux/spi/ads7846.h +++ b/include/linux/spi/ads7846.h @@ -12,7 +12,7 @@ enum ads7846_filter { }; struct ads7846_platform_data { - u16 model; /* 7843, 7845, 7846. */ + u16 model; /* 7843, 7845, 7846, 7873. */ u16 vref_delay_usecs; /* 0 for external vref; etc */ u16 vref_mv; /* external vref value, milliVolts */ bool keep_vref_on; /* set to keep vref on for differential -- cgit v1.2.3 From 4eb6f91b95e7618eae0103b6cba7c7f01f9d40f3 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 9 Mar 2010 20:38:47 -0800 Subject: Input: ad7877 - increase pen up imeout The time interval between consecutive interrupts depends on a number of tunables: first_conversion_delay, acquisition_time, averaging and foremost the pen_down_acc_interval. Since the mod_timer() action for the PEN UP event happens in the spi_async() callback function, latencies incurred by the spi bus drivers also need to be taken into account. So all in all, give the PEN UP event a bit more wiggle room and increase timeout to 100ms. Signed-off-by: Michael Hennerich Signed-off-by: Mike Frysinger Signed-off-by: Dmitry Torokhov --- drivers/input/touchscreen/ad7877.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/input/touchscreen/ad7877.c b/drivers/input/touchscreen/ad7877.c index eb83939c705e..e019d53d1ab4 100644 --- a/drivers/input/touchscreen/ad7877.c +++ b/drivers/input/touchscreen/ad7877.c @@ -46,7 +46,7 @@ #include #include -#define TS_PEN_UP_TIMEOUT msecs_to_jiffies(50) +#define TS_PEN_UP_TIMEOUT msecs_to_jiffies(100) #define MAX_SPI_FREQ_HZ 20000000 #define MAX_12BIT ((1<<12)-1) -- cgit v1.2.3 From 5c1f96f4cffbdde9e194f3ae5373953f3fa12836 Mon Sep 17 00:00:00 2001 From: Thomas Weber Date: Wed, 3 Mar 2010 09:16:54 +0100 Subject: OMAP: DSS2: VRAM: Fix early_param for vram In commit 2b0d8c251b8876d530a6bf671eb5425838fa698a the __early_param is replaced with the generic early_param. This patch fixes the parameter passing for the vram. Signed-off-by: Thomas Weber [tomi.valkeinen@nokia.com: changed the commit prefix] Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/vram.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/video/omap2/vram.c b/drivers/video/omap2/vram.c index 55a4de5e5d10..b266ffae0bde 100644 --- a/drivers/video/omap2/vram.c +++ b/drivers/video/omap2/vram.c @@ -511,13 +511,14 @@ static u32 omap_vram_sdram_size __initdata; static u32 omap_vram_def_sdram_size __initdata; static u32 omap_vram_def_sdram_start __initdata; -static void __init omap_vram_early_vram(char **p) +static int __init omap_vram_early_vram(char *p) { - omap_vram_def_sdram_size = memparse(*p, p); - if (**p == ',') - omap_vram_def_sdram_start = simple_strtoul((*p) + 1, p, 16); + omap_vram_def_sdram_size = memparse(p, &p); + if (*p == ',') + omap_vram_def_sdram_start = simple_strtoul(p + 1, &p, 16); + return 0; } -__early_param("vram=", omap_vram_early_vram); +early_param("vram", omap_vram_early_vram); /* * Called from map_io. We need to call to this early enough so that we -- cgit v1.2.3 From 2886539d5e649c22a6d2107eb431d3bee81e0e6d Mon Sep 17 00:00:00 2001 From: Rafi Rubin Date: Wed, 10 Mar 2010 16:10:28 +0100 Subject: HID: ntrig: fix touch events This reinstates the lost unpressing of BTN_TOUCH. To prevent undesireably touch toggles this also deals with tip switch events. Added a trap to prevent going out of bounds for hidinputs with empty reports. Clear bits of unused buttons which result in misidentification. Signed-off-by: Rafi Rubin Signed-off-by: Jiri Kosina --- drivers/hid/hid-ntrig.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/hid/hid-ntrig.c b/drivers/hid/hid-ntrig.c index 3234c729a895..edcc0c4247bb 100644 --- a/drivers/hid/hid-ntrig.c +++ b/drivers/hid/hid-ntrig.c @@ -140,6 +140,9 @@ static int ntrig_event (struct hid_device *hid, struct hid_field *field, nd->reading_mt = 1; nd->first_contact_confidence = 0; break; + case HID_DG_TIPSWITCH: + /* Prevent emission of touch until validated */ + return 1; case HID_DG_CONFIDENCE: nd->confidence = value; break; @@ -259,6 +262,7 @@ static int ntrig_event (struct hid_device *hid, struct hid_field *field, BTN_TOOL_TRIPLETAP, 0); input_report_key(input, BTN_TOOL_QUADTAP, 0); + input_report_key(input, BTN_TOUCH, 0); } break; @@ -308,13 +312,20 @@ static int ntrig_probe(struct hid_device *hdev, const struct hid_device_id *id) list_for_each_entry(hidinput, &hdev->inputs, list) { + if (hidinput->report->maxfield < 1) + continue; + input = hidinput->input; switch (hidinput->report->field[0]->application) { case HID_DG_PEN: input->name = "N-Trig Pen"; break; case HID_DG_TOUCHSCREEN: + /* These keys are redundant for fingers, clear them + * to prevent incorrect identification */ __clear_bit(BTN_TOOL_PEN, input->keybit); + __clear_bit(BTN_TOOL_FINGER, input->keybit); + __clear_bit(BTN_0, input->keybit); /* * A little something special to enable * two and three finger taps. -- cgit v1.2.3 From fe7a26257a4191de6047f7e1d38832472eb22f85 Mon Sep 17 00:00:00 2001 From: Ursula Braun Date: Mon, 8 Mar 2010 20:36:53 +0000 Subject: qeth: enable kmsg hash processing in qeth_core_sys.c provide qeth kmsg definitions to enable hash string generation for kernel message created with dev_err(). Signed-off-by: Ursula Braun Signed-off-by: Frank Blaschka Signed-off-by: David S. Miller --- drivers/s390/net/qeth_core_sys.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/s390/net/qeth_core_sys.c b/drivers/s390/net/qeth_core_sys.c index 88ae4357136a..25dfd5abd19b 100644 --- a/drivers/s390/net/qeth_core_sys.c +++ b/drivers/s390/net/qeth_core_sys.c @@ -8,6 +8,9 @@ * Frank Blaschka */ +#define KMSG_COMPONENT "qeth" +#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt + #include #include #include -- cgit v1.2.3 From 21fde749cbf71d03e8cf87a7a9a45349597e138a Mon Sep 17 00:00:00 2001 From: Frank Blaschka Date: Mon, 8 Mar 2010 20:36:54 +0000 Subject: qeth: l3 send dhcp in non pass thru mode dhcp frames are valid IPv4 packets so there is no need to send them in pass thru mode. This allows dhcp packets to pass HiperSockets. Also the dhcp release frame is send out correctly with this patch. Signed-off-by: Frank Blaschka Signed-off-by: Martin Schwidefsky Signed-off-by: David S. Miller --- drivers/s390/net/qeth_core.h | 3 ++- drivers/s390/net/qeth_l3_main.c | 10 ++++------ 2 files changed, 6 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/s390/net/qeth_core.h b/drivers/s390/net/qeth_core.h index a3ac4456e0b1..fcd005aad989 100644 --- a/drivers/s390/net/qeth_core.h +++ b/drivers/s390/net/qeth_core.h @@ -763,7 +763,8 @@ static inline int qeth_get_micros(void) static inline int qeth_get_ip_version(struct sk_buff *skb) { - switch (skb->protocol) { + struct ethhdr *ehdr = (struct ethhdr *)skb->data; + switch (ehdr->h_proto) { case ETH_P_IPV6: return 6; case ETH_P_IP: diff --git a/drivers/s390/net/qeth_l3_main.c b/drivers/s390/net/qeth_l3_main.c index 5475834ab916..42fe92c08c29 100644 --- a/drivers/s390/net/qeth_l3_main.c +++ b/drivers/s390/net/qeth_l3_main.c @@ -2900,10 +2900,8 @@ static int qeth_l3_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) int data_offset = -1; int nr_frags; - if ((card->info.type == QETH_CARD_TYPE_IQD) && - (((skb->protocol != htons(ETH_P_IPV6)) && - (skb->protocol != htons(ETH_P_IP))) || - card->options.sniffer)) + if (((card->info.type == QETH_CARD_TYPE_IQD) && (!ipv)) || + card->options.sniffer) goto tx_drop; if ((card->state != CARD_STATE_UP) || !card->lan_online) { @@ -2949,14 +2947,14 @@ static int qeth_l3_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) if (data_offset < 0) skb_pull(new_skb, ETH_HLEN); } else { - if (new_skb->protocol == htons(ETH_P_IP)) { + if (ipv == 4) { if (card->dev->type == ARPHRD_IEEE802_TR) skb_pull(new_skb, TR_HLEN); else skb_pull(new_skb, ETH_HLEN); } - if (new_skb->protocol == ETH_P_IPV6 && card->vlangrp && + if (ipv == 6 && card->vlangrp && vlan_tx_tag_present(new_skb)) { skb_push(new_skb, VLAN_HLEN); skb_copy_to_linear_data(new_skb, new_skb->data + 4, 4); -- cgit v1.2.3 From a959189a978e0104e8aa7f1522f5eff42d891456 Mon Sep 17 00:00:00 2001 From: Ursula Braun Date: Mon, 8 Mar 2010 20:36:55 +0000 Subject: qeth: set promisc off after trace disabling failure If HiperSockets Network Traffic Analyzer is switched off, but trace disabling fails somehow, the qeth driver does not switch off its promisc mode status. A following sniffer reactivation fails, since qeth does not see a need to reenable tracing. At the same time the code analyzing results of trace commands is restructured. Signed-off-by: Ursula Braun Signed-off-by: Frank Blaschka Signed-off-by: David S. Miller --- drivers/s390/net/qeth_l3_main.c | 56 ++++++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 26 deletions(-) (limited to 'drivers') diff --git a/drivers/s390/net/qeth_l3_main.c b/drivers/s390/net/qeth_l3_main.c index 42fe92c08c29..cd746da2951e 100644 --- a/drivers/s390/net/qeth_l3_main.c +++ b/drivers/s390/net/qeth_l3_main.c @@ -1691,39 +1691,43 @@ qeth_diags_trace_cb(struct qeth_card *card, struct qeth_reply *reply, cmd = (struct qeth_ipa_cmd *)data; rc = cmd->hdr.return_code; - if (rc) { + if (rc) QETH_DBF_TEXT_(TRACE, 2, "dxter%x", rc); - if (cmd->data.diagass.action == QETH_DIAGS_CMD_TRACE_ENABLE) { - switch (rc) { - case IPA_RC_HARDWARE_AUTH_ERROR: - dev_warn(&card->gdev->dev, "The device is not " - "authorized to run as a HiperSockets " - "network traffic analyzer\n"); - break; - case IPA_RC_TRACE_ALREADY_ACTIVE: - dev_warn(&card->gdev->dev, "A HiperSockets " - "network traffic analyzer is already " - "active in the HiperSockets LAN\n"); - break; - default: - break; - } - } - return 0; - } - switch (cmd->data.diagass.action) { case QETH_DIAGS_CMD_TRACE_QUERY: break; case QETH_DIAGS_CMD_TRACE_DISABLE: - card->info.promisc_mode = SET_PROMISC_MODE_OFF; - dev_info(&card->gdev->dev, "The HiperSockets network traffic " - "analyzer is deactivated\n"); + switch (rc) { + case 0: + case IPA_RC_INVALID_SUBCMD: + card->info.promisc_mode = SET_PROMISC_MODE_OFF; + dev_info(&card->gdev->dev, "The HiperSockets network " + "traffic analyzer is deactivated\n"); + break; + default: + break; + } break; case QETH_DIAGS_CMD_TRACE_ENABLE: - card->info.promisc_mode = SET_PROMISC_MODE_ON; - dev_info(&card->gdev->dev, "The HiperSockets network traffic " - "analyzer is activated\n"); + switch (rc) { + case 0: + card->info.promisc_mode = SET_PROMISC_MODE_ON; + dev_info(&card->gdev->dev, "The HiperSockets network " + "traffic analyzer is activated\n"); + break; + case IPA_RC_HARDWARE_AUTH_ERROR: + dev_warn(&card->gdev->dev, "The device is not " + "authorized to run as a HiperSockets network " + "traffic analyzer\n"); + break; + case IPA_RC_TRACE_ALREADY_ACTIVE: + dev_warn(&card->gdev->dev, "A HiperSockets " + "network traffic analyzer is already " + "active in the HiperSockets LAN\n"); + break; + default: + break; + } break; default: QETH_DBF_MESSAGE(2, "Unknown sniffer action (0x%04x) on %s\n", -- cgit v1.2.3 From 869da90b9ae39f0d5b9b5aa3a84502684a6aa1f4 Mon Sep 17 00:00:00 2001 From: Ursula Braun Date: Mon, 8 Mar 2010 20:36:56 +0000 Subject: qeth: no recovery after layer mismatch (z/VM NICs) Depending on their definition in z/VM, virtual devices for z/VM VSWITCH or GuestLAN must be configured either in layer2 or in layer3 mode. If qeth detects a layer mismatch, device activation fails. Trying to recover from this error cannot help; thus scheduling a recovery should be avoided. In addition, since recovery is forbidden during online setting of a qeth device, existence of its network device is guaranteed for all dev_close() calls in qeth. The corresponding checks can be removed. Signed-off-by: Ursula Braun Signed-off-by: Frank Blaschka Signed-off-by: David S. Miller --- drivers/s390/net/qeth_core_main.c | 3 ++- drivers/s390/net/qeth_l2_main.c | 16 ++++++---------- drivers/s390/net/qeth_l3_main.c | 16 ++++++---------- 3 files changed, 14 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/s390/net/qeth_core_main.c b/drivers/s390/net/qeth_core_main.c index fa8a519218ac..834830a4866d 100644 --- a/drivers/s390/net/qeth_core_main.c +++ b/drivers/s390/net/qeth_core_main.c @@ -537,7 +537,8 @@ static void qeth_send_control_data_cb(struct qeth_channel *channel, dev_err(&card->gdev->dev, "The qeth device is not configured " "for the OSI layer required by z/VM\n"); - qeth_schedule_recovery(card); + else + qeth_schedule_recovery(card); goto out; } diff --git a/drivers/s390/net/qeth_l2_main.c b/drivers/s390/net/qeth_l2_main.c index 51fde6f2e0b8..6f1e3036bafd 100644 --- a/drivers/s390/net/qeth_l2_main.c +++ b/drivers/s390/net/qeth_l2_main.c @@ -1071,11 +1071,9 @@ static int qeth_l2_recover(void *ptr) dev_info(&card->gdev->dev, "Device successfully recovered!\n"); else { - if (card->dev) { - rtnl_lock(); - dev_close(card->dev); - rtnl_unlock(); - } + rtnl_lock(); + dev_close(card->dev); + rtnl_unlock(); dev_warn(&card->gdev->dev, "The qeth device driver " "failed to recover an error on the device\n"); } @@ -1129,11 +1127,9 @@ static int qeth_l2_pm_resume(struct ccwgroup_device *gdev) if (card->state == CARD_STATE_RECOVER) { rc = __qeth_l2_set_online(card->gdev, 1); if (rc) { - if (card->dev) { - rtnl_lock(); - dev_close(card->dev); - rtnl_unlock(); - } + rtnl_lock(); + dev_close(card->dev); + rtnl_unlock(); } } else rc = __qeth_l2_set_online(card->gdev, 0); diff --git a/drivers/s390/net/qeth_l3_main.c b/drivers/s390/net/qeth_l3_main.c index cd746da2951e..b3b6e872d806 100644 --- a/drivers/s390/net/qeth_l3_main.c +++ b/drivers/s390/net/qeth_l3_main.c @@ -2219,11 +2219,9 @@ static int qeth_l3_stop_card(struct qeth_card *card, int recovery_mode) if (recovery_mode) qeth_l3_stop(card->dev); else { - if (card->dev) { - rtnl_lock(); - dev_close(card->dev); - rtnl_unlock(); - } + rtnl_lock(); + dev_close(card->dev); + rtnl_unlock(); } if (!card->use_hard_stop) { rc = qeth_send_stoplan(card); @@ -3536,11 +3534,9 @@ static int qeth_l3_pm_resume(struct ccwgroup_device *gdev) if (card->state == CARD_STATE_RECOVER) { rc = __qeth_l3_set_online(card->gdev, 1); if (rc) { - if (card->dev) { - rtnl_lock(); - dev_close(card->dev); - rtnl_unlock(); - } + rtnl_lock(); + dev_close(card->dev); + rtnl_unlock(); } } else rc = __qeth_l3_set_online(card->gdev, 0); -- cgit v1.2.3 From 78cb27939ff4fd66d7f76cfe7c59c0fdf1b29ed8 Mon Sep 17 00:00:00 2001 From: Frank Blaschka Date: Mon, 8 Mar 2010 20:36:57 +0000 Subject: qeth: change checksumming default for HiperSockets Deactivate inbound checksumming on HiperSocket is a valid but dangerous optimization in case the frame is routed from an OSA network to an HiperSockets network. To go for sure we change the default to software checksumming. Signed-off-by: Frank Blaschka Signed-off-by: David S. Miller --- drivers/s390/net/qeth_core_main.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers') diff --git a/drivers/s390/net/qeth_core_main.c b/drivers/s390/net/qeth_core_main.c index 834830a4866d..c9f5af5fe9f0 100644 --- a/drivers/s390/net/qeth_core_main.c +++ b/drivers/s390/net/qeth_core_main.c @@ -1114,8 +1114,6 @@ static int qeth_setup_card(struct qeth_card *card) card->ipato.enabled = 0; card->ipato.invert4 = 0; card->ipato.invert6 = 0; - if (card->info.type == QETH_CARD_TYPE_IQD) - card->options.checksum_type = NO_CHECKSUMMING; /* init QDIO stuff */ qeth_init_qdio_info(card); return 0; -- cgit v1.2.3 From fe234f0e5cbb880792d2d1ac0743cf8c07e9dde3 Mon Sep 17 00:00:00 2001 From: Louis Rilling Date: Tue, 9 Mar 2010 06:14:41 +0000 Subject: tg3: Fix tg3_poll_controller() passing wrong pointer to tg3_interrupt() Commit 09943a1819a240ff4a72f924d0038818fcdd0a90 Author: Matt Carlson Date: Fri Aug 28 14:01:57 2009 +0000 tg3: Convert ISR parameter to tnapi forgot to update tg3_poll_controller(), leading to intermittent crashes with netpoll. Fix this. Signed-off-by: Louis Rilling Cc: stable@kernel.org Signed-off-by: David S. Miller --- drivers/net/tg3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 0fa7688ab483..c3b4fe74cd6b 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -5279,7 +5279,7 @@ static void tg3_poll_controller(struct net_device *dev) struct tg3 *tp = netdev_priv(dev); for (i = 0; i < tp->irq_cnt; i++) - tg3_interrupt(tp->napi[i].irq_vec, dev); + tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); } #endif -- cgit v1.2.3 From 7f29a3baa825725d29db399663790d15c78cddcf Mon Sep 17 00:00:00 2001 From: Jussi Kivilinna Date: Tue, 9 Mar 2010 12:24:38 +0000 Subject: asix: fix setting mac address for AX88772 Setting new MAC address only worked when device was set to promiscuous mode. Fix MAC address by writing new address to device using undocumented command AX_CMD_READ_NODE_ID+1. Patch is tested with AX88772 device. Signed-off-by: Jussi Kivilinna Acked-by: David Hollis Signed-off-by: David S. Miller --- drivers/net/usb/asix.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/usb/asix.c b/drivers/net/usb/asix.c index 20e34608fa4a..9e05639435f2 100644 --- a/drivers/net/usb/asix.c +++ b/drivers/net/usb/asix.c @@ -54,6 +54,7 @@ static const char driver_name [] = "asix"; #define AX_CMD_WRITE_IPG0 0x12 #define AX_CMD_WRITE_IPG1 0x13 #define AX_CMD_READ_NODE_ID 0x13 +#define AX_CMD_WRITE_NODE_ID 0x14 #define AX_CMD_WRITE_IPG2 0x14 #define AX_CMD_WRITE_MULTI_FILTER 0x16 #define AX88172_CMD_READ_NODE_ID 0x17 @@ -165,6 +166,7 @@ static const char driver_name [] = "asix"; /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */ struct asix_data { u8 multi_filter[AX_MCAST_FILTER_SIZE]; + u8 mac_addr[ETH_ALEN]; u8 phymode; u8 ledmode; u8 eeprom_len; @@ -732,6 +734,30 @@ static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd) return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); } +static int asix_set_mac_address(struct net_device *net, void *p) +{ + struct usbnet *dev = netdev_priv(net); + struct asix_data *data = (struct asix_data *)&dev->data; + struct sockaddr *addr = p; + + if (netif_running(net)) + return -EBUSY; + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + + memcpy(net->dev_addr, addr->sa_data, ETH_ALEN); + + /* We use the 20 byte dev->data + * for our 6 byte mac buffer + * to avoid allocating memory that + * is tricky to free later */ + memcpy(data->mac_addr, addr->sa_data, ETH_ALEN); + asix_write_cmd_async(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, + data->mac_addr); + + return 0; +} + /* We need to override some ethtool_ops so we require our own structure so we don't interfere with other usbnet devices that may be connected at the same time. */ @@ -919,7 +945,7 @@ static const struct net_device_ops ax88772_netdev_ops = { .ndo_start_xmit = usbnet_start_xmit, .ndo_tx_timeout = usbnet_tx_timeout, .ndo_change_mtu = usbnet_change_mtu, - .ndo_set_mac_address = eth_mac_addr, + .ndo_set_mac_address = asix_set_mac_address, .ndo_validate_addr = eth_validate_addr, .ndo_do_ioctl = asix_ioctl, .ndo_set_multicast_list = asix_set_multicast, @@ -1213,7 +1239,7 @@ static const struct net_device_ops ax88178_netdev_ops = { .ndo_stop = usbnet_stop, .ndo_start_xmit = usbnet_start_xmit, .ndo_tx_timeout = usbnet_tx_timeout, - .ndo_set_mac_address = eth_mac_addr, + .ndo_set_mac_address = asix_set_mac_address, .ndo_validate_addr = eth_validate_addr, .ndo_set_multicast_list = asix_set_multicast, .ndo_do_ioctl = asix_ioctl, -- cgit v1.2.3 From 717ea4b3474852057b1ce2c639ce219f4f8d3a8d Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Wed, 10 Mar 2010 07:37:06 -0800 Subject: net: add ColdFire support to the smc91x driver Some embedded ColdFire based boards use the SMC 91x family of ethernet devices. (For example the Freescale M5249C3 and MoretonBay NETtel). Add IO access support to the SMC91x driver, and allow this driver to be configured for ColdFire platforms. Signed-off-by: Greg Ungerer Signed-off-by: David S. Miller --- drivers/net/Kconfig | 2 +- drivers/net/smc91x.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 7029cd50c458..0ba5b8e50a7c 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -907,7 +907,7 @@ config SMC91X select CRC32 select MII depends on ARM || REDWOOD_5 || REDWOOD_6 || M32R || SUPERH || \ - MIPS || BLACKFIN || MN10300 + MIPS || BLACKFIN || MN10300 || COLDFIRE help This is a driver for SMC's 91x series of Ethernet chipsets, including the SMC91C94 and the SMC91C111. Say Y if you want it diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h index a6ee883d1b0e..8d2772cc42f2 100644 --- a/drivers/net/smc91x.h +++ b/drivers/net/smc91x.h @@ -344,6 +344,34 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r, #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH +#elif defined(CONFIG_COLDFIRE) + +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_NOWAIT 1 + +static inline void mcf_insw(void *a, unsigned char *p, int l) +{ + u16 *wp = (u16 *) p; + while (l-- > 0) + *wp++ = readw(a); +} + +static inline void mcf_outsw(void *a, unsigned char *p, int l) +{ + u16 *wp = (u16 *) p; + while (l-- > 0) + writew(*wp++, a); +} + +#define SMC_inw(a, r) _swapw(readw((a) + (r))) +#define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r)) +#define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l) +#define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l) + +#define SMC_IRQ_FLAGS (IRQF_DISABLED) + #else /* -- cgit v1.2.3 From 07081fd8587478849b69d7b41596e81ff5a7f532 Mon Sep 17 00:00:00 2001 From: David Miller Date: Wed, 10 Mar 2010 14:05:35 -0700 Subject: uartlite: Fix build on sparc. We can get this driver enabled via MFD_TIMBERDALE which only requires GPIO to be on. But the of_address_to_resource() function is only present on powerpc and microblaze, so we have to conditionalize the CONFIG_OF probing bits on that. Signed-off-by: David S. Miller Signed-off-by: Grant Likely --- drivers/serial/uartlite.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/uartlite.c b/drivers/serial/uartlite.c index ab2ab3c81834..f0a6c61b17f7 100644 --- a/drivers/serial/uartlite.c +++ b/drivers/serial/uartlite.c @@ -19,7 +19,7 @@ #include #include #include -#if defined(CONFIG_OF) +#if defined(CONFIG_OF) && (defined(CONFIG_PPC32) || defined(CONFIG_MICROBLAZE)) #include #include #include @@ -581,7 +581,7 @@ static struct platform_driver ulite_platform_driver = { /* --------------------------------------------------------------------- * OF bus bindings */ -#if defined(CONFIG_OF) +#if defined(CONFIG_OF) && (defined(CONFIG_PPC32) || defined(CONFIG_MICROBLAZE)) static int __devinit ulite_of_probe(struct of_device *op, const struct of_device_id *match) { @@ -631,11 +631,11 @@ static inline void __exit ulite_of_unregister(void) { of_unregister_platform_driver(&ulite_of_driver); } -#else /* CONFIG_OF */ -/* CONFIG_OF not enabled; do nothing helpers */ +#else /* CONFIG_OF && (CONFIG_PPC32 || CONFIG_MICROBLAZE) */ +/* Appropriate config not enabled; do nothing helpers */ static inline int __init ulite_of_register(void) { return 0; } static inline void __exit ulite_of_unregister(void) { } -#endif /* CONFIG_OF */ +#endif /* CONFIG_OF && (CONFIG_PPC32 || CONFIG_MICROBLAZE) */ /* --------------------------------------------------------------------- * Module setup/teardown -- cgit v1.2.3 From e5a9a35cb9c0d92d7c986cb3696fb794be100087 Mon Sep 17 00:00:00 2001 From: Helmut Schaa Date: Fri, 5 Mar 2010 17:44:22 +0100 Subject: rt2x00: remove KSEG1ADDR define from rt2x00soc.h Remove the KSEG1ADDR define from rt2x00soc.h as it redefines and covers the correct one from the arch/mips/include/asm/addrspace.h. Otherwise the driver oopses on the target platform (Ralink rt3050 board). Signed-off-by: Helmut Schaa Acked-by: Ivo van Doorn Acked-by: Gertjan van Wingerde Signed-off-by: John W. Linville --- drivers/net/wireless/rt2x00/rt2x00soc.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/rt2x00/rt2x00soc.h b/drivers/net/wireless/rt2x00/rt2x00soc.h index 4739edfe2f00..474cbfc1efc7 100644 --- a/drivers/net/wireless/rt2x00/rt2x00soc.h +++ b/drivers/net/wireless/rt2x00/rt2x00soc.h @@ -26,8 +26,6 @@ #ifndef RT2X00SOC_H #define RT2X00SOC_H -#define KSEG1ADDR(__ptr) __ptr - /* * SoC driver handlers. */ -- cgit v1.2.3 From 8e59340e4fb65cfd748eaa1e23db057c52520f35 Mon Sep 17 00:00:00 2001 From: Zhu Yi Date: Mon, 8 Mar 2010 13:18:03 +0800 Subject: libipw: split ieee->networks into small pieces The ieee->networks consists of 128 struct libipw_network entries. If we allocate this chunk of memory altogether, it ends up with an order 4 page allocation. High order page allocation is likely to fail on system high load. This patch splits the big chunk memory allocation into small pieces, each is 344 bytes, allocates them with 128 times. The patch fixed bug http://bugzilla.kernel.org/show_bug.cgi?id=14989 Signed-off-by: Zhu Yi Signed-off-by: John W. Linville --- drivers/net/wireless/ipw2x00/libipw.h | 2 +- drivers/net/wireless/ipw2x00/libipw_module.c | 37 +++++++++++++--------------- 2 files changed, 18 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/ipw2x00/libipw.h b/drivers/net/wireless/ipw2x00/libipw.h index bf45391172f3..a6d5e42647e4 100644 --- a/drivers/net/wireless/ipw2x00/libipw.h +++ b/drivers/net/wireless/ipw2x00/libipw.h @@ -797,7 +797,7 @@ struct libipw_device { /* Probe / Beacon management */ struct list_head network_free_list; struct list_head network_list; - struct libipw_network *networks; + struct libipw_network *networks[MAX_NETWORK_COUNT]; int scans; int scan_age; diff --git a/drivers/net/wireless/ipw2x00/libipw_module.c b/drivers/net/wireless/ipw2x00/libipw_module.c index 1ae0b2b02c38..2fa55867bd8b 100644 --- a/drivers/net/wireless/ipw2x00/libipw_module.c +++ b/drivers/net/wireless/ipw2x00/libipw_module.c @@ -67,16 +67,17 @@ void *libipw_wiphy_privid = &libipw_wiphy_privid; static int libipw_networks_allocate(struct libipw_device *ieee) { - if (ieee->networks) - return 0; - - ieee->networks = - kzalloc(MAX_NETWORK_COUNT * sizeof(struct libipw_network), - GFP_KERNEL); - if (!ieee->networks) { - printk(KERN_WARNING "%s: Out of memory allocating beacons\n", - ieee->dev->name); - return -ENOMEM; + int i, j; + + for (i = 0; i < MAX_NETWORK_COUNT; i++) { + ieee->networks[i] = kzalloc(sizeof(struct libipw_network), + GFP_KERNEL); + if (!ieee->networks[i]) { + LIBIPW_ERROR("Out of memory allocating beacons\n"); + for (j = 0; j < i; j++) + kfree(ieee->networks[j]); + return -ENOMEM; + } } return 0; @@ -97,15 +98,11 @@ static inline void libipw_networks_free(struct libipw_device *ieee) { int i; - if (!ieee->networks) - return; - - for (i = 0; i < MAX_NETWORK_COUNT; i++) - if (ieee->networks[i].ibss_dfs) - kfree(ieee->networks[i].ibss_dfs); - - kfree(ieee->networks); - ieee->networks = NULL; + for (i = 0; i < MAX_NETWORK_COUNT; i++) { + if (ieee->networks[i]->ibss_dfs) + kfree(ieee->networks[i]->ibss_dfs); + kfree(ieee->networks[i]); + } } void libipw_networks_age(struct libipw_device *ieee, @@ -130,7 +127,7 @@ static void libipw_networks_initialize(struct libipw_device *ieee) INIT_LIST_HEAD(&ieee->network_free_list); INIT_LIST_HEAD(&ieee->network_list); for (i = 0; i < MAX_NETWORK_COUNT; i++) - list_add_tail(&ieee->networks[i].list, + list_add_tail(&ieee->networks[i]->list, &ieee->network_free_list); } -- cgit v1.2.3 From 8bd8beab49fec3f7d014c328641bd94de3df744b Mon Sep 17 00:00:00 2001 From: Bruno Randolf Date: Tue, 9 Mar 2010 16:55:23 +0900 Subject: ath5k: use fixed antenna for tx descriptors when using a fixed antenna we should use the antenna number in all tx descriptors, otherwise the hardware will sometimes send the frame out on the other antenna. it seems like the hardware does not always respect the default antenna and diversity settings (esp. AR5K_STA_ID1_DEFAULT_ANTENNA). also i would like to note that antenna diversity does not always work correctly on 5414 (at least) when only one antenna is connected: for example all frames might be received on antenna A but still the HW tries to send on antenna B some times, causing packet loss. this is both verified with the antenna statistics output of the previous patch and a spectrum analyzer. Signed-off-by: Bruno Randolf Acked-by: Nick Kossifidis Signed-off-by: John W. Linville --- drivers/net/wireless/ath/ath5k/phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c index 72474c0ccaff..ffe253ab9be7 100644 --- a/drivers/net/wireless/ath/ath5k/phy.c +++ b/drivers/net/wireless/ath/ath5k/phy.c @@ -1873,7 +1873,7 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) break; case AR5K_ANTMODE_FIXED_A: def_ant = 1; - tx_ant = 0; + tx_ant = 1; use_def_for_tx = true; update_def_on_tx = false; use_def_for_rts = true; @@ -1882,7 +1882,7 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) break; case AR5K_ANTMODE_FIXED_B: def_ant = 2; - tx_ant = 0; + tx_ant = 2; use_def_for_tx = true; update_def_on_tx = false; use_def_for_rts = true; -- cgit v1.2.3 From a3b980fd1391e75068ae25f3817728b27bfdb04c Mon Sep 17 00:00:00 2001 From: Bruno Randolf Date: Tue, 9 Mar 2010 16:55:33 +0900 Subject: ath5k: fix TSF reset to reset the TSF, AR5K_BEACON_RESET_TSF has to be 1, not 0. also we have a function for that so use it. Signed-off-by: Bruno Randolf Acked-by: Nick Kossifidis Signed-off-by: John W. Linville --- drivers/net/wireless/ath/ath5k/reset.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c index a35a7db0fc4c..c780b55020d2 100644 --- a/drivers/net/wireless/ath/ath5k/reset.c +++ b/drivers/net/wireless/ath/ath5k/reset.c @@ -1379,11 +1379,10 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, ath5k_hw_set_sleep_clock(ah, true); /* - * Disable beacons and reset the register + * Disable beacons and reset the TSF */ - AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE | - AR5K_BEACON_RESET_TSF); - + AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE); + ath5k_hw_reset_tsf(ah); return 0; } -- cgit v1.2.3 From 86415d43efd4f7093979cfa8a80232114266f1a4 Mon Sep 17 00:00:00 2001 From: Bruno Randolf Date: Tue, 9 Mar 2010 16:56:05 +0900 Subject: ath5k: fix I/Q calibration (for real) I/Q calibration was completely broken, resulting in a high number of CRC errors on received packets. before i could see around 10% to 20% CRC errors, with this patch they are between 0% and 3%. 1.) the removal of the mask in commit "ath5k: Fix I/Q calibration (f1cf2dbd0f798b71b1590e7aca6647f2caef1649)" resulted in no mask beeing used when writing the I/Q values into the register. additional errors in the calculation of the values (see 2.) resulted too high numbers, exceeding the masks, so wrong values like 0xfffffffe were written. to be safe we should always use the bitmask when writing parts of a register. 2.) using a (s32) cast for q_coff is a wrong conversion to signed, since we convert to a signed value later by substracting 128. this resulted in too low numbers for Q many times, which were limited to -16 by the boundary check later on. 3.) checked everything against the HAL sources and took over comments and minor optimizations from there. 4.) we can't use ENABLE_BITS when we want to write a number (the number can contain zeros). also always write the correction values first and set ENABLE bit last, like the HAL does. Signed-off-by: Bruno Randolf Cc: stable@kernel.org Acked-by: Nick Kossifidis Signed-off-by: John W. Linville --- drivers/net/wireless/ath/ath5k/phy.c | 37 ++++++++++++++++++------------------ drivers/net/wireless/ath/ath5k/reg.h | 1 + 2 files changed, 20 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c index ffe253ab9be7..eff3323efb4b 100644 --- a/drivers/net/wireless/ath/ath5k/phy.c +++ b/drivers/net/wireless/ath/ath5k/phy.c @@ -1386,38 +1386,39 @@ static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, goto done; /* Calibration has finished, get the results and re-run */ + + /* work around empty results which can apparently happen on 5212 */ for (i = 0; i <= 10; i++) { iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); + ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, + "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); + if (i_pwr && q_pwr) + break; } i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; q_coffd = q_pwr >> 7; - /* No correction */ - if (i_coffd == 0 || q_coffd == 0) + /* protect against divide by 0 and loss of sign bits */ + if (i_coffd == 0 || q_coffd < 2) goto done; - i_coff = ((-iq_corr) / i_coffd); + i_coff = (-iq_corr) / i_coffd; + i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ - /* Boundary check */ - if (i_coff > 31) - i_coff = 31; - if (i_coff < -32) - i_coff = -32; + q_coff = (i_pwr / q_coffd) - 128; + q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ - q_coff = (((s32)i_pwr / q_coffd) - 128); + ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, + "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", + i_coff, q_coff, i_coffd, q_coffd); - /* Boundary check */ - if (q_coff > 15) - q_coff = 15; - if (q_coff < -16) - q_coff = -16; - - /* Commit new I/Q value */ - AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | - ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); + /* Commit new I/Q values (set enable bit last to match HAL sources) */ + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); + AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); /* Re-enable calibration -if we don't we'll commit * the same values again and again */ diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h index 4cb9c5df9f46..1464f89b249c 100644 --- a/drivers/net/wireless/ath/ath5k/reg.h +++ b/drivers/net/wireless/ath/ath5k/reg.h @@ -2187,6 +2187,7 @@ */ #define AR5K_PHY_IQ 0x9920 /* Register Address */ #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */ +#define AR5K_PHY_IQ_CORR_Q_Q_COFF_S 0 #define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */ #define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 #define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */ -- cgit v1.2.3 From 5f13bfac0718ce6f83ecba3755f224c3790e8d66 Mon Sep 17 00:00:00 2001 From: Bruno Randolf Date: Tue, 9 Mar 2010 16:56:10 +0900 Subject: ath5k: read eeprom IQ calibration values correctly for G mode we read the IQ correction values (i_cal and q_cal) for G mode from a wrong location (the same shifts as for A mode is applied which is incorrect). use correct locations, matching the docs and HAL sources. also we should write IQ correction only when we have that information in the EEPROM, starting from version 4. also write it in the same way as we do in the periodic recalibration (enable last), just to be sure. Signed-off-by: Bruno Randolf Acked-by: Nick Kossifidis Signed-off-by: John W. Linville --- drivers/net/wireless/ath/ath5k/eeprom.c | 4 ++-- drivers/net/wireless/ath/ath5k/reset.c | 15 +++++++++------ 2 files changed, 11 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/ath/ath5k/eeprom.c b/drivers/net/wireless/ath/ath5k/eeprom.c index 6a3f4da7fb48..10b52262b232 100644 --- a/drivers/net/wireless/ath/ath5k/eeprom.c +++ b/drivers/net/wireless/ath/ath5k/eeprom.c @@ -429,8 +429,8 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset, ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; AR5K_EEPROM_READ(o++, val); - ee->ee_i_cal[mode] = (val >> 8) & 0x3f; - ee->ee_q_cal[mode] = (val >> 3) & 0x1f; + ee->ee_i_cal[mode] = (val >> 5) & 0x3f; + ee->ee_q_cal[mode] = val & 0x1f; if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { AR5K_EEPROM_READ(o++, val); diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c index c780b55020d2..cbf28e379843 100644 --- a/drivers/net/wireless/ath/ath5k/reset.c +++ b/drivers/net/wireless/ath/ath5k/reset.c @@ -851,12 +851,15 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah, AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, AR5K_INIT_CYCRSSI_THR1); - /* I/Q correction - * TODO: Per channel i/q infos ? */ - AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, - AR5K_PHY_IQ_CORR_ENABLE | - (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | - ee->ee_q_cal[ee_mode]); + /* I/Q correction (set enable bit last to match HAL sources) */ + /* TODO: Per channel i/q infos ? */ + if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, + ee->ee_i_cal[ee_mode]); + AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, + ee->ee_q_cal[ee_mode]); + AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); + } /* Heavy clipping -disable for now */ if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1) -- cgit v1.2.3 From 5e7749436d576a525d7b2a4bcffb17b3364b9e00 Mon Sep 17 00:00:00 2001 From: Scott Ellis Date: Wed, 10 Mar 2010 14:22:45 -0700 Subject: spi/omap2_mcspi: fix NULL pointer dereference Check spi->controller_state before dereferencing. Shows up NULL here when using spi_alloc_device()/spi_add_device() and spi_add_device() fails before spi_setup(). Calling spi_dev_put() on the leftover spi_device results in the error. Signed-off-by: Scott Ellis Signed-off-by: Grant Likely --- drivers/spi/omap2_mcspi.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index 715c518b1b68..87d44eeaaa7b 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c @@ -751,11 +751,13 @@ static void omap2_mcspi_cleanup(struct spi_device *spi) mcspi = spi_master_get_devdata(spi->master); mcspi_dma = &mcspi->dma_channels[spi->chip_select]; - /* Unlink controller state from context save list */ - cs = spi->controller_state; - list_del(&cs->node); + if (spi->controller_state) { + /* Unlink controller state from context save list */ + cs = spi->controller_state; + list_del(&cs->node); - kfree(spi->controller_state); + kfree(spi->controller_state); + } if (mcspi_dma->dma_rx_channel != -1) { omap_free_dma(mcspi_dma->dma_rx_channel); -- cgit v1.2.3 From 9bd4517ddc51c803784778ab52e6f0bc03b77a52 Mon Sep 17 00:00:00 2001 From: Scott Ellis Date: Wed, 10 Mar 2010 14:23:13 -0700 Subject: spi/omap2_mcspi: Use transaction speed if provided omap2_mcspi_transfer() gets called in omap2_mcspi_work() when the transaction speed_hz or bits_per_word fields are non-zero. omap2_mcspi_transfer() does not look at the speed_hz field so the override speed value is ignored. The code should probably change to one of these options. 1. Skip the call to omap2_mcsp_transfer() if the only reason was a non-zero speed_hz and it's not going to be used. 2. Use the new speed_hz value provided The patch below uses the speed_hz value. Signed-off-by: Scott Ellis Signed-off-by: Grant Likely --- drivers/spi/omap2_mcspi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index 87d44eeaaa7b..4dd786b99b8b 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c @@ -578,6 +578,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi, struct spi_master *spi_cntrl; u32 l = 0, div = 0; u8 word_len = spi->bits_per_word; + u32 speed_hz = spi->max_speed_hz; mcspi = spi_master_get_devdata(spi->master); spi_cntrl = mcspi->master; @@ -587,9 +588,12 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi, cs->word_len = word_len; - if (spi->max_speed_hz) { + if (t && t->speed_hz) + speed_hz = t->speed_hz; + + if (speed_hz) { while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div)) - > spi->max_speed_hz) + > speed_hz) div++; } else div = 15; -- cgit v1.2.3 From 41093167ec6c1854903a4bc38a37b5740c028984 Mon Sep 17 00:00:00 2001 From: Zhu Yi Date: Tue, 9 Mar 2010 16:05:31 +0800 Subject: ipw2200: use kmalloc for large local variables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixed below compiler warning: drivers/net/wireless/ipw2x00/ipw2200.c: In function ‘ipw_load_firmware’: drivers/net/wireless/ipw2x00/ipw2200.c:3260: warning: the frame size of 1168 bytes is larger than 1024 bytes Signed-off-by: Zhu Yi Signed-off-by: John W. Linville --- drivers/net/wireless/ipw2x00/ipw2200.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/wireless/ipw2x00/ipw2200.c b/drivers/net/wireless/ipw2x00/ipw2200.c index 63c2a7ade5fb..5c7aa1b1eb56 100644 --- a/drivers/net/wireless/ipw2x00/ipw2200.c +++ b/drivers/net/wireless/ipw2x00/ipw2200.c @@ -3177,14 +3177,27 @@ static int ipw_load_firmware(struct ipw_priv *priv, u8 * data, size_t len) int total_nr = 0; int i; struct pci_pool *pool; - u32 *virts[CB_NUMBER_OF_ELEMENTS_SMALL]; - dma_addr_t phys[CB_NUMBER_OF_ELEMENTS_SMALL]; + void **virts; + dma_addr_t *phys; IPW_DEBUG_TRACE("<< : \n"); + virts = kmalloc(sizeof(void *) * CB_NUMBER_OF_ELEMENTS_SMALL, + GFP_KERNEL); + if (!virts) + return -ENOMEM; + + phys = kmalloc(sizeof(dma_addr_t) * CB_NUMBER_OF_ELEMENTS_SMALL, + GFP_KERNEL); + if (!phys) { + kfree(virts); + return -ENOMEM; + } pool = pci_pool_create("ipw2200", priv->pci_dev, CB_MAX_LENGTH, 0, 0); if (!pool) { IPW_ERROR("pci_pool_create failed\n"); + kfree(phys); + kfree(virts); return -ENOMEM; } @@ -3254,6 +3267,8 @@ static int ipw_load_firmware(struct ipw_priv *priv, u8 * data, size_t len) pci_pool_free(pool, virts[i], phys[i]); pci_pool_destroy(pool); + kfree(phys); + kfree(virts); return ret; } -- cgit v1.2.3 From 04b4b88cca0ebe3813b4b6f014fb6a0db380b137 Mon Sep 17 00:00:00 2001 From: Vadim Zaliva Date: Wed, 10 Mar 2010 23:41:00 -0800 Subject: Input: appletouch - fix integer overflow issue When reading data from Geyser 2 touchpads used on post Oct 2005 Apple PowerBooks the driver was casting X and Y coordinates values to 'signed char'. Testing on one of such PowerBooks I have noticed that touchpad always generates positive values, but some of them are greater that 127, and thus, when cast to 'signed char' being interpreted as a negative. Such bigger values have been observed infrequently, closer to the edges of a touchpad, so the problem was not very visible. Nevertheless, the patch would potentially improve touchpad driver accuracy. Signed-off-by: Vadim Zaliva Signed-off-by: Dmitry Torokhov --- drivers/input/mouse/appletouch.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/input/mouse/appletouch.c b/drivers/input/mouse/appletouch.c index 908b5b44052f..53ec7ddd1826 100644 --- a/drivers/input/mouse/appletouch.c +++ b/drivers/input/mouse/appletouch.c @@ -205,8 +205,8 @@ struct atp { bool overflow_warned; int x_old; /* last reported x/y, */ int y_old; /* used for smoothing */ - signed char xy_cur[ATP_XSENSORS + ATP_YSENSORS]; - signed char xy_old[ATP_XSENSORS + ATP_YSENSORS]; + u8 xy_cur[ATP_XSENSORS + ATP_YSENSORS]; + u8 xy_old[ATP_XSENSORS + ATP_YSENSORS]; int xy_acc[ATP_XSENSORS + ATP_YSENSORS]; int idlecount; /* number of empty packets */ struct work_struct work; @@ -531,7 +531,7 @@ static void atp_complete_geyser_1_2(struct urb *urb) for (i = 0; i < ATP_XSENSORS + ATP_YSENSORS; i++) { /* accumulate the change */ - signed char change = dev->xy_old[i] - dev->xy_cur[i]; + int change = dev->xy_old[i] - dev->xy_cur[i]; dev->xy_acc[i] -= change; /* prevent down drifting */ -- cgit v1.2.3 From fdba2bb1f2eed85085a0fe154e1acb82de3239f7 Mon Sep 17 00:00:00 2001 From: Ranjith Lohithakshan Date: Wed, 10 Mar 2010 23:41:22 -0800 Subject: Input: ads7846 - add wakeup support Add wakeup support to the ads7846 driver. Platforms can enable wakeup capability by setting the wakeup flag in ads7846_platform_data. With this patch the ads7846 driver can be used to wake the system from suspend. Signed-off-by: Ranjith Lohithakshan Signed-off-by: Dmitry Torokhov --- drivers/input/touchscreen/ads7846.c | 10 ++++++++++ include/linux/spi/ads7846.h | 1 + 2 files changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c index d187be05955f..532279cda0e4 100644 --- a/drivers/input/touchscreen/ads7846.c +++ b/drivers/input/touchscreen/ads7846.c @@ -822,6 +822,9 @@ static int ads7846_suspend(struct spi_device *spi, pm_message_t message) spin_unlock_irq(&ts->lock); + if (device_may_wakeup(&ts->spi->dev)) + enable_irq_wake(ts->spi->irq); + return 0; } @@ -830,6 +833,9 @@ static int ads7846_resume(struct spi_device *spi) { struct ads7846 *ts = dev_get_drvdata(&spi->dev); + if (device_may_wakeup(&ts->spi->dev)) + disable_irq_wake(ts->spi->irq); + spin_lock_irq(&ts->lock); ts->is_suspended = 0; @@ -1201,6 +1207,8 @@ static int __devinit ads7846_probe(struct spi_device *spi) if (err) goto err_remove_attr_group; + device_init_wakeup(&spi->dev, pdata->wakeup); + return 0; err_remove_attr_group: @@ -1230,6 +1238,8 @@ static int __devexit ads7846_remove(struct spi_device *spi) { struct ads7846 *ts = dev_get_drvdata(&spi->dev); + device_init_wakeup(&spi->dev, false); + ads784x_hwmon_unregister(spi, ts); input_unregister_device(ts->input); diff --git a/include/linux/spi/ads7846.h b/include/linux/spi/ads7846.h index 5710c15d394a..b4ae570d3c98 100644 --- a/include/linux/spi/ads7846.h +++ b/include/linux/spi/ads7846.h @@ -53,5 +53,6 @@ struct ads7846_platform_data { int (*filter) (void *filter_data, int data_idx, int *val); void (*filter_cleanup)(void *filter_data); void (*wait_for_sync)(void); + bool wakeup; }; -- cgit v1.2.3 From afadb8e08c48d08b75f3caf8404742b13e6b3624 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 10 Mar 2010 23:41:33 -0800 Subject: Input: wm831x-on - convert to use genirq Now that the WM831x core has been converted to use genirq for the interrupt controller there is no need for the client drivers to use a WM831x-specific API rather than just calling genirq directly. Also fixes a leak of the IRQ during init failure - the error path free_irq() was using NULL rather than the driver data as the data pointer so free_irq() wouldn't have matched. Signed-off-by: Mark Brown Signed-off-by: Dmitry Torokhov --- drivers/input/misc/wm831x-on.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/input/misc/wm831x-on.c b/drivers/input/misc/wm831x-on.c index ba4f5dd7c60e..1e54bce72db5 100644 --- a/drivers/input/misc/wm831x-on.c +++ b/drivers/input/misc/wm831x-on.c @@ -97,8 +97,9 @@ static int __devinit wm831x_on_probe(struct platform_device *pdev) wm831x_on->dev->phys = "wm831x_on/input0"; wm831x_on->dev->dev.parent = &pdev->dev; - ret = wm831x_request_irq(wm831x, irq, wm831x_on_irq, - IRQF_TRIGGER_RISING, "wm831x_on", wm831x_on); + ret = request_threaded_irq(irq, NULL, wm831x_on_irq, + IRQF_TRIGGER_RISING, "wm831x_on", + wm831x_on); if (ret < 0) { dev_err(&pdev->dev, "Unable to request IRQ: %d\n", ret); goto err_input_dev; @@ -114,7 +115,7 @@ static int __devinit wm831x_on_probe(struct platform_device *pdev) return 0; err_irq: - wm831x_free_irq(wm831x, irq, NULL); + free_irq(irq, wm831x_on); err_input_dev: input_free_device(wm831x_on->dev); err: @@ -127,7 +128,7 @@ static int __devexit wm831x_on_remove(struct platform_device *pdev) struct wm831x_on *wm831x_on = platform_get_drvdata(pdev); int irq = platform_get_irq(pdev, 0); - wm831x_free_irq(wm831x_on->wm831x, irq, wm831x_on); + free_irq(irq, wm831x_on); cancel_delayed_work_sync(&wm831x_on->work); input_unregister_device(wm831x_on->dev); kfree(wm831x_on); -- cgit v1.2.3 From a6475c132278c1be158a13872c233aeab8a00176 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 18 Jan 2010 15:27:10 +0100 Subject: microblaze: Enable PCI, missing files There are two parts of changes. The first is just enable PCI in Makefiles and in Kconfig. The second is the rest of missing files. I didn't want to add it with previous patch because that patch is too big. Current Microblaze toolchain has problem with weak symbols that's why is necessary to apply this changes to be possible to compile pci support. Xilinx knows about this problem. Signed-off-by: Michal Simek --- arch/microblaze/Kconfig | 15 ++++ arch/microblaze/Makefile | 1 + arch/microblaze/include/asm/io.h | 16 +++- arch/microblaze/include/asm/pgtable.h | 15 ++++ arch/microblaze/include/asm/prom.h | 15 ++++ arch/microblaze/pci/Makefile | 5 ++ arch/microblaze/pci/indirect_pci.c | 163 ++++++++++++++++++++++++++++++++++ arch/microblaze/pci/iomap.c | 39 ++++++++ drivers/pci/Makefile | 1 + 9 files changed, 269 insertions(+), 1 deletion(-) create mode 100644 arch/microblaze/pci/Makefile create mode 100644 arch/microblaze/pci/indirect_pci.c create mode 100644 arch/microblaze/pci/iomap.c (limited to 'drivers') diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 71ec04137417..e1fa0844ba4e 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -256,6 +256,21 @@ source "fs/Kconfig.binfmt" endmenu +menu "Bus Options" + +config PCI + bool "PCI support" + +config PCI_DOMAINS + def_bool PCI + +config PCI_SYSCALL + def_bool PCI + +source "drivers/pci/Kconfig" + +endmenu + source "net/Kconfig" source "drivers/Kconfig" diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile index d2d6cfcb1a30..836832dd9b26 100644 --- a/arch/microblaze/Makefile +++ b/arch/microblaze/Makefile @@ -50,6 +50,7 @@ libs-y += $(LIBGCC) core-y += arch/microblaze/kernel/ core-y += arch/microblaze/mm/ core-y += arch/microblaze/platform/ +core-$(CONFIG_PCI) += arch/microblaze/pci/ drivers-$(CONFIG_OPROFILE) += arch/microblaze/oprofile/ diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h index f82df5d221a8..06d804b15a51 100644 --- a/arch/microblaze/include/asm/io.h +++ b/arch/microblaze/include/asm/io.h @@ -17,7 +17,21 @@ #include /* Get struct page {...} */ #include -#define PCI_DRAM_OFFSET 0 +#ifndef CONFIG_PCI +#define _IO_BASE 0 +#define _ISA_MEM_BASE 0 +#define PCI_DRAM_OFFSET 0 +#else +#define _IO_BASE isa_io_base +#define _ISA_MEM_BASE isa_mem_base +#define PCI_DRAM_OFFSET pci_dram_offset +#endif + +extern unsigned long isa_io_base; +extern unsigned long pci_io_base; +extern unsigned long pci_dram_offset; + +extern resource_size_t isa_mem_base; #define IO_SPACE_LIMIT (0xFFFFFFFF) diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h index cc3a4dfc3eaa..1c47f6f8bfb6 100644 --- a/arch/microblaze/include/asm/pgtable.h +++ b/arch/microblaze/include/asm/pgtable.h @@ -89,6 +89,21 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; } #endif /* __ASSEMBLY__ */ +/* + * Macro to mark a page protection value as "uncacheable". + */ + +#define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \ + _PAGE_WRITETHRU) + +#define pgprot_noncached(prot) \ + (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ + _PAGE_NO_CACHE | _PAGE_GUARDED)) + +#define pgprot_noncached_wc(prot) \ + (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ + _PAGE_NO_CACHE)) + /* * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash * table containing PTEs, together with a set of 16 segment registers, to diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h index 03f45a963204..e7d67a329bd7 100644 --- a/arch/microblaze/include/asm/prom.h +++ b/arch/microblaze/include/asm/prom.h @@ -31,6 +31,21 @@ /* Other Prototypes */ extern int early_uartlite_console(void); +#ifdef CONFIG_PCI +/* + * PCI <-> OF matching functions + * (XXX should these be here?) + */ +struct pci_bus; +struct pci_dev; +extern int pci_device_from_OF_node(struct device_node *node, + u8 *bus, u8 *devfn); +extern struct device_node *pci_busdev_to_OF_node(struct pci_bus *bus, + int devfn); +extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev); +extern void pci_create_OF_bus_map(void); +#endif + /* * OF address retreival & translation */ diff --git a/arch/microblaze/pci/Makefile b/arch/microblaze/pci/Makefile new file mode 100644 index 000000000000..2b8901864b23 --- /dev/null +++ b/arch/microblaze/pci/Makefile @@ -0,0 +1,5 @@ +# +# Makefile +# + +obj-$(CONFIG_PCI) += pci_32.o pci-common.o indirect_pci.o iomap.o diff --git a/arch/microblaze/pci/indirect_pci.c b/arch/microblaze/pci/indirect_pci.c new file mode 100644 index 000000000000..25f18f017f21 --- /dev/null +++ b/arch/microblaze/pci/indirect_pci.c @@ -0,0 +1,163 @@ +/* + * Support for indirect PCI bridges. + * + * Copyright (C) 1998 Gabriel Paubert. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +static int +indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, + int len, u32 *val) +{ + struct pci_controller *hose = pci_bus_to_host(bus); + volatile void __iomem *cfg_data; + u8 cfg_type = 0; + u32 bus_no, reg; + + if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) { + if (bus->number != hose->first_busno) + return PCIBIOS_DEVICE_NOT_FOUND; + if (devfn != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + } + + if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE) + if (bus->number != hose->first_busno) + cfg_type = 1; + + bus_no = (bus->number == hose->first_busno) ? + hose->self_busno : bus->number; + + if (hose->indirect_type & INDIRECT_TYPE_EXT_REG) + reg = ((offset & 0xf00) << 16) | (offset & 0xfc); + else + reg = offset & 0xfc; /* Only 3 bits for function */ + + if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN) + out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | + (devfn << 8) | reg | cfg_type)); + else + out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | + (devfn << 8) | reg | cfg_type)); + + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + cfg_data = hose->cfg_data + (offset & 3); /* Only 3 bits for function */ + switch (len) { + case 1: + *val = in_8(cfg_data); + break; + case 2: + *val = in_le16(cfg_data); + break; + default: + *val = in_le32(cfg_data); + break; + } + return PCIBIOS_SUCCESSFUL; +} + +static int +indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, + int len, u32 val) +{ + struct pci_controller *hose = pci_bus_to_host(bus); + volatile void __iomem *cfg_data; + u8 cfg_type = 0; + u32 bus_no, reg; + + if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) { + if (bus->number != hose->first_busno) + return PCIBIOS_DEVICE_NOT_FOUND; + if (devfn != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + } + + if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE) + if (bus->number != hose->first_busno) + cfg_type = 1; + + bus_no = (bus->number == hose->first_busno) ? + hose->self_busno : bus->number; + + if (hose->indirect_type & INDIRECT_TYPE_EXT_REG) + reg = ((offset & 0xf00) << 16) | (offset & 0xfc); + else + reg = offset & 0xfc; + + if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN) + out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | + (devfn << 8) | reg | cfg_type)); + else + out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | + (devfn << 8) | reg | cfg_type)); + + /* surpress setting of PCI_PRIMARY_BUS */ + if (hose->indirect_type & INDIRECT_TYPE_SURPRESS_PRIMARY_BUS) + if ((offset == PCI_PRIMARY_BUS) && + (bus->number == hose->first_busno)) + val &= 0xffffff00; + + /* Workaround for PCI_28 Errata in 440EPx/GRx */ + if ((hose->indirect_type & INDIRECT_TYPE_BROKEN_MRM) && + offset == PCI_CACHE_LINE_SIZE) { + val = 0; + } + + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + cfg_data = hose->cfg_data + (offset & 3); + switch (len) { + case 1: + out_8(cfg_data, val); + break; + case 2: + out_le16(cfg_data, val); + break; + default: + out_le32(cfg_data, val); + break; + } + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops indirect_pci_ops = { + .read = indirect_read_config, + .write = indirect_write_config, +}; + +void __init +setup_indirect_pci(struct pci_controller *hose, + resource_size_t cfg_addr, + resource_size_t cfg_data, u32 flags) +{ + resource_size_t base = cfg_addr & PAGE_MASK; + void __iomem *mbase; + + mbase = ioremap(base, PAGE_SIZE); + hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK); + if ((cfg_data & PAGE_MASK) != base) + mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE); + hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK); + hose->ops = &indirect_pci_ops; + hose->indirect_type = flags; +} diff --git a/arch/microblaze/pci/iomap.c b/arch/microblaze/pci/iomap.c new file mode 100644 index 000000000000..3fbf16f4e16c --- /dev/null +++ b/arch/microblaze/pci/iomap.c @@ -0,0 +1,39 @@ +/* + * ppc64 "iomap" interface implementation. + * + * (C) Copyright 2004 Linus Torvalds + */ +#include +#include +#include +#include +#include + +void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max) +{ + resource_size_t start = pci_resource_start(dev, bar); + resource_size_t len = pci_resource_len(dev, bar); + unsigned long flags = pci_resource_flags(dev, bar); + + if (!len) + return NULL; + if (max && len > max) + len = max; + if (flags & IORESOURCE_IO) + return ioport_map(start, len); + if (flags & IORESOURCE_MEM) + return ioremap(start, len); + /* What? */ + return NULL; +} +EXPORT_SYMBOL(pci_iomap); + +void pci_iounmap(struct pci_dev *dev, void __iomem *addr) +{ + if (isa_vaddr_is_ioport(addr)) + return; + if (pcibios_vaddr_is_ioport(addr)) + return; + iounmap(addr); +} +EXPORT_SYMBOL(pci_iounmap); diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 3d102dd87c9f..0b51857fbaf7 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_PPC) += setup-bus.o obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o obj-$(CONFIG_X86_VISWS) += setup-irq.o obj-$(CONFIG_MN10300) += setup-bus.o +obj-$(CONFIG_MICROBLAZE) += setup-bus.o # # ACPI Related PCI FW Functions -- cgit v1.2.3 From f0dc117abdfa9a0e96c3d013d836460ef3cd08c7 Mon Sep 17 00:00:00 2001 From: Eli Cohen Date: Wed, 3 Mar 2010 12:27:52 +0000 Subject: IPoIB: Fix TX queue lockup with mixed UD/CM traffic The IPoIB UD QP reports send completions to priv->send_cq, which is usually left unarmed; it only gets armed when the number of outstanding send requests reaches the size of the TX queue. This arming is done only in the send path for the UD QP. However, when sending CM packets, the net queue may be stopped for the same reasons but no measures are taken to recover the UD path from a lockup. Consider this scenario: a host sends high rate of both CM and UD packets, with a TX queue length of N. If at some time the number of outstanding UD packets is more than N/2 and the overall outstanding packets is N-1, and CM sends a packet (making the number of outstanding sends equal N), the TX queue will be stopped. When all the CM packets complete, the number of outstanding packets will still be higher than N/2 so the TX queue will not be restarted. Fix this by calling ib_req_notify_cq() when the queue is stopped in the CM path. Signed-off-by: Eli Cohen Signed-off-by: Roland Dreier --- drivers/infiniband/ulp/ipoib/ipoib_cm.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/infiniband/ulp/ipoib/ipoib_cm.c b/drivers/infiniband/ulp/ipoib/ipoib_cm.c index 83a7751c38d6..6e3cc865e369 100644 --- a/drivers/infiniband/ulp/ipoib/ipoib_cm.c +++ b/drivers/infiniband/ulp/ipoib/ipoib_cm.c @@ -752,6 +752,8 @@ void ipoib_cm_send(struct net_device *dev, struct sk_buff *skb, struct ipoib_cm_ if (++priv->tx_outstanding == ipoib_sendq_size) { ipoib_dbg(priv, "TX ring 0x%x full, stopping kernel net queue\n", tx->qp->qp_num); + if (ib_req_notify_cq(priv->send_cq, IB_CQ_NEXT_COMP)) + ipoib_warn(priv, "request notify on send CQ failed\n"); netif_stop_queue(dev); } } -- cgit v1.2.3 From a48f509b26cec53338f4b0abd52ecea35e3974b8 Mon Sep 17 00:00:00 2001 From: Or Gerlitz Date: Thu, 4 Mar 2010 13:17:37 +0000 Subject: IPoIB: Include return code in trace message for ib_post_send() failures Print the return code of ib_post_send() if it fails to make these debugging messages more useful. Signed-off-by: Or Gerlitz Signed-off-by: Roland Dreier --- drivers/infiniband/ulp/ipoib/ipoib_cm.c | 8 +++++--- drivers/infiniband/ulp/ipoib/ipoib_ib.c | 9 +++++---- 2 files changed, 10 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/infiniband/ulp/ipoib/ipoib_cm.c b/drivers/infiniband/ulp/ipoib/ipoib_cm.c index 6e3cc865e369..bc658373ad55 100644 --- a/drivers/infiniband/ulp/ipoib/ipoib_cm.c +++ b/drivers/infiniband/ulp/ipoib/ipoib_cm.c @@ -708,6 +708,7 @@ void ipoib_cm_send(struct net_device *dev, struct sk_buff *skb, struct ipoib_cm_ struct ipoib_dev_priv *priv = netdev_priv(dev); struct ipoib_cm_tx_buf *tx_req; u64 addr; + int rc; if (unlikely(skb->len > tx->mtu)) { ipoib_warn(priv, "packet len %d (> %d) too long to send, dropping\n", @@ -739,9 +740,10 @@ void ipoib_cm_send(struct net_device *dev, struct sk_buff *skb, struct ipoib_cm_ tx_req->mapping = addr; - if (unlikely(post_send(priv, tx, tx->tx_head & (ipoib_sendq_size - 1), - addr, skb->len))) { - ipoib_warn(priv, "post_send failed\n"); + rc = post_send(priv, tx, tx->tx_head & (ipoib_sendq_size - 1), + addr, skb->len); + if (unlikely(rc)) { + ipoib_warn(priv, "post_send failed, error %d\n", rc); ++dev->stats.tx_errors; ib_dma_unmap_single(priv->ca, addr, skb->len, DMA_TO_DEVICE); dev_kfree_skb_any(skb); diff --git a/drivers/infiniband/ulp/ipoib/ipoib_ib.c b/drivers/infiniband/ulp/ipoib/ipoib_ib.c index 8c91d9f37ada..5df40b128f81 100644 --- a/drivers/infiniband/ulp/ipoib/ipoib_ib.c +++ b/drivers/infiniband/ulp/ipoib/ipoib_ib.c @@ -529,7 +529,7 @@ void ipoib_send(struct net_device *dev, struct sk_buff *skb, { struct ipoib_dev_priv *priv = netdev_priv(dev); struct ipoib_tx_buf *tx_req; - int hlen; + int hlen, rc; void *phead; if (skb_is_gso(skb)) { @@ -585,9 +585,10 @@ void ipoib_send(struct net_device *dev, struct sk_buff *skb, netif_stop_queue(dev); } - if (unlikely(post_send(priv, priv->tx_head & (ipoib_sendq_size - 1), - address->ah, qpn, tx_req, phead, hlen))) { - ipoib_warn(priv, "post_send failed\n"); + rc = post_send(priv, priv->tx_head & (ipoib_sendq_size - 1), + address->ah, qpn, tx_req, phead, hlen); + if (unlikely(rc)) { + ipoib_warn(priv, "post_send failed, error %d\n", rc); ++dev->stats.tx_errors; --priv->tx_outstanding; ipoib_dma_unmap_tx(priv->ca, tx_req); -- cgit v1.2.3 From 070e140c4c536df33a9870318791b2ca8f7dbfcf Mon Sep 17 00:00:00 2001 From: Steve Wise Date: Thu, 4 Mar 2010 18:18:18 +0000 Subject: IB/mad: Ignore iWARP devices on device removal When an iWARP device is unloaded, the ib_mad module logs errors. It should be ignoring iWARP devices on device removal just like it does on device add. Signed-off-by: Steve Wise Acked-by: Sean Hefty Signed-off-by: Roland Dreier --- drivers/infiniband/core/mad.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/infiniband/core/mad.c b/drivers/infiniband/core/mad.c index 58463da814d1..e351b1548535 100644 --- a/drivers/infiniband/core/mad.c +++ b/drivers/infiniband/core/mad.c @@ -2953,6 +2953,9 @@ static void ib_mad_remove_device(struct ib_device *device) { int i, num_ports, cur_port; + if (rdma_node_get_transport(device->node_type) != RDMA_TRANSPORT_IB) + return; + if (device->node_type == RDMA_NODE_IB_SWITCH) { num_ports = 1; cur_port = 0; -- cgit v1.2.3 From 69960a275efc9d82797bbbe2460a2d6c9cace314 Mon Sep 17 00:00:00 2001 From: Steve Wise Date: Wed, 3 Mar 2010 15:06:34 +0000 Subject: RDMA/cxgb3: Wait at least one schedule cycle during device removal During a hot-plug LLD removal event or an EEH error event, iw_cxgb3 must ensure that any/all threads that might be in a cxgb3 exported function must return from the function before iw_cxgb3 returns from its event processing. Do this by calling synchronize_net(). Signed-off-by: Steve Wise Signed-off-by: Roland Dreier --- drivers/infiniband/hw/cxgb3/iwch.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/infiniband/hw/cxgb3/iwch.c b/drivers/infiniband/hw/cxgb3/iwch.c index ee1d8b4d4541..63f975f3e30f 100644 --- a/drivers/infiniband/hw/cxgb3/iwch.c +++ b/drivers/infiniband/hw/cxgb3/iwch.c @@ -189,6 +189,7 @@ static void close_rnic_dev(struct t3cdev *tdev) list_for_each_entry_safe(dev, tmp, &dev_list, entry) { if (dev->rdev.t3cdev_p == tdev) { dev->rdev.flags = CXIO_ERROR_FATAL; + synchronize_net(); cancel_delayed_work_sync(&dev->db_drop_task); list_del(&dev->entry); iwch_unregister_device(dev); @@ -217,6 +218,7 @@ static void iwch_event_handler(struct t3cdev *tdev, u32 evt, u32 port_id) switch (evt) { case OFFLOAD_STATUS_DOWN: { rdev->flags = CXIO_ERROR_FATAL; + synchronize_net(); event.event = IB_EVENT_DEVICE_FATAL; dispatch = 1; break; -- cgit v1.2.3 From 883c699241f48667ff59277d8c20790868fd4829 Mon Sep 17 00:00:00 2001 From: Faisal Latif Date: Tue, 2 Mar 2010 17:22:51 -0600 Subject: RDMA/nes: Set assume_aligned_header bit Set assume_aligned_header bit in QP context as requested by hardware group. Signed-off-by: Faisal Latif Signed-off-by: Roland Dreier --- drivers/infiniband/hw/nes/nes_verbs.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/infiniband/hw/nes/nes_verbs.c b/drivers/infiniband/hw/nes/nes_verbs.c index 815725f886c4..69928296d74b 100644 --- a/drivers/infiniband/hw/nes/nes_verbs.c +++ b/drivers/infiniband/hw/nes/nes_verbs.c @@ -1323,6 +1323,7 @@ static struct ib_qp *nes_create_qp(struct ib_pd *ibpd, nesqp->nesqp_context->aeq_token_low = cpu_to_le32((u32)((unsigned long)(nesqp))); nesqp->nesqp_context->aeq_token_high = cpu_to_le32((u32)(upper_32_bits((unsigned long)(nesqp)))); nesqp->nesqp_context->ird_ord_sizes = cpu_to_le32(NES_QPCONTEXT_ORDIRD_ALSMM | + NES_QPCONTEXT_ORDIRD_AAH | ((((u32)nesadapter->max_irrq_wr) << NES_QPCONTEXT_ORDIRD_IRDSIZE_SHIFT) & NES_QPCONTEXT_ORDIRD_IRDSIZE_MASK)); if (disable_mpa_crc) { -- cgit v1.2.3 From 9f29006ae8c85746e5a52d557f689359149a0793 Mon Sep 17 00:00:00 2001 From: Chien Tung Date: Wed, 3 Mar 2010 19:13:28 +0000 Subject: RDMA/nes: Clear stall bit before destroying NIC QP Clear the stall bit to drop any incoming packets while destroying NIC QP. This will prevent a chip resource leak. Signed-off-by: Chien Tung Signed-off-by: Roland Dreier --- drivers/infiniband/hw/nes/nes_hw.c | 8 ++++++++ drivers/infiniband/hw/nes/nes_hw.h | 1 + 2 files changed, 9 insertions(+) (limited to 'drivers') diff --git a/drivers/infiniband/hw/nes/nes_hw.c b/drivers/infiniband/hw/nes/nes_hw.c index ce7f53833577..925075557dc2 100644 --- a/drivers/infiniband/hw/nes/nes_hw.c +++ b/drivers/infiniband/hw/nes/nes_hw.c @@ -1899,9 +1899,14 @@ void nes_destroy_nic_qp(struct nes_vnic *nesvnic) u16 wqe_fragment_index; u64 wqe_frag; u32 cqp_head; + u32 wqm_cfg0; unsigned long flags; int ret; + /* clear wqe stall before destroying NIC QP */ + wqm_cfg0 = nes_read_indexed(nesdev, NES_IDX_WQM_CONFIG0); + nes_write_indexed(nesdev, NES_IDX_WQM_CONFIG0, wqm_cfg0 & 0xFFFF7FFF); + /* Free remaining NIC receive buffers */ while (nesvnic->nic.rq_head != nesvnic->nic.rq_tail) { nic_rqe = &nesvnic->nic.rq_vbase[nesvnic->nic.rq_tail]; @@ -2020,6 +2025,9 @@ void nes_destroy_nic_qp(struct nes_vnic *nesvnic) pci_free_consistent(nesdev->pcidev, nesvnic->nic_mem_size, nesvnic->nic_vbase, nesvnic->nic_pbase); + + /* restore old wqm_cfg0 value */ + nes_write_indexed(nesdev, NES_IDX_WQM_CONFIG0, wqm_cfg0); } /** diff --git a/drivers/infiniband/hw/nes/nes_hw.h b/drivers/infiniband/hw/nes/nes_hw.h index 9b1e7f869d83..bbbfe9fc5a5a 100644 --- a/drivers/infiniband/hw/nes/nes_hw.h +++ b/drivers/infiniband/hw/nes/nes_hw.h @@ -160,6 +160,7 @@ enum indexed_regs { NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI = 0x7004, NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO = 0x7008, NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI = 0x700c, + NES_IDX_WQM_CONFIG0 = 0x5000, NES_IDX_WQM_CONFIG1 = 0x5004, NES_IDX_CM_CONFIG = 0x5100, NES_IDX_NIC_LOGPORT_TO_PHYPORT = 0x6000, -- cgit v1.2.3 From a5300dcbbd5d455a1a5978095b8f78af66c540a6 Mon Sep 17 00:00:00 2001 From: Samuel Ortiz Date: Mon, 8 Mar 2010 20:07:48 +0100 Subject: mfd: Fix sm501 requested region size We should only request for the MFD used region, not the whole thing. Signed-off-by: Samuel Ortiz Tested-by: Paul Mundt Reviewed-by: H Hartley Sweeten --- drivers/mfd/sm501.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c index dc9ea95c0561..497712fd13ed 100644 --- a/drivers/mfd/sm501.c +++ b/drivers/mfd/sm501.c @@ -1430,7 +1430,7 @@ static int __devinit sm501_plat_probe(struct platform_device *dev) } sm->regs_claim = request_mem_region(sm->io_res->start, - resource_size(sm->io_res), "sm501"); + 0x100, "sm501"); if (sm->regs_claim == NULL) { dev_err(&dev->dev, "cannot claim registers\n"); @@ -1644,7 +1644,7 @@ static int __devinit sm501_pci_probe(struct pci_dev *dev, sm->mem_res = &dev->resource[0]; sm->regs_claim = request_mem_region(sm->io_res->start, - resource_size(sm->io_res), "sm501"); + 0x100, "sm501"); if (sm->regs_claim == NULL) { dev_err(&dev->dev, "cannot claim registers\n"); err= -EBUSY; -- cgit v1.2.3 From 8d002bdc9f1f9a1220c0d87a7321f0233ace97cd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 15 Dec 2009 21:49:57 +0100 Subject: mfd: Several MFD drivers should depend on GENERIC_HARDIRQS commit 5fb4d38b19d95a5f980f0a10adba798f5b92128c ("mfd: Move WM831x to generic IRQ") didn't take into account that genirq support depends on GENERIC_HARDIRQS. Additionally, 2.6.34-rc1 added: - commit 2afa62ea76027b00e472ddb672191e6e15425b43 ("mfd: Use genirq in 88pm860x"). - commit 760e4518788df6762700e6bb9dd8692379f11168 ("mfd: Convert WM8350 to genirq"). - commit 1f1cf8f98cf6588365efeaab8e7e7758aaa77f6e ("mfd: Update irq handler in max8925") Make all of them depend on GENERIC_HARDIRQS to avoid compile errors on architectures that don't support genirq yet. Signed-off-by: Geert Uytterhoeven Acked-by: Mark Brown Signed-off-by: Samuel Ortiz --- drivers/mfd/Kconfig | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 951fa9b93fbe..2a5a0b78f84e 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -11,7 +11,7 @@ config MFD_CORE config MFD_88PM860X bool "Support Marvell 88PM8606/88PM8607" - depends on I2C=y + depends on I2C=y && GENERIC_HARDIRQS select MFD_CORE help This supports for Marvell 88PM8606/88PM8607 Power Management IC. @@ -205,7 +205,7 @@ config PMIC_ADP5520 config MFD_MAX8925 bool "Maxim Semiconductor MAX8925 PMIC Support" - depends on I2C=y + depends on I2C=y && GENERIC_HARDIRQS select MFD_CORE help Say yes here to support for Maxim Semiconductor MAX8925. This is @@ -226,7 +226,7 @@ config MFD_WM8400 config MFD_WM831X bool "Support Wolfson Microelectronics WM831x/2x PMICs" select MFD_CORE - depends on I2C=y + depends on I2C=y && GENERIC_HARDIRQS help Support for the Wolfson Microelecronics WM831x and WM832x PMICs. This driver provides common support for accessing the device, @@ -235,6 +235,7 @@ config MFD_WM831X config MFD_WM8350 bool + depends on GENERIC_HARDIRQS config MFD_WM8350_CONFIG_MODE_0 bool @@ -287,7 +288,7 @@ config MFD_WM8352_CONFIG_MODE_3 config MFD_WM8350_I2C bool "Support Wolfson Microelectronics WM8350 with I2C" select MFD_WM8350 - depends on I2C=y + depends on I2C=y && GENERIC_HARDIRQS help The WM8350 is an integrated audio and power management subsystem with watchdog and RTC functionality for embedded -- cgit v1.2.3 From a72042c08a8ba3b685dc9cba62c57c48188ef2c8 Mon Sep 17 00:00:00 2001 From: Chien Tung Date: Wed, 3 Mar 2010 19:13:26 +0000 Subject: RDMA/nes: Fix CX4 link problem in back-to-back configuration Commit 09124e19 ("RDMA/nes: Add support for KR device id 0x0110") took out too much code and broke CX4 link detection in back-to-back configuration. Put back the code that does the link check. Signed-off-by: Chien Tung Signed-off-by: Roland Dreier --- drivers/infiniband/hw/nes/nes_nic.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/infiniband/hw/nes/nes_nic.c b/drivers/infiniband/hw/nes/nes_nic.c index a1d79b6856ac..91fdde382e82 100644 --- a/drivers/infiniband/hw/nes/nes_nic.c +++ b/drivers/infiniband/hw/nes/nes_nic.c @@ -1595,7 +1595,6 @@ struct net_device *nes_netdev_init(struct nes_device *nesdev, struct nes_vnic *nesvnic; struct net_device *netdev; struct nic_qp_map *curr_qp_map; - u32 u32temp; u8 phy_type = nesdev->nesadapter->phy_type[nesdev->mac_index]; netdev = alloc_etherdev(sizeof(struct nes_vnic)); @@ -1707,6 +1706,10 @@ struct net_device *nes_netdev_init(struct nes_device *nesdev, ((phy_type == NES_PHY_TYPE_PUMA_1G) && (((PCI_FUNC(nesdev->pcidev->devfn) == 1) && (nesdev->mac_index == 2)) || ((PCI_FUNC(nesdev->pcidev->devfn) == 2) && (nesdev->mac_index == 1)))))) { + u32 u32temp; + u32 link_mask; + u32 link_val; + u32temp = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + (0x200 * (nesdev->mac_index & 1))); if (phy_type != NES_PHY_TYPE_PUMA_1G) { @@ -1715,13 +1718,36 @@ struct net_device *nes_netdev_init(struct nes_device *nesdev, (0x200 * (nesdev->mac_index & 1)), u32temp); } + /* Check and set linkup here. This is for back to back */ + /* configuration where second port won't get link interrupt */ + switch (phy_type) { + case NES_PHY_TYPE_PUMA_1G: + if (nesdev->mac_index < 2) { + link_mask = 0x01010000; + link_val = 0x01010000; + } else { + link_mask = 0x02020000; + link_val = 0x02020000; + } + break; + default: + link_mask = 0x0f1f0000; + link_val = 0x0f0f0000; + break; + } + + u32temp = nes_read_indexed(nesdev, + NES_IDX_PHY_PCS_CONTROL_STATUS0 + + (0x200 * (nesdev->mac_index & 1))); + if ((u32temp & link_mask) == link_val) + nesvnic->linkup = 1; + /* clear the MAC interrupt status, assumes direct logical to physical mapping */ u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (0x200 * nesdev->mac_index)); nes_debug(NES_DBG_INIT, "Phy interrupt status = 0x%X.\n", u32temp); nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (0x200 * nesdev->mac_index), u32temp); nes_init_phy(nesdev); - } return netdev; -- cgit v1.2.3 From d0ab4a4d5094e5d17b103dc5073529a04f00a469 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 10 Mar 2010 15:20:35 -0800 Subject: rtc/hctosys: only claim the RTC provided the system time if it did MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Without this patch /sys/class/rtc/$CONFIG_RTC_HCTOSYS_DEVICE/hctosys contains a 1 (meaning "This rtc was used to initialize the system clock") even if reading the time at bootup failed. Moreover change error handling in rtc_hctosys() to use goto and so reduce the indention level. Signed-off-by: Uwe Kleine-König Cc: Paul Gortmaker Acked-by: Alessandro Zummo Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/rtc/hctosys.c | 59 ++++++++++++++++++++++++++++--------------------- drivers/rtc/rtc-sysfs.c | 5 +++-- include/linux/rtc.h | 6 +++++ 3 files changed, 43 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/hctosys.c b/drivers/rtc/hctosys.c index 33c0e98243ee..bc90b091f195 100644 --- a/drivers/rtc/hctosys.c +++ b/drivers/rtc/hctosys.c @@ -22,48 +22,57 @@ * the best guess is to add 0.5s. */ +int rtc_hctosys_ret = -ENODEV; + static int __init rtc_hctosys(void) { - int err; + int err = -ENODEV; struct rtc_time tm; + struct timespec tv = { + .tv_nsec = NSEC_PER_SEC >> 1, + }; struct rtc_device *rtc = rtc_class_open(CONFIG_RTC_HCTOSYS_DEVICE); if (rtc == NULL) { - printk("%s: unable to open rtc device (%s)\n", + pr_err("%s: unable to open rtc device (%s)\n", __FILE__, CONFIG_RTC_HCTOSYS_DEVICE); - return -ENODEV; + goto err_open; } err = rtc_read_time(rtc, &tm); - if (err == 0) { - err = rtc_valid_tm(&tm); - if (err == 0) { - struct timespec tv; + if (err) { + dev_err(rtc->dev.parent, + "hctosys: unable to read the hardware clock\n"); + goto err_read; - tv.tv_nsec = NSEC_PER_SEC >> 1; + } - rtc_tm_to_time(&tm, &tv.tv_sec); + err = rtc_valid_tm(&tm); + if (err) { + dev_err(rtc->dev.parent, + "hctosys: invalid date/time\n"); + goto err_invalid; + } - do_settimeofday(&tv); + rtc_tm_to_time(&tm, &tv.tv_sec); - dev_info(rtc->dev.parent, - "setting system clock to " - "%d-%02d-%02d %02d:%02d:%02d UTC (%u)\n", - tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday, - tm.tm_hour, tm.tm_min, tm.tm_sec, - (unsigned int) tv.tv_sec); - } - else - dev_err(rtc->dev.parent, - "hctosys: invalid date/time\n"); - } - else - dev_err(rtc->dev.parent, - "hctosys: unable to read the hardware clock\n"); + do_settimeofday(&tv); + dev_info(rtc->dev.parent, + "setting system clock to " + "%d-%02d-%02d %02d:%02d:%02d UTC (%u)\n", + tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday, + tm.tm_hour, tm.tm_min, tm.tm_sec, + (unsigned int) tv.tv_sec); + +err_invalid: +err_read: rtc_class_close(rtc); - return 0; +err_open: + rtc_hctosys_ret = err; + + return err; } late_initcall(rtc_hctosys); diff --git a/drivers/rtc/rtc-sysfs.c b/drivers/rtc/rtc-sysfs.c index 7dd23a6fc825..380083ca572f 100644 --- a/drivers/rtc/rtc-sysfs.c +++ b/drivers/rtc/rtc-sysfs.c @@ -107,8 +107,9 @@ rtc_sysfs_show_hctosys(struct device *dev, struct device_attribute *attr, char *buf) { #ifdef CONFIG_RTC_HCTOSYS_DEVICE - if (strcmp(dev_name(&to_rtc_device(dev)->dev), - CONFIG_RTC_HCTOSYS_DEVICE) == 0) + if (rtc_hctosys_ret == 0 && + strcmp(dev_name(&to_rtc_device(dev)->dev), + CONFIG_RTC_HCTOSYS_DEVICE) == 0) return sprintf(buf, "1\n"); else #endif diff --git a/include/linux/rtc.h b/include/linux/rtc.h index 60f88a7fb13d..14dbc83ded20 100644 --- a/include/linux/rtc.h +++ b/include/linux/rtc.h @@ -238,6 +238,12 @@ static inline bool is_leap_year(unsigned int year) return (!(year % 4) && (year % 100)) || !(year % 400); } +#ifdef CONFIG_RTC_HCTOSYS +extern int rtc_hctosys_ret; +#else +#define rtc_hctosys_ret -ENODEV +#endif + #endif /* __KERNEL__ */ #endif /* _LINUX_RTC_H_ */ -- cgit v1.2.3 From 516a82422209e078345d0ca54b16793d7bfd4782 Mon Sep 17 00:00:00 2001 From: Albert Herranz Date: Wed, 10 Mar 2010 15:20:37 -0800 Subject: sdio: recognize io card without powercycle SDIO Simplified Specification V2.00 states that it is strongly recommended that the host executes either a power reset or issues a CMD52 (I/O Reset) to re-initialize an I/O only card or the I/O portion of a combo card. Additionally, the CMD52 must be issued first because it cannot be issued after a CMD0. With this patch the Nintendo Wii SDIO-based WLAN card is detected after a system reset, without requiring a complete system powercycle. Signed-off-by: Albert Herranz Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/mmc/core/core.c | 1 + drivers/mmc/core/sdio_ops.c | 36 ++++++++++++++++++++++++++++++------ drivers/mmc/core/sdio_ops.h | 1 + 3 files changed, 32 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index f4b97d3c3d0f..3168ebd616b2 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -1089,6 +1089,7 @@ void mmc_rescan(struct work_struct *work) mmc_claim_host(host); mmc_power_up(host); + sdio_reset(host); mmc_go_idle(host); mmc_send_if_cond(host, host->ocr_avail); diff --git a/drivers/mmc/core/sdio_ops.c b/drivers/mmc/core/sdio_ops.c index 4eb7825fd1a7..dea36d9c22e6 100644 --- a/drivers/mmc/core/sdio_ops.c +++ b/drivers/mmc/core/sdio_ops.c @@ -67,13 +67,13 @@ int mmc_send_io_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr) return err; } -int mmc_io_rw_direct(struct mmc_card *card, int write, unsigned fn, - unsigned addr, u8 in, u8* out) +static int mmc_io_rw_direct_host(struct mmc_host *host, int write, unsigned fn, + unsigned addr, u8 in, u8 *out) { struct mmc_command cmd; int err; - BUG_ON(!card); + BUG_ON(!host); BUG_ON(fn > 7); /* sanity check */ @@ -90,11 +90,11 @@ int mmc_io_rw_direct(struct mmc_card *card, int write, unsigned fn, cmd.arg |= in; cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; - err = mmc_wait_for_cmd(card->host, &cmd, 0); + err = mmc_wait_for_cmd(host, &cmd, 0); if (err) return err; - if (mmc_host_is_spi(card->host)) { + if (mmc_host_is_spi(host)) { /* host driver already reported errors */ } else { if (cmd.resp[0] & R5_ERROR) @@ -106,7 +106,7 @@ int mmc_io_rw_direct(struct mmc_card *card, int write, unsigned fn, } if (out) { - if (mmc_host_is_spi(card->host)) + if (mmc_host_is_spi(host)) *out = (cmd.resp[0] >> 8) & 0xFF; else *out = cmd.resp[0] & 0xFF; @@ -115,6 +115,13 @@ int mmc_io_rw_direct(struct mmc_card *card, int write, unsigned fn, return 0; } +int mmc_io_rw_direct(struct mmc_card *card, int write, unsigned fn, + unsigned addr, u8 in, u8 *out) +{ + BUG_ON(!card); + return mmc_io_rw_direct_host(card->host, write, fn, addr, in, out); +} + int mmc_io_rw_extended(struct mmc_card *card, int write, unsigned fn, unsigned addr, int incr_addr, u8 *buf, unsigned blocks, unsigned blksz) { @@ -182,3 +189,20 @@ int mmc_io_rw_extended(struct mmc_card *card, int write, unsigned fn, return 0; } +int sdio_reset(struct mmc_host *host) +{ + int ret; + u8 abort; + + /* SDIO Simplified Specification V2.0, 4.4 Reset for SDIO */ + + ret = mmc_io_rw_direct_host(host, 0, 0, SDIO_CCCR_ABORT, 0, &abort); + if (ret) + abort = 0x08; + else + abort |= 0x08; + + ret = mmc_io_rw_direct_host(host, 1, 0, SDIO_CCCR_ABORT, abort, NULL); + return ret; +} + diff --git a/drivers/mmc/core/sdio_ops.h b/drivers/mmc/core/sdio_ops.h index e2e74b0d17d8..12a4d3ab174c 100644 --- a/drivers/mmc/core/sdio_ops.h +++ b/drivers/mmc/core/sdio_ops.h @@ -17,6 +17,7 @@ int mmc_io_rw_direct(struct mmc_card *card, int write, unsigned fn, unsigned addr, u8 in, u8* out); int mmc_io_rw_extended(struct mmc_card *card, int write, unsigned fn, unsigned addr, int incr_addr, u8 *buf, unsigned blocks, unsigned blksz); +int sdio_reset(struct mmc_host *host); #endif -- cgit v1.2.3 From 9b3a6549b2602ca30f58715a0071e29f9898cae9 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Wed, 10 Mar 2010 15:20:42 -0800 Subject: drivers/scsi/ses.c: eliminate double free The few lines below the kfree of hdr_buf may go to the label err_free which will also free hdr_buf. The most straightforward solution seems to be to just move the kfree of hdr_buf after these gotos. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // @r@ identifier E; expression E1; iterator I; statement S; @@ *kfree(E); ... when != E = E1 when != I(E,...) S when != &E *kfree(E); // Signed-off-by: Julia Lawall Cc: James Bottomley Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/scsi/ses.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/ses.c b/drivers/scsi/ses.c index 1d7a8780e00c..0d9d6f7567f5 100644 --- a/drivers/scsi/ses.c +++ b/drivers/scsi/ses.c @@ -595,8 +595,6 @@ static int ses_intf_add(struct device *cdev, ses_dev->page10_len = len; buf = NULL; } - kfree(hdr_buf); - scomp = kzalloc(sizeof(struct ses_component) * components, GFP_KERNEL); if (!scomp) goto err_free; @@ -608,6 +606,8 @@ static int ses_intf_add(struct device *cdev, goto err_free; } + kfree(hdr_buf); + edev->scratch = ses_dev; for (i = 0; i < components; i++) edev->component[i].scratch = scomp + i; -- cgit v1.2.3 From d49375434ec011dabcc8bfa5091f5327284e42ce Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:44 -0800 Subject: drivers/block/floppy.c: convert some #include Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index b9b117059b62..65e2443b207a 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -180,6 +180,8 @@ static int print_unex = 1; #include #include /* for invalidate_buffers() */ #include +#include +#include /* * PS/2 floppies have much slower step rates than regular floppies. @@ -191,8 +193,6 @@ static int slow_floppy; #include #include #include -#include -#include static int FLOPPY_IRQ = 6; static int FLOPPY_DMA = 2; -- cgit v1.2.3 From 48c8cee61f22fe5a2ea00488222b3415378469ad Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:45 -0800 Subject: drivers/block/floppy.c: #define space and column neatening Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 180 ++++++++++++++++++++++++++----------------------- 1 file changed, 97 insertions(+), 83 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 65e2443b207a..652668d76a8a 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -150,7 +150,7 @@ #define REALLY_SLOW_IO #define DEBUGT 2 -#define DCL_DEBUG /* debug disk change line */ +#define DCL_DEBUG /* debug disk change line */ /* do print messages for unexpected interrupts */ static int print_unex = 1; @@ -250,7 +250,7 @@ static int irqdma_allocated; static struct request *current_req; static struct request_queue *floppy_queue; -static void do_fd_request(struct request_queue * q); +static void do_fd_request(struct request_queue *q); #ifndef fd_get_dma_residue #define fd_get_dma_residue() get_dma_residue(FLOPPY_DMA) @@ -263,7 +263,7 @@ static void do_fd_request(struct request_queue * q); #endif #ifndef fd_dma_mem_alloc -#define fd_dma_mem_alloc(size) __get_dma_pages(GFP_KERNEL,get_order(size)) +#define fd_dma_mem_alloc(size) __get_dma_pages(GFP_KERNEL, get_order(size)) #endif static inline void fallback_on_nodma_alloc(char **addr, size_t l) @@ -285,57 +285,59 @@ static inline void fallback_on_nodma_alloc(char **addr, size_t l) static unsigned long fake_change; static int initialising = 1; -#define ITYPE(x) (((x)>>2) & 0x1f) -#define TOMINOR(x) ((x & 3) | ((x & 4) << 5)) -#define UNIT(x) ((x) & 0x03) /* drive on fdc */ -#define FDC(x) (((x) & 0x04) >> 2) /* fdc of drive */ +#define ITYPE(x) (((x) >> 2) & 0x1f) +#define TOMINOR(x) ((x & 3) | ((x & 4) << 5)) +#define UNIT(x) ((x) & 0x03) /* drive on fdc */ +#define FDC(x) (((x) & 0x04) >> 2) /* fdc of drive */ /* reverse mapping from unit and fdc to drive */ #define REVDRIVE(fdc, unit) ((unit) + ((fdc) << 2)) -#define DP (&drive_params[current_drive]) -#define DRS (&drive_state[current_drive]) -#define DRWE (&write_errors[current_drive]) -#define FDCS (&fdc_state[fdc]) -#define CLEARF(x) clear_bit(x##_BIT, &DRS->flags) -#define SETF(x) set_bit(x##_BIT, &DRS->flags) -#define TESTF(x) test_bit(x##_BIT, &DRS->flags) -#define UDP (&drive_params[drive]) -#define UDRS (&drive_state[drive]) -#define UDRWE (&write_errors[drive]) -#define UFDCS (&fdc_state[FDC(drive)]) -#define UCLEARF(x) clear_bit(x##_BIT, &UDRS->flags) -#define USETF(x) set_bit(x##_BIT, &UDRS->flags) -#define UTESTF(x) test_bit(x##_BIT, &UDRS->flags) +#define DP (&drive_params[current_drive]) +#define DRS (&drive_state[current_drive]) +#define DRWE (&write_errors[current_drive]) +#define FDCS (&fdc_state[fdc]) +#define CLEARF(x) clear_bit(x##_BIT, &DRS->flags) +#define SETF(x) set_bit(x##_BIT, &DRS->flags) +#define TESTF(x) test_bit(x##_BIT, &DRS->flags) -#define DPRINT(format, args...) printk(DEVICE_NAME "%d: " format, current_drive , ## args) +#define UDP (&drive_params[drive]) +#define UDRS (&drive_state[drive]) +#define UDRWE (&write_errors[drive]) +#define UFDCS (&fdc_state[FDC(drive)]) +#define UCLEARF(x) clear_bit(x##_BIT, &UDRS->flags) +#define USETF(x) set_bit(x##_BIT, &UDRS->flags) +#define UTESTF(x) test_bit(x##_BIT, &UDRS->flags) -#define PH_HEAD(floppy,head) (((((floppy)->stretch & 2) >>1) ^ head) << 2) -#define STRETCH(floppy) ((floppy)->stretch & FD_STRETCH) +#define DPRINT(format, args...) \ + printk(DEVICE_NAME "%d: " format, current_drive, ##args) -#define CLEARSTRUCT(x) memset((x), 0, sizeof(*(x))) +#define PH_HEAD(floppy, head) (((((floppy)->stretch & 2) >> 1) ^ head) << 2) +#define STRETCH(floppy) ((floppy)->stretch & FD_STRETCH) + +#define CLEARSTRUCT(x) memset((x), 0, sizeof(*(x))) /* read/write */ -#define COMMAND raw_cmd->cmd[0] -#define DR_SELECT raw_cmd->cmd[1] -#define TRACK raw_cmd->cmd[2] -#define HEAD raw_cmd->cmd[3] -#define SECTOR raw_cmd->cmd[4] -#define SIZECODE raw_cmd->cmd[5] -#define SECT_PER_TRACK raw_cmd->cmd[6] -#define GAP raw_cmd->cmd[7] -#define SIZECODE2 raw_cmd->cmd[8] +#define COMMAND (raw_cmd->cmd[0]) +#define DR_SELECT (raw_cmd->cmd[1]) +#define TRACK (raw_cmd->cmd[2]) +#define HEAD (raw_cmd->cmd[3]) +#define SECTOR (raw_cmd->cmd[4]) +#define SIZECODE (raw_cmd->cmd[5]) +#define SECT_PER_TRACK (raw_cmd->cmd[6]) +#define GAP (raw_cmd->cmd[7]) +#define SIZECODE2 (raw_cmd->cmd[8]) #define NR_RW 9 /* format */ -#define F_SIZECODE raw_cmd->cmd[2] -#define F_SECT_PER_TRACK raw_cmd->cmd[3] -#define F_GAP raw_cmd->cmd[4] -#define F_FILL raw_cmd->cmd[5] +#define F_SIZECODE (raw_cmd->cmd[2]) +#define F_SECT_PER_TRACK (raw_cmd->cmd[3]) +#define F_GAP (raw_cmd->cmd[4]) +#define F_FILL (raw_cmd->cmd[5]) #define NR_F 6 /* - * Maximum disk size (in kilobytes). This default is used whenever the - * current disk size is unknown. + * Maximum disk size (in kilobytes). + * This default is used whenever the current disk size is unknown. * [Now it is rather a minimum] */ #define MAX_DISK_SIZE 4 /* 3984 */ @@ -346,15 +348,16 @@ static int initialising = 1; #define MAX_REPLIES 16 static unsigned char reply_buffer[MAX_REPLIES]; static int inr; /* size of reply buffer, when called from interrupt */ -#define ST0 (reply_buffer[0]) -#define ST1 (reply_buffer[1]) -#define ST2 (reply_buffer[2]) -#define ST3 (reply_buffer[0]) /* result of GETSTATUS */ -#define R_TRACK (reply_buffer[3]) -#define R_HEAD (reply_buffer[4]) -#define R_SECTOR (reply_buffer[5]) -#define R_SIZECODE (reply_buffer[6]) -#define SEL_DLY (2*HZ/100) +#define ST0 (reply_buffer[0]) +#define ST1 (reply_buffer[1]) +#define ST2 (reply_buffer[2]) +#define ST3 (reply_buffer[0]) /* result of GETSTATUS */ +#define R_TRACK (reply_buffer[3]) +#define R_HEAD (reply_buffer[4]) +#define R_SECTOR (reply_buffer[5]) +#define R_SIZECODE (reply_buffer[6]) + +#define SEL_DLY (2 * HZ / 100) /* * this struct defines the different floppy drive types. @@ -505,9 +508,9 @@ static char floppy_device_name[] = "floppy"; static int probing; /* Synchronization of FDC access. */ -#define FD_COMMAND_NONE -1 -#define FD_COMMAND_ERROR 2 -#define FD_COMMAND_OKAY 3 +#define FD_COMMAND_NONE -1 +#define FD_COMMAND_ERROR 2 +#define FD_COMMAND_OKAY 3 static volatile int command_status = FD_COMMAND_NONE; static unsigned long fdc_busy; @@ -515,11 +518,11 @@ static DECLARE_WAIT_QUEUE_HEAD(fdc_wait); static DECLARE_WAIT_QUEUE_HEAD(command_done); #define NO_SIGNAL (!interruptible || !signal_pending(current)) -#define CALL(x) if ((x) == -EINTR) return -EINTR -#define ECALL(x) if ((ret = (x))) return ret; -#define _WAIT(x,i) CALL(ret=wait_til_done((x),i)) -#define WAIT(x) _WAIT((x),interruptible) -#define IWAIT(x) _WAIT((x),1) +#define CALL(x) if ((x) == -EINTR) return -EINTR +#define ECALL(x) if ((ret = (x))) return ret; +#define _WAIT(x,i) CALL(ret=wait_til_done((x),i)) +#define WAIT(x) _WAIT((x),interruptible) +#define IWAIT(x) _WAIT((x),1) /* Errors during formatting are counted here. */ static int format_errors; @@ -545,8 +548,9 @@ static int max_buffer_sectors; static int *errors; typedef void (*done_f)(int); static struct cont_t { - void (*interrupt)(void); /* this is called after the interrupt of the - * main command */ + void (*interrupt)(void); + /* this is called after the interrupt of the + * main command */ void (*redo)(void); /* this is called to retry the operation */ void (*error)(void); /* this is called to tally an error */ done_f done; /* this is called to say if the operation has @@ -579,9 +583,9 @@ static void reset_fdc(void); * information to interrupts. They are the data used for the current * request. */ -#define NO_TRACK -1 -#define NEED_1_RECAL -2 -#define NEED_2_RECAL -3 +#define NO_TRACK -1 +#define NEED_1_RECAL -2 +#define NEED_2_RECAL -3 static int usage_count; @@ -647,13 +651,13 @@ static void is_alive(const char *message) } #endif -static void (*do_floppy) (void) = NULL; +static void (*do_floppy)(void) = NULL; #ifdef FLOPPY_SANITY_CHECK #define OLOGSIZE 20 -static void (*lasthandler) (void); +static void (*lasthandler)(void); static unsigned long interruptjiffies; static unsigned long resultjiffies; static int resultsize; @@ -699,8 +703,8 @@ static void reschedule_timeout(int drive, const char *message, int marg) spin_unlock_irqrestore(&floppy_lock, flags); } -#define INFBOUND(a,b) (a)=max_t(int, a, b) -#define SUPBOUND(a,b) (a)=min_t(int, a, b) +#define INFBOUND(a, b) (a) = max_t(int, a, b) +#define SUPBOUND(a, b) (a) = min_t(int, a, b) /* * Bottom half floppy driver. @@ -909,10 +913,12 @@ static int _lock_fdc(int drive, int interruptible, int line) return 0; } -#define lock_fdc(drive,interruptible) _lock_fdc(drive,interruptible, __LINE__) +#define lock_fdc(drive, interruptible) \ + _lock_fdc(drive, interruptible, __LINE__) -#define LOCK_FDC(drive,interruptible) \ -if (lock_fdc(drive,interruptible)) return -EINTR; +#define LOCK_FDC(drive, interruptible) \ + if (lock_fdc(drive, interruptible)) \ + return -EINTR; /* unlocks the driver */ static inline void unlock_fdc(void) @@ -1003,7 +1009,7 @@ static void empty(void) static DECLARE_WORK(floppy_work, NULL); -static void schedule_bh(void (*handler) (void)) +static void schedule_bh(void (*handler)(void)) { PREPARE_WORK(&floppy_work, (work_func_t)handler); schedule_work(&floppy_work); @@ -2181,8 +2187,9 @@ static void format_interrupt(void) } #define CODE2SIZE (ssize = ((1 << SIZECODE) + 3) >> 2) -#define FM_MODE(x,y) ((y) & ~(((x)->rate & 0x80) >>1)) +#define FM_MODE(x, y) ((y) & ~(((x)->rate & 0x80) >> 1)) #define CT(x) ((x) | 0xc0) + static void setup_format_params(int track) { int n; @@ -2197,8 +2204,8 @@ static void setup_format_params(int track) raw_cmd = &default_raw_cmd; raw_cmd->track = track; - raw_cmd->flags = FD_RAW_WRITE | FD_RAW_INTR | FD_RAW_SPIN | - FD_RAW_NEED_DISK | FD_RAW_NEED_SEEK; + raw_cmd->flags = (FD_RAW_WRITE | FD_RAW_INTR | FD_RAW_SPIN | + FD_RAW_NEED_DISK | FD_RAW_NEED_SEEK); raw_cmd->rate = _floppy->rate & 0x43; raw_cmd->cmd_count = NR_F; COMMAND = FM_MODE(_floppy, FD_FORMAT); @@ -2600,8 +2607,9 @@ static void virtualdmabug_workaround(void) return; } #endif - SECT_PER_TRACK = end_sector; /* make sure SECT_PER_TRACK points - * to end of transfer */ + SECT_PER_TRACK = end_sector; + /* make sure SECT_PER_TRACK + * points to end of transfer */ } } @@ -3075,16 +3083,19 @@ static inline int fd_copyout(void __user *param, const void *address, return copy_to_user(param, address, size) ? -EFAULT : 0; } -static inline int fd_copyin(void __user *param, void *address, unsigned long size) +static inline int fd_copyin(void __user *param, void *address, + unsigned long size) { return copy_from_user(address, param, size) ? -EFAULT : 0; } -#define _COPYOUT(x) (copy_to_user((void __user *)param, &(x), sizeof(x)) ? -EFAULT : 0) -#define _COPYIN(x) (copy_from_user(&(x), (void __user *)param, sizeof(x)) ? -EFAULT : 0) +#define _COPYOUT(x) (copy_to_user((void __user *)param, &(x), sizeof(x)) \ + ? -EFAULT : 0) +#define _COPYIN(x) (copy_from_user(&(x), (void __user *)param, sizeof(x)) \ + ? -EFAULT : 0) -#define COPYOUT(x) ECALL(_COPYOUT(x)) -#define COPYIN(x) ECALL(_COPYIN(x)) +#define COPYOUT(x) ECALL(_COPYOUT(x)) +#define COPYIN(x) ECALL(_COPYIN(x)) static inline const char *drive_name(int type, int drive) { @@ -4148,7 +4159,8 @@ static ssize_t floppy_cmos_show(struct device *dev, drive = p->id; return sprintf(buf, "%X\n", UDP->cmos); } -DEVICE_ATTR(cmos,S_IRUGO,floppy_cmos_show,NULL); + +DEVICE_ATTR(cmos, S_IRUGO, floppy_cmos_show, NULL); static void floppy_device_release(struct device *dev) { @@ -4625,6 +4637,7 @@ static void __exit floppy_module_exit(void) /* eject disk, if any */ fd_eject(0); } + module_exit(floppy_module_exit); module_param(floppy, charp, 0); @@ -4636,9 +4649,10 @@ MODULE_LICENSE("GPL"); /* This doesn't actually get used other than for module information */ static const struct pnp_device_id floppy_pnpids[] = { - { "PNP0700", 0 }, - { } + {"PNP0700", 0}, + {} }; + MODULE_DEVICE_TABLE(pnp, floppy_pnpids); #else -- cgit v1.2.3 From b46df356de8c63882cfb1ee7501bd9c772a6981b Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:46 -0800 Subject: drivers/block/floppy.c: use pr_ Convert bare printk to pr_info and pr_cont Convert printk(KERN_ERR to pr_err Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 353 ++++++++++++++++++++++++------------------------- 1 file changed, 175 insertions(+), 178 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 652668d76a8a..dae637abeec3 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -273,7 +273,7 @@ static inline void fallback_on_nodma_alloc(char **addr, size_t l) return; /* we have the memory */ if (can_use_virtual_dma != 2) return; /* no fallback allowed */ - printk("DMA memory shortage. Temporarily falling back on virtual DMA\n"); + pr_info("DMA memory shortage. Temporarily falling back on virtual DMA\n"); *addr = (char *)nodma_mem_alloc(l); #else return; @@ -309,7 +309,7 @@ static int initialising = 1; #define UTESTF(x) test_bit(x##_BIT, &UDRS->flags) #define DPRINT(format, args...) \ - printk(DEVICE_NAME "%d: " format, current_drive, ##args) + pr_info(DEVICE_NAME "%d: " format, current_drive, ##args) #define PH_HEAD(floppy, head) (((((floppy)->stretch & 2) >> 1) ^ head) << 2) #define STRETCH(floppy) ((floppy)->stretch & FD_STRETCH) @@ -628,7 +628,7 @@ static inline void set_debugt(void) static inline void debugt(const char *message) { if (DP->flags & DEBUGT) - printk("%s dtime=%lu\n", message, jiffies - debugtimer); + pr_info("%s dtime=%lu\n", message, jiffies - debugtimer); } #else static inline void set_debugt(void) { } @@ -687,9 +687,7 @@ static void __reschedule_timeout(int drive, const char *message, int marg) fd_timeout.expires = jiffies + UDP->timeout; add_timer(&fd_timeout); if (UDP->flags & FD_DEBUG) { - DPRINT("reschedule timeout "); - printk(message, marg); - printk("\n"); + DPRINT("reschedule timeout %s %d\n", message, marg); } timeout_message = message; } @@ -861,7 +859,7 @@ static void set_fdc(int drive) current_drive = drive; } if (fdc != 1 && fdc != 0) { - printk("bad fdc value\n"); + pr_info("bad fdc value\n"); return; } set_dor(fdc, ~0, 8); @@ -878,8 +876,7 @@ static void set_fdc(int drive) static int _lock_fdc(int drive, int interruptible, int line) { if (!usage_count) { - printk(KERN_ERR - "Trying to lock fdc while usage count=0 at line %d\n", + pr_err("Trying to lock fdc while usage count=0 at line %d\n", line); return -1; } @@ -1115,16 +1112,16 @@ static void setup_DMA(void) if (raw_cmd->length == 0) { int i; - printk("zero dma transfer size:"); + pr_info("zero dma transfer size:"); for (i = 0; i < raw_cmd->cmd_count; i++) - printk("%x,", raw_cmd->cmd[i]); - printk("\n"); + pr_cont("%x,", raw_cmd->cmd[i]); + pr_cont("\n"); cont->done(0); FDCS->reset = 1; return; } if (((unsigned long)raw_cmd->kernel_data) % 512) { - printk("non aligned address: %p\n", raw_cmd->kernel_data); + pr_info("non aligned address: %p\n", raw_cmd->kernel_data); cont->done(0); FDCS->reset = 1; return; @@ -1427,10 +1424,40 @@ static int fdc_dtr(void) static void tell_sector(void) { - printk(": track %d, head %d, sector %d, size %d", - R_TRACK, R_HEAD, R_SECTOR, R_SIZECODE); + pr_cont(": track %d, head %d, sector %d, size %d", + R_TRACK, R_HEAD, R_SECTOR, R_SIZECODE); } /* tell_sector */ +static void print_errors(void) +{ + DPRINT(""); + if (ST0 & ST0_ECE) { + pr_cont("Recalibrate failed!"); + } else if (ST2 & ST2_CRC) { + pr_cont("data CRC error"); + tell_sector(); + } else if (ST1 & ST1_CRC) { + pr_cont("CRC error"); + tell_sector(); + } else if ((ST1 & (ST1_MAM | ST1_ND)) || + (ST2 & ST2_MAM)) { + if (!probing) { + pr_cont("sector not found"); + tell_sector(); + } else + pr_cont("probe failed..."); + } else if (ST2 & ST2_WC) { /* seek error */ + pr_cont("wrong cylinder"); + } else if (ST2 & ST2_BC) { /* cylinder marked as bad */ + pr_cont("bad cylinder"); + } else { + pr_cont("unknown error. ST[0..2] are: 0x%x 0x%x 0x%x", + ST0, ST1, ST2); + tell_sector(); + } + pr_cont("\n"); +} + /* * OK, this error interpreting routine is called after a * DMA read/write has succeeded @@ -1466,33 +1493,7 @@ static int interpret_errors(void) DPRINT("Over/Underrun - retrying\n"); bad = 0; } else if (*errors >= DP->max_errors.reporting) { - DPRINT(""); - if (ST0 & ST0_ECE) { - printk("Recalibrate failed!"); - } else if (ST2 & ST2_CRC) { - printk("data CRC error"); - tell_sector(); - } else if (ST1 & ST1_CRC) { - printk("CRC error"); - tell_sector(); - } else if ((ST1 & (ST1_MAM | ST1_ND)) - || (ST2 & ST2_MAM)) { - if (!probing) { - printk("sector not found"); - tell_sector(); - } else - printk("probe failed..."); - } else if (ST2 & ST2_WC) { /* seek error */ - printk("wrong cylinder"); - } else if (ST2 & ST2_BC) { /* cylinder marked as bad */ - printk("bad cylinder"); - } else { - printk - ("unknown error. ST[0..2] are: 0x%x 0x%x 0x%x", - ST0, ST1, ST2); - tell_sector(); - } - printk("\n"); + print_errors(); } if (ST2 & ST2_WC || ST2 & ST2_BC) /* wrong cylinder => recal */ @@ -1591,8 +1592,7 @@ static void seek_interrupt(void) if (DRS->track >= 0 && DRS->track != ST1 && !blind_seek) { #ifdef DCL_DEBUG if (DP->flags & FD_DEBUG) { - DPRINT - ("clearing NEWCHANGE flag because of effective seek\n"); + DPRINT("clearing NEWCHANGE flag because of effective seek\n"); DPRINT("jiffies=%lu\n", jiffies); } #endif @@ -1712,10 +1712,8 @@ static void recal_interrupt(void) * be already at track 0.) Clear the * new change flag */ #ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) { - DPRINT - ("clearing NEWCHANGE flag because of second recalibrate\n"); - } + if (DP->flags & FD_DEBUG) + DPRINT("clearing NEWCHANGE flag because of second recalibrate\n"); #endif CLEARF(FD_DISK_NEWCHANGE); @@ -1744,8 +1742,8 @@ static void print_result(char *message, int inr) DPRINT("%s ", message); if (inr >= 0) for (i = 0; i < inr; i++) - printk("repl[%d]=%x ", i, reply_buffer[i]); - printk("\n"); + pr_cont("repl[%d]=%x ", i, reply_buffer[i]); + pr_cont("\n"); } /* interrupt handler. Note that this can be called externally on the Sparc */ @@ -1766,9 +1764,9 @@ irqreturn_t floppy_interrupt(int irq, void *dev_id) do_floppy = NULL; if (fdc >= N_FDC || FDCS->address == -1) { /* we don't even know which FDC is the culprit */ - printk("DOR0=%x\n", fdc_state[0].dor); - printk("floppy interrupt on bizarre fdc %d\n", fdc); - printk("handler=%p\n", handler); + pr_info("DOR0=%x\n", fdc_state[0].dor); + pr_info("floppy interrupt on bizarre fdc %d\n", fdc); + pr_info("handler=%p\n", handler); is_alive("bizarre fdc"); return IRQ_NONE; } @@ -1826,7 +1824,7 @@ static void reset_interrupt(void) debugt("reset interrupt:"); result(); /* get the status ready for set_fdc */ if (FDCS->reset) { - printk("reset set in interrupt, calling %p\n", cont->error); + pr_info("reset set in interrupt, calling %p\n", cont->error); cont->error(); /* a reset just after a reset. BAD! */ } cont->redo(); @@ -1864,46 +1862,44 @@ static void show_floppy(void) { int i; - printk("\n"); - printk("floppy driver state\n"); - printk("-------------------\n"); - printk("now=%lu last interrupt=%lu diff=%lu last called handler=%p\n", - jiffies, interruptjiffies, jiffies - interruptjiffies, - lasthandler); + pr_info("\n"); + pr_info("floppy driver state\n"); + pr_info("-------------------\n"); + pr_info("now=%lu last interrupt=%lu diff=%lu last called handler=%p\n", + jiffies, interruptjiffies, jiffies - interruptjiffies, + lasthandler); #ifdef FLOPPY_SANITY_CHECK - printk("timeout_message=%s\n", timeout_message); - printk("last output bytes:\n"); + pr_info("timeout_message=%s\n", timeout_message); + pr_info("last output bytes:\n"); for (i = 0; i < OLOGSIZE; i++) - printk("%2x %2x %lu\n", - output_log[(i + output_log_pos) % OLOGSIZE].data, - output_log[(i + output_log_pos) % OLOGSIZE].status, - output_log[(i + output_log_pos) % OLOGSIZE].jiffies); - printk("last result at %lu\n", resultjiffies); - printk("last redo_fd_request at %lu\n", lastredo); - for (i = 0; i < resultsize; i++) { - printk("%2x ", reply_buffer[i]); - } - printk("\n"); + pr_info("%2x %2x %lu\n", + output_log[(i + output_log_pos) % OLOGSIZE].data, + output_log[(i + output_log_pos) % OLOGSIZE].status, + output_log[(i + output_log_pos) % OLOGSIZE].jiffies); + pr_info("last result at %lu\n", resultjiffies); + pr_info("last redo_fd_request at %lu\n", lastredo); + print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, + reply_buffer, resultsize, true); #endif - printk("status=%x\n", fd_inb(FD_STATUS)); - printk("fdc_busy=%lu\n", fdc_busy); + pr_info("status=%x\n", fd_inb(FD_STATUS)); + pr_info("fdc_busy=%lu\n", fdc_busy); if (do_floppy) - printk("do_floppy=%p\n", do_floppy); + pr_info("do_floppy=%p\n", do_floppy); if (work_pending(&floppy_work)) - printk("floppy_work.func=%p\n", floppy_work.func); + pr_info("floppy_work.func=%p\n", floppy_work.func); if (timer_pending(&fd_timer)) - printk("fd_timer.function=%p\n", fd_timer.function); + pr_info("fd_timer.function=%p\n", fd_timer.function); if (timer_pending(&fd_timeout)) { - printk("timer_function=%p\n", fd_timeout.function); - printk("expires=%lu\n", fd_timeout.expires - jiffies); - printk("now=%lu\n", jiffies); - } - printk("cont=%p\n", cont); - printk("current_req=%p\n", current_req); - printk("command_status=%d\n", command_status); - printk("\n"); + pr_info("timer_function=%p\n", fd_timeout.function); + pr_info("expires=%lu\n", fd_timeout.expires - jiffies); + pr_info("now=%lu\n", jiffies); + } + pr_info("cont=%p\n", cont); + pr_info("current_req=%p\n", current_req); + pr_info("command_status=%d\n", command_status); + pr_info("\n"); } static void floppy_shutdown(unsigned long data) @@ -1929,7 +1925,7 @@ static void floppy_shutdown(unsigned long data) cont->done(0); cont->redo(); /* this will recall reset when needed */ } else { - printk("no cont in shutdown!\n"); + pr_info("no cont in shutdown!\n"); process_fd_request(); } is_alive("floppy shutdown"); @@ -2329,10 +2325,10 @@ static void request_done(int uptodate) int block; probing = 0; - reschedule_timeout(MAXTIMEOUT, "request done %d", uptodate); + reschedule_timeout(MAXTIMEOUT, "request done", uptodate); if (!req) { - printk("floppy.c: no request in request_done\n"); + pr_info("floppy.c: no request in request_done\n"); return; } @@ -2405,13 +2401,13 @@ static void rw_interrupt(void) DIV_ROUND_UP(in_sector_offset + current_count_sectors, ssize)) { DPRINT("long rw: %x instead of %lx\n", nr_sectors, current_count_sectors); - printk("rs=%d s=%d\n", R_SECTOR, SECTOR); - printk("rh=%d h=%d\n", R_HEAD, HEAD); - printk("rt=%d t=%d\n", R_TRACK, TRACK); - printk("heads=%d eoc=%d\n", heads, eoc); - printk("spt=%d st=%d ss=%d\n", SECT_PER_TRACK, - fsector_t, ssize); - printk("in_sector_offset=%d\n", in_sector_offset); + pr_info("rs=%d s=%d\n", R_SECTOR, SECTOR); + pr_info("rh=%d h=%d\n", R_HEAD, HEAD); + pr_info("rt=%d t=%d\n", R_TRACK, TRACK); + pr_info("heads=%d eoc=%d\n", heads, eoc); + pr_info("spt=%d st=%d ss=%d\n", + SECT_PER_TRACK, fsector_t, ssize); + pr_info("in_sector_offset=%d\n", in_sector_offset); } #endif @@ -2521,14 +2517,14 @@ static void copy_buffer(int ssize, int max_sector, int max_sector_2) #ifdef FLOPPY_SANITY_CHECK if (remaining > blk_rq_bytes(current_req) && CT(COMMAND) == FD_WRITE) { DPRINT("in copy buffer\n"); - printk("current_count_sectors=%ld\n", current_count_sectors); - printk("remaining=%d\n", remaining >> 9); - printk("current_req->nr_sectors=%u\n", - blk_rq_sectors(current_req)); - printk("current_req->current_nr_sectors=%u\n", - blk_rq_cur_sectors(current_req)); - printk("max_sector=%d\n", max_sector); - printk("ssize=%d\n", ssize); + pr_info("current_count_sectors=%ld\n", current_count_sectors); + pr_info("remaining=%d\n", remaining >> 9); + pr_info("current_req->nr_sectors=%u\n", + blk_rq_sectors(current_req)); + pr_info("current_req->current_nr_sectors=%u\n", + blk_rq_cur_sectors(current_req)); + pr_info("max_sector=%d\n", max_sector); + pr_info("ssize=%d\n", ssize); } #endif @@ -2551,16 +2547,15 @@ static void copy_buffer(int ssize, int max_sector, int max_sector_2) floppy_track_buffer + (max_buffer_sectors << 10) || dma_buffer < floppy_track_buffer) { DPRINT("buffer overrun in copy buffer %d\n", - (int)((floppy_track_buffer - - dma_buffer) >> 9)); - printk("fsector_t=%d buffer_min=%d\n", - fsector_t, buffer_min); - printk("current_count_sectors=%ld\n", - current_count_sectors); + (int)((floppy_track_buffer - dma_buffer) >> 9)); + pr_info("fsector_t=%d buffer_min=%d\n", + fsector_t, buffer_min); + pr_info("current_count_sectors=%ld\n", + current_count_sectors); if (CT(COMMAND) == FD_READ) - printk("read\n"); + pr_info("read\n"); if (CT(COMMAND) == FD_WRITE) - printk("write\n"); + pr_info("write\n"); break; } if (((unsigned long)buffer) % 512) @@ -2602,8 +2597,8 @@ static void virtualdmabug_workaround(void) end_sector = SECTOR + hard_sectors - 1; #ifdef FLOPPY_SANITY_CHECK if (end_sector > SECT_PER_TRACK) { - printk("too many sectors %d > %d\n", - end_sector, SECT_PER_TRACK); + pr_info("too many sectors %d > %d\n", + end_sector, SECT_PER_TRACK); return; } #endif @@ -2632,7 +2627,7 @@ static int make_raw_rw_request(void) int ssize; if (max_buffer_sectors == 0) { - printk("VFS: Block I/O scheduled on unopened device\n"); + pr_info("VFS: Block I/O scheduled on unopened device\n"); return 0; } @@ -2853,19 +2848,19 @@ static int make_raw_rw_request(void) DPRINT("fractionary current count b=%lx s=%lx\n", raw_cmd->length, current_count_sectors); if (raw_cmd->kernel_data != current_req->buffer) - printk("addr=%d, length=%ld\n", - (int)((raw_cmd->kernel_data - - floppy_track_buffer) >> 9), - current_count_sectors); - printk("st=%d ast=%d mse=%d msi=%d\n", - fsector_t, aligned_sector_t, max_sector, max_size); - printk("ssize=%x SIZECODE=%d\n", ssize, SIZECODE); - printk("command=%x SECTOR=%d HEAD=%d, TRACK=%d\n", - COMMAND, SECTOR, HEAD, TRACK); - printk("buffer drive=%d\n", buffer_drive); - printk("buffer track=%d\n", buffer_track); - printk("buffer_min=%d\n", buffer_min); - printk("buffer_max=%d\n", buffer_max); + pr_info("addr=%d, length=%ld\n", + (int)((raw_cmd->kernel_data - + floppy_track_buffer) >> 9), + current_count_sectors); + pr_info("st=%d ast=%d mse=%d msi=%d\n", + fsector_t, aligned_sector_t, max_sector, max_size); + pr_info("ssize=%x SIZECODE=%d\n", ssize, SIZECODE); + pr_info("command=%x SECTOR=%d HEAD=%d, TRACK=%d\n", + COMMAND, SECTOR, HEAD, TRACK); + pr_info("buffer drive=%d\n", buffer_drive); + pr_info("buffer track=%d\n", buffer_track); + pr_info("buffer_min=%d\n", buffer_min); + pr_info("buffer_max=%d\n", buffer_max); return 0; } @@ -2876,14 +2871,14 @@ static int make_raw_rw_request(void) raw_cmd->kernel_data + raw_cmd->length > floppy_track_buffer + (max_buffer_sectors << 10)) { DPRINT("buffer overrun in schedule dma\n"); - printk("fsector_t=%d buffer_min=%d current_count=%ld\n", - fsector_t, buffer_min, raw_cmd->length >> 9); - printk("current_count_sectors=%ld\n", - current_count_sectors); + pr_info("fsector_t=%d buffer_min=%d current_count=%ld\n", + fsector_t, buffer_min, raw_cmd->length >> 9); + pr_info("current_count_sectors=%ld\n", + current_count_sectors); if (CT(COMMAND) == FD_READ) - printk("read\n"); + pr_info("read\n"); if (CT(COMMAND) == FD_WRITE) - printk("write\n"); + pr_info("write\n"); return 0; } } else if (raw_cmd->length > blk_rq_bytes(current_req) || @@ -2892,8 +2887,8 @@ static int make_raw_rw_request(void) return 0; } else if (raw_cmd->length < current_count_sectors << 9) { DPRINT("more sectors than bytes\n"); - printk("bytes=%ld\n", raw_cmd->length >> 9); - printk("sectors=%ld\n", current_count_sectors); + pr_info("bytes=%ld\n", raw_cmd->length >> 9); + pr_info("sectors=%ld\n", current_count_sectors); } if (raw_cmd->length == 0) { DPRINT("zero dma transfer attempted from make_raw_request\n"); @@ -2990,16 +2985,16 @@ static void process_fd_request(void) static void do_fd_request(struct request_queue * q) { if (max_buffer_sectors == 0) { - printk("VFS: do_fd_request called on non-open device\n"); + pr_info("VFS: do_fd_request called on non-open device\n"); return; } if (usage_count == 0) { - printk("warning: usage count=0, current_req=%p exiting\n", - current_req); - printk("sect=%ld type=%x flags=%x\n", - (long)blk_rq_pos(current_req), current_req->cmd_type, - current_req->cmd_flags); + pr_info("warning: usage count=0, current_req=%p exiting\n", + current_req); + pr_info("sect=%ld type=%x flags=%x\n", + (long)blk_rq_pos(current_req), current_req->cmd_type, + current_req->cmd_flags); return; } if (test_bit(0, &fdc_busy)) { @@ -3047,7 +3042,7 @@ static int poll_drive(int interruptible, int flag) static void reset_intr(void) { - printk("weird, reset interrupt called\n"); + pr_info("weird, reset interrupt called\n"); } static struct cont_t reset_cont = { @@ -3426,7 +3421,7 @@ static inline int normalize_ioctl(int *cmd, int *size) *size = _IOC_SIZE(*cmd); *cmd = ioctl_table[i]; if (*size > _IOC_SIZE(*cmd)) { - printk("ioctl not yet supported\n"); + pr_info("ioctl not yet supported\n"); return -EFAULT; } return 0; @@ -3634,7 +3629,7 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, static void __init config_types(void) { - int first = 1; + bool has_drive = false; int drive; /* read drive info out of physical CMOS */ @@ -3666,17 +3661,22 @@ static void __init config_types(void) name = temparea; } if (name) { - const char *prepend = ","; - if (first) { - prepend = KERN_INFO "Floppy drive(s):"; - first = 0; + const char *prepend; + if (!has_drive) { + prepend = ""; + has_drive = true; + pr_info("Floppy drive(s):"); + } else { + prepend = ","; } - printk("%s fd%d is %s", prepend, drive, name); + + pr_cont("%s fd%d is %s", prepend, drive, name); } *UDP = *params; } - if (!first) - printk("\n"); + + if (has_drive) + pr_cont("\n"); } static int floppy_release(struct gendisk *disk, fmode_t mode) @@ -3891,7 +3891,7 @@ static int floppy_revalidate(struct gendisk *disk) if (UTESTF(FD_DISK_CHANGED) || UTESTF(FD_VERIFY) || test_bit(drive, &fake_change) || NO_GEOM) { if (usage_count == 0) { - printk("VFS: revalidate called on non-open device.\n"); + pr_info("VFS: revalidate called on non-open device.\n"); return -EFAULT; } lock_fdc(drive, 0); @@ -3948,18 +3948,17 @@ static char __init get_fdc_version(void) if ((r = result()) <= 0x00) return FDC_NONE; /* No FDC present ??? */ if ((r == 1) && (reply_buffer[0] == 0x80)) { - printk(KERN_INFO "FDC %d is an 8272A\n", fdc); + pr_info("FDC %d is an 8272A\n", fdc); return FDC_8272A; /* 8272a/765 don't know DUMPREGS */ } if (r != 10) { - printk - ("FDC %d init: DUMPREGS: unexpected return of %d bytes.\n", - fdc, r); + pr_info("FDC %d init: DUMPREGS: unexpected return of %d bytes.\n", + fdc, r); return FDC_UNKNOWN; } if (!fdc_configure()) { - printk(KERN_INFO "FDC %d is an 82072\n", fdc); + pr_info("FDC %d is an 82072\n", fdc); return FDC_82072; /* 82072 doesn't know CONFIGURE */ } @@ -3967,52 +3966,50 @@ static char __init get_fdc_version(void) if (need_more_output() == MORE_OUTPUT) { output_byte(0); } else { - printk(KERN_INFO "FDC %d is an 82072A\n", fdc); + pr_info("FDC %d is an 82072A\n", fdc); return FDC_82072A; /* 82072A as found on Sparcs. */ } output_byte(FD_UNLOCK); r = result(); if ((r == 1) && (reply_buffer[0] == 0x80)) { - printk(KERN_INFO "FDC %d is a pre-1991 82077\n", fdc); + pr_info("FDC %d is a pre-1991 82077\n", fdc); return FDC_82077_ORIG; /* Pre-1991 82077, doesn't know * LOCK/UNLOCK */ } if ((r != 1) || (reply_buffer[0] != 0x00)) { - printk("FDC %d init: UNLOCK: unexpected return of %d bytes.\n", - fdc, r); + pr_info("FDC %d init: UNLOCK: unexpected return of %d bytes.\n", + fdc, r); return FDC_UNKNOWN; } output_byte(FD_PARTID); r = result(); if (r != 1) { - printk("FDC %d init: PARTID: unexpected return of %d bytes.\n", - fdc, r); + pr_info("FDC %d init: PARTID: unexpected return of %d bytes.\n", + fdc, r); return FDC_UNKNOWN; } if (reply_buffer[0] == 0x80) { - printk(KERN_INFO "FDC %d is a post-1991 82077\n", fdc); + pr_info("FDC %d is a post-1991 82077\n", fdc); return FDC_82077; /* Revised 82077AA passes all the tests */ } switch (reply_buffer[0] >> 5) { case 0x0: /* Either a 82078-1 or a 82078SL running at 5Volt */ - printk(KERN_INFO "FDC %d is an 82078.\n", fdc); + pr_info("FDC %d is an 82078.\n", fdc); return FDC_82078; case 0x1: - printk(KERN_INFO "FDC %d is a 44pin 82078\n", fdc); + pr_info("FDC %d is a 44pin 82078\n", fdc); return FDC_82078; case 0x2: - printk(KERN_INFO "FDC %d is a S82078B\n", fdc); + pr_info("FDC %d is a S82078B\n", fdc); return FDC_S82078B; case 0x3: - printk(KERN_INFO "FDC %d is a National Semiconductor PC87306\n", - fdc); + pr_info("FDC %d is a National Semiconductor PC87306\n", fdc); return FDC_87306; default: - printk(KERN_INFO - "FDC %d init: 82078 variant with unknown PARTID=%d.\n", - fdc, reply_buffer[0] >> 5); + pr_info("FDC %d init: 82078 variant with unknown PARTID=%d.\n", + fdc, reply_buffer[0] >> 5); return FDC_82078_UNKN; } } /* get_fdc_version */ @@ -4140,8 +4137,8 @@ static int __init floppy_setup(char *str) DPRINT("allowed options are:"); for (i = 0; i < ARRAY_SIZE(config_params); i++) - printk(" %s", config_params[i].name); - printk("\n"); + pr_cont(" %s", config_params[i].name); + pr_cont("\n"); } else DPRINT("botched floppy option\n"); DPRINT("Read Documentation/blockdev/floppy.txt\n"); @@ -4563,15 +4560,15 @@ static void floppy_release_irq_and_dma(void) #ifndef __sparc__ for (drive = 0; drive < N_FDC * 4; drive++) if (timer_pending(motor_off_timer + drive)) - printk("motor off timer %d still active\n", drive); + pr_info("motor off timer %d still active\n", drive); #endif if (timer_pending(&fd_timeout)) - printk("floppy timer still active:%s\n", timeout_message); + pr_info("floppy timer still active:%s\n", timeout_message); if (timer_pending(&fd_timer)) - printk("auxiliary floppy timer still active\n"); + pr_info("auxiliary floppy timer still active\n"); if (work_pending(&floppy_work)) - printk("work still pending\n"); + pr_info("work still pending\n"); #endif old_fdc = fdc; for (fdc = 0; fdc < N_FDC; fdc++) -- cgit v1.2.3 From a81ee5447157a4b9930bab8ec70cf77a55db64e8 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:46 -0800 Subject: drivers/block/floppy.c: remove unnecessary braces Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 44 +++++++++++++++++--------------------------- 1 file changed, 17 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index dae637abeec3..3072003d81ca 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -686,9 +686,8 @@ static void __reschedule_timeout(int drive, const char *message, int marg) } else fd_timeout.expires = jiffies + UDP->timeout; add_timer(&fd_timeout); - if (UDP->flags & FD_DEBUG) { + if (UDP->flags & FD_DEBUG) DPRINT("reschedule timeout %s %d\n", message, marg); - } timeout_message = message; } @@ -809,9 +808,8 @@ static int set_dor(int fdc, char mask, char data) if (is_selected(olddor, unit) && !is_selected(newdor, unit)) { drive = REVDRIVE(fdc, unit); #ifdef DCL_DEBUG - if (UDP->flags & FD_DEBUG) { + if (UDP->flags & FD_DEBUG) DPRINT("calling disk change from set_dor\n"); - } #endif disk_change(drive); } @@ -1030,9 +1028,8 @@ static void cancel_activity(void) static void fd_watchdog(void) { #ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) { + if (DP->flags & FD_DEBUG) DPRINT("calling disk change from watchdog\n"); - } #endif if (disk_change(current_drive)) { @@ -1369,9 +1366,9 @@ static void fdc_specify(void) /* Convert step rate from microseconds to milliseconds and 4 bits */ srt = 16 - DIV_ROUND_UP(DP->srt * scale_dtr / 1000, NOMINAL_DTR); - if (slow_floppy) { + if (slow_floppy) srt = srt / 4; - } + SUPBOUND(srt, 0xf); INFBOUND(srt, 0); @@ -1635,9 +1632,8 @@ static void seek_floppy(void) blind_seek = 0; #ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) { + if (DP->flags & FD_DEBUG) DPRINT("calling disk change from seek\n"); - } #endif if (!TESTF(FD_DISK_NEWCHANGE) && @@ -1969,9 +1965,8 @@ static void floppy_ready(void) return; #ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) { + if (DP->flags & FD_DEBUG) DPRINT("calling disk change from floppy_ready\n"); - } #endif if (!(raw_cmd->flags & FD_RAW_NO_MOTOR) && disk_change(current_drive) && !DP->select_delay) @@ -2004,9 +1999,8 @@ static void floppy_start(void) scandrives(); #ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) { + if (DP->flags & FD_DEBUG) DPRINT("setting NEWCHANGE in floppy_start\n"); - } #endif SETF(FD_DISK_NEWCHANGE); floppy_ready(); @@ -2758,9 +2752,8 @@ static int make_raw_rw_request(void) dma_limit = (MAX_DMA_ADDRESS - ((unsigned long)current_req->buffer)) >> 9; - if ((unsigned long)max_size > dma_limit) { + if ((unsigned long)max_size > dma_limit) max_size = dma_limit; - } /* 64 kb boundaries */ if (CROSS_64KB(current_req->buffer, max_size << 9)) max_size = (K_64 - @@ -3026,9 +3019,8 @@ static int poll_drive(int interruptible, int flag) raw_cmd->cmd_count = 0; cont = &poll_cont; #ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) { + if (DP->flags & FD_DEBUG) DPRINT("setting NEWCHANGE in poll_drive\n"); - } #endif SETF(FD_DISK_NEWCHANGE); WAIT(floppy_ready); @@ -3291,9 +3283,8 @@ static int raw_cmd_ioctl(int cmd, void __user *param) cont = &raw_cmd_cont; ret = wait_til_done(floppy_start, 1); #ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) { + if (DP->flags & FD_DEBUG) DPRINT("calling disk change from raw_cmd ioctl\n"); - } #endif if (ret != -EINTR && FDCS->reset) @@ -3486,18 +3477,18 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, * We do this in order to provide a means to eject floppy disks before * installing the new fdutils package */ if (cmd == CDROMEJECT || /* CD-ROM eject */ - cmd == 0x6470 /* SunOS floppy eject */ ) { + cmd == 0x6470) { /* SunOS floppy eject */ DPRINT("obsolete eject ioctl\n"); DPRINT("please use floppycontrol --eject\n"); cmd = FDEJECT; } - /* convert the old style command into a new style command */ - if ((cmd & 0xff00) == 0x0200) { - ECALL(normalize_ioctl(&cmd, &size)); - } else + if (!((cmd & 0xff00) == 0x0200)) return -EINVAL; + /* convert the old style command into a new style command */ + ECALL(normalize_ioctl(&cmd, &size)); + /* permission checks */ if (((cmd & 0x40) && !FD_IOCTL_ALLOWED) || ((cmd & 0x80) && !capable(CAP_SYS_ADMIN))) @@ -3746,9 +3737,8 @@ static int floppy_open(struct block_device *bdev, fmode_t mode) INFBOUND(try, 16); tmp = (char *)fd_dma_mem_alloc(1024 * try); } - if (!tmp && !floppy_track_buffer) { + if (!tmp && !floppy_track_buffer) fallback_on_nodma_alloc(&tmp, 2048 * try); - } if (!tmp && !floppy_track_buffer) { DPRINT("Unable to allocate DMA memory\n"); goto out; -- cgit v1.2.3 From 045f98363080ddbbcef6b8b8306ec58a818406a0 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:47 -0800 Subject: drivers/block/floppy.c: remove used once CHECK_READY macro Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 3072003d81ca..88a741c75110 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -575,7 +575,6 @@ static void floppy_release_irq_and_dma(void); * reset doesn't need to be tested before sending commands, because * output_byte is automatically disabled when reset is set. */ -#define CHECK_RESET { if (FDCS->reset){ reset_fdc(); return; } } static void reset_fdc(void); /* @@ -1958,7 +1957,10 @@ static int start_motor(void (*function)(void)) static void floppy_ready(void) { - CHECK_RESET; + if (FDCS->reset) { + reset_fdc(); + return; + } if (start_motor(floppy_ready)) return; if (fdc_dtr()) -- cgit v1.2.3 From d7b2b2ecd88d06ae212d069a4e187ab690b1636f Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:48 -0800 Subject: drivers/block/floppy.c: hoist assigns from if()s, neatening Move assigns above if()s Remove unnecessary parentheses from returns Use a temporary for a duplicated test Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 53 +++++++++++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 88a741c75110..7d1cd21a0ebc 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -1175,9 +1175,9 @@ static int wait_til_ready(void) /* sends a command byte to the fdc */ static int output_byte(char byte) { - int status; + int status = wait_til_ready(); - if ((status = wait_til_ready()) < 0) + if (status < 0) return -1; if ((status & (STATUS_READY | STATUS_DIR | STATUS_DMA)) == STATUS_READY) { fd_outb(byte, FD_DATA); @@ -1207,7 +1207,8 @@ static int result(void) int status = 0; for (i = 0; i < MAX_REPLIES; i++) { - if ((status = wait_til_ready()) < 0) + status = wait_til_ready(); + if (status < 0) break; status &= STATUS_DIR | STATUS_READY | STATUS_BUSY | STATUS_DMA; if ((status & ~STATUS_BUSY) == STATUS_READY) { @@ -1236,9 +1237,9 @@ static int result(void) /* does the fdc need more output? */ static int need_more_output(void) { - int status; + int status = wait_til_ready(); - if ((status = wait_til_ready()) < 0) + if (status < 0) return -1; if ((status & (STATUS_READY | STATUS_DIR | STATUS_DMA)) == STATUS_READY) return MORE_OUTPUT; @@ -1414,8 +1415,8 @@ static int fdc_dtr(void) * Pause 5 msec to avoid trouble. (Needs to be 2 jiffies) */ FDCS->dtr = raw_cmd->rate & 3; - return (fd_wait_for_completion(jiffies + 2UL * HZ / 100, - (timeout_fn) floppy_ready)); + return fd_wait_for_completion(jiffies + 2UL * HZ / 100, + (timeout_fn)floppy_ready); } /* fdc_dtr */ static void tell_sector(void) @@ -1951,8 +1952,8 @@ static int start_motor(void (*function)(void)) set_dor(fdc, mask, data); /* wait_for_completion also schedules reset if needed. */ - return (fd_wait_for_completion(DRS->select_date + DP->select_delay, - (timeout_fn) function)); + return fd_wait_for_completion(DRS->select_date + DP->select_delay, + (timeout_fn)function); } static void floppy_ready(void) @@ -2729,8 +2730,10 @@ static int make_raw_rw_request(void) } } else if (in_sector_offset || blk_rq_sectors(current_req) < ssize) { if (CT(COMMAND) == FD_WRITE) { - if (fsector_t + blk_rq_sectors(current_req) > ssize && - fsector_t + blk_rq_sectors(current_req) < ssize + ssize) + unsigned int sectors; + + sectors = fsector_t + blk_rq_sectors(current_req); + if (sectors > ssize && sectors < ssize + ssize) max_size = ssize + ssize; else max_size = ssize; @@ -2751,9 +2754,8 @@ static int make_raw_rw_request(void) * on a 64 bit machine! */ max_size = buffer_chain_size(); - dma_limit = - (MAX_DMA_ADDRESS - - ((unsigned long)current_req->buffer)) >> 9; + dma_limit = (MAX_DMA_ADDRESS - + ((unsigned long)current_req->buffer)) >> 9; if ((unsigned long)max_size > dma_limit) max_size = dma_limit; /* 64 kb boundaries */ @@ -2771,16 +2773,16 @@ static int make_raw_rw_request(void) */ if (!direct || (indirect * 2 > direct * 3 && - *errors < DP->max_errors.read_track && ((!probing - || (DP->read_track & (1 << DRS->probed_format)))))) { + *errors < DP->max_errors.read_track && + ((!probing || + (DP->read_track & (1 << DRS->probed_format)))))) { max_size = blk_rq_sectors(current_req); } else { raw_cmd->kernel_data = current_req->buffer; raw_cmd->length = current_count_sectors << 9; if (raw_cmd->length == 0) { - DPRINT - ("zero dma transfer attempted from make_raw_request\n"); - DPRINT("indirect=%d direct=%d fsector_t=%d", + DPRINT("zero dma transfer attempted from make_raw_request\n"); + DPRINT("indirect=%d direct=%d fsector_t=%d\n", indirect, direct, fsector_t); return 0; } @@ -2977,7 +2979,7 @@ static void process_fd_request(void) schedule_bh(redo_fd_request); } -static void do_fd_request(struct request_queue * q) +static void do_fd_request(struct request_queue *q) { if (max_buffer_sectors == 0) { pr_info("VFS: do_fd_request called on non-open device\n"); @@ -3937,7 +3939,8 @@ static char __init get_fdc_version(void) output_byte(FD_DUMPREGS); /* 82072 and better know DUMPREGS */ if (FDCS->reset) return FDC_NONE; - if ((r = result()) <= 0x00) + r = result(); + if (r <= 0x00) return FDC_NONE; /* No FDC present ??? */ if ((r == 1) && (reply_buffer[0] == 0x80)) { pr_info("FDC %d is an 8272A\n", fdc); @@ -3966,7 +3969,7 @@ static char __init get_fdc_version(void) r = result(); if ((r == 1) && (reply_buffer[0] == 0x80)) { pr_info("FDC %d is a pre-1991 82077\n", fdc); - return FDC_82077_ORIG; /* Pre-1991 82077, doesn't know + return FDC_82077_ORIG; /* Pre-1991 82077, doesn't know * LOCK/UNLOCK */ } if ((r != 1) || (reply_buffer[0] != 0x00)) { @@ -4357,7 +4360,8 @@ static int __init floppy_init(void) if (err) goto out_flush_work; - err = device_create_file(&floppy_device[drive].dev,&dev_attr_cmos); + err = device_create_file(&floppy_device[drive].dev, + &dev_attr_cmos); if (err) goto out_unreg_platform_dev; @@ -4578,7 +4582,8 @@ static void __init parse_floppy_cfg_string(char *cfg) char *ptr; while (*cfg) { - for (ptr = cfg; *cfg && *cfg != ' ' && *cfg != '\t'; cfg++) ; + for (ptr = cfg; *cfg && *cfg != ' ' && *cfg != '\t'; cfg++) + ; if (*cfg) { *cfg = '\0'; cfg++; -- cgit v1.2.3 From 2300f90e31178f44b0e903c12ea311df1297d7fa Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:49 -0800 Subject: drivers/block/floppy.c: remove LAST_OUT macro Macros with hidden returns are not nice. Convert the 2 uses to use direct code. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 7d1cd21a0ebc..7c0c7d09e089 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -1198,8 +1198,6 @@ static int output_byte(char byte) return -1; } -#define LAST_OUT(x) if (output_byte(x)<0){ reset_fdc();return;} - /* gets the response from the fdc */ static int result(void) { @@ -1679,7 +1677,10 @@ static void seek_floppy(void) do_floppy = seek_interrupt; output_byte(FD_SEEK); output_byte(UNIT(current_drive)); - LAST_OUT(track); + if (output_byte(track) < 0) { + reset_fdc(); + return; + } debugt("seek command:"); } @@ -1809,7 +1810,10 @@ static void recalibrate_floppy(void) debugt("recalibrate floppy:"); do_floppy = recal_interrupt; output_byte(FD_RECALIBRATE); - LAST_OUT(UNIT(current_drive)); + if (output_byte(UNIT(current_drive)) < 0) { + reset_fdc(); + return; + } } /* -- cgit v1.2.3 From bb57f0c662faa9879e8f265c9bc1f15bb238d2c7 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:50 -0800 Subject: drivers/block/floppy.c: comment neatening and remove naked ; Spacing, column alignment and a for loop with a naked semicolon converted to an assign and while Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 55 +++++++++++++++++++++++++++----------------------- 1 file changed, 30 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 7c0c7d09e089..48aefd9c5662 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -1262,9 +1262,12 @@ static inline void perpendicular_mode(void) default: DPRINT("Invalid data rate for perpendicular mode!\n"); cont->done(0); - FDCS->reset = 1; /* convenient way to return to - * redo without to much hassle (deep - * stack et al. */ + FDCS->reset = 1; + /* + * convenient way to return to + * redo without too much hassle + * (deep stack et al.) + */ return; } } else @@ -1977,8 +1980,8 @@ static void floppy_ready(void) #endif if (!(raw_cmd->flags & FD_RAW_NO_MOTOR) && disk_change(current_drive) && !DP->select_delay) - twaddle(); /* this clears the dcl on certain drive/controller - * combinations */ + twaddle(); /* this clears the dcl on certain + * drive/controller combinations */ #ifdef fd_chose_dma_mode if ((raw_cmd->flags & FD_RAW_READ) || (raw_cmd->flags & FD_RAW_WRITE)) { @@ -2806,15 +2809,14 @@ static int make_raw_rw_request(void) ((CT(COMMAND) == FD_READ || (!in_sector_offset && blk_rq_sectors(current_req) >= ssize)) && max_sector > 2 * max_buffer_sectors + buffer_min && - max_size + fsector_t > 2 * max_buffer_sectors + buffer_min) - /* not enough space */ - ) { + max_size + fsector_t > 2 * max_buffer_sectors + buffer_min)) { + /* not enough space */ buffer_track = -1; buffer_drive = current_drive; buffer_max = buffer_min = aligned_sector_t; } raw_cmd->kernel_data = floppy_track_buffer + - ((aligned_sector_t - buffer_min) << 9); + ((aligned_sector_t - buffer_min) << 9); if (CT(COMMAND) == FD_WRITE) { /* copy write buffer to track buffer. @@ -3171,11 +3173,12 @@ static inline int raw_cmd_copyout(int cmd, char __user *param, COPYOUT(*ptr); param += sizeof(struct floppy_raw_cmd); if ((ptr->flags & FD_RAW_READ) && ptr->buffer_length) { - if (ptr->length >= 0 - && ptr->length <= ptr->buffer_length) - ECALL(fd_copyout - (ptr->data, ptr->kernel_data, - ptr->buffer_length - ptr->length)); + if (ptr->length >= 0 && + ptr->length <= ptr->buffer_length) { + long length = ptr->buffer_length - ptr->length; + ECALL(fd_copyout(ptr->data, ptr->kernel_data, + length)); + } } ptr = ptr->next; } @@ -3827,8 +3830,7 @@ static int check_floppy_change(struct gendisk *disk) * a disk in the drive, and whether that disk is writable. */ -static void floppy_rb0_complete(struct bio *bio, - int err) +static void floppy_rb0_complete(struct bio *bio, int err) { complete((struct completion *)bio->bi_private); } @@ -4120,9 +4122,9 @@ static int __init floppy_setup(char *str) else param = config_params[i].def_param; if (config_params[i].fn) - config_params[i]. - fn(ints, param, - config_params[i].param2); + config_params[i].fn(ints, param, + config_params[i]. + param2); if (config_params[i].var) { DPRINT("%s=%d\n", str, param); *config_params[i].var = param; @@ -4180,8 +4182,8 @@ static const struct dev_pm_ops floppy_pm_ops = { static struct platform_driver floppy_driver = { .driver = { - .name = "floppy", - .pm = &floppy_pm_ops, + .name = "floppy", + .pm = &floppy_pm_ops, }, }; @@ -4429,8 +4431,10 @@ static int floppy_request_regions(int fdc) const struct io_region *p; for (p = io_regions; p < ARRAY_END(io_regions); p++) { - if (!request_region(FDCS->address + p->offset, p->size, "floppy")) { - DPRINT("Floppy io-port 0x%04lx in use\n", FDCS->address + p->offset); + if (!request_region(FDCS->address + p->offset, + p->size, "floppy")) { + DPRINT("Floppy io-port 0x%04lx in use\n", + FDCS->address + p->offset); floppy_release_allocated_regions(fdc, p); return -EBUSY; } @@ -4586,8 +4590,9 @@ static void __init parse_floppy_cfg_string(char *cfg) char *ptr; while (*cfg) { - for (ptr = cfg; *cfg && *cfg != ' ' && *cfg != '\t'; cfg++) - ; + ptr = cfg; + while (*cfg && *cfg != ' ' && *cfg != '\t') + cfg++; if (*cfg) { *cfg = '\0'; cfg++; -- cgit v1.2.3 From b87c9e0a880f2992dc210eb4ea8b2da6c63883ca Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:50 -0800 Subject: drivers/block/floppy.c: remove CLEARSTRUCT macro, use memset Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 48aefd9c5662..0cea96ceb78c 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -314,8 +314,6 @@ static int initialising = 1; #define PH_HEAD(floppy, head) (((((floppy)->stretch & 2) >> 1) ^ head) << 2) #define STRETCH(floppy) ((floppy)->stretch & FD_STRETCH) -#define CLEARSTRUCT(x) memset((x), 0, sizeof(*(x))) - /* read/write */ #define COMMAND (raw_cmd->cmd[0]) #define DR_SELECT (raw_cmd->cmd[1]) @@ -3509,7 +3507,7 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, return -EINVAL; /* copyin */ - CLEARSTRUCT(&inparam); + memset(&inparam, 0, sizeof(inparam)); if (_IOC_DIR(cmd) & _IOC_WRITE) ECALL(fd_copyin((void __user *)param, &inparam, size)) @@ -3598,7 +3596,7 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, OUT(FDGETFDCSTAT, UFDCS); case FDWERRORCLR: - CLEARSTRUCT(UDRWE); + memset(UDRWE, 0, sizeof(*UDRWE)); return 0; OUT(FDWERRORGET, UDRWE); @@ -4260,7 +4258,7 @@ static int __init floppy_init(void) for (i = 0; i < N_FDC; i++) { fdc = i; - CLEARSTRUCT(FDCS); + memset(FDCS, 0, sizeof(*FDCS)); FDCS->dtr = -1; FDCS->dor = 0x4; #if defined(__sparc__) || defined(__mc68000__) @@ -4293,8 +4291,8 @@ static int __init floppy_init(void) /* initialise drive state */ for (drive = 0; drive < N_DRIVE; drive++) { - CLEARSTRUCT(UDRS); - CLEARSTRUCT(UDRWE); + memset(UDRS, 0, sizeof(*UDRS)); + memset(UDRWE, 0, sizeof(*UDRWE)); USETF(FD_DISK_NEWCHANGE); USETF(FD_DISK_CHANGED); USETF(FD_VERIFY); -- cgit v1.2.3 From 96534f1dd5bf9d324c2d31355cb69565381d1460 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:51 -0800 Subject: drivers/block/floppy.c: indent a comment Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 0cea96ceb78c..7743d6c2dd6b 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -4262,7 +4262,7 @@ static int __init floppy_init(void) FDCS->dtr = -1; FDCS->dor = 0x4; #if defined(__sparc__) || defined(__mc68000__) - /*sparcs/sun3x don't have a DOR reset which we can fall back on to */ + /*sparcs/sun3x don't have a DOR reset which we can fall back on to */ #ifdef __mc68000__ if (MACH_IS_SUN3X) #endif -- cgit v1.2.3 From da27365342868df88fdd5c217bf68ec10b14b5f0 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:52 -0800 Subject: drivers/block/floppy.c: remove IN/OUT macros, indent switch/case Remove ugly IN/OUT macros, use direct case and code Add missing semicolon after ECALL Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 218 ++++++++++++++++++++++++------------------------- 1 file changed, 107 insertions(+), 111 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 7743d6c2dd6b..b58ceae9d0b5 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -3466,8 +3466,6 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, unsigned long param) { #define FD_IOCTL_ALLOWED (mode & (FMODE_WRITE|FMODE_WRITE_IOCTL)) -#define OUT(c,x) case c: outparam = (const char *) (x); break -#define IN(c,x,tag) case c: *(x) = inparam. tag ; return 0 int drive = (long)bdev->bd_disk->private_data; int type = ITYPE(UDRS->fd_device); @@ -3509,122 +3507,120 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, /* copyin */ memset(&inparam, 0, sizeof(inparam)); if (_IOC_DIR(cmd) & _IOC_WRITE) - ECALL(fd_copyin((void __user *)param, &inparam, size)) + ECALL(fd_copyin((void __user *)param, &inparam, size)); - switch (cmd) { - case FDEJECT: - if (UDRS->fd_ref != 1) - /* somebody else has this drive open */ - return -EBUSY; - LOCK_FDC(drive, 1); - - /* do the actual eject. Fails on - * non-Sparc architectures */ - ret = fd_eject(UNIT(drive)); - - USETF(FD_DISK_CHANGED); - USETF(FD_VERIFY); - process_fd_request(); - return ret; - case FDCLRPRM: - LOCK_FDC(drive, 1); - current_type[drive] = NULL; - floppy_sizes[drive] = MAX_DISK_SIZE << 1; - UDRS->keep_data = 0; - return invalidate_drive(bdev); - case FDSETPRM: - case FDDEFPRM: - return set_geometry(cmd, &inparam.g, - drive, type, bdev); - case FDGETPRM: - ECALL(get_floppy_geometry(drive, type, - (struct floppy_struct **) - &outparam)); - break; - - case FDMSGON: - UDP->flags |= FTD_MSG; - return 0; - case FDMSGOFF: - UDP->flags &= ~FTD_MSG; - return 0; - - case FDFMTBEG: - LOCK_FDC(drive, 1); - CALL(poll_drive(1, FD_RAW_NEED_DISK)); - ret = UDRS->flags; - process_fd_request(); - if (ret & FD_VERIFY) - return -ENODEV; - if (!(ret & FD_DISK_WRITABLE)) - return -EROFS; - return 0; - case FDFMTTRK: - if (UDRS->fd_ref != 1) - return -EBUSY; - return do_format(drive, &inparam.f); - case FDFMTEND: - case FDFLUSH: - LOCK_FDC(drive, 1); - return invalidate_drive(bdev); - - case FDSETEMSGTRESH: - UDP->max_errors.reporting = - (unsigned short)(param & 0x0f); - return 0; - OUT(FDGETMAXERRS, &UDP->max_errors); - IN(FDSETMAXERRS, &UDP->max_errors, max_errors); - - case FDGETDRVTYP: - outparam = drive_name(type, drive); - SUPBOUND(size, strlen(outparam) + 1); - break; - - IN(FDSETDRVPRM, UDP, dp); - OUT(FDGETDRVPRM, UDP); - - case FDPOLLDRVSTAT: - LOCK_FDC(drive, 1); - CALL(poll_drive(1, FD_RAW_NEED_DISK)); - process_fd_request(); - /* fall through */ - OUT(FDGETDRVSTAT, UDRS); - - case FDRESET: - return user_reset_fdc(drive, (int)param, 1); - - OUT(FDGETFDCSTAT, UFDCS); - - case FDWERRORCLR: - memset(UDRWE, 0, sizeof(*UDRWE)); - return 0; - OUT(FDWERRORGET, UDRWE); - - case FDRAWCMD: - if (type) - return -EINVAL; - LOCK_FDC(drive, 1); - set_floppy(drive); - CALL(i = raw_cmd_ioctl(cmd, (void __user *)param)); - process_fd_request(); - return i; + switch (cmd) { + case FDEJECT: + if (UDRS->fd_ref != 1) + /* somebody else has this drive open */ + return -EBUSY; + LOCK_FDC(drive, 1); - case FDTWADDLE: - LOCK_FDC(drive, 1); - twaddle(); - process_fd_request(); - return 0; + /* do the actual eject. Fails on + * non-Sparc architectures */ + ret = fd_eject(UNIT(drive)); - default: + USETF(FD_DISK_CHANGED); + USETF(FD_VERIFY); + process_fd_request(); + return ret; + case FDCLRPRM: + LOCK_FDC(drive, 1); + current_type[drive] = NULL; + floppy_sizes[drive] = MAX_DISK_SIZE << 1; + UDRS->keep_data = 0; + return invalidate_drive(bdev); + case FDSETPRM: + case FDDEFPRM: + return set_geometry(cmd, &inparam.g, drive, type, bdev); + case FDGETPRM: + ECALL(get_floppy_geometry(drive, type, + (struct floppy_struct **) + &outparam)); + break; + case FDMSGON: + UDP->flags |= FTD_MSG; + return 0; + case FDMSGOFF: + UDP->flags &= ~FTD_MSG; + return 0; + case FDFMTBEG: + LOCK_FDC(drive, 1); + CALL(poll_drive(1, FD_RAW_NEED_DISK)); + ret = UDRS->flags; + process_fd_request(); + if (ret & FD_VERIFY) + return -ENODEV; + if (!(ret & FD_DISK_WRITABLE)) + return -EROFS; + return 0; + case FDFMTTRK: + if (UDRS->fd_ref != 1) + return -EBUSY; + return do_format(drive, &inparam.f); + case FDFMTEND: + case FDFLUSH: + LOCK_FDC(drive, 1); + return invalidate_drive(bdev); + case FDSETEMSGTRESH: + UDP->max_errors.reporting = (unsigned short)(param & 0x0f); + return 0; + case FDGETMAXERRS: + outparam = (const char *)&UDP->max_errors; + break; + case FDSETMAXERRS: + UDP->max_errors = inparam.max_errors; + break; + case FDGETDRVTYP: + outparam = drive_name(type, drive); + SUPBOUND(size, strlen(outparam) + 1); + break; + case FDSETDRVPRM: + *UDP = inparam.dp; + break; + case FDGETDRVPRM: + outparam = (const char *)UDP; + break; + case FDPOLLDRVSTAT: + LOCK_FDC(drive, 1); + CALL(poll_drive(1, FD_RAW_NEED_DISK)); + process_fd_request(); + /* fall through */ + case FDGETDRVSTAT: + outparam = (const char *)UDRS; + break; + case FDRESET: + return user_reset_fdc(drive, (int)param, 1); + case FDGETFDCSTAT: + outparam = (const char *)UFDCS; + break; + case FDWERRORCLR: + memset(UDRWE, 0, sizeof(*UDRWE)); + return 0; + case FDWERRORGET: + outparam = (const char *)UDRWE; + break; + case FDRAWCMD: + if (type) return -EINVAL; - } + LOCK_FDC(drive, 1); + set_floppy(drive); + CALL(i = raw_cmd_ioctl(cmd, (void __user *)param)); + process_fd_request(); + return i; + case FDTWADDLE: + LOCK_FDC(drive, 1); + twaddle(); + process_fd_request(); + return 0; + default: + return -EINVAL; + } if (_IOC_DIR(cmd) & _IOC_READ) return fd_copyout((void __user *)param, outparam, size); - else - return 0; -#undef OUT -#undef IN + + return 0; } static void __init config_types(void) -- cgit v1.2.3 From a0a52d67de6da21db0e549e38749b7a00029fea3 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:52 -0800 Subject: drivers/block/floppy.c: remove a few spaces from function casts Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index b58ceae9d0b5..491f21ae83b6 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -632,7 +632,7 @@ static inline void set_debugt(void) { } static inline void debugt(const char *message) { } #endif /* DEBUGT */ -typedef void (*timeout_fn) (unsigned long); +typedef void (*timeout_fn)(unsigned long); static DEFINE_TIMER(fd_timeout, floppy_shutdown, 0, 0); static const char *timeout_message; @@ -1036,7 +1036,7 @@ static void fd_watchdog(void) reset_fdc(); } else { del_timer(&fd_timer); - fd_timer.function = (timeout_fn) fd_watchdog; + fd_timer.function = (timeout_fn)fd_watchdog; fd_timer.expires = jiffies + HZ / 10; add_timer(&fd_timer); } @@ -1534,9 +1534,9 @@ static void setup_rw_floppy(void) */ if (time_after(ready_date, jiffies + DP->select_delay)) { ready_date -= DP->select_delay; - function = (timeout_fn) floppy_start; + function = (timeout_fn)floppy_start; } else - function = (timeout_fn) setup_rw_floppy; + function = (timeout_fn)setup_rw_floppy; /* wait until the floppy is spinning fast enough */ if (fd_wait_for_completion(ready_date, function)) -- cgit v1.2.3 From 52a0d61f64123ab758d8b8cc8f8ca521733d2f32 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:53 -0800 Subject: drivers/block/floppy.c: remove macro LOCK_FDC Macros with hidden returns aren't nice. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 491f21ae83b6..50bd9e9370dd 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -908,10 +908,6 @@ static int _lock_fdc(int drive, int interruptible, int line) #define lock_fdc(drive, interruptible) \ _lock_fdc(drive, interruptible, __LINE__) -#define LOCK_FDC(drive, interruptible) \ - if (lock_fdc(drive, interruptible)) \ - return -EINTR; - /* unlocks the driver */ static inline void unlock_fdc(void) { @@ -2276,7 +2272,9 @@ static int do_format(int drive, struct format_descr *tmp_format_req) { int ret; - LOCK_FDC(drive, 1); + if (lock_fdc(drive, 1)) + return -EINTR; + set_floppy(drive); if (!_floppy || _floppy->track > DP->tracks || @@ -3056,8 +3054,9 @@ static int user_reset_fdc(int drive, int arg, int interruptible) { int ret; - ret = 0; - LOCK_FDC(drive, interruptible); + if (lock_fdc(drive, interruptible)) + return -EINTR; + if (arg == FD_RESET_ALWAYS) FDCS->reset = 1; if (FDCS->reset) { @@ -3065,7 +3064,7 @@ static int user_reset_fdc(int drive, int arg, int interruptible) WAIT(reset_fdc); } process_fd_request(); - return ret; + return 0; } /* @@ -3352,7 +3351,9 @@ static inline int set_geometry(unsigned int cmd, struct floppy_struct *g, mutex_unlock(&open_lock); } else { int oldStretch; - LOCK_FDC(drive, 1); + + if (lock_fdc(drive, 1)) + return -EINTR; if (cmd != FDDEFPRM) /* notice a disk change immediately, else * we lose our settings immediately*/ @@ -3435,7 +3436,8 @@ static int get_floppy_geometry(int drive, int type, struct floppy_struct **g) if (type) *g = &floppy_type[type]; else { - LOCK_FDC(drive, 0); + if (lock_fdc(drive, 0)) + return -EINTR; CALL(poll_drive(0, 0)); process_fd_request(); *g = current_type[drive]; @@ -3514,7 +3516,8 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, if (UDRS->fd_ref != 1) /* somebody else has this drive open */ return -EBUSY; - LOCK_FDC(drive, 1); + if (lock_fdc(drive, 1)) + return -EINTR; /* do the actual eject. Fails on * non-Sparc architectures */ @@ -3525,7 +3528,8 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, process_fd_request(); return ret; case FDCLRPRM: - LOCK_FDC(drive, 1); + if (lock_fdc(drive, 1)) + return -EINTR; current_type[drive] = NULL; floppy_sizes[drive] = MAX_DISK_SIZE << 1; UDRS->keep_data = 0; @@ -3545,7 +3549,8 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, UDP->flags &= ~FTD_MSG; return 0; case FDFMTBEG: - LOCK_FDC(drive, 1); + if (lock_fdc(drive, 1)) + return -EINTR; CALL(poll_drive(1, FD_RAW_NEED_DISK)); ret = UDRS->flags; process_fd_request(); @@ -3560,7 +3565,8 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, return do_format(drive, &inparam.f); case FDFMTEND: case FDFLUSH: - LOCK_FDC(drive, 1); + if (lock_fdc(drive, 1)) + return -EINTR; return invalidate_drive(bdev); case FDSETEMSGTRESH: UDP->max_errors.reporting = (unsigned short)(param & 0x0f); @@ -3582,7 +3588,8 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, outparam = (const char *)UDP; break; case FDPOLLDRVSTAT: - LOCK_FDC(drive, 1); + if (lock_fdc(drive, 1)) + return -EINTR; CALL(poll_drive(1, FD_RAW_NEED_DISK)); process_fd_request(); /* fall through */ @@ -3603,13 +3610,15 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, case FDRAWCMD: if (type) return -EINVAL; - LOCK_FDC(drive, 1); + if (lock_fdc(drive, 1)) + return -EINTR; set_floppy(drive); CALL(i = raw_cmd_ioctl(cmd, (void __user *)param)); process_fd_request(); return i; case FDTWADDLE: - LOCK_FDC(drive, 1); + if (lock_fdc(drive, 1)) + return -EINTR; twaddle(); process_fd_request(); return 0; -- cgit v1.2.3 From 87f530d8f1733651f3e34b81c801d6e1bb635936 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:54 -0800 Subject: drivers/block/floppy.c: add debug_dcl(...) macro Converted #ifdef DCL_DEBUG if (test) DPRINTK(...); #endif to debug_dcl(test, ...); Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 83 +++++++++++++++++++------------------------------- 1 file changed, 31 insertions(+), 52 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 50bd9e9370dd..41f366327193 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -152,6 +152,15 @@ #define DEBUGT 2 #define DCL_DEBUG /* debug disk change line */ +#ifdef DCL_DEBUG +#define debug_dcl(test, fmt, args...) \ + do { if ((test) & FD_DEBUG) DPRINT(fmt, ##args); } while (0) +#else +#define debug_dcl(test, fmt, args...) \ + do { if (0) DPRINT(fmt, ##args); } while (0) +#endif + + /* do print messages for unexpected interrupts */ static int print_unex = 1; #include @@ -748,14 +757,12 @@ static int disk_change(int drive) } #endif -#ifdef DCL_DEBUG - if (UDP->flags & FD_DEBUG) { - DPRINT("checking disk change line for drive %d\n", drive); - DPRINT("jiffies=%lu\n", jiffies); - DPRINT("disk change line=%x\n", fd_inb(FD_DIR) & 0x80); - DPRINT("flags=%lx\n", UDRS->flags); - } -#endif + debug_dcl(UDP->flags, + "checking disk change line for drive %d\n", drive); + debug_dcl(UDP->flags, "jiffies=%lu\n", jiffies); + debug_dcl(UDP->flags, "disk change line=%x\n", fd_inb(FD_DIR) & 0x80); + debug_dcl(UDP->flags, "flags=%lx\n", UDRS->flags); + if (UDP->flags & FD_BROKEN_DCL) return UTESTF(FD_DISK_CHANGED); if ((fd_inb(FD_DIR) ^ UDP->flags) & 0x80) { @@ -804,10 +811,8 @@ static int set_dor(int fdc, char mask, char data) unit = olddor & 0x3; if (is_selected(olddor, unit) && !is_selected(newdor, unit)) { drive = REVDRIVE(fdc, unit); -#ifdef DCL_DEBUG - if (UDP->flags & FD_DEBUG) - DPRINT("calling disk change from set_dor\n"); -#endif + debug_dcl(UDP->flags, + "calling disk change from set_dor\n"); disk_change(drive); } FDCS->dor = newdor; @@ -1020,10 +1025,7 @@ static void cancel_activity(void) * transfer */ static void fd_watchdog(void) { -#ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) - DPRINT("calling disk change from watchdog\n"); -#endif + debug_dcl(DP->flags, "calling disk change from watchdog\n"); if (disk_change(current_drive)) { DPRINT("disk removed during i/o\n"); @@ -1582,12 +1584,9 @@ static void seek_interrupt(void) return; } if (DRS->track >= 0 && DRS->track != ST1 && !blind_seek) { -#ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) { - DPRINT("clearing NEWCHANGE flag because of effective seek\n"); - DPRINT("jiffies=%lu\n", jiffies); - } -#endif + debug_dcl(DP->flags, + "clearing NEWCHANGE flag because of effective seek\n"); + debug_dcl(DP->flags, "jiffies=%lu\n", jiffies); CLEARF(FD_DISK_NEWCHANGE); /* effective seek */ DRS->select_date = jiffies; } @@ -1607,12 +1606,9 @@ static void check_wp(void) } CLEARF(FD_VERIFY); CLEARF(FD_NEED_TWADDLE); -#ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) { - DPRINT("checking whether disk is write protected\n"); - DPRINT("wp=%x\n", ST3 & 0x40); - } -#endif + debug_dcl(DP->flags, + "checking whether disk is write protected\n"); + debug_dcl(DP->flags, "wp=%x\n", ST3 & 0x40); if (!(ST3 & 0x40)) SETF(FD_DISK_WRITABLE); else @@ -1626,10 +1622,7 @@ static void seek_floppy(void) blind_seek = 0; -#ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) - DPRINT("calling disk change from seek\n"); -#endif + debug_dcl(DP->flags, "calling disk change from seek\n"); if (!TESTF(FD_DISK_NEWCHANGE) && disk_change(current_drive) && (raw_cmd->flags & FD_RAW_NEED_DISK)) { @@ -1705,10 +1698,8 @@ static void recal_interrupt(void) * not to move at recalibration is to * be already at track 0.) Clear the * new change flag */ -#ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) - DPRINT("clearing NEWCHANGE flag because of second recalibrate\n"); -#endif + debug_dcl(DP->flags, + "clearing NEWCHANGE flag because of second recalibrate\n"); CLEARF(FD_DISK_NEWCHANGE); DRS->select_date = jiffies; @@ -1968,10 +1959,7 @@ static void floppy_ready(void) if (fdc_dtr()) return; -#ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) - DPRINT("calling disk change from floppy_ready\n"); -#endif + debug_dcl(DP->flags, "calling disk change from floppy_ready\n"); if (!(raw_cmd->flags & FD_RAW_NO_MOTOR) && disk_change(current_drive) && !DP->select_delay) twaddle(); /* this clears the dcl on certain @@ -2002,10 +1990,7 @@ static void floppy_start(void) reschedule_timeout(current_reqD, "floppy start", 0); scandrives(); -#ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) - DPRINT("setting NEWCHANGE in floppy_start\n"); -#endif + debug_dcl(DP->flags, "setting NEWCHANGE in floppy_start\n"); SETF(FD_DISK_NEWCHANGE); floppy_ready(); } @@ -3024,10 +3009,7 @@ static int poll_drive(int interruptible, int flag) raw_cmd->track = 0; raw_cmd->cmd_count = 0; cont = &poll_cont; -#ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) - DPRINT("setting NEWCHANGE in poll_drive\n"); -#endif + debug_dcl(DP->flags, "setting NEWCHANGE in poll_drive\n"); SETF(FD_DISK_NEWCHANGE); WAIT(floppy_ready); return ret; @@ -3290,10 +3272,7 @@ static int raw_cmd_ioctl(int cmd, void __user *param) raw_cmd = my_raw_cmd; cont = &raw_cmd_cont; ret = wait_til_done(floppy_start, 1); -#ifdef DCL_DEBUG - if (DP->flags & FD_DEBUG) - DPRINT("calling disk change from raw_cmd ioctl\n"); -#endif + debug_dcl(DP->flags, "calling disk change from raw_cmd ioctl\n"); if (ret != -EINTR && FDCS->reset) ret = -EIO; -- cgit v1.2.3 From e029853612ba5999caed4dbc833dab729aac75ba Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:55 -0800 Subject: drivers/block/floppy.c: remove [U]CLEARF, [U]SETF, and [U]TESTF macros Use clear_bit, set_bit, and test_bit functions directly Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 94 +++++++++++++++++++++++++------------------------- 1 file changed, 47 insertions(+), 47 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 41f366327193..35ce4e3f04dd 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -305,17 +305,11 @@ static int initialising = 1; #define DRS (&drive_state[current_drive]) #define DRWE (&write_errors[current_drive]) #define FDCS (&fdc_state[fdc]) -#define CLEARF(x) clear_bit(x##_BIT, &DRS->flags) -#define SETF(x) set_bit(x##_BIT, &DRS->flags) -#define TESTF(x) test_bit(x##_BIT, &DRS->flags) #define UDP (&drive_params[drive]) #define UDRS (&drive_state[drive]) #define UDRWE (&write_errors[drive]) #define UFDCS (&fdc_state[FDC(drive)]) -#define UCLEARF(x) clear_bit(x##_BIT, &UDRS->flags) -#define USETF(x) set_bit(x##_BIT, &UDRS->flags) -#define UTESTF(x) test_bit(x##_BIT, &UDRS->flags) #define DPRINT(format, args...) \ pr_info(DEVICE_NAME "%d: " format, current_drive, ##args) @@ -764,13 +758,13 @@ static int disk_change(int drive) debug_dcl(UDP->flags, "flags=%lx\n", UDRS->flags); if (UDP->flags & FD_BROKEN_DCL) - return UTESTF(FD_DISK_CHANGED); + return test_bit(FD_DISK_CHANGED_BIT, &UDRS->flags); if ((fd_inb(FD_DIR) ^ UDP->flags) & 0x80) { - USETF(FD_VERIFY); /* verify write protection */ - if (UDRS->maxblock) { - /* mark it changed */ - USETF(FD_DISK_CHANGED); - } + set_bit(FD_VERIFY_BIT, &UDRS->flags); + /* verify write protection */ + + if (UDRS->maxblock) /* mark it changed */ + set_bit(FD_DISK_CHANGED_BIT, &UDRS->flags); /* invalidate its geometry */ if (UDRS->keep_data >= 0) { @@ -785,7 +779,7 @@ static int disk_change(int drive) return 1; } else { UDRS->last_checked = jiffies; - UCLEARF(FD_DISK_NEWCHANGE); + clear_bit(FD_DISK_NEWCHANGE_BIT, &UDRS->flags); } return 0; } @@ -1477,11 +1471,11 @@ static int interpret_errors(void) bad = 1; if (ST1 & ST1_WP) { DPRINT("Drive is write protected\n"); - CLEARF(FD_DISK_WRITABLE); + clear_bit(FD_DISK_WRITABLE_BIT, &DRS->flags); cont->done(0); bad = 2; } else if (ST1 & ST1_ND) { - SETF(FD_NEED_TWADDLE); + set_bit(FD_NEED_TWADDLE_BIT, &DRS->flags); } else if (ST1 & ST1_OR) { if (DP->flags & FTD_MSG) DPRINT("Over/Underrun - retrying\n"); @@ -1587,7 +1581,8 @@ static void seek_interrupt(void) debug_dcl(DP->flags, "clearing NEWCHANGE flag because of effective seek\n"); debug_dcl(DP->flags, "jiffies=%lu\n", jiffies); - CLEARF(FD_DISK_NEWCHANGE); /* effective seek */ + clear_bit(FD_DISK_NEWCHANGE_BIT, &DRS->flags); + /* effective seek */ DRS->select_date = jiffies; } DRS->track = ST1; @@ -1596,23 +1591,23 @@ static void seek_interrupt(void) static void check_wp(void) { - if (TESTF(FD_VERIFY)) { - /* check write protection */ + if (test_bit(FD_VERIFY_BIT, &DRS->flags)) { + /* check write protection */ output_byte(FD_GETSTATUS); output_byte(UNIT(current_drive)); if (result() != 1) { FDCS->reset = 1; return; } - CLEARF(FD_VERIFY); - CLEARF(FD_NEED_TWADDLE); + clear_bit(FD_VERIFY_BIT, &DRS->flags); + clear_bit(FD_NEED_TWADDLE_BIT, &DRS->flags); debug_dcl(DP->flags, "checking whether disk is write protected\n"); debug_dcl(DP->flags, "wp=%x\n", ST3 & 0x40); if (!(ST3 & 0x40)) - SETF(FD_DISK_WRITABLE); + set_bit(FD_DISK_WRITABLE_BIT, &DRS->flags); else - CLEARF(FD_DISK_WRITABLE); + clear_bit(FD_DISK_WRITABLE_BIT, &DRS->flags); } } @@ -1624,13 +1619,13 @@ static void seek_floppy(void) debug_dcl(DP->flags, "calling disk change from seek\n"); - if (!TESTF(FD_DISK_NEWCHANGE) && + if (!test_bit(FD_DISK_NEWCHANGE_BIT, &DRS->flags) && disk_change(current_drive) && (raw_cmd->flags & FD_RAW_NEED_DISK)) { /* the media changed flag should be cleared after the seek. * If it isn't, this means that there is really no disk in * the drive. */ - SETF(FD_DISK_CHANGED); + set_bit(FD_DISK_CHANGED_BIT, &DRS->flags); cont->done(0); cont->redo(); return; @@ -1638,7 +1633,7 @@ static void seek_floppy(void) if (DRS->track <= NEED_1_RECAL) { recalibrate_floppy(); return; - } else if (TESTF(FD_DISK_NEWCHANGE) && + } else if (test_bit(FD_DISK_NEWCHANGE_BIT, &DRS->flags) && (raw_cmd->flags & FD_RAW_NEED_DISK) && (DRS->track <= NO_TRACK || DRS->track == raw_cmd->track)) { /* we seek to clear the media-changed condition. Does anybody @@ -1701,7 +1696,7 @@ static void recal_interrupt(void) debug_dcl(DP->flags, "clearing NEWCHANGE flag because of second recalibrate\n"); - CLEARF(FD_DISK_NEWCHANGE); + clear_bit(FD_DISK_NEWCHANGE_BIT, &DRS->flags); DRS->select_date = jiffies; /* fall through */ default: @@ -1991,7 +1986,7 @@ static void floppy_start(void) scandrives(); debug_dcl(DP->flags, "setting NEWCHANGE in floppy_start\n"); - SETF(FD_DISK_NEWCHANGE); + set_bit(FD_DISK_NEWCHANGE_BIT, &DRS->flags); floppy_ready(); } @@ -2647,7 +2642,8 @@ static int make_raw_rw_request(void) HEAD = fsector_t / _floppy->sect; if (((_floppy->stretch & (FD_SWAPSIDES | FD_SECTBASEMASK)) || - TESTF(FD_NEED_TWADDLE)) && fsector_t < _floppy->sect) + test_bit(FD_NEED_TWADDLE_BIT, &DRS->flags)) && + fsector_t < _floppy->sect) max_sector = _floppy->sect; /* 2M disks have phantom sectors on the first track */ @@ -2919,7 +2915,7 @@ static void redo_fd_request(void) return; disk_change(current_drive); if (test_bit(current_drive, &fake_change) || - TESTF(FD_DISK_CHANGED)) { + test_bit(FD_DISK_CHANGED_BIT, &DRS->flags)) { DPRINT("disk absent or changed during operation\n"); REPEAT; } @@ -2944,7 +2940,7 @@ static void redo_fd_request(void) continue; } - if (TESTF(FD_NEED_TWADDLE)) + if (test_bit(FD_NEED_TWADDLE_BIT, &DRS->flags)) twaddle(); schedule_bh(floppy_start); debugt("queue fd request"); @@ -3010,7 +3006,7 @@ static int poll_drive(int interruptible, int flag) raw_cmd->cmd_count = 0; cont = &poll_cont; debug_dcl(DP->flags, "setting NEWCHANGE in poll_drive\n"); - SETF(FD_DISK_NEWCHANGE); + set_bit(FD_DISK_NEWCHANGE_BIT, &DRS->flags); WAIT(floppy_ready); return ret; } @@ -3502,8 +3498,8 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, * non-Sparc architectures */ ret = fd_eject(UNIT(drive)); - USETF(FD_DISK_CHANGED); - USETF(FD_VERIFY); + set_bit(FD_DISK_CHANGED_BIT, &UDRS->flags); + set_bit(FD_VERIFY_BIT, &UDRS->flags); process_fd_request(); return ret; case FDCLRPRM: @@ -3700,8 +3696,8 @@ static int floppy_open(struct block_device *bdev, fmode_t mode) goto out2; if (!UDRS->fd_ref && (UDP->flags & FD_BROKEN_DCL)) { - USETF(FD_DISK_CHANGED); - USETF(FD_VERIFY); + set_bit(FD_DISK_CHANGED_BIT, &UDRS->flags); + set_bit(FD_VERIFY_BIT, &UDRS->flags); } if (UDRS->fd_ref == -1 || (UDRS->fd_ref && (mode & FMODE_EXCL))) @@ -3761,11 +3757,12 @@ static int floppy_open(struct block_device *bdev, fmode_t mode) if (mode & (FMODE_READ|FMODE_WRITE)) { UDRS->last_checked = 0; check_disk_change(bdev); - if (UTESTF(FD_DISK_CHANGED)) + if (test_bit(FD_DISK_CHANGED_BIT, &UDRS->flags)) goto out; } res = -EROFS; - if ((mode & FMODE_WRITE) && !(UTESTF(FD_DISK_WRITABLE))) + if ((mode & FMODE_WRITE) && + !test_bit(FD_DISK_WRITABLE_BIT, &UDRS->flags)) goto out; } mutex_unlock(&open_lock); @@ -3789,7 +3786,8 @@ static int check_floppy_change(struct gendisk *disk) { int drive = (long)disk->private_data; - if (UTESTF(FD_DISK_CHANGED) || UTESTF(FD_VERIFY)) + if (test_bit(FD_DISK_CHANGED_BIT, &UDRS->flags) || + test_bit(FD_VERIFY_BIT, &UDRS->flags)) return 1; if (time_after(jiffies, UDRS->last_checked + UDP->checkfreq)) { @@ -3798,8 +3796,8 @@ static int check_floppy_change(struct gendisk *disk) process_fd_request(); } - if (UTESTF(FD_DISK_CHANGED) || - UTESTF(FD_VERIFY) || + if (test_bit(FD_DISK_CHANGED_BIT, &UDRS->flags) || + test_bit(FD_VERIFY_BIT, &UDRS->flags) || test_bit(drive, &fake_change) || (!ITYPE(UDRS->fd_device) && !current_type[drive])) return 1; @@ -3870,14 +3868,16 @@ static int floppy_revalidate(struct gendisk *disk) int cf; int res = 0; - if (UTESTF(FD_DISK_CHANGED) || - UTESTF(FD_VERIFY) || test_bit(drive, &fake_change) || NO_GEOM) { + if (test_bit(FD_DISK_CHANGED_BIT, &UDRS->flags) || + test_bit(FD_VERIFY_BIT, &UDRS->flags) || + test_bit(drive, &fake_change) || NO_GEOM) { if (usage_count == 0) { pr_info("VFS: revalidate called on non-open device.\n"); return -EFAULT; } lock_fdc(drive, 0); - cf = UTESTF(FD_DISK_CHANGED) || UTESTF(FD_VERIFY); + cf = (test_bit(FD_DISK_CHANGED_BIT, &UDRS->flags) || + test_bit(FD_VERIFY_BIT, &UDRS->flags)); if (!(cf || test_bit(drive, &fake_change) || NO_GEOM)) { process_fd_request(); /*already done by another thread */ return 0; @@ -3887,7 +3887,7 @@ static int floppy_revalidate(struct gendisk *disk) if (buffer_drive == drive) buffer_track = -1; clear_bit(drive, &fake_change); - UCLEARF(FD_DISK_CHANGED); + clear_bit(FD_DISK_CHANGED_BIT, &UDRS->flags); if (cf) UDRS->generation++; if (NO_GEOM) { @@ -4277,9 +4277,9 @@ static int __init floppy_init(void) for (drive = 0; drive < N_DRIVE; drive++) { memset(UDRS, 0, sizeof(*UDRS)); memset(UDRWE, 0, sizeof(*UDRWE)); - USETF(FD_DISK_NEWCHANGE); - USETF(FD_DISK_CHANGED); - USETF(FD_VERIFY); + set_bit(FD_DISK_NEWCHANGE_BIT, &UDRS->flags); + set_bit(FD_DISK_CHANGED_BIT, &UDRS->flags); + set_bit(FD_VERIFY_BIT, &UDRS->flags); UDRS->fd_device = -1; floppy_track_buffer = NULL; max_buffer_sectors = 0; -- cgit v1.2.3 From 4575b55281825d157573bbc5aa28b9144193ddd2 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:55 -0800 Subject: drivers/block/floppy.c: remove most uses of CALL and ECALL macros Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 51 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 35 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 35ce4e3f04dd..36cd33cbe44f 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -3151,8 +3151,10 @@ static inline int raw_cmd_copyout(int cmd, char __user *param, if (ptr->length >= 0 && ptr->length <= ptr->buffer_length) { long length = ptr->buffer_length - ptr->length; - ECALL(fd_copyout(ptr->data, ptr->kernel_data, - length)); + ret = fd_copyout(ptr->data, ptr->kernel_data, + length); + if (ret) + return ret; } } ptr = ptr->next; @@ -3223,9 +3225,12 @@ static inline int raw_cmd_copyin(int cmd, char __user *param, return -ENOMEM; ptr->buffer_length = ptr->length; } - if (ptr->flags & FD_RAW_WRITE) - ECALL(fd_copyin(ptr->data, ptr->kernel_data, - ptr->length)); + if (ptr->flags & FD_RAW_WRITE) { + ret = fd_copyin(ptr->data, ptr->kernel_data, + ptr->length); + if (ret) + return ret; + } rcmd = &(ptr->next); if (!(ptr->flags & FD_RAW_MORE)) return 0; @@ -3329,10 +3334,12 @@ static inline int set_geometry(unsigned int cmd, struct floppy_struct *g, if (lock_fdc(drive, 1)) return -EINTR; - if (cmd != FDDEFPRM) + if (cmd != FDDEFPRM) { /* notice a disk change immediately, else * we lose our settings immediately*/ - CALL(poll_drive(1, FD_RAW_NEED_DISK)); + if (poll_drive(1, FD_RAW_NEED_DISK) == -EINTR) + return -EINTR; + } oldStretch = g->stretch; user_params[drive] = *g; if (buffer_drive == drive) @@ -3413,7 +3420,8 @@ static int get_floppy_geometry(int drive, int type, struct floppy_struct **g) else { if (lock_fdc(drive, 0)) return -EINTR; - CALL(poll_drive(0, 0)); + if (poll_drive(0, 0) == -EINTR) + return -EINTR; process_fd_request(); *g = current_type[drive]; } @@ -3471,7 +3479,9 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, return -EINVAL; /* convert the old style command into a new style command */ - ECALL(normalize_ioctl(&cmd, &size)); + ret = normalize_ioctl(&cmd, &size); + if (ret) + return ret; /* permission checks */ if (((cmd & 0x40) && !FD_IOCTL_ALLOWED) || @@ -3483,8 +3493,11 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, /* copyin */ memset(&inparam, 0, sizeof(inparam)); - if (_IOC_DIR(cmd) & _IOC_WRITE) - ECALL(fd_copyin((void __user *)param, &inparam, size)); + if (_IOC_DIR(cmd) & _IOC_WRITE) { + ret = fd_copyin((void __user *)param, &inparam, size); + if (ret) + return ret; + } switch (cmd) { case FDEJECT: @@ -3513,9 +3526,11 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, case FDDEFPRM: return set_geometry(cmd, &inparam.g, drive, type, bdev); case FDGETPRM: - ECALL(get_floppy_geometry(drive, type, + ret = get_floppy_geometry(drive, type, (struct floppy_struct **) - &outparam)); + &outparam); + if (ret) + return ret; break; case FDMSGON: UDP->flags |= FTD_MSG; @@ -3526,7 +3541,8 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, case FDFMTBEG: if (lock_fdc(drive, 1)) return -EINTR; - CALL(poll_drive(1, FD_RAW_NEED_DISK)); + if (poll_drive(1, FD_RAW_NEED_DISK) == -EINTR) + return -EINTR; ret = UDRS->flags; process_fd_request(); if (ret & FD_VERIFY) @@ -3565,7 +3581,8 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, case FDPOLLDRVSTAT: if (lock_fdc(drive, 1)) return -EINTR; - CALL(poll_drive(1, FD_RAW_NEED_DISK)); + if (poll_drive(1, FD_RAW_NEED_DISK) == -EINTR) + return -EINTR; process_fd_request(); /* fall through */ case FDGETDRVSTAT: @@ -3588,7 +3605,9 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, if (lock_fdc(drive, 1)) return -EINTR; set_floppy(drive); - CALL(i = raw_cmd_ioctl(cmd, (void __user *)param)); + i = raw_cmd_ioctl(cmd, (void __user *)param); + if (i == -EINTR) + return -EINTR; process_fd_request(); return i; case FDTWADDLE: -- cgit v1.2.3 From 86b12b48a29f4795e2e550f510d39931576bdf75 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:56 -0800 Subject: drivers/block/floppy.c: remove [_]COPYIN [_]COPYOUT and ECALL macros Remove these obfuscating macros with hidden returns Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 36cd33cbe44f..665b32f598cb 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -520,7 +520,6 @@ static DECLARE_WAIT_QUEUE_HEAD(command_done); #define NO_SIGNAL (!interruptible || !signal_pending(current)) #define CALL(x) if ((x) == -EINTR) return -EINTR -#define ECALL(x) if ((ret = (x))) return ret; #define _WAIT(x,i) CALL(ret=wait_til_done((x),i)) #define WAIT(x) _WAIT((x),interruptible) #define IWAIT(x) _WAIT((x),1) @@ -3061,14 +3060,6 @@ static inline int fd_copyin(void __user *param, void *address, return copy_from_user(address, param, size) ? -EFAULT : 0; } -#define _COPYOUT(x) (copy_to_user((void __user *)param, &(x), sizeof(x)) \ - ? -EFAULT : 0) -#define _COPYIN(x) (copy_from_user(&(x), (void __user *)param, sizeof(x)) \ - ? -EFAULT : 0) - -#define COPYOUT(x) ECALL(_COPYOUT(x)) -#define COPYIN(x) ECALL(_COPYIN(x)) - static inline const char *drive_name(int type, int drive) { struct floppy_struct *floppy; @@ -3145,7 +3136,9 @@ static inline int raw_cmd_copyout(int cmd, char __user *param, int ret; while (ptr) { - COPYOUT(*ptr); + ret = copy_to_user((void __user *)param, ptr, sizeof(*ptr)); + if (ret) + return -EFAULT; param += sizeof(struct floppy_raw_cmd); if ((ptr->flags & FD_RAW_READ) && ptr->buffer_length) { if (ptr->length >= 0 && @@ -3195,7 +3188,9 @@ static inline int raw_cmd_copyin(int cmd, char __user *param, if (!ptr) return -ENOMEM; *rcmd = ptr; - COPYIN(*ptr); + ret = copy_from_user(ptr, (void __user *)param, sizeof(*ptr)); + if (ret) + return -EFAULT; ptr->next = NULL; ptr->buffer_length = 0; param += sizeof(struct floppy_raw_cmd); -- cgit v1.2.3 From 55eee80c6233c67217a6238dd94f1fc765c723d1 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:57 -0800 Subject: drivers/block/floppy.c: remove macros CALL, WAIT and IWAIT Obfuscating macros with embedded returns are not nice Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 665b32f598cb..4d0ac121b56f 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -519,10 +519,6 @@ static DECLARE_WAIT_QUEUE_HEAD(fdc_wait); static DECLARE_WAIT_QUEUE_HEAD(command_done); #define NO_SIGNAL (!interruptible || !signal_pending(current)) -#define CALL(x) if ((x) == -EINTR) return -EINTR -#define _WAIT(x,i) CALL(ret=wait_til_done((x),i)) -#define WAIT(x) _WAIT((x),interruptible) -#define IWAIT(x) _WAIT((x),1) /* Errors during formatting are counted here. */ static int format_errors; @@ -2268,7 +2264,9 @@ static int do_format(int drive, struct format_descr *tmp_format_req) format_errors = 0; cont = &format_cont; errors = &format_errors; - IWAIT(redo_format); + ret = wait_til_done(redo_format, 1); + if (ret == -EINTR) + return -EINTR; process_fd_request(); return ret; } @@ -2996,8 +2994,6 @@ static struct cont_t poll_cont = { static int poll_drive(int interruptible, int flag) { - int ret; - /* no auto-sense, just clear dcl */ raw_cmd = &default_raw_cmd; raw_cmd->flags = flag; @@ -3006,8 +3002,8 @@ static int poll_drive(int interruptible, int flag) cont = &poll_cont; debug_dcl(DP->flags, "setting NEWCHANGE in poll_drive\n"); set_bit(FD_DISK_NEWCHANGE_BIT, &DRS->flags); - WAIT(floppy_ready); - return ret; + + return wait_til_done(floppy_ready, interruptible); } /* @@ -3038,7 +3034,9 @@ static int user_reset_fdc(int drive, int arg, int interruptible) FDCS->reset = 1; if (FDCS->reset) { cont = &reset_cont; - WAIT(reset_fdc); + ret = wait_til_done(reset_fdc, interruptible); + if (ret == -EINTR) + return -EINTR; } process_fd_request(); return 0; -- cgit v1.2.3 From 74f63f469ed1cee8305840b7bbcee2f99797cd12 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:58 -0800 Subject: drivers/block/floppy.c: convert int 1/0 to bool true/false Various functions use int where bool is appropriate lock_fdc, wait_til_done, poll_drive, user_reset_fdc Convert to bool. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 60 +++++++++++++++++++++++++------------------------- 1 file changed, 30 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 4d0ac121b56f..028d7e4749d0 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -862,7 +862,7 @@ static void set_fdc(int drive) } /* locks the driver */ -static int _lock_fdc(int drive, int interruptible, int line) +static int _lock_fdc(int drive, bool interruptible, int line) { if (!usage_count) { pr_err("Trying to lock fdc while usage count=0 at line %d\n", @@ -2021,7 +2021,7 @@ static struct cont_t intr_cont = { .done = (done_f)empty }; -static int wait_til_done(void (*handler)(void), int interruptible) +static int wait_til_done(void (*handler)(void), bool interruptible) { int ret; @@ -2247,7 +2247,7 @@ static int do_format(int drive, struct format_descr *tmp_format_req) { int ret; - if (lock_fdc(drive, 1)) + if (lock_fdc(drive, true)) return -EINTR; set_floppy(drive); @@ -2264,7 +2264,7 @@ static int do_format(int drive, struct format_descr *tmp_format_req) format_errors = 0; cont = &format_cont; errors = &format_errors; - ret = wait_til_done(redo_format, 1); + ret = wait_til_done(redo_format, true); if (ret == -EINTR) return -EINTR; process_fd_request(); @@ -2980,7 +2980,7 @@ static void do_fd_request(struct request_queue *q) is_alive("do fd request, old request running"); return; } - lock_fdc(MAXTIMEOUT, 0); + lock_fdc(MAXTIMEOUT, false); process_fd_request(); is_alive("do fd request"); } @@ -2992,7 +2992,7 @@ static struct cont_t poll_cont = { .done = generic_done }; -static int poll_drive(int interruptible, int flag) +static int poll_drive(bool interruptible, int flag) { /* no auto-sense, just clear dcl */ raw_cmd = &default_raw_cmd; @@ -3023,7 +3023,7 @@ static struct cont_t reset_cont = { .done = generic_done }; -static int user_reset_fdc(int drive, int arg, int interruptible) +static int user_reset_fdc(int drive, int arg, bool interruptible) { int ret; @@ -3265,7 +3265,7 @@ static int raw_cmd_ioctl(int cmd, void __user *param) raw_cmd = my_raw_cmd; cont = &raw_cmd_cont; - ret = wait_til_done(floppy_start, 1); + ret = wait_til_done(floppy_start, true); debug_dcl(DP->flags, "calling disk change from raw_cmd ioctl\n"); if (ret != -EINTR && FDCS->reset) @@ -3305,7 +3305,7 @@ static inline int set_geometry(unsigned int cmd, struct floppy_struct *g, if (!capable(CAP_SYS_ADMIN)) return -EPERM; mutex_lock(&open_lock); - if (lock_fdc(drive, 1)) { + if (lock_fdc(drive, true)) { mutex_unlock(&open_lock); return -EINTR; } @@ -3325,12 +3325,12 @@ static inline int set_geometry(unsigned int cmd, struct floppy_struct *g, } else { int oldStretch; - if (lock_fdc(drive, 1)) + if (lock_fdc(drive, true)) return -EINTR; if (cmd != FDDEFPRM) { /* notice a disk change immediately, else * we lose our settings immediately*/ - if (poll_drive(1, FD_RAW_NEED_DISK) == -EINTR) + if (poll_drive(true, FD_RAW_NEED_DISK) == -EINTR) return -EINTR; } oldStretch = g->stretch; @@ -3411,9 +3411,9 @@ static int get_floppy_geometry(int drive, int type, struct floppy_struct **g) if (type) *g = &floppy_type[type]; else { - if (lock_fdc(drive, 0)) + if (lock_fdc(drive, false)) return -EINTR; - if (poll_drive(0, 0) == -EINTR) + if (poll_drive(false, 0) == -EINTR) return -EINTR; process_fd_request(); *g = current_type[drive]; @@ -3497,7 +3497,7 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, if (UDRS->fd_ref != 1) /* somebody else has this drive open */ return -EBUSY; - if (lock_fdc(drive, 1)) + if (lock_fdc(drive, true)) return -EINTR; /* do the actual eject. Fails on @@ -3509,7 +3509,7 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, process_fd_request(); return ret; case FDCLRPRM: - if (lock_fdc(drive, 1)) + if (lock_fdc(drive, true)) return -EINTR; current_type[drive] = NULL; floppy_sizes[drive] = MAX_DISK_SIZE << 1; @@ -3532,9 +3532,9 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, UDP->flags &= ~FTD_MSG; return 0; case FDFMTBEG: - if (lock_fdc(drive, 1)) + if (lock_fdc(drive, true)) return -EINTR; - if (poll_drive(1, FD_RAW_NEED_DISK) == -EINTR) + if (poll_drive(true, FD_RAW_NEED_DISK) == -EINTR) return -EINTR; ret = UDRS->flags; process_fd_request(); @@ -3549,7 +3549,7 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, return do_format(drive, &inparam.f); case FDFMTEND: case FDFLUSH: - if (lock_fdc(drive, 1)) + if (lock_fdc(drive, true)) return -EINTR; return invalidate_drive(bdev); case FDSETEMSGTRESH: @@ -3572,9 +3572,9 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, outparam = (const char *)UDP; break; case FDPOLLDRVSTAT: - if (lock_fdc(drive, 1)) + if (lock_fdc(drive, true)) return -EINTR; - if (poll_drive(1, FD_RAW_NEED_DISK) == -EINTR) + if (poll_drive(true, FD_RAW_NEED_DISK) == -EINTR) return -EINTR; process_fd_request(); /* fall through */ @@ -3582,7 +3582,7 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, outparam = (const char *)UDRS; break; case FDRESET: - return user_reset_fdc(drive, (int)param, 1); + return user_reset_fdc(drive, (int)param, true); case FDGETFDCSTAT: outparam = (const char *)UFDCS; break; @@ -3595,7 +3595,7 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, case FDRAWCMD: if (type) return -EINVAL; - if (lock_fdc(drive, 1)) + if (lock_fdc(drive, true)) return -EINTR; set_floppy(drive); i = raw_cmd_ioctl(cmd, (void __user *)param); @@ -3604,7 +3604,7 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, process_fd_request(); return i; case FDTWADDLE: - if (lock_fdc(drive, 1)) + if (lock_fdc(drive, true)) return -EINTR; twaddle(); process_fd_request(); @@ -3803,8 +3803,8 @@ static int check_floppy_change(struct gendisk *disk) return 1; if (time_after(jiffies, UDRS->last_checked + UDP->checkfreq)) { - lock_fdc(drive, 0); - poll_drive(0, 0); + lock_fdc(drive, false); + poll_drive(false, 0); process_fd_request(); } @@ -3887,7 +3887,7 @@ static int floppy_revalidate(struct gendisk *disk) pr_info("VFS: revalidate called on non-open device.\n"); return -EFAULT; } - lock_fdc(drive, 0); + lock_fdc(drive, false); cf = (test_bit(FD_DISK_CHANGED_BIT, &UDRS->flags) || test_bit(FD_VERIFY_BIT, &UDRS->flags)); if (!(cf || test_bit(drive, &fake_change) || NO_GEOM)) { @@ -3907,7 +3907,7 @@ static int floppy_revalidate(struct gendisk *disk) res = __floppy_read_block_0(opened_bdev[drive]); } else { if (cf) - poll_drive(0, FD_RAW_NEED_DISK); + poll_drive(false, FD_RAW_NEED_DISK); process_fd_request(); } } @@ -4164,7 +4164,7 @@ static int floppy_resume(struct device *dev) for (fdc = 0; fdc < N_FDC; fdc++) if (FDCS->address != -1) - user_reset_fdc(-1, FD_RESET_ALWAYS, 0); + user_reset_fdc(-1, FD_RESET_ALWAYS, false); return 0; } @@ -4311,7 +4311,7 @@ static int __init floppy_init(void) if (FDCS->address == -1) continue; FDCS->rawcmd = 2; - if (user_reset_fdc(-1, FD_RESET_ALWAYS, 0)) { + if (user_reset_fdc(-1, FD_RESET_ALWAYS, false)) { /* free ioports reserved by floppy_grab_irq_and_dma() */ floppy_release_regions(fdc); FDCS->address = -1; @@ -4334,7 +4334,7 @@ static int __init floppy_init(void) * properly, so force a reset for the standard FDC clones, * to avoid interrupt garbage. */ - user_reset_fdc(-1, FD_RESET_ALWAYS, 0); + user_reset_fdc(-1, FD_RESET_ALWAYS, false); } fdc = 0; del_timer(&fd_timeout); -- cgit v1.2.3 From c529730a98874fa951995d8a312c7fd606832eda Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:58 -0800 Subject: drivers/block/floppy.c: move leading && and || to preceding line Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 028d7e4749d0..94c7abc5e291 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -639,8 +639,8 @@ static const char *timeout_message; static void is_alive(const char *message) { /* this routine checks whether the floppy driver is "alive" */ - if (test_bit(0, &fdc_busy) && command_status < 2 - && !timer_pending(&fd_timeout)) { + if (test_bit(0, &fdc_busy) && command_status < 2 && + !timer_pending(&fd_timeout)) { DPRINT("timeout handler died: %s\n", message); } } @@ -1769,8 +1769,8 @@ irqreturn_t floppy_interrupt(int irq, void *dev_id) if (do_print) print_result("sensei", inr); max_sensei--; - } while ((ST0 & 0x83) != UNIT(current_drive) && inr == 2 - && max_sensei); + } while ((ST0 & 0x83) != UNIT(current_drive) && + inr == 2 && max_sensei); } if (!handler) { FDCS->reset = 1; -- cgit v1.2.3 From 4d18ef09dfe4d1272446ad55ce5d7b06ff4b9ca8 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:20:59 -0800 Subject: drivers/block/floppy.c: remove #define DEVICE_NAME "floppy" Use it directly in the one place it's used. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 94c7abc5e291..6b75e70ca628 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -250,8 +250,6 @@ static int allowed_drive_mask = 0x33; static int irqdma_allocated; -#define DEVICE_NAME "floppy" - #include #include #include /* for the compatibility eject ioctl */ @@ -312,7 +310,7 @@ static int initialising = 1; #define UFDCS (&fdc_state[FDC(drive)]) #define DPRINT(format, args...) \ - pr_info(DEVICE_NAME "%d: " format, current_drive, ##args) + pr_info("floppy%d: " format, current_drive, ##args) #define PH_HEAD(floppy, head) (((((floppy)->stretch & 2) >> 1) ^ head) << 2) #define STRETCH(floppy) ((floppy)->stretch & FD_STRETCH) -- cgit v1.2.3 From 29f1c7848feb3954939b52fd5b7dca30dbce9426 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:00 -0800 Subject: drivers/block/floppy.c: convert int initialising to bool initialized Don't initialize initialized either. Default is false. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 6b75e70ca628..e080e1930cc1 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -290,7 +290,7 @@ static inline void fallback_on_nodma_alloc(char **addr, size_t l) /* End dma memory related stuff */ static unsigned long fake_change; -static int initialising = 1; +static bool initialized; #define ITYPE(x) (((x) >> 2) & 0x1f) #define TOMINOR(x) ((x & 3) | ((x & 4) << 5)) @@ -1147,7 +1147,7 @@ static int wait_til_ready(void) if (status & STATUS_READY) return status; } - if (!initialising) { + if (initialized) { DPRINT("Getstatus times out (%x) on fdc %d\n", status, fdc); show_floppy(); } @@ -1173,7 +1173,7 @@ static int output_byte(char byte) return 0; } FDCS->reset = 1; - if (!initialising) { + if (initialized) { DPRINT("Unable to send byte %x to FDC. Fdc=%x Status=%x\n", byte, fdc, status); show_floppy(); @@ -1204,10 +1204,9 @@ static int result(void) else break; } - if (!initialising) { - DPRINT - ("get result error. Fdc=%d Last status=%x Read bytes=%d\n", - fdc, status, i); + if (initialized) { + DPRINT("get result error. Fdc=%d Last status=%x Read bytes=%d\n", + fdc, status, i); show_floppy(); } FDCS->reset = 1; @@ -1754,7 +1753,7 @@ irqreturn_t floppy_interrupt(int irq, void *dev_id) * activity. */ - do_print = !handler && print_unex && !initialising; + do_print = !handler && print_unex && initialized; inr = result(); if (do_print) @@ -1882,7 +1881,7 @@ static void floppy_shutdown(unsigned long data) { unsigned long flags; - if (!initialising) + if (initialized) show_floppy(); cancel_activity(); @@ -1894,7 +1893,7 @@ static void floppy_shutdown(unsigned long data) /* avoid dma going to a random drive after shutdown */ - if (!initialising) + if (initialized) DPRINT("floppy timeout called\n"); FDCS->reset = 1; if (cont) { @@ -4337,7 +4336,7 @@ static int __init floppy_init(void) fdc = 0; del_timer(&fd_timeout); current_drive = 0; - initialising = 0; + initialized = true; if (have_no_fdc) { DPRINT("no floppy controllers found\n"); err = have_no_fdc; -- cgit v1.2.3 From 57584c5a3824a15f65d2b065d9f453fc1ae1dab7 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:00 -0800 Subject: drivers/block/floppy.c: add function is_ready_state Used a couple of times, might simplify the code a bit. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index e080e1930cc1..1264102cdcb1 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -782,6 +782,12 @@ static inline int is_selected(int dor, int unit) return ((dor & (0x10 << unit)) && (dor & 3) == unit); } +static bool is_ready_state(int status) +{ + int state = status & (STATUS_READY | STATUS_DIR | STATUS_DMA); + return state == STATUS_READY; +} + static int set_dor(int fdc, char mask, char data) { unsigned char unit; @@ -823,8 +829,10 @@ static void twaddle(void) DRS->select_date = jiffies; } -/* reset all driver information about the current fdc. This is needed after - * a reset, and after a raw command. */ +/* + * Reset all driver information about the current fdc. + * This is needed after a reset, and after a raw command. + */ static void reset_fdc_info(int mode) { int drive; @@ -1162,7 +1170,8 @@ static int output_byte(char byte) if (status < 0) return -1; - if ((status & (STATUS_READY | STATUS_DIR | STATUS_DMA)) == STATUS_READY) { + + if (is_ready_state(status)) { fd_outb(byte, FD_DATA); #ifdef FLOPPY_SANITY_CHECK output_log[output_log_pos].data = byte; @@ -1221,8 +1230,10 @@ static int need_more_output(void) if (status < 0) return -1; - if ((status & (STATUS_READY | STATUS_DIR | STATUS_DMA)) == STATUS_READY) + + if (is_ready_state(status)) return MORE_OUTPUT; + return result(); } -- cgit v1.2.3 From 15b2630c587dcea931f563deb50d617af96b4edb Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:01 -0800 Subject: drivers/block/floppy.c: remove unnecessary return and braces Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 1264102cdcb1..00f3910e2d53 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -1796,10 +1796,8 @@ static void recalibrate_floppy(void) debugt("recalibrate floppy:"); do_floppy = recal_interrupt; output_byte(FD_RECALIBRATE); - if (output_byte(UNIT(current_drive)) < 0) { + if (output_byte(UNIT(current_drive)) < 0) reset_fdc(); - return; - } } /* -- cgit v1.2.3 From 416d8d2888db392c562fb8afaf9136730ef0da9e Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:02 -0800 Subject: drivers/block/floppy.c: remove REPEAT macro Macros with hidden flow changes aren't nice. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 00f3910e2d53..5d8f5510ebc5 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -2885,7 +2885,6 @@ static int make_raw_rw_request(void) static void redo_fd_request(void) { -#define REPEAT {request_done(0); continue; } int drive; int tmp; @@ -2920,7 +2919,8 @@ static void redo_fd_request(void) if (test_bit(current_drive, &fake_change) || test_bit(FD_DISK_CHANGED_BIT, &DRS->flags)) { DPRINT("disk absent or changed during operation\n"); - REPEAT; + request_done(0); + continue; } if (!_floppy) { /* Autodetection */ if (!probing) { @@ -2928,7 +2928,8 @@ static void redo_fd_request(void) if (next_valid_format()) { DPRINT("no autodetectable formats\n"); _floppy = NULL; - REPEAT; + request_done(0); + continue; } } probing = 1; @@ -2949,7 +2950,6 @@ static void redo_fd_request(void) debugt("queue fd request"); return; } -#undef REPEAT } static struct cont_t rw_cont = { -- cgit v1.2.3 From 0da3132f90c01f532dd85c537b5c78a196a11e24 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:03 -0800 Subject: drivers/block/floppy.c: unclutter redo_fd_request logic Change for(;;) with continue; to label: goto label Reduces indentation and adds a bit of clarity. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 105 ++++++++++++++++++++++++------------------------- 1 file changed, 52 insertions(+), 53 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 5d8f5510ebc5..8e24aa3a4e24 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -2892,64 +2892,63 @@ static void redo_fd_request(void) if (current_drive < N_DRIVE) floppy_off(current_drive); - for (;;) { - if (!current_req) { - struct request *req; - - spin_lock_irq(floppy_queue->queue_lock); - req = blk_fetch_request(floppy_queue); - spin_unlock_irq(floppy_queue->queue_lock); - if (!req) { - do_floppy = NULL; - unlock_fdc(); - return; - } - current_req = req; - } - drive = (long)current_req->rq_disk->private_data; - set_fdc(drive); - reschedule_timeout(current_reqD, "redo fd request", 0); - - set_floppy(drive); - raw_cmd = &default_raw_cmd; - raw_cmd->flags = 0; - if (start_motor(redo_fd_request)) +do_request: + if (!current_req) { + struct request *req; + + spin_lock_irq(floppy_queue->queue_lock); + req = blk_fetch_request(floppy_queue); + spin_unlock_irq(floppy_queue->queue_lock); + if (!req) { + do_floppy = NULL; + unlock_fdc(); return; - disk_change(current_drive); - if (test_bit(current_drive, &fake_change) || - test_bit(FD_DISK_CHANGED_BIT, &DRS->flags)) { - DPRINT("disk absent or changed during operation\n"); - request_done(0); - continue; - } - if (!_floppy) { /* Autodetection */ - if (!probing) { - DRS->probed_format = 0; - if (next_valid_format()) { - DPRINT("no autodetectable formats\n"); - _floppy = NULL; - request_done(0); - continue; - } - } - probing = 1; - _floppy = - floppy_type + DP->autodetect[DRS->probed_format]; - } else - probing = 0; - errors = &(current_req->errors); - tmp = make_raw_rw_request(); - if (tmp < 2) { - request_done(tmp); - continue; } + current_req = req; + } + drive = (long)current_req->rq_disk->private_data; + set_fdc(drive); + reschedule_timeout(current_reqD, "redo fd request", 0); - if (test_bit(FD_NEED_TWADDLE_BIT, &DRS->flags)) - twaddle(); - schedule_bh(floppy_start); - debugt("queue fd request"); + set_floppy(drive); + raw_cmd = &default_raw_cmd; + raw_cmd->flags = 0; + if (start_motor(redo_fd_request)) return; + + disk_change(current_drive); + if (test_bit(current_drive, &fake_change) || + test_bit(FD_DISK_CHANGED_BIT, &DRS->flags)) { + DPRINT("disk absent or changed during operation\n"); + request_done(0); + goto do_request; } + if (!_floppy) { /* Autodetection */ + if (!probing) { + DRS->probed_format = 0; + if (next_valid_format()) { + DPRINT("no autodetectable formats\n"); + _floppy = NULL; + request_done(0); + goto do_request; + } + } + probing = 1; + _floppy = floppy_type + DP->autodetect[DRS->probed_format]; + } else + probing = 0; + errors = &(current_req->errors); + tmp = make_raw_rw_request(); + if (tmp < 2) { + request_done(tmp); + goto do_request; + } + + if (test_bit(FD_NEED_TWADDLE_BIT, &DRS->flags)) + twaddle(); + schedule_bh(floppy_start); + debugt("queue fd request"); + return; } static struct cont_t rw_cont = { -- cgit v1.2.3 From 73507e6cd8dc6cd98a39164a9b775c7092faddb4 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:03 -0800 Subject: drivers/block/floppy.c: remove unnecessary argument from [__]reschedule_timeout Prior to patch "drivers/block/floppy.c: Use pr_" only reschedule_timeout(,"request done"...) printed a numeric value after a reschedule_timeout event message. Restore that behavior and remove the now unnecessary argument. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 8e24aa3a4e24..4de027deffb9 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -668,7 +668,7 @@ static int output_log_pos; #define current_reqD -1 #define MAXTIMEOUT -2 -static void __reschedule_timeout(int drive, const char *message, int marg) +static void __reschedule_timeout(int drive, const char *message) { if (drive == current_reqD) drive = current_drive; @@ -680,16 +680,16 @@ static void __reschedule_timeout(int drive, const char *message, int marg) fd_timeout.expires = jiffies + UDP->timeout; add_timer(&fd_timeout); if (UDP->flags & FD_DEBUG) - DPRINT("reschedule timeout %s %d\n", message, marg); + DPRINT("reschedule timeout %s\n", message); timeout_message = message; } -static void reschedule_timeout(int drive, const char *message, int marg) +static void reschedule_timeout(int drive, const char *message) { unsigned long flags; spin_lock_irqsave(&floppy_lock, flags); - __reschedule_timeout(drive, message, marg); + __reschedule_timeout(drive, message); spin_unlock_irqrestore(&floppy_lock, flags); } @@ -900,7 +900,7 @@ static int _lock_fdc(int drive, bool interruptible, int line) } command_status = FD_COMMAND_NONE; - __reschedule_timeout(drive, "lock fdc", 0); + __reschedule_timeout(drive, "lock fdc"); set_fdc(drive); return 0; } @@ -1983,7 +1983,7 @@ static void floppy_ready(void) static void floppy_start(void) { - reschedule_timeout(current_reqD, "floppy start", 0); + reschedule_timeout(current_reqD, "floppy start"); scandrives(); debug_dcl(DP->flags, "setting NEWCHANGE in floppy_start\n"); @@ -2007,7 +2007,7 @@ static void floppy_start(void) static void do_wakeup(void) { - reschedule_timeout(MAXTIMEOUT, "do wakeup", 0); + reschedule_timeout(MAXTIMEOUT, "do wakeup"); cont = NULL; command_status += 2; wake_up(&command_done); @@ -2306,9 +2306,11 @@ static void request_done(int uptodate) struct request *req = current_req; unsigned long flags; int block; + char msg[sizeof("request done ") + sizeof(int) * 3]; probing = 0; - reschedule_timeout(MAXTIMEOUT, "request done", uptodate); + snprintf(msg, sizeof(msg), "request done %d", uptodate); + reschedule_timeout(MAXTIMEOUT, msg); if (!req) { pr_info("floppy.c: no request in request_done\n"); @@ -2908,7 +2910,7 @@ do_request: } drive = (long)current_req->rq_disk->private_data; set_fdc(drive); - reschedule_timeout(current_reqD, "redo fd request", 0); + reschedule_timeout(current_reqD, "redo fd request"); set_floppy(drive); raw_cmd = &default_raw_cmd; @@ -4254,7 +4256,7 @@ static int __init floppy_init(void) else floppy_sizes[i] = MAX_DISK_SIZE << 1; - reschedule_timeout(MAXTIMEOUT, "floppy init", MAXTIMEOUT); + reschedule_timeout(MAXTIMEOUT, "floppy init"); config_types(); for (i = 0; i < N_FDC; i++) { -- cgit v1.2.3 From 1a23d133359eec2297ff4c72c260ccacb156d883 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:04 -0800 Subject: drivers/block/floppy.c: remove #define FLOPPY_SANITY_CHECK The code could not be compiled without the #define, so just remove it and the #ifdef/#endif lines. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 35 +---------------------------------- 1 file changed, 1 insertion(+), 34 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 4de027deffb9..c2d9c59f0e64 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -144,7 +144,6 @@ * Better audit of register_blkdev. */ -#define FLOPPY_SANITY_CHECK #undef FLOPPY_SILENT_DCL_CLEAR #define REALLY_SLOW_IO @@ -633,7 +632,6 @@ static DEFINE_TIMER(fd_timeout, floppy_shutdown, 0, 0); static const char *timeout_message; -#ifdef FLOPPY_SANITY_CHECK static void is_alive(const char *message) { /* this routine checks whether the floppy driver is "alive" */ @@ -642,12 +640,9 @@ static void is_alive(const char *message) DPRINT("timeout handler died: %s\n", message); } } -#endif static void (*do_floppy)(void) = NULL; -#ifdef FLOPPY_SANITY_CHECK - #define OLOGSIZE 20 static void (*lasthandler)(void); @@ -663,7 +658,6 @@ static struct output_log { } output_log[OLOGSIZE]; static int output_log_pos; -#endif #define current_reqD -1 #define MAXTIMEOUT -2 @@ -733,7 +727,6 @@ static int disk_change(int drive) { int fdc = FDC(drive); -#ifdef FLOPPY_SANITY_CHECK if (time_before(jiffies, UDRS->select_date + UDP->select_delay)) DPRINT("WARNING disk change called early\n"); if (!(FDCS->dor & (0x10 << UNIT(drive))) || @@ -742,7 +735,6 @@ static int disk_change(int drive) DPRINT("drive=%d fdc=%d dor=%x\n", drive, FDC(drive), (unsigned int)FDCS->dor); } -#endif debug_dcl(UDP->flags, "checking disk change line for drive %d\n", drive); @@ -1095,7 +1087,6 @@ static void setup_DMA(void) { unsigned long f; -#ifdef FLOPPY_SANITY_CHECK if (raw_cmd->length == 0) { int i; @@ -1113,7 +1104,6 @@ static void setup_DMA(void) FDCS->reset = 1; return; } -#endif f = claim_dma_lock(); fd_disable_dma(); #ifdef fd_dma_setup @@ -1173,12 +1163,10 @@ static int output_byte(char byte) if (is_ready_state(status)) { fd_outb(byte, FD_DATA); -#ifdef FLOPPY_SANITY_CHECK output_log[output_log_pos].data = byte; output_log[output_log_pos].status = status; output_log[output_log_pos].jiffies = jiffies; output_log_pos = (output_log_pos + 1) % OLOGSIZE; -#endif return 0; } FDCS->reset = 1; @@ -1202,10 +1190,8 @@ static int result(void) break; status &= STATUS_DIR | STATUS_READY | STATUS_BUSY | STATUS_DMA; if ((status & ~STATUS_BUSY) == STATUS_READY) { -#ifdef FLOPPY_SANITY_CHECK resultjiffies = jiffies; resultsize = i; -#endif return i; } if (status == (STATUS_DIR | STATUS_READY | STATUS_BUSY)) @@ -1853,7 +1839,6 @@ static void show_floppy(void) jiffies, interruptjiffies, jiffies - interruptjiffies, lasthandler); -#ifdef FLOPPY_SANITY_CHECK pr_info("timeout_message=%s\n", timeout_message); pr_info("last output bytes:\n"); for (i = 0; i < OLOGSIZE; i++) @@ -1865,7 +1850,6 @@ static void show_floppy(void) pr_info("last redo_fd_request at %lu\n", lastredo); print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, reply_buffer, resultsize, true); -#endif pr_info("status=%x\n", fd_inb(FD_STATUS)); pr_info("fdc_busy=%lu\n", fdc_busy); @@ -2381,7 +2365,6 @@ static void rw_interrupt(void) R_HEAD - HEAD) * SECT_PER_TRACK + R_SECTOR - SECTOR + eoc) << SIZECODE >> 2; -#ifdef FLOPPY_SANITY_CHECK if (nr_sectors / ssize > DIV_ROUND_UP(in_sector_offset + current_count_sectors, ssize)) { DPRINT("long rw: %x instead of %lx\n", @@ -2394,7 +2377,6 @@ static void rw_interrupt(void) SECT_PER_TRACK, fsector_t, ssize); pr_info("in_sector_offset=%d\n", in_sector_offset); } -#endif nr_sectors -= in_sector_offset; INFBOUND(nr_sectors, 0); @@ -2499,7 +2481,6 @@ static void copy_buffer(int ssize, int max_sector, int max_sector_2) blk_rq_sectors(current_req)); remaining = current_count_sectors << 9; -#ifdef FLOPPY_SANITY_CHECK if (remaining > blk_rq_bytes(current_req) && CT(COMMAND) == FD_WRITE) { DPRINT("in copy buffer\n"); pr_info("current_count_sectors=%ld\n", current_count_sectors); @@ -2511,7 +2492,6 @@ static void copy_buffer(int ssize, int max_sector, int max_sector_2) pr_info("max_sector=%d\n", max_sector); pr_info("ssize=%d\n", ssize); } -#endif buffer_max = max(max_sector, buffer_max); @@ -2527,7 +2507,6 @@ static void copy_buffer(int ssize, int max_sector, int max_sector_2) SUPBOUND(size, remaining); buffer = page_address(bv->bv_page) + bv->bv_offset; -#ifdef FLOPPY_SANITY_CHECK if (dma_buffer + size > floppy_track_buffer + (max_buffer_sectors << 10) || dma_buffer < floppy_track_buffer) { @@ -2545,7 +2524,7 @@ static void copy_buffer(int ssize, int max_sector, int max_sector_2) } if (((unsigned long)buffer) % 512) DPRINT("%p buffer not aligned\n", buffer); -#endif + if (CT(COMMAND) == FD_READ) memcpy(buffer, dma_buffer, size); else @@ -2554,13 +2533,11 @@ static void copy_buffer(int ssize, int max_sector, int max_sector_2) remaining -= size; dma_buffer += size; } -#ifdef FLOPPY_SANITY_CHECK if (remaining) { if (remaining > 0) max_sector -= remaining >> 9; DPRINT("weirdness: remaining %d\n", remaining >> 9); } -#endif } /* work around a bug in pseudo DMA @@ -2580,13 +2557,11 @@ static void virtualdmabug_workaround(void) hard_sectors = raw_cmd->length >> (7 + SIZECODE); end_sector = SECTOR + hard_sectors - 1; -#ifdef FLOPPY_SANITY_CHECK if (end_sector > SECT_PER_TRACK) { pr_info("too many sectors %d > %d\n", end_sector, SECT_PER_TRACK); return; } -#endif SECT_PER_TRACK = end_sector; /* make sure SECT_PER_TRACK * points to end of transfer */ @@ -2805,10 +2780,8 @@ static int make_raw_rw_request(void) * if we get here, we know that the write * is either aligned or the data already in the buffer * (buffer will be overwritten) */ -#ifdef FLOPPY_SANITY_CHECK if (in_sector_offset && buffer_track == -1) DPRINT("internal error offset !=0 on write\n"); -#endif buffer_track = raw_cmd->track; buffer_drive = current_drive; copy_buffer(ssize, max_sector, @@ -2822,7 +2795,6 @@ static int make_raw_rw_request(void) raw_cmd->length = in_sector_offset + current_count_sectors; raw_cmd->length = ((raw_cmd->length - 1) | (ssize - 1)) + 1; raw_cmd->length <<= 9; -#ifdef FLOPPY_SANITY_CHECK if ((raw_cmd->length < current_count_sectors << 9) || (raw_cmd->kernel_data != current_req->buffer && CT(COMMAND) == FD_WRITE && @@ -2879,7 +2851,6 @@ static int make_raw_rw_request(void) DPRINT("zero dma transfer attempted from make_raw_request\n"); return 0; } -#endif virtualdmabug_workaround(); return 2; @@ -4526,10 +4497,8 @@ cleanup: static void floppy_release_irq_and_dma(void) { int old_fdc; -#ifdef FLOPPY_SANITY_CHECK #ifndef __sparc__ int drive; -#endif #endif long tmpsize; unsigned long tmpaddr; @@ -4561,7 +4530,6 @@ static void floppy_release_irq_and_dma(void) buffer_min = buffer_max = -1; fd_dma_mem_free(tmpaddr, tmpsize); } -#ifdef FLOPPY_SANITY_CHECK #ifndef __sparc__ for (drive = 0; drive < N_FDC * 4; drive++) if (timer_pending(motor_off_timer + drive)) @@ -4574,7 +4542,6 @@ static void floppy_release_irq_and_dma(void) pr_info("auxiliary floppy timer still active\n"); if (work_pending(&floppy_work)) pr_info("work still pending\n"); -#endif old_fdc = fdc; for (fdc = 0; fdc < N_FDC; fdc++) if (FDCS->address != -1) -- cgit v1.2.3 From 891eda80a5227a12956d7997baf9f4b54a9aa4f9 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:05 -0800 Subject: drivers/block/floppy.c: DPRINT neatening Move DPRINT macro definition above 1st use Consolidate a format string (>80 columns) Add a newline to an unterminated message Comment neatened Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index c2d9c59f0e64..613c279afcf1 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -149,8 +149,11 @@ #define REALLY_SLOW_IO #define DEBUGT 2 -#define DCL_DEBUG /* debug disk change line */ +#define DPRINT(format, args...) \ + pr_info("floppy%d: " format, current_drive, ##args) + +#define DCL_DEBUG /* debug disk change line */ #ifdef DCL_DEBUG #define debug_dcl(test, fmt, args...) \ do { if ((test) & FD_DEBUG) DPRINT(fmt, ##args); } while (0) @@ -159,7 +162,6 @@ do { if (0) DPRINT(fmt, ##args); } while (0) #endif - /* do print messages for unexpected interrupts */ static int print_unex = 1; #include @@ -308,9 +310,6 @@ static bool initialized; #define UDRWE (&write_errors[drive]) #define UFDCS (&fdc_state[FDC(drive)]) -#define DPRINT(format, args...) \ - pr_info("floppy%d: " format, current_drive, ##args) - #define PH_HEAD(floppy, head) (((((floppy)->stretch & 2) >> 1) ^ head) << 2) #define STRETCH(floppy) ((floppy)->stretch & FD_STRETCH) @@ -345,7 +344,7 @@ static bool initialized; */ #define MAX_REPLIES 16 static unsigned char reply_buffer[MAX_REPLIES]; -static int inr; /* size of reply buffer, when called from interrupt */ +static int inr; /* size of reply buffer, when called from interrupt */ #define ST0 (reply_buffer[0]) #define ST1 (reply_buffer[1]) #define ST2 (reply_buffer[2]) @@ -755,8 +754,7 @@ static int disk_change(int drive) if (UDRS->keep_data >= 0) { if ((UDP->flags & FTD_MSG) && current_type[drive] != NULL) - DPRINT("Disk type is undefined after " - "disk change\n"); + DPRINT("Disk type is undefined after disk change\n"); current_type[drive] = NULL; floppy_sizes[TOMINOR(drive)] = MAX_DISK_SIZE << 1; } @@ -1447,7 +1445,7 @@ static int interpret_errors(void) char bad; if (inr != 7) { - DPRINT("-- FDC reply error"); + DPRINT("-- FDC reply error\n"); FDCS->reset = 1; return 1; } -- cgit v1.2.3 From 275176bc2a7bbd5c4446ba12b8f4353a69012053 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:06 -0800 Subject: drivers/block/floppy.c: use __func__ where appropriate Add and use __func__ to is_alive. Use __func__ in some DPRINTs. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 613c279afcf1..c500c5cc34ee 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -631,12 +631,12 @@ static DEFINE_TIMER(fd_timeout, floppy_shutdown, 0, 0); static const char *timeout_message; -static void is_alive(const char *message) +static void is_alive(const char *func, const char *message) { /* this routine checks whether the floppy driver is "alive" */ if (test_bit(0, &fdc_busy) && command_status < 2 && !timer_pending(&fd_timeout)) { - DPRINT("timeout handler died: %s\n", message); + DPRINT("%s: timeout handler died. %s\n", func, message); } } @@ -1734,7 +1734,7 @@ irqreturn_t floppy_interrupt(int irq, void *dev_id) pr_info("DOR0=%x\n", fdc_state[0].dor); pr_info("floppy interrupt on bizarre fdc %d\n", fdc); pr_info("handler=%p\n", handler); - is_alive("bizarre fdc"); + is_alive(__func__, "bizarre fdc"); return IRQ_NONE; } @@ -1769,7 +1769,7 @@ irqreturn_t floppy_interrupt(int irq, void *dev_id) return IRQ_NONE; } schedule_bh(handler); - is_alive("normal interrupt end"); + is_alive(__func__, "normal interrupt end"); /* FIXME! Was it really for us? */ return IRQ_HANDLED; @@ -1894,7 +1894,7 @@ static void floppy_shutdown(unsigned long data) pr_info("no cont in shutdown!\n"); process_fd_request(); } - is_alive("floppy shutdown"); + is_alive(__func__, ""); } /* start motor, check media-changed condition and write protection */ @@ -2027,7 +2027,7 @@ static int wait_til_done(void (*handler)(void), bool interruptible) if (command_status >= 2 || !NO_SIGNAL) break; - is_alive("wait_til_done"); + is_alive(__func__, ""); schedule(); } @@ -2602,7 +2602,7 @@ static int make_raw_rw_request(void) raw_cmd->flags |= FD_RAW_WRITE; COMMAND = FM_MODE(_floppy, FD_WRITE); } else { - DPRINT("make_raw_rw_request: unknown command\n"); + DPRINT("%s: unknown command\n", __func__); return 0; } @@ -2743,7 +2743,7 @@ static int make_raw_rw_request(void) raw_cmd->kernel_data = current_req->buffer; raw_cmd->length = current_count_sectors << 9; if (raw_cmd->length == 0) { - DPRINT("zero dma transfer attempted from make_raw_request\n"); + DPRINT("%s: zero dma transfer attempted\n", __func__); DPRINT("indirect=%d direct=%d fsector_t=%d\n", indirect, direct, fsector_t); return 0; @@ -2938,7 +2938,7 @@ static void process_fd_request(void) static void do_fd_request(struct request_queue *q) { if (max_buffer_sectors == 0) { - pr_info("VFS: do_fd_request called on non-open device\n"); + pr_info("VFS: %s called on non-open device\n", __func__); return; } @@ -2953,12 +2953,12 @@ static void do_fd_request(struct request_queue *q) if (test_bit(0, &fdc_busy)) { /* fdc busy, this new request will be treated when the current one is done */ - is_alive("do fd request, old request running"); + is_alive(__func__, "old request running"); return; } lock_fdc(MAXTIMEOUT, false); process_fd_request(); - is_alive("do fd request"); + is_alive(__func__, ""); } static struct cont_t poll_cont = { -- cgit v1.2.3 From 1ebddd85a6a6ad793eca82d65fba4573d0e28042 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:07 -0800 Subject: drivers/block/floppy.c: use %pf in logging messages Print the function name not the pointer address where useful and possible Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index c500c5cc34ee..46536b716acc 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -908,7 +908,7 @@ static inline void unlock_fdc(void) DPRINT("FDC access conflict!\n"); if (do_floppy) - DPRINT("device interrupt still active at FDC release: %p!\n", + DPRINT("device interrupt still active at FDC release: %pf!\n", do_floppy); command_status = FD_COMMAND_NONE; spin_lock_irqsave(&floppy_lock, flags); @@ -1733,7 +1733,7 @@ irqreturn_t floppy_interrupt(int irq, void *dev_id) /* we don't even know which FDC is the culprit */ pr_info("DOR0=%x\n", fdc_state[0].dor); pr_info("floppy interrupt on bizarre fdc %d\n", fdc); - pr_info("handler=%p\n", handler); + pr_info("handler=%pf\n", handler); is_alive(__func__, "bizarre fdc"); return IRQ_NONE; } @@ -1792,7 +1792,7 @@ static void reset_interrupt(void) debugt("reset interrupt:"); result(); /* get the status ready for set_fdc */ if (FDCS->reset) { - pr_info("reset set in interrupt, calling %p\n", cont->error); + pr_info("reset set in interrupt, calling %pf\n", cont->error); cont->error(); /* a reset just after a reset. BAD! */ } cont->redo(); @@ -1833,7 +1833,7 @@ static void show_floppy(void) pr_info("\n"); pr_info("floppy driver state\n"); pr_info("-------------------\n"); - pr_info("now=%lu last interrupt=%lu diff=%lu last called handler=%p\n", + pr_info("now=%lu last interrupt=%lu diff=%lu last called handler=%pf\n", jiffies, interruptjiffies, jiffies - interruptjiffies, lasthandler); @@ -1852,13 +1852,13 @@ static void show_floppy(void) pr_info("status=%x\n", fd_inb(FD_STATUS)); pr_info("fdc_busy=%lu\n", fdc_busy); if (do_floppy) - pr_info("do_floppy=%p\n", do_floppy); + pr_info("do_floppy=%pf\n", do_floppy); if (work_pending(&floppy_work)) - pr_info("floppy_work.func=%p\n", floppy_work.func); + pr_info("floppy_work.func=%pf\n", floppy_work.func); if (timer_pending(&fd_timer)) - pr_info("fd_timer.function=%p\n", fd_timer.function); + pr_info("fd_timer.function=%pf\n", fd_timer.function); if (timer_pending(&fd_timeout)) { - pr_info("timer_function=%p\n", fd_timeout.function); + pr_info("timer_function=%pf\n", fd_timeout.function); pr_info("expires=%lu\n", fd_timeout.expires - jiffies); pr_info("now=%lu\n", jiffies); } -- cgit v1.2.3 From ce2f11fe784f7999b82c7a71cdbcb86ad2653def Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:08 -0800 Subject: drivers/block/floppy.c: remove some unnecessary casting Remove char/void __user * use. Remove kmalloc cast. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 46536b716acc..4807203827cc 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -3104,13 +3104,13 @@ static struct cont_t raw_cmd_cont = { .done = raw_cmd_done }; -static inline int raw_cmd_copyout(int cmd, char __user *param, +static inline int raw_cmd_copyout(int cmd, void __user *param, struct floppy_raw_cmd *ptr) { int ret; while (ptr) { - ret = copy_to_user((void __user *)param, ptr, sizeof(*ptr)); + ret = copy_to_user(param, ptr, sizeof(*ptr)); if (ret) return -EFAULT; param += sizeof(struct floppy_raw_cmd); @@ -3148,7 +3148,7 @@ static void raw_cmd_free(struct floppy_raw_cmd **ptr) } } -static inline int raw_cmd_copyin(int cmd, char __user *param, +static inline int raw_cmd_copyin(int cmd, void __user *param, struct floppy_raw_cmd **rcmd) { struct floppy_raw_cmd *ptr; @@ -3157,12 +3157,11 @@ static inline int raw_cmd_copyin(int cmd, char __user *param, *rcmd = NULL; while (1) { - ptr = (struct floppy_raw_cmd *) - kmalloc(sizeof(struct floppy_raw_cmd), GFP_USER); + ptr = kmalloc(sizeof(struct floppy_raw_cmd), GFP_USER); if (!ptr) return -ENOMEM; *rcmd = ptr; - ret = copy_from_user(ptr, (void __user *)param, sizeof(*ptr)); + ret = copy_from_user(ptr, param, sizeof(*ptr)); if (ret) return -EFAULT; ptr->next = NULL; -- cgit v1.2.3 From 7f2527174ab1ee7f4550c91be47b3f843ff1316d Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:08 -0800 Subject: drivers/block/floppy.c: convert raw_cmd_copyin from while(1) to label: goto Reduces indent. Makes a bit more readable and intelligible. Return value now at bottom of function. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 73 ++++++++++++++++++++++++++------------------------ 1 file changed, 38 insertions(+), 35 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 4807203827cc..b7190fd582f4 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -3126,6 +3126,7 @@ static inline int raw_cmd_copyout(int cmd, void __user *param, } ptr = ptr->next; } + return 0; } @@ -3156,18 +3157,19 @@ static inline int raw_cmd_copyin(int cmd, void __user *param, int i; *rcmd = NULL; - while (1) { - ptr = kmalloc(sizeof(struct floppy_raw_cmd), GFP_USER); - if (!ptr) - return -ENOMEM; - *rcmd = ptr; - ret = copy_from_user(ptr, param, sizeof(*ptr)); - if (ret) - return -EFAULT; - ptr->next = NULL; - ptr->buffer_length = 0; - param += sizeof(struct floppy_raw_cmd); - if (ptr->cmd_count > 33) + +loop: + ptr = kmalloc(sizeof(struct floppy_raw_cmd), GFP_USER); + if (!ptr) + return -ENOMEM; + *rcmd = ptr; + ret = copy_from_user(ptr, param, sizeof(*ptr)); + if (ret) + return -EFAULT; + ptr->next = NULL; + ptr->buffer_length = 0; + param += sizeof(struct floppy_raw_cmd); + if (ptr->cmd_count > 33) /* the command may now also take up the space * initially intended for the reply & the * reply count. Needed for long 82078 commands @@ -3176,34 +3178,35 @@ static inline int raw_cmd_copyin(int cmd, void __user *param, * 16 bytes for a structure, you'll one day * discover that you really need 17... */ + return -EINVAL; + + for (i = 0; i < 16; i++) + ptr->reply[i] = 0; + ptr->resultcode = 0; + ptr->kernel_data = NULL; + + if (ptr->flags & (FD_RAW_READ | FD_RAW_WRITE)) { + if (ptr->length <= 0) return -EINVAL; + ptr->kernel_data = (char *)fd_dma_mem_alloc(ptr->length); + fallback_on_nodma_alloc(&ptr->kernel_data, ptr->length); + if (!ptr->kernel_data) + return -ENOMEM; + ptr->buffer_length = ptr->length; + } + if (ptr->flags & FD_RAW_WRITE) { + ret = fd_copyin(ptr->data, ptr->kernel_data, ptr->length); + if (ret) + return ret; + } - for (i = 0; i < 16; i++) - ptr->reply[i] = 0; - ptr->resultcode = 0; - ptr->kernel_data = NULL; - - if (ptr->flags & (FD_RAW_READ | FD_RAW_WRITE)) { - if (ptr->length <= 0) - return -EINVAL; - ptr->kernel_data = - (char *)fd_dma_mem_alloc(ptr->length); - fallback_on_nodma_alloc(&ptr->kernel_data, ptr->length); - if (!ptr->kernel_data) - return -ENOMEM; - ptr->buffer_length = ptr->length; - } - if (ptr->flags & FD_RAW_WRITE) { - ret = fd_copyin(ptr->data, ptr->kernel_data, - ptr->length); - if (ret) - return ret; - } + if (ptr->flags & FD_RAW_MORE) { rcmd = &(ptr->next); - if (!(ptr->flags & FD_RAW_MORE)) - return 0; ptr->rate &= 0x43; + goto loop; } + + return 0; } static int raw_cmd_ioctl(int cmd, void __user *param) -- cgit v1.2.3 From ded2863d09208b27baa4a6ad95bb7e5539e48c05 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:09 -0800 Subject: drivers/block/floppy.c: add __func__ to debugt Make debugt messages a little neater. Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index b7190fd582f4..1fe5225a3829 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -616,14 +616,14 @@ static inline void set_debugt(void) debugtimer = jiffies; } -static inline void debugt(const char *message) +static inline void debugt(const char *func, const char *msg) { if (DP->flags & DEBUGT) - pr_info("%s dtime=%lu\n", message, jiffies - debugtimer); + pr_info("%s:%s dtime=%lu\n", func, msg, jiffies - debugtimer); } #else static inline void set_debugt(void) { } -static inline void debugt(const char *message) { } +static inline void debugt(const char *func, const char *msg) { } #endif /* DEBUGT */ typedef void (*timeout_fn)(unsigned long); @@ -1533,7 +1533,7 @@ static void setup_rw_floppy(void) for (i = 0; i < raw_cmd->cmd_count; i++) r |= output_byte(raw_cmd->cmd[i]); - debugt("rw_command: "); + debugt(__func__, "rw_command"); if (r) { cont->error(); @@ -1556,7 +1556,7 @@ static int blind_seek; */ static void seek_interrupt(void) { - debugt("seek interrupt:"); + debugt(__func__, ""); if (inr != 2 || (ST0 & 0xF8) != 0x20) { DPRINT("seek failed\n"); DRS->track = NEED_2_RECAL; @@ -1604,7 +1604,7 @@ static void seek_floppy(void) blind_seek = 0; - debug_dcl(DP->flags, "calling disk change from seek\n"); + debug_dcl(DP->flags, "calling disk change from %s\n", __func__); if (!test_bit(FD_DISK_NEWCHANGE_BIT, &DRS->flags) && disk_change(current_drive) && (raw_cmd->flags & FD_RAW_NEED_DISK)) { @@ -1653,18 +1653,18 @@ static void seek_floppy(void) reset_fdc(); return; } - debugt("seek command:"); + debugt(__func__, ""); } static void recal_interrupt(void) { - debugt("recal interrupt:"); + debugt(__func__, ""); if (inr != 2) FDCS->reset = 1; else if (ST0 & ST0_ECE) { switch (DRS->track) { case NEED_1_RECAL: - debugt("recal interrupt need 1 recal:"); + debugt(__func__, "need 1 recal"); /* after a second recalibrate, we still haven't * reached track 0. Probably no drive. Raise an * error, as failing immediately might upset @@ -1673,7 +1673,7 @@ static void recal_interrupt(void) cont->redo(); return; case NEED_2_RECAL: - debugt("recal interrupt need 2 recal:"); + debugt(__func__, "need 2 recal"); /* If we already did a recalibrate, * and we are not at track 0, this * means we have moved. (The only way @@ -1687,7 +1687,7 @@ static void recal_interrupt(void) DRS->select_date = jiffies; /* fall through */ default: - debugt("recal interrupt default:"); + debugt(__func__, "default"); /* Recalibrate moves the head by at * most 80 steps. If after one * recalibrate we don't have reached @@ -1777,7 +1777,7 @@ irqreturn_t floppy_interrupt(int irq, void *dev_id) static void recalibrate_floppy(void) { - debugt("recalibrate floppy:"); + debugt(__func__, ""); do_floppy = recal_interrupt; output_byte(FD_RECALIBRATE); if (output_byte(UNIT(current_drive)) < 0) @@ -1789,7 +1789,7 @@ static void recalibrate_floppy(void) */ static void reset_interrupt(void) { - debugt("reset interrupt:"); + debugt(__func__, ""); result(); /* get the status ready for set_fdc */ if (FDCS->reset) { pr_info("reset set in interrupt, calling %pf\n", cont->error); @@ -2221,7 +2221,7 @@ static void redo_format(void) buffer_track = -1; setup_format_params(format_req.track << STRETCH(_floppy)); floppy_start(); - debugt("queue format request"); + debugt(__func__, "queue format request"); } static struct cont_t format_cont = { @@ -2918,7 +2918,7 @@ do_request: if (test_bit(FD_NEED_TWADDLE_BIT, &DRS->flags)) twaddle(); schedule_bh(floppy_start); - debugt("queue fd request"); + debugt(__func__, "queue fd request"); return; } -- cgit v1.2.3 From 712e1de43ed572886d6913a86eee5e73b7de4318 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:10 -0800 Subject: drivers/block/floppy.c: remove obfuscating CODE2SIZE macro Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 1fe5225a3829..0b659bb02ad4 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -2143,7 +2143,6 @@ static void format_interrupt(void) cont->redo(); } -#define CODE2SIZE (ssize = ((1 << SIZECODE) + 3) >> 2) #define FM_MODE(x, y) ((y) & ~(((x)->rate & 0x80) >> 1)) #define CT(x) ((x) | 0xc0) @@ -2347,7 +2346,7 @@ static void rw_interrupt(void) DRS->first_read_date = jiffies; nr_sectors = 0; - CODE2SIZE; + ssize = DIV_ROUND_UP(1 << SIZECODE, 4); if (ST1 & ST1_EOC) eoc = 1; @@ -2647,7 +2646,7 @@ static int make_raw_rw_request(void) raw_cmd->track = TRACK << STRETCH(_floppy); DR_SELECT = UNIT(current_drive) + PH_HEAD(_floppy, HEAD); GAP = _floppy->gap; - CODE2SIZE; + ssize = DIV_ROUND_UP(1 << SIZECODE, 4); SECT_PER_TRACK = _floppy->sect << 2 >> SIZECODE; SECTOR = ((fsector_t % _floppy->sect) << 2 >> SIZECODE) + FD_SECTBASE(_floppy); -- cgit v1.2.3 From 0aad92cfea6fec14bd57dd9c283cc6eb023c97bd Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:10 -0800 Subject: drivers/block/floppy.c: remove misleading, used once FD_IOCTL_ALLOWED macro Just code the test directly Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 0b659bb02ad4..67e8e5f366c5 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -3420,8 +3420,6 @@ static int fd_getgeo(struct block_device *bdev, struct hd_geometry *geo) static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, unsigned long param) { -#define FD_IOCTL_ALLOWED (mode & (FMODE_WRITE|FMODE_WRITE_IOCTL)) - int drive = (long)bdev->bd_disk->private_data; int type = ITYPE(UDRS->fd_device); int i; @@ -3454,7 +3452,7 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, return ret; /* permission checks */ - if (((cmd & 0x40) && !FD_IOCTL_ALLOWED) || + if (((cmd & 0x40) && !(mode & (FMODE_WRITE | FMODE_WRITE_IOCTL))) || ((cmd & 0x80) && !capable(CAP_SYS_ADMIN))) return -EPERM; -- cgit v1.2.3 From 724ee626f38feaea215a11790e1a0cb5d83b0628 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 10 Mar 2010 15:21:11 -0800 Subject: drivers/block/floppy.c: remove unnecessary casting in fd_ioctl Convert outparam to const void *. Cast outparam to const char * for strlen(). Signed-off-by: Joe Perches Cc: Stephen Hemminger Cc: Jens Axboe Cc: Marcin Slusarz Cc: Bartlomiej Zolnierkiewicz Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/block/floppy.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 67e8e5f366c5..90c4038702da 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -3431,7 +3431,7 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, struct floppy_max_errors max_errors; struct floppy_drive_params dp; } inparam; /* parameters coming from user space */ - const char *outparam; /* parameters passed back to user space */ + const void *outparam; /* parameters passed back to user space */ /* convert compatibility eject ioctls into floppy eject ioctl. * We do this in order to provide a means to eject floppy disks before @@ -3495,8 +3495,7 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, return set_geometry(cmd, &inparam.g, drive, type, bdev); case FDGETPRM: ret = get_floppy_geometry(drive, type, - (struct floppy_struct **) - &outparam); + (struct floppy_struct **)&outparam); if (ret) return ret; break; @@ -3531,20 +3530,20 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, UDP->max_errors.reporting = (unsigned short)(param & 0x0f); return 0; case FDGETMAXERRS: - outparam = (const char *)&UDP->max_errors; + outparam = &UDP->max_errors; break; case FDSETMAXERRS: UDP->max_errors = inparam.max_errors; break; case FDGETDRVTYP: outparam = drive_name(type, drive); - SUPBOUND(size, strlen(outparam) + 1); + SUPBOUND(size, strlen((const char *)outparam) + 1); break; case FDSETDRVPRM: *UDP = inparam.dp; break; case FDGETDRVPRM: - outparam = (const char *)UDP; + outparam = UDP; break; case FDPOLLDRVSTAT: if (lock_fdc(drive, true)) @@ -3554,18 +3553,18 @@ static int fd_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, process_fd_request(); /* fall through */ case FDGETDRVSTAT: - outparam = (const char *)UDRS; + outparam = UDRS; break; case FDRESET: return user_reset_fdc(drive, (int)param, true); case FDGETFDCSTAT: - outparam = (const char *)UFDCS; + outparam = UFDCS; break; case FDWERRORCLR: memset(UDRWE, 0, sizeof(*UDRWE)); return 0; case FDWERRORGET: - outparam = (const char *)UDRWE; + outparam = UDRWE; break; case FDRAWCMD: if (type) -- cgit v1.2.3 From 0d3580d40cc38bbaf63d0b2756931e0ae241a9ea Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Wed, 10 Mar 2010 15:21:23 -0800 Subject: asiliantfb: fix test of unsigned in asiliant_calc_dclk2() Ftarget, Fret, n and m are unsigned so the tests did not work. Signed-off-by: Roel Kluin Cc: Andres Salomon Cc: Krzysztof Helt Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/video/asiliantfb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/video/asiliantfb.c b/drivers/video/asiliantfb.c index 9fe90ce928fb..e70bc225fe31 100644 --- a/drivers/video/asiliantfb.c +++ b/drivers/video/asiliantfb.c @@ -140,7 +140,7 @@ static void asiliant_calc_dclk2(u32 *ppixclock, u8 *dclk2_m, u8 *dclk2_n, u8 *dc /* 3 <= m <= 257 */ if (m >= 3 && m <= 257) { - unsigned new_error = ((Ftarget * n) - (Fref * m)) >= 0 ? + unsigned new_error = Ftarget * n >= Fref * m ? ((Ftarget * n) - (Fref * m)) : ((Fref * m) - (Ftarget * n)); if (new_error < best_error) { best_n = n; @@ -152,7 +152,7 @@ static void asiliant_calc_dclk2(u32 *ppixclock, u8 *dclk2_m, u8 *dclk2_n, u8 *dc else if (m <= 1028) { /* remember there are still only 8-bits of precision in m, so * avoid over-optimistic error calculations */ - unsigned new_error = ((Ftarget * n) - (Fref * (m & ~3))) >= 0 ? + unsigned new_error = Ftarget * n >= Fref * (m & ~3) ? ((Ftarget * n) - (Fref * (m & ~3))) : ((Fref * (m & ~3)) - (Ftarget * n)); if (new_error < best_error) { best_n = n; -- cgit v1.2.3 From d40f29bff30a1a50d7ad69bd150c9cda1ce1ba9d Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Wed, 10 Mar 2010 15:21:24 -0800 Subject: fbdev: bf54x-lq043fb/bfin-t350mcqb-fb: drop custom mmap() handler The common Blackfin code implements the get_fb_unmapped_area() function, so we no longer need to have our own mmap() handler. The common fb code will take care of everything for us now. Signed-off-by: Michael Hennerich Signed-off-by: Mike Frysinger Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/video/bf54x-lq043fb.c | 30 ------------------------------ drivers/video/bfin-t350mcqb-fb.c | 29 ----------------------------- 2 files changed, 59 deletions(-) (limited to 'drivers') diff --git a/drivers/video/bf54x-lq043fb.c b/drivers/video/bf54x-lq043fb.c index e49ae5edcc00..814312a7452f 100644 --- a/drivers/video/bf54x-lq043fb.c +++ b/drivers/video/bf54x-lq043fb.c @@ -82,7 +82,6 @@ struct bfin_bf54xfb_info { unsigned char *fb_buffer; /* RGB Buffer */ dma_addr_t dma_handle; - int lq043_mmap; int lq043_open_cnt; int irq; spinlock_t lock; /* lock */ @@ -316,7 +315,6 @@ static int bfin_bf54x_fb_release(struct fb_info *info, int user) spin_lock(&fbi->lock); fbi->lq043_open_cnt--; - fbi->lq043_mmap = 0; if (fbi->lq043_open_cnt <= 0) { @@ -374,33 +372,6 @@ static int bfin_bf54x_fb_check_var(struct fb_var_screeninfo *var, return 0; } -static int bfin_bf54x_fb_mmap(struct fb_info *info, struct vm_area_struct *vma) -{ - - struct bfin_bf54xfb_info *fbi = info->par; - - if (fbi->lq043_mmap) - return -1; - - spin_lock(&fbi->lock); - fbi->lq043_mmap = 1; - spin_unlock(&fbi->lock); - - vma->vm_start = (unsigned long)(fbi->fb_buffer); - - vma->vm_end = vma->vm_start + info->fix.smem_len; - /* For those who don't understand how mmap works, go read - * Documentation/nommu-mmap.txt. - * For those that do, you will know that the VM_MAYSHARE flag - * must be set in the vma->vm_flags structure on noMMU - * Other flags can be set, and are documented in - * include/linux/mm.h - */ - vma->vm_flags |= VM_MAYSHARE | VM_SHARED; - - return 0; -} - int bfin_bf54x_fb_cursor(struct fb_info *info, struct fb_cursor *cursor) { if (nocursor) @@ -452,7 +423,6 @@ static struct fb_ops bfin_bf54x_fb_ops = { .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, .fb_imageblit = cfb_imageblit, - .fb_mmap = bfin_bf54x_fb_mmap, .fb_cursor = bfin_bf54x_fb_cursor, .fb_setcolreg = bfin_bf54x_fb_setcolreg, }; diff --git a/drivers/video/bfin-t350mcqb-fb.c b/drivers/video/bfin-t350mcqb-fb.c index 2549c53b26a0..5653d083a983 100644 --- a/drivers/video/bfin-t350mcqb-fb.c +++ b/drivers/video/bfin-t350mcqb-fb.c @@ -87,7 +87,6 @@ struct bfin_t350mcqbfb_info { struct device *dev; unsigned char *fb_buffer; /* RGB Buffer */ dma_addr_t dma_handle; - int lq043_mmap; int lq043_open_cnt; int irq; spinlock_t lock; /* lock */ @@ -235,7 +234,6 @@ static int bfin_t350mcqb_fb_release(struct fb_info *info, int user) spin_lock(&fbi->lock); fbi->lq043_open_cnt--; - fbi->lq043_mmap = 0; if (fbi->lq043_open_cnt <= 0) { bfin_t350mcqb_disable_ppi(); @@ -293,32 +291,6 @@ static int bfin_t350mcqb_fb_check_var(struct fb_var_screeninfo *var, return 0; } -static int bfin_t350mcqb_fb_mmap(struct fb_info *info, struct vm_area_struct *vma) -{ - struct bfin_t350mcqbfb_info *fbi = info->par; - - if (fbi->lq043_mmap) - return -1; - - spin_lock(&fbi->lock); - fbi->lq043_mmap = 1; - spin_unlock(&fbi->lock); - - vma->vm_start = (unsigned long)(fbi->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET); - - vma->vm_end = vma->vm_start + info->fix.smem_len; - /* For those who don't understand how mmap works, go read - * Documentation/nommu-mmap.txt. - * For those that do, you will know that the VM_MAYSHARE flag - * must be set in the vma->vm_flags structure on noMMU - * Other flags can be set, and are documented in - * include/linux/mm.h - */ - vma->vm_flags |= VM_MAYSHARE | VM_SHARED; - - return 0; -} - int bfin_t350mcqb_fb_cursor(struct fb_info *info, struct fb_cursor *cursor) { if (nocursor) @@ -370,7 +342,6 @@ static struct fb_ops bfin_t350mcqb_fb_ops = { .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, .fb_imageblit = cfb_imageblit, - .fb_mmap = bfin_t350mcqb_fb_mmap, .fb_cursor = bfin_t350mcqb_fb_cursor, .fb_setcolreg = bfin_t350mcqb_fb_setcolreg, }; -- cgit v1.2.3 From c1c341a060da1bd66a1982198b1a99765b07b8a2 Mon Sep 17 00:00:00 2001 From: Jaya Kumar Date: Wed, 10 Mar 2010 15:21:24 -0800 Subject: broadsheetfb: add multiple panel type support Update broadsheetfb to add support for multiple panel types. The 3.7" and 6" are known to work but the 9.7" is untested due to lack of hardware. Signed-off-by: Jaya Kumar Cc: Geert Uytterhoeven Cc: Krzysztof Helt Cc: Russell King Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/arm/mach-pxa/am300epd.c | 2 +- drivers/video/broadsheetfb.c | 127 +++++++++++++++++++++++++++++++++++++------ include/video/broadsheetfb.h | 1 + 3 files changed, 112 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c index 4bd10a17332e..993d75e66390 100644 --- a/arch/arm/mach-pxa/am300epd.c +++ b/arch/arm/mach-pxa/am300epd.c @@ -288,7 +288,7 @@ int __init am300_init(void) } module_param(panel_type, uint, 0); -MODULE_PARM_DESC(panel_type, "Select the panel type: 6, 8, 97"); +MODULE_PARM_DESC(panel_type, "Select the panel type: 37, 6, 97"); MODULE_DESCRIPTION("board driver for am300 epd kit"); MODULE_AUTHOR("Jaya Kumar"); diff --git a/drivers/video/broadsheetfb.c b/drivers/video/broadsheetfb.c index df9ccb901d86..8f011062dec5 100644 --- a/drivers/video/broadsheetfb.c +++ b/drivers/video/broadsheetfb.c @@ -33,7 +33,60 @@ #include