From a0e37da2a542acb6069b9e10d8aba3be4e5204d7 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 12 Feb 2018 19:32:37 -0600 Subject: ARM: OMAP2+: Cleanup omap_gpio_dev_attr usage The omap_gpio_dev_attr data was used to supply instance-specific data for legacy non-DT devices. The GPIO legacy device support has been cleaned up in commit 14944934f8ac ("ARM: OMAP2+: Remove legacy gpio code") a while ago and this data is therefore no longer needed. So, cleanup the structure and all the associated data in various hwmod data files. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- include/linux/platform_data/gpio-omap.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include/linux/platform_data') diff --git a/include/linux/platform_data/gpio-omap.h b/include/linux/platform_data/gpio-omap.h index cb2618147c34..8612855691b2 100644 --- a/include/linux/platform_data/gpio-omap.h +++ b/include/linux/platform_data/gpio-omap.h @@ -157,11 +157,6 @@ #define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) #define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) -struct omap_gpio_dev_attr { - int bank_width; /* GPIO bank width */ - bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ -}; - struct omap_gpio_reg_offs { u16 revision; u16 direction; -- cgit v1.2.3 From 1cddc364584e76c16354d34326c671aac2a23e4f Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 12 Feb 2018 19:32:40 -0600 Subject: ARM: OMAP2+: Cleanup omap2_spi_dev_attr and other legacy data The omap2_spi_dev_attr data was used to supply instance-specific data for legacy non-DT devices. The SPI legacy device support including the usage of the hwmod class revision data has been dropped in commit 6f3ab009a178 ("ARM: OMAP2+: Remove unused legacy code for device init") and this data is therefore no longer needed. So, cleanup the structure and all the associated data in various hwmod data files. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1 - arch/arm/mach-omap2/omap_hwmod_2430_data.c | 6 ----- arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 13 ----------- .../mach-omap2/omap_hwmod_33xx_43xx_common_data.h | 2 -- .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 7 ------ arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 2 -- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 26 ---------------------- arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 4 ---- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 22 ------------------ arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 26 ---------------------- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 26 ---------------------- arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 7 ------ include/linux/platform_data/spi-omap2-mcspi.h | 8 ------- 13 files changed, 150 deletions(-) (limited to 'include/linux/platform_data') diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 9f16b1b8d882..fe66cf247874 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -14,7 +14,6 @@ */ #include -#include #include #include "omap_hwmod.h" diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 409f0e634707..cdbd09b21168 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include "omap_hwmod.h" @@ -157,10 +156,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { }; /* mcspi3 */ -static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap2430_mcspi3_hwmod = { .name = "mcspi3", .main_clk = "mcspi3_fck", @@ -172,7 +167,6 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = { }, }, .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi3_dev_attr, }; /* usbhsotg */ diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 00a5ae5df82d..5345919a81f8 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -12,8 +12,6 @@ #include #include -#include - #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" #include "cm-regbits-24xx.h" @@ -159,7 +157,6 @@ static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = { struct omap_hwmod_class omap2xxx_mcspi_class = { .name = "mcspi", .sysc = &omap2xxx_mcspi_sysc, - .rev = OMAP2_MCSPI_REV, }; /* @@ -593,10 +590,6 @@ struct omap_hwmod omap2xxx_gpio4_hwmod = { }; /* mcspi1 */ -static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { - .num_chipselect = 4, -}; - struct omap_hwmod omap2xxx_mcspi1_hwmod = { .name = "mcspi1", .main_clk = "mcspi1_fck", @@ -608,14 +601,9 @@ struct omap_hwmod omap2xxx_mcspi1_hwmod = { }, }, .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi1_dev_attr, }; /* mcspi2 */ -static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { - .num_chipselect = 2, -}; - struct omap_hwmod omap2xxx_mcspi2_hwmod = { .name = "mcspi2", .main_clk = "mcspi2_fck", @@ -627,7 +615,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = { }, }, .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi2_dev_attr, }; static struct omap_hwmod_class omap2xxx_counter_hwmod_class = { diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h index bbda6887388b..6f81d7a4fec1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h @@ -139,8 +139,6 @@ extern struct omap_hwmod_class am33xx_epwmss_hwmod_class; extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class; extern struct omap_hwmod_class am33xx_spi_hwmod_class; -extern struct omap2_mcspi_dev_attr mcspi_attrib; - void omap_hwmod_am33xx_reg(void); void omap_hwmod_am43xx_reg(void); diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index b1118b1124d9..5efe91c6e95b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -17,7 +17,6 @@ #include #include -#include #include "omap_hwmod.h" #include "i2c.h" #include "wd_timer.h" @@ -879,13 +878,9 @@ static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { struct omap_hwmod_class am33xx_spi_hwmod_class = { .name = "mcspi", .sysc = &am33xx_mcspi_sysc, - .rev = OMAP4_MCSPI_REV, }; /* spi0 */ -struct omap2_mcspi_dev_attr mcspi_attrib = { - .num_chipselect = 2, -}; struct omap_hwmod am33xx_spi0_hwmod = { .name = "spi0", .class = &am33xx_spi_hwmod_class, @@ -896,7 +891,6 @@ struct omap_hwmod am33xx_spi0_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi_attrib, }; /* spi1 */ @@ -910,7 +904,6 @@ struct omap_hwmod am33xx_spi1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi_attrib, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 232d03045c6d..53e1ac3724f2 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -17,8 +17,6 @@ #include #include "omap_hwmod.h" -#include - #include "omap_hwmod_common_data.h" #include "control.h" diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 7515119cab64..23008cb35140 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -23,7 +23,6 @@ #include "l3_3xxx.h" #include "l4_3xxx.h" #include -#include #include "soc.h" #include "omap_hwmod.h" @@ -1189,14 +1188,9 @@ static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { static struct omap_hwmod_class omap34xx_mcspi_class = { .name = "mcspi", .sysc = &omap34xx_mcspi_sysc, - .rev = OMAP3_MCSPI_REV, }; /* mcspi1 */ -static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { - .num_chipselect = 4, -}; - static struct omap_hwmod omap34xx_mcspi1 = { .name = "mcspi1", .main_clk = "mcspi1_fck", @@ -1208,14 +1202,9 @@ static struct omap_hwmod omap34xx_mcspi1 = { }, }, .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi1_dev_attr, }; /* mcspi2 */ -static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap34xx_mcspi2 = { .name = "mcspi2", .main_clk = "mcspi2_fck", @@ -1227,16 +1216,9 @@ static struct omap_hwmod omap34xx_mcspi2 = { }, }, .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi2_dev_attr, }; /* mcspi3 */ - - -static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap34xx_mcspi3 = { .name = "mcspi3", .main_clk = "mcspi3_fck", @@ -1248,16 +1230,9 @@ static struct omap_hwmod omap34xx_mcspi3 = { }, }, .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi3_dev_attr, }; /* mcspi4 */ - - -static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { - .num_chipselect = 1, -}; - static struct omap_hwmod omap34xx_mcspi4 = { .name = "mcspi4", .main_clk = "mcspi4_fck", @@ -1269,7 +1244,6 @@ static struct omap_hwmod omap34xx_mcspi4 = { }, }, .class = &omap34xx_mcspi_class, - .dev_attr = &omap_mcspi4_dev_attr, }; /* usbhsotg */ diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index 4f31ce899869..5f73b730d4fc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include "omap_hwmod.h" #include "omap_hwmod_33xx_43xx_common_data.h" #include "prcm43xx.h" @@ -237,7 +236,6 @@ static struct omap_hwmod am43xx_spi2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi_attrib, }; static struct omap_hwmod am43xx_spi3_hwmod = { @@ -251,7 +249,6 @@ static struct omap_hwmod am43xx_spi3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi_attrib, }; static struct omap_hwmod am43xx_spi4_hwmod = { @@ -265,7 +262,6 @@ static struct omap_hwmod am43xx_spi4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi_attrib, }; static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 70eb826d5f65..5a313483b3b8 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -27,7 +27,6 @@ #include -#include #include #include "omap_hwmod.h" @@ -1838,14 +1837,9 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { .name = "mcspi", .sysc = &omap44xx_mcspi_sysc, - .rev = OMAP4_MCSPI_REV, }; /* mcspi1 */ -static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { - .num_chipselect = 4, -}; - static struct omap_hwmod omap44xx_mcspi1_hwmod = { .name = "mcspi1", .class = &omap44xx_mcspi_hwmod_class, @@ -1858,14 +1852,9 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi1_dev_attr, }; /* mcspi2 */ -static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap44xx_mcspi2_hwmod = { .name = "mcspi2", .class = &omap44xx_mcspi_hwmod_class, @@ -1878,14 +1867,9 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi2_dev_attr, }; /* mcspi3 */ -static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap44xx_mcspi3_hwmod = { .name = "mcspi3", .class = &omap44xx_mcspi_hwmod_class, @@ -1898,14 +1882,9 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi3_dev_attr, }; /* mcspi4 */ -static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { - .num_chipselect = 1, -}; - static struct omap_hwmod omap44xx_mcspi4_hwmod = { .name = "mcspi4", .class = &omap44xx_mcspi_hwmod_class, @@ -1918,7 +1897,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi4_dev_attr, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 2275789854dc..f901b17bd73a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -23,7 +23,6 @@ #include #include -#include #include #include "omap_hwmod.h" @@ -1123,15 +1122,9 @@ static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = { static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = { .name = "mcspi", .sysc = &omap54xx_mcspi_sysc, - .rev = OMAP4_MCSPI_REV, }; /* mcspi1 */ -/* mcspi1 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { - .num_chipselect = 4, -}; - static struct omap_hwmod omap54xx_mcspi1_hwmod = { .name = "mcspi1", .class = &omap54xx_mcspi_hwmod_class, @@ -1144,15 +1137,9 @@ static struct omap_hwmod omap54xx_mcspi1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi1_dev_attr, }; /* mcspi2 */ -/* mcspi2 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap54xx_mcspi2_hwmod = { .name = "mcspi2", .class = &omap54xx_mcspi_hwmod_class, @@ -1165,15 +1152,9 @@ static struct omap_hwmod omap54xx_mcspi2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi2_dev_attr, }; /* mcspi3 */ -/* mcspi3 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod omap54xx_mcspi3_hwmod = { .name = "mcspi3", .class = &omap54xx_mcspi_hwmod_class, @@ -1186,15 +1167,9 @@ static struct omap_hwmod omap54xx_mcspi3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi3_dev_attr, }; /* mcspi4 */ -/* mcspi4 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { - .num_chipselect = 1, -}; - static struct omap_hwmod omap54xx_mcspi4_hwmod = { .name = "mcspi4", .class = &omap54xx_mcspi_hwmod_class, @@ -1207,7 +1182,6 @@ static struct omap_hwmod omap54xx_mcspi4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi4_dev_attr, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index d0f1fd65d01f..d66dc806425d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -23,7 +23,6 @@ #include #include -#include #include #include "omap_hwmod.h" @@ -1375,15 +1374,9 @@ static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = { static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = { .name = "mcspi", .sysc = &dra7xx_mcspi_sysc, - .rev = OMAP4_MCSPI_REV, }; /* mcspi1 */ -/* mcspi1 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { - .num_chipselect = 4, -}; - static struct omap_hwmod dra7xx_mcspi1_hwmod = { .name = "mcspi1", .class = &dra7xx_mcspi_hwmod_class, @@ -1396,15 +1389,9 @@ static struct omap_hwmod dra7xx_mcspi1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi1_dev_attr, }; /* mcspi2 */ -/* mcspi2 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod dra7xx_mcspi2_hwmod = { .name = "mcspi2", .class = &dra7xx_mcspi_hwmod_class, @@ -1417,15 +1404,9 @@ static struct omap_hwmod dra7xx_mcspi2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi2_dev_attr, }; /* mcspi3 */ -/* mcspi3 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { - .num_chipselect = 2, -}; - static struct omap_hwmod dra7xx_mcspi3_hwmod = { .name = "mcspi3", .class = &dra7xx_mcspi_hwmod_class, @@ -1438,15 +1419,9 @@ static struct omap_hwmod dra7xx_mcspi3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi3_dev_attr, }; /* mcspi4 */ -/* mcspi4 dev_attr */ -static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { - .num_chipselect = 1, -}; - static struct omap_hwmod dra7xx_mcspi4_hwmod = { .name = "mcspi4", .class = &dra7xx_mcspi_hwmod_class, @@ -1459,7 +1434,6 @@ static struct omap_hwmod dra7xx_mcspi4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &mcspi4_dev_attr, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index 333a896c0c9a..686655f884c1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -18,7 +18,6 @@ #include #include -#include #include "omap_hwmod_common_data.h" #include "cm81xx.h" @@ -1118,11 +1117,6 @@ static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = { static struct omap_hwmod_class dm816x_mcspi_class = { .name = "mcspi", .sysc = &dm816x_mcspi_sysc, - .rev = OMAP3_MCSPI_REV, -}; - -static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = { - .num_chipselect = 4, }; static struct omap_hwmod dm81xx_mcspi1_hwmod = { @@ -1136,7 +1130,6 @@ static struct omap_hwmod dm81xx_mcspi1_hwmod = { }, }, .class = &dm816x_mcspi_class, - .dev_attr = &dm816x_mcspi1_dev_attr, }; static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { diff --git a/include/linux/platform_data/spi-omap2-mcspi.h b/include/linux/platform_data/spi-omap2-mcspi.h index 13c83a25958a..0bf9fddb8306 100644 --- a/include/linux/platform_data/spi-omap2-mcspi.h +++ b/include/linux/platform_data/spi-omap2-mcspi.h @@ -2,10 +2,6 @@ #ifndef _OMAP2_MCSPI_H #define _OMAP2_MCSPI_H -#define OMAP2_MCSPI_REV 0 -#define OMAP3_MCSPI_REV 1 -#define OMAP4_MCSPI_REV 2 - #define OMAP4_MCSPI_REG_OFFSET 0x100 #define MCSPI_PINDIR_D0_IN_D1_OUT 0 @@ -17,10 +13,6 @@ struct omap2_mcspi_platform_config { unsigned int pin_dir:1; }; -struct omap2_mcspi_dev_attr { - unsigned short num_chipselect; -}; - struct omap2_mcspi_device_config { unsigned turbo_mode:1; -- cgit v1.2.3 From 0693036ca800ab471e8f28caeb3a9ac4d77af810 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 12 Feb 2018 19:32:41 -0600 Subject: ARM: OMAP2+: Cleanup omap_mcbsp_dev_attr and other legacy data The omap_mcbsp_dev_attr data was used to supply instance-specific data for legacy non-DT devices. The legacy McBSP device support including the usage of the hwmod class revision data has been dropped in commit 48f6693790aa ("ARM: OMAP2+: Remove unused legacy code for McBSP") and this data is therefore no longer needed. So, cleanup the structure and all the associated data in various hwmod data files. Cc: Peter Ujfalusi Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 2 -- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 21 --------------------- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 3 --- arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 2 -- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 1 - include/linux/platform_data/asoc-ti-mcbsp.h | 12 ------------ 6 files changed, 41 deletions(-) (limited to 'include/linux/platform_data') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index cdbd09b21168..74eefd30518c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -14,7 +14,6 @@ */ #include -#include #include #include @@ -223,7 +222,6 @@ static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { .name = "mcbsp", .sysc = &omap2430_mcbsp_sysc, - .rev = MCBSP_CONFIG_TYPE2, }; static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 23008cb35140..23336b6c7125 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -22,7 +22,6 @@ #include #include "l3_3xxx.h" #include "l4_3xxx.h" -#include #include "soc.h" #include "omap_hwmod.h" @@ -896,7 +895,6 @@ static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { .name = "mcbsp", .sysc = &omap3xxx_mcbsp_sysc, - .rev = MCBSP_CONFIG_TYPE3, }; /* McBSP functional clock mapping */ @@ -911,7 +909,6 @@ static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { }; /* mcbsp1 */ - static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap3xxx_mcbsp_hwmod_class, @@ -928,11 +925,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { }; /* mcbsp2 */ - -static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { - .sidetone = "mcbsp2_sidetone", -}; - static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap3xxx_mcbsp_hwmod_class, @@ -946,15 +938,9 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { }, .opt_clks = mcbsp234_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), - .dev_attr = &omap34xx_mcbsp2_dev_attr, }; /* mcbsp3 */ - -static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { - .sidetone = "mcbsp3_sidetone", -}; - static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { .name = "mcbsp3", .class = &omap3xxx_mcbsp_hwmod_class, @@ -968,12 +954,9 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { }, .opt_clks = mcbsp234_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), - .dev_attr = &omap34xx_mcbsp3_dev_attr, }; /* mcbsp4 */ - - static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { .name = "mcbsp4", .class = &omap3xxx_mcbsp_hwmod_class, @@ -990,8 +973,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { }; /* mcbsp5 */ - - static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { .name = "mcbsp5", .class = &omap3xxx_mcbsp_hwmod_class, @@ -1020,7 +1001,6 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { }; /* mcbsp2_sidetone */ - static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { .name = "mcbsp2_sidetone", .class = &omap3xxx_mcbsp_sidetone_hwmod_class, @@ -1029,7 +1009,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { }; /* mcbsp3_sidetone */ - static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { .name = "mcbsp3_sidetone", .class = &omap3xxx_mcbsp_sidetone_hwmod_class, diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 5a313483b3b8..e4f8ae9cd637 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -27,8 +27,6 @@ #include -#include - #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" #include "cm1_44xx.h" @@ -1679,7 +1677,6 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { .name = "mcbsp", .sysc = &omap44xx_mcbsp_sysc, - .rev = MCBSP_CONFIG_TYPE4, }; /* mcbsp1 */ diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index f901b17bd73a..c72cd84b07ec 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -23,7 +23,6 @@ #include #include -#include #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" @@ -985,7 +984,6 @@ static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = { static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = { .name = "mcbsp", .sysc = &omap54xx_mcbsp_sysc, - .rev = MCBSP_CONFIG_TYPE4, }; /* mcbsp1 */ diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index d66dc806425d..62352d1e6361 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -23,7 +23,6 @@ #include #include -#include #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" diff --git a/include/linux/platform_data/asoc-ti-mcbsp.h b/include/linux/platform_data/asoc-ti-mcbsp.h index e684543254f3..e319d0a2ec82 100644 --- a/include/linux/platform_data/asoc-ti-mcbsp.h +++ b/include/linux/platform_data/asoc-ti-mcbsp.h @@ -25,10 +25,6 @@ #include #include -#define MCBSP_CONFIG_TYPE2 0x2 -#define MCBSP_CONFIG_TYPE3 0x3 -#define MCBSP_CONFIG_TYPE4 0x4 - /* Platform specific configuration */ struct omap_mcbsp_ops { void (*request)(unsigned int); @@ -47,14 +43,6 @@ struct omap_mcbsp_platform_data { int (*force_ick_on)(struct clk *clk, bool force_on); }; -/** - * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod - * @sidetone: name of the sidetone device - */ -struct omap_mcbsp_dev_attr { - const char *sidetone; -}; - void omap3_mcbsp_init_pdata_callback(struct omap_mcbsp_platform_data *pdata); #endif -- cgit v1.2.3 From bdec5a6b57896da81bc47262868468717a06bb69 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Sat, 17 Feb 2018 21:22:24 -0600 Subject: ARM: da8xx: use platform data for CFGCHIP syscon regmap This converts from using a platform device for the CFGCHIP syscon regmap to using platform data to pass the regmap to consumers. A lazy getter function is used so that the regmap will only be created if it is actually used. This function will also be used in the clock init when we convert to the common clock framework. The USB PHY driver is currently the only consumer. This driver is updated to use platform data to get the CFGCHIP regmap instead of syscon_regmap_lookup_by_pdevname(). Signed-off-by: David Lechner Acked-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/board-da830-evm.c | 4 --- arch/arm/mach-davinci/board-da850-evm.c | 4 --- arch/arm/mach-davinci/board-mityomapl138.c | 4 --- arch/arm/mach-davinci/board-omapl138-hawk.c | 4 --- arch/arm/mach-davinci/devices-da8xx.c | 45 +++++++++++++++-------------- arch/arm/mach-davinci/include/mach/da8xx.h | 3 +- arch/arm/mach-davinci/usb-da8xx.c | 6 ++++ drivers/phy/ti/phy-da8xx-usb.c | 8 +++-- include/linux/platform_data/phy-da8xx-usb.h | 21 ++++++++++++++ 9 files changed, 58 insertions(+), 41 deletions(-) create mode 100644 include/linux/platform_data/phy-da8xx-usb.h (limited to 'include/linux/platform_data') diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index f673cd7a6766..f960cbef6538 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -551,10 +551,6 @@ static __init void da830_evm_init(void) struct davinci_soc_info *soc_info = &davinci_soc_info; int ret; - ret = da8xx_register_cfgchip(); - if (ret) - pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret); - ret = da830_register_gpio(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index d898a94f6eae..26bdb10a8927 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -1334,10 +1334,6 @@ static __init void da850_evm_init(void) { int ret; - ret = da8xx_register_cfgchip(); - if (ret) - pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret); - ret = da850_register_gpio(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index b73ce7bae81f..9e7388ba413c 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -502,10 +502,6 @@ static void __init mityomapl138_init(void) { int ret; - ret = da8xx_register_cfgchip(); - if (ret) - pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret); - /* for now, no special EDMA channels are reserved */ ret = da850_register_edma(NULL); if (ret) diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index a3e78074be70..baab7eb61632 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c @@ -281,10 +281,6 @@ static __init void omapl138_hawk_init(void) { int ret; - ret = da8xx_register_cfgchip(); - if (ret) - pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret); - ret = da850_register_gpio(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index e1c40e73d30a..166bf29b1296 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -11,7 +11,6 @@ * (at your option) any later version. */ #include -#include #include #include #include @@ -1118,29 +1117,33 @@ int __init da850_register_sata(unsigned long refclkpn) } #endif -static struct syscon_platform_data da8xx_cfgchip_platform_data = { - .label = "cfgchip", -}; +static struct regmap *da8xx_cfgchip; -static struct resource da8xx_cfgchip_resources[] = { - { - .start = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP0_REG, - .end = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP4_REG + 3, - .flags = IORESOURCE_MEM, - }, -}; +/* regmap doesn't make a copy of this, so we need to keep the pointer around */ +static const char da8xx_cfgchip_name[] = "cfgchip"; -static struct platform_device da8xx_cfgchip_device = { - .name = "syscon", - .id = -1, - .dev = { - .platform_data = &da8xx_cfgchip_platform_data, - }, - .num_resources = ARRAY_SIZE(da8xx_cfgchip_resources), - .resource = da8xx_cfgchip_resources, +static const struct regmap_config da8xx_cfgchip_config __initconst = { + .name = da8xx_cfgchip_name, + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG, }; -int __init da8xx_register_cfgchip(void) +/** + * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap + * + * This is for use on non-DT boards only. For DT boards, use + * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip") + * + * Returns: Pointer to the CFGCHIP regmap or negative error code. + */ +struct regmap * __init da8xx_get_cfgchip(void) { - return platform_device_register(&da8xx_cfgchip_device); + if (IS_ERR_OR_NULL(da8xx_cfgchip)) + da8xx_cfgchip = regmap_init_mmio(NULL, + DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG), + &da8xx_cfgchip_config); + + return da8xx_cfgchip; } diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 93ff1569cee5..03f37ef4297f 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -123,7 +124,7 @@ void da8xx_rproc_reserve_cma(void); int da8xx_register_rproc(void); int da850_register_gpio(void); int da830_register_gpio(void); -int da8xx_register_cfgchip(void); +struct regmap *da8xx_get_cfgchip(void); extern struct platform_device da8xx_serial_device[]; extern struct emac_platform_data da8xx_emac_pdata; diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c index fb31f6eeba96..4d89d86ce7e5 100644 --- a/arch/arm/mach-davinci/usb-da8xx.c +++ b/arch/arm/mach-davinci/usb-da8xx.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,11 @@ static struct platform_device da8xx_usb_phy = { int __init da8xx_register_usb_phy(void) { + struct da8xx_usb_phy_platform_data pdata; + + pdata.cfgchip = da8xx_get_cfgchip(); + da8xx_usb_phy.dev.platform_data = &pdata; + return platform_device_register(&da8xx_usb_phy); } diff --git a/drivers/phy/ti/phy-da8xx-usb.c b/drivers/phy/ti/phy-da8xx-usb.c index 5bd33d06df95..befb886ff121 100644 --- a/drivers/phy/ti/phy-da8xx-usb.c +++ b/drivers/phy/ti/phy-da8xx-usb.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -145,6 +146,7 @@ static struct phy *da8xx_usb_phy_of_xlate(struct device *dev, static int da8xx_usb_phy_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct da8xx_usb_phy_platform_data *pdata = dev->platform_data; struct device_node *node = dev->of_node; struct da8xx_usb_phy *d_phy; @@ -152,11 +154,11 @@ static int da8xx_usb_phy_probe(struct platform_device *pdev) if (!d_phy) return -ENOMEM; - if (node) + if (pdata) + d_phy->regmap = pdata->cfgchip; + else d_phy->regmap = syscon_regmap_lookup_by_compatible( "ti,da830-cfgchip"); - else - d_phy->regmap = syscon_regmap_lookup_by_pdevname("syscon"); if (IS_ERR(d_phy->regmap)) { dev_err(dev, "Failed to get syscon\n"); return PTR_ERR(d_phy->regmap); diff --git a/include/linux/platform_data/phy-da8xx-usb.h b/include/linux/platform_data/phy-da8xx-usb.h new file mode 100644 index 000000000000..85c2b99381b2 --- /dev/null +++ b/include/linux/platform_data/phy-da8xx-usb.h @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-da8xx-usb - TI DaVinci DA8xx USB PHY driver + * + * Copyright (C) 2018 David Lechner + */ + +#ifndef __LINUX_PLATFORM_DATA_PHY_DA8XX_USB_H__ +#define __LINUX_PLATFORM_DATA_PHY_DA8XX_USB_H__ + +#include + +/** + * da8xx_usb_phy_platform_data + * @cfgchip: CFGCHIP syscon regmap + */ +struct da8xx_usb_phy_platform_data { + struct regmap *cfgchip; +}; + +#endif /* __LINUX_PLATFORM_DATA_PHY_DA8XX_USB_H__ */ -- cgit v1.2.3 From a7f249e33a44432de30d50f3c57868bc00a8f362 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Thu, 15 Feb 2018 11:31:47 +0530 Subject: clocksource: timer-ti-dm: Add timer ops to the platform data structure Add timer ops to the platform data structure Signed-off-by: Keerthy Reviewed-by: Sebastian Reichel Tested-by: Ladislav Michl Signed-off-by: Tony Lindgren --- include/linux/platform_data/dmtimer-omap.h | 38 ++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'include/linux/platform_data') diff --git a/include/linux/platform_data/dmtimer-omap.h b/include/linux/platform_data/dmtimer-omap.h index a19b78d826e9..757a0f9e26f9 100644 --- a/include/linux/platform_data/dmtimer-omap.h +++ b/include/linux/platform_data/dmtimer-omap.h @@ -20,12 +20,50 @@ #ifndef __PLATFORM_DATA_DMTIMER_OMAP_H__ #define __PLATFORM_DATA_DMTIMER_OMAP_H__ +struct omap_dm_timer_ops { + struct omap_dm_timer *(*request_by_node)(struct device_node *np); + struct omap_dm_timer *(*request_specific)(int timer_id); + struct omap_dm_timer *(*request)(void); + + int (*free)(struct omap_dm_timer *timer); + + void (*enable)(struct omap_dm_timer *timer); + void (*disable)(struct omap_dm_timer *timer); + + int (*get_irq)(struct omap_dm_timer *timer); + int (*set_int_enable)(struct omap_dm_timer *timer, + unsigned int value); + int (*set_int_disable)(struct omap_dm_timer *timer, u32 mask); + + struct clk *(*get_fclk)(struct omap_dm_timer *timer); + + int (*start)(struct omap_dm_timer *timer); + int (*stop)(struct omap_dm_timer *timer); + int (*set_source)(struct omap_dm_timer *timer, int source); + + int (*set_load)(struct omap_dm_timer *timer, int autoreload, + unsigned int value); + int (*set_match)(struct omap_dm_timer *timer, int enable, + unsigned int match); + int (*set_pwm)(struct omap_dm_timer *timer, int def_on, + int toggle, int trigger); + int (*set_prescaler)(struct omap_dm_timer *timer, int prescaler); + + unsigned int (*read_counter)(struct omap_dm_timer *timer); + int (*write_counter)(struct omap_dm_timer *timer, + unsigned int value); + unsigned int (*read_status)(struct omap_dm_timer *timer); + int (*write_status)(struct omap_dm_timer *timer, + unsigned int value); +}; + struct dmtimer_platform_data { /* set_timer_src - Only used for OMAP1 devices */ int (*set_timer_src)(struct platform_device *pdev, int source); u32 timer_capability; u32 timer_errata; int (*get_context_loss_count)(struct device *); + const struct omap_dm_timer_ops *timer_ops; }; #endif /* __PLATFORM_DATA_DMTIMER_OMAP_H__ */ -- cgit v1.2.3 From ef70b0bdeaf893dd6d9c3a8d05d9b65d395506c0 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 22 Feb 2018 14:00:25 -0800 Subject: bus: ti-sysc: Add support for platform data callbacks We want to pass the device tree configuration for interconnect target modules from ti-sysc driver to the existing platform hwmod code. This allows us to first validate the dts data against the existing platform data before we start dropping the platform data in favor of device tree data. To do this, let's add platform data callbacks for PM runtime functions to call for the interconnect target modules if platform data is available. Note that as ti-sysc driver can rebind, omap_auxdata_lookup and related functions can no longer be __init. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-n8x0.c | 4 +- arch/arm/mach-omap2/pdata-quirks.c | 40 ++++++++++++++- drivers/bus/ti-sysc.c | 96 ++++++++++++++++++++++++++++++----- include/linux/platform_data/ti-sysc.h | 49 ++++++++++++++++++ 4 files changed, 172 insertions(+), 17 deletions(-) (limited to 'include/linux/platform_data') diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 20f25539d572..75bc18646df6 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -566,11 +566,11 @@ static int n8x0_menelaus_late_init(struct device *dev) } #endif -struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { +struct menelaus_platform_data n8x0_menelaus_platform_data = { .late_init = n8x0_menelaus_late_init, }; -struct aic3x_pdata n810_aic33_data __initdata = { +struct aic3x_pdata n810_aic33_data = { .gpio_reset = 118, }; diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 1cca66ad68b5..eea82c31ee77 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -455,6 +456,42 @@ static void __init dra7x_evm_mmc_quirk(void) } #endif +static int ti_sysc_enable_module(struct device *dev, + const struct ti_sysc_cookie *cookie) +{ + if (!cookie->data) + return -EINVAL; + + return omap_hwmod_enable(cookie->data); +} + +static int ti_sysc_idle_module(struct device *dev, + const struct ti_sysc_cookie *cookie) +{ + if (!cookie->data) + return -EINVAL; + + return omap_hwmod_idle(cookie->data); +} + +static int ti_sysc_shutdown_module(struct device *dev, + const struct ti_sysc_cookie *cookie) +{ + if (!cookie->data) + return -EINVAL; + + return omap_hwmod_shutdown(cookie->data); +} + +static struct of_dev_auxdata omap_auxdata_lookup[]; + +static struct ti_sysc_platform_data ti_sysc_pdata = { + .auxdata = omap_auxdata_lookup, + .enable_module = ti_sysc_enable_module, + .idle_module = ti_sysc_idle_module, + .shutdown_module = ti_sysc_shutdown_module, +}; + static struct pcs_pdata pcs_pdata; void omap_pcs_legacy_init(int irq, void (*rearm)(void)) @@ -545,7 +582,7 @@ static struct pdata_init auxdata_quirks[] __initdata = { struct omap_sr_data __maybe_unused omap_sr_pdata[OMAP_SR_NR]; -static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { +static struct of_dev_auxdata omap_auxdata_lookup[] = { #ifdef CONFIG_MACH_NOKIA_N8X0 OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL), OF_DEV_AUXDATA("menelaus", 0x72, "1-0072", &n8x0_menelaus_platform_data), @@ -603,6 +640,7 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { &dra7_hsmmc_data_mmc3), #endif /* Common auxdata */ + OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata), OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata), { /* sentinel */ }, }; diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index fc9aac3d4d02..50fcb04e8179 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -25,13 +25,6 @@ #include -enum sysc_registers { - SYSC_REVISION, - SYSC_SYSCONFIG, - SYSC_SYSSTATUS, - SYSC_MAX_REGS, -}; - static const char * const reg_names[] = { "rev", "sysc", "syss", }; enum sysc_clocks { @@ -70,6 +63,7 @@ struct sysc { const char *legacy_mode; const struct sysc_capabilities *cap; struct sysc_config cfg; + struct ti_sysc_cookie cookie; const char *name; u32 revision; bool enabled; @@ -494,6 +488,7 @@ static void sysc_show_registers(struct sysc *ddata) bufp += sysc_show_reg(ddata, bufp, i); bufp += sysc_show_rev(bufp, ddata); + bufp += sysc_show_rev(bufp, ddata); dev_dbg(ddata->dev, "%llx:%x%s\n", ddata->module_pa, ddata->module_size, @@ -502,33 +497,70 @@ static void sysc_show_registers(struct sysc *ddata) static int __maybe_unused sysc_runtime_suspend(struct device *dev) { + struct ti_sysc_platform_data *pdata; struct sysc *ddata; - int i; + int error = 0, i; ddata = dev_get_drvdata(dev); - if (ddata->legacy_mode) + if (!ddata->enabled) return 0; + if (ddata->legacy_mode) { + pdata = dev_get_platdata(ddata->dev); + if (!pdata) + return 0; + + if (!pdata->idle_module) + return -ENODEV; + + error = pdata->idle_module(dev, &ddata->cookie); + if (error) + dev_err(dev, "%s: could not idle: %i\n", + __func__, error); + + goto idled; + } + for (i = 0; i < SYSC_MAX_CLOCKS; i++) { if (IS_ERR_OR_NULL(ddata->clocks[i])) continue; clk_disable(ddata->clocks[i]); } - return 0; +idled: + ddata->enabled = false; + + return error; } static int __maybe_unused sysc_runtime_resume(struct device *dev) { + struct ti_sysc_platform_data *pdata; struct sysc *ddata; - int i, error; + int error = 0, i; ddata = dev_get_drvdata(dev); - if (ddata->legacy_mode) + if (ddata->enabled) return 0; + if (ddata->legacy_mode) { + pdata = dev_get_platdata(ddata->dev); + if (!pdata) + return 0; + + if (!pdata->enable_module) + return -ENODEV; + + error = pdata->enable_module(dev, &ddata->cookie); + if (error) + dev_err(dev, "%s: could not enable: %i\n", + __func__, error); + + goto awake; + } + for (i = 0; i < SYSC_MAX_CLOCKS; i++) { if (IS_ERR_OR_NULL(ddata->clocks[i])) continue; @@ -537,7 +569,10 @@ static int __maybe_unused sysc_runtime_resume(struct device *dev) return error; } - return 0; +awake: + ddata->enabled = true; + + return error; } #ifdef CONFIG_PM_SLEEP @@ -1007,6 +1042,33 @@ static const struct sysc_capabilities sysc_omap4_usb_host_fs = { .regbits = &sysc_regbits_omap4_usb_host_fs, }; +static int sysc_init_pdata(struct sysc *ddata) +{ + struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); + struct ti_sysc_module_data mdata; + int error = 0; + + if (!pdata || !ddata->legacy_mode) + return 0; + + mdata.name = ddata->legacy_mode; + mdata.module_pa = ddata->module_pa; + mdata.module_size = ddata->module_size; + mdata.offsets = ddata->offsets; + mdata.nr_offsets = SYSC_MAX_REGS; + mdata.cap = ddata->cap; + mdata.cfg = &ddata->cfg; + + if (!pdata->init_module) + return -ENODEV; + + error = pdata->init_module(ddata->dev, &mdata, &ddata->cookie); + if (error == -EEXIST) + error = 0; + + return error; +} + static int sysc_init_match(struct sysc *ddata) { const struct sysc_capabilities *cap; @@ -1034,6 +1096,7 @@ static void ti_sysc_idle(struct work_struct *work) static int sysc_probe(struct platform_device *pdev) { + struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); struct sysc *ddata; int error; @@ -1072,6 +1135,10 @@ static int sysc_probe(struct platform_device *pdev) if (error) goto unprepare; + error = sysc_init_pdata(ddata); + if (error) + goto unprepare; + pm_runtime_enable(ddata->dev); error = sysc_init_module(ddata); @@ -1089,7 +1156,8 @@ static int sysc_probe(struct platform_device *pdev) ddata->dev->type = &sysc_device_type; error = of_platform_populate(ddata->dev->of_node, - NULL, NULL, ddata->dev); + NULL, pdata ? pdata->auxdata : NULL, + ddata->dev); if (error) goto err; diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index 1be356330b96..4176cb90e195 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -16,6 +16,10 @@ enum ti_sysc_module_type { TI_SYSC_OMAP4_USB_HOST_FS, }; +struct ti_sysc_cookie { + void *data; +}; + /** * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets * @midle_shift: Offset of the midle bit @@ -83,4 +87,49 @@ struct sysc_config { u32 quirks; }; +enum sysc_registers { + SYSC_REVISION, + SYSC_SYSCONFIG, + SYSC_SYSSTATUS, + SYSC_MAX_REGS, +}; + +/** + * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module + * @name: legacy "ti,hwmods" module name + * @module_pa: physical address of the interconnect target module + * @module_size: size of the interconnect target module + * @offsets: array of register offsets as listed in enum sysc_registers + * @nr_offsets: number of registers + * @cap: interconnect target module capabilities + * @cfg: interconnect target module configuration + * + * This data is enough to allocate a new struct omap_hwmod_class_sysconfig + * based on device tree data parsed by ti-sysc driver. + */ +struct ti_sysc_module_data { + const char *name; + u64 module_pa; + u32 module_size; + int *offsets; + int nr_offsets; + const struct sysc_capabilities *cap; + struct sysc_config *cfg; +}; + +struct device; + +struct ti_sysc_platform_data { + struct of_dev_auxdata *auxdata; + int (*init_module)(struct device *dev, + const struct ti_sysc_module_data *data, + struct ti_sysc_cookie *cookie); + int (*enable_module)(struct device *dev, + const struct ti_sysc_cookie *cookie); + int (*idle_module)(struct device *dev, + const struct ti_sysc_cookie *cookie); + int (*shutdown_module)(struct device *dev, + const struct ti_sysc_cookie *cookie); +}; + #endif /* __TI_SYSC_DATA_H__ */ -- cgit v1.2.3 From a885f0fe209f262efa2c1cac9278a5774e5f7a80 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 22 Feb 2018 14:03:48 -0800 Subject: bus: ti-sysc: Handle some devices in omap_device compatible way Now that ti-sysc can manage child devices, we must also be backwards compatible with the current omap_device code. With omap_device, we assume that the child device manages the interconnect target module directly. The drivers needing special handling are the ones that still set pm_runtime_irq_safe(). In the long run we want to update those drivers as otherwise they will cause problems with genpd as a permanent PM runtime usage count is set on the parent device. We can handle omap_device these devices by improving the ti-sysc quirk handling to detect the devices needing special handling based on register map and revision register if usable. We also need to implement dev_pm_domain for these child devices just like omap_device does. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 226 +++++++++++++++++++++++++++++++++- include/linux/platform_data/ti-sysc.h | 1 + 2 files changed, 224 insertions(+), 3 deletions(-) (limited to 'include/linux/platform_data') diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 50fcb04e8179..5aeab4533b5f 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -14,8 +14,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -68,6 +70,7 @@ struct sysc { u32 revision; bool enabled; bool needs_resume; + bool child_needs_resume; struct delayed_work idle_work; }; @@ -474,6 +477,14 @@ static int sysc_show_reg(struct sysc *ddata, return sprintf(bufp, ":%x", ddata->offsets[reg]); } +static int sysc_show_name(char *bufp, struct sysc *ddata) +{ + if (!ddata->name) + return 0; + + return sprintf(bufp, ":%s", ddata->name); +} + /** * sysc_show_registers - show information about interconnect target module * @ddata: device driver data @@ -488,7 +499,7 @@ static void sysc_show_registers(struct sysc *ddata) bufp += sysc_show_reg(ddata, bufp, i); bufp += sysc_show_rev(bufp, ddata); - bufp += sysc_show_rev(bufp, ddata); + bufp += sysc_show_name(bufp, ddata); dev_dbg(ddata->dev, "%llx:%x%s\n", ddata->module_pa, ddata->module_size, @@ -612,11 +623,93 @@ static const struct dev_pm_ops sysc_pm_ops = { NULL) }; +/* Module revision register based quirks */ +struct sysc_revision_quirk { + const char *name; + u32 base; + int rev_offset; + int sysc_offset; + int syss_offset; + u32 revision; + u32 revision_mask; + u32 quirks; +}; + +#define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ + optrev_val, optrevmask, optquirkmask) \ + { \ + .name = (optname), \ + .base = (optbase), \ + .rev_offset = (optrev), \ + .sysc_offset = (optsysc), \ + .syss_offset = (optsyss), \ + .revision = (optrev_val), \ + .revision_mask = (optrevmask), \ + .quirks = (optquirkmask), \ + } + +static const struct sysc_revision_quirk sysc_revision_quirks[] = { + /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ + SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, + SYSC_QUIRK_LEGACY_IDLE), +}; + +static void sysc_init_revision_quirks(struct sysc *ddata) +{ + const struct sysc_revision_quirk *q; + int i; + + for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { + q = &sysc_revision_quirks[i]; + + if (q->base && q->base != ddata->module_pa) + continue; + + if (q->rev_offset >= 0 && + q->rev_offset != ddata->offsets[SYSC_REVISION]) + continue; + + if (q->sysc_offset >= 0 && + q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) + continue; + + if (q->syss_offset >= 0 && + q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) + continue; + + if (q->revision == ddata->revision || + (q->revision & q->revision_mask) == + (ddata->revision & q->revision_mask)) { + ddata->name = q->name; + ddata->cfg.quirks |= q->quirks; + } + } +} + /* At this point the module is configured enough to read the revision */ static int sysc_init_module(struct sysc *ddata) { int error; + if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE_ON_INIT) { + ddata->revision = sysc_read_revision(ddata); + goto rev_quirks; + } + error = pm_runtime_get_sync(ddata->dev); if (error < 0) { pm_runtime_put_noidle(ddata->dev); @@ -626,6 +719,9 @@ static int sysc_init_module(struct sysc *ddata) ddata->revision = sysc_read_revision(ddata); pm_runtime_put_sync(ddata->dev); +rev_quirks: + sysc_init_revision_quirks(ddata); + return 0; } @@ -753,6 +849,127 @@ static struct sysc *sysc_child_to_parent(struct device *dev) return dev_get_drvdata(parent); } +static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) +{ + struct sysc *ddata; + int error; + + ddata = sysc_child_to_parent(dev); + + error = pm_generic_runtime_suspend(dev); + if (error) + return error; + + if (!ddata->enabled) + return 0; + + return sysc_runtime_suspend(ddata->dev); +} + +static int __maybe_unused sysc_child_runtime_resume(struct device *dev) +{ + struct sysc *ddata; + int error; + + ddata = sysc_child_to_parent(dev); + + if (!ddata->enabled) { + error = sysc_runtime_resume(ddata->dev); + if (error < 0) + dev_err(ddata->dev, + "%s error: %i\n", __func__, error); + } + + return pm_generic_runtime_resume(dev); +} + +#ifdef CONFIG_PM_SLEEP +static int sysc_child_suspend_noirq(struct device *dev) +{ + struct sysc *ddata; + int error; + + ddata = sysc_child_to_parent(dev); + + error = pm_generic_suspend_noirq(dev); + if (error) + return error; + + if (!pm_runtime_status_suspended(dev)) { + error = pm_generic_runtime_suspend(dev); + if (error) + return error; + + error = sysc_runtime_suspend(ddata->dev); + if (error) + return error; + + ddata->child_needs_resume = true; + } + + return 0; +} + +static int sysc_child_resume_noirq(struct device *dev) +{ + struct sysc *ddata; + int error; + + ddata = sysc_child_to_parent(dev); + + if (ddata->child_needs_resume) { + ddata->child_needs_resume = false; + + error = sysc_runtime_resume(ddata->dev); + if (error) + dev_err(ddata->dev, + "%s runtime resume error: %i\n", + __func__, error); + + error = pm_generic_runtime_resume(dev); + if (error) + dev_err(ddata->dev, + "%s generic runtime resume: %i\n", + __func__, error); + } + + return pm_generic_resume_noirq(dev); +} +#endif + +struct dev_pm_domain sysc_child_pm_domain = { + .ops = { + SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, + sysc_child_runtime_resume, + NULL) + USE_PLATFORM_PM_SLEEP_OPS + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, + sysc_child_resume_noirq) + } +}; + +/** + * sysc_legacy_idle_quirk - handle children in omap_device compatible way + * @ddata: device driver data + * @child: child device driver + * + * Allow idle for child devices as done with _od_runtime_suspend(). + * Otherwise many child devices will not idle because of the permanent + * parent usecount set in pm_runtime_irq_safe(). + * + * Note that the long term solution is to just modify the child device + * drivers to not set pm_runtime_irq_safe() and then this can be just + * dropped. + */ +static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) +{ + if (!ddata->legacy_mode) + return; + + if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) + dev_pm_domain_set(child, &sysc_child_pm_domain); +} + static int sysc_notifier_call(struct notifier_block *nb, unsigned long event, void *device) { @@ -770,6 +987,7 @@ static int sysc_notifier_call(struct notifier_block *nb, if (error && error != -EEXIST) dev_warn(ddata->dev, "could not add %s fck: %i\n", dev_name(dev), error); + sysc_legacy_idle_quirk(ddata, dev); break; default: break; @@ -974,7 +1192,8 @@ static const struct sysc_capabilities sysc_34xx_sr = { .type = TI_SYSC_OMAP34XX_SR, .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, .regbits = &sysc_regbits_omap34xx_sr, - .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED, + .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | + SYSC_QUIRK_LEGACY_IDLE, }; /* @@ -995,12 +1214,13 @@ static const struct sysc_capabilities sysc_36xx_sr = { .type = TI_SYSC_OMAP36XX_SR, .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, .regbits = &sysc_regbits_omap36xx_sr, - .mod_quirks = SYSC_QUIRK_UNCACHED, + .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, }; static const struct sysc_capabilities sysc_omap4_sr = { .type = TI_SYSC_OMAP4_SR, .regbits = &sysc_regbits_omap36xx_sr, + .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, }; /* diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index 4176cb90e195..80ce28d40832 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -45,6 +45,7 @@ struct sysc_regbits { s8 emufree_shift; }; +#define SYSC_QUIRK_LEGACY_IDLE BIT(8) #define SYSC_QUIRK_RESET_STATUS BIT(7) #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6) #define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5) -- cgit v1.2.3 From 41d9d44d725808f27b53f266733e6d17d83020ba Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Fri, 23 Feb 2018 09:43:56 -0600 Subject: ARM: OMAP2+: pm33xx-core: Add platform code needed for PM Most of the PM code needed for am335x and am437x can be moved into a module under drivers but some core code must remain in mach-omap2 at the moment. This includes some internal clockdomain APIs and low-level ARM APIs which are also not exported for use by modules. Implement a few functions that handle these low-level platform operations can be passed to the pm33xx module through the use of platform data. In addition to this, to be able to share data structures between C and the sleep33xx and sleep43xx assembly code, we can automatically generate all of the C struct member offsets and sizes as macros by processing pm-asm-offsets.c into assembly code and then extracting the relevant data as is done for the generated platform asm-offsets.h files. Finally, add amx3_common_pm_init to create a dummy platform_device for pm33xx so that our soon to be introduced pm33xx module can probe on am335x and am437x platforms to enable basic suspend to mem and standby support. Signed-off-by: Dave Gerlach Acked-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-omap2/Makefile | 16 +++ arch/arm/mach-omap2/common.h | 7 ++ arch/arm/mach-omap2/io.c | 2 + arch/arm/mach-omap2/pm-asm-offsets.c | 31 ++++++ arch/arm/mach-omap2/pm.h | 3 + arch/arm/mach-omap2/pm33xx-core.c | 189 +++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/sleep33xx.S | 2 + arch/arm/mach-omap2/sleep43xx.S | 2 + include/linux/platform_data/pm33xx.h | 42 ++++++++ 10 files changed, 295 insertions(+) create mode 100644 arch/arm/mach-omap2/pm-asm-offsets.c create mode 100644 arch/arm/mach-omap2/pm33xx-core.c create mode 100644 include/linux/platform_data/pm33xx.h (limited to 'include/linux/platform_data') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 00b1f17f8d44..9f27b486a536 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -72,6 +72,7 @@ config SOC_AM43XX select ARM_ERRATA_754322 select ARM_ERRATA_775420 select OMAP_INTERCONNECT + select ARM_CPU_SUSPEND if PM config SOC_DRA7XX bool "TI DRA7XX" diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index c15bbcad5f67..4603c30fef73 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -88,6 +88,8 @@ omap-4-5-pm-common += pm44xx.o obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common) obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common) obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-pm-common) +obj-$(CONFIG_SOC_AM33XX) += pm33xx-core.o sleep33xx.o +obj-$(CONFIG_SOC_AM43XX) += pm33xx-core.o sleep43xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o @@ -95,6 +97,8 @@ obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) +AFLAGS_sleep33xx.o :=-Wa,-march=armv7-a$(plus_sec) +AFLAGS_sleep43xx.o :=-Wa,-march=armv7-a$(plus_sec) endif @@ -232,3 +236,15 @@ obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) obj-y += omap_phy_internal.o obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o + +arch/arm/mach-omap2/pm-asm-offsets.s: arch/arm/mach-omap2/pm-asm-offsets.c + $(call if_changed_dep,cc_s_c) + +include/generated/ti-pm-asm-offsets.h: arch/arm/mach-omap2/pm-asm-offsets.s FORCE + $(call filechk,offsets,__TI_PM_ASM_OFFSETS_H__) + +# For rule to generate ti-emif-asm-offsets.h dependency +include drivers/memory/Makefile.asm-offsets + +arch/arm/mach-omap2/sleep33xx.o: include/generated/ti-pm-asm-offsets.h include/generated/ti-emif-asm-offsets.h +arch/arm/mach-omap2/sleep43xx.o: include/generated/ti-pm-asm-offsets.h include/generated/ti-emif-asm-offsets.h diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index bc202835371b..fbe0b78bf489 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -77,6 +77,13 @@ static inline int omap4_pm_init_early(void) } #endif +#if defined(CONFIG_PM) && (defined(CONFIG_SOC_AM33XX) || \ + defined(CONFIG_SOC_AM43XX)) +void amx3_common_pm_init(void); +#else +static inline void amx3_common_pm_init(void) { } +#endif + extern void omap2_init_common_infrastructure(void); extern void omap_init_time(void); diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index cb5d7314cf99..cf546dfe3b32 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -622,6 +622,7 @@ void __init am33xx_init_early(void) void __init am33xx_init_late(void) { omap_common_late_init(); + amx3_common_pm_init(); } #endif @@ -646,6 +647,7 @@ void __init am43xx_init_late(void) { omap_common_late_init(); omap2_clk_enable_autoidle_all(); + amx3_common_pm_init(); } #endif diff --git a/arch/arm/mach-omap2/pm-asm-offsets.c b/arch/arm/mach-omap2/pm-asm-offsets.c new file mode 100644 index 000000000000..6d4392da7c11 --- /dev/null +++ b/arch/arm/mach-omap2/pm-asm-offsets.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI AM33XX and AM43XX PM Assembly Offsets + * + * Copyright (C) 2017-2018 Texas Instruments Inc. + */ + +#include +#include + +int main(void) +{ + DEFINE(AMX3_PM_WFI_FLAGS_OFFSET, + offsetof(struct am33xx_pm_sram_data, wfi_flags)); + DEFINE(AMX3_PM_L2_AUX_CTRL_VAL_OFFSET, + offsetof(struct am33xx_pm_sram_data, l2_aux_ctrl_val)); + DEFINE(AMX3_PM_L2_PREFETCH_CTRL_VAL_OFFSET, + offsetof(struct am33xx_pm_sram_data, l2_prefetch_ctrl_val)); + DEFINE(AMX3_PM_SRAM_DATA_SIZE, sizeof(struct am33xx_pm_sram_data)); + + BLANK(); + + DEFINE(AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET, + offsetof(struct am33xx_pm_ro_sram_data, amx3_pm_sram_data_virt)); + DEFINE(AMX3_PM_RO_SRAM_DATA_PHYS_OFFSET, + offsetof(struct am33xx_pm_ro_sram_data, amx3_pm_sram_data_phys)); + DEFINE(AMX3_PM_RO_SRAM_DATA_SIZE, + sizeof(struct am33xx_pm_ro_sram_data)); + + return 0; +} diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 8e30772cfe32..c73776b82348 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -81,6 +81,9 @@ extern unsigned int omap3_do_wfi_sz; /* ... and its pointer from SRAM after copy */ extern void (*omap3_do_wfi_sram)(void); +extern struct am33xx_pm_sram_addr am33xx_pm_sram; +extern struct am33xx_pm_sram_addr am43xx_pm_sram; + extern void omap3_save_scratchpad_contents(void); #define PM_RTA_ERRATUM_i608 (1 << 0) diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c new file mode 100644 index 000000000000..93c0b5ba9f09 --- /dev/null +++ b/arch/arm/mach-omap2/pm33xx-core.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM33XX Arch Power Management Routines + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Dave Gerlach + */ + +#include +#include +#include +#include + +#include "cm33xx.h" +#include "common.h" +#include "control.h" +#include "clockdomain.h" +#include "iomap.h" +#include "omap_hwmod.h" +#include "pm.h" +#include "powerdomain.h" +#include "prm33xx.h" +#include "soc.h" +#include "sram.h" + +static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm; +static struct clockdomain *gfx_l4ls_clkdm; +static void __iomem *scu_base; + +static int __init am43xx_map_scu(void) +{ + scu_base = ioremap(scu_a9_get_base(), SZ_256); + + if (!scu_base) + return -ENOMEM; + + return 0; +} + +static int amx3_common_init(void) +{ + gfx_pwrdm = pwrdm_lookup("gfx_pwrdm"); + per_pwrdm = pwrdm_lookup("per_pwrdm"); + mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); + + if ((!gfx_pwrdm) || (!per_pwrdm) || (!mpu_pwrdm)) + return -ENODEV; + + (void)clkdm_for_each(omap_pm_clkdms_setup, NULL); + + /* CEFUSE domain can be turned off post bootup */ + cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm"); + if (cefuse_pwrdm) + omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF); + else + pr_err("PM: Failed to get cefuse_pwrdm\n"); + + return 0; +} + +static int am33xx_suspend_init(void) +{ + int ret; + + gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm"); + + if (!gfx_l4ls_clkdm) { + pr_err("PM: Cannot lookup gfx_l4ls_clkdm clockdomains\n"); + return -ENODEV; + } + + ret = amx3_common_init(); + + return ret; +} + +static int am43xx_suspend_init(void) +{ + int ret = 0; + + ret = am43xx_map_scu(); + if (ret) { + pr_err("PM: Could not ioremap SCU\n"); + return ret; + } + + ret = amx3_common_init(); + + return ret; +} + +static void amx3_pre_suspend_common(void) +{ + omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF); +} + +static void amx3_post_suspend_common(void) +{ + int status; + /* + * Because gfx_pwrdm is the only one under MPU control, + * comment on transition status + */ + status = pwrdm_read_pwrst(gfx_pwrdm); + if (status != PWRDM_POWER_OFF) + pr_err("PM: GFX domain did not transition: %x\n", status); +} + +static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long)) +{ + int ret = 0; + + amx3_pre_suspend_common(); + ret = cpu_suspend(0, fn); + amx3_post_suspend_common(); + + /* + * BUG: GFX_L4LS clock domain needs to be woken up to + * ensure thet L4LS clock domain does not get stuck in + * transition. If that happens L3 module does not get + * disabled, thereby leading to PER power domain + * transition failing + */ + + clkdm_wakeup(gfx_l4ls_clkdm); + clkdm_sleep(gfx_l4ls_clkdm); + + return ret; +} + +static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long)) +{ + int ret = 0; + + amx3_pre_suspend_common(); + scu_power_mode(scu_base, SCU_PM_POWEROFF); + ret = cpu_suspend(0, fn); + scu_power_mode(scu_base, SCU_PM_NORMAL); + amx3_post_suspend_common(); + + return ret; +} + +static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void) +{ + if (soc_is_am33xx()) + return &am33xx_pm_sram; + else if (soc_is_am437x()) + return &am43xx_pm_sram; + else + return NULL; +} + +static struct am33xx_pm_platform_data am33xx_ops = { + .init = am33xx_suspend_init, + .soc_suspend = am33xx_suspend, + .get_sram_addrs = amx3_get_sram_addrs, +}; + +static struct am33xx_pm_platform_data am43xx_ops = { + .init = am43xx_suspend_init, + .soc_suspend = am43xx_suspend, + .get_sram_addrs = amx3_get_sram_addrs, +}; + +static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void) +{ + if (soc_is_am33xx()) + return &am33xx_ops; + else if (soc_is_am437x()) + return &am43xx_ops; + else + return NULL; +} + +void __init amx3_common_pm_init(void) +{ + struct am33xx_pm_platform_data *pdata; + struct platform_device_info devinfo; + + pdata = am33xx_pm_get_pdata(); + + memset(&devinfo, 0, sizeof(devinfo)); + devinfo.name = "pm33xx"; + devinfo.data = pdata; + devinfo.size_data = sizeof(*pdata); + devinfo.id = -1; + platform_device_register_full(&devinfo); +} diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S index 04015f98b6e3..218d79930b04 100644 --- a/arch/arm/mach-omap2/sleep33xx.S +++ b/arch/arm/mach-omap2/sleep33xx.S @@ -6,6 +6,8 @@ * Dave Gerlach, Vaibhav Bedia */ +#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/sleep43xx.S b/arch/arm/mach-omap2/sleep43xx.S index 0defc735e319..59770a69396b 100644 --- a/arch/arm/mach-omap2/sleep43xx.S +++ b/arch/arm/mach-omap2/sleep43xx.S @@ -6,6 +6,8 @@ * Dave Gerlach, Vaibhav Bedia */ +#include +#include #include #include diff --git a/include/linux/platform_data/pm33xx.h b/include/linux/platform_data/pm33xx.h new file mode 100644 index 000000000000..f9bed2a0af9d --- /dev/null +++ b/include/linux/platform_data/pm33xx.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * TI pm33xx platform data + * + * Copyright (C) 2016-2018 Texas Instruments, Inc. + * Dave Gerlach + */ + +#ifndef _LINUX_PLATFORM_DATA_PM33XX_H +#define _LINUX_PLATFORM_DATA_PM33XX_H + +#include +#include + +#ifndef __ASSEMBLER__ +struct am33xx_pm_sram_addr { + void (*do_wfi)(void); + unsigned long *do_wfi_sz; + unsigned long *resume_offset; + unsigned long *emif_sram_table; + unsigned long *ro_sram_data; +}; + +struct am33xx_pm_platform_data { + int (*init)(void); + int (*soc_suspend)(unsigned int state, int (*fn)(unsigned long)); + struct am33xx_pm_sram_addr *(*get_sram_addrs)(void); +}; + +struct am33xx_pm_sram_data { + u32 wfi_flags; + u32 l2_aux_ctrl_val; + u32 l2_prefetch_ctrl_val; +} __packed __aligned(8); + +struct am33xx_pm_ro_sram_data { + u32 amx3_pm_sram_data_virt; + u32 amx3_pm_sram_data_phys; +} __packed __aligned(8); + +#endif /* __ASSEMBLER__ */ +#endif /* _LINUX_PLATFORM_DATA_PM33XX_H */ -- cgit v1.2.3 From 7576594c8e69f5a9e08c5b952d5139bb43574bbc Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 19 Feb 2018 23:35:54 +0100 Subject: mtd: nand: remove useless fields from pxa3xx NAND platform data The "enable arbiter" bit is available only for pxa3xx based platforms but it was experimentally shown that even if this bit is reserved, some Marvell platforms (64-bit) actually need it to be set. The driver always set this bit regardless of this property, which is harmless. Then this property is not needed. The "num_cs" field is always 1 and for a good reason, the old driver (pxa3xx_nand.c) could only handle one. The new driver that replaces it (marvell_nand.c) can handle more, but better use device tree for such description. As there is only one available chip select, there is no need for an array of partitions neither an array of partition numbers. Signed-off-by: Miquel Raynal Acked-by: Robert Jarzmik Signed-off-by: Boris Brezillon --- arch/arm/mach-mmp/aspenite.c | 6 ++-- arch/arm/mach-mmp/ttc_dkb.c | 5 +--- arch/arm/mach-pxa/cm-x300.c | 6 ++-- arch/arm/mach-pxa/colibri-pxa3xx.c | 6 ++-- arch/arm/mach-pxa/littleton.c | 6 ++-- arch/arm/mach-pxa/mxm8x10.c | 6 ++-- arch/arm/mach-pxa/raumfeld.c | 6 ++-- arch/arm/mach-pxa/zylonite.c | 6 ++-- drivers/mtd/nand/marvell_nand.c | 3 +- include/linux/platform_data/mtd-nand-pxa3xx.h | 43 ++++++++------------------- 10 files changed, 28 insertions(+), 65 deletions(-) (limited to 'include/linux/platform_data') diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c index d2283009a5ff..6c2ebf01893a 100644 --- a/arch/arm/mach-mmp/aspenite.c +++ b/arch/arm/mach-mmp/aspenite.c @@ -172,10 +172,8 @@ static struct mtd_partition aspenite_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data aspenite_nand_info = { - .enable_arbiter = 1, - .num_cs = 1, - .parts[0] = aspenite_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(aspenite_nand_partitions), + .parts = aspenite_nand_partitions, + .nr_parts = ARRAY_SIZE(aspenite_nand_partitions), }; static struct i2c_board_info aspenite_i2c_info[] __initdata = { diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index e0b6073c61a7..c7897fb2b6da 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c @@ -179,10 +179,7 @@ static struct mv_usb_platform_data ttc_usb_pdata = { #endif #if IS_ENABLED(CONFIG_MTD_NAND_MARVELL) -static struct pxa3xx_nand_platform_data dkb_nand_info = { - .enable_arbiter = 1, - .num_cs = 1, -}; +static struct pxa3xx_nand_platform_data dkb_nand_info = {}; #endif #if IS_ENABLED(CONFIG_MMP_DISP) diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index de1f8c995076..0e71799cab25 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -429,11 +429,9 @@ static struct mtd_partition cm_x300_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data cm_x300_nand_info = { - .enable_arbiter = 1, .keep_config = 1, - .num_cs = 1, - .parts[0] = cm_x300_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(cm_x300_nand_partitions), + .parts = cm_x300_nand_partitions, + .nr_parts = ARRAY_SIZE(cm_x300_nand_partitions), }; static void __init cm_x300_init_nand(void) diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index 3018eafd723e..e31a591e949f 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c @@ -138,11 +138,9 @@ static struct mtd_partition colibri_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data colibri_nand_info = { - .enable_arbiter = 1, .keep_config = 1, - .num_cs = 1, - .parts[0] = colibri_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(colibri_nand_partitions), + .parts = colibri_nand_partitions, + .nr_parts = ARRAY_SIZE(colibri_nand_partitions), }; void __init colibri_pxa3xx_init_nand(void) diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 193dccca1086..9e132b3e48c6 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -329,10 +329,8 @@ static struct mtd_partition littleton_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data littleton_nand_info = { - .enable_arbiter = 1, - .num_cs = 1, - .parts[0] = littleton_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(littleton_nand_partitions), + .parts = littleton_nand_partitions, + .nr_parts = ARRAY_SIZE(littleton_nand_partitions), }; static void __init littleton_init_nand(void) diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c index 5cc379c0626c..616b22397d73 100644 --- a/arch/arm/mach-pxa/mxm8x10.c +++ b/arch/arm/mach-pxa/mxm8x10.c @@ -389,11 +389,9 @@ static struct mtd_partition mxm_8x10_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data mxm_8x10_nand_info = { - .enable_arbiter = 1, .keep_config = 1, - .num_cs = 1, - .parts[0] = mxm_8x10_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(mxm_8x10_nand_partitions) + .parts = mxm_8x10_nand_partitions, + .nr_parts = ARRAY_SIZE(mxm_8x10_nand_partitions) }; static void __init mxm_8x10_nand_init(void) diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 4d5d05cf87d6..8c95ae58312a 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -346,11 +346,9 @@ static struct mtd_partition raumfeld_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data raumfeld_nand_info = { - .enable_arbiter = 1, .keep_config = 1, - .num_cs = 1, - .parts[0] = raumfeld_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(raumfeld_nand_partitions), + .parts = raumfeld_nand_partitions, + .nr_parts = ARRAY_SIZE(raumfeld_nand_partitions), }; /** diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 3a99fc054e96..d69de312d8d9 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -376,10 +376,8 @@ static struct mtd_partition zylonite_nand_partitions[] = { }; static struct pxa3xx_nand_platform_data zylonite_nand_info = { - .enable_arbiter = 1, - .num_cs = 1, - .parts[0] = zylonite_nand_partitions, - .nr_parts[0] = ARRAY_SIZE(zylonite_nand_partitions), + .parts = zylonite_nand_partitions, + .nr_parts = ARRAY_SIZE(zylonite_nand_partitions), }; static void __init zylonite_init_nand(void) diff --git a/drivers/mtd/nand/marvell_nand.c b/drivers/mtd/nand/marvell_nand.c index 2196f2a233d6..03805f9669da 100644 --- a/drivers/mtd/nand/marvell_nand.c +++ b/drivers/mtd/nand/marvell_nand.c @@ -2520,8 +2520,7 @@ static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc, if (pdata) /* Legacy bindings support only one chip */ - ret = mtd_device_register(mtd, pdata->parts[0], - pdata->nr_parts[0]); + ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); else ret = mtd_device_register(mtd, NULL, 0); if (ret) { diff --git a/include/linux/platform_data/mtd-nand-pxa3xx.h b/include/linux/platform_data/mtd-nand-pxa3xx.h index b42ad83cbc20..4fd0f592a2d2 100644 --- a/include/linux/platform_data/mtd-nand-pxa3xx.h +++ b/include/linux/platform_data/mtd-nand-pxa3xx.h @@ -6,41 +6,22 @@ #include /* - * Current pxa3xx_nand controller has two chip select which - * both be workable. - * - * Notice should be taken that: - * When you want to use this feature, you should not enable the - * keep configuration feature, for two chip select could be - * attached with different nand chip. The different page size - * and timing requirement make the keep configuration impossible. + * Current pxa3xx_nand controller has two chip select which both be workable but + * historically all platforms remaining on platform data used only one. Switch + * to device tree if you need more. */ - -/* The max num of chip select current support */ -#define NUM_CHIP_SELECT (2) struct pxa3xx_nand_platform_data { - - /* the data flash bus is shared between the Static Memory - * Controller and the Data Flash Controller, the arbiter - * controls the ownership of the bus - */ - int enable_arbiter; - - /* allow platform code to keep OBM/bootloader defined NFC config */ - int keep_config; - - /* indicate how many chip selects will be used */ - int num_cs; - - /* use an flash-based bad block table */ - bool flash_bbt; - - /* requested ECC strength and ECC step size */ + /* Keep OBM/bootloader NFC timing configuration */ + bool keep_config; + /* Use a flash-based bad block table */ + bool flash_bbt; + /* Requested ECC strength and ECC step size */ int ecc_strength, ecc_step_size; - - const struct mtd_partition *parts[NUM_CHIP_SELECT]; - unsigned int nr_parts[NUM_CHIP_SELECT]; + /* Partitions */ + const struct mtd_partition *parts; + unsigned int nr_parts; }; extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info); + #endif /* __ASM_ARCH_PXA3XX_NAND_H */ -- cgit v1.2.3 From f63109f0cb40bca848eef9bf096dfdb7def5e20d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 4 Mar 2018 23:37:22 +0100 Subject: gpio: htc-gpio: Include the right header This driver is a pure GPIO driver and should only include . Drop the include of from the platform data header as well, it serves no purpose. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-htc-egpio.c | 1 + include/linux/platform_data/gpio-htc-egpio.h | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'include/linux/platform_data') diff --git a/drivers/gpio/gpio-htc-egpio.c b/drivers/gpio/gpio-htc-egpio.c index 271356effb2e..516383934945 100644 --- a/drivers/gpio/gpio-htc-egpio.c +++ b/drivers/gpio/gpio-htc-egpio.c @@ -18,6 +18,7 @@ #include #include #include +#include struct egpio_chip { int reg_start; diff --git a/include/linux/platform_data/gpio-htc-egpio.h b/include/linux/platform_data/gpio-htc-egpio.h index b7baf1e42c55..9a3e78082883 100644 --- a/include/linux/platform_data/gpio-htc-egpio.h +++ b/include/linux/platform_data/gpio-htc-egpio.h @@ -6,8 +6,6 @@ #ifndef __HTC_EGPIO_H__ #define __HTC_EGPIO_H__ -#include - /* Descriptive values for all-in or all-out htc_egpio_chip descriptors. */ #define HTC_EGPIO_OUTPUT (~0) #define HTC_EGPIO_INPUT 0 -- cgit v1.2.3 From 2d172691515961cad2abb4bf1b15d187bf2106cf Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 15 Mar 2018 21:52:18 -0500 Subject: clk: davinci: New driver for davinci PLL clocks This adds a new driver for mach-davinci PLL clocks. This is porting the code from arch/arm/mach-davinci/clock.c to the common clock framework. Additionally, it adds device tree support for these clocks. The ifeq ($(CONFIG_COMMON_CLK), y) in the Makefile is needed to prevent compile errors until the clock code in arch/arm/mach-davinci is removed. Note: although there are similar clocks for TI Keystone we are not able to share the code for a few reasons. The keystone clocks are device tree only and use legacy one-node-per-clock bindings. Also the register layouts are a bit different, which would add even more if/else mess to the keystone clocks. And the keystone PLL driver doesn't support setting clock rates. Signed-off-by: David Lechner Signed-off-by: Stephen Boyd --- MAINTAINERS | 7 + drivers/clk/Makefile | 1 + drivers/clk/davinci/Makefile | 5 + drivers/clk/davinci/pll.c | 888 ++++++++++++++++++++++++++ drivers/clk/davinci/pll.h | 120 ++++ include/linux/platform_data/clk-davinci-pll.h | 21 + 6 files changed, 1042 insertions(+) create mode 100644 drivers/clk/davinci/Makefile create mode 100644 drivers/clk/davinci/pll.c create mode 100644 drivers/clk/davinci/pll.h create mode 100644 include/linux/platform_data/clk-davinci-pll.h (limited to 'include/linux/platform_data') diff --git a/MAINTAINERS b/MAINTAINERS index 3bdc260e36b7..e6b9f169a243 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13792,6 +13792,13 @@ F: arch/arm/mach-davinci/ F: drivers/i2c/busses/i2c-davinci.c F: arch/arm/boot/dts/da850* +TI DAVINCI SERIES CLOCK DRIVER +M: David Lechner +R: Sekhar Nori +S: Maintained +F: Documentation/devicetree/bindings/clock/ti/davinci/ +F: drivers/clk/davinci/ + TI DAVINCI SERIES GPIO DRIVER M: Keerthy L: linux-gpio@vger.kernel.org diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 71ec41e6364f..07ac0fdb71a9 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_ARCH_ARTPEC) += axis/ obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ +obj-$(CONFIG_ARCH_DAVINCI) += davinci/ obj-$(CONFIG_H8300) += h8300/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-y += imgtec/ diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile new file mode 100644 index 000000000000..d9673bd321e0 --- /dev/null +++ b/drivers/clk/davinci/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + +ifeq ($(CONFIG_COMMON_CLK), y) +obj-y += pll.o +endif diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c new file mode 100644 index 000000000000..bfa5b7e52d3d --- /dev/null +++ b/drivers/clk/davinci/pll.c @@ -0,0 +1,888 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PLL clock driver for TI Davinci SoCs + * + * Copyright (C) 2018 David Lechner + * + * Based on arch/arm/mach-davinci/clock.c + * Copyright (C) 2006-2007 Texas Instruments. + * Copyright (C) 2008-2009 Deep Root Systems, LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pll.h" + +#define MAX_NAME_SIZE 20 +#define OSCIN_CLK_NAME "oscin" + +#define REVID 0x000 +#define PLLCTL 0x100 +#define OCSEL 0x104 +#define PLLSECCTL 0x108 +#define PLLM 0x110 +#define PREDIV 0x114 +#define PLLDIV1 0x118 +#define PLLDIV2 0x11c +#define PLLDIV3 0x120 +#define OSCDIV 0x124 +#define POSTDIV 0x128 +#define BPDIV 0x12c +#define PLLCMD 0x138 +#define PLLSTAT 0x13c +#define ALNCTL 0x140 +#define DCHANGE 0x144 +#define CKEN 0x148 +#define CKSTAT 0x14c +#define SYSTAT 0x150 +#define PLLDIV4 0x160 +#define PLLDIV5 0x164 +#define PLLDIV6 0x168 +#define PLLDIV7 0x16c +#define PLLDIV8 0x170 +#define PLLDIV9 0x174 + +#define PLLCTL_PLLEN BIT(0) +#define PLLCTL_PLLPWRDN BIT(1) +#define PLLCTL_PLLRST BIT(3) +#define PLLCTL_PLLDIS BIT(4) +#define PLLCTL_PLLENSRC BIT(5) +#define PLLCTL_CLKMODE BIT(8) + +/* shared by most *DIV registers */ +#define DIV_RATIO_SHIFT 0 +#define DIV_RATIO_WIDTH 5 +#define DIV_ENABLE_SHIFT 15 + +#define PLLCMD_GOSET BIT(0) +#define PLLSTAT_GOSTAT BIT(0) + +#define CKEN_OBSCLK_SHIFT 1 +#define CKEN_AUXEN_SHIFT 0 + +/* + * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN + * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us + * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input + * is ~25MHz. Units are micro seconds. + */ +#define PLL_BYPASS_TIME 1 + +/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ +#define PLL_RESET_TIME 1 + +/* + * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 + * Units are micro seconds. + */ +#define PLL_LOCK_TIME 20 + +/** + * struct davinci_pll_clk - Main PLL clock (aka PLLOUT) + * @hw: clk_hw for the pll + * @base: Base memory address + * @pllm_min: The minimum allowable PLLM[PLLM] value + * @pllm_max: The maxiumum allowable PLLM[PLLM] value + * @pllm_mask: Bitmask for PLLM[PLLM] value + */ +struct davinci_pll_clk { + struct clk_hw hw; + void __iomem *base; + u32 pllm_min; + u32 pllm_max; + u32 pllm_mask; +}; + +#define to_davinci_pll_clk(_hw) \ + container_of((_hw), struct davinci_pll_clk, hw) + +static unsigned long davinci_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); + unsigned long rate = parent_rate; + u32 mult; + + mult = readl(pll->base + PLLM) & pll->pllm_mask; + rate *= mult + 1; + + return rate; +} + +static int davinci_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); + struct clk_hw *parent = req->best_parent_hw; + unsigned long parent_rate = req->best_parent_rate; + unsigned long rate = req->rate; + unsigned long best_rate, r; + u32 mult; + + /* there is a limited range of valid outputs (see datasheet) */ + if (rate < req->min_rate) + return -EINVAL; + + rate = min(rate, req->max_rate); + mult = rate / parent_rate; + best_rate = parent_rate * mult; + + /* easy case when there is no PREDIV */ + if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { + if (best_rate < req->min_rate) + return -EINVAL; + + if (mult < pll->pllm_min || mult > pll->pllm_max) + return -EINVAL; + + req->rate = best_rate; + + return 0; + } + + /* see if the PREDIV clock can help us */ + best_rate = 0; + + for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) { + parent_rate = clk_hw_round_rate(parent, rate / mult); + r = parent_rate * mult; + if (r < req->min_rate) + continue; + if (r > rate || r > req->max_rate) + break; + if (r > best_rate) { + best_rate = r; + req->rate = best_rate; + req->best_parent_rate = parent_rate; + if (best_rate == rate) + break; + } + } + + return 0; +} + +static int davinci_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); + u32 mult; + + mult = rate / parent_rate; + writel(mult - 1, pll->base + PLLM); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry); +#else +#define davinci_pll_debug_init NULL +#endif + +static const struct clk_ops davinci_pll_ops = { + .recalc_rate = davinci_pll_recalc_rate, + .determine_rate = davinci_pll_determine_rate, + .set_rate = davinci_pll_set_rate, + .debug_init = davinci_pll_debug_init, +}; + +/* PLLM works differently on DM365 */ +static unsigned long dm365_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); + unsigned long rate = parent_rate; + u32 mult; + + mult = readl(pll->base + PLLM) & pll->pllm_mask; + rate *= mult * 2; + + return rate; +} + +static const struct clk_ops dm365_pll_ops = { + .recalc_rate = dm365_pll_recalc_rate, + .debug_init = davinci_pll_debug_init, +}; + +/** + * davinci_pll_div_register - common *DIV clock implementation + * @name: the clock name + * @parent_name: the parent clock name + * @reg: the *DIV register + * @fixed: if true, the divider is a fixed value + * @flags: bitmap of CLK_* flags from clock-provider.h + */ +static struct clk *davinci_pll_div_register(struct device *dev, + const char *name, + const char *parent_name, + void __iomem *reg, + bool fixed, u32 flags) +{ + const char * const *parent_names = parent_name ? &parent_name : NULL; + int num_parents = parent_name ? 1 : 0; + const struct clk_ops *divider_ops = &clk_divider_ops; + struct clk_gate *gate; + struct clk_divider *divider; + + gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + gate->reg = reg; + gate->bit_idx = DIV_ENABLE_SHIFT; + + divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL); + if (!divider) + return ERR_PTR(-ENOMEM); + + divider->reg = reg; + divider->shift = DIV_RATIO_SHIFT; + divider->width = DIV_RATIO_WIDTH; + + if (fixed) { + divider->flags |= CLK_DIVIDER_READ_ONLY; + divider_ops = &clk_divider_ro_ops; + } + + return clk_register_composite(dev, name, parent_names, num_parents, + NULL, NULL, ÷r->hw, divider_ops, + &gate->hw, &clk_gate_ops, flags); +} + +struct davinci_pllen_clk { + struct clk_hw hw; + void __iomem *base; +}; + +#define to_davinci_pllen_clk(_hw) \ + container_of((_hw), struct davinci_pllen_clk, hw) + +static const struct clk_ops davinci_pllen_ops = { + /* this clocks just uses the clock notification feature */ +}; + +/* + * The PLL has to be switched into bypass mode while we are chaning the rate, + * so we do that on the PLLEN clock since it is the end of the line. This will + * switch to bypass before any of the parent clocks (PREDIV, PLL, POSTDIV) are + * changed and will switch back to the PLL after the changes have been made. + */ +static int davinci_pllen_rate_change(struct notifier_block *nb, + unsigned long flags, void *data) +{ + struct clk_notifier_data *cnd = data; + struct clk_hw *hw = __clk_get_hw(cnd->clk); + struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw); + u32 ctrl; + + ctrl = readl(pll->base + PLLCTL); + + if (flags == PRE_RATE_CHANGE) { + /* Switch the PLL to bypass mode */ + ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); + writel(ctrl, pll->base + PLLCTL); + + udelay(PLL_BYPASS_TIME); + + /* Reset and enable PLL */ + ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); + writel(ctrl, pll->base + PLLCTL); + } else { + udelay(PLL_RESET_TIME); + + /* Bring PLL out of reset */ + ctrl |= PLLCTL_PLLRST; + writel(ctrl, pll->base + PLLCTL); + + udelay(PLL_LOCK_TIME); + + /* Remove PLL from bypass mode */ + ctrl |= PLLCTL_PLLEN; + writel(ctrl, pll->base + PLLCTL); + } + + return NOTIFY_OK; +} + +static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *dev) +{ + struct davinci_pll_platform_data *pdata = dev_get_platdata(dev); + + /* + * Platform data is optional, so allocate a new struct if one was not + * provided. For device tree, this will always be the case. + */ + if (!pdata) + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return NULL; + + /* for device tree, we need to fill in the struct */ + if (dev->of_node) + pdata->cfgchip = + syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); + + return pdata; +} + +static struct notifier_block davinci_pllen_notifier = { + .notifier_call = davinci_pllen_rate_change, +}; + +/** + * davinci_pll_clk_register - Register a PLL clock + * @info: The device-specific clock info + * @parent_name: The parent clock name + * @base: The PLL's memory region + * + * This creates a series of clocks that represent the PLL. + * + * OSCIN > [PREDIV >] PLL > [POSTDIV >] PLLEN + * + * - OSCIN is the parent clock (on secondary PLL, may come from primary PLL) + * - PREDIV and POSTDIV are optional (depends on the PLL controller) + * - PLL is the PLL output (aka PLLOUT) + * - PLLEN is the bypass multiplexer + * + * Returns: The PLLOUT clock or a negative error code. + */ +struct clk *davinci_pll_clk_register(struct device *dev, + const struct davinci_pll_clk_info *info, + const char *parent_name, + void __iomem *base) +{ + struct davinci_pll_platform_data *pdata; + char prediv_name[MAX_NAME_SIZE]; + char pllout_name[MAX_NAME_SIZE]; + char postdiv_name[MAX_NAME_SIZE]; + char pllen_name[MAX_NAME_SIZE]; + struct clk_init_data init; + struct davinci_pll_clk *pllout; + struct davinci_pllen_clk *pllen; + struct clk *pllout_clk, *clk; + + pdata = davinci_pll_get_pdata(dev); + if (!pdata) + return ERR_PTR(-ENOMEM); + + if (info->flags & PLL_HAS_CLKMODE) { + /* + * If a PLL has PLLCTL[CLKMODE], then it is the primary PLL. + * We register a clock named "oscin" that serves as the internal + * "input clock" domain shared by both PLLs (if there are 2) + * and will be the parent clock to the AUXCLK, SYSCLKBP and + * OBSCLK domains. NB: The various TRMs use "OSCIN" to mean + * a number of different things. In this driver we use it to + * mean the signal after the PLLCTL[CLKMODE] switch. + */ + clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME, + parent_name, 0, 1, 1); + if (IS_ERR(clk)) + return clk; + + parent_name = OSCIN_CLK_NAME; + } + + if (info->flags & PLL_HAS_PREDIV) { + bool fixed = info->flags & PLL_PREDIV_FIXED_DIV; + u32 flags = 0; + + snprintf(prediv_name, MAX_NAME_SIZE, "%s_prediv", info->name); + + if (info->flags & PLL_PREDIV_ALWAYS_ENABLED) + flags |= CLK_IS_CRITICAL; + + /* Some? DM355 chips don't correctly report the PREDIV value */ + if (info->flags & PLL_PREDIV_FIXED8) + clk = clk_register_fixed_factor(dev, prediv_name, + parent_name, flags, 1, 8); + else + clk = davinci_pll_div_register(dev, prediv_name, + parent_name, base + PREDIV, fixed, flags); + if (IS_ERR(clk)) + return clk; + + parent_name = prediv_name; + } + + /* Unlock writing to PLL registers */ + if (info->unlock_reg) { + if (IS_ERR_OR_NULL(pdata->cfgchip)) + dev_warn(dev, "Failed to get CFGCHIP (%ld)\n", + PTR_ERR(pdata->cfgchip)); + else + regmap_write_bits(pdata->cfgchip, info->unlock_reg, + info->unlock_mask, 0); + } + + pllout = devm_kzalloc(dev, sizeof(*pllout), GFP_KERNEL); + if (!pllout) + return ERR_PTR(-ENOMEM); + + snprintf(pllout_name, MAX_NAME_SIZE, "%s_pllout", info->name); + + init.name = pllout_name; + if (info->flags & PLL_PLLM_2X) + init.ops = &dm365_pll_ops; + else + init.ops = &davinci_pll_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = 0; + + if (info->flags & PLL_HAS_PREDIV) + init.flags |= CLK_SET_RATE_PARENT; + + pllout->hw.init = &init; + pllout->base = base; + pllout->pllm_mask = info->pllm_mask; + pllout->pllm_min = info->pllm_min; + pllout->pllm_max = info->pllm_max; + + pllout_clk = devm_clk_register(dev, &pllout->hw); + if (IS_ERR(pllout_clk)) + return pllout_clk; + + clk_hw_set_rate_range(&pllout->hw, info->pllout_min_rate, + info->pllout_max_rate); + + parent_name = pllout_name; + + if (info->flags & PLL_HAS_POSTDIV) { + bool fixed = info->flags & PLL_POSTDIV_FIXED_DIV; + u32 flags = CLK_SET_RATE_PARENT; + + snprintf(postdiv_name, MAX_NAME_SIZE, "%s_postdiv", info->name); + + if (info->flags & PLL_POSTDIV_ALWAYS_ENABLED) + flags |= CLK_IS_CRITICAL; + + clk = davinci_pll_div_register(dev, postdiv_name, parent_name, + base + POSTDIV, fixed, flags); + if (IS_ERR(clk)) + return clk; + + parent_name = postdiv_name; + } + + pllen = devm_kzalloc(dev, sizeof(*pllout), GFP_KERNEL); + if (!pllen) + return ERR_PTR(-ENOMEM); + + snprintf(pllen_name, MAX_NAME_SIZE, "%s_pllen", info->name); + + init.name = pllen_name; + init.ops = &davinci_pllen_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = CLK_SET_RATE_PARENT; + + pllen->hw.init = &init; + pllen->base = base; + + clk = devm_clk_register(dev, &pllen->hw); + if (IS_ERR(clk)) + return clk; + + clk_notifier_register(clk, &davinci_pllen_notifier); + + return pllout_clk; +} + +/** + * davinci_pll_auxclk_register - Register bypass clock (AUXCLK) + * @name: The clock name + * @base: The PLL memory region + */ +struct clk *davinci_pll_auxclk_register(struct device *dev, + const char *name, + void __iomem *base) +{ + return clk_register_gate(dev, name, OSCIN_CLK_NAME, 0, base + CKEN, + CKEN_AUXEN_SHIFT, 0, NULL); +} + +/** + * davinci_pll_sysclkbp_clk_register - Register bypass divider clock (SYSCLKBP) + * @name: The clock name + * @base: The PLL memory region + */ +struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev, + const char *name, + void __iomem *base) +{ + return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV, + DIV_RATIO_SHIFT, DIV_RATIO_WIDTH, + CLK_DIVIDER_READ_ONLY, NULL); +} + +/** + * davinci_pll_obsclk_register - Register oscillator divider clock (OBSCLK) + * @info: The clock info + * @base: The PLL memory region + */ +struct clk * +davinci_pll_obsclk_register(struct device *dev, + const struct davinci_pll_obsclk_info *info, + void __iomem *base) +{ + struct clk_mux *mux; + struct clk_gate *gate; + struct clk_divider *divider; + u32 oscdiv; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + + mux->reg = base + OCSEL; + mux->table = info->table; + mux->mask = info->ocsrc_mask; + + gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + gate->reg = base + CKEN; + gate->bit_idx = CKEN_OBSCLK_SHIFT; + + divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL); + if (!divider) + return ERR_PTR(-ENOMEM); + + divider->reg = base + OSCDIV; + divider->shift = DIV_RATIO_SHIFT; + divider->width = DIV_RATIO_WIDTH; + + /* make sure divider is enabled just in case bootloader disabled it */ + oscdiv = readl(base + OSCDIV); + oscdiv |= BIT(DIV_ENABLE_SHIFT); + writel(oscdiv, base + OSCDIV); + + return clk_register_composite(dev, info->name, info->parent_names, + info->num_parents, + &mux->hw, &clk_mux_ops, + ÷r->hw, &clk_divider_ops, + &gate->hw, &clk_gate_ops, 0); +} + +/* The PLL SYSCLKn clocks have a mechanism for synchronizing rate changes. */ +static int davinci_pll_sysclk_rate_change(struct notifier_block *nb, + unsigned long flags, void *data) +{ + struct clk_notifier_data *cnd = data; + struct clk_hw *hw = __clk_get_hw(clk_get_parent(cnd->clk)); + struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw); + u32 pllcmd, pllstat; + + switch (flags) { + case POST_RATE_CHANGE: + /* apply the changes */ + pllcmd = readl(pll->base + PLLCMD); + pllcmd |= PLLCMD_GOSET; + writel(pllcmd, pll->base + PLLCMD); + /* fallthrough */ + case PRE_RATE_CHANGE: + /* Wait until for outstanding changes to take effect */ + do { + pllstat = readl(pll->base + PLLSTAT); + } while (pllstat & PLLSTAT_GOSTAT); + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block davinci_pll_sysclk_notifier = { + .notifier_call = davinci_pll_sysclk_rate_change, +}; + +/** + * davinci_pll_sysclk_register - Register divider clocks (SYSCLKn) + * @info: The clock info + * @base: The PLL memory region + */ +struct clk * +davinci_pll_sysclk_register(struct device *dev, + const struct davinci_pll_sysclk_info *info, + void __iomem *base) +{ + const struct clk_ops *divider_ops = &clk_divider_ops; + struct clk_gate *gate; + struct clk_divider *divider; + struct clk *clk; + u32 reg; + u32 flags = 0; + + /* PLLDIVn registers are not entirely consecutive */ + if (info->id < 4) + reg = PLLDIV1 + 4 * (info->id - 1); + else + reg = PLLDIV4 + 4 * (info->id - 4); + + gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + gate->reg = base + reg; + gate->bit_idx = DIV_ENABLE_SHIFT; + + divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL); + if (!divider) + return ERR_PTR(-ENOMEM); + + divider->reg = base + reg; + divider->shift = DIV_RATIO_SHIFT; + divider->width = info->ratio_width; + divider->flags = 0; + + if (info->flags & SYSCLK_FIXED_DIV) { + divider->flags |= CLK_DIVIDER_READ_ONLY; + divider_ops = &clk_divider_ro_ops; + } + + /* Only the ARM clock can change the parent PLL rate */ + if (info->flags & SYSCLK_ARM_RATE) + flags |= CLK_SET_RATE_PARENT; + + if (info->flags & SYSCLK_ALWAYS_ENABLED) + flags |= CLK_IS_CRITICAL; + + clk = clk_register_composite(dev, info->name, &info->parent_name, 1, + NULL, NULL, ÷r->hw, divider_ops, + &gate->hw, &clk_gate_ops, flags); + if (IS_ERR(clk)) + return clk; + + clk_notifier_register(clk, &davinci_pll_sysclk_notifier); + + return clk; +} + +int of_davinci_pll_init(struct device *dev, + const struct davinci_pll_clk_info *info, + const struct davinci_pll_obsclk_info *obsclk_info, + const struct davinci_pll_sysclk_info **div_info, + u8 max_sysclk_id, + void __iomem *base) +{ + struct device_node *node = dev->of_node; + struct device_node *child; + const char *parent_name; + struct clk *clk; + + if (info->flags & PLL_HAS_CLKMODE) + parent_name = of_clk_get_parent_name(node, 0); + else + parent_name = OSCIN_CLK_NAME; + + clk = davinci_pll_clk_register(dev, info, parent_name, base); + if (IS_ERR(clk)) { + dev_err(dev, "failed to register %s\n", info->name); + return PTR_ERR(clk); + } + + child = of_get_child_by_name(node, "pllout"); + if (of_device_is_available(child)) + of_clk_add_provider(child, of_clk_src_simple_get, clk); + of_node_put(child); + + child = of_get_child_by_name(node, "sysclk"); + if (of_device_is_available(child)) { + struct clk_onecell_data *clk_data; + struct clk **clks; + int n_clks = max_sysclk_id + 1; + int i; + + clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clks = devm_kmalloc_array(dev, n_clks, sizeof(*clks), GFP_KERNEL); + if (!clks) + return -ENOMEM; + + clk_data->clks = clks; + clk_data->clk_num = n_clks; + + for (i = 0; i < n_clks; i++) + clks[i] = ERR_PTR(-ENOENT); + + for (; *div_info; div_info++) { + clk = davinci_pll_sysclk_register(dev, *div_info, base); + if (IS_ERR(clk)) + dev_warn(dev, "failed to register %s (%ld)\n", + (*div_info)->name, PTR_ERR(clk)); + else + clks[(*div_info)->id] = clk; + } + of_clk_add_provider(child, of_clk_src_onecell_get, clk_data); + } + of_node_put(child); + + child = of_get_child_by_name(node, "auxclk"); + if (of_device_is_available(child)) { + char child_name[MAX_NAME_SIZE]; + + snprintf(child_name, MAX_NAME_SIZE, "%s_auxclk", info->name); + + clk = davinci_pll_auxclk_register(dev, child_name, base); + if (IS_ERR(clk)) + dev_warn(dev, "failed to register %s (%ld)\n", + child_name, PTR_ERR(clk)); + else + of_clk_add_provider(child, of_clk_src_simple_get, clk); + } + of_node_put(child); + + child = of_get_child_by_name(node, "obsclk"); + if (of_device_is_available(child)) { + if (obsclk_info) + clk = davinci_pll_obsclk_register(dev, obsclk_info, base); + else + clk = ERR_PTR(-EINVAL); + + if (IS_ERR(clk)) + dev_warn(dev, "failed to register obsclk (%ld)\n", + PTR_ERR(clk)); + else + of_clk_add_provider(child, of_clk_src_simple_get, clk); + } + of_node_put(child); + + return 0; +} + +static const struct of_device_id davinci_pll_of_match[] = { + { } +}; + +static const struct platform_device_id davinci_pll_id_table[] = { + { } +}; + +typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base); + +static int davinci_pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct of_device_id *of_id; + davinci_pll_init pll_init = NULL; + struct resource *res; + void __iomem *base; + + of_id = of_match_device(davinci_pll_of_match, dev); + if (of_id) + pll_init = of_id->data; + else if (pdev->id_entry) + pll_init = (void *)pdev->id_entry->driver_data; + + if (!pll_init) { + dev_err(dev, "unable to find driver data\n"); + return -EINVAL; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) { + dev_err(dev, "ioremap failed\n"); + return PTR_ERR(base); + } + + return pll_init(dev, base); +} + +static struct platform_driver davinci_pll_driver = { + .probe = davinci_pll_probe, + .driver = { + .name = "davinci-pll-clk", + .of_match_table = davinci_pll_of_match, + }, + .id_table = davinci_pll_id_table, +}; + +static int __init davinci_pll_driver_init(void) +{ + return platform_driver_register(&davinci_pll_driver); +} + +/* has to be postcore_initcall because PSC devices depend on PLL parent clocks */ +postcore_initcall(davinci_pll_driver_init); + +#ifdef CONFIG_DEBUG_FS +#include + +#define DEBUG_REG(n) \ +{ \ + .name = #n, \ + .offset = n, \ +} + +static const struct debugfs_reg32 davinci_pll_regs[] = { + DEBUG_REG(REVID), + DEBUG_REG(PLLCTL), + DEBUG_REG(OCSEL), + DEBUG_REG(PLLSECCTL), + DEBUG_REG(PLLM), + DEBUG_REG(PREDIV), + DEBUG_REG(PLLDIV1), + DEBUG_REG(PLLDIV2), + DEBUG_REG(PLLDIV3), + DEBUG_REG(OSCDIV), + DEBUG_REG(POSTDIV), + DEBUG_REG(BPDIV), + DEBUG_REG(PLLCMD), + DEBUG_REG(PLLSTAT), + DEBUG_REG(ALNCTL), + DEBUG_REG(DCHANGE), + DEBUG_REG(CKEN), + DEBUG_REG(CKSTAT), + DEBUG_REG(SYSTAT), + DEBUG_REG(PLLDIV4), + DEBUG_REG(PLLDIV5), + DEBUG_REG(PLLDIV6), + DEBUG_REG(PLLDIV7), + DEBUG_REG(PLLDIV8), + DEBUG_REG(PLLDIV9), +}; + +static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry) +{ + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); + struct debugfs_regset32 *regset; + struct dentry *d; + + regset = kzalloc(sizeof(*regset), GFP_KERNEL); + if (!regset) + return -ENOMEM; + + regset->regs = davinci_pll_regs; + regset->nregs = ARRAY_SIZE(davinci_pll_regs); + regset->base = pll->base; + + d = debugfs_create_regset32("registers", 0400, dentry, regset); + if (IS_ERR(d)) { + kfree(regset); + return PTR_ERR(d); + } + + return 0; +} +#endif diff --git a/drivers/clk/davinci/pll.h b/drivers/clk/davinci/pll.h new file mode 100644 index 000000000000..52103aeeceec --- /dev/null +++ b/drivers/clk/davinci/pll.h @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock driver for TI Davinci PSC controllers + * + * Copyright (C) 2018 David Lechner + */ + +#ifndef __CLK_DAVINCI_PLL_H___ +#define __CLK_DAVINCI_PLL_H___ + +#include +#include +#include +#include + +#define PLL_HAS_CLKMODE BIT(0) /* PLL has PLLCTL[CLKMODE] */ +#define PLL_HAS_PREDIV BIT(1) /* has prediv before PLL */ +#define PLL_PREDIV_ALWAYS_ENABLED BIT(2) /* don't clear DEN bit */ +#define PLL_PREDIV_FIXED_DIV BIT(3) /* fixed divider value */ +#define PLL_HAS_POSTDIV BIT(4) /* has postdiv after PLL */ +#define PLL_POSTDIV_ALWAYS_ENABLED BIT(5) /* don't clear DEN bit */ +#define PLL_POSTDIV_FIXED_DIV BIT(6) /* fixed divider value */ +#define PLL_HAS_EXTCLKSRC BIT(7) /* has selectable bypass */ +#define PLL_PLLM_2X BIT(8) /* PLLM value is 2x (DM365) */ +#define PLL_PREDIV_FIXED8 BIT(9) /* DM355 quirk */ + +/** davinci_pll_clk_info - controller-specific PLL info + * @name: The name of the PLL + * @unlock_reg: Option CFGCHIP register for unlocking PLL + * @unlock_mask: Bitmask used with @unlock_reg + * @pllm_mask: Bitmask for PLLM[PLLM] value + * @pllm_min: Minimum allowable value for PLLM[PLLM] + * @pllm_max: Maximum allowable value for PLLM[PLLM] + * @pllout_min_rate: Minimum allowable rate for PLLOUT + * @pllout_max_rate: Maximum allowable rate for PLLOUT + * @flags: Bitmap of PLL_* flags. + */ +struct davinci_pll_clk_info { + const char *name; + u32 unlock_reg; + u32 unlock_mask; + u32 pllm_mask; + u32 pllm_min; + u32 pllm_max; + unsigned long pllout_min_rate; + unsigned long pllout_max_rate; + u32 flags; +}; + +#define SYSCLK_ARM_RATE BIT(0) /* Controls ARM rate */ +#define SYSCLK_ALWAYS_ENABLED BIT(1) /* Or bad things happen */ +#define SYSCLK_FIXED_DIV BIT(2) /* Fixed divider */ + +/** davinci_pll_sysclk_info - SYSCLKn-specific info + * @name: The name of the clock + * @parent_name: The name of the parent clock + * @id: "n" in "SYSCLKn" + * @ratio_width: Width (in bits) of RATIO in PLLDIVn register + * @flags: Bitmap of SYSCLK_* flags. + */ +struct davinci_pll_sysclk_info { + const char *name; + const char *parent_name; + u32 id; + u32 ratio_width; + u32 flags; +}; + +#define SYSCLK(i, n, p, w, f) \ +static const struct davinci_pll_sysclk_info n = { \ + .name = #n, \ + .parent_name = #p, \ + .id = (i), \ + .ratio_width = (w), \ + .flags = (f), \ +} + +/** davinci_pll_obsclk_info - OBSCLK-specific info + * @name: The name of the clock + * @parent_names: Array of names of the parent clocks + * @num_parents: Length of @parent_names + * @table: Array of values to write to OCSEL[OCSRC] cooresponding to + * @parent_names + * @ocsrc_mask: Bitmask for OCSEL[OCSRC] + */ +struct davinci_pll_obsclk_info { + const char *name; + const char * const *parent_names; + u8 num_parents; + u32 *table; + u32 ocsrc_mask; +}; + +struct clk *davinci_pll_clk_register(struct device *dev, + const struct davinci_pll_clk_info *info, + const char *parent_name, + void __iomem *base); +struct clk *davinci_pll_auxclk_register(struct device *dev, + const char *name, + void __iomem *base); +struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev, + const char *name, + void __iomem *base); +struct clk * +davinci_pll_obsclk_register(struct device *dev, + const struct davinci_pll_obsclk_info *info, + void __iomem *base); +struct clk * +davinci_pll_sysclk_register(struct device *dev, + const struct davinci_pll_sysclk_info *info, + void __iomem *base); + +int of_davinci_pll_init(struct device *dev, + const struct davinci_pll_clk_info *info, + const struct davinci_pll_obsclk_info *obsclk_info, + const struct davinci_pll_sysclk_info **div_info, + u8 max_sysclk_id, + void __iomem *base); + +#endif /* __CLK_DAVINCI_PLL_H___ */ diff --git a/include/linux/platform_data/clk-davinci-pll.h b/include/linux/platform_data/clk-davinci-pll.h new file mode 100644 index 000000000000..e55dab1d578b --- /dev/null +++ b/include/linux/platform_data/clk-davinci-pll.h @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PLL clock driver for TI Davinci SoCs + * + * Copyright (C) 2018 David Lechner + */ + +#ifndef __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__ +#define __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__ + +#include + +/** + * davinci_pll_platform_data + * @cfgchip: CFGCHIP syscon regmap + */ +struct davinci_pll_platform_data { + struct regmap *cfgchip; +}; + +#endif /* __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__ */ -- cgit v1.2.3 From 1e88a8d64f221208801bb279ee7452df0b6d609f Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 15 Mar 2018 21:52:34 -0500 Subject: clk: davinci: New driver for TI DA8XX CFGCHIP clocks This adds a new driver for the gate and multiplexer clocks in the CFGCHIPn syscon registers on TI DA8XX-type SoCs. Signed-off-by: David Lechner Signed-off-by: Stephen Boyd --- drivers/clk/davinci/Makefile | 2 + drivers/clk/davinci/da8xx-cfgchip.c | 439 ++++++++++++++++++++++++ include/linux/platform_data/clk-da8xx-cfgchip.h | 21 ++ 3 files changed, 462 insertions(+) create mode 100644 drivers/clk/davinci/da8xx-cfgchip.c create mode 100644 include/linux/platform_data/clk-da8xx-cfgchip.h (limited to 'include/linux/platform_data') diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile index 6c388d44162d..11178b79b483 100644 --- a/drivers/clk/davinci/Makefile +++ b/drivers/clk/davinci/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 ifeq ($(CONFIG_COMMON_CLK), y) +obj-$(CONFIG_ARCH_DAVINCI_DA8XX) += da8xx-cfgchip.o + obj-y += pll.o obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o diff --git a/drivers/clk/davinci/da8xx-cfgchip.c b/drivers/clk/davinci/da8xx-cfgchip.c new file mode 100644 index 000000000000..880a77ace273 --- /dev/null +++ b/drivers/clk/davinci/da8xx-cfgchip.c @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP + * + * Copyright (C) 2018 David Lechner + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* --- Gate clocks --- */ + +#define DA8XX_GATE_CLOCK_IS_DIV4P5 BIT(1) + +struct da8xx_cfgchip_gate_clk_info { + const char *name; + u32 cfgchip; + u32 bit; + u32 flags; +}; + +struct da8xx_cfgchip_gate_clk { + struct clk_hw hw; + struct regmap *regmap; + u32 reg; + u32 mask; +}; + +#define to_da8xx_cfgchip_gate_clk(_hw) \ + container_of((_hw), struct da8xx_cfgchip_gate_clk, hw) + +static int da8xx_cfgchip_gate_clk_enable(struct clk_hw *hw) +{ + struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); + + return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask); +} + +static void da8xx_cfgchip_gate_clk_disable(struct clk_hw *hw) +{ + struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); + + regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0); +} + +static int da8xx_cfgchip_gate_clk_is_enabled(struct clk_hw *hw) +{ + struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); + unsigned int val; + + regmap_read(clk->regmap, clk->reg, &val); + + return !!(val & clk->mask); +} + +static unsigned long da8xx_cfgchip_div4p5_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + /* this clock divides by 4.5 */ + return parent_rate * 2 / 9; +} + +static const struct clk_ops da8xx_cfgchip_gate_clk_ops = { + .enable = da8xx_cfgchip_gate_clk_enable, + .disable = da8xx_cfgchip_gate_clk_disable, + .is_enabled = da8xx_cfgchip_gate_clk_is_enabled, +}; + +static const struct clk_ops da8xx_cfgchip_div4p5_clk_ops = { + .enable = da8xx_cfgchip_gate_clk_enable, + .disable = da8xx_cfgchip_gate_clk_disable, + .is_enabled = da8xx_cfgchip_gate_clk_is_enabled, + .recalc_rate = da8xx_cfgchip_div4p5_recalc_rate, +}; + +static struct da8xx_cfgchip_gate_clk * __init +da8xx_cfgchip_gate_clk_register(struct device *dev, + const struct da8xx_cfgchip_gate_clk_info *info, + struct regmap *regmap) +{ + struct clk *parent; + const char *parent_name; + struct da8xx_cfgchip_gate_clk *gate; + struct clk_init_data init; + int ret; + + parent = devm_clk_get(dev, NULL); + if (IS_ERR(parent)) + return ERR_CAST(parent); + + parent_name = __clk_get_name(parent); + + gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name = info->name; + if (info->flags & DA8XX_GATE_CLOCK_IS_DIV4P5) + init.ops = &da8xx_cfgchip_div4p5_clk_ops; + else + init.ops = &da8xx_cfgchip_gate_clk_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = 0; + + gate->hw.init = &init; + gate->regmap = regmap; + gate->reg = info->cfgchip; + gate->mask = info->bit; + + ret = devm_clk_hw_register(dev, &gate->hw); + if (ret < 0) + return ERR_PTR(ret); + + return gate; +} + +static const struct da8xx_cfgchip_gate_clk_info da8xx_tbclksync_info __initconst = { + .name = "ehrpwm_tbclk", + .cfgchip = CFGCHIP(1), + .bit = CFGCHIP1_TBCLKSYNC, +}; + +static int __init da8xx_cfgchip_register_tbclk(struct device *dev, + struct regmap *regmap) +{ + struct da8xx_cfgchip_gate_clk *gate; + + gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_tbclksync_info, + regmap); + if (IS_ERR(gate)) + return PTR_ERR(gate); + + clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.0"); + clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.1"); + + return 0; +} + +static const struct da8xx_cfgchip_gate_clk_info da8xx_div4p5ena_info __initconst = { + .name = "div4.5", + .cfgchip = CFGCHIP(3), + .bit = CFGCHIP3_DIV45PENA, + .flags = DA8XX_GATE_CLOCK_IS_DIV4P5, +}; + +static int __init da8xx_cfgchip_register_div4p5(struct device *dev, + struct regmap *regmap) +{ + struct da8xx_cfgchip_gate_clk *gate; + + gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_div4p5ena_info, regmap); + if (IS_ERR(gate)) + return PTR_ERR(gate); + + return 0; +} + +static int __init +of_da8xx_cfgchip_gate_clk_init(struct device *dev, + const struct da8xx_cfgchip_gate_clk_info *info, + struct regmap *regmap) +{ + struct da8xx_cfgchip_gate_clk *gate; + + gate = da8xx_cfgchip_gate_clk_register(dev, info, regmap); + if (IS_ERR(gate)) + return PTR_ERR(gate); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, gate); +} + +static int __init of_da8xx_tbclksync_init(struct device *dev, + struct regmap *regmap) +{ + return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_tbclksync_info, regmap); +} + +static int __init of_da8xx_div4p5ena_init(struct device *dev, + struct regmap *regmap) +{ + return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_div4p5ena_info, regmap); +} + +/* --- MUX clocks --- */ + +struct da8xx_cfgchip_mux_clk_info { + const char *name; + const char *parent0; + const char *parent1; + u32 cfgchip; + u32 bit; +}; + +struct da8xx_cfgchip_mux_clk { + struct clk_hw hw; + struct regmap *regmap; + u32 reg; + u32 mask; +}; + +#define to_da8xx_cfgchip_mux_clk(_hw) \ + container_of((_hw), struct da8xx_cfgchip_mux_clk, hw) + +static int da8xx_cfgchip_mux_clk_set_parent(struct clk_hw *hw, u8 index) +{ + struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw); + unsigned int val = index ? clk->mask : 0; + + return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val); +} + +static u8 da8xx_cfgchip_mux_clk_get_parent(struct clk_hw *hw) +{ + struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw); + unsigned int val; + + regmap_read(clk->regmap, clk->reg, &val); + + return (val & clk->mask) ? 1 : 0; +} + +static const struct clk_ops da8xx_cfgchip_mux_clk_ops = { + .set_parent = da8xx_cfgchip_mux_clk_set_parent, + .get_parent = da8xx_cfgchip_mux_clk_get_parent, +}; + +static struct da8xx_cfgchip_mux_clk * __init +da8xx_cfgchip_mux_clk_register(struct device *dev, + const struct da8xx_cfgchip_mux_clk_info *info, + struct regmap *regmap) +{ + const char * const parent_names[] = { info->parent0, info->parent1 }; + struct da8xx_cfgchip_mux_clk *mux; + struct clk_init_data init; + int ret; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + + init.name = info->name; + init.ops = &da8xx_cfgchip_mux_clk_ops; + init.parent_names = parent_names; + init.num_parents = 2; + init.flags = 0; + + mux->hw.init = &init; + mux->regmap = regmap; + mux->reg = info->cfgchip; + mux->mask = info->bit; + + ret = devm_clk_hw_register(dev, &mux->hw); + if (ret < 0) + return ERR_PTR(ret); + + return mux; +} + +static const struct da8xx_cfgchip_mux_clk_info da850_async1_info __initconst = { + .name = "async1", + .parent0 = "pll0_sysclk3", + .parent1 = "div4.5", + .cfgchip = CFGCHIP(3), + .bit = CFGCHIP3_EMA_CLKSRC, +}; + +static int __init da8xx_cfgchip_register_async1(struct device *dev, + struct regmap *regmap) +{ + struct da8xx_cfgchip_mux_clk *mux; + + mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async1_info, regmap); + if (IS_ERR(mux)) + return PTR_ERR(mux); + + clk_hw_register_clkdev(&mux->hw, "async1", "da850-psc0"); + + return 0; +} + +static const struct da8xx_cfgchip_mux_clk_info da850_async3_info __initconst = { + .name = "async3", + .parent0 = "pll0_sysclk2", + .parent1 = "pll1_sysclk2", + .cfgchip = CFGCHIP(3), + .bit = CFGCHIP3_ASYNC3_CLKSRC, +}; + +static int __init da850_cfgchip_register_async3(struct device *dev, + struct regmap *regmap) +{ + struct da8xx_cfgchip_mux_clk *mux; + struct clk_hw *parent; + + mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async3_info, regmap); + if (IS_ERR(mux)) + return PTR_ERR(mux); + + clk_hw_register_clkdev(&mux->hw, "async3", "da850-psc1"); + + /* pll1_sysclk2 is not affected by CPU scaling, so use it for async3 */ + parent = clk_hw_get_parent_by_index(&mux->hw, 1); + if (parent) + clk_set_parent(mux->hw.clk, parent->clk); + else + dev_warn(dev, "Failed to find async3 parent clock\n"); + + return 0; +} + +static int __init +of_da8xx_cfgchip_init_mux_clock(struct device *dev, + const struct da8xx_cfgchip_mux_clk_info *info, + struct regmap *regmap) +{ + struct da8xx_cfgchip_mux_clk *mux; + + mux = da8xx_cfgchip_mux_clk_register(dev, info, regmap); + if (IS_ERR(mux)) + return PTR_ERR(mux); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &mux->hw); +} + +static int __init of_da850_async1_init(struct device *dev, struct regmap *regmap) +{ + return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async1_info, regmap); +} + +static int __init of_da850_async3_init(struct device *dev, struct regmap *regmap) +{ + return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async3_info, regmap); +} + +/* --- platform device --- */ + +static const struct of_device_id da8xx_cfgchip_of_match[] = { + { + .compatible = "ti,da830-tbclksync", + .data = of_da8xx_tbclksync_init, + }, + { + .compatible = "ti,da830-div4p5ena", + .data = of_da8xx_div4p5ena_init, + }, + { + .compatible = "ti,da850-async1-clksrc", + .data = of_da850_async1_init, + }, + { + .compatible = "ti,da850-async3-clksrc", + .data = of_da850_async3_init, + }, + { } +}; + +static const struct platform_device_id da8xx_cfgchip_id_table[] = { + { + .name = "da830-tbclksync", + .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_tbclk, + }, + { + .name = "da830-div4p5ena", + .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_div4p5, + }, + { + .name = "da850-async1-clksrc", + .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_async1, + }, + { + .name = "da850-async3-clksrc", + .driver_data = (kernel_ulong_t)da850_cfgchip_register_async3, + }, + { } +}; + +typedef int (*da8xx_cfgchip_init)(struct device *dev, struct regmap *regmap); + +static int da8xx_cfgchip_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct da8xx_cfgchip_clk_platform_data *pdata = dev->platform_data; + const struct of_device_id *of_id; + da8xx_cfgchip_init clk_init = NULL; + struct regmap *regmap = NULL; + + of_id = of_match_device(da8xx_cfgchip_of_match, dev); + if (of_id) { + struct device_node *parent; + + clk_init = of_id->data; + parent = of_get_parent(dev->of_node); + regmap = syscon_node_to_regmap(parent); + of_node_put(parent); + } else if (pdev->id_entry && pdata) { + clk_init = (void *)pdev->id_entry->driver_data; + regmap = pdata->cfgchip; + } + + if (!clk_init) { + dev_err(dev, "unable to find driver data\n"); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(regmap)) { + dev_err(dev, "no regmap for CFGCHIP syscon\n"); + return regmap ? PTR_ERR(regmap) : -ENOENT; + } + + return clk_init(dev, regmap); +} + +static struct platform_driver da8xx_cfgchip_driver = { + .probe = da8xx_cfgchip_probe, + .driver = { + .name = "da8xx-cfgchip-clk", + .of_match_table = da8xx_cfgchip_of_match, + }, + .id_table = da8xx_cfgchip_id_table, +}; + +static int __init da8xx_cfgchip_driver_init(void) +{ + return platform_driver_register(&da8xx_cfgchip_driver); +} + +/* has to be postcore_initcall because PSC devices depend on the async3 clock */ +postcore_initcall(da8xx_cfgchip_driver_init); diff --git a/include/linux/platform_data/clk-da8xx-cfgchip.h b/include/linux/platform_data/clk-da8xx-cfgchip.h new file mode 100644 index 000000000000..de0f77d38669 --- /dev/null +++ b/include/linux/platform_data/clk-da8xx-cfgchip.h @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * clk-da8xx-cfgchip - TI DaVinci DA8xx CFGCHIP clock driver + * + * Copyright (C) 2018 David Lechner + */ + +#ifndef __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__ +#define __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__ + +#include + +/** + * da8xx_cfgchip_clk_platform_data + * @cfgchip: CFGCHIP syscon regmap + */ +struct da8xx_cfgchip_clk_platform_data { + struct regmap *cfgchip; +}; + +#endif /* __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__ */ -- cgit v1.2.3 From d726f6b1997528354e1053accbb6223981e81802 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Tue, 13 Feb 2018 22:09:34 +0000 Subject: platform/x86: mlx-platform: Add deffered bus functionality mlx-platform activates i2c-mux-reg, which creates buses needed by mlxreg-hotplug. If the mlxreg-hotplug probe runs before the i2c-mux-reg probe completes, it may attempt to connect a device to an adapter number that has not been created yet, and fail. Make mlx-platform driver record the highest bus number in mlxreg-hotplug platform data and defer mlxreg-hotplug probe until all the buses are created. Signed-off-by: Vadim Pasternak [dvhart: rewrite commit message more concisely] Signed-off-by: Darren Hart (VMware) --- drivers/platform/mellanox/mlxreg-hotplug.c | 7 +++++++ drivers/platform/x86/mlx-platform.c | 10 ++++++++++ include/linux/platform_data/mlxreg.h | 2 ++ 3 files changed, 19 insertions(+) (limited to 'include/linux/platform_data') diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c index 313cf8ad77bf..fe4910bc0f96 100644 --- a/drivers/platform/mellanox/mlxreg-hotplug.c +++ b/drivers/platform/mellanox/mlxreg-hotplug.c @@ -550,6 +550,7 @@ static int mlxreg_hotplug_probe(struct platform_device *pdev) { struct mlxreg_core_hotplug_platform_data *pdata; struct mlxreg_hotplug_priv_data *priv; + struct i2c_adapter *deferred_adap; int err; pdata = dev_get_platdata(&pdev->dev); @@ -558,6 +559,12 @@ static int mlxreg_hotplug_probe(struct platform_device *pdev) return -EINVAL; } + /* Defer probing if the necessary adapter is not configured yet. */ + deferred_adap = i2c_get_adapter(pdata->deferred_nr); + if (!deferred_adap) + return -EPROBE_DEFER; + i2c_put_adapter(deferred_adap); + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c index 71b452a89a6e..67f3c6d36988 100644 --- a/drivers/platform/x86/mlx-platform.c +++ b/drivers/platform/x86/mlx-platform.c @@ -697,6 +697,8 @@ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) ARRAY_SIZE(mlxplat_default_channels[i]); } mlxplat_hotplug = &mlxplat_mlxcpld_default_data; + mlxplat_hotplug->deferred_nr = + mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; return 1; }; @@ -711,6 +713,8 @@ static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) ARRAY_SIZE(mlxplat_msn21xx_channels); } mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data; + mlxplat_hotplug->deferred_nr = + mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; return 1; }; @@ -725,6 +729,8 @@ static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) ARRAY_SIZE(mlxplat_msn21xx_channels); } mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data; + mlxplat_hotplug->deferred_nr = + mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; return 1; }; @@ -739,6 +745,8 @@ static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) ARRAY_SIZE(mlxplat_msn21xx_channels); } mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data; + mlxplat_hotplug->deferred_nr = + mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; return 1; }; @@ -753,6 +761,8 @@ static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi) ARRAY_SIZE(mlxplat_msn21xx_channels); } mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data; + mlxplat_hotplug->deferred_nr = + mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; return 1; }; diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h index fcdc707eab99..262910967476 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -129,6 +129,7 @@ struct mlxreg_core_platform_data { * @mask: top aggregation interrupt common mask; * @cell_low: location of low aggregation interrupt register; * @mask_low: low aggregation interrupt common mask; + * @deferred_nr: I2C adapter number must be exist prior probing execution; */ struct mlxreg_core_hotplug_platform_data { struct mlxreg_core_item *items; @@ -139,6 +140,7 @@ struct mlxreg_core_hotplug_platform_data { u32 mask; u32 cell_low; u32 mask_low; + int deferred_nr; }; #endif /* __LINUX_PLATFORM_DATA_MLXREG_H */ -- cgit v1.2.3 From ef0f62264b2a9e6fc73476ed22ade1ff1f3ad7f3 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Tue, 13 Feb 2018 22:09:36 +0000 Subject: platform/x86: mlx-platform: Add physical bus number auto detection mlx-platform does not provide a bus number to i2c-mlxcpld, assuming it is always one. On some x86 systems, other i2c drivers may probe before i2c-mlxcpld, causing bus one to be busy. Make mlx-platform determine which adapter number is free prior to activating i2c-mlxpld, adjusting the mux base numbers accordingly. Update the mlxreg-hotplug pdata similarly. This adds an explicit mlx-platform build dependency on I2C, update the Kconfig accordingly. Add the missing REGMAP dependency while we're at it. Signed-off-by: Vadim Pasternak [dvhart: Rewrite commit message more concisely] [dvhart: Add build dependencies] Signed-off-by: Darren Hart (VMware) --- drivers/platform/mellanox/mlxreg-hotplug.c | 12 ++++--- drivers/platform/x86/Kconfig | 1 + drivers/platform/x86/mlx-platform.c | 53 ++++++++++++++++++++++++++++-- include/linux/platform_data/mlxreg.h | 2 ++ 4 files changed, 62 insertions(+), 6 deletions(-) (limited to 'include/linux/platform_data') diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c index c1e1c4f254ce..ea9e7f4479ca 100644 --- a/drivers/platform/mellanox/mlxreg-hotplug.c +++ b/drivers/platform/mellanox/mlxreg-hotplug.c @@ -96,6 +96,8 @@ struct mlxreg_hotplug_priv_data { static int mlxreg_hotplug_device_create(struct mlxreg_hotplug_priv_data *priv, struct mlxreg_core_data *data) { + struct mlxreg_core_hotplug_platform_data *pdata; + /* * Return if adapter number is negative. It could be in case hotplug * event is not associated with hotplug device. @@ -103,10 +105,12 @@ static int mlxreg_hotplug_device_create(struct mlxreg_hotplug_priv_data *priv, if (data->hpdev.nr < 0) return 0; - data->hpdev.adapter = i2c_get_adapter(data->hpdev.nr); + pdata = dev_get_platdata(&priv->pdev->dev); + data->hpdev.adapter = i2c_get_adapter(data->hpdev.nr + + pdata->shift_nr); if (!data->hpdev.adapter) { dev_err(priv->dev, "Failed to get adapter for bus %d\n", - data->hpdev.nr); + data->hpdev.nr + pdata->shift_nr); return -EFAULT; } @@ -114,8 +118,8 @@ static int mlxreg_hotplug_device_create(struct mlxreg_hotplug_priv_data *priv, data->hpdev.brdinfo); if (!data->hpdev.client) { dev_err(priv->dev, "Failed to create client %s at bus %d at addr 0x%02x\n", - data->hpdev.brdinfo->type, data->hpdev.nr, - data->hpdev.brdinfo->addr); + data->hpdev.brdinfo->type, data->hpdev.nr + + pdata->shift_nr, data->hpdev.brdinfo->addr); i2c_put_adapter(data->hpdev.adapter); data->hpdev.adapter = NULL; diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index 1868aab0282a..b528e44ad8ae 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig @@ -1175,6 +1175,7 @@ config INTEL_TELEMETRY config MLX_PLATFORM tristate "Mellanox Technologies platform support" + depends on I2C && REGMAP ---help--- This option enables system support for the Mellanox Technologies platform. The Mellanox systems provide data center networking diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c index 67f3c6d36988..7a0bd24c1ae2 100644 --- a/drivers/platform/x86/mlx-platform.c +++ b/drivers/platform/x86/mlx-platform.c @@ -85,6 +85,12 @@ #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(5, 0) +/* Default I2C parent bus number */ +#define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 + +/* Maximum number of possible physical buses equipped on system */ +#define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 + /* Number of channels in group */ #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 @@ -843,10 +849,48 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table); +static int mlxplat_mlxcpld_verify_bus_topology(int *nr) +{ + struct i2c_adapter *search_adap; + int shift, i; + + /* Scan adapters from expected id to verify it is free. */ + *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; + for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i < + MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; i++) { + search_adap = i2c_get_adapter(i); + if (search_adap) { + i2c_put_adapter(search_adap); + continue; + } + + /* Return if expected parent adapter is free. */ + if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR) + return 0; + break; + } + + /* Return with error if free id for adapter is not found. */ + if (i == MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM) + return -ENODEV; + + /* Shift adapter ids, since expected parent adapter is not free. */ + *nr = i; + for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) { + shift = *nr - mlxplat_mux_data[i].parent; + mlxplat_mux_data[i].parent = *nr; + mlxplat_mux_data[i].base_nr += shift; + if (shift > 0) + mlxplat_hotplug->shift_nr = shift; + } + + return 0; +} + static int __init mlxplat_init(void) { struct mlxplat_priv *priv; - int i, err; + int i, nr, err; if (!dmi_check_system(mlxplat_dmi_table)) return -ENODEV; @@ -866,7 +910,12 @@ static int __init mlxplat_init(void) } platform_set_drvdata(mlxplat_dev, priv); - priv->pdev_i2c = platform_device_register_simple("i2c_mlxcpld", -1, + err = mlxplat_mlxcpld_verify_bus_topology(&nr); + if (nr < 0) + goto fail_alloc; + + nr = (nr == MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM) ? -1 : nr; + priv->pdev_i2c = platform_device_register_simple("i2c_mlxcpld", nr, NULL, 0); if (IS_ERR(priv->pdev_i2c)) { err = PTR_ERR(priv->pdev_i2c); diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h index 262910967476..2744cff1b297 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -130,6 +130,7 @@ struct mlxreg_core_platform_data { * @cell_low: location of low aggregation interrupt register; * @mask_low: low aggregation interrupt common mask; * @deferred_nr: I2C adapter number must be exist prior probing execution; + * @shift_nr: I2C adapter numbers must be incremented by this value; */ struct mlxreg_core_hotplug_platform_data { struct mlxreg_core_item *items; @@ -141,6 +142,7 @@ struct mlxreg_core_hotplug_platform_data { u32 cell_low; u32 mask_low; int deferred_nr; + int shift_nr; }; #endif /* __LINUX_PLATFORM_DATA_MLXREG_H */ -- cgit v1.2.3 From f59b2dc2de63652cad750efc2ad1012eb1bb342f Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Mar 2018 18:16:31 +0100 Subject: pinctrl: remove adi2/blackfin drivers The blackfin architecture is getting removed, so these are now obsolete. Acked-by: Aaron Wu Signed-off-by: Arnd Bergmann --- drivers/pinctrl/Kconfig | 19 - drivers/pinctrl/Makefile | 3 - drivers/pinctrl/pinctrl-adi2-bf54x.c | 588 --------------- drivers/pinctrl/pinctrl-adi2-bf60x.c | 517 ------------- drivers/pinctrl/pinctrl-adi2.c | 1114 ---------------------------- drivers/pinctrl/pinctrl-adi2.h | 75 -- include/linux/platform_data/pinctrl-adi2.h | 40 - 7 files changed, 2356 deletions(-) delete mode 100644 drivers/pinctrl/pinctrl-adi2-bf54x.c delete mode 100644 drivers/pinctrl/pinctrl-adi2-bf60x.c delete mode 100644 drivers/pinctrl/pinctrl-adi2.c delete mode 100644 drivers/pinctrl/pinctrl-adi2.h delete mode 100644 include/linux/platform_data/pinctrl-adi2.h (limited to 'include/linux/platform_data') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 0f254b35c378..008073570a38 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -30,17 +30,6 @@ config DEBUG_PINCTRL help Say Y here to add some extra checks and diagnostics to PINCTRL calls. -config PINCTRL_ADI2 - bool "ADI pin controller driver" - depends on (BF54x || BF60x) - depends on !GPIO_ADI - select PINMUX - select IRQ_DOMAIN - help - This is the pin controller and gpio driver for ADI BF54x, BF60x and - future processors. This option is selected automatically when specific - machine and arch are selected to build. - config PINCTRL_ARTPEC6 bool "Axis ARTPEC-6 pin controller driver" depends on MACH_ARTPEC6 @@ -77,14 +66,6 @@ config PINCTRL_AXP209 selected. Say yes to enable pinctrl and GPIO support for the AXP209 PMIC -config PINCTRL_BF54x - def_bool y if BF54x - select PINCTRL_ADI2 - -config PINCTRL_BF60x - def_bool y if BF60x - select PINCTRL_ADI2 - config PINCTRL_AT91 bool "AT91 pinctrl driver" depends on OF diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d3692633e9ed..92a40bdb6273 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -8,12 +8,9 @@ obj-$(CONFIG_PINMUX) += pinmux.o obj-$(CONFIG_PINCONF) += pinconf.o obj-$(CONFIG_OF) += devicetree.o obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o -obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl-artpec6.o obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o -obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o -obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o diff --git a/drivers/pinctrl/pinctrl-adi2-bf54x.c b/drivers/pinctrl/pinctrl-adi2-bf54x.c deleted file mode 100644 index 008a29e92e56..000000000000 --- a/drivers/pinctrl/pinctrl-adi2-bf54x.c +++ /dev/null @@ -1,588 +0,0 @@ -/* - * Pinctrl Driver for ADI GPIO2 controller - * - * Copyright 2007-2013 Analog Devices Inc. - * - * Licensed under the GPLv2 or later - */ - -#include -#include "pinctrl-adi2.h" - -static const struct pinctrl_pin_desc adi_pads[] = { - PINCTRL_PIN(0, "PA0"), - PINCTRL_PIN(1, "PA1"), - PINCTRL_PIN(2, "PA2"), - PINCTRL_PIN(3, "PG3"), - PINCTRL_PIN(4, "PA4"), - PINCTRL_PIN(5, "PA5"), - PINCTRL_PIN(6, "PA6"), - PINCTRL_PIN(7, "PA7"), - PINCTRL_PIN(8, "PA8"), - PINCTRL_PIN(9, "PA9"), - PINCTRL_PIN(10, "PA10"), - PINCTRL_PIN(11, "PA11"), - PINCTRL_PIN(12, "PA12"), - PINCTRL_PIN(13, "PA13"), - PINCTRL_PIN(14, "PA14"), - PINCTRL_PIN(15, "PA15"), - PINCTRL_PIN(16, "PB0"), - PINCTRL_PIN(17, "PB1"), - PINCTRL_PIN(18, "PB2"), - PINCTRL_PIN(19, "PB3"), - PINCTRL_PIN(20, "PB4"), - PINCTRL_PIN(21, "PB5"), - PINCTRL_PIN(22, "PB6"), - PINCTRL_PIN(23, "PB7"), - PINCTRL_PIN(24, "PB8"), - PINCTRL_PIN(25, "PB9"), - PINCTRL_PIN(26, "PB10"), - PINCTRL_PIN(27, "PB11"), - PINCTRL_PIN(28, "PB12"), - PINCTRL_PIN(29, "PB13"), - PINCTRL_PIN(30, "PB14"), - PINCTRL_PIN(32, "PC0"), - PINCTRL_PIN(33, "PC1"), - PINCTRL_PIN(34, "PC2"), - PINCTRL_PIN(35, "PC3"), - PINCTRL_PIN(36, "PC4"), - PINCTRL_PIN(37, "PC5"), - PINCTRL_PIN(38, "PC6"), - PINCTRL_PIN(39, "PC7"), - PINCTRL_PIN(40, "PC8"), - PINCTRL_PIN(41, "PC9"), - PINCTRL_PIN(42, "PC10"), - PINCTRL_PIN(43, "PC11"), - PINCTRL_PIN(44, "PC12"), - PINCTRL_PIN(45, "PC13"), - PINCTRL_PIN(48, "PD0"), - PINCTRL_PIN(49, "PD1"), - PINCTRL_PIN(50, "PD2"), - PINCTRL_PIN(51, "PD3"), - PINCTRL_PIN(52, "PD4"), - PINCTRL_PIN(53, "PD5"), - PINCTRL_PIN(54, "PD6"), - PINCTRL_PIN(55, "PD7"), - PINCTRL_PIN(56, "PD8"), - PINCTRL_PIN(57, "PD9"), - PINCTRL_PIN(58, "PD10"), - PINCTRL_PIN(59, "PD11"), - PINCTRL_PIN(60, "PD12"), - PINCTRL_PIN(61, "PD13"), - PINCTRL_PIN(62, "PD14"), - PINCTRL_PIN(63, "PD15"), - PINCTRL_PIN(64, "PE0"), - PINCTRL_PIN(65, "PE1"), - PINCTRL_PIN(66, "PE2"), - PINCTRL_PIN(67, "PE3"), - PINCTRL_PIN(68, "PE4"), - PINCTRL_PIN(69, "PE5"), - PINCTRL_PIN(70, "PE6"), - PINCTRL_PIN(71, "PE7"), - PINCTRL_PIN(72, "PE8"), - PINCTRL_PIN(73, "PE9"), - PINCTRL_PIN(74, "PE10"), - PINCTRL_PIN(75, "PE11"), - PINCTRL_PIN(76, "PE12"), - PINCTRL_PIN(77, "PE13"), - PINCTRL_PIN(78, "PE14"), - PINCTRL_PIN(79, "PE15"), - PINCTRL_PIN(80, "PF0"), - PINCTRL_PIN(81, "PF1"), - PINCTRL_PIN(82, "PF2"), - PINCTRL_PIN(83, "PF3"), - PINCTRL_PIN(84, "PF4"), - PINCTRL_PIN(85, "PF5"), - PINCTRL_PIN(86, "PF6"), - PINCTRL_PIN(87, "PF7"), - PINCTRL_PIN(88, "PF8"), - PINCTRL_PIN(89, "PF9"), - PINCTRL_PIN(90, "PF10"), - PINCTRL_PIN(91, "PF11"), - PINCTRL_PIN(92, "PF12"), - PINCTRL_PIN(93, "PF13"), - PINCTRL_PIN(94, "PF14"), - PINCTRL_PIN(95, "PF15"), - PINCTRL_PIN(96, "PG0"), - PINCTRL_PIN(97, "PG1"), - PINCTRL_PIN(98, "PG2"), - PINCTRL_PIN(99, "PG3"), - PINCTRL_PIN(100, "PG4"), - PINCTRL_PIN(101, "PG5"), - PINCTRL_PIN(102, "PG6"), - PINCTRL_PIN(103, "PG7"), - PINCTRL_PIN(104, "PG8"), - PINCTRL_PIN(105, "PG9"), - PINCTRL_PIN(106, "PG10"), - PINCTRL_PIN(107, "PG11"), - PINCTRL_PIN(108, "PG12"), - PINCTRL_PIN(109, "PG13"), - PINCTRL_PIN(110, "PG14"), - PINCTRL_PIN(111, "PG15"), - PINCTRL_PIN(112, "PH0"), - PINCTRL_PIN(113, "PH1"), - PINCTRL_PIN(114, "PH2"), - PINCTRL_PIN(115, "PH3"), - PINCTRL_PIN(116, "PH4"), - PINCTRL_PIN(117, "PH5"), - PINCTRL_PIN(118, "PH6"), - PINCTRL_PIN(119, "PH7"), - PINCTRL_PIN(120, "PH8"), - PINCTRL_PIN(121, "PH9"), - PINCTRL_PIN(122, "PH10"), - PINCTRL_PIN(123, "PH11"), - PINCTRL_PIN(124, "PH12"), - PINCTRL_PIN(125, "PH13"), - PINCTRL_PIN(128, "PI0"), - PINCTRL_PIN(129, "PI1"), - PINCTRL_PIN(130, "PI2"), - PINCTRL_PIN(131, "PI3"), - PINCTRL_PIN(132, "PI4"), - PINCTRL_PIN(133, "PI5"), - PINCTRL_PIN(134, "PI6"), - PINCTRL_PIN(135, "PI7"), - PINCTRL_PIN(136, "PI8"), - PINCTRL_PIN(137, "PI9"), - PINCTRL_PIN(138, "PI10"), - PINCTRL_PIN(139, "PI11"), - PINCTRL_PIN(140, "PI12"), - PINCTRL_PIN(141, "PI13"), - PINCTRL_PIN(142, "PI14"), - PINCTRL_PIN(143, "PI15"), - PINCTRL_PIN(144, "PJ0"), - PINCTRL_PIN(145, "PJ1"), - PINCTRL_PIN(146, "PJ2"), - PINCTRL_PIN(147, "PJ3"), - PINCTRL_PIN(148, "PJ4"), - PINCTRL_PIN(149, "PJ5"), - PINCTRL_PIN(150, "PJ6"), - PINCTRL_PIN(151, "PJ7"), - PINCTRL_PIN(152, "PJ8"), - PINCTRL_PIN(153, "PJ9"), - PINCTRL_PIN(154, "PJ10"), - PINCTRL_PIN(155, "PJ11"), - PINCTRL_PIN(156, "PJ12"), - PINCTRL_PIN(157, "PJ13"), -}; - -static const unsigned uart0_pins[] = { - GPIO_PE7, GPIO_PE8, -}; - -static const unsigned uart1_pins[] = { - GPIO_PH0, GPIO_PH1, -}; - -static const unsigned uart1_ctsrts_pins[] = { - GPIO_PE9, GPIO_PE10, -}; - -static const unsigned uart2_pins[] = { - GPIO_PB4, GPIO_PB5, -}; - -static const unsigned uart3_pins[] = { - GPIO_PB6, GPIO_PB7, -}; - -static const unsigned uart3_ctsrts_pins[] = { - GPIO_PB2, GPIO_PB3, -}; - -static const unsigned rsi0_pins[] = { - GPIO_PC8, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12, GPIO_PC13, -}; - -static const unsigned spi0_pins[] = { - GPIO_PE0, GPIO_PE1, GPIO_PE2, -}; - -static const unsigned spi1_pins[] = { - GPIO_PG8, GPIO_PG9, GPIO_PG10, -}; - -static const unsigned twi0_pins[] = { - GPIO_PE14, GPIO_PE15, -}; - -static const unsigned twi1_pins[] = { - GPIO_PB0, GPIO_PB1, -}; - -static const unsigned rotary_pins[] = { - GPIO_PH4, GPIO_PH3, GPIO_PH5, -}; - -static const unsigned can0_pins[] = { - GPIO_PG13, GPIO_PG12, -}; - -static const unsigned can1_pins[] = { - GPIO_PG14, GPIO_PG15, -}; - -static const unsigned smc0_pins[] = { - GPIO_PH8, GPIO_PH9, GPIO_PH10, GPIO_PH11, GPIO_PH12, GPIO_PH13, - GPIO_PI0, GPIO_PI1, GPIO_PI2, GPIO_PI3, GPIO_PI4, GPIO_PI5, GPIO_PI6, - GPIO_PI7, GPIO_PI8, GPIO_PI9, GPIO_PI10, GPIO_PI11, - GPIO_PI12, GPIO_PI13, GPIO_PI14, GPIO_PI15, -}; - -static const unsigned sport0_pins[] = { - GPIO_PC0, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC6, GPIO_PC7, -}; - -static const unsigned sport1_pins[] = { - GPIO_PD0, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD6, GPIO_PD7, -}; - -static const unsigned sport2_pins[] = { - GPIO_PA0, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA6, GPIO_PA7, -}; - -static const unsigned sport3_pins[] = { - GPIO_PA8, GPIO_PA10, GPIO_PA11, GPIO_PA12, GPIO_PA14, GPIO_PA15, -}; - -static const unsigned ppi0_8b_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF13, GPIO_PG0, GPIO_PG1, GPIO_PG2, -}; - -static const unsigned ppi0_16b_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, - GPIO_PF13, GPIO_PF14, GPIO_PF15, - GPIO_PG0, GPIO_PG1, GPIO_PG2, -}; - -static const unsigned ppi0_24b_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, - GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PD0, GPIO_PD1, GPIO_PD2, - GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PG3, GPIO_PG4, - GPIO_PG0, GPIO_PG1, GPIO_PG2, -}; - -static const unsigned ppi1_8b_pins[] = { - GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6, - GPIO_PD7, GPIO_PE11, GPIO_PE12, GPIO_PE13, -}; - -static const unsigned ppi1_16b_pins[] = { - GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6, - GPIO_PD7, GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12, - GPIO_PD13, GPIO_PD14, GPIO_PD15, - GPIO_PE11, GPIO_PE12, GPIO_PE13, -}; - -static const unsigned ppi2_8b_pins[] = { - GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12, - GPIO_PD13, GPIO_PD14, GPIO_PD15, - GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3, -}; - -static const unsigned atapi_pins[] = { - GPIO_PH2, GPIO_PJ3, GPIO_PJ4, GPIO_PJ5, GPIO_PJ6, - GPIO_PJ7, GPIO_PJ8, GPIO_PJ9, GPIO_PJ10, -}; - -static const unsigned atapi_alter_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, - GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PG2, GPIO_PG3, GPIO_PG4, -}; - -static const unsigned nfc0_pins[] = { - GPIO_PJ1, GPIO_PJ2, -}; - -static const unsigned keys_4x4_pins[] = { - GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, - GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15, -}; - -static const unsigned keys_8x8_pins[] = { - GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, - GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15, - GPIO_PE0, GPIO_PE1, GPIO_PE2, GPIO_PE3, - GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7, -}; - -static const unsigned short uart0_mux[] = { - P_UART0_TX, P_UART0_RX, - 0 -}; - -static const unsigned short uart1_mux[] = { - P_UART1_TX, P_UART1_RX, - 0 -}; - -static const unsigned short uart1_ctsrts_mux[] = { - P_UART1_RTS, P_UART1_CTS, - 0 -}; - -static const unsigned short uart2_mux[] = { - P_UART2_TX, P_UART2_RX, - 0 -}; - -static const unsigned short uart3_mux[] = { - P_UART3_TX, P_UART3_RX, - 0 -}; - -static const unsigned short uart3_ctsrts_mux[] = { - P_UART3_RTS, P_UART3_CTS, - 0 -}; - -static const unsigned short rsi0_mux[] = { - P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, - 0 -}; - -static const unsigned short spi0_mux[] = { - P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0 -}; - -static const unsigned short spi1_mux[] = { - P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0 -}; - -static const unsigned short twi0_mux[] = { - P_TWI0_SCL, P_TWI0_SDA, 0 -}; - -static const unsigned short twi1_mux[] = { - P_TWI1_SCL, P_TWI1_SDA, 0 -}; - -static const unsigned short rotary_mux[] = { - P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0 -}; - -static const unsigned short sport0_mux[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static const unsigned short sport1_mux[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static const unsigned short sport2_mux[] = { - P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, - P_SPORT2_DRPRI, P_SPORT2_RSCLK, 0 -}; - -static const unsigned short sport3_mux[] = { - P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, - P_SPORT3_DRPRI, P_SPORT3_RSCLK, 0 -}; - -static const unsigned short can0_mux[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static const unsigned short can1_mux[] = { - P_CAN1_RX, P_CAN1_TX, 0 -}; - -static const unsigned short smc0_mux[] = { - P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, - P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21, - P_A22, P_A23, P_A24, P_A25, P_NOR_CLK, 0, -}; - -static const unsigned short ppi0_8b_mux[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const unsigned short ppi0_16b_mux[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, - P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const unsigned short ppi0_24b_mux[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, - P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, - P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19, - P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const unsigned short ppi1_8b_mux[] = { - P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, - P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, - P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, - 0, -}; - -static const unsigned short ppi1_16b_mux[] = { - P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, - P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, - P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11, - P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15, - P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, - 0, -}; - -static const unsigned short ppi2_8b_mux[] = { - P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3, - P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7, - P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2, - 0, -}; - -static const unsigned short atapi_mux[] = { - P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0, P_ATAPI_CS1, - P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ, P_ATAPI_IORDY, -}; - -static const unsigned short atapi_alter_mux[] = { - P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A, P_ATAPI_D3A, P_ATAPI_D4A, - P_ATAPI_D5A, P_ATAPI_D6A, P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, - P_ATAPI_D10A, P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A, - P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, - 0 -}; - -static const unsigned short nfc0_mux[] = { - P_NAND_CE, P_NAND_RB, - 0 -}; - -static const unsigned short keys_4x4_mux[] = { - P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0, - P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0, - 0 -}; - -static const unsigned short keys_8x8_mux[] = { - P_KEY_ROW7, P_KEY_ROW6, P_KEY_ROW5, P_KEY_ROW4, - P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0, - P_KEY_COL7, P_KEY_COL6, P_KEY_COL5, P_KEY_COL4, - P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0, - 0 -}; - -static const struct adi_pin_group adi_pin_groups[] = { - ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux), - ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux), - ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux), - ADI_PIN_GROUP("uart2grp", uart2_pins, uart2_mux), - ADI_PIN_GROUP("uart3grp", uart3_pins, uart3_mux), - ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins, uart3_ctsrts_mux), - ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux), - ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux), - ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux), - ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux), - ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux), - ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux), - ADI_PIN_GROUP("can0grp", can0_pins, can0_mux), - ADI_PIN_GROUP("can1grp", can1_pins, can1_mux), - ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux), - ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux), - ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux), - ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux), - ADI_PIN_GROUP("sport3grp", sport3_pins, sport3_mux), - ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux), - ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux), - ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux), - ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux), - ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux), - ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux), - ADI_PIN_GROUP("atapigrp", atapi_pins, atapi_mux), - ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins, atapi_alter_mux), - ADI_PIN_GROUP("nfc0grp", nfc0_pins, nfc0_mux), - ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins, keys_4x4_mux), - ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins, keys_8x8_mux), -}; - -static const char * const uart0grp[] = { "uart0grp" }; -static const char * const uart1grp[] = { "uart1grp" }; -static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" }; -static const char * const uart2grp[] = { "uart2grp" }; -static const char * const uart3grp[] = { "uart3grp" }; -static const char * const uart3ctsrtsgrp[] = { "uart3ctsrtsgrp" }; -static const char * const rsi0grp[] = { "rsi0grp" }; -static const char * const spi0grp[] = { "spi0grp" }; -static const char * const spi1grp[] = { "spi1grp" }; -static const char * const twi0grp[] = { "twi0grp" }; -static const char * const twi1grp[] = { "twi1grp" }; -static const char * const rotarygrp[] = { "rotarygrp" }; -static const char * const can0grp[] = { "can0grp" }; -static const char * const can1grp[] = { "can1grp" }; -static const char * const smc0grp[] = { "smc0grp" }; -static const char * const sport0grp[] = { "sport0grp" }; -static const char * const sport1grp[] = { "sport1grp" }; -static const char * const sport2grp[] = { "sport2grp" }; -static const char * const sport3grp[] = { "sport3grp" }; -static const char * const ppi0grp[] = { "ppi0_8bgrp", - "ppi0_16bgrp", - "ppi0_24bgrp" }; -static const char * const ppi1grp[] = { "ppi1_8bgrp", - "ppi1_16bgrp" }; -static const char * const ppi2grp[] = { "ppi2_8bgrp" }; -static const char * const atapigrp[] = { "atapigrp" }; -static const char * const atapialtergrp[] = { "atapialtergrp" }; -static const char * const nfc0grp[] = { "nfc0grp" }; -static const char * const keysgrp[] = { "keys_4x4grp", - "keys_8x8grp" }; - -static const struct adi_pmx_func adi_pmx_functions[] = { - ADI_PMX_FUNCTION("uart0", uart0grp), - ADI_PMX_FUNCTION("uart1", uart1grp), - ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp), - ADI_PMX_FUNCTION("uart2", uart2grp), - ADI_PMX_FUNCTION("uart3", uart3grp), - ADI_PMX_FUNCTION("uart3_ctsrts", uart3ctsrtsgrp), - ADI_PMX_FUNCTION("rsi0", rsi0grp), - ADI_PMX_FUNCTION("spi0", spi0grp), - ADI_PMX_FUNCTION("spi1", spi1grp), - ADI_PMX_FUNCTION("twi0", twi0grp), - ADI_PMX_FUNCTION("twi1", twi1grp), - ADI_PMX_FUNCTION("rotary", rotarygrp), - ADI_PMX_FUNCTION("can0", can0grp), - ADI_PMX_FUNCTION("can1", can1grp), - ADI_PMX_FUNCTION("smc0", smc0grp), - ADI_PMX_FUNCTION("sport0", sport0grp), - ADI_PMX_FUNCTION("sport1", sport1grp), - ADI_PMX_FUNCTION("sport2", sport2grp), - ADI_PMX_FUNCTION("sport3", sport3grp), - ADI_PMX_FUNCTION("ppi0", ppi0grp), - ADI_PMX_FUNCTION("ppi1", ppi1grp), - ADI_PMX_FUNCTION("ppi2", ppi2grp), - ADI_PMX_FUNCTION("atapi", atapigrp), - ADI_PMX_FUNCTION("atapi_alter", atapialtergrp), - ADI_PMX_FUNCTION("nfc0", nfc0grp), - ADI_PMX_FUNCTION("keys", keysgrp), -}; - -static const struct adi_pinctrl_soc_data adi_bf54x_soc = { - .functions = adi_pmx_functions, - .nfunctions = ARRAY_SIZE(adi_pmx_functions), - .groups = adi_pin_groups, - .ngroups = ARRAY_SIZE(adi_pin_groups), - .pins = adi_pads, - .npins = ARRAY_SIZE(adi_pads), -}; - -void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc) -{ - *soc = &adi_bf54x_soc; -} diff --git a/drivers/pinctrl/pinctrl-adi2-bf60x.c b/drivers/pinctrl/pinctrl-adi2-bf60x.c deleted file mode 100644 index fcfa00821f12..000000000000 --- a/drivers/pinctrl/pinctrl-adi2-bf60x.c +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Pinctrl Driver for ADI GPIO2 controller - * - * Copyright 2007-2013 Analog Devices Inc. - * - * Licensed under the GPLv2 or later - */ - -#include -#include "pinctrl-adi2.h" - -static const struct pinctrl_pin_desc adi_pads[] = { - PINCTRL_PIN(0, "PA0"), - PINCTRL_PIN(1, "PA1"), - PINCTRL_PIN(2, "PA2"), - PINCTRL_PIN(3, "PG3"), - PINCTRL_PIN(4, "PA4"), - PINCTRL_PIN(5, "PA5"), - PINCTRL_PIN(6, "PA6"), - PINCTRL_PIN(7, "PA7"), - PINCTRL_PIN(8, "PA8"), - PINCTRL_PIN(9, "PA9"), - PINCTRL_PIN(10, "PA10"), - PINCTRL_PIN(11, "PA11"), - PINCTRL_PIN(12, "PA12"), - PINCTRL_PIN(13, "PA13"), - PINCTRL_PIN(14, "PA14"), - PINCTRL_PIN(15, "PA15"), - PINCTRL_PIN(16, "PB0"), - PINCTRL_PIN(17, "PB1"), - PINCTRL_PIN(18, "PB2"), - PINCTRL_PIN(19, "PB3"), - PINCTRL_PIN(20, "PB4"), - PINCTRL_PIN(21, "PB5"), - PINCTRL_PIN(22, "PB6"), - PINCTRL_PIN(23, "PB7"), - PINCTRL_PIN(24, "PB8"), - PINCTRL_PIN(25, "PB9"), - PINCTRL_PIN(26, "PB10"), - PINCTRL_PIN(27, "PB11"), - PINCTRL_PIN(28, "PB12"), - PINCTRL_PIN(29, "PB13"), - PINCTRL_PIN(30, "PB14"), - PINCTRL_PIN(31, "PB15"), - PINCTRL_PIN(32, "PC0"), - PINCTRL_PIN(33, "PC1"), - PINCTRL_PIN(34, "PC2"), - PINCTRL_PIN(35, "PC3"), - PINCTRL_PIN(36, "PC4"), - PINCTRL_PIN(37, "PC5"), - PINCTRL_PIN(38, "PC6"), - PINCTRL_PIN(39, "PC7"), - PINCTRL_PIN(40, "PC8"), - PINCTRL_PIN(41, "PC9"), - PINCTRL_PIN(42, "PC10"), - PINCTRL_PIN(43, "PC11"), - PINCTRL_PIN(44, "PC12"), - PINCTRL_PIN(45, "PC13"), - PINCTRL_PIN(46, "PC14"), - PINCTRL_PIN(47, "PC15"), - PINCTRL_PIN(48, "PD0"), - PINCTRL_PIN(49, "PD1"), - PINCTRL_PIN(50, "PD2"), - PINCTRL_PIN(51, "PD3"), - PINCTRL_PIN(52, "PD4"), - PINCTRL_PIN(53, "PD5"), - PINCTRL_PIN(54, "PD6"), - PINCTRL_PIN(55, "PD7"), - PINCTRL_PIN(56, "PD8"), - PINCTRL_PIN(57, "PD9"), - PINCTRL_PIN(58, "PD10"), - PINCTRL_PIN(59, "PD11"), - PINCTRL_PIN(60, "PD12"), - PINCTRL_PIN(61, "PD13"), - PINCTRL_PIN(62, "PD14"), - PINCTRL_PIN(63, "PD15"), - PINCTRL_PIN(64, "PE0"), - PINCTRL_PIN(65, "PE1"), - PINCTRL_PIN(66, "PE2"), - PINCTRL_PIN(67, "PE3"), - PINCTRL_PIN(68, "PE4"), - PINCTRL_PIN(69, "PE5"), - PINCTRL_PIN(70, "PE6"), - PINCTRL_PIN(71, "PE7"), - PINCTRL_PIN(72, "PE8"), - PINCTRL_PIN(73, "PE9"), - PINCTRL_PIN(74, "PE10"), - PINCTRL_PIN(75, "PE11"), - PINCTRL_PIN(76, "PE12"), - PINCTRL_PIN(77, "PE13"), - PINCTRL_PIN(78, "PE14"), - PINCTRL_PIN(79, "PE15"), - PINCTRL_PIN(80, "PF0"), - PINCTRL_PIN(81, "PF1"), - PINCTRL_PIN(82, "PF2"), - PINCTRL_PIN(83, "PF3"), - PINCTRL_PIN(84, "PF4"), - PINCTRL_PIN(85, "PF5"), - PINCTRL_PIN(86, "PF6"), - PINCTRL_PIN(87, "PF7"), - PINCTRL_PIN(88, "PF8"), - PINCTRL_PIN(89, "PF9"), - PINCTRL_PIN(90, "PF10"), - PINCTRL_PIN(91, "PF11"), - PINCTRL_PIN(92, "PF12"), - PINCTRL_PIN(93, "PF13"), - PINCTRL_PIN(94, "PF14"), - PINCTRL_PIN(95, "PF15"), - PINCTRL_PIN(96, "PG0"), - PINCTRL_PIN(97, "PG1"), - PINCTRL_PIN(98, "PG2"), - PINCTRL_PIN(99, "PG3"), - PINCTRL_PIN(100, "PG4"), - PINCTRL_PIN(101, "PG5"), - PINCTRL_PIN(102, "PG6"), - PINCTRL_PIN(103, "PG7"), - PINCTRL_PIN(104, "PG8"), - PINCTRL_PIN(105, "PG9"), - PINCTRL_PIN(106, "PG10"), - PINCTRL_PIN(107, "PG11"), - PINCTRL_PIN(108, "PG12"), - PINCTRL_PIN(109, "PG13"), - PINCTRL_PIN(110, "PG14"), - PINCTRL_PIN(111, "PG15"), -}; - -static const unsigned uart0_pins[] = { - GPIO_PD7, GPIO_PD8, -}; - -static const unsigned uart0_ctsrts_pins[] = { - GPIO_PD9, GPIO_PD10, -}; - -static const unsigned uart1_pins[] = { - GPIO_PG15, GPIO_PG14, -}; - -static const unsigned uart1_ctsrts_pins[] = { - GPIO_PG10, GPIO_PG13, -}; - -static const unsigned rsi0_pins[] = { - GPIO_PG3, GPIO_PG2, GPIO_PG0, GPIO_PE15, GPIO_PG5, GPIO_PG6, -}; - -static const unsigned eth0_pins[] = { - GPIO_PC6, GPIO_PC7, GPIO_PC2, GPIO_PC0, GPIO_PC3, GPIO_PC1, - GPIO_PB13, GPIO_PD6, GPIO_PC5, GPIO_PC4, GPIO_PB14, GPIO_PB15, -}; - -static const unsigned eth1_pins[] = { - GPIO_PE10, GPIO_PE11, GPIO_PG3, GPIO_PG0, GPIO_PG2, GPIO_PE15, - GPIO_PG5, GPIO_PE12, GPIO_PE13, GPIO_PE14, GPIO_PG6, GPIO_PC9, -}; - -static const unsigned spi0_pins[] = { - GPIO_PD4, GPIO_PD2, GPIO_PD3, -}; - -static const unsigned spi1_pins[] = { - GPIO_PD5, GPIO_PD14, GPIO_PD13, -}; - -static const unsigned twi0_pins[] = { -}; - -static const unsigned twi1_pins[] = { -}; - -static const unsigned rotary_pins[] = { - GPIO_PG7, GPIO_PG11, GPIO_PG12, -}; - -static const unsigned can0_pins[] = { - GPIO_PG1, GPIO_PG4, -}; - -static const unsigned smc0_pins[] = { - GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6, - GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PB2, GPIO_PA10, GPIO_PA11, - GPIO_PB3, GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB6, - GPIO_PB7, GPIO_PB8, GPIO_PB10, GPIO_PB11, GPIO_PB0, -}; - -static const unsigned sport0_pins[] = { - GPIO_PB5, GPIO_PB4, GPIO_PB9, GPIO_PB8, GPIO_PB7, GPIO_PB11, -}; - -static const unsigned sport1_pins[] = { - GPIO_PE2, GPIO_PE5, GPIO_PD15, GPIO_PE4, GPIO_PE3, GPIO_PE1, -}; - -static const unsigned sport2_pins[] = { - GPIO_PG4, GPIO_PG1, GPIO_PG9, GPIO_PG10, GPIO_PG7, GPIO_PB12, -}; - -static const unsigned ppi0_8b_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF13, GPIO_PF14, GPIO_PF15, - GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9, -}; - -static const unsigned ppi0_16b_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, - GPIO_PF13, GPIO_PF14, GPIO_PF15, - GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9, -}; - -static const unsigned ppi0_24b_pins[] = { - GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6, - GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12, - GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PE0, GPIO_PE1, GPIO_PE2, - GPIO_PE3, GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7, GPIO_PE8, - GPIO_PE9, GPIO_PD12, GPIO_PD15, -}; - -static const unsigned ppi1_8b_pins[] = { - GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6, - GPIO_PC7, GPIO_PC8, GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6, -}; - -static const unsigned ppi1_16b_pins[] = { - GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6, - GPIO_PC7, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12, - GPIO_PC13, GPIO_PC14, GPIO_PC15, - GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6, -}; - -static const unsigned ppi2_8b_pins[] = { - GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6, - GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3, -}; - -static const unsigned ppi2_16b_pins[] = { - GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6, - GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11, GPIO_PA12, - GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB0, GPIO_PB1, GPIO_PB2, -}; - -static const unsigned lp0_pins[] = { - GPIO_PB0, GPIO_PB1, GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, - GPIO_PA4, GPIO_PA5, GPIO_PA6, GPIO_PA7, -}; - -static const unsigned lp1_pins[] = { - GPIO_PB3, GPIO_PB2, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11, - GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15, -}; - -static const unsigned lp2_pins[] = { - GPIO_PE6, GPIO_PE7, GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, - GPIO_PF4, GPIO_PF5, GPIO_PF6, GPIO_PF7, -}; - -static const unsigned lp3_pins[] = { - GPIO_PE9, GPIO_PE8, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, - GPIO_PF12, GPIO_PF13, GPIO_PF14, GPIO_PF15, -}; - -static const unsigned short uart0_mux[] = { - P_UART0_TX, P_UART0_RX, - 0 -}; - -static const unsigned short uart0_ctsrts_mux[] = { - P_UART0_RTS, P_UART0_CTS, - 0 -}; - -static const unsigned short uart1_mux[] = { - P_UART1_TX, P_UART1_RX, - 0 -}; - -static const unsigned short uart1_ctsrts_mux[] = { - P_UART1_RTS, P_UART1_CTS, - 0 -}; - -static const unsigned short rsi0_mux[] = { - P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, - P_RSI_CMD, P_RSI_CLK, 0 -}; - -static const unsigned short eth0_mux[] = P_RMII0; -static const unsigned short eth1_mux[] = P_RMII1; - -static const unsigned short spi0_mux[] = { - P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0 -}; - -static const unsigned short spi1_mux[] = { - P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0 -}; - -static const unsigned short twi0_mux[] = { - P_TWI0_SCL, P_TWI0_SDA, 0 -}; - -static const unsigned short twi1_mux[] = { - P_TWI1_SCL, P_TWI1_SDA, 0 -}; - -static const unsigned short rotary_mux[] = { - P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0 -}; - -static const unsigned short sport0_mux[] = { - P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK, - P_SPORT0_BFS, P_SPORT0_BD0, 0, -}; - -static const unsigned short sport1_mux[] = { - P_SPORT1_ACLK, P_SPORT1_AFS, P_SPORT1_AD0, P_SPORT1_BCLK, - P_SPORT1_BFS, P_SPORT1_BD0, 0, -}; - -static const unsigned short sport2_mux[] = { - P_SPORT2_ACLK, P_SPORT2_AFS, P_SPORT2_AD0, P_SPORT2_BCLK, - P_SPORT2_BFS, P_SPORT2_BD0, 0, -}; - -static const unsigned short can0_mux[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static const unsigned short smc0_mux[] = { - P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, - P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21, - P_A22, P_A23, P_A24, P_A25, P_NORCK, 0, -}; - -static const unsigned short ppi0_8b_mux[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const unsigned short ppi0_16b_mux[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, - P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const unsigned short ppi0_24b_mux[] = { - P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, - P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, - P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, - P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, - P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19, - P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23, - P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, - 0, -}; - -static const unsigned short ppi1_8b_mux[] = { - P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, - P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, - P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, - 0, -}; - -static const unsigned short ppi1_16b_mux[] = { - P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, - P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, - P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11, - P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15, - P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, - 0, -}; - -static const unsigned short ppi2_8b_mux[] = { - P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3, - P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7, - P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2, - 0, -}; - -static const unsigned short ppi2_16b_mux[] = { - P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3, - P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7, - P_PPI2_D8, P_PPI2_D9, P_PPI2_D10, P_PPI2_D11, - P_PPI2_D12, P_PPI2_D13, P_PPI2_D14, P_PPI2_D15, - P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2, - 0, -}; - -static const unsigned short lp0_mux[] = { - P_LP0_CLK, P_LP0_ACK, P_LP0_D0, P_LP0_D1, P_LP0_D2, - P_LP0_D3, P_LP0_D4, P_LP0_D5, P_LP0_D6, P_LP0_D7, - 0 -}; - -static const unsigned short lp1_mux[] = { - P_LP1_CLK, P_LP1_ACK, P_LP1_D0, P_LP1_D1, P_LP1_D2, - P_LP1_D3, P_LP1_D4, P_LP1_D5, P_LP1_D6, P_LP1_D7, - 0 -}; - -static const unsigned short lp2_mux[] = { - P_LP2_CLK, P_LP2_ACK, P_LP2_D0, P_LP2_D1, P_LP2_D2, - P_LP2_D3, P_LP2_D4, P_LP2_D5, P_LP2_D6, P_LP2_D7, - 0 -}; - -static const unsigned short lp3_mux[] = { - P_LP3_CLK, P_LP3_ACK, P_LP3_D0, P_LP3_D1, P_LP3_D2, - P_LP3_D3, P_LP3_D4, P_LP3_D5, P_LP3_D6, P_LP3_D7, - 0 -}; - -static const struct adi_pin_group adi_pin_groups[] = { - ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux), - ADI_PIN_GROUP("uart0ctsrtsgrp", uart0_ctsrts_pins, uart0_ctsrts_mux), - ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux), - ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux), - ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux), - ADI_PIN_GROUP("eth0grp", eth0_pins, eth0_mux), - ADI_PIN_GROUP("eth1grp", eth1_pins, eth1_mux), - ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux), - ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux), - ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux), - ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux), - ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux), - ADI_PIN_GROUP("can0grp", can0_pins, can0_mux), - ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux), - ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux), - ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux), - ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux), - ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux), - ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux), - ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux), - ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux), - ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux), - ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux), - ADI_PIN_GROUP("ppi2_16bgrp", ppi2_16b_pins, ppi2_16b_mux), - ADI_PIN_GROUP("lp0grp", lp0_pins, lp0_mux), - ADI_PIN_GROUP("lp1grp", lp1_pins, lp1_mux), - ADI_PIN_GROUP("lp2grp", lp2_pins, lp2_mux), - ADI_PIN_GROUP("lp3grp", lp3_pins, lp3_mux), -}; - -static const char * const uart0grp[] = { "uart0grp" }; -static const char * const uart0ctsrtsgrp[] = { "uart0ctsrtsgrp" }; -static const char * const uart1grp[] = { "uart1grp" }; -static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" }; -static const char * const rsi0grp[] = { "rsi0grp" }; -static const char * const eth0grp[] = { "eth0grp" }; -static const char * const eth1grp[] = { "eth1grp" }; -static const char * const spi0grp[] = { "spi0grp" }; -static const char * const spi1grp[] = { "spi1grp" }; -static const char * const twi0grp[] = { "twi0grp" }; -static const char * const twi1grp[] = { "twi1grp" }; -static const char * const rotarygrp[] = { "rotarygrp" }; -static const char * const can0grp[] = { "can0grp" }; -static const char * const smc0grp[] = { "smc0grp" }; -static const char * const sport0grp[] = { "sport0grp" }; -static const char * const sport1grp[] = { "sport1grp" }; -static const char * const sport2grp[] = { "sport2grp" }; -static const char * const ppi0grp[] = { "ppi0_8bgrp", - "ppi0_16bgrp", - "ppi0_24bgrp" }; -static const char * const ppi1grp[] = { "ppi1_8bgrp", - "ppi1_16bgrp" }; -static const char * const ppi2grp[] = { "ppi2_8bgrp", - "ppi2_16bgrp" }; -static const char * const lp0grp[] = { "lp0grp" }; -static const char * const lp1grp[] = { "lp1grp" }; -static const char * const lp2grp[] = { "lp2grp" }; -static const char * const lp3grp[] = { "lp3grp" }; - -static const struct adi_pmx_func adi_pmx_functions[] = { - ADI_PMX_FUNCTION("uart0", uart0grp), - ADI_PMX_FUNCTION("uart0_ctsrts", uart0ctsrtsgrp), - ADI_PMX_FUNCTION("uart1", uart1grp), - ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp), - ADI_PMX_FUNCTION("rsi0", rsi0grp), - ADI_PMX_FUNCTION("eth0", eth0grp), - ADI_PMX_FUNCTION("eth1", eth1grp), - ADI_PMX_FUNCTION("spi0", spi0grp), - ADI_PMX_FUNCTION("spi1", spi1grp), - ADI_PMX_FUNCTION("twi0", twi0grp), - ADI_PMX_FUNCTION("twi1", twi1grp), - ADI_PMX_FUNCTION("rotary", rotarygrp), - ADI_PMX_FUNCTION("can0", can0grp), - ADI_PMX_FUNCTION("smc0", smc0grp), - ADI_PMX_FUNCTION("sport0", sport0grp), - ADI_PMX_FUNCTION("sport1", sport1grp), - ADI_PMX_FUNCTION("sport2", sport2grp), - ADI_PMX_FUNCTION("ppi0", ppi0grp), - ADI_PMX_FUNCTION("ppi1", ppi1grp), - ADI_PMX_FUNCTION("ppi2", ppi2grp), - ADI_PMX_FUNCTION("lp0", lp0grp), - ADI_PMX_FUNCTION("lp1", lp1grp), - ADI_PMX_FUNCTION("lp2", lp2grp), - ADI_PMX_FUNCTION("lp3", lp3grp), -}; - -static const struct adi_pinctrl_soc_data adi_bf60x_soc = { - .functions = adi_pmx_functions, - .nfunctions = ARRAY_SIZE(adi_pmx_functions), - .groups = adi_pin_groups, - .ngroups = ARRAY_SIZE(adi_pin_groups), - .pins = adi_pads, - .npins = ARRAY_SIZE(adi_pads), -}; - -void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc) -{ - *soc = &adi_bf60x_soc; -} diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c deleted file mode 100644 index 094a451db2a2..000000000000 --- a/drivers/pinctrl/pinctrl-adi2.c +++ /dev/null @@ -1,1114 +0,0 @@ -/* - * Pinctrl Driver for ADI GPIO2 controller - * - * Copyright 2007-2013 Analog Devices Inc. - * - * Licensed under the GPLv2 or later - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "pinctrl-adi2.h" -#include "core.h" - -/* -According to the BF54x HRM, pint means "pin interrupt". -http://www.analog.com/static/imported-files/processor_manuals/ADSP-BF54x_hwr_rev1.2.pdf - -ADSP-BF54x processor Blackfin processors have four SIC interrupt chan- -nels dedicated to pin interrupt purposes. These channels are managed by -four hardware blocks, called PINT0, PINT1, PINT2, and PINT3. Every PINTx -block can sense to up to 32 pins. While PINT0 and PINT1 can sense the -pins of port A and port B, PINT2 and PINT3 manage all the pins from port -C to port J as shown in Figure 9-2. - -n BF54x HRM: -The ten GPIO ports are subdivided into 8-bit half ports, resulting in lower and -upper half 8-bit units. The PINTx_ASSIGN registers control the 8-bit multi- -plexers shown in Figure 9-3. Lower half units of eight pins can be -forwarded to either byte 0 or byte 2 of either associated PINTx block. -Upper half units can be forwarded to either byte 1 or byte 3 of the pin -interrupt blocks, without further restrictions. - -All MMR registers in the pin interrupt module are 32 bits wide. To simply the -mapping logic, this driver only maps a 16-bit gpio port to the upper or lower -16 bits of a PINTx block. You can find the Figure 9-3 on page 583. - -Each IRQ domain is binding to a GPIO bank device. 2 GPIO bank devices can map -to one PINT device. Two in "struct gpio_pint" are used to ease the PINT -interrupt handler. - -The GPIO bank mapping to the lower 16 bits of the PINT device set its IRQ -domain pointer in domain[0]. The IRQ domain pointer of the other bank is set -to domain[1]. PINT interrupt handler adi_gpio_handle_pint_irq() finds out -the current domain pointer according to whether the interrupt request mask -is in lower 16 bits (domain[0]) or upper 16bits (domain[1]). - -A PINT device is not part of a GPIO port device in Blackfin. Multiple GPIO -port devices can be mapped to the same PINT device. - -*/ - -static LIST_HEAD(adi_pint_list); -static LIST_HEAD(adi_gpio_port_list); - -#define DRIVER_NAME "pinctrl-adi2" - -#define PINT_HI_OFFSET 16 - -/** - * struct gpio_port_saved - GPIO port registers that should be saved between - * power suspend and resume operations. - * - * @fer: PORTx_FER register - * @data: PORTx_DATA register - * @dir: PORTx_DIR register - * @inen: PORTx_INEN register - * @mux: PORTx_MUX register - */ -struct gpio_port_saved { - u16 fer; - u16 data; - u16 dir; - u16 inen; - u32 mux; -}; - -/* - * struct gpio_pint_saved - PINT registers saved in PM operations - * - * @assign: ASSIGN register - * @edge_set: EDGE_SET register - * @invert_set: INVERT_SET register - */ -struct gpio_pint_saved { - u32 assign; - u32 edge_set; - u32 invert_set; -}; - -/** - * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO - * banks can be mapped into one Pin interrupt controller. - * - * @node: All gpio_pint instances are added to a global list. - * @base: PINT device register base address - * @irq: IRQ of the PINT device, it is the parent IRQ of all - * GPIO IRQs mapping to this device. - * @domain: [0] irq domain of the gpio port, whose hardware interrupts are - * mapping to the low 16-bit of the pint registers. - * [1] irq domain of the gpio port, whose hardware interrupts are - * mapping to the high 16-bit of the pint registers. - * @regs: address pointer to the PINT device - * @map_count: No more than 2 GPIO banks can be mapped to this PINT device. - * @lock: This lock make sure the irq_chip operations to one PINT device - * for different GPIO interrrupts are atomic. - * @pint_map_port: Set up the mapping between one PINT device and - * multiple GPIO banks. - */ -struct gpio_pint { - struct list_head node; - void __iomem *base; - int irq; - struct irq_domain *domain[2]; - struct gpio_pint_regs *regs; - struct gpio_pint_saved saved_data; - int map_count; - spinlock_t lock; - - int (*pint_map_port)(struct gpio_pint *pint, bool assign, - u8 map, struct irq_domain *domain); -}; - -/** - * ADI pin controller - * - * @dev: a pointer back to containing device - * @pctl: the pinctrl device - * @soc: SoC data for this specific chip - */ -struct adi_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl; - const struct adi_pinctrl_soc_data *soc; -}; - -/** - * struct gpio_port - GPIO bank device. Multiple ADI GPIO banks can be mapped - * into one pin interrupt controller. - * - * @node: All gpio_port instances are added to a list. - * @base: GPIO bank device register base address - * @irq_base: base IRQ of the GPIO bank device - * @width: PIN number of the GPIO bank device - * @regs: address pointer to the GPIO bank device - * @saved_data: registers that should be saved between PM operations. - * @dev: device structure of this GPIO bank - * @pint: GPIO PINT device that this GPIO bank mapped to - * @pint_map: GIOP bank mapping code in PINT device - * @pint_assign: The 32-bit PINT registers can be divided into 2 parts. A - * GPIO bank can be mapped into either low 16 bits[0] or high 16 - * bits[1] of each PINT register. - * @lock: This lock make sure the irq_chip operations to one PINT device - * for different GPIO interrrupts are atomic. - * @chip: abstract a GPIO controller - * @domain: The irq domain owned by the GPIO port. - * @rsvmap: Reservation map array for each pin in the GPIO bank - */ -struct gpio_port { - struct list_head node; - void __iomem *base; - int irq_base; - unsigned int width; - struct gpio_port_t *regs; - struct gpio_port_saved saved_data; - struct device *dev; - - struct gpio_pint *pint; - u8 pint_map; - bool pint_assign; - - spinlock_t lock; - struct gpio_chip chip; - struct irq_domain *domain; -}; - -static inline u8 pin_to_offset(struct pinctrl_gpio_range *range, unsigned pin) -{ - return pin - range->pin_base; -} - -static inline u32 hwirq_to_pintbit(struct gpio_port *port, int hwirq) -{ - return port->pint_assign ? BIT(hwirq) << PINT_HI_OFFSET : BIT(hwirq); -} - -static struct gpio_pint *find_gpio_pint(unsigned id) -{ - struct gpio_pint *pint; - int i = 0; - - list_for_each_entry(pint, &adi_pint_list, node) { - if (id == i) - return pint; - i++; - } - - return NULL; -} - -static inline void port_setup(struct gpio_port *port, unsigned offset, - bool use_for_gpio) -{ - struct gpio_port_t *regs = port->regs; - - if (use_for_gpio) - writew(readw(®s->port_fer) & ~BIT(offset), - ®s->port_fer); - else - writew(readw(®s->port_fer) | BIT(offset), ®s->port_fer); -} - -static inline void portmux_setup(struct gpio_port *port, unsigned offset, - unsigned short function) -{ - struct gpio_port_t *regs = port->regs; - u32 pmux; - - pmux = readl(®s->port_mux); - - /* The function field of each pin has 2 consecutive bits in - * the mux register. - */ - pmux &= ~(0x3 << (2 * offset)); - pmux |= (function & 0x3) << (2 * offset); - - writel(pmux, ®s->port_mux); -} - -static inline u16 get_portmux(struct gpio_port *port, unsigned offset) -{ - struct gpio_port_t *regs = port->regs; - u32 pmux = readl(®s->port_mux); - - /* The function field of each pin has 2 consecutive bits in - * the mux register. - */ - return pmux >> (2 * offset) & 0x3; -} - -static void adi_gpio_ack_irq(struct irq_data *d) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *regs = port->pint->regs; - unsigned pintbit = hwirq_to_pintbit(port, d->hwirq); - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { - if (readl(®s->invert_set) & pintbit) - writel(pintbit, ®s->invert_clear); - else - writel(pintbit, ®s->invert_set); - } - - writel(pintbit, ®s->request); - - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); -} - -static void adi_gpio_mask_ack_irq(struct irq_data *d) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *regs = port->pint->regs; - unsigned pintbit = hwirq_to_pintbit(port, d->hwirq); - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { - if (readl(®s->invert_set) & pintbit) - writel(pintbit, ®s->invert_clear); - else - writel(pintbit, ®s->invert_set); - } - - writel(pintbit, ®s->request); - writel(pintbit, ®s->mask_clear); - - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); -} - -static void adi_gpio_mask_irq(struct irq_data *d) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *regs = port->pint->regs; - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear); - - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); -} - -static void adi_gpio_unmask_irq(struct irq_data *d) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *regs = port->pint->regs; - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set); - - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); -} - -static unsigned int adi_gpio_irq_startup(struct irq_data *d) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *regs; - - if (!port) { - pr_err("GPIO IRQ %d :Not exist\n", d->irq); - /* FIXME: negative return code will be ignored */ - return -ENODEV; - } - - regs = port->pint->regs; - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - port_setup(port, d->hwirq, true); - writew(BIT(d->hwirq), &port->regs->dir_clear); - writew(readw(&port->regs->inen) | BIT(d->hwirq), &port->regs->inen); - - writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set); - - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); - - return 0; -} - -static void adi_gpio_irq_shutdown(struct irq_data *d) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *regs = port->pint->regs; - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear); - - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); -} - -static int adi_gpio_irq_type(struct irq_data *d, unsigned int type) -{ - unsigned long flags; - struct gpio_port *port = irq_data_get_irq_chip_data(d); - struct gpio_pint_regs *pint_regs; - unsigned pintmask; - unsigned int irq = d->irq; - int ret = 0; - char buf[16]; - - if (!port) { - pr_err("GPIO IRQ %d :Not exist\n", d->irq); - return -ENODEV; - } - - pint_regs = port->pint->regs; - - pintmask = hwirq_to_pintbit(port, d->hwirq); - - spin_lock_irqsave(&port->lock, flags); - spin_lock(&port->pint->lock); - - /* In case of interrupt autodetect, set irq type to edge sensitive. */ - if (type == IRQ_TYPE_PROBE) - type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; - - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | - IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { - snprintf(buf, 16, "gpio-irq%u", irq); - port_setup(port, d->hwirq, true); - } else - goto out; - - /* The GPIO interrupt is triggered only when its input value - * transfer from 0 to 1. So, invert the input value if the - * irq type is low or falling - */ - if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) - writel(pintmask, &pint_regs->invert_set); - else - writel(pintmask, &pint_regs->invert_clear); - - /* In edge sensitive case, if the input value of the requested irq - * is already 1, invert it. - */ - if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { - if (gpio_get_value(port->chip.base + d->hwirq)) - writel(pintmask, &pint_regs->invert_set); - else - writel(pintmask, &pint_regs->invert_clear); - } - - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - writel(pintmask, &pint_regs->edge_set); - irq_set_handler_locked(d, handle_edge_irq); - } else { - writel(pintmask, &pint_regs->edge_clear); - irq_set_handler_locked(d, handle_level_irq); - } - -out: - spin_unlock(&port->pint->lock); - spin_unlock_irqrestore(&port->lock, flags); - - return ret; -} - -#ifdef CONFIG_PM -static int adi_gpio_set_wake(struct irq_data *d, unsigned int state) -{ - struct gpio_port *port = irq_data_get_irq_chip_data(d); - - if (!port || !port->pint || port->pint->irq != d->irq) - return -EINVAL; - -#ifndef SEC_GCTL - adi_internal_set_wake(port->pint->irq, state); -#endif - - return 0; -} - -static int adi_pint_suspend(void) -{ - struct gpio_pint *pint; - - list_for_each_entry(pint, &adi_pint_list, node) { - writel(0xffffffff, &pint->regs->mask_clear); - pint->saved_data.assign = readl(&pint->regs->assign); - pint->saved_data.edge_set = readl(&pint->regs->edge_set); - pint->saved_data.invert_set = readl(&pint->regs->invert_set); - } - - return 0; -} - -static void adi_pint_resume(void) -{ - struct gpio_pint *pint; - - list_for_each_entry(pint, &adi_pint_list, node) { - writel(pint->saved_data.assign, &pint->regs->assign); - writel(pint->saved_data.edge_set, &pint->regs->edge_set); - writel(pint->saved_data.invert_set, &pint->regs->invert_set); - } -} - -static int adi_gpio_suspend(void) -{ - struct gpio_port *port; - - list_for_each_entry(port, &adi_gpio_port_list, node) { - port->saved_data.fer = readw(&port->regs->port_fer); - port->saved_data.mux = readl(&port->regs->port_mux); - port->saved_data.data = readw(&port->regs->data); - port->saved_data.inen = readw(&port->regs->inen); - port->saved_data.dir = readw(&port->regs->dir_set); - } - - return adi_pint_suspend(); -} - -static void adi_gpio_resume(void) -{ - struct gpio_port *port; - - adi_pint_resume(); - - list_for_each_entry(port, &adi_gpio_port_list, node) { - writel(port->saved_data.mux, &port->regs->port_mux); - writew(port->saved_data.fer, &port->regs->port_fer); - writew(port->saved_data.inen, &port->regs->inen); - writew(port->saved_data.data & port->saved_data.dir, - &port->regs->data_set); - writew(port->saved_data.dir, &port->regs->dir_set); - } - -} - -static struct syscore_ops gpio_pm_syscore_ops = { - .suspend = adi_gpio_suspend, - .resume = adi_gpio_resume, -}; -#else /* CONFIG_PM */ -#define adi_gpio_set_wake NULL -#endif /* CONFIG_PM */ - -#ifdef CONFIG_IRQ_PREFLOW_FASTEOI -static inline void preflow_handler(struct irq_desc *desc) -{ - if (desc->preflow_handler) - desc->preflow_handler(&desc->irq_data); -} -#else -static inline void preflow_handler(struct irq_desc *desc) { } -#endif - -static void adi_gpio_handle_pint_irq(struct irq_desc *desc) -{ - u32 request; - u32 level_mask, hwirq; - bool umask = false; - struct gpio_pint *pint = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); - struct gpio_pint_regs *regs = pint->regs; - struct irq_domain *domain; - - preflow_handler(desc); - chained_irq_enter(chip, desc); - - request = readl(®s->request); - level_mask = readl(®s->edge_set) & request; - - hwirq = 0; - domain = pint->domain[0]; - while (request) { - /* domain pointer need to be changed only once at IRQ 16 when - * we go through IRQ requests from bit 0 to bit 31. - */ - if (hwirq == PINT_HI_OFFSET) - domain = pint->domain[1]; - - if (request & 1) { - if (level_mask & BIT(hwirq)) { - umask = true; - chained_irq_exit(chip, desc); - } - generic_handle_irq(irq_find_mapping(domain, - hwirq % PINT_HI_OFFSET)); - } - - hwirq++; - request >>= 1; - } - - if (!umask) - chained_irq_exit(chip, desc); -} - -static struct irq_chip adi_gpio_irqchip = { - .name = "GPIO", - .irq_ack = adi_gpio_ack_irq, - .irq_mask = adi_gpio_mask_irq, - .irq_mask_ack = adi_gpio_mask_ack_irq, - .irq_unmask = adi_gpio_unmask_irq, - .irq_disable = adi_gpio_mask_irq, - .irq_enable = adi_gpio_unmask_irq, - .irq_set_type = adi_gpio_irq_type, - .irq_startup = adi_gpio_irq_startup, - .irq_shutdown = adi_gpio_irq_shutdown, - .irq_set_wake = adi_gpio_set_wake, -}; - -static int adi_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - - return pinctrl->soc->ngroups; -} - -static const char *adi_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - - return pinctrl->soc->groups[selector].name; -} - -static int adi_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *num_pins) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - - *pins = pinctrl->soc->groups[selector].pins; - *num_pins = pinctrl->soc->groups[selector].num; - return 0; -} - -static const struct pinctrl_ops adi_pctrl_ops = { - .get_groups_count = adi_get_groups_count, - .get_group_name = adi_get_group_name, - .get_group_pins = adi_get_group_pins, -}; - -static int adi_pinmux_set(struct pinctrl_dev *pctldev, unsigned func_id, - unsigned group_id) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - struct gpio_port *port; - struct pinctrl_gpio_range *range; - unsigned long flags; - unsigned short *mux, pin; - - mux = (unsigned short *)pinctrl->soc->groups[group_id].mux; - - while (*mux) { - pin = P_IDENT(*mux); - - range = pinctrl_find_gpio_range_from_pin(pctldev, pin); - if (range == NULL) /* should not happen */ - return -ENODEV; - - port = gpiochip_get_data(range->gc); - - spin_lock_irqsave(&port->lock, flags); - - portmux_setup(port, pin_to_offset(range, pin), - P_FUNCT2MUX(*mux)); - port_setup(port, pin_to_offset(range, pin), false); - mux++; - - spin_unlock_irqrestore(&port->lock, flags); - } - - return 0; -} - -static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - - return pinctrl->soc->nfunctions; -} - -static const char *adi_pinmux_get_func_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - - return pinctrl->soc->functions[selector].name; -} - -static int adi_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); - - *groups = pinctrl->soc->functions[selector].groups; - *num_groups = pinctrl->soc->functions[selector].num_groups; - return 0; -} - -static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, unsigned pin) -{ - struct gpio_port *port; - unsigned long flags; - u8 offset; - - port = gpiochip_get_data(range->gc); - offset = pin_to_offset(range, pin); - - spin_lock_irqsave(&port->lock, flags); - - port_setup(port, offset, true); - - spin_unlock_irqrestore(&port->lock, flags); - - return 0; -} - -static const struct pinmux_ops adi_pinmux_ops = { - .set_mux = adi_pinmux_set, - .get_functions_count = adi_pinmux_get_funcs_count, - .get_function_name = adi_pinmux_get_func_name, - .get_function_groups = adi_pinmux_get_groups, - .gpio_request_enable = adi_pinmux_request_gpio, - .strict = true, -}; - - -static struct pinctrl_desc adi_pinmux_desc = { - .name = DRIVER_NAME, - .pctlops = &adi_pctrl_ops, - .pmxops = &adi_pinmux_ops, - .owner = THIS_MODULE, -}; - -static int adi_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - struct gpio_port *port; - unsigned long flags; - - port = gpiochip_get_data(chip); - - spin_lock_irqsave(&port->lock, flags); - - writew(BIT(offset), &port->regs->dir_clear); - writew(readw(&port->regs->inen) | BIT(offset), &port->regs->inen); - - spin_unlock_irqrestore(&port->lock, flags); - - return 0; -} - -static void adi_gpio_set_value(struct gpio_chip *chip, unsigned offset, - int value) -{ - struct gpio_port *port = gpiochip_get_data(chip); - struct gpio_port_t *regs = port->regs; - unsigned long flags; - - spin_lock_irqsave(&port->lock, flags); - - if (value) - writew(BIT(offset), ®s->data_set); - else - writew(BIT(offset), ®s->data_clear); - - spin_unlock_irqrestore(&port->lock, flags); -} - -static int adi_gpio_direction_output(struct gpio_chip *chip, unsigned offset, - int value) -{ - struct gpio_port *port = gpiochip_get_data(chip); - struct gpio_port_t *regs = port->regs; - unsigned long flags; - - spin_lock_irqsave(&port->lock, flags); - - writew(readw(®s->inen) & ~BIT(offset), ®s->inen); - if (value) - writew(BIT(offset), ®s->data_set); - else - writew(BIT(offset), ®s->data_clear); - writew(BIT(offset), ®s->dir_set); - - spin_unlock_irqrestore(&port->lock, flags); - - return 0; -} - -static int adi_gpio_get_value(struct gpio_chip *chip, unsigned offset) -{ - struct gpio_port *port = gpiochip_get_data(chip); - struct gpio_port_t *regs = port->regs; - unsigned long flags; - int ret; - - spin_lock_irqsave(&port->lock, flags); - - ret = !!(readw(®s->data) & BIT(offset)); - - spin_unlock_irqrestore(&port->lock, flags); - - return ret; -} - -static int adi_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct gpio_port *port = gpiochip_get_data(chip); - - if (port->irq_base >= 0) - return irq_find_mapping(port->domain, offset); - else - return irq_create_mapping(port->domain, offset); -} - -static int adi_pint_map_port(struct gpio_pint *pint, bool assign, u8 map, - struct irq_domain *domain) -{ - struct gpio_pint_regs *regs = pint->regs; - u32 map_mask; - - if (pint->map_count > 1) - return -EINVAL; - - pint->map_count++; - - /* The map_mask of each gpio port is a 16-bit duplicate - * of the 8-bit map. It can be set to either high 16 bits or low - * 16 bits of the pint assignment register. - */ - map_mask = (map << 8) | map; - if (assign) { - map_mask <<= PINT_HI_OFFSET; - writel((readl(®s->assign) & 0xFFFF) | map_mask, - ®s->assign); - } else - writel((readl(®s->assign) & 0xFFFF0000) | map_mask, - ®s->assign); - - pint->domain[assign] = domain; - - return 0; -} - -static int adi_gpio_pint_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct resource *res; - struct gpio_pint *pint = devm_kzalloc(dev, sizeof(*pint), GFP_KERNEL); - - if (!pint) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pint->base = devm_ioremap_resource(dev, res); - if (IS_ERR(pint->base)) - return PTR_ERR(pint->base); - - pint->regs = (struct gpio_pint_regs *)pint->base; - - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res) { - dev_err(dev, "Invalid IRQ resource\n"); - return -ENODEV; - } - - spin_lock_init(&pint->lock); - - pint->irq = res->start; - pint->pint_map_port = adi_pint_map_port; - platform_set_drvdata(pdev, pint); - - irq_set_chained_handler_and_data(pint->irq, adi_gpio_handle_pint_irq, - pint); - - list_add_tail(&pint->node, &adi_pint_list); - - return 0; -} - -static int adi_gpio_pint_remove(struct platform_device *pdev) -{ - struct gpio_pint *pint = platform_get_drvdata(pdev); - - list_del(&pint->node); - irq_set_handler(pint->irq, handle_simple_irq); - - return 0; -} - -static int adi_gpio_irq_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hwirq) -{ - struct gpio_port *port = d->host_data; - - if (!port) - return -EINVAL; - - irq_set_chip_data(irq, port); - irq_set_chip_and_handler(irq, &adi_gpio_irqchip, - handle_level_irq); - - return 0; -} - -static const struct irq_domain_ops adi_gpio_irq_domain_ops = { - .map = adi_gpio_irq_map, - .xlate = irq_domain_xlate_onecell, -}; - -static int adi_gpio_init_int(struct gpio_port *port) -{ - struct device_node *node = port->dev->of_node; - struct gpio_pint *pint = port->pint; - int ret; - - port->domain = irq_domain_add_linear(node, port->width, - &adi_gpio_irq_domain_ops, port); - if (!port->domain) { - dev_err(port->dev, "Failed to create irqdomain\n"); - return -ENOSYS; - } - - /* According to BF54x and BF60x HRM, pin interrupt devices are not - * part of the GPIO port device. in GPIO interrupt mode, the GPIO - * pins of multiple port devices can be routed into one pin interrupt - * device. The mapping can be configured by setting pint assignment - * register with the mapping value of different GPIO port. This is - * done via function pint_map_port(). - */ - ret = pint->pint_map_port(port->pint, port->pint_assign, - port->pint_map, port->domain); - if (ret) - return ret; - - if (port->irq_base >= 0) { - ret = irq_create_strict_mappings(port->domain, port->irq_base, - 0, port->width); - if (ret) { - dev_err(port->dev, "Couldn't associate to domain\n"); - return ret; - } - } - - return 0; -} - -#define DEVNAME_SIZE 16 - -static int adi_gpio_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - const struct adi_pinctrl_gpio_platform_data *pdata; - struct resource *res; - struct gpio_port *port; - char pinctrl_devname[DEVNAME_SIZE]; - static int gpio; - int ret = 0; - - pdata = dev->platform_data; - if (!pdata) - return -EINVAL; - - port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); - if (!port) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - port->base = devm_ioremap_resource(dev, res); - if (IS_ERR(port->base)) - return PTR_ERR(port->base); - - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res) - port->irq_base = -1; - else - port->irq_base = res->start; - - port->width = pdata->port_width; - port->dev = dev; - port->regs = (struct gpio_port_t *)port->base; - port->pint_assign = pdata->pint_assign; - port->pint_map = pdata->pint_map; - - port->pint = find_gpio_pint(pdata->pint_id); - if (port->pint) { - ret = adi_gpio_init_int(port); - if (ret) - return ret; - } - - spin_lock_init(&port->lock); - - platform_set_drvdata(pdev, port); - - port->chip.label = "adi-gpio"; - port->chip.direction_input = adi_gpio_direction_input; - port->chip.get = adi_gpio_get_value; - port->chip.direction_output = adi_gpio_direction_output; - port->chip.set = adi_gpio_set_value; - port->chip.request = gpiochip_generic_request, - port->chip.free = gpiochip_generic_free, - port->chip.to_irq = adi_gpio_to_irq; - if (pdata->port_gpio_base > 0) - port->chip.base = pdata->port_gpio_base; - else - port->chip.base = gpio; - port->chip.ngpio = port->width; - gpio = port->chip.base + port->width; - - ret = gpiochip_add_data(&port->chip, port); - if (ret) { - dev_err(&pdev->dev, "Fail to add GPIO chip.\n"); - goto out_remove_domain; - } - - /* Add gpio pin range */ - snprintf(pinctrl_devname, DEVNAME_SIZE, "pinctrl-adi2.%d", - pdata->pinctrl_id); - pinctrl_devname[DEVNAME_SIZE - 1] = 0; - ret = gpiochip_add_pin_range(&port->chip, pinctrl_devname, - 0, pdata->port_pin_base, port->width); - if (ret) { - dev_err(&pdev->dev, "Fail to add pin range to %s.\n", - pinctrl_devname); - goto out_remove_gpiochip; - } - - list_add_tail(&port->node, &adi_gpio_port_list); - - return 0; - -out_remove_gpiochip: - gpiochip_remove(&port->chip); -out_remove_domain: - if (port->pint) - irq_domain_remove(port->domain); - - return ret; -} - -static int adi_gpio_remove(struct platform_device *pdev) -{ - struct gpio_port *port = platform_get_drvdata(pdev); - u8 offset; - - list_del(&port->node); - gpiochip_remove(&port->chip); - if (port->pint) { - for (offset = 0; offset < port->width; offset++) - irq_dispose_mapping(irq_find_mapping(port->domain, - offset)); - irq_domain_remove(port->domain); - } - - return 0; -} - -static int adi_pinctrl_probe(struct platform_device *pdev) -{ - struct adi_pinctrl *pinctrl; - - pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL); - if (!pinctrl) - return -ENOMEM; - - pinctrl->dev = &pdev->dev; - - adi_pinctrl_soc_init(&pinctrl->soc); - - adi_pinmux_desc.pins = pinctrl->soc->pins; - adi_pinmux_desc.npins = pinctrl->soc->npins; - - /* Now register the pin controller and all pins it handles */ - pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &adi_pinmux_desc, - pinctrl); - if (IS_ERR(pinctrl->pctl)) { - dev_err(&pdev->dev, "could not register pinctrl ADI2 driver\n"); - return PTR_ERR(pinctrl->pctl); - } - - platform_set_drvdata(pdev, pinctrl); - - return 0; -} - -static struct platform_driver adi_pinctrl_driver = { - .probe = adi_pinctrl_probe, - .driver = { - .name = DRIVER_NAME, - }, -}; - -static struct platform_driver adi_gpio_pint_driver = { - .probe = adi_gpio_pint_probe, - .remove = adi_gpio_pint_remove, - .driver = { - .name = "adi-gpio-pint", - }, -}; - -static struct platform_driver adi_gpio_driver = { - .probe = adi_gpio_probe, - .remove = adi_gpio_remove, - .driver = { - .name = "adi-gpio", - }, -}; - -static struct platform_driver * const drivers[] = { - &adi_pinctrl_driver, - &adi_gpio_pint_driver, - &adi_gpio_driver, -}; - -static int __init adi_pinctrl_setup(void) -{ - int ret; - - ret = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); - if (ret) - return ret; - -#ifdef CONFIG_PM - register_syscore_ops(&gpio_pm_syscore_ops); -#endif - return 0; -} -arch_initcall(adi_pinctrl_setup); - -MODULE_AUTHOR("Sonic Zhang "); -MODULE_DESCRIPTION("ADI gpio2 pin control driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-adi2.h b/drivers/pinctrl/pinctrl-adi2.h deleted file mode 100644 index 3ca29738213f..000000000000 --- a/drivers/pinctrl/pinctrl-adi2.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Pinctrl Driver for ADI GPIO2 controller - * - * Copyright 2007-2013 Analog Devices Inc. - * - * Licensed under the GPLv2 or later - */ - -#ifndef PINCTRL_PINCTRL_ADI2_H -#define PINCTRL_PINCTRL_ADI2_H - -#include - - /** - * struct adi_pin_group - describes a pin group - * @name: the name of this pin group - * @pins: an array of pins - * @num: the number of pins in this array - */ -struct adi_pin_group { - const char *name; - const unsigned *pins; - const unsigned num; - const unsigned short *mux; -}; - -#define ADI_PIN_GROUP(n, p, m) \ - { \ - .name = n, \ - .pins = p, \ - .num = ARRAY_SIZE(p), \ - .mux = m, \ - } - - /** - * struct adi_pmx_func - describes function mux setting of pin groups - * @name: the name of this function mux setting - * @groups: an array of pin groups - * @num_groups: the number of pin groups in this array - * @mux: the function mux setting array, end by zero - */ -struct adi_pmx_func { - const char *name; - const char * const *groups; - const unsigned num_groups; -}; - -#define ADI_PMX_FUNCTION(n, g) \ - { \ - .name = n, \ - .groups = g, \ - .num_groups = ARRAY_SIZE(g), \ - } - -/** - * struct adi_pinctrl_soc_data - ADI pin controller per-SoC configuration - * @functions: The functions supported on this SoC. - * @nfunction: The number of entries in @functions. - * @groups: An array describing all pin groups the pin SoC supports. - * @ngroups: The number of entries in @groups. - * @pins: An array describing all pins the pin controller affects. - * @npins: The number of entries in @pins. - */ -struct adi_pinctrl_soc_data { - const struct adi_pmx_func *functions; - int nfunctions; - const struct adi_pin_group *groups; - int ngroups; - const struct pinctrl_pin_desc *pins; - int npins; -}; - -void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc); - -#endif /* PINCTRL_PINCTRL_ADI2_H */ diff --git a/include/linux/platform_data/pinctrl-adi2.h b/include/linux/platform_data/pinctrl-adi2.h deleted file mode 100644 index 8f91300617ec..000000000000 --- a/include/linux/platform_data/pinctrl-adi2.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Pinctrl Driver for ADI GPIO2 controller - * - * Copyright 2007-2013 Analog Devices Inc. - * - * Licensed under the GPLv2 or later - */ - - -#ifndef PINCTRL_ADI2_H -#define PINCTRL_ADI2_H - -#include -#include - -/** - * struct adi_pinctrl_gpio_platform_data - Pinctrl gpio platform data - * for ADI GPIO2 device. - * - * @port_gpio_base: Optional global GPIO index of the GPIO bank. - * 0 means driver decides. - * @port_pin_base: Pin index of the pin controller device. - * @port_width: PIN number of the GPIO bank device - * @pint_id: GPIO PINT device id that this GPIO bank should map to. - * @pint_assign: The 32-bit GPIO PINT registers can be divided into 2 parts. A - * GPIO bank can be mapped into either low 16 bits[0] or high 16 - * bits[1] of each PINT register. - * @pint_map: GIOP bank mapping code in PINT device - */ -struct adi_pinctrl_gpio_platform_data { - unsigned int port_gpio_base; - unsigned int port_pin_base; - unsigned int port_width; - u8 pinctrl_id; - u8 pint_id; - bool pint_assign; - u8 pint_map; -}; - -#endif -- cgit v1.2.3 From c957ea5c797cfccffeee92e0af8e0e99212dd755 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Mar 2018 17:24:55 +0100 Subject: input: misc: remove blackfin rotary driver The blackfin architecture is getting removed, so this one is obsolete as well. Acked-by: Dmitry Torokhov Acked-by: Aaron Wu Signed-off-by: Arnd Bergmann --- drivers/input/misc/Kconfig | 9 - drivers/input/misc/Makefile | 1 - drivers/input/misc/bfin_rotary.c | 294 ------------------------------ include/linux/platform_data/bfin_rotary.h | 117 ------------ 4 files changed, 421 deletions(-) delete mode 100644 drivers/input/misc/bfin_rotary.c delete mode 100644 include/linux/platform_data/bfin_rotary.h (limited to 'include/linux/platform_data') diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 62a1312a7387..e9770f5e3f77 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -655,15 +655,6 @@ config INPUT_DM355EVM To compile this driver as a module, choose M here: the module will be called dm355evm_keys. -config INPUT_BFIN_ROTARY - tristate "Blackfin Rotary support" - depends on BF54x || BF52x - help - Say Y here if you want to use the Blackfin Rotary. - - To compile this driver as a module, choose M here: the - module will be called bfin-rotary. - config INPUT_WM831X_ON tristate "WM831X ON pin" depends on MFD_WM831X diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index a8f61af865aa..eb9c6c3ec530 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -19,7 +19,6 @@ obj-$(CONFIG_INPUT_ARIZONA_HAPTICS) += arizona-haptics.o obj-$(CONFIG_INPUT_ATI_REMOTE2) += ati_remote2.o obj-$(CONFIG_INPUT_ATLAS_BTNS) += atlas_btns.o obj-$(CONFIG_INPUT_ATMEL_CAPTOUCH) += atmel_captouch.o -obj-$(CONFIG_INPUT_BFIN_ROTARY) += bfin_rotary.o obj-$(CONFIG_INPUT_BMA150) += bma150.o obj-$(CONFIG_INPUT_CM109) += cm109.o obj-$(CONFIG_INPUT_CMA3000) += cma3000_d0x.o diff --git a/drivers/input/misc/bfin_rotary.c b/drivers/input/misc/bfin_rotary.c deleted file mode 100644 index 799ce3d2820e..000000000000 --- a/drivers/input/misc/bfin_rotary.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Rotary counter driver for Analog Devices Blackfin Processors - * - * Copyright 2008-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define CNT_CONFIG_OFF 0 /* CNT Config Offset */ -#define CNT_IMASK_OFF 4 /* CNT Interrupt Mask Offset */ -#define CNT_STATUS_OFF 8 /* CNT Status Offset */ -#define CNT_COMMAND_OFF 12 /* CNT Command Offset */ -#define CNT_DEBOUNCE_OFF 16 /* CNT Debounce Offset */ -#define CNT_COUNTER_OFF 20 /* CNT Counter Offset */ -#define CNT_MAX_OFF 24 /* CNT Maximum Count Offset */ -#define CNT_MIN_OFF 28 /* CNT Minimum Count Offset */ - -struct bfin_rot { - struct input_dev *input; - void __iomem *base; - int irq; - unsigned int up_key; - unsigned int down_key; - unsigned int button_key; - unsigned int rel_code; - - unsigned short mode; - unsigned short debounce; - - unsigned short cnt_config; - unsigned short cnt_imask; - unsigned short cnt_debounce; -}; - -static void report_key_event(struct input_dev *input, int keycode) -{ - /* simulate a press-n-release */ - input_report_key(input, keycode, 1); - input_sync(input); - input_report_key(input, keycode, 0); - input_sync(input); -} - -static void report_rotary_event(struct bfin_rot *rotary, int delta) -{ - struct input_dev *input = rotary->input; - - if (rotary->up_key) { - report_key_event(input, - delta > 0 ? rotary->up_key : rotary->down_key); - } else { - input_report_rel(input, rotary->rel_code, delta); - input_sync(input); - } -} - -static irqreturn_t bfin_rotary_isr(int irq, void *dev_id) -{ - struct bfin_rot *rotary = dev_id; - int delta; - - switch (readw(rotary->base + CNT_STATUS_OFF)) { - - case ICII: - break; - - case UCII: - case DCII: - delta = readl(rotary->base + CNT_COUNTER_OFF); - if (delta) - report_rotary_event(rotary, delta); - break; - - case CZMII: - report_key_event(rotary->input, rotary->button_key); - break; - - default: - break; - } - - writew(W1LCNT_ZERO, rotary->base + CNT_COMMAND_OFF); /* Clear COUNTER */ - writew(-1, rotary->base + CNT_STATUS_OFF); /* Clear STATUS */ - - return IRQ_HANDLED; -} - -static int bfin_rotary_open(struct input_dev *input) -{ - struct bfin_rot *rotary = input_get_drvdata(input); - unsigned short val; - - if (rotary->mode & ROT_DEBE) - writew(rotary->debounce & DPRESCALE, - rotary->base + CNT_DEBOUNCE_OFF); - - writew(rotary->mode & ~CNTE, rotary->base + CNT_CONFIG_OFF); - - val = UCIE | DCIE; - if (rotary->button_key) - val |= CZMIE; - writew(val, rotary->base + CNT_IMASK_OFF); - - writew(rotary->mode | CNTE, rotary->base + CNT_CONFIG_OFF); - - return 0; -} - -static void bfin_rotary_close(struct input_dev *input) -{ - struct bfin_rot *rotary = input_get_drvdata(input); - - writew(0, rotary->base + CNT_CONFIG_OFF); - writew(0, rotary->base + CNT_IMASK_OFF); -} - -static void bfin_rotary_free_action(void *data) -{ - peripheral_free_list(data); -} - -static int bfin_rotary_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - const struct bfin_rotary_platform_data *pdata = dev_get_platdata(dev); - struct bfin_rot *rotary; - struct resource *res; - struct input_dev *input; - int error; - - /* Basic validation */ - if ((pdata->rotary_up_key && !pdata->rotary_down_key) || - (!pdata->rotary_up_key && pdata->rotary_down_key)) { - return -EINVAL; - } - - if (pdata->pin_list) { - error = peripheral_request_list(pdata->pin_list, - dev_name(dev)); - if (error) { - dev_err(dev, "requesting peripherals failed: %d\n", - error); - return error; - } - - error = devm_add_action_or_reset(dev, bfin_rotary_free_action, - pdata->pin_list); - if (error) { - dev_err(dev, "setting cleanup action failed: %d\n", - error); - return error; - } - } - - rotary = devm_kzalloc(dev, sizeof(struct bfin_rot), GFP_KERNEL); - if (!rotary) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - rotary->base = devm_ioremap_resource(dev, res); - if (IS_ERR(rotary->base)) - return PTR_ERR(rotary->base); - - input = devm_input_allocate_device(dev); - if (!input) - return -ENOMEM; - - rotary->input = input; - - rotary->up_key = pdata->rotary_up_key; - rotary->down_key = pdata->rotary_down_key; - rotary->button_key = pdata->rotary_button_key; - rotary->rel_code = pdata->rotary_rel_code; - - rotary->mode = pdata->mode; - rotary->debounce = pdata->debounce; - - input->name = pdev->name; - input->phys = "bfin-rotary/input0"; - input->dev.parent = dev; - - input_set_drvdata(input, rotary); - - input->id.bustype = BUS_HOST; - input->id.vendor = 0x0001; - input->id.product = 0x0001; - input->id.version = 0x0100; - - input->open = bfin_rotary_open; - input->close = bfin_rotary_close; - - if (rotary->up_key) { - __set_bit(EV_KEY, input->evbit); - __set_bit(rotary->up_key, input->keybit); - __set_bit(rotary->down_key, input->keybit); - } else { - __set_bit(EV_REL, input->evbit); - __set_bit(rotary->rel_code, input->relbit); - } - - if (rotary->button_key) { - __set_bit(EV_KEY, input->evbit); - __set_bit(rotary->button_key, input->keybit); - } - - /* Quiesce the device before requesting irq */ - bfin_rotary_close(input); - - rotary->irq = platform_get_irq(pdev, 0); - if (rotary->irq < 0) { - dev_err(dev, "No rotary IRQ specified\n"); - return -ENOENT; - } - - error = devm_request_irq(dev, rotary->irq, bfin_rotary_isr, - 0, dev_name(dev), rotary); - if (error) { - dev_err(dev, "unable to claim irq %d; error %d\n", - rotary->irq, error); - return error; - } - - error = input_register_device(input); - if (error) { - dev_err(dev, "unable to register input device (%d)\n", error); - return error; - } - - platform_set_drvdata(pdev, rotary); - device_init_wakeup(dev, 1); - - return 0; -} - -static int __maybe_unused bfin_rotary_suspend(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - struct bfin_rot *rotary = platform_get_drvdata(pdev); - - rotary->cnt_config = readw(rotary->base + CNT_CONFIG_OFF); - rotary->cnt_imask = readw(rotary->base + CNT_IMASK_OFF); - rotary->cnt_debounce = readw(rotary->base + CNT_DEBOUNCE_OFF); - - if (device_may_wakeup(&pdev->dev)) - enable_irq_wake(rotary->irq); - - return 0; -} - -static int __maybe_unused bfin_rotary_resume(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - struct bfin_rot *rotary = platform_get_drvdata(pdev); - - writew(rotary->cnt_debounce, rotary->base + CNT_DEBOUNCE_OFF); - writew(rotary->cnt_imask, rotary->base + CNT_IMASK_OFF); - writew(rotary->cnt_config & ~CNTE, rotary->base + CNT_CONFIG_OFF); - - if (device_may_wakeup(&pdev->dev)) - disable_irq_wake(rotary->irq); - - if (rotary->cnt_config & CNTE) - writew(rotary->cnt_config, rotary->base + CNT_CONFIG_OFF); - - return 0; -} - -static SIMPLE_DEV_PM_OPS(bfin_rotary_pm_ops, - bfin_rotary_suspend, bfin_rotary_resume); - -static struct platform_driver bfin_rotary_device_driver = { - .probe = bfin_rotary_probe, - .driver = { - .name = "bfin-rotary", - .pm = &bfin_rotary_pm_ops, - }, -}; -module_platform_driver(bfin_rotary_device_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Michael Hennerich "); -MODULE_DESCRIPTION("Rotary Counter driver for Blackfin Processors"); -MODULE_ALIAS("platform:bfin-rotary"); diff --git a/include/linux/platform_data/bfin_rotary.h b/include/linux/platform_data/bfin_rotary.h deleted file mode 100644 index 98829370fee2..000000000000 --- a/include/linux/platform_data/bfin_rotary.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * board initialization should put one of these structures into platform_data - * and place the bfin-rotary onto platform_bus named "bfin-rotary". - * - * Copyright 2008-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BFIN_ROTARY_H -#define _BFIN_ROTARY_H - -/* mode bitmasks */ -#define ROT_QUAD_ENC CNTMODE_QUADENC /* quadrature/grey code encoder mode */ -#define ROT_BIN_ENC CNTMODE_BINENC /* binary encoder mode */ -#define ROT_UD_CNT CNTMODE_UDCNT /* rotary counter mode */ -#define ROT_DIR_CNT CNTMODE_DIRCNT /* direction counter mode */ - -#define ROT_DEBE DEBE /* Debounce Enable */ - -#define ROT_CDGINV CDGINV /* CDG Pin Polarity Invert */ -#define ROT_CUDINV CUDINV /* CUD Pin Polarity Invert */ -#define ROT_CZMINV CZMINV /* CZM Pin Polarity Invert */ - -struct bfin_rotary_platform_data { - /* set rotary UP KEY_### or BTN_### in case you prefer - * bfin-rotary to send EV_KEY otherwise set 0 - */ - unsigned int rotary_up_key; - /* set rotary DOWN KEY_### or BTN_### in case you prefer - * bfin-rotary to send EV_KEY otherwise set 0 - */ - unsigned int rotary_down_key; - /* set rotary BUTTON KEY_### or BTN_### */ - unsigned int rotary_button_key; - /* set rotary Relative Axis REL_### in case you prefer - * bfin-rotary to send EV_REL otherwise set 0 - */ - unsigned int rotary_rel_code; - unsigned short debounce; /* 0..17 */ - unsigned short mode; - unsigned short pm_wakeup; - unsigned short *pin_list; -}; - -/* CNT_CONFIG bitmasks */ -#define CNTE (1 << 0) /* Counter Enable */ -#define DEBE (1 << 1) /* Debounce Enable */ -#define CDGINV (1 << 4) /* CDG Pin Polarity Invert */ -#define CUDINV (1 << 5) /* CUD Pin Polarity Invert */ -#define CZMINV (1 << 6) /* CZM Pin Polarity Invert */ -#define CNTMODE_SHIFT 8 -#define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */ -#define ZMZC (1 << 1) /* CZM Zeroes Counter Enable */ -#define BNDMODE_SHIFT 12 -#define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */ -#define INPDIS (1 << 15) /* CUG and CDG Input Disable */ - -#define CNTMODE_QUADENC (0 << CNTMODE_SHIFT) /* quadrature encoder mode */ -#define CNTMODE_BINENC (1 << CNTMODE_SHIFT) /* binary encoder mode */ -#define CNTMODE_UDCNT (2 << CNTMODE_SHIFT) /* up/down counter mode */ -#define CNTMODE_DIRCNT (4 << CNTMODE_SHIFT) /* direction counter mode */ -#define CNTMODE_DIRTMR (5 << CNTMODE_SHIFT) /* direction timer mode */ - -#define BNDMODE_COMP (0 << BNDMODE_SHIFT) /* boundary compare mode */ -#define BNDMODE_ZERO (1 << BNDMODE_SHIFT) /* boundary compare and zero mode */ -#define BNDMODE_CAPT (2 << BNDMODE_SHIFT) /* boundary capture mode */ -#define BNDMODE_AEXT (3 << BNDMODE_SHIFT) /* boundary auto-extend mode */ - -/* CNT_IMASK bitmasks */ -#define ICIE (1 << 0) /* Illegal Gray/Binary Code Interrupt Enable */ -#define UCIE (1 << 1) /* Up count Interrupt Enable */ -#define DCIE (1 << 2) /* Down count Interrupt Enable */ -#define MINCIE (1 << 3) /* Min Count Interrupt Enable */ -#define MAXCIE (1 << 4) /* Max Count Interrupt Enable */ -#define COV31IE (1 << 5) /* Bit 31 Overflow Interrupt Enable */ -#define COV15IE (1 << 6) /* Bit 15 Overflow Interrupt Enable */ -#define CZEROIE (1 << 7) /* Count to Zero Interrupt Enable */ -#define CZMIE (1 << 8) /* CZM Pin Interrupt Enable */ -#define CZMEIE (1 << 9) /* CZM Error Interrupt Enable */ -#define CZMZIE (1 << 10) /* CZM Zeroes Counter Interrupt Enable */ - -/* CNT_STATUS bitmasks */ -#define ICII (1 << 0) /* Illegal Gray/Binary Code Interrupt Identifier */ -#define UCII (1 << 1) /* Up count Interrupt Identifier */ -#define DCII (1 << 2) /* Down count Interrupt Identifier */ -#define MINCII (1 << 3) /* Min Count Interrupt Identifier */ -#define MAXCII (1 << 4) /* Max Count Interrupt Identifier */ -#define COV31II (1 << 5) /* Bit 31 Overflow Interrupt Identifier */ -#define COV15II (1 << 6) /* Bit 15 Overflow Interrupt Identifier */ -#define CZEROII (1 << 7) /* Count to Zero Interrupt Identifier */ -#define CZMII (1 << 8) /* CZM Pin Interrupt Identifier */ -#define CZMEII (1 << 9) /* CZM Error Interrupt Identifier */ -#define CZMZII (1 << 10) /* CZM Zeroes Counter Interrupt Identifier */ - -/* CNT_COMMAND bitmasks */ -#define W1LCNT 0xf /* Load Counter Register */ -#define W1LMIN 0xf0 /* Load Min Register */ -#define W1LMAX 0xf00 /* Load Max Register */ -#define W1ZMONCE (1 << 12) /* Enable CZM Clear Counter Once */ - -#define W1LCNT_ZERO (1 << 0) /* write 1 to load CNT_COUNTER with zero */ -#define W1LCNT_MIN (1 << 2) /* write 1 to load CNT_COUNTER from CNT_MIN */ -#define W1LCNT_MAX (1 << 3) /* write 1 to load CNT_COUNTER from CNT_MAX */ - -#define W1LMIN_ZERO (1 << 4) /* write 1 to load CNT_MIN with zero */ -#define W1LMIN_CNT (1 << 5) /* write 1 to load CNT_MIN from CNT_COUNTER */ -#define W1LMIN_MAX (1 << 7) /* write 1 to load CNT_MIN from CNT_MAX */ - -#define W1LMAX_ZERO (1 << 8) /* write 1 to load CNT_MAX with zero */ -#define W1LMAX_CNT (1 << 9) /* write 1 to load CNT_MAX from CNT_COUNTER */ -#define W1LMAX_MIN (1 << 10) /* write 1 to load CNT_MAX from CNT_MIN */ - -/* CNT_DEBOUNCE bitmasks */ -#define DPRESCALE 0xf /* Load Counter Register */ - -#endif -- cgit v1.2.3 From 96a938aa214e965d5b4a2f10443b29cad14289b9 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 20 Mar 2018 15:31:38 -0700 Subject: Input: atmel_mxt_ts - remove platform data support Now that there are no users of custom Atmel platform data, and everyone has switched to the generic device properties, we can remove support for the platform data. Acked-by: Nick Dyer Signed-off-by: Dmitry Torokhov Signed-off-by: Benson Leung --- MAINTAINERS | 1 - drivers/input/touchscreen/atmel_mxt_ts.c | 130 ++++++++++++----------------- include/linux/platform_data/atmel_mxt_ts.h | 31 ------- 3 files changed, 55 insertions(+), 107 deletions(-) delete mode 100644 include/linux/platform_data/atmel_mxt_ts.h (limited to 'include/linux/platform_data') diff --git a/MAINTAINERS b/MAINTAINERS index 73c0cdabf755..d4b0b09d2e3f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2394,7 +2394,6 @@ T: git git://github.com/ndyer/linux.git S: Maintained F: Documentation/devicetree/bindings/input/atmel,maxtouch.txt F: drivers/input/touchscreen/atmel_mxt_ts.c -F: include/linux/platform_data/atmel_mxt_ts.h ATMEL SAMA5D2 ADC DRIVER M: Ludovic Desroches diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c index 799d2ac35787..5d9699fe1b55 100644 --- a/drivers/input/touchscreen/atmel_mxt_ts.c +++ b/drivers/input/touchscreen/atmel_mxt_ts.c @@ -23,10 +23,10 @@ #include #include #include -#include #include #include #include +#include #include #include #include @@ -269,12 +269,16 @@ static const struct v4l2_file_operations mxt_video_fops = { .poll = vb2_fop_poll, }; +enum mxt_suspend_mode { + MXT_SUSPEND_DEEP_SLEEP = 0, + MXT_SUSPEND_T9_CTRL = 1, +}; + /* Each client has this additional data */ struct mxt_data { struct i2c_client *client; struct input_dev *input_dev; char phys[64]; /* device physical location */ - const struct mxt_platform_data *pdata; struct mxt_object *object_table; struct mxt_info info; unsigned int irq; @@ -326,6 +330,9 @@ struct mxt_data { /* for config update handling */ struct completion crc_completion; + u32 *t19_keymap; + unsigned int t19_num_keys; + enum mxt_suspend_mode suspend_mode; }; @@ -745,15 +752,14 @@ static int mxt_write_object(struct mxt_data *data, static void mxt_input_button(struct mxt_data *data, u8 *message) { struct input_dev *input = data->input_dev; - const struct mxt_platform_data *pdata = data->pdata; int i; - for (i = 0; i < pdata->t19_num_keys; i++) { - if (pdata->t19_keymap[i] == KEY_RESERVED) + for (i = 0; i < data->t19_num_keys; i++) { + if (data->t19_keymap[i] == KEY_RESERVED) continue; /* Active-low switch */ - input_report_key(input, pdata->t19_keymap[i], + input_report_key(input, data->t19_keymap[i], !(message[1] & BIT(i))); } } @@ -761,7 +767,7 @@ static void mxt_input_button(struct mxt_data *data, u8 *message) static void mxt_input_sync(struct mxt_data *data) { input_mt_report_pointer_emulation(data->input_dev, - data->pdata->t19_num_keys); + data->t19_num_keys); input_sync(data->input_dev); } @@ -1861,7 +1867,6 @@ static void mxt_input_close(struct input_dev *dev); static void mxt_set_up_as_touchpad(struct input_dev *input_dev, struct mxt_data *data) { - const struct mxt_platform_data *pdata = data->pdata; int i; input_dev->name = "Atmel maXTouch Touchpad"; @@ -1875,15 +1880,14 @@ static void mxt_set_up_as_touchpad(struct input_dev *input_dev, input_abs_set_res(input_dev, ABS_MT_POSITION_Y, MXT_PIXELS_PER_MM); - for (i = 0; i < pdata->t19_num_keys; i++) - if (pdata->t19_keymap[i] != KEY_RESERVED) + for (i = 0; i < data->t19_num_keys; i++) + if (data->t19_keymap[i] != KEY_RESERVED) input_set_capability(input_dev, EV_KEY, - pdata->t19_keymap[i]); + data->t19_keymap[i]); } static int mxt_initialize_input_device(struct mxt_data *data) { - const struct mxt_platform_data *pdata = data->pdata; struct device *dev = &data->client->dev; struct input_dev *input_dev; int error; @@ -1949,7 +1953,7 @@ static int mxt_initialize_input_device(struct mxt_data *data) } /* If device has buttons we assume it is a touchpad */ - if (pdata->t19_num_keys) { + if (data->t19_num_keys) { mxt_set_up_as_touchpad(input_dev, data); mt_flags |= INPUT_MT_POINTER; } else { @@ -2923,51 +2927,42 @@ static void mxt_input_close(struct input_dev *dev) mxt_stop(data); } -static const struct mxt_platform_data * -mxt_parse_device_properties(struct i2c_client *client) +static int mxt_parse_device_properties(struct mxt_data *data) { static const char keymap_property[] = "linux,gpio-keymap"; - struct mxt_platform_data *pdata; + struct device *dev = &data->client->dev; u32 *keymap; int n_keys; int error; - pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); - if (!pdata) - return ERR_PTR(-ENOMEM); - - if (device_property_present(&client->dev, keymap_property)) { - n_keys = device_property_read_u32_array(&client->dev, - keymap_property, + if (device_property_present(dev, keymap_property)) { + n_keys = device_property_read_u32_array(dev, keymap_property, NULL, 0); if (n_keys <= 0) { error = n_keys < 0 ? n_keys : -EINVAL; - dev_err(&client->dev, - "invalid/malformed '%s' property: %d\n", + dev_err(dev, "invalid/malformed '%s' property: %d\n", keymap_property, error); - return ERR_PTR(error); + return error; } - keymap = devm_kmalloc_array(&client->dev, n_keys, sizeof(u32), + keymap = devm_kmalloc_array(dev, n_keys, sizeof(*keymap), GFP_KERNEL); if (!keymap) - return ERR_PTR(-ENOMEM); + return -ENOMEM; - error = device_property_read_u32_array(&client->dev, - keymap_property, + error = device_property_read_u32_array(dev, keymap_property, keymap, n_keys); if (error) { - dev_err(&client->dev, - "failed to parse '%s' property: %d\n", + dev_err(dev, "failed to parse '%s' property: %d\n", keymap_property, error); - return ERR_PTR(error); + return error; } - pdata->t19_keymap = keymap; - pdata->t19_num_keys = n_keys; + data->t19_keymap = keymap; + data->t19_num_keys = n_keys; } - return pdata; + return 0; } #ifdef CONFIG_ACPI @@ -3050,25 +3045,12 @@ static const struct dmi_system_id mxt_dmi_table[] = { { } }; -static int mxt_acpi_probe(struct i2c_client *client) +static int mxt_prepare_acpi_properties(struct i2c_client *client) { struct acpi_device *adev; const struct dmi_system_id *system_id; const struct mxt_acpi_platform_data *acpi_pdata; - /* - * Ignore ACPI devices representing bootloader mode. - * - * This is a bit of a hack: Google Chromebook BIOS creates ACPI - * devices for both application and bootloader modes, but we are - * interested in application mode only (if device is in bootloader - * mode we'll end up switching into application anyway). So far - * application mode addresses were all above 0x40, so we'll use it - * as a threshold. - */ - if (client->addr < 0x40) - return -ENXIO; - adev = ACPI_COMPANION(&client->dev); if (!adev) return -ENOENT; @@ -3104,24 +3086,12 @@ static int mxt_acpi_probe(struct i2c_client *client) return 0; } #else -static int mxt_acpi_probe(struct i2c_client *client) +static int mxt_prepare_acpi_properties(struct i2c_client *client) { return -ENOENT; } #endif -static const struct mxt_platform_data * -mxt_get_platform_data(struct i2c_client *client) -{ - const struct mxt_platform_data *pdata; - - pdata = dev_get_platdata(&client->dev); - if (pdata) - return pdata; - - return mxt_parse_device_properties(client); -} - static const struct dmi_system_id chromebook_T9_suspend_dmi[] = { { .matches = { @@ -3140,16 +3110,20 @@ static const struct dmi_system_id chromebook_T9_suspend_dmi[] = { static int mxt_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct mxt_data *data; - const struct mxt_platform_data *pdata; int error; - error = mxt_acpi_probe(client); - if (error && error != -ENOENT) - return error; - - pdata = mxt_get_platform_data(client); - if (IS_ERR(pdata)) - return PTR_ERR(pdata); + /* + * Ignore ACPI devices representing bootloader mode. + * + * This is a bit of a hack: Google Chromebook BIOS creates ACPI + * devices for both application and bootloader modes, but we are + * interested in application mode only (if device is in bootloader + * mode we'll end up switching into application anyway). So far + * application mode addresses were all above 0x40, so we'll use it + * as a threshold. + */ + if (ACPI_COMPANION(&client->dev) && client->addr < 0x40) + return -ENXIO; data = devm_kzalloc(&client->dev, sizeof(struct mxt_data), GFP_KERNEL); if (!data) @@ -3159,7 +3133,6 @@ static int mxt_probe(struct i2c_client *client, const struct i2c_device_id *id) client->adapter->nr, client->addr); data->client = client; - data->pdata = pdata; data->irq = client->irq; i2c_set_clientdata(client, data); @@ -3170,6 +3143,14 @@ static int mxt_probe(struct i2c_client *client, const struct i2c_device_id *id) data->suspend_mode = dmi_check_system(chromebook_T9_suspend_dmi) ? MXT_SUSPEND_T9_CTRL : MXT_SUSPEND_DEEP_SLEEP; + error = mxt_prepare_acpi_properties(client); + if (error && error != -ENOENT) + return error; + + error = mxt_parse_device_properties(data); + if (error) + return error; + data->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(data->reset_gpio)) { @@ -3179,8 +3160,7 @@ static int mxt_probe(struct i2c_client *client, const struct i2c_device_id *id) } error = devm_request_threaded_irq(&client->dev, client->irq, - NULL, mxt_interrupt, - pdata->irqflags | IRQF_ONESHOT, + NULL, mxt_interrupt, IRQF_ONESHOT, client->name, data); if (error) { dev_err(&client->dev, "Failed to register interrupt\n"); @@ -3300,7 +3280,7 @@ MODULE_DEVICE_TABLE(i2c, mxt_id); static struct i2c_driver mxt_driver = { .driver = { .name = "atmel_mxt_ts", - .of_match_table = of_match_ptr(mxt_of_match), + .of_match_table = mxt_of_match, .acpi_match_table = ACPI_PTR(mxt_acpi_id), .pm = &mxt_pm_ops, }, diff --git a/include/linux/platform_data/atmel_mxt_ts.h b/include/linux/platform_data/atmel_mxt_ts.h deleted file mode 100644 index 695035a8d7fb..000000000000 --- a/include/linux/platform_data/atmel_mxt_ts.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Atmel maXTouch Touchscreen driver - * - * Copyright (C) 2010 Samsung Electronics Co.Ltd - * Author: Joonyoung Shim - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __LINUX_PLATFORM_DATA_ATMEL_MXT_TS_H -#define __LINUX_PLATFORM_DATA_ATMEL_MXT_TS_H - -#include - -enum mxt_suspend_mode { - MXT_SUSPEND_DEEP_SLEEP = 0, - MXT_SUSPEND_T9_CTRL = 1, -}; - -/* The platform data for the Atmel maXTouch touchscreen driver */ -struct mxt_platform_data { - unsigned long irqflags; - u8 t19_num_keys; - const unsigned int *t19_keymap; - enum mxt_suspend_mode suspend_mode; -}; - -#endif /* __LINUX_PLATFORM_DATA_ATMEL_MXT_TS_H */ -- cgit v1.2.3