From 0475680b5c2ef4bbdc3af1f6cfd014ea08c8d981 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 19 Dec 2013 15:54:58 +0000 Subject: ARM: ux500: Don't use enums for MSP IDs - for easy DT conversion Signed-off-by: Lee Jones Acked-by: Linus Walleij Signed-off-by: Mark Brown --- include/linux/platform_data/asoc-ux500-msp.h | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'include/linux') diff --git a/include/linux/platform_data/asoc-ux500-msp.h b/include/linux/platform_data/asoc-ux500-msp.h index 9991aea3d577..2f34bb98fe2a 100644 --- a/include/linux/platform_data/asoc-ux500-msp.h +++ b/include/linux/platform_data/asoc-ux500-msp.h @@ -10,16 +10,9 @@ #include -enum msp_i2s_id { - MSP_I2S_0 = 0, - MSP_I2S_1, - MSP_I2S_2, - MSP_I2S_3, -}; - /* Platform data structure for a MSP I2S-device */ struct msp_i2s_platform_data { - enum msp_i2s_id id; + int id; struct stedma40_chan_cfg *msp_i2s_dma_rx; struct stedma40_chan_cfg *msp_i2s_dma_tx; }; -- cgit v1.2.3 From 3def927ea8c0a1983aa9f1499645efc53e005bb6 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 3 Jan 2014 15:27:47 +0200 Subject: mfd: twl-core: API to set the regcache bypass for a given regmap in twl If the regcache is enabled on the regmap module drivers might need to access to HW register(s) in certain cases in cache bypass mode. As an example of this is the audio block's ANAMICL register. In normal operation the content can be cached but during initialization one bit from the register need to be monitored. With the twl_set_regcache_bypass() the client driver can switch regcache bypass on and off when it is needed so we can utilize the regcache for more registers. Signed-off-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Lee Jones --- drivers/mfd/twl-core.c | 21 +++++++++++++++++++++ include/linux/i2c/twl.h | 3 +++ 2 files changed, 24 insertions(+) (limited to 'include/linux') diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c index c91cb4367b9b..f0abca79ff34 100644 --- a/drivers/mfd/twl-core.c +++ b/drivers/mfd/twl-core.c @@ -383,6 +383,27 @@ int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes) } EXPORT_SYMBOL(twl_i2c_read); +/** + * twl_regcache_bypass - Configure the regcache bypass for the regmap associated + * with the module + * @mod_no: module number + * @enable: Regcache bypass state + * + * Returns 0 else failure. + */ +int twl_set_regcache_bypass(u8 mod_no, bool enable) +{ + struct regmap *regmap = twl_get_regmap(mod_no); + + if (!regmap) + return -EPERM; + + regcache_cache_bypass(regmap, enable); + + return 0; +} +EXPORT_SYMBOL(twl_set_regcache_bypass); + /*----------------------------------------------------------------------*/ /** diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index 673a3ce67f31..a09da0910339 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -175,6 +175,9 @@ static inline int twl_class_is_ ##class(void) \ TWL_CLASS_IS(4030, TWL4030_CLASS_ID) TWL_CLASS_IS(6030, TWL6030_CLASS_ID) +/* Set the regcache bypass for the regmap associated with the nodule */ +int twl_set_regcache_bypass(u8 mod_no, bool enable); + /* * Read and write several 8-bit registers at once. */ -- cgit v1.2.3 From 7bfbdfea576e3ae109fa182519b6f004c6024952 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 3 Jan 2014 15:27:50 +0200 Subject: ASoC: twl4030: Remove check defaults functionality No need to keep the check defaults functionality anymore. Signed-off-by: Peter Ujfalusi Signed-off-by: Mark Brown --- include/linux/i2c/twl.h | 1 - sound/soc/codecs/twl4030.c | 23 ----------------------- 2 files changed, 24 deletions(-) (limited to 'include/linux') diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index a09da0910339..2937a9472b94 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -670,7 +670,6 @@ struct twl4030_codec_data { unsigned int digimic_delay; /* in ms */ unsigned int ramp_delay_value; unsigned int offset_cncl_path; - unsigned int check_defaults:1; unsigned int reset_registers:1; unsigned int hs_extmute:1; int hs_extmute_gpio; diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index 419108ae31de..7b732ab70d2c 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -268,25 +268,6 @@ static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) udelay(10); } -static inline void twl4030_check_defaults(struct snd_soc_codec *codec) -{ - int i, difference = 0; - u8 val; - - dev_dbg(codec->dev, "Checking TWL audio default configuration\n"); - for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) { - twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i); - if (val != twl4030_reg[i]) { - difference++; - dev_dbg(codec->dev, - "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n", - i, val, twl4030_reg[i]); - } - } - dev_dbg(codec->dev, "Found %d non-matching registers. %s\n", - difference, difference ? "Not OK" : "OK"); -} - static inline void twl4030_reset_registers(struct snd_soc_codec *codec) { int i; @@ -378,10 +359,6 @@ static void twl4030_init_chip(struct snd_soc_codec *codec) } } - /* Check defaults, if instructed before anything else */ - if (pdata && pdata->check_defaults) - twl4030_check_defaults(codec); - /* Reset registers, if no setup data or if instructed to do so */ if (!pdata || (pdata && pdata->reset_registers)) twl4030_reset_registers(codec); -- cgit v1.2.3 From 0dc41562a44c9e1012bb810c2a84e81c425867b0 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 3 Jan 2014 15:27:51 +0200 Subject: ASoC: twl4030: Remove reset registers functionality The register states now tracked by the regmap implementation in the core which makes the reset registers functionality 'redundant' since we know the state of the registers now all the time. Signed-off-by: Peter Ujfalusi Signed-off-by: Mark Brown --- include/linux/i2c/twl.h | 1 - sound/soc/codecs/twl4030.c | 17 ----------------- 2 files changed, 18 deletions(-) (limited to 'include/linux') diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h index 2937a9472b94..ade1c06d4ceb 100644 --- a/include/linux/i2c/twl.h +++ b/include/linux/i2c/twl.h @@ -670,7 +670,6 @@ struct twl4030_codec_data { unsigned int digimic_delay; /* in ms */ unsigned int ramp_delay_value; unsigned int offset_cncl_path; - unsigned int reset_registers:1; unsigned int hs_extmute:1; int hs_extmute_gpio; }; diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index 7b732ab70d2c..ab2f22299db2 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -268,17 +268,6 @@ static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) udelay(10); } -static inline void twl4030_reset_registers(struct snd_soc_codec *codec) -{ - int i; - - /* set all audio section registers to reasonable defaults */ - for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++) - if (i != TWL4030_REG_APLL_CTL) - twl4030_write(codec, i, twl4030_reg[i]); - -} - static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata, struct device_node *node) { @@ -359,10 +348,6 @@ static void twl4030_init_chip(struct snd_soc_codec *codec) } } - /* Reset registers, if no setup data or if instructed to do so */ - if (!pdata || (pdata && pdata->reset_registers)) - twl4030_reset_registers(codec); - /* Refresh APLL_CTL register from HW */ twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, TWL4030_REG_APLL_CTL); @@ -2293,8 +2278,6 @@ static int twl4030_soc_remove(struct snd_soc_codec *codec) struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); struct twl4030_codec_data *pdata = twl4030->pdata; - /* Reset registers to their chip default before leaving */ - twl4030_reset_registers(codec); twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio)) -- cgit v1.2.3 From 08e2d592582e6b780bd925efcdb4971bf173f39a Mon Sep 17 00:00:00 2001 From: Charles Keepax Date: Thu, 9 Jan 2014 14:29:24 +0000 Subject: mfd: wm5110: Add registers for headphone short circuit control Add the registers necessary to enable/disable the headphone short circuit protection. Signed-off-by: Charles Keepax Acked-by: Lee Jones Signed-off-by: Mark Brown --- drivers/mfd/wm5110-tables.c | 6 ++++++ include/linux/mfd/arizona/registers.h | 27 +++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) (limited to 'include/linux') diff --git a/drivers/mfd/wm5110-tables.c b/drivers/mfd/wm5110-tables.c index abd6713de7b0..4a4432eb499c 100644 --- a/drivers/mfd/wm5110-tables.c +++ b/drivers/mfd/wm5110-tables.c @@ -610,6 +610,9 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */ { 0x00000492, 0x0069 }, /* R1170 - PDM SPK2 CTRL 1 */ { 0x00000493, 0x0000 }, /* R1171 - PDM SPK2 CTRL 2 */ + { 0x000004A0, 0x3480 }, /* R1184 - HP1 Short Circuit Ctrl */ + { 0x000004A1, 0x3480 }, /* R1185 - HP2 Short Circuit Ctrl */ + { 0x000004A2, 0x3480 }, /* R1186 - HP3 Short Circuit Ctrl */ { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */ { 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */ { 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */ @@ -1639,6 +1642,9 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_PDM_SPK1_CTRL_2: case ARIZONA_PDM_SPK2_CTRL_1: case ARIZONA_PDM_SPK2_CTRL_2: + case ARIZONA_HP1_SHORT_CIRCUIT_CTRL: + case ARIZONA_HP2_SHORT_CIRCUIT_CTRL: + case ARIZONA_HP3_SHORT_CIRCUIT_CTRL: case ARIZONA_AIF1_BCLK_CTRL: case ARIZONA_AIF1_TX_PIN_CTRL: case ARIZONA_AIF1_RX_PIN_CTRL: diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h index 22916c0f1ca4..19883aeb1ac8 100644 --- a/include/linux/mfd/arizona/registers.h +++ b/include/linux/mfd/arizona/registers.h @@ -226,6 +226,9 @@ #define ARIZONA_PDM_SPK1_CTRL_2 0x491 #define ARIZONA_PDM_SPK2_CTRL_1 0x492 #define ARIZONA_PDM_SPK2_CTRL_2 0x493 +#define ARIZONA_HP1_SHORT_CIRCUIT_CTRL 0x4A0 +#define ARIZONA_HP2_SHORT_CIRCUIT_CTRL 0x4A1 +#define ARIZONA_HP3_SHORT_CIRCUIT_CTRL 0x4A2 #define ARIZONA_SPK_CTRL_2 0x4B5 #define ARIZONA_SPK_CTRL_3 0x4B6 #define ARIZONA_DAC_COMP_1 0x4DC @@ -3332,6 +3335,30 @@ #define ARIZONA_SPK2_FMT_SHIFT 0 /* SPK2_FMT */ #define ARIZONA_SPK2_FMT_WIDTH 1 /* SPK2_FMT */ +/* + * R1184 (0x4A0) - HP1 Short Circuit Ctrl + */ +#define ARIZONA_HP1_SC_ENA 0x1000 /* HP1_SC_ENA */ +#define ARIZONA_HP1_SC_ENA_MASK 0x1000 /* HP1_SC_ENA */ +#define ARIZONA_HP1_SC_ENA_SHIFT 12 /* HP1_SC_ENA */ +#define ARIZONA_HP1_SC_ENA_WIDTH 1 /* HP1_SC_ENA */ + +/* + * R1185 (0x4A1) - HP2 Short Circuit Ctrl + */ +#define ARIZONA_HP2_SC_ENA 0x1000 /* HP2_SC_ENA */ +#define ARIZONA_HP2_SC_ENA_MASK 0x1000 /* HP2_SC_ENA */ +#define ARIZONA_HP2_SC_ENA_SHIFT 12 /* HP2_SC_ENA */ +#define ARIZONA_HP2_SC_ENA_WIDTH 1 /* HP2_SC_ENA */ + +/* + * R1186 (0x4A2) - HP3 Short Circuit Ctrl + */ +#define ARIZONA_HP3_SC_ENA 0x1000 /* HP3_SC_ENA */ +#define ARIZONA_HP3_SC_ENA_MASK 0x1000 /* HP3_SC_ENA */ +#define ARIZONA_HP3_SC_ENA_SHIFT 12 /* HP3_SC_ENA */ +#define ARIZONA_HP3_SC_ENA_WIDTH 1 /* HP3_SC_ENA */ + /* * R1244 (0x4DC) - DAC comp 1 */ -- cgit v1.2.3 From 507205632dd12636cfe4af4322dace263dca0c21 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 11 Jan 2014 14:02:16 +0100 Subject: dma: Indicate residue granularity in dma_slave_caps This patch adds a new field to the dma_slave_caps struct which indicates the granularity with which the driver is able to update the residue field of the dma_tx_state struct. Making this information available to dmaengine users allows them to make better decisions on how to operate. E.g. for audio certain features like wakeup less operation or timer based scheduling only make sense and work correctly if the reported residue is fine-grained enough. Right now four different levels of granularity are supported: * DESCRIPTOR: The DMA channel is only able to tell whether a descriptor has been completed or not, which means residue reporting is not supported by this channel. The residue field of the dma_tx_state field will always be 0. * SEGMENT: The DMA channel updates the residue field after each successfully completed segment of the transfer (For cyclic transfers this is after each period). This is typically implemented by having the hardware generate an interrupt after each transferred segment and then the drivers updates the outstanding residue by the size of the segment. Another possibility is if the hardware supports SG and the segment descriptor has a field which gets set after the segment has been completed. The driver then counts the number of segments without the flag set to compute the residue. * BURST: The DMA channel updates the residue field after each transferred burst. This is typically only supported if the hardware has a progress register of some sort (E.g. a register with the current read/write address or a register with the amount of bursts/beats/bytes that have been transferred or still need to be transferred). Signed-off-by: Lars-Peter Clausen Acked-by: Vinod Koul Signed-off-by: Mark Brown --- include/linux/dmaengine.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'include/linux') diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index ed92b30a02fd..ba5f96db0754 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -364,6 +364,32 @@ struct dma_slave_config { unsigned int slave_id; }; +/** + * enum dma_residue_granularity - Granularity of the reported transfer residue + * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The + * DMA channel is only able to tell whether a descriptor has been completed or + * not, which means residue reporting is not supported by this channel. The + * residue field of the dma_tx_state field will always be 0. + * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully + * completed segment of the transfer (For cyclic transfers this is after each + * period). This is typically implemented by having the hardware generate an + * interrupt after each transferred segment and then the drivers updates the + * outstanding residue by the size of the segment. Another possibility is if + * the hardware supports scatter-gather and the segment descriptor has a field + * which gets set after the segment has been completed. The driver then counts + * the number of segments without the flag set to compute the residue. + * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred + * burst. This is typically only supported if the hardware has a progress + * register of some sort (E.g. a register with the current read/write address + * or a register with the amount of bursts/beats/bytes that have been + * transferred or still need to be transferred). + */ +enum dma_residue_granularity { + DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0, + DMA_RESIDUE_GRANULARITY_SEGMENT = 1, + DMA_RESIDUE_GRANULARITY_BURST = 2, +}; + /* struct dma_slave_caps - expose capabilities of a slave channel only * * @src_addr_widths: bit mask of src addr widths the channel supports @@ -374,6 +400,7 @@ struct dma_slave_config { * should be checked by controller as well * @cmd_pause: true, if pause and thereby resume is supported * @cmd_terminate: true, if terminate cmd is supported + * @residue_granularity: granularity of the reported transfer residue */ struct dma_slave_caps { u32 src_addr_widths; @@ -381,6 +408,7 @@ struct dma_slave_caps { u32 directions; bool cmd_pause; bool cmd_terminate; + enum dma_residue_granularity residue_granularity; }; static inline const char *dma_chan_name(struct dma_chan *chan) -- cgit v1.2.3