From da82250752708171b4d236c319a4e3a15f0efc70 Mon Sep 17 00:00:00 2001 From: Robin Holt Date: Fri, 25 Jun 2004 04:12:05 -0700 Subject: [PATCH] ia64: Fixups for the SN2 Block Transfer Engine The attached patch contains some cleanups to the bte code and introduces the ability to excercise bte interfaces on other nodes. This is an SGI Altix specific piece of hardware. Signed-off by: Robin Holt Signed-off by: Jesse Barnes Signed-off-by: David Mosberger --- include/asm-ia64/sn/bte.h | 49 ++++++++++++++++++++++------------------------- include/asm-ia64/sn/pda.h | 2 -- 2 files changed, 23 insertions(+), 28 deletions(-) (limited to 'include') diff --git a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h index 538385a21fb7..1b643d1e0820 100644 --- a/include/asm-ia64/sn/bte.h +++ b/include/asm-ia64/sn/bte.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2000-2003 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (c) 2000-2004 Silicon Graphics, Inc. All Rights Reserved. */ @@ -48,35 +48,31 @@ #define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE) /* Use a reserved bit to let the caller specify a wait for any BTE */ #define BTE_WACQUIRE (0x4000) +/* Use the BTE on the node with the destination memory */ +#define BTE_USE_DEST (BTE_WACQUIRE << 1) +/* Use any available BTE interface on any node for the transfer */ +#define BTE_USE_ANY (BTE_USE_DEST << 1) /* macro to force the IBCT0 value valid */ #define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE)) - -/* - * Handle locking of the bte interfaces. - * - * All transfers spinlock the interface before setting up the SHUB - * registers. Sync transfers hold the lock until all processing is - * complete. Async transfers release the lock as soon as the transfer - * is initiated. - * - * To determine if an interface is available, we must check both the - * busy bit and the spinlock for that interface. - */ -#define BTE_LOCK_IF_AVAIL(_x) (\ - (*pda->cpu_bte_if[_x]->most_rcnt_na & (IBLS_BUSY | IBLS_ERROR)) && \ - (!(spin_trylock(&(pda->cpu_bte_if[_x]->spinlock)))) \ - ) +#define BTE_ACTIVE (IBLS_BUSY | IBLS_ERROR) /* * Some macros to simplify reading. * Start with macros to locate the BTE control registers. */ -#define BTEREG_LNSTAT_ADDR ((u64 *)(bte->bte_base_addr)) -#define BTEREG_SRC_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_SRC)) -#define BTEREG_DEST_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_DEST)) -#define BTEREG_CTRL_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_CTRL)) -#define BTEREG_NOTIF_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_NOTIFY)) +#define BTE_LNSTAT_LOAD(_bte) \ + HUB_L(_bte->bte_base_addr) +#define BTE_LNSTAT_STORE(_bte, _x) \ + HUB_S(_bte->bte_base_addr, (_x)) +#define BTE_SRC_STORE(_bte, _x) \ + HUB_S(_bte->bte_base_addr + (BTEOFF_SRC/8), (_x)) +#define BTE_DEST_STORE(_bte, _x) \ + HUB_S(_bte->bte_base_addr + (BTEOFF_DEST/8), (_x)) +#define BTE_CTRL_STORE(_bte, _x) \ + HUB_S(_bte->bte_base_addr + (BTEOFF_CTRL/8), (_x)) +#define BTE_NOTIF_STORE(_bte, _x) \ + HUB_S(_bte->bte_base_addr + (BTEOFF_NOTIFY/8), (_x)) /* Possible results from bte_copy and bte_unaligned_copy */ @@ -110,16 +106,15 @@ typedef enum { * to work with a BTE. */ struct bteinfo_s { - u64 volatile notify ____cacheline_aligned; - char *bte_base_addr ____cacheline_aligned; + volatile u64 notify ____cacheline_aligned; + u64 *bte_base_addr ____cacheline_aligned; spinlock_t spinlock; cnodeid_t bte_cnode; /* cnode */ int bte_error_count; /* Number of errors encountered */ int bte_num; /* 0 --> BTE0, 1 --> BTE1 */ int cleanup_active; /* Interface is locked for cleanup */ volatile bte_result_t bh_error; /* error while processing */ - u64 volatile *most_rcnt_na; - void *scratch_buf; /* Node local scratch buffer */ + volatile u64 *most_rcnt_na; }; @@ -130,6 +125,8 @@ extern bte_result_t bte_copy(u64, u64, u64, u64, void *); extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64); extern void bte_error_handler(unsigned long); +#define bte_zero(dest, len, mode, notification) \ + bte_copy(0, dest, len, ((mode) | BTE_ZERO_FILL), notification) /* * The following is the prefered way of calling bte_unaligned_copy diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h index 20e9b5775435..fa472c3f983e 100644 --- a/include/asm-ia64/sn/pda.h +++ b/include/asm-ia64/sn/pda.h @@ -49,8 +49,6 @@ typedef struct pda_s { volatile unsigned long *pio_shub_war_cam_addr; volatile unsigned long *mem_write_status_addr; - struct bteinfo_s *cpu_bte_if[BTES_PER_NODE]; /* cpu interface order */ - unsigned long sn_soft_irr[4]; unsigned long sn_in_service_ivecs[4]; short cnodeid_to_nasid_table[MAX_NUMNODES]; -- cgit v1.2.3 From 2b5982c59961cd969e57a97a87b6be18bab44f10 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 25 Jun 2004 04:25:50 -0700 Subject: [PATCH] ia64: minor IOSAPIC cleanup Introduce iosapic_{read,write,eoi} to hide the IOSAPIC REG_SELECT stuff. i386 and x86_64 already do this for io_apic_{read,write}. Signed-off-by: Bjorn Helgaas Signed-off-by: David Mosberger --- arch/ia64/kernel/iosapic.c | 25 ++++++++----------------- include/asm-ia64/iosapic.h | 21 ++++++++++++++++++--- 2 files changed, 26 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c index 4638a2dd845d..21dafa720f25 100644 --- a/arch/ia64/kernel/iosapic.c +++ b/arch/ia64/kernel/iosapic.c @@ -217,10 +217,8 @@ set_rte (unsigned int vector, unsigned int dest, int mask) spin_lock_irqsave(&iosapic_lock, flags); { - writel(IOSAPIC_RTE_HIGH(rte_index), addr + IOSAPIC_REG_SELECT); - writel(high32, addr + IOSAPIC_WINDOW); - writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT); - writel(low32, addr + IOSAPIC_WINDOW); + iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32); + iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); iosapic_intr_info[vector].low32 = low32; } spin_unlock_irqrestore(&iosapic_lock, flags); @@ -249,12 +247,9 @@ mask_irq (unsigned int irq) spin_lock_irqsave(&iosapic_lock, flags); { - writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT); - /* set only the mask bit */ low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK; - - writel(low32, addr + IOSAPIC_WINDOW); + iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); } spin_unlock_irqrestore(&iosapic_lock, flags); } @@ -275,9 +270,8 @@ unmask_irq (unsigned int irq) spin_lock_irqsave(&iosapic_lock, flags); { - writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT); low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK; - writel(low32, addr + IOSAPIC_WINDOW); + iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); } spin_unlock_irqrestore(&iosapic_lock, flags); } @@ -325,10 +319,8 @@ iosapic_set_affinity (unsigned int irq, cpumask_t mask) low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT); iosapic_intr_info[vec].low32 = low32; - writel(IOSAPIC_RTE_HIGH(rte_index), addr + IOSAPIC_REG_SELECT); - writel(high32, addr + IOSAPIC_WINDOW); - writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT); - writel(low32, addr + IOSAPIC_WINDOW); + iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32); + iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); } spin_unlock_irqrestore(&iosapic_lock, flags); #endif @@ -351,7 +343,7 @@ iosapic_end_level_irq (unsigned int irq) ia64_vector vec = irq_to_vector(irq); move_irq(irq); - writel(vec, iosapic_intr_info[vec].addr + IOSAPIC_EOI); + iosapic_eoi(iosapic_intr_info[vec].addr, vec); } #define iosapic_shutdown_level_irq mask_irq @@ -428,8 +420,7 @@ iosapic_version (char *addr) * unsigned int reserved2 : 8; * } */ - writel(IOSAPIC_VERSION, addr + IOSAPIC_REG_SELECT); - return readl(IOSAPIC_WINDOW + addr); + return iosapic_read(addr, IOSAPIC_VERSION); } /* diff --git a/include/asm-ia64/iosapic.h b/include/asm-ia64/iosapic.h index d5bda84aeacc..cf40c9ef2493 100644 --- a/include/asm-ia64/iosapic.h +++ b/include/asm-ia64/iosapic.h @@ -1,13 +1,11 @@ #ifndef __ASM_IA64_IOSAPIC_H #define __ASM_IA64_IOSAPIC_H -#define IOSAPIC_DEFAULT_ADDR 0xFEC00000 - #define IOSAPIC_REG_SELECT 0x0 #define IOSAPIC_WINDOW 0x10 #define IOSAPIC_EOI 0x40 -#define IOSAPIC_VERSION 0x1 +#define IOSAPIC_VERSION 0x1 /* * Redirection table entry @@ -55,6 +53,23 @@ #define NR_IOSAPICS 256 +static inline unsigned int iosapic_read(char *iosapic, unsigned int reg) +{ + writel(reg, iosapic + IOSAPIC_REG_SELECT); + return readl(iosapic + IOSAPIC_WINDOW); +} + +static inline void iosapic_write(char *iosapic, unsigned int reg, u32 val) +{ + writel(reg, iosapic + IOSAPIC_REG_SELECT); + writel(val, iosapic + IOSAPIC_WINDOW); +} + +static inline void iosapic_eoi(char *iosapic, u32 vector) +{ + writel(vector, iosapic + IOSAPIC_EOI); +} + extern void __init iosapic_system_init (int pcat_compat); extern void __init iosapic_init (unsigned long address, unsigned int gsi_base); -- cgit v1.2.3 From 3ade83bef378f485816e251ba3f937ea3c2c596c Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 28 Jun 2004 22:57:11 -0700 Subject: [PATCH] ia64: define cpu_logical_id() always Define cpu_logical_id() even when !SMP. I added uses of this in some iosapic printk's, which broke the UP build. Signed-off-by: David Mosberger --- include/asm-ia64/smp.h | 4 ++++ include/asm-ia64/sn/sn_cpuid.h | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h index f12f939e3c00..513c704d1306 100644 --- a/include/asm-ia64/smp.h +++ b/include/asm-ia64/smp.h @@ -123,5 +123,9 @@ extern void smp_send_reschedule (int cpu); extern void lock_ipi_calllock(void); extern void unlock_ipi_calllock(void); +#else + +#define cpu_logical_id(cpuid) 0 + #endif /* CONFIG_SMP */ #endif /* _ASM_IA64_SMP_H */ diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h index 0c7cce652368..6f1128f1e895 100644 --- a/include/asm-ia64/sn/sn_cpuid.h +++ b/include/asm-ia64/sn/sn_cpuid.h @@ -84,7 +84,6 @@ */ #ifndef CONFIG_SMP -#define cpu_logical_id(cpu) 0 #define cpu_physical_id(cpuid) ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff) #endif -- cgit v1.2.3