From 8db06ceea34d15300e6163fa36ed3c71748175ee Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 7 Sep 2004 16:24:51 +0100 Subject: [ARM] Add cache_is_xxxx() functions for cache type identification. Add cache_is_xxxx() functions so we can easily identify the cache type of the CPU we're running on. --- include/asm-arm/system.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'include') diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index d500cc940f81..146a814e53a2 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -55,6 +55,38 @@ __val; \ }) +#define __cacheid_present(val) (val != read_cpuid(CPUID_ID)) +#define __cacheid_vivt(val) ((val & (15 << 25)) != (14 << 25)) +#define __cacheid_vipt(val) ((val & (15 << 25)) == (14 << 25)) +#define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25)) +#define __cacheid_vipt_aliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23)) + +#define cache_is_vivt() \ + ({ \ + unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ + (!__cacheid_present(__val)) || __cacheid_vivt(__val); \ + }) + +#define cache_is_vipt() \ + ({ \ + unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ + __cacheid_present(__val) && __cacheid_vipt(__val); \ + }) + +#define cache_is_vipt_nonaliasing() \ + ({ \ + unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ + __cacheid_present(__val) && \ + __cacheid_vipt_nonaliasing(__val); \ + }) + +#define cache_is_vipt_aliasing() \ + ({ \ + unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ + __cacheid_present(__val) && \ + __cacheid_vipt_aliasing(__val); \ + }) + /* * This is used to ensure the compiler did actually allocate the register we * asked it for some inline assembly sequences. Apparently we can't trust -- cgit v1.2.3