From bf4dae5ce1b95a5932e43036edcf3f1b324758c6 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 7 Aug 2013 22:21:57 +0200 Subject: pinctrl: nomadik: delete ancient pin control API The pin control subsystem was created to do away with custom pin control APIs such as this one. It was kept for backward-compatibility but is completely unused in the current kernel, so let's delete it. Signed-off-by: Linus Walleij --- include/linux/platform_data/pinctrl-nomadik.h | 24 ------------------------ 1 file changed, 24 deletions(-) (limited to 'include') diff --git a/include/linux/platform_data/pinctrl-nomadik.h b/include/linux/platform_data/pinctrl-nomadik.h index f73b2f0c55b7..abf5bed84df3 100644 --- a/include/linux/platform_data/pinctrl-nomadik.h +++ b/include/linux/platform_data/pinctrl-nomadik.h @@ -226,30 +226,6 @@ enum nmk_gpio_slpm { NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, }; -/* Older deprecated pin config API that should go away soon */ -extern int nmk_config_pin(pin_cfg_t cfg, bool sleep); -extern int nmk_config_pins(pin_cfg_t *cfgs, int num); -extern int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num); -extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode); -extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull); -#ifdef CONFIG_PINCTRL_NOMADIK -extern int nmk_gpio_set_mode(int gpio, int gpio_mode); -#else -static inline int nmk_gpio_set_mode(int gpio, int gpio_mode) -{ - return -ENODEV; -} -#endif -extern int nmk_gpio_get_mode(int gpio); - -extern void nmk_gpio_wakeups_suspend(void); -extern void nmk_gpio_wakeups_resume(void); - -extern void nmk_gpio_clocks_enable(void); -extern void nmk_gpio_clocks_disable(void); - -extern void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up); - /* * Platform data to register a block: only the initial gpio/irq number. */ -- cgit v1.2.3 From e81c8f18afc4fdd6e34d8c83814b8b5134dbb30f Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 6 Aug 2013 18:42:34 +0530 Subject: pinctrl: pinconf-generic: add generic APIs for mapping pinctrl node Add generic APIs to map the DT node and its sub node in pinconf generic driver. These APIs can be used from driver to parse the DT node who uses the pinconf generic APIs for defining their nodes. Changes from V1: - Add generic property for pins and functions in pinconf-generic. - Add APIs to map the DT and subnode. - Move common utils APIs to the pinctrl-utils from this file. - Update the binding document accordingly. Changes from V2: - Rebased the pinctrl binding doc on top of Stephen's cleanup. - Rename properties "pinctrl-pins" and "pinctrl-function" to "pins" and "function". Signed-off-by: Laxman Dewangan Reviewed-by: Stephen Warren Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 96 +++++++++++++++++++++++++++++++++ include/linux/pinctrl/pinconf-generic.h | 6 +++ 2 files changed, 102 insertions(+) (limited to 'include') diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 8594f033ac21..d9536caa9c41 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -24,6 +24,7 @@ #include #include "core.h" #include "pinconf.h" +#include "pinctrl-utils.h" #ifdef CONFIG_DEBUG_FS @@ -236,4 +237,99 @@ out: kfree(cfg); return ret; } + +int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, struct pinctrl_map **map, + unsigned *reserved_maps, unsigned *num_maps) +{ + int ret; + const char *function; + struct device *dev = pctldev->dev; + unsigned long *configs = NULL; + unsigned num_configs = 0; + unsigned reserve; + struct property *prop; + const char *group; + + ret = of_property_read_string(np, "function", &function); + if (ret < 0) { + /* EINVAL=missing, which is fine since it's optional */ + if (ret != -EINVAL) + dev_err(dev, + "could not parse property ti,function\n"); + function = NULL; + } + + ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); + if (ret < 0) { + dev_err(dev, "could not parse node property\n"); + return ret; + } + + reserve = 0; + if (function != NULL) + reserve++; + if (num_configs) + reserve++; + ret = of_property_count_strings(np, "pins"); + if (ret < 0) { + dev_err(dev, "could not parse property ti,pins\n"); + goto exit; + } + reserve *= ret; + + ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, + num_maps, reserve); + if (ret < 0) + goto exit; + + of_property_for_each_string(np, "pins", prop, group) { + if (function) { + ret = pinctrl_utils_add_map_mux(pctldev, map, + reserved_maps, num_maps, group, + function); + if (ret < 0) + goto exit; + } + + if (num_configs) { + ret = pinctrl_utils_add_map_configs(pctldev, map, + reserved_maps, num_maps, group, configs, + num_configs, PIN_MAP_TYPE_CONFIGS_PIN); + if (ret < 0) + goto exit; + } + } + ret = 0; + +exit: + kfree(configs); + return ret; +} +EXPORT_SYMBOL_GPL(pinconf_generic_dt_subnode_to_map); + +int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, struct pinctrl_map **map, + unsigned *num_maps) +{ + unsigned reserved_maps; + struct device_node *np; + int ret; + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + return 0; +} +EXPORT_SYMBOL_GPL(pinconf_generic_dt_node_to_map); + #endif diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index bf7e989abcb5..a472b93292a3 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -137,6 +137,12 @@ static inline unsigned long pinconf_to_config_packed(enum pin_config_param param return PIN_CONF_PACKED(param, argument); } +int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, struct pinctrl_map **map, + unsigned *reserved_maps, unsigned *num_maps); +int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, struct pinctrl_map **map, + unsigned *num_maps); #endif /* CONFIG_GENERIC_PINCONF */ #endif /* __LINUX_PINCTRL_PINCONF_GENERIC_H */ -- cgit v1.2.3 From 0a8d3e2412841c6b1dab1006fd5f7ab5b689db21 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 6 Aug 2013 18:42:35 +0530 Subject: pinctrl: palmas: add pincontrol driver TI Palmas series Power Management IC have multiple pins which can be configured for different functionality. This pins can be configured for different function. Also their properties like pull up/down, open drain enable/disable are configurable. Add support for pincontrol driver Palmas series device like TPS65913, TPS80036. The driver supports to be register from DT only. Changes from V1: - Add generic property for pins and functions in pinconf-generic. - Add APIs to map the DT and subnode. - Move common utils APIs to the pinctrl-utils from this file. - Update the binding document accordingly. Changes from V2: - Add ack by Lee. - Correct the binding docs. Signed-off-by: Laxman Dewangan Acked-by: Lee Jones Reviewed-by: Stephen Warren Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/pinctrl-palmas.txt | 96 ++ drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-palmas.c | 1085 ++++++++++++++++++++ include/linux/mfd/palmas.h | 35 +- 5 files changed, 1216 insertions(+), 11 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt create mode 100644 drivers/pinctrl/pinctrl-palmas.c (limited to 'include') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt new file mode 100644 index 000000000000..734d9b04d533 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt @@ -0,0 +1,96 @@ +Palmas Pincontrol bindings + +The pins of Palmas device can be set on different option and provides +the configuration for Pull UP/DOWN, open drain etc. + +Required properties: +- compatible: It must be one of following: + - "ti,palmas-pinctrl" for Palma series of the pincontrol. + - "ti,tps65913-pinctrl" for Palma series device TPS65913. + - "ti,tps80036-pinctrl" for Palma series device TPS80036. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Palmas's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +list of pins. This configuration can include the mux function to select on +those pin(s), and various pin configuration parameters, such as pull-up, +open drain. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +Optional properties: +- ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode. + Selection primary or secondary function associated to I2C2_SCL_SCE, + I2C2_SDA_SDO pin/pad for DVFS1 interface +- ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode. + Selection primary or secondary function associated to GPADC_START + and SYSEN2 pin/pad for DVFS2 interface + +This binding uses the following generic properties as defined in +pinctrl-bindings.txt: + +Required: pins +Options: function, bias-disable, bias-pull-up, bias-pull-down, + bias-pin-default, drive-open-drain. + +Note that many of these properties are only valid for certain specific pins. +See the Palmas device datasheet for complete details regarding which pins +support which functionality. + +Valid values for pin names are: + gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9, + gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, vac, powergood, + nreswarm, pwrdown, gpadc_start, reset_in, nsleep, enable1, enable2, + int. + +Valid value of function names are: + gpio, led, pwm, regen, sysen, clk32kgaudio, id, vbus_det, chrg_det, + vac, vacok, powergood, usb_psel, msecure, pwrhold, int, nreswarm, + simrsto, simrsti, low_vbat, wireless_chrg1, rcm, pwrdown, gpadc_start, + reset_in, nsleep, enable. + +There are 4 special functions: opt0, opt1, opt2 and opt3. If any of these +functions is selected then directly pins register will be written with 0, 1, 2 +or 3 respectively if it is valid for that pins or list of pins. + +Example: + palmas: tps65913 { + .... + pinctrl { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + pinctrl-names = "default"; + pinctrl-0 = <&palmas_pins_state>; + + palmas_pins_state: pinmux { + gpio0 { + pins = "gpio0"; + function = "id"; + bias-pull-up; + }; + + vac { + pins = "vac"; + function = "vacok"; + bias-pull-down; + }; + + gpio5 { + pins = "gpio5"; + function = "opt0"; + drive-open-drain = <1>; + }; + }; + }; + .... + }; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index bc830af1b23d..8542cd4a176a 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -261,6 +261,16 @@ config PINCTRL_EXYNOS5440 select PINMUX select PINCONF +config PINCTRL_PALMAS + bool "Pinctrl driver for the PALMA Series MFD devices" + depends on OF && MFD_PALMAS + select GENERIC_PINCONF + help + Palmas device supports the configuration of pins for different + functionality. This driver supports the pinmux, push-pull and + open drain configuration for the Palmas series devices like + TPS65913, TPS80036 etc. + config PINCTRL_S3C24XX bool "Samsung S3C24XX SoC pinctrl driver" depends on ARCH_S3C24XX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index bc03a6eb8255..496d9bf9e1b9 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o +obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_SIRF) += sirf/ diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c new file mode 100644 index 000000000000..2697c2efd74b --- /dev/null +++ b/drivers/pinctrl/pinctrl-palmas.c @@ -0,0 +1,1085 @@ +/* + * pinctrl-palmas.c -- TI PALMAS series pin control driver. + * + * Copyright (c) 2013, NVIDIA Corporation. + * + * Author: Laxman Dewangan + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, + * whether express or implied; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" +#include "pinconf.h" +#include "pinctrl-utils.h" + +#define PALMAS_PIN_GPIO0_ID 0 +#define PALMAS_PIN_GPIO1_VBUS_LED1_PWM1 1 +#define PALMAS_PIN_GPIO2_REGEN_LED2_PWM2 2 +#define PALMAS_PIN_GPIO3_CHRG_DET 3 +#define PALMAS_PIN_GPIO4_SYSEN1 4 +#define PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL 5 +#define PALMAS_PIN_GPIO6_SYSEN2 6 +#define PALMAS_PIN_GPIO7_MSECURE_PWRHOLD 7 +#define PALMAS_PIN_GPIO8_SIM1RSTI 8 +#define PALMAS_PIN_GPIO9_LOW_VBAT 9 +#define PALMAS_PIN_GPIO10_WIRELESS_CHRG1 10 +#define PALMAS_PIN_GPIO11_RCM 11 +#define PALMAS_PIN_GPIO12_SIM2RSTO 12 +#define PALMAS_PIN_GPIO13 13 +#define PALMAS_PIN_GPIO14 14 +#define PALMAS_PIN_GPIO15_SIM2RSTI 15 +#define PALMAS_PIN_VAC 16 +#define PALMAS_PIN_POWERGOOD_USB_PSEL 17 +#define PALMAS_PIN_NRESWARM 18 +#define PALMAS_PIN_PWRDOWN 19 +#define PALMAS_PIN_GPADC_START 20 +#define PALMAS_PIN_RESET_IN 21 +#define PALMAS_PIN_NSLEEP 22 +#define PALMAS_PIN_ENABLE1 23 +#define PALMAS_PIN_ENABLE2 24 +#define PALMAS_PIN_INT 25 +#define PALMAS_PIN_NUM (PALMAS_PIN_INT + 1) + +struct palmas_pin_function { + const char *name; + const char * const *groups; + unsigned ngroups; +}; + +struct palmas_pctrl_chip_info { + struct device *dev; + struct pinctrl_dev *pctl; + struct palmas *palmas; + int pins_current_opt[PALMAS_PIN_NUM]; + const struct palmas_pin_function *functions; + unsigned num_functions; + const struct palmas_pingroup *pin_groups; + int num_pin_groups; + const struct pinctrl_pin_desc *pins; + unsigned num_pins; +}; + +static const struct pinctrl_pin_desc palmas_pins_desc[] = { + PINCTRL_PIN(PALMAS_PIN_GPIO0_ID, "gpio0"), + PINCTRL_PIN(PALMAS_PIN_GPIO1_VBUS_LED1_PWM1, "gpio1"), + PINCTRL_PIN(PALMAS_PIN_GPIO2_REGEN_LED2_PWM2, "gpio2"), + PINCTRL_PIN(PALMAS_PIN_GPIO3_CHRG_DET, "gpio3"), + PINCTRL_PIN(PALMAS_PIN_GPIO4_SYSEN1, "gpio4"), + PINCTRL_PIN(PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL, "gpio5"), + PINCTRL_PIN(PALMAS_PIN_GPIO6_SYSEN2, "gpio6"), + PINCTRL_PIN(PALMAS_PIN_GPIO7_MSECURE_PWRHOLD, "gpio7"), + PINCTRL_PIN(PALMAS_PIN_GPIO8_SIM1RSTI, "gpio8"), + PINCTRL_PIN(PALMAS_PIN_GPIO9_LOW_VBAT, "gpio9"), + PINCTRL_PIN(PALMAS_PIN_GPIO10_WIRELESS_CHRG1, "gpio10"), + PINCTRL_PIN(PALMAS_PIN_GPIO11_RCM, "gpio11"), + PINCTRL_PIN(PALMAS_PIN_GPIO12_SIM2RSTO, "gpio12"), + PINCTRL_PIN(PALMAS_PIN_GPIO13, "gpio13"), + PINCTRL_PIN(PALMAS_PIN_GPIO14, "gpio14"), + PINCTRL_PIN(PALMAS_PIN_GPIO15_SIM2RSTI, "gpio15"), + PINCTRL_PIN(PALMAS_PIN_VAC, "vac"), + PINCTRL_PIN(PALMAS_PIN_POWERGOOD_USB_PSEL, "powergood"), + PINCTRL_PIN(PALMAS_PIN_NRESWARM, "nreswarm"), + PINCTRL_PIN(PALMAS_PIN_PWRDOWN, "pwrdown"), + PINCTRL_PIN(PALMAS_PIN_GPADC_START, "gpadc_start"), + PINCTRL_PIN(PALMAS_PIN_RESET_IN, "reset_in"), + PINCTRL_PIN(PALMAS_PIN_NSLEEP, "nsleep"), + PINCTRL_PIN(PALMAS_PIN_ENABLE1, "enable1"), + PINCTRL_PIN(PALMAS_PIN_ENABLE2, "enable2"), + PINCTRL_PIN(PALMAS_PIN_INT, "int"), +}; + +static const char * const opt0_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", + "gpio4", + "gpio5", + "gpio6", + "gpio7", + "gpio8", + "gpio9", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gpio15", + "vac", + "powergood", + "nreswarm", + "pwrdown", + "gpadc_start", + "reset_in", + "nsleep", + "enable1", + "enable2", + "int", +}; + +static const char * const opt1_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", + "gpio4", + "gpio5", + "gpio6", + "gpio7", + "gpio8", + "gpio9", + "gpio10", + "gpio11", + "gpio12", + "gpio15", + "vac", + "powergood", +}; + +static const char * const opt2_groups[] = { + "gpio1", + "gpio2", + "gpio5", + "gpio7", +}; + +static const char * const opt3_groups[] = { + "gpio1", + "gpio2", +}; + +static const char * const gpio_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", + "gpio4", + "gpio5", + "gpio6", + "gpio7", + "gpio8", + "gpio9", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gpio15", +}; + +static const char * const led_groups[] = { + "gpio1", + "gpio2", +}; + +static const char * const pwm_groups[] = { + "gpio1", + "gpio2", +}; + +static const char * const regen_groups[] = { + "gpio2", +}; + +static const char * const sysen_groups[] = { + "gpio4", + "gpio6", +}; + +static const char * const clk32kgaudio_groups[] = { + "gpio5", +}; + +static const char * const id_groups[] = { + "gpio0", +}; + +static const char * const vbus_det_groups[] = { + "gpio1", +}; + +static const char * const chrg_det_groups[] = { + "gpio3", +}; + +static const char * const vac_groups[] = { + "vac", +}; + +static const char * const vacok_groups[] = { + "vac", +}; + +static const char * const powergood_groups[] = { + "powergood", +}; + +static const char * const usb_psel_groups[] = { + "gpio5", + "powergood", +}; + +static const char * const msecure_groups[] = { + "gpio7", +}; + +static const char * const pwrhold_groups[] = { + "gpio7", +}; + +static const char * const int_groups[] = { + "int", +}; + +static const char * const nreswarm_groups[] = { + "nreswarm", +}; + +static const char * const simrsto_groups[] = { + "gpio12", +}; + +static const char * const simrsti_groups[] = { + "gpio8", + "gpio15", +}; + +static const char * const low_vbat_groups[] = { + "gpio9", +}; + +static const char * const wireless_chrg1_groups[] = { + "gpio10", +}; + +static const char * const rcm_groups[] = { + "gpio11", +}; + +static const char * const pwrdown_groups[] = { + "pwrdown", +}; + +static const char * const gpadc_start_groups[] = { + "gpadc_start", +}; + +static const char * const reset_in_groups[] = { + "reset_in", +}; + +static const char * const nsleep_groups[] = { + "nsleep", +}; + +static const char * const enable_groups[] = { + "enable1", + "enable2", +}; + +#define FUNCTION_GROUPS \ + FUNCTION_GROUP(opt0, OPTION0), \ + FUNCTION_GROUP(opt1, OPTION1), \ + FUNCTION_GROUP(opt2, OPTION2), \ + FUNCTION_GROUP(opt3, OPTION3), \ + FUNCTION_GROUP(gpio, GPIO), \ + FUNCTION_GROUP(led, LED), \ + FUNCTION_GROUP(pwm, PWM), \ + FUNCTION_GROUP(regen, REGEN), \ + FUNCTION_GROUP(sysen, SYSEN), \ + FUNCTION_GROUP(clk32kgaudio, CLK32KGAUDIO), \ + FUNCTION_GROUP(id, ID), \ + FUNCTION_GROUP(vbus_det, VBUS_DET), \ + FUNCTION_GROUP(chrg_det, CHRG_DET), \ + FUNCTION_GROUP(vac, VAC), \ + FUNCTION_GROUP(vacok, VACOK), \ + FUNCTION_GROUP(powergood, POWERGOOD), \ + FUNCTION_GROUP(usb_psel, USB_PSEL), \ + FUNCTION_GROUP(msecure, MSECURE), \ + FUNCTION_GROUP(pwrhold, PWRHOLD), \ + FUNCTION_GROUP(int, INT), \ + FUNCTION_GROUP(nreswarm, NRESWARM), \ + FUNCTION_GROUP(simrsto, SIMRSTO), \ + FUNCTION_GROUP(simrsti, SIMRSTI), \ + FUNCTION_GROUP(low_vbat, LOW_VBAT), \ + FUNCTION_GROUP(wireless_chrg1, WIRELESS_CHRG1), \ + FUNCTION_GROUP(rcm, RCM), \ + FUNCTION_GROUP(pwrdown, PWRDOWN), \ + FUNCTION_GROUP(gpadc_start, GPADC_START), \ + FUNCTION_GROUP(reset_in, RESET_IN), \ + FUNCTION_GROUP(nsleep, NSLEEP), \ + FUNCTION_GROUP(enable, ENABLE) + +static const struct palmas_pin_function palmas_pin_function[] = { +#undef FUNCTION_GROUP +#define FUNCTION_GROUP(fname, mux) \ + { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + + FUNCTION_GROUPS, +}; + +enum palmas_pinmux { +#undef FUNCTION_GROUP +#define FUNCTION_GROUP(fname, mux) PALMAS_PINMUX_##mux + FUNCTION_GROUPS, + PALMAS_PINMUX_NA = 0xFFFF, +}; + +struct palmas_pins_pullup_dn_info { + int pullup_dn_reg_base; + int pullup_dn_reg_add; + int pullup_dn_mask; + int normal_val; + int pull_up_val; + int pull_dn_val; +}; + +struct palmas_pins_od_info { + int od_reg_base; + int od_reg_add; + int od_mask; + int od_enable; + int od_disable; +}; + +struct palmas_pin_info { + enum palmas_pinmux mux_opt; + const struct palmas_pins_pullup_dn_info *pud_info; + const struct palmas_pins_od_info *od_info; +}; + +struct palmas_pingroup { + const char *name; + const unsigned pins[1]; + unsigned npins; + unsigned mux_reg_base; + unsigned mux_reg_add; + unsigned mux_reg_mask; + unsigned mux_bit_shift; + const struct palmas_pin_info *opt[4]; +}; + +#define PULL_UP_DN(_name, _rbase, _add, _mask, _nv, _uv, _dv) \ +static const struct palmas_pins_pullup_dn_info pud_##_name##_info = { \ + .pullup_dn_reg_base = PALMAS_##_rbase##_BASE, \ + .pullup_dn_reg_add = _add, \ + .pullup_dn_mask = _mask, \ + .normal_val = _nv, \ + .pull_up_val = _uv, \ + .pull_dn_val = _dv, \ +} + +PULL_UP_DN(nreswarm, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x2, 0x0, 0x2, -1); +PULL_UP_DN(pwrdown, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x4, 0x0, -1, 0x4); +PULL_UP_DN(gpadc_start, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x30, 0x0, 0x20, 0x10); +PULL_UP_DN(reset_in, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x40, 0x0, -1, 0x40); +PULL_UP_DN(nsleep, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x3, 0x0, 0x2, 0x1); +PULL_UP_DN(enable1, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0xC, 0x0, 0x8, 0x4); +PULL_UP_DN(enable2, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x30, 0x0, 0x20, 0x10); +PULL_UP_DN(vacok, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x40, 0x0, -1, 0x40); +PULL_UP_DN(chrg_det, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x10, 0x0, -1, 0x10); +PULL_UP_DN(pwrhold, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x4, 0x0, -1, 0x4); +PULL_UP_DN(msecure, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x1, 0x0, -1, 0x1); +PULL_UP_DN(id, USB_OTG, PALMAS_USB_ID_CTRL_SET, 0x40, 0x0, 0x40, -1); +PULL_UP_DN(gpio0, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x04, 0, -1, 1); +PULL_UP_DN(gpio1, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x0C, 0, 0x8, 0x4); +PULL_UP_DN(gpio2, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x30, 0x0, 0x20, 0x10); +PULL_UP_DN(gpio3, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x40, 0x0, -1, 0x40); +PULL_UP_DN(gpio4, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x03, 0x0, 0x2, 0x1); +PULL_UP_DN(gpio5, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x0c, 0x0, 0x8, 0x4); +PULL_UP_DN(gpio6, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x30, 0x0, 0x20, 0x10); +PULL_UP_DN(gpio7, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x40, 0x0, -1, 0x40); +PULL_UP_DN(gpio9, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x0C, 0x0, 0x8, 0x4); +PULL_UP_DN(gpio10, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x30, 0x0, 0x20, 0x10); +PULL_UP_DN(gpio11, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0xC0, 0x0, 0x80, 0x40); +PULL_UP_DN(gpio13, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x04, 0x0, -1, 0x04); +PULL_UP_DN(gpio14, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x30, 0x0, 0x20, 0x10); + +#define OD_INFO(_name, _rbase, _add, _mask, _ev, _dv) \ +static const struct palmas_pins_od_info od_##_name##_info = { \ + .od_reg_base = PALMAS_##_rbase##_BASE, \ + .od_reg_add = _add, \ + .od_mask = _mask, \ + .od_enable = _ev, \ + .od_disable = _dv, \ +} + +OD_INFO(gpio1, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x1, 0x1, 0x0); +OD_INFO(gpio2, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x2, 0x2, 0x0); +OD_INFO(gpio5, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x20, 0x20, 0x0); +OD_INFO(gpio10, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x04, 0x04, 0x0); +OD_INFO(gpio13, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x20, 0x20, 0x0); +OD_INFO(int, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x8, 0x8, 0x0); +OD_INFO(pwm1, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x20, 0x20, 0x0); +OD_INFO(pwm2, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x80, 0x80, 0x0); +OD_INFO(vbus_det, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x40, 0x40, 0x0); + +#define PIN_INFO(_name, _id, _pud_info, _od_info) \ +static const struct palmas_pin_info pin_##_name##_info = { \ + .mux_opt = PALMAS_PINMUX_##_id, \ + .pud_info = _pud_info, \ + .od_info = _od_info \ +} + +PIN_INFO(gpio0, GPIO, &pud_gpio0_info, NULL); +PIN_INFO(gpio1, GPIO, &pud_gpio1_info, &od_gpio1_info); +PIN_INFO(gpio2, GPIO, &pud_gpio2_info, &od_gpio2_info); +PIN_INFO(gpio3, GPIO, &pud_gpio3_info, NULL); +PIN_INFO(gpio4, GPIO, &pud_gpio4_info, NULL); +PIN_INFO(gpio5, GPIO, &pud_gpio5_info, &od_gpio5_info); +PIN_INFO(gpio6, GPIO, &pud_gpio6_info, NULL); +PIN_INFO(gpio7, GPIO, &pud_gpio7_info, NULL); +PIN_INFO(gpio8, GPIO, NULL, NULL); +PIN_INFO(gpio9, GPIO, &pud_gpio9_info, NULL); +PIN_INFO(gpio10, GPIO, &pud_gpio10_info, &od_gpio10_info); +PIN_INFO(gpio11, GPIO, &pud_gpio11_info, NULL); +PIN_INFO(gpio12, GPIO, NULL, NULL); +PIN_INFO(gpio13, GPIO, &pud_gpio13_info, &od_gpio13_info); +PIN_INFO(gpio14, GPIO, &pud_gpio14_info, NULL); +PIN_INFO(gpio15, GPIO, NULL, NULL); +PIN_INFO(id, ID, &pud_id_info, NULL); +PIN_INFO(led1, LED, NULL, NULL); +PIN_INFO(led2, LED, NULL, NULL); +PIN_INFO(regen, REGEN, NULL, NULL); +PIN_INFO(sysen1, SYSEN, NULL, NULL); +PIN_INFO(sysen2, SYSEN, NULL, NULL); +PIN_INFO(int, INT, NULL, &od_int_info); +PIN_INFO(pwm1, PWM, NULL, &od_pwm1_info); +PIN_INFO(pwm2, PWM, NULL, &od_pwm2_info); +PIN_INFO(vacok, VACOK, &pud_vacok_info, NULL); +PIN_INFO(chrg_det, CHRG_DET, &pud_chrg_det_info, NULL); +PIN_INFO(pwrhold, PWRHOLD, &pud_pwrhold_info, NULL); +PIN_INFO(msecure, MSECURE, &pud_msecure_info, NULL); +PIN_INFO(nreswarm, NA, &pud_nreswarm_info, NULL); +PIN_INFO(pwrdown, NA, &pud_pwrdown_info, NULL); +PIN_INFO(gpadc_start, NA, &pud_gpadc_start_info, NULL); +PIN_INFO(reset_in, NA, &pud_reset_in_info, NULL); +PIN_INFO(nsleep, NA, &pud_nsleep_info, NULL); +PIN_INFO(enable1, NA, &pud_enable1_info, NULL); +PIN_INFO(enable2, NA, &pud_enable2_info, NULL); +PIN_INFO(clk32kgaudio, CLK32KGAUDIO, NULL, NULL); +PIN_INFO(usb_psel, USB_PSEL, NULL, NULL); +PIN_INFO(vac, VAC, NULL, NULL); +PIN_INFO(powergood, POWERGOOD, NULL, NULL); +PIN_INFO(vbus_det, VBUS_DET, NULL, &od_vbus_det_info); +PIN_INFO(sim1rsti, SIMRSTI, NULL, NULL); +PIN_INFO(low_vbat, LOW_VBAT, NULL, NULL); +PIN_INFO(rcm, RCM, NULL, NULL); +PIN_INFO(sim2rsto, SIMRSTO, NULL, NULL); +PIN_INFO(sim2rsti, SIMRSTI, NULL, NULL); +PIN_INFO(wireless_chrg1, WIRELESS_CHRG1, NULL, NULL); + +#define PALMAS_PRIMARY_SECONDARY_NONE 0 +#define PALMAS_NONE_BASE 0 +#define PALMAS_PRIMARY_SECONDARY_INPUT3 PALMAS_PU_PD_INPUT_CTRL3 + +#define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3) \ + { \ + .name = #pg_name, \ + .pins = {PALMAS_PIN_##pin_id}, \ + .npins = 1, \ + .mux_reg_base = PALMAS_##base##_BASE, \ + .mux_reg_add = PALMAS_PRIMARY_SECONDARY_##reg, \ + .mux_reg_mask = _mask, \ + .mux_bit_shift = _bshift, \ + .opt = { \ + o0, \ + o1, \ + o2, \ + o3, \ + }, \ + } + +static const struct palmas_pingroup tps65913_pingroups[] = { + PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL), + PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info), + PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info), + PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL), + PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL), + PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL), + PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL), + PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL), + PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL), + PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL), + PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL), + PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL), + PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL), + PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL), + PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL), + PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL), + PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL), + PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL), +}; + +static const struct palmas_pingroup tps80036_pingroups[] = { + PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL), + PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info), + PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info), + PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL), + PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL), + PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL), + PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL), + PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL), + PALMAS_PINGROUP(gpio8, GPIO8_SIM1RSTI, PU_PD_OD, PAD4, 0x01, 0x0, &pin_gpio8_info, &pin_sim1rsti_info, NULL, NULL), + PALMAS_PINGROUP(gpio9, GPIO9_LOW_VBAT, PU_PD_OD, PAD4, 0x02, 0x1, &pin_gpio9_info, &pin_low_vbat_info, NULL, NULL), + PALMAS_PINGROUP(gpio10, GPIO10_WIRELESS_CHRG1, PU_PD_OD, PAD4, 0x04, 0x2, &pin_gpio10_info, &pin_wireless_chrg1_info, NULL, NULL), + PALMAS_PINGROUP(gpio11, GPIO11_RCM, PU_PD_OD, PAD4, 0x08, 0x3, &pin_gpio11_info, &pin_rcm_info, NULL, NULL), + PALMAS_PINGROUP(gpio12, GPIO12_SIM2RSTO, PU_PD_OD, PAD4, 0x10, 0x4, &pin_gpio12_info, &pin_sim2rsto_info, NULL, NULL), + PALMAS_PINGROUP(gpio13, GPIO13, NONE, NONE, 0x00, 0x0, &pin_gpio13_info, NULL, NULL, NULL), + PALMAS_PINGROUP(gpio14, GPIO14, NONE, NONE, 0x00, 0x0, &pin_gpio14_info, NULL, NULL, NULL), + PALMAS_PINGROUP(gpio15, GPIO15_SIM2RSTI, PU_PD_OD, PAD4, 0x80, 0x7, &pin_gpio15_info, &pin_sim2rsti_info, NULL, NULL), + PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL), + PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL), + PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL), + PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL), + PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL), + PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL), + PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL), + PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL), + PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL), + PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL), +}; + +static int palmas_pinctrl_get_pin_mux(struct palmas_pctrl_chip_info *pci) +{ + const struct palmas_pingroup *g; + unsigned int val; + int ret; + int i; + + for (i = 0; i < pci->num_pin_groups; ++i) { + g = &pci->pin_groups[i]; + if (g->mux_reg_base == PALMAS_NONE_BASE) { + pci->pins_current_opt[i] = 0; + continue; + } + ret = palmas_read(pci->palmas, g->mux_reg_base, + g->mux_reg_add, &val); + if (ret < 0) { + dev_err(pci->dev, "mux_reg 0x%02x read failed: %d\n", + g->mux_reg_add, ret); + return ret; + } + val &= g->mux_reg_mask; + pci->pins_current_opt[i] = val >> g->mux_bit_shift; + } + return 0; +} + +static int palmas_pinctrl_set_dvfs1(struct palmas_pctrl_chip_info *pci, + bool enable) +{ + int ret; + int val; + + val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 : 0; + ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE, + PALMAS_PRIMARY_SECONDARY_PAD3, + PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1, val); + if (ret < 0) + dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret); + return ret; +} + +static int palmas_pinctrl_set_dvfs2(struct palmas_pctrl_chip_info *pci, + bool enable) +{ + int ret; + int val; + + val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 : 0; + ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE, + PALMAS_PRIMARY_SECONDARY_PAD3, + PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2, val); + if (ret < 0) + dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret); + return ret; +} + +static int palmas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + + return pci->num_pin_groups; +} + +static const char *palmas_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + + return pci->pin_groups[group].name; +} + +static int palmas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, const unsigned **pins, unsigned *num_pins) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + + *pins = pci->pin_groups[group].pins; + *num_pins = pci->pin_groups[group].npins; + return 0; +} + +static const struct pinctrl_ops palmas_pinctrl_ops = { + .get_groups_count = palmas_pinctrl_get_groups_count, + .get_group_name = palmas_pinctrl_get_group_name, + .get_group_pins = palmas_pinctrl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int palmas_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + + return pci->num_functions; +} + +static const char *palmas_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + + return pci->functions[function].name; +} + +static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, const char * const **groups, + unsigned * const num_groups) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + + *groups = pci->functions[function].groups; + *num_groups = pci->functions[function].ngroups; + return 0; +} + +static int palmas_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, + unsigned group) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + const struct palmas_pingroup *g; + int i; + int ret; + + g = &pci->pin_groups[group]; + + /* If direct option is provided here */ + if (function <= PALMAS_PINMUX_OPTION3) { + if (!g->opt[function]) { + dev_err(pci->dev, "Pin %s does not support option %d\n", + g->name, function); + return -EINVAL; + } + i = function; + } else { + for (i = 0; i < ARRAY_SIZE(g->opt); i++) { + if (!g->opt[i]) + continue; + if (g->opt[i]->mux_opt == function) + break; + } + if (WARN_ON(i == ARRAY_SIZE(g->opt))) { + dev_err(pci->dev, "Pin %s does not support option %d\n", + g->name, function); + return -EINVAL; + } + } + + if (g->mux_reg_base == PALMAS_NONE_BASE) { + if (WARN_ON(i != 0)) + return -EINVAL; + return 0; + } + + dev_dbg(pci->dev, "%s(): Base0x%02x:0x%02x:0x%02x:0x%02x\n", + __func__, g->mux_reg_base, g->mux_reg_add, + g->mux_reg_mask, i << g->mux_bit_shift); + + ret = palmas_update_bits(pci->palmas, g->mux_reg_base, g->mux_reg_add, + g->mux_reg_mask, i << g->mux_bit_shift); + if (ret < 0) { + dev_err(pci->dev, "Reg 0x%02x update failed: %d\n", + g->mux_reg_add, ret); + return ret; + } + pci->pins_current_opt[group] = i; + return 0; +} + +static const struct pinmux_ops palmas_pinmux_ops = { + .get_functions_count = palmas_pinctrl_get_funcs_count, + .get_function_name = palmas_pinctrl_get_func_name, + .get_function_groups = palmas_pinctrl_get_func_groups, + .enable = palmas_pinctrl_enable, +}; + +static int palmas_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin, unsigned long *config) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + const struct palmas_pingroup *g; + const struct palmas_pin_info *opt; + unsigned int val; + int ret; + int base, add; + int rval; + int arg; + int group_nr; + + for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) { + if (pci->pin_groups[group_nr].pins[0] == pin) + break; + } + + if (group_nr == pci->num_pin_groups) { + dev_err(pci->dev, + "Pinconf is not supported for pin-id %d\n", pin); + return -ENOTSUPP; + } + + g = &pci->pin_groups[group_nr]; + opt = g->opt[pci->pins_current_opt[group_nr]]; + if (!opt) { + dev_err(pci->dev, + "Pinconf is not supported for pin %s\n", g->name); + return -ENOTSUPP; + } + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!opt->pud_info) { + dev_err(pci->dev, + "PULL control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + base = opt->pud_info->pullup_dn_reg_base; + add = opt->pud_info->pullup_dn_reg_add; + ret = palmas_read(pci->palmas, base, add, &val); + if (ret < 0) { + dev_err(pci->dev, "Reg 0x%02x read failed: %d\n", + add, ret); + return ret; + } + + rval = val & opt->pud_info->pullup_dn_mask; + arg = 0; + if ((opt->pud_info->normal_val >= 0) && + (opt->pud_info->normal_val == rval) && + (param == PIN_CONFIG_BIAS_DISABLE)) + arg = 1; + else if ((opt->pud_info->pull_up_val >= 0) && + (opt->pud_info->pull_up_val == rval) && + (param == PIN_CONFIG_BIAS_PULL_UP)) + arg = 1; + else if ((opt->pud_info->pull_dn_val >= 0) && + (opt->pud_info->pull_dn_val == rval) && + (param == PIN_CONFIG_BIAS_PULL_DOWN)) + arg = 1; + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!opt->od_info) { + dev_err(pci->dev, + "OD control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + base = opt->od_info->od_reg_base; + add = opt->od_info->od_reg_add; + ret = palmas_read(pci->palmas, base, add, &val); + if (ret < 0) { + dev_err(pci->dev, "Reg 0x%02x read failed: %d\n", + add, ret); + return ret; + } + rval = val & opt->od_info->od_mask; + arg = -1; + if ((opt->od_info->od_disable >= 0) && + (opt->od_info->od_disable == rval)) + arg = 0; + else if ((opt->od_info->od_enable >= 0) && + (opt->od_info->od_enable == rval)) + arg = 1; + if (arg < 0) { + dev_err(pci->dev, + "OD control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + break; + + default: + dev_err(pci->dev, "Properties not supported\n"); + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, (u16)arg); + return 0; +} + +static int palmas_pinconf_set(struct pinctrl_dev *pctldev, + unsigned pin, unsigned long config) +{ + struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(config); + u16 param_val = pinconf_to_config_argument(config); + const struct palmas_pingroup *g; + const struct palmas_pin_info *opt; + int ret; + int base, add, mask; + int rval; + int group_nr; + + for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) { + if (pci->pin_groups[group_nr].pins[0] == pin) + break; + } + + if (group_nr == pci->num_pin_groups) { + dev_err(pci->dev, + "Pinconf is not supported for pin-id %d\n", pin); + return -ENOTSUPP; + } + + g = &pci->pin_groups[group_nr]; + opt = g->opt[pci->pins_current_opt[group_nr]]; + if (!opt) { + dev_err(pci->dev, + "Pinconf is not supported for pin %s\n", g->name); + return -ENOTSUPP; + } + + switch (param) { + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + return 0; + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!opt->pud_info) { + dev_err(pci->dev, + "PULL control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + base = opt->pud_info->pullup_dn_reg_base; + add = opt->pud_info->pullup_dn_reg_add; + mask = opt->pud_info->pullup_dn_mask; + + if (param == PIN_CONFIG_BIAS_DISABLE) + rval = opt->pud_info->normal_val; + else if (param == PIN_CONFIG_BIAS_PULL_UP) + rval = opt->pud_info->pull_up_val; + else + rval = opt->pud_info->pull_dn_val; + + if (rval < 0) { + dev_err(pci->dev, + "PULL control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!opt->od_info) { + dev_err(pci->dev, + "OD control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + base = opt->od_info->od_reg_base; + add = opt->od_info->od_reg_add; + mask = opt->od_info->od_mask; + if (param_val == 0) + rval = opt->od_info->od_disable; + else + rval = opt->od_info->od_enable; + if (rval < 0) { + dev_err(pci->dev, + "OD control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + break; + default: + dev_err(pci->dev, "Properties not supported\n"); + return -ENOTSUPP; + } + + dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n", + __func__, base, add, mask, rval); + ret = palmas_update_bits(pci->palmas, base, add, mask, rval); + if (ret < 0) { + dev_err(pci->dev, "Reg 0x%02x update failed: %d\n", add, ret); + return ret; + } + return 0; +} + +static int palmas_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned group, unsigned long *config) +{ + dev_err(pctldev->dev, "palmas_pinconf_group_get op not supported\n"); + return -ENOTSUPP; +} + +static int palmas_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned group, unsigned long config) +{ + dev_err(pctldev->dev, "palmas_pinconf_group_set op not supported\n"); + return -ENOTSUPP; +} + +static const struct pinconf_ops palmas_pinconf_ops = { + .pin_config_get = palmas_pinconf_get, + .pin_config_set = palmas_pinconf_set, + .pin_config_group_get = palmas_pinconf_group_get, + .pin_config_group_set = palmas_pinconf_group_set, +}; + +static struct pinctrl_desc palmas_pinctrl_desc = { + .pctlops = &palmas_pinctrl_ops, + .pmxops = &palmas_pinmux_ops, + .confops = &palmas_pinconf_ops, + .owner = THIS_MODULE, +}; + +struct palmas_pinctrl_data { + const struct palmas_pingroup *pin_groups; + int num_pin_groups; +}; + +static struct palmas_pinctrl_data tps65913_pinctrl_data = { + .pin_groups = tps65913_pingroups, + .num_pin_groups = ARRAY_SIZE(tps65913_pingroups), +}; + +static struct palmas_pinctrl_data tps80036_pinctrl_data = { + .pin_groups = tps80036_pingroups, + .num_pin_groups = ARRAY_SIZE(tps80036_pingroups), +}; + +static struct of_device_id palmas_pinctrl_of_match[] = { + { .compatible = "ti,palmas-pinctrl", .data = &tps65913_pinctrl_data}, + { .compatible = "ti,tps65913-pinctrl", .data = &tps65913_pinctrl_data}, + { .compatible = "ti,tps80036-pinctrl", .data = &tps80036_pinctrl_data}, + { }, +}; +MODULE_DEVICE_TABLE(of, palmas_pinctrl_of_match); + +static int palmas_pinctrl_probe(struct platform_device *pdev) +{ + struct palmas_pctrl_chip_info *pci; + const struct palmas_pinctrl_data *pinctrl_data = &tps65913_pinctrl_data; + int ret; + bool enable_dvfs1 = false; + bool enable_dvfs2 = false; + + if (pdev->dev.of_node) { + const struct of_device_id *match; + match = of_match_device(palmas_pinctrl_of_match, &pdev->dev); + pinctrl_data = match->data; + enable_dvfs1 = of_property_read_bool(pdev->dev.of_node, + "ti,palmas-enable-dvfs1"); + enable_dvfs2 = of_property_read_bool(pdev->dev.of_node, + "ti,palmas-enable-dvfs2"); + } + + pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL); + if (!pci) { + dev_err(&pdev->dev, "Malloc for pci failed\n"); + return -ENOMEM; + } + + pci->dev = &pdev->dev; + pci->palmas = dev_get_drvdata(pdev->dev.parent); + + pci->pins = palmas_pins_desc; + pci->num_pins = ARRAY_SIZE(palmas_pins_desc); + pci->functions = palmas_pin_function; + pci->num_functions = ARRAY_SIZE(palmas_pin_function); + pci->pin_groups = pinctrl_data->pin_groups; + pci->num_pin_groups = pinctrl_data->num_pin_groups; + + platform_set_drvdata(pdev, pci); + + palmas_pinctrl_set_dvfs1(pci, enable_dvfs1); + palmas_pinctrl_set_dvfs2(pci, enable_dvfs2); + ret = palmas_pinctrl_get_pin_mux(pci); + if (ret < 0) { + dev_err(&pdev->dev, + "Reading pinctrol option register failed: %d\n", ret); + return ret; + } + + palmas_pinctrl_desc.name = dev_name(&pdev->dev); + palmas_pinctrl_desc.pins = palmas_pins_desc; + palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc); + pci->pctl = pinctrl_register(&palmas_pinctrl_desc, &pdev->dev, pci); + if (!pci->pctl) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return -ENODEV; + } + return 0; +} + +static int palmas_pinctrl_remove(struct platform_device *pdev) +{ + struct palmas_pctrl_chip_info *pci = platform_get_drvdata(pdev); + + pinctrl_unregister(pci->pctl); + return 0; +} + +static struct platform_driver palmas_pinctrl_driver = { + .driver = { + .name = "palmas-pinctrl", + .owner = THIS_MODULE, + .of_match_table = palmas_pinctrl_of_match, + }, + .probe = palmas_pinctrl_probe, + .remove = palmas_pinctrl_remove, +}; + +module_platform_driver(palmas_pinctrl_driver); + +MODULE_DESCRIPTION("Palmas pin control driver"); +MODULE_AUTHOR("Laxman Dewangan"); +MODULE_ALIAS("platform:palmas-pinctrl"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h index 1a8dd7afe084..2891f7cd902e 100644 --- a/include/linux/mfd/palmas.h +++ b/include/linux/mfd/palmas.h @@ -449,7 +449,7 @@ enum usb_irq_events { #define PALMAS_DVFS_BASE 0x180 #define PALMAS_PMU_CONTROL_BASE 0x1A0 #define PALMAS_RESOURCE_BASE 0x1D4 -#define PALMAS_PU_PD_OD_BASE 0x1F4 +#define PALMAS_PU_PD_OD_BASE 0x1F0 #define PALMAS_LED_BASE 0x200 #define PALMAS_INTERRUPT_BASE 0x210 #define PALMAS_USB_OTG_BASE 0x250 @@ -1734,16 +1734,20 @@ enum usb_irq_events { #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0 /* Registers for function PAD_CONTROL */ -#define PALMAS_PU_PD_INPUT_CTRL1 0x0 -#define PALMAS_PU_PD_INPUT_CTRL2 0x1 -#define PALMAS_PU_PD_INPUT_CTRL3 0x2 -#define PALMAS_OD_OUTPUT_CTRL 0x4 -#define PALMAS_POLARITY_CTRL 0x5 -#define PALMAS_PRIMARY_SECONDARY_PAD1 0x6 -#define PALMAS_PRIMARY_SECONDARY_PAD2 0x7 -#define PALMAS_I2C_SPI 0x8 -#define PALMAS_PU_PD_INPUT_CTRL4 0x9 -#define PALMAS_PRIMARY_SECONDARY_PAD3 0xA +#define PALMAS_OD_OUTPUT_CTRL2 0x2 +#define PALMAS_POLARITY_CTRL2 0x3 +#define PALMAS_PU_PD_INPUT_CTRL1 0x4 +#define PALMAS_PU_PD_INPUT_CTRL2 0x5 +#define PALMAS_PU_PD_INPUT_CTRL3 0x6 +#define PALMAS_PU_PD_INPUT_CTRL5 0x7 +#define PALMAS_OD_OUTPUT_CTRL 0x8 +#define PALMAS_POLARITY_CTRL 0x9 +#define PALMAS_PRIMARY_SECONDARY_PAD1 0xA +#define PALMAS_PRIMARY_SECONDARY_PAD2 0xB +#define PALMAS_I2C_SPI 0xC +#define PALMAS_PU_PD_INPUT_CTRL4 0xD +#define PALMAS_PRIMARY_SECONDARY_PAD3 0xE +#define PALMAS_PRIMARY_SECONDARY_PAD4 0xF /* Bit definitions for PU_PD_INPUT_CTRL1 */ #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 @@ -2501,6 +2505,15 @@ enum usb_irq_events { #define PALMAS_PU_PD_GPIO_CTRL1 0x6 #define PALMAS_PU_PD_GPIO_CTRL2 0x7 #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8 +#define PALMAS_GPIO_DATA_IN2 0x9 +#define PALMAS_GPIO_DATA_DIR2 0x0A +#define PALMAS_GPIO_DATA_OUT2 0x0B +#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C +#define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D +#define PALMAS_GPIO_SET_DATA_OUT2 0x0E +#define PALMAS_PU_PD_GPIO_CTRL3 0x0F +#define PALMAS_PU_PD_GPIO_CTRL4 0x10 +#define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11 /* Bit definitions for GPIO_DATA_IN */ #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 -- cgit v1.2.3 From 0d74d4a161c9f9870039af414b712552c0ed6dfb Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 15 Aug 2013 21:38:49 +0200 Subject: pinctrl: add includes and ifdefs for non-DT builds Commit e81c8f18afc4fdd6e34d8c83814b8b5134dbb30f "pinctrl: pinconf-generic: add generic APIs for mapping pinctrl node" Added function prototypes with implicit dependencies on other header files causing build warnings like this: In file included from arch/arm/mach-ux500/board-mop500-pins.c:12:0: include/linux/pinctrl/pinconf-generic.h:142:3: warning: 'struct device_node' declared inside parameter list [enabled by default] unsigned *reserved_maps, unsigned *num_maps); ^ include/linux/pinctrl/pinconf-generic.h:142:3: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default] include/linux/pinctrl/pinconf-generic.h:142:3: warning: 'struct pinctrl_dev' declared inside parameter list [enabled by default] include/linux/pinctrl/pinconf-generic.h:145:3: warning: 'struct device_node' declared inside parameter list [enabled by default] unsigned *num_maps); ^ Let's just add ifdefs for non-DT systems (the actual code is already ifdefed) and #include to get the most important structs and forward-declare the pinctrl core structs. Reported-by: Olof Johansson Cc: Laxman Dewangan Signed-off-by: Linus Walleij --- include/linux/pinctrl/pinconf-generic.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index a472b93292a3..83f5179ea0c5 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -137,12 +137,21 @@ static inline unsigned long pinconf_to_config_packed(enum pin_config_param param return PIN_CONF_PACKED(param, argument); } +#ifdef CONFIG_OF + +#include +struct pinctrl_dev; +struct pinctrl_map; + int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned *reserved_maps, unsigned *num_maps); int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, struct pinctrl_map **map, unsigned *num_maps); + +#endif + #endif /* CONFIG_GENERIC_PINCONF */ #endif /* __LINUX_PINCTRL_PINCONF_GENERIC_H */ -- cgit v1.2.3 From 3287c24088abded9f111ca797fdd36f86912d199 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 21 Aug 2013 16:53:37 +0530 Subject: pinctrl: utils : add support to pass config type in generic util APIs Add support to pass the config type like GROUP or PIN when using the utils or generic pin configuration APIs. This will make the APIs more generic. Added additional inline APIs such that it can be use directly as callback for the pinctrl_ops. Changes from V1: - Remove separate implementation for pins and group for pinctrl_utils_dt_free_map and improve this function to support both i.e. PINS and GROUPs. Signed-off-by: Laxman Dewangan Reviewed-by: Stephen Warren Tested-by: Stephen Warren Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 9 +++++---- drivers/pinctrl/pinctrl-palmas.c | 2 +- drivers/pinctrl/pinctrl-utils.c | 12 +++++++++--- include/linux/pinctrl/pinconf-generic.h | 22 ++++++++++++++++++++-- 4 files changed, 35 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index d9536caa9c41..2c62225bafab 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -240,7 +240,8 @@ out: int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, - unsigned *reserved_maps, unsigned *num_maps) + unsigned *reserved_maps, unsigned *num_maps, + enum pinctrl_map_type type) { int ret; const char *function; @@ -295,7 +296,7 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, if (num_configs) { ret = pinctrl_utils_add_map_configs(pctldev, map, reserved_maps, num_maps, group, configs, - num_configs, PIN_MAP_TYPE_CONFIGS_PIN); + num_configs, type); if (ret < 0) goto exit; } @@ -310,7 +311,7 @@ EXPORT_SYMBOL_GPL(pinconf_generic_dt_subnode_to_map); int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, struct pinctrl_map **map, - unsigned *num_maps) + unsigned *num_maps, enum pinctrl_map_type type) { unsigned reserved_maps; struct device_node *np; @@ -322,7 +323,7 @@ int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev, for_each_child_of_node(np_config, np) { ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map, - &reserved_maps, num_maps); + &reserved_maps, num_maps, type); if (ret < 0) { pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); return ret; diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c index 2697c2efd74b..9550c33b2544 100644 --- a/drivers/pinctrl/pinctrl-palmas.c +++ b/drivers/pinctrl/pinctrl-palmas.c @@ -655,7 +655,7 @@ static const struct pinctrl_ops palmas_pinctrl_ops = { .get_groups_count = palmas_pinctrl_get_groups_count, .get_group_name = palmas_pinctrl_get_group_name, .get_group_pins = palmas_pinctrl_get_group_pins, - .dt_node_to_map = pinconf_generic_dt_node_to_map, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, .dt_free_map = pinctrl_utils_dt_free_map, }; diff --git a/drivers/pinctrl/pinctrl-utils.c b/drivers/pinctrl/pinctrl-utils.c index b7ac646c43ba..48277e025f84 100644 --- a/drivers/pinctrl/pinctrl-utils.c +++ b/drivers/pinctrl/pinctrl-utils.c @@ -126,10 +126,16 @@ void pinctrl_utils_dt_free_map(struct pinctrl_dev *pctldev, { int i; - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) + for (i = 0; i < num_maps; i++) { + switch (map[i].type) { + case PIN_MAP_TYPE_CONFIGS_GROUP: + case PIN_MAP_TYPE_CONFIGS_PIN: kfree(map[i].data.configs.configs); - + break; + default: + break; + } + } kfree(map); } EXPORT_SYMBOL_GPL(pinctrl_utils_dt_free_map); diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index 83f5179ea0c5..fb90ef5eb038 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -140,15 +140,33 @@ static inline unsigned long pinconf_to_config_packed(enum pin_config_param param #ifdef CONFIG_OF #include +#include struct pinctrl_dev; struct pinctrl_map; int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, - unsigned *reserved_maps, unsigned *num_maps); + unsigned *reserved_maps, unsigned *num_maps, + enum pinctrl_map_type type); int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, struct pinctrl_map **map, - unsigned *num_maps); + unsigned *num_maps, enum pinctrl_map_type type); + +static inline int pinconf_generic_dt_node_to_map_group( + struct pinctrl_dev *pctldev, struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps, + PIN_MAP_TYPE_CONFIGS_GROUP); +} + +static inline int pinconf_generic_dt_node_to_map_pin( + struct pinctrl_dev *pctldev, struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps, + PIN_MAP_TYPE_CONFIGS_PIN); +} #endif -- cgit v1.2.3 From 03b054e9696c3cbd3d5905ec96da15acd0a2fe8d Mon Sep 17 00:00:00 2001 From: Sherman Yin Date: Tue, 27 Aug 2013 11:32:12 -0700 Subject: pinctrl: Pass all configs to driver on pin_config_set() When setting pin configuration in the pinctrl framework, pin_config_set() or pin_config_group_set() is called in a loop to set one configuration at a time for the specified pin or group. This patch 1) removes the loop and 2) changes the API to pass the whole pin config array to the driver. It is now up to the driver to loop through the configs. This allows the driver to potentially combine configs and reduce the number of writes to pin config registers. All c files changed have been build-tested to verify the change compiles and that the corresponding .o is successfully generated. Signed-off-by: Sherman Yin Reviewed-by: Christian Daudt Reviewed-by: Matt Porter Tested-by: Stephen Warren Acked-by: Laurent Pinchart Signed-off-by: Linus Walleij --- drivers/pinctrl/mvebu/pinctrl-mvebu.c | 26 +++-- drivers/pinctrl/pinconf.c | 42 ++++---- drivers/pinctrl/pinctrl-abx500.c | 187 ++++++++++++++++++---------------- drivers/pinctrl/pinctrl-at91.c | 48 +++++---- drivers/pinctrl/pinctrl-bcm2835.c | 43 ++++---- drivers/pinctrl/pinctrl-exynos5440.c | 113 ++++++++++---------- drivers/pinctrl/pinctrl-falcon.c | 63 +++++++----- drivers/pinctrl/pinctrl-imx.c | 28 ++--- drivers/pinctrl/pinctrl-mxs.c | 91 +++++++++-------- drivers/pinctrl/pinctrl-nomadik.c | 125 ++++++++++++----------- drivers/pinctrl/pinctrl-palmas.c | 134 +++++++++++++----------- drivers/pinctrl/pinctrl-rockchip.c | 57 +++++++---- drivers/pinctrl/pinctrl-samsung.c | 17 +++- drivers/pinctrl/pinctrl-single.c | 33 ++++-- drivers/pinctrl/pinctrl-st.c | 11 +- drivers/pinctrl/pinctrl-sunxi.c | 77 +++++++------- drivers/pinctrl/pinctrl-tegra.c | 69 +++++++------ drivers/pinctrl/pinctrl-tz1090-pdc.c | 135 +++++++++++++----------- drivers/pinctrl/pinctrl-tz1090.c | 140 ++++++++++++++----------- drivers/pinctrl/pinctrl-u300.c | 18 ++-- drivers/pinctrl/pinctrl-xway.c | 119 +++++++++++++--------- drivers/pinctrl/sh-pfc/pinctrl.c | 42 ++++---- drivers/pinctrl/vt8500/pinctrl-wmt.c | 54 +++++----- include/linux/pinctrl/pinconf.h | 6 +- 24 files changed, 952 insertions(+), 726 deletions(-) (limited to 'include') diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index bb7ddb1bc89f..e78c041c3c73 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -191,18 +191,27 @@ static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev, } static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned gid, unsigned long config) + unsigned gid, unsigned long *configs, + unsigned num_configs) { struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct mvebu_pinctrl_group *grp = &pctl->groups[gid]; + int i, ret; if (!grp->ctrl) return -EINVAL; - if (grp->ctrl->mpp_set) - return grp->ctrl->mpp_set(grp->ctrl, config); + for (i = 0; i < num_configs; i++) { + if (grp->ctrl->mpp_set) + ret = grp->ctrl->mpp_set(grp->ctrl, configs[i]); + else + ret = mvebu_common_mpp_set(pctl, grp, configs[i]); - return mvebu_common_mpp_set(pctl, grp, config); + if (ret) + return ret; + } /* for each config */ + + return 0; } static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, @@ -303,6 +312,7 @@ static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid, struct mvebu_pinctrl_group *grp = &pctl->groups[gid]; struct mvebu_mpp_ctrl_setting *setting; int ret; + unsigned long config; setting = mvebu_pinctrl_find_setting_by_name(pctl, grp, func->name); @@ -313,7 +323,8 @@ static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid, return -EINVAL; } - ret = mvebu_pinconf_group_set(pctldev, grp->gid, setting->val); + config = setting->val; + ret = mvebu_pinconf_group_set(pctldev, grp->gid, &config, 1); if (ret) { dev_err(pctl->dev, "cannot set group %s to %s\n", func->groups[gid], func->name); @@ -329,6 +340,7 @@ static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct mvebu_pinctrl_group *grp; struct mvebu_mpp_ctrl_setting *setting; + unsigned long config; grp = mvebu_pinctrl_find_group_by_pid(pctl, offset); if (!grp) @@ -341,7 +353,9 @@ static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, if (!setting) return -ENOTSUPP; - return mvebu_pinconf_group_set(pctldev, grp->gid, setting->val); + config = setting->val; + + return mvebu_pinconf_group_set(pctldev, grp->gid, &config, 1); } static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index 8da2d6db228c..a138965c01cb 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -158,7 +158,7 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting) { struct pinctrl_dev *pctldev = setting->pctldev; const struct pinconf_ops *ops = pctldev->desc->confops; - int i, ret; + int ret; if (!ops) { dev_err(pctldev->dev, "missing confops\n"); @@ -171,17 +171,15 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting) dev_err(pctldev->dev, "missing pin_config_set op\n"); return -EINVAL; } - for (i = 0; i < setting->data.configs.num_configs; i++) { - ret = ops->pin_config_set(pctldev, - setting->data.configs.group_or_pin, - setting->data.configs.configs[i]); - if (ret < 0) { - dev_err(pctldev->dev, - "pin_config_set op failed for pin %d config %08lx\n", - setting->data.configs.group_or_pin, - setting->data.configs.configs[i]); - return ret; - } + ret = ops->pin_config_set(pctldev, + setting->data.configs.group_or_pin, + setting->data.configs.configs, + setting->data.configs.num_configs); + if (ret < 0) { + dev_err(pctldev->dev, + "pin_config_set op failed for pin %d\n", + setting->data.configs.group_or_pin); + return ret; } break; case PIN_MAP_TYPE_CONFIGS_GROUP: @@ -190,17 +188,15 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting) "missing pin_config_group_set op\n"); return -EINVAL; } - for (i = 0; i < setting->data.configs.num_configs; i++) { - ret = ops->pin_config_group_set(pctldev, - setting->data.configs.group_or_pin, - setting->data.configs.configs[i]); - if (ret < 0) { - dev_err(pctldev->dev, - "pin_config_group_set op failed for group %d config %08lx\n", - setting->data.configs.group_or_pin, - setting->data.configs.configs[i]); - return ret; - } + ret = ops->pin_config_group_set(pctldev, + setting->data.configs.group_or_pin, + setting->data.configs.configs, + setting->data.configs.num_configs); + if (ret < 0) { + dev_err(pctldev->dev, + "pin_config_group_set op failed for group %d\n", + setting->data.configs.group_or_pin); + return ret; } break; default: diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c index 1d3f988c2c8b..8f25df06bc6b 100644 --- a/drivers/pinctrl/pinctrl-abx500.c +++ b/drivers/pinctrl/pinctrl-abx500.c @@ -1041,98 +1041,115 @@ static int abx500_pin_config_get(struct pinctrl_dev *pctldev, static int abx500_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config) + unsigned long *configs, + unsigned num_configs) { struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); struct gpio_chip *chip = &pct->chip; unsigned offset; int ret = -EINVAL; - enum pin_config_param param = pinconf_to_config_param(config); - enum pin_config_param argument = pinconf_to_config_argument(config); - - dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n", - pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input", - (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") : - (argument ? "pull up" : "pull down")); - - /* on ABx500, there is no GPIO0, so adjust the offset */ - offset = pin - 1; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - ret = abx500_gpio_direction_input(chip, offset); - if (ret < 0) - goto out; - /* - * Some chips only support pull down, while some actually - * support both pull up and pull down. Such chips have - * a "pullud" range specified for the pins that support - * both features. If the pin is not within that range, we - * fall back to the old bit set that only support pull down. - */ - if (abx500_pullud_supported(chip, pin)) - ret = abx500_set_pull_updown(pct, - pin, - ABX500_GPIO_PULL_NONE); - else - /* Chip only supports pull down */ - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, - offset, ABX500_GPIO_PULL_NONE); - break; - - case PIN_CONFIG_BIAS_PULL_DOWN: - ret = abx500_gpio_direction_input(chip, offset); - if (ret < 0) - goto out; - /* - * if argument = 1 set the pull down - * else clear the pull down - * Some chips only support pull down, while some actually - * support both pull up and pull down. Such chips have - * a "pullud" range specified for the pins that support - * both features. If the pin is not within that range, we - * fall back to the old bit set that only support pull down. - */ - if (abx500_pullud_supported(chip, pin)) - ret = abx500_set_pull_updown(pct, - pin, - argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE); - else - /* Chip only supports pull down */ - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, - offset, - argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE); - break; - - case PIN_CONFIG_BIAS_PULL_UP: - ret = abx500_gpio_direction_input(chip, offset); - if (ret < 0) - goto out; - /* - * if argument = 1 set the pull up - * else clear the pull up - */ - ret = abx500_gpio_direction_input(chip, offset); - /* - * Some chips only support pull down, while some actually - * support both pull up and pull down. Such chips have - * a "pullud" range specified for the pins that support - * both features. If the pin is not within that range, do - * nothing - */ - if (abx500_pullud_supported(chip, pin)) - ret = abx500_set_pull_updown(pct, - pin, - argument ? ABX500_GPIO_PULL_UP : ABX500_GPIO_PULL_NONE); - break; + int i; + enum pin_config_param param; + enum pin_config_param argument; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + argument = pinconf_to_config_argument(configs[i]); + + dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n", + pin, configs[i], + (param == PIN_CONFIG_OUTPUT) ? "output " : "input", + (param == PIN_CONFIG_OUTPUT) ? + (argument ? "high" : "low") : + (argument ? "pull up" : "pull down")); + + /* on ABx500, there is no GPIO0, so adjust the offset */ + offset = pin - 1; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = abx500_gpio_direction_input(chip, offset); + if (ret < 0) + goto out; + /* + * Some chips only support pull down, while some + * actually support both pull up and pull down. Such + * chips have a "pullud" range specified for the pins + * that support both features. If the pin is not + * within that range, we fall back to the old bit set + * that only support pull down. + */ + if (abx500_pullud_supported(chip, pin)) + ret = abx500_set_pull_updown(pct, + pin, + ABX500_GPIO_PULL_NONE); + else + /* Chip only supports pull down */ + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_PUD1_REG, offset, + ABX500_GPIO_PULL_NONE); + break; - case PIN_CONFIG_OUTPUT: - ret = abx500_gpio_direction_output(chip, offset, argument); - break; + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = abx500_gpio_direction_input(chip, offset); + if (ret < 0) + goto out; + /* + * if argument = 1 set the pull down + * else clear the pull down + * Some chips only support pull down, while some + * actually support both pull up and pull down. Such + * chips have a "pullud" range specified for the pins + * that support both features. If the pin is not + * within that range, we fall back to the old bit set + * that only support pull down. + */ + if (abx500_pullud_supported(chip, pin)) + ret = abx500_set_pull_updown(pct, + pin, + argument ? ABX500_GPIO_PULL_DOWN : + ABX500_GPIO_PULL_NONE); + else + /* Chip only supports pull down */ + ret = abx500_gpio_set_bits(chip, + AB8500_GPIO_PUD1_REG, + offset, + argument ? ABX500_GPIO_PULL_DOWN : + ABX500_GPIO_PULL_NONE); + break; - default: - dev_err(chip->dev, "illegal configuration requested\n"); - } + case PIN_CONFIG_BIAS_PULL_UP: + ret = abx500_gpio_direction_input(chip, offset); + if (ret < 0) + goto out; + /* + * if argument = 1 set the pull up + * else clear the pull up + */ + ret = abx500_gpio_direction_input(chip, offset); + /* + * Some chips only support pull down, while some + * actually support both pull up and pull down. Such + * chips have a "pullud" range specified for the pins + * that support both features. If the pin is not + * within that range, do nothing + */ + if (abx500_pullud_supported(chip, pin)) + ret = abx500_set_pull_updown(pct, + pin, + argument ? ABX500_GPIO_PULL_UP : + ABX500_GPIO_PULL_NONE); + break; + + case PIN_CONFIG_OUTPUT: + ret = abx500_gpio_direction_output(chip, offset, + argument); + break; + + default: + dev_err(chip->dev, "illegal configuration requested\n"); + } + } /* for each config */ out: if (ret < 0) dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 7cce066c71b6..9685ff6c8b01 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -736,30 +736,40 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev, } static int at91_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long config) + unsigned pin_id, unsigned long *configs, + unsigned num_configs) { struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); unsigned mask; void __iomem *pio; - - dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config); - pio = pin_to_controller(info, pin_to_bank(pin_id)); - mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); - - if (config & PULL_UP && config & PULL_DOWN) - return -EINVAL; - - at91_mux_set_pullup(pio, mask, config & PULL_UP); - at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); - if (info->ops->set_deglitch) - info->ops->set_deglitch(pio, mask, config & DEGLITCH); - if (info->ops->set_debounce) - info->ops->set_debounce(pio, mask, config & DEBOUNCE, + int i; + unsigned long config; + + for (i = 0; i < num_configs; i++) { + config = configs[i]; + + dev_dbg(info->dev, + "%s:%d, pin_id=%d, config=0x%lx", + __func__, __LINE__, pin_id, config); + pio = pin_to_controller(info, pin_to_bank(pin_id)); + mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); + + if (config & PULL_UP && config & PULL_DOWN) + return -EINVAL; + + at91_mux_set_pullup(pio, mask, config & PULL_UP); + at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); + if (info->ops->set_deglitch) + info->ops->set_deglitch(pio, mask, config & DEGLITCH); + if (info->ops->set_debounce) + info->ops->set_debounce(pio, mask, config & DEBOUNCE, (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); - if (info->ops->set_pulldown) - info->ops->set_pulldown(pio, mask, config & PULL_DOWN); - if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) - info->ops->disable_schmitt_trig(pio, mask); + if (info->ops->set_pulldown) + info->ops->set_pulldown(pio, mask, config & PULL_DOWN); + if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) + info->ops->disable_schmitt_trig(pio, mask); + + } /* for each config */ return 0; } diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c index a1c88b30f71f..c05c1ef2cc3c 100644 --- a/drivers/pinctrl/pinctrl-bcm2835.c +++ b/drivers/pinctrl/pinctrl-bcm2835.c @@ -893,28 +893,35 @@ static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev, } static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long config) + unsigned pin, unsigned long *configs, + unsigned num_configs) { struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); - enum bcm2835_pinconf_param param = BCM2835_PINCONF_UNPACK_PARAM(config); - u16 arg = BCM2835_PINCONF_UNPACK_ARG(config); + enum bcm2835_pinconf_param param; + u16 arg; u32 off, bit; + int i; - if (param != BCM2835_PINCONF_PARAM_PULL) - return -EINVAL; - - off = GPIO_REG_OFFSET(pin); - bit = GPIO_REG_SHIFT(pin); - - bcm2835_gpio_wr(pc, GPPUD, arg & 3); - /* - * Docs say to wait 150 cycles, but not of what. We assume a - * 1 MHz clock here, which is pretty slow... - */ - udelay(150); - bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); - udelay(150); - bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); + for (i = 0; i < num_configs; i++) { + param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]); + arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]); + + if (param != BCM2835_PINCONF_PARAM_PULL) + return -EINVAL; + + off = GPIO_REG_OFFSET(pin); + bit = GPIO_REG_SHIFT(pin); + + bcm2835_gpio_wr(pc, GPPUD, arg & 3); + /* + * Docs say to wait 150 cycles, but not of what. We assume a + * 1 MHz clock here, which is pretty slow... + */ + udelay(150); + bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); + udelay(150); + bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); + } /* for each config */ return 0; } diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c index 3b283fd898ff..544d469c5a7b 100644 --- a/drivers/pinctrl/pinctrl-exynos5440.c +++ b/drivers/pinctrl/pinctrl-exynos5440.c @@ -401,64 +401,71 @@ static const struct pinmux_ops exynos5440_pinmux_ops = { /* set the pin config settings for a specified pin */ static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long config) + unsigned long *configs, + unsigned num_configs) { struct exynos5440_pinctrl_priv_data *priv; void __iomem *base; - enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(config); - u32 cfg_value = PINCFG_UNPACK_VALUE(config); + enum pincfg_type cfg_type; + u32 cfg_value; u32 data; + int i; priv = pinctrl_dev_get_drvdata(pctldev); base = priv->reg_base; - switch (cfg_type) { - case PINCFG_TYPE_PUD: - /* first set pull enable/disable bit */ - data = readl(base + GPIO_PE); - data &= ~(1 << pin); - if (cfg_value) - data |= (1 << pin); - writel(data, base + GPIO_PE); - - /* then set pull up/down bit */ - data = readl(base + GPIO_PS); - data &= ~(1 << pin); - if (cfg_value == 2) - data |= (1 << pin); - writel(data, base + GPIO_PS); - break; - - case PINCFG_TYPE_DRV: - /* set the first bit of the drive strength */ - data = readl(base + GPIO_DS0); - data &= ~(1 << pin); - data |= ((cfg_value & 1) << pin); - writel(data, base + GPIO_DS0); - cfg_value >>= 1; - - /* set the second bit of the driver strength */ - data = readl(base + GPIO_DS1); - data &= ~(1 << pin); - data |= ((cfg_value & 1) << pin); - writel(data, base + GPIO_DS1); - break; - case PINCFG_TYPE_SKEW_RATE: - data = readl(base + GPIO_SR); - data &= ~(1 << pin); - data |= ((cfg_value & 1) << pin); - writel(data, base + GPIO_SR); - break; - case PINCFG_TYPE_INPUT_TYPE: - data = readl(base + GPIO_TYPE); - data &= ~(1 << pin); - data |= ((cfg_value & 1) << pin); - writel(data, base + GPIO_TYPE); - break; - default: - WARN_ON(1); - return -EINVAL; - } + for (i = 0; i < num_configs; i++) { + cfg_type = PINCFG_UNPACK_TYPE(configs[i]); + cfg_value = PINCFG_UNPACK_VALUE(configs[i]); + + switch (cfg_type) { + case PINCFG_TYPE_PUD: + /* first set pull enable/disable bit */ + data = readl(base + GPIO_PE); + data &= ~(1 << pin); + if (cfg_value) + data |= (1 << pin); + writel(data, base + GPIO_PE); + + /* then set pull up/down bit */ + data = readl(base + GPIO_PS); + data &= ~(1 << pin); + if (cfg_value == 2) + data |= (1 << pin); + writel(data, base + GPIO_PS); + break; + + case PINCFG_TYPE_DRV: + /* set the first bit of the drive strength */ + data = readl(base + GPIO_DS0); + data &= ~(1 << pin); + data |= ((cfg_value & 1) << pin); + writel(data, base + GPIO_DS0); + cfg_value >>= 1; + + /* set the second bit of the driver strength */ + data = readl(base + GPIO_DS1); + data &= ~(1 << pin); + data |= ((cfg_value & 1) << pin); + writel(data, base + GPIO_DS1); + break; + case PINCFG_TYPE_SKEW_RATE: + data = readl(base + GPIO_SR); + data &= ~(1 << pin); + data |= ((cfg_value & 1) << pin); + writel(data, base + GPIO_SR); + break; + case PINCFG_TYPE_INPUT_TYPE: + data = readl(base + GPIO_TYPE); + data &= ~(1 << pin); + data |= ((cfg_value & 1) << pin); + writel(data, base + GPIO_TYPE); + break; + default: + WARN_ON(1); + return -EINVAL; + } + } /* for each config */ return 0; } @@ -510,7 +517,8 @@ static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, /* set the pin config settings for a specified pin group */ static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long config) + unsigned group, unsigned long *configs, + unsigned num_configs) { struct exynos5440_pinctrl_priv_data *priv; const unsigned int *pins; @@ -520,7 +528,8 @@ static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev, pins = priv->pin_groups[group].pins; for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++) - exynos5440_pinconf_set(pctldev, pins[cnt], config); + exynos5440_pinconf_set(pctldev, pins[cnt], configs, + num_configs); return 0; } diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c index 4e731f24df85..2e62689b5e9f 100644 --- a/drivers/pinctrl/pinctrl-falcon.c +++ b/drivers/pinctrl/pinctrl-falcon.c @@ -238,7 +238,8 @@ static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev, } static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev, - unsigned group, unsigned long config) + unsigned group, unsigned long *configs, + unsigned num_configs) { return -ENOTSUPP; } @@ -279,39 +280,47 @@ static int falcon_pinconf_get(struct pinctrl_dev *pctrldev, } static int falcon_pinconf_set(struct pinctrl_dev *pctrldev, - unsigned pin, unsigned long config) + unsigned pin, unsigned long *configs, + unsigned num_configs) { - enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config); - int arg = LTQ_PINCONF_UNPACK_ARG(config); + enum ltq_pinconf_param param; + int arg; struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); void __iomem *mem = info->membase[PORT(pin)]; u32 reg; + int i; - switch (param) { - case LTQ_PINCONF_PARAM_DRIVE_CURRENT: - reg = LTQ_PADC_DCC; - break; - - case LTQ_PINCONF_PARAM_SLEW_RATE: - reg = LTQ_PADC_SRC; - break; - - case LTQ_PINCONF_PARAM_PULL: - if (arg == 1) - reg = LTQ_PADC_PDEN; - else - reg = LTQ_PADC_PUEN; - break; + for (i = 0; i < num_configs; i++) { + param = LTQ_PINCONF_UNPACK_PARAM(configs[i]); + arg = LTQ_PINCONF_UNPACK_ARG(configs[i]); + + switch (param) { + case LTQ_PINCONF_PARAM_DRIVE_CURRENT: + reg = LTQ_PADC_DCC; + break; + + case LTQ_PINCONF_PARAM_SLEW_RATE: + reg = LTQ_PADC_SRC; + break; + + case LTQ_PINCONF_PARAM_PULL: + if (arg == 1) + reg = LTQ_PADC_PDEN; + else + reg = LTQ_PADC_PUEN; + break; + + default: + pr_err("%s: Invalid config param %04x\n", + pinctrl_dev_get_name(pctrldev), param); + return -ENOTSUPP; + } - default: - pr_err("%s: Invalid config param %04x\n", - pinctrl_dev_get_name(pctrldev), param); - return -ENOTSUPP; - } + pad_w32(mem, BIT(PORT_PIN(pin)), reg); + if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin)))) + return -ENOTSUPP; + } /* for each config */ - pad_w32(mem, BIT(PORT_PIN(pin)), reg); - if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin)))) - return -ENOTSUPP; return 0; } diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c index 360249301315..d78dd813bff9 100644 --- a/drivers/pinctrl/pinctrl-imx.c +++ b/drivers/pinctrl/pinctrl-imx.c @@ -323,11 +323,13 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, } static int imx_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long config) + unsigned pin_id, unsigned long *configs, + unsigned num_configs) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; + int i; if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { dev_err(info->dev, "Pin(%s) does not support config function\n", @@ -338,17 +340,19 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, dev_dbg(ipctl->dev, "pinconf set pin %s\n", info->pins[pin_id].name); - if (info->flags & SHARE_MUX_CONF_REG) { - u32 reg; - reg = readl(ipctl->base + pin_reg->conf_reg); - reg &= ~0xffff; - reg |= config; - writel(reg, ipctl->base + pin_reg->conf_reg); - } else { - writel(config, ipctl->base + pin_reg->conf_reg); - } - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", - pin_reg->conf_reg, config); + for (i = 0; i < num_configs; i++) { + if (info->flags & SHARE_MUX_CONF_REG) { + u32 reg; + reg = readl(ipctl->base + pin_reg->conf_reg); + reg &= ~0xffff; + reg |= configs[i]; + writel(reg, ipctl->base + pin_reg->conf_reg); + } else { + writel(configs[i], ipctl->base + pin_reg->conf_reg); + } + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", + pin_reg->conf_reg, configs[i]); + } /* for each config */ return 0; } diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c index f5d56436ba7f..40c76f26998c 100644 --- a/drivers/pinctrl/pinctrl-mxs.c +++ b/drivers/pinctrl/pinctrl-mxs.c @@ -233,7 +233,8 @@ static int mxs_pinconf_get(struct pinctrl_dev *pctldev, } static int mxs_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long config) + unsigned pin, unsigned long *configs, + unsigned num_configs) { return -ENOTSUPP; } @@ -249,7 +250,8 @@ static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev, } static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long config) + unsigned group, unsigned long *configs, + unsigned num_configs) { struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); struct mxs_group *g = &d->soc->groups[group]; @@ -257,49 +259,56 @@ static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev, u8 ma, vol, pull, bank, shift; u16 pin; u32 i; + int n; + unsigned long config; - ma = CONFIG_TO_MA(config); - vol = CONFIG_TO_VOL(config); - pull = CONFIG_TO_PULL(config); - - for (i = 0; i < g->npins; i++) { - bank = PINID_TO_BANK(g->pins[i]); - pin = PINID_TO_PIN(g->pins[i]); - - /* drive */ - reg = d->base + d->soc->regs->drive; - reg += bank * 0x40 + pin / 8 * 0x10; - - /* mA */ - if (config & MA_PRESENT) { - shift = pin % 8 * 4; - writel(0x3 << shift, reg + CLR); - writel(ma << shift, reg + SET); - } - - /* vol */ - if (config & VOL_PRESENT) { - shift = pin % 8 * 4 + 2; - if (vol) - writel(1 << shift, reg + SET); - else - writel(1 << shift, reg + CLR); + for (n = 0; n < num_configs; n++) { + config = configs[n]; + + ma = CONFIG_TO_MA(config); + vol = CONFIG_TO_VOL(config); + pull = CONFIG_TO_PULL(config); + + for (i = 0; i < g->npins; i++) { + bank = PINID_TO_BANK(g->pins[i]); + pin = PINID_TO_PIN(g->pins[i]); + + /* drive */ + reg = d->base + d->soc->regs->drive; + reg += bank * 0x40 + pin / 8 * 0x10; + + /* mA */ + if (config & MA_PRESENT) { + shift = pin % 8 * 4; + writel(0x3 << shift, reg + CLR); + writel(ma << shift, reg + SET); + } + + /* vol */ + if (config & VOL_PRESENT) { + shift = pin % 8 * 4 + 2; + if (vol) + writel(1 << shift, reg + SET); + else + writel(1 << shift, reg + CLR); + } + + /* pull */ + if (config & PULL_PRESENT) { + reg = d->base + d->soc->regs->pull; + reg += bank * 0x10; + shift = pin; + if (pull) + writel(1 << shift, reg + SET); + else + writel(1 << shift, reg + CLR); + } } - /* pull */ - if (config & PULL_PRESENT) { - reg = d->base + d->soc->regs->pull; - reg += bank * 0x10; - shift = pin; - if (pull) - writel(1 << shift, reg + SET); - else - writel(1 << shift, reg + CLR); - } - } + /* cache the config value for mxs_pinconf_group_get() */ + g->config = config; - /* cache the config value for mxs_pinconf_group_get() */ - g->config = config; + } /* for each config */ return 0; } diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index f7c7279d081a..d7c3ae300fa7 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c @@ -1695,7 +1695,7 @@ static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, } static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config) + unsigned long *configs, unsigned num_configs) { static const char *pullnames[] = { [NMK_GPIO_PULL_NONE] = "none", @@ -1712,20 +1712,9 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, struct pinctrl_gpio_range *range; struct gpio_chip *chip; unsigned bit; - - /* - * The pin config contains pin number and altfunction fields, here - * we just ignore that part. It's being handled by the framework and - * pinmux callback respectively. - */ - pin_cfg_t cfg = (pin_cfg_t) config; - int pull = PIN_PULL(cfg); - int slpm = PIN_SLPM(cfg); - int output = PIN_DIR(cfg); - int val = PIN_VAL(cfg); - bool lowemi = PIN_LOWEMI(cfg); - bool gpiomode = PIN_GPIOMODE(cfg); - bool sleep = PIN_SLEEPMODE(cfg); + pin_cfg_t cfg; + int pull, slpm, output, val, i; + bool lowemi, gpiomode, sleep; range = nmk_match_gpio_range(pctldev, pin); if (!range) { @@ -1740,54 +1729,74 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, chip = range->gc; nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - if (sleep) { - int slpm_pull = PIN_SLPM_PULL(cfg); - int slpm_output = PIN_SLPM_DIR(cfg); - int slpm_val = PIN_SLPM_VAL(cfg); - - /* All pins go into GPIO mode at sleep */ - gpiomode = true; - + for (i = 0; i < num_configs; i++) { /* - * The SLPM_* values are normal values + 1 to allow zero to - * mean "same as normal". + * The pin config contains pin number and altfunction fields, + * here we just ignore that part. It's being handled by the + * framework and pinmux callback respectively. */ - if (slpm_pull) - pull = slpm_pull - 1; - if (slpm_output) - output = slpm_output - 1; - if (slpm_val) - val = slpm_val - 1; - - dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", - pin, - slpm_pull ? pullnames[pull] : "same", - slpm_output ? (output ? "output" : "input") : "same", - slpm_val ? (val ? "high" : "low") : "same"); - } + cfg = (pin_cfg_t) configs[i]; + pull = PIN_PULL(cfg); + slpm = PIN_SLPM(cfg); + output = PIN_DIR(cfg); + val = PIN_VAL(cfg); + lowemi = PIN_LOWEMI(cfg); + gpiomode = PIN_GPIOMODE(cfg); + sleep = PIN_SLEEPMODE(cfg); + + if (sleep) { + int slpm_pull = PIN_SLPM_PULL(cfg); + int slpm_output = PIN_SLPM_DIR(cfg); + int slpm_val = PIN_SLPM_VAL(cfg); + + /* All pins go into GPIO mode at sleep */ + gpiomode = true; + + /* + * The SLPM_* values are normal values + 1 to allow zero + * to mean "same as normal". + */ + if (slpm_pull) + pull = slpm_pull - 1; + if (slpm_output) + output = slpm_output - 1; + if (slpm_val) + val = slpm_val - 1; + + dev_dbg(nmk_chip->chip.dev, + "pin %d: sleep pull %s, dir %s, val %s\n", + pin, + slpm_pull ? pullnames[pull] : "same", + slpm_output ? (output ? "output" : "input") + : "same", + slpm_val ? (val ? "high" : "low") : "same"); + } - dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", - pin, cfg, pullnames[pull], slpmnames[slpm], - output ? "output " : "input", - output ? (val ? "high" : "low") : "", - lowemi ? "on" : "off"); + dev_dbg(nmk_chip->chip.dev, + "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", + pin, cfg, pullnames[pull], slpmnames[slpm], + output ? "output " : "input", + output ? (val ? "high" : "low") : "", + lowemi ? "on" : "off"); - clk_enable(nmk_chip->clk); - bit = pin % NMK_GPIO_PER_CHIP; - if (gpiomode) - /* No glitch when going to GPIO mode */ - __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); - if (output) - __nmk_gpio_make_output(nmk_chip, bit, val); - else { - __nmk_gpio_make_input(nmk_chip, bit); - __nmk_gpio_set_pull(nmk_chip, bit, pull); - } - /* TODO: isn't this only applicable on output pins? */ - __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); + clk_enable(nmk_chip->clk); + bit = pin % NMK_GPIO_PER_CHIP; + if (gpiomode) + /* No glitch when going to GPIO mode */ + __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); + if (output) + __nmk_gpio_make_output(nmk_chip, bit, val); + else { + __nmk_gpio_make_input(nmk_chip, bit); + __nmk_gpio_set_pull(nmk_chip, bit, pull); + } + /* TODO: isn't this only applicable on output pins? */ + __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); + + __nmk_gpio_set_slpm(nmk_chip, bit, slpm); + clk_disable(nmk_chip->clk); + } /* for each config */ - __nmk_gpio_set_slpm(nmk_chip, bit, slpm); - clk_disable(nmk_chip->clk); return 0; } diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c index 9550c33b2544..82638fac3cfa 100644 --- a/drivers/pinctrl/pinctrl-palmas.c +++ b/drivers/pinctrl/pinctrl-palmas.c @@ -854,17 +854,19 @@ static int palmas_pinconf_get(struct pinctrl_dev *pctldev, } static int palmas_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long config) + unsigned pin, unsigned long *configs, + unsigned num_configs) { struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(config); - u16 param_val = pinconf_to_config_argument(config); + enum pin_config_param param; + u16 param_val; const struct palmas_pingroup *g; const struct palmas_pin_info *opt; int ret; int base, add, mask; int rval; int group_nr; + int i; for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) { if (pci->pin_groups[group_nr].pins[0] == pin) @@ -885,70 +887,77 @@ static int palmas_pinconf_set(struct pinctrl_dev *pctldev, return -ENOTSUPP; } - switch (param) { - case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: - return 0; - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_BIAS_PULL_UP: - case PIN_CONFIG_BIAS_PULL_DOWN: - if (!opt->pud_info) { - dev_err(pci->dev, - "PULL control not supported for pin %s\n", - g->name); - return -ENOTSUPP; - } - base = opt->pud_info->pullup_dn_reg_base; - add = opt->pud_info->pullup_dn_reg_add; - mask = opt->pud_info->pullup_dn_mask; - - if (param == PIN_CONFIG_BIAS_DISABLE) - rval = opt->pud_info->normal_val; - else if (param == PIN_CONFIG_BIAS_PULL_UP) - rval = opt->pud_info->pull_up_val; - else - rval = opt->pud_info->pull_dn_val; + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + param_val = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + return 0; + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!opt->pud_info) { + dev_err(pci->dev, + "PULL control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + base = opt->pud_info->pullup_dn_reg_base; + add = opt->pud_info->pullup_dn_reg_add; + mask = opt->pud_info->pullup_dn_mask; + + if (param == PIN_CONFIG_BIAS_DISABLE) + rval = opt->pud_info->normal_val; + else if (param == PIN_CONFIG_BIAS_PULL_UP) + rval = opt->pud_info->pull_up_val; + else + rval = opt->pud_info->pull_dn_val; + + if (rval < 0) { + dev_err(pci->dev, + "PULL control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + break; - if (rval < 0) { - dev_err(pci->dev, - "PULL control not supported for pin %s\n", - g->name); + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!opt->od_info) { + dev_err(pci->dev, + "OD control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + base = opt->od_info->od_reg_base; + add = opt->od_info->od_reg_add; + mask = opt->od_info->od_mask; + if (param_val == 0) + rval = opt->od_info->od_disable; + else + rval = opt->od_info->od_enable; + if (rval < 0) { + dev_err(pci->dev, + "OD control not supported for pin %s\n", + g->name); + return -ENOTSUPP; + } + break; + default: + dev_err(pci->dev, "Properties not supported\n"); return -ENOTSUPP; } - break; - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - if (!opt->od_info) { - dev_err(pci->dev, - "OD control not supported for pin %s\n", - g->name); - return -ENOTSUPP; - } - base = opt->od_info->od_reg_base; - add = opt->od_info->od_reg_add; - mask = opt->od_info->od_mask; - if (param_val == 0) - rval = opt->od_info->od_disable; - else - rval = opt->od_info->od_enable; - if (rval < 0) { - dev_err(pci->dev, - "OD control not supported for pin %s\n", - g->name); - return -ENOTSUPP; + dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n", + __func__, base, add, mask, rval); + ret = palmas_update_bits(pci->palmas, base, add, mask, rval); + if (ret < 0) { + dev_err(pci->dev, "Reg 0x%02x update failed: %d\n", + add, ret); + return ret; } - break; - default: - dev_err(pci->dev, "Properties not supported\n"); - return -ENOTSUPP; - } + } /* for each config */ - dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n", - __func__, base, add, mask, rval); - ret = palmas_update_bits(pci->palmas, base, add, mask, rval); - if (ret < 0) { - dev_err(pci->dev, "Reg 0x%02x update failed: %d\n", add, ret); - return ret; - } return 0; } @@ -960,7 +969,8 @@ static int palmas_pinconf_group_get(struct pinctrl_dev *pctldev, } static int palmas_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long config) + unsigned group, unsigned long *configs, + unsigned num_configs) { dev_err(pctldev->dev, "palmas_pinconf_group_set op not supported\n"); return -ENOTSUPP; diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 51a7c24981d1..abff5895e81f 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -574,32 +574,45 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, /* set the pin config settings for a specified pin */ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long config) + unsigned long *configs, unsigned num_configs) { struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); struct rockchip_pin_bank *bank = pin_to_bank(info, pin); - enum pin_config_param param = pinconf_to_config_param(config); - u16 arg = pinconf_to_config_argument(config); - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - return rockchip_set_pull(bank, pin - bank->pin_base, param); - break; - case PIN_CONFIG_BIAS_PULL_UP: - case PIN_CONFIG_BIAS_PULL_DOWN: - case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: - if (!rockchip_pinconf_pull_valid(info->ctrl, param)) + enum pin_config_param param; + u16 arg; + int i; + int rc; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + rc = rockchip_set_pull(bank, pin - bank->pin_base, + param); + if (rc) + return rc; + break; + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + if (!rockchip_pinconf_pull_valid(info->ctrl, param)) + return -ENOTSUPP; + + if (!arg) + return -EINVAL; + + rc = rockchip_set_pull(bank, pin - bank->pin_base, + param); + if (rc) + return rc; + break; + default: return -ENOTSUPP; - - if (!arg) - return -EINVAL; - - return rockchip_set_pull(bank, pin - bank->pin_base, param); - break; - default: - return -ENOTSUPP; - break; - } + break; + } + } /* for each config */ return 0; } diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index 439f2ef680df..222648d69f25 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -442,9 +442,17 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin, /* set the pin config settings for a specified pin */ static int samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long config) + unsigned long *configs, unsigned num_configs) { - return samsung_pinconf_rw(pctldev, pin, &config, true); + int i, ret; + + for (i = 0; i < num_configs; i++) { + ret = samsung_pinconf_rw(pctldev, pin, &configs[i], true); + if (ret < 0) + return ret; + } /* for each config */ + + return 0; } /* get the pin config settings for a specified pin */ @@ -456,7 +464,8 @@ static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, /* set the pin config settings for a specified pin group */ static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long config) + unsigned group, unsigned long *configs, + unsigned num_configs) { struct samsung_pinctrl_drv_data *drvdata; const unsigned int *pins; @@ -466,7 +475,7 @@ static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev, pins = drvdata->pin_groups[group].pins; for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) - samsung_pinconf_set(pctldev, pins[cnt], config); + samsung_pinconf_set(pctldev, pins[cnt], configs, num_configs); return 0; } diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 6866548fab31..8f31768c665d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -209,7 +209,7 @@ struct pcs_device { static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config); static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config); + unsigned long *configs, unsigned num_configs); static enum pin_config_param pcs_bias[] = { PIN_CONFIG_BIAS_PULL_DOWN, @@ -536,7 +536,7 @@ static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin) int i; for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { config = pinconf_to_config_packed(pcs_bias[i], 0); - pcs_pinconf_set(pctldev, pin, config); + pcs_pinconf_set(pctldev, pin, &config, 1); } } @@ -622,22 +622,28 @@ static int pcs_pinconf_get(struct pinctrl_dev *pctldev, } static int pcs_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long config) + unsigned pin, unsigned long *configs, + unsigned num_configs) { struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); struct pcs_function *func; unsigned offset = 0, shift = 0, i, data, ret; u16 arg; + int j; ret = pcs_get_function(pctldev, pin, &func); if (ret) return ret; - for (i = 0; i < func->nconfs; i++) { - if (pinconf_to_config_param(config) == func->conf[i].param) { + for (j = 0; j < num_configs; j++) { + for (i = 0; i < func->nconfs; i++) { + if (pinconf_to_config_param(configs[j]) + != func->conf[i].param) + continue; + offset = pin * (pcs->width / BITS_PER_BYTE); data = pcs->read(pcs->base + offset); - arg = pinconf_to_config_argument(config); + arg = pinconf_to_config_argument(configs[j]); switch (func->conf[i].param) { /* 2 parameters */ case PIN_CONFIG_INPUT_SCHMITT: @@ -667,10 +673,14 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev, return -ENOTSUPP; } pcs->write(data, pcs->base + offset); - return 0; + + break; } - } - return -ENOTSUPP; + if (i >= func->nconfs) + return -ENOTSUPP; + } /* for each config */ + + return 0; } static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, @@ -695,7 +705,8 @@ static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, } static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long config) + unsigned group, unsigned long *configs, + unsigned num_configs) { const unsigned *pins; unsigned npins; @@ -705,7 +716,7 @@ static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, if (ret) return ret; for (i = 0; i < npins; i++) { - if (pcs_pinconf_set(pctldev, pins[i], config)) + if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs)) return -ENOTSUPP; } return 0; diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 2a10a318b648..9cadc68ee572 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -909,15 +909,18 @@ static void st_pinconf_set_retime(struct st_pinctrl *info, config, pin); } -static int st_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long config) +static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id, + unsigned long *configs, unsigned num_configs) { int pin = st_gpio_pin(pin_id); struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); + int i; - st_pinconf_set_config(pc, pin, config); - st_pinconf_set_retime(info, pc, pin, config); + for (i = 0; i < num_configs; i++) { + st_pinconf_set_config(pc, pin, configs[i]); + st_pinconf_set_retime(info, pc, pin, configs[i]); + } /* for each config */ return 0; } diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c index d251c76c2e62..8dbd465b01d3 100644 --- a/drivers/pinctrl/pinctrl-sunxi.c +++ b/drivers/pinctrl/pinctrl-sunxi.c @@ -274,50 +274,55 @@ static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, - unsigned long config) + unsigned long *configs, + unsigned num_configs) { struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct sunxi_pinctrl_group *g = &pctl->groups[group]; u32 val, mask; u16 strength; u8 dlevel; + int i; - switch (pinconf_to_config_param(config)) { - case PIN_CONFIG_DRIVE_STRENGTH: - strength = pinconf_to_config_argument(config); - if (strength > 40) - return -EINVAL; - /* - * We convert from mA to what the register expects: - * 0: 10mA - * 1: 20mA - * 2: 30mA - * 3: 40mA - */ - dlevel = strength / 10 - 1; - val = readl(pctl->membase + sunxi_dlevel_reg(g->pin)); - mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin); - writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin), - pctl->membase + sunxi_dlevel_reg(g->pin)); - break; - case PIN_CONFIG_BIAS_PULL_UP: - val = readl(pctl->membase + sunxi_pull_reg(g->pin)); - mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); - writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin), - pctl->membase + sunxi_pull_reg(g->pin)); - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - val = readl(pctl->membase + sunxi_pull_reg(g->pin)); - mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); - writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin), - pctl->membase + sunxi_pull_reg(g->pin)); - break; - default: - break; - } + for (i = 0; i < num_configs; i++) { + switch (pinconf_to_config_param(configs[i])) { + case PIN_CONFIG_DRIVE_STRENGTH: + strength = pinconf_to_config_argument(configs[i]); + if (strength > 40) + return -EINVAL; + /* + * We convert from mA to what the register expects: + * 0: 10mA + * 1: 20mA + * 2: 30mA + * 3: 40mA + */ + dlevel = strength / 10 - 1; + val = readl(pctl->membase + sunxi_dlevel_reg(g->pin)); + mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin); + writel((val & ~mask) + | dlevel << sunxi_dlevel_offset(g->pin), + pctl->membase + sunxi_dlevel_reg(g->pin)); + break; + case PIN_CONFIG_BIAS_PULL_UP: + val = readl(pctl->membase + sunxi_pull_reg(g->pin)); + mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); + writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin), + pctl->membase + sunxi_pull_reg(g->pin)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + val = readl(pctl->membase + sunxi_pull_reg(g->pin)); + mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); + writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin), + pctl->membase + sunxi_pull_reg(g->pin)); + break; + default: + break; + } - /* cache the config value */ - g->config = config; + /* cache the config value */ + g->config = configs[i]; + } /* for each config */ return 0; } diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c index be7e900fb298..a2e93a2b5ff4 100644 --- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/pinctrl-tegra.c @@ -436,7 +436,8 @@ static int tegra_pinconf_get(struct pinctrl_dev *pctldev, } static int tegra_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long config) + unsigned pin, unsigned long *configs, + unsigned num_configs) { dev_err(pctldev->dev, "pin_config_set op not supported\n"); return -ENOTSUPP; @@ -471,51 +472,57 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, } static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long config) + unsigned group, unsigned long *configs, + unsigned num_configs) { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config); - u16 arg = TEGRA_PINCONF_UNPACK_ARG(config); + enum tegra_pinconf_param param; + u16 arg; const struct tegra_pingroup *g; - int ret; + int ret, i; s8 bank, bit, width; s16 reg; u32 val, mask; g = &pmx->soc->groups[group]; - ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, - &width); - if (ret < 0) - return ret; + for (i = 0; i < num_configs; i++) { + param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]); + arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]); - val = pmx_readl(pmx, bank, reg); + ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, + &width); + if (ret < 0) + return ret; - /* LOCK can't be cleared */ - if (param == TEGRA_PINCONF_PARAM_LOCK) { - if ((val & BIT(bit)) && !arg) { - dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); - return -EINVAL; + val = pmx_readl(pmx, bank, reg); + + /* LOCK can't be cleared */ + if (param == TEGRA_PINCONF_PARAM_LOCK) { + if ((val & BIT(bit)) && !arg) { + dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); + return -EINVAL; + } } - } - /* Special-case Boolean values; allow any non-zero as true */ - if (width == 1) - arg = !!arg; + /* Special-case Boolean values; allow any non-zero as true */ + if (width == 1) + arg = !!arg; - /* Range-check user-supplied value */ - mask = (1 << width) - 1; - if (arg & ~mask) { - dev_err(pctldev->dev, - "config %lx: %x too big for %d bit register\n", - config, arg, width); - return -EINVAL; - } + /* Range-check user-supplied value */ + mask = (1 << width) - 1; + if (arg & ~mask) { + dev_err(pctldev->dev, + "config %lx: %x too big for %d bit register\n", + configs[i], arg, width); + return -EINVAL; + } - /* Update register */ - val &= ~(mask << bit); - val |= arg << bit; - pmx_writel(pmx, val, bank, reg); + /* Update register */ + val &= ~(mask << bit); + val |= arg << bit; + pmx_writel(pmx, val, bank, reg); + } /* for each config */ return 0; } diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c index 494ad4b83264..5bf01c28925e 100644 --- a/drivers/pinctrl/pinctrl-tz1090-pdc.c +++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c @@ -737,39 +737,46 @@ static int tz1090_pdc_pinconf_get(struct pinctrl_dev *pctldev, } static int tz1090_pdc_pinconf_set(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long config) + unsigned int pin, unsigned long *configs, + unsigned num_configs) { struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(config); - unsigned int arg = pinconf_to_config_argument(config); + enum pin_config_param param; + unsigned int arg; int ret; u32 reg, width, mask, shift, val, tmp; unsigned long flags; + int i; - dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", - __func__, tz1090_pdc_pins[pin].name, config); + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); - /* Get register information */ - ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, - ®, &width, &mask, &shift, &val); - if (ret < 0) - return ret; + dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", + __func__, tz1090_pdc_pins[pin].name, configs[i]); - /* Unpack argument and range check it */ - if (arg > 1) { - dev_dbg(pctldev->dev, "%s: arg %u out of range\n", - __func__, arg); - return -EINVAL; - } + /* Get register information */ + ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, + ®, &width, &mask, &shift, &val); + if (ret < 0) + return ret; - /* Write register field */ - __global_lock2(flags); - tmp = pmx_read(pmx, reg); - tmp &= ~mask; - if (arg) - tmp |= val << shift; - pmx_write(pmx, tmp, reg); - __global_unlock2(flags); + /* Unpack argument and range check it */ + if (arg > 1) { + dev_dbg(pctldev->dev, "%s: arg %u out of range\n", + __func__, arg); + return -EINVAL; + } + + /* Write register field */ + __global_lock2(flags); + tmp = pmx_read(pmx, reg); + tmp &= ~mask; + if (arg) + tmp |= val << shift; + pmx_write(pmx, tmp, reg); + __global_unlock2(flags); + } /* for each config */ return 0; } @@ -860,54 +867,68 @@ static int tz1090_pdc_pinconf_group_get(struct pinctrl_dev *pctldev, static int tz1090_pdc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned int group, - unsigned long config) + unsigned long *configs, + unsigned num_configs) { struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group]; - enum pin_config_param param = pinconf_to_config_param(config); + enum pin_config_param param; const unsigned int *pit; unsigned int i; int ret, arg; u32 reg, width, mask, shift, val; unsigned long flags; const int *map; + int j; - dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n", - __func__, g->name, config); + for (j = 0; j < num_configs; j++) { + param = pinconf_to_config_param(configs[j]); - /* Get register information */ - ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true, - ®, &width, &mask, &shift, &map); - if (ret < 0) { - /* - * Maybe we're trying to set a per-pin configuration of a group, - * so do the pins one by one. This is mainly as a convenience. - */ - for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) { - ret = tz1090_pdc_pinconf_set(pctldev, *pit, config); - if (ret) - return ret; - } - return 0; - } + dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n", + __func__, g->name, configs[j]); - /* Unpack argument and map it to register value */ - arg = pinconf_to_config_argument(config); - for (i = 0; i < BIT(width); ++i) { - if (map[i] == arg || (map[i] == -EINVAL && !arg)) { - /* Write register field */ - __global_lock2(flags); - val = pmx_read(pmx, reg); - val &= ~mask; - val |= i << shift; - pmx_write(pmx, val, reg); - __global_unlock2(flags); + /* Get register information */ + ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true, + ®, &width, &mask, &shift, + &map); + if (ret < 0) { + /* + * Maybe we're trying to set a per-pin configuration + * of a group, so do the pins one by one. This is + * mainly as a convenience. + */ + for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) { + ret = tz1090_pdc_pinconf_set(pctldev, *pit, + configs, num_configs); + if (ret) + return ret; + } return 0; } - } - dev_dbg(pctldev->dev, "%s: arg %u not supported\n", - __func__, arg); + /* Unpack argument and map it to register value */ + arg = pinconf_to_config_argument(configs[j]); + for (i = 0; i < BIT(width); ++i) { + if (map[i] == arg || (map[i] == -EINVAL && !arg)) { + /* Write register field */ + __global_lock2(flags); + val = pmx_read(pmx, reg); + val &= ~mask; + val |= i << shift; + pmx_write(pmx, val, reg); + __global_unlock2(flags); + goto next_config; + } + } + + dev_dbg(pctldev->dev, "%s: arg %u not supported\n", + __func__, arg); + return 0; + +next_config: + ; + } /* for each config */ + return 0; } diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c index 72d955252e41..bc9cd7a7602e 100644 --- a/drivers/pinctrl/pinctrl-tz1090.c +++ b/drivers/pinctrl/pinctrl-tz1090.c @@ -1762,39 +1762,46 @@ static int tz1090_pinconf_get(struct pinctrl_dev *pctldev, } static int tz1090_pinconf_set(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long config) + unsigned int pin, unsigned long *configs, + unsigned num_configs) { struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(config); - unsigned int arg = pinconf_to_config_argument(config); + enum pin_config_param param; + unsigned int arg; int ret; u32 reg, width, mask, shift, val, tmp; unsigned long flags; + int i; - dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", - __func__, tz1090_pins[pin].name, config); + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); - /* Get register information */ - ret = tz1090_pinconf_reg(pctldev, pin, param, true, - ®, &width, &mask, &shift, &val); - if (ret < 0) - return ret; + dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", + __func__, tz1090_pins[pin].name, configs[i]); - /* Unpack argument and range check it */ - if (arg > 1) { - dev_dbg(pctldev->dev, "%s: arg %u out of range\n", - __func__, arg); - return -EINVAL; - } + /* Get register information */ + ret = tz1090_pinconf_reg(pctldev, pin, param, true, + ®, &width, &mask, &shift, &val); + if (ret < 0) + return ret; - /* Write register field */ - __global_lock2(flags); - tmp = pmx_read(pmx, reg); - tmp &= ~mask; - if (arg) - tmp |= val << shift; - pmx_write(pmx, tmp, reg); - __global_unlock2(flags); + /* Unpack argument and range check it */ + if (arg > 1) { + dev_dbg(pctldev->dev, "%s: arg %u out of range\n", + __func__, arg); + return -EINVAL; + } + + /* Write register field */ + __global_lock2(flags); + tmp = pmx_read(pmx, reg); + tmp &= ~mask; + if (arg) + tmp |= val << shift; + pmx_write(pmx, tmp, reg); + __global_unlock2(flags); + } /* for each config */ return 0; } @@ -1894,68 +1901,81 @@ static int tz1090_pinconf_group_get(struct pinctrl_dev *pctldev, } static int tz1090_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned int group, unsigned long config) + unsigned int group, unsigned long *configs, + unsigned num_configs) { struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); const struct tz1090_pingroup *g; - enum pin_config_param param = pinconf_to_config_param(config); + enum pin_config_param param; unsigned int arg, pin, i; const unsigned int *pit; int ret; u32 reg, width, mask, shift, val; unsigned long flags; const int *map; + int j; if (group >= ARRAY_SIZE(tz1090_groups)) { pin = group - ARRAY_SIZE(tz1090_groups); - return tz1090_pinconf_set(pctldev, pin, config); + return tz1090_pinconf_set(pctldev, pin, configs, num_configs); } g = &tz1090_groups[group]; if (g->npins == 1) { pin = g->pins[0]; - ret = tz1090_pinconf_set(pctldev, pin, config); + ret = tz1090_pinconf_set(pctldev, pin, configs, num_configs); if (ret != -ENOTSUPP) return ret; } - dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n", - __func__, g->name, config); + for (j = 0; j < num_configs; j++) { + param = pinconf_to_config_param(configs[j]); - /* Get register information */ - ret = tz1090_pinconf_group_reg(pctldev, g, param, true, - ®, &width, &mask, &shift, &map); - if (ret < 0) { - /* - * Maybe we're trying to set a per-pin configuration of a group, - * so do the pins one by one. This is mainly as a convenience. - */ - for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) { - ret = tz1090_pinconf_set(pctldev, *pit, config); - if (ret) - return ret; - } - return 0; - } + dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n", + __func__, g->name, configs[j]); - /* Unpack argument and map it to register value */ - arg = pinconf_to_config_argument(config); - for (i = 0; i < BIT(width); ++i) { - if (map[i] == arg || (map[i] == -EINVAL && !arg)) { - /* Write register field */ - __global_lock2(flags); - val = pmx_read(pmx, reg); - val &= ~mask; - val |= i << shift; - pmx_write(pmx, val, reg); - __global_unlock2(flags); + /* Get register information */ + ret = tz1090_pinconf_group_reg(pctldev, g, param, true, ®, + &width, &mask, &shift, &map); + if (ret < 0) { + /* + * Maybe we're trying to set a per-pin configuration + * of a group, so do the pins one by one. This is + * mainly as a convenience. + */ + for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) { + ret = tz1090_pinconf_set(pctldev, *pit, configs, + num_configs); + if (ret) + return ret; + } return 0; } - } - dev_dbg(pctldev->dev, "%s: arg %u not supported\n", - __func__, arg); - return -EINVAL; + /* Unpack argument and map it to register value */ + arg = pinconf_to_config_argument(configs[j]); + for (i = 0; i < BIT(width); ++i) { + if (map[i] == arg || (map[i] == -EINVAL && !arg)) { + /* Write register field */ + __global_lock2(flags); + val = pmx_read(pmx, reg); + val &= ~mask; + val |= i << shift; + pmx_write(pmx, val, reg); + __global_unlock2(flags); + goto next_config; + } + } + + dev_dbg(pctldev->dev, "%s: arg %u not supported\n", + __func__, arg); + return -EINVAL; + +next_config: + ; + } /* for each config */ + + return 0; } static struct pinconf_ops tz1090_pinconf_ops = { diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c index 6fbdc06d2998..209a01b8bd3b 100644 --- a/drivers/pinctrl/pinctrl-u300.c +++ b/drivers/pinctrl/pinctrl-u300.c @@ -1027,21 +1027,23 @@ static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, } static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config) + unsigned long *configs, unsigned num_configs) { struct pinctrl_gpio_range *range = pinctrl_find_gpio_range_from_pin(pctldev, pin); - int ret; + int ret, i; if (!range) return -EINVAL; - /* Note: none of these configurations take any argument */ - ret = u300_gpio_config_set(range->gc, - (pin - range->pin_base + range->base), - pinconf_to_config_param(config)); - if (ret) - return ret; + for (i = 0; i < num_configs; i++) { + /* Note: none of these configurations take any argument */ + ret = u300_gpio_config_set(range->gc, + (pin - range->pin_base + range->base), + pinconf_to_config_param(configs[i])); + if (ret) + return ret; + } /* for each config */ return 0; } diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c index 86c8cf82105b..ed2d1ba69cef 100644 --- a/drivers/pinctrl/pinctrl-xway.c +++ b/drivers/pinctrl/pinctrl-xway.c @@ -499,74 +499,101 @@ static int xway_pinconf_get(struct pinctrl_dev *pctldev, static int xway_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config) + unsigned long *configs, + unsigned num_configs) { struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); - enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config); - int arg = LTQ_PINCONF_UNPACK_ARG(config); + enum ltq_pinconf_param param; + int arg; int port = PORT(pin); u32 reg; + int i; + + for (i = 0; i < num_configs; i++) { + param = LTQ_PINCONF_UNPACK_PARAM(configs[i]); + arg = LTQ_PINCONF_UNPACK_ARG(configs[i]); + + switch (param) { + case LTQ_PINCONF_PARAM_OPEN_DRAIN: + if (port == PORT3) + reg = GPIO3_OD; + else + reg = GPIO_OD(pin); + if (arg == 0) + gpio_setbit(info->membase[0], + reg, + PORT_PIN(pin)); + else + gpio_clearbit(info->membase[0], + reg, + PORT_PIN(pin)); + break; - switch (param) { - case LTQ_PINCONF_PARAM_OPEN_DRAIN: - if (port == PORT3) - reg = GPIO3_OD; - else - reg = GPIO_OD(pin); - if (arg == 0) + case LTQ_PINCONF_PARAM_PULL: + if (port == PORT3) + reg = GPIO3_PUDEN; + else + reg = GPIO_PUDEN(pin); + if (arg == 0) { + gpio_clearbit(info->membase[0], + reg, + PORT_PIN(pin)); + break; + } gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); - else - gpio_clearbit(info->membase[0], reg, PORT_PIN(pin)); - break; - case LTQ_PINCONF_PARAM_PULL: - if (port == PORT3) - reg = GPIO3_PUDEN; - else - reg = GPIO_PUDEN(pin); - if (arg == 0) { - gpio_clearbit(info->membase[0], reg, PORT_PIN(pin)); + if (port == PORT3) + reg = GPIO3_PUDSEL; + else + reg = GPIO_PUDSEL(pin); + if (arg == 1) + gpio_clearbit(info->membase[0], + reg, + PORT_PIN(pin)); + else if (arg == 2) + gpio_setbit(info->membase[0], + reg, + PORT_PIN(pin)); + else + dev_err(pctldev->dev, + "Invalid pull value %d\n", arg); break; - } - gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); - if (port == PORT3) - reg = GPIO3_PUDSEL; - else - reg = GPIO_PUDSEL(pin); - if (arg == 1) - gpio_clearbit(info->membase[0], reg, PORT_PIN(pin)); - else if (arg == 2) - gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); - else - dev_err(pctldev->dev, "Invalid pull value %d\n", arg); - break; + case LTQ_PINCONF_PARAM_OUTPUT: + reg = GPIO_DIR(pin); + if (arg == 0) + gpio_clearbit(info->membase[0], + reg, + PORT_PIN(pin)); + else + gpio_setbit(info->membase[0], + reg, + PORT_PIN(pin)); + break; - case LTQ_PINCONF_PARAM_OUTPUT: - reg = GPIO_DIR(pin); - if (arg == 0) - gpio_clearbit(info->membase[0], reg, PORT_PIN(pin)); - else - gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); - break; + default: + dev_err(pctldev->dev, + "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + } /* for each config */ - default: - dev_err(pctldev->dev, "Invalid config param %04x\n", param); - return -ENOTSUPP; - } return 0; } int xway_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned selector, - unsigned long config) + unsigned long *configs, + unsigned num_configs) { struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); int i, ret = 0; for (i = 0; i < info->grps[selector].npins && !ret; i++) ret = xway_pinconf_set(pctldev, - info->grps[selector].pins[i], config); + info->grps[selector].pins[i], + configs, + num_configs); return ret; } diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 8649ec3910a3..e758af95c209 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -529,38 +529,44 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, } static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, - unsigned long config) + unsigned long *configs, unsigned num_configs) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; - enum pin_config_param param = pinconf_to_config_param(config); + enum pin_config_param param; unsigned long flags; + unsigned int i; - if (!sh_pfc_pinconf_validate(pfc, _pin, param)) - return -ENOTSUPP; + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - case PIN_CONFIG_BIAS_PULL_DOWN: - case PIN_CONFIG_BIAS_DISABLE: - if (!pfc->info->ops || !pfc->info->ops->set_bias) + if (!sh_pfc_pinconf_validate(pfc, _pin, param)) return -ENOTSUPP; - spin_lock_irqsave(&pfc->lock, flags); - pfc->info->ops->set_bias(pfc, _pin, param); - spin_unlock_irqrestore(&pfc->lock, flags); + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_DISABLE: + if (!pfc->info->ops || !pfc->info->ops->set_bias) + return -ENOTSUPP; - break; + spin_lock_irqsave(&pfc->lock, flags); + pfc->info->ops->set_bias(pfc, _pin, param); + spin_unlock_irqrestore(&pfc->lock, flags); - default: - return -ENOTSUPP; - } + break; + + default: + return -ENOTSUPP; + } + } /* for each config */ return 0; } static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, - unsigned long config) + unsigned long *configs, + unsigned num_configs) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); const unsigned int *pins; @@ -571,7 +577,7 @@ static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, num_pins = pmx->pfc->info->groups[group].nr_pins; for (i = 0; i < num_pins; ++i) - sh_pfc_pinconf_set(pctldev, pins[i], config); + sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs); return 0; } diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c index 0cc4335bc0f2..39aec0850810 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wmt.c +++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c @@ -424,15 +424,16 @@ static int wmt_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, } static int wmt_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config) + unsigned long *configs, unsigned num_configs) { struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(config); - u16 arg = pinconf_to_config_argument(config); + enum pin_config_param param; + u16 arg; u32 bank = WMT_BANK_FROM_PIN(pin); u32 bit = WMT_BIT_FROM_PIN(pin); u32 reg_pull_en = data->banks[bank].reg_pull_en; u32 reg_pull_cfg = data->banks[bank].reg_pull_cfg; + int i; if ((reg_pull_en == NO_REG) || (reg_pull_cfg == NO_REG)) { dev_err(data->dev, "bias functions not supported on pin %d\n", @@ -440,28 +441,33 @@ static int wmt_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, return -EINVAL; } - if ((param == PIN_CONFIG_BIAS_PULL_DOWN) || - (param == PIN_CONFIG_BIAS_PULL_UP)) { - if (arg == 0) - param = PIN_CONFIG_BIAS_DISABLE; - } + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - wmt_clearbits(data, reg_pull_en, BIT(bit)); - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - wmt_clearbits(data, reg_pull_cfg, BIT(bit)); - wmt_setbits(data, reg_pull_en, BIT(bit)); - break; - case PIN_CONFIG_BIAS_PULL_UP: - wmt_setbits(data, reg_pull_cfg, BIT(bit)); - wmt_setbits(data, reg_pull_en, BIT(bit)); - break; - default: - dev_err(data->dev, "unknown pinconf param\n"); - return -EINVAL; - } + if ((param == PIN_CONFIG_BIAS_PULL_DOWN) || + (param == PIN_CONFIG_BIAS_PULL_UP)) { + if (arg == 0) + param = PIN_CONFIG_BIAS_DISABLE; + } + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + wmt_clearbits(data, reg_pull_en, BIT(bit)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + wmt_clearbits(data, reg_pull_cfg, BIT(bit)); + wmt_setbits(data, reg_pull_en, BIT(bit)); + break; + case PIN_CONFIG_BIAS_PULL_UP: + wmt_setbits(data, reg_pull_cfg, BIT(bit)); + wmt_setbits(data, reg_pull_en, BIT(bit)); + break; + default: + dev_err(data->dev, "unknown pinconf param\n"); + return -EINVAL; + } + } /* for each config */ return 0; } diff --git a/include/linux/pinctrl/pinconf.h b/include/linux/pinctrl/pinconf.h index f6998692bdc9..09eb80f2574a 100644 --- a/include/linux/pinctrl/pinconf.h +++ b/include/linux/pinctrl/pinconf.h @@ -47,13 +47,15 @@ struct pinconf_ops { unsigned long *config); int (*pin_config_set) (struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config); + unsigned long *configs, + unsigned num_configs); int (*pin_config_group_get) (struct pinctrl_dev *pctldev, unsigned selector, unsigned long *config); int (*pin_config_group_set) (struct pinctrl_dev *pctldev, unsigned selector, - unsigned long config); + unsigned long *configs, + unsigned num_configs); int (*pin_config_dbg_parse_modify) (struct pinctrl_dev *pctldev, const char *arg, unsigned long *config); -- cgit v1.2.3