From d672d0b0828181069a933edfd0184071b822acd6 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Wed, 2 Oct 2002 21:02:43 -0700 Subject: [SPARC64]: header cleanup, extern inline --> static inline --- include/asm-sparc64/checksum.h | 14 +++---- include/asm-sparc64/delay.h | 4 +- include/asm-sparc64/fpumacro.h | 4 +- include/asm-sparc64/irq.h | 6 +-- include/asm-sparc64/page.h | 2 +- include/asm-sparc64/pci.h | 4 +- include/asm-sparc64/pgtable.h | 10 ++--- include/asm-sparc64/psrcompat.h | 4 +- include/asm-sparc64/sbus.h | 4 +- include/asm-sparc64/siginfo.h | 2 +- include/asm-sparc64/smp.h | 4 +- include/asm-sparc64/spinlock.h | 6 +-- include/asm-sparc64/spitfire.h | 86 ++++++++++++++++++++--------------------- include/asm-sparc64/system.h | 8 ++-- include/asm-sparc64/uaccess.h | 4 +- include/asm-sparc64/upa.h | 16 ++++---- include/asm-sparc64/visasm.h | 2 +- 17 files changed, 90 insertions(+), 90 deletions(-) (limited to 'include') diff --git a/include/asm-sparc64/checksum.h b/include/asm-sparc64/checksum.h index 6128f20a8f1e..6cfa55be0f09 100644 --- a/include/asm-sparc64/checksum.h +++ b/include/asm-sparc64/checksum.h @@ -40,7 +40,7 @@ extern unsigned int csum_partial(const unsigned char * buff, int len, unsigned i */ extern unsigned int csum_partial_copy_sparc64(const char *src, char *dst, int len, unsigned int sum); -extern __inline__ unsigned int +static __inline__ unsigned int csum_partial_copy_nocheck (const char *src, char *dst, int len, unsigned int sum) { @@ -52,7 +52,7 @@ csum_partial_copy_nocheck (const char *src, char *dst, int len, return ret; } -extern __inline__ unsigned int +static __inline__ unsigned int csum_partial_copy_from_user(const char *src, char *dst, int len, unsigned int sum, int *err) { @@ -66,7 +66,7 @@ csum_partial_copy_from_user(const char *src, char *dst, int len, */ #define HAVE_CSUM_COPY_USER extern unsigned int csum_partial_copy_user_sparc64(const char *src, char *dst, int len, unsigned int sum); -extern __inline__ unsigned int +static __inline__ unsigned int csum_and_copy_to_user(const char *src, char *dst, int len, unsigned int sum, int *err) { @@ -78,7 +78,7 @@ csum_and_copy_to_user(const char *src, char *dst, int len, /* ihl is always 5 or greater, almost always is 5, and iph is word aligned * the majority of the time. */ -extern __inline__ unsigned short ip_fast_csum(__const__ unsigned char *iph, +static __inline__ unsigned short ip_fast_csum(__const__ unsigned char *iph, unsigned int ihl) { unsigned short sum; @@ -119,7 +119,7 @@ extern __inline__ unsigned short ip_fast_csum(__const__ unsigned char *iph, } /* Fold a partial checksum without adding pseudo headers. */ -extern __inline__ unsigned short csum_fold(unsigned int sum) +static __inline__ unsigned short csum_fold(unsigned int sum) { unsigned int tmp; @@ -134,7 +134,7 @@ extern __inline__ unsigned short csum_fold(unsigned int sum) return (sum & 0xffff); } -extern __inline__ unsigned long csum_tcpudp_nofold(unsigned long saddr, +static __inline__ unsigned long csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr, unsigned int len, unsigned short proto, @@ -201,7 +201,7 @@ static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr, } /* this routine is used for miscellaneous IP-like checksums, mainly in icmp.c */ -extern __inline__ unsigned short ip_compute_csum(unsigned char * buff, int len) +static __inline__ unsigned short ip_compute_csum(unsigned char * buff, int len) { return csum_fold(csum_partial(buff, len, 0)); } diff --git a/include/asm-sparc64/delay.h b/include/asm-sparc64/delay.h index 400c5eb3d8a3..90bf4b469138 100644 --- a/include/asm-sparc64/delay.h +++ b/include/asm-sparc64/delay.h @@ -18,7 +18,7 @@ extern unsigned long loops_per_jiffy; #endif -extern __inline__ void __delay(unsigned long loops) +static __inline__ void __delay(unsigned long loops) { __asm__ __volatile__( " b,pt %%xcc, 1f\n" @@ -32,7 +32,7 @@ extern __inline__ void __delay(unsigned long loops) : "cc"); } -extern __inline__ void __udelay(unsigned long usecs, unsigned long lps) +static __inline__ void __udelay(unsigned long usecs, unsigned long lps) { usecs *= 0x00000000000010c6UL; /* 2**32 / 1000000 */ diff --git a/include/asm-sparc64/fpumacro.h b/include/asm-sparc64/fpumacro.h index 21d2740a810b..d583e5efd75d 100644 --- a/include/asm-sparc64/fpumacro.h +++ b/include/asm-sparc64/fpumacro.h @@ -16,7 +16,7 @@ struct fpustate { #define FPUSTATE (struct fpustate *)(current_thread_info()->fpregs) -extern __inline__ unsigned long fprs_read(void) +static __inline__ unsigned long fprs_read(void) { unsigned long retval; @@ -25,7 +25,7 @@ extern __inline__ unsigned long fprs_read(void) return retval; } -extern __inline__ void fprs_write(unsigned long val) +static __inline__ void fprs_write(unsigned long val) { __asm__ __volatile__("wr %0, 0x0, %%fprs" : : "r" (val)); } diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h index cebf5b5a99e1..a56c528e9af4 100644 --- a/include/asm-sparc64/irq.h +++ b/include/asm-sparc64/irq.h @@ -133,21 +133,21 @@ extern int request_fast_irq(unsigned int irq, unsigned long flags, __const__ char *devname, void *dev_id); -extern __inline__ void set_softint(unsigned long bits) +static __inline__ void set_softint(unsigned long bits) { __asm__ __volatile__("wr %0, 0x0, %%set_softint" : /* No outputs */ : "r" (bits)); } -extern __inline__ void clear_softint(unsigned long bits) +static __inline__ void clear_softint(unsigned long bits) { __asm__ __volatile__("wr %0, 0x0, %%clear_softint" : /* No outputs */ : "r" (bits)); } -extern __inline__ unsigned long get_softint(void) +static __inline__ unsigned long get_softint(void) { unsigned long retval; diff --git a/include/asm-sparc64/page.h b/include/asm-sparc64/page.h index df6a1057484a..2fbe2fc42a63 100644 --- a/include/asm-sparc64/page.h +++ b/include/asm-sparc64/page.h @@ -161,7 +161,7 @@ struct sparc_phys_banks { extern struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS]; /* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) +static __inline__ int get_order(unsigned long size) { int order; diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h index 884102954ceb..79c738565f5d 100644 --- a/include/asm-sparc64/pci.h +++ b/include/asm-sparc64/pci.h @@ -17,12 +17,12 @@ #define PCI_IRQ_NONE 0xffffffff -extern inline void pcibios_set_master(struct pci_dev *dev) +static inline void pcibios_set_master(struct pci_dev *dev) { /* No special bus mastering setup handling */ } -extern inline void pcibios_penalize_isa_irq(int irq) +static inline void pcibios_penalize_isa_irq(int irq) { /* We don't do dynamic PCI IRQ allocation */ } diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h index f36f6b02c24d..453d7540e16c 100644 --- a/include/asm-sparc64/pgtable.h +++ b/include/asm-sparc64/pgtable.h @@ -212,7 +212,7 @@ extern struct page *mem_map_zero; #define page_pte_prot(page, prot) mk_pte(page, prot) #define page_pte(page) page_pte_prot(page, __pgprot(0)) -extern inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot) +static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot) { pte_t __pte; @@ -291,7 +291,7 @@ struct vm_area_struct; extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); /* Make a non-present pseudo-TTE. */ -extern inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space) +static inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space) { pte_t pte; pte_val(pte) = ((page) | pgprot_val(prot) | _PAGE_E) & ~(unsigned long)_PAGE_CACHE; @@ -313,7 +313,7 @@ extern inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space) extern unsigned long prom_virt_to_phys(unsigned long, int *); -extern __inline__ unsigned long +static __inline__ unsigned long sun4u_get_pte (unsigned long addr) { pgd_t *pgdp; @@ -330,13 +330,13 @@ sun4u_get_pte (unsigned long addr) return pte_val(*ptep) & _PAGE_PADDR; } -extern __inline__ unsigned long +static __inline__ unsigned long __get_phys (unsigned long addr) { return sun4u_get_pte (addr); } -extern __inline__ int +static __inline__ int __get_iospace (unsigned long addr) { return ((sun4u_get_pte (addr) & 0xf0000000) >> 28); diff --git a/include/asm-sparc64/psrcompat.h b/include/asm-sparc64/psrcompat.h index 12fa4871a545..46a1545f3804 100644 --- a/include/asm-sparc64/psrcompat.h +++ b/include/asm-sparc64/psrcompat.h @@ -24,7 +24,7 @@ #define PSR_V8PLUS 0xff000000 /* fake impl/ver, meaning a 64bit CPU is present */ #define PSR_XCC 0x000f0000 /* if PSR_V8PLUS, this is %xcc */ -extern inline unsigned int tstate_to_psr(unsigned long tstate) +static inline unsigned int tstate_to_psr(unsigned long tstate) { return ((tstate & TSTATE_CWP) | PSR_S | @@ -33,7 +33,7 @@ extern inline unsigned int tstate_to_psr(unsigned long tstate) PSR_V8PLUS); } -extern inline unsigned long psr_to_tstate_icc(unsigned int psr) +static inline unsigned long psr_to_tstate_icc(unsigned int psr) { unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12; if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS) diff --git a/include/asm-sparc64/sbus.h b/include/asm-sparc64/sbus.h index 5970645950ab..62ba8f064344 100644 --- a/include/asm-sparc64/sbus.h +++ b/include/asm-sparc64/sbus.h @@ -27,12 +27,12 @@ * numbers + offsets, and vice versa. */ -extern __inline__ unsigned long sbus_devaddr(int slotnum, unsigned long offset) +static __inline__ unsigned long sbus_devaddr(int slotnum, unsigned long offset) { return (unsigned long) (SUN_SBUS_BVADDR+((slotnum)<<28)+(offset)); } -extern __inline__ int sbus_dev_slot(unsigned long dev_addr) +static __inline__ int sbus_dev_slot(unsigned long dev_addr) { return (int) (((dev_addr)-SUN_SBUS_BVADDR)>>28); } diff --git a/include/asm-sparc64/siginfo.h b/include/asm-sparc64/siginfo.h index ff760c478463..f8d1959ea8dc 100644 --- a/include/asm-sparc64/siginfo.h +++ b/include/asm-sparc64/siginfo.h @@ -154,7 +154,7 @@ typedef struct sigevent32 { #include -extern inline void copy_siginfo(siginfo_t *to, siginfo_t *from) +static inline void copy_siginfo(siginfo_t *to, siginfo_t *from) { if (from->si_code < 0) *to = *from; diff --git a/include/asm-sparc64/smp.h b/include/asm-sparc64/smp.h index ae3370ebef98..babbfe5f916b 100644 --- a/include/asm-sparc64/smp.h +++ b/include/asm-sparc64/smp.h @@ -89,7 +89,7 @@ static inline int any_online_cpu(unsigned long mask) * General functions that each host system must provide. */ -extern __inline__ int hard_smp_processor_id(void) +static __inline__ int hard_smp_processor_id(void) { if (tlb_type == cheetah || tlb_type == cheetah_plus) { unsigned long safari_config; @@ -130,7 +130,7 @@ static __inline__ void smp_send_reschedule(int cpu) /* This is a nop as well because we capture all other cpus * anyways when making the PROM active. */ -extern __inline__ void smp_send_stop(void) { } +static __inline__ void smp_send_stop(void) { } #endif /* !(__ASSEMBLY__) */ diff --git a/include/asm-sparc64/spinlock.h b/include/asm-sparc64/spinlock.h index 48c93f17bb4f..8bdc07cfad6f 100644 --- a/include/asm-sparc64/spinlock.h +++ b/include/asm-sparc64/spinlock.h @@ -40,7 +40,7 @@ typedef unsigned char spinlock_t; do { membar("#LoadLoad"); \ } while(*((volatile unsigned char *)lock)) -extern __inline__ void _raw_spin_lock(spinlock_t *lock) +static __inline__ void _raw_spin_lock(spinlock_t *lock) { __asm__ __volatile__( "1: ldstub [%0], %%g7\n" @@ -57,7 +57,7 @@ extern __inline__ void _raw_spin_lock(spinlock_t *lock) : "g7", "memory"); } -extern __inline__ int _raw_spin_trylock(spinlock_t *lock) +static __inline__ int _raw_spin_trylock(spinlock_t *lock) { unsigned int result; __asm__ __volatile__("ldstub [%1], %0\n\t" @@ -68,7 +68,7 @@ extern __inline__ int _raw_spin_trylock(spinlock_t *lock) return (result == 0); } -extern __inline__ void _raw_spin_unlock(spinlock_t *lock) +static __inline__ void _raw_spin_unlock(spinlock_t *lock) { __asm__ __volatile__("membar #StoreStore | #LoadStore\n\t" "stb %%g0, [%0]" diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h index 022e3b95f89f..f93e66aaa1ba 100644 --- a/include/asm-sparc64/spitfire.h +++ b/include/asm-sparc64/spitfire.h @@ -56,7 +56,7 @@ extern enum ultra_tlb_layout tlb_type; SPITFIRE_HIGHEST_LOCKED_TLBENT : \ CHEETAH_HIGHEST_LOCKED_TLBENT) -extern __inline__ unsigned long spitfire_get_isfsr(void) +static __inline__ unsigned long spitfire_get_isfsr(void) { unsigned long ret; @@ -66,7 +66,7 @@ extern __inline__ unsigned long spitfire_get_isfsr(void) return ret; } -extern __inline__ unsigned long spitfire_get_dsfsr(void) +static __inline__ unsigned long spitfire_get_dsfsr(void) { unsigned long ret; @@ -76,7 +76,7 @@ extern __inline__ unsigned long spitfire_get_dsfsr(void) return ret; } -extern __inline__ unsigned long spitfire_get_sfar(void) +static __inline__ unsigned long spitfire_get_sfar(void) { unsigned long ret; @@ -86,7 +86,7 @@ extern __inline__ unsigned long spitfire_get_sfar(void) return ret; } -extern __inline__ void spitfire_put_isfsr(unsigned long sfsr) +static __inline__ void spitfire_put_isfsr(unsigned long sfsr) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" @@ -94,7 +94,7 @@ extern __inline__ void spitfire_put_isfsr(unsigned long sfsr) : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_IMMU)); } -extern __inline__ void spitfire_put_dsfsr(unsigned long sfsr) +static __inline__ void spitfire_put_dsfsr(unsigned long sfsr) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" @@ -102,7 +102,7 @@ extern __inline__ void spitfire_put_dsfsr(unsigned long sfsr) : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_DMMU)); } -extern __inline__ unsigned long spitfire_get_primary_context(void) +static __inline__ unsigned long spitfire_get_primary_context(void) { unsigned long ctx; @@ -112,7 +112,7 @@ extern __inline__ unsigned long spitfire_get_primary_context(void) return ctx; } -extern __inline__ void spitfire_set_primary_context(unsigned long ctx) +static __inline__ void spitfire_set_primary_context(unsigned long ctx) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" @@ -122,7 +122,7 @@ extern __inline__ void spitfire_set_primary_context(unsigned long ctx) __asm__ __volatile__ ("membar #Sync" : : : "memory"); } -extern __inline__ unsigned long spitfire_get_secondary_context(void) +static __inline__ unsigned long spitfire_get_secondary_context(void) { unsigned long ctx; @@ -132,7 +132,7 @@ extern __inline__ unsigned long spitfire_get_secondary_context(void) return ctx; } -extern __inline__ void spitfire_set_secondary_context(unsigned long ctx) +static __inline__ void spitfire_set_secondary_context(unsigned long ctx) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" @@ -145,7 +145,7 @@ extern __inline__ void spitfire_set_secondary_context(unsigned long ctx) /* The data cache is write through, so this just invalidates the * specified line. */ -extern __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag) +static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" @@ -160,7 +160,7 @@ extern __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long * a flush instruction (to any address) is sufficient to handle * this issue after the line is invalidated. */ -extern __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long tag) +static __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long tag) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" @@ -168,7 +168,7 @@ extern __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long : "r" (tag), "r" (addr), "i" (ASI_IC_TAG)); } -extern __inline__ unsigned long spitfire_get_dtlb_data(int entry) +static __inline__ unsigned long spitfire_get_dtlb_data(int entry) { unsigned long data; @@ -182,7 +182,7 @@ extern __inline__ unsigned long spitfire_get_dtlb_data(int entry) return data; } -extern __inline__ unsigned long spitfire_get_dtlb_tag(int entry) +static __inline__ unsigned long spitfire_get_dtlb_tag(int entry) { unsigned long tag; @@ -192,7 +192,7 @@ extern __inline__ unsigned long spitfire_get_dtlb_tag(int entry) return tag; } -extern __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data) +static __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" @@ -201,7 +201,7 @@ extern __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data) "i" (ASI_DTLB_DATA_ACCESS)); } -extern __inline__ unsigned long spitfire_get_itlb_data(int entry) +static __inline__ unsigned long spitfire_get_itlb_data(int entry) { unsigned long data; @@ -215,7 +215,7 @@ extern __inline__ unsigned long spitfire_get_itlb_data(int entry) return data; } -extern __inline__ unsigned long spitfire_get_itlb_tag(int entry) +static __inline__ unsigned long spitfire_get_itlb_tag(int entry) { unsigned long tag; @@ -225,7 +225,7 @@ extern __inline__ unsigned long spitfire_get_itlb_tag(int entry) return tag; } -extern __inline__ void spitfire_put_itlb_data(int entry, unsigned long data) +static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" @@ -237,7 +237,7 @@ extern __inline__ void spitfire_put_itlb_data(int entry, unsigned long data) /* Spitfire hardware assisted TLB flushes. */ /* Context level flushes. */ -extern __inline__ void spitfire_flush_dtlb_primary_context(void) +static __inline__ void spitfire_flush_dtlb_primary_context(void) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -245,7 +245,7 @@ extern __inline__ void spitfire_flush_dtlb_primary_context(void) : "r" (0x40), "i" (ASI_DMMU_DEMAP)); } -extern __inline__ void spitfire_flush_itlb_primary_context(void) +static __inline__ void spitfire_flush_itlb_primary_context(void) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -253,7 +253,7 @@ extern __inline__ void spitfire_flush_itlb_primary_context(void) : "r" (0x40), "i" (ASI_IMMU_DEMAP)); } -extern __inline__ void spitfire_flush_dtlb_secondary_context(void) +static __inline__ void spitfire_flush_dtlb_secondary_context(void) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -261,7 +261,7 @@ extern __inline__ void spitfire_flush_dtlb_secondary_context(void) : "r" (0x50), "i" (ASI_DMMU_DEMAP)); } -extern __inline__ void spitfire_flush_itlb_secondary_context(void) +static __inline__ void spitfire_flush_itlb_secondary_context(void) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -269,7 +269,7 @@ extern __inline__ void spitfire_flush_itlb_secondary_context(void) : "r" (0x50), "i" (ASI_IMMU_DEMAP)); } -extern __inline__ void spitfire_flush_dtlb_nucleus_context(void) +static __inline__ void spitfire_flush_dtlb_nucleus_context(void) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -277,7 +277,7 @@ extern __inline__ void spitfire_flush_dtlb_nucleus_context(void) : "r" (0x60), "i" (ASI_DMMU_DEMAP)); } -extern __inline__ void spitfire_flush_itlb_nucleus_context(void) +static __inline__ void spitfire_flush_itlb_nucleus_context(void) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -286,7 +286,7 @@ extern __inline__ void spitfire_flush_itlb_nucleus_context(void) } /* Page level flushes. */ -extern __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page) +static __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -294,7 +294,7 @@ extern __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page) : "r" (page), "i" (ASI_DMMU_DEMAP)); } -extern __inline__ void spitfire_flush_itlb_primary_page(unsigned long page) +static __inline__ void spitfire_flush_itlb_primary_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -302,7 +302,7 @@ extern __inline__ void spitfire_flush_itlb_primary_page(unsigned long page) : "r" (page), "i" (ASI_IMMU_DEMAP)); } -extern __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page) +static __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -310,7 +310,7 @@ extern __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page) : "r" (page | 0x10), "i" (ASI_DMMU_DEMAP)); } -extern __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page) +static __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -318,7 +318,7 @@ extern __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page) : "r" (page | 0x10), "i" (ASI_IMMU_DEMAP)); } -extern __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page) +static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -326,7 +326,7 @@ extern __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page) : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP)); } -extern __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page) +static __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -335,7 +335,7 @@ extern __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page) } /* Cheetah has "all non-locked" tlb flushes. */ -extern __inline__ void cheetah_flush_dtlb_all(void) +static __inline__ void cheetah_flush_dtlb_all(void) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -343,7 +343,7 @@ extern __inline__ void cheetah_flush_dtlb_all(void) : "r" (0x80), "i" (ASI_DMMU_DEMAP)); } -extern __inline__ void cheetah_flush_itlb_all(void) +static __inline__ void cheetah_flush_itlb_all(void) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" @@ -365,7 +365,7 @@ extern __inline__ void cheetah_flush_itlb_all(void) * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes * the problem for me. -DaveM */ -extern __inline__ unsigned long cheetah_get_ldtlb_data(int entry) +static __inline__ unsigned long cheetah_get_ldtlb_data(int entry) { unsigned long data; @@ -378,7 +378,7 @@ extern __inline__ unsigned long cheetah_get_ldtlb_data(int entry) return data; } -extern __inline__ unsigned long cheetah_get_litlb_data(int entry) +static __inline__ unsigned long cheetah_get_litlb_data(int entry) { unsigned long data; @@ -391,7 +391,7 @@ extern __inline__ unsigned long cheetah_get_litlb_data(int entry) return data; } -extern __inline__ unsigned long cheetah_get_ldtlb_tag(int entry) +static __inline__ unsigned long cheetah_get_ldtlb_tag(int entry) { unsigned long tag; @@ -403,7 +403,7 @@ extern __inline__ unsigned long cheetah_get_ldtlb_tag(int entry) return tag; } -extern __inline__ unsigned long cheetah_get_litlb_tag(int entry) +static __inline__ unsigned long cheetah_get_litlb_tag(int entry) { unsigned long tag; @@ -415,7 +415,7 @@ extern __inline__ unsigned long cheetah_get_litlb_tag(int entry) return tag; } -extern __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data) +static __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" @@ -425,7 +425,7 @@ extern __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data) "i" (ASI_DTLB_DATA_ACCESS)); } -extern __inline__ void cheetah_put_litlb_data(int entry, unsigned long data) +static __inline__ void cheetah_put_litlb_data(int entry, unsigned long data) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" @@ -435,7 +435,7 @@ extern __inline__ void cheetah_put_litlb_data(int entry, unsigned long data) "i" (ASI_ITLB_DATA_ACCESS)); } -extern __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb) +static __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb) { unsigned long data; @@ -447,7 +447,7 @@ extern __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb) return data; } -extern __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb) +static __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb) { unsigned long tag; @@ -457,7 +457,7 @@ extern __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb) return tag; } -extern __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb) +static __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" @@ -467,7 +467,7 @@ extern __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int "i" (ASI_DTLB_DATA_ACCESS)); } -extern __inline__ unsigned long cheetah_get_itlb_data(int entry) +static __inline__ unsigned long cheetah_get_itlb_data(int entry) { unsigned long data; @@ -480,7 +480,7 @@ extern __inline__ unsigned long cheetah_get_itlb_data(int entry) return data; } -extern __inline__ unsigned long cheetah_get_itlb_tag(int entry) +static __inline__ unsigned long cheetah_get_itlb_tag(int entry) { unsigned long tag; @@ -490,7 +490,7 @@ extern __inline__ unsigned long cheetah_get_itlb_tag(int entry) return tag; } -extern __inline__ void cheetah_put_itlb_data(int entry, unsigned long data) +static __inline__ void cheetah_put_itlb_data(int entry, unsigned long data) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h index b7edad3a52c6..ab2141904843 100644 --- a/include/asm-sparc64/system.h +++ b/include/asm-sparc64/system.h @@ -217,7 +217,7 @@ do { if (test_thread_flag(TIF_PERFCTR)) { \ } \ } while(0) -extern __inline__ unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val) +static __inline__ unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val) { __asm__ __volatile__( " mov %0, %%g5\n" @@ -233,7 +233,7 @@ extern __inline__ unsigned long xchg32(__volatile__ unsigned int *m, unsigned in return val; } -extern __inline__ unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val) +static __inline__ unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val) { __asm__ __volatile__( " mov %0, %%g5\n" @@ -277,7 +277,7 @@ extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noret #define __HAVE_ARCH_CMPXCHG 1 -extern __inline__ unsigned long +static __inline__ unsigned long __cmpxchg_u32(volatile int *m, int old, int new) { __asm__ __volatile__("cas [%2], %3, %0\n\t" @@ -289,7 +289,7 @@ __cmpxchg_u32(volatile int *m, int old, int new) return new; } -extern __inline__ unsigned long +static __inline__ unsigned long __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new) { __asm__ __volatile__("casx [%2], %3, %0\n\t" diff --git a/include/asm-sparc64/uaccess.h b/include/asm-sparc64/uaccess.h index a52de7d2a22a..5d9b9d4a070a 100644 --- a/include/asm-sparc64/uaccess.h +++ b/include/asm-sparc64/uaccess.h @@ -52,7 +52,7 @@ do { \ #define __access_ok(addr,size) 1 #define access_ok(type,addr,size) 1 -extern inline int verify_area(int type, const void * addr, unsigned long size) +static inline int verify_area(int type, const void * addr, unsigned long size) { return 0; } @@ -270,7 +270,7 @@ extern __kernel_size_t __copy_in_user(void *to, const void *from, __copy_in_user((void *)(to), \ (void *) (from), (__kernel_size_t)(n)) -extern __inline__ __kernel_size_t __clear_user(void *addr, __kernel_size_t size) +static __inline__ __kernel_size_t __clear_user(void *addr, __kernel_size_t size) { extern __kernel_size_t __bzero_noasi(void *addr, __kernel_size_t size); diff --git a/include/asm-sparc64/upa.h b/include/asm-sparc64/upa.h index fabcf2c51664..245b85b13a8d 100644 --- a/include/asm-sparc64/upa.h +++ b/include/asm-sparc64/upa.h @@ -25,7 +25,7 @@ /* UPA I/O space accessors */ #if defined(__KERNEL__) && !defined(__ASSEMBLY__) -extern __inline__ unsigned char _upa_readb(unsigned long addr) +static __inline__ unsigned char _upa_readb(unsigned long addr) { unsigned char ret; @@ -36,7 +36,7 @@ extern __inline__ unsigned char _upa_readb(unsigned long addr) return ret; } -extern __inline__ unsigned short _upa_readw(unsigned long addr) +static __inline__ unsigned short _upa_readw(unsigned long addr) { unsigned short ret; @@ -47,7 +47,7 @@ extern __inline__ unsigned short _upa_readw(unsigned long addr) return ret; } -extern __inline__ unsigned int _upa_readl(unsigned long addr) +static __inline__ unsigned int _upa_readl(unsigned long addr) { unsigned int ret; @@ -58,7 +58,7 @@ extern __inline__ unsigned int _upa_readl(unsigned long addr) return ret; } -extern __inline__ unsigned long _upa_readq(unsigned long addr) +static __inline__ unsigned long _upa_readq(unsigned long addr) { unsigned long ret; @@ -69,28 +69,28 @@ extern __inline__ unsigned long _upa_readq(unsigned long addr) return ret; } -extern __inline__ void _upa_writeb(unsigned char b, unsigned long addr) +static __inline__ void _upa_writeb(unsigned char b, unsigned long addr) { __asm__ __volatile__("stba\t%0, [%1] %2\t/* upa_writeb */" : /* no outputs */ : "r" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); } -extern __inline__ void _upa_writew(unsigned short w, unsigned long addr) +static __inline__ void _upa_writew(unsigned short w, unsigned long addr) { __asm__ __volatile__("stha\t%0, [%1] %2\t/* upa_writew */" : /* no outputs */ : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); } -extern __inline__ void _upa_writel(unsigned int l, unsigned long addr) +static __inline__ void _upa_writel(unsigned int l, unsigned long addr) { __asm__ __volatile__("stwa\t%0, [%1] %2\t/* upa_writel */" : /* no outputs */ : "r" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); } -extern __inline__ void _upa_writeq(unsigned long q, unsigned long addr) +static __inline__ void _upa_writeq(unsigned long q, unsigned long addr) { __asm__ __volatile__("stxa\t%0, [%1] %2\t/* upa_writeq */" : /* no outputs */ diff --git a/include/asm-sparc64/visasm.h b/include/asm-sparc64/visasm.h index 55e92117cd35..de98f235d7cf 100644 --- a/include/asm-sparc64/visasm.h +++ b/include/asm-sparc64/visasm.h @@ -42,7 +42,7 @@ wr %o5, 0, %fprs; #ifndef __ASSEMBLY__ -extern __inline__ void save_and_clear_fpu(void) { +static __inline__ void save_and_clear_fpu(void) { __asm__ __volatile__ ( " rd %%fprs, %%o5\n" " andcc %%o5, %0, %%g0\n" -- cgit v1.2.3 From 8800796300bf40e5649fe909bde102e33ccbb776 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Wed, 2 Oct 2002 21:21:46 -0700 Subject: include/asm-sparc64/pstate.h: Kill asm routines, nobody uses them. --- include/asm-sparc64/pstate.h | 28 ---------------------------- 1 file changed, 28 deletions(-) (limited to 'include') diff --git a/include/asm-sparc64/pstate.h b/include/asm-sparc64/pstate.h index a1e1414d62d5..fa69b5f6cf09 100644 --- a/include/asm-sparc64/pstate.h +++ b/include/asm-sparc64/pstate.h @@ -85,32 +85,4 @@ #define VERS_MAXTL 0x000000000000ff00 /* Maximum Trap Level. */ #define VERS_MAXWIN 0x000000000000001f /* Maximum Reg Window Index. */ -#if defined(__KERNEL__) && !defined(__ASSEMBLY__) -#define set_pstate(bits) \ - __asm__ __volatile__( \ - "rdpr %%pstate, %%g1\n\t" \ - "or %%g1, %0, %%g1\n\t" \ - "wrpr %%g1, 0x0, %%pstate\n\t" \ - : /* no outputs */ \ - : "i" (bits) \ - : "g1") - -#define clear_pstate(bits) \ - __asm__ __volatile__( \ - "rdpr %%pstate, %%g1\n\t" \ - "andn %%g1, %0, %%g1\n\t" \ - "wrpr %%g1, 0x0, %%pstate\n\t" \ - : /* no outputs */ \ - : "i" (bits) \ - : "g1") - -#define change_pstate(bits) \ - __asm__ __volatile__( \ - "rdpr %%pstate, %%g1\n\t" \ - "wrpr %%g1, %0, %%pstate\n\t" \ - : /* no outputs */ \ - : "i" (bits) \ - : "g1") -#endif - #endif /* !(_SPARC64_PSTATE_H) */ -- cgit v1.2.3 From 403acce588de0a4fc054a57f97551073de1c75b9 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Fri, 4 Oct 2002 11:37:12 -0700 Subject: [SPARC]: Uninline kmap atomic operations. --- arch/sparc/kernel/sparc_ksyms.c | 9 ++++ arch/sparc/mm/Makefile | 4 ++ arch/sparc/mm/generic.c | 2 + arch/sparc/mm/highmem.c | 99 +++++++++++++++++++++++++++++++++++++++++ arch/sparc/mm/srmmu.c | 2 + include/asm-sparc/highmem.h | 82 +--------------------------------- 6 files changed, 118 insertions(+), 80 deletions(-) create mode 100644 arch/sparc/mm/highmem.c (limited to 'include') diff --git a/arch/sparc/kernel/sparc_ksyms.c b/arch/sparc/kernel/sparc_ksyms.c index edde8477752e..07d60fa9359d 100644 --- a/arch/sparc/kernel/sparc_ksyms.c +++ b/arch/sparc/kernel/sparc_ksyms.c @@ -23,6 +23,9 @@ #include #endif #include +#ifdef CONFIG_HIGHMEM +#include +#endif #include #include @@ -199,6 +202,12 @@ EXPORT_SYMBOL(ioremap); EXPORT_SYMBOL(iounmap); #endif +/* in arch/sparc/mm/highmem.c */ +#ifdef CONFIG_HIGHMEM +EXPORT_SYMBOL(kmap_atomic); +EXPORT_SYMBOL(kunmap_atomic); +#endif + /* Solaris/SunOS binary compatibility */ EXPORT_SYMBOL(svr4_setcontext); EXPORT_SYMBOL(svr4_getcontext); diff --git a/arch/sparc/mm/Makefile b/arch/sparc/mm/Makefile index ae51af202022..59985c15a307 100644 --- a/arch/sparc/mm/Makefile +++ b/arch/sparc/mm/Makefile @@ -12,6 +12,10 @@ else obj-y += srmmu.o iommu.o io-unit.o hypersparc.o viking.o tsunami.o swift.o endif +ifdef CONFIG_HIGHMEM +obj-y += highmem.o +endif + ifdef CONFIG_SMP obj-y += nosun4c.o else diff --git a/arch/sparc/mm/generic.c b/arch/sparc/mm/generic.c index 5d7f7c4d670e..6d2febb040b0 100644 --- a/arch/sparc/mm/generic.c +++ b/arch/sparc/mm/generic.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include static inline void forget_pte(pte_t page) { diff --git a/arch/sparc/mm/highmem.c b/arch/sparc/mm/highmem.c new file mode 100644 index 000000000000..7b4ebf2064a2 --- /dev/null +++ b/arch/sparc/mm/highmem.c @@ -0,0 +1,99 @@ +/* + * highmem.c: virtual kernel memory mappings for high memory + * + * Provides kernel-static versions of atomic kmap functions originally + * found as inlines in include/asm-sparc/highmem.h. These became + * needed as kmap_atomic() and kunmap_atomic() started getting + * called from within modules. + * -- Tomas Szepe , September 2002 + * + * But kmap_atomic() and kunmap_atomic() cannot be inlined in + * modules because they are loaded with btfixup-ped functions. + */ + +/* + * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap + * gives a more generic (and caching) interface. But kmap_atomic can + * be used in IRQ contexts, so in some (very limited) cases we need it. + * + * XXX This is an old text. Actually, it's good to use atomic kmaps, + * provided you remember that they are atomic and not try to sleep + * with a kmap taken, much like a spinlock. Non-atomic kmaps are + * shared by CPUs, and so precious, and establishing them requires IPI. + * Atomic kmaps are lightweight and we may have NCPUS more of them. + */ +#include +#include +#include +#include +#include + +void *kmap_atomic(struct page *page, enum km_type type) +{ + unsigned long idx; + unsigned long vaddr; + + inc_preempt_count(); + if (page < highmem_start_page) + return page_address(page); + + idx = type + KM_TYPE_NR*smp_processor_id(); + vaddr = FIX_KMAP_BEGIN + idx * PAGE_SIZE; + +/* XXX Fix - Anton */ +#if 0 + __flush_cache_one(vaddr); +#else + flush_cache_all(); +#endif + +#if HIGHMEM_DEBUG + if (!pte_none(*(kmap_pte+idx))) + BUG(); +#endif + set_pte(kmap_pte+idx, mk_pte(page, kmap_prot)); +/* XXX Fix - Anton */ +#if 0 + __flush_tlb_one(vaddr); +#else + flush_tlb_all(); +#endif + + return (void*) vaddr; +} + +void kunmap_atomic(void *kvaddr, enum km_type type) +{ + unsigned long vaddr = (unsigned long) kvaddr; + unsigned long idx = type + KM_TYPE_NR*smp_processor_id(); + + if (vaddr < FIX_KMAP_BEGIN) { // FIXME + dec_preempt_count(); + return; + } + + if (vaddr != FIX_KMAP_BEGIN + idx * PAGE_SIZE) + BUG(); + +/* XXX Fix - Anton */ +#if 0 + __flush_cache_one(vaddr); +#else + flush_cache_all(); +#endif + +#ifdef HIGHMEM_DEBUG + /* + * force other mappings to Oops if they'll try to access + * this pte without first remap it + */ + pte_clear(kmap_pte+idx); +/* XXX Fix - Anton */ +#if 0 + __flush_tlb_one(vaddr); +#else + flush_tlb_all(); +#endif +#endif + dec_preempt_count(); +} diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c index 0624774d0540..9051649b82b1 100644 --- a/arch/sparc/mm/srmmu.c +++ b/arch/sparc/mm/srmmu.c @@ -38,6 +38,8 @@ #include #include #include +#include +#include /* Now the cpu specific definitions. */ #include diff --git a/include/asm-sparc/highmem.h b/include/asm-sparc/highmem.h index e9bf972142f8..e4c8edc4409d 100644 --- a/include/asm-sparc/highmem.h +++ b/include/asm-sparc/highmem.h @@ -20,13 +20,8 @@ #ifdef __KERNEL__ -#include #include -#include #include -#include -#include -#include /* undef for production */ #define HIGHMEM_DEBUG 1 @@ -72,81 +67,8 @@ static inline void kunmap(struct page *page) kunmap_high(page); } -/* - * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap - * gives a more generic (and caching) interface. But kmap_atomic can - * be used in IRQ contexts, so in some (very limited) cases we need - * it. - */ -static inline void *kmap_atomic(struct page *page, enum km_type type) -{ - unsigned long idx; - unsigned long vaddr; - - inc_preempt_count(); - if (page < highmem_start_page) - return page_address(page); - - idx = type + KM_TYPE_NR*smp_processor_id(); - vaddr = FIX_KMAP_BEGIN + idx * PAGE_SIZE; - -/* XXX Fix - Anton */ -#if 0 - __flush_cache_one(vaddr); -#else - flush_cache_all(); -#endif - -#if HIGHMEM_DEBUG - if (!pte_none(*(kmap_pte+idx))) - BUG(); -#endif - set_pte(kmap_pte+idx, mk_pte(page, kmap_prot)); -/* XXX Fix - Anton */ -#if 0 - __flush_tlb_one(vaddr); -#else - flush_tlb_all(); -#endif - - return (void*) vaddr; -} - -static inline void kunmap_atomic(void *kvaddr, enum km_type type) -{ - unsigned long vaddr = (unsigned long) kvaddr; - unsigned long idx = type + KM_TYPE_NR*smp_processor_id(); - - if (vaddr < FIX_KMAP_BEGIN) { // FIXME - dec_preempt_count(); - return; - } - - if (vaddr != FIX_KMAP_BEGIN + idx * PAGE_SIZE) - BUG(); - -/* XXX Fix - Anton */ -#if 0 - __flush_cache_one(vaddr); -#else - flush_cache_all(); -#endif - -#ifdef HIGHMEM_DEBUG - /* - * force other mappings to Oops if they'll try to access - * this pte without first remap it - */ - pte_clear(kmap_pte+idx); -/* XXX Fix - Anton */ -#if 0 - __flush_tlb_one(vaddr); -#else - flush_tlb_all(); -#endif -#endif - dec_preempt_count(); -} +extern void *kmap_atomic(struct page *page, enum km_type type); +extern void kunmap_atomic(void *kvaddr, enum km_type type); static inline struct page *kmap_atomic_to_page(void *ptr) { -- cgit v1.2.3