From 7bbb3cc5c816fc167601ce9519adae5eced3ea6d Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Wed, 6 Dec 2006 17:13:54 -0800 Subject: ARM: OMAP: 24xx pinmux updates Add some OMAP 24xx pin mux declarations to support: - TUSB 6010 EVM (on H4) - All three full speed USB ports - GPIOs used with USB0 on Apollon and H4 For OMAP2, issue MUX_WARNINGS and debug messages correctly; and make the message look more like the OMAP1 message. Signed-off-by: Kyungmin Park Signed-off-by: David Brownell Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/mux.h | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index 828cc5c114e1..f1ec2edd4040 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -421,7 +421,9 @@ enum omap24xx_index { /* 24xx clock */ W14_24XX_SYS_CLKOUT, - /* 24xx GPMC wait pin monitoring */ + /* 24xx GPMC chipselects, wait pin monitoring */ + E2_GPMC_NCS2, + L2_GPMC_NCS7, L3_GPMC_WAIT0, N7_GPMC_WAIT1, M1_GPMC_WAIT2, @@ -435,6 +437,7 @@ enum omap24xx_index { /* 24xx GPIO */ M21_242X_GPIO11, + P21_242X_GPIO12, AA10_242X_GPIO13, AA6_242X_GPIO14, AA4_242X_GPIO15, @@ -444,7 +447,9 @@ enum omap24xx_index { Y20_24XX_GPIO60, W4__24XX_GPIO74, M15_24XX_GPIO92, + J15_24XX_GPIO99, V14_24XX_GPIO117, + P14_24XX_GPIO125, /* 242x DBG GPIO */ V4_242X_GPIO49, @@ -486,6 +491,30 @@ enum omap24xx_index { G18_24XX_MMC_CMD_DIR, H15_24XX_MMC_CLKI, + /* Full speed USB */ + J20_24XX_USB0_PUEN, + J19_24XX_USB0_VP, + K20_24XX_USB0_VM, + J18_24XX_USB0_RCV, + K19_24XX_USB0_TXEN, + J14_24XX_USB0_SE0, + K18_24XX_USB0_DAT, + + N14_24XX_USB1_SE0, + W12_24XX_USB1_SE0, + P15_24XX_USB1_DAT, + R13_24XX_USB1_DAT, + W20_24XX_USB1_TXEN, + P13_24XX_USB1_TXEN, + V19_24XX_USB1_RCV, + V12_24XX_USB1_RCV, + + AA10_24XX_USB2_SE0, + Y11_24XX_USB2_DAT, + AA12_24XX_USB2_TXEN, + AA6_24XX_USB2_RCV, + AA4_24XX_USB2_TLLSE0, + /* Keypad GPIO*/ T19_24XX_KBR0, R19_24XX_KBR1, -- cgit v1.2.3 From c7b87f3d5037a35b5c7bb916ffc826be3fcb208d Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 10 May 2007 16:46:13 +0100 Subject: [ARM] ecard: add helper function for setting ecard irq ops Rather than having every driver fiddle about setting its private IRQ operations and data, provide a helper function to contain this functionality in one place. Arrange to remove the driver-private IRQ operations and data when the device is removed from the driver, and remove the driver private code to do this. This fixes potential problems caused by drivers forgetting to remove these hooks. Signed-off-by: Russell King --- arch/arm/kernel/ecard.c | 16 ++++++++++++++++ drivers/ata/pata_icside.c | 13 ++++--------- drivers/ide/arm/icside.c | 9 +++------ drivers/net/arm/etherh.c | 4 +--- drivers/scsi/arm/cumana_2.c | 4 ++-- drivers/scsi/arm/eesox.c | 4 ++-- drivers/scsi/arm/powertec.c | 4 ++-- include/asm-arm/ecard.h | 4 +++- 8 files changed, 33 insertions(+), 25 deletions(-) (limited to 'include') diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index bdbd7da99286..65f1398723a4 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c @@ -958,6 +958,14 @@ void ecard_release_resources(struct expansion_card *ec) } EXPORT_SYMBOL(ecard_release_resources); +void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data) +{ + ec->irq_data = irq_data; + barrier(); + ec->ops = ops; +} +EXPORT_SYMBOL(ecard_setirq); + /* * Probe for an expansion card. * @@ -1133,6 +1141,14 @@ static int ecard_drv_remove(struct device *dev) drv->remove(ec); ecard_release(ec); + /* + * Restore the default operations. We ensure that the + * ops are set before we change the data. + */ + ec->ops = &ecard_default_ops; + barrier(); + ec->irq_data = NULL; + return 0; } diff --git a/drivers/ata/pata_icside.c b/drivers/ata/pata_icside.c index dbc8ee2adcf0..d7621a39ed09 100644 --- a/drivers/ata/pata_icside.c +++ b/drivers/ata/pata_icside.c @@ -434,8 +434,8 @@ pata_icside_register_v5(struct ata_probe_ent *ae, struct expansion_card *ec) ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; ec->irqmask = 1; - ec->irq_data = state; - ec->ops = &pata_icside_ops_arcin_v5; + + ecard_setirq(ec, &pata_icside_ops_arcin_v5, state); /* * Be on the safe side - disable interrupts @@ -480,8 +480,7 @@ pata_icside_register_v6(struct ata_probe_ent *ae, struct expansion_card *ec) writeb(sel, ioc_base); - ec->irq_data = state; - ec->ops = &pata_icside_ops_arcin_v6; + ecard_setirq(ec, &pata_icside_ops_arcin_v6, state); state->irq_port = easi_base; state->ioc_base = ioc_base; @@ -609,8 +608,7 @@ static void pata_icside_shutdown(struct expansion_card *ec) * this register via that region. */ local_irq_save(flags); - if (ec->ops) - ec->ops->irqdisable(ec, ec->irq); + ec->ops->irqdisable(ec, ec->irq); local_irq_restore(flags); /* @@ -638,9 +636,6 @@ static void __devexit pata_icside_remove(struct expansion_card *ec) * don't NULL out the drvdata - devres/libata wants it * to free the ata_host structure. */ - ec->ops = NULL; - ec->irq_data = NULL; - if (state->dma != NO_DMA) free_dma(state->dma); if (state->ioc_base) diff --git a/drivers/ide/arm/icside.c b/drivers/ide/arm/icside.c index 1fe0457243db..69c949ea93e3 100644 --- a/drivers/ide/arm/icside.c +++ b/drivers/ide/arm/icside.c @@ -574,8 +574,8 @@ icside_register_v5(struct icside_state *state, struct expansion_card *ec) ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; ec->irqmask = 1; - ec->irq_data = state; - ec->ops = &icside_ops_arcin_v5; + + ecard_setirq(ec, &icside_ops_arcin_v5, state); /* * Be on the safe side - disable interrupts @@ -630,8 +630,7 @@ icside_register_v6(struct icside_state *state, struct expansion_card *ec) writeb(sel, ioc_base); - ec->irq_data = state; - ec->ops = &icside_ops_arcin_v6; + ecard_setirq(ec, &icside_ops_arcin_v6, state); state->irq_port = easi_base; state->ioc_base = ioc_base; @@ -793,8 +792,6 @@ static void __devexit icside_remove(struct expansion_card *ec) } ecard_set_drvdata(ec, NULL); - ec->ops = NULL; - ec->irq_data = NULL; if (state->ioc_base) iounmap(state->ioc_base); diff --git a/drivers/net/arm/etherh.c b/drivers/net/arm/etherh.c index 61f574aa3a99..387f1e3a4e84 100644 --- a/drivers/net/arm/etherh.c +++ b/drivers/net/arm/etherh.c @@ -710,8 +710,7 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id) * IRQ and control port handling - only for non-NIC slot cards. */ if (ec->slot_no != 8) { - ec->ops = ðerh_ops; - ec->irq_data = eh; + ecard_setirq(ec, ðerh_ops, eh); } else { /* * If we're in the NIC slot, make sure the IRQ is enabled @@ -778,7 +777,6 @@ static void __devexit etherh_remove(struct expansion_card *ec) ecard_set_drvdata(ec, NULL); unregister_netdev(dev); - ec->ops = NULL; if (eh->ioc_fast) iounmap(eh->ioc_fast); diff --git a/drivers/scsi/arm/cumana_2.c b/drivers/scsi/arm/cumana_2.c index 82add77ad131..f51aa3446bc7 100644 --- a/drivers/scsi/arm/cumana_2.c +++ b/drivers/scsi/arm/cumana_2.c @@ -450,8 +450,8 @@ cumanascsi2_probe(struct expansion_card *ec, const struct ecard_id *id) ec->irqaddr = info->base + CUMANASCSI2_STATUS; ec->irqmask = STATUS_INT; - ec->irq_data = info; - ec->ops = &cumanascsi_2_ops; + + ecard_setirq(ec, &cumanascsi_2_ops, info); ret = fas216_init(host); if (ret) diff --git a/drivers/scsi/arm/eesox.c b/drivers/scsi/arm/eesox.c index ed06a8c19ad6..cc5d513aa99a 100644 --- a/drivers/scsi/arm/eesox.c +++ b/drivers/scsi/arm/eesox.c @@ -569,8 +569,8 @@ eesoxscsi_probe(struct expansion_card *ec, const struct ecard_id *id) ec->irqaddr = base + EESOX_DMASTAT; ec->irqmask = EESOX_STAT_INTR; - ec->irq_data = info; - ec->ops = &eesoxscsi_ops; + + ecard_setirq(ec, &eesoxscsi_ops, info); device_create_file(&ec->dev, &dev_attr_bus_term); diff --git a/drivers/scsi/arm/powertec.c b/drivers/scsi/arm/powertec.c index 159047a34997..3cbd525b58c5 100644 --- a/drivers/scsi/arm/powertec.c +++ b/drivers/scsi/arm/powertec.c @@ -361,8 +361,8 @@ powertecscsi_probe(struct expansion_card *ec, const struct ecard_id *id) ec->irqaddr = base + POWERTEC_INTR_STATUS; ec->irqmask = POWERTEC_INTR_BIT; - ec->irq_data = info; - ec->ops = &powertecscsi_ops; + + ecard_setirq(ec, &powertecscsi_ops, info); device_create_file(&ec->dev, &dev_attr_bus_term); diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h index 3a6d3eb27622..8f1000eac91f 100644 --- a/include/asm-arm/ecard.h +++ b/include/asm-arm/ecard.h @@ -121,7 +121,7 @@ struct in_ecid { /* Packed card ID information */ typedef struct expansion_card ecard_t; typedef unsigned long *loader_t; -typedef struct { /* Card handler routines */ +typedef struct expansion_card_ops { /* Card handler routines */ void (*irqenable)(ecard_t *ec, int irqnr); void (*irqdisable)(ecard_t *ec, int irqnr); int (*irqpending)(ecard_t *ec); @@ -179,6 +179,8 @@ struct expansion_card { u64 dma_mask; }; +void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data); + struct in_chunk_dir { unsigned int start_offset; union { -- cgit v1.2.3 From 10bdaaa0fad620145cf10e2b573266b2d80b44de Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 10 May 2007 18:40:51 +0100 Subject: [ARM] ecard: add ecardm_iomap() / ecardm_iounmap() Add devres ecardm_iomap() and ecardm_iounmap() for Acorn expansion cards. Convert all expansion card drivers to use them. Signed-off-by: Russell King --- arch/arm/kernel/ecard.c | 19 ++++++++++++++++++- drivers/ata/pata_icside.c | 35 +++++++++-------------------------- drivers/ide/arm/icside.c | 32 ++++++++------------------------ drivers/ide/arm/rapide.c | 5 +---- drivers/net/arm/ether1.c | 6 +----- drivers/net/arm/ether3.c | 6 +----- drivers/net/arm/etherh.c | 13 ++----------- drivers/scsi/arm/arxescsi.c | 12 ++---------- drivers/scsi/arm/cumana_2.c | 12 ++---------- drivers/scsi/arm/eesox.c | 12 ++---------- drivers/scsi/arm/powertec.c | 12 ++---------- drivers/serial/8250_acorn.c | 3 +-- include/asm-arm/ecard.h | 4 ++++ 13 files changed, 53 insertions(+), 118 deletions(-) (limited to 'include') diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index 65f1398723a4..f56d48c451ea 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c @@ -41,11 +41,11 @@ #include #include #include +#include #include #include #include -#include #include #include #include @@ -966,6 +966,23 @@ void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *op } EXPORT_SYMBOL(ecard_setirq); +void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res, + unsigned long offset, unsigned long maxsize) +{ + unsigned long start = ecard_resource_start(ec, res); + unsigned long end = ecard_resource_end(ec, res); + + if (offset > (end - start)) + return NULL; + + start += offset; + if (maxsize && end - start > maxsize) + end = start + maxsize; + + return devm_ioremap(&ec->dev, start, end - start); +} +EXPORT_SYMBOL(ecardm_iomap); + /* * Probe for an expansion card. * diff --git a/drivers/ata/pata_icside.c b/drivers/ata/pata_icside.c index d7621a39ed09..d323e75b05d5 100644 --- a/drivers/ata/pata_icside.c +++ b/drivers/ata/pata_icside.c @@ -425,8 +425,7 @@ pata_icside_register_v5(struct ata_probe_ent *ae, struct expansion_card *ec) struct pata_icside_state *state = ae->private_data; void __iomem *base; - base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), - ecard_resource_len(ec, ECARD_RES_MEMC)); + base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0); if (!base) return -ENOMEM; @@ -453,24 +452,17 @@ pata_icside_register_v6(struct ata_probe_ent *ae, struct expansion_card *ec) struct pata_icside_state *state = ae->private_data; void __iomem *ioc_base, *easi_base; unsigned int sel = 0; - int ret; - ioc_base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), - ecard_resource_len(ec, ECARD_RES_IOCFAST)); - if (!ioc_base) { - ret = -ENOMEM; - goto out; - } + ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); + if (!ioc_base) + return -ENOMEM; easi_base = ioc_base; if (ecard_resource_flags(ec, ECARD_RES_EASI)) { - easi_base = ioremap(ecard_resource_start(ec, ECARD_RES_EASI), - ecard_resource_len(ec, ECARD_RES_EASI)); - if (!easi_base) { - ret = -ENOMEM; - goto unmap_slot; - } + easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0); + if (!easi_base) + return -ENOMEM; /* * Enable access to the EASI region. @@ -507,10 +499,6 @@ pata_icside_register_v6(struct ata_probe_ent *ae, struct expansion_card *ec) return icside_dma_init(ae, ec); - unmap_slot: - iounmap(ioc_base); - out: - return ret; } static int __devinit @@ -534,8 +522,7 @@ pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id) state->type = ICS_TYPE_NOTYPE; state->dma = NO_DMA; - idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), - ecard_resource_len(ec, ECARD_RES_IOCFAST)); + idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); if (idmem) { unsigned int type; @@ -543,7 +530,7 @@ pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id) type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1; type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2; type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3; - iounmap(idmem); + ecardm_iounmap(ec, idmem); state->type = type; } @@ -638,10 +625,6 @@ static void __devexit pata_icside_remove(struct expansion_card *ec) */ if (state->dma != NO_DMA) free_dma(state->dma); - if (state->ioc_base) - iounmap(state->ioc_base); - if (state->ioc_base != state->irq_port) - iounmap(state->irq_port); kfree(state); ecard_release_resources(ec); diff --git a/drivers/ide/arm/icside.c b/drivers/ide/arm/icside.c index 69c949ea93e3..66f826252aee 100644 --- a/drivers/ide/arm/icside.c +++ b/drivers/ide/arm/icside.c @@ -565,8 +565,7 @@ icside_register_v5(struct icside_state *state, struct expansion_card *ec) ide_hwif_t *hwif; void __iomem *base; - base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), - ecard_resource_len(ec, ECARD_RES_MEMC)); + base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); if (!base) return -ENOMEM; @@ -583,10 +582,8 @@ icside_register_v5(struct icside_state *state, struct expansion_card *ec) icside_irqdisable_arcin_v5(ec, 0); hwif = icside_setup(base, &icside_cardinfo_v5, ec); - if (!hwif) { - iounmap(base); + if (!hwif) return -ENODEV; - } state->hwif[0] = hwif; @@ -605,8 +602,7 @@ icside_register_v6(struct icside_state *state, struct expansion_card *ec) unsigned int sel = 0; int ret; - ioc_base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), - ecard_resource_len(ec, ECARD_RES_IOCFAST)); + ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); if (!ioc_base) { ret = -ENOMEM; goto out; @@ -615,11 +611,10 @@ icside_register_v6(struct icside_state *state, struct expansion_card *ec) easi_base = ioc_base; if (ecard_resource_flags(ec, ECARD_RES_EASI)) { - easi_base = ioremap(ecard_resource_start(ec, ECARD_RES_EASI), - ecard_resource_len(ec, ECARD_RES_EASI)); + easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0); if (!easi_base) { ret = -ENOMEM; - goto unmap_slot; + goto out; } /* @@ -648,7 +643,7 @@ icside_register_v6(struct icside_state *state, struct expansion_card *ec) if (!hwif || !mate) { ret = -ENODEV; - goto unmap_port; + goto out; } state->hwif[0] = hwif; @@ -685,11 +680,6 @@ icside_register_v6(struct icside_state *state, struct expansion_card *ec) return 0; - unmap_port: - if (easi_base != ioc_base) - iounmap(easi_base); - unmap_slot: - iounmap(ioc_base); out: return ret; } @@ -715,8 +705,7 @@ icside_probe(struct expansion_card *ec, const struct ecard_id *id) state->type = ICS_TYPE_NOTYPE; state->dev = &ec->dev; - idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), - ecard_resource_len(ec, ECARD_RES_IOCFAST)); + idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); if (idmem) { unsigned int type; @@ -724,7 +713,7 @@ icside_probe(struct expansion_card *ec, const struct ecard_id *id) type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1; type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2; type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3; - iounmap(idmem); + ecardm_iounmap(ec, idmem); state->type = type; } @@ -793,11 +782,6 @@ static void __devexit icside_remove(struct expansion_card *ec) ecard_set_drvdata(ec, NULL); - if (state->ioc_base) - iounmap(state->ioc_base); - if (state->ioc_base != state->irq_port) - iounmap(state->irq_port); - kfree(state); ecard_release_resources(ec); } diff --git a/drivers/ide/arm/rapide.c b/drivers/ide/arm/rapide.c index 890ea3fac3c6..83811af11610 100644 --- a/drivers/ide/arm/rapide.c +++ b/drivers/ide/arm/rapide.c @@ -63,8 +63,7 @@ rapide_probe(struct expansion_card *ec, const struct ecard_id *id) if (ret) goto out; - base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), - ecard_resource_len(ec, ECARD_RES_MEMC)); + base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); if (!base) { ret = -ENOMEM; goto release; @@ -81,7 +80,6 @@ rapide_probe(struct expansion_card *ec, const struct ecard_id *id) goto out; } - iounmap(base); release: ecard_release_resources(ec); out: @@ -96,7 +94,6 @@ static void __devexit rapide_remove(struct expansion_card *ec) /* there must be a better way */ ide_unregister(hwif - ide_hwifs); - iounmap(hwif->hwif_data); ecard_release_resources(ec); } diff --git a/drivers/net/arm/ether1.c b/drivers/net/arm/ether1.c index f075cebe84ad..f21148e7b579 100644 --- a/drivers/net/arm/ether1.c +++ b/drivers/net/arm/ether1.c @@ -1014,8 +1014,7 @@ ether1_probe(struct expansion_card *ec, const struct ecard_id *id) SET_NETDEV_DEV(dev, &ec->dev); dev->irq = ec->irq; - priv(dev)->base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), - ecard_resource_len(ec, ECARD_RES_IOCFAST)); + priv(dev)->base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); if (!priv(dev)->base) { ret = -ENOMEM; goto free; @@ -1056,8 +1055,6 @@ ether1_probe(struct expansion_card *ec, const struct ecard_id *id) return 0; free: - if (priv(dev)->base) - iounmap(priv(dev)->base); free_netdev(dev); release: ecard_release_resources(ec); @@ -1072,7 +1069,6 @@ static void __devexit ether1_remove(struct expansion_card *ec) ecard_set_drvdata(ec, NULL); unregister_netdev(dev); - iounmap(priv(dev)->base); free_netdev(dev); ecard_release_resources(ec); } diff --git a/drivers/net/arm/ether3.c b/drivers/net/arm/ether3.c index 32da2eb9bcee..da713500654d 100644 --- a/drivers/net/arm/ether3.c +++ b/drivers/net/arm/ether3.c @@ -793,8 +793,7 @@ ether3_probe(struct expansion_card *ec, const struct ecard_id *id) SET_MODULE_OWNER(dev); SET_NETDEV_DEV(dev, &ec->dev); - priv(dev)->base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), - ecard_resource_len(ec, ECARD_RES_MEMC)); + priv(dev)->base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); if (!priv(dev)->base) { ret = -ENOMEM; goto free; @@ -869,8 +868,6 @@ ether3_probe(struct expansion_card *ec, const struct ecard_id *id) return 0; free: - if (priv(dev)->base) - iounmap(priv(dev)->base); free_netdev(dev); release: ecard_release_resources(ec); @@ -885,7 +882,6 @@ static void __devexit ether3_remove(struct expansion_card *ec) ecard_set_drvdata(ec, NULL); unregister_netdev(dev); - iounmap(priv(dev)->base); free_netdev(dev); ecard_release_resources(ec); } diff --git a/drivers/net/arm/etherh.c b/drivers/net/arm/etherh.c index 387f1e3a4e84..769ba69451f4 100644 --- a/drivers/net/arm/etherh.c +++ b/drivers/net/arm/etherh.c @@ -686,7 +686,7 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id) eh->supported = data->supported; eh->ctrl = 0; eh->id = ec->cid.product; - eh->memc = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), PAGE_SIZE); + eh->memc = ecardm_iomap(ec, ECARD_RES_MEMC, 0, PAGE_SIZE); if (!eh->memc) { ret = -ENOMEM; goto free; @@ -694,7 +694,7 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id) eh->ctrl_port = eh->memc; if (data->ctrl_ioc) { - eh->ioc_fast = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST), PAGE_SIZE); + eh->ioc_fast = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, PAGE_SIZE); if (!eh->ioc_fast) { ret = -ENOMEM; goto free; @@ -758,10 +758,6 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id) return 0; free: - if (eh->ioc_fast) - iounmap(eh->ioc_fast); - if (eh->memc) - iounmap(eh->memc); free_netdev(dev); release: ecard_release_resources(ec); @@ -772,16 +768,11 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id) static void __devexit etherh_remove(struct expansion_card *ec) { struct net_device *dev = ecard_get_drvdata(ec); - struct etherh_priv *eh = etherh_priv(dev); ecard_set_drvdata(ec, NULL); unregister_netdev(dev); - if (eh->ioc_fast) - iounmap(eh->ioc_fast); - iounmap(eh->memc); - free_netdev(dev); ecard_release_resources(ec); diff --git a/drivers/scsi/arm/arxescsi.c b/drivers/scsi/arm/arxescsi.c index 7e132c5bacf8..2836fe248df9 100644 --- a/drivers/scsi/arm/arxescsi.c +++ b/drivers/scsi/arm/arxescsi.c @@ -281,7 +281,6 @@ arxescsi_probe(struct expansion_card *ec, const struct ecard_id *id) { struct Scsi_Host *host; struct arxescsi_info *info; - unsigned long resbase, reslen; void __iomem *base; int ret; @@ -289,9 +288,7 @@ arxescsi_probe(struct expansion_card *ec, const struct ecard_id *id) if (ret) goto out; - resbase = ecard_resource_start(ec, ECARD_RES_MEMC); - reslen = ecard_resource_len(ec, ECARD_RES_MEMC); - base = ioremap(resbase, reslen); + base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); if (!base) { ret = -ENOMEM; goto out_region; @@ -300,7 +297,7 @@ arxescsi_probe(struct expansion_card *ec, const struct ecard_id *id) host = scsi_host_alloc(&arxescsi_template, sizeof(struct arxescsi_info)); if (!host) { ret = -ENOMEM; - goto out_unmap; + goto out_region; } info = (struct arxescsi_info *)host->hostdata; @@ -337,8 +334,6 @@ arxescsi_probe(struct expansion_card *ec, const struct ecard_id *id) fas216_release(host); out_unregister: scsi_host_put(host); - out_unmap: - iounmap(base); out_region: ecard_release_resources(ec); out: @@ -348,13 +343,10 @@ arxescsi_probe(struct expansion_card *ec, const struct ecard_id *id) static void __devexit arxescsi_remove(struct expansion_card *ec) { struct Scsi_Host *host = ecard_get_drvdata(ec); - struct arxescsi_info *info = (struct arxescsi_info *)host->hostdata; ecard_set_drvdata(ec, NULL); fas216_remove(host); - iounmap(info->base); - fas216_release(host); scsi_host_put(host); ecard_release_resources(ec); diff --git a/drivers/scsi/arm/cumana_2.c b/drivers/scsi/arm/cumana_2.c index f51aa3446bc7..68a64123af8f 100644 --- a/drivers/scsi/arm/cumana_2.c +++ b/drivers/scsi/arm/cumana_2.c @@ -401,7 +401,6 @@ cumanascsi2_probe(struct expansion_card *ec, const struct ecard_id *id) { struct Scsi_Host *host; struct cumanascsi2_info *info; - unsigned long resbase, reslen; void __iomem *base; int ret; @@ -409,9 +408,7 @@ cumanascsi2_probe(struct expansion_card *ec, const struct ecard_id *id) if (ret) goto out; - resbase = ecard_resource_start(ec, ECARD_RES_MEMC); - reslen = ecard_resource_len(ec, ECARD_RES_MEMC); - base = ioremap(resbase, reslen); + base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); if (!base) { ret = -ENOMEM; goto out_region; @@ -421,7 +418,7 @@ cumanascsi2_probe(struct expansion_card *ec, const struct ecard_id *id) sizeof(struct cumanascsi2_info)); if (!host) { ret = -ENOMEM; - goto out_unmap; + goto out_region; } ecard_set_drvdata(ec, host); @@ -490,9 +487,6 @@ cumanascsi2_probe(struct expansion_card *ec, const struct ecard_id *id) out_free: scsi_host_put(host); - out_unmap: - iounmap(base); - out_region: ecard_release_resources(ec); @@ -512,8 +506,6 @@ static void __devexit cumanascsi2_remove(struct expansion_card *ec) free_dma(info->info.scsi.dma); free_irq(ec->irq, info); - iounmap(info->base); - fas216_release(host); scsi_host_put(host); ecard_release_resources(ec); diff --git a/drivers/scsi/arm/eesox.c b/drivers/scsi/arm/eesox.c index cc5d513aa99a..bb2477b3fb0b 100644 --- a/drivers/scsi/arm/eesox.c +++ b/drivers/scsi/arm/eesox.c @@ -519,7 +519,6 @@ eesoxscsi_probe(struct expansion_card *ec, const struct ecard_id *id) { struct Scsi_Host *host; struct eesoxscsi_info *info; - unsigned long resbase, reslen; void __iomem *base; int ret; @@ -527,9 +526,7 @@ eesoxscsi_probe(struct expansion_card *ec, const struct ecard_id *id) if (ret) goto out; - resbase = ecard_resource_start(ec, ECARD_RES_IOCFAST); - reslen = ecard_resource_len(ec, ECARD_RES_IOCFAST); - base = ioremap(resbase, reslen); + base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); if (!base) { ret = -ENOMEM; goto out_region; @@ -539,7 +536,7 @@ eesoxscsi_probe(struct expansion_card *ec, const struct ecard_id *id) sizeof(struct eesoxscsi_info)); if (!host) { ret = -ENOMEM; - goto out_unmap; + goto out_region; } ecard_set_drvdata(ec, host); @@ -612,9 +609,6 @@ eesoxscsi_probe(struct expansion_card *ec, const struct ecard_id *id) device_remove_file(&ec->dev, &dev_attr_bus_term); scsi_host_put(host); - out_unmap: - iounmap(base); - out_region: ecard_release_resources(ec); @@ -636,8 +630,6 @@ static void __devexit eesoxscsi_remove(struct expansion_card *ec) device_remove_file(&ec->dev, &dev_attr_bus_term); - iounmap(info->base); - fas216_release(host); scsi_host_put(host); ecard_release_resources(ec); diff --git a/drivers/scsi/arm/powertec.c b/drivers/scsi/arm/powertec.c index 3cbd525b58c5..d9a546d1917c 100644 --- a/drivers/scsi/arm/powertec.c +++ b/drivers/scsi/arm/powertec.c @@ -313,7 +313,6 @@ powertecscsi_probe(struct expansion_card *ec, const struct ecard_id *id) { struct Scsi_Host *host; struct powertec_info *info; - unsigned long resbase, reslen; void __iomem *base; int ret; @@ -321,9 +320,7 @@ powertecscsi_probe(struct expansion_card *ec, const struct ecard_id *id) if (ret) goto out; - resbase = ecard_resource_start(ec, ECARD_RES_IOCFAST); - reslen = ecard_resource_len(ec, ECARD_RES_IOCFAST); - base = ioremap(resbase, reslen); + base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); if (!base) { ret = -ENOMEM; goto out_region; @@ -333,7 +330,7 @@ powertecscsi_probe(struct expansion_card *ec, const struct ecard_id *id) sizeof (struct powertec_info)); if (!host) { ret = -ENOMEM; - goto out_unmap; + goto out_region; } ecard_set_drvdata(ec, host); @@ -404,9 +401,6 @@ powertecscsi_probe(struct expansion_card *ec, const struct ecard_id *id) device_remove_file(&ec->dev, &dev_attr_bus_term); scsi_host_put(host); - out_unmap: - iounmap(base); - out_region: ecard_release_resources(ec); @@ -428,8 +422,6 @@ static void __devexit powertecscsi_remove(struct expansion_card *ec) free_dma(info->info.scsi.dma); free_irq(ec->irq, info); - iounmap(info->base); - fas216_release(host); scsi_host_put(host); ecard_release_resources(ec); diff --git a/drivers/serial/8250_acorn.c b/drivers/serial/8250_acorn.c index 562ba745a044..b0ce8c56f1a4 100644 --- a/drivers/serial/8250_acorn.c +++ b/drivers/serial/8250_acorn.c @@ -54,7 +54,7 @@ serial_card_probe(struct expansion_card *ec, const struct ecard_id *id) info->num_ports = type->num_ports; bus_addr = ecard_resource_start(ec, type->type); - info->vaddr = ioremap(bus_addr, ecard_resource_len(ec, type->type)); + info->vaddr = ecardm_iomap(ec, type->type, 0, 0); if (!info->vaddr) { kfree(info); return -ENOMEM; @@ -91,7 +91,6 @@ static void __devexit serial_card_remove(struct expansion_card *ec) if (info->ports[i] > 0) serial8250_unregister_port(info->ports[i]); - iounmap(info->vaddr); kfree(info); } diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h index 8f1000eac91f..684fe0645239 100644 --- a/include/asm-arm/ecard.h +++ b/include/asm-arm/ecard.h @@ -226,6 +226,10 @@ ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed) extern int ecard_request_resources(struct expansion_card *ec); extern void ecard_release_resources(struct expansion_card *ec); +void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res, + unsigned long offset, unsigned long maxsize); +#define ecardm_iounmap(__ec, __addr) devm_iounmap(&(__ec)->dev, __addr) + extern struct bus_type ecard_bus_type; #define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev) -- cgit v1.2.3 From b8b6970b4fe08397554295b0c5169bec7575f7c9 Mon Sep 17 00:00:00 2001 From: Graeme Gregory Date: Wed, 9 May 2007 15:55:24 +0100 Subject: [ARM] 4365/1: Add AC97 clock to s3c2443 machine This adds the ac97 clock to the s3c2443 machine files. It seems to have been simply missed out previously. Signed-off-by: Graeme Gregory Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2443/clock.c | 4 ++++ include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h | 1 + 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index dd2272fb1131..0b6e360aeae7 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -791,6 +791,10 @@ static struct clk init_clocks[] = { .name = "usb-bus-host", .id = -1, .parent = &clk_usb_bus_host, + }, { .name = "ac97", + .id = -1, + .parent = &clk_p, + .ctrlbit = S3C2443_PCLKCON_AC97, } }; diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h index cd9e26568f85..c1414658d1c5 100644 --- a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h @@ -129,6 +129,7 @@ #define S3C2443_PCLKCON_IIC (1<<4) #define S3C2443_PCLKCON_SDI (1<<5) #define S3C2443_PCLKCON_ADC (1<<7) +#define S3C2443_PCLKCON_AC97 (1<<8) #define S3C2443_PCLKCON_IIS (1<<9) #define S3C2443_PCLKCON_PWMT (1<<10) #define S3C2443_PCLKCON_WDT (1<<11) -- cgit v1.2.3 From f75fd965d500d33720948f30d409c6c7729a80af Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 9 May 2007 20:21:11 +0100 Subject: [ARM] Fix iop32x/iop33x build arch/arm/plat-iop/io.c:26: error: conflicting types for '__iop3xx_ioremap' Signed-off-by: Russell King --- include/asm-arm/arch-iop13xx/io.h | 2 +- include/asm-arm/arch-iop32x/io.h | 2 +- include/asm-arm/arch-iop33x/io.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h index 7dfff4ad82b3..a6e0f9e6ddcf 100644 --- a/include/asm-arm/arch-iop13xx/io.h +++ b/include/asm-arm/arch-iop13xx/io.h @@ -27,7 +27,7 @@ extern void __iomem * __iop13xx_io(unsigned long io_addr); extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop13xx_iounmap(void __iomem *addr); extern u32 iop13xx_atue_mem_base; diff --git a/include/asm-arm/arch-iop32x/io.h b/include/asm-arm/arch-iop32x/io.h index 994f16af5057..958af751a484 100644 --- a/include/asm-arm/arch-iop32x/io.h +++ b/include/asm-arm/arch-iop32x/io.h @@ -14,7 +14,7 @@ #include extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop3xx_iounmap(void __iomem *addr); #define IO_SPACE_LIMIT 0xffffffff diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h index 993f7589b29f..fec9c53e2b10 100644 --- a/include/asm-arm/arch-iop33x/io.h +++ b/include/asm-arm/arch-iop33x/io.h @@ -14,7 +14,7 @@ #include extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop3xx_iounmap(void __iomem *addr); #define IO_SPACE_LIMIT 0xffffffff -- cgit v1.2.3 From 030f4810e782e541468d36c27e721b582b7820a4 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Fri, 11 May 2007 13:21:27 +0100 Subject: [ARM] 4369/1: AT91: Fix circular dependency in header files Resolve the circular dependency in the AT91 header files (io.h and hardware.h) by moving the at91_sys_read() and at91_sys_write() functions to io.h Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/hardware.h | 17 ----------------- include/asm-arm/arch-at91/io.h | 18 ++++++++++++++++++ include/asm-arm/arch-at91/irqs.h | 1 + include/asm-arm/arch-at91/uncompress.h | 2 +- 4 files changed, 20 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 28133e0154dd..1c14382dc3f5 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -69,22 +69,5 @@ /* Clocks */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ -#ifndef __ASSEMBLY__ -#include - -static inline unsigned int at91_sys_read(unsigned int reg_offset) -{ - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; - - return __raw_readl(addr + reg_offset); -} - -static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) -{ - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; - - __raw_writel(value, addr + reg_offset); -} -#endif #endif diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h index 401f327ec047..80073fd36b8e 100644 --- a/include/asm-arm/arch-at91/io.h +++ b/include/asm-arm/arch-at91/io.h @@ -29,4 +29,22 @@ #define __mem_pci(a) (a) +#ifndef __ASSEMBLY__ + +static inline unsigned int at91_sys_read(unsigned int reg_offset) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + return __raw_readl(addr + reg_offset); +} + +static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + __raw_writel(value, addr + reg_offset); +} + +#endif + #endif diff --git a/include/asm-arm/arch-at91/irqs.h b/include/asm-arm/arch-at91/irqs.h index 1ffa3bb9a9c1..1127a3b5e928 100644 --- a/include/asm-arm/arch-at91/irqs.h +++ b/include/asm-arm/arch-at91/irqs.h @@ -21,6 +21,7 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H +#include #include #define NR_AIC_IRQS 32 diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h index a193d28304b6..30ac587b3b41 100644 --- a/include/asm-arm/arch-at91/uncompress.h +++ b/include/asm-arm/arch-at91/uncompress.h @@ -21,7 +21,7 @@ #ifndef __ASM_ARCH_UNCOMPRESS_H #define __ASM_ARCH_UNCOMPRESS_H -#include +#include #include /* -- cgit v1.2.3 From 7c6337e225364870e9bf02a3ae277d9fdea483f8 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 30 Apr 2007 19:37:19 +0100 Subject: [ARM] 4303/3: base kernel support for TI DaVinci Add base kernel support for the TI DaVinci platform. This patch only includes interrupts, timers, CPU identification, serial support and basic power and sleep controller init. More drivers to come. Signed-off-by: Kevin Hilman Signed-off-by: Russell King --- arch/arm/Kconfig | 11 +- arch/arm/Makefile | 1 + arch/arm/mach-davinci/Kconfig | 23 ++ arch/arm/mach-davinci/Makefile | 10 + arch/arm/mach-davinci/Makefile.boot | 3 + arch/arm/mach-davinci/board-evm.c | 131 ++++++++++ arch/arm/mach-davinci/id.c | 94 ++++++++ arch/arm/mach-davinci/io.c | 51 ++++ arch/arm/mach-davinci/irq.c | 226 ++++++++++++++++++ arch/arm/mach-davinci/psc.c | 113 +++++++++ arch/arm/mach-davinci/serial.c | 96 ++++++++ arch/arm/mach-davinci/time.c | 372 +++++++++++++++++++++++++++++ arch/arm/mm/Kconfig | 4 +- include/asm-arm/arch-davinci/common.h | 19 ++ include/asm-arm/arch-davinci/debug-macro.S | 21 ++ include/asm-arm/arch-davinci/dma.h | 16 ++ include/asm-arm/arch-davinci/entry-macro.S | 32 +++ include/asm-arm/arch-davinci/hardware.h | 14 ++ include/asm-arm/arch-davinci/io.h | 79 ++++++ include/asm-arm/arch-davinci/irqs.h | 105 ++++++++ include/asm-arm/arch-davinci/memory.h | 64 +++++ include/asm-arm/arch-davinci/psc.h | 76 ++++++ include/asm-arm/arch-davinci/serial.h | 20 ++ include/asm-arm/arch-davinci/system.h | 29 +++ include/asm-arm/arch-davinci/timex.h | 17 ++ include/asm-arm/arch-davinci/uncompress.h | 35 +++ include/asm-arm/arch-davinci/vmalloc.h | 15 ++ 27 files changed, 1674 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-davinci/Kconfig create mode 100644 arch/arm/mach-davinci/Makefile create mode 100644 arch/arm/mach-davinci/Makefile.boot create mode 100644 arch/arm/mach-davinci/board-evm.c create mode 100644 arch/arm/mach-davinci/id.c create mode 100644 arch/arm/mach-davinci/io.c create mode 100644 arch/arm/mach-davinci/irq.c create mode 100644 arch/arm/mach-davinci/psc.c create mode 100644 arch/arm/mach-davinci/serial.c create mode 100644 arch/arm/mach-davinci/time.c create mode 100644 include/asm-arm/arch-davinci/common.h create mode 100644 include/asm-arm/arch-davinci/debug-macro.S create mode 100644 include/asm-arm/arch-davinci/dma.h create mode 100644 include/asm-arm/arch-davinci/entry-macro.S create mode 100644 include/asm-arm/arch-davinci/hardware.h create mode 100644 include/asm-arm/arch-davinci/io.h create mode 100644 include/asm-arm/arch-davinci/irqs.h create mode 100644 include/asm-arm/arch-davinci/memory.h create mode 100644 include/asm-arm/arch-davinci/psc.h create mode 100644 include/asm-arm/arch-davinci/serial.h create mode 100644 include/asm-arm/arch-davinci/system.h create mode 100644 include/asm-arm/arch-davinci/timex.h create mode 100644 include/asm-arm/arch-davinci/uncompress.h create mode 100644 include/asm-arm/arch-davinci/vmalloc.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d7c0984d4a86..34d1462e4341 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -384,6 +384,13 @@ config ARCH_OMAP help Support for TI's OMAP platform (OMAP1 and OMAP2). +config ARCH_DAVINCI + bool "TI DaVinci" + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + help + Support for TI's DaVinci platform. + endchoice source "arch/arm/mach-clps711x/Kconfig" @@ -445,6 +452,8 @@ source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-ns9xxx/Kconfig" +source "arch/arm/mach-davinci/Kconfig" + # Definitions to make life easier config ARCH_ACORN bool @@ -674,7 +683,7 @@ config LEDS ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ - ARCH_AT91 || MACH_TRIZEPS4 + ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI help If you say Y here, the LEDs on your machine will be used to provide useful information about your current system status. diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 00ea4305ad5d..d568d86b0729 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -135,6 +135,7 @@ endif machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000 + machine-$(CONFIG_ARCH_DAVINCI) := davinci ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig new file mode 100644 index 000000000000..bac988e7a4c3 --- /dev/null +++ b/arch/arm/mach-davinci/Kconfig @@ -0,0 +1,23 @@ +if ARCH_DAVINCI + +menu "TI DaVinci Implementations" + +comment "DaVinci Core Type" + +config ARCH_DAVINCI644x + default y + bool "DaVinci 644x based system" + +comment "DaVinci Board Type" + +config MACH_DAVINCI_EVM + bool "TI DaVinci EVM" + default y + depends on ARCH_DAVINCI644x + help + Configure this option to specify the whether the board used + for development is a DaVinci EVM + +endmenu + +endif diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile new file mode 100644 index 000000000000..a8f88cd29905 --- /dev/null +++ b/arch/arm/mach-davinci/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the linux kernel. +# +# + +# Common objects +obj-y := time.o irq.o serial.o io.o id.o psc.o + +# Board specific +obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot new file mode 100644 index 000000000000..e1dd366f836b --- /dev/null +++ b/arch/arm/mach-davinci/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x80008000 +params_phys-y := 0x80000100 +initrd_phys-y := 0x80800000 diff --git a/arch/arm/mach-davinci/board-evm.c b/arch/arm/mach-davinci/board-evm.c new file mode 100644 index 000000000000..633c12e43044 --- /dev/null +++ b/arch/arm/mach-davinci/board-evm.c @@ -0,0 +1,131 @@ +/* + * TI DaVinci EVM board support + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* other misc. init functions */ +void __init davinci_psc_init(void); +void __init davinci_irq_init(void); +void __init davinci_map_common_io(void); + +/* NOR Flash base address set to CS0 by default */ +#define NOR_FLASH_PHYS 0x02000000 + +static struct mtd_partition davinci_evm_partitions[] = { + /* bootloader (U-Boot, etc) in first 4 sectors */ + { + .name = "bootloader", + .offset = 0, + .size = 4 * SZ_64K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* bootloader params in the next 1 sectors */ + { + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = SZ_64K, + .mask_flags = 0, + }, + /* kernel */ + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M, + .mask_flags = 0 + }, + /* file system */ + { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0 + } +}; + +static struct physmap_flash_data davinci_evm_flash_data = { + .width = 2, + .parts = davinci_evm_partitions, + .nr_parts = ARRAY_SIZE(davinci_evm_partitions), +}; + +/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF + * limits addresses to 16M, so using addresses past 16M will wrap */ +static struct resource davinci_evm_flash_resource = { + .start = NOR_FLASH_PHYS, + .end = NOR_FLASH_PHYS + SZ_16M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device davinci_evm_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &davinci_evm_flash_data, + }, + .num_resources = 1, + .resource = &davinci_evm_flash_resource, +}; + +static struct platform_device *davinci_evm_devices[] __initdata = { + &davinci_evm_flash_device, +}; + +static void __init +davinci_evm_map_io(void) +{ + davinci_map_common_io(); +} + +static __init void davinci_evm_init(void) +{ + davinci_psc_init(); + +#if defined(CONFIG_BLK_DEV_DAVINCI) || defined(CONFIG_BLK_DEV_DAVINCI_MODULE) + printk(KERN_WARNING "WARNING: both IDE and NOR flash are enabled, " + "but share pins.\n\t Disable IDE for NOR support.\n"); +#endif + + platform_add_devices(davinci_evm_devices, + ARRAY_SIZE(davinci_evm_devices)); +} + +static __init void davinci_evm_irq_init(void) +{ + davinci_irq_init(); +} + +MACHINE_START(DAVINCI_EVM, "DaVinci EVM") + /* Maintainer: MontaVista Software */ + .phys_io = IO_PHYS, + .io_pg_offst = (io_p2v(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (DAVINCI_DDR_BASE + 0x100), + .map_io = davinci_evm_map_io, + .init_irq = davinci_evm_irq_init, + .timer = &davinci_timer, + .init_machine = davinci_evm_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/id.c b/arch/arm/mach-davinci/id.c new file mode 100644 index 000000000000..70608f76aed8 --- /dev/null +++ b/arch/arm/mach-davinci/id.c @@ -0,0 +1,94 @@ +/* + * Davinci CPU identification code + * + * Copyright (C) 2006 Komal Shah + * + * Derived from OMAP1 CPU identification code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#define JTAG_ID_BASE 0x01c40028 + +struct davinci_id { + u8 variant; /* JTAG ID bits 31:28 */ + u16 part_no; /* JTAG ID bits 27:12 */ + u32 manufacturer; /* JTAG ID bits 11:1 */ + u32 type; /* Cpu id bits [31:8], cpu class bits [7:0] */ +}; + +/* Register values to detect the DaVinci version */ +static struct davinci_id davinci_ids[] __initdata = { + { + /* DM6446 */ + .part_no = 0xb700, + .variant = 0x0, + .manufacturer = 0x017, + .type = 0x64460000, + }, +}; + +/* + * Get Device Part No. from JTAG ID register + */ +static u16 __init davinci_get_part_no(void) +{ + u32 dev_id, part_no; + + dev_id = davinci_readl(JTAG_ID_BASE); + + part_no = ((dev_id >> 12) & 0xffff); + + return part_no; +} + +/* + * Get Device Revision from JTAG ID register + */ +static u8 __init davinci_get_variant(void) +{ + u32 variant; + + variant = davinci_readl(JTAG_ID_BASE); + + variant = (variant >> 28) & 0xf; + + return variant; +} + +void __init davinci_check_revision(void) +{ + int i; + u16 part_no; + u8 variant; + + part_no = davinci_get_part_no(); + variant = davinci_get_variant(); + + /* First check only the major version in a safe way */ + for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { + if (part_no == (davinci_ids[i].part_no)) { + system_rev = davinci_ids[i].type; + break; + } + } + + /* Check if we can find the dev revision */ + for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { + if (part_no == davinci_ids[i].part_no && + variant == davinci_ids[i].variant) { + system_rev = davinci_ids[i].type; + break; + } + } + + printk("DaVinci DM%04x variant 0x%x\n", system_rev >> 16, variant); +} diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c new file mode 100644 index 000000000000..87fae6fb6ecf --- /dev/null +++ b/arch/arm/mach-davinci/io.c @@ -0,0 +1,51 @@ +/* + * DaVinci I/O mapping code + * + * Copyright (C) 2005-2006 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include +#include + +#include + +extern void davinci_check_revision(void); + +/* + * The machine specific code may provide the extra mapping besides the + * default mapping provided here. + */ +static struct map_desc davinci_io_desc[] __initdata = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, +}; + +void __init davinci_map_common_io(void) +{ + iotable_init(davinci_io_desc, ARRAY_SIZE(davinci_io_desc)); + + /* Normally devicemaps_init() would flush caches and tlb after + * mdesc->map_io(), but we must also do it here because of the CPU + * revision check below. + */ + local_flush_tlb_all(); + flush_cache_all(); + + /* We want to check CPU revision early for cpu_is_xxxx() macros. + * IO space mapping must be initialized before we can do that. + */ + davinci_check_revision(); +} diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c new file mode 100644 index 000000000000..1333d84d2e45 --- /dev/null +++ b/arch/arm/mach-davinci/irq.c @@ -0,0 +1,226 @@ +/* + * Interrupt handler for DaVinci boards. + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include + +#include +#include +#include + +#define IRQ_BIT(irq) ((irq) & 0x1f) + +#define FIQ_REG0_OFFSET 0x0000 +#define FIQ_REG1_OFFSET 0x0004 +#define IRQ_REG0_OFFSET 0x0008 +#define IRQ_REG1_OFFSET 0x000C +#define IRQ_ENT_REG0_OFFSET 0x0018 +#define IRQ_ENT_REG1_OFFSET 0x001C +#define IRQ_INCTL_REG_OFFSET 0x0020 +#define IRQ_EABASE_REG_OFFSET 0x0024 +#define IRQ_INTPRI0_REG_OFFSET 0x0030 +#define IRQ_INTPRI7_REG_OFFSET 0x004C + +static inline unsigned int davinci_irq_readl(int offset) +{ + return davinci_readl(DAVINCI_ARM_INTC_BASE + offset); +} + +static inline void davinci_irq_writel(unsigned long value, int offset) +{ + davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset); +} + +/* Disable interrupt */ +static void davinci_mask_irq(unsigned int irq) +{ + unsigned int mask; + u32 l; + + mask = 1 << IRQ_BIT(irq); + + if (irq > 31) { + l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); + l &= ~mask; + davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); + } else { + l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); + l &= ~mask; + davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); + } +} + +/* Enable interrupt */ +static void davinci_unmask_irq(unsigned int irq) +{ + unsigned int mask; + u32 l; + + mask = 1 << IRQ_BIT(irq); + + if (irq > 31) { + l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); + l |= mask; + davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); + } else { + l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); + l |= mask; + davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); + } +} + +/* EOI interrupt */ +static void davinci_ack_irq(unsigned int irq) +{ + unsigned int mask; + + mask = 1 << IRQ_BIT(irq); + + if (irq > 31) + davinci_irq_writel(mask, IRQ_REG1_OFFSET); + else + davinci_irq_writel(mask, IRQ_REG0_OFFSET); +} + +static struct irq_chip davinci_irq_chip_0 = { + .name = "AINTC", + .ack = davinci_ack_irq, + .mask = davinci_mask_irq, + .unmask = davinci_unmask_irq, +}; + + +/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ +static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { + [IRQ_VDINT0] = 2, + [IRQ_VDINT1] = 6, + [IRQ_VDINT2] = 6, + [IRQ_HISTINT] = 6, + [IRQ_H3AINT] = 6, + [IRQ_PRVUINT] = 6, + [IRQ_RSZINT] = 6, + [7] = 7, + [IRQ_VENCINT] = 6, + [IRQ_ASQINT] = 6, + [IRQ_IMXINT] = 6, + [IRQ_VLCDINT] = 6, + [IRQ_USBINT] = 4, + [IRQ_EMACINT] = 4, + [14] = 7, + [15] = 7, + [IRQ_CCINT0] = 5, /* dma */ + [IRQ_CCERRINT] = 5, /* dma */ + [IRQ_TCERRINT0] = 5, /* dma */ + [IRQ_TCERRINT] = 5, /* dma */ + [IRQ_PSCIN] = 7, + [21] = 7, + [IRQ_IDE] = 4, + [23] = 7, + [IRQ_MBXINT] = 7, + [IRQ_MBRINT] = 7, + [IRQ_MMCINT] = 7, + [IRQ_SDIOINT] = 7, + [28] = 7, + [IRQ_DDRINT] = 7, + [IRQ_AEMIFINT] = 7, + [IRQ_VLQINT] = 4, + [IRQ_TINT0_TINT12] = 2, /* clockevent */ + [IRQ_TINT0_TINT34] = 2, /* clocksource */ + [IRQ_TINT1_TINT12] = 7, /* DSP timer */ + [IRQ_TINT1_TINT34] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_PWMINT2] = 7, + [IRQ_I2C] = 3, + [IRQ_UARTINT0] = 3, + [IRQ_UARTINT1] = 3, + [IRQ_UARTINT2] = 3, + [IRQ_SPINT0] = 3, + [IRQ_SPINT1] = 3, + [45] = 7, + [IRQ_DSP2ARM0] = 4, + [IRQ_DSP2ARM1] = 4, + [IRQ_GPIO0] = 7, + [IRQ_GPIO1] = 7, + [IRQ_GPIO2] = 7, + [IRQ_GPIO3] = 7, + [IRQ_GPIO4] = 7, + [IRQ_GPIO5] = 7, + [IRQ_GPIO6] = 7, + [IRQ_GPIO7] = 7, + [IRQ_GPIOBNK0] = 7, + [IRQ_GPIOBNK1] = 7, + [IRQ_GPIOBNK2] = 7, + [IRQ_GPIOBNK3] = 7, + [IRQ_GPIOBNK4] = 7, + [IRQ_COMMTX] = 7, + [IRQ_COMMRX] = 7, + [IRQ_EMUINT] = 7, +}; + +/* ARM Interrupt Controller Initialization */ +void __init davinci_irq_init(void) +{ + unsigned i; + const u8 *priority = default_priorities; + + /* Clear all interrupt requests */ + davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); + davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); + + /* Disable all interrupts */ + davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET); + davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET); + + /* Interrupts disabled immediately, IRQ entry reflects all */ + davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET); + + /* we don't use the hardware vector table, just its entry addresses */ + davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET); + + /* Clear all interrupt requests */ + davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); + davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); + + for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { + unsigned j; + u32 pri; + + for (j = 0, pri = 0; j < 32; j += 4, priority++) + pri |= (*priority & 0x07) << j; + davinci_irq_writel(pri, i); + } + + /* set up genirq dispatch for ARM INTC */ + for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) { + set_irq_chip(i, &davinci_irq_chip_0); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + if (i != IRQ_TINT1_TINT34) + set_irq_handler(i, handle_edge_irq); + else + set_irq_handler(i, handle_level_irq); + } +} diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c new file mode 100644 index 000000000000..e1b0050283a6 --- /dev/null +++ b/arch/arm/mach-davinci/psc.c @@ -0,0 +1,113 @@ +/* + * TI DaVinci Power and Sleep Controller (PSC) + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include + +#include +#include +#include + +#define PTCMD __REG(0x01C41120) +#define PDSTAT __REG(0x01C41200) +#define PDCTL1 __REG(0x01C41304) +#define EPCPR __REG(0x01C41070) +#define PTSTAT __REG(0x01C41128) + +#define MDSTAT IO_ADDRESS(0x01C41800) +#define MDCTL IO_ADDRESS(0x01C41A00) + +#define PINMUX0 __REG(0x01c40000) +#define PINMUX1 __REG(0x01c40004) +#define VDD3P3V_PWDN __REG(0x01C40048) + +static void davinci_psc_mux(unsigned int id) +{ + switch (id) { + case DAVINCI_LPSC_ATA: + PINMUX0 |= (1 << 17) | (1 << 16); + break; + case DAVINCI_LPSC_MMC_SD: + /* VDD power manupulations are done in U-Boot for CPMAC + * so applies to MMC as well + */ + /*Set up the pull regiter for MMC */ + VDD3P3V_PWDN = 0x0; + PINMUX1 &= (~(1 << 9)); + break; + case DAVINCI_LPSC_I2C: + PINMUX1 |= (1 << 7); + break; + case DAVINCI_LPSC_McBSP: + PINMUX1 |= (1 << 10); + break; + default: + break; + } +} + +/* Enable or disable a PSC domain */ +void davinci_psc_config(unsigned int domain, unsigned int id, char enable) +{ + volatile unsigned int *mdstat = (unsigned int *)((int)MDSTAT + 4 * id); + volatile unsigned int *mdctl = (unsigned int *)((int)MDCTL + 4 * id); + + if (id < 0) + return; + + if (enable) + *mdctl |= 0x00000003; /* Enable Module */ + else + *mdctl &= 0xFFFFFFF2; /* Disable Module */ + + if ((PDSTAT & 0x00000001) == 0) { + PDCTL1 |= 0x1; + PTCMD = (1 << domain); + while ((((EPCPR >> domain) & 1) == 0)); + + PDCTL1 |= 0x100; + while (!(((PTSTAT >> domain) & 1) == 0)); + } else { + PTCMD = (1 << domain); + while (!(((PTSTAT >> domain) & 1) == 0)); + } + + if (enable) + while (!((*mdstat & 0x0000001F) == 0x3)); + else + while (!((*mdstat & 0x0000001F) == 0x2)); + + if (enable) + davinci_psc_mux(id); +} + +void __init davinci_psc_init(void) +{ + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSMSTR, 1); + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSSLV, 1); + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPCC, 1); + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC0, 1); + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC1, 1); + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_GPIO, 1); + + /* Turn on WatchDog timer LPSC. Needed for RESET to work */ + davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TIMER2, 1); +} diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c new file mode 100644 index 000000000000..8368c93c788d --- /dev/null +++ b/arch/arm/mach-davinci/serial.c @@ -0,0 +1,96 @@ +/* + * TI DaVinci serial driver + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define UART_DAVINCI_PWREMU 0x0c + +static inline unsigned int davinci_serial_in(struct plat_serial8250_port *up, + int offset) +{ + offset <<= up->regshift; + return (unsigned int)__raw_readb(up->membase + offset); +} + +static inline void davinci_serial_outp(struct plat_serial8250_port *p, + int offset, int value) +{ + offset <<= p->regshift; + __raw_writeb(value, p->membase + offset); +} + +static struct plat_serial8250_port serial_platform_data[] = { + { + .membase = (char *)IO_ADDRESS(DAVINCI_UART0_BASE), + .mapbase = (unsigned long)DAVINCI_UART0_BASE, + .irq = IRQ_UARTINT0, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 27000000, + }, + { + .flags = 0 + }, +}; + +static struct platform_device serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = serial_platform_data, + }, +}; + +static void __init davinci_serial_reset(struct plat_serial8250_port *p) +{ + /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */ + unsigned int pwremu = 0; + + davinci_serial_outp(p, UART_IER, 0); /* disable all interrupts */ + + davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); + mdelay(10); + + pwremu |= (0x3 << 13); + pwremu |= 0x1; + davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); +} + +static int __init davinci_init(void) +{ + davinci_serial_reset(&serial_platform_data[0]); + return platform_device_register(&serial_device); +} + +arch_initcall(davinci_init); diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c new file mode 100644 index 000000000000..4d8425de6922 --- /dev/null +++ b/arch/arm/mach-davinci/time.c @@ -0,0 +1,372 @@ +/* + * DaVinci timer subsystem + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +static struct clock_event_device clockevent_davinci; + +#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) +#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) +#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00) + +enum { + T0_BOT = 0, T0_TOP, T1_BOT, T1_TOP, NUM_TIMERS, +}; + +#define IS_TIMER1(id) (id & 0x2) +#define IS_TIMER0(id) (!IS_TIMER1(id)) +#define IS_TIMER_TOP(id) ((id & 0x1)) +#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id)) + +static int timer_irqs[NUM_TIMERS] = { + IRQ_TINT0_TINT12, + IRQ_TINT0_TINT34, + IRQ_TINT1_TINT12, + IRQ_TINT1_TINT34, +}; + +/* + * This driver configures the 2 64-bit count-up timers as 4 independent + * 32-bit count-up timers used as follows: + * + * T0_BOT: Timer 0, bottom: clockevent source for hrtimers + * T0_TOP: Timer 0, top : clocksource for generic timekeeping + * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) + * T1_TOP: Timer 1, top : + */ +#define TID_CLOCKEVENT T0_BOT +#define TID_CLOCKSOURCE T0_TOP + +/* Timer register offsets */ +#define PID12 0x0 +#define TIM12 0x10 +#define TIM34 0x14 +#define PRD12 0x18 +#define PRD34 0x1c +#define TCR 0x20 +#define TGCR 0x24 +#define WDTCR 0x28 + +/* Timer register bitfields */ +#define TCR_ENAMODE_DISABLE 0x0 +#define TCR_ENAMODE_ONESHOT 0x1 +#define TCR_ENAMODE_PERIODIC 0x2 +#define TCR_ENAMODE_MASK 0x3 + +#define TGCR_TIMMODE_SHIFT 2 +#define TGCR_TIMMODE_64BIT_GP 0x0 +#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1 +#define TGCR_TIMMODE_64BIT_WDOG 0x2 +#define TGCR_TIMMODE_32BIT_CHAINED 0x3 + +#define TGCR_TIM12RS_SHIFT 0 +#define TGCR_TIM34RS_SHIFT 1 +#define TGCR_RESET 0x0 +#define TGCR_UNRESET 0x1 +#define TGCR_RESET_MASK 0x3 + +#define WDTCR_WDEN_SHIFT 14 +#define WDTCR_WDEN_DISABLE 0x0 +#define WDTCR_WDEN_ENABLE 0x1 +#define WDTCR_WDKEY_SHIFT 16 +#define WDTCR_WDKEY_SEQ0 0xa5c6 +#define WDTCR_WDKEY_SEQ1 0xda7e + +struct timer_s { + char *name; + unsigned int id; + unsigned long period; + unsigned long opts; + unsigned long reg_base; + unsigned long tim_reg; + unsigned long prd_reg; + unsigned long enamode_shift; + struct irqaction irqaction; +}; +static struct timer_s timers[]; + +/* values for 'opts' field of struct timer_s */ +#define TIMER_OPTS_DISABLED 0x00 +#define TIMER_OPTS_ONESHOT 0x01 +#define TIMER_OPTS_PERIODIC 0x02 + +static int timer32_config(struct timer_s *t) +{ + u32 tcr = davinci_readl(t->reg_base + TCR); + + /* disable timer */ + tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); + davinci_writel(tcr, t->reg_base + TCR); + + /* reset counter to zero, set new period */ + davinci_writel(0, t->tim_reg); + davinci_writel(t->period, t->prd_reg); + + /* Set enable mode */ + if (t->opts & TIMER_OPTS_ONESHOT) { + tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift; + } else if (t->opts & TIMER_OPTS_PERIODIC) { + tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; + } + + davinci_writel(tcr, t->reg_base + TCR); + return 0; +} + +static inline u32 timer32_read(struct timer_s *t) +{ + return davinci_readl(t->tim_reg); +} + +static irqreturn_t timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clockevent_davinci; + + evt->event_handler(evt); + return IRQ_HANDLED; +} + +/* called when 32-bit counter wraps */ +static irqreturn_t freerun_interrupt(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + +static struct timer_s timers[] = { + [TID_CLOCKEVENT] = { + .name = "clockevent", + .opts = TIMER_OPTS_DISABLED, + .irqaction = { + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = timer_interrupt, + } + }, + [TID_CLOCKSOURCE] = { + .name = "free-run counter", + .period = ~0, + .opts = TIMER_OPTS_PERIODIC, + .irqaction = { + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = freerun_interrupt, + } + }, +}; + +static void __init timer_init(void) +{ + u32 bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE}; + int i; + + /* Global init of each 64-bit timer as a whole */ + for(i=0; i<2; i++) { + u32 tgcr, base = bases[i]; + + /* Disabled, Internal clock source */ + davinci_writel(0, base + TCR); + + /* reset both timers, no pre-scaler for timer34 */ + tgcr = 0; + davinci_writel(tgcr, base + TGCR); + + /* Set both timers to unchained 32-bit */ + tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; + davinci_writel(tgcr, base + TGCR); + + /* Unreset timers */ + tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | + (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); + davinci_writel(tgcr, base + TGCR); + + /* Init both counters to zero */ + davinci_writel(0, base + TIM12); + davinci_writel(0, base + TIM34); + } + + /* Init of each timer as a 32-bit timer */ + for (i=0; i< ARRAY_SIZE(timers); i++) { + struct timer_s *t = &timers[i]; + + if (t->name) { + t->id = i; + t->reg_base = (IS_TIMER1(t->id) ? + DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE); + + if (IS_TIMER_BOT(t->id)) { + t->enamode_shift = 6; + t->tim_reg = t->reg_base + TIM12; + t->prd_reg = t->reg_base + PRD12; + } else { + t->enamode_shift = 22; + t->tim_reg = t->reg_base + TIM34; + t->prd_reg = t->reg_base + PRD34; + } + + /* Register interrupt */ + t->irqaction.name = t->name; + t->irqaction.dev_id = (void *)t; + if (t->irqaction.handler != NULL) { + setup_irq(timer_irqs[t->id], &t->irqaction); + } + + timer32_config(&timers[i]); + } + } +} + +/* + * clocksource + */ +static cycle_t read_cycles(void) +{ + struct timer_s *t = &timers[TID_CLOCKSOURCE]; + + return (cycles_t)timer32_read(t); +} + +static struct clocksource clocksource_davinci = { + .name = "timer0_1", + .rating = 300, + .read = read_cycles, + .mask = CLOCKSOURCE_MASK(32), + .shift = 24, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +/* + * clockevent + */ +static int davinci_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct timer_s *t = &timers[TID_CLOCKEVENT]; + + t->period = cycles; + timer32_config(t); + return 0; +} + +static void davinci_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + struct timer_s *t = &timers[TID_CLOCKEVENT]; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + t->period = CLOCK_TICK_RATE / (HZ); + t->opts = TIMER_OPTS_PERIODIC; + timer32_config(t); + break; + case CLOCK_EVT_MODE_ONESHOT: + t->opts = TIMER_OPTS_ONESHOT; + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + t->opts = TIMER_OPTS_DISABLED; + break; + } +} + +static struct clock_event_device clockevent_davinci = { + .name = "timer0_0", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_next_event = davinci_set_next_event, + .set_mode = davinci_set_mode, +}; + + +static void __init davinci_timer_init(void) +{ + static char err[] __initdata = KERN_ERR + "%s: can't register clocksource!\n"; + + /* init timer hw */ + timer_init(); + + /* setup clocksource */ + clocksource_davinci.mult = + clocksource_khz2mult(CLOCK_TICK_RATE/1000, + clocksource_davinci.shift); + if (clocksource_register(&clocksource_davinci)) + printk(err, clocksource_davinci.name); + + /* setup clockevent */ + clockevent_davinci.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, + clockevent_davinci.shift); + clockevent_davinci.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &clockevent_davinci); + clockevent_davinci.min_delta_ns = + clockevent_delta2ns(1, &clockevent_davinci); + + clockevent_davinci.cpumask = cpumask_of_cpu(0); + clockevents_register_device(&clockevent_davinci); +} + +struct sys_timer davinci_timer = { + .init = davinci_timer_init, +}; + + +/* reset board using watchdog timer */ +void davinci_watchdog_reset(void) { + u32 tgcr, wdtcr, base = DAVINCI_WDOG_BASE; + + /* disable, internal clock source */ + davinci_writel(0, base + TCR); + + /* reset timer, set mode to 64-bit watchdog, and unreset */ + tgcr = 0; + davinci_writel(tgcr, base + TCR); + tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT; + tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | + (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); + davinci_writel(tgcr, base + TCR); + + /* clear counter and period regs */ + davinci_writel(0, base + TIM12); + davinci_writel(0, base + TIM34); + davinci_writel(0, base + PRD12); + davinci_writel(0, base + PRD34); + + /* enable */ + wdtcr = davinci_readl(base + WDTCR); + wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT; + davinci_writel(wdtcr, base + WDTCR); + + /* put watchdog in pre-active state */ + wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); + davinci_writel(wdtcr, base + WDTCR); + + /* put watchdog in active state */ + wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); + davinci_writel(wdtcr, base + WDTCR); + + /* write an invalid value to the WDKEY field to trigger + * a watchdog reset */ + wdtcr = 0x00004000; + davinci_writel(wdtcr, base + WDTCR); +} diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index b81391a4e374..2900e59395a5 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -171,8 +171,8 @@ config CPU_ARM925T # ARM926T config CPU_ARM926T bool "Support ARM926T processor" - depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX - default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX + depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX || ARCH_DAVINCI + default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX || ARCH_DAVINCI select CPU_32v5 select CPU_ABRT_EV5TJ select CPU_CACHE_VIVT diff --git a/include/asm-arm/arch-davinci/common.h b/include/asm-arm/arch-davinci/common.h new file mode 100644 index 000000000000..a97dfbb15e57 --- /dev/null +++ b/include/asm-arm/arch-davinci/common.h @@ -0,0 +1,19 @@ +/* + * Header for code common to all DaVinci machines. + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H +#define __ARCH_ARM_MACH_DAVINCI_COMMON_H + +struct sys_timer; + +extern struct sys_timer davinci_timer; + +#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ diff --git a/include/asm-arm/arch-davinci/debug-macro.S b/include/asm-arm/arch-davinci/debug-macro.S new file mode 100644 index 000000000000..e6c0f0d5d062 --- /dev/null +++ b/include/asm-arm/arch-davinci/debug-macro.S @@ -0,0 +1,21 @@ +/* + * Debugging macro for DaVinci + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x01000000 @ physical base address + movne \rx, #0xfe000000 @ virtual base + orr \rx, \rx, #0x00c20000 @ UART 0 + .endm + +#define UART_SHIFT 2 +#include diff --git a/include/asm-arm/arch-davinci/dma.h b/include/asm-arm/arch-davinci/dma.h new file mode 100644 index 000000000000..8e2f2d0ba667 --- /dev/null +++ b/include/asm-arm/arch-davinci/dma.h @@ -0,0 +1,16 @@ +/* + * DaVinci DMA definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +#endif /* __ASM_ARCH_DMA_H */ diff --git a/include/asm-arm/arch-davinci/entry-macro.S b/include/asm-arm/arch-davinci/entry-macro.S new file mode 100644 index 000000000000..3ebfcc5cb58e --- /dev/null +++ b/include/asm-arm/arch-davinci/entry-macro.S @@ -0,0 +1,32 @@ +/* + * Low-level IRQ helper macros for TI DaVinci-based platforms + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE) + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \tmp, [\base, #0x14] + mov \tmp, \tmp, lsr #2 + sub \irqnr, \tmp, #1 + cmp \tmp, #0 + .endm + + .macro irq_prio_table + .endm diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h new file mode 100644 index 000000000000..60362d80229e --- /dev/null +++ b/include/asm-arm/arch-davinci/hardware.h @@ -0,0 +1,14 @@ +/* + * Common hardware definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-davinci/io.h b/include/asm-arm/arch-davinci/io.h new file mode 100644 index 000000000000..e7accb910864 --- /dev/null +++ b/include/asm-arm/arch-davinci/io.h @@ -0,0 +1,79 @@ +/* + * DaVinci IO address definitions + * + * Copied from include/asm/arm/arch-omap/io.h + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * ---------------------------------------------------------------------------- + * I/O mapping + * ---------------------------------------------------------------------------- + */ +#define IO_PHYS 0x01c00000 +#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ +#define IO_SIZE 0x00400000 +#define IO_VIRT (IO_PHYS + IO_OFFSET) +#define io_p2v(pa) ((pa) + IO_OFFSET) +#define io_v2p(va) ((va) - IO_OFFSET) +#define IO_ADDRESS(x) io_p2v(x) + +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ +#define PCIO_BASE 0 +#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) + +#ifndef __ASSEMBLER__ + +/* + * Functions to access the DaVinci IO region + * + * NOTE: - Use davinci_read/write[bwl] for physical register addresses + * - Use __raw_read/write[bwl]() for virtual register addresses + * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses + * - DO NOT use hardcoded virtual addresses to allow changing the + * IO address space again if needed + */ +#define davinci_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) +#define davinci_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) +#define davinci_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) + +#define davinci_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) +#define davinci_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) +#define davinci_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) + +/* 16 bit uses LDRH/STRH, base +/- offset_8 */ +typedef struct { volatile u16 offset[256]; } __regbase16; +#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \ + ->offset[((vaddr)&0xff)>>1] +#define __REG16(paddr) __REGV16(io_p2v(paddr)) + +/* 8/32 bit uses LDR/STR, base +/- offset_12 */ +typedef struct { volatile u8 offset[4096]; } __regbase8; +#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \ + ->offset[((vaddr)&4095)>>0] +#define __REG8(paddr) __REGV8(io_p2v(paddr)) + +typedef struct { volatile u32 offset[4096]; } __regbase32; +#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \ + ->offset[((vaddr)&4095)>>2] + +#define __REG(paddr) __REGV32(io_p2v(paddr)) +#else + +#define __REG(x) (*((volatile unsigned long *)io_p2v(x))) + +#endif /* __ASSEMBLER__ */ +#endif /* __ASM_ARCH_IO_H */ diff --git a/include/asm-arm/arch-davinci/irqs.h b/include/asm-arm/arch-davinci/irqs.h new file mode 100644 index 000000000000..f4c5ca6da9f4 --- /dev/null +++ b/include/asm-arm/arch-davinci/irqs.h @@ -0,0 +1,105 @@ +/* + * DaVinci interrupt controller definitions + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* Base address */ +#define DAVINCI_ARM_INTC_BASE 0x01C48000 + +/* Interrupt lines */ +#define IRQ_VDINT0 0 +#define IRQ_VDINT1 1 +#define IRQ_VDINT2 2 +#define IRQ_HISTINT 3 +#define IRQ_H3AINT 4 +#define IRQ_PRVUINT 5 +#define IRQ_RSZINT 6 +#define IRQ_VFOCINT 7 +#define IRQ_VENCINT 8 +#define IRQ_ASQINT 9 +#define IRQ_IMXINT 10 +#define IRQ_VLCDINT 11 +#define IRQ_USBINT 12 +#define IRQ_EMACINT 13 + +#define IRQ_CCINT0 16 +#define IRQ_CCERRINT 17 +#define IRQ_TCERRINT0 18 +#define IRQ_TCERRINT 19 +#define IRQ_PSCIN 20 + +#define IRQ_IDE 22 +#define IRQ_HPIINT 23 +#define IRQ_MBXINT 24 +#define IRQ_MBRINT 25 +#define IRQ_MMCINT 26 +#define IRQ_SDIOINT 27 +#define IRQ_MSINT 28 +#define IRQ_DDRINT 29 +#define IRQ_AEMIFINT 30 +#define IRQ_VLQINT 31 +#define IRQ_TINT0_TINT12 32 +#define IRQ_TINT0_TINT34 33 +#define IRQ_TINT1_TINT12 34 +#define IRQ_TINT1_TINT34 35 +#define IRQ_PWMINT0 36 +#define IRQ_PWMINT1 37 +#define IRQ_PWMINT2 38 +#define IRQ_I2C 39 +#define IRQ_UARTINT0 40 +#define IRQ_UARTINT1 41 +#define IRQ_UARTINT2 42 +#define IRQ_SPINT0 43 +#define IRQ_SPINT1 44 + +#define IRQ_DSP2ARM0 46 +#define IRQ_DSP2ARM1 47 +#define IRQ_GPIO0 48 +#define IRQ_GPIO1 49 +#define IRQ_GPIO2 50 +#define IRQ_GPIO3 51 +#define IRQ_GPIO4 52 +#define IRQ_GPIO5 53 +#define IRQ_GPIO6 54 +#define IRQ_GPIO7 55 +#define IRQ_GPIOBNK0 56 +#define IRQ_GPIOBNK1 57 +#define IRQ_GPIOBNK2 58 +#define IRQ_GPIOBNK3 59 +#define IRQ_GPIOBNK4 60 +#define IRQ_COMMTX 61 +#define IRQ_COMMRX 62 +#define IRQ_EMUINT 63 + +#define DAVINCI_N_AINTC_IRQ 64 +#define DAVINCI_N_GPIO 71 + +#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) + +#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 + +#endif /* __ASM_ARCH_IRQS_H */ diff --git a/include/asm-arm/arch-davinci/memory.h b/include/asm-arm/arch-davinci/memory.h new file mode 100644 index 000000000000..dd1625c23cf4 --- /dev/null +++ b/include/asm-arm/arch-davinci/memory.h @@ -0,0 +1,64 @@ +/* + * DaVinci memory space definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/************************************************************************** + * Included Files + **************************************************************************/ +#include +#include + +/************************************************************************** + * Definitions + **************************************************************************/ +#define DAVINCI_DDR_BASE 0x80000000 +#define DAVINCI_IRAM_BASE 0x00008000 /* ARM Internal RAM */ + +#define PHYS_OFFSET DAVINCI_DDR_BASE + +/* + * Increase size of DMA-consistent memory region + */ +#define CONSISTENT_DMA_SIZE (14<<20) + +#ifndef __ASSEMBLY__ +/* + * Restrict DMA-able region to workaround silicon bug. The bug + * restricts buffers available for DMA to video hardware to be + * below 128M + */ +static inline void +__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes) +{ + unsigned int sz = (128<<20) >> PAGE_SHIFT; + + if (node != 0) + sz = 0; + + size[1] = size[0] - sz; + size[0] = sz; +} + +#define arch_adjust_zones(node, zone_size, holes) \ + if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes) + +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) + +#endif + +/* + * Bus address is physical address + */ +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/include/asm-arm/arch-davinci/psc.h b/include/asm-arm/arch-davinci/psc.h new file mode 100644 index 000000000000..4977aa071e1e --- /dev/null +++ b/include/asm-arm/arch-davinci/psc.h @@ -0,0 +1,76 @@ +/* + * DaVinci Power & Sleep Controller (PSC) defines + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_PSC_H +#define __ASM_ARCH_PSC_H + +/* Power and Sleep Controller (PSC) Domains */ +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 + +#define DAVINCI_LPSC_VPSSMSTR 0 +#define DAVINCI_LPSC_VPSSSLV 1 +#define DAVINCI_LPSC_TPCC 2 +#define DAVINCI_LPSC_TPTC0 3 +#define DAVINCI_LPSC_TPTC1 4 +#define DAVINCI_LPSC_EMAC 5 +#define DAVINCI_LPSC_EMAC_WRAPPER 6 +#define DAVINCI_LPSC_MDIO 7 +#define DAVINCI_LPSC_IEEE1394 8 +#define DAVINCI_LPSC_USB 9 +#define DAVINCI_LPSC_ATA 10 +#define DAVINCI_LPSC_VLYNQ 11 +#define DAVINCI_LPSC_UHPI 12 +#define DAVINCI_LPSC_DDR_EMIF 13 +#define DAVINCI_LPSC_AEMIF 14 +#define DAVINCI_LPSC_MMC_SD 15 +#define DAVINCI_LPSC_MEMSTICK 16 +#define DAVINCI_LPSC_McBSP 17 +#define DAVINCI_LPSC_I2C 18 +#define DAVINCI_LPSC_UART0 19 +#define DAVINCI_LPSC_UART1 20 +#define DAVINCI_LPSC_UART2 21 +#define DAVINCI_LPSC_SPI 22 +#define DAVINCI_LPSC_PWM0 23 +#define DAVINCI_LPSC_PWM1 24 +#define DAVINCI_LPSC_PWM2 25 +#define DAVINCI_LPSC_GPIO 26 +#define DAVINCI_LPSC_TIMER0 27 +#define DAVINCI_LPSC_TIMER1 28 +#define DAVINCI_LPSC_TIMER2 29 +#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 +#define DAVINCI_LPSC_ARM 31 +#define DAVINCI_LPSC_SCR2 32 +#define DAVINCI_LPSC_SCR3 33 +#define DAVINCI_LPSC_SCR4 34 +#define DAVINCI_LPSC_CROSSBAR 35 +#define DAVINCI_LPSC_CFG27 36 +#define DAVINCI_LPSC_CFG3 37 +#define DAVINCI_LPSC_CFG5 38 +#define DAVINCI_LPSC_GEM 39 +#define DAVINCI_LPSC_IMCOP 40 + +#endif /* __ASM_ARCH_PSC_H */ diff --git a/include/asm-arm/arch-davinci/serial.h b/include/asm-arm/arch-davinci/serial.h new file mode 100644 index 000000000000..ed418ef76805 --- /dev/null +++ b/include/asm-arm/arch-davinci/serial.h @@ -0,0 +1,20 @@ +/* + * DaVinci serial device definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_SERIAL_H +#define __ASM_ARCH_SERIAL_H + +#include + +#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) +#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) +#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) + +#endif /* __ASM_ARCH_SERIAL_H */ diff --git a/include/asm-arm/arch-davinci/system.h b/include/asm-arm/arch-davinci/system.h new file mode 100644 index 000000000000..440ac515804b --- /dev/null +++ b/include/asm-arm/arch-davinci/system.h @@ -0,0 +1,29 @@ +/* + * DaVinci system defines + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include +#include + +extern void davinci_watchdog_reset(void); + +static void arch_idle(void) +{ + cpu_do_idle(); +} + +static void arch_reset(char mode) +{ + davinci_watchdog_reset(); +} + +#endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/include/asm-arm/arch-davinci/timex.h b/include/asm-arm/arch-davinci/timex.h new file mode 100644 index 000000000000..52827567841d --- /dev/null +++ b/include/asm-arm/arch-davinci/timex.h @@ -0,0 +1,17 @@ +/* + * DaVinci timer defines + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* The source frequency for the timers is the 27MHz clock */ +#define CLOCK_TICK_RATE 27000000 + +#endif /* __ASM_ARCH_TIMEX_H__ */ diff --git a/include/asm-arm/arch-davinci/uncompress.h b/include/asm-arm/arch-davinci/uncompress.h new file mode 100644 index 000000000000..f6d1570f7206 --- /dev/null +++ b/include/asm-arm/arch-davinci/uncompress.h @@ -0,0 +1,35 @@ +/* + * Serial port stubs for kernel decompress status messages + * + * Author: Anant Gole + * (C) Copyright (C) 2006, Texas Instruments, Inc + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include + +/* PORT_16C550A, in polled non-fifo mode */ + +static void putc(char c) +{ + volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; + + while (!(uart[UART_LSR] & UART_LSR_THRE)) + barrier(); + uart[UART_TX] = c; +} + +static inline void flush(void) +{ + volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; + while (!(uart[UART_LSR] & UART_LSR_THRE)) + barrier(); +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-davinci/vmalloc.h b/include/asm-arm/arch-davinci/vmalloc.h new file mode 100644 index 000000000000..9b47fa89b333 --- /dev/null +++ b/include/asm-arm/arch-davinci/vmalloc.h @@ -0,0 +1,15 @@ +/* + * DaVinci vmalloc definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include + +/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ +#define VMALLOC_END (IO_VIRT - (2<<20)) -- cgit v1.2.3 From 2fd0237538480c8d704c385b6f9abc3f6c46b760 Mon Sep 17 00:00:00 2001 From: Daniel Wolstenholme Date: Thu, 10 May 2007 22:33:02 -0700 Subject: [ARM] iop13xx: msi support Enable devices to signal interrupts via PCI memory cycles. rev6: * fix enable/disable typo, Michael Ellerman rev5: * fix up ack, enable, and disable for iop13xx_msi_chip rev4: * move smp compile fix to separate patch * use dynamic_irq_init in create_irq() * hookup mask/unmask routines in iop13xx_msi_chip rev3: * change msi.c to use linux/smp.h instead of asm/smp.h * call dynamic_irq_cleanup at destroy_irq time rev2: * destroy_irq did not take the full 128 bits of msi_irq_in_use into account * added missing '&' for calls to test_and_set_bit and clear_bit [ebiederm@xmission.com: review comments/suggestions] [dan.j.williams@intel.com: cleanups/forward port to 2.6-git] Signed-off-by: Daniel Wolstenholme Signed-off-by: Dan Williams Acked-by: Eric W. Biederman Signed-off-by: Andrew Morton Signed-off-by: Russell King --- arch/arm/mach-iop13xx/Makefile | 1 + arch/arm/mach-iop13xx/irq.c | 5 +- arch/arm/mach-iop13xx/msi.c | 194 +++++++++++++++++++++++++++++++++ arch/arm/mach-iop13xx/pci.c | 16 +++ include/asm-arm/arch-iop13xx/iop13xx.h | 29 +++++ include/asm-arm/arch-iop13xx/irqs.h | 8 +- include/asm-arm/arch-iop13xx/msi.h | 11 ++ 7 files changed, 262 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-iop13xx/msi.c create mode 100644 include/asm-arm/arch-iop13xx/msi.h (limited to 'include') diff --git a/arch/arm/mach-iop13xx/Makefile b/arch/arm/mach-iop13xx/Makefile index da1609dc0dee..cad015fee12f 100644 --- a/arch/arm/mach-iop13xx/Makefile +++ b/arch/arm/mach-iop13xx/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_ARCH_IOP13XX) += io.o obj-$(CONFIG_ARCH_IOP13XX) += tpmi.o obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o +obj-$(CONFIG_PCI_MSI) += msi.o diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index b2eb0b961031..5791addd436b 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c @@ -26,6 +26,7 @@ #include #include #include +#include /* INTCTL0 CP6 R0 Page 4 */ @@ -258,7 +259,7 @@ void __init iop13xx_init_irq(void) write_intbase(INTBASE); write_intsize(INTSIZE_4); - for(i = 0; i < NR_IOP13XX_IRQS; i++) { + for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { if (i < 32) set_irq_chip(i, &iop13xx_irqchip1); else if (i < 64) @@ -271,4 +272,6 @@ void __init iop13xx_init_irq(void) set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } + + iop13xx_msi_init(); } diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c new file mode 100644 index 000000000000..2d2369302220 --- /dev/null +++ b/arch/arm/mach-iop13xx/msi.c @@ -0,0 +1,194 @@ +/* + * arch/arm/mach-iop13xx/msi.c + * + * PCI MSI support for the iop13xx processor + * + * Copyright (c) 2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place - Suite 330, Boston, MA 02111-1307 USA. + * + */ +#include +#include +#include +#include + + +#define IOP13XX_NUM_MSI_IRQS 128 +static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); + +/* IMIPR0 CP6 R8 Page 1 + */ +static inline u32 read_imipr_0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); + return val; +} +static inline void write_imipr_0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); +} + +/* IMIPR1 CP6 R9 Page 1 + */ +static inline u32 read_imipr_1(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); + return val; +} +static inline void write_imipr_1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); +} + +/* IMIPR2 CP6 R10 Page 1 + */ +static inline u32 read_imipr_2(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); + return val; +} +static inline void write_imipr_2(u32 val) +{ + asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); +} + +/* IMIPR3 CP6 R11 Page 1 + */ +static inline u32 read_imipr_3(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); + return val; +} +static inline void write_imipr_3(u32 val) +{ + asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); +} + +static u32 (*read_imipr[])(void) = { + read_imipr_0, + read_imipr_1, + read_imipr_2, + read_imipr_3, +}; + +static void (*write_imipr[])(u32) = { + write_imipr_0, + write_imipr_1, + write_imipr_2, + write_imipr_3, +}; + +static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) +{ + int i, j; + unsigned long status; + + /* read IMIPR registers and find any active interrupts, + * then call ISR for each active interrupt + */ + for (i = 0; i < ARRAY_SIZE(read_imipr); i++) { + status = (read_imipr[i])(); + if (!status) + continue; + + do { + j = find_first_bit(&status, 32); + (write_imipr[i])(1 << j); /* write back to clear bit */ + desc = irq_desc + IRQ_IOP13XX_MSI_0 + j + (32*i); + desc_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i), desc); + status = (read_imipr[i])(); + } while (status); + } +} + +void __init iop13xx_msi_init(void) +{ + set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); +} + +/* + * Dynamic irq allocate and deallocation + */ +int create_irq(void) +{ + int irq, pos; + +again: + pos = find_first_zero_bit(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); + irq = IRQ_IOP13XX_MSI_0 + pos; + if (irq > NR_IRQS) + return -ENOSPC; + /* test_and_set_bit operates on 32-bits at a time */ + if (test_and_set_bit(pos, msi_irq_in_use)) + goto again; + + dynamic_irq_init(irq); + + return irq; +} + +void destroy_irq(unsigned int irq) +{ + int pos = irq - IRQ_IOP13XX_MSI_0; + + dynamic_irq_cleanup(irq); + + clear_bit(pos, msi_irq_in_use); +} + +void arch_teardown_msi_irq(unsigned int irq) +{ + destroy_irq(irq); +} + +static void iop13xx_msi_nop(unsigned int irq) +{ + return; +} + +static struct irq_chip iop13xx_msi_chip = { + .name = "PCI-MSI", + .ack = iop13xx_msi_nop, + .enable = unmask_msi_irq, + .disable = mask_msi_irq, + .mask = mask_msi_irq, + .unmask = unmask_msi_irq, +}; + +int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) +{ + int id, irq = create_irq(); + struct msi_msg msg; + + if (irq < 0) + return irq; + + set_irq_msi(irq, desc); + + msg.address_hi = 0x0; + msg.address_lo = IOP13XX_MU_MIMR_PCI; + + id = iop13xx_cpu_id(); + msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); + + write_msi_msg(irq, &msg); + set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); + + return irq; +} diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index d1d0d32ca77c..1c9e94c38b7e 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -559,6 +559,14 @@ void __init iop13xx_atue_setup(void) int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE); u32 reg_val; +#ifdef CONFIG_PCI_MSI + /* BAR 0 (inbound msi window) */ + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); + __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0); + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0); + __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0); +#endif + /* BAR 1 (1:1 mapping with Physical RAM) */ /* Set limit and enable */ __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, @@ -720,6 +728,14 @@ void __init iop13xx_atux_setup(void) else atux_trhfa_timeout = jiffies; +#ifdef CONFIG_PCI_MSI + /* BAR 0 (inbound msi window) */ + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); + __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0); + __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0); + __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0); +#endif + /* BAR 1 (1:1 mapping with Physical RAM) */ /* Set limit and enable */ __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index 85707e9c3325..e6736c3d1f7f 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -181,6 +181,7 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200 #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400 #define IOP13XX_PBI_PMMR_OFFSET 0x00001580 +#define IOP13XX_MU_PMMR_OFFSET 0x00004000 #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188 #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) @@ -412,6 +413,34 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7) /*=======================================================================*/ +/*============================MESSAGING UNIT=============================*/ +#define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\ + (ofs)) + +#define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10) +#define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14) +#define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18) +#define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C) +#define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20) +#define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24) +#define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28) +#define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C) +#define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30) +#define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34) +#define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38) +#define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C) +#define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48) +#define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50) +#define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54) +#define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84) + +#define IOP13XX_MU_WINDOW_SIZE (8 * 1024) +#define IOP13XX_MU_BASE_PHYS (0xff000000) +#define IOP13XX_MU_BASE_PCI (0xff000000) +#define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48) +#define IOP13XX_MU_MIMR_CORE_SELECT (15) +/*=======================================================================*/ + /*==============================ADMA UNITS===============================*/ #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h index 5c6fac2a4004..054e7acb5bfa 100644 --- a/include/asm-arm/arch-iop13xx/irqs.h +++ b/include/asm-arm/arch-iop13xx/irqs.h @@ -168,7 +168,7 @@ static inline u32 read_intpnd_3(void) #define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ #define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ #define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ -#define IRQ_IOP13XX_RSVD_113 (113) /* 17 */ +#define IRQ_IOP13XX_INBD_MSI (113) /* 17 */ #define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ #define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ #define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ @@ -184,7 +184,13 @@ static inline u32 read_intpnd_3(void) #define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ #define IRQ_IOP13XX_HPI (127) /* 31 */ +#ifdef CONFIG_PCI_MSI +#define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1) +#define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128) +#else #define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) +#endif + #define NR_IRQS NR_IOP13XX_IRQS #endif /* _IOP13XX_IRQ_H_ */ diff --git a/include/asm-arm/arch-iop13xx/msi.h b/include/asm-arm/arch-iop13xx/msi.h new file mode 100644 index 000000000000..b80c5ae17e99 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/msi.h @@ -0,0 +1,11 @@ +#ifndef _IOP13XX_MSI_H_ +#define _IOP13XX_MSI_H_ +#ifdef CONFIG_PCI_MSI +void iop13xx_msi_init(void); +#else +static inline void iop13xx_msi_init(void) +{ + return; +} +#endif +#endif -- cgit v1.2.3 From 877d7720f5f67793b9b6027840d2c88ea25dc4c8 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Fri, 11 May 2007 20:49:56 +0100 Subject: [ARM] 4370/3: AT91: Support for Atmel AT91SAM9RL processors. Add support for Atmel's new AT91SAM9RL range of processors. Includes similar peripherals as other AT91SAM9 processors, but with a High-speed USB controller and various sizes of internal SRAM. Signed-off-by: Nicolas Ferre Signed-off-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91/Kconfig | 3 + arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/at91sam9rl.c | 341 ++++++++++++++ arch/arm/mach-at91/at91sam9rl_devices.c | 634 ++++++++++++++++++++++++++ arch/arm/mach-at91/generic.h | 2 + arch/arm/mm/Kconfig | 4 +- drivers/usb/gadget/Kconfig | 2 +- include/asm-arm/arch-at91/at91sam9rl.h | 110 +++++ include/asm-arm/arch-at91/at91sam9rl_matrix.h | 96 ++++ include/asm-arm/arch-at91/cpu.h | 9 + include/asm-arm/arch-at91/hardware.h | 2 + include/asm-arm/arch-at91/timex.h | 5 + include/asm-avr32/arch-at32ap/cpu.h | 1 + 13 files changed, 1207 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-at91/at91sam9rl.c create mode 100644 arch/arm/mach-at91/at91sam9rl_devices.c create mode 100644 include/asm-arm/arch-at91/at91sam9rl.h create mode 100644 include/asm-arm/arch-at91/at91sam9rl_matrix.h (limited to 'include') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 018d637f87fc..1ba120c5cd0c 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -17,6 +17,9 @@ config ARCH_AT91SAM9261 config ARCH_AT91SAM9263 bool "AT91SAM9263" +config ARCH_AT91SAM9RL + bool "AT91SAM9RL" + endchoice # ---------------------------------------------------------- diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index a412ae18a421..66d79e6c68a3 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devic obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o +obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o # AT91RM9200 board-specific support obj-$(CONFIG_MACH_ONEARM) += board-1arm.o diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c new file mode 100644 index 000000000000..4813a35f6cf5 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -0,0 +1,341 @@ +/* + * arch/arm/mach-at91/at91sam9rl.c + * + * Copyright (C) 2005 SAN People + * Copyright (C) 2007 Atmel Corporation + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include "generic.h" +#include "clock.h" + +static struct map_desc at91sam9rl_io_desc[] __initdata = { + { + .virtual = AT91_VA_BASE_SYS, + .pfn = __phys_to_pfn(AT91_BASE_SYS), + .length = SZ_16K, + .type = MT_DEVICE, + }, +}; + +static struct map_desc at91sam9rl_sram_desc[] __initdata = { + { + .pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE), + .type = MT_DEVICE, + } +}; + +/* -------------------------------------------------------------------- + * Clocks + * -------------------------------------------------------------------- */ + +/* + * The peripheral clocks. + */ +static struct clk pioA_clk = { + .name = "pioA_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_PIOA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioB_clk = { + .name = "pioB_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_PIOB, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioC_clk = { + .name = "pioC_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_PIOC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioD_clk = { + .name = "pioD_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_PIOD, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart0_clk = { + .name = "usart0_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_US0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart1_clk = { + .name = "usart1_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_US1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart2_clk = { + .name = "usart2_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_US2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart3_clk = { + .name = "usart3_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_US3, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc_clk = { + .name = "mci_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_MCI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk twi0_clk = { + .name = "twi0_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_TWI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk twi1_clk = { + .name = "twi1_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_TWI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi_clk = { + .name = "spi_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_SPI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc0_clk = { + .name = "ssc0_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_SSC0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc1_clk = { + .name = "ssc1_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_SSC1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tc0_clk = { + .name = "tc0_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_TC0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tc1_clk = { + .name = "tc1_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_TC1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tc2_clk = { + .name = "tc2_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_TC2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pwmc_clk = { + .name = "pwmc_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_PWMC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tsc_clk = { + .name = "tsc_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_TSC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk dma_clk = { + .name = "dma_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_DMA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk udphs_clk = { + .name = "udphs_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk lcdc_clk = { + .name = "lcdc_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_LCDC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ac97_clk = { + .name = "ac97_clk", + .pmc_mask = 1 << AT91SAM9RL_ID_AC97C, + .type = CLK_TYPE_PERIPHERAL, +}; + +static struct clk *periph_clocks[] __initdata = { + &pioA_clk, + &pioB_clk, + &pioC_clk, + &pioD_clk, + &usart0_clk, + &usart1_clk, + &usart2_clk, + &usart3_clk, + &mmc_clk, + &twi0_clk, + &twi1_clk, + &spi_clk, + &ssc0_clk, + &ssc1_clk, + &tc0_clk, + &tc1_clk, + &tc2_clk, + &pwmc_clk, + &tsc_clk, + &dma_clk, + &udphs_clk, + &lcdc_clk, + &ac97_clk, + // irq0 +}; + +/* + * The two programmable clocks. + * You must configure pin multiplexing to bring these signals out. + */ +static struct clk pck0 = { + .name = "pck0", + .pmc_mask = AT91_PMC_PCK0, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 0, +}; +static struct clk pck1 = { + .name = "pck1", + .pmc_mask = AT91_PMC_PCK1, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 1, +}; + +static void __init at91sam9rl_register_clocks(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) + clk_register(periph_clocks[i]); + + clk_register(&pck0); + clk_register(&pck1); +} + +/* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ + +static struct at91_gpio_bank at91sam9rl_gpio[] = { + { + .id = AT91SAM9RL_ID_PIOA, + .offset = AT91_PIOA, + .clock = &pioA_clk, + }, { + .id = AT91SAM9RL_ID_PIOB, + .offset = AT91_PIOB, + .clock = &pioB_clk, + }, { + .id = AT91SAM9RL_ID_PIOC, + .offset = AT91_PIOC, + .clock = &pioC_clk, + }, { + .id = AT91SAM9RL_ID_PIOD, + .offset = AT91_PIOD, + .clock = &pioD_clk, + } +}; + +static void at91sam9rl_reset(void) +{ + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); +} + + +/* -------------------------------------------------------------------- + * AT91SAM9RL processor initialization + * -------------------------------------------------------------------- */ + +void __init at91sam9rl_initialize(unsigned long main_clock) +{ + unsigned long cidr, sram_size; + + /* Map peripherals */ + iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc)); + + cidr = at91_sys_read(AT91_DBGU_CIDR); + + switch (cidr & AT91_CIDR_SRAMSIZ) { + case AT91_CIDR_SRAMSIZ_32K: + sram_size = 2 * SZ_16K; + break; + case AT91_CIDR_SRAMSIZ_16K: + default: + sram_size = SZ_16K; + } + + at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size; + at91sam9rl_sram_desc->length = sram_size; + + /* Map SRAM */ + iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc)); + + at91_arch_reset = at91sam9rl_reset; + at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); + + /* Init clock subsystem */ + at91_clock_init(main_clock); + + /* Register the processor-specific clocks */ + at91sam9rl_register_clocks(); + + /* Register GPIO subsystem */ + at91_gpio_init(at91sam9rl_gpio, 4); +} + +/* -------------------------------------------------------------------- + * Interrupt initialization + * -------------------------------------------------------------------- */ + +/* + * The default interrupt priority levels (0 = lowest, 7 = highest). + */ +static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { + 7, /* Advanced Interrupt Controller */ + 7, /* System Peripherals */ + 1, /* Parallel IO Controller A */ + 1, /* Parallel IO Controller B */ + 1, /* Parallel IO Controller C */ + 1, /* Parallel IO Controller D */ + 5, /* USART 0 */ + 5, /* USART 1 */ + 5, /* USART 2 */ + 5, /* USART 3 */ + 0, /* Multimedia Card Interface */ + 6, /* Two-Wire Interface 0 */ + 6, /* Two-Wire Interface 1 */ + 5, /* Serial Peripheral Interface */ + 4, /* Serial Synchronous Controller 0 */ + 4, /* Serial Synchronous Controller 1 */ + 0, /* Timer Counter 0 */ + 0, /* Timer Counter 1 */ + 0, /* Timer Counter 2 */ + 0, + 0, /* Touch Screen Controller */ + 0, /* DMA Controller */ + 2, /* USB Device High speed port */ + 2, /* LCD Controller */ + 6, /* AC97 Controller */ + 0, + 0, + 0, + 0, + 0, + 0, + 0, /* Advanced Interrupt Controller */ +}; + +void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS]) +{ + if (!priority) + priority = at91sam9rl_default_irq_priority; + + /* Initialize the AIC interrupt controller */ + at91_aic_init(priority); + + /* Enable GPIO interrupts */ + at91_gpio_irq_setup(); +} diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c new file mode 100644 index 000000000000..e775aa65bb63 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9rl_devices.c @@ -0,0 +1,634 @@ +/* + * Copyright (C) 2007 Atmel Corporation + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include +#include + +#include +#include + +#include