diff options
| author | Yuuki NAGAO <wf.yn386@gmail.com> | 2025-09-15 09:39:28 +0900 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2025-09-18 17:02:39 +1000 |
| commit | 03e3a06de641cca6299b1a7bb8f9379014e61b8e (patch) | |
| tree | 5bf7f08f93cda3a36e52e2b1c16815448c4d8453 | |
| parent | 06a90e0b4b38543741c5749b5710f2796c61f0d8 (diff) | |
stm32/boards/NUCLEO_G474RE: Change flash latency for NUCLEO-G474RE.
For NUCLEO-G474RE, FLASH_LATENCY_4 can be specified instead of
FLASH_LATENCY_8 because it runs at 170MHz.
Signed-off-by: Yuuki NAGAO <wf.yn386@gmail.com>
| -rw-r--r-- | ports/stm32/boards/NUCLEO_G474RE/mpconfigboard.h | 2 | ||||
| -rw-r--r-- | ports/stm32/system_stm32.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/ports/stm32/boards/NUCLEO_G474RE/mpconfigboard.h b/ports/stm32/boards/NUCLEO_G474RE/mpconfigboard.h index 62d104a54..e807a5478 100644 --- a/ports/stm32/boards/NUCLEO_G474RE/mpconfigboard.h +++ b/ports/stm32/boards/NUCLEO_G474RE/mpconfigboard.h @@ -29,7 +29,7 @@ #define MICROPY_HW_CLK_USE_HSI48 (1) // for RNG // 4 wait states -#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_8 +#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_4 // UART config #define MICROPY_HW_LPUART1_TX (pin_A2) // A2 (to STLINK), B11, C1 diff --git a/ports/stm32/system_stm32.c b/ports/stm32/system_stm32.c index b76a41e97..5a9fef1c2 100644 --- a/ports/stm32/system_stm32.c +++ b/ports/stm32/system_stm32.c @@ -494,7 +494,7 @@ MP_WEAK void SystemClock_Config(void) { #endif #if defined(STM32G4) - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, MICROPY_HW_FLASH_LATENCY) != HAL_OK) { MICROPY_BOARD_FATAL_ERROR("HAL_RCC_ClockConfig"); } PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPUART1 |