diff options
| author | patrick <patrick@thinktransit.com.au> | 2023-05-17 01:06:04 +1000 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2023-05-19 22:37:25 +1000 |
| commit | 05e143dbddbde07e4f31a0376b8869bcf9fb1939 (patch) | |
| tree | 9234225ace0e647640bb29b963640b87ad0aaa65 | |
| parent | 3a7ad642672a61d3adb1510bf26913376ff837c8 (diff) | |
esp32/esp32_ulp: Enable FSM ULP for S2 and S3 chips.
This commit enables the ULP for the S2 and S3 chips.
Note this is the FSM (Finite State Machine) ULP.
Signed-off-by: Patrick Joy <patrick@joytech.com.au>
| -rw-r--r-- | docs/library/esp32.rst | 8 | ||||
| -rw-r--r-- | ports/esp32/esp32_ulp.c | 9 | ||||
| -rw-r--r-- | ports/esp32/modesp32.c | 2 |
3 files changed, 17 insertions, 2 deletions
diff --git a/docs/library/esp32.rst b/docs/library/esp32.rst index 12d089021..d9241d545 100644 --- a/docs/library/esp32.rst +++ b/docs/library/esp32.rst @@ -279,6 +279,14 @@ For more details see Espressif's `ESP-IDF RMT documentation. Ultra-Low-Power co-processor ---------------------------- +This class gives access to the Ultra Low Power (ULP) co-processor on the ESP32, +ESP32-S2 and ESP32-S3 chips. + +.. warning:: + + This class does not provide access to the RISCV ULP co-processor available + on the ESP32-S2 and ESP32-S3 chips. + .. class:: ULP() This class provides access to the Ultra-Low-Power co-processor. diff --git a/ports/esp32/esp32_ulp.c b/ports/esp32/esp32_ulp.c index 843bdb236..e7962ce1a 100644 --- a/ports/esp32/esp32_ulp.c +++ b/ports/esp32/esp32_ulp.c @@ -26,7 +26,8 @@ #include "py/runtime.h" -#if CONFIG_IDF_TARGET_ESP32 + +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #include "esp32/ulp.h" #include "esp_err.h" @@ -87,7 +88,13 @@ STATIC const mp_rom_map_elem_t esp32_ulp_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_set_wakeup_period), MP_ROM_PTR(&esp32_ulp_set_wakeup_period_obj) }, { MP_ROM_QSTR(MP_QSTR_load_binary), MP_ROM_PTR(&esp32_ulp_load_binary_obj) }, { MP_ROM_QSTR(MP_QSTR_run), MP_ROM_PTR(&esp32_ulp_run_obj) }, + #if CONFIG_IDF_TARGET_ESP32 { MP_ROM_QSTR(MP_QSTR_RESERVE_MEM), MP_ROM_INT(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM) }, + #elif CONFIG_IDF_TARGET_ESP32S2 + { MP_ROM_QSTR(MP_QSTR_RESERVE_MEM), MP_ROM_INT(CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM) }, + #elif CONFIG_IDF_TARGET_ESP32S3 + { MP_ROM_QSTR(MP_QSTR_RESERVE_MEM), MP_ROM_INT(CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM) }, + #endif }; STATIC MP_DEFINE_CONST_DICT(esp32_ulp_locals_dict, esp32_ulp_locals_dict_table); diff --git a/ports/esp32/modesp32.c b/ports/esp32/modesp32.c index 017db36e2..7a436bf77 100644 --- a/ports/esp32/modesp32.c +++ b/ports/esp32/modesp32.c @@ -217,7 +217,7 @@ STATIC const mp_rom_map_elem_t esp32_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_NVS), MP_ROM_PTR(&esp32_nvs_type) }, { MP_ROM_QSTR(MP_QSTR_Partition), MP_ROM_PTR(&esp32_partition_type) }, { MP_ROM_QSTR(MP_QSTR_RMT), MP_ROM_PTR(&esp32_rmt_type) }, - #if CONFIG_IDF_TARGET_ESP32 + #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 { MP_ROM_QSTR(MP_QSTR_ULP), MP_ROM_PTR(&esp32_ulp_type) }, #endif |