diff options
author | Krzysztof Blazewicz <krzysztof.blazewicz@uxeon.com> | 2016-09-07 13:00:17 +0200 |
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committer | Krzysztof Blazewicz <krzysztof.blazewicz@uxeon.com> | 2016-11-16 12:43:27 +0100 |
commit | 0280b2c1b1eb761fa66db620c96cdcf276c2cf94 (patch) | |
tree | 4aa3edf9616f52f23bb73abd9643634135581fcd | |
parent | fa833f96df05ea25bba44396754d1d8f24aece92 (diff) |
stmhal/i2c: handle I2C IRQs
This is required by HAL Driver for error handling since v1.5.0
-rw-r--r-- | stmhal/i2c.c | 24 | ||||
-rw-r--r-- | stmhal/stm32_it.c | 44 |
2 files changed, 68 insertions, 0 deletions
diff --git a/stmhal/i2c.c b/stmhal/i2c.c index 9b7ec4dab..53c9667b6 100644 --- a/stmhal/i2c.c +++ b/stmhal/i2c.c @@ -253,6 +253,24 @@ void i2c_init(I2C_HandleTypeDef *i2c) { const pyb_i2c_obj_t *self = &pyb_i2c_obj[i2c_unit - 1]; dma_invalidate_channel(self->tx_dma_descr); dma_invalidate_channel(self->rx_dma_descr); + + if (0) { + #if defined(MICROPY_HW_I2C1_SCL) + } else if (i2c->Instance == I2C1) { + HAL_NVIC_EnableIRQ(I2C1_EV_IRQn); + HAL_NVIC_EnableIRQ(I2C1_ER_IRQn); + #endif + #if defined(MICROPY_HW_I2C2_SCL) + } else if (i2c->Instance == I2C2) { + HAL_NVIC_EnableIRQ(I2C2_EV_IRQn); + HAL_NVIC_EnableIRQ(I2C2_ER_IRQn); + #endif + #if defined(MICROPY_HW_I2C3_SCL) + } else if (i2c->Instance == I2C3) { + HAL_NVIC_EnableIRQ(I2C3_EV_IRQn); + HAL_NVIC_EnableIRQ(I2C3_ER_IRQn); + #endif + } } void i2c_deinit(I2C_HandleTypeDef *i2c) { @@ -263,18 +281,24 @@ void i2c_deinit(I2C_HandleTypeDef *i2c) { __I2C1_FORCE_RESET(); __I2C1_RELEASE_RESET(); __I2C1_CLK_DISABLE(); + HAL_NVIC_DisableIRQ(I2C1_EV_IRQn); + HAL_NVIC_DisableIRQ(I2C1_ER_IRQn); #endif #if defined(MICROPY_HW_I2C2_SCL) } else if (i2c->Instance == I2C2) { __I2C2_FORCE_RESET(); __I2C2_RELEASE_RESET(); __I2C2_CLK_DISABLE(); + HAL_NVIC_DisableIRQ(I2C2_EV_IRQn); + HAL_NVIC_DisableIRQ(I2C2_ER_IRQn); #endif #if defined(MICROPY_HW_I2C3_SCL) } else if (i2c->Instance == I2C3) { __I2C3_FORCE_RESET(); __I2C3_RELEASE_RESET(); __I2C3_CLK_DISABLE(); + HAL_NVIC_DisableIRQ(I2C3_EV_IRQn); + HAL_NVIC_DisableIRQ(I2C3_ER_IRQn); #endif } } diff --git a/stmhal/stm32_it.c b/stmhal/stm32_it.c index d2f8c271c..f59655915 100644 --- a/stmhal/stm32_it.c +++ b/stmhal/stm32_it.c @@ -79,10 +79,12 @@ #include "storage.h" #include "can.h" #include "dma.h" +#include "i2c.h" extern void __fatal_error(const char*); extern PCD_HandleTypeDef pcd_fs_handle; extern PCD_HandleTypeDef pcd_hs_handle; + /******************************************************************************/ /* Cortex-M4 Processor Exceptions Handlers */ /******************************************************************************/ @@ -700,3 +702,45 @@ void CAN2_RX1_IRQHandler(void) { IRQ_EXIT(CAN2_RX1_IRQn); } #endif // MICROPY_HW_ENABLE_CAN + +#if defined(MICROPY_HW_I2C1_SCL) +void I2C1_EV_IRQHandler(void) { + IRQ_ENTER(I2C1_EV_IRQn); + HAL_I2C_EV_IRQHandler(&I2CHandle1); + IRQ_EXIT(I2C1_EV_IRQn); +} + +void I2C1_ER_IRQHandler(void) { + IRQ_ENTER(I2C1_ER_IRQn); + HAL_I2C_ER_IRQHandler(&I2CHandle1); + IRQ_EXIT(I2C1_ER_IRQn); +} +#endif // defined(MICROPY_HW_I2C1_SCL) + +#if defined(MICROPY_HW_I2C2_SCL) +void I2C2_EV_IRQHandler(void) { + IRQ_ENTER(I2C2_EV_IRQn); + HAL_I2C_EV_IRQHandler(&I2CHandle2); + IRQ_EXIT(I2C2_EV_IRQn); +} + +void I2C2_ER_IRQHandler(void) { + IRQ_ENTER(I2C2_ER_IRQn); + HAL_I2C_ER_IRQHandler(&I2CHandle2); + IRQ_EXIT(I2C2_ER_IRQn); +} +#endif // defined(MICROPY_HW_I2C2_SCL) + +#if defined(MICROPY_HW_I2C3_SCL) +void I2C3_EV_IRQHandler(void) { + IRQ_ENTER(I2C3_EV_IRQn); + HAL_I2C_EV_IRQHandler(&I2CHandle3); + IRQ_EXIT(I2C3_EV_IRQn); +} + +void I2C3_ER_IRQHandler(void) { + IRQ_ENTER(I2C3_ER_IRQn); + HAL_I2C_ER_IRQHandler(&I2CHandle3); + IRQ_EXIT(I2C3_ER_IRQn); +} +#endif // defined(MICROPY_HW_I2C3_SCL) |