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authorJared Hancock <jared.hancock@centeredsolutions.com>2024-03-20 09:04:49 -0500
committerDamien George <damien@micropython.org>2024-03-25 13:25:19 +1100
commit086d4d127d2b85d8e04c73f7f54fc90c0a2e5c57 (patch)
treea152c2b72f9db1991454bad4d144ed768f8c9d64
parentfcaf10991727bdf125b2b4f21e4557dd4f74d255 (diff)
extmod/network_wiznet5k: Properly enable interrupt signal on w5100s.
According to the datasheet, the IEN bit to enable the interrupt is in the MR2 register, not the MR register. This is just cleanup as the interrupt appears to be enabled by default after resetting the chip. Tested on W5100S_EVB_PICO.
-rw-r--r--extmod/network_wiznet5k.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/extmod/network_wiznet5k.c b/extmod/network_wiznet5k.c
index b550f8c1f..b8ca075b3 100644
--- a/extmod/network_wiznet5k.c
+++ b/extmod/network_wiznet5k.c
@@ -221,7 +221,7 @@ static void wiznet5k_init(void) {
setSn_IMR(0, Sn_IR_RECV);
#if _WIZCHIP_ == W5100S
// Enable interrupt pin
- setMR(MR2_G_IEN);
+ setMR2(getMR2() | MR2_G_IEN);
#endif
mp_hal_pin_input(wiznet5k_obj.pin_intn);