stm32/system_stm32f0: Add support for using HSE and PLL as SYSCLK.

To configure the SYSCLK on an F0 enable one of:

    MICROPY_HW_CLK_USE_HSI48
    MICROPY_HW_CLK_USE_HSE
    MICROPY_HW_CLK_USE_BYPASS

2 files changed, 29 insertions, 3 deletions

diff --git a/ports/stm32/boards/NUCLEO_F091RC/mpconfigboard.h b/ports/stm32/boards/NUCLEO_F091RC/mpconfigboard.h
index 5e67916cb..e1802da2d 100644
--- a/ports/stm32/boards/NUCLEO_F091RC/mpconfigboard.h
+++ b/ports/stm32/boards/NUCLEO_F091RC/mpconfigboard.h
@@ -17,6 +17,7 @@
 #define MICROPY_HW_HAS_SWITCH       (1)
 
 // For system clock, board uses internal 48MHz, HSI48
+#define MICROPY_HW_CLK_USE_HSI48    (1)
 
 // The board has an external 32kHz crystal
 #define MICROPY_HW_RTC_USE_LSE      (1)
diff --git a/ports/stm32/system_stm32f0.c b/ports/stm32/system_stm32f0.c
index afabdb667..c3c675c74 100644
--- a/ports/stm32/system_stm32f0.c
+++ b/ports/stm32/system_stm32f0.c
@@ -40,7 +40,7 @@
   ******************************************************************************
   */
 
-#include STM32_HAL_H
+#include "py/mphal.h"
 
 #ifndef HSE_VALUE
 #define HSE_VALUE (8000000)
@@ -135,12 +135,37 @@ void SystemClock_Config(void) {
     // Set flash latency to 1 because SYSCLK > 24MHz
     FLASH->ACR = (FLASH->ACR & ~0x7) | 0x1;
 
+    #if MICROPY_HW_CLK_USE_HSI48
     // Use the 48MHz internal oscillator
+
     RCC->CR2 |= RCC_CR2_HSI48ON;
     while ((RCC->CR2 & RCC_CR2_HSI48RDY) == 0) {
     }
-    RCC->CFGR |= 3 << RCC_CFGR_SW_Pos;
-    while (((RCC->CFGR >> RCC_CFGR_SWS_Pos) & 0x3) != 0x03) {
+    const uint32_t sysclk_src = 3;
+
+    #else
+    // Use HSE and the PLL to get a 48MHz SYSCLK
+
+    #if MICROPY_HW_CLK_USE_BYPASS
+    RCC->CR |= RCC_CR_HSEBYP;
+    #endif
+    RCC->CR |= RCC_CR_HSEON;
+    while ((RCC->CR & RCC_CR_HSERDY) == 0) {
+        // Wait for HSE to be ready
+    }
+    RCC->CFGR = ((48000000 / HSE_VALUE) - 2) << RCC_CFGR_PLLMUL_Pos | 2 << RCC_CFGR_PLLSRC_Pos;
+    RCC->CFGR2 = 0; // Input clock not divided
+    RCC->CR |= RCC_CR_PLLON; // Turn PLL on
+    while ((RCC->CR & RCC_CR_PLLRDY) == 0) {
+        // Wait for PLL to lock
+    }
+    const uint32_t sysclk_src = 2;
+
+    #endif
+
+    // Select SYSCLK source
+    RCC->CFGR |= sysclk_src << RCC_CFGR_SW_Pos;
+    while (((RCC->CFGR >> RCC_CFGR_SWS_Pos) & 0x3) != sysclk_src) {
         // Wait for SYSCLK source to change
     }