summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDamien George <damien@micropython.org>2025-06-30 11:27:50 +1000
committerDamien George <damien@micropython.org>2025-07-08 13:18:13 +1000
commit29b5c2207cd3f267018c566ee20f2d95f3b38f5e (patch)
tree512c9fcbbba71a45e5fb3c12fbe80269f44282ed
parenta4a098ff8210a086d947b53771ed747a8998cef0 (diff)
tests/extmod_hardware/machine_uart_irq_rxidle.py: Test multiple writes.
This tests that the RXIDLE callback is called correctly after a second lot of bytes are received. Signed-off-by: Damien George <damien@micropython.org>
-rw-r--r--tests/extmod_hardware/machine_uart_irq_rxidle.py20
-rw-r--r--tests/extmod_hardware/machine_uart_irq_rxidle.py.exp24
2 files changed, 33 insertions, 11 deletions
diff --git a/tests/extmod_hardware/machine_uart_irq_rxidle.py b/tests/extmod_hardware/machine_uart_irq_rxidle.py
index ced24dca6..3c743c9e0 100644
--- a/tests/extmod_hardware/machine_uart_irq_rxidle.py
+++ b/tests/extmod_hardware/machine_uart_irq_rxidle.py
@@ -64,10 +64,13 @@ def irq(u):
print("IRQ_RXIDLE:", bool(u.irq().flags() & u.IRQ_RXIDLE), "data:", u.read())
-text = "12345678"
+text = ("12345678", "abcdefgh")
# Test that the IRQ is called for each set of byte received.
for bits_per_s in (2400, 9600, 115200):
+ print("========")
+ print("bits_per_s:", bits_per_s)
+
if tx_pin is None:
uart = UART(uart_id, bits_per_s)
else:
@@ -81,10 +84,11 @@ for bits_per_s in (2400, 9600, 115200):
# Configure desired IRQ.
uart.irq(irq, uart.IRQ_RXIDLE)
- # Write data and wait for IRQ.
- print("write", bits_per_s)
- uart.write(text)
- uart.flush()
- print("ready")
- time.sleep_ms(100)
- print("done")
+ for i in range(2):
+ # Write data and wait for IRQ.
+ print("write")
+ uart.write(text[i])
+ uart.flush()
+ print("ready")
+ time.sleep_ms(100)
+ print("done")
diff --git a/tests/extmod_hardware/machine_uart_irq_rxidle.py.exp b/tests/extmod_hardware/machine_uart_irq_rxidle.py.exp
index ce1890a06..f3c7497e4 100644
--- a/tests/extmod_hardware/machine_uart_irq_rxidle.py.exp
+++ b/tests/extmod_hardware/machine_uart_irq_rxidle.py.exp
@@ -1,12 +1,30 @@
-write 2400
+========
+bits_per_s: 2400
+write
ready
IRQ_RXIDLE: True data: b'12345678'
done
-write 9600
+write
+ready
+IRQ_RXIDLE: True data: b'abcdefgh'
+done
+========
+bits_per_s: 9600
+write
ready
IRQ_RXIDLE: True data: b'12345678'
done
-write 115200
+write
+ready
+IRQ_RXIDLE: True data: b'abcdefgh'
+done
+========
+bits_per_s: 115200
+write
ready
IRQ_RXIDLE: True data: b'12345678'
done
+write
+ready
+IRQ_RXIDLE: True data: b'abcdefgh'
+done