diff options
| author | robert-hh <robert@hammelrath.com> | 2025-01-26 21:39:58 +0100 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2025-02-10 11:31:28 +1100 |
| commit | 2a80d5c68b5e03570784d18985d5388995ba0e40 (patch) | |
| tree | 96c9f54abe0c92a8e8aa28fb72ae2fa642f1a29d | |
| parent | b251aec0fcfef75b43b69c329b9a34c3703a6b90 (diff) | |
mimxrt/flash: Swap the order of disabling IRQ and disabling the cache.
This change stopped problems with USB IRQ happening during flash writes.
Signed-off-by: robert-hh <robert@hammelrath.com>
| -rw-r--r-- | ports/mimxrt/flash.c | 21 |
1 files changed, 8 insertions, 13 deletions
diff --git a/ports/mimxrt/flash.c b/ports/mimxrt/flash.c index 7df799884..cdcdc7483 100644 --- a/ports/mimxrt/flash.c +++ b/ports/mimxrt/flash.c @@ -43,14 +43,13 @@ void flash_init(void) { __attribute__((section(".ram_functions"))) status_t flash_erase_block(uint32_t erase_addr) { status_t status = kStatus_Fail; - SCB_CleanInvalidateDCache(); - SCB_DisableDCache(); __disable_irq(); + SCB_DisableDCache(); status = flexspi_nor_flash_erase_block(BOARD_FLEX_SPI, erase_addr); - __enable_irq(); SCB_EnableDCache(); + __enable_irq(); return status; } @@ -60,14 +59,13 @@ __attribute__((section(".ram_functions"))) status_t flash_erase_block(uint32_t e __attribute__((section(".ram_functions"))) status_t flash_erase_sector(uint32_t erase_addr) { status_t status = kStatus_Fail; - SCB_CleanInvalidateDCache(); - SCB_DisableDCache(); __disable_irq(); + SCB_DisableDCache(); status = flexspi_nor_flash_erase_sector(BOARD_FLEX_SPI, erase_addr); - __enable_irq(); SCB_EnableDCache(); + __enable_irq(); return status; } @@ -83,10 +81,6 @@ __attribute__((section(".ram_functions"))) status_t flash_write_block(uint32_t d if (length == 0) { status = kStatus_Success; // Nothing to do } else { - - SCB_CleanInvalidateDCache(); - SCB_DisableDCache(); - // write data in chunks not crossing a page boundary do { next_addr = dest_addr - (dest_addr % PAGE_SIZE_BYTES) + PAGE_SIZE_BYTES; // next page boundary @@ -96,7 +90,11 @@ __attribute__((section(".ram_functions"))) status_t flash_write_block(uint32_t d } __disable_irq(); + SCB_DisableDCache(); + status = flexspi_nor_flash_page_program(BOARD_FLEX_SPI, dest_addr, (uint32_t *)src, write_length); + + SCB_EnableDCache(); __enable_irq(); // Update remaining data length @@ -106,9 +104,6 @@ __attribute__((section(".ram_functions"))) status_t flash_write_block(uint32_t d src += write_length; dest_addr += write_length; } while ((length > 0) && (status == kStatus_Success)); - - SCB_EnableDCache(); - } return status; } |