diff options
| author | iabdalkader <i.abdalkader@gmail.com> | 2025-03-27 13:48:42 +0100 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2025-06-26 12:10:04 +1000 |
| commit | 5c6da117995ef7f9a7396c4048d3e34f56d73ba4 (patch) | |
| tree | 12c5fe70dab2309a760021e4b5ec7899c32deff4 | |
| parent | cbe50635e85e7b7966d51fe65626304bd04f4032 (diff) | |
stm32/boards/ARDUINO_GIGA: Define additional GC blocks in SDRAM.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
| -rw-r--r-- | ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.h | 1 | ||||
| -rw-r--r-- | ports/stm32/boards/ARDUINO_GIGA/stm32h747.ld | 25 |
2 files changed, 26 insertions, 0 deletions
diff --git a/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.h b/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.h index cef45d730..44f6ce66b 100644 --- a/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.h +++ b/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.h @@ -31,6 +31,7 @@ typedef unsigned int mp_uint_t; // must be pointer size #define MICROPY_HW_ENABLE_MMCARD (0) #define MICROPY_HW_ENTER_BOOTLOADER_VIA_RESET (0) #define MICROPY_HW_TIM_IS_RESERVED(id) (id == 1) +#define MICROPY_GC_SPLIT_HEAP (1) // ROMFS config #define MICROPY_HW_ROMFS_ENABLE_EXTERNAL_QSPI (1) diff --git a/ports/stm32/boards/ARDUINO_GIGA/stm32h747.ld b/ports/stm32/boards/ARDUINO_GIGA/stm32h747.ld index e7bb950db..dceb1a748 100644 --- a/ports/stm32/boards/ARDUINO_GIGA/stm32h747.ld +++ b/ports/stm32/boards/ARDUINO_GIGA/stm32h747.ld @@ -12,6 +12,7 @@ MEMORY SRAM2 (xrw) : ORIGIN = 0x30020000, LENGTH = 128K /* SRAM2 D2 */ SRAM3 (xrw) : ORIGIN = 0x30040000, LENGTH = 32K /* SRAM3 D2 */ SRAM4 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K /* SRAM4 D3 */ + SDRAM (xrw) : ORIGIN = 0x60000000, LENGTH = 8M /* SDRAM */ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K /* Total available flash */ FLASH_BL (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* Arduino bootloader */ FLASH_FS (r) : ORIGIN = 0x08020000, LENGTH = 128K /* filesystem */ @@ -53,3 +54,27 @@ _openamp_shm_region_start = ORIGIN(SRAM4); _openamp_shm_region_end = ORIGIN(SRAM4) + LENGTH(SRAM4); INCLUDE common_blifs.ld + +SECTIONS +{ + /* GC blocks addresses and sizes */ + .gc.blocks.table (READONLY) : { + . = ALIGN(4); + _gc_blocks_table_start = .; + + LONG (ORIGIN(SRAM1)); + LONG (128K); + + LONG (ORIGIN(SDRAM) + 0M); + LONG (2M); + + LONG (ORIGIN(SDRAM) + 2M); + LONG (2M); + + LONG (ORIGIN(SDRAM) + 4M); + LONG (4M); + + _gc_blocks_table_end = .; + . = ALIGN(4); + } > FLASH_TEXT +} |