diff options
| author | NitiKaur <nitikaur102@gmail.com> | 2021-07-10 17:41:53 +0530 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2021-07-20 00:26:37 +1000 |
| commit | 6a9133a8b5fc2c19635ae0260569837aaaad2b37 (patch) | |
| tree | 40372b305335823523c96cdb85435e99428a2ddd | |
| parent | da74ef661587011132570abfe70114ca8ccd679c (diff) | |
docs/rp2: Update general section to give a brief technical overview.
| -rw-r--r-- | docs/rp2/general.rst | 26 |
1 files changed, 22 insertions, 4 deletions
diff --git a/docs/rp2/general.rst b/docs/rp2/general.rst index 9ff83a965..7042d0d25 100644 --- a/docs/rp2/general.rst +++ b/docs/rp2/general.rst @@ -10,9 +10,27 @@ the RP2040. Technical specifications and SoC datasheets ------------------------------------------- -Datasheets! +For detailed technical specifications, please refer to the `datasheets +<https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf>`_ -Short summary of tech specs! +The RP2040 microcontroller is manufactured on a 40 nm silicon process in a 7x7mm +QFN-56 SMD package. The key features include: -Description of general structure of the port (it's built on top of the APIs -provided by the Raspberry Pi SDK). +* 133 MHz dual ARM Cortex-M0+ cores (overclockable to over 400 MHz) +* 264KB SRAM in six independent banks +* No internal Flash or EEPROM memory (after reset, the bootloader loads + firmware from either the external flash memory or USB bus into internal SRAM) +* QSPI bus controller, which + supports up to 16 MB of external Flash memory +* On-chip programmable LDO togenerate core voltage +* 2 on-chip PLLs to generate USB and core clocks +* 30 GPIOpins, of which 4 can optionally be used as analog inputs + +The peripherals include: + +* 2 UARTs +* 2 SPI controllers +* 2 I2C contollers +* 16 PWM channels +* USB 1.1 controller +* 8 PIO state machines |