diff options
author | Damien George <damien.p.george@gmail.com> | 2018-09-24 17:07:15 +1000 |
---|---|---|
committer | Damien George <damien.p.george@gmail.com> | 2018-09-24 17:34:05 +1000 |
commit | 6ea6c7cc9ee20273210afd49740b26d722518a92 (patch) | |
tree | 41afd18cae4fe01e457c3591041876bf0663389b | |
parent | bc54c57590a714f334e06d645acf87d4be0e607a (diff) |
stm32/powerctrl: Don't configure clocks if already at desired frequency.
Configuring clocks is a critical operation and is best to avoid when
possible. If the clocks really need to be reset to the same values then
one can pass in a slightly higher value, eg 168000001 Hz to get 168MHz.
-rw-r--r-- | ports/stm32/powerctrl.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/ports/stm32/powerctrl.c b/ports/stm32/powerctrl.c index d05c37737..4199cf690 100644 --- a/ports/stm32/powerctrl.c +++ b/ports/stm32/powerctrl.c @@ -128,6 +128,14 @@ STATIC uint32_t calc_apb_div(uint32_t wanted_div) { } int powerctrl_set_sysclk(uint32_t sysclk, uint32_t ahb, uint32_t apb1, uint32_t apb2) { + // Return straightaway if the clocks are already at the desired frequency + if (sysclk == HAL_RCC_GetSysClockFreq() + && ahb == HAL_RCC_GetHCLKFreq() + && apb1 == HAL_RCC_GetPCLK1Freq() + && apb2 == HAL_RCC_GetPCLK2Freq()) { + return 0; + } + // Default PLL parameters that give 48MHz on PLL48CK uint32_t m = HSE_VALUE / 1000000, n = 336, p = 2, q = 7; uint32_t sysclk_source; |