diff options
| author | iabdalkader <i.abdalkader@gmail.com> | 2020-10-02 21:23:09 +0200 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2020-10-06 23:31:08 +1100 |
| commit | 7497d891a7cfade68d8c7d26b64080c56e0579e5 (patch) | |
| tree | 429253d71d60d1c0a5bc7f539abb23fd575573f0 | |
| parent | 1dc64359dab733b3c77f07d9d79589010f6fd8e0 (diff) | |
stm32/sdio: Don't change any DMA2 settings on H7 MCUs.
DMA2 clock and registers should be left in their current state in the H7
build.
| -rw-r--r-- | ports/stm32/sdio.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/ports/stm32/sdio.c b/ports/stm32/sdio.c index 79cc9c9a3..87f550e3a 100644 --- a/ports/stm32/sdio.c +++ b/ports/stm32/sdio.c @@ -76,7 +76,9 @@ void sdio_init(uint32_t irq_pri) { #endif mp_hal_delay_us(10); + #if defined(STM32F7) __HAL_RCC_DMA2_CLK_ENABLE(); // enable DMA2 peripheral + #endif NVIC_SetPriority(SDMMC1_IRQn, irq_pri); @@ -216,7 +218,9 @@ int sdio_transfer(uint32_t cmd, uint32_t arg, uint32_t *resp) { } #endif + #if defined(STM32F7) DMA2_Stream3->CR = 0; // ensure DMA is reset + #endif SDMMC1->ICR = SDMMC_STATIC_FLAGS; // clear interrupts SDMMC1->ARG = arg; SDMMC1->CMD = cmd | SDMMC_CMD_WAITRESP_0 | SDMMC_CMD_CPSMEN; @@ -296,7 +300,9 @@ int sdio_transfer_cmd53(bool write, uint32_t block_size, uint32_t arg, size_t le SDMMC1->DTIMER = 0x2000000; // about 700ms running at 48MHz SDMMC1->DLEN = (len + block_size - 1) & ~(block_size - 1); + #if defined(STM32F7) DMA2_Stream3->CR = 0; + #endif if (dma) { // prepare DMA so it's ready when the DPSM starts its transfer |