diff options
| author | Andrew Leech <andrew.leech@planetinnovation.com.au> | 2018-07-17 10:32:36 +1000 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2018-07-23 23:15:18 +1000 |
| commit | 968fa47392de2f84a968760f73df4e8e850ce578 (patch) | |
| tree | 31e83b994e1d0ff28453213928cf5c6e13c7624d | |
| parent | a1db1506a207df7b5845daaa31a3975135a6ea30 (diff) | |
stm32/sdram: On F7 MCUs enable MPU on external SDRAM.
This prevents hard-faults on non-aligned accesses.
Reference: http://www.keil.com/support/docs/3777.htm
| -rw-r--r-- | ports/stm32/sdram.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/ports/stm32/sdram.c b/ports/stm32/sdram.c index 323c66b1a..e3500a121 100644 --- a/ports/stm32/sdram.c +++ b/ports/stm32/sdram.c @@ -211,6 +211,35 @@ static void sdram_init_seq(SDRAM_HandleTypeDef */ #define REFRESH_COUNT (MICROPY_HW_SDRAM_REFRESH_RATE * 90000 / 8192 - 20) HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT); + + #if defined(STM32F7) + /* Enable MPU for the SDRAM Memory Region to allow non-aligned + accesses (hard-fault otherwise) + */ + + MPU_Region_InitTypeDef MPU_InitStruct; + + /* Disable the MPU */ + HAL_MPU_Disable(); + + /* Configure the MPU attributes for SDRAM */ + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + MPU_InitStruct.BaseAddress = SDRAM_START_ADDRESS; + MPU_InitStruct.Size = MPU_REGION_SIZE_4MB; + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + MPU_InitStruct.Number = MPU_REGION_NUMBER0; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; + MPU_InitStruct.SubRegionDisable = 0x00; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + + /* Enable the MPU */ + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); + #endif } bool __attribute__((optimize("O0"))) sdram_test(bool fast) { |