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| author | Alessandro Gatti <a.gatti@frob.it> | 2025-03-22 02:35:32 +0100 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2025-04-03 16:26:47 +1100 |
| commit | 9ab6906f50fe41b6168ce64ae792e3750fd311f9 (patch) | |
| tree | e35468f953dcfe59268df53c13a4df363e3356c4 | |
| parent | 1660faacf6c8a5837a76dfa2b12f90e87347863c (diff) | |
esp32/esp32_common.cmake: Use native gchelper for RISC-V.
This commit changes the gchelper implementation in use for RV32-based
targets (ESP32C3, ESP32C6) from the generic one written in C to the one
written in assembler that is specific to the CPU in question.
The native implementation is already exercised on most CI builds as it
is used by the QEMU port to compile and test the RV32 target.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
| -rw-r--r-- | ports/esp32/esp32_common.cmake | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/ports/esp32/esp32_common.cmake b/ports/esp32/esp32_common.cmake index f7b00900a..d026a64b0 100644 --- a/ports/esp32/esp32_common.cmake +++ b/ports/esp32/esp32_common.cmake @@ -16,7 +16,10 @@ endif() # RISC-V specific inclusions if(CONFIG_IDF_TARGET_ARCH_RISCV) - list(APPEND MICROPY_SOURCE_LIB ${MICROPY_DIR}/shared/runtime/gchelper_generic.c) + list(APPEND MICROPY_SOURCE_LIB + ${MICROPY_DIR}/shared/runtime/gchelper_native.c + ${MICROPY_DIR}/shared/runtime/gchelper_rv32i.s + ) list(APPEND IDF_COMPONENTS riscv) endif() |