diff options
| author | Damien George <damien.p.george@gmail.com> | 2018-09-24 14:51:17 +1000 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2018-09-24 14:51:17 +1000 |
| commit | 9e4812771b7425c6e6ed3377d835e381c5bbfb04 (patch) | |
| tree | 3346dff9b9c811e46a6f425013b828429a33e788 | |
| parent | dff14c740b34dfed57dcd23513516c3e14ac02de (diff) | |
stm32/powerctrl: Fix configuring APB1/APB2 frequency when AHB also set.
APB1/APB2 are derived from AHB, so if the user sets AHB!=SYSCLK then the
APB1/APB2 dividers must be computed from the new AHB.
| -rw-r--r-- | ports/stm32/powerctrl.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/ports/stm32/powerctrl.c b/ports/stm32/powerctrl.c index 594fba682..003fadfd8 100644 --- a/ports/stm32/powerctrl.c +++ b/ports/stm32/powerctrl.c @@ -110,13 +110,16 @@ set_clk: } else { RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; } + #if !defined(STM32H7) + ahb = sysclk >> AHBPrescTable[RCC_ClkInitStruct.AHBCLKDivider >> RCC_CFGR_HPRE_Pos]; + #endif if (apb1 != 0) { - RCC_ClkInitStruct.APB1CLKDivider = calc_apb_div(sysclk / apb1); + RCC_ClkInitStruct.APB1CLKDivider = calc_apb_div(ahb / apb1); } else { RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; } if (apb2 != 0) { - RCC_ClkInitStruct.APB2CLKDivider = calc_apb_div(sysclk / apb2); + RCC_ClkInitStruct.APB2CLKDivider = calc_apb_div(ahb / apb2); } else { RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; } |