diff options
| author | iabdalkader <i.abdalkader@gmail.com> | 2022-04-13 12:21:42 +0200 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2022-04-26 22:32:29 +1000 |
| commit | b28839420d84e9f7d73e37258b6ecc74d0a017d3 (patch) | |
| tree | d592c5bbe863ac7e792253f97e04f81094e42259 | |
| parent | 0e6873840b820e75da29585ed3e4b9fefdf2e90b (diff) | |
stm32/qspi: Support common flash sizes in MPU configuration.
Add MPU configuration for common flash sizes up to 256MiB.
| -rw-r--r-- | ports/stm32/qspi.c | 34 |
1 files changed, 32 insertions, 2 deletions
diff --git a/ports/stm32/qspi.c b/ports/stm32/qspi.c index 5ead66f4e..027061fd7 100644 --- a/ports/stm32/qspi.c +++ b/ports/stm32/qspi.c @@ -52,6 +52,10 @@ #define MICROPY_HW_QSPI_CS_HIGH_CYCLES 2 // nCS stays high for 2 cycles #endif +#ifndef MICROPY_HW_QSPI_MPU_REGION_SIZE +#define MICROPY_HW_QSPI_MPU_REGION_SIZE ((1 << (MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 - 3)) >> 20) +#endif + #if (MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 - 3 - 1) >= 24 #define QSPI_CMD 0xec #define QSPI_ADSIZE 3 @@ -74,11 +78,37 @@ static inline void qspi_mpu_enable_mapped(void) { // for the memory-mapped region, so 3 MPU regions are used to disable access // to everything except the valid address space, using holes in the bottom // of the regions and nesting them. - // At the moment this is hard-coded to 2MiB of QSPI address space. + // Note: Disabling a subregion (by setting its corresponding SRD bit to 1) + // means another region overlapping the disabled range matches instead. If no + // other enabled region overlaps the disabled subregion, and the access is + // unprivileged or the background region is disabled, the MPU issues a fault. uint32_t irq_state = mpu_config_start(); + #if MICROPY_HW_QSPI_MPU_REGION_SIZE > 128 + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0xFF, MPU_REGION_SIZE_256MB)); + #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 64 + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x0F, MPU_REGION_SIZE_256MB)); + #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 32 + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x03, MPU_REGION_SIZE_256MB)); + #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 16 + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB)); + #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 8 + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x0F, MPU_REGION_SIZE_32MB)); + #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 4 mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB)); - mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x0f, MPU_REGION_SIZE_32MB)); + mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x03, MPU_REGION_SIZE_32MB)); + #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 2 + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_32MB)); + #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 1 + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x0F, MPU_REGION_SIZE_32MB)); mpu_config_region(MPU_REGION_QSPI3, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_16MB)); + #else + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_32MB)); + mpu_config_region(MPU_REGION_QSPI3, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x03, MPU_REGION_SIZE_4MB)); + #endif mpu_config_end(irq_state); } |