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authorAngus Gratton <angus@redyak.com.au>2024-08-15 16:06:19 +1000
committerDamien George <damien@micropython.org>2024-08-16 14:22:51 +1000
commitb6a3aa10f5a223a43971ac22e6db7c967916d70a (patch)
treee99598acedf517a83ad261fbbcc3151e6ecbc703
parent6565b3cb34954737428f98f0306b7e3cad146482 (diff)
esp32: Remove the increased stack limit margin for ESP32-C3.
The extra limit for C3 dates from 6823514 which added C3 support. Measuring the minimum stack margins that can pass the stress tests I measured 768 bytes for ESP32-S3 and 512 bytes for ESP32-C3 on ESP-IDF V5.2.2 and similar on V5.0.4. i.e. The ESP32-C3 actually needs less stack margin not more! I think the extra margin for ESP32-C3 probably arose from: 1. Some toolchain inefficiency in the IDF V4.x RISC-V compiler codegen, that has since been improved. OR 2. The race condition that was fixed in e3955f42 where sometimes the limit wasn't set correctly at all. This seems to trigger more on C3, presumably some timing artifact, and I'd believe that some binaries might be more susceptible than others due to random factors. OR 3. Commit 6007f3e2062cc65fc8416f241c682e37eb956c11 which enabled custom NLR handling for ESP32-C3. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton <angus@redyak.com.au>
-rw-r--r--ports/esp32/mpconfigport.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/ports/esp32/mpconfigport.h b/ports/esp32/mpconfigport.h
index 723310b23..5051afb79 100644
--- a/ports/esp32/mpconfigport.h
+++ b/ports/esp32/mpconfigport.h
@@ -62,11 +62,7 @@
// Python internal features
#define MICROPY_READER_VFS (1)
#define MICROPY_ENABLE_GC (1)
-#if CONFIG_IDF_TARGET_ARCH_RISCV // RISC-V SoCs use more stack than Xtensa
-#define MICROPY_STACK_CHECK_MARGIN (2048) // This may be unnecessarily conservative
-#else
#define MICROPY_STACK_CHECK_MARGIN (1024)
-#endif
#define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1)
#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_MPZ)
#define MICROPY_ERROR_REPORTING (MICROPY_ERROR_REPORTING_NORMAL)