diff options
| author | Phil Howard <github@gadgetoid.com> | 2025-05-29 13:46:05 +0100 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2025-06-17 11:40:42 +1000 |
| commit | b725c26b4e351b71b8f72ad8e55bbbd5ccce4602 (patch) | |
| tree | 3ddabe84e673b0f24d93038027eab1380a008895 | |
| parent | c1196cadb185a6834146c358ecbf495bd556c303 (diff) | |
rp2/rp2_flash: Add MICROPY_HW_FLASH_MAX_FREQ to replace fixed max freq.
Assuming a 133MHz capable flash in 91cff8e4f10ea665c5f3f4b16d62c98d6ca22037
caused `rp2_flash_set_timing_internal` to set out of range dividers for
some boards (anything with value of 4 and flash that doesn't tolerate
higher speeds).
This affected (at least) the XIAO RP2350 board, making it non-bootable.
Since Pico SDK's `PICO_FLASH_SPI_CLKDIV` is entirely unreliable on a system
with a variable system clock (users can change it at runtime) then use it
only to work out a default `MICROPY_HW_FLASH_MAX_FREQ`.
This value can be overridden in board config.
Note that RP2350's default clock is 150MHz, RP2040's is 125MHz and it has
been certified at 200MHz so it's quite possible that
`PICO_FLASH_SPI_CLKDIV` is unreliable even at standard RP2 clocks.
(If flash timings are marginal then this can manifest as instability rather
than outright failure.)
Fixes issue #17375.
Signed-off-by: Phil Howard <github@gadgetoid.com>
| -rw-r--r-- | ports/rp2/rp2_flash.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/ports/rp2/rp2_flash.c b/ports/rp2/rp2_flash.c index a9beabf05..8b467fc6c 100644 --- a/ports/rp2/rp2_flash.c +++ b/ports/rp2/rp2_flash.c @@ -49,6 +49,14 @@ static_assert(MICROPY_HW_ROMFS_BYTES % 4096 == 0, "ROMFS size must be a multiple of 4K"); static_assert(MICROPY_HW_FLASH_STORAGE_BYTES % 4096 == 0, "Flash storage size must be a multiple of 4K"); +#ifndef MICROPY_HW_FLASH_MAX_FREQ +// Emulate Pico SDK's SYS_CLK_HZ / PICO_FLASH_SPI_CLKDIV behaviour by default. +// On RP2040 if PICO_USE_FASTEST_SUPPORTED_CLOCK is set then SYS_CLK_HZ can be +// 200MHz, potentially putting timings derived from PICO_FLASH_SPI_CLKDIV +// out of range. +#define MICROPY_HW_FLASH_MAX_FREQ (SYS_CLK_HZ / PICO_FLASH_SPI_CLKDIV) +#endif + #ifndef MICROPY_HW_FLASH_STORAGE_BASE #define MICROPY_HW_FLASH_STORAGE_BASE (PICO_FLASH_SIZE_BYTES - MICROPY_HW_FLASH_STORAGE_BYTES) #endif @@ -104,9 +112,8 @@ static bool use_multicore_lockout(void) { // and core1 locked out if relevant. static void __no_inline_not_in_flash_func(rp2_flash_set_timing_internal)(int clock_hz) { - // Use the minimum divisor assuming a 133MHz flash. - const int max_flash_freq = 133000000; - int divisor = (clock_hz + max_flash_freq - 1) / max_flash_freq; + // Use the minimum divisor based upon our target MICROPY_HW_FLASH_MAX_FREQ + int divisor = (clock_hz + MICROPY_HW_FLASH_MAX_FREQ - 1) / MICROPY_HW_FLASH_MAX_FREQ; #if PICO_RP2350 // Make sure flash is deselected - QMI doesn't appear to have a busy flag(!) |