all: Replace busses with buses.

"buses" is the widely accepted plural form of "bus".

7 files changed, 7 insertions, 7 deletions

diff --git a/docs/library/network.CC3K.rst b/docs/library/network.CC3K.rst
index 18210e2d2..41d3fb437 100644
--- a/docs/library/network.CC3K.rst
+++ b/docs/library/network.CC3K.rst
@@ -25,7 +25,7 @@ For this example to work the CC3000 module must have the following connections:
     - VBEN connected to Y4
     - IRQ connected to Y3
 
-It is possible to use other SPI busses and other pins for CS, VBEN and IRQ.
+It is possible to use other SPI buses and other pins for CS, VBEN and IRQ.
 
 Constructors
 ------------
diff --git a/docs/library/network.WIZNET5K.rst b/docs/library/network.WIZNET5K.rst
index e21e3a497..9e2c40f7f 100644
--- a/docs/library/network.WIZNET5K.rst
+++ b/docs/library/network.WIZNET5K.rst
@@ -26,7 +26,7 @@ For this example to work the WIZnet5x00 module must have the following connectio
     - nSS connected to X5
     - nRESET connected to X4
 
-It is possible to use other SPI busses and other pins for nSS and nRESET.
+It is possible to use other SPI buses and other pins for nSS and nRESET.
 
 Constructors
 ------------
diff --git a/docs/library/pyb.CAN.rst b/docs/library/pyb.CAN.rst
index 649bcda10..bcaeeba9d 100644
--- a/docs/library/pyb.CAN.rst
+++ b/docs/library/pyb.CAN.rst
@@ -30,7 +30,7 @@ Constructors
    the bus, if any).  If extra arguments are given, the bus is initialised.
    See :meth:`CAN.init` for parameters of initialisation.
 
-   The physical pins of the CAN busses are:
+   The physical pins of the CAN buses are:
 
      - ``CAN(1)`` is on ``YA``: ``(RX, TX) = (Y3, Y4) = (PB8, PB9)``
      - ``CAN(2)`` is on ``YB``: ``(RX, TX) = (Y5, Y6) = (PB12, PB13)``
diff --git a/docs/library/pyb.I2C.rst b/docs/library/pyb.I2C.rst
index 641dcb881..56b036e07 100644
--- a/docs/library/pyb.I2C.rst
+++ b/docs/library/pyb.I2C.rst
@@ -64,7 +64,7 @@ Constructors
    the bus, if any).  If extra arguments are given, the bus is initialised.
    See ``init`` for parameters of initialisation.
 
-   The physical pins of the I2C busses on Pyboards V1.0 and V1.1 are:
+   The physical pins of the I2C buses on Pyboards V1.0 and V1.1 are:
 
      - ``I2C(1)`` is on the X position: ``(SCL, SDA) = (X9, X10) = (PB6, PB7)``
      - ``I2C(2)`` is on the Y position: ``(SCL, SDA) = (Y9, Y10) = (PB10, PB11)``
diff --git a/docs/library/pyb.SPI.rst b/docs/library/pyb.SPI.rst
index 24e2ec5a7..c76b16789 100644
--- a/docs/library/pyb.SPI.rst
+++ b/docs/library/pyb.SPI.rst
@@ -36,7 +36,7 @@ Constructors
    the bus, if any).  If extra arguments are given, the bus is initialised.
    See ``init`` for parameters of initialisation.
 
-   The physical pins of the SPI busses are:
+   The physical pins of the SPI buses are:
 
      - ``SPI(1)`` is on the X position: ``(NSS, SCK, MISO, MOSI) = (X5, X6, X7, X8) = (PA4, PA5, PA6, PA7)``
      - ``SPI(2)`` is on the Y position: ``(NSS, SCK, MISO, MOSI) = (Y5, Y6, Y7, Y8) = (PB12, PB13, PB14, PB15)``
diff --git a/docs/library/pyb.UART.rst b/docs/library/pyb.UART.rst
index a1d6e5900..e1735403c 100644
--- a/docs/library/pyb.UART.rst
+++ b/docs/library/pyb.UART.rst
@@ -57,7 +57,7 @@ Constructors
    the bus, if any).  If extra arguments are given, the bus is initialised.
    See ``init`` for parameters of initialisation.
 
-   The physical pins of the UART busses on Pyboard are:
+   The physical pins of the UART buses on Pyboard are:
 
      - ``UART(4)`` is on ``XA``: ``(TX, RX) = (X1, X2) = (PA0, PA1)``
      - ``UART(1)`` is on ``XB``: ``(TX, RX) = (X9, X10) = (PB6, PB7)``
diff --git a/docs/library/pyb.rst b/docs/library/pyb.rst
index addcd20a9..321be3c52 100644
--- a/docs/library/pyb.rst
+++ b/docs/library/pyb.rst
@@ -126,7 +126,7 @@ Power related functions
     - pclk2: frequency of the APB2 bus
 
    If given any arguments then the function sets the frequency of the CPU,
-   and the busses if additional arguments are given.  Frequencies are given in
+   and the buses if additional arguments are given.  Frequencies are given in
    Hz.  Eg freq(120000000) sets sysclk (the CPU frequency) to 120MHz.  Note that
    not all values are supported and the largest supported frequency not greater
    than the given value will be selected.