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authorDaniel Campora <daniel@wipy.io>2015-09-15 19:54:58 +0200
committerDaniel Campora <daniel@wipy.io>2015-09-16 10:10:40 +0200
commit861fad581975640dc943990ee889f3dc7cd8eb5d (patch)
tree0050f8ab9150b2b85b7bd6ab42f281fd275ef528 /docs/wipy/quickref.rst
parent22b4c28f854bb2066a0d7471b50f9e00e1363239 (diff)
docs: Adapt WiPy's ADC doc and quickref to the new API.
Diffstat (limited to 'docs/wipy/quickref.rst')
-rw-r--r--docs/wipy/quickref.rst30
1 files changed, 13 insertions, 17 deletions
diff --git a/docs/wipy/quickref.rst b/docs/wipy/quickref.rst
index cad6d98b0..8376e5b40 100644
--- a/docs/wipy/quickref.rst
+++ b/docs/wipy/quickref.rst
@@ -78,8 +78,9 @@ See :ref:`pyb.ADC <pyb.ADC>`. ::
from pyb import ADC
- adc = ADC(1)
- adc.read() # read value, 0-4095
+ adc = ADC()
+ apin = adc.channel(pin='GP3')
+ apin() # read value, 0-4095
UART (serial bus)
-----------------
@@ -94,21 +95,16 @@ See :ref:`pyb.Pin <pyb.Pin>` and :ref:`pyb.UART <pyb.UART>`. ::
SPI bus
-------
-See :ref:`pyb.Pin <pyb.Pin>` and :ref:`pyb.SPI <pyb.SPI>`. ::
+See :ref:`pyb.SPI <pyb.SPI>`. ::
- from pyb import Pin, SPI
-
- # first assign CLK, MISO, MOSI, CS to the correct pins
- Pin('GP14', af=7, mode=Pin.STD) # CLK
- Pin('GP15', af=7, mode=Pin.STD) # MISO
- Pin('GP16', af=7, mode=Pin.STD) # MOSI
- Pin('GP17', af=7, mode=Pin.STD) # NSS/CS
+ from pyb SPI
# configure the SPI master @ 2MHz
- spi = SPI(1, SPI.MASTER, baudrate=200000, polarity=0, phase=0)
- spi.send('hello')
- spi.recv(5) # receive 5 bytes on the bus
- spi.send_recv('hello') # send a receive 5 bytes
+ spi = SPI(0, SPI.MASTER, baudrate=200000, polarity=0, phase=0)
+ spi.write('hello')
+ spi.read(5) # receive 5 bytes on the bus
+ rbuf = bytearray(5)
+ spi.write_readinto('hello', rbuf) # send a receive 5 bytes
I2C bus
-------
@@ -132,9 +128,9 @@ See :ref:`pyb.WDT <pyb.WDT>`. ::
from pyb import WDT
# enable the WDT with a timeout of 5s (1s is the minimum)
- wdt = WDT(5000)
- wdt.kick()
-
+ wdt = WDT(timeout=5000)
+ wdt.feed()
+
Real time clock (RTC)
---------------------