diff options
| author | Andrew Leech <andrew.leech@planetinnovation.com.au> | 2021-03-05 10:15:29 +1100 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2022-12-09 13:25:18 +1100 |
| commit | 7ee5afe8d16e4b53a2468df097e6e1a91b8127ce (patch) | |
| tree | 50c2da13c3402ffe099ce4871295615cc1248b8a /drivers/bus/softqspi.c | |
| parent | ab0258fb1ef58c7fcadd9e964921ab5adf89b443 (diff) | |
drivers/bus: Detect QSPI transfer errors and pass up to spiflash driver.
This changes the signatures of QSPI write_cmd_data, write_cmd_addr_data and
read_cmd_qaddr_qdata so they return an error code. The softqspi and stm32
hardware qspi driver are updated to follow this new signature. Also the
spiflash driver is updated to use these new return values.
Signed-off-by: Damien George <damien@micropython.org>
Diffstat (limited to 'drivers/bus/softqspi.c')
| -rw-r--r-- | drivers/bus/softqspi.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/bus/softqspi.c b/drivers/bus/softqspi.c index 71ab55976..6ede29dcd 100644 --- a/drivers/bus/softqspi.c +++ b/drivers/bus/softqspi.c @@ -158,15 +158,16 @@ STATIC void mp_soft_qspi_qwrite(mp_soft_qspi_obj_t *self, size_t len, const uint //mp_hal_pin_input(self->io1); } -STATIC void mp_soft_qspi_write_cmd_data(void *self_in, uint8_t cmd, size_t len, uint32_t data) { +STATIC int mp_soft_qspi_write_cmd_data(void *self_in, uint8_t cmd, size_t len, uint32_t data) { mp_soft_qspi_obj_t *self = (mp_soft_qspi_obj_t*)self_in; uint32_t cmd_buf = cmd | data << 8; CS_LOW(self); mp_soft_qspi_transfer(self, 1 + len, (uint8_t*)&cmd_buf, NULL); CS_HIGH(self); + return 0; } -STATIC void mp_soft_qspi_write_cmd_addr_data(void *self_in, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src) { +STATIC int mp_soft_qspi_write_cmd_addr_data(void *self_in, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src) { mp_soft_qspi_obj_t *self = (mp_soft_qspi_obj_t*)self_in; uint8_t cmd_buf[5] = {cmd}; uint8_t addr_len = mp_spi_set_addr_buff(&cmd_buf[1], addr); @@ -174,6 +175,7 @@ STATIC void mp_soft_qspi_write_cmd_addr_data(void *self_in, uint8_t cmd, uint32_ mp_soft_qspi_transfer(self, addr_len + 1, cmd_buf, NULL); mp_soft_qspi_transfer(self, len, src, NULL); CS_HIGH(self); + return 0; } STATIC uint32_t mp_soft_qspi_read_cmd(void *self_in, uint8_t cmd, size_t len) { @@ -185,7 +187,7 @@ STATIC uint32_t mp_soft_qspi_read_cmd(void *self_in, uint8_t cmd, size_t len) { return cmd_buf >> 8; } -STATIC void mp_soft_qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest) { +STATIC int mp_soft_qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest) { mp_soft_qspi_obj_t *self = (mp_soft_qspi_obj_t*)self_in; uint8_t cmd_buf[7] = {cmd}; uint8_t addr_len = mp_spi_set_addr_buff(&cmd_buf[1], addr); @@ -194,6 +196,7 @@ STATIC void mp_soft_qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32 mp_soft_qspi_qwrite(self, addr_len + 3, &cmd_buf[1]); // 3/4 addr bytes, 1 extra byte (0), 2 dummy bytes (4 dummy cycles) mp_soft_qspi_qread(self, len, dest); CS_HIGH(self); + return 0; } const mp_qspi_proto_t mp_soft_qspi_proto = { |
