diff options
| author | Damien George <damien@micropython.org> | 2021-09-16 22:16:36 +1000 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2021-09-16 22:58:47 +1000 |
| commit | 54d33b266ca337d8fb42852422cc6bf87c813e4e (patch) | |
| tree | 22ef9c7cb0b16b8e8ec5564698f47ce3815961f1 /ports/esp32/uart.c | |
| parent | b326edf68c5edb648fac4dc2a3403ee33510e179 (diff) | |
esp32: Add support for ESP32-S3 SoCs.
Thanks to Seon Rozenblum aka @UnexpectedMaker for the work.
Signed-off-by: Damien George <damien@micropython.org>
Diffstat (limited to 'ports/esp32/uart.c')
| -rw-r--r-- | ports/esp32/uart.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/ports/esp32/uart.c b/ports/esp32/uart.c index 480b364a5..58fc0c6c6 100644 --- a/ports/esp32/uart.c +++ b/ports/esp32/uart.c @@ -45,13 +45,18 @@ void uart_init(void) { // all code executed in ISR must be in IRAM, and any const data must be in DRAM STATIC void IRAM_ATTR uart_irq_handler(void *arg) { volatile uart_dev_t *uart = &UART0; + #if CONFIG_IDF_TARGET_ESP32S3 + uart->int_clr.rxfifo_full_int_clr = 1; + uart->int_clr.rxfifo_tout_int_clr = 1; + #else uart->int_clr.rxfifo_full = 1; - uart->int_clr.frm_err = 1; uart->int_clr.rxfifo_tout = 1; + uart->int_clr.frm_err = 1; + #endif while (uart->status.rxfifo_cnt) { #if CONFIG_IDF_TARGET_ESP32 uint8_t c = uart->fifo.rw_byte; - #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 + #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 uint8_t c = READ_PERI_REG(UART_FIFO_AHB_REG(0)); // UART0 #endif if (c == mp_interrupt_char) { |