summaryrefslogtreecommitdiff
path: root/ports/esp32/uart.c
diff options
context:
space:
mode:
authorDamien George <damien@micropython.org>2021-07-18 12:11:21 +1000
committerDamien George <damien@micropython.org>2021-07-18 23:58:24 +1000
commit6823514845c13339efb0e3ff716d2cfa72297d72 (patch)
treed9133f52d52f7bea652ef2d792e9aba07e511b4c /ports/esp32/uart.c
parent59dbbe9be7f91f53f60803559db88cfb75cf1c2a (diff)
esp32: Add initial support for ESP32C3 SoCs.
Supported features for this SoC are: - UART REPL, filesystem - Pin, ADC, PWM, SoftI2C, SoftSPI, Timer, RTC - OneWire, DHT, NeoPixel - RMT - WiFi, Bluetooth Signed-off-by: Damien George <damien@micropython.org>
Diffstat (limited to 'ports/esp32/uart.c')
-rw-r--r--ports/esp32/uart.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/ports/esp32/uart.c b/ports/esp32/uart.c
index c4fe41eaf..480b364a5 100644
--- a/ports/esp32/uart.c
+++ b/ports/esp32/uart.c
@@ -51,7 +51,7 @@ STATIC void IRAM_ATTR uart_irq_handler(void *arg) {
while (uart->status.rxfifo_cnt) {
#if CONFIG_IDF_TARGET_ESP32
uint8_t c = uart->fifo.rw_byte;
- #elif CONFIG_IDF_TARGET_ESP32S2
+ #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2
uint8_t c = READ_PERI_REG(UART_FIFO_AHB_REG(0)); // UART0
#endif
if (c == mp_interrupt_char) {