diff options
| author | patrick <patrick@thinktransit.com.au> | 2023-05-14 17:36:56 +1000 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2023-05-22 10:11:24 +1000 |
| commit | a802f719085d52f61bd08908de298f92d226be0b (patch) | |
| tree | 629cd0507dacad32f9c3faad30ef0355d93fa53a /ports/esp32/uart.c | |
| parent | 05e143dbddbde07e4f31a0376b8869bcf9fb1939 (diff) | |
esp32/uart: Use xtal as UART clock source on S3 and C3.
Change UART clock source on S3/C3 so the UART can operate when CPU
frequency is below 80MHz. This allows the UART to remain operational when
using Dynamic Frequency Scaling (DFS).
Signed-off-by: Patrick Joy <patrick@joytech.com.au>
Diffstat (limited to 'ports/esp32/uart.c')
| -rw-r--r-- | ports/esp32/uart.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/ports/esp32/uart.c b/ports/esp32/uart.c index f6493dc79..e871ca1d7 100644 --- a/ports/esp32/uart.c +++ b/ports/esp32/uart.c @@ -46,6 +46,10 @@ void uart_stdout_init(void) { .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, .rx_flow_ctrl_thresh = 0 }; + #if SOC_UART_SUPPORT_XTAL_CLK + // works independently of APB frequency + uartcfg.source_clk = UART_SCLK_XTAL; // ESP32C3, ESP32S3 + #endif uart_param_config(MICROPY_HW_UART_REPL, &uartcfg); const uint32_t rxbuf = 129; // IDF requires > 128 min |