stm32: Add initial support for H5 MCUs.

This commit adds initial support for STM32H5xx MCUs.  The following
features have been confirmed to be working on an STM32H573:
- UART over REPL and USB CDC
- USB CDC and MSC
- internal flash filesystem
- machine.Pin
- machine.SPI transfers with DMA
- machine.ADC
- machine.RTC
- pyb.LED
- pyb.Switch
- pyb.rng
- mboot

Signed-off-by: Damien George <damien@micropython.org>

1 files changed, 20 insertions, 14 deletions

diff --git a/ports/stm32/modmachine.c b/ports/stm32/modmachine.c
index 25fc66eb9..1869b984d 100644
--- a/ports/stm32/modmachine.c
+++ b/ports/stm32/modmachine.c
@@ -58,23 +58,20 @@
 #include "uart.h"
 #include "wdt.h"
 
-#if defined(STM32L0)
-// L0 does not have a BOR, so use POR instead
-#define RCC_CSR_BORRSTF RCC_CSR_PORRSTF
-#endif
-
-#if defined(STM32G4) || defined(STM32L4) || defined(STM32WB) || defined(STM32WL)
-// L4 does not have a POR, so use BOR instead
-#define RCC_CSR_PORRSTF RCC_CSR_BORRSTF
-#endif
-
 #if defined(STM32G0)
 // G0 has BOR and POR combined
 #define RCC_CSR_BORRSTF RCC_CSR_PWRRSTF
 #define RCC_CSR_PORRSTF RCC_CSR_PWRRSTF
 #endif
 
-#if defined(STM32H7)
+#if defined(STM32H5)
+#define RCC_SR          RSR
+#define RCC_SR_IWDGRSTF RCC_RSR_IWDGRSTF
+#define RCC_SR_WWDGRSTF RCC_RSR_WWDGRSTF
+#define RCC_SR_BORRSTF  RCC_RSR_BORRSTF
+#define RCC_SR_PINRSTF  RCC_RSR_PINRSTF
+#define RCC_SR_RMVF     RCC_RSR_RMVF
+#elif defined(STM32H7)
 #define RCC_SR          RSR
 #define RCC_SR_IWDGRSTF RCC_RSR_IWDG1RSTF
 #define RCC_SR_WWDGRSTF RCC_RSR_WWDG1RSTF
@@ -86,8 +83,12 @@
 #define RCC_SR          CSR
 #define RCC_SR_IWDGRSTF RCC_CSR_IWDGRSTF
 #define RCC_SR_WWDGRSTF RCC_CSR_WWDGRSTF
+#if defined(RCC_CSR_PORRSTF)
 #define RCC_SR_PORRSTF  RCC_CSR_PORRSTF
+#endif
+#if defined(RCC_CSR_BORRSTF)
 #define RCC_SR_BORRSTF  RCC_CSR_BORRSTF
+#endif
 #define RCC_SR_PINRSTF  RCC_CSR_PINRSTF
 #define RCC_SR_RMVF     RCC_CSR_RMVF
 #endif
@@ -137,9 +138,12 @@ void machine_init(void) {
         uint32_t state = RCC->RCC_SR;
         if (state & RCC_SR_IWDGRSTF || state & RCC_SR_WWDGRSTF) {
             reset_cause = PYB_RESET_WDT;
-        } else if (state & RCC_SR_PORRSTF
-                   #if !defined(STM32F0) && !defined(STM32F412Zx) && !defined(STM32L1)
-                   || state & RCC_SR_BORRSTF
+        } else if (0
+                   #if defined(RCC_SR_PORRSTF)
+                   || (state & RCC_SR_PORRSTF)
+                   #endif
+                   #if defined(RCC_SR_BORRSTF)
+                   || (state & RCC_SR_BORRSTF)
                    #endif
                    ) {
             reset_cause = PYB_RESET_POWER_ON;
@@ -286,6 +290,8 @@ NORETURN mp_obj_t machine_bootloader(size_t n_args, const mp_obj_t *args) {
 
     #if defined(STM32F7) || defined(STM32H7)
     powerctrl_enter_bootloader(0, 0x1ff00000);
+    #elif defined(STM32H5)
+    powerctrl_enter_bootloader(0, 0x0bf97000);
     #else
     powerctrl_enter_bootloader(0, 0x00000000);
     #endif