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authorDamien George <damien.p.george@gmail.com>2020-01-30 16:29:45 +1100
committerDamien George <damien.p.george@gmail.com>2020-01-30 16:29:45 +1100
commit29b84ea79856e8ba512ef7ea70b265e9d86e45b6 (patch)
tree94aea6ee657054cad322e6d1cfe21f31ad13eb39 /ports/stm32/powerctrl.c
parentc96a2f636b48b065e8404af6d67fbae5986fd34a (diff)
stm32/powerctrl: Disable HSI if not needed to save a bit of power.
Diffstat (limited to 'ports/stm32/powerctrl.c')
-rw-r--r--ports/stm32/powerctrl.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/ports/stm32/powerctrl.c b/ports/stm32/powerctrl.c
index 1d1792c38..d1ac85f0e 100644
--- a/ports/stm32/powerctrl.c
+++ b/ports/stm32/powerctrl.c
@@ -44,6 +44,13 @@
extern uint32_t _estack[];
#define BL_STATE ((uint32_t*)&_estack)
+static inline void powerctrl_disable_hsi_if_unused(void) {
+ #if !MICROPY_HW_CLK_USE_HSI && (defined(STM32F4) || defined(STM32F7) || defined(STM32H7))
+ // Disable HSI if it's not used to save a little bit of power
+ __HAL_RCC_HSI_DISABLE();
+ #endif
+}
+
NORETURN void powerctrl_mcu_reset(void) {
BL_STATE[1] = 1; // invalidate bootloader address
#if __DCACHE_PRESENT == 1
@@ -155,6 +162,8 @@ int powerctrl_rcc_clock_config_pll(RCC_ClkInitTypeDef *rcc_init, uint32_t sysclk
return -MP_EIO;
}
+ powerctrl_disable_hsi_if_unused();
+
return 0;
}
@@ -390,6 +399,8 @@ void powerctrl_enter_stop_mode(void) {
}
#endif
+ powerctrl_disable_hsi_if_unused();
+
#if defined(STM32F7)
if (RCC->DCKCFGR2 & RCC_DCKCFGR2_CK48MSEL) {
// Enable PLLSAI if it is selected as 48MHz source