diff options
| author | Damien George <damien.p.george@gmail.com> | 2020-01-29 16:49:13 +1100 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2020-01-29 16:49:13 +1100 |
| commit | a542c6d7e0340e5ff5364426131bdbd69a64e746 (patch) | |
| tree | b4f09a20a9692ae6031479517fdd9f2b3d861152 /ports/stm32/powerctrl.c | |
| parent | c3095b37e96aeb69564f53d30a12242ab42bbd02 (diff) | |
stm32/powerctrl: For F7, allow PLLM!=HSE when setting PLLSAI to 48MHz.
PLLM is shared among all PLL blocks on F7 MCUs, and this calculation to
configure PLLSAI to have 48MHz on the P output previously assumed that PLLM
is equal to HSE (eg PLLM=25 for HSE=25MHz). This commit relaxes this
assumption to allow other values of PLLM.
Diffstat (limited to 'ports/stm32/powerctrl.c')
| -rw-r--r-- | ports/stm32/powerctrl.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/ports/stm32/powerctrl.c b/ports/stm32/powerctrl.c index dfd9e8262..1d1792c38 100644 --- a/ports/stm32/powerctrl.c +++ b/ports/stm32/powerctrl.c @@ -94,9 +94,11 @@ int powerctrl_rcc_clock_config_pll(RCC_ClkInitTypeDef *rcc_init, uint32_t sysclk if (need_pllsai) { // Configure PLLSAI at 48MHz for those peripherals that need this freq - const uint32_t pllsain = 192; + // (calculation assumes it can get an integral value of PLLSAIN) + const uint32_t pllm = (RCC->PLLCFGR >> RCC_PLLCFGR_PLLM_Pos) & 0x3f; const uint32_t pllsaip = 4; const uint32_t pllsaiq = 2; + const uint32_t pllsain = 48 * pllsaip * pllm / (HSE_VALUE / 1000000); RCC->PLLSAICFGR = pllsaiq << RCC_PLLSAICFGR_PLLSAIQ_Pos | (pllsaip / 2 - 1) << RCC_PLLSAICFGR_PLLSAIP_Pos | pllsain << RCC_PLLSAICFGR_PLLSAIN_Pos; |