diff options
| author | Jim Mussared <jim.mussared@gmail.com> | 2020-08-28 14:59:24 +1000 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2020-09-08 23:53:12 +1000 |
| commit | 0f28020a68b190d973dc5ef2049c76eb28acddee (patch) | |
| tree | 2b0465399249eac169a1de3146d00e9e760a466a /ports/stm32/powerctrlboot.c | |
| parent | 9c9cc7a02f6f998d0141989040d68219d6ad0625 (diff) | |
stm32/powerctrlboot: Acquire HSEM5 on STM32WB during SystemClock_Config.
This is required to allow using WS firmware newer than 1.1.1 concurrently
with USB (e.g. USB VCP). It prevents CPU2 from modifying the CLK48 config
on boot.
Tested on WS=1.8 FUS=1.1.
See AN5289 and https://github.com/micropython/micropython/issues/6316
Diffstat (limited to 'ports/stm32/powerctrlboot.c')
| -rw-r--r-- | ports/stm32/powerctrlboot.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/ports/stm32/powerctrlboot.c b/ports/stm32/powerctrlboot.c index 206b19b75..880e43e04 100644 --- a/ports/stm32/powerctrlboot.c +++ b/ports/stm32/powerctrlboot.c @@ -154,12 +154,23 @@ void SystemClock_Config(void) { #elif defined(STM32WB) +#include "stm32wbxx_ll_hsem.h" + +// This semaphore protected access to the CLK48 configuration. +// CPU1 should hold this semaphore while the USB peripheral is in use. +// See AN5289 and https://github.com/micropython/micropython/issues/6316. +#define CLK48_SEMID (5) + void SystemClock_Config(void) { // Enable the 32MHz external oscillator RCC->CR |= RCC_CR_HSEON; while (!(RCC->CR & RCC_CR_HSERDY)) { } + // Prevent CPU2 from disabling CLK48. + while (LL_HSEM_1StepLock(HSEM, CLK48_SEMID)) { + } + // Use HSE and the PLL to get a 64MHz SYSCLK #define PLLM (HSE_VALUE / 8000000) // VCO input is 8MHz #define PLLN (24) // 24*8MHz = 192MHz |