diff options
| author | Rene Straub <rene@see5.ch> | 2023-10-21 15:03:53 +0200 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2023-11-03 17:14:05 +1100 |
| commit | 47ea831c0e741722a9e7a94bb453947cff5f66d8 (patch) | |
| tree | ee0284496b4a2a8031d3586a2ff908b6d2834337 /ports/stm32/powerctrlboot.c | |
| parent | e5014a4d7953808355c1882a65d6d7824cdd0001 (diff) | |
stm32: Add STM32H5 support for sleep mode.
Update rtc, machine and powerctrl drivers to support STM32H5 sleep
modes. This makes RTC alarm wakeup working from lightsleep() and
deepsleep().
Changes:
- Determine start reason for machine.reset_cause() in modmachine.c.
- Add proper interrupt clear code in rtc.c.
- Add wakeup functionality in powerctrl_enter_stop_mode(). Remember
and restore voltage scaling level. Restart HSI48 if it was on before
entering sleep mode.
- Clear DBGMCU_CR in SystemClock_Config() as for other variants.
Otherwise debug flags prevent entering sleep mode.
Implementation Notes:
- rtc.c: EXTI_RTSTR1 bits are not present for H5. Code sequence from
G0/G4/L4/WB/WL would be invalid. RTSTR is only defined for external
(GPIO) interrupts. Maybe this is also true for other STM32 variants.
- powerctrl_enter_stop_mode() uses complicated, nested conditionals
to select STM32 variants. To make code slightly better readable,
comment have been added. A non-nested, #if/#elif sequence would
make the code more readable. I leave this to the original authors.
Signed-off-by: Rene Straub <rene@see5.ch>
Diffstat (limited to 'ports/stm32/powerctrlboot.c')
| -rw-r--r-- | ports/stm32/powerctrlboot.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/ports/stm32/powerctrlboot.c b/ports/stm32/powerctrlboot.c index c7802a558..31dae527c 100644 --- a/ports/stm32/powerctrlboot.c +++ b/ports/stm32/powerctrlboot.c @@ -298,6 +298,10 @@ void SystemClock_Config(void) { LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL3Q); #endif + + #ifdef NDEBUG + DBGMCU->CR = 0; + #endif } #elif defined(STM32L0) |
